python_code
stringlengths 0
1.8M
| repo_name
stringclasses 7
values | file_path
stringlengths 5
99
|
|---|---|---|
// SPDX-License-Identifier: GPL-2.0
//
// PCM3060 SPI driver
//
// Copyright (C) 2018 Kirill Marinushkin <[email protected]>
#include <linux/module.h>
#include <linux/spi/spi.h>
#include <sound/soc.h>
#include "pcm3060.h"
static int pcm3060_spi_probe(struct spi_device *spi)
{
struct pcm3060_priv *priv;
priv = devm_kzalloc(&spi->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
spi_set_drvdata(spi, priv);
priv->regmap = devm_regmap_init_spi(spi, &pcm3060_regmap);
if (IS_ERR(priv->regmap))
return PTR_ERR(priv->regmap);
return pcm3060_probe(&spi->dev);
}
static const struct spi_device_id pcm3060_spi_id[] = {
{ .name = "pcm3060" },
{ },
};
MODULE_DEVICE_TABLE(spi, pcm3060_spi_id);
#ifdef CONFIG_OF
static const struct of_device_id pcm3060_of_match[] = {
{ .compatible = "ti,pcm3060" },
{ },
};
MODULE_DEVICE_TABLE(of, pcm3060_of_match);
#endif /* CONFIG_OF */
static struct spi_driver pcm3060_spi_driver = {
.driver = {
.name = "pcm3060",
#ifdef CONFIG_OF
.of_match_table = pcm3060_of_match,
#endif /* CONFIG_OF */
},
.id_table = pcm3060_spi_id,
.probe = pcm3060_spi_probe,
};
module_spi_driver(pcm3060_spi_driver);
MODULE_DESCRIPTION("PCM3060 SPI driver");
MODULE_AUTHOR("Kirill Marinushkin <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/pcm3060-spi.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* nau8810.c -- NAU8810 ALSA Soc Audio driver
*
* Copyright 2016 Nuvoton Technology Corp.
*
* Author: David Lin <[email protected]>
*
* Based on WM8974.c
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "nau8810.h"
#define NAU_PLL_FREQ_MAX 100000000
#define NAU_PLL_FREQ_MIN 90000000
#define NAU_PLL_REF_MAX 33000000
#define NAU_PLL_REF_MIN 8000000
#define NAU_PLL_OPTOP_MIN 6
static const int nau8810_mclk_scaler[] = { 10, 15, 20, 30, 40, 60, 80, 120 };
static const struct reg_default nau8810_reg_defaults[] = {
{ NAU8810_REG_POWER1, 0x0000 },
{ NAU8810_REG_POWER2, 0x0000 },
{ NAU8810_REG_POWER3, 0x0000 },
{ NAU8810_REG_IFACE, 0x0050 },
{ NAU8810_REG_COMP, 0x0000 },
{ NAU8810_REG_CLOCK, 0x0140 },
{ NAU8810_REG_SMPLR, 0x0000 },
{ NAU8810_REG_DAC, 0x0000 },
{ NAU8810_REG_DACGAIN, 0x00FF },
{ NAU8810_REG_ADC, 0x0100 },
{ NAU8810_REG_ADCGAIN, 0x00FF },
{ NAU8810_REG_EQ1, 0x012C },
{ NAU8810_REG_EQ2, 0x002C },
{ NAU8810_REG_EQ3, 0x002C },
{ NAU8810_REG_EQ4, 0x002C },
{ NAU8810_REG_EQ5, 0x002C },
{ NAU8810_REG_DACLIM1, 0x0032 },
{ NAU8810_REG_DACLIM2, 0x0000 },
{ NAU8810_REG_NOTCH1, 0x0000 },
{ NAU8810_REG_NOTCH2, 0x0000 },
{ NAU8810_REG_NOTCH3, 0x0000 },
{ NAU8810_REG_NOTCH4, 0x0000 },
{ NAU8810_REG_ALC1, 0x0038 },
{ NAU8810_REG_ALC2, 0x000B },
{ NAU8810_REG_ALC3, 0x0032 },
{ NAU8810_REG_NOISEGATE, 0x0000 },
{ NAU8810_REG_PLLN, 0x0008 },
{ NAU8810_REG_PLLK1, 0x000C },
{ NAU8810_REG_PLLK2, 0x0093 },
{ NAU8810_REG_PLLK3, 0x00E9 },
{ NAU8810_REG_ATTEN, 0x0000 },
{ NAU8810_REG_INPUT_SIGNAL, 0x0003 },
{ NAU8810_REG_PGAGAIN, 0x0010 },
{ NAU8810_REG_ADCBOOST, 0x0100 },
{ NAU8810_REG_OUTPUT, 0x0002 },
{ NAU8810_REG_SPKMIX, 0x0001 },
{ NAU8810_REG_SPKGAIN, 0x0039 },
{ NAU8810_REG_MONOMIX, 0x0001 },
{ NAU8810_REG_POWER4, 0x0000 },
{ NAU8810_REG_TSLOTCTL1, 0x0000 },
{ NAU8810_REG_TSLOTCTL2, 0x0020 },
{ NAU8810_REG_DEVICE_REVID, 0x0000 },
{ NAU8810_REG_I2C_DEVICEID, 0x001A },
{ NAU8810_REG_ADDITIONID, 0x00CA },
{ NAU8810_REG_RESERVE, 0x0124 },
{ NAU8810_REG_OUTCTL, 0x0001 },
{ NAU8810_REG_ALC1ENHAN1, 0x0010 },
{ NAU8810_REG_ALC1ENHAN2, 0x0000 },
{ NAU8810_REG_MISCCTL, 0x0000 },
{ NAU8810_REG_OUTTIEOFF, 0x0000 },
{ NAU8810_REG_AGCP2POUT, 0x0000 },
{ NAU8810_REG_AGCPOUT, 0x0000 },
{ NAU8810_REG_AMTCTL, 0x0000 },
{ NAU8810_REG_OUTTIEOFFMAN, 0x0000 },
};
static bool nau8810_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case NAU8810_REG_RESET ... NAU8810_REG_SMPLR:
case NAU8810_REG_DAC ... NAU8810_REG_DACGAIN:
case NAU8810_REG_ADC ... NAU8810_REG_ADCGAIN:
case NAU8810_REG_EQ1 ... NAU8810_REG_EQ5:
case NAU8810_REG_DACLIM1 ... NAU8810_REG_DACLIM2:
case NAU8810_REG_NOTCH1 ... NAU8810_REG_NOTCH4:
case NAU8810_REG_ALC1 ... NAU8810_REG_ATTEN:
case NAU8810_REG_INPUT_SIGNAL ... NAU8810_REG_PGAGAIN:
case NAU8810_REG_ADCBOOST:
case NAU8810_REG_OUTPUT ... NAU8810_REG_SPKMIX:
case NAU8810_REG_SPKGAIN:
case NAU8810_REG_MONOMIX:
case NAU8810_REG_POWER4 ... NAU8810_REG_TSLOTCTL2:
case NAU8810_REG_DEVICE_REVID ... NAU8810_REG_RESERVE:
case NAU8810_REG_OUTCTL ... NAU8810_REG_ALC1ENHAN2:
case NAU8810_REG_MISCCTL:
case NAU8810_REG_OUTTIEOFF ... NAU8810_REG_OUTTIEOFFMAN:
return true;
default:
return false;
}
}
static bool nau8810_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case NAU8810_REG_RESET ... NAU8810_REG_SMPLR:
case NAU8810_REG_DAC ... NAU8810_REG_DACGAIN:
case NAU8810_REG_ADC ... NAU8810_REG_ADCGAIN:
case NAU8810_REG_EQ1 ... NAU8810_REG_EQ5:
case NAU8810_REG_DACLIM1 ... NAU8810_REG_DACLIM2:
case NAU8810_REG_NOTCH1 ... NAU8810_REG_NOTCH4:
case NAU8810_REG_ALC1 ... NAU8810_REG_ATTEN:
case NAU8810_REG_INPUT_SIGNAL ... NAU8810_REG_PGAGAIN:
case NAU8810_REG_ADCBOOST:
case NAU8810_REG_OUTPUT ... NAU8810_REG_SPKMIX:
case NAU8810_REG_SPKGAIN:
case NAU8810_REG_MONOMIX:
case NAU8810_REG_POWER4 ... NAU8810_REG_TSLOTCTL2:
case NAU8810_REG_OUTCTL ... NAU8810_REG_ALC1ENHAN2:
case NAU8810_REG_MISCCTL:
case NAU8810_REG_OUTTIEOFF ... NAU8810_REG_OUTTIEOFFMAN:
return true;
default:
return false;
}
}
static bool nau8810_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case NAU8810_REG_RESET:
case NAU8810_REG_DEVICE_REVID ... NAU8810_REG_RESERVE:
return true;
default:
return false;
}
}
/* The EQ parameters get function is to get the 5 band equalizer control.
* The regmap raw read can't work here because regmap doesn't provide
* value format for value width of 9 bits. Therefore, the driver reads data
* from cache and makes value format according to the endianness of
* bytes type control element.
*/
static int nau8810_eq_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
struct soc_bytes_ext *params = (void *)kcontrol->private_value;
int i, reg, reg_val;
u16 *val;
val = (u16 *)ucontrol->value.bytes.data;
reg = NAU8810_REG_EQ1;
for (i = 0; i < params->max / sizeof(u16); i++) {
regmap_read(nau8810->regmap, reg + i, ®_val);
/* conversion of 16-bit integers between native CPU format
* and big endian format
*/
reg_val = cpu_to_be16(reg_val);
memcpy(val + i, ®_val, sizeof(reg_val));
}
return 0;
}
/* The EQ parameters put function is to make configuration of 5 band equalizer
* control. These configuration includes central frequency, equalizer gain,
* cut-off frequency, bandwidth control, and equalizer path.
* The regmap raw write can't work here because regmap doesn't provide
* register and value format for register with address 7 bits and value 9 bits.
* Therefore, the driver makes value format according to the endianness of
* bytes type control element and writes data to codec.
*/
static int nau8810_eq_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
struct soc_bytes_ext *params = (void *)kcontrol->private_value;
void *data;
u16 *val, value;
int i, reg, ret;
data = kmemdup(ucontrol->value.bytes.data,
params->max, GFP_KERNEL | GFP_DMA);
if (!data)
return -ENOMEM;
val = (u16 *)data;
reg = NAU8810_REG_EQ1;
for (i = 0; i < params->max / sizeof(u16); i++) {
/* conversion of 16-bit integers between native CPU format
* and big endian format
*/
value = be16_to_cpu(*(val + i));
ret = regmap_write(nau8810->regmap, reg + i, value);
if (ret) {
dev_err(component->dev, "EQ configuration fail, register: %x ret: %d\n",
reg + i, ret);
kfree(data);
return ret;
}
}
kfree(data);
return 0;
}
static const char * const nau8810_companding[] = {
"Off", "NC", "u-law", "A-law" };
static const struct soc_enum nau8810_companding_adc_enum =
SOC_ENUM_SINGLE(NAU8810_REG_COMP, NAU8810_ADCCM_SFT,
ARRAY_SIZE(nau8810_companding), nau8810_companding);
static const struct soc_enum nau8810_companding_dac_enum =
SOC_ENUM_SINGLE(NAU8810_REG_COMP, NAU8810_DACCM_SFT,
ARRAY_SIZE(nau8810_companding), nau8810_companding);
static const char * const nau8810_deemp[] = {
"None", "32kHz", "44.1kHz", "48kHz" };
static const struct soc_enum nau8810_deemp_enum =
SOC_ENUM_SINGLE(NAU8810_REG_DAC, NAU8810_DEEMP_SFT,
ARRAY_SIZE(nau8810_deemp), nau8810_deemp);
static const char * const nau8810_eqmode[] = {"Capture", "Playback" };
static const struct soc_enum nau8810_eqmode_enum =
SOC_ENUM_SINGLE(NAU8810_REG_EQ1, NAU8810_EQM_SFT,
ARRAY_SIZE(nau8810_eqmode), nau8810_eqmode);
static const char * const nau8810_alc[] = {"Normal", "Limiter" };
static const struct soc_enum nau8810_alc_enum =
SOC_ENUM_SINGLE(NAU8810_REG_ALC3, NAU8810_ALCM_SFT,
ARRAY_SIZE(nau8810_alc), nau8810_alc);
static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0);
static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0);
static const struct snd_kcontrol_new nau8810_snd_controls[] = {
SOC_ENUM("ADC Companding", nau8810_companding_adc_enum),
SOC_ENUM("DAC Companding", nau8810_companding_dac_enum),
SOC_ENUM("DAC De-emphasis", nau8810_deemp_enum),
SOC_ENUM("EQ Function", nau8810_eqmode_enum),
SND_SOC_BYTES_EXT("EQ Parameters", 10,
nau8810_eq_get, nau8810_eq_put),
SOC_SINGLE("DAC Inversion Switch", NAU8810_REG_DAC,
NAU8810_DACPL_SFT, 1, 0),
SOC_SINGLE_TLV("Playback Volume", NAU8810_REG_DACGAIN,
NAU8810_DACGAIN_SFT, 0xff, 0, digital_tlv),
SOC_SINGLE("High Pass Filter Switch", NAU8810_REG_ADC,
NAU8810_HPFEN_SFT, 1, 0),
SOC_SINGLE("High Pass Cut Off", NAU8810_REG_ADC,
NAU8810_HPF_SFT, 0x7, 0),
SOC_SINGLE("ADC Inversion Switch", NAU8810_REG_ADC,
NAU8810_ADCPL_SFT, 1, 0),
SOC_SINGLE_TLV("Capture Volume", NAU8810_REG_ADCGAIN,
NAU8810_ADCGAIN_SFT, 0xff, 0, digital_tlv),
SOC_SINGLE_TLV("EQ1 Volume", NAU8810_REG_EQ1,
NAU8810_EQ1GC_SFT, 0x18, 1, eq_tlv),
SOC_SINGLE_TLV("EQ2 Volume", NAU8810_REG_EQ2,
NAU8810_EQ2GC_SFT, 0x18, 1, eq_tlv),
SOC_SINGLE_TLV("EQ3 Volume", NAU8810_REG_EQ3,
NAU8810_EQ3GC_SFT, 0x18, 1, eq_tlv),
SOC_SINGLE_TLV("EQ4 Volume", NAU8810_REG_EQ4,
NAU8810_EQ4GC_SFT, 0x18, 1, eq_tlv),
SOC_SINGLE_TLV("EQ5 Volume", NAU8810_REG_EQ5,
NAU8810_EQ5GC_SFT, 0x18, 1, eq_tlv),
SOC_SINGLE("DAC Limiter Switch", NAU8810_REG_DACLIM1,
NAU8810_DACLIMEN_SFT, 1, 0),
SOC_SINGLE("DAC Limiter Decay", NAU8810_REG_DACLIM1,
NAU8810_DACLIMDCY_SFT, 0xf, 0),
SOC_SINGLE("DAC Limiter Attack", NAU8810_REG_DACLIM1,
NAU8810_DACLIMATK_SFT, 0xf, 0),
SOC_SINGLE("DAC Limiter Threshold", NAU8810_REG_DACLIM2,
NAU8810_DACLIMTHL_SFT, 0x7, 0),
SOC_SINGLE("DAC Limiter Boost", NAU8810_REG_DACLIM2,
NAU8810_DACLIMBST_SFT, 0xf, 0),
SOC_ENUM("ALC Mode", nau8810_alc_enum),
SOC_SINGLE("ALC Enable Switch", NAU8810_REG_ALC1,
NAU8810_ALCEN_SFT, 1, 0),
SOC_SINGLE("ALC Max Volume", NAU8810_REG_ALC1,
NAU8810_ALCMXGAIN_SFT, 0x7, 0),
SOC_SINGLE("ALC Min Volume", NAU8810_REG_ALC1,
NAU8810_ALCMINGAIN_SFT, 0x7, 0),
SOC_SINGLE("ALC ZC Switch", NAU8810_REG_ALC2,
NAU8810_ALCZC_SFT, 1, 0),
SOC_SINGLE("ALC Hold", NAU8810_REG_ALC2,
NAU8810_ALCHT_SFT, 0xf, 0),
SOC_SINGLE("ALC Target", NAU8810_REG_ALC2,
NAU8810_ALCSL_SFT, 0xf, 0),
SOC_SINGLE("ALC Decay", NAU8810_REG_ALC3,
NAU8810_ALCDCY_SFT, 0xf, 0),
SOC_SINGLE("ALC Attack", NAU8810_REG_ALC3,
NAU8810_ALCATK_SFT, 0xf, 0),
SOC_SINGLE("ALC Noise Gate Switch", NAU8810_REG_NOISEGATE,
NAU8810_ALCNEN_SFT, 1, 0),
SOC_SINGLE("ALC Noise Gate Threshold", NAU8810_REG_NOISEGATE,
NAU8810_ALCNTH_SFT, 0x7, 0),
SOC_SINGLE("PGA ZC Switch", NAU8810_REG_PGAGAIN,
NAU8810_PGAZC_SFT, 1, 0),
SOC_SINGLE_TLV("PGA Volume", NAU8810_REG_PGAGAIN,
NAU8810_PGAGAIN_SFT, 0x3f, 0, inpga_tlv),
SOC_SINGLE("Speaker ZC Switch", NAU8810_REG_SPKGAIN,
NAU8810_SPKZC_SFT, 1, 0),
SOC_SINGLE("Speaker Mute Switch", NAU8810_REG_SPKGAIN,
NAU8810_SPKMT_SFT, 1, 0),
SOC_SINGLE_TLV("Speaker Volume", NAU8810_REG_SPKGAIN,
NAU8810_SPKGAIN_SFT, 0x3f, 0, spk_tlv),
SOC_SINGLE("Capture Boost(+20dB)", NAU8810_REG_ADCBOOST,
NAU8810_PGABST_SFT, 1, 0),
SOC_SINGLE("Mono Mute Switch", NAU8810_REG_MONOMIX,
NAU8810_MOUTMXMT_SFT, 1, 0),
SOC_SINGLE("DAC Oversampling Rate(128x) Switch", NAU8810_REG_DAC,
NAU8810_DACOS_SFT, 1, 0),
SOC_SINGLE("ADC Oversampling Rate(128x) Switch", NAU8810_REG_ADC,
NAU8810_ADCOS_SFT, 1, 0),
};
/* Speaker Output Mixer */
static const struct snd_kcontrol_new nau8810_speaker_mixer_controls[] = {
SOC_DAPM_SINGLE("AUX Bypass Switch", NAU8810_REG_SPKMIX,
NAU8810_AUXSPK_SFT, 1, 0),
SOC_DAPM_SINGLE("Line Bypass Switch", NAU8810_REG_SPKMIX,
NAU8810_BYPSPK_SFT, 1, 0),
SOC_DAPM_SINGLE("PCM Playback Switch", NAU8810_REG_SPKMIX,
NAU8810_DACSPK_SFT, 1, 0),
};
/* Mono Output Mixer */
static const struct snd_kcontrol_new nau8810_mono_mixer_controls[] = {
SOC_DAPM_SINGLE("AUX Bypass Switch", NAU8810_REG_MONOMIX,
NAU8810_AUXMOUT_SFT, 1, 0),
SOC_DAPM_SINGLE("Line Bypass Switch", NAU8810_REG_MONOMIX,
NAU8810_BYPMOUT_SFT, 1, 0),
SOC_DAPM_SINGLE("PCM Playback Switch", NAU8810_REG_MONOMIX,
NAU8810_DACMOUT_SFT, 1, 0),
};
/* PGA Mute */
static const struct snd_kcontrol_new nau8810_pgaboost_mixer_controls[] = {
SOC_DAPM_SINGLE("AUX PGA Switch", NAU8810_REG_ADCBOOST,
NAU8810_AUXBSTGAIN_SFT, 0x7, 0),
SOC_DAPM_SINGLE("PGA Mute Switch", NAU8810_REG_PGAGAIN,
NAU8810_PGAMT_SFT, 1, 1),
SOC_DAPM_SINGLE("PMIC PGA Switch", NAU8810_REG_ADCBOOST,
NAU8810_PMICBSTGAIN_SFT, 0x7, 0),
};
/* Input PGA */
static const struct snd_kcontrol_new nau8810_inpga[] = {
SOC_DAPM_SINGLE("AUX Switch", NAU8810_REG_INPUT_SIGNAL,
NAU8810_AUXPGA_SFT, 1, 0),
SOC_DAPM_SINGLE("MicN Switch", NAU8810_REG_INPUT_SIGNAL,
NAU8810_NMICPGA_SFT, 1, 0),
SOC_DAPM_SINGLE("MicP Switch", NAU8810_REG_INPUT_SIGNAL,
NAU8810_PMICPGA_SFT, 1, 0),
};
/* Loopback Switch */
static const struct snd_kcontrol_new nau8810_loopback =
SOC_DAPM_SINGLE("Switch", NAU8810_REG_COMP,
NAU8810_ADDAP_SFT, 1, 0);
static int check_mclk_select_pll(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
unsigned int value;
regmap_read(nau8810->regmap, NAU8810_REG_CLOCK, &value);
return (value & NAU8810_CLKM_MASK);
}
static int check_mic_enabled(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(source->dapm);
struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
unsigned int value;
regmap_read(nau8810->regmap, NAU8810_REG_INPUT_SIGNAL, &value);
if (value & NAU8810_PMICPGA_EN || value & NAU8810_NMICPGA_EN)
return 1;
regmap_read(nau8810->regmap, NAU8810_REG_ADCBOOST, &value);
if (value & NAU8810_PMICBSTGAIN_MASK)
return 1;
return 0;
}
static const struct snd_soc_dapm_widget nau8810_dapm_widgets[] = {
SND_SOC_DAPM_MIXER("Speaker Mixer", NAU8810_REG_POWER3,
NAU8810_SPKMX_EN_SFT, 0, &nau8810_speaker_mixer_controls[0],
ARRAY_SIZE(nau8810_speaker_mixer_controls)),
SND_SOC_DAPM_MIXER("Mono Mixer", NAU8810_REG_POWER3,
NAU8810_MOUTMX_EN_SFT, 0, &nau8810_mono_mixer_controls[0],
ARRAY_SIZE(nau8810_mono_mixer_controls)),
SND_SOC_DAPM_DAC("DAC", "Playback", NAU8810_REG_POWER3,
NAU8810_DAC_EN_SFT, 0),
SND_SOC_DAPM_ADC("ADC", "Capture", NAU8810_REG_POWER2,
NAU8810_ADC_EN_SFT, 0),
SND_SOC_DAPM_PGA("SpkN Out", NAU8810_REG_POWER3,
NAU8810_NSPK_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("SpkP Out", NAU8810_REG_POWER3,
NAU8810_PSPK_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("Mono Out", NAU8810_REG_POWER3,
NAU8810_MOUT_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Input PGA", NAU8810_REG_POWER2,
NAU8810_PGA_EN_SFT, 0, nau8810_inpga,
ARRAY_SIZE(nau8810_inpga)),
SND_SOC_DAPM_MIXER("Input Boost Stage", NAU8810_REG_POWER2,
NAU8810_BST_EN_SFT, 0, nau8810_pgaboost_mixer_controls,
ARRAY_SIZE(nau8810_pgaboost_mixer_controls)),
SND_SOC_DAPM_PGA("AUX Input", NAU8810_REG_POWER1,
NAU8810_AUX_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Mic Bias", NAU8810_REG_POWER1,
NAU8810_MICBIAS_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PLL", NAU8810_REG_POWER1,
NAU8810_PLL_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_SWITCH("Digital Loopback", SND_SOC_NOPM, 0, 0,
&nau8810_loopback),
SND_SOC_DAPM_INPUT("AUX"),
SND_SOC_DAPM_INPUT("MICN"),
SND_SOC_DAPM_INPUT("MICP"),
SND_SOC_DAPM_OUTPUT("MONOOUT"),
SND_SOC_DAPM_OUTPUT("SPKOUTP"),
SND_SOC_DAPM_OUTPUT("SPKOUTN"),
};
static const struct snd_soc_dapm_route nau8810_dapm_routes[] = {
{"DAC", NULL, "PLL", check_mclk_select_pll},
/* Mono output mixer */
{"Mono Mixer", "AUX Bypass Switch", "AUX Input"},
{"Mono Mixer", "PCM Playback Switch", "DAC"},
{"Mono Mixer", "Line Bypass Switch", "Input Boost Stage"},
/* Speaker output mixer */
{"Speaker Mixer", "AUX Bypass Switch", "AUX Input"},
{"Speaker Mixer", "PCM Playback Switch", "DAC"},
{"Speaker Mixer", "Line Bypass Switch", "Input Boost Stage"},
/* Outputs */
{"Mono Out", NULL, "Mono Mixer"},
{"MONOOUT", NULL, "Mono Out"},
{"SpkN Out", NULL, "Speaker Mixer"},
{"SpkP Out", NULL, "Speaker Mixer"},
{"SPKOUTN", NULL, "SpkN Out"},
{"SPKOUTP", NULL, "SpkP Out"},
/* Input Boost Stage */
{"ADC", NULL, "Input Boost Stage"},
{"ADC", NULL, "PLL", check_mclk_select_pll},
{"Input Boost Stage", "AUX PGA Switch", "AUX Input"},
{"Input Boost Stage", "PGA Mute Switch", "Input PGA"},
{"Input Boost Stage", "PMIC PGA Switch", "MICP"},
/* Input PGA */
{"Input PGA", NULL, "Mic Bias", check_mic_enabled},
{"Input PGA", "AUX Switch", "AUX Input"},
{"Input PGA", "MicN Switch", "MICN"},
{"Input PGA", "MicP Switch", "MICP"},
{"AUX Input", NULL, "AUX"},
/* Digital Looptack */
{"Digital Loopback", "Switch", "ADC"},
{"DAC", NULL, "Digital Loopback"},
};
static int nau8810_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
nau8810->clk_id = clk_id;
nau8810->sysclk = freq;
dev_dbg(nau8810->dev, "master sysclk %dHz, source %s\n",
freq, clk_id == NAU8810_SCLK_PLL ? "PLL" : "MCLK");
return 0;
}
static int nau8810_calc_pll(unsigned int pll_in,
unsigned int fs, struct nau8810_pll *pll_param)
{
u64 f2, f2_max, pll_ratio;
int i, scal_sel;
if (pll_in > NAU_PLL_REF_MAX || pll_in < NAU_PLL_REF_MIN)
return -EINVAL;
f2_max = 0;
scal_sel = ARRAY_SIZE(nau8810_mclk_scaler);
for (i = 0; i < ARRAY_SIZE(nau8810_mclk_scaler); i++) {
f2 = 256ULL * fs * 4 * nau8810_mclk_scaler[i];
f2 = div_u64(f2, 10);
if (f2 > NAU_PLL_FREQ_MIN && f2 < NAU_PLL_FREQ_MAX &&
f2_max < f2) {
f2_max = f2;
scal_sel = i;
}
}
if (ARRAY_SIZE(nau8810_mclk_scaler) == scal_sel)
return -EINVAL;
pll_param->mclk_scaler = scal_sel;
f2 = f2_max;
/* Calculate the PLL 4-bit integer input and the PLL 24-bit fractional
* input; round up the 24+4bit.
*/
pll_ratio = div_u64(f2 << 28, pll_in);
pll_param->pre_factor = 0;
if (((pll_ratio >> 28) & 0xF) < NAU_PLL_OPTOP_MIN) {
pll_ratio <<= 1;
pll_param->pre_factor = 1;
}
pll_param->pll_int = (pll_ratio >> 28) & 0xF;
pll_param->pll_frac = ((pll_ratio & 0xFFFFFFF) >> 4);
return 0;
}
static int nau8810_set_pll(struct snd_soc_dai *codec_dai, int pll_id,
int source, unsigned int freq_in, unsigned int freq_out)
{
struct snd_soc_component *component = codec_dai->component;
struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
struct regmap *map = nau8810->regmap;
struct nau8810_pll *pll_param = &nau8810->pll;
int ret, fs;
fs = freq_out / 256;
ret = nau8810_calc_pll(freq_in, fs, pll_param);
if (ret < 0) {
dev_err(nau8810->dev, "Unsupported input clock %d\n", freq_in);
return ret;
}
dev_info(nau8810->dev, "pll_int=%x pll_frac=%x mclk_scaler=%x pre_factor=%x\n",
pll_param->pll_int, pll_param->pll_frac, pll_param->mclk_scaler,
pll_param->pre_factor);
regmap_update_bits(map, NAU8810_REG_PLLN,
NAU8810_PLLMCLK_DIV2 | NAU8810_PLLN_MASK,
(pll_param->pre_factor ? NAU8810_PLLMCLK_DIV2 : 0) |
pll_param->pll_int);
regmap_write(map, NAU8810_REG_PLLK1,
(pll_param->pll_frac >> NAU8810_PLLK1_SFT) &
NAU8810_PLLK1_MASK);
regmap_write(map, NAU8810_REG_PLLK2,
(pll_param->pll_frac >> NAU8810_PLLK2_SFT) &
NAU8810_PLLK2_MASK);
regmap_write(map, NAU8810_REG_PLLK3,
pll_param->pll_frac & NAU8810_PLLK3_MASK);
regmap_update_bits(map, NAU8810_REG_CLOCK, NAU8810_MCLKSEL_MASK,
pll_param->mclk_scaler << NAU8810_MCLKSEL_SFT);
regmap_update_bits(map, NAU8810_REG_CLOCK,
NAU8810_CLKM_MASK, NAU8810_CLKM_PLL);
return 0;
}
static int nau8810_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
u16 ctrl1_val = 0, ctrl2_val = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
ctrl2_val |= NAU8810_CLKIO_MASTER;
break;
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
ctrl1_val |= NAU8810_AIFMT_I2S;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
ctrl1_val |= NAU8810_AIFMT_LEFT;
break;
case SND_SOC_DAIFMT_DSP_A:
ctrl1_val |= NAU8810_AIFMT_PCM_A;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
ctrl1_val |= NAU8810_BCLKP_IB | NAU8810_FSP_IF;
break;
case SND_SOC_DAIFMT_IB_NF:
ctrl1_val |= NAU8810_BCLKP_IB;
break;
case SND_SOC_DAIFMT_NB_IF:
ctrl1_val |= NAU8810_FSP_IF;
break;
default:
return -EINVAL;
}
regmap_update_bits(nau8810->regmap, NAU8810_REG_IFACE,
NAU8810_AIFMT_MASK | NAU8810_FSP_IF |
NAU8810_BCLKP_IB, ctrl1_val);
regmap_update_bits(nau8810->regmap, NAU8810_REG_CLOCK,
NAU8810_CLKIO_MASK, ctrl2_val);
return 0;
}
static int nau8810_mclk_clkdiv(struct nau8810 *nau8810, int rate)
{
int i, sclk, imclk = rate * 256, div = 0;
if (!nau8810->sysclk) {
dev_err(nau8810->dev, "Make mclk div configuration fail because of invalid system clock\n");
return -EINVAL;
}
/* Configure the master clock prescaler div to make system
* clock to approximate the internal master clock (IMCLK);
* and large or equal to IMCLK.
*/
for (i = 1; i < ARRAY_SIZE(nau8810_mclk_scaler); i++) {
sclk = (nau8810->sysclk * 10) /
nau8810_mclk_scaler[i];
if (sclk < imclk)
break;
div = i;
}
dev_dbg(nau8810->dev,
"master clock prescaler %x for fs %d\n", div, rate);
/* master clock from MCLK and disable PLL */
regmap_update_bits(nau8810->regmap, NAU8810_REG_CLOCK,
NAU8810_MCLKSEL_MASK, (div << NAU8810_MCLKSEL_SFT));
regmap_update_bits(nau8810->regmap, NAU8810_REG_CLOCK,
NAU8810_CLKM_MASK, NAU8810_CLKM_MCLK);
return 0;
}
static int nau8810_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
int val_len = 0, val_rate = 0, ret = 0;
unsigned int ctrl_val, bclk_fs, bclk_div;
/* Select BCLK configuration if the codec as master. */
regmap_read(nau8810->regmap, NAU8810_REG_CLOCK, &ctrl_val);
if (ctrl_val & NAU8810_CLKIO_MASTER) {
/* get the bclk and fs ratio */
bclk_fs = snd_soc_params_to_bclk(params) / params_rate(params);
if (bclk_fs <= 32)
bclk_div = NAU8810_BCLKDIV_8;
else if (bclk_fs <= 64)
bclk_div = NAU8810_BCLKDIV_4;
else if (bclk_fs <= 128)
bclk_div = NAU8810_BCLKDIV_2;
else
return -EINVAL;
regmap_update_bits(nau8810->regmap, NAU8810_REG_CLOCK,
NAU8810_BCLKSEL_MASK, bclk_div);
}
switch (params_width(params)) {
case 16:
break;
case 20:
val_len |= NAU8810_WLEN_20;
break;
case 24:
val_len |= NAU8810_WLEN_24;
break;
case 32:
val_len |= NAU8810_WLEN_32;
break;
}
switch (params_rate(params)) {
case 8000:
val_rate |= NAU8810_SMPLR_8K;
break;
case 11025:
val_rate |= NAU8810_SMPLR_12K;
break;
case 16000:
val_rate |= NAU8810_SMPLR_16K;
break;
case 22050:
val_rate |= NAU8810_SMPLR_24K;
break;
case 32000:
val_rate |= NAU8810_SMPLR_32K;
break;
case 44100:
case 48000:
break;
}
regmap_update_bits(nau8810->regmap, NAU8810_REG_IFACE,
NAU8810_WLEN_MASK, val_len);
regmap_update_bits(nau8810->regmap, NAU8810_REG_SMPLR,
NAU8810_SMPLR_MASK, val_rate);
/* If the master clock is from MCLK, provide the runtime FS for driver
* to get the master clock prescaler configuration.
*/
if (nau8810->clk_id == NAU8810_SCLK_MCLK) {
ret = nau8810_mclk_clkdiv(nau8810, params_rate(params));
if (ret < 0)
dev_err(nau8810->dev, "MCLK div configuration fail\n");
}
return ret;
}
static int nau8810_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct nau8810 *nau8810 = snd_soc_component_get_drvdata(component);
struct regmap *map = nau8810->regmap;
switch (level) {
case SND_SOC_BIAS_ON:
case SND_SOC_BIAS_PREPARE:
regmap_update_bits(map, NAU8810_REG_POWER1,
NAU8810_REFIMP_MASK, NAU8810_REFIMP_80K);
break;
case SND_SOC_BIAS_STANDBY:
regmap_update_bits(map, NAU8810_REG_POWER1,
NAU8810_IOBUF_EN | NAU8810_ABIAS_EN,
NAU8810_IOBUF_EN | NAU8810_ABIAS_EN);
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
regcache_sync(map);
regmap_update_bits(map, NAU8810_REG_POWER1,
NAU8810_REFIMP_MASK, NAU8810_REFIMP_3K);
mdelay(100);
}
regmap_update_bits(map, NAU8810_REG_POWER1,
NAU8810_REFIMP_MASK, NAU8810_REFIMP_300K);
break;
case SND_SOC_BIAS_OFF:
regmap_write(map, NAU8810_REG_POWER1, 0);
regmap_write(map, NAU8810_REG_POWER2, 0);
regmap_write(map, NAU8810_REG_POWER3, 0);
break;
}
return 0;
}
#define NAU8810_RATES (SNDRV_PCM_RATE_8000_48000)
#define NAU8810_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops nau8810_ops = {
.hw_params = nau8810_pcm_hw_params,
.set_fmt = nau8810_set_dai_fmt,
.set_sysclk = nau8810_set_sysclk,
.set_pll = nau8810_set_pll,
};
static struct snd_soc_dai_driver nau8810_dai = {
.name = "nau8810-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2, /* Only 1 channel of data */
.rates = NAU8810_RATES,
.formats = NAU8810_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2, /* Only 1 channel of data */
.rates = NAU8810_RATES,
.formats = NAU8810_FORMATS,
},
.ops = &nau8810_ops,
.symmetric_rate = 1,
};
static const struct regmap_config nau8810_regmap_config = {
.reg_bits = 7,
.val_bits = 9,
.max_register = NAU8810_REG_MAX,
.readable_reg = nau8810_readable_reg,
.writeable_reg = nau8810_writeable_reg,
.volatile_reg = nau8810_volatile_reg,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = nau8810_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(nau8810_reg_defaults),
};
static const struct snd_soc_component_driver nau8810_component_driver = {
.set_bias_level = nau8810_set_bias_level,
.controls = nau8810_snd_controls,
.num_controls = ARRAY_SIZE(nau8810_snd_controls),
.dapm_widgets = nau8810_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(nau8810_dapm_widgets),
.dapm_routes = nau8810_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(nau8810_dapm_routes),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int nau8810_i2c_probe(struct i2c_client *i2c)
{
struct device *dev = &i2c->dev;
struct nau8810 *nau8810 = dev_get_platdata(dev);
if (!nau8810) {
nau8810 = devm_kzalloc(dev, sizeof(*nau8810), GFP_KERNEL);
if (!nau8810)
return -ENOMEM;
}
i2c_set_clientdata(i2c, nau8810);
nau8810->regmap = devm_regmap_init_i2c(i2c, &nau8810_regmap_config);
if (IS_ERR(nau8810->regmap))
return PTR_ERR(nau8810->regmap);
nau8810->dev = dev;
regmap_write(nau8810->regmap, NAU8810_REG_RESET, 0x00);
return devm_snd_soc_register_component(dev,
&nau8810_component_driver, &nau8810_dai, 1);
}
static const struct i2c_device_id nau8810_i2c_id[] = {
{ "nau8810", 0 },
{ "nau8812", 0 },
{ "nau8814", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, nau8810_i2c_id);
#ifdef CONFIG_OF
static const struct of_device_id nau8810_of_match[] = {
{ .compatible = "nuvoton,nau8810", },
{ .compatible = "nuvoton,nau8812", },
{ .compatible = "nuvoton,nau8814", },
{ }
};
MODULE_DEVICE_TABLE(of, nau8810_of_match);
#endif
static struct i2c_driver nau8810_i2c_driver = {
.driver = {
.name = "nau8810",
.of_match_table = of_match_ptr(nau8810_of_match),
},
.probe = nau8810_i2c_probe,
.id_table = nau8810_i2c_id,
};
module_i2c_driver(nau8810_i2c_driver);
MODULE_DESCRIPTION("ASoC NAU8810 driver");
MODULE_AUTHOR("David Lin <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/nau8810.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* ALSA Soc PCM3008 codec support
*
* Author: Hugo Villeneuve
* Copyright (C) 2008 Lyrtech inc
*
* Based on AC97 Soc codec, original copyright follow:
* Copyright 2005 Wolfson Microelectronics PLC.
*
* Generic PCM3008 support.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/gpio.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include "pcm3008.h"
static int pcm3008_dac_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct pcm3008_setup_data *setup = component->dev->platform_data;
gpio_set_value_cansleep(setup->pdda_pin,
SND_SOC_DAPM_EVENT_ON(event));
return 0;
}
static int pcm3008_adc_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct pcm3008_setup_data *setup = component->dev->platform_data;
gpio_set_value_cansleep(setup->pdad_pin,
SND_SOC_DAPM_EVENT_ON(event));
return 0;
}
static const struct snd_soc_dapm_widget pcm3008_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("VINL"),
SND_SOC_DAPM_INPUT("VINR"),
SND_SOC_DAPM_DAC_E("DAC", NULL, SND_SOC_NOPM, 0, 0, pcm3008_dac_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_ADC_E("ADC", NULL, SND_SOC_NOPM, 0, 0, pcm3008_adc_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_OUTPUT("VOUTL"),
SND_SOC_DAPM_OUTPUT("VOUTR"),
};
static const struct snd_soc_dapm_route pcm3008_dapm_routes[] = {
{ "PCM3008 Capture", NULL, "ADC" },
{ "ADC", NULL, "VINL" },
{ "ADC", NULL, "VINR" },
{ "DAC", NULL, "PCM3008 Playback" },
{ "VOUTL", NULL, "DAC" },
{ "VOUTR", NULL, "DAC" },
};
#define PCM3008_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000)
static struct snd_soc_dai_driver pcm3008_dai = {
.name = "pcm3008-hifi",
.playback = {
.stream_name = "PCM3008 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = PCM3008_RATES,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.capture = {
.stream_name = "PCM3008 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = PCM3008_RATES,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
};
static const struct snd_soc_component_driver soc_component_dev_pcm3008 = {
.dapm_widgets = pcm3008_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(pcm3008_dapm_widgets),
.dapm_routes = pcm3008_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(pcm3008_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int pcm3008_codec_probe(struct platform_device *pdev)
{
struct pcm3008_setup_data *setup = pdev->dev.platform_data;
int ret;
if (!setup)
return -EINVAL;
/* DEM1 DEM0 DE-EMPHASIS_MODE
* Low Low De-emphasis 44.1 kHz ON
* Low High De-emphasis OFF
* High Low De-emphasis 48 kHz ON
* High High De-emphasis 32 kHz ON
*/
/* Configure DEM0 GPIO (turning OFF DAC De-emphasis). */
ret = devm_gpio_request_one(&pdev->dev, setup->dem0_pin,
GPIOF_OUT_INIT_HIGH, "codec_dem0");
if (ret != 0)
return ret;
/* Configure DEM1 GPIO (turning OFF DAC De-emphasis). */
ret = devm_gpio_request_one(&pdev->dev, setup->dem1_pin,
GPIOF_OUT_INIT_LOW, "codec_dem1");
if (ret != 0)
return ret;
/* Configure PDAD GPIO. */
ret = devm_gpio_request_one(&pdev->dev, setup->pdad_pin,
GPIOF_OUT_INIT_LOW, "codec_pdad");
if (ret != 0)
return ret;
/* Configure PDDA GPIO. */
ret = devm_gpio_request_one(&pdev->dev, setup->pdda_pin,
GPIOF_OUT_INIT_LOW, "codec_pdda");
if (ret != 0)
return ret;
return devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_pcm3008, &pcm3008_dai, 1);
}
MODULE_ALIAS("platform:pcm3008-codec");
static struct platform_driver pcm3008_codec_driver = {
.probe = pcm3008_codec_probe,
.driver = {
.name = "pcm3008-codec",
},
};
module_platform_driver(pcm3008_codec_driver);
MODULE_DESCRIPTION("Soc PCM3008 driver");
MODULE_AUTHOR("Hugo Villeneuve");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/pcm3008.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// ALSA SoC Audio driver for CS47L92 codec
//
// Copyright (C) 2016-2019 Cirrus Logic, Inc. and
// Cirrus Logic International Semiconductor Ltd.
//
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <linux/irqchip/irq-madera.h>
#include <linux/mfd/madera/core.h>
#include <linux/mfd/madera/registers.h>
#include "madera.h"
#include "wm_adsp.h"
#define CS47L92_NUM_ADSP 1
#define CS47L92_MONO_OUTPUTS 3
#define DRV_NAME "cs47l92-codec"
struct cs47l92 {
struct madera_priv core;
struct madera_fll fll[2];
};
static const struct cs_dsp_region cs47l92_dsp1_regions[] = {
{ .type = WMFW_ADSP2_PM, .base = 0x080000 },
{ .type = WMFW_ADSP2_ZM, .base = 0x0e0000 },
{ .type = WMFW_ADSP2_XM, .base = 0x0a0000 },
{ .type = WMFW_ADSP2_YM, .base = 0x0c0000 },
};
static const char * const cs47l92_outdemux_texts[] = {
"HPOUT3",
"HPOUT4",
};
static int cs47l92_put_demux(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_dapm_kcontrol_component(kcontrol);
struct snd_soc_dapm_context *dapm =
snd_soc_component_get_dapm(component);
struct cs47l92 *cs47l92 = snd_soc_component_get_drvdata(component);
struct madera_priv *priv = &cs47l92->core;
struct madera *madera = priv->madera;
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int ep_sel, mux, change, cur;
bool out_mono;
int ret;
if (ucontrol->value.enumerated.item[0] > e->items - 1)
return -EINVAL;
mux = ucontrol->value.enumerated.item[0];
snd_soc_dapm_mutex_lock(dapm);
ep_sel = mux << e->shift_l;
change = snd_soc_component_test_bits(component, MADERA_OUTPUT_ENABLES_1,
MADERA_EP_SEL_MASK,
ep_sel);
if (!change)
goto end;
ret = regmap_read(madera->regmap, MADERA_OUTPUT_ENABLES_1, &cur);
if (ret != 0)
dev_warn(madera->dev, "Failed to read outputs: %d\n", ret);
/* EP_SEL should not be modified while HPOUT3 or 4 is enabled */
ret = regmap_update_bits(madera->regmap, MADERA_OUTPUT_ENABLES_1,
MADERA_OUT3L_ENA | MADERA_OUT3R_ENA, 0);
if (ret)
dev_warn(madera->dev, "Failed to disable outputs: %d\n", ret);
usleep_range(2000, 3000); /* wait for wseq to complete */
ret = regmap_update_bits(madera->regmap, MADERA_OUTPUT_ENABLES_1,
MADERA_EP_SEL, ep_sel);
if (ret) {
dev_err(madera->dev, "Failed to set OUT3 demux: %d\n", ret);
} else {
out_mono = madera->pdata.codec.out_mono[2 + mux];
ret = madera_set_output_mode(component, 3, out_mono);
if (ret < 0)
dev_warn(madera->dev,
"Failed to set output mode: %d\n", ret);
}
ret = regmap_update_bits(madera->regmap, MADERA_OUTPUT_ENABLES_1,
MADERA_OUT3L_ENA | MADERA_OUT3R_ENA, cur);
if (ret) {
dev_warn(madera->dev, "Failed to restore outputs: %d\n", ret);
} else {
/* wait for wseq */
if (cur & (MADERA_OUT3L_ENA | MADERA_OUT3R_ENA))
msleep(34); /* enable delay */
else
usleep_range(2000, 3000); /* disable delay */
}
end:
snd_soc_dapm_mutex_unlock(dapm);
ret = snd_soc_dapm_mux_update_power(dapm, kcontrol, mux, e, NULL);
if (ret < 0) {
dev_err(madera->dev, "Failed to update demux power state: %d\n", ret);
return ret;
}
return change;
}
static SOC_ENUM_SINGLE_DECL(cs47l92_outdemux_enum,
MADERA_OUTPUT_ENABLES_1,
MADERA_EP_SEL_SHIFT,
cs47l92_outdemux_texts);
static const struct snd_kcontrol_new cs47l92_outdemux =
SOC_DAPM_ENUM_EXT("OUT3 Demux", cs47l92_outdemux_enum,
snd_soc_dapm_get_enum_double, cs47l92_put_demux);
static int cs47l92_adsp_power_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct cs47l92 *cs47l92 = snd_soc_component_get_drvdata(component);
struct madera_priv *priv = &cs47l92->core;
struct madera *madera = priv->madera;
unsigned int freq;
int ret;
ret = regmap_read(madera->regmap, MADERA_DSP_CLOCK_2, &freq);
if (ret != 0) {
dev_err(madera->dev,
"Failed to read MADERA_DSP_CLOCK_2: %d\n", ret);
return ret;
}
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
ret = madera_set_adsp_clk(&cs47l92->core, w->shift, freq);
if (ret)
return ret;
break;
default:
break;
}
return wm_adsp_early_event(w, kcontrol, event);
}
static int cs47l92_outclk_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct cs47l92 *cs47l92 = snd_soc_component_get_drvdata(component);
struct madera_priv *priv = &cs47l92->core;
struct madera *madera = priv->madera;
unsigned int val;
int ret;
ret = regmap_read(madera->regmap, MADERA_OUTPUT_RATE_1, &val);
if (ret) {
dev_err(madera->dev, "Failed to read OUTCLK source: %d\n", ret);
return ret;
}
val &= MADERA_OUT_CLK_SRC_MASK;
switch (val) {
case MADERA_OUTCLK_MCLK1:
case MADERA_OUTCLK_MCLK2:
case MADERA_OUTCLK_MCLK3:
val -= (MADERA_OUTCLK_MCLK1 - MADERA_MCLK1);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
ret = clk_prepare_enable(madera->mclk[val].clk);
if (ret)
return ret;
break;
case SND_SOC_DAPM_POST_PMD:
clk_disable_unprepare(madera->mclk[val].clk);
break;
default:
break;
}
break;
default:
break;
}
return madera_domain_clk_ev(w, kcontrol, event);
}
#define CS47L92_NG_SRC(name, base) \
SOC_SINGLE(name " NG HPOUT1L Switch", base, 0, 1, 0), \
SOC_SINGLE(name " NG HPOUT1R Switch", base, 1, 1, 0), \
SOC_SINGLE(name " NG HPOUT2L Switch", base, 2, 1, 0), \
SOC_SINGLE(name " NG HPOUT2R Switch", base, 3, 1, 0), \
SOC_SINGLE(name " NG HPOUT3L Switch", base, 4, 1, 0), \
SOC_SINGLE(name " NG HPOUT3R Switch", base, 5, 1, 0), \
SOC_SINGLE(name " NG SPKDAT1L Switch", base, 8, 1, 0), \
SOC_SINGLE(name " NG SPKDAT1R Switch", base, 9, 1, 0)
static const struct snd_kcontrol_new cs47l92_snd_controls[] = {
SOC_ENUM("IN1 OSR", madera_in_dmic_osr[0]),
SOC_ENUM("IN2 OSR", madera_in_dmic_osr[1]),
SOC_ENUM("IN3 OSR", madera_in_dmic_osr[2]),
SOC_ENUM("IN4 OSR", madera_in_dmic_osr[3]),
SOC_SINGLE_RANGE_TLV("IN1L Volume", MADERA_IN1L_CONTROL,
MADERA_IN1L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
SOC_SINGLE_RANGE_TLV("IN1R Volume", MADERA_IN1R_CONTROL,
MADERA_IN1R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
SOC_SINGLE_RANGE_TLV("IN2L Volume", MADERA_IN2L_CONTROL,
MADERA_IN2L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
SOC_SINGLE_RANGE_TLV("IN2R Volume", MADERA_IN2R_CONTROL,
MADERA_IN2R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
SOC_ENUM("IN HPF Cutoff Frequency", madera_in_hpf_cut_enum),
SOC_SINGLE_EXT("IN1L LP Switch", MADERA_ADC_DIGITAL_VOLUME_1L,
MADERA_IN1L_LP_MODE_SHIFT, 1, 0,
snd_soc_get_volsw, madera_lp_mode_put),
SOC_SINGLE_EXT("IN1R LP Switch", MADERA_ADC_DIGITAL_VOLUME_1R,
MADERA_IN1L_LP_MODE_SHIFT, 1, 0,
snd_soc_get_volsw, madera_lp_mode_put),
SOC_SINGLE_EXT("IN2L LP Switch", MADERA_ADC_DIGITAL_VOLUME_2L,
MADERA_IN1L_LP_MODE_SHIFT, 1, 0,
snd_soc_get_volsw, madera_lp_mode_put),
SOC_SINGLE_EXT("IN2R LP Switch", MADERA_ADC_DIGITAL_VOLUME_2R,
MADERA_IN1L_LP_MODE_SHIFT, 1, 0,
snd_soc_get_volsw, madera_lp_mode_put),
SOC_SINGLE("IN1L HPF Switch", MADERA_IN1L_CONTROL,
MADERA_IN1L_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN1R HPF Switch", MADERA_IN1R_CONTROL,
MADERA_IN1R_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN2L HPF Switch", MADERA_IN2L_CONTROL,
MADERA_IN2L_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN2R HPF Switch", MADERA_IN2R_CONTROL,
MADERA_IN2R_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN3L HPF Switch", MADERA_IN3L_CONTROL,
MADERA_IN3L_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN3R HPF Switch", MADERA_IN3R_CONTROL,
MADERA_IN3R_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN4L HPF Switch", MADERA_IN4L_CONTROL,
MADERA_IN4L_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN4R HPF Switch", MADERA_IN4R_CONTROL,
MADERA_IN4R_HPF_SHIFT, 1, 0),
SOC_SINGLE_TLV("IN1L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_1L,
MADERA_IN1L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_SINGLE_TLV("IN1R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_1R,
MADERA_IN1R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_SINGLE_TLV("IN2L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_2L,
MADERA_IN2L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_SINGLE_TLV("IN2R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_2R,
MADERA_IN2R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_SINGLE_TLV("IN3L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_3L,
MADERA_IN3L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_SINGLE_TLV("IN3R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_3R,
MADERA_IN3R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_SINGLE_TLV("IN4L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_4L,
MADERA_IN4L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_SINGLE_TLV("IN4R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_4R,
MADERA_IN4R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_ENUM("Input Ramp Up", madera_in_vi_ramp),
SOC_ENUM("Input Ramp Down", madera_in_vd_ramp),
MADERA_MIXER_CONTROLS("EQ1", MADERA_EQ1MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("EQ2", MADERA_EQ2MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("EQ3", MADERA_EQ3MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("EQ4", MADERA_EQ4MIX_INPUT_1_SOURCE),
MADERA_EQ_CONTROL("EQ1 Coefficients", MADERA_EQ1_2),
SOC_SINGLE_TLV("EQ1 B1 Volume", MADERA_EQ1_1, MADERA_EQ1_B1_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ1 B2 Volume", MADERA_EQ1_1, MADERA_EQ1_B2_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ1 B3 Volume", MADERA_EQ1_1, MADERA_EQ1_B3_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ1 B4 Volume", MADERA_EQ1_2, MADERA_EQ1_B4_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ1 B5 Volume", MADERA_EQ1_2, MADERA_EQ1_B5_GAIN_SHIFT,
24, 0, madera_eq_tlv),
MADERA_EQ_CONTROL("EQ2 Coefficients", MADERA_EQ2_2),
SOC_SINGLE_TLV("EQ2 B1 Volume", MADERA_EQ2_1, MADERA_EQ2_B1_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ2 B2 Volume", MADERA_EQ2_1, MADERA_EQ2_B2_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ2 B3 Volume", MADERA_EQ2_1, MADERA_EQ2_B3_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ2 B4 Volume", MADERA_EQ2_2, MADERA_EQ2_B4_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ2 B5 Volume", MADERA_EQ2_2, MADERA_EQ2_B5_GAIN_SHIFT,
24, 0, madera_eq_tlv),
MADERA_EQ_CONTROL("EQ3 Coefficients", MADERA_EQ3_2),
SOC_SINGLE_TLV("EQ3 B1 Volume", MADERA_EQ3_1, MADERA_EQ3_B1_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ3 B2 Volume", MADERA_EQ3_1, MADERA_EQ3_B2_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ3 B3 Volume", MADERA_EQ3_1, MADERA_EQ3_B3_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ3 B4 Volume", MADERA_EQ3_2, MADERA_EQ3_B4_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ3 B5 Volume", MADERA_EQ3_2, MADERA_EQ3_B5_GAIN_SHIFT,
24, 0, madera_eq_tlv),
MADERA_EQ_CONTROL("EQ4 Coefficients", MADERA_EQ4_2),
SOC_SINGLE_TLV("EQ4 B1 Volume", MADERA_EQ4_1, MADERA_EQ4_B1_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ4 B2 Volume", MADERA_EQ4_1, MADERA_EQ4_B2_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ4 B3 Volume", MADERA_EQ4_1, MADERA_EQ4_B3_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ4 B4 Volume", MADERA_EQ4_2, MADERA_EQ4_B4_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ4 B5 Volume", MADERA_EQ4_2, MADERA_EQ4_B5_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE("DAC High Performance Mode Switch", MADERA_OUTPUT_RATE_1,
MADERA_CP_DAC_MODE_SHIFT, 1, 0),
MADERA_MIXER_CONTROLS("DRC1L", MADERA_DRC1LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DRC1R", MADERA_DRC1RMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DRC2L", MADERA_DRC2LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DRC2R", MADERA_DRC2RMIX_INPUT_1_SOURCE),
SND_SOC_BYTES_MASK("DRC1", MADERA_DRC1_CTRL1, 5,
MADERA_DRC1R_ENA | MADERA_DRC1L_ENA),
SND_SOC_BYTES_MASK("DRC2", MADERA_DRC2_CTRL1, 5,
MADERA_DRC2R_ENA | MADERA_DRC2L_ENA),
MADERA_MIXER_CONTROLS("LHPF1", MADERA_HPLP1MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("LHPF2", MADERA_HPLP2MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("LHPF3", MADERA_HPLP3MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("LHPF4", MADERA_HPLP4MIX_INPUT_1_SOURCE),
MADERA_LHPF_CONTROL("LHPF1 Coefficients", MADERA_HPLPF1_2),
MADERA_LHPF_CONTROL("LHPF2 Coefficients", MADERA_HPLPF2_2),
MADERA_LHPF_CONTROL("LHPF3 Coefficients", MADERA_HPLPF3_2),
MADERA_LHPF_CONTROL("LHPF4 Coefficients", MADERA_HPLPF4_2),
SOC_ENUM("LHPF1 Mode", madera_lhpf1_mode),
SOC_ENUM("LHPF2 Mode", madera_lhpf2_mode),
SOC_ENUM("LHPF3 Mode", madera_lhpf3_mode),
SOC_ENUM("LHPF4 Mode", madera_lhpf4_mode),
MADERA_RATE_ENUM("ISRC1 FSL", madera_isrc_fsl[0]),
MADERA_RATE_ENUM("ISRC2 FSL", madera_isrc_fsl[1]),
MADERA_RATE_ENUM("ISRC1 FSH", madera_isrc_fsh[0]),
MADERA_RATE_ENUM("ISRC2 FSH", madera_isrc_fsh[1]),
MADERA_RATE_ENUM("ASRC1 Rate 1", madera_asrc1_bidir_rate[0]),
MADERA_RATE_ENUM("ASRC1 Rate 2", madera_asrc1_bidir_rate[1]),
WM_ADSP2_PRELOAD_SWITCH("DSP1", 1),
MADERA_MIXER_CONTROLS("DSP1L", MADERA_DSP1LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DSP1R", MADERA_DSP1RMIX_INPUT_1_SOURCE),
SOC_SINGLE_TLV("Noise Generator Volume", MADERA_COMFORT_NOISE_GENERATOR,
MADERA_NOISE_GEN_GAIN_SHIFT, 0x16, 0, madera_noise_tlv),
MADERA_MIXER_CONTROLS("HPOUT1L", MADERA_OUT1LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("HPOUT1R", MADERA_OUT1RMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("HPOUT2L", MADERA_OUT2LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("HPOUT2R", MADERA_OUT2RMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("HPOUT3L", MADERA_OUT3LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("HPOUT3R", MADERA_OUT3RMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SPKDAT1L", MADERA_OUT5LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SPKDAT1R", MADERA_OUT5RMIX_INPUT_1_SOURCE),
SOC_SINGLE("HPOUT1 SC Protect Switch", MADERA_HP1_SHORT_CIRCUIT_CTRL,
MADERA_HP1_SC_ENA_SHIFT, 1, 0),
SOC_SINGLE("HPOUT2 SC Protect Switch", MADERA_HP2_SHORT_CIRCUIT_CTRL,
MADERA_HP2_SC_ENA_SHIFT, 1, 0),
SOC_SINGLE("HPOUT3 SC Protect Switch", MADERA_HP3_SHORT_CIRCUIT_CTRL,
MADERA_HP3_SC_ENA_SHIFT, 1, 0),
SOC_SINGLE("SPKDAT1 High Performance Switch", MADERA_OUTPUT_PATH_CONFIG_5L,
MADERA_OUT5_OSR_SHIFT, 1, 0),
SOC_DOUBLE_R("HPOUT1 Digital Switch", MADERA_DAC_DIGITAL_VOLUME_1L,
MADERA_DAC_DIGITAL_VOLUME_1R, MADERA_OUT1L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R("HPOUT2 Digital Switch", MADERA_DAC_DIGITAL_VOLUME_2L,
MADERA_DAC_DIGITAL_VOLUME_2R, MADERA_OUT2L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R("HPOUT3 Digital Switch", MADERA_DAC_DIGITAL_VOLUME_3L,
MADERA_DAC_DIGITAL_VOLUME_3R, MADERA_OUT3L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R("SPKDAT1 Digital Switch", MADERA_DAC_DIGITAL_VOLUME_5L,
MADERA_DAC_DIGITAL_VOLUME_5R, MADERA_OUT5L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", MADERA_DAC_DIGITAL_VOLUME_1L,
MADERA_DAC_DIGITAL_VOLUME_1R, MADERA_OUT1L_VOL_SHIFT,
0xbf, 0, madera_digital_tlv),
SOC_DOUBLE_R_TLV("HPOUT2 Digital Volume", MADERA_DAC_DIGITAL_VOLUME_2L,
MADERA_DAC_DIGITAL_VOLUME_2R, MADERA_OUT2L_VOL_SHIFT,
0xbf, 0, madera_digital_tlv),
SOC_DOUBLE_R_TLV("HPOUT3 Digital Volume", MADERA_DAC_DIGITAL_VOLUME_3L,
MADERA_DAC_DIGITAL_VOLUME_3R, MADERA_OUT3L_VOL_SHIFT,
0xbf, 0, madera_digital_tlv),
SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", MADERA_DAC_DIGITAL_VOLUME_5L,
MADERA_DAC_DIGITAL_VOLUME_5R, MADERA_OUT5L_VOL_SHIFT,
0xbf, 0, madera_digital_tlv),
SOC_DOUBLE("SPKDAT1 Switch", MADERA_PDM_SPK1_CTRL_1, MADERA_SPK1L_MUTE_SHIFT,
MADERA_SPK1R_MUTE_SHIFT, 1, 1),
SOC_ENUM("Output Ramp Up", madera_out_vi_ramp),
SOC_ENUM("Output Ramp Down", madera_out_vd_ramp),
SOC_SINGLE("Noise Gate Switch", MADERA_NOISE_GATE_CONTROL,
MADERA_NGATE_ENA_SHIFT, 1, 0),
SOC_SINGLE_TLV("Noise Gate Threshold Volume", MADERA_NOISE_GATE_CONTROL,
MADERA_NGATE_THR_SHIFT, 7, 1, madera_ng_tlv),
SOC_ENUM("Noise Gate Hold", madera_ng_hold),
SOC_ENUM_EXT("DFC1RX Width", madera_dfc_width[0],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC1RX Type", madera_dfc_type[0],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC1TX Width", madera_dfc_width[1],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC1TX Type", madera_dfc_type[1],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC2RX Width", madera_dfc_width[2],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC2RX Type", madera_dfc_type[2],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC2TX Width", madera_dfc_width[3],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC2TX Type", madera_dfc_type[3],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC3RX Width", madera_dfc_width[4],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC3RX Type", madera_dfc_type[4],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC3TX Width", madera_dfc_width[5],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC3TX Type", madera_dfc_type[5],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC4RX Width", madera_dfc_width[6],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC4RX Type", madera_dfc_type[6],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC4TX Width", madera_dfc_width[7],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC4TX Type", madera_dfc_type[7],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC5RX Width", madera_dfc_width[8],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC5RX Type", madera_dfc_type[8],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC5TX Width", madera_dfc_width[9],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC5TX Type", madera_dfc_type[9],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC6RX Width", madera_dfc_width[10],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC6RX Type", madera_dfc_type[10],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC6TX Width", madera_dfc_width[11],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC6TX Type", madera_dfc_type[11],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC7RX Width", madera_dfc_width[12],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC7RX Type", madera_dfc_type[12],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC7TX Width", madera_dfc_width[13],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC7TX Type", madera_dfc_type[13],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC8RX Width", madera_dfc_width[14],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC8RX Type", madera_dfc_type[14],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC8TX Width", madera_dfc_width[15],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC8TX Type", madera_dfc_type[15],
snd_soc_get_enum_double, madera_dfc_put),
CS47L92_NG_SRC("HPOUT1L", MADERA_NOISE_GATE_SELECT_1L),
CS47L92_NG_SRC("HPOUT1R", MADERA_NOISE_GATE_SELECT_1R),
CS47L92_NG_SRC("HPOUT2L", MADERA_NOISE_GATE_SELECT_2L),
CS47L92_NG_SRC("HPOUT2R", MADERA_NOISE_GATE_SELECT_2R),
CS47L92_NG_SRC("HPOUT3L", MADERA_NOISE_GATE_SELECT_3L),
CS47L92_NG_SRC("HPOUT3R", MADERA_NOISE_GATE_SELECT_3R),
CS47L92_NG_SRC("SPKDAT1L", MADERA_NOISE_GATE_SELECT_5L),
CS47L92_NG_SRC("SPKDAT1R", MADERA_NOISE_GATE_SELECT_5R),
MADERA_MIXER_CONTROLS("AIF1TX1", MADERA_AIF1TX1MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF1TX2", MADERA_AIF1TX2MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF1TX3", MADERA_AIF1TX3MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF1TX4", MADERA_AIF1TX4MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF1TX5", MADERA_AIF1TX5MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF1TX6", MADERA_AIF1TX6MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF1TX7", MADERA_AIF1TX7MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF1TX8", MADERA_AIF1TX8MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF2TX1", MADERA_AIF2TX1MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF2TX2", MADERA_AIF2TX2MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF2TX3", MADERA_AIF2TX3MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF2TX4", MADERA_AIF2TX4MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF2TX5", MADERA_AIF2TX5MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF2TX6", MADERA_AIF2TX6MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF2TX7", MADERA_AIF2TX7MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF2TX8", MADERA_AIF2TX8MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF3TX1", MADERA_AIF3TX1MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF3TX2", MADERA_AIF3TX2MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF3TX3", MADERA_AIF3TX3MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF3TX4", MADERA_AIF3TX4MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SLIMTX1", MADERA_SLIMTX1MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SLIMTX2", MADERA_SLIMTX2MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SLIMTX3", MADERA_SLIMTX3MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SLIMTX4", MADERA_SLIMTX4MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SLIMTX5", MADERA_SLIMTX5MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SLIMTX6", MADERA_SLIMTX6MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SLIMTX7", MADERA_SLIMTX7MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SLIMTX8", MADERA_SLIMTX8MIX_INPUT_1_SOURCE),
MADERA_GAINMUX_CONTROLS("SPDIFTX1", MADERA_SPDIF1TX1MIX_INPUT_1_SOURCE),
MADERA_GAINMUX_CONTROLS("SPDIFTX2", MADERA_SPDIF1TX2MIX_INPUT_1_SOURCE),
WM_ADSP_FW_CONTROL("DSP1", 0),
};
MADERA_MIXER_ENUMS(EQ1, MADERA_EQ1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(EQ2, MADERA_EQ2MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(EQ3, MADERA_EQ3MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(EQ4, MADERA_EQ4MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DRC1L, MADERA_DRC1LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DRC1R, MADERA_DRC1RMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DRC2L, MADERA_DRC2LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DRC2R, MADERA_DRC2RMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(LHPF1, MADERA_HPLP1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(LHPF2, MADERA_HPLP2MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(LHPF3, MADERA_HPLP3MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(LHPF4, MADERA_HPLP4MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP1L, MADERA_DSP1LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP1R, MADERA_DSP1RMIX_INPUT_1_SOURCE);
MADERA_DSP_AUX_ENUMS(DSP1, MADERA_DSP1AUX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(PWM1, MADERA_PWM1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(PWM2, MADERA_PWM2MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(OUT1L, MADERA_OUT1LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(OUT1R, MADERA_OUT1RMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(OUT2L, MADERA_OUT2LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(OUT2R, MADERA_OUT2RMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(OUT3L, MADERA_OUT3LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(OUT3R, MADERA_OUT3RMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SPKDAT1L, MADERA_OUT5LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SPKDAT1R, MADERA_OUT5RMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX1, MADERA_AIF1TX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX2, MADERA_AIF1TX2MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX3, MADERA_AIF1TX3MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX4, MADERA_AIF1TX4MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX5, MADERA_AIF1TX5MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX6, MADERA_AIF1TX6MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX7, MADERA_AIF1TX7MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX8, MADERA_AIF1TX8MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF2TX1, MADERA_AIF2TX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF2TX2, MADERA_AIF2TX2MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF2TX3, MADERA_AIF2TX3MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF2TX4, MADERA_AIF2TX4MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF2TX5, MADERA_AIF2TX5MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF2TX6, MADERA_AIF2TX6MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF2TX7, MADERA_AIF2TX7MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF2TX8, MADERA_AIF2TX8MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF3TX1, MADERA_AIF3TX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF3TX2, MADERA_AIF3TX2MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF3TX3, MADERA_AIF3TX3MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF3TX4, MADERA_AIF3TX4MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SLIMTX1, MADERA_SLIMTX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SLIMTX2, MADERA_SLIMTX2MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SLIMTX3, MADERA_SLIMTX3MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SLIMTX4, MADERA_SLIMTX4MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SLIMTX5, MADERA_SLIMTX5MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SLIMTX6, MADERA_SLIMTX6MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SLIMTX7, MADERA_SLIMTX7MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SLIMTX8, MADERA_SLIMTX8MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(SPD1TX1, MADERA_SPDIF1TX1MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(SPD1TX2, MADERA_SPDIF1TX2MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ASRC1IN1L, MADERA_ASRC1_1LMIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ASRC1IN1R, MADERA_ASRC1_1RMIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ASRC1IN2L, MADERA_ASRC1_2LMIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ASRC1IN2R, MADERA_ASRC1_2RMIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1INT1, MADERA_ISRC1INT1MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1INT2, MADERA_ISRC1INT2MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1DEC1, MADERA_ISRC1DEC1MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1DEC2, MADERA_ISRC1DEC2MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2INT1, MADERA_ISRC2INT1MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2INT2, MADERA_ISRC2INT2MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2DEC1, MADERA_ISRC2DEC1MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2DEC2, MADERA_ISRC2DEC2MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(DFC1, MADERA_DFC1MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(DFC2, MADERA_DFC2MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(DFC3, MADERA_DFC3MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(DFC4, MADERA_DFC4MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(DFC5, MADERA_DFC5MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(DFC6, MADERA_DFC6MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(DFC7, MADERA_DFC7MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(DFC8, MADERA_DFC8MIX_INPUT_1_SOURCE);
static const char * const cs47l92_aec_loopback_texts[] = {
"HPOUT1L", "HPOUT1R", "HPOUT2L", "HPOUT2R", "HPOUT3L", "HPOUT3R",
"SPKDAT1L", "SPKDAT1R",
};
static const unsigned int cs47l92_aec_loopback_values[] = {
0, 1, 2, 3, 4, 5, 8, 9
};
static const struct soc_enum cs47l92_aec_loopback =
SOC_VALUE_ENUM_SINGLE(MADERA_DAC_AEC_CONTROL_1,
MADERA_AEC1_LOOPBACK_SRC_SHIFT, 0xf,
ARRAY_SIZE(cs47l92_aec_loopback_texts),
cs47l92_aec_loopback_texts,
cs47l92_aec_loopback_values);
static const struct snd_kcontrol_new cs47l92_aec_loopback_mux =
SOC_DAPM_ENUM("AEC1 Loopback", cs47l92_aec_loopback);
static const struct snd_soc_dapm_widget cs47l92_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("SYSCLK", MADERA_SYSTEM_CLOCK_1, MADERA_SYSCLK_ENA_SHIFT,
0, madera_sysclk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("ASYNCCLK", MADERA_ASYNC_CLOCK_1,
MADERA_ASYNC_CLK_ENA_SHIFT, 0, madera_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("OPCLK", MADERA_OUTPUT_SYSTEM_CLOCK,
MADERA_OPCLK_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ASYNCOPCLK", MADERA_OUTPUT_ASYNC_CLOCK,
MADERA_OPCLK_ASYNC_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DSPCLK", MADERA_DSP_CLOCK_1, MADERA_DSP_CLK_ENA_SHIFT,
0, madera_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD1", 20, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD2", 20, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("MICVDD", 0, SND_SOC_DAPM_REGULATOR_BYPASS),
SND_SOC_DAPM_SUPPLY("MICBIAS1", MADERA_MIC_BIAS_CTRL_1,
MADERA_MICB1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS2", MADERA_MIC_BIAS_CTRL_2,
MADERA_MICB1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS1A", MADERA_MIC_BIAS_CTRL_5,
MADERA_MICB1A_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS1B", MADERA_MIC_BIAS_CTRL_5,
MADERA_MICB1B_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS1C", MADERA_MIC_BIAS_CTRL_5,
MADERA_MICB1C_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS1D", MADERA_MIC_BIAS_CTRL_5,
MADERA_MICB1D_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS2A", MADERA_MIC_BIAS_CTRL_6,
MADERA_MICB2A_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS2B", MADERA_MIC_BIAS_CTRL_6,
MADERA_MICB2B_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("FXCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_FX, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("ASRC1CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_ASRC1, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("ISRC1CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_ISRC1, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("ISRC2CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_ISRC2, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("OUTCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_OUT, 0,
cs47l92_outclk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("SPDCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_SPD, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_DSP1, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("AIF1TXCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_AIF1, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("AIF2TXCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_AIF2, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("AIF3TXCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_AIF3, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("SLIMBUSCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_SLIMBUS, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("PWMCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_PWM, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("DFCCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_DFC, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SIGGEN("TONE"),
SND_SOC_DAPM_SIGGEN("NOISE"),
SND_SOC_DAPM_INPUT("IN1ALN"),
SND_SOC_DAPM_INPUT("IN1ALP"),
SND_SOC_DAPM_INPUT("IN1BLN"),
SND_SOC_DAPM_INPUT("IN1BLP"),
SND_SOC_DAPM_INPUT("IN1ARN"),
SND_SOC_DAPM_INPUT("IN1ARP"),
SND_SOC_DAPM_INPUT("IN1BR"),
SND_SOC_DAPM_INPUT("IN2ALN"),
SND_SOC_DAPM_INPUT("IN2ALP"),
SND_SOC_DAPM_INPUT("IN2BL"),
SND_SOC_DAPM_INPUT("IN2ARN"),
SND_SOC_DAPM_INPUT("IN2ARP"),
SND_SOC_DAPM_INPUT("IN2BR"),
SND_SOC_DAPM_MUX("IN1L Analog Mux", SND_SOC_NOPM, 0, 0, &madera_inmux[0]),
SND_SOC_DAPM_MUX("IN1R Analog Mux", SND_SOC_NOPM, 0, 0, &madera_inmux[1]),
SND_SOC_DAPM_MUX("IN2L Analog Mux", SND_SOC_NOPM, 0, 0, &madera_inmux[2]),
SND_SOC_DAPM_MUX("IN2R Analog Mux", SND_SOC_NOPM, 0, 0, &madera_inmux[3]),
SND_SOC_DAPM_MUX("IN1L Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[0]),
SND_SOC_DAPM_MUX("IN1R Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[0]),
SND_SOC_DAPM_MUX("IN2L Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[1]),
SND_SOC_DAPM_MUX("IN2R Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[1]),
SND_SOC_DAPM_DEMUX("OUT3 Demux", SND_SOC_NOPM, 0, 0, &cs47l92_outdemux),
SND_SOC_DAPM_MUX("OUT3 Mono Mux", SND_SOC_NOPM, 0, 0, &cs47l92_outdemux),
SND_SOC_DAPM_OUTPUT("DRC1 Signal Activity"),
SND_SOC_DAPM_OUTPUT("DRC2 Signal Activity"),
SND_SOC_DAPM_PGA("PWM1 Driver", MADERA_PWM_DRIVE_1, MADERA_PWM1_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA("PWM2 Driver", MADERA_PWM_DRIVE_1, MADERA_PWM2_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 0,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 1,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 2,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 3,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 4,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX6", NULL, 5,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX7", NULL, 6,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX7_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX8", NULL, 7,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX8_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0,
MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX2", NULL, 1,
MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX3", NULL, 2,
MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX4", NULL, 3,
MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX5", NULL, 4,
MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX6", NULL, 5,
MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX7", NULL, 6,
MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX7_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX8", NULL, 7,
MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX8_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX1", NULL, 0,
MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
MADERA_SLIMTX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX2", NULL, 1,
MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
MADERA_SLIMTX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX3", NULL, 2,
MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
MADERA_SLIMTX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX4", NULL, 3,
MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
MADERA_SLIMTX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX5", NULL, 4,
MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
MADERA_SLIMTX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX6", NULL, 5,
MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
MADERA_SLIMTX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX7", NULL, 6,
MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
MADERA_SLIMTX7_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX8", NULL, 7,
MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
MADERA_SLIMTX8_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF3TX1", NULL, 0,
MADERA_AIF3_TX_ENABLES, MADERA_AIF3TX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF3TX2", NULL, 1,
MADERA_AIF3_TX_ENABLES, MADERA_AIF3TX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF3TX3", NULL, 2,
MADERA_AIF3_TX_ENABLES, MADERA_AIF3TX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF3TX4", NULL, 3,
MADERA_AIF3_TX_ENABLES, MADERA_AIF3TX4_ENA_SHIFT, 0),
SND_SOC_DAPM_PGA_E("OUT1L", SND_SOC_NOPM,
MADERA_OUT1L_ENA_SHIFT, 0, NULL, 0, madera_hp_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT1R", SND_SOC_NOPM,
MADERA_OUT1R_ENA_SHIFT, 0, NULL, 0, madera_hp_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT2L", SND_SOC_NOPM,
MADERA_OUT2L_ENA_SHIFT, 0, NULL, 0, madera_hp_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT2R", SND_SOC_NOPM,
MADERA_OUT2R_ENA_SHIFT, 0, NULL, 0, madera_hp_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT3L", MADERA_OUTPUT_ENABLES_1,
MADERA_OUT3L_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT3R", MADERA_OUTPUT_ENABLES_1,
MADERA_OUT3R_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT5L", MADERA_OUTPUT_ENABLES_1,
MADERA_OUT5L_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT5R", MADERA_OUTPUT_ENABLES_1,
MADERA_OUT5R_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA("SPD1TX1", MADERA_SPD1_TX_CONTROL,
MADERA_SPD1_VAL1_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("SPD1TX2", MADERA_SPD1_TX_CONTROL,
MADERA_SPD1_VAL2_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("SPD1", MADERA_SPD1_TX_CONTROL,
MADERA_SPD1_ENA_SHIFT, 0, NULL, 0),
/*
* mux_in widgets : arranged in the order of sources
* specified in MADERA_MIXER_INPUT_ROUTES
*/
SND_SOC_DAPM_PGA("Noise Generator", MADERA_COMFORT_NOISE_GENERATOR,
MADERA_NOISE_GEN_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("Tone Generator 1", MADERA_TONE_GENERATOR_1,
MADERA_TONE1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("Tone Generator 2", MADERA_TONE_GENERATOR_1,
MADERA_TONE2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SIGGEN("HAPTICS"),
SND_SOC_DAPM_MUX("AEC1 Loopback", MADERA_DAC_AEC_CONTROL_1,
MADERA_AEC1_LOOPBACK_ENA_SHIFT, 0,
&cs47l92_aec_loopback_mux),
SND_SOC_DAPM_PGA_E("IN1L", MADERA_INPUT_ENABLES, MADERA_IN1L_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN1R", MADERA_INPUT_ENABLES, MADERA_IN1R_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN2L", MADERA_INPUT_ENABLES, MADERA_IN2L_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN2R", MADERA_INPUT_ENABLES, MADERA_IN2R_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN3L", MADERA_INPUT_ENABLES, MADERA_IN3L_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN3R", MADERA_INPUT_ENABLES, MADERA_IN3R_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN4L", MADERA_INPUT_ENABLES, MADERA_IN4L_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN4R", MADERA_INPUT_ENABLES, MADERA_IN4R_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 0,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 1,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 2,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 3,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 4,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX6", NULL, 5,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX7", NULL, 6,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX7_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX8", NULL, 7,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX8_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0,
MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX2", NULL, 1,
MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX3", NULL, 2,
MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX4", NULL, 3,
MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX5", NULL, 4,
MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX6", NULL, 5,
MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX7", NULL, 6,
MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX7_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX8", NULL, 7,
MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX8_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF3RX1", NULL, 0,
MADERA_AIF3_RX_ENABLES, MADERA_AIF3RX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF3RX2", NULL, 1,
MADERA_AIF3_RX_ENABLES, MADERA_AIF3RX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF3RX3", NULL, 2,
MADERA_AIF3_RX_ENABLES, MADERA_AIF3RX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF3RX4", NULL, 3,
MADERA_AIF3_RX_ENABLES, MADERA_AIF3RX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX1", NULL, 0, MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
MADERA_SLIMRX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX2", NULL, 1, MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
MADERA_SLIMRX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX3", NULL, 2, MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
MADERA_SLIMRX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX4", NULL, 3, MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
MADERA_SLIMRX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX5", NULL, 4, MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
MADERA_SLIMRX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX6", NULL, 5, MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
MADERA_SLIMRX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX7", NULL, 6, MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
MADERA_SLIMRX7_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX8", NULL, 7, MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
MADERA_SLIMRX8_ENA_SHIFT, 0),
SND_SOC_DAPM_PGA("EQ1", MADERA_EQ1_1, MADERA_EQ1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ2", MADERA_EQ2_1, MADERA_EQ2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ3", MADERA_EQ3_1, MADERA_EQ3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ4", MADERA_EQ4_1, MADERA_EQ4_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("DRC1L", MADERA_DRC1_CTRL1, MADERA_DRC1L_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("DRC1R", MADERA_DRC1_CTRL1, MADERA_DRC1R_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("DRC2L", MADERA_DRC2_CTRL1, MADERA_DRC2L_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("DRC2R", MADERA_DRC2_CTRL1, MADERA_DRC2R_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF1", MADERA_HPLPF1_1, MADERA_LHPF1_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF2", MADERA_HPLPF2_1, MADERA_LHPF2_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF3", MADERA_HPLPF3_1, MADERA_LHPF3_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF4", MADERA_HPLPF4_1, MADERA_LHPF4_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("ASRC1IN1L", MADERA_ASRC1_ENABLE,
MADERA_ASRC1_IN1L_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ASRC1IN1R", MADERA_ASRC1_ENABLE,
MADERA_ASRC1_IN1R_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ASRC1IN2L", MADERA_ASRC1_ENABLE,
MADERA_ASRC1_IN2L_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ASRC1IN2R", MADERA_ASRC1_ENABLE,
MADERA_ASRC1_IN2R_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC1", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_DEC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC2", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_DEC2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1INT1", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_INT1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1INT2", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_INT2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2DEC1", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_DEC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2DEC2", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_DEC2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2INT1", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_INT1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2INT2", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_INT2_ENA_SHIFT, 0, NULL, 0),
WM_ADSP2("DSP1", 0, cs47l92_adsp_power_ev),
/* end of ordered widget list */
SND_SOC_DAPM_PGA("DFC1", MADERA_DFC1_CTRL, MADERA_DFC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("DFC2", MADERA_DFC2_CTRL, MADERA_DFC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("DFC3", MADERA_DFC3_CTRL, MADERA_DFC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("DFC4", MADERA_DFC4_CTRL, MADERA_DFC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("DFC5", MADERA_DFC5_CTRL, MADERA_DFC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("DFC6", MADERA_DFC6_CTRL, MADERA_DFC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("DFC7", MADERA_DFC7_CTRL, MADERA_DFC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("DFC8", MADERA_DFC8_CTRL, MADERA_DFC1_ENA_SHIFT, 0, NULL, 0),
MADERA_MIXER_WIDGETS(EQ1, "EQ1"),
MADERA_MIXER_WIDGETS(EQ2, "EQ2"),
MADERA_MIXER_WIDGETS(EQ3, "EQ3"),
MADERA_MIXER_WIDGETS(EQ4, "EQ4"),
MADERA_MIXER_WIDGETS(DRC1L, "DRC1L"),
MADERA_MIXER_WIDGETS(DRC1R, "DRC1R"),
MADERA_MIXER_WIDGETS(DRC2L, "DRC2L"),
MADERA_MIXER_WIDGETS(DRC2R, "DRC2R"),
SND_SOC_DAPM_SWITCH("DRC1 Activity Output", SND_SOC_NOPM, 0, 0,
&madera_drc_activity_output_mux[0]),
SND_SOC_DAPM_SWITCH("DRC2 Activity Output", SND_SOC_NOPM, 0, 0,
&madera_drc_activity_output_mux[1]),
MADERA_MIXER_WIDGETS(LHPF1, "LHPF1"),
MADERA_MIXER_WIDGETS(LHPF2, "LHPF2"),
MADERA_MIXER_WIDGETS(LHPF3, "LHPF3"),
MADERA_MIXER_WIDGETS(LHPF4, "LHPF4"),
MADERA_MIXER_WIDGETS(PWM1, "PWM1"),
MADERA_MIXER_WIDGETS(PWM2, "PWM2"),
MADERA_MIXER_WIDGETS(OUT1L, "HPOUT1L"),
MADERA_MIXER_WIDGETS(OUT1R, "HPOUT1R"),
MADERA_MIXER_WIDGETS(OUT2L, "HPOUT2L"),
MADERA_MIXER_WIDGETS(OUT2R, "HPOUT2R"),
MADERA_MIXER_WIDGETS(OUT3L, "HPOUT3L"),
MADERA_MIXER_WIDGETS(OUT3R, "HPOUT3R"),
MADERA_MIXER_WIDGETS(SPKDAT1L, "SPKDAT1L"),
MADERA_MIXER_WIDGETS(SPKDAT1R, "SPKDAT1R"),
MADERA_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"),
MADERA_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"),
MADERA_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"),
MADERA_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"),
MADERA_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"),
MADERA_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"),
MADERA_MIXER_WIDGETS(AIF1TX7, "AIF1TX7"),
MADERA_MIXER_WIDGETS(AIF1TX8, "AIF1TX8"),
MADERA_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"),
MADERA_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"),
MADERA_MIXER_WIDGETS(AIF2TX3, "AIF2TX3"),
MADERA_MIXER_WIDGETS(AIF2TX4, "AIF2TX4"),
MADERA_MIXER_WIDGETS(AIF2TX5, "AIF2TX5"),
MADERA_MIXER_WIDGETS(AIF2TX6, "AIF2TX6"),
MADERA_MIXER_WIDGETS(AIF2TX7, "AIF2TX7"),
MADERA_MIXER_WIDGETS(AIF2TX8, "AIF2TX8"),
MADERA_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"),
MADERA_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"),
MADERA_MIXER_WIDGETS(AIF3TX3, "AIF3TX3"),
MADERA_MIXER_WIDGETS(AIF3TX4, "AIF3TX4"),
MADERA_MIXER_WIDGETS(SLIMTX1, "SLIMTX1"),
MADERA_MIXER_WIDGETS(SLIMTX2, "SLIMTX2"),
MADERA_MIXER_WIDGETS(SLIMTX3, "SLIMTX3"),
MADERA_MIXER_WIDGETS(SLIMTX4, "SLIMTX4"),
MADERA_MIXER_WIDGETS(SLIMTX5, "SLIMTX5"),
MADERA_MIXER_WIDGETS(SLIMTX6, "SLIMTX6"),
MADERA_MIXER_WIDGETS(SLIMTX7, "SLIMTX7"),
MADERA_MIXER_WIDGETS(SLIMTX8, "SLIMTX8"),
MADERA_MUX_WIDGETS(SPD1TX1, "SPDIFTX1"),
MADERA_MUX_WIDGETS(SPD1TX2, "SPDIFTX2"),
MADERA_MUX_WIDGETS(ASRC1IN1L, "ASRC1IN1L"),
MADERA_MUX_WIDGETS(ASRC1IN1R, "ASRC1IN1R"),
MADERA_MUX_WIDGETS(ASRC1IN2L, "ASRC1IN2L"),
MADERA_MUX_WIDGETS(ASRC1IN2R, "ASRC1IN2R"),
MADERA_DSP_WIDGETS(DSP1, "DSP1"),
MADERA_MUX_WIDGETS(ISRC1DEC1, "ISRC1DEC1"),
MADERA_MUX_WIDGETS(ISRC1DEC2, "ISRC1DEC2"),
MADERA_MUX_WIDGETS(ISRC1INT1, "ISRC1INT1"),
MADERA_MUX_WIDGETS(ISRC1INT2, "ISRC1INT2"),
MADERA_MUX_WIDGETS(ISRC2DEC1, "ISRC2DEC1"),
MADERA_MUX_WIDGETS(ISRC2DEC2, "ISRC2DEC2"),
MADERA_MUX_WIDGETS(ISRC2INT1, "ISRC2INT1"),
MADERA_MUX_WIDGETS(ISRC2INT2, "ISRC2INT2"),
MADERA_MUX_WIDGETS(DFC1, "DFC1"),
MADERA_MUX_WIDGETS(DFC2, "DFC2"),
MADERA_MUX_WIDGETS(DFC3, "DFC3"),
MADERA_MUX_WIDGETS(DFC4, "DFC4"),
MADERA_MUX_WIDGETS(DFC5, "DFC5"),
MADERA_MUX_WIDGETS(DFC6, "DFC6"),
MADERA_MUX_WIDGETS(DFC7, "DFC7"),
MADERA_MUX_WIDGETS(DFC8, "DFC8"),
SND_SOC_DAPM_OUTPUT("HPOUT1L"),
SND_SOC_DAPM_OUTPUT("HPOUT1R"),
SND_SOC_DAPM_OUTPUT("HPOUT2L"),
SND_SOC_DAPM_OUTPUT("HPOUT2R"),
SND_SOC_DAPM_OUTPUT("HPOUT3L"),
SND_SOC_DAPM_OUTPUT("HPOUT3R"),
SND_SOC_DAPM_OUTPUT("HPOUT4L"),
SND_SOC_DAPM_OUTPUT("HPOUT4R"),
SND_SOC_DAPM_OUTPUT("SPKDAT1L"),
SND_SOC_DAPM_OUTPUT("SPKDAT1R"),
SND_SOC_DAPM_OUTPUT("SPDIF1"),
SND_SOC_DAPM_OUTPUT("MICSUPP"),
};
#define MADERA_MIXER_INPUT_ROUTES(name) \
{ name, "Noise Generator", "Noise Generator" }, \
{ name, "Tone Generator 1", "Tone Generator 1" }, \
{ name, "Tone Generator 2", "Tone Generator 2" }, \
{ name, "Haptics", "HAPTICS" }, \
{ name, "AEC1", "AEC1 Loopback" }, \
{ name, "IN1L", "IN1L" }, \
{ name, "IN1R", "IN1R" }, \
{ name, "IN2L", "IN2L" }, \
{ name, "IN2R", "IN2R" }, \
{ name, "IN3L", "IN3L" }, \
{ name, "IN3R", "IN3R" }, \
{ name, "IN4L", "IN4L" }, \
{ name, "IN4R", "IN4R" }, \
{ name, "AIF1RX1", "AIF1RX1" }, \
{ name, "AIF1RX2", "AIF1RX2" }, \
{ name, "AIF1RX3", "AIF1RX3" }, \
{ name, "AIF1RX4", "AIF1RX4" }, \
{ name, "AIF1RX5", "AIF1RX5" }, \
{ name, "AIF1RX6", "AIF1RX6" }, \
{ name, "AIF1RX7", "AIF1RX7" }, \
{ name, "AIF1RX8", "AIF1RX8" }, \
{ name, "AIF2RX1", "AIF2RX1" }, \
{ name, "AIF2RX2", "AIF2RX2" }, \
{ name, "AIF2RX3", "AIF2RX3" }, \
{ name, "AIF2RX4", "AIF2RX4" }, \
{ name, "AIF2RX5", "AIF2RX5" }, \
{ name, "AIF2RX6", "AIF2RX6" }, \
{ name, "AIF2RX7", "AIF2RX7" }, \
{ name, "AIF2RX8", "AIF2RX8" }, \
{ name, "AIF3RX1", "AIF3RX1" }, \
{ name, "AIF3RX2", "AIF3RX2" }, \
{ name, "AIF3RX3", "AIF3RX3" }, \
{ name, "AIF3RX4", "AIF3RX4" }, \
{ name, "SLIMRX1", "SLIMRX1" }, \
{ name, "SLIMRX2", "SLIMRX2" }, \
{ name, "SLIMRX3", "SLIMRX3" }, \
{ name, "SLIMRX4", "SLIMRX4" }, \
{ name, "SLIMRX5", "SLIMRX5" }, \
{ name, "SLIMRX6", "SLIMRX6" }, \
{ name, "SLIMRX7", "SLIMRX7" }, \
{ name, "SLIMRX8", "SLIMRX8" }, \
{ name, "EQ1", "EQ1" }, \
{ name, "EQ2", "EQ2" }, \
{ name, "EQ3", "EQ3" }, \
{ name, "EQ4", "EQ4" }, \
{ name, "DRC1L", "DRC1L" }, \
{ name, "DRC1R", "DRC1R" }, \
{ name, "DRC2L", "DRC2L" }, \
{ name, "DRC2R", "DRC2R" }, \
{ name, "LHPF1", "LHPF1" }, \
{ name, "LHPF2", "LHPF2" }, \
{ name, "LHPF3", "LHPF3" }, \
{ name, "LHPF4", "LHPF4" }, \
{ name, "ASRC1IN1L", "ASRC1IN1L" }, \
{ name, "ASRC1IN1R", "ASRC1IN1R" }, \
{ name, "ASRC1IN2L", "ASRC1IN2L" }, \
{ name, "ASRC1IN2R", "ASRC1IN2R" }, \
{ name, "ISRC1DEC1", "ISRC1DEC1" }, \
{ name, "ISRC1DEC2", "ISRC1DEC2" }, \
{ name, "ISRC1INT1", "ISRC1INT1" }, \
{ name, "ISRC1INT2", "ISRC1INT2" }, \
{ name, "ISRC2DEC1", "ISRC2DEC1" }, \
{ name, "ISRC2DEC2", "ISRC2DEC2" }, \
{ name, "ISRC2INT1", "ISRC2INT1" }, \
{ name, "ISRC2INT2", "ISRC2INT2" }, \
{ name, "DSP1.1", "DSP1" }, \
{ name, "DSP1.2", "DSP1" }, \
{ name, "DSP1.3", "DSP1" }, \
{ name, "DSP1.4", "DSP1" }, \
{ name, "DSP1.5", "DSP1" }, \
{ name, "DSP1.6", "DSP1" }, \
{ name, "DFC1", "DFC1" }, \
{ name, "DFC2", "DFC2" }, \
{ name, "DFC3", "DFC3" }, \
{ name, "DFC4", "DFC4" }, \
{ name, "DFC5", "DFC5" }, \
{ name, "DFC6", "DFC6" }, \
{ name, "DFC7", "DFC7" }, \
{ name, "DFC8", "DFC8" }
static const struct snd_soc_dapm_route cs47l92_dapm_routes[] = {
/* Internal clock domains */
{ "EQ1", NULL, "FXCLK" },
{ "EQ2", NULL, "FXCLK" },
{ "EQ3", NULL, "FXCLK" },
{ "EQ4", NULL, "FXCLK" },
{ "DRC1L", NULL, "FXCLK" },
{ "DRC1R", NULL, "FXCLK" },
{ "DRC2L", NULL, "FXCLK" },
{ "DRC2R", NULL, "FXCLK" },
{ "LHPF1", NULL, "FXCLK" },
{ "LHPF2", NULL, "FXCLK" },
{ "LHPF3", NULL, "FXCLK" },
{ "LHPF4", NULL, "FXCLK" },
{ "PWM1 Mixer", NULL, "PWMCLK" },
{ "PWM2 Mixer", NULL, "PWMCLK" },
{ "OUT1L", NULL, "OUTCLK" },
{ "OUT1R", NULL, "OUTCLK" },
{ "OUT2L", NULL, "OUTCLK" },
{ "OUT2R", NULL, "OUTCLK" },
{ "OUT3L", NULL, "OUTCLK" },
{ "OUT3R", NULL, "OUTCLK" },
{ "OUT5L", NULL, "OUTCLK" },
{ "OUT5R", NULL, "OUTCLK" },
{ "AIF1TX1", NULL, "AIF1TXCLK" },
{ "AIF1TX2", NULL, "AIF1TXCLK" },
{ "AIF1TX3", NULL, "AIF1TXCLK" },
{ "AIF1TX4", NULL, "AIF1TXCLK" },
{ "AIF1TX5", NULL, "AIF1TXCLK" },
{ "AIF1TX6", NULL, "AIF1TXCLK" },
{ "AIF1TX7", NULL, "AIF1TXCLK" },
{ "AIF1TX8", NULL, "AIF1TXCLK" },
{ "AIF2TX1", NULL, "AIF2TXCLK" },
{ "AIF2TX2", NULL, "AIF2TXCLK" },
{ "AIF2TX3", NULL, "AIF2TXCLK" },
{ "AIF2TX4", NULL, "AIF2TXCLK" },
{ "AIF2TX5", NULL, "AIF2TXCLK" },
{ "AIF2TX6", NULL, "AIF2TXCLK" },
{ "AIF2TX7", NULL, "AIF2TXCLK" },
{ "AIF2TX8", NULL, "AIF2TXCLK" },
{ "AIF3TX1", NULL, "AIF3TXCLK" },
{ "AIF3TX2", NULL, "AIF3TXCLK" },
{ "AIF3TX3", NULL, "AIF3TXCLK" },
{ "AIF3TX4", NULL, "AIF3TXCLK" },
{ "SLIMTX1", NULL, "SLIMBUSCLK" },
{ "SLIMTX2", NULL, "SLIMBUSCLK" },
{ "SLIMTX3", NULL, "SLIMBUSCLK" },
{ "SLIMTX4", NULL, "SLIMBUSCLK" },
{ "SLIMTX5", NULL, "SLIMBUSCLK" },
{ "SLIMTX6", NULL, "SLIMBUSCLK" },
{ "SLIMTX7", NULL, "SLIMBUSCLK" },
{ "SLIMTX8", NULL, "SLIMBUSCLK" },
{ "SPD1TX1", NULL, "SPDCLK" },
{ "SPD1TX2", NULL, "SPDCLK" },
{ "DSP1", NULL, "DSP1CLK" },
{ "ISRC1DEC1", NULL, "ISRC1CLK" },
{ "ISRC1DEC2", NULL, "ISRC1CLK" },
{ "ISRC1INT1", NULL, "ISRC1CLK" },
{ "ISRC1INT2", NULL, "ISRC1CLK" },
{ "ISRC2DEC1", NULL, "ISRC2CLK" },
{ "ISRC2DEC2", NULL, "ISRC2CLK" },
{ "ISRC2INT1", NULL, "ISRC2CLK" },
{ "ISRC2INT2", NULL, "ISRC2CLK" },
{ "ASRC1IN1L", NULL, "ASRC1CLK" },
{ "ASRC1IN1R", NULL, "ASRC1CLK" },
{ "ASRC1IN2L", NULL, "ASRC1CLK" },
{ "ASRC1IN2R", NULL, "ASRC1CLK" },
{ "DFC1", NULL, "DFCCLK" },
{ "DFC2", NULL, "DFCCLK" },
{ "DFC3", NULL, "DFCCLK" },
{ "DFC4", NULL, "DFCCLK" },
{ "DFC5", NULL, "DFCCLK" },
{ "DFC6", NULL, "DFCCLK" },
{ "DFC7", NULL, "DFCCLK" },
{ "DFC8", NULL, "DFCCLK" },
{ "OUT1L", NULL, "CPVDD1" },
{ "OUT1L", NULL, "CPVDD2" },
{ "OUT1R", NULL, "CPVDD1" },
{ "OUT1R", NULL, "CPVDD2" },
{ "OUT2L", NULL, "CPVDD1" },
{ "OUT2L", NULL, "CPVDD2" },
{ "OUT2R", NULL, "CPVDD1" },
{ "OUT2R", NULL, "CPVDD2" },
{ "OUT3L", NULL, "CPVDD1" },
{ "OUT3L", NULL, "CPVDD2" },
{ "OUT3R", NULL, "CPVDD1" },
{ "OUT3R", NULL, "CPVDD2" },
{ "OUT1L", NULL, "SYSCLK" },
{ "OUT1R", NULL, "SYSCLK" },
{ "OUT2L", NULL, "SYSCLK" },
{ "OUT2R", NULL, "SYSCLK" },
{ "OUT3L", NULL, "SYSCLK" },
{ "OUT3R", NULL, "SYSCLK" },
{ "OUT5L", NULL, "SYSCLK" },
{ "OUT5R", NULL, "SYSCLK" },
{ "SPD1", NULL, "SYSCLK" },
{ "SPD1", NULL, "SPD1TX1" },
{ "SPD1", NULL, "SPD1TX2" },
{ "IN1L", NULL, "SYSCLK" },
{ "IN1R", NULL, "SYSCLK" },
{ "IN2L", NULL, "SYSCLK" },
{ "IN2R", NULL, "SYSCLK" },
{ "IN3L", NULL, "SYSCLK" },
{ "IN3R", NULL, "SYSCLK" },
{ "IN4L", NULL, "SYSCLK" },
{ "IN4R", NULL, "SYSCLK" },
{ "ASRC1IN1L", NULL, "SYSCLK" },
{ "ASRC1IN1R", NULL, "SYSCLK" },
{ "ASRC1IN2L", NULL, "SYSCLK" },
{ "ASRC1IN2R", NULL, "SYSCLK" },
{ "ASRC1IN1L", NULL, "ASYNCCLK" },
{ "ASRC1IN1R", NULL, "ASYNCCLK" },
{ "ASRC1IN2L", NULL, "ASYNCCLK" },
{ "ASRC1IN2R", NULL, "ASYNCCLK" },
{ "MICBIAS1", NULL, "MICVDD" },
{ "MICBIAS2", NULL, "MICVDD" },
{ "MICBIAS1A", NULL, "MICBIAS1" },
{ "MICBIAS1B", NULL, "MICBIAS1" },
{ "MICBIAS1C", NULL, "MICBIAS1" },
{ "MICBIAS1D", NULL, "MICBIAS1" },
{ "MICBIAS2A", NULL, "MICBIAS2" },
{ "MICBIAS2B", NULL, "MICBIAS2" },
{ "Noise Generator", NULL, "SYSCLK" },
{ "Tone Generator 1", NULL, "SYSCLK" },
{ "Tone Generator 2", NULL, "SYSCLK" },
{ "Noise Generator", NULL, "NOISE" },
{ "Tone Generator 1", NULL, "TONE" },
{ "Tone Generator 2", NULL, "TONE" },
{ "AIF1 Capture", NULL, "AIF1TX1" },
{ "AIF1 Capture", NULL, "AIF1TX2" },
{ "AIF1 Capture", NULL, "AIF1TX3" },
{ "AIF1 Capture", NULL, "AIF1TX4" },
{ "AIF1 Capture", NULL, "AIF1TX5" },
{ "AIF1 Capture", NULL, "AIF1TX6" },
{ "AIF1 Capture", NULL, "AIF1TX7" },
{ "AIF1 Capture", NULL, "AIF1TX8" },
{ "AIF1RX1", NULL, "AIF1 Playback" },
{ "AIF1RX2", NULL, "AIF1 Playback" },
{ "AIF1RX3", NULL, "AIF1 Playback" },
{ "AIF1RX4", NULL, "AIF1 Playback" },
{ "AIF1RX5", NULL, "AIF1 Playback" },
{ "AIF1RX6", NULL, "AIF1 Playback" },
{ "AIF1RX7", NULL, "AIF1 Playback" },
{ "AIF1RX8", NULL, "AIF1 Playback" },
{ "AIF2 Capture", NULL, "AIF2TX1" },
{ "AIF2 Capture", NULL, "AIF2TX2" },
{ "AIF2 Capture", NULL, "AIF2TX3" },
{ "AIF2 Capture", NULL, "AIF2TX4" },
{ "AIF2 Capture", NULL, "AIF2TX5" },
{ "AIF2 Capture", NULL, "AIF2TX6" },
{ "AIF2 Capture", NULL, "AIF2TX7" },
{ "AIF2 Capture", NULL, "AIF2TX8" },
{ "AIF2RX1", NULL, "AIF2 Playback" },
{ "AIF2RX2", NULL, "AIF2 Playback" },
{ "AIF2RX3", NULL, "AIF2 Playback" },
{ "AIF2RX4", NULL, "AIF2 Playback" },
{ "AIF2RX5", NULL, "AIF2 Playback" },
{ "AIF2RX6", NULL, "AIF2 Playback" },
{ "AIF2RX7", NULL, "AIF2 Playback" },
{ "AIF2RX8", NULL, "AIF2 Playback" },
{ "AIF3 Capture", NULL, "AIF3TX1" },
{ "AIF3 Capture", NULL, "AIF3TX2" },
{ "AIF3 Capture", NULL, "AIF3TX3" },
{ "AIF3 Capture", NULL, "AIF3TX4" },
{ "AIF3RX1", NULL, "AIF3 Playback" },
{ "AIF3RX2", NULL, "AIF3 Playback" },
{ "AIF3RX3", NULL, "AIF3 Playback" },
{ "AIF3RX4", NULL, "AIF3 Playback" },
{ "Slim1 Capture", NULL, "SLIMTX1" },
{ "Slim1 Capture", NULL, "SLIMTX2" },
{ "Slim1 Capture", NULL, "SLIMTX3" },
{ "Slim1 Capture", NULL, "SLIMTX4" },
{ "SLIMRX1", NULL, "Slim1 Playback" },
{ "SLIMRX2", NULL, "Slim1 Playback" },
{ "SLIMRX3", NULL, "Slim1 Playback" },
{ "SLIMRX4", NULL, "Slim1 Playback" },
{ "Slim2 Capture", NULL, "SLIMTX5" },
{ "Slim2 Capture", NULL, "SLIMTX6" },
{ "SLIMRX5", NULL, "Slim2 Playback" },
{ "SLIMRX6", NULL, "Slim2 Playback" },
{ "Slim3 Capture", NULL, "SLIMTX7" },
{ "Slim3 Capture", NULL, "SLIMTX8" },
{ "SLIMRX7", NULL, "Slim3 Playback" },
{ "SLIMRX8", NULL, "Slim3 Playback" },
{ "AIF1 Playback", NULL, "SYSCLK" },
{ "AIF2 Playback", NULL, "SYSCLK" },
{ "AIF3 Playback", NULL, "SYSCLK" },
{ "Slim1 Playback", NULL, "SYSCLK" },
{ "Slim2 Playback", NULL, "SYSCLK" },
{ "Slim3 Playback", NULL, "SYSCLK" },
{ "AIF1 Capture", NULL, "SYSCLK" },
{ "AIF2 Capture", NULL, "SYSCLK" },
{ "AIF3 Capture", NULL, "SYSCLK" },
{ "Slim1 Capture", NULL, "SYSCLK" },
{ "Slim2 Capture", NULL, "SYSCLK" },
{ "Slim3 Capture", NULL, "SYSCLK" },
{ "Audio Trace DSP", NULL, "DSP1" },
{ "IN1L Analog Mux", "A", "IN1ALN" },
{ "IN1L Analog Mux", "A", "IN1ALP" },
{ "IN1L Analog Mux", "B", "IN1BLN" },
{ "IN1L Analog Mux", "B", "IN1BLP" },
{ "IN1R Analog Mux", "A", "IN1ARN" },
{ "IN1R Analog Mux", "A", "IN1ARP" },
{ "IN1R Analog Mux", "B", "IN1BR" },
{ "IN1R Analog Mux", "B", "IN1ALN" },
{ "IN1L Mode", "Analog", "IN1L Analog Mux" },
{ "IN1R Mode", "Analog", "IN1R Analog Mux" },
{ "IN1L Mode", "Digital", "IN1ALN" },
{ "IN1L Mode", "Digital", "IN1ALP" },
{ "IN1R Mode", "Digital", "IN1ALN" },
{ "IN1R Mode", "Digital", "IN1ALP" },
{ "IN1L", NULL, "IN1L Mode" },
{ "IN1R", NULL, "IN1R Mode" },
{ "IN2L Analog Mux", "A", "IN2ALN" },
{ "IN2L Analog Mux", "A", "IN2ALP" },
{ "IN2L Analog Mux", "B", "IN2ALN" },
{ "IN2L Analog Mux", "B", "IN2BL" },
{ "IN2R Analog Mux", "A", "IN2ARN" },
{ "IN2R Analog Mux", "A", "IN2ARP" },
{ "IN2R Analog Mux", "B", "IN2ARN" },
{ "IN2R Analog Mux", "B", "IN2BR" },
{ "IN2L Mode", "Analog", "IN2L Analog Mux" },
{ "IN2R Mode", "Analog", "IN2R Analog Mux" },
{ "IN2L Mode", "Digital", "IN2ALN" },
{ "IN2L Mode", "Digital", "IN2ALP" },
{ "IN2R Mode", "Digital", "IN2ALN" },
{ "IN2R Mode", "Digital", "IN2ALP" },
{ "IN2L", NULL, "IN2L Mode" },
{ "IN2R", NULL, "IN2R Mode" },
{ "IN3L", NULL, "IN1ARN" },
{ "IN3L", NULL, "IN1ARP" },
{ "IN3R", NULL, "IN1ARN" },
{ "IN3R", NULL, "IN1ARP" },
{ "IN4L", NULL, "IN2ARN" },
{ "IN4L", NULL, "IN2ARP" },
{ "IN4R", NULL, "IN2ARN" },
{ "IN4R", NULL, "IN2ARP" },
MADERA_MIXER_ROUTES("OUT1L", "HPOUT1L"),
MADERA_MIXER_ROUTES("OUT1R", "HPOUT1R"),
MADERA_MIXER_ROUTES("OUT2L", "HPOUT2L"),
MADERA_MIXER_ROUTES("OUT2R", "HPOUT2R"),
MADERA_MIXER_ROUTES("OUT3L", "HPOUT3L"),
MADERA_MIXER_ROUTES("OUT3R", "HPOUT3R"),
MADERA_MIXER_ROUTES("OUT5L", "SPKDAT1L"),
MADERA_MIXER_ROUTES("OUT5R", "SPKDAT1R"),
MADERA_MIXER_ROUTES("PWM1 Driver", "PWM1"),
MADERA_MIXER_ROUTES("PWM2 Driver", "PWM2"),
MADERA_MIXER_ROUTES("AIF1TX1", "AIF1TX1"),
MADERA_MIXER_ROUTES("AIF1TX2", "AIF1TX2"),
MADERA_MIXER_ROUTES("AIF1TX3", "AIF1TX3"),
MADERA_MIXER_ROUTES("AIF1TX4", "AIF1TX4"),
MADERA_MIXER_ROUTES("AIF1TX5", "AIF1TX5"),
MADERA_MIXER_ROUTES("AIF1TX6", "AIF1TX6"),
MADERA_MIXER_ROUTES("AIF1TX7", "AIF1TX7"),
MADERA_MIXER_ROUTES("AIF1TX8", "AIF1TX8"),
MADERA_MIXER_ROUTES("AIF2TX1", "AIF2TX1"),
MADERA_MIXER_ROUTES("AIF2TX2", "AIF2TX2"),
MADERA_MIXER_ROUTES("AIF2TX3", "AIF2TX3"),
MADERA_MIXER_ROUTES("AIF2TX4", "AIF2TX4"),
MADERA_MIXER_ROUTES("AIF2TX5", "AIF2TX5"),
MADERA_MIXER_ROUTES("AIF2TX6", "AIF2TX6"),
MADERA_MIXER_ROUTES("AIF2TX7", "AIF2TX7"),
MADERA_MIXER_ROUTES("AIF2TX8", "AIF2TX8"),
MADERA_MIXER_ROUTES("AIF3TX1", "AIF3TX1"),
MADERA_MIXER_ROUTES("AIF3TX2", "AIF3TX2"),
MADERA_MIXER_ROUTES("AIF3TX3", "AIF3TX3"),
MADERA_MIXER_ROUTES("AIF3TX4", "AIF3TX4"),
MADERA_MIXER_ROUTES("SLIMTX1", "SLIMTX1"),
MADERA_MIXER_ROUTES("SLIMTX2", "SLIMTX2"),
MADERA_MIXER_ROUTES("SLIMTX3", "SLIMTX3"),
MADERA_MIXER_ROUTES("SLIMTX4", "SLIMTX4"),
MADERA_MIXER_ROUTES("SLIMTX5", "SLIMTX5"),
MADERA_MIXER_ROUTES("SLIMTX6", "SLIMTX6"),
MADERA_MIXER_ROUTES("SLIMTX7", "SLIMTX7"),
MADERA_MIXER_ROUTES("SLIMTX8", "SLIMTX8"),
MADERA_MUX_ROUTES("SPD1TX1", "SPDIFTX1"),
MADERA_MUX_ROUTES("SPD1TX2", "SPDIFTX2"),
MADERA_MIXER_ROUTES("EQ1", "EQ1"),
MADERA_MIXER_ROUTES("EQ2", "EQ2"),
MADERA_MIXER_ROUTES("EQ3", "EQ3"),
MADERA_MIXER_ROUTES("EQ4", "EQ4"),
MADERA_MIXER_ROUTES("DRC1L", "DRC1L"),
MADERA_MIXER_ROUTES("DRC1R", "DRC1R"),
MADERA_MIXER_ROUTES("DRC2L", "DRC2L"),
MADERA_MIXER_ROUTES("DRC2R", "DRC2R"),
MADERA_MIXER_ROUTES("LHPF1", "LHPF1"),
MADERA_MIXER_ROUTES("LHPF2", "LHPF2"),
MADERA_MIXER_ROUTES("LHPF3", "LHPF3"),
MADERA_MIXER_ROUTES("LHPF4", "LHPF4"),
MADERA_MUX_ROUTES("ASRC1IN1L", "ASRC1IN1L"),
MADERA_MUX_ROUTES("ASRC1IN1R", "ASRC1IN1R"),
MADERA_MUX_ROUTES("ASRC1IN2L", "ASRC1IN2L"),
MADERA_MUX_ROUTES("ASRC1IN2R", "ASRC1IN2R"),
MADERA_DSP_ROUTES("DSP1"),
MADERA_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"),
MADERA_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"),
MADERA_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"),
MADERA_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"),
MADERA_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"),
MADERA_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"),
MADERA_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"),
MADERA_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"),
{ "AEC1 Loopback", "HPOUT1L", "OUT1L" },
{ "AEC1 Loopback", "HPOUT1R", "OUT1R" },
{ "HPOUT1L", NULL, "OUT1L" },
{ "HPOUT1R", NULL, "OUT1R" },
{ "AEC1 Loopback", "HPOUT2L", "OUT2L" },
{ "AEC1 Loopback", "HPOUT2R", "OUT2R" },
{ "HPOUT2L", NULL, "OUT2L" },
{ "HPOUT2R", NULL, "OUT2R" },
{ "AEC1 Loopback", "HPOUT3L", "OUT3L" },
{ "AEC1 Loopback", "HPOUT3R", "OUT3R" },
{ "OUT3 Demux", NULL, "OUT3L" },
{ "OUT3 Demux", NULL, "OUT3R" },
{ "OUT3R", NULL, "OUT3 Mono Mux" },
{ "HPOUT3L", "HPOUT3", "OUT3 Demux" },
{ "HPOUT3R", "HPOUT3", "OUT3 Demux" },
{ "HPOUT4L", "HPOUT4", "OUT3 Demux" },
{ "HPOUT4R", "HPOUT4", "OUT3 Demux" },
{ "AEC1 Loopback", "SPKDAT1L", "OUT5L" },
{ "AEC1 Loopback", "SPKDAT1R", "OUT5R" },
{ "SPKDAT1L", NULL, "OUT5L" },
{ "SPKDAT1R", NULL, "OUT5R" },
{ "SPDIF1", NULL, "SPD1" },
{ "MICSUPP", NULL, "SYSCLK" },
{ "DRC1 Signal Activity", NULL, "DRC1 Activity Output" },
{ "DRC2 Signal Activity", NULL, "DRC2 Activity Output" },
{ "DRC1 Activity Output", "Switch", "DRC1L" },
{ "DRC1 Activity Output", "Switch", "DRC1R" },
{ "DRC2 Activity Output", "Switch", "DRC2L" },
{ "DRC2 Activity Output", "Switch", "DRC2R" },
MADERA_MUX_ROUTES("DFC1", "DFC1"),
MADERA_MUX_ROUTES("DFC2", "DFC2"),
MADERA_MUX_ROUTES("DFC3", "DFC3"),
MADERA_MUX_ROUTES("DFC4", "DFC4"),
MADERA_MUX_ROUTES("DFC5", "DFC5"),
MADERA_MUX_ROUTES("DFC6", "DFC6"),
MADERA_MUX_ROUTES("DFC7", "DFC7"),
MADERA_MUX_ROUTES("DFC8", "DFC8"),
};
static int cs47l92_set_fll(struct snd_soc_component *component, int fll_id,
int source, unsigned int fref, unsigned int fout)
{
struct cs47l92 *cs47l92 = snd_soc_component_get_drvdata(component);
switch (fll_id) {
case MADERA_FLL1_REFCLK:
return madera_fllhj_set_refclk(&cs47l92->fll[0], source, fref,
fout);
case MADERA_FLL2_REFCLK:
return madera_fllhj_set_refclk(&cs47l92->fll[1], source, fref,
fout);
default:
return -EINVAL;
}
}
static const struct snd_soc_dai_ops cs47l92_dai_ops = {
.compress_new = snd_soc_new_compress,
};
static struct snd_soc_dai_driver cs47l92_dai[] = {
{
.name = "cs47l92-aif1",
.id = 1,
.base = MADERA_AIF1_BCLK_CTRL,
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 8,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 1,
.channels_max = 8,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &madera_dai_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
{
.name = "cs47l92-aif2",
.id = 2,
.base = MADERA_AIF2_BCLK_CTRL,
.playback = {
.stream_name = "AIF2 Playback",
.channels_min = 1,
.channels_max = 8,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.capture = {
.stream_name = "AIF2 Capture",
.channels_min = 1,
.channels_max = 8,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &madera_dai_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
{
.name = "cs47l92-aif3",
.id = 3,
.base = MADERA_AIF3_BCLK_CTRL,
.playback = {
.stream_name = "AIF3 Playback",
.channels_min = 1,
.channels_max = 4,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.capture = {
.stream_name = "AIF3 Capture",
.channels_min = 1,
.channels_max = 4,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &madera_dai_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
{
.name = "cs47l92-slim1",
.id = 5,
.playback = {
.stream_name = "Slim1 Playback",
.channels_min = 1,
.channels_max = 4,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.capture = {
.stream_name = "Slim1 Capture",
.channels_min = 1,
.channels_max = 4,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &madera_simple_dai_ops,
},
{
.name = "cs47l92-slim2",
.id = 6,
.playback = {
.stream_name = "Slim2 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.capture = {
.stream_name = "Slim2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &madera_simple_dai_ops,
},
{
.name = "cs47l92-slim3",
.id = 7,
.playback = {
.stream_name = "Slim3 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.capture = {
.stream_name = "Slim3 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &madera_simple_dai_ops,
},
{
.name = "cs47l92-cpu-trace",
.capture = {
.stream_name = "Audio Trace CPU",
.channels_min = 1,
.channels_max = 2,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &cs47l92_dai_ops,
},
{
.name = "cs47l92-dsp-trace",
.capture = {
.stream_name = "Audio Trace DSP",
.channels_min = 1,
.channels_max = 2,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
},
};
static int cs47l92_open(struct snd_soc_component *component,
struct snd_compr_stream *stream)
{
struct snd_soc_pcm_runtime *rtd = stream->private_data;
struct cs47l92 *cs47l92 = snd_soc_component_get_drvdata(component);
struct madera_priv *priv = &cs47l92->core;
struct madera *madera = priv->madera;
int n_adsp;
if (strcmp(asoc_rtd_to_codec(rtd, 0)->name, "cs47l92-dsp-trace") == 0) {
n_adsp = 0;
} else {
dev_err(madera->dev,
"No suitable compressed stream for DAI '%s'\n",
asoc_rtd_to_codec(rtd, 0)->name);
return -EINVAL;
}
return wm_adsp_compr_open(&priv->adsp[n_adsp], stream);
}
static irqreturn_t cs47l92_adsp2_irq(int irq, void *data)
{
struct cs47l92 *cs47l92 = data;
struct madera_priv *priv = &cs47l92->core;
struct madera *madera = priv->madera;
int ret;
ret = wm_adsp_compr_handle_irq(&priv->adsp[0]);
if (ret == -ENODEV) {
dev_err(madera->dev, "Spurious compressed data IRQ\n");
return IRQ_NONE;
}
return IRQ_HANDLED;
}
static const struct snd_soc_dapm_route cs47l92_mono_routes[] = {
{ "OUT1R", NULL, "OUT1L" },
{ "OUT2R", NULL, "OUT2L" },
{ "OUT3 Mono Mux", "HPOUT3", "OUT3L" },
{ "OUT3 Mono Mux", "HPOUT4", "OUT3L" },
};
static int cs47l92_component_probe(struct snd_soc_component *component)
{
struct cs47l92 *cs47l92 = snd_soc_component_get_drvdata(component);
struct madera *madera = cs47l92->core.madera;
int ret;
snd_soc_component_init_regmap(component, madera->regmap);
mutex_lock(&madera->dapm_ptr_lock);
madera->dapm = snd_soc_component_get_dapm(component);
mutex_unlock(&madera->dapm_ptr_lock);
ret = madera_init_inputs(component);
if (ret)
return ret;
ret = madera_init_outputs(component, cs47l92_mono_routes,
ARRAY_SIZE(cs47l92_mono_routes),
CS47L92_MONO_OUTPUTS);
if (ret)
return ret;
snd_soc_component_disable_pin(component, "HAPTICS");
ret = snd_soc_add_component_controls(component,
madera_adsp_rate_controls,
CS47L92_NUM_ADSP);
if (ret)
return ret;
return wm_adsp2_component_probe(&cs47l92->core.adsp[0], component);
}
static void cs47l92_component_remove(struct snd_soc_component *component)
{
struct cs47l92 *cs47l92 = snd_soc_component_get_drvdata(component);
struct madera *madera = cs47l92->core.madera;
mutex_lock(&madera->dapm_ptr_lock);
madera->dapm = NULL;
mutex_unlock(&madera->dapm_ptr_lock);
wm_adsp2_component_remove(&cs47l92->core.adsp[0], component);
}
#define CS47L92_DIG_VU 0x0200
static unsigned int cs47l92_digital_vu[] = {
MADERA_DAC_DIGITAL_VOLUME_1L,
MADERA_DAC_DIGITAL_VOLUME_1R,
MADERA_DAC_DIGITAL_VOLUME_2L,
MADERA_DAC_DIGITAL_VOLUME_2R,
MADERA_DAC_DIGITAL_VOLUME_3L,
MADERA_DAC_DIGITAL_VOLUME_3R,
MADERA_DAC_DIGITAL_VOLUME_5L,
MADERA_DAC_DIGITAL_VOLUME_5R,
};
static const struct snd_compress_ops cs47l92_compress_ops = {
.open = &cs47l92_open,
.free = &wm_adsp_compr_free,
.set_params = &wm_adsp_compr_set_params,
.get_caps = &wm_adsp_compr_get_caps,
.trigger = &wm_adsp_compr_trigger,
.pointer = &wm_adsp_compr_pointer,
.copy = &wm_adsp_compr_copy,
};
static const struct snd_soc_component_driver soc_component_dev_cs47l92 = {
.probe = &cs47l92_component_probe,
.remove = &cs47l92_component_remove,
.set_sysclk = &madera_set_sysclk,
.set_pll = &cs47l92_set_fll,
.name = DRV_NAME,
.compress_ops = &cs47l92_compress_ops,
.controls = cs47l92_snd_controls,
.num_controls = ARRAY_SIZE(cs47l92_snd_controls),
.dapm_widgets = cs47l92_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(cs47l92_dapm_widgets),
.dapm_routes = cs47l92_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(cs47l92_dapm_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
static int cs47l92_probe(struct platform_device *pdev)
{
struct madera *madera = dev_get_drvdata(pdev->dev.parent);
struct cs47l92 *cs47l92;
int i, ret;
BUILD_BUG_ON(ARRAY_SIZE(cs47l92_dai) > MADERA_MAX_DAI);
/* quick exit if Madera irqchip driver hasn't completed probe */
if (!madera->irq_dev) {
dev_dbg(&pdev->dev, "irqchip driver not ready\n");
return -EPROBE_DEFER;
}
cs47l92 = devm_kzalloc(&pdev->dev, sizeof(struct cs47l92), GFP_KERNEL);
if (!cs47l92)
return -ENOMEM;
platform_set_drvdata(pdev, cs47l92);
cs47l92->core.madera = madera;
cs47l92->core.dev = &pdev->dev;
cs47l92->core.num_inputs = 8;
ret = madera_core_init(&cs47l92->core);
if (ret)
return ret;
ret = madera_request_irq(madera, MADERA_IRQ_DSP_IRQ1,
"ADSP2 Compressed IRQ", cs47l92_adsp2_irq,
cs47l92);
if (ret != 0) {
dev_err(&pdev->dev, "Failed to request DSP IRQ: %d\n", ret);
goto error_core;
}
ret = madera_set_irq_wake(madera, MADERA_IRQ_DSP_IRQ1, 1);
if (ret)
dev_warn(&pdev->dev, "Failed to set DSP IRQ wake: %d\n", ret);
cs47l92->core.adsp[0].part = "cs47l92";
cs47l92->core.adsp[0].cs_dsp.num = 1;
cs47l92->core.adsp[0].cs_dsp.type = WMFW_ADSP2;
cs47l92->core.adsp[0].cs_dsp.rev = 2;
cs47l92->core.adsp[0].cs_dsp.dev = madera->dev;
cs47l92->core.adsp[0].cs_dsp.regmap = madera->regmap_32bit;
cs47l92->core.adsp[0].cs_dsp.base = MADERA_DSP1_CONFIG_1;
cs47l92->core.adsp[0].cs_dsp.mem = cs47l92_dsp1_regions;
cs47l92->core.adsp[0].cs_dsp.num_mems = ARRAY_SIZE(cs47l92_dsp1_regions);
cs47l92->core.adsp[0].cs_dsp.lock_regions = CS_ADSP2_REGION_1_9;
ret = wm_adsp2_init(&cs47l92->core.adsp[0]);
if (ret != 0)
goto error_dsp_irq;
ret = madera_init_bus_error_irq(&cs47l92->core, 0, wm_adsp2_bus_error);
if (ret != 0)
goto error_adsp;
madera_init_fll(madera, 1, MADERA_FLL1_CONTROL_1 - 1,
&cs47l92->fll[0]);
madera_init_fll(madera, 2, MADERA_FLL2_CONTROL_1 - 1,
&cs47l92->fll[1]);
for (i = 0; i < ARRAY_SIZE(cs47l92_dai); i++)
madera_init_dai(&cs47l92->core, i);
/* Latch volume update bits */
for (i = 0; i < ARRAY_SIZE(cs47l92_digital_vu); i++)
regmap_update_bits(madera->regmap, cs47l92_digital_vu[i],
CS47L92_DIG_VU, CS47L92_DIG_VU);
pm_runtime_enable(&pdev->dev);
pm_runtime_idle(&pdev->dev);
ret = devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_cs47l92,
cs47l92_dai,
ARRAY_SIZE(cs47l92_dai));
if (ret < 0) {
dev_err(&pdev->dev, "Failed to register component: %d\n", ret);
goto error_pm_runtime;
}
return ret;
error_pm_runtime:
pm_runtime_disable(&pdev->dev);
madera_free_bus_error_irq(&cs47l92->core, 0);
error_adsp:
wm_adsp2_remove(&cs47l92->core.adsp[0]);
error_dsp_irq:
madera_set_irq_wake(madera, MADERA_IRQ_DSP_IRQ1, 0);
madera_free_irq(madera, MADERA_IRQ_DSP_IRQ1, cs47l92);
error_core:
madera_core_free(&cs47l92->core);
return ret;
}
static void cs47l92_remove(struct platform_device *pdev)
{
struct cs47l92 *cs47l92 = platform_get_drvdata(pdev);
pm_runtime_disable(&pdev->dev);
madera_free_bus_error_irq(&cs47l92->core, 0);
wm_adsp2_remove(&cs47l92->core.adsp[0]);
madera_set_irq_wake(cs47l92->core.madera, MADERA_IRQ_DSP_IRQ1, 0);
madera_free_irq(cs47l92->core.madera, MADERA_IRQ_DSP_IRQ1, cs47l92);
madera_core_free(&cs47l92->core);
}
static struct platform_driver cs47l92_codec_driver = {
.driver = {
.name = "cs47l92-codec",
},
.probe = &cs47l92_probe,
.remove_new = cs47l92_remove,
};
module_platform_driver(cs47l92_codec_driver);
MODULE_SOFTDEP("pre: madera irq-madera arizona-micsupp");
MODULE_DESCRIPTION("ASoC CS47L92 driver");
MODULE_AUTHOR("Stuart Henderson <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:cs47l92-codec");
| linux-master | sound/soc/codecs/cs47l92.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ADAV801 audio driver
*
* Copyright 2014 Analog Devices Inc.
*/
#include <linux/module.h>
#include <linux/spi/spi.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include "adav80x.h"
static const struct spi_device_id adav80x_spi_id[] = {
{ "adav801", 0 },
{ }
};
MODULE_DEVICE_TABLE(spi, adav80x_spi_id);
static int adav80x_spi_probe(struct spi_device *spi)
{
struct regmap_config config;
config = adav80x_regmap_config;
config.read_flag_mask = 0x01;
return adav80x_bus_probe(&spi->dev, devm_regmap_init_spi(spi, &config));
}
static struct spi_driver adav80x_spi_driver = {
.driver = {
.name = "adav801",
},
.probe = adav80x_spi_probe,
.id_table = adav80x_spi_id,
};
module_spi_driver(adav80x_spi_driver);
MODULE_DESCRIPTION("ASoC ADAV801 driver");
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_AUTHOR("Yi Li <[email protected]>>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/adav801.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// nau8315.c -- NAU8315 ALSA SoC Audio Amplifier Driver
//
// Copyright 2020 Nuvoton Technology Crop.
//
// Author: David Lin <[email protected]>
//
// Based on MAX98357A.c
#include <linux/acpi.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include <sound/soc-dapm.h>
struct nau8315_priv {
struct gpio_desc *enable;
int enpin_switch;
};
static int nau8315_daiops_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct nau8315_priv *nau8315 =
snd_soc_component_get_drvdata(component);
if (!nau8315->enable)
return 0;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
if (nau8315->enpin_switch) {
gpiod_set_value(nau8315->enable, 1);
dev_dbg(component->dev, "set enable to 1");
}
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
gpiod_set_value(nau8315->enable, 0);
dev_dbg(component->dev, "set enable to 0");
break;
}
return 0;
}
static int nau8315_enpin_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct nau8315_priv *nau8315 =
snd_soc_component_get_drvdata(component);
if (event & SND_SOC_DAPM_PRE_PMU)
nau8315->enpin_switch = 1;
else if (event & SND_SOC_DAPM_POST_PMD)
nau8315->enpin_switch = 0;
return 0;
}
static const struct snd_soc_dapm_widget nau8315_dapm_widgets[] = {
SND_SOC_DAPM_OUTPUT("Speaker"),
SND_SOC_DAPM_OUT_DRV_E("EN_Pin", SND_SOC_NOPM, 0, 0, NULL, 0,
nau8315_enpin_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
};
static const struct snd_soc_dapm_route nau8315_dapm_routes[] = {
{"EN_Pin", NULL, "HiFi Playback"},
{"Speaker", NULL, "EN_Pin"},
};
static const struct snd_soc_component_driver nau8315_component_driver = {
.dapm_widgets = nau8315_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(nau8315_dapm_widgets),
.dapm_routes = nau8315_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(nau8315_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct snd_soc_dai_ops nau8315_dai_ops = {
.trigger = nau8315_daiops_trigger,
};
#define NAU8315_RATES SNDRV_PCM_RATE_8000_96000
#define NAU8315_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_3LE)
static struct snd_soc_dai_driver nau8315_dai_driver = {
.name = "nau8315-hifi",
.playback = {
.stream_name = "HiFi Playback",
.formats = NAU8315_FORMATS,
.rates = NAU8315_RATES,
.channels_min = 1,
.channels_max = 2,
},
.ops = &nau8315_dai_ops,
};
static int nau8315_platform_probe(struct platform_device *pdev)
{
struct nau8315_priv *nau8315;
nau8315 = devm_kzalloc(&pdev->dev, sizeof(*nau8315), GFP_KERNEL);
if (!nau8315)
return -ENOMEM;
nau8315->enable = devm_gpiod_get_optional(&pdev->dev,
"enable", GPIOD_OUT_LOW);
if (IS_ERR(nau8315->enable))
return PTR_ERR(nau8315->enable);
dev_set_drvdata(&pdev->dev, nau8315);
return devm_snd_soc_register_component(&pdev->dev,
&nau8315_component_driver,
&nau8315_dai_driver, 1);
}
#ifdef CONFIG_OF
static const struct of_device_id nau8315_device_id[] = {
{ .compatible = "nuvoton,nau8315" },
{ .compatible = "nuvoton,nau8318" },
{}
};
MODULE_DEVICE_TABLE(of, nau8315_device_id);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id nau8315_acpi_match[] = {
{ "NVTN2010", 0 },
{ "NVTN2012", 0},
{},
};
MODULE_DEVICE_TABLE(acpi, nau8315_acpi_match);
#endif
static struct platform_driver nau8315_platform_driver = {
.driver = {
.name = "nau8315",
.of_match_table = of_match_ptr(nau8315_device_id),
.acpi_match_table = ACPI_PTR(nau8315_acpi_match),
},
.probe = nau8315_platform_probe,
};
module_platform_driver(nau8315_platform_driver);
MODULE_DESCRIPTION("ASoC NAU8315 Mono Class-D Amplifier Driver");
MODULE_AUTHOR("David Lin <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/nau8315.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* uda1380.c - Philips UDA1380 ALSA SoC audio driver
*
* Copyright (c) 2007-2009 Philipp Zabel <[email protected]>
*
* Modified by Richard Purdie <[email protected]> to fit into SoC
* codec model.
*
* Copyright (c) 2005 Giorgio Padrin <[email protected]>
* Copyright 2005 Openedhand Ltd.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/slab.h>
#include <linux/errno.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/workqueue.h>
#include <sound/core.h>
#include <sound/control.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <sound/uda1380.h>
#include "uda1380.h"
/* codec private data */
struct uda1380_priv {
struct snd_soc_component *component;
unsigned int dac_clk;
struct work_struct work;
struct i2c_client *i2c;
u16 *reg_cache;
};
/*
* uda1380 register cache
*/
static const u16 uda1380_reg[UDA1380_CACHEREGNUM] = {
0x0502, 0x0000, 0x0000, 0x3f3f,
0x0202, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0xff00, 0x0000, 0x4800,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x8000, 0x0002, 0x0000,
};
static unsigned long uda1380_cache_dirty;
/*
* read uda1380 register cache
*/
static inline unsigned int uda1380_read_reg_cache(struct snd_soc_component *component,
unsigned int reg)
{
struct uda1380_priv *uda1380 = snd_soc_component_get_drvdata(component);
u16 *cache = uda1380->reg_cache;
if (reg == UDA1380_RESET)
return 0;
if (reg >= UDA1380_CACHEREGNUM)
return -1;
return cache[reg];
}
/*
* write uda1380 register cache
*/
static inline void uda1380_write_reg_cache(struct snd_soc_component *component,
u16 reg, unsigned int value)
{
struct uda1380_priv *uda1380 = snd_soc_component_get_drvdata(component);
u16 *cache = uda1380->reg_cache;
if (reg >= UDA1380_CACHEREGNUM)
return;
if ((reg >= 0x10) && (cache[reg] != value))
set_bit(reg - 0x10, &uda1380_cache_dirty);
cache[reg] = value;
}
/*
* write to the UDA1380 register space
*/
static int uda1380_write(struct snd_soc_component *component, unsigned int reg,
unsigned int value)
{
struct uda1380_priv *uda1380 = snd_soc_component_get_drvdata(component);
u8 data[3];
/* data is
* data[0] is register offset
* data[1] is MS byte
* data[2] is LS byte
*/
data[0] = reg;
data[1] = (value & 0xff00) >> 8;
data[2] = value & 0x00ff;
uda1380_write_reg_cache(component, reg, value);
/* the interpolator & decimator regs must only be written when the
* codec DAI is active.
*/
if (!snd_soc_component_active(component) && (reg >= UDA1380_MVOL))
return 0;
pr_debug("uda1380: hw write %x val %x\n", reg, value);
if (i2c_master_send(uda1380->i2c, data, 3) == 3) {
unsigned int val;
i2c_master_send(uda1380->i2c, data, 1);
i2c_master_recv(uda1380->i2c, data, 2);
val = (data[0]<<8) | data[1];
if (val != value) {
pr_debug("uda1380: READ BACK VAL %x\n",
(data[0]<<8) | data[1]);
return -EIO;
}
if (reg >= 0x10)
clear_bit(reg - 0x10, &uda1380_cache_dirty);
return 0;
} else
return -EIO;
}
static void uda1380_sync_cache(struct snd_soc_component *component)
{
struct uda1380_priv *uda1380 = snd_soc_component_get_drvdata(component);
int reg;
u8 data[3];
u16 *cache = uda1380->reg_cache;
/* Sync reg_cache with the hardware */
for (reg = 0; reg < UDA1380_MVOL; reg++) {
data[0] = reg;
data[1] = (cache[reg] & 0xff00) >> 8;
data[2] = cache[reg] & 0x00ff;
if (i2c_master_send(uda1380->i2c, data, 3) != 3)
dev_err(component->dev, "%s: write to reg 0x%x failed\n",
__func__, reg);
}
}
static int uda1380_reset(struct snd_soc_component *component)
{
struct uda1380_platform_data *pdata = component->dev->platform_data;
struct uda1380_priv *uda1380 = snd_soc_component_get_drvdata(component);
if (gpio_is_valid(pdata->gpio_reset)) {
gpio_set_value(pdata->gpio_reset, 1);
mdelay(1);
gpio_set_value(pdata->gpio_reset, 0);
} else {
u8 data[3];
data[0] = UDA1380_RESET;
data[1] = 0;
data[2] = 0;
if (i2c_master_send(uda1380->i2c, data, 3) != 3) {
dev_err(component->dev, "%s: failed\n", __func__);
return -EIO;
}
}
return 0;
}
static void uda1380_flush_work(struct work_struct *work)
{
struct uda1380_priv *uda1380 = container_of(work, struct uda1380_priv, work);
struct snd_soc_component *uda1380_component = uda1380->component;
int bit, reg;
for_each_set_bit(bit, &uda1380_cache_dirty, UDA1380_CACHEREGNUM - 0x10) {
reg = 0x10 + bit;
pr_debug("uda1380: flush reg %x val %x:\n", reg,
uda1380_read_reg_cache(uda1380_component, reg));
uda1380_write(uda1380_component, reg,
uda1380_read_reg_cache(uda1380_component, reg));
clear_bit(bit, &uda1380_cache_dirty);
}
}
/* declarations of ALSA reg_elem_REAL controls */
static const char *uda1380_deemp[] = {
"None",
"32kHz",
"44.1kHz",
"48kHz",
"96kHz",
};
static const char *uda1380_input_sel[] = {
"Line",
"Mic + Line R",
"Line L",
"Mic",
};
static const char *uda1380_output_sel[] = {
"DAC",
"Analog Mixer",
};
static const char *uda1380_spf_mode[] = {
"Flat",
"Minimum1",
"Minimum2",
"Maximum"
};
static const char *uda1380_capture_sel[] = {
"ADC",
"Digital Mixer"
};
static const char *uda1380_sel_ns[] = {
"3rd-order",
"5th-order"
};
static const char *uda1380_mix_control[] = {
"off",
"PCM only",
"before sound processing",
"after sound processing"
};
static const char *uda1380_sdet_setting[] = {
"3200",
"4800",
"9600",
"19200"
};
static const char *uda1380_os_setting[] = {
"single-speed",
"double-speed (no mixing)",
"quad-speed (no mixing)"
};
static const struct soc_enum uda1380_deemp_enum[] = {
SOC_ENUM_SINGLE(UDA1380_DEEMP, 8, ARRAY_SIZE(uda1380_deemp),
uda1380_deemp),
SOC_ENUM_SINGLE(UDA1380_DEEMP, 0, ARRAY_SIZE(uda1380_deemp),
uda1380_deemp),
};
static SOC_ENUM_SINGLE_DECL(uda1380_input_sel_enum,
UDA1380_ADC, 2, uda1380_input_sel); /* SEL_MIC, SEL_LNA */
static SOC_ENUM_SINGLE_DECL(uda1380_output_sel_enum,
UDA1380_PM, 7, uda1380_output_sel); /* R02_EN_AVC */
static SOC_ENUM_SINGLE_DECL(uda1380_spf_enum,
UDA1380_MODE, 14, uda1380_spf_mode); /* M */
static SOC_ENUM_SINGLE_DECL(uda1380_capture_sel_enum,
UDA1380_IFACE, 6, uda1380_capture_sel); /* SEL_SOURCE */
static SOC_ENUM_SINGLE_DECL(uda1380_sel_ns_enum,
UDA1380_MIXER, 14, uda1380_sel_ns); /* SEL_NS */
static SOC_ENUM_SINGLE_DECL(uda1380_mix_enum,
UDA1380_MIXER, 12, uda1380_mix_control); /* MIX, MIX_POS */
static SOC_ENUM_SINGLE_DECL(uda1380_sdet_enum,
UDA1380_MIXER, 4, uda1380_sdet_setting); /* SD_VALUE */
static SOC_ENUM_SINGLE_DECL(uda1380_os_enum,
UDA1380_MIXER, 0, uda1380_os_setting); /* OS */
/*
* from -48 dB in 1.5 dB steps (mute instead of -49.5 dB)
*/
static DECLARE_TLV_DB_SCALE(amix_tlv, -4950, 150, 1);
/*
* from -78 dB in 1 dB steps (3 dB steps, really. LSB are ignored),
* from -66 dB in 0.5 dB steps (2 dB steps, really) and
* from -52 dB in 0.25 dB steps
*/
static const DECLARE_TLV_DB_RANGE(mvol_tlv,
0, 15, TLV_DB_SCALE_ITEM(-8200, 100, 1),
16, 43, TLV_DB_SCALE_ITEM(-6600, 50, 0),
44, 252, TLV_DB_SCALE_ITEM(-5200, 25, 0)
);
/*
* from -72 dB in 1.5 dB steps (6 dB steps really),
* from -66 dB in 0.75 dB steps (3 dB steps really),
* from -60 dB in 0.5 dB steps (2 dB steps really) and
* from -46 dB in 0.25 dB steps
*/
static const DECLARE_TLV_DB_RANGE(vc_tlv,
0, 7, TLV_DB_SCALE_ITEM(-7800, 150, 1),
8, 15, TLV_DB_SCALE_ITEM(-6600, 75, 0),
16, 43, TLV_DB_SCALE_ITEM(-6000, 50, 0),
44, 228, TLV_DB_SCALE_ITEM(-4600, 25, 0)
);
/* from 0 to 6 dB in 2 dB steps if SPF mode != flat */
static DECLARE_TLV_DB_SCALE(tr_tlv, 0, 200, 0);
/* from 0 to 24 dB in 2 dB steps, if SPF mode == maximum, otherwise cuts
* off at 18 dB max) */
static DECLARE_TLV_DB_SCALE(bb_tlv, 0, 200, 0);
/* from -63 to 24 dB in 0.5 dB steps (-128...48) */
static DECLARE_TLV_DB_SCALE(dec_tlv, -6400, 50, 1);
/* from 0 to 24 dB in 3 dB steps */
static DECLARE_TLV_DB_SCALE(pga_tlv, 0, 300, 0);
/* from 0 to 30 dB in 2 dB steps */
static DECLARE_TLV_DB_SCALE(vga_tlv, 0, 200, 0);
static const struct snd_kcontrol_new uda1380_snd_controls[] = {
SOC_DOUBLE_TLV("Analog Mixer Volume", UDA1380_AMIX, 0, 8, 44, 1, amix_tlv), /* AVCR, AVCL */
SOC_DOUBLE_TLV("Master Playback Volume", UDA1380_MVOL, 0, 8, 252, 1, mvol_tlv), /* MVCL, MVCR */
SOC_SINGLE_TLV("ADC Playback Volume", UDA1380_MIXVOL, 8, 228, 1, vc_tlv), /* VC2 */
SOC_SINGLE_TLV("PCM Playback Volume", UDA1380_MIXVOL, 0, 228, 1, vc_tlv), /* VC1 */
SOC_ENUM("Sound Processing Filter", uda1380_spf_enum), /* M */
SOC_DOUBLE_TLV("Tone Control - Treble", UDA1380_MODE, 4, 12, 3, 0, tr_tlv), /* TRL, TRR */
SOC_DOUBLE_TLV("Tone Control - Bass", UDA1380_MODE, 0, 8, 15, 0, bb_tlv), /* BBL, BBR */
/**/ SOC_SINGLE("Master Playback Switch", UDA1380_DEEMP, 14, 1, 1), /* MTM */
SOC_SINGLE("ADC Playback Switch", UDA1380_DEEMP, 11, 1, 1), /* MT2 from decimation filter */
SOC_ENUM("ADC Playback De-emphasis", uda1380_deemp_enum[0]), /* DE2 */
SOC_SINGLE("PCM Playback Switch", UDA1380_DEEMP, 3, 1, 1), /* MT1, from digital data input */
SOC_ENUM("PCM Playback De-emphasis", uda1380_deemp_enum[1]), /* DE1 */
SOC_SINGLE("DAC Polarity inverting Switch", UDA1380_MIXER, 15, 1, 0), /* DA_POL_INV */
SOC_ENUM("Noise Shaper", uda1380_sel_ns_enum), /* SEL_NS */
SOC_ENUM("Digital Mixer Signal Control", uda1380_mix_enum), /* MIX_POS, MIX */
SOC_SINGLE("Silence Detector Switch", UDA1380_MIXER, 6, 1, 0), /* SDET_ON */
SOC_ENUM("Silence Detector Setting", uda1380_sdet_enum), /* SD_VALUE */
SOC_ENUM("Oversampling Input", uda1380_os_enum), /* OS */
SOC_DOUBLE_S8_TLV("ADC Capture Volume", UDA1380_DEC, -128, 48, dec_tlv), /* ML_DEC, MR_DEC */
/**/ SOC_SINGLE("ADC Capture Switch", UDA1380_PGA, 15, 1, 1), /* MT_ADC */
SOC_DOUBLE_TLV("Line Capture Volume", UDA1380_PGA, 0, 8, 8, 0, pga_tlv), /* PGA_GAINCTRLL, PGA_GAINCTRLR */
SOC_SINGLE("ADC Polarity inverting Switch", UDA1380_ADC, 12, 1, 0), /* ADCPOL_INV */
SOC_SINGLE_TLV("Mic Capture Volume", UDA1380_ADC, 8, 15, 0, vga_tlv), /* VGA_CTRL */
SOC_SINGLE("DC Filter Bypass Switch", UDA1380_ADC, 1, 1, 0), /* SKIP_DCFIL (before decimator) */
SOC_SINGLE("DC Filter Enable Switch", UDA1380_ADC, 0, 1, 0), /* EN_DCFIL (at output of decimator) */
SOC_SINGLE("AGC Timing", UDA1380_AGC, 8, 7, 0), /* TODO: enum, see table 62 */
SOC_SINGLE("AGC Target level", UDA1380_AGC, 2, 3, 1), /* AGC_LEVEL */
/* -5.5, -8, -11.5, -14 dBFS */
SOC_SINGLE("AGC Switch", UDA1380_AGC, 0, 1, 0),
};
/* Input mux */
static const struct snd_kcontrol_new uda1380_input_mux_control =
SOC_DAPM_ENUM("Route", uda1380_input_sel_enum);
/* Output mux */
static const struct snd_kcontrol_new uda1380_output_mux_control =
SOC_DAPM_ENUM("Route", uda1380_output_sel_enum);
/* Capture mux */
static const struct snd_kcontrol_new uda1380_capture_mux_control =
SOC_DAPM_ENUM("Route", uda1380_capture_sel_enum);
static const struct snd_soc_dapm_widget uda1380_dapm_widgets[] = {
SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0,
&uda1380_input_mux_control),
SND_SOC_DAPM_MUX("Output Mux", SND_SOC_NOPM, 0, 0,
&uda1380_output_mux_control),
SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0,
&uda1380_capture_mux_control),
SND_SOC_DAPM_PGA("Left PGA", UDA1380_PM, 3, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right PGA", UDA1380_PM, 1, 0, NULL, 0),
SND_SOC_DAPM_PGA("Mic LNA", UDA1380_PM, 4, 0, NULL, 0),
SND_SOC_DAPM_ADC("Left ADC", "Left Capture", UDA1380_PM, 2, 0),
SND_SOC_DAPM_ADC("Right ADC", "Right Capture", UDA1380_PM, 0, 0),
SND_SOC_DAPM_INPUT("VINM"),
SND_SOC_DAPM_INPUT("VINL"),
SND_SOC_DAPM_INPUT("VINR"),
SND_SOC_DAPM_MIXER("Analog Mixer", UDA1380_PM, 6, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("VOUTLHP"),
SND_SOC_DAPM_OUTPUT("VOUTRHP"),
SND_SOC_DAPM_OUTPUT("VOUTL"),
SND_SOC_DAPM_OUTPUT("VOUTR"),
SND_SOC_DAPM_DAC("DAC", "Playback", UDA1380_PM, 10, 0),
SND_SOC_DAPM_PGA("HeadPhone Driver", UDA1380_PM, 13, 0, NULL, 0),
};
static const struct snd_soc_dapm_route uda1380_dapm_routes[] = {
/* output mux */
{"HeadPhone Driver", NULL, "Output Mux"},
{"VOUTR", NULL, "Output Mux"},
{"VOUTL", NULL, "Output Mux"},
{"Analog Mixer", NULL, "VINR"},
{"Analog Mixer", NULL, "VINL"},
{"Analog Mixer", NULL, "DAC"},
{"Output Mux", "DAC", "DAC"},
{"Output Mux", "Analog Mixer", "Analog Mixer"},
/* {"DAC", "Digital Mixer", "I2S" } */
/* headphone driver */
{"VOUTLHP", NULL, "HeadPhone Driver"},
{"VOUTRHP", NULL, "HeadPhone Driver"},
/* input mux */
{"Left ADC", NULL, "Input Mux"},
{"Input Mux", "Mic", "Mic LNA"},
{"Input Mux", "Mic + Line R", "Mic LNA"},
{"Input Mux", "Line L", "Left PGA"},
{"Input Mux", "Line", "Left PGA"},
/* right input */
{"Right ADC", "Mic + Line R", "Right PGA"},
{"Right ADC", "Line", "Right PGA"},
/* inputs */
{"Mic LNA", NULL, "VINM"},
{"Left PGA", NULL, "VINL"},
{"Right PGA", NULL, "VINR"},
};
static int uda1380_set_dai_fmt_both(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
int iface;
/* set up DAI based upon fmt */
iface = uda1380_read_reg_cache(component, UDA1380_IFACE);
iface &= ~(R01_SFORI_MASK | R01_SIM | R01_SFORO_MASK);
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface |= R01_SFORI_I2S | R01_SFORO_I2S;
break;
case SND_SOC_DAIFMT_LSB:
iface |= R01_SFORI_LSB16 | R01_SFORO_LSB16;
break;
case SND_SOC_DAIFMT_MSB:
iface |= R01_SFORI_MSB | R01_SFORO_MSB;
}
/* DATAI is consumer only */
if ((fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) != SND_SOC_DAIFMT_CBC_CFC)
return -EINVAL;
uda1380_write_reg_cache(component, UDA1380_IFACE, iface);
return 0;
}
static int uda1380_set_dai_fmt_playback(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
int iface;
/* set up DAI based upon fmt */
iface = uda1380_read_reg_cache(component, UDA1380_IFACE);
iface &= ~R01_SFORI_MASK;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface |= R01_SFORI_I2S;
break;
case SND_SOC_DAIFMT_LSB:
iface |= R01_SFORI_LSB16;
break;
case SND_SOC_DAIFMT_MSB:
iface |= R01_SFORI_MSB;
}
/* DATAI is consumer only */
if ((fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) != SND_SOC_DAIFMT_CBC_CFC)
return -EINVAL;
uda1380_write(component, UDA1380_IFACE, iface);
return 0;
}
static int uda1380_set_dai_fmt_capture(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
int iface;
/* set up DAI based upon fmt */
iface = uda1380_read_reg_cache(component, UDA1380_IFACE);
iface &= ~(R01_SIM | R01_SFORO_MASK);
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface |= R01_SFORO_I2S;
break;
case SND_SOC_DAIFMT_LSB:
iface |= R01_SFORO_LSB16;
break;
case SND_SOC_DAIFMT_MSB:
iface |= R01_SFORO_MSB;
}
if ((fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) == SND_SOC_DAIFMT_CBP_CFP)
iface |= R01_SIM;
uda1380_write(component, UDA1380_IFACE, iface);
return 0;
}
static int uda1380_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct uda1380_priv *uda1380 = snd_soc_component_get_drvdata(component);
int mixer = uda1380_read_reg_cache(component, UDA1380_MIXER);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
uda1380_write_reg_cache(component, UDA1380_MIXER,
mixer & ~R14_SILENCE);
schedule_work(&uda1380->work);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
uda1380_write_reg_cache(component, UDA1380_MIXER,
mixer | R14_SILENCE);
schedule_work(&uda1380->work);
break;
}
return 0;
}
static int uda1380_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
u16 clk = uda1380_read_reg_cache(component, UDA1380_CLK);
/* set WSPLL power and divider if running from this clock */
if (clk & R00_DAC_CLK) {
int rate = params_rate(params);
u16 pm = uda1380_read_reg_cache(component, UDA1380_PM);
clk &= ~0x3; /* clear SEL_LOOP_DIV */
switch (rate) {
case 6250 ... 12500:
clk |= 0x0;
break;
case 12501 ... 25000:
clk |= 0x1;
break;
case 25001 ... 50000:
clk |= 0x2;
break;
case 50001 ... 100000:
clk |= 0x3;
break;
}
uda1380_write(component, UDA1380_PM, R02_PON_PLL | pm);
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
clk |= R00_EN_DAC | R00_EN_INT;
else
clk |= R00_EN_ADC | R00_EN_DEC;
uda1380_write(component, UDA1380_CLK, clk);
return 0;
}
static void uda1380_pcm_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
u16 clk = uda1380_read_reg_cache(component, UDA1380_CLK);
/* shut down WSPLL power if running from this clock */
if (clk & R00_DAC_CLK) {
u16 pm = uda1380_read_reg_cache(component, UDA1380_PM);
uda1380_write(component, UDA1380_PM, ~R02_PON_PLL & pm);
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
clk &= ~(R00_EN_DAC | R00_EN_INT);
else
clk &= ~(R00_EN_ADC | R00_EN_DEC);
uda1380_write(component, UDA1380_CLK, clk);
}
static int uda1380_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
int pm = uda1380_read_reg_cache(component, UDA1380_PM);
int reg;
struct uda1380_platform_data *pdata = component->dev->platform_data;
switch (level) {
case SND_SOC_BIAS_ON:
case SND_SOC_BIAS_PREPARE:
/* ADC, DAC on */
uda1380_write(component, UDA1380_PM, R02_PON_BIAS | pm);
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
if (gpio_is_valid(pdata->gpio_power)) {
gpio_set_value(pdata->gpio_power, 1);
mdelay(1);
uda1380_reset(component);
}
uda1380_sync_cache(component);
}
uda1380_write(component, UDA1380_PM, 0x0);
break;
case SND_SOC_BIAS_OFF:
if (!gpio_is_valid(pdata->gpio_power))
break;
gpio_set_value(pdata->gpio_power, 0);
/* Mark mixer regs cache dirty to sync them with
* codec regs on power on.
*/
for (reg = UDA1380_MVOL; reg < UDA1380_CACHEREGNUM; reg++)
set_bit(reg - 0x10, &uda1380_cache_dirty);
}
return 0;
}
#define UDA1380_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
static const struct snd_soc_dai_ops uda1380_dai_ops = {
.hw_params = uda1380_pcm_hw_params,
.shutdown = uda1380_pcm_shutdown,
.trigger = uda1380_trigger,
.set_fmt = uda1380_set_dai_fmt_both,
};
static const struct snd_soc_dai_ops uda1380_dai_ops_playback = {
.hw_params = uda1380_pcm_hw_params,
.shutdown = uda1380_pcm_shutdown,
.trigger = uda1380_trigger,
.set_fmt = uda1380_set_dai_fmt_playback,
};
static const struct snd_soc_dai_ops uda1380_dai_ops_capture = {
.hw_params = uda1380_pcm_hw_params,
.shutdown = uda1380_pcm_shutdown,
.trigger = uda1380_trigger,
.set_fmt = uda1380_set_dai_fmt_capture,
};
static struct snd_soc_dai_driver uda1380_dai[] = {
{
.name = "uda1380-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = UDA1380_RATES,
.formats = SNDRV_PCM_FMTBIT_S16_LE,},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = UDA1380_RATES,
.formats = SNDRV_PCM_FMTBIT_S16_LE,},
.ops = &uda1380_dai_ops,
},
{ /* playback only - dual interface */
.name = "uda1380-hifi-playback",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = UDA1380_RATES,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.ops = &uda1380_dai_ops_playback,
},
{ /* capture only - dual interface*/
.name = "uda1380-hifi-capture",
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = UDA1380_RATES,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.ops = &uda1380_dai_ops_capture,
},
};
static int uda1380_probe(struct snd_soc_component *component)
{
struct uda1380_platform_data *pdata =component->dev->platform_data;
struct uda1380_priv *uda1380 = snd_soc_component_get_drvdata(component);
int ret;
uda1380->component = component;
if (!gpio_is_valid(pdata->gpio_power)) {
ret = uda1380_reset(component);
if (ret)
return ret;
}
INIT_WORK(&uda1380->work, uda1380_flush_work);
/* set clock input */
switch (pdata->dac_clk) {
case UDA1380_DAC_CLK_SYSCLK:
uda1380_write_reg_cache(component, UDA1380_CLK, 0);
break;
case UDA1380_DAC_CLK_WSPLL:
uda1380_write_reg_cache(component, UDA1380_CLK,
R00_DAC_CLK);
break;
}
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_uda1380 = {
.probe = uda1380_probe,
.read = uda1380_read_reg_cache,
.write = uda1380_write,
.set_bias_level = uda1380_set_bias_level,
.controls = uda1380_snd_controls,
.num_controls = ARRAY_SIZE(uda1380_snd_controls),
.dapm_widgets = uda1380_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(uda1380_dapm_widgets),
.dapm_routes = uda1380_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(uda1380_dapm_routes),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int uda1380_i2c_probe(struct i2c_client *i2c)
{
struct uda1380_platform_data *pdata = i2c->dev.platform_data;
struct uda1380_priv *uda1380;
int ret;
if (!pdata)
return -EINVAL;
uda1380 = devm_kzalloc(&i2c->dev, sizeof(struct uda1380_priv),
GFP_KERNEL);
if (uda1380 == NULL)
return -ENOMEM;
if (gpio_is_valid(pdata->gpio_reset)) {
ret = devm_gpio_request_one(&i2c->dev, pdata->gpio_reset,
GPIOF_OUT_INIT_LOW, "uda1380 reset");
if (ret)
return ret;
}
if (gpio_is_valid(pdata->gpio_power)) {
ret = devm_gpio_request_one(&i2c->dev, pdata->gpio_power,
GPIOF_OUT_INIT_LOW, "uda1380 power");
if (ret)
return ret;
}
uda1380->reg_cache = devm_kmemdup(&i2c->dev,
uda1380_reg,
ARRAY_SIZE(uda1380_reg) * sizeof(u16),
GFP_KERNEL);
if (!uda1380->reg_cache)
return -ENOMEM;
i2c_set_clientdata(i2c, uda1380);
uda1380->i2c = i2c;
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_uda1380, uda1380_dai, ARRAY_SIZE(uda1380_dai));
return ret;
}
static const struct i2c_device_id uda1380_i2c_id[] = {
{ "uda1380", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, uda1380_i2c_id);
static const struct of_device_id uda1380_of_match[] = {
{ .compatible = "nxp,uda1380", },
{ }
};
MODULE_DEVICE_TABLE(of, uda1380_of_match);
static struct i2c_driver uda1380_i2c_driver = {
.driver = {
.name = "uda1380-codec",
.of_match_table = uda1380_of_match,
},
.probe = uda1380_i2c_probe,
.id_table = uda1380_i2c_id,
};
module_i2c_driver(uda1380_i2c_driver);
MODULE_AUTHOR("Giorgio Padrin");
MODULE_DESCRIPTION("Audio support for codec Philips UDA1380");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/uda1380.c |
// SPDX-License-Identifier: GPL-2.0
//
// rt711.c -- rt711 ALSA SoC audio driver
//
// Copyright(c) 2019 Realtek Semiconductor Corp.
//
//
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm_runtime.h>
#include <linux/pm.h>
#include <linux/soundwire/sdw.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/sdw.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/hda_verbs.h>
#include <sound/jack.h>
#include "rt711.h"
static int rt711_index_write(struct regmap *regmap,
unsigned int nid, unsigned int reg, unsigned int value)
{
int ret;
unsigned int addr = ((RT711_PRIV_INDEX_W_H | nid) << 8) | reg;
ret = regmap_write(regmap, addr, value);
if (ret < 0)
pr_err("Failed to set private value: %06x <= %04x ret=%d\n",
addr, value, ret);
return ret;
}
static int rt711_index_read(struct regmap *regmap,
unsigned int nid, unsigned int reg, unsigned int *value)
{
int ret;
unsigned int addr = ((RT711_PRIV_INDEX_W_H | nid) << 8) | reg;
*value = 0;
ret = regmap_read(regmap, addr, value);
if (ret < 0)
pr_err("Failed to get private value: %06x => %04x ret=%d\n",
addr, *value, ret);
return ret;
}
static int rt711_index_update_bits(struct regmap *regmap, unsigned int nid,
unsigned int reg, unsigned int mask, unsigned int val)
{
unsigned int tmp, orig;
int ret;
ret = rt711_index_read(regmap, nid, reg, &orig);
if (ret < 0)
return ret;
tmp = orig & ~mask;
tmp |= val & mask;
return rt711_index_write(regmap, nid, reg, tmp);
}
static void rt711_reset(struct regmap *regmap)
{
regmap_write(regmap, RT711_FUNC_RESET, 0);
rt711_index_update_bits(regmap, RT711_VENDOR_REG,
RT711_PARA_VERB_CTL, RT711_HIDDEN_REG_SW_RESET,
RT711_HIDDEN_REG_SW_RESET);
}
static int rt711_calibration(struct rt711_priv *rt711)
{
unsigned int val, loop = 0;
struct device *dev;
struct regmap *regmap = rt711->regmap;
int ret = 0;
mutex_lock(&rt711->calibrate_mutex);
regmap_write(rt711->regmap,
RT711_SET_AUDIO_POWER_STATE, AC_PWRST_D0);
dev = regmap_get_device(regmap);
/* Calibration manual mode */
rt711_index_update_bits(regmap, RT711_VENDOR_REG, RT711_FSM_CTL,
0xf, 0x0);
/* trigger */
rt711_index_update_bits(regmap, RT711_VENDOR_CALI,
RT711_DAC_DC_CALI_CTL1, RT711_DAC_DC_CALI_TRIGGER,
RT711_DAC_DC_CALI_TRIGGER);
/* wait for calibration process */
rt711_index_read(regmap, RT711_VENDOR_CALI,
RT711_DAC_DC_CALI_CTL1, &val);
while (val & RT711_DAC_DC_CALI_TRIGGER) {
if (loop >= 500) {
pr_err("%s, calibration time-out!\n",
__func__);
ret = -ETIMEDOUT;
break;
}
loop++;
usleep_range(10000, 11000);
rt711_index_read(regmap, RT711_VENDOR_CALI,
RT711_DAC_DC_CALI_CTL1, &val);
}
/* depop mode */
rt711_index_update_bits(regmap, RT711_VENDOR_REG,
RT711_FSM_CTL, 0xf, RT711_DEPOP_CTL);
regmap_write(rt711->regmap,
RT711_SET_AUDIO_POWER_STATE, AC_PWRST_D3);
mutex_unlock(&rt711->calibrate_mutex);
dev_dbg(dev, "%s calibration complete, ret=%d\n", __func__, ret);
return ret;
}
static unsigned int rt711_button_detect(struct rt711_priv *rt711)
{
unsigned int btn_type = 0, val80, val81;
int ret;
ret = rt711_index_read(rt711->regmap, RT711_VENDOR_REG,
RT711_IRQ_FLAG_TABLE1, &val80);
if (ret < 0)
goto read_error;
ret = rt711_index_read(rt711->regmap, RT711_VENDOR_REG,
RT711_IRQ_FLAG_TABLE2, &val81);
if (ret < 0)
goto read_error;
val80 &= 0x0381;
val81 &= 0xff00;
switch (val80) {
case 0x0200:
case 0x0100:
case 0x0080:
btn_type |= SND_JACK_BTN_0;
break;
case 0x0001:
btn_type |= SND_JACK_BTN_3;
break;
}
switch (val81) {
case 0x8000:
case 0x4000:
case 0x2000:
btn_type |= SND_JACK_BTN_1;
break;
case 0x1000:
case 0x0800:
case 0x0400:
btn_type |= SND_JACK_BTN_2;
break;
case 0x0200:
case 0x0100:
btn_type |= SND_JACK_BTN_3;
break;
}
read_error:
return btn_type;
}
static int rt711_headset_detect(struct rt711_priv *rt711)
{
unsigned int buf, loop = 0;
int ret;
unsigned int jack_status = 0, reg;
ret = rt711_index_read(rt711->regmap, RT711_VENDOR_REG,
RT711_COMBO_JACK_AUTO_CTL2, &buf);
if (ret < 0)
goto io_error;
while (loop < 500 &&
(buf & RT711_COMBOJACK_AUTO_DET_STATUS) == 0) {
loop++;
usleep_range(9000, 10000);
ret = rt711_index_read(rt711->regmap, RT711_VENDOR_REG,
RT711_COMBO_JACK_AUTO_CTL2, &buf);
if (ret < 0)
goto io_error;
reg = RT711_VERB_GET_PIN_SENSE | RT711_HP_OUT;
ret = regmap_read(rt711->regmap, reg, &jack_status);
if (ret < 0)
goto io_error;
if ((jack_status & (1 << 31)) == 0)
goto remove_error;
}
if (loop >= 500)
goto to_error;
if (buf & RT711_COMBOJACK_AUTO_DET_TRS)
rt711->jack_type = SND_JACK_HEADPHONE;
else if ((buf & RT711_COMBOJACK_AUTO_DET_CTIA) ||
(buf & RT711_COMBOJACK_AUTO_DET_OMTP))
rt711->jack_type = SND_JACK_HEADSET;
return 0;
to_error:
ret = -ETIMEDOUT;
pr_err_ratelimited("Time-out error in %s\n", __func__);
return ret;
io_error:
pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret);
return ret;
remove_error:
pr_err_ratelimited("Jack removal in %s\n", __func__);
return -ENODEV;
}
static void rt711_jack_detect_handler(struct work_struct *work)
{
struct rt711_priv *rt711 =
container_of(work, struct rt711_priv, jack_detect_work.work);
int btn_type = 0, ret;
unsigned int jack_status = 0, reg;
if (!rt711->hs_jack)
return;
if (!snd_soc_card_is_instantiated(rt711->component->card))
return;
if (pm_runtime_status_suspended(rt711->slave->dev.parent)) {
dev_dbg(&rt711->slave->dev,
"%s: parent device is pm_runtime_status_suspended, skipping jack detection\n",
__func__);
return;
}
reg = RT711_VERB_GET_PIN_SENSE | RT711_HP_OUT;
ret = regmap_read(rt711->regmap, reg, &jack_status);
if (ret < 0)
goto io_error;
/* pin attached */
if (jack_status & (1 << 31)) {
/* jack in */
if (rt711->jack_type == 0) {
ret = rt711_headset_detect(rt711);
if (ret < 0)
return;
if (rt711->jack_type == SND_JACK_HEADSET)
btn_type = rt711_button_detect(rt711);
} else if (rt711->jack_type == SND_JACK_HEADSET) {
/* jack is already in, report button event */
btn_type = rt711_button_detect(rt711);
}
} else {
/* jack out */
rt711->jack_type = 0;
}
dev_dbg(&rt711->slave->dev,
"in %s, jack_type=0x%x\n", __func__, rt711->jack_type);
dev_dbg(&rt711->slave->dev,
"in %s, btn_type=0x%x\n", __func__, btn_type);
snd_soc_jack_report(rt711->hs_jack, rt711->jack_type | btn_type,
SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3);
if (btn_type) {
/* button released */
snd_soc_jack_report(rt711->hs_jack, rt711->jack_type,
SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3);
mod_delayed_work(system_power_efficient_wq,
&rt711->jack_btn_check_work, msecs_to_jiffies(200));
}
return;
io_error:
pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret);
}
static void rt711_btn_check_handler(struct work_struct *work)
{
struct rt711_priv *rt711 = container_of(work, struct rt711_priv,
jack_btn_check_work.work);
int btn_type = 0, ret;
unsigned int jack_status = 0, reg;
reg = RT711_VERB_GET_PIN_SENSE | RT711_HP_OUT;
ret = regmap_read(rt711->regmap, reg, &jack_status);
if (ret < 0)
goto io_error;
/* pin attached */
if (jack_status & (1 << 31)) {
if (rt711->jack_type == SND_JACK_HEADSET) {
/* jack is already in, report button event */
btn_type = rt711_button_detect(rt711);
}
} else {
rt711->jack_type = 0;
}
/* cbj comparator */
ret = rt711_index_read(rt711->regmap, RT711_VENDOR_REG,
RT711_COMBO_JACK_AUTO_CTL2, ®);
if (ret < 0)
goto io_error;
if ((reg & 0xf0) == 0xf0)
btn_type = 0;
dev_dbg(&rt711->slave->dev,
"%s, btn_type=0x%x\n", __func__, btn_type);
snd_soc_jack_report(rt711->hs_jack, rt711->jack_type | btn_type,
SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3);
if (btn_type) {
/* button released */
snd_soc_jack_report(rt711->hs_jack, rt711->jack_type,
SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3);
mod_delayed_work(system_power_efficient_wq,
&rt711->jack_btn_check_work, msecs_to_jiffies(200));
}
return;
io_error:
pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret);
}
static void rt711_jack_init(struct rt711_priv *rt711)
{
struct snd_soc_dapm_context *dapm =
snd_soc_component_get_dapm(rt711->component);
mutex_lock(&rt711->calibrate_mutex);
/* power on */
if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
regmap_write(rt711->regmap,
RT711_SET_AUDIO_POWER_STATE, AC_PWRST_D0);
if (rt711->hs_jack) {
/* unsolicited response & IRQ control */
regmap_write(rt711->regmap,
RT711_SET_MIC2_UNSOLICITED_ENABLE, 0x82);
regmap_write(rt711->regmap,
RT711_SET_HP_UNSOLICITED_ENABLE, 0x81);
regmap_write(rt711->regmap,
RT711_SET_INLINE_UNSOLICITED_ENABLE, 0x83);
rt711_index_write(rt711->regmap, RT711_VENDOR_REG,
0x10, 0x2420);
rt711_index_write(rt711->regmap, RT711_VENDOR_REG,
0x19, 0x2e11);
switch (rt711->jd_src) {
case RT711_JD1:
/* default settings was already for JD1 */
break;
case RT711_JD2:
rt711_index_update_bits(rt711->regmap, RT711_VENDOR_REG,
RT711_JD_CTL2, RT711_JD2_2PORT_200K_DECODE_HP |
RT711_HP_JD_SEL_JD2,
RT711_JD2_2PORT_200K_DECODE_HP |
RT711_HP_JD_SEL_JD2);
rt711_index_update_bits(rt711->regmap, RT711_VENDOR_REG,
RT711_CC_DET1,
RT711_HP_JD_FINAL_RESULT_CTL_JD12,
RT711_HP_JD_FINAL_RESULT_CTL_JD12);
break;
case RT711_JD2_100K:
rt711_index_update_bits(rt711->regmap, RT711_VENDOR_REG,
RT711_JD_CTL2, RT711_JD2_2PORT_100K_DECODE | RT711_JD2_1PORT_TYPE_DECODE |
RT711_HP_JD_SEL_JD2 | RT711_JD1_2PORT_TYPE_100K_DECODE,
RT711_JD2_2PORT_100K_DECODE_HP | RT711_JD2_1PORT_JD_HP |
RT711_HP_JD_SEL_JD2 | RT711_JD1_2PORT_JD_RESERVED);
rt711_index_update_bits(rt711->regmap, RT711_VENDOR_REG,
RT711_CC_DET1,
RT711_HP_JD_FINAL_RESULT_CTL_JD12,
RT711_HP_JD_FINAL_RESULT_CTL_JD12);
break;
case RT711_JD2_1P8V_1PORT:
rt711_index_update_bits(rt711->regmap, RT711_VENDOR_REG,
RT711_JD_CTL1, RT711_JD2_DIGITAL_JD_MODE_SEL,
RT711_JD2_1_JD_MODE);
rt711_index_update_bits(rt711->regmap, RT711_VENDOR_REG,
RT711_JD_CTL2, RT711_JD2_1PORT_TYPE_DECODE |
RT711_HP_JD_SEL_JD2,
RT711_JD2_1PORT_JD_HP |
RT711_HP_JD_SEL_JD2);
rt711_index_update_bits(rt711->regmap, RT711_VENDOR_REG,
RT711_JD_CTL4, RT711_JD2_PAD_PULL_UP_MASK |
RT711_JD2_MODE_SEL_MASK,
RT711_JD2_PAD_PULL_UP |
RT711_JD2_MODE2_1P8V_1PORT);
rt711_index_update_bits(rt711->regmap, RT711_VENDOR_REG,
RT711_CC_DET1,
RT711_HP_JD_FINAL_RESULT_CTL_JD12,
RT711_HP_JD_FINAL_RESULT_CTL_JD12);
break;
default:
dev_warn(rt711->component->dev, "Wrong JD source\n");
break;
}
dev_dbg(&rt711->slave->dev, "in %s enable\n", __func__);
mod_delayed_work(system_power_efficient_wq,
&rt711->jack_detect_work, msecs_to_jiffies(250));
} else {
regmap_write(rt711->regmap,
RT711_SET_MIC2_UNSOLICITED_ENABLE, 0x00);
regmap_write(rt711->regmap,
RT711_SET_HP_UNSOLICITED_ENABLE, 0x00);
regmap_write(rt711->regmap,
RT711_SET_INLINE_UNSOLICITED_ENABLE, 0x00);
dev_dbg(&rt711->slave->dev, "in %s disable\n", __func__);
}
/* power off */
if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
regmap_write(rt711->regmap,
RT711_SET_AUDIO_POWER_STATE, AC_PWRST_D3);
mutex_unlock(&rt711->calibrate_mutex);
}
static int rt711_set_jack_detect(struct snd_soc_component *component,
struct snd_soc_jack *hs_jack, void *data)
{
struct rt711_priv *rt711 = snd_soc_component_get_drvdata(component);
int ret;
rt711->hs_jack = hs_jack;
/* we can only resume if the device was initialized at least once */
if (!rt711->first_hw_init)
return 0;
ret = pm_runtime_resume_and_get(component->dev);
if (ret < 0) {
if (ret != -EACCES) {
dev_err(component->dev, "%s: failed to resume %d\n", __func__, ret);
return ret;
}
/* pm_runtime not enabled yet */
dev_dbg(component->dev, "%s: skipping jack init for now\n", __func__);
return 0;
}
rt711_jack_init(rt711);
pm_runtime_mark_last_busy(component->dev);
pm_runtime_put_autosuspend(component->dev);
return 0;
}
static void rt711_get_gain(struct rt711_priv *rt711, unsigned int addr_h,
unsigned int addr_l, unsigned int val_h,
unsigned int *r_val, unsigned int *l_val)
{
/* R Channel */
*r_val = (val_h << 8);
regmap_read(rt711->regmap, addr_l, r_val);
/* L Channel */
val_h |= 0x20;
*l_val = (val_h << 8);
regmap_read(rt711->regmap, addr_h, l_val);
}
/* For Verb-Set Amplifier Gain (Verb ID = 3h) */
static int rt711_set_amp_gain_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct snd_soc_dapm_context *dapm =
snd_soc_component_get_dapm(component);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct rt711_priv *rt711 = snd_soc_component_get_drvdata(component);
unsigned int addr_h, addr_l, val_h, val_ll, val_lr;
unsigned int read_ll, read_rl;
int i;
mutex_lock(&rt711->calibrate_mutex);
/* Can't use update bit function, so read the original value first */
addr_h = mc->reg;
addr_l = mc->rreg;
if (mc->shift == RT711_DIR_OUT_SFT) /* output */
val_h = 0x80;
else /* input */
val_h = 0x0;
rt711_get_gain(rt711, addr_h, addr_l, val_h, &read_rl, &read_ll);
/* L Channel */
if (mc->invert) {
/* for mute/unmute */
val_ll = (mc->max - ucontrol->value.integer.value[0])
<< RT711_MUTE_SFT;
/* keep gain */
read_ll = read_ll & 0x7f;
val_ll |= read_ll;
} else {
/* for gain */
val_ll = ((ucontrol->value.integer.value[0]) & 0x7f);
if (val_ll > mc->max)
val_ll = mc->max;
/* keep mute status */
read_ll = read_ll & (1 << RT711_MUTE_SFT);
val_ll |= read_ll;
}
if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
regmap_write(rt711->regmap,
RT711_SET_AUDIO_POWER_STATE, AC_PWRST_D0);
/* R Channel */
if (mc->invert) {
/* for mute/unmute */
val_lr = (mc->max - ucontrol->value.integer.value[1])
<< RT711_MUTE_SFT;
/* keep gain */
read_rl = read_rl & 0x7f;
val_lr |= read_rl;
} else {
/* for gain */
val_lr = ((ucontrol->value.integer.value[1]) & 0x7f);
if (val_lr > mc->max)
val_lr = mc->max;
/* keep mute status */
read_rl = read_rl & (1 << RT711_MUTE_SFT);
val_lr |= read_rl;
}
for (i = 0; i < 3; i++) { /* retry 3 times at most */
if (val_ll == val_lr) {
/* Set both L/R channels at the same time */
val_h = (1 << mc->shift) | (3 << 4);
regmap_write(rt711->regmap,
addr_h, (val_h << 8 | val_ll));
regmap_write(rt711->regmap,
addr_l, (val_h << 8 | val_ll));
} else {
/* Lch*/
val_h = (1 << mc->shift) | (1 << 5);
regmap_write(rt711->regmap,
addr_h, (val_h << 8 | val_ll));
/* Rch */
val_h = (1 << mc->shift) | (1 << 4);
regmap_write(rt711->regmap,
addr_l, (val_h << 8 | val_lr));
}
/* check result */
if (mc->shift == RT711_DIR_OUT_SFT) /* output */
val_h = 0x80;
else /* input */
val_h = 0x0;
rt711_get_gain(rt711, addr_h, addr_l, val_h,
&read_rl, &read_ll);
if (read_rl == val_lr && read_ll == val_ll)
break;
}
if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
regmap_write(rt711->regmap,
RT711_SET_AUDIO_POWER_STATE, AC_PWRST_D3);
mutex_unlock(&rt711->calibrate_mutex);
return 0;
}
static int rt711_set_amp_gain_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt711_priv *rt711 = snd_soc_component_get_drvdata(component);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
unsigned int addr_h, addr_l, val_h;
unsigned int read_ll, read_rl;
/* switch to get command */
addr_h = mc->reg;
addr_l = mc->rreg;
if (mc->shift == RT711_DIR_OUT_SFT) /* output */
val_h = 0x80;
else /* input */
val_h = 0x0;
rt711_get_gain(rt711, addr_h, addr_l, val_h, &read_rl, &read_ll);
if (mc->invert) {
/* mute/unmute for switch controls */
read_ll = !((read_ll & 0x80) >> RT711_MUTE_SFT);
read_rl = !((read_rl & 0x80) >> RT711_MUTE_SFT);
} else {
/* for gain volume controls */
read_ll = read_ll & 0x7f;
read_rl = read_rl & 0x7f;
}
ucontrol->value.integer.value[0] = read_ll;
ucontrol->value.integer.value[1] = read_rl;
return 0;
}
static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0);
static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -1725, 75, 0);
static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
static const struct snd_kcontrol_new rt711_snd_controls[] = {
SOC_DOUBLE_R_EXT_TLV("DAC Surr Playback Volume",
RT711_SET_GAIN_DAC2_H, RT711_SET_GAIN_DAC2_L,
RT711_DIR_OUT_SFT, 0x57, 0,
rt711_set_amp_gain_get, rt711_set_amp_gain_put, out_vol_tlv),
SOC_DOUBLE_R_EXT("ADC 08 Capture Switch",
RT711_SET_GAIN_ADC2_H, RT711_SET_GAIN_ADC2_L,
RT711_DIR_IN_SFT, 1, 1,
rt711_set_amp_gain_get, rt711_set_amp_gain_put),
SOC_DOUBLE_R_EXT("ADC 09 Capture Switch",
RT711_SET_GAIN_ADC1_H, RT711_SET_GAIN_ADC1_L,
RT711_DIR_IN_SFT, 1, 1,
rt711_set_amp_gain_get, rt711_set_amp_gain_put),
SOC_DOUBLE_R_EXT_TLV("ADC 08 Capture Volume",
RT711_SET_GAIN_ADC2_H, RT711_SET_GAIN_ADC2_L,
RT711_DIR_IN_SFT, 0x3f, 0,
rt711_set_amp_gain_get, rt711_set_amp_gain_put, in_vol_tlv),
SOC_DOUBLE_R_EXT_TLV("ADC 09 Capture Volume",
RT711_SET_GAIN_ADC1_H, RT711_SET_GAIN_ADC1_L,
RT711_DIR_IN_SFT, 0x3f, 0,
rt711_set_amp_gain_get, rt711_set_amp_gain_put, in_vol_tlv),
SOC_DOUBLE_R_EXT_TLV("AMIC Volume",
RT711_SET_GAIN_AMIC_H, RT711_SET_GAIN_AMIC_L,
RT711_DIR_IN_SFT, 3, 0,
rt711_set_amp_gain_get, rt711_set_amp_gain_put, mic_vol_tlv),
SOC_DOUBLE_R_EXT_TLV("DMIC1 Volume",
RT711_SET_GAIN_DMIC1_H, RT711_SET_GAIN_DMIC1_L,
RT711_DIR_IN_SFT, 3, 0,
rt711_set_amp_gain_get, rt711_set_amp_gain_put, mic_vol_tlv),
SOC_DOUBLE_R_EXT_TLV("DMIC2 Volume",
RT711_SET_GAIN_DMIC2_H, RT711_SET_GAIN_DMIC2_L,
RT711_DIR_IN_SFT, 3, 0,
rt711_set_amp_gain_get, rt711_set_amp_gain_put, mic_vol_tlv),
};
static int rt711_mux_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_dapm_kcontrol_component(kcontrol);
struct rt711_priv *rt711 = snd_soc_component_get_drvdata(component);
unsigned int reg, val = 0, nid;
int ret;
if (strstr(ucontrol->id.name, "ADC 22 Mux"))
nid = RT711_MIXER_IN1;
else if (strstr(ucontrol->id.name, "ADC 23 Mux"))
nid = RT711_MIXER_IN2;
else
return -EINVAL;
/* vid = 0xf01 */
reg = RT711_VERB_SET_CONNECT_SEL | nid;
ret = regmap_read(rt711->regmap, reg, &val);
if (ret < 0) {
dev_err(component->dev, "%s: sdw read failed: %d\n",
__func__, ret);
return ret;
}
ucontrol->value.enumerated.item[0] = val;
return 0;
}
static int rt711_mux_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_dapm_kcontrol_component(kcontrol);
struct snd_soc_dapm_context *dapm =
snd_soc_dapm_kcontrol_dapm(kcontrol);
struct rt711_priv *rt711 = snd_soc_component_get_drvdata(component);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int *item = ucontrol->value.enumerated.item;
unsigned int val, val2 = 0, change, reg, nid;
int ret;
if (item[0] >= e->items)
return -EINVAL;
if (strstr(ucontrol->id.name, "ADC 22 Mux"))
nid = RT711_MIXER_IN1;
else if (strstr(ucontrol->id.name, "ADC 23 Mux"))
nid = RT711_MIXER_IN2;
else
return -EINVAL;
/* Verb ID = 0x701h */
val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
reg = RT711_VERB_SET_CONNECT_SEL | nid;
ret = regmap_read(rt711->regmap, reg, &val2);
if (ret < 0) {
dev_err(component->dev, "%s: sdw read failed: %d\n",
__func__, ret);
return ret;
}
if (val == val2)
change = 0;
else
change = 1;
if (change) {
reg = RT711_VERB_SET_CONNECT_SEL | nid;
regmap_write(rt711->regmap, reg, val);
}
snd_soc_dapm_mux_update_power(dapm, kcontrol,
item[0], e, NULL);
return change;
}
static const char * const adc_mux_text[] = {
"MIC2",
"LINE1",
"LINE2",
"DMIC",
};
static SOC_ENUM_SINGLE_DECL(
rt711_adc22_enum, SND_SOC_NOPM, 0, adc_mux_text);
static SOC_ENUM_SINGLE_DECL(
rt711_adc23_enum, SND_SOC_NOPM, 0, adc_mux_text);
static const struct snd_kcontrol_new rt711_adc22_mux =
SOC_DAPM_ENUM_EXT("ADC 22 Mux", rt711_adc22_enum,
rt711_mux_get, rt711_mux_put);
static const struct snd_kcontrol_new rt711_adc23_mux =
SOC_DAPM_ENUM_EXT("ADC 23 Mux", rt711_adc23_enum,
rt711_mux_get, rt711_mux_put);
static int rt711_dac_surround_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt711_priv *rt711 = snd_soc_component_get_drvdata(component);
unsigned int val_h = (1 << RT711_DIR_OUT_SFT) | (0x3 << 4);
unsigned int val_l;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_write(rt711->regmap,
RT711_SET_STREAMID_DAC2, 0x10);
val_l = 0x00;
regmap_write(rt711->regmap,
RT711_SET_GAIN_HP_H, (val_h << 8 | val_l));
break;
case SND_SOC_DAPM_PRE_PMD:
val_l = (1 << RT711_MUTE_SFT);
regmap_write(rt711->regmap,
RT711_SET_GAIN_HP_H, (val_h << 8 | val_l));
usleep_range(50000, 55000);
regmap_write(rt711->regmap,
RT711_SET_STREAMID_DAC2, 0x00);
break;
}
return 0;
}
static int rt711_adc_09_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt711_priv *rt711 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_write(rt711->regmap,
RT711_SET_STREAMID_ADC1, 0x10);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_write(rt711->regmap,
RT711_SET_STREAMID_ADC1, 0x00);
break;
}
return 0;
}
static int rt711_adc_08_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt711_priv *rt711 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_write(rt711->regmap,
RT711_SET_STREAMID_ADC2, 0x10);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_write(rt711->regmap,
RT711_SET_STREAMID_ADC2, 0x00);
break;
}
return 0;
}
static const struct snd_soc_dapm_widget rt711_dapm_widgets[] = {
SND_SOC_DAPM_OUTPUT("HP"),
SND_SOC_DAPM_INPUT("MIC2"),
SND_SOC_DAPM_INPUT("DMIC1"),
SND_SOC_DAPM_INPUT("DMIC2"),
SND_SOC_DAPM_INPUT("LINE1"),
SND_SOC_DAPM_INPUT("LINE2"),
SND_SOC_DAPM_DAC_E("DAC Surround", NULL, SND_SOC_NOPM, 0, 0,
rt711_dac_surround_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_ADC_E("ADC 09", NULL, SND_SOC_NOPM, 0, 0,
rt711_adc_09_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_ADC_E("ADC 08", NULL, SND_SOC_NOPM, 0, 0,
rt711_adc_08_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_MUX("ADC 22 Mux", SND_SOC_NOPM, 0, 0,
&rt711_adc22_mux),
SND_SOC_DAPM_MUX("ADC 23 Mux", SND_SOC_NOPM, 0, 0,
&rt711_adc23_mux),
SND_SOC_DAPM_AIF_IN("DP3RX", "DP3 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("DP2TX", "DP2 Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0),
};
static const struct snd_soc_dapm_route rt711_audio_map[] = {
{"DAC Surround", NULL, "DP3RX"},
{"DP2TX", NULL, "ADC 09"},
{"DP4TX", NULL, "ADC 08"},
{"ADC 09", NULL, "ADC 22 Mux"},
{"ADC 08", NULL, "ADC 23 Mux"},
{"ADC 22 Mux", "DMIC", "DMIC1"},
{"ADC 22 Mux", "LINE1", "LINE1"},
{"ADC 22 Mux", "LINE2", "LINE2"},
{"ADC 22 Mux", "MIC2", "MIC2"},
{"ADC 23 Mux", "DMIC", "DMIC2"},
{"ADC 23 Mux", "LINE1", "LINE1"},
{"ADC 23 Mux", "LINE2", "LINE2"},
{"ADC 23 Mux", "MIC2", "MIC2"},
{"HP", NULL, "DAC Surround"},
};
static int rt711_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct snd_soc_dapm_context *dapm =
snd_soc_component_get_dapm(component);
struct rt711_priv *rt711 = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_PREPARE:
if (dapm->bias_level == SND_SOC_BIAS_STANDBY) {
regmap_write(rt711->regmap,
RT711_SET_AUDIO_POWER_STATE,
AC_PWRST_D0);
}
break;
case SND_SOC_BIAS_STANDBY:
mutex_lock(&rt711->calibrate_mutex);
regmap_write(rt711->regmap,
RT711_SET_AUDIO_POWER_STATE,
AC_PWRST_D3);
mutex_unlock(&rt711->calibrate_mutex);
break;
default:
break;
}
return 0;
}
static int rt711_parse_dt(struct rt711_priv *rt711, struct device *dev)
{
device_property_read_u32(dev, "realtek,jd-src",
&rt711->jd_src);
return 0;
}
static int rt711_probe(struct snd_soc_component *component)
{
struct rt711_priv *rt711 = snd_soc_component_get_drvdata(component);
int ret;
rt711_parse_dt(rt711, &rt711->slave->dev);
rt711->component = component;
if (!rt711->first_hw_init)
return 0;
ret = pm_runtime_resume(component->dev);
if (ret < 0 && ret != -EACCES)
return ret;
return 0;
}
static const struct snd_soc_component_driver soc_codec_dev_rt711 = {
.probe = rt711_probe,
.set_bias_level = rt711_set_bias_level,
.controls = rt711_snd_controls,
.num_controls = ARRAY_SIZE(rt711_snd_controls),
.dapm_widgets = rt711_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt711_dapm_widgets),
.dapm_routes = rt711_audio_map,
.num_dapm_routes = ARRAY_SIZE(rt711_audio_map),
.set_jack = rt711_set_jack_detect,
.endianness = 1,
};
static int rt711_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
int direction)
{
snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
return 0;
}
static void rt711_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
snd_soc_dai_set_dma_data(dai, substream, NULL);
}
static int rt711_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt711_priv *rt711 = snd_soc_component_get_drvdata(component);
struct sdw_stream_config stream_config = {0};
struct sdw_port_config port_config = {0};
struct sdw_stream_runtime *sdw_stream;
int retval;
unsigned int val = 0;
dev_dbg(dai->dev, "%s %s", __func__, dai->name);
sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
if (!sdw_stream)
return -EINVAL;
if (!rt711->slave)
return -EINVAL;
/* SoundWire specific configuration */
snd_sdw_params_to_config(substream, params, &stream_config, &port_config);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
port_config.num = 3;
} else {
if (dai->id == RT711_AIF1)
port_config.num = 4;
else if (dai->id == RT711_AIF2)
port_config.num = 2;
else
return -EINVAL;
}
retval = sdw_stream_add_slave(rt711->slave, &stream_config,
&port_config, 1, sdw_stream);
if (retval) {
dev_err(dai->dev, "Unable to configure port\n");
return retval;
}
if (params_channels(params) <= 16) {
/* bit 3:0 Number of Channel */
val |= (params_channels(params) - 1);
} else {
dev_err(component->dev, "Unsupported channels %d\n",
params_channels(params));
return -EINVAL;
}
switch (params_width(params)) {
/* bit 6:4 Bits per Sample */
case 8:
break;
case 16:
val |= (0x1 << 4);
break;
case 20:
val |= (0x2 << 4);
break;
case 24:
val |= (0x3 << 4);
break;
case 32:
val |= (0x4 << 4);
break;
default:
return -EINVAL;
}
/* 48Khz */
regmap_write(rt711->regmap, RT711_DAC_FORMAT_H, val);
regmap_write(rt711->regmap, RT711_ADC1_FORMAT_H, val);
regmap_write(rt711->regmap, RT711_ADC2_FORMAT_H, val);
return retval;
}
static int rt711_pcm_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt711_priv *rt711 = snd_soc_component_get_drvdata(component);
struct sdw_stream_runtime *sdw_stream =
snd_soc_dai_get_dma_data(dai, substream);
if (!rt711->slave)
return -EINVAL;
sdw_stream_remove_slave(rt711->slave, sdw_stream);
return 0;
}
#define RT711_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
#define RT711_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
static const struct snd_soc_dai_ops rt711_ops = {
.hw_params = rt711_pcm_hw_params,
.hw_free = rt711_pcm_hw_free,
.set_stream = rt711_set_sdw_stream,
.shutdown = rt711_shutdown,
};
static struct snd_soc_dai_driver rt711_dai[] = {
{
.name = "rt711-aif1",
.id = RT711_AIF1,
.playback = {
.stream_name = "DP3 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT711_STEREO_RATES,
.formats = RT711_FORMATS,
},
.capture = {
.stream_name = "DP4 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT711_STEREO_RATES,
.formats = RT711_FORMATS,
},
.ops = &rt711_ops,
},
{
.name = "rt711-aif2",
.id = RT711_AIF2,
.capture = {
.stream_name = "DP2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT711_STEREO_RATES,
.formats = RT711_FORMATS,
},
.ops = &rt711_ops,
}
};
/* Bus clock frequency */
#define RT711_CLK_FREQ_9600000HZ 9600000
#define RT711_CLK_FREQ_12000000HZ 12000000
#define RT711_CLK_FREQ_6000000HZ 6000000
#define RT711_CLK_FREQ_4800000HZ 4800000
#define RT711_CLK_FREQ_2400000HZ 2400000
#define RT711_CLK_FREQ_12288000HZ 12288000
int rt711_clock_config(struct device *dev)
{
struct rt711_priv *rt711 = dev_get_drvdata(dev);
unsigned int clk_freq, value;
clk_freq = (rt711->params.curr_dr_freq >> 1);
switch (clk_freq) {
case RT711_CLK_FREQ_12000000HZ:
value = 0x0;
break;
case RT711_CLK_FREQ_6000000HZ:
value = 0x1;
break;
case RT711_CLK_FREQ_9600000HZ:
value = 0x2;
break;
case RT711_CLK_FREQ_4800000HZ:
value = 0x3;
break;
case RT711_CLK_FREQ_2400000HZ:
value = 0x4;
break;
case RT711_CLK_FREQ_12288000HZ:
value = 0x5;
break;
default:
return -EINVAL;
}
regmap_write(rt711->regmap, 0xe0, value);
regmap_write(rt711->regmap, 0xf0, value);
dev_dbg(dev, "%s complete, clk_freq=%d\n", __func__, clk_freq);
return 0;
}
static void rt711_calibration_work(struct work_struct *work)
{
struct rt711_priv *rt711 =
container_of(work, struct rt711_priv, calibration_work);
rt711_calibration(rt711);
}
int rt711_init(struct device *dev, struct regmap *sdw_regmap,
struct regmap *regmap, struct sdw_slave *slave)
{
struct rt711_priv *rt711;
int ret;
rt711 = devm_kzalloc(dev, sizeof(*rt711), GFP_KERNEL);
if (!rt711)
return -ENOMEM;
dev_set_drvdata(dev, rt711);
rt711->slave = slave;
rt711->sdw_regmap = sdw_regmap;
rt711->regmap = regmap;
regcache_cache_only(rt711->regmap, true);
mutex_init(&rt711->calibrate_mutex);
mutex_init(&rt711->disable_irq_lock);
INIT_DELAYED_WORK(&rt711->jack_detect_work, rt711_jack_detect_handler);
INIT_DELAYED_WORK(&rt711->jack_btn_check_work, rt711_btn_check_handler);
INIT_WORK(&rt711->calibration_work, rt711_calibration_work);
/*
* Mark hw_init to false
* HW init will be performed when device reports present
*/
rt711->hw_init = false;
rt711->first_hw_init = false;
/* JD source uses JD2 in default */
rt711->jd_src = RT711_JD2;
ret = devm_snd_soc_register_component(dev,
&soc_codec_dev_rt711,
rt711_dai,
ARRAY_SIZE(rt711_dai));
if (ret < 0)
return ret;
/* set autosuspend parameters */
pm_runtime_set_autosuspend_delay(dev, 3000);
pm_runtime_use_autosuspend(dev);
/* make sure the device does not suspend immediately */
pm_runtime_mark_last_busy(dev);
pm_runtime_enable(dev);
/* important note: the device is NOT tagged as 'active' and will remain
* 'suspended' until the hardware is enumerated/initialized. This is required
* to make sure the ASoC framework use of pm_runtime_get_sync() does not silently
* fail with -EACCESS because of race conditions between card creation and enumeration
*/
dev_dbg(dev, "%s\n", __func__);
return ret;
}
int rt711_io_init(struct device *dev, struct sdw_slave *slave)
{
struct rt711_priv *rt711 = dev_get_drvdata(dev);
rt711->disable_irq = false;
if (rt711->hw_init)
return 0;
regcache_cache_only(rt711->regmap, false);
if (rt711->first_hw_init)
regcache_cache_bypass(rt711->regmap, true);
/*
* PM runtime status is marked as 'active' only when a Slave reports as Attached
*/
if (!rt711->first_hw_init)
/* update count of parent 'active' children */
pm_runtime_set_active(&slave->dev);
pm_runtime_get_noresume(&slave->dev);
rt711_reset(rt711->regmap);
/* power on */
regmap_write(rt711->regmap, RT711_SET_AUDIO_POWER_STATE, AC_PWRST_D0);
/* Set Pin Widget */
regmap_write(rt711->regmap, RT711_SET_PIN_MIC2, 0x25);
regmap_write(rt711->regmap, RT711_SET_PIN_HP, 0xc0);
regmap_write(rt711->regmap, RT711_SET_PIN_DMIC1, 0x20);
regmap_write(rt711->regmap, RT711_SET_PIN_DMIC2, 0x20);
regmap_write(rt711->regmap, RT711_SET_PIN_LINE1, 0x20);
regmap_write(rt711->regmap, RT711_SET_PIN_LINE2, 0x20);
/* Mute HP/ADC1/ADC2 */
regmap_write(rt711->regmap, RT711_SET_GAIN_HP_H, 0xa080);
regmap_write(rt711->regmap, RT711_SET_GAIN_HP_H, 0x9080);
regmap_write(rt711->regmap, RT711_SET_GAIN_ADC2_H, 0x6080);
regmap_write(rt711->regmap, RT711_SET_GAIN_ADC2_H, 0x5080);
regmap_write(rt711->regmap, RT711_SET_GAIN_ADC1_H, 0x6080);
regmap_write(rt711->regmap, RT711_SET_GAIN_ADC1_H, 0x5080);
/* Set Configuration Default */
regmap_write(rt711->regmap, 0x4f12, 0x91);
regmap_write(rt711->regmap, 0x4e12, 0xd6);
regmap_write(rt711->regmap, 0x4d12, 0x11);
regmap_write(rt711->regmap, 0x4c12, 0x20);
regmap_write(rt711->regmap, 0x4f13, 0x91);
regmap_write(rt711->regmap, 0x4e13, 0xd6);
regmap_write(rt711->regmap, 0x4d13, 0x11);
regmap_write(rt711->regmap, 0x4c13, 0x21);
regmap_write(rt711->regmap, 0x4c21, 0xf0);
regmap_write(rt711->regmap, 0x4d21, 0x11);
regmap_write(rt711->regmap, 0x4e21, 0x11);
regmap_write(rt711->regmap, 0x4f21, 0x01);
/* Data port arrangement */
rt711_index_write(rt711->regmap, RT711_VENDOR_REG,
RT711_TX_RX_MUX_CTL, 0x0154);
/* Set index */
rt711_index_write(rt711->regmap, RT711_VENDOR_REG,
RT711_DIGITAL_MISC_CTRL4, 0x201b);
rt711_index_write(rt711->regmap, RT711_VENDOR_REG,
RT711_COMBO_JACK_AUTO_CTL1, 0x5089);
rt711_index_write(rt711->regmap, RT711_VENDOR_REG,
RT711_VREFOUT_CTL, 0x5064);
rt711_index_write(rt711->regmap, RT711_VENDOR_REG,
RT711_INLINE_CMD_CTL, 0xd249);
/* Finish Initial Settings, set power to D3 */
regmap_write(rt711->regmap, RT711_SET_AUDIO_POWER_STATE, AC_PWRST_D3);
if (rt711->first_hw_init)
rt711_calibration(rt711);
else
schedule_work(&rt711->calibration_work);
/*
* if set_jack callback occurred early than io_init,
* we set up the jack detection function now
*/
if (rt711->hs_jack)
rt711_jack_init(rt711);
if (rt711->first_hw_init) {
regcache_cache_bypass(rt711->regmap, false);
regcache_mark_dirty(rt711->regmap);
} else
rt711->first_hw_init = true;
/* Mark Slave initialization complete */
rt711->hw_init = true;
pm_runtime_mark_last_busy(&slave->dev);
pm_runtime_put_autosuspend(&slave->dev);
dev_dbg(&slave->dev, "%s hw_init complete\n", __func__);
return 0;
}
MODULE_DESCRIPTION("ASoC RT711 SDW driver");
MODULE_AUTHOR("Shuming Fan <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/rt711.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8940.c -- WM8940 ALSA Soc Audio driver
*
* Author: Jonathan Cameron <[email protected]>
*
* Based on wm8510.c
* Copyright 2006 Wolfson Microelectronics PLC.
* Author: Liam Girdwood <[email protected]>
*
* Not currently handled:
* Notch filter control
* AUXMode (inverting vs mixer)
* No means to obtain current gain if alc enabled.
* No use made of gpio
* Fast VMID discharge for power down
* Soft Start
* DLR and ALR Swaps not enabled
* Digital Sidetone not supported
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "wm8940.h"
struct wm8940_priv {
unsigned int mclk;
unsigned int fs;
struct regmap *regmap;
};
static bool wm8940_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8940_SOFTRESET:
return true;
default:
return false;
}
}
static bool wm8940_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8940_SOFTRESET:
case WM8940_POWER1:
case WM8940_POWER2:
case WM8940_POWER3:
case WM8940_IFACE:
case WM8940_COMPANDINGCTL:
case WM8940_CLOCK:
case WM8940_ADDCNTRL:
case WM8940_GPIO:
case WM8940_CTLINT:
case WM8940_DAC:
case WM8940_DACVOL:
case WM8940_ADC:
case WM8940_ADCVOL:
case WM8940_NOTCH1:
case WM8940_NOTCH2:
case WM8940_NOTCH3:
case WM8940_NOTCH4:
case WM8940_NOTCH5:
case WM8940_NOTCH6:
case WM8940_NOTCH7:
case WM8940_NOTCH8:
case WM8940_DACLIM1:
case WM8940_DACLIM2:
case WM8940_ALC1:
case WM8940_ALC2:
case WM8940_ALC3:
case WM8940_NOISEGATE:
case WM8940_PLLN:
case WM8940_PLLK1:
case WM8940_PLLK2:
case WM8940_PLLK3:
case WM8940_ALC4:
case WM8940_INPUTCTL:
case WM8940_PGAGAIN:
case WM8940_ADCBOOST:
case WM8940_OUTPUTCTL:
case WM8940_SPKMIX:
case WM8940_SPKVOL:
case WM8940_MONOMIX:
return true;
default:
return false;
}
}
static const struct reg_default wm8940_reg_defaults[] = {
{ 0x1, 0x0000 }, /* Power 1 */
{ 0x2, 0x0000 }, /* Power 2 */
{ 0x3, 0x0000 }, /* Power 3 */
{ 0x4, 0x0010 }, /* Interface Control */
{ 0x5, 0x0000 }, /* Companding Control */
{ 0x6, 0x0140 }, /* Clock Control */
{ 0x7, 0x0000 }, /* Additional Controls */
{ 0x8, 0x0000 }, /* GPIO Control */
{ 0x9, 0x0002 }, /* Auto Increment Control */
{ 0xa, 0x0000 }, /* DAC Control */
{ 0xb, 0x00FF }, /* DAC Volume */
{ 0xe, 0x0100 }, /* ADC Control */
{ 0xf, 0x00FF }, /* ADC Volume */
{ 0x10, 0x0000 }, /* Notch Filter 1 Control 1 */
{ 0x11, 0x0000 }, /* Notch Filter 1 Control 2 */
{ 0x12, 0x0000 }, /* Notch Filter 2 Control 1 */
{ 0x13, 0x0000 }, /* Notch Filter 2 Control 2 */
{ 0x14, 0x0000 }, /* Notch Filter 3 Control 1 */
{ 0x15, 0x0000 }, /* Notch Filter 3 Control 2 */
{ 0x16, 0x0000 }, /* Notch Filter 4 Control 1 */
{ 0x17, 0x0000 }, /* Notch Filter 4 Control 2 */
{ 0x18, 0x0032 }, /* DAC Limit Control 1 */
{ 0x19, 0x0000 }, /* DAC Limit Control 2 */
{ 0x20, 0x0038 }, /* ALC Control 1 */
{ 0x21, 0x000B }, /* ALC Control 2 */
{ 0x22, 0x0032 }, /* ALC Control 3 */
{ 0x23, 0x0000 }, /* Noise Gate */
{ 0x24, 0x0041 }, /* PLLN */
{ 0x25, 0x000C }, /* PLLK1 */
{ 0x26, 0x0093 }, /* PLLK2 */
{ 0x27, 0x00E9 }, /* PLLK3 */
{ 0x2a, 0x0030 }, /* ALC Control 4 */
{ 0x2c, 0x0002 }, /* Input Control */
{ 0x2d, 0x0050 }, /* PGA Gain */
{ 0x2f, 0x0002 }, /* ADC Boost Control */
{ 0x31, 0x0002 }, /* Output Control */
{ 0x32, 0x0000 }, /* Speaker Mixer Control */
{ 0x36, 0x0079 }, /* Speaker Volume */
{ 0x38, 0x0000 }, /* Mono Mixer Control */
};
static const char *wm8940_companding[] = { "Off", "NC", "u-law", "A-law" };
static SOC_ENUM_SINGLE_DECL(wm8940_adc_companding_enum,
WM8940_COMPANDINGCTL, 1, wm8940_companding);
static SOC_ENUM_SINGLE_DECL(wm8940_dac_companding_enum,
WM8940_COMPANDINGCTL, 3, wm8940_companding);
static const char *wm8940_alc_mode_text[] = {"ALC", "Limiter"};
static SOC_ENUM_SINGLE_DECL(wm8940_alc_mode_enum,
WM8940_ALC3, 8, wm8940_alc_mode_text);
static const char *wm8940_mic_bias_level_text[] = {"0.9", "0.65"};
static SOC_ENUM_SINGLE_DECL(wm8940_mic_bias_level_enum,
WM8940_INPUTCTL, 8, wm8940_mic_bias_level_text);
static const char *wm8940_filter_mode_text[] = {"Audio", "Application"};
static SOC_ENUM_SINGLE_DECL(wm8940_filter_mode_enum,
WM8940_ADC, 7, wm8940_filter_mode_text);
static DECLARE_TLV_DB_SCALE(wm8940_spk_vol_tlv, -5700, 100, 1);
static DECLARE_TLV_DB_SCALE(wm8940_att_tlv, -1000, 1000, 0);
static DECLARE_TLV_DB_SCALE(wm8940_pga_vol_tlv, -1200, 75, 0);
static DECLARE_TLV_DB_SCALE(wm8940_alc_min_tlv, -1200, 600, 0);
static DECLARE_TLV_DB_SCALE(wm8940_alc_max_tlv, 675, 600, 0);
static DECLARE_TLV_DB_SCALE(wm8940_alc_tar_tlv, -2250, 50, 0);
static DECLARE_TLV_DB_SCALE(wm8940_lim_boost_tlv, 0, 100, 0);
static DECLARE_TLV_DB_SCALE(wm8940_lim_thresh_tlv, -600, 100, 0);
static DECLARE_TLV_DB_SCALE(wm8940_adc_tlv, -12750, 50, 1);
static DECLARE_TLV_DB_SCALE(wm8940_capture_boost_vol_tlv, 0, 2000, 0);
static const struct snd_kcontrol_new wm8940_snd_controls[] = {
SOC_SINGLE("Digital Loopback Switch", WM8940_COMPANDINGCTL,
6, 1, 0),
SOC_ENUM("DAC Companding", wm8940_dac_companding_enum),
SOC_ENUM("ADC Companding", wm8940_adc_companding_enum),
SOC_ENUM("ALC Mode", wm8940_alc_mode_enum),
SOC_SINGLE("ALC Switch", WM8940_ALC1, 8, 1, 0),
SOC_SINGLE_TLV("ALC Capture Max Gain", WM8940_ALC1,
3, 7, 1, wm8940_alc_max_tlv),
SOC_SINGLE_TLV("ALC Capture Min Gain", WM8940_ALC1,
0, 7, 0, wm8940_alc_min_tlv),
SOC_SINGLE_TLV("ALC Capture Target", WM8940_ALC2,
0, 14, 0, wm8940_alc_tar_tlv),
SOC_SINGLE("ALC Capture Hold", WM8940_ALC2, 4, 10, 0),
SOC_SINGLE("ALC Capture Decay", WM8940_ALC3, 4, 10, 0),
SOC_SINGLE("ALC Capture Attach", WM8940_ALC3, 0, 10, 0),
SOC_SINGLE("ALC ZC Switch", WM8940_ALC4, 1, 1, 0),
SOC_SINGLE("ALC Capture Noise Gate Switch", WM8940_NOISEGATE,
3, 1, 0),
SOC_SINGLE("ALC Capture Noise Gate Threshold", WM8940_NOISEGATE,
0, 7, 0),
SOC_SINGLE("DAC Playback Limiter Switch", WM8940_DACLIM1, 8, 1, 0),
SOC_SINGLE("DAC Playback Limiter Attack", WM8940_DACLIM1, 0, 9, 0),
SOC_SINGLE("DAC Playback Limiter Decay", WM8940_DACLIM1, 4, 11, 0),
SOC_SINGLE_TLV("DAC Playback Limiter Threshold", WM8940_DACLIM2,
4, 9, 1, wm8940_lim_thresh_tlv),
SOC_SINGLE_TLV("DAC Playback Limiter Boost", WM8940_DACLIM2,
0, 12, 0, wm8940_lim_boost_tlv),
SOC_SINGLE("Capture PGA ZC Switch", WM8940_PGAGAIN, 7, 1, 0),
SOC_SINGLE_TLV("Capture PGA Volume", WM8940_PGAGAIN,
0, 63, 0, wm8940_pga_vol_tlv),
SOC_SINGLE_TLV("Digital Playback Volume", WM8940_DACVOL,
0, 255, 0, wm8940_adc_tlv),
SOC_SINGLE_TLV("Digital Capture Volume", WM8940_ADCVOL,
0, 255, 0, wm8940_adc_tlv),
SOC_ENUM("Mic Bias Level", wm8940_mic_bias_level_enum),
SOC_SINGLE_TLV("Capture Boost Volue", WM8940_ADCBOOST,
8, 1, 0, wm8940_capture_boost_vol_tlv),
SOC_SINGLE_TLV("Speaker Playback Volume", WM8940_SPKVOL,
0, 63, 0, wm8940_spk_vol_tlv),
SOC_SINGLE("Speaker Playback Switch", WM8940_SPKVOL, 6, 1, 1),
SOC_SINGLE_TLV("Speaker Mixer Line Bypass Volume", WM8940_SPKVOL,
8, 1, 1, wm8940_att_tlv),
SOC_SINGLE("Speaker Playback ZC Switch", WM8940_SPKVOL, 7, 1, 0),
SOC_SINGLE("Mono Out Switch", WM8940_MONOMIX, 6, 1, 1),
SOC_SINGLE_TLV("Mono Mixer Line Bypass Volume", WM8940_MONOMIX,
7, 1, 1, wm8940_att_tlv),
SOC_SINGLE("High Pass Filter Switch", WM8940_ADC, 8, 1, 0),
SOC_ENUM("High Pass Filter Mode", wm8940_filter_mode_enum),
SOC_SINGLE("High Pass Filter Cut Off", WM8940_ADC, 4, 7, 0),
SOC_SINGLE("ADC Inversion Switch", WM8940_ADC, 0, 1, 0),
SOC_SINGLE("DAC Inversion Switch", WM8940_DAC, 0, 1, 0),
SOC_SINGLE("DAC Auto Mute Switch", WM8940_DAC, 2, 1, 0),
SOC_SINGLE("ZC Timeout Clock Switch", WM8940_ADDCNTRL, 0, 1, 0),
};
static const struct snd_kcontrol_new wm8940_speaker_mixer_controls[] = {
SOC_DAPM_SINGLE("Line Bypass Switch", WM8940_SPKMIX, 1, 1, 0),
SOC_DAPM_SINGLE("Aux Playback Switch", WM8940_SPKMIX, 5, 1, 0),
SOC_DAPM_SINGLE("PCM Playback Switch", WM8940_SPKMIX, 0, 1, 0),
};
static const struct snd_kcontrol_new wm8940_mono_mixer_controls[] = {
SOC_DAPM_SINGLE("Line Bypass Switch", WM8940_MONOMIX, 1, 1, 0),
SOC_DAPM_SINGLE("Aux Playback Switch", WM8940_MONOMIX, 2, 1, 0),
SOC_DAPM_SINGLE("PCM Playback Switch", WM8940_MONOMIX, 0, 1, 0),
};
static DECLARE_TLV_DB_SCALE(wm8940_boost_vol_tlv, -1500, 300, 1);
static const struct snd_kcontrol_new wm8940_input_boost_controls[] = {
SOC_DAPM_SINGLE("Mic PGA Switch", WM8940_PGAGAIN, 6, 1, 1),
SOC_DAPM_SINGLE_TLV("Aux Volume", WM8940_ADCBOOST,
0, 7, 0, wm8940_boost_vol_tlv),
SOC_DAPM_SINGLE_TLV("Mic Volume", WM8940_ADCBOOST,
4, 7, 0, wm8940_boost_vol_tlv),
};
static const struct snd_kcontrol_new wm8940_micpga_controls[] = {
SOC_DAPM_SINGLE("AUX Switch", WM8940_INPUTCTL, 2, 1, 0),
SOC_DAPM_SINGLE("MICP Switch", WM8940_INPUTCTL, 0, 1, 0),
SOC_DAPM_SINGLE("MICN Switch", WM8940_INPUTCTL, 1, 1, 0),
};
static const struct snd_soc_dapm_widget wm8940_dapm_widgets[] = {
SND_SOC_DAPM_MIXER("Speaker Mixer", WM8940_POWER3, 2, 0,
&wm8940_speaker_mixer_controls[0],
ARRAY_SIZE(wm8940_speaker_mixer_controls)),
SND_SOC_DAPM_MIXER("Mono Mixer", WM8940_POWER3, 3, 0,
&wm8940_mono_mixer_controls[0],
ARRAY_SIZE(wm8940_mono_mixer_controls)),
SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM8940_POWER3, 0, 0),
SND_SOC_DAPM_PGA("SpkN Out", WM8940_POWER3, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA("SpkP Out", WM8940_POWER3, 6, 0, NULL, 0),
SND_SOC_DAPM_PGA("Mono Out", WM8940_POWER3, 7, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("MONOOUT"),
SND_SOC_DAPM_OUTPUT("SPKOUTP"),
SND_SOC_DAPM_OUTPUT("SPKOUTN"),
SND_SOC_DAPM_PGA("Aux Input", WM8940_POWER1, 6, 0, NULL, 0),
SND_SOC_DAPM_ADC("ADC", "HiFi Capture", WM8940_POWER2, 0, 0),
SND_SOC_DAPM_MIXER("Mic PGA", WM8940_POWER2, 2, 0,
&wm8940_micpga_controls[0],
ARRAY_SIZE(wm8940_micpga_controls)),
SND_SOC_DAPM_MIXER("Boost Mixer", WM8940_POWER2, 4, 0,
&wm8940_input_boost_controls[0],
ARRAY_SIZE(wm8940_input_boost_controls)),
SND_SOC_DAPM_MICBIAS("Mic Bias", WM8940_POWER1, 4, 0),
SND_SOC_DAPM_INPUT("MICN"),
SND_SOC_DAPM_INPUT("MICP"),
SND_SOC_DAPM_INPUT("AUX"),
};
static const struct snd_soc_dapm_route wm8940_dapm_routes[] = {
/* Mono output mixer */
{"Mono Mixer", "PCM Playback Switch", "DAC"},
{"Mono Mixer", "Aux Playback Switch", "Aux Input"},
{"Mono Mixer", "Line Bypass Switch", "Boost Mixer"},
/* Speaker output mixer */
{"Speaker Mixer", "PCM Playback Switch", "DAC"},
{"Speaker Mixer", "Aux Playback Switch", "Aux Input"},
{"Speaker Mixer", "Line Bypass Switch", "Boost Mixer"},
/* Outputs */
{"Mono Out", NULL, "Mono Mixer"},
{"MONOOUT", NULL, "Mono Out"},
{"SpkN Out", NULL, "Speaker Mixer"},
{"SpkP Out", NULL, "Speaker Mixer"},
{"SPKOUTN", NULL, "SpkN Out"},
{"SPKOUTP", NULL, "SpkP Out"},
/* Microphone PGA */
{"Mic PGA", "MICN Switch", "MICN"},
{"Mic PGA", "MICP Switch", "MICP"},
{"Mic PGA", "AUX Switch", "AUX"},
/* Boost Mixer */
{"Boost Mixer", "Mic PGA Switch", "Mic PGA"},
{"Boost Mixer", "Mic Volume", "MICP"},
{"Boost Mixer", "Aux Volume", "Aux Input"},
{"ADC", NULL, "Boost Mixer"},
};
#define wm8940_reset(c) snd_soc_component_write(c, WM8940_SOFTRESET, 0);
static int wm8940_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
u16 iface = snd_soc_component_read(component, WM8940_IFACE) & 0xFE67;
u16 clk = snd_soc_component_read(component, WM8940_CLOCK) & 0x1fe;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
clk |= 1;
break;
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, WM8940_CLOCK, clk);
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface |= (2 << 3);
break;
case SND_SOC_DAIFMT_LEFT_J:
iface |= (1 << 3);
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_DSP_A:
iface |= (3 << 3);
break;
case SND_SOC_DAIFMT_DSP_B:
iface |= (3 << 3) | (1 << 7);
break;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_NB_IF:
iface |= (1 << 7);
break;
case SND_SOC_DAIFMT_IB_NF:
iface |= (1 << 8);
break;
case SND_SOC_DAIFMT_IB_IF:
iface |= (1 << 8) | (1 << 7);
break;
}
snd_soc_component_write(component, WM8940_IFACE, iface);
return 0;
}
static int wm8940_update_clocks(struct snd_soc_dai *dai);
static int wm8940_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm8940_priv *priv = snd_soc_component_get_drvdata(component);
u16 iface = snd_soc_component_read(component, WM8940_IFACE) & 0xFD9F;
u16 addcntrl = snd_soc_component_read(component, WM8940_ADDCNTRL) & 0xFFF1;
u16 companding = snd_soc_component_read(component,
WM8940_COMPANDINGCTL) & 0xFFDF;
int ret;
priv->fs = params_rate(params);
ret = wm8940_update_clocks(dai);
if (ret)
return ret;
/* LoutR control */
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE
&& params_channels(params) == 2)
iface |= (1 << 9);
switch (params_rate(params)) {
case 8000:
addcntrl |= (0x5 << 1);
break;
case 11025:
addcntrl |= (0x4 << 1);
break;
case 16000:
addcntrl |= (0x3 << 1);
break;
case 22050:
addcntrl |= (0x2 << 1);
break;
case 32000:
addcntrl |= (0x1 << 1);
break;
case 44100:
case 48000:
break;
}
ret = snd_soc_component_write(component, WM8940_ADDCNTRL, addcntrl);
if (ret)
goto error_ret;
switch (params_width(params)) {
case 8:
companding = companding | (1 << 5);
break;
case 16:
break;
case 20:
iface |= (1 << 5);
break;
case 24:
iface |= (2 << 5);
break;
case 32:
iface |= (3 << 5);
break;
}
ret = snd_soc_component_write(component, WM8940_COMPANDINGCTL, companding);
if (ret)
goto error_ret;
ret = snd_soc_component_write(component, WM8940_IFACE, iface);
error_ret:
return ret;
}
static int wm8940_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
u16 mute_reg = snd_soc_component_read(component, WM8940_DAC) & 0xffbf;
if (mute)
mute_reg |= 0x40;
return snd_soc_component_write(component, WM8940_DAC, mute_reg);
}
static int wm8940_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct wm8940_priv *wm8940 = snd_soc_component_get_drvdata(component);
u16 val;
u16 pwr_reg = snd_soc_component_read(component, WM8940_POWER1) & 0x1F0;
int ret = 0;
switch (level) {
case SND_SOC_BIAS_ON:
/* ensure bufioen and biasen */
pwr_reg |= (1 << 2) | (1 << 3);
/* Enable thermal shutdown */
val = snd_soc_component_read(component, WM8940_OUTPUTCTL);
ret = snd_soc_component_write(component, WM8940_OUTPUTCTL, val | 0x2);
if (ret)
break;
/* set vmid to 75k */
ret = snd_soc_component_write(component, WM8940_POWER1, pwr_reg | 0x1);
break;
case SND_SOC_BIAS_PREPARE:
/* ensure bufioen and biasen */
pwr_reg |= (1 << 2) | (1 << 3);
ret = snd_soc_component_write(component, WM8940_POWER1, pwr_reg | 0x1);
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
ret = regcache_sync(wm8940->regmap);
if (ret < 0) {
dev_err(component->dev, "Failed to sync cache: %d\n", ret);
return ret;
}
}
/* ensure bufioen and biasen */
pwr_reg |= (1 << 2) | (1 << 3);
/* set vmid to 300k for standby */
ret = snd_soc_component_write(component, WM8940_POWER1, pwr_reg | 0x2);
break;
case SND_SOC_BIAS_OFF:
ret = snd_soc_component_write(component, WM8940_POWER1, pwr_reg);
break;
}
return ret;
}
struct pll_ {
unsigned int pre_scale:2;
unsigned int n:4;
unsigned int k;
};
static struct pll_ pll_div;
/* The size in bits of the pll divide multiplied by 10
* to allow rounding later */
#define FIXED_PLL_SIZE ((1 << 24) * 10)
static void pll_factors(unsigned int target, unsigned int source)
{
unsigned long long Kpart;
unsigned int K, Ndiv, Nmod;
/* The left shift ist to avoid accuracy loss when right shifting */
Ndiv = target / source;
if (Ndiv > 12) {
source <<= 1;
/* Multiply by 2 */
pll_div.pre_scale = 0;
Ndiv = target / source;
} else if (Ndiv < 3) {
source >>= 2;
/* Divide by 4 */
pll_div.pre_scale = 3;
Ndiv = target / source;
} else if (Ndiv < 6) {
source >>= 1;
/* divide by 2 */
pll_div.pre_scale = 2;
Ndiv = target / source;
} else
pll_div.pre_scale = 1;
if ((Ndiv < 6) || (Ndiv > 12))
printk(KERN_WARNING
"WM8940 N value %d outwith recommended range!d\n",
Ndiv);
pll_div.n = Ndiv;
Nmod = target % source;
Kpart = FIXED_PLL_SIZE * (long long)Nmod;
do_div(Kpart, source);
K = Kpart & 0xFFFFFFFF;
/* Check if we need to round */
if ((K % 10) >= 5)
K += 5;
/* Move down to proper range now rounding is done */
K /= 10;
pll_div.k = K;
}
/* Untested at the moment */
static int wm8940_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
int source, unsigned int freq_in, unsigned int freq_out)
{
struct snd_soc_component *component = codec_dai->component;
u16 reg;
/* Turn off PLL */
reg = snd_soc_component_read(component, WM8940_POWER1);
snd_soc_component_write(component, WM8940_POWER1, reg & 0x1df);
if (freq_in == 0 || freq_out == 0) {
/* Clock CODEC directly from MCLK */
reg = snd_soc_component_read(component, WM8940_CLOCK);
snd_soc_component_write(component, WM8940_CLOCK, reg & 0x0ff);
/* Pll power down */
snd_soc_component_write(component, WM8940_PLLN, (1 << 7));
return 0;
}
/* Pll is followed by a frequency divide by 4 */
pll_factors(freq_out*4, freq_in);
if (pll_div.k)
snd_soc_component_write(component, WM8940_PLLN,
(pll_div.pre_scale << 4) | pll_div.n | (1 << 6));
else /* No factional component */
snd_soc_component_write(component, WM8940_PLLN,
(pll_div.pre_scale << 4) | pll_div.n);
snd_soc_component_write(component, WM8940_PLLK1, pll_div.k >> 18);
snd_soc_component_write(component, WM8940_PLLK2, (pll_div.k >> 9) & 0x1ff);
snd_soc_component_write(component, WM8940_PLLK3, pll_div.k & 0x1ff);
/* Enable the PLL */
reg = snd_soc_component_read(component, WM8940_POWER1);
snd_soc_component_write(component, WM8940_POWER1, reg | 0x020);
/* Run CODEC from PLL instead of MCLK */
reg = snd_soc_component_read(component, WM8940_CLOCK);
snd_soc_component_write(component, WM8940_CLOCK, reg | 0x100);
return 0;
}
static int wm8940_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
int div_id, int div)
{
struct snd_soc_component *component = codec_dai->component;
u16 reg;
int ret = 0;
switch (div_id) {
case WM8940_BCLKDIV:
reg = snd_soc_component_read(component, WM8940_CLOCK) & 0xFFE3;
ret = snd_soc_component_write(component, WM8940_CLOCK, reg | (div << 2));
break;
case WM8940_MCLKDIV:
reg = snd_soc_component_read(component, WM8940_CLOCK) & 0xFF1F;
ret = snd_soc_component_write(component, WM8940_CLOCK, reg | (div << 5));
break;
case WM8940_OPCLKDIV:
reg = snd_soc_component_read(component, WM8940_GPIO) & 0xFFCF;
ret = snd_soc_component_write(component, WM8940_GPIO, reg | (div << 4));
break;
}
return ret;
}
static unsigned int wm8940_get_mclkdiv(unsigned int f_in, unsigned int f_out,
int *mclkdiv)
{
unsigned int ratio = 2 * f_in / f_out;
if (ratio <= 2) {
*mclkdiv = WM8940_MCLKDIV_1;
ratio = 2;
} else if (ratio == 3) {
*mclkdiv = WM8940_MCLKDIV_1_5;
} else if (ratio == 4) {
*mclkdiv = WM8940_MCLKDIV_2;
} else if (ratio <= 6) {
*mclkdiv = WM8940_MCLKDIV_3;
ratio = 6;
} else if (ratio <= 8) {
*mclkdiv = WM8940_MCLKDIV_4;
ratio = 8;
} else if (ratio <= 12) {
*mclkdiv = WM8940_MCLKDIV_6;
ratio = 12;
} else if (ratio <= 16) {
*mclkdiv = WM8940_MCLKDIV_8;
ratio = 16;
} else {
*mclkdiv = WM8940_MCLKDIV_12;
ratio = 24;
}
return f_out * ratio / 2;
}
static int wm8940_update_clocks(struct snd_soc_dai *dai)
{
struct snd_soc_component *codec = dai->component;
struct wm8940_priv *priv = snd_soc_component_get_drvdata(codec);
unsigned int fs256;
unsigned int fpll = 0;
unsigned int f;
int mclkdiv;
if (!priv->mclk || !priv->fs)
return 0;
fs256 = 256 * priv->fs;
f = wm8940_get_mclkdiv(priv->mclk, fs256, &mclkdiv);
if (f != priv->mclk) {
/* The PLL performs best around 90MHz */
fpll = wm8940_get_mclkdiv(22500000, fs256, &mclkdiv);
}
wm8940_set_dai_pll(dai, 0, 0, priv->mclk, fpll);
wm8940_set_dai_clkdiv(dai, WM8940_MCLKDIV, mclkdiv);
return 0;
}
static int wm8940_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct snd_soc_component *codec = dai->component;
struct wm8940_priv *priv = snd_soc_component_get_drvdata(codec);
if (dir != SND_SOC_CLOCK_IN)
return -EINVAL;
priv->mclk = freq;
return wm8940_update_clocks(dai);
}
#define WM8940_RATES SNDRV_PCM_RATE_8000_48000
#define WM8940_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops wm8940_dai_ops = {
.hw_params = wm8940_i2s_hw_params,
.set_sysclk = wm8940_set_dai_sysclk,
.mute_stream = wm8940_mute,
.set_fmt = wm8940_set_dai_fmt,
.set_clkdiv = wm8940_set_dai_clkdiv,
.set_pll = wm8940_set_dai_pll,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver wm8940_dai = {
.name = "wm8940-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM8940_RATES,
.formats = WM8940_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM8940_RATES,
.formats = WM8940_FORMATS,
},
.ops = &wm8940_dai_ops,
.symmetric_rate = 1,
};
static int wm8940_probe(struct snd_soc_component *component)
{
struct wm8940_setup_data *pdata = component->dev->platform_data;
int ret;
u16 reg;
/*
* Check chip ID for wm8940 - value of 0x00 offset
* SOFTWARE_RESET on write
* CHIP_ID on read
*/
reg = snd_soc_component_read(component, WM8940_SOFTRESET);
if (reg != WM8940_CHIP_ID) {
dev_err(component->dev, "Wrong wm8940 chip ID: 0x%x\n", reg);
return -ENODEV;
}
ret = wm8940_reset(component);
if (ret < 0) {
dev_err(component->dev, "Failed to issue reset\n");
return ret;
}
snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
ret = snd_soc_component_write(component, WM8940_POWER1, 0x180);
if (ret < 0)
return ret;
if (pdata) {
reg = snd_soc_component_read(component, WM8940_OUTPUTCTL);
ret = snd_soc_component_write(component, WM8940_OUTPUTCTL, reg | pdata->vroi);
if (ret < 0)
return ret;
}
return ret;
}
static const struct snd_soc_component_driver soc_component_dev_wm8940 = {
.probe = wm8940_probe,
.set_bias_level = wm8940_set_bias_level,
.controls = wm8940_snd_controls,
.num_controls = ARRAY_SIZE(wm8940_snd_controls),
.dapm_widgets = wm8940_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8940_dapm_widgets),
.dapm_routes = wm8940_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(wm8940_dapm_routes),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config wm8940_regmap = {
.reg_bits = 8,
.val_bits = 16,
.max_register = WM8940_MONOMIX,
.reg_defaults = wm8940_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8940_reg_defaults),
.cache_type = REGCACHE_MAPLE,
.readable_reg = wm8940_readable_register,
.volatile_reg = wm8940_volatile_register,
};
static int wm8940_i2c_probe(struct i2c_client *i2c)
{
struct wm8940_priv *wm8940;
int ret;
wm8940 = devm_kzalloc(&i2c->dev, sizeof(struct wm8940_priv),
GFP_KERNEL);
if (wm8940 == NULL)
return -ENOMEM;
wm8940->regmap = devm_regmap_init_i2c(i2c, &wm8940_regmap);
if (IS_ERR(wm8940->regmap))
return PTR_ERR(wm8940->regmap);
i2c_set_clientdata(i2c, wm8940);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_wm8940, &wm8940_dai, 1);
return ret;
}
static const struct i2c_device_id wm8940_i2c_id[] = {
{ "wm8940", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8940_i2c_id);
static const struct of_device_id wm8940_of_match[] = {
{ .compatible = "wlf,wm8940", },
{ }
};
MODULE_DEVICE_TABLE(of, wm8940_of_match);
static struct i2c_driver wm8940_i2c_driver = {
.driver = {
.name = "wm8940",
.of_match_table = wm8940_of_match,
},
.probe = wm8940_i2c_probe,
.id_table = wm8940_i2c_id,
};
module_i2c_driver(wm8940_i2c_driver);
MODULE_DESCRIPTION("ASoC WM8940 driver");
MODULE_AUTHOR("Jonathan Cameron");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8940.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ALSA SoC TLV320AIC23 codec driver SPI interface
*
* Author: Arun KS, <[email protected]>
* Copyright: (C) 2008 Mistral Solutions Pvt Ltd.,
*
* Based on sound/soc/codecs/wm8731.c by Richard Purdie
*/
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include <sound/soc.h>
#include "tlv320aic23.h"
static int aic23_spi_probe(struct spi_device *spi)
{
int ret;
struct regmap *regmap;
dev_dbg(&spi->dev, "probing tlv320aic23 spi device\n");
spi->mode = SPI_MODE_0;
ret = spi_setup(spi);
if (ret < 0)
return ret;
regmap = devm_regmap_init_spi(spi, &tlv320aic23_regmap);
return tlv320aic23_probe(&spi->dev, regmap);
}
static struct spi_driver aic23_spi = {
.driver = {
.name = "tlv320aic23",
},
.probe = aic23_spi_probe,
};
module_spi_driver(aic23_spi);
MODULE_DESCRIPTION("ASoC TLV320AIC23 codec driver SPI");
MODULE_AUTHOR("Arun KS <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/tlv320aic23-spi.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8804.c -- WM8804 S/PDIF transceiver driver
*
* Copyright 2010-11 Wolfson Microelectronics plc
*
* Author: Dimitris Papastamos <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/gpio/consumer.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/of_device.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/soc-dapm.h>
#include "wm8804.h"
#define WM8804_NUM_SUPPLIES 2
static const char *wm8804_supply_names[WM8804_NUM_SUPPLIES] = {
"PVDD",
"DVDD"
};
static const struct reg_default wm8804_reg_defaults[] = {
{ 3, 0x21 }, /* R3 - PLL1 */
{ 4, 0xFD }, /* R4 - PLL2 */
{ 5, 0x36 }, /* R5 - PLL3 */
{ 6, 0x07 }, /* R6 - PLL4 */
{ 7, 0x16 }, /* R7 - PLL5 */
{ 8, 0x18 }, /* R8 - PLL6 */
{ 9, 0xFF }, /* R9 - SPDMODE */
{ 10, 0x00 }, /* R10 - INTMASK */
{ 18, 0x00 }, /* R18 - SPDTX1 */
{ 19, 0x00 }, /* R19 - SPDTX2 */
{ 20, 0x00 }, /* R20 - SPDTX3 */
{ 21, 0x71 }, /* R21 - SPDTX4 */
{ 22, 0x0B }, /* R22 - SPDTX5 */
{ 23, 0x70 }, /* R23 - GPO0 */
{ 24, 0x57 }, /* R24 - GPO1 */
{ 26, 0x42 }, /* R26 - GPO2 */
{ 27, 0x06 }, /* R27 - AIFTX */
{ 28, 0x06 }, /* R28 - AIFRX */
{ 29, 0x80 }, /* R29 - SPDRX1 */
{ 30, 0x07 }, /* R30 - PWRDN */
};
struct wm8804_priv {
struct device *dev;
struct regmap *regmap;
struct regulator_bulk_data supplies[WM8804_NUM_SUPPLIES];
struct notifier_block disable_nb[WM8804_NUM_SUPPLIES];
int mclk_div;
struct gpio_desc *reset;
int aif_pwr;
};
static int txsrc_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
static int wm8804_aif_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event);
/*
* We can't use the same notifier block for more than one supply and
* there's no way I can see to get from a callback to the caller
* except container_of().
*/
#define WM8804_REGULATOR_EVENT(n) \
static int wm8804_regulator_event_##n(struct notifier_block *nb, \
unsigned long event, void *data) \
{ \
struct wm8804_priv *wm8804 = container_of(nb, struct wm8804_priv, \
disable_nb[n]); \
if (event & REGULATOR_EVENT_DISABLE) { \
regcache_mark_dirty(wm8804->regmap); \
} \
return 0; \
}
WM8804_REGULATOR_EVENT(0)
WM8804_REGULATOR_EVENT(1)
static const char *txsrc_text[] = { "S/PDIF RX", "AIF" };
static SOC_ENUM_SINGLE_DECL(txsrc, WM8804_SPDTX4, 6, txsrc_text);
static const struct snd_kcontrol_new wm8804_tx_source_mux[] = {
SOC_DAPM_ENUM_EXT("Input Source", txsrc,
snd_soc_dapm_get_enum_double, txsrc_put),
};
static const struct snd_soc_dapm_widget wm8804_dapm_widgets[] = {
SND_SOC_DAPM_OUTPUT("SPDIF Out"),
SND_SOC_DAPM_INPUT("SPDIF In"),
SND_SOC_DAPM_PGA("SPDIFTX", WM8804_PWRDN, 2, 1, NULL, 0),
SND_SOC_DAPM_PGA("SPDIFRX", WM8804_PWRDN, 1, 1, NULL, 0),
SND_SOC_DAPM_MUX("Tx Source", SND_SOC_NOPM, 6, 0, wm8804_tx_source_mux),
SND_SOC_DAPM_AIF_OUT_E("AIFTX", NULL, 0, SND_SOC_NOPM, 0, 0, wm8804_aif_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_AIF_IN_E("AIFRX", NULL, 0, SND_SOC_NOPM, 0, 0, wm8804_aif_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
};
static const struct snd_soc_dapm_route wm8804_dapm_routes[] = {
{ "AIFRX", NULL, "Playback" },
{ "Tx Source", "AIF", "AIFRX" },
{ "SPDIFRX", NULL, "SPDIF In" },
{ "Tx Source", "S/PDIF RX", "SPDIFRX" },
{ "SPDIFTX", NULL, "Tx Source" },
{ "SPDIF Out", NULL, "SPDIFTX" },
{ "AIFTX", NULL, "SPDIFRX" },
{ "Capture", NULL, "AIFTX" },
};
static int wm8804_aif_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wm8804_priv *wm8804 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
/* power up the aif */
if (!wm8804->aif_pwr)
snd_soc_component_update_bits(component, WM8804_PWRDN, 0x10, 0x0);
wm8804->aif_pwr++;
break;
case SND_SOC_DAPM_POST_PMD:
/* power down only both paths are disabled */
wm8804->aif_pwr--;
if (!wm8804->aif_pwr)
snd_soc_component_update_bits(component, WM8804_PWRDN, 0x10, 0x10);
break;
}
return 0;
}
static int txsrc_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int val = ucontrol->value.enumerated.item[0] << e->shift_l;
unsigned int mask = 1 << e->shift_l;
unsigned int txpwr;
if (val != 0 && val != mask)
return -EINVAL;
snd_soc_dapm_mutex_lock(dapm);
if (snd_soc_component_test_bits(component, e->reg, mask, val)) {
/* save the current power state of the transmitter */
txpwr = snd_soc_component_read(component, WM8804_PWRDN) & 0x4;
/* power down the transmitter */
snd_soc_component_update_bits(component, WM8804_PWRDN, 0x4, 0x4);
/* set the tx source */
snd_soc_component_update_bits(component, e->reg, mask, val);
/* restore the transmitter's configuration */
snd_soc_component_update_bits(component, WM8804_PWRDN, 0x4, txpwr);
}
snd_soc_dapm_mutex_unlock(dapm);
return 0;
}
static bool wm8804_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8804_RST_DEVID1:
case WM8804_DEVID2:
case WM8804_DEVREV:
case WM8804_INTSTAT:
case WM8804_SPDSTAT:
case WM8804_RXCHAN1:
case WM8804_RXCHAN2:
case WM8804_RXCHAN3:
case WM8804_RXCHAN4:
case WM8804_RXCHAN5:
return true;
default:
return false;
}
}
static int wm8804_soft_reset(struct wm8804_priv *wm8804)
{
return regmap_write(wm8804->regmap, WM8804_RST_DEVID1, 0x0);
}
static int wm8804_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component;
u16 format, master, bcp, lrp;
component = dai->component;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
format = 0x2;
break;
case SND_SOC_DAIFMT_RIGHT_J:
format = 0x0;
break;
case SND_SOC_DAIFMT_LEFT_J:
format = 0x1;
break;
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B:
format = 0x3;
break;
default:
dev_err(dai->dev, "Unknown dai format\n");
return -EINVAL;
}
/* set data format */
snd_soc_component_update_bits(component, WM8804_AIFTX, 0x3, format);
snd_soc_component_update_bits(component, WM8804_AIFRX, 0x3, format);
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
master = 1;
break;
case SND_SOC_DAIFMT_CBS_CFS:
master = 0;
break;
default:
dev_err(dai->dev, "Unknown master/slave configuration\n");
return -EINVAL;
}
/* set master/slave mode */
snd_soc_component_update_bits(component, WM8804_AIFRX, 0x40, master << 6);
bcp = lrp = 0;
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
bcp = lrp = 1;
break;
case SND_SOC_DAIFMT_IB_NF:
bcp = 1;
break;
case SND_SOC_DAIFMT_NB_IF:
lrp = 1;
break;
default:
dev_err(dai->dev, "Unknown polarity configuration\n");
return -EINVAL;
}
/* set frame inversion */
snd_soc_component_update_bits(component, WM8804_AIFTX, 0x10 | 0x20,
(bcp << 4) | (lrp << 5));
snd_soc_component_update_bits(component, WM8804_AIFRX, 0x10 | 0x20,
(bcp << 4) | (lrp << 5));
return 0;
}
static int wm8804_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component;
u16 blen;
component = dai->component;
switch (params_width(params)) {
case 16:
blen = 0x0;
break;
case 20:
blen = 0x1;
break;
case 24:
blen = 0x2;
break;
default:
dev_err(dai->dev, "Unsupported word length: %u\n",
params_width(params));
return -EINVAL;
}
/* set word length */
snd_soc_component_update_bits(component, WM8804_AIFTX, 0xc, blen << 2);
snd_soc_component_update_bits(component, WM8804_AIFRX, 0xc, blen << 2);
return 0;
}
struct pll_div {
u32 prescale:1;
u32 mclkdiv:1;
u32 freqmode:2;
u32 n:4;
u32 k:22;
};
/* PLL rate to output rate divisions */
static struct {
unsigned int div;
unsigned int freqmode;
unsigned int mclkdiv;
} post_table[] = {
{ 2, 0, 0 },
{ 4, 0, 1 },
{ 4, 1, 0 },
{ 8, 1, 1 },
{ 8, 2, 0 },
{ 16, 2, 1 },
{ 12, 3, 0 },
{ 24, 3, 1 }
};
#define FIXED_PLL_SIZE ((1ULL << 22) * 10)
static int pll_factors(struct pll_div *pll_div, unsigned int target,
unsigned int source, unsigned int mclk_div)
{
u64 Kpart;
unsigned long int K, Ndiv, Nmod, tmp;
int i;
/*
* Scale the output frequency up; the PLL should run in the
* region of 90-100MHz.
*/
for (i = 0; i < ARRAY_SIZE(post_table); i++) {
tmp = target * post_table[i].div;
if ((tmp >= 90000000 && tmp <= 100000000) &&
(mclk_div == post_table[i].mclkdiv)) {
pll_div->freqmode = post_table[i].freqmode;
pll_div->mclkdiv = post_table[i].mclkdiv;
target *= post_table[i].div;
break;
}
}
if (i == ARRAY_SIZE(post_table)) {
pr_err("%s: Unable to scale output frequency: %uHz\n",
__func__, target);
return -EINVAL;
}
pll_div->prescale = 0;
Ndiv = target / source;
if (Ndiv < 5) {
source >>= 1;
pll_div->prescale = 1;
Ndiv = target / source;
}
if (Ndiv < 5 || Ndiv > 13) {
pr_err("%s: WM8804 N value is not within the recommended range: %lu\n",
__func__, Ndiv);
return -EINVAL;
}
pll_div->n = Ndiv;
Nmod = target % source;
Kpart = FIXED_PLL_SIZE * (u64)Nmod;
do_div(Kpart, source);
K = Kpart & 0xffffffff;
if ((K % 10) >= 5)
K += 5;
K /= 10;
pll_div->k = K;
return 0;
}
static int wm8804_set_pll(struct snd_soc_dai *dai, int pll_id,
int source, unsigned int freq_in,
unsigned int freq_out)
{
struct snd_soc_component *component = dai->component;
struct wm8804_priv *wm8804 = snd_soc_component_get_drvdata(component);
bool change;
if (!freq_in || !freq_out) {
/* disable the PLL */
regmap_update_bits_check(wm8804->regmap, WM8804_PWRDN,
0x1, 0x1, &change);
if (change)
pm_runtime_put(wm8804->dev);
} else {
int ret;
struct pll_div pll_div;
ret = pll_factors(&pll_div, freq_out, freq_in,
wm8804->mclk_div);
if (ret)
return ret;
/* power down the PLL before reprogramming it */
regmap_update_bits_check(wm8804->regmap, WM8804_PWRDN,
0x1, 0x1, &change);
if (!change)
pm_runtime_get_sync(wm8804->dev);
/* set PLLN and PRESCALE */
snd_soc_component_update_bits(component, WM8804_PLL4, 0xf | 0x10,
pll_div.n | (pll_div.prescale << 4));
/* set mclkdiv and freqmode */
snd_soc_component_update_bits(component, WM8804_PLL5, 0x3 | 0x8,
pll_div.freqmode | (pll_div.mclkdiv << 3));
/* set PLLK */
snd_soc_component_write(component, WM8804_PLL1, pll_div.k & 0xff);
snd_soc_component_write(component, WM8804_PLL2, (pll_div.k >> 8) & 0xff);
snd_soc_component_write(component, WM8804_PLL3, pll_div.k >> 16);
/* power up the PLL */
snd_soc_component_update_bits(component, WM8804_PWRDN, 0x1, 0);
}
return 0;
}
static int wm8804_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component;
component = dai->component;
switch (clk_id) {
case WM8804_TX_CLKSRC_MCLK:
if ((freq >= 10000000 && freq <= 14400000)
|| (freq >= 16280000 && freq <= 27000000))
snd_soc_component_update_bits(component, WM8804_PLL6, 0x80, 0x80);
else {
dev_err(dai->dev, "OSCCLOCK is not within the "
"recommended range: %uHz\n", freq);
return -EINVAL;
}
break;
case WM8804_TX_CLKSRC_PLL:
snd_soc_component_update_bits(component, WM8804_PLL6, 0x80, 0);
break;
case WM8804_CLKOUT_SRC_CLK1:
snd_soc_component_update_bits(component, WM8804_PLL6, 0x8, 0);
break;
case WM8804_CLKOUT_SRC_OSCCLK:
snd_soc_component_update_bits(component, WM8804_PLL6, 0x8, 0x8);
break;
default:
dev_err(dai->dev, "Unknown clock source: %d\n", clk_id);
return -EINVAL;
}
return 0;
}
static int wm8804_set_clkdiv(struct snd_soc_dai *dai,
int div_id, int div)
{
struct snd_soc_component *component;
struct wm8804_priv *wm8804;
component = dai->component;
switch (div_id) {
case WM8804_CLKOUT_DIV:
snd_soc_component_update_bits(component, WM8804_PLL5, 0x30,
(div & 0x3) << 4);
break;
case WM8804_MCLK_DIV:
wm8804 = snd_soc_component_get_drvdata(component);
wm8804->mclk_div = div;
break;
default:
dev_err(dai->dev, "Unknown clock divider: %d\n", div_id);
return -EINVAL;
}
return 0;
}
static const struct snd_soc_dai_ops wm8804_dai_ops = {
.hw_params = wm8804_hw_params,
.set_fmt = wm8804_set_fmt,
.set_sysclk = wm8804_set_sysclk,
.set_clkdiv = wm8804_set_clkdiv,
.set_pll = wm8804_set_pll
};
#define WM8804_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE)
#define WM8804_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | \
SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000)
static struct snd_soc_dai_driver wm8804_dai = {
.name = "wm8804-spdif",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = WM8804_RATES,
.formats = WM8804_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = WM8804_RATES,
.formats = WM8804_FORMATS,
},
.ops = &wm8804_dai_ops,
.symmetric_rate = 1
};
static const struct snd_soc_component_driver soc_component_dev_wm8804 = {
.dapm_widgets = wm8804_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8804_dapm_widgets),
.dapm_routes = wm8804_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(wm8804_dapm_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
const struct regmap_config wm8804_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = WM8804_MAX_REGISTER,
.volatile_reg = wm8804_volatile,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = wm8804_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8804_reg_defaults),
};
EXPORT_SYMBOL_GPL(wm8804_regmap_config);
int wm8804_probe(struct device *dev, struct regmap *regmap)
{
struct wm8804_priv *wm8804;
unsigned int id1, id2;
int i, ret;
wm8804 = devm_kzalloc(dev, sizeof(*wm8804), GFP_KERNEL);
if (!wm8804)
return -ENOMEM;
dev_set_drvdata(dev, wm8804);
wm8804->dev = dev;
wm8804->regmap = regmap;
wm8804->reset = devm_gpiod_get_optional(dev, "wlf,reset",
GPIOD_OUT_LOW);
if (IS_ERR(wm8804->reset)) {
ret = PTR_ERR(wm8804->reset);
dev_err(dev, "Failed to get reset line: %d\n", ret);
return ret;
}
for (i = 0; i < ARRAY_SIZE(wm8804->supplies); i++)
wm8804->supplies[i].supply = wm8804_supply_names[i];
ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(wm8804->supplies),
wm8804->supplies);
if (ret) {
dev_err(dev, "Failed to request supplies: %d\n", ret);
return ret;
}
wm8804->disable_nb[0].notifier_call = wm8804_regulator_event_0;
wm8804->disable_nb[1].notifier_call = wm8804_regulator_event_1;
/* This should really be moved into the regulator core */
for (i = 0; i < ARRAY_SIZE(wm8804->supplies); i++) {
struct regulator *regulator = wm8804->supplies[i].consumer;
ret = devm_regulator_register_notifier(regulator,
&wm8804->disable_nb[i]);
if (ret != 0) {
dev_err(dev,
"Failed to register regulator notifier: %d\n",
ret);
return ret;
}
}
ret = regulator_bulk_enable(ARRAY_SIZE(wm8804->supplies),
wm8804->supplies);
if (ret) {
dev_err(dev, "Failed to enable supplies: %d\n", ret);
return ret;
}
gpiod_set_value_cansleep(wm8804->reset, 1);
ret = regmap_read(regmap, WM8804_RST_DEVID1, &id1);
if (ret < 0) {
dev_err(dev, "Failed to read device ID: %d\n", ret);
goto err_reg_enable;
}
ret = regmap_read(regmap, WM8804_DEVID2, &id2);
if (ret < 0) {
dev_err(dev, "Failed to read device ID: %d\n", ret);
goto err_reg_enable;
}
id2 = (id2 << 8) | id1;
if (id2 != 0x8805) {
dev_err(dev, "Invalid device ID: %#x\n", id2);
ret = -EINVAL;
goto err_reg_enable;
}
ret = regmap_read(regmap, WM8804_DEVREV, &id1);
if (ret < 0) {
dev_err(dev, "Failed to read device revision: %d\n",
ret);
goto err_reg_enable;
}
dev_info(dev, "revision %c\n", id1 + 'A');
if (!wm8804->reset) {
ret = wm8804_soft_reset(wm8804);
if (ret < 0) {
dev_err(dev, "Failed to issue reset: %d\n", ret);
goto err_reg_enable;
}
}
ret = devm_snd_soc_register_component(dev, &soc_component_dev_wm8804,
&wm8804_dai, 1);
if (ret < 0) {
dev_err(dev, "Failed to register CODEC: %d\n", ret);
goto err_reg_enable;
}
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
pm_runtime_idle(dev);
return 0;
err_reg_enable:
regulator_bulk_disable(ARRAY_SIZE(wm8804->supplies), wm8804->supplies);
return ret;
}
EXPORT_SYMBOL_GPL(wm8804_probe);
void wm8804_remove(struct device *dev)
{
pm_runtime_disable(dev);
}
EXPORT_SYMBOL_GPL(wm8804_remove);
#if IS_ENABLED(CONFIG_PM)
static int wm8804_runtime_resume(struct device *dev)
{
struct wm8804_priv *wm8804 = dev_get_drvdata(dev);
int ret;
ret = regulator_bulk_enable(ARRAY_SIZE(wm8804->supplies),
wm8804->supplies);
if (ret) {
dev_err(wm8804->dev, "Failed to enable supplies: %d\n", ret);
return ret;
}
regcache_sync(wm8804->regmap);
/* Power up OSCCLK */
regmap_update_bits(wm8804->regmap, WM8804_PWRDN, 0x8, 0x0);
return 0;
}
static int wm8804_runtime_suspend(struct device *dev)
{
struct wm8804_priv *wm8804 = dev_get_drvdata(dev);
/* Power down OSCCLK */
regmap_update_bits(wm8804->regmap, WM8804_PWRDN, 0x8, 0x8);
regulator_bulk_disable(ARRAY_SIZE(wm8804->supplies),
wm8804->supplies);
return 0;
}
#endif
const struct dev_pm_ops wm8804_pm = {
SET_RUNTIME_PM_OPS(wm8804_runtime_suspend, wm8804_runtime_resume, NULL)
};
EXPORT_SYMBOL_GPL(wm8804_pm);
MODULE_DESCRIPTION("ASoC WM8804 driver");
MODULE_AUTHOR("Dimitris Papastamos <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8804.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ALSA SoC SPDIF DIT driver
*
* This driver is used by controllers which can operate in DIT (SPDI/F) where
* no codec is needed. This file provides stub codec that can be used
* in these configurations. TI DaVinci Audio controller uses this driver.
*
* Author: Steve Chen, <[email protected]>
* Copyright: (C) 2009 MontaVista Software, Inc., <[email protected]>
* Copyright: (C) 2009 Texas Instruments, India
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/slab.h>
#include <sound/soc.h>
#include <sound/pcm.h>
#include <sound/initval.h>
#include <linux/of.h>
#define DRV_NAME "spdif-dit"
#define STUB_RATES SNDRV_PCM_RATE_8000_192000
#define STUB_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dapm_widget dit_widgets[] = {
SND_SOC_DAPM_OUTPUT("spdif-out"),
};
static const struct snd_soc_dapm_route dit_routes[] = {
{ "spdif-out", NULL, "Playback" },
};
static struct snd_soc_component_driver soc_codec_spdif_dit = {
.dapm_widgets = dit_widgets,
.num_dapm_widgets = ARRAY_SIZE(dit_widgets),
.dapm_routes = dit_routes,
.num_dapm_routes = ARRAY_SIZE(dit_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static struct snd_soc_dai_driver dit_stub_dai = {
.name = "dit-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 384,
.rates = STUB_RATES,
.formats = STUB_FORMATS,
},
};
static int spdif_dit_probe(struct platform_device *pdev)
{
return devm_snd_soc_register_component(&pdev->dev,
&soc_codec_spdif_dit,
&dit_stub_dai, 1);
}
#ifdef CONFIG_OF
static const struct of_device_id spdif_dit_dt_ids[] = {
{ .compatible = "linux,spdif-dit", },
{ }
};
MODULE_DEVICE_TABLE(of, spdif_dit_dt_ids);
#endif
static struct platform_driver spdif_dit_driver = {
.probe = spdif_dit_probe,
.driver = {
.name = DRV_NAME,
.of_match_table = of_match_ptr(spdif_dit_dt_ids),
},
};
module_platform_driver(spdif_dit_driver);
MODULE_AUTHOR("Steve Chen <[email protected]>");
MODULE_DESCRIPTION("SPDIF dummy codec driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRV_NAME);
| linux-master | sound/soc/codecs/spdif_transmitter.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* ad73311.c -- ALSA Soc AD73311 codec support
*
* Copyright: Analog Devices Inc.
* Author: Cliff Cai <[email protected]>
*/
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/ac97_codec.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include "ad73311.h"
static const struct snd_soc_dapm_widget ad73311_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("VINP"),
SND_SOC_DAPM_INPUT("VINN"),
SND_SOC_DAPM_OUTPUT("VOUTN"),
SND_SOC_DAPM_OUTPUT("VOUTP"),
};
static const struct snd_soc_dapm_route ad73311_dapm_routes[] = {
{ "Capture", NULL, "VINP" },
{ "Capture", NULL, "VINN" },
{ "VOUTN", NULL, "Playback" },
{ "VOUTP", NULL, "Playback" },
};
static struct snd_soc_dai_driver ad73311_dai = {
.name = "ad73311-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 1,
.rates = SNDRV_PCM_RATE_8000,
.formats = SNDRV_PCM_FMTBIT_S16_LE, },
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 1,
.rates = SNDRV_PCM_RATE_8000,
.formats = SNDRV_PCM_FMTBIT_S16_LE, },
};
static const struct snd_soc_component_driver soc_component_dev_ad73311 = {
.dapm_widgets = ad73311_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(ad73311_dapm_widgets),
.dapm_routes = ad73311_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(ad73311_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int ad73311_probe(struct platform_device *pdev)
{
return devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_ad73311, &ad73311_dai, 1);
}
static struct platform_driver ad73311_codec_driver = {
.driver = {
.name = "ad73311",
},
.probe = ad73311_probe,
};
module_platform_driver(ad73311_codec_driver);
MODULE_DESCRIPTION("ASoC ad73311 driver");
MODULE_AUTHOR("Cliff Cai ");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/ad73311.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8770.c -- WM8770 ALSA SoC Audio driver
*
* Copyright 2010 Wolfson Microelectronics plc
*
* Author: Dimitris Papastamos <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/of_device.h>
#include <linux/pm.h>
#include <linux/spi/spi.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "wm8770.h"
#define WM8770_NUM_SUPPLIES 3
static const char *wm8770_supply_names[WM8770_NUM_SUPPLIES] = {
"AVDD1",
"AVDD2",
"DVDD"
};
static const struct reg_default wm8770_reg_defaults[] = {
{ 0, 0x7f },
{ 1, 0x7f },
{ 2, 0x7f },
{ 3, 0x7f },
{ 4, 0x7f },
{ 5, 0x7f },
{ 6, 0x7f },
{ 7, 0x7f },
{ 8, 0x7f },
{ 9, 0xff },
{ 10, 0xff },
{ 11, 0xff },
{ 12, 0xff },
{ 13, 0xff },
{ 14, 0xff },
{ 15, 0xff },
{ 16, 0xff },
{ 17, 0xff },
{ 18, 0 },
{ 19, 0x90 },
{ 20, 0 },
{ 21, 0 },
{ 22, 0x22 },
{ 23, 0x22 },
{ 24, 0x3e },
{ 25, 0xc },
{ 26, 0xc },
{ 27, 0x100 },
{ 28, 0x189 },
{ 29, 0x189 },
{ 30, 0x8770 },
};
static bool wm8770_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8770_RESET:
return true;
default:
return false;
}
}
struct wm8770_priv {
struct regmap *regmap;
struct regulator_bulk_data supplies[WM8770_NUM_SUPPLIES];
struct notifier_block disable_nb[WM8770_NUM_SUPPLIES];
struct snd_soc_component *component;
int sysclk;
};
static int vout12supply_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event);
static int vout34supply_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event);
/*
* We can't use the same notifier block for more than one supply and
* there's no way I can see to get from a callback to the caller
* except container_of().
*/
#define WM8770_REGULATOR_EVENT(n) \
static int wm8770_regulator_event_##n(struct notifier_block *nb, \
unsigned long event, void *data) \
{ \
struct wm8770_priv *wm8770 = container_of(nb, struct wm8770_priv, \
disable_nb[n]); \
if (event & REGULATOR_EVENT_DISABLE) { \
regcache_mark_dirty(wm8770->regmap); \
} \
return 0; \
}
WM8770_REGULATOR_EVENT(0)
WM8770_REGULATOR_EVENT(1)
WM8770_REGULATOR_EVENT(2)
static const DECLARE_TLV_DB_SCALE(adc_tlv, -1200, 100, 0);
static const DECLARE_TLV_DB_SCALE(dac_dig_tlv, -12750, 50, 1);
static const DECLARE_TLV_DB_SCALE(dac_alg_tlv, -12700, 100, 1);
static const char *dac_phase_text[][2] = {
{ "DAC1 Normal", "DAC1 Inverted" },
{ "DAC2 Normal", "DAC2 Inverted" },
{ "DAC3 Normal", "DAC3 Inverted" },
{ "DAC4 Normal", "DAC4 Inverted" },
};
static const struct soc_enum dac_phase[] = {
SOC_ENUM_DOUBLE(WM8770_DACPHASE, 0, 1, 2, dac_phase_text[0]),
SOC_ENUM_DOUBLE(WM8770_DACPHASE, 2, 3, 2, dac_phase_text[1]),
SOC_ENUM_DOUBLE(WM8770_DACPHASE, 4, 5, 2, dac_phase_text[2]),
SOC_ENUM_DOUBLE(WM8770_DACPHASE, 6, 7, 2, dac_phase_text[3]),
};
static const struct snd_kcontrol_new wm8770_snd_controls[] = {
/* global DAC playback controls */
SOC_SINGLE_TLV("DAC Playback Volume", WM8770_MSDIGVOL, 0, 255, 0,
dac_dig_tlv),
SOC_SINGLE("DAC Playback Switch", WM8770_DACMUTE, 4, 1, 1),
SOC_SINGLE("DAC Playback ZC Switch", WM8770_DACCTRL1, 0, 1, 0),
/* global VOUT playback controls */
SOC_SINGLE_TLV("VOUT Playback Volume", WM8770_MSALGVOL, 0, 127, 0,
dac_alg_tlv),
SOC_SINGLE("VOUT Playback ZC Switch", WM8770_MSALGVOL, 7, 1, 0),
/* VOUT1/2/3/4 specific controls */
SOC_DOUBLE_R_TLV("VOUT1 Playback Volume", WM8770_VOUT1LVOL,
WM8770_VOUT1RVOL, 0, 127, 0, dac_alg_tlv),
SOC_DOUBLE_R("VOUT1 Playback ZC Switch", WM8770_VOUT1LVOL,
WM8770_VOUT1RVOL, 7, 1, 0),
SOC_DOUBLE_R_TLV("VOUT2 Playback Volume", WM8770_VOUT2LVOL,
WM8770_VOUT2RVOL, 0, 127, 0, dac_alg_tlv),
SOC_DOUBLE_R("VOUT2 Playback ZC Switch", WM8770_VOUT2LVOL,
WM8770_VOUT2RVOL, 7, 1, 0),
SOC_DOUBLE_R_TLV("VOUT3 Playback Volume", WM8770_VOUT3LVOL,
WM8770_VOUT3RVOL, 0, 127, 0, dac_alg_tlv),
SOC_DOUBLE_R("VOUT3 Playback ZC Switch", WM8770_VOUT3LVOL,
WM8770_VOUT3RVOL, 7, 1, 0),
SOC_DOUBLE_R_TLV("VOUT4 Playback Volume", WM8770_VOUT4LVOL,
WM8770_VOUT4RVOL, 0, 127, 0, dac_alg_tlv),
SOC_DOUBLE_R("VOUT4 Playback ZC Switch", WM8770_VOUT4LVOL,
WM8770_VOUT4RVOL, 7, 1, 0),
/* DAC1/2/3/4 specific controls */
SOC_DOUBLE_R_TLV("DAC1 Playback Volume", WM8770_DAC1LVOL,
WM8770_DAC1RVOL, 0, 255, 0, dac_dig_tlv),
SOC_SINGLE("DAC1 Deemphasis Switch", WM8770_DACCTRL2, 0, 1, 0),
SOC_ENUM("DAC1 Phase", dac_phase[0]),
SOC_DOUBLE_R_TLV("DAC2 Playback Volume", WM8770_DAC2LVOL,
WM8770_DAC2RVOL, 0, 255, 0, dac_dig_tlv),
SOC_SINGLE("DAC2 Deemphasis Switch", WM8770_DACCTRL2, 1, 1, 0),
SOC_ENUM("DAC2 Phase", dac_phase[1]),
SOC_DOUBLE_R_TLV("DAC3 Playback Volume", WM8770_DAC3LVOL,
WM8770_DAC3RVOL, 0, 255, 0, dac_dig_tlv),
SOC_SINGLE("DAC3 Deemphasis Switch", WM8770_DACCTRL2, 2, 1, 0),
SOC_ENUM("DAC3 Phase", dac_phase[2]),
SOC_DOUBLE_R_TLV("DAC4 Playback Volume", WM8770_DAC4LVOL,
WM8770_DAC4RVOL, 0, 255, 0, dac_dig_tlv),
SOC_SINGLE("DAC4 Deemphasis Switch", WM8770_DACCTRL2, 3, 1, 0),
SOC_ENUM("DAC4 Phase", dac_phase[3]),
/* ADC specific controls */
SOC_DOUBLE_R_TLV("Capture Volume", WM8770_ADCLCTRL, WM8770_ADCRCTRL,
0, 31, 0, adc_tlv),
SOC_DOUBLE_R("Capture Switch", WM8770_ADCLCTRL, WM8770_ADCRCTRL,
5, 1, 1),
/* other controls */
SOC_SINGLE("ADC 128x Oversampling Switch", WM8770_MSTRCTRL, 3, 1, 0),
SOC_SINGLE("ADC Highpass Filter Switch", WM8770_IFACECTRL, 8, 1, 1)
};
static const char *ain_text[] = {
"AIN1", "AIN2", "AIN3", "AIN4",
"AIN5", "AIN6", "AIN7", "AIN8"
};
static SOC_ENUM_DOUBLE_DECL(ain_enum,
WM8770_ADCMUX, 0, 4, ain_text);
static const struct snd_kcontrol_new ain_mux =
SOC_DAPM_ENUM("Capture Mux", ain_enum);
static const struct snd_kcontrol_new vout1_mix_controls[] = {
SOC_DAPM_SINGLE("DAC1 Switch", WM8770_OUTMUX1, 0, 1, 0),
SOC_DAPM_SINGLE("AUX1 Switch", WM8770_OUTMUX1, 1, 1, 0),
SOC_DAPM_SINGLE("Bypass Switch", WM8770_OUTMUX1, 2, 1, 0)
};
static const struct snd_kcontrol_new vout2_mix_controls[] = {
SOC_DAPM_SINGLE("DAC2 Switch", WM8770_OUTMUX1, 3, 1, 0),
SOC_DAPM_SINGLE("AUX2 Switch", WM8770_OUTMUX1, 4, 1, 0),
SOC_DAPM_SINGLE("Bypass Switch", WM8770_OUTMUX1, 5, 1, 0)
};
static const struct snd_kcontrol_new vout3_mix_controls[] = {
SOC_DAPM_SINGLE("DAC3 Switch", WM8770_OUTMUX2, 0, 1, 0),
SOC_DAPM_SINGLE("AUX3 Switch", WM8770_OUTMUX2, 1, 1, 0),
SOC_DAPM_SINGLE("Bypass Switch", WM8770_OUTMUX2, 2, 1, 0)
};
static const struct snd_kcontrol_new vout4_mix_controls[] = {
SOC_DAPM_SINGLE("DAC4 Switch", WM8770_OUTMUX2, 3, 1, 0),
SOC_DAPM_SINGLE("Bypass Switch", WM8770_OUTMUX2, 4, 1, 0)
};
static const struct snd_soc_dapm_widget wm8770_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("AUX1"),
SND_SOC_DAPM_INPUT("AUX2"),
SND_SOC_DAPM_INPUT("AUX3"),
SND_SOC_DAPM_INPUT("AIN1"),
SND_SOC_DAPM_INPUT("AIN2"),
SND_SOC_DAPM_INPUT("AIN3"),
SND_SOC_DAPM_INPUT("AIN4"),
SND_SOC_DAPM_INPUT("AIN5"),
SND_SOC_DAPM_INPUT("AIN6"),
SND_SOC_DAPM_INPUT("AIN7"),
SND_SOC_DAPM_INPUT("AIN8"),
SND_SOC_DAPM_MUX("Capture Mux", WM8770_ADCMUX, 8, 1, &ain_mux),
SND_SOC_DAPM_ADC("ADC", "Capture", WM8770_PWDNCTRL, 1, 1),
SND_SOC_DAPM_DAC("DAC1", "Playback", WM8770_PWDNCTRL, 2, 1),
SND_SOC_DAPM_DAC("DAC2", "Playback", WM8770_PWDNCTRL, 3, 1),
SND_SOC_DAPM_DAC("DAC3", "Playback", WM8770_PWDNCTRL, 4, 1),
SND_SOC_DAPM_DAC("DAC4", "Playback", WM8770_PWDNCTRL, 5, 1),
SND_SOC_DAPM_SUPPLY("VOUT12 Supply", SND_SOC_NOPM, 0, 0,
vout12supply_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("VOUT34 Supply", SND_SOC_NOPM, 0, 0,
vout34supply_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER("VOUT1 Mixer", SND_SOC_NOPM, 0, 0,
vout1_mix_controls, ARRAY_SIZE(vout1_mix_controls)),
SND_SOC_DAPM_MIXER("VOUT2 Mixer", SND_SOC_NOPM, 0, 0,
vout2_mix_controls, ARRAY_SIZE(vout2_mix_controls)),
SND_SOC_DAPM_MIXER("VOUT3 Mixer", SND_SOC_NOPM, 0, 0,
vout3_mix_controls, ARRAY_SIZE(vout3_mix_controls)),
SND_SOC_DAPM_MIXER("VOUT4 Mixer", SND_SOC_NOPM, 0, 0,
vout4_mix_controls, ARRAY_SIZE(vout4_mix_controls)),
SND_SOC_DAPM_OUTPUT("VOUT1"),
SND_SOC_DAPM_OUTPUT("VOUT2"),
SND_SOC_DAPM_OUTPUT("VOUT3"),
SND_SOC_DAPM_OUTPUT("VOUT4")
};
static const struct snd_soc_dapm_route wm8770_intercon[] = {
{ "Capture Mux", "AIN1", "AIN1" },
{ "Capture Mux", "AIN2", "AIN2" },
{ "Capture Mux", "AIN3", "AIN3" },
{ "Capture Mux", "AIN4", "AIN4" },
{ "Capture Mux", "AIN5", "AIN5" },
{ "Capture Mux", "AIN6", "AIN6" },
{ "Capture Mux", "AIN7", "AIN7" },
{ "Capture Mux", "AIN8", "AIN8" },
{ "ADC", NULL, "Capture Mux" },
{ "VOUT1 Mixer", NULL, "VOUT12 Supply" },
{ "VOUT1 Mixer", "DAC1 Switch", "DAC1" },
{ "VOUT1 Mixer", "AUX1 Switch", "AUX1" },
{ "VOUT1 Mixer", "Bypass Switch", "Capture Mux" },
{ "VOUT2 Mixer", NULL, "VOUT12 Supply" },
{ "VOUT2 Mixer", "DAC2 Switch", "DAC2" },
{ "VOUT2 Mixer", "AUX2 Switch", "AUX2" },
{ "VOUT2 Mixer", "Bypass Switch", "Capture Mux" },
{ "VOUT3 Mixer", NULL, "VOUT34 Supply" },
{ "VOUT3 Mixer", "DAC3 Switch", "DAC3" },
{ "VOUT3 Mixer", "AUX3 Switch", "AUX3" },
{ "VOUT3 Mixer", "Bypass Switch", "Capture Mux" },
{ "VOUT4 Mixer", NULL, "VOUT34 Supply" },
{ "VOUT4 Mixer", "DAC4 Switch", "DAC4" },
{ "VOUT4 Mixer", "Bypass Switch", "Capture Mux" },
{ "VOUT1", NULL, "VOUT1 Mixer" },
{ "VOUT2", NULL, "VOUT2 Mixer" },
{ "VOUT3", NULL, "VOUT3 Mixer" },
{ "VOUT4", NULL, "VOUT4 Mixer" }
};
static int vout12supply_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_component_update_bits(component, WM8770_OUTMUX1, 0x180, 0);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component, WM8770_OUTMUX1, 0x180, 0x180);
break;
}
return 0;
}
static int vout34supply_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_component_update_bits(component, WM8770_OUTMUX2, 0x180, 0);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component, WM8770_OUTMUX2, 0x180, 0x180);
break;
}
return 0;
}
static int wm8770_reset(struct snd_soc_component *component)
{
return snd_soc_component_write(component, WM8770_RESET, 0);
}
static int wm8770_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component;
int iface, master;
component = dai->component;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
master = 0x100;
break;
case SND_SOC_DAIFMT_CBS_CFS:
master = 0;
break;
default:
return -EINVAL;
}
iface = 0;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface |= 0x2;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
iface |= 0x1;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
iface |= 0xc;
break;
case SND_SOC_DAIFMT_IB_NF:
iface |= 0x8;
break;
case SND_SOC_DAIFMT_NB_IF:
iface |= 0x4;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, WM8770_IFACECTRL, 0xf, iface);
snd_soc_component_update_bits(component, WM8770_MSTRCTRL, 0x100, master);
return 0;
}
static const int mclk_ratios[] = {
128,
192,
256,
384,
512,
768
};
static int wm8770_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component;
struct wm8770_priv *wm8770;
int i;
int iface;
int shift;
int ratio;
component = dai->component;
wm8770 = snd_soc_component_get_drvdata(component);
iface = 0;
switch (params_width(params)) {
case 16:
break;
case 20:
iface |= 0x10;
break;
case 24:
iface |= 0x20;
break;
case 32:
iface |= 0x30;
break;
}
switch (substream->stream) {
case SNDRV_PCM_STREAM_PLAYBACK:
i = 0;
shift = 4;
break;
case SNDRV_PCM_STREAM_CAPTURE:
i = 2;
shift = 0;
break;
default:
return -EINVAL;
}
/* Only need to set MCLK/LRCLK ratio if we're master */
if (snd_soc_component_read(component, WM8770_MSTRCTRL) & 0x100) {
for (; i < ARRAY_SIZE(mclk_ratios); ++i) {
ratio = wm8770->sysclk / params_rate(params);
if (ratio == mclk_ratios[i])
break;
}
if (i == ARRAY_SIZE(mclk_ratios)) {
dev_err(component->dev,
"Unable to configure MCLK ratio %d/%d\n",
wm8770->sysclk, params_rate(params));
return -EINVAL;
}
dev_dbg(component->dev, "MCLK is %dfs\n", mclk_ratios[i]);
snd_soc_component_update_bits(component, WM8770_MSTRCTRL, 0x7 << shift,
i << shift);
}
snd_soc_component_update_bits(component, WM8770_IFACECTRL, 0x30, iface);
return 0;
}
static int wm8770_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component;
component = dai->component;
return snd_soc_component_update_bits(component, WM8770_DACMUTE, 0x10,
!!mute << 4);
}
static int wm8770_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component;
struct wm8770_priv *wm8770;
component = dai->component;
wm8770 = snd_soc_component_get_drvdata(component);
wm8770->sysclk = freq;
return 0;
}
static int wm8770_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
int ret;
struct wm8770_priv *wm8770;
wm8770 = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
ret = regulator_bulk_enable(ARRAY_SIZE(wm8770->supplies),
wm8770->supplies);
if (ret) {
dev_err(component->dev,
"Failed to enable supplies: %d\n",
ret);
return ret;
}
regcache_sync(wm8770->regmap);
/* global powerup */
snd_soc_component_write(component, WM8770_PWDNCTRL, 0);
}
break;
case SND_SOC_BIAS_OFF:
/* global powerdown */
snd_soc_component_write(component, WM8770_PWDNCTRL, 1);
regulator_bulk_disable(ARRAY_SIZE(wm8770->supplies),
wm8770->supplies);
break;
}
return 0;
}
#define WM8770_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops wm8770_dai_ops = {
.mute_stream = wm8770_mute,
.hw_params = wm8770_hw_params,
.set_fmt = wm8770_set_fmt,
.set_sysclk = wm8770_set_sysclk,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver wm8770_dai = {
.name = "wm8770-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = WM8770_FORMATS
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = WM8770_FORMATS
},
.ops = &wm8770_dai_ops,
.symmetric_rate = 1
};
static int wm8770_probe(struct snd_soc_component *component)
{
struct wm8770_priv *wm8770;
int ret;
wm8770 = snd_soc_component_get_drvdata(component);
wm8770->component = component;
ret = regulator_bulk_enable(ARRAY_SIZE(wm8770->supplies),
wm8770->supplies);
if (ret) {
dev_err(component->dev, "Failed to enable supplies: %d\n", ret);
return ret;
}
ret = wm8770_reset(component);
if (ret < 0) {
dev_err(component->dev, "Failed to issue reset: %d\n", ret);
goto err_reg_enable;
}
/* latch the volume update bits */
snd_soc_component_update_bits(component, WM8770_MSDIGVOL, 0x100, 0x100);
snd_soc_component_update_bits(component, WM8770_MSALGVOL, 0x100, 0x100);
snd_soc_component_update_bits(component, WM8770_VOUT1RVOL, 0x100, 0x100);
snd_soc_component_update_bits(component, WM8770_VOUT2RVOL, 0x100, 0x100);
snd_soc_component_update_bits(component, WM8770_VOUT3RVOL, 0x100, 0x100);
snd_soc_component_update_bits(component, WM8770_VOUT4RVOL, 0x100, 0x100);
snd_soc_component_update_bits(component, WM8770_DAC1RVOL, 0x100, 0x100);
snd_soc_component_update_bits(component, WM8770_DAC2RVOL, 0x100, 0x100);
snd_soc_component_update_bits(component, WM8770_DAC3RVOL, 0x100, 0x100);
snd_soc_component_update_bits(component, WM8770_DAC4RVOL, 0x100, 0x100);
/* mute all DACs */
snd_soc_component_update_bits(component, WM8770_DACMUTE, 0x10, 0x10);
err_reg_enable:
regulator_bulk_disable(ARRAY_SIZE(wm8770->supplies), wm8770->supplies);
return ret;
}
static const struct snd_soc_component_driver soc_component_dev_wm8770 = {
.probe = wm8770_probe,
.set_bias_level = wm8770_set_bias_level,
.controls = wm8770_snd_controls,
.num_controls = ARRAY_SIZE(wm8770_snd_controls),
.dapm_widgets = wm8770_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8770_dapm_widgets),
.dapm_routes = wm8770_intercon,
.num_dapm_routes = ARRAY_SIZE(wm8770_intercon),
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct of_device_id wm8770_of_match[] = {
{ .compatible = "wlf,wm8770", },
{ }
};
MODULE_DEVICE_TABLE(of, wm8770_of_match);
static const struct regmap_config wm8770_regmap = {
.reg_bits = 7,
.val_bits = 9,
.max_register = WM8770_RESET,
.reg_defaults = wm8770_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8770_reg_defaults),
.cache_type = REGCACHE_MAPLE,
.volatile_reg = wm8770_volatile_reg,
};
static int wm8770_spi_probe(struct spi_device *spi)
{
struct wm8770_priv *wm8770;
int ret, i;
wm8770 = devm_kzalloc(&spi->dev, sizeof(struct wm8770_priv),
GFP_KERNEL);
if (!wm8770)
return -ENOMEM;
for (i = 0; i < ARRAY_SIZE(wm8770->supplies); i++)
wm8770->supplies[i].supply = wm8770_supply_names[i];
ret = devm_regulator_bulk_get(&spi->dev, ARRAY_SIZE(wm8770->supplies),
wm8770->supplies);
if (ret) {
dev_err(&spi->dev, "Failed to request supplies: %d\n", ret);
return ret;
}
wm8770->disable_nb[0].notifier_call = wm8770_regulator_event_0;
wm8770->disable_nb[1].notifier_call = wm8770_regulator_event_1;
wm8770->disable_nb[2].notifier_call = wm8770_regulator_event_2;
/* This should really be moved into the regulator core */
for (i = 0; i < ARRAY_SIZE(wm8770->supplies); i++) {
ret = devm_regulator_register_notifier(
wm8770->supplies[i].consumer,
&wm8770->disable_nb[i]);
if (ret) {
dev_err(&spi->dev,
"Failed to register regulator notifier: %d\n",
ret);
}
}
wm8770->regmap = devm_regmap_init_spi(spi, &wm8770_regmap);
if (IS_ERR(wm8770->regmap))
return PTR_ERR(wm8770->regmap);
spi_set_drvdata(spi, wm8770);
ret = devm_snd_soc_register_component(&spi->dev,
&soc_component_dev_wm8770, &wm8770_dai, 1);
return ret;
}
static struct spi_driver wm8770_spi_driver = {
.driver = {
.name = "wm8770",
.of_match_table = wm8770_of_match,
},
.probe = wm8770_spi_probe,
};
module_spi_driver(wm8770_spi_driver);
MODULE_DESCRIPTION("ASoC WM8770 driver");
MODULE_AUTHOR("Dimitris Papastamos <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8770.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Driver for ADAU1361/ADAU1461/ADAU1761/ADAU1961 codec
*
* Copyright 2014 Analog Devices Inc.
* Author: Lars-Peter Clausen <[email protected]>
*/
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include <sound/soc.h>
#include "adau1761.h"
static void adau1761_spi_switch_mode(struct device *dev)
{
struct spi_device *spi = to_spi_device(dev);
/*
* To get the device into SPI mode CLATCH has to be pulled low three
* times. Do this by issuing three dummy reads.
*/
spi_w8r8(spi, 0x00);
spi_w8r8(spi, 0x00);
spi_w8r8(spi, 0x00);
}
static int adau1761_spi_probe(struct spi_device *spi)
{
const struct spi_device_id *id = spi_get_device_id(spi);
struct regmap_config config;
if (!id)
return -EINVAL;
config = adau1761_regmap_config;
config.val_bits = 8;
config.reg_bits = 24;
config.read_flag_mask = 0x1;
return adau1761_probe(&spi->dev,
devm_regmap_init_spi(spi, &config),
id->driver_data, adau1761_spi_switch_mode);
}
static void adau1761_spi_remove(struct spi_device *spi)
{
adau17x1_remove(&spi->dev);
}
static const struct spi_device_id adau1761_spi_id[] = {
{ "adau1361", ADAU1361 },
{ "adau1461", ADAU1761 },
{ "adau1761", ADAU1761 },
{ "adau1961", ADAU1361 },
{ }
};
MODULE_DEVICE_TABLE(spi, adau1761_spi_id);
#if defined(CONFIG_OF)
static const struct of_device_id adau1761_spi_dt_ids[] = {
{ .compatible = "adi,adau1361", },
{ .compatible = "adi,adau1461", },
{ .compatible = "adi,adau1761", },
{ .compatible = "adi,adau1961", },
{ },
};
MODULE_DEVICE_TABLE(of, adau1761_spi_dt_ids);
#endif
static struct spi_driver adau1761_spi_driver = {
.driver = {
.name = "adau1761",
.of_match_table = of_match_ptr(adau1761_spi_dt_ids),
},
.probe = adau1761_spi_probe,
.remove = adau1761_spi_remove,
.id_table = adau1761_spi_id,
};
module_spi_driver(adau1761_spi_driver);
MODULE_DESCRIPTION("ASoC ADAU1361/ADAU1461/ADAU1761/ADAU1961 CODEC SPI driver");
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/adau1761-spi.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8904.c -- WM8904 ALSA SoC Audio driver
*
* Copyright 2009-12 Wolfson Microelectronics plc
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/wm8904.h>
#include "wm8904.h"
enum wm8904_type {
WM8904,
WM8912,
};
#define WM8904_NUM_DCS_CHANNELS 4
#define WM8904_NUM_SUPPLIES 5
static const char *wm8904_supply_names[WM8904_NUM_SUPPLIES] = {
"DCVDD",
"DBVDD",
"AVDD",
"CPVDD",
"MICVDD",
};
/* codec private data */
struct wm8904_priv {
struct regmap *regmap;
struct clk *mclk;
enum wm8904_type devtype;
struct regulator_bulk_data supplies[WM8904_NUM_SUPPLIES];
struct wm8904_pdata *pdata;
int deemph;
/* Platform provided DRC configuration */
const char **drc_texts;
int drc_cfg;
struct soc_enum drc_enum;
/* Platform provided ReTune mobile configuration */
int num_retune_mobile_texts;
const char **retune_mobile_texts;
int retune_mobile_cfg;
struct soc_enum retune_mobile_enum;
/* FLL setup */
int fll_src;
int fll_fref;
int fll_fout;
/* Clocking configuration */
unsigned int mclk_rate;
int sysclk_src;
unsigned int sysclk_rate;
int tdm_width;
int tdm_slots;
int bclk;
int fs;
/* DC servo configuration - cached offset values */
int dcs_state[WM8904_NUM_DCS_CHANNELS];
};
static const struct reg_default wm8904_reg_defaults[] = {
{ 4, 0x0018 }, /* R4 - Bias Control 0 */
{ 5, 0x0000 }, /* R5 - VMID Control 0 */
{ 6, 0x0000 }, /* R6 - Mic Bias Control 0 */
{ 7, 0x0000 }, /* R7 - Mic Bias Control 1 */
{ 8, 0x0001 }, /* R8 - Analogue DAC 0 */
{ 9, 0x9696 }, /* R9 - mic Filter Control */
{ 10, 0x0001 }, /* R10 - Analogue ADC 0 */
{ 12, 0x0000 }, /* R12 - Power Management 0 */
{ 14, 0x0000 }, /* R14 - Power Management 2 */
{ 15, 0x0000 }, /* R15 - Power Management 3 */
{ 18, 0x0000 }, /* R18 - Power Management 6 */
{ 20, 0x945E }, /* R20 - Clock Rates 0 */
{ 21, 0x0C05 }, /* R21 - Clock Rates 1 */
{ 22, 0x0006 }, /* R22 - Clock Rates 2 */
{ 24, 0x0050 }, /* R24 - Audio Interface 0 */
{ 25, 0x000A }, /* R25 - Audio Interface 1 */
{ 26, 0x00E4 }, /* R26 - Audio Interface 2 */
{ 27, 0x0040 }, /* R27 - Audio Interface 3 */
{ 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */
{ 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */
{ 32, 0x0000 }, /* R32 - DAC Digital 0 */
{ 33, 0x0008 }, /* R33 - DAC Digital 1 */
{ 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */
{ 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */
{ 38, 0x0010 }, /* R38 - ADC Digital 0 */
{ 39, 0x0000 }, /* R39 - Digital Microphone 0 */
{ 40, 0x01AF }, /* R40 - DRC 0 */
{ 41, 0x3248 }, /* R41 - DRC 1 */
{ 42, 0x0000 }, /* R42 - DRC 2 */
{ 43, 0x0000 }, /* R43 - DRC 3 */
{ 44, 0x0085 }, /* R44 - Analogue Left Input 0 */
{ 45, 0x0085 }, /* R45 - Analogue Right Input 0 */
{ 46, 0x0044 }, /* R46 - Analogue Left Input 1 */
{ 47, 0x0044 }, /* R47 - Analogue Right Input 1 */
{ 57, 0x002D }, /* R57 - Analogue OUT1 Left */
{ 58, 0x002D }, /* R58 - Analogue OUT1 Right */
{ 59, 0x0039 }, /* R59 - Analogue OUT2 Left */
{ 60, 0x0039 }, /* R60 - Analogue OUT2 Right */
{ 61, 0x0000 }, /* R61 - Analogue OUT12 ZC */
{ 67, 0x0000 }, /* R67 - DC Servo 0 */
{ 69, 0xAAAA }, /* R69 - DC Servo 2 */
{ 71, 0xAAAA }, /* R71 - DC Servo 4 */
{ 72, 0xAAAA }, /* R72 - DC Servo 5 */
{ 90, 0x0000 }, /* R90 - Analogue HP 0 */
{ 94, 0x0000 }, /* R94 - Analogue Lineout 0 */
{ 98, 0x0000 }, /* R98 - Charge Pump 0 */
{ 104, 0x0004 }, /* R104 - Class W 0 */
{ 108, 0x0000 }, /* R108 - Write Sequencer 0 */
{ 109, 0x0000 }, /* R109 - Write Sequencer 1 */
{ 110, 0x0000 }, /* R110 - Write Sequencer 2 */
{ 111, 0x0000 }, /* R111 - Write Sequencer 3 */
{ 112, 0x0000 }, /* R112 - Write Sequencer 4 */
{ 116, 0x0000 }, /* R116 - FLL Control 1 */
{ 117, 0x0007 }, /* R117 - FLL Control 2 */
{ 118, 0x0000 }, /* R118 - FLL Control 3 */
{ 119, 0x2EE0 }, /* R119 - FLL Control 4 */
{ 120, 0x0004 }, /* R120 - FLL Control 5 */
{ 121, 0x0014 }, /* R121 - GPIO Control 1 */
{ 122, 0x0010 }, /* R122 - GPIO Control 2 */
{ 123, 0x0010 }, /* R123 - GPIO Control 3 */
{ 124, 0x0000 }, /* R124 - GPIO Control 4 */
{ 126, 0x0000 }, /* R126 - Digital Pulls */
{ 128, 0xFFFF }, /* R128 - Interrupt Status Mask */
{ 129, 0x0000 }, /* R129 - Interrupt Polarity */
{ 130, 0x0000 }, /* R130 - Interrupt Debounce */
{ 134, 0x0000 }, /* R134 - EQ1 */
{ 135, 0x000C }, /* R135 - EQ2 */
{ 136, 0x000C }, /* R136 - EQ3 */
{ 137, 0x000C }, /* R137 - EQ4 */
{ 138, 0x000C }, /* R138 - EQ5 */
{ 139, 0x000C }, /* R139 - EQ6 */
{ 140, 0x0FCA }, /* R140 - EQ7 */
{ 141, 0x0400 }, /* R141 - EQ8 */
{ 142, 0x00D8 }, /* R142 - EQ9 */
{ 143, 0x1EB5 }, /* R143 - EQ10 */
{ 144, 0xF145 }, /* R144 - EQ11 */
{ 145, 0x0B75 }, /* R145 - EQ12 */
{ 146, 0x01C5 }, /* R146 - EQ13 */
{ 147, 0x1C58 }, /* R147 - EQ14 */
{ 148, 0xF373 }, /* R148 - EQ15 */
{ 149, 0x0A54 }, /* R149 - EQ16 */
{ 150, 0x0558 }, /* R150 - EQ17 */
{ 151, 0x168E }, /* R151 - EQ18 */
{ 152, 0xF829 }, /* R152 - EQ19 */
{ 153, 0x07AD }, /* R153 - EQ20 */
{ 154, 0x1103 }, /* R154 - EQ21 */
{ 155, 0x0564 }, /* R155 - EQ22 */
{ 156, 0x0559 }, /* R156 - EQ23 */
{ 157, 0x4000 }, /* R157 - EQ24 */
{ 161, 0x0000 }, /* R161 - Control Interface Test 1 */
{ 204, 0x0000 }, /* R204 - Analogue Output Bias 0 */
{ 247, 0x0000 }, /* R247 - FLL NCO Test 0 */
{ 248, 0x0019 }, /* R248 - FLL NCO Test 1 */
};
static bool wm8904_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8904_SW_RESET_AND_ID:
case WM8904_REVISION:
case WM8904_DC_SERVO_1:
case WM8904_DC_SERVO_6:
case WM8904_DC_SERVO_7:
case WM8904_DC_SERVO_8:
case WM8904_DC_SERVO_9:
case WM8904_DC_SERVO_READBACK_0:
case WM8904_INTERRUPT_STATUS:
return true;
default:
return false;
}
}
static bool wm8904_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8904_SW_RESET_AND_ID:
case WM8904_REVISION:
case WM8904_BIAS_CONTROL_0:
case WM8904_VMID_CONTROL_0:
case WM8904_MIC_BIAS_CONTROL_0:
case WM8904_MIC_BIAS_CONTROL_1:
case WM8904_ANALOGUE_DAC_0:
case WM8904_MIC_FILTER_CONTROL:
case WM8904_ANALOGUE_ADC_0:
case WM8904_POWER_MANAGEMENT_0:
case WM8904_POWER_MANAGEMENT_2:
case WM8904_POWER_MANAGEMENT_3:
case WM8904_POWER_MANAGEMENT_6:
case WM8904_CLOCK_RATES_0:
case WM8904_CLOCK_RATES_1:
case WM8904_CLOCK_RATES_2:
case WM8904_AUDIO_INTERFACE_0:
case WM8904_AUDIO_INTERFACE_1:
case WM8904_AUDIO_INTERFACE_2:
case WM8904_AUDIO_INTERFACE_3:
case WM8904_DAC_DIGITAL_VOLUME_LEFT:
case WM8904_DAC_DIGITAL_VOLUME_RIGHT:
case WM8904_DAC_DIGITAL_0:
case WM8904_DAC_DIGITAL_1:
case WM8904_ADC_DIGITAL_VOLUME_LEFT:
case WM8904_ADC_DIGITAL_VOLUME_RIGHT:
case WM8904_ADC_DIGITAL_0:
case WM8904_DIGITAL_MICROPHONE_0:
case WM8904_DRC_0:
case WM8904_DRC_1:
case WM8904_DRC_2:
case WM8904_DRC_3:
case WM8904_ANALOGUE_LEFT_INPUT_0:
case WM8904_ANALOGUE_RIGHT_INPUT_0:
case WM8904_ANALOGUE_LEFT_INPUT_1:
case WM8904_ANALOGUE_RIGHT_INPUT_1:
case WM8904_ANALOGUE_OUT1_LEFT:
case WM8904_ANALOGUE_OUT1_RIGHT:
case WM8904_ANALOGUE_OUT2_LEFT:
case WM8904_ANALOGUE_OUT2_RIGHT:
case WM8904_ANALOGUE_OUT12_ZC:
case WM8904_DC_SERVO_0:
case WM8904_DC_SERVO_1:
case WM8904_DC_SERVO_2:
case WM8904_DC_SERVO_4:
case WM8904_DC_SERVO_5:
case WM8904_DC_SERVO_6:
case WM8904_DC_SERVO_7:
case WM8904_DC_SERVO_8:
case WM8904_DC_SERVO_9:
case WM8904_DC_SERVO_READBACK_0:
case WM8904_ANALOGUE_HP_0:
case WM8904_ANALOGUE_LINEOUT_0:
case WM8904_CHARGE_PUMP_0:
case WM8904_CLASS_W_0:
case WM8904_WRITE_SEQUENCER_0:
case WM8904_WRITE_SEQUENCER_1:
case WM8904_WRITE_SEQUENCER_2:
case WM8904_WRITE_SEQUENCER_3:
case WM8904_WRITE_SEQUENCER_4:
case WM8904_FLL_CONTROL_1:
case WM8904_FLL_CONTROL_2:
case WM8904_FLL_CONTROL_3:
case WM8904_FLL_CONTROL_4:
case WM8904_FLL_CONTROL_5:
case WM8904_GPIO_CONTROL_1:
case WM8904_GPIO_CONTROL_2:
case WM8904_GPIO_CONTROL_3:
case WM8904_GPIO_CONTROL_4:
case WM8904_DIGITAL_PULLS:
case WM8904_INTERRUPT_STATUS:
case WM8904_INTERRUPT_STATUS_MASK:
case WM8904_INTERRUPT_POLARITY:
case WM8904_INTERRUPT_DEBOUNCE:
case WM8904_EQ1:
case WM8904_EQ2:
case WM8904_EQ3:
case WM8904_EQ4:
case WM8904_EQ5:
case WM8904_EQ6:
case WM8904_EQ7:
case WM8904_EQ8:
case WM8904_EQ9:
case WM8904_EQ10:
case WM8904_EQ11:
case WM8904_EQ12:
case WM8904_EQ13:
case WM8904_EQ14:
case WM8904_EQ15:
case WM8904_EQ16:
case WM8904_EQ17:
case WM8904_EQ18:
case WM8904_EQ19:
case WM8904_EQ20:
case WM8904_EQ21:
case WM8904_EQ22:
case WM8904_EQ23:
case WM8904_EQ24:
case WM8904_CONTROL_INTERFACE_TEST_1:
case WM8904_ADC_TEST_0:
case WM8904_ANALOGUE_OUTPUT_BIAS_0:
case WM8904_FLL_NCO_TEST_0:
case WM8904_FLL_NCO_TEST_1:
return true;
default:
return false;
}
}
static int wm8904_configure_clocking(struct snd_soc_component *component)
{
struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
unsigned int clock0, clock2, rate;
/* Gate the clock while we're updating to avoid misclocking */
clock2 = snd_soc_component_read(component, WM8904_CLOCK_RATES_2);
snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2,
WM8904_SYSCLK_SRC, 0);
/* This should be done on init() for bypass paths */
switch (wm8904->sysclk_src) {
case WM8904_CLK_MCLK:
dev_dbg(component->dev, "Using %dHz MCLK\n", wm8904->mclk_rate);
clock2 &= ~WM8904_SYSCLK_SRC;
rate = wm8904->mclk_rate;
/* Ensure the FLL is stopped */
snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
break;
case WM8904_CLK_FLL:
dev_dbg(component->dev, "Using %dHz FLL clock\n",
wm8904->fll_fout);
clock2 |= WM8904_SYSCLK_SRC;
rate = wm8904->fll_fout;
break;
default:
dev_err(component->dev, "System clock not configured\n");
return -EINVAL;
}
/* SYSCLK shouldn't be over 13.5MHz */
if (rate > 13500000) {
clock0 = WM8904_MCLK_DIV;
wm8904->sysclk_rate = rate / 2;
} else {
clock0 = 0;
wm8904->sysclk_rate = rate;
}
snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_0, WM8904_MCLK_DIV,
clock0);
snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2,
WM8904_CLK_SYS_ENA | WM8904_SYSCLK_SRC, clock2);
dev_dbg(component->dev, "CLK_SYS is %dHz\n", wm8904->sysclk_rate);
return 0;
}
static void wm8904_set_drc(struct snd_soc_component *component)
{
struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
struct wm8904_pdata *pdata = wm8904->pdata;
int save, i;
/* Save any enables; the configuration should clear them. */
save = snd_soc_component_read(component, WM8904_DRC_0);
for (i = 0; i < WM8904_DRC_REGS; i++)
snd_soc_component_update_bits(component, WM8904_DRC_0 + i, 0xffff,
pdata->drc_cfgs[wm8904->drc_cfg].regs[i]);
/* Reenable the DRC */
snd_soc_component_update_bits(component, WM8904_DRC_0,
WM8904_DRC_ENA | WM8904_DRC_DAC_PATH, save);
}
static int wm8904_put_drc_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
struct wm8904_pdata *pdata = wm8904->pdata;
int value = ucontrol->value.enumerated.item[0];
if (value >= pdata->num_drc_cfgs)
return -EINVAL;
wm8904->drc_cfg = value;
wm8904_set_drc(component);
return 0;
}
static int wm8904_get_drc_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
ucontrol->value.enumerated.item[0] = wm8904->drc_cfg;
return 0;
}
static void wm8904_set_retune_mobile(struct snd_soc_component *component)
{
struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
struct wm8904_pdata *pdata = wm8904->pdata;
int best, best_val, save, i, cfg;
if (!pdata || !wm8904->num_retune_mobile_texts)
return;
/* Find the version of the currently selected configuration
* with the nearest sample rate. */
cfg = wm8904->retune_mobile_cfg;
best = 0;
best_val = INT_MAX;
for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
if (strcmp(pdata->retune_mobile_cfgs[i].name,
wm8904->retune_mobile_texts[cfg]) == 0 &&
abs(pdata->retune_mobile_cfgs[i].rate
- wm8904->fs) < best_val) {
best = i;
best_val = abs(pdata->retune_mobile_cfgs[i].rate
- wm8904->fs);
}
}
dev_dbg(component->dev, "ReTune Mobile %s/%dHz for %dHz sample rate\n",
pdata->retune_mobile_cfgs[best].name,
pdata->retune_mobile_cfgs[best].rate,
wm8904->fs);
/* The EQ will be disabled while reconfiguring it, remember the
* current configuration.
*/
save = snd_soc_component_read(component, WM8904_EQ1);
for (i = 0; i < WM8904_EQ_REGS; i++)
snd_soc_component_update_bits(component, WM8904_EQ1 + i, 0xffff,
pdata->retune_mobile_cfgs[best].regs[i]);
snd_soc_component_update_bits(component, WM8904_EQ1, WM8904_EQ_ENA, save);
}
static int wm8904_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
struct wm8904_pdata *pdata = wm8904->pdata;
int value = ucontrol->value.enumerated.item[0];
if (value >= pdata->num_retune_mobile_cfgs)
return -EINVAL;
wm8904->retune_mobile_cfg = value;
wm8904_set_retune_mobile(component);
return 0;
}
static int wm8904_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
ucontrol->value.enumerated.item[0] = wm8904->retune_mobile_cfg;
return 0;
}
static int deemph_settings[] = { 0, 32000, 44100, 48000 };
static int wm8904_set_deemph(struct snd_soc_component *component)
{
struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
int val, i, best;
/* If we're using deemphasis select the nearest available sample
* rate.
*/
if (wm8904->deemph) {
best = 1;
for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
if (abs(deemph_settings[i] - wm8904->fs) <
abs(deemph_settings[best] - wm8904->fs))
best = i;
}
val = best << WM8904_DEEMPH_SHIFT;
} else {
val = 0;
}
dev_dbg(component->dev, "Set deemphasis %d\n", val);
return snd_soc_component_update_bits(component, WM8904_DAC_DIGITAL_1,
WM8904_DEEMPH_MASK, val);
}
static int wm8904_get_deemph(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = wm8904->deemph;
return 0;
}
static int wm8904_put_deemph(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
unsigned int deemph = ucontrol->value.integer.value[0];
if (deemph > 1)
return -EINVAL;
wm8904->deemph = deemph;
return wm8904_set_deemph(component);
}
static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
static const char *hpf_mode_text[] = {
"Hi-fi", "Voice 1", "Voice 2", "Voice 3"
};
static SOC_ENUM_SINGLE_DECL(hpf_mode, WM8904_ADC_DIGITAL_0, 5,
hpf_mode_text);
static int wm8904_adc_osr_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
unsigned int val;
int ret;
ret = snd_soc_put_volsw(kcontrol, ucontrol);
if (ret < 0)
return ret;
if (ucontrol->value.integer.value[0])
val = 0;
else
val = WM8904_ADC_128_OSR_TST_MODE | WM8904_ADC_BIASX1P5;
snd_soc_component_update_bits(component, WM8904_ADC_TEST_0,
WM8904_ADC_128_OSR_TST_MODE | WM8904_ADC_BIASX1P5,
val);
return ret;
}
static const struct snd_kcontrol_new wm8904_adc_snd_controls[] = {
SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8904_ADC_DIGITAL_VOLUME_LEFT,
WM8904_ADC_DIGITAL_VOLUME_RIGHT, 1, 119, 0, digital_tlv),
/* No TLV since it depends on mode */
SOC_DOUBLE_R("Capture Volume", WM8904_ANALOGUE_LEFT_INPUT_0,
WM8904_ANALOGUE_RIGHT_INPUT_0, 0, 31, 0),
SOC_DOUBLE_R("Capture Switch", WM8904_ANALOGUE_LEFT_INPUT_0,
WM8904_ANALOGUE_RIGHT_INPUT_0, 7, 1, 1),
SOC_SINGLE("High Pass Filter Switch", WM8904_ADC_DIGITAL_0, 4, 1, 0),
SOC_ENUM("High Pass Filter Mode", hpf_mode),
SOC_SINGLE_EXT("ADC 128x OSR Switch", WM8904_ANALOGUE_ADC_0, 0, 1, 0,
snd_soc_get_volsw, wm8904_adc_osr_put),
};
static const char *drc_path_text[] = {
"ADC", "DAC"
};
static SOC_ENUM_SINGLE_DECL(drc_path, WM8904_DRC_0, 14, drc_path_text);
static const struct snd_kcontrol_new wm8904_dac_snd_controls[] = {
SOC_SINGLE_TLV("Digital Playback Boost Volume",
WM8904_AUDIO_INTERFACE_0, 9, 3, 0, dac_boost_tlv),
SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8904_DAC_DIGITAL_VOLUME_LEFT,
WM8904_DAC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
SOC_DOUBLE_R_TLV("Headphone Volume", WM8904_ANALOGUE_OUT1_LEFT,
WM8904_ANALOGUE_OUT1_RIGHT, 0, 63, 0, out_tlv),
SOC_DOUBLE_R("Headphone Switch", WM8904_ANALOGUE_OUT1_LEFT,
WM8904_ANALOGUE_OUT1_RIGHT, 8, 1, 1),
SOC_DOUBLE_R("Headphone ZC Switch", WM8904_ANALOGUE_OUT1_LEFT,
WM8904_ANALOGUE_OUT1_RIGHT, 6, 1, 0),
SOC_DOUBLE_R_TLV("Line Output Volume", WM8904_ANALOGUE_OUT2_LEFT,
WM8904_ANALOGUE_OUT2_RIGHT, 0, 63, 0, out_tlv),
SOC_DOUBLE_R("Line Output Switch", WM8904_ANALOGUE_OUT2_LEFT,
WM8904_ANALOGUE_OUT2_RIGHT, 8, 1, 1),
SOC_DOUBLE_R("Line Output ZC Switch", WM8904_ANALOGUE_OUT2_LEFT,
WM8904_ANALOGUE_OUT2_RIGHT, 6, 1, 0),
SOC_SINGLE("EQ Switch", WM8904_EQ1, 0, 1, 0),
SOC_SINGLE("DRC Switch", WM8904_DRC_0, 15, 1, 0),
SOC_ENUM("DRC Path", drc_path),
SOC_SINGLE("DAC OSRx2 Switch", WM8904_DAC_DIGITAL_1, 6, 1, 0),
SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
wm8904_get_deemph, wm8904_put_deemph),
};
static const struct snd_kcontrol_new wm8904_snd_controls[] = {
SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8904_DAC_DIGITAL_0, 4, 8, 15, 0,
sidetone_tlv),
};
static const struct snd_kcontrol_new wm8904_eq_controls[] = {
SOC_SINGLE_TLV("EQ1 Volume", WM8904_EQ2, 0, 24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ2 Volume", WM8904_EQ3, 0, 24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ3 Volume", WM8904_EQ4, 0, 24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ4 Volume", WM8904_EQ5, 0, 24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ5 Volume", WM8904_EQ6, 0, 24, 0, eq_tlv),
};
static int cp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
if (WARN_ON(event != SND_SOC_DAPM_POST_PMU))
return -EINVAL;
/* Maximum startup time */
udelay(500);
return 0;
}
static int sysclk_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* If we're using the FLL then we only start it when
* required; we assume that the configuration has been
* done previously and all we need to do is kick it
* off.
*/
switch (wm8904->sysclk_src) {
case WM8904_CLK_FLL:
snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
WM8904_FLL_OSC_ENA,
WM8904_FLL_OSC_ENA);
snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
WM8904_FLL_ENA,
WM8904_FLL_ENA);
break;
default:
break;
}
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
break;
}
return 0;
}
static int out_pga_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
int reg, val;
int dcs_mask;
int dcs_l, dcs_r;
int dcs_l_reg, dcs_r_reg;
int an_out_reg;
int timeout;
int pwr_reg;
/* This code is shared between HP and LINEOUT; we do all our
* power management in stereo pairs to avoid latency issues so
* we reuse shift to identify which rather than strcmp() the
* name. */
reg = w->shift;
switch (reg) {
case WM8904_ANALOGUE_HP_0:
pwr_reg = WM8904_POWER_MANAGEMENT_2;
dcs_mask = WM8904_DCS_ENA_CHAN_0 | WM8904_DCS_ENA_CHAN_1;
dcs_r_reg = WM8904_DC_SERVO_8;
dcs_l_reg = WM8904_DC_SERVO_9;
an_out_reg = WM8904_ANALOGUE_OUT1_LEFT;
dcs_l = 0;
dcs_r = 1;
break;
case WM8904_ANALOGUE_LINEOUT_0:
pwr_reg = WM8904_POWER_MANAGEMENT_3;
dcs_mask = WM8904_DCS_ENA_CHAN_2 | WM8904_DCS_ENA_CHAN_3;
dcs_r_reg = WM8904_DC_SERVO_6;
dcs_l_reg = WM8904_DC_SERVO_7;
an_out_reg = WM8904_ANALOGUE_OUT2_LEFT;
dcs_l = 2;
dcs_r = 3;
break;
default:
WARN(1, "Invalid reg %d\n", reg);
return -EINVAL;
}
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* Power on the PGAs */
snd_soc_component_update_bits(component, pwr_reg,
WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA,
WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA);
/* Power on the amplifier */
snd_soc_component_update_bits(component, reg,
WM8904_HPL_ENA | WM8904_HPR_ENA,
WM8904_HPL_ENA | WM8904_HPR_ENA);
/* Enable the first stage */
snd_soc_component_update_bits(component, reg,
WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY,
WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY);
/* Power up the DC servo */
snd_soc_component_update_bits(component, WM8904_DC_SERVO_0,
dcs_mask, dcs_mask);
/* Either calibrate the DC servo or restore cached state
* if we have that.
*/
if (wm8904->dcs_state[dcs_l] || wm8904->dcs_state[dcs_r]) {
dev_dbg(component->dev, "Restoring DC servo state\n");
snd_soc_component_write(component, dcs_l_reg,
wm8904->dcs_state[dcs_l]);
snd_soc_component_write(component, dcs_r_reg,
wm8904->dcs_state[dcs_r]);
snd_soc_component_write(component, WM8904_DC_SERVO_1, dcs_mask);
timeout = 20;
} else {
dev_dbg(component->dev, "Calibrating DC servo\n");
snd_soc_component_write(component, WM8904_DC_SERVO_1,
dcs_mask << WM8904_DCS_TRIG_STARTUP_0_SHIFT);
timeout = 500;
}
/* Wait for DC servo to complete */
dcs_mask <<= WM8904_DCS_CAL_COMPLETE_SHIFT;
do {
val = snd_soc_component_read(component, WM8904_DC_SERVO_READBACK_0);
if ((val & dcs_mask) == dcs_mask)
break;
msleep(1);
} while (--timeout);
if ((val & dcs_mask) != dcs_mask)
dev_warn(component->dev, "DC servo timed out\n");
else
dev_dbg(component->dev, "DC servo ready\n");
/* Enable the output stage */
snd_soc_component_update_bits(component, reg,
WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP,
WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP);
/* Update volume, requires PGA to be powered */
val = snd_soc_component_read(component, an_out_reg);
snd_soc_component_write(component, an_out_reg, val);
break;
case SND_SOC_DAPM_POST_PMU:
/* Unshort the output itself */
snd_soc_component_update_bits(component, reg,
WM8904_HPL_RMV_SHORT |
WM8904_HPR_RMV_SHORT,
WM8904_HPL_RMV_SHORT |
WM8904_HPR_RMV_SHORT);
break;
case SND_SOC_DAPM_PRE_PMD:
/* Short the output */
snd_soc_component_update_bits(component, reg,
WM8904_HPL_RMV_SHORT |
WM8904_HPR_RMV_SHORT, 0);
break;
case SND_SOC_DAPM_POST_PMD:
/* Cache the DC servo configuration; this will be
* invalidated if we change the configuration. */
wm8904->dcs_state[dcs_l] = snd_soc_component_read(component, dcs_l_reg);
wm8904->dcs_state[dcs_r] = snd_soc_component_read(component, dcs_r_reg);
snd_soc_component_update_bits(component, WM8904_DC_SERVO_0,
dcs_mask, 0);
/* Disable the amplifier input and output stages */
snd_soc_component_update_bits(component, reg,
WM8904_HPL_ENA | WM8904_HPR_ENA |
WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY |
WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP,
0);
/* PGAs too */
snd_soc_component_update_bits(component, pwr_reg,
WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA,
0);
break;
}
return 0;
}
static const char *input_mode_text[] = {
"Single-Ended", "Differential Line", "Differential Mic"
};
static const char *lin_text[] = {
"IN1L", "IN2L", "IN3L"
};
static SOC_ENUM_SINGLE_DECL(lin_enum, WM8904_ANALOGUE_LEFT_INPUT_1, 2,
lin_text);
static const struct snd_kcontrol_new lin_mux =
SOC_DAPM_ENUM("Left Capture Mux", lin_enum);
static SOC_ENUM_SINGLE_DECL(lin_inv_enum, WM8904_ANALOGUE_LEFT_INPUT_1, 4,
lin_text);
static const struct snd_kcontrol_new lin_inv_mux =
SOC_DAPM_ENUM("Left Capture Inverting Mux", lin_inv_enum);
static SOC_ENUM_SINGLE_DECL(lin_mode_enum,
WM8904_ANALOGUE_LEFT_INPUT_1, 0,
input_mode_text);
static const struct snd_kcontrol_new lin_mode =
SOC_DAPM_ENUM("Left Capture Mode", lin_mode_enum);
static const char *rin_text[] = {
"IN1R", "IN2R", "IN3R"
};
static SOC_ENUM_SINGLE_DECL(rin_enum, WM8904_ANALOGUE_RIGHT_INPUT_1, 2,
rin_text);
static const struct snd_kcontrol_new rin_mux =
SOC_DAPM_ENUM("Right Capture Mux", rin_enum);
static SOC_ENUM_SINGLE_DECL(rin_inv_enum, WM8904_ANALOGUE_RIGHT_INPUT_1, 4,
rin_text);
static const struct snd_kcontrol_new rin_inv_mux =
SOC_DAPM_ENUM("Right Capture Inverting Mux", rin_inv_enum);
static SOC_ENUM_SINGLE_DECL(rin_mode_enum,
WM8904_ANALOGUE_RIGHT_INPUT_1, 0,
input_mode_text);
static const struct snd_kcontrol_new rin_mode =
SOC_DAPM_ENUM("Right Capture Mode", rin_mode_enum);
static const char *aif_text[] = {
"Left", "Right"
};
static SOC_ENUM_SINGLE_DECL(aifoutl_enum, WM8904_AUDIO_INTERFACE_0, 7,
aif_text);
static const struct snd_kcontrol_new aifoutl_mux =
SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum);
static SOC_ENUM_SINGLE_DECL(aifoutr_enum, WM8904_AUDIO_INTERFACE_0, 6,
aif_text);
static const struct snd_kcontrol_new aifoutr_mux =
SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum);
static SOC_ENUM_SINGLE_DECL(aifinl_enum, WM8904_AUDIO_INTERFACE_0, 5,
aif_text);
static const struct snd_kcontrol_new aifinl_mux =
SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum);
static SOC_ENUM_SINGLE_DECL(aifinr_enum, WM8904_AUDIO_INTERFACE_0, 4,
aif_text);
static const struct snd_kcontrol_new aifinr_mux =
SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum);
static const struct snd_soc_dapm_widget wm8904_core_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("SYSCLK", WM8904_CLOCK_RATES_2, 2, 0, sysclk_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8904_CLOCK_RATES_2, 1, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("TOCLK", WM8904_CLOCK_RATES_2, 0, 0, NULL, 0),
};
static const struct snd_soc_dapm_widget wm8904_adc_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("IN1L"),
SND_SOC_DAPM_INPUT("IN1R"),
SND_SOC_DAPM_INPUT("IN2L"),
SND_SOC_DAPM_INPUT("IN2R"),
SND_SOC_DAPM_INPUT("IN3L"),
SND_SOC_DAPM_INPUT("IN3R"),
SND_SOC_DAPM_SUPPLY("MICBIAS", WM8904_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lin_mux),
SND_SOC_DAPM_MUX("Left Capture Inverting Mux", SND_SOC_NOPM, 0, 0,
&lin_inv_mux),
SND_SOC_DAPM_MUX("Left Capture Mode", SND_SOC_NOPM, 0, 0, &lin_mode),
SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rin_mux),
SND_SOC_DAPM_MUX("Right Capture Inverting Mux", SND_SOC_NOPM, 0, 0,
&rin_inv_mux),
SND_SOC_DAPM_MUX("Right Capture Mode", SND_SOC_NOPM, 0, 0, &rin_mode),
SND_SOC_DAPM_PGA("Left Capture PGA", WM8904_POWER_MANAGEMENT_0, 1, 0,
NULL, 0),
SND_SOC_DAPM_PGA("Right Capture PGA", WM8904_POWER_MANAGEMENT_0, 0, 0,
NULL, 0),
SND_SOC_DAPM_ADC("ADCL", NULL, WM8904_POWER_MANAGEMENT_6, 1, 0),
SND_SOC_DAPM_ADC("ADCR", NULL, WM8904_POWER_MANAGEMENT_6, 0, 0),
SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux),
SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux),
SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
};
static const struct snd_soc_dapm_widget wm8904_dac_dapm_widgets[] = {
SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux),
SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux),
SND_SOC_DAPM_DAC("DACL", NULL, WM8904_POWER_MANAGEMENT_6, 3, 0),
SND_SOC_DAPM_DAC("DACR", NULL, WM8904_POWER_MANAGEMENT_6, 2, 0),
SND_SOC_DAPM_SUPPLY("Charge pump", WM8904_CHARGE_PUMP_0, 0, 0, cp_event,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA("HPL PGA", SND_SOC_NOPM, 1, 0, NULL, 0),
SND_SOC_DAPM_PGA("HPR PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("LINEL PGA", SND_SOC_NOPM, 1, 0, NULL, 0),
SND_SOC_DAPM_PGA("LINER PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM, WM8904_ANALOGUE_HP_0,
0, NULL, 0, out_pga_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("Line Output", SND_SOC_NOPM, WM8904_ANALOGUE_LINEOUT_0,
0, NULL, 0, out_pga_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_OUTPUT("HPOUTL"),
SND_SOC_DAPM_OUTPUT("HPOUTR"),
SND_SOC_DAPM_OUTPUT("LINEOUTL"),
SND_SOC_DAPM_OUTPUT("LINEOUTR"),
};
static const char *out_mux_text[] = {
"DAC", "Bypass"
};
static SOC_ENUM_SINGLE_DECL(hpl_enum, WM8904_ANALOGUE_OUT12_ZC, 3,
out_mux_text);
static const struct snd_kcontrol_new hpl_mux =
SOC_DAPM_ENUM("HPL Mux", hpl_enum);
static SOC_ENUM_SINGLE_DECL(hpr_enum, WM8904_ANALOGUE_OUT12_ZC, 2,
out_mux_text);
static const struct snd_kcontrol_new hpr_mux =
SOC_DAPM_ENUM("HPR Mux", hpr_enum);
static SOC_ENUM_SINGLE_DECL(linel_enum, WM8904_ANALOGUE_OUT12_ZC, 1,
out_mux_text);
static const struct snd_kcontrol_new linel_mux =
SOC_DAPM_ENUM("LINEL Mux", linel_enum);
static SOC_ENUM_SINGLE_DECL(liner_enum, WM8904_ANALOGUE_OUT12_ZC, 0,
out_mux_text);
static const struct snd_kcontrol_new liner_mux =
SOC_DAPM_ENUM("LINER Mux", liner_enum);
static const char *sidetone_text[] = {
"None", "Left", "Right"
};
static SOC_ENUM_SINGLE_DECL(dacl_sidetone_enum, WM8904_DAC_DIGITAL_0, 2,
sidetone_text);
static const struct snd_kcontrol_new dacl_sidetone_mux =
SOC_DAPM_ENUM("Left Sidetone Mux", dacl_sidetone_enum);
static SOC_ENUM_SINGLE_DECL(dacr_sidetone_enum, WM8904_DAC_DIGITAL_0, 0,
sidetone_text);
static const struct snd_kcontrol_new dacr_sidetone_mux =
SOC_DAPM_ENUM("Right Sidetone Mux", dacr_sidetone_enum);
static const struct snd_soc_dapm_widget wm8904_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("Class G", WM8904_CLASS_W_0, 0, 1, NULL, 0),
SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &dacl_sidetone_mux),
SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &dacr_sidetone_mux),
SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
SND_SOC_DAPM_MUX("LINEL Mux", SND_SOC_NOPM, 0, 0, &linel_mux),
SND_SOC_DAPM_MUX("LINER Mux", SND_SOC_NOPM, 0, 0, &liner_mux),
};
static const struct snd_soc_dapm_route core_intercon[] = {
{ "CLK_DSP", NULL, "SYSCLK" },
{ "TOCLK", NULL, "SYSCLK" },
};
static const struct snd_soc_dapm_route adc_intercon[] = {
{ "Left Capture Mux", "IN1L", "IN1L" },
{ "Left Capture Mux", "IN2L", "IN2L" },
{ "Left Capture Mux", "IN3L", "IN3L" },
{ "Left Capture Inverting Mux", "IN1L", "IN1L" },
{ "Left Capture Inverting Mux", "IN2L", "IN2L" },
{ "Left Capture Inverting Mux", "IN3L", "IN3L" },
{ "Left Capture Mode", "Single-Ended", "Left Capture Inverting Mux" },
{ "Left Capture Mode", "Differential Line", "Left Capture Mux" },
{ "Left Capture Mode", "Differential Line", "Left Capture Inverting Mux" },
{ "Left Capture Mode", "Differential Mic", "Left Capture Mux" },
{ "Left Capture Mode", "Differential Mic", "Left Capture Inverting Mux" },
{ "Right Capture Mux", "IN1R", "IN1R" },
{ "Right Capture Mux", "IN2R", "IN2R" },
{ "Right Capture Mux", "IN3R", "IN3R" },
{ "Right Capture Inverting Mux", "IN1R", "IN1R" },
{ "Right Capture Inverting Mux", "IN2R", "IN2R" },
{ "Right Capture Inverting Mux", "IN3R", "IN3R" },
{ "Right Capture Mode", "Single-Ended", "Right Capture Inverting Mux" },
{ "Right Capture Mode", "Differential Line", "Right Capture Mux" },
{ "Right Capture Mode", "Differential Line", "Right Capture Inverting Mux" },
{ "Right Capture Mode", "Differential Mic", "Right Capture Mux" },
{ "Right Capture Mode", "Differential Mic", "Right Capture Inverting Mux" },
{ "Left Capture PGA", NULL, "Left Capture Mode" },
{ "Right Capture PGA", NULL, "Right Capture Mode" },
{ "AIFOUTL Mux", "Left", "ADCL" },
{ "AIFOUTL Mux", "Right", "ADCR" },
{ "AIFOUTR Mux", "Left", "ADCL" },
{ "AIFOUTR Mux", "Right", "ADCR" },
{ "AIFOUTL", NULL, "AIFOUTL Mux" },
{ "AIFOUTR", NULL, "AIFOUTR Mux" },
{ "ADCL", NULL, "CLK_DSP" },
{ "ADCL", NULL, "Left Capture PGA" },
{ "ADCR", NULL, "CLK_DSP" },
{ "ADCR", NULL, "Right Capture PGA" },
};
static const struct snd_soc_dapm_route dac_intercon[] = {
{ "DACL Mux", "Left", "AIFINL" },
{ "DACL Mux", "Right", "AIFINR" },
{ "DACR Mux", "Left", "AIFINL" },
{ "DACR Mux", "Right", "AIFINR" },
{ "DACL", NULL, "DACL Mux" },
{ "DACL", NULL, "CLK_DSP" },
{ "DACR", NULL, "DACR Mux" },
{ "DACR", NULL, "CLK_DSP" },
{ "Charge pump", NULL, "SYSCLK" },
{ "Headphone Output", NULL, "HPL PGA" },
{ "Headphone Output", NULL, "HPR PGA" },
{ "Headphone Output", NULL, "Charge pump" },
{ "Headphone Output", NULL, "TOCLK" },
{ "Line Output", NULL, "LINEL PGA" },
{ "Line Output", NULL, "LINER PGA" },
{ "Line Output", NULL, "Charge pump" },
{ "Line Output", NULL, "TOCLK" },
{ "HPOUTL", NULL, "Headphone Output" },
{ "HPOUTR", NULL, "Headphone Output" },
{ "LINEOUTL", NULL, "Line Output" },
{ "LINEOUTR", NULL, "Line Output" },
};
static const struct snd_soc_dapm_route wm8904_intercon[] = {
{ "Left Sidetone", "Left", "ADCL" },
{ "Left Sidetone", "Right", "ADCR" },
{ "DACL", NULL, "Left Sidetone" },
{ "Right Sidetone", "Left", "ADCL" },
{ "Right Sidetone", "Right", "ADCR" },
{ "DACR", NULL, "Right Sidetone" },
{ "Left Bypass", NULL, "Class G" },
{ "Left Bypass", NULL, "Left Capture PGA" },
{ "Right Bypass", NULL, "Class G" },
{ "Right Bypass", NULL, "Right Capture PGA" },
{ "HPL Mux", "DAC", "DACL" },
{ "HPL Mux", "Bypass", "Left Bypass" },
{ "HPR Mux", "DAC", "DACR" },
{ "HPR Mux", "Bypass", "Right Bypass" },
{ "LINEL Mux", "DAC", "DACL" },
{ "LINEL Mux", "Bypass", "Left Bypass" },
{ "LINER Mux", "DAC", "DACR" },
{ "LINER Mux", "Bypass", "Right Bypass" },
{ "HPL PGA", NULL, "HPL Mux" },
{ "HPR PGA", NULL, "HPR Mux" },
{ "LINEL PGA", NULL, "LINEL Mux" },
{ "LINER PGA", NULL, "LINER Mux" },
};
static const struct snd_soc_dapm_route wm8912_intercon[] = {
{ "HPL PGA", NULL, "DACL" },
{ "HPR PGA", NULL, "DACR" },
{ "LINEL PGA", NULL, "DACL" },
{ "LINER PGA", NULL, "DACR" },
};
static int wm8904_add_widgets(struct snd_soc_component *component)
{
struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
snd_soc_dapm_new_controls(dapm, wm8904_core_dapm_widgets,
ARRAY_SIZE(wm8904_core_dapm_widgets));
snd_soc_dapm_add_routes(dapm, core_intercon,
ARRAY_SIZE(core_intercon));
switch (wm8904->devtype) {
case WM8904:
snd_soc_add_component_controls(component, wm8904_adc_snd_controls,
ARRAY_SIZE(wm8904_adc_snd_controls));
snd_soc_add_component_controls(component, wm8904_dac_snd_controls,
ARRAY_SIZE(wm8904_dac_snd_controls));
snd_soc_add_component_controls(component, wm8904_snd_controls,
ARRAY_SIZE(wm8904_snd_controls));
snd_soc_dapm_new_controls(dapm, wm8904_adc_dapm_widgets,
ARRAY_SIZE(wm8904_adc_dapm_widgets));
snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets,
ARRAY_SIZE(wm8904_dac_dapm_widgets));
snd_soc_dapm_new_controls(dapm, wm8904_dapm_widgets,
ARRAY_SIZE(wm8904_dapm_widgets));
snd_soc_dapm_add_routes(dapm, adc_intercon,
ARRAY_SIZE(adc_intercon));
snd_soc_dapm_add_routes(dapm, dac_intercon,
ARRAY_SIZE(dac_intercon));
snd_soc_dapm_add_routes(dapm, wm8904_intercon,
ARRAY_SIZE(wm8904_intercon));
break;
case WM8912:
snd_soc_add_component_controls(component, wm8904_dac_snd_controls,
ARRAY_SIZE(wm8904_dac_snd_controls));
snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets,
ARRAY_SIZE(wm8904_dac_dapm_widgets));
snd_soc_dapm_add_routes(dapm, dac_intercon,
ARRAY_SIZE(dac_intercon));
snd_soc_dapm_add_routes(dapm, wm8912_intercon,
ARRAY_SIZE(wm8912_intercon));
break;
}
return 0;
}
static struct {
int ratio;
unsigned int clk_sys_rate;
} clk_sys_rates[] = {
{ 64, 0 },
{ 128, 1 },
{ 192, 2 },
{ 256, 3 },
{ 384, 4 },
{ 512, 5 },
{ 786, 6 },
{ 1024, 7 },
{ 1408, 8 },
{ 1536, 9 },
};
static struct {
int rate;
int sample_rate;
} sample_rates[] = {
{ 8000, 0 },
{ 11025, 1 },
{ 12000, 1 },
{ 16000, 2 },
{ 22050, 3 },
{ 24000, 3 },
{ 32000, 4 },
{ 44100, 5 },
{ 48000, 5 },
};
static struct {
int div; /* *10 due to .5s */
int bclk_div;
} bclk_divs[] = {
{ 10, 0 },
{ 15, 1 },
{ 20, 2 },
{ 30, 3 },
{ 40, 4 },
{ 50, 5 },
{ 55, 6 },
{ 60, 7 },
{ 80, 8 },
{ 100, 9 },
{ 110, 10 },
{ 120, 11 },
{ 160, 12 },
{ 200, 13 },
{ 220, 14 },
{ 240, 16 },
{ 200, 17 },
{ 320, 18 },
{ 440, 19 },
{ 480, 20 },
};
static int wm8904_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
int ret, i, best, best_val, cur_val;
unsigned int aif1 = 0;
unsigned int aif2 = 0;
unsigned int aif3 = 0;
unsigned int clock1 = 0;
unsigned int dac_digital1 = 0;
/* What BCLK do we need? */
wm8904->fs = params_rate(params);
if (wm8904->tdm_slots) {
dev_dbg(component->dev, "Configuring for %d %d bit TDM slots\n",
wm8904->tdm_slots, wm8904->tdm_width);
wm8904->bclk = snd_soc_calc_bclk(wm8904->fs,
wm8904->tdm_width, 2,
wm8904->tdm_slots);
} else {
wm8904->bclk = snd_soc_params_to_bclk(params);
}
switch (params_width(params)) {
case 16:
break;
case 20:
aif1 |= 0x40;
break;
case 24:
aif1 |= 0x80;
break;
case 32:
aif1 |= 0xc0;
break;
default:
return -EINVAL;
}
dev_dbg(component->dev, "Target BCLK is %dHz\n", wm8904->bclk);
ret = wm8904_configure_clocking(component);
if (ret != 0)
return ret;
/* Select nearest CLK_SYS_RATE */
best = 0;
best_val = abs((wm8904->sysclk_rate / clk_sys_rates[0].ratio)
- wm8904->fs);
for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
cur_val = abs((wm8904->sysclk_rate /
clk_sys_rates[i].ratio) - wm8904->fs);
if (cur_val < best_val) {
best = i;
best_val = cur_val;
}
}
dev_dbg(component->dev, "Selected CLK_SYS_RATIO of %d\n",
clk_sys_rates[best].ratio);
clock1 |= (clk_sys_rates[best].clk_sys_rate
<< WM8904_CLK_SYS_RATE_SHIFT);
/* SAMPLE_RATE */
best = 0;
best_val = abs(wm8904->fs - sample_rates[0].rate);
for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
/* Closest match */
cur_val = abs(wm8904->fs - sample_rates[i].rate);
if (cur_val < best_val) {
best = i;
best_val = cur_val;
}
}
dev_dbg(component->dev, "Selected SAMPLE_RATE of %dHz\n",
sample_rates[best].rate);
clock1 |= (sample_rates[best].sample_rate
<< WM8904_SAMPLE_RATE_SHIFT);
/* Enable sloping stopband filter for low sample rates */
if (wm8904->fs <= 24000)
dac_digital1 |= WM8904_DAC_SB_FILT;
/* BCLK_DIV */
best = 0;
best_val = INT_MAX;
for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
cur_val = ((wm8904->sysclk_rate * 10) / bclk_divs[i].div)
- wm8904->bclk;
if (cur_val < 0) /* Table is sorted */
break;
if (cur_val < best_val) {
best = i;
best_val = cur_val;
}
}
wm8904->bclk = (wm8904->sysclk_rate * 10) / bclk_divs[best].div;
dev_dbg(component->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
bclk_divs[best].div, wm8904->bclk);
aif2 |= bclk_divs[best].bclk_div;
/* LRCLK is a simple fraction of BCLK */
dev_dbg(component->dev, "LRCLK_RATE is %d\n", wm8904->bclk / wm8904->fs);
aif3 |= wm8904->bclk / wm8904->fs;
/* Apply the settings */
snd_soc_component_update_bits(component, WM8904_DAC_DIGITAL_1,
WM8904_DAC_SB_FILT, dac_digital1);
snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_1,
WM8904_AIF_WL_MASK, aif1);
snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_2,
WM8904_BCLK_DIV_MASK, aif2);
snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_3,
WM8904_LRCLK_RATE_MASK, aif3);
snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_1,
WM8904_SAMPLE_RATE_MASK |
WM8904_CLK_SYS_RATE_MASK, clock1);
/* Update filters for the new settings */
wm8904_set_retune_mobile(component);
wm8904_set_deemph(component);
return 0;
}
static int wm8904_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
unsigned int aif1 = 0;
unsigned int aif3 = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
break;
case SND_SOC_DAIFMT_CBS_CFM:
aif3 |= WM8904_LRCLK_DIR;
break;
case SND_SOC_DAIFMT_CBM_CFS:
aif1 |= WM8904_BCLK_DIR;
break;
case SND_SOC_DAIFMT_CBM_CFM:
aif1 |= WM8904_BCLK_DIR;
aif3 |= WM8904_LRCLK_DIR;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_B:
aif1 |= 0x3 | WM8904_AIF_LRCLK_INV;
fallthrough;
case SND_SOC_DAIFMT_DSP_A:
aif1 |= 0x3;
break;
case SND_SOC_DAIFMT_I2S:
aif1 |= 0x2;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
aif1 |= 0x1;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B:
/* frame inversion not valid for DSP modes */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
aif1 |= WM8904_AIF_BCLK_INV;
break;
default:
return -EINVAL;
}
break;
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_RIGHT_J:
case SND_SOC_DAIFMT_LEFT_J:
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
aif1 |= WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV;
break;
case SND_SOC_DAIFMT_IB_NF:
aif1 |= WM8904_AIF_BCLK_INV;
break;
case SND_SOC_DAIFMT_NB_IF:
aif1 |= WM8904_AIF_LRCLK_INV;
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_1,
WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV |
WM8904_AIF_FMT_MASK | WM8904_BCLK_DIR, aif1);
snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_3,
WM8904_LRCLK_DIR, aif3);
return 0;
}
static int wm8904_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
int aif1 = 0;
/* Don't need to validate anything if we're turning off TDM */
if (slots == 0)
goto out;
/* Note that we allow configurations we can't handle ourselves -
* for example, we can generate clocks for slots 2 and up even if
* we can't use those slots ourselves.
*/
aif1 |= WM8904_AIFADC_TDM | WM8904_AIFDAC_TDM;
switch (rx_mask) {
case 3:
break;
case 0xc:
aif1 |= WM8904_AIFADC_TDM_CHAN;
break;
default:
return -EINVAL;
}
switch (tx_mask) {
case 3:
break;
case 0xc:
aif1 |= WM8904_AIFDAC_TDM_CHAN;
break;
default:
return -EINVAL;
}
out:
wm8904->tdm_width = slot_width;
wm8904->tdm_slots = slots / 2;
snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_1,
WM8904_AIFADC_TDM | WM8904_AIFADC_TDM_CHAN |
WM8904_AIFDAC_TDM | WM8904_AIFDAC_TDM_CHAN, aif1);
return 0;
}
struct _fll_div {
u16 fll_fratio;
u16 fll_outdiv;
u16 fll_clk_ref_div;
u16 n;
u16 k;
};
/* The size in bits of the FLL divide multiplied by 10
* to allow rounding later */
#define FIXED_FLL_SIZE ((1 << 16) * 10)
static struct {
unsigned int min;
unsigned int max;
u16 fll_fratio;
int ratio;
} fll_fratios[] = {
{ 0, 64000, 4, 16 },
{ 64000, 128000, 3, 8 },
{ 128000, 256000, 2, 4 },
{ 256000, 1000000, 1, 2 },
{ 1000000, 13500000, 0, 1 },
};
static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
unsigned int Fout)
{
u64 Kpart;
unsigned int K, Ndiv, Nmod, target;
unsigned int div;
int i;
/* Fref must be <=13.5MHz */
div = 1;
fll_div->fll_clk_ref_div = 0;
while ((Fref / div) > 13500000) {
div *= 2;
fll_div->fll_clk_ref_div++;
if (div > 8) {
pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
Fref);
return -EINVAL;
}
}
pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
/* Apply the division for our remaining calculations */
Fref /= div;
/* Fvco should be 90-100MHz; don't check the upper bound */
div = 4;
while (Fout * div < 90000000) {
div++;
if (div > 64) {
pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
Fout);
return -EINVAL;
}
}
target = Fout * div;
fll_div->fll_outdiv = div - 1;
pr_debug("Fvco=%dHz\n", target);
/* Find an appropriate FLL_FRATIO and factor it out of the target */
for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
fll_div->fll_fratio = fll_fratios[i].fll_fratio;
target /= fll_fratios[i].ratio;
break;
}
}
if (i == ARRAY_SIZE(fll_fratios)) {
pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
return -EINVAL;
}
/* Now, calculate N.K */
Ndiv = target / Fref;
fll_div->n = Ndiv;
Nmod = target % Fref;
pr_debug("Nmod=%d\n", Nmod);
/* Calculate fractional part - scale up so we can round. */
Kpart = FIXED_FLL_SIZE * (long long)Nmod;
do_div(Kpart, Fref);
K = Kpart & 0xFFFFFFFF;
if ((K % 10) >= 5)
K += 5;
/* Move down to proper range now rounding is done */
fll_div->k = K / 10;
pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
fll_div->n, fll_div->k,
fll_div->fll_fratio, fll_div->fll_outdiv,
fll_div->fll_clk_ref_div);
return 0;
}
static int wm8904_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
unsigned int Fref, unsigned int Fout)
{
struct snd_soc_component *component = dai->component;
struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
struct _fll_div fll_div;
int ret, val;
int clock2, fll1;
/* Any change? */
if (source == wm8904->fll_src && Fref == wm8904->fll_fref &&
Fout == wm8904->fll_fout)
return 0;
clock2 = snd_soc_component_read(component, WM8904_CLOCK_RATES_2);
if (Fout == 0) {
dev_dbg(component->dev, "FLL disabled\n");
wm8904->fll_fref = 0;
wm8904->fll_fout = 0;
/* Gate SYSCLK to avoid glitches */
snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2,
WM8904_CLK_SYS_ENA, 0);
snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
goto out;
}
/* Validate the FLL ID */
switch (source) {
case WM8904_FLL_MCLK:
case WM8904_FLL_LRCLK:
case WM8904_FLL_BCLK:
ret = fll_factors(&fll_div, Fref, Fout);
if (ret != 0)
return ret;
break;
case WM8904_FLL_FREE_RUNNING:
dev_dbg(component->dev, "Using free running FLL\n");
/* Force 12MHz and output/4 for now */
Fout = 12000000;
Fref = 12000000;
memset(&fll_div, 0, sizeof(fll_div));
fll_div.fll_outdiv = 3;
break;
default:
dev_err(component->dev, "Unknown FLL ID %d\n", fll_id);
return -EINVAL;
}
/* Save current state then disable the FLL and SYSCLK to avoid
* misclocking */
fll1 = snd_soc_component_read(component, WM8904_FLL_CONTROL_1);
snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2,
WM8904_CLK_SYS_ENA, 0);
snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
/* Unlock forced oscilator control to switch it on/off */
snd_soc_component_update_bits(component, WM8904_CONTROL_INTERFACE_TEST_1,
WM8904_USER_KEY, WM8904_USER_KEY);
if (fll_id == WM8904_FLL_FREE_RUNNING) {
val = WM8904_FLL_FRC_NCO;
} else {
val = 0;
}
snd_soc_component_update_bits(component, WM8904_FLL_NCO_TEST_1, WM8904_FLL_FRC_NCO,
val);
snd_soc_component_update_bits(component, WM8904_CONTROL_INTERFACE_TEST_1,
WM8904_USER_KEY, 0);
switch (fll_id) {
case WM8904_FLL_MCLK:
snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5,
WM8904_FLL_CLK_REF_SRC_MASK, 0);
break;
case WM8904_FLL_LRCLK:
snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5,
WM8904_FLL_CLK_REF_SRC_MASK, 1);
break;
case WM8904_FLL_BCLK:
snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5,
WM8904_FLL_CLK_REF_SRC_MASK, 2);
break;
}
if (fll_div.k)
val = WM8904_FLL_FRACN_ENA;
else
val = 0;
snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
WM8904_FLL_FRACN_ENA, val);
snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_2,
WM8904_FLL_OUTDIV_MASK | WM8904_FLL_FRATIO_MASK,
(fll_div.fll_outdiv << WM8904_FLL_OUTDIV_SHIFT) |
(fll_div.fll_fratio << WM8904_FLL_FRATIO_SHIFT));
snd_soc_component_write(component, WM8904_FLL_CONTROL_3, fll_div.k);
snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_4, WM8904_FLL_N_MASK,
fll_div.n << WM8904_FLL_N_SHIFT);
snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5,
WM8904_FLL_CLK_REF_DIV_MASK,
fll_div.fll_clk_ref_div
<< WM8904_FLL_CLK_REF_DIV_SHIFT);
dev_dbg(component->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
wm8904->fll_fref = Fref;
wm8904->fll_fout = Fout;
wm8904->fll_src = source;
/* Enable the FLL if it was previously active */
snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
WM8904_FLL_OSC_ENA, fll1);
snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
WM8904_FLL_ENA, fll1);
out:
/* Reenable SYSCLK if it was previously active */
snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2,
WM8904_CLK_SYS_ENA, clock2);
return 0;
}
static int wm8904_set_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct wm8904_priv *priv = snd_soc_component_get_drvdata(component);
unsigned long mclk_freq;
int ret;
switch (clk_id) {
case WM8904_CLK_AUTO:
/* We don't have any rate constraints, so just ignore the
* request to disable constraining.
*/
if (!freq)
return 0;
mclk_freq = clk_get_rate(priv->mclk);
/* enable FLL if a different sysclk is desired */
if (mclk_freq != freq) {
priv->sysclk_src = WM8904_CLK_FLL;
ret = wm8904_set_fll(dai, WM8904_FLL_MCLK,
WM8904_FLL_MCLK,
mclk_freq, freq);
if (ret)
return ret;
break;
}
clk_id = WM8904_CLK_MCLK;
fallthrough;
case WM8904_CLK_MCLK:
priv->sysclk_src = clk_id;
priv->mclk_rate = freq;
break;
case WM8904_CLK_FLL:
priv->sysclk_src = clk_id;
break;
default:
return -EINVAL;
}
dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
wm8904_configure_clocking(component);
return 0;
}
static int wm8904_mute(struct snd_soc_dai *codec_dai, int mute, int direction)
{
struct snd_soc_component *component = codec_dai->component;
int val;
if (mute)
val = WM8904_DAC_MUTE;
else
val = 0;
snd_soc_component_update_bits(component, WM8904_DAC_DIGITAL_1, WM8904_DAC_MUTE, val);
return 0;
}
static int wm8904_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
int ret;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
/* VMID resistance 2*50k */
snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0,
WM8904_VMID_RES_MASK,
0x1 << WM8904_VMID_RES_SHIFT);
/* Normal bias current */
snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0,
WM8904_ISEL_MASK, 2 << WM8904_ISEL_SHIFT);
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
wm8904->supplies);
if (ret != 0) {
dev_err(component->dev,
"Failed to enable supplies: %d\n",
ret);
return ret;
}
ret = clk_prepare_enable(wm8904->mclk);
if (ret) {
dev_err(component->dev,
"Failed to enable MCLK: %d\n", ret);
regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies),
wm8904->supplies);
return ret;
}
regcache_cache_only(wm8904->regmap, false);
regcache_sync(wm8904->regmap);
/* Enable bias */
snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0,
WM8904_BIAS_ENA, WM8904_BIAS_ENA);
/* Enable VMID, VMID buffering, 2*5k resistance */
snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0,
WM8904_VMID_ENA |
WM8904_VMID_RES_MASK,
WM8904_VMID_ENA |
0x3 << WM8904_VMID_RES_SHIFT);
/* Let VMID ramp */
msleep(1);
}
/* Maintain VMID with 2*250k */
snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0,
WM8904_VMID_RES_MASK,
0x2 << WM8904_VMID_RES_SHIFT);
/* Bias current *0.5 */
snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0,
WM8904_ISEL_MASK, 0);
break;
case SND_SOC_BIAS_OFF:
/* Turn off VMID */
snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0,
WM8904_VMID_RES_MASK | WM8904_VMID_ENA, 0);
/* Stop bias generation */
snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0,
WM8904_BIAS_ENA, 0);
snd_soc_component_write(component, WM8904_SW_RESET_AND_ID, 0);
regcache_cache_only(wm8904->regmap, true);
regcache_mark_dirty(wm8904->regmap);
regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies),
wm8904->supplies);
clk_disable_unprepare(wm8904->mclk);
break;
}
return 0;
}
#define WM8904_RATES SNDRV_PCM_RATE_8000_96000
#define WM8904_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops wm8904_dai_ops = {
.set_sysclk = wm8904_set_sysclk,
.set_fmt = wm8904_set_fmt,
.set_tdm_slot = wm8904_set_tdm_slot,
.set_pll = wm8904_set_fll,
.hw_params = wm8904_hw_params,
.mute_stream = wm8904_mute,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver wm8904_dai = {
.name = "wm8904-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = WM8904_RATES,
.formats = WM8904_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = WM8904_RATES,
.formats = WM8904_FORMATS,
},
.ops = &wm8904_dai_ops,
.symmetric_rate = 1,
};
static void wm8904_handle_retune_mobile_pdata(struct snd_soc_component *component)
{
struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
struct wm8904_pdata *pdata = wm8904->pdata;
struct snd_kcontrol_new control =
SOC_ENUM_EXT("EQ Mode",
wm8904->retune_mobile_enum,
wm8904_get_retune_mobile_enum,
wm8904_put_retune_mobile_enum);
int ret, i, j;
const char **t;
/* We need an array of texts for the enum API but the number
* of texts is likely to be less than the number of
* configurations due to the sample rate dependency of the
* configurations. */
wm8904->num_retune_mobile_texts = 0;
wm8904->retune_mobile_texts = NULL;
for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
for (j = 0; j < wm8904->num_retune_mobile_texts; j++) {
if (strcmp(pdata->retune_mobile_cfgs[i].name,
wm8904->retune_mobile_texts[j]) == 0)
break;
}
if (j != wm8904->num_retune_mobile_texts)
continue;
/* Expand the array... */
t = krealloc(wm8904->retune_mobile_texts,
sizeof(char *) *
(wm8904->num_retune_mobile_texts + 1),
GFP_KERNEL);
if (t == NULL)
continue;
/* ...store the new entry... */
t[wm8904->num_retune_mobile_texts] =
pdata->retune_mobile_cfgs[i].name;
/* ...and remember the new version. */
wm8904->num_retune_mobile_texts++;
wm8904->retune_mobile_texts = t;
}
dev_dbg(component->dev, "Allocated %d unique ReTune Mobile names\n",
wm8904->num_retune_mobile_texts);
wm8904->retune_mobile_enum.items = wm8904->num_retune_mobile_texts;
wm8904->retune_mobile_enum.texts = wm8904->retune_mobile_texts;
ret = snd_soc_add_component_controls(component, &control, 1);
if (ret != 0)
dev_err(component->dev,
"Failed to add ReTune Mobile control: %d\n", ret);
}
static void wm8904_handle_pdata(struct snd_soc_component *component)
{
struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
struct wm8904_pdata *pdata = wm8904->pdata;
int ret, i;
if (!pdata) {
snd_soc_add_component_controls(component, wm8904_eq_controls,
ARRAY_SIZE(wm8904_eq_controls));
return;
}
dev_dbg(component->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
if (pdata->num_drc_cfgs) {
struct snd_kcontrol_new control =
SOC_ENUM_EXT("DRC Mode", wm8904->drc_enum,
wm8904_get_drc_enum, wm8904_put_drc_enum);
/* We need an array of texts for the enum API */
wm8904->drc_texts = kmalloc_array(pdata->num_drc_cfgs,
sizeof(char *),
GFP_KERNEL);
if (!wm8904->drc_texts)
return;
for (i = 0; i < pdata->num_drc_cfgs; i++)
wm8904->drc_texts[i] = pdata->drc_cfgs[i].name;
wm8904->drc_enum.items = pdata->num_drc_cfgs;
wm8904->drc_enum.texts = wm8904->drc_texts;
ret = snd_soc_add_component_controls(component, &control, 1);
if (ret != 0)
dev_err(component->dev,
"Failed to add DRC mode control: %d\n", ret);
wm8904_set_drc(component);
}
dev_dbg(component->dev, "%d ReTune Mobile configurations\n",
pdata->num_retune_mobile_cfgs);
if (pdata->num_retune_mobile_cfgs)
wm8904_handle_retune_mobile_pdata(component);
else
snd_soc_add_component_controls(component, wm8904_eq_controls,
ARRAY_SIZE(wm8904_eq_controls));
}
static int wm8904_probe(struct snd_soc_component *component)
{
struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
switch (wm8904->devtype) {
case WM8904:
break;
case WM8912:
memset(&wm8904_dai.capture, 0, sizeof(wm8904_dai.capture));
break;
default:
dev_err(component->dev, "Unknown device type %d\n",
wm8904->devtype);
return -EINVAL;
}
wm8904_handle_pdata(component);
wm8904_add_widgets(component);
return 0;
}
static void wm8904_remove(struct snd_soc_component *component)
{
struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
kfree(wm8904->retune_mobile_texts);
kfree(wm8904->drc_texts);
}
static const struct snd_soc_component_driver soc_component_dev_wm8904 = {
.probe = wm8904_probe,
.remove = wm8904_remove,
.set_bias_level = wm8904_set_bias_level,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config wm8904_regmap = {
.reg_bits = 8,
.val_bits = 16,
.max_register = WM8904_MAX_REGISTER,
.volatile_reg = wm8904_volatile_register,
.readable_reg = wm8904_readable_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = wm8904_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8904_reg_defaults),
};
#ifdef CONFIG_OF
static const struct of_device_id wm8904_of_match[] = {
{
.compatible = "wlf,wm8904",
.data = (void *)WM8904,
}, {
.compatible = "wlf,wm8912",
.data = (void *)WM8912,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, wm8904_of_match);
#endif
static const struct i2c_device_id wm8904_i2c_id[];
static int wm8904_i2c_probe(struct i2c_client *i2c)
{
struct wm8904_priv *wm8904;
unsigned int val;
int ret, i;
wm8904 = devm_kzalloc(&i2c->dev, sizeof(struct wm8904_priv),
GFP_KERNEL);
if (wm8904 == NULL)
return -ENOMEM;
wm8904->mclk = devm_clk_get(&i2c->dev, "mclk");
if (IS_ERR(wm8904->mclk)) {
ret = PTR_ERR(wm8904->mclk);
dev_err(&i2c->dev, "Failed to get MCLK\n");
return ret;
}
wm8904->regmap = devm_regmap_init_i2c(i2c, &wm8904_regmap);
if (IS_ERR(wm8904->regmap)) {
ret = PTR_ERR(wm8904->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
if (i2c->dev.of_node) {
const struct of_device_id *match;
match = of_match_node(wm8904_of_match, i2c->dev.of_node);
if (match == NULL)
return -EINVAL;
wm8904->devtype = (uintptr_t)match->data;
} else {
const struct i2c_device_id *id =
i2c_match_id(wm8904_i2c_id, i2c);
wm8904->devtype = id->driver_data;
}
i2c_set_clientdata(i2c, wm8904);
wm8904->pdata = i2c->dev.platform_data;
for (i = 0; i < ARRAY_SIZE(wm8904->supplies); i++)
wm8904->supplies[i].supply = wm8904_supply_names[i];
ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8904->supplies),
wm8904->supplies);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
return ret;
}
ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
wm8904->supplies);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
return ret;
}
ret = regmap_read(wm8904->regmap, WM8904_SW_RESET_AND_ID, &val);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
goto err_enable;
}
if (val != 0x8904) {
dev_err(&i2c->dev, "Device is not a WM8904, ID is %x\n", val);
ret = -EINVAL;
goto err_enable;
}
ret = regmap_read(wm8904->regmap, WM8904_REVISION, &val);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to read device revision: %d\n",
ret);
goto err_enable;
}
dev_info(&i2c->dev, "revision %c\n", val + 'A');
ret = regmap_write(wm8904->regmap, WM8904_SW_RESET_AND_ID, 0);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
goto err_enable;
}
/* Change some default settings - latch VU and enable ZC */
regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_LEFT,
WM8904_ADC_VU, WM8904_ADC_VU);
regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_RIGHT,
WM8904_ADC_VU, WM8904_ADC_VU);
regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_LEFT,
WM8904_DAC_VU, WM8904_DAC_VU);
regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_RIGHT,
WM8904_DAC_VU, WM8904_DAC_VU);
regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_LEFT,
WM8904_HPOUT_VU | WM8904_HPOUTLZC,
WM8904_HPOUT_VU | WM8904_HPOUTLZC);
regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_RIGHT,
WM8904_HPOUT_VU | WM8904_HPOUTRZC,
WM8904_HPOUT_VU | WM8904_HPOUTRZC);
regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_LEFT,
WM8904_LINEOUT_VU | WM8904_LINEOUTLZC,
WM8904_LINEOUT_VU | WM8904_LINEOUTLZC);
regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_RIGHT,
WM8904_LINEOUT_VU | WM8904_LINEOUTRZC,
WM8904_LINEOUT_VU | WM8904_LINEOUTRZC);
regmap_update_bits(wm8904->regmap, WM8904_CLOCK_RATES_0,
WM8904_SR_MODE, 0);
/* Apply configuration from the platform data. */
if (wm8904->pdata) {
for (i = 0; i < WM8904_GPIO_REGS; i++) {
if (!wm8904->pdata->gpio_cfg[i])
continue;
regmap_update_bits(wm8904->regmap,
WM8904_GPIO_CONTROL_1 + i,
0xffff,
wm8904->pdata->gpio_cfg[i]);
}
/* Zero is the default value for these anyway */
for (i = 0; i < WM8904_MIC_REGS; i++)
regmap_update_bits(wm8904->regmap,
WM8904_MIC_BIAS_CONTROL_0 + i,
0xffff,
wm8904->pdata->mic_cfg[i]);
}
/* Set Class W by default - this will be managed by the Class
* G widget at runtime where bypass paths are available.
*/
regmap_update_bits(wm8904->regmap, WM8904_CLASS_W_0,
WM8904_CP_DYN_PWR, WM8904_CP_DYN_PWR);
/* Use normal bias source */
regmap_update_bits(wm8904->regmap, WM8904_BIAS_CONTROL_0,
WM8904_POBCTRL, 0);
/* Fill the cache for the ADC test register */
regmap_read(wm8904->regmap, WM8904_ADC_TEST_0, &val);
/* Can leave the device powered off until we need it */
regcache_cache_only(wm8904->regmap, true);
regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_wm8904, &wm8904_dai, 1);
if (ret != 0)
return ret;
return 0;
err_enable:
regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
return ret;
}
static const struct i2c_device_id wm8904_i2c_id[] = {
{ "wm8904", WM8904 },
{ "wm8912", WM8912 },
{ "wm8918", WM8904 }, /* Actually a subset, updates to follow */
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8904_i2c_id);
static struct i2c_driver wm8904_i2c_driver = {
.driver = {
.name = "wm8904",
.of_match_table = of_match_ptr(wm8904_of_match),
},
.probe = wm8904_i2c_probe,
.id_table = wm8904_i2c_id,
};
module_i2c_driver(wm8904_i2c_driver);
MODULE_DESCRIPTION("ASoC WM8904 driver");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8904.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8988.c -- WM8988 ALSA SoC audio driver
*
* Copyright 2009 Wolfson Microelectronics plc
* Copyright 2005 Openedhand Ltd.
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/tlv.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include "wm8988.h"
/*
* wm8988 register cache
* We can't read the WM8988 register space when we
* are using 2 wire for device control, so we cache them instead.
*/
static const struct reg_default wm8988_reg_defaults[] = {
{ 0, 0x0097 },
{ 1, 0x0097 },
{ 2, 0x0079 },
{ 3, 0x0079 },
{ 5, 0x0008 },
{ 7, 0x000a },
{ 8, 0x0000 },
{ 10, 0x00ff },
{ 11, 0x00ff },
{ 12, 0x000f },
{ 13, 0x000f },
{ 16, 0x0000 },
{ 17, 0x007b },
{ 18, 0x0000 },
{ 19, 0x0032 },
{ 20, 0x0000 },
{ 21, 0x00c3 },
{ 22, 0x00c3 },
{ 23, 0x00c0 },
{ 24, 0x0000 },
{ 25, 0x0000 },
{ 26, 0x0000 },
{ 27, 0x0000 },
{ 31, 0x0000 },
{ 32, 0x0000 },
{ 33, 0x0000 },
{ 34, 0x0050 },
{ 35, 0x0050 },
{ 36, 0x0050 },
{ 37, 0x0050 },
{ 40, 0x0079 },
{ 41, 0x0079 },
{ 42, 0x0079 },
};
static bool wm8988_writeable(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8988_LINVOL:
case WM8988_RINVOL:
case WM8988_LOUT1V:
case WM8988_ROUT1V:
case WM8988_ADCDAC:
case WM8988_IFACE:
case WM8988_SRATE:
case WM8988_LDAC:
case WM8988_RDAC:
case WM8988_BASS:
case WM8988_TREBLE:
case WM8988_RESET:
case WM8988_3D:
case WM8988_ALC1:
case WM8988_ALC2:
case WM8988_ALC3:
case WM8988_NGATE:
case WM8988_LADC:
case WM8988_RADC:
case WM8988_ADCTL1:
case WM8988_ADCTL2:
case WM8988_PWR1:
case WM8988_PWR2:
case WM8988_ADCTL3:
case WM8988_ADCIN:
case WM8988_LADCIN:
case WM8988_RADCIN:
case WM8988_LOUTM1:
case WM8988_LOUTM2:
case WM8988_ROUTM1:
case WM8988_ROUTM2:
case WM8988_LOUT2V:
case WM8988_ROUT2V:
case WM8988_LPPB:
return true;
default:
return false;
}
}
/* codec private data */
struct wm8988_priv {
struct regmap *regmap;
unsigned int sysclk;
const struct snd_pcm_hw_constraint_list *sysclk_constraints;
};
#define wm8988_reset(c) snd_soc_component_write(c, WM8988_RESET, 0)
/*
* WM8988 Controls
*/
static const char *bass_boost_txt[] = {"Linear Control", "Adaptive Boost"};
static SOC_ENUM_SINGLE_DECL(bass_boost,
WM8988_BASS, 7, bass_boost_txt);
static const char *bass_filter_txt[] = { "130Hz @ 48kHz", "200Hz @ 48kHz" };
static SOC_ENUM_SINGLE_DECL(bass_filter,
WM8988_BASS, 6, bass_filter_txt);
static const char *treble_txt[] = {"8kHz", "4kHz"};
static SOC_ENUM_SINGLE_DECL(treble,
WM8988_TREBLE, 6, treble_txt);
static const char *stereo_3d_lc_txt[] = {"200Hz", "500Hz"};
static SOC_ENUM_SINGLE_DECL(stereo_3d_lc,
WM8988_3D, 5, stereo_3d_lc_txt);
static const char *stereo_3d_uc_txt[] = {"2.2kHz", "1.5kHz"};
static SOC_ENUM_SINGLE_DECL(stereo_3d_uc,
WM8988_3D, 6, stereo_3d_uc_txt);
static const char *stereo_3d_func_txt[] = {"Capture", "Playback"};
static SOC_ENUM_SINGLE_DECL(stereo_3d_func,
WM8988_3D, 7, stereo_3d_func_txt);
static const char *alc_func_txt[] = {"Off", "Right", "Left", "Stereo"};
static SOC_ENUM_SINGLE_DECL(alc_func,
WM8988_ALC1, 7, alc_func_txt);
static const char *ng_type_txt[] = {"Constant PGA Gain",
"Mute ADC Output"};
static SOC_ENUM_SINGLE_DECL(ng_type,
WM8988_NGATE, 1, ng_type_txt);
static const char *deemph_txt[] = {"None", "32Khz", "44.1Khz", "48Khz"};
static SOC_ENUM_SINGLE_DECL(deemph,
WM8988_ADCDAC, 1, deemph_txt);
static const char *adcpol_txt[] = {"Normal", "L Invert", "R Invert",
"L + R Invert"};
static SOC_ENUM_SINGLE_DECL(adcpol,
WM8988_ADCDAC, 5, adcpol_txt);
static const DECLARE_TLV_DB_SCALE(pga_tlv, -1725, 75, 0);
static const DECLARE_TLV_DB_SCALE(adc_tlv, -9750, 50, 1);
static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
static const struct snd_kcontrol_new wm8988_snd_controls[] = {
SOC_ENUM("Bass Boost", bass_boost),
SOC_ENUM("Bass Filter", bass_filter),
SOC_SINGLE("Bass Volume", WM8988_BASS, 0, 15, 1),
SOC_SINGLE("Treble Volume", WM8988_TREBLE, 0, 15, 0),
SOC_ENUM("Treble Cut-off", treble),
SOC_SINGLE("3D Switch", WM8988_3D, 0, 1, 0),
SOC_SINGLE("3D Volume", WM8988_3D, 1, 15, 0),
SOC_ENUM("3D Lower Cut-off", stereo_3d_lc),
SOC_ENUM("3D Upper Cut-off", stereo_3d_uc),
SOC_ENUM("3D Mode", stereo_3d_func),
SOC_SINGLE("ALC Capture Target Volume", WM8988_ALC1, 0, 7, 0),
SOC_SINGLE("ALC Capture Max Volume", WM8988_ALC1, 4, 7, 0),
SOC_ENUM("ALC Capture Function", alc_func),
SOC_SINGLE("ALC Capture ZC Switch", WM8988_ALC2, 7, 1, 0),
SOC_SINGLE("ALC Capture Hold Time", WM8988_ALC2, 0, 15, 0),
SOC_SINGLE("ALC Capture Decay Time", WM8988_ALC3, 4, 15, 0),
SOC_SINGLE("ALC Capture Attack Time", WM8988_ALC3, 0, 15, 0),
SOC_SINGLE("ALC Capture NG Threshold", WM8988_NGATE, 3, 31, 0),
SOC_ENUM("ALC Capture NG Type", ng_type),
SOC_SINGLE("ALC Capture NG Switch", WM8988_NGATE, 0, 1, 0),
SOC_SINGLE("ZC Timeout Switch", WM8988_ADCTL1, 0, 1, 0),
SOC_DOUBLE_R_TLV("Capture Digital Volume", WM8988_LADC, WM8988_RADC,
0, 255, 0, adc_tlv),
SOC_DOUBLE_R_TLV("Capture Volume", WM8988_LINVOL, WM8988_RINVOL,
0, 63, 0, pga_tlv),
SOC_DOUBLE_R("Capture ZC Switch", WM8988_LINVOL, WM8988_RINVOL, 6, 1, 0),
SOC_DOUBLE_R("Capture Switch", WM8988_LINVOL, WM8988_RINVOL, 7, 1, 1),
SOC_ENUM("Playback De-emphasis", deemph),
SOC_ENUM("Capture Polarity", adcpol),
SOC_SINGLE("Playback 6dB Attenuate", WM8988_ADCDAC, 7, 1, 0),
SOC_SINGLE("Capture 6dB Attenuate", WM8988_ADCDAC, 8, 1, 0),
SOC_DOUBLE_R_TLV("PCM Volume", WM8988_LDAC, WM8988_RDAC, 0, 255, 0, dac_tlv),
SOC_SINGLE_TLV("Left Mixer Left Bypass Volume", WM8988_LOUTM1, 4, 7, 1,
bypass_tlv),
SOC_SINGLE_TLV("Left Mixer Right Bypass Volume", WM8988_LOUTM2, 4, 7, 1,
bypass_tlv),
SOC_SINGLE_TLV("Right Mixer Left Bypass Volume", WM8988_ROUTM1, 4, 7, 1,
bypass_tlv),
SOC_SINGLE_TLV("Right Mixer Right Bypass Volume", WM8988_ROUTM2, 4, 7, 1,
bypass_tlv),
SOC_DOUBLE_R("Output 1 Playback ZC Switch", WM8988_LOUT1V,
WM8988_ROUT1V, 7, 1, 0),
SOC_DOUBLE_R_TLV("Output 1 Playback Volume", WM8988_LOUT1V, WM8988_ROUT1V,
0, 127, 0, out_tlv),
SOC_DOUBLE_R("Output 2 Playback ZC Switch", WM8988_LOUT2V,
WM8988_ROUT2V, 7, 1, 0),
SOC_DOUBLE_R_TLV("Output 2 Playback Volume", WM8988_LOUT2V, WM8988_ROUT2V,
0, 127, 0, out_tlv),
};
/*
* DAPM Controls
*/
static int wm8988_lrc_control(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
u16 adctl2 = snd_soc_component_read(component, WM8988_ADCTL2);
/* Use the DAC to gate LRC if active, otherwise use ADC */
if (snd_soc_component_read(component, WM8988_PWR2) & 0x180)
adctl2 &= ~0x4;
else
adctl2 |= 0x4;
return snd_soc_component_write(component, WM8988_ADCTL2, adctl2);
}
static const char *wm8988_line_texts[] = {
"Line 1", "Line 2", "PGA", "Differential"};
static const unsigned int wm8988_line_values[] = {
0, 1, 3, 4};
static const struct soc_enum wm8988_lline_enum =
SOC_VALUE_ENUM_SINGLE(WM8988_LOUTM1, 0, 7,
ARRAY_SIZE(wm8988_line_texts),
wm8988_line_texts,
wm8988_line_values);
static const struct snd_kcontrol_new wm8988_left_line_controls =
SOC_DAPM_ENUM("Route", wm8988_lline_enum);
static const struct soc_enum wm8988_rline_enum =
SOC_VALUE_ENUM_SINGLE(WM8988_ROUTM1, 0, 7,
ARRAY_SIZE(wm8988_line_texts),
wm8988_line_texts,
wm8988_line_values);
static const struct snd_kcontrol_new wm8988_right_line_controls =
SOC_DAPM_ENUM("Route", wm8988_rline_enum);
/* Left Mixer */
static const struct snd_kcontrol_new wm8988_left_mixer_controls[] = {
SOC_DAPM_SINGLE("Playback Switch", WM8988_LOUTM1, 8, 1, 0),
SOC_DAPM_SINGLE("Left Bypass Switch", WM8988_LOUTM1, 7, 1, 0),
SOC_DAPM_SINGLE("Right Playback Switch", WM8988_LOUTM2, 8, 1, 0),
SOC_DAPM_SINGLE("Right Bypass Switch", WM8988_LOUTM2, 7, 1, 0),
};
/* Right Mixer */
static const struct snd_kcontrol_new wm8988_right_mixer_controls[] = {
SOC_DAPM_SINGLE("Left Playback Switch", WM8988_ROUTM1, 8, 1, 0),
SOC_DAPM_SINGLE("Left Bypass Switch", WM8988_ROUTM1, 7, 1, 0),
SOC_DAPM_SINGLE("Playback Switch", WM8988_ROUTM2, 8, 1, 0),
SOC_DAPM_SINGLE("Right Bypass Switch", WM8988_ROUTM2, 7, 1, 0),
};
static const char *wm8988_pga_sel[] = {"Line 1", "Line 2", "Differential"};
static const unsigned int wm8988_pga_val[] = { 0, 1, 3 };
/* Left PGA Mux */
static const struct soc_enum wm8988_lpga_enum =
SOC_VALUE_ENUM_SINGLE(WM8988_LADCIN, 6, 3,
ARRAY_SIZE(wm8988_pga_sel),
wm8988_pga_sel,
wm8988_pga_val);
static const struct snd_kcontrol_new wm8988_left_pga_controls =
SOC_DAPM_ENUM("Route", wm8988_lpga_enum);
/* Right PGA Mux */
static const struct soc_enum wm8988_rpga_enum =
SOC_VALUE_ENUM_SINGLE(WM8988_RADCIN, 6, 3,
ARRAY_SIZE(wm8988_pga_sel),
wm8988_pga_sel,
wm8988_pga_val);
static const struct snd_kcontrol_new wm8988_right_pga_controls =
SOC_DAPM_ENUM("Route", wm8988_rpga_enum);
/* Differential Mux */
static const char *wm8988_diff_sel[] = {"Line 1", "Line 2"};
static SOC_ENUM_SINGLE_DECL(diffmux,
WM8988_ADCIN, 8, wm8988_diff_sel);
static const struct snd_kcontrol_new wm8988_diffmux_controls =
SOC_DAPM_ENUM("Route", diffmux);
/* Mono ADC Mux */
static const char *wm8988_mono_mux[] = {"Stereo", "Mono (Left)",
"Mono (Right)", "Digital Mono"};
static SOC_ENUM_SINGLE_DECL(monomux,
WM8988_ADCIN, 6, wm8988_mono_mux);
static const struct snd_kcontrol_new wm8988_monomux_controls =
SOC_DAPM_ENUM("Route", monomux);
static const struct snd_soc_dapm_widget wm8988_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("Mic Bias", WM8988_PWR1, 1, 0, NULL, 0),
SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
&wm8988_diffmux_controls),
SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
&wm8988_monomux_controls),
SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
&wm8988_monomux_controls),
SND_SOC_DAPM_MUX("Left PGA Mux", WM8988_PWR1, 5, 0,
&wm8988_left_pga_controls),
SND_SOC_DAPM_MUX("Right PGA Mux", WM8988_PWR1, 4, 0,
&wm8988_right_pga_controls),
SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
&wm8988_left_line_controls),
SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
&wm8988_right_line_controls),
SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8988_PWR1, 2, 0),
SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8988_PWR1, 3, 0),
SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8988_PWR2, 7, 0),
SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8988_PWR2, 8, 0),
SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
&wm8988_left_mixer_controls[0],
ARRAY_SIZE(wm8988_left_mixer_controls)),
SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
&wm8988_right_mixer_controls[0],
ARRAY_SIZE(wm8988_right_mixer_controls)),
SND_SOC_DAPM_PGA("Right Out 2", WM8988_PWR2, 3, 0, NULL, 0),
SND_SOC_DAPM_PGA("Left Out 2", WM8988_PWR2, 4, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Out 1", WM8988_PWR2, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA("Left Out 1", WM8988_PWR2, 6, 0, NULL, 0),
SND_SOC_DAPM_POST("LRC control", wm8988_lrc_control),
SND_SOC_DAPM_OUTPUT("LOUT1"),
SND_SOC_DAPM_OUTPUT("ROUT1"),
SND_SOC_DAPM_OUTPUT("LOUT2"),
SND_SOC_DAPM_OUTPUT("ROUT2"),
SND_SOC_DAPM_OUTPUT("VREF"),
SND_SOC_DAPM_INPUT("LINPUT1"),
SND_SOC_DAPM_INPUT("LINPUT2"),
SND_SOC_DAPM_INPUT("RINPUT1"),
SND_SOC_DAPM_INPUT("RINPUT2"),
};
static const struct snd_soc_dapm_route wm8988_dapm_routes[] = {
{ "Left Line Mux", "Line 1", "LINPUT1" },
{ "Left Line Mux", "Line 2", "LINPUT2" },
{ "Left Line Mux", "PGA", "Left PGA Mux" },
{ "Left Line Mux", "Differential", "Differential Mux" },
{ "Right Line Mux", "Line 1", "RINPUT1" },
{ "Right Line Mux", "Line 2", "RINPUT2" },
{ "Right Line Mux", "PGA", "Right PGA Mux" },
{ "Right Line Mux", "Differential", "Differential Mux" },
{ "Left PGA Mux", "Line 1", "LINPUT1" },
{ "Left PGA Mux", "Line 2", "LINPUT2" },
{ "Left PGA Mux", "Differential", "Differential Mux" },
{ "Right PGA Mux", "Line 1", "RINPUT1" },
{ "Right PGA Mux", "Line 2", "RINPUT2" },
{ "Right PGA Mux", "Differential", "Differential Mux" },
{ "Differential Mux", "Line 1", "LINPUT1" },
{ "Differential Mux", "Line 1", "RINPUT1" },
{ "Differential Mux", "Line 2", "LINPUT2" },
{ "Differential Mux", "Line 2", "RINPUT2" },
{ "Left ADC Mux", "Stereo", "Left PGA Mux" },
{ "Left ADC Mux", "Mono (Left)", "Left PGA Mux" },
{ "Left ADC Mux", "Digital Mono", "Left PGA Mux" },
{ "Right ADC Mux", "Stereo", "Right PGA Mux" },
{ "Right ADC Mux", "Mono (Right)", "Right PGA Mux" },
{ "Right ADC Mux", "Digital Mono", "Right PGA Mux" },
{ "Left ADC", NULL, "Left ADC Mux" },
{ "Right ADC", NULL, "Right ADC Mux" },
{ "Left Line Mux", "Line 1", "LINPUT1" },
{ "Left Line Mux", "Line 2", "LINPUT2" },
{ "Left Line Mux", "PGA", "Left PGA Mux" },
{ "Left Line Mux", "Differential", "Differential Mux" },
{ "Right Line Mux", "Line 1", "RINPUT1" },
{ "Right Line Mux", "Line 2", "RINPUT2" },
{ "Right Line Mux", "PGA", "Right PGA Mux" },
{ "Right Line Mux", "Differential", "Differential Mux" },
{ "Left Mixer", "Playback Switch", "Left DAC" },
{ "Left Mixer", "Left Bypass Switch", "Left Line Mux" },
{ "Left Mixer", "Right Playback Switch", "Right DAC" },
{ "Left Mixer", "Right Bypass Switch", "Right Line Mux" },
{ "Right Mixer", "Left Playback Switch", "Left DAC" },
{ "Right Mixer", "Left Bypass Switch", "Left Line Mux" },
{ "Right Mixer", "Playback Switch", "Right DAC" },
{ "Right Mixer", "Right Bypass Switch", "Right Line Mux" },
{ "Left Out 1", NULL, "Left Mixer" },
{ "LOUT1", NULL, "Left Out 1" },
{ "Right Out 1", NULL, "Right Mixer" },
{ "ROUT1", NULL, "Right Out 1" },
{ "Left Out 2", NULL, "Left Mixer" },
{ "LOUT2", NULL, "Left Out 2" },
{ "Right Out 2", NULL, "Right Mixer" },
{ "ROUT2", NULL, "Right Out 2" },
};
struct _coeff_div {
u32 mclk;
u32 rate;
u16 fs;
u8 sr:5;
u8 usb:1;
};
/* codec hifi mclk clock divider coefficients */
static const struct _coeff_div coeff_div[] = {
/* 8k */
{12288000, 8000, 1536, 0x6, 0x0},
{11289600, 8000, 1408, 0x16, 0x0},
{18432000, 8000, 2304, 0x7, 0x0},
{16934400, 8000, 2112, 0x17, 0x0},
{12000000, 8000, 1500, 0x6, 0x1},
/* 11.025k */
{11289600, 11025, 1024, 0x18, 0x0},
{16934400, 11025, 1536, 0x19, 0x0},
{12000000, 11025, 1088, 0x19, 0x1},
/* 16k */
{12288000, 16000, 768, 0xa, 0x0},
{18432000, 16000, 1152, 0xb, 0x0},
{12000000, 16000, 750, 0xa, 0x1},
/* 22.05k */
{11289600, 22050, 512, 0x1a, 0x0},
{16934400, 22050, 768, 0x1b, 0x0},
{12000000, 22050, 544, 0x1b, 0x1},
/* 32k */
{12288000, 32000, 384, 0xc, 0x0},
{18432000, 32000, 576, 0xd, 0x0},
{12000000, 32000, 375, 0xa, 0x1},
/* 44.1k */
{11289600, 44100, 256, 0x10, 0x0},
{16934400, 44100, 384, 0x11, 0x0},
{12000000, 44100, 272, 0x11, 0x1},
/* 48k */
{12288000, 48000, 256, 0x0, 0x0},
{18432000, 48000, 384, 0x1, 0x0},
{12000000, 48000, 250, 0x0, 0x1},
/* 88.2k */
{11289600, 88200, 128, 0x1e, 0x0},
{16934400, 88200, 192, 0x1f, 0x0},
{12000000, 88200, 136, 0x1f, 0x1},
/* 96k */
{12288000, 96000, 128, 0xe, 0x0},
{18432000, 96000, 192, 0xf, 0x0},
{12000000, 96000, 125, 0xe, 0x1},
};
static inline int get_coeff(int mclk, int rate)
{
int i;
for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
return i;
}
return -EINVAL;
}
/* The set of rates we can generate from the above for each SYSCLK */
static const unsigned int rates_12288[] = {
8000, 12000, 16000, 24000, 32000, 48000, 96000,
};
static const struct snd_pcm_hw_constraint_list constraints_12288 = {
.count = ARRAY_SIZE(rates_12288),
.list = rates_12288,
};
static const unsigned int rates_112896[] = {
8000, 11025, 22050, 44100,
};
static const struct snd_pcm_hw_constraint_list constraints_112896 = {
.count = ARRAY_SIZE(rates_112896),
.list = rates_112896,
};
static const unsigned int rates_12[] = {
8000, 11025, 12000, 16000, 22050, 24000, 32000, 41100, 48000,
48000, 88235, 96000,
};
static const struct snd_pcm_hw_constraint_list constraints_12 = {
.count = ARRAY_SIZE(rates_12),
.list = rates_12,
};
/*
* Note that this should be called from init rather than from hw_params.
*/
static int wm8988_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct wm8988_priv *wm8988 = snd_soc_component_get_drvdata(component);
switch (freq) {
case 11289600:
case 18432000:
case 22579200:
case 36864000:
wm8988->sysclk_constraints = &constraints_112896;
wm8988->sysclk = freq;
return 0;
case 12288000:
case 16934400:
case 24576000:
case 33868800:
wm8988->sysclk_constraints = &constraints_12288;
wm8988->sysclk = freq;
return 0;
case 12000000:
case 24000000:
wm8988->sysclk_constraints = &constraints_12;
wm8988->sysclk = freq;
return 0;
}
return -EINVAL;
}
static int wm8988_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
u16 iface = 0;
/* set master/slave audio interface */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
iface = 0x0040;
break;
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface |= 0x0002;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
iface |= 0x0001;
break;
case SND_SOC_DAIFMT_DSP_A:
iface |= 0x0003;
break;
case SND_SOC_DAIFMT_DSP_B:
iface |= 0x0013;
break;
default:
return -EINVAL;
}
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
iface |= 0x0090;
break;
case SND_SOC_DAIFMT_IB_NF:
iface |= 0x0080;
break;
case SND_SOC_DAIFMT_NB_IF:
iface |= 0x0010;
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, WM8988_IFACE, iface);
return 0;
}
static int wm8988_pcm_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm8988_priv *wm8988 = snd_soc_component_get_drvdata(component);
/* The set of sample rates that can be supported depends on the
* MCLK supplied to the CODEC - enforce this.
*/
if (!wm8988->sysclk) {
dev_err(component->dev,
"No MCLK configured, call set_sysclk() on init\n");
return -EINVAL;
}
snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
wm8988->sysclk_constraints);
return 0;
}
static int wm8988_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm8988_priv *wm8988 = snd_soc_component_get_drvdata(component);
u16 iface = snd_soc_component_read(component, WM8988_IFACE) & 0x1f3;
u16 srate = snd_soc_component_read(component, WM8988_SRATE) & 0x180;
int coeff;
coeff = get_coeff(wm8988->sysclk, params_rate(params));
if (coeff < 0) {
coeff = get_coeff(wm8988->sysclk / 2, params_rate(params));
srate |= 0x40;
}
if (coeff < 0) {
dev_err(component->dev,
"Unable to configure sample rate %dHz with %dHz MCLK\n",
params_rate(params), wm8988->sysclk);
return coeff;
}
/* bit size */
switch (params_width(params)) {
case 16:
break;
case 20:
iface |= 0x0004;
break;
case 24:
iface |= 0x0008;
break;
case 32:
iface |= 0x000c;
break;
}
/* set iface & srate */
snd_soc_component_write(component, WM8988_IFACE, iface);
if (coeff >= 0)
snd_soc_component_write(component, WM8988_SRATE, srate |
(coeff_div[coeff].sr << 1) | coeff_div[coeff].usb);
return 0;
}
static int wm8988_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
u16 mute_reg = snd_soc_component_read(component, WM8988_ADCDAC) & 0xfff7;
if (mute)
snd_soc_component_write(component, WM8988_ADCDAC, mute_reg | 0x8);
else
snd_soc_component_write(component, WM8988_ADCDAC, mute_reg);
return 0;
}
static int wm8988_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct wm8988_priv *wm8988 = snd_soc_component_get_drvdata(component);
u16 pwr_reg = snd_soc_component_read(component, WM8988_PWR1) & ~0x1c1;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
/* VREF, VMID=2x50k, digital enabled */
snd_soc_component_write(component, WM8988_PWR1, pwr_reg | 0x00c0);
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
regcache_sync(wm8988->regmap);
/* VREF, VMID=2x5k */
snd_soc_component_write(component, WM8988_PWR1, pwr_reg | 0x1c1);
/* Charge caps */
msleep(100);
}
/* VREF, VMID=2*500k, digital stopped */
snd_soc_component_write(component, WM8988_PWR1, pwr_reg | 0x0141);
break;
case SND_SOC_BIAS_OFF:
snd_soc_component_write(component, WM8988_PWR1, 0x0000);
break;
}
return 0;
}
#define WM8988_RATES SNDRV_PCM_RATE_8000_96000
#define WM8988_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE)
static const struct snd_soc_dai_ops wm8988_ops = {
.startup = wm8988_pcm_startup,
.hw_params = wm8988_pcm_hw_params,
.set_fmt = wm8988_set_dai_fmt,
.set_sysclk = wm8988_set_dai_sysclk,
.mute_stream = wm8988_mute,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver wm8988_dai = {
.name = "wm8988-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM8988_RATES,
.formats = WM8988_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM8988_RATES,
.formats = WM8988_FORMATS,
},
.ops = &wm8988_ops,
.symmetric_rate = 1,
};
static int wm8988_probe(struct snd_soc_component *component)
{
int ret = 0;
ret = wm8988_reset(component);
if (ret < 0) {
dev_err(component->dev, "Failed to issue reset\n");
return ret;
}
/* set the update bits (we always update left then right) */
snd_soc_component_update_bits(component, WM8988_RADC, 0x0100, 0x0100);
snd_soc_component_update_bits(component, WM8988_RDAC, 0x0100, 0x0100);
snd_soc_component_update_bits(component, WM8988_ROUT1V, 0x0100, 0x0100);
snd_soc_component_update_bits(component, WM8988_ROUT2V, 0x0100, 0x0100);
snd_soc_component_update_bits(component, WM8988_RINVOL, 0x0100, 0x0100);
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_wm8988 = {
.probe = wm8988_probe,
.set_bias_level = wm8988_set_bias_level,
.controls = wm8988_snd_controls,
.num_controls = ARRAY_SIZE(wm8988_snd_controls),
.dapm_widgets = wm8988_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8988_dapm_widgets),
.dapm_routes = wm8988_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(wm8988_dapm_routes),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config wm8988_regmap = {
.reg_bits = 7,
.val_bits = 9,
.max_register = WM8988_LPPB,
.writeable_reg = wm8988_writeable,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = wm8988_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8988_reg_defaults),
};
#if defined(CONFIG_SPI_MASTER)
static int wm8988_spi_probe(struct spi_device *spi)
{
struct wm8988_priv *wm8988;
int ret;
wm8988 = devm_kzalloc(&spi->dev, sizeof(struct wm8988_priv),
GFP_KERNEL);
if (wm8988 == NULL)
return -ENOMEM;
wm8988->regmap = devm_regmap_init_spi(spi, &wm8988_regmap);
if (IS_ERR(wm8988->regmap)) {
ret = PTR_ERR(wm8988->regmap);
dev_err(&spi->dev, "Failed to init regmap: %d\n", ret);
return ret;
}
spi_set_drvdata(spi, wm8988);
ret = devm_snd_soc_register_component(&spi->dev,
&soc_component_dev_wm8988, &wm8988_dai, 1);
return ret;
}
static struct spi_driver wm8988_spi_driver = {
.driver = {
.name = "wm8988",
},
.probe = wm8988_spi_probe,
};
#endif /* CONFIG_SPI_MASTER */
#if IS_ENABLED(CONFIG_I2C)
static int wm8988_i2c_probe(struct i2c_client *i2c)
{
struct wm8988_priv *wm8988;
int ret;
wm8988 = devm_kzalloc(&i2c->dev, sizeof(struct wm8988_priv),
GFP_KERNEL);
if (wm8988 == NULL)
return -ENOMEM;
i2c_set_clientdata(i2c, wm8988);
wm8988->regmap = devm_regmap_init_i2c(i2c, &wm8988_regmap);
if (IS_ERR(wm8988->regmap)) {
ret = PTR_ERR(wm8988->regmap);
dev_err(&i2c->dev, "Failed to init regmap: %d\n", ret);
return ret;
}
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_wm8988, &wm8988_dai, 1);
return ret;
}
static const struct i2c_device_id wm8988_i2c_id[] = {
{ "wm8988", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8988_i2c_id);
static struct i2c_driver wm8988_i2c_driver = {
.driver = {
.name = "wm8988",
},
.probe = wm8988_i2c_probe,
.id_table = wm8988_i2c_id,
};
#endif
static int __init wm8988_modinit(void)
{
int ret = 0;
#if IS_ENABLED(CONFIG_I2C)
ret = i2c_add_driver(&wm8988_i2c_driver);
if (ret != 0) {
printk(KERN_ERR "Failed to register WM8988 I2C driver: %d\n",
ret);
}
#endif
#if defined(CONFIG_SPI_MASTER)
ret = spi_register_driver(&wm8988_spi_driver);
if (ret != 0) {
printk(KERN_ERR "Failed to register WM8988 SPI driver: %d\n",
ret);
}
#endif
return ret;
}
module_init(wm8988_modinit);
static void __exit wm8988_exit(void)
{
#if IS_ENABLED(CONFIG_I2C)
i2c_del_driver(&wm8988_i2c_driver);
#endif
#if defined(CONFIG_SPI_MASTER)
spi_unregister_driver(&wm8988_spi_driver);
#endif
}
module_exit(wm8988_exit);
MODULE_DESCRIPTION("ASoC WM8988 driver");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8988.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// rt722-sdca.c -- rt722 SDCA ALSA SoC audio driver
//
// Copyright(c) 2023 Realtek Semiconductor Corp.
//
//
#include <linux/bitops.h>
#include <sound/core.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <sound/initval.h>
#include <sound/jack.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <sound/pcm.h>
#include <linux/pm_runtime.h>
#include <sound/pcm_params.h>
#include <linux/soundwire/sdw_registers.h>
#include <linux/slab.h>
#include <sound/soc-dapm.h>
#include <sound/tlv.h>
#include "rt722-sdca.h"
int rt722_sdca_index_write(struct rt722_sdca_priv *rt722,
unsigned int nid, unsigned int reg, unsigned int value)
{
struct regmap *regmap = rt722->mbq_regmap;
unsigned int addr = (nid << 20) | reg;
int ret;
ret = regmap_write(regmap, addr, value);
if (ret < 0)
dev_err(&rt722->slave->dev,
"Failed to set private value: %06x <= %04x ret=%d\n",
addr, value, ret);
return ret;
}
int rt722_sdca_index_read(struct rt722_sdca_priv *rt722,
unsigned int nid, unsigned int reg, unsigned int *value)
{
int ret;
struct regmap *regmap = rt722->mbq_regmap;
unsigned int addr = (nid << 20) | reg;
ret = regmap_read(regmap, addr, value);
if (ret < 0)
dev_err(&rt722->slave->dev,
"Failed to get private value: %06x => %04x ret=%d\n",
addr, *value, ret);
return ret;
}
static int rt722_sdca_index_update_bits(struct rt722_sdca_priv *rt722,
unsigned int nid, unsigned int reg, unsigned int mask, unsigned int val)
{
unsigned int tmp;
int ret;
ret = rt722_sdca_index_read(rt722, nid, reg, &tmp);
if (ret < 0)
return ret;
set_mask_bits(&tmp, mask, val);
return rt722_sdca_index_write(rt722, nid, reg, tmp);
}
static int rt722_sdca_btn_type(unsigned char *buffer)
{
if ((*buffer & 0xf0) == 0x10 || (*buffer & 0x0f) == 0x01 || (*(buffer + 1) == 0x01) ||
(*(buffer + 1) == 0x10))
return SND_JACK_BTN_2;
else if ((*buffer & 0xf0) == 0x20 || (*buffer & 0x0f) == 0x02 || (*(buffer + 1) == 0x02) ||
(*(buffer + 1) == 0x20))
return SND_JACK_BTN_3;
else if ((*buffer & 0xf0) == 0x40 || (*buffer & 0x0f) == 0x04 || (*(buffer + 1) == 0x04) ||
(*(buffer + 1) == 0x40))
return SND_JACK_BTN_0;
else if ((*buffer & 0xf0) == 0x80 || (*buffer & 0x0f) == 0x08 || (*(buffer + 1) == 0x08) ||
(*(buffer + 1) == 0x80))
return SND_JACK_BTN_1;
return 0;
}
static unsigned int rt722_sdca_button_detect(struct rt722_sdca_priv *rt722)
{
unsigned int btn_type = 0, offset, idx, val, owner;
int ret;
unsigned char buf[3];
/* get current UMP message owner */
ret = regmap_read(rt722->regmap,
SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01,
RT722_SDCA_CTL_HIDTX_CURRENT_OWNER, 0), &owner);
if (ret < 0)
return 0;
/* if owner is device then there is no button event from device */
if (owner == 1)
return 0;
/* read UMP message offset */
ret = regmap_read(rt722->regmap,
SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01,
RT722_SDCA_CTL_HIDTX_MESSAGE_OFFSET, 0), &offset);
if (ret < 0)
goto _end_btn_det_;
for (idx = 0; idx < sizeof(buf); idx++) {
ret = regmap_read(rt722->regmap,
RT722_BUF_ADDR_HID1 + offset + idx, &val);
if (ret < 0)
goto _end_btn_det_;
buf[idx] = val & 0xff;
}
if (buf[0] == 0x11)
btn_type = rt722_sdca_btn_type(&buf[1]);
_end_btn_det_:
/* Host is owner, so set back to device */
if (owner == 0)
/* set owner to device */
regmap_write(rt722->regmap,
SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01,
RT722_SDCA_CTL_HIDTX_CURRENT_OWNER, 0), 0x01);
return btn_type;
}
static int rt722_sdca_headset_detect(struct rt722_sdca_priv *rt722)
{
unsigned int det_mode;
int ret;
/* get detected_mode */
ret = regmap_read(rt722->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49,
RT722_SDCA_CTL_DETECTED_MODE, 0), &det_mode);
if (ret < 0)
goto io_error;
switch (det_mode) {
case 0x00:
rt722->jack_type = 0;
break;
case 0x03:
rt722->jack_type = SND_JACK_HEADPHONE;
break;
case 0x05:
rt722->jack_type = SND_JACK_HEADSET;
break;
}
/* write selected_mode */
if (det_mode) {
ret = regmap_write(rt722->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49,
RT722_SDCA_CTL_SELECTED_MODE, 0), det_mode);
if (ret < 0)
goto io_error;
}
dev_dbg(&rt722->slave->dev,
"%s, detected_mode=0x%x\n", __func__, det_mode);
return 0;
io_error:
pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret);
return ret;
}
static void rt722_sdca_jack_detect_handler(struct work_struct *work)
{
struct rt722_sdca_priv *rt722 =
container_of(work, struct rt722_sdca_priv, jack_detect_work.work);
int btn_type = 0, ret;
if (!rt722->hs_jack)
return;
if (!rt722->component->card || !rt722->component->card->instantiated)
return;
/* SDW_SCP_SDCA_INT_SDCA_6 is used for jack detection */
if (rt722->scp_sdca_stat1 & SDW_SCP_SDCA_INT_SDCA_6) {
ret = rt722_sdca_headset_detect(rt722);
if (ret < 0)
return;
}
/* SDW_SCP_SDCA_INT_SDCA_8 is used for button detection */
if (rt722->scp_sdca_stat2 & SDW_SCP_SDCA_INT_SDCA_8)
btn_type = rt722_sdca_button_detect(rt722);
if (rt722->jack_type == 0)
btn_type = 0;
dev_dbg(&rt722->slave->dev,
"in %s, jack_type=%d\n", __func__, rt722->jack_type);
dev_dbg(&rt722->slave->dev,
"in %s, btn_type=0x%x\n", __func__, btn_type);
dev_dbg(&rt722->slave->dev,
"in %s, scp_sdca_stat1=0x%x, scp_sdca_stat2=0x%x\n", __func__,
rt722->scp_sdca_stat1, rt722->scp_sdca_stat2);
snd_soc_jack_report(rt722->hs_jack, rt722->jack_type | btn_type,
SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3);
if (btn_type) {
/* button released */
snd_soc_jack_report(rt722->hs_jack, rt722->jack_type,
SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3);
mod_delayed_work(system_power_efficient_wq,
&rt722->jack_btn_check_work, msecs_to_jiffies(200));
}
}
static void rt722_sdca_btn_check_handler(struct work_struct *work)
{
struct rt722_sdca_priv *rt722 =
container_of(work, struct rt722_sdca_priv, jack_btn_check_work.work);
int btn_type = 0, ret, idx;
unsigned int det_mode, offset, val;
unsigned char buf[3];
ret = regmap_read(rt722->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49,
RT722_SDCA_CTL_DETECTED_MODE, 0), &det_mode);
if (ret < 0)
goto io_error;
/* pin attached */
if (det_mode) {
/* read UMP message offset */
ret = regmap_read(rt722->regmap,
SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01,
RT722_SDCA_CTL_HIDTX_MESSAGE_OFFSET, 0), &offset);
if (ret < 0)
goto io_error;
for (idx = 0; idx < sizeof(buf); idx++) {
ret = regmap_read(rt722->regmap,
RT722_BUF_ADDR_HID1 + offset + idx, &val);
if (ret < 0)
goto io_error;
buf[idx] = val & 0xff;
}
if (buf[0] == 0x11)
btn_type = rt722_sdca_btn_type(&buf[1]);
} else
rt722->jack_type = 0;
dev_dbg(&rt722->slave->dev, "%s, btn_type=0x%x\n", __func__, btn_type);
snd_soc_jack_report(rt722->hs_jack, rt722->jack_type | btn_type,
SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3);
if (btn_type) {
/* button released */
snd_soc_jack_report(rt722->hs_jack, rt722->jack_type,
SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3);
mod_delayed_work(system_power_efficient_wq,
&rt722->jack_btn_check_work, msecs_to_jiffies(200));
}
return;
io_error:
pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret);
}
static void rt722_sdca_jack_init(struct rt722_sdca_priv *rt722)
{
mutex_lock(&rt722->calibrate_mutex);
if (rt722->hs_jack) {
/* set SCP_SDCA_IntMask1[0]=1 */
sdw_write_no_pm(rt722->slave, SDW_SCP_SDCA_INTMASK1,
SDW_SCP_SDCA_INTMASK_SDCA_0 | SDW_SCP_SDCA_INTMASK_SDCA_6);
/* set SCP_SDCA_IntMask2[0]=1 */
sdw_write_no_pm(rt722->slave, SDW_SCP_SDCA_INTMASK2,
SDW_SCP_SDCA_INTMASK_SDCA_8);
dev_dbg(&rt722->slave->dev, "in %s enable\n", __func__);
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
RT722_HDA_LEGACY_UNSOL_CTL, 0x016E);
/* set XU(et03h) & XU(et0Dh) to Not bypassed */
regmap_write(rt722->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_XU03,
RT722_SDCA_CTL_SELECTED_MODE, 0), 0);
regmap_write(rt722->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_XU0D,
RT722_SDCA_CTL_SELECTED_MODE, 0), 0);
/* trigger GE interrupt */
rt722_sdca_index_update_bits(rt722, RT722_VENDOR_HDA_CTL,
RT722_GE_RELATED_CTL2, 0x4000, 0x4000);
}
mutex_unlock(&rt722->calibrate_mutex);
}
static int rt722_sdca_set_jack_detect(struct snd_soc_component *component,
struct snd_soc_jack *hs_jack, void *data)
{
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
int ret;
rt722->hs_jack = hs_jack;
ret = pm_runtime_resume_and_get(component->dev);
if (ret < 0) {
if (ret != -EACCES) {
dev_err(component->dev, "%s: failed to resume %d\n", __func__, ret);
return ret;
}
/* pm_runtime not enabled yet */
dev_dbg(component->dev, "%s: skipping jack init for now\n", __func__);
return 0;
}
rt722_sdca_jack_init(rt722);
pm_runtime_mark_last_busy(component->dev);
pm_runtime_put_autosuspend(component->dev);
return 0;
}
/* For SDCA control DAC/ADC Gain */
static int rt722_sdca_set_gain_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
unsigned int read_l, read_r, gain_l_val, gain_r_val;
unsigned int adc_vol_flag = 0, changed = 0;
unsigned int lvalue, rvalue;
const unsigned int interval_offset = 0xc0;
const unsigned int tendB = 0xa00;
if (strstr(ucontrol->id.name, "FU1E Capture Volume") ||
strstr(ucontrol->id.name, "FU0F Capture Volume"))
adc_vol_flag = 1;
regmap_read(rt722->mbq_regmap, mc->reg, &lvalue);
regmap_read(rt722->mbq_regmap, mc->rreg, &rvalue);
/* L Channel */
gain_l_val = ucontrol->value.integer.value[0];
if (gain_l_val > mc->max)
gain_l_val = mc->max;
if (mc->shift == 8) /* boost gain */
gain_l_val = gain_l_val * tendB;
else {
/* ADC/DAC gain */
if (adc_vol_flag)
gain_l_val = 0x1e00 - ((mc->max - gain_l_val) * interval_offset);
else
gain_l_val = 0 - ((mc->max - gain_l_val) * interval_offset);
gain_l_val &= 0xffff;
}
/* R Channel */
gain_r_val = ucontrol->value.integer.value[1];
if (gain_r_val > mc->max)
gain_r_val = mc->max;
if (mc->shift == 8) /* boost gain */
gain_r_val = gain_r_val * tendB;
else {
/* ADC/DAC gain */
if (adc_vol_flag)
gain_r_val = 0x1e00 - ((mc->max - gain_r_val) * interval_offset);
else
gain_r_val = 0 - ((mc->max - gain_r_val) * interval_offset);
gain_r_val &= 0xffff;
}
if (lvalue != gain_l_val || rvalue != gain_r_val)
changed = 1;
else
return 0;
/* Lch*/
regmap_write(rt722->mbq_regmap, mc->reg, gain_l_val);
/* Rch */
regmap_write(rt722->mbq_regmap, mc->rreg, gain_r_val);
regmap_read(rt722->mbq_regmap, mc->reg, &read_l);
regmap_read(rt722->mbq_regmap, mc->rreg, &read_r);
if (read_r == gain_r_val && read_l == gain_l_val)
return changed;
return -EIO;
}
static int rt722_sdca_set_gain_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
unsigned int read_l, read_r, ctl_l = 0, ctl_r = 0;
unsigned int adc_vol_flag = 0;
const unsigned int interval_offset = 0xc0;
const unsigned int tendB = 0xa00;
if (strstr(ucontrol->id.name, "FU1E Capture Volume") ||
strstr(ucontrol->id.name, "FU0F Capture Volume"))
adc_vol_flag = 1;
regmap_read(rt722->mbq_regmap, mc->reg, &read_l);
regmap_read(rt722->mbq_regmap, mc->rreg, &read_r);
if (mc->shift == 8) /* boost gain */
ctl_l = read_l / tendB;
else {
if (adc_vol_flag)
ctl_l = mc->max - (((0x1e00 - read_l) & 0xffff) / interval_offset);
else
ctl_l = mc->max - (((0 - read_l) & 0xffff) / interval_offset);
}
if (read_l != read_r) {
if (mc->shift == 8) /* boost gain */
ctl_r = read_r / tendB;
else { /* ADC/DAC gain */
if (adc_vol_flag)
ctl_r = mc->max - (((0x1e00 - read_r) & 0xffff) / interval_offset);
else
ctl_r = mc->max - (((0 - read_r) & 0xffff) / interval_offset);
}
} else {
ctl_r = ctl_l;
}
ucontrol->value.integer.value[0] = ctl_l;
ucontrol->value.integer.value[1] = ctl_r;
return 0;
}
static int rt722_sdca_set_fu1e_capture_ctl(struct rt722_sdca_priv *rt722)
{
int err, i;
unsigned int ch_mute;
for (i = 0; i < ARRAY_SIZE(rt722->fu1e_mixer_mute); i++) {
ch_mute = rt722->fu1e_dapm_mute || rt722->fu1e_mixer_mute[i];
err = regmap_write(rt722->regmap,
SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E,
RT722_SDCA_CTL_FU_MUTE, CH_01) + i, ch_mute);
if (err < 0)
return err;
}
return 0;
}
static int rt722_sdca_fu1e_capture_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
struct rt722_sdca_dmic_kctrl_priv *p =
(struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value;
unsigned int i;
for (i = 0; i < p->count; i++)
ucontrol->value.integer.value[i] = !rt722->fu1e_mixer_mute[i];
return 0;
}
static int rt722_sdca_fu1e_capture_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
struct rt722_sdca_dmic_kctrl_priv *p =
(struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value;
int err, changed = 0, i;
for (i = 0; i < p->count; i++) {
if (rt722->fu1e_mixer_mute[i] != !ucontrol->value.integer.value[i])
changed = 1;
rt722->fu1e_mixer_mute[i] = !ucontrol->value.integer.value[i];
}
err = rt722_sdca_set_fu1e_capture_ctl(rt722);
if (err < 0)
return err;
return changed;
}
static int rt722_sdca_set_fu0f_capture_ctl(struct rt722_sdca_priv *rt722)
{
int err;
unsigned int ch_l, ch_r;
ch_l = (rt722->fu0f_dapm_mute || rt722->fu0f_mixer_l_mute) ? 0x01 : 0x00;
ch_r = (rt722->fu0f_dapm_mute || rt722->fu0f_mixer_r_mute) ? 0x01 : 0x00;
err = regmap_write(rt722->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F,
RT722_SDCA_CTL_FU_MUTE, CH_L), ch_l);
if (err < 0)
return err;
err = regmap_write(rt722->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F,
RT722_SDCA_CTL_FU_MUTE, CH_R), ch_r);
if (err < 0)
return err;
return 0;
}
static int rt722_sdca_fu0f_capture_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = !rt722->fu0f_mixer_l_mute;
ucontrol->value.integer.value[1] = !rt722->fu0f_mixer_r_mute;
return 0;
}
static int rt722_sdca_fu0f_capture_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
int err, changed = 0;
if (rt722->fu0f_mixer_l_mute != !ucontrol->value.integer.value[0] ||
rt722->fu0f_mixer_r_mute != !ucontrol->value.integer.value[1])
changed = 1;
rt722->fu0f_mixer_l_mute = !ucontrol->value.integer.value[0];
rt722->fu0f_mixer_r_mute = !ucontrol->value.integer.value[1];
err = rt722_sdca_set_fu0f_capture_ctl(rt722);
if (err < 0)
return err;
return changed;
}
static int rt722_sdca_fu_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
struct rt722_sdca_dmic_kctrl_priv *p =
(struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value;
if (p->max == 1)
uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
else
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = p->count;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = p->max;
return 0;
}
static int rt722_sdca_dmic_set_gain_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
struct rt722_sdca_dmic_kctrl_priv *p =
(struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value;
unsigned int boost_step = 0x0a00;
unsigned int vol_max = 0x1e00;
unsigned int regvalue, ctl, i;
unsigned int adc_vol_flag = 0;
const unsigned int interval_offset = 0xc0;
if (strstr(ucontrol->id.name, "FU1E Capture Volume"))
adc_vol_flag = 1;
/* check all channels */
for (i = 0; i < p->count; i++) {
regmap_read(rt722->mbq_regmap, p->reg_base + i, ®value);
if (!adc_vol_flag) /* boost gain */
ctl = regvalue / boost_step;
else { /* ADC gain */
if (adc_vol_flag)
ctl = p->max - (((vol_max - regvalue) & 0xffff) / interval_offset);
else
ctl = p->max - (((0 - regvalue) & 0xffff) / interval_offset);
}
ucontrol->value.integer.value[i] = ctl;
}
return 0;
}
static int rt722_sdca_dmic_set_gain_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt722_sdca_dmic_kctrl_priv *p =
(struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value;
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
unsigned int boost_step = 0x0a00;
unsigned int vol_max = 0x1e00;
unsigned int gain_val[4];
unsigned int i, adc_vol_flag = 0, changed = 0;
unsigned int regvalue[4];
const unsigned int interval_offset = 0xc0;
int err;
if (strstr(ucontrol->id.name, "FU1E Capture Volume"))
adc_vol_flag = 1;
/* check all channels */
for (i = 0; i < p->count; i++) {
regmap_read(rt722->mbq_regmap, p->reg_base + i, ®value[i]);
gain_val[i] = ucontrol->value.integer.value[i];
if (gain_val[i] > p->max)
gain_val[i] = p->max;
if (!adc_vol_flag) /* boost gain */
gain_val[i] = gain_val[i] * boost_step;
else { /* ADC gain */
gain_val[i] = vol_max - ((p->max - gain_val[i]) * interval_offset);
gain_val[i] &= 0xffff;
}
if (regvalue[i] != gain_val[i])
changed = 1;
}
if (!changed)
return 0;
for (i = 0; i < p->count; i++) {
err = regmap_write(rt722->mbq_regmap, p->reg_base + i, gain_val[i]);
if (err < 0)
dev_err(&rt722->slave->dev, "%#08x can't be set\n", p->reg_base + i);
}
return changed;
}
#define RT722_SDCA_PR_VALUE(xreg_base, xcount, xmax, xinvert) \
((unsigned long)&(struct rt722_sdca_dmic_kctrl_priv) \
{.reg_base = xreg_base, .count = xcount, .max = xmax, \
.invert = xinvert})
#define RT722_SDCA_FU_CTRL(xname, reg_base, xmax, xinvert, xcount) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
.info = rt722_sdca_fu_info, \
.get = rt722_sdca_fu1e_capture_get, \
.put = rt722_sdca_fu1e_capture_put, \
.private_value = RT722_SDCA_PR_VALUE(reg_base, xcount, xmax, xinvert)}
#define RT722_SDCA_EXT_TLV(xname, reg_base, xhandler_get,\
xhandler_put, xcount, xmax, tlv_array) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
SNDRV_CTL_ELEM_ACCESS_READWRITE, \
.tlv.p = (tlv_array), \
.info = rt722_sdca_fu_info, \
.get = xhandler_get, .put = xhandler_put, \
.private_value = RT722_SDCA_PR_VALUE(reg_base, xcount, xmax, 0) }
static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0);
static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -1725, 75, 0);
static const DECLARE_TLV_DB_SCALE(boost_vol_tlv, 0, 1000, 0);
static const struct snd_kcontrol_new rt722_sdca_controls[] = {
/* Headphone playback settings */
SOC_DOUBLE_R_EXT_TLV("FU05 Playback Volume",
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05,
RT722_SDCA_CTL_FU_VOLUME, CH_L),
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05,
RT722_SDCA_CTL_FU_VOLUME, CH_R), 0, 0x57, 0,
rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, out_vol_tlv),
/* Headset mic capture settings */
SOC_DOUBLE_EXT("FU0F Capture Switch", SND_SOC_NOPM, 0, 1, 1, 0,
rt722_sdca_fu0f_capture_get, rt722_sdca_fu0f_capture_put),
SOC_DOUBLE_R_EXT_TLV("FU0F Capture Volume",
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F,
RT722_SDCA_CTL_FU_VOLUME, CH_L),
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F,
RT722_SDCA_CTL_FU_VOLUME, CH_R), 0, 0x3f, 0,
rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, mic_vol_tlv),
SOC_DOUBLE_R_EXT_TLV("FU33 Boost Volume",
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44,
RT722_SDCA_CTL_FU_CH_GAIN, CH_L),
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44,
RT722_SDCA_CTL_FU_CH_GAIN, CH_R), 8, 3, 0,
rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, boost_vol_tlv),
/* AMP playback settings */
SOC_DOUBLE_R_EXT_TLV("FU06 Playback Volume",
SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06,
RT722_SDCA_CTL_FU_VOLUME, CH_L),
SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06,
RT722_SDCA_CTL_FU_VOLUME, CH_R), 0, 0x57, 0,
rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, out_vol_tlv),
/* DMIC capture settings */
RT722_SDCA_FU_CTRL("FU1E Capture Switch",
SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E,
RT722_SDCA_CTL_FU_MUTE, CH_01), 1, 1, 4),
RT722_SDCA_EXT_TLV("FU1E Capture Volume",
SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E,
RT722_SDCA_CTL_FU_VOLUME, CH_01),
rt722_sdca_dmic_set_gain_get, rt722_sdca_dmic_set_gain_put,
4, 0x3f, mic_vol_tlv),
RT722_SDCA_EXT_TLV("FU15 Boost Volume",
SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_FU15,
RT722_SDCA_CTL_FU_CH_GAIN, CH_01),
rt722_sdca_dmic_set_gain_get, rt722_sdca_dmic_set_gain_put,
4, 3, boost_vol_tlv),
};
static int rt722_sdca_adc_mux_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_dapm_kcontrol_component(kcontrol);
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
unsigned int val = 0, mask_sft;
if (strstr(ucontrol->id.name, "ADC 22 Mux"))
mask_sft = 12;
else if (strstr(ucontrol->id.name, "ADC 24 Mux"))
mask_sft = 4;
else if (strstr(ucontrol->id.name, "ADC 25 Mux"))
mask_sft = 0;
else
return -EINVAL;
rt722_sdca_index_read(rt722, RT722_VENDOR_HDA_CTL,
RT722_HDA_LEGACY_MUX_CTL0, &val);
ucontrol->value.enumerated.item[0] = (val >> mask_sft) & 0x7;
return 0;
}
static int rt722_sdca_adc_mux_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_dapm_kcontrol_component(kcontrol);
struct snd_soc_dapm_context *dapm =
snd_soc_dapm_kcontrol_dapm(kcontrol);
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int *item = ucontrol->value.enumerated.item;
unsigned int val, val2 = 0, change, mask_sft;
if (item[0] >= e->items)
return -EINVAL;
if (strstr(ucontrol->id.name, "ADC 22 Mux"))
mask_sft = 12;
else if (strstr(ucontrol->id.name, "ADC 24 Mux"))
mask_sft = 4;
else if (strstr(ucontrol->id.name, "ADC 25 Mux"))
mask_sft = 0;
else
return -EINVAL;
val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
rt722_sdca_index_read(rt722, RT722_VENDOR_HDA_CTL,
RT722_HDA_LEGACY_MUX_CTL0, &val2);
val2 = (0x7 << mask_sft) & val2;
if (val == val2)
change = 0;
else
change = 1;
if (change)
rt722_sdca_index_update_bits(rt722, RT722_VENDOR_HDA_CTL,
RT722_HDA_LEGACY_MUX_CTL0, 0x7 << mask_sft,
val << mask_sft);
snd_soc_dapm_mux_update_power(dapm, kcontrol,
item[0], e, NULL);
return change;
}
static const char * const adc22_mux_text[] = {
"MIC2",
"LINE1",
"LINE2",
};
static const char * const adc07_10_mux_text[] = {
"DMIC1",
"DMIC2",
};
static SOC_ENUM_SINGLE_DECL(
rt722_adc22_enum, SND_SOC_NOPM, 0, adc22_mux_text);
static SOC_ENUM_SINGLE_DECL(
rt722_adc24_enum, SND_SOC_NOPM, 0, adc07_10_mux_text);
static SOC_ENUM_SINGLE_DECL(
rt722_adc25_enum, SND_SOC_NOPM, 0, adc07_10_mux_text);
static const struct snd_kcontrol_new rt722_sdca_adc22_mux =
SOC_DAPM_ENUM_EXT("ADC 22 Mux", rt722_adc22_enum,
rt722_sdca_adc_mux_get, rt722_sdca_adc_mux_put);
static const struct snd_kcontrol_new rt722_sdca_adc24_mux =
SOC_DAPM_ENUM_EXT("ADC 24 Mux", rt722_adc24_enum,
rt722_sdca_adc_mux_get, rt722_sdca_adc_mux_put);
static const struct snd_kcontrol_new rt722_sdca_adc25_mux =
SOC_DAPM_ENUM_EXT("ADC 25 Mux", rt722_adc25_enum,
rt722_sdca_adc_mux_get, rt722_sdca_adc_mux_put);
static int rt722_sdca_fu42_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
unsigned char unmute = 0x0, mute = 0x1;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_write(rt722->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05,
RT722_SDCA_CTL_FU_MUTE, CH_L), unmute);
regmap_write(rt722->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05,
RT722_SDCA_CTL_FU_MUTE, CH_R), unmute);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_write(rt722->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05,
RT722_SDCA_CTL_FU_MUTE, CH_L), mute);
regmap_write(rt722->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05,
RT722_SDCA_CTL_FU_MUTE, CH_R), mute);
break;
}
return 0;
}
static int rt722_sdca_fu21_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
unsigned char unmute = 0x0, mute = 0x1;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_write(rt722->regmap,
SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06,
RT722_SDCA_CTL_FU_MUTE, CH_L), unmute);
regmap_write(rt722->regmap,
SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06,
RT722_SDCA_CTL_FU_MUTE, CH_R), unmute);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_write(rt722->regmap,
SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06,
RT722_SDCA_CTL_FU_MUTE, CH_L), mute);
regmap_write(rt722->regmap,
SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06,
RT722_SDCA_CTL_FU_MUTE, CH_R), mute);
break;
}
return 0;
}
static int rt722_sdca_fu113_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
rt722->fu1e_dapm_mute = false;
rt722_sdca_set_fu1e_capture_ctl(rt722);
break;
case SND_SOC_DAPM_PRE_PMD:
rt722->fu1e_dapm_mute = true;
rt722_sdca_set_fu1e_capture_ctl(rt722);
break;
}
return 0;
}
static int rt722_sdca_fu36_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
rt722->fu0f_dapm_mute = false;
rt722_sdca_set_fu0f_capture_ctl(rt722);
break;
case SND_SOC_DAPM_PRE_PMD:
rt722->fu0f_dapm_mute = true;
rt722_sdca_set_fu0f_capture_ctl(rt722);
break;
}
return 0;
}
static int rt722_sdca_pde47_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
unsigned char ps0 = 0x0, ps3 = 0x3;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_write(rt722->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40,
RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_write(rt722->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40,
RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3);
break;
}
return 0;
}
static int rt722_sdca_pde23_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
unsigned char ps0 = 0x0, ps3 = 0x3;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_write(rt722->regmap,
SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23,
RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_write(rt722->regmap,
SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23,
RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3);
break;
}
return 0;
}
static int rt722_sdca_pde11_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
unsigned char ps0 = 0x0, ps3 = 0x3;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_write(rt722->regmap,
SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A,
RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_write(rt722->regmap,
SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A,
RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3);
break;
}
return 0;
}
static int rt722_sdca_pde12_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
unsigned char ps0 = 0x0, ps3 = 0x3;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_write(rt722->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12,
RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_write(rt722->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12,
RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3);
break;
}
return 0;
}
static const struct snd_soc_dapm_widget rt722_sdca_dapm_widgets[] = {
SND_SOC_DAPM_OUTPUT("HP"),
SND_SOC_DAPM_OUTPUT("SPK"),
SND_SOC_DAPM_INPUT("MIC2"),
SND_SOC_DAPM_INPUT("LINE1"),
SND_SOC_DAPM_INPUT("LINE2"),
SND_SOC_DAPM_INPUT("DMIC1_2"),
SND_SOC_DAPM_INPUT("DMIC3_4"),
SND_SOC_DAPM_SUPPLY("PDE 23", SND_SOC_NOPM, 0, 0,
rt722_sdca_pde23_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SUPPLY("PDE 47", SND_SOC_NOPM, 0, 0,
rt722_sdca_pde47_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SUPPLY("PDE 11", SND_SOC_NOPM, 0, 0,
rt722_sdca_pde11_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SUPPLY("PDE 12", SND_SOC_NOPM, 0, 0,
rt722_sdca_pde12_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_DAC_E("FU 21", NULL, SND_SOC_NOPM, 0, 0,
rt722_sdca_fu21_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_DAC_E("FU 42", NULL, SND_SOC_NOPM, 0, 0,
rt722_sdca_fu42_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_ADC_E("FU 36", NULL, SND_SOC_NOPM, 0, 0,
rt722_sdca_fu36_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_ADC_E("FU 113", NULL, SND_SOC_NOPM, 0, 0,
rt722_sdca_fu113_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_MUX("ADC 22 Mux", SND_SOC_NOPM, 0, 0,
&rt722_sdca_adc22_mux),
SND_SOC_DAPM_MUX("ADC 24 Mux", SND_SOC_NOPM, 0, 0,
&rt722_sdca_adc24_mux),
SND_SOC_DAPM_MUX("ADC 25 Mux", SND_SOC_NOPM, 0, 0,
&rt722_sdca_adc25_mux),
SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Headphone Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("DP2TX", "DP2 Headset Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("DP3RX", "DP3 Speaker Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("DP6TX", "DP6 DMic Capture", 0, SND_SOC_NOPM, 0, 0),
};
static const struct snd_soc_dapm_route rt722_sdca_audio_map[] = {
{"FU 42", NULL, "DP1RX"},
{"FU 21", NULL, "DP3RX"},
{"ADC 22 Mux", "MIC2", "MIC2"},
{"ADC 22 Mux", "LINE1", "LINE1"},
{"ADC 22 Mux", "LINE2", "LINE2"},
{"ADC 24 Mux", "DMIC1", "DMIC1_2"},
{"ADC 24 Mux", "DMIC2", "DMIC3_4"},
{"ADC 25 Mux", "DMIC1", "DMIC1_2"},
{"ADC 25 Mux", "DMIC2", "DMIC3_4"},
{"FU 36", NULL, "PDE 12"},
{"FU 36", NULL, "ADC 22 Mux"},
{"FU 113", NULL, "PDE 11"},
{"FU 113", NULL, "ADC 24 Mux"},
{"FU 113", NULL, "ADC 25 Mux"},
{"DP2TX", NULL, "FU 36"},
{"DP6TX", NULL, "FU 113"},
{"HP", NULL, "PDE 47"},
{"HP", NULL, "FU 42"},
{"SPK", NULL, "PDE 23"},
{"SPK", NULL, "FU 21"},
};
static int rt722_sdca_parse_dt(struct rt722_sdca_priv *rt722, struct device *dev)
{
device_property_read_u32(dev, "realtek,jd-src", &rt722->jd_src);
return 0;
}
static int rt722_sdca_probe(struct snd_soc_component *component)
{
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
int ret;
rt722_sdca_parse_dt(rt722, &rt722->slave->dev);
rt722->component = component;
ret = pm_runtime_resume(component->dev);
if (ret < 0 && ret != -EACCES)
return ret;
return 0;
}
static const struct snd_soc_component_driver soc_sdca_dev_rt722 = {
.probe = rt722_sdca_probe,
.controls = rt722_sdca_controls,
.num_controls = ARRAY_SIZE(rt722_sdca_controls),
.dapm_widgets = rt722_sdca_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt722_sdca_dapm_widgets),
.dapm_routes = rt722_sdca_audio_map,
.num_dapm_routes = ARRAY_SIZE(rt722_sdca_audio_map),
.set_jack = rt722_sdca_set_jack_detect,
.endianness = 1,
};
static int rt722_sdca_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
int direction)
{
snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
return 0;
}
static void rt722_sdca_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
snd_soc_dai_set_dma_data(dai, substream, NULL);
}
static int rt722_sdca_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
struct sdw_stream_config stream_config;
struct sdw_port_config port_config;
enum sdw_data_direction direction;
struct sdw_stream_runtime *sdw_stream;
int retval, port, num_channels;
unsigned int sampling_rate;
dev_dbg(dai->dev, "%s %s", __func__, dai->name);
sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
if (!sdw_stream)
return -EINVAL;
if (!rt722->slave)
return -EINVAL;
/*
* RT722_AIF1 with port = 1 for headphone playback
* RT722_AIF1 with port = 2 for headset-mic capture
* RT722_AIF2 with port = 3 for speaker playback
* RT722_AIF3 with port = 6 for digital-mic capture
*/
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
direction = SDW_DATA_DIR_RX;
if (dai->id == RT722_AIF1)
port = 1;
else if (dai->id == RT722_AIF2)
port = 3;
else
return -EINVAL;
} else {
direction = SDW_DATA_DIR_TX;
if (dai->id == RT722_AIF1)
port = 2;
else if (dai->id == RT722_AIF3)
port = 6;
else
return -EINVAL;
}
stream_config.frame_rate = params_rate(params);
stream_config.ch_count = params_channels(params);
stream_config.bps = snd_pcm_format_width(params_format(params));
stream_config.direction = direction;
num_channels = params_channels(params);
port_config.ch_mask = GENMASK(num_channels - 1, 0);
port_config.num = port;
retval = sdw_stream_add_slave(rt722->slave, &stream_config,
&port_config, 1, sdw_stream);
if (retval) {
dev_err(dai->dev, "Unable to configure port\n");
return retval;
}
if (params_channels(params) > 16) {
dev_err(component->dev, "Unsupported channels %d\n",
params_channels(params));
return -EINVAL;
}
/* sampling rate configuration */
switch (params_rate(params)) {
case 44100:
sampling_rate = RT722_SDCA_RATE_44100HZ;
break;
case 48000:
sampling_rate = RT722_SDCA_RATE_48000HZ;
break;
case 96000:
sampling_rate = RT722_SDCA_RATE_96000HZ;
break;
case 192000:
sampling_rate = RT722_SDCA_RATE_192000HZ;
break;
default:
dev_err(component->dev, "Rate %d is not supported\n",
params_rate(params));
return -EINVAL;
}
/* set sampling frequency */
if (dai->id == RT722_AIF1) {
regmap_write(rt722->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS01,
RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate);
regmap_write(rt722->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS11,
RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate);
}
if (dai->id == RT722_AIF2)
regmap_write(rt722->regmap,
SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_CS31,
RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate);
if (dai->id == RT722_AIF3)
regmap_write(rt722->regmap,
SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_CS1F,
RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate);
return 0;
}
static int rt722_sdca_pcm_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
struct sdw_stream_runtime *sdw_stream =
snd_soc_dai_get_dma_data(dai, substream);
if (!rt722->slave)
return -EINVAL;
sdw_stream_remove_slave(rt722->slave, sdw_stream);
return 0;
}
#define RT722_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
#define RT722_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE)
static const struct snd_soc_dai_ops rt722_sdca_ops = {
.hw_params = rt722_sdca_pcm_hw_params,
.hw_free = rt722_sdca_pcm_hw_free,
.set_stream = rt722_sdca_set_sdw_stream,
.shutdown = rt722_sdca_shutdown,
};
static struct snd_soc_dai_driver rt722_sdca_dai[] = {
{
.name = "rt722-sdca-aif1",
.id = RT722_AIF1,
.playback = {
.stream_name = "DP1 Headphone Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT722_STEREO_RATES,
.formats = RT722_FORMATS,
},
.capture = {
.stream_name = "DP2 Headset Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT722_STEREO_RATES,
.formats = RT722_FORMATS,
},
.ops = &rt722_sdca_ops,
},
{
.name = "rt722-sdca-aif2",
.id = RT722_AIF2,
.playback = {
.stream_name = "DP3 Speaker Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT722_STEREO_RATES,
.formats = RT722_FORMATS,
},
.ops = &rt722_sdca_ops,
},
{
.name = "rt722-sdca-aif3",
.id = RT722_AIF3,
.capture = {
.stream_name = "DP6 DMic Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT722_STEREO_RATES,
.formats = RT722_FORMATS,
},
.ops = &rt722_sdca_ops,
}
};
int rt722_sdca_init(struct device *dev, struct regmap *regmap,
struct regmap *mbq_regmap, struct sdw_slave *slave)
{
struct rt722_sdca_priv *rt722;
rt722 = devm_kzalloc(dev, sizeof(*rt722), GFP_KERNEL);
if (!rt722)
return -ENOMEM;
dev_set_drvdata(dev, rt722);
rt722->slave = slave;
rt722->regmap = regmap;
rt722->mbq_regmap = mbq_regmap;
mutex_init(&rt722->calibrate_mutex);
mutex_init(&rt722->disable_irq_lock);
INIT_DELAYED_WORK(&rt722->jack_detect_work, rt722_sdca_jack_detect_handler);
INIT_DELAYED_WORK(&rt722->jack_btn_check_work, rt722_sdca_btn_check_handler);
/*
* Mark hw_init to false
* HW init will be performed when device reports present
*/
rt722->hw_init = false;
rt722->first_hw_init = false;
rt722->fu1e_dapm_mute = true;
rt722->fu0f_dapm_mute = true;
rt722->fu0f_mixer_l_mute = rt722->fu0f_mixer_r_mute = true;
rt722->fu1e_mixer_mute[0] = rt722->fu1e_mixer_mute[1] =
rt722->fu1e_mixer_mute[2] = rt722->fu1e_mixer_mute[3] = true;
return devm_snd_soc_register_component(dev,
&soc_sdca_dev_rt722, rt722_sdca_dai, ARRAY_SIZE(rt722_sdca_dai));
}
static void rt722_sdca_dmic_preset(struct rt722_sdca_priv *rt722)
{
/* Set AD07 power entity floating control */
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
RT722_ADC0A_08_PDE_FLOAT_CTL, 0x2a29);
/* Set AD10 power entity floating control */
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
RT722_ADC10_PDE_FLOAT_CTL, 0x2a00);
/* Set DMIC1/DMIC2 power entity floating control */
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
RT722_DMIC1_2_PDE_FLOAT_CTL, 0x2a2a);
/* Set DMIC2 IT entity floating control */
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
RT722_DMIC_ENT_FLOAT_CTL, 0x2626);
/* Set AD10 FU entity floating control */
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
RT722_ADC_ENT_FLOAT_CTL, 0x1e00);
/* Set DMIC2 FU entity floating control */
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
RT722_DMIC_GAIN_ENT_FLOAT_CTL0, 0x1515);
/* Set AD10 FU channel floating control */
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
RT722_ADC_VOL_CH_FLOAT_CTL, 0x0304);
/* Set DMIC2 FU channel floating control */
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
RT722_DMIC_GAIN_ENT_FLOAT_CTL2, 0x0304);
/* vf71f_r12_07_06 and vf71f_r13_07_06 = 2’b00 */
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
RT722_HDA_LEGACY_CONFIG_CTL0, 0x0000);
/* Enable vf707_r12_05/vf707_r13_05 */
regmap_write(rt722->regmap,
SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_IT26,
RT722_SDCA_CTL_VENDOR_DEF, 0), 0x01);
/* Fine tune PDE2A latency */
regmap_write(rt722->regmap, 0x2f5c, 0x25);
}
static void rt722_sdca_amp_preset(struct rt722_sdca_priv *rt722)
{
/* Set DVQ=01 */
rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_CLSD_CTRL6,
0xc215);
/* Reset dc_cal_top */
rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DC_CALIB_CTRL,
0x702c);
/* W1C Trigger Calibration */
rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DC_CALIB_CTRL,
0xf02d);
/* Set DAC02/ClassD power entity floating control */
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_AMP_PDE_FLOAT_CTL,
0x2323);
/* Set EAPD high */
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_EAPD_CTL,
0x0002);
/* Enable vf707_r14 */
regmap_write(rt722->regmap,
SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_OT23,
RT722_SDCA_CTL_VENDOR_DEF, CH_08), 0x04);
}
static void rt722_sdca_jack_preset(struct rt722_sdca_priv *rt722)
{
int loop_check, chk_cnt = 100, ret;
unsigned int calib_status = 0;
/* Read eFuse */
rt722_sdca_index_write(rt722, RT722_VENDOR_SPK_EFUSE, RT722_DC_CALIB_CTRL,
0x4808);
/* Button A, B, C, D bypass mode */
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL4,
0xcf00);
/* HID1 slot enable */
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL5,
0x000f);
/* Report ID for HID1 */
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL0,
0x1100);
/* OSC/OOC for slot 2, 3 */
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL7,
0x0c12);
/* Set JD de-bounce clock control */
rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_JD_CTRL1,
0x7002);
/* Set DVQ=01 */
rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_CLSD_CTRL6,
0xc215);
/* FSM switch to calibration manual mode */
rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_FSM_CTL,
0x4100);
/* W1C Trigger DC calibration (HP) */
rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DAC_DC_CALI_CTL3,
0x008d);
/* check HP calibration FSM status */
for (loop_check = 0; loop_check < chk_cnt; loop_check++) {
ret = rt722_sdca_index_read(rt722, RT722_VENDOR_CALI,
RT722_DAC_DC_CALI_CTL3, &calib_status);
if (ret < 0 || loop_check == chk_cnt)
dev_dbg(&rt722->slave->dev, "calibration failed!, ret=%d\n", ret);
if ((calib_status & 0x0040) == 0x0)
break;
}
/* Release HP-JD, EN_CBJ_TIE_GL/R open, en_osw gating auto done bit */
rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_DIGITAL_MISC_CTRL4,
0x0010);
/* Set ADC09 power entity floating control */
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_ADC0A_08_PDE_FLOAT_CTL,
0x2a12);
/* Set MIC2 and LINE1 power entity floating control */
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_MIC2_LINE2_PDE_FLOAT_CTL,
0x3429);
/* Set ET41h and LINE2 power entity floating control */
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_ET41_LINE2_PDE_FLOAT_CTL,
0x4112);
/* Set DAC03 and HP power entity floating control */
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_DAC03_HP_PDE_FLOAT_CTL,
0x4040);
/* Fine tune PDE40 latency */
regmap_write(rt722->regmap, 0x2f58, 0x07);
}
int rt722_sdca_io_init(struct device *dev, struct sdw_slave *slave)
{
struct rt722_sdca_priv *rt722 = dev_get_drvdata(dev);
rt722->disable_irq = false;
if (rt722->hw_init)
return 0;
if (rt722->first_hw_init) {
regcache_cache_only(rt722->regmap, false);
regcache_cache_bypass(rt722->regmap, true);
regcache_cache_only(rt722->mbq_regmap, false);
regcache_cache_bypass(rt722->mbq_regmap, true);
} else {
/*
* PM runtime is only enabled when a Slave reports as Attached
*/
/* set autosuspend parameters */
pm_runtime_set_autosuspend_delay(&slave->dev, 3000);
pm_runtime_use_autosuspend(&slave->dev);
/* update count of parent 'active' children */
pm_runtime_set_active(&slave->dev);
/* make sure the device does not suspend immediately */
pm_runtime_mark_last_busy(&slave->dev);
pm_runtime_enable(&slave->dev);
}
pm_runtime_get_noresume(&slave->dev);
rt722_sdca_dmic_preset(rt722);
rt722_sdca_amp_preset(rt722);
rt722_sdca_jack_preset(rt722);
if (rt722->first_hw_init) {
regcache_cache_bypass(rt722->regmap, false);
regcache_mark_dirty(rt722->regmap);
regcache_cache_bypass(rt722->mbq_regmap, false);
regcache_mark_dirty(rt722->mbq_regmap);
} else
rt722->first_hw_init = true;
/* Mark Slave initialization complete */
rt722->hw_init = true;
pm_runtime_mark_last_busy(&slave->dev);
pm_runtime_put_autosuspend(&slave->dev);
dev_dbg(&slave->dev, "%s hw_init complete\n", __func__);
return 0;
}
MODULE_DESCRIPTION("ASoC RT722 SDCA SDW driver");
MODULE_AUTHOR("Jack Yu <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/rt722-sdca.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8711.c -- WM8711 ALSA SoC Audio driver
*
* Copyright 2006 Wolfson Microelectronics
*
* Author: Mike Arthur <[email protected]>
*
* Based on wm8731.c by Richard Purdie
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <linux/of_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <sound/initval.h>
#include "wm8711.h"
/* codec private data */
struct wm8711_priv {
struct regmap *regmap;
unsigned int sysclk;
};
/*
* wm8711 register cache
* We can't read the WM8711 register space when we are
* using 2 wire for device control, so we cache them instead.
* There is no point in caching the reset register
*/
static const struct reg_default wm8711_reg_defaults[] = {
{ 0, 0x0079 }, { 1, 0x0079 }, { 2, 0x000a }, { 3, 0x0008 },
{ 4, 0x009f }, { 5, 0x000a }, { 6, 0x0000 }, { 7, 0x0000 },
};
static bool wm8711_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8711_RESET:
return true;
default:
return false;
}
}
#define wm8711_reset(c) snd_soc_component_write(c, WM8711_RESET, 0)
static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
static const struct snd_kcontrol_new wm8711_snd_controls[] = {
SOC_DOUBLE_R_TLV("Master Playback Volume", WM8711_LOUT1V, WM8711_ROUT1V,
0, 127, 0, out_tlv),
SOC_DOUBLE_R("Master Playback ZC Switch", WM8711_LOUT1V, WM8711_ROUT1V,
7, 1, 0),
};
/* Output Mixer */
static const struct snd_kcontrol_new wm8711_output_mixer_controls[] = {
SOC_DAPM_SINGLE("Line Bypass Switch", WM8711_APANA, 3, 1, 0),
SOC_DAPM_SINGLE("HiFi Playback Switch", WM8711_APANA, 4, 1, 0),
};
static const struct snd_soc_dapm_widget wm8711_dapm_widgets[] = {
SND_SOC_DAPM_MIXER("Output Mixer", WM8711_PWR, 4, 1,
&wm8711_output_mixer_controls[0],
ARRAY_SIZE(wm8711_output_mixer_controls)),
SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM8711_PWR, 3, 1),
SND_SOC_DAPM_OUTPUT("LOUT"),
SND_SOC_DAPM_OUTPUT("LHPOUT"),
SND_SOC_DAPM_OUTPUT("ROUT"),
SND_SOC_DAPM_OUTPUT("RHPOUT"),
};
static const struct snd_soc_dapm_route wm8711_intercon[] = {
/* output mixer */
{"Output Mixer", "Line Bypass Switch", "Line Input"},
{"Output Mixer", "HiFi Playback Switch", "DAC"},
/* outputs */
{"RHPOUT", NULL, "Output Mixer"},
{"ROUT", NULL, "Output Mixer"},
{"LHPOUT", NULL, "Output Mixer"},
{"LOUT", NULL, "Output Mixer"},
};
struct _coeff_div {
u32 mclk;
u32 rate;
u16 fs;
u8 sr:4;
u8 bosr:1;
u8 usb:1;
};
/* codec mclk clock divider coefficients */
static const struct _coeff_div coeff_div[] = {
/* 48k */
{12288000, 48000, 256, 0x0, 0x0, 0x0},
{18432000, 48000, 384, 0x0, 0x1, 0x0},
{12000000, 48000, 250, 0x0, 0x0, 0x1},
/* 32k */
{12288000, 32000, 384, 0x6, 0x0, 0x0},
{18432000, 32000, 576, 0x6, 0x1, 0x0},
{12000000, 32000, 375, 0x6, 0x0, 0x1},
/* 8k */
{12288000, 8000, 1536, 0x3, 0x0, 0x0},
{18432000, 8000, 2304, 0x3, 0x1, 0x0},
{11289600, 8000, 1408, 0xb, 0x0, 0x0},
{16934400, 8000, 2112, 0xb, 0x1, 0x0},
{12000000, 8000, 1500, 0x3, 0x0, 0x1},
/* 96k */
{12288000, 96000, 128, 0x7, 0x0, 0x0},
{18432000, 96000, 192, 0x7, 0x1, 0x0},
{12000000, 96000, 125, 0x7, 0x0, 0x1},
/* 44.1k */
{11289600, 44100, 256, 0x8, 0x0, 0x0},
{16934400, 44100, 384, 0x8, 0x1, 0x0},
{12000000, 44100, 272, 0x8, 0x1, 0x1},
/* 88.2k */
{11289600, 88200, 128, 0xf, 0x0, 0x0},
{16934400, 88200, 192, 0xf, 0x1, 0x0},
{12000000, 88200, 136, 0xf, 0x1, 0x1},
};
static inline int get_coeff(int mclk, int rate)
{
int i;
for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
return i;
}
return 0;
}
static int wm8711_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm8711_priv *wm8711 = snd_soc_component_get_drvdata(component);
u16 iface = snd_soc_component_read(component, WM8711_IFACE) & 0xfff3;
int i = get_coeff(wm8711->sysclk, params_rate(params));
u16 srate = (coeff_div[i].sr << 2) |
(coeff_div[i].bosr << 1) | coeff_div[i].usb;
snd_soc_component_write(component, WM8711_SRATE, srate);
/* bit size */
switch (params_width(params)) {
case 16:
break;
case 20:
iface |= 0x0004;
break;
case 24:
iface |= 0x0008;
break;
}
snd_soc_component_write(component, WM8711_IFACE, iface);
return 0;
}
static int wm8711_pcm_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
/* set active */
snd_soc_component_write(component, WM8711_ACTIVE, 0x0001);
return 0;
}
static void wm8711_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
/* deactivate */
if (!snd_soc_component_active(component)) {
udelay(50);
snd_soc_component_write(component, WM8711_ACTIVE, 0x0);
}
}
static int wm8711_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
u16 mute_reg = snd_soc_component_read(component, WM8711_APDIGI) & 0xfff7;
if (mute)
snd_soc_component_write(component, WM8711_APDIGI, mute_reg | 0x8);
else
snd_soc_component_write(component, WM8711_APDIGI, mute_reg);
return 0;
}
static int wm8711_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct wm8711_priv *wm8711 = snd_soc_component_get_drvdata(component);
switch (freq) {
case 11289600:
case 12000000:
case 12288000:
case 16934400:
case 18432000:
wm8711->sysclk = freq;
return 0;
}
return -EINVAL;
}
static int wm8711_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
u16 iface = snd_soc_component_read(component, WM8711_IFACE) & 0x000c;
/* set master/slave audio interface */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
iface |= 0x0040;
break;
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface |= 0x0002;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
iface |= 0x0001;
break;
case SND_SOC_DAIFMT_DSP_A:
iface |= 0x0003;
break;
case SND_SOC_DAIFMT_DSP_B:
iface |= 0x0013;
break;
default:
return -EINVAL;
}
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
iface |= 0x0090;
break;
case SND_SOC_DAIFMT_IB_NF:
iface |= 0x0080;
break;
case SND_SOC_DAIFMT_NB_IF:
iface |= 0x0010;
break;
default:
return -EINVAL;
}
/* set iface */
snd_soc_component_write(component, WM8711_IFACE, iface);
return 0;
}
static int wm8711_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct wm8711_priv *wm8711 = snd_soc_component_get_drvdata(component);
u16 reg = snd_soc_component_read(component, WM8711_PWR) & 0xff7f;
switch (level) {
case SND_SOC_BIAS_ON:
snd_soc_component_write(component, WM8711_PWR, reg);
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
regcache_sync(wm8711->regmap);
snd_soc_component_write(component, WM8711_PWR, reg | 0x0040);
break;
case SND_SOC_BIAS_OFF:
snd_soc_component_write(component, WM8711_ACTIVE, 0x0);
snd_soc_component_write(component, WM8711_PWR, 0xffff);
break;
}
return 0;
}
#define WM8711_RATES SNDRV_PCM_RATE_8000_96000
#define WM8711_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE)
static const struct snd_soc_dai_ops wm8711_ops = {
.prepare = wm8711_pcm_prepare,
.hw_params = wm8711_hw_params,
.shutdown = wm8711_shutdown,
.mute_stream = wm8711_mute,
.set_sysclk = wm8711_set_dai_sysclk,
.set_fmt = wm8711_set_dai_fmt,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver wm8711_dai = {
.name = "wm8711-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM8711_RATES,
.formats = WM8711_FORMATS,
},
.ops = &wm8711_ops,
};
static int wm8711_probe(struct snd_soc_component *component)
{
int ret;
ret = wm8711_reset(component);
if (ret < 0) {
dev_err(component->dev, "Failed to issue reset\n");
return ret;
}
/* Latch the update bits */
snd_soc_component_update_bits(component, WM8711_LOUT1V, 0x0100, 0x0100);
snd_soc_component_update_bits(component, WM8711_ROUT1V, 0x0100, 0x0100);
return ret;
}
static const struct snd_soc_component_driver soc_component_dev_wm8711 = {
.probe = wm8711_probe,
.set_bias_level = wm8711_set_bias_level,
.controls = wm8711_snd_controls,
.num_controls = ARRAY_SIZE(wm8711_snd_controls),
.dapm_widgets = wm8711_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8711_dapm_widgets),
.dapm_routes = wm8711_intercon,
.num_dapm_routes = ARRAY_SIZE(wm8711_intercon),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct of_device_id wm8711_of_match[] = {
{ .compatible = "wlf,wm8711", },
{ }
};
MODULE_DEVICE_TABLE(of, wm8711_of_match);
static const struct regmap_config wm8711_regmap = {
.reg_bits = 7,
.val_bits = 9,
.max_register = WM8711_RESET,
.reg_defaults = wm8711_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8711_reg_defaults),
.cache_type = REGCACHE_MAPLE,
.volatile_reg = wm8711_volatile,
};
#if defined(CONFIG_SPI_MASTER)
static int wm8711_spi_probe(struct spi_device *spi)
{
struct wm8711_priv *wm8711;
int ret;
wm8711 = devm_kzalloc(&spi->dev, sizeof(struct wm8711_priv),
GFP_KERNEL);
if (wm8711 == NULL)
return -ENOMEM;
wm8711->regmap = devm_regmap_init_spi(spi, &wm8711_regmap);
if (IS_ERR(wm8711->regmap))
return PTR_ERR(wm8711->regmap);
spi_set_drvdata(spi, wm8711);
ret = devm_snd_soc_register_component(&spi->dev,
&soc_component_dev_wm8711, &wm8711_dai, 1);
return ret;
}
static struct spi_driver wm8711_spi_driver = {
.driver = {
.name = "wm8711",
.of_match_table = wm8711_of_match,
},
.probe = wm8711_spi_probe,
};
#endif /* CONFIG_SPI_MASTER */
#if IS_ENABLED(CONFIG_I2C)
static int wm8711_i2c_probe(struct i2c_client *client)
{
struct wm8711_priv *wm8711;
int ret;
wm8711 = devm_kzalloc(&client->dev, sizeof(struct wm8711_priv),
GFP_KERNEL);
if (wm8711 == NULL)
return -ENOMEM;
wm8711->regmap = devm_regmap_init_i2c(client, &wm8711_regmap);
if (IS_ERR(wm8711->regmap))
return PTR_ERR(wm8711->regmap);
i2c_set_clientdata(client, wm8711);
ret = devm_snd_soc_register_component(&client->dev,
&soc_component_dev_wm8711, &wm8711_dai, 1);
return ret;
}
static const struct i2c_device_id wm8711_i2c_id[] = {
{ "wm8711", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8711_i2c_id);
static struct i2c_driver wm8711_i2c_driver = {
.driver = {
.name = "wm8711",
.of_match_table = wm8711_of_match,
},
.probe = wm8711_i2c_probe,
.id_table = wm8711_i2c_id,
};
#endif
static int __init wm8711_modinit(void)
{
int ret;
#if IS_ENABLED(CONFIG_I2C)
ret = i2c_add_driver(&wm8711_i2c_driver);
if (ret != 0) {
printk(KERN_ERR "Failed to register WM8711 I2C driver: %d\n",
ret);
}
#endif
#if defined(CONFIG_SPI_MASTER)
ret = spi_register_driver(&wm8711_spi_driver);
if (ret != 0) {
printk(KERN_ERR "Failed to register WM8711 SPI driver: %d\n",
ret);
}
#endif
return 0;
}
module_init(wm8711_modinit);
static void __exit wm8711_exit(void)
{
#if IS_ENABLED(CONFIG_I2C)
i2c_del_driver(&wm8711_i2c_driver);
#endif
#if defined(CONFIG_SPI_MASTER)
spi_unregister_driver(&wm8711_spi_driver);
#endif
}
module_exit(wm8711_exit);
MODULE_DESCRIPTION("ASoC WM8711 driver");
MODULE_AUTHOR("Mike Arthur");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8711.c |
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright 2011-2019 NW Digital Radio
*
* Author: Annaliese McDermond <[email protected]>
*
* Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27.
*
*/
#include <linux/spi/spi.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include "tlv320aic32x4.h"
static const struct of_device_id aic32x4_of_id[];
static int aic32x4_spi_probe(struct spi_device *spi)
{
struct regmap *regmap;
struct regmap_config config;
config = aic32x4_regmap_config;
config.reg_bits = 7;
config.pad_bits = 1;
config.val_bits = 8;
config.read_flag_mask = 0x01;
regmap = devm_regmap_init_spi(spi, &config);
if (spi->dev.of_node) {
const struct of_device_id *oid;
oid = of_match_node(aic32x4_of_id, spi->dev.of_node);
dev_set_drvdata(&spi->dev, (void *)oid->data);
} else {
const struct spi_device_id *id_entry;
id_entry = spi_get_device_id(spi);
dev_set_drvdata(&spi->dev, (void *)id_entry->driver_data);
}
return aic32x4_probe(&spi->dev, regmap);
}
static void aic32x4_spi_remove(struct spi_device *spi)
{
aic32x4_remove(&spi->dev);
}
static const struct spi_device_id aic32x4_spi_id[] = {
{ "tlv320aic32x4", (kernel_ulong_t)AIC32X4_TYPE_AIC32X4 },
{ "tlv320aic32x6", (kernel_ulong_t)AIC32X4_TYPE_AIC32X6 },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(spi, aic32x4_spi_id);
static const struct of_device_id aic32x4_of_id[] = {
{ .compatible = "ti,tlv320aic32x4", .data = (void *)AIC32X4_TYPE_AIC32X4 },
{ .compatible = "ti,tlv320aic32x6", .data = (void *)AIC32X4_TYPE_AIC32X6 },
{ /* senitel */ }
};
MODULE_DEVICE_TABLE(of, aic32x4_of_id);
static struct spi_driver aic32x4_spi_driver = {
.driver = {
.name = "tlv320aic32x4",
.owner = THIS_MODULE,
.of_match_table = aic32x4_of_id,
},
.probe = aic32x4_spi_probe,
.remove = aic32x4_spi_remove,
.id_table = aic32x4_spi_id,
};
module_spi_driver(aic32x4_spi_driver);
MODULE_DESCRIPTION("ASoC TLV320AIC32x4 codec driver SPI");
MODULE_AUTHOR("Annaliese McDermond <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/tlv320aic32x4-spi.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// rt5682.c -- RT5682 ALSA SoC audio component driver
//
// Copyright 2018 Realtek Semiconductor Corp.
// Author: Bard Liao <[email protected]>
//
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/acpi.h>
#include <linux/gpio/consumer.h>
#include <linux/mutex.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/jack.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/rt5682.h>
#include "rl6231.h"
#include "rt5682.h"
static const struct rt5682_platform_data i2s_default_platform_data = {
.dmic1_data_pin = RT5682_DMIC1_DATA_GPIO2,
.dmic1_clk_pin = RT5682_DMIC1_CLK_GPIO3,
.jd_src = RT5682_JD1,
.btndet_delay = 16,
.dai_clk_names[RT5682_DAI_WCLK_IDX] = "rt5682-dai-wclk",
.dai_clk_names[RT5682_DAI_BCLK_IDX] = "rt5682-dai-bclk",
};
static const struct regmap_config rt5682_regmap = {
.reg_bits = 16,
.val_bits = 16,
.max_register = RT5682_I2C_MODE,
.volatile_reg = rt5682_volatile_register,
.readable_reg = rt5682_readable_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = rt5682_reg,
.num_reg_defaults = RT5682_REG_NUM,
.use_single_read = true,
.use_single_write = true,
};
static void rt5682_jd_check_handler(struct work_struct *work)
{
struct rt5682_priv *rt5682 = container_of(work, struct rt5682_priv,
jd_check_work.work);
if (snd_soc_component_read(rt5682->component, RT5682_AJD1_CTRL) & RT5682_JDH_RS_MASK)
/* jack out */
mod_delayed_work(system_power_efficient_wq,
&rt5682->jack_detect_work, 0);
else
schedule_delayed_work(&rt5682->jd_check_work, 500);
}
static irqreturn_t rt5682_irq(int irq, void *data)
{
struct rt5682_priv *rt5682 = data;
mod_delayed_work(system_power_efficient_wq,
&rt5682->jack_detect_work, msecs_to_jiffies(rt5682->irq_work_delay_time));
return IRQ_HANDLED;
}
static struct snd_soc_dai_driver rt5682_dai[] = {
{
.name = "rt5682-aif1",
.id = RT5682_AIF1,
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT5682_STEREO_RATES,
.formats = RT5682_FORMATS,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT5682_STEREO_RATES,
.formats = RT5682_FORMATS,
},
.ops = &rt5682_aif1_dai_ops,
},
{
.name = "rt5682-aif2",
.id = RT5682_AIF2,
.capture = {
.stream_name = "AIF2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT5682_STEREO_RATES,
.formats = RT5682_FORMATS,
},
.ops = &rt5682_aif2_dai_ops,
},
};
static void rt5682_i2c_disable_regulators(void *data)
{
struct rt5682_priv *rt5682 = data;
regulator_bulk_disable(ARRAY_SIZE(rt5682->supplies), rt5682->supplies);
}
static int rt5682_i2c_probe(struct i2c_client *i2c)
{
struct rt5682_platform_data *pdata = dev_get_platdata(&i2c->dev);
struct rt5682_priv *rt5682;
int i, ret;
unsigned int val;
rt5682 = devm_kzalloc(&i2c->dev, sizeof(struct rt5682_priv),
GFP_KERNEL);
if (!rt5682)
return -ENOMEM;
i2c_set_clientdata(i2c, rt5682);
rt5682->i2c_dev = &i2c->dev;
rt5682->pdata = i2s_default_platform_data;
if (pdata)
rt5682->pdata = *pdata;
else
rt5682_parse_dt(rt5682, &i2c->dev);
rt5682->regmap = devm_regmap_init_i2c(i2c, &rt5682_regmap);
if (IS_ERR(rt5682->regmap)) {
ret = PTR_ERR(rt5682->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
for (i = 0; i < ARRAY_SIZE(rt5682->supplies); i++)
rt5682->supplies[i].supply = rt5682_supply_names[i];
ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5682->supplies),
rt5682->supplies);
if (ret) {
dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
return ret;
}
ret = devm_add_action_or_reset(&i2c->dev, rt5682_i2c_disable_regulators,
rt5682);
if (ret)
return ret;
ret = regulator_bulk_enable(ARRAY_SIZE(rt5682->supplies),
rt5682->supplies);
if (ret) {
dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
return ret;
}
ret = rt5682_get_ldo1(rt5682, &i2c->dev);
if (ret)
return ret;
/* Sleep for 300 ms miniumum */
usleep_range(300000, 350000);
regmap_write(rt5682->regmap, RT5682_I2C_MODE, 0x1);
usleep_range(10000, 15000);
regmap_read(rt5682->regmap, RT5682_DEVICE_ID, &val);
if (val != DEVICE_ID) {
dev_err(&i2c->dev,
"Device with ID register %x is not rt5682\n", val);
return -ENODEV;
}
mutex_init(&rt5682->calibrate_mutex);
rt5682_calibrate(rt5682);
rt5682_apply_patch_list(rt5682, &i2c->dev);
regmap_write(rt5682->regmap, RT5682_DEPOP_1, 0x0000);
/* DMIC pin*/
if (rt5682->pdata.dmic1_data_pin != RT5682_DMIC1_NULL) {
switch (rt5682->pdata.dmic1_data_pin) {
case RT5682_DMIC1_DATA_GPIO2: /* share with LRCK2 */
regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1,
RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO2);
regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
RT5682_GP2_PIN_MASK, RT5682_GP2_PIN_DMIC_SDA);
break;
case RT5682_DMIC1_DATA_GPIO5: /* share with DACDAT1 */
regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1,
RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO5);
regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
RT5682_GP5_PIN_MASK, RT5682_GP5_PIN_DMIC_SDA);
break;
default:
dev_warn(&i2c->dev, "invalid DMIC_DAT pin\n");
break;
}
switch (rt5682->pdata.dmic1_clk_pin) {
case RT5682_DMIC1_CLK_GPIO1: /* share with IRQ */
regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_DMIC_CLK);
break;
case RT5682_DMIC1_CLK_GPIO3: /* share with BCLK2 */
regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
RT5682_GP3_PIN_MASK, RT5682_GP3_PIN_DMIC_CLK);
if (rt5682->pdata.dmic_clk_driving_high)
regmap_update_bits(rt5682->regmap,
RT5682_PAD_DRIVING_CTRL,
RT5682_PAD_DRV_GP3_MASK,
2 << RT5682_PAD_DRV_GP3_SFT);
break;
default:
dev_warn(&i2c->dev, "invalid DMIC_CLK pin\n");
break;
}
}
regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
RT5682_LDO1_DVO_MASK | RT5682_HP_DRIVER_MASK,
RT5682_LDO1_DVO_12 | RT5682_HP_DRIVER_5X);
regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080);
regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
RT5682_GP4_PIN_MASK | RT5682_GP5_PIN_MASK,
RT5682_GP4_PIN_ADCDAT1 | RT5682_GP5_PIN_DACDAT1);
regmap_write(rt5682->regmap, RT5682_TEST_MODE_CTRL_1, 0x0000);
regmap_update_bits(rt5682->regmap, RT5682_BIAS_CUR_CTRL_8,
RT5682_HPA_CP_BIAS_CTRL_MASK, RT5682_HPA_CP_BIAS_3UA);
regmap_update_bits(rt5682->regmap, RT5682_CHARGE_PUMP_1,
RT5682_CP_CLK_HP_MASK, RT5682_CP_CLK_HP_300KHZ);
regmap_update_bits(rt5682->regmap, RT5682_HP_CHARGE_PUMP_1,
RT5682_PM_HP_MASK, RT5682_PM_HP_HV);
regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1,
RT5682_FIFO_CLK_DIV_MASK, RT5682_FIFO_CLK_DIV_2);
INIT_DELAYED_WORK(&rt5682->jack_detect_work,
rt5682_jack_detect_handler);
INIT_DELAYED_WORK(&rt5682->jd_check_work,
rt5682_jd_check_handler);
if (i2c->irq) {
ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
rt5682_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
| IRQF_ONESHOT, "rt5682", rt5682);
if (!ret)
rt5682->irq = i2c->irq;
else
dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
}
#ifdef CONFIG_COMMON_CLK
/* Check if MCLK provided */
rt5682->mclk = devm_clk_get_optional(&i2c->dev, "mclk");
if (IS_ERR(rt5682->mclk))
return PTR_ERR(rt5682->mclk);
/* Register CCF DAI clock control */
ret = rt5682_register_dai_clks(rt5682);
if (ret)
return ret;
/* Initial setup for CCF */
rt5682->lrck[RT5682_AIF1] = 48000;
#endif
return devm_snd_soc_register_component(&i2c->dev,
&rt5682_soc_component_dev,
rt5682_dai, ARRAY_SIZE(rt5682_dai));
}
static void rt5682_i2c_shutdown(struct i2c_client *client)
{
struct rt5682_priv *rt5682 = i2c_get_clientdata(client);
disable_irq(client->irq);
cancel_delayed_work_sync(&rt5682->jack_detect_work);
cancel_delayed_work_sync(&rt5682->jd_check_work);
rt5682_reset(rt5682);
}
static void rt5682_i2c_remove(struct i2c_client *client)
{
rt5682_i2c_shutdown(client);
}
static const struct of_device_id rt5682_of_match[] = {
{.compatible = "realtek,rt5682i"},
{},
};
MODULE_DEVICE_TABLE(of, rt5682_of_match);
static const struct acpi_device_id rt5682_acpi_match[] = {
{"10EC5682", 0,},
{},
};
MODULE_DEVICE_TABLE(acpi, rt5682_acpi_match);
static const struct i2c_device_id rt5682_i2c_id[] = {
{"rt5682", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, rt5682_i2c_id);
static struct i2c_driver rt5682_i2c_driver = {
.driver = {
.name = "rt5682",
.of_match_table = rt5682_of_match,
.acpi_match_table = rt5682_acpi_match,
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
},
.probe = rt5682_i2c_probe,
.remove = rt5682_i2c_remove,
.shutdown = rt5682_i2c_shutdown,
.id_table = rt5682_i2c_id,
};
module_i2c_driver(rt5682_i2c_driver);
MODULE_DESCRIPTION("ASoC RT5682 driver");
MODULE_AUTHOR("Bard Liao <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/rt5682-i2c.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* SSM2518 amplifier audio driver
*
* Copyright 2013 Analog Devices Inc.
* Author: Lars-Peter Clausen <[email protected]>
*/
#include <linux/err.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/gpio/consumer.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "ssm2518.h"
#define SSM2518_REG_POWER1 0x00
#define SSM2518_REG_CLOCK 0x01
#define SSM2518_REG_SAI_CTRL1 0x02
#define SSM2518_REG_SAI_CTRL2 0x03
#define SSM2518_REG_CHAN_MAP 0x04
#define SSM2518_REG_LEFT_VOL 0x05
#define SSM2518_REG_RIGHT_VOL 0x06
#define SSM2518_REG_MUTE_CTRL 0x07
#define SSM2518_REG_FAULT_CTRL 0x08
#define SSM2518_REG_POWER2 0x09
#define SSM2518_REG_DRC_1 0x0a
#define SSM2518_REG_DRC_2 0x0b
#define SSM2518_REG_DRC_3 0x0c
#define SSM2518_REG_DRC_4 0x0d
#define SSM2518_REG_DRC_5 0x0e
#define SSM2518_REG_DRC_6 0x0f
#define SSM2518_REG_DRC_7 0x10
#define SSM2518_REG_DRC_8 0x11
#define SSM2518_REG_DRC_9 0x12
#define SSM2518_POWER1_RESET BIT(7)
#define SSM2518_POWER1_NO_BCLK BIT(5)
#define SSM2518_POWER1_MCS_MASK (0xf << 1)
#define SSM2518_POWER1_MCS_64FS (0x0 << 1)
#define SSM2518_POWER1_MCS_128FS (0x1 << 1)
#define SSM2518_POWER1_MCS_256FS (0x2 << 1)
#define SSM2518_POWER1_MCS_384FS (0x3 << 1)
#define SSM2518_POWER1_MCS_512FS (0x4 << 1)
#define SSM2518_POWER1_MCS_768FS (0x5 << 1)
#define SSM2518_POWER1_MCS_100FS (0x6 << 1)
#define SSM2518_POWER1_MCS_200FS (0x7 << 1)
#define SSM2518_POWER1_MCS_400FS (0x8 << 1)
#define SSM2518_POWER1_SPWDN BIT(0)
#define SSM2518_CLOCK_ASR BIT(0)
#define SSM2518_SAI_CTRL1_FMT_MASK (0x3 << 5)
#define SSM2518_SAI_CTRL1_FMT_I2S (0x0 << 5)
#define SSM2518_SAI_CTRL1_FMT_LJ (0x1 << 5)
#define SSM2518_SAI_CTRL1_FMT_RJ_24BIT (0x2 << 5)
#define SSM2518_SAI_CTRL1_FMT_RJ_16BIT (0x3 << 5)
#define SSM2518_SAI_CTRL1_SAI_MASK (0x7 << 2)
#define SSM2518_SAI_CTRL1_SAI_I2S (0x0 << 2)
#define SSM2518_SAI_CTRL1_SAI_TDM_2 (0x1 << 2)
#define SSM2518_SAI_CTRL1_SAI_TDM_4 (0x2 << 2)
#define SSM2518_SAI_CTRL1_SAI_TDM_8 (0x3 << 2)
#define SSM2518_SAI_CTRL1_SAI_TDM_16 (0x4 << 2)
#define SSM2518_SAI_CTRL1_SAI_MONO (0x5 << 2)
#define SSM2518_SAI_CTRL1_FS_MASK (0x3)
#define SSM2518_SAI_CTRL1_FS_8000_12000 (0x0)
#define SSM2518_SAI_CTRL1_FS_16000_24000 (0x1)
#define SSM2518_SAI_CTRL1_FS_32000_48000 (0x2)
#define SSM2518_SAI_CTRL1_FS_64000_96000 (0x3)
#define SSM2518_SAI_CTRL2_BCLK_INTERAL BIT(7)
#define SSM2518_SAI_CTRL2_LRCLK_PULSE BIT(6)
#define SSM2518_SAI_CTRL2_LRCLK_INVERT BIT(5)
#define SSM2518_SAI_CTRL2_MSB BIT(4)
#define SSM2518_SAI_CTRL2_SLOT_WIDTH_MASK (0x3 << 2)
#define SSM2518_SAI_CTRL2_SLOT_WIDTH_32 (0x0 << 2)
#define SSM2518_SAI_CTRL2_SLOT_WIDTH_24 (0x1 << 2)
#define SSM2518_SAI_CTRL2_SLOT_WIDTH_16 (0x2 << 2)
#define SSM2518_SAI_CTRL2_BCLK_INVERT BIT(1)
#define SSM2518_CHAN_MAP_RIGHT_SLOT_OFFSET 4
#define SSM2518_CHAN_MAP_RIGHT_SLOT_MASK 0xf0
#define SSM2518_CHAN_MAP_LEFT_SLOT_OFFSET 0
#define SSM2518_CHAN_MAP_LEFT_SLOT_MASK 0x0f
#define SSM2518_MUTE_CTRL_ANA_GAIN BIT(5)
#define SSM2518_MUTE_CTRL_MUTE_MASTER BIT(0)
#define SSM2518_POWER2_APWDN BIT(0)
#define SSM2518_DAC_MUTE BIT(6)
#define SSM2518_DAC_FS_MASK 0x07
#define SSM2518_DAC_FS_8000 0x00
#define SSM2518_DAC_FS_16000 0x01
#define SSM2518_DAC_FS_32000 0x02
#define SSM2518_DAC_FS_64000 0x03
#define SSM2518_DAC_FS_128000 0x04
struct ssm2518 {
struct regmap *regmap;
bool right_j;
unsigned int sysclk;
const struct snd_pcm_hw_constraint_list *constraints;
struct gpio_desc *enable_gpio;
};
static const struct reg_default ssm2518_reg_defaults[] = {
{ 0x00, 0x05 },
{ 0x01, 0x00 },
{ 0x02, 0x02 },
{ 0x03, 0x00 },
{ 0x04, 0x10 },
{ 0x05, 0x40 },
{ 0x06, 0x40 },
{ 0x07, 0x81 },
{ 0x08, 0x0c },
{ 0x09, 0x99 },
{ 0x0a, 0x7c },
{ 0x0b, 0x5b },
{ 0x0c, 0x57 },
{ 0x0d, 0x89 },
{ 0x0e, 0x8c },
{ 0x0f, 0x77 },
{ 0x10, 0x26 },
{ 0x11, 0x1c },
{ 0x12, 0x97 },
};
static const DECLARE_TLV_DB_MINMAX_MUTE(ssm2518_vol_tlv, -7125, 2400);
static const DECLARE_TLV_DB_SCALE(ssm2518_compressor_tlv, -3400, 200, 0);
static const DECLARE_TLV_DB_SCALE(ssm2518_expander_tlv, -8100, 300, 0);
static const DECLARE_TLV_DB_SCALE(ssm2518_noise_gate_tlv, -9600, 300, 0);
static const DECLARE_TLV_DB_SCALE(ssm2518_post_drc_tlv, -2400, 300, 0);
static const DECLARE_TLV_DB_RANGE(ssm2518_limiter_tlv,
0, 7, TLV_DB_SCALE_ITEM(-2200, 200, 0),
7, 15, TLV_DB_SCALE_ITEM(-800, 100, 0),
);
static const char * const ssm2518_drc_peak_detector_attack_time_text[] = {
"0 ms", "0.1 ms", "0.19 ms", "0.37 ms", "0.75 ms", "1.5 ms", "3 ms",
"6 ms", "12 ms", "24 ms", "48 ms", "96 ms", "192 ms", "384 ms",
"768 ms", "1536 ms",
};
static const char * const ssm2518_drc_peak_detector_release_time_text[] = {
"0 ms", "1.5 ms", "3 ms", "6 ms", "12 ms", "24 ms", "48 ms", "96 ms",
"192 ms", "384 ms", "768 ms", "1536 ms", "3072 ms", "6144 ms",
"12288 ms", "24576 ms"
};
static const char * const ssm2518_drc_hold_time_text[] = {
"0 ms", "0.67 ms", "1.33 ms", "2.67 ms", "5.33 ms", "10.66 ms",
"21.32 ms", "42.64 ms", "85.28 ms", "170.56 ms", "341.12 ms",
"682.24 ms", "1364 ms",
};
static SOC_ENUM_SINGLE_DECL(ssm2518_drc_peak_detector_attack_time_enum,
SSM2518_REG_DRC_2, 4, ssm2518_drc_peak_detector_attack_time_text);
static SOC_ENUM_SINGLE_DECL(ssm2518_drc_peak_detector_release_time_enum,
SSM2518_REG_DRC_2, 0, ssm2518_drc_peak_detector_release_time_text);
static SOC_ENUM_SINGLE_DECL(ssm2518_drc_attack_time_enum,
SSM2518_REG_DRC_6, 4, ssm2518_drc_peak_detector_attack_time_text);
static SOC_ENUM_SINGLE_DECL(ssm2518_drc_decay_time_enum,
SSM2518_REG_DRC_6, 0, ssm2518_drc_peak_detector_release_time_text);
static SOC_ENUM_SINGLE_DECL(ssm2518_drc_hold_time_enum,
SSM2518_REG_DRC_7, 4, ssm2518_drc_hold_time_text);
static SOC_ENUM_SINGLE_DECL(ssm2518_drc_noise_gate_hold_time_enum,
SSM2518_REG_DRC_7, 0, ssm2518_drc_hold_time_text);
static SOC_ENUM_SINGLE_DECL(ssm2518_drc_rms_averaging_time_enum,
SSM2518_REG_DRC_9, 0, ssm2518_drc_peak_detector_release_time_text);
static const struct snd_kcontrol_new ssm2518_snd_controls[] = {
SOC_SINGLE("Playback De-emphasis Switch", SSM2518_REG_MUTE_CTRL,
4, 1, 0),
SOC_DOUBLE_R_TLV("Master Playback Volume", SSM2518_REG_LEFT_VOL,
SSM2518_REG_RIGHT_VOL, 0, 0xff, 1, ssm2518_vol_tlv),
SOC_DOUBLE("Master Playback Switch", SSM2518_REG_MUTE_CTRL, 2, 1, 1, 1),
SOC_SINGLE("Amp Low Power Mode Switch", SSM2518_REG_POWER2, 4, 1, 0),
SOC_SINGLE("DAC Low Power Mode Switch", SSM2518_REG_POWER2, 3, 1, 0),
SOC_SINGLE("DRC Limiter Switch", SSM2518_REG_DRC_1, 5, 1, 0),
SOC_SINGLE("DRC Compressor Switch", SSM2518_REG_DRC_1, 4, 1, 0),
SOC_SINGLE("DRC Expander Switch", SSM2518_REG_DRC_1, 3, 1, 0),
SOC_SINGLE("DRC Noise Gate Switch", SSM2518_REG_DRC_1, 2, 1, 0),
SOC_DOUBLE("DRC Switch", SSM2518_REG_DRC_1, 0, 1, 1, 0),
SOC_SINGLE_TLV("DRC Limiter Threshold Volume",
SSM2518_REG_DRC_3, 4, 15, 1, ssm2518_limiter_tlv),
SOC_SINGLE_TLV("DRC Compressor Lower Threshold Volume",
SSM2518_REG_DRC_3, 0, 15, 1, ssm2518_compressor_tlv),
SOC_SINGLE_TLV("DRC Expander Upper Threshold Volume", SSM2518_REG_DRC_4,
4, 15, 1, ssm2518_expander_tlv),
SOC_SINGLE_TLV("DRC Noise Gate Threshold Volume",
SSM2518_REG_DRC_4, 0, 15, 1, ssm2518_noise_gate_tlv),
SOC_SINGLE_TLV("DRC Upper Output Threshold Volume",
SSM2518_REG_DRC_5, 4, 15, 1, ssm2518_limiter_tlv),
SOC_SINGLE_TLV("DRC Lower Output Threshold Volume",
SSM2518_REG_DRC_5, 0, 15, 1, ssm2518_noise_gate_tlv),
SOC_SINGLE_TLV("DRC Post Volume", SSM2518_REG_DRC_8,
2, 15, 1, ssm2518_post_drc_tlv),
SOC_ENUM("DRC Peak Detector Attack Time",
ssm2518_drc_peak_detector_attack_time_enum),
SOC_ENUM("DRC Peak Detector Release Time",
ssm2518_drc_peak_detector_release_time_enum),
SOC_ENUM("DRC Attack Time", ssm2518_drc_attack_time_enum),
SOC_ENUM("DRC Decay Time", ssm2518_drc_decay_time_enum),
SOC_ENUM("DRC Hold Time", ssm2518_drc_hold_time_enum),
SOC_ENUM("DRC Noise Gate Hold Time",
ssm2518_drc_noise_gate_hold_time_enum),
SOC_ENUM("DRC RMS Averaging Time", ssm2518_drc_rms_averaging_time_enum),
};
static const struct snd_soc_dapm_widget ssm2518_dapm_widgets[] = {
SND_SOC_DAPM_DAC("DACL", "HiFi Playback", SSM2518_REG_POWER2, 1, 1),
SND_SOC_DAPM_DAC("DACR", "HiFi Playback", SSM2518_REG_POWER2, 2, 1),
SND_SOC_DAPM_OUTPUT("OUTL"),
SND_SOC_DAPM_OUTPUT("OUTR"),
};
static const struct snd_soc_dapm_route ssm2518_routes[] = {
{ "OUTL", NULL, "DACL" },
{ "OUTR", NULL, "DACR" },
};
struct ssm2518_mcs_lut {
unsigned int rate;
const unsigned int *sysclks;
};
static const unsigned int ssm2518_sysclks_2048000[] = {
2048000, 4096000, 8192000, 12288000, 16384000, 24576000,
3200000, 6400000, 12800000, 0
};
static const unsigned int ssm2518_sysclks_2822000[] = {
2822000, 5644800, 11289600, 16934400, 22579200, 33868800,
4410000, 8820000, 17640000, 0
};
static const unsigned int ssm2518_sysclks_3072000[] = {
3072000, 6144000, 12288000, 16384000, 24576000, 38864000,
4800000, 9600000, 19200000, 0
};
static const struct ssm2518_mcs_lut ssm2518_mcs_lut[] = {
{ 8000, ssm2518_sysclks_2048000, },
{ 11025, ssm2518_sysclks_2822000, },
{ 12000, ssm2518_sysclks_3072000, },
{ 16000, ssm2518_sysclks_2048000, },
{ 24000, ssm2518_sysclks_3072000, },
{ 22050, ssm2518_sysclks_2822000, },
{ 32000, ssm2518_sysclks_2048000, },
{ 44100, ssm2518_sysclks_2822000, },
{ 48000, ssm2518_sysclks_3072000, },
{ 96000, ssm2518_sysclks_3072000, },
};
static const unsigned int ssm2518_rates_2048000[] = {
8000, 16000, 32000,
};
static const struct snd_pcm_hw_constraint_list ssm2518_constraints_2048000 = {
.list = ssm2518_rates_2048000,
.count = ARRAY_SIZE(ssm2518_rates_2048000),
};
static const unsigned int ssm2518_rates_2822000[] = {
11025, 22050, 44100,
};
static const struct snd_pcm_hw_constraint_list ssm2518_constraints_2822000 = {
.list = ssm2518_rates_2822000,
.count = ARRAY_SIZE(ssm2518_rates_2822000),
};
static const unsigned int ssm2518_rates_3072000[] = {
12000, 24000, 48000, 96000,
};
static const struct snd_pcm_hw_constraint_list ssm2518_constraints_3072000 = {
.list = ssm2518_rates_3072000,
.count = ARRAY_SIZE(ssm2518_rates_3072000),
};
static const unsigned int ssm2518_rates_12288000[] = {
8000, 12000, 16000, 24000, 32000, 48000, 96000,
};
static const struct snd_pcm_hw_constraint_list ssm2518_constraints_12288000 = {
.list = ssm2518_rates_12288000,
.count = ARRAY_SIZE(ssm2518_rates_12288000),
};
static int ssm2518_lookup_mcs(struct ssm2518 *ssm2518,
unsigned int rate)
{
const unsigned int *sysclks = NULL;
int i;
for (i = 0; i < ARRAY_SIZE(ssm2518_mcs_lut); i++) {
if (ssm2518_mcs_lut[i].rate == rate) {
sysclks = ssm2518_mcs_lut[i].sysclks;
break;
}
}
if (!sysclks)
return -EINVAL;
for (i = 0; sysclks[i]; i++) {
if (sysclks[i] == ssm2518->sysclk)
return i;
}
return -EINVAL;
}
static int ssm2518_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct ssm2518 *ssm2518 = snd_soc_component_get_drvdata(component);
unsigned int rate = params_rate(params);
unsigned int ctrl1, ctrl1_mask;
int mcs;
int ret;
mcs = ssm2518_lookup_mcs(ssm2518, rate);
if (mcs < 0)
return mcs;
ctrl1_mask = SSM2518_SAI_CTRL1_FS_MASK;
if (rate >= 8000 && rate <= 12000)
ctrl1 = SSM2518_SAI_CTRL1_FS_8000_12000;
else if (rate >= 16000 && rate <= 24000)
ctrl1 = SSM2518_SAI_CTRL1_FS_16000_24000;
else if (rate >= 32000 && rate <= 48000)
ctrl1 = SSM2518_SAI_CTRL1_FS_32000_48000;
else if (rate >= 64000 && rate <= 96000)
ctrl1 = SSM2518_SAI_CTRL1_FS_64000_96000;
else
return -EINVAL;
if (ssm2518->right_j) {
switch (params_width(params)) {
case 16:
ctrl1 |= SSM2518_SAI_CTRL1_FMT_RJ_16BIT;
break;
case 24:
ctrl1 |= SSM2518_SAI_CTRL1_FMT_RJ_24BIT;
break;
default:
return -EINVAL;
}
ctrl1_mask |= SSM2518_SAI_CTRL1_FMT_MASK;
}
/* Disable auto samplerate detection */
ret = regmap_update_bits(ssm2518->regmap, SSM2518_REG_CLOCK,
SSM2518_CLOCK_ASR, SSM2518_CLOCK_ASR);
if (ret < 0)
return ret;
ret = regmap_update_bits(ssm2518->regmap, SSM2518_REG_SAI_CTRL1,
ctrl1_mask, ctrl1);
if (ret < 0)
return ret;
return regmap_update_bits(ssm2518->regmap, SSM2518_REG_POWER1,
SSM2518_POWER1_MCS_MASK, mcs << 1);
}
static int ssm2518_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct ssm2518 *ssm2518 = snd_soc_component_get_drvdata(dai->component);
unsigned int val;
if (mute)
val = SSM2518_MUTE_CTRL_MUTE_MASTER;
else
val = 0;
return regmap_update_bits(ssm2518->regmap, SSM2518_REG_MUTE_CTRL,
SSM2518_MUTE_CTRL_MUTE_MASTER, val);
}
static int ssm2518_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct ssm2518 *ssm2518 = snd_soc_component_get_drvdata(dai->component);
unsigned int ctrl1 = 0, ctrl2 = 0;
bool invert_fclk;
int ret;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
invert_fclk = false;
break;
case SND_SOC_DAIFMT_IB_NF:
ctrl2 |= SSM2518_SAI_CTRL2_BCLK_INVERT;
invert_fclk = false;
break;
case SND_SOC_DAIFMT_NB_IF:
invert_fclk = true;
break;
case SND_SOC_DAIFMT_IB_IF:
ctrl2 |= SSM2518_SAI_CTRL2_BCLK_INVERT;
invert_fclk = true;
break;
default:
return -EINVAL;
}
ssm2518->right_j = false;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
ctrl1 |= SSM2518_SAI_CTRL1_FMT_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
ctrl1 |= SSM2518_SAI_CTRL1_FMT_LJ;
invert_fclk = !invert_fclk;
break;
case SND_SOC_DAIFMT_RIGHT_J:
ctrl1 |= SSM2518_SAI_CTRL1_FMT_RJ_24BIT;
ssm2518->right_j = true;
invert_fclk = !invert_fclk;
break;
case SND_SOC_DAIFMT_DSP_A:
ctrl2 |= SSM2518_SAI_CTRL2_LRCLK_PULSE;
ctrl1 |= SSM2518_SAI_CTRL1_FMT_I2S;
invert_fclk = false;
break;
case SND_SOC_DAIFMT_DSP_B:
ctrl2 |= SSM2518_SAI_CTRL2_LRCLK_PULSE;
ctrl1 |= SSM2518_SAI_CTRL1_FMT_LJ;
invert_fclk = false;
break;
default:
return -EINVAL;
}
if (invert_fclk)
ctrl2 |= SSM2518_SAI_CTRL2_LRCLK_INVERT;
ret = regmap_write(ssm2518->regmap, SSM2518_REG_SAI_CTRL1, ctrl1);
if (ret)
return ret;
return regmap_write(ssm2518->regmap, SSM2518_REG_SAI_CTRL2, ctrl2);
}
static int ssm2518_set_power(struct ssm2518 *ssm2518, bool enable)
{
int ret = 0;
if (!enable) {
ret = regmap_update_bits(ssm2518->regmap, SSM2518_REG_POWER1,
SSM2518_POWER1_SPWDN, SSM2518_POWER1_SPWDN);
regcache_mark_dirty(ssm2518->regmap);
}
if (ssm2518->enable_gpio)
gpiod_set_value_cansleep(ssm2518->enable_gpio, enable);
regcache_cache_only(ssm2518->regmap, !enable);
if (enable) {
ret = regmap_update_bits(ssm2518->regmap, SSM2518_REG_POWER1,
SSM2518_POWER1_SPWDN | SSM2518_POWER1_RESET, 0x00);
regcache_sync(ssm2518->regmap);
}
return ret;
}
static int ssm2518_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct ssm2518 *ssm2518 = snd_soc_component_get_drvdata(component);
int ret = 0;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
ret = ssm2518_set_power(ssm2518, true);
break;
case SND_SOC_BIAS_OFF:
ret = ssm2518_set_power(ssm2518, false);
break;
}
return ret;
}
static int ssm2518_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int width)
{
struct ssm2518 *ssm2518 = snd_soc_component_get_drvdata(dai->component);
unsigned int ctrl1, ctrl2;
int left_slot, right_slot;
int ret;
if (slots == 0)
return regmap_update_bits(ssm2518->regmap,
SSM2518_REG_SAI_CTRL1, SSM2518_SAI_CTRL1_SAI_MASK,
SSM2518_SAI_CTRL1_SAI_I2S);
if (tx_mask == 0 || rx_mask != 0)
return -EINVAL;
if (slots == 1) {
if (tx_mask != 1)
return -EINVAL;
left_slot = 0;
right_slot = 0;
} else {
/* We assume the left channel < right channel */
left_slot = __ffs(tx_mask);
tx_mask &= ~(1 << left_slot);
if (tx_mask == 0) {
right_slot = left_slot;
} else {
right_slot = __ffs(tx_mask);
tx_mask &= ~(1 << right_slot);
}
}
if (tx_mask != 0 || left_slot >= slots || right_slot >= slots)
return -EINVAL;
switch (width) {
case 16:
ctrl2 = SSM2518_SAI_CTRL2_SLOT_WIDTH_16;
break;
case 24:
ctrl2 = SSM2518_SAI_CTRL2_SLOT_WIDTH_24;
break;
case 32:
ctrl2 = SSM2518_SAI_CTRL2_SLOT_WIDTH_32;
break;
default:
return -EINVAL;
}
switch (slots) {
case 1:
ctrl1 = SSM2518_SAI_CTRL1_SAI_MONO;
break;
case 2:
ctrl1 = SSM2518_SAI_CTRL1_SAI_TDM_2;
break;
case 4:
ctrl1 = SSM2518_SAI_CTRL1_SAI_TDM_4;
break;
case 8:
ctrl1 = SSM2518_SAI_CTRL1_SAI_TDM_8;
break;
case 16:
ctrl1 = SSM2518_SAI_CTRL1_SAI_TDM_16;
break;
default:
return -EINVAL;
}
ret = regmap_write(ssm2518->regmap, SSM2518_REG_CHAN_MAP,
(left_slot << SSM2518_CHAN_MAP_LEFT_SLOT_OFFSET) |
(right_slot << SSM2518_CHAN_MAP_RIGHT_SLOT_OFFSET));
if (ret)
return ret;
ret = regmap_update_bits(ssm2518->regmap, SSM2518_REG_SAI_CTRL1,
SSM2518_SAI_CTRL1_SAI_MASK, ctrl1);
if (ret)
return ret;
return regmap_update_bits(ssm2518->regmap, SSM2518_REG_SAI_CTRL2,
SSM2518_SAI_CTRL2_SLOT_WIDTH_MASK, ctrl2);
}
static int ssm2518_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct ssm2518 *ssm2518 = snd_soc_component_get_drvdata(dai->component);
if (ssm2518->constraints)
snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE, ssm2518->constraints);
return 0;
}
#define SSM2518_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32)
static const struct snd_soc_dai_ops ssm2518_dai_ops = {
.startup = ssm2518_startup,
.hw_params = ssm2518_hw_params,
.mute_stream = ssm2518_mute,
.set_fmt = ssm2518_set_dai_fmt,
.set_tdm_slot = ssm2518_set_tdm_slot,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver ssm2518_dai = {
.name = "ssm2518-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = SSM2518_FORMATS,
},
.ops = &ssm2518_dai_ops,
};
static int ssm2518_set_sysclk(struct snd_soc_component *component, int clk_id,
int source, unsigned int freq, int dir)
{
struct ssm2518 *ssm2518 = snd_soc_component_get_drvdata(component);
unsigned int val;
if (clk_id != SSM2518_SYSCLK)
return -EINVAL;
switch (source) {
case SSM2518_SYSCLK_SRC_MCLK:
val = 0;
break;
case SSM2518_SYSCLK_SRC_BCLK:
/* In this case the bitclock is used as the system clock, and
* the bitclock signal needs to be connected to the MCLK pin and
* the BCLK pin is left unconnected */
val = SSM2518_POWER1_NO_BCLK;
break;
default:
return -EINVAL;
}
switch (freq) {
case 0:
ssm2518->constraints = NULL;
break;
case 2048000:
case 4096000:
case 8192000:
case 3200000:
case 6400000:
case 12800000:
ssm2518->constraints = &ssm2518_constraints_2048000;
break;
case 2822000:
case 5644800:
case 11289600:
case 16934400:
case 22579200:
case 33868800:
case 4410000:
case 8820000:
case 17640000:
ssm2518->constraints = &ssm2518_constraints_2822000;
break;
case 3072000:
case 6144000:
case 38864000:
case 4800000:
case 9600000:
case 19200000:
ssm2518->constraints = &ssm2518_constraints_3072000;
break;
case 12288000:
case 16384000:
case 24576000:
ssm2518->constraints = &ssm2518_constraints_12288000;
break;
default:
return -EINVAL;
}
ssm2518->sysclk = freq;
return regmap_update_bits(ssm2518->regmap, SSM2518_REG_POWER1,
SSM2518_POWER1_NO_BCLK, val);
}
static const struct snd_soc_component_driver ssm2518_component_driver = {
.set_bias_level = ssm2518_set_bias_level,
.set_sysclk = ssm2518_set_sysclk,
.controls = ssm2518_snd_controls,
.num_controls = ARRAY_SIZE(ssm2518_snd_controls),
.dapm_widgets = ssm2518_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(ssm2518_dapm_widgets),
.dapm_routes = ssm2518_routes,
.num_dapm_routes = ARRAY_SIZE(ssm2518_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config ssm2518_regmap_config = {
.val_bits = 8,
.reg_bits = 8,
.max_register = SSM2518_REG_DRC_9,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = ssm2518_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(ssm2518_reg_defaults),
};
static int ssm2518_i2c_probe(struct i2c_client *i2c)
{
struct ssm2518 *ssm2518;
int ret;
ssm2518 = devm_kzalloc(&i2c->dev, sizeof(*ssm2518), GFP_KERNEL);
if (ssm2518 == NULL)
return -ENOMEM;
/* Start with enabling the chip */
ssm2518->enable_gpio = devm_gpiod_get_optional(&i2c->dev, NULL,
GPIOD_OUT_HIGH);
ret = PTR_ERR_OR_ZERO(ssm2518->enable_gpio);
if (ret)
return ret;
gpiod_set_consumer_name(ssm2518->enable_gpio, "SSM2518 nSD");
i2c_set_clientdata(i2c, ssm2518);
ssm2518->regmap = devm_regmap_init_i2c(i2c, &ssm2518_regmap_config);
if (IS_ERR(ssm2518->regmap))
return PTR_ERR(ssm2518->regmap);
/*
* The reset bit is obviously volatile, but we need to be able to cache
* the other bits in the register, so we can't just mark the whole
* register as volatile. Since this is the only place where we'll ever
* touch the reset bit just bypass the cache for this operation.
*/
regcache_cache_bypass(ssm2518->regmap, true);
ret = regmap_write(ssm2518->regmap, SSM2518_REG_POWER1,
SSM2518_POWER1_RESET);
regcache_cache_bypass(ssm2518->regmap, false);
if (ret)
return ret;
ret = regmap_update_bits(ssm2518->regmap, SSM2518_REG_POWER2,
SSM2518_POWER2_APWDN, 0x00);
if (ret)
return ret;
ret = ssm2518_set_power(ssm2518, false);
if (ret)
return ret;
return devm_snd_soc_register_component(&i2c->dev,
&ssm2518_component_driver,
&ssm2518_dai, 1);
}
#ifdef CONFIG_OF
static const struct of_device_id ssm2518_dt_ids[] = {
{ .compatible = "adi,ssm2518", },
{ }
};
MODULE_DEVICE_TABLE(of, ssm2518_dt_ids);
#endif
static const struct i2c_device_id ssm2518_i2c_ids[] = {
{ "ssm2518", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, ssm2518_i2c_ids);
static struct i2c_driver ssm2518_driver = {
.driver = {
.name = "ssm2518",
.of_match_table = of_match_ptr(ssm2518_dt_ids),
},
.probe = ssm2518_i2c_probe,
.id_table = ssm2518_i2c_ids,
};
module_i2c_driver(ssm2518_driver);
MODULE_DESCRIPTION("ASoC SSM2518 driver");
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/ssm2518.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2021, Maxim Integrated
#include <linux/acpi.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/cdev.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <sound/tlv.h>
#include "max98520.h"
static struct reg_default max98520_reg[] = {
{MAX98520_R2000_SW_RESET, 0x00},
{MAX98520_R2001_STATUS_1, 0x00},
{MAX98520_R2002_STATUS_2, 0x00},
{MAX98520_R2020_THERM_WARN_THRESH, 0x46},
{MAX98520_R2021_THERM_SHDN_THRESH, 0x64},
{MAX98520_R2022_THERM_HYSTERESIS, 0x02},
{MAX98520_R2023_THERM_FOLDBACK_SET, 0x31},
{MAX98520_R2027_THERM_FOLDBACK_EN, 0x01},
{MAX98520_R2030_CLK_MON_CTRL, 0x00},
{MAX98520_R2037_ERR_MON_CTRL, 0x01},
{MAX98520_R2040_PCM_MODE_CFG, 0xC0},
{MAX98520_R2041_PCM_CLK_SETUP, 0x04},
{MAX98520_R2042_PCM_SR_SETUP, 0x08},
{MAX98520_R2043_PCM_RX_SRC1, 0x00},
{MAX98520_R2044_PCM_RX_SRC2, 0x00},
{MAX98520_R204F_PCM_RX_EN, 0x00},
{MAX98520_R2090_AMP_VOL_CTRL, 0x00},
{MAX98520_R2091_AMP_PATH_GAIN, 0x03},
{MAX98520_R2092_AMP_DSP_CFG, 0x02},
{MAX98520_R2094_SSM_CFG, 0x01},
{MAX98520_R2095_AMP_CFG, 0xF0},
{MAX98520_R209F_AMP_EN, 0x00},
{MAX98520_R20B0_ADC_SR, 0x00},
{MAX98520_R20B1_ADC_RESOLUTION, 0x00},
{MAX98520_R20B2_ADC_PVDD0_CFG, 0x02},
{MAX98520_R20B3_ADC_THERMAL_CFG, 0x02},
{MAX98520_R20B4_ADC_READBACK_CTRL, 0x00},
{MAX98520_R20B5_ADC_READBACK_UPDATE, 0x00},
{MAX98520_R20B6_ADC_PVDD_READBACK_MSB, 0x00},
{MAX98520_R20B7_ADC_PVDD_READBACK_LSB, 0x00},
{MAX98520_R20B8_ADC_TEMP_READBACK_MSB, 0x00},
{MAX98520_R20B9_ADC_TEMP_READBACK_LSB, 0x00},
{MAX98520_R20BA_ADC_LOW_PVDD_READBACK_MSB, 0xFF},
{MAX98520_R20BB_ADC_LOW_READBACK_LSB, 0x01},
{MAX98520_R20BC_ADC_HIGH_TEMP_READBACK_MSB, 0x00},
{MAX98520_R20BD_ADC_HIGH_TEMP_READBACK_LSB, 0x00},
{MAX98520_R20CF_MEAS_ADC_CFG, 0x00},
{MAX98520_R20D0_DHT_CFG1, 0x00},
{MAX98520_R20D1_LIMITER_CFG1, 0x08},
{MAX98520_R20D2_LIMITER_CFG2, 0x00},
{MAX98520_R20D3_DHT_CFG2, 0x14},
{MAX98520_R20D4_DHT_CFG3, 0x02},
{MAX98520_R20D5_DHT_CFG4, 0x04},
{MAX98520_R20D6_DHT_HYSTERESIS_CFG, 0x07},
{MAX98520_R20D8_DHT_EN, 0x00},
{MAX98520_R210E_AUTO_RESTART_BEHAVIOR, 0x00},
{MAX98520_R210F_GLOBAL_EN, 0x00},
{MAX98520_R21FF_REVISION_ID, 0x00},
};
static int max98520_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct max98520_priv *max98520 =
snd_soc_component_get_drvdata(component);
unsigned int format = 0;
unsigned int invert = 0;
dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt);
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
invert = MAX98520_PCM_MODE_CFG_PCM_BCLKEDGE;
break;
default:
dev_err(component->dev, "DAI invert mode unsupported\n");
return -EINVAL;
}
regmap_update_bits(max98520->regmap,
MAX98520_R2041_PCM_CLK_SETUP,
MAX98520_PCM_MODE_CFG_PCM_BCLKEDGE,
invert);
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
format = MAX98520_PCM_FORMAT_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
format = MAX98520_PCM_FORMAT_LJ;
break;
case SND_SOC_DAIFMT_DSP_A:
format = MAX98520_PCM_FORMAT_TDM_MODE1;
break;
case SND_SOC_DAIFMT_DSP_B:
format = MAX98520_PCM_FORMAT_TDM_MODE0;
break;
default:
return -EINVAL;
}
regmap_update_bits(max98520->regmap,
MAX98520_R2040_PCM_MODE_CFG,
MAX98520_PCM_MODE_CFG_FORMAT_MASK,
format << MAX98520_PCM_MODE_CFG_FORMAT_SHIFT);
return 0;
}
/* BCLKs per LRCLK */
static const int bclk_sel_table[] = {
32, 48, 64, 96, 128, 192, 256, 384, 512, 320,
};
static int max98520_get_bclk_sel(int bclk)
{
int i;
/* match BCLKs per LRCLK */
for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) {
if (bclk_sel_table[i] == bclk)
return i + 2;
}
return 0;
}
static int max98520_set_clock(struct snd_soc_component *component,
struct snd_pcm_hw_params *params)
{
struct max98520_priv *max98520 =
snd_soc_component_get_drvdata(component);
/* BCLK/LRCLK ratio calculation */
int blr_clk_ratio = params_channels(params) * max98520->ch_size;
int value;
if (!max98520->tdm_mode) {
/* BCLK configuration */
value = max98520_get_bclk_sel(blr_clk_ratio);
if (!value) {
dev_err(component->dev, "format unsupported %d\n",
params_format(params));
return -EINVAL;
}
regmap_update_bits(max98520->regmap,
MAX98520_R2041_PCM_CLK_SETUP,
MAX98520_PCM_CLK_SETUP_BSEL_MASK,
value);
}
dev_dbg(component->dev, "%s tdm_mode:%d out\n", __func__, max98520->tdm_mode);
return 0;
}
static int max98520_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct max98520_priv *max98520 =
snd_soc_component_get_drvdata(component);
unsigned int sampling_rate = 0;
unsigned int chan_sz = 0;
/* pcm mode configuration */
switch (snd_pcm_format_width(params_format(params))) {
case 16:
chan_sz = MAX98520_PCM_MODE_CFG_CHANSZ_16;
break;
case 24:
chan_sz = MAX98520_PCM_MODE_CFG_CHANSZ_24;
break;
case 32:
chan_sz = MAX98520_PCM_MODE_CFG_CHANSZ_32;
break;
default:
dev_err(component->dev, "format unsupported %d\n",
params_format(params));
goto err;
}
max98520->ch_size = snd_pcm_format_width(params_format(params));
regmap_update_bits(max98520->regmap,
MAX98520_R2040_PCM_MODE_CFG,
MAX98520_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
dev_dbg(component->dev, "format supported %d",
params_format(params));
/* sampling rate configuration */
switch (params_rate(params)) {
case 8000:
sampling_rate = MAX98520_PCM_SR_8000;
break;
case 11025:
sampling_rate = MAX98520_PCM_SR_11025;
break;
case 12000:
sampling_rate = MAX98520_PCM_SR_12000;
break;
case 16000:
sampling_rate = MAX98520_PCM_SR_16000;
break;
case 22050:
sampling_rate = MAX98520_PCM_SR_22050;
break;
case 24000:
sampling_rate = MAX98520_PCM_SR_24000;
break;
case 32000:
sampling_rate = MAX98520_PCM_SR_32000;
break;
case 44100:
sampling_rate = MAX98520_PCM_SR_44100;
break;
case 48000:
sampling_rate = MAX98520_PCM_SR_48000;
break;
case 88200:
sampling_rate = MAX98520_PCM_SR_88200;
break;
case 96000:
sampling_rate = MAX98520_PCM_SR_96000;
break;
case 176400:
sampling_rate = MAX98520_PCM_SR_176400;
break;
case 192000:
sampling_rate = MAX98520_PCM_SR_192000;
break;
default:
dev_err(component->dev, "rate %d not supported\n",
params_rate(params));
goto err;
}
dev_dbg(component->dev, " %s ch_size: %d, sampling rate : %d out\n", __func__,
snd_pcm_format_width(params_format(params)), params_rate(params));
/* set DAI_SR to correct LRCLK frequency */
regmap_update_bits(max98520->regmap,
MAX98520_R2042_PCM_SR_SETUP,
MAX98520_PCM_SR_MASK,
sampling_rate);
return max98520_set_clock(component, params);
err:
dev_dbg(component->dev, "%s out error", __func__);
return -EINVAL;
}
static int max98520_dai_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask,
int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
struct max98520_priv *max98520 =
snd_soc_component_get_drvdata(component);
int bsel;
unsigned int chan_sz = 0;
if (!tx_mask && !rx_mask && !slots && !slot_width)
max98520->tdm_mode = false;
else
max98520->tdm_mode = true;
/* BCLK configuration */
bsel = max98520_get_bclk_sel(slots * slot_width);
if (bsel == 0) {
dev_err(component->dev, "BCLK %d not supported\n",
slots * slot_width);
return -EINVAL;
}
regmap_update_bits(max98520->regmap,
MAX98520_R2041_PCM_CLK_SETUP,
MAX98520_PCM_CLK_SETUP_BSEL_MASK,
bsel);
/* Channel size configuration */
switch (slot_width) {
case 16:
chan_sz = MAX98520_PCM_MODE_CFG_CHANSZ_16;
break;
case 24:
chan_sz = MAX98520_PCM_MODE_CFG_CHANSZ_24;
break;
case 32:
chan_sz = MAX98520_PCM_MODE_CFG_CHANSZ_32;
break;
default:
dev_err(component->dev, "format unsupported %d\n",
slot_width);
return -EINVAL;
}
regmap_update_bits(max98520->regmap,
MAX98520_R2040_PCM_MODE_CFG,
MAX98520_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
/* Rx slot configuration */
regmap_update_bits(max98520->regmap,
MAX98520_R2044_PCM_RX_SRC2,
MAX98520_PCM_DMIX_CH0_SRC_MASK,
rx_mask);
regmap_update_bits(max98520->regmap,
MAX98520_R2044_PCM_RX_SRC2,
MAX98520_PCM_DMIX_CH1_SRC_MASK,
rx_mask << MAX98520_PCM_DMIX_CH1_SHIFT);
return 0;
}
#define MAX98520_RATES SNDRV_PCM_RATE_8000_192000
#define MAX98520_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops max98520_dai_ops = {
.set_fmt = max98520_dai_set_fmt,
.hw_params = max98520_dai_hw_params,
.set_tdm_slot = max98520_dai_tdm_slot,
};
static int max98520_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct max98520_priv *max98520 =
snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
dev_dbg(component->dev, " AMP ON\n");
regmap_write(max98520->regmap, MAX98520_R209F_AMP_EN, 1);
regmap_write(max98520->regmap, MAX98520_R210F_GLOBAL_EN, 1);
usleep_range(30000, 31000);
break;
case SND_SOC_DAPM_POST_PMD:
dev_dbg(component->dev, " AMP OFF\n");
regmap_write(max98520->regmap, MAX98520_R210F_GLOBAL_EN, 0);
regmap_write(max98520->regmap, MAX98520_R209F_AMP_EN, 0);
usleep_range(30000, 31000);
break;
default:
return 0;
}
return 0;
}
static const char * const max98520_switch_text[] = {
"Left", "Right", "LeftRight"};
static const struct soc_enum dai_sel_enum =
SOC_ENUM_SINGLE(MAX98520_R2043_PCM_RX_SRC1,
0, 3, max98520_switch_text);
static const struct snd_kcontrol_new max98520_dai_controls =
SOC_DAPM_ENUM("DAI Sel", dai_sel_enum);
static const struct snd_kcontrol_new max98520_left_input_mixer_controls[] = {
SOC_DAPM_SINGLE("PCM_INPUT_CH0", MAX98520_R2044_PCM_RX_SRC2, 0, 0x0, 0),
SOC_DAPM_SINGLE("PCM_INPUT_CH1", MAX98520_R2044_PCM_RX_SRC2, 0, 0x1, 0),
SOC_DAPM_SINGLE("PCM_INPUT_CH2", MAX98520_R2044_PCM_RX_SRC2, 0, 0x2, 0),
SOC_DAPM_SINGLE("PCM_INPUT_CH3", MAX98520_R2044_PCM_RX_SRC2, 0, 0x3, 0),
SOC_DAPM_SINGLE("PCM_INPUT_CH4", MAX98520_R2044_PCM_RX_SRC2, 0, 0x4, 0),
SOC_DAPM_SINGLE("PCM_INPUT_CH5", MAX98520_R2044_PCM_RX_SRC2, 0, 0x5, 0),
SOC_DAPM_SINGLE("PCM_INPUT_CH6", MAX98520_R2044_PCM_RX_SRC2, 0, 0x6, 0),
SOC_DAPM_SINGLE("PCM_INPUT_CH7", MAX98520_R2044_PCM_RX_SRC2, 0, 0x7, 0),
SOC_DAPM_SINGLE("PCM_INPUT_CH8", MAX98520_R2044_PCM_RX_SRC2, 0, 0x8, 0),
SOC_DAPM_SINGLE("PCM_INPUT_CH9", MAX98520_R2044_PCM_RX_SRC2, 0, 0x9, 0),
SOC_DAPM_SINGLE("PCM_INPUT_CH10", MAX98520_R2044_PCM_RX_SRC2, 0, 0xa, 0),
SOC_DAPM_SINGLE("PCM_INPUT_CH11", MAX98520_R2044_PCM_RX_SRC2, 0, 0xb, 0),
SOC_DAPM_SINGLE("PCM_INPUT_CH12", MAX98520_R2044_PCM_RX_SRC2, 0, 0xc, 0),
SOC_DAPM_SINGLE("PCM_INPUT_CH13", MAX98520_R2044_PCM_RX_SRC2, 0, 0xd, 0),
SOC_DAPM_SINGLE("PCM_INPUT_CH14", MAX98520_R2044_PCM_RX_SRC2, 0, 0xe, 0),
SOC_DAPM_SINGLE("PCM_INPUT_CH15", MAX98520_R2044_PCM_RX_SRC2, 0, 0xf, 0),
};
static const struct snd_kcontrol_new max98520_right_input_mixer_controls[] = {
SOC_DAPM_SINGLE("PCM_INPUT_CH0", MAX98520_R2044_PCM_RX_SRC2, 4, 0x0, 0),
SOC_DAPM_SINGLE("PCM_INPUT_CH1", MAX98520_R2044_PCM_RX_SRC2, 4, 0x1, 0),
SOC_DAPM_SINGLE("PCM_INPUT_CH2", MAX98520_R2044_PCM_RX_SRC2, 4, 0x2, 0),
SOC_DAPM_SINGLE("PCM_INPUT_CH3", MAX98520_R2044_PCM_RX_SRC2, 4, 0x3, 0),
SOC_DAPM_SINGLE("PCM_INPUT_CH4", MAX98520_R2044_PCM_RX_SRC2, 4, 0x4, 0),
SOC_DAPM_SINGLE("PCM_INPUT_CH5", MAX98520_R2044_PCM_RX_SRC2, 4, 0x5, 0),
SOC_DAPM_SINGLE("PCM_INPUT_CH6", MAX98520_R2044_PCM_RX_SRC2, 4, 0x6, 0),
SOC_DAPM_SINGLE("PCM_INPUT_CH7", MAX98520_R2044_PCM_RX_SRC2, 4, 0x7, 0),
SOC_DAPM_SINGLE("PCM_INPUT_CH8", MAX98520_R2044_PCM_RX_SRC2, 4, 0x8, 0),
SOC_DAPM_SINGLE("PCM_INPUT_CH9", MAX98520_R2044_PCM_RX_SRC2, 4, 0x9, 0),
SOC_DAPM_SINGLE("PCM_INPUT_CH10", MAX98520_R2044_PCM_RX_SRC2, 4, 0xa, 0),
SOC_DAPM_SINGLE("PCM_INPUT_CH11", MAX98520_R2044_PCM_RX_SRC2, 4, 0xb, 0),
SOC_DAPM_SINGLE("PCM_INPUT_CH12", MAX98520_R2044_PCM_RX_SRC2, 4, 0xc, 0),
SOC_DAPM_SINGLE("PCM_INPUT_CH13", MAX98520_R2044_PCM_RX_SRC2, 4, 0xd, 0),
SOC_DAPM_SINGLE("PCM_INPUT_CH14", MAX98520_R2044_PCM_RX_SRC2, 4, 0xe, 0),
SOC_DAPM_SINGLE("PCM_INPUT_CH15", MAX98520_R2044_PCM_RX_SRC2, 4, 0xf, 0),
};
static const struct snd_soc_dapm_widget max98520_dapm_widgets[] = {
SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback",
SND_SOC_NOPM, 0, 0, max98520_dac_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0, &max98520_dai_controls),
SND_SOC_DAPM_OUTPUT("BE_OUT"),
/* Left Input Selection */
SND_SOC_DAPM_MIXER("Left Input Selection", SND_SOC_NOPM, 0, 0,
&max98520_left_input_mixer_controls[0],
ARRAY_SIZE(max98520_left_input_mixer_controls)),
/* Right Input Selection */
SND_SOC_DAPM_MIXER("Right Input Selection", SND_SOC_NOPM, 0, 0,
&max98520_right_input_mixer_controls[0],
ARRAY_SIZE(max98520_right_input_mixer_controls)),
};
static const DECLARE_TLV_DB_SCALE(max98520_digital_tlv, -6300, 50, 1);
static const DECLARE_TLV_DB_SCALE(max98520_spk_tlv, -600, 300, 0);
static const DECLARE_TLV_DB_RANGE(max98520_dht_lim_thresh_tlv,
0, 15, TLV_DB_SCALE_ITEM(-1500, 100, 0),
);
static const DECLARE_TLV_DB_RANGE(max98520_dht_hysteresis_tlv,
0, 3, TLV_DB_SCALE_ITEM(100, 100, 0),
4, 7, TLV_DB_SCALE_ITEM(600, 200, 0),
);
static const DECLARE_TLV_DB_RANGE(max98520_dht_rotation_point_tlv,
0, 1, TLV_DB_SCALE_ITEM(-1500, 300, 0),
2, 4, TLV_DB_SCALE_ITEM(-1000, 200, 0),
5, 10, TLV_DB_SCALE_ITEM(-500, 100, 0),
);
static const DECLARE_TLV_DB_RANGE(max98520_dht_supply_hr_tlv,
0, 16, TLV_DB_SCALE_ITEM(-2000, 250, 0),
);
static const DECLARE_TLV_DB_RANGE(max98520_dht_max_atten_tlv,
1, 20, TLV_DB_SCALE_ITEM(-2000, 100, 0),
);
static const char * const max98520_dht_attack_rate_text[] = {
"20us", "40us", "80us", "160us", "320us", "640us",
"1.28ms", "2.56ms", "5.12ms", "10.24ms", "20.48ms", "40.96ms",
"81.92ms", "163.84ms"
};
static SOC_ENUM_SINGLE_DECL(max98520_dht_attack_rate_enum,
MAX98520_R20D4_DHT_CFG3, 0,
max98520_dht_attack_rate_text);
static const char * const max98520_dht_release_rate_text[] = {
"2ms", "4ms", "8ms", "16ms", "32ms", "64ms", "128ms", "256ms", "512ms",
"1.024s", "2.048s", "4.096s", "8.192s", "16.384s"
};
static SOC_ENUM_SINGLE_DECL(max98520_dht_release_rate_enum,
MAX98520_R20D5_DHT_CFG4, 0,
max98520_dht_release_rate_text);
static bool max98520_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX98520_R2000_SW_RESET:
case MAX98520_R2027_THERM_FOLDBACK_EN:
case MAX98520_R2030_CLK_MON_CTRL:
case MAX98520_R2037_ERR_MON_CTRL:
case MAX98520_R204F_PCM_RX_EN:
case MAX98520_R209F_AMP_EN:
case MAX98520_R20CF_MEAS_ADC_CFG:
case MAX98520_R20D8_DHT_EN:
case MAX98520_R21FF_REVISION_ID:
case MAX98520_R2001_STATUS_1... MAX98520_R2002_STATUS_2:
case MAX98520_R2020_THERM_WARN_THRESH... MAX98520_R2023_THERM_FOLDBACK_SET:
case MAX98520_R2040_PCM_MODE_CFG... MAX98520_R2044_PCM_RX_SRC2:
case MAX98520_R2090_AMP_VOL_CTRL... MAX98520_R2092_AMP_DSP_CFG:
case MAX98520_R2094_SSM_CFG... MAX98520_R2095_AMP_CFG:
case MAX98520_R20B0_ADC_SR... MAX98520_R20BD_ADC_HIGH_TEMP_READBACK_LSB:
case MAX98520_R20D0_DHT_CFG1... MAX98520_R20D6_DHT_HYSTERESIS_CFG:
case MAX98520_R210E_AUTO_RESTART_BEHAVIOR... MAX98520_R210F_GLOBAL_EN:
case MAX98520_R2161_BOOST_TM1... MAX98520_R2163_BOOST_TM3:
return true;
default:
return false;
}
};
static bool max98520_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX98520_R210F_GLOBAL_EN:
case MAX98520_R21FF_REVISION_ID:
case MAX98520_R2000_SW_RESET:
case MAX98520_R2001_STATUS_1 ... MAX98520_R2002_STATUS_2:
case MAX98520_R20B4_ADC_READBACK_CTRL
... MAX98520_R20BD_ADC_HIGH_TEMP_READBACK_LSB:
return true;
default:
return false;
}
}
static const struct snd_kcontrol_new max98520_snd_controls[] = {
/* Volume */
SOC_SINGLE_TLV("Digital Volume", MAX98520_R2090_AMP_VOL_CTRL,
0, 0x7F, 1, max98520_digital_tlv),
SOC_SINGLE_TLV("Speaker Volume", MAX98520_R2091_AMP_PATH_GAIN,
0, 0x5, 0, max98520_spk_tlv),
/* Volume Ramp Up/Down Enable*/
SOC_SINGLE("Ramp Up Switch", MAX98520_R2092_AMP_DSP_CFG,
MAX98520_DSP_SPK_VOL_RMPUP_SHIFT, 1, 0),
SOC_SINGLE("Ramp Down Switch", MAX98520_R2092_AMP_DSP_CFG,
MAX98520_DSP_SPK_VOL_RMPDN_SHIFT, 1, 0),
/* Clock Monitor Enable */
SOC_SINGLE("CLK Monitor Switch", MAX98520_R2037_ERR_MON_CTRL,
MAX98520_CTRL_CMON_EN_SHIFT, 1, 0),
/* Clock Monitor Config */
SOC_SINGLE("CLKMON Autorestart Switch", MAX98520_R2030_CLK_MON_CTRL,
MAX98520_CMON_AUTORESTART_SHIFT, 1, 0),
/* Dither Enable */
SOC_SINGLE("Dither Switch", MAX98520_R2092_AMP_DSP_CFG,
MAX98520_DSP_SPK_DITH_EN_SHIFT, 1, 0),
/* DC Blocker Enable */
SOC_SINGLE("DC Blocker Switch", MAX98520_R2092_AMP_DSP_CFG,
MAX98520_DSP_SPK_DCBLK_EN_SHIFT, 1, 0),
/* Speaker Safe Mode Enable */
SOC_SINGLE("Speaker Safemode Switch", MAX98520_R2092_AMP_DSP_CFG,
MAX98520_DSP_SPK_SAFE_EN_SHIFT, 1, 0),
/* AMP SSM Enable */
SOC_SINGLE("CP Bypass Switch", MAX98520_R2094_SSM_CFG,
MAX98520_SSM_RCVR_MODE_SHIFT, 1, 0),
/* Dynamic Headroom Tracking */
SOC_SINGLE("DHT Switch", MAX98520_R20D8_DHT_EN, 0, 1, 0),
SOC_SINGLE("DHT Limiter Mode", MAX98520_R20D2_LIMITER_CFG2,
MAX98520_DHT_LIMITER_MODE_SHIFT, 1, 0),
SOC_SINGLE("DHT Hysteresis Switch", MAX98520_R20D6_DHT_HYSTERESIS_CFG,
MAX98520_DHT_HYSTERESIS_SWITCH_SHIFT, 1, 0),
SOC_SINGLE_TLV("DHT Rot Pnt", MAX98520_R20D0_DHT_CFG1,
MAX98520_DHT_VROT_PNT_SHIFT, 10, 1, max98520_dht_rotation_point_tlv),
SOC_SINGLE_TLV("DHT Supply Headroom", MAX98520_R20D1_LIMITER_CFG1,
MAX98520_DHT_SUPPLY_HR_SHIFT, 16, 0, max98520_dht_supply_hr_tlv),
SOC_SINGLE_TLV("DHT Limiter Threshold", MAX98520_R20D2_LIMITER_CFG2,
MAX98520_DHT_LIMITER_THRESHOLD_SHIFT, 0xF, 1, max98520_dht_lim_thresh_tlv),
SOC_SINGLE_TLV("DHT Max Attenuation", MAX98520_R20D3_DHT_CFG2,
MAX98520_DHT_MAX_ATTEN_SHIFT, 20, 1, max98520_dht_max_atten_tlv),
SOC_SINGLE_TLV("DHT Hysteresis", MAX98520_R20D6_DHT_HYSTERESIS_CFG,
MAX98520_DHT_HYSTERESIS_SHIFT, 0x7, 0, max98520_dht_hysteresis_tlv),
SOC_ENUM("DHT Attack Rate", max98520_dht_attack_rate_enum),
SOC_ENUM("DHT Release Rate", max98520_dht_release_rate_enum),
/* ADC configuration */
SOC_SINGLE("ADC PVDD CH Switch", MAX98520_R20CF_MEAS_ADC_CFG, 0, 1, 0),
SOC_SINGLE("ADC PVDD FLT Switch", MAX98520_R20B2_ADC_PVDD0_CFG, MAX98520_FLT_EN_SHIFT, 1, 0),
SOC_SINGLE("ADC TEMP FLT Switch", MAX98520_R20B3_ADC_THERMAL_CFG, MAX98520_FLT_EN_SHIFT, 1, 0),
SOC_SINGLE("ADC PVDD MSB", MAX98520_R20B6_ADC_PVDD_READBACK_MSB, 0, 0xFF, 0),
SOC_SINGLE("ADC PVDD LSB", MAX98520_R20B7_ADC_PVDD_READBACK_LSB, 0, 0x01, 0),
SOC_SINGLE("ADC TEMP MSB", MAX98520_R20B8_ADC_TEMP_READBACK_MSB, 0, 0xFF, 0),
SOC_SINGLE("ADC TEMP LSB", MAX98520_R20B9_ADC_TEMP_READBACK_LSB, 0, 0x01, 0),
};
static const struct snd_soc_dapm_route max98520_audio_map[] = {
/* Plabyack */
{"DAI Sel Mux", "Left", "Amp Enable"},
{"DAI Sel Mux", "Right", "Amp Enable"},
{"DAI Sel Mux", "LeftRight", "Amp Enable"},
{"BE_OUT", NULL, "DAI Sel Mux"},
};
static struct snd_soc_dai_driver max98520_dai[] = {
{
.name = "max98520-aif1",
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MAX98520_RATES,
.formats = MAX98520_FORMATS,
},
.ops = &max98520_dai_ops,
}
};
static int max98520_probe(struct snd_soc_component *component)
{
struct max98520_priv *max98520 =
snd_soc_component_get_drvdata(component);
/* Software Reset */
regmap_write(max98520->regmap, MAX98520_R2000_SW_RESET, 1);
/* L/R mono mix configuration : "DAI Sel" for 0x2043 */
regmap_write(max98520->regmap, MAX98520_R2043_PCM_RX_SRC1, 0x2);
/* PCM input channles configuration : "Left Input Selection" for 0x2044 */
/* PCM input channles configuration : "Right Input Selection" for 0x2044 */
regmap_write(max98520->regmap, MAX98520_R2044_PCM_RX_SRC2, 0x10);
/* Enable DC blocker */
regmap_update_bits(max98520->regmap, MAX98520_R2092_AMP_DSP_CFG, 1, 1);
/* Enable Clock Monitor Auto-restart */
regmap_write(max98520->regmap, MAX98520_R2030_CLK_MON_CTRL, 0x1);
/* set Rx Enable */
regmap_update_bits(max98520->regmap,
MAX98520_R204F_PCM_RX_EN,
MAX98520_PCM_RX_EN_MASK,
1);
return 0;
}
static int __maybe_unused max98520_suspend(struct device *dev)
{
struct max98520_priv *max98520 = dev_get_drvdata(dev);
regcache_cache_only(max98520->regmap, true);
regcache_mark_dirty(max98520->regmap);
return 0;
}
static int __maybe_unused max98520_resume(struct device *dev)
{
struct max98520_priv *max98520 = dev_get_drvdata(dev);
regcache_cache_only(max98520->regmap, false);
regmap_write(max98520->regmap, MAX98520_R2000_SW_RESET, 1);
regcache_sync(max98520->regmap);
return 0;
}
static const struct dev_pm_ops max98520_pm = {
SET_SYSTEM_SLEEP_PM_OPS(max98520_suspend, max98520_resume)
};
static const struct snd_soc_component_driver soc_codec_dev_max98520 = {
.probe = max98520_probe,
.controls = max98520_snd_controls,
.num_controls = ARRAY_SIZE(max98520_snd_controls),
.dapm_widgets = max98520_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(max98520_dapm_widgets),
.dapm_routes = max98520_audio_map,
.num_dapm_routes = ARRAY_SIZE(max98520_audio_map),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config max98520_regmap = {
.reg_bits = 16,
.val_bits = 8,
.max_register = MAX98520_R21FF_REVISION_ID,
.reg_defaults = max98520_reg,
.num_reg_defaults = ARRAY_SIZE(max98520_reg),
.readable_reg = max98520_readable_register,
.volatile_reg = max98520_volatile_reg,
.cache_type = REGCACHE_RBTREE,
};
static void max98520_power_on(struct max98520_priv *max98520, bool poweron)
{
if (max98520->reset_gpio)
gpiod_set_value_cansleep(max98520->reset_gpio, !poweron);
}
static int max98520_i2c_probe(struct i2c_client *i2c)
{
int ret;
int reg = 0;
struct max98520_priv *max98520;
struct i2c_adapter *adapter = to_i2c_adapter(i2c->dev.parent);
ret = i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA);
if (!ret) {
dev_err(&i2c->dev, "I2C check functionality failed\n");
return -ENXIO;
}
max98520 = devm_kzalloc(&i2c->dev, sizeof(*max98520), GFP_KERNEL);
if (!max98520)
return -ENOMEM;
i2c_set_clientdata(i2c, max98520);
/* regmap initialization */
max98520->regmap = devm_regmap_init_i2c(i2c, &max98520_regmap);
if (IS_ERR(max98520->regmap)) {
ret = PTR_ERR(max98520->regmap);
dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
return ret;
}
/* Power on device */
max98520->reset_gpio = devm_gpiod_get_optional(&i2c->dev, "reset", GPIOD_OUT_HIGH);
if (max98520->reset_gpio) {
if (IS_ERR(max98520->reset_gpio)) {
ret = PTR_ERR(max98520->reset_gpio);
dev_err(&i2c->dev, "Unable to request GPIO pin: %d.\n", ret);
return ret;
}
max98520_power_on(max98520, 1);
}
/* Check Revision ID */
ret = regmap_read(max98520->regmap, MAX98520_R21FF_REVISION_ID, ®);
if (ret < 0) {
dev_err(&i2c->dev,
"Failed to read: 0x%02X\n", MAX98520_R21FF_REVISION_ID);
return ret;
}
dev_info(&i2c->dev, "MAX98520 revisionID: 0x%02X\n", reg);
/* codec registration */
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_codec_dev_max98520,
max98520_dai, ARRAY_SIZE(max98520_dai));
if (ret < 0)
dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
return ret;
}
static const struct i2c_device_id max98520_i2c_id[] = {
{ "max98520", 0},
{ },
};
MODULE_DEVICE_TABLE(i2c, max98520_i2c_id);
#if defined(CONFIG_OF)
static const struct of_device_id max98520_of_match[] = {
{ .compatible = "maxim,max98520", },
{ }
};
MODULE_DEVICE_TABLE(of, max98520_of_match);
#endif
static struct i2c_driver max98520_i2c_driver = {
.driver = {
.name = "max98520",
.of_match_table = of_match_ptr(max98520_of_match),
.pm = &max98520_pm,
},
.probe = max98520_i2c_probe,
.id_table = max98520_i2c_id,
};
module_i2c_driver(max98520_i2c_driver)
MODULE_DESCRIPTION("ALSA SoC MAX98520 driver");
MODULE_AUTHOR("George Song <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/max98520.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* rt5514.c -- RT5514 ALSA SoC audio codec driver
*
* Copyright 2015 Realtek Semiconductor Corp.
* Author: Oder Chiou <[email protected]>
*/
#include <linux/acpi.h>
#include <linux/fs.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/regmap.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/firmware.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "rl6231.h"
#include "rt5514.h"
#if IS_ENABLED(CONFIG_SND_SOC_RT5514_SPI)
#include "rt5514-spi.h"
#endif
static const struct reg_sequence rt5514_i2c_patch[] = {
{0x1800101c, 0x00000000},
{0x18001100, 0x0000031f},
{0x18001104, 0x00000007},
{0x18001108, 0x00000000},
{0x1800110c, 0x00000000},
{0x18001110, 0x00000000},
{0x18001114, 0x00000001},
{0x18001118, 0x00000000},
{0x18002f08, 0x00000006},
{0x18002f00, 0x00055149},
{0x18002f00, 0x0005514b},
{0x18002f00, 0x00055149},
{0xfafafafa, 0x00000001},
{0x18002f10, 0x00000001},
{0x18002f10, 0x00000000},
{0x18002f10, 0x00000001},
{0xfafafafa, 0x00000001},
{0x18002000, 0x000010ec},
{0xfafafafa, 0x00000000},
};
static const struct reg_sequence rt5514_patch[] = {
{RT5514_DIG_IO_CTRL, 0x00000040},
{RT5514_CLK_CTRL1, 0x38020041},
{RT5514_SRC_CTRL, 0x44000eee},
{RT5514_ANA_CTRL_LDO10, 0x00028604},
{RT5514_ANA_CTRL_ADCFED, 0x00000800},
{RT5514_ASRC_IN_CTRL1, 0x00000003},
{RT5514_DOWNFILTER0_CTRL3, 0x10000342},
{RT5514_DOWNFILTER1_CTRL3, 0x10000342},
};
static const struct reg_default rt5514_reg[] = {
{RT5514_RESET, 0x00000000},
{RT5514_PWR_ANA1, 0x00808880},
{RT5514_PWR_ANA2, 0x00220000},
{RT5514_I2S_CTRL1, 0x00000330},
{RT5514_I2S_CTRL2, 0x20000000},
{RT5514_VAD_CTRL6, 0xc00007d2},
{RT5514_EXT_VAD_CTRL, 0x80000080},
{RT5514_DIG_IO_CTRL, 0x00000040},
{RT5514_PAD_CTRL1, 0x00804000},
{RT5514_DMIC_DATA_CTRL, 0x00000005},
{RT5514_DIG_SOURCE_CTRL, 0x00000002},
{RT5514_SRC_CTRL, 0x44000eee},
{RT5514_DOWNFILTER2_CTRL1, 0x0000882f},
{RT5514_PLL_SOURCE_CTRL, 0x00000004},
{RT5514_CLK_CTRL1, 0x38020041},
{RT5514_CLK_CTRL2, 0x00000000},
{RT5514_PLL3_CALIB_CTRL1, 0x00400200},
{RT5514_PLL3_CALIB_CTRL5, 0x40220012},
{RT5514_DELAY_BUF_CTRL1, 0x7fff006a},
{RT5514_DELAY_BUF_CTRL3, 0x00000000},
{RT5514_ASRC_IN_CTRL1, 0x00000003},
{RT5514_DOWNFILTER0_CTRL1, 0x00020c2f},
{RT5514_DOWNFILTER0_CTRL2, 0x00020c2f},
{RT5514_DOWNFILTER0_CTRL3, 0x10000342},
{RT5514_DOWNFILTER1_CTRL1, 0x00020c2f},
{RT5514_DOWNFILTER1_CTRL2, 0x00020c2f},
{RT5514_DOWNFILTER1_CTRL3, 0x10000342},
{RT5514_ANA_CTRL_LDO10, 0x00028604},
{RT5514_ANA_CTRL_LDO18_16, 0x02000345},
{RT5514_ANA_CTRL_ADC12, 0x0000a2a8},
{RT5514_ANA_CTRL_ADC21, 0x00001180},
{RT5514_ANA_CTRL_ADC22, 0x0000aaa8},
{RT5514_ANA_CTRL_ADC23, 0x00151427},
{RT5514_ANA_CTRL_MICBST, 0x00002000},
{RT5514_ANA_CTRL_ADCFED, 0x00000800},
{RT5514_ANA_CTRL_INBUF, 0x00000143},
{RT5514_ANA_CTRL_VREF, 0x00008d50},
{RT5514_ANA_CTRL_PLL3, 0x0000000e},
{RT5514_ANA_CTRL_PLL1_1, 0x00000000},
{RT5514_ANA_CTRL_PLL1_2, 0x00030220},
{RT5514_DMIC_LP_CTRL, 0x00000000},
{RT5514_MISC_CTRL_DSP, 0x00000000},
{RT5514_DSP_CTRL1, 0x00055149},
{RT5514_DSP_CTRL3, 0x00000006},
{RT5514_DSP_CTRL4, 0x00000001},
{RT5514_VENDOR_ID1, 0x00000001},
{RT5514_VENDOR_ID2, 0x10ec5514},
};
static void rt5514_enable_dsp_prepare(struct rt5514_priv *rt5514)
{
/* Reset */
regmap_write(rt5514->i2c_regmap, 0x18002000, 0x000010ec);
/* LDO_I_limit */
regmap_write(rt5514->i2c_regmap, 0x18002200, 0x00028604);
/* I2C bypass enable */
regmap_write(rt5514->i2c_regmap, 0xfafafafa, 0x00000001);
/* mini-core reset */
regmap_write(rt5514->i2c_regmap, 0x18002f00, 0x0005514b);
regmap_write(rt5514->i2c_regmap, 0x18002f00, 0x00055149);
/* I2C bypass disable */
regmap_write(rt5514->i2c_regmap, 0xfafafafa, 0x00000000);
/* PIN config */
regmap_write(rt5514->i2c_regmap, 0x18002070, 0x00000040);
/* PLL3(QN)=RCOSC*(10+2) */
regmap_write(rt5514->i2c_regmap, 0x18002240, 0x0000000a);
/* PLL3 source=RCOSC, fsi=rt_clk */
regmap_write(rt5514->i2c_regmap, 0x18002100, 0x0000000b);
/* Power on RCOSC, pll3 */
regmap_write(rt5514->i2c_regmap, 0x18002004, 0x00808b81);
/* DSP clk source = pll3, ENABLE DSP clk */
regmap_write(rt5514->i2c_regmap, 0x18002f08, 0x00000005);
/* Enable DSP clk auto switch */
regmap_write(rt5514->i2c_regmap, 0x18001114, 0x00000001);
/* Reduce DSP power */
regmap_write(rt5514->i2c_regmap, 0x18001118, 0x00000001);
}
static bool rt5514_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case RT5514_VENDOR_ID1:
case RT5514_VENDOR_ID2:
return true;
default:
return false;
}
}
static bool rt5514_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case RT5514_RESET:
case RT5514_PWR_ANA1:
case RT5514_PWR_ANA2:
case RT5514_I2S_CTRL1:
case RT5514_I2S_CTRL2:
case RT5514_VAD_CTRL6:
case RT5514_EXT_VAD_CTRL:
case RT5514_DIG_IO_CTRL:
case RT5514_PAD_CTRL1:
case RT5514_DMIC_DATA_CTRL:
case RT5514_DIG_SOURCE_CTRL:
case RT5514_SRC_CTRL:
case RT5514_DOWNFILTER2_CTRL1:
case RT5514_PLL_SOURCE_CTRL:
case RT5514_CLK_CTRL1:
case RT5514_CLK_CTRL2:
case RT5514_PLL3_CALIB_CTRL1:
case RT5514_PLL3_CALIB_CTRL5:
case RT5514_DELAY_BUF_CTRL1:
case RT5514_DELAY_BUF_CTRL3:
case RT5514_ASRC_IN_CTRL1:
case RT5514_DOWNFILTER0_CTRL1:
case RT5514_DOWNFILTER0_CTRL2:
case RT5514_DOWNFILTER0_CTRL3:
case RT5514_DOWNFILTER1_CTRL1:
case RT5514_DOWNFILTER1_CTRL2:
case RT5514_DOWNFILTER1_CTRL3:
case RT5514_ANA_CTRL_LDO10:
case RT5514_ANA_CTRL_LDO18_16:
case RT5514_ANA_CTRL_ADC12:
case RT5514_ANA_CTRL_ADC21:
case RT5514_ANA_CTRL_ADC22:
case RT5514_ANA_CTRL_ADC23:
case RT5514_ANA_CTRL_MICBST:
case RT5514_ANA_CTRL_ADCFED:
case RT5514_ANA_CTRL_INBUF:
case RT5514_ANA_CTRL_VREF:
case RT5514_ANA_CTRL_PLL3:
case RT5514_ANA_CTRL_PLL1_1:
case RT5514_ANA_CTRL_PLL1_2:
case RT5514_DMIC_LP_CTRL:
case RT5514_MISC_CTRL_DSP:
case RT5514_DSP_CTRL1:
case RT5514_DSP_CTRL3:
case RT5514_DSP_CTRL4:
case RT5514_VENDOR_ID1:
case RT5514_VENDOR_ID2:
return true;
default:
return false;
}
}
static bool rt5514_i2c_readable_register(struct device *dev,
unsigned int reg)
{
switch (reg) {
case RT5514_DSP_MAPPING | RT5514_RESET:
case RT5514_DSP_MAPPING | RT5514_PWR_ANA1:
case RT5514_DSP_MAPPING | RT5514_PWR_ANA2:
case RT5514_DSP_MAPPING | RT5514_I2S_CTRL1:
case RT5514_DSP_MAPPING | RT5514_I2S_CTRL2:
case RT5514_DSP_MAPPING | RT5514_VAD_CTRL6:
case RT5514_DSP_MAPPING | RT5514_EXT_VAD_CTRL:
case RT5514_DSP_MAPPING | RT5514_DIG_IO_CTRL:
case RT5514_DSP_MAPPING | RT5514_PAD_CTRL1:
case RT5514_DSP_MAPPING | RT5514_DMIC_DATA_CTRL:
case RT5514_DSP_MAPPING | RT5514_DIG_SOURCE_CTRL:
case RT5514_DSP_MAPPING | RT5514_SRC_CTRL:
case RT5514_DSP_MAPPING | RT5514_DOWNFILTER2_CTRL1:
case RT5514_DSP_MAPPING | RT5514_PLL_SOURCE_CTRL:
case RT5514_DSP_MAPPING | RT5514_CLK_CTRL1:
case RT5514_DSP_MAPPING | RT5514_CLK_CTRL2:
case RT5514_DSP_MAPPING | RT5514_PLL3_CALIB_CTRL1:
case RT5514_DSP_MAPPING | RT5514_PLL3_CALIB_CTRL5:
case RT5514_DSP_MAPPING | RT5514_DELAY_BUF_CTRL1:
case RT5514_DSP_MAPPING | RT5514_DELAY_BUF_CTRL3:
case RT5514_DSP_MAPPING | RT5514_ASRC_IN_CTRL1:
case RT5514_DSP_MAPPING | RT5514_DOWNFILTER0_CTRL1:
case RT5514_DSP_MAPPING | RT5514_DOWNFILTER0_CTRL2:
case RT5514_DSP_MAPPING | RT5514_DOWNFILTER0_CTRL3:
case RT5514_DSP_MAPPING | RT5514_DOWNFILTER1_CTRL1:
case RT5514_DSP_MAPPING | RT5514_DOWNFILTER1_CTRL2:
case RT5514_DSP_MAPPING | RT5514_DOWNFILTER1_CTRL3:
case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_LDO10:
case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_LDO18_16:
case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC12:
case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC21:
case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC22:
case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC23:
case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_MICBST:
case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADCFED:
case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_INBUF:
case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_VREF:
case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_PLL3:
case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_PLL1_1:
case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_PLL1_2:
case RT5514_DSP_MAPPING | RT5514_DMIC_LP_CTRL:
case RT5514_DSP_MAPPING | RT5514_MISC_CTRL_DSP:
case RT5514_DSP_MAPPING | RT5514_DSP_CTRL1:
case RT5514_DSP_MAPPING | RT5514_DSP_CTRL3:
case RT5514_DSP_MAPPING | RT5514_DSP_CTRL4:
case RT5514_DSP_MAPPING | RT5514_VENDOR_ID1:
case RT5514_DSP_MAPPING | RT5514_VENDOR_ID2:
return true;
default:
return false;
}
}
/* {-3, 0, +3, +4.5, +7.5, +9.5, +12, +14, +17} dB */
static const DECLARE_TLV_DB_RANGE(bst_tlv,
0, 2, TLV_DB_SCALE_ITEM(-300, 300, 0),
3, 3, TLV_DB_SCALE_ITEM(450, 0, 0),
4, 4, TLV_DB_SCALE_ITEM(750, 0, 0),
5, 5, TLV_DB_SCALE_ITEM(950, 0, 0),
6, 6, TLV_DB_SCALE_ITEM(1200, 0, 0),
7, 7, TLV_DB_SCALE_ITEM(1400, 0, 0),
8, 8, TLV_DB_SCALE_ITEM(1700, 0, 0)
);
static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
static int rt5514_dsp_voice_wake_up_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = rt5514->dsp_enabled;
return 0;
}
static int rt5514_calibration(struct rt5514_priv *rt5514, bool on)
{
if (on) {
regmap_write(rt5514->regmap, RT5514_ANA_CTRL_PLL3, 0x0000000a);
regmap_update_bits(rt5514->regmap, RT5514_PLL_SOURCE_CTRL, 0xf,
0xa);
regmap_update_bits(rt5514->regmap, RT5514_PWR_ANA1, 0x301,
0x301);
regmap_write(rt5514->regmap, RT5514_PLL3_CALIB_CTRL4,
0x80000000 | rt5514->pll3_cal_value);
regmap_write(rt5514->regmap, RT5514_PLL3_CALIB_CTRL1,
0x8bb80800);
regmap_update_bits(rt5514->regmap, RT5514_PLL3_CALIB_CTRL5,
0xc0000000, 0x80000000);
regmap_update_bits(rt5514->regmap, RT5514_PLL3_CALIB_CTRL5,
0xc0000000, 0xc0000000);
} else {
regmap_update_bits(rt5514->regmap, RT5514_PLL3_CALIB_CTRL5,
0xc0000000, 0x40000000);
regmap_update_bits(rt5514->regmap, RT5514_PWR_ANA1, 0x301, 0);
regmap_update_bits(rt5514->regmap, RT5514_PLL_SOURCE_CTRL, 0xf,
0x4);
}
return 0;
}
static int rt5514_dsp_voice_wake_up_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
const struct firmware *fw = NULL;
u8 buf[8];
if (ucontrol->value.integer.value[0] == rt5514->dsp_enabled)
return 0;
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
rt5514->dsp_enabled = ucontrol->value.integer.value[0];
if (rt5514->dsp_enabled) {
if (rt5514->pdata.dsp_calib_clk_name &&
!IS_ERR(rt5514->dsp_calib_clk)) {
if (clk_set_rate(rt5514->dsp_calib_clk,
rt5514->pdata.dsp_calib_clk_rate))
dev_err(component->dev,
"Can't set rate for mclk");
if (clk_prepare_enable(rt5514->dsp_calib_clk))
dev_err(component->dev,
"Can't enable dsp_calib_clk");
rt5514_calibration(rt5514, true);
msleep(20);
#if IS_ENABLED(CONFIG_SND_SOC_RT5514_SPI)
rt5514_spi_burst_read(RT5514_PLL3_CALIB_CTRL6 |
RT5514_DSP_MAPPING, buf, sizeof(buf));
#else
dev_err(component->dev, "There is no SPI driver for"
" loading the firmware\n");
memset(buf, 0, sizeof(buf));
#endif
rt5514->pll3_cal_value = buf[0] | buf[1] << 8 |
buf[2] << 16 | buf[3] << 24;
rt5514_calibration(rt5514, false);
clk_disable_unprepare(rt5514->dsp_calib_clk);
}
rt5514_enable_dsp_prepare(rt5514);
request_firmware(&fw, RT5514_FIRMWARE1, component->dev);
if (fw) {
#if IS_ENABLED(CONFIG_SND_SOC_RT5514_SPI)
rt5514_spi_burst_write(0x4ff60000, fw->data,
((fw->size/8)+1)*8);
#else
dev_err(component->dev, "There is no SPI driver for"
" loading the firmware\n");
#endif
release_firmware(fw);
fw = NULL;
}
request_firmware(&fw, RT5514_FIRMWARE2, component->dev);
if (fw) {
#if IS_ENABLED(CONFIG_SND_SOC_RT5514_SPI)
rt5514_spi_burst_write(0x4ffc0000, fw->data,
((fw->size/8)+1)*8);
#else
dev_err(component->dev, "There is no SPI driver for"
" loading the firmware\n");
#endif
release_firmware(fw);
fw = NULL;
}
/* DSP run */
regmap_write(rt5514->i2c_regmap, 0x18002f00,
0x00055148);
if (rt5514->pdata.dsp_calib_clk_name &&
!IS_ERR(rt5514->dsp_calib_clk)) {
msleep(20);
regmap_write(rt5514->i2c_regmap, 0x1800211c,
rt5514->pll3_cal_value);
regmap_write(rt5514->i2c_regmap, 0x18002124,
0x00220012);
regmap_write(rt5514->i2c_regmap, 0x18002124,
0x80220042);
regmap_write(rt5514->i2c_regmap, 0x18002124,
0xe0220042);
}
} else {
regmap_multi_reg_write(rt5514->i2c_regmap,
rt5514_i2c_patch, ARRAY_SIZE(rt5514_i2c_patch));
regcache_mark_dirty(rt5514->regmap);
regcache_sync(rt5514->regmap);
}
}
return 1;
}
static const struct snd_kcontrol_new rt5514_snd_controls[] = {
SOC_DOUBLE_TLV("MIC Boost Volume", RT5514_ANA_CTRL_MICBST,
RT5514_SEL_BSTL_SFT, RT5514_SEL_BSTR_SFT, 8, 0, bst_tlv),
SOC_DOUBLE_R_TLV("ADC1 Capture Volume", RT5514_DOWNFILTER0_CTRL1,
RT5514_DOWNFILTER0_CTRL2, RT5514_AD_GAIN_SFT, 63, 0,
adc_vol_tlv),
SOC_DOUBLE_R_TLV("ADC2 Capture Volume", RT5514_DOWNFILTER1_CTRL1,
RT5514_DOWNFILTER1_CTRL2, RT5514_AD_GAIN_SFT, 63, 0,
adc_vol_tlv),
SOC_SINGLE_EXT("DSP Voice Wake Up", SND_SOC_NOPM, 0, 1, 0,
rt5514_dsp_voice_wake_up_get, rt5514_dsp_voice_wake_up_put),
};
/* ADC Mixer*/
static const struct snd_kcontrol_new rt5514_sto1_adc_l_mix[] = {
SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER0_CTRL1,
RT5514_AD_DMIC_MIX_BIT, 1, 1),
SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER0_CTRL1,
RT5514_AD_AD_MIX_BIT, 1, 1),
};
static const struct snd_kcontrol_new rt5514_sto1_adc_r_mix[] = {
SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER0_CTRL2,
RT5514_AD_DMIC_MIX_BIT, 1, 1),
SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER0_CTRL2,
RT5514_AD_AD_MIX_BIT, 1, 1),
};
static const struct snd_kcontrol_new rt5514_sto2_adc_l_mix[] = {
SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER1_CTRL1,
RT5514_AD_DMIC_MIX_BIT, 1, 1),
SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER1_CTRL1,
RT5514_AD_AD_MIX_BIT, 1, 1),
};
static const struct snd_kcontrol_new rt5514_sto2_adc_r_mix[] = {
SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER1_CTRL2,
RT5514_AD_DMIC_MIX_BIT, 1, 1),
SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER1_CTRL2,
RT5514_AD_AD_MIX_BIT, 1, 1),
};
/* DMIC Source */
static const char * const rt5514_dmic_src[] = {
"DMIC1", "DMIC2"
};
static SOC_ENUM_SINGLE_DECL(
rt5514_stereo1_dmic_enum, RT5514_DIG_SOURCE_CTRL,
RT5514_AD0_DMIC_INPUT_SEL_SFT, rt5514_dmic_src);
static const struct snd_kcontrol_new rt5514_sto1_dmic_mux =
SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5514_stereo1_dmic_enum);
static SOC_ENUM_SINGLE_DECL(
rt5514_stereo2_dmic_enum, RT5514_DIG_SOURCE_CTRL,
RT5514_AD1_DMIC_INPUT_SEL_SFT, rt5514_dmic_src);
static const struct snd_kcontrol_new rt5514_sto2_dmic_mux =
SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5514_stereo2_dmic_enum);
/**
* rt5514_calc_dmic_clk - Calculate the frequency divider parameter of dmic.
*
* @component: only used for dev_warn
* @rate: base clock rate.
*
* Choose divider parameter that gives the highest possible DMIC frequency in
* 1MHz - 3MHz range.
*/
static int rt5514_calc_dmic_clk(struct snd_soc_component *component, int rate)
{
static const int div[] = {2, 3, 4, 8, 12, 16, 24, 32};
int i;
if (rate < 1000000 * div[0]) {
pr_warn("Base clock rate %d is too low\n", rate);
return -EINVAL;
}
for (i = 0; i < ARRAY_SIZE(div); i++) {
/* find divider that gives DMIC frequency below 3.072MHz */
if (3072000 * div[i] >= rate)
return i;
}
dev_warn(component->dev, "Base clock rate %d is too high\n", rate);
return -EINVAL;
}
static int rt5514_set_dmic_clk(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
int idx;
idx = rt5514_calc_dmic_clk(component, rt5514->sysclk);
if (idx < 0)
dev_err(component->dev, "Failed to set DMIC clock\n");
else
regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL1,
RT5514_CLK_DMIC_OUT_SEL_MASK,
idx << RT5514_CLK_DMIC_OUT_SEL_SFT);
if (rt5514->pdata.dmic_init_delay)
msleep(rt5514->pdata.dmic_init_delay);
return idx;
}
static int rt5514_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
if (rt5514->sysclk_src == RT5514_SCLK_S_PLL1)
return 1;
else
return 0;
}
static int rt5514_i2s_use_asrc(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
return (rt5514->sysclk > rt5514->lrck * 384);
}
static const struct snd_soc_dapm_widget rt5514_dapm_widgets[] = {
/* Input Lines */
SND_SOC_DAPM_INPUT("DMIC1L"),
SND_SOC_DAPM_INPUT("DMIC1R"),
SND_SOC_DAPM_INPUT("DMIC2L"),
SND_SOC_DAPM_INPUT("DMIC2R"),
SND_SOC_DAPM_INPUT("AMICL"),
SND_SOC_DAPM_INPUT("AMICR"),
SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DMIC CLK", 1, SND_SOC_NOPM, 0, 0,
rt5514_set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_SUPPLY("ADC CLK", RT5514_CLK_CTRL1,
RT5514_CLK_AD_ANA1_EN_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("LDO18 IN", RT5514_PWR_ANA1,
RT5514_POW_LDO18_IN_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("LDO18 ADC", RT5514_PWR_ANA1,
RT5514_POW_LDO18_ADC_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("LDO21", RT5514_PWR_ANA1, RT5514_POW_LDO21_BIT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("BG LDO18 IN", RT5514_PWR_ANA1,
RT5514_POW_BG_LDO18_IN_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("BG LDO21", RT5514_PWR_ANA1,
RT5514_POW_BG_LDO21_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("BG MBIAS", RT5514_PWR_ANA2,
RT5514_POW_BG_MBIAS_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MBIAS", RT5514_PWR_ANA2, RT5514_POW_MBIAS_BIT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("VREF2", RT5514_PWR_ANA2, RT5514_POW_VREF2_BIT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("VREF1", RT5514_PWR_ANA2, RT5514_POW_VREF1_BIT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC Power", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("LDO16L", RT5514_PWR_ANA2, RT5514_POWL_LDO16_BIT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC1L", RT5514_PWR_ANA2, RT5514_POW_ADC1_L_BIT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("BSTL2", RT5514_PWR_ANA2, RT5514_POW2_BSTL_BIT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("BSTL", RT5514_PWR_ANA2, RT5514_POW_BSTL_BIT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("ADCFEDL", RT5514_PWR_ANA2, RT5514_POW_ADCFEDL_BIT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADCL Power", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("LDO16R", RT5514_PWR_ANA2, RT5514_POWR_LDO16_BIT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC1R", RT5514_PWR_ANA2, RT5514_POW_ADC1_R_BIT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("BSTR2", RT5514_PWR_ANA2, RT5514_POW2_BSTR_BIT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("BSTR", RT5514_PWR_ANA2, RT5514_POW_BSTR_BIT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("ADCFEDR", RT5514_PWR_ANA2, RT5514_POW_ADCFEDR_BIT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADCR Power", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PLL1 LDO ENABLE", RT5514_ANA_CTRL_PLL1_2,
RT5514_EN_LDO_PLL1_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PLL1 LDO", RT5514_PWR_ANA2,
RT5514_POW_PLL1_LDO_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PLL1", RT5514_PWR_ANA2, RT5514_POW_PLL1_BIT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ASRC AD1", 1, RT5514_CLK_CTRL2,
RT5514_CLK_AD0_ASRC_EN_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ASRC AD2", 1, RT5514_CLK_CTRL2,
RT5514_CLK_AD1_ASRC_EN_BIT, 0, NULL, 0),
/* ADC Mux */
SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
&rt5514_sto1_dmic_mux),
SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
&rt5514_sto2_dmic_mux),
/* ADC Mixer */
SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5514_CLK_CTRL1,
RT5514_CLK_AD0_EN_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5514_CLK_CTRL1,
RT5514_CLK_AD1_EN_BIT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
rt5514_sto1_adc_l_mix, ARRAY_SIZE(rt5514_sto1_adc_l_mix)),
SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
rt5514_sto1_adc_r_mix, ARRAY_SIZE(rt5514_sto1_adc_r_mix)),
SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
rt5514_sto2_adc_l_mix, ARRAY_SIZE(rt5514_sto2_adc_l_mix)),
SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
rt5514_sto2_adc_r_mix, ARRAY_SIZE(rt5514_sto2_adc_r_mix)),
SND_SOC_DAPM_ADC("Stereo1 ADC MIXL", NULL, RT5514_DOWNFILTER0_CTRL1,
RT5514_AD_AD_MUTE_BIT, 1),
SND_SOC_DAPM_ADC("Stereo1 ADC MIXR", NULL, RT5514_DOWNFILTER0_CTRL2,
RT5514_AD_AD_MUTE_BIT, 1),
SND_SOC_DAPM_ADC("Stereo2 ADC MIXL", NULL, RT5514_DOWNFILTER1_CTRL1,
RT5514_AD_AD_MUTE_BIT, 1),
SND_SOC_DAPM_ADC("Stereo2 ADC MIXR", NULL, RT5514_DOWNFILTER1_CTRL2,
RT5514_AD_AD_MUTE_BIT, 1),
/* ADC PGA */
SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
/* Audio Interface */
SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
};
static const struct snd_soc_dapm_route rt5514_dapm_routes[] = {
{ "DMIC1", NULL, "DMIC1L" },
{ "DMIC1", NULL, "DMIC1R" },
{ "DMIC2", NULL, "DMIC2L" },
{ "DMIC2", NULL, "DMIC2R" },
{ "DMIC1L", NULL, "DMIC CLK" },
{ "DMIC1R", NULL, "DMIC CLK" },
{ "DMIC2L", NULL, "DMIC CLK" },
{ "DMIC2R", NULL, "DMIC CLK" },
{ "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
{ "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
{ "Sto1 ADC MIXL", "DMIC Switch", "Stereo1 DMIC Mux" },
{ "Sto1 ADC MIXL", "ADC Switch", "AMICL" },
{ "Sto1 ADC MIXR", "DMIC Switch", "Stereo1 DMIC Mux" },
{ "Sto1 ADC MIXR", "ADC Switch", "AMICR" },
{ "ADC Power", NULL, "LDO18 IN" },
{ "ADC Power", NULL, "LDO18 ADC" },
{ "ADC Power", NULL, "LDO21" },
{ "ADC Power", NULL, "BG LDO18 IN" },
{ "ADC Power", NULL, "BG LDO21" },
{ "ADC Power", NULL, "BG MBIAS" },
{ "ADC Power", NULL, "MBIAS" },
{ "ADC Power", NULL, "VREF2" },
{ "ADC Power", NULL, "VREF1" },
{ "ADCL Power", NULL, "LDO16L" },
{ "ADCL Power", NULL, "ADC1L" },
{ "ADCL Power", NULL, "BSTL2" },
{ "ADCL Power", NULL, "BSTL" },
{ "ADCL Power", NULL, "ADCFEDL" },
{ "ADCR Power", NULL, "LDO16R" },
{ "ADCR Power", NULL, "ADC1R" },
{ "ADCR Power", NULL, "BSTR2" },
{ "ADCR Power", NULL, "BSTR" },
{ "ADCR Power", NULL, "ADCFEDR" },
{ "AMICL", NULL, "ADC CLK" },
{ "AMICL", NULL, "ADC Power" },
{ "AMICL", NULL, "ADCL Power" },
{ "AMICR", NULL, "ADC CLK" },
{ "AMICR", NULL, "ADC Power" },
{ "AMICR", NULL, "ADCR Power" },
{ "PLL1 LDO", NULL, "PLL1 LDO ENABLE" },
{ "PLL1", NULL, "PLL1 LDO" },
{ "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
{ "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
{ "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
{ "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
{ "Stereo1 ADC MIX", NULL, "adc stereo1 filter" },
{ "adc stereo1 filter", NULL, "PLL1", rt5514_is_sys_clk_from_pll },
{ "adc stereo1 filter", NULL, "ASRC AD1", rt5514_i2s_use_asrc },
{ "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
{ "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
{ "Sto2 ADC MIXL", "DMIC Switch", "Stereo2 DMIC Mux" },
{ "Sto2 ADC MIXL", "ADC Switch", "AMICL" },
{ "Sto2 ADC MIXR", "DMIC Switch", "Stereo2 DMIC Mux" },
{ "Sto2 ADC MIXR", "ADC Switch", "AMICR" },
{ "Stereo2 ADC MIXL", NULL, "Sto2 ADC MIXL" },
{ "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
{ "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
{ "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
{ "Stereo2 ADC MIX", NULL, "adc stereo2 filter" },
{ "adc stereo2 filter", NULL, "PLL1", rt5514_is_sys_clk_from_pll },
{ "adc stereo2 filter", NULL, "ASRC AD2", rt5514_i2s_use_asrc },
{ "AIF1TX", NULL, "Stereo1 ADC MIX"},
{ "AIF1TX", NULL, "Stereo2 ADC MIX"},
};
static int rt5514_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
int pre_div, bclk_ms, frame_size;
unsigned int val_len = 0;
rt5514->lrck = params_rate(params);
pre_div = rl6231_get_clk_info(rt5514->sysclk, rt5514->lrck);
if (pre_div < 0) {
dev_err(component->dev, "Unsupported clock setting\n");
return -EINVAL;
}
frame_size = snd_soc_params_to_frame_size(params);
if (frame_size < 0) {
dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
return -EINVAL;
}
bclk_ms = frame_size > 32;
rt5514->bclk = rt5514->lrck * (32 << bclk_ms);
dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
rt5514->bclk, rt5514->lrck);
dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
bclk_ms, pre_div, dai->id);
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
break;
case SNDRV_PCM_FORMAT_S20_3LE:
val_len = RT5514_I2S_DL_20;
break;
case SNDRV_PCM_FORMAT_S24_LE:
val_len = RT5514_I2S_DL_24;
break;
case SNDRV_PCM_FORMAT_S8:
val_len = RT5514_I2S_DL_8;
break;
default:
return -EINVAL;
}
regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL1, RT5514_I2S_DL_MASK,
val_len);
regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL1,
RT5514_CLK_AD_ANA1_SEL_MASK,
(pre_div + 1) << RT5514_CLK_AD_ANA1_SEL_SFT);
regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL2,
RT5514_CLK_SYS_DIV_OUT_MASK | RT5514_SEL_ADC_OSR_MASK,
pre_div << RT5514_CLK_SYS_DIV_OUT_SFT |
pre_div << RT5514_SEL_ADC_OSR_SFT);
return 0;
}
static int rt5514_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0;
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_NB_IF:
reg_val |= RT5514_I2S_LR_INV;
break;
case SND_SOC_DAIFMT_IB_NF:
reg_val |= RT5514_I2S_BP_INV;
break;
case SND_SOC_DAIFMT_IB_IF:
reg_val |= RT5514_I2S_BP_INV | RT5514_I2S_LR_INV;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_LEFT_J:
reg_val |= RT5514_I2S_DF_LEFT;
break;
case SND_SOC_DAIFMT_DSP_A:
reg_val |= RT5514_I2S_DF_PCM_A;
break;
case SND_SOC_DAIFMT_DSP_B:
reg_val |= RT5514_I2S_DF_PCM_B;
break;
default:
return -EINVAL;
}
regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL1,
RT5514_I2S_DF_MASK | RT5514_I2S_BP_MASK | RT5514_I2S_LR_MASK,
reg_val);
return 0;
}
static int rt5514_set_dai_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0;
if (freq == rt5514->sysclk && clk_id == rt5514->sysclk_src)
return 0;
switch (clk_id) {
case RT5514_SCLK_S_MCLK:
reg_val |= RT5514_CLK_SYS_PRE_SEL_MCLK;
break;
case RT5514_SCLK_S_PLL1:
reg_val |= RT5514_CLK_SYS_PRE_SEL_PLL;
break;
default:
dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
return -EINVAL;
}
regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL2,
RT5514_CLK_SYS_PRE_SEL_MASK, reg_val);
rt5514->sysclk = freq;
rt5514->sysclk_src = clk_id;
dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
return 0;
}
static int rt5514_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
unsigned int freq_in, unsigned int freq_out)
{
struct snd_soc_component *component = dai->component;
struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
struct rl6231_pll_code pll_code;
int ret;
if (!freq_in || !freq_out) {
dev_dbg(component->dev, "PLL disabled\n");
rt5514->pll_in = 0;
rt5514->pll_out = 0;
regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL2,
RT5514_CLK_SYS_PRE_SEL_MASK,
RT5514_CLK_SYS_PRE_SEL_MCLK);
return 0;
}
if (source == rt5514->pll_src && freq_in == rt5514->pll_in &&
freq_out == rt5514->pll_out)
return 0;
switch (source) {
case RT5514_PLL1_S_MCLK:
regmap_update_bits(rt5514->regmap, RT5514_PLL_SOURCE_CTRL,
RT5514_PLL_1_SEL_MASK, RT5514_PLL_1_SEL_MCLK);
break;
case RT5514_PLL1_S_BCLK:
regmap_update_bits(rt5514->regmap, RT5514_PLL_SOURCE_CTRL,
RT5514_PLL_1_SEL_MASK, RT5514_PLL_1_SEL_SCLK);
break;
default:
dev_err(component->dev, "Unknown PLL source %d\n", source);
return -EINVAL;
}
ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
if (ret < 0) {
dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
return ret;
}
dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
pll_code.n_code, pll_code.k_code);
regmap_write(rt5514->regmap, RT5514_ANA_CTRL_PLL1_1,
pll_code.k_code << RT5514_PLL_K_SFT |
pll_code.n_code << RT5514_PLL_N_SFT |
(pll_code.m_bp ? 0 : pll_code.m_code) << RT5514_PLL_M_SFT);
regmap_update_bits(rt5514->regmap, RT5514_ANA_CTRL_PLL1_2,
RT5514_PLL_M_BP, pll_code.m_bp << RT5514_PLL_M_BP_SFT);
rt5514->pll_in = freq_in;
rt5514->pll_out = freq_out;
rt5514->pll_src = source;
return 0;
}
static int rt5514_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
unsigned int val = 0, val2 = 0;
if (rx_mask || tx_mask)
val |= RT5514_TDM_MODE;
switch (tx_mask) {
case 0x3:
val2 |= RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH2 |
RT5514_TDM_DOCKING_START_SLOT0;
break;
case 0x30:
val2 |= RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH2 |
RT5514_TDM_DOCKING_START_SLOT4;
break;
case 0xf:
val2 |= RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH4 |
RT5514_TDM_DOCKING_START_SLOT0;
break;
case 0xf0:
val2 |= RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH4 |
RT5514_TDM_DOCKING_START_SLOT4;
break;
default:
break;
}
switch (slots) {
case 4:
val |= RT5514_TDMSLOT_SEL_RX_4CH | RT5514_TDMSLOT_SEL_TX_4CH;
break;
case 6:
val |= RT5514_TDMSLOT_SEL_RX_6CH | RT5514_TDMSLOT_SEL_TX_6CH;
break;
case 8:
val |= RT5514_TDMSLOT_SEL_RX_8CH | RT5514_TDMSLOT_SEL_TX_8CH;
break;
case 2:
default:
break;
}
switch (slot_width) {
case 20:
val |= RT5514_CH_LEN_RX_20 | RT5514_CH_LEN_TX_20;
break;
case 24:
val |= RT5514_CH_LEN_RX_24 | RT5514_CH_LEN_TX_24;
break;
case 25:
val |= RT5514_TDM_MODE2;
break;
case 32:
val |= RT5514_CH_LEN_RX_32 | RT5514_CH_LEN_TX_32;
break;
case 16:
default:
break;
}
regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL1, RT5514_TDM_MODE |
RT5514_TDMSLOT_SEL_RX_MASK | RT5514_TDMSLOT_SEL_TX_MASK |
RT5514_CH_LEN_RX_MASK | RT5514_CH_LEN_TX_MASK |
RT5514_TDM_MODE2, val);
regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL2,
RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH_MASK |
RT5514_TDM_DOCKING_START_MASK, val2);
return 0;
}
static int rt5514_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
int ret;
switch (level) {
case SND_SOC_BIAS_PREPARE:
if (IS_ERR(rt5514->mclk))
break;
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) {
clk_disable_unprepare(rt5514->mclk);
} else {
ret = clk_prepare_enable(rt5514->mclk);
if (ret)
return ret;
}
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
/*
* If the DSP is enabled in start of recording, the DSP
* should be disabled, and sync back to normal recording
* settings to make sure recording properly.
*/
if (rt5514->dsp_enabled) {
rt5514->dsp_enabled = 0;
regmap_multi_reg_write(rt5514->i2c_regmap,
rt5514_i2c_patch,
ARRAY_SIZE(rt5514_i2c_patch));
regcache_mark_dirty(rt5514->regmap);
regcache_sync(rt5514->regmap);
}
}
break;
default:
break;
}
return 0;
}
static int rt5514_probe(struct snd_soc_component *component)
{
struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
struct platform_device *pdev = container_of(component->dev,
struct platform_device, dev);
rt5514->mclk = devm_clk_get(component->dev, "mclk");
if (PTR_ERR(rt5514->mclk) == -EPROBE_DEFER)
return -EPROBE_DEFER;
if (rt5514->pdata.dsp_calib_clk_name) {
rt5514->dsp_calib_clk = devm_clk_get(&pdev->dev,
rt5514->pdata.dsp_calib_clk_name);
if (PTR_ERR(rt5514->dsp_calib_clk) == -EPROBE_DEFER)
return -EPROBE_DEFER;
}
rt5514->component = component;
rt5514->pll3_cal_value = 0x0078b000;
return 0;
}
static int rt5514_i2c_read(void *context, unsigned int reg, unsigned int *val)
{
struct i2c_client *client = context;
struct rt5514_priv *rt5514 = i2c_get_clientdata(client);
regmap_read(rt5514->i2c_regmap, reg | RT5514_DSP_MAPPING, val);
return 0;
}
static int rt5514_i2c_write(void *context, unsigned int reg, unsigned int val)
{
struct i2c_client *client = context;
struct rt5514_priv *rt5514 = i2c_get_clientdata(client);
regmap_write(rt5514->i2c_regmap, reg | RT5514_DSP_MAPPING, val);
return 0;
}
#define RT5514_STEREO_RATES SNDRV_PCM_RATE_8000_192000
#define RT5514_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
static const struct snd_soc_dai_ops rt5514_aif_dai_ops = {
.hw_params = rt5514_hw_params,
.set_fmt = rt5514_set_dai_fmt,
.set_sysclk = rt5514_set_dai_sysclk,
.set_pll = rt5514_set_dai_pll,
.set_tdm_slot = rt5514_set_tdm_slot,
};
static struct snd_soc_dai_driver rt5514_dai[] = {
{
.name = "rt5514-aif1",
.id = 0,
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 1,
.channels_max = 4,
.rates = RT5514_STEREO_RATES,
.formats = RT5514_FORMATS,
},
.ops = &rt5514_aif_dai_ops,
}
};
static const struct snd_soc_component_driver soc_component_dev_rt5514 = {
.probe = rt5514_probe,
.set_bias_level = rt5514_set_bias_level,
.controls = rt5514_snd_controls,
.num_controls = ARRAY_SIZE(rt5514_snd_controls),
.dapm_widgets = rt5514_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt5514_dapm_widgets),
.dapm_routes = rt5514_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(rt5514_dapm_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config rt5514_i2c_regmap = {
.name = "i2c",
.reg_bits = 32,
.val_bits = 32,
.readable_reg = rt5514_i2c_readable_register,
.cache_type = REGCACHE_NONE,
};
static const struct regmap_config rt5514_regmap = {
.reg_bits = 16,
.val_bits = 32,
.max_register = RT5514_VENDOR_ID2,
.volatile_reg = rt5514_volatile_register,
.readable_reg = rt5514_readable_register,
.reg_read = rt5514_i2c_read,
.reg_write = rt5514_i2c_write,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = rt5514_reg,
.num_reg_defaults = ARRAY_SIZE(rt5514_reg),
.use_single_read = true,
.use_single_write = true,
};
static const struct i2c_device_id rt5514_i2c_id[] = {
{ "rt5514", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, rt5514_i2c_id);
#if defined(CONFIG_OF)
static const struct of_device_id rt5514_of_match[] = {
{ .compatible = "realtek,rt5514", },
{},
};
MODULE_DEVICE_TABLE(of, rt5514_of_match);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id rt5514_acpi_match[] = {
{ "10EC5514", 0},
{},
};
MODULE_DEVICE_TABLE(acpi, rt5514_acpi_match);
#endif
static int rt5514_parse_dp(struct rt5514_priv *rt5514, struct device *dev)
{
device_property_read_u32(dev, "realtek,dmic-init-delay-ms",
&rt5514->pdata.dmic_init_delay);
device_property_read_string(dev, "realtek,dsp-calib-clk-name",
&rt5514->pdata.dsp_calib_clk_name);
device_property_read_u32(dev, "realtek,dsp-calib-clk-rate",
&rt5514->pdata.dsp_calib_clk_rate);
return 0;
}
static __maybe_unused int rt5514_i2c_resume(struct device *dev)
{
struct rt5514_priv *rt5514 = dev_get_drvdata(dev);
unsigned int val;
/*
* Add a bogus read to avoid rt5514's confusion after s2r in case it
* saw glitches on the i2c lines and thought the other side sent a
* start bit.
*/
regmap_read(rt5514->regmap, RT5514_VENDOR_ID2, &val);
return 0;
}
static int rt5514_i2c_probe(struct i2c_client *i2c)
{
struct rt5514_platform_data *pdata = dev_get_platdata(&i2c->dev);
struct rt5514_priv *rt5514;
int ret;
unsigned int val = ~0;
rt5514 = devm_kzalloc(&i2c->dev, sizeof(struct rt5514_priv),
GFP_KERNEL);
if (rt5514 == NULL)
return -ENOMEM;
i2c_set_clientdata(i2c, rt5514);
if (pdata)
rt5514->pdata = *pdata;
else
rt5514_parse_dp(rt5514, &i2c->dev);
rt5514->i2c_regmap = devm_regmap_init_i2c(i2c, &rt5514_i2c_regmap);
if (IS_ERR(rt5514->i2c_regmap)) {
ret = PTR_ERR(rt5514->i2c_regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
rt5514->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5514_regmap);
if (IS_ERR(rt5514->regmap)) {
ret = PTR_ERR(rt5514->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
/*
* The rt5514 can get confused if the i2c lines glitch together, as
* can happen at bootup as regulators are turned off and on. If it's
* in this glitched state the first i2c read will fail, so we'll give
* it one change to retry.
*/
ret = regmap_read(rt5514->regmap, RT5514_VENDOR_ID2, &val);
if (ret || val != RT5514_DEVICE_ID)
ret = regmap_read(rt5514->regmap, RT5514_VENDOR_ID2, &val);
if (ret || val != RT5514_DEVICE_ID) {
dev_err(&i2c->dev,
"Device with ID register %x is not rt5514\n", val);
return -ENODEV;
}
ret = regmap_multi_reg_write(rt5514->i2c_regmap, rt5514_i2c_patch,
ARRAY_SIZE(rt5514_i2c_patch));
if (ret != 0)
dev_warn(&i2c->dev, "Failed to apply i2c_regmap patch: %d\n",
ret);
ret = regmap_register_patch(rt5514->regmap, rt5514_patch,
ARRAY_SIZE(rt5514_patch));
if (ret != 0)
dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
return devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_rt5514,
rt5514_dai, ARRAY_SIZE(rt5514_dai));
}
static const struct dev_pm_ops rt5514_i2_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(NULL, rt5514_i2c_resume)
};
static struct i2c_driver rt5514_i2c_driver = {
.driver = {
.name = "rt5514",
.acpi_match_table = ACPI_PTR(rt5514_acpi_match),
.of_match_table = of_match_ptr(rt5514_of_match),
.pm = &rt5514_i2_pm_ops,
},
.probe = rt5514_i2c_probe,
.id_table = rt5514_i2c_id,
};
module_i2c_driver(rt5514_i2c_driver);
MODULE_DESCRIPTION("ASoC RT5514 driver");
MODULE_AUTHOR("Oder Chiou <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/rt5514.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// sdw-mockup.c -- a mockup SoundWire codec for tests where only the host
// drives the bus.
//
// Copyright(c) 2021 Intel Corporation
//
//
#include <linux/device.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/soundwire/sdw.h>
#include <linux/soundwire/sdw_type.h>
#include <linux/soundwire/sdw_registers.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/sdw.h>
#include <sound/soc.h>
struct sdw_mockup_priv {
struct sdw_slave *slave;
};
static int sdw_mockup_component_probe(struct snd_soc_component *component)
{
return 0;
}
static void sdw_mockup_component_remove(struct snd_soc_component *component)
{
}
static const struct snd_soc_component_driver snd_soc_sdw_mockup_component = {
.probe = sdw_mockup_component_probe,
.remove = sdw_mockup_component_remove,
.endianness = 1,
};
static int sdw_mockup_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
int direction)
{
snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
return 0;
}
static void sdw_mockup_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
snd_soc_dai_set_dma_data(dai, substream, NULL);
}
static int sdw_mockup_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct sdw_mockup_priv *sdw_mockup = snd_soc_component_get_drvdata(component);
struct sdw_stream_config stream_config = {0};
struct sdw_port_config port_config = {0};
struct sdw_stream_runtime *sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
int ret;
if (!sdw_stream)
return -EINVAL;
if (!sdw_mockup->slave)
return -EINVAL;
/* SoundWire specific configuration */
snd_sdw_params_to_config(substream, params, &stream_config, &port_config);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
port_config.num = 1;
else
port_config.num = 8;
ret = sdw_stream_add_slave(sdw_mockup->slave, &stream_config,
&port_config, 1, sdw_stream);
if (ret)
dev_err(dai->dev, "Unable to configure port\n");
return ret;
}
static int sdw_mockup_pcm_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct sdw_mockup_priv *sdw_mockup = snd_soc_component_get_drvdata(component);
struct sdw_stream_runtime *sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
if (!sdw_mockup->slave)
return -EINVAL;
sdw_stream_remove_slave(sdw_mockup->slave, sdw_stream);
return 0;
}
static const struct snd_soc_dai_ops sdw_mockup_ops = {
.hw_params = sdw_mockup_pcm_hw_params,
.hw_free = sdw_mockup_pcm_hw_free,
.set_stream = sdw_mockup_set_sdw_stream,
.shutdown = sdw_mockup_shutdown,
};
static struct snd_soc_dai_driver sdw_mockup_dai[] = {
{
.name = "sdw-mockup-aif1",
.id = 1,
.playback = {
.stream_name = "DP1 Playback",
.channels_min = 1,
.channels_max = 2,
},
.capture = {
.stream_name = "DP8 Capture",
.channels_min = 1,
.channels_max = 2,
},
.ops = &sdw_mockup_ops,
},
};
static int sdw_mockup_update_status(struct sdw_slave *slave,
enum sdw_slave_status status)
{
return 0;
}
static int sdw_mockup_read_prop(struct sdw_slave *slave)
{
struct sdw_slave_prop *prop = &slave->prop;
int nval;
int i, j;
u32 bit;
unsigned long addr;
struct sdw_dpn_prop *dpn;
prop->paging_support = false;
/*
* first we need to allocate memory for set bits in port lists
* the port allocation is completely arbitrary:
* DP0 is not supported
* DP1 is sink
* DP8 is source
*/
prop->source_ports = BIT(8);
prop->sink_ports = BIT(1);
nval = hweight32(prop->source_ports);
prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
sizeof(*prop->src_dpn_prop),
GFP_KERNEL);
if (!prop->src_dpn_prop)
return -ENOMEM;
i = 0;
dpn = prop->src_dpn_prop;
addr = prop->source_ports;
for_each_set_bit(bit, &addr, 32) {
dpn[i].num = bit;
dpn[i].type = SDW_DPN_FULL;
dpn[i].simple_ch_prep_sm = true;
i++;
}
/* do this again for sink now */
nval = hweight32(prop->sink_ports);
prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
sizeof(*prop->sink_dpn_prop),
GFP_KERNEL);
if (!prop->sink_dpn_prop)
return -ENOMEM;
j = 0;
dpn = prop->sink_dpn_prop;
addr = prop->sink_ports;
for_each_set_bit(bit, &addr, 32) {
dpn[j].num = bit;
dpn[j].type = SDW_DPN_FULL;
dpn[j].simple_ch_prep_sm = true;
j++;
}
prop->simple_clk_stop_capable = true;
/* wake-up event */
prop->wake_capable = 0;
return 0;
}
static int sdw_mockup_bus_config(struct sdw_slave *slave,
struct sdw_bus_params *params)
{
return 0;
}
static int sdw_mockup_interrupt_callback(struct sdw_slave *slave,
struct sdw_slave_intr_status *status)
{
return 0;
}
static const struct sdw_slave_ops sdw_mockup_slave_ops = {
.read_prop = sdw_mockup_read_prop,
.interrupt_callback = sdw_mockup_interrupt_callback,
.update_status = sdw_mockup_update_status,
.bus_config = sdw_mockup_bus_config,
};
static int sdw_mockup_sdw_probe(struct sdw_slave *slave,
const struct sdw_device_id *id)
{
struct device *dev = &slave->dev;
struct sdw_mockup_priv *sdw_mockup;
int ret;
sdw_mockup = devm_kzalloc(dev, sizeof(*sdw_mockup), GFP_KERNEL);
if (!sdw_mockup)
return -ENOMEM;
dev_set_drvdata(dev, sdw_mockup);
sdw_mockup->slave = slave;
slave->is_mockup_device = true;
ret = devm_snd_soc_register_component(dev,
&snd_soc_sdw_mockup_component,
sdw_mockup_dai,
ARRAY_SIZE(sdw_mockup_dai));
return ret;
}
static int sdw_mockup_sdw_remove(struct sdw_slave *slave)
{
return 0;
}
/*
* Intel reserved parts ID with the following mapping expected:
* 0xAAAA: generic full-duplex codec
* 0xAA55: headset codec (mock-up of RT711/RT5682) - full-duplex
* 0x55AA: amplifier (mock-up of RT1308/Maxim 98373) - playback only with
* IV feedback
* 0x5555: mic codec (mock-up of RT715) - capture-only
*/
static const struct sdw_device_id sdw_mockup_id[] = {
SDW_SLAVE_ENTRY_EXT(0x0105, 0xAAAA, 0x0, 0, 0),
SDW_SLAVE_ENTRY_EXT(0x0105, 0xAA55, 0x0, 0, 0),
SDW_SLAVE_ENTRY_EXT(0x0105, 0x55AA, 0x0, 0, 0),
SDW_SLAVE_ENTRY_EXT(0x0105, 0x5555, 0x0, 0, 0),
{},
};
MODULE_DEVICE_TABLE(sdw, sdw_mockup_id);
static struct sdw_driver sdw_mockup_sdw_driver = {
.driver = {
.name = "sdw-mockup",
.owner = THIS_MODULE,
},
.probe = sdw_mockup_sdw_probe,
.remove = sdw_mockup_sdw_remove,
.ops = &sdw_mockup_slave_ops,
.id_table = sdw_mockup_id,
};
module_sdw_driver(sdw_mockup_sdw_driver);
MODULE_DESCRIPTION("ASoC SDW mockup codec driver");
MODULE_AUTHOR("Pierre-Louis Bossart <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/sdw-mockup.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* max98088.c -- MAX98088 ALSA SoC Audio driver
*
* Copyright 2010 Maxim Integrated Products
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/clk.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <linux/slab.h>
#include <asm/div64.h>
#include <sound/max98088.h>
#include "max98088.h"
enum max98088_type {
MAX98088,
MAX98089,
};
struct max98088_cdata {
unsigned int rate;
unsigned int fmt;
int eq_sel;
};
struct max98088_priv {
struct regmap *regmap;
enum max98088_type devtype;
struct max98088_pdata *pdata;
struct clk *mclk;
unsigned char mclk_prescaler;
unsigned int sysclk;
struct max98088_cdata dai[2];
int eq_textcnt;
const char **eq_texts;
struct soc_enum eq_enum;
u8 ina_state;
u8 inb_state;
unsigned int ex_mode;
unsigned int digmic;
unsigned int mic1pre;
unsigned int mic2pre;
unsigned int extmic_mode;
};
static const struct reg_default max98088_reg[] = {
{ 0xf, 0x00 }, /* 0F interrupt enable */
{ 0x10, 0x00 }, /* 10 master clock */
{ 0x11, 0x00 }, /* 11 DAI1 clock mode */
{ 0x12, 0x00 }, /* 12 DAI1 clock control */
{ 0x13, 0x00 }, /* 13 DAI1 clock control */
{ 0x14, 0x00 }, /* 14 DAI1 format */
{ 0x15, 0x00 }, /* 15 DAI1 clock */
{ 0x16, 0x00 }, /* 16 DAI1 config */
{ 0x17, 0x00 }, /* 17 DAI1 TDM */
{ 0x18, 0x00 }, /* 18 DAI1 filters */
{ 0x19, 0x00 }, /* 19 DAI2 clock mode */
{ 0x1a, 0x00 }, /* 1A DAI2 clock control */
{ 0x1b, 0x00 }, /* 1B DAI2 clock control */
{ 0x1c, 0x00 }, /* 1C DAI2 format */
{ 0x1d, 0x00 }, /* 1D DAI2 clock */
{ 0x1e, 0x00 }, /* 1E DAI2 config */
{ 0x1f, 0x00 }, /* 1F DAI2 TDM */
{ 0x20, 0x00 }, /* 20 DAI2 filters */
{ 0x21, 0x00 }, /* 21 data config */
{ 0x22, 0x00 }, /* 22 DAC mixer */
{ 0x23, 0x00 }, /* 23 left ADC mixer */
{ 0x24, 0x00 }, /* 24 right ADC mixer */
{ 0x25, 0x00 }, /* 25 left HP mixer */
{ 0x26, 0x00 }, /* 26 right HP mixer */
{ 0x27, 0x00 }, /* 27 HP control */
{ 0x28, 0x00 }, /* 28 left REC mixer */
{ 0x29, 0x00 }, /* 29 right REC mixer */
{ 0x2a, 0x00 }, /* 2A REC control */
{ 0x2b, 0x00 }, /* 2B left SPK mixer */
{ 0x2c, 0x00 }, /* 2C right SPK mixer */
{ 0x2d, 0x00 }, /* 2D SPK control */
{ 0x2e, 0x00 }, /* 2E sidetone */
{ 0x2f, 0x00 }, /* 2F DAI1 playback level */
{ 0x30, 0x00 }, /* 30 DAI1 playback level */
{ 0x31, 0x00 }, /* 31 DAI2 playback level */
{ 0x32, 0x00 }, /* 32 DAI2 playbakc level */
{ 0x33, 0x00 }, /* 33 left ADC level */
{ 0x34, 0x00 }, /* 34 right ADC level */
{ 0x35, 0x00 }, /* 35 MIC1 level */
{ 0x36, 0x00 }, /* 36 MIC2 level */
{ 0x37, 0x00 }, /* 37 INA level */
{ 0x38, 0x00 }, /* 38 INB level */
{ 0x39, 0x00 }, /* 39 left HP volume */
{ 0x3a, 0x00 }, /* 3A right HP volume */
{ 0x3b, 0x00 }, /* 3B left REC volume */
{ 0x3c, 0x00 }, /* 3C right REC volume */
{ 0x3d, 0x00 }, /* 3D left SPK volume */
{ 0x3e, 0x00 }, /* 3E right SPK volume */
{ 0x3f, 0x00 }, /* 3F MIC config */
{ 0x40, 0x00 }, /* 40 MIC threshold */
{ 0x41, 0x00 }, /* 41 excursion limiter filter */
{ 0x42, 0x00 }, /* 42 excursion limiter threshold */
{ 0x43, 0x00 }, /* 43 ALC */
{ 0x44, 0x00 }, /* 44 power limiter threshold */
{ 0x45, 0x00 }, /* 45 power limiter config */
{ 0x46, 0x00 }, /* 46 distortion limiter config */
{ 0x47, 0x00 }, /* 47 audio input */
{ 0x48, 0x00 }, /* 48 microphone */
{ 0x49, 0x00 }, /* 49 level control */
{ 0x4a, 0x00 }, /* 4A bypass switches */
{ 0x4b, 0x00 }, /* 4B jack detect */
{ 0x4c, 0x00 }, /* 4C input enable */
{ 0x4d, 0x00 }, /* 4D output enable */
{ 0x4e, 0xF0 }, /* 4E bias control */
{ 0x4f, 0x00 }, /* 4F DAC power */
{ 0x50, 0x0F }, /* 50 DAC power */
{ 0x51, 0x00 }, /* 51 system */
{ 0x52, 0x00 }, /* 52 DAI1 EQ1 */
{ 0x53, 0x00 }, /* 53 DAI1 EQ1 */
{ 0x54, 0x00 }, /* 54 DAI1 EQ1 */
{ 0x55, 0x00 }, /* 55 DAI1 EQ1 */
{ 0x56, 0x00 }, /* 56 DAI1 EQ1 */
{ 0x57, 0x00 }, /* 57 DAI1 EQ1 */
{ 0x58, 0x00 }, /* 58 DAI1 EQ1 */
{ 0x59, 0x00 }, /* 59 DAI1 EQ1 */
{ 0x5a, 0x00 }, /* 5A DAI1 EQ1 */
{ 0x5b, 0x00 }, /* 5B DAI1 EQ1 */
{ 0x5c, 0x00 }, /* 5C DAI1 EQ2 */
{ 0x5d, 0x00 }, /* 5D DAI1 EQ2 */
{ 0x5e, 0x00 }, /* 5E DAI1 EQ2 */
{ 0x5f, 0x00 }, /* 5F DAI1 EQ2 */
{ 0x60, 0x00 }, /* 60 DAI1 EQ2 */
{ 0x61, 0x00 }, /* 61 DAI1 EQ2 */
{ 0x62, 0x00 }, /* 62 DAI1 EQ2 */
{ 0x63, 0x00 }, /* 63 DAI1 EQ2 */
{ 0x64, 0x00 }, /* 64 DAI1 EQ2 */
{ 0x65, 0x00 }, /* 65 DAI1 EQ2 */
{ 0x66, 0x00 }, /* 66 DAI1 EQ3 */
{ 0x67, 0x00 }, /* 67 DAI1 EQ3 */
{ 0x68, 0x00 }, /* 68 DAI1 EQ3 */
{ 0x69, 0x00 }, /* 69 DAI1 EQ3 */
{ 0x6a, 0x00 }, /* 6A DAI1 EQ3 */
{ 0x6b, 0x00 }, /* 6B DAI1 EQ3 */
{ 0x6c, 0x00 }, /* 6C DAI1 EQ3 */
{ 0x6d, 0x00 }, /* 6D DAI1 EQ3 */
{ 0x6e, 0x00 }, /* 6E DAI1 EQ3 */
{ 0x6f, 0x00 }, /* 6F DAI1 EQ3 */
{ 0x70, 0x00 }, /* 70 DAI1 EQ4 */
{ 0x71, 0x00 }, /* 71 DAI1 EQ4 */
{ 0x72, 0x00 }, /* 72 DAI1 EQ4 */
{ 0x73, 0x00 }, /* 73 DAI1 EQ4 */
{ 0x74, 0x00 }, /* 74 DAI1 EQ4 */
{ 0x75, 0x00 }, /* 75 DAI1 EQ4 */
{ 0x76, 0x00 }, /* 76 DAI1 EQ4 */
{ 0x77, 0x00 }, /* 77 DAI1 EQ4 */
{ 0x78, 0x00 }, /* 78 DAI1 EQ4 */
{ 0x79, 0x00 }, /* 79 DAI1 EQ4 */
{ 0x7a, 0x00 }, /* 7A DAI1 EQ5 */
{ 0x7b, 0x00 }, /* 7B DAI1 EQ5 */
{ 0x7c, 0x00 }, /* 7C DAI1 EQ5 */
{ 0x7d, 0x00 }, /* 7D DAI1 EQ5 */
{ 0x7e, 0x00 }, /* 7E DAI1 EQ5 */
{ 0x7f, 0x00 }, /* 7F DAI1 EQ5 */
{ 0x80, 0x00 }, /* 80 DAI1 EQ5 */
{ 0x81, 0x00 }, /* 81 DAI1 EQ5 */
{ 0x82, 0x00 }, /* 82 DAI1 EQ5 */
{ 0x83, 0x00 }, /* 83 DAI1 EQ5 */
{ 0x84, 0x00 }, /* 84 DAI2 EQ1 */
{ 0x85, 0x00 }, /* 85 DAI2 EQ1 */
{ 0x86, 0x00 }, /* 86 DAI2 EQ1 */
{ 0x87, 0x00 }, /* 87 DAI2 EQ1 */
{ 0x88, 0x00 }, /* 88 DAI2 EQ1 */
{ 0x89, 0x00 }, /* 89 DAI2 EQ1 */
{ 0x8a, 0x00 }, /* 8A DAI2 EQ1 */
{ 0x8b, 0x00 }, /* 8B DAI2 EQ1 */
{ 0x8c, 0x00 }, /* 8C DAI2 EQ1 */
{ 0x8d, 0x00 }, /* 8D DAI2 EQ1 */
{ 0x8e, 0x00 }, /* 8E DAI2 EQ2 */
{ 0x8f, 0x00 }, /* 8F DAI2 EQ2 */
{ 0x90, 0x00 }, /* 90 DAI2 EQ2 */
{ 0x91, 0x00 }, /* 91 DAI2 EQ2 */
{ 0x92, 0x00 }, /* 92 DAI2 EQ2 */
{ 0x93, 0x00 }, /* 93 DAI2 EQ2 */
{ 0x94, 0x00 }, /* 94 DAI2 EQ2 */
{ 0x95, 0x00 }, /* 95 DAI2 EQ2 */
{ 0x96, 0x00 }, /* 96 DAI2 EQ2 */
{ 0x97, 0x00 }, /* 97 DAI2 EQ2 */
{ 0x98, 0x00 }, /* 98 DAI2 EQ3 */
{ 0x99, 0x00 }, /* 99 DAI2 EQ3 */
{ 0x9a, 0x00 }, /* 9A DAI2 EQ3 */
{ 0x9b, 0x00 }, /* 9B DAI2 EQ3 */
{ 0x9c, 0x00 }, /* 9C DAI2 EQ3 */
{ 0x9d, 0x00 }, /* 9D DAI2 EQ3 */
{ 0x9e, 0x00 }, /* 9E DAI2 EQ3 */
{ 0x9f, 0x00 }, /* 9F DAI2 EQ3 */
{ 0xa0, 0x00 }, /* A0 DAI2 EQ3 */
{ 0xa1, 0x00 }, /* A1 DAI2 EQ3 */
{ 0xa2, 0x00 }, /* A2 DAI2 EQ4 */
{ 0xa3, 0x00 }, /* A3 DAI2 EQ4 */
{ 0xa4, 0x00 }, /* A4 DAI2 EQ4 */
{ 0xa5, 0x00 }, /* A5 DAI2 EQ4 */
{ 0xa6, 0x00 }, /* A6 DAI2 EQ4 */
{ 0xa7, 0x00 }, /* A7 DAI2 EQ4 */
{ 0xa8, 0x00 }, /* A8 DAI2 EQ4 */
{ 0xa9, 0x00 }, /* A9 DAI2 EQ4 */
{ 0xaa, 0x00 }, /* AA DAI2 EQ4 */
{ 0xab, 0x00 }, /* AB DAI2 EQ4 */
{ 0xac, 0x00 }, /* AC DAI2 EQ5 */
{ 0xad, 0x00 }, /* AD DAI2 EQ5 */
{ 0xae, 0x00 }, /* AE DAI2 EQ5 */
{ 0xaf, 0x00 }, /* AF DAI2 EQ5 */
{ 0xb0, 0x00 }, /* B0 DAI2 EQ5 */
{ 0xb1, 0x00 }, /* B1 DAI2 EQ5 */
{ 0xb2, 0x00 }, /* B2 DAI2 EQ5 */
{ 0xb3, 0x00 }, /* B3 DAI2 EQ5 */
{ 0xb4, 0x00 }, /* B4 DAI2 EQ5 */
{ 0xb5, 0x00 }, /* B5 DAI2 EQ5 */
{ 0xb6, 0x00 }, /* B6 DAI1 biquad */
{ 0xb7, 0x00 }, /* B7 DAI1 biquad */
{ 0xb8 ,0x00 }, /* B8 DAI1 biquad */
{ 0xb9, 0x00 }, /* B9 DAI1 biquad */
{ 0xba, 0x00 }, /* BA DAI1 biquad */
{ 0xbb, 0x00 }, /* BB DAI1 biquad */
{ 0xbc, 0x00 }, /* BC DAI1 biquad */
{ 0xbd, 0x00 }, /* BD DAI1 biquad */
{ 0xbe, 0x00 }, /* BE DAI1 biquad */
{ 0xbf, 0x00 }, /* BF DAI1 biquad */
{ 0xc0, 0x00 }, /* C0 DAI2 biquad */
{ 0xc1, 0x00 }, /* C1 DAI2 biquad */
{ 0xc2, 0x00 }, /* C2 DAI2 biquad */
{ 0xc3, 0x00 }, /* C3 DAI2 biquad */
{ 0xc4, 0x00 }, /* C4 DAI2 biquad */
{ 0xc5, 0x00 }, /* C5 DAI2 biquad */
{ 0xc6, 0x00 }, /* C6 DAI2 biquad */
{ 0xc7, 0x00 }, /* C7 DAI2 biquad */
{ 0xc8, 0x00 }, /* C8 DAI2 biquad */
{ 0xc9, 0x00 }, /* C9 DAI2 biquad */
};
static bool max98088_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case M98088_REG_00_IRQ_STATUS ... 0xC9:
case M98088_REG_FF_REV_ID:
return true;
default:
return false;
}
}
static bool max98088_writeable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case M98088_REG_03_BATTERY_VOLTAGE ... 0xC9:
return true;
default:
return false;
}
}
static bool max98088_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case M98088_REG_00_IRQ_STATUS ... M98088_REG_03_BATTERY_VOLTAGE:
case M98088_REG_FF_REV_ID:
return true;
default:
return false;
}
}
static const struct regmap_config max98088_regmap = {
.reg_bits = 8,
.val_bits = 8,
.readable_reg = max98088_readable_register,
.writeable_reg = max98088_writeable_register,
.volatile_reg = max98088_volatile_register,
.max_register = 0xff,
.reg_defaults = max98088_reg,
.num_reg_defaults = ARRAY_SIZE(max98088_reg),
.cache_type = REGCACHE_RBTREE,
};
/*
* Load equalizer DSP coefficient configurations registers
*/
static void m98088_eq_band(struct snd_soc_component *component, unsigned int dai,
unsigned int band, u16 *coefs)
{
unsigned int eq_reg;
unsigned int i;
if (WARN_ON(band > 4) ||
WARN_ON(dai > 1))
return;
/* Load the base register address */
eq_reg = dai ? M98088_REG_84_DAI2_EQ_BASE : M98088_REG_52_DAI1_EQ_BASE;
/* Add the band address offset, note adjustment for word address */
eq_reg += band * (M98088_COEFS_PER_BAND << 1);
/* Step through the registers and coefs */
for (i = 0; i < M98088_COEFS_PER_BAND; i++) {
snd_soc_component_write(component, eq_reg++, M98088_BYTE1(coefs[i]));
snd_soc_component_write(component, eq_reg++, M98088_BYTE0(coefs[i]));
}
}
/*
* Excursion limiter modes
*/
static const char *max98088_exmode_texts[] = {
"Off", "100Hz", "400Hz", "600Hz", "800Hz", "1000Hz", "200-400Hz",
"400-600Hz", "400-800Hz",
};
static const unsigned int max98088_exmode_values[] = {
0x00, 0x43, 0x10, 0x20, 0x30, 0x40, 0x11, 0x22, 0x32
};
static SOC_VALUE_ENUM_SINGLE_DECL(max98088_exmode_enum,
M98088_REG_41_SPKDHP, 0, 127,
max98088_exmode_texts,
max98088_exmode_values);
static const char *max98088_ex_thresh[] = { /* volts PP */
"0.6", "1.2", "1.8", "2.4", "3.0", "3.6", "4.2", "4.8"};
static SOC_ENUM_SINGLE_DECL(max98088_ex_thresh_enum,
M98088_REG_42_SPKDHP_THRESH, 0,
max98088_ex_thresh);
static const char *max98088_fltr_mode[] = {"Voice", "Music" };
static SOC_ENUM_SINGLE_DECL(max98088_filter_mode_enum,
M98088_REG_18_DAI1_FILTERS, 7,
max98088_fltr_mode);
static const char *max98088_extmic_text[] = { "None", "MIC1", "MIC2" };
static SOC_ENUM_SINGLE_DECL(max98088_extmic_enum,
M98088_REG_48_CFG_MIC, 0,
max98088_extmic_text);
static const struct snd_kcontrol_new max98088_extmic_mux =
SOC_DAPM_ENUM("External MIC Mux", max98088_extmic_enum);
static const char *max98088_dai1_fltr[] = {
"Off", "fc=258/fs=16k", "fc=500/fs=16k",
"fc=258/fs=8k", "fc=500/fs=8k", "fc=200"};
static SOC_ENUM_SINGLE_DECL(max98088_dai1_dac_filter_enum,
M98088_REG_18_DAI1_FILTERS, 0,
max98088_dai1_fltr);
static SOC_ENUM_SINGLE_DECL(max98088_dai1_adc_filter_enum,
M98088_REG_18_DAI1_FILTERS, 4,
max98088_dai1_fltr);
static int max98088_mic1pre_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
unsigned int sel = ucontrol->value.integer.value[0];
max98088->mic1pre = sel;
snd_soc_component_update_bits(component, M98088_REG_35_LVL_MIC1, M98088_MICPRE_MASK,
(1+sel)<<M98088_MICPRE_SHIFT);
return 0;
}
static int max98088_mic1pre_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = max98088->mic1pre;
return 0;
}
static int max98088_mic2pre_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
unsigned int sel = ucontrol->value.integer.value[0];
max98088->mic2pre = sel;
snd_soc_component_update_bits(component, M98088_REG_36_LVL_MIC2, M98088_MICPRE_MASK,
(1+sel)<<M98088_MICPRE_SHIFT);
return 0;
}
static int max98088_mic2pre_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = max98088->mic2pre;
return 0;
}
static const DECLARE_TLV_DB_RANGE(max98088_micboost_tlv,
0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0)
);
static const DECLARE_TLV_DB_RANGE(max98088_hp_tlv,
0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
28, 31, TLV_DB_SCALE_ITEM(150, 50, 0)
);
static const DECLARE_TLV_DB_RANGE(max98088_spk_tlv,
0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
28, 31, TLV_DB_SCALE_ITEM(650, 50, 0)
);
static const struct snd_kcontrol_new max98088_snd_controls[] = {
SOC_DOUBLE_R_TLV("Headphone Volume", M98088_REG_39_LVL_HP_L,
M98088_REG_3A_LVL_HP_R, 0, 31, 0, max98088_hp_tlv),
SOC_DOUBLE_R_TLV("Speaker Volume", M98088_REG_3D_LVL_SPK_L,
M98088_REG_3E_LVL_SPK_R, 0, 31, 0, max98088_spk_tlv),
SOC_DOUBLE_R_TLV("Receiver Volume", M98088_REG_3B_LVL_REC_L,
M98088_REG_3C_LVL_REC_R, 0, 31, 0, max98088_spk_tlv),
SOC_DOUBLE_R("Headphone Switch", M98088_REG_39_LVL_HP_L,
M98088_REG_3A_LVL_HP_R, 7, 1, 1),
SOC_DOUBLE_R("Speaker Switch", M98088_REG_3D_LVL_SPK_L,
M98088_REG_3E_LVL_SPK_R, 7, 1, 1),
SOC_DOUBLE_R("Receiver Switch", M98088_REG_3B_LVL_REC_L,
M98088_REG_3C_LVL_REC_R, 7, 1, 1),
SOC_SINGLE("MIC1 Volume", M98088_REG_35_LVL_MIC1, 0, 31, 1),
SOC_SINGLE("MIC2 Volume", M98088_REG_36_LVL_MIC2, 0, 31, 1),
SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
M98088_REG_35_LVL_MIC1, 5, 2, 0,
max98088_mic1pre_get, max98088_mic1pre_set,
max98088_micboost_tlv),
SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
M98088_REG_36_LVL_MIC2, 5, 2, 0,
max98088_mic2pre_get, max98088_mic2pre_set,
max98088_micboost_tlv),
SOC_SINGLE("Noise Gate Threshold", M98088_REG_40_MICAGC_THRESH,
4, 15, 0),
SOC_SINGLE("INA Volume", M98088_REG_37_LVL_INA, 0, 7, 1),
SOC_SINGLE("INB Volume", M98088_REG_38_LVL_INB, 0, 7, 1),
SOC_SINGLE("ADCL Volume", M98088_REG_33_LVL_ADC_L, 0, 15, 0),
SOC_SINGLE("ADCR Volume", M98088_REG_34_LVL_ADC_R, 0, 15, 0),
SOC_SINGLE("ADCL Boost Volume", M98088_REG_33_LVL_ADC_L, 4, 3, 0),
SOC_SINGLE("ADCR Boost Volume", M98088_REG_34_LVL_ADC_R, 4, 3, 0),
SOC_SINGLE("EQ1 Switch", M98088_REG_49_CFG_LEVEL, 0, 1, 0),
SOC_SINGLE("EQ2 Switch", M98088_REG_49_CFG_LEVEL, 1, 1, 0),
SOC_ENUM("EX Limiter Mode", max98088_exmode_enum),
SOC_ENUM("EX Limiter Threshold", max98088_ex_thresh_enum),
SOC_ENUM("DAI1 Filter Mode", max98088_filter_mode_enum),
SOC_ENUM("DAI1 DAC Filter", max98088_dai1_dac_filter_enum),
SOC_ENUM("DAI1 ADC Filter", max98088_dai1_adc_filter_enum),
SOC_SINGLE("DAI2 DC Block Switch", M98088_REG_20_DAI2_FILTERS,
0, 1, 0),
SOC_SINGLE("ALC Switch", M98088_REG_43_SPKALC_COMP, 7, 1, 0),
SOC_SINGLE("ALC Threshold", M98088_REG_43_SPKALC_COMP, 0, 7, 0),
SOC_SINGLE("ALC Multiband", M98088_REG_43_SPKALC_COMP, 3, 1, 0),
SOC_SINGLE("ALC Release Time", M98088_REG_43_SPKALC_COMP, 4, 7, 0),
SOC_SINGLE("PWR Limiter Threshold", M98088_REG_44_PWRLMT_CFG,
4, 15, 0),
SOC_SINGLE("PWR Limiter Weight", M98088_REG_44_PWRLMT_CFG, 0, 7, 0),
SOC_SINGLE("PWR Limiter Time1", M98088_REG_45_PWRLMT_TIME, 0, 15, 0),
SOC_SINGLE("PWR Limiter Time2", M98088_REG_45_PWRLMT_TIME, 4, 15, 0),
SOC_SINGLE("THD Limiter Threshold", M98088_REG_46_THDLMT_CFG, 4, 15, 0),
SOC_SINGLE("THD Limiter Time", M98088_REG_46_THDLMT_CFG, 0, 7, 0),
};
/* Left speaker mixer switch */
static const struct snd_kcontrol_new max98088_left_speaker_mixer_controls[] = {
SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0),
SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0),
SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0),
SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0),
SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 5, 1, 0),
SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 6, 1, 0),
SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 1, 1, 0),
SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 2, 1, 0),
SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 3, 1, 0),
SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 4, 1, 0),
};
/* Right speaker mixer switch */
static const struct snd_kcontrol_new max98088_right_speaker_mixer_controls[] = {
SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0),
SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0),
SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0),
SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0),
SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 5, 1, 0),
SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 6, 1, 0),
SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 1, 1, 0),
SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 2, 1, 0),
SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 3, 1, 0),
SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 4, 1, 0),
};
/* Left headphone mixer switch */
static const struct snd_kcontrol_new max98088_left_hp_mixer_controls[] = {
SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0),
SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0),
SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0),
SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0),
SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_25_MIX_HP_LEFT, 5, 1, 0),
SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_25_MIX_HP_LEFT, 6, 1, 0),
SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_25_MIX_HP_LEFT, 1, 1, 0),
SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_25_MIX_HP_LEFT, 2, 1, 0),
SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_25_MIX_HP_LEFT, 3, 1, 0),
SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_25_MIX_HP_LEFT, 4, 1, 0),
};
/* Right headphone mixer switch */
static const struct snd_kcontrol_new max98088_right_hp_mixer_controls[] = {
SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0),
SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0),
SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0),
SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0),
SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 5, 1, 0),
SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 6, 1, 0),
SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_26_MIX_HP_RIGHT, 1, 1, 0),
SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_26_MIX_HP_RIGHT, 2, 1, 0),
SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_26_MIX_HP_RIGHT, 3, 1, 0),
SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_26_MIX_HP_RIGHT, 4, 1, 0),
};
/* Left earpiece/receiver mixer switch */
static const struct snd_kcontrol_new max98088_left_rec_mixer_controls[] = {
SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0),
SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0),
SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0),
SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0),
SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_28_MIX_REC_LEFT, 5, 1, 0),
SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_28_MIX_REC_LEFT, 6, 1, 0),
SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_28_MIX_REC_LEFT, 1, 1, 0),
SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_28_MIX_REC_LEFT, 2, 1, 0),
SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_28_MIX_REC_LEFT, 3, 1, 0),
SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_28_MIX_REC_LEFT, 4, 1, 0),
};
/* Right earpiece/receiver mixer switch */
static const struct snd_kcontrol_new max98088_right_rec_mixer_controls[] = {
SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0),
SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0),
SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0),
SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0),
SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 5, 1, 0),
SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 6, 1, 0),
SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_29_MIX_REC_RIGHT, 1, 1, 0),
SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_29_MIX_REC_RIGHT, 2, 1, 0),
SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_29_MIX_REC_RIGHT, 3, 1, 0),
SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_29_MIX_REC_RIGHT, 4, 1, 0),
};
/* Left ADC mixer switch */
static const struct snd_kcontrol_new max98088_left_ADC_mixer_controls[] = {
SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_23_MIX_ADC_LEFT, 7, 1, 0),
SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_23_MIX_ADC_LEFT, 6, 1, 0),
SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_23_MIX_ADC_LEFT, 3, 1, 0),
SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_23_MIX_ADC_LEFT, 2, 1, 0),
SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_23_MIX_ADC_LEFT, 1, 1, 0),
SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_23_MIX_ADC_LEFT, 0, 1, 0),
};
/* Right ADC mixer switch */
static const struct snd_kcontrol_new max98088_right_ADC_mixer_controls[] = {
SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 7, 1, 0),
SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 6, 1, 0),
SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 3, 1, 0),
SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 2, 1, 0),
SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 1, 1, 0),
SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 0, 1, 0),
};
static int max98088_mic_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
if (w->reg == M98088_REG_35_LVL_MIC1) {
snd_soc_component_update_bits(component, w->reg, M98088_MICPRE_MASK,
(1+max98088->mic1pre)<<M98088_MICPRE_SHIFT);
} else {
snd_soc_component_update_bits(component, w->reg, M98088_MICPRE_MASK,
(1+max98088->mic2pre)<<M98088_MICPRE_SHIFT);
}
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component, w->reg, M98088_MICPRE_MASK, 0);
break;
default:
return -EINVAL;
}
return 0;
}
/*
* The line inputs are 2-channel stereo inputs with the left
* and right channels sharing a common PGA power control signal.
*/
static int max98088_line_pga(struct snd_soc_dapm_widget *w,
int event, int line, u8 channel)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
u8 *state;
if (WARN_ON(!(channel == 1 || channel == 2)))
return -EINVAL;
switch (line) {
case LINE_INA:
state = &max98088->ina_state;
break;
case LINE_INB:
state = &max98088->inb_state;
break;
default:
return -EINVAL;
}
switch (event) {
case SND_SOC_DAPM_POST_PMU:
*state |= channel;
snd_soc_component_update_bits(component, w->reg,
(1 << w->shift), (1 << w->shift));
break;
case SND_SOC_DAPM_POST_PMD:
*state &= ~channel;
if (*state == 0) {
snd_soc_component_update_bits(component, w->reg,
(1 << w->shift), 0);
}
break;
default:
return -EINVAL;
}
return 0;
}
static int max98088_pga_ina1_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *k, int event)
{
return max98088_line_pga(w, event, LINE_INA, 1);
}
static int max98088_pga_ina2_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *k, int event)
{
return max98088_line_pga(w, event, LINE_INA, 2);
}
static int max98088_pga_inb1_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *k, int event)
{
return max98088_line_pga(w, event, LINE_INB, 1);
}
static int max98088_pga_inb2_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *k, int event)
{
return max98088_line_pga(w, event, LINE_INB, 2);
}
static const struct snd_soc_dapm_widget max98088_dapm_widgets[] = {
SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 1, 0),
SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 0, 0),
SND_SOC_DAPM_DAC("DACL1", "HiFi Playback",
M98088_REG_4D_PWR_EN_OUT, 1, 0),
SND_SOC_DAPM_DAC("DACR1", "HiFi Playback",
M98088_REG_4D_PWR_EN_OUT, 0, 0),
SND_SOC_DAPM_DAC("DACL2", "Aux Playback",
M98088_REG_4D_PWR_EN_OUT, 1, 0),
SND_SOC_DAPM_DAC("DACR2", "Aux Playback",
M98088_REG_4D_PWR_EN_OUT, 0, 0),
SND_SOC_DAPM_PGA("HP Left Out", M98088_REG_4D_PWR_EN_OUT,
7, 0, NULL, 0),
SND_SOC_DAPM_PGA("HP Right Out", M98088_REG_4D_PWR_EN_OUT,
6, 0, NULL, 0),
SND_SOC_DAPM_PGA("SPK Left Out", M98088_REG_4D_PWR_EN_OUT,
5, 0, NULL, 0),
SND_SOC_DAPM_PGA("SPK Right Out", M98088_REG_4D_PWR_EN_OUT,
4, 0, NULL, 0),
SND_SOC_DAPM_PGA("REC Left Out", M98088_REG_4D_PWR_EN_OUT,
3, 0, NULL, 0),
SND_SOC_DAPM_PGA("REC Right Out", M98088_REG_4D_PWR_EN_OUT,
2, 0, NULL, 0),
SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0,
&max98088_extmic_mux),
SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
&max98088_left_hp_mixer_controls[0],
ARRAY_SIZE(max98088_left_hp_mixer_controls)),
SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
&max98088_right_hp_mixer_controls[0],
ARRAY_SIZE(max98088_right_hp_mixer_controls)),
SND_SOC_DAPM_MIXER("Left SPK Mixer", SND_SOC_NOPM, 0, 0,
&max98088_left_speaker_mixer_controls[0],
ARRAY_SIZE(max98088_left_speaker_mixer_controls)),
SND_SOC_DAPM_MIXER("Right SPK Mixer", SND_SOC_NOPM, 0, 0,
&max98088_right_speaker_mixer_controls[0],
ARRAY_SIZE(max98088_right_speaker_mixer_controls)),
SND_SOC_DAPM_MIXER("Left REC Mixer", SND_SOC_NOPM, 0, 0,
&max98088_left_rec_mixer_controls[0],
ARRAY_SIZE(max98088_left_rec_mixer_controls)),
SND_SOC_DAPM_MIXER("Right REC Mixer", SND_SOC_NOPM, 0, 0,
&max98088_right_rec_mixer_controls[0],
ARRAY_SIZE(max98088_right_rec_mixer_controls)),
SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
&max98088_left_ADC_mixer_controls[0],
ARRAY_SIZE(max98088_left_ADC_mixer_controls)),
SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
&max98088_right_ADC_mixer_controls[0],
ARRAY_SIZE(max98088_right_ADC_mixer_controls)),
SND_SOC_DAPM_PGA_E("MIC1 Input", M98088_REG_35_LVL_MIC1,
5, 0, NULL, 0, max98088_mic_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("MIC2 Input", M98088_REG_36_LVL_MIC2,
5, 0, NULL, 0, max98088_mic_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("INA1 Input", M98088_REG_4C_PWR_EN_IN,
7, 0, NULL, 0, max98088_pga_ina1_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("INA2 Input", M98088_REG_4C_PWR_EN_IN,
7, 0, NULL, 0, max98088_pga_ina2_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("INB1 Input", M98088_REG_4C_PWR_EN_IN,
6, 0, NULL, 0, max98088_pga_inb1_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("INB2 Input", M98088_REG_4C_PWR_EN_IN,
6, 0, NULL, 0, max98088_pga_inb2_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MICBIAS("MICBIAS", M98088_REG_4C_PWR_EN_IN, 3, 0),
SND_SOC_DAPM_OUTPUT("HPL"),
SND_SOC_DAPM_OUTPUT("HPR"),
SND_SOC_DAPM_OUTPUT("SPKL"),
SND_SOC_DAPM_OUTPUT("SPKR"),
SND_SOC_DAPM_OUTPUT("RECL"),
SND_SOC_DAPM_OUTPUT("RECR"),
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_INPUT("MIC2"),
SND_SOC_DAPM_INPUT("INA1"),
SND_SOC_DAPM_INPUT("INA2"),
SND_SOC_DAPM_INPUT("INB1"),
SND_SOC_DAPM_INPUT("INB2"),
};
static const struct snd_soc_dapm_route max98088_audio_map[] = {
/* Left headphone output mixer */
{"Left HP Mixer", "Left DAC1 Switch", "DACL1"},
{"Left HP Mixer", "Left DAC2 Switch", "DACL2"},
{"Left HP Mixer", "Right DAC1 Switch", "DACR1"},
{"Left HP Mixer", "Right DAC2 Switch", "DACR2"},
{"Left HP Mixer", "MIC1 Switch", "MIC1 Input"},
{"Left HP Mixer", "MIC2 Switch", "MIC2 Input"},
{"Left HP Mixer", "INA1 Switch", "INA1 Input"},
{"Left HP Mixer", "INA2 Switch", "INA2 Input"},
{"Left HP Mixer", "INB1 Switch", "INB1 Input"},
{"Left HP Mixer", "INB2 Switch", "INB2 Input"},
/* Right headphone output mixer */
{"Right HP Mixer", "Left DAC1 Switch", "DACL1"},
{"Right HP Mixer", "Left DAC2 Switch", "DACL2" },
{"Right HP Mixer", "Right DAC1 Switch", "DACR1"},
{"Right HP Mixer", "Right DAC2 Switch", "DACR2"},
{"Right HP Mixer", "MIC1 Switch", "MIC1 Input"},
{"Right HP Mixer", "MIC2 Switch", "MIC2 Input"},
{"Right HP Mixer", "INA1 Switch", "INA1 Input"},
{"Right HP Mixer", "INA2 Switch", "INA2 Input"},
{"Right HP Mixer", "INB1 Switch", "INB1 Input"},
{"Right HP Mixer", "INB2 Switch", "INB2 Input"},
/* Left speaker output mixer */
{"Left SPK Mixer", "Left DAC1 Switch", "DACL1"},
{"Left SPK Mixer", "Left DAC2 Switch", "DACL2"},
{"Left SPK Mixer", "Right DAC1 Switch", "DACR1"},
{"Left SPK Mixer", "Right DAC2 Switch", "DACR2"},
{"Left SPK Mixer", "MIC1 Switch", "MIC1 Input"},
{"Left SPK Mixer", "MIC2 Switch", "MIC2 Input"},
{"Left SPK Mixer", "INA1 Switch", "INA1 Input"},
{"Left SPK Mixer", "INA2 Switch", "INA2 Input"},
{"Left SPK Mixer", "INB1 Switch", "INB1 Input"},
{"Left SPK Mixer", "INB2 Switch", "INB2 Input"},
/* Right speaker output mixer */
{"Right SPK Mixer", "Left DAC1 Switch", "DACL1"},
{"Right SPK Mixer", "Left DAC2 Switch", "DACL2"},
{"Right SPK Mixer", "Right DAC1 Switch", "DACR1"},
{"Right SPK Mixer", "Right DAC2 Switch", "DACR2"},
{"Right SPK Mixer", "MIC1 Switch", "MIC1 Input"},
{"Right SPK Mixer", "MIC2 Switch", "MIC2 Input"},
{"Right SPK Mixer", "INA1 Switch", "INA1 Input"},
{"Right SPK Mixer", "INA2 Switch", "INA2 Input"},
{"Right SPK Mixer", "INB1 Switch", "INB1 Input"},
{"Right SPK Mixer", "INB2 Switch", "INB2 Input"},
/* Earpiece/Receiver output mixer */
{"Left REC Mixer", "Left DAC1 Switch", "DACL1"},
{"Left REC Mixer", "Left DAC2 Switch", "DACL2"},
{"Left REC Mixer", "Right DAC1 Switch", "DACR1"},
{"Left REC Mixer", "Right DAC2 Switch", "DACR2"},
{"Left REC Mixer", "MIC1 Switch", "MIC1 Input"},
{"Left REC Mixer", "MIC2 Switch", "MIC2 Input"},
{"Left REC Mixer", "INA1 Switch", "INA1 Input"},
{"Left REC Mixer", "INA2 Switch", "INA2 Input"},
{"Left REC Mixer", "INB1 Switch", "INB1 Input"},
{"Left REC Mixer", "INB2 Switch", "INB2 Input"},
/* Earpiece/Receiver output mixer */
{"Right REC Mixer", "Left DAC1 Switch", "DACL1"},
{"Right REC Mixer", "Left DAC2 Switch", "DACL2"},
{"Right REC Mixer", "Right DAC1 Switch", "DACR1"},
{"Right REC Mixer", "Right DAC2 Switch", "DACR2"},
{"Right REC Mixer", "MIC1 Switch", "MIC1 Input"},
{"Right REC Mixer", "MIC2 Switch", "MIC2 Input"},
{"Right REC Mixer", "INA1 Switch", "INA1 Input"},
{"Right REC Mixer", "INA2 Switch", "INA2 Input"},
{"Right REC Mixer", "INB1 Switch", "INB1 Input"},
{"Right REC Mixer", "INB2 Switch", "INB2 Input"},
{"HP Left Out", NULL, "Left HP Mixer"},
{"HP Right Out", NULL, "Right HP Mixer"},
{"SPK Left Out", NULL, "Left SPK Mixer"},
{"SPK Right Out", NULL, "Right SPK Mixer"},
{"REC Left Out", NULL, "Left REC Mixer"},
{"REC Right Out", NULL, "Right REC Mixer"},
{"HPL", NULL, "HP Left Out"},
{"HPR", NULL, "HP Right Out"},
{"SPKL", NULL, "SPK Left Out"},
{"SPKR", NULL, "SPK Right Out"},
{"RECL", NULL, "REC Left Out"},
{"RECR", NULL, "REC Right Out"},
/* Left ADC input mixer */
{"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
{"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
{"Left ADC Mixer", "INA1 Switch", "INA1 Input"},
{"Left ADC Mixer", "INA2 Switch", "INA2 Input"},
{"Left ADC Mixer", "INB1 Switch", "INB1 Input"},
{"Left ADC Mixer", "INB2 Switch", "INB2 Input"},
/* Right ADC input mixer */
{"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
{"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
{"Right ADC Mixer", "INA1 Switch", "INA1 Input"},
{"Right ADC Mixer", "INA2 Switch", "INA2 Input"},
{"Right ADC Mixer", "INB1 Switch", "INB1 Input"},
{"Right ADC Mixer", "INB2 Switch", "INB2 Input"},
/* Inputs */
{"ADCL", NULL, "Left ADC Mixer"},
{"ADCR", NULL, "Right ADC Mixer"},
{"INA1 Input", NULL, "INA1"},
{"INA2 Input", NULL, "INA2"},
{"INB1 Input", NULL, "INB1"},
{"INB2 Input", NULL, "INB2"},
{"MIC1 Input", NULL, "MIC1"},
{"MIC2 Input", NULL, "MIC2"},
};
/* codec mclk clock divider coefficients */
static const struct {
u32 rate;
u8 sr;
} rate_table[] = {
{8000, 0x10},
{11025, 0x20},
{16000, 0x30},
{22050, 0x40},
{24000, 0x50},
{32000, 0x60},
{44100, 0x70},
{48000, 0x80},
{88200, 0x90},
{96000, 0xA0},
};
static inline int rate_value(int rate, u8 *value)
{
int i;
for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
if (rate_table[i].rate >= rate) {
*value = rate_table[i].sr;
return 0;
}
}
*value = rate_table[0].sr;
return -EINVAL;
}
static int max98088_dai1_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
struct max98088_cdata *cdata;
unsigned long long ni;
unsigned int rate;
u8 regval;
cdata = &max98088->dai[0];
rate = params_rate(params);
switch (params_width(params)) {
case 16:
snd_soc_component_update_bits(component, M98088_REG_14_DAI1_FORMAT,
M98088_DAI_WS, 0);
break;
case 24:
snd_soc_component_update_bits(component, M98088_REG_14_DAI1_FORMAT,
M98088_DAI_WS, M98088_DAI_WS);
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0);
if (rate_value(rate, ®val))
return -EINVAL;
snd_soc_component_update_bits(component, M98088_REG_11_DAI1_CLKMODE,
M98088_CLKMODE_MASK, regval);
cdata->rate = rate;
/* Configure NI when operating as master */
if (snd_soc_component_read(component, M98088_REG_14_DAI1_FORMAT)
& M98088_DAI_MAS) {
unsigned long pclk;
if (max98088->sysclk == 0) {
dev_err(component->dev, "Invalid system clock frequency\n");
return -EINVAL;
}
ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
* (unsigned long long int)rate;
pclk = DIV_ROUND_CLOSEST(max98088->sysclk, max98088->mclk_prescaler);
ni = DIV_ROUND_CLOSEST_ULL(ni, pclk);
snd_soc_component_write(component, M98088_REG_12_DAI1_CLKCFG_HI,
(ni >> 8) & 0x7F);
snd_soc_component_write(component, M98088_REG_13_DAI1_CLKCFG_LO,
ni & 0xFF);
}
/* Update sample rate mode */
if (rate < 50000)
snd_soc_component_update_bits(component, M98088_REG_18_DAI1_FILTERS,
M98088_DAI_DHF, 0);
else
snd_soc_component_update_bits(component, M98088_REG_18_DAI1_FILTERS,
M98088_DAI_DHF, M98088_DAI_DHF);
snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN,
M98088_SHDNRUN);
return 0;
}
static int max98088_dai2_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
struct max98088_cdata *cdata;
unsigned long long ni;
unsigned int rate;
u8 regval;
cdata = &max98088->dai[1];
rate = params_rate(params);
switch (params_width(params)) {
case 16:
snd_soc_component_update_bits(component, M98088_REG_1C_DAI2_FORMAT,
M98088_DAI_WS, 0);
break;
case 24:
snd_soc_component_update_bits(component, M98088_REG_1C_DAI2_FORMAT,
M98088_DAI_WS, M98088_DAI_WS);
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0);
if (rate_value(rate, ®val))
return -EINVAL;
snd_soc_component_update_bits(component, M98088_REG_19_DAI2_CLKMODE,
M98088_CLKMODE_MASK, regval);
cdata->rate = rate;
/* Configure NI when operating as master */
if (snd_soc_component_read(component, M98088_REG_1C_DAI2_FORMAT)
& M98088_DAI_MAS) {
unsigned long pclk;
if (max98088->sysclk == 0) {
dev_err(component->dev, "Invalid system clock frequency\n");
return -EINVAL;
}
ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
* (unsigned long long int)rate;
pclk = DIV_ROUND_CLOSEST(max98088->sysclk, max98088->mclk_prescaler);
ni = DIV_ROUND_CLOSEST_ULL(ni, pclk);
snd_soc_component_write(component, M98088_REG_1A_DAI2_CLKCFG_HI,
(ni >> 8) & 0x7F);
snd_soc_component_write(component, M98088_REG_1B_DAI2_CLKCFG_LO,
ni & 0xFF);
}
/* Update sample rate mode */
if (rate < 50000)
snd_soc_component_update_bits(component, M98088_REG_20_DAI2_FILTERS,
M98088_DAI_DHF, 0);
else
snd_soc_component_update_bits(component, M98088_REG_20_DAI2_FILTERS,
M98088_DAI_DHF, M98088_DAI_DHF);
snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN,
M98088_SHDNRUN);
return 0;
}
static int max98088_dai_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
/* Requested clock frequency is already setup */
if (freq == max98088->sysclk)
return 0;
if (!IS_ERR(max98088->mclk)) {
freq = clk_round_rate(max98088->mclk, freq);
clk_set_rate(max98088->mclk, freq);
}
/* Setup clocks for slave mode, and using the PLL
* PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
* 0x02 (when master clk is 20MHz to 30MHz)..
*/
if ((freq >= 10000000) && (freq < 20000000)) {
snd_soc_component_write(component, M98088_REG_10_SYS_CLK, 0x10);
max98088->mclk_prescaler = 1;
} else if ((freq >= 20000000) && (freq < 30000000)) {
snd_soc_component_write(component, M98088_REG_10_SYS_CLK, 0x20);
max98088->mclk_prescaler = 2;
} else {
dev_err(component->dev, "Invalid master clock frequency\n");
return -EINVAL;
}
if (snd_soc_component_read(component, M98088_REG_51_PWR_SYS) & M98088_SHDNRUN) {
snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS,
M98088_SHDNRUN, 0);
snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS,
M98088_SHDNRUN, M98088_SHDNRUN);
}
dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
max98088->sysclk = freq;
return 0;
}
static int max98088_dai1_set_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
struct max98088_cdata *cdata;
u8 reg15val;
u8 reg14val = 0;
cdata = &max98088->dai[0];
if (fmt != cdata->fmt) {
cdata->fmt = fmt;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC:
/* Consumer mode PLL */
snd_soc_component_write(component, M98088_REG_12_DAI1_CLKCFG_HI,
0x80);
snd_soc_component_write(component, M98088_REG_13_DAI1_CLKCFG_LO,
0x00);
break;
case SND_SOC_DAIFMT_CBP_CFP:
/* Set to provider mode */
reg14val |= M98088_DAI_MAS;
break;
default:
dev_err(component->dev, "Clock mode unsupported");
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
reg14val |= M98088_DAI_DLY;
break;
case SND_SOC_DAIFMT_LEFT_J:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_NB_IF:
reg14val |= M98088_DAI_WCI;
break;
case SND_SOC_DAIFMT_IB_NF:
reg14val |= M98088_DAI_BCI;
break;
case SND_SOC_DAIFMT_IB_IF:
reg14val |= M98088_DAI_BCI|M98088_DAI_WCI;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, M98088_REG_14_DAI1_FORMAT,
M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI |
M98088_DAI_WCI, reg14val);
reg15val = M98088_DAI_BSEL64;
if (max98088->digmic)
reg15val |= M98088_DAI_OSR64;
snd_soc_component_write(component, M98088_REG_15_DAI1_CLOCK, reg15val);
}
return 0;
}
static int max98088_dai2_set_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
struct max98088_cdata *cdata;
u8 reg1Cval = 0;
cdata = &max98088->dai[1];
if (fmt != cdata->fmt) {
cdata->fmt = fmt;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC:
/* Consumer mode PLL */
snd_soc_component_write(component, M98088_REG_1A_DAI2_CLKCFG_HI,
0x80);
snd_soc_component_write(component, M98088_REG_1B_DAI2_CLKCFG_LO,
0x00);
break;
case SND_SOC_DAIFMT_CBP_CFP:
/* Set to provider mode */
reg1Cval |= M98088_DAI_MAS;
break;
default:
dev_err(component->dev, "Clock mode unsupported");
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
reg1Cval |= M98088_DAI_DLY;
break;
case SND_SOC_DAIFMT_LEFT_J:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_NB_IF:
reg1Cval |= M98088_DAI_WCI;
break;
case SND_SOC_DAIFMT_IB_NF:
reg1Cval |= M98088_DAI_BCI;
break;
case SND_SOC_DAIFMT_IB_IF:
reg1Cval |= M98088_DAI_BCI|M98088_DAI_WCI;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, M98088_REG_1C_DAI2_FORMAT,
M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI |
M98088_DAI_WCI, reg1Cval);
snd_soc_component_write(component, M98088_REG_1D_DAI2_CLOCK,
M98088_DAI_BSEL64);
}
return 0;
}
static int max98088_dai1_mute(struct snd_soc_dai *codec_dai, int mute,
int direction)
{
struct snd_soc_component *component = codec_dai->component;
int reg;
if (mute)
reg = M98088_DAI_MUTE;
else
reg = 0;
snd_soc_component_update_bits(component, M98088_REG_2F_LVL_DAI1_PLAY,
M98088_DAI_MUTE_MASK, reg);
return 0;
}
static int max98088_dai2_mute(struct snd_soc_dai *codec_dai, int mute,
int direction)
{
struct snd_soc_component *component = codec_dai->component;
int reg;
if (mute)
reg = M98088_DAI_MUTE;
else
reg = 0;
snd_soc_component_update_bits(component, M98088_REG_31_LVL_DAI2_PLAY,
M98088_DAI_MUTE_MASK, reg);
return 0;
}
static int max98088_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
/*
* SND_SOC_BIAS_PREPARE is called while preparing for a
* transition to ON or away from ON. If current bias_level
* is SND_SOC_BIAS_ON, then it is preparing for a transition
* away from ON. Disable the clock in that case, otherwise
* enable it.
*/
if (!IS_ERR(max98088->mclk)) {
if (snd_soc_component_get_bias_level(component) ==
SND_SOC_BIAS_ON)
clk_disable_unprepare(max98088->mclk);
else
clk_prepare_enable(max98088->mclk);
}
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
regcache_sync(max98088->regmap);
snd_soc_component_update_bits(component, M98088_REG_4C_PWR_EN_IN,
M98088_MBEN, M98088_MBEN);
break;
case SND_SOC_BIAS_OFF:
snd_soc_component_update_bits(component, M98088_REG_4C_PWR_EN_IN,
M98088_MBEN, 0);
regcache_mark_dirty(max98088->regmap);
break;
}
return 0;
}
#define MAX98088_RATES SNDRV_PCM_RATE_8000_96000
#define MAX98088_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
static const struct snd_soc_dai_ops max98088_dai1_ops = {
.set_sysclk = max98088_dai_set_sysclk,
.set_fmt = max98088_dai1_set_fmt,
.hw_params = max98088_dai1_hw_params,
.mute_stream = max98088_dai1_mute,
.no_capture_mute = 1,
};
static const struct snd_soc_dai_ops max98088_dai2_ops = {
.set_sysclk = max98088_dai_set_sysclk,
.set_fmt = max98088_dai2_set_fmt,
.hw_params = max98088_dai2_hw_params,
.mute_stream = max98088_dai2_mute,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver max98088_dai[] = {
{
.name = "HiFi",
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MAX98088_RATES,
.formats = MAX98088_FORMATS,
},
.capture = {
.stream_name = "HiFi Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MAX98088_RATES,
.formats = MAX98088_FORMATS,
},
.ops = &max98088_dai1_ops,
},
{
.name = "Aux",
.playback = {
.stream_name = "Aux Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MAX98088_RATES,
.formats = MAX98088_FORMATS,
},
.ops = &max98088_dai2_ops,
}
};
static const char *eq_mode_name[] = {"EQ1 Mode", "EQ2 Mode"};
static int max98088_get_channel(struct snd_soc_component *component, const char *name)
{
int ret;
ret = match_string(eq_mode_name, ARRAY_SIZE(eq_mode_name), name);
if (ret < 0)
dev_err(component->dev, "Bad EQ channel name '%s'\n", name);
return ret;
}
static void max98088_setup_eq1(struct snd_soc_component *component)
{
struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
struct max98088_pdata *pdata = max98088->pdata;
struct max98088_eq_cfg *coef_set;
int best, best_val, save, i, sel, fs;
struct max98088_cdata *cdata;
cdata = &max98088->dai[0];
if (!pdata || !max98088->eq_textcnt)
return;
/* Find the selected configuration with nearest sample rate */
fs = cdata->rate;
sel = cdata->eq_sel;
best = 0;
best_val = INT_MAX;
for (i = 0; i < pdata->eq_cfgcnt; i++) {
if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 &&
abs(pdata->eq_cfg[i].rate - fs) < best_val) {
best = i;
best_val = abs(pdata->eq_cfg[i].rate - fs);
}
}
dev_dbg(component->dev, "Selected %s/%dHz for %dHz sample rate\n",
pdata->eq_cfg[best].name,
pdata->eq_cfg[best].rate, fs);
/* Disable EQ while configuring, and save current on/off state */
save = snd_soc_component_read(component, M98088_REG_49_CFG_LEVEL);
snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, 0);
coef_set = &pdata->eq_cfg[sel];
m98088_eq_band(component, 0, 0, coef_set->band1);
m98088_eq_band(component, 0, 1, coef_set->band2);
m98088_eq_band(component, 0, 2, coef_set->band3);
m98088_eq_band(component, 0, 3, coef_set->band4);
m98088_eq_band(component, 0, 4, coef_set->band5);
/* Restore the original on/off state */
snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, save);
}
static void max98088_setup_eq2(struct snd_soc_component *component)
{
struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
struct max98088_pdata *pdata = max98088->pdata;
struct max98088_eq_cfg *coef_set;
int best, best_val, save, i, sel, fs;
struct max98088_cdata *cdata;
cdata = &max98088->dai[1];
if (!pdata || !max98088->eq_textcnt)
return;
/* Find the selected configuration with nearest sample rate */
fs = cdata->rate;
sel = cdata->eq_sel;
best = 0;
best_val = INT_MAX;
for (i = 0; i < pdata->eq_cfgcnt; i++) {
if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 &&
abs(pdata->eq_cfg[i].rate - fs) < best_val) {
best = i;
best_val = abs(pdata->eq_cfg[i].rate - fs);
}
}
dev_dbg(component->dev, "Selected %s/%dHz for %dHz sample rate\n",
pdata->eq_cfg[best].name,
pdata->eq_cfg[best].rate, fs);
/* Disable EQ while configuring, and save current on/off state */
save = snd_soc_component_read(component, M98088_REG_49_CFG_LEVEL);
snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN, 0);
coef_set = &pdata->eq_cfg[sel];
m98088_eq_band(component, 1, 0, coef_set->band1);
m98088_eq_band(component, 1, 1, coef_set->band2);
m98088_eq_band(component, 1, 2, coef_set->band3);
m98088_eq_band(component, 1, 3, coef_set->band4);
m98088_eq_band(component, 1, 4, coef_set->band5);
/* Restore the original on/off state */
snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN,
save);
}
static int max98088_put_eq_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
struct max98088_pdata *pdata = max98088->pdata;
int channel = max98088_get_channel(component, kcontrol->id.name);
struct max98088_cdata *cdata;
int sel = ucontrol->value.enumerated.item[0];
if (channel < 0)
return channel;
cdata = &max98088->dai[channel];
if (sel >= pdata->eq_cfgcnt)
return -EINVAL;
cdata->eq_sel = sel;
switch (channel) {
case 0:
max98088_setup_eq1(component);
break;
case 1:
max98088_setup_eq2(component);
break;
}
return 0;
}
static int max98088_get_eq_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
int channel = max98088_get_channel(component, kcontrol->id.name);
struct max98088_cdata *cdata;
if (channel < 0)
return channel;
cdata = &max98088->dai[channel];
ucontrol->value.enumerated.item[0] = cdata->eq_sel;
return 0;
}
static void max98088_handle_eq_pdata(struct snd_soc_component *component)
{
struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
struct max98088_pdata *pdata = max98088->pdata;
struct max98088_eq_cfg *cfg;
unsigned int cfgcnt;
int i, j;
const char **t;
int ret;
struct snd_kcontrol_new controls[] = {
SOC_ENUM_EXT((char *)eq_mode_name[0],
max98088->eq_enum,
max98088_get_eq_enum,
max98088_put_eq_enum),
SOC_ENUM_EXT((char *)eq_mode_name[1],
max98088->eq_enum,
max98088_get_eq_enum,
max98088_put_eq_enum),
};
BUILD_BUG_ON(ARRAY_SIZE(controls) != ARRAY_SIZE(eq_mode_name));
cfg = pdata->eq_cfg;
cfgcnt = pdata->eq_cfgcnt;
/* Setup an array of texts for the equalizer enum.
* This is based on Mark Brown's equalizer driver code.
*/
max98088->eq_textcnt = 0;
max98088->eq_texts = NULL;
for (i = 0; i < cfgcnt; i++) {
for (j = 0; j < max98088->eq_textcnt; j++) {
if (strcmp(cfg[i].name, max98088->eq_texts[j]) == 0)
break;
}
if (j != max98088->eq_textcnt)
continue;
/* Expand the array */
t = krealloc(max98088->eq_texts,
sizeof(char *) * (max98088->eq_textcnt + 1),
GFP_KERNEL);
if (t == NULL)
continue;
/* Store the new entry */
t[max98088->eq_textcnt] = cfg[i].name;
max98088->eq_textcnt++;
max98088->eq_texts = t;
}
/* Now point the soc_enum to .texts array items */
max98088->eq_enum.texts = max98088->eq_texts;
max98088->eq_enum.items = max98088->eq_textcnt;
ret = snd_soc_add_component_controls(component, controls, ARRAY_SIZE(controls));
if (ret != 0)
dev_err(component->dev, "Failed to add EQ control: %d\n", ret);
}
static void max98088_handle_pdata(struct snd_soc_component *component)
{
struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
struct max98088_pdata *pdata = max98088->pdata;
u8 regval = 0;
if (!pdata) {
dev_dbg(component->dev, "No platform data\n");
return;
}
/* Configure mic for analog/digital mic mode */
if (pdata->digmic_left_mode)
regval |= M98088_DIGMIC_L;
if (pdata->digmic_right_mode)
regval |= M98088_DIGMIC_R;
max98088->digmic = (regval ? 1 : 0);
snd_soc_component_write(component, M98088_REG_48_CFG_MIC, regval);
/* Configure receiver output */
regval = ((pdata->receiver_mode) ? M98088_REC_LINEMODE : 0);
snd_soc_component_update_bits(component, M98088_REG_2A_MIC_REC_CNTL,
M98088_REC_LINEMODE_MASK, regval);
/* Configure equalizers */
if (pdata->eq_cfgcnt)
max98088_handle_eq_pdata(component);
}
static int max98088_probe(struct snd_soc_component *component)
{
struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
struct max98088_cdata *cdata;
int ret = 0;
regcache_mark_dirty(max98088->regmap);
/* initialize private data */
max98088->sysclk = (unsigned)-1;
max98088->eq_textcnt = 0;
cdata = &max98088->dai[0];
cdata->rate = (unsigned)-1;
cdata->fmt = (unsigned)-1;
cdata->eq_sel = 0;
cdata = &max98088->dai[1];
cdata->rate = (unsigned)-1;
cdata->fmt = (unsigned)-1;
cdata->eq_sel = 0;
max98088->ina_state = 0;
max98088->inb_state = 0;
max98088->ex_mode = 0;
max98088->digmic = 0;
max98088->mic1pre = 0;
max98088->mic2pre = 0;
ret = snd_soc_component_read(component, M98088_REG_FF_REV_ID);
if (ret < 0) {
dev_err(component->dev, "Failed to read device revision: %d\n",
ret);
goto err_access;
}
dev_info(component->dev, "revision %c\n", ret - 0x40 + 'A');
snd_soc_component_write(component, M98088_REG_51_PWR_SYS, M98088_PWRSV);
snd_soc_component_write(component, M98088_REG_0F_IRQ_ENABLE, 0x00);
snd_soc_component_write(component, M98088_REG_22_MIX_DAC,
M98088_DAI1L_TO_DACL|M98088_DAI2L_TO_DACL|
M98088_DAI1R_TO_DACR|M98088_DAI2R_TO_DACR);
snd_soc_component_write(component, M98088_REG_4E_BIAS_CNTL, 0xF0);
snd_soc_component_write(component, M98088_REG_50_DAC_BIAS2, 0x0F);
snd_soc_component_write(component, M98088_REG_16_DAI1_IOCFG,
M98088_S1NORMAL|M98088_SDATA);
snd_soc_component_write(component, M98088_REG_1E_DAI2_IOCFG,
M98088_S2NORMAL|M98088_SDATA);
max98088_handle_pdata(component);
err_access:
return ret;
}
static void max98088_remove(struct snd_soc_component *component)
{
struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
kfree(max98088->eq_texts);
}
static const struct snd_soc_component_driver soc_component_dev_max98088 = {
.probe = max98088_probe,
.remove = max98088_remove,
.set_bias_level = max98088_set_bias_level,
.controls = max98088_snd_controls,
.num_controls = ARRAY_SIZE(max98088_snd_controls),
.dapm_widgets = max98088_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(max98088_dapm_widgets),
.dapm_routes = max98088_audio_map,
.num_dapm_routes = ARRAY_SIZE(max98088_audio_map),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct i2c_device_id max98088_i2c_id[] = {
{ "max98088", MAX98088 },
{ "max98089", MAX98089 },
{ }
};
MODULE_DEVICE_TABLE(i2c, max98088_i2c_id);
static int max98088_i2c_probe(struct i2c_client *i2c)
{
struct max98088_priv *max98088;
const struct i2c_device_id *id;
max98088 = devm_kzalloc(&i2c->dev, sizeof(struct max98088_priv),
GFP_KERNEL);
if (max98088 == NULL)
return -ENOMEM;
max98088->regmap = devm_regmap_init_i2c(i2c, &max98088_regmap);
if (IS_ERR(max98088->regmap))
return PTR_ERR(max98088->regmap);
max98088->mclk = devm_clk_get(&i2c->dev, "mclk");
if (IS_ERR(max98088->mclk))
if (PTR_ERR(max98088->mclk) == -EPROBE_DEFER)
return PTR_ERR(max98088->mclk);
id = i2c_match_id(max98088_i2c_id, i2c);
max98088->devtype = id->driver_data;
i2c_set_clientdata(i2c, max98088);
max98088->pdata = i2c->dev.platform_data;
return devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_max98088,
&max98088_dai[0], 2);
}
#if defined(CONFIG_OF)
static const struct of_device_id max98088_of_match[] = {
{ .compatible = "maxim,max98088" },
{ .compatible = "maxim,max98089" },
{ }
};
MODULE_DEVICE_TABLE(of, max98088_of_match);
#endif
static struct i2c_driver max98088_i2c_driver = {
.driver = {
.name = "max98088",
.of_match_table = of_match_ptr(max98088_of_match),
},
.probe = max98088_i2c_probe,
.id_table = max98088_i2c_id,
};
module_i2c_driver(max98088_i2c_driver);
MODULE_DESCRIPTION("ALSA SoC MAX98088 driver");
MODULE_AUTHOR("Peter Hsiang, Jesse Marroquin");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/max98088.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// rt711-sdca.c -- rt711 SDCA ALSA SoC audio driver
//
// Copyright(c) 2021 Realtek Semiconductor Corp.
//
//
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm_runtime.h>
#include <linux/soundwire/sdw_registers.h>
#include <linux/slab.h>
#include <linux/bitops.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/sdw.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/jack.h>
#include "rt711-sdca.h"
static int rt711_sdca_index_write(struct rt711_sdca_priv *rt711,
unsigned int nid, unsigned int reg, unsigned int value)
{
int ret;
struct regmap *regmap = rt711->mbq_regmap;
unsigned int addr = (nid << 20) | reg;
ret = regmap_write(regmap, addr, value);
if (ret < 0)
dev_err(&rt711->slave->dev,
"Failed to set private value: %06x <= %04x ret=%d\n",
addr, value, ret);
return ret;
}
static int rt711_sdca_index_read(struct rt711_sdca_priv *rt711,
unsigned int nid, unsigned int reg, unsigned int *value)
{
int ret;
struct regmap *regmap = rt711->mbq_regmap;
unsigned int addr = (nid << 20) | reg;
ret = regmap_read(regmap, addr, value);
if (ret < 0)
dev_err(&rt711->slave->dev,
"Failed to get private value: %06x => %04x ret=%d\n",
addr, *value, ret);
return ret;
}
static int rt711_sdca_index_update_bits(struct rt711_sdca_priv *rt711,
unsigned int nid, unsigned int reg, unsigned int mask, unsigned int val)
{
unsigned int tmp;
int ret;
ret = rt711_sdca_index_read(rt711, nid, reg, &tmp);
if (ret < 0)
return ret;
set_mask_bits(&tmp, mask, val);
return rt711_sdca_index_write(rt711, nid, reg, tmp);
}
static void rt711_sdca_reset(struct rt711_sdca_priv *rt711)
{
rt711_sdca_index_update_bits(rt711, RT711_VENDOR_REG,
RT711_PARA_VERB_CTL, RT711_HIDDEN_REG_SW_RESET,
RT711_HIDDEN_REG_SW_RESET);
rt711_sdca_index_update_bits(rt711, RT711_VENDOR_HDA_CTL,
RT711_HDA_LEGACY_RESET_CTL, 0x1, 0x1);
}
static int rt711_sdca_calibration(struct rt711_sdca_priv *rt711)
{
unsigned int val, loop_rc = 0, loop_dc = 0;
struct device *dev;
struct regmap *regmap = rt711->regmap;
int chk_cnt = 100;
int ret = 0;
mutex_lock(&rt711->calibrate_mutex);
dev = regmap_get_device(regmap);
regmap_read(rt711->regmap, RT711_RC_CAL_STATUS, &val);
/* RC calibration */
if (!(val & 0x40))
rt711_sdca_index_update_bits(rt711, RT711_VENDOR_ANALOG_CTL,
RT711_MISC_POWER_CTL0, 0x0010, 0x0010);
for (loop_rc = 0; loop_rc < chk_cnt && !(val & 0x40); loop_rc++) {
usleep_range(10000, 11000);
ret = regmap_read(rt711->regmap, RT711_RC_CAL_STATUS, &val);
if (ret < 0)
goto _cali_fail_;
}
if (loop_rc == chk_cnt)
dev_err(dev, "%s, RC calibration time-out!\n", __func__);
/* HP calibration by manual mode setting */
rt711_sdca_index_update_bits(rt711, RT711_VENDOR_REG,
RT711_FSM_CTL, 0x2000, 0x2000);
/* Calibration manual mode */
rt711_sdca_index_update_bits(rt711, RT711_VENDOR_REG,
RT711_FSM_CTL, 0xf, RT711_CALI_CTL);
/* reset HP calibration */
rt711_sdca_index_update_bits(rt711, RT711_VENDOR_CALI,
RT711_DAC_DC_CALI_CTL1, RT711_DAC_DC_FORCE_CALI_RST, 0x00);
rt711_sdca_index_update_bits(rt711, RT711_VENDOR_CALI,
RT711_DAC_DC_CALI_CTL1, RT711_DAC_DC_FORCE_CALI_RST,
RT711_DAC_DC_FORCE_CALI_RST);
/* cal_clk_en_reg */
if (rt711->hw_ver == RT711_VER_VD0)
rt711_sdca_index_update_bits(rt711, RT711_VENDOR_CALI,
RT711_DAC_DC_CALI_CTL1, RT711_DAC_DC_CALI_CLK_EN,
RT711_DAC_DC_CALI_CLK_EN);
/* trigger */
rt711_sdca_index_update_bits(rt711, RT711_VENDOR_CALI,
RT711_DAC_DC_CALI_CTL1, RT711_DAC_DC_CALI_TRIGGER,
RT711_DAC_DC_CALI_TRIGGER);
/* wait for calibration process */
rt711_sdca_index_read(rt711, RT711_VENDOR_CALI,
RT711_DAC_DC_CALI_CTL1, &val);
for (loop_dc = 0; loop_dc < chk_cnt &&
(val & RT711_DAC_DC_CALI_TRIGGER); loop_dc++) {
usleep_range(10000, 11000);
ret = rt711_sdca_index_read(rt711, RT711_VENDOR_CALI,
RT711_DAC_DC_CALI_CTL1, &val);
if (ret < 0)
goto _cali_fail_;
}
if (loop_dc == chk_cnt)
dev_err(dev, "%s, calibration time-out!\n", __func__);
if (loop_dc == chk_cnt || loop_rc == chk_cnt)
ret = -ETIMEDOUT;
_cali_fail_:
/* enable impedance sense */
rt711_sdca_index_update_bits(rt711, RT711_VENDOR_REG,
RT711_FSM_CTL, RT711_FSM_IMP_EN, RT711_FSM_IMP_EN);
/* release HP-JD and trigger FSM */
rt711_sdca_index_write(rt711, RT711_VENDOR_REG,
RT711_DIGITAL_MISC_CTRL4, 0x201b);
mutex_unlock(&rt711->calibrate_mutex);
dev_dbg(dev, "%s calibration complete, ret=%d\n", __func__, ret);
return ret;
}
static unsigned int rt711_sdca_button_detect(struct rt711_sdca_priv *rt711)
{
unsigned int btn_type = 0, offset, idx, val, owner;
int ret;
unsigned char buf[3];
/* get current UMP message owner */
ret = regmap_read(rt711->regmap,
SDW_SDCA_CTL(FUNC_NUM_HID, RT711_SDCA_ENT_HID01, RT711_SDCA_CTL_HIDTX_CURRENT_OWNER, 0),
&owner);
if (ret < 0)
return 0;
/* if owner is device then there is no button event from device */
if (owner == 1)
return 0;
/* read UMP message offset */
ret = regmap_read(rt711->regmap,
SDW_SDCA_CTL(FUNC_NUM_HID, RT711_SDCA_ENT_HID01, RT711_SDCA_CTL_HIDTX_MESSAGE_OFFSET, 0),
&offset);
if (ret < 0)
goto _end_btn_det_;
for (idx = 0; idx < sizeof(buf); idx++) {
ret = regmap_read(rt711->regmap,
RT711_BUF_ADDR_HID1 + offset + idx, &val);
if (ret < 0)
goto _end_btn_det_;
buf[idx] = val & 0xff;
}
if (buf[0] == 0x11) {
switch (buf[1] & 0xf0) {
case 0x10:
btn_type |= SND_JACK_BTN_2;
break;
case 0x20:
btn_type |= SND_JACK_BTN_3;
break;
case 0x40:
btn_type |= SND_JACK_BTN_0;
break;
case 0x80:
btn_type |= SND_JACK_BTN_1;
break;
}
switch (buf[2]) {
case 0x01:
case 0x10:
btn_type |= SND_JACK_BTN_2;
break;
case 0x02:
case 0x20:
btn_type |= SND_JACK_BTN_3;
break;
case 0x04:
case 0x40:
btn_type |= SND_JACK_BTN_0;
break;
case 0x08:
case 0x80:
btn_type |= SND_JACK_BTN_1;
break;
}
}
_end_btn_det_:
/* Host is owner, so set back to device */
if (owner == 0)
/* set owner to device */
regmap_write(rt711->regmap,
SDW_SDCA_CTL(FUNC_NUM_HID, RT711_SDCA_ENT_HID01,
RT711_SDCA_CTL_HIDTX_SET_OWNER_TO_DEVICE, 0), 0x01);
return btn_type;
}
static int rt711_sdca_headset_detect(struct rt711_sdca_priv *rt711)
{
unsigned int det_mode;
int ret;
/* get detected_mode */
ret = regmap_read(rt711->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_GE49, RT711_SDCA_CTL_DETECTED_MODE, 0),
&det_mode);
if (ret < 0)
goto io_error;
switch (det_mode) {
case 0x00:
rt711->jack_type = 0;
break;
case 0x03:
rt711->jack_type = SND_JACK_HEADPHONE;
break;
case 0x05:
rt711->jack_type = SND_JACK_HEADSET;
break;
}
/* write selected_mode */
if (det_mode) {
ret = regmap_write(rt711->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_GE49, RT711_SDCA_CTL_SELECTED_MODE, 0),
det_mode);
if (ret < 0)
goto io_error;
}
dev_dbg(&rt711->slave->dev,
"%s, detected_mode=0x%x\n", __func__, det_mode);
return 0;
io_error:
pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret);
return ret;
}
static void rt711_sdca_jack_detect_handler(struct work_struct *work)
{
struct rt711_sdca_priv *rt711 =
container_of(work, struct rt711_sdca_priv, jack_detect_work.work);
int btn_type = 0, ret;
if (!rt711->hs_jack)
return;
if (!snd_soc_card_is_instantiated(rt711->component->card))
return;
/* SDW_SCP_SDCA_INT_SDCA_0 is used for jack detection */
if (rt711->scp_sdca_stat1 & SDW_SCP_SDCA_INT_SDCA_0) {
ret = rt711_sdca_headset_detect(rt711);
if (ret < 0)
return;
}
/* SDW_SCP_SDCA_INT_SDCA_8 is used for button detection */
if (rt711->scp_sdca_stat2 & SDW_SCP_SDCA_INT_SDCA_8)
btn_type = rt711_sdca_button_detect(rt711);
if (rt711->jack_type == 0)
btn_type = 0;
dev_dbg(&rt711->slave->dev,
"in %s, jack_type=0x%x\n", __func__, rt711->jack_type);
dev_dbg(&rt711->slave->dev,
"in %s, btn_type=0x%x\n", __func__, btn_type);
dev_dbg(&rt711->slave->dev,
"in %s, scp_sdca_stat1=0x%x, scp_sdca_stat2=0x%x\n", __func__,
rt711->scp_sdca_stat1, rt711->scp_sdca_stat2);
snd_soc_jack_report(rt711->hs_jack, rt711->jack_type | btn_type,
SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3);
if (btn_type) {
/* button released */
snd_soc_jack_report(rt711->hs_jack, rt711->jack_type,
SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3);
mod_delayed_work(system_power_efficient_wq,
&rt711->jack_btn_check_work, msecs_to_jiffies(200));
}
}
static void rt711_sdca_btn_check_handler(struct work_struct *work)
{
struct rt711_sdca_priv *rt711 =
container_of(work, struct rt711_sdca_priv, jack_btn_check_work.work);
int btn_type = 0, ret, idx;
unsigned int det_mode, offset, val;
unsigned char buf[3];
ret = regmap_read(rt711->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_GE49, RT711_SDCA_CTL_DETECTED_MODE, 0),
&det_mode);
if (ret < 0)
goto io_error;
/* pin attached */
if (det_mode) {
/* read UMP message offset */
ret = regmap_read(rt711->regmap,
SDW_SDCA_CTL(FUNC_NUM_HID, RT711_SDCA_ENT_HID01, RT711_SDCA_CTL_HIDTX_MESSAGE_OFFSET, 0),
&offset);
if (ret < 0)
goto io_error;
for (idx = 0; idx < sizeof(buf); idx++) {
ret = regmap_read(rt711->regmap,
RT711_BUF_ADDR_HID1 + offset + idx, &val);
if (ret < 0)
goto io_error;
buf[idx] = val & 0xff;
}
if (buf[0] == 0x11) {
switch (buf[1] & 0xf0) {
case 0x10:
btn_type |= SND_JACK_BTN_2;
break;
case 0x20:
btn_type |= SND_JACK_BTN_3;
break;
case 0x40:
btn_type |= SND_JACK_BTN_0;
break;
case 0x80:
btn_type |= SND_JACK_BTN_1;
break;
}
switch (buf[2]) {
case 0x01:
case 0x10:
btn_type |= SND_JACK_BTN_2;
break;
case 0x02:
case 0x20:
btn_type |= SND_JACK_BTN_3;
break;
case 0x04:
case 0x40:
btn_type |= SND_JACK_BTN_0;
break;
case 0x08:
case 0x80:
btn_type |= SND_JACK_BTN_1;
break;
}
}
} else
rt711->jack_type = 0;
dev_dbg(&rt711->slave->dev, "%s, btn_type=0x%x\n", __func__, btn_type);
snd_soc_jack_report(rt711->hs_jack, rt711->jack_type | btn_type,
SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3);
if (btn_type) {
/* button released */
snd_soc_jack_report(rt711->hs_jack, rt711->jack_type,
SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3);
mod_delayed_work(system_power_efficient_wq,
&rt711->jack_btn_check_work, msecs_to_jiffies(200));
}
return;
io_error:
pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret);
}
static void rt711_sdca_jack_init(struct rt711_sdca_priv *rt711)
{
mutex_lock(&rt711->calibrate_mutex);
if (rt711->hs_jack) {
/* Enable HID1 event & set button RTC mode */
rt711_sdca_index_update_bits(rt711, RT711_VENDOR_HDA_CTL,
RT711_PUSH_BTN_INT_CTL6, 0x80f0, 0x8000);
rt711_sdca_index_update_bits(rt711, RT711_VENDOR_HDA_CTL,
RT711_PUSH_BTN_INT_CTL2, 0x11dd, 0x11dd);
rt711_sdca_index_write(rt711, RT711_VENDOR_HDA_CTL,
RT711_PUSH_BTN_INT_CTL7, 0xffff);
rt711_sdca_index_update_bits(rt711, RT711_VENDOR_HDA_CTL,
RT711_PUSH_BTN_INT_CTL9, 0xf000, 0x0000);
/* GE_mode_change_event_en & Hid1_push_button_event_en */
rt711_sdca_index_update_bits(rt711, RT711_VENDOR_HDA_CTL,
RT711_GE_MODE_RELATED_CTL, 0x0c00, 0x0c00);
switch (rt711->jd_src) {
case RT711_JD1:
/* default settings was already for JD1 */
break;
case RT711_JD2:
rt711_sdca_index_update_bits(rt711, RT711_VENDOR_REG,
RT711_JD_CTL1, RT711_JD2_DIGITAL_MODE_SEL,
RT711_JD2_DIGITAL_MODE_SEL);
rt711_sdca_index_update_bits(rt711, RT711_VENDOR_REG,
RT711_JD_CTL2, RT711_JD2_2PORT_200K_DECODE_HP | RT711_HP_JD_SEL_JD2,
RT711_JD2_2PORT_200K_DECODE_HP | RT711_HP_JD_SEL_JD2);
rt711_sdca_index_update_bits(rt711, RT711_VENDOR_REG,
RT711_CC_DET1,
RT711_HP_JD_FINAL_RESULT_CTL_JD12,
RT711_HP_JD_FINAL_RESULT_CTL_JD12);
break;
case RT711_JD2_100K:
rt711_sdca_index_write(rt711, RT711_VENDOR_REG,
RT711_COMBO_JACK_AUTO_CTL3, 0xa47e);
rt711_sdca_index_update_bits(rt711, RT711_VENDOR_REG,
RT711_JD_CTL1, RT711_JD2_DIGITAL_MODE_SEL,
RT711_JD2_DIGITAL_MODE_SEL);
rt711_sdca_index_update_bits(rt711, RT711_VENDOR_REG,
RT711_JD_CTL2, RT711_JD2_2PORT_200K_DECODE_HP |
RT711_JD2_2PORT_100K_DECODE_MASK | RT711_HP_JD_SEL_JD2,
RT711_JD2_2PORT_100K_DECODE_HP | RT711_HP_JD_SEL_JD2);
rt711_sdca_index_update_bits(rt711, RT711_VENDOR_REG,
RT711_CC_DET1,
RT711_HP_JD_FINAL_RESULT_CTL_JD12 | RT711_POW_CC1_AGPI,
RT711_HP_JD_FINAL_RESULT_CTL_JD12 | RT711_POW_CC1_AGPI_OFF);
break;
default:
dev_warn(rt711->component->dev, "Wrong JD source\n");
break;
}
/* set SCP_SDCA_IntMask1[0]=1 */
sdw_write_no_pm(rt711->slave, SDW_SCP_SDCA_INTMASK1, SDW_SCP_SDCA_INTMASK_SDCA_0);
/* set SCP_SDCA_IntMask2[0]=1 */
sdw_write_no_pm(rt711->slave, SDW_SCP_SDCA_INTMASK2, SDW_SCP_SDCA_INTMASK_SDCA_8);
dev_dbg(&rt711->slave->dev, "in %s enable\n", __func__);
} else {
/* disable HID 1/2 event */
rt711_sdca_index_update_bits(rt711, RT711_VENDOR_HDA_CTL,
RT711_GE_MODE_RELATED_CTL, 0x0c00, 0x0000);
dev_dbg(&rt711->slave->dev, "in %s disable\n", __func__);
}
mutex_unlock(&rt711->calibrate_mutex);
}
static int rt711_sdca_set_jack_detect(struct snd_soc_component *component,
struct snd_soc_jack *hs_jack, void *data)
{
struct rt711_sdca_priv *rt711 = snd_soc_component_get_drvdata(component);
int ret;
rt711->hs_jack = hs_jack;
/* we can only resume if the device was initialized at least once */
if (!rt711->first_hw_init)
return 0;
ret = pm_runtime_resume_and_get(component->dev);
if (ret < 0) {
if (ret != -EACCES) {
dev_err(component->dev, "%s: failed to resume %d\n", __func__, ret);
return ret;
}
/* pm_runtime not enabled yet */
dev_dbg(component->dev, "%s: skipping jack init for now\n", __func__);
return 0;
}
rt711_sdca_jack_init(rt711);
pm_runtime_mark_last_busy(component->dev);
pm_runtime_put_autosuspend(component->dev);
return 0;
}
/* For SDCA control DAC/ADC Gain */
static int rt711_sdca_set_gain_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct rt711_sdca_priv *rt711 = snd_soc_component_get_drvdata(component);
unsigned int read_l, read_r, gain_l_val, gain_r_val;
unsigned int i, adc_vol_flag = 0, changed = 0;
unsigned int lvalue, rvalue;
if (strstr(ucontrol->id.name, "FU1E Capture Volume") ||
strstr(ucontrol->id.name, "FU0F Capture Volume"))
adc_vol_flag = 1;
regmap_read(rt711->mbq_regmap, mc->reg, &lvalue);
regmap_read(rt711->mbq_regmap, mc->rreg, &rvalue);
/* control value to 2's complement value */
/* L Channel */
gain_l_val = ucontrol->value.integer.value[0];
if (gain_l_val > mc->max)
gain_l_val = mc->max;
read_l = gain_l_val;
if (mc->shift == 8) /* boost gain */
gain_l_val = (gain_l_val * 10) << mc->shift;
else { /* ADC/DAC gain */
if (adc_vol_flag && gain_l_val > mc->shift)
gain_l_val = (gain_l_val - mc->shift) * 75;
else
gain_l_val = (mc->shift - gain_l_val) * 75;
gain_l_val <<= 8;
gain_l_val /= 100;
if (!(adc_vol_flag && read_l > mc->shift)) {
gain_l_val = ~gain_l_val;
gain_l_val += 1;
}
gain_l_val &= 0xffff;
}
/* R Channel */
gain_r_val = ucontrol->value.integer.value[1];
if (gain_r_val > mc->max)
gain_r_val = mc->max;
read_r = gain_r_val;
if (mc->shift == 8) /* boost gain */
gain_r_val = (gain_r_val * 10) << mc->shift;
else { /* ADC/DAC gain */
if (adc_vol_flag && gain_r_val > mc->shift)
gain_r_val = (gain_r_val - mc->shift) * 75;
else
gain_r_val = (mc->shift - gain_r_val) * 75;
gain_r_val <<= 8;
gain_r_val /= 100;
if (!(adc_vol_flag && read_r > mc->shift)) {
gain_r_val = ~gain_r_val;
gain_r_val += 1;
}
gain_r_val &= 0xffff;
}
if (lvalue != gain_l_val || rvalue != gain_r_val)
changed = 1;
else
return 0;
for (i = 0; i < 3; i++) { /* retry 3 times at most */
/* Lch*/
regmap_write(rt711->mbq_regmap, mc->reg, gain_l_val);
/* Rch */
regmap_write(rt711->mbq_regmap, mc->rreg, gain_r_val);
regmap_read(rt711->mbq_regmap, mc->reg, &read_l);
regmap_read(rt711->mbq_regmap, mc->rreg, &read_r);
if (read_r == gain_r_val && read_l == gain_l_val)
break;
}
return i == 3 ? -EIO : changed;
}
static int rt711_sdca_set_gain_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt711_sdca_priv *rt711 = snd_soc_component_get_drvdata(component);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
unsigned int read_l, read_r, ctl_l = 0, ctl_r = 0;
unsigned int adc_vol_flag = 0, neg_flag = 0;
if (strstr(ucontrol->id.name, "FU1E Capture Volume") ||
strstr(ucontrol->id.name, "FU0F Capture Volume"))
adc_vol_flag = 1;
regmap_read(rt711->mbq_regmap, mc->reg, &read_l);
regmap_read(rt711->mbq_regmap, mc->rreg, &read_r);
/* 2's complement value to control value */
if (mc->shift == 8) /* boost gain */
ctl_l = (read_l >> mc->shift) / 10;
else { /* ADC/DAC gain */
ctl_l = read_l;
if (read_l & BIT(15)) {
ctl_l = 0xffff & ~(read_l - 1);
neg_flag = 1;
}
ctl_l *= 100;
ctl_l >>= 8;
if (adc_vol_flag) {
if (neg_flag)
ctl_l = mc->shift - (ctl_l / 75);
else
ctl_l = mc->shift + (ctl_l / 75);
} else
ctl_l = mc->max - (ctl_l / 75);
}
neg_flag = 0;
if (read_l != read_r) {
if (mc->shift == 8) /* boost gain */
ctl_r = (read_r >> mc->shift) / 10;
else { /* ADC/DAC gain */
ctl_r = read_r;
if (read_r & BIT(15)) {
ctl_r = 0xffff & ~(read_r - 1);
neg_flag = 1;
}
ctl_r *= 100;
ctl_r >>= 8;
if (adc_vol_flag) {
if (neg_flag)
ctl_r = mc->shift - (ctl_r / 75);
else
ctl_r = mc->shift + (ctl_r / 75);
} else
ctl_r = mc->max - (ctl_r / 75);
}
} else
ctl_r = ctl_l;
ucontrol->value.integer.value[0] = ctl_l;
ucontrol->value.integer.value[1] = ctl_r;
return 0;
}
static int rt711_sdca_set_fu0f_capture_ctl(struct rt711_sdca_priv *rt711)
{
int err;
unsigned int ch_l, ch_r;
ch_l = (rt711->fu0f_dapm_mute || rt711->fu0f_mixer_l_mute) ? 0x01 : 0x00;
ch_r = (rt711->fu0f_dapm_mute || rt711->fu0f_mixer_r_mute) ? 0x01 : 0x00;
err = regmap_write(rt711->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_USER_FU0F,
RT711_SDCA_CTL_FU_MUTE, CH_L), ch_l);
if (err < 0)
return err;
err = regmap_write(rt711->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_USER_FU0F,
RT711_SDCA_CTL_FU_MUTE, CH_R), ch_r);
if (err < 0)
return err;
return 0;
}
static int rt711_sdca_set_fu1e_capture_ctl(struct rt711_sdca_priv *rt711)
{
int err;
unsigned int ch_l, ch_r;
ch_l = (rt711->fu1e_dapm_mute || rt711->fu1e_mixer_l_mute) ? 0x01 : 0x00;
ch_r = (rt711->fu1e_dapm_mute || rt711->fu1e_mixer_r_mute) ? 0x01 : 0x00;
err = regmap_write(rt711->regmap,
SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT711_SDCA_ENT_USER_FU1E,
RT711_SDCA_CTL_FU_MUTE, CH_L), ch_l);
if (err < 0)
return err;
err = regmap_write(rt711->regmap,
SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT711_SDCA_ENT_USER_FU1E,
RT711_SDCA_CTL_FU_MUTE, CH_R), ch_r);
if (err < 0)
return err;
return 0;
}
static int rt711_sdca_fu1e_capture_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt711_sdca_priv *rt711 = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = !rt711->fu1e_mixer_l_mute;
ucontrol->value.integer.value[1] = !rt711->fu1e_mixer_r_mute;
return 0;
}
static int rt711_sdca_fu1e_capture_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt711_sdca_priv *rt711 = snd_soc_component_get_drvdata(component);
int err, changed = 0;
if (rt711->fu1e_mixer_l_mute != !ucontrol->value.integer.value[0] ||
rt711->fu1e_mixer_r_mute != !ucontrol->value.integer.value[1])
changed = 1;
rt711->fu1e_mixer_l_mute = !ucontrol->value.integer.value[0];
rt711->fu1e_mixer_r_mute = !ucontrol->value.integer.value[1];
err = rt711_sdca_set_fu1e_capture_ctl(rt711);
if (err < 0)
return err;
return changed;
}
static int rt711_sdca_fu0f_capture_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt711_sdca_priv *rt711 = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = !rt711->fu0f_mixer_l_mute;
ucontrol->value.integer.value[1] = !rt711->fu0f_mixer_r_mute;
return 0;
}
static int rt711_sdca_fu0f_capture_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt711_sdca_priv *rt711 = snd_soc_component_get_drvdata(component);
int err, changed = 0;
if (rt711->fu0f_mixer_l_mute != !ucontrol->value.integer.value[0] ||
rt711->fu0f_mixer_r_mute != !ucontrol->value.integer.value[1])
changed = 1;
rt711->fu0f_mixer_l_mute = !ucontrol->value.integer.value[0];
rt711->fu0f_mixer_r_mute = !ucontrol->value.integer.value[1];
err = rt711_sdca_set_fu0f_capture_ctl(rt711);
if (err < 0)
return err;
return changed;
}
static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0);
static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -1725, 75, 0);
static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
static const struct snd_kcontrol_new rt711_sdca_snd_controls[] = {
SOC_DOUBLE_R_EXT_TLV("FU05 Playback Volume",
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_USER_FU05, RT711_SDCA_CTL_FU_VOLUME, CH_L),
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_USER_FU05, RT711_SDCA_CTL_FU_VOLUME, CH_R),
0x57, 0x57, 0,
rt711_sdca_set_gain_get, rt711_sdca_set_gain_put, out_vol_tlv),
SOC_DOUBLE_EXT("FU1E Capture Switch", SND_SOC_NOPM, 0, 1, 1, 0,
rt711_sdca_fu1e_capture_get, rt711_sdca_fu1e_capture_put),
SOC_DOUBLE_EXT("FU0F Capture Switch", SND_SOC_NOPM, 0, 1, 1, 0,
rt711_sdca_fu0f_capture_get, rt711_sdca_fu0f_capture_put),
SOC_DOUBLE_R_EXT_TLV("FU1E Capture Volume",
SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT711_SDCA_ENT_USER_FU1E, RT711_SDCA_CTL_FU_VOLUME, CH_L),
SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT711_SDCA_ENT_USER_FU1E, RT711_SDCA_CTL_FU_VOLUME, CH_R),
0x17, 0x3f, 0,
rt711_sdca_set_gain_get, rt711_sdca_set_gain_put, in_vol_tlv),
SOC_DOUBLE_R_EXT_TLV("FU0F Capture Volume",
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_USER_FU0F, RT711_SDCA_CTL_FU_VOLUME, CH_L),
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_USER_FU0F, RT711_SDCA_CTL_FU_VOLUME, CH_R),
0x17, 0x3f, 0,
rt711_sdca_set_gain_get, rt711_sdca_set_gain_put, in_vol_tlv),
SOC_DOUBLE_R_EXT_TLV("FU44 Gain Volume",
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_PLATFORM_FU44, RT711_SDCA_CTL_FU_CH_GAIN, CH_L),
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_PLATFORM_FU44, RT711_SDCA_CTL_FU_CH_GAIN, CH_R),
8, 3, 0,
rt711_sdca_set_gain_get, rt711_sdca_set_gain_put, mic_vol_tlv),
SOC_DOUBLE_R_EXT_TLV("FU15 Gain Volume",
SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT711_SDCA_ENT_PLATFORM_FU15, RT711_SDCA_CTL_FU_CH_GAIN, CH_L),
SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT711_SDCA_ENT_PLATFORM_FU15, RT711_SDCA_CTL_FU_CH_GAIN, CH_R),
8, 3, 0,
rt711_sdca_set_gain_get, rt711_sdca_set_gain_put, mic_vol_tlv),
};
static int rt711_sdca_mux_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_dapm_kcontrol_component(kcontrol);
struct rt711_sdca_priv *rt711 = snd_soc_component_get_drvdata(component);
unsigned int val = 0, mask_sft;
if (strstr(ucontrol->id.name, "ADC 22 Mux"))
mask_sft = 10;
else if (strstr(ucontrol->id.name, "ADC 23 Mux"))
mask_sft = 13;
else
return -EINVAL;
rt711_sdca_index_read(rt711, RT711_VENDOR_HDA_CTL,
RT711_HDA_LEGACY_MUX_CTL1, &val);
ucontrol->value.enumerated.item[0] = (val >> mask_sft) & 0x7;
return 0;
}
static int rt711_sdca_mux_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_dapm_kcontrol_component(kcontrol);
struct snd_soc_dapm_context *dapm =
snd_soc_dapm_kcontrol_dapm(kcontrol);
struct rt711_sdca_priv *rt711 = snd_soc_component_get_drvdata(component);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int *item = ucontrol->value.enumerated.item;
unsigned int val, val2 = 0, change, mask_sft;
if (item[0] >= e->items)
return -EINVAL;
if (strstr(ucontrol->id.name, "ADC 22 Mux"))
mask_sft = 10;
else if (strstr(ucontrol->id.name, "ADC 23 Mux"))
mask_sft = 13;
else
return -EINVAL;
val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
rt711_sdca_index_read(rt711, RT711_VENDOR_HDA_CTL,
RT711_HDA_LEGACY_MUX_CTL1, &val2);
val2 = (val2 >> mask_sft) & 0x7;
if (val == val2)
change = 0;
else
change = 1;
if (change)
rt711_sdca_index_update_bits(rt711, RT711_VENDOR_HDA_CTL,
RT711_HDA_LEGACY_MUX_CTL1, 0x7 << mask_sft,
val << mask_sft);
snd_soc_dapm_mux_update_power(dapm, kcontrol,
item[0], e, NULL);
return change;
}
static const char * const adc_mux_text[] = {
"MIC2",
"LINE1",
"LINE2",
"DMIC",
};
static SOC_ENUM_SINGLE_DECL(
rt711_adc22_enum, SND_SOC_NOPM, 0, adc_mux_text);
static SOC_ENUM_SINGLE_DECL(
rt711_adc23_enum, SND_SOC_NOPM, 0, adc_mux_text);
static const struct snd_kcontrol_new rt711_sdca_adc22_mux =
SOC_DAPM_ENUM_EXT("ADC 22 Mux", rt711_adc22_enum,
rt711_sdca_mux_get, rt711_sdca_mux_put);
static const struct snd_kcontrol_new rt711_sdca_adc23_mux =
SOC_DAPM_ENUM_EXT("ADC 23 Mux", rt711_adc23_enum,
rt711_sdca_mux_get, rt711_sdca_mux_put);
static int rt711_sdca_fu05_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt711_sdca_priv *rt711 = snd_soc_component_get_drvdata(component);
unsigned char unmute = 0x0, mute = 0x1;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_write(rt711->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_USER_FU05,
RT711_SDCA_CTL_FU_MUTE, CH_L),
unmute);
regmap_write(rt711->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_USER_FU05,
RT711_SDCA_CTL_FU_MUTE, CH_R),
unmute);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_write(rt711->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_USER_FU05,
RT711_SDCA_CTL_FU_MUTE, CH_L),
mute);
regmap_write(rt711->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_USER_FU05,
RT711_SDCA_CTL_FU_MUTE, CH_R),
mute);
break;
}
return 0;
}
static int rt711_sdca_fu0f_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt711_sdca_priv *rt711 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
rt711->fu0f_dapm_mute = false;
rt711_sdca_set_fu0f_capture_ctl(rt711);
break;
case SND_SOC_DAPM_PRE_PMD:
rt711->fu0f_dapm_mute = true;
rt711_sdca_set_fu0f_capture_ctl(rt711);
break;
}
return 0;
}
static int rt711_sdca_fu1e_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt711_sdca_priv *rt711 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
rt711->fu1e_dapm_mute = false;
rt711_sdca_set_fu1e_capture_ctl(rt711);
break;
case SND_SOC_DAPM_PRE_PMD:
rt711->fu1e_dapm_mute = true;
rt711_sdca_set_fu1e_capture_ctl(rt711);
break;
}
return 0;
}
static int rt711_sdca_pde28_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt711_sdca_priv *rt711 = snd_soc_component_get_drvdata(component);
unsigned char ps0 = 0x0, ps3 = 0x3;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_write(rt711->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_PDE28,
RT711_SDCA_CTL_REQ_POWER_STATE, 0),
ps0);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_write(rt711->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_PDE28,
RT711_SDCA_CTL_REQ_POWER_STATE, 0),
ps3);
break;
}
return 0;
}
static int rt711_sdca_pde29_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt711_sdca_priv *rt711 = snd_soc_component_get_drvdata(component);
unsigned char ps0 = 0x0, ps3 = 0x3;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_write(rt711->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_PDE29,
RT711_SDCA_CTL_REQ_POWER_STATE, 0),
ps0);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_write(rt711->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_PDE29,
RT711_SDCA_CTL_REQ_POWER_STATE, 0),
ps3);
break;
}
return 0;
}
static int rt711_sdca_pde2a_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt711_sdca_priv *rt711 = snd_soc_component_get_drvdata(component);
unsigned char ps0 = 0x0, ps3 = 0x3;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_write(rt711->regmap,
SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT711_SDCA_ENT_PDE2A,
RT711_SDCA_CTL_REQ_POWER_STATE, 0),
ps0);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_write(rt711->regmap,
SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT711_SDCA_ENT_PDE2A,
RT711_SDCA_CTL_REQ_POWER_STATE, 0),
ps3);
break;
}
return 0;
}
static int rt711_sdca_line1_power_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt711_sdca_priv *rt711 = snd_soc_component_get_drvdata(component);
static unsigned int sel_mode = 0xffff;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_read(rt711->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_GE49,
RT711_SDCA_CTL_SELECTED_MODE, 0),
&sel_mode);
regmap_write(rt711->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_LINE1,
RT711_SDCA_CTL_VENDOR_DEF, 0),
0x1);
regmap_write(rt711->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_GE49,
RT711_SDCA_CTL_SELECTED_MODE, 0),
0x7);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_write(rt711->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_LINE1,
RT711_SDCA_CTL_VENDOR_DEF, 0),
0x0);
if (sel_mode != 0xffff)
regmap_write(rt711->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_GE49,
RT711_SDCA_CTL_SELECTED_MODE, 0),
sel_mode);
break;
}
return 0;
}
static int rt711_sdca_line2_power_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt711_sdca_priv *rt711 = snd_soc_component_get_drvdata(component);
unsigned char ps0 = 0x0, ps3 = 0x3;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_write(rt711->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_PDELINE2,
RT711_SDCA_CTL_REQ_POWER_STATE, 0),
ps0);
regmap_write(rt711->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_LINE2,
RT711_SDCA_CTL_VENDOR_DEF, 0),
0x1);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_write(rt711->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_LINE2,
RT711_SDCA_CTL_VENDOR_DEF, 0),
0x0);
regmap_write(rt711->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_PDELINE2,
RT711_SDCA_CTL_REQ_POWER_STATE, 0),
ps3);
break;
}
return 0;
}
static const struct snd_soc_dapm_widget rt711_sdca_dapm_widgets[] = {
SND_SOC_DAPM_OUTPUT("HP"),
SND_SOC_DAPM_INPUT("MIC2"),
SND_SOC_DAPM_INPUT("DMIC1"),
SND_SOC_DAPM_INPUT("DMIC2"),
SND_SOC_DAPM_INPUT("LINE1"),
SND_SOC_DAPM_INPUT("LINE2"),
SND_SOC_DAPM_PGA_E("LINE1 Power", SND_SOC_NOPM,
0, 0, NULL, 0, rt711_sdca_line1_power_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA_E("LINE2 Power", SND_SOC_NOPM,
0, 0, NULL, 0, rt711_sdca_line2_power_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SUPPLY("PDE 28", SND_SOC_NOPM, 0, 0,
rt711_sdca_pde28_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SUPPLY("PDE 29", SND_SOC_NOPM, 0, 0,
rt711_sdca_pde29_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SUPPLY("PDE 2A", SND_SOC_NOPM, 0, 0,
rt711_sdca_pde2a_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_DAC_E("FU 05", NULL, SND_SOC_NOPM, 0, 0,
rt711_sdca_fu05_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_ADC_E("FU 0F", NULL, SND_SOC_NOPM, 0, 0,
rt711_sdca_fu0f_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_ADC_E("FU 1E", NULL, SND_SOC_NOPM, 0, 0,
rt711_sdca_fu1e_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_MUX("ADC 22 Mux", SND_SOC_NOPM, 0, 0,
&rt711_sdca_adc22_mux),
SND_SOC_DAPM_MUX("ADC 23 Mux", SND_SOC_NOPM, 0, 0,
&rt711_sdca_adc23_mux),
SND_SOC_DAPM_AIF_IN("DP3RX", "DP3 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("DP2TX", "DP2 Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0),
};
static const struct snd_soc_dapm_route rt711_sdca_audio_map[] = {
{"FU 05", NULL, "DP3RX"},
{"DP2TX", NULL, "FU 0F"},
{"DP4TX", NULL, "FU 1E"},
{"LINE1 Power", NULL, "LINE1"},
{"LINE2 Power", NULL, "LINE2"},
{"HP", NULL, "PDE 28"},
{"FU 0F", NULL, "PDE 29"},
{"FU 1E", NULL, "PDE 2A"},
{"FU 0F", NULL, "ADC 22 Mux"},
{"FU 1E", NULL, "ADC 23 Mux"},
{"ADC 22 Mux", "DMIC", "DMIC1"},
{"ADC 22 Mux", "LINE1", "LINE1 Power"},
{"ADC 22 Mux", "LINE2", "LINE2 Power"},
{"ADC 22 Mux", "MIC2", "MIC2"},
{"ADC 23 Mux", "DMIC", "DMIC2"},
{"ADC 23 Mux", "LINE1", "LINE1 Power"},
{"ADC 23 Mux", "LINE2", "LINE2 Power"},
{"ADC 23 Mux", "MIC2", "MIC2"},
{"HP", NULL, "FU 05"},
};
static int rt711_sdca_parse_dt(struct rt711_sdca_priv *rt711, struct device *dev)
{
device_property_read_u32(dev, "realtek,jd-src", &rt711->jd_src);
return 0;
}
static int rt711_sdca_probe(struct snd_soc_component *component)
{
struct rt711_sdca_priv *rt711 = snd_soc_component_get_drvdata(component);
int ret;
rt711_sdca_parse_dt(rt711, &rt711->slave->dev);
rt711->component = component;
if (!rt711->first_hw_init)
return 0;
ret = pm_runtime_resume(component->dev);
if (ret < 0 && ret != -EACCES)
return ret;
return 0;
}
static const struct snd_soc_component_driver soc_sdca_dev_rt711 = {
.probe = rt711_sdca_probe,
.controls = rt711_sdca_snd_controls,
.num_controls = ARRAY_SIZE(rt711_sdca_snd_controls),
.dapm_widgets = rt711_sdca_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt711_sdca_dapm_widgets),
.dapm_routes = rt711_sdca_audio_map,
.num_dapm_routes = ARRAY_SIZE(rt711_sdca_audio_map),
.set_jack = rt711_sdca_set_jack_detect,
.endianness = 1,
};
static int rt711_sdca_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
int direction)
{
snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
return 0;
}
static void rt711_sdca_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
snd_soc_dai_set_dma_data(dai, substream, NULL);
}
static int rt711_sdca_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt711_sdca_priv *rt711 = snd_soc_component_get_drvdata(component);
struct sdw_stream_config stream_config = {0};
struct sdw_port_config port_config = {0};
struct sdw_stream_runtime *sdw_stream;
int retval;
unsigned int sampling_rate;
dev_dbg(dai->dev, "%s %s", __func__, dai->name);
sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
if (!sdw_stream)
return -EINVAL;
if (!rt711->slave)
return -EINVAL;
/* SoundWire specific configuration */
snd_sdw_params_to_config(substream, params, &stream_config, &port_config);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
port_config.num = 3;
} else {
if (dai->id == RT711_AIF1)
port_config.num = 2;
else if (dai->id == RT711_AIF2)
port_config.num = 4;
else
return -EINVAL;
}
retval = sdw_stream_add_slave(rt711->slave, &stream_config,
&port_config, 1, sdw_stream);
if (retval) {
dev_err(dai->dev, "Unable to configure port\n");
return retval;
}
if (params_channels(params) > 16) {
dev_err(component->dev, "Unsupported channels %d\n",
params_channels(params));
return -EINVAL;
}
/* sampling rate configuration */
switch (params_rate(params)) {
case 44100:
sampling_rate = RT711_SDCA_RATE_44100HZ;
break;
case 48000:
sampling_rate = RT711_SDCA_RATE_48000HZ;
break;
case 96000:
sampling_rate = RT711_SDCA_RATE_96000HZ;
break;
case 192000:
sampling_rate = RT711_SDCA_RATE_192000HZ;
break;
default:
dev_err(component->dev, "Rate %d is not supported\n",
params_rate(params));
return -EINVAL;
}
/* set sampling frequency */
regmap_write(rt711->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_CS01, RT711_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
sampling_rate);
regmap_write(rt711->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_CS11, RT711_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
sampling_rate);
regmap_write(rt711->regmap,
SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT711_SDCA_ENT_CS1F, RT711_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
sampling_rate);
return 0;
}
static int rt711_sdca_pcm_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt711_sdca_priv *rt711 = snd_soc_component_get_drvdata(component);
struct sdw_stream_runtime *sdw_stream =
snd_soc_dai_get_dma_data(dai, substream);
if (!rt711->slave)
return -EINVAL;
sdw_stream_remove_slave(rt711->slave, sdw_stream);
return 0;
}
#define RT711_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | \
SNDRV_PCM_RATE_192000)
#define RT711_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE)
static const struct snd_soc_dai_ops rt711_sdca_ops = {
.hw_params = rt711_sdca_pcm_hw_params,
.hw_free = rt711_sdca_pcm_hw_free,
.set_stream = rt711_sdca_set_sdw_stream,
.shutdown = rt711_sdca_shutdown,
};
static struct snd_soc_dai_driver rt711_sdca_dai[] = {
{
.name = "rt711-sdca-aif1",
.id = RT711_AIF1,
.playback = {
.stream_name = "DP3 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT711_STEREO_RATES,
.formats = RT711_FORMATS,
},
.capture = {
.stream_name = "DP2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT711_STEREO_RATES,
.formats = RT711_FORMATS,
},
.ops = &rt711_sdca_ops,
},
{
.name = "rt711-sdca-aif2",
.id = RT711_AIF2,
.capture = {
.stream_name = "DP4 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT711_STEREO_RATES,
.formats = RT711_FORMATS,
},
.ops = &rt711_sdca_ops,
}
};
int rt711_sdca_init(struct device *dev, struct regmap *regmap,
struct regmap *mbq_regmap, struct sdw_slave *slave)
{
struct rt711_sdca_priv *rt711;
int ret;
rt711 = devm_kzalloc(dev, sizeof(*rt711), GFP_KERNEL);
if (!rt711)
return -ENOMEM;
dev_set_drvdata(dev, rt711);
rt711->slave = slave;
rt711->regmap = regmap;
rt711->mbq_regmap = mbq_regmap;
regcache_cache_only(rt711->regmap, true);
regcache_cache_only(rt711->mbq_regmap, true);
mutex_init(&rt711->calibrate_mutex);
mutex_init(&rt711->disable_irq_lock);
INIT_DELAYED_WORK(&rt711->jack_detect_work, rt711_sdca_jack_detect_handler);
INIT_DELAYED_WORK(&rt711->jack_btn_check_work, rt711_sdca_btn_check_handler);
/*
* Mark hw_init to false
* HW init will be performed when device reports present
*/
rt711->hw_init = false;
rt711->first_hw_init = false;
rt711->fu0f_dapm_mute = true;
rt711->fu1e_dapm_mute = true;
rt711->fu0f_mixer_l_mute = rt711->fu0f_mixer_r_mute = true;
rt711->fu1e_mixer_l_mute = rt711->fu1e_mixer_r_mute = true;
/* JD source uses JD2 in default */
rt711->jd_src = RT711_JD2;
ret = devm_snd_soc_register_component(dev,
&soc_sdca_dev_rt711,
rt711_sdca_dai,
ARRAY_SIZE(rt711_sdca_dai));
if (ret < 0)
return ret;
/* set autosuspend parameters */
pm_runtime_set_autosuspend_delay(dev, 3000);
pm_runtime_use_autosuspend(dev);
/* make sure the device does not suspend immediately */
pm_runtime_mark_last_busy(dev);
pm_runtime_enable(dev);
/* important note: the device is NOT tagged as 'active' and will remain
* 'suspended' until the hardware is enumerated/initialized. This is required
* to make sure the ASoC framework use of pm_runtime_get_sync() does not silently
* fail with -EACCESS because of race conditions between card creation and enumeration
*/
dev_dbg(dev, "%s\n", __func__);
return 0;
}
static void rt711_sdca_vd0_io_init(struct rt711_sdca_priv *rt711)
{
rt711_sdca_index_write(rt711, RT711_VENDOR_REG,
RT711_GPIO_TEST_MODE_CTL2, 0x0e00);
rt711_sdca_index_write(rt711, RT711_VENDOR_HDA_CTL,
RT711_HDA_LEGACY_GPIO_CTL, 0x0008);
regmap_write(rt711->regmap, 0x2f5a, 0x01);
rt711_sdca_index_write(rt711, RT711_VENDOR_REG,
RT711_ADC27_VOL_SET, 0x8728);
rt711_sdca_index_write(rt711, RT711_VENDOR_REG,
RT711_COMBO_JACK_AUTO_CTL3, 0xa472);
regmap_write(rt711->regmap, 0x2f50, 0x02);
rt711_sdca_index_update_bits(rt711, RT711_VENDOR_ANALOG_CTL,
RT711_MISC_POWER_CTL4, 0x6000, 0x6000);
rt711_sdca_index_update_bits(rt711, RT711_VENDOR_REG,
RT711_COMBO_JACK_AUTO_CTL3, 0x000c, 0x000c);
rt711_sdca_index_write(rt711, RT711_VENDOR_HDA_CTL,
RT711_HDA_LEGACY_CONFIG_CTL, 0x0000);
rt711_sdca_index_write(rt711, RT711_VENDOR_VAD,
RT711_VAD_SRAM_CTL1, 0x0050);
}
static void rt711_sdca_vd1_io_init(struct rt711_sdca_priv *rt711)
{
rt711_sdca_index_update_bits(rt711, RT711_VENDOR_HDA_CTL,
RT711_HDA_LEGACY_UNSOLICITED_CTL, 0x0300, 0x0000);
rt711_sdca_index_write(rt711, RT711_VENDOR_REG,
RT711_COMBO_JACK_AUTO_CTL3, 0xa43e);
regmap_write(rt711->regmap, 0x2f5a, 0x05);
rt711_sdca_index_write(rt711, RT711_VENDOR_REG,
RT711_JD_CTRL6, 0x0500);
rt711_sdca_index_write(rt711, RT711_VENDOR_REG,
RT711_DMIC_CTL1, 0x6173);
rt711_sdca_index_write(rt711, RT711_VENDOR_HDA_CTL,
RT711_HDA_LEGACY_CONFIG_CTL, 0x0000);
rt711_sdca_index_write(rt711, RT711_VENDOR_VAD,
RT711_VAD_SRAM_CTL1, 0x0050);
}
int rt711_sdca_io_init(struct device *dev, struct sdw_slave *slave)
{
struct rt711_sdca_priv *rt711 = dev_get_drvdata(dev);
int ret = 0;
unsigned int val;
rt711->disable_irq = false;
if (rt711->hw_init)
return 0;
regcache_cache_only(rt711->regmap, false);
regcache_cache_only(rt711->mbq_regmap, false);
if (rt711->first_hw_init) {
regcache_cache_bypass(rt711->regmap, true);
regcache_cache_bypass(rt711->mbq_regmap, true);
} else {
/*
* PM runtime status is marked as 'active' only when a Slave reports as Attached
*/
/* update count of parent 'active' children */
pm_runtime_set_active(&slave->dev);
}
pm_runtime_get_noresume(&slave->dev);
rt711_sdca_reset(rt711);
rt711_sdca_index_read(rt711, RT711_VENDOR_REG, RT711_JD_PRODUCT_NUM, &val);
rt711->hw_ver = val & 0xf;
if (rt711->hw_ver == RT711_VER_VD0)
rt711_sdca_vd0_io_init(rt711);
else
rt711_sdca_vd1_io_init(rt711);
/* DP4 mux select from 08_filter_Out_pri */
rt711_sdca_index_update_bits(rt711, RT711_VENDOR_REG,
RT711_FILTER_SRC_SEL, 0x1800, 0x0800);
/* ge_exclusive_inbox_en disable */
rt711_sdca_index_update_bits(rt711, RT711_VENDOR_HDA_CTL,
RT711_PUSH_BTN_INT_CTL0, 0x20, 0x00);
/* calibration */
ret = rt711_sdca_calibration(rt711);
if (ret < 0)
dev_err(dev, "%s, calibration failed!\n", __func__);
/* HP output enable */
regmap_write(rt711->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_OT1, RT711_SDCA_CTL_VENDOR_DEF, 0), 0x4);
/*
* if set_jack callback occurred early than io_init,
* we set up the jack detection function now
*/
if (rt711->hs_jack)
rt711_sdca_jack_init(rt711);
if (rt711->first_hw_init) {
regcache_cache_bypass(rt711->regmap, false);
regcache_mark_dirty(rt711->regmap);
regcache_cache_bypass(rt711->mbq_regmap, false);
regcache_mark_dirty(rt711->mbq_regmap);
} else
rt711->first_hw_init = true;
/* Mark Slave initialization complete */
rt711->hw_init = true;
pm_runtime_mark_last_busy(&slave->dev);
pm_runtime_put_autosuspend(&slave->dev);
dev_dbg(&slave->dev, "%s hw_init complete\n", __func__);
return 0;
}
MODULE_DESCRIPTION("ASoC RT711 SDCA SDW driver");
MODULE_AUTHOR("Shuming Fan <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/rt711-sdca.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// rt1019.c -- RT1019 ALSA SoC audio amplifier driver
// Author: Jack Yu <[email protected]>
//
// Copyright(c) 2021 Realtek Semiconductor Corp.
//
//
#include <linux/acpi.h>
#include <linux/fs.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/regmap.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/firmware.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "rl6231.h"
#include "rt1019.h"
static const struct reg_default rt1019_reg[] = {
{ 0x0000, 0x00 },
{ 0x0011, 0x04 },
{ 0x0013, 0x00 },
{ 0x0019, 0x30 },
{ 0x001b, 0x01 },
{ 0x005c, 0x00 },
{ 0x005e, 0x10 },
{ 0x005f, 0xec },
{ 0x0061, 0x10 },
{ 0x0062, 0x19 },
{ 0x0066, 0x08 },
{ 0x0100, 0x80 },
{ 0x0100, 0x51 },
{ 0x0102, 0x23 },
{ 0x0311, 0x00 },
{ 0x0312, 0x3e },
{ 0x0313, 0x86 },
{ 0x0400, 0x03 },
{ 0x0401, 0x02 },
{ 0x0402, 0x01 },
{ 0x0504, 0xff },
{ 0x0505, 0x24 },
{ 0x0b00, 0x50 },
{ 0x0b01, 0xc3 },
};
static bool rt1019_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case RT1019_PWR_STRP_2:
case RT1019_VER_ID:
case RT1019_VEND_ID_1:
case RT1019_VEND_ID_2:
case RT1019_DEV_ID_1:
case RT1019_DEV_ID_2:
return true;
default:
return false;
}
}
static bool rt1019_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case RT1019_RESET:
case RT1019_IDS_CTRL:
case RT1019_ASEL_CTRL:
case RT1019_PWR_STRP_2:
case RT1019_BEEP_TONE:
case RT1019_VER_ID:
case RT1019_VEND_ID_1:
case RT1019_VEND_ID_2:
case RT1019_DEV_ID_1:
case RT1019_DEV_ID_2:
case RT1019_SDB_CTRL:
case RT1019_CLK_TREE_1:
case RT1019_CLK_TREE_2:
case RT1019_CLK_TREE_3:
case RT1019_PLL_1:
case RT1019_PLL_2:
case RT1019_PLL_3:
case RT1019_TDM_1:
case RT1019_TDM_2:
case RT1019_TDM_3:
case RT1019_DMIX_MONO_1:
case RT1019_DMIX_MONO_2:
case RT1019_BEEP_1:
case RT1019_BEEP_2:
return true;
default:
return false;
}
}
static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9525, 75, 0);
static const char * const rt1019_din_source_select[] = {
"Left",
"Right",
"Left + Right average",
};
static SOC_ENUM_SINGLE_DECL(rt1019_mono_lr_sel, RT1019_IDS_CTRL, 0,
rt1019_din_source_select);
static const struct snd_kcontrol_new rt1019_snd_controls[] = {
SOC_SINGLE_TLV("DAC Playback Volume", RT1019_DMIX_MONO_1, 0,
127, 0, dac_vol_tlv),
SOC_ENUM("Mono LR Select", rt1019_mono_lr_sel),
};
static int r1019_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_component_write(component, RT1019_SDB_CTRL, 0xb);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_write(component, RT1019_SDB_CTRL, 0xa);
break;
default:
break;
}
return 0;
}
static const struct snd_soc_dapm_widget rt1019_dapm_widgets[] = {
SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC_E("DAC", NULL, SND_SOC_NOPM, 0, 0,
r1019_dac_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_OUTPUT("SPO"),
};
static const struct snd_soc_dapm_route rt1019_dapm_routes[] = {
{ "DAC", NULL, "AIFRX" },
{ "SPO", NULL, "DAC" },
};
static int rt1019_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt1019_priv *rt1019 = snd_soc_component_get_drvdata(component);
int pre_div, bclk_ms, frame_size;
unsigned int val_len = 0, sys_div_da_filter = 0;
unsigned int sys_dac_osr = 0, sys_fifo_clk = 0;
unsigned int sys_clk_cal = 0, sys_asrc_in = 0;
rt1019->lrck = params_rate(params);
pre_div = rl6231_get_clk_info(rt1019->sysclk, rt1019->lrck);
if (pre_div < 0) {
dev_err(component->dev, "Unsupported clock setting\n");
return -EINVAL;
}
frame_size = snd_soc_params_to_frame_size(params);
if (frame_size < 0) {
dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
return -EINVAL;
}
bclk_ms = frame_size > 32;
rt1019->bclk = rt1019->lrck * (32 << bclk_ms);
dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
rt1019->bclk, rt1019->lrck);
dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
bclk_ms, pre_div, dai->id);
switch (pre_div) {
case 0:
sys_div_da_filter = RT1019_SYS_DIV_DA_FIL_DIV1;
sys_dac_osr = RT1019_SYS_DA_OSR_DIV1;
sys_asrc_in = RT1019_ASRC_256FS_DIV1;
sys_fifo_clk = RT1019_SEL_FIFO_DIV1;
sys_clk_cal = RT1019_SEL_CLK_CAL_DIV1;
break;
case 1:
sys_div_da_filter = RT1019_SYS_DIV_DA_FIL_DIV2;
sys_dac_osr = RT1019_SYS_DA_OSR_DIV2;
sys_asrc_in = RT1019_ASRC_256FS_DIV2;
sys_fifo_clk = RT1019_SEL_FIFO_DIV2;
sys_clk_cal = RT1019_SEL_CLK_CAL_DIV2;
break;
case 3:
sys_div_da_filter = RT1019_SYS_DIV_DA_FIL_DIV4;
sys_dac_osr = RT1019_SYS_DA_OSR_DIV4;
sys_asrc_in = RT1019_ASRC_256FS_DIV4;
sys_fifo_clk = RT1019_SEL_FIFO_DIV4;
sys_clk_cal = RT1019_SEL_CLK_CAL_DIV4;
break;
default:
return -EINVAL;
}
switch (params_width(params)) {
case 16:
break;
case 20:
val_len = RT1019_I2S_DL_20;
break;
case 24:
val_len = RT1019_I2S_DL_24;
break;
case 32:
val_len = RT1019_I2S_DL_32;
break;
case 8:
val_len = RT1019_I2S_DL_8;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, RT1019_TDM_2, RT1019_I2S_DL_MASK,
val_len);
snd_soc_component_update_bits(component, RT1019_CLK_TREE_1,
RT1019_SEL_FIFO_MASK, sys_fifo_clk);
snd_soc_component_update_bits(component, RT1019_CLK_TREE_2,
RT1019_SYS_DIV_DA_FIL_MASK | RT1019_SYS_DA_OSR_MASK |
RT1019_ASRC_256FS_MASK, sys_div_da_filter | sys_dac_osr |
sys_asrc_in);
snd_soc_component_update_bits(component, RT1019_CLK_TREE_3,
RT1019_SEL_CLK_CAL_MASK, sys_clk_cal);
return 0;
}
static int rt1019_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
unsigned int reg_val = 0, reg_val2 = 0;
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
reg_val2 |= RT1019_TDM_BCLK_INV;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_LEFT_J:
reg_val |= RT1019_I2S_DF_LEFT;
break;
case SND_SOC_DAIFMT_DSP_A:
reg_val |= RT1019_I2S_DF_PCM_A_R;
break;
case SND_SOC_DAIFMT_DSP_B:
reg_val |= RT1019_I2S_DF_PCM_B_R;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, RT1019_TDM_2,
RT1019_I2S_DF_MASK, reg_val);
snd_soc_component_update_bits(component, RT1019_TDM_1,
RT1019_TDM_BCLK_MASK, reg_val2);
return 0;
}
static int rt1019_set_dai_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct rt1019_priv *rt1019 = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0;
if (freq == rt1019->sysclk && clk_id == rt1019->sysclk_src)
return 0;
switch (clk_id) {
case RT1019_SCLK_S_BCLK:
reg_val |= RT1019_CLK_SYS_PRE_SEL_BCLK;
break;
case RT1019_SCLK_S_PLL:
reg_val |= RT1019_CLK_SYS_PRE_SEL_PLL;
break;
default:
dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
return -EINVAL;
}
rt1019->sysclk = freq;
rt1019->sysclk_src = clk_id;
dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
snd_soc_component_update_bits(component, RT1019_CLK_TREE_1,
RT1019_CLK_SYS_PRE_SEL_MASK, reg_val);
return 0;
}
static int rt1019_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
unsigned int freq_in, unsigned int freq_out)
{
struct snd_soc_component *component = dai->component;
struct rt1019_priv *rt1019 = snd_soc_component_get_drvdata(component);
struct rl6231_pll_code pll_code;
int ret;
if (!freq_in || !freq_out) {
dev_dbg(component->dev, "PLL disabled\n");
rt1019->pll_in = 0;
rt1019->pll_out = 0;
return 0;
}
if (source == rt1019->pll_src && freq_in == rt1019->pll_in &&
freq_out == rt1019->pll_out)
return 0;
switch (source) {
case RT1019_PLL_S_BCLK:
snd_soc_component_update_bits(component, RT1019_CLK_TREE_1,
RT1019_PLL_SRC_MASK, RT1019_PLL_SRC_SEL_BCLK);
break;
case RT1019_PLL_S_RC25M:
snd_soc_component_update_bits(component, RT1019_CLK_TREE_1,
RT1019_PLL_SRC_MASK, RT1019_PLL_SRC_SEL_RC);
break;
default:
dev_err(component->dev, "Unknown PLL source %d\n", source);
return -EINVAL;
}
ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
if (ret < 0) {
dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
return ret;
}
dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
pll_code.n_code, pll_code.k_code);
snd_soc_component_update_bits(component, RT1019_PWR_STRP_2,
RT1019_AUTO_BITS_SEL_MASK | RT1019_AUTO_CLK_SEL_MASK,
RT1019_AUTO_BITS_SEL_MANU | RT1019_AUTO_CLK_SEL_MANU);
snd_soc_component_update_bits(component, RT1019_PLL_1,
RT1019_PLL_M_MASK | RT1019_PLL_M_BP_MASK | RT1019_PLL_Q_8_8_MASK,
((pll_code.m_bp ? 0 : pll_code.m_code) << RT1019_PLL_M_SFT) |
(pll_code.m_bp << RT1019_PLL_M_BP_SFT) |
((pll_code.n_code >> 8) & RT1019_PLL_Q_8_8_MASK));
snd_soc_component_update_bits(component, RT1019_PLL_2,
RT1019_PLL_Q_7_0_MASK, pll_code.n_code & RT1019_PLL_Q_7_0_MASK);
snd_soc_component_update_bits(component, RT1019_PLL_3,
RT1019_PLL_K_MASK, pll_code.k_code);
rt1019->pll_in = freq_in;
rt1019->pll_out = freq_out;
rt1019->pll_src = source;
return 0;
}
static int rt1019_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
unsigned int cn = 0, cl = 0, rx_slotnum;
int ret = 0, first_bit;
switch (slots) {
case 4:
cn = RT1019_I2S_TX_4CH;
break;
case 6:
cn = RT1019_I2S_TX_6CH;
break;
case 8:
cn = RT1019_I2S_TX_8CH;
break;
case 2:
break;
default:
return -EINVAL;
}
switch (slot_width) {
case 20:
cl = RT1019_TDM_CL_20;
break;
case 24:
cl = RT1019_TDM_CL_24;
break;
case 32:
cl = RT1019_TDM_CL_32;
break;
case 8:
cl = RT1019_TDM_CL_8;
break;
case 16:
break;
default:
return -EINVAL;
}
/* Rx slot configuration */
rx_slotnum = hweight_long(rx_mask);
if (rx_slotnum != 1) {
ret = -EINVAL;
dev_err(component->dev, "too many rx slots or zero slot\n");
goto _set_tdm_err_;
}
/* This is an assumption that the system sends stereo audio to the
* amplifier typically. And the stereo audio is placed in slot 0/2/4/6
* as the starting slot. The users could select the channel from
* L/R/L+R by "Mono LR Select" control.
*/
first_bit = __ffs(rx_mask);
switch (first_bit) {
case 0:
case 2:
case 4:
case 6:
snd_soc_component_update_bits(component,
RT1019_TDM_3,
RT1019_TDM_I2S_TX_L_DAC1_1_MASK |
RT1019_TDM_I2S_TX_R_DAC1_1_MASK,
(first_bit << RT1019_TDM_I2S_TX_L_DAC1_1_SFT) |
((first_bit + 1) << RT1019_TDM_I2S_TX_R_DAC1_1_SFT));
break;
case 1:
case 3:
case 5:
case 7:
snd_soc_component_update_bits(component,
RT1019_TDM_3,
RT1019_TDM_I2S_TX_L_DAC1_1_MASK |
RT1019_TDM_I2S_TX_R_DAC1_1_MASK,
((first_bit - 1) << RT1019_TDM_I2S_TX_L_DAC1_1_SFT) |
(first_bit << RT1019_TDM_I2S_TX_R_DAC1_1_SFT));
break;
default:
ret = -EINVAL;
goto _set_tdm_err_;
}
snd_soc_component_update_bits(component, RT1019_TDM_1,
RT1019_TDM_CL_MASK, cl);
snd_soc_component_update_bits(component, RT1019_TDM_2,
RT1019_I2S_CH_TX_MASK, cn);
_set_tdm_err_:
return ret;
}
static int rt1019_probe(struct snd_soc_component *component)
{
struct rt1019_priv *rt1019 = snd_soc_component_get_drvdata(component);
rt1019->component = component;
snd_soc_component_write(component, RT1019_SDB_CTRL, 0xa);
return 0;
}
#define RT1019_STEREO_RATES SNDRV_PCM_RATE_8000_192000
#define RT1019_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
static const struct snd_soc_dai_ops rt1019_aif_dai_ops = {
.hw_params = rt1019_hw_params,
.set_fmt = rt1019_set_dai_fmt,
.set_sysclk = rt1019_set_dai_sysclk,
.set_pll = rt1019_set_dai_pll,
.set_tdm_slot = rt1019_set_tdm_slot,
};
static struct snd_soc_dai_driver rt1019_dai[] = {
{
.name = "rt1019-aif",
.id = 0,
.playback = {
.stream_name = "AIF Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT1019_STEREO_RATES,
.formats = RT1019_FORMATS,
},
.ops = &rt1019_aif_dai_ops,
}
};
static const struct snd_soc_component_driver soc_component_dev_rt1019 = {
.probe = rt1019_probe,
.controls = rt1019_snd_controls,
.num_controls = ARRAY_SIZE(rt1019_snd_controls),
.dapm_widgets = rt1019_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt1019_dapm_widgets),
.dapm_routes = rt1019_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(rt1019_dapm_routes),
.endianness = 1,
};
static const struct regmap_config rt1019_regmap = {
.reg_bits = 16,
.val_bits = 8,
.use_single_read = true,
.use_single_write = true,
.max_register = RT1019_BEEP_2,
.volatile_reg = rt1019_volatile_register,
.readable_reg = rt1019_readable_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = rt1019_reg,
.num_reg_defaults = ARRAY_SIZE(rt1019_reg),
};
static const struct i2c_device_id rt1019_i2c_id[] = {
{ "rt1019", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, rt1019_i2c_id);
static const struct of_device_id rt1019_of_match[] __maybe_unused = {
{ .compatible = "realtek,rt1019", },
{},
};
MODULE_DEVICE_TABLE(of, rt1019_of_match);
#ifdef CONFIG_ACPI
static const struct acpi_device_id rt1019_acpi_match[] = {
{ "10EC1019", 0},
{ },
};
MODULE_DEVICE_TABLE(acpi, rt1019_acpi_match);
#endif
static int rt1019_i2c_probe(struct i2c_client *i2c)
{
struct rt1019_priv *rt1019;
int ret;
unsigned int val, val2, dev_id;
rt1019 = devm_kzalloc(&i2c->dev, sizeof(struct rt1019_priv),
GFP_KERNEL);
if (!rt1019)
return -ENOMEM;
i2c_set_clientdata(i2c, rt1019);
rt1019->regmap = devm_regmap_init_i2c(i2c, &rt1019_regmap);
if (IS_ERR(rt1019->regmap)) {
ret = PTR_ERR(rt1019->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
regmap_read(rt1019->regmap, RT1019_DEV_ID_1, &val);
regmap_read(rt1019->regmap, RT1019_DEV_ID_2, &val2);
dev_id = val << 8 | val2;
if (dev_id != RT1019_DEVICE_ID_VAL && dev_id != RT1019_DEVICE_ID_VAL2) {
dev_err(&i2c->dev,
"Device with ID register 0x%x is not rt1019\n", dev_id);
return -ENODEV;
}
return devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_rt1019, rt1019_dai, ARRAY_SIZE(rt1019_dai));
}
static struct i2c_driver rt1019_i2c_driver = {
.driver = {
.name = "rt1019",
.of_match_table = of_match_ptr(rt1019_of_match),
.acpi_match_table = ACPI_PTR(rt1019_acpi_match),
},
.probe = rt1019_i2c_probe,
.id_table = rt1019_i2c_id,
};
module_i2c_driver(rt1019_i2c_driver);
MODULE_DESCRIPTION("ASoC RT1019 driver");
MODULE_AUTHOR("Jack Yu <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/rt1019.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* rt5660.c -- RT5660 ALSA SoC audio codec driver
*
* Copyright 2016 Realtek Semiconductor Corp.
* Author: Oder Chiou <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/acpi.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "rl6231.h"
#include "rt5660.h"
#define RT5660_DEVICE_ID 0x6338
#define RT5660_PR_RANGE_BASE (0xff + 1)
#define RT5660_PR_SPACING 0x100
#define RT5660_PR_BASE (RT5660_PR_RANGE_BASE + (0 * RT5660_PR_SPACING))
static const struct regmap_range_cfg rt5660_ranges[] = {
{ .name = "PR", .range_min = RT5660_PR_BASE,
.range_max = RT5660_PR_BASE + 0xf3,
.selector_reg = RT5660_PRIV_INDEX,
.selector_mask = 0xff,
.selector_shift = 0x0,
.window_start = RT5660_PRIV_DATA,
.window_len = 0x1, },
};
static const struct reg_sequence rt5660_patch[] = {
{ RT5660_ALC_PGA_CTRL2, 0x44c3 },
{ RT5660_PR_BASE + 0x3d, 0x2600 },
};
static const struct reg_default rt5660_reg[] = {
{ 0x00, 0x0000 },
{ 0x01, 0xc800 },
{ 0x02, 0xc8c8 },
{ 0x0d, 0x1010 },
{ 0x0e, 0x1010 },
{ 0x19, 0xafaf },
{ 0x1c, 0x2f2f },
{ 0x1e, 0x0000 },
{ 0x27, 0x6060 },
{ 0x29, 0x8080 },
{ 0x2a, 0x4242 },
{ 0x2f, 0x0000 },
{ 0x3b, 0x0000 },
{ 0x3c, 0x007f },
{ 0x3d, 0x0000 },
{ 0x3e, 0x007f },
{ 0x45, 0xe000 },
{ 0x46, 0x003e },
{ 0x48, 0xf800 },
{ 0x4a, 0x0004 },
{ 0x4d, 0x0000 },
{ 0x4e, 0x0000 },
{ 0x4f, 0x01ff },
{ 0x50, 0x0000 },
{ 0x51, 0x0000 },
{ 0x52, 0x01ff },
{ 0x61, 0x0000 },
{ 0x62, 0x0000 },
{ 0x63, 0x00c0 },
{ 0x64, 0x0000 },
{ 0x65, 0x0000 },
{ 0x66, 0x0000 },
{ 0x70, 0x8000 },
{ 0x73, 0x7000 },
{ 0x74, 0x3c00 },
{ 0x75, 0x2800 },
{ 0x80, 0x0000 },
{ 0x81, 0x0000 },
{ 0x82, 0x0000 },
{ 0x8c, 0x0228 },
{ 0x8d, 0xa000 },
{ 0x8e, 0x0000 },
{ 0x92, 0x0000 },
{ 0x93, 0x3000 },
{ 0xa1, 0x0059 },
{ 0xa2, 0x0001 },
{ 0xa3, 0x5c80 },
{ 0xa4, 0x0146 },
{ 0xa5, 0x1f1f },
{ 0xa6, 0x78c6 },
{ 0xa7, 0xe5ec },
{ 0xa8, 0xba61 },
{ 0xa9, 0x3c78 },
{ 0xaa, 0x8ae2 },
{ 0xab, 0xe5ec },
{ 0xac, 0xc600 },
{ 0xad, 0xba61 },
{ 0xae, 0x17ed },
{ 0xb0, 0x2080 },
{ 0xb1, 0x0000 },
{ 0xb3, 0x001f },
{ 0xb4, 0x020c },
{ 0xb5, 0x1f00 },
{ 0xb6, 0x0000 },
{ 0xb7, 0x4000 },
{ 0xbb, 0x0000 },
{ 0xbd, 0x0000 },
{ 0xbe, 0x0000 },
{ 0xbf, 0x0100 },
{ 0xc0, 0x0000 },
{ 0xc2, 0x0000 },
{ 0xd3, 0xa220 },
{ 0xd9, 0x0809 },
{ 0xda, 0x0000 },
{ 0xe0, 0x8000 },
{ 0xe1, 0x0200 },
{ 0xe2, 0x8000 },
{ 0xe3, 0x0200 },
{ 0xe4, 0x0f20 },
{ 0xe5, 0x001f },
{ 0xe6, 0x020c },
{ 0xe7, 0x1f00 },
{ 0xe8, 0x0000 },
{ 0xe9, 0x4000 },
{ 0xea, 0x00a6 },
{ 0xeb, 0x04c3 },
{ 0xec, 0x27c8 },
{ 0xed, 0x7418 },
{ 0xee, 0xbf50 },
{ 0xef, 0x0045 },
{ 0xf0, 0x0007 },
{ 0xfa, 0x0000 },
{ 0xfd, 0x0000 },
{ 0xfe, 0x10ec },
{ 0xff, 0x6338 },
};
static bool rt5660_volatile_register(struct device *dev, unsigned int reg)
{
int i;
for (i = 0; i < ARRAY_SIZE(rt5660_ranges); i++)
if ((reg >= rt5660_ranges[i].window_start &&
reg <= rt5660_ranges[i].window_start +
rt5660_ranges[i].window_len) ||
(reg >= rt5660_ranges[i].range_min &&
reg <= rt5660_ranges[i].range_max))
return true;
switch (reg) {
case RT5660_RESET:
case RT5660_PRIV_DATA:
case RT5660_EQ_CTRL1:
case RT5660_IRQ_CTRL2:
case RT5660_INT_IRQ_ST:
case RT5660_VENDOR_ID:
case RT5660_VENDOR_ID1:
case RT5660_VENDOR_ID2:
return true;
default:
return false;
}
}
static bool rt5660_readable_register(struct device *dev, unsigned int reg)
{
int i;
for (i = 0; i < ARRAY_SIZE(rt5660_ranges); i++)
if ((reg >= rt5660_ranges[i].window_start &&
reg <= rt5660_ranges[i].window_start +
rt5660_ranges[i].window_len) ||
(reg >= rt5660_ranges[i].range_min &&
reg <= rt5660_ranges[i].range_max))
return true;
switch (reg) {
case RT5660_RESET:
case RT5660_SPK_VOL:
case RT5660_LOUT_VOL:
case RT5660_IN1_IN2:
case RT5660_IN3_IN4:
case RT5660_DAC1_DIG_VOL:
case RT5660_STO1_ADC_DIG_VOL:
case RT5660_ADC_BST_VOL1:
case RT5660_STO1_ADC_MIXER:
case RT5660_AD_DA_MIXER:
case RT5660_STO_DAC_MIXER:
case RT5660_DIG_INF1_DATA:
case RT5660_REC_L1_MIXER:
case RT5660_REC_L2_MIXER:
case RT5660_REC_R1_MIXER:
case RT5660_REC_R2_MIXER:
case RT5660_LOUT_MIXER:
case RT5660_SPK_MIXER:
case RT5660_SPO_MIXER:
case RT5660_SPO_CLSD_RATIO:
case RT5660_OUT_L_GAIN1:
case RT5660_OUT_L_GAIN2:
case RT5660_OUT_L1_MIXER:
case RT5660_OUT_R_GAIN1:
case RT5660_OUT_R_GAIN2:
case RT5660_OUT_R1_MIXER:
case RT5660_PWR_DIG1:
case RT5660_PWR_DIG2:
case RT5660_PWR_ANLG1:
case RT5660_PWR_ANLG2:
case RT5660_PWR_MIXER:
case RT5660_PWR_VOL:
case RT5660_PRIV_INDEX:
case RT5660_PRIV_DATA:
case RT5660_I2S1_SDP:
case RT5660_ADDA_CLK1:
case RT5660_ADDA_CLK2:
case RT5660_DMIC_CTRL1:
case RT5660_GLB_CLK:
case RT5660_PLL_CTRL1:
case RT5660_PLL_CTRL2:
case RT5660_CLSD_AMP_OC_CTRL:
case RT5660_CLSD_AMP_CTRL:
case RT5660_LOUT_AMP_CTRL:
case RT5660_SPK_AMP_SPKVDD:
case RT5660_MICBIAS:
case RT5660_CLSD_OUT_CTRL1:
case RT5660_CLSD_OUT_CTRL2:
case RT5660_DIPOLE_MIC_CTRL1:
case RT5660_DIPOLE_MIC_CTRL2:
case RT5660_DIPOLE_MIC_CTRL3:
case RT5660_DIPOLE_MIC_CTRL4:
case RT5660_DIPOLE_MIC_CTRL5:
case RT5660_DIPOLE_MIC_CTRL6:
case RT5660_DIPOLE_MIC_CTRL7:
case RT5660_DIPOLE_MIC_CTRL8:
case RT5660_DIPOLE_MIC_CTRL9:
case RT5660_DIPOLE_MIC_CTRL10:
case RT5660_DIPOLE_MIC_CTRL11:
case RT5660_DIPOLE_MIC_CTRL12:
case RT5660_EQ_CTRL1:
case RT5660_EQ_CTRL2:
case RT5660_DRC_AGC_CTRL1:
case RT5660_DRC_AGC_CTRL2:
case RT5660_DRC_AGC_CTRL3:
case RT5660_DRC_AGC_CTRL4:
case RT5660_DRC_AGC_CTRL5:
case RT5660_JD_CTRL:
case RT5660_IRQ_CTRL1:
case RT5660_IRQ_CTRL2:
case RT5660_INT_IRQ_ST:
case RT5660_GPIO_CTRL1:
case RT5660_GPIO_CTRL2:
case RT5660_WIND_FILTER_CTRL1:
case RT5660_SV_ZCD1:
case RT5660_SV_ZCD2:
case RT5660_DRC1_LM_CTRL1:
case RT5660_DRC1_LM_CTRL2:
case RT5660_DRC2_LM_CTRL1:
case RT5660_DRC2_LM_CTRL2:
case RT5660_MULTI_DRC_CTRL:
case RT5660_DRC2_CTRL1:
case RT5660_DRC2_CTRL2:
case RT5660_DRC2_CTRL3:
case RT5660_DRC2_CTRL4:
case RT5660_DRC2_CTRL5:
case RT5660_ALC_PGA_CTRL1:
case RT5660_ALC_PGA_CTRL2:
case RT5660_ALC_PGA_CTRL3:
case RT5660_ALC_PGA_CTRL4:
case RT5660_ALC_PGA_CTRL5:
case RT5660_ALC_PGA_CTRL6:
case RT5660_ALC_PGA_CTRL7:
case RT5660_GEN_CTRL1:
case RT5660_GEN_CTRL2:
case RT5660_GEN_CTRL3:
case RT5660_VENDOR_ID:
case RT5660_VENDOR_ID1:
case RT5660_VENDOR_ID2:
return true;
default:
return false;
}
}
static const DECLARE_TLV_DB_SCALE(rt5660_out_vol_tlv, -4650, 150, 0);
static const DECLARE_TLV_DB_SCALE(rt5660_dac_vol_tlv, -6525, 75, 0);
static const DECLARE_TLV_DB_SCALE(rt5660_adc_vol_tlv, -1725, 75, 0);
static const DECLARE_TLV_DB_SCALE(rt5660_adc_bst_tlv, 0, 1200, 0);
static const DECLARE_TLV_DB_SCALE(rt5660_bst_tlv, -1200, 75, 0);
static const struct snd_kcontrol_new rt5660_snd_controls[] = {
/* Speaker Output Volume */
SOC_SINGLE("Speaker Playback Switch", RT5660_SPK_VOL, RT5660_L_MUTE_SFT,
1, 1),
SOC_SINGLE_TLV("Speaker Playback Volume", RT5660_SPK_VOL,
RT5660_L_VOL_SFT, 39, 1, rt5660_out_vol_tlv),
/* OUTPUT Control */
SOC_DOUBLE("OUT Playback Switch", RT5660_LOUT_VOL, RT5660_L_MUTE_SFT,
RT5660_R_MUTE_SFT, 1, 1),
SOC_DOUBLE_TLV("OUT Playback Volume", RT5660_LOUT_VOL, RT5660_L_VOL_SFT,
RT5660_R_VOL_SFT, 39, 1, rt5660_out_vol_tlv),
/* DAC Digital Volume */
SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5660_DAC1_DIG_VOL,
RT5660_DAC_L1_VOL_SFT, RT5660_DAC_R1_VOL_SFT, 87, 0,
rt5660_dac_vol_tlv),
/* IN1/IN2/IN3 Control */
SOC_SINGLE_TLV("IN1 Boost Volume", RT5660_IN1_IN2, RT5660_BST_SFT1, 69,
0, rt5660_bst_tlv),
SOC_SINGLE_TLV("IN2 Boost Volume", RT5660_IN1_IN2, RT5660_BST_SFT2, 69,
0, rt5660_bst_tlv),
SOC_SINGLE_TLV("IN3 Boost Volume", RT5660_IN3_IN4, RT5660_BST_SFT3, 69,
0, rt5660_bst_tlv),
/* ADC Digital Volume Control */
SOC_DOUBLE("ADC Capture Switch", RT5660_STO1_ADC_DIG_VOL,
RT5660_L_MUTE_SFT, RT5660_R_MUTE_SFT, 1, 1),
SOC_DOUBLE_TLV("ADC Capture Volume", RT5660_STO1_ADC_DIG_VOL,
RT5660_ADC_L_VOL_SFT, RT5660_ADC_R_VOL_SFT, 63, 0,
rt5660_adc_vol_tlv),
/* ADC Boost Volume Control */
SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5660_ADC_BST_VOL1,
RT5660_STO1_ADC_L_BST_SFT, RT5660_STO1_ADC_R_BST_SFT, 3, 0,
rt5660_adc_bst_tlv),
};
/**
* rt5660_set_dmic_clk - Set parameter of dmic.
*
* @w: DAPM widget.
* @kcontrol: The kcontrol of this widget.
* @event: Event id.
*
*/
static int rt5660_set_dmic_clk(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5660_priv *rt5660 = snd_soc_component_get_drvdata(component);
int idx, rate;
rate = rt5660->sysclk / rl6231_get_pre_div(rt5660->regmap,
RT5660_ADDA_CLK1, RT5660_I2S_PD1_SFT);
idx = rl6231_calc_dmic_clk(rate);
if (idx < 0)
dev_err(component->dev, "Failed to set DMIC clock\n");
else
snd_soc_component_update_bits(component, RT5660_DMIC_CTRL1,
RT5660_DMIC_CLK_MASK, idx << RT5660_DMIC_CLK_SFT);
return idx;
}
static int rt5660_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
unsigned int val;
val = snd_soc_component_read(component, RT5660_GLB_CLK);
val &= RT5660_SCLK_SRC_MASK;
if (val == RT5660_SCLK_SRC_PLL1)
return 1;
else
return 0;
}
/* Digital Mixer */
static const struct snd_kcontrol_new rt5660_sto1_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5660_STO1_ADC_MIXER,
RT5660_M_ADC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5660_STO1_ADC_MIXER,
RT5660_M_ADC_L2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5660_sto1_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5660_STO1_ADC_MIXER,
RT5660_M_ADC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5660_STO1_ADC_MIXER,
RT5660_M_ADC_R2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5660_dac_l_mix[] = {
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5660_AD_DA_MIXER,
RT5660_M_ADCMIX_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC1 Switch", RT5660_AD_DA_MIXER,
RT5660_M_DAC1_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5660_dac_r_mix[] = {
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5660_AD_DA_MIXER,
RT5660_M_ADCMIX_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC1 Switch", RT5660_AD_DA_MIXER,
RT5660_M_DAC1_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5660_sto_dac_l_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5660_STO_DAC_MIXER,
RT5660_M_DAC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5660_STO_DAC_MIXER,
RT5660_M_DAC_R1_STO_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5660_sto_dac_r_mix[] = {
SOC_DAPM_SINGLE("DAC R1 Switch", RT5660_STO_DAC_MIXER,
RT5660_M_DAC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L1 Switch", RT5660_STO_DAC_MIXER,
RT5660_M_DAC_L1_STO_R_SFT, 1, 1),
};
/* Analog Input Mixer */
static const struct snd_kcontrol_new rt5660_rec_l_mix[] = {
SOC_DAPM_SINGLE("BST3 Switch", RT5660_REC_L2_MIXER,
RT5660_M_BST3_RM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5660_REC_L2_MIXER,
RT5660_M_BST2_RM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5660_REC_L2_MIXER,
RT5660_M_BST1_RM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("OUT MIXL Switch", RT5660_REC_L2_MIXER,
RT5660_M_OM_L_RM_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5660_rec_r_mix[] = {
SOC_DAPM_SINGLE("BST3 Switch", RT5660_REC_R2_MIXER,
RT5660_M_BST3_RM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5660_REC_R2_MIXER,
RT5660_M_BST2_RM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5660_REC_R2_MIXER,
RT5660_M_BST1_RM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("OUT MIXR Switch", RT5660_REC_R2_MIXER,
RT5660_M_OM_R_RM_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5660_spk_mix[] = {
SOC_DAPM_SINGLE("BST3 Switch", RT5660_SPK_MIXER,
RT5660_M_BST3_SM_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5660_SPK_MIXER,
RT5660_M_BST1_SM_SFT, 1, 1),
SOC_DAPM_SINGLE("DACL Switch", RT5660_SPK_MIXER,
RT5660_M_DACL_SM_SFT, 1, 1),
SOC_DAPM_SINGLE("DACR Switch", RT5660_SPK_MIXER,
RT5660_M_DACR_SM_SFT, 1, 1),
SOC_DAPM_SINGLE("OUTMIXL Switch", RT5660_SPK_MIXER,
RT5660_M_OM_L_SM_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5660_out_l_mix[] = {
SOC_DAPM_SINGLE("BST3 Switch", RT5660_OUT_L1_MIXER,
RT5660_M_BST3_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5660_OUT_L1_MIXER,
RT5660_M_BST2_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5660_OUT_L1_MIXER,
RT5660_M_BST1_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("RECMIXL Switch", RT5660_OUT_L1_MIXER,
RT5660_M_RM_L_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DACR Switch", RT5660_OUT_L1_MIXER,
RT5660_M_DAC_R_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DACL Switch", RT5660_OUT_L1_MIXER,
RT5660_M_DAC_L_OM_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5660_out_r_mix[] = {
SOC_DAPM_SINGLE("BST2 Switch", RT5660_OUT_R1_MIXER,
RT5660_M_BST2_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5660_OUT_R1_MIXER,
RT5660_M_BST1_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("RECMIXR Switch", RT5660_OUT_R1_MIXER,
RT5660_M_RM_R_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DACR Switch", RT5660_OUT_R1_MIXER,
RT5660_M_DAC_R_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DACL Switch", RT5660_OUT_R1_MIXER,
RT5660_M_DAC_L_OM_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5660_spo_mix[] = {
SOC_DAPM_SINGLE("DACR Switch", RT5660_SPO_MIXER,
RT5660_M_DAC_R_SPM_SFT, 1, 1),
SOC_DAPM_SINGLE("DACL Switch", RT5660_SPO_MIXER,
RT5660_M_DAC_L_SPM_SFT, 1, 1),
SOC_DAPM_SINGLE("SPKVOL Switch", RT5660_SPO_MIXER,
RT5660_M_SV_SPM_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5660_SPO_MIXER,
RT5660_M_BST1_SPM_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5660_lout_mix[] = {
SOC_DAPM_SINGLE("DAC Switch", RT5660_LOUT_MIXER,
RT5660_M_DAC1_LM_SFT, 1, 1),
SOC_DAPM_SINGLE("OUTMIX Switch", RT5660_LOUT_MIXER,
RT5660_M_LOVOL_LM_SFT, 1, 1),
};
static const struct snd_kcontrol_new spk_vol_control =
SOC_DAPM_SINGLE("Switch", RT5660_SPK_VOL,
RT5660_VOL_L_SFT, 1, 1);
static const struct snd_kcontrol_new lout_l_vol_control =
SOC_DAPM_SINGLE("Switch", RT5660_LOUT_VOL,
RT5660_VOL_L_SFT, 1, 1);
static const struct snd_kcontrol_new lout_r_vol_control =
SOC_DAPM_SINGLE("Switch", RT5660_LOUT_VOL,
RT5660_VOL_R_SFT, 1, 1);
/* Interface data select */
static const char * const rt5660_data_select[] = {
"L/R", "R/L", "L/L", "R/R"
};
static SOC_ENUM_SINGLE_DECL(rt5660_if1_dac_enum,
RT5660_DIG_INF1_DATA, RT5660_IF1_DAC_IN_SFT, rt5660_data_select);
static SOC_ENUM_SINGLE_DECL(rt5660_if1_adc_enum,
RT5660_DIG_INF1_DATA, RT5660_IF1_ADC_IN_SFT, rt5660_data_select);
static const struct snd_kcontrol_new rt5660_if1_dac_swap_mux =
SOC_DAPM_ENUM("IF1 DAC Swap Source", rt5660_if1_dac_enum);
static const struct snd_kcontrol_new rt5660_if1_adc_swap_mux =
SOC_DAPM_ENUM("IF1 ADC Swap Source", rt5660_if1_adc_enum);
static int rt5660_lout_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(component, RT5660_LOUT_AMP_CTRL,
RT5660_LOUT_CO_MASK | RT5660_LOUT_CB_MASK,
RT5660_LOUT_CO_EN | RT5660_LOUT_CB_PU);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, RT5660_LOUT_AMP_CTRL,
RT5660_LOUT_CO_MASK | RT5660_LOUT_CB_MASK,
RT5660_LOUT_CO_DIS | RT5660_LOUT_CB_PD);
break;
default:
return 0;
}
return 0;
}
static const struct snd_soc_dapm_widget rt5660_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("LDO2", RT5660_PWR_ANLG1,
RT5660_PWR_LDO2_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PLL1", RT5660_PWR_ANLG2,
RT5660_PWR_PLL_BIT, 0, NULL, 0),
/* MICBIAS */
SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5660_PWR_ANLG2,
RT5660_PWR_MB1_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5660_PWR_ANLG2,
RT5660_PWR_MB2_BIT, 0, NULL, 0),
/* Input Side */
/* Input Lines */
SND_SOC_DAPM_INPUT("DMIC L1"),
SND_SOC_DAPM_INPUT("DMIC R1"),
SND_SOC_DAPM_INPUT("IN1P"),
SND_SOC_DAPM_INPUT("IN1N"),
SND_SOC_DAPM_INPUT("IN2P"),
SND_SOC_DAPM_INPUT("IN3P"),
SND_SOC_DAPM_INPUT("IN3N"),
SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
rt5660_set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_SUPPLY("DMIC Power", RT5660_DMIC_CTRL1,
RT5660_DMIC_1_EN_SFT, 0, NULL, 0),
/* Boost */
SND_SOC_DAPM_PGA("BST1", RT5660_PWR_ANLG2, RT5660_PWR_BST1_BIT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("BST2", RT5660_PWR_ANLG2, RT5660_PWR_BST2_BIT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("BST3", RT5660_PWR_ANLG2, RT5660_PWR_BST3_BIT, 0,
NULL, 0),
/* REC Mixer */
SND_SOC_DAPM_MIXER("RECMIXL", RT5660_PWR_MIXER, RT5660_PWR_RM_L_BIT,
0, rt5660_rec_l_mix, ARRAY_SIZE(rt5660_rec_l_mix)),
SND_SOC_DAPM_MIXER("RECMIXR", RT5660_PWR_MIXER, RT5660_PWR_RM_R_BIT,
0, rt5660_rec_r_mix, ARRAY_SIZE(rt5660_rec_r_mix)),
/* ADCs */
SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SUPPLY("ADC L power", RT5660_PWR_DIG1,
RT5660_PWR_ADC_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC R power", RT5660_PWR_DIG1,
RT5660_PWR_ADC_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC clock", RT5660_PR_BASE + RT5660_CHOP_DAC_ADC,
12, 0, NULL, 0),
/* ADC Mixer */
SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5660_PWR_DIG2,
RT5660_PWR_ADC_S1F_BIT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
rt5660_sto1_adc_l_mix, ARRAY_SIZE(rt5660_sto1_adc_l_mix)),
SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
rt5660_sto1_adc_r_mix, ARRAY_SIZE(rt5660_sto1_adc_r_mix)),
/* ADC */
SND_SOC_DAPM_ADC("Stereo1 ADC MIXL", NULL, RT5660_STO1_ADC_DIG_VOL,
RT5660_L_MUTE_SFT, 1),
SND_SOC_DAPM_ADC("Stereo1 ADC MIXR", NULL, RT5660_STO1_ADC_DIG_VOL,
RT5660_R_MUTE_SFT, 1),
/* Digital Interface */
SND_SOC_DAPM_SUPPLY("I2S1", RT5660_PWR_DIG1, RT5660_PWR_I2S1_BIT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX("IF1 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5660_if1_dac_swap_mux),
SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX("IF1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5660_if1_adc_swap_mux),
/* Audio Interface */
SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
/* Output Side */
/* DAC mixer before sound effect */
SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, rt5660_dac_l_mix,
ARRAY_SIZE(rt5660_dac_l_mix)),
SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, rt5660_dac_r_mix,
ARRAY_SIZE(rt5660_dac_r_mix)),
/* DAC Mixer */
SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5660_PWR_DIG2,
RT5660_PWR_DAC_S1F_BIT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
rt5660_sto_dac_l_mix, ARRAY_SIZE(rt5660_sto_dac_l_mix)),
SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
rt5660_sto_dac_r_mix, ARRAY_SIZE(rt5660_sto_dac_r_mix)),
/* DACs */
SND_SOC_DAPM_DAC("DAC L1", NULL, RT5660_PWR_DIG1,
RT5660_PWR_DAC_L1_BIT, 0),
SND_SOC_DAPM_DAC("DAC R1", NULL, RT5660_PWR_DIG1,
RT5660_PWR_DAC_R1_BIT, 0),
/* OUT Mixer */
SND_SOC_DAPM_MIXER("SPK MIX", RT5660_PWR_MIXER, RT5660_PWR_SM_BIT,
0, rt5660_spk_mix, ARRAY_SIZE(rt5660_spk_mix)),
SND_SOC_DAPM_MIXER("OUT MIXL", RT5660_PWR_MIXER, RT5660_PWR_OM_L_BIT,
0, rt5660_out_l_mix, ARRAY_SIZE(rt5660_out_l_mix)),
SND_SOC_DAPM_MIXER("OUT MIXR", RT5660_PWR_MIXER, RT5660_PWR_OM_R_BIT,
0, rt5660_out_r_mix, ARRAY_SIZE(rt5660_out_r_mix)),
/* Output Volume */
SND_SOC_DAPM_SWITCH("SPKVOL", RT5660_PWR_VOL,
RT5660_PWR_SV_BIT, 0, &spk_vol_control),
SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM,
0, 0, NULL, 0),
SND_SOC_DAPM_PGA("LOUTVOL", SND_SOC_NOPM,
0, 0, NULL, 0),
SND_SOC_DAPM_SWITCH("LOUTVOL L", SND_SOC_NOPM,
RT5660_PWR_LV_L_BIT, 0, &lout_l_vol_control),
SND_SOC_DAPM_SWITCH("LOUTVOL R", SND_SOC_NOPM,
RT5660_PWR_LV_R_BIT, 0, &lout_r_vol_control),
/* HPO/LOUT/Mono Mixer */
SND_SOC_DAPM_MIXER("SPO MIX", SND_SOC_NOPM, 0,
0, rt5660_spo_mix, ARRAY_SIZE(rt5660_spo_mix)),
SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0,
rt5660_lout_mix, ARRAY_SIZE(rt5660_lout_mix)),
SND_SOC_DAPM_SUPPLY("VREF HP", RT5660_GEN_CTRL1,
RT5660_PWR_VREF_HP_SFT, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("LOUT amp", 1, RT5660_PWR_ANLG1,
RT5660_PWR_HA_BIT, 0, rt5660_lout_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_S("SPK amp", 1, RT5660_PWR_DIG1,
RT5660_PWR_CLS_D_BIT, 0, NULL, 0),
/* Output Lines */
SND_SOC_DAPM_OUTPUT("LOUTL"),
SND_SOC_DAPM_OUTPUT("LOUTR"),
SND_SOC_DAPM_OUTPUT("SPO"),
};
static const struct snd_soc_dapm_route rt5660_dapm_routes[] = {
{ "MICBIAS1", NULL, "LDO2" },
{ "MICBIAS2", NULL, "LDO2" },
{ "BST1", NULL, "IN1P" },
{ "BST1", NULL, "IN1N" },
{ "BST2", NULL, "IN2P" },
{ "BST3", NULL, "IN3P" },
{ "BST3", NULL, "IN3N" },
{ "RECMIXL", "BST3 Switch", "BST3" },
{ "RECMIXL", "BST2 Switch", "BST2" },
{ "RECMIXL", "BST1 Switch", "BST1" },
{ "RECMIXL", "OUT MIXL Switch", "OUT MIXL" },
{ "RECMIXR", "BST3 Switch", "BST3" },
{ "RECMIXR", "BST2 Switch", "BST2" },
{ "RECMIXR", "BST1 Switch", "BST1" },
{ "RECMIXR", "OUT MIXR Switch", "OUT MIXR" },
{ "ADC L", NULL, "RECMIXL" },
{ "ADC L", NULL, "ADC L power" },
{ "ADC L", NULL, "ADC clock" },
{ "ADC R", NULL, "RECMIXR" },
{ "ADC R", NULL, "ADC R power" },
{ "ADC R", NULL, "ADC clock" },
{"DMIC L1", NULL, "DMIC CLK"},
{"DMIC L1", NULL, "DMIC Power"},
{"DMIC R1", NULL, "DMIC CLK"},
{"DMIC R1", NULL, "DMIC Power"},
{ "Sto1 ADC MIXL", "ADC1 Switch", "ADC L" },
{ "Sto1 ADC MIXL", "ADC2 Switch", "DMIC L1" },
{ "Sto1 ADC MIXR", "ADC1 Switch", "ADC R" },
{ "Sto1 ADC MIXR", "ADC2 Switch", "DMIC R1" },
{ "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
{ "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
{ "adc stereo1 filter", NULL, "PLL1", rt5660_is_sys_clk_from_pll },
{ "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
{ "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
{ "adc stereo1 filter", NULL, "PLL1", rt5660_is_sys_clk_from_pll },
{ "IF1 ADC", NULL, "Stereo1 ADC MIXL" },
{ "IF1 ADC", NULL, "Stereo1 ADC MIXR" },
{ "IF1 ADC", NULL, "I2S1" },
{ "IF1 ADC Swap Mux", "L/R", "IF1 ADC" },
{ "IF1 ADC Swap Mux", "R/L", "IF1 ADC" },
{ "IF1 ADC Swap Mux", "L/L", "IF1 ADC" },
{ "IF1 ADC Swap Mux", "R/R", "IF1 ADC" },
{ "AIF1TX", NULL, "IF1 ADC Swap Mux" },
{ "IF1 DAC", NULL, "AIF1RX" },
{ "IF1 DAC", NULL, "I2S1" },
{ "IF1 DAC Swap Mux", "L/R", "IF1 DAC" },
{ "IF1 DAC Swap Mux", "R/L", "IF1 DAC" },
{ "IF1 DAC Swap Mux", "L/L", "IF1 DAC" },
{ "IF1 DAC Swap Mux", "R/R", "IF1 DAC" },
{ "IF1 DAC L", NULL, "IF1 DAC Swap Mux" },
{ "IF1 DAC R", NULL, "IF1 DAC Swap Mux" },
{ "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },
{ "DAC1 MIXL", "DAC1 Switch", "IF1 DAC L" },
{ "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" },
{ "DAC1 MIXR", "DAC1 Switch", "IF1 DAC R" },
{ "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
{ "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
{ "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
{ "dac stereo1 filter", NULL, "PLL1", rt5660_is_sys_clk_from_pll },
{ "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
{ "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
{ "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
{ "dac stereo1 filter", NULL, "PLL1", rt5660_is_sys_clk_from_pll },
{ "DAC L1", NULL, "Stereo DAC MIXL" },
{ "DAC R1", NULL, "Stereo DAC MIXR" },
{ "SPK MIX", "BST3 Switch", "BST3" },
{ "SPK MIX", "BST1 Switch", "BST1" },
{ "SPK MIX", "DACL Switch", "DAC L1" },
{ "SPK MIX", "DACR Switch", "DAC R1" },
{ "SPK MIX", "OUTMIXL Switch", "OUT MIXL" },
{ "OUT MIXL", "BST3 Switch", "BST3" },
{ "OUT MIXL", "BST2 Switch", "BST2" },
{ "OUT MIXL", "BST1 Switch", "BST1" },
{ "OUT MIXL", "RECMIXL Switch", "RECMIXL" },
{ "OUT MIXL", "DACR Switch", "DAC R1" },
{ "OUT MIXL", "DACL Switch", "DAC L1" },
{ "OUT MIXR", "BST2 Switch", "BST2" },
{ "OUT MIXR", "BST1 Switch", "BST1" },
{ "OUT MIXR", "RECMIXR Switch", "RECMIXR" },
{ "OUT MIXR", "DACR Switch", "DAC R1" },
{ "OUT MIXR", "DACL Switch", "DAC L1" },
{ "SPO MIX", "DACR Switch", "DAC R1" },
{ "SPO MIX", "DACL Switch", "DAC L1" },
{ "SPO MIX", "SPKVOL Switch", "SPKVOL" },
{ "SPO MIX", "BST1 Switch", "BST1" },
{ "SPKVOL", "Switch", "SPK MIX" },
{ "LOUTVOL L", "Switch", "OUT MIXL" },
{ "LOUTVOL R", "Switch", "OUT MIXR" },
{ "LOUTVOL", NULL, "LOUTVOL L" },
{ "LOUTVOL", NULL, "LOUTVOL R" },
{ "DAC 1", NULL, "DAC L1" },
{ "DAC 1", NULL, "DAC R1" },
{ "LOUT MIX", "DAC Switch", "DAC 1" },
{ "LOUT MIX", "OUTMIX Switch", "LOUTVOL" },
{ "LOUT amp", NULL, "LOUT MIX" },
{ "LOUT amp", NULL, "VREF HP" },
{ "LOUTL", NULL, "LOUT amp" },
{ "LOUTR", NULL, "LOUT amp" },
{ "SPK amp", NULL, "SPO MIX" },
{ "SPO", NULL, "SPK amp" },
};
static int rt5660_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt5660_priv *rt5660 = snd_soc_component_get_drvdata(component);
unsigned int val_len = 0, val_clk, mask_clk;
int pre_div, bclk_ms, frame_size;
rt5660->lrck[dai->id] = params_rate(params);
pre_div = rl6231_get_clk_info(rt5660->sysclk, rt5660->lrck[dai->id]);
if (pre_div < 0) {
dev_err(component->dev, "Unsupported clock setting %d for DAI %d\n",
rt5660->lrck[dai->id], dai->id);
return -EINVAL;
}
frame_size = snd_soc_params_to_frame_size(params);
if (frame_size < 0) {
dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
return frame_size;
}
if (frame_size > 32)
bclk_ms = 1;
else
bclk_ms = 0;
rt5660->bclk[dai->id] = rt5660->lrck[dai->id] * (32 << bclk_ms);
dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
rt5660->bclk[dai->id], rt5660->lrck[dai->id]);
dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
bclk_ms, pre_div, dai->id);
switch (params_width(params)) {
case 16:
break;
case 20:
val_len |= RT5660_I2S_DL_20;
break;
case 24:
val_len |= RT5660_I2S_DL_24;
break;
case 8:
val_len |= RT5660_I2S_DL_8;
break;
default:
return -EINVAL;
}
switch (dai->id) {
case RT5660_AIF1:
mask_clk = RT5660_I2S_BCLK_MS1_MASK | RT5660_I2S_PD1_MASK;
val_clk = bclk_ms << RT5660_I2S_BCLK_MS1_SFT |
pre_div << RT5660_I2S_PD1_SFT;
snd_soc_component_update_bits(component, RT5660_I2S1_SDP, RT5660_I2S_DL_MASK,
val_len);
snd_soc_component_update_bits(component, RT5660_ADDA_CLK1, mask_clk, val_clk);
break;
default:
dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
return -EINVAL;
}
return 0;
}
static int rt5660_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct rt5660_priv *rt5660 = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
rt5660->master[dai->id] = 1;
break;
case SND_SOC_DAIFMT_CBS_CFS:
reg_val |= RT5660_I2S_MS_S;
rt5660->master[dai->id] = 0;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
reg_val |= RT5660_I2S_BP_INV;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_LEFT_J:
reg_val |= RT5660_I2S_DF_LEFT;
break;
case SND_SOC_DAIFMT_DSP_A:
reg_val |= RT5660_I2S_DF_PCM_A;
break;
case SND_SOC_DAIFMT_DSP_B:
reg_val |= RT5660_I2S_DF_PCM_B;
break;
default:
return -EINVAL;
}
switch (dai->id) {
case RT5660_AIF1:
snd_soc_component_update_bits(component, RT5660_I2S1_SDP,
RT5660_I2S_MS_MASK | RT5660_I2S_BP_MASK |
RT5660_I2S_DF_MASK, reg_val);
break;
default:
dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
return -EINVAL;
}
return 0;
}
static int rt5660_set_dai_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct rt5660_priv *rt5660 = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0;
if (freq == rt5660->sysclk && clk_id == rt5660->sysclk_src)
return 0;
switch (clk_id) {
case RT5660_SCLK_S_MCLK:
reg_val |= RT5660_SCLK_SRC_MCLK;
break;
case RT5660_SCLK_S_PLL1:
reg_val |= RT5660_SCLK_SRC_PLL1;
break;
case RT5660_SCLK_S_RCCLK:
reg_val |= RT5660_SCLK_SRC_RCCLK;
break;
default:
dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
return -EINVAL;
}
snd_soc_component_update_bits(component, RT5660_GLB_CLK, RT5660_SCLK_SRC_MASK,
reg_val);
rt5660->sysclk = freq;
rt5660->sysclk_src = clk_id;
dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
return 0;
}
static int rt5660_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
unsigned int freq_in, unsigned int freq_out)
{
struct snd_soc_component *component = dai->component;
struct rt5660_priv *rt5660 = snd_soc_component_get_drvdata(component);
struct rl6231_pll_code pll_code;
int ret;
if (source == rt5660->pll_src && freq_in == rt5660->pll_in &&
freq_out == rt5660->pll_out)
return 0;
if (!freq_in || !freq_out) {
dev_dbg(component->dev, "PLL disabled\n");
rt5660->pll_in = 0;
rt5660->pll_out = 0;
snd_soc_component_update_bits(component, RT5660_GLB_CLK,
RT5660_SCLK_SRC_MASK, RT5660_SCLK_SRC_MCLK);
return 0;
}
switch (source) {
case RT5660_PLL1_S_MCLK:
snd_soc_component_update_bits(component, RT5660_GLB_CLK,
RT5660_PLL1_SRC_MASK, RT5660_PLL1_SRC_MCLK);
break;
case RT5660_PLL1_S_BCLK:
snd_soc_component_update_bits(component, RT5660_GLB_CLK,
RT5660_PLL1_SRC_MASK, RT5660_PLL1_SRC_BCLK1);
break;
default:
dev_err(component->dev, "Unknown PLL source %d\n", source);
return -EINVAL;
}
ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
if (ret < 0) {
dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
return ret;
}
dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
pll_code.n_code, pll_code.k_code);
snd_soc_component_write(component, RT5660_PLL_CTRL1,
pll_code.n_code << RT5660_PLL_N_SFT | pll_code.k_code);
snd_soc_component_write(component, RT5660_PLL_CTRL2,
((pll_code.m_bp ? 0 : pll_code.m_code) << RT5660_PLL_M_SFT) |
(pll_code.m_bp << RT5660_PLL_M_BP_SFT));
rt5660->pll_in = freq_in;
rt5660->pll_out = freq_out;
rt5660->pll_src = source;
return 0;
}
static int rt5660_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct rt5660_priv *rt5660 = snd_soc_component_get_drvdata(component);
int ret;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
snd_soc_component_update_bits(component, RT5660_GEN_CTRL1,
RT5660_DIG_GATE_CTRL, RT5660_DIG_GATE_CTRL);
if (IS_ERR(rt5660->mclk))
break;
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) {
clk_disable_unprepare(rt5660->mclk);
} else {
ret = clk_prepare_enable(rt5660->mclk);
if (ret)
return ret;
}
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
snd_soc_component_update_bits(component, RT5660_PWR_ANLG1,
RT5660_PWR_VREF1 | RT5660_PWR_MB |
RT5660_PWR_BG | RT5660_PWR_VREF2,
RT5660_PWR_VREF1 | RT5660_PWR_MB |
RT5660_PWR_BG | RT5660_PWR_VREF2);
usleep_range(10000, 15000);
snd_soc_component_update_bits(component, RT5660_PWR_ANLG1,
RT5660_PWR_FV1 | RT5660_PWR_FV2,
RT5660_PWR_FV1 | RT5660_PWR_FV2);
}
break;
case SND_SOC_BIAS_OFF:
snd_soc_component_update_bits(component, RT5660_GEN_CTRL1,
RT5660_DIG_GATE_CTRL, 0);
break;
default:
break;
}
return 0;
}
static int rt5660_probe(struct snd_soc_component *component)
{
struct rt5660_priv *rt5660 = snd_soc_component_get_drvdata(component);
rt5660->component = component;
return 0;
}
static void rt5660_remove(struct snd_soc_component *component)
{
snd_soc_component_write(component, RT5660_RESET, 0);
}
#ifdef CONFIG_PM
static int rt5660_suspend(struct snd_soc_component *component)
{
struct rt5660_priv *rt5660 = snd_soc_component_get_drvdata(component);
regcache_cache_only(rt5660->regmap, true);
regcache_mark_dirty(rt5660->regmap);
return 0;
}
static int rt5660_resume(struct snd_soc_component *component)
{
struct rt5660_priv *rt5660 = snd_soc_component_get_drvdata(component);
if (rt5660->pdata.poweroff_codec_in_suspend)
msleep(350);
regcache_cache_only(rt5660->regmap, false);
regcache_sync(rt5660->regmap);
return 0;
}
#else
#define rt5660_suspend NULL
#define rt5660_resume NULL
#endif
#define RT5660_STEREO_RATES SNDRV_PCM_RATE_8000_192000
#define RT5660_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
static const struct snd_soc_dai_ops rt5660_aif_dai_ops = {
.hw_params = rt5660_hw_params,
.set_fmt = rt5660_set_dai_fmt,
.set_sysclk = rt5660_set_dai_sysclk,
.set_pll = rt5660_set_dai_pll,
};
static struct snd_soc_dai_driver rt5660_dai[] = {
{
.name = "rt5660-aif1",
.id = RT5660_AIF1,
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT5660_STEREO_RATES,
.formats = RT5660_FORMATS,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT5660_STEREO_RATES,
.formats = RT5660_FORMATS,
},
.ops = &rt5660_aif_dai_ops,
},
};
static const struct snd_soc_component_driver soc_component_dev_rt5660 = {
.probe = rt5660_probe,
.remove = rt5660_remove,
.suspend = rt5660_suspend,
.resume = rt5660_resume,
.set_bias_level = rt5660_set_bias_level,
.controls = rt5660_snd_controls,
.num_controls = ARRAY_SIZE(rt5660_snd_controls),
.dapm_widgets = rt5660_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt5660_dapm_widgets),
.dapm_routes = rt5660_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(rt5660_dapm_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config rt5660_regmap = {
.reg_bits = 8,
.val_bits = 16,
.use_single_read = true,
.use_single_write = true,
.max_register = RT5660_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5660_ranges) *
RT5660_PR_SPACING),
.volatile_reg = rt5660_volatile_register,
.readable_reg = rt5660_readable_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = rt5660_reg,
.num_reg_defaults = ARRAY_SIZE(rt5660_reg),
.ranges = rt5660_ranges,
.num_ranges = ARRAY_SIZE(rt5660_ranges),
};
static const struct i2c_device_id rt5660_i2c_id[] = {
{ "rt5660", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, rt5660_i2c_id);
#ifdef CONFIG_OF
static const struct of_device_id rt5660_of_match[] = {
{ .compatible = "realtek,rt5660", },
{},
};
MODULE_DEVICE_TABLE(of, rt5660_of_match);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id rt5660_acpi_match[] = {
{ "10EC5660", 0 },
{ "10EC3277", 0 },
{ },
};
MODULE_DEVICE_TABLE(acpi, rt5660_acpi_match);
#endif
static int rt5660_parse_dt(struct rt5660_priv *rt5660, struct device *dev)
{
rt5660->pdata.in1_diff = device_property_read_bool(dev,
"realtek,in1-differential");
rt5660->pdata.in3_diff = device_property_read_bool(dev,
"realtek,in3-differential");
rt5660->pdata.poweroff_codec_in_suspend = device_property_read_bool(dev,
"realtek,poweroff-in-suspend");
device_property_read_u32(dev, "realtek,dmic1-data-pin",
&rt5660->pdata.dmic1_data_pin);
return 0;
}
static int rt5660_i2c_probe(struct i2c_client *i2c)
{
struct rt5660_platform_data *pdata = dev_get_platdata(&i2c->dev);
struct rt5660_priv *rt5660;
int ret;
unsigned int val;
rt5660 = devm_kzalloc(&i2c->dev, sizeof(struct rt5660_priv),
GFP_KERNEL);
if (rt5660 == NULL)
return -ENOMEM;
/* Check if MCLK provided */
rt5660->mclk = devm_clk_get(&i2c->dev, "mclk");
if (PTR_ERR(rt5660->mclk) == -EPROBE_DEFER)
return -EPROBE_DEFER;
i2c_set_clientdata(i2c, rt5660);
if (pdata)
rt5660->pdata = *pdata;
else if (i2c->dev.of_node)
rt5660_parse_dt(rt5660, &i2c->dev);
rt5660->regmap = devm_regmap_init_i2c(i2c, &rt5660_regmap);
if (IS_ERR(rt5660->regmap)) {
ret = PTR_ERR(rt5660->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
regmap_read(rt5660->regmap, RT5660_VENDOR_ID2, &val);
if (val != RT5660_DEVICE_ID) {
dev_err(&i2c->dev,
"Device with ID register %#x is not rt5660\n", val);
return -ENODEV;
}
regmap_write(rt5660->regmap, RT5660_RESET, 0);
ret = regmap_register_patch(rt5660->regmap, rt5660_patch,
ARRAY_SIZE(rt5660_patch));
if (ret != 0)
dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
regmap_update_bits(rt5660->regmap, RT5660_GEN_CTRL1,
RT5660_AUTO_DIS_AMP | RT5660_MCLK_DET | RT5660_POW_CLKDET,
RT5660_AUTO_DIS_AMP | RT5660_MCLK_DET | RT5660_POW_CLKDET);
if (rt5660->pdata.dmic1_data_pin) {
regmap_update_bits(rt5660->regmap, RT5660_GPIO_CTRL1,
RT5660_GP1_PIN_MASK, RT5660_GP1_PIN_DMIC1_SCL);
if (rt5660->pdata.dmic1_data_pin == RT5660_DMIC1_DATA_GPIO2)
regmap_update_bits(rt5660->regmap, RT5660_DMIC_CTRL1,
RT5660_SEL_DMIC_DATA_MASK,
RT5660_SEL_DMIC_DATA_GPIO2);
else if (rt5660->pdata.dmic1_data_pin == RT5660_DMIC1_DATA_IN1P)
regmap_update_bits(rt5660->regmap, RT5660_DMIC_CTRL1,
RT5660_SEL_DMIC_DATA_MASK,
RT5660_SEL_DMIC_DATA_IN1P);
}
return devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_rt5660,
rt5660_dai, ARRAY_SIZE(rt5660_dai));
}
static struct i2c_driver rt5660_i2c_driver = {
.driver = {
.name = "rt5660",
.acpi_match_table = ACPI_PTR(rt5660_acpi_match),
.of_match_table = of_match_ptr(rt5660_of_match),
},
.probe = rt5660_i2c_probe,
.id_table = rt5660_i2c_id,
};
module_i2c_driver(rt5660_i2c_driver);
MODULE_DESCRIPTION("ASoC RT5660 driver");
MODULE_AUTHOR("Oder Chiou <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/rt5660.c |
// SPDX-License-Identifier: GPL-2.0
//
// rt700.c -- rt700 ALSA SoC audio driver
//
// Copyright(c) 2019 Realtek Semiconductor Corp.
//
//
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm_runtime.h>
#include <linux/pm.h>
#include <linux/soundwire/sdw.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/sdw.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/hda_verbs.h>
#include <sound/jack.h>
#include "rt700.h"
static int rt700_index_write(struct regmap *regmap,
unsigned int reg, unsigned int value)
{
int ret;
unsigned int addr = (RT700_PRIV_INDEX_W_H << 8) | reg;
ret = regmap_write(regmap, addr, value);
if (ret < 0)
pr_err("Failed to set private value: %06x <= %04x ret=%d\n",
addr, value, ret);
return ret;
}
static int rt700_index_read(struct regmap *regmap,
unsigned int reg, unsigned int *value)
{
int ret;
unsigned int addr = (RT700_PRIV_INDEX_W_H << 8) | reg;
*value = 0;
ret = regmap_read(regmap, addr, value);
if (ret < 0)
pr_err("Failed to get private value: %06x => %04x ret=%d\n",
addr, *value, ret);
return ret;
}
static unsigned int rt700_button_detect(struct rt700_priv *rt700)
{
unsigned int btn_type = 0, val80, val81;
int ret;
ret = rt700_index_read(rt700->regmap, RT700_IRQ_FLAG_TABLE1, &val80);
if (ret < 0)
goto read_error;
ret = rt700_index_read(rt700->regmap, RT700_IRQ_FLAG_TABLE2, &val81);
if (ret < 0)
goto read_error;
val80 &= 0x0381;
val81 &= 0xff00;
switch (val80) {
case 0x0200:
case 0x0100:
case 0x0080:
btn_type |= SND_JACK_BTN_0;
break;
case 0x0001:
btn_type |= SND_JACK_BTN_3;
break;
}
switch (val81) {
case 0x8000:
case 0x4000:
case 0x2000:
btn_type |= SND_JACK_BTN_1;
break;
case 0x1000:
case 0x0800:
case 0x0400:
btn_type |= SND_JACK_BTN_2;
break;
case 0x0200:
case 0x0100:
btn_type |= SND_JACK_BTN_3;
break;
}
read_error:
return btn_type;
}
static int rt700_headset_detect(struct rt700_priv *rt700)
{
unsigned int buf, loop = 0;
int ret;
unsigned int jack_status = 0, reg;
ret = rt700_index_read(rt700->regmap,
RT700_COMBO_JACK_AUTO_CTL2, &buf);
if (ret < 0)
goto io_error;
while (loop < 500 &&
(buf & RT700_COMBOJACK_AUTO_DET_STATUS) == 0) {
loop++;
usleep_range(9000, 10000);
ret = rt700_index_read(rt700->regmap,
RT700_COMBO_JACK_AUTO_CTL2, &buf);
if (ret < 0)
goto io_error;
reg = RT700_VERB_GET_PIN_SENSE | RT700_HP_OUT;
ret = regmap_read(rt700->regmap, reg, &jack_status);
if ((jack_status & (1 << 31)) == 0)
goto remove_error;
}
if (loop >= 500)
goto to_error;
if (buf & RT700_COMBOJACK_AUTO_DET_TRS)
rt700->jack_type = SND_JACK_HEADPHONE;
else if ((buf & RT700_COMBOJACK_AUTO_DET_CTIA) ||
(buf & RT700_COMBOJACK_AUTO_DET_OMTP))
rt700->jack_type = SND_JACK_HEADSET;
return 0;
to_error:
ret = -ETIMEDOUT;
pr_err_ratelimited("Time-out error in %s\n", __func__);
return ret;
io_error:
pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret);
return ret;
remove_error:
pr_err_ratelimited("Jack removal in %s\n", __func__);
return -ENODEV;
}
static void rt700_jack_detect_handler(struct work_struct *work)
{
struct rt700_priv *rt700 =
container_of(work, struct rt700_priv, jack_detect_work.work);
int btn_type = 0, ret;
unsigned int jack_status = 0, reg;
if (!rt700->hs_jack)
return;
if (!snd_soc_card_is_instantiated(rt700->component->card))
return;
reg = RT700_VERB_GET_PIN_SENSE | RT700_HP_OUT;
ret = regmap_read(rt700->regmap, reg, &jack_status);
if (ret < 0)
goto io_error;
/* pin attached */
if (jack_status & (1 << 31)) {
/* jack in */
if (rt700->jack_type == 0) {
ret = rt700_headset_detect(rt700);
if (ret < 0)
return;
if (rt700->jack_type == SND_JACK_HEADSET)
btn_type = rt700_button_detect(rt700);
} else if (rt700->jack_type == SND_JACK_HEADSET) {
/* jack is already in, report button event */
btn_type = rt700_button_detect(rt700);
}
} else {
/* jack out */
rt700->jack_type = 0;
}
dev_dbg(&rt700->slave->dev,
"in %s, jack_type=0x%x\n", __func__, rt700->jack_type);
dev_dbg(&rt700->slave->dev,
"in %s, btn_type=0x%x\n", __func__, btn_type);
snd_soc_jack_report(rt700->hs_jack, rt700->jack_type | btn_type,
SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3);
if (btn_type) {
/* button released */
snd_soc_jack_report(rt700->hs_jack, rt700->jack_type,
SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3);
mod_delayed_work(system_power_efficient_wq,
&rt700->jack_btn_check_work, msecs_to_jiffies(200));
}
return;
io_error:
pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret);
}
static void rt700_btn_check_handler(struct work_struct *work)
{
struct rt700_priv *rt700 = container_of(work, struct rt700_priv,
jack_btn_check_work.work);
int btn_type = 0, ret;
unsigned int jack_status = 0, reg;
reg = RT700_VERB_GET_PIN_SENSE | RT700_HP_OUT;
ret = regmap_read(rt700->regmap, reg, &jack_status);
if (ret < 0)
goto io_error;
/* pin attached */
if (jack_status & (1 << 31)) {
if (rt700->jack_type == SND_JACK_HEADSET) {
/* jack is already in, report button event */
btn_type = rt700_button_detect(rt700);
}
} else {
rt700->jack_type = 0;
}
/* cbj comparator */
ret = rt700_index_read(rt700->regmap, RT700_COMBO_JACK_AUTO_CTL2, ®);
if (ret < 0)
goto io_error;
if ((reg & 0xf0) == 0xf0)
btn_type = 0;
dev_dbg(&rt700->slave->dev,
"%s, btn_type=0x%x\n", __func__, btn_type);
snd_soc_jack_report(rt700->hs_jack, rt700->jack_type | btn_type,
SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3);
if (btn_type) {
/* button released */
snd_soc_jack_report(rt700->hs_jack, rt700->jack_type,
SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3);
mod_delayed_work(system_power_efficient_wq,
&rt700->jack_btn_check_work, msecs_to_jiffies(200));
}
return;
io_error:
pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret);
}
static void rt700_jack_init(struct rt700_priv *rt700)
{
struct snd_soc_dapm_context *dapm =
snd_soc_component_get_dapm(rt700->component);
/* power on */
if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
regmap_write(rt700->regmap,
RT700_SET_AUDIO_POWER_STATE, AC_PWRST_D0);
if (rt700->hs_jack) {
/* Enable Jack Detection */
regmap_write(rt700->regmap,
RT700_SET_MIC2_UNSOLICITED_ENABLE, 0x82);
regmap_write(rt700->regmap,
RT700_SET_HP_UNSOLICITED_ENABLE, 0x81);
regmap_write(rt700->regmap,
RT700_SET_INLINE_UNSOLICITED_ENABLE, 0x83);
rt700_index_write(rt700->regmap, 0x10, 0x2420);
rt700_index_write(rt700->regmap, 0x19, 0x2e11);
dev_dbg(&rt700->slave->dev, "in %s enable\n", __func__);
mod_delayed_work(system_power_efficient_wq,
&rt700->jack_detect_work, msecs_to_jiffies(250));
} else {
regmap_write(rt700->regmap,
RT700_SET_MIC2_UNSOLICITED_ENABLE, 0x00);
regmap_write(rt700->regmap,
RT700_SET_HP_UNSOLICITED_ENABLE, 0x00);
regmap_write(rt700->regmap,
RT700_SET_INLINE_UNSOLICITED_ENABLE, 0x00);
dev_dbg(&rt700->slave->dev, "in %s disable\n", __func__);
}
/* power off */
if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
regmap_write(rt700->regmap,
RT700_SET_AUDIO_POWER_STATE, AC_PWRST_D3);
}
static int rt700_set_jack_detect(struct snd_soc_component *component,
struct snd_soc_jack *hs_jack, void *data)
{
struct rt700_priv *rt700 = snd_soc_component_get_drvdata(component);
int ret;
rt700->hs_jack = hs_jack;
/* we can only resume if the device was initialized at least once */
if (!rt700->first_hw_init)
return 0;
ret = pm_runtime_resume_and_get(component->dev);
if (ret < 0) {
if (ret != -EACCES) {
dev_err(component->dev, "%s: failed to resume %d\n", __func__, ret);
return ret;
}
/* pm_runtime not enabled yet */
dev_dbg(component->dev, "%s: skipping jack init for now\n", __func__);
return 0;
}
rt700_jack_init(rt700);
pm_runtime_mark_last_busy(component->dev);
pm_runtime_put_autosuspend(component->dev);
return 0;
}
static void rt700_get_gain(struct rt700_priv *rt700, unsigned int addr_h,
unsigned int addr_l, unsigned int val_h,
unsigned int *r_val, unsigned int *l_val)
{
/* R Channel */
*r_val = (val_h << 8);
regmap_read(rt700->regmap, addr_l, r_val);
/* L Channel */
val_h |= 0x20;
*l_val = (val_h << 8);
regmap_read(rt700->regmap, addr_h, l_val);
}
/* For Verb-Set Amplifier Gain (Verb ID = 3h) */
static int rt700_set_amp_gain_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct snd_soc_dapm_context *dapm =
snd_soc_component_get_dapm(component);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct rt700_priv *rt700 = snd_soc_component_get_drvdata(component);
unsigned int addr_h, addr_l, val_h, val_ll, val_lr;
unsigned int read_ll, read_rl;
int i;
/* Can't use update bit function, so read the original value first */
addr_h = mc->reg;
addr_l = mc->rreg;
if (mc->shift == RT700_DIR_OUT_SFT) /* output */
val_h = 0x80;
else /* input */
val_h = 0x0;
rt700_get_gain(rt700, addr_h, addr_l, val_h, &read_rl, &read_ll);
/* L Channel */
if (mc->invert) {
/* for mute */
val_ll = (mc->max - ucontrol->value.integer.value[0]) << 7;
/* keep gain */
read_ll = read_ll & 0x7f;
val_ll |= read_ll;
} else {
/* for gain */
val_ll = ((ucontrol->value.integer.value[0]) & 0x7f);
if (val_ll > mc->max)
val_ll = mc->max;
/* keep mute status */
read_ll = read_ll & 0x80;
val_ll |= read_ll;
}
if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
regmap_write(rt700->regmap,
RT700_SET_AUDIO_POWER_STATE, AC_PWRST_D0);
/* R Channel */
if (mc->invert) {
/* for mute */
val_lr = (mc->max - ucontrol->value.integer.value[1]) << 7;
/* keep gain */
read_rl = read_rl & 0x7f;
val_lr |= read_rl;
} else {
/* for gain */
val_lr = ((ucontrol->value.integer.value[1]) & 0x7f);
if (val_lr > mc->max)
val_lr = mc->max;
/* keep mute status */
read_rl = read_rl & 0x80;
val_lr |= read_rl;
}
for (i = 0; i < 3; i++) { /* retry 3 times at most */
if (val_ll == val_lr) {
/* Set both L/R channels at the same time */
val_h = (1 << mc->shift) | (3 << 4);
regmap_write(rt700->regmap,
addr_h, (val_h << 8 | val_ll));
regmap_write(rt700->regmap,
addr_l, (val_h << 8 | val_ll));
} else {
/* Lch*/
val_h = (1 << mc->shift) | (1 << 5);
regmap_write(rt700->regmap,
addr_h, (val_h << 8 | val_ll));
/* Rch */
val_h = (1 << mc->shift) | (1 << 4);
regmap_write(rt700->regmap,
addr_l, (val_h << 8 | val_lr));
}
/* check result */
if (mc->shift == RT700_DIR_OUT_SFT) /* output */
val_h = 0x80;
else /* input */
val_h = 0x0;
rt700_get_gain(rt700, addr_h, addr_l, val_h,
&read_rl, &read_ll);
if (read_rl == val_lr && read_ll == val_ll)
break;
}
if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
regmap_write(rt700->regmap,
RT700_SET_AUDIO_POWER_STATE, AC_PWRST_D3);
return 0;
}
static int rt700_set_amp_gain_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt700_priv *rt700 = snd_soc_component_get_drvdata(component);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
unsigned int addr_h, addr_l, val_h;
unsigned int read_ll, read_rl;
addr_h = mc->reg;
addr_l = mc->rreg;
if (mc->shift == RT700_DIR_OUT_SFT) /* output */
val_h = 0x80;
else /* input */
val_h = 0x0;
rt700_get_gain(rt700, addr_h, addr_l, val_h, &read_rl, &read_ll);
if (mc->invert) {
/* for mute status */
read_ll = !((read_ll & 0x80) >> RT700_MUTE_SFT);
read_rl = !((read_rl & 0x80) >> RT700_MUTE_SFT);
} else {
/* for gain */
read_ll = read_ll & 0x7f;
read_rl = read_rl & 0x7f;
}
ucontrol->value.integer.value[0] = read_ll;
ucontrol->value.integer.value[1] = read_rl;
return 0;
}
static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0);
static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -1725, 75, 0);
static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
static const struct snd_kcontrol_new rt700_snd_controls[] = {
SOC_DOUBLE_R_EXT_TLV("DAC Front Playback Volume",
RT700_SET_GAIN_DAC1_H, RT700_SET_GAIN_DAC1_L,
RT700_DIR_OUT_SFT, 0x57, 0,
rt700_set_amp_gain_get, rt700_set_amp_gain_put, out_vol_tlv),
SOC_DOUBLE_R_EXT("ADC 08 Capture Switch",
RT700_SET_GAIN_ADC2_H, RT700_SET_GAIN_ADC2_L,
RT700_DIR_IN_SFT, 1, 1,
rt700_set_amp_gain_get, rt700_set_amp_gain_put),
SOC_DOUBLE_R_EXT("ADC 09 Capture Switch",
RT700_SET_GAIN_ADC1_H, RT700_SET_GAIN_ADC1_L,
RT700_DIR_IN_SFT, 1, 1,
rt700_set_amp_gain_get, rt700_set_amp_gain_put),
SOC_DOUBLE_R_EXT_TLV("ADC 08 Capture Volume",
RT700_SET_GAIN_ADC2_H, RT700_SET_GAIN_ADC2_L,
RT700_DIR_IN_SFT, 0x3f, 0,
rt700_set_amp_gain_get, rt700_set_amp_gain_put, in_vol_tlv),
SOC_DOUBLE_R_EXT_TLV("ADC 09 Capture Volume",
RT700_SET_GAIN_ADC1_H, RT700_SET_GAIN_ADC1_L,
RT700_DIR_IN_SFT, 0x3f, 0,
rt700_set_amp_gain_get, rt700_set_amp_gain_put, in_vol_tlv),
SOC_DOUBLE_R_EXT_TLV("AMIC Volume",
RT700_SET_GAIN_AMIC_H, RT700_SET_GAIN_AMIC_L,
RT700_DIR_IN_SFT, 3, 0,
rt700_set_amp_gain_get, rt700_set_amp_gain_put, mic_vol_tlv),
};
static int rt700_mux_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_dapm_kcontrol_component(kcontrol);
struct rt700_priv *rt700 = snd_soc_component_get_drvdata(component);
unsigned int reg, val = 0, nid;
int ret;
if (strstr(ucontrol->id.name, "HPO Mux"))
nid = RT700_HP_OUT;
else if (strstr(ucontrol->id.name, "ADC 22 Mux"))
nid = RT700_MIXER_IN1;
else if (strstr(ucontrol->id.name, "ADC 23 Mux"))
nid = RT700_MIXER_IN2;
else
return -EINVAL;
/* vid = 0xf01 */
reg = RT700_VERB_SET_CONNECT_SEL | nid;
ret = regmap_read(rt700->regmap, reg, &val);
if (ret < 0)
return ret;
ucontrol->value.enumerated.item[0] = val;
return 0;
}
static int rt700_mux_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_dapm_kcontrol_component(kcontrol);
struct snd_soc_dapm_context *dapm =
snd_soc_dapm_kcontrol_dapm(kcontrol);
struct rt700_priv *rt700 = snd_soc_component_get_drvdata(component);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int *item = ucontrol->value.enumerated.item;
unsigned int val, val2 = 0, change, reg, nid;
int ret;
if (item[0] >= e->items)
return -EINVAL;
if (strstr(ucontrol->id.name, "HPO Mux"))
nid = RT700_HP_OUT;
else if (strstr(ucontrol->id.name, "ADC 22 Mux"))
nid = RT700_MIXER_IN1;
else if (strstr(ucontrol->id.name, "ADC 23 Mux"))
nid = RT700_MIXER_IN2;
else
return -EINVAL;
/* Verb ID = 0x701h */
val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
reg = RT700_VERB_SET_CONNECT_SEL | nid;
ret = regmap_read(rt700->regmap, reg, &val2);
if (ret < 0)
return ret;
if (val == val2)
change = 0;
else
change = 1;
if (change) {
reg = RT700_VERB_SET_CONNECT_SEL | nid;
regmap_write(rt700->regmap, reg, val);
}
snd_soc_dapm_mux_update_power(dapm, kcontrol,
item[0], e, NULL);
return change;
}
static const char * const adc_mux_text[] = {
"MIC2",
"LINE1",
"LINE2",
"DMIC",
};
static SOC_ENUM_SINGLE_DECL(
rt700_adc22_enum, SND_SOC_NOPM, 0, adc_mux_text);
static SOC_ENUM_SINGLE_DECL(
rt700_adc23_enum, SND_SOC_NOPM, 0, adc_mux_text);
static const struct snd_kcontrol_new rt700_adc22_mux =
SOC_DAPM_ENUM_EXT("ADC 22 Mux", rt700_adc22_enum,
rt700_mux_get, rt700_mux_put);
static const struct snd_kcontrol_new rt700_adc23_mux =
SOC_DAPM_ENUM_EXT("ADC 23 Mux", rt700_adc23_enum,
rt700_mux_get, rt700_mux_put);
static const char * const out_mux_text[] = {
"Front",
"Surround",
};
static SOC_ENUM_SINGLE_DECL(
rt700_hp_enum, SND_SOC_NOPM, 0, out_mux_text);
static const struct snd_kcontrol_new rt700_hp_mux =
SOC_DAPM_ENUM_EXT("HP Mux", rt700_hp_enum,
rt700_mux_get, rt700_mux_put);
static int rt700_dac_front_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt700_priv *rt700 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_write(rt700->regmap,
RT700_SET_STREAMID_DAC1, 0x10);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_write(rt700->regmap,
RT700_SET_STREAMID_DAC1, 0x00);
break;
}
return 0;
}
static int rt700_dac_surround_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt700_priv *rt700 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_write(rt700->regmap,
RT700_SET_STREAMID_DAC2, 0x10);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_write(rt700->regmap,
RT700_SET_STREAMID_DAC2, 0x00);
break;
}
return 0;
}
static int rt700_adc_09_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt700_priv *rt700 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_write(rt700->regmap,
RT700_SET_STREAMID_ADC1, 0x10);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_write(rt700->regmap,
RT700_SET_STREAMID_ADC1, 0x00);
break;
}
return 0;
}
static int rt700_adc_08_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt700_priv *rt700 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_write(rt700->regmap,
RT700_SET_STREAMID_ADC2, 0x10);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_write(rt700->regmap,
RT700_SET_STREAMID_ADC2, 0x00);
break;
}
return 0;
}
static int rt700_hpo_mux_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt700_priv *rt700 = snd_soc_component_get_drvdata(component);
unsigned int val_h = (1 << RT700_DIR_OUT_SFT) | (0x3 << 4);
unsigned int val_l;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
val_l = 0x00;
regmap_write(rt700->regmap,
RT700_SET_GAIN_HP_H, (val_h << 8 | val_l));
break;
case SND_SOC_DAPM_PRE_PMD:
val_l = (1 << RT700_MUTE_SFT);
regmap_write(rt700->regmap,
RT700_SET_GAIN_HP_H, (val_h << 8 | val_l));
usleep_range(50000, 55000);
break;
}
return 0;
}
static int rt700_spk_pga_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt700_priv *rt700 = snd_soc_component_get_drvdata(component);
unsigned int val_h = (1 << RT700_DIR_OUT_SFT) | (0x3 << 4);
unsigned int val_l;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
val_l = 0x00;
regmap_write(rt700->regmap,
RT700_SET_GAIN_SPK_H, (val_h << 8 | val_l));
break;
case SND_SOC_DAPM_PRE_PMD:
val_l = (1 << RT700_MUTE_SFT);
regmap_write(rt700->regmap,
RT700_SET_GAIN_SPK_H, (val_h << 8 | val_l));
break;
}
return 0;
}
static const struct snd_soc_dapm_widget rt700_dapm_widgets[] = {
SND_SOC_DAPM_OUTPUT("HP"),
SND_SOC_DAPM_OUTPUT("SPK"),
SND_SOC_DAPM_INPUT("DMIC1"),
SND_SOC_DAPM_INPUT("DMIC2"),
SND_SOC_DAPM_INPUT("MIC2"),
SND_SOC_DAPM_INPUT("LINE1"),
SND_SOC_DAPM_INPUT("LINE2"),
SND_SOC_DAPM_DAC_E("DAC Front", NULL, SND_SOC_NOPM, 0, 0,
rt700_dac_front_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_DAC_E("DAC Surround", NULL, SND_SOC_NOPM, 0, 0,
rt700_dac_surround_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_MUX_E("HPO Mux", SND_SOC_NOPM, 0, 0, &rt700_hp_mux,
rt700_hpo_mux_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA_E("SPK PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
rt700_spk_pga_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_ADC_E("ADC 09", NULL, SND_SOC_NOPM, 0, 0,
rt700_adc_09_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_ADC_E("ADC 08", NULL, SND_SOC_NOPM, 0, 0,
rt700_adc_08_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_MUX("ADC 22 Mux", SND_SOC_NOPM, 0, 0,
&rt700_adc22_mux),
SND_SOC_DAPM_MUX("ADC 23 Mux", SND_SOC_NOPM, 0, 0,
&rt700_adc23_mux),
SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("DP3RX", "DP3 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("DP2TX", "DP2 Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0),
};
static const struct snd_soc_dapm_route rt700_audio_map[] = {
{"DAC Front", NULL, "DP1RX"},
{"DAC Surround", NULL, "DP3RX"},
{"DP2TX", NULL, "ADC 09"},
{"DP4TX", NULL, "ADC 08"},
{"ADC 09", NULL, "ADC 22 Mux"},
{"ADC 08", NULL, "ADC 23 Mux"},
{"ADC 22 Mux", "DMIC", "DMIC1"},
{"ADC 22 Mux", "LINE1", "LINE1"},
{"ADC 22 Mux", "LINE2", "LINE2"},
{"ADC 22 Mux", "MIC2", "MIC2"},
{"ADC 23 Mux", "DMIC", "DMIC2"},
{"ADC 23 Mux", "LINE1", "LINE1"},
{"ADC 23 Mux", "LINE2", "LINE2"},
{"ADC 23 Mux", "MIC2", "MIC2"},
{"HPO Mux", "Front", "DAC Front"},
{"HPO Mux", "Surround", "DAC Surround"},
{"HP", NULL, "HPO Mux"},
{"SPK PGA", NULL, "DAC Front"},
{"SPK", NULL, "SPK PGA"},
};
static int rt700_probe(struct snd_soc_component *component)
{
struct rt700_priv *rt700 = snd_soc_component_get_drvdata(component);
int ret;
rt700->component = component;
if (!rt700->first_hw_init)
return 0;
ret = pm_runtime_resume(component->dev);
if (ret < 0 && ret != -EACCES)
return ret;
return 0;
}
static int rt700_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct snd_soc_dapm_context *dapm =
snd_soc_component_get_dapm(component);
struct rt700_priv *rt700 = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_PREPARE:
if (dapm->bias_level == SND_SOC_BIAS_STANDBY) {
regmap_write(rt700->regmap,
RT700_SET_AUDIO_POWER_STATE,
AC_PWRST_D0);
}
break;
case SND_SOC_BIAS_STANDBY:
regmap_write(rt700->regmap,
RT700_SET_AUDIO_POWER_STATE,
AC_PWRST_D3);
break;
default:
break;
}
dapm->bias_level = level;
return 0;
}
static const struct snd_soc_component_driver soc_codec_dev_rt700 = {
.probe = rt700_probe,
.set_bias_level = rt700_set_bias_level,
.controls = rt700_snd_controls,
.num_controls = ARRAY_SIZE(rt700_snd_controls),
.dapm_widgets = rt700_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt700_dapm_widgets),
.dapm_routes = rt700_audio_map,
.num_dapm_routes = ARRAY_SIZE(rt700_audio_map),
.set_jack = rt700_set_jack_detect,
.endianness = 1,
};
static int rt700_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
int direction)
{
snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
return 0;
}
static void rt700_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
snd_soc_dai_set_dma_data(dai, substream, NULL);
}
static int rt700_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt700_priv *rt700 = snd_soc_component_get_drvdata(component);
struct sdw_stream_config stream_config = {0};
struct sdw_port_config port_config = {0};
struct sdw_stream_runtime *sdw_stream;
int retval;
unsigned int val = 0;
dev_dbg(dai->dev, "%s %s", __func__, dai->name);
sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
if (!sdw_stream)
return -EINVAL;
if (!rt700->slave)
return -EINVAL;
/* SoundWire specific configuration */
snd_sdw_params_to_config(substream, params, &stream_config, &port_config);
/* This code assumes port 1 for playback and port 2 for capture */
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
port_config.num = 1;
else
port_config.num = 2;
switch (dai->id) {
case RT700_AIF1:
break;
case RT700_AIF2:
port_config.num += 2;
break;
default:
dev_err(component->dev, "Invalid DAI id %d\n", dai->id);
return -EINVAL;
}
retval = sdw_stream_add_slave(rt700->slave, &stream_config,
&port_config, 1, sdw_stream);
if (retval) {
dev_err(dai->dev, "Unable to configure port\n");
return retval;
}
if (params_channels(params) <= 16) {
/* bit 3:0 Number of Channel */
val |= (params_channels(params) - 1);
} else {
dev_err(component->dev, "Unsupported channels %d\n",
params_channels(params));
return -EINVAL;
}
switch (params_width(params)) {
/* bit 6:4 Bits per Sample */
case 8:
break;
case 16:
val |= (0x1 << 4);
break;
case 20:
val |= (0x2 << 4);
break;
case 24:
val |= (0x3 << 4);
break;
case 32:
val |= (0x4 << 4);
break;
default:
return -EINVAL;
}
/* 48Khz */
regmap_write(rt700->regmap, RT700_DAC_FORMAT_H, val);
regmap_write(rt700->regmap, RT700_ADC_FORMAT_H, val);
return retval;
}
static int rt700_pcm_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt700_priv *rt700 = snd_soc_component_get_drvdata(component);
struct sdw_stream_runtime *sdw_stream =
snd_soc_dai_get_dma_data(dai, substream);
if (!rt700->slave)
return -EINVAL;
sdw_stream_remove_slave(rt700->slave, sdw_stream);
return 0;
}
#define RT700_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
#define RT700_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
static const struct snd_soc_dai_ops rt700_ops = {
.hw_params = rt700_pcm_hw_params,
.hw_free = rt700_pcm_hw_free,
.set_stream = rt700_set_sdw_stream,
.shutdown = rt700_shutdown,
};
static struct snd_soc_dai_driver rt700_dai[] = {
{
.name = "rt700-aif1",
.id = RT700_AIF1,
.playback = {
.stream_name = "DP1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT700_STEREO_RATES,
.formats = RT700_FORMATS,
},
.capture = {
.stream_name = "DP2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT700_STEREO_RATES,
.formats = RT700_FORMATS,
},
.ops = &rt700_ops,
},
{
.name = "rt700-aif2",
.id = RT700_AIF2,
.playback = {
.stream_name = "DP3 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT700_STEREO_RATES,
.formats = RT700_FORMATS,
},
.capture = {
.stream_name = "DP4 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT700_STEREO_RATES,
.formats = RT700_FORMATS,
},
.ops = &rt700_ops,
},
};
/* Bus clock frequency */
#define RT700_CLK_FREQ_9600000HZ 9600000
#define RT700_CLK_FREQ_12000000HZ 12000000
#define RT700_CLK_FREQ_6000000HZ 6000000
#define RT700_CLK_FREQ_4800000HZ 4800000
#define RT700_CLK_FREQ_2400000HZ 2400000
#define RT700_CLK_FREQ_12288000HZ 12288000
int rt700_clock_config(struct device *dev)
{
struct rt700_priv *rt700 = dev_get_drvdata(dev);
unsigned int clk_freq, value;
clk_freq = (rt700->params.curr_dr_freq >> 1);
switch (clk_freq) {
case RT700_CLK_FREQ_12000000HZ:
value = 0x0;
break;
case RT700_CLK_FREQ_6000000HZ:
value = 0x1;
break;
case RT700_CLK_FREQ_9600000HZ:
value = 0x2;
break;
case RT700_CLK_FREQ_4800000HZ:
value = 0x3;
break;
case RT700_CLK_FREQ_2400000HZ:
value = 0x4;
break;
case RT700_CLK_FREQ_12288000HZ:
value = 0x5;
break;
default:
return -EINVAL;
}
regmap_write(rt700->regmap, 0xe0, value);
regmap_write(rt700->regmap, 0xf0, value);
dev_dbg(dev, "%s complete, clk_freq=%d\n", __func__, clk_freq);
return 0;
}
int rt700_init(struct device *dev, struct regmap *sdw_regmap,
struct regmap *regmap, struct sdw_slave *slave)
{
struct rt700_priv *rt700;
int ret;
rt700 = devm_kzalloc(dev, sizeof(*rt700), GFP_KERNEL);
if (!rt700)
return -ENOMEM;
dev_set_drvdata(dev, rt700);
rt700->slave = slave;
rt700->sdw_regmap = sdw_regmap;
rt700->regmap = regmap;
regcache_cache_only(rt700->regmap, true);
mutex_init(&rt700->disable_irq_lock);
INIT_DELAYED_WORK(&rt700->jack_detect_work,
rt700_jack_detect_handler);
INIT_DELAYED_WORK(&rt700->jack_btn_check_work,
rt700_btn_check_handler);
/*
* Mark hw_init to false
* HW init will be performed when device reports present
*/
rt700->hw_init = false;
rt700->first_hw_init = false;
ret = devm_snd_soc_register_component(dev,
&soc_codec_dev_rt700,
rt700_dai,
ARRAY_SIZE(rt700_dai));
if (ret < 0)
return ret;
/* set autosuspend parameters */
pm_runtime_set_autosuspend_delay(dev, 3000);
pm_runtime_use_autosuspend(dev);
/* make sure the device does not suspend immediately */
pm_runtime_mark_last_busy(dev);
pm_runtime_enable(dev);
/* important note: the device is NOT tagged as 'active' and will remain
* 'suspended' until the hardware is enumerated/initialized. This is required
* to make sure the ASoC framework use of pm_runtime_get_sync() does not silently
* fail with -EACCESS because of race conditions between card creation and enumeration
*/
dev_dbg(&slave->dev, "%s\n", __func__);
return 0;
}
int rt700_io_init(struct device *dev, struct sdw_slave *slave)
{
struct rt700_priv *rt700 = dev_get_drvdata(dev);
rt700->disable_irq = false;
if (rt700->hw_init)
return 0;
regcache_cache_only(rt700->regmap, false);
if (rt700->first_hw_init)
regcache_cache_bypass(rt700->regmap, true);
/*
* PM runtime is only enabled when a Slave reports as Attached
*/
if (!rt700->first_hw_init)
/* PM runtime status is marked as 'active' only when a Slave reports as Attached */
pm_runtime_set_active(&slave->dev);
pm_runtime_get_noresume(&slave->dev);
/* reset */
regmap_write(rt700->regmap, 0xff01, 0x0000);
regmap_write(rt700->regmap, 0x7520, 0x001a);
regmap_write(rt700->regmap, 0x7420, 0xc003);
/* power on */
regmap_write(rt700->regmap, RT700_SET_AUDIO_POWER_STATE, AC_PWRST_D0);
/* Set Pin Widget */
regmap_write(rt700->regmap, RT700_SET_PIN_HP, 0x40);
regmap_write(rt700->regmap, RT700_SET_PIN_SPK, 0x40);
regmap_write(rt700->regmap, RT700_SET_EAPD_SPK, RT700_EAPD_HIGH);
regmap_write(rt700->regmap, RT700_SET_PIN_DMIC1, 0x20);
regmap_write(rt700->regmap, RT700_SET_PIN_DMIC2, 0x20);
regmap_write(rt700->regmap, RT700_SET_PIN_MIC2, 0x20);
/* Set Configuration Default */
regmap_write(rt700->regmap, 0x4f12, 0x91);
regmap_write(rt700->regmap, 0x4e12, 0xd6);
regmap_write(rt700->regmap, 0x4d12, 0x11);
regmap_write(rt700->regmap, 0x4c12, 0x20);
regmap_write(rt700->regmap, 0x4f13, 0x91);
regmap_write(rt700->regmap, 0x4e13, 0xd6);
regmap_write(rt700->regmap, 0x4d13, 0x11);
regmap_write(rt700->regmap, 0x4c13, 0x21);
regmap_write(rt700->regmap, 0x4f19, 0x02);
regmap_write(rt700->regmap, 0x4e19, 0xa1);
regmap_write(rt700->regmap, 0x4d19, 0x90);
regmap_write(rt700->regmap, 0x4c19, 0x80);
/* Enable Line2 */
regmap_write(rt700->regmap, 0x371b, 0x40);
regmap_write(rt700->regmap, 0x731b, 0xb0);
regmap_write(rt700->regmap, 0x839b, 0x00);
/* Set index */
rt700_index_write(rt700->regmap, 0x4a, 0x201b);
rt700_index_write(rt700->regmap, 0x45, 0x5089);
rt700_index_write(rt700->regmap, 0x6b, 0x5064);
rt700_index_write(rt700->regmap, 0x48, 0xd249);
/* Finish Initial Settings, set power to D3 */
regmap_write(rt700->regmap, RT700_SET_AUDIO_POWER_STATE, AC_PWRST_D3);
/*
* if set_jack callback occurred early than io_init,
* we set up the jack detection function now
*/
if (rt700->hs_jack)
rt700_jack_init(rt700);
if (rt700->first_hw_init) {
regcache_cache_bypass(rt700->regmap, false);
regcache_mark_dirty(rt700->regmap);
} else
rt700->first_hw_init = true;
/* Mark Slave initialization complete */
rt700->hw_init = true;
pm_runtime_mark_last_busy(&slave->dev);
pm_runtime_put_autosuspend(&slave->dev);
dev_dbg(&slave->dev, "%s hw_init complete\n", __func__);
return 0;
}
MODULE_DESCRIPTION("ASoC RT700 driver SDW");
MODULE_AUTHOR("Shuming Fan <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/rt700.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Driver for the PCM5102A codec
*
* Author: Florian Meier <[email protected]>
* Copyright 2013
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <sound/soc.h>
static struct snd_soc_dai_driver pcm5102a_dai = {
.name = "pcm5102a-hifi",
.playback = {
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_384000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S32_LE
},
};
static struct snd_soc_component_driver soc_component_dev_pcm5102a = {
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int pcm5102a_probe(struct platform_device *pdev)
{
return devm_snd_soc_register_component(&pdev->dev, &soc_component_dev_pcm5102a,
&pcm5102a_dai, 1);
}
static const struct of_device_id pcm5102a_of_match[] = {
{ .compatible = "ti,pcm5102a", },
{ }
};
MODULE_DEVICE_TABLE(of, pcm5102a_of_match);
static struct platform_driver pcm5102a_codec_driver = {
.probe = pcm5102a_probe,
.driver = {
.name = "pcm5102a-codec",
.of_match_table = pcm5102a_of_match,
},
};
module_platform_driver(pcm5102a_codec_driver);
MODULE_DESCRIPTION("ASoC PCM5102A codec driver");
MODULE_AUTHOR("Florian Meier <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/pcm5102a.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// rt1017-sdca-sdw.c -- rt1017 SDCA ALSA SoC amplifier audio driver
//
// Copyright(c) 2023 Realtek Semiconductor Corp.
//
//
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/pm_runtime.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "rt1017-sdca-sdw.h"
static bool rt1017_sdca_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x2f55:
case 0x3206:
case 0xc000:
case 0xc001:
case 0xc022:
case 0xc030:
case 0xc104:
case 0xc10b:
case 0xc10c:
case 0xc110:
case 0xc112:
case 0xc300:
case 0xc301:
case 0xc318:
case 0xc325 ... 0xc328:
case 0xc331:
case 0xc340:
case 0xc350 ... 0xc351:
case 0xc500:
case 0xc502:
case 0xc504:
case 0xc507:
case 0xc509:
case 0xc510:
case 0xc512:
case 0xc518:
case 0xc51b:
case 0xc51d:
case 0xc520:
case 0xc540 ... 0xc542:
case 0xc550 ... 0xc552:
case 0xc600:
case 0xc602:
case 0xc612:
case 0xc622:
case 0xc632:
case 0xc642:
case 0xc651:
case 0xca00:
case 0xca09 ... 0xca0c:
case 0xca0e ... 0xca0f:
case 0xca10 ... 0xca11:
case 0xca16 ... 0xca17:
case 0xcb00:
case 0xcc00:
case 0xcc02:
case 0xd017:
case 0xd01a ... 0xd01c:
case 0xd101:
case 0xd20c:
case 0xd300:
case 0xd370:
case 0xd500:
case 0xd545 ... 0xd548:
case 0xd5a5 ... 0xd5a8:
case 0xd5aa ... 0xd5ad:
case 0xda04 ... 0xda07:
case 0xda09 ... 0xda0a:
case 0xda0c ... 0xda0f:
case 0xda11 ... 0xda14:
case 0xda16 ... 0xda19:
case 0xdab6 ... 0xdabb:
case 0xdb09 ... 0xdb0a:
case 0xdb14:
case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_UDMPU21,
RT1017_SDCA_CTL_UDMPU_CLUSTER, 0):
case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_FU,
RT1017_SDCA_CTL_FU_MUTE, 0x01):
case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_XU22,
RT1017_SDCA_CTL_BYPASS, 0):
case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_SAPU29,
RT1017_SDCA_CTL_PROT_STAT, 0):
case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_CS21,
RT1017_SDCA_CTL_FS_INDEX, 0):
case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_PDE23,
RT1017_SDCA_CTL_REQ_POWER_STATE, 0):
case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_PDE22,
RT1017_SDCA_CTL_REQ_POWER_STATE, 0):
return true;
default:
return false;
}
}
static bool rt1017_sdca_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x2f55:
case 0xc000:
case 0xc022:
case 0xc351:
case 0xc518:
case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_SAPU29,
RT1017_SDCA_CTL_PROT_STAT, 0):
return true;
default:
return false;
}
}
static const struct reg_sequence rt1017_blind_write[] = {
{ 0xc001, 0x43 },
{ 0x2f55, 0x02 },
{ 0x3206, 0x80 },
{ 0x005f, 0x7f },
{ 0xd101, 0xa0 },
{ 0xc112, 0xc0 },
{ 0xc104, 0xaa },
{ 0xc110, 0x59 },
{ 0xc112, 0xc0 },
{ 0xc340, 0x80 },
{ 0xd017, 0x2c },
{ 0xd01a, 0xc8 },
{ 0xd01b, 0xcf },
{ 0xd01c, 0x0c },
{ 0xd20c, 0x14 },
{ 0xdb09, 0x0f },
{ 0xdb0a, 0x7f },
{ 0xdb14, 0x03 },
{ 0xcb00, 0x31 },
{ 0xc318, 0x44 },
{ 0xc325, 0xce },
{ 0xc326, 0x13 },
{ 0xc327, 0x5f },
{ 0xc328, 0xf3 },
{ 0xc350, 0xe1 },
{ 0xc351, 0x88 },
{ 0xc030, 0x14 },
{ 0xc331, 0xf2 },
{ 0xc551, 0x0f },
{ 0xc552, 0xff },
{ 0xc651, 0xc0 },
{ 0xc550, 0xd0 },
{ 0xc612, 0x00 },
{ 0xc622, 0x00 },
{ 0xc632, 0x00 },
{ 0xc642, 0x00 },
{ 0xc602, 0xf0 },
{ 0xc600, 0xd0 },
{ 0xcc02, 0x78 },
{ 0xcc00, 0x90 },
{ 0xc300, 0x3f },
{ 0xc301, 0x1d },
{ 0xc10b, 0x2e },
{ 0xc10c, 0x36 },
{ 0xd5a5, 0x00 },
{ 0xd5a6, 0x6a },
{ 0xd5a7, 0xaa },
{ 0xd5a8, 0xaa },
{ 0xd5aa, 0x00 },
{ 0xd5ab, 0x16 },
{ 0xd5ac, 0xdb },
{ 0xd5ad, 0x6d },
{ 0xd545, 0x09 },
{ 0xd546, 0x30 },
{ 0xd547, 0xf0 },
{ 0xd548, 0xf0 },
{ 0xd500, 0x20 },
{ 0xc504, 0x3f },
{ 0xc540, 0x00 },
{ 0xc541, 0x0a },
{ 0xc542, 0x1a },
{ 0xc512, 0x00 },
{ 0xc520, 0x40 },
{ 0xc51b, 0x7f },
{ 0xc51d, 0x0f },
{ 0xc500, 0x40 },
{ 0xc502, 0xde },
{ 0xc507, 0x05 },
{ 0xc509, 0x05 },
{ 0xc510, 0x40 },
{ 0xc518, 0xc0 },
{ 0xc500, 0xc0 },
{ 0xda0c, 0x00 },
{ 0xda0d, 0x0b },
{ 0xda0e, 0x55 },
{ 0xda0f, 0x55 },
{ 0xda04, 0x00 },
{ 0xda05, 0x51 },
{ 0xda06, 0xeb },
{ 0xda07, 0x85 },
{ 0xca16, 0x0f },
{ 0xca17, 0x00 },
{ 0xda09, 0x5d },
{ 0xda0a, 0xc0 },
{ 0xda11, 0x26 },
{ 0xda12, 0x66 },
{ 0xda13, 0x66 },
{ 0xda14, 0x66 },
{ 0xda16, 0x79 },
{ 0xda17, 0x99 },
{ 0xda18, 0x99 },
{ 0xda19, 0x99 },
{ 0xca09, 0x00 },
{ 0xca0a, 0x07 },
{ 0xca0b, 0x89 },
{ 0xca0c, 0x61 },
{ 0xca0e, 0x00 },
{ 0xca0f, 0x03 },
{ 0xca10, 0xc4 },
{ 0xca11, 0xb0 },
{ 0xdab6, 0x00 },
{ 0xdab7, 0x01 },
{ 0xdab8, 0x00 },
{ 0xdab9, 0x00 },
{ 0xdaba, 0x00 },
{ 0xdabb, 0x00 },
{ 0xd017, 0x0e },
{ 0xca00, 0xcd },
{ 0xc022, 0x84 },
};
#define RT1017_MAX_REG_NUM 0x4108ffff
static const struct regmap_config rt1017_sdca_regmap = {
.reg_bits = 32,
.val_bits = 8,
.readable_reg = rt1017_sdca_readable_register,
.volatile_reg = rt1017_sdca_volatile_register,
.max_register = RT1017_MAX_REG_NUM,
.reg_defaults = rt1017_sdca_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(rt1017_sdca_reg_defaults),
.cache_type = REGCACHE_MAPLE,
.use_single_read = true,
.use_single_write = true,
};
static int rt1017_sdca_read_prop(struct sdw_slave *slave)
{
struct sdw_slave_prop *prop = &slave->prop;
int nval;
int i, j;
u32 bit;
unsigned long addr;
struct sdw_dpn_prop *dpn;
prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
prop->paging_support = true;
/* first we need to allocate memory for set bits in port lists
* port = 1 for AMP playback
* port = 2 for IV capture
*/
prop->source_ports = BIT(2); /* BITMAP: 00000100 */
prop->sink_ports = BIT(1); /* BITMAP: 00000010 */
nval = hweight32(prop->source_ports);
prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
sizeof(*prop->src_dpn_prop), GFP_KERNEL);
if (!prop->src_dpn_prop)
return -ENOMEM;
i = 0;
dpn = prop->src_dpn_prop;
addr = prop->source_ports;
for_each_set_bit(bit, &addr, 32) {
dpn[i].num = bit;
dpn[i].type = SDW_DPN_FULL;
dpn[i].simple_ch_prep_sm = true;
dpn[i].ch_prep_timeout = 10;
i++;
}
/* do this again for sink now */
nval = hweight32(prop->sink_ports);
prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
sizeof(*prop->sink_dpn_prop), GFP_KERNEL);
if (!prop->sink_dpn_prop)
return -ENOMEM;
j = 0;
dpn = prop->sink_dpn_prop;
addr = prop->sink_ports;
for_each_set_bit(bit, &addr, 32) {
dpn[j].num = bit;
dpn[j].type = SDW_DPN_FULL;
dpn[j].simple_ch_prep_sm = true;
dpn[j].ch_prep_timeout = 10;
j++;
}
/* set the timeout values */
prop->clk_stop_timeout = 64;
return 0;
}
static int rt1017_sdca_io_init(struct device *dev, struct sdw_slave *slave)
{
struct rt1017_sdca_priv *rt1017 = dev_get_drvdata(dev);
if (rt1017->hw_init)
return 0;
if (rt1017->first_hw_init) {
regcache_cache_only(rt1017->regmap, false);
regcache_cache_bypass(rt1017->regmap, true);
} else {
/*
* PM runtime is only enabled when a Slave reports as Attached
*/
/* set autosuspend parameters */
pm_runtime_set_autosuspend_delay(&slave->dev, 3000);
pm_runtime_use_autosuspend(&slave->dev);
/* update count of parent 'active' children */
pm_runtime_set_active(&slave->dev);
/* make sure the device does not suspend immediately */
pm_runtime_mark_last_busy(&slave->dev);
pm_runtime_enable(&slave->dev);
}
pm_runtime_get_noresume(&slave->dev);
/* sw reset */
regmap_write(rt1017->regmap, 0xc000, 0x02);
/* initial settings - blind write */
regmap_multi_reg_write(rt1017->regmap, rt1017_blind_write,
ARRAY_SIZE(rt1017_blind_write));
if (rt1017->first_hw_init) {
regcache_cache_bypass(rt1017->regmap, false);
regcache_mark_dirty(rt1017->regmap);
} else
rt1017->first_hw_init = true;
/* Mark Slave initialization complete */
rt1017->hw_init = true;
pm_runtime_mark_last_busy(&slave->dev);
pm_runtime_put_autosuspend(&slave->dev);
dev_dbg(&slave->dev, "hw_init complete\n");
return 0;
}
static int rt1017_sdca_update_status(struct sdw_slave *slave,
enum sdw_slave_status status)
{
struct rt1017_sdca_priv *rt1017 = dev_get_drvdata(&slave->dev);
if (status == SDW_SLAVE_UNATTACHED)
rt1017->hw_init = false;
/*
* Perform initialization only if slave status is present and
* hw_init flag is false
*/
if (rt1017->hw_init || status != SDW_SLAVE_ATTACHED)
return 0;
/* perform I/O transfers required for Slave initialization */
return rt1017_sdca_io_init(&slave->dev, slave);
}
static const char * const rt1017_rx_data_ch_select[] = {
"Bypass",
"CN1",
"CN2",
"CN3",
"CN4",
"(1+2)/2",
"(1+3)/2",
"(1+4)/2",
"(2+3)/2",
"(2+4)/2",
"(3+4)/2",
};
static SOC_ENUM_SINGLE_DECL(rt1017_rx_data_ch_enum,
SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_UDMPU21,
RT1017_SDCA_CTL_UDMPU_CLUSTER, 0),
0, rt1017_rx_data_ch_select);
static const struct snd_kcontrol_new rt1017_sdca_controls[] = {
/* UDMPU Cluster Selection */
SOC_ENUM("RX Channel Select", rt1017_rx_data_ch_enum),
};
static const struct snd_kcontrol_new rt1017_sto_dac =
SOC_DAPM_SINGLE("Switch",
SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_FU, RT1017_SDCA_CTL_FU_MUTE, 0x1),
0, 1, 1);
static int rt1017_sdca_pde23_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt1017_sdca_priv *rt1017 = snd_soc_component_get_drvdata(component);
unsigned char ps0 = 0x0, ps3 = 0x3;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_write(rt1017->regmap,
SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_PDE23,
RT1017_SDCA_CTL_REQ_POWER_STATE, 0),
ps0);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_write(rt1017->regmap,
SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_PDE23,
RT1017_SDCA_CTL_REQ_POWER_STATE, 0),
ps3);
break;
default:
break;
}
return 0;
}
static int rt1017_sdca_classd_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt1017_sdca_priv *rt1017 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_update_bits(rt1017->regmap, RT1017_PWM_TRIM_1,
RT1017_PWM_FREQ_CTL_SRC_SEL_MASK, RT1017_PWM_FREQ_CTL_SRC_SEL_REG);
regmap_write(rt1017->regmap, RT1017_CLASSD_INT_1, 0x10);
break;
default:
break;
}
return 0;
}
static int rt1017_sdca_feedback_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt1017_sdca_priv *rt1017 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
regmap_update_bits(rt1017->regmap, 0xd017, 0x1f, 0x08);
break;
case SND_SOC_DAPM_POST_PMD:
regmap_update_bits(rt1017->regmap, 0xd017, 0x1f, 0x09);
break;
default:
break;
}
return 0;
}
static const struct snd_soc_dapm_widget rt1017_sdca_dapm_widgets[] = {
/* Audio Interface */
SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT_E("DP2TX", "DP2 Capture", 0, SND_SOC_NOPM, 0, 0,
rt1017_sdca_feedback_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
/* Digital Interface */
SND_SOC_DAPM_SWITCH("DAC", SND_SOC_NOPM, 0, 0, &rt1017_sto_dac),
/* Output Lines */
SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
rt1017_sdca_classd_event, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_OUTPUT("SPO"),
SND_SOC_DAPM_SUPPLY("PDE23", SND_SOC_NOPM, 0, 0,
rt1017_sdca_pde23_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA("I Sense", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("V Sense", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SIGGEN("I Gen"),
SND_SOC_DAPM_SIGGEN("V Gen"),
};
static const struct snd_soc_dapm_route rt1017_sdca_dapm_routes[] = {
{ "DAC", "Switch", "DP1RX" },
{ "CLASS D", NULL, "DAC" },
{ "CLASS D", NULL, "PDE23" },
{ "SPO", NULL, "CLASS D" },
{ "I Sense", NULL, "I Gen" },
{ "V Sense", NULL, "V Gen" },
{ "I Sense", NULL, "PDE23" },
{ "V Sense", NULL, "PDE23" },
{ "DP2TX", NULL, "I Sense" },
{ "DP2TX", NULL, "V Sense" },
};
static struct sdw_slave_ops rt1017_sdca_slave_ops = {
.read_prop = rt1017_sdca_read_prop,
.update_status = rt1017_sdca_update_status,
};
static int rt1017_sdca_component_probe(struct snd_soc_component *component)
{
int ret;
ret = pm_runtime_resume(component->dev);
if (ret < 0 && ret != -EACCES)
return ret;
return 0;
}
static void rt1017_sdca_component_remove(struct snd_soc_component *component)
{
struct rt1017_sdca_priv *rt1017 = snd_soc_component_get_drvdata(component);
regcache_cache_only(rt1017->regmap, true);
}
static const struct snd_soc_component_driver soc_sdca_component_rt1017 = {
.probe = rt1017_sdca_component_probe,
.remove = rt1017_sdca_component_remove,
.controls = rt1017_sdca_controls,
.num_controls = ARRAY_SIZE(rt1017_sdca_controls),
.dapm_widgets = rt1017_sdca_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt1017_sdca_dapm_widgets),
.dapm_routes = rt1017_sdca_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(rt1017_sdca_dapm_routes),
.endianness = 1,
};
static int rt1017_sdca_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
int direction)
{
snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
return 0;
}
static void rt1017_sdca_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
snd_soc_dai_set_dma_data(dai, substream, NULL);
}
static int rt1017_sdca_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt1017_sdca_priv *rt1017 = snd_soc_component_get_drvdata(component);
struct sdw_stream_config stream_config;
struct sdw_port_config port_config;
enum sdw_data_direction direction;
struct sdw_stream_runtime *sdw_stream;
int retval, port, num_channels, ch_mask;
unsigned int sampling_rate;
dev_dbg(dai->dev, "%s %s", __func__, dai->name);
sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
if (!sdw_stream)
return -EINVAL;
if (!rt1017->sdw_slave)
return -EINVAL;
/* SoundWire specific configuration */
/* port 1 for playback */
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
direction = SDW_DATA_DIR_RX;
port = 1;
} else {
direction = SDW_DATA_DIR_TX;
port = 2;
}
num_channels = params_channels(params);
ch_mask = (1 << num_channels) - 1;
stream_config.frame_rate = params_rate(params);
stream_config.ch_count = num_channels;
stream_config.bps = snd_pcm_format_width(params_format(params));
stream_config.direction = direction;
port_config.ch_mask = ch_mask;
port_config.num = port;
dev_dbg(dai->dev, "frame_rate %d, ch_count %d, bps %d, direction %d, ch_mask %d, port: %d\n",
params_rate(params), num_channels, snd_pcm_format_width(params_format(params)),
direction, ch_mask, port);
retval = sdw_stream_add_slave(rt1017->sdw_slave, &stream_config,
&port_config, 1, sdw_stream);
if (retval) {
dev_err(dai->dev, "Unable to configure port\n");
return retval;
}
/* sampling rate configuration */
switch (params_rate(params)) {
case 44100:
sampling_rate = RT1017_SDCA_RATE_44100HZ;
break;
case 48000:
sampling_rate = RT1017_SDCA_RATE_48000HZ;
break;
case 96000:
sampling_rate = RT1017_SDCA_RATE_96000HZ;
break;
case 192000:
sampling_rate = RT1017_SDCA_RATE_192000HZ;
break;
default:
dev_err(component->dev, "Rate %d is not supported\n",
params_rate(params));
return -EINVAL;
}
/* set sampling frequency */
regmap_write(rt1017->regmap,
SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_CS21,
RT1017_SDCA_CTL_FS_INDEX, 0),
sampling_rate);
return 0;
}
static int rt1017_sdca_pcm_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt1017_sdca_priv *rt1017 = snd_soc_component_get_drvdata(component);
struct sdw_stream_runtime *sdw_stream =
snd_soc_dai_get_dma_data(dai, substream);
if (!rt1017->sdw_slave)
return -EINVAL;
sdw_stream_remove_slave(rt1017->sdw_slave, sdw_stream);
return 0;
}
static const struct snd_soc_dai_ops rt1017_sdca_ops = {
.hw_params = rt1017_sdca_pcm_hw_params,
.hw_free = rt1017_sdca_pcm_hw_free,
.set_stream = rt1017_sdca_set_sdw_stream,
.shutdown = rt1017_sdca_shutdown,
};
#define RT1017_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
#define RT1017_FORMATS (SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE)
static struct snd_soc_dai_driver rt1017_sdca_dai[] = {
{
.name = "rt1017-aif",
.playback = {
.stream_name = "DP1 Playback",
.channels_min = 1,
.channels_max = 1,
.rates = RT1017_STEREO_RATES,
.formats = RT1017_FORMATS,
},
.capture = {
.stream_name = "DP2 Capture",
.channels_min = 1,
.channels_max = 1,
.rates = RT1017_STEREO_RATES,
.formats = RT1017_FORMATS,
},
.ops = &rt1017_sdca_ops,
},
};
static int rt1017_sdca_init(struct device *dev, struct regmap *regmap,
struct sdw_slave *slave)
{
struct rt1017_sdca_priv *rt1017;
int ret;
rt1017 = devm_kzalloc(dev, sizeof(*rt1017), GFP_KERNEL);
if (!rt1017)
return -ENOMEM;
dev_set_drvdata(dev, rt1017);
rt1017->sdw_slave = slave;
rt1017->regmap = regmap;
/*
* Mark hw_init to false
* HW init will be performed when device reports present
*/
rt1017->hw_init = false;
rt1017->first_hw_init = false;
ret = devm_snd_soc_register_component(dev,
&soc_sdca_component_rt1017,
rt1017_sdca_dai,
ARRAY_SIZE(rt1017_sdca_dai));
return ret;
}
static int rt1017_sdca_sdw_probe(struct sdw_slave *slave,
const struct sdw_device_id *id)
{
struct regmap *regmap;
/* Regmap Initialization */
regmap = devm_regmap_init_sdw(slave, &rt1017_sdca_regmap);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return rt1017_sdca_init(&slave->dev, regmap, slave);
}
static int rt1017_sdca_sdw_remove(struct sdw_slave *slave)
{
struct rt1017_sdca_priv *rt1017 = dev_get_drvdata(&slave->dev);
if (rt1017->first_hw_init)
pm_runtime_disable(&slave->dev);
return 0;
}
static const struct sdw_device_id rt1017_sdca_id[] = {
SDW_SLAVE_ENTRY_EXT(0x025d, 0x1017, 0x3, 0x1, 0),
{},
};
MODULE_DEVICE_TABLE(sdw, rt1017_sdca_id);
static int __maybe_unused rt1017_sdca_dev_suspend(struct device *dev)
{
struct rt1017_sdca_priv *rt1017 = dev_get_drvdata(dev);
if (!rt1017->hw_init)
return 0;
regcache_cache_only(rt1017->regmap, true);
return 0;
}
#define RT1017_PROBE_TIMEOUT 5000
static int __maybe_unused rt1017_sdca_dev_resume(struct device *dev)
{
struct sdw_slave *slave = dev_to_sdw_dev(dev);
struct rt1017_sdca_priv *rt1017 = dev_get_drvdata(dev);
unsigned long time;
if (!rt1017->first_hw_init)
return 0;
if (!slave->unattach_request)
goto regmap_sync;
time = wait_for_completion_timeout(&slave->initialization_complete,
msecs_to_jiffies(RT1017_PROBE_TIMEOUT));
if (!time) {
dev_err(&slave->dev, "Initialization not complete, timed out\n");
sdw_show_ping_status(slave->bus, true);
return -ETIMEDOUT;
}
regmap_sync:
slave->unattach_request = 0;
regcache_cache_only(rt1017->regmap, false);
regcache_sync(rt1017->regmap);
return 0;
}
static const struct dev_pm_ops rt1017_sdca_pm = {
SET_SYSTEM_SLEEP_PM_OPS(rt1017_sdca_dev_suspend, rt1017_sdca_dev_resume)
SET_RUNTIME_PM_OPS(rt1017_sdca_dev_suspend, rt1017_sdca_dev_resume, NULL)
};
static struct sdw_driver rt1017_sdca_sdw_driver = {
.driver = {
.name = "rt1017-sdca",
.owner = THIS_MODULE,
.pm = &rt1017_sdca_pm,
},
.probe = rt1017_sdca_sdw_probe,
.remove = rt1017_sdca_sdw_remove,
.ops = &rt1017_sdca_slave_ops,
.id_table = rt1017_sdca_id,
};
module_sdw_driver(rt1017_sdca_sdw_driver);
MODULE_DESCRIPTION("ASoC RT1017 driver SDCA SDW");
MODULE_AUTHOR("Derek Fang <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/rt1017-sdca-sdw.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// rt711-sdw-sdca.c -- rt711 SDCA ALSA SoC audio driver
//
// Copyright(c) 2021 Realtek Semiconductor Corp.
//
//
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/mod_devicetable.h>
#include <linux/soundwire/sdw_registers.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include "rt711-sdca.h"
#include "rt711-sdca-sdw.h"
static bool rt711_sdca_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x201a ... 0x2027:
case 0x2029 ... 0x202a:
case 0x202d ... 0x2034:
case 0x2200 ... 0x2204:
case 0x2206 ... 0x2212:
case 0x2220 ... 0x2223:
case 0x2230 ... 0x2239:
case 0x2f01 ... 0x2f0f:
case 0x2f30 ... 0x2f36:
case 0x2f50 ... 0x2f5a:
case 0x2f60:
case 0x3200 ... 0x3212:
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_GE49, RT711_SDCA_CTL_SELECTED_MODE, 0):
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_GE49, RT711_SDCA_CTL_DETECTED_MODE, 0):
case SDW_SDCA_CTL(FUNC_NUM_HID, RT711_SDCA_ENT_HID01, RT711_SDCA_CTL_HIDTX_CURRENT_OWNER, 0) ...
SDW_SDCA_CTL(FUNC_NUM_HID, RT711_SDCA_ENT_HID01, RT711_SDCA_CTL_HIDTX_MESSAGE_LENGTH, 0):
case RT711_BUF_ADDR_HID1 ... RT711_BUF_ADDR_HID2:
return true;
default:
return false;
}
}
static bool rt711_sdca_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x201b:
case 0x201c:
case 0x201d:
case 0x201f:
case 0x2021:
case 0x2023:
case 0x2230:
case 0x202d ... 0x202f: /* BRA */
case 0x2200 ... 0x2212: /* i2c debug */
case RT711_RC_CAL_STATUS:
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_GE49, RT711_SDCA_CTL_DETECTED_MODE, 0):
case SDW_SDCA_CTL(FUNC_NUM_HID, RT711_SDCA_ENT_HID01, RT711_SDCA_CTL_HIDTX_CURRENT_OWNER, 0) ...
SDW_SDCA_CTL(FUNC_NUM_HID, RT711_SDCA_ENT_HID01, RT711_SDCA_CTL_HIDTX_MESSAGE_LENGTH, 0):
case RT711_BUF_ADDR_HID1 ... RT711_BUF_ADDR_HID2:
return true;
default:
return false;
}
}
static bool rt711_sdca_mbq_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x2000000 ... 0x20000ff:
case 0x5600000 ... 0x56000ff:
case 0x5700000 ... 0x57000ff:
case 0x5800000 ... 0x58000ff:
case 0x5900000 ... 0x59000ff:
case 0x5b00000 ... 0x5b000ff:
case 0x5f00000 ... 0x5f000ff:
case 0x6100000 ... 0x61000ff:
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_USER_FU05, RT711_SDCA_CTL_FU_VOLUME, CH_L):
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_USER_FU05, RT711_SDCA_CTL_FU_VOLUME, CH_R):
case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT711_SDCA_ENT_USER_FU1E, RT711_SDCA_CTL_FU_VOLUME, CH_L):
case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT711_SDCA_ENT_USER_FU1E, RT711_SDCA_CTL_FU_VOLUME, CH_R):
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_USER_FU0F, RT711_SDCA_CTL_FU_VOLUME, CH_L):
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_USER_FU0F, RT711_SDCA_CTL_FU_VOLUME, CH_R):
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_PLATFORM_FU44, RT711_SDCA_CTL_FU_CH_GAIN, CH_L):
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT711_SDCA_ENT_PLATFORM_FU44, RT711_SDCA_CTL_FU_CH_GAIN, CH_R):
case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT711_SDCA_ENT_PLATFORM_FU15, RT711_SDCA_CTL_FU_CH_GAIN, CH_L):
case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT711_SDCA_ENT_PLATFORM_FU15, RT711_SDCA_CTL_FU_CH_GAIN, CH_R):
return true;
default:
return false;
}
}
static bool rt711_sdca_mbq_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x2000000:
case 0x200001a:
case 0x2000046:
case 0x2000080:
case 0x2000081:
case 0x2000083:
case 0x5800000:
case 0x5800001:
case 0x5f00001:
case 0x6100008:
return true;
default:
return false;
}
}
static const struct regmap_config rt711_sdca_regmap = {
.reg_bits = 32,
.val_bits = 8,
.readable_reg = rt711_sdca_readable_register,
.volatile_reg = rt711_sdca_volatile_register,
.max_register = 0x44ffffff,
.reg_defaults = rt711_sdca_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(rt711_sdca_reg_defaults),
.cache_type = REGCACHE_MAPLE,
.use_single_read = true,
.use_single_write = true,
};
static const struct regmap_config rt711_sdca_mbq_regmap = {
.name = "sdw-mbq",
.reg_bits = 32,
.val_bits = 16,
.readable_reg = rt711_sdca_mbq_readable_register,
.volatile_reg = rt711_sdca_mbq_volatile_register,
.max_register = 0x40800f12,
.reg_defaults = rt711_sdca_mbq_defaults,
.num_reg_defaults = ARRAY_SIZE(rt711_sdca_mbq_defaults),
.cache_type = REGCACHE_MAPLE,
.use_single_read = true,
.use_single_write = true,
};
static int rt711_sdca_update_status(struct sdw_slave *slave,
enum sdw_slave_status status)
{
struct rt711_sdca_priv *rt711 = dev_get_drvdata(&slave->dev);
if (status == SDW_SLAVE_UNATTACHED)
rt711->hw_init = false;
if (status == SDW_SLAVE_ATTACHED) {
if (rt711->hs_jack) {
/*
* Due to the SCP_SDCA_INTMASK will be cleared by any reset, and then
* if the device attached again, we will need to set the setting back.
* It could avoid losing the jack detection interrupt.
* This also could sync with the cache value as the rt711_sdca_jack_init set.
*/
sdw_write_no_pm(rt711->slave, SDW_SCP_SDCA_INTMASK1,
SDW_SCP_SDCA_INTMASK_SDCA_0);
sdw_write_no_pm(rt711->slave, SDW_SCP_SDCA_INTMASK2,
SDW_SCP_SDCA_INTMASK_SDCA_8);
}
}
/*
* Perform initialization only if slave status is present and
* hw_init flag is false
*/
if (rt711->hw_init || status != SDW_SLAVE_ATTACHED)
return 0;
/* perform I/O transfers required for Slave initialization */
return rt711_sdca_io_init(&slave->dev, slave);
}
static int rt711_sdca_read_prop(struct sdw_slave *slave)
{
struct sdw_slave_prop *prop = &slave->prop;
int nval;
int i, j;
u32 bit;
unsigned long addr;
struct sdw_dpn_prop *dpn;
prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
prop->paging_support = true;
/* first we need to allocate memory for set bits in port lists */
prop->source_ports = 0x14; /* BITMAP: 00010100 */
prop->sink_ports = 0x8; /* BITMAP: 00001000 */
nval = hweight32(prop->source_ports);
prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
sizeof(*prop->src_dpn_prop), GFP_KERNEL);
if (!prop->src_dpn_prop)
return -ENOMEM;
i = 0;
dpn = prop->src_dpn_prop;
addr = prop->source_ports;
for_each_set_bit(bit, &addr, 32) {
dpn[i].num = bit;
dpn[i].type = SDW_DPN_FULL;
dpn[i].simple_ch_prep_sm = true;
dpn[i].ch_prep_timeout = 10;
i++;
}
/* do this again for sink now */
nval = hweight32(prop->sink_ports);
prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
sizeof(*prop->sink_dpn_prop), GFP_KERNEL);
if (!prop->sink_dpn_prop)
return -ENOMEM;
j = 0;
dpn = prop->sink_dpn_prop;
addr = prop->sink_ports;
for_each_set_bit(bit, &addr, 32) {
dpn[j].num = bit;
dpn[j].type = SDW_DPN_FULL;
dpn[j].simple_ch_prep_sm = true;
dpn[j].ch_prep_timeout = 10;
j++;
}
/* set the timeout values */
prop->clk_stop_timeout = 700;
/* wake-up event */
prop->wake_capable = 1;
return 0;
}
static int rt711_sdca_interrupt_callback(struct sdw_slave *slave,
struct sdw_slave_intr_status *status)
{
struct rt711_sdca_priv *rt711 = dev_get_drvdata(&slave->dev);
int ret, stat;
int count = 0, retry = 3;
unsigned int sdca_cascade, scp_sdca_stat1, scp_sdca_stat2 = 0;
dev_dbg(&slave->dev,
"%s control_port_stat=%x, sdca_cascade=%x", __func__,
status->control_port, status->sdca_cascade);
if (cancel_delayed_work_sync(&rt711->jack_detect_work)) {
dev_warn(&slave->dev, "%s the pending delayed_work was cancelled", __func__);
/* avoid the HID owner doesn't change to device */
if (rt711->scp_sdca_stat2)
scp_sdca_stat2 = rt711->scp_sdca_stat2;
}
/*
* The critical section below intentionally protects a rather large piece of code.
* We don't want to allow the system suspend to disable an interrupt while we are
* processing it, which could be problematic given the quirky SoundWire interrupt
* scheme. We do want however to prevent new workqueues from being scheduled if
* the disable_irq flag was set during system suspend.
*/
mutex_lock(&rt711->disable_irq_lock);
ret = sdw_read_no_pm(rt711->slave, SDW_SCP_SDCA_INT1);
if (ret < 0)
goto io_error;
rt711->scp_sdca_stat1 = ret;
ret = sdw_read_no_pm(rt711->slave, SDW_SCP_SDCA_INT2);
if (ret < 0)
goto io_error;
rt711->scp_sdca_stat2 = ret;
if (scp_sdca_stat2)
rt711->scp_sdca_stat2 |= scp_sdca_stat2;
do {
/* clear flag */
ret = sdw_read_no_pm(rt711->slave, SDW_SCP_SDCA_INT1);
if (ret < 0)
goto io_error;
if (ret & SDW_SCP_SDCA_INTMASK_SDCA_0) {
ret = sdw_write_no_pm(rt711->slave, SDW_SCP_SDCA_INT1,
SDW_SCP_SDCA_INTMASK_SDCA_0);
if (ret < 0)
goto io_error;
}
ret = sdw_read_no_pm(rt711->slave, SDW_SCP_SDCA_INT2);
if (ret < 0)
goto io_error;
if (ret & SDW_SCP_SDCA_INTMASK_SDCA_8) {
ret = sdw_write_no_pm(rt711->slave, SDW_SCP_SDCA_INT2,
SDW_SCP_SDCA_INTMASK_SDCA_8);
if (ret < 0)
goto io_error;
}
/* check if flag clear or not */
ret = sdw_read_no_pm(rt711->slave, SDW_DP0_INT);
if (ret < 0)
goto io_error;
sdca_cascade = ret & SDW_DP0_SDCA_CASCADE;
ret = sdw_read_no_pm(rt711->slave, SDW_SCP_SDCA_INT1);
if (ret < 0)
goto io_error;
scp_sdca_stat1 = ret & SDW_SCP_SDCA_INTMASK_SDCA_0;
ret = sdw_read_no_pm(rt711->slave, SDW_SCP_SDCA_INT2);
if (ret < 0)
goto io_error;
scp_sdca_stat2 = ret & SDW_SCP_SDCA_INTMASK_SDCA_8;
stat = scp_sdca_stat1 || scp_sdca_stat2 || sdca_cascade;
count++;
} while (stat != 0 && count < retry);
if (stat)
dev_warn(&slave->dev,
"%s scp_sdca_stat1=0x%x, scp_sdca_stat2=0x%x\n", __func__,
rt711->scp_sdca_stat1, rt711->scp_sdca_stat2);
if (status->sdca_cascade && !rt711->disable_irq)
mod_delayed_work(system_power_efficient_wq,
&rt711->jack_detect_work, msecs_to_jiffies(30));
mutex_unlock(&rt711->disable_irq_lock);
return 0;
io_error:
mutex_unlock(&rt711->disable_irq_lock);
pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret);
return ret;
}
static const struct sdw_slave_ops rt711_sdca_slave_ops = {
.read_prop = rt711_sdca_read_prop,
.interrupt_callback = rt711_sdca_interrupt_callback,
.update_status = rt711_sdca_update_status,
};
static int rt711_sdca_sdw_probe(struct sdw_slave *slave,
const struct sdw_device_id *id)
{
struct regmap *regmap, *mbq_regmap;
/* Regmap Initialization */
mbq_regmap = devm_regmap_init_sdw_mbq(slave, &rt711_sdca_mbq_regmap);
if (IS_ERR(mbq_regmap))
return PTR_ERR(mbq_regmap);
regmap = devm_regmap_init_sdw(slave, &rt711_sdca_regmap);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return rt711_sdca_init(&slave->dev, regmap, mbq_regmap, slave);
}
static int rt711_sdca_sdw_remove(struct sdw_slave *slave)
{
struct rt711_sdca_priv *rt711 = dev_get_drvdata(&slave->dev);
if (rt711->hw_init) {
cancel_delayed_work_sync(&rt711->jack_detect_work);
cancel_delayed_work_sync(&rt711->jack_btn_check_work);
}
pm_runtime_disable(&slave->dev);
mutex_destroy(&rt711->calibrate_mutex);
mutex_destroy(&rt711->disable_irq_lock);
return 0;
}
static const struct sdw_device_id rt711_sdca_id[] = {
SDW_SLAVE_ENTRY_EXT(0x025d, 0x711, 0x3, 0x1, 0),
{},
};
MODULE_DEVICE_TABLE(sdw, rt711_sdca_id);
static int __maybe_unused rt711_sdca_dev_suspend(struct device *dev)
{
struct rt711_sdca_priv *rt711 = dev_get_drvdata(dev);
if (!rt711->hw_init)
return 0;
cancel_delayed_work_sync(&rt711->jack_detect_work);
cancel_delayed_work_sync(&rt711->jack_btn_check_work);
regcache_cache_only(rt711->regmap, true);
regcache_cache_only(rt711->mbq_regmap, true);
return 0;
}
static int __maybe_unused rt711_sdca_dev_system_suspend(struct device *dev)
{
struct rt711_sdca_priv *rt711_sdca = dev_get_drvdata(dev);
struct sdw_slave *slave = dev_to_sdw_dev(dev);
int ret1, ret2;
if (!rt711_sdca->hw_init)
return 0;
/*
* prevent new interrupts from being handled after the
* deferred work completes and before the parent disables
* interrupts on the link
*/
mutex_lock(&rt711_sdca->disable_irq_lock);
rt711_sdca->disable_irq = true;
ret1 = sdw_update_no_pm(slave, SDW_SCP_SDCA_INTMASK1,
SDW_SCP_SDCA_INTMASK_SDCA_0, 0);
ret2 = sdw_update_no_pm(slave, SDW_SCP_SDCA_INTMASK2,
SDW_SCP_SDCA_INTMASK_SDCA_8, 0);
mutex_unlock(&rt711_sdca->disable_irq_lock);
if (ret1 < 0 || ret2 < 0) {
/* log but don't prevent suspend from happening */
dev_dbg(&slave->dev, "%s: could not disable SDCA interrupts\n:", __func__);
}
return rt711_sdca_dev_suspend(dev);
}
#define RT711_PROBE_TIMEOUT 5000
static int __maybe_unused rt711_sdca_dev_resume(struct device *dev)
{
struct sdw_slave *slave = dev_to_sdw_dev(dev);
struct rt711_sdca_priv *rt711 = dev_get_drvdata(dev);
unsigned long time;
if (!rt711->first_hw_init)
return 0;
if (!slave->unattach_request) {
if (rt711->disable_irq == true) {
mutex_lock(&rt711->disable_irq_lock);
sdw_write_no_pm(slave, SDW_SCP_SDCA_INTMASK1, SDW_SCP_SDCA_INTMASK_SDCA_0);
sdw_write_no_pm(slave, SDW_SCP_SDCA_INTMASK2, SDW_SCP_SDCA_INTMASK_SDCA_8);
rt711->disable_irq = false;
mutex_unlock(&rt711->disable_irq_lock);
}
goto regmap_sync;
}
time = wait_for_completion_timeout(&slave->initialization_complete,
msecs_to_jiffies(RT711_PROBE_TIMEOUT));
if (!time) {
dev_err(&slave->dev, "Initialization not complete, timed out\n");
sdw_show_ping_status(slave->bus, true);
return -ETIMEDOUT;
}
regmap_sync:
slave->unattach_request = 0;
regcache_cache_only(rt711->regmap, false);
regcache_sync(rt711->regmap);
regcache_cache_only(rt711->mbq_regmap, false);
regcache_sync(rt711->mbq_regmap);
return 0;
}
static const struct dev_pm_ops rt711_sdca_pm = {
SET_SYSTEM_SLEEP_PM_OPS(rt711_sdca_dev_system_suspend, rt711_sdca_dev_resume)
SET_RUNTIME_PM_OPS(rt711_sdca_dev_suspend, rt711_sdca_dev_resume, NULL)
};
static struct sdw_driver rt711_sdca_sdw_driver = {
.driver = {
.name = "rt711-sdca",
.owner = THIS_MODULE,
.pm = &rt711_sdca_pm,
},
.probe = rt711_sdca_sdw_probe,
.remove = rt711_sdca_sdw_remove,
.ops = &rt711_sdca_slave_ops,
.id_table = rt711_sdca_id,
};
module_sdw_driver(rt711_sdca_sdw_driver);
MODULE_DESCRIPTION("ASoC RT711 SDCA SDW driver");
MODULE_AUTHOR("Shuming Fan <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/rt711-sdca-sdw.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* linux/sound/soc/codecs/tlv320aic32x4.c
*
* Copyright 2011 Vista Silicon S.L.
*
* Author: Javier Martin <[email protected]>
*
* Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/gpio.h>
#include <linux/of_gpio.h>
#include <linux/cdev.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/of_clk.h>
#include <linux/regulator/consumer.h>
#include <sound/tlv320aic32x4.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "tlv320aic32x4.h"
struct aic32x4_priv {
struct regmap *regmap;
u32 power_cfg;
u32 micpga_routing;
bool swapdacs;
int rstn_gpio;
const char *mclk_name;
struct regulator *supply_ldo;
struct regulator *supply_iov;
struct regulator *supply_dv;
struct regulator *supply_av;
struct aic32x4_setup_data *setup;
struct device *dev;
enum aic32x4_type type;
unsigned int fmt;
};
static int aic32x4_reset_adc(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
u32 adc_reg;
/*
* Workaround: the datasheet does not mention a required programming
* sequence but experiments show the ADC needs to be reset after each
* capture to avoid audible artifacts.
*/
switch (event) {
case SND_SOC_DAPM_POST_PMD:
adc_reg = snd_soc_component_read(component, AIC32X4_ADCSETUP);
snd_soc_component_write(component, AIC32X4_ADCSETUP, adc_reg |
AIC32X4_LADC_EN | AIC32X4_RADC_EN);
snd_soc_component_write(component, AIC32X4_ADCSETUP, adc_reg);
break;
}
return 0;
};
static int mic_bias_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
/* Change Mic Bias Registor */
snd_soc_component_update_bits(component, AIC32X4_MICBIAS,
AIC32x4_MICBIAS_MASK,
AIC32X4_MICBIAS_LDOIN |
AIC32X4_MICBIAS_2075V);
printk(KERN_DEBUG "%s: Mic Bias will be turned ON\n", __func__);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, AIC32X4_MICBIAS,
AIC32x4_MICBIAS_MASK, 0);
printk(KERN_DEBUG "%s: Mic Bias will be turned OFF\n",
__func__);
break;
}
return 0;
}
static int aic32x4_get_mfp1_gpio(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
u8 val;
val = snd_soc_component_read(component, AIC32X4_DINCTL);
ucontrol->value.integer.value[0] = (val & 0x01);
return 0;
};
static int aic32x4_set_mfp2_gpio(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
u8 val;
u8 gpio_check;
val = snd_soc_component_read(component, AIC32X4_DOUTCTL);
gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED);
if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) {
printk(KERN_ERR "%s: MFP2 is not configure as a GPIO output\n",
__func__);
return -EINVAL;
}
if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP2_GPIO_OUT_HIGH))
return 0;
if (ucontrol->value.integer.value[0])
val |= ucontrol->value.integer.value[0];
else
val &= ~AIC32X4_MFP2_GPIO_OUT_HIGH;
snd_soc_component_write(component, AIC32X4_DOUTCTL, val);
return 0;
};
static int aic32x4_get_mfp3_gpio(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
u8 val;
val = snd_soc_component_read(component, AIC32X4_SCLKCTL);
ucontrol->value.integer.value[0] = (val & 0x01);
return 0;
};
static int aic32x4_set_mfp4_gpio(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
u8 val;
u8 gpio_check;
val = snd_soc_component_read(component, AIC32X4_MISOCTL);
gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED);
if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) {
printk(KERN_ERR "%s: MFP4 is not configure as a GPIO output\n",
__func__);
return -EINVAL;
}
if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP5_GPIO_OUT_HIGH))
return 0;
if (ucontrol->value.integer.value[0])
val |= ucontrol->value.integer.value[0];
else
val &= ~AIC32X4_MFP5_GPIO_OUT_HIGH;
snd_soc_component_write(component, AIC32X4_MISOCTL, val);
return 0;
};
static int aic32x4_get_mfp5_gpio(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
u8 val;
val = snd_soc_component_read(component, AIC32X4_GPIOCTL);
ucontrol->value.integer.value[0] = ((val & 0x2) >> 1);
return 0;
};
static int aic32x4_set_mfp5_gpio(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
u8 val;
u8 gpio_check;
val = snd_soc_component_read(component, AIC32X4_GPIOCTL);
gpio_check = (val & AIC32X4_MFP5_GPIO_OUTPUT);
if (gpio_check != AIC32X4_MFP5_GPIO_OUTPUT) {
printk(KERN_ERR "%s: MFP5 is not configure as a GPIO output\n",
__func__);
return -EINVAL;
}
if (ucontrol->value.integer.value[0] == (val & 0x1))
return 0;
if (ucontrol->value.integer.value[0])
val |= ucontrol->value.integer.value[0];
else
val &= 0xfe;
snd_soc_component_write(component, AIC32X4_GPIOCTL, val);
return 0;
};
static const struct snd_kcontrol_new aic32x4_mfp1[] = {
SOC_SINGLE_BOOL_EXT("MFP1 GPIO", 0, aic32x4_get_mfp1_gpio, NULL),
};
static const struct snd_kcontrol_new aic32x4_mfp2[] = {
SOC_SINGLE_BOOL_EXT("MFP2 GPIO", 0, NULL, aic32x4_set_mfp2_gpio),
};
static const struct snd_kcontrol_new aic32x4_mfp3[] = {
SOC_SINGLE_BOOL_EXT("MFP3 GPIO", 0, aic32x4_get_mfp3_gpio, NULL),
};
static const struct snd_kcontrol_new aic32x4_mfp4[] = {
SOC_SINGLE_BOOL_EXT("MFP4 GPIO", 0, NULL, aic32x4_set_mfp4_gpio),
};
static const struct snd_kcontrol_new aic32x4_mfp5[] = {
SOC_SINGLE_BOOL_EXT("MFP5 GPIO", 0, aic32x4_get_mfp5_gpio,
aic32x4_set_mfp5_gpio),
};
/* 0dB min, 0.5dB steps */
static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0);
/* -63.5dB min, 0.5dB steps */
static DECLARE_TLV_DB_SCALE(tlv_pcm, -6350, 50, 0);
/* -6dB min, 1dB steps */
static DECLARE_TLV_DB_SCALE(tlv_driver_gain, -600, 100, 0);
/* -12dB min, 0.5dB steps */
static DECLARE_TLV_DB_SCALE(tlv_adc_vol, -1200, 50, 0);
/* -6dB min, 1dB steps */
static DECLARE_TLV_DB_SCALE(tlv_tas_driver_gain, -5850, 50, 0);
static DECLARE_TLV_DB_SCALE(tlv_amp_vol, 0, 600, 1);
static const char * const lo_cm_text[] = {
"Full Chip", "1.65V",
};
static SOC_ENUM_SINGLE_DECL(lo_cm_enum, AIC32X4_CMMODE, 3, lo_cm_text);
static const char * const ptm_text[] = {
"P3", "P2", "P1",
};
static SOC_ENUM_SINGLE_DECL(l_ptm_enum, AIC32X4_LPLAYBACK, 2, ptm_text);
static SOC_ENUM_SINGLE_DECL(r_ptm_enum, AIC32X4_RPLAYBACK, 2, ptm_text);
static const struct snd_kcontrol_new aic32x4_snd_controls[] = {
SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL,
AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm),
SOC_ENUM("DAC Left Playback PowerTune Switch", l_ptm_enum),
SOC_ENUM("DAC Right Playback PowerTune Switch", r_ptm_enum),
SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN,
AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0,
tlv_driver_gain),
SOC_DOUBLE_R_S_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN,
AIC32X4_LORGAIN, 0, -0x6, 0x1d, 5, 0,
tlv_driver_gain),
SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN,
AIC32X4_HPRGAIN, 6, 0x01, 1),
SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN,
AIC32X4_LORGAIN, 6, 0x01, 1),
SOC_ENUM("LO Playback Common Mode Switch", lo_cm_enum),
SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL,
AIC32X4_RMICPGAVOL, 7, 0x01, 1),
SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0),
SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0),
SOC_DOUBLE_R_S_TLV("ADC Level Volume", AIC32X4_LADCVOL,
AIC32X4_RADCVOL, 0, -0x18, 0x28, 6, 0, tlv_adc_vol),
SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL,
AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5),
SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0),
SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0),
SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1,
4, 0x07, 0),
SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1,
0, 0x03, 0),
SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2,
6, 0x03, 0),
SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2,
1, 0x1F, 0),
SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3,
0, 0x7F, 0),
SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4,
3, 0x1F, 0),
SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5,
3, 0x1F, 0),
SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6,
0, 0x1F, 0),
SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7,
0, 0x0F, 0),
};
static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0),
};
static const struct snd_kcontrol_new hpr_output_mixer_controls[] = {
SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0),
SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0),
};
static const struct snd_kcontrol_new lol_output_mixer_controls[] = {
SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0),
};
static const struct snd_kcontrol_new lor_output_mixer_controls[] = {
SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0),
};
static const char * const resistor_text[] = {
"Off", "10 kOhm", "20 kOhm", "40 kOhm",
};
/* Left mixer pins */
static SOC_ENUM_SINGLE_DECL(in1l_lpga_p_enum, AIC32X4_LMICPGAPIN, 6, resistor_text);
static SOC_ENUM_SINGLE_DECL(in2l_lpga_p_enum, AIC32X4_LMICPGAPIN, 4, resistor_text);
static SOC_ENUM_SINGLE_DECL(in3l_lpga_p_enum, AIC32X4_LMICPGAPIN, 2, resistor_text);
static SOC_ENUM_SINGLE_DECL(in1r_lpga_p_enum, AIC32X4_LMICPGAPIN, 0, resistor_text);
static SOC_ENUM_SINGLE_DECL(cml_lpga_n_enum, AIC32X4_LMICPGANIN, 6, resistor_text);
static SOC_ENUM_SINGLE_DECL(in2r_lpga_n_enum, AIC32X4_LMICPGANIN, 4, resistor_text);
static SOC_ENUM_SINGLE_DECL(in3r_lpga_n_enum, AIC32X4_LMICPGANIN, 2, resistor_text);
static const struct snd_kcontrol_new in1l_to_lmixer_controls[] = {
SOC_DAPM_ENUM("IN1_L L+ Switch", in1l_lpga_p_enum),
};
static const struct snd_kcontrol_new in2l_to_lmixer_controls[] = {
SOC_DAPM_ENUM("IN2_L L+ Switch", in2l_lpga_p_enum),
};
static const struct snd_kcontrol_new in3l_to_lmixer_controls[] = {
SOC_DAPM_ENUM("IN3_L L+ Switch", in3l_lpga_p_enum),
};
static const struct snd_kcontrol_new in1r_to_lmixer_controls[] = {
SOC_DAPM_ENUM("IN1_R L+ Switch", in1r_lpga_p_enum),
};
static const struct snd_kcontrol_new cml_to_lmixer_controls[] = {
SOC_DAPM_ENUM("CM_L L- Switch", cml_lpga_n_enum),
};
static const struct snd_kcontrol_new in2r_to_lmixer_controls[] = {
SOC_DAPM_ENUM("IN2_R L- Switch", in2r_lpga_n_enum),
};
static const struct snd_kcontrol_new in3r_to_lmixer_controls[] = {
SOC_DAPM_ENUM("IN3_R L- Switch", in3r_lpga_n_enum),
};
/* Right mixer pins */
static SOC_ENUM_SINGLE_DECL(in1r_rpga_p_enum, AIC32X4_RMICPGAPIN, 6, resistor_text);
static SOC_ENUM_SINGLE_DECL(in2r_rpga_p_enum, AIC32X4_RMICPGAPIN, 4, resistor_text);
static SOC_ENUM_SINGLE_DECL(in3r_rpga_p_enum, AIC32X4_RMICPGAPIN, 2, resistor_text);
static SOC_ENUM_SINGLE_DECL(in2l_rpga_p_enum, AIC32X4_RMICPGAPIN, 0, resistor_text);
static SOC_ENUM_SINGLE_DECL(cmr_rpga_n_enum, AIC32X4_RMICPGANIN, 6, resistor_text);
static SOC_ENUM_SINGLE_DECL(in1l_rpga_n_enum, AIC32X4_RMICPGANIN, 4, resistor_text);
static SOC_ENUM_SINGLE_DECL(in3l_rpga_n_enum, AIC32X4_RMICPGANIN, 2, resistor_text);
static const struct snd_kcontrol_new in1r_to_rmixer_controls[] = {
SOC_DAPM_ENUM("IN1_R R+ Switch", in1r_rpga_p_enum),
};
static const struct snd_kcontrol_new in2r_to_rmixer_controls[] = {
SOC_DAPM_ENUM("IN2_R R+ Switch", in2r_rpga_p_enum),
};
static const struct snd_kcontrol_new in3r_to_rmixer_controls[] = {
SOC_DAPM_ENUM("IN3_R R+ Switch", in3r_rpga_p_enum),
};
static const struct snd_kcontrol_new in2l_to_rmixer_controls[] = {
SOC_DAPM_ENUM("IN2_L R+ Switch", in2l_rpga_p_enum),
};
static const struct snd_kcontrol_new cmr_to_rmixer_controls[] = {
SOC_DAPM_ENUM("CM_R R- Switch", cmr_rpga_n_enum),
};
static const struct snd_kcontrol_new in1l_to_rmixer_controls[] = {
SOC_DAPM_ENUM("IN1_L R- Switch", in1l_rpga_n_enum),
};
static const struct snd_kcontrol_new in3l_to_rmixer_controls[] = {
SOC_DAPM_ENUM("IN3_L R- Switch", in3l_rpga_n_enum),
};
static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = {
SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0),
SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0,
&hpl_output_mixer_controls[0],
ARRAY_SIZE(hpl_output_mixer_controls)),
SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),
SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0,
&lol_output_mixer_controls[0],
ARRAY_SIZE(lol_output_mixer_controls)),
SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0),
SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0),
SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0,
&hpr_output_mixer_controls[0],
ARRAY_SIZE(hpr_output_mixer_controls)),
SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0),
SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0,
&lor_output_mixer_controls[0],
ARRAY_SIZE(lor_output_mixer_controls)),
SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0),
SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0),
SND_SOC_DAPM_MUX("IN1_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
in1r_to_rmixer_controls),
SND_SOC_DAPM_MUX("IN2_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
in2r_to_rmixer_controls),
SND_SOC_DAPM_MUX("IN3_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
in3r_to_rmixer_controls),
SND_SOC_DAPM_MUX("IN2_L to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
in2l_to_rmixer_controls),
SND_SOC_DAPM_MUX("CM_R to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
cmr_to_rmixer_controls),
SND_SOC_DAPM_MUX("IN1_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
in1l_to_rmixer_controls),
SND_SOC_DAPM_MUX("IN3_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
in3l_to_rmixer_controls),
SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0),
SND_SOC_DAPM_MUX("IN1_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
in1l_to_lmixer_controls),
SND_SOC_DAPM_MUX("IN2_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
in2l_to_lmixer_controls),
SND_SOC_DAPM_MUX("IN3_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
in3l_to_lmixer_controls),
SND_SOC_DAPM_MUX("IN1_R to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
in1r_to_lmixer_controls),
SND_SOC_DAPM_MUX("CM_L to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
cml_to_lmixer_controls),
SND_SOC_DAPM_MUX("IN2_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
in2r_to_lmixer_controls),
SND_SOC_DAPM_MUX("IN3_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
in3r_to_lmixer_controls),
SND_SOC_DAPM_SUPPLY("Mic Bias", AIC32X4_MICBIAS, 6, 0, mic_bias_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_POST("ADC Reset", aic32x4_reset_adc),
SND_SOC_DAPM_OUTPUT("HPL"),
SND_SOC_DAPM_OUTPUT("HPR"),
SND_SOC_DAPM_OUTPUT("LOL"),
SND_SOC_DAPM_OUTPUT("LOR"),
SND_SOC_DAPM_INPUT("IN1_L"),
SND_SOC_DAPM_INPUT("IN1_R"),
SND_SOC_DAPM_INPUT("IN2_L"),
SND_SOC_DAPM_INPUT("IN2_R"),
SND_SOC_DAPM_INPUT("IN3_L"),
SND_SOC_DAPM_INPUT("IN3_R"),
SND_SOC_DAPM_INPUT("CM_L"),
SND_SOC_DAPM_INPUT("CM_R"),
};
static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = {
/* Left Output */
{"HPL Output Mixer", "L_DAC Switch", "Left DAC"},
{"HPL Output Mixer", "IN1_L Switch", "IN1_L"},
{"HPL Power", NULL, "HPL Output Mixer"},
{"HPL", NULL, "HPL Power"},
{"LOL Output Mixer", "L_DAC Switch", "Left DAC"},
{"LOL Power", NULL, "LOL Output Mixer"},
{"LOL", NULL, "LOL Power"},
/* Right Output */
{"HPR Output Mixer", "R_DAC Switch", "Right DAC"},
{"HPR Output Mixer", "IN1_R Switch", "IN1_R"},
{"HPR Power", NULL, "HPR Output Mixer"},
{"HPR", NULL, "HPR Power"},
{"LOR Output Mixer", "R_DAC Switch", "Right DAC"},
{"LOR Power", NULL, "LOR Output Mixer"},
{"LOR", NULL, "LOR Power"},
/* Right Input */
{"Right ADC", NULL, "IN1_R to Right Mixer Positive Resistor"},
{"IN1_R to Right Mixer Positive Resistor", "10 kOhm", "IN1_R"},
{"IN1_R to Right Mixer Positive Resistor", "20 kOhm", "IN1_R"},
{"IN1_R to Right Mixer Positive Resistor", "40 kOhm", "IN1_R"},
{"Right ADC", NULL, "IN2_R to Right Mixer Positive Resistor"},
{"IN2_R to Right Mixer Positive Resistor", "10 kOhm", "IN2_R"},
{"IN2_R to Right Mixer Positive Resistor", "20 kOhm", "IN2_R"},
{"IN2_R to Right Mixer Positive Resistor", "40 kOhm", "IN2_R"},
{"Right ADC", NULL, "IN3_R to Right Mixer Positive Resistor"},
{"IN3_R to Right Mixer Positive Resistor", "10 kOhm", "IN3_R"},
{"IN3_R to Right Mixer Positive Resistor", "20 kOhm", "IN3_R"},
{"IN3_R to Right Mixer Positive Resistor", "40 kOhm", "IN3_R"},
{"Right ADC", NULL, "IN2_L to Right Mixer Positive Resistor"},
{"IN2_L to Right Mixer Positive Resistor", "10 kOhm", "IN2_L"},
{"IN2_L to Right Mixer Positive Resistor", "20 kOhm", "IN2_L"},
{"IN2_L to Right Mixer Positive Resistor", "40 kOhm", "IN2_L"},
{"Right ADC", NULL, "CM_R to Right Mixer Negative Resistor"},
{"CM_R to Right Mixer Negative Resistor", "10 kOhm", "CM_R"},
{"CM_R to Right Mixer Negative Resistor", "20 kOhm", "CM_R"},
{"CM_R to Right Mixer Negative Resistor", "40 kOhm", "CM_R"},
{"Right ADC", NULL, "IN1_L to Right Mixer Negative Resistor"},
{"IN1_L to Right Mixer Negative Resistor", "10 kOhm", "IN1_L"},
{"IN1_L to Right Mixer Negative Resistor", "20 kOhm", "IN1_L"},
{"IN1_L to Right Mixer Negative Resistor", "40 kOhm", "IN1_L"},
{"Right ADC", NULL, "IN3_L to Right Mixer Negative Resistor"},
{"IN3_L to Right Mixer Negative Resistor", "10 kOhm", "IN3_L"},
{"IN3_L to Right Mixer Negative Resistor", "20 kOhm", "IN3_L"},
{"IN3_L to Right Mixer Negative Resistor", "40 kOhm", "IN3_L"},
/* Left Input */
{"Left ADC", NULL, "IN1_L to Left Mixer Positive Resistor"},
{"IN1_L to Left Mixer Positive Resistor", "10 kOhm", "IN1_L"},
{"IN1_L to Left Mixer Positive Resistor", "20 kOhm", "IN1_L"},
{"IN1_L to Left Mixer Positive Resistor", "40 kOhm", "IN1_L"},
{"Left ADC", NULL, "IN2_L to Left Mixer Positive Resistor"},
{"IN2_L to Left Mixer Positive Resistor", "10 kOhm", "IN2_L"},
{"IN2_L to Left Mixer Positive Resistor", "20 kOhm", "IN2_L"},
{"IN2_L to Left Mixer Positive Resistor", "40 kOhm", "IN2_L"},
{"Left ADC", NULL, "IN3_L to Left Mixer Positive Resistor"},
{"IN3_L to Left Mixer Positive Resistor", "10 kOhm", "IN3_L"},
{"IN3_L to Left Mixer Positive Resistor", "20 kOhm", "IN3_L"},
{"IN3_L to Left Mixer Positive Resistor", "40 kOhm", "IN3_L"},
{"Left ADC", NULL, "IN1_R to Left Mixer Positive Resistor"},
{"IN1_R to Left Mixer Positive Resistor", "10 kOhm", "IN1_R"},
{"IN1_R to Left Mixer Positive Resistor", "20 kOhm", "IN1_R"},
{"IN1_R to Left Mixer Positive Resistor", "40 kOhm", "IN1_R"},
{"Left ADC", NULL, "CM_L to Left Mixer Negative Resistor"},
{"CM_L to Left Mixer Negative Resistor", "10 kOhm", "CM_L"},
{"CM_L to Left Mixer Negative Resistor", "20 kOhm", "CM_L"},
{"CM_L to Left Mixer Negative Resistor", "40 kOhm", "CM_L"},
{"Left ADC", NULL, "IN2_R to Left Mixer Negative Resistor"},
{"IN2_R to Left Mixer Negative Resistor", "10 kOhm", "IN2_R"},
{"IN2_R to Left Mixer Negative Resistor", "20 kOhm", "IN2_R"},
{"IN2_R to Left Mixer Negative Resistor", "40 kOhm", "IN2_R"},
{"Left ADC", NULL, "IN3_R to Left Mixer Negative Resistor"},
{"IN3_R to Left Mixer Negative Resistor", "10 kOhm", "IN3_R"},
{"IN3_R to Left Mixer Negative Resistor", "20 kOhm", "IN3_R"},
{"IN3_R to Left Mixer Negative Resistor", "40 kOhm", "IN3_R"},
};
static const struct regmap_range_cfg aic32x4_regmap_pages[] = {
{
.selector_reg = 0,
.selector_mask = 0xff,
.window_start = 0,
.window_len = 128,
.range_min = 0,
.range_max = AIC32X4_REFPOWERUP,
},
};
const struct regmap_config aic32x4_regmap_config = {
.max_register = AIC32X4_REFPOWERUP,
.ranges = aic32x4_regmap_pages,
.num_ranges = ARRAY_SIZE(aic32x4_regmap_pages),
};
EXPORT_SYMBOL(aic32x4_regmap_config);
static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct clk *mclk;
struct clk *pll;
pll = devm_clk_get(component->dev, "pll");
if (IS_ERR(pll))
return PTR_ERR(pll);
mclk = clk_get_parent(pll);
return clk_set_rate(mclk, freq);
}
static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
u8 iface_reg_1 = 0;
u8 iface_reg_2 = 0;
u8 iface_reg_3 = 0;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER;
break;
case SND_SOC_DAIFMT_CBC_CFC:
break;
default:
printk(KERN_ERR "aic32x4: invalid clock provider\n");
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_DSP_A:
iface_reg_1 |= (AIC32X4_DSP_MODE <<
AIC32X4_IFACE1_DATATYPE_SHIFT);
iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */
iface_reg_2 = 0x01; /* add offset 1 */
break;
case SND_SOC_DAIFMT_DSP_B:
iface_reg_1 |= (AIC32X4_DSP_MODE <<
AIC32X4_IFACE1_DATATYPE_SHIFT);
iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */
break;
case SND_SOC_DAIFMT_RIGHT_J:
iface_reg_1 |= (AIC32X4_RIGHT_JUSTIFIED_MODE <<
AIC32X4_IFACE1_DATATYPE_SHIFT);
break;
case SND_SOC_DAIFMT_LEFT_J:
iface_reg_1 |= (AIC32X4_LEFT_JUSTIFIED_MODE <<
AIC32X4_IFACE1_DATATYPE_SHIFT);
break;
default:
printk(KERN_ERR "aic32x4: invalid DAI interface format\n");
return -EINVAL;
}
aic32x4->fmt = fmt;
snd_soc_component_update_bits(component, AIC32X4_IFACE1,
AIC32X4_IFACE1_DATATYPE_MASK |
AIC32X4_IFACE1_MASTER_MASK, iface_reg_1);
snd_soc_component_update_bits(component, AIC32X4_IFACE2,
AIC32X4_DATA_OFFSET_MASK, iface_reg_2);
snd_soc_component_update_bits(component, AIC32X4_IFACE3,
AIC32X4_BCLKINV_MASK, iface_reg_3);
return 0;
}
static int aic32x4_set_aosr(struct snd_soc_component *component, u8 aosr)
{
return snd_soc_component_write(component, AIC32X4_AOSR, aosr);
}
static int aic32x4_set_dosr(struct snd_soc_component *component, u16 dosr)
{
snd_soc_component_write(component, AIC32X4_DOSRMSB, dosr >> 8);
snd_soc_component_write(component, AIC32X4_DOSRLSB,
(dosr & 0xff));
return 0;
}
static int aic32x4_set_processing_blocks(struct snd_soc_component *component,
u8 r_block, u8 p_block)
{
struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
if (aic32x4->type == AIC32X4_TYPE_TAS2505) {
if (r_block || p_block > 3)
return -EINVAL;
snd_soc_component_write(component, AIC32X4_DACSPB, p_block);
} else { /* AIC32x4 */
if (r_block > 18 || p_block > 25)
return -EINVAL;
snd_soc_component_write(component, AIC32X4_ADCSPB, r_block);
snd_soc_component_write(component, AIC32X4_DACSPB, p_block);
}
return 0;
}
static int aic32x4_setup_clocks(struct snd_soc_component *component,
unsigned int sample_rate, unsigned int channels,
unsigned int bit_depth)
{
struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
u8 aosr;
u16 dosr;
u8 adc_resource_class, dac_resource_class;
u8 madc, nadc, mdac, ndac, max_nadc, min_mdac, max_ndac;
u8 dosr_increment;
u16 max_dosr, min_dosr;
unsigned long adc_clock_rate, dac_clock_rate;
int ret;
static struct clk_bulk_data clocks[] = {
{ .id = "pll" },
{ .id = "nadc" },
{ .id = "madc" },
{ .id = "ndac" },
{ .id = "mdac" },
{ .id = "bdiv" },
};
ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
if (ret)
return ret;
if (sample_rate <= 48000) {
aosr = 128;
adc_resource_class = 6;
dac_resource_class = 8;
dosr_increment = 8;
if (aic32x4->type == AIC32X4_TYPE_TAS2505)
aic32x4_set_processing_blocks(component, 0, 1);
else
aic32x4_set_processing_blocks(component, 1, 1);
} else if (sample_rate <= 96000) {
aosr = 64;
adc_resource_class = 6;
dac_resource_class = 8;
dosr_increment = 4;
if (aic32x4->type == AIC32X4_TYPE_TAS2505)
aic32x4_set_processing_blocks(component, 0, 1);
else
aic32x4_set_processing_blocks(component, 1, 9);
} else if (sample_rate == 192000) {
aosr = 32;
adc_resource_class = 3;
dac_resource_class = 4;
dosr_increment = 2;
if (aic32x4->type == AIC32X4_TYPE_TAS2505)
aic32x4_set_processing_blocks(component, 0, 1);
else
aic32x4_set_processing_blocks(component, 13, 19);
} else {
dev_err(component->dev, "Sampling rate not supported\n");
return -EINVAL;
}
/* PCM over I2S is always 2-channel */
if ((aic32x4->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_I2S)
channels = 2;
madc = DIV_ROUND_UP((32 * adc_resource_class), aosr);
max_dosr = (AIC32X4_MAX_DOSR_FREQ / sample_rate / dosr_increment) *
dosr_increment;
min_dosr = (AIC32X4_MIN_DOSR_FREQ / sample_rate / dosr_increment) *
dosr_increment;
max_nadc = AIC32X4_MAX_CODEC_CLKIN_FREQ / (madc * aosr * sample_rate);
for (nadc = max_nadc; nadc > 0; --nadc) {
adc_clock_rate = nadc * madc * aosr * sample_rate;
for (dosr = max_dosr; dosr >= min_dosr;
dosr -= dosr_increment) {
min_mdac = DIV_ROUND_UP((32 * dac_resource_class), dosr);
max_ndac = AIC32X4_MAX_CODEC_CLKIN_FREQ /
(min_mdac * dosr * sample_rate);
for (mdac = min_mdac; mdac <= 128; ++mdac) {
for (ndac = max_ndac; ndac > 0; --ndac) {
dac_clock_rate = ndac * mdac * dosr *
sample_rate;
if (dac_clock_rate == adc_clock_rate) {
if (clk_round_rate(clocks[0].clk, dac_clock_rate) == 0)
continue;
clk_set_rate(clocks[0].clk,
dac_clock_rate);
clk_set_rate(clocks[1].clk,
sample_rate * aosr *
madc);
clk_set_rate(clocks[2].clk,
sample_rate * aosr);
aic32x4_set_aosr(component,
aosr);
clk_set_rate(clocks[3].clk,
sample_rate * dosr *
mdac);
clk_set_rate(clocks[4].clk,
sample_rate * dosr);
aic32x4_set_dosr(component,
dosr);
clk_set_rate(clocks[5].clk,
sample_rate * channels *
bit_depth);
return 0;
}
}
}
}
}
dev_err(component->dev,
"Could not set clocks to support sample rate.\n");
return -EINVAL;
}
static int aic32x4_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
u8 iface1_reg = 0;
u8 dacsetup_reg = 0;
aic32x4_setup_clocks(component, params_rate(params),
params_channels(params),
params_physical_width(params));
switch (params_physical_width(params)) {
case 16:
iface1_reg |= (AIC32X4_WORD_LEN_16BITS <<
AIC32X4_IFACE1_DATALEN_SHIFT);
break;
case 20:
iface1_reg |= (AIC32X4_WORD_LEN_20BITS <<
AIC32X4_IFACE1_DATALEN_SHIFT);
break;
case 24:
iface1_reg |= (AIC32X4_WORD_LEN_24BITS <<
AIC32X4_IFACE1_DATALEN_SHIFT);
break;
case 32:
iface1_reg |= (AIC32X4_WORD_LEN_32BITS <<
AIC32X4_IFACE1_DATALEN_SHIFT);
break;
}
snd_soc_component_update_bits(component, AIC32X4_IFACE1,
AIC32X4_IFACE1_DATALEN_MASK, iface1_reg);
if (params_channels(params) == 1) {
dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN;
} else {
if (aic32x4->swapdacs)
dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN;
else
dacsetup_reg = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN;
}
snd_soc_component_update_bits(component, AIC32X4_DACSETUP,
AIC32X4_DAC_CHAN_MASK, dacsetup_reg);
return 0;
}
static int aic32x4_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
snd_soc_component_update_bits(component, AIC32X4_DACMUTE,
AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0);
return 0;
}
static int aic32x4_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
int ret;
static struct clk_bulk_data clocks[] = {
{ .id = "madc" },
{ .id = "mdac" },
{ .id = "bdiv" },
};
ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
if (ret)
return ret;
switch (level) {
case SND_SOC_BIAS_ON:
ret = clk_bulk_prepare_enable(ARRAY_SIZE(clocks), clocks);
if (ret) {
dev_err(component->dev, "Failed to enable clocks\n");
return ret;
}
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
/* Initial cold start */
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
break;
clk_bulk_disable_unprepare(ARRAY_SIZE(clocks), clocks);
break;
case SND_SOC_BIAS_OFF:
break;
}
return 0;
}
#define AIC32X4_RATES SNDRV_PCM_RATE_8000_192000
#define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
| SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_3LE \
| SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops aic32x4_ops = {
.hw_params = aic32x4_hw_params,
.mute_stream = aic32x4_mute,
.set_fmt = aic32x4_set_dai_fmt,
.set_sysclk = aic32x4_set_dai_sysclk,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver aic32x4_dai = {
.name = "tlv320aic32x4-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = AIC32X4_RATES,
.formats = AIC32X4_FORMATS,},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 8,
.rates = AIC32X4_RATES,
.formats = AIC32X4_FORMATS,},
.ops = &aic32x4_ops,
.symmetric_rate = 1,
};
static void aic32x4_setup_gpios(struct snd_soc_component *component)
{
struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
/* setup GPIO functions */
/* MFP1 */
if (aic32x4->setup->gpio_func[0] != AIC32X4_MFPX_DEFAULT_VALUE) {
snd_soc_component_write(component, AIC32X4_DINCTL,
aic32x4->setup->gpio_func[0]);
snd_soc_add_component_controls(component, aic32x4_mfp1,
ARRAY_SIZE(aic32x4_mfp1));
}
/* MFP2 */
if (aic32x4->setup->gpio_func[1] != AIC32X4_MFPX_DEFAULT_VALUE) {
snd_soc_component_write(component, AIC32X4_DOUTCTL,
aic32x4->setup->gpio_func[1]);
snd_soc_add_component_controls(component, aic32x4_mfp2,
ARRAY_SIZE(aic32x4_mfp2));
}
/* MFP3 */
if (aic32x4->setup->gpio_func[2] != AIC32X4_MFPX_DEFAULT_VALUE) {
snd_soc_component_write(component, AIC32X4_SCLKCTL,
aic32x4->setup->gpio_func[2]);
snd_soc_add_component_controls(component, aic32x4_mfp3,
ARRAY_SIZE(aic32x4_mfp3));
}
/* MFP4 */
if (aic32x4->setup->gpio_func[3] != AIC32X4_MFPX_DEFAULT_VALUE) {
snd_soc_component_write(component, AIC32X4_MISOCTL,
aic32x4->setup->gpio_func[3]);
snd_soc_add_component_controls(component, aic32x4_mfp4,
ARRAY_SIZE(aic32x4_mfp4));
}
/* MFP5 */
if (aic32x4->setup->gpio_func[4] != AIC32X4_MFPX_DEFAULT_VALUE) {
snd_soc_component_write(component, AIC32X4_GPIOCTL,
aic32x4->setup->gpio_func[4]);
snd_soc_add_component_controls(component, aic32x4_mfp5,
ARRAY_SIZE(aic32x4_mfp5));
}
}
static int aic32x4_component_probe(struct snd_soc_component *component)
{
struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
u32 tmp_reg;
int ret;
static struct clk_bulk_data clocks[] = {
{ .id = "codec_clkin" },
{ .id = "pll" },
{ .id = "bdiv" },
{ .id = "mdac" },
};
ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
if (ret)
return ret;
if (aic32x4->setup)
aic32x4_setup_gpios(component);
clk_set_parent(clocks[0].clk, clocks[1].clk);
clk_set_parent(clocks[2].clk, clocks[3].clk);
/* Power platform configuration */
if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
snd_soc_component_write(component, AIC32X4_MICBIAS,
AIC32X4_MICBIAS_LDOIN | AIC32X4_MICBIAS_2075V);
}
if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE)
snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
AIC32X4_LDOCTLEN : 0;
snd_soc_component_write(component, AIC32X4_LDOCTL, tmp_reg);
tmp_reg = snd_soc_component_read(component, AIC32X4_CMMODE);
if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36)
tmp_reg |= AIC32X4_LDOIN_18_36;
if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED)
tmp_reg |= AIC32X4_LDOIN2HP;
snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg);
/* Mic PGA routing */
if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K)
snd_soc_component_write(component, AIC32X4_LMICPGANIN,
AIC32X4_LMICPGANIN_IN2R_10K);
else
snd_soc_component_write(component, AIC32X4_LMICPGANIN,
AIC32X4_LMICPGANIN_CM1L_10K);
if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K)
snd_soc_component_write(component, AIC32X4_RMICPGANIN,
AIC32X4_RMICPGANIN_IN1L_10K);
else
snd_soc_component_write(component, AIC32X4_RMICPGANIN,
AIC32X4_RMICPGANIN_CM1R_10K);
/*
* Workaround: for an unknown reason, the ADC needs to be powered up
* and down for the first capture to work properly. It seems related to
* a HW BUG or some kind of behavior not documented in the datasheet.
*/
tmp_reg = snd_soc_component_read(component, AIC32X4_ADCSETUP);
snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg |
AIC32X4_LADC_EN | AIC32X4_RADC_EN);
snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg);
/*
* Enable the fast charging feature and ensure the needed 40ms ellapsed
* before using the analog circuits.
*/
snd_soc_component_write(component, AIC32X4_REFPOWERUP,
AIC32X4_REFPOWERUP_40MS);
msleep(40);
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_aic32x4 = {
.probe = aic32x4_component_probe,
.set_bias_level = aic32x4_set_bias_level,
.controls = aic32x4_snd_controls,
.num_controls = ARRAY_SIZE(aic32x4_snd_controls),
.dapm_widgets = aic32x4_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets),
.dapm_routes = aic32x4_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct snd_kcontrol_new aic32x4_tas2505_snd_controls[] = {
SOC_SINGLE_S8_TLV("PCM Playback Volume",
AIC32X4_LDACVOL, -0x7f, 0x30, tlv_pcm),
SOC_ENUM("DAC Playback PowerTune Switch", l_ptm_enum),
SOC_SINGLE_TLV("HP Driver Gain Volume",
AIC32X4_HPLGAIN, 0, 0x74, 1, tlv_tas_driver_gain),
SOC_SINGLE("HP DAC Playback Switch", AIC32X4_HPLGAIN, 6, 1, 1),
SOC_SINGLE_TLV("Speaker Driver Playback Volume",
TAS2505_SPKVOL1, 0, 0x74, 1, tlv_tas_driver_gain),
SOC_SINGLE_TLV("Speaker Amplifier Playback Volume",
TAS2505_SPKVOL2, 4, 5, 0, tlv_amp_vol),
SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
};
static const struct snd_kcontrol_new hp_output_mixer_controls[] = {
SOC_DAPM_SINGLE("DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
};
static const struct snd_soc_dapm_widget aic32x4_tas2505_dapm_widgets[] = {
SND_SOC_DAPM_DAC("DAC", "Playback", AIC32X4_DACSETUP, 7, 0),
SND_SOC_DAPM_MIXER("HP Output Mixer", SND_SOC_NOPM, 0, 0,
&hp_output_mixer_controls[0],
ARRAY_SIZE(hp_output_mixer_controls)),
SND_SOC_DAPM_PGA("HP Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA("Speaker Driver", TAS2505_SPK, 1, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("HP"),
SND_SOC_DAPM_OUTPUT("Speaker"),
};
static const struct snd_soc_dapm_route aic32x4_tas2505_dapm_routes[] = {
/* Left Output */
{"HP Output Mixer", "DAC Switch", "DAC"},
{"HP Power", NULL, "HP Output Mixer"},
{"HP", NULL, "HP Power"},
{"Speaker Driver", NULL, "DAC"},
{"Speaker", NULL, "Speaker Driver"},
};
static struct snd_soc_dai_driver aic32x4_tas2505_dai = {
.name = "tas2505-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = AIC32X4_FORMATS,},
.ops = &aic32x4_ops,
.symmetric_rate = 1,
};
static int aic32x4_tas2505_component_probe(struct snd_soc_component *component)
{
struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
u32 tmp_reg;
int ret;
static struct clk_bulk_data clocks[] = {
{ .id = "codec_clkin" },
{ .id = "pll" },
{ .id = "bdiv" },
{ .id = "mdac" },
};
ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
if (ret)
return ret;
if (aic32x4->setup)
aic32x4_setup_gpios(component);
clk_set_parent(clocks[0].clk, clocks[1].clk);
clk_set_parent(clocks[2].clk, clocks[3].clk);
/* Power platform configuration */
if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE)
snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
AIC32X4_LDOCTLEN : 0;
snd_soc_component_write(component, AIC32X4_LDOCTL, tmp_reg);
tmp_reg = snd_soc_component_read(component, AIC32X4_CMMODE);
if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36)
tmp_reg |= AIC32X4_LDOIN_18_36;
if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED)
tmp_reg |= AIC32X4_LDOIN2HP;
snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg);
/*
* Enable the fast charging feature and ensure the needed 40ms ellapsed
* before using the analog circuits.
*/
snd_soc_component_write(component, TAS2505_REFPOWERUP,
AIC32X4_REFPOWERUP_40MS);
msleep(40);
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_aic32x4_tas2505 = {
.probe = aic32x4_tas2505_component_probe,
.set_bias_level = aic32x4_set_bias_level,
.controls = aic32x4_tas2505_snd_controls,
.num_controls = ARRAY_SIZE(aic32x4_tas2505_snd_controls),
.dapm_widgets = aic32x4_tas2505_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(aic32x4_tas2505_dapm_widgets),
.dapm_routes = aic32x4_tas2505_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(aic32x4_tas2505_dapm_routes),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4,
struct device_node *np)
{
struct aic32x4_setup_data *aic32x4_setup;
int ret;
aic32x4_setup = devm_kzalloc(aic32x4->dev, sizeof(*aic32x4_setup),
GFP_KERNEL);
if (!aic32x4_setup)
return -ENOMEM;
ret = of_property_match_string(np, "clock-names", "mclk");
if (ret < 0)
return -EINVAL;
aic32x4->mclk_name = of_clk_get_parent_name(np, ret);
aic32x4->swapdacs = false;
aic32x4->micpga_routing = 0;
aic32x4->rstn_gpio = of_get_named_gpio(np, "reset-gpios", 0);
if (of_property_read_u32_array(np, "aic32x4-gpio-func",
aic32x4_setup->gpio_func, 5) >= 0)
aic32x4->setup = aic32x4_setup;
return 0;
}
static void aic32x4_disable_regulators(struct aic32x4_priv *aic32x4)
{
regulator_disable(aic32x4->supply_iov);
if (!IS_ERR(aic32x4->supply_ldo))
regulator_disable(aic32x4->supply_ldo);
if (!IS_ERR(aic32x4->supply_dv))
regulator_disable(aic32x4->supply_dv);
if (!IS_ERR(aic32x4->supply_av))
regulator_disable(aic32x4->supply_av);
}
static int aic32x4_setup_regulators(struct device *dev,
struct aic32x4_priv *aic32x4)
{
int ret = 0;
aic32x4->supply_ldo = devm_regulator_get_optional(dev, "ldoin");
aic32x4->supply_iov = devm_regulator_get(dev, "iov");
aic32x4->supply_dv = devm_regulator_get_optional(dev, "dv");
aic32x4->supply_av = devm_regulator_get_optional(dev, "av");
/* Check if the regulator requirements are fulfilled */
if (IS_ERR(aic32x4->supply_iov)) {
dev_err(dev, "Missing supply 'iov'\n");
return PTR_ERR(aic32x4->supply_iov);
}
if (IS_ERR(aic32x4->supply_ldo)) {
if (PTR_ERR(aic32x4->supply_ldo) == -EPROBE_DEFER)
return -EPROBE_DEFER;
if (IS_ERR(aic32x4->supply_dv)) {
dev_err(dev, "Missing supply 'dv' or 'ldoin'\n");
return PTR_ERR(aic32x4->supply_dv);
}
if (IS_ERR(aic32x4->supply_av)) {
dev_err(dev, "Missing supply 'av' or 'ldoin'\n");
return PTR_ERR(aic32x4->supply_av);
}
} else {
if (PTR_ERR(aic32x4->supply_dv) == -EPROBE_DEFER)
return -EPROBE_DEFER;
if (PTR_ERR(aic32x4->supply_av) == -EPROBE_DEFER)
return -EPROBE_DEFER;
}
ret = regulator_enable(aic32x4->supply_iov);
if (ret) {
dev_err(dev, "Failed to enable regulator iov\n");
return ret;
}
if (!IS_ERR(aic32x4->supply_ldo)) {
ret = regulator_enable(aic32x4->supply_ldo);
if (ret) {
dev_err(dev, "Failed to enable regulator ldo\n");
goto error_ldo;
}
}
if (!IS_ERR(aic32x4->supply_dv)) {
ret = regulator_enable(aic32x4->supply_dv);
if (ret) {
dev_err(dev, "Failed to enable regulator dv\n");
goto error_dv;
}
}
if (!IS_ERR(aic32x4->supply_av)) {
ret = regulator_enable(aic32x4->supply_av);
if (ret) {
dev_err(dev, "Failed to enable regulator av\n");
goto error_av;
}
}
if (!IS_ERR(aic32x4->supply_ldo) && IS_ERR(aic32x4->supply_av))
aic32x4->power_cfg |= AIC32X4_PWR_AIC32X4_LDO_ENABLE;
return 0;
error_av:
if (!IS_ERR(aic32x4->supply_dv))
regulator_disable(aic32x4->supply_dv);
error_dv:
if (!IS_ERR(aic32x4->supply_ldo))
regulator_disable(aic32x4->supply_ldo);
error_ldo:
regulator_disable(aic32x4->supply_iov);
return ret;
}
int aic32x4_probe(struct device *dev, struct regmap *regmap)
{
struct aic32x4_priv *aic32x4;
struct aic32x4_pdata *pdata = dev->platform_data;
struct device_node *np = dev->of_node;
int ret;
if (IS_ERR(regmap))
return PTR_ERR(regmap);
aic32x4 = devm_kzalloc(dev, sizeof(struct aic32x4_priv),
GFP_KERNEL);
if (aic32x4 == NULL)
return -ENOMEM;
aic32x4->dev = dev;
aic32x4->type = (uintptr_t)dev_get_drvdata(dev);
dev_set_drvdata(dev, aic32x4);
if (pdata) {
aic32x4->power_cfg = pdata->power_cfg;
aic32x4->swapdacs = pdata->swapdacs;
aic32x4->micpga_routing = pdata->micpga_routing;
aic32x4->rstn_gpio = pdata->rstn_gpio;
aic32x4->mclk_name = "mclk";
} else if (np) {
ret = aic32x4_parse_dt(aic32x4, np);
if (ret) {
dev_err(dev, "Failed to parse DT node\n");
return ret;
}
} else {
aic32x4->power_cfg = 0;
aic32x4->swapdacs = false;
aic32x4->micpga_routing = 0;
aic32x4->rstn_gpio = -1;
aic32x4->mclk_name = "mclk";
}
if (gpio_is_valid(aic32x4->rstn_gpio)) {
ret = devm_gpio_request_one(dev, aic32x4->rstn_gpio,
GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn");
if (ret != 0)
return ret;
}
ret = aic32x4_setup_regulators(dev, aic32x4);
if (ret) {
dev_err(dev, "Failed to setup regulators\n");
return ret;
}
if (gpio_is_valid(aic32x4->rstn_gpio)) {
ndelay(10);
gpio_set_value_cansleep(aic32x4->rstn_gpio, 1);
mdelay(1);
}
ret = regmap_write(regmap, AIC32X4_RESET, 0x01);
if (ret)
goto err_disable_regulators;
ret = aic32x4_register_clocks(dev, aic32x4->mclk_name);
if (ret)
goto err_disable_regulators;
switch (aic32x4->type) {
case AIC32X4_TYPE_TAS2505:
ret = devm_snd_soc_register_component(dev,
&soc_component_dev_aic32x4_tas2505, &aic32x4_tas2505_dai, 1);
break;
default:
ret = devm_snd_soc_register_component(dev,
&soc_component_dev_aic32x4, &aic32x4_dai, 1);
}
if (ret) {
dev_err(dev, "Failed to register component\n");
goto err_disable_regulators;
}
return 0;
err_disable_regulators:
aic32x4_disable_regulators(aic32x4);
return ret;
}
EXPORT_SYMBOL(aic32x4_probe);
void aic32x4_remove(struct device *dev)
{
struct aic32x4_priv *aic32x4 = dev_get_drvdata(dev);
aic32x4_disable_regulators(aic32x4);
}
EXPORT_SYMBOL(aic32x4_remove);
MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver");
MODULE_AUTHOR("Javier Martin <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/tlv320aic32x4.c |
// SPDX-License-Identifier: GPL-2.0
//
// cs35l41-i2c.c -- CS35l41 I2C driver
//
// Copyright 2017-2021 Cirrus Logic, Inc.
//
// Author: David Rhodes <[email protected]>
#include <linux/acpi.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include "cs35l41.h"
static const struct i2c_device_id cs35l41_id_i2c[] = {
{ "cs35l40", 0 },
{ "cs35l41", 0 },
{ "cs35l51", 0 },
{ "cs35l53", 0 },
{}
};
MODULE_DEVICE_TABLE(i2c, cs35l41_id_i2c);
static int cs35l41_i2c_probe(struct i2c_client *client)
{
struct cs35l41_private *cs35l41;
struct device *dev = &client->dev;
struct cs35l41_hw_cfg *hw_cfg = dev_get_platdata(dev);
const struct regmap_config *regmap_config = &cs35l41_regmap_i2c;
int ret;
cs35l41 = devm_kzalloc(dev, sizeof(struct cs35l41_private), GFP_KERNEL);
if (!cs35l41)
return -ENOMEM;
cs35l41->dev = dev;
cs35l41->irq = client->irq;
i2c_set_clientdata(client, cs35l41);
cs35l41->regmap = devm_regmap_init_i2c(client, regmap_config);
if (IS_ERR(cs35l41->regmap)) {
ret = PTR_ERR(cs35l41->regmap);
dev_err(cs35l41->dev, "Failed to allocate register map: %d\n", ret);
return ret;
}
return cs35l41_probe(cs35l41, hw_cfg);
}
static void cs35l41_i2c_remove(struct i2c_client *client)
{
struct cs35l41_private *cs35l41 = i2c_get_clientdata(client);
cs35l41_remove(cs35l41);
}
#ifdef CONFIG_OF
static const struct of_device_id cs35l41_of_match[] = {
{ .compatible = "cirrus,cs35l40" },
{ .compatible = "cirrus,cs35l41" },
{},
};
MODULE_DEVICE_TABLE(of, cs35l41_of_match);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id cs35l41_acpi_match[] = {
{ "CSC3541", 0 }, /* Cirrus Logic PnP ID + part ID */
{},
};
MODULE_DEVICE_TABLE(acpi, cs35l41_acpi_match);
#endif
static struct i2c_driver cs35l41_i2c_driver = {
.driver = {
.name = "cs35l41",
.pm = &cs35l41_pm_ops,
.of_match_table = of_match_ptr(cs35l41_of_match),
.acpi_match_table = ACPI_PTR(cs35l41_acpi_match),
},
.id_table = cs35l41_id_i2c,
.probe = cs35l41_i2c_probe,
.remove = cs35l41_i2c_remove,
};
module_i2c_driver(cs35l41_i2c_driver);
MODULE_DESCRIPTION("I2C CS35L41 driver");
MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cs35l41-i2c.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm5100.c -- WM5100 ALSA SoC Audio driver
*
* Copyright 2011-2 Wolfson Microelectronics plc
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/export.h>
#include <linux/pm.h>
#include <linux/gcd.h>
#include <linux/gpio/driver.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <linux/regulator/fixed.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/jack.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/wm5100.h>
#include "wm5100.h"
#define WM5100_NUM_CORE_SUPPLIES 2
static const char *wm5100_core_supply_names[WM5100_NUM_CORE_SUPPLIES] = {
"DBVDD1",
"LDOVDD", /* If DCVDD is supplied externally specify as LDOVDD */
};
#define WM5100_AIFS 3
#define WM5100_SYNC_SRS 3
struct wm5100_fll {
int fref;
int fout;
int src;
struct completion lock;
};
/* codec private data */
struct wm5100_priv {
struct device *dev;
struct regmap *regmap;
struct snd_soc_component *component;
struct regulator_bulk_data core_supplies[WM5100_NUM_CORE_SUPPLIES];
int rev;
int sysclk;
int asyncclk;
bool aif_async[WM5100_AIFS];
bool aif_symmetric[WM5100_AIFS];
int sr_ref[WM5100_SYNC_SRS];
bool out_ena[2];
struct snd_soc_jack *jack;
bool jack_detecting;
bool jack_mic;
int jack_mode;
int jack_flips;
struct wm5100_fll fll[2];
struct wm5100_pdata pdata;
#ifdef CONFIG_GPIOLIB
struct gpio_chip gpio_chip;
#endif
};
static int wm5100_sr_code[] = {
0,
12000,
24000,
48000,
96000,
192000,
384000,
768000,
0,
11025,
22050,
44100,
88200,
176400,
352800,
705600,
4000,
8000,
16000,
32000,
64000,
128000,
256000,
512000,
};
static int wm5100_sr_regs[WM5100_SYNC_SRS] = {
WM5100_CLOCKING_4,
WM5100_CLOCKING_5,
WM5100_CLOCKING_6,
};
static int wm5100_alloc_sr(struct snd_soc_component *component, int rate)
{
struct wm5100_priv *wm5100 = snd_soc_component_get_drvdata(component);
int sr_code, sr_free, i;
for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
if (wm5100_sr_code[i] == rate)
break;
if (i == ARRAY_SIZE(wm5100_sr_code)) {
dev_err(component->dev, "Unsupported sample rate: %dHz\n", rate);
return -EINVAL;
}
sr_code = i;
if ((wm5100->sysclk % rate) == 0) {
/* Is this rate already in use? */
sr_free = -1;
for (i = 0; i < ARRAY_SIZE(wm5100_sr_regs); i++) {
if (!wm5100->sr_ref[i] && sr_free == -1) {
sr_free = i;
continue;
}
if ((snd_soc_component_read(component, wm5100_sr_regs[i]) &
WM5100_SAMPLE_RATE_1_MASK) == sr_code)
break;
}
if (i < ARRAY_SIZE(wm5100_sr_regs)) {
wm5100->sr_ref[i]++;
dev_dbg(component->dev, "SR %dHz, slot %d, ref %d\n",
rate, i, wm5100->sr_ref[i]);
return i;
}
if (sr_free == -1) {
dev_err(component->dev, "All SR slots already in use\n");
return -EBUSY;
}
dev_dbg(component->dev, "Allocating SR slot %d for %dHz\n",
sr_free, rate);
wm5100->sr_ref[sr_free]++;
snd_soc_component_update_bits(component, wm5100_sr_regs[sr_free],
WM5100_SAMPLE_RATE_1_MASK,
sr_code);
return sr_free;
} else {
dev_err(component->dev,
"SR %dHz incompatible with %dHz SYSCLK and %dHz ASYNCCLK\n",
rate, wm5100->sysclk, wm5100->asyncclk);
return -EINVAL;
}
}
static void wm5100_free_sr(struct snd_soc_component *component, int rate)
{
struct wm5100_priv *wm5100 = snd_soc_component_get_drvdata(component);
int i, sr_code;
for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
if (wm5100_sr_code[i] == rate)
break;
if (i == ARRAY_SIZE(wm5100_sr_code)) {
dev_err(component->dev, "Unsupported sample rate: %dHz\n", rate);
return;
}
sr_code = wm5100_sr_code[i];
for (i = 0; i < ARRAY_SIZE(wm5100_sr_regs); i++) {
if (!wm5100->sr_ref[i])
continue;
if ((snd_soc_component_read(component, wm5100_sr_regs[i]) &
WM5100_SAMPLE_RATE_1_MASK) == sr_code)
break;
}
if (i < ARRAY_SIZE(wm5100_sr_regs)) {
wm5100->sr_ref[i]--;
dev_dbg(component->dev, "Dereference SR %dHz, count now %d\n",
rate, wm5100->sr_ref[i]);
} else {
dev_warn(component->dev, "Freeing unreferenced sample rate %dHz\n",
rate);
}
}
static int wm5100_reset(struct wm5100_priv *wm5100)
{
if (wm5100->pdata.reset) {
gpio_set_value_cansleep(wm5100->pdata.reset, 0);
gpio_set_value_cansleep(wm5100->pdata.reset, 1);
return 0;
} else {
return regmap_write(wm5100->regmap, WM5100_SOFTWARE_RESET, 0);
}
}
static DECLARE_TLV_DB_SCALE(in_tlv, -6300, 100, 0);
static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
static DECLARE_TLV_DB_SCALE(mixer_tlv, -3200, 100, 0);
static DECLARE_TLV_DB_SCALE(out_tlv, -6400, 100, 0);
static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0);
static const char *wm5100_mixer_texts[] = {
"None",
"Tone Generator 1",
"Tone Generator 2",
"AEC loopback",
"IN1L",
"IN1R",
"IN2L",
"IN2R",
"IN3L",
"IN3R",
"IN4L",
"IN4R",
"AIF1RX1",
"AIF1RX2",
"AIF1RX3",
"AIF1RX4",
"AIF1RX5",
"AIF1RX6",
"AIF1RX7",
"AIF1RX8",
"AIF2RX1",
"AIF2RX2",
"AIF3RX1",
"AIF3RX2",
"EQ1",
"EQ2",
"EQ3",
"EQ4",
"DRC1L",
"DRC1R",
"LHPF1",
"LHPF2",
"LHPF3",
"LHPF4",
"DSP1.1",
"DSP1.2",
"DSP1.3",
"DSP1.4",
"DSP1.5",
"DSP1.6",
"DSP2.1",
"DSP2.2",
"DSP2.3",
"DSP2.4",
"DSP2.5",
"DSP2.6",
"DSP3.1",
"DSP3.2",
"DSP3.3",
"DSP3.4",
"DSP3.5",
"DSP3.6",
"ASRC1L",
"ASRC1R",
"ASRC2L",
"ASRC2R",
"ISRC1INT1",
"ISRC1INT2",
"ISRC1INT3",
"ISRC1INT4",
"ISRC2INT1",
"ISRC2INT2",
"ISRC2INT3",
"ISRC2INT4",
"ISRC1DEC1",
"ISRC1DEC2",
"ISRC1DEC3",
"ISRC1DEC4",
"ISRC2DEC1",
"ISRC2DEC2",
"ISRC2DEC3",
"ISRC2DEC4",
};
static int wm5100_mixer_values[] = {
0x00,
0x04, /* Tone */
0x05,
0x08, /* AEC */
0x10, /* Input */
0x11,
0x12,
0x13,
0x14,
0x15,
0x16,
0x17,
0x20, /* AIF */
0x21,
0x22,
0x23,
0x24,
0x25,
0x26,
0x27,
0x28,
0x29,
0x30, /* AIF3 - check */
0x31,
0x50, /* EQ */
0x51,
0x52,
0x53,
0x54,
0x58, /* DRC */
0x59,
0x60, /* LHPF1 */
0x61, /* LHPF2 */
0x62, /* LHPF3 */
0x63, /* LHPF4 */
0x68, /* DSP1 */
0x69,
0x6a,
0x6b,
0x6c,
0x6d,
0x70, /* DSP2 */
0x71,
0x72,
0x73,
0x74,
0x75,
0x78, /* DSP3 */
0x79,
0x7a,
0x7b,
0x7c,
0x7d,
0x90, /* ASRC1 */
0x91,
0x92, /* ASRC2 */
0x93,
0xa0, /* ISRC1DEC1 */
0xa1,
0xa2,
0xa3,
0xa4, /* ISRC1INT1 */
0xa5,
0xa6,
0xa7,
0xa8, /* ISRC2DEC1 */
0xa9,
0xaa,
0xab,
0xac, /* ISRC2INT1 */
0xad,
0xae,
0xaf,
};
#define WM5100_MIXER_CONTROLS(name, base) \
SOC_SINGLE_TLV(name " Input 1 Volume", base + 1 , \
WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
SOC_SINGLE_TLV(name " Input 2 Volume", base + 3 , \
WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
SOC_SINGLE_TLV(name " Input 3 Volume", base + 5 , \
WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
SOC_SINGLE_TLV(name " Input 4 Volume", base + 7 , \
WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv)
#define WM5100_MUX_ENUM_DECL(name, reg) \
SOC_VALUE_ENUM_SINGLE_DECL(name, reg, 0, 0xff, \
wm5100_mixer_texts, wm5100_mixer_values)
#define WM5100_MUX_CTL_DECL(name) \
const struct snd_kcontrol_new name##_mux = \
SOC_DAPM_ENUM("Route", name##_enum)
#define WM5100_MIXER_ENUMS(name, base_reg) \
static WM5100_MUX_ENUM_DECL(name##_in1_enum, base_reg); \
static WM5100_MUX_ENUM_DECL(name##_in2_enum, base_reg + 2); \
static WM5100_MUX_ENUM_DECL(name##_in3_enum, base_reg + 4); \
static WM5100_MUX_ENUM_DECL(name##_in4_enum, base_reg + 6); \
static WM5100_MUX_CTL_DECL(name##_in1); \
static WM5100_MUX_CTL_DECL(name##_in2); \
static WM5100_MUX_CTL_DECL(name##_in3); \
static WM5100_MUX_CTL_DECL(name##_in4)
WM5100_MIXER_ENUMS(HPOUT1L, WM5100_OUT1LMIX_INPUT_1_SOURCE);
WM5100_MIXER_ENUMS(HPOUT1R, WM5100_OUT1RMIX_INPUT_1_SOURCE);
WM5100_MIXER_ENUMS(HPOUT2L, WM5100_OUT2LMIX_INPUT_1_SOURCE);
WM5100_MIXER_ENUMS(HPOUT2R, WM5100_OUT2RMIX_INPUT_1_SOURCE);
WM5100_MIXER_ENUMS(HPOUT3L, WM5100_OUT3LMIX_INPUT_1_SOURCE);
WM5100_MIXER_ENUMS(HPOUT3R, WM5100_OUT3RMIX_INPUT_1_SOURCE);
WM5100_MIXER_ENUMS(SPKOUTL, WM5100_OUT4LMIX_INPUT_1_SOURCE);
WM5100_MIXER_ENUMS(SPKOUTR, WM5100_OUT4RMIX_INPUT_1_SOURCE);
WM5100_MIXER_ENUMS(SPKDAT1L, WM5100_OUT5LMIX_INPUT_1_SOURCE);
WM5100_MIXER_ENUMS(SPKDAT1R, WM5100_OUT5RMIX_INPUT_1_SOURCE);
WM5100_MIXER_ENUMS(SPKDAT2L, WM5100_OUT6LMIX_INPUT_1_SOURCE);
WM5100_MIXER_ENUMS(SPKDAT2R, WM5100_OUT6RMIX_INPUT_1_SOURCE);
WM5100_MIXER_ENUMS(PWM1, WM5100_PWM1MIX_INPUT_1_SOURCE);
WM5100_MIXER_ENUMS(PWM2, WM5100_PWM1MIX_INPUT_1_SOURCE);
WM5100_MIXER_ENUMS(AIF1TX1, WM5100_AIF1TX1MIX_INPUT_1_SOURCE);
WM5100_MIXER_ENUMS(AIF1TX2, WM5100_AIF1TX2MIX_INPUT_1_SOURCE);
WM5100_MIXER_ENUMS(AIF1TX3, WM5100_AIF1TX3MIX_INPUT_1_SOURCE);
WM5100_MIXER_ENUMS(AIF1TX4, WM5100_AIF1TX4MIX_INPUT_1_SOURCE);
WM5100_MIXER_ENUMS(AIF1TX5, WM5100_AIF1TX5MIX_INPUT_1_SOURCE);
WM5100_MIXER_ENUMS(AIF1TX6, WM5100_AIF1TX6MIX_INPUT_1_SOURCE);
WM5100_MIXER_ENUMS(AIF1TX7, WM5100_AIF1TX7MIX_INPUT_1_SOURCE);
WM5100_MIXER_ENUMS(AIF1TX8, WM5100_AIF1TX8MIX_INPUT_1_SOURCE);
WM5100_MIXER_ENUMS(AIF2TX1, WM5100_AIF2TX1MIX_INPUT_1_SOURCE);
WM5100_MIXER_ENUMS(AIF2TX2, WM5100_AIF2TX2MIX_INPUT_1_SOURCE);
WM5100_MIXER_ENUMS(AIF3TX1, WM5100_AIF1TX1MIX_INPUT_1_SOURCE);
WM5100_MIXER_ENUMS(AIF3TX2, WM5100_AIF1TX2MIX_INPUT_1_SOURCE);
WM5100_MIXER_ENUMS(EQ1, WM5100_EQ1MIX_INPUT_1_SOURCE);
WM5100_MIXER_ENUMS(EQ2, WM5100_EQ2MIX_INPUT_1_SOURCE);
WM5100_MIXER_ENUMS(EQ3, WM5100_EQ3MIX_INPUT_1_SOURCE);
WM5100_MIXER_ENUMS(EQ4, WM5100_EQ4MIX_INPUT_1_SOURCE);
WM5100_MIXER_ENUMS(DRC1L, WM5100_DRC1LMIX_INPUT_1_SOURCE);
WM5100_MIXER_ENUMS(DRC1R, WM5100_DRC1RMIX_INPUT_1_SOURCE);
WM5100_MIXER_ENUMS(LHPF1, WM5100_HPLP1MIX_INPUT_1_SOURCE);
WM5100_MIXER_ENUMS(LHPF2, WM5100_HPLP2MIX_INPUT_1_SOURCE);
WM5100_MIXER_ENUMS(LHPF3, WM5100_HPLP3MIX_INPUT_1_SOURCE);
WM5100_MIXER_ENUMS(LHPF4, WM5100_HPLP4MIX_INPUT_1_SOURCE);
#define WM5100_MUX(name, ctrl) \
SND_SOC_DAPM_MUX(name, SND_SOC_NOPM, 0, 0, ctrl)
#define WM5100_MIXER_WIDGETS(name, name_str) \
WM5100_MUX(name_str " Input 1", &name##_in1_mux), \
WM5100_MUX(name_str " Input 2", &name##_in2_mux), \
WM5100_MUX(name_str " Input 3", &name##_in3_mux), \
WM5100_MUX(name_str " Input 4", &name##_in4_mux), \
SND_SOC_DAPM_MIXER(name_str " Mixer", SND_SOC_NOPM, 0, 0, NULL, 0)
#define WM5100_MIXER_INPUT_ROUTES(name) \
{ name, "Tone Generator 1", "Tone Generator 1" }, \
{ name, "Tone Generator 2", "Tone Generator 2" }, \
{ name, "IN1L", "IN1L PGA" }, \
{ name, "IN1R", "IN1R PGA" }, \
{ name, "IN2L", "IN2L PGA" }, \
{ name, "IN2R", "IN2R PGA" }, \
{ name, "IN3L", "IN3L PGA" }, \
{ name, "IN3R", "IN3R PGA" }, \
{ name, "IN4L", "IN4L PGA" }, \
{ name, "IN4R", "IN4R PGA" }, \
{ name, "AIF1RX1", "AIF1RX1" }, \
{ name, "AIF1RX2", "AIF1RX2" }, \
{ name, "AIF1RX3", "AIF1RX3" }, \
{ name, "AIF1RX4", "AIF1RX4" }, \
{ name, "AIF1RX5", "AIF1RX5" }, \
{ name, "AIF1RX6", "AIF1RX6" }, \
{ name, "AIF1RX7", "AIF1RX7" }, \
{ name, "AIF1RX8", "AIF1RX8" }, \
{ name, "AIF2RX1", "AIF2RX1" }, \
{ name, "AIF2RX2", "AIF2RX2" }, \
{ name, "AIF3RX1", "AIF3RX1" }, \
{ name, "AIF3RX2", "AIF3RX2" }, \
{ name, "EQ1", "EQ1" }, \
{ name, "EQ2", "EQ2" }, \
{ name, "EQ3", "EQ3" }, \
{ name, "EQ4", "EQ4" }, \
{ name, "DRC1L", "DRC1L" }, \
{ name, "DRC1R", "DRC1R" }, \
{ name, "LHPF1", "LHPF1" }, \
{ name, "LHPF2", "LHPF2" }, \
{ name, "LHPF3", "LHPF3" }, \
{ name, "LHPF4", "LHPF4" }
#define WM5100_MIXER_ROUTES(widget, name) \
{ widget, NULL, name " Mixer" }, \
{ name " Mixer", NULL, name " Input 1" }, \
{ name " Mixer", NULL, name " Input 2" }, \
{ name " Mixer", NULL, name " Input 3" }, \
{ name " Mixer", NULL, name " Input 4" }, \
WM5100_MIXER_INPUT_ROUTES(name " Input 1"), \
WM5100_MIXER_INPUT_ROUTES(name " Input 2"), \
WM5100_MIXER_INPUT_ROUTES(name " Input 3"), \
WM5100_MIXER_INPUT_ROUTES(name " Input 4")
static const char *wm5100_lhpf_mode_text[] = {
"Low-pass", "High-pass"
};
static SOC_ENUM_SINGLE_DECL(wm5100_lhpf1_mode,
WM5100_HPLPF1_1, WM5100_LHPF1_MODE_SHIFT,
wm5100_lhpf_mode_text);
static SOC_ENUM_SINGLE_DECL(wm5100_lhpf2_mode,
WM5100_HPLPF2_1, WM5100_LHPF2_MODE_SHIFT,
wm5100_lhpf_mode_text);
static SOC_ENUM_SINGLE_DECL(wm5100_lhpf3_mode,
WM5100_HPLPF3_1, WM5100_LHPF3_MODE_SHIFT,
wm5100_lhpf_mode_text);
static SOC_ENUM_SINGLE_DECL(wm5100_lhpf4_mode,
WM5100_HPLPF4_1, WM5100_LHPF4_MODE_SHIFT,
wm5100_lhpf_mode_text);
static const struct snd_kcontrol_new wm5100_snd_controls[] = {
SOC_SINGLE("IN1 High Performance Switch", WM5100_IN1L_CONTROL,
WM5100_IN1_OSR_SHIFT, 1, 0),
SOC_SINGLE("IN2 High Performance Switch", WM5100_IN2L_CONTROL,
WM5100_IN2_OSR_SHIFT, 1, 0),
SOC_SINGLE("IN3 High Performance Switch", WM5100_IN3L_CONTROL,
WM5100_IN3_OSR_SHIFT, 1, 0),
SOC_SINGLE("IN4 High Performance Switch", WM5100_IN4L_CONTROL,
WM5100_IN4_OSR_SHIFT, 1, 0),
/* Only applicable for analogue inputs */
SOC_DOUBLE_R_TLV("IN1 Volume", WM5100_IN1L_CONTROL, WM5100_IN1R_CONTROL,
WM5100_IN1L_PGA_VOL_SHIFT, 94, 0, in_tlv),
SOC_DOUBLE_R_TLV("IN2 Volume", WM5100_IN2L_CONTROL, WM5100_IN2R_CONTROL,
WM5100_IN2L_PGA_VOL_SHIFT, 94, 0, in_tlv),
SOC_DOUBLE_R_TLV("IN3 Volume", WM5100_IN3L_CONTROL, WM5100_IN3R_CONTROL,
WM5100_IN3L_PGA_VOL_SHIFT, 94, 0, in_tlv),
SOC_DOUBLE_R_TLV("IN4 Volume", WM5100_IN4L_CONTROL, WM5100_IN4R_CONTROL,
WM5100_IN4L_PGA_VOL_SHIFT, 94, 0, in_tlv),
SOC_DOUBLE_R_TLV("IN1 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_1L,
WM5100_ADC_DIGITAL_VOLUME_1R, WM5100_IN1L_VOL_SHIFT, 191,
0, digital_tlv),
SOC_DOUBLE_R_TLV("IN2 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_2L,
WM5100_ADC_DIGITAL_VOLUME_2R, WM5100_IN2L_VOL_SHIFT, 191,
0, digital_tlv),
SOC_DOUBLE_R_TLV("IN3 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_3L,
WM5100_ADC_DIGITAL_VOLUME_3R, WM5100_IN3L_VOL_SHIFT, 191,
0, digital_tlv),
SOC_DOUBLE_R_TLV("IN4 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_4L,
WM5100_ADC_DIGITAL_VOLUME_4R, WM5100_IN4L_VOL_SHIFT, 191,
0, digital_tlv),
SOC_DOUBLE_R("IN1 Switch", WM5100_ADC_DIGITAL_VOLUME_1L,
WM5100_ADC_DIGITAL_VOLUME_1R, WM5100_IN1L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R("IN2 Switch", WM5100_ADC_DIGITAL_VOLUME_2L,
WM5100_ADC_DIGITAL_VOLUME_2R, WM5100_IN2L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R("IN3 Switch", WM5100_ADC_DIGITAL_VOLUME_3L,
WM5100_ADC_DIGITAL_VOLUME_3R, WM5100_IN3L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R("IN4 Switch", WM5100_ADC_DIGITAL_VOLUME_4L,
WM5100_ADC_DIGITAL_VOLUME_4R, WM5100_IN4L_MUTE_SHIFT, 1, 1),
SND_SOC_BYTES_MASK("EQ1 Coefficients", WM5100_EQ1_1, 20, WM5100_EQ1_ENA),
SND_SOC_BYTES_MASK("EQ2 Coefficients", WM5100_EQ2_1, 20, WM5100_EQ2_ENA),
SND_SOC_BYTES_MASK("EQ3 Coefficients", WM5100_EQ3_1, 20, WM5100_EQ3_ENA),
SND_SOC_BYTES_MASK("EQ4 Coefficients", WM5100_EQ4_1, 20, WM5100_EQ4_ENA),
SND_SOC_BYTES_MASK("DRC Coefficients", WM5100_DRC1_CTRL1, 5,
WM5100_DRCL_ENA | WM5100_DRCR_ENA),
SND_SOC_BYTES("LHPF1 Coefficients", WM5100_HPLPF1_2, 1),
SND_SOC_BYTES("LHPF2 Coefficients", WM5100_HPLPF2_2, 1),
SND_SOC_BYTES("LHPF3 Coefficients", WM5100_HPLPF3_2, 1),
SND_SOC_BYTES("LHPF4 Coefficients", WM5100_HPLPF4_2, 1),
SOC_SINGLE("HPOUT1 High Performance Switch", WM5100_OUT_VOLUME_1L,
WM5100_OUT1_OSR_SHIFT, 1, 0),
SOC_SINGLE("HPOUT2 High Performance Switch", WM5100_OUT_VOLUME_2L,
WM5100_OUT2_OSR_SHIFT, 1, 0),
SOC_SINGLE("HPOUT3 High Performance Switch", WM5100_OUT_VOLUME_3L,
WM5100_OUT3_OSR_SHIFT, 1, 0),
SOC_SINGLE("SPKOUT High Performance Switch", WM5100_OUT_VOLUME_4L,
WM5100_OUT4_OSR_SHIFT, 1, 0),
SOC_SINGLE("SPKDAT1 High Performance Switch", WM5100_DAC_VOLUME_LIMIT_5L,
WM5100_OUT5_OSR_SHIFT, 1, 0),
SOC_SINGLE("SPKDAT2 High Performance Switch", WM5100_DAC_VOLUME_LIMIT_6L,
WM5100_OUT6_OSR_SHIFT, 1, 0),
SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_1L,
WM5100_DAC_DIGITAL_VOLUME_1R, WM5100_OUT1L_VOL_SHIFT, 159, 0,
digital_tlv),
SOC_DOUBLE_R_TLV("HPOUT2 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_2L,
WM5100_DAC_DIGITAL_VOLUME_2R, WM5100_OUT2L_VOL_SHIFT, 159, 0,
digital_tlv),
SOC_DOUBLE_R_TLV("HPOUT3 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_3L,
WM5100_DAC_DIGITAL_VOLUME_3R, WM5100_OUT3L_VOL_SHIFT, 159, 0,
digital_tlv),
SOC_DOUBLE_R_TLV("SPKOUT Digital Volume", WM5100_DAC_DIGITAL_VOLUME_4L,
WM5100_DAC_DIGITAL_VOLUME_4R, WM5100_OUT4L_VOL_SHIFT, 159, 0,
digital_tlv),
SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_5L,
WM5100_DAC_DIGITAL_VOLUME_5R, WM5100_OUT5L_VOL_SHIFT, 159, 0,
digital_tlv),
SOC_DOUBLE_R_TLV("SPKDAT2 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_6L,
WM5100_DAC_DIGITAL_VOLUME_6R, WM5100_OUT6L_VOL_SHIFT, 159, 0,
digital_tlv),
SOC_DOUBLE_R("HPOUT1 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_1L,
WM5100_DAC_DIGITAL_VOLUME_1R, WM5100_OUT1L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R("HPOUT2 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_2L,
WM5100_DAC_DIGITAL_VOLUME_2R, WM5100_OUT2L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R("HPOUT3 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_3L,
WM5100_DAC_DIGITAL_VOLUME_3R, WM5100_OUT3L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R("SPKOUT Digital Switch", WM5100_DAC_DIGITAL_VOLUME_4L,
WM5100_DAC_DIGITAL_VOLUME_4R, WM5100_OUT4L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R("SPKDAT1 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_5L,
WM5100_DAC_DIGITAL_VOLUME_5R, WM5100_OUT5L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R("SPKDAT2 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_6L,
WM5100_DAC_DIGITAL_VOLUME_6R, WM5100_OUT6L_MUTE_SHIFT, 1, 1),
/* FIXME: Only valid from -12dB to 0dB (52-64) */
SOC_DOUBLE_R_TLV("HPOUT1 Volume", WM5100_OUT_VOLUME_1L, WM5100_OUT_VOLUME_1R,
WM5100_OUT1L_PGA_VOL_SHIFT, 64, 0, out_tlv),
SOC_DOUBLE_R_TLV("HPOUT2 Volume", WM5100_OUT_VOLUME_2L, WM5100_OUT_VOLUME_2R,
WM5100_OUT2L_PGA_VOL_SHIFT, 64, 0, out_tlv),
SOC_DOUBLE_R_TLV("HPOUT3 Volume", WM5100_OUT_VOLUME_3L, WM5100_OUT_VOLUME_3R,
WM5100_OUT2L_PGA_VOL_SHIFT, 64, 0, out_tlv),
SOC_DOUBLE("SPKDAT1 Switch", WM5100_PDM_SPK1_CTRL_1, WM5100_SPK1L_MUTE_SHIFT,
WM5100_SPK1R_MUTE_SHIFT, 1, 1),
SOC_DOUBLE("SPKDAT2 Switch", WM5100_PDM_SPK2_CTRL_1, WM5100_SPK2L_MUTE_SHIFT,
WM5100_SPK2R_MUTE_SHIFT, 1, 1),
SOC_SINGLE_TLV("EQ1 Band 1 Volume", WM5100_EQ1_1, WM5100_EQ1_B1_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ1 Band 2 Volume", WM5100_EQ1_1, WM5100_EQ1_B2_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ1 Band 3 Volume", WM5100_EQ1_1, WM5100_EQ1_B3_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ1 Band 4 Volume", WM5100_EQ1_2, WM5100_EQ1_B4_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ1 Band 5 Volume", WM5100_EQ1_2, WM5100_EQ1_B5_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ2 Band 1 Volume", WM5100_EQ2_1, WM5100_EQ2_B1_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ2 Band 2 Volume", WM5100_EQ2_1, WM5100_EQ2_B2_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ2 Band 3 Volume", WM5100_EQ2_1, WM5100_EQ2_B3_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ2 Band 4 Volume", WM5100_EQ2_2, WM5100_EQ2_B4_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ2 Band 5 Volume", WM5100_EQ2_2, WM5100_EQ2_B5_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ3 Band 1 Volume", WM5100_EQ1_1, WM5100_EQ3_B1_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ3 Band 2 Volume", WM5100_EQ3_1, WM5100_EQ3_B2_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ3 Band 3 Volume", WM5100_EQ3_1, WM5100_EQ3_B3_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ3 Band 4 Volume", WM5100_EQ3_2, WM5100_EQ3_B4_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ3 Band 5 Volume", WM5100_EQ3_2, WM5100_EQ3_B5_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ4 Band 1 Volume", WM5100_EQ4_1, WM5100_EQ4_B1_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ4 Band 2 Volume", WM5100_EQ4_1, WM5100_EQ4_B2_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ4 Band 3 Volume", WM5100_EQ4_1, WM5100_EQ4_B3_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ4 Band 4 Volume", WM5100_EQ4_2, WM5100_EQ4_B4_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ4 Band 5 Volume", WM5100_EQ4_2, WM5100_EQ4_B5_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_ENUM("LHPF1 Mode", wm5100_lhpf1_mode),
SOC_ENUM("LHPF2 Mode", wm5100_lhpf2_mode),
SOC_ENUM("LHPF3 Mode", wm5100_lhpf3_mode),
SOC_ENUM("LHPF4 Mode", wm5100_lhpf4_mode),
WM5100_MIXER_CONTROLS("HPOUT1L", WM5100_OUT1LMIX_INPUT_1_SOURCE),
WM5100_MIXER_CONTROLS("HPOUT1R", WM5100_OUT1RMIX_INPUT_1_SOURCE),
WM5100_MIXER_CONTROLS("HPOUT2L", WM5100_OUT2LMIX_INPUT_1_SOURCE),
WM5100_MIXER_CONTROLS("HPOUT2R", WM5100_OUT2RMIX_INPUT_1_SOURCE),
WM5100_MIXER_CONTROLS("HPOUT3L", WM5100_OUT3LMIX_INPUT_1_SOURCE),
WM5100_MIXER_CONTROLS("HPOUT3R", WM5100_OUT3RMIX_INPUT_1_SOURCE),
WM5100_MIXER_CONTROLS("SPKOUTL", WM5100_OUT4LMIX_INPUT_1_SOURCE),
WM5100_MIXER_CONTROLS("SPKOUTR", WM5100_OUT4RMIX_INPUT_1_SOURCE),
WM5100_MIXER_CONTROLS("SPKDAT1L", WM5100_OUT5LMIX_INPUT_1_SOURCE),
WM5100_MIXER_CONTROLS("SPKDAT1R", WM5100_OUT5RMIX_INPUT_1_SOURCE),
WM5100_MIXER_CONTROLS("SPKDAT2L", WM5100_OUT6LMIX_INPUT_1_SOURCE),
WM5100_MIXER_CONTROLS("SPKDAT2R", WM5100_OUT6RMIX_INPUT_1_SOURCE),
WM5100_MIXER_CONTROLS("PWM1", WM5100_PWM1MIX_INPUT_1_SOURCE),
WM5100_MIXER_CONTROLS("PWM2", WM5100_PWM2MIX_INPUT_1_SOURCE),
WM5100_MIXER_CONTROLS("AIF1TX1", WM5100_AIF1TX1MIX_INPUT_1_SOURCE),
WM5100_MIXER_CONTROLS("AIF1TX2", WM5100_AIF1TX2MIX_INPUT_1_SOURCE),
WM5100_MIXER_CONTROLS("AIF1TX3", WM5100_AIF1TX3MIX_INPUT_1_SOURCE),
WM5100_MIXER_CONTROLS("AIF1TX4", WM5100_AIF1TX4MIX_INPUT_1_SOURCE),
WM5100_MIXER_CONTROLS("AIF1TX5", WM5100_AIF1TX5MIX_INPUT_1_SOURCE),
WM5100_MIXER_CONTROLS("AIF1TX6", WM5100_AIF1TX6MIX_INPUT_1_SOURCE),
WM5100_MIXER_CONTROLS("AIF1TX7", WM5100_AIF1TX7MIX_INPUT_1_SOURCE),
WM5100_MIXER_CONTROLS("AIF1TX8", WM5100_AIF1TX8MIX_INPUT_1_SOURCE),
WM5100_MIXER_CONTROLS("AIF2TX1", WM5100_AIF2TX1MIX_INPUT_1_SOURCE),
WM5100_MIXER_CONTROLS("AIF2TX2", WM5100_AIF2TX2MIX_INPUT_1_SOURCE),
WM5100_MIXER_CONTROLS("AIF3TX1", WM5100_AIF3TX1MIX_INPUT_1_SOURCE),
WM5100_MIXER_CONTROLS("AIF3TX2", WM5100_AIF3TX2MIX_INPUT_1_SOURCE),
WM5100_MIXER_CONTROLS("EQ1", WM5100_EQ1MIX_INPUT_1_SOURCE),
WM5100_MIXER_CONTROLS("EQ2", WM5100_EQ2MIX_INPUT_1_SOURCE),
WM5100_MIXER_CONTROLS("EQ3", WM5100_EQ3MIX_INPUT_1_SOURCE),
WM5100_MIXER_CONTROLS("EQ4", WM5100_EQ4MIX_INPUT_1_SOURCE),
WM5100_MIXER_CONTROLS("DRC1L", WM5100_DRC1LMIX_INPUT_1_SOURCE),
WM5100_MIXER_CONTROLS("DRC1R", WM5100_DRC1RMIX_INPUT_1_SOURCE),
SND_SOC_BYTES_MASK("DRC", WM5100_DRC1_CTRL1, 5,
WM5100_DRCL_ENA | WM5100_DRCR_ENA),
WM5100_MIXER_CONTROLS("LHPF1", WM5100_HPLP1MIX_INPUT_1_SOURCE),
WM5100_MIXER_CONTROLS("LHPF2", WM5100_HPLP2MIX_INPUT_1_SOURCE),
WM5100_MIXER_CONTROLS("LHPF3", WM5100_HPLP3MIX_INPUT_1_SOURCE),
WM5100_MIXER_CONTROLS("LHPF4", WM5100_HPLP4MIX_INPUT_1_SOURCE),
};
static void wm5100_seq_notifier(struct snd_soc_component *component,
enum snd_soc_dapm_type event, int subseq)
{
struct wm5100_priv *wm5100 = snd_soc_component_get_drvdata(component);
u16 val, expect, i;
/* Wait for the outputs to flag themselves as enabled */
if (wm5100->out_ena[0]) {
expect = snd_soc_component_read(component, WM5100_CHANNEL_ENABLES_1);
for (i = 0; i < 200; i++) {
val = snd_soc_component_read(component, WM5100_OUTPUT_STATUS_1);
if (val == expect) {
wm5100->out_ena[0] = false;
break;
}
}
if (i == 200) {
dev_err(component->dev, "Timeout waiting for OUTPUT1 %x\n",
expect);
}
}
if (wm5100->out_ena[1]) {
expect = snd_soc_component_read(component, WM5100_OUTPUT_ENABLES_2);
for (i = 0; i < 200; i++) {
val = snd_soc_component_read(component, WM5100_OUTPUT_STATUS_2);
if (val == expect) {
wm5100->out_ena[1] = false;
break;
}
}
if (i == 200) {
dev_err(component->dev, "Timeout waiting for OUTPUT2 %x\n",
expect);
}
}
}
static int wm5100_out_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wm5100_priv *wm5100 = snd_soc_component_get_drvdata(component);
switch (w->reg) {
case WM5100_CHANNEL_ENABLES_1:
wm5100->out_ena[0] = true;
break;
case WM5100_OUTPUT_ENABLES_2:
wm5100->out_ena[0] = true;
break;
default:
break;
}
return 0;
}
static void wm5100_log_status3(struct wm5100_priv *wm5100, int val)
{
if (val & WM5100_SPK_SHUTDOWN_WARN_EINT)
dev_crit(wm5100->dev, "Speaker shutdown warning\n");
if (val & WM5100_SPK_SHUTDOWN_EINT)
dev_crit(wm5100->dev, "Speaker shutdown\n");
if (val & WM5100_CLKGEN_ERR_EINT)
dev_crit(wm5100->dev, "SYSCLK underclocked\n");
if (val & WM5100_CLKGEN_ERR_ASYNC_EINT)
dev_crit(wm5100->dev, "ASYNCCLK underclocked\n");
}
static void wm5100_log_status4(struct wm5100_priv *wm5100, int val)
{
if (val & WM5100_AIF3_ERR_EINT)
dev_err(wm5100->dev, "AIF3 configuration error\n");
if (val & WM5100_AIF2_ERR_EINT)
dev_err(wm5100->dev, "AIF2 configuration error\n");
if (val & WM5100_AIF1_ERR_EINT)
dev_err(wm5100->dev, "AIF1 configuration error\n");
if (val & WM5100_CTRLIF_ERR_EINT)
dev_err(wm5100->dev, "Control interface error\n");
if (val & WM5100_ISRC2_UNDERCLOCKED_EINT)
dev_err(wm5100->dev, "ISRC2 underclocked\n");
if (val & WM5100_ISRC1_UNDERCLOCKED_EINT)
dev_err(wm5100->dev, "ISRC1 underclocked\n");
if (val & WM5100_FX_UNDERCLOCKED_EINT)
dev_err(wm5100->dev, "FX underclocked\n");
if (val & WM5100_AIF3_UNDERCLOCKED_EINT)
dev_err(wm5100->dev, "AIF3 underclocked\n");
if (val & WM5100_AIF2_UNDERCLOCKED_EINT)
dev_err(wm5100->dev, "AIF2 underclocked\n");
if (val & WM5100_AIF1_UNDERCLOCKED_EINT)
dev_err(wm5100->dev, "AIF1 underclocked\n");
if (val & WM5100_ASRC_UNDERCLOCKED_EINT)
dev_err(wm5100->dev, "ASRC underclocked\n");
if (val & WM5100_DAC_UNDERCLOCKED_EINT)
dev_err(wm5100->dev, "DAC underclocked\n");
if (val & WM5100_ADC_UNDERCLOCKED_EINT)
dev_err(wm5100->dev, "ADC underclocked\n");
if (val & WM5100_MIXER_UNDERCLOCKED_EINT)
dev_err(wm5100->dev, "Mixer underclocked\n");
}
static int wm5100_post_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wm5100_priv *wm5100 = snd_soc_component_get_drvdata(component);
int ret;
ret = snd_soc_component_read(component, WM5100_INTERRUPT_RAW_STATUS_3);
ret &= WM5100_SPK_SHUTDOWN_WARN_STS |
WM5100_SPK_SHUTDOWN_STS | WM5100_CLKGEN_ERR_STS |
WM5100_CLKGEN_ERR_ASYNC_STS;
wm5100_log_status3(wm5100, ret);
ret = snd_soc_component_read(component, WM5100_INTERRUPT_RAW_STATUS_4);
wm5100_log_status4(wm5100, ret);
return 0;
}
static const struct snd_soc_dapm_widget wm5100_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("SYSCLK", WM5100_CLOCKING_3, WM5100_SYSCLK_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("ASYNCCLK", WM5100_CLOCKING_6, WM5100_ASYNC_CLK_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD2", 0, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD3", 0, 0),
SND_SOC_DAPM_SUPPLY("CP1", WM5100_HP_CHARGE_PUMP_1, WM5100_CP1_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("CP2", WM5100_MIC_CHARGE_PUMP_1, WM5100_CP2_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("CP2 Active", WM5100_MIC_CHARGE_PUMP_1,
WM5100_CP2_BYPASS_SHIFT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS1", WM5100_MIC_BIAS_CTRL_1, WM5100_MICB1_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS2", WM5100_MIC_BIAS_CTRL_2, WM5100_MICB2_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS3", WM5100_MIC_BIAS_CTRL_3, WM5100_MICB3_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_INPUT("IN1L"),
SND_SOC_DAPM_INPUT("IN1R"),
SND_SOC_DAPM_INPUT("IN2L"),
SND_SOC_DAPM_INPUT("IN2R"),
SND_SOC_DAPM_INPUT("IN3L"),
SND_SOC_DAPM_INPUT("IN3R"),
SND_SOC_DAPM_INPUT("IN4L"),
SND_SOC_DAPM_INPUT("IN4R"),
SND_SOC_DAPM_SIGGEN("TONE"),
SND_SOC_DAPM_PGA_E("IN1L PGA", WM5100_INPUT_ENABLES, WM5100_IN1L_ENA_SHIFT, 0,
NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN1R PGA", WM5100_INPUT_ENABLES, WM5100_IN1R_ENA_SHIFT, 0,
NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN2L PGA", WM5100_INPUT_ENABLES, WM5100_IN2L_ENA_SHIFT, 0,
NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN2R PGA", WM5100_INPUT_ENABLES, WM5100_IN2R_ENA_SHIFT, 0,
NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN3L PGA", WM5100_INPUT_ENABLES, WM5100_IN3L_ENA_SHIFT, 0,
NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN3R PGA", WM5100_INPUT_ENABLES, WM5100_IN3R_ENA_SHIFT, 0,
NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN4L PGA", WM5100_INPUT_ENABLES, WM5100_IN4L_ENA_SHIFT, 0,
NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN4R PGA", WM5100_INPUT_ENABLES, WM5100_IN4R_ENA_SHIFT, 0,
NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA("Tone Generator 1", WM5100_TONE_GENERATOR_1,
WM5100_TONE1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("Tone Generator 2", WM5100_TONE_GENERATOR_1,
WM5100_TONE2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 0,
WM5100_AUDIO_IF_1_27, WM5100_AIF1RX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 1,
WM5100_AUDIO_IF_1_27, WM5100_AIF1RX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 2,
WM5100_AUDIO_IF_1_27, WM5100_AIF1RX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 3,
WM5100_AUDIO_IF_1_27, WM5100_AIF1RX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 4,
WM5100_AUDIO_IF_1_27, WM5100_AIF1RX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX6", "AIF1 Playback", 5,
WM5100_AUDIO_IF_1_27, WM5100_AIF1RX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX7", "AIF1 Playback", 6,
WM5100_AUDIO_IF_1_27, WM5100_AIF1RX7_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX8", "AIF1 Playback", 7,
WM5100_AUDIO_IF_1_27, WM5100_AIF1RX8_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 0,
WM5100_AUDIO_IF_2_27, WM5100_AIF2RX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX2", "AIF2 Playback", 1,
WM5100_AUDIO_IF_2_27, WM5100_AIF2RX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF3RX1", "AIF3 Playback", 0,
WM5100_AUDIO_IF_3_27, WM5100_AIF3RX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF3RX2", "AIF3 Playback", 1,
WM5100_AUDIO_IF_3_27, WM5100_AIF3RX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 0,
WM5100_AUDIO_IF_1_26, WM5100_AIF1TX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 1,
WM5100_AUDIO_IF_1_26, WM5100_AIF1TX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 2,
WM5100_AUDIO_IF_1_26, WM5100_AIF1TX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 3,
WM5100_AUDIO_IF_1_26, WM5100_AIF1TX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 4,
WM5100_AUDIO_IF_1_26, WM5100_AIF1TX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX6", "AIF1 Capture", 5,
WM5100_AUDIO_IF_1_26, WM5100_AIF1TX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX7", "AIF1 Capture", 6,
WM5100_AUDIO_IF_1_26, WM5100_AIF1TX7_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX8", "AIF1 Capture", 7,
WM5100_AUDIO_IF_1_26, WM5100_AIF1TX8_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX1", "AIF2 Capture", 0,
WM5100_AUDIO_IF_2_26, WM5100_AIF2TX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX2", "AIF2 Capture", 1,
WM5100_AUDIO_IF_2_26, WM5100_AIF2TX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF3TX1", "AIF3 Capture", 0,
WM5100_AUDIO_IF_3_26, WM5100_AIF3TX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF3TX2", "AIF3 Capture", 1,
WM5100_AUDIO_IF_3_26, WM5100_AIF3TX2_ENA_SHIFT, 0),
SND_SOC_DAPM_PGA_E("OUT6L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT6L_ENA_SHIFT, 0,
NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT6R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT6R_ENA_SHIFT, 0,
NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT5L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT5L_ENA_SHIFT, 0,
NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT5R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT5R_ENA_SHIFT, 0,
NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT4L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT4L_ENA_SHIFT, 0,
NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT4R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT4R_ENA_SHIFT, 0,
NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT3L", WM5100_CHANNEL_ENABLES_1, WM5100_HP3L_ENA_SHIFT, 0,
NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT3R", WM5100_CHANNEL_ENABLES_1, WM5100_HP3R_ENA_SHIFT, 0,
NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT2L", WM5100_CHANNEL_ENABLES_1, WM5100_HP2L_ENA_SHIFT, 0,
NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT2R", WM5100_CHANNEL_ENABLES_1, WM5100_HP2R_ENA_SHIFT, 0,
NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT1L", WM5100_CHANNEL_ENABLES_1, WM5100_HP1L_ENA_SHIFT, 0,
NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT1R", WM5100_CHANNEL_ENABLES_1, WM5100_HP1R_ENA_SHIFT, 0,
NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("PWM1 Driver", WM5100_PWM_DRIVE_1, WM5100_PWM1_ENA_SHIFT, 0,
NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("PWM2 Driver", WM5100_PWM_DRIVE_1, WM5100_PWM2_ENA_SHIFT, 0,
NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA("EQ1", WM5100_EQ1_1, WM5100_EQ1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ2", WM5100_EQ2_1, WM5100_EQ2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ3", WM5100_EQ3_1, WM5100_EQ3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ4", WM5100_EQ4_1, WM5100_EQ4_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("DRC1L", WM5100_DRC1_CTRL1, WM5100_DRCL_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("DRC1R", WM5100_DRC1_CTRL1, WM5100_DRCR_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF1", WM5100_HPLPF1_1, WM5100_LHPF1_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF2", WM5100_HPLPF2_1, WM5100_LHPF2_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF3", WM5100_HPLPF3_1, WM5100_LHPF3_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF4", WM5100_HPLPF4_1, WM5100_LHPF4_ENA_SHIFT, 0,
NULL, 0),
WM5100_MIXER_WIDGETS(EQ1, "EQ1"),
WM5100_MIXER_WIDGETS(EQ2, "EQ2"),
WM5100_MIXER_WIDGETS(EQ3, "EQ3"),
WM5100_MIXER_WIDGETS(EQ4, "EQ4"),
WM5100_MIXER_WIDGETS(DRC1L, "DRC1L"),
WM5100_MIXER_WIDGETS(DRC1R, "DRC1R"),
WM5100_MIXER_WIDGETS(LHPF1, "LHPF1"),
WM5100_MIXER_WIDGETS(LHPF2, "LHPF2"),
WM5100_MIXER_WIDGETS(LHPF3, "LHPF3"),
WM5100_MIXER_WIDGETS(LHPF4, "LHPF4"),
WM5100_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"),
WM5100_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"),
WM5100_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"),
WM5100_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"),
WM5100_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"),
WM5100_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"),
WM5100_MIXER_WIDGETS(AIF1TX7, "AIF1TX7"),
WM5100_MIXER_WIDGETS(AIF1TX8, "AIF1TX8"),
WM5100_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"),
WM5100_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"),
WM5100_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"),
WM5100_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"),
WM5100_MIXER_WIDGETS(HPOUT1L, "HPOUT1L"),
WM5100_MIXER_WIDGETS(HPOUT1R, "HPOUT1R"),
WM5100_MIXER_WIDGETS(HPOUT2L, "HPOUT2L"),
WM5100_MIXER_WIDGETS(HPOUT2R, "HPOUT2R"),
WM5100_MIXER_WIDGETS(HPOUT3L, "HPOUT3L"),
WM5100_MIXER_WIDGETS(HPOUT3R, "HPOUT3R"),
WM5100_MIXER_WIDGETS(SPKOUTL, "SPKOUTL"),
WM5100_MIXER_WIDGETS(SPKOUTR, "SPKOUTR"),
WM5100_MIXER_WIDGETS(SPKDAT1L, "SPKDAT1L"),
WM5100_MIXER_WIDGETS(SPKDAT1R, "SPKDAT1R"),
WM5100_MIXER_WIDGETS(SPKDAT2L, "SPKDAT2L"),
WM5100_MIXER_WIDGETS(SPKDAT2R, "SPKDAT2R"),
WM5100_MIXER_WIDGETS(PWM1, "PWM1"),
WM5100_MIXER_WIDGETS(PWM2, "PWM2"),
SND_SOC_DAPM_OUTPUT("HPOUT1L"),
SND_SOC_DAPM_OUTPUT("HPOUT1R"),
SND_SOC_DAPM_OUTPUT("HPOUT2L"),
SND_SOC_DAPM_OUTPUT("HPOUT2R"),
SND_SOC_DAPM_OUTPUT("HPOUT3L"),
SND_SOC_DAPM_OUTPUT("HPOUT3R"),
SND_SOC_DAPM_OUTPUT("SPKOUTL"),
SND_SOC_DAPM_OUTPUT("SPKOUTR"),
SND_SOC_DAPM_OUTPUT("SPKDAT1"),
SND_SOC_DAPM_OUTPUT("SPKDAT2"),
SND_SOC_DAPM_OUTPUT("PWM1"),
SND_SOC_DAPM_OUTPUT("PWM2"),
};
/* We register a _POST event if we don't have IRQ support so we can
* look at the error status from the CODEC - if we've got the IRQ
* hooked up then we will get prompted to look by an interrupt.
*/
static const struct snd_soc_dapm_widget wm5100_dapm_widgets_noirq[] = {
SND_SOC_DAPM_POST("Post", wm5100_post_ev),
};
static const struct snd_soc_dapm_route wm5100_dapm_routes[] = {
{ "CP1", NULL, "CPVDD" },
{ "CP2 Active", NULL, "CPVDD" },
{ "IN1L", NULL, "SYSCLK" },
{ "IN1R", NULL, "SYSCLK" },
{ "IN2L", NULL, "SYSCLK" },
{ "IN2R", NULL, "SYSCLK" },
{ "IN3L", NULL, "SYSCLK" },
{ "IN3R", NULL, "SYSCLK" },
{ "IN4L", NULL, "SYSCLK" },
{ "IN4R", NULL, "SYSCLK" },
{ "OUT1L", NULL, "SYSCLK" },
{ "OUT1R", NULL, "SYSCLK" },
{ "OUT2L", NULL, "SYSCLK" },
{ "OUT2R", NULL, "SYSCLK" },
{ "OUT3L", NULL, "SYSCLK" },
{ "OUT3R", NULL, "SYSCLK" },
{ "OUT4L", NULL, "SYSCLK" },
{ "OUT4R", NULL, "SYSCLK" },
{ "OUT5L", NULL, "SYSCLK" },
{ "OUT5R", NULL, "SYSCLK" },
{ "OUT6L", NULL, "SYSCLK" },
{ "OUT6R", NULL, "SYSCLK" },
{ "AIF1RX1", NULL, "SYSCLK" },
{ "AIF1RX2", NULL, "SYSCLK" },
{ "AIF1RX3", NULL, "SYSCLK" },
{ "AIF1RX4", NULL, "SYSCLK" },
{ "AIF1RX5", NULL, "SYSCLK" },
{ "AIF1RX6", NULL, "SYSCLK" },
{ "AIF1RX7", NULL, "SYSCLK" },
{ "AIF1RX8", NULL, "SYSCLK" },
{ "AIF2RX1", NULL, "SYSCLK" },
{ "AIF2RX1", NULL, "DBVDD2" },
{ "AIF2RX2", NULL, "SYSCLK" },
{ "AIF2RX2", NULL, "DBVDD2" },
{ "AIF3RX1", NULL, "SYSCLK" },
{ "AIF3RX1", NULL, "DBVDD3" },
{ "AIF3RX2", NULL, "SYSCLK" },
{ "AIF3RX2", NULL, "DBVDD3" },
{ "AIF1TX1", NULL, "SYSCLK" },
{ "AIF1TX2", NULL, "SYSCLK" },
{ "AIF1TX3", NULL, "SYSCLK" },
{ "AIF1TX4", NULL, "SYSCLK" },
{ "AIF1TX5", NULL, "SYSCLK" },
{ "AIF1TX6", NULL, "SYSCLK" },
{ "AIF1TX7", NULL, "SYSCLK" },
{ "AIF1TX8", NULL, "SYSCLK" },
{ "AIF2TX1", NULL, "SYSCLK" },
{ "AIF2TX1", NULL, "DBVDD2" },
{ "AIF2TX2", NULL, "SYSCLK" },
{ "AIF2TX2", NULL, "DBVDD2" },
{ "AIF3TX1", NULL, "SYSCLK" },
{ "AIF3TX1", NULL, "DBVDD3" },
{ "AIF3TX2", NULL, "SYSCLK" },
{ "AIF3TX2", NULL, "DBVDD3" },
{ "MICBIAS1", NULL, "CP2" },
{ "MICBIAS2", NULL, "CP2" },
{ "MICBIAS3", NULL, "CP2" },
{ "IN1L PGA", NULL, "CP2" },
{ "IN1R PGA", NULL, "CP2" },
{ "IN2L PGA", NULL, "CP2" },
{ "IN2R PGA", NULL, "CP2" },
{ "IN3L PGA", NULL, "CP2" },
{ "IN3R PGA", NULL, "CP2" },
{ "IN4L PGA", NULL, "CP2" },
{ "IN4R PGA", NULL, "CP2" },
{ "IN1L PGA", NULL, "CP2 Active" },
{ "IN1R PGA", NULL, "CP2 Active" },
{ "IN2L PGA", NULL, "CP2 Active" },
{ "IN2R PGA", NULL, "CP2 Active" },
{ "IN3L PGA", NULL, "CP2 Active" },
{ "IN3R PGA", NULL, "CP2 Active" },
{ "IN4L PGA", NULL, "CP2 Active" },
{ "IN4R PGA", NULL, "CP2 Active" },
{ "OUT1L", NULL, "CP1" },
{ "OUT1R", NULL, "CP1" },
{ "OUT2L", NULL, "CP1" },
{ "OUT2R", NULL, "CP1" },
{ "OUT3L", NULL, "CP1" },
{ "OUT3R", NULL, "CP1" },
{ "Tone Generator 1", NULL, "TONE" },
{ "Tone Generator 2", NULL, "TONE" },
{ "IN1L PGA", NULL, "IN1L" },
{ "IN1R PGA", NULL, "IN1R" },
{ "IN2L PGA", NULL, "IN2L" },
{ "IN2R PGA", NULL, "IN2R" },
{ "IN3L PGA", NULL, "IN3L" },
{ "IN3R PGA", NULL, "IN3R" },
{ "IN4L PGA", NULL, "IN4L" },
{ "IN4R PGA", NULL, "IN4R" },
WM5100_MIXER_ROUTES("OUT1L", "HPOUT1L"),
WM5100_MIXER_ROUTES("OUT1R", "HPOUT1R"),
WM5100_MIXER_ROUTES("OUT2L", "HPOUT2L"),
WM5100_MIXER_ROUTES("OUT2R", "HPOUT2R"),
WM5100_MIXER_ROUTES("OUT3L", "HPOUT3L"),
WM5100_MIXER_ROUTES("OUT3R", "HPOUT3R"),
WM5100_MIXER_ROUTES("OUT4L", "SPKOUTL"),
WM5100_MIXER_ROUTES("OUT4R", "SPKOUTR"),
WM5100_MIXER_ROUTES("OUT5L", "SPKDAT1L"),
WM5100_MIXER_ROUTES("OUT5R", "SPKDAT1R"),
WM5100_MIXER_ROUTES("OUT6L", "SPKDAT2L"),
WM5100_MIXER_ROUTES("OUT6R", "SPKDAT2R"),
WM5100_MIXER_ROUTES("PWM1 Driver", "PWM1"),
WM5100_MIXER_ROUTES("PWM2 Driver", "PWM2"),
WM5100_MIXER_ROUTES("AIF1TX1", "AIF1TX1"),
WM5100_MIXER_ROUTES("AIF1TX2", "AIF1TX2"),
WM5100_MIXER_ROUTES("AIF1TX3", "AIF1TX3"),
WM5100_MIXER_ROUTES("AIF1TX4", "AIF1TX4"),
WM5100_MIXER_ROUTES("AIF1TX5", "AIF1TX5"),
WM5100_MIXER_ROUTES("AIF1TX6", "AIF1TX6"),
WM5100_MIXER_ROUTES("AIF1TX7", "AIF1TX7"),
WM5100_MIXER_ROUTES("AIF1TX8", "AIF1TX8"),
WM5100_MIXER_ROUTES("AIF2TX1", "AIF2TX1"),
WM5100_MIXER_ROUTES("AIF2TX2", "AIF2TX2"),
WM5100_MIXER_ROUTES("AIF3TX1", "AIF3TX1"),
WM5100_MIXER_ROUTES("AIF3TX2", "AIF3TX2"),
WM5100_MIXER_ROUTES("EQ1", "EQ1"),
WM5100_MIXER_ROUTES("EQ2", "EQ2"),
WM5100_MIXER_ROUTES("EQ3", "EQ3"),
WM5100_MIXER_ROUTES("EQ4", "EQ4"),
WM5100_MIXER_ROUTES("DRC1L", "DRC1L"),
WM5100_MIXER_ROUTES("DRC1R", "DRC1R"),
WM5100_MIXER_ROUTES("LHPF1", "LHPF1"),
WM5100_MIXER_ROUTES("LHPF2", "LHPF2"),
WM5100_MIXER_ROUTES("LHPF3", "LHPF3"),
WM5100_MIXER_ROUTES("LHPF4", "LHPF4"),
{ "HPOUT1L", NULL, "OUT1L" },
{ "HPOUT1R", NULL, "OUT1R" },
{ "HPOUT2L", NULL, "OUT2L" },
{ "HPOUT2R", NULL, "OUT2R" },
{ "HPOUT3L", NULL, "OUT3L" },
{ "HPOUT3R", NULL, "OUT3R" },
{ "SPKOUTL", NULL, "OUT4L" },
{ "SPKOUTR", NULL, "OUT4R" },
{ "SPKDAT1", NULL, "OUT5L" },
{ "SPKDAT1", NULL, "OUT5R" },
{ "SPKDAT2", NULL, "OUT6L" },
{ "SPKDAT2", NULL, "OUT6R" },
{ "PWM1", NULL, "PWM1 Driver" },
{ "PWM2", NULL, "PWM2 Driver" },
};
static const struct reg_sequence wm5100_reva_patches[] = {
{ WM5100_AUDIO_IF_1_10, 0 },
{ WM5100_AUDIO_IF_1_11, 1 },
{ WM5100_AUDIO_IF_1_12, 2 },
{ WM5100_AUDIO_IF_1_13, 3 },
{ WM5100_AUDIO_IF_1_14, 4 },
{ WM5100_AUDIO_IF_1_15, 5 },
{ WM5100_AUDIO_IF_1_16, 6 },
{ WM5100_AUDIO_IF_1_17, 7 },
{ WM5100_AUDIO_IF_1_18, 0 },
{ WM5100_AUDIO_IF_1_19, 1 },
{ WM5100_AUDIO_IF_1_20, 2 },
{ WM5100_AUDIO_IF_1_21, 3 },
{ WM5100_AUDIO_IF_1_22, 4 },
{ WM5100_AUDIO_IF_1_23, 5 },
{ WM5100_AUDIO_IF_1_24, 6 },
{ WM5100_AUDIO_IF_1_25, 7 },
{ WM5100_AUDIO_IF_2_10, 0 },
{ WM5100_AUDIO_IF_2_11, 1 },
{ WM5100_AUDIO_IF_2_18, 0 },
{ WM5100_AUDIO_IF_2_19, 1 },
{ WM5100_AUDIO_IF_3_10, 0 },
{ WM5100_AUDIO_IF_3_11, 1 },
{ WM5100_AUDIO_IF_3_18, 0 },
{ WM5100_AUDIO_IF_3_19, 1 },
};
static int wm5100_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
int lrclk, bclk, mask, base;
base = dai->driver->base;
lrclk = 0;
bclk = 0;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
mask = 0;
break;
case SND_SOC_DAIFMT_I2S:
mask = 2;
break;
default:
dev_err(component->dev, "Unsupported DAI format %d\n",
fmt & SND_SOC_DAIFMT_FORMAT_MASK);
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
break;
case SND_SOC_DAIFMT_CBS_CFM:
lrclk |= WM5100_AIF1TX_LRCLK_MSTR;
break;
case SND_SOC_DAIFMT_CBM_CFS:
bclk |= WM5100_AIF1_BCLK_MSTR;
break;
case SND_SOC_DAIFMT_CBM_CFM:
lrclk |= WM5100_AIF1TX_LRCLK_MSTR;
bclk |= WM5100_AIF1_BCLK_MSTR;
break;
default:
dev_err(component->dev, "Unsupported master mode %d\n",
fmt & SND_SOC_DAIFMT_MASTER_MASK);
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
bclk |= WM5100_AIF1_BCLK_INV;
lrclk |= WM5100_AIF1TX_LRCLK_INV;
break;
case SND_SOC_DAIFMT_IB_NF:
bclk |= WM5100_AIF1_BCLK_INV;
break;
case SND_SOC_DAIFMT_NB_IF:
lrclk |= WM5100_AIF1TX_LRCLK_INV;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, base + 1, WM5100_AIF1_BCLK_MSTR |
WM5100_AIF1_BCLK_INV, bclk);
snd_soc_component_update_bits(component, base + 2, WM5100_AIF1TX_LRCLK_MSTR |
WM5100_AIF1TX_LRCLK_INV, lrclk);
snd_soc_component_update_bits(component, base + 3, WM5100_AIF1TX_LRCLK_MSTR |
WM5100_AIF1TX_LRCLK_INV, lrclk);
snd_soc_component_update_bits(component, base + 5, WM5100_AIF1_FMT_MASK, mask);
return 0;
}
#define WM5100_NUM_BCLK_RATES 19
static int wm5100_bclk_rates_dat[WM5100_NUM_BCLK_RATES] = {
32000,
48000,
64000,
96000,
128000,
192000,
256000,
384000,
512000,
768000,
1024000,
1536000,
2048000,
3072000,
4096000,
6144000,
8192000,
12288000,
24576000,
};
static int wm5100_bclk_rates_cd[WM5100_NUM_BCLK_RATES] = {
29400,
44100,
58800,
88200,
117600,
176400,
235200,
352800,
470400,
705600,
940800,
1411200,
1881600,
2882400,
3763200,
5644800,
7526400,
11289600,
22579600,
};
static int wm5100_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm5100_priv *wm5100 = snd_soc_component_get_drvdata(component);
bool async = wm5100->aif_async[dai->id];
int i, base, bclk, aif_rate, lrclk, wl, fl, sr;
int *bclk_rates;
base = dai->driver->base;
/* Data sizes if not using TDM */
wl = params_width(params);
if (wl < 0)
return wl;
fl = snd_soc_params_to_frame_size(params);
if (fl < 0)
return fl;
dev_dbg(component->dev, "Word length %d bits, frame length %d bits\n",
wl, fl);
/* Target BCLK rate */
bclk = snd_soc_params_to_bclk(params);
if (bclk < 0)
return bclk;
/* Root for BCLK depends on SYS/ASYNCCLK */
if (!async) {
aif_rate = wm5100->sysclk;
sr = wm5100_alloc_sr(component, params_rate(params));
if (sr < 0)
return sr;
} else {
/* If we're in ASYNCCLK set the ASYNC sample rate */
aif_rate = wm5100->asyncclk;
sr = 3;
for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
if (params_rate(params) == wm5100_sr_code[i])
break;
if (i == ARRAY_SIZE(wm5100_sr_code)) {
dev_err(component->dev, "Invalid rate %dHzn",
params_rate(params));
return -EINVAL;
}
/* TODO: We should really check for symmetry */
snd_soc_component_update_bits(component, WM5100_CLOCKING_8,
WM5100_ASYNC_SAMPLE_RATE_MASK, i);
}
if (!aif_rate) {
dev_err(component->dev, "%s has no rate set\n",
async ? "ASYNCCLK" : "SYSCLK");
return -EINVAL;
}
dev_dbg(component->dev, "Target BCLK is %dHz, using %dHz %s\n",
bclk, aif_rate, async ? "ASYNCCLK" : "SYSCLK");
if (aif_rate % 4000)
bclk_rates = wm5100_bclk_rates_cd;
else
bclk_rates = wm5100_bclk_rates_dat;
for (i = 0; i < WM5100_NUM_BCLK_RATES; i++)
if (bclk_rates[i] >= bclk && (bclk_rates[i] % bclk == 0))
break;
if (i == WM5100_NUM_BCLK_RATES) {
dev_err(component->dev,
"No valid BCLK for %dHz found from %dHz %s\n",
bclk, aif_rate, async ? "ASYNCCLK" : "SYSCLK");
return -EINVAL;
}
bclk = i;
dev_dbg(component->dev, "Setting %dHz BCLK\n", bclk_rates[bclk]);
snd_soc_component_update_bits(component, base + 1, WM5100_AIF1_BCLK_FREQ_MASK, bclk);
lrclk = bclk_rates[bclk] / params_rate(params);
dev_dbg(component->dev, "Setting %dHz LRCLK\n", bclk_rates[bclk] / lrclk);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
wm5100->aif_symmetric[dai->id])
snd_soc_component_update_bits(component, base + 7,
WM5100_AIF1RX_BCPF_MASK, lrclk);
else
snd_soc_component_update_bits(component, base + 6,
WM5100_AIF1TX_BCPF_MASK, lrclk);
i = (wl << WM5100_AIF1TX_WL_SHIFT) | fl;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
snd_soc_component_update_bits(component, base + 9,
WM5100_AIF1RX_WL_MASK |
WM5100_AIF1RX_SLOT_LEN_MASK, i);
else
snd_soc_component_update_bits(component, base + 8,
WM5100_AIF1TX_WL_MASK |
WM5100_AIF1TX_SLOT_LEN_MASK, i);
snd_soc_component_update_bits(component, base + 4, WM5100_AIF1_RATE_MASK, sr);
return 0;
}
static const struct snd_soc_dai_ops wm5100_dai_ops = {
.set_fmt = wm5100_set_fmt,
.hw_params = wm5100_hw_params,
};
static int wm5100_set_sysclk(struct snd_soc_component *component, int clk_id,
int source, unsigned int freq, int dir)
{
struct wm5100_priv *wm5100 = snd_soc_component_get_drvdata(component);
int *rate_store;
int fval, audio_rate, ret, reg;
switch (clk_id) {
case WM5100_CLK_SYSCLK:
reg = WM5100_CLOCKING_3;
rate_store = &wm5100->sysclk;
break;
case WM5100_CLK_ASYNCCLK:
reg = WM5100_CLOCKING_7;
rate_store = &wm5100->asyncclk;
break;
case WM5100_CLK_32KHZ:
/* The 32kHz clock is slightly different to the others */
switch (source) {
case WM5100_CLKSRC_MCLK1:
case WM5100_CLKSRC_MCLK2:
case WM5100_CLKSRC_SYSCLK:
snd_soc_component_update_bits(component, WM5100_CLOCKING_1,
WM5100_CLK_32K_SRC_MASK,
source);
break;
default:
return -EINVAL;
}
return 0;
case WM5100_CLK_AIF1:
case WM5100_CLK_AIF2:
case WM5100_CLK_AIF3:
/* Not real clocks, record which clock domain they're in */
switch (source) {
case WM5100_CLKSRC_SYSCLK:
wm5100->aif_async[clk_id - 1] = false;
break;
case WM5100_CLKSRC_ASYNCCLK:
wm5100->aif_async[clk_id - 1] = true;
break;
default:
dev_err(component->dev, "Invalid source %d\n", source);
return -EINVAL;
}
return 0;
case WM5100_CLK_OPCLK:
switch (freq) {
case 5644800:
case 6144000:
snd_soc_component_update_bits(component, WM5100_MISC_GPIO_1,
WM5100_OPCLK_SEL_MASK, 0);
break;
case 11289600:
case 12288000:
snd_soc_component_update_bits(component, WM5100_MISC_GPIO_1,
WM5100_OPCLK_SEL_MASK, 0);
break;
case 22579200:
case 24576000:
snd_soc_component_update_bits(component, WM5100_MISC_GPIO_1,
WM5100_OPCLK_SEL_MASK, 0);
break;
default:
dev_err(component->dev, "Unsupported OPCLK %dHz\n",
freq);
return -EINVAL;
}
return 0;
default:
dev_err(component->dev, "Unknown clock %d\n", clk_id);
return -EINVAL;
}
switch (source) {
case WM5100_CLKSRC_SYSCLK:
case WM5100_CLKSRC_ASYNCCLK:
dev_err(component->dev, "Invalid source %d\n", source);
return -EINVAL;
}
switch (freq) {
case 5644800:
case 6144000:
fval = 0;
break;
case 11289600:
case 12288000:
fval = 1;
break;
case 22579200:
case 24576000:
fval = 2;
break;
default:
dev_err(component->dev, "Invalid clock rate: %d\n", freq);
return -EINVAL;
}
switch (freq) {
case 5644800:
case 11289600:
case 22579200:
audio_rate = 44100;
break;
case 6144000:
case 12288000:
case 24576000:
audio_rate = 48000;
break;
default:
BUG();
audio_rate = 0;
break;
}
/* TODO: Check if MCLKs are in use and enable/disable pulls to
* match.
*/
snd_soc_component_update_bits(component, reg, WM5100_SYSCLK_FREQ_MASK |
WM5100_SYSCLK_SRC_MASK,
fval << WM5100_SYSCLK_FREQ_SHIFT | source);
/* If this is SYSCLK then configure the clock rate for the
* internal audio functions to the natural sample rate for
* this clock rate.
*/
if (clk_id == WM5100_CLK_SYSCLK) {
dev_dbg(component->dev, "Setting primary audio rate to %dHz",
audio_rate);
if (0 && *rate_store)
wm5100_free_sr(component, audio_rate);
ret = wm5100_alloc_sr(component, audio_rate);
if (ret != 0)
dev_warn(component->dev, "Primary audio slot is %d\n",
ret);
}
*rate_store = freq;
return 0;
}
struct _fll_div {
u16 fll_fratio;
u16 fll_outdiv;
u16 fll_refclk_div;
u16 n;
u16 theta;
u16 lambda;
};
static struct {
unsigned int min;
unsigned int max;
u16 fll_fratio;
int ratio;
} fll_fratios[] = {
{ 0, 64000, 4, 16 },
{ 64000, 128000, 3, 8 },
{ 128000, 256000, 2, 4 },
{ 256000, 1000000, 1, 2 },
{ 1000000, 13500000, 0, 1 },
};
static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
unsigned int Fout)
{
unsigned int target;
unsigned int div;
unsigned int fratio, gcd_fll;
int i;
/* Fref must be <=13.5MHz */
div = 1;
fll_div->fll_refclk_div = 0;
while ((Fref / div) > 13500000) {
div *= 2;
fll_div->fll_refclk_div++;
if (div > 8) {
pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
Fref);
return -EINVAL;
}
}
pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
/* Apply the division for our remaining calculations */
Fref /= div;
/* Fvco should be 90-100MHz; don't check the upper bound */
div = 2;
while (Fout * div < 90000000) {
div++;
if (div > 64) {
pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
Fout);
return -EINVAL;
}
}
target = Fout * div;
fll_div->fll_outdiv = div - 1;
pr_debug("FLL Fvco=%dHz\n", target);
/* Find an appropraite FLL_FRATIO and factor it out of the target */
for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
fll_div->fll_fratio = fll_fratios[i].fll_fratio;
fratio = fll_fratios[i].ratio;
break;
}
}
if (i == ARRAY_SIZE(fll_fratios)) {
pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
return -EINVAL;
}
fll_div->n = target / (fratio * Fref);
if (target % Fref == 0) {
fll_div->theta = 0;
fll_div->lambda = 0;
} else {
gcd_fll = gcd(target, fratio * Fref);
fll_div->theta = (target - (fll_div->n * fratio * Fref))
/ gcd_fll;
fll_div->lambda = (fratio * Fref) / gcd_fll;
}
pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
fll_div->n, fll_div->theta, fll_div->lambda);
pr_debug("FLL_FRATIO=%x(%d) FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
fll_div->fll_fratio, fratio, fll_div->fll_outdiv,
fll_div->fll_refclk_div);
return 0;
}
static int wm5100_set_fll(struct snd_soc_component *component, int fll_id, int source,
unsigned int Fref, unsigned int Fout)
{
struct i2c_client *i2c = to_i2c_client(component->dev);
struct wm5100_priv *wm5100 = snd_soc_component_get_drvdata(component);
struct _fll_div factors;
struct wm5100_fll *fll;
int ret, base, lock, i, timeout;
unsigned long time_left;
switch (fll_id) {
case WM5100_FLL1:
fll = &wm5100->fll[0];
base = WM5100_FLL1_CONTROL_1 - 1;
lock = WM5100_FLL1_LOCK_STS;
break;
case WM5100_FLL2:
fll = &wm5100->fll[1];
base = WM5100_FLL2_CONTROL_2 - 1;
lock = WM5100_FLL2_LOCK_STS;
break;
default:
dev_err(component->dev, "Unknown FLL %d\n",fll_id);
return -EINVAL;
}
if (!Fout) {
dev_dbg(component->dev, "FLL%d disabled", fll_id);
if (fll->fout)
pm_runtime_put(component->dev);
fll->fout = 0;
snd_soc_component_update_bits(component, base + 1, WM5100_FLL1_ENA, 0);
return 0;
}
switch (source) {
case WM5100_FLL_SRC_MCLK1:
case WM5100_FLL_SRC_MCLK2:
case WM5100_FLL_SRC_FLL1:
case WM5100_FLL_SRC_FLL2:
case WM5100_FLL_SRC_AIF1BCLK:
case WM5100_FLL_SRC_AIF2BCLK:
case WM5100_FLL_SRC_AIF3BCLK:
break;
default:
dev_err(component->dev, "Invalid FLL source %d\n", source);
return -EINVAL;
}
ret = fll_factors(&factors, Fref, Fout);
if (ret < 0)
return ret;
/* Disable the FLL while we reconfigure */
snd_soc_component_update_bits(component, base + 1, WM5100_FLL1_ENA, 0);
snd_soc_component_update_bits(component, base + 2,
WM5100_FLL1_OUTDIV_MASK | WM5100_FLL1_FRATIO_MASK,
(factors.fll_outdiv << WM5100_FLL1_OUTDIV_SHIFT) |
factors.fll_fratio);
snd_soc_component_update_bits(component, base + 3, WM5100_FLL1_THETA_MASK,
factors.theta);
snd_soc_component_update_bits(component, base + 5, WM5100_FLL1_N_MASK, factors.n);
snd_soc_component_update_bits(component, base + 6,
WM5100_FLL1_REFCLK_DIV_MASK |
WM5100_FLL1_REFCLK_SRC_MASK,
(factors.fll_refclk_div
<< WM5100_FLL1_REFCLK_DIV_SHIFT) | source);
snd_soc_component_update_bits(component, base + 7, WM5100_FLL1_LAMBDA_MASK,
factors.lambda);
/* Clear any pending completions */
try_wait_for_completion(&fll->lock);
pm_runtime_get_sync(component->dev);
snd_soc_component_update_bits(component, base + 1, WM5100_FLL1_ENA, WM5100_FLL1_ENA);
if (i2c->irq)
timeout = 2;
else
timeout = 50;
snd_soc_component_update_bits(component, WM5100_CLOCKING_3, WM5100_SYSCLK_ENA,
WM5100_SYSCLK_ENA);
/* Poll for the lock; will use interrupt when we can test */
for (i = 0; i < timeout; i++) {
if (i2c->irq) {
time_left = wait_for_completion_timeout(&fll->lock,
msecs_to_jiffies(25));
if (time_left > 0)
break;
} else {
msleep(1);
}
ret = snd_soc_component_read(component,
WM5100_INTERRUPT_RAW_STATUS_3);
if (ret < 0) {
dev_err(component->dev,
"Failed to read FLL status: %d\n",
ret);
continue;
}
if (ret & lock)
break;
}
if (i == timeout) {
dev_err(component->dev, "FLL%d lock timed out\n", fll_id);
pm_runtime_put(component->dev);
return -ETIMEDOUT;
}
fll->src = source;
fll->fref = Fref;
fll->fout = Fout;
dev_dbg(component->dev, "FLL%d running %dHz->%dHz\n", fll_id,
Fref, Fout);
return 0;
}
/* Actually go much higher */
#define WM5100_RATES SNDRV_PCM_RATE_8000_192000
#define WM5100_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver wm5100_dai[] = {
{
.name = "wm5100-aif1",
.base = WM5100_AUDIO_IF_1_1 - 1,
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 2,
.channels_max = 2,
.rates = WM5100_RATES,
.formats = WM5100_FORMATS,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 2,
.channels_max = 2,
.rates = WM5100_RATES,
.formats = WM5100_FORMATS,
},
.ops = &wm5100_dai_ops,
},
{
.name = "wm5100-aif2",
.id = 1,
.base = WM5100_AUDIO_IF_2_1 - 1,
.playback = {
.stream_name = "AIF2 Playback",
.channels_min = 2,
.channels_max = 2,
.rates = WM5100_RATES,
.formats = WM5100_FORMATS,
},
.capture = {
.stream_name = "AIF2 Capture",
.channels_min = 2,
.channels_max = 2,
.rates = WM5100_RATES,
.formats = WM5100_FORMATS,
},
.ops = &wm5100_dai_ops,
},
{
.name = "wm5100-aif3",
.id = 2,
.base = WM5100_AUDIO_IF_3_1 - 1,
.playback = {
.stream_name = "AIF3 Playback",
.channels_min = 2,
.channels_max = 2,
.rates = WM5100_RATES,
.formats = WM5100_FORMATS,
},
.capture = {
.stream_name = "AIF3 Capture",
.channels_min = 2,
.channels_max = 2,
.rates = WM5100_RATES,
.formats = WM5100_FORMATS,
},
.ops = &wm5100_dai_ops,
},
};
static int wm5100_dig_vu[] = {
WM5100_ADC_DIGITAL_VOLUME_1L,
WM5100_ADC_DIGITAL_VOLUME_1R,
WM5100_ADC_DIGITAL_VOLUME_2L,
WM5100_ADC_DIGITAL_VOLUME_2R,
WM5100_ADC_DIGITAL_VOLUME_3L,
WM5100_ADC_DIGITAL_VOLUME_3R,
WM5100_ADC_DIGITAL_VOLUME_4L,
WM5100_ADC_DIGITAL_VOLUME_4R,
WM5100_DAC_DIGITAL_VOLUME_1L,
WM5100_DAC_DIGITAL_VOLUME_1R,
WM5100_DAC_DIGITAL_VOLUME_2L,
WM5100_DAC_DIGITAL_VOLUME_2R,
WM5100_DAC_DIGITAL_VOLUME_3L,
WM5100_DAC_DIGITAL_VOLUME_3R,
WM5100_DAC_DIGITAL_VOLUME_4L,
WM5100_DAC_DIGITAL_VOLUME_4R,
WM5100_DAC_DIGITAL_VOLUME_5L,
WM5100_DAC_DIGITAL_VOLUME_5R,
WM5100_DAC_DIGITAL_VOLUME_6L,
WM5100_DAC_DIGITAL_VOLUME_6R,
};
static void wm5100_set_detect_mode(struct wm5100_priv *wm5100, int the_mode)
{
struct wm5100_jack_mode *mode = &wm5100->pdata.jack_modes[the_mode];
if (WARN_ON(the_mode >= ARRAY_SIZE(wm5100->pdata.jack_modes)))
return;
gpio_set_value_cansleep(wm5100->pdata.hp_pol, mode->hp_pol);
regmap_update_bits(wm5100->regmap, WM5100_ACCESSORY_DETECT_MODE_1,
WM5100_ACCDET_BIAS_SRC_MASK |
WM5100_ACCDET_SRC,
(mode->bias << WM5100_ACCDET_BIAS_SRC_SHIFT) |
mode->micd_src << WM5100_ACCDET_SRC_SHIFT);
regmap_update_bits(wm5100->regmap, WM5100_MISC_CONTROL,
WM5100_HPCOM_SRC,
mode->micd_src << WM5100_HPCOM_SRC_SHIFT);
wm5100->jack_mode = the_mode;
dev_dbg(wm5100->dev, "Set microphone polarity to %d\n",
wm5100->jack_mode);
}
static void wm5100_report_headphone(struct wm5100_priv *wm5100)
{
dev_dbg(wm5100->dev, "Headphone detected\n");
wm5100->jack_detecting = false;
snd_soc_jack_report(wm5100->jack, SND_JACK_HEADPHONE,
SND_JACK_HEADPHONE);
/* Increase the detection rate a bit for responsiveness. */
regmap_update_bits(wm5100->regmap, WM5100_MIC_DETECT_1,
WM5100_ACCDET_RATE_MASK,
7 << WM5100_ACCDET_RATE_SHIFT);
}
static void wm5100_micd_irq(struct wm5100_priv *wm5100)
{
unsigned int val;
int ret;
ret = regmap_read(wm5100->regmap, WM5100_MIC_DETECT_3, &val);
if (ret != 0) {
dev_err(wm5100->dev, "Failed to read microphone status: %d\n",
ret);
return;
}
dev_dbg(wm5100->dev, "Microphone event: %x\n", val);
if (!(val & WM5100_ACCDET_VALID)) {
dev_warn(wm5100->dev, "Microphone detection state invalid\n");
return;
}
/* No accessory, reset everything and report removal */
if (!(val & WM5100_ACCDET_STS)) {
dev_dbg(wm5100->dev, "Jack removal detected\n");
wm5100->jack_mic = false;
wm5100->jack_detecting = true;
wm5100->jack_flips = 0;
snd_soc_jack_report(wm5100->jack, 0,
SND_JACK_LINEOUT | SND_JACK_HEADSET |
SND_JACK_BTN_0);
regmap_update_bits(wm5100->regmap, WM5100_MIC_DETECT_1,
WM5100_ACCDET_RATE_MASK,
WM5100_ACCDET_RATE_MASK);
return;
}
/* If the measurement is very high we've got a microphone,
* either we just detected one or if we already reported then
* we've got a button release event.
*/
if (val & 0x400) {
if (wm5100->jack_detecting) {
dev_dbg(wm5100->dev, "Microphone detected\n");
wm5100->jack_mic = true;
wm5100->jack_detecting = false;
snd_soc_jack_report(wm5100->jack,
SND_JACK_HEADSET,
SND_JACK_HEADSET | SND_JACK_BTN_0);
/* Increase poll rate to give better responsiveness
* for buttons */
regmap_update_bits(wm5100->regmap, WM5100_MIC_DETECT_1,
WM5100_ACCDET_RATE_MASK,
5 << WM5100_ACCDET_RATE_SHIFT);
} else {
dev_dbg(wm5100->dev, "Mic button up\n");
snd_soc_jack_report(wm5100->jack, 0, SND_JACK_BTN_0);
}
return;
}
/* If we detected a lower impedence during initial startup
* then we probably have the wrong polarity, flip it. Don't
* do this for the lowest impedences to speed up detection of
* plain headphones and give up if neither polarity looks
* sensible.
*/
if (wm5100->jack_detecting && (val & 0x3f8)) {
wm5100->jack_flips++;
if (wm5100->jack_flips > 1)
wm5100_report_headphone(wm5100);
else
wm5100_set_detect_mode(wm5100, !wm5100->jack_mode);
return;
}
/* Don't distinguish between buttons, just report any low
* impedence as BTN_0.
*/
if (val & 0x3fc) {
if (wm5100->jack_mic) {
dev_dbg(wm5100->dev, "Mic button detected\n");
snd_soc_jack_report(wm5100->jack, SND_JACK_BTN_0,
SND_JACK_BTN_0);
} else if (wm5100->jack_detecting) {
wm5100_report_headphone(wm5100);
}
}
}
int wm5100_detect(struct snd_soc_component *component, struct snd_soc_jack *jack)
{
struct wm5100_priv *wm5100 = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
if (jack) {
wm5100->jack = jack;
wm5100->jack_detecting = true;
wm5100->jack_flips = 0;
wm5100_set_detect_mode(wm5100, 0);
/* Slowest detection rate, gives debounce for initial
* detection */
snd_soc_component_update_bits(component, WM5100_MIC_DETECT_1,
WM5100_ACCDET_BIAS_STARTTIME_MASK |
WM5100_ACCDET_RATE_MASK,
(7 << WM5100_ACCDET_BIAS_STARTTIME_SHIFT) |
WM5100_ACCDET_RATE_MASK);
/* We need the charge pump to power MICBIAS */
snd_soc_dapm_mutex_lock(dapm);
snd_soc_dapm_force_enable_pin_unlocked(dapm, "CP2");
snd_soc_dapm_force_enable_pin_unlocked(dapm, "SYSCLK");
snd_soc_dapm_sync_unlocked(dapm);
snd_soc_dapm_mutex_unlock(dapm);
/* We start off just enabling microphone detection - even a
* plain headphone will trigger detection.
*/
snd_soc_component_update_bits(component, WM5100_MIC_DETECT_1,
WM5100_ACCDET_ENA, WM5100_ACCDET_ENA);
snd_soc_component_update_bits(component, WM5100_INTERRUPT_STATUS_3_MASK,
WM5100_IM_ACCDET_EINT, 0);
} else {
snd_soc_component_update_bits(component, WM5100_INTERRUPT_STATUS_3_MASK,
WM5100_IM_HPDET_EINT |
WM5100_IM_ACCDET_EINT,
WM5100_IM_HPDET_EINT |
WM5100_IM_ACCDET_EINT);
snd_soc_component_update_bits(component, WM5100_MIC_DETECT_1,
WM5100_ACCDET_ENA, 0);
wm5100->jack = NULL;
}
return 0;
}
EXPORT_SYMBOL_GPL(wm5100_detect);
static irqreturn_t wm5100_irq(int irq, void *data)
{
struct wm5100_priv *wm5100 = data;
irqreturn_t status = IRQ_NONE;
unsigned int irq_val, mask_val;
int ret;
ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_3, &irq_val);
if (ret < 0) {
dev_err(wm5100->dev, "Failed to read IRQ status 3: %d\n",
ret);
irq_val = 0;
}
ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_3_MASK,
&mask_val);
if (ret < 0) {
dev_err(wm5100->dev, "Failed to read IRQ mask 3: %d\n",
ret);
mask_val = 0xffff;
}
irq_val &= ~mask_val;
regmap_write(wm5100->regmap, WM5100_INTERRUPT_STATUS_3, irq_val);
if (irq_val)
status = IRQ_HANDLED;
wm5100_log_status3(wm5100, irq_val);
if (irq_val & WM5100_FLL1_LOCK_EINT) {
dev_dbg(wm5100->dev, "FLL1 locked\n");
complete(&wm5100->fll[0].lock);
}
if (irq_val & WM5100_FLL2_LOCK_EINT) {
dev_dbg(wm5100->dev, "FLL2 locked\n");
complete(&wm5100->fll[1].lock);
}
if (irq_val & WM5100_ACCDET_EINT)
wm5100_micd_irq(wm5100);
ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_4, &irq_val);
if (ret < 0) {
dev_err(wm5100->dev, "Failed to read IRQ status 4: %d\n",
ret);
irq_val = 0;
}
ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_4_MASK,
&mask_val);
if (ret < 0) {
dev_err(wm5100->dev, "Failed to read IRQ mask 4: %d\n",
ret);
mask_val = 0xffff;
}
irq_val &= ~mask_val;
if (irq_val)
status = IRQ_HANDLED;
regmap_write(wm5100->regmap, WM5100_INTERRUPT_STATUS_4, irq_val);
wm5100_log_status4(wm5100, irq_val);
return status;
}
static irqreturn_t wm5100_edge_irq(int irq, void *data)
{
irqreturn_t ret = IRQ_NONE;
irqreturn_t val;
do {
val = wm5100_irq(irq, data);
if (val != IRQ_NONE)
ret = val;
} while (val != IRQ_NONE);
return ret;
}
#ifdef CONFIG_GPIOLIB
static void wm5100_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct wm5100_priv *wm5100 = gpiochip_get_data(chip);
regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset,
WM5100_GP1_LVL, !!value << WM5100_GP1_LVL_SHIFT);
}
static int wm5100_gpio_direction_out(struct gpio_chip *chip,
unsigned offset, int value)
{
struct wm5100_priv *wm5100 = gpiochip_get_data(chip);
int val, ret;
val = (1 << WM5100_GP1_FN_SHIFT) | (!!value << WM5100_GP1_LVL_SHIFT);
ret = regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset,
WM5100_GP1_FN_MASK | WM5100_GP1_DIR |
WM5100_GP1_LVL, val);
if (ret < 0)
return ret;
else
return 0;
}
static int wm5100_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct wm5100_priv *wm5100 = gpiochip_get_data(chip);
unsigned int reg;
int ret;
ret = regmap_read(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset, ®);
if (ret < 0)
return ret;
return (reg & WM5100_GP1_LVL) != 0;
}
static int wm5100_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
{
struct wm5100_priv *wm5100 = gpiochip_get_data(chip);
return regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset,
WM5100_GP1_FN_MASK | WM5100_GP1_DIR,
(1 << WM5100_GP1_FN_SHIFT) |
(1 << WM5100_GP1_DIR_SHIFT));
}
static const struct gpio_chip wm5100_template_chip = {
.label = "wm5100",
.owner = THIS_MODULE,
.direction_output = wm5100_gpio_direction_out,
.set = wm5100_gpio_set,
.direction_input = wm5100_gpio_direction_in,
.get = wm5100_gpio_get,
.can_sleep = 1,
};
static void wm5100_init_gpio(struct i2c_client *i2c)
{
struct wm5100_priv *wm5100 = i2c_get_clientdata(i2c);
int ret;
wm5100->gpio_chip = wm5100_template_chip;
wm5100->gpio_chip.ngpio = 6;
wm5100->gpio_chip.parent = &i2c->dev;
if (wm5100->pdata.gpio_base)
wm5100->gpio_chip.base = wm5100->pdata.gpio_base;
else
wm5100->gpio_chip.base = -1;
ret = gpiochip_add_data(&wm5100->gpio_chip, wm5100);
if (ret != 0)
dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
}
static void wm5100_free_gpio(struct i2c_client *i2c)
{
struct wm5100_priv *wm5100 = i2c_get_clientdata(i2c);
gpiochip_remove(&wm5100->gpio_chip);
}
#else
static void wm5100_init_gpio(struct i2c_client *i2c)
{
}
static void wm5100_free_gpio(struct i2c_client *i2c)
{
}
#endif
static int wm5100_probe(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct i2c_client *i2c = to_i2c_client(component->dev);
struct wm5100_priv *wm5100 = snd_soc_component_get_drvdata(component);
int ret, i;
wm5100->component = component;
for (i = 0; i < ARRAY_SIZE(wm5100_dig_vu); i++)
snd_soc_component_update_bits(component, wm5100_dig_vu[i], WM5100_OUT_VU,
WM5100_OUT_VU);
/* Don't debounce interrupts to support use of SYSCLK only */
snd_soc_component_write(component, WM5100_IRQ_DEBOUNCE_1, 0);
snd_soc_component_write(component, WM5100_IRQ_DEBOUNCE_2, 0);
/* TODO: check if we're symmetric */
if (i2c->irq)
snd_soc_dapm_new_controls(dapm, wm5100_dapm_widgets_noirq,
ARRAY_SIZE(wm5100_dapm_widgets_noirq));
if (wm5100->pdata.hp_pol) {
ret = gpio_request_one(wm5100->pdata.hp_pol,
GPIOF_OUT_INIT_HIGH, "WM5100 HP_POL");
if (ret < 0) {
dev_err(&i2c->dev, "Failed to request HP_POL %d: %d\n",
wm5100->pdata.hp_pol, ret);
goto err_gpio;
}
}
return 0;
err_gpio:
return ret;
}
static void wm5100_remove(struct snd_soc_component *component)
{
struct wm5100_priv *wm5100 = snd_soc_component_get_drvdata(component);
if (wm5100->pdata.hp_pol) {
gpio_free(wm5100->pdata.hp_pol);
}
}
static const struct snd_soc_component_driver soc_component_dev_wm5100 = {
.probe = wm5100_probe,
.remove = wm5100_remove,
.set_sysclk = wm5100_set_sysclk,
.set_pll = wm5100_set_fll,
.seq_notifier = wm5100_seq_notifier,
.controls = wm5100_snd_controls,
.num_controls = ARRAY_SIZE(wm5100_snd_controls),
.dapm_widgets = wm5100_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm5100_dapm_widgets),
.dapm_routes = wm5100_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(wm5100_dapm_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config wm5100_regmap = {
.reg_bits = 16,
.val_bits = 16,
.max_register = WM5100_MAX_REGISTER,
.reg_defaults = wm5100_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm5100_reg_defaults),
.volatile_reg = wm5100_volatile_register,
.readable_reg = wm5100_readable_register,
.cache_type = REGCACHE_MAPLE,
};
static const unsigned int wm5100_mic_ctrl_reg[] = {
WM5100_IN1L_CONTROL,
WM5100_IN2L_CONTROL,
WM5100_IN3L_CONTROL,
WM5100_IN4L_CONTROL,
};
static int wm5100_i2c_probe(struct i2c_client *i2c)
{
struct wm5100_pdata *pdata = dev_get_platdata(&i2c->dev);
struct wm5100_priv *wm5100;
unsigned int reg;
int ret, i, irq_flags;
wm5100 = devm_kzalloc(&i2c->dev, sizeof(struct wm5100_priv),
GFP_KERNEL);
if (wm5100 == NULL)
return -ENOMEM;
wm5100->dev = &i2c->dev;
wm5100->regmap = devm_regmap_init_i2c(i2c, &wm5100_regmap);
if (IS_ERR(wm5100->regmap)) {
ret = PTR_ERR(wm5100->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
goto err;
}
for (i = 0; i < ARRAY_SIZE(wm5100->fll); i++)
init_completion(&wm5100->fll[i].lock);
if (pdata)
wm5100->pdata = *pdata;
i2c_set_clientdata(i2c, wm5100);
for (i = 0; i < ARRAY_SIZE(wm5100->core_supplies); i++)
wm5100->core_supplies[i].supply = wm5100_core_supply_names[i];
ret = devm_regulator_bulk_get(&i2c->dev,
ARRAY_SIZE(wm5100->core_supplies),
wm5100->core_supplies);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to request core supplies: %d\n",
ret);
goto err;
}
ret = regulator_bulk_enable(ARRAY_SIZE(wm5100->core_supplies),
wm5100->core_supplies);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to enable core supplies: %d\n",
ret);
goto err;
}
if (wm5100->pdata.ldo_ena) {
ret = gpio_request_one(wm5100->pdata.ldo_ena,
GPIOF_OUT_INIT_HIGH, "WM5100 LDOENA");
if (ret < 0) {
dev_err(&i2c->dev, "Failed to request LDOENA %d: %d\n",
wm5100->pdata.ldo_ena, ret);
goto err_enable;
}
msleep(2);
}
if (wm5100->pdata.reset) {
ret = gpio_request_one(wm5100->pdata.reset,
GPIOF_OUT_INIT_HIGH, "WM5100 /RESET");
if (ret < 0) {
dev_err(&i2c->dev, "Failed to request /RESET %d: %d\n",
wm5100->pdata.reset, ret);
goto err_ldo;
}
}
ret = regmap_read(wm5100->regmap, WM5100_SOFTWARE_RESET, ®);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
goto err_reset;
}
switch (reg) {
case 0x8997:
case 0x5100:
break;
default:
dev_err(&i2c->dev, "Device is not a WM5100, ID is %x\n", reg);
ret = -EINVAL;
goto err_reset;
}
ret = regmap_read(wm5100->regmap, WM5100_DEVICE_REVISION, ®);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to read revision register\n");
goto err_reset;
}
wm5100->rev = reg & WM5100_DEVICE_REVISION_MASK;
dev_info(&i2c->dev, "revision %c\n", wm5100->rev + 'A');
ret = wm5100_reset(wm5100);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to issue reset\n");
goto err_reset;
}
switch (wm5100->rev) {
case 0:
ret = regmap_register_patch(wm5100->regmap,
wm5100_reva_patches,
ARRAY_SIZE(wm5100_reva_patches));
if (ret != 0) {
dev_err(&i2c->dev, "Failed to register patches: %d\n",
ret);
goto err_reset;
}
break;
default:
break;
}
wm5100_init_gpio(i2c);
for (i = 0; i < ARRAY_SIZE(wm5100->pdata.gpio_defaults); i++) {
if (!wm5100->pdata.gpio_defaults[i])
continue;
regmap_write(wm5100->regmap, WM5100_GPIO_CTRL_1 + i,
wm5100->pdata.gpio_defaults[i]);
}
for (i = 0; i < ARRAY_SIZE(wm5100->pdata.in_mode); i++) {
regmap_update_bits(wm5100->regmap, wm5100_mic_ctrl_reg[i],
WM5100_IN1_MODE_MASK |
WM5100_IN1_DMIC_SUP_MASK,
(wm5100->pdata.in_mode[i] <<
WM5100_IN1_MODE_SHIFT) |
(wm5100->pdata.dmic_sup[i] <<
WM5100_IN1_DMIC_SUP_SHIFT));
}
if (i2c->irq) {
if (wm5100->pdata.irq_flags)
irq_flags = wm5100->pdata.irq_flags;
else
irq_flags = IRQF_TRIGGER_LOW;
irq_flags |= IRQF_ONESHOT;
if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
ret = request_threaded_irq(i2c->irq, NULL,
wm5100_edge_irq, irq_flags,
"wm5100", wm5100);
else
ret = request_threaded_irq(i2c->irq, NULL, wm5100_irq,
irq_flags, "wm5100",
wm5100);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n",
i2c->irq, ret);
} else {
/* Enable default interrupts */
regmap_update_bits(wm5100->regmap,
WM5100_INTERRUPT_STATUS_3_MASK,
WM5100_IM_SPK_SHUTDOWN_WARN_EINT |
WM5100_IM_SPK_SHUTDOWN_EINT |
WM5100_IM_ASRC2_LOCK_EINT |
WM5100_IM_ASRC1_LOCK_EINT |
WM5100_IM_FLL2_LOCK_EINT |
WM5100_IM_FLL1_LOCK_EINT |
WM5100_CLKGEN_ERR_EINT |
WM5100_CLKGEN_ERR_ASYNC_EINT, 0);
regmap_update_bits(wm5100->regmap,
WM5100_INTERRUPT_STATUS_4_MASK,
WM5100_AIF3_ERR_EINT |
WM5100_AIF2_ERR_EINT |
WM5100_AIF1_ERR_EINT |
WM5100_CTRLIF_ERR_EINT |
WM5100_ISRC2_UNDERCLOCKED_EINT |
WM5100_ISRC1_UNDERCLOCKED_EINT |
WM5100_FX_UNDERCLOCKED_EINT |
WM5100_AIF3_UNDERCLOCKED_EINT |
WM5100_AIF2_UNDERCLOCKED_EINT |
WM5100_AIF1_UNDERCLOCKED_EINT |
WM5100_ASRC_UNDERCLOCKED_EINT |
WM5100_DAC_UNDERCLOCKED_EINT |
WM5100_ADC_UNDERCLOCKED_EINT |
WM5100_MIXER_UNDERCLOCKED_EINT, 0);
}
}
pm_runtime_set_active(&i2c->dev);
pm_runtime_enable(&i2c->dev);
pm_request_idle(&i2c->dev);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_wm5100, wm5100_dai,
ARRAY_SIZE(wm5100_dai));
if (ret < 0) {
dev_err(&i2c->dev, "Failed to register WM5100: %d\n", ret);
goto err_reset;
}
return ret;
err_reset:
pm_runtime_disable(&i2c->dev);
if (i2c->irq)
free_irq(i2c->irq, wm5100);
wm5100_free_gpio(i2c);
if (wm5100->pdata.reset) {
gpio_set_value_cansleep(wm5100->pdata.reset, 0);
gpio_free(wm5100->pdata.reset);
}
err_ldo:
if (wm5100->pdata.ldo_ena) {
gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
gpio_free(wm5100->pdata.ldo_ena);
}
err_enable:
regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies),
wm5100->core_supplies);
err:
return ret;
}
static void wm5100_i2c_remove(struct i2c_client *i2c)
{
struct wm5100_priv *wm5100 = i2c_get_clientdata(i2c);
pm_runtime_disable(&i2c->dev);
if (i2c->irq)
free_irq(i2c->irq, wm5100);
wm5100_free_gpio(i2c);
if (wm5100->pdata.reset) {
gpio_set_value_cansleep(wm5100->pdata.reset, 0);
gpio_free(wm5100->pdata.reset);
}
if (wm5100->pdata.ldo_ena) {
gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
gpio_free(wm5100->pdata.ldo_ena);
}
}
#ifdef CONFIG_PM
static int wm5100_runtime_suspend(struct device *dev)
{
struct wm5100_priv *wm5100 = dev_get_drvdata(dev);
regcache_cache_only(wm5100->regmap, true);
regcache_mark_dirty(wm5100->regmap);
if (wm5100->pdata.ldo_ena)
gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies),
wm5100->core_supplies);
return 0;
}
static int wm5100_runtime_resume(struct device *dev)
{
struct wm5100_priv *wm5100 = dev_get_drvdata(dev);
int ret;
ret = regulator_bulk_enable(ARRAY_SIZE(wm5100->core_supplies),
wm5100->core_supplies);
if (ret != 0) {
dev_err(dev, "Failed to enable supplies: %d\n",
ret);
return ret;
}
if (wm5100->pdata.ldo_ena) {
gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 1);
msleep(2);
}
regcache_cache_only(wm5100->regmap, false);
regcache_sync(wm5100->regmap);
return 0;
}
#endif
static const struct dev_pm_ops wm5100_pm = {
SET_RUNTIME_PM_OPS(wm5100_runtime_suspend, wm5100_runtime_resume,
NULL)
};
static const struct i2c_device_id wm5100_i2c_id[] = {
{ "wm5100", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm5100_i2c_id);
static struct i2c_driver wm5100_i2c_driver = {
.driver = {
.name = "wm5100",
.pm = &wm5100_pm,
},
.probe = wm5100_i2c_probe,
.remove = wm5100_i2c_remove,
.id_table = wm5100_i2c_id,
};
module_i2c_driver(wm5100_i2c_driver);
MODULE_DESCRIPTION("ASoC WM5100 driver");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm5100.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// aw88261.c -- AW88261 ALSA SoC Audio driver
//
// Copyright (c) 2023 awinic Technology CO., LTD
//
// Author: Jimmy Zhang <[email protected]>
// Author: Weidong Wang <[email protected]>
//
#include <linux/i2c.h>
#include <linux/firmware.h>
#include <linux/of_gpio.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include "aw88261.h"
#include "aw88395/aw88395_data_type.h"
#include "aw88395/aw88395_device.h"
static const struct regmap_config aw88261_remap_config = {
.val_bits = 16,
.reg_bits = 8,
.max_register = AW88261_REG_MAX - 1,
.reg_format_endian = REGMAP_ENDIAN_LITTLE,
.val_format_endian = REGMAP_ENDIAN_BIG,
};
static void aw88261_dev_set_volume(struct aw_device *aw_dev, unsigned int value)
{
struct aw_volume_desc *vol_desc = &aw_dev->volume_desc;
unsigned int real_value, volume;
unsigned int reg_value;
volume = min((value + vol_desc->init_volume), (unsigned int)AW88261_MUTE_VOL);
real_value = DB_TO_REG_VAL(volume);
regmap_read(aw_dev->regmap, AW88261_SYSCTRL2_REG, ®_value);
real_value = (real_value | (reg_value & AW88261_VOL_START_MASK));
dev_dbg(aw_dev->dev, "value 0x%x , real_value:0x%x", value, real_value);
regmap_write(aw_dev->regmap, AW88261_SYSCTRL2_REG, real_value);
}
static void aw88261_dev_fade_in(struct aw_device *aw_dev)
{
struct aw_volume_desc *desc = &aw_dev->volume_desc;
int fade_in_vol = desc->ctl_volume;
int fade_step = aw_dev->fade_step;
int i;
if (fade_step == 0 || aw_dev->fade_in_time == 0) {
aw88261_dev_set_volume(aw_dev, fade_in_vol);
return;
}
for (i = AW88261_MUTE_VOL; i >= fade_in_vol; i -= fade_step) {
aw88261_dev_set_volume(aw_dev, i);
usleep_range(aw_dev->fade_in_time,
aw_dev->fade_in_time + 10);
}
if (i != fade_in_vol)
aw88261_dev_set_volume(aw_dev, fade_in_vol);
}
static void aw88261_dev_fade_out(struct aw_device *aw_dev)
{
struct aw_volume_desc *desc = &aw_dev->volume_desc;
int fade_step = aw_dev->fade_step;
int i;
if (fade_step == 0 || aw_dev->fade_out_time == 0) {
aw88261_dev_set_volume(aw_dev, AW88261_MUTE_VOL);
return;
}
for (i = desc->ctl_volume; i <= AW88261_MUTE_VOL; i += fade_step) {
aw88261_dev_set_volume(aw_dev, i);
usleep_range(aw_dev->fade_out_time, aw_dev->fade_out_time + 10);
}
if (i != AW88261_MUTE_VOL) {
aw88261_dev_set_volume(aw_dev, AW88261_MUTE_VOL);
usleep_range(aw_dev->fade_out_time, aw_dev->fade_out_time + 10);
}
}
static void aw88261_dev_i2s_tx_enable(struct aw_device *aw_dev, bool flag)
{
if (flag)
regmap_update_bits(aw_dev->regmap, AW88261_I2SCFG1_REG,
~AW88261_I2STXEN_MASK, AW88261_I2STXEN_ENABLE_VALUE);
else
regmap_update_bits(aw_dev->regmap, AW88261_I2SCFG1_REG,
~AW88261_I2STXEN_MASK, AW88261_I2STXEN_DISABLE_VALUE);
}
static void aw88261_dev_pwd(struct aw_device *aw_dev, bool pwd)
{
if (pwd)
regmap_update_bits(aw_dev->regmap, AW88261_SYSCTRL_REG,
~AW88261_PWDN_MASK, AW88261_PWDN_POWER_DOWN_VALUE);
else
regmap_update_bits(aw_dev->regmap, AW88261_SYSCTRL_REG,
~AW88261_PWDN_MASK, AW88261_PWDN_WORKING_VALUE);
}
static void aw88261_dev_amppd(struct aw_device *aw_dev, bool amppd)
{
if (amppd)
regmap_update_bits(aw_dev->regmap, AW88261_SYSCTRL_REG,
~AW88261_AMPPD_MASK, AW88261_AMPPD_POWER_DOWN_VALUE);
else
regmap_update_bits(aw_dev->regmap, AW88261_SYSCTRL_REG,
~AW88261_AMPPD_MASK, AW88261_AMPPD_WORKING_VALUE);
}
static void aw88261_dev_mute(struct aw_device *aw_dev, bool is_mute)
{
if (is_mute) {
aw88261_dev_fade_out(aw_dev);
regmap_update_bits(aw_dev->regmap, AW88261_SYSCTRL_REG,
~AW88261_HMUTE_MASK, AW88261_HMUTE_ENABLE_VALUE);
} else {
regmap_update_bits(aw_dev->regmap, AW88261_SYSCTRL_REG,
~AW88261_HMUTE_MASK, AW88261_HMUTE_DISABLE_VALUE);
aw88261_dev_fade_in(aw_dev);
}
}
static void aw88261_dev_clear_int_status(struct aw_device *aw_dev)
{
unsigned int int_status;
/* read int status and clear */
regmap_read(aw_dev->regmap, AW88261_SYSINT_REG, &int_status);
/* make sure int status is clear */
regmap_read(aw_dev->regmap, AW88261_SYSINT_REG, &int_status);
dev_dbg(aw_dev->dev, "read interrupt reg = 0x%04x", int_status);
}
static int aw88261_dev_get_iis_status(struct aw_device *aw_dev)
{
unsigned int reg_val;
int ret;
ret = regmap_read(aw_dev->regmap, AW88261_SYSST_REG, ®_val);
if (ret)
return ret;
if ((reg_val & AW88261_BIT_PLL_CHECK) != AW88261_BIT_PLL_CHECK) {
dev_err(aw_dev->dev, "check pll lock fail,reg_val:0x%04x", reg_val);
return -EINVAL;
}
return ret;
}
static int aw88261_dev_check_mode1_pll(struct aw_device *aw_dev)
{
int ret, i;
for (i = 0; i < AW88261_DEV_SYSST_CHECK_MAX; i++) {
ret = aw88261_dev_get_iis_status(aw_dev);
if (ret) {
dev_err(aw_dev->dev, "mode1 iis signal check error");
usleep_range(AW88261_2000_US, AW88261_2000_US + 10);
} else {
return ret;
}
}
return -EPERM;
}
static int aw88261_dev_check_mode2_pll(struct aw_device *aw_dev)
{
unsigned int reg_val;
int ret, i;
ret = regmap_read(aw_dev->regmap, AW88261_PLLCTRL1_REG, ®_val);
if (ret)
return ret;
reg_val &= (~AW88261_CCO_MUX_MASK);
if (reg_val == AW88261_CCO_MUX_DIVIDED_VALUE) {
dev_dbg(aw_dev->dev, "CCO_MUX is already divider");
return -EPERM;
}
/* change mode2 */
ret = regmap_update_bits(aw_dev->regmap, AW88261_PLLCTRL1_REG,
~AW88261_CCO_MUX_MASK, AW88261_CCO_MUX_DIVIDED_VALUE);
if (ret)
return ret;
for (i = 0; i < AW88261_DEV_SYSST_CHECK_MAX; i++) {
ret = aw88261_dev_get_iis_status(aw_dev);
if (ret) {
dev_err(aw_dev->dev, "mode2 iis signal check error");
usleep_range(AW88261_2000_US, AW88261_2000_US + 10);
} else {
break;
}
}
/* change mode1 */
ret = regmap_update_bits(aw_dev->regmap, AW88261_PLLCTRL1_REG,
~AW88261_CCO_MUX_MASK, AW88261_CCO_MUX_BYPASS_VALUE);
if (ret == 0) {
usleep_range(AW88261_2000_US, AW88261_2000_US + 10);
for (i = 0; i < AW88261_DEV_SYSST_CHECK_MAX; i++) {
ret = aw88261_dev_check_mode1_pll(aw_dev);
if (ret) {
dev_err(aw_dev->dev, "mode2 switch to mode1, iis signal check error");
usleep_range(AW88261_2000_US, AW88261_2000_US + 10);
} else {
break;
}
}
}
return ret;
}
static int aw88261_dev_check_syspll(struct aw_device *aw_dev)
{
int ret;
ret = aw88261_dev_check_mode1_pll(aw_dev);
if (ret) {
dev_dbg(aw_dev->dev, "mode1 check iis failed try switch to mode2 check");
ret = aw88261_dev_check_mode2_pll(aw_dev);
if (ret) {
dev_err(aw_dev->dev, "mode2 check iis failed");
return ret;
}
}
return ret;
}
static int aw88261_dev_check_sysst(struct aw_device *aw_dev)
{
unsigned int check_val;
unsigned int reg_val;
int ret, i;
for (i = 0; i < AW88261_DEV_SYSST_CHECK_MAX; i++) {
ret = regmap_read(aw_dev->regmap, AW88261_SYSST_REG, ®_val);
if (ret)
return ret;
check_val = reg_val & (~AW88261_BIT_SYSST_CHECK_MASK)
& AW88261_BIT_SYSST_CHECK;
if (check_val != AW88261_BIT_SYSST_CHECK) {
dev_err(aw_dev->dev, "check sysst fail, reg_val=0x%04x, check:0x%x",
reg_val, AW88261_BIT_SYSST_CHECK);
usleep_range(AW88261_2000_US, AW88261_2000_US + 10);
} else {
return 0;
}
}
return -EPERM;
}
static void aw88261_dev_uls_hmute(struct aw_device *aw_dev, bool uls_hmute)
{
if (uls_hmute)
regmap_update_bits(aw_dev->regmap, AW88261_SYSCTRL_REG,
~AW88261_ULS_HMUTE_MASK,
AW88261_ULS_HMUTE_ENABLE_VALUE);
else
regmap_update_bits(aw_dev->regmap, AW88261_SYSCTRL_REG,
~AW88261_ULS_HMUTE_MASK,
AW88261_ULS_HMUTE_DISABLE_VALUE);
}
static void aw88261_reg_force_set(struct aw88261 *aw88261)
{
if (aw88261->frcset_en == AW88261_FRCSET_ENABLE) {
/* set FORCE_PWM */
regmap_update_bits(aw88261->regmap, AW88261_BSTCTRL3_REG,
AW88261_FORCE_PWM_MASK, AW88261_FORCE_PWM_FORCEMINUS_PWM_VALUE);
/* set BOOST_OS_WIDTH */
regmap_update_bits(aw88261->regmap, AW88261_BSTCTRL5_REG,
AW88261_BST_OS_WIDTH_MASK, AW88261_BST_OS_WIDTH_50NS_VALUE);
/* set BURST_LOOPR */
regmap_update_bits(aw88261->regmap, AW88261_BSTCTRL6_REG,
AW88261_BST_LOOPR_MASK, AW88261_BST_LOOPR_340K_VALUE);
/* set RSQN_DLY */
regmap_update_bits(aw88261->regmap, AW88261_BSTCTRL7_REG,
AW88261_RSQN_DLY_MASK, AW88261_RSQN_DLY_35NS_VALUE);
/* set BURST_SSMODE */
regmap_update_bits(aw88261->regmap, AW88261_BSTCTRL8_REG,
AW88261_BURST_SSMODE_MASK, AW88261_BURST_SSMODE_FAST_VALUE);
/* set BST_BURST */
regmap_update_bits(aw88261->regmap, AW88261_BSTCTRL9_REG,
AW88261_BST_BURST_MASK, AW88261_BST_BURST_30MA_VALUE);
} else {
dev_dbg(aw88261->aw_pa->dev, "needn't set reg value");
}
}
static int aw88261_dev_get_icalk(struct aw_device *aw_dev, int16_t *icalk)
{
u16 reg_icalk, reg_icalkl;
unsigned int reg_val;
int ret;
ret = regmap_read(aw_dev->regmap, AW88261_EFRH4_REG, ®_val);
if (ret)
return ret;
reg_icalk = reg_val & (~AW88261_EF_ISN_GESLP_H_MASK);
ret = regmap_read(aw_dev->regmap, AW88261_EFRL4_REG, ®_val);
if (ret)
return ret;
reg_icalkl = reg_val & (~AW88261_EF_ISN_GESLP_L_MASK);
reg_icalk = (reg_icalk >> AW88261_ICALK_SHIFT) & (reg_icalkl >> AW88261_ICALKL_SHIFT);
if (reg_icalk & (~AW88261_EF_ISN_GESLP_SIGN_MASK))
reg_icalk = reg_icalk | ~AW88261_EF_ISN_GESLP_NEG;
*icalk = (int16_t)reg_icalk;
return ret;
}
static int aw88261_dev_get_vcalk(struct aw_device *aw_dev, int16_t *vcalk)
{
u16 reg_vcalk, reg_vcalkl;
unsigned int reg_val;
int ret;
ret = regmap_read(aw_dev->regmap, AW88261_EFRH3_REG, ®_val);
if (ret)
return ret;
reg_vcalk = (u16)reg_val & (~AW88261_EF_VSN_GESLP_H_MASK);
ret = regmap_read(aw_dev->regmap, AW88261_EFRL3_REG, ®_val);
if (ret)
return ret;
reg_vcalkl = (u16)reg_val & (~AW88261_EF_VSN_GESLP_L_MASK);
reg_vcalk = (reg_vcalk >> AW88261_VCALK_SHIFT) & (reg_vcalkl >> AW88261_VCALKL_SHIFT);
if (reg_vcalk & AW88261_EF_VSN_GESLP_SIGN_MASK)
reg_vcalk = reg_vcalk | (~AW88261_EF_VSN_GESLP_NEG);
*vcalk = (int16_t)reg_vcalk;
return ret;
}
static int aw88261_dev_set_vcalb(struct aw_device *aw_dev)
{
int16_t icalk_val, vcalk_val;
int icalk, vcalk, vcalb;
u32 reg_val;
int ret;
ret = aw88261_dev_get_icalk(aw_dev, &icalk_val);
if (ret)
return ret;
ret = aw88261_dev_get_vcalk(aw_dev, &vcalk_val);
if (ret)
return ret;
icalk = AW88261_CABL_BASE_VALUE + AW88261_ICABLK_FACTOR * icalk_val;
vcalk = AW88261_CABL_BASE_VALUE + AW88261_VCABLK_FACTOR * vcalk_val;
if (!vcalk)
return -EINVAL;
vcalb = AW88261_VCAL_FACTOR * icalk / vcalk;
reg_val = (unsigned int)vcalb;
dev_dbg(aw_dev->dev, "icalk=%d, vcalk=%d, vcalb=%d, reg_val=0x%04x",
icalk, vcalk, vcalb, reg_val);
ret = regmap_write(aw_dev->regmap, AW88261_VSNTM1_REG, reg_val);
return ret;
}
static int aw88261_dev_reg_update(struct aw88261 *aw88261,
unsigned char *data, unsigned int len)
{
struct aw_device *aw_dev = aw88261->aw_pa;
struct aw_volume_desc *vol_desc = &aw_dev->volume_desc;
unsigned int read_val, efcheck_val, read_vol;
int data_len, i, ret;
int16_t *reg_data;
u16 reg_val;
u8 reg_addr;
if (!len || !data) {
dev_err(aw_dev->dev, "reg data is null or len is 0");
return -EINVAL;
}
reg_data = (int16_t *)data;
data_len = len >> 1;
if (data_len & 0x1) {
dev_err(aw_dev->dev, "data len:%d unsupported", data_len);
return -EINVAL;
}
for (i = 0; i < data_len; i += 2) {
reg_addr = reg_data[i];
reg_val = reg_data[i + 1];
if (reg_addr == AW88261_SYSCTRL_REG) {
aw88261->amppd_st = reg_val & (~AW88261_AMPPD_MASK);
ret = regmap_read(aw_dev->regmap, reg_addr, &read_val);
if (ret)
break;
read_val &= (~AW88261_AMPPD_MASK) | (~AW88261_PWDN_MASK) |
(~AW88261_HMUTE_MASK);
reg_val &= (AW88261_AMPPD_MASK | AW88261_PWDN_MASK | AW88261_HMUTE_MASK);
reg_val |= read_val;
/* enable uls hmute */
reg_val &= AW88261_ULS_HMUTE_MASK;
reg_val |= AW88261_ULS_HMUTE_ENABLE_VALUE;
}
if (reg_addr == AW88261_DBGCTRL_REG) {
efcheck_val = reg_val & (~AW88261_EF_DBMD_MASK);
if (efcheck_val == AW88261_OR_VALUE)
aw88261->efuse_check = AW88261_EF_OR_CHECK;
else
aw88261->efuse_check = AW88261_EF_AND_CHECK;
}
/* i2stxen */
if (reg_addr == AW88261_I2SCTRL3_REG) {
/* close tx */
reg_val &= AW88261_I2STXEN_MASK;
reg_val |= AW88261_I2STXEN_DISABLE_VALUE;
}
if (reg_addr == AW88261_SYSCTRL2_REG) {
read_vol = (reg_val & (~AW88261_VOL_MASK)) >>
AW88261_VOL_START_BIT;
aw_dev->volume_desc.init_volume =
REG_VAL_TO_DB(read_vol);
}
if (reg_addr == AW88261_VSNTM1_REG)
continue;
ret = regmap_write(aw_dev->regmap, reg_addr, reg_val);
if (ret)
break;
}
ret = aw88261_dev_set_vcalb(aw_dev);
if (ret)
return ret;
if (aw_dev->prof_cur != aw_dev->prof_index)
vol_desc->ctl_volume = 0;
/* keep min volume */
aw88261_dev_set_volume(aw_dev, vol_desc->mute_volume);
return ret;
}
static char *aw88261_dev_get_prof_name(struct aw_device *aw_dev, int index)
{
struct aw_prof_info *prof_info = &aw_dev->prof_info;
struct aw_prof_desc *prof_desc;
if ((index >= aw_dev->prof_info.count) || (index < 0)) {
dev_err(aw_dev->dev, "index[%d] overflow count[%d]",
index, aw_dev->prof_info.count);
return NULL;
}
prof_desc = &aw_dev->prof_info.prof_desc[index];
return prof_info->prof_name_list[prof_desc->id];
}
static int aw88261_dev_get_prof_data(struct aw_device *aw_dev, int index,
struct aw_prof_desc **prof_desc)
{
if ((index >= aw_dev->prof_info.count) || (index < 0)) {
dev_err(aw_dev->dev, "%s: index[%d] overflow count[%d]\n",
__func__, index, aw_dev->prof_info.count);
return -EINVAL;
}
*prof_desc = &aw_dev->prof_info.prof_desc[index];
return 0;
}
static int aw88261_dev_fw_update(struct aw88261 *aw88261)
{
struct aw_device *aw_dev = aw88261->aw_pa;
struct aw_prof_desc *prof_index_desc;
struct aw_sec_data_desc *sec_desc;
char *prof_name;
int ret;
prof_name = aw88261_dev_get_prof_name(aw_dev, aw_dev->prof_index);
if (!prof_name) {
dev_err(aw_dev->dev, "get prof name failed");
return -EINVAL;
}
dev_dbg(aw_dev->dev, "start update %s", prof_name);
ret = aw88261_dev_get_prof_data(aw_dev, aw_dev->prof_index, &prof_index_desc);
if (ret)
return ret;
/* update reg */
sec_desc = prof_index_desc->sec_desc;
ret = aw88261_dev_reg_update(aw88261, sec_desc[AW88395_DATA_TYPE_REG].data,
sec_desc[AW88395_DATA_TYPE_REG].len);
if (ret) {
dev_err(aw_dev->dev, "update reg failed");
return ret;
}
aw_dev->prof_cur = aw_dev->prof_index;
return ret;
}
static int aw88261_dev_start(struct aw88261 *aw88261)
{
struct aw_device *aw_dev = aw88261->aw_pa;
int ret;
if (aw_dev->status == AW88261_DEV_PW_ON) {
dev_info(aw_dev->dev, "already power on");
return 0;
}
/* power on */
aw88261_dev_pwd(aw_dev, false);
usleep_range(AW88261_2000_US, AW88261_2000_US + 10);
ret = aw88261_dev_check_syspll(aw_dev);
if (ret) {
dev_err(aw_dev->dev, "pll check failed cannot start");
goto pll_check_fail;
}
/* amppd on */
aw88261_dev_amppd(aw_dev, false);
usleep_range(AW88261_1000_US, AW88261_1000_US + 50);
/* check i2s status */
ret = aw88261_dev_check_sysst(aw_dev);
if (ret) {
dev_err(aw_dev->dev, "sysst check failed");
goto sysst_check_fail;
}
/* enable tx feedback */
aw88261_dev_i2s_tx_enable(aw_dev, true);
if (aw88261->amppd_st)
aw88261_dev_amppd(aw_dev, true);
aw88261_reg_force_set(aw88261);
/* close uls mute */
aw88261_dev_uls_hmute(aw_dev, false);
/* close mute */
if (!aw88261->mute_st)
aw88261_dev_mute(aw_dev, false);
/* clear inturrupt */
aw88261_dev_clear_int_status(aw_dev);
aw_dev->status = AW88261_DEV_PW_ON;
return 0;
sysst_check_fail:
aw88261_dev_i2s_tx_enable(aw_dev, false);
aw88261_dev_clear_int_status(aw_dev);
aw88261_dev_amppd(aw_dev, true);
pll_check_fail:
aw88261_dev_pwd(aw_dev, true);
aw_dev->status = AW88261_DEV_PW_OFF;
return ret;
}
static int aw88261_dev_stop(struct aw_device *aw_dev)
{
if (aw_dev->status == AW88261_DEV_PW_OFF) {
dev_info(aw_dev->dev, "already power off");
return 0;
}
aw_dev->status = AW88261_DEV_PW_OFF;
/* clear inturrupt */
aw88261_dev_clear_int_status(aw_dev);
aw88261_dev_uls_hmute(aw_dev, true);
/* set mute */
aw88261_dev_mute(aw_dev, true);
/* close tx feedback */
aw88261_dev_i2s_tx_enable(aw_dev, false);
usleep_range(AW88261_1000_US, AW88261_1000_US + 100);
/* enable amppd */
aw88261_dev_amppd(aw_dev, true);
/* set power down */
aw88261_dev_pwd(aw_dev, true);
return 0;
}
static int aw88261_reg_update(struct aw88261 *aw88261, bool force)
{
struct aw_device *aw_dev = aw88261->aw_pa;
int ret;
if (force) {
ret = regmap_write(aw_dev->regmap,
AW88261_ID_REG, AW88261_SOFT_RESET_VALUE);
if (ret)
return ret;
ret = aw88261_dev_fw_update(aw88261);
if (ret)
return ret;
} else {
if (aw_dev->prof_cur != aw_dev->prof_index) {
ret = aw88261_dev_fw_update(aw88261);
if (ret)
return ret;
} else {
ret = 0;
}
}
aw_dev->prof_cur = aw_dev->prof_index;
return ret;
}
static void aw88261_start_pa(struct aw88261 *aw88261)
{
int ret, i;
for (i = 0; i < AW88261_START_RETRIES; i++) {
ret = aw88261_reg_update(aw88261, aw88261->phase_sync);
if (ret) {
dev_err(aw88261->aw_pa->dev, "fw update failed, cnt:%d\n", i);
continue;
}
ret = aw88261_dev_start(aw88261);
if (ret) {
dev_err(aw88261->aw_pa->dev, "aw88261 device start failed. retry = %d", i);
continue;
} else {
dev_info(aw88261->aw_pa->dev, "start success\n");
break;
}
}
}
static void aw88261_startup_work(struct work_struct *work)
{
struct aw88261 *aw88261 =
container_of(work, struct aw88261, start_work.work);
mutex_lock(&aw88261->lock);
aw88261_start_pa(aw88261);
mutex_unlock(&aw88261->lock);
}
static void aw88261_start(struct aw88261 *aw88261, bool sync_start)
{
if (aw88261->aw_pa->fw_status != AW88261_DEV_FW_OK)
return;
if (aw88261->aw_pa->status == AW88261_DEV_PW_ON)
return;
if (sync_start == AW88261_SYNC_START)
aw88261_start_pa(aw88261);
else
queue_delayed_work(system_wq,
&aw88261->start_work,
AW88261_START_WORK_DELAY_MS);
}
static struct snd_soc_dai_driver aw88261_dai[] = {
{
.name = "aw88261-aif",
.id = 1,
.playback = {
.stream_name = "Speaker_Playback",
.channels_min = 1,
.channels_max = 2,
.rates = AW88261_RATES,
.formats = AW88261_FORMATS,
},
.capture = {
.stream_name = "Speaker_Capture",
.channels_min = 1,
.channels_max = 2,
.rates = AW88261_RATES,
.formats = AW88261_FORMATS,
},
},
};
static int aw88261_get_fade_in_time(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct aw88261 *aw88261 = snd_soc_component_get_drvdata(component);
struct aw_device *aw_dev = aw88261->aw_pa;
ucontrol->value.integer.value[0] = aw_dev->fade_in_time;
return 0;
}
static int aw88261_set_fade_in_time(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct aw88261 *aw88261 = snd_soc_component_get_drvdata(component);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct aw_device *aw_dev = aw88261->aw_pa;
int time;
time = ucontrol->value.integer.value[0];
if (time < mc->min || time > mc->max)
return -EINVAL;
if (time != aw_dev->fade_in_time) {
aw_dev->fade_in_time = time;
return 1;
}
return 0;
}
static int aw88261_get_fade_out_time(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct aw88261 *aw88261 = snd_soc_component_get_drvdata(component);
struct aw_device *aw_dev = aw88261->aw_pa;
ucontrol->value.integer.value[0] = aw_dev->fade_out_time;
return 0;
}
static int aw88261_set_fade_out_time(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct aw88261 *aw88261 = snd_soc_component_get_drvdata(component);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct aw_device *aw_dev = aw88261->aw_pa;
int time;
time = ucontrol->value.integer.value[0];
if (time < mc->min || time > mc->max)
return -EINVAL;
if (time != aw_dev->fade_out_time) {
aw_dev->fade_out_time = time;
return 1;
}
return 0;
}
static int aw88261_dev_set_profile_index(struct aw_device *aw_dev, int index)
{
/* check the index whether is valid */
if ((index >= aw_dev->prof_info.count) || (index < 0))
return -EINVAL;
/* check the index whether change */
if (aw_dev->prof_index == index)
return -EPERM;
aw_dev->prof_index = index;
return 0;
}
static int aw88261_profile_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct aw88261 *aw88261 = snd_soc_component_get_drvdata(codec);
const char *prof_name;
char *name;
int count;
uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
uinfo->count = 1;
count = aw88261->aw_pa->prof_info.count;
if (count <= 0) {
uinfo->value.enumerated.items = 0;
return 0;
}
uinfo->value.enumerated.items = count;
if (uinfo->value.enumerated.item >= count)
uinfo->value.enumerated.item = count - 1;
name = uinfo->value.enumerated.name;
count = uinfo->value.enumerated.item;
prof_name = aw88261_dev_get_prof_name(aw88261->aw_pa, count);
if (!prof_name) {
strscpy(uinfo->value.enumerated.name, "null",
strlen("null") + 1);
return 0;
}
strscpy(name, prof_name, sizeof(uinfo->value.enumerated.name));
return 0;
}
static int aw88261_profile_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct aw88261 *aw88261 = snd_soc_component_get_drvdata(codec);
ucontrol->value.integer.value[0] = aw88261->aw_pa->prof_index;
return 0;
}
static int aw88261_profile_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct aw88261 *aw88261 = snd_soc_component_get_drvdata(codec);
int ret;
/* pa stop or stopping just set profile */
mutex_lock(&aw88261->lock);
ret = aw88261_dev_set_profile_index(aw88261->aw_pa, ucontrol->value.integer.value[0]);
if (ret) {
dev_dbg(codec->dev, "profile index does not change");
mutex_unlock(&aw88261->lock);
return 0;
}
if (aw88261->aw_pa->status) {
aw88261_dev_stop(aw88261->aw_pa);
aw88261_start(aw88261, AW88261_SYNC_START);
}
mutex_unlock(&aw88261->lock);
return 1;
}
static int aw88261_volume_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct aw88261 *aw88261 = snd_soc_component_get_drvdata(codec);
struct aw_volume_desc *vol_desc = &aw88261->aw_pa->volume_desc;
ucontrol->value.integer.value[0] = vol_desc->ctl_volume;
return 0;
}
static int aw88261_volume_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct aw88261 *aw88261 = snd_soc_component_get_drvdata(codec);
struct aw_volume_desc *vol_desc = &aw88261->aw_pa->volume_desc;
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
int value;
value = ucontrol->value.integer.value[0];
if (value < mc->min || value > mc->max)
return -EINVAL;
if (vol_desc->ctl_volume != value) {
vol_desc->ctl_volume = value;
aw88261_dev_set_volume(aw88261->aw_pa, vol_desc->ctl_volume);
return 1;
}
return 0;
}
static int aw88261_get_fade_step(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct aw88261 *aw88261 = snd_soc_component_get_drvdata(codec);
ucontrol->value.integer.value[0] = aw88261->aw_pa->fade_step;
return 0;
}
static int aw88261_set_fade_step(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct aw88261 *aw88261 = snd_soc_component_get_drvdata(codec);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
int value;
value = ucontrol->value.integer.value[0];
if (value < mc->min || value > mc->max)
return -EINVAL;
if (aw88261->aw_pa->fade_step != value) {
aw88261->aw_pa->fade_step = value;
return 1;
}
return 0;
}
static const struct snd_kcontrol_new aw88261_controls[] = {
SOC_SINGLE_EXT("PCM Playback Volume", AW88261_SYSCTRL2_REG,
6, AW88261_MUTE_VOL, 0, aw88261_volume_get,
aw88261_volume_set),
SOC_SINGLE_EXT("Fade Step", 0, 0, AW88261_MUTE_VOL, 0,
aw88261_get_fade_step, aw88261_set_fade_step),
SOC_SINGLE_EXT("Volume Ramp Up Step", 0, 0, FADE_TIME_MAX, FADE_TIME_MIN,
aw88261_get_fade_in_time, aw88261_set_fade_in_time),
SOC_SINGLE_EXT("Volume Ramp Down Step", 0, 0, FADE_TIME_MAX, FADE_TIME_MIN,
aw88261_get_fade_out_time, aw88261_set_fade_out_time),
AW88261_PROFILE_EXT("Profile Set", aw88261_profile_info,
aw88261_profile_get, aw88261_profile_set),
};
static int aw88261_playback_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *k, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct aw88261 *aw88261 = snd_soc_component_get_drvdata(component);
mutex_lock(&aw88261->lock);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
aw88261_start(aw88261, AW88261_ASYNC_START);
break;
case SND_SOC_DAPM_POST_PMD:
aw88261_dev_stop(aw88261->aw_pa);
break;
default:
break;
}
mutex_unlock(&aw88261->lock);
return 0;
}
static const struct snd_soc_dapm_widget aw88261_dapm_widgets[] = {
/* playback */
SND_SOC_DAPM_AIF_IN_E("AIF_RX", "Speaker_Playback", 0, 0, 0, 0,
aw88261_playback_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_OUTPUT("DAC Output"),
/* capture */
SND_SOC_DAPM_AIF_OUT("AIF_TX", "Speaker_Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_INPUT("ADC Input"),
};
static const struct snd_soc_dapm_route aw88261_audio_map[] = {
{"DAC Output", NULL, "AIF_RX"},
{"AIF_TX", NULL, "ADC Input"},
};
static int aw88261_frcset_check(struct aw88261 *aw88261)
{
unsigned int reg_val;
u16 temh, teml, tem;
int ret;
ret = regmap_read(aw88261->regmap, AW88261_EFRH3_REG, ®_val);
if (ret)
return ret;
temh = ((u16)reg_val & (~AW88261_TEMH_MASK));
ret = regmap_read(aw88261->regmap, AW88261_EFRL3_REG, ®_val);
if (ret)
return ret;
teml = ((u16)reg_val & (~AW88261_TEML_MASK));
if (aw88261->efuse_check == AW88261_EF_OR_CHECK)
tem = (temh | teml);
else
tem = (temh & teml);
if (tem == AW88261_DEFAULT_CFG)
aw88261->frcset_en = AW88261_FRCSET_ENABLE;
else
aw88261->frcset_en = AW88261_FRCSET_DISABLE;
dev_dbg(aw88261->aw_pa->dev, "tem is 0x%04x, frcset_en is %d",
tem, aw88261->frcset_en);
return ret;
}
static int aw88261_dev_init(struct aw88261 *aw88261, struct aw_container *aw_cfg)
{
struct aw_device *aw_dev = aw88261->aw_pa;
int ret;
ret = aw88395_dev_cfg_load(aw_dev, aw_cfg);
if (ret) {
dev_err(aw_dev->dev, "aw_dev acf parse failed");
return -EINVAL;
}
ret = regmap_write(aw_dev->regmap, AW88261_ID_REG, AW88261_SOFT_RESET_VALUE);
if (ret)
return ret;
aw_dev->fade_in_time = AW88261_500_US;
aw_dev->fade_out_time = AW88261_500_US;
aw_dev->prof_cur = AW88261_INIT_PROFILE;
aw_dev->prof_index = AW88261_INIT_PROFILE;
ret = aw88261_dev_fw_update(aw88261);
if (ret) {
dev_err(aw_dev->dev, "fw update failed ret = %d\n", ret);
return ret;
}
ret = aw88261_frcset_check(aw88261);
if (ret) {
dev_err(aw_dev->dev, "aw88261_frcset_check ret = %d\n", ret);
return ret;
}
aw88261_dev_clear_int_status(aw_dev);
aw88261_dev_uls_hmute(aw_dev, true);
aw88261_dev_mute(aw_dev, true);
aw88261_dev_i2s_tx_enable(aw_dev, false);
usleep_range(AW88261_1000_US, AW88261_1000_US + 100);
aw88261_dev_amppd(aw_dev, true);
aw88261_dev_pwd(aw_dev, true);
return 0;
}
static int aw88261_request_firmware_file(struct aw88261 *aw88261)
{
const struct firmware *cont = NULL;
int ret;
aw88261->aw_pa->fw_status = AW88261_DEV_FW_FAILED;
ret = request_firmware(&cont, AW88261_ACF_FILE, aw88261->aw_pa->dev);
if (ret)
return dev_err_probe(aw88261->aw_pa->dev, ret,
"load [%s] failed!", AW88261_ACF_FILE);
dev_info(aw88261->aw_pa->dev, "loaded %s - size: %zu\n",
AW88261_ACF_FILE, cont ? cont->size : 0);
aw88261->aw_cfg = devm_kzalloc(aw88261->aw_pa->dev, cont->size + sizeof(int), GFP_KERNEL);
if (!aw88261->aw_cfg) {
release_firmware(cont);
return -ENOMEM;
}
aw88261->aw_cfg->len = (int)cont->size;
memcpy(aw88261->aw_cfg->data, cont->data, cont->size);
release_firmware(cont);
ret = aw88395_dev_load_acf_check(aw88261->aw_pa, aw88261->aw_cfg);
if (ret) {
dev_err(aw88261->aw_pa->dev, "load [%s] failed !", AW88261_ACF_FILE);
return ret;
}
mutex_lock(&aw88261->lock);
/* aw device init */
ret = aw88261_dev_init(aw88261, aw88261->aw_cfg);
if (ret)
dev_err(aw88261->aw_pa->dev, "dev init failed");
mutex_unlock(&aw88261->lock);
return ret;
}
static int aw88261_codec_probe(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct aw88261 *aw88261 = snd_soc_component_get_drvdata(component);
int ret;
INIT_DELAYED_WORK(&aw88261->start_work, aw88261_startup_work);
ret = aw88261_request_firmware_file(aw88261);
if (ret)
return dev_err_probe(aw88261->aw_pa->dev, ret,
"aw88261_request_firmware_file failed\n");
/* add widgets */
ret = snd_soc_dapm_new_controls(dapm, aw88261_dapm_widgets,
ARRAY_SIZE(aw88261_dapm_widgets));
if (ret)
return ret;
/* add route */
ret = snd_soc_dapm_add_routes(dapm, aw88261_audio_map,
ARRAY_SIZE(aw88261_audio_map));
if (ret)
return ret;
ret = snd_soc_add_component_controls(component, aw88261_controls,
ARRAY_SIZE(aw88261_controls));
return ret;
}
static void aw88261_codec_remove(struct snd_soc_component *aw_codec)
{
struct aw88261 *aw88261 = snd_soc_component_get_drvdata(aw_codec);
cancel_delayed_work_sync(&aw88261->start_work);
}
static const struct snd_soc_component_driver soc_codec_dev_aw88261 = {
.probe = aw88261_codec_probe,
.remove = aw88261_codec_remove,
};
static void aw88261_hw_reset(struct aw88261 *aw88261)
{
gpiod_set_value_cansleep(aw88261->reset_gpio, 0);
usleep_range(AW88261_1000_US, AW88261_1000_US + 10);
gpiod_set_value_cansleep(aw88261->reset_gpio, 1);
usleep_range(AW88261_1000_US, AW88261_1000_US + 10);
}
static void aw88261_parse_channel_dt(struct aw88261 *aw88261)
{
struct aw_device *aw_dev = aw88261->aw_pa;
struct device_node *np = aw_dev->dev->of_node;
u32 channel_value = AW88261_DEV_DEFAULT_CH;
u32 sync_enable = false;
of_property_read_u32(np, "sound-channel", &channel_value);
of_property_read_u32(np, "sync-flag", &sync_enable);
aw_dev->channel = channel_value;
aw88261->phase_sync = sync_enable;
}
static int aw88261_init(struct aw88261 **aw88261, struct i2c_client *i2c, struct regmap *regmap)
{
struct aw_device *aw_dev;
unsigned int chip_id;
int ret;
/* read chip id */
ret = regmap_read(regmap, AW88261_ID_REG, &chip_id);
if (ret) {
dev_err(&i2c->dev, "%s read chipid error. ret = %d", __func__, ret);
return ret;
}
if (chip_id != AW88261_CHIP_ID) {
dev_err(&i2c->dev, "unsupported device");
return -ENXIO;
}
dev_info(&i2c->dev, "chip id = %x\n", chip_id);
aw_dev = devm_kzalloc(&i2c->dev, sizeof(*aw_dev), GFP_KERNEL);
if (!aw_dev)
return -ENOMEM;
(*aw88261)->aw_pa = aw_dev;
aw_dev->i2c = i2c;
aw_dev->regmap = regmap;
aw_dev->dev = &i2c->dev;
aw_dev->chip_id = AW88261_CHIP_ID;
aw_dev->acf = NULL;
aw_dev->prof_info.prof_desc = NULL;
aw_dev->prof_info.count = 0;
aw_dev->prof_info.prof_type = AW88395_DEV_NONE_TYPE_ID;
aw_dev->channel = 0;
aw_dev->fw_status = AW88261_DEV_FW_FAILED;
aw_dev->fade_step = AW88261_VOLUME_STEP_DB;
aw_dev->volume_desc.ctl_volume = AW88261_VOL_DEFAULT_VALUE;
aw_dev->volume_desc.mute_volume = AW88261_MUTE_VOL;
aw88261_parse_channel_dt(*aw88261);
return ret;
}
static int aw88261_i2c_probe(struct i2c_client *i2c)
{
struct aw88261 *aw88261;
int ret;
ret = i2c_check_functionality(i2c->adapter, I2C_FUNC_I2C);
if (!ret)
return dev_err_probe(&i2c->dev, -ENXIO, "check_functionality failed");
aw88261 = devm_kzalloc(&i2c->dev, sizeof(*aw88261), GFP_KERNEL);
if (!aw88261)
return -ENOMEM;
mutex_init(&aw88261->lock);
i2c_set_clientdata(i2c, aw88261);
aw88261->reset_gpio = devm_gpiod_get_optional(&i2c->dev, "reset", GPIOD_OUT_LOW);
if (IS_ERR(aw88261->reset_gpio))
dev_info(&i2c->dev, "reset gpio not defined\n");
else
aw88261_hw_reset(aw88261);
aw88261->regmap = devm_regmap_init_i2c(i2c, &aw88261_remap_config);
if (IS_ERR(aw88261->regmap)) {
ret = PTR_ERR(aw88261->regmap);
return dev_err_probe(&i2c->dev, ret, "failed to init regmap: %d\n", ret);
}
/* aw pa init */
ret = aw88261_init(&aw88261, i2c, aw88261->regmap);
if (ret)
return ret;
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_codec_dev_aw88261,
aw88261_dai, ARRAY_SIZE(aw88261_dai));
if (ret)
dev_err(&i2c->dev, "failed to register aw88261: %d", ret);
return ret;
}
static const struct i2c_device_id aw88261_i2c_id[] = {
{ AW88261_I2C_NAME, 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, aw88261_i2c_id);
static struct i2c_driver aw88261_i2c_driver = {
.driver = {
.name = AW88261_I2C_NAME,
},
.probe = aw88261_i2c_probe,
.id_table = aw88261_i2c_id,
};
module_i2c_driver(aw88261_i2c_driver);
MODULE_DESCRIPTION("ASoC AW88261 Smart PA Driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/aw88261.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ALSA SoC driver for
* Asahi Kasei AK5386 Single-ended 24-Bit 192kHz delta-sigma ADC
*
* (c) 2013 Daniel Mack <[email protected]>
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/of_device.h>
#include <linux/regulator/consumer.h>
#include <sound/soc.h>
#include <sound/pcm.h>
#include <sound/initval.h>
static const char * const supply_names[] = {
"va", "vd"
};
struct ak5386_priv {
int reset_gpio;
struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
};
static const struct snd_soc_dapm_widget ak5386_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("AINL"),
SND_SOC_DAPM_INPUT("AINR"),
};
static const struct snd_soc_dapm_route ak5386_dapm_routes[] = {
{ "Capture", NULL, "AINL" },
{ "Capture", NULL, "AINR" },
};
static int ak5386_soc_probe(struct snd_soc_component *component)
{
struct ak5386_priv *priv = snd_soc_component_get_drvdata(component);
return regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
}
static void ak5386_soc_remove(struct snd_soc_component *component)
{
struct ak5386_priv *priv = snd_soc_component_get_drvdata(component);
regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies);
}
#ifdef CONFIG_PM
static int ak5386_soc_suspend(struct snd_soc_component *component)
{
struct ak5386_priv *priv = snd_soc_component_get_drvdata(component);
regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies);
return 0;
}
static int ak5386_soc_resume(struct snd_soc_component *component)
{
struct ak5386_priv *priv = snd_soc_component_get_drvdata(component);
return regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
}
#else
#define ak5386_soc_suspend NULL
#define ak5386_soc_resume NULL
#endif /* CONFIG_PM */
static const struct snd_soc_component_driver soc_component_ak5386 = {
.probe = ak5386_soc_probe,
.remove = ak5386_soc_remove,
.suspend = ak5386_soc_suspend,
.resume = ak5386_soc_resume,
.dapm_widgets = ak5386_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(ak5386_dapm_widgets),
.dapm_routes = ak5386_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(ak5386_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int ak5386_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int format)
{
struct snd_soc_component *component = codec_dai->component;
format &= SND_SOC_DAIFMT_FORMAT_MASK;
if (format != SND_SOC_DAIFMT_LEFT_J &&
format != SND_SOC_DAIFMT_I2S) {
dev_err(component->dev, "Invalid DAI format\n");
return -EINVAL;
}
return 0;
}
static int ak5386_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct ak5386_priv *priv = snd_soc_component_get_drvdata(component);
/*
* From the datasheet:
*
* All external clocks (MCLK, SCLK and LRCK) must be present unless
* PDN pin = “L”. If these clocks are not provided, the AK5386 may
* draw excess current due to its use of internal dynamically
* refreshed logic. If the external clocks are not present, place
* the AK5386 in power-down mode (PDN pin = “L”).
*/
if (gpio_is_valid(priv->reset_gpio))
gpio_set_value(priv->reset_gpio, 1);
return 0;
}
static int ak5386_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct ak5386_priv *priv = snd_soc_component_get_drvdata(component);
if (gpio_is_valid(priv->reset_gpio))
gpio_set_value(priv->reset_gpio, 0);
return 0;
}
static const struct snd_soc_dai_ops ak5386_dai_ops = {
.set_fmt = ak5386_set_dai_fmt,
.hw_params = ak5386_hw_params,
.hw_free = ak5386_hw_free,
};
static struct snd_soc_dai_driver ak5386_dai = {
.name = "ak5386-hifi",
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S24_3LE,
},
.ops = &ak5386_dai_ops,
};
#ifdef CONFIG_OF
static const struct of_device_id ak5386_dt_ids[] = {
{ .compatible = "asahi-kasei,ak5386", },
{ }
};
MODULE_DEVICE_TABLE(of, ak5386_dt_ids);
#endif
static int ak5386_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct ak5386_priv *priv;
int ret, i;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->reset_gpio = -EINVAL;
dev_set_drvdata(dev, priv);
for (i = 0; i < ARRAY_SIZE(supply_names); i++)
priv->supplies[i].supply = supply_names[i];
ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(priv->supplies),
priv->supplies);
if (ret < 0)
return ret;
if (of_match_device(of_match_ptr(ak5386_dt_ids), dev))
priv->reset_gpio = of_get_named_gpio(dev->of_node,
"reset-gpio", 0);
if (gpio_is_valid(priv->reset_gpio))
if (devm_gpio_request_one(dev, priv->reset_gpio,
GPIOF_OUT_INIT_LOW,
"AK5386 Reset"))
priv->reset_gpio = -EINVAL;
return devm_snd_soc_register_component(dev, &soc_component_ak5386,
&ak5386_dai, 1);
}
static struct platform_driver ak5386_driver = {
.probe = ak5386_probe,
.driver = {
.name = "ak5386",
.of_match_table = of_match_ptr(ak5386_dt_ids),
},
};
module_platform_driver(ak5386_driver);
MODULE_DESCRIPTION("ASoC driver for AK5386 ADC");
MODULE_AUTHOR("Daniel Mack <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/ak5386.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* cs35l32.c -- CS35L32 ALSA SoC audio driver
*
* Copyright 2014 CirrusLogic, Inc.
*
* Author: Brian Austin <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/gpio.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/gpio/consumer.h>
#include <linux/of_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <dt-bindings/sound/cs35l32.h>
#include "cs35l32.h"
#include "cirrus_legacy.h"
#define CS35L32_NUM_SUPPLIES 2
static const char *const cs35l32_supply_names[CS35L32_NUM_SUPPLIES] = {
"VA",
"VP",
};
struct cs35l32_private {
struct regmap *regmap;
struct snd_soc_component *component;
struct regulator_bulk_data supplies[CS35L32_NUM_SUPPLIES];
struct cs35l32_platform_data pdata;
struct gpio_desc *reset_gpio;
};
static const struct reg_default cs35l32_reg_defaults[] = {
{ 0x06, 0x04 }, /* Power Ctl 1 */
{ 0x07, 0xE8 }, /* Power Ctl 2 */
{ 0x08, 0x40 }, /* Clock Ctl */
{ 0x09, 0x20 }, /* Low Battery Threshold */
{ 0x0A, 0x00 }, /* Voltage Monitor [RO] */
{ 0x0B, 0x40 }, /* Conv Peak Curr Protection CTL */
{ 0x0C, 0x07 }, /* IMON Scaling */
{ 0x0D, 0x03 }, /* Audio/LED Pwr Manager */
{ 0x0F, 0x20 }, /* Serial Port Control */
{ 0x10, 0x14 }, /* Class D Amp CTL */
{ 0x11, 0x00 }, /* Protection Release CTL */
{ 0x12, 0xFF }, /* Interrupt Mask 1 */
{ 0x13, 0xFF }, /* Interrupt Mask 2 */
{ 0x14, 0xFF }, /* Interrupt Mask 3 */
{ 0x19, 0x00 }, /* LED Flash Mode Current */
{ 0x1A, 0x00 }, /* LED Movie Mode Current */
{ 0x1B, 0x20 }, /* LED Flash Timer */
{ 0x1C, 0x00 }, /* LED Flash Inhibit Current */
};
static bool cs35l32_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS35L32_DEVID_AB ... CS35L32_AUDIO_LED_MNGR:
case CS35L32_ADSP_CTL ... CS35L32_FLASH_INHIBIT:
return true;
default:
return false;
}
}
static bool cs35l32_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS35L32_DEVID_AB ... CS35L32_REV_ID:
case CS35L32_INT_STATUS_1 ... CS35L32_LED_STATUS:
return true;
default:
return false;
}
}
static bool cs35l32_precious_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS35L32_INT_STATUS_1 ... CS35L32_LED_STATUS:
return true;
default:
return false;
}
}
static DECLARE_TLV_DB_SCALE(classd_ctl_tlv, 900, 300, 0);
static const struct snd_kcontrol_new imon_ctl =
SOC_DAPM_SINGLE("Switch", CS35L32_PWRCTL2, 6, 1, 1);
static const struct snd_kcontrol_new vmon_ctl =
SOC_DAPM_SINGLE("Switch", CS35L32_PWRCTL2, 7, 1, 1);
static const struct snd_kcontrol_new vpmon_ctl =
SOC_DAPM_SINGLE("Switch", CS35L32_PWRCTL2, 5, 1, 1);
static const struct snd_kcontrol_new cs35l32_snd_controls[] = {
SOC_SINGLE_TLV("Speaker Volume", CS35L32_CLASSD_CTL,
3, 0x04, 1, classd_ctl_tlv),
SOC_SINGLE("Zero Cross Switch", CS35L32_CLASSD_CTL, 2, 1, 0),
SOC_SINGLE("Gain Manager Switch", CS35L32_AUDIO_LED_MNGR, 3, 1, 0),
};
static const struct snd_soc_dapm_widget cs35l32_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("BOOST", CS35L32_PWRCTL1, 2, 1, NULL, 0),
SND_SOC_DAPM_OUT_DRV("Speaker", CS35L32_PWRCTL1, 7, 1, NULL, 0),
SND_SOC_DAPM_AIF_OUT("SDOUT", NULL, 0, CS35L32_PWRCTL2, 3, 1),
SND_SOC_DAPM_INPUT("VP"),
SND_SOC_DAPM_INPUT("ISENSE"),
SND_SOC_DAPM_INPUT("VSENSE"),
SND_SOC_DAPM_SWITCH("VMON ADC", CS35L32_PWRCTL2, 7, 1, &vmon_ctl),
SND_SOC_DAPM_SWITCH("IMON ADC", CS35L32_PWRCTL2, 6, 1, &imon_ctl),
SND_SOC_DAPM_SWITCH("VPMON ADC", CS35L32_PWRCTL2, 5, 1, &vpmon_ctl),
};
static const struct snd_soc_dapm_route cs35l32_audio_map[] = {
{"Speaker", NULL, "BOOST"},
{"VMON ADC", NULL, "VSENSE"},
{"IMON ADC", NULL, "ISENSE"},
{"VPMON ADC", NULL, "VP"},
{"SDOUT", "Switch", "VMON ADC"},
{"SDOUT", "Switch", "IMON ADC"},
{"SDOUT", "Switch", "VPMON ADC"},
{"Capture", NULL, "SDOUT"},
};
static int cs35l32_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
snd_soc_component_update_bits(component, CS35L32_ADSP_CTL,
CS35L32_ADSP_MASTER_MASK,
CS35L32_ADSP_MASTER_MASK);
break;
case SND_SOC_DAIFMT_CBS_CFS:
snd_soc_component_update_bits(component, CS35L32_ADSP_CTL,
CS35L32_ADSP_MASTER_MASK, 0);
break;
default:
return -EINVAL;
}
return 0;
}
static int cs35l32_set_tristate(struct snd_soc_dai *dai, int tristate)
{
struct snd_soc_component *component = dai->component;
return snd_soc_component_update_bits(component, CS35L32_PWRCTL2,
CS35L32_SDOUT_3ST, tristate << 3);
}
static const struct snd_soc_dai_ops cs35l32_ops = {
.set_fmt = cs35l32_set_dai_fmt,
.set_tristate = cs35l32_set_tristate,
};
static struct snd_soc_dai_driver cs35l32_dai[] = {
{
.name = "cs35l32-monitor",
.id = 0,
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = CS35L32_RATES,
.formats = CS35L32_FORMATS,
},
.ops = &cs35l32_ops,
.symmetric_rate = 1,
}
};
static int cs35l32_component_set_sysclk(struct snd_soc_component *component,
int clk_id, int source, unsigned int freq, int dir)
{
unsigned int val;
switch (freq) {
case 6000000:
val = CS35L32_MCLK_RATIO;
break;
case 12000000:
val = CS35L32_MCLK_DIV2_MASK | CS35L32_MCLK_RATIO;
break;
case 6144000:
val = 0;
break;
case 12288000:
val = CS35L32_MCLK_DIV2_MASK;
break;
default:
return -EINVAL;
}
return snd_soc_component_update_bits(component, CS35L32_CLK_CTL,
CS35L32_MCLK_DIV2_MASK | CS35L32_MCLK_RATIO_MASK, val);
}
static const struct snd_soc_component_driver soc_component_dev_cs35l32 = {
.set_sysclk = cs35l32_component_set_sysclk,
.controls = cs35l32_snd_controls,
.num_controls = ARRAY_SIZE(cs35l32_snd_controls),
.dapm_widgets = cs35l32_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(cs35l32_dapm_widgets),
.dapm_routes = cs35l32_audio_map,
.num_dapm_routes = ARRAY_SIZE(cs35l32_audio_map),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
/* Current and threshold powerup sequence Pg37 in datasheet */
static const struct reg_sequence cs35l32_monitor_patch[] = {
{ 0x00, 0x99 },
{ 0x48, 0x17 },
{ 0x49, 0x56 },
{ 0x43, 0x01 },
{ 0x3B, 0x62 },
{ 0x3C, 0x80 },
{ 0x00, 0x00 },
};
static const struct regmap_config cs35l32_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = CS35L32_MAX_REGISTER,
.reg_defaults = cs35l32_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(cs35l32_reg_defaults),
.volatile_reg = cs35l32_volatile_register,
.readable_reg = cs35l32_readable_register,
.precious_reg = cs35l32_precious_register,
.cache_type = REGCACHE_MAPLE,
.use_single_read = true,
.use_single_write = true,
};
static int cs35l32_handle_of_data(struct i2c_client *i2c_client,
struct cs35l32_platform_data *pdata)
{
struct device_node *np = i2c_client->dev.of_node;
unsigned int val;
if (of_property_read_u32(np, "cirrus,sdout-share", &val) >= 0)
pdata->sdout_share = val;
if (of_property_read_u32(np, "cirrus,boost-manager", &val))
val = -1u;
switch (val) {
case CS35L32_BOOST_MGR_AUTO:
case CS35L32_BOOST_MGR_AUTO_AUDIO:
case CS35L32_BOOST_MGR_BYPASS:
case CS35L32_BOOST_MGR_FIXED:
pdata->boost_mng = val;
break;
case -1u:
default:
dev_err(&i2c_client->dev,
"Wrong cirrus,boost-manager DT value %d\n", val);
pdata->boost_mng = CS35L32_BOOST_MGR_BYPASS;
}
if (of_property_read_u32(np, "cirrus,sdout-datacfg", &val))
val = -1u;
switch (val) {
case CS35L32_DATA_CFG_LR_VP:
case CS35L32_DATA_CFG_LR_STAT:
case CS35L32_DATA_CFG_LR:
case CS35L32_DATA_CFG_LR_VPSTAT:
pdata->sdout_datacfg = val;
break;
case -1u:
default:
dev_err(&i2c_client->dev,
"Wrong cirrus,sdout-datacfg DT value %d\n", val);
pdata->sdout_datacfg = CS35L32_DATA_CFG_LR;
}
if (of_property_read_u32(np, "cirrus,battery-threshold", &val))
val = -1u;
switch (val) {
case CS35L32_BATT_THRESH_3_1V:
case CS35L32_BATT_THRESH_3_2V:
case CS35L32_BATT_THRESH_3_3V:
case CS35L32_BATT_THRESH_3_4V:
pdata->batt_thresh = val;
break;
case -1u:
default:
dev_err(&i2c_client->dev,
"Wrong cirrus,battery-threshold DT value %d\n", val);
pdata->batt_thresh = CS35L32_BATT_THRESH_3_3V;
}
if (of_property_read_u32(np, "cirrus,battery-recovery", &val))
val = -1u;
switch (val) {
case CS35L32_BATT_RECOV_3_1V:
case CS35L32_BATT_RECOV_3_2V:
case CS35L32_BATT_RECOV_3_3V:
case CS35L32_BATT_RECOV_3_4V:
case CS35L32_BATT_RECOV_3_5V:
case CS35L32_BATT_RECOV_3_6V:
pdata->batt_recov = val;
break;
case -1u:
default:
dev_err(&i2c_client->dev,
"Wrong cirrus,battery-recovery DT value %d\n", val);
pdata->batt_recov = CS35L32_BATT_RECOV_3_4V;
}
return 0;
}
static int cs35l32_i2c_probe(struct i2c_client *i2c_client)
{
struct cs35l32_private *cs35l32;
struct cs35l32_platform_data *pdata =
dev_get_platdata(&i2c_client->dev);
int ret, i, devid;
unsigned int reg;
cs35l32 = devm_kzalloc(&i2c_client->dev, sizeof(*cs35l32), GFP_KERNEL);
if (!cs35l32)
return -ENOMEM;
i2c_set_clientdata(i2c_client, cs35l32);
cs35l32->regmap = devm_regmap_init_i2c(i2c_client, &cs35l32_regmap);
if (IS_ERR(cs35l32->regmap)) {
ret = PTR_ERR(cs35l32->regmap);
dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
return ret;
}
if (pdata) {
cs35l32->pdata = *pdata;
} else {
pdata = devm_kzalloc(&i2c_client->dev, sizeof(*pdata),
GFP_KERNEL);
if (!pdata)
return -ENOMEM;
if (i2c_client->dev.of_node) {
ret = cs35l32_handle_of_data(i2c_client,
&cs35l32->pdata);
if (ret != 0)
return ret;
}
}
for (i = 0; i < ARRAY_SIZE(cs35l32->supplies); i++)
cs35l32->supplies[i].supply = cs35l32_supply_names[i];
ret = devm_regulator_bulk_get(&i2c_client->dev,
ARRAY_SIZE(cs35l32->supplies),
cs35l32->supplies);
if (ret != 0) {
dev_err(&i2c_client->dev,
"Failed to request supplies: %d\n", ret);
return ret;
}
ret = regulator_bulk_enable(ARRAY_SIZE(cs35l32->supplies),
cs35l32->supplies);
if (ret != 0) {
dev_err(&i2c_client->dev,
"Failed to enable supplies: %d\n", ret);
return ret;
}
/* Reset the Device */
cs35l32->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
"reset", GPIOD_OUT_LOW);
if (IS_ERR(cs35l32->reset_gpio)) {
ret = PTR_ERR(cs35l32->reset_gpio);
goto err_supplies;
}
gpiod_set_value_cansleep(cs35l32->reset_gpio, 1);
/* initialize codec */
devid = cirrus_read_device_id(cs35l32->regmap, CS35L32_DEVID_AB);
if (devid < 0) {
ret = devid;
dev_err(&i2c_client->dev, "Failed to read device ID: %d\n", ret);
goto err_disable;
}
if (devid != CS35L32_CHIP_ID) {
ret = -ENODEV;
dev_err(&i2c_client->dev,
"CS35L32 Device ID (%X). Expected %X\n",
devid, CS35L32_CHIP_ID);
goto err_disable;
}
ret = regmap_read(cs35l32->regmap, CS35L32_REV_ID, ®);
if (ret < 0) {
dev_err(&i2c_client->dev, "Get Revision ID failed\n");
goto err_disable;
}
ret = regmap_register_patch(cs35l32->regmap, cs35l32_monitor_patch,
ARRAY_SIZE(cs35l32_monitor_patch));
if (ret < 0) {
dev_err(&i2c_client->dev, "Failed to apply errata patch\n");
goto err_disable;
}
dev_info(&i2c_client->dev,
"Cirrus Logic CS35L32, Revision: %02X\n", reg & 0xFF);
/* Setup VBOOST Management */
if (cs35l32->pdata.boost_mng)
regmap_update_bits(cs35l32->regmap, CS35L32_AUDIO_LED_MNGR,
CS35L32_BOOST_MASK,
cs35l32->pdata.boost_mng);
/* Setup ADSP Format Config */
if (cs35l32->pdata.sdout_share)
regmap_update_bits(cs35l32->regmap, CS35L32_ADSP_CTL,
CS35L32_ADSP_SHARE_MASK,
cs35l32->pdata.sdout_share << 3);
/* Setup ADSP Data Configuration */
if (cs35l32->pdata.sdout_datacfg)
regmap_update_bits(cs35l32->regmap, CS35L32_ADSP_CTL,
CS35L32_ADSP_DATACFG_MASK,
cs35l32->pdata.sdout_datacfg << 4);
/* Setup Low Battery Recovery */
if (cs35l32->pdata.batt_recov)
regmap_update_bits(cs35l32->regmap, CS35L32_BATT_THRESHOLD,
CS35L32_BATT_REC_MASK,
cs35l32->pdata.batt_recov << 1);
/* Setup Low Battery Threshold */
if (cs35l32->pdata.batt_thresh)
regmap_update_bits(cs35l32->regmap, CS35L32_BATT_THRESHOLD,
CS35L32_BATT_THRESH_MASK,
cs35l32->pdata.batt_thresh << 4);
/* Power down the AMP */
regmap_update_bits(cs35l32->regmap, CS35L32_PWRCTL1, CS35L32_PDN_AMP,
CS35L32_PDN_AMP);
/* Clear MCLK Error Bit since we don't have the clock yet */
regmap_read(cs35l32->regmap, CS35L32_INT_STATUS_1, ®);
ret = devm_snd_soc_register_component(&i2c_client->dev,
&soc_component_dev_cs35l32, cs35l32_dai,
ARRAY_SIZE(cs35l32_dai));
if (ret < 0)
goto err_disable;
return 0;
err_disable:
gpiod_set_value_cansleep(cs35l32->reset_gpio, 0);
err_supplies:
regulator_bulk_disable(ARRAY_SIZE(cs35l32->supplies),
cs35l32->supplies);
return ret;
}
static void cs35l32_i2c_remove(struct i2c_client *i2c_client)
{
struct cs35l32_private *cs35l32 = i2c_get_clientdata(i2c_client);
/* Hold down reset */
gpiod_set_value_cansleep(cs35l32->reset_gpio, 0);
}
#ifdef CONFIG_PM
static int cs35l32_runtime_suspend(struct device *dev)
{
struct cs35l32_private *cs35l32 = dev_get_drvdata(dev);
regcache_cache_only(cs35l32->regmap, true);
regcache_mark_dirty(cs35l32->regmap);
/* Hold down reset */
gpiod_set_value_cansleep(cs35l32->reset_gpio, 0);
/* remove power */
regulator_bulk_disable(ARRAY_SIZE(cs35l32->supplies),
cs35l32->supplies);
return 0;
}
static int cs35l32_runtime_resume(struct device *dev)
{
struct cs35l32_private *cs35l32 = dev_get_drvdata(dev);
int ret;
/* Enable power */
ret = regulator_bulk_enable(ARRAY_SIZE(cs35l32->supplies),
cs35l32->supplies);
if (ret != 0) {
dev_err(dev, "Failed to enable supplies: %d\n",
ret);
return ret;
}
gpiod_set_value_cansleep(cs35l32->reset_gpio, 1);
regcache_cache_only(cs35l32->regmap, false);
regcache_sync(cs35l32->regmap);
return 0;
}
#endif
static const struct dev_pm_ops cs35l32_runtime_pm = {
SET_RUNTIME_PM_OPS(cs35l32_runtime_suspend, cs35l32_runtime_resume,
NULL)
};
static const struct of_device_id cs35l32_of_match[] = {
{ .compatible = "cirrus,cs35l32", },
{},
};
MODULE_DEVICE_TABLE(of, cs35l32_of_match);
static const struct i2c_device_id cs35l32_id[] = {
{"cs35l32", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, cs35l32_id);
static struct i2c_driver cs35l32_i2c_driver = {
.driver = {
.name = "cs35l32",
.pm = &cs35l32_runtime_pm,
.of_match_table = cs35l32_of_match,
},
.id_table = cs35l32_id,
.probe = cs35l32_i2c_probe,
.remove = cs35l32_i2c_remove,
};
module_i2c_driver(cs35l32_i2c_driver);
MODULE_DESCRIPTION("ASoC CS35L32 driver");
MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cs35l32.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* dmic.c -- SoC audio for Generic Digital MICs
*
* Author: Liam Girdwood <[email protected]>
*/
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#define MAX_MODESWITCH_DELAY 70
static int modeswitch_delay;
module_param(modeswitch_delay, uint, 0644);
static int wakeup_delay;
module_param(wakeup_delay, uint, 0644);
struct dmic {
struct gpio_desc *gpio_en;
int wakeup_delay;
/* Delay after DMIC mode switch */
int modeswitch_delay;
};
static int dmic_daiops_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct dmic *dmic = snd_soc_component_get_drvdata(component);
switch (cmd) {
case SNDRV_PCM_TRIGGER_STOP:
if (dmic->modeswitch_delay)
mdelay(dmic->modeswitch_delay);
break;
}
return 0;
}
static const struct snd_soc_dai_ops dmic_dai_ops = {
.trigger = dmic_daiops_trigger,
};
static int dmic_aif_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event) {
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct dmic *dmic = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
if (dmic->gpio_en)
gpiod_set_value_cansleep(dmic->gpio_en, 1);
if (dmic->wakeup_delay)
msleep(dmic->wakeup_delay);
break;
case SND_SOC_DAPM_POST_PMD:
if (dmic->gpio_en)
gpiod_set_value_cansleep(dmic->gpio_en, 0);
break;
}
return 0;
}
static struct snd_soc_dai_driver dmic_dai = {
.name = "dmic-hifi",
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.formats = SNDRV_PCM_FMTBIT_S32_LE
| SNDRV_PCM_FMTBIT_S24_LE
| SNDRV_PCM_FMTBIT_S16_LE
| SNDRV_PCM_FMTBIT_DSD_U8
| SNDRV_PCM_FMTBIT_DSD_U16_LE
| SNDRV_PCM_FMTBIT_DSD_U32_LE,
},
.ops = &dmic_dai_ops,
};
static int dmic_component_probe(struct snd_soc_component *component)
{
struct dmic *dmic;
dmic = devm_kzalloc(component->dev, sizeof(*dmic), GFP_KERNEL);
if (!dmic)
return -ENOMEM;
dmic->gpio_en = devm_gpiod_get_optional(component->dev,
"dmicen", GPIOD_OUT_LOW);
if (IS_ERR(dmic->gpio_en))
return PTR_ERR(dmic->gpio_en);
device_property_read_u32(component->dev, "wakeup-delay-ms",
&dmic->wakeup_delay);
device_property_read_u32(component->dev, "modeswitch-delay-ms",
&dmic->modeswitch_delay);
if (wakeup_delay)
dmic->wakeup_delay = wakeup_delay;
if (modeswitch_delay)
dmic->modeswitch_delay = modeswitch_delay;
if (dmic->modeswitch_delay > MAX_MODESWITCH_DELAY)
dmic->modeswitch_delay = MAX_MODESWITCH_DELAY;
snd_soc_component_set_drvdata(component, dmic);
return 0;
}
static const struct snd_soc_dapm_widget dmic_dapm_widgets[] = {
SND_SOC_DAPM_AIF_OUT_E("DMIC AIF", "Capture", 0,
SND_SOC_NOPM, 0, 0, dmic_aif_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_INPUT("DMic"),
};
static const struct snd_soc_dapm_route intercon[] = {
{"DMIC AIF", NULL, "DMic"},
};
static const struct snd_soc_component_driver soc_dmic = {
.probe = dmic_component_probe,
.dapm_widgets = dmic_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(dmic_dapm_widgets),
.dapm_routes = intercon,
.num_dapm_routes = ARRAY_SIZE(intercon),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int dmic_dev_probe(struct platform_device *pdev)
{
int err;
u32 chans;
struct snd_soc_dai_driver *dai_drv = &dmic_dai;
if (pdev->dev.of_node) {
err = of_property_read_u32(pdev->dev.of_node, "num-channels", &chans);
if (err && (err != -EINVAL))
return err;
if (!err) {
if (chans < 1 || chans > 8)
return -EINVAL;
dai_drv = devm_kzalloc(&pdev->dev, sizeof(*dai_drv), GFP_KERNEL);
if (!dai_drv)
return -ENOMEM;
memcpy(dai_drv, &dmic_dai, sizeof(*dai_drv));
dai_drv->capture.channels_max = chans;
}
}
return devm_snd_soc_register_component(&pdev->dev,
&soc_dmic, dai_drv, 1);
}
MODULE_ALIAS("platform:dmic-codec");
static const struct of_device_id dmic_dev_match[] = {
{.compatible = "dmic-codec"},
{}
};
MODULE_DEVICE_TABLE(of, dmic_dev_match);
static struct platform_driver dmic_driver = {
.driver = {
.name = "dmic-codec",
.of_match_table = dmic_dev_match,
},
.probe = dmic_dev_probe,
};
module_platform_driver(dmic_driver);
MODULE_DESCRIPTION("Generic DMIC driver");
MODULE_AUTHOR("Liam Girdwood <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/dmic.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017 BayLibre, SAS.
* Author: Jerome Brunet <[email protected]>
*/
#include <linux/of_platform.h>
#include <linux/module.h>
#include <sound/soc.h>
/*
* The everest 7134 is a very simple DA converter with no register
*/
struct es7134_clock_mode {
unsigned int rate_min;
unsigned int rate_max;
unsigned int *mclk_fs;
unsigned int mclk_fs_num;
};
struct es7134_chip {
struct snd_soc_dai_driver *dai_drv;
const struct es7134_clock_mode *modes;
unsigned int mode_num;
const struct snd_soc_dapm_widget *extra_widgets;
unsigned int extra_widget_num;
const struct snd_soc_dapm_route *extra_routes;
unsigned int extra_route_num;
};
struct es7134_data {
unsigned int mclk;
const struct es7134_chip *chip;
};
static int es7134_check_mclk(struct snd_soc_dai *dai,
struct es7134_data *priv,
unsigned int rate)
{
unsigned int mfs = priv->mclk / rate;
int i, j;
for (i = 0; i < priv->chip->mode_num; i++) {
const struct es7134_clock_mode *mode = &priv->chip->modes[i];
if (rate < mode->rate_min || rate > mode->rate_max)
continue;
for (j = 0; j < mode->mclk_fs_num; j++) {
if (mode->mclk_fs[j] == mfs)
return 0;
}
dev_err(dai->dev, "unsupported mclk_fs %u for rate %u\n",
mfs, rate);
return -EINVAL;
}
/* should not happen */
dev_err(dai->dev, "unsupported rate: %u\n", rate);
return -EINVAL;
}
static int es7134_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct es7134_data *priv = snd_soc_dai_get_drvdata(dai);
/* mclk has not been provided, assume it is OK */
if (!priv->mclk)
return 0;
return es7134_check_mclk(dai, priv, params_rate(params));
}
static int es7134_set_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct es7134_data *priv = snd_soc_dai_get_drvdata(dai);
if (dir == SND_SOC_CLOCK_IN && clk_id == 0) {
priv->mclk = freq;
return 0;
}
return -ENOTSUPP;
}
static int es7134_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
fmt &= (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_INV_MASK |
SND_SOC_DAIFMT_MASTER_MASK);
if (fmt != (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBC_CFC)) {
dev_err(codec_dai->dev, "Invalid DAI format\n");
return -EINVAL;
}
return 0;
}
static int es7134_component_probe(struct snd_soc_component *c)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(c);
struct es7134_data *priv = snd_soc_component_get_drvdata(c);
const struct es7134_chip *chip = priv->chip;
int ret;
if (chip->extra_widget_num) {
ret = snd_soc_dapm_new_controls(dapm, chip->extra_widgets,
chip->extra_widget_num);
if (ret) {
dev_err(c->dev, "failed to add extra widgets\n");
return ret;
}
}
if (chip->extra_route_num) {
ret = snd_soc_dapm_add_routes(dapm, chip->extra_routes,
chip->extra_route_num);
if (ret) {
dev_err(c->dev, "failed to add extra routes\n");
return ret;
}
}
return 0;
}
static const struct snd_soc_dai_ops es7134_dai_ops = {
.set_fmt = es7134_set_fmt,
.hw_params = es7134_hw_params,
.set_sysclk = es7134_set_sysclk,
};
static struct snd_soc_dai_driver es7134_dai = {
.name = "es7134-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = (SNDRV_PCM_RATE_8000_48000 |
SNDRV_PCM_RATE_88200 |
SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_176400 |
SNDRV_PCM_RATE_192000),
.formats = (SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S18_3LE |
SNDRV_PCM_FMTBIT_S20_3LE |
SNDRV_PCM_FMTBIT_S24_3LE |
SNDRV_PCM_FMTBIT_S24_LE),
},
.ops = &es7134_dai_ops,
};
static const struct es7134_clock_mode es7134_modes[] = {
{
/* Single speed mode */
.rate_min = 8000,
.rate_max = 50000,
.mclk_fs = (unsigned int[]) { 256, 384, 512, 768, 1024 },
.mclk_fs_num = 5,
}, {
/* Double speed mode */
.rate_min = 84000,
.rate_max = 100000,
.mclk_fs = (unsigned int[]) { 128, 192, 256, 384, 512 },
.mclk_fs_num = 5,
}, {
/* Quad speed mode */
.rate_min = 167000,
.rate_max = 192000,
.mclk_fs = (unsigned int[]) { 128, 192, 256 },
.mclk_fs_num = 3,
},
};
/* Digital I/O are also supplied by VDD on the es7134 */
static const struct snd_soc_dapm_route es7134_extra_routes[] = {
{ "Playback", NULL, "VDD", }
};
static const struct es7134_chip es7134_chip __maybe_unused = {
.dai_drv = &es7134_dai,
.modes = es7134_modes,
.mode_num = ARRAY_SIZE(es7134_modes),
.extra_routes = es7134_extra_routes,
.extra_route_num = ARRAY_SIZE(es7134_extra_routes),
};
static const struct snd_soc_dapm_widget es7134_dapm_widgets[] = {
SND_SOC_DAPM_OUTPUT("AOUTL"),
SND_SOC_DAPM_OUTPUT("AOUTR"),
SND_SOC_DAPM_DAC("DAC", "Playback", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("VDD", 0, 0),
};
static const struct snd_soc_dapm_route es7134_dapm_routes[] = {
{ "AOUTL", NULL, "DAC" },
{ "AOUTR", NULL, "DAC" },
{ "DAC", NULL, "VDD" },
};
static const struct snd_soc_component_driver es7134_component_driver = {
.probe = es7134_component_probe,
.dapm_widgets = es7134_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(es7134_dapm_widgets),
.dapm_routes = es7134_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(es7134_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static struct snd_soc_dai_driver es7154_dai = {
.name = "es7154-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = (SNDRV_PCM_RATE_8000_48000 |
SNDRV_PCM_RATE_88200 |
SNDRV_PCM_RATE_96000),
.formats = (SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S18_3LE |
SNDRV_PCM_FMTBIT_S20_3LE |
SNDRV_PCM_FMTBIT_S24_3LE |
SNDRV_PCM_FMTBIT_S24_LE),
},
.ops = &es7134_dai_ops,
};
static const struct es7134_clock_mode es7154_modes[] = {
{
/* Single speed mode */
.rate_min = 8000,
.rate_max = 50000,
.mclk_fs = (unsigned int[]) { 32, 64, 128, 192, 256,
384, 512, 768, 1024 },
.mclk_fs_num = 9,
}, {
/* Double speed mode */
.rate_min = 84000,
.rate_max = 100000,
.mclk_fs = (unsigned int[]) { 128, 192, 256, 384, 512,
768, 1024},
.mclk_fs_num = 7,
}
};
/* Es7154 has a separate supply for digital I/O */
static const struct snd_soc_dapm_widget es7154_extra_widgets[] = {
SND_SOC_DAPM_REGULATOR_SUPPLY("PVDD", 0, 0),
};
static const struct snd_soc_dapm_route es7154_extra_routes[] = {
{ "Playback", NULL, "PVDD", }
};
static const struct es7134_chip es7154_chip __maybe_unused = {
.dai_drv = &es7154_dai,
.modes = es7154_modes,
.mode_num = ARRAY_SIZE(es7154_modes),
.extra_routes = es7154_extra_routes,
.extra_route_num = ARRAY_SIZE(es7154_extra_routes),
.extra_widgets = es7154_extra_widgets,
.extra_widget_num = ARRAY_SIZE(es7154_extra_widgets),
};
static int es7134_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct es7134_data *priv;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
platform_set_drvdata(pdev, priv);
priv->chip = of_device_get_match_data(dev);
if (!priv->chip) {
dev_err(dev, "failed to match device\n");
return -ENODEV;
}
return devm_snd_soc_register_component(&pdev->dev,
&es7134_component_driver,
priv->chip->dai_drv, 1);
}
#ifdef CONFIG_OF
static const struct of_device_id es7134_ids[] = {
{ .compatible = "everest,es7134", .data = &es7134_chip },
{ .compatible = "everest,es7144", .data = &es7134_chip },
{ .compatible = "everest,es7154", .data = &es7154_chip },
{ }
};
MODULE_DEVICE_TABLE(of, es7134_ids);
#endif
static struct platform_driver es7134_driver = {
.driver = {
.name = "es7134",
.of_match_table = of_match_ptr(es7134_ids),
},
.probe = es7134_probe,
};
module_platform_driver(es7134_driver);
MODULE_DESCRIPTION("ASoC ES7134 audio codec driver");
MODULE_AUTHOR("Jerome Brunet <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/es7134.c |
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/regulator/consumer.h>
#include <sound/soc.h>
struct aw8738_priv {
struct gpio_desc *gpiod_mode;
unsigned int mode;
};
static int aw8738_drv_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *c = snd_soc_dapm_to_component(w->dapm);
struct aw8738_priv *aw = snd_soc_component_get_drvdata(c);
int i;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
for (i = 0; i < aw->mode; i++) {
gpiod_set_value_cansleep(aw->gpiod_mode, 0);
udelay(2);
gpiod_set_value_cansleep(aw->gpiod_mode, 1);
udelay(2);
}
msleep(40);
break;
case SND_SOC_DAPM_PRE_PMD:
gpiod_set_value_cansleep(aw->gpiod_mode, 0);
usleep_range(1000, 2000);
break;
default:
WARN(1, "Unexpected event");
return -EINVAL;
}
return 0;
}
static const struct snd_soc_dapm_widget aw8738_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("IN"),
SND_SOC_DAPM_OUT_DRV_E("DRV", SND_SOC_NOPM, 0, 0, NULL, 0, aw8738_drv_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_OUTPUT("OUT"),
};
static const struct snd_soc_dapm_route aw8738_dapm_routes[] = {
{ "DRV", NULL, "IN" },
{ "OUT", NULL, "DRV" },
};
static const struct snd_soc_component_driver aw8738_component_driver = {
.dapm_widgets = aw8738_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(aw8738_dapm_widgets),
.dapm_routes = aw8738_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(aw8738_dapm_routes),
};
static int aw8738_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct aw8738_priv *aw;
int ret;
aw = devm_kzalloc(dev, sizeof(*aw), GFP_KERNEL);
if (!aw)
return -ENOMEM;
platform_set_drvdata(pdev, aw);
aw->gpiod_mode = devm_gpiod_get(dev, "mode", GPIOD_OUT_LOW);
if (IS_ERR(aw->gpiod_mode))
return dev_err_probe(dev, PTR_ERR(aw->gpiod_mode),
"Failed to get 'mode' gpio");
ret = device_property_read_u32(dev, "awinic,mode", &aw->mode);
if (ret)
return -EINVAL;
return devm_snd_soc_register_component(&pdev->dev,
&aw8738_component_driver,
NULL, 0);
}
#ifdef CONFIG_OF
static const struct of_device_id aw8738_of_match[] = {
{ .compatible = "awinic,aw8738" },
{ }
};
MODULE_DEVICE_TABLE(of, aw8738_of_match);
#endif
static struct platform_driver aw8738_driver = {
.probe = aw8738_probe,
.driver = {
.name = "aw8738",
.of_match_table = of_match_ptr(aw8738_of_match),
},
};
module_platform_driver(aw8738_driver);
MODULE_DESCRIPTION("Awinic AW8738 Amplifier Driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/aw8738.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8993.c -- WM8993 ALSA SoC audio driver
*
* Copyright 2009-12 Wolfson Microelectronics plc
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/tlv.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/wm8993.h>
#include "wm8993.h"
#include "wm_hubs.h"
#define WM8993_NUM_SUPPLIES 6
static const char *wm8993_supply_names[WM8993_NUM_SUPPLIES] = {
"DCVDD",
"DBVDD",
"AVDD1",
"AVDD2",
"CPVDD",
"SPKVDD",
};
static const struct reg_default wm8993_reg_defaults[] = {
{ 1, 0x0000 }, /* R1 - Power Management (1) */
{ 2, 0x6000 }, /* R2 - Power Management (2) */
{ 3, 0x0000 }, /* R3 - Power Management (3) */
{ 4, 0x4050 }, /* R4 - Audio Interface (1) */
{ 5, 0x4000 }, /* R5 - Audio Interface (2) */
{ 6, 0x01C8 }, /* R6 - Clocking 1 */
{ 7, 0x0000 }, /* R7 - Clocking 2 */
{ 8, 0x0000 }, /* R8 - Audio Interface (3) */
{ 9, 0x0040 }, /* R9 - Audio Interface (4) */
{ 10, 0x0004 }, /* R10 - DAC CTRL */
{ 11, 0x00C0 }, /* R11 - Left DAC Digital Volume */
{ 12, 0x00C0 }, /* R12 - Right DAC Digital Volume */
{ 13, 0x0000 }, /* R13 - Digital Side Tone */
{ 14, 0x0300 }, /* R14 - ADC CTRL */
{ 15, 0x00C0 }, /* R15 - Left ADC Digital Volume */
{ 16, 0x00C0 }, /* R16 - Right ADC Digital Volume */
{ 18, 0x0000 }, /* R18 - GPIO CTRL 1 */
{ 19, 0x0010 }, /* R19 - GPIO1 */
{ 20, 0x0000 }, /* R20 - IRQ_DEBOUNCE */
{ 21, 0x0000 }, /* R21 - Inputs Clamp */
{ 22, 0x8000 }, /* R22 - GPIOCTRL 2 */
{ 23, 0x0800 }, /* R23 - GPIO_POL */
{ 24, 0x008B }, /* R24 - Left Line Input 1&2 Volume */
{ 25, 0x008B }, /* R25 - Left Line Input 3&4 Volume */
{ 26, 0x008B }, /* R26 - Right Line Input 1&2 Volume */
{ 27, 0x008B }, /* R27 - Right Line Input 3&4 Volume */
{ 28, 0x006D }, /* R28 - Left Output Volume */
{ 29, 0x006D }, /* R29 - Right Output Volume */
{ 30, 0x0066 }, /* R30 - Line Outputs Volume */
{ 31, 0x0020 }, /* R31 - HPOUT2 Volume */
{ 32, 0x0079 }, /* R32 - Left OPGA Volume */
{ 33, 0x0079 }, /* R33 - Right OPGA Volume */
{ 34, 0x0003 }, /* R34 - SPKMIXL Attenuation */
{ 35, 0x0003 }, /* R35 - SPKMIXR Attenuation */
{ 36, 0x0011 }, /* R36 - SPKOUT Mixers */
{ 37, 0x0100 }, /* R37 - SPKOUT Boost */
{ 38, 0x0079 }, /* R38 - Speaker Volume Left */
{ 39, 0x0079 }, /* R39 - Speaker Volume Right */
{ 40, 0x0000 }, /* R40 - Input Mixer2 */
{ 41, 0x0000 }, /* R41 - Input Mixer3 */
{ 42, 0x0000 }, /* R42 - Input Mixer4 */
{ 43, 0x0000 }, /* R43 - Input Mixer5 */
{ 44, 0x0000 }, /* R44 - Input Mixer6 */
{ 45, 0x0000 }, /* R45 - Output Mixer1 */
{ 46, 0x0000 }, /* R46 - Output Mixer2 */
{ 47, 0x0000 }, /* R47 - Output Mixer3 */
{ 48, 0x0000 }, /* R48 - Output Mixer4 */
{ 49, 0x0000 }, /* R49 - Output Mixer5 */
{ 50, 0x0000 }, /* R50 - Output Mixer6 */
{ 51, 0x0000 }, /* R51 - HPOUT2 Mixer */
{ 52, 0x0000 }, /* R52 - Line Mixer1 */
{ 53, 0x0000 }, /* R53 - Line Mixer2 */
{ 54, 0x0000 }, /* R54 - Speaker Mixer */
{ 55, 0x0000 }, /* R55 - Additional Control */
{ 56, 0x0000 }, /* R56 - AntiPOP1 */
{ 57, 0x0000 }, /* R57 - AntiPOP2 */
{ 58, 0x0000 }, /* R58 - MICBIAS */
{ 60, 0x0000 }, /* R60 - FLL Control 1 */
{ 61, 0x0000 }, /* R61 - FLL Control 2 */
{ 62, 0x0000 }, /* R62 - FLL Control 3 */
{ 63, 0x2EE0 }, /* R63 - FLL Control 4 */
{ 64, 0x0002 }, /* R64 - FLL Control 5 */
{ 65, 0x2287 }, /* R65 - Clocking 3 */
{ 66, 0x025F }, /* R66 - Clocking 4 */
{ 67, 0x0000 }, /* R67 - MW Slave Control */
{ 69, 0x0002 }, /* R69 - Bus Control 1 */
{ 70, 0x0000 }, /* R70 - Write Sequencer 0 */
{ 71, 0x0000 }, /* R71 - Write Sequencer 1 */
{ 72, 0x0000 }, /* R72 - Write Sequencer 2 */
{ 73, 0x0000 }, /* R73 - Write Sequencer 3 */
{ 74, 0x0000 }, /* R74 - Write Sequencer 4 */
{ 75, 0x0000 }, /* R75 - Write Sequencer 5 */
{ 76, 0x1F25 }, /* R76 - Charge Pump 1 */
{ 81, 0x0000 }, /* R81 - Class W 0 */
{ 85, 0x054A }, /* R85 - DC Servo 1 */
{ 87, 0x0000 }, /* R87 - DC Servo 3 */
{ 96, 0x0100 }, /* R96 - Analogue HP 0 */
{ 98, 0x0000 }, /* R98 - EQ1 */
{ 99, 0x000C }, /* R99 - EQ2 */
{ 100, 0x000C }, /* R100 - EQ3 */
{ 101, 0x000C }, /* R101 - EQ4 */
{ 102, 0x000C }, /* R102 - EQ5 */
{ 103, 0x000C }, /* R103 - EQ6 */
{ 104, 0x0FCA }, /* R104 - EQ7 */
{ 105, 0x0400 }, /* R105 - EQ8 */
{ 106, 0x00D8 }, /* R106 - EQ9 */
{ 107, 0x1EB5 }, /* R107 - EQ10 */
{ 108, 0xF145 }, /* R108 - EQ11 */
{ 109, 0x0B75 }, /* R109 - EQ12 */
{ 110, 0x01C5 }, /* R110 - EQ13 */
{ 111, 0x1C58 }, /* R111 - EQ14 */
{ 112, 0xF373 }, /* R112 - EQ15 */
{ 113, 0x0A54 }, /* R113 - EQ16 */
{ 114, 0x0558 }, /* R114 - EQ17 */
{ 115, 0x168E }, /* R115 - EQ18 */
{ 116, 0xF829 }, /* R116 - EQ19 */
{ 117, 0x07AD }, /* R117 - EQ20 */
{ 118, 0x1103 }, /* R118 - EQ21 */
{ 119, 0x0564 }, /* R119 - EQ22 */
{ 120, 0x0559 }, /* R120 - EQ23 */
{ 121, 0x4000 }, /* R121 - EQ24 */
{ 122, 0x0000 }, /* R122 - Digital Pulls */
{ 123, 0x0F08 }, /* R123 - DRC Control 1 */
{ 124, 0x0000 }, /* R124 - DRC Control 2 */
{ 125, 0x0080 }, /* R125 - DRC Control 3 */
{ 126, 0x0000 }, /* R126 - DRC Control 4 */
};
static struct {
int ratio;
int clk_sys_rate;
} clk_sys_rates[] = {
{ 64, 0 },
{ 128, 1 },
{ 192, 2 },
{ 256, 3 },
{ 384, 4 },
{ 512, 5 },
{ 768, 6 },
{ 1024, 7 },
{ 1408, 8 },
{ 1536, 9 },
};
static struct {
int rate;
int sample_rate;
} sample_rates[] = {
{ 8000, 0 },
{ 11025, 1 },
{ 12000, 1 },
{ 16000, 2 },
{ 22050, 3 },
{ 24000, 3 },
{ 32000, 4 },
{ 44100, 5 },
{ 48000, 5 },
};
static struct {
int div; /* *10 due to .5s */
int bclk_div;
} bclk_divs[] = {
{ 10, 0 },
{ 15, 1 },
{ 20, 2 },
{ 30, 3 },
{ 40, 4 },
{ 55, 5 },
{ 60, 6 },
{ 80, 7 },
{ 110, 8 },
{ 120, 9 },
{ 160, 10 },
{ 220, 11 },
{ 240, 12 },
{ 320, 13 },
{ 440, 14 },
{ 480, 15 },
};
struct wm8993_priv {
struct wm_hubs_data hubs_data;
struct device *dev;
struct regmap *regmap;
struct regulator_bulk_data supplies[WM8993_NUM_SUPPLIES];
struct wm8993_platform_data pdata;
struct completion fll_lock;
int master;
int sysclk_source;
int tdm_slots;
int tdm_width;
unsigned int mclk_rate;
unsigned int sysclk_rate;
unsigned int fs;
unsigned int bclk;
unsigned int fll_fref;
unsigned int fll_fout;
int fll_src;
};
static bool wm8993_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8993_SOFTWARE_RESET:
case WM8993_GPIO_CTRL_1:
case WM8993_DC_SERVO_0:
case WM8993_DC_SERVO_READBACK_0:
case WM8993_DC_SERVO_READBACK_1:
case WM8993_DC_SERVO_READBACK_2:
return true;
default:
return false;
}
}
static bool wm8993_readable(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8993_SOFTWARE_RESET:
case WM8993_POWER_MANAGEMENT_1:
case WM8993_POWER_MANAGEMENT_2:
case WM8993_POWER_MANAGEMENT_3:
case WM8993_AUDIO_INTERFACE_1:
case WM8993_AUDIO_INTERFACE_2:
case WM8993_CLOCKING_1:
case WM8993_CLOCKING_2:
case WM8993_AUDIO_INTERFACE_3:
case WM8993_AUDIO_INTERFACE_4:
case WM8993_DAC_CTRL:
case WM8993_LEFT_DAC_DIGITAL_VOLUME:
case WM8993_RIGHT_DAC_DIGITAL_VOLUME:
case WM8993_DIGITAL_SIDE_TONE:
case WM8993_ADC_CTRL:
case WM8993_LEFT_ADC_DIGITAL_VOLUME:
case WM8993_RIGHT_ADC_DIGITAL_VOLUME:
case WM8993_GPIO_CTRL_1:
case WM8993_GPIO1:
case WM8993_IRQ_DEBOUNCE:
case WM8993_GPIOCTRL_2:
case WM8993_GPIO_POL:
case WM8993_LEFT_LINE_INPUT_1_2_VOLUME:
case WM8993_LEFT_LINE_INPUT_3_4_VOLUME:
case WM8993_RIGHT_LINE_INPUT_1_2_VOLUME:
case WM8993_RIGHT_LINE_INPUT_3_4_VOLUME:
case WM8993_LEFT_OUTPUT_VOLUME:
case WM8993_RIGHT_OUTPUT_VOLUME:
case WM8993_LINE_OUTPUTS_VOLUME:
case WM8993_HPOUT2_VOLUME:
case WM8993_LEFT_OPGA_VOLUME:
case WM8993_RIGHT_OPGA_VOLUME:
case WM8993_SPKMIXL_ATTENUATION:
case WM8993_SPKMIXR_ATTENUATION:
case WM8993_SPKOUT_MIXERS:
case WM8993_SPKOUT_BOOST:
case WM8993_SPEAKER_VOLUME_LEFT:
case WM8993_SPEAKER_VOLUME_RIGHT:
case WM8993_INPUT_MIXER2:
case WM8993_INPUT_MIXER3:
case WM8993_INPUT_MIXER4:
case WM8993_INPUT_MIXER5:
case WM8993_INPUT_MIXER6:
case WM8993_OUTPUT_MIXER1:
case WM8993_OUTPUT_MIXER2:
case WM8993_OUTPUT_MIXER3:
case WM8993_OUTPUT_MIXER4:
case WM8993_OUTPUT_MIXER5:
case WM8993_OUTPUT_MIXER6:
case WM8993_HPOUT2_MIXER:
case WM8993_LINE_MIXER1:
case WM8993_LINE_MIXER2:
case WM8993_SPEAKER_MIXER:
case WM8993_ADDITIONAL_CONTROL:
case WM8993_ANTIPOP1:
case WM8993_ANTIPOP2:
case WM8993_MICBIAS:
case WM8993_FLL_CONTROL_1:
case WM8993_FLL_CONTROL_2:
case WM8993_FLL_CONTROL_3:
case WM8993_FLL_CONTROL_4:
case WM8993_FLL_CONTROL_5:
case WM8993_CLOCKING_3:
case WM8993_CLOCKING_4:
case WM8993_MW_SLAVE_CONTROL:
case WM8993_BUS_CONTROL_1:
case WM8993_WRITE_SEQUENCER_0:
case WM8993_WRITE_SEQUENCER_1:
case WM8993_WRITE_SEQUENCER_2:
case WM8993_WRITE_SEQUENCER_3:
case WM8993_WRITE_SEQUENCER_4:
case WM8993_WRITE_SEQUENCER_5:
case WM8993_CHARGE_PUMP_1:
case WM8993_CLASS_W_0:
case WM8993_DC_SERVO_0:
case WM8993_DC_SERVO_1:
case WM8993_DC_SERVO_3:
case WM8993_DC_SERVO_READBACK_0:
case WM8993_DC_SERVO_READBACK_1:
case WM8993_DC_SERVO_READBACK_2:
case WM8993_ANALOGUE_HP_0:
case WM8993_EQ1:
case WM8993_EQ2:
case WM8993_EQ3:
case WM8993_EQ4:
case WM8993_EQ5:
case WM8993_EQ6:
case WM8993_EQ7:
case WM8993_EQ8:
case WM8993_EQ9:
case WM8993_EQ10:
case WM8993_EQ11:
case WM8993_EQ12:
case WM8993_EQ13:
case WM8993_EQ14:
case WM8993_EQ15:
case WM8993_EQ16:
case WM8993_EQ17:
case WM8993_EQ18:
case WM8993_EQ19:
case WM8993_EQ20:
case WM8993_EQ21:
case WM8993_EQ22:
case WM8993_EQ23:
case WM8993_EQ24:
case WM8993_DIGITAL_PULLS:
case WM8993_DRC_CONTROL_1:
case WM8993_DRC_CONTROL_2:
case WM8993_DRC_CONTROL_3:
case WM8993_DRC_CONTROL_4:
return true;
default:
return false;
}
}
struct _fll_div {
u16 fll_fratio;
u16 fll_outdiv;
u16 fll_clk_ref_div;
u16 n;
u16 k;
};
/* The size in bits of the FLL divide multiplied by 10
* to allow rounding later */
#define FIXED_FLL_SIZE ((1 << 16) * 10)
static struct {
unsigned int min;
unsigned int max;
u16 fll_fratio;
int ratio;
} fll_fratios[] = {
{ 0, 64000, 4, 16 },
{ 64000, 128000, 3, 8 },
{ 128000, 256000, 2, 4 },
{ 256000, 1000000, 1, 2 },
{ 1000000, 13500000, 0, 1 },
};
static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
unsigned int Fout)
{
u64 Kpart;
unsigned int K, Ndiv, Nmod, target;
unsigned int div;
int i;
/* Fref must be <=13.5MHz */
div = 1;
fll_div->fll_clk_ref_div = 0;
while ((Fref / div) > 13500000) {
div *= 2;
fll_div->fll_clk_ref_div++;
if (div > 8) {
pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
Fref);
return -EINVAL;
}
}
pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
/* Apply the division for our remaining calculations */
Fref /= div;
/* Fvco should be 90-100MHz; don't check the upper bound */
div = 0;
target = Fout * 2;
while (target < 90000000) {
div++;
target *= 2;
if (div > 7) {
pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
Fout);
return -EINVAL;
}
}
fll_div->fll_outdiv = div;
pr_debug("Fvco=%dHz\n", target);
/* Find an appropriate FLL_FRATIO and factor it out of the target */
for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
fll_div->fll_fratio = fll_fratios[i].fll_fratio;
target /= fll_fratios[i].ratio;
break;
}
}
if (i == ARRAY_SIZE(fll_fratios)) {
pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
return -EINVAL;
}
/* Now, calculate N.K */
Ndiv = target / Fref;
fll_div->n = Ndiv;
Nmod = target % Fref;
pr_debug("Nmod=%d\n", Nmod);
/* Calculate fractional part - scale up so we can round. */
Kpart = FIXED_FLL_SIZE * (long long)Nmod;
do_div(Kpart, Fref);
K = Kpart & 0xFFFFFFFF;
if ((K % 10) >= 5)
K += 5;
/* Move down to proper range now rounding is done */
fll_div->k = K / 10;
pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
fll_div->n, fll_div->k,
fll_div->fll_fratio, fll_div->fll_outdiv,
fll_div->fll_clk_ref_div);
return 0;
}
static int _wm8993_set_fll(struct snd_soc_component *component, int fll_id, int source,
unsigned int Fref, unsigned int Fout)
{
struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
struct i2c_client *i2c = to_i2c_client(component->dev);
u16 reg1, reg4, reg5;
struct _fll_div fll_div;
unsigned int timeout;
int ret;
/* Any change? */
if (Fref == wm8993->fll_fref && Fout == wm8993->fll_fout)
return 0;
/* Disable the FLL */
if (Fout == 0) {
dev_dbg(component->dev, "FLL disabled\n");
wm8993->fll_fref = 0;
wm8993->fll_fout = 0;
reg1 = snd_soc_component_read(component, WM8993_FLL_CONTROL_1);
reg1 &= ~WM8993_FLL_ENA;
snd_soc_component_write(component, WM8993_FLL_CONTROL_1, reg1);
return 0;
}
ret = fll_factors(&fll_div, Fref, Fout);
if (ret != 0)
return ret;
reg5 = snd_soc_component_read(component, WM8993_FLL_CONTROL_5);
reg5 &= ~WM8993_FLL_CLK_SRC_MASK;
switch (fll_id) {
case WM8993_FLL_MCLK:
break;
case WM8993_FLL_LRCLK:
reg5 |= 1;
break;
case WM8993_FLL_BCLK:
reg5 |= 2;
break;
default:
dev_err(component->dev, "Unknown FLL ID %d\n", fll_id);
return -EINVAL;
}
/* Any FLL configuration change requires that the FLL be
* disabled first. */
reg1 = snd_soc_component_read(component, WM8993_FLL_CONTROL_1);
reg1 &= ~WM8993_FLL_ENA;
snd_soc_component_write(component, WM8993_FLL_CONTROL_1, reg1);
/* Apply the configuration */
if (fll_div.k)
reg1 |= WM8993_FLL_FRAC_MASK;
else
reg1 &= ~WM8993_FLL_FRAC_MASK;
snd_soc_component_write(component, WM8993_FLL_CONTROL_1, reg1);
snd_soc_component_write(component, WM8993_FLL_CONTROL_2,
(fll_div.fll_outdiv << WM8993_FLL_OUTDIV_SHIFT) |
(fll_div.fll_fratio << WM8993_FLL_FRATIO_SHIFT));
snd_soc_component_write(component, WM8993_FLL_CONTROL_3, fll_div.k);
reg4 = snd_soc_component_read(component, WM8993_FLL_CONTROL_4);
reg4 &= ~WM8993_FLL_N_MASK;
reg4 |= fll_div.n << WM8993_FLL_N_SHIFT;
snd_soc_component_write(component, WM8993_FLL_CONTROL_4, reg4);
reg5 &= ~WM8993_FLL_CLK_REF_DIV_MASK;
reg5 |= fll_div.fll_clk_ref_div << WM8993_FLL_CLK_REF_DIV_SHIFT;
snd_soc_component_write(component, WM8993_FLL_CONTROL_5, reg5);
/* If we've got an interrupt wired up make sure we get it */
if (i2c->irq)
timeout = msecs_to_jiffies(20);
else if (Fref < 1000000)
timeout = msecs_to_jiffies(3);
else
timeout = msecs_to_jiffies(1);
try_wait_for_completion(&wm8993->fll_lock);
/* Enable the FLL */
snd_soc_component_write(component, WM8993_FLL_CONTROL_1, reg1 | WM8993_FLL_ENA);
timeout = wait_for_completion_timeout(&wm8993->fll_lock, timeout);
if (i2c->irq && !timeout)
dev_warn(component->dev, "Timed out waiting for FLL\n");
dev_dbg(component->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
wm8993->fll_fref = Fref;
wm8993->fll_fout = Fout;
wm8993->fll_src = source;
return 0;
}
static int wm8993_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
unsigned int Fref, unsigned int Fout)
{
return _wm8993_set_fll(dai->component, fll_id, source, Fref, Fout);
}
static int configure_clock(struct snd_soc_component *component)
{
struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
unsigned int reg;
/* This should be done on init() for bypass paths */
switch (wm8993->sysclk_source) {
case WM8993_SYSCLK_MCLK:
dev_dbg(component->dev, "Using %dHz MCLK\n", wm8993->mclk_rate);
reg = snd_soc_component_read(component, WM8993_CLOCKING_2);
reg &= ~(WM8993_MCLK_DIV | WM8993_SYSCLK_SRC);
if (wm8993->mclk_rate > 13500000) {
reg |= WM8993_MCLK_DIV;
wm8993->sysclk_rate = wm8993->mclk_rate / 2;
} else {
reg &= ~WM8993_MCLK_DIV;
wm8993->sysclk_rate = wm8993->mclk_rate;
}
snd_soc_component_write(component, WM8993_CLOCKING_2, reg);
break;
case WM8993_SYSCLK_FLL:
dev_dbg(component->dev, "Using %dHz FLL clock\n",
wm8993->fll_fout);
reg = snd_soc_component_read(component, WM8993_CLOCKING_2);
reg |= WM8993_SYSCLK_SRC;
if (wm8993->fll_fout > 13500000) {
reg |= WM8993_MCLK_DIV;
wm8993->sysclk_rate = wm8993->fll_fout / 2;
} else {
reg &= ~WM8993_MCLK_DIV;
wm8993->sysclk_rate = wm8993->fll_fout;
}
snd_soc_component_write(component, WM8993_CLOCKING_2, reg);
break;
default:
dev_err(component->dev, "System clock not configured\n");
return -EINVAL;
}
dev_dbg(component->dev, "CLK_SYS is %dHz\n", wm8993->sysclk_rate);
return 0;
}
static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
static const DECLARE_TLV_DB_SCALE(drc_comp_threash, -4500, 75, 0);
static const DECLARE_TLV_DB_SCALE(drc_comp_amp, -2250, 75, 0);
static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
static const DECLARE_TLV_DB_RANGE(drc_max_tlv,
0, 2, TLV_DB_SCALE_ITEM(1200, 600, 0),
3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0)
);
static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -1800, 300, 0);
static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
static const char *dac_deemph_text[] = {
"None",
"32kHz",
"44.1kHz",
"48kHz",
};
static SOC_ENUM_SINGLE_DECL(dac_deemph,
WM8993_DAC_CTRL, 4, dac_deemph_text);
static const char *adc_hpf_text[] = {
"Hi-Fi",
"Voice 1",
"Voice 2",
"Voice 3",
};
static SOC_ENUM_SINGLE_DECL(adc_hpf,
WM8993_ADC_CTRL, 5, adc_hpf_text);
static const char *drc_path_text[] = {
"ADC",
"DAC"
};
static SOC_ENUM_SINGLE_DECL(drc_path,
WM8993_DRC_CONTROL_1, 14, drc_path_text);
static const char *drc_r0_text[] = {
"1",
"1/2",
"1/4",
"1/8",
"1/16",
"0",
};
static SOC_ENUM_SINGLE_DECL(drc_r0,
WM8993_DRC_CONTROL_3, 8, drc_r0_text);
static const char *drc_r1_text[] = {
"1",
"1/2",
"1/4",
"1/8",
"0",
};
static SOC_ENUM_SINGLE_DECL(drc_r1,
WM8993_DRC_CONTROL_4, 13, drc_r1_text);
static const char *drc_attack_text[] = {
"Reserved",
"181us",
"363us",
"726us",
"1.45ms",
"2.9ms",
"5.8ms",
"11.6ms",
"23.2ms",
"46.4ms",
"92.8ms",
"185.6ms",
};
static SOC_ENUM_SINGLE_DECL(drc_attack,
WM8993_DRC_CONTROL_2, 12, drc_attack_text);
static const char *drc_decay_text[] = {
"186ms",
"372ms",
"743ms",
"1.49s",
"2.97ms",
"5.94ms",
"11.89ms",
"23.78ms",
"47.56ms",
};
static SOC_ENUM_SINGLE_DECL(drc_decay,
WM8993_DRC_CONTROL_2, 8, drc_decay_text);
static const char *drc_ff_text[] = {
"5 samples",
"9 samples",
};
static SOC_ENUM_SINGLE_DECL(drc_ff,
WM8993_DRC_CONTROL_3, 7, drc_ff_text);
static const char *drc_qr_rate_text[] = {
"0.725ms",
"1.45ms",
"5.8ms",
};
static SOC_ENUM_SINGLE_DECL(drc_qr_rate,
WM8993_DRC_CONTROL_3, 0, drc_qr_rate_text);
static const char *drc_smooth_text[] = {
"Low",
"Medium",
"High",
};
static SOC_ENUM_SINGLE_DECL(drc_smooth,
WM8993_DRC_CONTROL_1, 4, drc_smooth_text);
static const struct snd_kcontrol_new wm8993_snd_controls[] = {
SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8993_DIGITAL_SIDE_TONE,
5, 9, 12, 0, sidetone_tlv),
SOC_SINGLE("DRC Switch", WM8993_DRC_CONTROL_1, 15, 1, 0),
SOC_ENUM("DRC Path", drc_path),
SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8993_DRC_CONTROL_2,
2, 60, 1, drc_comp_threash),
SOC_SINGLE_TLV("DRC Compressor Amplitude Volume", WM8993_DRC_CONTROL_3,
11, 30, 1, drc_comp_amp),
SOC_ENUM("DRC R0", drc_r0),
SOC_ENUM("DRC R1", drc_r1),
SOC_SINGLE_TLV("DRC Minimum Volume", WM8993_DRC_CONTROL_1, 2, 3, 1,
drc_min_tlv),
SOC_SINGLE_TLV("DRC Maximum Volume", WM8993_DRC_CONTROL_1, 0, 3, 0,
drc_max_tlv),
SOC_ENUM("DRC Attack Rate", drc_attack),
SOC_ENUM("DRC Decay Rate", drc_decay),
SOC_ENUM("DRC FF Delay", drc_ff),
SOC_SINGLE("DRC Anti-clip Switch", WM8993_DRC_CONTROL_1, 9, 1, 0),
SOC_SINGLE("DRC Quick Release Switch", WM8993_DRC_CONTROL_1, 10, 1, 0),
SOC_SINGLE_TLV("DRC Quick Release Volume", WM8993_DRC_CONTROL_3, 2, 3, 0,
drc_qr_tlv),
SOC_ENUM("DRC Quick Release Rate", drc_qr_rate),
SOC_SINGLE("DRC Smoothing Switch", WM8993_DRC_CONTROL_1, 11, 1, 0),
SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8993_DRC_CONTROL_1, 8, 1, 0),
SOC_ENUM("DRC Smoothing Hysteresis Threshold", drc_smooth),
SOC_SINGLE_TLV("DRC Startup Volume", WM8993_DRC_CONTROL_4, 8, 18, 0,
drc_startup_tlv),
SOC_SINGLE("EQ Switch", WM8993_EQ1, 0, 1, 0),
SOC_DOUBLE_R_TLV("Capture Volume", WM8993_LEFT_ADC_DIGITAL_VOLUME,
WM8993_RIGHT_ADC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
SOC_SINGLE("ADC High Pass Filter Switch", WM8993_ADC_CTRL, 8, 1, 0),
SOC_ENUM("ADC High Pass Filter Mode", adc_hpf),
SOC_DOUBLE_R_TLV("Playback Volume", WM8993_LEFT_DAC_DIGITAL_VOLUME,
WM8993_RIGHT_DAC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
SOC_SINGLE_TLV("Playback Boost Volume", WM8993_AUDIO_INTERFACE_2, 10, 3, 0,
dac_boost_tlv),
SOC_ENUM("DAC Deemphasis", dac_deemph),
SOC_SINGLE_TLV("SPKL DAC Volume", WM8993_SPKMIXL_ATTENUATION,
2, 1, 1, wm_hubs_spkmix_tlv),
SOC_SINGLE_TLV("SPKR DAC Volume", WM8993_SPKMIXR_ATTENUATION,
2, 1, 1, wm_hubs_spkmix_tlv),
};
static const struct snd_kcontrol_new wm8993_eq_controls[] = {
SOC_SINGLE_TLV("EQ1 Volume", WM8993_EQ2, 0, 24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ2 Volume", WM8993_EQ3, 0, 24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ3 Volume", WM8993_EQ4, 0, 24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ4 Volume", WM8993_EQ5, 0, 24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ5 Volume", WM8993_EQ6, 0, 24, 0, eq_tlv),
};
static int clk_sys_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
return configure_clock(component);
case SND_SOC_DAPM_POST_PMD:
break;
}
return 0;
}
static const struct snd_kcontrol_new left_speaker_mixer[] = {
SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 7, 1, 0),
SOC_DAPM_SINGLE("IN1LP Switch", WM8993_SPEAKER_MIXER, 5, 1, 0),
SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 3, 1, 0),
SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
};
static const struct snd_kcontrol_new right_speaker_mixer[] = {
SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
SOC_DAPM_SINGLE("IN1RP Switch", WM8993_SPEAKER_MIXER, 4, 1, 0),
SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 2, 1, 0),
SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 0, 1, 0),
};
static const char *aif_text[] = {
"Left", "Right"
};
static SOC_ENUM_SINGLE_DECL(aifoutl_enum,
WM8993_AUDIO_INTERFACE_1, 15, aif_text);
static const struct snd_kcontrol_new aifoutl_mux =
SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum);
static SOC_ENUM_SINGLE_DECL(aifoutr_enum,
WM8993_AUDIO_INTERFACE_1, 14, aif_text);
static const struct snd_kcontrol_new aifoutr_mux =
SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum);
static SOC_ENUM_SINGLE_DECL(aifinl_enum,
WM8993_AUDIO_INTERFACE_2, 15, aif_text);
static const struct snd_kcontrol_new aifinl_mux =
SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum);
static SOC_ENUM_SINGLE_DECL(aifinr_enum,
WM8993_AUDIO_INTERFACE_2, 14, aif_text);
static const struct snd_kcontrol_new aifinr_mux =
SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum);
static const char *sidetone_text[] = {
"None", "Left", "Right"
};
static SOC_ENUM_SINGLE_DECL(sidetonel_enum,
WM8993_DIGITAL_SIDE_TONE, 2, sidetone_text);
static const struct snd_kcontrol_new sidetonel_mux =
SOC_DAPM_ENUM("Left Sidetone", sidetonel_enum);
static SOC_ENUM_SINGLE_DECL(sidetoner_enum,
WM8993_DIGITAL_SIDE_TONE, 0, sidetone_text);
static const struct snd_kcontrol_new sidetoner_mux =
SOC_DAPM_ENUM("Right Sidetone", sidetoner_enum);
static const struct snd_soc_dapm_widget wm8993_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8993_BUS_CONTROL_1, 1, 0, clk_sys_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("TOCLK", WM8993_CLOCKING_1, 14, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8993_CLOCKING_3, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_ADC("ADCL", NULL, WM8993_POWER_MANAGEMENT_2, 1, 0),
SND_SOC_DAPM_ADC("ADCR", NULL, WM8993_POWER_MANAGEMENT_2, 0, 0),
SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux),
SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux),
SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux),
SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux),
SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &sidetonel_mux),
SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &sidetoner_mux),
SND_SOC_DAPM_DAC("DACL", NULL, WM8993_POWER_MANAGEMENT_3, 1, 0),
SND_SOC_DAPM_DAC("DACR", NULL, WM8993_POWER_MANAGEMENT_3, 0, 0),
SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
SND_SOC_DAPM_MIXER("SPKL", WM8993_POWER_MANAGEMENT_3, 8, 0,
left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
SND_SOC_DAPM_MIXER("SPKR", WM8993_POWER_MANAGEMENT_3, 9, 0,
right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
};
static const struct snd_soc_dapm_route routes[] = {
{ "MICBIAS1", NULL, "VMID" },
{ "MICBIAS2", NULL, "VMID" },
{ "ADCL", NULL, "CLK_SYS" },
{ "ADCL", NULL, "CLK_DSP" },
{ "ADCR", NULL, "CLK_SYS" },
{ "ADCR", NULL, "CLK_DSP" },
{ "AIFOUTL Mux", "Left", "ADCL" },
{ "AIFOUTL Mux", "Right", "ADCR" },
{ "AIFOUTR Mux", "Left", "ADCL" },
{ "AIFOUTR Mux", "Right", "ADCR" },
{ "AIFOUTL", NULL, "AIFOUTL Mux" },
{ "AIFOUTR", NULL, "AIFOUTR Mux" },
{ "DACL Mux", "Left", "AIFINL" },
{ "DACL Mux", "Right", "AIFINR" },
{ "DACR Mux", "Left", "AIFINL" },
{ "DACR Mux", "Right", "AIFINR" },
{ "DACL Sidetone", "Left", "ADCL" },
{ "DACL Sidetone", "Right", "ADCR" },
{ "DACR Sidetone", "Left", "ADCL" },
{ "DACR Sidetone", "Right", "ADCR" },
{ "DACL", NULL, "CLK_SYS" },
{ "DACL", NULL, "CLK_DSP" },
{ "DACL", NULL, "DACL Mux" },
{ "DACL", NULL, "DACL Sidetone" },
{ "DACR", NULL, "CLK_SYS" },
{ "DACR", NULL, "CLK_DSP" },
{ "DACR", NULL, "DACR Mux" },
{ "DACR", NULL, "DACR Sidetone" },
{ "Left Output Mixer", "DAC Switch", "DACL" },
{ "Right Output Mixer", "DAC Switch", "DACR" },
{ "Left Output PGA", NULL, "CLK_SYS" },
{ "Right Output PGA", NULL, "CLK_SYS" },
{ "SPKL", "DAC Switch", "DACL" },
{ "SPKL", NULL, "CLK_SYS" },
{ "SPKR", "DAC Switch", "DACR" },
{ "SPKR", NULL, "CLK_SYS" },
{ "Left Headphone Mux", "DAC", "DACL" },
{ "Right Headphone Mux", "DAC", "DACR" },
};
static int wm8993_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
int ret;
wm_hubs_set_bias_level(component, level);
switch (level) {
case SND_SOC_BIAS_ON:
case SND_SOC_BIAS_PREPARE:
/* VMID=2*40k */
snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_1,
WM8993_VMID_SEL_MASK, 0x2);
snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_2,
WM8993_TSHUT_ENA, WM8993_TSHUT_ENA);
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies),
wm8993->supplies);
if (ret != 0)
return ret;
regcache_cache_only(wm8993->regmap, false);
regcache_sync(wm8993->regmap);
wm_hubs_vmid_ena(component);
/* Bring up VMID with fast soft start */
snd_soc_component_update_bits(component, WM8993_ANTIPOP2,
WM8993_STARTUP_BIAS_ENA |
WM8993_VMID_BUF_ENA |
WM8993_VMID_RAMP_MASK |
WM8993_BIAS_SRC,
WM8993_STARTUP_BIAS_ENA |
WM8993_VMID_BUF_ENA |
WM8993_VMID_RAMP_MASK |
WM8993_BIAS_SRC);
/* If either line output is single ended we
* need the VMID buffer */
if (!wm8993->pdata.lineout1_diff ||
!wm8993->pdata.lineout2_diff)
snd_soc_component_update_bits(component, WM8993_ANTIPOP1,
WM8993_LINEOUT_VMID_BUF_ENA,
WM8993_LINEOUT_VMID_BUF_ENA);
/* VMID=2*40k */
snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_1,
WM8993_VMID_SEL_MASK |
WM8993_BIAS_ENA,
WM8993_BIAS_ENA | 0x2);
msleep(32);
/* Switch to normal bias */
snd_soc_component_update_bits(component, WM8993_ANTIPOP2,
WM8993_BIAS_SRC |
WM8993_STARTUP_BIAS_ENA, 0);
}
/* VMID=2*240k */
snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_1,
WM8993_VMID_SEL_MASK, 0x4);
snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_2,
WM8993_TSHUT_ENA, 0);
break;
case SND_SOC_BIAS_OFF:
snd_soc_component_update_bits(component, WM8993_ANTIPOP1,
WM8993_LINEOUT_VMID_BUF_ENA, 0);
snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_1,
WM8993_VMID_SEL_MASK | WM8993_BIAS_ENA,
0);
snd_soc_component_update_bits(component, WM8993_ANTIPOP2,
WM8993_STARTUP_BIAS_ENA |
WM8993_VMID_BUF_ENA |
WM8993_VMID_RAMP_MASK |
WM8993_BIAS_SRC, 0);
regcache_cache_only(wm8993->regmap, true);
regcache_mark_dirty(wm8993->regmap);
regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies),
wm8993->supplies);
break;
}
return 0;
}
static int wm8993_set_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
switch (clk_id) {
case WM8993_SYSCLK_MCLK:
wm8993->mclk_rate = freq;
fallthrough;
case WM8993_SYSCLK_FLL:
wm8993->sysclk_source = clk_id;
break;
default:
return -EINVAL;
}
return 0;
}
static int wm8993_set_dai_fmt(struct snd_soc_dai *dai,
unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
unsigned int aif1 = snd_soc_component_read(component, WM8993_AUDIO_INTERFACE_1);
unsigned int aif4 = snd_soc_component_read(component, WM8993_AUDIO_INTERFACE_4);
aif1 &= ~(WM8993_BCLK_DIR | WM8993_AIF_BCLK_INV |
WM8993_AIF_LRCLK_INV | WM8993_AIF_FMT_MASK);
aif4 &= ~WM8993_LRCLK_DIR;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
wm8993->master = 0;
break;
case SND_SOC_DAIFMT_CBS_CFM:
aif4 |= WM8993_LRCLK_DIR;
wm8993->master = 1;
break;
case SND_SOC_DAIFMT_CBM_CFS:
aif1 |= WM8993_BCLK_DIR;
wm8993->master = 1;
break;
case SND_SOC_DAIFMT_CBM_CFM:
aif1 |= WM8993_BCLK_DIR;
aif4 |= WM8993_LRCLK_DIR;
wm8993->master = 1;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_B:
aif1 |= WM8993_AIF_LRCLK_INV;
fallthrough;
case SND_SOC_DAIFMT_DSP_A:
aif1 |= 0x18;
break;
case SND_SOC_DAIFMT_I2S:
aif1 |= 0x10;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
aif1 |= 0x8;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B:
/* frame inversion not valid for DSP modes */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
aif1 |= WM8993_AIF_BCLK_INV;
break;
default:
return -EINVAL;
}
break;
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_RIGHT_J:
case SND_SOC_DAIFMT_LEFT_J:
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
aif1 |= WM8993_AIF_BCLK_INV | WM8993_AIF_LRCLK_INV;
break;
case SND_SOC_DAIFMT_IB_NF:
aif1 |= WM8993_AIF_BCLK_INV;
break;
case SND_SOC_DAIFMT_NB_IF:
aif1 |= WM8993_AIF_LRCLK_INV;
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, WM8993_AUDIO_INTERFACE_1, aif1);
snd_soc_component_write(component, WM8993_AUDIO_INTERFACE_4, aif4);
return 0;
}
static int wm8993_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
int ret, i, best, best_val, cur_val;
unsigned int clocking1, clocking3, aif1, aif4;
clocking1 = snd_soc_component_read(component, WM8993_CLOCKING_1);
clocking1 &= ~WM8993_BCLK_DIV_MASK;
clocking3 = snd_soc_component_read(component, WM8993_CLOCKING_3);
clocking3 &= ~(WM8993_CLK_SYS_RATE_MASK | WM8993_SAMPLE_RATE_MASK);
aif1 = snd_soc_component_read(component, WM8993_AUDIO_INTERFACE_1);
aif1 &= ~WM8993_AIF_WL_MASK;
aif4 = snd_soc_component_read(component, WM8993_AUDIO_INTERFACE_4);
aif4 &= ~WM8993_LRCLK_RATE_MASK;
/* What BCLK do we need? */
wm8993->fs = params_rate(params);
wm8993->bclk = 2 * wm8993->fs;
if (wm8993->tdm_slots) {
dev_dbg(component->dev, "Configuring for %d %d bit TDM slots\n",
wm8993->tdm_slots, wm8993->tdm_width);
wm8993->bclk *= wm8993->tdm_width * wm8993->tdm_slots;
} else {
switch (params_width(params)) {
case 16:
wm8993->bclk *= 16;
break;
case 20:
wm8993->bclk *= 20;
aif1 |= 0x8;
break;
case 24:
wm8993->bclk *= 24;
aif1 |= 0x10;
break;
case 32:
wm8993->bclk *= 32;
aif1 |= 0x18;
break;
default:
return -EINVAL;
}
}
dev_dbg(component->dev, "Target BCLK is %dHz\n", wm8993->bclk);
ret = configure_clock(component);
if (ret != 0)
return ret;
/* Select nearest CLK_SYS_RATE */
best = 0;
best_val = abs((wm8993->sysclk_rate / clk_sys_rates[0].ratio)
- wm8993->fs);
for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
cur_val = abs((wm8993->sysclk_rate /
clk_sys_rates[i].ratio) - wm8993->fs);
if (cur_val < best_val) {
best = i;
best_val = cur_val;
}
}
dev_dbg(component->dev, "Selected CLK_SYS_RATIO of %d\n",
clk_sys_rates[best].ratio);
clocking3 |= (clk_sys_rates[best].clk_sys_rate
<< WM8993_CLK_SYS_RATE_SHIFT);
/* SAMPLE_RATE */
best = 0;
best_val = abs(wm8993->fs - sample_rates[0].rate);
for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
/* Closest match */
cur_val = abs(wm8993->fs - sample_rates[i].rate);
if (cur_val < best_val) {
best = i;
best_val = cur_val;
}
}
dev_dbg(component->dev, "Selected SAMPLE_RATE of %dHz\n",
sample_rates[best].rate);
clocking3 |= (sample_rates[best].sample_rate
<< WM8993_SAMPLE_RATE_SHIFT);
/* BCLK_DIV */
best = 0;
best_val = INT_MAX;
for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
cur_val = ((wm8993->sysclk_rate * 10) / bclk_divs[i].div)
- wm8993->bclk;
if (cur_val < 0) /* Table is sorted */
break;
if (cur_val < best_val) {
best = i;
best_val = cur_val;
}
}
wm8993->bclk = (wm8993->sysclk_rate * 10) / bclk_divs[best].div;
dev_dbg(component->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
bclk_divs[best].div, wm8993->bclk);
clocking1 |= bclk_divs[best].bclk_div << WM8993_BCLK_DIV_SHIFT;
/* LRCLK is a simple fraction of BCLK */
dev_dbg(component->dev, "LRCLK_RATE is %d\n", wm8993->bclk / wm8993->fs);
aif4 |= wm8993->bclk / wm8993->fs;
snd_soc_component_write(component, WM8993_CLOCKING_1, clocking1);
snd_soc_component_write(component, WM8993_CLOCKING_3, clocking3);
snd_soc_component_write(component, WM8993_AUDIO_INTERFACE_1, aif1);
snd_soc_component_write(component, WM8993_AUDIO_INTERFACE_4, aif4);
/* ReTune Mobile? */
if (wm8993->pdata.num_retune_configs) {
u16 eq1 = snd_soc_component_read(component, WM8993_EQ1);
struct wm8993_retune_mobile_setting *s;
best = 0;
best_val = abs(wm8993->pdata.retune_configs[0].rate
- wm8993->fs);
for (i = 0; i < wm8993->pdata.num_retune_configs; i++) {
cur_val = abs(wm8993->pdata.retune_configs[i].rate
- wm8993->fs);
if (cur_val < best_val) {
best_val = cur_val;
best = i;
}
}
s = &wm8993->pdata.retune_configs[best];
dev_dbg(component->dev, "ReTune Mobile %s tuned for %dHz\n",
s->name, s->rate);
/* Disable EQ while we reconfigure */
snd_soc_component_update_bits(component, WM8993_EQ1, WM8993_EQ_ENA, 0);
for (i = 1; i < ARRAY_SIZE(s->config); i++)
snd_soc_component_write(component, WM8993_EQ1 + i, s->config[i]);
snd_soc_component_update_bits(component, WM8993_EQ1, WM8993_EQ_ENA, eq1);
}
return 0;
}
static int wm8993_mute(struct snd_soc_dai *codec_dai, int mute, int direction)
{
struct snd_soc_component *component = codec_dai->component;
unsigned int reg;
reg = snd_soc_component_read(component, WM8993_DAC_CTRL);
if (mute)
reg |= WM8993_DAC_MUTE;
else
reg &= ~WM8993_DAC_MUTE;
snd_soc_component_write(component, WM8993_DAC_CTRL, reg);
return 0;
}
static int wm8993_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
int aif1 = 0;
int aif2 = 0;
/* Don't need to validate anything if we're turning off TDM */
if (slots == 0) {
wm8993->tdm_slots = 0;
goto out;
}
/* Note that we allow configurations we can't handle ourselves -
* for example, we can generate clocks for slots 2 and up even if
* we can't use those slots ourselves.
*/
aif1 |= WM8993_AIFADC_TDM;
aif2 |= WM8993_AIFDAC_TDM;
switch (rx_mask) {
case 3:
break;
case 0xc:
aif1 |= WM8993_AIFADC_TDM_CHAN;
break;
default:
return -EINVAL;
}
switch (tx_mask) {
case 3:
break;
case 0xc:
aif2 |= WM8993_AIFDAC_TDM_CHAN;
break;
default:
return -EINVAL;
}
out:
wm8993->tdm_width = slot_width;
wm8993->tdm_slots = slots / 2;
snd_soc_component_update_bits(component, WM8993_AUDIO_INTERFACE_1,
WM8993_AIFADC_TDM | WM8993_AIFADC_TDM_CHAN, aif1);
snd_soc_component_update_bits(component, WM8993_AUDIO_INTERFACE_2,
WM8993_AIFDAC_TDM | WM8993_AIFDAC_TDM_CHAN, aif2);
return 0;
}
static irqreturn_t wm8993_irq(int irq, void *data)
{
struct wm8993_priv *wm8993 = data;
int mask, val, ret;
ret = regmap_read(wm8993->regmap, WM8993_GPIO_CTRL_1, &val);
if (ret != 0) {
dev_err(wm8993->dev, "Failed to read interrupt status: %d\n",
ret);
return IRQ_NONE;
}
ret = regmap_read(wm8993->regmap, WM8993_GPIOCTRL_2, &mask);
if (ret != 0) {
dev_err(wm8993->dev, "Failed to read interrupt mask: %d\n",
ret);
return IRQ_NONE;
}
/* The IRQ pin status is visible in the register too */
val &= ~(mask | WM8993_IRQ);
if (!val)
return IRQ_NONE;
if (val & WM8993_TEMPOK_EINT)
dev_crit(wm8993->dev, "Thermal warning\n");
if (val & WM8993_FLL_LOCK_EINT) {
dev_dbg(wm8993->dev, "FLL locked\n");
complete(&wm8993->fll_lock);
}
ret = regmap_write(wm8993->regmap, WM8993_GPIO_CTRL_1, val);
if (ret != 0)
dev_err(wm8993->dev, "Failed to ack interrupt: %d\n", ret);
return IRQ_HANDLED;
}
static const struct snd_soc_dai_ops wm8993_ops = {
.set_sysclk = wm8993_set_sysclk,
.set_fmt = wm8993_set_dai_fmt,
.hw_params = wm8993_hw_params,
.mute_stream = wm8993_mute,
.set_pll = wm8993_set_fll,
.set_tdm_slot = wm8993_set_tdm_slot,
.no_capture_mute = 1,
};
#define WM8993_RATES SNDRV_PCM_RATE_8000_48000
#define WM8993_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver wm8993_dai = {
.name = "wm8993-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM8993_RATES,
.formats = WM8993_FORMATS,
.sig_bits = 24,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM8993_RATES,
.formats = WM8993_FORMATS,
.sig_bits = 24,
},
.ops = &wm8993_ops,
.symmetric_rate = 1,
};
static int wm8993_probe(struct snd_soc_component *component)
{
struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
wm8993->hubs_data.hp_startup_mode = 1;
wm8993->hubs_data.dcs_codes_l = -2;
wm8993->hubs_data.dcs_codes_r = -2;
wm8993->hubs_data.series_startup = 1;
/* Latch volume update bits and default ZC on */
snd_soc_component_update_bits(component, WM8993_RIGHT_DAC_DIGITAL_VOLUME,
WM8993_DAC_VU, WM8993_DAC_VU);
snd_soc_component_update_bits(component, WM8993_RIGHT_ADC_DIGITAL_VOLUME,
WM8993_ADC_VU, WM8993_ADC_VU);
/* Manualy manage the HPOUT sequencing for independent stereo
* control. */
snd_soc_component_update_bits(component, WM8993_ANALOGUE_HP_0,
WM8993_HPOUT1_AUTO_PU, 0);
/* Use automatic clock configuration */
snd_soc_component_update_bits(component, WM8993_CLOCKING_4, WM8993_SR_MODE, 0);
wm_hubs_handle_analogue_pdata(component, wm8993->pdata.lineout1_diff,
wm8993->pdata.lineout2_diff,
wm8993->pdata.lineout1fb,
wm8993->pdata.lineout2fb,
wm8993->pdata.jd_scthr,
wm8993->pdata.jd_thr,
wm8993->pdata.micbias1_delay,
wm8993->pdata.micbias2_delay,
wm8993->pdata.micbias1_lvl,
wm8993->pdata.micbias2_lvl);
snd_soc_add_component_controls(component, wm8993_snd_controls,
ARRAY_SIZE(wm8993_snd_controls));
if (wm8993->pdata.num_retune_configs != 0) {
dev_dbg(component->dev, "Using ReTune Mobile\n");
} else {
dev_dbg(component->dev, "No ReTune Mobile, using normal EQ\n");
snd_soc_add_component_controls(component, wm8993_eq_controls,
ARRAY_SIZE(wm8993_eq_controls));
}
snd_soc_dapm_new_controls(dapm, wm8993_dapm_widgets,
ARRAY_SIZE(wm8993_dapm_widgets));
wm_hubs_add_analogue_controls(component);
snd_soc_dapm_add_routes(dapm, routes, ARRAY_SIZE(routes));
wm_hubs_add_analogue_routes(component, wm8993->pdata.lineout1_diff,
wm8993->pdata.lineout2_diff);
/* If the line outputs are differential then we aren't presenting
* VMID as an output and can disable it.
*/
if (wm8993->pdata.lineout1_diff && wm8993->pdata.lineout2_diff)
dapm->idle_bias_off = 1;
return 0;
}
#ifdef CONFIG_PM
static int wm8993_suspend(struct snd_soc_component *component)
{
struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
int fll_fout = wm8993->fll_fout;
int fll_fref = wm8993->fll_fref;
int ret;
/* Stop the FLL in an orderly fashion */
ret = _wm8993_set_fll(component, 0, 0, 0, 0);
if (ret != 0) {
dev_err(component->dev, "Failed to stop FLL\n");
return ret;
}
wm8993->fll_fout = fll_fout;
wm8993->fll_fref = fll_fref;
snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
return 0;
}
static int wm8993_resume(struct snd_soc_component *component)
{
struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
int ret;
snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
/* Restart the FLL? */
if (wm8993->fll_fout) {
int fll_fout = wm8993->fll_fout;
int fll_fref = wm8993->fll_fref;
wm8993->fll_fref = 0;
wm8993->fll_fout = 0;
ret = _wm8993_set_fll(component, 0, wm8993->fll_src,
fll_fref, fll_fout);
if (ret != 0)
dev_err(component->dev, "Failed to restart FLL\n");
}
return 0;
}
#else
#define wm8993_suspend NULL
#define wm8993_resume NULL
#endif
/* Tune DC servo configuration */
static const struct reg_sequence wm8993_regmap_patch[] = {
{ 0x44, 3 },
{ 0x56, 3 },
{ 0x44, 0 },
};
static const struct regmap_config wm8993_regmap = {
.reg_bits = 8,
.val_bits = 16,
.max_register = WM8993_MAX_REGISTER,
.volatile_reg = wm8993_volatile,
.readable_reg = wm8993_readable,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = wm8993_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8993_reg_defaults),
};
static const struct snd_soc_component_driver soc_component_dev_wm8993 = {
.probe = wm8993_probe,
.suspend = wm8993_suspend,
.resume = wm8993_resume,
.set_bias_level = wm8993_set_bias_level,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int wm8993_i2c_probe(struct i2c_client *i2c)
{
struct wm8993_priv *wm8993;
unsigned int reg;
int ret, i;
wm8993 = devm_kzalloc(&i2c->dev, sizeof(struct wm8993_priv),
GFP_KERNEL);
if (wm8993 == NULL)
return -ENOMEM;
wm8993->dev = &i2c->dev;
init_completion(&wm8993->fll_lock);
wm8993->regmap = devm_regmap_init_i2c(i2c, &wm8993_regmap);
if (IS_ERR(wm8993->regmap)) {
ret = PTR_ERR(wm8993->regmap);
dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
return ret;
}
i2c_set_clientdata(i2c, wm8993);
for (i = 0; i < ARRAY_SIZE(wm8993->supplies); i++)
wm8993->supplies[i].supply = wm8993_supply_names[i];
ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8993->supplies),
wm8993->supplies);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
return ret;
}
ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies),
wm8993->supplies);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
return ret;
}
ret = regmap_read(wm8993->regmap, WM8993_SOFTWARE_RESET, ®);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret);
goto err_enable;
}
if (reg != 0x8993) {
dev_err(&i2c->dev, "Invalid ID register value %x\n", reg);
ret = -EINVAL;
goto err_enable;
}
ret = regmap_write(wm8993->regmap, WM8993_SOFTWARE_RESET, 0xffff);
if (ret != 0)
goto err_enable;
ret = regmap_register_patch(wm8993->regmap, wm8993_regmap_patch,
ARRAY_SIZE(wm8993_regmap_patch));
if (ret != 0)
dev_warn(wm8993->dev, "Failed to apply regmap patch: %d\n",
ret);
if (i2c->irq) {
/* Put GPIO1 into interrupt mode (only GPIO1 can output IRQ) */
ret = regmap_update_bits(wm8993->regmap, WM8993_GPIO1,
WM8993_GPIO1_PD |
WM8993_GPIO1_SEL_MASK, 7);
if (ret != 0)
goto err_enable;
ret = request_threaded_irq(i2c->irq, NULL, wm8993_irq,
IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
"wm8993", wm8993);
if (ret != 0)
goto err_enable;
}
regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
regcache_cache_only(wm8993->regmap, true);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_wm8993, &wm8993_dai, 1);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
goto err_irq;
}
return 0;
err_irq:
if (i2c->irq)
free_irq(i2c->irq, wm8993);
err_enable:
regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
return ret;
}
static void wm8993_i2c_remove(struct i2c_client *i2c)
{
struct wm8993_priv *wm8993 = i2c_get_clientdata(i2c);
if (i2c->irq)
free_irq(i2c->irq, wm8993);
regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
}
static const struct i2c_device_id wm8993_i2c_id[] = {
{ "wm8993", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8993_i2c_id);
static struct i2c_driver wm8993_i2c_driver = {
.driver = {
.name = "wm8993",
},
.probe = wm8993_i2c_probe,
.remove = wm8993_i2c_remove,
.id_table = wm8993_i2c_id,
};
module_i2c_driver(wm8993_i2c_driver);
MODULE_DESCRIPTION("ASoC WM8993 driver");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8993.c |
// SPDX-License-Identifier: GPL-2.0
//
// ALSA SoC Texas Instruments TAS2770 20-W Digital Input Mono Class-D
// Audio Amplifier with Speaker I/V Sense
//
// Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/
// Author: Tracy Yi <[email protected]>
// Frank Shi <[email protected]>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/regulator/consumer.h>
#include <linux/firmware.h>
#include <linux/regmap.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/slab.h>
#include <sound/soc.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "tas2770.h"
#define TAS2770_MDELAY 0xFFFFFFFE
static void tas2770_reset(struct tas2770_priv *tas2770)
{
if (tas2770->reset_gpio) {
gpiod_set_value_cansleep(tas2770->reset_gpio, 0);
msleep(20);
gpiod_set_value_cansleep(tas2770->reset_gpio, 1);
usleep_range(1000, 2000);
}
snd_soc_component_write(tas2770->component, TAS2770_SW_RST,
TAS2770_RST);
usleep_range(1000, 2000);
}
static int tas2770_update_pwr_ctrl(struct tas2770_priv *tas2770)
{
struct snd_soc_component *component = tas2770->component;
unsigned int val;
int ret;
if (tas2770->dac_powered)
val = tas2770->unmuted ?
TAS2770_PWR_CTRL_ACTIVE : TAS2770_PWR_CTRL_MUTE;
else
val = TAS2770_PWR_CTRL_SHUTDOWN;
ret = snd_soc_component_update_bits(component, TAS2770_PWR_CTRL,
TAS2770_PWR_CTRL_MASK, val);
if (ret < 0)
return ret;
return 0;
}
#ifdef CONFIG_PM
static int tas2770_codec_suspend(struct snd_soc_component *component)
{
struct tas2770_priv *tas2770 = snd_soc_component_get_drvdata(component);
int ret = 0;
regcache_cache_only(tas2770->regmap, true);
regcache_mark_dirty(tas2770->regmap);
if (tas2770->sdz_gpio) {
gpiod_set_value_cansleep(tas2770->sdz_gpio, 0);
} else {
ret = snd_soc_component_update_bits(component, TAS2770_PWR_CTRL,
TAS2770_PWR_CTRL_MASK,
TAS2770_PWR_CTRL_SHUTDOWN);
if (ret < 0) {
regcache_cache_only(tas2770->regmap, false);
regcache_sync(tas2770->regmap);
return ret;
}
ret = 0;
}
return ret;
}
static int tas2770_codec_resume(struct snd_soc_component *component)
{
struct tas2770_priv *tas2770 = snd_soc_component_get_drvdata(component);
int ret;
if (tas2770->sdz_gpio) {
gpiod_set_value_cansleep(tas2770->sdz_gpio, 1);
usleep_range(1000, 2000);
} else {
ret = tas2770_update_pwr_ctrl(tas2770);
if (ret < 0)
return ret;
}
regcache_cache_only(tas2770->regmap, false);
return regcache_sync(tas2770->regmap);
}
#else
#define tas2770_codec_suspend NULL
#define tas2770_codec_resume NULL
#endif
static const char * const tas2770_ASI1_src[] = {
"I2C offset", "Left", "Right", "LeftRightDiv2",
};
static SOC_ENUM_SINGLE_DECL(
tas2770_ASI1_src_enum, TAS2770_TDM_CFG_REG2,
4, tas2770_ASI1_src);
static const struct snd_kcontrol_new tas2770_asi1_mux =
SOC_DAPM_ENUM("ASI1 Source", tas2770_ASI1_src_enum);
static int tas2770_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct tas2770_priv *tas2770 =
snd_soc_component_get_drvdata(component);
int ret;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
tas2770->dac_powered = 1;
ret = tas2770_update_pwr_ctrl(tas2770);
break;
case SND_SOC_DAPM_PRE_PMD:
tas2770->dac_powered = 0;
ret = tas2770_update_pwr_ctrl(tas2770);
break;
default:
dev_err(tas2770->dev, "Not supported evevt\n");
return -EINVAL;
}
return ret;
}
static const struct snd_kcontrol_new isense_switch =
SOC_DAPM_SINGLE("Switch", TAS2770_PWR_CTRL, 3, 1, 1);
static const struct snd_kcontrol_new vsense_switch =
SOC_DAPM_SINGLE("Switch", TAS2770_PWR_CTRL, 2, 1, 1);
static const struct snd_soc_dapm_widget tas2770_dapm_widgets[] = {
SND_SOC_DAPM_AIF_IN("ASI1", "ASI1 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_MUX("ASI1 Sel", SND_SOC_NOPM, 0, 0, &tas2770_asi1_mux),
SND_SOC_DAPM_SWITCH("ISENSE", TAS2770_PWR_CTRL, 3, 1, &isense_switch),
SND_SOC_DAPM_SWITCH("VSENSE", TAS2770_PWR_CTRL, 2, 1, &vsense_switch),
SND_SOC_DAPM_DAC_E("DAC", NULL, SND_SOC_NOPM, 0, 0, tas2770_dac_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_OUTPUT("OUT"),
SND_SOC_DAPM_SIGGEN("VMON"),
SND_SOC_DAPM_SIGGEN("IMON")
};
static const struct snd_soc_dapm_route tas2770_audio_map[] = {
{"ASI1 Sel", "I2C offset", "ASI1"},
{"ASI1 Sel", "Left", "ASI1"},
{"ASI1 Sel", "Right", "ASI1"},
{"ASI1 Sel", "LeftRightDiv2", "ASI1"},
{"DAC", NULL, "ASI1 Sel"},
{"OUT", NULL, "DAC"},
{"ISENSE", "Switch", "IMON"},
{"VSENSE", "Switch", "VMON"},
};
static int tas2770_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
struct tas2770_priv *tas2770 =
snd_soc_component_get_drvdata(component);
tas2770->unmuted = !mute;
return tas2770_update_pwr_ctrl(tas2770);
}
static int tas2770_set_bitwidth(struct tas2770_priv *tas2770, int bitwidth)
{
int ret;
struct snd_soc_component *component = tas2770->component;
switch (bitwidth) {
case SNDRV_PCM_FORMAT_S16_LE:
ret = snd_soc_component_update_bits(component, TAS2770_TDM_CFG_REG2,
TAS2770_TDM_CFG_REG2_RXW_MASK,
TAS2770_TDM_CFG_REG2_RXW_16BITS);
tas2770->v_sense_slot = tas2770->i_sense_slot + 2;
break;
case SNDRV_PCM_FORMAT_S24_LE:
ret = snd_soc_component_update_bits(component, TAS2770_TDM_CFG_REG2,
TAS2770_TDM_CFG_REG2_RXW_MASK,
TAS2770_TDM_CFG_REG2_RXW_24BITS);
tas2770->v_sense_slot = tas2770->i_sense_slot + 4;
break;
case SNDRV_PCM_FORMAT_S32_LE:
ret = snd_soc_component_update_bits(component, TAS2770_TDM_CFG_REG2,
TAS2770_TDM_CFG_REG2_RXW_MASK,
TAS2770_TDM_CFG_REG2_RXW_32BITS);
tas2770->v_sense_slot = tas2770->i_sense_slot + 4;
break;
default:
return -EINVAL;
}
if (ret < 0)
return ret;
ret = snd_soc_component_update_bits(component, TAS2770_TDM_CFG_REG5,
TAS2770_TDM_CFG_REG5_VSNS_MASK |
TAS2770_TDM_CFG_REG5_50_MASK,
TAS2770_TDM_CFG_REG5_VSNS_ENABLE |
tas2770->v_sense_slot);
if (ret < 0)
return ret;
ret = snd_soc_component_update_bits(component, TAS2770_TDM_CFG_REG6,
TAS2770_TDM_CFG_REG6_ISNS_MASK |
TAS2770_TDM_CFG_REG6_50_MASK,
TAS2770_TDM_CFG_REG6_ISNS_ENABLE |
tas2770->i_sense_slot);
if (ret < 0)
return ret;
return 0;
}
static int tas2770_set_samplerate(struct tas2770_priv *tas2770, int samplerate)
{
struct snd_soc_component *component = tas2770->component;
int ramp_rate_val;
int ret;
switch (samplerate) {
case 48000:
ramp_rate_val = TAS2770_TDM_CFG_REG0_SMP_48KHZ |
TAS2770_TDM_CFG_REG0_31_44_1_48KHZ;
break;
case 44100:
ramp_rate_val = TAS2770_TDM_CFG_REG0_SMP_44_1KHZ |
TAS2770_TDM_CFG_REG0_31_44_1_48KHZ;
break;
case 96000:
ramp_rate_val = TAS2770_TDM_CFG_REG0_SMP_48KHZ |
TAS2770_TDM_CFG_REG0_31_88_2_96KHZ;
break;
case 88200:
ramp_rate_val = TAS2770_TDM_CFG_REG0_SMP_44_1KHZ |
TAS2770_TDM_CFG_REG0_31_88_2_96KHZ;
break;
case 192000:
ramp_rate_val = TAS2770_TDM_CFG_REG0_SMP_48KHZ |
TAS2770_TDM_CFG_REG0_31_176_4_192KHZ;
break;
case 176400:
ramp_rate_val = TAS2770_TDM_CFG_REG0_SMP_44_1KHZ |
TAS2770_TDM_CFG_REG0_31_176_4_192KHZ;
break;
default:
return -EINVAL;
}
ret = snd_soc_component_update_bits(component, TAS2770_TDM_CFG_REG0,
TAS2770_TDM_CFG_REG0_SMP_MASK |
TAS2770_TDM_CFG_REG0_31_MASK,
ramp_rate_val);
if (ret < 0)
return ret;
return 0;
}
static int tas2770_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct tas2770_priv *tas2770 =
snd_soc_component_get_drvdata(component);
int ret;
ret = tas2770_set_bitwidth(tas2770, params_format(params));
if (ret)
return ret;
return tas2770_set_samplerate(tas2770, params_rate(params));
}
static int tas2770_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct tas2770_priv *tas2770 =
snd_soc_component_get_drvdata(component);
u8 tdm_rx_start_slot = 0, invert_fpol = 0, fpol_preinv = 0, asi_cfg_1 = 0;
int ret;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC:
break;
default:
dev_err(tas2770->dev, "ASI invalid DAI clocking\n");
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_IF:
invert_fpol = 1;
fallthrough;
case SND_SOC_DAIFMT_NB_NF:
asi_cfg_1 |= TAS2770_TDM_CFG_REG1_RX_RSING;
break;
case SND_SOC_DAIFMT_IB_IF:
invert_fpol = 1;
fallthrough;
case SND_SOC_DAIFMT_IB_NF:
asi_cfg_1 |= TAS2770_TDM_CFG_REG1_RX_FALING;
break;
default:
dev_err(tas2770->dev, "ASI format Inverse is not found\n");
return -EINVAL;
}
ret = snd_soc_component_update_bits(component, TAS2770_TDM_CFG_REG1,
TAS2770_TDM_CFG_REG1_RX_MASK,
asi_cfg_1);
if (ret < 0)
return ret;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
tdm_rx_start_slot = 1;
fpol_preinv = 0;
break;
case SND_SOC_DAIFMT_DSP_A:
tdm_rx_start_slot = 0;
fpol_preinv = 1;
break;
case SND_SOC_DAIFMT_DSP_B:
tdm_rx_start_slot = 1;
fpol_preinv = 1;
break;
case SND_SOC_DAIFMT_LEFT_J:
tdm_rx_start_slot = 0;
fpol_preinv = 1;
break;
default:
dev_err(tas2770->dev,
"DAI Format is not found, fmt=0x%x\n", fmt);
return -EINVAL;
}
ret = snd_soc_component_update_bits(component, TAS2770_TDM_CFG_REG1,
TAS2770_TDM_CFG_REG1_MASK,
(tdm_rx_start_slot << TAS2770_TDM_CFG_REG1_51_SHIFT));
if (ret < 0)
return ret;
ret = snd_soc_component_update_bits(component, TAS2770_TDM_CFG_REG0,
TAS2770_TDM_CFG_REG0_FPOL_MASK,
(fpol_preinv ^ invert_fpol)
? TAS2770_TDM_CFG_REG0_FPOL_RSING
: TAS2770_TDM_CFG_REG0_FPOL_FALING);
if (ret < 0)
return ret;
return 0;
}
static int tas2770_set_dai_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask,
unsigned int rx_mask,
int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
int left_slot, right_slot;
int ret;
if (tx_mask == 0 || rx_mask != 0)
return -EINVAL;
left_slot = __ffs(tx_mask);
tx_mask &= ~(1 << left_slot);
if (tx_mask == 0) {
right_slot = left_slot;
} else {
right_slot = __ffs(tx_mask);
tx_mask &= ~(1 << right_slot);
}
if (tx_mask != 0 || left_slot >= slots || right_slot >= slots)
return -EINVAL;
ret = snd_soc_component_update_bits(component, TAS2770_TDM_CFG_REG3,
TAS2770_TDM_CFG_REG3_30_MASK,
(left_slot << TAS2770_TDM_CFG_REG3_30_SHIFT));
if (ret < 0)
return ret;
ret = snd_soc_component_update_bits(component, TAS2770_TDM_CFG_REG3,
TAS2770_TDM_CFG_REG3_RXS_MASK,
(right_slot << TAS2770_TDM_CFG_REG3_RXS_SHIFT));
if (ret < 0)
return ret;
switch (slot_width) {
case 16:
ret = snd_soc_component_update_bits(component, TAS2770_TDM_CFG_REG2,
TAS2770_TDM_CFG_REG2_RXS_MASK,
TAS2770_TDM_CFG_REG2_RXS_16BITS);
break;
case 24:
ret = snd_soc_component_update_bits(component, TAS2770_TDM_CFG_REG2,
TAS2770_TDM_CFG_REG2_RXS_MASK,
TAS2770_TDM_CFG_REG2_RXS_24BITS);
break;
case 32:
ret = snd_soc_component_update_bits(component, TAS2770_TDM_CFG_REG2,
TAS2770_TDM_CFG_REG2_RXS_MASK,
TAS2770_TDM_CFG_REG2_RXS_32BITS);
break;
case 0:
/* Do not change slot width */
ret = 0;
break;
default:
ret = -EINVAL;
}
if (ret < 0)
return ret;
return 0;
}
static const struct snd_soc_dai_ops tas2770_dai_ops = {
.mute_stream = tas2770_mute,
.hw_params = tas2770_hw_params,
.set_fmt = tas2770_set_fmt,
.set_tdm_slot = tas2770_set_dai_tdm_slot,
.no_capture_mute = 1,
};
#define TAS2770_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
#define TAS2770_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_192000\
)
static struct snd_soc_dai_driver tas2770_dai_driver[] = {
{
.name = "tas2770 ASI1",
.id = 0,
.playback = {
.stream_name = "ASI1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = TAS2770_RATES,
.formats = TAS2770_FORMATS,
},
.capture = {
.stream_name = "ASI1 Capture",
.channels_min = 0,
.channels_max = 2,
.rates = TAS2770_RATES,
.formats = TAS2770_FORMATS,
},
.ops = &tas2770_dai_ops,
.symmetric_rate = 1,
},
};
static const struct regmap_config tas2770_i2c_regmap;
static int tas2770_codec_probe(struct snd_soc_component *component)
{
struct tas2770_priv *tas2770 =
snd_soc_component_get_drvdata(component);
tas2770->component = component;
if (tas2770->sdz_gpio) {
gpiod_set_value_cansleep(tas2770->sdz_gpio, 1);
usleep_range(1000, 2000);
}
tas2770_reset(tas2770);
regmap_reinit_cache(tas2770->regmap, &tas2770_i2c_regmap);
return 0;
}
static DECLARE_TLV_DB_SCALE(tas2770_digital_tlv, 1100, 50, 0);
static DECLARE_TLV_DB_SCALE(tas2770_playback_volume, -12750, 50, 0);
static const struct snd_kcontrol_new tas2770_snd_controls[] = {
SOC_SINGLE_TLV("Speaker Playback Volume", TAS2770_PLAY_CFG_REG2,
0, TAS2770_PLAY_CFG_REG2_VMAX, 1, tas2770_playback_volume),
SOC_SINGLE_TLV("Amp Gain Volume", TAS2770_PLAY_CFG_REG0, 0, 0x14, 0,
tas2770_digital_tlv),
};
static const struct snd_soc_component_driver soc_component_driver_tas2770 = {
.probe = tas2770_codec_probe,
.suspend = tas2770_codec_suspend,
.resume = tas2770_codec_resume,
.controls = tas2770_snd_controls,
.num_controls = ARRAY_SIZE(tas2770_snd_controls),
.dapm_widgets = tas2770_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(tas2770_dapm_widgets),
.dapm_routes = tas2770_audio_map,
.num_dapm_routes = ARRAY_SIZE(tas2770_audio_map),
.idle_bias_on = 1,
.endianness = 1,
};
static int tas2770_register_codec(struct tas2770_priv *tas2770)
{
return devm_snd_soc_register_component(tas2770->dev,
&soc_component_driver_tas2770,
tas2770_dai_driver, ARRAY_SIZE(tas2770_dai_driver));
}
static const struct reg_default tas2770_reg_defaults[] = {
{ TAS2770_PAGE, 0x00 },
{ TAS2770_SW_RST, 0x00 },
{ TAS2770_PWR_CTRL, 0x0e },
{ TAS2770_PLAY_CFG_REG0, 0x10 },
{ TAS2770_PLAY_CFG_REG1, 0x01 },
{ TAS2770_PLAY_CFG_REG2, 0x00 },
{ TAS2770_MSC_CFG_REG0, 0x07 },
{ TAS2770_TDM_CFG_REG1, 0x02 },
{ TAS2770_TDM_CFG_REG2, 0x0a },
{ TAS2770_TDM_CFG_REG3, 0x10 },
{ TAS2770_INT_MASK_REG0, 0xfc },
{ TAS2770_INT_MASK_REG1, 0xb1 },
{ TAS2770_INT_CFG, 0x05 },
{ TAS2770_MISC_IRQ, 0x81 },
{ TAS2770_CLK_CGF, 0x0c },
};
static bool tas2770_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case TAS2770_PAGE: /* regmap implementation requires this */
case TAS2770_SW_RST: /* always clears after write */
case TAS2770_BO_PRV_REG0:/* has a self clearing bit */
case TAS2770_LVE_INT_REG0:
case TAS2770_LVE_INT_REG1:
case TAS2770_LAT_INT_REG0:/* Sticky interrupt flags */
case TAS2770_LAT_INT_REG1:/* Sticky interrupt flags */
case TAS2770_VBAT_MSB:
case TAS2770_VBAT_LSB:
case TAS2770_TEMP_MSB:
case TAS2770_TEMP_LSB:
return true;
}
return false;
}
static bool tas2770_writeable(struct device *dev, unsigned int reg)
{
switch (reg) {
case TAS2770_LVE_INT_REG0:
case TAS2770_LVE_INT_REG1:
case TAS2770_LAT_INT_REG0:
case TAS2770_LAT_INT_REG1:
case TAS2770_VBAT_MSB:
case TAS2770_VBAT_LSB:
case TAS2770_TEMP_MSB:
case TAS2770_TEMP_LSB:
case TAS2770_TDM_CLK_DETC:
case TAS2770_REV_AND_GPID:
return false;
}
return true;
}
static const struct regmap_range_cfg tas2770_regmap_ranges[] = {
{
.range_min = 0,
.range_max = 1 * 128,
.selector_reg = TAS2770_PAGE,
.selector_mask = 0xff,
.selector_shift = 0,
.window_start = 0,
.window_len = 128,
},
};
static const struct regmap_config tas2770_i2c_regmap = {
.reg_bits = 8,
.val_bits = 8,
.writeable_reg = tas2770_writeable,
.volatile_reg = tas2770_volatile,
.reg_defaults = tas2770_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tas2770_reg_defaults),
.cache_type = REGCACHE_RBTREE,
.ranges = tas2770_regmap_ranges,
.num_ranges = ARRAY_SIZE(tas2770_regmap_ranges),
.max_register = 1 * 128,
};
static int tas2770_parse_dt(struct device *dev, struct tas2770_priv *tas2770)
{
int rc = 0;
rc = fwnode_property_read_u32(dev->fwnode, "ti,imon-slot-no",
&tas2770->i_sense_slot);
if (rc) {
dev_info(tas2770->dev, "Property %s is missing setting default slot\n",
"ti,imon-slot-no");
tas2770->i_sense_slot = 0;
}
rc = fwnode_property_read_u32(dev->fwnode, "ti,vmon-slot-no",
&tas2770->v_sense_slot);
if (rc) {
dev_info(tas2770->dev, "Property %s is missing setting default slot\n",
"ti,vmon-slot-no");
tas2770->v_sense_slot = 2;
}
tas2770->sdz_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH);
if (IS_ERR(tas2770->sdz_gpio)) {
if (PTR_ERR(tas2770->sdz_gpio) == -EPROBE_DEFER)
return -EPROBE_DEFER;
tas2770->sdz_gpio = NULL;
}
return 0;
}
static int tas2770_i2c_probe(struct i2c_client *client)
{
struct tas2770_priv *tas2770;
int result;
tas2770 = devm_kzalloc(&client->dev, sizeof(struct tas2770_priv),
GFP_KERNEL);
if (!tas2770)
return -ENOMEM;
tas2770->dev = &client->dev;
i2c_set_clientdata(client, tas2770);
dev_set_drvdata(&client->dev, tas2770);
tas2770->regmap = devm_regmap_init_i2c(client, &tas2770_i2c_regmap);
if (IS_ERR(tas2770->regmap)) {
result = PTR_ERR(tas2770->regmap);
dev_err(&client->dev, "Failed to allocate register map: %d\n",
result);
return result;
}
if (client->dev.of_node) {
result = tas2770_parse_dt(&client->dev, tas2770);
if (result) {
dev_err(tas2770->dev, "%s: Failed to parse devicetree\n",
__func__);
return result;
}
}
tas2770->reset_gpio = devm_gpiod_get_optional(tas2770->dev, "reset",
GPIOD_OUT_HIGH);
if (IS_ERR(tas2770->reset_gpio)) {
if (PTR_ERR(tas2770->reset_gpio) == -EPROBE_DEFER) {
tas2770->reset_gpio = NULL;
return -EPROBE_DEFER;
}
}
result = tas2770_register_codec(tas2770);
if (result)
dev_err(tas2770->dev, "Register codec failed.\n");
return result;
}
static const struct i2c_device_id tas2770_i2c_id[] = {
{ "tas2770", 0},
{ }
};
MODULE_DEVICE_TABLE(i2c, tas2770_i2c_id);
#if defined(CONFIG_OF)
static const struct of_device_id tas2770_of_match[] = {
{ .compatible = "ti,tas2770" },
{},
};
MODULE_DEVICE_TABLE(of, tas2770_of_match);
#endif
static struct i2c_driver tas2770_i2c_driver = {
.driver = {
.name = "tas2770",
.of_match_table = of_match_ptr(tas2770_of_match),
},
.probe = tas2770_i2c_probe,
.id_table = tas2770_i2c_id,
};
module_i2c_driver(tas2770_i2c_driver);
MODULE_AUTHOR("Shi Fu <[email protected]>");
MODULE_DESCRIPTION("TAS2770 I2C Smart Amplifier driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/tas2770.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* rt5645.c -- RT5645 ALSA SoC audio codec driver
*
* Copyright 2013 Realtek Semiconductor Corp.
* Author: Bard Liao <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/gpio/consumer.h>
#include <linux/acpi.h>
#include <linux/dmi.h>
#include <linux/regulator/consumer.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/jack.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "rl6231.h"
#include "rt5645.h"
#define QUIRK_INV_JD1_1(q) ((q) & 1)
#define QUIRK_LEVEL_IRQ(q) (((q) >> 1) & 1)
#define QUIRK_IN2_DIFF(q) (((q) >> 2) & 1)
#define QUIRK_INV_HP_POL(q) (((q) >> 3) & 1)
#define QUIRK_JD_MODE(q) (((q) >> 4) & 7)
#define QUIRK_DMIC1_DATA_PIN(q) (((q) >> 8) & 3)
#define QUIRK_DMIC2_DATA_PIN(q) (((q) >> 12) & 3)
static unsigned int quirk = -1;
module_param(quirk, uint, 0444);
MODULE_PARM_DESC(quirk, "RT5645 pdata quirk override");
static const struct acpi_gpio_mapping *cht_rt5645_gpios;
#define RT5645_DEVICE_ID 0x6308
#define RT5650_DEVICE_ID 0x6419
#define RT5645_PR_RANGE_BASE (0xff + 1)
#define RT5645_PR_SPACING 0x100
#define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING))
#define RT5645_HWEQ_NUM 57
#define TIME_TO_POWER_MS 400
static const struct regmap_range_cfg rt5645_ranges[] = {
{
.name = "PR",
.range_min = RT5645_PR_BASE,
.range_max = RT5645_PR_BASE + 0xf8,
.selector_reg = RT5645_PRIV_INDEX,
.selector_mask = 0xff,
.selector_shift = 0x0,
.window_start = RT5645_PRIV_DATA,
.window_len = 0x1,
},
};
static const struct reg_sequence init_list[] = {
{RT5645_PR_BASE + 0x3d, 0x3600},
{RT5645_PR_BASE + 0x1c, 0xfd70},
{RT5645_PR_BASE + 0x20, 0x611f},
{RT5645_PR_BASE + 0x21, 0x4040},
{RT5645_PR_BASE + 0x23, 0x0004},
{RT5645_ASRC_4, 0x0120},
};
static const struct reg_sequence rt5650_init_list[] = {
{0xf6, 0x0100},
{RT5645_PWR_ANLG1, 0x02},
};
static const struct reg_default rt5645_reg[] = {
{ 0x00, 0x0000 },
{ 0x01, 0xc8c8 },
{ 0x02, 0xc8c8 },
{ 0x03, 0xc8c8 },
{ 0x0a, 0x0002 },
{ 0x0b, 0x2827 },
{ 0x0c, 0xe000 },
{ 0x0d, 0x0000 },
{ 0x0e, 0x0000 },
{ 0x0f, 0x0808 },
{ 0x14, 0x3333 },
{ 0x16, 0x4b00 },
{ 0x18, 0x018b },
{ 0x19, 0xafaf },
{ 0x1a, 0xafaf },
{ 0x1b, 0x0001 },
{ 0x1c, 0x2f2f },
{ 0x1d, 0x2f2f },
{ 0x1e, 0x0000 },
{ 0x20, 0x0000 },
{ 0x27, 0x7060 },
{ 0x28, 0x7070 },
{ 0x29, 0x8080 },
{ 0x2a, 0x5656 },
{ 0x2b, 0x5454 },
{ 0x2c, 0xaaa0 },
{ 0x2d, 0x0000 },
{ 0x2f, 0x1002 },
{ 0x31, 0x5000 },
{ 0x32, 0x0000 },
{ 0x33, 0x0000 },
{ 0x34, 0x0000 },
{ 0x35, 0x0000 },
{ 0x3b, 0x0000 },
{ 0x3c, 0x007f },
{ 0x3d, 0x0000 },
{ 0x3e, 0x007f },
{ 0x3f, 0x0000 },
{ 0x40, 0x001f },
{ 0x41, 0x0000 },
{ 0x42, 0x001f },
{ 0x45, 0x6000 },
{ 0x46, 0x003e },
{ 0x47, 0x003e },
{ 0x48, 0xf807 },
{ 0x4a, 0x0004 },
{ 0x4d, 0x0000 },
{ 0x4e, 0x0000 },
{ 0x4f, 0x01ff },
{ 0x50, 0x0000 },
{ 0x51, 0x0000 },
{ 0x52, 0x01ff },
{ 0x53, 0xf000 },
{ 0x56, 0x0111 },
{ 0x57, 0x0064 },
{ 0x58, 0xef0e },
{ 0x59, 0xf0f0 },
{ 0x5a, 0xef0e },
{ 0x5b, 0xf0f0 },
{ 0x5c, 0xef0e },
{ 0x5d, 0xf0f0 },
{ 0x5e, 0xf000 },
{ 0x5f, 0x0000 },
{ 0x61, 0x0300 },
{ 0x62, 0x0000 },
{ 0x63, 0x00c2 },
{ 0x64, 0x0000 },
{ 0x65, 0x0000 },
{ 0x66, 0x0000 },
{ 0x6a, 0x0000 },
{ 0x6c, 0x0aaa },
{ 0x70, 0x8000 },
{ 0x71, 0x8000 },
{ 0x72, 0x8000 },
{ 0x73, 0x7770 },
{ 0x74, 0x3e00 },
{ 0x75, 0x2409 },
{ 0x76, 0x000a },
{ 0x77, 0x0c00 },
{ 0x78, 0x0000 },
{ 0x79, 0x0123 },
{ 0x80, 0x0000 },
{ 0x81, 0x0000 },
{ 0x82, 0x0000 },
{ 0x83, 0x0000 },
{ 0x84, 0x0000 },
{ 0x85, 0x0000 },
{ 0x8a, 0x0120 },
{ 0x8e, 0x0004 },
{ 0x8f, 0x1100 },
{ 0x90, 0x0646 },
{ 0x91, 0x0c06 },
{ 0x93, 0x0000 },
{ 0x94, 0x0200 },
{ 0x95, 0x0000 },
{ 0x9a, 0x2184 },
{ 0x9b, 0x010a },
{ 0x9c, 0x0aea },
{ 0x9d, 0x000c },
{ 0x9e, 0x0400 },
{ 0xa0, 0xa0a8 },
{ 0xa1, 0x0059 },
{ 0xa2, 0x0001 },
{ 0xae, 0x6000 },
{ 0xaf, 0x0000 },
{ 0xb0, 0x6000 },
{ 0xb1, 0x0000 },
{ 0xb2, 0x0000 },
{ 0xb3, 0x001f },
{ 0xb4, 0x020c },
{ 0xb5, 0x1f00 },
{ 0xb6, 0x0000 },
{ 0xbb, 0x0000 },
{ 0xbc, 0x0000 },
{ 0xbd, 0x0000 },
{ 0xbe, 0x0000 },
{ 0xbf, 0x3100 },
{ 0xc0, 0x0000 },
{ 0xc1, 0x0000 },
{ 0xc2, 0x0000 },
{ 0xc3, 0x2000 },
{ 0xcd, 0x0000 },
{ 0xce, 0x0000 },
{ 0xcf, 0x1813 },
{ 0xd0, 0x0690 },
{ 0xd1, 0x1c17 },
{ 0xd3, 0xb320 },
{ 0xd4, 0x0000 },
{ 0xd6, 0x0400 },
{ 0xd9, 0x0809 },
{ 0xda, 0x0000 },
{ 0xdb, 0x0003 },
{ 0xdc, 0x0049 },
{ 0xdd, 0x001b },
{ 0xdf, 0x0008 },
{ 0xe0, 0x4000 },
{ 0xe6, 0x8000 },
{ 0xe7, 0x0200 },
{ 0xec, 0xb300 },
{ 0xed, 0x0000 },
{ 0xf0, 0x001f },
{ 0xf1, 0x020c },
{ 0xf2, 0x1f00 },
{ 0xf3, 0x0000 },
{ 0xf4, 0x4000 },
{ 0xf8, 0x0000 },
{ 0xf9, 0x0000 },
{ 0xfa, 0x2060 },
{ 0xfb, 0x4040 },
{ 0xfc, 0x0000 },
{ 0xfd, 0x0002 },
{ 0xfe, 0x10ec },
{ 0xff, 0x6308 },
};
static const struct reg_default rt5650_reg[] = {
{ 0x00, 0x0000 },
{ 0x01, 0xc8c8 },
{ 0x02, 0xc8c8 },
{ 0x03, 0xc8c8 },
{ 0x0a, 0x0002 },
{ 0x0b, 0x2827 },
{ 0x0c, 0xe000 },
{ 0x0d, 0x0000 },
{ 0x0e, 0x0000 },
{ 0x0f, 0x0808 },
{ 0x14, 0x3333 },
{ 0x16, 0x4b00 },
{ 0x18, 0x018b },
{ 0x19, 0xafaf },
{ 0x1a, 0xafaf },
{ 0x1b, 0x0001 },
{ 0x1c, 0x2f2f },
{ 0x1d, 0x2f2f },
{ 0x1e, 0x0000 },
{ 0x20, 0x0000 },
{ 0x27, 0x7060 },
{ 0x28, 0x7070 },
{ 0x29, 0x8080 },
{ 0x2a, 0x5656 },
{ 0x2b, 0x5454 },
{ 0x2c, 0xaaa0 },
{ 0x2d, 0x0000 },
{ 0x2f, 0x5002 },
{ 0x31, 0x5000 },
{ 0x32, 0x0000 },
{ 0x33, 0x0000 },
{ 0x34, 0x0000 },
{ 0x35, 0x0000 },
{ 0x3b, 0x0000 },
{ 0x3c, 0x007f },
{ 0x3d, 0x0000 },
{ 0x3e, 0x007f },
{ 0x3f, 0x0000 },
{ 0x40, 0x001f },
{ 0x41, 0x0000 },
{ 0x42, 0x001f },
{ 0x45, 0x6000 },
{ 0x46, 0x003e },
{ 0x47, 0x003e },
{ 0x48, 0xf807 },
{ 0x4a, 0x0004 },
{ 0x4d, 0x0000 },
{ 0x4e, 0x0000 },
{ 0x4f, 0x01ff },
{ 0x50, 0x0000 },
{ 0x51, 0x0000 },
{ 0x52, 0x01ff },
{ 0x53, 0xf000 },
{ 0x56, 0x0111 },
{ 0x57, 0x0064 },
{ 0x58, 0xef0e },
{ 0x59, 0xf0f0 },
{ 0x5a, 0xef0e },
{ 0x5b, 0xf0f0 },
{ 0x5c, 0xef0e },
{ 0x5d, 0xf0f0 },
{ 0x5e, 0xf000 },
{ 0x5f, 0x0000 },
{ 0x61, 0x0300 },
{ 0x62, 0x0000 },
{ 0x63, 0x00c2 },
{ 0x64, 0x0000 },
{ 0x65, 0x0000 },
{ 0x66, 0x0000 },
{ 0x6a, 0x0000 },
{ 0x6c, 0x0aaa },
{ 0x70, 0x8000 },
{ 0x71, 0x8000 },
{ 0x72, 0x8000 },
{ 0x73, 0x7770 },
{ 0x74, 0x3e00 },
{ 0x75, 0x2409 },
{ 0x76, 0x000a },
{ 0x77, 0x0c00 },
{ 0x78, 0x0000 },
{ 0x79, 0x0123 },
{ 0x7a, 0x0123 },
{ 0x80, 0x0000 },
{ 0x81, 0x0000 },
{ 0x82, 0x0000 },
{ 0x83, 0x0000 },
{ 0x84, 0x0000 },
{ 0x85, 0x0000 },
{ 0x8a, 0x0120 },
{ 0x8e, 0x0004 },
{ 0x8f, 0x1100 },
{ 0x90, 0x0646 },
{ 0x91, 0x0c06 },
{ 0x93, 0x0000 },
{ 0x94, 0x0200 },
{ 0x95, 0x0000 },
{ 0x9a, 0x2184 },
{ 0x9b, 0x010a },
{ 0x9c, 0x0aea },
{ 0x9d, 0x000c },
{ 0x9e, 0x0400 },
{ 0xa0, 0xa0a8 },
{ 0xa1, 0x0059 },
{ 0xa2, 0x0001 },
{ 0xae, 0x6000 },
{ 0xaf, 0x0000 },
{ 0xb0, 0x6000 },
{ 0xb1, 0x0000 },
{ 0xb2, 0x0000 },
{ 0xb3, 0x001f },
{ 0xb4, 0x020c },
{ 0xb5, 0x1f00 },
{ 0xb6, 0x0000 },
{ 0xbb, 0x0000 },
{ 0xbc, 0x0000 },
{ 0xbd, 0x0000 },
{ 0xbe, 0x0000 },
{ 0xbf, 0x3100 },
{ 0xc0, 0x0000 },
{ 0xc1, 0x0000 },
{ 0xc2, 0x0000 },
{ 0xc3, 0x2000 },
{ 0xcd, 0x0000 },
{ 0xce, 0x0000 },
{ 0xcf, 0x1813 },
{ 0xd0, 0x0690 },
{ 0xd1, 0x1c17 },
{ 0xd3, 0xb320 },
{ 0xd4, 0x0000 },
{ 0xd6, 0x0400 },
{ 0xd9, 0x0809 },
{ 0xda, 0x0000 },
{ 0xdb, 0x0003 },
{ 0xdc, 0x0049 },
{ 0xdd, 0x001b },
{ 0xdf, 0x0008 },
{ 0xe0, 0x4000 },
{ 0xe6, 0x8000 },
{ 0xe7, 0x0200 },
{ 0xec, 0xb300 },
{ 0xed, 0x0000 },
{ 0xf0, 0x001f },
{ 0xf1, 0x020c },
{ 0xf2, 0x1f00 },
{ 0xf3, 0x0000 },
{ 0xf4, 0x4000 },
{ 0xf8, 0x0000 },
{ 0xf9, 0x0000 },
{ 0xfa, 0x2060 },
{ 0xfb, 0x4040 },
{ 0xfc, 0x0000 },
{ 0xfd, 0x0002 },
{ 0xfe, 0x10ec },
{ 0xff, 0x6308 },
};
struct rt5645_eq_param_s {
unsigned short reg;
unsigned short val;
};
struct rt5645_eq_param_s_be16 {
__be16 reg;
__be16 val;
};
static const char *const rt5645_supply_names[] = {
"avdd",
"cpvdd",
};
struct rt5645_platform_data {
/* IN2 can optionally be differential */
bool in2_diff;
unsigned int dmic1_data_pin;
/* 0 = IN2N; 1 = GPIO5; 2 = GPIO11 */
unsigned int dmic2_data_pin;
/* 0 = IN2P; 1 = GPIO6; 2 = GPIO10; 3 = GPIO12 */
unsigned int jd_mode;
/* Use level triggered irq */
bool level_trigger_irq;
/* Invert JD1_1 status polarity */
bool inv_jd1_1;
/* Invert HP detect status polarity */
bool inv_hp_pol;
/* Value to assign to snd_soc_card.long_name */
const char *long_name;
/* Some (package) variants have the headset-mic pin not-connected */
bool no_headset_mic;
};
struct rt5645_priv {
struct snd_soc_component *component;
struct rt5645_platform_data pdata;
struct regmap *regmap;
struct i2c_client *i2c;
struct gpio_desc *gpiod_hp_det;
struct snd_soc_jack *hp_jack;
struct snd_soc_jack *mic_jack;
struct snd_soc_jack *btn_jack;
struct delayed_work jack_detect_work, rcclock_work;
struct regulator_bulk_data supplies[ARRAY_SIZE(rt5645_supply_names)];
struct rt5645_eq_param_s *eq_param;
struct timer_list btn_check_timer;
int codec_type;
int sysclk;
int sysclk_src;
int lrck[RT5645_AIFS];
int bclk[RT5645_AIFS];
int master[RT5645_AIFS];
int pll_src;
int pll_in;
int pll_out;
int jack_type;
bool en_button_func;
int v_id;
};
static int rt5645_reset(struct snd_soc_component *component)
{
return snd_soc_component_write(component, RT5645_RESET, 0);
}
static bool rt5645_volatile_register(struct device *dev, unsigned int reg)
{
int i;
for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
if (reg >= rt5645_ranges[i].range_min &&
reg <= rt5645_ranges[i].range_max) {
return true;
}
}
switch (reg) {
case RT5645_RESET:
case RT5645_PRIV_INDEX:
case RT5645_PRIV_DATA:
case RT5645_IN1_CTRL1:
case RT5645_IN1_CTRL2:
case RT5645_IN1_CTRL3:
case RT5645_A_JD_CTRL1:
case RT5645_ADC_EQ_CTRL1:
case RT5645_EQ_CTRL1:
case RT5645_ALC_CTRL_1:
case RT5645_IRQ_CTRL2:
case RT5645_IRQ_CTRL3:
case RT5645_INT_IRQ_ST:
case RT5645_IL_CMD:
case RT5650_4BTN_IL_CMD1:
case RT5645_VENDOR_ID:
case RT5645_VENDOR_ID1:
case RT5645_VENDOR_ID2:
return true;
default:
return false;
}
}
static bool rt5645_readable_register(struct device *dev, unsigned int reg)
{
int i;
for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
if (reg >= rt5645_ranges[i].range_min &&
reg <= rt5645_ranges[i].range_max) {
return true;
}
}
switch (reg) {
case RT5645_RESET:
case RT5645_SPK_VOL:
case RT5645_HP_VOL:
case RT5645_LOUT1:
case RT5645_IN1_CTRL1:
case RT5645_IN1_CTRL2:
case RT5645_IN1_CTRL3:
case RT5645_IN2_CTRL:
case RT5645_INL1_INR1_VOL:
case RT5645_SPK_FUNC_LIM:
case RT5645_ADJ_HPF_CTRL:
case RT5645_DAC1_DIG_VOL:
case RT5645_DAC2_DIG_VOL:
case RT5645_DAC_CTRL:
case RT5645_STO1_ADC_DIG_VOL:
case RT5645_MONO_ADC_DIG_VOL:
case RT5645_ADC_BST_VOL1:
case RT5645_ADC_BST_VOL2:
case RT5645_STO1_ADC_MIXER:
case RT5645_MONO_ADC_MIXER:
case RT5645_AD_DA_MIXER:
case RT5645_STO_DAC_MIXER:
case RT5645_MONO_DAC_MIXER:
case RT5645_DIG_MIXER:
case RT5650_A_DAC_SOUR:
case RT5645_DIG_INF1_DATA:
case RT5645_PDM_OUT_CTRL:
case RT5645_REC_L1_MIXER:
case RT5645_REC_L2_MIXER:
case RT5645_REC_R1_MIXER:
case RT5645_REC_R2_MIXER:
case RT5645_HPMIXL_CTRL:
case RT5645_HPOMIXL_CTRL:
case RT5645_HPMIXR_CTRL:
case RT5645_HPOMIXR_CTRL:
case RT5645_HPO_MIXER:
case RT5645_SPK_L_MIXER:
case RT5645_SPK_R_MIXER:
case RT5645_SPO_MIXER:
case RT5645_SPO_CLSD_RATIO:
case RT5645_OUT_L1_MIXER:
case RT5645_OUT_R1_MIXER:
case RT5645_OUT_L_GAIN1:
case RT5645_OUT_L_GAIN2:
case RT5645_OUT_R_GAIN1:
case RT5645_OUT_R_GAIN2:
case RT5645_LOUT_MIXER:
case RT5645_HAPTIC_CTRL1:
case RT5645_HAPTIC_CTRL2:
case RT5645_HAPTIC_CTRL3:
case RT5645_HAPTIC_CTRL4:
case RT5645_HAPTIC_CTRL5:
case RT5645_HAPTIC_CTRL6:
case RT5645_HAPTIC_CTRL7:
case RT5645_HAPTIC_CTRL8:
case RT5645_HAPTIC_CTRL9:
case RT5645_HAPTIC_CTRL10:
case RT5645_PWR_DIG1:
case RT5645_PWR_DIG2:
case RT5645_PWR_ANLG1:
case RT5645_PWR_ANLG2:
case RT5645_PWR_MIXER:
case RT5645_PWR_VOL:
case RT5645_PRIV_INDEX:
case RT5645_PRIV_DATA:
case RT5645_I2S1_SDP:
case RT5645_I2S2_SDP:
case RT5645_ADDA_CLK1:
case RT5645_ADDA_CLK2:
case RT5645_DMIC_CTRL1:
case RT5645_DMIC_CTRL2:
case RT5645_TDM_CTRL_1:
case RT5645_TDM_CTRL_2:
case RT5645_TDM_CTRL_3:
case RT5650_TDM_CTRL_4:
case RT5645_GLB_CLK:
case RT5645_PLL_CTRL1:
case RT5645_PLL_CTRL2:
case RT5645_ASRC_1:
case RT5645_ASRC_2:
case RT5645_ASRC_3:
case RT5645_ASRC_4:
case RT5645_DEPOP_M1:
case RT5645_DEPOP_M2:
case RT5645_DEPOP_M3:
case RT5645_CHARGE_PUMP:
case RT5645_MICBIAS:
case RT5645_A_JD_CTRL1:
case RT5645_VAD_CTRL4:
case RT5645_CLSD_OUT_CTRL:
case RT5645_ADC_EQ_CTRL1:
case RT5645_ADC_EQ_CTRL2:
case RT5645_EQ_CTRL1:
case RT5645_EQ_CTRL2:
case RT5645_ALC_CTRL_1:
case RT5645_ALC_CTRL_2:
case RT5645_ALC_CTRL_3:
case RT5645_ALC_CTRL_4:
case RT5645_ALC_CTRL_5:
case RT5645_JD_CTRL:
case RT5645_IRQ_CTRL1:
case RT5645_IRQ_CTRL2:
case RT5645_IRQ_CTRL3:
case RT5645_INT_IRQ_ST:
case RT5645_GPIO_CTRL1:
case RT5645_GPIO_CTRL2:
case RT5645_GPIO_CTRL3:
case RT5645_BASS_BACK:
case RT5645_MP3_PLUS1:
case RT5645_MP3_PLUS2:
case RT5645_ADJ_HPF1:
case RT5645_ADJ_HPF2:
case RT5645_HP_CALIB_AMP_DET:
case RT5645_SV_ZCD1:
case RT5645_SV_ZCD2:
case RT5645_IL_CMD:
case RT5645_IL_CMD2:
case RT5645_IL_CMD3:
case RT5650_4BTN_IL_CMD1:
case RT5650_4BTN_IL_CMD2:
case RT5645_DRC1_HL_CTRL1:
case RT5645_DRC2_HL_CTRL1:
case RT5645_ADC_MONO_HP_CTRL1:
case RT5645_ADC_MONO_HP_CTRL2:
case RT5645_DRC2_CTRL1:
case RT5645_DRC2_CTRL2:
case RT5645_DRC2_CTRL3:
case RT5645_DRC2_CTRL4:
case RT5645_DRC2_CTRL5:
case RT5645_JD_CTRL3:
case RT5645_JD_CTRL4:
case RT5645_GEN_CTRL1:
case RT5645_GEN_CTRL2:
case RT5645_GEN_CTRL3:
case RT5645_VENDOR_ID:
case RT5645_VENDOR_ID1:
case RT5645_VENDOR_ID2:
return true;
default:
return false;
}
}
static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
static const DECLARE_TLV_DB_RANGE(bst_tlv,
0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
);
/* {-6, -4.5, -3, -1.5, 0, 0.82, 1.58, 2.28} dB */
static const DECLARE_TLV_DB_RANGE(spk_clsd_tlv,
0, 4, TLV_DB_SCALE_ITEM(-600, 150, 0),
5, 5, TLV_DB_SCALE_ITEM(82, 0, 0),
6, 6, TLV_DB_SCALE_ITEM(158, 0, 0),
7, 7, TLV_DB_SCALE_ITEM(228, 0, 0)
);
static int rt5645_hweq_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
uinfo->count = RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s);
return 0;
}
static int rt5645_hweq_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
struct rt5645_eq_param_s_be16 *eq_param =
(struct rt5645_eq_param_s_be16 *)ucontrol->value.bytes.data;
int i;
for (i = 0; i < RT5645_HWEQ_NUM; i++) {
eq_param[i].reg = cpu_to_be16(rt5645->eq_param[i].reg);
eq_param[i].val = cpu_to_be16(rt5645->eq_param[i].val);
}
return 0;
}
static bool rt5645_validate_hweq(unsigned short reg)
{
if ((reg >= 0x1a4 && reg <= 0x1cd) || (reg >= 0x1e5 && reg <= 0x1f8) ||
(reg == RT5645_EQ_CTRL2))
return true;
return false;
}
static int rt5645_hweq_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
struct rt5645_eq_param_s_be16 *eq_param =
(struct rt5645_eq_param_s_be16 *)ucontrol->value.bytes.data;
int i;
for (i = 0; i < RT5645_HWEQ_NUM; i++) {
rt5645->eq_param[i].reg = be16_to_cpu(eq_param[i].reg);
rt5645->eq_param[i].val = be16_to_cpu(eq_param[i].val);
}
/* The final setting of the table should be RT5645_EQ_CTRL2 */
for (i = RT5645_HWEQ_NUM - 1; i >= 0; i--) {
if (rt5645->eq_param[i].reg == 0)
continue;
else if (rt5645->eq_param[i].reg != RT5645_EQ_CTRL2)
return 0;
else
break;
}
for (i = 0; i < RT5645_HWEQ_NUM; i++) {
if (!rt5645_validate_hweq(rt5645->eq_param[i].reg) &&
rt5645->eq_param[i].reg != 0)
return 0;
else if (rt5645->eq_param[i].reg == 0)
break;
}
return 0;
}
#define RT5645_HWEQ(xname) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
.info = rt5645_hweq_info, \
.get = rt5645_hweq_get, \
.put = rt5645_hweq_put \
}
static int rt5645_spk_put_volsw(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
int ret;
regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PU);
ret = snd_soc_put_volsw(kcontrol, ucontrol);
mod_delayed_work(system_power_efficient_wq, &rt5645->rcclock_work,
msecs_to_jiffies(200));
return ret;
}
static const char * const rt5645_dac1_vol_ctrl_mode_text[] = {
"immediately", "zero crossing", "soft ramp"
};
static SOC_ENUM_SINGLE_DECL(
rt5645_dac1_vol_ctrl_mode, RT5645_PR_BASE,
RT5645_DA1_ZDET_SFT, rt5645_dac1_vol_ctrl_mode_text);
static const struct snd_kcontrol_new rt5645_snd_controls[] = {
/* Speaker Output Volume */
SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL,
RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
SOC_DOUBLE_EXT_TLV("Speaker Playback Volume", RT5645_SPK_VOL,
RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, snd_soc_get_volsw,
rt5645_spk_put_volsw, out_vol_tlv),
/* ClassD modulator Speaker Gain Ratio */
SOC_SINGLE_TLV("Speaker ClassD Playback Volume", RT5645_SPO_CLSD_RATIO,
RT5645_SPK_G_CLSD_SFT, 7, 0, spk_clsd_tlv),
/* Headphone Output Volume */
SOC_DOUBLE("Headphone Channel Switch", RT5645_HP_VOL,
RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
SOC_DOUBLE_TLV("Headphone Playback Volume", RT5645_HP_VOL,
RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
/* OUTPUT Control */
SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1,
RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1,
RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
SOC_DOUBLE_TLV("OUT Playback Volume", RT5645_LOUT1,
RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
/* DAC Digital Volume */
SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL,
RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1),
SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL,
RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL,
RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
/* IN1/IN2 Control */
SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1,
RT5645_BST_SFT1, 12, 0, bst_tlv),
SOC_SINGLE_TLV("IN2 Boost", RT5645_IN2_CTRL,
RT5645_BST_SFT2, 8, 0, bst_tlv),
/* INL/INR Volume Control */
SOC_DOUBLE_TLV("IN Capture Volume", RT5645_INL1_INR1_VOL,
RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv),
/* ADC Digital Volume Control */
SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL,
RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL,
RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL,
RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL,
RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
/* ADC Boost Volume Control */
SOC_DOUBLE_TLV("ADC Boost Capture Volume", RT5645_ADC_BST_VOL1,
RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0,
adc_bst_tlv),
SOC_DOUBLE_TLV("Mono ADC Boost Capture Volume", RT5645_ADC_BST_VOL2,
RT5645_MONO_ADC_L_BST_SFT, RT5645_MONO_ADC_R_BST_SFT, 3, 0,
adc_bst_tlv),
/* I2S2 function select */
SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT,
1, 1),
RT5645_HWEQ("Speaker HWEQ"),
/* Digital Soft Volume Control */
SOC_ENUM("DAC1 Digital Volume Control Func", rt5645_dac1_vol_ctrl_mode),
};
/**
* set_dmic_clk - Set parameter of dmic.
*
* @w: DAPM widget.
* @kcontrol: The kcontrol of this widget.
* @event: Event id.
*
*/
static int set_dmic_clk(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
int idx, rate;
rate = rt5645->sysclk / rl6231_get_pre_div(rt5645->regmap,
RT5645_ADDA_CLK1, RT5645_I2S_PD1_SFT);
idx = rl6231_calc_dmic_clk(rate);
if (idx < 0)
dev_err(component->dev, "Failed to set DMIC clock\n");
else
snd_soc_component_update_bits(component, RT5645_DMIC_CTRL1,
RT5645_DMIC_CLK_MASK, idx << RT5645_DMIC_CLK_SFT);
return idx;
}
static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
unsigned int val;
val = snd_soc_component_read(component, RT5645_GLB_CLK);
val &= RT5645_SCLK_SRC_MASK;
if (val == RT5645_SCLK_SRC_PLL1)
return 1;
else
return 0;
}
static int is_using_asrc(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
unsigned int reg, shift, val;
switch (source->shift) {
case 0:
reg = RT5645_ASRC_3;
shift = 0;
break;
case 1:
reg = RT5645_ASRC_3;
shift = 4;
break;
case 3:
reg = RT5645_ASRC_2;
shift = 0;
break;
case 8:
reg = RT5645_ASRC_2;
shift = 4;
break;
case 9:
reg = RT5645_ASRC_2;
shift = 8;
break;
case 10:
reg = RT5645_ASRC_2;
shift = 12;
break;
default:
return 0;
}
val = (snd_soc_component_read(component, reg) >> shift) & 0xf;
switch (val) {
case 1:
case 2:
case 3:
case 4:
return 1;
default:
return 0;
}
}
static int rt5645_enable_hweq(struct snd_soc_component *component)
{
struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
int i;
for (i = 0; i < RT5645_HWEQ_NUM; i++) {
if (rt5645_validate_hweq(rt5645->eq_param[i].reg))
regmap_write(rt5645->regmap, rt5645->eq_param[i].reg,
rt5645->eq_param[i].val);
else
break;
}
return 0;
}
/**
* rt5645_sel_asrc_clk_src - select ASRC clock source for a set of filters
* @component: SoC audio component device.
* @filter_mask: mask of filters.
* @clk_src: clock source
*
* The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5645 can
* only support standard 32fs or 64fs i2s format, ASRC should be enabled to
* support special i2s clock format such as Intel's 100fs(100 * sampling rate).
* ASRC function will track i2s clock and generate a corresponding system clock
* for codec. This function provides an API to select the clock source for a
* set of filters specified by the mask. And the codec driver will turn on ASRC
* for these filters if ASRC is selected as their clock source.
*/
int rt5645_sel_asrc_clk_src(struct snd_soc_component *component,
unsigned int filter_mask, unsigned int clk_src)
{
unsigned int asrc2_mask = 0;
unsigned int asrc2_value = 0;
unsigned int asrc3_mask = 0;
unsigned int asrc3_value = 0;
switch (clk_src) {
case RT5645_CLK_SEL_SYS:
case RT5645_CLK_SEL_I2S1_ASRC:
case RT5645_CLK_SEL_I2S2_ASRC:
case RT5645_CLK_SEL_SYS2:
break;
default:
return -EINVAL;
}
if (filter_mask & RT5645_DA_STEREO_FILTER) {
asrc2_mask |= RT5645_DA_STO_CLK_SEL_MASK;
asrc2_value = (asrc2_value & ~RT5645_DA_STO_CLK_SEL_MASK)
| (clk_src << RT5645_DA_STO_CLK_SEL_SFT);
}
if (filter_mask & RT5645_DA_MONO_L_FILTER) {
asrc2_mask |= RT5645_DA_MONOL_CLK_SEL_MASK;
asrc2_value = (asrc2_value & ~RT5645_DA_MONOL_CLK_SEL_MASK)
| (clk_src << RT5645_DA_MONOL_CLK_SEL_SFT);
}
if (filter_mask & RT5645_DA_MONO_R_FILTER) {
asrc2_mask |= RT5645_DA_MONOR_CLK_SEL_MASK;
asrc2_value = (asrc2_value & ~RT5645_DA_MONOR_CLK_SEL_MASK)
| (clk_src << RT5645_DA_MONOR_CLK_SEL_SFT);
}
if (filter_mask & RT5645_AD_STEREO_FILTER) {
asrc2_mask |= RT5645_AD_STO1_CLK_SEL_MASK;
asrc2_value = (asrc2_value & ~RT5645_AD_STO1_CLK_SEL_MASK)
| (clk_src << RT5645_AD_STO1_CLK_SEL_SFT);
}
if (filter_mask & RT5645_AD_MONO_L_FILTER) {
asrc3_mask |= RT5645_AD_MONOL_CLK_SEL_MASK;
asrc3_value = (asrc3_value & ~RT5645_AD_MONOL_CLK_SEL_MASK)
| (clk_src << RT5645_AD_MONOL_CLK_SEL_SFT);
}
if (filter_mask & RT5645_AD_MONO_R_FILTER) {
asrc3_mask |= RT5645_AD_MONOR_CLK_SEL_MASK;
asrc3_value = (asrc3_value & ~RT5645_AD_MONOR_CLK_SEL_MASK)
| (clk_src << RT5645_AD_MONOR_CLK_SEL_SFT);
}
if (asrc2_mask)
snd_soc_component_update_bits(component, RT5645_ASRC_2,
asrc2_mask, asrc2_value);
if (asrc3_mask)
snd_soc_component_update_bits(component, RT5645_ASRC_3,
asrc3_mask, asrc3_value);
return 0;
}
EXPORT_SYMBOL_GPL(rt5645_sel_asrc_clk_src);
/* Digital Mixer */
static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
RT5645_M_ADC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
RT5645_M_ADC_L2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
RT5645_M_ADC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
RT5645_M_ADC_R2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
RT5645_M_MONO_ADC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
RT5645_M_MONO_ADC_L2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
RT5645_M_MONO_ADC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
RT5645_M_MONO_ADC_R2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5645_dac_l_mix[] = {
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
RT5645_M_ADCMIX_L_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER,
RT5645_M_DAC1_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5645_dac_r_mix[] = {
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
RT5645_M_ADCMIX_R_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER,
RT5645_M_DAC1_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
RT5645_M_DAC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER,
RT5645_M_DAC_L2_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
RT5645_M_DAC_R1_STO_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = {
SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
RT5645_M_DAC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER,
RT5645_M_DAC_R2_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
RT5645_M_DAC_L1_STO_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_MONO_DAC_MIXER,
RT5645_M_DAC_L1_MONO_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
RT5645_M_DAC_L2_MONO_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
RT5645_M_DAC_R2_MONO_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = {
SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER,
RT5645_M_DAC_R1_MONO_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
RT5645_M_DAC_R2_MONO_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
RT5645_M_DAC_L2_MONO_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5645_dig_l_mix[] = {
SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5645_DIG_MIXER,
RT5645_M_STO_L_DAC_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
RT5645_M_DAC_L2_DAC_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
RT5645_M_DAC_R2_DAC_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5645_dig_r_mix[] = {
SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5645_DIG_MIXER,
RT5645_M_STO_R_DAC_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
RT5645_M_DAC_R2_DAC_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
RT5645_M_DAC_L2_DAC_R_SFT, 1, 1),
};
/* Analog Input Mixer */
static const struct snd_kcontrol_new rt5645_rec_l_mix[] = {
SOC_DAPM_SINGLE("HPOL Switch", RT5645_REC_L2_MIXER,
RT5645_M_HP_L_RM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("INL Switch", RT5645_REC_L2_MIXER,
RT5645_M_IN_L_RM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_L2_MIXER,
RT5645_M_BST2_RM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_L2_MIXER,
RT5645_M_BST1_RM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("OUT MIXL Switch", RT5645_REC_L2_MIXER,
RT5645_M_OM_L_RM_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5645_rec_r_mix[] = {
SOC_DAPM_SINGLE("HPOR Switch", RT5645_REC_R2_MIXER,
RT5645_M_HP_R_RM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("INR Switch", RT5645_REC_R2_MIXER,
RT5645_M_IN_R_RM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_R2_MIXER,
RT5645_M_BST2_RM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_R2_MIXER,
RT5645_M_BST1_RM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("OUT MIXR Switch", RT5645_REC_R2_MIXER,
RT5645_M_OM_R_RM_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5645_spk_l_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPK_L_MIXER,
RT5645_M_DAC_L1_SM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER,
RT5645_M_DAC_L2_SM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("INL Switch", RT5645_SPK_L_MIXER,
RT5645_M_IN_L_SM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5645_SPK_L_MIXER,
RT5645_M_BST1_L_SM_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5645_spk_r_mix[] = {
SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER,
RT5645_M_DAC_R1_SM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER,
RT5645_M_DAC_R2_SM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("INR Switch", RT5645_SPK_R_MIXER,
RT5645_M_IN_R_SM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5645_SPK_R_MIXER,
RT5645_M_BST2_R_SM_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5645_out_l_mix[] = {
SOC_DAPM_SINGLE("BST1 Switch", RT5645_OUT_L1_MIXER,
RT5645_M_BST1_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("INL Switch", RT5645_OUT_L1_MIXER,
RT5645_M_IN_L_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER,
RT5645_M_DAC_L2_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_OUT_L1_MIXER,
RT5645_M_DAC_L1_OM_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5645_out_r_mix[] = {
SOC_DAPM_SINGLE("BST2 Switch", RT5645_OUT_R1_MIXER,
RT5645_M_BST2_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("INR Switch", RT5645_OUT_R1_MIXER,
RT5645_M_IN_R_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER,
RT5645_M_DAC_R2_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER,
RT5645_M_DAC_R1_OM_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5645_spo_l_mix[] = {
SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
RT5645_M_DAC_R1_SPM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPO_MIXER,
RT5645_M_DAC_L1_SPM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
RT5645_M_SV_R_SPM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("SPKVOL L Switch", RT5645_SPO_MIXER,
RT5645_M_SV_L_SPM_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5645_spo_r_mix[] = {
SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
RT5645_M_DAC_R1_SPM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
RT5645_M_SV_R_SPM_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5645_hpo_mix[] = {
SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPO_MIXER,
RT5645_M_DAC1_HM_SFT, 1, 1),
SOC_DAPM_SINGLE("HPVOL Switch", RT5645_HPO_MIXER,
RT5645_M_HPVOL_HM_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = {
SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXL_CTRL,
RT5645_M_DAC1_HV_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXL_CTRL,
RT5645_M_DAC2_HV_SFT, 1, 1),
SOC_DAPM_SINGLE("INL Switch", RT5645_HPOMIXL_CTRL,
RT5645_M_IN_HV_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5645_HPOMIXL_CTRL,
RT5645_M_BST1_HV_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = {
SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXR_CTRL,
RT5645_M_DAC1_HV_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXR_CTRL,
RT5645_M_DAC2_HV_SFT, 1, 1),
SOC_DAPM_SINGLE("INR Switch", RT5645_HPOMIXR_CTRL,
RT5645_M_IN_HV_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5645_HPOMIXR_CTRL,
RT5645_M_BST2_HV_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5645_lout_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_LOUT_MIXER,
RT5645_M_DAC_L1_LM_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER,
RT5645_M_DAC_R1_LM_SFT, 1, 1),
SOC_DAPM_SINGLE("OUTMIX L Switch", RT5645_LOUT_MIXER,
RT5645_M_OV_L_LM_SFT, 1, 1),
SOC_DAPM_SINGLE("OUTMIX R Switch", RT5645_LOUT_MIXER,
RT5645_M_OV_R_LM_SFT, 1, 1),
};
/*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */
static const char * const rt5645_dac1_src[] = {
"IF1 DAC", "IF2 DAC", "IF3 DAC"
};
static SOC_ENUM_SINGLE_DECL(
rt5645_dac1l_enum, RT5645_AD_DA_MIXER,
RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src);
static const struct snd_kcontrol_new rt5645_dac1l_mux =
SOC_DAPM_ENUM("DAC1 L source", rt5645_dac1l_enum);
static SOC_ENUM_SINGLE_DECL(
rt5645_dac1r_enum, RT5645_AD_DA_MIXER,
RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src);
static const struct snd_kcontrol_new rt5645_dac1r_mux =
SOC_DAPM_ENUM("DAC1 R source", rt5645_dac1r_enum);
/*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */
static const char * const rt5645_dac12_src[] = {
"IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "VAD_ADC"
};
static SOC_ENUM_SINGLE_DECL(
rt5645_dac2l_enum, RT5645_DAC_CTRL,
RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src);
static const struct snd_kcontrol_new rt5645_dac_l2_mux =
SOC_DAPM_ENUM("DAC2 L source", rt5645_dac2l_enum);
static const char * const rt5645_dacr2_src[] = {
"IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "Haptic"
};
static SOC_ENUM_SINGLE_DECL(
rt5645_dac2r_enum, RT5645_DAC_CTRL,
RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src);
static const struct snd_kcontrol_new rt5645_dac_r2_mux =
SOC_DAPM_ENUM("DAC2 R source", rt5645_dac2r_enum);
/* Stereo1 ADC source */
/* MX-27 [12] */
static const char * const rt5645_stereo_adc1_src[] = {
"DAC MIX", "ADC"
};
static SOC_ENUM_SINGLE_DECL(
rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER,
RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src);
static const struct snd_kcontrol_new rt5645_sto_adc1_mux =
SOC_DAPM_ENUM("Stereo1 ADC1 Mux", rt5645_stereo1_adc1_enum);
/* MX-27 [11] */
static const char * const rt5645_stereo_adc2_src[] = {
"DAC MIX", "DMIC"
};
static SOC_ENUM_SINGLE_DECL(
rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER,
RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src);
static const struct snd_kcontrol_new rt5645_sto_adc2_mux =
SOC_DAPM_ENUM("Stereo1 ADC2 Mux", rt5645_stereo1_adc2_enum);
/* MX-27 [8] */
static const char * const rt5645_stereo_dmic_src[] = {
"DMIC1", "DMIC2"
};
static SOC_ENUM_SINGLE_DECL(
rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER,
RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src);
static const struct snd_kcontrol_new rt5645_sto1_dmic_mux =
SOC_DAPM_ENUM("Stereo1 DMIC source", rt5645_stereo1_dmic_enum);
/* Mono ADC source */
/* MX-28 [12] */
static const char * const rt5645_mono_adc_l1_src[] = {
"Mono DAC MIXL", "ADC"
};
static SOC_ENUM_SINGLE_DECL(
rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER,
RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src);
static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux =
SOC_DAPM_ENUM("Mono ADC1 left source", rt5645_mono_adc_l1_enum);
/* MX-28 [11] */
static const char * const rt5645_mono_adc_l2_src[] = {
"Mono DAC MIXL", "DMIC"
};
static SOC_ENUM_SINGLE_DECL(
rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER,
RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src);
static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux =
SOC_DAPM_ENUM("Mono ADC2 left source", rt5645_mono_adc_l2_enum);
/* MX-28 [8] */
static const char * const rt5645_mono_dmic_src[] = {
"DMIC1", "DMIC2"
};
static SOC_ENUM_SINGLE_DECL(
rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER,
RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src);
static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux =
SOC_DAPM_ENUM("Mono DMIC left source", rt5645_mono_dmic_l_enum);
/* MX-28 [1:0] */
static SOC_ENUM_SINGLE_DECL(
rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER,
RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src);
static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux =
SOC_DAPM_ENUM("Mono DMIC Right source", rt5645_mono_dmic_r_enum);
/* MX-28 [4] */
static const char * const rt5645_mono_adc_r1_src[] = {
"Mono DAC MIXR", "ADC"
};
static SOC_ENUM_SINGLE_DECL(
rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER,
RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src);
static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux =
SOC_DAPM_ENUM("Mono ADC1 right source", rt5645_mono_adc_r1_enum);
/* MX-28 [3] */
static const char * const rt5645_mono_adc_r2_src[] = {
"Mono DAC MIXR", "DMIC"
};
static SOC_ENUM_SINGLE_DECL(
rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER,
RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src);
static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux =
SOC_DAPM_ENUM("Mono ADC2 right source", rt5645_mono_adc_r2_enum);
/* MX-77 [9:8] */
static const char * const rt5645_if1_adc_in_src[] = {
"IF_ADC1/IF_ADC2/VAD_ADC", "IF_ADC2/IF_ADC1/VAD_ADC",
"VAD_ADC/IF_ADC1/IF_ADC2", "VAD_ADC/IF_ADC2/IF_ADC1"
};
static SOC_ENUM_SINGLE_DECL(
rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1,
RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src);
static const struct snd_kcontrol_new rt5645_if1_adc_in_mux =
SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum);
/* MX-78 [4:0] */
static const char * const rt5650_if1_adc_in_src[] = {
"IF_ADC1/IF_ADC2/DAC_REF/Null",
"IF_ADC1/IF_ADC2/Null/DAC_REF",
"IF_ADC1/DAC_REF/IF_ADC2/Null",
"IF_ADC1/DAC_REF/Null/IF_ADC2",
"IF_ADC1/Null/DAC_REF/IF_ADC2",
"IF_ADC1/Null/IF_ADC2/DAC_REF",
"IF_ADC2/IF_ADC1/DAC_REF/Null",
"IF_ADC2/IF_ADC1/Null/DAC_REF",
"IF_ADC2/DAC_REF/IF_ADC1/Null",
"IF_ADC2/DAC_REF/Null/IF_ADC1",
"IF_ADC2/Null/DAC_REF/IF_ADC1",
"IF_ADC2/Null/IF_ADC1/DAC_REF",
"DAC_REF/IF_ADC1/IF_ADC2/Null",
"DAC_REF/IF_ADC1/Null/IF_ADC2",
"DAC_REF/IF_ADC2/IF_ADC1/Null",
"DAC_REF/IF_ADC2/Null/IF_ADC1",
"DAC_REF/Null/IF_ADC1/IF_ADC2",
"DAC_REF/Null/IF_ADC2/IF_ADC1",
"Null/IF_ADC1/IF_ADC2/DAC_REF",
"Null/IF_ADC1/DAC_REF/IF_ADC2",
"Null/IF_ADC2/IF_ADC1/DAC_REF",
"Null/IF_ADC2/DAC_REF/IF_ADC1",
"Null/DAC_REF/IF_ADC1/IF_ADC2",
"Null/DAC_REF/IF_ADC2/IF_ADC1",
};
static SOC_ENUM_SINGLE_DECL(
rt5650_if1_adc_in_enum, RT5645_TDM_CTRL_2,
0, rt5650_if1_adc_in_src);
static const struct snd_kcontrol_new rt5650_if1_adc_in_mux =
SOC_DAPM_ENUM("IF1 ADC IN source", rt5650_if1_adc_in_enum);
/* MX-78 [15:14][13:12][11:10] */
static const char * const rt5645_tdm_adc_swap_select[] = {
"L/R", "R/L", "L/L", "R/R"
};
static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot0_1_enum,
RT5645_TDM_CTRL_2, 14, rt5645_tdm_adc_swap_select);
static const struct snd_kcontrol_new rt5650_if1_adc1_in_mux =
SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5650_tdm_adc_slot0_1_enum);
static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot2_3_enum,
RT5645_TDM_CTRL_2, 12, rt5645_tdm_adc_swap_select);
static const struct snd_kcontrol_new rt5650_if1_adc2_in_mux =
SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5650_tdm_adc_slot2_3_enum);
static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot4_5_enum,
RT5645_TDM_CTRL_2, 10, rt5645_tdm_adc_swap_select);
static const struct snd_kcontrol_new rt5650_if1_adc3_in_mux =
SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5650_tdm_adc_slot4_5_enum);
/* MX-77 [7:6][5:4][3:2] */
static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum,
RT5645_TDM_CTRL_1, 6, rt5645_tdm_adc_swap_select);
static const struct snd_kcontrol_new rt5645_if1_adc1_in_mux =
SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5645_tdm_adc_slot0_1_enum);
static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum,
RT5645_TDM_CTRL_1, 4, rt5645_tdm_adc_swap_select);
static const struct snd_kcontrol_new rt5645_if1_adc2_in_mux =
SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5645_tdm_adc_slot2_3_enum);
static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum,
RT5645_TDM_CTRL_1, 2, rt5645_tdm_adc_swap_select);
static const struct snd_kcontrol_new rt5645_if1_adc3_in_mux =
SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5645_tdm_adc_slot4_5_enum);
/* MX-79 [14:12][10:8][6:4][2:0] */
static const char * const rt5645_tdm_dac_swap_select[] = {
"Slot0", "Slot1", "Slot2", "Slot3"
};
static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac0_enum,
RT5645_TDM_CTRL_3, 12, rt5645_tdm_dac_swap_select);
static const struct snd_kcontrol_new rt5645_if1_dac0_tdm_sel_mux =
SOC_DAPM_ENUM("IF1 DAC0 source", rt5645_tdm_dac0_enum);
static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac1_enum,
RT5645_TDM_CTRL_3, 8, rt5645_tdm_dac_swap_select);
static const struct snd_kcontrol_new rt5645_if1_dac1_tdm_sel_mux =
SOC_DAPM_ENUM("IF1 DAC1 source", rt5645_tdm_dac1_enum);
static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac2_enum,
RT5645_TDM_CTRL_3, 4, rt5645_tdm_dac_swap_select);
static const struct snd_kcontrol_new rt5645_if1_dac2_tdm_sel_mux =
SOC_DAPM_ENUM("IF1 DAC2 source", rt5645_tdm_dac2_enum);
static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac3_enum,
RT5645_TDM_CTRL_3, 0, rt5645_tdm_dac_swap_select);
static const struct snd_kcontrol_new rt5645_if1_dac3_tdm_sel_mux =
SOC_DAPM_ENUM("IF1 DAC3 source", rt5645_tdm_dac3_enum);
/* MX-7a [14:12][10:8][6:4][2:0] */
static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac0_enum,
RT5650_TDM_CTRL_4, 12, rt5645_tdm_dac_swap_select);
static const struct snd_kcontrol_new rt5650_if1_dac0_tdm_sel_mux =
SOC_DAPM_ENUM("IF1 DAC0 source", rt5650_tdm_dac0_enum);
static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac1_enum,
RT5650_TDM_CTRL_4, 8, rt5645_tdm_dac_swap_select);
static const struct snd_kcontrol_new rt5650_if1_dac1_tdm_sel_mux =
SOC_DAPM_ENUM("IF1 DAC1 source", rt5650_tdm_dac1_enum);
static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac2_enum,
RT5650_TDM_CTRL_4, 4, rt5645_tdm_dac_swap_select);
static const struct snd_kcontrol_new rt5650_if1_dac2_tdm_sel_mux =
SOC_DAPM_ENUM("IF1 DAC2 source", rt5650_tdm_dac2_enum);
static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac3_enum,
RT5650_TDM_CTRL_4, 0, rt5645_tdm_dac_swap_select);
static const struct snd_kcontrol_new rt5650_if1_dac3_tdm_sel_mux =
SOC_DAPM_ENUM("IF1 DAC3 source", rt5650_tdm_dac3_enum);
/* MX-2d [3] [2] */
static const char * const rt5650_a_dac1_src[] = {
"DAC1", "Stereo DAC Mixer"
};
static SOC_ENUM_SINGLE_DECL(
rt5650_a_dac1_l_enum, RT5650_A_DAC_SOUR,
RT5650_A_DAC1_L_IN_SFT, rt5650_a_dac1_src);
static const struct snd_kcontrol_new rt5650_a_dac1_l_mux =
SOC_DAPM_ENUM("A DAC1 L source", rt5650_a_dac1_l_enum);
static SOC_ENUM_SINGLE_DECL(
rt5650_a_dac1_r_enum, RT5650_A_DAC_SOUR,
RT5650_A_DAC1_R_IN_SFT, rt5650_a_dac1_src);
static const struct snd_kcontrol_new rt5650_a_dac1_r_mux =
SOC_DAPM_ENUM("A DAC1 R source", rt5650_a_dac1_r_enum);
/* MX-2d [1] [0] */
static const char * const rt5650_a_dac2_src[] = {
"Stereo DAC Mixer", "Mono DAC Mixer"
};
static SOC_ENUM_SINGLE_DECL(
rt5650_a_dac2_l_enum, RT5650_A_DAC_SOUR,
RT5650_A_DAC2_L_IN_SFT, rt5650_a_dac2_src);
static const struct snd_kcontrol_new rt5650_a_dac2_l_mux =
SOC_DAPM_ENUM("A DAC2 L source", rt5650_a_dac2_l_enum);
static SOC_ENUM_SINGLE_DECL(
rt5650_a_dac2_r_enum, RT5650_A_DAC_SOUR,
RT5650_A_DAC2_R_IN_SFT, rt5650_a_dac2_src);
static const struct snd_kcontrol_new rt5650_a_dac2_r_mux =
SOC_DAPM_ENUM("A DAC2 R source", rt5650_a_dac2_r_enum);
/* MX-2F [13:12] */
static const char * const rt5645_if2_adc_in_src[] = {
"IF_ADC1", "IF_ADC2", "VAD_ADC"
};
static SOC_ENUM_SINGLE_DECL(
rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA,
RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src);
static const struct snd_kcontrol_new rt5645_if2_adc_in_mux =
SOC_DAPM_ENUM("IF2 ADC IN source", rt5645_if2_adc_in_enum);
/* MX-31 [15] [13] [11] [9] */
static const char * const rt5645_pdm_src[] = {
"Mono DAC", "Stereo DAC"
};
static SOC_ENUM_SINGLE_DECL(
rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL,
RT5645_PDM1_L_SFT, rt5645_pdm_src);
static const struct snd_kcontrol_new rt5645_pdm1_l_mux =
SOC_DAPM_ENUM("PDM1 L source", rt5645_pdm1_l_enum);
static SOC_ENUM_SINGLE_DECL(
rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL,
RT5645_PDM1_R_SFT, rt5645_pdm_src);
static const struct snd_kcontrol_new rt5645_pdm1_r_mux =
SOC_DAPM_ENUM("PDM1 R source", rt5645_pdm1_r_enum);
/* MX-9D [9:8] */
static const char * const rt5645_vad_adc_src[] = {
"Sto1 ADC L", "Mono ADC L", "Mono ADC R"
};
static SOC_ENUM_SINGLE_DECL(
rt5645_vad_adc_enum, RT5645_VAD_CTRL4,
RT5645_VAD_SEL_SFT, rt5645_vad_adc_src);
static const struct snd_kcontrol_new rt5645_vad_adc_mux =
SOC_DAPM_ENUM("VAD ADC source", rt5645_vad_adc_enum);
static const struct snd_kcontrol_new spk_l_vol_control =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
RT5645_L_MUTE_SFT, 1, 1);
static const struct snd_kcontrol_new spk_r_vol_control =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
RT5645_R_MUTE_SFT, 1, 1);
static const struct snd_kcontrol_new hp_l_vol_control =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
RT5645_L_MUTE_SFT, 1, 1);
static const struct snd_kcontrol_new hp_r_vol_control =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
RT5645_R_MUTE_SFT, 1, 1);
static const struct snd_kcontrol_new pdm1_l_vol_control =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
RT5645_M_PDM1_L, 1, 1);
static const struct snd_kcontrol_new pdm1_r_vol_control =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
RT5645_M_PDM1_R, 1, 1);
static void hp_amp_power(struct snd_soc_component *component, int on)
{
static int hp_amp_power_count;
struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
int i, val;
if (on) {
if (hp_amp_power_count <= 0) {
if (rt5645->codec_type == CODEC_TYPE_RT5650) {
snd_soc_component_write(component, RT5645_DEPOP_M2, 0x3100);
snd_soc_component_write(component, RT5645_CHARGE_PUMP,
0x0e06);
snd_soc_component_write(component, RT5645_DEPOP_M1, 0x000d);
regmap_write(rt5645->regmap, RT5645_PR_BASE +
RT5645_HP_DCC_INT1, 0x9f01);
for (i = 0; i < 20; i++) {
usleep_range(1000, 1500);
regmap_read(rt5645->regmap, RT5645_PR_BASE +
RT5645_HP_DCC_INT1, &val);
if (!(val & 0x8000))
break;
}
snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
RT5645_HP_CO_MASK, RT5645_HP_CO_EN);
regmap_write(rt5645->regmap, RT5645_PR_BASE +
0x3e, 0x7400);
snd_soc_component_write(component, RT5645_DEPOP_M3, 0x0737);
regmap_write(rt5645->regmap, RT5645_PR_BASE +
RT5645_MAMP_INT_REG2, 0xfc00);
snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140);
snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
RT5645_PWR_HP_L | RT5645_PWR_HP_R,
RT5645_PWR_HP_L | RT5645_PWR_HP_R);
msleep(90);
} else {
/* depop parameters */
snd_soc_component_update_bits(component, RT5645_DEPOP_M2,
RT5645_DEPOP_MASK, RT5645_DEPOP_MAN);
snd_soc_component_write(component, RT5645_DEPOP_M1, 0x000d);
regmap_write(rt5645->regmap, RT5645_PR_BASE +
RT5645_HP_DCC_INT1, 0x9f01);
mdelay(150);
/* headphone amp power on */
snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
RT5645_PWR_FV1 | RT5645_PWR_FV2, 0);
snd_soc_component_update_bits(component, RT5645_PWR_VOL,
RT5645_PWR_HV_L | RT5645_PWR_HV_R,
RT5645_PWR_HV_L | RT5645_PWR_HV_R);
snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
RT5645_PWR_HP_L | RT5645_PWR_HP_R |
RT5645_PWR_HA,
RT5645_PWR_HP_L | RT5645_PWR_HP_R |
RT5645_PWR_HA);
mdelay(5);
snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
RT5645_PWR_FV1 | RT5645_PWR_FV2,
RT5645_PWR_FV1 | RT5645_PWR_FV2);
snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
RT5645_HP_CO_MASK | RT5645_HP_SG_MASK,
RT5645_HP_CO_EN | RT5645_HP_SG_EN);
regmap_write(rt5645->regmap, RT5645_PR_BASE +
0x14, 0x1aaa);
regmap_write(rt5645->regmap, RT5645_PR_BASE +
0x24, 0x0430);
}
}
hp_amp_power_count++;
} else {
hp_amp_power_count--;
if (hp_amp_power_count <= 0) {
if (rt5645->codec_type == CODEC_TYPE_RT5650) {
regmap_write(rt5645->regmap, RT5645_PR_BASE +
0x3e, 0x7400);
snd_soc_component_write(component, RT5645_DEPOP_M3, 0x0737);
regmap_write(rt5645->regmap, RT5645_PR_BASE +
RT5645_MAMP_INT_REG2, 0xfc00);
snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140);
msleep(100);
snd_soc_component_write(component, RT5645_DEPOP_M1, 0x0001);
snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
RT5645_PWR_HP_L | RT5645_PWR_HP_R, 0);
} else {
snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
RT5645_HP_SG_MASK |
RT5645_HP_L_SMT_MASK |
RT5645_HP_R_SMT_MASK,
RT5645_HP_SG_DIS |
RT5645_HP_L_SMT_DIS |
RT5645_HP_R_SMT_DIS);
/* headphone amp power down */
snd_soc_component_write(component, RT5645_DEPOP_M1, 0x0000);
snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
RT5645_PWR_HP_L | RT5645_PWR_HP_R |
RT5645_PWR_HA, 0);
snd_soc_component_update_bits(component, RT5645_DEPOP_M2,
RT5645_DEPOP_MASK, 0);
}
}
}
}
static int rt5645_hp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
hp_amp_power(component, 1);
/* headphone unmute sequence */
if (rt5645->codec_type == CODEC_TYPE_RT5645) {
snd_soc_component_update_bits(component, RT5645_DEPOP_M3,
RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
RT5645_CP_FQ3_MASK,
(RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) |
(RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
(RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT));
regmap_write(rt5645->regmap, RT5645_PR_BASE +
RT5645_MAMP_INT_REG2, 0xfc00);
snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN);
snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
RT5645_RSTN_MASK, RT5645_RSTN_EN);
snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK |
RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS |
RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
msleep(40);
snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |
RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |
RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);
}
break;
case SND_SOC_DAPM_PRE_PMD:
/* headphone mute sequence */
if (rt5645->codec_type == CODEC_TYPE_RT5645) {
snd_soc_component_update_bits(component, RT5645_DEPOP_M3,
RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
RT5645_CP_FQ3_MASK,
(RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) |
(RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
(RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT));
regmap_write(rt5645->regmap, RT5645_PR_BASE +
RT5645_MAMP_INT_REG2, 0xfc00);
snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
RT5645_HP_SG_MASK, RT5645_HP_SG_EN);
snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
RT5645_RSTP_MASK, RT5645_RSTP_EN);
snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK |
RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS |
RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
msleep(30);
}
hp_amp_power(component, 0);
break;
default:
return 0;
}
return 0;
}
static int rt5645_spk_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
rt5645_enable_hweq(component);
snd_soc_component_update_bits(component, RT5645_PWR_DIG1,
RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
RT5645_PWR_CLS_D_L,
RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
RT5645_PWR_CLS_D_L);
snd_soc_component_update_bits(component, RT5645_GEN_CTRL3,
RT5645_DET_CLK_MASK, RT5645_DET_CLK_MODE1);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, RT5645_GEN_CTRL3,
RT5645_DET_CLK_MASK, RT5645_DET_CLK_DIS);
snd_soc_component_write(component, RT5645_EQ_CTRL2, 0);
snd_soc_component_update_bits(component, RT5645_PWR_DIG1,
RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
RT5645_PWR_CLS_D_L, 0);
break;
default:
return 0;
}
return 0;
}
static int rt5645_lout_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
hp_amp_power(component, 1);
snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
RT5645_PWR_LM, RT5645_PWR_LM);
snd_soc_component_update_bits(component, RT5645_LOUT1,
RT5645_L_MUTE | RT5645_R_MUTE, 0);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, RT5645_LOUT1,
RT5645_L_MUTE | RT5645_R_MUTE,
RT5645_L_MUTE | RT5645_R_MUTE);
snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
RT5645_PWR_LM, 0);
hp_amp_power(component, 0);
break;
default:
return 0;
}
return 0;
}
static int rt5645_bst2_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(component, RT5645_PWR_ANLG2,
RT5645_PWR_BST2_P, RT5645_PWR_BST2_P);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, RT5645_PWR_ANLG2,
RT5645_PWR_BST2_P, 0);
break;
default:
return 0;
}
return 0;
}
static int rt5645_set_micbias1_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *k, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,
RT5645_MICBIAS1_POW_CTRL_SEL_MASK,
RT5645_MICBIAS1_POW_CTRL_SEL_M);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,
RT5645_MICBIAS1_POW_CTRL_SEL_MASK,
RT5645_MICBIAS1_POW_CTRL_SEL_A);
break;
default:
return 0;
}
return 0;
}
static int rt5645_set_micbias2_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *k, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,
RT5645_MICBIAS2_POW_CTRL_SEL_MASK,
RT5645_MICBIAS2_POW_CTRL_SEL_M);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,
RT5645_MICBIAS2_POW_CTRL_SEL_MASK,
RT5645_MICBIAS2_POW_CTRL_SEL_A);
break;
default:
return 0;
}
return 0;
}
static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER,
RT5645_PWR_LDO2_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2,
RT5645_PWR_PLL_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("JD Power", RT5645_PWR_ANLG2,
RT5645_PWR_JD1_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5645_PWR_VOL,
RT5645_PWR_MIC_DET_BIT, 0, NULL, 0),
/* ASRC */
SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5645_ASRC_1,
11, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5645_ASRC_1,
12, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5645_ASRC_1,
10, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5645_ASRC_1,
9, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5645_ASRC_1,
8, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5645_ASRC_1,
7, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5645_ASRC_1,
5, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5645_ASRC_1,
4, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5645_ASRC_1,
3, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5645_ASRC_1,
1, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5645_ASRC_1,
0, 0, NULL, 0),
/* Input Side */
/* micbias */
SND_SOC_DAPM_SUPPLY("micbias1", RT5645_PWR_ANLG2,
RT5645_PWR_MB1_BIT, 0, rt5645_set_micbias1_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("micbias2", RT5645_PWR_ANLG2,
RT5645_PWR_MB2_BIT, 0, rt5645_set_micbias2_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
/* Input Lines */
SND_SOC_DAPM_INPUT("DMIC L1"),
SND_SOC_DAPM_INPUT("DMIC R1"),
SND_SOC_DAPM_INPUT("DMIC L2"),
SND_SOC_DAPM_INPUT("DMIC R2"),
SND_SOC_DAPM_INPUT("IN1P"),
SND_SOC_DAPM_INPUT("IN1N"),
SND_SOC_DAPM_INPUT("IN2P"),
SND_SOC_DAPM_INPUT("IN2N"),
SND_SOC_DAPM_INPUT("Haptic Generator"),
SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5645_DMIC_CTRL1,
RT5645_DMIC_1_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5645_DMIC_CTRL1,
RT5645_DMIC_2_EN_SFT, 0, NULL, 0),
/* Boost */
SND_SOC_DAPM_PGA("BST1", RT5645_PWR_ANLG2,
RT5645_PWR_BST1_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA_E("BST2", RT5645_PWR_ANLG2,
RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
/* Input Volume */
SND_SOC_DAPM_PGA("INL VOL", RT5645_PWR_VOL,
RT5645_PWR_IN_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("INR VOL", RT5645_PWR_VOL,
RT5645_PWR_IN_R_BIT, 0, NULL, 0),
/* REC Mixer */
SND_SOC_DAPM_MIXER("RECMIXL", RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT,
0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)),
SND_SOC_DAPM_MIXER("RECMIXR", RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT,
0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)),
/* ADCs */
SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SUPPLY("ADC L power", RT5645_PWR_DIG1,
RT5645_PWR_ADC_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC R power", RT5645_PWR_DIG1,
RT5645_PWR_ADC_R_BIT, 0, NULL, 0),
/* ADC Mux */
SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
&rt5645_sto1_dmic_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
&rt5645_sto_adc2_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
&rt5645_sto_adc2_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
&rt5645_sto_adc1_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
&rt5645_sto_adc1_mux),
SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
&rt5645_mono_dmic_l_mux),
SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
&rt5645_mono_dmic_r_mux),
SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
&rt5645_mono_adc_l2_mux),
SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
&rt5645_mono_adc_l1_mux),
SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
&rt5645_mono_adc_r1_mux),
SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
&rt5645_mono_adc_r2_mux),
/* ADC Mixer */
SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter", 1, RT5645_PWR_DIG2,
RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0),
SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix),
NULL, 0),
SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix),
NULL, 0),
SND_SOC_DAPM_SUPPLY_S("adc mono left filter", 1, RT5645_PWR_DIG2,
RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix),
NULL, 0),
SND_SOC_DAPM_SUPPLY_S("adc mono right filter", 1, RT5645_PWR_DIG2,
RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix),
NULL, 0),
/* ADC PGA */
SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
/* IF1 2 Mux */
SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM,
0, 0, &rt5645_if2_adc_in_mux),
/* Digital Interface */
SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1,
RT5645_PWR_I2S1_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("I2S2", RT5645_PWR_DIG1,
RT5645_PWR_I2S2_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
/* Digital Interface Select */
SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM,
0, 0, &rt5645_vad_adc_mux),
/* Audio Interface */
SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
/* Output Side */
/* DAC mixer before sound effect */
SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)),
SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)),
/* DAC2 channel Mux */
SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux),
SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux),
SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1,
RT5645_PWR_DAC_L2_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1,
RT5645_PWR_DAC_R2_BIT, 0, NULL, 0),
SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux),
SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux),
/* DAC Mixer */
SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter", 1, RT5645_PWR_DIG2,
RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("dac mono left filter", 1, RT5645_PWR_DIG2,
RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("dac mono right filter", 1, RT5645_PWR_DIG2,
RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)),
SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)),
SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)),
SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)),
SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)),
SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)),
/* DACs */
SND_SOC_DAPM_DAC("DAC L1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT,
0),
SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT,
0),
SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT,
0),
SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT,
0),
/* OUT Mixer */
SND_SOC_DAPM_MIXER("SPK MIXL", RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT,
0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)),
SND_SOC_DAPM_MIXER("SPK MIXR", RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT,
0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)),
SND_SOC_DAPM_MIXER("OUT MIXL", RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT,
0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)),
SND_SOC_DAPM_MIXER("OUT MIXR", RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT,
0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)),
/* Ouput Volume */
SND_SOC_DAPM_SWITCH("SPKVOL L", RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0,
&spk_l_vol_control),
SND_SOC_DAPM_SWITCH("SPKVOL R", RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0,
&spk_r_vol_control),
SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT,
0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)),
SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT,
0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)),
SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power", RT5645_PWR_MIXER,
RT5645_PWR_HM_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power", RT5645_PWR_MIXER,
RT5645_PWR_HM_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SWITCH("HPOVOL L", SND_SOC_NOPM, 0, 0, &hp_l_vol_control),
SND_SOC_DAPM_SWITCH("HPOVOL R", SND_SOC_NOPM, 0, 0, &hp_r_vol_control),
/* HPO/LOUT/Mono Mixer */
SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix,
ARRAY_SIZE(rt5645_spo_l_mix)),
SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix,
ARRAY_SIZE(rt5645_spo_r_mix)),
SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, rt5645_hpo_mix,
ARRAY_SIZE(rt5645_hpo_mix)),
SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, rt5645_lout_mix,
ARRAY_SIZE(rt5645_lout_mix)),
SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_S("SPK amp", 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
/* PDM */
SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT,
0, NULL, 0),
SND_SOC_DAPM_MUX("PDM1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux),
SND_SOC_DAPM_MUX("PDM1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux),
SND_SOC_DAPM_SWITCH("PDM1 L", SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control),
SND_SOC_DAPM_SWITCH("PDM1 R", SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control),
/* Output Lines */
SND_SOC_DAPM_OUTPUT("HPOL"),
SND_SOC_DAPM_OUTPUT("HPOR"),
SND_SOC_DAPM_OUTPUT("LOUTL"),
SND_SOC_DAPM_OUTPUT("LOUTR"),
SND_SOC_DAPM_OUTPUT("PDM1L"),
SND_SOC_DAPM_OUTPUT("PDM1R"),
SND_SOC_DAPM_OUTPUT("SPOL"),
SND_SOC_DAPM_OUTPUT("SPOR"),
};
static const struct snd_soc_dapm_widget rt5645_specific_dapm_widgets[] = {
SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
&rt5645_if1_dac0_tdm_sel_mux),
SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
&rt5645_if1_dac1_tdm_sel_mux),
SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
&rt5645_if1_dac2_tdm_sel_mux),
SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
&rt5645_if1_dac3_tdm_sel_mux),
SND_SOC_DAPM_MUX("RT5645 IF1 ADC Mux", SND_SOC_NOPM,
0, 0, &rt5645_if1_adc_in_mux),
SND_SOC_DAPM_MUX("RT5645 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
0, 0, &rt5645_if1_adc1_in_mux),
SND_SOC_DAPM_MUX("RT5645 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
0, 0, &rt5645_if1_adc2_in_mux),
SND_SOC_DAPM_MUX("RT5645 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
0, 0, &rt5645_if1_adc3_in_mux),
};
static const struct snd_soc_dapm_widget rt5650_specific_dapm_widgets[] = {
SND_SOC_DAPM_MUX("A DAC1 L Mux", SND_SOC_NOPM,
0, 0, &rt5650_a_dac1_l_mux),
SND_SOC_DAPM_MUX("A DAC1 R Mux", SND_SOC_NOPM,
0, 0, &rt5650_a_dac1_r_mux),
SND_SOC_DAPM_MUX("A DAC2 L Mux", SND_SOC_NOPM,
0, 0, &rt5650_a_dac2_l_mux),
SND_SOC_DAPM_MUX("A DAC2 R Mux", SND_SOC_NOPM,
0, 0, &rt5650_a_dac2_r_mux),
SND_SOC_DAPM_MUX("RT5650 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
0, 0, &rt5650_if1_adc1_in_mux),
SND_SOC_DAPM_MUX("RT5650 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
0, 0, &rt5650_if1_adc2_in_mux),
SND_SOC_DAPM_MUX("RT5650 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
0, 0, &rt5650_if1_adc3_in_mux),
SND_SOC_DAPM_MUX("RT5650 IF1 ADC Mux", SND_SOC_NOPM,
0, 0, &rt5650_if1_adc_in_mux),
SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
&rt5650_if1_dac0_tdm_sel_mux),
SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
&rt5650_if1_dac1_tdm_sel_mux),
SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
&rt5650_if1_dac2_tdm_sel_mux),
SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
&rt5650_if1_dac3_tdm_sel_mux),
};
static const struct snd_soc_dapm_route rt5645_dapm_routes[] = {
{ "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
{ "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
{ "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
{ "dac mono left filter", NULL, "DAC MONO L ASRC", is_using_asrc },
{ "dac mono right filter", NULL, "DAC MONO R ASRC", is_using_asrc },
{ "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
{ "I2S1", NULL, "I2S1 ASRC" },
{ "I2S2", NULL, "I2S2 ASRC" },
{ "IN1P", NULL, "LDO2" },
{ "IN2P", NULL, "LDO2" },
{ "DMIC1", NULL, "DMIC L1" },
{ "DMIC1", NULL, "DMIC R1" },
{ "DMIC2", NULL, "DMIC L2" },
{ "DMIC2", NULL, "DMIC R2" },
{ "BST1", NULL, "IN1P" },
{ "BST1", NULL, "IN1N" },
{ "BST1", NULL, "JD Power" },
{ "BST1", NULL, "Mic Det Power" },
{ "BST2", NULL, "IN2P" },
{ "BST2", NULL, "IN2N" },
{ "INL VOL", NULL, "IN2P" },
{ "INR VOL", NULL, "IN2N" },
{ "RECMIXL", "HPOL Switch", "HPOL" },
{ "RECMIXL", "INL Switch", "INL VOL" },
{ "RECMIXL", "BST2 Switch", "BST2" },
{ "RECMIXL", "BST1 Switch", "BST1" },
{ "RECMIXL", "OUT MIXL Switch", "OUT MIXL" },
{ "RECMIXR", "HPOR Switch", "HPOR" },
{ "RECMIXR", "INR Switch", "INR VOL" },
{ "RECMIXR", "BST2 Switch", "BST2" },
{ "RECMIXR", "BST1 Switch", "BST1" },
{ "RECMIXR", "OUT MIXR Switch", "OUT MIXR" },
{ "ADC L", NULL, "RECMIXL" },
{ "ADC L", NULL, "ADC L power" },
{ "ADC R", NULL, "RECMIXR" },
{ "ADC R", NULL, "ADC R power" },
{"DMIC L1", NULL, "DMIC CLK"},
{"DMIC L1", NULL, "DMIC1 Power"},
{"DMIC R1", NULL, "DMIC CLK"},
{"DMIC R1", NULL, "DMIC1 Power"},
{"DMIC L2", NULL, "DMIC CLK"},
{"DMIC L2", NULL, "DMIC2 Power"},
{"DMIC R2", NULL, "DMIC CLK"},
{"DMIC R2", NULL, "DMIC2 Power"},
{ "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
{ "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
{ "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC" },
{ "Mono DMIC L Mux", "DMIC1", "DMIC L1" },
{ "Mono DMIC L Mux", "DMIC2", "DMIC L2" },
{ "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC" },
{ "Mono DMIC R Mux", "DMIC1", "DMIC R1" },
{ "Mono DMIC R Mux", "DMIC2", "DMIC R2" },
{ "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC" },
{ "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" },
{ "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
{ "Stereo1 ADC L1 Mux", "ADC", "ADC L" },
{ "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
{ "Stereo1 ADC R1 Mux", "ADC", "ADC R" },
{ "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
{ "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" },
{ "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
{ "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
{ "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
{ "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
{ "Mono ADC L1 Mux", "ADC", "ADC L" },
{ "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
{ "Mono ADC R1 Mux", "ADC", "ADC R" },
{ "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
{ "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
{ "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
{ "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
{ "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
{ "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
{ "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
{ "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
{ "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
{ "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
{ "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
{ "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
{ "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
{ "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
{ "Mono ADC MIXL", NULL, "adc mono left filter" },
{ "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
{ "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
{ "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
{ "Mono ADC MIXR", NULL, "adc mono right filter" },
{ "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
{ "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" },
{ "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" },
{ "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" },
{ "IF_ADC1", NULL, "Stereo1 ADC MIXL" },
{ "IF_ADC1", NULL, "Stereo1 ADC MIXR" },
{ "IF_ADC2", NULL, "Mono ADC MIXL" },
{ "IF_ADC2", NULL, "Mono ADC MIXR" },
{ "VAD_ADC", NULL, "VAD ADC Mux" },
{ "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
{ "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
{ "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" },
{ "IF1 ADC", NULL, "I2S1" },
{ "IF2 ADC", NULL, "I2S2" },
{ "IF2 ADC", NULL, "IF2 ADC Mux" },
{ "AIF2TX", NULL, "IF2 ADC" },
{ "IF1 DAC0", NULL, "AIF1RX" },
{ "IF1 DAC1", NULL, "AIF1RX" },
{ "IF1 DAC2", NULL, "AIF1RX" },
{ "IF1 DAC3", NULL, "AIF1RX" },
{ "IF2 DAC", NULL, "AIF2RX" },
{ "IF1 DAC0", NULL, "I2S1" },
{ "IF1 DAC1", NULL, "I2S1" },
{ "IF1 DAC2", NULL, "I2S1" },
{ "IF1 DAC3", NULL, "I2S1" },
{ "IF2 DAC", NULL, "I2S2" },
{ "IF2 DAC L", NULL, "IF2 DAC" },
{ "IF2 DAC R", NULL, "IF2 DAC" },
{ "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" },
{ "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" },
{ "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },
{ "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" },
{ "DAC1 MIXL", NULL, "dac stereo1 filter" },
{ "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" },
{ "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" },
{ "DAC1 MIXR", NULL, "dac stereo1 filter" },
{ "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
{ "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" },
{ "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },
{ "DAC L2 Volume", NULL, "DAC L2 Mux" },
{ "DAC L2 Volume", NULL, "dac mono left filter" },
{ "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
{ "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" },
{ "DAC R2 Mux", "Haptic", "Haptic Generator" },
{ "DAC R2 Volume", NULL, "DAC R2 Mux" },
{ "DAC R2 Volume", NULL, "dac mono right filter" },
{ "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
{ "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
{ "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
{ "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
{ "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
{ "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
{ "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
{ "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
{ "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
{ "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
{ "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
{ "Mono DAC MIXL", NULL, "dac mono left filter" },
{ "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
{ "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
{ "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
{ "Mono DAC MIXR", NULL, "dac mono right filter" },
{ "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
{ "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
{ "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
{ "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
{ "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
{ "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
{ "DAC L1", NULL, "PLL1", is_sys_clk_from_pll },
{ "DAC R1", NULL, "PLL1", is_sys_clk_from_pll },
{ "DAC L2", NULL, "PLL1", is_sys_clk_from_pll },
{ "DAC R2", NULL, "PLL1", is_sys_clk_from_pll },
{ "SPK MIXL", "BST1 Switch", "BST1" },
{ "SPK MIXL", "INL Switch", "INL VOL" },
{ "SPK MIXL", "DAC L1 Switch", "DAC L1" },
{ "SPK MIXL", "DAC L2 Switch", "DAC L2" },
{ "SPK MIXR", "BST2 Switch", "BST2" },
{ "SPK MIXR", "INR Switch", "INR VOL" },
{ "SPK MIXR", "DAC R1 Switch", "DAC R1" },
{ "SPK MIXR", "DAC R2 Switch", "DAC R2" },
{ "OUT MIXL", "BST1 Switch", "BST1" },
{ "OUT MIXL", "INL Switch", "INL VOL" },
{ "OUT MIXL", "DAC L2 Switch", "DAC L2" },
{ "OUT MIXL", "DAC L1 Switch", "DAC L1" },
{ "OUT MIXR", "BST2 Switch", "BST2" },
{ "OUT MIXR", "INR Switch", "INR VOL" },
{ "OUT MIXR", "DAC R2 Switch", "DAC R2" },
{ "OUT MIXR", "DAC R1 Switch", "DAC R1" },
{ "HPOVOL MIXL", "DAC1 Switch", "DAC L1" },
{ "HPOVOL MIXL", "DAC2 Switch", "DAC L2" },
{ "HPOVOL MIXL", "INL Switch", "INL VOL" },
{ "HPOVOL MIXL", "BST1 Switch", "BST1" },
{ "HPOVOL MIXL", NULL, "HPOVOL MIXL Power" },
{ "HPOVOL MIXR", "DAC1 Switch", "DAC R1" },
{ "HPOVOL MIXR", "DAC2 Switch", "DAC R2" },
{ "HPOVOL MIXR", "INR Switch", "INR VOL" },
{ "HPOVOL MIXR", "BST2 Switch", "BST2" },
{ "HPOVOL MIXR", NULL, "HPOVOL MIXR Power" },
{ "DAC 2", NULL, "DAC L2" },
{ "DAC 2", NULL, "DAC R2" },
{ "DAC 1", NULL, "DAC L1" },
{ "DAC 1", NULL, "DAC R1" },
{ "HPOVOL L", "Switch", "HPOVOL MIXL" },
{ "HPOVOL R", "Switch", "HPOVOL MIXR" },
{ "HPOVOL", NULL, "HPOVOL L" },
{ "HPOVOL", NULL, "HPOVOL R" },
{ "HPO MIX", "DAC1 Switch", "DAC 1" },
{ "HPO MIX", "HPVOL Switch", "HPOVOL" },
{ "SPKVOL L", "Switch", "SPK MIXL" },
{ "SPKVOL R", "Switch", "SPK MIXR" },
{ "SPOL MIX", "DAC L1 Switch", "DAC L1" },
{ "SPOL MIX", "SPKVOL L Switch", "SPKVOL L" },
{ "SPOR MIX", "DAC R1 Switch", "DAC R1" },
{ "SPOR MIX", "SPKVOL R Switch", "SPKVOL R" },
{ "LOUT MIX", "DAC L1 Switch", "DAC L1" },
{ "LOUT MIX", "DAC R1 Switch", "DAC R1" },
{ "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" },
{ "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" },
{ "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
{ "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" },
{ "PDM1 L Mux", NULL, "PDM1 Power" },
{ "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
{ "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" },
{ "PDM1 R Mux", NULL, "PDM1 Power" },
{ "HP amp", NULL, "HPO MIX" },
{ "HP amp", NULL, "JD Power" },
{ "HP amp", NULL, "Mic Det Power" },
{ "HP amp", NULL, "LDO2" },
{ "HPOL", NULL, "HP amp" },
{ "HPOR", NULL, "HP amp" },
{ "LOUT amp", NULL, "LOUT MIX" },
{ "LOUTL", NULL, "LOUT amp" },
{ "LOUTR", NULL, "LOUT amp" },
{ "PDM1 L", "Switch", "PDM1 L Mux" },
{ "PDM1 R", "Switch", "PDM1 R Mux" },
{ "PDM1L", NULL, "PDM1 L" },
{ "PDM1R", NULL, "PDM1 R" },
{ "SPK amp", NULL, "SPOL MIX" },
{ "SPK amp", NULL, "SPOR MIX" },
{ "SPOL", NULL, "SPK amp" },
{ "SPOR", NULL, "SPK amp" },
};
static const struct snd_soc_dapm_route rt5650_specific_dapm_routes[] = {
{ "A DAC1 L Mux", "DAC1", "DAC1 MIXL"},
{ "A DAC1 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
{ "A DAC1 R Mux", "DAC1", "DAC1 MIXR"},
{ "A DAC1 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
{ "A DAC2 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
{ "A DAC2 L Mux", "Mono DAC Mixer", "Mono DAC MIXL"},
{ "A DAC2 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
{ "A DAC2 R Mux", "Mono DAC Mixer", "Mono DAC MIXR"},
{ "DAC L1", NULL, "A DAC1 L Mux" },
{ "DAC R1", NULL, "A DAC1 R Mux" },
{ "DAC L2", NULL, "A DAC2 L Mux" },
{ "DAC R2", NULL, "A DAC2 R Mux" },
{ "RT5650 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
{ "RT5650 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
{ "RT5650 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
{ "RT5650 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
{ "RT5650 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
{ "RT5650 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
{ "RT5650 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
{ "RT5650 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
{ "RT5650 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
{ "RT5650 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
{ "RT5650 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
{ "RT5650 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
{ "IF1 ADC", NULL, "RT5650 IF1 ADC1 Swap Mux" },
{ "IF1 ADC", NULL, "RT5650 IF1 ADC2 Swap Mux" },
{ "IF1 ADC", NULL, "RT5650 IF1 ADC3 Swap Mux" },
{ "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/DAC_REF/Null", "IF1 ADC" },
{ "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/Null/DAC_REF", "IF1 ADC" },
{ "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/IF_ADC2/Null", "IF1 ADC" },
{ "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/Null/IF_ADC2", "IF1 ADC" },
{ "RT5650 IF1 ADC Mux", "IF_ADC1/Null/DAC_REF/IF_ADC2", "IF1 ADC" },
{ "RT5650 IF1 ADC Mux", "IF_ADC1/Null/IF_ADC2/DAC_REF", "IF1 ADC" },
{ "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/DAC_REF/Null", "IF1 ADC" },
{ "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/Null/DAC_REF", "IF1 ADC" },
{ "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/IF_ADC1/Null", "IF1 ADC" },
{ "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/Null/IF_ADC1", "IF1 ADC" },
{ "RT5650 IF1 ADC Mux", "IF_ADC2/Null/DAC_REF/IF_ADC1", "IF1 ADC" },
{ "RT5650 IF1 ADC Mux", "IF_ADC2/Null/IF_ADC1/DAC_REF", "IF1 ADC" },
{ "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/IF_ADC2/Null", "IF1 ADC" },
{ "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/Null/IF_ADC2", "IF1 ADC" },
{ "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/IF_ADC1/Null", "IF1 ADC" },
{ "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/Null/IF_ADC1", "IF1 ADC" },
{ "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC1/IF_ADC2", "IF1 ADC" },
{ "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC2/IF_ADC1", "IF1 ADC" },
{ "RT5650 IF1 ADC Mux", "Null/IF_ADC1/IF_ADC2/DAC_REF", "IF1 ADC" },
{ "RT5650 IF1 ADC Mux", "Null/IF_ADC1/DAC_REF/IF_ADC2", "IF1 ADC" },
{ "RT5650 IF1 ADC Mux", "Null/IF_ADC2/IF_ADC1/DAC_REF", "IF1 ADC" },
{ "RT5650 IF1 ADC Mux", "Null/IF_ADC2/DAC_REF/IF_ADC1", "IF1 ADC" },
{ "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC1/IF_ADC2", "IF1 ADC" },
{ "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC2/IF_ADC1", "IF1 ADC" },
{ "AIF1TX", NULL, "RT5650 IF1 ADC Mux" },
{ "RT5650 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
{ "RT5650 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
{ "RT5650 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
{ "RT5650 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
{ "RT5650 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
{ "RT5650 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
{ "RT5650 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
{ "RT5650 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
{ "RT5650 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
{ "RT5650 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
{ "RT5650 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
{ "RT5650 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
{ "RT5650 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
{ "RT5650 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
{ "RT5650 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
{ "RT5650 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
{ "DAC1 L Mux", "IF1 DAC", "RT5650 IF1 DAC1 L Mux" },
{ "DAC1 R Mux", "IF1 DAC", "RT5650 IF1 DAC1 R Mux" },
{ "DAC L2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 L Mux" },
{ "DAC R2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 R Mux" },
};
static const struct snd_soc_dapm_route rt5645_specific_dapm_routes[] = {
{ "DAC L1", NULL, "Stereo DAC MIXL" },
{ "DAC R1", NULL, "Stereo DAC MIXR" },
{ "DAC L2", NULL, "Mono DAC MIXL" },
{ "DAC R2", NULL, "Mono DAC MIXR" },
{ "RT5645 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
{ "RT5645 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
{ "RT5645 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
{ "RT5645 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
{ "RT5645 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
{ "RT5645 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
{ "RT5645 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
{ "RT5645 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
{ "RT5645 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
{ "RT5645 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
{ "RT5645 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
{ "RT5645 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
{ "IF1 ADC", NULL, "RT5645 IF1 ADC1 Swap Mux" },
{ "IF1 ADC", NULL, "RT5645 IF1 ADC2 Swap Mux" },
{ "IF1 ADC", NULL, "RT5645 IF1 ADC3 Swap Mux" },
{ "RT5645 IF1 ADC Mux", "IF_ADC1/IF_ADC2/VAD_ADC", "IF1 ADC" },
{ "RT5645 IF1 ADC Mux", "IF_ADC2/IF_ADC1/VAD_ADC", "IF1 ADC" },
{ "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC1/IF_ADC2", "IF1 ADC" },
{ "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC2/IF_ADC1", "IF1 ADC" },
{ "AIF1TX", NULL, "RT5645 IF1 ADC Mux" },
{ "RT5645 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
{ "RT5645 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
{ "RT5645 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
{ "RT5645 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
{ "RT5645 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
{ "RT5645 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
{ "RT5645 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
{ "RT5645 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
{ "RT5645 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
{ "RT5645 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
{ "RT5645 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
{ "RT5645 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
{ "RT5645 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
{ "RT5645 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
{ "RT5645 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
{ "RT5645 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
{ "DAC1 L Mux", "IF1 DAC", "RT5645 IF1 DAC1 L Mux" },
{ "DAC1 R Mux", "IF1 DAC", "RT5645 IF1 DAC1 R Mux" },
{ "DAC L2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 L Mux" },
{ "DAC R2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 R Mux" },
};
static const struct snd_soc_dapm_route rt5645_old_dapm_routes[] = {
{ "SPOL MIX", "DAC R1 Switch", "DAC R1" },
{ "SPOL MIX", "SPKVOL R Switch", "SPKVOL R" },
};
static int rt5645_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
unsigned int val_len = 0, val_clk, mask_clk, dl_sft;
int pre_div, bclk_ms, frame_size;
rt5645->lrck[dai->id] = params_rate(params);
pre_div = rl6231_get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]);
if (pre_div < 0) {
dev_err(component->dev, "Unsupported clock setting\n");
return -EINVAL;
}
frame_size = snd_soc_params_to_frame_size(params);
if (frame_size < 0) {
dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
return -EINVAL;
}
switch (rt5645->codec_type) {
case CODEC_TYPE_RT5650:
dl_sft = 4;
break;
default:
dl_sft = 2;
break;
}
bclk_ms = frame_size > 32;
rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms);
dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
rt5645->bclk[dai->id], rt5645->lrck[dai->id]);
dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
bclk_ms, pre_div, dai->id);
switch (params_width(params)) {
case 16:
break;
case 20:
val_len = 0x1;
break;
case 24:
val_len = 0x2;
break;
case 8:
val_len = 0x3;
break;
default:
return -EINVAL;
}
switch (dai->id) {
case RT5645_AIF1:
mask_clk = RT5645_I2S_PD1_MASK;
val_clk = pre_div << RT5645_I2S_PD1_SFT;
snd_soc_component_update_bits(component, RT5645_I2S1_SDP,
(0x3 << dl_sft), (val_len << dl_sft));
snd_soc_component_update_bits(component, RT5645_ADDA_CLK1, mask_clk, val_clk);
break;
case RT5645_AIF2:
mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK;
val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT |
pre_div << RT5645_I2S_PD2_SFT;
snd_soc_component_update_bits(component, RT5645_I2S2_SDP,
(0x3 << dl_sft), (val_len << dl_sft));
snd_soc_component_update_bits(component, RT5645_ADDA_CLK1, mask_clk, val_clk);
break;
default:
dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
return -EINVAL;
}
return 0;
}
static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0, pol_sft;
switch (rt5645->codec_type) {
case CODEC_TYPE_RT5650:
pol_sft = 8;
break;
default:
pol_sft = 7;
break;
}
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
rt5645->master[dai->id] = 1;
break;
case SND_SOC_DAIFMT_CBS_CFS:
reg_val |= RT5645_I2S_MS_S;
rt5645->master[dai->id] = 0;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
reg_val |= (1 << pol_sft);
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_LEFT_J:
reg_val |= RT5645_I2S_DF_LEFT;
break;
case SND_SOC_DAIFMT_DSP_A:
reg_val |= RT5645_I2S_DF_PCM_A;
break;
case SND_SOC_DAIFMT_DSP_B:
reg_val |= RT5645_I2S_DF_PCM_B;
break;
default:
return -EINVAL;
}
switch (dai->id) {
case RT5645_AIF1:
snd_soc_component_update_bits(component, RT5645_I2S1_SDP,
RT5645_I2S_MS_MASK | (1 << pol_sft) |
RT5645_I2S_DF_MASK, reg_val);
break;
case RT5645_AIF2:
snd_soc_component_update_bits(component, RT5645_I2S2_SDP,
RT5645_I2S_MS_MASK | (1 << pol_sft) |
RT5645_I2S_DF_MASK, reg_val);
break;
default:
dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
return -EINVAL;
}
return 0;
}
static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0;
if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src)
return 0;
switch (clk_id) {
case RT5645_SCLK_S_MCLK:
reg_val |= RT5645_SCLK_SRC_MCLK;
break;
case RT5645_SCLK_S_PLL1:
reg_val |= RT5645_SCLK_SRC_PLL1;
break;
case RT5645_SCLK_S_RCCLK:
reg_val |= RT5645_SCLK_SRC_RCCLK;
break;
default:
dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
return -EINVAL;
}
snd_soc_component_update_bits(component, RT5645_GLB_CLK,
RT5645_SCLK_SRC_MASK, reg_val);
rt5645->sysclk = freq;
rt5645->sysclk_src = clk_id;
dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
return 0;
}
static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
unsigned int freq_in, unsigned int freq_out)
{
struct snd_soc_component *component = dai->component;
struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
struct rl6231_pll_code pll_code;
int ret;
if (source == rt5645->pll_src && freq_in == rt5645->pll_in &&
freq_out == rt5645->pll_out)
return 0;
if (!freq_in || !freq_out) {
dev_dbg(component->dev, "PLL disabled\n");
rt5645->pll_in = 0;
rt5645->pll_out = 0;
snd_soc_component_update_bits(component, RT5645_GLB_CLK,
RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK);
return 0;
}
switch (source) {
case RT5645_PLL1_S_MCLK:
snd_soc_component_update_bits(component, RT5645_GLB_CLK,
RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK);
break;
case RT5645_PLL1_S_BCLK1:
case RT5645_PLL1_S_BCLK2:
switch (dai->id) {
case RT5645_AIF1:
snd_soc_component_update_bits(component, RT5645_GLB_CLK,
RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1);
break;
case RT5645_AIF2:
snd_soc_component_update_bits(component, RT5645_GLB_CLK,
RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2);
break;
default:
dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
return -EINVAL;
}
break;
default:
dev_err(component->dev, "Unknown PLL source %d\n", source);
return -EINVAL;
}
ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
if (ret < 0) {
dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
return ret;
}
dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
pll_code.n_code, pll_code.k_code);
snd_soc_component_write(component, RT5645_PLL_CTRL1,
pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code);
snd_soc_component_write(component, RT5645_PLL_CTRL2,
((pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT) |
(pll_code.m_bp << RT5645_PLL_M_BP_SFT));
rt5645->pll_in = freq_in;
rt5645->pll_out = freq_out;
rt5645->pll_src = source;
return 0;
}
static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
unsigned int i_slot_sft, o_slot_sft, i_width_sht, o_width_sht, en_sft;
unsigned int mask, val = 0;
switch (rt5645->codec_type) {
case CODEC_TYPE_RT5650:
en_sft = 15;
i_slot_sft = 10;
o_slot_sft = 8;
i_width_sht = 6;
o_width_sht = 4;
mask = 0x8ff0;
break;
default:
en_sft = 14;
i_slot_sft = o_slot_sft = 12;
i_width_sht = o_width_sht = 10;
mask = 0x7c00;
break;
}
if (rx_mask || tx_mask) {
val |= (1 << en_sft);
if (rt5645->codec_type == CODEC_TYPE_RT5645)
snd_soc_component_update_bits(component, RT5645_BASS_BACK,
RT5645_G_BB_BST_MASK, RT5645_G_BB_BST_25DB);
}
switch (slots) {
case 4:
val |= (1 << i_slot_sft) | (1 << o_slot_sft);
break;
case 6:
val |= (2 << i_slot_sft) | (2 << o_slot_sft);
break;
case 8:
val |= (3 << i_slot_sft) | (3 << o_slot_sft);
break;
case 2:
default:
break;
}
switch (slot_width) {
case 20:
val |= (1 << i_width_sht) | (1 << o_width_sht);
break;
case 24:
val |= (2 << i_width_sht) | (2 << o_width_sht);
break;
case 32:
val |= (3 << i_width_sht) | (3 << o_width_sht);
break;
case 16:
default:
break;
}
snd_soc_component_update_bits(component, RT5645_TDM_CTRL_1, mask, val);
return 0;
}
static int rt5645_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_PREPARE:
if (SND_SOC_BIAS_STANDBY == snd_soc_component_get_bias_level(component)) {
snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
RT5645_PWR_VREF1 | RT5645_PWR_MB |
RT5645_PWR_BG | RT5645_PWR_VREF2,
RT5645_PWR_VREF1 | RT5645_PWR_MB |
RT5645_PWR_BG | RT5645_PWR_VREF2);
mdelay(10);
snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
RT5645_PWR_FV1 | RT5645_PWR_FV2,
RT5645_PWR_FV1 | RT5645_PWR_FV2);
snd_soc_component_update_bits(component, RT5645_GEN_CTRL1,
RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
}
break;
case SND_SOC_BIAS_STANDBY:
snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
RT5645_PWR_VREF1 | RT5645_PWR_MB |
RT5645_PWR_BG | RT5645_PWR_VREF2,
RT5645_PWR_VREF1 | RT5645_PWR_MB |
RT5645_PWR_BG | RT5645_PWR_VREF2);
mdelay(10);
snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
RT5645_PWR_FV1 | RT5645_PWR_FV2,
RT5645_PWR_FV1 | RT5645_PWR_FV2);
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140);
msleep(40);
if (rt5645->en_button_func)
queue_delayed_work(system_power_efficient_wq,
&rt5645->jack_detect_work,
msecs_to_jiffies(0));
}
break;
case SND_SOC_BIAS_OFF:
snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1100);
if (!rt5645->en_button_func)
snd_soc_component_update_bits(component, RT5645_GEN_CTRL1,
RT5645_DIG_GATE_CTRL, 0);
snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
RT5645_PWR_VREF1 | RT5645_PWR_MB |
RT5645_PWR_BG | RT5645_PWR_VREF2 |
RT5645_PWR_FV1 | RT5645_PWR_FV2, 0x0);
break;
default:
break;
}
return 0;
}
static void rt5645_enable_push_button_irq(struct snd_soc_component *component,
bool enable)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
if (enable) {
snd_soc_dapm_force_enable_pin(dapm, "ADC L power");
snd_soc_dapm_force_enable_pin(dapm, "ADC R power");
snd_soc_dapm_sync(dapm);
snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD1, 0x3, 0x3);
snd_soc_component_update_bits(component,
RT5645_INT_IRQ_ST, 0x8, 0x8);
snd_soc_component_update_bits(component,
RT5650_4BTN_IL_CMD2, 0x8000, 0x8000);
snd_soc_component_read(component, RT5650_4BTN_IL_CMD1);
pr_debug("%s read %x = %x\n", __func__, RT5650_4BTN_IL_CMD1,
snd_soc_component_read(component, RT5650_4BTN_IL_CMD1));
} else {
snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD2, 0x8000, 0x0);
snd_soc_component_update_bits(component, RT5645_INT_IRQ_ST, 0x8, 0x0);
snd_soc_dapm_disable_pin(dapm, "ADC L power");
snd_soc_dapm_disable_pin(dapm, "ADC R power");
snd_soc_dapm_sync(dapm);
}
}
static int rt5645_jack_detect(struct snd_soc_component *component, int jack_insert)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
unsigned int val;
if (jack_insert) {
regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0206);
/* for jack type detect */
snd_soc_dapm_force_enable_pin(dapm, "LDO2");
snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power");
snd_soc_dapm_sync(dapm);
if (!snd_soc_card_is_instantiated(dapm->card)) {
/* Power up necessary bits for JD if dapm is
not ready yet */
regmap_update_bits(rt5645->regmap, RT5645_PWR_ANLG1,
RT5645_PWR_MB | RT5645_PWR_VREF2,
RT5645_PWR_MB | RT5645_PWR_VREF2);
regmap_update_bits(rt5645->regmap, RT5645_PWR_MIXER,
RT5645_PWR_LDO2, RT5645_PWR_LDO2);
regmap_update_bits(rt5645->regmap, RT5645_PWR_VOL,
RT5645_PWR_MIC_DET, RT5645_PWR_MIC_DET);
}
regmap_write(rt5645->regmap, RT5645_JD_CTRL3, 0x00f0);
regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD);
regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN);
msleep(100);
regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
RT5645_CBJ_MN_JD, 0);
msleep(600);
regmap_read(rt5645->regmap, RT5645_IN1_CTRL3, &val);
val &= 0x7;
dev_dbg(component->dev, "val = %d\n", val);
if ((val == 1 || val == 2) && !rt5645->pdata.no_headset_mic) {
rt5645->jack_type = SND_JACK_HEADSET;
if (rt5645->en_button_func) {
rt5645_enable_push_button_irq(component, true);
}
} else {
snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
snd_soc_dapm_sync(dapm);
rt5645->jack_type = SND_JACK_HEADPHONE;
}
if (rt5645->pdata.level_trigger_irq)
regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
RT5645_JD_1_1_MASK, RT5645_JD_1_1_NOR);
regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0e06);
} else { /* jack out */
rt5645->jack_type = 0;
regmap_update_bits(rt5645->regmap, RT5645_HP_VOL,
RT5645_L_MUTE | RT5645_R_MUTE,
RT5645_L_MUTE | RT5645_R_MUTE);
regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD);
regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
RT5645_CBJ_BST1_EN, 0);
if (rt5645->en_button_func)
rt5645_enable_push_button_irq(component, false);
if (rt5645->pdata.jd_mode == 0)
snd_soc_dapm_disable_pin(dapm, "LDO2");
snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
snd_soc_dapm_sync(dapm);
if (rt5645->pdata.level_trigger_irq)
regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);
}
return rt5645->jack_type;
}
static int rt5645_button_detect(struct snd_soc_component *component)
{
int btn_type, val;
val = snd_soc_component_read(component, RT5650_4BTN_IL_CMD1);
pr_debug("val=0x%x\n", val);
btn_type = val & 0xfff0;
snd_soc_component_write(component, RT5650_4BTN_IL_CMD1, val);
return btn_type;
}
static irqreturn_t rt5645_irq(int irq, void *data);
int rt5645_set_jack_detect(struct snd_soc_component *component,
struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack,
struct snd_soc_jack *btn_jack)
{
struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
rt5645->hp_jack = hp_jack;
rt5645->mic_jack = mic_jack;
rt5645->btn_jack = btn_jack;
if (rt5645->btn_jack && rt5645->codec_type == CODEC_TYPE_RT5650) {
rt5645->en_button_func = true;
regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL1,
RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
}
rt5645_irq(0, rt5645);
return 0;
}
EXPORT_SYMBOL_GPL(rt5645_set_jack_detect);
static int rt5645_component_set_jack(struct snd_soc_component *component,
struct snd_soc_jack *hs_jack, void *data)
{
struct snd_soc_jack *mic_jack = NULL;
struct snd_soc_jack *btn_jack = NULL;
int type;
if (hs_jack) {
type = *(int *)data;
if (type & SND_JACK_MICROPHONE)
mic_jack = hs_jack;
if (type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3))
btn_jack = hs_jack;
}
return rt5645_set_jack_detect(component, hs_jack, mic_jack, btn_jack);
}
static void rt5645_jack_detect_work(struct work_struct *work)
{
struct rt5645_priv *rt5645 =
container_of(work, struct rt5645_priv, jack_detect_work.work);
int val, btn_type, gpio_state = 0, report = 0;
if (!rt5645->component)
return;
switch (rt5645->pdata.jd_mode) {
case 0: /* Not using rt5645 JD */
if (rt5645->gpiod_hp_det) {
gpio_state = gpiod_get_value(rt5645->gpiod_hp_det);
if (rt5645->pdata.inv_hp_pol)
gpio_state ^= 1;
dev_dbg(rt5645->component->dev, "gpio_state = %d\n",
gpio_state);
report = rt5645_jack_detect(rt5645->component, gpio_state);
}
snd_soc_jack_report(rt5645->hp_jack,
report, SND_JACK_HEADPHONE);
snd_soc_jack_report(rt5645->mic_jack,
report, SND_JACK_MICROPHONE);
return;
case 4:
val = snd_soc_component_read(rt5645->component, RT5645_A_JD_CTRL1) & 0x0020;
break;
default: /* read rt5645 jd1_1 status */
val = snd_soc_component_read(rt5645->component, RT5645_INT_IRQ_ST) & 0x1000;
break;
}
if (!val && (rt5645->jack_type == 0)) { /* jack in */
report = rt5645_jack_detect(rt5645->component, 1);
} else if (!val && rt5645->jack_type != 0) {
/* for push button and jack out */
btn_type = 0;
if (snd_soc_component_read(rt5645->component, RT5645_INT_IRQ_ST) & 0x4) {
/* button pressed */
report = SND_JACK_HEADSET;
btn_type = rt5645_button_detect(rt5645->component);
/* rt5650 can report three kinds of button behavior,
one click, double click and hold. However,
currently we will report button pressed/released
event. So all the three button behaviors are
treated as button pressed. */
switch (btn_type) {
case 0x8000:
case 0x4000:
case 0x2000:
report |= SND_JACK_BTN_0;
break;
case 0x1000:
case 0x0800:
case 0x0400:
report |= SND_JACK_BTN_1;
break;
case 0x0200:
case 0x0100:
case 0x0080:
report |= SND_JACK_BTN_2;
break;
case 0x0040:
case 0x0020:
case 0x0010:
report |= SND_JACK_BTN_3;
break;
case 0x0000: /* unpressed */
break;
default:
dev_err(rt5645->component->dev,
"Unexpected button code 0x%04x\n",
btn_type);
break;
}
}
if (btn_type == 0)/* button release */
report = rt5645->jack_type;
else {
mod_timer(&rt5645->btn_check_timer,
msecs_to_jiffies(100));
}
} else {
/* jack out */
report = 0;
snd_soc_component_update_bits(rt5645->component,
RT5645_INT_IRQ_ST, 0x1, 0x0);
rt5645_jack_detect(rt5645->component, 0);
}
snd_soc_jack_report(rt5645->hp_jack, report, SND_JACK_HEADPHONE);
snd_soc_jack_report(rt5645->mic_jack, report, SND_JACK_MICROPHONE);
if (rt5645->en_button_func)
snd_soc_jack_report(rt5645->btn_jack,
report, SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3);
}
static void rt5645_rcclock_work(struct work_struct *work)
{
struct rt5645_priv *rt5645 =
container_of(work, struct rt5645_priv, rcclock_work.work);
regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PD);
}
static irqreturn_t rt5645_irq(int irq, void *data)
{
struct rt5645_priv *rt5645 = data;
queue_delayed_work(system_power_efficient_wq,
&rt5645->jack_detect_work, msecs_to_jiffies(250));
return IRQ_HANDLED;
}
static void rt5645_btn_check_callback(struct timer_list *t)
{
struct rt5645_priv *rt5645 = from_timer(rt5645, t, btn_check_timer);
queue_delayed_work(system_power_efficient_wq,
&rt5645->jack_detect_work, msecs_to_jiffies(5));
}
static int rt5645_probe(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
rt5645->component = component;
switch (rt5645->codec_type) {
case CODEC_TYPE_RT5645:
snd_soc_dapm_new_controls(dapm,
rt5645_specific_dapm_widgets,
ARRAY_SIZE(rt5645_specific_dapm_widgets));
snd_soc_dapm_add_routes(dapm,
rt5645_specific_dapm_routes,
ARRAY_SIZE(rt5645_specific_dapm_routes));
if (rt5645->v_id < 3) {
snd_soc_dapm_add_routes(dapm,
rt5645_old_dapm_routes,
ARRAY_SIZE(rt5645_old_dapm_routes));
}
break;
case CODEC_TYPE_RT5650:
snd_soc_dapm_new_controls(dapm,
rt5650_specific_dapm_widgets,
ARRAY_SIZE(rt5650_specific_dapm_widgets));
snd_soc_dapm_add_routes(dapm,
rt5650_specific_dapm_routes,
ARRAY_SIZE(rt5650_specific_dapm_routes));
break;
}
snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
/* for JD function */
if (rt5645->pdata.jd_mode) {
snd_soc_dapm_force_enable_pin(dapm, "JD Power");
snd_soc_dapm_force_enable_pin(dapm, "LDO2");
snd_soc_dapm_sync(dapm);
}
if (rt5645->pdata.long_name)
component->card->long_name = rt5645->pdata.long_name;
rt5645->eq_param = devm_kcalloc(component->dev,
RT5645_HWEQ_NUM, sizeof(struct rt5645_eq_param_s),
GFP_KERNEL);
if (!rt5645->eq_param)
return -ENOMEM;
return 0;
}
static void rt5645_remove(struct snd_soc_component *component)
{
rt5645_reset(component);
}
#ifdef CONFIG_PM
static int rt5645_suspend(struct snd_soc_component *component)
{
struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
regcache_cache_only(rt5645->regmap, true);
regcache_mark_dirty(rt5645->regmap);
return 0;
}
static int rt5645_resume(struct snd_soc_component *component)
{
struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
regcache_cache_only(rt5645->regmap, false);
regcache_sync(rt5645->regmap);
return 0;
}
#else
#define rt5645_suspend NULL
#define rt5645_resume NULL
#endif
#define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_96000
#define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
static const struct snd_soc_dai_ops rt5645_aif_dai_ops = {
.hw_params = rt5645_hw_params,
.set_fmt = rt5645_set_dai_fmt,
.set_sysclk = rt5645_set_dai_sysclk,
.set_tdm_slot = rt5645_set_tdm_slot,
.set_pll = rt5645_set_dai_pll,
};
static struct snd_soc_dai_driver rt5645_dai[] = {
{
.name = "rt5645-aif1",
.id = RT5645_AIF1,
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT5645_STEREO_RATES,
.formats = RT5645_FORMATS,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 1,
.channels_max = 4,
.rates = RT5645_STEREO_RATES,
.formats = RT5645_FORMATS,
},
.ops = &rt5645_aif_dai_ops,
},
{
.name = "rt5645-aif2",
.id = RT5645_AIF2,
.playback = {
.stream_name = "AIF2 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT5645_STEREO_RATES,
.formats = RT5645_FORMATS,
},
.capture = {
.stream_name = "AIF2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT5645_STEREO_RATES,
.formats = RT5645_FORMATS,
},
.ops = &rt5645_aif_dai_ops,
},
};
static const struct snd_soc_component_driver soc_component_dev_rt5645 = {
.probe = rt5645_probe,
.remove = rt5645_remove,
.suspend = rt5645_suspend,
.resume = rt5645_resume,
.set_bias_level = rt5645_set_bias_level,
.controls = rt5645_snd_controls,
.num_controls = ARRAY_SIZE(rt5645_snd_controls),
.dapm_widgets = rt5645_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt5645_dapm_widgets),
.dapm_routes = rt5645_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(rt5645_dapm_routes),
.set_jack = rt5645_component_set_jack,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config rt5645_regmap = {
.reg_bits = 8,
.val_bits = 16,
.use_single_read = true,
.use_single_write = true,
.max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
RT5645_PR_SPACING),
.volatile_reg = rt5645_volatile_register,
.readable_reg = rt5645_readable_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = rt5645_reg,
.num_reg_defaults = ARRAY_SIZE(rt5645_reg),
.ranges = rt5645_ranges,
.num_ranges = ARRAY_SIZE(rt5645_ranges),
};
static const struct regmap_config rt5650_regmap = {
.reg_bits = 8,
.val_bits = 16,
.use_single_read = true,
.use_single_write = true,
.max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
RT5645_PR_SPACING),
.volatile_reg = rt5645_volatile_register,
.readable_reg = rt5645_readable_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = rt5650_reg,
.num_reg_defaults = ARRAY_SIZE(rt5650_reg),
.ranges = rt5645_ranges,
.num_ranges = ARRAY_SIZE(rt5645_ranges),
};
static const struct regmap_config temp_regmap = {
.name="nocache",
.reg_bits = 8,
.val_bits = 16,
.use_single_read = true,
.use_single_write = true,
.max_register = RT5645_VENDOR_ID2 + 1,
.cache_type = REGCACHE_NONE,
};
static const struct i2c_device_id rt5645_i2c_id[] = {
{ "rt5645", 0 },
{ "rt5650", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id);
#ifdef CONFIG_OF
static const struct of_device_id rt5645_of_match[] = {
{ .compatible = "realtek,rt5645", },
{ .compatible = "realtek,rt5650", },
{ }
};
MODULE_DEVICE_TABLE(of, rt5645_of_match);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id rt5645_acpi_match[] = {
{ "10EC5645", 0 },
{ "10EC5648", 0 },
{ "10EC5650", 0 },
{ "10EC5640", 0 },
{ "10EC3270", 0 },
{},
};
MODULE_DEVICE_TABLE(acpi, rt5645_acpi_match);
#endif
static const struct rt5645_platform_data intel_braswell_platform_data = {
.dmic1_data_pin = RT5645_DMIC1_DISABLE,
.dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
.jd_mode = 3,
};
static const struct rt5645_platform_data buddy_platform_data = {
.dmic1_data_pin = RT5645_DMIC_DATA_GPIO5,
.dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
.jd_mode = 4,
.level_trigger_irq = true,
};
static const struct rt5645_platform_data gpd_win_platform_data = {
.jd_mode = 3,
.inv_jd1_1 = true,
.long_name = "gpd-win-pocket-rt5645",
/* The GPD pocket has a diff. mic, for the win this does not matter. */
.in2_diff = true,
};
static const struct rt5645_platform_data asus_t100ha_platform_data = {
.dmic1_data_pin = RT5645_DMIC_DATA_IN2N,
.dmic2_data_pin = RT5645_DMIC2_DISABLE,
.jd_mode = 3,
.inv_jd1_1 = true,
};
static const struct rt5645_platform_data asus_t101ha_platform_data = {
.dmic1_data_pin = RT5645_DMIC_DATA_IN2N,
.dmic2_data_pin = RT5645_DMIC2_DISABLE,
.jd_mode = 3,
};
static const struct rt5645_platform_data lenovo_ideapad_miix_310_pdata = {
.jd_mode = 3,
.in2_diff = true,
};
static const struct rt5645_platform_data jd_mode3_platform_data = {
.jd_mode = 3,
};
static const struct rt5645_platform_data lattepanda_board_platform_data = {
.jd_mode = 2,
.inv_jd1_1 = true
};
static const struct rt5645_platform_data kahlee_platform_data = {
.dmic1_data_pin = RT5645_DMIC_DATA_GPIO5,
.dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
.jd_mode = 3,
};
static const struct rt5645_platform_data ecs_ef20_platform_data = {
.dmic1_data_pin = RT5645_DMIC1_DISABLE,
.dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
.inv_hp_pol = 1,
};
static const struct acpi_gpio_params ef20_hp_detect = { 1, 0, false };
static const struct acpi_gpio_mapping cht_rt5645_ef20_gpios[] = {
{ "hp-detect-gpios", &ef20_hp_detect, 1 },
{ },
};
static int cht_rt5645_ef20_quirk_cb(const struct dmi_system_id *id)
{
cht_rt5645_gpios = cht_rt5645_ef20_gpios;
return 1;
}
static const struct dmi_system_id dmi_platform_data[] = {
{
.ident = "Chrome Buddy",
.matches = {
DMI_MATCH(DMI_PRODUCT_NAME, "Buddy"),
},
.driver_data = (void *)&buddy_platform_data,
},
{
.ident = "Intel Strago",
.matches = {
DMI_MATCH(DMI_PRODUCT_NAME, "Strago"),
},
.driver_data = (void *)&intel_braswell_platform_data,
},
{
.ident = "Google Chrome",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
},
.driver_data = (void *)&intel_braswell_platform_data,
},
{
.ident = "Google Setzer",
.matches = {
DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"),
},
.driver_data = (void *)&intel_braswell_platform_data,
},
{
.ident = "Microsoft Surface 3",
.matches = {
DMI_MATCH(DMI_PRODUCT_NAME, "Surface 3"),
},
.driver_data = (void *)&intel_braswell_platform_data,
},
{
/*
* Match for the GPDwin which unfortunately uses somewhat
* generic dmi strings, which is why we test for 4 strings.
* Comparing against 23 other byt/cht boards, board_vendor
* and board_name are unique to the GPDwin, where as only one
* other board has the same board_serial and 3 others have
* the same default product_name. Also the GPDwin is the
* only device to have both board_ and product_name not set.
*/
.ident = "GPD Win / Pocket",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
DMI_MATCH(DMI_BOARD_NAME, "Default string"),
DMI_MATCH(DMI_BOARD_SERIAL, "Default string"),
DMI_MATCH(DMI_PRODUCT_NAME, "Default string"),
},
.driver_data = (void *)&gpd_win_platform_data,
},
{
.ident = "ASUS T100HAN",
.matches = {
DMI_EXACT_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
DMI_MATCH(DMI_PRODUCT_NAME, "T100HAN"),
},
.driver_data = (void *)&asus_t100ha_platform_data,
},
{
.ident = "ASUS T101HA",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
DMI_MATCH(DMI_PRODUCT_NAME, "T101HA"),
},
.driver_data = (void *)&asus_t101ha_platform_data,
},
{
.ident = "MINIX Z83-4",
.matches = {
DMI_EXACT_MATCH(DMI_SYS_VENDOR, "MINIX"),
DMI_MATCH(DMI_PRODUCT_NAME, "Z83-4"),
},
.driver_data = (void *)&jd_mode3_platform_data,
},
{
.ident = "Teclast X80 Pro",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "TECLAST"),
DMI_MATCH(DMI_PRODUCT_NAME, "X80 Pro"),
},
.driver_data = (void *)&jd_mode3_platform_data,
},
{
.ident = "Lenovo Ideapad Miix 310",
.matches = {
DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"),
DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "80SG"),
DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "MIIX 310-10ICR"),
},
.driver_data = (void *)&lenovo_ideapad_miix_310_pdata,
},
{
.ident = "Lenovo Ideapad Miix 320",
.matches = {
DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"),
DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "80XF"),
DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "Lenovo MIIX 320-10ICR"),
},
.driver_data = (void *)&intel_braswell_platform_data,
},
{
.ident = "LattePanda board",
.matches = {
DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
DMI_EXACT_MATCH(DMI_BOARD_NAME, "Cherry Trail CR"),
DMI_EXACT_MATCH(DMI_BOARD_VERSION, "Default string"),
},
.driver_data = (void *)&lattepanda_board_platform_data,
},
{
.ident = "Chrome Kahlee",
.matches = {
DMI_MATCH(DMI_PRODUCT_NAME, "Kahlee"),
},
.driver_data = (void *)&kahlee_platform_data,
},
{
.ident = "Medion E1239T",
.matches = {
DMI_EXACT_MATCH(DMI_SYS_VENDOR, "MEDION"),
DMI_MATCH(DMI_PRODUCT_NAME, "E1239T MD60568"),
},
.driver_data = (void *)&intel_braswell_platform_data,
},
{
.ident = "EF20",
.callback = cht_rt5645_ef20_quirk_cb,
.matches = {
DMI_MATCH(DMI_PRODUCT_NAME, "EF20"),
},
.driver_data = (void *)&ecs_ef20_platform_data,
},
{
.ident = "EF20EA",
.callback = cht_rt5645_ef20_quirk_cb,
.matches = {
DMI_MATCH(DMI_PRODUCT_NAME, "EF20EA"),
},
.driver_data = (void *)&ecs_ef20_platform_data,
},
{ }
};
static bool rt5645_check_dp(struct device *dev)
{
if (device_property_present(dev, "realtek,in2-differential") ||
device_property_present(dev, "realtek,dmic1-data-pin") ||
device_property_present(dev, "realtek,dmic2-data-pin") ||
device_property_present(dev, "realtek,jd-mode"))
return true;
return false;
}
static int rt5645_parse_dt(struct rt5645_priv *rt5645, struct device *dev)
{
rt5645->pdata.in2_diff = device_property_read_bool(dev,
"realtek,in2-differential");
device_property_read_u32(dev,
"realtek,dmic1-data-pin", &rt5645->pdata.dmic1_data_pin);
device_property_read_u32(dev,
"realtek,dmic2-data-pin", &rt5645->pdata.dmic2_data_pin);
device_property_read_u32(dev,
"realtek,jd-mode", &rt5645->pdata.jd_mode);
return 0;
}
static int rt5645_i2c_probe(struct i2c_client *i2c)
{
struct rt5645_platform_data *pdata = NULL;
const struct dmi_system_id *dmi_data;
struct rt5645_priv *rt5645;
int ret, i;
unsigned int val;
struct regmap *regmap;
rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv),
GFP_KERNEL);
if (rt5645 == NULL)
return -ENOMEM;
rt5645->i2c = i2c;
i2c_set_clientdata(i2c, rt5645);
dmi_data = dmi_first_match(dmi_platform_data);
if (dmi_data) {
dev_info(&i2c->dev, "Detected %s platform\n", dmi_data->ident);
pdata = dmi_data->driver_data;
}
if (pdata)
rt5645->pdata = *pdata;
else if (rt5645_check_dp(&i2c->dev))
rt5645_parse_dt(rt5645, &i2c->dev);
else
rt5645->pdata = jd_mode3_platform_data;
if (quirk != -1) {
rt5645->pdata.in2_diff = QUIRK_IN2_DIFF(quirk);
rt5645->pdata.level_trigger_irq = QUIRK_LEVEL_IRQ(quirk);
rt5645->pdata.inv_jd1_1 = QUIRK_INV_JD1_1(quirk);
rt5645->pdata.inv_hp_pol = QUIRK_INV_HP_POL(quirk);
rt5645->pdata.jd_mode = QUIRK_JD_MODE(quirk);
rt5645->pdata.dmic1_data_pin = QUIRK_DMIC1_DATA_PIN(quirk);
rt5645->pdata.dmic2_data_pin = QUIRK_DMIC2_DATA_PIN(quirk);
}
if (has_acpi_companion(&i2c->dev)) {
if (cht_rt5645_gpios) {
if (devm_acpi_dev_add_driver_gpios(&i2c->dev, cht_rt5645_gpios))
dev_dbg(&i2c->dev, "Failed to add driver gpios\n");
}
/* The ALC3270 package has the headset-mic pin not-connected */
if (acpi_dev_hid_uid_match(ACPI_COMPANION(&i2c->dev), "10EC3270", NULL))
rt5645->pdata.no_headset_mic = true;
}
rt5645->gpiod_hp_det = devm_gpiod_get_optional(&i2c->dev, "hp-detect",
GPIOD_IN);
if (IS_ERR(rt5645->gpiod_hp_det)) {
dev_info(&i2c->dev, "failed to initialize gpiod\n");
ret = PTR_ERR(rt5645->gpiod_hp_det);
/*
* Continue if optional gpiod is missing, bail for all other
* errors, including -EPROBE_DEFER
*/
if (ret != -ENOENT)
return ret;
}
for (i = 0; i < ARRAY_SIZE(rt5645->supplies); i++)
rt5645->supplies[i].supply = rt5645_supply_names[i];
ret = devm_regulator_bulk_get(&i2c->dev,
ARRAY_SIZE(rt5645->supplies),
rt5645->supplies);
if (ret) {
dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
return ret;
}
ret = regulator_bulk_enable(ARRAY_SIZE(rt5645->supplies),
rt5645->supplies);
if (ret) {
dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
return ret;
}
regmap = devm_regmap_init_i2c(i2c, &temp_regmap);
if (IS_ERR(regmap)) {
ret = PTR_ERR(regmap);
dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n",
ret);
goto err_enable;
}
/*
* Read after 400msec, as it is the interval required between
* read and power On.
*/
msleep(TIME_TO_POWER_MS);
ret = regmap_read(regmap, RT5645_VENDOR_ID2, &val);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to read: 0x%02X\n, ret = %d", RT5645_VENDOR_ID2, ret);
goto err_enable;
}
switch (val) {
case RT5645_DEVICE_ID:
rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap);
rt5645->codec_type = CODEC_TYPE_RT5645;
break;
case RT5650_DEVICE_ID:
rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5650_regmap);
rt5645->codec_type = CODEC_TYPE_RT5650;
break;
default:
dev_err(&i2c->dev,
"Device with ID register %#x is not rt5645 or rt5650\n",
val);
ret = -ENODEV;
goto err_enable;
}
if (IS_ERR(rt5645->regmap)) {
ret = PTR_ERR(rt5645->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
goto err_enable;
}
regmap_write(rt5645->regmap, RT5645_RESET, 0);
regmap_read(regmap, RT5645_VENDOR_ID, &val);
rt5645->v_id = val & 0xff;
regmap_write(rt5645->regmap, RT5645_AD_DA_MIXER, 0x8080);
ret = regmap_multi_reg_write(rt5645->regmap, init_list,
ARRAY_SIZE(init_list));
if (ret != 0)
dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
if (rt5645->codec_type == CODEC_TYPE_RT5650) {
ret = regmap_multi_reg_write(rt5645->regmap, rt5650_init_list,
ARRAY_SIZE(rt5650_init_list));
if (ret != 0)
dev_warn(&i2c->dev, "Apply rt5650 patch failed: %d\n",
ret);
}
regmap_update_bits(rt5645->regmap, RT5645_CLSD_OUT_CTRL, 0xc0, 0xc0);
if (rt5645->pdata.in2_diff)
regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL,
RT5645_IN_DF2, RT5645_IN_DF2);
if (rt5645->pdata.dmic1_data_pin || rt5645->pdata.dmic2_data_pin) {
regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL);
}
switch (rt5645->pdata.dmic1_data_pin) {
case RT5645_DMIC_DATA_IN2N:
regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N);
break;
case RT5645_DMIC_DATA_GPIO5:
regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
RT5645_I2S2_DAC_PIN_MASK, RT5645_I2S2_DAC_PIN_GPIO);
regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5);
regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA);
break;
case RT5645_DMIC_DATA_GPIO11:
regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11);
regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
RT5645_GP11_PIN_MASK,
RT5645_GP11_PIN_DMIC1_SDA);
break;
default:
break;
}
switch (rt5645->pdata.dmic2_data_pin) {
case RT5645_DMIC_DATA_IN2P:
regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P);
break;
case RT5645_DMIC_DATA_GPIO6:
regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6);
regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA);
break;
case RT5645_DMIC_DATA_GPIO10:
regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10);
regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
RT5645_GP10_PIN_MASK,
RT5645_GP10_PIN_DMIC2_SDA);
break;
case RT5645_DMIC_DATA_GPIO12:
regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO12);
regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
RT5645_GP12_PIN_MASK,
RT5645_GP12_PIN_DMIC2_SDA);
break;
default:
break;
}
if (rt5645->pdata.jd_mode) {
regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
RT5645_IRQ_CLK_GATE_CTRL,
RT5645_IRQ_CLK_GATE_CTRL);
regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT);
regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN);
regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE);
regmap_update_bits(rt5645->regmap, RT5645_HPO_MIXER,
RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE);
regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN);
regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
switch (rt5645->pdata.jd_mode) {
case 1:
regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
RT5645_JD1_MODE_MASK,
RT5645_JD1_MODE_0);
break;
case 2:
regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
RT5645_JD1_MODE_MASK,
RT5645_JD1_MODE_1);
break;
case 3:
case 4:
regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
RT5645_JD1_MODE_MASK,
RT5645_JD1_MODE_2);
break;
default:
break;
}
if (rt5645->pdata.inv_jd1_1) {
regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);
}
}
regmap_update_bits(rt5645->regmap, RT5645_ADDA_CLK1,
RT5645_I2S_PD1_MASK, RT5645_I2S_PD1_2);
if (rt5645->pdata.level_trigger_irq) {
regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);
}
timer_setup(&rt5645->btn_check_timer, rt5645_btn_check_callback, 0);
INIT_DELAYED_WORK(&rt5645->jack_detect_work, rt5645_jack_detect_work);
INIT_DELAYED_WORK(&rt5645->rcclock_work, rt5645_rcclock_work);
if (rt5645->i2c->irq) {
ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq,
IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
| IRQF_ONESHOT, "rt5645", rt5645);
if (ret) {
dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
goto err_enable;
}
}
ret = devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_rt5645,
rt5645_dai, ARRAY_SIZE(rt5645_dai));
if (ret)
goto err_irq;
return 0;
err_irq:
if (rt5645->i2c->irq)
free_irq(rt5645->i2c->irq, rt5645);
err_enable:
regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies);
return ret;
}
static void rt5645_i2c_remove(struct i2c_client *i2c)
{
struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);
if (i2c->irq)
free_irq(i2c->irq, rt5645);
/*
* Since the rt5645_btn_check_callback() can queue jack_detect_work,
* the timer need to be delted first
*/
del_timer_sync(&rt5645->btn_check_timer);
cancel_delayed_work_sync(&rt5645->jack_detect_work);
cancel_delayed_work_sync(&rt5645->rcclock_work);
regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies);
}
static void rt5645_i2c_shutdown(struct i2c_client *i2c)
{
struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);
regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
RT5645_RING2_SLEEVE_GND, RT5645_RING2_SLEEVE_GND);
regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, RT5645_CBJ_MN_JD,
RT5645_CBJ_MN_JD);
regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, RT5645_CBJ_BST1_EN,
0);
msleep(20);
regmap_write(rt5645->regmap, RT5645_RESET, 0);
}
static int __maybe_unused rt5645_sys_suspend(struct device *dev)
{
struct rt5645_priv *rt5645 = dev_get_drvdata(dev);
del_timer_sync(&rt5645->btn_check_timer);
cancel_delayed_work_sync(&rt5645->jack_detect_work);
cancel_delayed_work_sync(&rt5645->rcclock_work);
regcache_cache_only(rt5645->regmap, true);
regcache_mark_dirty(rt5645->regmap);
return 0;
}
static int __maybe_unused rt5645_sys_resume(struct device *dev)
{
struct rt5645_priv *rt5645 = dev_get_drvdata(dev);
regcache_cache_only(rt5645->regmap, false);
regcache_sync(rt5645->regmap);
if (rt5645->hp_jack) {
rt5645->jack_type = 0;
rt5645_jack_detect_work(&rt5645->jack_detect_work.work);
}
return 0;
}
static const struct dev_pm_ops rt5645_pm = {
SET_SYSTEM_SLEEP_PM_OPS(rt5645_sys_suspend, rt5645_sys_resume)
};
static struct i2c_driver rt5645_i2c_driver = {
.driver = {
.name = "rt5645",
.of_match_table = of_match_ptr(rt5645_of_match),
.acpi_match_table = ACPI_PTR(rt5645_acpi_match),
.pm = &rt5645_pm,
},
.probe = rt5645_i2c_probe,
.remove = rt5645_i2c_remove,
.shutdown = rt5645_i2c_shutdown,
.id_table = rt5645_i2c_id,
};
module_i2c_driver(rt5645_i2c_driver);
MODULE_DESCRIPTION("ASoC RT5645 driver");
MODULE_AUTHOR("Bard Liao <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/rt5645.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8974.c -- WM8974 ALSA Soc Audio driver
*
* Copyright 2006-2009 Wolfson Microelectronics PLC.
*
* Author: Liam Girdwood <[email protected]>
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "wm8974.h"
struct wm8974_priv {
unsigned int mclk;
unsigned int fs;
};
static const struct reg_default wm8974_reg_defaults[] = {
{ 0, 0x0000 }, { 1, 0x0000 }, { 2, 0x0000 }, { 3, 0x0000 },
{ 4, 0x0050 }, { 5, 0x0000 }, { 6, 0x0140 }, { 7, 0x0000 },
{ 8, 0x0000 }, { 9, 0x0000 }, { 10, 0x0000 }, { 11, 0x00ff },
{ 12, 0x0000 }, { 13, 0x0000 }, { 14, 0x0100 }, { 15, 0x00ff },
{ 16, 0x0000 }, { 17, 0x0000 }, { 18, 0x012c }, { 19, 0x002c },
{ 20, 0x002c }, { 21, 0x002c }, { 22, 0x002c }, { 23, 0x0000 },
{ 24, 0x0032 }, { 25, 0x0000 }, { 26, 0x0000 }, { 27, 0x0000 },
{ 28, 0x0000 }, { 29, 0x0000 }, { 30, 0x0000 }, { 31, 0x0000 },
{ 32, 0x0038 }, { 33, 0x000b }, { 34, 0x0032 }, { 35, 0x0000 },
{ 36, 0x0008 }, { 37, 0x000c }, { 38, 0x0093 }, { 39, 0x00e9 },
{ 40, 0x0000 }, { 41, 0x0000 }, { 42, 0x0000 }, { 43, 0x0000 },
{ 44, 0x0003 }, { 45, 0x0010 }, { 46, 0x0000 }, { 47, 0x0000 },
{ 48, 0x0000 }, { 49, 0x0002 }, { 50, 0x0000 }, { 51, 0x0000 },
{ 52, 0x0000 }, { 53, 0x0000 }, { 54, 0x0039 }, { 55, 0x0000 },
{ 56, 0x0000 },
};
#define WM8974_POWER1_BIASEN 0x08
#define WM8974_POWER1_BUFIOEN 0x04
#define wm8974_reset(c) snd_soc_component_write(c, WM8974_RESET, 0)
static const char *wm8974_companding[] = {"Off", "NC", "u-law", "A-law" };
static const char *wm8974_deemp[] = {"None", "32kHz", "44.1kHz", "48kHz" };
static const char *wm8974_eqmode[] = {"Capture", "Playback" };
static const char *wm8974_bw[] = {"Narrow", "Wide" };
static const char *wm8974_eq1[] = {"80Hz", "105Hz", "135Hz", "175Hz" };
static const char *wm8974_eq2[] = {"230Hz", "300Hz", "385Hz", "500Hz" };
static const char *wm8974_eq3[] = {"650Hz", "850Hz", "1.1kHz", "1.4kHz" };
static const char *wm8974_eq4[] = {"1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz" };
static const char *wm8974_eq5[] = {"5.3kHz", "6.9kHz", "9kHz", "11.7kHz" };
static const char *wm8974_alc[] = {"ALC", "Limiter" };
static const struct soc_enum wm8974_enum[] = {
SOC_ENUM_SINGLE(WM8974_COMP, 1, 4, wm8974_companding), /* adc */
SOC_ENUM_SINGLE(WM8974_COMP, 3, 4, wm8974_companding), /* dac */
SOC_ENUM_SINGLE(WM8974_DAC, 4, 4, wm8974_deemp),
SOC_ENUM_SINGLE(WM8974_EQ1, 8, 2, wm8974_eqmode),
SOC_ENUM_SINGLE(WM8974_EQ1, 5, 4, wm8974_eq1),
SOC_ENUM_SINGLE(WM8974_EQ2, 8, 2, wm8974_bw),
SOC_ENUM_SINGLE(WM8974_EQ2, 5, 4, wm8974_eq2),
SOC_ENUM_SINGLE(WM8974_EQ3, 8, 2, wm8974_bw),
SOC_ENUM_SINGLE(WM8974_EQ3, 5, 4, wm8974_eq3),
SOC_ENUM_SINGLE(WM8974_EQ4, 8, 2, wm8974_bw),
SOC_ENUM_SINGLE(WM8974_EQ4, 5, 4, wm8974_eq4),
SOC_ENUM_SINGLE(WM8974_EQ5, 8, 2, wm8974_bw),
SOC_ENUM_SINGLE(WM8974_EQ5, 5, 4, wm8974_eq5),
SOC_ENUM_SINGLE(WM8974_ALC3, 8, 2, wm8974_alc),
};
static const char *wm8974_auxmode_text[] = { "Buffer", "Mixer" };
static SOC_ENUM_SINGLE_DECL(wm8974_auxmode,
WM8974_INPUT, 3, wm8974_auxmode_text);
static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0);
static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0);
static const struct snd_kcontrol_new wm8974_snd_controls[] = {
SOC_SINGLE("Digital Loopback Switch", WM8974_COMP, 0, 1, 0),
SOC_ENUM("DAC Companding", wm8974_enum[1]),
SOC_ENUM("ADC Companding", wm8974_enum[0]),
SOC_ENUM("Playback De-emphasis", wm8974_enum[2]),
SOC_SINGLE("DAC Inversion Switch", WM8974_DAC, 0, 1, 0),
SOC_SINGLE_TLV("PCM Volume", WM8974_DACVOL, 0, 255, 0, digital_tlv),
SOC_SINGLE("High Pass Filter Switch", WM8974_ADC, 8, 1, 0),
SOC_SINGLE("High Pass Cut Off", WM8974_ADC, 4, 7, 0),
SOC_SINGLE("ADC Inversion Switch", WM8974_ADC, 0, 1, 0),
SOC_SINGLE_TLV("Capture Volume", WM8974_ADCVOL, 0, 255, 0, digital_tlv),
SOC_ENUM("Equaliser Function", wm8974_enum[3]),
SOC_ENUM("EQ1 Cut Off", wm8974_enum[4]),
SOC_SINGLE_TLV("EQ1 Volume", WM8974_EQ1, 0, 24, 1, eq_tlv),
SOC_ENUM("Equaliser EQ2 Bandwidth", wm8974_enum[5]),
SOC_ENUM("EQ2 Cut Off", wm8974_enum[6]),
SOC_SINGLE_TLV("EQ2 Volume", WM8974_EQ2, 0, 24, 1, eq_tlv),
SOC_ENUM("Equaliser EQ3 Bandwidth", wm8974_enum[7]),
SOC_ENUM("EQ3 Cut Off", wm8974_enum[8]),
SOC_SINGLE_TLV("EQ3 Volume", WM8974_EQ3, 0, 24, 1, eq_tlv),
SOC_ENUM("Equaliser EQ4 Bandwidth", wm8974_enum[9]),
SOC_ENUM("EQ4 Cut Off", wm8974_enum[10]),
SOC_SINGLE_TLV("EQ4 Volume", WM8974_EQ4, 0, 24, 1, eq_tlv),
SOC_ENUM("Equaliser EQ5 Bandwidth", wm8974_enum[11]),
SOC_ENUM("EQ5 Cut Off", wm8974_enum[12]),
SOC_SINGLE_TLV("EQ5 Volume", WM8974_EQ5, 0, 24, 1, eq_tlv),
SOC_SINGLE("DAC Playback Limiter Switch", WM8974_DACLIM1, 8, 1, 0),
SOC_SINGLE("DAC Playback Limiter Decay", WM8974_DACLIM1, 4, 15, 0),
SOC_SINGLE("DAC Playback Limiter Attack", WM8974_DACLIM1, 0, 15, 0),
SOC_SINGLE("DAC Playback Limiter Threshold", WM8974_DACLIM2, 4, 7, 0),
SOC_SINGLE("DAC Playback Limiter Boost", WM8974_DACLIM2, 0, 15, 0),
SOC_SINGLE("ALC Enable Switch", WM8974_ALC1, 8, 1, 0),
SOC_SINGLE("ALC Capture Max Gain", WM8974_ALC1, 3, 7, 0),
SOC_SINGLE("ALC Capture Min Gain", WM8974_ALC1, 0, 7, 0),
SOC_SINGLE("ALC Capture ZC Switch", WM8974_ALC2, 8, 1, 0),
SOC_SINGLE("ALC Capture Hold", WM8974_ALC2, 4, 7, 0),
SOC_SINGLE("ALC Capture Target", WM8974_ALC2, 0, 15, 0),
SOC_ENUM("ALC Capture Mode", wm8974_enum[13]),
SOC_SINGLE("ALC Capture Decay", WM8974_ALC3, 4, 15, 0),
SOC_SINGLE("ALC Capture Attack", WM8974_ALC3, 0, 15, 0),
SOC_SINGLE("ALC Capture Noise Gate Switch", WM8974_NGATE, 3, 1, 0),
SOC_SINGLE("ALC Capture Noise Gate Threshold", WM8974_NGATE, 0, 7, 0),
SOC_SINGLE("Capture PGA ZC Switch", WM8974_INPPGA, 7, 1, 0),
SOC_SINGLE_TLV("Capture PGA Volume", WM8974_INPPGA, 0, 63, 0, inpga_tlv),
SOC_SINGLE("Speaker Playback ZC Switch", WM8974_SPKVOL, 7, 1, 0),
SOC_SINGLE("Speaker Playback Switch", WM8974_SPKVOL, 6, 1, 1),
SOC_SINGLE_TLV("Speaker Playback Volume", WM8974_SPKVOL, 0, 63, 0, spk_tlv),
SOC_ENUM("Aux Mode", wm8974_auxmode),
SOC_SINGLE("Capture Boost(+20dB)", WM8974_ADCBOOST, 8, 1, 0),
SOC_SINGLE("Mono Playback Switch", WM8974_MONOMIX, 6, 1, 1),
/* DAC / ADC oversampling */
SOC_SINGLE("DAC 128x Oversampling Switch", WM8974_DAC, 8, 1, 0),
SOC_SINGLE("ADC 128x Oversampling Switch", WM8974_ADC, 8, 1, 0),
};
/* Speaker Output Mixer */
static const struct snd_kcontrol_new wm8974_speaker_mixer_controls[] = {
SOC_DAPM_SINGLE("Line Bypass Switch", WM8974_SPKMIX, 1, 1, 0),
SOC_DAPM_SINGLE("Aux Playback Switch", WM8974_SPKMIX, 5, 1, 0),
SOC_DAPM_SINGLE("PCM Playback Switch", WM8974_SPKMIX, 0, 1, 0),
};
/* Mono Output Mixer */
static const struct snd_kcontrol_new wm8974_mono_mixer_controls[] = {
SOC_DAPM_SINGLE("Line Bypass Switch", WM8974_MONOMIX, 1, 1, 0),
SOC_DAPM_SINGLE("Aux Playback Switch", WM8974_MONOMIX, 2, 1, 0),
SOC_DAPM_SINGLE("PCM Playback Switch", WM8974_MONOMIX, 0, 1, 0),
};
/* Boost mixer */
static const struct snd_kcontrol_new wm8974_boost_mixer[] = {
SOC_DAPM_SINGLE("Aux Switch", WM8974_INPPGA, 6, 1, 1),
};
/* Input PGA */
static const struct snd_kcontrol_new wm8974_inpga[] = {
SOC_DAPM_SINGLE("Aux Switch", WM8974_INPUT, 2, 1, 0),
SOC_DAPM_SINGLE("MicN Switch", WM8974_INPUT, 1, 1, 0),
SOC_DAPM_SINGLE("MicP Switch", WM8974_INPUT, 0, 1, 0),
};
static const struct snd_soc_dapm_widget wm8974_dapm_widgets[] = {
SND_SOC_DAPM_MIXER("Speaker Mixer", WM8974_POWER3, 2, 0,
&wm8974_speaker_mixer_controls[0],
ARRAY_SIZE(wm8974_speaker_mixer_controls)),
SND_SOC_DAPM_MIXER("Mono Mixer", WM8974_POWER3, 3, 0,
&wm8974_mono_mixer_controls[0],
ARRAY_SIZE(wm8974_mono_mixer_controls)),
SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM8974_POWER3, 0, 0),
SND_SOC_DAPM_ADC("ADC", "HiFi Capture", WM8974_POWER2, 0, 0),
SND_SOC_DAPM_PGA("Aux Input", WM8974_POWER1, 6, 0, NULL, 0),
SND_SOC_DAPM_PGA("SpkN Out", WM8974_POWER3, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA("SpkP Out", WM8974_POWER3, 6, 0, NULL, 0),
SND_SOC_DAPM_PGA("Mono Out", WM8974_POWER3, 7, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Input PGA", WM8974_POWER2, 2, 0, wm8974_inpga,
ARRAY_SIZE(wm8974_inpga)),
SND_SOC_DAPM_MIXER("Boost Mixer", WM8974_POWER2, 4, 0,
wm8974_boost_mixer, ARRAY_SIZE(wm8974_boost_mixer)),
SND_SOC_DAPM_SUPPLY("Mic Bias", WM8974_POWER1, 4, 0, NULL, 0),
SND_SOC_DAPM_INPUT("MICN"),
SND_SOC_DAPM_INPUT("MICP"),
SND_SOC_DAPM_INPUT("AUX"),
SND_SOC_DAPM_OUTPUT("MONOOUT"),
SND_SOC_DAPM_OUTPUT("SPKOUTP"),
SND_SOC_DAPM_OUTPUT("SPKOUTN"),
};
static const struct snd_soc_dapm_route wm8974_dapm_routes[] = {
/* Mono output mixer */
{"Mono Mixer", "PCM Playback Switch", "DAC"},
{"Mono Mixer", "Aux Playback Switch", "Aux Input"},
{"Mono Mixer", "Line Bypass Switch", "Boost Mixer"},
/* Speaker output mixer */
{"Speaker Mixer", "PCM Playback Switch", "DAC"},
{"Speaker Mixer", "Aux Playback Switch", "Aux Input"},
{"Speaker Mixer", "Line Bypass Switch", "Boost Mixer"},
/* Outputs */
{"Mono Out", NULL, "Mono Mixer"},
{"MONOOUT", NULL, "Mono Out"},
{"SpkN Out", NULL, "Speaker Mixer"},
{"SpkP Out", NULL, "Speaker Mixer"},
{"SPKOUTN", NULL, "SpkN Out"},
{"SPKOUTP", NULL, "SpkP Out"},
/* Boost Mixer */
{"ADC", NULL, "Boost Mixer"},
{"Boost Mixer", "Aux Switch", "Aux Input"},
{"Boost Mixer", NULL, "Input PGA"},
{"Boost Mixer", NULL, "MICP"},
/* Input PGA */
{"Input PGA", "Aux Switch", "Aux Input"},
{"Input PGA", "MicN Switch", "MICN"},
{"Input PGA", "MicP Switch", "MICP"},
/* Inputs */
{"Aux Input", NULL, "AUX"},
};
struct pll_ {
unsigned int pre_div:1;
unsigned int n:4;
unsigned int k;
};
/* The size in bits of the pll divide multiplied by 10
* to allow rounding later */
#define FIXED_PLL_SIZE ((1 << 24) * 10)
static void pll_factors(struct pll_ *pll_div,
unsigned int target, unsigned int source)
{
unsigned long long Kpart;
unsigned int K, Ndiv, Nmod;
/* There is a fixed divide by 4 in the output path */
target *= 4;
Ndiv = target / source;
if (Ndiv < 6) {
source /= 2;
pll_div->pre_div = 1;
Ndiv = target / source;
} else
pll_div->pre_div = 0;
if ((Ndiv < 6) || (Ndiv > 12))
printk(KERN_WARNING
"WM8974 N value %u outwith recommended range!\n",
Ndiv);
pll_div->n = Ndiv;
Nmod = target % source;
Kpart = FIXED_PLL_SIZE * (long long)Nmod;
do_div(Kpart, source);
K = Kpart & 0xFFFFFFFF;
/* Check if we need to round */
if ((K % 10) >= 5)
K += 5;
/* Move down to proper range now rounding is done */
K /= 10;
pll_div->k = K;
}
static int wm8974_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
int source, unsigned int freq_in, unsigned int freq_out)
{
struct snd_soc_component *component = codec_dai->component;
struct pll_ pll_div;
u16 reg;
if (freq_in == 0 || freq_out == 0) {
/* Clock CODEC directly from MCLK */
reg = snd_soc_component_read(component, WM8974_CLOCK);
snd_soc_component_write(component, WM8974_CLOCK, reg & 0x0ff);
/* Turn off PLL */
reg = snd_soc_component_read(component, WM8974_POWER1);
snd_soc_component_write(component, WM8974_POWER1, reg & 0x1df);
return 0;
}
pll_factors(&pll_div, freq_out, freq_in);
snd_soc_component_write(component, WM8974_PLLN, (pll_div.pre_div << 4) | pll_div.n);
snd_soc_component_write(component, WM8974_PLLK1, pll_div.k >> 18);
snd_soc_component_write(component, WM8974_PLLK2, (pll_div.k >> 9) & 0x1ff);
snd_soc_component_write(component, WM8974_PLLK3, pll_div.k & 0x1ff);
reg = snd_soc_component_read(component, WM8974_POWER1);
snd_soc_component_write(component, WM8974_POWER1, reg | 0x020);
/* Run CODEC from PLL instead of MCLK */
reg = snd_soc_component_read(component, WM8974_CLOCK);
snd_soc_component_write(component, WM8974_CLOCK, reg | 0x100);
return 0;
}
/*
* Configure WM8974 clock dividers.
*/
static int wm8974_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
int div_id, int div)
{
struct snd_soc_component *component = codec_dai->component;
u16 reg;
switch (div_id) {
case WM8974_OPCLKDIV:
reg = snd_soc_component_read(component, WM8974_GPIO) & 0x1cf;
snd_soc_component_write(component, WM8974_GPIO, reg | div);
break;
case WM8974_MCLKDIV:
reg = snd_soc_component_read(component, WM8974_CLOCK) & 0x11f;
snd_soc_component_write(component, WM8974_CLOCK, reg | div);
break;
case WM8974_BCLKDIV:
reg = snd_soc_component_read(component, WM8974_CLOCK) & 0x1e3;
snd_soc_component_write(component, WM8974_CLOCK, reg | div);
break;
default:
return -EINVAL;
}
return 0;
}
static unsigned int wm8974_get_mclkdiv(unsigned int f_in, unsigned int f_out,
int *mclkdiv)
{
unsigned int ratio = 2 * f_in / f_out;
if (ratio <= 2) {
*mclkdiv = WM8974_MCLKDIV_1;
ratio = 2;
} else if (ratio == 3) {
*mclkdiv = WM8974_MCLKDIV_1_5;
} else if (ratio == 4) {
*mclkdiv = WM8974_MCLKDIV_2;
} else if (ratio <= 6) {
*mclkdiv = WM8974_MCLKDIV_3;
ratio = 6;
} else if (ratio <= 8) {
*mclkdiv = WM8974_MCLKDIV_4;
ratio = 8;
} else if (ratio <= 12) {
*mclkdiv = WM8974_MCLKDIV_6;
ratio = 12;
} else if (ratio <= 16) {
*mclkdiv = WM8974_MCLKDIV_8;
ratio = 16;
} else {
*mclkdiv = WM8974_MCLKDIV_12;
ratio = 24;
}
return f_out * ratio / 2;
}
static int wm8974_update_clocks(struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm8974_priv *priv = snd_soc_component_get_drvdata(component);
unsigned int fs256;
unsigned int fpll = 0;
unsigned int f;
int mclkdiv;
if (!priv->mclk || !priv->fs)
return 0;
fs256 = 256 * priv->fs;
f = wm8974_get_mclkdiv(priv->mclk, fs256, &mclkdiv);
if (f != priv->mclk) {
/* The PLL performs best around 90MHz */
fpll = wm8974_get_mclkdiv(22500000, fs256, &mclkdiv);
}
wm8974_set_dai_pll(dai, 0, 0, priv->mclk, fpll);
wm8974_set_dai_clkdiv(dai, WM8974_MCLKDIV, mclkdiv);
return 0;
}
static int wm8974_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct wm8974_priv *priv = snd_soc_component_get_drvdata(component);
if (dir != SND_SOC_CLOCK_IN)
return -EINVAL;
priv->mclk = freq;
return wm8974_update_clocks(dai);
}
static int wm8974_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
u16 iface = 0;
u16 clk = snd_soc_component_read(component, WM8974_CLOCK) & 0x1fe;
/* set master/slave audio interface */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
clk |= 0x0001;
break;
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface |= 0x0010;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
iface |= 0x0008;
break;
case SND_SOC_DAIFMT_DSP_A:
if ((fmt & SND_SOC_DAIFMT_INV_MASK) == SND_SOC_DAIFMT_IB_IF ||
(fmt & SND_SOC_DAIFMT_INV_MASK) == SND_SOC_DAIFMT_NB_IF) {
return -EINVAL;
}
iface |= 0x00018;
break;
default:
return -EINVAL;
}
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
iface |= 0x0180;
break;
case SND_SOC_DAIFMT_IB_NF:
iface |= 0x0100;
break;
case SND_SOC_DAIFMT_NB_IF:
iface |= 0x0080;
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, WM8974_IFACE, iface);
snd_soc_component_write(component, WM8974_CLOCK, clk);
return 0;
}
static int wm8974_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm8974_priv *priv = snd_soc_component_get_drvdata(component);
u16 iface = snd_soc_component_read(component, WM8974_IFACE) & 0x19f;
u16 adn = snd_soc_component_read(component, WM8974_ADD) & 0x1f1;
int err;
priv->fs = params_rate(params);
err = wm8974_update_clocks(dai);
if (err)
return err;
/* bit size */
switch (params_width(params)) {
case 16:
break;
case 20:
iface |= 0x0020;
break;
case 24:
iface |= 0x0040;
break;
case 32:
iface |= 0x0060;
break;
}
/* filter coefficient */
switch (params_rate(params)) {
case 8000:
adn |= 0x5 << 1;
break;
case 11025:
adn |= 0x4 << 1;
break;
case 16000:
adn |= 0x3 << 1;
break;
case 22050:
adn |= 0x2 << 1;
break;
case 32000:
adn |= 0x1 << 1;
break;
case 44100:
case 48000:
break;
}
snd_soc_component_write(component, WM8974_IFACE, iface);
snd_soc_component_write(component, WM8974_ADD, adn);
return 0;
}
static int wm8974_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
u16 mute_reg = snd_soc_component_read(component, WM8974_DAC) & 0xffbf;
if (mute)
snd_soc_component_write(component, WM8974_DAC, mute_reg | 0x40);
else
snd_soc_component_write(component, WM8974_DAC, mute_reg);
return 0;
}
/* liam need to make this lower power with dapm */
static int wm8974_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
u16 power1 = snd_soc_component_read(component, WM8974_POWER1) & ~0x3;
switch (level) {
case SND_SOC_BIAS_ON:
case SND_SOC_BIAS_PREPARE:
power1 |= 0x1; /* VMID 50k */
snd_soc_component_write(component, WM8974_POWER1, power1);
break;
case SND_SOC_BIAS_STANDBY:
power1 |= WM8974_POWER1_BIASEN | WM8974_POWER1_BUFIOEN;
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
regcache_sync(dev_get_regmap(component->dev, NULL));
/* Initial cap charge at VMID 5k */
snd_soc_component_write(component, WM8974_POWER1, power1 | 0x3);
mdelay(100);
}
power1 |= 0x2; /* VMID 500k */
snd_soc_component_write(component, WM8974_POWER1, power1);
break;
case SND_SOC_BIAS_OFF:
snd_soc_component_write(component, WM8974_POWER1, 0);
snd_soc_component_write(component, WM8974_POWER2, 0);
snd_soc_component_write(component, WM8974_POWER3, 0);
break;
}
return 0;
}
#define WM8974_RATES (SNDRV_PCM_RATE_8000_48000)
#define WM8974_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE)
static const struct snd_soc_dai_ops wm8974_ops = {
.hw_params = wm8974_pcm_hw_params,
.mute_stream = wm8974_mute,
.set_fmt = wm8974_set_dai_fmt,
.set_clkdiv = wm8974_set_dai_clkdiv,
.set_pll = wm8974_set_dai_pll,
.set_sysclk = wm8974_set_dai_sysclk,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver wm8974_dai = {
.name = "wm8974-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2, /* Only 1 channel of data */
.rates = WM8974_RATES,
.formats = WM8974_FORMATS,},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2, /* Only 1 channel of data */
.rates = WM8974_RATES,
.formats = WM8974_FORMATS,},
.ops = &wm8974_ops,
.symmetric_rate = 1,
};
static const struct regmap_config wm8974_regmap = {
.reg_bits = 7,
.val_bits = 9,
.max_register = WM8974_MONOMIX,
.reg_defaults = wm8974_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8974_reg_defaults),
.cache_type = REGCACHE_FLAT,
};
static int wm8974_probe(struct snd_soc_component *component)
{
int ret = 0;
ret = wm8974_reset(component);
if (ret < 0) {
dev_err(component->dev, "Failed to issue reset\n");
return ret;
}
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_wm8974 = {
.probe = wm8974_probe,
.set_bias_level = wm8974_set_bias_level,
.controls = wm8974_snd_controls,
.num_controls = ARRAY_SIZE(wm8974_snd_controls),
.dapm_widgets = wm8974_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8974_dapm_widgets),
.dapm_routes = wm8974_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(wm8974_dapm_routes),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int wm8974_i2c_probe(struct i2c_client *i2c)
{
struct wm8974_priv *priv;
struct regmap *regmap;
int ret;
priv = devm_kzalloc(&i2c->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
i2c_set_clientdata(i2c, priv);
regmap = devm_regmap_init_i2c(i2c, &wm8974_regmap);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_wm8974, &wm8974_dai, 1);
return ret;
}
static const struct i2c_device_id wm8974_i2c_id[] = {
{ "wm8974", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8974_i2c_id);
static const struct of_device_id wm8974_of_match[] = {
{ .compatible = "wlf,wm8974", },
{ }
};
MODULE_DEVICE_TABLE(of, wm8974_of_match);
static struct i2c_driver wm8974_i2c_driver = {
.driver = {
.name = "wm8974",
.of_match_table = wm8974_of_match,
},
.probe = wm8974_i2c_probe,
.id_table = wm8974_i2c_id,
};
module_i2c_driver(wm8974_i2c_driver);
MODULE_DESCRIPTION("ASoC WM8974 driver");
MODULE_AUTHOR("Liam Girdwood");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8974.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* AD1938/AD1939 audio driver
*
* Copyright 2014 Analog Devices Inc.
*/
#include <linux/module.h>
#include <linux/spi/spi.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include "ad193x.h"
static int ad193x_spi_probe(struct spi_device *spi)
{
const struct spi_device_id *id = spi_get_device_id(spi);
struct regmap_config config;
config = ad193x_regmap_config;
config.val_bits = 8;
config.reg_bits = 16;
config.read_flag_mask = 0x09;
config.write_flag_mask = 0x08;
return ad193x_probe(&spi->dev, devm_regmap_init_spi(spi, &config),
(enum ad193x_type)id->driver_data);
}
static const struct spi_device_id ad193x_spi_id[] = {
{ "ad193x", AD193X },
{ "ad1933", AD1933 },
{ "ad1934", AD1934 },
{ "ad1938", AD193X },
{ "ad1939", AD193X },
{ "adau1328", AD193X },
{ }
};
MODULE_DEVICE_TABLE(spi, ad193x_spi_id);
static struct spi_driver ad193x_spi_driver = {
.driver = {
.name = "ad193x",
},
.probe = ad193x_spi_probe,
.id_table = ad193x_spi_id,
};
module_spi_driver(ad193x_spi_driver);
MODULE_DESCRIPTION("ASoC AD1938/AD1939 audio CODEC driver");
MODULE_AUTHOR("Barry Song <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/ad193x-spi.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for ADAU1381/ADAU1781 codec
*
* Copyright 2011-2013 Analog Devices Inc.
* Author: Lars-Peter Clausen <[email protected]>
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <linux/platform_data/adau17x1.h>
#include "adau17x1.h"
#include "adau1781.h"
#define ADAU1781_DMIC_BEEP_CTRL 0x4008
#define ADAU1781_LEFT_PGA 0x400e
#define ADAU1781_RIGHT_PGA 0x400f
#define ADAU1781_LEFT_PLAYBACK_MIXER 0x401c
#define ADAU1781_RIGHT_PLAYBACK_MIXER 0x401e
#define ADAU1781_MONO_PLAYBACK_MIXER 0x401f
#define ADAU1781_LEFT_LINEOUT 0x4025
#define ADAU1781_RIGHT_LINEOUT 0x4026
#define ADAU1781_SPEAKER 0x4027
#define ADAU1781_BEEP_ZC 0x4028
#define ADAU1781_DEJITTER 0x4032
#define ADAU1781_DIG_PWDN0 0x4080
#define ADAU1781_DIG_PWDN1 0x4081
#define ADAU1781_INPUT_DIFFERNTIAL BIT(3)
#define ADAU1381_FIRMWARE "adau1381.bin"
#define ADAU1781_FIRMWARE "adau1781.bin"
static const struct reg_default adau1781_reg_defaults[] = {
{ ADAU1781_DMIC_BEEP_CTRL, 0x00 },
{ ADAU1781_LEFT_PGA, 0xc7 },
{ ADAU1781_RIGHT_PGA, 0xc7 },
{ ADAU1781_LEFT_PLAYBACK_MIXER, 0x00 },
{ ADAU1781_RIGHT_PLAYBACK_MIXER, 0x00 },
{ ADAU1781_MONO_PLAYBACK_MIXER, 0x00 },
{ ADAU1781_LEFT_LINEOUT, 0x00 },
{ ADAU1781_RIGHT_LINEOUT, 0x00 },
{ ADAU1781_SPEAKER, 0x00 },
{ ADAU1781_BEEP_ZC, 0x19 },
{ ADAU1781_DEJITTER, 0x60 },
{ ADAU1781_DIG_PWDN1, 0x0c },
{ ADAU1781_DIG_PWDN1, 0x00 },
{ ADAU17X1_CLOCK_CONTROL, 0x00 },
{ ADAU17X1_PLL_CONTROL, 0x00 },
{ ADAU17X1_REC_POWER_MGMT, 0x00 },
{ ADAU17X1_MICBIAS, 0x04 },
{ ADAU17X1_SERIAL_PORT0, 0x00 },
{ ADAU17X1_SERIAL_PORT1, 0x00 },
{ ADAU17X1_CONVERTER0, 0x00 },
{ ADAU17X1_CONVERTER1, 0x00 },
{ ADAU17X1_LEFT_INPUT_DIGITAL_VOL, 0x00 },
{ ADAU17X1_RIGHT_INPUT_DIGITAL_VOL, 0x00 },
{ ADAU17X1_ADC_CONTROL, 0x00 },
{ ADAU17X1_PLAY_POWER_MGMT, 0x00 },
{ ADAU17X1_DAC_CONTROL0, 0x00 },
{ ADAU17X1_DAC_CONTROL1, 0x00 },
{ ADAU17X1_DAC_CONTROL2, 0x00 },
{ ADAU17X1_SERIAL_PORT_PAD, 0x00 },
{ ADAU17X1_CONTROL_PORT_PAD0, 0x00 },
{ ADAU17X1_CONTROL_PORT_PAD1, 0x00 },
{ ADAU17X1_DSP_SAMPLING_RATE, 0x01 },
{ ADAU17X1_SERIAL_INPUT_ROUTE, 0x00 },
{ ADAU17X1_SERIAL_OUTPUT_ROUTE, 0x00 },
{ ADAU17X1_DSP_ENABLE, 0x00 },
{ ADAU17X1_DSP_RUN, 0x00 },
{ ADAU17X1_SERIAL_SAMPLING_RATE, 0x00 },
};
static const DECLARE_TLV_DB_SCALE(adau1781_speaker_tlv, 0, 200, 0);
static const DECLARE_TLV_DB_RANGE(adau1781_pga_tlv,
0, 1, TLV_DB_SCALE_ITEM(0, 600, 0),
2, 3, TLV_DB_SCALE_ITEM(1000, 400, 0),
4, 4, TLV_DB_SCALE_ITEM(1700, 0, 0),
5, 7, TLV_DB_SCALE_ITEM(2000, 600, 0)
);
static const DECLARE_TLV_DB_RANGE(adau1781_beep_tlv,
0, 1, TLV_DB_SCALE_ITEM(0, 600, 0),
2, 3, TLV_DB_SCALE_ITEM(1000, 400, 0),
4, 4, TLV_DB_SCALE_ITEM(-2300, 0, 0),
5, 7, TLV_DB_SCALE_ITEM(2000, 600, 0)
);
static const DECLARE_TLV_DB_SCALE(adau1781_sidetone_tlv, -1800, 300, 1);
static const char * const adau1781_speaker_bias_select_text[] = {
"Normal operation", "Power saving", "Enhanced performance",
};
static const char * const adau1781_bias_select_text[] = {
"Normal operation", "Extreme power saving", "Power saving",
"Enhanced performance",
};
static SOC_ENUM_SINGLE_DECL(adau1781_adc_bias_enum,
ADAU17X1_REC_POWER_MGMT, 3, adau1781_bias_select_text);
static SOC_ENUM_SINGLE_DECL(adau1781_speaker_bias_enum,
ADAU17X1_PLAY_POWER_MGMT, 6, adau1781_speaker_bias_select_text);
static SOC_ENUM_SINGLE_DECL(adau1781_dac_bias_enum,
ADAU17X1_PLAY_POWER_MGMT, 4, adau1781_bias_select_text);
static SOC_ENUM_SINGLE_DECL(adau1781_playback_bias_enum,
ADAU17X1_PLAY_POWER_MGMT, 2, adau1781_bias_select_text);
static SOC_ENUM_SINGLE_DECL(adau1781_capture_bias_enum,
ADAU17X1_REC_POWER_MGMT, 1, adau1781_bias_select_text);
static const struct snd_kcontrol_new adau1781_controls[] = {
SOC_SINGLE_TLV("Beep Capture Volume", ADAU1781_DMIC_BEEP_CTRL, 0, 7, 0,
adau1781_beep_tlv),
SOC_DOUBLE_R_TLV("PGA Capture Volume", ADAU1781_LEFT_PGA,
ADAU1781_RIGHT_PGA, 5, 7, 0, adau1781_pga_tlv),
SOC_DOUBLE_R("PGA Capture Switch", ADAU1781_LEFT_PGA,
ADAU1781_RIGHT_PGA, 1, 1, 0),
SOC_DOUBLE_R("Lineout Playback Switch", ADAU1781_LEFT_LINEOUT,
ADAU1781_RIGHT_LINEOUT, 1, 1, 0),
SOC_SINGLE("Beep ZC Switch", ADAU1781_BEEP_ZC, 0, 1, 0),
SOC_SINGLE("Mono Playback Switch", ADAU1781_MONO_PLAYBACK_MIXER,
0, 1, 0),
SOC_SINGLE_TLV("Mono Playback Volume", ADAU1781_SPEAKER, 6, 3, 0,
adau1781_speaker_tlv),
SOC_ENUM("ADC Bias", adau1781_adc_bias_enum),
SOC_ENUM("DAC Bias", adau1781_dac_bias_enum),
SOC_ENUM("Capture Bias", adau1781_capture_bias_enum),
SOC_ENUM("Playback Bias", adau1781_playback_bias_enum),
SOC_ENUM("Speaker Bias", adau1781_speaker_bias_enum),
};
static const struct snd_kcontrol_new adau1781_beep_mixer_controls[] = {
SOC_DAPM_SINGLE("Beep Capture Switch", ADAU1781_DMIC_BEEP_CTRL,
3, 1, 0),
};
static const struct snd_kcontrol_new adau1781_left_mixer_controls[] = {
SOC_DAPM_SINGLE_AUTODISABLE("Switch",
ADAU1781_LEFT_PLAYBACK_MIXER, 5, 1, 0),
SOC_DAPM_SINGLE_TLV("Beep Playback Volume",
ADAU1781_LEFT_PLAYBACK_MIXER, 1, 8, 0, adau1781_sidetone_tlv),
};
static const struct snd_kcontrol_new adau1781_right_mixer_controls[] = {
SOC_DAPM_SINGLE_AUTODISABLE("Switch",
ADAU1781_RIGHT_PLAYBACK_MIXER, 6, 1, 0),
SOC_DAPM_SINGLE_TLV("Beep Playback Volume",
ADAU1781_LEFT_PLAYBACK_MIXER, 1, 8, 0, adau1781_sidetone_tlv),
};
static const struct snd_kcontrol_new adau1781_mono_mixer_controls[] = {
SOC_DAPM_SINGLE_AUTODISABLE("Left Switch",
ADAU1781_MONO_PLAYBACK_MIXER, 7, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("Right Switch",
ADAU1781_MONO_PLAYBACK_MIXER, 6, 1, 0),
SOC_DAPM_SINGLE_TLV("Beep Playback Volume",
ADAU1781_MONO_PLAYBACK_MIXER, 2, 8, 0, adau1781_sidetone_tlv),
};
static int adau1781_dejitter_fixup(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct adau *adau = snd_soc_component_get_drvdata(component);
/* After any power changes have been made the dejitter circuit
* has to be reinitialized. */
regmap_write(adau->regmap, ADAU1781_DEJITTER, 0);
if (!adau->master)
regmap_write(adau->regmap, ADAU1781_DEJITTER, 5);
return 0;
}
static const struct snd_soc_dapm_widget adau1781_dapm_widgets[] = {
SND_SOC_DAPM_PGA("Left PGA", ADAU1781_LEFT_PGA, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right PGA", ADAU1781_RIGHT_PGA, 0, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("Speaker", ADAU1781_SPEAKER, 0, 0, NULL, 0),
SOC_MIXER_NAMED_CTL_ARRAY("Beep Mixer", ADAU17X1_MICBIAS, 4, 0,
adau1781_beep_mixer_controls),
SOC_MIXER_ARRAY("Left Lineout Mixer", SND_SOC_NOPM, 0, 0,
adau1781_left_mixer_controls),
SOC_MIXER_ARRAY("Right Lineout Mixer", SND_SOC_NOPM, 0, 0,
adau1781_right_mixer_controls),
SOC_MIXER_ARRAY("Mono Mixer", SND_SOC_NOPM, 0, 0,
adau1781_mono_mixer_controls),
SND_SOC_DAPM_SUPPLY("Serial Input Routing", ADAU1781_DIG_PWDN0,
2, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Serial Output Routing", ADAU1781_DIG_PWDN0,
3, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Clock Domain Transfer", ADAU1781_DIG_PWDN0,
5, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Serial Ports", ADAU1781_DIG_PWDN0, 4, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC Engine", ADAU1781_DIG_PWDN0, 7, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC Engine", ADAU1781_DIG_PWDN1, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Digital Mic", ADAU1781_DIG_PWDN1, 1, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Sound Engine", ADAU1781_DIG_PWDN0, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, ADAU1781_DIG_PWDN0, 1, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Zero Crossing Detector", ADAU1781_DIG_PWDN1, 2, 0,
NULL, 0),
SND_SOC_DAPM_POST("Dejitter fixup", adau1781_dejitter_fixup),
SND_SOC_DAPM_INPUT("BEEP"),
SND_SOC_DAPM_OUTPUT("AOUTL"),
SND_SOC_DAPM_OUTPUT("AOUTR"),
SND_SOC_DAPM_OUTPUT("SP"),
SND_SOC_DAPM_INPUT("LMIC"),
SND_SOC_DAPM_INPUT("RMIC"),
};
static const struct snd_soc_dapm_route adau1781_dapm_routes[] = {
{ "Left Lineout Mixer", NULL, "Left Playback Enable" },
{ "Right Lineout Mixer", NULL, "Right Playback Enable" },
{ "Left Lineout Mixer", "Beep Playback Volume", "Beep Mixer" },
{ "Left Lineout Mixer", "Switch", "Left DAC" },
{ "Right Lineout Mixer", "Beep Playback Volume", "Beep Mixer" },
{ "Right Lineout Mixer", "Switch", "Right DAC" },
{ "Mono Mixer", "Beep Playback Volume", "Beep Mixer" },
{ "Mono Mixer", "Right Switch", "Right DAC" },
{ "Mono Mixer", "Left Switch", "Left DAC" },
{ "Speaker", NULL, "Mono Mixer" },
{ "Mono Mixer", NULL, "SYSCLK" },
{ "Left Lineout Mixer", NULL, "SYSCLK" },
{ "Left Lineout Mixer", NULL, "SYSCLK" },
{ "Beep Mixer", "Beep Capture Switch", "BEEP" },
{ "Beep Mixer", NULL, "Zero Crossing Detector" },
{ "Left DAC", NULL, "DAC Engine" },
{ "Right DAC", NULL, "DAC Engine" },
{ "Sound Engine", NULL, "SYSCLK" },
{ "DSP", NULL, "Sound Engine" },
{ "Left Decimator", NULL, "ADC Engine" },
{ "Right Decimator", NULL, "ADC Engine" },
{ "AIFCLK", NULL, "SYSCLK" },
{ "Playback", NULL, "Serial Input Routing" },
{ "Playback", NULL, "Serial Ports" },
{ "Playback", NULL, "Clock Domain Transfer" },
{ "Capture", NULL, "Serial Output Routing" },
{ "Capture", NULL, "Serial Ports" },
{ "Capture", NULL, "Clock Domain Transfer" },
{ "AOUTL", NULL, "Left Lineout Mixer" },
{ "AOUTR", NULL, "Right Lineout Mixer" },
{ "SP", NULL, "Speaker" },
};
static const struct snd_soc_dapm_route adau1781_adc_dapm_routes[] = {
{ "Left PGA", NULL, "LMIC" },
{ "Right PGA", NULL, "RMIC" },
{ "Left Decimator", NULL, "Left PGA" },
{ "Right Decimator", NULL, "Right PGA" },
};
static const char * const adau1781_dmic_select_text[] = {
"DMIC1", "DMIC2",
};
static SOC_ENUM_SINGLE_VIRT_DECL(adau1781_dmic_select_enum,
adau1781_dmic_select_text);
static const struct snd_kcontrol_new adau1781_dmic_mux =
SOC_DAPM_ENUM("DMIC Select", adau1781_dmic_select_enum);
static const struct snd_soc_dapm_widget adau1781_dmic_dapm_widgets[] = {
SND_SOC_DAPM_MUX("DMIC Select", SND_SOC_NOPM, 0, 0, &adau1781_dmic_mux),
SND_SOC_DAPM_ADC("DMIC1", NULL, ADAU1781_DMIC_BEEP_CTRL, 4, 0),
SND_SOC_DAPM_ADC("DMIC2", NULL, ADAU1781_DMIC_BEEP_CTRL, 5, 0),
};
static const struct snd_soc_dapm_route adau1781_dmic_dapm_routes[] = {
{ "DMIC1", NULL, "LMIC" },
{ "DMIC2", NULL, "RMIC" },
{ "DMIC1", NULL, "Digital Mic" },
{ "DMIC2", NULL, "Digital Mic" },
{ "DMIC Select", "DMIC1", "DMIC1" },
{ "DMIC Select", "DMIC2", "DMIC2" },
{ "Left Decimator", NULL, "DMIC Select" },
{ "Right Decimator", NULL, "DMIC Select" },
};
static int adau1781_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct adau *adau = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL,
ADAU17X1_CLOCK_CONTROL_SYSCLK_EN,
ADAU17X1_CLOCK_CONTROL_SYSCLK_EN);
/* Precharge */
regmap_update_bits(adau->regmap, ADAU1781_DIG_PWDN1, 0x8, 0x8);
break;
case SND_SOC_BIAS_OFF:
regmap_update_bits(adau->regmap, ADAU1781_DIG_PWDN1, 0xc, 0x0);
regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL,
ADAU17X1_CLOCK_CONTROL_SYSCLK_EN, 0);
break;
}
return 0;
}
static bool adau1781_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case ADAU1781_DMIC_BEEP_CTRL:
case ADAU1781_LEFT_PGA:
case ADAU1781_RIGHT_PGA:
case ADAU1781_LEFT_PLAYBACK_MIXER:
case ADAU1781_RIGHT_PLAYBACK_MIXER:
case ADAU1781_MONO_PLAYBACK_MIXER:
case ADAU1781_LEFT_LINEOUT:
case ADAU1781_RIGHT_LINEOUT:
case ADAU1781_SPEAKER:
case ADAU1781_BEEP_ZC:
case ADAU1781_DEJITTER:
case ADAU1781_DIG_PWDN0:
case ADAU1781_DIG_PWDN1:
return true;
default:
break;
}
return adau17x1_readable_register(dev, reg);
}
static int adau1781_set_input_mode(struct adau *adau, unsigned int reg,
bool differential)
{
unsigned int val;
if (differential)
val = ADAU1781_INPUT_DIFFERNTIAL;
else
val = 0;
return regmap_update_bits(adau->regmap, reg,
ADAU1781_INPUT_DIFFERNTIAL, val);
}
static int adau1781_component_probe(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct adau1781_platform_data *pdata = dev_get_platdata(component->dev);
struct adau *adau = snd_soc_component_get_drvdata(component);
int ret;
ret = adau17x1_add_widgets(component);
if (ret)
return ret;
if (pdata) {
ret = adau1781_set_input_mode(adau, ADAU1781_LEFT_PGA,
pdata->left_input_differential);
if (ret)
return ret;
ret = adau1781_set_input_mode(adau, ADAU1781_RIGHT_PGA,
pdata->right_input_differential);
if (ret)
return ret;
}
if (pdata && pdata->use_dmic) {
ret = snd_soc_dapm_new_controls(dapm,
adau1781_dmic_dapm_widgets,
ARRAY_SIZE(adau1781_dmic_dapm_widgets));
if (ret)
return ret;
ret = snd_soc_dapm_add_routes(dapm, adau1781_dmic_dapm_routes,
ARRAY_SIZE(adau1781_dmic_dapm_routes));
if (ret)
return ret;
} else {
ret = snd_soc_dapm_add_routes(dapm, adau1781_adc_dapm_routes,
ARRAY_SIZE(adau1781_adc_dapm_routes));
if (ret)
return ret;
}
ret = adau17x1_add_routes(component);
if (ret < 0)
return ret;
return 0;
}
static const struct snd_soc_component_driver adau1781_component_driver = {
.probe = adau1781_component_probe,
.resume = adau17x1_resume,
.set_bias_level = adau1781_set_bias_level,
.controls = adau1781_controls,
.num_controls = ARRAY_SIZE(adau1781_controls),
.dapm_widgets = adau1781_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(adau1781_dapm_widgets),
.dapm_routes = adau1781_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(adau1781_dapm_routes),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
#define ADAU1781_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver adau1781_dai_driver = {
.name = "adau-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = ADAU1781_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = ADAU1781_FORMATS,
},
.ops = &adau17x1_dai_ops,
};
const struct regmap_config adau1781_regmap_config = {
.val_bits = 8,
.reg_bits = 16,
.max_register = 0x40f8,
.reg_defaults = adau1781_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(adau1781_reg_defaults),
.readable_reg = adau1781_readable_register,
.volatile_reg = adau17x1_volatile_register,
.precious_reg = adau17x1_precious_register,
.cache_type = REGCACHE_MAPLE,
};
EXPORT_SYMBOL_GPL(adau1781_regmap_config);
int adau1781_probe(struct device *dev, struct regmap *regmap,
enum adau17x1_type type, void (*switch_mode)(struct device *dev))
{
const char *firmware_name;
int ret;
switch (type) {
case ADAU1381:
firmware_name = ADAU1381_FIRMWARE;
break;
case ADAU1781:
firmware_name = ADAU1781_FIRMWARE;
break;
default:
return -EINVAL;
}
ret = adau17x1_probe(dev, regmap, type, switch_mode, firmware_name);
if (ret)
return ret;
return devm_snd_soc_register_component(dev, &adau1781_component_driver,
&adau1781_dai_driver, 1);
}
EXPORT_SYMBOL_GPL(adau1781_probe);
MODULE_DESCRIPTION("ASoC ADAU1381/ADAU1781 driver");
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/adau1781.c |
// SPDX-License-Identifier: GPL-2.0
//
// JZ4740 CODEC driver
//
// Copyright (C) 2009-2010, Lars-Peter Clausen <[email protected]>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/regmap.h>
#include <linux/delay.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#define JZ4740_REG_CODEC_1 0x0
#define JZ4740_REG_CODEC_2 0x4
#define JZ4740_CODEC_1_LINE_ENABLE BIT(29)
#define JZ4740_CODEC_1_MIC_ENABLE BIT(28)
#define JZ4740_CODEC_1_SW1_ENABLE BIT(27)
#define JZ4740_CODEC_1_ADC_ENABLE BIT(26)
#define JZ4740_CODEC_1_SW2_ENABLE BIT(25)
#define JZ4740_CODEC_1_DAC_ENABLE BIT(24)
#define JZ4740_CODEC_1_VREF_DISABLE BIT(20)
#define JZ4740_CODEC_1_VREF_AMP_DISABLE BIT(19)
#define JZ4740_CODEC_1_VREF_PULLDOWN BIT(18)
#define JZ4740_CODEC_1_VREF_LOW_CURRENT BIT(17)
#define JZ4740_CODEC_1_VREF_HIGH_CURRENT BIT(16)
#define JZ4740_CODEC_1_HEADPHONE_DISABLE BIT(14)
#define JZ4740_CODEC_1_HEADPHONE_AMP_CHANGE_ANY BIT(13)
#define JZ4740_CODEC_1_HEADPHONE_CHARGE BIT(12)
#define JZ4740_CODEC_1_HEADPHONE_PULLDOWN (BIT(11) | BIT(10))
#define JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M BIT(9)
#define JZ4740_CODEC_1_HEADPHONE_POWERDOWN BIT(8)
#define JZ4740_CODEC_1_SUSPEND BIT(1)
#define JZ4740_CODEC_1_RESET BIT(0)
#define JZ4740_CODEC_1_LINE_ENABLE_OFFSET 29
#define JZ4740_CODEC_1_MIC_ENABLE_OFFSET 28
#define JZ4740_CODEC_1_SW1_ENABLE_OFFSET 27
#define JZ4740_CODEC_1_ADC_ENABLE_OFFSET 26
#define JZ4740_CODEC_1_SW2_ENABLE_OFFSET 25
#define JZ4740_CODEC_1_DAC_ENABLE_OFFSET 24
#define JZ4740_CODEC_1_HEADPHONE_DISABLE_OFFSET 14
#define JZ4740_CODEC_1_HEADPHONE_POWERDOWN_OFFSET 8
#define JZ4740_CODEC_2_INPUT_VOLUME_MASK 0x1f0000
#define JZ4740_CODEC_2_SAMPLE_RATE_MASK 0x000f00
#define JZ4740_CODEC_2_MIC_BOOST_GAIN_MASK 0x000030
#define JZ4740_CODEC_2_HEADPHONE_VOLUME_MASK 0x000003
#define JZ4740_CODEC_2_INPUT_VOLUME_OFFSET 16
#define JZ4740_CODEC_2_SAMPLE_RATE_OFFSET 8
#define JZ4740_CODEC_2_MIC_BOOST_GAIN_OFFSET 4
#define JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET 0
static const struct reg_default jz4740_codec_reg_defaults[] = {
{ JZ4740_REG_CODEC_1, 0x021b2302 },
{ JZ4740_REG_CODEC_2, 0x00170803 },
};
struct jz4740_codec {
struct regmap *regmap;
};
static const DECLARE_TLV_DB_RANGE(jz4740_mic_tlv,
0, 2, TLV_DB_SCALE_ITEM(0, 600, 0),
3, 3, TLV_DB_SCALE_ITEM(2000, 0, 0)
);
static const DECLARE_TLV_DB_SCALE(jz4740_out_tlv, 0, 200, 0);
static const DECLARE_TLV_DB_SCALE(jz4740_in_tlv, -3450, 150, 0);
static const struct snd_kcontrol_new jz4740_codec_controls[] = {
SOC_SINGLE_TLV("Master Playback Volume", JZ4740_REG_CODEC_2,
JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET, 3, 0,
jz4740_out_tlv),
SOC_SINGLE_TLV("Master Capture Volume", JZ4740_REG_CODEC_2,
JZ4740_CODEC_2_INPUT_VOLUME_OFFSET, 31, 0,
jz4740_in_tlv),
SOC_SINGLE("Master Playback Switch", JZ4740_REG_CODEC_1,
JZ4740_CODEC_1_HEADPHONE_DISABLE_OFFSET, 1, 1),
SOC_SINGLE_TLV("Mic Capture Volume", JZ4740_REG_CODEC_2,
JZ4740_CODEC_2_MIC_BOOST_GAIN_OFFSET, 3, 0,
jz4740_mic_tlv),
};
static const struct snd_kcontrol_new jz4740_codec_output_controls[] = {
SOC_DAPM_SINGLE("Bypass Switch", JZ4740_REG_CODEC_1,
JZ4740_CODEC_1_SW1_ENABLE_OFFSET, 1, 0),
SOC_DAPM_SINGLE("DAC Switch", JZ4740_REG_CODEC_1,
JZ4740_CODEC_1_SW2_ENABLE_OFFSET, 1, 0),
};
static const struct snd_kcontrol_new jz4740_codec_input_controls[] = {
SOC_DAPM_SINGLE("Line Capture Switch", JZ4740_REG_CODEC_1,
JZ4740_CODEC_1_LINE_ENABLE_OFFSET, 1, 0),
SOC_DAPM_SINGLE("Mic Capture Switch", JZ4740_REG_CODEC_1,
JZ4740_CODEC_1_MIC_ENABLE_OFFSET, 1, 0),
};
static const struct snd_soc_dapm_widget jz4740_codec_dapm_widgets[] = {
SND_SOC_DAPM_ADC("ADC", "Capture", JZ4740_REG_CODEC_1,
JZ4740_CODEC_1_ADC_ENABLE_OFFSET, 0),
SND_SOC_DAPM_DAC("DAC", "Playback", JZ4740_REG_CODEC_1,
JZ4740_CODEC_1_DAC_ENABLE_OFFSET, 0),
SND_SOC_DAPM_MIXER("Output Mixer", JZ4740_REG_CODEC_1,
JZ4740_CODEC_1_HEADPHONE_POWERDOWN_OFFSET, 1,
jz4740_codec_output_controls,
ARRAY_SIZE(jz4740_codec_output_controls)),
SND_SOC_DAPM_MIXER_NAMED_CTL("Input Mixer", SND_SOC_NOPM, 0, 0,
jz4740_codec_input_controls,
ARRAY_SIZE(jz4740_codec_input_controls)),
SND_SOC_DAPM_MIXER("Line Input", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("LOUT"),
SND_SOC_DAPM_OUTPUT("ROUT"),
SND_SOC_DAPM_INPUT("MIC"),
SND_SOC_DAPM_INPUT("LIN"),
SND_SOC_DAPM_INPUT("RIN"),
};
static const struct snd_soc_dapm_route jz4740_codec_dapm_routes[] = {
{"Line Input", NULL, "LIN"},
{"Line Input", NULL, "RIN"},
{"Input Mixer", "Line Capture Switch", "Line Input"},
{"Input Mixer", "Mic Capture Switch", "MIC"},
{"ADC", NULL, "Input Mixer"},
{"Output Mixer", "Bypass Switch", "Input Mixer"},
{"Output Mixer", "DAC Switch", "DAC"},
{"LOUT", NULL, "Output Mixer"},
{"ROUT", NULL, "Output Mixer"},
};
static int jz4740_codec_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct jz4740_codec *jz4740_codec = snd_soc_component_get_drvdata(dai->component);
uint32_t val;
switch (params_rate(params)) {
case 8000:
val = 0;
break;
case 11025:
val = 1;
break;
case 12000:
val = 2;
break;
case 16000:
val = 3;
break;
case 22050:
val = 4;
break;
case 24000:
val = 5;
break;
case 32000:
val = 6;
break;
case 44100:
val = 7;
break;
case 48000:
val = 8;
break;
default:
return -EINVAL;
}
val <<= JZ4740_CODEC_2_SAMPLE_RATE_OFFSET;
regmap_update_bits(jz4740_codec->regmap, JZ4740_REG_CODEC_2,
JZ4740_CODEC_2_SAMPLE_RATE_MASK, val);
return 0;
}
static const struct snd_soc_dai_ops jz4740_codec_dai_ops = {
.hw_params = jz4740_codec_hw_params,
};
static struct snd_soc_dai_driver jz4740_codec_dai = {
.name = "jz4740-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
},
.ops = &jz4740_codec_dai_ops,
.symmetric_rate = 1,
};
static void jz4740_codec_wakeup(struct regmap *regmap)
{
regmap_set_bits(regmap, JZ4740_REG_CODEC_1, JZ4740_CODEC_1_RESET);
udelay(2);
regmap_clear_bits(regmap, JZ4740_REG_CODEC_1,
JZ4740_CODEC_1_SUSPEND | JZ4740_CODEC_1_RESET);
regcache_sync(regmap);
}
static int jz4740_codec_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct jz4740_codec *jz4740_codec = snd_soc_component_get_drvdata(component);
struct regmap *regmap = jz4740_codec->regmap;
unsigned int mask;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
mask = JZ4740_CODEC_1_VREF_DISABLE |
JZ4740_CODEC_1_VREF_AMP_DISABLE |
JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
regmap_clear_bits(regmap, JZ4740_REG_CODEC_1, mask);
break;
case SND_SOC_BIAS_STANDBY:
/* The only way to clear the suspend flag is to reset the codec */
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
jz4740_codec_wakeup(regmap);
mask = JZ4740_CODEC_1_VREF_DISABLE |
JZ4740_CODEC_1_VREF_AMP_DISABLE |
JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
regmap_set_bits(regmap, JZ4740_REG_CODEC_1, mask);
break;
case SND_SOC_BIAS_OFF:
mask = JZ4740_CODEC_1_SUSPEND;
regmap_set_bits(regmap, JZ4740_REG_CODEC_1, mask);
regcache_mark_dirty(regmap);
break;
default:
break;
}
return 0;
}
static int jz4740_codec_dev_probe(struct snd_soc_component *component)
{
struct jz4740_codec *jz4740_codec = snd_soc_component_get_drvdata(component);
regmap_update_bits(jz4740_codec->regmap, JZ4740_REG_CODEC_1,
JZ4740_CODEC_1_SW2_ENABLE, JZ4740_CODEC_1_SW2_ENABLE);
return 0;
}
static const struct snd_soc_component_driver soc_codec_dev_jz4740_codec = {
.probe = jz4740_codec_dev_probe,
.set_bias_level = jz4740_codec_set_bias_level,
.controls = jz4740_codec_controls,
.num_controls = ARRAY_SIZE(jz4740_codec_controls),
.dapm_widgets = jz4740_codec_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(jz4740_codec_dapm_widgets),
.dapm_routes = jz4740_codec_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(jz4740_codec_dapm_routes),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config jz4740_codec_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = JZ4740_REG_CODEC_2,
.reg_defaults = jz4740_codec_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(jz4740_codec_reg_defaults),
.cache_type = REGCACHE_MAPLE,
};
static int jz4740_codec_probe(struct platform_device *pdev)
{
int ret;
struct jz4740_codec *jz4740_codec;
void __iomem *base;
jz4740_codec = devm_kzalloc(&pdev->dev, sizeof(*jz4740_codec),
GFP_KERNEL);
if (!jz4740_codec)
return -ENOMEM;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
jz4740_codec->regmap = devm_regmap_init_mmio(&pdev->dev, base,
&jz4740_codec_regmap_config);
if (IS_ERR(jz4740_codec->regmap))
return PTR_ERR(jz4740_codec->regmap);
platform_set_drvdata(pdev, jz4740_codec);
ret = devm_snd_soc_register_component(&pdev->dev,
&soc_codec_dev_jz4740_codec, &jz4740_codec_dai, 1);
if (ret)
dev_err(&pdev->dev, "Failed to register codec\n");
return ret;
}
static const struct of_device_id jz4740_codec_of_matches[] = {
{ .compatible = "ingenic,jz4740-codec", },
{ }
};
MODULE_DEVICE_TABLE(of, jz4740_codec_of_matches);
static struct platform_driver jz4740_codec_driver = {
.probe = jz4740_codec_probe,
.driver = {
.name = "jz4740-codec",
.of_match_table = jz4740_codec_of_matches,
},
};
module_platform_driver(jz4740_codec_driver);
MODULE_DESCRIPTION("JZ4740 SoC internal codec driver");
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:jz4740-codec");
| linux-master | sound/soc/codecs/jz4740.c |
// SPDX-License-Identifier: GPL-2.0
/*
* ALSA SoC CPCAP codec driver
*
* Copyright (C) 2017 - 2018 Sebastian Reichel <[email protected]>
*
* Very loosely based on original driver from Motorola:
* Copyright (C) 2007 - 2009 Motorola, Inc.
*/
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/platform_device.h>
#include <linux/mfd/motorola-cpcap.h>
#include <sound/core.h>
#include <sound/soc.h>
#include <sound/tlv.h>
/* Register 512 CPCAP_REG_VAUDIOC --- Audio Regulator and Bias Voltage */
#define CPCAP_BIT_AUDIO_LOW_PWR 6
#define CPCAP_BIT_AUD_LOWPWR_SPEED 5
#define CPCAP_BIT_VAUDIOPRISTBY 4
#define CPCAP_BIT_VAUDIO_MODE1 2
#define CPCAP_BIT_VAUDIO_MODE0 1
#define CPCAP_BIT_V_AUDIO_EN 0
/* Register 513 CPCAP_REG_CC --- CODEC */
#define CPCAP_BIT_CDC_CLK2 15
#define CPCAP_BIT_CDC_CLK1 14
#define CPCAP_BIT_CDC_CLK0 13
#define CPCAP_BIT_CDC_SR3 12
#define CPCAP_BIT_CDC_SR2 11
#define CPCAP_BIT_CDC_SR1 10
#define CPCAP_BIT_CDC_SR0 9
#define CPCAP_BIT_CDC_CLOCK_TREE_RESET 8
#define CPCAP_BIT_MIC2_CDC_EN 7
#define CPCAP_BIT_CDC_EN_RX 6
#define CPCAP_BIT_DF_RESET 5
#define CPCAP_BIT_MIC1_CDC_EN 4
#define CPCAP_BIT_AUDOHPF_1 3
#define CPCAP_BIT_AUDOHPF_0 2
#define CPCAP_BIT_AUDIHPF_1 1
#define CPCAP_BIT_AUDIHPF_0 0
/* Register 514 CPCAP_REG_CDI --- CODEC Digital Audio Interface */
#define CPCAP_BIT_CDC_PLL_SEL 15
#define CPCAP_BIT_CLK_IN_SEL 13
#define CPCAP_BIT_DIG_AUD_IN 12
#define CPCAP_BIT_CDC_CLK_EN 11
#define CPCAP_BIT_CDC_DIG_AUD_FS1 10
#define CPCAP_BIT_CDC_DIG_AUD_FS0 9
#define CPCAP_BIT_MIC2_TIMESLOT2 8
#define CPCAP_BIT_MIC2_TIMESLOT1 7
#define CPCAP_BIT_MIC2_TIMESLOT0 6
#define CPCAP_BIT_MIC1_RX_TIMESLOT2 5
#define CPCAP_BIT_MIC1_RX_TIMESLOT1 4
#define CPCAP_BIT_MIC1_RX_TIMESLOT0 3
#define CPCAP_BIT_FS_INV 2
#define CPCAP_BIT_CLK_INV 1
#define CPCAP_BIT_SMB_CDC 0
/* Register 515 CPCAP_REG_SDAC --- Stereo DAC */
#define CPCAP_BIT_FSYNC_CLK_IN_COMMON 11
#define CPCAP_BIT_SLAVE_PLL_CLK_INPUT 10
#define CPCAP_BIT_ST_CLOCK_TREE_RESET 9
#define CPCAP_BIT_DF_RESET_ST_DAC 8
#define CPCAP_BIT_ST_SR3 7
#define CPCAP_BIT_ST_SR2 6
#define CPCAP_BIT_ST_SR1 5
#define CPCAP_BIT_ST_SR0 4
#define CPCAP_BIT_ST_DAC_CLK2 3
#define CPCAP_BIT_ST_DAC_CLK1 2
#define CPCAP_BIT_ST_DAC_CLK0 1
#define CPCAP_BIT_ST_DAC_EN 0
/* Register 516 CPCAP_REG_SDACDI --- Stereo DAC Digital Audio Interface */
#define CPCAP_BIT_ST_L_TIMESLOT2 13
#define CPCAP_BIT_ST_L_TIMESLOT1 12
#define CPCAP_BIT_ST_L_TIMESLOT0 11
#define CPCAP_BIT_ST_R_TIMESLOT2 10
#define CPCAP_BIT_ST_R_TIMESLOT1 9
#define CPCAP_BIT_ST_R_TIMESLOT0 8
#define CPCAP_BIT_ST_DAC_CLK_IN_SEL 7
#define CPCAP_BIT_ST_FS_INV 6
#define CPCAP_BIT_ST_CLK_INV 5
#define CPCAP_BIT_ST_DIG_AUD_FS1 4
#define CPCAP_BIT_ST_DIG_AUD_FS0 3
#define CPCAP_BIT_DIG_AUD_IN_ST_DAC 2
#define CPCAP_BIT_ST_CLK_EN 1
#define CPCAP_BIT_SMB_ST_DAC 0
/* Register 517 CPCAP_REG_TXI --- TX Interface */
#define CPCAP_BIT_PTT_TH 15
#define CPCAP_BIT_PTT_CMP_EN 14
#define CPCAP_BIT_HS_ID_TX 13
#define CPCAP_BIT_MB_ON2 12
#define CPCAP_BIT_MB_ON1L 11
#define CPCAP_BIT_MB_ON1R 10
#define CPCAP_BIT_RX_L_ENCODE 9
#define CPCAP_BIT_RX_R_ENCODE 8
#define CPCAP_BIT_MIC2_MUX 7
#define CPCAP_BIT_MIC2_PGA_EN 6
#define CPCAP_BIT_CDET_DIS 5
#define CPCAP_BIT_EMU_MIC_MUX 4
#define CPCAP_BIT_HS_MIC_MUX 3
#define CPCAP_BIT_MIC1_MUX 2
#define CPCAP_BIT_MIC1_PGA_EN 1
#define CPCAP_BIT_DLM 0
/* Register 518 CPCAP_REG_TXMP --- Mic Gain */
#define CPCAP_BIT_MB_BIAS_R1 11
#define CPCAP_BIT_MB_BIAS_R0 10
#define CPCAP_BIT_MIC2_GAIN_4 9
#define CPCAP_BIT_MIC2_GAIN_3 8
#define CPCAP_BIT_MIC2_GAIN_2 7
#define CPCAP_BIT_MIC2_GAIN_1 6
#define CPCAP_BIT_MIC2_GAIN_0 5
#define CPCAP_BIT_MIC1_GAIN_4 4
#define CPCAP_BIT_MIC1_GAIN_3 3
#define CPCAP_BIT_MIC1_GAIN_2 2
#define CPCAP_BIT_MIC1_GAIN_1 1
#define CPCAP_BIT_MIC1_GAIN_0 0
/* Register 519 CPCAP_REG_RXOA --- RX Output Amplifier */
#define CPCAP_BIT_UNUSED_519_15 15
#define CPCAP_BIT_UNUSED_519_14 14
#define CPCAP_BIT_UNUSED_519_13 13
#define CPCAP_BIT_STDAC_LOW_PWR_DISABLE 12
#define CPCAP_BIT_HS_LOW_PWR 11
#define CPCAP_BIT_HS_ID_RX 10
#define CPCAP_BIT_ST_HS_CP_EN 9
#define CPCAP_BIT_EMU_SPKR_R_EN 8
#define CPCAP_BIT_EMU_SPKR_L_EN 7
#define CPCAP_BIT_HS_L_EN 6
#define CPCAP_BIT_HS_R_EN 5
#define CPCAP_BIT_A4_LINEOUT_L_EN 4
#define CPCAP_BIT_A4_LINEOUT_R_EN 3
#define CPCAP_BIT_A2_LDSP_L_EN 2
#define CPCAP_BIT_A2_LDSP_R_EN 1
#define CPCAP_BIT_A1_EAR_EN 0
/* Register 520 CPCAP_REG_RXVC --- RX Volume Control */
#define CPCAP_BIT_VOL_EXT3 15
#define CPCAP_BIT_VOL_EXT2 14
#define CPCAP_BIT_VOL_EXT1 13
#define CPCAP_BIT_VOL_EXT0 12
#define CPCAP_BIT_VOL_DAC3 11
#define CPCAP_BIT_VOL_DAC2 10
#define CPCAP_BIT_VOL_DAC1 9
#define CPCAP_BIT_VOL_DAC0 8
#define CPCAP_BIT_VOL_DAC_LSB_1dB1 7
#define CPCAP_BIT_VOL_DAC_LSB_1dB0 6
#define CPCAP_BIT_VOL_CDC3 5
#define CPCAP_BIT_VOL_CDC2 4
#define CPCAP_BIT_VOL_CDC1 3
#define CPCAP_BIT_VOL_CDC0 2
#define CPCAP_BIT_VOL_CDC_LSB_1dB1 1
#define CPCAP_BIT_VOL_CDC_LSB_1dB0 0
/* Register 521 CPCAP_REG_RXCOA --- Codec to Output Amp Switches */
#define CPCAP_BIT_PGA_CDC_EN 10
#define CPCAP_BIT_CDC_SW 9
#define CPCAP_BIT_PGA_OUTR_USBDP_CDC_SW 8
#define CPCAP_BIT_PGA_OUTL_USBDN_CDC_SW 7
#define CPCAP_BIT_ALEFT_HS_CDC_SW 6
#define CPCAP_BIT_ARIGHT_HS_CDC_SW 5
#define CPCAP_BIT_A4_LINEOUT_L_CDC_SW 4
#define CPCAP_BIT_A4_LINEOUT_R_CDC_SW 3
#define CPCAP_BIT_A2_LDSP_L_CDC_SW 2
#define CPCAP_BIT_A2_LDSP_R_CDC_SW 1
#define CPCAP_BIT_A1_EAR_CDC_SW 0
/* Register 522 CPCAP_REG_RXSDOA --- RX Stereo DAC to Output Amp Switches */
#define CPCAP_BIT_PGA_DAC_EN 12
#define CPCAP_BIT_ST_DAC_SW 11
#define CPCAP_BIT_MONO_DAC1 10
#define CPCAP_BIT_MONO_DAC0 9
#define CPCAP_BIT_PGA_OUTR_USBDP_DAC_SW 8
#define CPCAP_BIT_PGA_OUTL_USBDN_DAC_SW 7
#define CPCAP_BIT_ALEFT_HS_DAC_SW 6
#define CPCAP_BIT_ARIGHT_HS_DAC_SW 5
#define CPCAP_BIT_A4_LINEOUT_L_DAC_SW 4
#define CPCAP_BIT_A4_LINEOUT_R_DAC_SW 3
#define CPCAP_BIT_A2_LDSP_L_DAC_SW 2
#define CPCAP_BIT_A2_LDSP_R_DAC_SW 1
#define CPCAP_BIT_A1_EAR_DAC_SW 0
/* Register 523 CPCAP_REG_RXEPOA --- RX External PGA to Output Amp Switches */
#define CPCAP_BIT_PGA_EXT_L_EN 14
#define CPCAP_BIT_PGA_EXT_R_EN 13
#define CPCAP_BIT_PGA_IN_L_SW 12
#define CPCAP_BIT_PGA_IN_R_SW 11
#define CPCAP_BIT_MONO_EXT1 10
#define CPCAP_BIT_MONO_EXT0 9
#define CPCAP_BIT_PGA_OUTR_USBDP_EXT_SW 8
#define CPCAP_BIT_PGA_OUTL_USBDN_EXT_SW 7
#define CPCAP_BIT_ALEFT_HS_EXT_SW 6
#define CPCAP_BIT_ARIGHT_HS_EXT_SW 5
#define CPCAP_BIT_A4_LINEOUT_L_EXT_SW 4
#define CPCAP_BIT_A4_LINEOUT_R_EXT_SW 3
#define CPCAP_BIT_A2_LDSP_L_EXT_SW 2
#define CPCAP_BIT_A2_LDSP_R_EXT_SW 1
#define CPCAP_BIT_A1_EAR_EXT_SW 0
/* Register 525 CPCAP_REG_A2LA --- SPK Amplifier and Clock Config for Headset */
#define CPCAP_BIT_NCP_CLK_SYNC 7
#define CPCAP_BIT_A2_CLK_SYNC 6
#define CPCAP_BIT_A2_FREE_RUN 5
#define CPCAP_BIT_A2_CLK2 4
#define CPCAP_BIT_A2_CLK1 3
#define CPCAP_BIT_A2_CLK0 2
#define CPCAP_BIT_A2_CLK_IN 1
#define CPCAP_BIT_A2_CONFIG 0
#define SLEEP_ACTIVATE_POWER 2
#define CLOCK_TREE_RESET_TIME 1
/* constants for ST delay workaround */
#define STM_STDAC_ACTIVATE_RAMP_TIME 1
#define STM_STDAC_EN_TEST_PRE 0x090C
#define STM_STDAC_EN_TEST_POST 0x0000
#define STM_STDAC_EN_ST_TEST1_PRE 0x2400
#define STM_STDAC_EN_ST_TEST1_POST 0x0400
struct cpcap_reg_info {
u16 reg;
u16 mask;
u16 val;
};
static const struct cpcap_reg_info cpcap_default_regs[] = {
{ CPCAP_REG_VAUDIOC, 0x003F, 0x0000 },
{ CPCAP_REG_CC, 0xFFFF, 0x0000 },
{ CPCAP_REG_CC, 0xFFFF, 0x0000 },
{ CPCAP_REG_CDI, 0xBFFF, 0x0000 },
{ CPCAP_REG_SDAC, 0x0FFF, 0x0000 },
{ CPCAP_REG_SDACDI, 0x3FFF, 0x0000 },
{ CPCAP_REG_TXI, 0x0FDF, 0x0000 },
{ CPCAP_REG_TXMP, 0x0FFF, 0x0400 },
{ CPCAP_REG_RXOA, 0x01FF, 0x0000 },
{ CPCAP_REG_RXVC, 0xFF3C, 0x0000 },
{ CPCAP_REG_RXCOA, 0x07FF, 0x0000 },
{ CPCAP_REG_RXSDOA, 0x1FFF, 0x0000 },
{ CPCAP_REG_RXEPOA, 0x7FFF, 0x0000 },
{ CPCAP_REG_A2LA, BIT(CPCAP_BIT_A2_FREE_RUN),
BIT(CPCAP_BIT_A2_FREE_RUN) },
};
enum cpcap_dai {
CPCAP_DAI_HIFI,
CPCAP_DAI_VOICE,
};
struct cpcap_audio {
struct snd_soc_component *component;
struct regmap *regmap;
u16 vendor;
int codec_clk_id;
int codec_freq;
int codec_format;
};
static int cpcap_st_workaround(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
int err = 0;
/* Only CPCAP from ST requires workaround */
if (cpcap->vendor != CPCAP_VENDOR_ST)
return 0;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
err = regmap_write(cpcap->regmap, CPCAP_REG_TEST,
STM_STDAC_EN_TEST_PRE);
if (err)
return err;
err = regmap_write(cpcap->regmap, CPCAP_REG_ST_TEST1,
STM_STDAC_EN_ST_TEST1_PRE);
break;
case SND_SOC_DAPM_POST_PMU:
msleep(STM_STDAC_ACTIVATE_RAMP_TIME);
err = regmap_write(cpcap->regmap, CPCAP_REG_ST_TEST1,
STM_STDAC_EN_ST_TEST1_POST);
if (err)
return err;
err = regmap_write(cpcap->regmap, CPCAP_REG_TEST,
STM_STDAC_EN_TEST_POST);
break;
default:
break;
}
return err;
}
/* Capture Gain Control: 0dB to 31dB in 1dB steps */
static const DECLARE_TLV_DB_SCALE(mic_gain_tlv, 0, 100, 0);
/* Playback Gain Control: -33dB to 12dB in 3dB steps */
static const DECLARE_TLV_DB_SCALE(vol_tlv, -3300, 300, 0);
static const struct snd_kcontrol_new cpcap_snd_controls[] = {
/* Playback Gain */
SOC_SINGLE_TLV("HiFi Playback Volume",
CPCAP_REG_RXVC, CPCAP_BIT_VOL_DAC0, 0xF, 0, vol_tlv),
SOC_SINGLE_TLV("Voice Playback Volume",
CPCAP_REG_RXVC, CPCAP_BIT_VOL_CDC0, 0xF, 0, vol_tlv),
SOC_SINGLE_TLV("Ext Playback Volume",
CPCAP_REG_RXVC, CPCAP_BIT_VOL_EXT0, 0xF, 0, vol_tlv),
/* Capture Gain */
SOC_SINGLE_TLV("Mic1 Capture Volume",
CPCAP_REG_TXMP, CPCAP_BIT_MIC1_GAIN_0, 0x1F, 0, mic_gain_tlv),
SOC_SINGLE_TLV("Mic2 Capture Volume",
CPCAP_REG_TXMP, CPCAP_BIT_MIC2_GAIN_0, 0x1F, 0, mic_gain_tlv),
/* Phase Invert */
SOC_SINGLE("Hifi Left Phase Invert Switch",
CPCAP_REG_RXSDOA, CPCAP_BIT_MONO_DAC0, 1, 0),
SOC_SINGLE("Ext Left Phase Invert Switch",
CPCAP_REG_RXEPOA, CPCAP_BIT_MONO_EXT0, 1, 0),
};
static const char * const cpcap_out_mux_texts[] = {
"Off", "Voice", "HiFi", "Ext"
};
static const char * const cpcap_in_right_mux_texts[] = {
"Off", "Mic 1", "Headset Mic", "EMU Mic", "Ext Right"
};
static const char * const cpcap_in_left_mux_texts[] = {
"Off", "Mic 2", "Ext Left"
};
/*
* input muxes use unusual register layout, so that we need to use custom
* getter/setter methods
*/
static SOC_ENUM_SINGLE_EXT_DECL(cpcap_input_left_mux_enum,
cpcap_in_left_mux_texts);
static SOC_ENUM_SINGLE_EXT_DECL(cpcap_input_right_mux_enum,
cpcap_in_right_mux_texts);
/*
* mux uses same bit in CPCAP_REG_RXCOA, CPCAP_REG_RXSDOA & CPCAP_REG_RXEPOA;
* even though the register layout makes it look like a mixer, this is a mux.
* Enabling multiple inputs will result in no audio being forwarded.
*/
static SOC_ENUM_SINGLE_DECL(cpcap_earpiece_mux_enum, 0, 0, cpcap_out_mux_texts);
static SOC_ENUM_SINGLE_DECL(cpcap_spkr_r_mux_enum, 0, 1, cpcap_out_mux_texts);
static SOC_ENUM_SINGLE_DECL(cpcap_spkr_l_mux_enum, 0, 2, cpcap_out_mux_texts);
static SOC_ENUM_SINGLE_DECL(cpcap_line_r_mux_enum, 0, 3, cpcap_out_mux_texts);
static SOC_ENUM_SINGLE_DECL(cpcap_line_l_mux_enum, 0, 4, cpcap_out_mux_texts);
static SOC_ENUM_SINGLE_DECL(cpcap_hs_r_mux_enum, 0, 5, cpcap_out_mux_texts);
static SOC_ENUM_SINGLE_DECL(cpcap_hs_l_mux_enum, 0, 6, cpcap_out_mux_texts);
static SOC_ENUM_SINGLE_DECL(cpcap_emu_l_mux_enum, 0, 7, cpcap_out_mux_texts);
static SOC_ENUM_SINGLE_DECL(cpcap_emu_r_mux_enum, 0, 8, cpcap_out_mux_texts);
static int cpcap_output_mux_get_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int shift = e->shift_l;
int reg_voice, reg_hifi, reg_ext, status;
int err;
err = regmap_read(cpcap->regmap, CPCAP_REG_RXCOA, ®_voice);
if (err)
return err;
err = regmap_read(cpcap->regmap, CPCAP_REG_RXSDOA, ®_hifi);
if (err)
return err;
err = regmap_read(cpcap->regmap, CPCAP_REG_RXEPOA, ®_ext);
if (err)
return err;
reg_voice = (reg_voice >> shift) & 1;
reg_hifi = (reg_hifi >> shift) & 1;
reg_ext = (reg_ext >> shift) & 1;
status = reg_ext << 2 | reg_hifi << 1 | reg_voice;
switch (status) {
case 0x04:
ucontrol->value.enumerated.item[0] = 3;
break;
case 0x02:
ucontrol->value.enumerated.item[0] = 2;
break;
case 0x01:
ucontrol->value.enumerated.item[0] = 1;
break;
default:
ucontrol->value.enumerated.item[0] = 0;
break;
}
return 0;
}
static int cpcap_output_mux_put_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm =
snd_soc_dapm_kcontrol_dapm(kcontrol);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int muxval = ucontrol->value.enumerated.item[0];
unsigned int mask = BIT(e->shift_l);
u16 reg_voice = 0x00, reg_hifi = 0x00, reg_ext = 0x00;
int err;
switch (muxval) {
case 1:
reg_voice = mask;
break;
case 2:
reg_hifi = mask;
break;
case 3:
reg_ext = mask;
break;
default:
break;
}
err = regmap_update_bits(cpcap->regmap, CPCAP_REG_RXCOA,
mask, reg_voice);
if (err)
return err;
err = regmap_update_bits(cpcap->regmap, CPCAP_REG_RXSDOA,
mask, reg_hifi);
if (err)
return err;
err = regmap_update_bits(cpcap->regmap, CPCAP_REG_RXEPOA,
mask, reg_ext);
if (err)
return err;
snd_soc_dapm_mux_update_power(dapm, kcontrol, muxval, e, NULL);
return 0;
}
static int cpcap_input_right_mux_get_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
int regval, mask;
int err;
err = regmap_read(cpcap->regmap, CPCAP_REG_TXI, ®val);
if (err)
return err;
mask = 0;
mask |= BIT(CPCAP_BIT_MIC1_MUX);
mask |= BIT(CPCAP_BIT_HS_MIC_MUX);
mask |= BIT(CPCAP_BIT_EMU_MIC_MUX);
mask |= BIT(CPCAP_BIT_RX_R_ENCODE);
switch (regval & mask) {
case BIT(CPCAP_BIT_RX_R_ENCODE):
ucontrol->value.enumerated.item[0] = 4;
break;
case BIT(CPCAP_BIT_EMU_MIC_MUX):
ucontrol->value.enumerated.item[0] = 3;
break;
case BIT(CPCAP_BIT_HS_MIC_MUX):
ucontrol->value.enumerated.item[0] = 2;
break;
case BIT(CPCAP_BIT_MIC1_MUX):
ucontrol->value.enumerated.item[0] = 1;
break;
default:
ucontrol->value.enumerated.item[0] = 0;
break;
}
return 0;
}
static int cpcap_input_right_mux_put_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm =
snd_soc_dapm_kcontrol_dapm(kcontrol);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int muxval = ucontrol->value.enumerated.item[0];
int regval = 0, mask;
int err;
mask = 0;
mask |= BIT(CPCAP_BIT_MIC1_MUX);
mask |= BIT(CPCAP_BIT_HS_MIC_MUX);
mask |= BIT(CPCAP_BIT_EMU_MIC_MUX);
mask |= BIT(CPCAP_BIT_RX_R_ENCODE);
switch (muxval) {
case 1:
regval = BIT(CPCAP_BIT_MIC1_MUX);
break;
case 2:
regval = BIT(CPCAP_BIT_HS_MIC_MUX);
break;
case 3:
regval = BIT(CPCAP_BIT_EMU_MIC_MUX);
break;
case 4:
regval = BIT(CPCAP_BIT_RX_R_ENCODE);
break;
default:
break;
}
err = regmap_update_bits(cpcap->regmap, CPCAP_REG_TXI,
mask, regval);
if (err)
return err;
snd_soc_dapm_mux_update_power(dapm, kcontrol, muxval, e, NULL);
return 0;
}
static int cpcap_input_left_mux_get_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
int regval, mask;
int err;
err = regmap_read(cpcap->regmap, CPCAP_REG_TXI, ®val);
if (err)
return err;
mask = 0;
mask |= BIT(CPCAP_BIT_MIC2_MUX);
mask |= BIT(CPCAP_BIT_RX_L_ENCODE);
switch (regval & mask) {
case BIT(CPCAP_BIT_RX_L_ENCODE):
ucontrol->value.enumerated.item[0] = 2;
break;
case BIT(CPCAP_BIT_MIC2_MUX):
ucontrol->value.enumerated.item[0] = 1;
break;
default:
ucontrol->value.enumerated.item[0] = 0;
break;
}
return 0;
}
static int cpcap_input_left_mux_put_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm =
snd_soc_dapm_kcontrol_dapm(kcontrol);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int muxval = ucontrol->value.enumerated.item[0];
int regval = 0, mask;
int err;
mask = 0;
mask |= BIT(CPCAP_BIT_MIC2_MUX);
mask |= BIT(CPCAP_BIT_RX_L_ENCODE);
switch (muxval) {
case 1:
regval = BIT(CPCAP_BIT_MIC2_MUX);
break;
case 2:
regval = BIT(CPCAP_BIT_RX_L_ENCODE);
break;
default:
break;
}
err = regmap_update_bits(cpcap->regmap, CPCAP_REG_TXI,
mask, regval);
if (err)
return err;
snd_soc_dapm_mux_update_power(dapm, kcontrol, muxval, e, NULL);
return 0;
}
static const struct snd_kcontrol_new cpcap_input_left_mux =
SOC_DAPM_ENUM_EXT("Input Left", cpcap_input_left_mux_enum,
cpcap_input_left_mux_get_enum,
cpcap_input_left_mux_put_enum);
static const struct snd_kcontrol_new cpcap_input_right_mux =
SOC_DAPM_ENUM_EXT("Input Right", cpcap_input_right_mux_enum,
cpcap_input_right_mux_get_enum,
cpcap_input_right_mux_put_enum);
static const struct snd_kcontrol_new cpcap_emu_left_mux =
SOC_DAPM_ENUM_EXT("EMU Left", cpcap_emu_l_mux_enum,
cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
static const struct snd_kcontrol_new cpcap_emu_right_mux =
SOC_DAPM_ENUM_EXT("EMU Right", cpcap_emu_r_mux_enum,
cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
static const struct snd_kcontrol_new cpcap_hs_left_mux =
SOC_DAPM_ENUM_EXT("Headset Left", cpcap_hs_l_mux_enum,
cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
static const struct snd_kcontrol_new cpcap_hs_right_mux =
SOC_DAPM_ENUM_EXT("Headset Right", cpcap_hs_r_mux_enum,
cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
static const struct snd_kcontrol_new cpcap_line_left_mux =
SOC_DAPM_ENUM_EXT("Line Left", cpcap_line_l_mux_enum,
cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
static const struct snd_kcontrol_new cpcap_line_right_mux =
SOC_DAPM_ENUM_EXT("Line Right", cpcap_line_r_mux_enum,
cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
static const struct snd_kcontrol_new cpcap_speaker_left_mux =
SOC_DAPM_ENUM_EXT("Speaker Left", cpcap_spkr_l_mux_enum,
cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
static const struct snd_kcontrol_new cpcap_speaker_right_mux =
SOC_DAPM_ENUM_EXT("Speaker Right", cpcap_spkr_r_mux_enum,
cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
static const struct snd_kcontrol_new cpcap_earpiece_mux =
SOC_DAPM_ENUM_EXT("Earpiece", cpcap_earpiece_mux_enum,
cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
static const struct snd_kcontrol_new cpcap_hifi_mono_mixer_controls[] = {
SOC_DAPM_SINGLE("HiFi Mono Playback Switch",
CPCAP_REG_RXSDOA, CPCAP_BIT_MONO_DAC1, 1, 0),
};
static const struct snd_kcontrol_new cpcap_ext_mono_mixer_controls[] = {
SOC_DAPM_SINGLE("Ext Mono Playback Switch",
CPCAP_REG_RXEPOA, CPCAP_BIT_MONO_EXT0, 1, 0),
};
static const struct snd_kcontrol_new cpcap_extr_mute_control =
SOC_DAPM_SINGLE("Switch",
CPCAP_REG_RXEPOA, CPCAP_BIT_PGA_IN_R_SW, 1, 0);
static const struct snd_kcontrol_new cpcap_extl_mute_control =
SOC_DAPM_SINGLE("Switch",
CPCAP_REG_RXEPOA, CPCAP_BIT_PGA_IN_L_SW, 1, 0);
static const struct snd_kcontrol_new cpcap_voice_loopback =
SOC_DAPM_SINGLE("Switch",
CPCAP_REG_TXI, CPCAP_BIT_DLM, 1, 0);
static const struct snd_soc_dapm_widget cpcap_dapm_widgets[] = {
/* DAIs */
SND_SOC_DAPM_AIF_IN("HiFi RX", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("Voice RX", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("Voice TX", NULL, 0, SND_SOC_NOPM, 0, 0),
/* Power Supply */
SND_SOC_DAPM_REGULATOR_SUPPLY("VAUDIO", SLEEP_ACTIVATE_POWER, 0),
/* Highpass Filters */
SND_SOC_DAPM_REG(snd_soc_dapm_pga, "Highpass Filter RX",
CPCAP_REG_CC, CPCAP_BIT_AUDIHPF_0, 0x3, 0x3, 0x0),
SND_SOC_DAPM_REG(snd_soc_dapm_pga, "Highpass Filter TX",
CPCAP_REG_CC, CPCAP_BIT_AUDOHPF_0, 0x3, 0x3, 0x0),
/* Clocks */
SND_SOC_DAPM_SUPPLY("HiFi DAI Clock",
CPCAP_REG_SDACDI, CPCAP_BIT_ST_CLK_EN, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Voice DAI Clock",
CPCAP_REG_CDI, CPCAP_BIT_CDC_CLK_EN, 0, NULL, 0),
/* Microphone Bias */
SND_SOC_DAPM_SUPPLY("MIC1R Bias",
CPCAP_REG_TXI, CPCAP_BIT_MB_ON1R, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MIC1L Bias",
CPCAP_REG_TXI, CPCAP_BIT_MB_ON1L, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MIC2 Bias",
CPCAP_REG_TXI, CPCAP_BIT_MB_ON2, 0, NULL, 0),
/* Inputs */
SND_SOC_DAPM_INPUT("MICR"),
SND_SOC_DAPM_INPUT("HSMIC"),
SND_SOC_DAPM_INPUT("EMUMIC"),
SND_SOC_DAPM_INPUT("MICL"),
SND_SOC_DAPM_INPUT("EXTR"),
SND_SOC_DAPM_INPUT("EXTL"),
/* Capture Route */
SND_SOC_DAPM_MUX("Right Capture Route",
SND_SOC_NOPM, 0, 0, &cpcap_input_right_mux),
SND_SOC_DAPM_MUX("Left Capture Route",
SND_SOC_NOPM, 0, 0, &cpcap_input_left_mux),
/* Capture PGAs */
SND_SOC_DAPM_PGA("Microphone 1 PGA",
CPCAP_REG_TXI, CPCAP_BIT_MIC1_PGA_EN, 0, NULL, 0),
SND_SOC_DAPM_PGA("Microphone 2 PGA",
CPCAP_REG_TXI, CPCAP_BIT_MIC2_PGA_EN, 0, NULL, 0),
/* ADC */
SND_SOC_DAPM_ADC("ADC Right", NULL,
CPCAP_REG_CC, CPCAP_BIT_MIC1_CDC_EN, 0),
SND_SOC_DAPM_ADC("ADC Left", NULL,
CPCAP_REG_CC, CPCAP_BIT_MIC2_CDC_EN, 0),
/* DAC */
SND_SOC_DAPM_DAC_E("DAC HiFi", NULL,
CPCAP_REG_SDAC, CPCAP_BIT_ST_DAC_EN, 0,
cpcap_st_workaround,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_DAC_E("DAC Voice", NULL,
CPCAP_REG_CC, CPCAP_BIT_CDC_EN_RX, 0,
cpcap_st_workaround,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
/* Playback PGA */
SND_SOC_DAPM_PGA("HiFi PGA",
CPCAP_REG_RXSDOA, CPCAP_BIT_PGA_DAC_EN, 0, NULL, 0),
SND_SOC_DAPM_PGA("Voice PGA",
CPCAP_REG_RXCOA, CPCAP_BIT_PGA_CDC_EN, 0, NULL, 0),
SND_SOC_DAPM_PGA_E("Ext Right PGA",
CPCAP_REG_RXEPOA, CPCAP_BIT_PGA_EXT_R_EN, 0,
NULL, 0,
cpcap_st_workaround,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("Ext Left PGA",
CPCAP_REG_RXEPOA, CPCAP_BIT_PGA_EXT_L_EN, 0,
NULL, 0,
cpcap_st_workaround,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
/* Playback Switch */
SND_SOC_DAPM_SWITCH("Ext Right Enable", SND_SOC_NOPM, 0, 0,
&cpcap_extr_mute_control),
SND_SOC_DAPM_SWITCH("Ext Left Enable", SND_SOC_NOPM, 0, 0,
&cpcap_extl_mute_control),
/* Loopback Switch */
SND_SOC_DAPM_SWITCH("Voice Loopback", SND_SOC_NOPM, 0, 0,
&cpcap_voice_loopback),
/* Mono Mixer */
SOC_MIXER_ARRAY("HiFi Mono Left Mixer", SND_SOC_NOPM, 0, 0,
cpcap_hifi_mono_mixer_controls),
SOC_MIXER_ARRAY("HiFi Mono Right Mixer", SND_SOC_NOPM, 0, 0,
cpcap_hifi_mono_mixer_controls),
SOC_MIXER_ARRAY("Ext Mono Left Mixer", SND_SOC_NOPM, 0, 0,
cpcap_ext_mono_mixer_controls),
SOC_MIXER_ARRAY("Ext Mono Right Mixer", SND_SOC_NOPM, 0, 0,
cpcap_ext_mono_mixer_controls),
/* Output Routes */
SND_SOC_DAPM_MUX("Earpiece Playback Route", SND_SOC_NOPM, 0, 0,
&cpcap_earpiece_mux),
SND_SOC_DAPM_MUX("Speaker Right Playback Route", SND_SOC_NOPM, 0, 0,
&cpcap_speaker_right_mux),
SND_SOC_DAPM_MUX("Speaker Left Playback Route", SND_SOC_NOPM, 0, 0,
&cpcap_speaker_left_mux),
SND_SOC_DAPM_MUX("Lineout Right Playback Route", SND_SOC_NOPM, 0, 0,
&cpcap_line_right_mux),
SND_SOC_DAPM_MUX("Lineout Left Playback Route", SND_SOC_NOPM, 0, 0,
&cpcap_line_left_mux),
SND_SOC_DAPM_MUX("Headset Right Playback Route", SND_SOC_NOPM, 0, 0,
&cpcap_hs_right_mux),
SND_SOC_DAPM_MUX("Headset Left Playback Route", SND_SOC_NOPM, 0, 0,
&cpcap_hs_left_mux),
SND_SOC_DAPM_MUX("EMU Right Playback Route", SND_SOC_NOPM, 0, 0,
&cpcap_emu_right_mux),
SND_SOC_DAPM_MUX("EMU Left Playback Route", SND_SOC_NOPM, 0, 0,
&cpcap_emu_left_mux),
/* Output Amplifier */
SND_SOC_DAPM_PGA("Earpiece PGA",
CPCAP_REG_RXOA, CPCAP_BIT_A1_EAR_EN, 0, NULL, 0),
SND_SOC_DAPM_PGA("Speaker Right PGA",
CPCAP_REG_RXOA, CPCAP_BIT_A2_LDSP_R_EN, 0, NULL, 0),
SND_SOC_DAPM_PGA("Speaker Left PGA",
CPCAP_REG_RXOA, CPCAP_BIT_A2_LDSP_L_EN, 0, NULL, 0),
SND_SOC_DAPM_PGA("Lineout Right PGA",
CPCAP_REG_RXOA, CPCAP_BIT_A4_LINEOUT_R_EN, 0, NULL, 0),
SND_SOC_DAPM_PGA("Lineout Left PGA",
CPCAP_REG_RXOA, CPCAP_BIT_A4_LINEOUT_L_EN, 0, NULL, 0),
SND_SOC_DAPM_PGA("Headset Right PGA",
CPCAP_REG_RXOA, CPCAP_BIT_HS_R_EN, 0, NULL, 0),
SND_SOC_DAPM_PGA("Headset Left PGA",
CPCAP_REG_RXOA, CPCAP_BIT_HS_L_EN, 0, NULL, 0),
SND_SOC_DAPM_PGA("EMU Right PGA",
CPCAP_REG_RXOA, CPCAP_BIT_EMU_SPKR_R_EN, 0, NULL, 0),
SND_SOC_DAPM_PGA("EMU Left PGA",
CPCAP_REG_RXOA, CPCAP_BIT_EMU_SPKR_L_EN, 0, NULL, 0),
/* Headet Charge Pump */
SND_SOC_DAPM_SUPPLY("Headset Charge Pump",
CPCAP_REG_RXOA, CPCAP_BIT_ST_HS_CP_EN, 0, NULL, 0),
/* Outputs */
SND_SOC_DAPM_OUTPUT("EP"),
SND_SOC_DAPM_OUTPUT("SPKR"),
SND_SOC_DAPM_OUTPUT("SPKL"),
SND_SOC_DAPM_OUTPUT("LINER"),
SND_SOC_DAPM_OUTPUT("LINEL"),
SND_SOC_DAPM_OUTPUT("HSR"),
SND_SOC_DAPM_OUTPUT("HSL"),
SND_SOC_DAPM_OUTPUT("EMUR"),
SND_SOC_DAPM_OUTPUT("EMUL"),
};
static const struct snd_soc_dapm_route intercon[] = {
/* Power Supply */
{"HiFi PGA", NULL, "VAUDIO"},
{"Voice PGA", NULL, "VAUDIO"},
{"Ext Right PGA", NULL, "VAUDIO"},
{"Ext Left PGA", NULL, "VAUDIO"},
{"Microphone 1 PGA", NULL, "VAUDIO"},
{"Microphone 2 PGA", NULL, "VAUDIO"},
/* Stream -> AIF */
{"HiFi RX", NULL, "HiFi Playback"},
{"Voice RX", NULL, "Voice Playback"},
{"Voice Capture", NULL, "Voice TX"},
/* AIF clocks */
{"HiFi RX", NULL, "HiFi DAI Clock"},
{"Voice RX", NULL, "Voice DAI Clock"},
{"Voice TX", NULL, "Voice DAI Clock"},
/* Digital Loopback */
{"Voice Loopback", "Switch", "Voice TX"},
{"Voice RX", NULL, "Voice Loopback"},
/* Highpass Filters */
{"Highpass Filter RX", NULL, "Voice RX"},
{"Voice TX", NULL, "Highpass Filter TX"},
/* AIF -> DAC mapping */
{"DAC HiFi", NULL, "HiFi RX"},
{"DAC Voice", NULL, "Highpass Filter RX"},
/* DAC -> PGA */
{"HiFi PGA", NULL, "DAC HiFi"},
{"Voice PGA", NULL, "DAC Voice"},
/* Ext Input -> PGA */
{"Ext Right PGA", NULL, "EXTR"},
{"Ext Left PGA", NULL, "EXTL"},
/* Ext PGA -> Ext Playback Switch */
{"Ext Right Enable", "Switch", "Ext Right PGA"},
{"Ext Left Enable", "Switch", "Ext Left PGA"},
/* HiFi PGA -> Mono Mixer */
{"HiFi Mono Left Mixer", NULL, "HiFi PGA"},
{"HiFi Mono Left Mixer", "HiFi Mono Playback Switch", "HiFi PGA"},
{"HiFi Mono Right Mixer", NULL, "HiFi PGA"},
{"HiFi Mono Right Mixer", "HiFi Mono Playback Switch", "HiFi PGA"},
/* Ext Playback Switch -> Ext Mono Mixer */
{"Ext Mono Right Mixer", NULL, "Ext Right Enable"},
{"Ext Mono Right Mixer", "Ext Mono Playback Switch", "Ext Left Enable"},
{"Ext Mono Left Mixer", NULL, "Ext Left Enable"},
{"Ext Mono Left Mixer", "Ext Mono Playback Switch", "Ext Right Enable"},
/* HiFi Mono Mixer -> Output Route */
{"Earpiece Playback Route", "HiFi", "HiFi Mono Right Mixer"},
{"Speaker Right Playback Route", "HiFi", "HiFi Mono Right Mixer"},
{"Speaker Left Playback Route", "HiFi", "HiFi Mono Left Mixer"},
{"Lineout Right Playback Route", "HiFi", "HiFi Mono Right Mixer"},
{"Lineout Left Playback Route", "HiFi", "HiFi Mono Left Mixer"},
{"Headset Right Playback Route", "HiFi", "HiFi Mono Right Mixer"},
{"Headset Left Playback Route", "HiFi", "HiFi Mono Left Mixer"},
{"EMU Right Playback Route", "HiFi", "HiFi Mono Right Mixer"},
{"EMU Left Playback Route", "HiFi", "HiFi Mono Left Mixer"},
/* Voice PGA -> Output Route */
{"Earpiece Playback Route", "Voice", "Voice PGA"},
{"Speaker Right Playback Route", "Voice", "Voice PGA"},
{"Speaker Left Playback Route", "Voice", "Voice PGA"},
{"Lineout Right Playback Route", "Voice", "Voice PGA"},
{"Lineout Left Playback Route", "Voice", "Voice PGA"},
{"Headset Right Playback Route", "Voice", "Voice PGA"},
{"Headset Left Playback Route", "Voice", "Voice PGA"},
{"EMU Right Playback Route", "Voice", "Voice PGA"},
{"EMU Left Playback Route", "Voice", "Voice PGA"},
/* Ext Mono Mixer -> Output Route */
{"Earpiece Playback Route", "Ext", "Ext Mono Right Mixer"},
{"Speaker Right Playback Route", "Ext", "Ext Mono Right Mixer"},
{"Speaker Left Playback Route", "Ext", "Ext Mono Left Mixer"},
{"Lineout Right Playback Route", "Ext", "Ext Mono Right Mixer"},
{"Lineout Left Playback Route", "Ext", "Ext Mono Left Mixer"},
{"Headset Right Playback Route", "Ext", "Ext Mono Right Mixer"},
{"Headset Left Playback Route", "Ext", "Ext Mono Left Mixer"},
{"EMU Right Playback Route", "Ext", "Ext Mono Right Mixer"},
{"EMU Left Playback Route", "Ext", "Ext Mono Left Mixer"},
/* Output Route -> Output Amplifier */
{"Earpiece PGA", NULL, "Earpiece Playback Route"},
{"Speaker Right PGA", NULL, "Speaker Right Playback Route"},
{"Speaker Left PGA", NULL, "Speaker Left Playback Route"},
{"Lineout Right PGA", NULL, "Lineout Right Playback Route"},
{"Lineout Left PGA", NULL, "Lineout Left Playback Route"},
{"Headset Right PGA", NULL, "Headset Right Playback Route"},
{"Headset Left PGA", NULL, "Headset Left Playback Route"},
{"EMU Right PGA", NULL, "EMU Right Playback Route"},
{"EMU Left PGA", NULL, "EMU Left Playback Route"},
/* Output Amplifier -> Output */
{"EP", NULL, "Earpiece PGA"},
{"SPKR", NULL, "Speaker Right PGA"},
{"SPKL", NULL, "Speaker Left PGA"},
{"LINER", NULL, "Lineout Right PGA"},
{"LINEL", NULL, "Lineout Left PGA"},
{"HSR", NULL, "Headset Right PGA"},
{"HSL", NULL, "Headset Left PGA"},
{"EMUR", NULL, "EMU Right PGA"},
{"EMUL", NULL, "EMU Left PGA"},
/* Headset Charge Pump -> Headset */
{"HSR", NULL, "Headset Charge Pump"},
{"HSL", NULL, "Headset Charge Pump"},
/* Mic -> Mic Route */
{"Right Capture Route", "Mic 1", "MICR"},
{"Right Capture Route", "Headset Mic", "HSMIC"},
{"Right Capture Route", "EMU Mic", "EMUMIC"},
{"Right Capture Route", "Ext Right", "EXTR"},
{"Left Capture Route", "Mic 2", "MICL"},
{"Left Capture Route", "Ext Left", "EXTL"},
/* Input Route -> Microphone PGA */
{"Microphone 1 PGA", NULL, "Right Capture Route"},
{"Microphone 2 PGA", NULL, "Left Capture Route"},
/* Microphone PGA -> ADC */
{"ADC Right", NULL, "Microphone 1 PGA"},
{"ADC Left", NULL, "Microphone 2 PGA"},
/* ADC -> Stream */
{"Highpass Filter TX", NULL, "ADC Right"},
{"Highpass Filter TX", NULL, "ADC Left"},
/* Mic Bias */
{"MICL", NULL, "MIC1L Bias"},
{"MICR", NULL, "MIC1R Bias"},
};
static int cpcap_set_sysclk(struct cpcap_audio *cpcap, enum cpcap_dai dai,
int clk_id, int freq)
{
u16 clkfreqreg, clkfreqshift;
u16 clkfreqmask, clkfreqval;
u16 clkidreg, clkidshift;
u16 mask, val;
int err;
switch (dai) {
case CPCAP_DAI_HIFI:
clkfreqreg = CPCAP_REG_SDAC;
clkfreqshift = CPCAP_BIT_ST_DAC_CLK0;
clkidreg = CPCAP_REG_SDACDI;
clkidshift = CPCAP_BIT_ST_DAC_CLK_IN_SEL;
break;
case CPCAP_DAI_VOICE:
clkfreqreg = CPCAP_REG_CC;
clkfreqshift = CPCAP_BIT_CDC_CLK0;
clkidreg = CPCAP_REG_CDI;
clkidshift = CPCAP_BIT_CLK_IN_SEL;
break;
default:
dev_err(cpcap->component->dev, "invalid DAI: %d", dai);
return -EINVAL;
}
/* setup clk id */
if (clk_id < 0 || clk_id > 1) {
dev_err(cpcap->component->dev, "invalid clk id %d", clk_id);
return -EINVAL;
}
err = regmap_update_bits(cpcap->regmap, clkidreg, BIT(clkidshift),
clk_id ? BIT(clkidshift) : 0);
if (err)
return err;
/* enable PLL for Voice DAI */
if (dai == CPCAP_DAI_VOICE) {
mask = BIT(CPCAP_BIT_CDC_PLL_SEL);
val = BIT(CPCAP_BIT_CDC_PLL_SEL);
err = regmap_update_bits(cpcap->regmap, CPCAP_REG_CDI,
mask, val);
if (err)
return err;
}
/* setup frequency */
clkfreqmask = 0x7 << clkfreqshift;
switch (freq) {
case 15360000:
clkfreqval = 0x01 << clkfreqshift;
break;
case 16800000:
clkfreqval = 0x02 << clkfreqshift;
break;
case 19200000:
clkfreqval = 0x03 << clkfreqshift;
break;
case 26000000:
clkfreqval = 0x04 << clkfreqshift;
break;
case 33600000:
clkfreqval = 0x05 << clkfreqshift;
break;
case 38400000:
clkfreqval = 0x06 << clkfreqshift;
break;
default:
dev_err(cpcap->component->dev, "unsupported freq %u", freq);
return -EINVAL;
}
err = regmap_update_bits(cpcap->regmap, clkfreqreg,
clkfreqmask, clkfreqval);
if (err)
return err;
if (dai == CPCAP_DAI_VOICE) {
cpcap->codec_clk_id = clk_id;
cpcap->codec_freq = freq;
}
return 0;
}
static int cpcap_set_samprate(struct cpcap_audio *cpcap, enum cpcap_dai dai,
int samplerate)
{
struct snd_soc_component *component = cpcap->component;
u16 sampreg, sampmask, sampshift, sampval, sampreset;
int err, sampreadval;
switch (dai) {
case CPCAP_DAI_HIFI:
sampreg = CPCAP_REG_SDAC;
sampshift = CPCAP_BIT_ST_SR0;
sampreset = BIT(CPCAP_BIT_DF_RESET_ST_DAC) |
BIT(CPCAP_BIT_ST_CLOCK_TREE_RESET);
break;
case CPCAP_DAI_VOICE:
sampreg = CPCAP_REG_CC;
sampshift = CPCAP_BIT_CDC_SR0;
sampreset = BIT(CPCAP_BIT_DF_RESET) |
BIT(CPCAP_BIT_CDC_CLOCK_TREE_RESET);
break;
default:
dev_err(component->dev, "invalid DAI: %d", dai);
return -EINVAL;
}
sampmask = 0xF << sampshift | sampreset;
switch (samplerate) {
case 48000:
sampval = 0x8 << sampshift;
break;
case 44100:
sampval = 0x7 << sampshift;
break;
case 32000:
sampval = 0x6 << sampshift;
break;
case 24000:
sampval = 0x5 << sampshift;
break;
case 22050:
sampval = 0x4 << sampshift;
break;
case 16000:
sampval = 0x3 << sampshift;
break;
case 12000:
sampval = 0x2 << sampshift;
break;
case 11025:
sampval = 0x1 << sampshift;
break;
case 8000:
sampval = 0x0 << sampshift;
break;
default:
dev_err(component->dev, "unsupported samplerate %d", samplerate);
return -EINVAL;
}
err = regmap_update_bits(cpcap->regmap, sampreg,
sampmask, sampval | sampreset);
if (err)
return err;
/* Wait for clock tree reset to complete */
mdelay(CLOCK_TREE_RESET_TIME);
err = regmap_read(cpcap->regmap, sampreg, &sampreadval);
if (err)
return err;
if (sampreadval & sampreset) {
dev_err(component->dev, "reset self-clear failed: %04x",
sampreadval);
return -EIO;
}
return 0;
}
static int cpcap_hifi_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
int rate = params_rate(params);
dev_dbg(component->dev, "HiFi setup HW params: rate=%d", rate);
return cpcap_set_samprate(cpcap, CPCAP_DAI_HIFI, rate);
}
static int cpcap_hifi_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id,
unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
struct device *dev = component->dev;
dev_dbg(dev, "HiFi setup sysclk: clk_id=%u, freq=%u", clk_id, freq);
return cpcap_set_sysclk(cpcap, CPCAP_DAI_HIFI, clk_id, freq);
}
static int cpcap_hifi_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
struct device *dev = component->dev;
static const u16 reg = CPCAP_REG_SDACDI;
static const u16 mask =
BIT(CPCAP_BIT_SMB_ST_DAC) |
BIT(CPCAP_BIT_ST_CLK_INV) |
BIT(CPCAP_BIT_ST_FS_INV) |
BIT(CPCAP_BIT_ST_DIG_AUD_FS0) |
BIT(CPCAP_BIT_ST_DIG_AUD_FS1) |
BIT(CPCAP_BIT_ST_L_TIMESLOT0) |
BIT(CPCAP_BIT_ST_L_TIMESLOT1) |
BIT(CPCAP_BIT_ST_L_TIMESLOT2) |
BIT(CPCAP_BIT_ST_R_TIMESLOT0) |
BIT(CPCAP_BIT_ST_R_TIMESLOT1) |
BIT(CPCAP_BIT_ST_R_TIMESLOT2);
u16 val = 0x0000;
dev_dbg(dev, "HiFi setup dai format (%08x)", fmt);
/*
* "HiFi Playback" should always be configured as
* SND_SOC_DAIFMT_CBP_CFP - codec clk & frm provider
* SND_SOC_DAIFMT_I2S - I2S mode
*/
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
val &= ~BIT(CPCAP_BIT_SMB_ST_DAC);
break;
default:
dev_err(dev, "HiFi dai fmt failed: CPCAP should be provider");
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_IB_IF:
val |= BIT(CPCAP_BIT_ST_FS_INV);
val |= BIT(CPCAP_BIT_ST_CLK_INV);
break;
case SND_SOC_DAIFMT_IB_NF:
val &= ~BIT(CPCAP_BIT_ST_FS_INV);
val |= BIT(CPCAP_BIT_ST_CLK_INV);
break;
case SND_SOC_DAIFMT_NB_IF:
val |= BIT(CPCAP_BIT_ST_FS_INV);
val &= ~BIT(CPCAP_BIT_ST_CLK_INV);
break;
case SND_SOC_DAIFMT_NB_NF:
val &= ~BIT(CPCAP_BIT_ST_FS_INV);
val &= ~BIT(CPCAP_BIT_ST_CLK_INV);
break;
default:
dev_err(dev, "HiFi dai fmt failed: unsupported clock invert mode");
return -EINVAL;
}
if (val & BIT(CPCAP_BIT_ST_CLK_INV))
val &= ~BIT(CPCAP_BIT_ST_CLK_INV);
else
val |= BIT(CPCAP_BIT_ST_CLK_INV);
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
val |= BIT(CPCAP_BIT_ST_DIG_AUD_FS0);
val |= BIT(CPCAP_BIT_ST_DIG_AUD_FS1);
break;
default:
/* 01 - 4 slots network mode */
val |= BIT(CPCAP_BIT_ST_DIG_AUD_FS0);
val &= ~BIT(CPCAP_BIT_ST_DIG_AUD_FS1);
/* L on slot 1 */
val |= BIT(CPCAP_BIT_ST_L_TIMESLOT0);
break;
}
dev_dbg(dev, "HiFi dai format: val=%04x", val);
return regmap_update_bits(cpcap->regmap, reg, mask, val);
}
static int cpcap_hifi_set_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
static const u16 reg = CPCAP_REG_RXSDOA;
static const u16 mask = BIT(CPCAP_BIT_ST_DAC_SW);
u16 val;
if (mute)
val = 0;
else
val = BIT(CPCAP_BIT_ST_DAC_SW);
dev_dbg(component->dev, "HiFi mute: %d", mute);
return regmap_update_bits(cpcap->regmap, reg, mask, val);
}
static const struct snd_soc_dai_ops cpcap_dai_hifi_ops = {
.hw_params = cpcap_hifi_hw_params,
.set_sysclk = cpcap_hifi_set_dai_sysclk,
.set_fmt = cpcap_hifi_set_dai_fmt,
.mute_stream = cpcap_hifi_set_mute,
.no_capture_mute = 1,
};
static int cpcap_voice_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct device *dev = component->dev;
struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
static const u16 reg_cdi = CPCAP_REG_CDI;
int rate = params_rate(params);
int channels = params_channels(params);
int direction = substream->stream;
u16 val, mask;
int err;
dev_dbg(dev, "Voice setup HW params: rate=%d, direction=%d, chan=%d",
rate, direction, channels);
err = cpcap_set_samprate(cpcap, CPCAP_DAI_VOICE, rate);
if (err)
return err;
if (direction == SNDRV_PCM_STREAM_CAPTURE) {
mask = 0x0000;
mask |= BIT(CPCAP_BIT_MIC1_RX_TIMESLOT0);
mask |= BIT(CPCAP_BIT_MIC1_RX_TIMESLOT1);
mask |= BIT(CPCAP_BIT_MIC1_RX_TIMESLOT2);
mask |= BIT(CPCAP_BIT_MIC2_TIMESLOT0);
mask |= BIT(CPCAP_BIT_MIC2_TIMESLOT1);
mask |= BIT(CPCAP_BIT_MIC2_TIMESLOT2);
val = 0x0000;
if (channels >= 2)
val = BIT(CPCAP_BIT_MIC1_RX_TIMESLOT0);
err = regmap_update_bits(cpcap->regmap, reg_cdi, mask, val);
if (err)
return err;
}
return 0;
}
static int cpcap_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id,
unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
dev_dbg(component->dev, "Voice setup sysclk: clk_id=%u, freq=%u",
clk_id, freq);
return cpcap_set_sysclk(cpcap, CPCAP_DAI_VOICE, clk_id, freq);
}
static int cpcap_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
static const u16 mask = BIT(CPCAP_BIT_SMB_CDC) |
BIT(CPCAP_BIT_CLK_INV) |
BIT(CPCAP_BIT_FS_INV) |
BIT(CPCAP_BIT_CDC_DIG_AUD_FS0) |
BIT(CPCAP_BIT_CDC_DIG_AUD_FS1);
u16 val = 0x0000;
int err;
dev_dbg(component->dev, "Voice setup dai format (%08x)", fmt);
/*
* "Voice Playback" and "Voice Capture" should always be
* configured as SND_SOC_DAIFMT_CBP_CFP - codec clk & frm
* provider
*/
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
val &= ~BIT(CPCAP_BIT_SMB_CDC);
break;
default:
dev_err(component->dev, "Voice dai fmt failed: CPCAP should be the provider");
val &= ~BIT(CPCAP_BIT_SMB_CDC);
break;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_IB_IF:
val |= BIT(CPCAP_BIT_CLK_INV);
val |= BIT(CPCAP_BIT_FS_INV);
break;
case SND_SOC_DAIFMT_IB_NF:
val |= BIT(CPCAP_BIT_CLK_INV);
val &= ~BIT(CPCAP_BIT_FS_INV);
break;
case SND_SOC_DAIFMT_NB_IF:
val &= ~BIT(CPCAP_BIT_CLK_INV);
val |= BIT(CPCAP_BIT_FS_INV);
break;
case SND_SOC_DAIFMT_NB_NF:
val &= ~BIT(CPCAP_BIT_CLK_INV);
val &= ~BIT(CPCAP_BIT_FS_INV);
break;
default:
dev_err(component->dev, "Voice dai fmt failed: unsupported clock invert mode");
break;
}
if (val & BIT(CPCAP_BIT_CLK_INV))
val &= ~BIT(CPCAP_BIT_CLK_INV);
else
val |= BIT(CPCAP_BIT_CLK_INV);
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
/* 11 - true I2S mode */
val |= BIT(CPCAP_BIT_CDC_DIG_AUD_FS0);
val |= BIT(CPCAP_BIT_CDC_DIG_AUD_FS1);
break;
default:
/* 4 timeslots network mode */
val |= BIT(CPCAP_BIT_CDC_DIG_AUD_FS0);
val &= ~BIT(CPCAP_BIT_CDC_DIG_AUD_FS1);
break;
}
dev_dbg(component->dev, "Voice dai format: val=%04x", val);
err = regmap_update_bits(cpcap->regmap, CPCAP_REG_CDI, mask, val);
if (err)
return err;
cpcap->codec_format = val;
return 0;
}
/*
* Configure codec for voice call if requested.
*
* We can configure most with snd_soc_dai_set_sysclk(), snd_soc_dai_set_fmt()
* and snd_soc_dai_set_tdm_slot(). This function configures the rest of the
* cpcap related hardware as CPU is not involved in the voice call.
*/
static int cpcap_voice_call(struct cpcap_audio *cpcap, struct snd_soc_dai *dai,
bool voice_call)
{
int mask, err;
/* Modem to codec VAUDIO_MODE1 */
mask = BIT(CPCAP_BIT_VAUDIO_MODE1);
err = regmap_update_bits(cpcap->regmap, CPCAP_REG_VAUDIOC,
mask, voice_call ? mask : 0);
if (err)
return err;
/* Clear MIC1_MUX for call */
mask = BIT(CPCAP_BIT_MIC1_MUX);
err = regmap_update_bits(cpcap->regmap, CPCAP_REG_TXI,
mask, voice_call ? 0 : mask);
if (err)
return err;
/* Set MIC2_MUX for call */
mask = BIT(CPCAP_BIT_MB_ON1L) | BIT(CPCAP_BIT_MB_ON1R) |
BIT(CPCAP_BIT_MIC2_MUX) | BIT(CPCAP_BIT_MIC2_PGA_EN);
err = regmap_update_bits(cpcap->regmap, CPCAP_REG_TXI,
mask, voice_call ? mask : 0);
if (err)
return err;
/* Enable LDSP for call */
mask = BIT(CPCAP_BIT_A2_LDSP_L_EN) | BIT(CPCAP_BIT_A2_LDSP_R_EN);
err = regmap_update_bits(cpcap->regmap, CPCAP_REG_RXOA,
mask, voice_call ? mask : 0);
if (err)
return err;
/* Enable CPCAP_BIT_PGA_CDC_EN for call */
mask = BIT(CPCAP_BIT_PGA_CDC_EN);
err = regmap_update_bits(cpcap->regmap, CPCAP_REG_RXCOA,
mask, voice_call ? mask : 0);
if (err)
return err;
/* Unmute voice for call */
if (dai) {
err = snd_soc_dai_digital_mute(dai, !voice_call,
SNDRV_PCM_STREAM_PLAYBACK);
if (err)
return err;
}
/* Set modem to codec mic CDC and HPF for call */
mask = BIT(CPCAP_BIT_MIC2_CDC_EN) | BIT(CPCAP_BIT_CDC_EN_RX) |
BIT(CPCAP_BIT_AUDOHPF_1) | BIT(CPCAP_BIT_AUDOHPF_0) |
BIT(CPCAP_BIT_AUDIHPF_1) | BIT(CPCAP_BIT_AUDIHPF_0);
err = regmap_update_bits(cpcap->regmap, CPCAP_REG_CC,
mask, voice_call ? mask : 0);
if (err)
return err;
/* Enable modem to codec CDC for call*/
mask = BIT(CPCAP_BIT_CDC_CLK_EN);
err = regmap_update_bits(cpcap->regmap, CPCAP_REG_CDI,
mask, voice_call ? mask : 0);
return err;
}
static int cpcap_voice_set_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask,
int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
int err, ts_mask, mask;
bool voice_call;
/*
* Primitive test for voice call, probably needs more checks
* later on for 16-bit calls detected, Bluetooth headset etc.
*/
if (tx_mask == 0 && rx_mask == 1 && slot_width == 8)
voice_call = true;
else
voice_call = false;
ts_mask = 0x7 << CPCAP_BIT_MIC2_TIMESLOT0;
ts_mask |= 0x7 << CPCAP_BIT_MIC1_RX_TIMESLOT0;
mask = (tx_mask & 0x7) << CPCAP_BIT_MIC2_TIMESLOT0;
mask |= (rx_mask & 0x7) << CPCAP_BIT_MIC1_RX_TIMESLOT0;
err = regmap_update_bits(cpcap->regmap, CPCAP_REG_CDI,
ts_mask, mask);
if (err)
return err;
err = cpcap_set_samprate(cpcap, CPCAP_DAI_VOICE, slot_width * 1000);
if (err)
return err;
err = cpcap_voice_call(cpcap, dai, voice_call);
if (err)
return err;
return 0;
}
static int cpcap_voice_set_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
static const u16 reg = CPCAP_REG_RXCOA;
static const u16 mask = BIT(CPCAP_BIT_CDC_SW);
u16 val;
if (mute)
val = 0;
else
val = BIT(CPCAP_BIT_CDC_SW);
dev_dbg(component->dev, "Voice mute: %d", mute);
return regmap_update_bits(cpcap->regmap, reg, mask, val);
};
static const struct snd_soc_dai_ops cpcap_dai_voice_ops = {
.hw_params = cpcap_voice_hw_params,
.set_sysclk = cpcap_voice_set_dai_sysclk,
.set_fmt = cpcap_voice_set_dai_fmt,
.set_tdm_slot = cpcap_voice_set_tdm_slot,
.mute_stream = cpcap_voice_set_mute,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver cpcap_dai[] = {
{
.id = 0,
.name = "cpcap-hifi",
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE,
},
.ops = &cpcap_dai_hifi_ops,
},
{
.id = 1,
.name = "cpcap-voice",
.playback = {
.stream_name = "Voice Playback",
.channels_min = 1,
.channels_max = 1,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.capture = {
.stream_name = "Voice Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.ops = &cpcap_dai_voice_ops,
},
};
static int cpcap_dai_mux(struct cpcap_audio *cpcap, bool swap_dai_configuration)
{
u16 hifi_val, voice_val;
u16 hifi_mask = BIT(CPCAP_BIT_DIG_AUD_IN_ST_DAC);
u16 voice_mask = BIT(CPCAP_BIT_DIG_AUD_IN);
int err;
if (!swap_dai_configuration) {
/* Codec on DAI0, HiFi on DAI1 */
voice_val = 0;
hifi_val = hifi_mask;
} else {
/* Codec on DAI1, HiFi on DAI0 */
voice_val = voice_mask;
hifi_val = 0;
}
err = regmap_update_bits(cpcap->regmap, CPCAP_REG_CDI,
voice_mask, voice_val);
if (err)
return err;
err = regmap_update_bits(cpcap->regmap, CPCAP_REG_SDACDI,
hifi_mask, hifi_val);
if (err)
return err;
return 0;
}
static int cpcap_audio_reset(struct snd_soc_component *component,
bool swap_dai_configuration)
{
struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
int i, err = 0;
dev_dbg(component->dev, "init audio codec");
for (i = 0; i < ARRAY_SIZE(cpcap_default_regs); i++) {
err = regmap_update_bits(cpcap->regmap,
cpcap_default_regs[i].reg,
cpcap_default_regs[i].mask,
cpcap_default_regs[i].val);
if (err)
return err;
}
/* setup default settings */
err = cpcap_dai_mux(cpcap, swap_dai_configuration);
if (err)
return err;
err = cpcap_set_sysclk(cpcap, CPCAP_DAI_HIFI, 0, 26000000);
if (err)
return err;
err = cpcap_set_sysclk(cpcap, CPCAP_DAI_VOICE, 0, 26000000);
if (err)
return err;
err = cpcap_set_samprate(cpcap, CPCAP_DAI_HIFI, 48000);
if (err)
return err;
err = cpcap_set_samprate(cpcap, CPCAP_DAI_VOICE, 48000);
if (err)
return err;
return 0;
}
static int cpcap_soc_probe(struct snd_soc_component *component)
{
struct cpcap_audio *cpcap;
int err;
cpcap = devm_kzalloc(component->dev, sizeof(*cpcap), GFP_KERNEL);
if (!cpcap)
return -ENOMEM;
snd_soc_component_set_drvdata(component, cpcap);
cpcap->component = component;
cpcap->regmap = dev_get_regmap(component->dev->parent, NULL);
if (!cpcap->regmap)
return -ENODEV;
snd_soc_component_init_regmap(component, cpcap->regmap);
err = cpcap_get_vendor(component->dev, cpcap->regmap, &cpcap->vendor);
if (err)
return err;
return cpcap_audio_reset(component, false);
}
static struct snd_soc_component_driver soc_codec_dev_cpcap = {
.probe = cpcap_soc_probe,
.controls = cpcap_snd_controls,
.num_controls = ARRAY_SIZE(cpcap_snd_controls),
.dapm_widgets = cpcap_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(cpcap_dapm_widgets),
.dapm_routes = intercon,
.num_dapm_routes = ARRAY_SIZE(intercon),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int cpcap_codec_probe(struct platform_device *pdev)
{
struct device_node *codec_node =
of_get_child_by_name(pdev->dev.parent->of_node, "audio-codec");
if (!codec_node)
return -ENODEV;
pdev->dev.of_node = codec_node;
return devm_snd_soc_register_component(&pdev->dev, &soc_codec_dev_cpcap,
cpcap_dai, ARRAY_SIZE(cpcap_dai));
}
static struct platform_driver cpcap_codec_driver = {
.probe = cpcap_codec_probe,
.driver = {
.name = "cpcap-codec",
},
};
module_platform_driver(cpcap_codec_driver);
MODULE_ALIAS("platform:cpcap-codec");
MODULE_DESCRIPTION("ASoC CPCAP codec driver");
MODULE_AUTHOR("Sebastian Reichel");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/cpcap.c |
// SPDX-License-Identifier: GPL-2.0
//
// Analog Devices ADAU7118 8 channel PDM-to-I2S/TDM Converter Standalone Hw
// driver
//
// Copyright 2019 Analog Devices Inc.
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "adau7118.h"
static int adau7118_probe_hw(struct platform_device *pdev)
{
return adau7118_probe(&pdev->dev, NULL, true);
}
static const struct of_device_id adau7118_of_match[] = {
{ .compatible = "adi,adau7118" },
{}
};
MODULE_DEVICE_TABLE(of, adau7118_of_match);
static const struct platform_device_id adau7118_id[] = {
{ .name = "adau7118" },
{ }
};
MODULE_DEVICE_TABLE(platform, adau7118_id);
static struct platform_driver adau7118_driver_hw = {
.driver = {
.name = "adau7118",
.of_match_table = adau7118_of_match,
},
.probe = adau7118_probe_hw,
.id_table = adau7118_id,
};
module_platform_driver(adau7118_driver_hw);
MODULE_AUTHOR("Nuno Sa <[email protected]>");
MODULE_DESCRIPTION("ADAU7118 8 channel PDM-to-I2S/TDM Converter driver for standalone hw mode");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/adau7118-hw.c |
// SPDX-License-Identifier: GPL-2.0
//
// rk3328 ALSA SoC Audio driver
//
// Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd All rights reserved.
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
#include <sound/dmaengine_pcm.h>
#include <sound/pcm_params.h>
#include "rk3328_codec.h"
/*
* volume setting
* 0: -39dB
* 26: 0dB
* 31: 6dB
* Step: 1.5dB
*/
#define OUT_VOLUME (0x18)
#define RK3328_GRF_SOC_CON2 (0x0408)
#define RK3328_GRF_SOC_CON10 (0x0428)
#define INITIAL_FREQ (11289600)
struct rk3328_codec_priv {
struct regmap *regmap;
struct gpio_desc *mute;
struct clk *mclk;
struct clk *pclk;
unsigned int sclk;
int spk_depop_time; /* msec */
};
static const struct reg_default rk3328_codec_reg_defaults[] = {
{ CODEC_RESET, 0x03 },
{ DAC_INIT_CTRL1, 0x00 },
{ DAC_INIT_CTRL2, 0x50 },
{ DAC_INIT_CTRL3, 0x0e },
{ DAC_PRECHARGE_CTRL, 0x01 },
{ DAC_PWR_CTRL, 0x00 },
{ DAC_CLK_CTRL, 0x00 },
{ HPMIX_CTRL, 0x00 },
{ HPOUT_CTRL, 0x00 },
{ HPOUTL_GAIN_CTRL, 0x00 },
{ HPOUTR_GAIN_CTRL, 0x00 },
{ HPOUT_POP_CTRL, 0x11 },
};
static int rk3328_codec_reset(struct rk3328_codec_priv *rk3328)
{
regmap_write(rk3328->regmap, CODEC_RESET, 0x00);
mdelay(10);
regmap_write(rk3328->regmap, CODEC_RESET, 0x03);
return 0;
}
static int rk3328_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct rk3328_codec_priv *rk3328 =
snd_soc_component_get_drvdata(dai->component);
unsigned int val;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC:
val = PIN_DIRECTION_IN | DAC_I2S_MODE_SLAVE;
break;
case SND_SOC_DAIFMT_CBP_CFP:
val = PIN_DIRECTION_OUT | DAC_I2S_MODE_MASTER;
break;
default:
return -EINVAL;
}
regmap_update_bits(rk3328->regmap, DAC_INIT_CTRL1,
PIN_DIRECTION_MASK | DAC_I2S_MODE_MASK, val);
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B:
val = DAC_MODE_PCM;
break;
case SND_SOC_DAIFMT_I2S:
val = DAC_MODE_I2S;
break;
case SND_SOC_DAIFMT_RIGHT_J:
val = DAC_MODE_RJM;
break;
case SND_SOC_DAIFMT_LEFT_J:
val = DAC_MODE_LJM;
break;
default:
return -EINVAL;
}
regmap_update_bits(rk3328->regmap, DAC_INIT_CTRL2,
DAC_MODE_MASK, val);
return 0;
}
static int rk3328_mute_stream(struct snd_soc_dai *dai, int mute, int direction)
{
struct rk3328_codec_priv *rk3328 =
snd_soc_component_get_drvdata(dai->component);
unsigned int val;
if (mute)
val = HPOUTL_MUTE | HPOUTR_MUTE;
else
val = HPOUTL_UNMUTE | HPOUTR_UNMUTE;
regmap_update_bits(rk3328->regmap, HPOUT_CTRL,
HPOUTL_MUTE_MASK | HPOUTR_MUTE_MASK, val);
return 0;
}
static int rk3328_codec_power_on(struct rk3328_codec_priv *rk3328, int wait_ms)
{
regmap_update_bits(rk3328->regmap, DAC_PRECHARGE_CTRL,
DAC_CHARGE_XCHARGE_MASK, DAC_CHARGE_PRECHARGE);
mdelay(10);
regmap_update_bits(rk3328->regmap, DAC_PRECHARGE_CTRL,
DAC_CHARGE_CURRENT_ALL_MASK,
DAC_CHARGE_CURRENT_ALL_ON);
mdelay(wait_ms);
return 0;
}
static int rk3328_codec_power_off(struct rk3328_codec_priv *rk3328, int wait_ms)
{
regmap_update_bits(rk3328->regmap, DAC_PRECHARGE_CTRL,
DAC_CHARGE_XCHARGE_MASK, DAC_CHARGE_DISCHARGE);
mdelay(10);
regmap_update_bits(rk3328->regmap, DAC_PRECHARGE_CTRL,
DAC_CHARGE_CURRENT_ALL_MASK,
DAC_CHARGE_CURRENT_ALL_ON);
mdelay(wait_ms);
return 0;
}
static const struct rk3328_reg_msk_val playback_open_list[] = {
{ DAC_PWR_CTRL, DAC_PWR_MASK, DAC_PWR_ON },
{ DAC_PWR_CTRL, DACL_PATH_REFV_MASK | DACR_PATH_REFV_MASK,
DACL_PATH_REFV_ON | DACR_PATH_REFV_ON },
{ DAC_PWR_CTRL, HPOUTL_ZERO_CROSSING_MASK | HPOUTR_ZERO_CROSSING_MASK,
HPOUTL_ZERO_CROSSING_ON | HPOUTR_ZERO_CROSSING_ON },
{ HPOUT_POP_CTRL, HPOUTR_POP_MASK | HPOUTL_POP_MASK,
HPOUTR_POP_WORK | HPOUTL_POP_WORK },
{ HPMIX_CTRL, HPMIXL_MASK | HPMIXR_MASK, HPMIXL_EN | HPMIXR_EN },
{ HPMIX_CTRL, HPMIXL_INIT_MASK | HPMIXR_INIT_MASK,
HPMIXL_INIT_EN | HPMIXR_INIT_EN },
{ HPOUT_CTRL, HPOUTL_MASK | HPOUTR_MASK, HPOUTL_EN | HPOUTR_EN },
{ HPOUT_CTRL, HPOUTL_INIT_MASK | HPOUTR_INIT_MASK,
HPOUTL_INIT_EN | HPOUTR_INIT_EN },
{ DAC_CLK_CTRL, DACL_REFV_MASK | DACR_REFV_MASK,
DACL_REFV_ON | DACR_REFV_ON },
{ DAC_CLK_CTRL, DACL_CLK_MASK | DACR_CLK_MASK,
DACL_CLK_ON | DACR_CLK_ON },
{ DAC_CLK_CTRL, DACL_MASK | DACR_MASK, DACL_ON | DACR_ON },
{ DAC_CLK_CTRL, DACL_INIT_MASK | DACR_INIT_MASK,
DACL_INIT_ON | DACR_INIT_ON },
{ DAC_SELECT, DACL_SELECT_MASK | DACR_SELECT_MASK,
DACL_SELECT | DACR_SELECT },
{ HPMIX_CTRL, HPMIXL_INIT2_MASK | HPMIXR_INIT2_MASK,
HPMIXL_INIT2_EN | HPMIXR_INIT2_EN },
{ HPOUT_CTRL, HPOUTL_MUTE_MASK | HPOUTR_MUTE_MASK,
HPOUTL_UNMUTE | HPOUTR_UNMUTE },
};
static int rk3328_codec_open_playback(struct rk3328_codec_priv *rk3328)
{
int i;
regmap_update_bits(rk3328->regmap, DAC_PRECHARGE_CTRL,
DAC_CHARGE_CURRENT_ALL_MASK,
DAC_CHARGE_CURRENT_I);
for (i = 0; i < ARRAY_SIZE(playback_open_list); i++) {
regmap_update_bits(rk3328->regmap,
playback_open_list[i].reg,
playback_open_list[i].msk,
playback_open_list[i].val);
mdelay(1);
}
msleep(rk3328->spk_depop_time);
gpiod_set_value(rk3328->mute, 0);
regmap_update_bits(rk3328->regmap, HPOUTL_GAIN_CTRL,
HPOUTL_GAIN_MASK, OUT_VOLUME);
regmap_update_bits(rk3328->regmap, HPOUTR_GAIN_CTRL,
HPOUTR_GAIN_MASK, OUT_VOLUME);
return 0;
}
static const struct rk3328_reg_msk_val playback_close_list[] = {
{ HPMIX_CTRL, HPMIXL_INIT2_MASK | HPMIXR_INIT2_MASK,
HPMIXL_INIT2_DIS | HPMIXR_INIT2_DIS },
{ DAC_SELECT, DACL_SELECT_MASK | DACR_SELECT_MASK,
DACL_UNSELECT | DACR_UNSELECT },
{ HPOUT_CTRL, HPOUTL_MUTE_MASK | HPOUTR_MUTE_MASK,
HPOUTL_MUTE | HPOUTR_MUTE },
{ HPOUT_CTRL, HPOUTL_INIT_MASK | HPOUTR_INIT_MASK,
HPOUTL_INIT_DIS | HPOUTR_INIT_DIS },
{ HPOUT_CTRL, HPOUTL_MASK | HPOUTR_MASK, HPOUTL_DIS | HPOUTR_DIS },
{ HPMIX_CTRL, HPMIXL_MASK | HPMIXR_MASK, HPMIXL_DIS | HPMIXR_DIS },
{ DAC_CLK_CTRL, DACL_MASK | DACR_MASK, DACL_OFF | DACR_OFF },
{ DAC_CLK_CTRL, DACL_CLK_MASK | DACR_CLK_MASK,
DACL_CLK_OFF | DACR_CLK_OFF },
{ DAC_CLK_CTRL, DACL_REFV_MASK | DACR_REFV_MASK,
DACL_REFV_OFF | DACR_REFV_OFF },
{ HPOUT_POP_CTRL, HPOUTR_POP_MASK | HPOUTL_POP_MASK,
HPOUTR_POP_XCHARGE | HPOUTL_POP_XCHARGE },
{ DAC_PWR_CTRL, DACL_PATH_REFV_MASK | DACR_PATH_REFV_MASK,
DACL_PATH_REFV_OFF | DACR_PATH_REFV_OFF },
{ DAC_PWR_CTRL, DAC_PWR_MASK, DAC_PWR_OFF },
{ HPMIX_CTRL, HPMIXL_INIT_MASK | HPMIXR_INIT_MASK,
HPMIXL_INIT_DIS | HPMIXR_INIT_DIS },
{ DAC_CLK_CTRL, DACL_INIT_MASK | DACR_INIT_MASK,
DACL_INIT_OFF | DACR_INIT_OFF },
};
static int rk3328_codec_close_playback(struct rk3328_codec_priv *rk3328)
{
size_t i;
gpiod_set_value(rk3328->mute, 1);
regmap_update_bits(rk3328->regmap, HPOUTL_GAIN_CTRL,
HPOUTL_GAIN_MASK, 0);
regmap_update_bits(rk3328->regmap, HPOUTR_GAIN_CTRL,
HPOUTR_GAIN_MASK, 0);
for (i = 0; i < ARRAY_SIZE(playback_close_list); i++) {
regmap_update_bits(rk3328->regmap,
playback_close_list[i].reg,
playback_close_list[i].msk,
playback_close_list[i].val);
mdelay(1);
}
/* Workaround for silence when changed Fs 48 -> 44.1kHz */
rk3328_codec_reset(rk3328);
regmap_update_bits(rk3328->regmap, DAC_PRECHARGE_CTRL,
DAC_CHARGE_CURRENT_ALL_MASK,
DAC_CHARGE_CURRENT_ALL_ON);
return 0;
}
static int rk3328_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct rk3328_codec_priv *rk3328 =
snd_soc_component_get_drvdata(dai->component);
unsigned int val = 0;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
val = DAC_VDL_16BITS;
break;
case SNDRV_PCM_FORMAT_S20_3LE:
val = DAC_VDL_20BITS;
break;
case SNDRV_PCM_FORMAT_S24_LE:
val = DAC_VDL_24BITS;
break;
case SNDRV_PCM_FORMAT_S32_LE:
val = DAC_VDL_32BITS;
break;
default:
return -EINVAL;
}
regmap_update_bits(rk3328->regmap, DAC_INIT_CTRL2, DAC_VDL_MASK, val);
val = DAC_WL_32BITS | DAC_RST_DIS;
regmap_update_bits(rk3328->regmap, DAC_INIT_CTRL3,
DAC_WL_MASK | DAC_RST_MASK, val);
return 0;
}
static int rk3328_pcm_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct rk3328_codec_priv *rk3328 =
snd_soc_component_get_drvdata(dai->component);
return rk3328_codec_open_playback(rk3328);
}
static void rk3328_pcm_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct rk3328_codec_priv *rk3328 =
snd_soc_component_get_drvdata(dai->component);
rk3328_codec_close_playback(rk3328);
}
static const struct snd_soc_dai_ops rk3328_dai_ops = {
.hw_params = rk3328_hw_params,
.set_fmt = rk3328_set_dai_fmt,
.mute_stream = rk3328_mute_stream,
.startup = rk3328_pcm_startup,
.shutdown = rk3328_pcm_shutdown,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver rk3328_dai[] = {
{
.name = "rk3328-hifi",
.id = RK3328_HIFI,
.playback = {
.stream_name = "HIFI Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = (SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S20_3LE |
SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S32_LE),
},
.capture = {
.stream_name = "HIFI Capture",
.channels_min = 2,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = (SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S20_3LE |
SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S32_LE),
},
.ops = &rk3328_dai_ops,
},
};
static int rk3328_codec_probe(struct snd_soc_component *component)
{
struct rk3328_codec_priv *rk3328 =
snd_soc_component_get_drvdata(component);
rk3328_codec_reset(rk3328);
rk3328_codec_power_on(rk3328, 0);
return 0;
}
static void rk3328_codec_remove(struct snd_soc_component *component)
{
struct rk3328_codec_priv *rk3328 =
snd_soc_component_get_drvdata(component);
rk3328_codec_close_playback(rk3328);
rk3328_codec_power_off(rk3328, 0);
}
static const struct snd_soc_component_driver soc_codec_rk3328 = {
.probe = rk3328_codec_probe,
.remove = rk3328_codec_remove,
};
static bool rk3328_codec_write_read_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case CODEC_RESET:
case DAC_INIT_CTRL1:
case DAC_INIT_CTRL2:
case DAC_INIT_CTRL3:
case DAC_PRECHARGE_CTRL:
case DAC_PWR_CTRL:
case DAC_CLK_CTRL:
case HPMIX_CTRL:
case DAC_SELECT:
case HPOUT_CTRL:
case HPOUTL_GAIN_CTRL:
case HPOUTR_GAIN_CTRL:
case HPOUT_POP_CTRL:
return true;
default:
return false;
}
}
static bool rk3328_codec_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case CODEC_RESET:
return true;
default:
return false;
}
}
static const struct regmap_config rk3328_codec_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = HPOUT_POP_CTRL,
.writeable_reg = rk3328_codec_write_read_reg,
.readable_reg = rk3328_codec_write_read_reg,
.volatile_reg = rk3328_codec_volatile_reg,
.reg_defaults = rk3328_codec_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(rk3328_codec_reg_defaults),
.cache_type = REGCACHE_FLAT,
};
static int rk3328_platform_probe(struct platform_device *pdev)
{
struct device_node *rk3328_np = pdev->dev.of_node;
struct rk3328_codec_priv *rk3328;
struct regmap *grf;
void __iomem *base;
int ret = 0;
rk3328 = devm_kzalloc(&pdev->dev, sizeof(*rk3328), GFP_KERNEL);
if (!rk3328)
return -ENOMEM;
grf = syscon_regmap_lookup_by_phandle(rk3328_np,
"rockchip,grf");
if (IS_ERR(grf)) {
dev_err(&pdev->dev, "missing 'rockchip,grf'\n");
return PTR_ERR(grf);
}
/* enable i2s_acodec_en */
regmap_write(grf, RK3328_GRF_SOC_CON2,
(BIT(14) << 16 | BIT(14)));
ret = of_property_read_u32(rk3328_np, "spk-depop-time-ms",
&rk3328->spk_depop_time);
if (ret < 0) {
dev_info(&pdev->dev, "spk_depop_time use default value.\n");
rk3328->spk_depop_time = 200;
}
rk3328->mute = gpiod_get_optional(&pdev->dev, "mute", GPIOD_OUT_HIGH);
if (IS_ERR(rk3328->mute))
return PTR_ERR(rk3328->mute);
/*
* Rock64 is the only supported platform to have widely relied on
* this; if we do happen to come across an old DTB, just leave the
* external mute forced off.
*/
if (!rk3328->mute && of_machine_is_compatible("pine64,rock64")) {
dev_warn(&pdev->dev, "assuming implicit control of GPIO_MUTE; update devicetree if possible\n");
regmap_write(grf, RK3328_GRF_SOC_CON10, BIT(17) | BIT(1));
}
rk3328->mclk = devm_clk_get(&pdev->dev, "mclk");
if (IS_ERR(rk3328->mclk))
return PTR_ERR(rk3328->mclk);
ret = clk_prepare_enable(rk3328->mclk);
if (ret)
return ret;
clk_set_rate(rk3328->mclk, INITIAL_FREQ);
rk3328->pclk = devm_clk_get(&pdev->dev, "pclk");
if (IS_ERR(rk3328->pclk)) {
dev_err(&pdev->dev, "can't get acodec pclk\n");
ret = PTR_ERR(rk3328->pclk);
goto err_unprepare_mclk;
}
ret = clk_prepare_enable(rk3328->pclk);
if (ret < 0) {
dev_err(&pdev->dev, "failed to enable acodec pclk\n");
goto err_unprepare_mclk;
}
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base)) {
ret = PTR_ERR(base);
goto err_unprepare_pclk;
}
rk3328->regmap = devm_regmap_init_mmio(&pdev->dev, base,
&rk3328_codec_regmap_config);
if (IS_ERR(rk3328->regmap)) {
ret = PTR_ERR(rk3328->regmap);
goto err_unprepare_pclk;
}
platform_set_drvdata(pdev, rk3328);
ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_rk3328,
rk3328_dai,
ARRAY_SIZE(rk3328_dai));
if (ret)
goto err_unprepare_pclk;
return 0;
err_unprepare_pclk:
clk_disable_unprepare(rk3328->pclk);
err_unprepare_mclk:
clk_disable_unprepare(rk3328->mclk);
return ret;
}
static const struct of_device_id rk3328_codec_of_match[] __maybe_unused = {
{ .compatible = "rockchip,rk3328-codec", },
{},
};
MODULE_DEVICE_TABLE(of, rk3328_codec_of_match);
static struct platform_driver rk3328_codec_driver = {
.driver = {
.name = "rk3328-codec",
.of_match_table = of_match_ptr(rk3328_codec_of_match),
},
.probe = rk3328_platform_probe,
};
module_platform_driver(rk3328_codec_driver);
MODULE_AUTHOR("Sugar Zhang <[email protected]>");
MODULE_DESCRIPTION("ASoC rk3328 codec driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/rk3328_codec.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* NAU88L24 ALSA SoC audio driver
*
* Copyright 2016 Nuvoton Technology Corp.
* Author: John Hsu <[email protected]>
*/
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/dmi.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/acpi.h>
#include <linux/math64.h>
#include <linux/semaphore.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/jack.h>
#include "nau8824.h"
#define NAU8824_JD_ACTIVE_HIGH BIT(0)
#define NAU8824_MONO_SPEAKER BIT(1)
static int nau8824_quirk;
static int quirk_override = -1;
module_param_named(quirk, quirk_override, uint, 0444);
MODULE_PARM_DESC(quirk, "Board-specific quirk override");
static int nau8824_config_sysclk(struct nau8824 *nau8824,
int clk_id, unsigned int freq);
static bool nau8824_is_jack_inserted(struct nau8824 *nau8824);
/* the ADC threshold of headset */
#define DMIC_CLK 3072000
/* the ADC threshold of headset */
#define HEADSET_SARADC_THD 0x80
/* the parameter threshold of FLL */
#define NAU_FREF_MAX 13500000
#define NAU_FVCO_MAX 100000000
#define NAU_FVCO_MIN 90000000
/* scaling for mclk from sysclk_src output */
static const struct nau8824_fll_attr mclk_src_scaling[] = {
{ 1, 0x0 },
{ 2, 0x2 },
{ 4, 0x3 },
{ 8, 0x4 },
{ 16, 0x5 },
{ 32, 0x6 },
{ 3, 0x7 },
{ 6, 0xa },
{ 12, 0xb },
{ 24, 0xc },
};
/* ratio for input clk freq */
static const struct nau8824_fll_attr fll_ratio[] = {
{ 512000, 0x01 },
{ 256000, 0x02 },
{ 128000, 0x04 },
{ 64000, 0x08 },
{ 32000, 0x10 },
{ 8000, 0x20 },
{ 4000, 0x40 },
};
static const struct nau8824_fll_attr fll_pre_scalar[] = {
{ 1, 0x0 },
{ 2, 0x1 },
{ 4, 0x2 },
{ 8, 0x3 },
};
/* the maximum frequency of CLK_ADC and CLK_DAC */
#define CLK_DA_AD_MAX 6144000
/* over sampling rate */
static const struct nau8824_osr_attr osr_dac_sel[] = {
{ 64, 2 }, /* OSR 64, SRC 1/4 */
{ 256, 0 }, /* OSR 256, SRC 1 */
{ 128, 1 }, /* OSR 128, SRC 1/2 */
{ 0, 0 },
{ 32, 3 }, /* OSR 32, SRC 1/8 */
};
static const struct nau8824_osr_attr osr_adc_sel[] = {
{ 32, 3 }, /* OSR 32, SRC 1/8 */
{ 64, 2 }, /* OSR 64, SRC 1/4 */
{ 128, 1 }, /* OSR 128, SRC 1/2 */
{ 256, 0 }, /* OSR 256, SRC 1 */
};
static const struct reg_default nau8824_reg_defaults[] = {
{ NAU8824_REG_ENA_CTRL, 0x0000 },
{ NAU8824_REG_CLK_GATING_ENA, 0x0000 },
{ NAU8824_REG_CLK_DIVIDER, 0x0000 },
{ NAU8824_REG_FLL1, 0x0000 },
{ NAU8824_REG_FLL2, 0x3126 },
{ NAU8824_REG_FLL3, 0x0008 },
{ NAU8824_REG_FLL4, 0x0010 },
{ NAU8824_REG_FLL5, 0xC000 },
{ NAU8824_REG_FLL6, 0x6000 },
{ NAU8824_REG_FLL_VCO_RSV, 0xF13C },
{ NAU8824_REG_JACK_DET_CTRL, 0x0000 },
{ NAU8824_REG_INTERRUPT_SETTING_1, 0x0000 },
{ NAU8824_REG_IRQ, 0x0000 },
{ NAU8824_REG_CLEAR_INT_REG, 0x0000 },
{ NAU8824_REG_INTERRUPT_SETTING, 0x1000 },
{ NAU8824_REG_SAR_ADC, 0x0015 },
{ NAU8824_REG_VDET_COEFFICIENT, 0x0110 },
{ NAU8824_REG_VDET_THRESHOLD_1, 0x0000 },
{ NAU8824_REG_VDET_THRESHOLD_2, 0x0000 },
{ NAU8824_REG_VDET_THRESHOLD_3, 0x0000 },
{ NAU8824_REG_VDET_THRESHOLD_4, 0x0000 },
{ NAU8824_REG_GPIO_SEL, 0x0000 },
{ NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 0x000B },
{ NAU8824_REG_PORT0_I2S_PCM_CTRL_2, 0x0010 },
{ NAU8824_REG_PORT0_LEFT_TIME_SLOT, 0x0000 },
{ NAU8824_REG_PORT0_RIGHT_TIME_SLOT, 0x0000 },
{ NAU8824_REG_TDM_CTRL, 0x0000 },
{ NAU8824_REG_ADC_HPF_FILTER, 0x0000 },
{ NAU8824_REG_ADC_FILTER_CTRL, 0x0002 },
{ NAU8824_REG_DAC_FILTER_CTRL_1, 0x0000 },
{ NAU8824_REG_DAC_FILTER_CTRL_2, 0x0000 },
{ NAU8824_REG_NOTCH_FILTER_1, 0x0000 },
{ NAU8824_REG_NOTCH_FILTER_2, 0x0000 },
{ NAU8824_REG_EQ1_LOW, 0x112C },
{ NAU8824_REG_EQ2_EQ3, 0x2C2C },
{ NAU8824_REG_EQ4_EQ5, 0x2C2C },
{ NAU8824_REG_ADC_CH0_DGAIN_CTRL, 0x0100 },
{ NAU8824_REG_ADC_CH1_DGAIN_CTRL, 0x0100 },
{ NAU8824_REG_ADC_CH2_DGAIN_CTRL, 0x0100 },
{ NAU8824_REG_ADC_CH3_DGAIN_CTRL, 0x0100 },
{ NAU8824_REG_DAC_MUTE_CTRL, 0x0000 },
{ NAU8824_REG_DAC_CH0_DGAIN_CTRL, 0x0100 },
{ NAU8824_REG_DAC_CH1_DGAIN_CTRL, 0x0100 },
{ NAU8824_REG_ADC_TO_DAC_ST, 0x0000 },
{ NAU8824_REG_DRC_KNEE_IP12_ADC_CH01, 0x1486 },
{ NAU8824_REG_DRC_KNEE_IP34_ADC_CH01, 0x0F12 },
{ NAU8824_REG_DRC_SLOPE_ADC_CH01, 0x25FF },
{ NAU8824_REG_DRC_ATKDCY_ADC_CH01, 0x3457 },
{ NAU8824_REG_DRC_KNEE_IP12_ADC_CH23, 0x1486 },
{ NAU8824_REG_DRC_KNEE_IP34_ADC_CH23, 0x0F12 },
{ NAU8824_REG_DRC_SLOPE_ADC_CH23, 0x25FF },
{ NAU8824_REG_DRC_ATKDCY_ADC_CH23, 0x3457 },
{ NAU8824_REG_DRC_GAINL_ADC0, 0x0200 },
{ NAU8824_REG_DRC_GAINL_ADC1, 0x0200 },
{ NAU8824_REG_DRC_GAINL_ADC2, 0x0200 },
{ NAU8824_REG_DRC_GAINL_ADC3, 0x0200 },
{ NAU8824_REG_DRC_KNEE_IP12_DAC, 0x1486 },
{ NAU8824_REG_DRC_KNEE_IP34_DAC, 0x0F12 },
{ NAU8824_REG_DRC_SLOPE_DAC, 0x25F9 },
{ NAU8824_REG_DRC_ATKDCY_DAC, 0x3457 },
{ NAU8824_REG_DRC_GAIN_DAC_CH0, 0x0200 },
{ NAU8824_REG_DRC_GAIN_DAC_CH1, 0x0200 },
{ NAU8824_REG_MODE, 0x0000 },
{ NAU8824_REG_MODE1, 0x0000 },
{ NAU8824_REG_MODE2, 0x0000 },
{ NAU8824_REG_CLASSG, 0x0000 },
{ NAU8824_REG_OTP_EFUSE, 0x0000 },
{ NAU8824_REG_OTPDOUT_1, 0x0000 },
{ NAU8824_REG_OTPDOUT_2, 0x0000 },
{ NAU8824_REG_MISC_CTRL, 0x0000 },
{ NAU8824_REG_I2C_TIMEOUT, 0xEFFF },
{ NAU8824_REG_TEST_MODE, 0x0000 },
{ NAU8824_REG_I2C_DEVICE_ID, 0x1AF1 },
{ NAU8824_REG_SAR_ADC_DATA_OUT, 0x00FF },
{ NAU8824_REG_BIAS_ADJ, 0x0000 },
{ NAU8824_REG_PGA_GAIN, 0x0000 },
{ NAU8824_REG_TRIM_SETTINGS, 0x0000 },
{ NAU8824_REG_ANALOG_CONTROL_1, 0x0000 },
{ NAU8824_REG_ANALOG_CONTROL_2, 0x0000 },
{ NAU8824_REG_ENABLE_LO, 0x0000 },
{ NAU8824_REG_GAIN_LO, 0x0000 },
{ NAU8824_REG_CLASSD_GAIN_1, 0x0000 },
{ NAU8824_REG_CLASSD_GAIN_2, 0x0000 },
{ NAU8824_REG_ANALOG_ADC_1, 0x0011 },
{ NAU8824_REG_ANALOG_ADC_2, 0x0020 },
{ NAU8824_REG_RDAC, 0x0008 },
{ NAU8824_REG_MIC_BIAS, 0x0006 },
{ NAU8824_REG_HS_VOLUME_CONTROL, 0x0000 },
{ NAU8824_REG_BOOST, 0x0000 },
{ NAU8824_REG_FEPGA, 0x0000 },
{ NAU8824_REG_FEPGA_II, 0x0000 },
{ NAU8824_REG_FEPGA_SE, 0x0000 },
{ NAU8824_REG_FEPGA_ATTENUATION, 0x0000 },
{ NAU8824_REG_ATT_PORT0, 0x0000 },
{ NAU8824_REG_ATT_PORT1, 0x0000 },
{ NAU8824_REG_POWER_UP_CONTROL, 0x0000 },
{ NAU8824_REG_CHARGE_PUMP_CONTROL, 0x0300 },
{ NAU8824_REG_CHARGE_PUMP_INPUT, 0x0013 },
};
static int nau8824_sema_acquire(struct nau8824 *nau8824, long timeout)
{
int ret;
if (timeout) {
ret = down_timeout(&nau8824->jd_sem, timeout);
if (ret < 0)
dev_warn(nau8824->dev, "Acquire semaphore timeout\n");
} else {
ret = down_interruptible(&nau8824->jd_sem);
if (ret < 0)
dev_warn(nau8824->dev, "Acquire semaphore fail\n");
}
return ret;
}
static inline void nau8824_sema_release(struct nau8824 *nau8824)
{
up(&nau8824->jd_sem);
}
static bool nau8824_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case NAU8824_REG_ENA_CTRL ... NAU8824_REG_FLL_VCO_RSV:
case NAU8824_REG_JACK_DET_CTRL:
case NAU8824_REG_INTERRUPT_SETTING_1:
case NAU8824_REG_IRQ:
case NAU8824_REG_CLEAR_INT_REG ... NAU8824_REG_VDET_THRESHOLD_4:
case NAU8824_REG_GPIO_SEL:
case NAU8824_REG_PORT0_I2S_PCM_CTRL_1 ... NAU8824_REG_TDM_CTRL:
case NAU8824_REG_ADC_HPF_FILTER ... NAU8824_REG_EQ4_EQ5:
case NAU8824_REG_ADC_CH0_DGAIN_CTRL ... NAU8824_REG_ADC_TO_DAC_ST:
case NAU8824_REG_DRC_KNEE_IP12_ADC_CH01 ... NAU8824_REG_DRC_GAINL_ADC3:
case NAU8824_REG_DRC_KNEE_IP12_DAC ... NAU8824_REG_DRC_GAIN_DAC_CH1:
case NAU8824_REG_CLASSG ... NAU8824_REG_OTP_EFUSE:
case NAU8824_REG_OTPDOUT_1 ... NAU8824_REG_OTPDOUT_2:
case NAU8824_REG_I2C_TIMEOUT:
case NAU8824_REG_I2C_DEVICE_ID ... NAU8824_REG_SAR_ADC_DATA_OUT:
case NAU8824_REG_BIAS_ADJ ... NAU8824_REG_CLASSD_GAIN_2:
case NAU8824_REG_ANALOG_ADC_1 ... NAU8824_REG_ATT_PORT1:
case NAU8824_REG_POWER_UP_CONTROL ... NAU8824_REG_CHARGE_PUMP_INPUT:
return true;
default:
return false;
}
}
static bool nau8824_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case NAU8824_REG_RESET ... NAU8824_REG_FLL_VCO_RSV:
case NAU8824_REG_JACK_DET_CTRL:
case NAU8824_REG_INTERRUPT_SETTING_1:
case NAU8824_REG_CLEAR_INT_REG ... NAU8824_REG_VDET_THRESHOLD_4:
case NAU8824_REG_GPIO_SEL:
case NAU8824_REG_PORT0_I2S_PCM_CTRL_1 ... NAU8824_REG_TDM_CTRL:
case NAU8824_REG_ADC_HPF_FILTER ... NAU8824_REG_EQ4_EQ5:
case NAU8824_REG_ADC_CH0_DGAIN_CTRL ... NAU8824_REG_ADC_TO_DAC_ST:
case NAU8824_REG_DRC_KNEE_IP12_ADC_CH01:
case NAU8824_REG_DRC_KNEE_IP34_ADC_CH01:
case NAU8824_REG_DRC_SLOPE_ADC_CH01:
case NAU8824_REG_DRC_ATKDCY_ADC_CH01:
case NAU8824_REG_DRC_KNEE_IP12_ADC_CH23:
case NAU8824_REG_DRC_KNEE_IP34_ADC_CH23:
case NAU8824_REG_DRC_SLOPE_ADC_CH23:
case NAU8824_REG_DRC_ATKDCY_ADC_CH23:
case NAU8824_REG_DRC_KNEE_IP12_DAC ... NAU8824_REG_DRC_ATKDCY_DAC:
case NAU8824_REG_CLASSG ... NAU8824_REG_OTP_EFUSE:
case NAU8824_REG_I2C_TIMEOUT:
case NAU8824_REG_BIAS_ADJ ... NAU8824_REG_CLASSD_GAIN_2:
case NAU8824_REG_ANALOG_ADC_1 ... NAU8824_REG_ATT_PORT1:
case NAU8824_REG_POWER_UP_CONTROL ... NAU8824_REG_CHARGE_PUMP_CONTROL:
return true;
default:
return false;
}
}
static bool nau8824_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case NAU8824_REG_RESET:
case NAU8824_REG_IRQ ... NAU8824_REG_CLEAR_INT_REG:
case NAU8824_REG_DRC_GAINL_ADC0 ... NAU8824_REG_DRC_GAINL_ADC3:
case NAU8824_REG_DRC_GAIN_DAC_CH0 ... NAU8824_REG_DRC_GAIN_DAC_CH1:
case NAU8824_REG_OTPDOUT_1 ... NAU8824_REG_OTPDOUT_2:
case NAU8824_REG_I2C_DEVICE_ID ... NAU8824_REG_SAR_ADC_DATA_OUT:
case NAU8824_REG_CHARGE_PUMP_INPUT:
return true;
default:
return false;
}
}
static const char * const nau8824_companding[] = {
"Off", "NC", "u-law", "A-law" };
static const struct soc_enum nau8824_companding_adc_enum =
SOC_ENUM_SINGLE(NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 12,
ARRAY_SIZE(nau8824_companding), nau8824_companding);
static const struct soc_enum nau8824_companding_dac_enum =
SOC_ENUM_SINGLE(NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 14,
ARRAY_SIZE(nau8824_companding), nau8824_companding);
static const char * const nau8824_adc_decimation[] = {
"32", "64", "128", "256" };
static const struct soc_enum nau8824_adc_decimation_enum =
SOC_ENUM_SINGLE(NAU8824_REG_ADC_FILTER_CTRL, 0,
ARRAY_SIZE(nau8824_adc_decimation), nau8824_adc_decimation);
static const char * const nau8824_dac_oversampl[] = {
"64", "256", "128", "", "32" };
static const struct soc_enum nau8824_dac_oversampl_enum =
SOC_ENUM_SINGLE(NAU8824_REG_DAC_FILTER_CTRL_1, 0,
ARRAY_SIZE(nau8824_dac_oversampl), nau8824_dac_oversampl);
static const char * const nau8824_input_channel[] = {
"Input CH0", "Input CH1", "Input CH2", "Input CH3" };
static const struct soc_enum nau8824_adc_ch0_enum =
SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH0_DGAIN_CTRL, 9,
ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);
static const struct soc_enum nau8824_adc_ch1_enum =
SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH1_DGAIN_CTRL, 9,
ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);
static const struct soc_enum nau8824_adc_ch2_enum =
SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH2_DGAIN_CTRL, 9,
ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);
static const struct soc_enum nau8824_adc_ch3_enum =
SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH3_DGAIN_CTRL, 9,
ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);
static const char * const nau8824_tdm_slot[] = {
"Slot 0", "Slot 1", "Slot 2", "Slot 3" };
static const struct soc_enum nau8824_dac_left_sel_enum =
SOC_ENUM_SINGLE(NAU8824_REG_TDM_CTRL, 6,
ARRAY_SIZE(nau8824_tdm_slot), nau8824_tdm_slot);
static const struct soc_enum nau8824_dac_right_sel_enum =
SOC_ENUM_SINGLE(NAU8824_REG_TDM_CTRL, 4,
ARRAY_SIZE(nau8824_tdm_slot), nau8824_tdm_slot);
static const DECLARE_TLV_DB_MINMAX_MUTE(spk_vol_tlv, 0, 2400);
static const DECLARE_TLV_DB_MINMAX(hp_vol_tlv, -3000, 0);
static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 200, 0);
static const DECLARE_TLV_DB_SCALE(dmic_vol_tlv, -12800, 50, 0);
static const struct snd_kcontrol_new nau8824_snd_controls[] = {
SOC_ENUM("ADC Companding", nau8824_companding_adc_enum),
SOC_ENUM("DAC Companding", nau8824_companding_dac_enum),
SOC_ENUM("ADC Decimation Rate", nau8824_adc_decimation_enum),
SOC_ENUM("DAC Oversampling Rate", nau8824_dac_oversampl_enum),
SOC_SINGLE_TLV("Speaker Right DACR Volume",
NAU8824_REG_CLASSD_GAIN_1, 8, 0x1f, 0, spk_vol_tlv),
SOC_SINGLE_TLV("Speaker Left DACL Volume",
NAU8824_REG_CLASSD_GAIN_2, 0, 0x1f, 0, spk_vol_tlv),
SOC_SINGLE_TLV("Speaker Left DACR Volume",
NAU8824_REG_CLASSD_GAIN_1, 0, 0x1f, 0, spk_vol_tlv),
SOC_SINGLE_TLV("Speaker Right DACL Volume",
NAU8824_REG_CLASSD_GAIN_2, 8, 0x1f, 0, spk_vol_tlv),
SOC_SINGLE_TLV("Headphone Right DACR Volume",
NAU8824_REG_ATT_PORT0, 8, 0x1f, 0, hp_vol_tlv),
SOC_SINGLE_TLV("Headphone Left DACL Volume",
NAU8824_REG_ATT_PORT0, 0, 0x1f, 0, hp_vol_tlv),
SOC_SINGLE_TLV("Headphone Right DACL Volume",
NAU8824_REG_ATT_PORT1, 8, 0x1f, 0, hp_vol_tlv),
SOC_SINGLE_TLV("Headphone Left DACR Volume",
NAU8824_REG_ATT_PORT1, 0, 0x1f, 0, hp_vol_tlv),
SOC_SINGLE_TLV("MIC1 Volume", NAU8824_REG_FEPGA_II,
NAU8824_FEPGA_GAINL_SFT, 0x12, 0, mic_vol_tlv),
SOC_SINGLE_TLV("MIC2 Volume", NAU8824_REG_FEPGA_II,
NAU8824_FEPGA_GAINR_SFT, 0x12, 0, mic_vol_tlv),
SOC_SINGLE_TLV("DMIC1 Volume", NAU8824_REG_ADC_CH0_DGAIN_CTRL,
0, 0x164, 0, dmic_vol_tlv),
SOC_SINGLE_TLV("DMIC2 Volume", NAU8824_REG_ADC_CH1_DGAIN_CTRL,
0, 0x164, 0, dmic_vol_tlv),
SOC_SINGLE_TLV("DMIC3 Volume", NAU8824_REG_ADC_CH2_DGAIN_CTRL,
0, 0x164, 0, dmic_vol_tlv),
SOC_SINGLE_TLV("DMIC4 Volume", NAU8824_REG_ADC_CH3_DGAIN_CTRL,
0, 0x164, 0, dmic_vol_tlv),
SOC_ENUM("ADC CH0 Select", nau8824_adc_ch0_enum),
SOC_ENUM("ADC CH1 Select", nau8824_adc_ch1_enum),
SOC_ENUM("ADC CH2 Select", nau8824_adc_ch2_enum),
SOC_ENUM("ADC CH3 Select", nau8824_adc_ch3_enum),
SOC_SINGLE("ADC CH0 TX Switch", NAU8824_REG_TDM_CTRL, 0, 1, 0),
SOC_SINGLE("ADC CH1 TX Switch", NAU8824_REG_TDM_CTRL, 1, 1, 0),
SOC_SINGLE("ADC CH2 TX Switch", NAU8824_REG_TDM_CTRL, 2, 1, 0),
SOC_SINGLE("ADC CH3 TX Switch", NAU8824_REG_TDM_CTRL, 3, 1, 0),
SOC_ENUM("DACL Channel Source", nau8824_dac_left_sel_enum),
SOC_ENUM("DACR Channel Source", nau8824_dac_right_sel_enum),
SOC_SINGLE("DACL LR Mix", NAU8824_REG_DAC_MUTE_CTRL, 0, 1, 0),
SOC_SINGLE("DACR LR Mix", NAU8824_REG_DAC_MUTE_CTRL, 1, 1, 0),
SOC_SINGLE("THD for key media",
NAU8824_REG_VDET_THRESHOLD_1, 8, 0xff, 0),
SOC_SINGLE("THD for key voice command",
NAU8824_REG_VDET_THRESHOLD_1, 0, 0xff, 0),
SOC_SINGLE("THD for key volume up",
NAU8824_REG_VDET_THRESHOLD_2, 8, 0xff, 0),
SOC_SINGLE("THD for key volume down",
NAU8824_REG_VDET_THRESHOLD_2, 0, 0xff, 0),
};
static int nau8824_output_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* Disables the TESTDAC to let DAC signal pass through. */
regmap_update_bits(nau8824->regmap, NAU8824_REG_ENABLE_LO,
NAU8824_TEST_DAC_EN, 0);
break;
case SND_SOC_DAPM_POST_PMD:
regmap_update_bits(nau8824->regmap, NAU8824_REG_ENABLE_LO,
NAU8824_TEST_DAC_EN, NAU8824_TEST_DAC_EN);
break;
default:
return -EINVAL;
}
return 0;
}
static int nau8824_spk_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
regmap_update_bits(nau8824->regmap,
NAU8824_REG_ANALOG_CONTROL_2,
NAU8824_CLASSD_CLAMP_DIS, NAU8824_CLASSD_CLAMP_DIS);
break;
case SND_SOC_DAPM_POST_PMD:
regmap_update_bits(nau8824->regmap,
NAU8824_REG_ANALOG_CONTROL_2,
NAU8824_CLASSD_CLAMP_DIS, 0);
break;
default:
return -EINVAL;
}
return 0;
}
static int nau8824_pump_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
/* Prevent startup click by letting charge pump to ramp up */
msleep(10);
regmap_update_bits(nau8824->regmap,
NAU8824_REG_CHARGE_PUMP_CONTROL,
NAU8824_JAMNODCLOW, NAU8824_JAMNODCLOW);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_update_bits(nau8824->regmap,
NAU8824_REG_CHARGE_PUMP_CONTROL,
NAU8824_JAMNODCLOW, 0);
break;
default:
return -EINVAL;
}
return 0;
}
static int system_clock_control(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *k, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
struct regmap *regmap = nau8824->regmap;
unsigned int value;
bool clk_fll, error;
if (SND_SOC_DAPM_EVENT_OFF(event)) {
dev_dbg(nau8824->dev, "system clock control : POWER OFF\n");
/* Set clock source to disable or internal clock before the
* playback or capture end. Codec needs clock for Jack
* detection and button press if jack inserted; otherwise,
* the clock should be closed.
*/
if (nau8824_is_jack_inserted(nau8824)) {
nau8824_config_sysclk(nau8824,
NAU8824_CLK_INTERNAL, 0);
} else {
nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0);
}
} else {
dev_dbg(nau8824->dev, "system clock control : POWER ON\n");
/* Check the clock source setting is proper or not
* no matter the source is from FLL or MCLK.
*/
regmap_read(regmap, NAU8824_REG_FLL1, &value);
clk_fll = value & NAU8824_FLL_RATIO_MASK;
/* It's error to use internal clock when playback */
regmap_read(regmap, NAU8824_REG_FLL6, &value);
error = value & NAU8824_DCO_EN;
if (!error) {
/* Check error depending on source is FLL or MCLK. */
regmap_read(regmap, NAU8824_REG_CLK_DIVIDER, &value);
if (clk_fll)
error = !(value & NAU8824_CLK_SRC_VCO);
else
error = value & NAU8824_CLK_SRC_VCO;
}
/* Recover the clock source setting if error. */
if (error) {
if (clk_fll) {
regmap_update_bits(regmap,
NAU8824_REG_FLL6, NAU8824_DCO_EN, 0);
regmap_update_bits(regmap,
NAU8824_REG_CLK_DIVIDER,
NAU8824_CLK_SRC_MASK,
NAU8824_CLK_SRC_VCO);
} else {
nau8824_config_sysclk(nau8824,
NAU8824_CLK_MCLK, 0);
}
}
}
return 0;
}
static int dmic_clock_control(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *k, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
int src;
/* The DMIC clock is gotten from system clock (256fs) divided by
* DMIC_SRC (1, 2, 4, 8, 16, 32). The clock has to be equal or
* less than 3.072 MHz.
*/
for (src = 0; src < 5; src++) {
if ((0x1 << (8 - src)) * nau8824->fs <= DMIC_CLK)
break;
}
dev_dbg(nau8824->dev, "dmic src %d for mclk %d\n", src, nau8824->fs * 256);
regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER,
NAU8824_CLK_DMIC_SRC_MASK, (src << NAU8824_CLK_DMIC_SRC_SFT));
return 0;
}
static const struct snd_kcontrol_new nau8824_adc_ch0_dmic =
SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,
NAU8824_ADC_CH0_DMIC_SFT, 1, 0);
static const struct snd_kcontrol_new nau8824_adc_ch1_dmic =
SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,
NAU8824_ADC_CH1_DMIC_SFT, 1, 0);
static const struct snd_kcontrol_new nau8824_adc_ch2_dmic =
SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,
NAU8824_ADC_CH2_DMIC_SFT, 1, 0);
static const struct snd_kcontrol_new nau8824_adc_ch3_dmic =
SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,
NAU8824_ADC_CH3_DMIC_SFT, 1, 0);
static const struct snd_kcontrol_new nau8824_adc_left_mixer[] = {
SOC_DAPM_SINGLE("MIC Switch", NAU8824_REG_FEPGA,
NAU8824_FEPGA_MODEL_MIC1_SFT, 1, 0),
SOC_DAPM_SINGLE("HSMIC Switch", NAU8824_REG_FEPGA,
NAU8824_FEPGA_MODEL_HSMIC_SFT, 1, 0),
};
static const struct snd_kcontrol_new nau8824_adc_right_mixer[] = {
SOC_DAPM_SINGLE("MIC Switch", NAU8824_REG_FEPGA,
NAU8824_FEPGA_MODER_MIC2_SFT, 1, 0),
SOC_DAPM_SINGLE("HSMIC Switch", NAU8824_REG_FEPGA,
NAU8824_FEPGA_MODER_HSMIC_SFT, 1, 0),
};
static const struct snd_kcontrol_new nau8824_hp_left_mixer[] = {
SOC_DAPM_SINGLE("DAC Right Switch", NAU8824_REG_ENABLE_LO,
NAU8824_DACR_HPL_EN_SFT, 1, 0),
SOC_DAPM_SINGLE("DAC Left Switch", NAU8824_REG_ENABLE_LO,
NAU8824_DACL_HPL_EN_SFT, 1, 0),
};
static const struct snd_kcontrol_new nau8824_hp_right_mixer[] = {
SOC_DAPM_SINGLE("DAC Left Switch", NAU8824_REG_ENABLE_LO,
NAU8824_DACL_HPR_EN_SFT, 1, 0),
SOC_DAPM_SINGLE("DAC Right Switch", NAU8824_REG_ENABLE_LO,
NAU8824_DACR_HPR_EN_SFT, 1, 0),
};
static const char * const nau8824_dac_src[] = { "DACL", "DACR" };
static SOC_ENUM_SINGLE_DECL(
nau8824_dacl_enum, NAU8824_REG_DAC_CH0_DGAIN_CTRL,
NAU8824_DAC_CH0_SEL_SFT, nau8824_dac_src);
static SOC_ENUM_SINGLE_DECL(
nau8824_dacr_enum, NAU8824_REG_DAC_CH1_DGAIN_CTRL,
NAU8824_DAC_CH1_SEL_SFT, nau8824_dac_src);
static const struct snd_kcontrol_new nau8824_dacl_mux =
SOC_DAPM_ENUM("DACL Source", nau8824_dacl_enum);
static const struct snd_kcontrol_new nau8824_dacr_mux =
SOC_DAPM_ENUM("DACR Source", nau8824_dacr_enum);
static const struct snd_soc_dapm_widget nau8824_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("System Clock", SND_SOC_NOPM, 0, 0,
system_clock_control, SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_INPUT("HSMIC1"),
SND_SOC_DAPM_INPUT("HSMIC2"),
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_INPUT("MIC2"),
SND_SOC_DAPM_INPUT("DMIC1"),
SND_SOC_DAPM_INPUT("DMIC2"),
SND_SOC_DAPM_INPUT("DMIC3"),
SND_SOC_DAPM_INPUT("DMIC4"),
SND_SOC_DAPM_SUPPLY("SAR", NAU8824_REG_SAR_ADC,
NAU8824_SAR_ADC_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS", NAU8824_REG_MIC_BIAS,
NAU8824_MICBIAS_POWERUP_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DMIC12 Power", NAU8824_REG_BIAS_ADJ,
NAU8824_DMIC1_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DMIC34 Power", NAU8824_REG_BIAS_ADJ,
NAU8824_DMIC2_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DMIC Clock", SND_SOC_NOPM, 0, 0,
dmic_clock_control, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SWITCH("DMIC1 Enable", SND_SOC_NOPM,
0, 0, &nau8824_adc_ch0_dmic),
SND_SOC_DAPM_SWITCH("DMIC2 Enable", SND_SOC_NOPM,
0, 0, &nau8824_adc_ch1_dmic),
SND_SOC_DAPM_SWITCH("DMIC3 Enable", SND_SOC_NOPM,
0, 0, &nau8824_adc_ch2_dmic),
SND_SOC_DAPM_SWITCH("DMIC4 Enable", SND_SOC_NOPM,
0, 0, &nau8824_adc_ch3_dmic),
SND_SOC_DAPM_MIXER("Left ADC", NAU8824_REG_POWER_UP_CONTROL,
12, 0, nau8824_adc_left_mixer,
ARRAY_SIZE(nau8824_adc_left_mixer)),
SND_SOC_DAPM_MIXER("Right ADC", NAU8824_REG_POWER_UP_CONTROL,
13, 0, nau8824_adc_right_mixer,
ARRAY_SIZE(nau8824_adc_right_mixer)),
SND_SOC_DAPM_ADC("ADCL", NULL, NAU8824_REG_ANALOG_ADC_2,
NAU8824_ADCL_EN_SFT, 0),
SND_SOC_DAPM_ADC("ADCR", NULL, NAU8824_REG_ANALOG_ADC_2,
NAU8824_ADCR_EN_SFT, 0),
SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIFRX", "Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DACL", NULL, NAU8824_REG_RDAC,
NAU8824_DACL_EN_SFT, 0),
SND_SOC_DAPM_SUPPLY("DACL Clock", NAU8824_REG_RDAC,
NAU8824_DACL_CLK_SFT, 0, NULL, 0),
SND_SOC_DAPM_DAC("DACR", NULL, NAU8824_REG_RDAC,
NAU8824_DACR_EN_SFT, 0),
SND_SOC_DAPM_SUPPLY("DACR Clock", NAU8824_REG_RDAC,
NAU8824_DACR_CLK_SFT, 0, NULL, 0),
SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &nau8824_dacl_mux),
SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &nau8824_dacr_mux),
SND_SOC_DAPM_PGA_S("Output DACL", 0, NAU8824_REG_CHARGE_PUMP_CONTROL,
8, 1, nau8824_output_dac_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_S("Output DACR", 0, NAU8824_REG_CHARGE_PUMP_CONTROL,
9, 1, nau8824_output_dac_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_S("ClassD", 0, NAU8824_REG_CLASSD_GAIN_1,
NAU8824_CLASSD_EN_SFT, 0, nau8824_spk_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER("Left Headphone", NAU8824_REG_CLASSG,
NAU8824_CLASSG_LDAC_EN_SFT, 0, nau8824_hp_left_mixer,
ARRAY_SIZE(nau8824_hp_left_mixer)),
SND_SOC_DAPM_MIXER("Right Headphone", NAU8824_REG_CLASSG,
NAU8824_CLASSG_RDAC_EN_SFT, 0, nau8824_hp_right_mixer,
ARRAY_SIZE(nau8824_hp_right_mixer)),
SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8824_REG_CHARGE_PUMP_CONTROL,
NAU8824_CHARGE_PUMP_EN_SFT, 0, nau8824_pump_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA("Output Driver L",
NAU8824_REG_POWER_UP_CONTROL, 3, 0, NULL, 0),
SND_SOC_DAPM_PGA("Output Driver R",
NAU8824_REG_POWER_UP_CONTROL, 2, 0, NULL, 0),
SND_SOC_DAPM_PGA("Main Driver L",
NAU8824_REG_POWER_UP_CONTROL, 1, 0, NULL, 0),
SND_SOC_DAPM_PGA("Main Driver R",
NAU8824_REG_POWER_UP_CONTROL, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("HP Boost Driver", NAU8824_REG_BOOST,
NAU8824_HP_BOOST_DIS_SFT, 1, NULL, 0),
SND_SOC_DAPM_PGA("Class G", NAU8824_REG_CLASSG,
NAU8824_CLASSG_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("SPKOUTL"),
SND_SOC_DAPM_OUTPUT("SPKOUTR"),
SND_SOC_DAPM_OUTPUT("HPOL"),
SND_SOC_DAPM_OUTPUT("HPOR"),
};
static const struct snd_soc_dapm_route nau8824_dapm_routes[] = {
{"DMIC1 Enable", "Switch", "DMIC1"},
{"DMIC2 Enable", "Switch", "DMIC2"},
{"DMIC3 Enable", "Switch", "DMIC3"},
{"DMIC4 Enable", "Switch", "DMIC4"},
{"DMIC1", NULL, "DMIC12 Power"},
{"DMIC2", NULL, "DMIC12 Power"},
{"DMIC3", NULL, "DMIC34 Power"},
{"DMIC4", NULL, "DMIC34 Power"},
{"DMIC12 Power", NULL, "DMIC Clock"},
{"DMIC34 Power", NULL, "DMIC Clock"},
{"Left ADC", "MIC Switch", "MIC1"},
{"Left ADC", "HSMIC Switch", "HSMIC1"},
{"Right ADC", "MIC Switch", "MIC2"},
{"Right ADC", "HSMIC Switch", "HSMIC2"},
{"ADCL", NULL, "Left ADC"},
{"ADCR", NULL, "Right ADC"},
{"AIFTX", NULL, "MICBIAS"},
{"AIFTX", NULL, "ADCL"},
{"AIFTX", NULL, "ADCR"},
{"AIFTX", NULL, "DMIC1 Enable"},
{"AIFTX", NULL, "DMIC2 Enable"},
{"AIFTX", NULL, "DMIC3 Enable"},
{"AIFTX", NULL, "DMIC4 Enable"},
{"AIFTX", NULL, "System Clock"},
{"AIFRX", NULL, "System Clock"},
{"DACL", NULL, "AIFRX"},
{"DACL", NULL, "DACL Clock"},
{"DACR", NULL, "AIFRX"},
{"DACR", NULL, "DACR Clock"},
{"DACL Mux", "DACL", "DACL"},
{"DACL Mux", "DACR", "DACR"},
{"DACR Mux", "DACL", "DACL"},
{"DACR Mux", "DACR", "DACR"},
{"Output DACL", NULL, "DACL Mux"},
{"Output DACR", NULL, "DACR Mux"},
{"ClassD", NULL, "Output DACL"},
{"ClassD", NULL, "Output DACR"},
{"Left Headphone", "DAC Left Switch", "Output DACL"},
{"Left Headphone", "DAC Right Switch", "Output DACR"},
{"Right Headphone", "DAC Left Switch", "Output DACL"},
{"Right Headphone", "DAC Right Switch", "Output DACR"},
{"Charge Pump", NULL, "Left Headphone"},
{"Charge Pump", NULL, "Right Headphone"},
{"Output Driver L", NULL, "Charge Pump"},
{"Output Driver R", NULL, "Charge Pump"},
{"Main Driver L", NULL, "Output Driver L"},
{"Main Driver R", NULL, "Output Driver R"},
{"Class G", NULL, "Main Driver L"},
{"Class G", NULL, "Main Driver R"},
{"HP Boost Driver", NULL, "Class G"},
{"SPKOUTL", NULL, "ClassD"},
{"SPKOUTR", NULL, "ClassD"},
{"HPOL", NULL, "HP Boost Driver"},
{"HPOR", NULL, "HP Boost Driver"},
};
static bool nau8824_is_jack_inserted(struct nau8824 *nau8824)
{
struct snd_soc_jack *jack = nau8824->jack;
bool insert = false;
if (nau8824->irq && jack)
insert = jack->status & SND_JACK_HEADPHONE;
return insert;
}
static void nau8824_int_status_clear_all(struct regmap *regmap)
{
int active_irq, clear_irq, i;
/* Reset the intrruption status from rightmost bit if the corres-
* ponding irq event occurs.
*/
regmap_read(regmap, NAU8824_REG_IRQ, &active_irq);
for (i = 0; i < NAU8824_REG_DATA_LEN; i++) {
clear_irq = (0x1 << i);
if (active_irq & clear_irq)
regmap_write(regmap,
NAU8824_REG_CLEAR_INT_REG, clear_irq);
}
}
static void nau8824_eject_jack(struct nau8824 *nau8824)
{
struct snd_soc_dapm_context *dapm = nau8824->dapm;
struct regmap *regmap = nau8824->regmap;
/* Clear all interruption status */
nau8824_int_status_clear_all(regmap);
snd_soc_dapm_disable_pin(dapm, "SAR");
snd_soc_dapm_disable_pin(dapm, "MICBIAS");
snd_soc_dapm_sync(dapm);
/* Enable the insertion interruption, disable the ejection
* interruption, and then bypass de-bounce circuit.
*/
regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING,
NAU8824_IRQ_KEY_RELEASE_DIS | NAU8824_IRQ_KEY_SHORT_PRESS_DIS |
NAU8824_IRQ_EJECT_DIS | NAU8824_IRQ_INSERT_DIS,
NAU8824_IRQ_KEY_RELEASE_DIS | NAU8824_IRQ_KEY_SHORT_PRESS_DIS |
NAU8824_IRQ_EJECT_DIS);
regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING_1,
NAU8824_IRQ_INSERT_EN | NAU8824_IRQ_EJECT_EN,
NAU8824_IRQ_INSERT_EN);
regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL,
NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE);
/* Close clock for jack type detection at manual mode */
if (dapm->bias_level < SND_SOC_BIAS_PREPARE)
nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0);
}
static void nau8824_jdet_work(struct work_struct *work)
{
struct nau8824 *nau8824 = container_of(
work, struct nau8824, jdet_work);
struct snd_soc_dapm_context *dapm = nau8824->dapm;
struct regmap *regmap = nau8824->regmap;
int adc_value, event = 0, event_mask = 0;
snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
snd_soc_dapm_force_enable_pin(dapm, "SAR");
snd_soc_dapm_sync(dapm);
msleep(100);
regmap_read(regmap, NAU8824_REG_SAR_ADC_DATA_OUT, &adc_value);
adc_value = adc_value & NAU8824_SAR_ADC_DATA_MASK;
dev_dbg(nau8824->dev, "SAR ADC data 0x%02x\n", adc_value);
if (adc_value < HEADSET_SARADC_THD) {
event |= SND_JACK_HEADPHONE;
snd_soc_dapm_disable_pin(dapm, "SAR");
snd_soc_dapm_disable_pin(dapm, "MICBIAS");
snd_soc_dapm_sync(dapm);
} else {
event |= SND_JACK_HEADSET;
}
event_mask |= SND_JACK_HEADSET;
snd_soc_jack_report(nau8824->jack, event, event_mask);
/* Enable short key press and release interruption. */
regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING,
NAU8824_IRQ_KEY_RELEASE_DIS |
NAU8824_IRQ_KEY_SHORT_PRESS_DIS, 0);
if (nau8824->resume_lock) {
nau8824_sema_release(nau8824);
nau8824->resume_lock = false;
}
}
static void nau8824_setup_auto_irq(struct nau8824 *nau8824)
{
struct regmap *regmap = nau8824->regmap;
/* Enable jack ejection interruption. */
regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING_1,
NAU8824_IRQ_INSERT_EN | NAU8824_IRQ_EJECT_EN,
NAU8824_IRQ_EJECT_EN);
regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING,
NAU8824_IRQ_EJECT_DIS, 0);
/* Enable internal VCO needed for interruptions */
if (nau8824->dapm->bias_level < SND_SOC_BIAS_PREPARE)
nau8824_config_sysclk(nau8824, NAU8824_CLK_INTERNAL, 0);
regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL,
NAU8824_JD_SLEEP_MODE, 0);
}
static int nau8824_button_decode(int value)
{
int buttons = 0;
/* The chip supports up to 8 buttons, but ALSA defines
* only 6 buttons.
*/
if (value & BIT(0))
buttons |= SND_JACK_BTN_0;
if (value & BIT(1))
buttons |= SND_JACK_BTN_1;
if (value & BIT(2))
buttons |= SND_JACK_BTN_2;
if (value & BIT(3))
buttons |= SND_JACK_BTN_3;
if (value & BIT(4))
buttons |= SND_JACK_BTN_4;
if (value & BIT(5))
buttons |= SND_JACK_BTN_5;
return buttons;
}
#define NAU8824_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \
SND_JACK_BTN_2 | SND_JACK_BTN_3)
static irqreturn_t nau8824_interrupt(int irq, void *data)
{
struct nau8824 *nau8824 = (struct nau8824 *)data;
struct regmap *regmap = nau8824->regmap;
int active_irq, clear_irq = 0, event = 0, event_mask = 0;
if (regmap_read(regmap, NAU8824_REG_IRQ, &active_irq)) {
dev_err(nau8824->dev, "failed to read irq status\n");
return IRQ_NONE;
}
dev_dbg(nau8824->dev, "IRQ %x\n", active_irq);
if (active_irq & NAU8824_JACK_EJECTION_DETECTED) {
nau8824_eject_jack(nau8824);
event_mask |= SND_JACK_HEADSET;
clear_irq = NAU8824_JACK_EJECTION_DETECTED;
/* release semaphore held after resume,
* and cancel jack detection
*/
if (nau8824->resume_lock) {
nau8824_sema_release(nau8824);
nau8824->resume_lock = false;
}
cancel_work_sync(&nau8824->jdet_work);
} else if (active_irq & NAU8824_KEY_SHORT_PRESS_IRQ) {
int key_status, button_pressed;
regmap_read(regmap, NAU8824_REG_CLEAR_INT_REG,
&key_status);
/* lower 8 bits of the register are for pressed keys */
button_pressed = nau8824_button_decode(key_status);
event |= button_pressed;
dev_dbg(nau8824->dev, "button %x pressed\n", event);
event_mask |= NAU8824_BUTTONS;
clear_irq = NAU8824_KEY_SHORT_PRESS_IRQ;
} else if (active_irq & NAU8824_KEY_RELEASE_IRQ) {
event_mask = NAU8824_BUTTONS;
clear_irq = NAU8824_KEY_RELEASE_IRQ;
} else if (active_irq & NAU8824_JACK_INSERTION_DETECTED) {
/* Turn off insertion interruption at manual mode */
regmap_update_bits(regmap,
NAU8824_REG_INTERRUPT_SETTING,
NAU8824_IRQ_INSERT_DIS,
NAU8824_IRQ_INSERT_DIS);
regmap_update_bits(regmap,
NAU8824_REG_INTERRUPT_SETTING_1,
NAU8824_IRQ_INSERT_EN, 0);
/* detect microphone and jack type */
cancel_work_sync(&nau8824->jdet_work);
schedule_work(&nau8824->jdet_work);
/* Enable interruption for jack type detection at audo
* mode which can detect microphone and jack type.
*/
nau8824_setup_auto_irq(nau8824);
}
if (!clear_irq)
clear_irq = active_irq;
/* clears the rightmost interruption */
regmap_write(regmap, NAU8824_REG_CLEAR_INT_REG, clear_irq);
if (event_mask)
snd_soc_jack_report(nau8824->jack, event, event_mask);
return IRQ_HANDLED;
}
static const struct nau8824_osr_attr *
nau8824_get_osr(struct nau8824 *nau8824, int stream)
{
unsigned int osr;
if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
regmap_read(nau8824->regmap,
NAU8824_REG_DAC_FILTER_CTRL_1, &osr);
osr &= NAU8824_DAC_OVERSAMPLE_MASK;
if (osr >= ARRAY_SIZE(osr_dac_sel))
return NULL;
return &osr_dac_sel[osr];
} else {
regmap_read(nau8824->regmap,
NAU8824_REG_ADC_FILTER_CTRL, &osr);
osr &= NAU8824_ADC_SYNC_DOWN_MASK;
if (osr >= ARRAY_SIZE(osr_adc_sel))
return NULL;
return &osr_adc_sel[osr];
}
}
static int nau8824_dai_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
const struct nau8824_osr_attr *osr;
osr = nau8824_get_osr(nau8824, substream->stream);
if (!osr || !osr->osr)
return -EINVAL;
return snd_pcm_hw_constraint_minmax(substream->runtime,
SNDRV_PCM_HW_PARAM_RATE,
0, CLK_DA_AD_MAX / osr->osr);
}
static int nau8824_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
unsigned int val_len = 0, ctrl_val, bclk_fs, bclk_div;
const struct nau8824_osr_attr *osr;
int err = -EINVAL;
nau8824_sema_acquire(nau8824, HZ);
/* CLK_DAC or CLK_ADC = OSR * FS
* DAC or ADC clock frequency is defined as Over Sampling Rate (OSR)
* multiplied by the audio sample rate (Fs). Note that the OSR and Fs
* values must be selected such that the maximum frequency is less
* than 6.144 MHz.
*/
nau8824->fs = params_rate(params);
osr = nau8824_get_osr(nau8824, substream->stream);
if (!osr || !osr->osr)
goto error;
if (nau8824->fs * osr->osr > CLK_DA_AD_MAX)
goto error;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER,
NAU8824_CLK_DAC_SRC_MASK,
osr->clk_src << NAU8824_CLK_DAC_SRC_SFT);
else
regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER,
NAU8824_CLK_ADC_SRC_MASK,
osr->clk_src << NAU8824_CLK_ADC_SRC_SFT);
/* make BCLK and LRC divde configuration if the codec as master. */
regmap_read(nau8824->regmap,
NAU8824_REG_PORT0_I2S_PCM_CTRL_2, &ctrl_val);
if (ctrl_val & NAU8824_I2S_MS_MASTER) {
/* get the bclk and fs ratio */
bclk_fs = snd_soc_params_to_bclk(params) / nau8824->fs;
if (bclk_fs <= 32)
bclk_div = 0x3;
else if (bclk_fs <= 64)
bclk_div = 0x2;
else if (bclk_fs <= 128)
bclk_div = 0x1;
else if (bclk_fs <= 256)
bclk_div = 0;
else
goto error;
regmap_update_bits(nau8824->regmap,
NAU8824_REG_PORT0_I2S_PCM_CTRL_2,
NAU8824_I2S_LRC_DIV_MASK | NAU8824_I2S_BLK_DIV_MASK,
(bclk_div << NAU8824_I2S_LRC_DIV_SFT) | bclk_div);
}
switch (params_width(params)) {
case 16:
val_len |= NAU8824_I2S_DL_16;
break;
case 20:
val_len |= NAU8824_I2S_DL_20;
break;
case 24:
val_len |= NAU8824_I2S_DL_24;
break;
case 32:
val_len |= NAU8824_I2S_DL_32;
break;
default:
goto error;
}
regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_1,
NAU8824_I2S_DL_MASK, val_len);
err = 0;
error:
nau8824_sema_release(nau8824);
return err;
}
static int nau8824_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
unsigned int ctrl1_val = 0, ctrl2_val = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
ctrl2_val |= NAU8824_I2S_MS_MASTER;
break;
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
ctrl1_val |= NAU8824_I2S_BP_INV;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
ctrl1_val |= NAU8824_I2S_DF_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
ctrl1_val |= NAU8824_I2S_DF_LEFT;
break;
case SND_SOC_DAIFMT_RIGHT_J:
ctrl1_val |= NAU8824_I2S_DF_RIGTH;
break;
case SND_SOC_DAIFMT_DSP_A:
ctrl1_val |= NAU8824_I2S_DF_PCM_AB;
break;
case SND_SOC_DAIFMT_DSP_B:
ctrl1_val |= NAU8824_I2S_DF_PCM_AB;
ctrl1_val |= NAU8824_I2S_PCMB_EN;
break;
default:
return -EINVAL;
}
nau8824_sema_acquire(nau8824, HZ);
regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_1,
NAU8824_I2S_DF_MASK | NAU8824_I2S_BP_MASK |
NAU8824_I2S_PCMB_EN, ctrl1_val);
regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_2,
NAU8824_I2S_MS_MASK, ctrl2_val);
nau8824_sema_release(nau8824);
return 0;
}
/**
* nau8824_set_tdm_slot - configure DAI TDM.
* @dai: DAI
* @tx_mask: Bitmask representing active TX slots. Ex.
* 0xf for normal 4 channel TDM.
* 0xf0 for shifted 4 channel TDM
* @rx_mask: Bitmask [0:1] representing active DACR RX slots.
* Bitmask [2:3] representing active DACL RX slots.
* 00=CH0,01=CH1,10=CH2,11=CH3. Ex.
* 0xf for DACL/R selecting TDM CH3.
* 0xf0 for DACL/R selecting shifted TDM CH3.
* @slots: Number of slots in use.
* @slot_width: Width in bits for each slot.
*
* Configures a DAI for TDM operation. Only support 4 slots TDM.
*/
static int nau8824_set_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
unsigned int tslot_l = 0, ctrl_val = 0;
if (slots > 4 || ((tx_mask & 0xf0) && (tx_mask & 0xf)) ||
((rx_mask & 0xf0) && (rx_mask & 0xf)) ||
((rx_mask & 0xf0) && (tx_mask & 0xf)) ||
((rx_mask & 0xf) && (tx_mask & 0xf0)))
return -EINVAL;
ctrl_val |= (NAU8824_TDM_MODE | NAU8824_TDM_OFFSET_EN);
if (tx_mask & 0xf0) {
tslot_l = 4 * slot_width;
ctrl_val |= (tx_mask >> 4);
} else {
ctrl_val |= tx_mask;
}
if (rx_mask & 0xf0)
ctrl_val |= ((rx_mask >> 4) << NAU8824_TDM_DACR_RX_SFT);
else
ctrl_val |= (rx_mask << NAU8824_TDM_DACR_RX_SFT);
regmap_update_bits(nau8824->regmap, NAU8824_REG_TDM_CTRL,
NAU8824_TDM_MODE | NAU8824_TDM_OFFSET_EN |
NAU8824_TDM_DACL_RX_MASK | NAU8824_TDM_DACR_RX_MASK |
NAU8824_TDM_TX_MASK, ctrl_val);
regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_LEFT_TIME_SLOT,
NAU8824_TSLOT_L_MASK, tslot_l);
return 0;
}
/**
* nau8824_calc_fll_param - Calculate FLL parameters.
* @fll_in: external clock provided to codec.
* @fs: sampling rate.
* @fll_param: Pointer to structure of FLL parameters.
*
* Calculate FLL parameters to configure codec.
*
* Returns 0 for success or negative error code.
*/
static int nau8824_calc_fll_param(unsigned int fll_in,
unsigned int fs, struct nau8824_fll *fll_param)
{
u64 fvco, fvco_max;
unsigned int fref, i, fvco_sel;
/* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing
* freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
* FREF = freq_in / NAU8824_FLL_REF_DIV_MASK
*/
for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
fref = fll_in / fll_pre_scalar[i].param;
if (fref <= NAU_FREF_MAX)
break;
}
if (i == ARRAY_SIZE(fll_pre_scalar))
return -EINVAL;
fll_param->clk_ref_div = fll_pre_scalar[i].val;
/* Choose the FLL ratio based on FREF */
for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
if (fref >= fll_ratio[i].param)
break;
}
if (i == ARRAY_SIZE(fll_ratio))
return -EINVAL;
fll_param->ratio = fll_ratio[i].val;
/* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.
* FDCO must be within the 90MHz - 124MHz or the FFL cannot be
* guaranteed across the full range of operation.
* FDCO = freq_out * 2 * mclk_src_scaling
*/
fvco_max = 0;
fvco_sel = ARRAY_SIZE(mclk_src_scaling);
for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param;
if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&
fvco_max < fvco) {
fvco_max = fvco;
fvco_sel = i;
}
}
if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel)
return -EINVAL;
fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
/* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional
* input based on FDCO, FREF and FLL ratio.
*/
fvco = div_u64(fvco_max << 16, fref * fll_param->ratio);
fll_param->fll_int = (fvco >> 16) & 0x3FF;
fll_param->fll_frac = fvco & 0xFFFF;
return 0;
}
static void nau8824_fll_apply(struct regmap *regmap,
struct nau8824_fll *fll_param)
{
regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER,
NAU8824_CLK_SRC_MASK | NAU8824_CLK_MCLK_SRC_MASK,
NAU8824_CLK_SRC_MCLK | fll_param->mclk_src);
regmap_update_bits(regmap, NAU8824_REG_FLL1,
NAU8824_FLL_RATIO_MASK, fll_param->ratio);
/* FLL 16-bit fractional input */
regmap_write(regmap, NAU8824_REG_FLL2, fll_param->fll_frac);
/* FLL 10-bit integer input */
regmap_update_bits(regmap, NAU8824_REG_FLL3,
NAU8824_FLL_INTEGER_MASK, fll_param->fll_int);
/* FLL pre-scaler */
regmap_update_bits(regmap, NAU8824_REG_FLL4,
NAU8824_FLL_REF_DIV_MASK,
fll_param->clk_ref_div << NAU8824_FLL_REF_DIV_SFT);
/* select divided VCO input */
regmap_update_bits(regmap, NAU8824_REG_FLL5,
NAU8824_FLL_CLK_SW_MASK, NAU8824_FLL_CLK_SW_REF);
/* Disable free-running mode */
regmap_update_bits(regmap,
NAU8824_REG_FLL6, NAU8824_DCO_EN, 0);
if (fll_param->fll_frac) {
regmap_update_bits(regmap, NAU8824_REG_FLL5,
NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN |
NAU8824_FLL_FTR_SW_MASK,
NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN |
NAU8824_FLL_FTR_SW_FILTER);
regmap_update_bits(regmap, NAU8824_REG_FLL6,
NAU8824_SDM_EN, NAU8824_SDM_EN);
} else {
regmap_update_bits(regmap, NAU8824_REG_FLL5,
NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN |
NAU8824_FLL_FTR_SW_MASK, NAU8824_FLL_FTR_SW_ACCU);
regmap_update_bits(regmap,
NAU8824_REG_FLL6, NAU8824_SDM_EN, 0);
}
}
/* freq_out must be 256*Fs in order to achieve the best performance */
static int nau8824_set_pll(struct snd_soc_component *component, int pll_id, int source,
unsigned int freq_in, unsigned int freq_out)
{
struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
struct nau8824_fll fll_param;
int ret, fs;
fs = freq_out / 256;
ret = nau8824_calc_fll_param(freq_in, fs, &fll_param);
if (ret < 0) {
dev_err(nau8824->dev, "Unsupported input clock %d\n", freq_in);
return ret;
}
dev_dbg(nau8824->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac,
fll_param.fll_int, fll_param.clk_ref_div);
nau8824_fll_apply(nau8824->regmap, &fll_param);
mdelay(2);
regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER,
NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_VCO);
return 0;
}
static int nau8824_config_sysclk(struct nau8824 *nau8824,
int clk_id, unsigned int freq)
{
struct regmap *regmap = nau8824->regmap;
switch (clk_id) {
case NAU8824_CLK_DIS:
regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER,
NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_MCLK);
regmap_update_bits(regmap, NAU8824_REG_FLL6,
NAU8824_DCO_EN, 0);
break;
case NAU8824_CLK_MCLK:
nau8824_sema_acquire(nau8824, HZ);
regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER,
NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_MCLK);
regmap_update_bits(regmap, NAU8824_REG_FLL6,
NAU8824_DCO_EN, 0);
nau8824_sema_release(nau8824);
break;
case NAU8824_CLK_INTERNAL:
regmap_update_bits(regmap, NAU8824_REG_FLL6,
NAU8824_DCO_EN, NAU8824_DCO_EN);
regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER,
NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_VCO);
break;
case NAU8824_CLK_FLL_MCLK:
nau8824_sema_acquire(nau8824, HZ);
regmap_update_bits(regmap, NAU8824_REG_FLL3,
NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_MCLK);
nau8824_sema_release(nau8824);
break;
case NAU8824_CLK_FLL_BLK:
nau8824_sema_acquire(nau8824, HZ);
regmap_update_bits(regmap, NAU8824_REG_FLL3,
NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_BLK);
nau8824_sema_release(nau8824);
break;
case NAU8824_CLK_FLL_FS:
nau8824_sema_acquire(nau8824, HZ);
regmap_update_bits(regmap, NAU8824_REG_FLL3,
NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_FS);
nau8824_sema_release(nau8824);
break;
default:
dev_err(nau8824->dev, "Invalid clock id (%d)\n", clk_id);
return -EINVAL;
}
dev_dbg(nau8824->dev, "Sysclk is %dHz and clock id is %d\n", freq,
clk_id);
return 0;
}
static int nau8824_set_sysclk(struct snd_soc_component *component,
int clk_id, int source, unsigned int freq, int dir)
{
struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
return nau8824_config_sysclk(nau8824, clk_id, freq);
}
static void nau8824_resume_setup(struct nau8824 *nau8824)
{
nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0);
if (nau8824->irq) {
/* Clear all interruption status */
nau8824_int_status_clear_all(nau8824->regmap);
/* Enable jack detection at sleep mode, insertion detection,
* and ejection detection.
*/
regmap_update_bits(nau8824->regmap, NAU8824_REG_ENA_CTRL,
NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE);
regmap_update_bits(nau8824->regmap,
NAU8824_REG_INTERRUPT_SETTING_1,
NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN,
NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN);
regmap_update_bits(nau8824->regmap,
NAU8824_REG_INTERRUPT_SETTING,
NAU8824_IRQ_EJECT_DIS | NAU8824_IRQ_INSERT_DIS, 0);
}
}
static int nau8824_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
/* Setup codec configuration after resume */
nau8824_resume_setup(nau8824);
}
break;
case SND_SOC_BIAS_OFF:
regmap_update_bits(nau8824->regmap,
NAU8824_REG_INTERRUPT_SETTING, 0x3ff, 0x3ff);
regmap_update_bits(nau8824->regmap,
NAU8824_REG_INTERRUPT_SETTING_1,
NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN, 0);
break;
}
return 0;
}
static int nau8824_component_probe(struct snd_soc_component *component)
{
struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
nau8824->dapm = dapm;
return 0;
}
static int __maybe_unused nau8824_suspend(struct snd_soc_component *component)
{
struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
if (nau8824->irq) {
disable_irq(nau8824->irq);
snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
}
regcache_cache_only(nau8824->regmap, true);
regcache_mark_dirty(nau8824->regmap);
return 0;
}
static int __maybe_unused nau8824_resume(struct snd_soc_component *component)
{
struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
int ret;
regcache_cache_only(nau8824->regmap, false);
regcache_sync(nau8824->regmap);
if (nau8824->irq) {
/* Hold semaphore to postpone playback happening
* until jack detection done.
*/
nau8824->resume_lock = true;
ret = nau8824_sema_acquire(nau8824, 0);
if (ret)
nau8824->resume_lock = false;
enable_irq(nau8824->irq);
}
return 0;
}
static const struct snd_soc_component_driver nau8824_component_driver = {
.probe = nau8824_component_probe,
.set_sysclk = nau8824_set_sysclk,
.set_pll = nau8824_set_pll,
.set_bias_level = nau8824_set_bias_level,
.suspend = nau8824_suspend,
.resume = nau8824_resume,
.controls = nau8824_snd_controls,
.num_controls = ARRAY_SIZE(nau8824_snd_controls),
.dapm_widgets = nau8824_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(nau8824_dapm_widgets),
.dapm_routes = nau8824_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(nau8824_dapm_routes),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct snd_soc_dai_ops nau8824_dai_ops = {
.startup = nau8824_dai_startup,
.hw_params = nau8824_hw_params,
.set_fmt = nau8824_set_fmt,
.set_tdm_slot = nau8824_set_tdm_slot,
};
#define NAU8824_RATES SNDRV_PCM_RATE_8000_192000
#define NAU8824_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
| SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver nau8824_dai = {
.name = NAU8824_CODEC_DAI,
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = NAU8824_RATES,
.formats = NAU8824_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = NAU8824_RATES,
.formats = NAU8824_FORMATS,
},
.ops = &nau8824_dai_ops,
};
static const struct regmap_config nau8824_regmap_config = {
.val_bits = NAU8824_REG_ADDR_LEN,
.reg_bits = NAU8824_REG_DATA_LEN,
.max_register = NAU8824_REG_MAX,
.readable_reg = nau8824_readable_reg,
.writeable_reg = nau8824_writeable_reg,
.volatile_reg = nau8824_volatile_reg,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = nau8824_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(nau8824_reg_defaults),
};
/**
* nau8824_enable_jack_detect - Specify a jack for event reporting
*
* @component: component to register the jack with
* @jack: jack to use to report headset and button events on
*
* After this function has been called the headset insert/remove and button
* events will be routed to the given jack. Jack can be null to stop
* reporting.
*/
int nau8824_enable_jack_detect(struct snd_soc_component *component,
struct snd_soc_jack *jack)
{
struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
int ret;
nau8824->jack = jack;
/* Initiate jack detection work queue */
INIT_WORK(&nau8824->jdet_work, nau8824_jdet_work);
ret = devm_request_threaded_irq(nau8824->dev, nau8824->irq, NULL,
nau8824_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT,
"nau8824", nau8824);
if (ret) {
dev_err(nau8824->dev, "Cannot request irq %d (%d)\n",
nau8824->irq, ret);
}
return ret;
}
EXPORT_SYMBOL_GPL(nau8824_enable_jack_detect);
static void nau8824_reset_chip(struct regmap *regmap)
{
regmap_write(regmap, NAU8824_REG_RESET, 0x00);
regmap_write(regmap, NAU8824_REG_RESET, 0x00);
}
static void nau8824_setup_buttons(struct nau8824 *nau8824)
{
struct regmap *regmap = nau8824->regmap;
regmap_update_bits(regmap, NAU8824_REG_SAR_ADC,
NAU8824_SAR_TRACKING_GAIN_MASK,
nau8824->sar_voltage << NAU8824_SAR_TRACKING_GAIN_SFT);
regmap_update_bits(regmap, NAU8824_REG_SAR_ADC,
NAU8824_SAR_COMPARE_TIME_MASK,
nau8824->sar_compare_time << NAU8824_SAR_COMPARE_TIME_SFT);
regmap_update_bits(regmap, NAU8824_REG_SAR_ADC,
NAU8824_SAR_SAMPLING_TIME_MASK,
nau8824->sar_sampling_time << NAU8824_SAR_SAMPLING_TIME_SFT);
regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT,
NAU8824_LEVELS_NR_MASK,
(nau8824->sar_threshold_num - 1) << NAU8824_LEVELS_NR_SFT);
regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT,
NAU8824_HYSTERESIS_MASK,
nau8824->sar_hysteresis << NAU8824_HYSTERESIS_SFT);
regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT,
NAU8824_SHORTKEY_DEBOUNCE_MASK,
nau8824->key_debounce << NAU8824_SHORTKEY_DEBOUNCE_SFT);
regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_1,
(nau8824->sar_threshold[0] << 8) | nau8824->sar_threshold[1]);
regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_2,
(nau8824->sar_threshold[2] << 8) | nau8824->sar_threshold[3]);
regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_3,
(nau8824->sar_threshold[4] << 8) | nau8824->sar_threshold[5]);
regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_4,
(nau8824->sar_threshold[6] << 8) | nau8824->sar_threshold[7]);
}
static void nau8824_init_regs(struct nau8824 *nau8824)
{
struct regmap *regmap = nau8824->regmap;
/* Enable Bias/VMID/VMID Tieoff */
regmap_update_bits(regmap, NAU8824_REG_BIAS_ADJ,
NAU8824_VMID | NAU8824_VMID_SEL_MASK, NAU8824_VMID |
(nau8824->vref_impedance << NAU8824_VMID_SEL_SFT));
regmap_update_bits(regmap, NAU8824_REG_BOOST,
NAU8824_GLOBAL_BIAS_EN, NAU8824_GLOBAL_BIAS_EN);
mdelay(2);
regmap_update_bits(regmap, NAU8824_REG_MIC_BIAS,
NAU8824_MICBIAS_VOLTAGE_MASK, nau8824->micbias_voltage);
/* Disable Boost Driver, Automatic Short circuit protection enable */
regmap_update_bits(regmap, NAU8824_REG_BOOST,
NAU8824_PRECHARGE_DIS | NAU8824_HP_BOOST_DIS |
NAU8824_HP_BOOST_G_DIS | NAU8824_SHORT_SHUTDOWN_EN,
NAU8824_PRECHARGE_DIS | NAU8824_HP_BOOST_DIS |
NAU8824_HP_BOOST_G_DIS | NAU8824_SHORT_SHUTDOWN_EN);
/* Scaling for ADC and DAC clock */
regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER,
NAU8824_CLK_ADC_SRC_MASK | NAU8824_CLK_DAC_SRC_MASK,
(0x1 << NAU8824_CLK_ADC_SRC_SFT) |
(0x1 << NAU8824_CLK_DAC_SRC_SFT));
regmap_update_bits(regmap, NAU8824_REG_DAC_MUTE_CTRL,
NAU8824_DAC_ZC_EN, NAU8824_DAC_ZC_EN);
regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL,
NAU8824_DAC_CH1_EN | NAU8824_DAC_CH0_EN |
NAU8824_ADC_CH0_EN | NAU8824_ADC_CH1_EN |
NAU8824_ADC_CH2_EN | NAU8824_ADC_CH3_EN,
NAU8824_DAC_CH1_EN | NAU8824_DAC_CH0_EN |
NAU8824_ADC_CH0_EN | NAU8824_ADC_CH1_EN |
NAU8824_ADC_CH2_EN | NAU8824_ADC_CH3_EN);
regmap_update_bits(regmap, NAU8824_REG_CLK_GATING_ENA,
NAU8824_CLK_ADC_CH23_EN | NAU8824_CLK_ADC_CH01_EN |
NAU8824_CLK_DAC_CH1_EN | NAU8824_CLK_DAC_CH0_EN |
NAU8824_CLK_I2S_EN | NAU8824_CLK_GAIN_EN |
NAU8824_CLK_SAR_EN | NAU8824_CLK_DMIC_CH23_EN,
NAU8824_CLK_ADC_CH23_EN | NAU8824_CLK_ADC_CH01_EN |
NAU8824_CLK_DAC_CH1_EN | NAU8824_CLK_DAC_CH0_EN |
NAU8824_CLK_I2S_EN | NAU8824_CLK_GAIN_EN |
NAU8824_CLK_SAR_EN | NAU8824_CLK_DMIC_CH23_EN);
/* Class G timer 64ms */
regmap_update_bits(regmap, NAU8824_REG_CLASSG,
NAU8824_CLASSG_TIMER_MASK,
0x20 << NAU8824_CLASSG_TIMER_SFT);
regmap_update_bits(regmap, NAU8824_REG_TRIM_SETTINGS,
NAU8824_DRV_CURR_INC, NAU8824_DRV_CURR_INC);
/* Disable DACR/L power */
regmap_update_bits(regmap, NAU8824_REG_CHARGE_PUMP_CONTROL,
NAU8824_SPKR_PULL_DOWN | NAU8824_SPKL_PULL_DOWN |
NAU8824_POWER_DOWN_DACR | NAU8824_POWER_DOWN_DACL,
NAU8824_SPKR_PULL_DOWN | NAU8824_SPKL_PULL_DOWN |
NAU8824_POWER_DOWN_DACR | NAU8824_POWER_DOWN_DACL);
/* Enable TESTDAC. This sets the analog DAC inputs to a '0' input
* signal to avoid any glitches due to power up transients in both
* the analog and digital DAC circuit.
*/
regmap_update_bits(regmap, NAU8824_REG_ENABLE_LO,
NAU8824_TEST_DAC_EN, NAU8824_TEST_DAC_EN);
/* Config L/R channel */
regmap_update_bits(regmap, NAU8824_REG_DAC_CH0_DGAIN_CTRL,
NAU8824_DAC_CH0_SEL_MASK, NAU8824_DAC_CH0_SEL_I2S0);
regmap_update_bits(regmap, NAU8824_REG_DAC_CH1_DGAIN_CTRL,
NAU8824_DAC_CH1_SEL_MASK, NAU8824_DAC_CH1_SEL_I2S1);
regmap_update_bits(regmap, NAU8824_REG_ENABLE_LO,
NAU8824_DACR_HPR_EN | NAU8824_DACL_HPL_EN,
NAU8824_DACR_HPR_EN | NAU8824_DACL_HPL_EN);
/* Default oversampling/decimations settings are unusable
* (audible hiss). Set it to something better.
*/
regmap_update_bits(regmap, NAU8824_REG_ADC_FILTER_CTRL,
NAU8824_ADC_SYNC_DOWN_MASK, NAU8824_ADC_SYNC_DOWN_64);
regmap_update_bits(regmap, NAU8824_REG_DAC_FILTER_CTRL_1,
NAU8824_DAC_CICCLP_OFF | NAU8824_DAC_OVERSAMPLE_MASK,
NAU8824_DAC_CICCLP_OFF | NAU8824_DAC_OVERSAMPLE_64);
/* DAC clock delay 2ns, VREF */
regmap_update_bits(regmap, NAU8824_REG_RDAC,
NAU8824_RDAC_CLK_DELAY_MASK | NAU8824_RDAC_VREF_MASK,
(0x2 << NAU8824_RDAC_CLK_DELAY_SFT) |
(0x3 << NAU8824_RDAC_VREF_SFT));
/* PGA input mode selection */
regmap_update_bits(regmap, NAU8824_REG_FEPGA,
NAU8824_FEPGA_MODEL_SHORT_EN | NAU8824_FEPGA_MODER_SHORT_EN,
NAU8824_FEPGA_MODEL_SHORT_EN | NAU8824_FEPGA_MODER_SHORT_EN);
/* Digital microphone control */
regmap_update_bits(regmap, NAU8824_REG_ANALOG_CONTROL_1,
NAU8824_DMIC_CLK_DRV_STRG | NAU8824_DMIC_CLK_SLEW_FAST,
NAU8824_DMIC_CLK_DRV_STRG | NAU8824_DMIC_CLK_SLEW_FAST);
regmap_update_bits(regmap, NAU8824_REG_JACK_DET_CTRL,
NAU8824_JACK_LOGIC,
/* jkdet_polarity - 1 is for active-low */
nau8824->jkdet_polarity ? 0 : NAU8824_JACK_LOGIC);
regmap_update_bits(regmap,
NAU8824_REG_JACK_DET_CTRL, NAU8824_JACK_EJECT_DT_MASK,
(nau8824->jack_eject_debounce << NAU8824_JACK_EJECT_DT_SFT));
if (nau8824->sar_threshold_num)
nau8824_setup_buttons(nau8824);
}
static int nau8824_setup_irq(struct nau8824 *nau8824)
{
/* Disable interruption before codec initiation done */
regmap_update_bits(nau8824->regmap, NAU8824_REG_ENA_CTRL,
NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE);
regmap_update_bits(nau8824->regmap,
NAU8824_REG_INTERRUPT_SETTING, 0x3ff, 0x3ff);
regmap_update_bits(nau8824->regmap, NAU8824_REG_INTERRUPT_SETTING_1,
NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN, 0);
return 0;
}
static void nau8824_print_device_properties(struct nau8824 *nau8824)
{
struct device *dev = nau8824->dev;
int i;
dev_dbg(dev, "jkdet-polarity: %d\n", nau8824->jkdet_polarity);
dev_dbg(dev, "micbias-voltage: %d\n", nau8824->micbias_voltage);
dev_dbg(dev, "vref-impedance: %d\n", nau8824->vref_impedance);
dev_dbg(dev, "sar-threshold-num: %d\n", nau8824->sar_threshold_num);
for (i = 0; i < nau8824->sar_threshold_num; i++)
dev_dbg(dev, "sar-threshold[%d]=%x\n", i,
nau8824->sar_threshold[i]);
dev_dbg(dev, "sar-hysteresis: %d\n", nau8824->sar_hysteresis);
dev_dbg(dev, "sar-voltage: %d\n", nau8824->sar_voltage);
dev_dbg(dev, "sar-compare-time: %d\n", nau8824->sar_compare_time);
dev_dbg(dev, "sar-sampling-time: %d\n", nau8824->sar_sampling_time);
dev_dbg(dev, "short-key-debounce: %d\n", nau8824->key_debounce);
dev_dbg(dev, "jack-eject-debounce: %d\n",
nau8824->jack_eject_debounce);
}
static int nau8824_read_device_properties(struct device *dev,
struct nau8824 *nau8824) {
int ret;
ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity",
&nau8824->jkdet_polarity);
if (ret)
nau8824->jkdet_polarity = 1;
ret = device_property_read_u32(dev, "nuvoton,micbias-voltage",
&nau8824->micbias_voltage);
if (ret)
nau8824->micbias_voltage = 6;
ret = device_property_read_u32(dev, "nuvoton,vref-impedance",
&nau8824->vref_impedance);
if (ret)
nau8824->vref_impedance = 2;
ret = device_property_read_u32(dev, "nuvoton,sar-threshold-num",
&nau8824->sar_threshold_num);
if (ret)
nau8824->sar_threshold_num = 4;
ret = device_property_read_u32_array(dev, "nuvoton,sar-threshold",
nau8824->sar_threshold, nau8824->sar_threshold_num);
if (ret) {
nau8824->sar_threshold[0] = 0x0a;
nau8824->sar_threshold[1] = 0x14;
nau8824->sar_threshold[2] = 0x26;
nau8824->sar_threshold[3] = 0x73;
}
ret = device_property_read_u32(dev, "nuvoton,sar-hysteresis",
&nau8824->sar_hysteresis);
if (ret)
nau8824->sar_hysteresis = 0;
ret = device_property_read_u32(dev, "nuvoton,sar-voltage",
&nau8824->sar_voltage);
if (ret)
nau8824->sar_voltage = 6;
ret = device_property_read_u32(dev, "nuvoton,sar-compare-time",
&nau8824->sar_compare_time);
if (ret)
nau8824->sar_compare_time = 1;
ret = device_property_read_u32(dev, "nuvoton,sar-sampling-time",
&nau8824->sar_sampling_time);
if (ret)
nau8824->sar_sampling_time = 1;
ret = device_property_read_u32(dev, "nuvoton,short-key-debounce",
&nau8824->key_debounce);
if (ret)
nau8824->key_debounce = 0;
ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce",
&nau8824->jack_eject_debounce);
if (ret)
nau8824->jack_eject_debounce = 1;
return 0;
}
/* Please keep this list alphabetically sorted */
static const struct dmi_system_id nau8824_quirk_table[] = {
{
/* Cyberbook T116 rugged tablet */
.matches = {
DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "Default string"),
DMI_EXACT_MATCH(DMI_BOARD_NAME, "Cherry Trail CR"),
DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "20170531"),
},
.driver_data = (void *)(NAU8824_JD_ACTIVE_HIGH |
NAU8824_MONO_SPEAKER),
},
{
/* CUBE iwork8 Air */
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "cube"),
DMI_MATCH(DMI_PRODUCT_NAME, "i1-TF"),
DMI_MATCH(DMI_BOARD_NAME, "Cherry Trail CR"),
},
.driver_data = (void *)(NAU8824_MONO_SPEAKER),
},
{
/* Pipo W2S */
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "PIPO"),
DMI_MATCH(DMI_PRODUCT_NAME, "W2S"),
},
.driver_data = (void *)(NAU8824_MONO_SPEAKER),
},
{
/* Positivo CW14Q01P */
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Positivo Tecnologia SA"),
DMI_MATCH(DMI_BOARD_NAME, "CW14Q01P"),
},
.driver_data = (void *)(NAU8824_JD_ACTIVE_HIGH),
},
{
/* Positivo K1424G */
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Positivo Tecnologia SA"),
DMI_MATCH(DMI_BOARD_NAME, "K1424G"),
},
.driver_data = (void *)(NAU8824_JD_ACTIVE_HIGH),
},
{
/* Positivo N14ZP74G */
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Positivo Tecnologia SA"),
DMI_MATCH(DMI_BOARD_NAME, "N14ZP74G"),
},
.driver_data = (void *)(NAU8824_JD_ACTIVE_HIGH),
},
{}
};
static void nau8824_check_quirks(void)
{
const struct dmi_system_id *dmi_id;
if (quirk_override != -1) {
nau8824_quirk = quirk_override;
return;
}
dmi_id = dmi_first_match(nau8824_quirk_table);
if (dmi_id)
nau8824_quirk = (unsigned long)dmi_id->driver_data;
}
const char *nau8824_components(void)
{
nau8824_check_quirks();
if (nau8824_quirk & NAU8824_MONO_SPEAKER)
return "cfg-spk:1";
else
return "cfg-spk:2";
}
EXPORT_SYMBOL_GPL(nau8824_components);
static int nau8824_i2c_probe(struct i2c_client *i2c)
{
struct device *dev = &i2c->dev;
struct nau8824 *nau8824 = dev_get_platdata(dev);
int ret, value;
if (!nau8824) {
nau8824 = devm_kzalloc(dev, sizeof(*nau8824), GFP_KERNEL);
if (!nau8824)
return -ENOMEM;
ret = nau8824_read_device_properties(dev, nau8824);
if (ret)
return ret;
}
i2c_set_clientdata(i2c, nau8824);
nau8824->regmap = devm_regmap_init_i2c(i2c, &nau8824_regmap_config);
if (IS_ERR(nau8824->regmap))
return PTR_ERR(nau8824->regmap);
nau8824->resume_lock = false;
nau8824->dev = dev;
nau8824->irq = i2c->irq;
sema_init(&nau8824->jd_sem, 1);
nau8824_check_quirks();
if (nau8824_quirk & NAU8824_JD_ACTIVE_HIGH)
nau8824->jkdet_polarity = 0;
nau8824_print_device_properties(nau8824);
ret = regmap_read(nau8824->regmap, NAU8824_REG_I2C_DEVICE_ID, &value);
if (ret < 0) {
dev_err(dev, "Failed to read device id from the NAU8824: %d\n",
ret);
return ret;
}
nau8824_reset_chip(nau8824->regmap);
nau8824_init_regs(nau8824);
if (i2c->irq)
nau8824_setup_irq(nau8824);
return devm_snd_soc_register_component(dev,
&nau8824_component_driver, &nau8824_dai, 1);
}
static const struct i2c_device_id nau8824_i2c_ids[] = {
{ "nau8824", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, nau8824_i2c_ids);
#ifdef CONFIG_OF
static const struct of_device_id nau8824_of_ids[] = {
{ .compatible = "nuvoton,nau8824", },
{}
};
MODULE_DEVICE_TABLE(of, nau8824_of_ids);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id nau8824_acpi_match[] = {
{ "10508824", 0 },
{},
};
MODULE_DEVICE_TABLE(acpi, nau8824_acpi_match);
#endif
static struct i2c_driver nau8824_i2c_driver = {
.driver = {
.name = "nau8824",
.of_match_table = of_match_ptr(nau8824_of_ids),
.acpi_match_table = ACPI_PTR(nau8824_acpi_match),
},
.probe = nau8824_i2c_probe,
.id_table = nau8824_i2c_ids,
};
module_i2c_driver(nau8824_i2c_driver);
MODULE_DESCRIPTION("ASoC NAU88L24 driver");
MODULE_AUTHOR("John Hsu <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/nau8824.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* hdac_hdmi.c - ASoc HDA-HDMI codec driver for Intel platforms
*
* Copyright (C) 2014-2015 Intel Corp
* Author: Samreen Nilofer <[email protected]>
* Subhransu S. Prusty <[email protected]>
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*/
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/hdmi.h>
#include <drm/drm_edid.h>
#include <sound/pcm_params.h>
#include <sound/jack.h>
#include <sound/soc.h>
#include <sound/hdaudio_ext.h>
#include <sound/hda_i915.h>
#include <sound/pcm_drm_eld.h>
#include <sound/hda_chmap.h>
#include "../../hda/local.h"
#include "hdac_hdmi.h"
#define NAME_SIZE 32
#define AMP_OUT_MUTE 0xb080
#define AMP_OUT_UNMUTE 0xb000
#define PIN_OUT (AC_PINCTL_OUT_EN)
#define HDA_MAX_CONNECTIONS 32
#define HDA_MAX_CVTS 3
#define HDA_MAX_PORTS 3
#define ELD_MAX_SIZE 256
#define ELD_FIXED_BYTES 20
#define ELD_VER_CEA_861D 2
#define ELD_VER_PARTIAL 31
#define ELD_MAX_MNL 16
struct hdac_hdmi_cvt_params {
unsigned int channels_min;
unsigned int channels_max;
u32 rates;
u64 formats;
unsigned int maxbps;
};
struct hdac_hdmi_cvt {
struct list_head head;
hda_nid_t nid;
const char *name;
struct hdac_hdmi_cvt_params params;
};
/* Currently only spk_alloc, more to be added */
struct hdac_hdmi_parsed_eld {
u8 spk_alloc;
};
struct hdac_hdmi_eld {
bool monitor_present;
bool eld_valid;
int eld_size;
char eld_buffer[ELD_MAX_SIZE];
struct hdac_hdmi_parsed_eld info;
};
struct hdac_hdmi_pin {
struct list_head head;
hda_nid_t nid;
bool mst_capable;
struct hdac_hdmi_port *ports;
int num_ports;
struct hdac_device *hdev;
};
struct hdac_hdmi_port {
struct list_head head;
int id;
struct hdac_hdmi_pin *pin;
int num_mux_nids;
hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
struct hdac_hdmi_eld eld;
const char *jack_pin;
bool is_connect;
struct snd_soc_dapm_context *dapm;
const char *output_pin;
struct work_struct dapm_work;
};
struct hdac_hdmi_pcm {
struct list_head head;
int pcm_id;
struct list_head port_list;
struct hdac_hdmi_cvt *cvt;
struct snd_soc_jack *jack;
int stream_tag;
int channels;
int format;
bool chmap_set;
unsigned char chmap[8]; /* ALSA API channel-map */
struct mutex lock;
int jack_event;
struct snd_kcontrol *eld_ctl;
};
struct hdac_hdmi_dai_port_map {
int dai_id;
struct hdac_hdmi_port *port;
struct hdac_hdmi_cvt *cvt;
};
struct hdac_hdmi_drv_data {
unsigned int vendor_nid;
};
struct hdac_hdmi_priv {
struct hdac_device *hdev;
struct snd_soc_component *component;
struct snd_card *card;
struct hdac_hdmi_dai_port_map dai_map[HDA_MAX_CVTS];
struct list_head pin_list;
struct list_head cvt_list;
struct list_head pcm_list;
int num_pin;
int num_cvt;
int num_ports;
struct mutex pin_mutex;
struct hdac_chmap chmap;
struct hdac_hdmi_drv_data *drv_data;
struct snd_soc_dai_driver *dai_drv;
};
#define hdev_to_hdmi_priv(_hdev) dev_get_drvdata(&(_hdev)->dev)
static struct hdac_hdmi_pcm *
hdac_hdmi_get_pcm_from_cvt(struct hdac_hdmi_priv *hdmi,
struct hdac_hdmi_cvt *cvt)
{
struct hdac_hdmi_pcm *pcm;
list_for_each_entry(pcm, &hdmi->pcm_list, head) {
if (pcm->cvt == cvt)
return pcm;
}
return NULL;
}
static void hdac_hdmi_jack_report(struct hdac_hdmi_pcm *pcm,
struct hdac_hdmi_port *port, bool is_connect)
{
struct hdac_device *hdev = port->pin->hdev;
port->is_connect = is_connect;
if (is_connect) {
/*
* Report Jack connect event when a device is connected
* for the first time where same PCM is attached to multiple
* ports.
*/
if (pcm->jack_event == 0) {
dev_dbg(&hdev->dev,
"jack report for pcm=%d\n",
pcm->pcm_id);
snd_soc_jack_report(pcm->jack, SND_JACK_AVOUT,
SND_JACK_AVOUT);
}
pcm->jack_event++;
} else {
/*
* Report Jack disconnect event when a device is disconnected
* is the only last connected device when same PCM is attached
* to multiple ports.
*/
if (pcm->jack_event == 1)
snd_soc_jack_report(pcm->jack, 0, SND_JACK_AVOUT);
if (pcm->jack_event > 0)
pcm->jack_event--;
}
}
static void hdac_hdmi_port_dapm_update(struct hdac_hdmi_port *port)
{
if (port->is_connect)
snd_soc_dapm_enable_pin(port->dapm, port->jack_pin);
else
snd_soc_dapm_disable_pin(port->dapm, port->jack_pin);
snd_soc_dapm_sync(port->dapm);
}
static void hdac_hdmi_jack_dapm_work(struct work_struct *work)
{
struct hdac_hdmi_port *port;
port = container_of(work, struct hdac_hdmi_port, dapm_work);
hdac_hdmi_port_dapm_update(port);
}
static void hdac_hdmi_jack_report_sync(struct hdac_hdmi_pcm *pcm,
struct hdac_hdmi_port *port, bool is_connect)
{
hdac_hdmi_jack_report(pcm, port, is_connect);
hdac_hdmi_port_dapm_update(port);
}
/* MST supported verbs */
/*
* Get the no devices that can be connected to a port on the Pin widget.
*/
static int hdac_hdmi_get_port_len(struct hdac_device *hdev, hda_nid_t nid)
{
unsigned int caps;
unsigned int type, param;
caps = get_wcaps(hdev, nid);
type = get_wcaps_type(caps);
if (!(caps & AC_WCAP_DIGITAL) || (type != AC_WID_PIN))
return 0;
param = snd_hdac_read_parm_uncached(hdev, nid, AC_PAR_DEVLIST_LEN);
if (param == -1)
return param;
return param & AC_DEV_LIST_LEN_MASK;
}
/*
* Get the port entry select on the pin. Return the port entry
* id selected on the pin. Return 0 means the first port entry
* is selected or MST is not supported.
*/
static int hdac_hdmi_port_select_get(struct hdac_device *hdev,
struct hdac_hdmi_port *port)
{
return snd_hdac_codec_read(hdev, port->pin->nid,
0, AC_VERB_GET_DEVICE_SEL, 0);
}
/*
* Sets the selected port entry for the configuring Pin widget verb.
* returns error if port set is not equal to port get otherwise success
*/
static int hdac_hdmi_port_select_set(struct hdac_device *hdev,
struct hdac_hdmi_port *port)
{
int num_ports;
if (!port->pin->mst_capable)
return 0;
/* AC_PAR_DEVLIST_LEN is 0 based. */
num_ports = hdac_hdmi_get_port_len(hdev, port->pin->nid);
if (num_ports < 0)
return -EIO;
/*
* Device List Length is a 0 based integer value indicating the
* number of sink device that a MST Pin Widget can support.
*/
if (num_ports + 1 < port->id)
return 0;
snd_hdac_codec_write(hdev, port->pin->nid, 0,
AC_VERB_SET_DEVICE_SEL, port->id);
if (port->id != hdac_hdmi_port_select_get(hdev, port))
return -EIO;
dev_dbg(&hdev->dev, "Selected the port=%d\n", port->id);
return 0;
}
static struct hdac_hdmi_pcm *get_hdmi_pcm_from_id(struct hdac_hdmi_priv *hdmi,
int pcm_idx)
{
struct hdac_hdmi_pcm *pcm;
list_for_each_entry(pcm, &hdmi->pcm_list, head) {
if (pcm->pcm_id == pcm_idx)
return pcm;
}
return NULL;
}
static unsigned int sad_format(const u8 *sad)
{
return ((sad[0] >> 0x3) & 0x1f);
}
static unsigned int sad_sample_bits_lpcm(const u8 *sad)
{
return (sad[2] & 7);
}
static int hdac_hdmi_eld_limit_formats(struct snd_pcm_runtime *runtime,
void *eld)
{
u64 formats = SNDRV_PCM_FMTBIT_S16;
int i;
const u8 *sad, *eld_buf = eld;
sad = drm_eld_sad(eld_buf);
if (!sad)
goto format_constraint;
for (i = drm_eld_sad_count(eld_buf); i > 0; i--, sad += 3) {
if (sad_format(sad) == 1) { /* AUDIO_CODING_TYPE_LPCM */
/*
* the controller support 20 and 24 bits in 32 bit
* container so we set S32
*/
if (sad_sample_bits_lpcm(sad) & 0x6)
formats |= SNDRV_PCM_FMTBIT_S32;
}
}
format_constraint:
return snd_pcm_hw_constraint_mask64(runtime, SNDRV_PCM_HW_PARAM_FORMAT,
formats);
}
static void
hdac_hdmi_set_dip_index(struct hdac_device *hdev, hda_nid_t pin_nid,
int packet_index, int byte_index)
{
int val;
val = (packet_index << 5) | (byte_index & 0x1f);
snd_hdac_codec_write(hdev, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
}
struct dp_audio_infoframe {
u8 type; /* 0x84 */
u8 len; /* 0x1b */
u8 ver; /* 0x11 << 2 */
u8 CC02_CT47; /* match with HDMI infoframe from this on */
u8 SS01_SF24;
u8 CXT04;
u8 CA;
u8 LFEPBL01_LSV36_DM_INH7;
};
static int hdac_hdmi_setup_audio_infoframe(struct hdac_device *hdev,
struct hdac_hdmi_pcm *pcm, struct hdac_hdmi_port *port)
{
uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE];
struct hdmi_audio_infoframe frame;
struct hdac_hdmi_pin *pin = port->pin;
struct dp_audio_infoframe dp_ai;
struct hdac_hdmi_priv *hdmi = hdev_to_hdmi_priv(hdev);
struct hdac_hdmi_cvt *cvt = pcm->cvt;
u8 *dip;
int ret;
int i;
const u8 *eld_buf;
u8 conn_type;
int channels, ca;
ca = snd_hdac_channel_allocation(hdev, port->eld.info.spk_alloc,
pcm->channels, pcm->chmap_set, true, pcm->chmap);
channels = snd_hdac_get_active_channels(ca);
hdmi->chmap.ops.set_channel_count(hdev, cvt->nid, channels);
snd_hdac_setup_channel_mapping(&hdmi->chmap, pin->nid, false, ca,
pcm->channels, pcm->chmap, pcm->chmap_set);
eld_buf = port->eld.eld_buffer;
conn_type = drm_eld_get_conn_type(eld_buf);
switch (conn_type) {
case DRM_ELD_CONN_TYPE_HDMI:
hdmi_audio_infoframe_init(&frame);
frame.channels = channels;
frame.channel_allocation = ca;
ret = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
if (ret < 0)
return ret;
break;
case DRM_ELD_CONN_TYPE_DP:
memset(&dp_ai, 0, sizeof(dp_ai));
dp_ai.type = 0x84;
dp_ai.len = 0x1b;
dp_ai.ver = 0x11 << 2;
dp_ai.CC02_CT47 = channels - 1;
dp_ai.CA = ca;
dip = (u8 *)&dp_ai;
break;
default:
dev_err(&hdev->dev, "Invalid connection type: %d\n", conn_type);
return -EIO;
}
/* stop infoframe transmission */
hdac_hdmi_set_dip_index(hdev, pin->nid, 0x0, 0x0);
snd_hdac_codec_write(hdev, pin->nid, 0,
AC_VERB_SET_HDMI_DIP_XMIT, AC_DIPXMIT_DISABLE);
/* Fill infoframe. Index auto-incremented */
hdac_hdmi_set_dip_index(hdev, pin->nid, 0x0, 0x0);
if (conn_type == DRM_ELD_CONN_TYPE_HDMI) {
for (i = 0; i < sizeof(buffer); i++)
snd_hdac_codec_write(hdev, pin->nid, 0,
AC_VERB_SET_HDMI_DIP_DATA, buffer[i]);
} else {
for (i = 0; i < sizeof(dp_ai); i++)
snd_hdac_codec_write(hdev, pin->nid, 0,
AC_VERB_SET_HDMI_DIP_DATA, dip[i]);
}
/* Start infoframe */
hdac_hdmi_set_dip_index(hdev, pin->nid, 0x0, 0x0);
snd_hdac_codec_write(hdev, pin->nid, 0,
AC_VERB_SET_HDMI_DIP_XMIT, AC_DIPXMIT_BEST);
return 0;
}
static int hdac_hdmi_set_stream(struct snd_soc_dai *dai,
void *stream, int direction)
{
struct hdac_hdmi_priv *hdmi = snd_soc_dai_get_drvdata(dai);
struct hdac_device *hdev = hdmi->hdev;
struct hdac_hdmi_dai_port_map *dai_map;
struct hdac_hdmi_pcm *pcm;
struct hdac_stream *hstream;
if (!stream)
return -EINVAL;
hstream = (struct hdac_stream *)stream;
dev_dbg(&hdev->dev, "%s: strm_tag: %d\n", __func__, hstream->stream_tag);
dai_map = &hdmi->dai_map[dai->id];
pcm = hdac_hdmi_get_pcm_from_cvt(hdmi, dai_map->cvt);
if (pcm)
pcm->stream_tag = (hstream->stream_tag << 4);
return 0;
}
static int hdac_hdmi_set_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *hparams, struct snd_soc_dai *dai)
{
struct hdac_hdmi_priv *hdmi = snd_soc_dai_get_drvdata(dai);
struct hdac_hdmi_dai_port_map *dai_map;
struct hdac_hdmi_pcm *pcm;
int format;
dai_map = &hdmi->dai_map[dai->id];
format = snd_hdac_calc_stream_format(params_rate(hparams),
params_channels(hparams), params_format(hparams),
dai->driver->playback.sig_bits, 0);
pcm = hdac_hdmi_get_pcm_from_cvt(hdmi, dai_map->cvt);
if (!pcm)
return -EIO;
pcm->format = format;
pcm->channels = params_channels(hparams);
return 0;
}
static int hdac_hdmi_query_port_connlist(struct hdac_device *hdev,
struct hdac_hdmi_pin *pin,
struct hdac_hdmi_port *port)
{
if (!(get_wcaps(hdev, pin->nid) & AC_WCAP_CONN_LIST)) {
dev_warn(&hdev->dev,
"HDMI: pin %d wcaps %#x does not support connection list\n",
pin->nid, get_wcaps(hdev, pin->nid));
return -EINVAL;
}
if (hdac_hdmi_port_select_set(hdev, port) < 0)
return -EIO;
port->num_mux_nids = snd_hdac_get_connections(hdev, pin->nid,
port->mux_nids, HDA_MAX_CONNECTIONS);
if (port->num_mux_nids == 0)
dev_warn(&hdev->dev,
"No connections found for pin:port %d:%d\n",
pin->nid, port->id);
dev_dbg(&hdev->dev, "num_mux_nids %d for pin:port %d:%d\n",
port->num_mux_nids, pin->nid, port->id);
return port->num_mux_nids;
}
/*
* Query pcm list and return port to which stream is routed.
*
* Also query connection list of the pin, to validate the cvt to port map.
*
* Same stream rendering to multiple ports simultaneously can be done
* possibly, but not supported for now in driver. So return the first port
* connected.
*/
static struct hdac_hdmi_port *hdac_hdmi_get_port_from_cvt(
struct hdac_device *hdev,
struct hdac_hdmi_priv *hdmi,
struct hdac_hdmi_cvt *cvt)
{
struct hdac_hdmi_pcm *pcm;
struct hdac_hdmi_port *port;
int ret, i;
list_for_each_entry(pcm, &hdmi->pcm_list, head) {
if (pcm->cvt == cvt) {
if (list_empty(&pcm->port_list))
continue;
list_for_each_entry(port, &pcm->port_list, head) {
mutex_lock(&pcm->lock);
ret = hdac_hdmi_query_port_connlist(hdev,
port->pin, port);
mutex_unlock(&pcm->lock);
if (ret < 0)
continue;
for (i = 0; i < port->num_mux_nids; i++) {
if (port->mux_nids[i] == cvt->nid &&
port->eld.monitor_present &&
port->eld.eld_valid)
return port;
}
}
}
}
return NULL;
}
/*
* Go through all converters and ensure connection is set to
* the correct pin as set via kcontrols.
*/
static void hdac_hdmi_verify_connect_sel_all_pins(struct hdac_device *hdev)
{
struct hdac_hdmi_priv *hdmi = hdev_to_hdmi_priv(hdev);
struct hdac_hdmi_port *port;
struct hdac_hdmi_cvt *cvt;
int cvt_idx = 0;
list_for_each_entry(cvt, &hdmi->cvt_list, head) {
port = hdac_hdmi_get_port_from_cvt(hdev, hdmi, cvt);
if (port && port->pin) {
snd_hdac_codec_write(hdev, port->pin->nid, 0,
AC_VERB_SET_CONNECT_SEL, cvt_idx);
dev_dbg(&hdev->dev, "%s: %s set connect %d -> %d\n",
__func__, cvt->name, port->pin->nid, cvt_idx);
}
++cvt_idx;
}
}
/*
* This tries to get a valid pin and set the HW constraints based on the
* ELD. Even if a valid pin is not found return success so that device open
* doesn't fail.
*/
static int hdac_hdmi_pcm_open(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct hdac_hdmi_priv *hdmi = snd_soc_dai_get_drvdata(dai);
struct hdac_device *hdev = hdmi->hdev;
struct hdac_hdmi_dai_port_map *dai_map;
struct hdac_hdmi_cvt *cvt;
struct hdac_hdmi_port *port;
int ret;
dai_map = &hdmi->dai_map[dai->id];
cvt = dai_map->cvt;
port = hdac_hdmi_get_port_from_cvt(hdev, hdmi, cvt);
/*
* To make PA and other userland happy.
* userland scans devices so returning error does not help.
*/
if (!port)
return 0;
if ((!port->eld.monitor_present) ||
(!port->eld.eld_valid)) {
dev_warn(&hdev->dev,
"Failed: present?:%d ELD valid?:%d pin:port: %d:%d\n",
port->eld.monitor_present, port->eld.eld_valid,
port->pin->nid, port->id);
return 0;
}
dai_map->port = port;
ret = hdac_hdmi_eld_limit_formats(substream->runtime,
port->eld.eld_buffer);
if (ret < 0)
return ret;
return snd_pcm_hw_constraint_eld(substream->runtime,
port->eld.eld_buffer);
}
static void hdac_hdmi_pcm_close(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct hdac_hdmi_priv *hdmi = snd_soc_dai_get_drvdata(dai);
struct hdac_hdmi_dai_port_map *dai_map;
struct hdac_hdmi_pcm *pcm;
dai_map = &hdmi->dai_map[dai->id];
pcm = hdac_hdmi_get_pcm_from_cvt(hdmi, dai_map->cvt);
if (pcm) {
mutex_lock(&pcm->lock);
pcm->chmap_set = false;
memset(pcm->chmap, 0, sizeof(pcm->chmap));
pcm->channels = 0;
mutex_unlock(&pcm->lock);
}
if (dai_map->port)
dai_map->port = NULL;
}
static int
hdac_hdmi_query_cvt_params(struct hdac_device *hdev, struct hdac_hdmi_cvt *cvt)
{
unsigned int chans;
struct hdac_hdmi_priv *hdmi = hdev_to_hdmi_priv(hdev);
int err;
chans = get_wcaps(hdev, cvt->nid);
chans = get_wcaps_channels(chans);
cvt->params.channels_min = 2;
cvt->params.channels_max = chans;
if (chans > hdmi->chmap.channels_max)
hdmi->chmap.channels_max = chans;
err = snd_hdac_query_supported_pcm(hdev, cvt->nid,
&cvt->params.rates,
&cvt->params.formats,
&cvt->params.maxbps);
if (err < 0)
dev_err(&hdev->dev,
"Failed to query pcm params for nid %d: %d\n",
cvt->nid, err);
return err;
}
static int hdac_hdmi_fill_widget_info(struct device *dev,
struct snd_soc_dapm_widget *w, enum snd_soc_dapm_type id,
void *priv, const char *wname, const char *stream,
struct snd_kcontrol_new *wc, int numkc,
int (*event)(struct snd_soc_dapm_widget *,
struct snd_kcontrol *, int), unsigned short event_flags)
{
w->id = id;
w->name = devm_kstrdup(dev, wname, GFP_KERNEL);
if (!w->name)
return -ENOMEM;
w->sname = stream;
w->reg = SND_SOC_NOPM;
w->shift = 0;
w->kcontrol_news = wc;
w->num_kcontrols = numkc;
w->priv = priv;
w->event = event;
w->event_flags = event_flags;
return 0;
}
static void hdac_hdmi_fill_route(struct snd_soc_dapm_route *route,
const char *sink, const char *control, const char *src,
int (*handler)(struct snd_soc_dapm_widget *src,
struct snd_soc_dapm_widget *sink))
{
route->sink = sink;
route->source = src;
route->control = control;
route->connected = handler;
}
static struct hdac_hdmi_pcm *hdac_hdmi_get_pcm(struct hdac_device *hdev,
struct hdac_hdmi_port *port)
{
struct hdac_hdmi_priv *hdmi = hdev_to_hdmi_priv(hdev);
struct hdac_hdmi_pcm *pcm;
struct hdac_hdmi_port *p;
list_for_each_entry(pcm, &hdmi->pcm_list, head) {
if (list_empty(&pcm->port_list))
continue;
list_for_each_entry(p, &pcm->port_list, head) {
if (p->id == port->id && port->pin == p->pin)
return pcm;
}
}
return NULL;
}
static void hdac_hdmi_set_power_state(struct hdac_device *hdev,
hda_nid_t nid, unsigned int pwr_state)
{
int count;
unsigned int state;
if (get_wcaps(hdev, nid) & AC_WCAP_POWER) {
if (!snd_hdac_check_power_state(hdev, nid, pwr_state)) {
for (count = 0; count < 10; count++) {
snd_hdac_codec_read(hdev, nid, 0,
AC_VERB_SET_POWER_STATE,
pwr_state);
state = snd_hdac_sync_power_state(hdev,
nid, pwr_state);
if (!(state & AC_PWRST_ERROR))
break;
}
}
}
}
static void hdac_hdmi_set_amp(struct hdac_device *hdev,
hda_nid_t nid, int val)
{
if (get_wcaps(hdev, nid) & AC_WCAP_OUT_AMP)
snd_hdac_codec_write(hdev, nid, 0,
AC_VERB_SET_AMP_GAIN_MUTE, val);
}
static int hdac_hdmi_pin_output_widget_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kc, int event)
{
struct hdac_hdmi_port *port = w->priv;
struct hdac_device *hdev = dev_to_hdac_dev(w->dapm->dev);
struct hdac_hdmi_pcm *pcm;
dev_dbg(&hdev->dev, "%s: widget: %s event: %x\n",
__func__, w->name, event);
pcm = hdac_hdmi_get_pcm(hdev, port);
if (!pcm)
return -EIO;
/* set the device if pin is mst_capable */
if (hdac_hdmi_port_select_set(hdev, port) < 0)
return -EIO;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
hdac_hdmi_set_power_state(hdev, port->pin->nid, AC_PWRST_D0);
/* Enable out path for this pin widget */
snd_hdac_codec_write(hdev, port->pin->nid, 0,
AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
hdac_hdmi_set_amp(hdev, port->pin->nid, AMP_OUT_UNMUTE);
return hdac_hdmi_setup_audio_infoframe(hdev, pcm, port);
case SND_SOC_DAPM_POST_PMD:
hdac_hdmi_set_amp(hdev, port->pin->nid, AMP_OUT_MUTE);
/* Disable out path for this pin widget */
snd_hdac_codec_write(hdev, port->pin->nid, 0,
AC_VERB_SET_PIN_WIDGET_CONTROL, 0);
hdac_hdmi_set_power_state(hdev, port->pin->nid, AC_PWRST_D3);
break;
}
return 0;
}
static int hdac_hdmi_cvt_output_widget_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kc, int event)
{
struct hdac_hdmi_cvt *cvt = w->priv;
struct hdac_device *hdev = dev_to_hdac_dev(w->dapm->dev);
struct hdac_hdmi_priv *hdmi = hdev_to_hdmi_priv(hdev);
struct hdac_hdmi_pcm *pcm;
dev_dbg(&hdev->dev, "%s: widget: %s event: %x\n",
__func__, w->name, event);
pcm = hdac_hdmi_get_pcm_from_cvt(hdmi, cvt);
if (!pcm)
return -EIO;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
hdac_hdmi_set_power_state(hdev, cvt->nid, AC_PWRST_D0);
/* Enable transmission */
snd_hdac_codec_write(hdev, cvt->nid, 0,
AC_VERB_SET_DIGI_CONVERT_1, 1);
/* Category Code (CC) to zero */
snd_hdac_codec_write(hdev, cvt->nid, 0,
AC_VERB_SET_DIGI_CONVERT_2, 0);
snd_hdac_codec_write(hdev, cvt->nid, 0,
AC_VERB_SET_CHANNEL_STREAMID, pcm->stream_tag);
snd_hdac_codec_write(hdev, cvt->nid, 0,
AC_VERB_SET_STREAM_FORMAT, pcm->format);
/*
* The connection indices are shared by all converters and
* may interfere with each other. Ensure correct
* routing for all converters at stream start.
*/
hdac_hdmi_verify_connect_sel_all_pins(hdev);
break;
case SND_SOC_DAPM_POST_PMD:
snd_hdac_codec_write(hdev, cvt->nid, 0,
AC_VERB_SET_CHANNEL_STREAMID, 0);
snd_hdac_codec_write(hdev, cvt->nid, 0,
AC_VERB_SET_STREAM_FORMAT, 0);
hdac_hdmi_set_power_state(hdev, cvt->nid, AC_PWRST_D3);
break;
}
return 0;
}
static int hdac_hdmi_pin_mux_widget_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kc, int event)
{
struct hdac_hdmi_port *port = w->priv;
struct hdac_device *hdev = dev_to_hdac_dev(w->dapm->dev);
int mux_idx;
dev_dbg(&hdev->dev, "%s: widget: %s event: %x\n",
__func__, w->name, event);
if (!kc)
kc = w->kcontrols[0];
mux_idx = dapm_kcontrol_get_value(kc);
/* set the device if pin is mst_capable */
if (hdac_hdmi_port_select_set(hdev, port) < 0)
return -EIO;
if (mux_idx > 0) {
snd_hdac_codec_write(hdev, port->pin->nid, 0,
AC_VERB_SET_CONNECT_SEL, (mux_idx - 1));
}
return 0;
}
/*
* Based on user selection, map the PINs with the PCMs.
*/
static int hdac_hdmi_set_pin_port_mux(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
int ret;
struct hdac_hdmi_port *p, *p_next;
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kcontrol);
struct snd_soc_dapm_context *dapm = w->dapm;
struct hdac_hdmi_port *port = w->priv;
struct hdac_device *hdev = dev_to_hdac_dev(dapm->dev);
struct hdac_hdmi_priv *hdmi = hdev_to_hdmi_priv(hdev);
struct hdac_hdmi_pcm *pcm;
const char *cvt_name = e->texts[ucontrol->value.enumerated.item[0]];
ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
if (ret < 0)
return ret;
if (port == NULL)
return -EINVAL;
mutex_lock(&hdmi->pin_mutex);
list_for_each_entry(pcm, &hdmi->pcm_list, head) {
if (list_empty(&pcm->port_list))
continue;
list_for_each_entry_safe(p, p_next, &pcm->port_list, head) {
if (p == port && p->id == port->id &&
p->pin == port->pin) {
hdac_hdmi_jack_report_sync(pcm, port, false);
list_del(&p->head);
}
}
}
/*
* Jack status is not reported during device probe as the
* PCMs are not registered by then. So report it here.
*/
list_for_each_entry(pcm, &hdmi->pcm_list, head) {
if (!strcmp(cvt_name, pcm->cvt->name)) {
list_add_tail(&port->head, &pcm->port_list);
if (port->eld.monitor_present && port->eld.eld_valid) {
hdac_hdmi_jack_report_sync(pcm, port, true);
mutex_unlock(&hdmi->pin_mutex);
return ret;
}
}
}
mutex_unlock(&hdmi->pin_mutex);
return ret;
}
/*
* Ideally the Mux inputs should be based on the num_muxs enumerated, but
* the display driver seem to be programming the connection list for the pin
* widget runtime.
*
* So programming all the possible inputs for the mux, the user has to take
* care of selecting the right one and leaving all other inputs selected to
* "NONE"
*/
static int hdac_hdmi_create_pin_port_muxs(struct hdac_device *hdev,
struct hdac_hdmi_port *port,
struct snd_soc_dapm_widget *widget,
const char *widget_name)
{
struct hdac_hdmi_priv *hdmi = hdev_to_hdmi_priv(hdev);
struct hdac_hdmi_pin *pin = port->pin;
struct snd_kcontrol_new *kc;
struct hdac_hdmi_cvt *cvt;
struct soc_enum *se;
char kc_name[NAME_SIZE];
char mux_items[NAME_SIZE];
/* To hold inputs to the Pin mux */
char *items[HDA_MAX_CONNECTIONS];
int i = 0;
int num_items = hdmi->num_cvt + 1;
kc = devm_kzalloc(&hdev->dev, sizeof(*kc), GFP_KERNEL);
if (!kc)
return -ENOMEM;
se = devm_kzalloc(&hdev->dev, sizeof(*se), GFP_KERNEL);
if (!se)
return -ENOMEM;
snprintf(kc_name, NAME_SIZE, "Pin %d port %d Input",
pin->nid, port->id);
kc->name = devm_kstrdup(&hdev->dev, kc_name, GFP_KERNEL);
if (!kc->name)
return -ENOMEM;
kc->private_value = (long)se;
kc->iface = SNDRV_CTL_ELEM_IFACE_MIXER;
kc->access = 0;
kc->info = snd_soc_info_enum_double;
kc->put = hdac_hdmi_set_pin_port_mux;
kc->get = snd_soc_dapm_get_enum_double;
se->reg = SND_SOC_NOPM;
/* enum texts: ["NONE", "cvt #", "cvt #", ...] */
se->items = num_items;
se->mask = roundup_pow_of_two(se->items) - 1;
sprintf(mux_items, "NONE");
items[i] = devm_kstrdup(&hdev->dev, mux_items, GFP_KERNEL);
if (!items[i])
return -ENOMEM;
list_for_each_entry(cvt, &hdmi->cvt_list, head) {
i++;
sprintf(mux_items, "cvt %d", cvt->nid);
items[i] = devm_kstrdup(&hdev->dev, mux_items, GFP_KERNEL);
if (!items[i])
return -ENOMEM;
}
se->texts = devm_kmemdup(&hdev->dev, items,
(num_items * sizeof(char *)), GFP_KERNEL);
if (!se->texts)
return -ENOMEM;
return hdac_hdmi_fill_widget_info(&hdev->dev, widget,
snd_soc_dapm_mux, port, widget_name, NULL, kc, 1,
hdac_hdmi_pin_mux_widget_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_REG);
}
/* Add cvt <- input <- mux route map */
static void hdac_hdmi_add_pinmux_cvt_route(struct hdac_device *hdev,
struct snd_soc_dapm_widget *widgets,
struct snd_soc_dapm_route *route, int rindex)
{
struct hdac_hdmi_priv *hdmi = hdev_to_hdmi_priv(hdev);
const struct snd_kcontrol_new *kc;
struct soc_enum *se;
int mux_index = hdmi->num_cvt + hdmi->num_ports;
int i, j;
for (i = 0; i < hdmi->num_ports; i++) {
kc = widgets[mux_index].kcontrol_news;
se = (struct soc_enum *)kc->private_value;
for (j = 0; j < hdmi->num_cvt; j++) {
hdac_hdmi_fill_route(&route[rindex],
widgets[mux_index].name,
se->texts[j + 1],
widgets[j].name, NULL);
rindex++;
}
mux_index++;
}
}
/*
* Widgets are added in the below sequence
* Converter widgets for num converters enumerated
* Pin-port widgets for num ports for Pins enumerated
* Pin-port mux widgets to represent connenction list of pin widget
*
* For each port, one Mux and One output widget is added
* Total widgets elements = num_cvt + (num_ports * 2);
*
* Routes are added as below:
* pin-port mux -> pin (based on num_ports)
* cvt -> "Input sel control" -> pin-port_mux
*
* Total route elements:
* num_ports + (pin_muxes * num_cvt)
*/
static int create_fill_widget_route_map(struct snd_soc_dapm_context *dapm)
{
struct snd_soc_dapm_widget *widgets;
struct snd_soc_dapm_route *route;
struct hdac_device *hdev = dev_to_hdac_dev(dapm->dev);
struct hdac_hdmi_priv *hdmi = hdev_to_hdmi_priv(hdev);
struct snd_soc_dai_driver *dai_drv = hdmi->dai_drv;
char widget_name[NAME_SIZE];
struct hdac_hdmi_cvt *cvt;
struct hdac_hdmi_pin *pin;
int ret, i = 0, num_routes = 0, j;
if (list_empty(&hdmi->cvt_list) || list_empty(&hdmi->pin_list))
return -EINVAL;
widgets = devm_kzalloc(dapm->dev, (sizeof(*widgets) *
((2 * hdmi->num_ports) + hdmi->num_cvt)),
GFP_KERNEL);
if (!widgets)
return -ENOMEM;
/* DAPM widgets to represent each converter widget */
list_for_each_entry(cvt, &hdmi->cvt_list, head) {
sprintf(widget_name, "Converter %d", cvt->nid);
ret = hdac_hdmi_fill_widget_info(dapm->dev, &widgets[i],
snd_soc_dapm_aif_in, cvt,
widget_name, dai_drv[i].playback.stream_name, NULL, 0,
hdac_hdmi_cvt_output_widget_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD);
if (ret < 0)
return ret;
i++;
}
list_for_each_entry(pin, &hdmi->pin_list, head) {
for (j = 0; j < pin->num_ports; j++) {
sprintf(widget_name, "hif%d-%d Output",
pin->nid, pin->ports[j].id);
ret = hdac_hdmi_fill_widget_info(dapm->dev, &widgets[i],
snd_soc_dapm_output, &pin->ports[j],
widget_name, NULL, NULL, 0,
hdac_hdmi_pin_output_widget_event,
SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMD);
if (ret < 0)
return ret;
pin->ports[j].output_pin = widgets[i].name;
i++;
}
}
/* DAPM widgets to represent the connection list to pin widget */
list_for_each_entry(pin, &hdmi->pin_list, head) {
for (j = 0; j < pin->num_ports; j++) {
sprintf(widget_name, "Pin%d-Port%d Mux",
pin->nid, pin->ports[j].id);
ret = hdac_hdmi_create_pin_port_muxs(hdev,
&pin->ports[j], &widgets[i],
widget_name);
if (ret < 0)
return ret;
i++;
/* For cvt to pin_mux mapping */
num_routes += hdmi->num_cvt;
/* For pin_mux to pin mapping */
num_routes++;
}
}
route = devm_kzalloc(dapm->dev, (sizeof(*route) * num_routes),
GFP_KERNEL);
if (!route)
return -ENOMEM;
i = 0;
/* Add pin <- NULL <- mux route map */
list_for_each_entry(pin, &hdmi->pin_list, head) {
for (j = 0; j < pin->num_ports; j++) {
int sink_index = i + hdmi->num_cvt;
int src_index = sink_index + pin->num_ports *
hdmi->num_pin;
hdac_hdmi_fill_route(&route[i],
widgets[sink_index].name, NULL,
widgets[src_index].name, NULL);
i++;
}
}
hdac_hdmi_add_pinmux_cvt_route(hdev, widgets, route, i);
snd_soc_dapm_new_controls(dapm, widgets,
((2 * hdmi->num_ports) + hdmi->num_cvt));
snd_soc_dapm_add_routes(dapm, route, num_routes);
snd_soc_dapm_new_widgets(dapm->card);
return 0;
}
static int hdac_hdmi_init_dai_map(struct hdac_device *hdev)
{
struct hdac_hdmi_priv *hdmi = hdev_to_hdmi_priv(hdev);
struct hdac_hdmi_dai_port_map *dai_map;
struct hdac_hdmi_cvt *cvt;
int dai_id = 0;
if (list_empty(&hdmi->cvt_list))
return -EINVAL;
list_for_each_entry(cvt, &hdmi->cvt_list, head) {
dai_map = &hdmi->dai_map[dai_id];
dai_map->dai_id = dai_id;
dai_map->cvt = cvt;
dai_id++;
if (dai_id == HDA_MAX_CVTS) {
dev_warn(&hdev->dev,
"Max dais supported: %d\n", dai_id);
break;
}
}
return 0;
}
static int hdac_hdmi_add_cvt(struct hdac_device *hdev, hda_nid_t nid)
{
struct hdac_hdmi_priv *hdmi = hdev_to_hdmi_priv(hdev);
struct hdac_hdmi_cvt *cvt;
char name[NAME_SIZE];
cvt = devm_kzalloc(&hdev->dev, sizeof(*cvt), GFP_KERNEL);
if (!cvt)
return -ENOMEM;
cvt->nid = nid;
sprintf(name, "cvt %d", cvt->nid);
cvt->name = devm_kstrdup(&hdev->dev, name, GFP_KERNEL);
if (!cvt->name)
return -ENOMEM;
list_add_tail(&cvt->head, &hdmi->cvt_list);
hdmi->num_cvt++;
return hdac_hdmi_query_cvt_params(hdev, cvt);
}
static int hdac_hdmi_parse_eld(struct hdac_device *hdev,
struct hdac_hdmi_port *port)
{
unsigned int ver, mnl;
ver = (port->eld.eld_buffer[DRM_ELD_VER] & DRM_ELD_VER_MASK)
>> DRM_ELD_VER_SHIFT;
if (ver != ELD_VER_CEA_861D && ver != ELD_VER_PARTIAL) {
dev_err(&hdev->dev, "HDMI: Unknown ELD version %d\n", ver);
return -EINVAL;
}
mnl = (port->eld.eld_buffer[DRM_ELD_CEA_EDID_VER_MNL] &
DRM_ELD_MNL_MASK) >> DRM_ELD_MNL_SHIFT;
if (mnl > ELD_MAX_MNL) {
dev_err(&hdev->dev, "HDMI: MNL Invalid %d\n", mnl);
return -EINVAL;
}
port->eld.info.spk_alloc = port->eld.eld_buffer[DRM_ELD_SPEAKER];
return 0;
}
static void hdac_hdmi_present_sense(struct hdac_hdmi_pin *pin,
struct hdac_hdmi_port *port)
{
struct hdac_device *hdev = pin->hdev;
struct hdac_hdmi_priv *hdmi = hdev_to_hdmi_priv(hdev);
struct hdac_hdmi_pcm *pcm;
int size = 0;
int port_id = -1;
bool eld_valid, eld_changed;
if (!hdmi)
return;
/*
* In case of non MST pin, get_eld info API expectes port
* to be -1.
*/
mutex_lock(&hdmi->pin_mutex);
port->eld.monitor_present = false;
if (pin->mst_capable)
port_id = port->id;
size = snd_hdac_acomp_get_eld(hdev, pin->nid, port_id,
&port->eld.monitor_present,
port->eld.eld_buffer,
ELD_MAX_SIZE);
if (size > 0) {
size = min(size, ELD_MAX_SIZE);
if (hdac_hdmi_parse_eld(hdev, port) < 0)
size = -EINVAL;
}
eld_valid = port->eld.eld_valid;
if (size > 0) {
port->eld.eld_valid = true;
port->eld.eld_size = size;
} else {
port->eld.eld_valid = false;
port->eld.eld_size = 0;
}
eld_changed = (eld_valid != port->eld.eld_valid);
pcm = hdac_hdmi_get_pcm(hdev, port);
if (!port->eld.monitor_present || !port->eld.eld_valid) {
dev_err(&hdev->dev, "%s: disconnect for pin:port %d:%d\n",
__func__, pin->nid, port->id);
/*
* PCMs are not registered during device probe, so don't
* report jack here. It will be done in usermode mux
* control select.
*/
if (pcm) {
hdac_hdmi_jack_report(pcm, port, false);
schedule_work(&port->dapm_work);
}
mutex_unlock(&hdmi->pin_mutex);
return;
}
if (port->eld.monitor_present && port->eld.eld_valid) {
if (pcm) {
hdac_hdmi_jack_report(pcm, port, true);
schedule_work(&port->dapm_work);
}
print_hex_dump_debug("ELD: ", DUMP_PREFIX_OFFSET, 16, 1,
port->eld.eld_buffer, port->eld.eld_size, false);
}
mutex_unlock(&hdmi->pin_mutex);
if (eld_changed && pcm)
snd_ctl_notify(hdmi->card,
SNDRV_CTL_EVENT_MASK_VALUE |
SNDRV_CTL_EVENT_MASK_INFO,
&pcm->eld_ctl->id);
}
static int hdac_hdmi_add_ports(struct hdac_device *hdev,
struct hdac_hdmi_pin *pin)
{
struct hdac_hdmi_port *ports;
int max_ports = HDA_MAX_PORTS;
int i;
/*
* FIXME: max_port may vary for each platform, so pass this as
* as driver data or query from i915 interface when this API is
* implemented.
*/
ports = devm_kcalloc(&hdev->dev, max_ports, sizeof(*ports), GFP_KERNEL);
if (!ports)
return -ENOMEM;
for (i = 0; i < max_ports; i++) {
ports[i].id = i;
ports[i].pin = pin;
INIT_WORK(&ports[i].dapm_work, hdac_hdmi_jack_dapm_work);
}
pin->ports = ports;
pin->num_ports = max_ports;
return 0;
}
static int hdac_hdmi_add_pin(struct hdac_device *hdev, hda_nid_t nid)
{
struct hdac_hdmi_priv *hdmi = hdev_to_hdmi_priv(hdev);
struct hdac_hdmi_pin *pin;
int ret;
pin = devm_kzalloc(&hdev->dev, sizeof(*pin), GFP_KERNEL);
if (!pin)
return -ENOMEM;
pin->nid = nid;
pin->mst_capable = false;
pin->hdev = hdev;
ret = hdac_hdmi_add_ports(hdev, pin);
if (ret < 0)
return ret;
list_add_tail(&pin->head, &hdmi->pin_list);
hdmi->num_pin++;
hdmi->num_ports += pin->num_ports;
return 0;
}
#define INTEL_VENDOR_NID 0x08
#define INTEL_GLK_VENDOR_NID 0x0b
#define INTEL_GET_VENDOR_VERB 0xf81
#define INTEL_SET_VENDOR_VERB 0x781
#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
static void hdac_hdmi_skl_enable_all_pins(struct hdac_device *hdev)
{
unsigned int vendor_param;
struct hdac_hdmi_priv *hdmi = hdev_to_hdmi_priv(hdev);
unsigned int vendor_nid = hdmi->drv_data->vendor_nid;
vendor_param = snd_hdac_codec_read(hdev, vendor_nid, 0,
INTEL_GET_VENDOR_VERB, 0);
if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
return;
vendor_param |= INTEL_EN_ALL_PIN_CVTS;
vendor_param = snd_hdac_codec_read(hdev, vendor_nid, 0,
INTEL_SET_VENDOR_VERB, vendor_param);
if (vendor_param == -1)
return;
}
static void hdac_hdmi_skl_enable_dp12(struct hdac_device *hdev)
{
unsigned int vendor_param;
struct hdac_hdmi_priv *hdmi = hdev_to_hdmi_priv(hdev);
unsigned int vendor_nid = hdmi->drv_data->vendor_nid;
vendor_param = snd_hdac_codec_read(hdev, vendor_nid, 0,
INTEL_GET_VENDOR_VERB, 0);
if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
return;
/* enable DP1.2 mode */
vendor_param |= INTEL_EN_DP12;
vendor_param = snd_hdac_codec_read(hdev, vendor_nid, 0,
INTEL_SET_VENDOR_VERB, vendor_param);
if (vendor_param == -1)
return;
}
static int hdac_hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct hdac_hdmi_priv *hdmi = snd_soc_component_get_drvdata(component);
struct hdac_hdmi_pcm *pcm;
struct hdac_hdmi_port *port;
struct hdac_hdmi_eld *eld;
uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
uinfo->count = 0;
pcm = get_hdmi_pcm_from_id(hdmi, kcontrol->id.device);
if (!pcm) {
dev_dbg(component->dev, "%s: no pcm, device %d\n", __func__,
kcontrol->id.device);
return 0;
}
if (list_empty(&pcm->port_list)) {
dev_dbg(component->dev, "%s: empty port list, device %d\n",
__func__, kcontrol->id.device);
return 0;
}
mutex_lock(&hdmi->pin_mutex);
list_for_each_entry(port, &pcm->port_list, head) {
eld = &port->eld;
if (eld->eld_valid) {
uinfo->count = eld->eld_size;
break;
}
}
mutex_unlock(&hdmi->pin_mutex);
return 0;
}
static int hdac_hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct hdac_hdmi_priv *hdmi = snd_soc_component_get_drvdata(component);
struct hdac_hdmi_pcm *pcm;
struct hdac_hdmi_port *port;
struct hdac_hdmi_eld *eld;
memset(ucontrol->value.bytes.data, 0, sizeof(ucontrol->value.bytes.data));
pcm = get_hdmi_pcm_from_id(hdmi, kcontrol->id.device);
if (!pcm) {
dev_dbg(component->dev, "%s: no pcm, device %d\n", __func__,
kcontrol->id.device);
return 0;
}
if (list_empty(&pcm->port_list)) {
dev_dbg(component->dev, "%s: empty port list, device %d\n",
__func__, kcontrol->id.device);
return 0;
}
mutex_lock(&hdmi->pin_mutex);
list_for_each_entry(port, &pcm->port_list, head) {
eld = &port->eld;
if (!eld->eld_valid)
continue;
if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
eld->eld_size > ELD_MAX_SIZE) {
mutex_unlock(&hdmi->pin_mutex);
dev_err(component->dev, "%s: buffer too small, device %d eld_size %d\n",
__func__, kcontrol->id.device, eld->eld_size);
snd_BUG();
return -EINVAL;
}
memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
eld->eld_size);
break;
}
mutex_unlock(&hdmi->pin_mutex);
return 0;
}
static int hdac_hdmi_create_eld_ctl(struct snd_soc_component *component, struct hdac_hdmi_pcm *pcm)
{
struct snd_kcontrol *kctl;
struct snd_kcontrol_new hdmi_eld_ctl = {
.access = SNDRV_CTL_ELEM_ACCESS_READ |
SNDRV_CTL_ELEM_ACCESS_VOLATILE,
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = "ELD",
.info = hdac_hdmi_eld_ctl_info,
.get = hdac_hdmi_eld_ctl_get,
.device = pcm->pcm_id,
};
/* add ELD ctl with the device number corresponding to the PCM stream */
kctl = snd_ctl_new1(&hdmi_eld_ctl, component);
if (!kctl)
return -ENOMEM;
pcm->eld_ctl = kctl;
return snd_ctl_add(component->card->snd_card, kctl);
}
static const struct snd_soc_dai_ops hdmi_dai_ops = {
.startup = hdac_hdmi_pcm_open,
.shutdown = hdac_hdmi_pcm_close,
.hw_params = hdac_hdmi_set_hw_params,
.set_stream = hdac_hdmi_set_stream,
};
/*
* Each converter can support a stream independently. So a dai is created
* based on the number of converter queried.
*/
static int hdac_hdmi_create_dais(struct hdac_device *hdev,
struct snd_soc_dai_driver **dais,
struct hdac_hdmi_priv *hdmi, int num_dais)
{
struct snd_soc_dai_driver *hdmi_dais;
struct hdac_hdmi_cvt *cvt;
char name[NAME_SIZE], dai_name[NAME_SIZE];
int i = 0;
u32 rates, bps;
unsigned int rate_max = 384000, rate_min = 8000;
u64 formats;
int ret;
hdmi_dais = devm_kzalloc(&hdev->dev,
(sizeof(*hdmi_dais) * num_dais),
GFP_KERNEL);
if (!hdmi_dais)
return -ENOMEM;
list_for_each_entry(cvt, &hdmi->cvt_list, head) {
ret = snd_hdac_query_supported_pcm(hdev, cvt->nid,
&rates, &formats, &bps);
if (ret)
return ret;
/* Filter out 44.1, 88.2 and 176.4Khz */
rates &= ~(SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |
SNDRV_PCM_RATE_176400);
if (!rates)
return -EINVAL;
sprintf(dai_name, "intel-hdmi-hifi%d", i+1);
hdmi_dais[i].name = devm_kstrdup(&hdev->dev,
dai_name, GFP_KERNEL);
if (!hdmi_dais[i].name)
return -ENOMEM;
snprintf(name, sizeof(name), "hifi%d", i+1);
hdmi_dais[i].playback.stream_name =
devm_kstrdup(&hdev->dev, name, GFP_KERNEL);
if (!hdmi_dais[i].playback.stream_name)
return -ENOMEM;
/*
* Set caps based on capability queried from the converter.
* It will be constrained runtime based on ELD queried.
*/
hdmi_dais[i].playback.formats = formats;
hdmi_dais[i].playback.rates = rates;
hdmi_dais[i].playback.rate_max = rate_max;
hdmi_dais[i].playback.rate_min = rate_min;
hdmi_dais[i].playback.channels_min = 2;
hdmi_dais[i].playback.channels_max = 2;
hdmi_dais[i].playback.sig_bits = bps;
hdmi_dais[i].ops = &hdmi_dai_ops;
i++;
}
*dais = hdmi_dais;
hdmi->dai_drv = hdmi_dais;
return 0;
}
/*
* Parse all nodes and store the cvt/pin nids in array
* Add one time initialization for pin and cvt widgets
*/
static int hdac_hdmi_parse_and_map_nid(struct hdac_device *hdev,
struct snd_soc_dai_driver **dais, int *num_dais)
{
hda_nid_t nid;
int i, num_nodes;
struct hdac_hdmi_priv *hdmi = hdev_to_hdmi_priv(hdev);
int ret;
hdac_hdmi_skl_enable_all_pins(hdev);
hdac_hdmi_skl_enable_dp12(hdev);
num_nodes = snd_hdac_get_sub_nodes(hdev, hdev->afg, &nid);
if (!nid || num_nodes <= 0) {
dev_warn(&hdev->dev, "HDMI: failed to get afg sub nodes\n");
return -EINVAL;
}
for (i = 0; i < num_nodes; i++, nid++) {
unsigned int caps;
unsigned int type;
caps = get_wcaps(hdev, nid);
type = get_wcaps_type(caps);
if (!(caps & AC_WCAP_DIGITAL))
continue;
switch (type) {
case AC_WID_AUD_OUT:
ret = hdac_hdmi_add_cvt(hdev, nid);
if (ret < 0)
return ret;
break;
case AC_WID_PIN:
ret = hdac_hdmi_add_pin(hdev, nid);
if (ret < 0)
return ret;
break;
}
}
if (!hdmi->num_pin || !hdmi->num_cvt) {
ret = -EIO;
dev_err(&hdev->dev, "Bad pin/cvt setup in %s\n", __func__);
return ret;
}
ret = hdac_hdmi_create_dais(hdev, dais, hdmi, hdmi->num_cvt);
if (ret) {
dev_err(&hdev->dev, "Failed to create dais with err: %d\n",
ret);
return ret;
}
*num_dais = hdmi->num_cvt;
ret = hdac_hdmi_init_dai_map(hdev);
if (ret < 0)
dev_err(&hdev->dev, "Failed to init DAI map with err: %d\n",
ret);
return ret;
}
static int hdac_hdmi_pin2port(void *aptr, int pin)
{
return pin - 4; /* map NID 0x05 -> port #1 */
}
static void hdac_hdmi_eld_notify_cb(void *aptr, int port, int pipe)
{
struct hdac_device *hdev = aptr;
struct hdac_hdmi_priv *hdmi = hdev_to_hdmi_priv(hdev);
struct hdac_hdmi_pin *pin;
struct hdac_hdmi_port *hport = NULL;
struct snd_soc_component *component = hdmi->component;
int i;
/* Don't know how this mapping is derived */
hda_nid_t pin_nid = port + 0x04;
dev_dbg(&hdev->dev, "%s: for pin:%d port=%d\n", __func__,
pin_nid, pipe);
/*
* skip notification during system suspend (but not in runtime PM);
* the state will be updated at resume. Also since the ELD and
* connection states are updated in anyway at the end of the resume,
* we can skip it when received during PM process.
*/
if (snd_power_get_state(component->card->snd_card) !=
SNDRV_CTL_POWER_D0)
return;
if (atomic_read(&hdev->in_pm))
return;
list_for_each_entry(pin, &hdmi->pin_list, head) {
if (pin->nid != pin_nid)
continue;
/* In case of non MST pin, pipe is -1 */
if (pipe == -1) {
pin->mst_capable = false;
/* if not MST, default is port[0] */
hport = &pin->ports[0];
} else {
for (i = 0; i < pin->num_ports; i++) {
pin->mst_capable = true;
if (pin->ports[i].id == pipe) {
hport = &pin->ports[i];
break;
}
}
}
if (hport)
hdac_hdmi_present_sense(pin, hport);
}
}
static struct drm_audio_component_audio_ops aops = {
.pin2port = hdac_hdmi_pin2port,
.pin_eld_notify = hdac_hdmi_eld_notify_cb,
};
static struct snd_pcm *hdac_hdmi_get_pcm_from_id(struct snd_soc_card *card,
int device)
{
struct snd_soc_pcm_runtime *rtd;
for_each_card_rtds(card, rtd) {
if (rtd->pcm && (rtd->pcm->device == device))
return rtd->pcm;
}
return NULL;
}
/* create jack pin kcontrols */
static int create_fill_jack_kcontrols(struct snd_soc_card *card,
struct hdac_device *hdev)
{
struct hdac_hdmi_pin *pin;
struct snd_kcontrol_new *kc;
char kc_name[NAME_SIZE], xname[NAME_SIZE];
char *name;
int i = 0, j;
struct hdac_hdmi_priv *hdmi = hdev_to_hdmi_priv(hdev);
struct snd_soc_component *component = hdmi->component;
kc = devm_kcalloc(component->dev, hdmi->num_ports,
sizeof(*kc), GFP_KERNEL);
if (!kc)
return -ENOMEM;
list_for_each_entry(pin, &hdmi->pin_list, head) {
for (j = 0; j < pin->num_ports; j++) {
snprintf(xname, sizeof(xname), "hif%d-%d Jack",
pin->nid, pin->ports[j].id);
name = devm_kstrdup(component->dev, xname, GFP_KERNEL);
if (!name)
return -ENOMEM;
snprintf(kc_name, sizeof(kc_name), "%s Switch", xname);
kc[i].name = devm_kstrdup(component->dev, kc_name,
GFP_KERNEL);
if (!kc[i].name)
return -ENOMEM;
kc[i].private_value = (unsigned long)name;
kc[i].iface = SNDRV_CTL_ELEM_IFACE_MIXER;
kc[i].access = 0;
kc[i].info = snd_soc_dapm_info_pin_switch;
kc[i].put = snd_soc_dapm_put_pin_switch;
kc[i].get = snd_soc_dapm_get_pin_switch;
i++;
}
}
return snd_soc_add_card_controls(card, kc, i);
}
int hdac_hdmi_jack_port_init(struct snd_soc_component *component,
struct snd_soc_dapm_context *dapm)
{
struct hdac_hdmi_priv *hdmi = snd_soc_component_get_drvdata(component);
struct hdac_device *hdev = hdmi->hdev;
struct hdac_hdmi_pin *pin;
struct snd_soc_dapm_widget *widgets;
struct snd_soc_dapm_route *route;
char w_name[NAME_SIZE];
int i = 0, j, ret;
widgets = devm_kcalloc(dapm->dev, hdmi->num_ports,
sizeof(*widgets), GFP_KERNEL);
if (!widgets)
return -ENOMEM;
route = devm_kcalloc(dapm->dev, hdmi->num_ports,
sizeof(*route), GFP_KERNEL);
if (!route)
return -ENOMEM;
/* create Jack DAPM widget */
list_for_each_entry(pin, &hdmi->pin_list, head) {
for (j = 0; j < pin->num_ports; j++) {
snprintf(w_name, sizeof(w_name), "hif%d-%d Jack",
pin->nid, pin->ports[j].id);
ret = hdac_hdmi_fill_widget_info(dapm->dev, &widgets[i],
snd_soc_dapm_spk, NULL,
w_name, NULL, NULL, 0, NULL, 0);
if (ret < 0)
return ret;
pin->ports[j].jack_pin = widgets[i].name;
pin->ports[j].dapm = dapm;
/* add to route from Jack widget to output */
hdac_hdmi_fill_route(&route[i], pin->ports[j].jack_pin,
NULL, pin->ports[j].output_pin, NULL);
i++;
}
}
/* Add Route from Jack widget to the output widget */
ret = snd_soc_dapm_new_controls(dapm, widgets, hdmi->num_ports);
if (ret < 0)
return ret;
ret = snd_soc_dapm_add_routes(dapm, route, hdmi->num_ports);
if (ret < 0)
return ret;
ret = snd_soc_dapm_new_widgets(dapm->card);
if (ret < 0)
return ret;
/* Add Jack Pin switch Kcontrol */
ret = create_fill_jack_kcontrols(dapm->card, hdev);
if (ret < 0)
return ret;
/* default set the Jack Pin switch to OFF */
list_for_each_entry(pin, &hdmi->pin_list, head) {
for (j = 0; j < pin->num_ports; j++)
snd_soc_dapm_disable_pin(pin->ports[j].dapm,
pin->ports[j].jack_pin);
}
return 0;
}
EXPORT_SYMBOL_GPL(hdac_hdmi_jack_port_init);
int hdac_hdmi_jack_init(struct snd_soc_dai *dai, int device,
struct snd_soc_jack *jack)
{
struct snd_soc_component *component = dai->component;
struct hdac_hdmi_priv *hdmi = snd_soc_component_get_drvdata(component);
struct hdac_device *hdev = hdmi->hdev;
struct hdac_hdmi_pcm *pcm;
struct snd_pcm *snd_pcm;
int err;
/*
* this is a new PCM device, create new pcm and
* add to the pcm list
*/
pcm = devm_kzalloc(&hdev->dev, sizeof(*pcm), GFP_KERNEL);
if (!pcm)
return -ENOMEM;
pcm->pcm_id = device;
pcm->cvt = hdmi->dai_map[dai->id].cvt;
pcm->jack_event = 0;
pcm->jack = jack;
mutex_init(&pcm->lock);
INIT_LIST_HEAD(&pcm->port_list);
snd_pcm = hdac_hdmi_get_pcm_from_id(dai->component->card, device);
if (snd_pcm) {
err = snd_hdac_add_chmap_ctls(snd_pcm, device, &hdmi->chmap);
if (err < 0) {
dev_err(&hdev->dev,
"chmap control add failed with err: %d for pcm: %d\n",
err, device);
return err;
}
}
/* add control for ELD Bytes */
err = hdac_hdmi_create_eld_ctl(component, pcm);
if (err < 0) {
dev_err(&hdev->dev,
"eld control add failed with err: %d for pcm: %d\n",
err, device);
return err;
}
list_add_tail(&pcm->head, &hdmi->pcm_list);
return 0;
}
EXPORT_SYMBOL_GPL(hdac_hdmi_jack_init);
static void hdac_hdmi_present_sense_all_pins(struct hdac_device *hdev,
struct hdac_hdmi_priv *hdmi, bool detect_pin_caps)
{
int i;
struct hdac_hdmi_pin *pin;
list_for_each_entry(pin, &hdmi->pin_list, head) {
if (detect_pin_caps) {
if (hdac_hdmi_get_port_len(hdev, pin->nid) == 0)
pin->mst_capable = false;
else
pin->mst_capable = true;
}
for (i = 0; i < pin->num_ports; i++) {
if (!pin->mst_capable && i > 0)
continue;
hdac_hdmi_present_sense(pin, &pin->ports[i]);
}
}
}
static int hdmi_codec_probe(struct snd_soc_component *component)
{
struct hdac_hdmi_priv *hdmi = snd_soc_component_get_drvdata(component);
struct hdac_device *hdev = hdmi->hdev;
struct snd_soc_dapm_context *dapm =
snd_soc_component_get_dapm(component);
struct hdac_ext_link *hlink;
int ret;
hdmi->component = component;
/*
* hold the ref while we probe, also no need to drop the ref on
* exit, we call pm_runtime_suspend() so that will do for us
*/
hlink = snd_hdac_ext_bus_get_hlink_by_name(hdev->bus, dev_name(&hdev->dev));
if (!hlink) {
dev_err(&hdev->dev, "hdac link not found\n");
return -EIO;
}
snd_hdac_ext_bus_link_get(hdev->bus, hlink);
ret = create_fill_widget_route_map(dapm);
if (ret < 0)
return ret;
aops.audio_ptr = hdev;
ret = snd_hdac_acomp_register_notifier(hdev->bus, &aops);
if (ret < 0) {
dev_err(&hdev->dev, "notifier register failed: err: %d\n", ret);
return ret;
}
hdac_hdmi_present_sense_all_pins(hdev, hdmi, true);
/* Imp: Store the card pointer in hda_codec */
hdmi->card = dapm->card->snd_card;
/*
* Setup a device_link between card device and HDMI codec device.
* The card device is the consumer and the HDMI codec device is
* the supplier. With this setting, we can make sure that the audio
* domain in display power will be always turned on before operating
* on the HDMI audio codec registers.
* Let's use the flag DL_FLAG_AUTOREMOVE_CONSUMER. This can make
* sure the device link is freed when the machine driver is removed.
*/
device_link_add(component->card->dev, &hdev->dev, DL_FLAG_RPM_ACTIVE |
DL_FLAG_AUTOREMOVE_CONSUMER);
/*
* hdac_device core already sets the state to active and calls
* get_noresume. So enable runtime and set the device to suspend.
*/
pm_runtime_enable(&hdev->dev);
pm_runtime_put(&hdev->dev);
pm_runtime_suspend(&hdev->dev);
return 0;
}
static void hdmi_codec_remove(struct snd_soc_component *component)
{
struct hdac_hdmi_priv *hdmi = snd_soc_component_get_drvdata(component);
struct hdac_device *hdev = hdmi->hdev;
int ret;
ret = snd_hdac_acomp_register_notifier(hdev->bus, NULL);
if (ret < 0)
dev_err(&hdev->dev, "notifier unregister failed: err: %d\n",
ret);
pm_runtime_disable(&hdev->dev);
}
#ifdef CONFIG_PM_SLEEP
static int hdmi_codec_resume(struct device *dev)
{
struct hdac_device *hdev = dev_to_hdac_dev(dev);
struct hdac_hdmi_priv *hdmi = hdev_to_hdmi_priv(hdev);
int ret;
ret = pm_runtime_force_resume(dev);
if (ret < 0)
return ret;
/*
* As the ELD notify callback request is not entertained while the
* device is in suspend state. Need to manually check detection of
* all pins here. pin capablity change is not support, so use the
* already set pin caps.
*
* NOTE: this is safe to call even if the codec doesn't actually resume.
* The pin check involves only with DRM audio component hooks, so it
* works even if the HD-audio side is still dreaming peacefully.
*/
hdac_hdmi_present_sense_all_pins(hdev, hdmi, false);
return 0;
}
#else
#define hdmi_codec_resume NULL
#endif
static const struct snd_soc_component_driver hdmi_hda_codec = {
.probe = hdmi_codec_probe,
.remove = hdmi_codec_remove,
.use_pmdown_time = 1,
.endianness = 1,
};
static void hdac_hdmi_get_chmap(struct hdac_device *hdev, int pcm_idx,
unsigned char *chmap)
{
struct hdac_hdmi_priv *hdmi = hdev_to_hdmi_priv(hdev);
struct hdac_hdmi_pcm *pcm = get_hdmi_pcm_from_id(hdmi, pcm_idx);
memcpy(chmap, pcm->chmap, ARRAY_SIZE(pcm->chmap));
}
static void hdac_hdmi_set_chmap(struct hdac_device *hdev, int pcm_idx,
unsigned char *chmap, int prepared)
{
struct hdac_hdmi_priv *hdmi = hdev_to_hdmi_priv(hdev);
struct hdac_hdmi_pcm *pcm = get_hdmi_pcm_from_id(hdmi, pcm_idx);
struct hdac_hdmi_port *port;
if (!pcm)
return;
if (list_empty(&pcm->port_list))
return;
mutex_lock(&pcm->lock);
pcm->chmap_set = true;
memcpy(pcm->chmap, chmap, ARRAY_SIZE(pcm->chmap));
list_for_each_entry(port, &pcm->port_list, head)
if (prepared)
hdac_hdmi_setup_audio_infoframe(hdev, pcm, port);
mutex_unlock(&pcm->lock);
}
static bool is_hdac_hdmi_pcm_attached(struct hdac_device *hdev, int pcm_idx)
{
struct hdac_hdmi_priv *hdmi = hdev_to_hdmi_priv(hdev);
struct hdac_hdmi_pcm *pcm = get_hdmi_pcm_from_id(hdmi, pcm_idx);
if (!pcm)
return false;
if (list_empty(&pcm->port_list))
return false;
return true;
}
static int hdac_hdmi_get_spk_alloc(struct hdac_device *hdev, int pcm_idx)
{
struct hdac_hdmi_priv *hdmi = hdev_to_hdmi_priv(hdev);
struct hdac_hdmi_pcm *pcm = get_hdmi_pcm_from_id(hdmi, pcm_idx);
struct hdac_hdmi_port *port;
if (!pcm)
return 0;
if (list_empty(&pcm->port_list))
return 0;
port = list_first_entry(&pcm->port_list, struct hdac_hdmi_port, head);
if (!port || !port->eld.eld_valid)
return 0;
return port->eld.info.spk_alloc;
}
static struct hdac_hdmi_drv_data intel_glk_drv_data = {
.vendor_nid = INTEL_GLK_VENDOR_NID,
};
static struct hdac_hdmi_drv_data intel_drv_data = {
.vendor_nid = INTEL_VENDOR_NID,
};
static int hdac_hdmi_dev_probe(struct hdac_device *hdev)
{
struct hdac_hdmi_priv *hdmi_priv;
struct snd_soc_dai_driver *hdmi_dais = NULL;
struct hdac_ext_link *hlink;
int num_dais = 0;
int ret;
struct hdac_driver *hdrv = drv_to_hdac_driver(hdev->dev.driver);
const struct hda_device_id *hdac_id = hdac_get_device_id(hdev, hdrv);
/* hold the ref while we probe */
hlink = snd_hdac_ext_bus_get_hlink_by_name(hdev->bus, dev_name(&hdev->dev));
if (!hlink) {
dev_err(&hdev->dev, "hdac link not found\n");
return -EIO;
}
snd_hdac_ext_bus_link_get(hdev->bus, hlink);
hdmi_priv = devm_kzalloc(&hdev->dev, sizeof(*hdmi_priv), GFP_KERNEL);
if (hdmi_priv == NULL)
return -ENOMEM;
snd_hdac_register_chmap_ops(hdev, &hdmi_priv->chmap);
hdmi_priv->chmap.ops.get_chmap = hdac_hdmi_get_chmap;
hdmi_priv->chmap.ops.set_chmap = hdac_hdmi_set_chmap;
hdmi_priv->chmap.ops.is_pcm_attached = is_hdac_hdmi_pcm_attached;
hdmi_priv->chmap.ops.get_spk_alloc = hdac_hdmi_get_spk_alloc;
hdmi_priv->hdev = hdev;
if (!hdac_id)
return -ENODEV;
if (hdac_id->driver_data)
hdmi_priv->drv_data =
(struct hdac_hdmi_drv_data *)hdac_id->driver_data;
else
hdmi_priv->drv_data = &intel_drv_data;
dev_set_drvdata(&hdev->dev, hdmi_priv);
INIT_LIST_HEAD(&hdmi_priv->pin_list);
INIT_LIST_HEAD(&hdmi_priv->cvt_list);
INIT_LIST_HEAD(&hdmi_priv->pcm_list);
mutex_init(&hdmi_priv->pin_mutex);
/*
* Turned off in the runtime_suspend during the first explicit
* pm_runtime_suspend call.
*/
snd_hdac_display_power(hdev->bus, hdev->addr, true);
ret = hdac_hdmi_parse_and_map_nid(hdev, &hdmi_dais, &num_dais);
if (ret < 0) {
dev_err(&hdev->dev,
"Failed in parse and map nid with err: %d\n", ret);
return ret;
}
snd_hdac_refresh_widgets(hdev);
/* ASoC specific initialization */
ret = devm_snd_soc_register_component(&hdev->dev, &hdmi_hda_codec,
hdmi_dais, num_dais);
snd_hdac_ext_bus_link_put(hdev->bus, hlink);
return ret;
}
static void clear_dapm_works(struct hdac_device *hdev)
{
struct hdac_hdmi_priv *hdmi = hdev_to_hdmi_priv(hdev);
struct hdac_hdmi_pin *pin;
int i;
list_for_each_entry(pin, &hdmi->pin_list, head)
for (i = 0; i < pin->num_ports; i++)
cancel_work_sync(&pin->ports[i].dapm_work);
}
static int hdac_hdmi_dev_remove(struct hdac_device *hdev)
{
clear_dapm_works(hdev);
snd_hdac_display_power(hdev->bus, hdev->addr, false);
return 0;
}
#ifdef CONFIG_PM
static int hdac_hdmi_runtime_suspend(struct device *dev)
{
struct hdac_device *hdev = dev_to_hdac_dev(dev);
struct hdac_bus *bus = hdev->bus;
struct hdac_ext_link *hlink;
dev_dbg(dev, "Enter: %s\n", __func__);
/* controller may not have been initialized for the first time */
if (!bus)
return 0;
/*
* Power down afg.
* codec_read is preferred over codec_write to set the power state.
* This way verb is send to set the power state and response
* is received. So setting power state is ensured without using loop
* to read the state.
*/
snd_hdac_codec_read(hdev, hdev->afg, 0, AC_VERB_SET_POWER_STATE,
AC_PWRST_D3);
hlink = snd_hdac_ext_bus_get_hlink_by_name(bus, dev_name(dev));
if (!hlink) {
dev_err(dev, "hdac link not found\n");
return -EIO;
}
snd_hdac_codec_link_down(hdev);
snd_hdac_ext_bus_link_put(bus, hlink);
snd_hdac_display_power(bus, hdev->addr, false);
return 0;
}
static int hdac_hdmi_runtime_resume(struct device *dev)
{
struct hdac_device *hdev = dev_to_hdac_dev(dev);
struct hdac_bus *bus = hdev->bus;
struct hdac_ext_link *hlink;
dev_dbg(dev, "Enter: %s\n", __func__);
/* controller may not have been initialized for the first time */
if (!bus)
return 0;
hlink = snd_hdac_ext_bus_get_hlink_by_name(bus, dev_name(dev));
if (!hlink) {
dev_err(dev, "hdac link not found\n");
return -EIO;
}
snd_hdac_ext_bus_link_get(bus, hlink);
snd_hdac_codec_link_up(hdev);
snd_hdac_display_power(bus, hdev->addr, true);
hdac_hdmi_skl_enable_all_pins(hdev);
hdac_hdmi_skl_enable_dp12(hdev);
/* Power up afg */
snd_hdac_codec_read(hdev, hdev->afg, 0, AC_VERB_SET_POWER_STATE,
AC_PWRST_D0);
return 0;
}
#else
#define hdac_hdmi_runtime_suspend NULL
#define hdac_hdmi_runtime_resume NULL
#endif
static const struct dev_pm_ops hdac_hdmi_pm = {
SET_RUNTIME_PM_OPS(hdac_hdmi_runtime_suspend, hdac_hdmi_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, hdmi_codec_resume)
};
static const struct hda_device_id hdmi_list[] = {
HDA_CODEC_EXT_ENTRY(0x80862809, 0x100000, "Skylake HDMI", 0),
HDA_CODEC_EXT_ENTRY(0x8086280a, 0x100000, "Broxton HDMI", 0),
HDA_CODEC_EXT_ENTRY(0x8086280b, 0x100000, "Kabylake HDMI", 0),
HDA_CODEC_EXT_ENTRY(0x8086280c, 0x100000, "Cannonlake HDMI",
&intel_glk_drv_data),
HDA_CODEC_EXT_ENTRY(0x8086280d, 0x100000, "Geminilake HDMI",
&intel_glk_drv_data),
{}
};
MODULE_DEVICE_TABLE(hdaudio, hdmi_list);
static struct hdac_driver hdmi_driver = {
.driver = {
.name = "HDMI HDA Codec",
.pm = &hdac_hdmi_pm,
},
.id_table = hdmi_list,
.probe = hdac_hdmi_dev_probe,
.remove = hdac_hdmi_dev_remove,
};
static int __init hdmi_init(void)
{
return snd_hda_ext_driver_register(&hdmi_driver);
}
static void __exit hdmi_exit(void)
{
snd_hda_ext_driver_unregister(&hdmi_driver);
}
module_init(hdmi_init);
module_exit(hdmi_exit);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("HDMI HD codec");
MODULE_AUTHOR("Samreen Nilofer<[email protected]>");
MODULE_AUTHOR("Subhransu S. Prusty<[email protected]>");
| linux-master | sound/soc/codecs/hdac_hdmi.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* AD193X Audio Codec driver supporting AD1936/7/8/9
*
* Copyright 2010 Analog Devices Inc.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include "ad193x.h"
/* codec private data */
struct ad193x_priv {
struct regmap *regmap;
enum ad193x_type type;
int sysclk;
};
/*
* AD193X volume/mute/de-emphasis etc. controls
*/
static const char * const ad193x_deemp[] = {"None", "48kHz", "44.1kHz", "32kHz"};
static SOC_ENUM_SINGLE_DECL(ad193x_deemp_enum, AD193X_DAC_CTRL2, 1,
ad193x_deemp);
static const DECLARE_TLV_DB_MINMAX(adau193x_tlv, -9563, 0);
static const unsigned int ad193x_sb[] = {32};
static struct snd_pcm_hw_constraint_list constr = {
.list = ad193x_sb,
.count = ARRAY_SIZE(ad193x_sb),
};
static const struct snd_kcontrol_new ad193x_snd_controls[] = {
/* DAC volume control */
SOC_DOUBLE_R_TLV("DAC1 Volume", AD193X_DAC_L1_VOL,
AD193X_DAC_R1_VOL, 0, 0xFF, 1, adau193x_tlv),
SOC_DOUBLE_R_TLV("DAC2 Volume", AD193X_DAC_L2_VOL,
AD193X_DAC_R2_VOL, 0, 0xFF, 1, adau193x_tlv),
SOC_DOUBLE_R_TLV("DAC3 Volume", AD193X_DAC_L3_VOL,
AD193X_DAC_R3_VOL, 0, 0xFF, 1, adau193x_tlv),
SOC_DOUBLE_R_TLV("DAC4 Volume", AD193X_DAC_L4_VOL,
AD193X_DAC_R4_VOL, 0, 0xFF, 1, adau193x_tlv),
/* DAC switch control */
SOC_DOUBLE("DAC1 Switch", AD193X_DAC_CHNL_MUTE, AD193X_DACL1_MUTE,
AD193X_DACR1_MUTE, 1, 1),
SOC_DOUBLE("DAC2 Switch", AD193X_DAC_CHNL_MUTE, AD193X_DACL2_MUTE,
AD193X_DACR2_MUTE, 1, 1),
SOC_DOUBLE("DAC3 Switch", AD193X_DAC_CHNL_MUTE, AD193X_DACL3_MUTE,
AD193X_DACR3_MUTE, 1, 1),
SOC_DOUBLE("DAC4 Switch", AD193X_DAC_CHNL_MUTE, AD193X_DACL4_MUTE,
AD193X_DACR4_MUTE, 1, 1),
/* DAC de-emphasis */
SOC_ENUM("Playback Deemphasis", ad193x_deemp_enum),
};
static const struct snd_kcontrol_new ad193x_adc_snd_controls[] = {
/* ADC switch control */
SOC_DOUBLE("ADC1 Switch", AD193X_ADC_CTRL0, AD193X_ADCL1_MUTE,
AD193X_ADCR1_MUTE, 1, 1),
SOC_DOUBLE("ADC2 Switch", AD193X_ADC_CTRL0, AD193X_ADCL2_MUTE,
AD193X_ADCR2_MUTE, 1, 1),
/* ADC high-pass filter */
SOC_SINGLE("ADC High Pass Filter Switch", AD193X_ADC_CTRL0,
AD193X_ADC_HIGHPASS_FILTER, 1, 0),
};
static const struct snd_soc_dapm_widget ad193x_dapm_widgets[] = {
SND_SOC_DAPM_DAC("DAC", "Playback", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_PGA("DAC Output", AD193X_DAC_CTRL0, 0, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("PLL_PWR", AD193X_PLL_CLK_CTRL0, 0, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("SYSCLK", AD193X_PLL_CLK_CTRL0, 7, 0, NULL, 0),
SND_SOC_DAPM_VMID("VMID"),
SND_SOC_DAPM_OUTPUT("DAC1OUT"),
SND_SOC_DAPM_OUTPUT("DAC2OUT"),
SND_SOC_DAPM_OUTPUT("DAC3OUT"),
SND_SOC_DAPM_OUTPUT("DAC4OUT"),
};
static const struct snd_soc_dapm_widget ad193x_adc_widgets[] = {
SND_SOC_DAPM_ADC("ADC", "Capture", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SUPPLY("ADC_PWR", AD193X_ADC_CTRL0, 0, 1, NULL, 0),
SND_SOC_DAPM_INPUT("ADC1IN"),
SND_SOC_DAPM_INPUT("ADC2IN"),
};
static int ad193x_check_pll(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
struct ad193x_priv *ad193x = snd_soc_component_get_drvdata(component);
return !!ad193x->sysclk;
}
static const struct snd_soc_dapm_route audio_paths[] = {
{ "DAC", NULL, "SYSCLK" },
{ "DAC Output", NULL, "DAC" },
{ "DAC Output", NULL, "VMID" },
{ "DAC1OUT", NULL, "DAC Output" },
{ "DAC2OUT", NULL, "DAC Output" },
{ "DAC3OUT", NULL, "DAC Output" },
{ "DAC4OUT", NULL, "DAC Output" },
{ "SYSCLK", NULL, "PLL_PWR", &ad193x_check_pll },
};
static const struct snd_soc_dapm_route ad193x_adc_audio_paths[] = {
{ "ADC", NULL, "SYSCLK" },
{ "ADC", NULL, "ADC_PWR" },
{ "ADC", NULL, "ADC1IN" },
{ "ADC", NULL, "ADC2IN" },
};
static inline bool ad193x_has_adc(const struct ad193x_priv *ad193x)
{
switch (ad193x->type) {
case AD1933:
case AD1934:
return false;
default:
break;
}
return true;
}
/*
* DAI ops entries
*/
static int ad193x_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct ad193x_priv *ad193x = snd_soc_component_get_drvdata(dai->component);
if (mute)
regmap_update_bits(ad193x->regmap, AD193X_DAC_CTRL2,
AD193X_DAC_MASTER_MUTE,
AD193X_DAC_MASTER_MUTE);
else
regmap_update_bits(ad193x->regmap, AD193X_DAC_CTRL2,
AD193X_DAC_MASTER_MUTE, 0);
return 0;
}
static int ad193x_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int width)
{
struct ad193x_priv *ad193x = snd_soc_component_get_drvdata(dai->component);
unsigned int channels;
switch (slots) {
case 2:
channels = AD193X_2_CHANNELS;
break;
case 4:
channels = AD193X_4_CHANNELS;
break;
case 8:
channels = AD193X_8_CHANNELS;
break;
case 16:
channels = AD193X_16_CHANNELS;
break;
default:
return -EINVAL;
}
regmap_update_bits(ad193x->regmap, AD193X_DAC_CTRL1,
AD193X_DAC_CHAN_MASK, channels << AD193X_DAC_CHAN_SHFT);
if (ad193x_has_adc(ad193x))
regmap_update_bits(ad193x->regmap, AD193X_ADC_CTRL2,
AD193X_ADC_CHAN_MASK,
channels << AD193X_ADC_CHAN_SHFT);
return 0;
}
static int ad193x_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct ad193x_priv *ad193x = snd_soc_component_get_drvdata(codec_dai->component);
unsigned int adc_serfmt = 0;
unsigned int dac_serfmt = 0;
unsigned int adc_fmt = 0;
unsigned int dac_fmt = 0;
/* At present, the driver only support AUX ADC mode(SND_SOC_DAIFMT_I2S
* with TDM), ADC&DAC TDM mode(SND_SOC_DAIFMT_DSP_A) and DAC I2S mode
* (SND_SOC_DAIFMT_I2S)
*/
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
adc_serfmt |= AD193X_ADC_SERFMT_TDM;
dac_serfmt |= AD193X_DAC_SERFMT_STEREO;
break;
case SND_SOC_DAIFMT_DSP_A:
adc_serfmt |= AD193X_ADC_SERFMT_AUX;
dac_serfmt |= AD193X_DAC_SERFMT_TDM;
break;
default:
if (ad193x_has_adc(ad193x))
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF: /* normal bit clock + frame */
break;
case SND_SOC_DAIFMT_NB_IF: /* normal bclk + invert frm */
adc_fmt |= AD193X_ADC_LEFT_HIGH;
dac_fmt |= AD193X_DAC_LEFT_HIGH;
break;
case SND_SOC_DAIFMT_IB_NF: /* invert bclk + normal frm */
adc_fmt |= AD193X_ADC_BCLK_INV;
dac_fmt |= AD193X_DAC_BCLK_INV;
break;
case SND_SOC_DAIFMT_IB_IF: /* invert bclk + frm */
adc_fmt |= AD193X_ADC_LEFT_HIGH;
adc_fmt |= AD193X_ADC_BCLK_INV;
dac_fmt |= AD193X_DAC_LEFT_HIGH;
dac_fmt |= AD193X_DAC_BCLK_INV;
break;
default:
return -EINVAL;
}
/* For DSP_*, LRCLK's polarity must be inverted */
if (fmt & SND_SOC_DAIFMT_DSP_A)
dac_fmt ^= AD193X_DAC_LEFT_HIGH;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
adc_fmt |= AD193X_ADC_LCR_MASTER;
adc_fmt |= AD193X_ADC_BCLK_MASTER;
dac_fmt |= AD193X_DAC_LCR_MASTER;
dac_fmt |= AD193X_DAC_BCLK_MASTER;
break;
case SND_SOC_DAIFMT_CBC_CFP:
adc_fmt |= AD193X_ADC_LCR_MASTER;
dac_fmt |= AD193X_DAC_LCR_MASTER;
break;
case SND_SOC_DAIFMT_CBP_CFC:
adc_fmt |= AD193X_ADC_BCLK_MASTER;
dac_fmt |= AD193X_DAC_BCLK_MASTER;
break;
case SND_SOC_DAIFMT_CBC_CFC:
break;
default:
return -EINVAL;
}
if (ad193x_has_adc(ad193x)) {
regmap_update_bits(ad193x->regmap, AD193X_ADC_CTRL1,
AD193X_ADC_SERFMT_MASK, adc_serfmt);
regmap_update_bits(ad193x->regmap, AD193X_ADC_CTRL2,
AD193X_ADC_FMT_MASK, adc_fmt);
}
regmap_update_bits(ad193x->regmap, AD193X_DAC_CTRL0,
AD193X_DAC_SERFMT_MASK, dac_serfmt);
regmap_update_bits(ad193x->regmap, AD193X_DAC_CTRL1,
AD193X_DAC_FMT_MASK, dac_fmt);
return 0;
}
static int ad193x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct ad193x_priv *ad193x = snd_soc_component_get_drvdata(component);
if (clk_id == AD193X_SYSCLK_MCLK) {
/* MCLK must be 512 x fs */
if (dir == SND_SOC_CLOCK_OUT || freq != 24576000)
return -EINVAL;
regmap_update_bits(ad193x->regmap, AD193X_PLL_CLK_CTRL1,
AD193X_PLL_SRC_MASK,
AD193X_PLL_DAC_SRC_MCLK |
AD193X_PLL_CLK_SRC_MCLK);
snd_soc_dapm_sync(dapm);
return 0;
}
switch (freq) {
case 12288000:
case 18432000:
case 24576000:
case 36864000:
ad193x->sysclk = freq;
return 0;
}
return -EINVAL;
}
static int ad193x_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
int word_len = 0, master_rate = 0;
struct snd_soc_component *component = dai->component;
struct ad193x_priv *ad193x = snd_soc_component_get_drvdata(component);
bool is_playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
u8 dacc0;
dev_dbg(dai->dev, "%s() rate=%u format=%#x width=%u channels=%u\n",
__func__, params_rate(params), params_format(params),
params_width(params), params_channels(params));
/* bit size */
switch (params_width(params)) {
case 16:
word_len = 3;
break;
case 20:
word_len = 1;
break;
case 24:
case 32:
word_len = 0;
break;
}
switch (ad193x->sysclk) {
case 12288000:
master_rate = AD193X_PLL_INPUT_256;
break;
case 18432000:
master_rate = AD193X_PLL_INPUT_384;
break;
case 24576000:
master_rate = AD193X_PLL_INPUT_512;
break;
case 36864000:
master_rate = AD193X_PLL_INPUT_768;
break;
}
if (is_playback) {
switch (params_rate(params)) {
case 48000:
dacc0 = AD193X_DAC_SR_48;
break;
case 96000:
dacc0 = AD193X_DAC_SR_96;
break;
case 192000:
dacc0 = AD193X_DAC_SR_192;
break;
default:
dev_err(dai->dev, "invalid sampling rate: %d\n", params_rate(params));
return -EINVAL;
}
regmap_update_bits(ad193x->regmap, AD193X_DAC_CTRL0, AD193X_DAC_SR_MASK, dacc0);
}
regmap_update_bits(ad193x->regmap, AD193X_PLL_CLK_CTRL0,
AD193X_PLL_INPUT_MASK, master_rate);
regmap_update_bits(ad193x->regmap, AD193X_DAC_CTRL2,
AD193X_DAC_WORD_LEN_MASK,
word_len << AD193X_DAC_WORD_LEN_SHFT);
if (ad193x_has_adc(ad193x))
regmap_update_bits(ad193x->regmap, AD193X_ADC_CTRL1,
AD193X_ADC_WORD_LEN_MASK, word_len);
return 0;
}
static int ad193x_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
return snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
&constr);
}
static const struct snd_soc_dai_ops ad193x_dai_ops = {
.startup = ad193x_startup,
.hw_params = ad193x_hw_params,
.mute_stream = ad193x_mute,
.set_tdm_slot = ad193x_set_tdm_slot,
.set_sysclk = ad193x_set_dai_sysclk,
.set_fmt = ad193x_set_dai_fmt,
.no_capture_mute = 1,
};
/* codec DAI instance */
static struct snd_soc_dai_driver ad193x_dai = {
.name = "ad193x-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 4,
.rates = SNDRV_PCM_RATE_48000,
.formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE,
},
.ops = &ad193x_dai_ops,
};
/* codec DAI instance for DAC only */
static struct snd_soc_dai_driver ad193x_no_adc_dai = {
.name = "ad193x-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE,
},
.ops = &ad193x_dai_ops,
};
/* codec register values to set after reset */
static void ad193x_reg_default_init(struct ad193x_priv *ad193x)
{
static const struct reg_sequence reg_init[] = {
{ 0, 0x99 }, /* PLL_CLK_CTRL0: pll input: mclki/xi 12.288Mhz */
{ 1, 0x04 }, /* PLL_CLK_CTRL1: no on-chip Vref */
{ 2, 0x40 }, /* DAC_CTRL0: TDM mode */
{ 3, 0x00 }, /* DAC_CTRL1: reset */
{ 4, 0x1A }, /* DAC_CTRL2: 48kHz de-emphasis, unmute dac */
{ 5, 0x00 }, /* DAC_CHNL_MUTE: unmute DAC channels */
{ 6, 0x00 }, /* DAC_L1_VOL: no attenuation */
{ 7, 0x00 }, /* DAC_R1_VOL: no attenuation */
{ 8, 0x00 }, /* DAC_L2_VOL: no attenuation */
{ 9, 0x00 }, /* DAC_R2_VOL: no attenuation */
{ 10, 0x00 }, /* DAC_L3_VOL: no attenuation */
{ 11, 0x00 }, /* DAC_R3_VOL: no attenuation */
{ 12, 0x00 }, /* DAC_L4_VOL: no attenuation */
{ 13, 0x00 }, /* DAC_R4_VOL: no attenuation */
};
static const struct reg_sequence reg_adc_init[] = {
{ 14, 0x03 }, /* ADC_CTRL0: high-pass filter enable */
{ 15, 0x43 }, /* ADC_CTRL1: sata delay=1, adc aux mode */
{ 16, 0x00 }, /* ADC_CTRL2: reset */
};
regmap_multi_reg_write(ad193x->regmap, reg_init, ARRAY_SIZE(reg_init));
if (ad193x_has_adc(ad193x)) {
regmap_multi_reg_write(ad193x->regmap, reg_adc_init,
ARRAY_SIZE(reg_adc_init));
}
}
static int ad193x_component_probe(struct snd_soc_component *component)
{
struct ad193x_priv *ad193x = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
int num, ret;
/* default setting for ad193x */
ad193x_reg_default_init(ad193x);
/* adc only */
if (ad193x_has_adc(ad193x)) {
/* add adc controls */
num = ARRAY_SIZE(ad193x_adc_snd_controls);
ret = snd_soc_add_component_controls(component,
ad193x_adc_snd_controls,
num);
if (ret)
return ret;
/* add adc widgets */
num = ARRAY_SIZE(ad193x_adc_widgets);
ret = snd_soc_dapm_new_controls(dapm,
ad193x_adc_widgets,
num);
if (ret)
return ret;
/* add adc routes */
num = ARRAY_SIZE(ad193x_adc_audio_paths);
ret = snd_soc_dapm_add_routes(dapm,
ad193x_adc_audio_paths,
num);
if (ret)
return ret;
}
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_ad193x = {
.probe = ad193x_component_probe,
.controls = ad193x_snd_controls,
.num_controls = ARRAY_SIZE(ad193x_snd_controls),
.dapm_widgets = ad193x_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(ad193x_dapm_widgets),
.dapm_routes = audio_paths,
.num_dapm_routes = ARRAY_SIZE(audio_paths),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
const struct regmap_config ad193x_regmap_config = {
.max_register = AD193X_NUM_REGS - 1,
};
EXPORT_SYMBOL_GPL(ad193x_regmap_config);
int ad193x_probe(struct device *dev, struct regmap *regmap,
enum ad193x_type type)
{
struct ad193x_priv *ad193x;
if (IS_ERR(regmap))
return PTR_ERR(regmap);
ad193x = devm_kzalloc(dev, sizeof(*ad193x), GFP_KERNEL);
if (ad193x == NULL)
return -ENOMEM;
ad193x->regmap = regmap;
ad193x->type = type;
dev_set_drvdata(dev, ad193x);
if (ad193x_has_adc(ad193x))
return devm_snd_soc_register_component(dev, &soc_component_dev_ad193x,
&ad193x_dai, 1);
return devm_snd_soc_register_component(dev, &soc_component_dev_ad193x,
&ad193x_no_adc_dai, 1);
}
EXPORT_SYMBOL_GPL(ad193x_probe);
MODULE_DESCRIPTION("ASoC ad193x driver");
MODULE_AUTHOR("Barry Song <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/ad193x.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2021, Linaro Limited
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/component.h>
#include <linux/pm_runtime.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/soundwire/sdw.h>
#include <linux/soundwire/sdw_type.h>
#include <linux/soundwire/sdw_registers.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include "wcd938x.h"
#define SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(m) (0xE0 + 0x10 * (m))
static struct wcd938x_sdw_ch_info wcd938x_sdw_rx_ch_info[] = {
WCD_SDW_CH(WCD938X_HPH_L, WCD938X_HPH_PORT, BIT(0)),
WCD_SDW_CH(WCD938X_HPH_R, WCD938X_HPH_PORT, BIT(1)),
WCD_SDW_CH(WCD938X_CLSH, WCD938X_CLSH_PORT, BIT(0)),
WCD_SDW_CH(WCD938X_COMP_L, WCD938X_COMP_PORT, BIT(0)),
WCD_SDW_CH(WCD938X_COMP_R, WCD938X_COMP_PORT, BIT(1)),
WCD_SDW_CH(WCD938X_LO, WCD938X_LO_PORT, BIT(0)),
WCD_SDW_CH(WCD938X_DSD_L, WCD938X_DSD_PORT, BIT(0)),
WCD_SDW_CH(WCD938X_DSD_R, WCD938X_DSD_PORT, BIT(1)),
};
static struct wcd938x_sdw_ch_info wcd938x_sdw_tx_ch_info[] = {
WCD_SDW_CH(WCD938X_ADC1, WCD938X_ADC_1_2_PORT, BIT(0)),
WCD_SDW_CH(WCD938X_ADC2, WCD938X_ADC_1_2_PORT, BIT(1)),
WCD_SDW_CH(WCD938X_ADC3, WCD938X_ADC_3_4_PORT, BIT(0)),
WCD_SDW_CH(WCD938X_ADC4, WCD938X_ADC_3_4_PORT, BIT(1)),
WCD_SDW_CH(WCD938X_DMIC0, WCD938X_DMIC_0_3_MBHC_PORT, BIT(0)),
WCD_SDW_CH(WCD938X_DMIC1, WCD938X_DMIC_0_3_MBHC_PORT, BIT(1)),
WCD_SDW_CH(WCD938X_MBHC, WCD938X_DMIC_0_3_MBHC_PORT, BIT(2)),
WCD_SDW_CH(WCD938X_DMIC2, WCD938X_DMIC_0_3_MBHC_PORT, BIT(2)),
WCD_SDW_CH(WCD938X_DMIC3, WCD938X_DMIC_0_3_MBHC_PORT, BIT(3)),
WCD_SDW_CH(WCD938X_DMIC4, WCD938X_DMIC_4_7_PORT, BIT(0)),
WCD_SDW_CH(WCD938X_DMIC5, WCD938X_DMIC_4_7_PORT, BIT(1)),
WCD_SDW_CH(WCD938X_DMIC6, WCD938X_DMIC_4_7_PORT, BIT(2)),
WCD_SDW_CH(WCD938X_DMIC7, WCD938X_DMIC_4_7_PORT, BIT(3)),
};
static struct sdw_dpn_prop wcd938x_dpn_prop[WCD938X_MAX_SWR_PORTS] = {
{
.num = 1,
.type = SDW_DPN_SIMPLE,
.min_ch = 1,
.max_ch = 8,
.simple_ch_prep_sm = true,
}, {
.num = 2,
.type = SDW_DPN_SIMPLE,
.min_ch = 1,
.max_ch = 4,
.simple_ch_prep_sm = true,
}, {
.num = 3,
.type = SDW_DPN_SIMPLE,
.min_ch = 1,
.max_ch = 4,
.simple_ch_prep_sm = true,
}, {
.num = 4,
.type = SDW_DPN_SIMPLE,
.min_ch = 1,
.max_ch = 4,
.simple_ch_prep_sm = true,
}, {
.num = 5,
.type = SDW_DPN_SIMPLE,
.min_ch = 1,
.max_ch = 4,
.simple_ch_prep_sm = true,
}
};
struct device *wcd938x_sdw_device_get(struct device_node *np)
{
return bus_find_device_by_of_node(&sdw_bus_type, np);
}
EXPORT_SYMBOL_GPL(wcd938x_sdw_device_get);
int wcd938x_swr_get_current_bank(struct sdw_slave *sdev)
{
int bank;
bank = sdw_read(sdev, SDW_SCP_CTRL);
return ((bank & 0x40) ? 1 : 0);
}
EXPORT_SYMBOL_GPL(wcd938x_swr_get_current_bank);
int wcd938x_sdw_hw_params(struct wcd938x_sdw_priv *wcd,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct sdw_port_config port_config[WCD938X_MAX_SWR_PORTS];
unsigned long ch_mask;
int i, j;
wcd->sconfig.ch_count = 1;
wcd->active_ports = 0;
for (i = 0; i < WCD938X_MAX_SWR_PORTS; i++) {
ch_mask = wcd->port_config[i].ch_mask;
if (!ch_mask)
continue;
for_each_set_bit(j, &ch_mask, 4)
wcd->sconfig.ch_count++;
port_config[wcd->active_ports] = wcd->port_config[i];
wcd->active_ports++;
}
wcd->sconfig.bps = 1;
wcd->sconfig.frame_rate = params_rate(params);
if (wcd->is_tx)
wcd->sconfig.direction = SDW_DATA_DIR_TX;
else
wcd->sconfig.direction = SDW_DATA_DIR_RX;
wcd->sconfig.type = SDW_STREAM_PCM;
return sdw_stream_add_slave(wcd->sdev, &wcd->sconfig,
&port_config[0], wcd->active_ports,
wcd->sruntime);
}
EXPORT_SYMBOL_GPL(wcd938x_sdw_hw_params);
int wcd938x_sdw_free(struct wcd938x_sdw_priv *wcd,
struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
sdw_stream_remove_slave(wcd->sdev, wcd->sruntime);
return 0;
}
EXPORT_SYMBOL_GPL(wcd938x_sdw_free);
int wcd938x_sdw_set_sdw_stream(struct wcd938x_sdw_priv *wcd,
struct snd_soc_dai *dai,
void *stream, int direction)
{
wcd->sruntime = stream;
return 0;
}
EXPORT_SYMBOL_GPL(wcd938x_sdw_set_sdw_stream);
static int wcd9380_update_status(struct sdw_slave *slave,
enum sdw_slave_status status)
{
struct wcd938x_sdw_priv *wcd = dev_get_drvdata(&slave->dev);
if (wcd->regmap && (status == SDW_SLAVE_ATTACHED)) {
/* Write out any cached changes that happened between probe and attach */
regcache_cache_only(wcd->regmap, false);
return regcache_sync(wcd->regmap);
}
return 0;
}
static int wcd9380_bus_config(struct sdw_slave *slave,
struct sdw_bus_params *params)
{
sdw_write(slave, SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(params->next_bank), 0x01);
return 0;
}
static int wcd9380_interrupt_callback(struct sdw_slave *slave,
struct sdw_slave_intr_status *status)
{
struct wcd938x_sdw_priv *wcd = dev_get_drvdata(&slave->dev);
struct irq_domain *slave_irq = wcd->slave_irq;
u32 sts1, sts2, sts3;
do {
handle_nested_irq(irq_find_mapping(slave_irq, 0));
regmap_read(wcd->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1);
regmap_read(wcd->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2);
regmap_read(wcd->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3);
} while (sts1 || sts2 || sts3);
return IRQ_HANDLED;
}
static const struct reg_default wcd938x_defaults[] = {
{WCD938X_ANA_PAGE_REGISTER, 0x00},
{WCD938X_ANA_BIAS, 0x00},
{WCD938X_ANA_RX_SUPPLIES, 0x00},
{WCD938X_ANA_HPH, 0x0C},
{WCD938X_ANA_EAR, 0x00},
{WCD938X_ANA_EAR_COMPANDER_CTL, 0x02},
{WCD938X_ANA_TX_CH1, 0x20},
{WCD938X_ANA_TX_CH2, 0x00},
{WCD938X_ANA_TX_CH3, 0x20},
{WCD938X_ANA_TX_CH4, 0x00},
{WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC, 0x00},
{WCD938X_ANA_MICB3_DSP_EN_LOGIC, 0x00},
{WCD938X_ANA_MBHC_MECH, 0x39},
{WCD938X_ANA_MBHC_ELECT, 0x08},
{WCD938X_ANA_MBHC_ZDET, 0x00},
{WCD938X_ANA_MBHC_RESULT_1, 0x00},
{WCD938X_ANA_MBHC_RESULT_2, 0x00},
{WCD938X_ANA_MBHC_RESULT_3, 0x00},
{WCD938X_ANA_MBHC_BTN0, 0x00},
{WCD938X_ANA_MBHC_BTN1, 0x10},
{WCD938X_ANA_MBHC_BTN2, 0x20},
{WCD938X_ANA_MBHC_BTN3, 0x30},
{WCD938X_ANA_MBHC_BTN4, 0x40},
{WCD938X_ANA_MBHC_BTN5, 0x50},
{WCD938X_ANA_MBHC_BTN6, 0x60},
{WCD938X_ANA_MBHC_BTN7, 0x70},
{WCD938X_ANA_MICB1, 0x10},
{WCD938X_ANA_MICB2, 0x10},
{WCD938X_ANA_MICB2_RAMP, 0x00},
{WCD938X_ANA_MICB3, 0x10},
{WCD938X_ANA_MICB4, 0x10},
{WCD938X_BIAS_CTL, 0x2A},
{WCD938X_BIAS_VBG_FINE_ADJ, 0x55},
{WCD938X_LDOL_VDDCX_ADJUST, 0x01},
{WCD938X_LDOL_DISABLE_LDOL, 0x00},
{WCD938X_MBHC_CTL_CLK, 0x00},
{WCD938X_MBHC_CTL_ANA, 0x00},
{WCD938X_MBHC_CTL_SPARE_1, 0x00},
{WCD938X_MBHC_CTL_SPARE_2, 0x00},
{WCD938X_MBHC_CTL_BCS, 0x00},
{WCD938X_MBHC_MOISTURE_DET_FSM_STATUS, 0x00},
{WCD938X_MBHC_TEST_CTL, 0x00},
{WCD938X_LDOH_MODE, 0x2B},
{WCD938X_LDOH_BIAS, 0x68},
{WCD938X_LDOH_STB_LOADS, 0x00},
{WCD938X_LDOH_SLOWRAMP, 0x50},
{WCD938X_MICB1_TEST_CTL_1, 0x1A},
{WCD938X_MICB1_TEST_CTL_2, 0x00},
{WCD938X_MICB1_TEST_CTL_3, 0xA4},
{WCD938X_MICB2_TEST_CTL_1, 0x1A},
{WCD938X_MICB2_TEST_CTL_2, 0x00},
{WCD938X_MICB2_TEST_CTL_3, 0x24},
{WCD938X_MICB3_TEST_CTL_1, 0x1A},
{WCD938X_MICB3_TEST_CTL_2, 0x00},
{WCD938X_MICB3_TEST_CTL_3, 0xA4},
{WCD938X_MICB4_TEST_CTL_1, 0x1A},
{WCD938X_MICB4_TEST_CTL_2, 0x00},
{WCD938X_MICB4_TEST_CTL_3, 0xA4},
{WCD938X_TX_COM_ADC_VCM, 0x39},
{WCD938X_TX_COM_BIAS_ATEST, 0xE0},
{WCD938X_TX_COM_SPARE1, 0x00},
{WCD938X_TX_COM_SPARE2, 0x00},
{WCD938X_TX_COM_TXFE_DIV_CTL, 0x22},
{WCD938X_TX_COM_TXFE_DIV_START, 0x00},
{WCD938X_TX_COM_SPARE3, 0x00},
{WCD938X_TX_COM_SPARE4, 0x00},
{WCD938X_TX_1_2_TEST_EN, 0xCC},
{WCD938X_TX_1_2_ADC_IB, 0xE9},
{WCD938X_TX_1_2_ATEST_REFCTL, 0x0A},
{WCD938X_TX_1_2_TEST_CTL, 0x38},
{WCD938X_TX_1_2_TEST_BLK_EN1, 0xFF},
{WCD938X_TX_1_2_TXFE1_CLKDIV, 0x00},
{WCD938X_TX_1_2_SAR2_ERR, 0x00},
{WCD938X_TX_1_2_SAR1_ERR, 0x00},
{WCD938X_TX_3_4_TEST_EN, 0xCC},
{WCD938X_TX_3_4_ADC_IB, 0xE9},
{WCD938X_TX_3_4_ATEST_REFCTL, 0x0A},
{WCD938X_TX_3_4_TEST_CTL, 0x38},
{WCD938X_TX_3_4_TEST_BLK_EN3, 0xFF},
{WCD938X_TX_3_4_TXFE3_CLKDIV, 0x00},
{WCD938X_TX_3_4_SAR4_ERR, 0x00},
{WCD938X_TX_3_4_SAR3_ERR, 0x00},
{WCD938X_TX_3_4_TEST_BLK_EN2, 0xFB},
{WCD938X_TX_3_4_TXFE2_CLKDIV, 0x00},
{WCD938X_TX_3_4_SPARE1, 0x00},
{WCD938X_TX_3_4_TEST_BLK_EN4, 0xFB},
{WCD938X_TX_3_4_TXFE4_CLKDIV, 0x00},
{WCD938X_TX_3_4_SPARE2, 0x00},
{WCD938X_CLASSH_MODE_1, 0x40},
{WCD938X_CLASSH_MODE_2, 0x3A},
{WCD938X_CLASSH_MODE_3, 0x00},
{WCD938X_CLASSH_CTRL_VCL_1, 0x70},
{WCD938X_CLASSH_CTRL_VCL_2, 0x82},
{WCD938X_CLASSH_CTRL_CCL_1, 0x31},
{WCD938X_CLASSH_CTRL_CCL_2, 0x80},
{WCD938X_CLASSH_CTRL_CCL_3, 0x80},
{WCD938X_CLASSH_CTRL_CCL_4, 0x51},
{WCD938X_CLASSH_CTRL_CCL_5, 0x00},
{WCD938X_CLASSH_BUCK_TMUX_A_D, 0x00},
{WCD938X_CLASSH_BUCK_SW_DRV_CNTL, 0x77},
{WCD938X_CLASSH_SPARE, 0x00},
{WCD938X_FLYBACK_EN, 0x4E},
{WCD938X_FLYBACK_VNEG_CTRL_1, 0x0B},
{WCD938X_FLYBACK_VNEG_CTRL_2, 0x45},
{WCD938X_FLYBACK_VNEG_CTRL_3, 0x74},
{WCD938X_FLYBACK_VNEG_CTRL_4, 0x7F},
{WCD938X_FLYBACK_VNEG_CTRL_5, 0x83},
{WCD938X_FLYBACK_VNEG_CTRL_6, 0x98},
{WCD938X_FLYBACK_VNEG_CTRL_7, 0xA9},
{WCD938X_FLYBACK_VNEG_CTRL_8, 0x68},
{WCD938X_FLYBACK_VNEG_CTRL_9, 0x64},
{WCD938X_FLYBACK_VNEGDAC_CTRL_1, 0xED},
{WCD938X_FLYBACK_VNEGDAC_CTRL_2, 0xF0},
{WCD938X_FLYBACK_VNEGDAC_CTRL_3, 0xA6},
{WCD938X_FLYBACK_CTRL_1, 0x65},
{WCD938X_FLYBACK_TEST_CTL, 0x00},
{WCD938X_RX_AUX_SW_CTL, 0x00},
{WCD938X_RX_PA_AUX_IN_CONN, 0x01},
{WCD938X_RX_TIMER_DIV, 0x32},
{WCD938X_RX_OCP_CTL, 0x1F},
{WCD938X_RX_OCP_COUNT, 0x77},
{WCD938X_RX_BIAS_EAR_DAC, 0xA0},
{WCD938X_RX_BIAS_EAR_AMP, 0xAA},
{WCD938X_RX_BIAS_HPH_LDO, 0xA9},
{WCD938X_RX_BIAS_HPH_PA, 0xAA},
{WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2, 0x8A},
{WCD938X_RX_BIAS_HPH_RDAC_LDO, 0x88},
{WCD938X_RX_BIAS_HPH_CNP1, 0x82},
{WCD938X_RX_BIAS_HPH_LOWPOWER, 0x82},
{WCD938X_RX_BIAS_AUX_DAC, 0xA0},
{WCD938X_RX_BIAS_AUX_AMP, 0xAA},
{WCD938X_RX_BIAS_VNEGDAC_BLEEDER, 0x50},
{WCD938X_RX_BIAS_MISC, 0x00},
{WCD938X_RX_BIAS_BUCK_RST, 0x08},
{WCD938X_RX_BIAS_BUCK_VREF_ERRAMP, 0x44},
{WCD938X_RX_BIAS_FLYB_ERRAMP, 0x40},
{WCD938X_RX_BIAS_FLYB_BUFF, 0xAA},
{WCD938X_RX_BIAS_FLYB_MID_RST, 0x14},
{WCD938X_HPH_L_STATUS, 0x04},
{WCD938X_HPH_R_STATUS, 0x04},
{WCD938X_HPH_CNP_EN, 0x80},
{WCD938X_HPH_CNP_WG_CTL, 0x9A},
{WCD938X_HPH_CNP_WG_TIME, 0x14},
{WCD938X_HPH_OCP_CTL, 0x28},
{WCD938X_HPH_AUTO_CHOP, 0x16},
{WCD938X_HPH_CHOP_CTL, 0x83},
{WCD938X_HPH_PA_CTL1, 0x46},
{WCD938X_HPH_PA_CTL2, 0x50},
{WCD938X_HPH_L_EN, 0x80},
{WCD938X_HPH_L_TEST, 0xE0},
{WCD938X_HPH_L_ATEST, 0x50},
{WCD938X_HPH_R_EN, 0x80},
{WCD938X_HPH_R_TEST, 0xE0},
{WCD938X_HPH_R_ATEST, 0x54},
{WCD938X_HPH_RDAC_CLK_CTL1, 0x99},
{WCD938X_HPH_RDAC_CLK_CTL2, 0x9B},
{WCD938X_HPH_RDAC_LDO_CTL, 0x33},
{WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL, 0x00},
{WCD938X_HPH_REFBUFF_UHQA_CTL, 0x68},
{WCD938X_HPH_REFBUFF_LP_CTL, 0x0E},
{WCD938X_HPH_L_DAC_CTL, 0x20},
{WCD938X_HPH_R_DAC_CTL, 0x20},
{WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL, 0x55},
{WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0x19},
{WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1, 0xA0},
{WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS, 0x00},
{WCD938X_EAR_EAR_EN_REG, 0x22},
{WCD938X_EAR_EAR_PA_CON, 0x44},
{WCD938X_EAR_EAR_SP_CON, 0xDB},
{WCD938X_EAR_EAR_DAC_CON, 0x80},
{WCD938X_EAR_EAR_CNP_FSM_CON, 0xB2},
{WCD938X_EAR_TEST_CTL, 0x00},
{WCD938X_EAR_STATUS_REG_1, 0x00},
{WCD938X_EAR_STATUS_REG_2, 0x08},
{WCD938X_ANA_NEW_PAGE_REGISTER, 0x00},
{WCD938X_HPH_NEW_ANA_HPH2, 0x00},
{WCD938X_HPH_NEW_ANA_HPH3, 0x00},
{WCD938X_SLEEP_CTL, 0x16},
{WCD938X_SLEEP_WATCHDOG_CTL, 0x00},
{WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL, 0x00},
{WCD938X_MBHC_NEW_CTL_1, 0x02},
{WCD938X_MBHC_NEW_CTL_2, 0x05},
{WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0xE9},
{WCD938X_MBHC_NEW_ZDET_ANA_CTL, 0x0F},
{WCD938X_MBHC_NEW_ZDET_RAMP_CTL, 0x00},
{WCD938X_MBHC_NEW_FSM_STATUS, 0x00},
{WCD938X_MBHC_NEW_ADC_RESULT, 0x00},
{WCD938X_TX_NEW_AMIC_MUX_CFG, 0x00},
{WCD938X_AUX_AUXPA, 0x00},
{WCD938X_LDORXTX_MODE, 0x0C},
{WCD938X_LDORXTX_CONFIG, 0x10},
{WCD938X_DIE_CRACK_DIE_CRK_DET_EN, 0x00},
{WCD938X_DIE_CRACK_DIE_CRK_DET_OUT, 0x00},
{WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL, 0x40},
{WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x81},
{WCD938X_HPH_NEW_INT_RDAC_VREF_CTL, 0x10},
{WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL, 0x00},
{WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x81},
{WCD938X_HPH_NEW_INT_PA_MISC1, 0x22},
{WCD938X_HPH_NEW_INT_PA_MISC2, 0x00},
{WCD938X_HPH_NEW_INT_PA_RDAC_MISC, 0x00},
{WCD938X_HPH_NEW_INT_HPH_TIMER1, 0xFE},
{WCD938X_HPH_NEW_INT_HPH_TIMER2, 0x02},
{WCD938X_HPH_NEW_INT_HPH_TIMER3, 0x4E},
{WCD938X_HPH_NEW_INT_HPH_TIMER4, 0x54},
{WCD938X_HPH_NEW_INT_PA_RDAC_MISC2, 0x00},
{WCD938X_HPH_NEW_INT_PA_RDAC_MISC3, 0x00},
{WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW, 0x90},
{WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW, 0x90},
{WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI, 0x62},
{WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP, 0x01},
{WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP, 0x11},
{WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL, 0x57},
{WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 0x01},
{WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x00},
{WCD938X_MBHC_NEW_INT_SPARE_2, 0x00},
{WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON, 0xA8},
{WCD938X_EAR_INT_NEW_CNP_VCM_CON1, 0x42},
{WCD938X_EAR_INT_NEW_CNP_VCM_CON2, 0x22},
{WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS, 0x00},
{WCD938X_AUX_INT_EN_REG, 0x00},
{WCD938X_AUX_INT_PA_CTRL, 0x06},
{WCD938X_AUX_INT_SP_CTRL, 0xD2},
{WCD938X_AUX_INT_DAC_CTRL, 0x80},
{WCD938X_AUX_INT_CLK_CTRL, 0x50},
{WCD938X_AUX_INT_TEST_CTRL, 0x00},
{WCD938X_AUX_INT_STATUS_REG, 0x00},
{WCD938X_AUX_INT_MISC, 0x00},
{WCD938X_LDORXTX_INT_BIAS, 0x6E},
{WCD938X_LDORXTX_INT_STB_LOADS_DTEST, 0x50},
{WCD938X_LDORXTX_INT_TEST0, 0x1C},
{WCD938X_LDORXTX_INT_STARTUP_TIMER, 0xFF},
{WCD938X_LDORXTX_INT_TEST1, 0x1F},
{WCD938X_LDORXTX_INT_STATUS, 0x00},
{WCD938X_SLEEP_INT_WATCHDOG_CTL_1, 0x0A},
{WCD938X_SLEEP_INT_WATCHDOG_CTL_2, 0x0A},
{WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1, 0x02},
{WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2, 0x60},
{WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2, 0xFF},
{WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1, 0x7F},
{WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0, 0x3F},
{WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M, 0x1F},
{WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M, 0x0F},
{WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1, 0xD7},
{WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0, 0xC8},
{WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP, 0xC6},
{WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1, 0xD5},
{WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0, 0xCA},
{WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP, 0x05},
{WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0, 0xA5},
{WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP, 0x13},
{WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1, 0x88},
{WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP, 0x42},
{WCD938X_TX_COM_NEW_INT_TXADC_INT_L2, 0xFF},
{WCD938X_TX_COM_NEW_INT_TXADC_INT_L1, 0x64},
{WCD938X_TX_COM_NEW_INT_TXADC_INT_L0, 0x64},
{WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP, 0x77},
{WCD938X_DIGITAL_PAGE_REGISTER, 0x00},
{WCD938X_DIGITAL_CHIP_ID0, 0x00},
{WCD938X_DIGITAL_CHIP_ID1, 0x00},
{WCD938X_DIGITAL_CHIP_ID2, 0x0D},
{WCD938X_DIGITAL_CHIP_ID3, 0x01},
{WCD938X_DIGITAL_SWR_TX_CLK_RATE, 0x00},
{WCD938X_DIGITAL_CDC_RST_CTL, 0x03},
{WCD938X_DIGITAL_TOP_CLK_CFG, 0x00},
{WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x00},
{WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0},
{WCD938X_DIGITAL_SWR_RST_EN, 0x00},
{WCD938X_DIGITAL_CDC_PATH_MODE, 0x55},
{WCD938X_DIGITAL_CDC_RX_RST, 0x00},
{WCD938X_DIGITAL_CDC_RX0_CTL, 0xFC},
{WCD938X_DIGITAL_CDC_RX1_CTL, 0xFC},
{WCD938X_DIGITAL_CDC_RX2_CTL, 0xFC},
{WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x00},
{WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x00},
{WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x00},
{WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x1E},
{WCD938X_DIGITAL_CDC_HPH_DSM_A1_0, 0x00},
{WCD938X_DIGITAL_CDC_HPH_DSM_A1_1, 0x01},
{WCD938X_DIGITAL_CDC_HPH_DSM_A2_0, 0x63},
{WCD938X_DIGITAL_CDC_HPH_DSM_A2_1, 0x04},
{WCD938X_DIGITAL_CDC_HPH_DSM_A3_0, 0xAC},
{WCD938X_DIGITAL_CDC_HPH_DSM_A3_1, 0x04},
{WCD938X_DIGITAL_CDC_HPH_DSM_A4_0, 0x1A},
{WCD938X_DIGITAL_CDC_HPH_DSM_A4_1, 0x03},
{WCD938X_DIGITAL_CDC_HPH_DSM_A5_0, 0xBC},
{WCD938X_DIGITAL_CDC_HPH_DSM_A5_1, 0x02},
{WCD938X_DIGITAL_CDC_HPH_DSM_A6_0, 0xC7},
{WCD938X_DIGITAL_CDC_HPH_DSM_A7_0, 0xF8},
{WCD938X_DIGITAL_CDC_HPH_DSM_C_0, 0x47},
{WCD938X_DIGITAL_CDC_HPH_DSM_C_1, 0x43},
{WCD938X_DIGITAL_CDC_HPH_DSM_C_2, 0xB1},
{WCD938X_DIGITAL_CDC_HPH_DSM_C_3, 0x17},
{WCD938X_DIGITAL_CDC_HPH_DSM_R1, 0x4D},
{WCD938X_DIGITAL_CDC_HPH_DSM_R2, 0x29},
{WCD938X_DIGITAL_CDC_HPH_DSM_R3, 0x34},
{WCD938X_DIGITAL_CDC_HPH_DSM_R4, 0x59},
{WCD938X_DIGITAL_CDC_HPH_DSM_R5, 0x66},
{WCD938X_DIGITAL_CDC_HPH_DSM_R6, 0x87},
{WCD938X_DIGITAL_CDC_HPH_DSM_R7, 0x64},
{WCD938X_DIGITAL_CDC_AUX_DSM_A1_0, 0x00},
{WCD938X_DIGITAL_CDC_AUX_DSM_A1_1, 0x01},
{WCD938X_DIGITAL_CDC_AUX_DSM_A2_0, 0x96},
{WCD938X_DIGITAL_CDC_AUX_DSM_A2_1, 0x09},
{WCD938X_DIGITAL_CDC_AUX_DSM_A3_0, 0xAB},
{WCD938X_DIGITAL_CDC_AUX_DSM_A3_1, 0x05},
{WCD938X_DIGITAL_CDC_AUX_DSM_A4_0, 0x1C},
{WCD938X_DIGITAL_CDC_AUX_DSM_A4_1, 0x02},
{WCD938X_DIGITAL_CDC_AUX_DSM_A5_0, 0x17},
{WCD938X_DIGITAL_CDC_AUX_DSM_A5_1, 0x02},
{WCD938X_DIGITAL_CDC_AUX_DSM_A6_0, 0xAA},
{WCD938X_DIGITAL_CDC_AUX_DSM_A7_0, 0xE3},
{WCD938X_DIGITAL_CDC_AUX_DSM_C_0, 0x69},
{WCD938X_DIGITAL_CDC_AUX_DSM_C_1, 0x54},
{WCD938X_DIGITAL_CDC_AUX_DSM_C_2, 0x02},
{WCD938X_DIGITAL_CDC_AUX_DSM_C_3, 0x15},
{WCD938X_DIGITAL_CDC_AUX_DSM_R1, 0xA4},
{WCD938X_DIGITAL_CDC_AUX_DSM_R2, 0xB5},
{WCD938X_DIGITAL_CDC_AUX_DSM_R3, 0x86},
{WCD938X_DIGITAL_CDC_AUX_DSM_R4, 0x85},
{WCD938X_DIGITAL_CDC_AUX_DSM_R5, 0xAA},
{WCD938X_DIGITAL_CDC_AUX_DSM_R6, 0xE2},
{WCD938X_DIGITAL_CDC_AUX_DSM_R7, 0x62},
{WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0, 0x55},
{WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1, 0xA9},
{WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0, 0x3D},
{WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1, 0x2E},
{WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2, 0x01},
{WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0, 0x00},
{WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1, 0xFC},
{WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2, 0x01},
{WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x00},
{WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x00},
{WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0x00},
{WCD938X_DIGITAL_CDC_SWR_CLH, 0x00},
{WCD938X_DIGITAL_SWR_CLH_BYP, 0x00},
{WCD938X_DIGITAL_CDC_TX0_CTL, 0x68},
{WCD938X_DIGITAL_CDC_TX1_CTL, 0x68},
{WCD938X_DIGITAL_CDC_TX2_CTL, 0x68},
{WCD938X_DIGITAL_CDC_TX_RST, 0x00},
{WCD938X_DIGITAL_CDC_REQ_CTL, 0x01},
{WCD938X_DIGITAL_CDC_RST, 0x00},
{WCD938X_DIGITAL_CDC_AMIC_CTL, 0x0F},
{WCD938X_DIGITAL_CDC_DMIC_CTL, 0x04},
{WCD938X_DIGITAL_CDC_DMIC1_CTL, 0x01},
{WCD938X_DIGITAL_CDC_DMIC2_CTL, 0x01},
{WCD938X_DIGITAL_CDC_DMIC3_CTL, 0x01},
{WCD938X_DIGITAL_CDC_DMIC4_CTL, 0x01},
{WCD938X_DIGITAL_EFUSE_PRG_CTL, 0x00},
{WCD938X_DIGITAL_EFUSE_CTL, 0x2B},
{WCD938X_DIGITAL_CDC_DMIC_RATE_1_2, 0x11},
{WCD938X_DIGITAL_CDC_DMIC_RATE_3_4, 0x11},
{WCD938X_DIGITAL_PDM_WD_CTL0, 0x00},
{WCD938X_DIGITAL_PDM_WD_CTL1, 0x00},
{WCD938X_DIGITAL_PDM_WD_CTL2, 0x00},
{WCD938X_DIGITAL_INTR_MODE, 0x00},
{WCD938X_DIGITAL_INTR_MASK_0, 0xFF},
{WCD938X_DIGITAL_INTR_MASK_1, 0xFF},
{WCD938X_DIGITAL_INTR_MASK_2, 0x3F},
{WCD938X_DIGITAL_INTR_STATUS_0, 0x00},
{WCD938X_DIGITAL_INTR_STATUS_1, 0x00},
{WCD938X_DIGITAL_INTR_STATUS_2, 0x00},
{WCD938X_DIGITAL_INTR_CLEAR_0, 0x00},
{WCD938X_DIGITAL_INTR_CLEAR_1, 0x00},
{WCD938X_DIGITAL_INTR_CLEAR_2, 0x00},
{WCD938X_DIGITAL_INTR_LEVEL_0, 0x00},
{WCD938X_DIGITAL_INTR_LEVEL_1, 0x00},
{WCD938X_DIGITAL_INTR_LEVEL_2, 0x00},
{WCD938X_DIGITAL_INTR_SET_0, 0x00},
{WCD938X_DIGITAL_INTR_SET_1, 0x00},
{WCD938X_DIGITAL_INTR_SET_2, 0x00},
{WCD938X_DIGITAL_INTR_TEST_0, 0x00},
{WCD938X_DIGITAL_INTR_TEST_1, 0x00},
{WCD938X_DIGITAL_INTR_TEST_2, 0x00},
{WCD938X_DIGITAL_TX_MODE_DBG_EN, 0x00},
{WCD938X_DIGITAL_TX_MODE_DBG_0_1, 0x00},
{WCD938X_DIGITAL_TX_MODE_DBG_2_3, 0x00},
{WCD938X_DIGITAL_LB_IN_SEL_CTL, 0x00},
{WCD938X_DIGITAL_LOOP_BACK_MODE, 0x00},
{WCD938X_DIGITAL_SWR_DAC_TEST, 0x00},
{WCD938X_DIGITAL_SWR_HM_TEST_RX_0, 0x40},
{WCD938X_DIGITAL_SWR_HM_TEST_TX_0, 0x40},
{WCD938X_DIGITAL_SWR_HM_TEST_RX_1, 0x00},
{WCD938X_DIGITAL_SWR_HM_TEST_TX_1, 0x00},
{WCD938X_DIGITAL_SWR_HM_TEST_TX_2, 0x00},
{WCD938X_DIGITAL_SWR_HM_TEST_0, 0x00},
{WCD938X_DIGITAL_SWR_HM_TEST_1, 0x00},
{WCD938X_DIGITAL_PAD_CTL_SWR_0, 0x8F},
{WCD938X_DIGITAL_PAD_CTL_SWR_1, 0x06},
{WCD938X_DIGITAL_I2C_CTL, 0x00},
{WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE, 0x00},
{WCD938X_DIGITAL_EFUSE_TEST_CTL_0, 0x00},
{WCD938X_DIGITAL_EFUSE_TEST_CTL_1, 0x00},
{WCD938X_DIGITAL_EFUSE_T_DATA_0, 0x00},
{WCD938X_DIGITAL_EFUSE_T_DATA_1, 0x00},
{WCD938X_DIGITAL_PAD_CTL_PDM_RX0, 0xF1},
{WCD938X_DIGITAL_PAD_CTL_PDM_RX1, 0xF1},
{WCD938X_DIGITAL_PAD_CTL_PDM_TX0, 0xF1},
{WCD938X_DIGITAL_PAD_CTL_PDM_TX1, 0xF1},
{WCD938X_DIGITAL_PAD_CTL_PDM_TX2, 0xF1},
{WCD938X_DIGITAL_PAD_INP_DIS_0, 0x00},
{WCD938X_DIGITAL_PAD_INP_DIS_1, 0x00},
{WCD938X_DIGITAL_DRIVE_STRENGTH_0, 0x00},
{WCD938X_DIGITAL_DRIVE_STRENGTH_1, 0x00},
{WCD938X_DIGITAL_DRIVE_STRENGTH_2, 0x00},
{WCD938X_DIGITAL_RX_DATA_EDGE_CTL, 0x1F},
{WCD938X_DIGITAL_TX_DATA_EDGE_CTL, 0x80},
{WCD938X_DIGITAL_GPIO_MODE, 0x00},
{WCD938X_DIGITAL_PIN_CTL_OE, 0x00},
{WCD938X_DIGITAL_PIN_CTL_DATA_0, 0x00},
{WCD938X_DIGITAL_PIN_CTL_DATA_1, 0x00},
{WCD938X_DIGITAL_PIN_STATUS_0, 0x00},
{WCD938X_DIGITAL_PIN_STATUS_1, 0x00},
{WCD938X_DIGITAL_DIG_DEBUG_CTL, 0x00},
{WCD938X_DIGITAL_DIG_DEBUG_EN, 0x00},
{WCD938X_DIGITAL_ANA_CSR_DBG_ADD, 0x00},
{WCD938X_DIGITAL_ANA_CSR_DBG_CTL, 0x48},
{WCD938X_DIGITAL_SSP_DBG, 0x00},
{WCD938X_DIGITAL_MODE_STATUS_0, 0x00},
{WCD938X_DIGITAL_MODE_STATUS_1, 0x00},
{WCD938X_DIGITAL_SPARE_0, 0x00},
{WCD938X_DIGITAL_SPARE_1, 0x00},
{WCD938X_DIGITAL_SPARE_2, 0x00},
{WCD938X_DIGITAL_EFUSE_REG_0, 0x00},
{WCD938X_DIGITAL_EFUSE_REG_1, 0xFF},
{WCD938X_DIGITAL_EFUSE_REG_2, 0xFF},
{WCD938X_DIGITAL_EFUSE_REG_3, 0xFF},
{WCD938X_DIGITAL_EFUSE_REG_4, 0xFF},
{WCD938X_DIGITAL_EFUSE_REG_5, 0xFF},
{WCD938X_DIGITAL_EFUSE_REG_6, 0xFF},
{WCD938X_DIGITAL_EFUSE_REG_7, 0xFF},
{WCD938X_DIGITAL_EFUSE_REG_8, 0xFF},
{WCD938X_DIGITAL_EFUSE_REG_9, 0xFF},
{WCD938X_DIGITAL_EFUSE_REG_10, 0xFF},
{WCD938X_DIGITAL_EFUSE_REG_11, 0xFF},
{WCD938X_DIGITAL_EFUSE_REG_12, 0xFF},
{WCD938X_DIGITAL_EFUSE_REG_13, 0xFF},
{WCD938X_DIGITAL_EFUSE_REG_14, 0xFF},
{WCD938X_DIGITAL_EFUSE_REG_15, 0xFF},
{WCD938X_DIGITAL_EFUSE_REG_16, 0xFF},
{WCD938X_DIGITAL_EFUSE_REG_17, 0xFF},
{WCD938X_DIGITAL_EFUSE_REG_18, 0xFF},
{WCD938X_DIGITAL_EFUSE_REG_19, 0xFF},
{WCD938X_DIGITAL_EFUSE_REG_20, 0x0E},
{WCD938X_DIGITAL_EFUSE_REG_21, 0x00},
{WCD938X_DIGITAL_EFUSE_REG_22, 0x00},
{WCD938X_DIGITAL_EFUSE_REG_23, 0xF8},
{WCD938X_DIGITAL_EFUSE_REG_24, 0x16},
{WCD938X_DIGITAL_EFUSE_REG_25, 0x00},
{WCD938X_DIGITAL_EFUSE_REG_26, 0x00},
{WCD938X_DIGITAL_EFUSE_REG_27, 0x00},
{WCD938X_DIGITAL_EFUSE_REG_28, 0x00},
{WCD938X_DIGITAL_EFUSE_REG_29, 0x00},
{WCD938X_DIGITAL_EFUSE_REG_30, 0x00},
{WCD938X_DIGITAL_EFUSE_REG_31, 0x00},
{WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0x88},
{WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0x88},
{WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0x88},
{WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0x88},
{WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0x88},
{WCD938X_DIGITAL_DEM_BYPASS_DATA0, 0x55},
{WCD938X_DIGITAL_DEM_BYPASS_DATA1, 0x55},
{WCD938X_DIGITAL_DEM_BYPASS_DATA2, 0x55},
{WCD938X_DIGITAL_DEM_BYPASS_DATA3, 0x01},
};
static bool wcd938x_rdwr_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case WCD938X_ANA_PAGE_REGISTER:
case WCD938X_ANA_BIAS:
case WCD938X_ANA_RX_SUPPLIES:
case WCD938X_ANA_HPH:
case WCD938X_ANA_EAR:
case WCD938X_ANA_EAR_COMPANDER_CTL:
case WCD938X_ANA_TX_CH1:
case WCD938X_ANA_TX_CH2:
case WCD938X_ANA_TX_CH3:
case WCD938X_ANA_TX_CH4:
case WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC:
case WCD938X_ANA_MICB3_DSP_EN_LOGIC:
case WCD938X_ANA_MBHC_MECH:
case WCD938X_ANA_MBHC_ELECT:
case WCD938X_ANA_MBHC_ZDET:
case WCD938X_ANA_MBHC_BTN0:
case WCD938X_ANA_MBHC_BTN1:
case WCD938X_ANA_MBHC_BTN2:
case WCD938X_ANA_MBHC_BTN3:
case WCD938X_ANA_MBHC_BTN4:
case WCD938X_ANA_MBHC_BTN5:
case WCD938X_ANA_MBHC_BTN6:
case WCD938X_ANA_MBHC_BTN7:
case WCD938X_ANA_MICB1:
case WCD938X_ANA_MICB2:
case WCD938X_ANA_MICB2_RAMP:
case WCD938X_ANA_MICB3:
case WCD938X_ANA_MICB4:
case WCD938X_BIAS_CTL:
case WCD938X_BIAS_VBG_FINE_ADJ:
case WCD938X_LDOL_VDDCX_ADJUST:
case WCD938X_LDOL_DISABLE_LDOL:
case WCD938X_MBHC_CTL_CLK:
case WCD938X_MBHC_CTL_ANA:
case WCD938X_MBHC_CTL_SPARE_1:
case WCD938X_MBHC_CTL_SPARE_2:
case WCD938X_MBHC_CTL_BCS:
case WCD938X_MBHC_TEST_CTL:
case WCD938X_LDOH_MODE:
case WCD938X_LDOH_BIAS:
case WCD938X_LDOH_STB_LOADS:
case WCD938X_LDOH_SLOWRAMP:
case WCD938X_MICB1_TEST_CTL_1:
case WCD938X_MICB1_TEST_CTL_2:
case WCD938X_MICB1_TEST_CTL_3:
case WCD938X_MICB2_TEST_CTL_1:
case WCD938X_MICB2_TEST_CTL_2:
case WCD938X_MICB2_TEST_CTL_3:
case WCD938X_MICB3_TEST_CTL_1:
case WCD938X_MICB3_TEST_CTL_2:
case WCD938X_MICB3_TEST_CTL_3:
case WCD938X_MICB4_TEST_CTL_1:
case WCD938X_MICB4_TEST_CTL_2:
case WCD938X_MICB4_TEST_CTL_3:
case WCD938X_TX_COM_ADC_VCM:
case WCD938X_TX_COM_BIAS_ATEST:
case WCD938X_TX_COM_SPARE1:
case WCD938X_TX_COM_SPARE2:
case WCD938X_TX_COM_TXFE_DIV_CTL:
case WCD938X_TX_COM_TXFE_DIV_START:
case WCD938X_TX_COM_SPARE3:
case WCD938X_TX_COM_SPARE4:
case WCD938X_TX_1_2_TEST_EN:
case WCD938X_TX_1_2_ADC_IB:
case WCD938X_TX_1_2_ATEST_REFCTL:
case WCD938X_TX_1_2_TEST_CTL:
case WCD938X_TX_1_2_TEST_BLK_EN1:
case WCD938X_TX_1_2_TXFE1_CLKDIV:
case WCD938X_TX_3_4_TEST_EN:
case WCD938X_TX_3_4_ADC_IB:
case WCD938X_TX_3_4_ATEST_REFCTL:
case WCD938X_TX_3_4_TEST_CTL:
case WCD938X_TX_3_4_TEST_BLK_EN3:
case WCD938X_TX_3_4_TXFE3_CLKDIV:
case WCD938X_TX_3_4_TEST_BLK_EN2:
case WCD938X_TX_3_4_TXFE2_CLKDIV:
case WCD938X_TX_3_4_SPARE1:
case WCD938X_TX_3_4_TEST_BLK_EN4:
case WCD938X_TX_3_4_TXFE4_CLKDIV:
case WCD938X_TX_3_4_SPARE2:
case WCD938X_CLASSH_MODE_1:
case WCD938X_CLASSH_MODE_2:
case WCD938X_CLASSH_MODE_3:
case WCD938X_CLASSH_CTRL_VCL_1:
case WCD938X_CLASSH_CTRL_VCL_2:
case WCD938X_CLASSH_CTRL_CCL_1:
case WCD938X_CLASSH_CTRL_CCL_2:
case WCD938X_CLASSH_CTRL_CCL_3:
case WCD938X_CLASSH_CTRL_CCL_4:
case WCD938X_CLASSH_CTRL_CCL_5:
case WCD938X_CLASSH_BUCK_TMUX_A_D:
case WCD938X_CLASSH_BUCK_SW_DRV_CNTL:
case WCD938X_CLASSH_SPARE:
case WCD938X_FLYBACK_EN:
case WCD938X_FLYBACK_VNEG_CTRL_1:
case WCD938X_FLYBACK_VNEG_CTRL_2:
case WCD938X_FLYBACK_VNEG_CTRL_3:
case WCD938X_FLYBACK_VNEG_CTRL_4:
case WCD938X_FLYBACK_VNEG_CTRL_5:
case WCD938X_FLYBACK_VNEG_CTRL_6:
case WCD938X_FLYBACK_VNEG_CTRL_7:
case WCD938X_FLYBACK_VNEG_CTRL_8:
case WCD938X_FLYBACK_VNEG_CTRL_9:
case WCD938X_FLYBACK_VNEGDAC_CTRL_1:
case WCD938X_FLYBACK_VNEGDAC_CTRL_2:
case WCD938X_FLYBACK_VNEGDAC_CTRL_3:
case WCD938X_FLYBACK_CTRL_1:
case WCD938X_FLYBACK_TEST_CTL:
case WCD938X_RX_AUX_SW_CTL:
case WCD938X_RX_PA_AUX_IN_CONN:
case WCD938X_RX_TIMER_DIV:
case WCD938X_RX_OCP_CTL:
case WCD938X_RX_OCP_COUNT:
case WCD938X_RX_BIAS_EAR_DAC:
case WCD938X_RX_BIAS_EAR_AMP:
case WCD938X_RX_BIAS_HPH_LDO:
case WCD938X_RX_BIAS_HPH_PA:
case WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2:
case WCD938X_RX_BIAS_HPH_RDAC_LDO:
case WCD938X_RX_BIAS_HPH_CNP1:
case WCD938X_RX_BIAS_HPH_LOWPOWER:
case WCD938X_RX_BIAS_AUX_DAC:
case WCD938X_RX_BIAS_AUX_AMP:
case WCD938X_RX_BIAS_VNEGDAC_BLEEDER:
case WCD938X_RX_BIAS_MISC:
case WCD938X_RX_BIAS_BUCK_RST:
case WCD938X_RX_BIAS_BUCK_VREF_ERRAMP:
case WCD938X_RX_BIAS_FLYB_ERRAMP:
case WCD938X_RX_BIAS_FLYB_BUFF:
case WCD938X_RX_BIAS_FLYB_MID_RST:
case WCD938X_HPH_CNP_EN:
case WCD938X_HPH_CNP_WG_CTL:
case WCD938X_HPH_CNP_WG_TIME:
case WCD938X_HPH_OCP_CTL:
case WCD938X_HPH_AUTO_CHOP:
case WCD938X_HPH_CHOP_CTL:
case WCD938X_HPH_PA_CTL1:
case WCD938X_HPH_PA_CTL2:
case WCD938X_HPH_L_EN:
case WCD938X_HPH_L_TEST:
case WCD938X_HPH_L_ATEST:
case WCD938X_HPH_R_EN:
case WCD938X_HPH_R_TEST:
case WCD938X_HPH_R_ATEST:
case WCD938X_HPH_RDAC_CLK_CTL1:
case WCD938X_HPH_RDAC_CLK_CTL2:
case WCD938X_HPH_RDAC_LDO_CTL:
case WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL:
case WCD938X_HPH_REFBUFF_UHQA_CTL:
case WCD938X_HPH_REFBUFF_LP_CTL:
case WCD938X_HPH_L_DAC_CTL:
case WCD938X_HPH_R_DAC_CTL:
case WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL:
case WCD938X_HPH_SURGE_HPHLR_SURGE_EN:
case WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1:
case WCD938X_EAR_EAR_EN_REG:
case WCD938X_EAR_EAR_PA_CON:
case WCD938X_EAR_EAR_SP_CON:
case WCD938X_EAR_EAR_DAC_CON:
case WCD938X_EAR_EAR_CNP_FSM_CON:
case WCD938X_EAR_TEST_CTL:
case WCD938X_ANA_NEW_PAGE_REGISTER:
case WCD938X_HPH_NEW_ANA_HPH2:
case WCD938X_HPH_NEW_ANA_HPH3:
case WCD938X_SLEEP_CTL:
case WCD938X_SLEEP_WATCHDOG_CTL:
case WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL:
case WCD938X_MBHC_NEW_CTL_1:
case WCD938X_MBHC_NEW_CTL_2:
case WCD938X_MBHC_NEW_PLUG_DETECT_CTL:
case WCD938X_MBHC_NEW_ZDET_ANA_CTL:
case WCD938X_MBHC_NEW_ZDET_RAMP_CTL:
case WCD938X_TX_NEW_AMIC_MUX_CFG:
case WCD938X_AUX_AUXPA:
case WCD938X_LDORXTX_MODE:
case WCD938X_LDORXTX_CONFIG:
case WCD938X_DIE_CRACK_DIE_CRK_DET_EN:
case WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL:
case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L:
case WCD938X_HPH_NEW_INT_RDAC_VREF_CTL:
case WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL:
case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R:
case WCD938X_HPH_NEW_INT_PA_MISC1:
case WCD938X_HPH_NEW_INT_PA_MISC2:
case WCD938X_HPH_NEW_INT_PA_RDAC_MISC:
case WCD938X_HPH_NEW_INT_HPH_TIMER1:
case WCD938X_HPH_NEW_INT_HPH_TIMER2:
case WCD938X_HPH_NEW_INT_HPH_TIMER3:
case WCD938X_HPH_NEW_INT_HPH_TIMER4:
case WCD938X_HPH_NEW_INT_PA_RDAC_MISC2:
case WCD938X_HPH_NEW_INT_PA_RDAC_MISC3:
case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW:
case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW:
case WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI:
case WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP:
case WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP:
case WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL:
case WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL:
case WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT:
case WCD938X_MBHC_NEW_INT_SPARE_2:
case WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON:
case WCD938X_EAR_INT_NEW_CNP_VCM_CON1:
case WCD938X_EAR_INT_NEW_CNP_VCM_CON2:
case WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS:
case WCD938X_AUX_INT_EN_REG:
case WCD938X_AUX_INT_PA_CTRL:
case WCD938X_AUX_INT_SP_CTRL:
case WCD938X_AUX_INT_DAC_CTRL:
case WCD938X_AUX_INT_CLK_CTRL:
case WCD938X_AUX_INT_TEST_CTRL:
case WCD938X_AUX_INT_MISC:
case WCD938X_LDORXTX_INT_BIAS:
case WCD938X_LDORXTX_INT_STB_LOADS_DTEST:
case WCD938X_LDORXTX_INT_TEST0:
case WCD938X_LDORXTX_INT_STARTUP_TIMER:
case WCD938X_LDORXTX_INT_TEST1:
case WCD938X_SLEEP_INT_WATCHDOG_CTL_1:
case WCD938X_SLEEP_INT_WATCHDOG_CTL_2:
case WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1:
case WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2:
case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2:
case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1:
case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0:
case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M:
case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M:
case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1:
case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0:
case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP:
case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1:
case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0:
case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP:
case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0:
case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP:
case WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1:
case WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP:
case WCD938X_TX_COM_NEW_INT_TXADC_INT_L2:
case WCD938X_TX_COM_NEW_INT_TXADC_INT_L1:
case WCD938X_TX_COM_NEW_INT_TXADC_INT_L0:
case WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP:
case WCD938X_DIGITAL_PAGE_REGISTER:
case WCD938X_DIGITAL_SWR_TX_CLK_RATE:
case WCD938X_DIGITAL_CDC_RST_CTL:
case WCD938X_DIGITAL_TOP_CLK_CFG:
case WCD938X_DIGITAL_CDC_ANA_CLK_CTL:
case WCD938X_DIGITAL_CDC_DIG_CLK_CTL:
case WCD938X_DIGITAL_SWR_RST_EN:
case WCD938X_DIGITAL_CDC_PATH_MODE:
case WCD938X_DIGITAL_CDC_RX_RST:
case WCD938X_DIGITAL_CDC_RX0_CTL:
case WCD938X_DIGITAL_CDC_RX1_CTL:
case WCD938X_DIGITAL_CDC_RX2_CTL:
case WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1:
case WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3:
case WCD938X_DIGITAL_CDC_COMP_CTL_0:
case WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL:
case WCD938X_DIGITAL_CDC_HPH_DSM_A1_0:
case WCD938X_DIGITAL_CDC_HPH_DSM_A1_1:
case WCD938X_DIGITAL_CDC_HPH_DSM_A2_0:
case WCD938X_DIGITAL_CDC_HPH_DSM_A2_1:
case WCD938X_DIGITAL_CDC_HPH_DSM_A3_0:
case WCD938X_DIGITAL_CDC_HPH_DSM_A3_1:
case WCD938X_DIGITAL_CDC_HPH_DSM_A4_0:
case WCD938X_DIGITAL_CDC_HPH_DSM_A4_1:
case WCD938X_DIGITAL_CDC_HPH_DSM_A5_0:
case WCD938X_DIGITAL_CDC_HPH_DSM_A5_1:
case WCD938X_DIGITAL_CDC_HPH_DSM_A6_0:
case WCD938X_DIGITAL_CDC_HPH_DSM_A7_0:
case WCD938X_DIGITAL_CDC_HPH_DSM_C_0:
case WCD938X_DIGITAL_CDC_HPH_DSM_C_1:
case WCD938X_DIGITAL_CDC_HPH_DSM_C_2:
case WCD938X_DIGITAL_CDC_HPH_DSM_C_3:
case WCD938X_DIGITAL_CDC_HPH_DSM_R1:
case WCD938X_DIGITAL_CDC_HPH_DSM_R2:
case WCD938X_DIGITAL_CDC_HPH_DSM_R3:
case WCD938X_DIGITAL_CDC_HPH_DSM_R4:
case WCD938X_DIGITAL_CDC_HPH_DSM_R5:
case WCD938X_DIGITAL_CDC_HPH_DSM_R6:
case WCD938X_DIGITAL_CDC_HPH_DSM_R7:
case WCD938X_DIGITAL_CDC_AUX_DSM_A1_0:
case WCD938X_DIGITAL_CDC_AUX_DSM_A1_1:
case WCD938X_DIGITAL_CDC_AUX_DSM_A2_0:
case WCD938X_DIGITAL_CDC_AUX_DSM_A2_1:
case WCD938X_DIGITAL_CDC_AUX_DSM_A3_0:
case WCD938X_DIGITAL_CDC_AUX_DSM_A3_1:
case WCD938X_DIGITAL_CDC_AUX_DSM_A4_0:
case WCD938X_DIGITAL_CDC_AUX_DSM_A4_1:
case WCD938X_DIGITAL_CDC_AUX_DSM_A5_0:
case WCD938X_DIGITAL_CDC_AUX_DSM_A5_1:
case WCD938X_DIGITAL_CDC_AUX_DSM_A6_0:
case WCD938X_DIGITAL_CDC_AUX_DSM_A7_0:
case WCD938X_DIGITAL_CDC_AUX_DSM_C_0:
case WCD938X_DIGITAL_CDC_AUX_DSM_C_1:
case WCD938X_DIGITAL_CDC_AUX_DSM_C_2:
case WCD938X_DIGITAL_CDC_AUX_DSM_C_3:
case WCD938X_DIGITAL_CDC_AUX_DSM_R1:
case WCD938X_DIGITAL_CDC_AUX_DSM_R2:
case WCD938X_DIGITAL_CDC_AUX_DSM_R3:
case WCD938X_DIGITAL_CDC_AUX_DSM_R4:
case WCD938X_DIGITAL_CDC_AUX_DSM_R5:
case WCD938X_DIGITAL_CDC_AUX_DSM_R6:
case WCD938X_DIGITAL_CDC_AUX_DSM_R7:
case WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0:
case WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1:
case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0:
case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1:
case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2:
case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0:
case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1:
case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2:
case WCD938X_DIGITAL_CDC_HPH_GAIN_CTL:
case WCD938X_DIGITAL_CDC_AUX_GAIN_CTL:
case WCD938X_DIGITAL_CDC_EAR_PATH_CTL:
case WCD938X_DIGITAL_CDC_SWR_CLH:
case WCD938X_DIGITAL_SWR_CLH_BYP:
case WCD938X_DIGITAL_CDC_TX0_CTL:
case WCD938X_DIGITAL_CDC_TX1_CTL:
case WCD938X_DIGITAL_CDC_TX2_CTL:
case WCD938X_DIGITAL_CDC_TX_RST:
case WCD938X_DIGITAL_CDC_REQ_CTL:
case WCD938X_DIGITAL_CDC_RST:
case WCD938X_DIGITAL_CDC_AMIC_CTL:
case WCD938X_DIGITAL_CDC_DMIC_CTL:
case WCD938X_DIGITAL_CDC_DMIC1_CTL:
case WCD938X_DIGITAL_CDC_DMIC2_CTL:
case WCD938X_DIGITAL_CDC_DMIC3_CTL:
case WCD938X_DIGITAL_CDC_DMIC4_CTL:
case WCD938X_DIGITAL_EFUSE_PRG_CTL:
case WCD938X_DIGITAL_EFUSE_CTL:
case WCD938X_DIGITAL_CDC_DMIC_RATE_1_2:
case WCD938X_DIGITAL_CDC_DMIC_RATE_3_4:
case WCD938X_DIGITAL_PDM_WD_CTL0:
case WCD938X_DIGITAL_PDM_WD_CTL1:
case WCD938X_DIGITAL_PDM_WD_CTL2:
case WCD938X_DIGITAL_INTR_MODE:
case WCD938X_DIGITAL_INTR_MASK_0:
case WCD938X_DIGITAL_INTR_MASK_1:
case WCD938X_DIGITAL_INTR_MASK_2:
case WCD938X_DIGITAL_INTR_CLEAR_0:
case WCD938X_DIGITAL_INTR_CLEAR_1:
case WCD938X_DIGITAL_INTR_CLEAR_2:
case WCD938X_DIGITAL_INTR_LEVEL_0:
case WCD938X_DIGITAL_INTR_LEVEL_1:
case WCD938X_DIGITAL_INTR_LEVEL_2:
case WCD938X_DIGITAL_INTR_SET_0:
case WCD938X_DIGITAL_INTR_SET_1:
case WCD938X_DIGITAL_INTR_SET_2:
case WCD938X_DIGITAL_INTR_TEST_0:
case WCD938X_DIGITAL_INTR_TEST_1:
case WCD938X_DIGITAL_INTR_TEST_2:
case WCD938X_DIGITAL_TX_MODE_DBG_EN:
case WCD938X_DIGITAL_TX_MODE_DBG_0_1:
case WCD938X_DIGITAL_TX_MODE_DBG_2_3:
case WCD938X_DIGITAL_LB_IN_SEL_CTL:
case WCD938X_DIGITAL_LOOP_BACK_MODE:
case WCD938X_DIGITAL_SWR_DAC_TEST:
case WCD938X_DIGITAL_SWR_HM_TEST_RX_0:
case WCD938X_DIGITAL_SWR_HM_TEST_TX_0:
case WCD938X_DIGITAL_SWR_HM_TEST_RX_1:
case WCD938X_DIGITAL_SWR_HM_TEST_TX_1:
case WCD938X_DIGITAL_SWR_HM_TEST_TX_2:
case WCD938X_DIGITAL_PAD_CTL_SWR_0:
case WCD938X_DIGITAL_PAD_CTL_SWR_1:
case WCD938X_DIGITAL_I2C_CTL:
case WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE:
case WCD938X_DIGITAL_EFUSE_TEST_CTL_0:
case WCD938X_DIGITAL_EFUSE_TEST_CTL_1:
case WCD938X_DIGITAL_PAD_CTL_PDM_RX0:
case WCD938X_DIGITAL_PAD_CTL_PDM_RX1:
case WCD938X_DIGITAL_PAD_CTL_PDM_TX0:
case WCD938X_DIGITAL_PAD_CTL_PDM_TX1:
case WCD938X_DIGITAL_PAD_CTL_PDM_TX2:
case WCD938X_DIGITAL_PAD_INP_DIS_0:
case WCD938X_DIGITAL_PAD_INP_DIS_1:
case WCD938X_DIGITAL_DRIVE_STRENGTH_0:
case WCD938X_DIGITAL_DRIVE_STRENGTH_1:
case WCD938X_DIGITAL_DRIVE_STRENGTH_2:
case WCD938X_DIGITAL_RX_DATA_EDGE_CTL:
case WCD938X_DIGITAL_TX_DATA_EDGE_CTL:
case WCD938X_DIGITAL_GPIO_MODE:
case WCD938X_DIGITAL_PIN_CTL_OE:
case WCD938X_DIGITAL_PIN_CTL_DATA_0:
case WCD938X_DIGITAL_PIN_CTL_DATA_1:
case WCD938X_DIGITAL_DIG_DEBUG_CTL:
case WCD938X_DIGITAL_DIG_DEBUG_EN:
case WCD938X_DIGITAL_ANA_CSR_DBG_ADD:
case WCD938X_DIGITAL_ANA_CSR_DBG_CTL:
case WCD938X_DIGITAL_SSP_DBG:
case WCD938X_DIGITAL_SPARE_0:
case WCD938X_DIGITAL_SPARE_1:
case WCD938X_DIGITAL_SPARE_2:
case WCD938X_DIGITAL_TX_REQ_FB_CTL_0:
case WCD938X_DIGITAL_TX_REQ_FB_CTL_1:
case WCD938X_DIGITAL_TX_REQ_FB_CTL_2:
case WCD938X_DIGITAL_TX_REQ_FB_CTL_3:
case WCD938X_DIGITAL_TX_REQ_FB_CTL_4:
case WCD938X_DIGITAL_DEM_BYPASS_DATA0:
case WCD938X_DIGITAL_DEM_BYPASS_DATA1:
case WCD938X_DIGITAL_DEM_BYPASS_DATA2:
case WCD938X_DIGITAL_DEM_BYPASS_DATA3:
return true;
}
return false;
}
static bool wcd938x_readonly_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case WCD938X_ANA_MBHC_RESULT_1:
case WCD938X_ANA_MBHC_RESULT_2:
case WCD938X_ANA_MBHC_RESULT_3:
case WCD938X_MBHC_MOISTURE_DET_FSM_STATUS:
case WCD938X_TX_1_2_SAR2_ERR:
case WCD938X_TX_1_2_SAR1_ERR:
case WCD938X_TX_3_4_SAR4_ERR:
case WCD938X_TX_3_4_SAR3_ERR:
case WCD938X_HPH_L_STATUS:
case WCD938X_HPH_R_STATUS:
case WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS:
case WCD938X_EAR_STATUS_REG_1:
case WCD938X_EAR_STATUS_REG_2:
case WCD938X_MBHC_NEW_FSM_STATUS:
case WCD938X_MBHC_NEW_ADC_RESULT:
case WCD938X_DIE_CRACK_DIE_CRK_DET_OUT:
case WCD938X_AUX_INT_STATUS_REG:
case WCD938X_LDORXTX_INT_STATUS:
case WCD938X_DIGITAL_CHIP_ID0:
case WCD938X_DIGITAL_CHIP_ID1:
case WCD938X_DIGITAL_CHIP_ID2:
case WCD938X_DIGITAL_CHIP_ID3:
case WCD938X_DIGITAL_INTR_STATUS_0:
case WCD938X_DIGITAL_INTR_STATUS_1:
case WCD938X_DIGITAL_INTR_STATUS_2:
case WCD938X_DIGITAL_INTR_CLEAR_0:
case WCD938X_DIGITAL_INTR_CLEAR_1:
case WCD938X_DIGITAL_INTR_CLEAR_2:
case WCD938X_DIGITAL_SWR_HM_TEST_0:
case WCD938X_DIGITAL_SWR_HM_TEST_1:
case WCD938X_DIGITAL_EFUSE_T_DATA_0:
case WCD938X_DIGITAL_EFUSE_T_DATA_1:
case WCD938X_DIGITAL_PIN_STATUS_0:
case WCD938X_DIGITAL_PIN_STATUS_1:
case WCD938X_DIGITAL_MODE_STATUS_0:
case WCD938X_DIGITAL_MODE_STATUS_1:
case WCD938X_DIGITAL_EFUSE_REG_0:
case WCD938X_DIGITAL_EFUSE_REG_1:
case WCD938X_DIGITAL_EFUSE_REG_2:
case WCD938X_DIGITAL_EFUSE_REG_3:
case WCD938X_DIGITAL_EFUSE_REG_4:
case WCD938X_DIGITAL_EFUSE_REG_5:
case WCD938X_DIGITAL_EFUSE_REG_6:
case WCD938X_DIGITAL_EFUSE_REG_7:
case WCD938X_DIGITAL_EFUSE_REG_8:
case WCD938X_DIGITAL_EFUSE_REG_9:
case WCD938X_DIGITAL_EFUSE_REG_10:
case WCD938X_DIGITAL_EFUSE_REG_11:
case WCD938X_DIGITAL_EFUSE_REG_12:
case WCD938X_DIGITAL_EFUSE_REG_13:
case WCD938X_DIGITAL_EFUSE_REG_14:
case WCD938X_DIGITAL_EFUSE_REG_15:
case WCD938X_DIGITAL_EFUSE_REG_16:
case WCD938X_DIGITAL_EFUSE_REG_17:
case WCD938X_DIGITAL_EFUSE_REG_18:
case WCD938X_DIGITAL_EFUSE_REG_19:
case WCD938X_DIGITAL_EFUSE_REG_20:
case WCD938X_DIGITAL_EFUSE_REG_21:
case WCD938X_DIGITAL_EFUSE_REG_22:
case WCD938X_DIGITAL_EFUSE_REG_23:
case WCD938X_DIGITAL_EFUSE_REG_24:
case WCD938X_DIGITAL_EFUSE_REG_25:
case WCD938X_DIGITAL_EFUSE_REG_26:
case WCD938X_DIGITAL_EFUSE_REG_27:
case WCD938X_DIGITAL_EFUSE_REG_28:
case WCD938X_DIGITAL_EFUSE_REG_29:
case WCD938X_DIGITAL_EFUSE_REG_30:
case WCD938X_DIGITAL_EFUSE_REG_31:
return true;
}
return false;
}
static bool wcd938x_readable_register(struct device *dev, unsigned int reg)
{
bool ret;
ret = wcd938x_readonly_register(dev, reg);
if (!ret)
return wcd938x_rdwr_register(dev, reg);
return ret;
}
static bool wcd938x_writeable_register(struct device *dev, unsigned int reg)
{
return wcd938x_rdwr_register(dev, reg);
}
static bool wcd938x_volatile_register(struct device *dev, unsigned int reg)
{
if (reg <= WCD938X_BASE_ADDRESS)
return false;
if (reg == WCD938X_DIGITAL_SWR_TX_CLK_RATE)
return true;
if (wcd938x_readonly_register(dev, reg))
return true;
return false;
}
static const struct regmap_config wcd938x_regmap_config = {
.name = "wcd938x_csr",
.reg_bits = 32,
.val_bits = 8,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = wcd938x_defaults,
.num_reg_defaults = ARRAY_SIZE(wcd938x_defaults),
.max_register = WCD938X_MAX_REGISTER,
.readable_reg = wcd938x_readable_register,
.writeable_reg = wcd938x_writeable_register,
.volatile_reg = wcd938x_volatile_register,
};
static const struct sdw_slave_ops wcd9380_slave_ops = {
.update_status = wcd9380_update_status,
.interrupt_callback = wcd9380_interrupt_callback,
.bus_config = wcd9380_bus_config,
};
static int wcd938x_sdw_component_bind(struct device *dev,
struct device *master, void *data)
{
return 0;
}
static void wcd938x_sdw_component_unbind(struct device *dev,
struct device *master, void *data)
{
}
static const struct component_ops wcd938x_sdw_component_ops = {
.bind = wcd938x_sdw_component_bind,
.unbind = wcd938x_sdw_component_unbind,
};
static int wcd9380_probe(struct sdw_slave *pdev,
const struct sdw_device_id *id)
{
struct device *dev = &pdev->dev;
struct wcd938x_sdw_priv *wcd;
int ret;
wcd = devm_kzalloc(dev, sizeof(*wcd), GFP_KERNEL);
if (!wcd)
return -ENOMEM;
/**
* Port map index starts with 0, however the data port for this codec
* are from index 1
*/
if (of_property_read_bool(dev->of_node, "qcom,tx-port-mapping")) {
wcd->is_tx = true;
ret = of_property_read_u32_array(dev->of_node, "qcom,tx-port-mapping",
&pdev->m_port_map[1],
WCD938X_MAX_TX_SWR_PORTS);
} else {
ret = of_property_read_u32_array(dev->of_node, "qcom,rx-port-mapping",
&pdev->m_port_map[1],
WCD938X_MAX_SWR_PORTS);
}
if (ret < 0)
dev_info(dev, "Static Port mapping not specified\n");
wcd->sdev = pdev;
dev_set_drvdata(dev, wcd);
pdev->prop.scp_int1_mask = SDW_SCP_INT1_IMPL_DEF |
SDW_SCP_INT1_BUS_CLASH |
SDW_SCP_INT1_PARITY;
pdev->prop.lane_control_support = true;
pdev->prop.simple_clk_stop_capable = true;
if (wcd->is_tx) {
pdev->prop.source_ports = GENMASK(WCD938X_MAX_SWR_PORTS, 0);
pdev->prop.src_dpn_prop = wcd938x_dpn_prop;
wcd->ch_info = &wcd938x_sdw_tx_ch_info[0];
pdev->prop.wake_capable = true;
} else {
pdev->prop.sink_ports = GENMASK(WCD938X_MAX_SWR_PORTS, 0);
pdev->prop.sink_dpn_prop = wcd938x_dpn_prop;
wcd->ch_info = &wcd938x_sdw_rx_ch_info[0];
}
if (wcd->is_tx) {
wcd->regmap = devm_regmap_init_sdw(pdev, &wcd938x_regmap_config);
if (IS_ERR(wcd->regmap))
return dev_err_probe(dev, PTR_ERR(wcd->regmap),
"Regmap init failed\n");
/* Start in cache-only until device is enumerated */
regcache_cache_only(wcd->regmap, true);
}
pm_runtime_set_autosuspend_delay(dev, 3000);
pm_runtime_use_autosuspend(dev);
pm_runtime_mark_last_busy(dev);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
return component_add(dev, &wcd938x_sdw_component_ops);
}
static const struct sdw_device_id wcd9380_slave_id[] = {
SDW_SLAVE_ENTRY(0x0217, 0x10d, 0),
{},
};
MODULE_DEVICE_TABLE(sdw, wcd9380_slave_id);
static int __maybe_unused wcd938x_sdw_runtime_suspend(struct device *dev)
{
struct wcd938x_sdw_priv *wcd = dev_get_drvdata(dev);
if (wcd->regmap) {
regcache_cache_only(wcd->regmap, true);
regcache_mark_dirty(wcd->regmap);
}
return 0;
}
static int __maybe_unused wcd938x_sdw_runtime_resume(struct device *dev)
{
struct wcd938x_sdw_priv *wcd = dev_get_drvdata(dev);
if (wcd->regmap) {
regcache_cache_only(wcd->regmap, false);
regcache_sync(wcd->regmap);
}
pm_runtime_mark_last_busy(dev);
return 0;
}
static const struct dev_pm_ops wcd938x_sdw_pm_ops = {
SET_RUNTIME_PM_OPS(wcd938x_sdw_runtime_suspend, wcd938x_sdw_runtime_resume, NULL)
};
static struct sdw_driver wcd9380_codec_driver = {
.probe = wcd9380_probe,
.ops = &wcd9380_slave_ops,
.id_table = wcd9380_slave_id,
.driver = {
.name = "wcd9380-codec",
.pm = &wcd938x_sdw_pm_ops,
}
};
module_sdw_driver(wcd9380_codec_driver);
MODULE_DESCRIPTION("WCD938X SDW codec driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wcd938x-sdw.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* es8328-i2c.c -- ES8328 ALSA SoC I2C Audio driver
*
* Copyright 2014 Sutajio Ko-Usagi PTE LTD
*
* Author: Sean Cross <[email protected]>
*/
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include "es8328.h"
static const struct i2c_device_id es8328_id[] = {
{ "es8328", 0 },
{ "es8388", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, es8328_id);
static const struct of_device_id es8328_of_match[] = {
{ .compatible = "everest,es8328", },
{ .compatible = "everest,es8388", },
{ }
};
MODULE_DEVICE_TABLE(of, es8328_of_match);
static int es8328_i2c_probe(struct i2c_client *i2c)
{
return es8328_probe(&i2c->dev,
devm_regmap_init_i2c(i2c, &es8328_regmap_config));
}
static struct i2c_driver es8328_i2c_driver = {
.driver = {
.name = "es8328",
.of_match_table = es8328_of_match,
},
.probe = es8328_i2c_probe,
.id_table = es8328_id,
};
module_i2c_driver(es8328_i2c_driver);
MODULE_DESCRIPTION("ASoC ES8328 audio CODEC I2C driver");
MODULE_AUTHOR("Sean Cross <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/es8328-i2c.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ADAU1977/ADAU1978/ADAU1979 driver
*
* Copyright 2014 Analog Devices Inc.
* Author: Lars-Peter Clausen <[email protected]>
*/
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/initval.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <dt-bindings/sound/adi,adau1977.h>
#include "adau1977.h"
#define ADAU1977_REG_POWER 0x00
#define ADAU1977_REG_PLL 0x01
#define ADAU1977_REG_BOOST 0x02
#define ADAU1977_REG_MICBIAS 0x03
#define ADAU1977_REG_BLOCK_POWER_SAI 0x04
#define ADAU1977_REG_SAI_CTRL0 0x05
#define ADAU1977_REG_SAI_CTRL1 0x06
#define ADAU1977_REG_CMAP12 0x07
#define ADAU1977_REG_CMAP34 0x08
#define ADAU1977_REG_SAI_OVERTEMP 0x09
#define ADAU1977_REG_POST_ADC_GAIN(x) (0x0a + (x))
#define ADAU1977_REG_MISC_CONTROL 0x0e
#define ADAU1977_REG_DIAG_CONTROL 0x10
#define ADAU1977_REG_STATUS(x) (0x11 + (x))
#define ADAU1977_REG_DIAG_IRQ1 0x15
#define ADAU1977_REG_DIAG_IRQ2 0x16
#define ADAU1977_REG_ADJUST1 0x17
#define ADAU1977_REG_ADJUST2 0x18
#define ADAU1977_REG_ADC_CLIP 0x19
#define ADAU1977_REG_DC_HPF_CAL 0x1a
#define ADAU1977_POWER_RESET BIT(7)
#define ADAU1977_POWER_PWUP BIT(0)
#define ADAU1977_PLL_CLK_S BIT(4)
#define ADAU1977_PLL_MCS_MASK 0x7
#define ADAU1977_MICBIAS_MB_VOLTS_MASK 0xf0
#define ADAU1977_MICBIAS_MB_VOLTS_OFFSET 4
#define ADAU1977_BLOCK_POWER_SAI_LR_POL BIT(7)
#define ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE BIT(6)
#define ADAU1977_BLOCK_POWER_SAI_LDO_EN BIT(5)
#define ADAU1977_SAI_CTRL0_FMT_MASK (0x3 << 6)
#define ADAU1977_SAI_CTRL0_FMT_I2S (0x0 << 6)
#define ADAU1977_SAI_CTRL0_FMT_LJ (0x1 << 6)
#define ADAU1977_SAI_CTRL0_FMT_RJ_24BIT (0x2 << 6)
#define ADAU1977_SAI_CTRL0_FMT_RJ_16BIT (0x3 << 6)
#define ADAU1977_SAI_CTRL0_SAI_MASK (0x7 << 3)
#define ADAU1977_SAI_CTRL0_SAI_I2S (0x0 << 3)
#define ADAU1977_SAI_CTRL0_SAI_TDM_2 (0x1 << 3)
#define ADAU1977_SAI_CTRL0_SAI_TDM_4 (0x2 << 3)
#define ADAU1977_SAI_CTRL0_SAI_TDM_8 (0x3 << 3)
#define ADAU1977_SAI_CTRL0_SAI_TDM_16 (0x4 << 3)
#define ADAU1977_SAI_CTRL0_FS_MASK (0x7)
#define ADAU1977_SAI_CTRL0_FS_8000_12000 (0x0)
#define ADAU1977_SAI_CTRL0_FS_16000_24000 (0x1)
#define ADAU1977_SAI_CTRL0_FS_32000_48000 (0x2)
#define ADAU1977_SAI_CTRL0_FS_64000_96000 (0x3)
#define ADAU1977_SAI_CTRL0_FS_128000_192000 (0x4)
#define ADAU1977_SAI_CTRL1_SLOT_WIDTH_MASK (0x3 << 5)
#define ADAU1977_SAI_CTRL1_SLOT_WIDTH_32 (0x0 << 5)
#define ADAU1977_SAI_CTRL1_SLOT_WIDTH_24 (0x1 << 5)
#define ADAU1977_SAI_CTRL1_SLOT_WIDTH_16 (0x2 << 5)
#define ADAU1977_SAI_CTRL1_DATA_WIDTH_MASK (0x1 << 4)
#define ADAU1977_SAI_CTRL1_DATA_WIDTH_16BIT (0x1 << 4)
#define ADAU1977_SAI_CTRL1_DATA_WIDTH_24BIT (0x0 << 4)
#define ADAU1977_SAI_CTRL1_LRCLK_PULSE BIT(3)
#define ADAU1977_SAI_CTRL1_MSB BIT(2)
#define ADAU1977_SAI_CTRL1_BCLKRATE_16 (0x1 << 1)
#define ADAU1977_SAI_CTRL1_BCLKRATE_32 (0x0 << 1)
#define ADAU1977_SAI_CTRL1_BCLKRATE_MASK (0x1 << 1)
#define ADAU1977_SAI_CTRL1_MASTER BIT(0)
#define ADAU1977_SAI_OVERTEMP_DRV_C(x) BIT(4 + (x))
#define ADAU1977_SAI_OVERTEMP_DRV_HIZ BIT(3)
#define ADAU1977_MISC_CONTROL_SUM_MODE_MASK (0x3 << 6)
#define ADAU1977_MISC_CONTROL_SUM_MODE_1CH (0x2 << 6)
#define ADAU1977_MISC_CONTROL_SUM_MODE_2CH (0x1 << 6)
#define ADAU1977_MISC_CONTROL_SUM_MODE_4CH (0x0 << 6)
#define ADAU1977_MISC_CONTROL_MMUTE BIT(4)
#define ADAU1977_MISC_CONTROL_DC_CAL BIT(0)
#define ADAU1977_CHAN_MAP_SECOND_SLOT_OFFSET 4
#define ADAU1977_CHAN_MAP_FIRST_SLOT_OFFSET 0
struct adau1977 {
struct regmap *regmap;
bool right_j;
unsigned int sysclk;
enum adau1977_sysclk_src sysclk_src;
struct gpio_desc *reset_gpio;
enum adau1977_type type;
struct regulator *avdd_reg;
struct regulator *dvdd_reg;
struct snd_pcm_hw_constraint_list constraints;
struct device *dev;
void (*switch_mode)(struct device *dev);
unsigned int max_clock_provider_fs;
unsigned int slot_width;
bool enabled;
bool clock_provider;
};
static const struct reg_default adau1977_reg_defaults[] = {
{ 0x00, 0x00 },
{ 0x01, 0x41 },
{ 0x02, 0x4a },
{ 0x03, 0x7d },
{ 0x04, 0x3d },
{ 0x05, 0x02 },
{ 0x06, 0x00 },
{ 0x07, 0x10 },
{ 0x08, 0x32 },
{ 0x09, 0xf0 },
{ 0x0a, 0xa0 },
{ 0x0b, 0xa0 },
{ 0x0c, 0xa0 },
{ 0x0d, 0xa0 },
{ 0x0e, 0x02 },
{ 0x10, 0x0f },
{ 0x15, 0x20 },
{ 0x16, 0x00 },
{ 0x17, 0x00 },
{ 0x18, 0x00 },
{ 0x1a, 0x00 },
};
static const DECLARE_TLV_DB_MINMAX_MUTE(adau1977_adc_gain, -3562, 6000);
static const struct snd_soc_dapm_widget adau1977_micbias_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("MICBIAS", ADAU1977_REG_MICBIAS,
3, 0, NULL, 0)
};
static const struct snd_soc_dapm_widget adau1977_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("Vref", ADAU1977_REG_BLOCK_POWER_SAI,
4, 0, NULL, 0),
SND_SOC_DAPM_ADC("ADC1", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 0, 0),
SND_SOC_DAPM_ADC("ADC2", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 1, 0),
SND_SOC_DAPM_ADC("ADC3", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 2, 0),
SND_SOC_DAPM_ADC("ADC4", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 3, 0),
SND_SOC_DAPM_INPUT("AIN1"),
SND_SOC_DAPM_INPUT("AIN2"),
SND_SOC_DAPM_INPUT("AIN3"),
SND_SOC_DAPM_INPUT("AIN4"),
SND_SOC_DAPM_OUTPUT("VREF"),
};
static const struct snd_soc_dapm_route adau1977_dapm_routes[] = {
{ "ADC1", NULL, "AIN1" },
{ "ADC2", NULL, "AIN2" },
{ "ADC3", NULL, "AIN3" },
{ "ADC4", NULL, "AIN4" },
{ "ADC1", NULL, "Vref" },
{ "ADC2", NULL, "Vref" },
{ "ADC3", NULL, "Vref" },
{ "ADC4", NULL, "Vref" },
{ "VREF", NULL, "Vref" },
};
#define ADAU1977_VOLUME(x) \
SOC_SINGLE_TLV("ADC" #x " Capture Volume", \
ADAU1977_REG_POST_ADC_GAIN((x) - 1), \
0, 255, 1, adau1977_adc_gain)
#define ADAU1977_HPF_SWITCH(x) \
SOC_SINGLE("ADC" #x " Highpass-Filter Capture Switch", \
ADAU1977_REG_DC_HPF_CAL, (x) - 1, 1, 0)
#define ADAU1977_DC_SUB_SWITCH(x) \
SOC_SINGLE("ADC" #x " DC Subtraction Capture Switch", \
ADAU1977_REG_DC_HPF_CAL, (x) + 3, 1, 0)
static const struct snd_kcontrol_new adau1977_snd_controls[] = {
ADAU1977_VOLUME(1),
ADAU1977_VOLUME(2),
ADAU1977_VOLUME(3),
ADAU1977_VOLUME(4),
ADAU1977_HPF_SWITCH(1),
ADAU1977_HPF_SWITCH(2),
ADAU1977_HPF_SWITCH(3),
ADAU1977_HPF_SWITCH(4),
ADAU1977_DC_SUB_SWITCH(1),
ADAU1977_DC_SUB_SWITCH(2),
ADAU1977_DC_SUB_SWITCH(3),
ADAU1977_DC_SUB_SWITCH(4),
};
static int adau1977_reset(struct adau1977 *adau1977)
{
int ret;
/*
* The reset bit is obviously volatile, but we need to be able to cache
* the other bits in the register, so we can't just mark the whole
* register as volatile. Since this is the only place where we'll ever
* touch the reset bit just bypass the cache for this operation.
*/
regcache_cache_bypass(adau1977->regmap, true);
ret = regmap_write(adau1977->regmap, ADAU1977_REG_POWER,
ADAU1977_POWER_RESET);
regcache_cache_bypass(adau1977->regmap, false);
return ret;
}
/*
* Returns the appropriate setting for ths FS field in the CTRL0 register
* depending on the rate.
*/
static int adau1977_lookup_fs(unsigned int rate)
{
if (rate >= 8000 && rate <= 12000)
return ADAU1977_SAI_CTRL0_FS_8000_12000;
else if (rate >= 16000 && rate <= 24000)
return ADAU1977_SAI_CTRL0_FS_16000_24000;
else if (rate >= 32000 && rate <= 48000)
return ADAU1977_SAI_CTRL0_FS_32000_48000;
else if (rate >= 64000 && rate <= 96000)
return ADAU1977_SAI_CTRL0_FS_64000_96000;
else if (rate >= 128000 && rate <= 192000)
return ADAU1977_SAI_CTRL0_FS_128000_192000;
else
return -EINVAL;
}
static int adau1977_lookup_mcs(struct adau1977 *adau1977, unsigned int rate,
unsigned int fs)
{
unsigned int mcs;
/*
* rate = sysclk / (512 * mcs_lut[mcs]) * 2**fs
* => mcs_lut[mcs] = sysclk / (512 * rate) * 2**fs
* => mcs_lut[mcs] = sysclk / ((512 / 2**fs) * rate)
*/
rate *= 512 >> fs;
if (adau1977->sysclk % rate != 0)
return -EINVAL;
mcs = adau1977->sysclk / rate;
/* The factors configured by MCS are 1, 2, 3, 4, 6 */
if (mcs < 1 || mcs > 6 || mcs == 5)
return -EINVAL;
mcs = mcs - 1;
if (mcs == 5)
mcs = 4;
return mcs;
}
static int adau1977_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct adau1977 *adau1977 = snd_soc_component_get_drvdata(component);
unsigned int rate = params_rate(params);
unsigned int slot_width;
unsigned int ctrl0, ctrl0_mask;
unsigned int ctrl1;
int mcs, fs;
int ret;
fs = adau1977_lookup_fs(rate);
if (fs < 0)
return fs;
if (adau1977->sysclk_src == ADAU1977_SYSCLK_SRC_MCLK) {
mcs = adau1977_lookup_mcs(adau1977, rate, fs);
if (mcs < 0)
return mcs;
} else {
mcs = 0;
}
ctrl0_mask = ADAU1977_SAI_CTRL0_FS_MASK;
ctrl0 = fs;
if (adau1977->right_j) {
switch (params_width(params)) {
case 16:
ctrl0 |= ADAU1977_SAI_CTRL0_FMT_RJ_16BIT;
break;
case 24:
ctrl0 |= ADAU1977_SAI_CTRL0_FMT_RJ_24BIT;
break;
default:
return -EINVAL;
}
ctrl0_mask |= ADAU1977_SAI_CTRL0_FMT_MASK;
}
if (adau1977->clock_provider) {
switch (params_width(params)) {
case 16:
ctrl1 = ADAU1977_SAI_CTRL1_DATA_WIDTH_16BIT;
slot_width = 16;
break;
case 24:
case 32:
ctrl1 = ADAU1977_SAI_CTRL1_DATA_WIDTH_24BIT;
slot_width = 32;
break;
default:
return -EINVAL;
}
/* In TDM mode there is a fixed slot width */
if (adau1977->slot_width)
slot_width = adau1977->slot_width;
if (slot_width == 16)
ctrl1 |= ADAU1977_SAI_CTRL1_BCLKRATE_16;
else
ctrl1 |= ADAU1977_SAI_CTRL1_BCLKRATE_32;
ret = regmap_update_bits(adau1977->regmap,
ADAU1977_REG_SAI_CTRL1,
ADAU1977_SAI_CTRL1_DATA_WIDTH_MASK |
ADAU1977_SAI_CTRL1_BCLKRATE_MASK,
ctrl1);
if (ret < 0)
return ret;
}
ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL0,
ctrl0_mask, ctrl0);
if (ret < 0)
return ret;
return regmap_update_bits(adau1977->regmap, ADAU1977_REG_PLL,
ADAU1977_PLL_MCS_MASK, mcs);
}
static int adau1977_power_disable(struct adau1977 *adau1977)
{
int ret = 0;
if (!adau1977->enabled)
return 0;
ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_POWER,
ADAU1977_POWER_PWUP, 0);
if (ret)
return ret;
regcache_mark_dirty(adau1977->regmap);
gpiod_set_value_cansleep(adau1977->reset_gpio, 0);
regcache_cache_only(adau1977->regmap, true);
regulator_disable(adau1977->avdd_reg);
if (adau1977->dvdd_reg)
regulator_disable(adau1977->dvdd_reg);
adau1977->enabled = false;
return 0;
}
static int adau1977_power_enable(struct adau1977 *adau1977)
{
unsigned int val;
int ret = 0;
if (adau1977->enabled)
return 0;
ret = regulator_enable(adau1977->avdd_reg);
if (ret)
return ret;
if (adau1977->dvdd_reg) {
ret = regulator_enable(adau1977->dvdd_reg);
if (ret)
goto err_disable_avdd;
}
gpiod_set_value_cansleep(adau1977->reset_gpio, 1);
regcache_cache_only(adau1977->regmap, false);
if (adau1977->switch_mode)
adau1977->switch_mode(adau1977->dev);
ret = adau1977_reset(adau1977);
if (ret)
goto err_disable_dvdd;
ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_POWER,
ADAU1977_POWER_PWUP, ADAU1977_POWER_PWUP);
if (ret)
goto err_disable_dvdd;
ret = regcache_sync(adau1977->regmap);
if (ret)
goto err_disable_dvdd;
/*
* The PLL register is not affected by the software reset. It is
* possible that the value of the register was changed to the
* default value while we were in cache only mode. In this case
* regcache_sync will skip over it and we have to manually sync
* it.
*/
ret = regmap_read(adau1977->regmap, ADAU1977_REG_PLL, &val);
if (ret)
goto err_disable_dvdd;
if (val == 0x41) {
regcache_cache_bypass(adau1977->regmap, true);
ret = regmap_write(adau1977->regmap, ADAU1977_REG_PLL,
0x41);
if (ret)
goto err_disable_dvdd;
regcache_cache_bypass(adau1977->regmap, false);
}
adau1977->enabled = true;
return ret;
err_disable_dvdd:
if (adau1977->dvdd_reg)
regulator_disable(adau1977->dvdd_reg);
err_disable_avdd:
regulator_disable(adau1977->avdd_reg);
return ret;
}
static int adau1977_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct adau1977 *adau1977 = snd_soc_component_get_drvdata(component);
int ret = 0;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
ret = adau1977_power_enable(adau1977);
break;
case SND_SOC_BIAS_OFF:
ret = adau1977_power_disable(adau1977);
break;
}
return ret;
}
static int adau1977_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int width)
{
struct adau1977 *adau1977 = snd_soc_component_get_drvdata(dai->component);
unsigned int ctrl0, ctrl1, drv;
unsigned int slot[4];
unsigned int i;
int ret;
if (slots == 0) {
/* 0 = No fixed slot width */
adau1977->slot_width = 0;
adau1977->max_clock_provider_fs = 192000;
return regmap_update_bits(adau1977->regmap,
ADAU1977_REG_SAI_CTRL0, ADAU1977_SAI_CTRL0_SAI_MASK,
ADAU1977_SAI_CTRL0_SAI_I2S);
}
if (rx_mask == 0 || tx_mask != 0)
return -EINVAL;
drv = 0;
for (i = 0; i < 4; i++) {
slot[i] = __ffs(rx_mask);
drv |= ADAU1977_SAI_OVERTEMP_DRV_C(i);
rx_mask &= ~(1 << slot[i]);
if (slot[i] >= slots)
return -EINVAL;
if (rx_mask == 0)
break;
}
if (rx_mask != 0)
return -EINVAL;
switch (width) {
case 16:
ctrl1 = ADAU1977_SAI_CTRL1_SLOT_WIDTH_16;
break;
case 24:
/* We can only generate 16 bit or 32 bit wide slots */
if (adau1977->clock_provider)
return -EINVAL;
ctrl1 = ADAU1977_SAI_CTRL1_SLOT_WIDTH_24;
break;
case 32:
ctrl1 = ADAU1977_SAI_CTRL1_SLOT_WIDTH_32;
break;
default:
return -EINVAL;
}
switch (slots) {
case 2:
ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_2;
break;
case 4:
ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_4;
break;
case 8:
ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_8;
break;
case 16:
ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_16;
break;
default:
return -EINVAL;
}
ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_OVERTEMP,
ADAU1977_SAI_OVERTEMP_DRV_C(0) |
ADAU1977_SAI_OVERTEMP_DRV_C(1) |
ADAU1977_SAI_OVERTEMP_DRV_C(2) |
ADAU1977_SAI_OVERTEMP_DRV_C(3), drv);
if (ret)
return ret;
ret = regmap_write(adau1977->regmap, ADAU1977_REG_CMAP12,
(slot[1] << ADAU1977_CHAN_MAP_SECOND_SLOT_OFFSET) |
(slot[0] << ADAU1977_CHAN_MAP_FIRST_SLOT_OFFSET));
if (ret)
return ret;
ret = regmap_write(adau1977->regmap, ADAU1977_REG_CMAP34,
(slot[3] << ADAU1977_CHAN_MAP_SECOND_SLOT_OFFSET) |
(slot[2] << ADAU1977_CHAN_MAP_FIRST_SLOT_OFFSET));
if (ret)
return ret;
ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL0,
ADAU1977_SAI_CTRL0_SAI_MASK, ctrl0);
if (ret)
return ret;
ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL1,
ADAU1977_SAI_CTRL1_SLOT_WIDTH_MASK, ctrl1);
if (ret)
return ret;
adau1977->slot_width = width;
/* In clock provider mode the maximum bitclock is 24.576 MHz */
adau1977->max_clock_provider_fs = min(192000, 24576000 / width / slots);
return 0;
}
static int adau1977_mute(struct snd_soc_dai *dai, int mute, int stream)
{
struct adau1977 *adau1977 = snd_soc_component_get_drvdata(dai->component);
unsigned int val;
if (mute)
val = ADAU1977_MISC_CONTROL_MMUTE;
else
val = 0;
return regmap_update_bits(adau1977->regmap, ADAU1977_REG_MISC_CONTROL,
ADAU1977_MISC_CONTROL_MMUTE, val);
}
static int adau1977_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct adau1977 *adau1977 = snd_soc_component_get_drvdata(dai->component);
unsigned int ctrl0 = 0, ctrl1 = 0, block_power = 0;
bool invert_lrclk;
int ret;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC:
adau1977->clock_provider = false;
break;
case SND_SOC_DAIFMT_CBP_CFP:
ctrl1 |= ADAU1977_SAI_CTRL1_MASTER;
adau1977->clock_provider = true;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
invert_lrclk = false;
break;
case SND_SOC_DAIFMT_IB_NF:
block_power |= ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE;
invert_lrclk = false;
break;
case SND_SOC_DAIFMT_NB_IF:
invert_lrclk = true;
break;
case SND_SOC_DAIFMT_IB_IF:
block_power |= ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE;
invert_lrclk = true;
break;
default:
return -EINVAL;
}
adau1977->right_j = false;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
ctrl0 |= ADAU1977_SAI_CTRL0_FMT_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
ctrl0 |= ADAU1977_SAI_CTRL0_FMT_LJ;
invert_lrclk = !invert_lrclk;
break;
case SND_SOC_DAIFMT_RIGHT_J:
ctrl0 |= ADAU1977_SAI_CTRL0_FMT_RJ_24BIT;
adau1977->right_j = true;
invert_lrclk = !invert_lrclk;
break;
case SND_SOC_DAIFMT_DSP_A:
ctrl1 |= ADAU1977_SAI_CTRL1_LRCLK_PULSE;
ctrl0 |= ADAU1977_SAI_CTRL0_FMT_I2S;
invert_lrclk = false;
break;
case SND_SOC_DAIFMT_DSP_B:
ctrl1 |= ADAU1977_SAI_CTRL1_LRCLK_PULSE;
ctrl0 |= ADAU1977_SAI_CTRL0_FMT_LJ;
invert_lrclk = false;
break;
default:
return -EINVAL;
}
if (invert_lrclk)
block_power |= ADAU1977_BLOCK_POWER_SAI_LR_POL;
ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_BLOCK_POWER_SAI,
ADAU1977_BLOCK_POWER_SAI_LR_POL |
ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE, block_power);
if (ret)
return ret;
ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL0,
ADAU1977_SAI_CTRL0_FMT_MASK,
ctrl0);
if (ret)
return ret;
return regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL1,
ADAU1977_SAI_CTRL1_MASTER | ADAU1977_SAI_CTRL1_LRCLK_PULSE,
ctrl1);
}
static int adau1977_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct adau1977 *adau1977 = snd_soc_component_get_drvdata(dai->component);
u64 formats = 0;
if (adau1977->slot_width == 16)
formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE;
else if (adau1977->right_j || adau1977->slot_width == 24)
formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE;
snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE, &adau1977->constraints);
if (adau1977->clock_provider)
snd_pcm_hw_constraint_minmax(substream->runtime,
SNDRV_PCM_HW_PARAM_RATE, 8000,
adau1977->max_clock_provider_fs);
if (formats != 0)
snd_pcm_hw_constraint_mask64(substream->runtime,
SNDRV_PCM_HW_PARAM_FORMAT, formats);
return 0;
}
static int adau1977_set_tristate(struct snd_soc_dai *dai, int tristate)
{
struct adau1977 *adau1977 = snd_soc_component_get_drvdata(dai->component);
unsigned int val;
if (tristate)
val = ADAU1977_SAI_OVERTEMP_DRV_HIZ;
else
val = 0;
return regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_OVERTEMP,
ADAU1977_SAI_OVERTEMP_DRV_HIZ, val);
}
static const struct snd_soc_dai_ops adau1977_dai_ops = {
.startup = adau1977_startup,
.hw_params = adau1977_hw_params,
.mute_stream = adau1977_mute,
.set_fmt = adau1977_set_dai_fmt,
.set_tdm_slot = adau1977_set_tdm_slot,
.set_tristate = adau1977_set_tristate,
};
static struct snd_soc_dai_driver adau1977_dai = {
.name = "adau1977-hifi",
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 4,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S32_LE,
.sig_bits = 24,
},
.ops = &adau1977_dai_ops,
};
static const unsigned int adau1977_rates[] = {
8000, 16000, 32000, 64000, 128000,
11025, 22050, 44100, 88200, 172400,
12000, 24000, 48000, 96000, 192000,
};
#define ADAU1977_RATE_CONSTRAINT_MASK_32000 0x001f
#define ADAU1977_RATE_CONSTRAINT_MASK_44100 0x03e0
#define ADAU1977_RATE_CONSTRAINT_MASK_48000 0x7c00
/* All rates >= 32000 */
#define ADAU1977_RATE_CONSTRAINT_MASK_LRCLK 0x739c
static bool adau1977_check_sysclk(unsigned int mclk, unsigned int base_freq)
{
unsigned int mcs;
if (mclk % (base_freq * 128) != 0)
return false;
mcs = mclk / (128 * base_freq);
if (mcs < 1 || mcs > 6 || mcs == 5)
return false;
return true;
}
static int adau1977_set_sysclk(struct snd_soc_component *component,
int clk_id, int source, unsigned int freq, int dir)
{
struct adau1977 *adau1977 = snd_soc_component_get_drvdata(component);
unsigned int mask = 0;
unsigned int clk_src;
unsigned int ret;
if (dir != SND_SOC_CLOCK_IN)
return -EINVAL;
if (clk_id != ADAU1977_SYSCLK)
return -EINVAL;
switch (source) {
case ADAU1977_SYSCLK_SRC_MCLK:
clk_src = 0;
break;
case ADAU1977_SYSCLK_SRC_LRCLK:
clk_src = ADAU1977_PLL_CLK_S;
break;
default:
return -EINVAL;
}
if (freq != 0 && source == ADAU1977_SYSCLK_SRC_MCLK) {
if (freq < 4000000 || freq > 36864000)
return -EINVAL;
if (adau1977_check_sysclk(freq, 32000))
mask |= ADAU1977_RATE_CONSTRAINT_MASK_32000;
if (adau1977_check_sysclk(freq, 44100))
mask |= ADAU1977_RATE_CONSTRAINT_MASK_44100;
if (adau1977_check_sysclk(freq, 48000))
mask |= ADAU1977_RATE_CONSTRAINT_MASK_48000;
if (mask == 0)
return -EINVAL;
} else if (source == ADAU1977_SYSCLK_SRC_LRCLK) {
mask = ADAU1977_RATE_CONSTRAINT_MASK_LRCLK;
}
ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_PLL,
ADAU1977_PLL_CLK_S, clk_src);
if (ret)
return ret;
adau1977->constraints.mask = mask;
adau1977->sysclk_src = source;
adau1977->sysclk = freq;
return 0;
}
static int adau1977_component_probe(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct adau1977 *adau1977 = snd_soc_component_get_drvdata(component);
int ret;
switch (adau1977->type) {
case ADAU1977:
ret = snd_soc_dapm_new_controls(dapm,
adau1977_micbias_dapm_widgets,
ARRAY_SIZE(adau1977_micbias_dapm_widgets));
if (ret < 0)
return ret;
break;
default:
break;
}
return 0;
}
static const struct snd_soc_component_driver adau1977_component_driver = {
.probe = adau1977_component_probe,
.set_bias_level = adau1977_set_bias_level,
.set_sysclk = adau1977_set_sysclk,
.controls = adau1977_snd_controls,
.num_controls = ARRAY_SIZE(adau1977_snd_controls),
.dapm_widgets = adau1977_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(adau1977_dapm_widgets),
.dapm_routes = adau1977_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(adau1977_dapm_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
static int adau1977_setup_micbias(struct adau1977 *adau1977)
{
unsigned int micbias;
if (device_property_read_u32(adau1977->dev, "adi,micbias", &micbias))
micbias = ADAU1977_MICBIAS_8V5;
if (micbias > ADAU1977_MICBIAS_9V0) {
dev_err(adau1977->dev, "Invalid value for 'adi,micbias'\n");
return -EINVAL;
}
return regmap_update_bits(adau1977->regmap, ADAU1977_REG_MICBIAS,
ADAU1977_MICBIAS_MB_VOLTS_MASK,
micbias << ADAU1977_MICBIAS_MB_VOLTS_OFFSET);
}
int adau1977_probe(struct device *dev, struct regmap *regmap,
enum adau1977_type type, void (*switch_mode)(struct device *dev))
{
unsigned int power_off_mask;
struct adau1977 *adau1977;
int ret;
if (IS_ERR(regmap))
return PTR_ERR(regmap);
adau1977 = devm_kzalloc(dev, sizeof(*adau1977), GFP_KERNEL);
if (adau1977 == NULL)
return -ENOMEM;
adau1977->dev = dev;
adau1977->type = type;
adau1977->regmap = regmap;
adau1977->switch_mode = switch_mode;
adau1977->max_clock_provider_fs = 192000;
adau1977->constraints.list = adau1977_rates;
adau1977->constraints.count = ARRAY_SIZE(adau1977_rates);
adau1977->avdd_reg = devm_regulator_get(dev, "AVDD");
if (IS_ERR(adau1977->avdd_reg))
return PTR_ERR(adau1977->avdd_reg);
adau1977->dvdd_reg = devm_regulator_get_optional(dev, "DVDD");
if (IS_ERR(adau1977->dvdd_reg)) {
if (PTR_ERR(adau1977->dvdd_reg) != -ENODEV)
return PTR_ERR(adau1977->dvdd_reg);
adau1977->dvdd_reg = NULL;
}
adau1977->reset_gpio = devm_gpiod_get_optional(dev, "reset",
GPIOD_OUT_LOW);
if (IS_ERR(adau1977->reset_gpio))
return PTR_ERR(adau1977->reset_gpio);
dev_set_drvdata(dev, adau1977);
if (adau1977->reset_gpio)
ndelay(100);
ret = adau1977_power_enable(adau1977);
if (ret)
return ret;
if (type == ADAU1977) {
ret = adau1977_setup_micbias(adau1977);
if (ret)
goto err_poweroff;
}
if (adau1977->dvdd_reg)
power_off_mask = ~0;
else
power_off_mask = (unsigned int)~ADAU1977_BLOCK_POWER_SAI_LDO_EN;
ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_BLOCK_POWER_SAI,
power_off_mask, 0x00);
if (ret)
goto err_poweroff;
ret = adau1977_power_disable(adau1977);
if (ret)
return ret;
return devm_snd_soc_register_component(dev, &adau1977_component_driver,
&adau1977_dai, 1);
err_poweroff:
adau1977_power_disable(adau1977);
return ret;
}
EXPORT_SYMBOL_GPL(adau1977_probe);
static bool adau1977_register_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case ADAU1977_REG_STATUS(0):
case ADAU1977_REG_STATUS(1):
case ADAU1977_REG_STATUS(2):
case ADAU1977_REG_STATUS(3):
case ADAU1977_REG_ADC_CLIP:
return true;
}
return false;
}
const struct regmap_config adau1977_regmap_config = {
.max_register = ADAU1977_REG_DC_HPF_CAL,
.volatile_reg = adau1977_register_volatile,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = adau1977_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(adau1977_reg_defaults),
};
EXPORT_SYMBOL_GPL(adau1977_regmap_config);
MODULE_DESCRIPTION("ASoC ADAU1977/ADAU1978/ADAU1979 driver");
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/adau1977.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ALSA SoC Texas Instruments TLV320DAC33 codec driver
*
* Author: Peter Ujfalusi <[email protected]>
*
* Copyright: (C) 2009 Nokia Corporation
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/gpio.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/tlv320dac33-plat.h>
#include "tlv320dac33.h"
/*
* The internal FIFO is 24576 bytes long
* It can be configured to hold 16bit or 24bit samples
* In 16bit configuration the FIFO can hold 6144 stereo samples
* In 24bit configuration the FIFO can hold 4096 stereo samples
*/
#define DAC33_FIFO_SIZE_16BIT 6144
#define DAC33_FIFO_SIZE_24BIT 4096
#define DAC33_MODE7_MARGIN 10 /* Safety margin for FIFO in Mode7 */
#define BURST_BASEFREQ_HZ 49152000
#define SAMPLES_TO_US(rate, samples) \
(1000000000 / (((rate) * 1000) / (samples)))
#define US_TO_SAMPLES(rate, us) \
((rate) / (1000000 / ((us) < 1000000 ? (us) : 1000000)))
#define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \
(((samples)*5000) / (((burstrate)*5000) / ((burstrate) - (playrate))))
static void dac33_calculate_times(struct snd_pcm_substream *substream,
struct snd_soc_component *component);
static int dac33_prepare_chip(struct snd_pcm_substream *substream,
struct snd_soc_component *component);
enum dac33_state {
DAC33_IDLE = 0,
DAC33_PREFILL,
DAC33_PLAYBACK,
DAC33_FLUSH,
};
enum dac33_fifo_modes {
DAC33_FIFO_BYPASS = 0,
DAC33_FIFO_MODE1,
DAC33_FIFO_MODE7,
DAC33_FIFO_LAST_MODE,
};
#define DAC33_NUM_SUPPLIES 3
static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
"AVDD",
"DVDD",
"IOVDD",
};
struct tlv320dac33_priv {
struct mutex mutex;
struct work_struct work;
struct snd_soc_component *component;
struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
struct snd_pcm_substream *substream;
int power_gpio;
int chip_power;
int irq;
unsigned int refclk;
unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */
enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
unsigned int fifo_size; /* Size of the FIFO in samples */
unsigned int nsample; /* burst read amount from host */
int mode1_latency; /* latency caused by the i2c writes in
* us */
u8 burst_bclkdiv; /* BCLK divider value in burst mode */
u8 *reg_cache;
unsigned int burst_rate; /* Interface speed in Burst modes */
int keep_bclk; /* Keep the BCLK continuously running
* in FIFO modes */
spinlock_t lock;
unsigned long long t_stamp1; /* Time stamp for FIFO modes to */
unsigned long long t_stamp2; /* calculate the FIFO caused delay */
unsigned int mode1_us_burst; /* Time to burst read n number of
* samples */
unsigned int mode7_us_to_lthr; /* Time to reach lthr from uthr */
unsigned int uthr;
enum dac33_state state;
struct i2c_client *i2c;
};
static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
0x00, 0x00, /* 0x38 - 0x39 */
/* Registers 0x3a - 0x3f are reserved */
0x00, 0x00, /* 0x3a - 0x3b */
0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
0x00, 0x80, /* 0x44 - 0x45 */
/* Registers 0x46 - 0x47 are reserved */
0x80, 0x80, /* 0x46 - 0x47 */
0x80, 0x00, 0x00, /* 0x48 - 0x4a */
/* Registers 0x4b - 0x7c are reserved */
0x00, /* 0x4b */
0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
0x00, /* 0x7c */
0xda, 0x33, 0x03, /* 0x7d - 0x7f */
};
/* Register read and write */
static inline unsigned int dac33_read_reg_cache(struct snd_soc_component *component,
unsigned reg)
{
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
u8 *cache = dac33->reg_cache;
if (reg >= DAC33_CACHEREGNUM)
return 0;
return cache[reg];
}
static inline void dac33_write_reg_cache(struct snd_soc_component *component,
u8 reg, u8 value)
{
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
u8 *cache = dac33->reg_cache;
if (reg >= DAC33_CACHEREGNUM)
return;
cache[reg] = value;
}
static int dac33_read(struct snd_soc_component *component, unsigned int reg,
u8 *value)
{
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
int val, ret = 0;
*value = reg & 0xff;
/* If powered off, return the cached value */
if (dac33->chip_power) {
val = i2c_smbus_read_byte_data(dac33->i2c, value[0]);
if (val < 0) {
dev_err(component->dev, "Read failed (%d)\n", val);
value[0] = dac33_read_reg_cache(component, reg);
ret = val;
} else {
value[0] = val;
dac33_write_reg_cache(component, reg, val);
}
} else {
value[0] = dac33_read_reg_cache(component, reg);
}
return ret;
}
static int dac33_write(struct snd_soc_component *component, unsigned int reg,
unsigned int value)
{
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
u8 data[2];
int ret = 0;
/*
* data is
* D15..D8 dac33 register offset
* D7...D0 register data
*/
data[0] = reg & 0xff;
data[1] = value & 0xff;
dac33_write_reg_cache(component, data[0], data[1]);
if (dac33->chip_power) {
ret = i2c_master_send(dac33->i2c, data, 2);
if (ret != 2)
dev_err(component->dev, "Write failed (%d)\n", ret);
else
ret = 0;
}
return ret;
}
static int dac33_write_locked(struct snd_soc_component *component, unsigned int reg,
unsigned int value)
{
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
int ret;
mutex_lock(&dac33->mutex);
ret = dac33_write(component, reg, value);
mutex_unlock(&dac33->mutex);
return ret;
}
#define DAC33_I2C_ADDR_AUTOINC 0x80
static int dac33_write16(struct snd_soc_component *component, unsigned int reg,
unsigned int value)
{
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
u8 data[3];
int ret = 0;
/*
* data is
* D23..D16 dac33 register offset
* D15..D8 register data MSB
* D7...D0 register data LSB
*/
data[0] = reg & 0xff;
data[1] = (value >> 8) & 0xff;
data[2] = value & 0xff;
dac33_write_reg_cache(component, data[0], data[1]);
dac33_write_reg_cache(component, data[0] + 1, data[2]);
if (dac33->chip_power) {
/* We need to set autoincrement mode for 16 bit writes */
data[0] |= DAC33_I2C_ADDR_AUTOINC;
ret = i2c_master_send(dac33->i2c, data, 3);
if (ret != 3)
dev_err(component->dev, "Write failed (%d)\n", ret);
else
ret = 0;
}
return ret;
}
static void dac33_init_chip(struct snd_soc_component *component)
{
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
if (unlikely(!dac33->chip_power))
return;
/* A : DAC sample rate Fsref/1.5 */
dac33_write(component, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
/* B : DAC src=normal, not muted */
dac33_write(component, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
DAC33_DACSRCL_LEFT);
/* C : (defaults) */
dac33_write(component, DAC33_DAC_CTRL_C, 0x00);
/* 73 : volume soft stepping control,
clock source = internal osc (?) */
dac33_write(component, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
/* Restore only selected registers (gains mostly) */
dac33_write(component, DAC33_LDAC_DIG_VOL_CTRL,
dac33_read_reg_cache(component, DAC33_LDAC_DIG_VOL_CTRL));
dac33_write(component, DAC33_RDAC_DIG_VOL_CTRL,
dac33_read_reg_cache(component, DAC33_RDAC_DIG_VOL_CTRL));
dac33_write(component, DAC33_LINEL_TO_LLO_VOL,
dac33_read_reg_cache(component, DAC33_LINEL_TO_LLO_VOL));
dac33_write(component, DAC33_LINER_TO_RLO_VOL,
dac33_read_reg_cache(component, DAC33_LINER_TO_RLO_VOL));
dac33_write(component, DAC33_OUT_AMP_CTRL,
dac33_read_reg_cache(component, DAC33_OUT_AMP_CTRL));
dac33_write(component, DAC33_LDAC_PWR_CTRL,
dac33_read_reg_cache(component, DAC33_LDAC_PWR_CTRL));
dac33_write(component, DAC33_RDAC_PWR_CTRL,
dac33_read_reg_cache(component, DAC33_RDAC_PWR_CTRL));
}
static inline int dac33_read_id(struct snd_soc_component *component)
{
int i, ret = 0;
u8 reg;
for (i = 0; i < 3; i++) {
ret = dac33_read(component, DAC33_DEVICE_ID_MSB + i, ®);
if (ret < 0)
break;
}
return ret;
}
static inline void dac33_soft_power(struct snd_soc_component *component, int power)
{
u8 reg;
reg = dac33_read_reg_cache(component, DAC33_PWR_CTRL);
if (power)
reg |= DAC33_PDNALLB;
else
reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
DAC33_DACRPDNB | DAC33_DACLPDNB);
dac33_write(component, DAC33_PWR_CTRL, reg);
}
static inline void dac33_disable_digital(struct snd_soc_component *component)
{
u8 reg;
/* Stop the DAI clock */
reg = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_B);
reg &= ~DAC33_BCLKON;
dac33_write(component, DAC33_SER_AUDIOIF_CTRL_B, reg);
/* Power down the Oscillator, and DACs */
reg = dac33_read_reg_cache(component, DAC33_PWR_CTRL);
reg &= ~(DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB);
dac33_write(component, DAC33_PWR_CTRL, reg);
}
static int dac33_hard_power(struct snd_soc_component *component, int power)
{
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
int ret = 0;
mutex_lock(&dac33->mutex);
/* Safety check */
if (unlikely(power == dac33->chip_power)) {
dev_dbg(component->dev, "Trying to set the same power state: %s\n",
power ? "ON" : "OFF");
goto exit;
}
if (power) {
ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
dac33->supplies);
if (ret != 0) {
dev_err(component->dev,
"Failed to enable supplies: %d\n", ret);
goto exit;
}
if (dac33->power_gpio >= 0)
gpio_set_value(dac33->power_gpio, 1);
dac33->chip_power = 1;
} else {
dac33_soft_power(component, 0);
if (dac33->power_gpio >= 0)
gpio_set_value(dac33->power_gpio, 0);
ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
dac33->supplies);
if (ret != 0) {
dev_err(component->dev,
"Failed to disable supplies: %d\n", ret);
goto exit;
}
dac33->chip_power = 0;
}
exit:
mutex_unlock(&dac33->mutex);
return ret;
}
static int dac33_playback_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
if (likely(dac33->substream)) {
dac33_calculate_times(dac33->substream, component);
dac33_prepare_chip(dac33->substream, component);
}
break;
case SND_SOC_DAPM_POST_PMD:
dac33_disable_digital(component);
break;
}
return 0;
}
static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
ucontrol->value.enumerated.item[0] = dac33->fifo_mode;
return 0;
}
static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
int ret = 0;
if (dac33->fifo_mode == ucontrol->value.enumerated.item[0])
return 0;
/* Do not allow changes while stream is running*/
if (snd_soc_component_active(component))
return -EPERM;
if (ucontrol->value.enumerated.item[0] >= DAC33_FIFO_LAST_MODE)
ret = -EINVAL;
else
dac33->fifo_mode = ucontrol->value.enumerated.item[0];
return ret;
}
/* Codec operation modes */
static const char *dac33_fifo_mode_texts[] = {
"Bypass", "Mode 1", "Mode 7"
};
static SOC_ENUM_SINGLE_EXT_DECL(dac33_fifo_mode_enum, dac33_fifo_mode_texts);
/* L/R Line Output Gain */
static const char *lr_lineout_gain_texts[] = {
"Line -12dB DAC 0dB", "Line -6dB DAC 6dB",
"Line 0dB DAC 12dB", "Line 6dB DAC 18dB",
};
static SOC_ENUM_SINGLE_DECL(l_lineout_gain_enum,
DAC33_LDAC_PWR_CTRL, 0,
lr_lineout_gain_texts);
static SOC_ENUM_SINGLE_DECL(r_lineout_gain_enum,
DAC33_RDAC_PWR_CTRL, 0,
lr_lineout_gain_texts);
/*
* DACL/R digital volume control:
* from 0 dB to -63.5 in 0.5 dB steps
* Need to be inverted later on:
* 0x00 == 0 dB
* 0x7f == -63.5 dB
*/
static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
static const struct snd_kcontrol_new dac33_snd_controls[] = {
SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
0, 0x7f, 1, dac_digivol_tlv),
SOC_DOUBLE_R("DAC Digital Playback Switch",
DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
SOC_DOUBLE_R("Line to Line Out Volume",
DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
SOC_ENUM("Left Line Output Gain", l_lineout_gain_enum),
SOC_ENUM("Right Line Output Gain", r_lineout_gain_enum),
};
static const struct snd_kcontrol_new dac33_mode_snd_controls[] = {
SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
dac33_get_fifo_mode, dac33_set_fifo_mode),
};
/* Analog bypass */
static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
/* LOP L/R invert selection */
static const char *dac33_lr_lom_texts[] = {"DAC", "LOP"};
static SOC_ENUM_SINGLE_DECL(dac33_left_lom_enum,
DAC33_OUT_AMP_CTRL, 3,
dac33_lr_lom_texts);
static const struct snd_kcontrol_new dac33_dapm_left_lom_control =
SOC_DAPM_ENUM("Route", dac33_left_lom_enum);
static SOC_ENUM_SINGLE_DECL(dac33_right_lom_enum,
DAC33_OUT_AMP_CTRL, 2,
dac33_lr_lom_texts);
static const struct snd_kcontrol_new dac33_dapm_right_lom_control =
SOC_DAPM_ENUM("Route", dac33_right_lom_enum);
static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
SND_SOC_DAPM_OUTPUT("LEFT_LO"),
SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
SND_SOC_DAPM_INPUT("LINEL"),
SND_SOC_DAPM_INPUT("LINER"),
SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0),
/* Analog bypass */
SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
&dac33_dapm_abypassl_control),
SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
&dac33_dapm_abypassr_control),
SND_SOC_DAPM_MUX("Left LOM Inverted From", SND_SOC_NOPM, 0, 0,
&dac33_dapm_left_lom_control),
SND_SOC_DAPM_MUX("Right LOM Inverted From", SND_SOC_NOPM, 0, 0,
&dac33_dapm_right_lom_control),
/*
* For DAPM path, when only the anlog bypass path is enabled, and the
* LOP inverted from the corresponding DAC side.
* This is needed, so we can attach the DAC power supply in this case.
*/
SND_SOC_DAPM_PGA("Left Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amplifier",
DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amplifier",
DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
SND_SOC_DAPM_SUPPLY("Left DAC Power",
DAC33_LDAC_PWR_CTRL, 2, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Right DAC Power",
DAC33_RDAC_PWR_CTRL, 2, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Codec Power",
DAC33_PWR_CTRL, 4, 0, NULL, 0),
SND_SOC_DAPM_PRE("Pre Playback", dac33_playback_event),
SND_SOC_DAPM_POST("Post Playback", dac33_playback_event),
};
static const struct snd_soc_dapm_route audio_map[] = {
/* Analog bypass */
{"Analog Left Bypass", "Switch", "LINEL"},
{"Analog Right Bypass", "Switch", "LINER"},
{"Output Left Amplifier", NULL, "DACL"},
{"Output Right Amplifier", NULL, "DACR"},
{"Left Bypass PGA", NULL, "Analog Left Bypass"},
{"Right Bypass PGA", NULL, "Analog Right Bypass"},
{"Left LOM Inverted From", "DAC", "Left Bypass PGA"},
{"Right LOM Inverted From", "DAC", "Right Bypass PGA"},
{"Left LOM Inverted From", "LOP", "Analog Left Bypass"},
{"Right LOM Inverted From", "LOP", "Analog Right Bypass"},
{"Output Left Amplifier", NULL, "Left LOM Inverted From"},
{"Output Right Amplifier", NULL, "Right LOM Inverted From"},
{"DACL", NULL, "Left DAC Power"},
{"DACR", NULL, "Right DAC Power"},
{"Left Bypass PGA", NULL, "Left DAC Power"},
{"Right Bypass PGA", NULL, "Right DAC Power"},
/* output */
{"LEFT_LO", NULL, "Output Left Amplifier"},
{"RIGHT_LO", NULL, "Output Right Amplifier"},
{"LEFT_LO", NULL, "Codec Power"},
{"RIGHT_LO", NULL, "Codec Power"},
};
static int dac33_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
int ret;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
/* Coming from OFF, switch on the component */
ret = dac33_hard_power(component, 1);
if (ret != 0)
return ret;
dac33_init_chip(component);
}
break;
case SND_SOC_BIAS_OFF:
/* Do not power off, when the component is already off */
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
return 0;
ret = dac33_hard_power(component, 0);
if (ret != 0)
return ret;
break;
}
return 0;
}
static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
{
struct snd_soc_component *component = dac33->component;
unsigned int delay;
unsigned long flags;
switch (dac33->fifo_mode) {
case DAC33_FIFO_MODE1:
dac33_write16(component, DAC33_NSAMPLE_MSB,
DAC33_THRREG(dac33->nsample));
/* Take the timestamps */
spin_lock_irqsave(&dac33->lock, flags);
dac33->t_stamp2 = ktime_to_us(ktime_get());
dac33->t_stamp1 = dac33->t_stamp2;
spin_unlock_irqrestore(&dac33->lock, flags);
dac33_write16(component, DAC33_PREFILL_MSB,
DAC33_THRREG(dac33->alarm_threshold));
/* Enable Alarm Threshold IRQ with a delay */
delay = SAMPLES_TO_US(dac33->burst_rate,
dac33->alarm_threshold) + 1000;
usleep_range(delay, delay + 500);
dac33_write(component, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
break;
case DAC33_FIFO_MODE7:
/* Take the timestamp */
spin_lock_irqsave(&dac33->lock, flags);
dac33->t_stamp1 = ktime_to_us(ktime_get());
/* Move back the timestamp with drain time */
dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
spin_unlock_irqrestore(&dac33->lock, flags);
dac33_write16(component, DAC33_PREFILL_MSB,
DAC33_THRREG(DAC33_MODE7_MARGIN));
/* Enable Upper Threshold IRQ */
dac33_write(component, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
break;
default:
dev_warn(component->dev, "Unhandled FIFO mode: %d\n",
dac33->fifo_mode);
break;
}
}
static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
{
struct snd_soc_component *component = dac33->component;
unsigned long flags;
switch (dac33->fifo_mode) {
case DAC33_FIFO_MODE1:
/* Take the timestamp */
spin_lock_irqsave(&dac33->lock, flags);
dac33->t_stamp2 = ktime_to_us(ktime_get());
spin_unlock_irqrestore(&dac33->lock, flags);
dac33_write16(component, DAC33_NSAMPLE_MSB,
DAC33_THRREG(dac33->nsample));
break;
case DAC33_FIFO_MODE7:
/* At the moment we are not using interrupts in mode7 */
break;
default:
dev_warn(component->dev, "Unhandled FIFO mode: %d\n",
dac33->fifo_mode);
break;
}
}
static void dac33_work(struct work_struct *work)
{
struct snd_soc_component *component;
struct tlv320dac33_priv *dac33;
u8 reg;
dac33 = container_of(work, struct tlv320dac33_priv, work);
component = dac33->component;
mutex_lock(&dac33->mutex);
switch (dac33->state) {
case DAC33_PREFILL:
dac33->state = DAC33_PLAYBACK;
dac33_prefill_handler(dac33);
break;
case DAC33_PLAYBACK:
dac33_playback_handler(dac33);
break;
case DAC33_IDLE:
break;
case DAC33_FLUSH:
dac33->state = DAC33_IDLE;
/* Mask all interrupts from dac33 */
dac33_write(component, DAC33_FIFO_IRQ_MASK, 0);
/* flush fifo */
reg = dac33_read_reg_cache(component, DAC33_FIFO_CTRL_A);
reg |= DAC33_FIFOFLUSH;
dac33_write(component, DAC33_FIFO_CTRL_A, reg);
break;
}
mutex_unlock(&dac33->mutex);
}
static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
{
struct snd_soc_component *component = dev;
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
unsigned long flags;
spin_lock_irqsave(&dac33->lock, flags);
dac33->t_stamp1 = ktime_to_us(ktime_get());
spin_unlock_irqrestore(&dac33->lock, flags);
/* Do not schedule the workqueue in Mode7 */
if (dac33->fifo_mode != DAC33_FIFO_MODE7)
schedule_work(&dac33->work);
return IRQ_HANDLED;
}
static void dac33_oscwait(struct snd_soc_component *component)
{
int timeout = 60;
u8 reg;
do {
usleep_range(1000, 2000);
dac33_read(component, DAC33_INT_OSC_STATUS, ®);
} while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
dev_err(component->dev,
"internal oscillator calibration failed\n");
}
static int dac33_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
/* Stream started, save the substream pointer */
dac33->substream = substream;
return 0;
}
static void dac33_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
dac33->substream = NULL;
}
#define CALC_BURST_RATE(bclkdiv, bclk_per_sample) \
(BURST_BASEFREQ_HZ / bclkdiv / bclk_per_sample)
static int dac33_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
/* Check parameters for validity */
switch (params_rate(params)) {
case 44100:
case 48000:
break;
default:
dev_err(component->dev, "unsupported rate %d\n",
params_rate(params));
return -EINVAL;
}
switch (params_width(params)) {
case 16:
dac33->fifo_size = DAC33_FIFO_SIZE_16BIT;
dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 32);
break;
case 32:
dac33->fifo_size = DAC33_FIFO_SIZE_24BIT;
dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 64);
break;
default:
dev_err(component->dev, "unsupported width %d\n",
params_width(params));
return -EINVAL;
}
return 0;
}
#define CALC_OSCSET(rate, refclk) ( \
((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
#define CALC_RATIOSET(rate, refclk) ( \
((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
/*
* tlv320dac33 is strict on the sequence of the register writes, if the register
* writes happens in different order, than dac33 might end up in unknown state.
* Use the known, working sequence of register writes to initialize the dac33.
*/
static int dac33_prepare_chip(struct snd_pcm_substream *substream,
struct snd_soc_component *component)
{
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
u8 aictrl_a, aictrl_b, fifoctrl_a;
switch (substream->runtime->rate) {
case 44100:
case 48000:
oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
ratioset = CALC_RATIOSET(substream->runtime->rate,
dac33->refclk);
break;
default:
dev_err(component->dev, "unsupported rate %d\n",
substream->runtime->rate);
return -EINVAL;
}
aictrl_a = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_A);
aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
/* Read FIFO control A, and clear FIFO flush bit */
fifoctrl_a = dac33_read_reg_cache(component, DAC33_FIFO_CTRL_A);
fifoctrl_a &= ~DAC33_FIFOFLUSH;
fifoctrl_a &= ~DAC33_WIDTH;
switch (substream->runtime->format) {
case SNDRV_PCM_FORMAT_S16_LE:
aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
fifoctrl_a |= DAC33_WIDTH;
break;
case SNDRV_PCM_FORMAT_S32_LE:
aictrl_a |= (DAC33_NCYCL_32 | DAC33_WLEN_24);
break;
default:
dev_err(component->dev, "unsupported format %d\n",
substream->runtime->format);
return -EINVAL;
}
mutex_lock(&dac33->mutex);
if (!dac33->chip_power) {
/*
* Chip is not powered yet.
* Do the init in the dac33_set_bias_level later.
*/
mutex_unlock(&dac33->mutex);
return 0;
}
dac33_soft_power(component, 0);
dac33_soft_power(component, 1);
reg_tmp = dac33_read_reg_cache(component, DAC33_INT_OSC_CTRL);
dac33_write(component, DAC33_INT_OSC_CTRL, reg_tmp);
/* Write registers 0x08 and 0x09 (MSB, LSB) */
dac33_write16(component, DAC33_INT_OSC_FREQ_RAT_A, oscset);
/* OSC calibration time */
dac33_write(component, DAC33_CALIB_TIME, 96);
/* adjustment treshold & step */
dac33_write(component, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
DAC33_ADJSTEP(1));
/* div=4 / gain=1 / div */
dac33_write(component, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
pwr_ctrl = dac33_read_reg_cache(component, DAC33_PWR_CTRL);
pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
dac33_write(component, DAC33_PWR_CTRL, pwr_ctrl);
dac33_oscwait(component);
if (dac33->fifo_mode) {
/* Generic for all FIFO modes */
/* 50-51 : ASRC Control registers */
dac33_write(component, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
dac33_write(component, DAC33_ASRC_CTRL_B, 1); /* ??? */
/* Write registers 0x34 and 0x35 (MSB, LSB) */
dac33_write16(component, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
/* Set interrupts to high active */
dac33_write(component, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
} else {
/* FIFO bypass mode */
/* 50-51 : ASRC Control registers */
dac33_write(component, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
dac33_write(component, DAC33_ASRC_CTRL_B, 0); /* ??? */
}
/* Interrupt behaviour configuration */
switch (dac33->fifo_mode) {
case DAC33_FIFO_MODE1:
dac33_write(component, DAC33_FIFO_IRQ_MODE_B,
DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
break;
case DAC33_FIFO_MODE7:
dac33_write(component, DAC33_FIFO_IRQ_MODE_A,
DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL));
break;
default:
/* in FIFO bypass mode, the interrupts are not used */
break;
}
aictrl_b = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_B);
switch (dac33->fifo_mode) {
case DAC33_FIFO_MODE1:
/*
* For mode1:
* Disable the FIFO bypass (Enable the use of FIFO)
* Select nSample mode
* BCLK is only running when data is needed by DAC33
*/
fifoctrl_a &= ~DAC33_FBYPAS;
fifoctrl_a &= ~DAC33_FAUTO;
if (dac33->keep_bclk)
aictrl_b |= DAC33_BCLKON;
else
aictrl_b &= ~DAC33_BCLKON;
break;
case DAC33_FIFO_MODE7:
/*
* For mode1:
* Disable the FIFO bypass (Enable the use of FIFO)
* Select Threshold mode
* BCLK is only running when data is needed by DAC33
*/
fifoctrl_a &= ~DAC33_FBYPAS;
fifoctrl_a |= DAC33_FAUTO;
if (dac33->keep_bclk)
aictrl_b |= DAC33_BCLKON;
else
aictrl_b &= ~DAC33_BCLKON;
break;
default:
/*
* For FIFO bypass mode:
* Enable the FIFO bypass (Disable the FIFO use)
* Set the BCLK as continuous
*/
fifoctrl_a |= DAC33_FBYPAS;
aictrl_b |= DAC33_BCLKON;
break;
}
dac33_write(component, DAC33_FIFO_CTRL_A, fifoctrl_a);
dac33_write(component, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
dac33_write(component, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
/*
* BCLK divide ratio
* 0: 1.5
* 1: 1
* 2: 2
* ...
* 254: 254
* 255: 255
*/
if (dac33->fifo_mode)
dac33_write(component, DAC33_SER_AUDIOIF_CTRL_C,
dac33->burst_bclkdiv);
else
if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE)
dac33_write(component, DAC33_SER_AUDIOIF_CTRL_C, 32);
else
dac33_write(component, DAC33_SER_AUDIOIF_CTRL_C, 16);
switch (dac33->fifo_mode) {
case DAC33_FIFO_MODE1:
dac33_write16(component, DAC33_ATHR_MSB,
DAC33_THRREG(dac33->alarm_threshold));
break;
case DAC33_FIFO_MODE7:
/*
* Configure the threshold levels, and leave 10 sample space
* at the bottom, and also at the top of the FIFO
*/
dac33_write16(component, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr));
dac33_write16(component, DAC33_LTHR_MSB,
DAC33_THRREG(DAC33_MODE7_MARGIN));
break;
default:
break;
}
mutex_unlock(&dac33->mutex);
return 0;
}
static void dac33_calculate_times(struct snd_pcm_substream *substream,
struct snd_soc_component *component)
{
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
unsigned int period_size = substream->runtime->period_size;
unsigned int rate = substream->runtime->rate;
unsigned int nsample_limit;
/* In bypass mode we don't need to calculate */
if (!dac33->fifo_mode)
return;
switch (dac33->fifo_mode) {
case DAC33_FIFO_MODE1:
/* Number of samples under i2c latency */
dac33->alarm_threshold = US_TO_SAMPLES(rate,
dac33->mode1_latency);
nsample_limit = dac33->fifo_size - dac33->alarm_threshold;
if (period_size <= dac33->alarm_threshold)
/*
* Configure nSamaple to number of periods,
* which covers the latency requironment.
*/
dac33->nsample = period_size *
((dac33->alarm_threshold / period_size) +
((dac33->alarm_threshold % period_size) ?
1 : 0));
else if (period_size > nsample_limit)
dac33->nsample = nsample_limit;
else
dac33->nsample = period_size;
dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
dac33->nsample);
dac33->t_stamp1 = 0;
dac33->t_stamp2 = 0;
break;
case DAC33_FIFO_MODE7:
dac33->uthr = UTHR_FROM_PERIOD_SIZE(period_size, rate,
dac33->burst_rate) + 9;
if (dac33->uthr > (dac33->fifo_size - DAC33_MODE7_MARGIN))
dac33->uthr = dac33->fifo_size - DAC33_MODE7_MARGIN;
if (dac33->uthr < (DAC33_MODE7_MARGIN + 10))
dac33->uthr = (DAC33_MODE7_MARGIN + 10);
dac33->mode7_us_to_lthr =
SAMPLES_TO_US(substream->runtime->rate,
dac33->uthr - DAC33_MODE7_MARGIN + 1);
dac33->t_stamp1 = 0;
break;
default:
break;
}
}
static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
int ret = 0;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
if (dac33->fifo_mode) {
dac33->state = DAC33_PREFILL;
schedule_work(&dac33->work);
}
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
if (dac33->fifo_mode) {
dac33->state = DAC33_FLUSH;
schedule_work(&dac33->work);
}
break;
default:
ret = -EINVAL;
}
return ret;
}
static snd_pcm_sframes_t dac33_dai_delay(
struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
unsigned long long t0, t1, t_now;
unsigned int time_delta, uthr;
int samples_out, samples_in, samples;
snd_pcm_sframes_t delay = 0;
unsigned long flags;
switch (dac33->fifo_mode) {
case DAC33_FIFO_BYPASS:
break;
case DAC33_FIFO_MODE1:
spin_lock_irqsave(&dac33->lock, flags);
t0 = dac33->t_stamp1;
t1 = dac33->t_stamp2;
spin_unlock_irqrestore(&dac33->lock, flags);
t_now = ktime_to_us(ktime_get());
/* We have not started to fill the FIFO yet, delay is 0 */
if (!t1)
goto out;
if (t0 > t1) {
/*
* Phase 1:
* After Alarm threshold, and before nSample write
*/
time_delta = t_now - t0;
samples_out = time_delta ? US_TO_SAMPLES(
substream->runtime->rate,
time_delta) : 0;
if (likely(dac33->alarm_threshold > samples_out))
delay = dac33->alarm_threshold - samples_out;
else
delay = 0;
} else if ((t_now - t1) <= dac33->mode1_us_burst) {
/*
* Phase 2:
* After nSample write (during burst operation)
*/
time_delta = t_now - t0;
samples_out = time_delta ? US_TO_SAMPLES(
substream->runtime->rate,
time_delta) : 0;
time_delta = t_now - t1;
samples_in = time_delta ? US_TO_SAMPLES(
dac33->burst_rate,
time_delta) : 0;
samples = dac33->alarm_threshold;
samples += (samples_in - samples_out);
if (likely(samples > 0))
delay = samples;
else
delay = 0;
} else {
/*
* Phase 3:
* After burst operation, before next alarm threshold
*/
time_delta = t_now - t0;
samples_out = time_delta ? US_TO_SAMPLES(
substream->runtime->rate,
time_delta) : 0;
samples_in = dac33->nsample;
samples = dac33->alarm_threshold;
samples += (samples_in - samples_out);
if (likely(samples > 0))
delay = samples > dac33->fifo_size ?
dac33->fifo_size : samples;
else
delay = 0;
}
break;
case DAC33_FIFO_MODE7:
spin_lock_irqsave(&dac33->lock, flags);
t0 = dac33->t_stamp1;
uthr = dac33->uthr;
spin_unlock_irqrestore(&dac33->lock, flags);
t_now = ktime_to_us(ktime_get());
/* We have not started to fill the FIFO yet, delay is 0 */
if (!t0)
goto out;
if (t_now <= t0) {
/*
* Either the timestamps are messed or equal. Report
* maximum delay
*/
delay = uthr;
goto out;
}
time_delta = t_now - t0;
if (time_delta <= dac33->mode7_us_to_lthr) {
/*
* Phase 1:
* After burst (draining phase)
*/
samples_out = US_TO_SAMPLES(
substream->runtime->rate,
time_delta);
if (likely(uthr > samples_out))
delay = uthr - samples_out;
else
delay = 0;
} else {
/*
* Phase 2:
* During burst operation
*/
time_delta = time_delta - dac33->mode7_us_to_lthr;
samples_out = US_TO_SAMPLES(
substream->runtime->rate,
time_delta);
samples_in = US_TO_SAMPLES(
dac33->burst_rate,
time_delta);
delay = DAC33_MODE7_MARGIN + samples_in - samples_out;
if (unlikely(delay > uthr))
delay = uthr;
}
break;
default:
dev_warn(component->dev, "Unhandled FIFO mode: %d\n",
dac33->fifo_mode);
break;
}
out:
return delay;
}
static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
u8 ioc_reg, asrcb_reg;
ioc_reg = dac33_read_reg_cache(component, DAC33_INT_OSC_CTRL);
asrcb_reg = dac33_read_reg_cache(component, DAC33_ASRC_CTRL_B);
switch (clk_id) {
case TLV320DAC33_MCLK:
ioc_reg |= DAC33_REFSEL;
asrcb_reg |= DAC33_SRCREFSEL;
break;
case TLV320DAC33_SLEEPCLK:
ioc_reg &= ~DAC33_REFSEL;
asrcb_reg &= ~DAC33_SRCREFSEL;
break;
default:
dev_err(component->dev, "Invalid clock ID (%d)\n", clk_id);
break;
}
dac33->refclk = freq;
dac33_write_reg_cache(component, DAC33_INT_OSC_CTRL, ioc_reg);
dac33_write_reg_cache(component, DAC33_ASRC_CTRL_B, asrcb_reg);
return 0;
}
static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
u8 aictrl_a, aictrl_b;
aictrl_a = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_A);
aictrl_b = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_B);
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
break;
case SND_SOC_DAIFMT_CBC_CFC:
if (dac33->fifo_mode) {
dev_err(component->dev, "FIFO mode requires provider mode\n");
return -EINVAL;
} else
aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
break;
default:
return -EINVAL;
}
aictrl_a &= ~DAC33_AFMT_MASK;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
aictrl_a |= DAC33_AFMT_I2S;
break;
case SND_SOC_DAIFMT_DSP_A:
aictrl_a |= DAC33_AFMT_DSP;
aictrl_b &= ~DAC33_DATA_DELAY_MASK;
aictrl_b |= DAC33_DATA_DELAY(0);
break;
case SND_SOC_DAIFMT_RIGHT_J:
aictrl_a |= DAC33_AFMT_RIGHT_J;
break;
case SND_SOC_DAIFMT_LEFT_J:
aictrl_a |= DAC33_AFMT_LEFT_J;
break;
default:
dev_err(component->dev, "Unsupported format (%u)\n",
fmt & SND_SOC_DAIFMT_FORMAT_MASK);
return -EINVAL;
}
dac33_write_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
dac33_write_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
return 0;
}
static int dac33_soc_probe(struct snd_soc_component *component)
{
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
int ret = 0;
dac33->component = component;
/* Read the tlv320dac33 ID registers */
ret = dac33_hard_power(component, 1);
if (ret != 0) {
dev_err(component->dev, "Failed to power up component: %d\n", ret);
goto err_power;
}
ret = dac33_read_id(component);
dac33_hard_power(component, 0);
if (ret < 0) {
dev_err(component->dev, "Failed to read chip ID: %d\n", ret);
ret = -ENODEV;
goto err_power;
}
/* Check if the IRQ number is valid and request it */
if (dac33->irq >= 0) {
ret = request_irq(dac33->irq, dac33_interrupt_handler,
IRQF_TRIGGER_RISING,
component->name, component);
if (ret < 0) {
dev_err(component->dev, "Could not request IRQ%d (%d)\n",
dac33->irq, ret);
dac33->irq = -1;
}
if (dac33->irq != -1) {
INIT_WORK(&dac33->work, dac33_work);
}
}
/* Only add the FIFO controls, if we have valid IRQ number */
if (dac33->irq >= 0)
snd_soc_add_component_controls(component, dac33_mode_snd_controls,
ARRAY_SIZE(dac33_mode_snd_controls));
err_power:
return ret;
}
static void dac33_soc_remove(struct snd_soc_component *component)
{
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
if (dac33->irq >= 0) {
free_irq(dac33->irq, dac33->component);
flush_work(&dac33->work);
}
}
static const struct snd_soc_component_driver soc_component_dev_tlv320dac33 = {
.read = dac33_read_reg_cache,
.write = dac33_write_locked,
.set_bias_level = dac33_set_bias_level,
.probe = dac33_soc_probe,
.remove = dac33_soc_remove,
.controls = dac33_snd_controls,
.num_controls = ARRAY_SIZE(dac33_snd_controls),
.dapm_widgets = dac33_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(dac33_dapm_widgets),
.dapm_routes = audio_map,
.num_dapm_routes = ARRAY_SIZE(audio_map),
.use_pmdown_time = 1,
.endianness = 1,
};
#define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000)
#define DAC33_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops dac33_dai_ops = {
.startup = dac33_startup,
.shutdown = dac33_shutdown,
.hw_params = dac33_hw_params,
.trigger = dac33_pcm_trigger,
.delay = dac33_dai_delay,
.set_sysclk = dac33_set_dai_sysclk,
.set_fmt = dac33_set_dai_fmt,
};
static struct snd_soc_dai_driver dac33_dai = {
.name = "tlv320dac33-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = DAC33_RATES,
.formats = DAC33_FORMATS,
.sig_bits = 24,
},
.ops = &dac33_dai_ops,
};
static int dac33_i2c_probe(struct i2c_client *client)
{
struct tlv320dac33_platform_data *pdata;
struct tlv320dac33_priv *dac33;
int ret, i;
if (client->dev.platform_data == NULL) {
dev_err(&client->dev, "Platform data not set\n");
return -ENODEV;
}
pdata = client->dev.platform_data;
dac33 = devm_kzalloc(&client->dev, sizeof(struct tlv320dac33_priv),
GFP_KERNEL);
if (dac33 == NULL)
return -ENOMEM;
dac33->reg_cache = devm_kmemdup(&client->dev,
dac33_reg,
ARRAY_SIZE(dac33_reg) * sizeof(u8),
GFP_KERNEL);
if (!dac33->reg_cache)
return -ENOMEM;
dac33->i2c = client;
mutex_init(&dac33->mutex);
spin_lock_init(&dac33->lock);
i2c_set_clientdata(client, dac33);
dac33->power_gpio = pdata->power_gpio;
dac33->burst_bclkdiv = pdata->burst_bclkdiv;
dac33->keep_bclk = pdata->keep_bclk;
dac33->mode1_latency = pdata->mode1_latency;
if (!dac33->mode1_latency)
dac33->mode1_latency = 10000; /* 10ms */
dac33->irq = client->irq;
/* Disable FIFO use by default */
dac33->fifo_mode = DAC33_FIFO_BYPASS;
/* Check if the reset GPIO number is valid and request it */
if (dac33->power_gpio >= 0) {
ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
if (ret < 0) {
dev_err(&client->dev,
"Failed to request reset GPIO (%d)\n",
dac33->power_gpio);
goto err_gpio;
}
gpio_direction_output(dac33->power_gpio, 0);
}
for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
dac33->supplies[i].supply = dac33_supply_names[i];
ret = devm_regulator_bulk_get(&client->dev, ARRAY_SIZE(dac33->supplies),
dac33->supplies);
if (ret != 0) {
dev_err(&client->dev, "Failed to request supplies: %d\n", ret);
goto err_get;
}
ret = devm_snd_soc_register_component(&client->dev,
&soc_component_dev_tlv320dac33, &dac33_dai, 1);
if (ret < 0)
goto err_get;
return ret;
err_get:
if (dac33->power_gpio >= 0)
gpio_free(dac33->power_gpio);
err_gpio:
return ret;
}
static void dac33_i2c_remove(struct i2c_client *client)
{
struct tlv320dac33_priv *dac33 = i2c_get_clientdata(client);
if (unlikely(dac33->chip_power))
dac33_hard_power(dac33->component, 0);
if (dac33->power_gpio >= 0)
gpio_free(dac33->power_gpio);
}
static const struct i2c_device_id tlv320dac33_i2c_id[] = {
{
.name = "tlv320dac33",
.driver_data = 0,
},
{ },
};
MODULE_DEVICE_TABLE(i2c, tlv320dac33_i2c_id);
static struct i2c_driver tlv320dac33_i2c_driver = {
.driver = {
.name = "tlv320dac33-codec",
},
.probe = dac33_i2c_probe,
.remove = dac33_i2c_remove,
.id_table = tlv320dac33_i2c_id,
};
module_i2c_driver(tlv320dac33_i2c_driver);
MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
MODULE_AUTHOR("Peter Ujfalusi <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/tlv320dac33.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* sound/soc/codecs/wm8782.c
* simple, strap-pin configured 24bit 2ch ADC
*
* Copyright: 2011 Raumfeld GmbH
* Author: Johannes Stezenbach <[email protected]>
*
* based on ad73311.c
* Copyright: Analog Devices Inc.
* Author: Cliff Cai <[email protected]>
*/
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/regulator/consumer.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/ac97_codec.h>
#include <sound/initval.h>
#include <sound/soc.h>
static const struct snd_soc_dapm_widget wm8782_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("AINL"),
SND_SOC_DAPM_INPUT("AINR"),
};
static const struct snd_soc_dapm_route wm8782_dapm_routes[] = {
{ "Capture", NULL, "AINL" },
{ "Capture", NULL, "AINR" },
};
static struct snd_soc_dai_driver wm8782_dai = {
.name = "wm8782",
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
/* For configurations with FSAMPEN=0 */
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S20_3LE |
SNDRV_PCM_FMTBIT_S24_LE,
},
};
/* regulator power supply names */
static const char *supply_names[] = {
"Vdda", /* analog supply, 2.7V - 3.6V */
"Vdd", /* digital supply, 2.7V - 5.5V */
};
struct wm8782_priv {
struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
};
static int wm8782_soc_probe(struct snd_soc_component *component)
{
struct wm8782_priv *priv = snd_soc_component_get_drvdata(component);
return regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
}
static void wm8782_soc_remove(struct snd_soc_component *component)
{
struct wm8782_priv *priv = snd_soc_component_get_drvdata(component);
regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies);
}
#ifdef CONFIG_PM
static int wm8782_soc_suspend(struct snd_soc_component *component)
{
struct wm8782_priv *priv = snd_soc_component_get_drvdata(component);
regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies);
return 0;
}
static int wm8782_soc_resume(struct snd_soc_component *component)
{
struct wm8782_priv *priv = snd_soc_component_get_drvdata(component);
return regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
}
#else
#define wm8782_soc_suspend NULL
#define wm8782_soc_resume NULL
#endif /* CONFIG_PM */
static const struct snd_soc_component_driver soc_component_dev_wm8782 = {
.probe = wm8782_soc_probe,
.remove = wm8782_soc_remove,
.suspend = wm8782_soc_suspend,
.resume = wm8782_soc_resume,
.dapm_widgets = wm8782_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8782_dapm_widgets),
.dapm_routes = wm8782_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(wm8782_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int wm8782_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct wm8782_priv *priv;
int ret, i;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
dev_set_drvdata(dev, priv);
for (i = 0; i < ARRAY_SIZE(supply_names); i++)
priv->supplies[i].supply = supply_names[i];
ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(priv->supplies),
priv->supplies);
if (ret < 0)
return ret;
return devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_wm8782, &wm8782_dai, 1);
}
#ifdef CONFIG_OF
static const struct of_device_id wm8782_of_match[] = {
{ .compatible = "wlf,wm8782", },
{ }
};
MODULE_DEVICE_TABLE(of, wm8782_of_match);
#endif
static struct platform_driver wm8782_codec_driver = {
.driver = {
.name = "wm8782",
.of_match_table = of_match_ptr(wm8782_of_match),
},
.probe = wm8782_probe,
};
module_platform_driver(wm8782_codec_driver);
MODULE_DESCRIPTION("ASoC WM8782 driver");
MODULE_AUTHOR("Johannes Stezenbach <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8782.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2022, Analog Devices Inc.
#include <linux/acpi.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/cdev.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include "max98388.h"
static struct reg_default max98388_reg[] = {
{MAX98388_R2000_SW_RESET, 0x00},
{MAX98388_R2001_INT_RAW1, 0x00},
{MAX98388_R2002_INT_RAW2, 0x00},
{MAX98388_R2004_INT_STATE1, 0x00},
{MAX98388_R2005_INT_STATE2, 0x00},
{MAX98388_R2020_THERM_WARN_THRESH, 0x0A},
{MAX98388_R2031_SPK_MON_THRESH, 0x58},
{MAX98388_R2032_SPK_MON_LD_SEL, 0x08},
{MAX98388_R2033_SPK_MON_DURATION, 0x02},
{MAX98388_R2037_ERR_MON_CTRL, 0x01},
{MAX98388_R2040_PCM_MODE_CFG, 0xC0},
{MAX98388_R2041_PCM_CLK_SETUP, 0x04},
{MAX98388_R2042_PCM_SR_SETUP, 0x88},
{MAX98388_R2044_PCM_TX_CTRL1, 0x00},
{MAX98388_R2045_PCM_TX_CTRL2, 0x00},
{MAX98388_R2050_PCM_TX_HIZ_CTRL1, 0xFF},
{MAX98388_R2051_PCM_TX_HIZ_CTRL2, 0xFF},
{MAX98388_R2052_PCM_TX_HIZ_CTRL3, 0xFF},
{MAX98388_R2053_PCM_TX_HIZ_CTRL4, 0xFF},
{MAX98388_R2054_PCM_TX_HIZ_CTRL5, 0xFF},
{MAX98388_R2055_PCM_TX_HIZ_CTRL6, 0xFF},
{MAX98388_R2056_PCM_TX_HIZ_CTRL7, 0xFF},
{MAX98388_R2057_PCM_TX_HIZ_CTRL8, 0xFF},
{MAX98388_R2058_PCM_RX_SRC1, 0x00},
{MAX98388_R2059_PCM_RX_SRC2, 0x01},
{MAX98388_R205C_PCM_TX_DRIVE_STRENGTH, 0x00},
{MAX98388_R205D_PCM_TX_SRC_EN, 0x00},
{MAX98388_R205E_PCM_RX_EN, 0x00},
{MAX98388_R205F_PCM_TX_EN, 0x00},
{MAX98388_R2090_SPK_CH_VOL_CTRL, 0x00},
{MAX98388_R2091_SPK_CH_CFG, 0x02},
{MAX98388_R2092_SPK_AMP_OUT_CFG, 0x03},
{MAX98388_R2093_SPK_AMP_SSM_CFG, 0x01},
{MAX98388_R2094_SPK_AMP_ER_CTRL, 0x00},
{MAX98388_R209E_SPK_CH_PINK_NOISE_EN, 0x00},
{MAX98388_R209F_SPK_CH_AMP_EN, 0x00},
{MAX98388_R20A0_IV_DATA_DSP_CTRL, 0x10},
{MAX98388_R20A7_IV_DATA_EN, 0x00},
{MAX98388_R20E0_BP_ALC_THRESH, 0x04},
{MAX98388_R20E1_BP_ALC_RATES, 0x20},
{MAX98388_R20E2_BP_ALC_ATTEN, 0x06},
{MAX98388_R20E3_BP_ALC_REL, 0x02},
{MAX98388_R20E4_BP_ALC_MUTE, 0x33},
{MAX98388_R20EE_BP_INF_HOLD_REL, 0x00},
{MAX98388_R20EF_BP_ALC_EN, 0x00},
{MAX98388_R210E_AUTO_RESTART, 0x00},
{MAX98388_R210F_GLOBAL_EN, 0x00},
{MAX98388_R22FF_REV_ID, 0x00},
};
static int max98388_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct max98388_priv *max98388 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_write(max98388->regmap,
MAX98388_R210F_GLOBAL_EN, 1);
usleep_range(30000, 31000);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_write(max98388->regmap,
MAX98388_R210F_GLOBAL_EN, 0);
usleep_range(30000, 31000);
max98388->tdm_mode = false;
break;
default:
return 0;
}
return 0;
}
static const char * const max98388_monomix_switch_text[] = {
"Left", "Right", "LeftRight"};
static const struct soc_enum dai_sel_enum =
SOC_ENUM_SINGLE(MAX98388_R2058_PCM_RX_SRC1,
MAX98388_PCM_TO_SPK_MONOMIX_CFG_SHIFT,
3, max98388_monomix_switch_text);
static const struct snd_kcontrol_new max98388_dai_controls =
SOC_DAPM_ENUM("DAI Sel", dai_sel_enum);
static const struct snd_kcontrol_new max98388_vi_control =
SOC_DAPM_SINGLE("Switch", MAX98388_R205F_PCM_TX_EN, 0, 1, 0);
static const struct snd_soc_dapm_widget max98388_dapm_widgets[] = {
SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback",
MAX98388_R205E_PCM_RX_EN, 0, 0, max98388_dac_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0,
&max98388_dai_controls),
SND_SOC_DAPM_OUTPUT("BE_OUT"),
SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0,
MAX98388_R20A7_IV_DATA_EN, 0, 0),
SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0,
MAX98388_R20A7_IV_DATA_EN, 1, 0),
SND_SOC_DAPM_ADC("ADC Voltage", NULL,
MAX98388_R205D_PCM_TX_SRC_EN, 0, 0),
SND_SOC_DAPM_ADC("ADC Current", NULL,
MAX98388_R205D_PCM_TX_SRC_EN, 1, 0),
SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0,
&max98388_vi_control),
SND_SOC_DAPM_SIGGEN("VMON"),
SND_SOC_DAPM_SIGGEN("IMON"),
};
static DECLARE_TLV_DB_SCALE(max98388_digital_tlv, -6350, 50, 1);
static DECLARE_TLV_DB_SCALE(max98388_amp_gain_tlv, -300, 300, 0);
static const char * const max98388_alc_max_atten_text[] = {
"0dBFS", "-1dBFS", "-2dBFS", "-3dBFS", "-4dBFS", "-5dBFS",
"-6dBFS", "-7dBFS", "-8dBFS", "-9dBFS", "-10dBFS", "-11dBFS",
"-12dBFS", "-13dBFS", "-14dBFS", "-15dBFS"
};
static SOC_ENUM_SINGLE_DECL(max98388_alc_max_atten_enum,
MAX98388_R20E2_BP_ALC_ATTEN,
MAX98388_ALC_MAX_ATTEN_SHIFT,
max98388_alc_max_atten_text);
static const char * const max98388_thermal_warn_text[] = {
"95C", "105C", "115C", "125C"
};
static SOC_ENUM_SINGLE_DECL(max98388_thermal_warning_thresh_enum,
MAX98388_R2020_THERM_WARN_THRESH,
MAX98388_THERM_WARN_THRESH_SHIFT,
max98388_thermal_warn_text);
static const char * const max98388_thermal_shutdown_text[] = {
"135C", "145C", "155C", "165C"
};
static SOC_ENUM_SINGLE_DECL(max98388_thermal_shutdown_thresh_enum,
MAX98388_R2020_THERM_WARN_THRESH,
MAX98388_THERM_SHDN_THRESH_SHIFT,
max98388_thermal_shutdown_text);
static const char * const max98388_alc_thresh_single_text[] = {
"3.625V", "3.550V", "3.475V", "3.400V", "3.325V", "3.250V",
"3.175V", "3.100V", "3.025V", "2.950V", "2.875V", "2.800V",
"2.725V", "2.650V", "2.575V", "2.500V"
};
static SOC_ENUM_SINGLE_DECL(max98388_alc_thresh_single_enum,
MAX98388_R20E0_BP_ALC_THRESH,
MAX98388_ALC_THRESH_SHIFT,
max98388_alc_thresh_single_text);
static const char * const max98388_alc_attack_rate_text[] = {
"0", "10us", "20us", "40us", "80us", "160us",
"320us", "640us", "1.28ms", "2.56ms", "5.12ms", "10.24ms",
"20.48ms", "40.96ms", "81.92ms", "163.84ms"
};
static SOC_ENUM_SINGLE_DECL(max98388_alc_attack_rate_enum,
MAX98388_R20E1_BP_ALC_RATES,
MAX98388_ALC_ATTACK_RATE_SHIFT,
max98388_alc_attack_rate_text);
static const char * const max98388_alc_release_rate_text[] = {
"20us", "40us", "80us", "160us", "320us", "640us",
"1.28ms", "2.56ms", "5.12ms", "10.24ms", "20.48ms", "40.96ms",
"81.92ms", "163.84ms", "327.68ms", "655.36ms"
};
static SOC_ENUM_SINGLE_DECL(max98388_alc_release_rate_enum,
MAX98388_R20E1_BP_ALC_RATES,
MAX98388_ALC_RELEASE_RATE_SHIFT,
max98388_alc_release_rate_text);
static const char * const max98388_alc_debounce_text[] = {
"0.01ms", "0.1ms", "1ms", "10ms", "100ms", "250ms", "500ms", "hold"
};
static SOC_ENUM_SINGLE_DECL(max98388_alc_debouce_enum,
MAX98388_R20E3_BP_ALC_REL,
MAX98388_ALC_DEBOUNCE_TIME_SHIFT,
max98388_alc_debounce_text);
static const char * const max98388_alc_mute_delay_text[] = {
"0.01ms", "0.05ms", "0.1ms", "0.5ms", "1ms", "5ms", "25ms", "250ms"
};
static SOC_ENUM_SINGLE_DECL(max98388_alc_mute_delay_enum,
MAX98388_R20E4_BP_ALC_MUTE,
MAX98388_ALC_MUTE_DELAY_SHIFT,
max98388_alc_mute_delay_text);
static const char * const max98388_spkmon_duration_text[] = {
"10ms", "25ms", "50ms", "75ms", "100ms", "200ms", "300ms", "400ms",
"500ms", "600ms", "700ms", "800ms", "900ms", "1000ms", "1100ms", "1200ms"
};
static SOC_ENUM_SINGLE_DECL(max98388_spkmon_duration_enum,
MAX98388_R2033_SPK_MON_DURATION,
MAX98388_SPKMON_DURATION_SHIFT,
max98388_spkmon_duration_text);
static const char * const max98388_spkmon_thresh_text[] = {
"0.03V", "0.06V", "0.09V", "0.12V", "0.15V", "0.18V", "0.20V", "0.23V",
"0.26V", "0.29V", "0.32V", "0.35V", "0.38V", "0.41V", "0.44V", "0.47V",
"0.50V", "0.53V", "0.56V", "0.58V", "0.61V", "0.64V", "0.67V", "0.70V",
"0.73V", "0.76V", "0.79V", "0.82V", "0.85V", "0.88V", "0.91V", "0.94V",
"0.96V", "0.99V", "1.02V", "1.05V", "1.08V", "1.11V", "1.14V", "1.17V",
"1.20V", "1.23V", "1.26V", "1.29V", "1.32V", "1.35V", "1.37V", "1.40V",
"1.43V", "1.46V", "1.49V", "1.52V", "1.55V", "1.58V", "1.61V", "1.64V",
"1.67V", "1.70V", "1.73V", "1.75V", "1.78V", "1.81V", "1.84V", "1.87V",
"1.90V", "1.93V", "1.96V", "1.99V", "2.02V", "2.05V", "2.08V", "2.11V",
"2.13V", "2.16V", "2.19V", "2.22V", "2.25V", "2.28V", "2.31V", "2.34V",
"2.37V", "2.40V", "2.43V", "2.46V", "2.49V", "2.51V", "2.54V", "2.57V",
"2.60V", "2.63V", "2.66V", "2.69V", "2.72V", "2.75V", "2.78V", "2.81V",
"2.84V", "2.87V", "2.89V", "2.92V", "2.95V", "2.98V", "3.01V", "3.04V",
"3.07V", "3.10V", "3.13V", "3.16V", "3.19V", "3.22V", "3.25V", "3.27V",
"3.30V", "3.33V", "3.36V", "3.39V", "3.42V", "3.45V", "3.48V", "3.51V",
"3.54V", "3.57V", "3.60V", "3.63V", "3.66V", "3.68V", "3.71V", "3.74V"
};
static SOC_ENUM_SINGLE_DECL(max98388_spkmon_thresh_enum,
MAX98388_R2031_SPK_MON_THRESH,
MAX98388_SPKMON_THRESH_SHIFT,
max98388_spkmon_thresh_text);
static const char * const max98388_spkmon_load_text[] = {
"2.00ohm", "2.25ohm", "2.50ohm", "2.75ohm", "3.00ohm", "3.25ohm",
"3.50ohm", "3.75ohm", "4.00ohm", "4.25ohm", "4.50ohm", "4.75ohm",
"5.00ohm", "5.25ohm", "5.50ohm", "5.75ohm", "6.00ohm", "6.25ohm",
"6.50ohm", "6.75ohm", "7.00ohm", "7.25ohm", "7.50ohm", "7.75ohm",
"8.00ohm", "8.25ohm", "8.50ohm", "8.75ohm", "9.00ohm", "9.25ohm",
"9.50ohm", "9.75ohm", "10.00ohm", "10.25ohm", "10.50ohm", "10.75ohm",
"11.00ohm", "11.25ohm", "11.50ohm", "11.75ohm", "12.00ohm", "12.25ohm",
"12.50ohm", "12.75ohm", "13.00ohm", "13.25ohm", "13.50ohm", "13.75ohm",
"14.00ohm", "14.25ohm", "14.50ohm", "14.75ohm", "15.00ohm", "15.25ohm",
"15.50ohm", "15.75ohm", "16.00ohm", "16.25ohm", "16.50ohm", "16.75ohm",
"17.00ohm", "17.25ohm", "17.50ohm", "17.75ohm", "18.00ohm", "18.25ohm",
"18.50ohm", "18.75ohm", "19.00ohm", "19.25ohm", "19.50ohm", "19.75ohm",
"20.00ohm", "20.25ohm", "20.50ohm", "20.75ohm", "21.00ohm", "21.25ohm",
"21.50ohm", "21.75ohm", "22.00ohm", "22.25ohm", "22.50ohm", "22.75ohm",
"23.00ohm", "23.25ohm", "23.50ohm", "23.75ohm", "24.00ohm", "24.25ohm",
"24.50ohm", "24.75ohm", "25.00ohm", "25.25ohm", "25.50ohm", "25.75ohm",
"26.00ohm", "26.25ohm", "26.50ohm", "26.75ohm", "27.00ohm", "27.25ohm",
"27.50ohm", "27.75ohm", "28.00ohm", "28.25ohm", "28.50ohm", "28.75ohm",
"29.00ohm", "29.25ohm", "29.50ohm", "29.75ohm", "30.00ohm", "30.25ohm",
"30.50ohm", "30.75ohm", "31.00ohm", "31.25ohm", "31.50ohm", "31.75ohm",
"32.00ohm", "32.25ohm", "32.50ohm", "32.75ohm", "33.00ohm", "33.25ohm",
"33.50ohm", "33.75ohm"
};
static SOC_ENUM_SINGLE_DECL(max98388_spkmon_load_enum,
MAX98388_R2032_SPK_MON_LD_SEL,
MAX98388_SPKMON_LOAD_SHIFT,
max98388_spkmon_load_text);
static const char * const max98388_edge_rate_text[] = {
"Normal", "Reduced", "Maximum", "Increased",
};
static SOC_ENUM_SINGLE_DECL(max98388_edge_rate_falling_enum,
MAX98388_R2094_SPK_AMP_ER_CTRL,
MAX98388_EDGE_RATE_FALL_SHIFT,
max98388_edge_rate_text);
static SOC_ENUM_SINGLE_DECL(max98388_edge_rate_rising_enum,
MAX98388_R2094_SPK_AMP_ER_CTRL,
MAX98388_EDGE_RATE_RISE_SHIFT,
max98388_edge_rate_text);
static const char * const max98388_ssm_mod_text[] = {
"1.5%", "3.0%", "4.5%", "6.0%",
};
static SOC_ENUM_SINGLE_DECL(max98388_ssm_mod_enum,
MAX98388_R2093_SPK_AMP_SSM_CFG,
MAX98388_SPK_AMP_SSM_MOD_SHIFT,
max98388_ssm_mod_text);
static const struct snd_kcontrol_new max98388_snd_controls[] = {
SOC_SINGLE("Ramp Up Switch", MAX98388_R2091_SPK_CH_CFG,
MAX98388_SPK_CFG_VOL_RMPUP_SHIFT, 1, 0),
SOC_SINGLE("Ramp Down Switch", MAX98388_R2091_SPK_CH_CFG,
MAX98388_SPK_CFG_VOL_RMPDN_SHIFT, 1, 0),
/* Two Cell Mode Enable */
SOC_SINGLE("OP Mode Switch", MAX98388_R2092_SPK_AMP_OUT_CFG,
MAX98388_SPK_AMP_OUT_MODE_SHIFT, 1, 0),
/* Speaker Amplifier Overcurrent Automatic Restart Enable */
SOC_SINGLE("OVC Autorestart Switch", MAX98388_R210E_AUTO_RESTART,
MAX98388_OVC_AUTORESTART_SHIFT, 1, 0),
/* Thermal Shutdown Automatic Restart Enable */
SOC_SINGLE("THERM Autorestart Switch", MAX98388_R210E_AUTO_RESTART,
MAX98388_THERM_AUTORESTART_SHIFT, 1, 0),
/* PVDD UVLO Auto Restart */
SOC_SINGLE("UVLO Autorestart Switch", MAX98388_R210E_AUTO_RESTART,
MAX98388_PVDD_UVLO_AUTORESTART_SHIFT, 1, 0),
/* Clock Monitor Automatic Restart Enable */
SOC_SINGLE("CMON Autorestart Switch", MAX98388_R210E_AUTO_RESTART,
MAX98388_CMON_AUTORESTART_SHIFT, 1, 0),
SOC_SINGLE("CLK Monitor Switch", MAX98388_R2037_ERR_MON_CTRL,
MAX98388_CLOCK_MON_SHIFT, 1, 0),
/* Pinknoise Generator Enable */
SOC_SINGLE("Pinknoise Gen Switch", MAX98388_R209E_SPK_CH_PINK_NOISE_EN,
MAX98388_PINK_NOISE_GEN_SHIFT, 1, 0),
/* Dither Enable */
SOC_SINGLE("Dither Switch", MAX98388_R2091_SPK_CH_CFG,
MAX98388_SPK_CFG_DITH_EN_SHIFT, 1, 0),
SOC_SINGLE("VI Dither Switch", MAX98388_R20A0_IV_DATA_DSP_CTRL,
MAX98388_AMP_DSP_CTRL_DITH_SHIFT, 1, 0),
/* DC Blocker Enable */
SOC_SINGLE("DC Blocker Switch", MAX98388_R2091_SPK_CH_CFG,
MAX98388_SPK_CFG_DCBLK_SHIFT, 1, 0),
SOC_SINGLE("Voltage DC Blocker Switch", MAX98388_R20A0_IV_DATA_DSP_CTRL,
MAX98388_AMP_DSP_CTRL_VOL_DCBLK_SHIFT, 1, 0),
SOC_SINGLE("Current DC Blocker Switch", MAX98388_R20A0_IV_DATA_DSP_CTRL,
MAX98388_AMP_DSP_CTRL_CUR_DCBLK_SHIFT, 1, 0),
/* Digital Volume */
SOC_SINGLE_TLV("Digital Volume", MAX98388_R2090_SPK_CH_VOL_CTRL,
0, 0x7F, 1, max98388_digital_tlv),
/* Speaker Volume */
SOC_SINGLE_TLV("Speaker Volume", MAX98388_R2092_SPK_AMP_OUT_CFG,
0, 5, 0, max98388_amp_gain_tlv),
SOC_ENUM("Thermal Warn Thresh", max98388_thermal_warning_thresh_enum),
SOC_ENUM("Thermal SHDN Thresh", max98388_thermal_shutdown_thresh_enum),
/* Brownout Protection Automatic Level Control */
SOC_SINGLE("ALC Switch", MAX98388_R20EF_BP_ALC_EN, 0, 1, 0),
SOC_ENUM("ALC Thresh", max98388_alc_thresh_single_enum),
SOC_ENUM("ALC Attack Rate", max98388_alc_attack_rate_enum),
SOC_ENUM("ALC Release Rate", max98388_alc_release_rate_enum),
SOC_ENUM("ALC Max Atten", max98388_alc_max_atten_enum),
SOC_ENUM("ALC Debounce Time", max98388_alc_debouce_enum),
SOC_SINGLE("ALC Unmute Ramp Switch", MAX98388_R20E4_BP_ALC_MUTE,
MAX98388_ALC_UNMUTE_RAMP_EN_SHIFT, 1, 0),
SOC_SINGLE("ALC Mute Ramp Switch", MAX98388_R20E4_BP_ALC_MUTE,
MAX98388_ALC_MUTE_RAMP_EN_SHIFT, 1, 0),
SOC_SINGLE("ALC Mute Switch", MAX98388_R20E4_BP_ALC_MUTE,
MAX98388_ALC_MUTE_EN_SHIFT, 1, 0),
SOC_ENUM("ALC Mute Delay", max98388_alc_mute_delay_enum),
/* Speaker Monitor */
SOC_SINGLE("SPKMON Switch", MAX98388_R2037_ERR_MON_CTRL,
MAX98388_SPK_MON_SHIFT, 1, 0),
SOC_ENUM("SPKMON Thresh", max98388_spkmon_thresh_enum),
SOC_ENUM("SPKMON Load", max98388_spkmon_load_enum),
SOC_ENUM("SPKMON Duration", max98388_spkmon_duration_enum),
/* General Parameters */
SOC_ENUM("Fall Slew Rate", max98388_edge_rate_falling_enum),
SOC_ENUM("Rise Slew Rate", max98388_edge_rate_rising_enum),
SOC_SINGLE("AMP SSM Switch", MAX98388_R2093_SPK_AMP_SSM_CFG,
MAX98388_SPK_AMP_SSM_EN_SHIFT, 1, 0),
SOC_ENUM("AMP SSM Mod", max98388_ssm_mod_enum),
};
static const struct snd_soc_dapm_route max98388_audio_map[] = {
/* Plabyack */
{"DAI Sel Mux", "Left", "Amp Enable"},
{"DAI Sel Mux", "Right", "Amp Enable"},
{"DAI Sel Mux", "LeftRight", "Amp Enable"},
{"BE_OUT", NULL, "DAI Sel Mux"},
/* Capture */
{ "ADC Voltage", NULL, "VMON"},
{ "ADC Current", NULL, "IMON"},
{ "VI Sense", "Switch", "ADC Voltage"},
{ "VI Sense", "Switch", "ADC Current"},
{ "Voltage Sense", NULL, "VI Sense"},
{ "Current Sense", NULL, "VI Sense"},
};
static void max98388_reset(struct max98388_priv *max98388, struct device *dev)
{
int ret, reg, count;
/* Software Reset */
ret = regmap_update_bits(max98388->regmap,
MAX98388_R2000_SW_RESET,
MAX98388_SOFT_RESET,
MAX98388_SOFT_RESET);
if (ret)
dev_err(dev, "Reset command failed. (ret:%d)\n", ret);
count = 0;
while (count < 3) {
usleep_range(10000, 11000);
/* Software Reset Verification */
ret = regmap_read(max98388->regmap,
MAX98388_R22FF_REV_ID, ®);
if (!ret) {
dev_info(dev, "Reset completed (retry:%d)\n", count);
return;
}
count++;
}
dev_err(dev, "Reset failed. (ret:%d)\n", ret);
}
static int max98388_probe(struct snd_soc_component *component)
{
struct max98388_priv *max98388 = snd_soc_component_get_drvdata(component);
/* Software Reset */
max98388_reset(max98388, component->dev);
/* General channel source configuration */
regmap_write(max98388->regmap,
MAX98388_R2059_PCM_RX_SRC2,
0x10);
/* Enable DC blocker */
regmap_write(max98388->regmap,
MAX98388_R2091_SPK_CH_CFG,
0x1);
/* Enable IMON VMON DC blocker */
regmap_write(max98388->regmap,
MAX98388_R20A0_IV_DATA_DSP_CTRL,
0x3);
/* TX slot configuration */
regmap_write(max98388->regmap,
MAX98388_R2044_PCM_TX_CTRL1,
max98388->v_slot);
regmap_write(max98388->regmap,
MAX98388_R2045_PCM_TX_CTRL2,
max98388->i_slot);
/* Enable Auto-restart behavior by default */
regmap_write(max98388->regmap,
MAX98388_R210E_AUTO_RESTART, 0xF);
/* Set interleave mode */
if (max98388->interleave_mode)
regmap_update_bits(max98388->regmap,
MAX98388_R2040_PCM_MODE_CFG,
MAX98388_PCM_TX_CH_INTERLEAVE_MASK,
MAX98388_PCM_TX_CH_INTERLEAVE_MASK);
/* Speaker Amplifier Channel Enable */
regmap_update_bits(max98388->regmap,
MAX98388_R209F_SPK_CH_AMP_EN,
MAX98388_SPK_EN_MASK, 1);
return 0;
}
static int max98388_dai_set_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct max98388_priv *max98388 = snd_soc_component_get_drvdata(component);
unsigned int format = 0;
unsigned int invert = 0;
dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt);
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
invert = MAX98388_PCM_MODE_CFG_PCM_BCLKEDGE;
break;
default:
dev_err(component->dev, "DAI invert mode unsupported\n");
return -EINVAL;
}
regmap_update_bits(max98388->regmap,
MAX98388_R2041_PCM_CLK_SETUP,
MAX98388_PCM_MODE_CFG_PCM_BCLKEDGE,
invert);
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
format = MAX98388_PCM_FORMAT_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
format = MAX98388_PCM_FORMAT_LJ;
break;
case SND_SOC_DAIFMT_DSP_A:
format = MAX98388_PCM_FORMAT_TDM_MODE1;
break;
case SND_SOC_DAIFMT_DSP_B:
format = MAX98388_PCM_FORMAT_TDM_MODE0;
break;
default:
return -EINVAL;
}
regmap_update_bits(max98388->regmap,
MAX98388_R2040_PCM_MODE_CFG,
MAX98388_PCM_MODE_CFG_FORMAT_MASK,
format << MAX98388_PCM_MODE_CFG_FORMAT_SHIFT);
return 0;
}
/* BCLKs per LRCLK */
static const int bclk_sel_table[] = {
32, 48, 64, 96, 128, 192, 256, 384, 512, 320,
};
static int max98388_get_bclk_sel(int bclk)
{
int i;
/* match BCLKs per LRCLK */
for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) {
if (bclk_sel_table[i] == bclk)
return i + 2;
}
return 0;
}
static int max98388_set_clock(struct snd_soc_component *component,
struct snd_pcm_hw_params *params)
{
struct max98388_priv *max98388 = snd_soc_component_get_drvdata(component);
/* BCLK/LRCLK ratio calculation */
int blr_clk_ratio = params_channels(params) * max98388->ch_size;
int value;
if (!max98388->tdm_mode) {
/* BCLK configuration */
value = max98388_get_bclk_sel(blr_clk_ratio);
if (!value) {
dev_err(component->dev, "format unsupported %d\n",
params_format(params));
return -EINVAL;
}
regmap_update_bits(max98388->regmap,
MAX98388_R2041_PCM_CLK_SETUP,
MAX98388_PCM_CLK_SETUP_BSEL_MASK,
value);
}
return 0;
}
static int max98388_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct max98388_priv *max98388 = snd_soc_component_get_drvdata(component);
unsigned int sampling_rate = 0;
unsigned int chan_sz = 0;
int ret, reg;
int status = 0;
/* pcm mode configuration */
switch (snd_pcm_format_width(params_format(params))) {
case 16:
chan_sz = MAX98388_PCM_MODE_CFG_CHANSZ_16;
break;
case 24:
chan_sz = MAX98388_PCM_MODE_CFG_CHANSZ_24;
break;
case 32:
chan_sz = MAX98388_PCM_MODE_CFG_CHANSZ_32;
break;
default:
dev_err(component->dev, "format unsupported %d\n",
params_format(params));
goto err;
}
max98388->ch_size = snd_pcm_format_width(params_format(params));
ret = regmap_read(max98388->regmap,
MAX98388_R2040_PCM_MODE_CFG, ®);
if (ret < 0)
goto err;
/* GLOBAL_EN OFF prior to the channel size re-configure */
if (chan_sz != (reg & MAX98388_PCM_MODE_CFG_CHANSZ_MASK)) {
ret = regmap_read(max98388->regmap,
MAX98388_R210F_GLOBAL_EN, &status);
if (ret < 0)
goto err;
if (status) {
regmap_write(max98388->regmap,
MAX98388_R210F_GLOBAL_EN, 0);
usleep_range(30000, 31000);
}
regmap_update_bits(max98388->regmap,
MAX98388_R2040_PCM_MODE_CFG,
MAX98388_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
}
dev_dbg(component->dev, "format supported %d",
params_format(params));
/* sampling rate configuration */
switch (params_rate(params)) {
case 8000:
sampling_rate = MAX98388_PCM_SR_8000;
break;
case 11025:
sampling_rate = MAX98388_PCM_SR_11025;
break;
case 12000:
sampling_rate = MAX98388_PCM_SR_12000;
break;
case 16000:
sampling_rate = MAX98388_PCM_SR_16000;
break;
case 22050:
sampling_rate = MAX98388_PCM_SR_22050;
break;
case 24000:
sampling_rate = MAX98388_PCM_SR_24000;
break;
case 32000:
sampling_rate = MAX98388_PCM_SR_32000;
break;
case 44100:
sampling_rate = MAX98388_PCM_SR_44100;
break;
case 48000:
sampling_rate = MAX98388_PCM_SR_48000;
break;
case 88200:
sampling_rate = MAX98388_PCM_SR_88200;
break;
case 96000:
sampling_rate = MAX98388_PCM_SR_96000;
break;
default:
dev_err(component->dev, "rate %d not supported\n",
params_rate(params));
goto err;
}
/* set DAI_SR to correct LRCLK frequency */
regmap_update_bits(max98388->regmap,
MAX98388_R2042_PCM_SR_SETUP,
MAX98388_PCM_SR_MASK,
sampling_rate);
/* set sampling rate of IV */
if (max98388->interleave_mode &&
sampling_rate > MAX98388_PCM_SR_16000)
regmap_update_bits(max98388->regmap,
MAX98388_R2042_PCM_SR_SETUP,
MAX98388_PCM_SR_IV_MASK,
(sampling_rate - 3) << MAX98388_PCM_SR_IV_SHIFT);
else
regmap_update_bits(max98388->regmap,
MAX98388_R2042_PCM_SR_SETUP,
MAX98388_PCM_SR_IV_MASK,
sampling_rate << MAX98388_PCM_SR_IV_SHIFT);
ret = max98388_set_clock(component, params);
if (status) {
regmap_write(max98388->regmap,
MAX98388_R210F_GLOBAL_EN, 1);
usleep_range(30000, 31000);
}
return ret;
err:
return -EINVAL;
}
#define MAX_NUM_SLOTS 16
#define MAX_NUM_CH 2
static int max98388_dai_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask,
int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
struct max98388_priv *max98388 = snd_soc_component_get_drvdata(component);
int bsel = 0;
unsigned int chan_sz = 0;
unsigned int mask;
int cnt, slot_found;
int addr, bits;
if (!tx_mask && !rx_mask && !slots && !slot_width)
max98388->tdm_mode = false;
else
max98388->tdm_mode = true;
/* BCLK configuration */
bsel = max98388_get_bclk_sel(slots * slot_width);
if (bsel == 0) {
dev_err(component->dev, "BCLK %d not supported\n",
slots * slot_width);
return -EINVAL;
}
regmap_update_bits(max98388->regmap,
MAX98388_R2041_PCM_CLK_SETUP,
MAX98388_PCM_CLK_SETUP_BSEL_MASK,
bsel);
/* Channel size configuration */
switch (slot_width) {
case 16:
chan_sz = MAX98388_PCM_MODE_CFG_CHANSZ_16;
break;
case 24:
chan_sz = MAX98388_PCM_MODE_CFG_CHANSZ_24;
break;
case 32:
chan_sz = MAX98388_PCM_MODE_CFG_CHANSZ_32;
break;
default:
dev_err(component->dev, "format unsupported %d\n",
slot_width);
return -EINVAL;
}
regmap_update_bits(max98388->regmap,
MAX98388_R2040_PCM_MODE_CFG,
MAX98388_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
/* Rx slot configuration */
slot_found = 0;
mask = rx_mask;
for (cnt = 0 ; cnt < MAX_NUM_SLOTS ; cnt++, mask >>= 1) {
if (mask & 0x1) {
if (slot_found == 0)
regmap_update_bits(max98388->regmap,
MAX98388_R2059_PCM_RX_SRC2,
MAX98388_RX_SRC_CH0_SHIFT,
cnt);
else
regmap_update_bits(max98388->regmap,
MAX98388_R2059_PCM_RX_SRC2,
MAX98388_RX_SRC_CH1_SHIFT,
cnt);
slot_found++;
if (slot_found >= MAX_NUM_CH)
break;
}
}
/* speaker feedback slot configuration */
slot_found = 0;
mask = tx_mask;
for (cnt = 0 ; cnt < MAX_NUM_SLOTS ; cnt++, mask >>= 1) {
if (mask & 0x1) {
addr = MAX98388_R2044_PCM_TX_CTRL1 + (cnt / 8);
bits = cnt % 8;
regmap_update_bits(max98388->regmap, addr, bits, bits);
if (slot_found >= MAX_NUM_CH)
break;
}
}
return 0;
}
#define MAX98388_RATES SNDRV_PCM_RATE_8000_96000
#define MAX98388_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops max98388_dai_ops = {
.set_fmt = max98388_dai_set_fmt,
.hw_params = max98388_dai_hw_params,
.set_tdm_slot = max98388_dai_tdm_slot,
};
static bool max98388_readable_register(struct device *dev,
unsigned int reg)
{
switch (reg) {
case MAX98388_R2001_INT_RAW1 ... MAX98388_R2002_INT_RAW2:
case MAX98388_R2004_INT_STATE1... MAX98388_R2005_INT_STATE2:
case MAX98388_R2020_THERM_WARN_THRESH:
case MAX98388_R2031_SPK_MON_THRESH
... MAX98388_R2033_SPK_MON_DURATION:
case MAX98388_R2037_ERR_MON_CTRL:
case MAX98388_R2040_PCM_MODE_CFG
... MAX98388_R2042_PCM_SR_SETUP:
case MAX98388_R2044_PCM_TX_CTRL1
... MAX98388_R2045_PCM_TX_CTRL2:
case MAX98388_R2050_PCM_TX_HIZ_CTRL1
... MAX98388_R2059_PCM_RX_SRC2:
case MAX98388_R205C_PCM_TX_DRIVE_STRENGTH
... MAX98388_R205F_PCM_TX_EN:
case MAX98388_R2090_SPK_CH_VOL_CTRL
... MAX98388_R2094_SPK_AMP_ER_CTRL:
case MAX98388_R209E_SPK_CH_PINK_NOISE_EN
... MAX98388_R209F_SPK_CH_AMP_EN:
case MAX98388_R20A0_IV_DATA_DSP_CTRL:
case MAX98388_R20A7_IV_DATA_EN:
case MAX98388_R20E0_BP_ALC_THRESH ... MAX98388_R20E4_BP_ALC_MUTE:
case MAX98388_R20EE_BP_INF_HOLD_REL ... MAX98388_R20EF_BP_ALC_EN:
case MAX98388_R210E_AUTO_RESTART:
case MAX98388_R210F_GLOBAL_EN:
case MAX98388_R22FF_REV_ID:
return true;
default:
return false;
}
};
static bool max98388_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX98388_R2001_INT_RAW1 ... MAX98388_R2005_INT_STATE2:
case MAX98388_R210F_GLOBAL_EN:
case MAX98388_R22FF_REV_ID:
return true;
default:
return false;
}
}
static struct snd_soc_dai_driver max98388_dai[] = {
{
.name = "max98388-aif1",
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MAX98388_RATES,
.formats = MAX98388_FORMATS,
},
.capture = {
.stream_name = "HiFi Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MAX98388_RATES,
.formats = MAX98388_FORMATS,
},
.ops = &max98388_dai_ops,
}
};
static int max98388_suspend(struct device *dev)
{
struct max98388_priv *max98388 = dev_get_drvdata(dev);
regcache_cache_only(max98388->regmap, true);
regcache_mark_dirty(max98388->regmap);
return 0;
}
static int max98388_resume(struct device *dev)
{
struct max98388_priv *max98388 = dev_get_drvdata(dev);
regcache_cache_only(max98388->regmap, false);
max98388_reset(max98388, dev);
regcache_sync(max98388->regmap);
return 0;
}
static const struct dev_pm_ops max98388_pm = {
SYSTEM_SLEEP_PM_OPS(max98388_suspend, max98388_resume)
};
static const struct regmap_config max98388_regmap = {
.reg_bits = 16,
.val_bits = 8,
.max_register = MAX98388_R22FF_REV_ID,
.reg_defaults = max98388_reg,
.num_reg_defaults = ARRAY_SIZE(max98388_reg),
.readable_reg = max98388_readable_register,
.volatile_reg = max98388_volatile_reg,
.cache_type = REGCACHE_RBTREE,
};
static const struct snd_soc_component_driver soc_codec_dev_max98388 = {
.probe = max98388_probe,
.controls = max98388_snd_controls,
.num_controls = ARRAY_SIZE(max98388_snd_controls),
.dapm_widgets = max98388_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(max98388_dapm_widgets),
.dapm_routes = max98388_audio_map,
.num_dapm_routes = ARRAY_SIZE(max98388_audio_map),
.use_pmdown_time = 1,
.endianness = 1,
};
static void max98388_read_deveice_property(struct device *dev,
struct max98388_priv *max98388)
{
int value;
if (!device_property_read_u32(dev, "adi,vmon-slot-no", &value))
max98388->v_slot = value & 0xF;
else
max98388->v_slot = 0;
if (!device_property_read_u32(dev, "adi,imon-slot-no", &value))
max98388->i_slot = value & 0xF;
else
max98388->i_slot = 1;
if (device_property_read_bool(dev, "adi,interleave-mode"))
max98388->interleave_mode = true;
else
max98388->interleave_mode = false;
}
static int max98388_i2c_probe(struct i2c_client *i2c)
{
int ret = 0;
int reg = 0;
struct max98388_priv *max98388 = NULL;
max98388 = devm_kzalloc(&i2c->dev, sizeof(*max98388), GFP_KERNEL);
if (!max98388)
return -ENOMEM;
i2c_set_clientdata(i2c, max98388);
/* regmap initialization */
max98388->regmap = devm_regmap_init_i2c(i2c, &max98388_regmap);
if (IS_ERR(max98388->regmap))
return dev_err_probe(&i2c->dev, PTR_ERR(max98388->regmap),
"Failed to allocate register map.\n");
/* voltage/current slot & gpio configuration */
max98388_read_deveice_property(&i2c->dev, max98388);
/* Device Reset */
max98388->reset_gpio = devm_gpiod_get_optional(&i2c->dev,
"reset", GPIOD_OUT_HIGH);
if (IS_ERR(max98388->reset_gpio))
return dev_err_probe(&i2c->dev, PTR_ERR(max98388->reset_gpio),
"Unable to request GPIO\n");
if (max98388->reset_gpio) {
usleep_range(5000, 6000);
gpiod_set_value_cansleep(max98388->reset_gpio, 0);
/* Wait for the hw reset done */
usleep_range(5000, 6000);
}
/* Read Revision ID */
ret = regmap_read(max98388->regmap,
MAX98388_R22FF_REV_ID, ®);
if (ret < 0)
return dev_err_probe(&i2c->dev, ret,
"Failed to read the revision ID\n");
dev_info(&i2c->dev, "MAX98388 revisionID: 0x%02X\n", reg);
/* codec registration */
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_codec_dev_max98388,
max98388_dai,
ARRAY_SIZE(max98388_dai));
if (ret < 0)
dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
return ret;
}
static const struct i2c_device_id max98388_i2c_id[] = {
{ "max98388", 0},
{ },
};
MODULE_DEVICE_TABLE(i2c, max98388_i2c_id);
static const struct of_device_id max98388_of_match[] = {
{ .compatible = "adi,max98388", },
{ }
};
MODULE_DEVICE_TABLE(of, max98388_of_match);
static const struct acpi_device_id max98388_acpi_match[] = {
{ "ADS8388", 0 },
{},
};
MODULE_DEVICE_TABLE(acpi, max98388_acpi_match);
static struct i2c_driver max98388_i2c_driver = {
.driver = {
.name = "max98388",
.of_match_table = max98388_of_match,
.acpi_match_table = max98388_acpi_match,
.pm = pm_sleep_ptr(&max98388_pm),
},
.probe = max98388_i2c_probe,
.id_table = max98388_i2c_id,
};
module_i2c_driver(max98388_i2c_driver)
MODULE_DESCRIPTION("ALSA SoC MAX98388 driver");
MODULE_AUTHOR("Ryan Lee <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/max98388.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* cs42l83-i2c.c -- CS42L83 ALSA SoC audio driver for I2C
*
* Based on cs42l42-i2c.c:
* Copyright 2016, 2022 Cirrus Logic, Inc.
*/
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/types.h>
#include "cs42l42.h"
static const struct reg_default cs42l83_reg_defaults[] = {
{ CS42L42_FRZ_CTL, 0x00 },
{ CS42L42_SRC_CTL, 0x10 },
{ CS42L42_MCLK_CTL, 0x00 }, /* <- only deviation from CS42L42 */
{ CS42L42_SFTRAMP_RATE, 0xA4 },
{ CS42L42_SLOW_START_ENABLE, 0x70 },
{ CS42L42_I2C_DEBOUNCE, 0x88 },
{ CS42L42_I2C_STRETCH, 0x03 },
{ CS42L42_I2C_TIMEOUT, 0xB7 },
{ CS42L42_PWR_CTL1, 0xFF },
{ CS42L42_PWR_CTL2, 0x84 },
{ CS42L42_PWR_CTL3, 0x20 },
{ CS42L42_RSENSE_CTL1, 0x40 },
{ CS42L42_RSENSE_CTL2, 0x00 },
{ CS42L42_OSC_SWITCH, 0x00 },
{ CS42L42_RSENSE_CTL3, 0x1B },
{ CS42L42_TSENSE_CTL, 0x1B },
{ CS42L42_TSRS_INT_DISABLE, 0x00 },
{ CS42L42_HSDET_CTL1, 0x77 },
{ CS42L42_HSDET_CTL2, 0x00 },
{ CS42L42_HS_SWITCH_CTL, 0xF3 },
{ CS42L42_HS_CLAMP_DISABLE, 0x00 },
{ CS42L42_MCLK_SRC_SEL, 0x00 },
{ CS42L42_SPDIF_CLK_CFG, 0x00 },
{ CS42L42_FSYNC_PW_LOWER, 0x00 },
{ CS42L42_FSYNC_PW_UPPER, 0x00 },
{ CS42L42_FSYNC_P_LOWER, 0xF9 },
{ CS42L42_FSYNC_P_UPPER, 0x00 },
{ CS42L42_ASP_CLK_CFG, 0x00 },
{ CS42L42_ASP_FRM_CFG, 0x10 },
{ CS42L42_FS_RATE_EN, 0x00 },
{ CS42L42_IN_ASRC_CLK, 0x00 },
{ CS42L42_OUT_ASRC_CLK, 0x00 },
{ CS42L42_PLL_DIV_CFG1, 0x00 },
{ CS42L42_ADC_OVFL_INT_MASK, 0x01 },
{ CS42L42_MIXER_INT_MASK, 0x0F },
{ CS42L42_SRC_INT_MASK, 0x0F },
{ CS42L42_ASP_RX_INT_MASK, 0x1F },
{ CS42L42_ASP_TX_INT_MASK, 0x0F },
{ CS42L42_CODEC_INT_MASK, 0x03 },
{ CS42L42_SRCPL_INT_MASK, 0x7F },
{ CS42L42_VPMON_INT_MASK, 0x01 },
{ CS42L42_PLL_LOCK_INT_MASK, 0x01 },
{ CS42L42_TSRS_PLUG_INT_MASK, 0x0F },
{ CS42L42_PLL_CTL1, 0x00 },
{ CS42L42_PLL_DIV_FRAC0, 0x00 },
{ CS42L42_PLL_DIV_FRAC1, 0x00 },
{ CS42L42_PLL_DIV_FRAC2, 0x00 },
{ CS42L42_PLL_DIV_INT, 0x40 },
{ CS42L42_PLL_CTL3, 0x10 },
{ CS42L42_PLL_CAL_RATIO, 0x80 },
{ CS42L42_PLL_CTL4, 0x03 },
{ CS42L42_LOAD_DET_EN, 0x00 },
{ CS42L42_HSBIAS_SC_AUTOCTL, 0x03 },
{ CS42L42_WAKE_CTL, 0xC0 },
{ CS42L42_ADC_DISABLE_MUTE, 0x00 },
{ CS42L42_TIPSENSE_CTL, 0x02 },
{ CS42L42_MISC_DET_CTL, 0x03 },
{ CS42L42_MIC_DET_CTL1, 0x1F },
{ CS42L42_MIC_DET_CTL2, 0x2F },
{ CS42L42_DET_INT1_MASK, 0xE0 },
{ CS42L42_DET_INT2_MASK, 0xFF },
{ CS42L42_HS_BIAS_CTL, 0xC2 },
{ CS42L42_ADC_CTL, 0x00 },
{ CS42L42_ADC_VOLUME, 0x00 },
{ CS42L42_ADC_WNF_HPF_CTL, 0x71 },
{ CS42L42_DAC_CTL1, 0x00 },
{ CS42L42_DAC_CTL2, 0x02 },
{ CS42L42_HP_CTL, 0x0D },
{ CS42L42_CLASSH_CTL, 0x07 },
{ CS42L42_MIXER_CHA_VOL, 0x3F },
{ CS42L42_MIXER_ADC_VOL, 0x3F },
{ CS42L42_MIXER_CHB_VOL, 0x3F },
{ CS42L42_EQ_COEF_IN0, 0x00 },
{ CS42L42_EQ_COEF_IN1, 0x00 },
{ CS42L42_EQ_COEF_IN2, 0x00 },
{ CS42L42_EQ_COEF_IN3, 0x00 },
{ CS42L42_EQ_COEF_RW, 0x00 },
{ CS42L42_EQ_COEF_OUT0, 0x00 },
{ CS42L42_EQ_COEF_OUT1, 0x00 },
{ CS42L42_EQ_COEF_OUT2, 0x00 },
{ CS42L42_EQ_COEF_OUT3, 0x00 },
{ CS42L42_EQ_INIT_STAT, 0x00 },
{ CS42L42_EQ_START_FILT, 0x00 },
{ CS42L42_EQ_MUTE_CTL, 0x00 },
{ CS42L42_SP_RX_CH_SEL, 0x04 },
{ CS42L42_SP_RX_ISOC_CTL, 0x04 },
{ CS42L42_SP_RX_FS, 0x8C },
{ CS42l42_SPDIF_CH_SEL, 0x0E },
{ CS42L42_SP_TX_ISOC_CTL, 0x04 },
{ CS42L42_SP_TX_FS, 0xCC },
{ CS42L42_SPDIF_SW_CTL1, 0x3F },
{ CS42L42_SRC_SDIN_FS, 0x40 },
{ CS42L42_SRC_SDOUT_FS, 0x40 },
{ CS42L42_SPDIF_CTL1, 0x01 },
{ CS42L42_SPDIF_CTL2, 0x00 },
{ CS42L42_SPDIF_CTL3, 0x00 },
{ CS42L42_SPDIF_CTL4, 0x42 },
{ CS42L42_ASP_TX_SZ_EN, 0x00 },
{ CS42L42_ASP_TX_CH_EN, 0x00 },
{ CS42L42_ASP_TX_CH_AP_RES, 0x0F },
{ CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 },
{ CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 },
{ CS42L42_ASP_TX_HIZ_DLY_CFG, 0x00 },
{ CS42L42_ASP_TX_CH2_BIT_MSB, 0x00 },
{ CS42L42_ASP_TX_CH2_BIT_LSB, 0x00 },
{ CS42L42_ASP_RX_DAI0_EN, 0x00 },
{ CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x03 },
{ CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 },
{ CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x00 },
{ CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x03 },
{ CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 },
{ CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0x00 },
{ CS42L42_ASP_RX_DAI0_CH3_AP_RES, 0x03 },
{ CS42L42_ASP_RX_DAI0_CH3_BIT_MSB, 0x00 },
{ CS42L42_ASP_RX_DAI0_CH3_BIT_LSB, 0x00 },
{ CS42L42_ASP_RX_DAI0_CH4_AP_RES, 0x03 },
{ CS42L42_ASP_RX_DAI0_CH4_BIT_MSB, 0x00 },
{ CS42L42_ASP_RX_DAI0_CH4_BIT_LSB, 0x00 },
{ CS42L42_ASP_RX_DAI1_CH1_AP_RES, 0x03 },
{ CS42L42_ASP_RX_DAI1_CH1_BIT_MSB, 0x00 },
{ CS42L42_ASP_RX_DAI1_CH1_BIT_LSB, 0x00 },
{ CS42L42_ASP_RX_DAI1_CH2_AP_RES, 0x03 },
{ CS42L42_ASP_RX_DAI1_CH2_BIT_MSB, 0x00 },
{ CS42L42_ASP_RX_DAI1_CH2_BIT_LSB, 0x00 },
};
/*
* This is all the same as for CS42L42 but we
* replace the on-reset register defaults.
*/
static const struct regmap_config cs42l83_regmap = {
.reg_bits = 8,
.val_bits = 8,
.readable_reg = cs42l42_readable_register,
.volatile_reg = cs42l42_volatile_register,
.ranges = &cs42l42_page_range,
.num_ranges = 1,
.max_register = CS42L42_MAX_REGISTER,
.reg_defaults = cs42l83_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(cs42l83_reg_defaults),
.cache_type = REGCACHE_MAPLE,
.use_single_read = true,
.use_single_write = true,
};
static int cs42l83_i2c_probe(struct i2c_client *i2c_client)
{
struct device *dev = &i2c_client->dev;
struct cs42l42_private *cs42l83;
struct regmap *regmap;
int ret;
cs42l83 = devm_kzalloc(dev, sizeof(*cs42l83), GFP_KERNEL);
if (!cs42l83)
return -ENOMEM;
regmap = devm_regmap_init_i2c(i2c_client, &cs42l83_regmap);
if (IS_ERR(regmap))
return dev_err_probe(&i2c_client->dev, PTR_ERR(regmap),
"regmap_init() failed\n");
cs42l83->devid = CS42L83_CHIP_ID;
cs42l83->dev = dev;
cs42l83->regmap = regmap;
cs42l83->irq = i2c_client->irq;
ret = cs42l42_common_probe(cs42l83, &cs42l42_soc_component, &cs42l42_dai);
if (ret)
return ret;
return cs42l42_init(cs42l83);
}
static void cs42l83_i2c_remove(struct i2c_client *i2c_client)
{
struct cs42l42_private *cs42l83 = dev_get_drvdata(&i2c_client->dev);
cs42l42_common_remove(cs42l83);
}
static int __maybe_unused cs42l83_i2c_resume(struct device *dev)
{
int ret;
ret = cs42l42_resume(dev);
if (ret)
return ret;
cs42l42_resume_restore(dev);
return 0;
}
static const struct dev_pm_ops cs42l83_i2c_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(cs42l42_suspend, cs42l83_i2c_resume)
};
static const struct of_device_id __maybe_unused cs42l83_of_match[] = {
{ .compatible = "cirrus,cs42l83", },
{}
};
MODULE_DEVICE_TABLE(of, cs42l83_of_match);
static struct i2c_driver cs42l83_i2c_driver = {
.driver = {
.name = "cs42l83",
.pm = &cs42l83_i2c_pm_ops,
.of_match_table = of_match_ptr(cs42l83_of_match),
},
.probe = cs42l83_i2c_probe,
.remove = cs42l83_i2c_remove,
};
module_i2c_driver(cs42l83_i2c_driver);
MODULE_DESCRIPTION("ASoC CS42L83 I2C driver");
MODULE_AUTHOR("Martin Povišer <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_IMPORT_NS(SND_SOC_CS42L42_CORE);
| linux-master | sound/soc/codecs/cs42l83-i2c.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8997.c -- WM8997 ALSA SoC Audio driver
*
* Copyright 2012 Wolfson Microelectronics plc
*
* Author: Charles Keepax <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/jack.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <linux/mfd/arizona/core.h>
#include <linux/mfd/arizona/registers.h>
#include "arizona.h"
#include "wm8997.h"
struct wm8997_priv {
struct arizona_priv core;
struct arizona_fll fll[2];
};
static DECLARE_TLV_DB_SCALE(ana_tlv, 0, 100, 0);
static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0);
static DECLARE_TLV_DB_SCALE(noise_tlv, -13200, 600, 0);
static DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
static const struct reg_default wm8997_sysclk_reva_patch[] = {
{ 0x301D, 0x7B15 },
{ 0x301B, 0x0050 },
{ 0x305D, 0x7B17 },
{ 0x305B, 0x0050 },
{ 0x3001, 0x08FE },
{ 0x3003, 0x00F4 },
{ 0x3041, 0x08FF },
{ 0x3043, 0x0005 },
{ 0x3020, 0x0225 },
{ 0x3021, 0x0A00 },
{ 0x3022, 0xE24D },
{ 0x3023, 0x0800 },
{ 0x3024, 0xE24D },
{ 0x3025, 0xF000 },
{ 0x3060, 0x0226 },
{ 0x3061, 0x0A00 },
{ 0x3062, 0xE252 },
{ 0x3063, 0x0800 },
{ 0x3064, 0xE252 },
{ 0x3065, 0xF000 },
{ 0x3116, 0x022B },
{ 0x3117, 0xFA00 },
{ 0x3110, 0x246C },
{ 0x3111, 0x0A03 },
{ 0x3112, 0x246E },
{ 0x3113, 0x0A03 },
{ 0x3114, 0x2470 },
{ 0x3115, 0x0A03 },
{ 0x3126, 0x246C },
{ 0x3127, 0x0A02 },
{ 0x3128, 0x246E },
{ 0x3129, 0x0A02 },
{ 0x312A, 0x2470 },
{ 0x312B, 0xFA02 },
{ 0x3125, 0x0800 },
};
static int wm8997_sysclk_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct arizona *arizona = dev_get_drvdata(component->dev->parent);
struct regmap *regmap = arizona->regmap;
const struct reg_default *patch = NULL;
int i, patch_size;
switch (arizona->rev) {
case 0:
patch = wm8997_sysclk_reva_patch;
patch_size = ARRAY_SIZE(wm8997_sysclk_reva_patch);
break;
default:
break;
}
switch (event) {
case SND_SOC_DAPM_POST_PMU:
if (patch)
for (i = 0; i < patch_size; i++)
regmap_write_async(regmap, patch[i].reg,
patch[i].def);
break;
case SND_SOC_DAPM_PRE_PMD:
break;
case SND_SOC_DAPM_PRE_PMU:
case SND_SOC_DAPM_POST_PMD:
return arizona_clk_ev(w, kcontrol, event);
default:
return 0;
}
return arizona_dvfs_sysclk_ev(w, kcontrol, event);
}
static const char * const wm8997_osr_text[] = {
"Low power", "Normal", "High performance",
};
static const unsigned int wm8997_osr_val[] = {
0x0, 0x3, 0x5,
};
static const struct soc_enum wm8997_hpout_osr[] = {
SOC_VALUE_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_1L,
ARIZONA_OUT1_OSR_SHIFT, 0x7,
ARRAY_SIZE(wm8997_osr_text),
wm8997_osr_text, wm8997_osr_val),
SOC_VALUE_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_3L,
ARIZONA_OUT3_OSR_SHIFT, 0x7,
ARRAY_SIZE(wm8997_osr_text),
wm8997_osr_text, wm8997_osr_val),
};
#define WM8997_NG_SRC(name, base) \
SOC_SINGLE(name " NG HPOUT1L Switch", base, 0, 1, 0), \
SOC_SINGLE(name " NG HPOUT1R Switch", base, 1, 1, 0), \
SOC_SINGLE(name " NG EPOUT Switch", base, 4, 1, 0), \
SOC_SINGLE(name " NG SPKOUT Switch", base, 6, 1, 0), \
SOC_SINGLE(name " NG SPKDAT1L Switch", base, 8, 1, 0), \
SOC_SINGLE(name " NG SPKDAT1R Switch", base, 9, 1, 0)
static const struct snd_kcontrol_new wm8997_snd_controls[] = {
SOC_SINGLE("IN1 High Performance Switch", ARIZONA_IN1L_CONTROL,
ARIZONA_IN1_OSR_SHIFT, 1, 0),
SOC_SINGLE("IN2 High Performance Switch", ARIZONA_IN2L_CONTROL,
ARIZONA_IN2_OSR_SHIFT, 1, 0),
SOC_SINGLE_RANGE_TLV("IN1L Volume", ARIZONA_IN1L_CONTROL,
ARIZONA_IN1L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv),
SOC_SINGLE_RANGE_TLV("IN1R Volume", ARIZONA_IN1R_CONTROL,
ARIZONA_IN1R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv),
SOC_SINGLE_RANGE_TLV("IN2L Volume", ARIZONA_IN2L_CONTROL,
ARIZONA_IN2L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv),
SOC_SINGLE_RANGE_TLV("IN2R Volume", ARIZONA_IN2R_CONTROL,
ARIZONA_IN2R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv),
SOC_SINGLE_TLV("IN1L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1L,
ARIZONA_IN1L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
SOC_SINGLE_TLV("IN1R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1R,
ARIZONA_IN1R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
SOC_SINGLE_TLV("IN2L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2L,
ARIZONA_IN2L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
SOC_SINGLE_TLV("IN2R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2R,
ARIZONA_IN2R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
SOC_ENUM("Input Ramp Up", arizona_in_vi_ramp),
SOC_ENUM("Input Ramp Down", arizona_in_vd_ramp),
ARIZONA_MIXER_CONTROLS("EQ1", ARIZONA_EQ1MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("EQ2", ARIZONA_EQ2MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("EQ3", ARIZONA_EQ3MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("EQ4", ARIZONA_EQ4MIX_INPUT_1_SOURCE),
ARIZONA_EQ_CONTROL("EQ1 Coefficients", ARIZONA_EQ1_2),
SOC_SINGLE_TLV("EQ1 B1 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B1_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ1 B2 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B2_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ1 B3 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B3_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ1 B4 Volume", ARIZONA_EQ1_2, ARIZONA_EQ1_B4_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ1 B5 Volume", ARIZONA_EQ1_2, ARIZONA_EQ1_B5_GAIN_SHIFT,
24, 0, eq_tlv),
ARIZONA_EQ_CONTROL("EQ2 Coefficients", ARIZONA_EQ2_2),
SOC_SINGLE_TLV("EQ2 B1 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B1_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ2 B2 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B2_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ2 B3 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B3_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ2 B4 Volume", ARIZONA_EQ2_2, ARIZONA_EQ2_B4_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ2 B5 Volume", ARIZONA_EQ2_2, ARIZONA_EQ2_B5_GAIN_SHIFT,
24, 0, eq_tlv),
ARIZONA_EQ_CONTROL("EQ3 Coefficients", ARIZONA_EQ3_2),
SOC_SINGLE_TLV("EQ3 B1 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B1_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ3 B2 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B2_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ3 B3 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B3_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ3 B4 Volume", ARIZONA_EQ3_2, ARIZONA_EQ3_B4_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ3 B5 Volume", ARIZONA_EQ3_2, ARIZONA_EQ3_B5_GAIN_SHIFT,
24, 0, eq_tlv),
ARIZONA_EQ_CONTROL("EQ4 Coefficients", ARIZONA_EQ4_2),
SOC_SINGLE_TLV("EQ4 B1 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B1_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ4 B2 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B2_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ4 B3 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B3_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ4 B4 Volume", ARIZONA_EQ4_2, ARIZONA_EQ4_B4_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ4 B5 Volume", ARIZONA_EQ4_2, ARIZONA_EQ4_B5_GAIN_SHIFT,
24, 0, eq_tlv),
ARIZONA_MIXER_CONTROLS("DRC1L", ARIZONA_DRC1LMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("DRC1R", ARIZONA_DRC1RMIX_INPUT_1_SOURCE),
SND_SOC_BYTES_MASK("DRC1", ARIZONA_DRC1_CTRL1, 5,
ARIZONA_DRC1R_ENA | ARIZONA_DRC1L_ENA),
ARIZONA_MIXER_CONTROLS("LHPF1", ARIZONA_HPLP1MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("LHPF2", ARIZONA_HPLP2MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("LHPF3", ARIZONA_HPLP3MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("LHPF4", ARIZONA_HPLP4MIX_INPUT_1_SOURCE),
SOC_ENUM("LHPF1 Mode", arizona_lhpf1_mode),
SOC_ENUM("LHPF2 Mode", arizona_lhpf2_mode),
SOC_ENUM("LHPF3 Mode", arizona_lhpf3_mode),
SOC_ENUM("LHPF4 Mode", arizona_lhpf4_mode),
ARIZONA_LHPF_CONTROL("LHPF1 Coefficients", ARIZONA_HPLPF1_2),
ARIZONA_LHPF_CONTROL("LHPF2 Coefficients", ARIZONA_HPLPF2_2),
ARIZONA_LHPF_CONTROL("LHPF3 Coefficients", ARIZONA_HPLPF3_2),
ARIZONA_LHPF_CONTROL("LHPF4 Coefficients", ARIZONA_HPLPF4_2),
SOC_ENUM("ISRC1 FSL", arizona_isrc_fsl[0]),
SOC_ENUM("ISRC2 FSL", arizona_isrc_fsl[1]),
ARIZONA_MIXER_CONTROLS("Mic", ARIZONA_MICMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("Noise", ARIZONA_NOISEMIX_INPUT_1_SOURCE),
SOC_SINGLE_TLV("Noise Generator Volume", ARIZONA_COMFORT_NOISE_GENERATOR,
ARIZONA_NOISE_GEN_GAIN_SHIFT, 0x16, 0, noise_tlv),
ARIZONA_MIXER_CONTROLS("HPOUT1L", ARIZONA_OUT1LMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("HPOUT1R", ARIZONA_OUT1RMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("EPOUT", ARIZONA_OUT3LMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SPKOUT", ARIZONA_OUT4LMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SPKDAT1L", ARIZONA_OUT5LMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SPKDAT1R", ARIZONA_OUT5RMIX_INPUT_1_SOURCE),
SOC_SINGLE("Speaker High Performance Switch", ARIZONA_OUTPUT_PATH_CONFIG_4L,
ARIZONA_OUT4_OSR_SHIFT, 1, 0),
SOC_SINGLE("SPKDAT1 High Performance Switch", ARIZONA_OUTPUT_PATH_CONFIG_5L,
ARIZONA_OUT5_OSR_SHIFT, 1, 0),
SOC_DOUBLE_R("HPOUT1 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_1L,
ARIZONA_DAC_DIGITAL_VOLUME_1R, ARIZONA_OUT1L_MUTE_SHIFT, 1, 1),
SOC_SINGLE("EPOUT Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_3L,
ARIZONA_OUT3L_MUTE_SHIFT, 1, 1),
SOC_SINGLE("Speaker Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_4L,
ARIZONA_OUT4L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R("SPKDAT1 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_5L,
ARIZONA_DAC_DIGITAL_VOLUME_5R, ARIZONA_OUT5L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_1L,
ARIZONA_DAC_DIGITAL_VOLUME_1R, ARIZONA_OUT1L_VOL_SHIFT,
0xbf, 0, digital_tlv),
SOC_SINGLE_TLV("EPOUT Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_3L,
ARIZONA_OUT3L_VOL_SHIFT, 0xbf, 0, digital_tlv),
SOC_SINGLE_TLV("Speaker Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_4L,
ARIZONA_OUT4L_VOL_SHIFT, 0xbf, 0, digital_tlv),
SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_5L,
ARIZONA_DAC_DIGITAL_VOLUME_5R, ARIZONA_OUT5L_VOL_SHIFT,
0xbf, 0, digital_tlv),
SOC_ENUM("HPOUT1 OSR", wm8997_hpout_osr[0]),
SOC_ENUM("EPOUT OSR", wm8997_hpout_osr[1]),
SOC_ENUM("Output Ramp Up", arizona_out_vi_ramp),
SOC_ENUM("Output Ramp Down", arizona_out_vd_ramp),
SOC_DOUBLE("SPKDAT1 Switch", ARIZONA_PDM_SPK1_CTRL_1, ARIZONA_SPK1L_MUTE_SHIFT,
ARIZONA_SPK1R_MUTE_SHIFT, 1, 1),
SOC_SINGLE("Noise Gate Switch", ARIZONA_NOISE_GATE_CONTROL,
ARIZONA_NGATE_ENA_SHIFT, 1, 0),
SOC_SINGLE_TLV("Noise Gate Threshold Volume", ARIZONA_NOISE_GATE_CONTROL,
ARIZONA_NGATE_THR_SHIFT, 7, 1, ng_tlv),
SOC_ENUM("Noise Gate Hold", arizona_ng_hold),
WM8997_NG_SRC("HPOUT1L", ARIZONA_NOISE_GATE_SELECT_1L),
WM8997_NG_SRC("HPOUT1R", ARIZONA_NOISE_GATE_SELECT_1R),
WM8997_NG_SRC("EPOUT", ARIZONA_NOISE_GATE_SELECT_3L),
WM8997_NG_SRC("SPKOUT", ARIZONA_NOISE_GATE_SELECT_4L),
WM8997_NG_SRC("SPKDAT1L", ARIZONA_NOISE_GATE_SELECT_5L),
WM8997_NG_SRC("SPKDAT1R", ARIZONA_NOISE_GATE_SELECT_5R),
ARIZONA_MIXER_CONTROLS("AIF1TX1", ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF1TX2", ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF1TX3", ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF1TX4", ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF1TX5", ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF1TX6", ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF1TX7", ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF1TX8", ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF2TX1", ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF2TX2", ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SLIMTX1", ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SLIMTX2", ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SLIMTX3", ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SLIMTX4", ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SLIMTX5", ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SLIMTX6", ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SLIMTX7", ARIZONA_SLIMTX7MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SLIMTX8", ARIZONA_SLIMTX8MIX_INPUT_1_SOURCE),
};
ARIZONA_MIXER_ENUMS(EQ1, ARIZONA_EQ1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(EQ2, ARIZONA_EQ2MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(EQ3, ARIZONA_EQ3MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(EQ4, ARIZONA_EQ4MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(DRC1L, ARIZONA_DRC1LMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(DRC1R, ARIZONA_DRC1RMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(LHPF1, ARIZONA_HPLP1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(LHPF2, ARIZONA_HPLP2MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(LHPF3, ARIZONA_HPLP3MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(LHPF4, ARIZONA_HPLP4MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(Mic, ARIZONA_MICMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(Noise, ARIZONA_NOISEMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(PWM1, ARIZONA_PWM1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(PWM2, ARIZONA_PWM2MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(OUT1L, ARIZONA_OUT1LMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(OUT1R, ARIZONA_OUT1RMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(OUT3, ARIZONA_OUT3LMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SPKOUT, ARIZONA_OUT4LMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SPKDAT1L, ARIZONA_OUT5LMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SPKDAT1R, ARIZONA_OUT5RMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX1, ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX2, ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX3, ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX4, ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX5, ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX6, ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX7, ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX8, ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF2TX1, ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF2TX2, ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SLIMTX1, ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SLIMTX2, ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SLIMTX3, ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SLIMTX4, ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SLIMTX5, ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SLIMTX6, ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SLIMTX7, ARIZONA_SLIMTX7MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SLIMTX8, ARIZONA_SLIMTX8MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC1INT1, ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC1INT2, ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC1DEC1, ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC1DEC2, ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC2INT1, ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC2INT2, ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC2DEC1, ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC2DEC2, ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE);
static const char *wm8997_aec_loopback_texts[] = {
"HPOUT1L", "HPOUT1R", "EPOUT", "SPKOUT", "SPKDAT1L", "SPKDAT1R",
};
static const unsigned int wm8997_aec_loopback_values[] = {
0, 1, 4, 6, 8, 9,
};
static const struct soc_enum wm8997_aec_loopback =
SOC_VALUE_ENUM_SINGLE(ARIZONA_DAC_AEC_CONTROL_1,
ARIZONA_AEC_LOOPBACK_SRC_SHIFT, 0xf,
ARRAY_SIZE(wm8997_aec_loopback_texts),
wm8997_aec_loopback_texts,
wm8997_aec_loopback_values);
static const struct snd_kcontrol_new wm8997_aec_loopback_mux =
SOC_DAPM_ENUM("AEC Loopback", wm8997_aec_loopback);
static const struct snd_soc_dapm_widget wm8997_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("SYSCLK", ARIZONA_SYSTEM_CLOCK_1, ARIZONA_SYSCLK_ENA_SHIFT,
0, wm8997_sysclk_ev,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("ASYNCCLK", ARIZONA_ASYNC_CLOCK_1,
ARIZONA_ASYNC_CLK_ENA_SHIFT, 0, arizona_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("OPCLK", ARIZONA_OUTPUT_SYSTEM_CLOCK,
ARIZONA_OPCLK_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ASYNCOPCLK", ARIZONA_OUTPUT_ASYNC_CLOCK,
ARIZONA_OPCLK_ASYNC_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD2", 0, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("MICVDD", 0, SND_SOC_DAPM_REGULATOR_BYPASS),
SND_SOC_DAPM_REGULATOR_SUPPLY("SPKVDD", 0, 0),
SND_SOC_DAPM_SIGGEN("TONE"),
SND_SOC_DAPM_SIGGEN("NOISE"),
SND_SOC_DAPM_SIGGEN("HAPTICS"),
SND_SOC_DAPM_INPUT("IN1L"),
SND_SOC_DAPM_INPUT("IN1R"),
SND_SOC_DAPM_INPUT("IN2L"),
SND_SOC_DAPM_INPUT("IN2R"),
SND_SOC_DAPM_PGA_E("IN1L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN1L_ENA_SHIFT,
0, NULL, 0, arizona_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN1R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN1R_ENA_SHIFT,
0, NULL, 0, arizona_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN2L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN2L_ENA_SHIFT,
0, NULL, 0, arizona_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN2R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN2R_ENA_SHIFT,
0, NULL, 0, arizona_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY("MICBIAS1", ARIZONA_MIC_BIAS_CTRL_1,
ARIZONA_MICB1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS2", ARIZONA_MIC_BIAS_CTRL_2,
ARIZONA_MICB2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS3", ARIZONA_MIC_BIAS_CTRL_3,
ARIZONA_MICB3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("Noise Generator", ARIZONA_COMFORT_NOISE_GENERATOR,
ARIZONA_NOISE_GEN_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("Tone Generator 1", ARIZONA_TONE_GENERATOR_1,
ARIZONA_TONE1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("Tone Generator 2", ARIZONA_TONE_GENERATOR_1,
ARIZONA_TONE2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("Mic Mute Mixer", ARIZONA_MIC_NOISE_MIX_CONTROL_1,
ARIZONA_MICMUTE_MIX_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ1", ARIZONA_EQ1_1, ARIZONA_EQ1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ2", ARIZONA_EQ2_1, ARIZONA_EQ2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ3", ARIZONA_EQ3_1, ARIZONA_EQ3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ4", ARIZONA_EQ4_1, ARIZONA_EQ4_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("DRC1L", ARIZONA_DRC1_CTRL1, ARIZONA_DRC1L_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("DRC1R", ARIZONA_DRC1_CTRL1, ARIZONA_DRC1R_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF1", ARIZONA_HPLPF1_1, ARIZONA_LHPF1_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF2", ARIZONA_HPLPF2_1, ARIZONA_LHPF2_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF3", ARIZONA_HPLPF3_1, ARIZONA_LHPF3_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF4", ARIZONA_HPLPF4_1, ARIZONA_LHPF4_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("PWM1 Driver", ARIZONA_PWM_DRIVE_1, ARIZONA_PWM1_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA("PWM2 Driver", ARIZONA_PWM_DRIVE_1, ARIZONA_PWM2_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1INT1", ARIZONA_ISRC_1_CTRL_3,
ARIZONA_ISRC1_INT0_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1INT2", ARIZONA_ISRC_1_CTRL_3,
ARIZONA_ISRC1_INT1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC1", ARIZONA_ISRC_1_CTRL_3,
ARIZONA_ISRC1_DEC0_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC2", ARIZONA_ISRC_1_CTRL_3,
ARIZONA_ISRC1_DEC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2INT1", ARIZONA_ISRC_2_CTRL_3,
ARIZONA_ISRC2_INT0_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2INT2", ARIZONA_ISRC_2_CTRL_3,
ARIZONA_ISRC2_INT1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2DEC1", ARIZONA_ISRC_2_CTRL_3,
ARIZONA_ISRC2_DEC0_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2DEC2", ARIZONA_ISRC_2_CTRL_3,
ARIZONA_ISRC2_DEC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 0,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 1,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 2,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 3,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 4,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX6", NULL, 5,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX7", NULL, 6,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX7_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX8", NULL, 7,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX8_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 0,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 1,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 2,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 3,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 4,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX6", NULL, 5,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX7", NULL, 6,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX7_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX8", NULL, 7,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX8_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0,
ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX2", NULL, 1,
ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0,
ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX2", NULL, 1,
ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX1", NULL, 0,
ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE,
ARIZONA_SLIMTX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX2", NULL, 1,
ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE,
ARIZONA_SLIMTX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX3", NULL, 2,
ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE,
ARIZONA_SLIMTX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX4", NULL, 3,
ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE,
ARIZONA_SLIMTX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX5", NULL, 4,
ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE,
ARIZONA_SLIMTX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX6", NULL, 5,
ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE,
ARIZONA_SLIMTX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX7", NULL, 6,
ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE,
ARIZONA_SLIMTX7_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX8", NULL, 7,
ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE,
ARIZONA_SLIMTX8_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX1", NULL, 0,
ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE,
ARIZONA_SLIMRX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX2", NULL, 1,
ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE,
ARIZONA_SLIMRX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX3", NULL, 2,
ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE,
ARIZONA_SLIMRX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX4", NULL, 3,
ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE,
ARIZONA_SLIMRX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX5", NULL, 4,
ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE,
ARIZONA_SLIMRX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX6", NULL, 5,
ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE,
ARIZONA_SLIMRX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX7", NULL, 6,
ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE,
ARIZONA_SLIMRX7_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX8", NULL, 7,
ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE,
ARIZONA_SLIMRX8_ENA_SHIFT, 0),
SND_SOC_DAPM_MUX("AEC Loopback", ARIZONA_DAC_AEC_CONTROL_1,
ARIZONA_AEC_LOOPBACK_ENA_SHIFT, 0, &wm8997_aec_loopback_mux),
SND_SOC_DAPM_PGA_E("OUT1L", SND_SOC_NOPM,
ARIZONA_OUT1L_ENA_SHIFT, 0, NULL, 0, arizona_hp_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT1R", SND_SOC_NOPM,
ARIZONA_OUT1R_ENA_SHIFT, 0, NULL, 0, arizona_hp_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT3L", ARIZONA_OUTPUT_ENABLES_1,
ARIZONA_OUT3L_ENA_SHIFT, 0, NULL, 0, arizona_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT5L", ARIZONA_OUTPUT_ENABLES_1,
ARIZONA_OUT5L_ENA_SHIFT, 0, NULL, 0, arizona_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT5R", ARIZONA_OUTPUT_ENABLES_1,
ARIZONA_OUT5R_ENA_SHIFT, 0, NULL, 0, arizona_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
ARIZONA_MIXER_WIDGETS(EQ1, "EQ1"),
ARIZONA_MIXER_WIDGETS(EQ2, "EQ2"),
ARIZONA_MIXER_WIDGETS(EQ3, "EQ3"),
ARIZONA_MIXER_WIDGETS(EQ4, "EQ4"),
ARIZONA_MIXER_WIDGETS(DRC1L, "DRC1L"),
ARIZONA_MIXER_WIDGETS(DRC1R, "DRC1R"),
ARIZONA_MIXER_WIDGETS(LHPF1, "LHPF1"),
ARIZONA_MIXER_WIDGETS(LHPF2, "LHPF2"),
ARIZONA_MIXER_WIDGETS(LHPF3, "LHPF3"),
ARIZONA_MIXER_WIDGETS(LHPF4, "LHPF4"),
ARIZONA_MIXER_WIDGETS(Mic, "Mic"),
ARIZONA_MIXER_WIDGETS(Noise, "Noise"),
ARIZONA_MIXER_WIDGETS(PWM1, "PWM1"),
ARIZONA_MIXER_WIDGETS(PWM2, "PWM2"),
ARIZONA_MIXER_WIDGETS(OUT1L, "HPOUT1L"),
ARIZONA_MIXER_WIDGETS(OUT1R, "HPOUT1R"),
ARIZONA_MIXER_WIDGETS(OUT3, "EPOUT"),
ARIZONA_MIXER_WIDGETS(SPKOUT, "SPKOUT"),
ARIZONA_MIXER_WIDGETS(SPKDAT1L, "SPKDAT1L"),
ARIZONA_MIXER_WIDGETS(SPKDAT1R, "SPKDAT1R"),
ARIZONA_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"),
ARIZONA_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"),
ARIZONA_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"),
ARIZONA_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"),
ARIZONA_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"),
ARIZONA_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"),
ARIZONA_MIXER_WIDGETS(AIF1TX7, "AIF1TX7"),
ARIZONA_MIXER_WIDGETS(AIF1TX8, "AIF1TX8"),
ARIZONA_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"),
ARIZONA_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"),
ARIZONA_MIXER_WIDGETS(SLIMTX1, "SLIMTX1"),
ARIZONA_MIXER_WIDGETS(SLIMTX2, "SLIMTX2"),
ARIZONA_MIXER_WIDGETS(SLIMTX3, "SLIMTX3"),
ARIZONA_MIXER_WIDGETS(SLIMTX4, "SLIMTX4"),
ARIZONA_MIXER_WIDGETS(SLIMTX5, "SLIMTX5"),
ARIZONA_MIXER_WIDGETS(SLIMTX6, "SLIMTX6"),
ARIZONA_MIXER_WIDGETS(SLIMTX7, "SLIMTX7"),
ARIZONA_MIXER_WIDGETS(SLIMTX8, "SLIMTX8"),
ARIZONA_MUX_WIDGETS(ISRC1DEC1, "ISRC1DEC1"),
ARIZONA_MUX_WIDGETS(ISRC1DEC2, "ISRC1DEC2"),
ARIZONA_MUX_WIDGETS(ISRC1INT1, "ISRC1INT1"),
ARIZONA_MUX_WIDGETS(ISRC1INT2, "ISRC1INT2"),
ARIZONA_MUX_WIDGETS(ISRC2DEC1, "ISRC2DEC1"),
ARIZONA_MUX_WIDGETS(ISRC2DEC2, "ISRC2DEC2"),
ARIZONA_MUX_WIDGETS(ISRC2INT1, "ISRC2INT1"),
ARIZONA_MUX_WIDGETS(ISRC2INT2, "ISRC2INT2"),
SND_SOC_DAPM_OUTPUT("HPOUT1L"),
SND_SOC_DAPM_OUTPUT("HPOUT1R"),
SND_SOC_DAPM_OUTPUT("EPOUTN"),
SND_SOC_DAPM_OUTPUT("EPOUTP"),
SND_SOC_DAPM_OUTPUT("SPKOUTN"),
SND_SOC_DAPM_OUTPUT("SPKOUTP"),
SND_SOC_DAPM_OUTPUT("SPKDAT1L"),
SND_SOC_DAPM_OUTPUT("SPKDAT1R"),
SND_SOC_DAPM_OUTPUT("MICSUPP"),
};
#define ARIZONA_MIXER_INPUT_ROUTES(name) \
{ name, "Noise Generator", "Noise Generator" }, \
{ name, "Tone Generator 1", "Tone Generator 1" }, \
{ name, "Tone Generator 2", "Tone Generator 2" }, \
{ name, "Haptics", "HAPTICS" }, \
{ name, "AEC", "AEC Loopback" }, \
{ name, "IN1L", "IN1L PGA" }, \
{ name, "IN1R", "IN1R PGA" }, \
{ name, "IN2L", "IN2L PGA" }, \
{ name, "IN2R", "IN2R PGA" }, \
{ name, "Mic Mute Mixer", "Mic Mute Mixer" }, \
{ name, "AIF1RX1", "AIF1RX1" }, \
{ name, "AIF1RX2", "AIF1RX2" }, \
{ name, "AIF1RX3", "AIF1RX3" }, \
{ name, "AIF1RX4", "AIF1RX4" }, \
{ name, "AIF1RX5", "AIF1RX5" }, \
{ name, "AIF1RX6", "AIF1RX6" }, \
{ name, "AIF1RX7", "AIF1RX7" }, \
{ name, "AIF1RX8", "AIF1RX8" }, \
{ name, "AIF2RX1", "AIF2RX1" }, \
{ name, "AIF2RX2", "AIF2RX2" }, \
{ name, "SLIMRX1", "SLIMRX1" }, \
{ name, "SLIMRX2", "SLIMRX2" }, \
{ name, "SLIMRX3", "SLIMRX3" }, \
{ name, "SLIMRX4", "SLIMRX4" }, \
{ name, "SLIMRX5", "SLIMRX5" }, \
{ name, "SLIMRX6", "SLIMRX6" }, \
{ name, "SLIMRX7", "SLIMRX7" }, \
{ name, "SLIMRX8", "SLIMRX8" }, \
{ name, "EQ1", "EQ1" }, \
{ name, "EQ2", "EQ2" }, \
{ name, "EQ3", "EQ3" }, \
{ name, "EQ4", "EQ4" }, \
{ name, "DRC1L", "DRC1L" }, \
{ name, "DRC1R", "DRC1R" }, \
{ name, "LHPF1", "LHPF1" }, \
{ name, "LHPF2", "LHPF2" }, \
{ name, "LHPF3", "LHPF3" }, \
{ name, "LHPF4", "LHPF4" }, \
{ name, "ISRC1DEC1", "ISRC1DEC1" }, \
{ name, "ISRC1DEC2", "ISRC1DEC2" }, \
{ name, "ISRC1INT1", "ISRC1INT1" }, \
{ name, "ISRC1INT2", "ISRC1INT2" }, \
{ name, "ISRC2DEC1", "ISRC2DEC1" }, \
{ name, "ISRC2DEC2", "ISRC2DEC2" }, \
{ name, "ISRC2INT1", "ISRC2INT1" }, \
{ name, "ISRC2INT2", "ISRC2INT2" }
static const struct snd_soc_dapm_route wm8997_dapm_routes[] = {
{ "AIF2 Capture", NULL, "DBVDD2" },
{ "AIF2 Playback", NULL, "DBVDD2" },
{ "OUT1L", NULL, "CPVDD" },
{ "OUT1R", NULL, "CPVDD" },
{ "OUT3L", NULL, "CPVDD" },
{ "OUT4L", NULL, "SPKVDD" },
{ "OUT1L", NULL, "SYSCLK" },
{ "OUT1R", NULL, "SYSCLK" },
{ "OUT3L", NULL, "SYSCLK" },
{ "OUT4L", NULL, "SYSCLK" },
{ "IN1L", NULL, "SYSCLK" },
{ "IN1R", NULL, "SYSCLK" },
{ "IN2L", NULL, "SYSCLK" },
{ "IN2R", NULL, "SYSCLK" },
{ "MICBIAS1", NULL, "MICVDD" },
{ "MICBIAS2", NULL, "MICVDD" },
{ "MICBIAS3", NULL, "MICVDD" },
{ "Noise Generator", NULL, "SYSCLK" },
{ "Tone Generator 1", NULL, "SYSCLK" },
{ "Tone Generator 2", NULL, "SYSCLK" },
{ "Noise Generator", NULL, "NOISE" },
{ "Tone Generator 1", NULL, "TONE" },
{ "Tone Generator 2", NULL, "TONE" },
{ "AIF1 Capture", NULL, "AIF1TX1" },
{ "AIF1 Capture", NULL, "AIF1TX2" },
{ "AIF1 Capture", NULL, "AIF1TX3" },
{ "AIF1 Capture", NULL, "AIF1TX4" },
{ "AIF1 Capture", NULL, "AIF1TX5" },
{ "AIF1 Capture", NULL, "AIF1TX6" },
{ "AIF1 Capture", NULL, "AIF1TX7" },
{ "AIF1 Capture", NULL, "AIF1TX8" },
{ "AIF1RX1", NULL, "AIF1 Playback" },
{ "AIF1RX2", NULL, "AIF1 Playback" },
{ "AIF1RX3", NULL, "AIF1 Playback" },
{ "AIF1RX4", NULL, "AIF1 Playback" },
{ "AIF1RX5", NULL, "AIF1 Playback" },
{ "AIF1RX6", NULL, "AIF1 Playback" },
{ "AIF1RX7", NULL, "AIF1 Playback" },
{ "AIF1RX8", NULL, "AIF1 Playback" },
{ "AIF2 Capture", NULL, "AIF2TX1" },
{ "AIF2 Capture", NULL, "AIF2TX2" },
{ "AIF2RX1", NULL, "AIF2 Playback" },
{ "AIF2RX2", NULL, "AIF2 Playback" },
{ "Slim1 Capture", NULL, "SLIMTX1" },
{ "Slim1 Capture", NULL, "SLIMTX2" },
{ "Slim1 Capture", NULL, "SLIMTX3" },
{ "Slim1 Capture", NULL, "SLIMTX4" },
{ "SLIMRX1", NULL, "Slim1 Playback" },
{ "SLIMRX2", NULL, "Slim1 Playback" },
{ "SLIMRX3", NULL, "Slim1 Playback" },
{ "SLIMRX4", NULL, "Slim1 Playback" },
{ "Slim2 Capture", NULL, "SLIMTX5" },
{ "Slim2 Capture", NULL, "SLIMTX6" },
{ "SLIMRX5", NULL, "Slim2 Playback" },
{ "SLIMRX6", NULL, "Slim2 Playback" },
{ "Slim3 Capture", NULL, "SLIMTX7" },
{ "Slim3 Capture", NULL, "SLIMTX8" },
{ "SLIMRX7", NULL, "Slim3 Playback" },
{ "SLIMRX8", NULL, "Slim3 Playback" },
{ "AIF1 Playback", NULL, "SYSCLK" },
{ "AIF2 Playback", NULL, "SYSCLK" },
{ "Slim1 Playback", NULL, "SYSCLK" },
{ "Slim2 Playback", NULL, "SYSCLK" },
{ "Slim3 Playback", NULL, "SYSCLK" },
{ "AIF1 Capture", NULL, "SYSCLK" },
{ "AIF2 Capture", NULL, "SYSCLK" },
{ "Slim1 Capture", NULL, "SYSCLK" },
{ "Slim2 Capture", NULL, "SYSCLK" },
{ "Slim3 Capture", NULL, "SYSCLK" },
{ "IN1L PGA", NULL, "IN1L" },
{ "IN1R PGA", NULL, "IN1R" },
{ "IN2L PGA", NULL, "IN2L" },
{ "IN2R PGA", NULL, "IN2R" },
ARIZONA_MIXER_ROUTES("OUT1L", "HPOUT1L"),
ARIZONA_MIXER_ROUTES("OUT1R", "HPOUT1R"),
ARIZONA_MIXER_ROUTES("OUT3L", "EPOUT"),
ARIZONA_MIXER_ROUTES("OUT4L", "SPKOUT"),
ARIZONA_MIXER_ROUTES("OUT5L", "SPKDAT1L"),
ARIZONA_MIXER_ROUTES("OUT5R", "SPKDAT1R"),
ARIZONA_MIXER_ROUTES("PWM1 Driver", "PWM1"),
ARIZONA_MIXER_ROUTES("PWM2 Driver", "PWM2"),
ARIZONA_MIXER_ROUTES("AIF1TX1", "AIF1TX1"),
ARIZONA_MIXER_ROUTES("AIF1TX2", "AIF1TX2"),
ARIZONA_MIXER_ROUTES("AIF1TX3", "AIF1TX3"),
ARIZONA_MIXER_ROUTES("AIF1TX4", "AIF1TX4"),
ARIZONA_MIXER_ROUTES("AIF1TX5", "AIF1TX5"),
ARIZONA_MIXER_ROUTES("AIF1TX6", "AIF1TX6"),
ARIZONA_MIXER_ROUTES("AIF1TX7", "AIF1TX7"),
ARIZONA_MIXER_ROUTES("AIF1TX8", "AIF1TX8"),
ARIZONA_MIXER_ROUTES("AIF2TX1", "AIF2TX1"),
ARIZONA_MIXER_ROUTES("AIF2TX2", "AIF2TX2"),
ARIZONA_MIXER_ROUTES("SLIMTX1", "SLIMTX1"),
ARIZONA_MIXER_ROUTES("SLIMTX2", "SLIMTX2"),
ARIZONA_MIXER_ROUTES("SLIMTX3", "SLIMTX3"),
ARIZONA_MIXER_ROUTES("SLIMTX4", "SLIMTX4"),
ARIZONA_MIXER_ROUTES("SLIMTX5", "SLIMTX5"),
ARIZONA_MIXER_ROUTES("SLIMTX6", "SLIMTX6"),
ARIZONA_MIXER_ROUTES("SLIMTX7", "SLIMTX7"),
ARIZONA_MIXER_ROUTES("SLIMTX8", "SLIMTX8"),
ARIZONA_MIXER_ROUTES("EQ1", "EQ1"),
ARIZONA_MIXER_ROUTES("EQ2", "EQ2"),
ARIZONA_MIXER_ROUTES("EQ3", "EQ3"),
ARIZONA_MIXER_ROUTES("EQ4", "EQ4"),
ARIZONA_MIXER_ROUTES("DRC1L", "DRC1L"),
ARIZONA_MIXER_ROUTES("DRC1R", "DRC1R"),
ARIZONA_MIXER_ROUTES("LHPF1", "LHPF1"),
ARIZONA_MIXER_ROUTES("LHPF2", "LHPF2"),
ARIZONA_MIXER_ROUTES("LHPF3", "LHPF3"),
ARIZONA_MIXER_ROUTES("LHPF4", "LHPF4"),
ARIZONA_MIXER_ROUTES("Mic Mute Mixer", "Noise"),
ARIZONA_MIXER_ROUTES("Mic Mute Mixer", "Mic"),
ARIZONA_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"),
ARIZONA_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"),
ARIZONA_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"),
ARIZONA_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"),
ARIZONA_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"),
ARIZONA_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"),
ARIZONA_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"),
ARIZONA_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"),
{ "AEC Loopback", "HPOUT1L", "OUT1L" },
{ "AEC Loopback", "HPOUT1R", "OUT1R" },
{ "HPOUT1L", NULL, "OUT1L" },
{ "HPOUT1R", NULL, "OUT1R" },
{ "AEC Loopback", "EPOUT", "OUT3L" },
{ "EPOUTN", NULL, "OUT3L" },
{ "EPOUTP", NULL, "OUT3L" },
{ "AEC Loopback", "SPKOUT", "OUT4L" },
{ "SPKOUTN", NULL, "OUT4L" },
{ "SPKOUTP", NULL, "OUT4L" },
{ "AEC Loopback", "SPKDAT1L", "OUT5L" },
{ "AEC Loopback", "SPKDAT1R", "OUT5R" },
{ "SPKDAT1L", NULL, "OUT5L" },
{ "SPKDAT1R", NULL, "OUT5R" },
{ "MICSUPP", NULL, "SYSCLK" },
};
static int wm8997_set_fll(struct snd_soc_component *component, int fll_id,
int source, unsigned int Fref, unsigned int Fout)
{
struct wm8997_priv *wm8997 = snd_soc_component_get_drvdata(component);
switch (fll_id) {
case WM8997_FLL1:
return arizona_set_fll(&wm8997->fll[0], source, Fref, Fout);
case WM8997_FLL2:
return arizona_set_fll(&wm8997->fll[1], source, Fref, Fout);
case WM8997_FLL1_REFCLK:
return arizona_set_fll_refclk(&wm8997->fll[0], source, Fref,
Fout);
case WM8997_FLL2_REFCLK:
return arizona_set_fll_refclk(&wm8997->fll[1], source, Fref,
Fout);
default:
return -EINVAL;
}
}
#define WM8997_RATES SNDRV_PCM_RATE_KNOT
#define WM8997_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver wm8997_dai[] = {
{
.name = "wm8997-aif1",
.id = 1,
.base = ARIZONA_AIF1_BCLK_CTRL,
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 8,
.rates = WM8997_RATES,
.formats = WM8997_FORMATS,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 1,
.channels_max = 8,
.rates = WM8997_RATES,
.formats = WM8997_FORMATS,
},
.ops = &arizona_dai_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
{
.name = "wm8997-aif2",
.id = 2,
.base = ARIZONA_AIF2_BCLK_CTRL,
.playback = {
.stream_name = "AIF2 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM8997_RATES,
.formats = WM8997_FORMATS,
},
.capture = {
.stream_name = "AIF2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM8997_RATES,
.formats = WM8997_FORMATS,
},
.ops = &arizona_dai_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
{
.name = "wm8997-slim1",
.id = 3,
.playback = {
.stream_name = "Slim1 Playback",
.channels_min = 1,
.channels_max = 4,
.rates = WM8997_RATES,
.formats = WM8997_FORMATS,
},
.capture = {
.stream_name = "Slim1 Capture",
.channels_min = 1,
.channels_max = 4,
.rates = WM8997_RATES,
.formats = WM8997_FORMATS,
},
.ops = &arizona_simple_dai_ops,
},
{
.name = "wm8997-slim2",
.id = 4,
.playback = {
.stream_name = "Slim2 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM8997_RATES,
.formats = WM8997_FORMATS,
},
.capture = {
.stream_name = "Slim2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM8997_RATES,
.formats = WM8997_FORMATS,
},
.ops = &arizona_simple_dai_ops,
},
{
.name = "wm8997-slim3",
.id = 5,
.playback = {
.stream_name = "Slim3 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM8997_RATES,
.formats = WM8997_FORMATS,
},
.capture = {
.stream_name = "Slim3 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM8997_RATES,
.formats = WM8997_FORMATS,
},
.ops = &arizona_simple_dai_ops,
},
};
static int wm8997_component_probe(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct wm8997_priv *priv = snd_soc_component_get_drvdata(component);
struct arizona *arizona = priv->core.arizona;
int ret;
snd_soc_component_init_regmap(component, arizona->regmap);
ret = arizona_init_spk(component);
if (ret < 0)
return ret;
snd_soc_component_disable_pin(component, "HAPTICS");
priv->core.arizona->dapm = dapm;
return 0;
}
static void wm8997_component_remove(struct snd_soc_component *component)
{
struct wm8997_priv *priv = snd_soc_component_get_drvdata(component);
priv->core.arizona->dapm = NULL;
}
#define WM8997_DIG_VU 0x0200
static unsigned int wm8997_digital_vu[] = {
ARIZONA_DAC_DIGITAL_VOLUME_1L,
ARIZONA_DAC_DIGITAL_VOLUME_1R,
ARIZONA_DAC_DIGITAL_VOLUME_3L,
ARIZONA_DAC_DIGITAL_VOLUME_4L,
ARIZONA_DAC_DIGITAL_VOLUME_5L,
ARIZONA_DAC_DIGITAL_VOLUME_5R,
};
static const struct snd_soc_component_driver soc_component_dev_wm8997 = {
.probe = wm8997_component_probe,
.remove = wm8997_component_remove,
.set_sysclk = arizona_set_sysclk,
.set_pll = wm8997_set_fll,
.set_jack = arizona_jack_set_jack,
.controls = wm8997_snd_controls,
.num_controls = ARRAY_SIZE(wm8997_snd_controls),
.dapm_widgets = wm8997_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8997_dapm_widgets),
.dapm_routes = wm8997_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(wm8997_dapm_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
static int wm8997_probe(struct platform_device *pdev)
{
struct arizona *arizona = dev_get_drvdata(pdev->dev.parent);
struct wm8997_priv *wm8997;
int i, ret;
wm8997 = devm_kzalloc(&pdev->dev, sizeof(struct wm8997_priv),
GFP_KERNEL);
if (wm8997 == NULL)
return -ENOMEM;
platform_set_drvdata(pdev, wm8997);
if (IS_ENABLED(CONFIG_OF)) {
if (!dev_get_platdata(arizona->dev)) {
ret = arizona_of_get_audio_pdata(arizona);
if (ret < 0)
return ret;
}
}
wm8997->core.arizona = arizona;
wm8997->core.num_inputs = 4;
arizona_init_dvfs(&wm8997->core);
/* This may return -EPROBE_DEFER, so do this early on */
ret = arizona_jack_codec_dev_probe(&wm8997->core, &pdev->dev);
if (ret)
return ret;
for (i = 0; i < ARRAY_SIZE(wm8997->fll); i++)
wm8997->fll[i].vco_mult = 1;
arizona_init_fll(arizona, 1, ARIZONA_FLL1_CONTROL_1 - 1,
ARIZONA_IRQ_FLL1_LOCK, ARIZONA_IRQ_FLL1_CLOCK_OK,
&wm8997->fll[0]);
arizona_init_fll(arizona, 2, ARIZONA_FLL2_CONTROL_1 - 1,
ARIZONA_IRQ_FLL2_LOCK, ARIZONA_IRQ_FLL2_CLOCK_OK,
&wm8997->fll[1]);
/* SR2 fixed at 8kHz, SR3 fixed at 16kHz */
regmap_update_bits(arizona->regmap, ARIZONA_SAMPLE_RATE_2,
ARIZONA_SAMPLE_RATE_2_MASK, 0x11);
regmap_update_bits(arizona->regmap, ARIZONA_SAMPLE_RATE_3,
ARIZONA_SAMPLE_RATE_3_MASK, 0x12);
for (i = 0; i < ARRAY_SIZE(wm8997_dai); i++)
arizona_init_dai(&wm8997->core, i);
/* Latch volume update bits */
for (i = 0; i < ARRAY_SIZE(wm8997_digital_vu); i++)
regmap_update_bits(arizona->regmap, wm8997_digital_vu[i],
WM8997_DIG_VU, WM8997_DIG_VU);
pm_runtime_enable(&pdev->dev);
pm_runtime_idle(&pdev->dev);
arizona_init_common(arizona);
ret = arizona_init_vol_limit(arizona);
if (ret < 0)
goto err_jack_codec_dev;
ret = arizona_init_spk_irqs(arizona);
if (ret < 0)
goto err_jack_codec_dev;
ret = devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_wm8997,
wm8997_dai,
ARRAY_SIZE(wm8997_dai));
if (ret < 0) {
dev_err(&pdev->dev, "Failed to register component: %d\n", ret);
goto err_spk_irqs;
}
return ret;
err_spk_irqs:
arizona_free_spk_irqs(arizona);
err_jack_codec_dev:
pm_runtime_disable(&pdev->dev);
arizona_jack_codec_dev_remove(&wm8997->core);
return ret;
}
static void wm8997_remove(struct platform_device *pdev)
{
struct wm8997_priv *wm8997 = platform_get_drvdata(pdev);
struct arizona *arizona = wm8997->core.arizona;
pm_runtime_disable(&pdev->dev);
arizona_free_spk_irqs(arizona);
arizona_jack_codec_dev_remove(&wm8997->core);
}
static struct platform_driver wm8997_codec_driver = {
.driver = {
.name = "wm8997-codec",
},
.probe = wm8997_probe,
.remove_new = wm8997_remove,
};
module_platform_driver(wm8997_codec_driver);
MODULE_DESCRIPTION("ASoC WM8997 driver");
MODULE_AUTHOR("Charles Keepax <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:wm8997-codec");
| linux-master | sound/soc/codecs/wm8997.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* cs47l24.h -- ALSA SoC Audio driver for Cirrus Logic CS47L24
*
* Copyright 2015 Cirrus Logic Inc.
*
* Author: Richard Fitzgerald <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/jack.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <linux/mfd/arizona/core.h>
#include <linux/mfd/arizona/registers.h>
#include "arizona.h"
#include "wm_adsp.h"
#include "cs47l24.h"
#define DRV_NAME "cs47l24-codec"
struct cs47l24_priv {
struct arizona_priv core;
struct arizona_fll fll[2];
};
static const struct cs_dsp_region cs47l24_dsp2_regions[] = {
{ .type = WMFW_ADSP2_PM, .base = 0x200000 },
{ .type = WMFW_ADSP2_ZM, .base = 0x280000 },
{ .type = WMFW_ADSP2_XM, .base = 0x290000 },
{ .type = WMFW_ADSP2_YM, .base = 0x2a8000 },
};
static const struct cs_dsp_region cs47l24_dsp3_regions[] = {
{ .type = WMFW_ADSP2_PM, .base = 0x300000 },
{ .type = WMFW_ADSP2_ZM, .base = 0x380000 },
{ .type = WMFW_ADSP2_XM, .base = 0x390000 },
{ .type = WMFW_ADSP2_YM, .base = 0x3a8000 },
};
static const struct cs_dsp_region *cs47l24_dsp_regions[] = {
cs47l24_dsp2_regions,
cs47l24_dsp3_regions,
};
static int cs47l24_adsp_power_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct arizona *arizona = dev_get_drvdata(component->dev->parent);
unsigned int v;
int ret;
ret = regmap_read(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, &v);
if (ret != 0) {
dev_err(component->dev, "Failed to read SYSCLK state: %d\n", ret);
return ret;
}
v = (v & ARIZONA_SYSCLK_FREQ_MASK) >> ARIZONA_SYSCLK_FREQ_SHIFT;
wm_adsp2_set_dspclk(w, v);
return wm_adsp_early_event(w, kcontrol, event);
}
static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0);
static DECLARE_TLV_DB_SCALE(noise_tlv, -13200, 600, 0);
static DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
#define CS47L24_NG_SRC(name, base) \
SOC_SINGLE(name " NG HPOUT1L Switch", base, 0, 1, 0), \
SOC_SINGLE(name " NG HPOUT1R Switch", base, 1, 1, 0), \
SOC_SINGLE(name " NG SPKOUT Switch", base, 6, 1, 0)
static const struct snd_kcontrol_new cs47l24_snd_controls[] = {
SOC_ENUM("IN1 OSR", arizona_in_dmic_osr[0]),
SOC_ENUM("IN2 OSR", arizona_in_dmic_osr[1]),
SOC_ENUM("IN HPF Cutoff Frequency", arizona_in_hpf_cut_enum),
SOC_SINGLE("IN1L HPF Switch", ARIZONA_IN1L_CONTROL,
ARIZONA_IN1L_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN1R HPF Switch", ARIZONA_IN1R_CONTROL,
ARIZONA_IN1R_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN2L HPF Switch", ARIZONA_IN2L_CONTROL,
ARIZONA_IN2L_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN2R HPF Switch", ARIZONA_IN2R_CONTROL,
ARIZONA_IN2R_HPF_SHIFT, 1, 0),
SOC_SINGLE_TLV("IN1L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1L,
ARIZONA_IN1L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
SOC_SINGLE_TLV("IN1R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1R,
ARIZONA_IN1R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
SOC_SINGLE_TLV("IN2L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2L,
ARIZONA_IN2L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
SOC_SINGLE_TLV("IN2R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2R,
ARIZONA_IN2R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
SOC_ENUM("Input Ramp Up", arizona_in_vi_ramp),
SOC_ENUM("Input Ramp Down", arizona_in_vd_ramp),
ARIZONA_MIXER_CONTROLS("EQ1", ARIZONA_EQ1MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("EQ2", ARIZONA_EQ2MIX_INPUT_1_SOURCE),
ARIZONA_EQ_CONTROL("EQ1 Coefficients", ARIZONA_EQ1_2),
SOC_SINGLE_TLV("EQ1 B1 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B1_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ1 B2 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B2_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ1 B3 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B3_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ1 B4 Volume", ARIZONA_EQ1_2, ARIZONA_EQ1_B4_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ1 B5 Volume", ARIZONA_EQ1_2, ARIZONA_EQ1_B5_GAIN_SHIFT,
24, 0, eq_tlv),
ARIZONA_EQ_CONTROL("EQ2 Coefficients", ARIZONA_EQ2_2),
SOC_SINGLE_TLV("EQ2 B1 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B1_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ2 B2 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B2_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ2 B3 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B3_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ2 B4 Volume", ARIZONA_EQ2_2, ARIZONA_EQ2_B4_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ2 B5 Volume", ARIZONA_EQ2_2, ARIZONA_EQ2_B5_GAIN_SHIFT,
24, 0, eq_tlv),
ARIZONA_MIXER_CONTROLS("DRC1L", ARIZONA_DRC1LMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("DRC1R", ARIZONA_DRC1RMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("DRC2L", ARIZONA_DRC2LMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("DRC2R", ARIZONA_DRC2RMIX_INPUT_1_SOURCE),
SND_SOC_BYTES_MASK("DRC1", ARIZONA_DRC1_CTRL1, 5,
ARIZONA_DRC1R_ENA | ARIZONA_DRC1L_ENA),
SND_SOC_BYTES_MASK("DRC2", ARIZONA_DRC2_CTRL1, 5,
ARIZONA_DRC2R_ENA | ARIZONA_DRC2L_ENA),
ARIZONA_MIXER_CONTROLS("LHPF1", ARIZONA_HPLP1MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("LHPF2", ARIZONA_HPLP2MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("LHPF3", ARIZONA_HPLP3MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("LHPF4", ARIZONA_HPLP4MIX_INPUT_1_SOURCE),
ARIZONA_LHPF_CONTROL("LHPF1 Coefficients", ARIZONA_HPLPF1_2),
ARIZONA_LHPF_CONTROL("LHPF2 Coefficients", ARIZONA_HPLPF2_2),
ARIZONA_LHPF_CONTROL("LHPF3 Coefficients", ARIZONA_HPLPF3_2),
ARIZONA_LHPF_CONTROL("LHPF4 Coefficients", ARIZONA_HPLPF4_2),
SOC_ENUM("LHPF1 Mode", arizona_lhpf1_mode),
SOC_ENUM("LHPF2 Mode", arizona_lhpf2_mode),
SOC_ENUM("LHPF3 Mode", arizona_lhpf3_mode),
SOC_ENUM("LHPF4 Mode", arizona_lhpf4_mode),
SOC_ENUM("ISRC1 FSL", arizona_isrc_fsl[0]),
SOC_ENUM("ISRC2 FSL", arizona_isrc_fsl[1]),
SOC_ENUM("ISRC3 FSL", arizona_isrc_fsl[2]),
SOC_ENUM("ISRC1 FSH", arizona_isrc_fsh[0]),
SOC_ENUM("ISRC2 FSH", arizona_isrc_fsh[1]),
SOC_ENUM("ISRC3 FSH", arizona_isrc_fsh[2]),
SOC_ENUM("ASRC RATE 1", arizona_asrc_rate1),
WM_ADSP2_PRELOAD_SWITCH("DSP2", 2),
WM_ADSP2_PRELOAD_SWITCH("DSP3", 3),
ARIZONA_MIXER_CONTROLS("DSP2L", ARIZONA_DSP2LMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("DSP2R", ARIZONA_DSP2RMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("DSP3L", ARIZONA_DSP3LMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("DSP3R", ARIZONA_DSP3RMIX_INPUT_1_SOURCE),
SOC_SINGLE_TLV("Noise Generator Volume", ARIZONA_COMFORT_NOISE_GENERATOR,
ARIZONA_NOISE_GEN_GAIN_SHIFT, 0x16, 0, noise_tlv),
ARIZONA_MIXER_CONTROLS("HPOUT1L", ARIZONA_OUT1LMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("HPOUT1R", ARIZONA_OUT1RMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SPKOUT", ARIZONA_OUT4LMIX_INPUT_1_SOURCE),
SOC_SINGLE("HPOUT1 SC Protect Switch", ARIZONA_HP1_SHORT_CIRCUIT_CTRL,
ARIZONA_HP1_SC_ENA_SHIFT, 1, 0),
SOC_DOUBLE_R("HPOUT1 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_1L,
ARIZONA_DAC_DIGITAL_VOLUME_1R, ARIZONA_OUT1L_MUTE_SHIFT, 1, 1),
SOC_SINGLE("Speaker Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_4L,
ARIZONA_OUT4L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_1L,
ARIZONA_DAC_DIGITAL_VOLUME_1R, ARIZONA_OUT1L_VOL_SHIFT,
0xbf, 0, digital_tlv),
SOC_SINGLE_TLV("Speaker Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_4L,
ARIZONA_OUT4L_VOL_SHIFT, 0xbf, 0, digital_tlv),
SOC_ENUM("Output Ramp Up", arizona_out_vi_ramp),
SOC_ENUM("Output Ramp Down", arizona_out_vd_ramp),
SOC_SINGLE("Noise Gate Switch", ARIZONA_NOISE_GATE_CONTROL,
ARIZONA_NGATE_ENA_SHIFT, 1, 0),
SOC_SINGLE_TLV("Noise Gate Threshold Volume", ARIZONA_NOISE_GATE_CONTROL,
ARIZONA_NGATE_THR_SHIFT, 7, 1, ng_tlv),
SOC_ENUM("Noise Gate Hold", arizona_ng_hold),
CS47L24_NG_SRC("HPOUT1L", ARIZONA_NOISE_GATE_SELECT_1L),
CS47L24_NG_SRC("HPOUT1R", ARIZONA_NOISE_GATE_SELECT_1R),
CS47L24_NG_SRC("SPKOUT", ARIZONA_NOISE_GATE_SELECT_4L),
ARIZONA_MIXER_CONTROLS("AIF1TX1", ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF1TX2", ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF1TX3", ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF1TX4", ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF1TX5", ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF1TX6", ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF1TX7", ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF1TX8", ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF2TX1", ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF2TX2", ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF2TX3", ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF2TX4", ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF2TX5", ARIZONA_AIF2TX5MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF2TX6", ARIZONA_AIF2TX6MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF3TX1", ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF3TX2", ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE),
WM_ADSP_FW_CONTROL("DSP2", 1),
WM_ADSP_FW_CONTROL("DSP3", 2),
};
ARIZONA_MIXER_ENUMS(EQ1, ARIZONA_EQ1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(EQ2, ARIZONA_EQ2MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(DRC1L, ARIZONA_DRC1LMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(DRC1R, ARIZONA_DRC1RMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(DRC2L, ARIZONA_DRC2LMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(DRC2R, ARIZONA_DRC2RMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(LHPF1, ARIZONA_HPLP1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(LHPF2, ARIZONA_HPLP2MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(LHPF3, ARIZONA_HPLP3MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(LHPF4, ARIZONA_HPLP4MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(DSP2L, ARIZONA_DSP2LMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(DSP2R, ARIZONA_DSP2RMIX_INPUT_1_SOURCE);
ARIZONA_DSP_AUX_ENUMS(DSP2, ARIZONA_DSP2AUX1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(DSP3L, ARIZONA_DSP3LMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(DSP3R, ARIZONA_DSP3RMIX_INPUT_1_SOURCE);
ARIZONA_DSP_AUX_ENUMS(DSP3, ARIZONA_DSP3AUX1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(PWM1, ARIZONA_PWM1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(PWM2, ARIZONA_PWM2MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(OUT1L, ARIZONA_OUT1LMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(OUT1R, ARIZONA_OUT1RMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SPKOUT, ARIZONA_OUT4LMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX1, ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX2, ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX3, ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX4, ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX5, ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX6, ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX7, ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX8, ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF2TX1, ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF2TX2, ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF2TX3, ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF2TX4, ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF2TX5, ARIZONA_AIF2TX5MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF2TX6, ARIZONA_AIF2TX6MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF3TX1, ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF3TX2, ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ASRC1L, ARIZONA_ASRC1LMIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ASRC1R, ARIZONA_ASRC1RMIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ASRC2L, ARIZONA_ASRC2LMIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ASRC2R, ARIZONA_ASRC2RMIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC1INT1, ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC1INT2, ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC1INT3, ARIZONA_ISRC1INT3MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC1INT4, ARIZONA_ISRC1INT4MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC1DEC1, ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC1DEC2, ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC1DEC3, ARIZONA_ISRC1DEC3MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC1DEC4, ARIZONA_ISRC1DEC4MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC2INT1, ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC2INT2, ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC2INT3, ARIZONA_ISRC2INT3MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC2INT4, ARIZONA_ISRC2INT4MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC2DEC1, ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC2DEC2, ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC2DEC3, ARIZONA_ISRC2DEC3MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC2DEC4, ARIZONA_ISRC2DEC4MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC3INT1, ARIZONA_ISRC3INT1MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC3INT2, ARIZONA_ISRC3INT2MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC3INT3, ARIZONA_ISRC3INT3MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC3INT4, ARIZONA_ISRC3INT4MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC3DEC1, ARIZONA_ISRC3DEC1MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC3DEC2, ARIZONA_ISRC3DEC2MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC3DEC3, ARIZONA_ISRC3DEC3MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC3DEC4, ARIZONA_ISRC3DEC4MIX_INPUT_1_SOURCE);
static const char * const cs47l24_aec_loopback_texts[] = {
"HPOUT1L", "HPOUT1R", "SPKOUT",
};
static const unsigned int cs47l24_aec_loopback_values[] = {
0, 1, 6,
};
static const struct soc_enum cs47l24_aec_loopback =
SOC_VALUE_ENUM_SINGLE(ARIZONA_DAC_AEC_CONTROL_1,
ARIZONA_AEC_LOOPBACK_SRC_SHIFT, 0xf,
ARRAY_SIZE(cs47l24_aec_loopback_texts),
cs47l24_aec_loopback_texts,
cs47l24_aec_loopback_values);
static const struct snd_kcontrol_new cs47l24_aec_loopback_mux =
SOC_DAPM_ENUM("AEC Loopback", cs47l24_aec_loopback);
static const struct snd_soc_dapm_widget cs47l24_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("SYSCLK", ARIZONA_SYSTEM_CLOCK_1,
ARIZONA_SYSCLK_ENA_SHIFT, 0, arizona_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("ASYNCCLK", ARIZONA_ASYNC_CLOCK_1,
ARIZONA_ASYNC_CLK_ENA_SHIFT, 0, arizona_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("OPCLK", ARIZONA_OUTPUT_SYSTEM_CLOCK,
ARIZONA_OPCLK_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ASYNCOPCLK", ARIZONA_OUTPUT_ASYNC_CLOCK,
ARIZONA_OPCLK_ASYNC_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("MICVDD", 0, SND_SOC_DAPM_REGULATOR_BYPASS),
SND_SOC_DAPM_REGULATOR_SUPPLY("SPKVDD", 0, 0),
SND_SOC_DAPM_SIGGEN("TONE"),
SND_SOC_DAPM_SIGGEN("NOISE"),
SND_SOC_DAPM_SIGGEN("HAPTICS"),
SND_SOC_DAPM_INPUT("IN1L"),
SND_SOC_DAPM_INPUT("IN1R"),
SND_SOC_DAPM_INPUT("IN2L"),
SND_SOC_DAPM_INPUT("IN2R"),
SND_SOC_DAPM_OUTPUT("DRC1 Signal Activity"),
SND_SOC_DAPM_OUTPUT("DRC2 Signal Activity"),
SND_SOC_DAPM_OUTPUT("DSP Voice Trigger"),
SND_SOC_DAPM_SWITCH("DSP3 Voice Trigger", SND_SOC_NOPM, 2, 0,
&arizona_voice_trigger_switch[2]),
SND_SOC_DAPM_PGA_E("IN1L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN1L_ENA_SHIFT,
0, NULL, 0, arizona_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN1R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN1R_ENA_SHIFT,
0, NULL, 0, arizona_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN2L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN2L_ENA_SHIFT,
0, NULL, 0, arizona_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN2R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN2R_ENA_SHIFT,
0, NULL, 0, arizona_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY("MICBIAS1", ARIZONA_MIC_BIAS_CTRL_1,
ARIZONA_MICB1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS2", ARIZONA_MIC_BIAS_CTRL_2,
ARIZONA_MICB1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("Noise Generator", ARIZONA_COMFORT_NOISE_GENERATOR,
ARIZONA_NOISE_GEN_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("Tone Generator 1", ARIZONA_TONE_GENERATOR_1,
ARIZONA_TONE1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("Tone Generator 2", ARIZONA_TONE_GENERATOR_1,
ARIZONA_TONE2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ1", ARIZONA_EQ1_1, ARIZONA_EQ1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ2", ARIZONA_EQ2_1, ARIZONA_EQ2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("DRC1L", ARIZONA_DRC1_CTRL1, ARIZONA_DRC1L_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("DRC1R", ARIZONA_DRC1_CTRL1, ARIZONA_DRC1R_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("DRC2L", ARIZONA_DRC2_CTRL1, ARIZONA_DRC2L_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("DRC2R", ARIZONA_DRC2_CTRL1, ARIZONA_DRC2R_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF1", ARIZONA_HPLPF1_1, ARIZONA_LHPF1_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF2", ARIZONA_HPLPF2_1, ARIZONA_LHPF2_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF3", ARIZONA_HPLPF3_1, ARIZONA_LHPF3_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF4", ARIZONA_HPLPF4_1, ARIZONA_LHPF4_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("PWM1 Driver", ARIZONA_PWM_DRIVE_1, ARIZONA_PWM1_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA("PWM2 Driver", ARIZONA_PWM_DRIVE_1, ARIZONA_PWM2_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA("ASRC1L", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC1L_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("ASRC1R", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC1R_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("ASRC2L", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC2L_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("ASRC2R", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC2R_ENA_SHIFT, 0,
NULL, 0),
WM_ADSP2("DSP2", 1, cs47l24_adsp_power_ev),
WM_ADSP2("DSP3", 2, cs47l24_adsp_power_ev),
SND_SOC_DAPM_PGA("ISRC1INT1", ARIZONA_ISRC_1_CTRL_3,
ARIZONA_ISRC1_INT0_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1INT2", ARIZONA_ISRC_1_CTRL_3,
ARIZONA_ISRC1_INT1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1INT3", ARIZONA_ISRC_1_CTRL_3,
ARIZONA_ISRC1_INT2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1INT4", ARIZONA_ISRC_1_CTRL_3,
ARIZONA_ISRC1_INT3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC1", ARIZONA_ISRC_1_CTRL_3,
ARIZONA_ISRC1_DEC0_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC2", ARIZONA_ISRC_1_CTRL_3,
ARIZONA_ISRC1_DEC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC3", ARIZONA_ISRC_1_CTRL_3,
ARIZONA_ISRC1_DEC2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC4", ARIZONA_ISRC_1_CTRL_3,
ARIZONA_ISRC1_DEC3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2INT1", ARIZONA_ISRC_2_CTRL_3,
ARIZONA_ISRC2_INT0_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2INT2", ARIZONA_ISRC_2_CTRL_3,
ARIZONA_ISRC2_INT1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2INT3", ARIZONA_ISRC_2_CTRL_3,
ARIZONA_ISRC2_INT2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2INT4", ARIZONA_ISRC_2_CTRL_3,
ARIZONA_ISRC2_INT3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2DEC1", ARIZONA_ISRC_2_CTRL_3,
ARIZONA_ISRC2_DEC0_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2DEC2", ARIZONA_ISRC_2_CTRL_3,
ARIZONA_ISRC2_DEC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2DEC3", ARIZONA_ISRC_2_CTRL_3,
ARIZONA_ISRC2_DEC2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2DEC4", ARIZONA_ISRC_2_CTRL_3,
ARIZONA_ISRC2_DEC3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC3INT1", ARIZONA_ISRC_3_CTRL_3,
ARIZONA_ISRC3_INT0_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC3INT2", ARIZONA_ISRC_3_CTRL_3,
ARIZONA_ISRC3_INT1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC3INT3", ARIZONA_ISRC_3_CTRL_3,
ARIZONA_ISRC3_INT2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC3INT4", ARIZONA_ISRC_3_CTRL_3,
ARIZONA_ISRC3_INT3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC3DEC1", ARIZONA_ISRC_3_CTRL_3,
ARIZONA_ISRC3_DEC0_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC3DEC2", ARIZONA_ISRC_3_CTRL_3,
ARIZONA_ISRC3_DEC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC3DEC3", ARIZONA_ISRC_3_CTRL_3,
ARIZONA_ISRC3_DEC2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC3DEC4", ARIZONA_ISRC_3_CTRL_3,
ARIZONA_ISRC3_DEC3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_MUX("AEC Loopback", ARIZONA_DAC_AEC_CONTROL_1,
ARIZONA_AEC_LOOPBACK_ENA_SHIFT, 0, &cs47l24_aec_loopback_mux),
SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 0,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 1,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 2,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 3,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 4,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX6", NULL, 5,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX7", NULL, 6,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX7_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX8", NULL, 7,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX8_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 0,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 1,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 2,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 3,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 4,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX6", NULL, 5,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX7", NULL, 6,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX7_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX8", NULL, 7,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX8_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0,
ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX2", NULL, 1,
ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX3", NULL, 2,
ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX4", NULL, 3,
ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX5", NULL, 4,
ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX6", NULL, 5,
ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0,
ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX2", NULL, 1,
ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX3", NULL, 2,
ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX4", NULL, 3,
ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX5", NULL, 4,
ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX6", NULL, 5,
ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF3TX1", NULL, 0,
ARIZONA_AIF3_TX_ENABLES, ARIZONA_AIF3TX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF3TX2", NULL, 1,
ARIZONA_AIF3_TX_ENABLES, ARIZONA_AIF3TX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF3RX1", NULL, 0,
ARIZONA_AIF3_RX_ENABLES, ARIZONA_AIF3RX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF3RX2", NULL, 1,
ARIZONA_AIF3_RX_ENABLES, ARIZONA_AIF3RX2_ENA_SHIFT, 0),
SND_SOC_DAPM_PGA_E("OUT1L", SND_SOC_NOPM,
ARIZONA_OUT1L_ENA_SHIFT, 0, NULL, 0, arizona_hp_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT1R", SND_SOC_NOPM,
ARIZONA_OUT1R_ENA_SHIFT, 0, NULL, 0, arizona_hp_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
ARIZONA_MIXER_WIDGETS(EQ1, "EQ1"),
ARIZONA_MIXER_WIDGETS(EQ2, "EQ2"),
ARIZONA_MIXER_WIDGETS(DRC1L, "DRC1L"),
ARIZONA_MIXER_WIDGETS(DRC1R, "DRC1R"),
ARIZONA_MIXER_WIDGETS(DRC2L, "DRC2L"),
ARIZONA_MIXER_WIDGETS(DRC2R, "DRC2R"),
ARIZONA_MIXER_WIDGETS(LHPF1, "LHPF1"),
ARIZONA_MIXER_WIDGETS(LHPF2, "LHPF2"),
ARIZONA_MIXER_WIDGETS(LHPF3, "LHPF3"),
ARIZONA_MIXER_WIDGETS(LHPF4, "LHPF4"),
ARIZONA_MIXER_WIDGETS(PWM1, "PWM1"),
ARIZONA_MIXER_WIDGETS(PWM2, "PWM2"),
ARIZONA_MIXER_WIDGETS(OUT1L, "HPOUT1L"),
ARIZONA_MIXER_WIDGETS(OUT1R, "HPOUT1R"),
ARIZONA_MIXER_WIDGETS(SPKOUT, "SPKOUT"),
ARIZONA_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"),
ARIZONA_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"),
ARIZONA_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"),
ARIZONA_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"),
ARIZONA_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"),
ARIZONA_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"),
ARIZONA_MIXER_WIDGETS(AIF1TX7, "AIF1TX7"),
ARIZONA_MIXER_WIDGETS(AIF1TX8, "AIF1TX8"),
ARIZONA_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"),
ARIZONA_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"),
ARIZONA_MIXER_WIDGETS(AIF2TX3, "AIF2TX3"),
ARIZONA_MIXER_WIDGETS(AIF2TX4, "AIF2TX4"),
ARIZONA_MIXER_WIDGETS(AIF2TX5, "AIF2TX5"),
ARIZONA_MIXER_WIDGETS(AIF2TX6, "AIF2TX6"),
ARIZONA_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"),
ARIZONA_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"),
ARIZONA_MUX_WIDGETS(ASRC1L, "ASRC1L"),
ARIZONA_MUX_WIDGETS(ASRC1R, "ASRC1R"),
ARIZONA_MUX_WIDGETS(ASRC2L, "ASRC2L"),
ARIZONA_MUX_WIDGETS(ASRC2R, "ASRC2R"),
ARIZONA_DSP_WIDGETS(DSP2, "DSP2"),
ARIZONA_DSP_WIDGETS(DSP3, "DSP3"),
ARIZONA_MUX_WIDGETS(ISRC1DEC1, "ISRC1DEC1"),
ARIZONA_MUX_WIDGETS(ISRC1DEC2, "ISRC1DEC2"),
ARIZONA_MUX_WIDGETS(ISRC1DEC3, "ISRC1DEC3"),
ARIZONA_MUX_WIDGETS(ISRC1DEC4, "ISRC1DEC4"),
ARIZONA_MUX_WIDGETS(ISRC1INT1, "ISRC1INT1"),
ARIZONA_MUX_WIDGETS(ISRC1INT2, "ISRC1INT2"),
ARIZONA_MUX_WIDGETS(ISRC1INT3, "ISRC1INT3"),
ARIZONA_MUX_WIDGETS(ISRC1INT4, "ISRC1INT4"),
ARIZONA_MUX_WIDGETS(ISRC2DEC1, "ISRC2DEC1"),
ARIZONA_MUX_WIDGETS(ISRC2DEC2, "ISRC2DEC2"),
ARIZONA_MUX_WIDGETS(ISRC2DEC3, "ISRC2DEC3"),
ARIZONA_MUX_WIDGETS(ISRC2DEC4, "ISRC2DEC4"),
ARIZONA_MUX_WIDGETS(ISRC2INT1, "ISRC2INT1"),
ARIZONA_MUX_WIDGETS(ISRC2INT2, "ISRC2INT2"),
ARIZONA_MUX_WIDGETS(ISRC2INT3, "ISRC2INT3"),
ARIZONA_MUX_WIDGETS(ISRC2INT4, "ISRC2INT4"),
ARIZONA_MUX_WIDGETS(ISRC3DEC1, "ISRC3DEC1"),
ARIZONA_MUX_WIDGETS(ISRC3DEC2, "ISRC3DEC2"),
ARIZONA_MUX_WIDGETS(ISRC3DEC3, "ISRC3DEC3"),
ARIZONA_MUX_WIDGETS(ISRC3DEC4, "ISRC3DEC4"),
ARIZONA_MUX_WIDGETS(ISRC3INT1, "ISRC3INT1"),
ARIZONA_MUX_WIDGETS(ISRC3INT2, "ISRC3INT2"),
ARIZONA_MUX_WIDGETS(ISRC3INT3, "ISRC3INT3"),
ARIZONA_MUX_WIDGETS(ISRC3INT4, "ISRC3INT4"),
SND_SOC_DAPM_OUTPUT("HPOUT1L"),
SND_SOC_DAPM_OUTPUT("HPOUT1R"),
SND_SOC_DAPM_OUTPUT("SPKOUTN"),
SND_SOC_DAPM_OUTPUT("SPKOUTP"),
SND_SOC_DAPM_OUTPUT("MICSUPP"),
};
#define ARIZONA_MIXER_INPUT_ROUTES(name) \
{ name, "Noise Generator", "Noise Generator" }, \
{ name, "Tone Generator 1", "Tone Generator 1" }, \
{ name, "Tone Generator 2", "Tone Generator 2" }, \
{ name, "Haptics", "HAPTICS" }, \
{ name, "AEC", "AEC Loopback" }, \
{ name, "IN1L", "IN1L PGA" }, \
{ name, "IN1R", "IN1R PGA" }, \
{ name, "IN2L", "IN2L PGA" }, \
{ name, "IN2R", "IN2R PGA" }, \
{ name, "AIF1RX1", "AIF1RX1" }, \
{ name, "AIF1RX2", "AIF1RX2" }, \
{ name, "AIF1RX3", "AIF1RX3" }, \
{ name, "AIF1RX4", "AIF1RX4" }, \
{ name, "AIF1RX5", "AIF1RX5" }, \
{ name, "AIF1RX6", "AIF1RX6" }, \
{ name, "AIF1RX7", "AIF1RX7" }, \
{ name, "AIF1RX8", "AIF1RX8" }, \
{ name, "AIF2RX1", "AIF2RX1" }, \
{ name, "AIF2RX2", "AIF2RX2" }, \
{ name, "AIF2RX3", "AIF2RX3" }, \
{ name, "AIF2RX4", "AIF2RX4" }, \
{ name, "AIF2RX5", "AIF2RX5" }, \
{ name, "AIF2RX6", "AIF2RX6" }, \
{ name, "AIF3RX1", "AIF3RX1" }, \
{ name, "AIF3RX2", "AIF3RX2" }, \
{ name, "EQ1", "EQ1" }, \
{ name, "EQ2", "EQ2" }, \
{ name, "DRC1L", "DRC1L" }, \
{ name, "DRC1R", "DRC1R" }, \
{ name, "DRC2L", "DRC2L" }, \
{ name, "DRC2R", "DRC2R" }, \
{ name, "LHPF1", "LHPF1" }, \
{ name, "LHPF2", "LHPF2" }, \
{ name, "LHPF3", "LHPF3" }, \
{ name, "LHPF4", "LHPF4" }, \
{ name, "ASRC1L", "ASRC1L" }, \
{ name, "ASRC1R", "ASRC1R" }, \
{ name, "ASRC2L", "ASRC2L" }, \
{ name, "ASRC2R", "ASRC2R" }, \
{ name, "ISRC1DEC1", "ISRC1DEC1" }, \
{ name, "ISRC1DEC2", "ISRC1DEC2" }, \
{ name, "ISRC1DEC3", "ISRC1DEC3" }, \
{ name, "ISRC1DEC4", "ISRC1DEC4" }, \
{ name, "ISRC1INT1", "ISRC1INT1" }, \
{ name, "ISRC1INT2", "ISRC1INT2" }, \
{ name, "ISRC1INT3", "ISRC1INT3" }, \
{ name, "ISRC1INT4", "ISRC1INT4" }, \
{ name, "ISRC2DEC1", "ISRC2DEC1" }, \
{ name, "ISRC2DEC2", "ISRC2DEC2" }, \
{ name, "ISRC2DEC3", "ISRC2DEC3" }, \
{ name, "ISRC2DEC4", "ISRC2DEC4" }, \
{ name, "ISRC2INT1", "ISRC2INT1" }, \
{ name, "ISRC2INT2", "ISRC2INT2" }, \
{ name, "ISRC2INT3", "ISRC2INT3" }, \
{ name, "ISRC2INT4", "ISRC2INT4" }, \
{ name, "ISRC3DEC1", "ISRC3DEC1" }, \
{ name, "ISRC3DEC2", "ISRC3DEC2" }, \
{ name, "ISRC3DEC3", "ISRC3DEC3" }, \
{ name, "ISRC3DEC4", "ISRC3DEC4" }, \
{ name, "ISRC3INT1", "ISRC3INT1" }, \
{ name, "ISRC3INT2", "ISRC3INT2" }, \
{ name, "ISRC3INT3", "ISRC3INT3" }, \
{ name, "ISRC3INT4", "ISRC3INT4" }, \
{ name, "DSP2.1", "DSP2" }, \
{ name, "DSP2.2", "DSP2" }, \
{ name, "DSP2.3", "DSP2" }, \
{ name, "DSP2.4", "DSP2" }, \
{ name, "DSP2.5", "DSP2" }, \
{ name, "DSP2.6", "DSP2" }, \
{ name, "DSP3.1", "DSP3" }, \
{ name, "DSP3.2", "DSP3" }, \
{ name, "DSP3.3", "DSP3" }, \
{ name, "DSP3.4", "DSP3" }, \
{ name, "DSP3.5", "DSP3" }, \
{ name, "DSP3.6", "DSP3" }
static const struct snd_soc_dapm_route cs47l24_dapm_routes[] = {
{ "OUT1L", NULL, "CPVDD" },
{ "OUT1R", NULL, "CPVDD" },
{ "OUT4L", NULL, "SPKVDD" },
{ "OUT1L", NULL, "SYSCLK" },
{ "OUT1R", NULL, "SYSCLK" },
{ "OUT4L", NULL, "SYSCLK" },
{ "IN1L", NULL, "SYSCLK" },
{ "IN1R", NULL, "SYSCLK" },
{ "IN2L", NULL, "SYSCLK" },
{ "IN2R", NULL, "SYSCLK" },
{ "ASRC1L", NULL, "SYSCLK" },
{ "ASRC1R", NULL, "SYSCLK" },
{ "ASRC2L", NULL, "SYSCLK" },
{ "ASRC2R", NULL, "SYSCLK" },
{ "ASRC1L", NULL, "ASYNCCLK" },
{ "ASRC1R", NULL, "ASYNCCLK" },
{ "ASRC2L", NULL, "ASYNCCLK" },
{ "ASRC2R", NULL, "ASYNCCLK" },
{ "MICBIAS1", NULL, "MICVDD" },
{ "MICBIAS2", NULL, "MICVDD" },
{ "Noise Generator", NULL, "SYSCLK" },
{ "Tone Generator 1", NULL, "SYSCLK" },
{ "Tone Generator 2", NULL, "SYSCLK" },
{ "Noise Generator", NULL, "NOISE" },
{ "Tone Generator 1", NULL, "TONE" },
{ "Tone Generator 2", NULL, "TONE" },
{ "AIF1 Capture", NULL, "AIF1TX1" },
{ "AIF1 Capture", NULL, "AIF1TX2" },
{ "AIF1 Capture", NULL, "AIF1TX3" },
{ "AIF1 Capture", NULL, "AIF1TX4" },
{ "AIF1 Capture", NULL, "AIF1TX5" },
{ "AIF1 Capture", NULL, "AIF1TX6" },
{ "AIF1 Capture", NULL, "AIF1TX7" },
{ "AIF1 Capture", NULL, "AIF1TX8" },
{ "AIF1RX1", NULL, "AIF1 Playback" },
{ "AIF1RX2", NULL, "AIF1 Playback" },
{ "AIF1RX3", NULL, "AIF1 Playback" },
{ "AIF1RX4", NULL, "AIF1 Playback" },
{ "AIF1RX5", NULL, "AIF1 Playback" },
{ "AIF1RX6", NULL, "AIF1 Playback" },
{ "AIF1RX7", NULL, "AIF1 Playback" },
{ "AIF1RX8", NULL, "AIF1 Playback" },
{ "AIF2 Capture", NULL, "AIF2TX1" },
{ "AIF2 Capture", NULL, "AIF2TX2" },
{ "AIF2 Capture", NULL, "AIF2TX3" },
{ "AIF2 Capture", NULL, "AIF2TX4" },
{ "AIF2 Capture", NULL, "AIF2TX5" },
{ "AIF2 Capture", NULL, "AIF2TX6" },
{ "AIF2RX1", NULL, "AIF2 Playback" },
{ "AIF2RX2", NULL, "AIF2 Playback" },
{ "AIF2RX3", NULL, "AIF2 Playback" },
{ "AIF2RX4", NULL, "AIF2 Playback" },
{ "AIF2RX5", NULL, "AIF2 Playback" },
{ "AIF2RX6", NULL, "AIF2 Playback" },
{ "AIF3 Capture", NULL, "AIF3TX1" },
{ "AIF3 Capture", NULL, "AIF3TX2" },
{ "AIF3RX1", NULL, "AIF3 Playback" },
{ "AIF3RX2", NULL, "AIF3 Playback" },
{ "AIF1 Playback", NULL, "SYSCLK" },
{ "AIF2 Playback", NULL, "SYSCLK" },
{ "AIF3 Playback", NULL, "SYSCLK" },
{ "AIF1 Capture", NULL, "SYSCLK" },
{ "AIF2 Capture", NULL, "SYSCLK" },
{ "AIF3 Capture", NULL, "SYSCLK" },
{ "Voice Control DSP", NULL, "DSP3" },
{ "IN1L PGA", NULL, "IN1L" },
{ "IN1R PGA", NULL, "IN1R" },
{ "IN2L PGA", NULL, "IN2L" },
{ "IN2R PGA", NULL, "IN2R" },
{ "Audio Trace DSP", NULL, "DSP2" },
ARIZONA_MIXER_ROUTES("OUT1L", "HPOUT1L"),
ARIZONA_MIXER_ROUTES("OUT1R", "HPOUT1R"),
ARIZONA_MIXER_ROUTES("OUT4L", "SPKOUT"),
ARIZONA_MIXER_ROUTES("PWM1 Driver", "PWM1"),
ARIZONA_MIXER_ROUTES("PWM2 Driver", "PWM2"),
ARIZONA_MIXER_ROUTES("AIF1TX1", "AIF1TX1"),
ARIZONA_MIXER_ROUTES("AIF1TX2", "AIF1TX2"),
ARIZONA_MIXER_ROUTES("AIF1TX3", "AIF1TX3"),
ARIZONA_MIXER_ROUTES("AIF1TX4", "AIF1TX4"),
ARIZONA_MIXER_ROUTES("AIF1TX5", "AIF1TX5"),
ARIZONA_MIXER_ROUTES("AIF1TX6", "AIF1TX6"),
ARIZONA_MIXER_ROUTES("AIF1TX7", "AIF1TX7"),
ARIZONA_MIXER_ROUTES("AIF1TX8", "AIF1TX8"),
ARIZONA_MIXER_ROUTES("AIF2TX1", "AIF2TX1"),
ARIZONA_MIXER_ROUTES("AIF2TX2", "AIF2TX2"),
ARIZONA_MIXER_ROUTES("AIF2TX3", "AIF2TX3"),
ARIZONA_MIXER_ROUTES("AIF2TX4", "AIF2TX4"),
ARIZONA_MIXER_ROUTES("AIF2TX5", "AIF2TX5"),
ARIZONA_MIXER_ROUTES("AIF2TX6", "AIF2TX6"),
ARIZONA_MIXER_ROUTES("AIF3TX1", "AIF3TX1"),
ARIZONA_MIXER_ROUTES("AIF3TX2", "AIF3TX2"),
ARIZONA_MIXER_ROUTES("EQ1", "EQ1"),
ARIZONA_MIXER_ROUTES("EQ2", "EQ2"),
ARIZONA_MIXER_ROUTES("DRC1L", "DRC1L"),
ARIZONA_MIXER_ROUTES("DRC1R", "DRC1R"),
ARIZONA_MIXER_ROUTES("DRC2L", "DRC2L"),
ARIZONA_MIXER_ROUTES("DRC2R", "DRC2R"),
ARIZONA_MIXER_ROUTES("LHPF1", "LHPF1"),
ARIZONA_MIXER_ROUTES("LHPF2", "LHPF2"),
ARIZONA_MIXER_ROUTES("LHPF3", "LHPF3"),
ARIZONA_MIXER_ROUTES("LHPF4", "LHPF4"),
ARIZONA_MUX_ROUTES("ASRC1L", "ASRC1L"),
ARIZONA_MUX_ROUTES("ASRC1R", "ASRC1R"),
ARIZONA_MUX_ROUTES("ASRC2L", "ASRC2L"),
ARIZONA_MUX_ROUTES("ASRC2R", "ASRC2R"),
ARIZONA_DSP_ROUTES("DSP2"),
ARIZONA_DSP_ROUTES("DSP3"),
ARIZONA_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"),
ARIZONA_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"),
ARIZONA_MUX_ROUTES("ISRC1INT3", "ISRC1INT3"),
ARIZONA_MUX_ROUTES("ISRC1INT4", "ISRC1INT4"),
ARIZONA_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"),
ARIZONA_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"),
ARIZONA_MUX_ROUTES("ISRC1DEC3", "ISRC1DEC3"),
ARIZONA_MUX_ROUTES("ISRC1DEC4", "ISRC1DEC4"),
ARIZONA_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"),
ARIZONA_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"),
ARIZONA_MUX_ROUTES("ISRC2INT3", "ISRC2INT3"),
ARIZONA_MUX_ROUTES("ISRC2INT4", "ISRC2INT4"),
ARIZONA_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"),
ARIZONA_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"),
ARIZONA_MUX_ROUTES("ISRC2DEC3", "ISRC2DEC3"),
ARIZONA_MUX_ROUTES("ISRC2DEC4", "ISRC2DEC4"),
ARIZONA_MUX_ROUTES("ISRC3INT1", "ISRC3INT1"),
ARIZONA_MUX_ROUTES("ISRC3INT2", "ISRC3INT2"),
ARIZONA_MUX_ROUTES("ISRC3INT3", "ISRC3INT3"),
ARIZONA_MUX_ROUTES("ISRC3INT4", "ISRC3INT4"),
ARIZONA_MUX_ROUTES("ISRC3DEC1", "ISRC3DEC1"),
ARIZONA_MUX_ROUTES("ISRC3DEC2", "ISRC3DEC2"),
ARIZONA_MUX_ROUTES("ISRC3DEC3", "ISRC3DEC3"),
ARIZONA_MUX_ROUTES("ISRC3DEC4", "ISRC3DEC4"),
{ "AEC Loopback", "HPOUT1L", "OUT1L" },
{ "AEC Loopback", "HPOUT1R", "OUT1R" },
{ "HPOUT1L", NULL, "OUT1L" },
{ "HPOUT1R", NULL, "OUT1R" },
{ "AEC Loopback", "SPKOUT", "OUT4L" },
{ "SPKOUTN", NULL, "OUT4L" },
{ "SPKOUTP", NULL, "OUT4L" },
{ "MICSUPP", NULL, "SYSCLK" },
{ "DRC1 Signal Activity", NULL, "SYSCLK" },
{ "DRC2 Signal Activity", NULL, "SYSCLK" },
{ "DRC1 Signal Activity", NULL, "DRC1L" },
{ "DRC1 Signal Activity", NULL, "DRC1R" },
{ "DRC2 Signal Activity", NULL, "DRC2L" },
{ "DRC2 Signal Activity", NULL, "DRC2R" },
{ "DSP Voice Trigger", NULL, "SYSCLK" },
{ "DSP Voice Trigger", NULL, "DSP3 Voice Trigger" },
{ "DSP3 Voice Trigger", "Switch", "DSP3" },
};
static int cs47l24_set_fll(struct snd_soc_component *component, int fll_id,
int source, unsigned int Fref, unsigned int Fout)
{
struct cs47l24_priv *cs47l24 = snd_soc_component_get_drvdata(component);
switch (fll_id) {
case CS47L24_FLL1:
return arizona_set_fll(&cs47l24->fll[0], source, Fref, Fout);
case CS47L24_FLL2:
return arizona_set_fll(&cs47l24->fll[1], source, Fref, Fout);
case CS47L24_FLL1_REFCLK:
return arizona_set_fll_refclk(&cs47l24->fll[0], source, Fref,
Fout);
case CS47L24_FLL2_REFCLK:
return arizona_set_fll_refclk(&cs47l24->fll[1], source, Fref,
Fout);
default:
return -EINVAL;
}
}
#define CS47L24_RATES SNDRV_PCM_RATE_KNOT
#define CS47L24_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops cs47l24_dai_ops = {
.compress_new = snd_soc_new_compress,
};
static struct snd_soc_dai_driver cs47l24_dai[] = {
{
.name = "cs47l24-aif1",
.id = 1,
.base = ARIZONA_AIF1_BCLK_CTRL,
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 8,
.rates = CS47L24_RATES,
.formats = CS47L24_FORMATS,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 1,
.channels_max = 8,
.rates = CS47L24_RATES,
.formats = CS47L24_FORMATS,
},
.ops = &arizona_dai_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
{
.name = "cs47l24-aif2",
.id = 2,
.base = ARIZONA_AIF2_BCLK_CTRL,
.playback = {
.stream_name = "AIF2 Playback",
.channels_min = 1,
.channels_max = 6,
.rates = CS47L24_RATES,
.formats = CS47L24_FORMATS,
},
.capture = {
.stream_name = "AIF2 Capture",
.channels_min = 1,
.channels_max = 6,
.rates = CS47L24_RATES,
.formats = CS47L24_FORMATS,
},
.ops = &arizona_dai_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
{
.name = "cs47l24-aif3",
.id = 3,
.base = ARIZONA_AIF3_BCLK_CTRL,
.playback = {
.stream_name = "AIF3 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = CS47L24_RATES,
.formats = CS47L24_FORMATS,
},
.capture = {
.stream_name = "AIF3 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = CS47L24_RATES,
.formats = CS47L24_FORMATS,
},
.ops = &arizona_dai_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
{
.name = "cs47l24-cpu-voicectrl",
.capture = {
.stream_name = "Voice Control CPU",
.channels_min = 1,
.channels_max = 1,
.rates = CS47L24_RATES,
.formats = CS47L24_FORMATS,
},
.ops = &cs47l24_dai_ops,
},
{
.name = "cs47l24-dsp-voicectrl",
.capture = {
.stream_name = "Voice Control DSP",
.channels_min = 1,
.channels_max = 1,
.rates = CS47L24_RATES,
.formats = CS47L24_FORMATS,
},
},
{
.name = "cs47l24-cpu-trace",
.capture = {
.stream_name = "Audio Trace CPU",
.channels_min = 1,
.channels_max = 6,
.rates = CS47L24_RATES,
.formats = CS47L24_FORMATS,
},
.ops = &cs47l24_dai_ops,
},
{
.name = "cs47l24-dsp-trace",
.capture = {
.stream_name = "Audio Trace DSP",
.channels_min = 1,
.channels_max = 6,
.rates = CS47L24_RATES,
.formats = CS47L24_FORMATS,
},
},
};
static int cs47l24_open(struct snd_soc_component *component,
struct snd_compr_stream *stream)
{
struct snd_soc_pcm_runtime *rtd = stream->private_data;
struct cs47l24_priv *priv = snd_soc_component_get_drvdata(component);
struct arizona *arizona = priv->core.arizona;
int n_adsp;
if (strcmp(asoc_rtd_to_codec(rtd, 0)->name, "cs47l24-dsp-voicectrl") == 0) {
n_adsp = 2;
} else if (strcmp(asoc_rtd_to_codec(rtd, 0)->name, "cs47l24-dsp-trace") == 0) {
n_adsp = 1;
} else {
dev_err(arizona->dev,
"No suitable compressed stream for DAI '%s'\n",
asoc_rtd_to_codec(rtd, 0)->name);
return -EINVAL;
}
return wm_adsp_compr_open(&priv->core.adsp[n_adsp], stream);
}
static irqreturn_t cs47l24_adsp2_irq(int irq, void *data)
{
struct cs47l24_priv *priv = data;
struct arizona *arizona = priv->core.arizona;
struct arizona_voice_trigger_info info;
int serviced = 0;
int i, ret;
for (i = 1; i <= 2; ++i) {
ret = wm_adsp_compr_handle_irq(&priv->core.adsp[i]);
if (ret != -ENODEV)
serviced++;
if (ret == WM_ADSP_COMPR_VOICE_TRIGGER) {
info.core = i;
arizona_call_notifiers(arizona,
ARIZONA_NOTIFY_VOICE_TRIGGER,
&info);
}
}
if (!serviced) {
dev_err(arizona->dev, "Spurious compressed data IRQ\n");
return IRQ_NONE;
}
return IRQ_HANDLED;
}
static int cs47l24_component_probe(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct cs47l24_priv *priv = snd_soc_component_get_drvdata(component);
struct arizona *arizona = priv->core.arizona;
int ret;
arizona->dapm = dapm;
snd_soc_component_init_regmap(component, arizona->regmap);
ret = arizona_init_spk(component);
if (ret < 0)
return ret;
arizona_init_gpio(component);
arizona_init_mono(component);
ret = wm_adsp2_component_probe(&priv->core.adsp[1], component);
if (ret)
goto err_adsp2_codec_probe;
ret = wm_adsp2_component_probe(&priv->core.adsp[2], component);
if (ret)
goto err_adsp2_codec_probe;
ret = snd_soc_add_component_controls(component,
&arizona_adsp2_rate_controls[1],
2);
if (ret)
goto err_adsp2_codec_probe;
snd_soc_component_disable_pin(component, "HAPTICS");
return 0;
err_adsp2_codec_probe:
wm_adsp2_component_remove(&priv->core.adsp[1], component);
wm_adsp2_component_remove(&priv->core.adsp[2], component);
return ret;
}
static void cs47l24_component_remove(struct snd_soc_component *component)
{
struct cs47l24_priv *priv = snd_soc_component_get_drvdata(component);
wm_adsp2_component_remove(&priv->core.adsp[1], component);
wm_adsp2_component_remove(&priv->core.adsp[2], component);
priv->core.arizona->dapm = NULL;
}
#define CS47L24_DIG_VU 0x0200
static unsigned int cs47l24_digital_vu[] = {
ARIZONA_DAC_DIGITAL_VOLUME_1L,
ARIZONA_DAC_DIGITAL_VOLUME_1R,
ARIZONA_DAC_DIGITAL_VOLUME_4L,
};
static const struct snd_compress_ops cs47l24_compress_ops = {
.open = cs47l24_open,
.free = wm_adsp_compr_free,
.set_params = wm_adsp_compr_set_params,
.get_caps = wm_adsp_compr_get_caps,
.trigger = wm_adsp_compr_trigger,
.pointer = wm_adsp_compr_pointer,
.copy = wm_adsp_compr_copy,
};
static const struct snd_soc_component_driver soc_component_dev_cs47l24 = {
.probe = cs47l24_component_probe,
.remove = cs47l24_component_remove,
.set_sysclk = arizona_set_sysclk,
.set_pll = cs47l24_set_fll,
.name = DRV_NAME,
.compress_ops = &cs47l24_compress_ops,
.controls = cs47l24_snd_controls,
.num_controls = ARRAY_SIZE(cs47l24_snd_controls),
.dapm_widgets = cs47l24_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(cs47l24_dapm_widgets),
.dapm_routes = cs47l24_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(cs47l24_dapm_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
static int cs47l24_probe(struct platform_device *pdev)
{
struct arizona *arizona = dev_get_drvdata(pdev->dev.parent);
struct cs47l24_priv *cs47l24;
int i, ret;
BUILD_BUG_ON(ARRAY_SIZE(cs47l24_dai) > ARIZONA_MAX_DAI);
cs47l24 = devm_kzalloc(&pdev->dev, sizeof(struct cs47l24_priv),
GFP_KERNEL);
if (!cs47l24)
return -ENOMEM;
if (IS_ENABLED(CONFIG_OF)) {
if (!dev_get_platdata(arizona->dev)) {
ret = arizona_of_get_audio_pdata(arizona);
if (ret < 0)
return ret;
}
}
platform_set_drvdata(pdev, cs47l24);
cs47l24->core.arizona = arizona;
cs47l24->core.num_inputs = 4;
for (i = 1; i <= 2; i++) {
cs47l24->core.adsp[i].part = "cs47l24";
cs47l24->core.adsp[i].cs_dsp.num = i + 1;
cs47l24->core.adsp[i].cs_dsp.type = WMFW_ADSP2;
cs47l24->core.adsp[i].cs_dsp.dev = arizona->dev;
cs47l24->core.adsp[i].cs_dsp.regmap = arizona->regmap;
cs47l24->core.adsp[i].cs_dsp.base = ARIZONA_DSP1_CONTROL_1 +
(0x100 * i);
cs47l24->core.adsp[i].cs_dsp.mem = cs47l24_dsp_regions[i - 1];
cs47l24->core.adsp[i].cs_dsp.num_mems =
ARRAY_SIZE(cs47l24_dsp2_regions);
ret = wm_adsp2_init(&cs47l24->core.adsp[i]);
if (ret != 0)
return ret;
}
for (i = 0; i < ARRAY_SIZE(cs47l24->fll); i++)
cs47l24->fll[i].vco_mult = 3;
arizona_init_fll(arizona, 1, ARIZONA_FLL1_CONTROL_1 - 1,
ARIZONA_IRQ_FLL1_LOCK, ARIZONA_IRQ_FLL1_CLOCK_OK,
&cs47l24->fll[0]);
arizona_init_fll(arizona, 2, ARIZONA_FLL2_CONTROL_1 - 1,
ARIZONA_IRQ_FLL2_LOCK, ARIZONA_IRQ_FLL2_CLOCK_OK,
&cs47l24->fll[1]);
/* SR2 fixed at 8kHz, SR3 fixed at 16kHz */
regmap_update_bits(arizona->regmap, ARIZONA_SAMPLE_RATE_2,
ARIZONA_SAMPLE_RATE_2_MASK, 0x11);
regmap_update_bits(arizona->regmap, ARIZONA_SAMPLE_RATE_3,
ARIZONA_SAMPLE_RATE_3_MASK, 0x12);
for (i = 0; i < ARRAY_SIZE(cs47l24_dai); i++)
arizona_init_dai(&cs47l24->core, i);
/* Latch volume update bits */
for (i = 0; i < ARRAY_SIZE(cs47l24_digital_vu); i++)
regmap_update_bits(arizona->regmap, cs47l24_digital_vu[i],
CS47L24_DIG_VU, CS47L24_DIG_VU);
pm_runtime_enable(&pdev->dev);
pm_runtime_idle(&pdev->dev);
ret = arizona_request_irq(arizona, ARIZONA_IRQ_DSP_IRQ1,
"ADSP2 Compressed IRQ", cs47l24_adsp2_irq,
cs47l24);
if (ret != 0) {
dev_err(&pdev->dev, "Failed to request DSP IRQ: %d\n", ret);
return ret;
}
ret = arizona_set_irq_wake(arizona, ARIZONA_IRQ_DSP_IRQ1, 1);
if (ret != 0)
dev_warn(&pdev->dev,
"Failed to set compressed IRQ as a wake source: %d\n",
ret);
arizona_init_common(arizona);
ret = arizona_init_vol_limit(arizona);
if (ret < 0)
goto err_dsp_irq;
ret = arizona_init_spk_irqs(arizona);
if (ret < 0)
goto err_dsp_irq;
ret = devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_cs47l24,
cs47l24_dai,
ARRAY_SIZE(cs47l24_dai));
if (ret < 0) {
dev_err(&pdev->dev, "Failed to register component: %d\n", ret);
goto err_spk_irqs;
}
return ret;
err_spk_irqs:
arizona_free_spk_irqs(arizona);
err_dsp_irq:
arizona_set_irq_wake(arizona, ARIZONA_IRQ_DSP_IRQ1, 0);
arizona_free_irq(arizona, ARIZONA_IRQ_DSP_IRQ1, cs47l24);
return ret;
}
static void cs47l24_remove(struct platform_device *pdev)
{
struct cs47l24_priv *cs47l24 = platform_get_drvdata(pdev);
struct arizona *arizona = cs47l24->core.arizona;
pm_runtime_disable(&pdev->dev);
wm_adsp2_remove(&cs47l24->core.adsp[1]);
wm_adsp2_remove(&cs47l24->core.adsp[2]);
arizona_free_spk_irqs(arizona);
arizona_set_irq_wake(arizona, ARIZONA_IRQ_DSP_IRQ1, 0);
arizona_free_irq(arizona, ARIZONA_IRQ_DSP_IRQ1, cs47l24);
}
static struct platform_driver cs47l24_codec_driver = {
.driver = {
.name = "cs47l24-codec",
},
.probe = cs47l24_probe,
.remove_new = cs47l24_remove,
};
module_platform_driver(cs47l24_codec_driver);
MODULE_DESCRIPTION("ASoC CS47L24 driver");
MODULE_AUTHOR("Richard Fitzgerald <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:cs47l24-codec");
| linux-master | sound/soc/codecs/cs47l24.c |
// SPDX-License-Identifier: GPL-2.0
//
// cs35l36.c -- CS35L36 ALSA SoC audio driver
//
// Copyright 2018 Cirrus Logic, Inc.
//
// Author: James Schulman <[email protected]>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/workqueue.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/gpio/consumer.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <linux/gpio.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/cs35l36.h>
#include <linux/of_irq.h>
#include <linux/completion.h>
#include "cs35l36.h"
/*
* Some fields take zero as a valid value so use a high bit flag that won't
* get written to the device to mark those.
*/
#define CS35L36_VALID_PDATA 0x80000000
static const char * const cs35l36_supplies[] = {
"VA",
"VP",
};
struct cs35l36_private {
struct device *dev;
struct cs35l36_platform_data pdata;
struct regmap *regmap;
struct regulator_bulk_data supplies[2];
int num_supplies;
int clksrc;
int chip_version;
int rev_id;
int ldm_mode_sel;
struct gpio_desc *reset_gpio;
};
struct cs35l36_pll_config {
int freq;
int clk_cfg;
int fll_igain;
};
static const struct cs35l36_pll_config cs35l36_pll_sysclk[] = {
{32768, 0x00, 0x05},
{8000, 0x01, 0x03},
{11025, 0x02, 0x03},
{12000, 0x03, 0x03},
{16000, 0x04, 0x04},
{22050, 0x05, 0x04},
{24000, 0x06, 0x04},
{32000, 0x07, 0x05},
{44100, 0x08, 0x05},
{48000, 0x09, 0x05},
{88200, 0x0A, 0x06},
{96000, 0x0B, 0x06},
{128000, 0x0C, 0x07},
{176400, 0x0D, 0x07},
{192000, 0x0E, 0x07},
{256000, 0x0F, 0x08},
{352800, 0x10, 0x08},
{384000, 0x11, 0x08},
{512000, 0x12, 0x09},
{705600, 0x13, 0x09},
{750000, 0x14, 0x09},
{768000, 0x15, 0x09},
{1000000, 0x16, 0x0A},
{1024000, 0x17, 0x0A},
{1200000, 0x18, 0x0A},
{1411200, 0x19, 0x0A},
{1500000, 0x1A, 0x0A},
{1536000, 0x1B, 0x0A},
{2000000, 0x1C, 0x0A},
{2048000, 0x1D, 0x0A},
{2400000, 0x1E, 0x0A},
{2822400, 0x1F, 0x0A},
{3000000, 0x20, 0x0A},
{3072000, 0x21, 0x0A},
{3200000, 0x22, 0x0A},
{4000000, 0x23, 0x0A},
{4096000, 0x24, 0x0A},
{4800000, 0x25, 0x0A},
{5644800, 0x26, 0x0A},
{6000000, 0x27, 0x0A},
{6144000, 0x28, 0x0A},
{6250000, 0x29, 0x08},
{6400000, 0x2A, 0x0A},
{6500000, 0x2B, 0x08},
{6750000, 0x2C, 0x09},
{7526400, 0x2D, 0x0A},
{8000000, 0x2E, 0x0A},
{8192000, 0x2F, 0x0A},
{9600000, 0x30, 0x0A},
{11289600, 0x31, 0x0A},
{12000000, 0x32, 0x0A},
{12288000, 0x33, 0x0A},
{12500000, 0x34, 0x08},
{12800000, 0x35, 0x0A},
{13000000, 0x36, 0x0A},
{13500000, 0x37, 0x0A},
{19200000, 0x38, 0x0A},
{22579200, 0x39, 0x0A},
{24000000, 0x3A, 0x0A},
{24576000, 0x3B, 0x0A},
{25000000, 0x3C, 0x0A},
{25600000, 0x3D, 0x0A},
{26000000, 0x3E, 0x0A},
{27000000, 0x3F, 0x0A},
};
static struct reg_default cs35l36_reg[] = {
{CS35L36_TESTKEY_CTRL, 0x00000000},
{CS35L36_USERKEY_CTL, 0x00000000},
{CS35L36_OTP_CTRL1, 0x00002460},
{CS35L36_OTP_CTRL2, 0x00000000},
{CS35L36_OTP_CTRL3, 0x00000000},
{CS35L36_OTP_CTRL4, 0x00000000},
{CS35L36_OTP_CTRL5, 0x00000000},
{CS35L36_PAC_CTL1, 0x00000004},
{CS35L36_PAC_CTL2, 0x00000000},
{CS35L36_PAC_CTL3, 0x00000000},
{CS35L36_PWR_CTRL1, 0x00000000},
{CS35L36_PWR_CTRL2, 0x00003321},
{CS35L36_PWR_CTRL3, 0x01000010},
{CS35L36_CTRL_OVRRIDE, 0x00000002},
{CS35L36_AMP_OUT_MUTE, 0x00000000},
{CS35L36_OTP_TRIM_STATUS, 0x00000000},
{CS35L36_DISCH_FILT, 0x00000000},
{CS35L36_PROTECT_REL_ERR, 0x00000000},
{CS35L36_PAD_INTERFACE, 0x00000038},
{CS35L36_PLL_CLK_CTRL, 0x00000010},
{CS35L36_GLOBAL_CLK_CTRL, 0x00000003},
{CS35L36_ADC_CLK_CTRL, 0x00000000},
{CS35L36_SWIRE_CLK_CTRL, 0x00000000},
{CS35L36_SP_SCLK_CLK_CTRL, 0x00000000},
{CS35L36_MDSYNC_EN, 0x00000000},
{CS35L36_MDSYNC_TX_ID, 0x00000000},
{CS35L36_MDSYNC_PWR_CTRL, 0x00000000},
{CS35L36_MDSYNC_DATA_TX, 0x00000000},
{CS35L36_MDSYNC_TX_STATUS, 0x00000002},
{CS35L36_MDSYNC_RX_STATUS, 0x00000000},
{CS35L36_MDSYNC_ERR_STATUS, 0x00000000},
{CS35L36_BSTCVRT_VCTRL1, 0x00000000},
{CS35L36_BSTCVRT_VCTRL2, 0x00000001},
{CS35L36_BSTCVRT_PEAK_CUR, 0x0000004A},
{CS35L36_BSTCVRT_SFT_RAMP, 0x00000003},
{CS35L36_BSTCVRT_COEFF, 0x00002424},
{CS35L36_BSTCVRT_SLOPE_LBST, 0x00005800},
{CS35L36_BSTCVRT_SW_FREQ, 0x00010000},
{CS35L36_BSTCVRT_DCM_CTRL, 0x00002001},
{CS35L36_BSTCVRT_DCM_MODE_FORCE, 0x00000000},
{CS35L36_BSTCVRT_OVERVOLT_CTRL, 0x00000130},
{CS35L36_VPI_LIMIT_MODE, 0x00000000},
{CS35L36_VPI_LIMIT_MINMAX, 0x00003000},
{CS35L36_VPI_VP_THLD, 0x00101010},
{CS35L36_VPI_TRACK_CTRL, 0x00000000},
{CS35L36_VPI_TRIG_MODE_CTRL, 0x00000000},
{CS35L36_VPI_TRIG_STEPS, 0x00000000},
{CS35L36_VI_SPKMON_FILT, 0x00000003},
{CS35L36_VI_SPKMON_GAIN, 0x00000909},
{CS35L36_VI_SPKMON_IP_SEL, 0x00000000},
{CS35L36_DTEMP_WARN_THLD, 0x00000002},
{CS35L36_DTEMP_STATUS, 0x00000000},
{CS35L36_VPVBST_FS_SEL, 0x00000001},
{CS35L36_VPVBST_VP_CTRL, 0x000001C0},
{CS35L36_VPVBST_VBST_CTRL, 0x000001C0},
{CS35L36_ASP_TX_PIN_CTRL, 0x00000028},
{CS35L36_ASP_RATE_CTRL, 0x00090000},
{CS35L36_ASP_FORMAT, 0x00000002},
{CS35L36_ASP_FRAME_CTRL, 0x00180018},
{CS35L36_ASP_TX1_TX2_SLOT, 0x00010000},
{CS35L36_ASP_TX3_TX4_SLOT, 0x00030002},
{CS35L36_ASP_TX5_TX6_SLOT, 0x00050004},
{CS35L36_ASP_TX7_TX8_SLOT, 0x00070006},
{CS35L36_ASP_RX1_SLOT, 0x00000000},
{CS35L36_ASP_RX_TX_EN, 0x00000000},
{CS35L36_ASP_RX1_SEL, 0x00000008},
{CS35L36_ASP_TX1_SEL, 0x00000018},
{CS35L36_ASP_TX2_SEL, 0x00000019},
{CS35L36_ASP_TX3_SEL, 0x00000028},
{CS35L36_ASP_TX4_SEL, 0x00000029},
{CS35L36_ASP_TX5_SEL, 0x00000020},
{CS35L36_ASP_TX6_SEL, 0x00000000},
{CS35L36_SWIRE_P1_TX1_SEL, 0x00000018},
{CS35L36_SWIRE_P1_TX2_SEL, 0x00000019},
{CS35L36_SWIRE_P2_TX1_SEL, 0x00000028},
{CS35L36_SWIRE_P2_TX2_SEL, 0x00000029},
{CS35L36_SWIRE_P2_TX3_SEL, 0x00000020},
{CS35L36_SWIRE_DP1_FIFO_CFG, 0x0000001B},
{CS35L36_SWIRE_DP2_FIFO_CFG, 0x0000001B},
{CS35L36_SWIRE_DP3_FIFO_CFG, 0x0000001B},
{CS35L36_SWIRE_PCM_RX_DATA, 0x00000000},
{CS35L36_SWIRE_FS_SEL, 0x00000001},
{CS35L36_AMP_DIG_VOL_CTRL, 0x00008000},
{CS35L36_VPBR_CFG, 0x02AA1905},
{CS35L36_VBBR_CFG, 0x02AA1905},
{CS35L36_VPBR_STATUS, 0x00000000},
{CS35L36_VBBR_STATUS, 0x00000000},
{CS35L36_OVERTEMP_CFG, 0x00000001},
{CS35L36_AMP_ERR_VOL, 0x00000000},
{CS35L36_CLASSH_CFG, 0x000B0405},
{CS35L36_CLASSH_FET_DRV_CFG, 0x00000111},
{CS35L36_NG_CFG, 0x00000033},
{CS35L36_AMP_GAIN_CTRL, 0x00000273},
{CS35L36_PWM_MOD_IO_CTRL, 0x00000000},
{CS35L36_PWM_MOD_STATUS, 0x00000000},
{CS35L36_DAC_MSM_CFG, 0x00000000},
{CS35L36_AMP_SLOPE_CTRL, 0x00000B00},
{CS35L36_AMP_PDM_VOLUME, 0x00000000},
{CS35L36_AMP_PDM_RATE_CTRL, 0x00000000},
{CS35L36_PDM_CH_SEL, 0x00000000},
{CS35L36_AMP_NG_CTRL, 0x0000212F},
{CS35L36_PDM_HIGHFILT_CTRL, 0x00000000},
{CS35L36_PAC_INT0_CTRL, 0x00000001},
{CS35L36_PAC_INT1_CTRL, 0x00000001},
{CS35L36_PAC_INT2_CTRL, 0x00000001},
{CS35L36_PAC_INT3_CTRL, 0x00000001},
{CS35L36_PAC_INT4_CTRL, 0x00000001},
{CS35L36_PAC_INT5_CTRL, 0x00000001},
{CS35L36_PAC_INT6_CTRL, 0x00000001},
{CS35L36_PAC_INT7_CTRL, 0x00000001},
};
static bool cs35l36_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS35L36_SW_RESET:
case CS35L36_SW_REV:
case CS35L36_HW_REV:
case CS35L36_TESTKEY_CTRL:
case CS35L36_USERKEY_CTL:
case CS35L36_OTP_MEM30:
case CS35L36_OTP_CTRL1:
case CS35L36_OTP_CTRL2:
case CS35L36_OTP_CTRL3:
case CS35L36_OTP_CTRL4:
case CS35L36_OTP_CTRL5:
case CS35L36_PAC_CTL1:
case CS35L36_PAC_CTL2:
case CS35L36_PAC_CTL3:
case CS35L36_DEVICE_ID:
case CS35L36_FAB_ID:
case CS35L36_REV_ID:
case CS35L36_PWR_CTRL1:
case CS35L36_PWR_CTRL2:
case CS35L36_PWR_CTRL3:
case CS35L36_CTRL_OVRRIDE:
case CS35L36_AMP_OUT_MUTE:
case CS35L36_OTP_TRIM_STATUS:
case CS35L36_DISCH_FILT:
case CS35L36_PROTECT_REL_ERR:
case CS35L36_PAD_INTERFACE:
case CS35L36_PLL_CLK_CTRL:
case CS35L36_GLOBAL_CLK_CTRL:
case CS35L36_ADC_CLK_CTRL:
case CS35L36_SWIRE_CLK_CTRL:
case CS35L36_SP_SCLK_CLK_CTRL:
case CS35L36_TST_FS_MON0:
case CS35L36_MDSYNC_EN:
case CS35L36_MDSYNC_TX_ID:
case CS35L36_MDSYNC_PWR_CTRL:
case CS35L36_MDSYNC_DATA_TX:
case CS35L36_MDSYNC_TX_STATUS:
case CS35L36_MDSYNC_RX_STATUS:
case CS35L36_MDSYNC_ERR_STATUS:
case CS35L36_BSTCVRT_VCTRL1:
case CS35L36_BSTCVRT_VCTRL2:
case CS35L36_BSTCVRT_PEAK_CUR:
case CS35L36_BSTCVRT_SFT_RAMP:
case CS35L36_BSTCVRT_COEFF:
case CS35L36_BSTCVRT_SLOPE_LBST:
case CS35L36_BSTCVRT_SW_FREQ:
case CS35L36_BSTCVRT_DCM_CTRL:
case CS35L36_BSTCVRT_DCM_MODE_FORCE:
case CS35L36_BSTCVRT_OVERVOLT_CTRL:
case CS35L36_BST_TST_MANUAL:
case CS35L36_BST_ANA2_TEST:
case CS35L36_VPI_LIMIT_MODE:
case CS35L36_VPI_LIMIT_MINMAX:
case CS35L36_VPI_VP_THLD:
case CS35L36_VPI_TRACK_CTRL:
case CS35L36_VPI_TRIG_MODE_CTRL:
case CS35L36_VPI_TRIG_STEPS:
case CS35L36_VI_SPKMON_FILT:
case CS35L36_VI_SPKMON_GAIN:
case CS35L36_VI_SPKMON_IP_SEL:
case CS35L36_DTEMP_WARN_THLD:
case CS35L36_DTEMP_STATUS:
case CS35L36_VPVBST_FS_SEL:
case CS35L36_VPVBST_VP_CTRL:
case CS35L36_VPVBST_VBST_CTRL:
case CS35L36_ASP_TX_PIN_CTRL:
case CS35L36_ASP_RATE_CTRL:
case CS35L36_ASP_FORMAT:
case CS35L36_ASP_FRAME_CTRL:
case CS35L36_ASP_TX1_TX2_SLOT:
case CS35L36_ASP_TX3_TX4_SLOT:
case CS35L36_ASP_TX5_TX6_SLOT:
case CS35L36_ASP_TX7_TX8_SLOT:
case CS35L36_ASP_RX1_SLOT:
case CS35L36_ASP_RX_TX_EN:
case CS35L36_ASP_RX1_SEL:
case CS35L36_ASP_TX1_SEL:
case CS35L36_ASP_TX2_SEL:
case CS35L36_ASP_TX3_SEL:
case CS35L36_ASP_TX4_SEL:
case CS35L36_ASP_TX5_SEL:
case CS35L36_ASP_TX6_SEL:
case CS35L36_SWIRE_P1_TX1_SEL:
case CS35L36_SWIRE_P1_TX2_SEL:
case CS35L36_SWIRE_P2_TX1_SEL:
case CS35L36_SWIRE_P2_TX2_SEL:
case CS35L36_SWIRE_P2_TX3_SEL:
case CS35L36_SWIRE_DP1_FIFO_CFG:
case CS35L36_SWIRE_DP2_FIFO_CFG:
case CS35L36_SWIRE_DP3_FIFO_CFG:
case CS35L36_SWIRE_PCM_RX_DATA:
case CS35L36_SWIRE_FS_SEL:
case CS35L36_AMP_DIG_VOL_CTRL:
case CS35L36_VPBR_CFG:
case CS35L36_VBBR_CFG:
case CS35L36_VPBR_STATUS:
case CS35L36_VBBR_STATUS:
case CS35L36_OVERTEMP_CFG:
case CS35L36_AMP_ERR_VOL:
case CS35L36_CLASSH_CFG:
case CS35L36_CLASSH_FET_DRV_CFG:
case CS35L36_NG_CFG:
case CS35L36_AMP_GAIN_CTRL:
case CS35L36_PWM_MOD_IO_CTRL:
case CS35L36_PWM_MOD_STATUS:
case CS35L36_DAC_MSM_CFG:
case CS35L36_AMP_SLOPE_CTRL:
case CS35L36_AMP_PDM_VOLUME:
case CS35L36_AMP_PDM_RATE_CTRL:
case CS35L36_PDM_CH_SEL:
case CS35L36_AMP_NG_CTRL:
case CS35L36_PDM_HIGHFILT_CTRL:
case CS35L36_INT1_STATUS:
case CS35L36_INT2_STATUS:
case CS35L36_INT3_STATUS:
case CS35L36_INT4_STATUS:
case CS35L36_INT1_RAW_STATUS:
case CS35L36_INT2_RAW_STATUS:
case CS35L36_INT3_RAW_STATUS:
case CS35L36_INT4_RAW_STATUS:
case CS35L36_INT1_MASK:
case CS35L36_INT2_MASK:
case CS35L36_INT3_MASK:
case CS35L36_INT4_MASK:
case CS35L36_INT1_EDGE_LVL_CTRL:
case CS35L36_INT3_EDGE_LVL_CTRL:
case CS35L36_PAC_INT_STATUS:
case CS35L36_PAC_INT_RAW_STATUS:
case CS35L36_PAC_INT_FLUSH_CTRL:
case CS35L36_PAC_INT0_CTRL:
case CS35L36_PAC_INT1_CTRL:
case CS35L36_PAC_INT2_CTRL:
case CS35L36_PAC_INT3_CTRL:
case CS35L36_PAC_INT4_CTRL:
case CS35L36_PAC_INT5_CTRL:
case CS35L36_PAC_INT6_CTRL:
case CS35L36_PAC_INT7_CTRL:
return true;
default:
if (reg >= CS35L36_PAC_PMEM_WORD0 &&
reg <= CS35L36_PAC_PMEM_WORD1023)
return true;
else
return false;
}
}
static bool cs35l36_precious_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS35L36_TESTKEY_CTRL:
case CS35L36_USERKEY_CTL:
case CS35L36_TST_FS_MON0:
return true;
default:
return false;
}
}
static bool cs35l36_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS35L36_SW_RESET:
case CS35L36_SW_REV:
case CS35L36_HW_REV:
case CS35L36_TESTKEY_CTRL:
case CS35L36_USERKEY_CTL:
case CS35L36_DEVICE_ID:
case CS35L36_FAB_ID:
case CS35L36_REV_ID:
case CS35L36_INT1_STATUS:
case CS35L36_INT2_STATUS:
case CS35L36_INT3_STATUS:
case CS35L36_INT4_STATUS:
case CS35L36_INT1_RAW_STATUS:
case CS35L36_INT2_RAW_STATUS:
case CS35L36_INT3_RAW_STATUS:
case CS35L36_INT4_RAW_STATUS:
case CS35L36_INT1_MASK:
case CS35L36_INT2_MASK:
case CS35L36_INT3_MASK:
case CS35L36_INT4_MASK:
case CS35L36_INT1_EDGE_LVL_CTRL:
case CS35L36_INT3_EDGE_LVL_CTRL:
case CS35L36_PAC_INT_STATUS:
case CS35L36_PAC_INT_RAW_STATUS:
case CS35L36_PAC_INT_FLUSH_CTRL:
return true;
default:
if (reg >= CS35L36_PAC_PMEM_WORD0 &&
reg <= CS35L36_PAC_PMEM_WORD1023)
return true;
else
return false;
}
}
static const DECLARE_TLV_DB_RANGE(dig_vol_tlv, 0, 912,
TLV_DB_MINMAX_ITEM(-10200, 1200));
static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 0, 1, 1);
static const char * const cs35l36_pcm_sftramp_text[] = {
"Off", ".5ms", "1ms", "2ms", "4ms", "8ms", "15ms", "30ms"};
static SOC_ENUM_SINGLE_DECL(pcm_sft_ramp, CS35L36_AMP_DIG_VOL_CTRL, 0,
cs35l36_pcm_sftramp_text);
static int cs35l36_ldm_sel_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct cs35l36_private *cs35l36 =
snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = cs35l36->ldm_mode_sel;
return 0;
}
static int cs35l36_ldm_sel_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct cs35l36_private *cs35l36 =
snd_soc_component_get_drvdata(component);
int val = (ucontrol->value.integer.value[0]) ? CS35L36_NG_AMP_EN_MASK :
0;
cs35l36->ldm_mode_sel = val;
regmap_update_bits(cs35l36->regmap, CS35L36_NG_CFG,
CS35L36_NG_AMP_EN_MASK, val);
return 0;
}
static const struct snd_kcontrol_new cs35l36_aud_controls[] = {
SOC_SINGLE_SX_TLV("Digital PCM Volume", CS35L36_AMP_DIG_VOL_CTRL,
3, 0x4D0, 0x390, dig_vol_tlv),
SOC_SINGLE_TLV("Analog PCM Volume", CS35L36_AMP_GAIN_CTRL, 5, 0x13, 0,
amp_gain_tlv),
SOC_ENUM("PCM Soft Ramp", pcm_sft_ramp),
SOC_SINGLE("Amp Gain Zero-Cross Switch", CS35L36_AMP_GAIN_CTRL,
CS35L36_AMP_ZC_SHIFT, 1, 0),
SOC_SINGLE("PDM LDM Enter Ramp Switch", CS35L36_DAC_MSM_CFG,
CS35L36_PDM_LDM_ENTER_SHIFT, 1, 0),
SOC_SINGLE("PDM LDM Exit Ramp Switch", CS35L36_DAC_MSM_CFG,
CS35L36_PDM_LDM_EXIT_SHIFT, 1, 0),
SOC_SINGLE_BOOL_EXT("LDM Select Switch", 0, cs35l36_ldm_sel_get,
cs35l36_ldm_sel_put),
};
static int cs35l36_main_amp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct cs35l36_private *cs35l36 =
snd_soc_component_get_drvdata(component);
u32 reg;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_update_bits(cs35l36->regmap, CS35L36_PWR_CTRL1,
CS35L36_GLOBAL_EN_MASK,
1 << CS35L36_GLOBAL_EN_SHIFT);
usleep_range(2000, 2100);
regmap_read(cs35l36->regmap, CS35L36_INT4_RAW_STATUS, ®);
if (WARN_ON_ONCE(reg & CS35L36_PLL_UNLOCK_MASK))
dev_crit(cs35l36->dev, "PLL Unlocked\n");
regmap_update_bits(cs35l36->regmap, CS35L36_ASP_RX1_SEL,
CS35L36_PCM_RX_SEL_MASK,
CS35L36_PCM_RX_SEL_PCM);
regmap_update_bits(cs35l36->regmap, CS35L36_AMP_OUT_MUTE,
CS35L36_AMP_MUTE_MASK,
0 << CS35L36_AMP_MUTE_SHIFT);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_update_bits(cs35l36->regmap, CS35L36_ASP_RX1_SEL,
CS35L36_PCM_RX_SEL_MASK,
CS35L36_PCM_RX_SEL_ZERO);
regmap_update_bits(cs35l36->regmap, CS35L36_AMP_OUT_MUTE,
CS35L36_AMP_MUTE_MASK,
1 << CS35L36_AMP_MUTE_SHIFT);
break;
case SND_SOC_DAPM_POST_PMD:
regmap_update_bits(cs35l36->regmap, CS35L36_PWR_CTRL1,
CS35L36_GLOBAL_EN_MASK,
0 << CS35L36_GLOBAL_EN_SHIFT);
usleep_range(2000, 2100);
break;
default:
dev_dbg(component->dev, "Invalid event = 0x%x\n", event);
return -EINVAL;
}
return 0;
}
static int cs35l36_boost_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct cs35l36_private *cs35l36 =
snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
if (!cs35l36->pdata.extern_boost)
regmap_update_bits(cs35l36->regmap, CS35L36_PWR_CTRL2,
CS35L36_BST_EN_MASK,
CS35L36_BST_EN <<
CS35L36_BST_EN_SHIFT);
break;
case SND_SOC_DAPM_POST_PMD:
if (!cs35l36->pdata.extern_boost)
regmap_update_bits(cs35l36->regmap, CS35L36_PWR_CTRL2,
CS35L36_BST_EN_MASK,
CS35L36_BST_DIS_VP <<
CS35L36_BST_EN_SHIFT);
break;
default:
dev_dbg(component->dev, "Invalid event = 0x%x\n", event);
return -EINVAL;
}
return 0;
}
static const char * const cs35l36_chan_text[] = {
"RX1",
"RX2",
};
static SOC_ENUM_SINGLE_DECL(chansel_enum, CS35L36_ASP_RX1_SLOT, 0,
cs35l36_chan_text);
static const struct snd_kcontrol_new cs35l36_chan_mux =
SOC_DAPM_ENUM("Input Mux", chansel_enum);
static const struct snd_kcontrol_new amp_enable_ctrl =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", CS35L36_AMP_OUT_MUTE,
CS35L36_AMP_MUTE_SHIFT, 1, 1);
static const struct snd_kcontrol_new boost_ctrl =
SOC_DAPM_SINGLE_VIRT("Switch", 1);
static const char * const asp_tx_src_text[] = {
"Zero Fill", "ASPRX1", "VMON", "IMON", "ERRVOL", "VPMON", "VBSTMON"
};
static const unsigned int asp_tx_src_values[] = {
0x00, 0x08, 0x18, 0x19, 0x20, 0x28, 0x29
};
static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx1_src_enum, CS35L36_ASP_TX1_SEL, 0,
CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
asp_tx_src_values);
static const struct snd_kcontrol_new asp_tx1_src =
SOC_DAPM_ENUM("ASPTX1SRC", asp_tx1_src_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx2_src_enum, CS35L36_ASP_TX2_SEL, 0,
CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
asp_tx_src_values);
static const struct snd_kcontrol_new asp_tx2_src =
SOC_DAPM_ENUM("ASPTX2SRC", asp_tx2_src_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx3_src_enum, CS35L36_ASP_TX3_SEL, 0,
CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
asp_tx_src_values);
static const struct snd_kcontrol_new asp_tx3_src =
SOC_DAPM_ENUM("ASPTX3SRC", asp_tx3_src_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx4_src_enum, CS35L36_ASP_TX4_SEL, 0,
CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
asp_tx_src_values);
static const struct snd_kcontrol_new asp_tx4_src =
SOC_DAPM_ENUM("ASPTX4SRC", asp_tx4_src_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx5_src_enum, CS35L36_ASP_TX5_SEL, 0,
CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
asp_tx_src_values);
static const struct snd_kcontrol_new asp_tx5_src =
SOC_DAPM_ENUM("ASPTX5SRC", asp_tx5_src_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx6_src_enum, CS35L36_ASP_TX6_SEL, 0,
CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
asp_tx_src_values);
static const struct snd_kcontrol_new asp_tx6_src =
SOC_DAPM_ENUM("ASPTX6SRC", asp_tx6_src_enum);
static const struct snd_soc_dapm_widget cs35l36_dapm_widgets[] = {
SND_SOC_DAPM_MUX("Channel Mux", SND_SOC_NOPM, 0, 0, &cs35l36_chan_mux),
SND_SOC_DAPM_AIF_IN("SDIN", NULL, 0, CS35L36_ASP_RX_TX_EN, 16, 0),
SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L36_PWR_CTRL2, 0, 0, NULL, 0,
cs35l36_main_amp_event, SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_OUTPUT("SPK"),
SND_SOC_DAPM_SWITCH("AMP Enable", SND_SOC_NOPM, 0, 1, &_enable_ctrl),
SND_SOC_DAPM_MIXER("CLASS H", CS35L36_PWR_CTRL3, 4, 0, NULL, 0),
SND_SOC_DAPM_SWITCH_E("BOOST Enable", SND_SOC_NOPM, 0, 0, &boost_ctrl,
cs35l36_boost_event, SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_AIF_OUT("ASPTX1", NULL, 0, CS35L36_ASP_RX_TX_EN, 0, 0),
SND_SOC_DAPM_AIF_OUT("ASPTX2", NULL, 1, CS35L36_ASP_RX_TX_EN, 1, 0),
SND_SOC_DAPM_AIF_OUT("ASPTX3", NULL, 2, CS35L36_ASP_RX_TX_EN, 2, 0),
SND_SOC_DAPM_AIF_OUT("ASPTX4", NULL, 3, CS35L36_ASP_RX_TX_EN, 3, 0),
SND_SOC_DAPM_AIF_OUT("ASPTX5", NULL, 4, CS35L36_ASP_RX_TX_EN, 4, 0),
SND_SOC_DAPM_AIF_OUT("ASPTX6", NULL, 5, CS35L36_ASP_RX_TX_EN, 5, 0),
SND_SOC_DAPM_MUX("ASPTX1SRC", SND_SOC_NOPM, 0, 0, &asp_tx1_src),
SND_SOC_DAPM_MUX("ASPTX2SRC", SND_SOC_NOPM, 0, 0, &asp_tx2_src),
SND_SOC_DAPM_MUX("ASPTX3SRC", SND_SOC_NOPM, 0, 0, &asp_tx3_src),
SND_SOC_DAPM_MUX("ASPTX4SRC", SND_SOC_NOPM, 0, 0, &asp_tx4_src),
SND_SOC_DAPM_MUX("ASPTX5SRC", SND_SOC_NOPM, 0, 0, &asp_tx5_src),
SND_SOC_DAPM_MUX("ASPTX6SRC", SND_SOC_NOPM, 0, 0, &asp_tx6_src),
SND_SOC_DAPM_ADC("VMON ADC", NULL, CS35L36_PWR_CTRL2, 12, 0),
SND_SOC_DAPM_ADC("IMON ADC", NULL, CS35L36_PWR_CTRL2, 13, 0),
SND_SOC_DAPM_ADC("VPMON ADC", NULL, CS35L36_PWR_CTRL2, 8, 0),
SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, CS35L36_PWR_CTRL2, 9, 0),
SND_SOC_DAPM_INPUT("VP"),
SND_SOC_DAPM_INPUT("VBST"),
SND_SOC_DAPM_INPUT("VSENSE"),
};
static const struct snd_soc_dapm_route cs35l36_audio_map[] = {
{"VPMON ADC", NULL, "VP"},
{"VBSTMON ADC", NULL, "VBST"},
{"IMON ADC", NULL, "VSENSE"},
{"VMON ADC", NULL, "VSENSE"},
{"ASPTX1SRC", "IMON", "IMON ADC"},
{"ASPTX1SRC", "VMON", "VMON ADC"},
{"ASPTX1SRC", "VBSTMON", "VBSTMON ADC"},
{"ASPTX1SRC", "VPMON", "VPMON ADC"},
{"ASPTX2SRC", "IMON", "IMON ADC"},
{"ASPTX2SRC", "VMON", "VMON ADC"},
{"ASPTX2SRC", "VBSTMON", "VBSTMON ADC"},
{"ASPTX2SRC", "VPMON", "VPMON ADC"},
{"ASPTX3SRC", "IMON", "IMON ADC"},
{"ASPTX3SRC", "VMON", "VMON ADC"},
{"ASPTX3SRC", "VBSTMON", "VBSTMON ADC"},
{"ASPTX3SRC", "VPMON", "VPMON ADC"},
{"ASPTX4SRC", "IMON", "IMON ADC"},
{"ASPTX4SRC", "VMON", "VMON ADC"},
{"ASPTX4SRC", "VBSTMON", "VBSTMON ADC"},
{"ASPTX4SRC", "VPMON", "VPMON ADC"},
{"ASPTX5SRC", "IMON", "IMON ADC"},
{"ASPTX5SRC", "VMON", "VMON ADC"},
{"ASPTX5SRC", "VBSTMON", "VBSTMON ADC"},
{"ASPTX5SRC", "VPMON", "VPMON ADC"},
{"ASPTX6SRC", "IMON", "IMON ADC"},
{"ASPTX6SRC", "VMON", "VMON ADC"},
{"ASPTX6SRC", "VBSTMON", "VBSTMON ADC"},
{"ASPTX6SRC", "VPMON", "VPMON ADC"},
{"ASPTX1", NULL, "ASPTX1SRC"},
{"ASPTX2", NULL, "ASPTX2SRC"},
{"ASPTX3", NULL, "ASPTX3SRC"},
{"ASPTX4", NULL, "ASPTX4SRC"},
{"ASPTX5", NULL, "ASPTX5SRC"},
{"ASPTX6", NULL, "ASPTX6SRC"},
{"AMP Capture", NULL, "ASPTX1"},
{"AMP Capture", NULL, "ASPTX2"},
{"AMP Capture", NULL, "ASPTX3"},
{"AMP Capture", NULL, "ASPTX4"},
{"AMP Capture", NULL, "ASPTX5"},
{"AMP Capture", NULL, "ASPTX6"},
{"AMP Enable", "Switch", "AMP Playback"},
{"SDIN", NULL, "AMP Enable"},
{"Channel Mux", "RX1", "SDIN"},
{"Channel Mux", "RX2", "SDIN"},
{"BOOST Enable", "Switch", "Channel Mux"},
{"CLASS H", NULL, "BOOST Enable"},
{"Main AMP", NULL, "Channel Mux"},
{"Main AMP", NULL, "CLASS H"},
{"SPK", NULL, "Main AMP"},
};
static int cs35l36_set_dai_fmt(struct snd_soc_dai *component_dai,
unsigned int fmt)
{
struct cs35l36_private *cs35l36 =
snd_soc_component_get_drvdata(component_dai->component);
unsigned int asp_fmt, lrclk_fmt, sclk_fmt, clock_provider, clk_frc;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
clock_provider = 1;
break;
case SND_SOC_DAIFMT_CBC_CFC:
clock_provider = 0;
break;
default:
return -EINVAL;
}
regmap_update_bits(cs35l36->regmap, CS35L36_ASP_TX_PIN_CTRL,
CS35L36_SCLK_MSTR_MASK,
clock_provider << CS35L36_SCLK_MSTR_SHIFT);
regmap_update_bits(cs35l36->regmap, CS35L36_ASP_RATE_CTRL,
CS35L36_LRCLK_MSTR_MASK,
clock_provider << CS35L36_LRCLK_MSTR_SHIFT);
switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) {
case SND_SOC_DAIFMT_CONT:
clk_frc = 1;
break;
case SND_SOC_DAIFMT_GATED:
clk_frc = 0;
break;
default:
return -EINVAL;
}
regmap_update_bits(cs35l36->regmap, CS35L36_ASP_TX_PIN_CTRL,
CS35L36_SCLK_FRC_MASK, clk_frc <<
CS35L36_SCLK_FRC_SHIFT);
regmap_update_bits(cs35l36->regmap, CS35L36_ASP_RATE_CTRL,
CS35L36_LRCLK_FRC_MASK, clk_frc <<
CS35L36_LRCLK_FRC_SHIFT);
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
asp_fmt = 0;
break;
case SND_SOC_DAIFMT_I2S:
asp_fmt = 2;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_IF:
lrclk_fmt = 1;
sclk_fmt = 0;
break;
case SND_SOC_DAIFMT_IB_NF:
lrclk_fmt = 0;
sclk_fmt = 1;
break;
case SND_SOC_DAIFMT_IB_IF:
lrclk_fmt = 1;
sclk_fmt = 1;
break;
case SND_SOC_DAIFMT_NB_NF:
lrclk_fmt = 0;
sclk_fmt = 0;
break;
default:
return -EINVAL;
}
regmap_update_bits(cs35l36->regmap, CS35L36_ASP_RATE_CTRL,
CS35L36_LRCLK_INV_MASK,
lrclk_fmt << CS35L36_LRCLK_INV_SHIFT);
regmap_update_bits(cs35l36->regmap, CS35L36_ASP_TX_PIN_CTRL,
CS35L36_SCLK_INV_MASK,
sclk_fmt << CS35L36_SCLK_INV_SHIFT);
regmap_update_bits(cs35l36->regmap, CS35L36_ASP_FORMAT,
CS35L36_ASP_FMT_MASK, asp_fmt);
return 0;
}
struct cs35l36_global_fs_config {
int rate;
int fs_cfg;
};
static const struct cs35l36_global_fs_config cs35l36_fs_rates[] = {
{12000, 0x01},
{24000, 0x02},
{48000, 0x03},
{96000, 0x04},
{192000, 0x05},
{384000, 0x06},
{11025, 0x09},
{22050, 0x0A},
{44100, 0x0B},
{88200, 0x0C},
{176400, 0x0D},
{8000, 0x11},
{16000, 0x12},
{32000, 0x13},
};
static int cs35l36_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct cs35l36_private *cs35l36 =
snd_soc_component_get_drvdata(dai->component);
unsigned int asp_width, global_fs = params_rate(params);
int i;
for (i = 0; i < ARRAY_SIZE(cs35l36_fs_rates); i++) {
if (global_fs == cs35l36_fs_rates[i].rate)
regmap_update_bits(cs35l36->regmap,
CS35L36_GLOBAL_CLK_CTRL,
CS35L36_GLOBAL_FS_MASK,
cs35l36_fs_rates[i].fs_cfg <<
CS35L36_GLOBAL_FS_SHIFT);
}
switch (params_width(params)) {
case 16:
asp_width = CS35L36_ASP_WIDTH_16;
break;
case 24:
asp_width = CS35L36_ASP_WIDTH_24;
break;
case 32:
asp_width = CS35L36_ASP_WIDTH_32;
break;
default:
return -EINVAL;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
regmap_update_bits(cs35l36->regmap, CS35L36_ASP_FRAME_CTRL,
CS35L36_ASP_RX_WIDTH_MASK,
asp_width << CS35L36_ASP_RX_WIDTH_SHIFT);
} else {
regmap_update_bits(cs35l36->regmap, CS35L36_ASP_FRAME_CTRL,
CS35L36_ASP_TX_WIDTH_MASK,
asp_width << CS35L36_ASP_TX_WIDTH_SHIFT);
}
return 0;
}
static int cs35l36_dai_set_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct cs35l36_private *cs35l36 =
snd_soc_component_get_drvdata(component);
int fs1, fs2;
if (freq > CS35L36_FS_NOM_6MHZ) {
fs1 = CS35L36_FS1_DEFAULT_VAL;
fs2 = CS35L36_FS2_DEFAULT_VAL;
} else {
fs1 = 3 * DIV_ROUND_UP(CS35L36_FS_NOM_6MHZ * 4, freq) + 4;
fs2 = 5 * DIV_ROUND_UP(CS35L36_FS_NOM_6MHZ * 4, freq) + 4;
}
regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
CS35L36_TEST_UNLOCK1);
regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
CS35L36_TEST_UNLOCK2);
regmap_update_bits(cs35l36->regmap, CS35L36_TST_FS_MON0,
CS35L36_FS1_WINDOW_MASK | CS35L36_FS2_WINDOW_MASK,
fs1 | (fs2 << CS35L36_FS2_WINDOW_SHIFT));
regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
CS35L36_TEST_LOCK1);
regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
CS35L36_TEST_LOCK2);
return 0;
}
static const struct cs35l36_pll_config *cs35l36_get_clk_config(
struct cs35l36_private *cs35l36, int freq)
{
int i;
for (i = 0; i < ARRAY_SIZE(cs35l36_pll_sysclk); i++) {
if (cs35l36_pll_sysclk[i].freq == freq)
return &cs35l36_pll_sysclk[i];
}
return NULL;
}
static const unsigned int cs35l36_src_rates[] = {
8000, 12000, 11025, 16000, 22050, 24000, 32000,
44100, 48000, 88200, 96000, 176400, 192000, 384000
};
static const struct snd_pcm_hw_constraint_list cs35l36_constraints = {
.count = ARRAY_SIZE(cs35l36_src_rates),
.list = cs35l36_src_rates,
};
static int cs35l36_pcm_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE, &cs35l36_constraints);
return 0;
}
static const struct snd_soc_dai_ops cs35l36_ops = {
.startup = cs35l36_pcm_startup,
.set_fmt = cs35l36_set_dai_fmt,
.hw_params = cs35l36_pcm_hw_params,
.set_sysclk = cs35l36_dai_set_sysclk,
};
static struct snd_soc_dai_driver cs35l36_dai[] = {
{
.name = "cs35l36-pcm",
.id = 0,
.playback = {
.stream_name = "AMP Playback",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = CS35L36_RX_FORMATS,
},
.capture = {
.stream_name = "AMP Capture",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = CS35L36_TX_FORMATS,
},
.ops = &cs35l36_ops,
.symmetric_rate = 1,
},
};
static int cs35l36_component_set_sysclk(struct snd_soc_component *component,
int clk_id, int source, unsigned int freq,
int dir)
{
struct cs35l36_private *cs35l36 =
snd_soc_component_get_drvdata(component);
const struct cs35l36_pll_config *clk_cfg;
int prev_clksrc;
bool pdm_switch;
prev_clksrc = cs35l36->clksrc;
switch (clk_id) {
case 0:
cs35l36->clksrc = CS35L36_PLLSRC_SCLK;
break;
case 1:
cs35l36->clksrc = CS35L36_PLLSRC_LRCLK;
break;
case 2:
cs35l36->clksrc = CS35L36_PLLSRC_PDMCLK;
break;
case 3:
cs35l36->clksrc = CS35L36_PLLSRC_SELF;
break;
case 4:
cs35l36->clksrc = CS35L36_PLLSRC_MCLK;
break;
default:
return -EINVAL;
}
clk_cfg = cs35l36_get_clk_config(cs35l36, freq);
if (clk_cfg == NULL) {
dev_err(component->dev, "Invalid CLK Config Freq: %d\n", freq);
return -EINVAL;
}
regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
CS35L36_PLL_OPENLOOP_MASK,
1 << CS35L36_PLL_OPENLOOP_SHIFT);
regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
CS35L36_REFCLK_FREQ_MASK,
clk_cfg->clk_cfg << CS35L36_REFCLK_FREQ_SHIFT);
regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
CS35L36_PLL_REFCLK_EN_MASK,
0 << CS35L36_PLL_REFCLK_EN_SHIFT);
regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
CS35L36_PLL_CLK_SEL_MASK,
cs35l36->clksrc);
regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
CS35L36_PLL_OPENLOOP_MASK,
0 << CS35L36_PLL_OPENLOOP_SHIFT);
regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
CS35L36_PLL_REFCLK_EN_MASK,
1 << CS35L36_PLL_REFCLK_EN_SHIFT);
if (cs35l36->rev_id == CS35L36_REV_A0) {
regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
CS35L36_TEST_UNLOCK1);
regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
CS35L36_TEST_UNLOCK2);
regmap_write(cs35l36->regmap, CS35L36_DCO_CTRL, 0x00036DA8);
regmap_write(cs35l36->regmap, CS35L36_MISC_CTRL, 0x0100EE0E);
regmap_update_bits(cs35l36->regmap, CS35L36_PLL_LOOP_PARAMS,
CS35L36_PLL_IGAIN_MASK,
CS35L36_PLL_IGAIN <<
CS35L36_PLL_IGAIN_SHIFT);
regmap_update_bits(cs35l36->regmap, CS35L36_PLL_LOOP_PARAMS,
CS35L36_PLL_FFL_IGAIN_MASK,
clk_cfg->fll_igain);
regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
CS35L36_TEST_LOCK1);
regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
CS35L36_TEST_LOCK2);
}
if (cs35l36->clksrc == CS35L36_PLLSRC_PDMCLK) {
pdm_switch = cs35l36->ldm_mode_sel &&
(prev_clksrc != CS35L36_PLLSRC_PDMCLK);
if (pdm_switch)
regmap_update_bits(cs35l36->regmap, CS35L36_NG_CFG,
CS35L36_NG_DELAY_MASK,
0 << CS35L36_NG_DELAY_SHIFT);
regmap_update_bits(cs35l36->regmap, CS35L36_DAC_MSM_CFG,
CS35L36_PDM_MODE_MASK,
1 << CS35L36_PDM_MODE_SHIFT);
if (pdm_switch)
regmap_update_bits(cs35l36->regmap, CS35L36_NG_CFG,
CS35L36_NG_DELAY_MASK,
3 << CS35L36_NG_DELAY_SHIFT);
} else {
pdm_switch = cs35l36->ldm_mode_sel &&
(prev_clksrc == CS35L36_PLLSRC_PDMCLK);
if (pdm_switch)
regmap_update_bits(cs35l36->regmap, CS35L36_NG_CFG,
CS35L36_NG_DELAY_MASK,
0 << CS35L36_NG_DELAY_SHIFT);
regmap_update_bits(cs35l36->regmap, CS35L36_DAC_MSM_CFG,
CS35L36_PDM_MODE_MASK,
0 << CS35L36_PDM_MODE_SHIFT);
if (pdm_switch)
regmap_update_bits(cs35l36->regmap, CS35L36_NG_CFG,
CS35L36_NG_DELAY_MASK,
3 << CS35L36_NG_DELAY_SHIFT);
}
return 0;
}
static int cs35l36_boost_inductor(struct cs35l36_private *cs35l36, int inductor)
{
regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_COEFF,
CS35L36_BSTCVRT_K1_MASK, 0x3C);
regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_COEFF,
CS35L36_BSTCVRT_K2_MASK,
0x3C << CS35L36_BSTCVRT_K2_SHIFT);
regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_SW_FREQ,
CS35L36_BSTCVRT_CCMFREQ_MASK, 0x00);
switch (inductor) {
case 1000: /* 1 uH */
regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_SLOPE_LBST,
CS35L36_BSTCVRT_SLOPE_MASK,
0x75 << CS35L36_BSTCVRT_SLOPE_SHIFT);
regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_SLOPE_LBST,
CS35L36_BSTCVRT_LBSTVAL_MASK, 0x00);
break;
case 1200: /* 1.2 uH */
regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_SLOPE_LBST,
CS35L36_BSTCVRT_SLOPE_MASK,
0x6B << CS35L36_BSTCVRT_SLOPE_SHIFT);
regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_SLOPE_LBST,
CS35L36_BSTCVRT_LBSTVAL_MASK, 0x01);
break;
default:
dev_err(cs35l36->dev, "%s Invalid Inductor Value %d uH\n",
__func__, inductor);
return -EINVAL;
}
return 0;
}
static int cs35l36_component_probe(struct snd_soc_component *component)
{
struct cs35l36_private *cs35l36 =
snd_soc_component_get_drvdata(component);
int ret;
if ((cs35l36->rev_id == CS35L36_REV_A0) && cs35l36->pdata.dcm_mode) {
regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_DCM_CTRL,
CS35L36_DCM_AUTO_MASK,
CS35L36_DCM_AUTO_MASK);
regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
CS35L36_TEST_UNLOCK1);
regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
CS35L36_TEST_UNLOCK2);
regmap_update_bits(cs35l36->regmap, CS35L36_BST_TST_MANUAL,
CS35L36_BST_MAN_IPKCOMP_MASK,
0 << CS35L36_BST_MAN_IPKCOMP_SHIFT);
regmap_update_bits(cs35l36->regmap, CS35L36_BST_TST_MANUAL,
CS35L36_BST_MAN_IPKCOMP_EN_MASK,
CS35L36_BST_MAN_IPKCOMP_EN_MASK);
regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
CS35L36_TEST_LOCK1);
regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
CS35L36_TEST_LOCK2);
}
if (cs35l36->pdata.amp_pcm_inv)
regmap_update_bits(cs35l36->regmap, CS35L36_AMP_DIG_VOL_CTRL,
CS35L36_AMP_PCM_INV_MASK,
CS35L36_AMP_PCM_INV_MASK);
if (cs35l36->pdata.multi_amp_mode)
regmap_update_bits(cs35l36->regmap, CS35L36_ASP_TX_PIN_CTRL,
CS35L36_ASP_TX_HIZ_MASK,
CS35L36_ASP_TX_HIZ_MASK);
if (cs35l36->pdata.imon_pol_inv)
regmap_update_bits(cs35l36->regmap, CS35L36_VI_SPKMON_FILT,
CS35L36_IMON_POL_MASK, 0);
if (cs35l36->pdata.vmon_pol_inv)
regmap_update_bits(cs35l36->regmap, CS35L36_VI_SPKMON_FILT,
CS35L36_VMON_POL_MASK, 0);
if (cs35l36->pdata.bst_vctl)
regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_VCTRL1,
CS35L35_BSTCVRT_CTL_MASK,
cs35l36->pdata.bst_vctl);
if (cs35l36->pdata.bst_vctl_sel)
regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_VCTRL2,
CS35L35_BSTCVRT_CTL_SEL_MASK,
cs35l36->pdata.bst_vctl_sel);
if (cs35l36->pdata.bst_ipk)
regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_PEAK_CUR,
CS35L36_BST_IPK_MASK,
cs35l36->pdata.bst_ipk);
if (cs35l36->pdata.boost_ind) {
ret = cs35l36_boost_inductor(cs35l36, cs35l36->pdata.boost_ind);
if (ret < 0) {
dev_err(cs35l36->dev,
"Boost inductor config failed(%d)\n", ret);
return ret;
}
}
if (cs35l36->pdata.temp_warn_thld)
regmap_update_bits(cs35l36->regmap, CS35L36_DTEMP_WARN_THLD,
CS35L36_TEMP_THLD_MASK,
cs35l36->pdata.temp_warn_thld);
if (cs35l36->pdata.irq_drv_sel)
regmap_update_bits(cs35l36->regmap, CS35L36_PAD_INTERFACE,
CS35L36_INT_DRV_SEL_MASK,
cs35l36->pdata.irq_drv_sel <<
CS35L36_INT_DRV_SEL_SHIFT);
if (cs35l36->pdata.irq_gpio_sel)
regmap_update_bits(cs35l36->regmap, CS35L36_PAD_INTERFACE,
CS35L36_INT_GPIO_SEL_MASK,
cs35l36->pdata.irq_gpio_sel <<
CS35L36_INT_GPIO_SEL_SHIFT);
/*
* Rev B0 has 2 versions
* L36 is 10V
* L37 is 12V
* If L36 we need to clamp some values for safety
* after probe has setup dt values. We want to make
* sure we dont miss any values set in probe
*/
if (cs35l36->chip_version == CS35L36_10V_L36) {
regmap_update_bits(cs35l36->regmap,
CS35L36_BSTCVRT_OVERVOLT_CTRL,
CS35L36_BST_OVP_THLD_MASK,
CS35L36_BST_OVP_THLD_11V);
regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
CS35L36_TEST_UNLOCK1);
regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
CS35L36_TEST_UNLOCK2);
regmap_update_bits(cs35l36->regmap, CS35L36_BST_ANA2_TEST,
CS35L36_BST_OVP_TRIM_MASK,
CS35L36_BST_OVP_TRIM_11V <<
CS35L36_BST_OVP_TRIM_SHIFT);
regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_VCTRL2,
CS35L36_BST_CTRL_LIM_MASK,
1 << CS35L36_BST_CTRL_LIM_SHIFT);
regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_VCTRL1,
CS35L35_BSTCVRT_CTL_MASK,
CS35L36_BST_CTRL_10V_CLAMP);
regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
CS35L36_TEST_LOCK1);
regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
CS35L36_TEST_LOCK2);
}
/*
* RevA and B require the disabling of
* SYNC_GLOBAL_OVR when GLOBAL_EN = 0.
* Just turn it off from default
*/
regmap_update_bits(cs35l36->regmap, CS35L36_CTRL_OVRRIDE,
CS35L36_SYNC_GLOBAL_OVR_MASK,
0 << CS35L36_SYNC_GLOBAL_OVR_SHIFT);
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_cs35l36 = {
.probe = &cs35l36_component_probe,
.set_sysclk = cs35l36_component_set_sysclk,
.dapm_widgets = cs35l36_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(cs35l36_dapm_widgets),
.dapm_routes = cs35l36_audio_map,
.num_dapm_routes = ARRAY_SIZE(cs35l36_audio_map),
.controls = cs35l36_aud_controls,
.num_controls = ARRAY_SIZE(cs35l36_aud_controls),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static struct regmap_config cs35l36_regmap = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = CS35L36_PAC_PMEM_WORD1023,
.reg_defaults = cs35l36_reg,
.num_reg_defaults = ARRAY_SIZE(cs35l36_reg),
.precious_reg = cs35l36_precious_reg,
.volatile_reg = cs35l36_volatile_reg,
.readable_reg = cs35l36_readable_reg,
.cache_type = REGCACHE_MAPLE,
};
static irqreturn_t cs35l36_irq(int irq, void *data)
{
struct cs35l36_private *cs35l36 = data;
unsigned int status[4];
unsigned int masks[4];
int ret = IRQ_NONE;
/* ack the irq by reading all status registers */
regmap_bulk_read(cs35l36->regmap, CS35L36_INT1_STATUS, status,
ARRAY_SIZE(status));
regmap_bulk_read(cs35l36->regmap, CS35L36_INT1_MASK, masks,
ARRAY_SIZE(masks));
/* Check to see if unmasked bits are active */
if (!(status[0] & ~masks[0]) && !(status[1] & ~masks[1]) &&
!(status[2] & ~masks[2]) && !(status[3] & ~masks[3])) {
return IRQ_NONE;
}
/*
* The following interrupts require a
* protection release cycle to get the
* speaker out of Safe-Mode.
*/
if (status[2] & CS35L36_AMP_SHORT_ERR) {
dev_crit(cs35l36->dev, "Amp short error\n");
regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
CS35L36_AMP_SHORT_ERR_RLS, 0);
regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
CS35L36_AMP_SHORT_ERR_RLS,
CS35L36_AMP_SHORT_ERR_RLS);
regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
CS35L36_AMP_SHORT_ERR_RLS, 0);
regmap_update_bits(cs35l36->regmap, CS35L36_INT3_STATUS,
CS35L36_AMP_SHORT_ERR,
CS35L36_AMP_SHORT_ERR);
ret = IRQ_HANDLED;
}
if (status[0] & CS35L36_TEMP_WARN) {
dev_crit(cs35l36->dev, "Over temperature warning\n");
regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
CS35L36_TEMP_WARN_ERR_RLS, 0);
regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
CS35L36_TEMP_WARN_ERR_RLS,
CS35L36_TEMP_WARN_ERR_RLS);
regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
CS35L36_TEMP_WARN_ERR_RLS, 0);
regmap_update_bits(cs35l36->regmap, CS35L36_INT1_STATUS,
CS35L36_TEMP_WARN, CS35L36_TEMP_WARN);
ret = IRQ_HANDLED;
}
if (status[0] & CS35L36_TEMP_ERR) {
dev_crit(cs35l36->dev, "Over temperature error\n");
regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
CS35L36_TEMP_ERR_RLS, 0);
regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
CS35L36_TEMP_ERR_RLS, CS35L36_TEMP_ERR_RLS);
regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
CS35L36_TEMP_ERR_RLS, 0);
regmap_update_bits(cs35l36->regmap, CS35L36_INT1_STATUS,
CS35L36_TEMP_ERR, CS35L36_TEMP_ERR);
ret = IRQ_HANDLED;
}
if (status[0] & CS35L36_BST_OVP_ERR) {
dev_crit(cs35l36->dev, "VBST Over Voltage error\n");
regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
CS35L36_TEMP_ERR_RLS, 0);
regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
CS35L36_TEMP_ERR_RLS, CS35L36_TEMP_ERR_RLS);
regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
CS35L36_TEMP_ERR_RLS, 0);
regmap_update_bits(cs35l36->regmap, CS35L36_INT1_STATUS,
CS35L36_BST_OVP_ERR, CS35L36_BST_OVP_ERR);
ret = IRQ_HANDLED;
}
if (status[0] & CS35L36_BST_DCM_UVP_ERR) {
dev_crit(cs35l36->dev, "DCM VBST Under Voltage Error\n");
regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
CS35L36_BST_UVP_ERR_RLS, 0);
regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
CS35L36_BST_UVP_ERR_RLS,
CS35L36_BST_UVP_ERR_RLS);
regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
CS35L36_BST_UVP_ERR_RLS, 0);
regmap_update_bits(cs35l36->regmap, CS35L36_INT1_STATUS,
CS35L36_BST_DCM_UVP_ERR,
CS35L36_BST_DCM_UVP_ERR);
ret = IRQ_HANDLED;
}
if (status[0] & CS35L36_BST_SHORT_ERR) {
dev_crit(cs35l36->dev, "LBST SHORT error!\n");
regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
CS35L36_BST_SHORT_ERR_RLS, 0);
regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
CS35L36_BST_SHORT_ERR_RLS,
CS35L36_BST_SHORT_ERR_RLS);
regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
CS35L36_BST_SHORT_ERR_RLS, 0);
regmap_update_bits(cs35l36->regmap, CS35L36_INT1_STATUS,
CS35L36_BST_SHORT_ERR,
CS35L36_BST_SHORT_ERR);
ret = IRQ_HANDLED;
}
return ret;
}
static int cs35l36_handle_of_data(struct i2c_client *i2c_client,
struct cs35l36_platform_data *pdata)
{
struct device_node *np = i2c_client->dev.of_node;
struct cs35l36_vpbr_cfg *vpbr_config = &pdata->vpbr_config;
struct device_node *vpbr_node;
unsigned int val;
int ret;
if (!np)
return 0;
ret = of_property_read_u32(np, "cirrus,boost-ctl-millivolt", &val);
if (!ret) {
if (val < 2550 || val > 12000) {
dev_err(&i2c_client->dev,
"Invalid Boost Voltage %d mV\n", val);
return -EINVAL;
}
pdata->bst_vctl = (((val - 2550) / 100) + 1) << 1;
} else {
dev_err(&i2c_client->dev,
"Unable to find required parameter 'cirrus,boost-ctl-millivolt'");
return -EINVAL;
}
ret = of_property_read_u32(np, "cirrus,boost-ctl-select", &val);
if (!ret)
pdata->bst_vctl_sel = val | CS35L36_VALID_PDATA;
ret = of_property_read_u32(np, "cirrus,boost-peak-milliamp", &val);
if (!ret) {
if (val < 1600 || val > 4500) {
dev_err(&i2c_client->dev,
"Invalid Boost Peak Current %u mA\n", val);
return -EINVAL;
}
pdata->bst_ipk = (val - 1600) / 50;
} else {
dev_err(&i2c_client->dev,
"Unable to find required parameter 'cirrus,boost-peak-milliamp'");
return -EINVAL;
}
pdata->multi_amp_mode = of_property_read_bool(np,
"cirrus,multi-amp-mode");
pdata->dcm_mode = of_property_read_bool(np,
"cirrus,dcm-mode-enable");
pdata->amp_pcm_inv = of_property_read_bool(np,
"cirrus,amp-pcm-inv");
pdata->imon_pol_inv = of_property_read_bool(np,
"cirrus,imon-pol-inv");
pdata->vmon_pol_inv = of_property_read_bool(np,
"cirrus,vmon-pol-inv");
if (of_property_read_u32(np, "cirrus,temp-warn-threshold", &val) >= 0)
pdata->temp_warn_thld = val | CS35L36_VALID_PDATA;
if (of_property_read_u32(np, "cirrus,boost-ind-nanohenry", &val) >= 0) {
pdata->boost_ind = val;
} else {
dev_err(&i2c_client->dev, "Inductor not specified.\n");
return -EINVAL;
}
if (of_property_read_u32(np, "cirrus,irq-drive-select", &val) >= 0)
pdata->irq_drv_sel = val | CS35L36_VALID_PDATA;
if (of_property_read_u32(np, "cirrus,irq-gpio-select", &val) >= 0)
pdata->irq_gpio_sel = val | CS35L36_VALID_PDATA;
/* VPBR Config */
vpbr_node = of_get_child_by_name(np, "cirrus,vpbr-config");
vpbr_config->is_present = vpbr_node ? true : false;
if (vpbr_config->is_present) {
if (of_property_read_u32(vpbr_node, "cirrus,vpbr-en",
&val) >= 0)
vpbr_config->vpbr_en = val;
if (of_property_read_u32(vpbr_node, "cirrus,vpbr-thld",
&val) >= 0)
vpbr_config->vpbr_thld = val;
if (of_property_read_u32(vpbr_node, "cirrus,vpbr-atk-rate",
&val) >= 0)
vpbr_config->vpbr_atk_rate = val;
if (of_property_read_u32(vpbr_node, "cirrus,vpbr-atk-vol",
&val) >= 0)
vpbr_config->vpbr_atk_vol = val;
if (of_property_read_u32(vpbr_node, "cirrus,vpbr-max-attn",
&val) >= 0)
vpbr_config->vpbr_max_attn = val;
if (of_property_read_u32(vpbr_node, "cirrus,vpbr-wait",
&val) >= 0)
vpbr_config->vpbr_wait = val;
if (of_property_read_u32(vpbr_node, "cirrus,vpbr-rel-rate",
&val) >= 0)
vpbr_config->vpbr_rel_rate = val;
if (of_property_read_u32(vpbr_node, "cirrus,vpbr-mute-en",
&val) >= 0)
vpbr_config->vpbr_mute_en = val;
}
of_node_put(vpbr_node);
return 0;
}
static int cs35l36_pac(struct cs35l36_private *cs35l36)
{
int ret, count;
unsigned int val;
if (cs35l36->rev_id != CS35L36_REV_B0)
return 0;
/*
* Magic code for internal PAC
*/
regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
CS35L36_TEST_UNLOCK1);
regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
CS35L36_TEST_UNLOCK2);
usleep_range(9500, 10500);
regmap_write(cs35l36->regmap, CS35L36_PAC_CTL1,
CS35L36_PAC_RESET);
regmap_write(cs35l36->regmap, CS35L36_PAC_CTL3,
CS35L36_PAC_MEM_ACCESS);
regmap_write(cs35l36->regmap, CS35L36_PAC_PMEM_WORD0,
CS35L36_B0_PAC_PATCH);
regmap_write(cs35l36->regmap, CS35L36_PAC_CTL3,
CS35L36_PAC_MEM_ACCESS_CLR);
regmap_write(cs35l36->regmap, CS35L36_PAC_CTL1,
CS35L36_PAC_ENABLE_MASK);
usleep_range(9500, 10500);
ret = regmap_read(cs35l36->regmap, CS35L36_INT4_STATUS, &val);
if (ret < 0) {
dev_err(cs35l36->dev, "Failed to read int4_status %d\n", ret);
return ret;
}
count = 0;
while (!(val & CS35L36_MCU_CONFIG_CLR)) {
usleep_range(100, 200);
count++;
ret = regmap_read(cs35l36->regmap, CS35L36_INT4_STATUS,
&val);
if (ret < 0) {
dev_err(cs35l36->dev, "Failed to read int4_status %d\n",
ret);
return ret;
}
if (count >= 100)
return -EINVAL;
}
regmap_write(cs35l36->regmap, CS35L36_INT4_STATUS,
CS35L36_MCU_CONFIG_CLR);
regmap_update_bits(cs35l36->regmap, CS35L36_PAC_CTL1,
CS35L36_PAC_ENABLE_MASK, 0);
regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
CS35L36_TEST_LOCK1);
regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
CS35L36_TEST_LOCK2);
return 0;
}
static void cs35l36_apply_vpbr_config(struct cs35l36_private *cs35l36)
{
struct cs35l36_platform_data *pdata = &cs35l36->pdata;
struct cs35l36_vpbr_cfg *vpbr_config = &pdata->vpbr_config;
regmap_update_bits(cs35l36->regmap, CS35L36_PWR_CTRL3,
CS35L36_VPBR_EN_MASK,
vpbr_config->vpbr_en <<
CS35L36_VPBR_EN_SHIFT);
regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
CS35L36_VPBR_THLD_MASK,
vpbr_config->vpbr_thld <<
CS35L36_VPBR_THLD_SHIFT);
regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
CS35L36_VPBR_MAX_ATTN_MASK,
vpbr_config->vpbr_max_attn <<
CS35L36_VPBR_MAX_ATTN_SHIFT);
regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
CS35L36_VPBR_ATK_VOL_MASK,
vpbr_config->vpbr_atk_vol <<
CS35L36_VPBR_ATK_VOL_SHIFT);
regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
CS35L36_VPBR_ATK_RATE_MASK,
vpbr_config->vpbr_atk_rate <<
CS35L36_VPBR_ATK_RATE_SHIFT);
regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
CS35L36_VPBR_WAIT_MASK,
vpbr_config->vpbr_wait <<
CS35L36_VPBR_WAIT_SHIFT);
regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
CS35L36_VPBR_REL_RATE_MASK,
vpbr_config->vpbr_rel_rate <<
CS35L36_VPBR_REL_RATE_SHIFT);
regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
CS35L36_VPBR_MUTE_EN_MASK,
vpbr_config->vpbr_mute_en <<
CS35L36_VPBR_MUTE_EN_SHIFT);
}
static const struct reg_sequence cs35l36_reva0_errata_patch[] = {
{ CS35L36_TESTKEY_CTRL, CS35L36_TEST_UNLOCK1 },
{ CS35L36_TESTKEY_CTRL, CS35L36_TEST_UNLOCK2 },
/* Errata Writes */
{ CS35L36_OTP_CTRL1, 0x00002060 },
{ CS35L36_OTP_CTRL2, 0x00000001 },
{ CS35L36_OTP_CTRL1, 0x00002460 },
{ CS35L36_OTP_CTRL2, 0x00000001 },
{ 0x00002088, 0x012A1838 },
{ 0x00003014, 0x0100EE0E },
{ 0x00003008, 0x0008184A },
{ 0x00007418, 0x509001C8 },
{ 0x00007064, 0x0929A800 },
{ 0x00002D10, 0x0002C01C },
{ 0x0000410C, 0x00000A11 },
{ 0x00006E08, 0x8B19140C },
{ 0x00006454, 0x0300000A },
{ CS35L36_AMP_NG_CTRL, 0x000020EF },
{ 0x00007E34, 0x0000000E },
{ 0x0000410C, 0x00000A11 },
{ 0x00007410, 0x20514B00 },
/* PAC Config */
{ CS35L36_CTRL_OVRRIDE, 0x00000000 },
{ CS35L36_PAC_INT0_CTRL, 0x00860001 },
{ CS35L36_PAC_INT1_CTRL, 0x00860001 },
{ CS35L36_PAC_INT2_CTRL, 0x00860001 },
{ CS35L36_PAC_INT3_CTRL, 0x00860001 },
{ CS35L36_PAC_INT4_CTRL, 0x00860001 },
{ CS35L36_PAC_INT5_CTRL, 0x00860001 },
{ CS35L36_PAC_INT6_CTRL, 0x00860001 },
{ CS35L36_PAC_INT7_CTRL, 0x00860001 },
{ CS35L36_PAC_INT_FLUSH_CTRL, 0x000000FF },
{ CS35L36_TESTKEY_CTRL, CS35L36_TEST_LOCK1 },
{ CS35L36_TESTKEY_CTRL, CS35L36_TEST_LOCK2 },
};
static const struct reg_sequence cs35l36_revb0_errata_patch[] = {
{ CS35L36_TESTKEY_CTRL, CS35L36_TEST_UNLOCK1 },
{ CS35L36_TESTKEY_CTRL, CS35L36_TEST_UNLOCK2 },
{ 0x00007064, 0x0929A800 },
{ 0x00007850, 0x00002FA9 },
{ 0x00007854, 0x0003F1D5 },
{ 0x00007858, 0x0003F5E3 },
{ 0x0000785C, 0x00001137 },
{ 0x00007860, 0x0001A7A5 },
{ 0x00007864, 0x0002F16A },
{ 0x00007868, 0x00003E21 },
{ 0x00007848, 0x00000001 },
{ 0x00003854, 0x05180240 },
{ 0x00007418, 0x509001C8 },
{ 0x0000394C, 0x028764BD },
{ CS35L36_TESTKEY_CTRL, CS35L36_TEST_LOCK1 },
{ CS35L36_TESTKEY_CTRL, CS35L36_TEST_LOCK2 },
};
static int cs35l36_i2c_probe(struct i2c_client *i2c_client)
{
struct cs35l36_private *cs35l36;
struct device *dev = &i2c_client->dev;
struct cs35l36_platform_data *pdata = dev_get_platdata(dev);
struct irq_data *irq_d;
int ret, irq_pol, chip_irq_pol, i;
u32 reg_id, reg_revid, l37_id_reg;
cs35l36 = devm_kzalloc(dev, sizeof(struct cs35l36_private), GFP_KERNEL);
if (!cs35l36)
return -ENOMEM;
cs35l36->dev = dev;
i2c_set_clientdata(i2c_client, cs35l36);
cs35l36->regmap = devm_regmap_init_i2c(i2c_client, &cs35l36_regmap);
if (IS_ERR(cs35l36->regmap)) {
ret = PTR_ERR(cs35l36->regmap);
dev_err(dev, "regmap_init() failed: %d\n", ret);
return ret;
}
cs35l36->num_supplies = ARRAY_SIZE(cs35l36_supplies);
for (i = 0; i < ARRAY_SIZE(cs35l36_supplies); i++)
cs35l36->supplies[i].supply = cs35l36_supplies[i];
ret = devm_regulator_bulk_get(dev, cs35l36->num_supplies,
cs35l36->supplies);
if (ret != 0) {
dev_err(dev, "Failed to request core supplies: %d\n", ret);
return ret;
}
if (pdata) {
cs35l36->pdata = *pdata;
} else {
pdata = devm_kzalloc(dev, sizeof(struct cs35l36_platform_data),
GFP_KERNEL);
if (!pdata)
return -ENOMEM;
if (i2c_client->dev.of_node) {
ret = cs35l36_handle_of_data(i2c_client, pdata);
if (ret != 0)
return ret;
}
cs35l36->pdata = *pdata;
}
ret = regulator_bulk_enable(cs35l36->num_supplies, cs35l36->supplies);
if (ret != 0) {
dev_err(dev, "Failed to enable core supplies: %d\n", ret);
return ret;
}
/* returning NULL can be an option if in stereo mode */
cs35l36->reset_gpio = devm_gpiod_get_optional(dev, "reset",
GPIOD_OUT_LOW);
if (IS_ERR(cs35l36->reset_gpio)) {
ret = PTR_ERR(cs35l36->reset_gpio);
cs35l36->reset_gpio = NULL;
if (ret == -EBUSY) {
dev_info(dev, "Reset line busy, assuming shared reset\n");
} else {
dev_err(dev, "Failed to get reset GPIO: %d\n", ret);
goto err_disable_regs;
}
}
if (cs35l36->reset_gpio)
gpiod_set_value_cansleep(cs35l36->reset_gpio, 1);
usleep_range(2000, 2100);
/* initialize amplifier */
ret = regmap_read(cs35l36->regmap, CS35L36_SW_RESET, ®_id);
if (ret < 0) {
dev_err(dev, "Get Device ID failed %d\n", ret);
goto err;
}
if (reg_id != CS35L36_CHIP_ID) {
dev_err(dev, "Device ID (%X). Expected ID %X\n", reg_id,
CS35L36_CHIP_ID);
ret = -ENODEV;
goto err;
}
ret = regmap_read(cs35l36->regmap, CS35L36_REV_ID, ®_revid);
if (ret < 0) {
dev_err(&i2c_client->dev, "Get Revision ID failed %d\n", ret);
goto err;
}
cs35l36->rev_id = reg_revid >> 8;
ret = regmap_read(cs35l36->regmap, CS35L36_OTP_MEM30, &l37_id_reg);
if (ret < 0) {
dev_err(&i2c_client->dev, "Failed to read otp_id Register %d\n",
ret);
goto err;
}
if ((l37_id_reg & CS35L36_OTP_REV_MASK) == CS35L36_OTP_REV_L37)
cs35l36->chip_version = CS35L36_12V_L37;
else
cs35l36->chip_version = CS35L36_10V_L36;
switch (cs35l36->rev_id) {
case CS35L36_REV_A0:
ret = regmap_register_patch(cs35l36->regmap,
cs35l36_reva0_errata_patch,
ARRAY_SIZE(cs35l36_reva0_errata_patch));
if (ret < 0) {
dev_err(dev, "Failed to apply A0 errata patch %d\n",
ret);
goto err;
}
break;
case CS35L36_REV_B0:
ret = cs35l36_pac(cs35l36);
if (ret < 0) {
dev_err(dev, "Failed to Trim OTP %d\n", ret);
goto err;
}
ret = regmap_register_patch(cs35l36->regmap,
cs35l36_revb0_errata_patch,
ARRAY_SIZE(cs35l36_revb0_errata_patch));
if (ret < 0) {
dev_err(dev, "Failed to apply B0 errata patch %d\n",
ret);
goto err;
}
break;
}
if (pdata->vpbr_config.is_present)
cs35l36_apply_vpbr_config(cs35l36);
irq_d = irq_get_irq_data(i2c_client->irq);
if (!irq_d) {
dev_err(&i2c_client->dev, "Invalid IRQ: %d\n", i2c_client->irq);
ret = -ENODEV;
goto err;
}
irq_pol = irqd_get_trigger_type(irq_d);
switch (irq_pol) {
case IRQF_TRIGGER_FALLING:
case IRQF_TRIGGER_LOW:
chip_irq_pol = 0;
break;
case IRQF_TRIGGER_RISING:
case IRQF_TRIGGER_HIGH:
chip_irq_pol = 1;
break;
default:
dev_err(cs35l36->dev, "Invalid IRQ polarity: %d\n", irq_pol);
ret = -EINVAL;
goto err;
}
regmap_update_bits(cs35l36->regmap, CS35L36_PAD_INTERFACE,
CS35L36_INT_POL_SEL_MASK,
chip_irq_pol << CS35L36_INT_POL_SEL_SHIFT);
ret = devm_request_threaded_irq(dev, i2c_client->irq, NULL, cs35l36_irq,
IRQF_ONESHOT | irq_pol, "cs35l36",
cs35l36);
if (ret != 0) {
dev_err(dev, "Failed to request IRQ: %d\n", ret);
goto err;
}
regmap_update_bits(cs35l36->regmap, CS35L36_PAD_INTERFACE,
CS35L36_INT_OUTPUT_EN_MASK, 1);
/* Set interrupt masks for critical errors */
regmap_write(cs35l36->regmap, CS35L36_INT1_MASK,
CS35L36_INT1_MASK_DEFAULT);
regmap_write(cs35l36->regmap, CS35L36_INT3_MASK,
CS35L36_INT3_MASK_DEFAULT);
dev_info(&i2c_client->dev, "Cirrus Logic CS35L%d, Revision: %02X\n",
cs35l36->chip_version, reg_revid >> 8);
ret = devm_snd_soc_register_component(dev, &soc_component_dev_cs35l36,
cs35l36_dai,
ARRAY_SIZE(cs35l36_dai));
if (ret < 0) {
dev_err(dev, "%s: Register component failed %d\n", __func__,
ret);
goto err;
}
return 0;
err:
gpiod_set_value_cansleep(cs35l36->reset_gpio, 0);
err_disable_regs:
regulator_bulk_disable(cs35l36->num_supplies, cs35l36->supplies);
return ret;
}
static void cs35l36_i2c_remove(struct i2c_client *client)
{
struct cs35l36_private *cs35l36 = i2c_get_clientdata(client);
/* Reset interrupt masks for device removal */
regmap_write(cs35l36->regmap, CS35L36_INT1_MASK,
CS35L36_INT1_MASK_RESET);
regmap_write(cs35l36->regmap, CS35L36_INT3_MASK,
CS35L36_INT3_MASK_RESET);
if (cs35l36->reset_gpio)
gpiod_set_value_cansleep(cs35l36->reset_gpio, 0);
regulator_bulk_disable(cs35l36->num_supplies, cs35l36->supplies);
}
static const struct of_device_id cs35l36_of_match[] = {
{.compatible = "cirrus,cs35l36"},
{},
};
MODULE_DEVICE_TABLE(of, cs35l36_of_match);
static const struct i2c_device_id cs35l36_id[] = {
{"cs35l36", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, cs35l36_id);
static struct i2c_driver cs35l36_i2c_driver = {
.driver = {
.name = "cs35l36",
.of_match_table = cs35l36_of_match,
},
.id_table = cs35l36_id,
.probe = cs35l36_i2c_probe,
.remove = cs35l36_i2c_remove,
};
module_i2c_driver(cs35l36_i2c_driver);
MODULE_DESCRIPTION("ASoC CS35L36 driver");
MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cs35l36.c |
/*
* Cirrus Logic CS42448/CS42888 Audio CODEC Digital Audio Interface (DAI) driver
*
* Copyright (C) 2014 Freescale Semiconductor, Inc.
*
* Author: Nicolin Chen <[email protected]>
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/gpio/consumer.h>
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include "cs42xx8.h"
#define CS42XX8_NUM_SUPPLIES 4
static const char *const cs42xx8_supply_names[CS42XX8_NUM_SUPPLIES] = {
"VA",
"VD",
"VLS",
"VLC",
};
#define CS42XX8_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE)
/* codec private data */
struct cs42xx8_priv {
struct regulator_bulk_data supplies[CS42XX8_NUM_SUPPLIES];
const struct cs42xx8_driver_data *drvdata;
struct regmap *regmap;
struct clk *clk;
bool slave_mode;
unsigned long sysclk;
u32 tx_channels;
struct gpio_desc *gpiod_reset;
u32 rate[2];
};
/* -127.5dB to 0dB with step of 0.5dB */
static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
/* -64dB to 24dB with step of 0.5dB */
static const DECLARE_TLV_DB_SCALE(adc_tlv, -6400, 50, 0);
static const char *const cs42xx8_adc_single[] = { "Differential", "Single-Ended" };
static const char *const cs42xx8_szc[] = { "Immediate Change", "Zero Cross",
"Soft Ramp", "Soft Ramp on Zero Cross" };
static const struct soc_enum adc1_single_enum =
SOC_ENUM_SINGLE(CS42XX8_ADCCTL, 4, 2, cs42xx8_adc_single);
static const struct soc_enum adc2_single_enum =
SOC_ENUM_SINGLE(CS42XX8_ADCCTL, 3, 2, cs42xx8_adc_single);
static const struct soc_enum adc3_single_enum =
SOC_ENUM_SINGLE(CS42XX8_ADCCTL, 2, 2, cs42xx8_adc_single);
static const struct soc_enum dac_szc_enum =
SOC_ENUM_SINGLE(CS42XX8_TXCTL, 5, 4, cs42xx8_szc);
static const struct soc_enum adc_szc_enum =
SOC_ENUM_SINGLE(CS42XX8_TXCTL, 0, 4, cs42xx8_szc);
static const struct snd_kcontrol_new cs42xx8_snd_controls[] = {
SOC_DOUBLE_R_TLV("DAC1 Playback Volume", CS42XX8_VOLAOUT1,
CS42XX8_VOLAOUT2, 0, 0xff, 1, dac_tlv),
SOC_DOUBLE_R_TLV("DAC2 Playback Volume", CS42XX8_VOLAOUT3,
CS42XX8_VOLAOUT4, 0, 0xff, 1, dac_tlv),
SOC_DOUBLE_R_TLV("DAC3 Playback Volume", CS42XX8_VOLAOUT5,
CS42XX8_VOLAOUT6, 0, 0xff, 1, dac_tlv),
SOC_DOUBLE_R_TLV("DAC4 Playback Volume", CS42XX8_VOLAOUT7,
CS42XX8_VOLAOUT8, 0, 0xff, 1, dac_tlv),
SOC_DOUBLE_R_S_TLV("ADC1 Capture Volume", CS42XX8_VOLAIN1,
CS42XX8_VOLAIN2, 0, -0x80, 0x30, 7, 0, adc_tlv),
SOC_DOUBLE_R_S_TLV("ADC2 Capture Volume", CS42XX8_VOLAIN3,
CS42XX8_VOLAIN4, 0, -0x80, 0x30, 7, 0, adc_tlv),
SOC_DOUBLE("DAC1 Invert Switch", CS42XX8_DACINV, 0, 1, 1, 0),
SOC_DOUBLE("DAC2 Invert Switch", CS42XX8_DACINV, 2, 3, 1, 0),
SOC_DOUBLE("DAC3 Invert Switch", CS42XX8_DACINV, 4, 5, 1, 0),
SOC_DOUBLE("DAC4 Invert Switch", CS42XX8_DACINV, 6, 7, 1, 0),
SOC_DOUBLE("ADC1 Invert Switch", CS42XX8_ADCINV, 0, 1, 1, 0),
SOC_DOUBLE("ADC2 Invert Switch", CS42XX8_ADCINV, 2, 3, 1, 0),
SOC_SINGLE("ADC High-Pass Filter Switch", CS42XX8_ADCCTL, 7, 1, 1),
SOC_SINGLE("DAC De-emphasis Switch", CS42XX8_ADCCTL, 5, 1, 0),
SOC_ENUM("ADC1 Single Ended Mode Switch", adc1_single_enum),
SOC_ENUM("ADC2 Single Ended Mode Switch", adc2_single_enum),
SOC_SINGLE("DAC Single Volume Control Switch", CS42XX8_TXCTL, 7, 1, 0),
SOC_ENUM("DAC Soft Ramp & Zero Cross Control Switch", dac_szc_enum),
SOC_SINGLE("DAC Auto Mute Switch", CS42XX8_TXCTL, 4, 1, 0),
SOC_SINGLE("Mute ADC Serial Port Switch", CS42XX8_TXCTL, 3, 1, 0),
SOC_SINGLE("ADC Single Volume Control Switch", CS42XX8_TXCTL, 2, 1, 0),
SOC_ENUM("ADC Soft Ramp & Zero Cross Control Switch", adc_szc_enum),
};
static const struct snd_kcontrol_new cs42xx8_adc3_snd_controls[] = {
SOC_DOUBLE_R_S_TLV("ADC3 Capture Volume", CS42XX8_VOLAIN5,
CS42XX8_VOLAIN6, 0, -0x80, 0x30, 7, 0, adc_tlv),
SOC_DOUBLE("ADC3 Invert Switch", CS42XX8_ADCINV, 4, 5, 1, 0),
SOC_ENUM("ADC3 Single Ended Mode Switch", adc3_single_enum),
};
static const struct snd_soc_dapm_widget cs42xx8_dapm_widgets[] = {
SND_SOC_DAPM_DAC("DAC1", "Playback", CS42XX8_PWRCTL, 1, 1),
SND_SOC_DAPM_DAC("DAC2", "Playback", CS42XX8_PWRCTL, 2, 1),
SND_SOC_DAPM_DAC("DAC3", "Playback", CS42XX8_PWRCTL, 3, 1),
SND_SOC_DAPM_DAC("DAC4", "Playback", CS42XX8_PWRCTL, 4, 1),
SND_SOC_DAPM_OUTPUT("AOUT1L"),
SND_SOC_DAPM_OUTPUT("AOUT1R"),
SND_SOC_DAPM_OUTPUT("AOUT2L"),
SND_SOC_DAPM_OUTPUT("AOUT2R"),
SND_SOC_DAPM_OUTPUT("AOUT3L"),
SND_SOC_DAPM_OUTPUT("AOUT3R"),
SND_SOC_DAPM_OUTPUT("AOUT4L"),
SND_SOC_DAPM_OUTPUT("AOUT4R"),
SND_SOC_DAPM_ADC("ADC1", "Capture", CS42XX8_PWRCTL, 5, 1),
SND_SOC_DAPM_ADC("ADC2", "Capture", CS42XX8_PWRCTL, 6, 1),
SND_SOC_DAPM_INPUT("AIN1L"),
SND_SOC_DAPM_INPUT("AIN1R"),
SND_SOC_DAPM_INPUT("AIN2L"),
SND_SOC_DAPM_INPUT("AIN2R"),
SND_SOC_DAPM_SUPPLY("PWR", CS42XX8_PWRCTL, 0, 1, NULL, 0),
};
static const struct snd_soc_dapm_widget cs42xx8_adc3_dapm_widgets[] = {
SND_SOC_DAPM_ADC("ADC3", "Capture", CS42XX8_PWRCTL, 7, 1),
SND_SOC_DAPM_INPUT("AIN3L"),
SND_SOC_DAPM_INPUT("AIN3R"),
};
static const struct snd_soc_dapm_route cs42xx8_dapm_routes[] = {
/* Playback */
{ "AOUT1L", NULL, "DAC1" },
{ "AOUT1R", NULL, "DAC1" },
{ "DAC1", NULL, "PWR" },
{ "AOUT2L", NULL, "DAC2" },
{ "AOUT2R", NULL, "DAC2" },
{ "DAC2", NULL, "PWR" },
{ "AOUT3L", NULL, "DAC3" },
{ "AOUT3R", NULL, "DAC3" },
{ "DAC3", NULL, "PWR" },
{ "AOUT4L", NULL, "DAC4" },
{ "AOUT4R", NULL, "DAC4" },
{ "DAC4", NULL, "PWR" },
/* Capture */
{ "ADC1", NULL, "AIN1L" },
{ "ADC1", NULL, "AIN1R" },
{ "ADC1", NULL, "PWR" },
{ "ADC2", NULL, "AIN2L" },
{ "ADC2", NULL, "AIN2R" },
{ "ADC2", NULL, "PWR" },
};
static const struct snd_soc_dapm_route cs42xx8_adc3_dapm_routes[] = {
/* Capture */
{ "ADC3", NULL, "AIN3L" },
{ "ADC3", NULL, "AIN3R" },
{ "ADC3", NULL, "PWR" },
};
struct cs42xx8_ratios {
unsigned int mfreq;
unsigned int min_mclk;
unsigned int max_mclk;
unsigned int ratio[3];
};
/*
* According to reference mannual, define the cs42xx8_ratio struct
* MFreq2 | MFreq1 | MFreq0 | Description | SSM | DSM | QSM |
* 0 | 0 | 0 |1.029MHz to 12.8MHz | 256 | 128 | 64 |
* 0 | 0 | 1 |1.536MHz to 19.2MHz | 384 | 192 | 96 |
* 0 | 1 | 0 |2.048MHz to 25.6MHz | 512 | 256 | 128 |
* 0 | 1 | 1 |3.072MHz to 38.4MHz | 768 | 384 | 192 |
* 1 | x | x |4.096MHz to 51.2MHz |1024 | 512 | 256 |
*/
static const struct cs42xx8_ratios cs42xx8_ratios[] = {
{ 0, 1029000, 12800000, {256, 128, 64} },
{ 2, 1536000, 19200000, {384, 192, 96} },
{ 4, 2048000, 25600000, {512, 256, 128} },
{ 6, 3072000, 38400000, {768, 384, 192} },
{ 8, 4096000, 51200000, {1024, 512, 256} },
};
static int cs42xx8_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct cs42xx8_priv *cs42xx8 = snd_soc_component_get_drvdata(component);
cs42xx8->sysclk = freq;
return 0;
}
static int cs42xx8_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int format)
{
struct snd_soc_component *component = codec_dai->component;
struct cs42xx8_priv *cs42xx8 = snd_soc_component_get_drvdata(component);
u32 val;
/* Set DAI format */
switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_LEFT_J:
val = CS42XX8_INTF_DAC_DIF_LEFTJ | CS42XX8_INTF_ADC_DIF_LEFTJ;
break;
case SND_SOC_DAIFMT_I2S:
val = CS42XX8_INTF_DAC_DIF_I2S | CS42XX8_INTF_ADC_DIF_I2S;
break;
case SND_SOC_DAIFMT_RIGHT_J:
val = CS42XX8_INTF_DAC_DIF_RIGHTJ | CS42XX8_INTF_ADC_DIF_RIGHTJ;
break;
case SND_SOC_DAIFMT_DSP_A:
val = CS42XX8_INTF_DAC_DIF_TDM | CS42XX8_INTF_ADC_DIF_TDM;
break;
default:
dev_err(component->dev, "unsupported dai format\n");
return -EINVAL;
}
regmap_update_bits(cs42xx8->regmap, CS42XX8_INTF,
CS42XX8_INTF_DAC_DIF_MASK |
CS42XX8_INTF_ADC_DIF_MASK, val);
/* Set master/slave audio interface */
switch (format & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
cs42xx8->slave_mode = true;
break;
case SND_SOC_DAIFMT_CBM_CFM:
cs42xx8->slave_mode = false;
break;
default:
dev_err(component->dev, "unsupported master/slave mode\n");
return -EINVAL;
}
return 0;
}
static int cs42xx8_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct cs42xx8_priv *cs42xx8 = snd_soc_component_get_drvdata(component);
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
u32 ratio[2];
u32 rate[2];
u32 fm[2];
u32 i, val, mask;
bool condition1, condition2;
if (tx)
cs42xx8->tx_channels = params_channels(params);
rate[tx] = params_rate(params);
rate[!tx] = cs42xx8->rate[!tx];
ratio[tx] = rate[tx] > 0 ? cs42xx8->sysclk / rate[tx] : 0;
ratio[!tx] = rate[!tx] > 0 ? cs42xx8->sysclk / rate[!tx] : 0;
/* Get functional mode for tx and rx according to rate */
for (i = 0; i < 2; i++) {
if (cs42xx8->slave_mode) {
fm[i] = CS42XX8_FM_AUTO;
} else {
if (rate[i] < 50000) {
fm[i] = CS42XX8_FM_SINGLE;
} else if (rate[i] > 50000 && rate[i] < 100000) {
fm[i] = CS42XX8_FM_DOUBLE;
} else if (rate[i] > 100000 && rate[i] < 200000) {
fm[i] = CS42XX8_FM_QUAD;
} else {
dev_err(component->dev,
"unsupported sample rate\n");
return -EINVAL;
}
}
}
for (i = 0; i < ARRAY_SIZE(cs42xx8_ratios); i++) {
/* Is the ratio[tx] valid ? */
condition1 = ((fm[tx] == CS42XX8_FM_AUTO) ?
(cs42xx8_ratios[i].ratio[0] == ratio[tx] ||
cs42xx8_ratios[i].ratio[1] == ratio[tx] ||
cs42xx8_ratios[i].ratio[2] == ratio[tx]) :
(cs42xx8_ratios[i].ratio[fm[tx]] == ratio[tx])) &&
cs42xx8->sysclk >= cs42xx8_ratios[i].min_mclk &&
cs42xx8->sysclk <= cs42xx8_ratios[i].max_mclk;
if (!ratio[tx])
condition1 = true;
/* Is the ratio[!tx] valid ? */
condition2 = ((fm[!tx] == CS42XX8_FM_AUTO) ?
(cs42xx8_ratios[i].ratio[0] == ratio[!tx] ||
cs42xx8_ratios[i].ratio[1] == ratio[!tx] ||
cs42xx8_ratios[i].ratio[2] == ratio[!tx]) :
(cs42xx8_ratios[i].ratio[fm[!tx]] == ratio[!tx]));
if (!ratio[!tx])
condition2 = true;
/*
* Both ratio[tx] and ratio[!tx] is valid, then we get
* a proper MFreq.
*/
if (condition1 && condition2)
break;
}
if (i == ARRAY_SIZE(cs42xx8_ratios)) {
dev_err(component->dev, "unsupported sysclk ratio\n");
return -EINVAL;
}
cs42xx8->rate[tx] = params_rate(params);
mask = CS42XX8_FUNCMOD_MFREQ_MASK;
val = cs42xx8_ratios[i].mfreq;
regmap_update_bits(cs42xx8->regmap, CS42XX8_FUNCMOD,
CS42XX8_FUNCMOD_xC_FM_MASK(tx) | mask,
CS42XX8_FUNCMOD_xC_FM(tx, fm[tx]) | val);
return 0;
}
static int cs42xx8_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct cs42xx8_priv *cs42xx8 = snd_soc_component_get_drvdata(component);
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
/* Clear stored rate */
cs42xx8->rate[tx] = 0;
regmap_update_bits(cs42xx8->regmap, CS42XX8_FUNCMOD,
CS42XX8_FUNCMOD_xC_FM_MASK(tx),
CS42XX8_FUNCMOD_xC_FM(tx, CS42XX8_FM_AUTO));
return 0;
}
static int cs42xx8_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
struct cs42xx8_priv *cs42xx8 = snd_soc_component_get_drvdata(component);
u8 dac_unmute = cs42xx8->tx_channels ?
~((0x1 << cs42xx8->tx_channels) - 1) : 0;
regmap_write(cs42xx8->regmap, CS42XX8_DACMUTE,
mute ? CS42XX8_DACMUTE_ALL : dac_unmute);
return 0;
}
static const struct snd_soc_dai_ops cs42xx8_dai_ops = {
.set_fmt = cs42xx8_set_dai_fmt,
.set_sysclk = cs42xx8_set_dai_sysclk,
.hw_params = cs42xx8_hw_params,
.hw_free = cs42xx8_hw_free,
.mute_stream = cs42xx8_mute,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver cs42xx8_dai = {
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = CS42XX8_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = CS42XX8_FORMATS,
},
.ops = &cs42xx8_dai_ops,
};
static const struct reg_default cs42xx8_reg[] = {
{ 0x02, 0x00 }, /* Power Control */
{ 0x03, 0xF0 }, /* Functional Mode */
{ 0x04, 0x46 }, /* Interface Formats */
{ 0x05, 0x00 }, /* ADC Control & DAC De-Emphasis */
{ 0x06, 0x10 }, /* Transition Control */
{ 0x07, 0x00 }, /* DAC Channel Mute */
{ 0x08, 0x00 }, /* Volume Control AOUT1 */
{ 0x09, 0x00 }, /* Volume Control AOUT2 */
{ 0x0a, 0x00 }, /* Volume Control AOUT3 */
{ 0x0b, 0x00 }, /* Volume Control AOUT4 */
{ 0x0c, 0x00 }, /* Volume Control AOUT5 */
{ 0x0d, 0x00 }, /* Volume Control AOUT6 */
{ 0x0e, 0x00 }, /* Volume Control AOUT7 */
{ 0x0f, 0x00 }, /* Volume Control AOUT8 */
{ 0x10, 0x00 }, /* DAC Channel Invert */
{ 0x11, 0x00 }, /* Volume Control AIN1 */
{ 0x12, 0x00 }, /* Volume Control AIN2 */
{ 0x13, 0x00 }, /* Volume Control AIN3 */
{ 0x14, 0x00 }, /* Volume Control AIN4 */
{ 0x15, 0x00 }, /* Volume Control AIN5 */
{ 0x16, 0x00 }, /* Volume Control AIN6 */
{ 0x17, 0x00 }, /* ADC Channel Invert */
{ 0x18, 0x00 }, /* Status Control */
{ 0x1a, 0x00 }, /* Status Mask */
{ 0x1b, 0x00 }, /* MUTEC Pin Control */
};
static bool cs42xx8_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS42XX8_STATUS:
return true;
default:
return false;
}
}
static bool cs42xx8_writeable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS42XX8_CHIPID:
case CS42XX8_STATUS:
return false;
default:
return true;
}
}
const struct regmap_config cs42xx8_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = CS42XX8_LASTREG,
.reg_defaults = cs42xx8_reg,
.num_reg_defaults = ARRAY_SIZE(cs42xx8_reg),
.volatile_reg = cs42xx8_volatile_register,
.writeable_reg = cs42xx8_writeable_register,
.cache_type = REGCACHE_MAPLE,
};
EXPORT_SYMBOL_GPL(cs42xx8_regmap_config);
static int cs42xx8_component_probe(struct snd_soc_component *component)
{
struct cs42xx8_priv *cs42xx8 = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
switch (cs42xx8->drvdata->num_adcs) {
case 3:
snd_soc_add_component_controls(component, cs42xx8_adc3_snd_controls,
ARRAY_SIZE(cs42xx8_adc3_snd_controls));
snd_soc_dapm_new_controls(dapm, cs42xx8_adc3_dapm_widgets,
ARRAY_SIZE(cs42xx8_adc3_dapm_widgets));
snd_soc_dapm_add_routes(dapm, cs42xx8_adc3_dapm_routes,
ARRAY_SIZE(cs42xx8_adc3_dapm_routes));
break;
default:
break;
}
/* Mute all DAC channels */
regmap_write(cs42xx8->regmap, CS42XX8_DACMUTE, CS42XX8_DACMUTE_ALL);
return 0;
}
static const struct snd_soc_component_driver cs42xx8_driver = {
.probe = cs42xx8_component_probe,
.controls = cs42xx8_snd_controls,
.num_controls = ARRAY_SIZE(cs42xx8_snd_controls),
.dapm_widgets = cs42xx8_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(cs42xx8_dapm_widgets),
.dapm_routes = cs42xx8_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(cs42xx8_dapm_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
const struct cs42xx8_driver_data cs42448_data = {
.name = "cs42448",
.num_adcs = 3,
};
EXPORT_SYMBOL_GPL(cs42448_data);
const struct cs42xx8_driver_data cs42888_data = {
.name = "cs42888",
.num_adcs = 2,
};
EXPORT_SYMBOL_GPL(cs42888_data);
int cs42xx8_probe(struct device *dev, struct regmap *regmap, struct cs42xx8_driver_data *drvdata)
{
struct cs42xx8_priv *cs42xx8;
int ret, val, i;
if (IS_ERR(regmap)) {
ret = PTR_ERR(regmap);
dev_err(dev, "failed to allocate regmap: %d\n", ret);
return ret;
}
cs42xx8 = devm_kzalloc(dev, sizeof(*cs42xx8), GFP_KERNEL);
if (cs42xx8 == NULL)
return -ENOMEM;
dev_set_drvdata(dev, cs42xx8);
cs42xx8->regmap = regmap;
cs42xx8->drvdata = drvdata;
cs42xx8->gpiod_reset = devm_gpiod_get_optional(dev, "reset",
GPIOD_OUT_HIGH);
if (IS_ERR(cs42xx8->gpiod_reset))
return PTR_ERR(cs42xx8->gpiod_reset);
gpiod_set_value_cansleep(cs42xx8->gpiod_reset, 0);
cs42xx8->clk = devm_clk_get(dev, "mclk");
if (IS_ERR(cs42xx8->clk)) {
dev_err(dev, "failed to get the clock: %ld\n",
PTR_ERR(cs42xx8->clk));
return -EINVAL;
}
cs42xx8->sysclk = clk_get_rate(cs42xx8->clk);
for (i = 0; i < ARRAY_SIZE(cs42xx8->supplies); i++)
cs42xx8->supplies[i].supply = cs42xx8_supply_names[i];
ret = devm_regulator_bulk_get(dev,
ARRAY_SIZE(cs42xx8->supplies), cs42xx8->supplies);
if (ret) {
dev_err(dev, "failed to request supplies: %d\n", ret);
return ret;
}
ret = regulator_bulk_enable(ARRAY_SIZE(cs42xx8->supplies),
cs42xx8->supplies);
if (ret) {
dev_err(dev, "failed to enable supplies: %d\n", ret);
return ret;
}
/* Make sure hardware reset done */
msleep(5);
/* Validate the chip ID */
ret = regmap_read(cs42xx8->regmap, CS42XX8_CHIPID, &val);
if (ret < 0) {
dev_err(dev, "failed to get device ID, ret = %d", ret);
goto err_enable;
}
/* The top four bits of the chip ID should be 0000 */
if (((val & CS42XX8_CHIPID_CHIP_ID_MASK) >> 4) != 0x00) {
dev_err(dev, "unmatched chip ID: %d\n",
(val & CS42XX8_CHIPID_CHIP_ID_MASK) >> 4);
ret = -EINVAL;
goto err_enable;
}
dev_info(dev, "found device, revision %X\n",
val & CS42XX8_CHIPID_REV_ID_MASK);
cs42xx8_dai.name = cs42xx8->drvdata->name;
/* Each adc supports stereo input */
cs42xx8_dai.capture.channels_max = cs42xx8->drvdata->num_adcs * 2;
ret = devm_snd_soc_register_component(dev, &cs42xx8_driver, &cs42xx8_dai, 1);
if (ret) {
dev_err(dev, "failed to register component:%d\n", ret);
goto err_enable;
}
regcache_cache_only(cs42xx8->regmap, true);
err_enable:
regulator_bulk_disable(ARRAY_SIZE(cs42xx8->supplies),
cs42xx8->supplies);
return ret;
}
EXPORT_SYMBOL_GPL(cs42xx8_probe);
#ifdef CONFIG_PM
static int cs42xx8_runtime_resume(struct device *dev)
{
struct cs42xx8_priv *cs42xx8 = dev_get_drvdata(dev);
int ret;
ret = clk_prepare_enable(cs42xx8->clk);
if (ret) {
dev_err(dev, "failed to enable mclk: %d\n", ret);
return ret;
}
gpiod_set_value_cansleep(cs42xx8->gpiod_reset, 0);
ret = regulator_bulk_enable(ARRAY_SIZE(cs42xx8->supplies),
cs42xx8->supplies);
if (ret) {
dev_err(dev, "failed to enable supplies: %d\n", ret);
goto err_clk;
}
/* Make sure hardware reset done */
msleep(5);
regcache_cache_only(cs42xx8->regmap, false);
regcache_mark_dirty(cs42xx8->regmap);
ret = regcache_sync(cs42xx8->regmap);
if (ret) {
dev_err(dev, "failed to sync regmap: %d\n", ret);
goto err_bulk;
}
return 0;
err_bulk:
regulator_bulk_disable(ARRAY_SIZE(cs42xx8->supplies),
cs42xx8->supplies);
err_clk:
clk_disable_unprepare(cs42xx8->clk);
return ret;
}
static int cs42xx8_runtime_suspend(struct device *dev)
{
struct cs42xx8_priv *cs42xx8 = dev_get_drvdata(dev);
regcache_cache_only(cs42xx8->regmap, true);
regulator_bulk_disable(ARRAY_SIZE(cs42xx8->supplies),
cs42xx8->supplies);
gpiod_set_value_cansleep(cs42xx8->gpiod_reset, 1);
clk_disable_unprepare(cs42xx8->clk);
return 0;
}
#endif
const struct dev_pm_ops cs42xx8_pm = {
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
SET_RUNTIME_PM_OPS(cs42xx8_runtime_suspend, cs42xx8_runtime_resume, NULL)
};
EXPORT_SYMBOL_GPL(cs42xx8_pm);
MODULE_DESCRIPTION("Cirrus Logic CS42448/CS42888 ALSA SoC Codec Driver");
MODULE_AUTHOR("Freescale Semiconductor, Inc.");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cs42xx8.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* alc5623.c -- alc562[123] ALSA Soc Audio driver
*
* Copyright 2008 Realtek Microelectronics
* Author: flove <[email protected]> Ethan <[email protected]>
*
* Copyright 2010 Arnaud Patard <[email protected]>
*
* Based on WM8753.c
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/tlv.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/alc5623.h>
#include "alc5623.h"
static int caps_charge = 2000;
module_param(caps_charge, int, 0);
MODULE_PARM_DESC(caps_charge, "ALC5623 cap charge time (msecs)");
/* codec private data */
struct alc5623_priv {
struct regmap *regmap;
u8 id;
unsigned int sysclk;
unsigned int add_ctrl;
unsigned int jack_det_ctrl;
};
static inline int alc5623_reset(struct snd_soc_component *component)
{
return snd_soc_component_write(component, ALC5623_RESET, 0);
}
static int amp_mixer_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
/* to power-on/off class-d amp generators/speaker */
/* need to write to 'index-46h' register : */
/* so write index num (here 0x46) to reg 0x6a */
/* and then 0xffff/0 to reg 0x6c */
snd_soc_component_write(component, ALC5623_HID_CTRL_INDEX, 0x46);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_component_write(component, ALC5623_HID_CTRL_DATA, 0xFFFF);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_write(component, ALC5623_HID_CTRL_DATA, 0);
break;
}
return 0;
}
/*
* ALC5623 Controls
*/
static const DECLARE_TLV_DB_SCALE(vol_tlv, -3450, 150, 0);
static const DECLARE_TLV_DB_SCALE(hp_tlv, -4650, 150, 0);
static const DECLARE_TLV_DB_SCALE(adc_rec_tlv, -1650, 150, 0);
static const DECLARE_TLV_DB_RANGE(boost_tlv,
0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0)
);
static const DECLARE_TLV_DB_SCALE(dig_tlv, 0, 600, 0);
static const struct snd_kcontrol_new alc5621_vol_snd_controls[] = {
SOC_DOUBLE_TLV("Speaker Playback Volume",
ALC5623_SPK_OUT_VOL, 8, 0, 31, 1, hp_tlv),
SOC_DOUBLE("Speaker Playback Switch",
ALC5623_SPK_OUT_VOL, 15, 7, 1, 1),
SOC_DOUBLE_TLV("Headphone Playback Volume",
ALC5623_HP_OUT_VOL, 8, 0, 31, 1, hp_tlv),
SOC_DOUBLE("Headphone Playback Switch",
ALC5623_HP_OUT_VOL, 15, 7, 1, 1),
};
static const struct snd_kcontrol_new alc5622_vol_snd_controls[] = {
SOC_DOUBLE_TLV("Speaker Playback Volume",
ALC5623_SPK_OUT_VOL, 8, 0, 31, 1, hp_tlv),
SOC_DOUBLE("Speaker Playback Switch",
ALC5623_SPK_OUT_VOL, 15, 7, 1, 1),
SOC_DOUBLE_TLV("Line Playback Volume",
ALC5623_HP_OUT_VOL, 8, 0, 31, 1, hp_tlv),
SOC_DOUBLE("Line Playback Switch",
ALC5623_HP_OUT_VOL, 15, 7, 1, 1),
};
static const struct snd_kcontrol_new alc5623_vol_snd_controls[] = {
SOC_DOUBLE_TLV("Line Playback Volume",
ALC5623_SPK_OUT_VOL, 8, 0, 31, 1, hp_tlv),
SOC_DOUBLE("Line Playback Switch",
ALC5623_SPK_OUT_VOL, 15, 7, 1, 1),
SOC_DOUBLE_TLV("Headphone Playback Volume",
ALC5623_HP_OUT_VOL, 8, 0, 31, 1, hp_tlv),
SOC_DOUBLE("Headphone Playback Switch",
ALC5623_HP_OUT_VOL, 15, 7, 1, 1),
};
static const struct snd_kcontrol_new alc5623_snd_controls[] = {
SOC_DOUBLE_TLV("Auxout Playback Volume",
ALC5623_MONO_AUX_OUT_VOL, 8, 0, 31, 1, hp_tlv),
SOC_DOUBLE("Auxout Playback Switch",
ALC5623_MONO_AUX_OUT_VOL, 15, 7, 1, 1),
SOC_DOUBLE_TLV("PCM Playback Volume",
ALC5623_STEREO_DAC_VOL, 8, 0, 31, 1, vol_tlv),
SOC_DOUBLE_TLV("AuxI Capture Volume",
ALC5623_AUXIN_VOL, 8, 0, 31, 1, vol_tlv),
SOC_DOUBLE_TLV("LineIn Capture Volume",
ALC5623_LINE_IN_VOL, 8, 0, 31, 1, vol_tlv),
SOC_SINGLE_TLV("Mic1 Capture Volume",
ALC5623_MIC_VOL, 8, 31, 1, vol_tlv),
SOC_SINGLE_TLV("Mic2 Capture Volume",
ALC5623_MIC_VOL, 0, 31, 1, vol_tlv),
SOC_DOUBLE_TLV("Rec Capture Volume",
ALC5623_ADC_REC_GAIN, 7, 0, 31, 0, adc_rec_tlv),
SOC_SINGLE_TLV("Mic 1 Boost Volume",
ALC5623_MIC_CTRL, 10, 2, 0, boost_tlv),
SOC_SINGLE_TLV("Mic 2 Boost Volume",
ALC5623_MIC_CTRL, 8, 2, 0, boost_tlv),
SOC_SINGLE_TLV("Digital Boost Volume",
ALC5623_ADD_CTRL_REG, 4, 3, 0, dig_tlv),
};
/*
* DAPM Controls
*/
static const struct snd_kcontrol_new alc5623_hp_mixer_controls[] = {
SOC_DAPM_SINGLE("LI2HP Playback Switch", ALC5623_LINE_IN_VOL, 15, 1, 1),
SOC_DAPM_SINGLE("AUXI2HP Playback Switch", ALC5623_AUXIN_VOL, 15, 1, 1),
SOC_DAPM_SINGLE("MIC12HP Playback Switch", ALC5623_MIC_ROUTING_CTRL, 15, 1, 1),
SOC_DAPM_SINGLE("MIC22HP Playback Switch", ALC5623_MIC_ROUTING_CTRL, 7, 1, 1),
SOC_DAPM_SINGLE("DAC2HP Playback Switch", ALC5623_STEREO_DAC_VOL, 15, 1, 1),
};
static const struct snd_kcontrol_new alc5623_hpl_mixer_controls[] = {
SOC_DAPM_SINGLE("ADC2HP_L Playback Switch", ALC5623_ADC_REC_GAIN, 15, 1, 1),
};
static const struct snd_kcontrol_new alc5623_hpr_mixer_controls[] = {
SOC_DAPM_SINGLE("ADC2HP_R Playback Switch", ALC5623_ADC_REC_GAIN, 14, 1, 1),
};
static const struct snd_kcontrol_new alc5623_mono_mixer_controls[] = {
SOC_DAPM_SINGLE("ADC2MONO_L Playback Switch", ALC5623_ADC_REC_GAIN, 13, 1, 1),
SOC_DAPM_SINGLE("ADC2MONO_R Playback Switch", ALC5623_ADC_REC_GAIN, 12, 1, 1),
SOC_DAPM_SINGLE("LI2MONO Playback Switch", ALC5623_LINE_IN_VOL, 13, 1, 1),
SOC_DAPM_SINGLE("AUXI2MONO Playback Switch", ALC5623_AUXIN_VOL, 13, 1, 1),
SOC_DAPM_SINGLE("MIC12MONO Playback Switch", ALC5623_MIC_ROUTING_CTRL, 13, 1, 1),
SOC_DAPM_SINGLE("MIC22MONO Playback Switch", ALC5623_MIC_ROUTING_CTRL, 5, 1, 1),
SOC_DAPM_SINGLE("DAC2MONO Playback Switch", ALC5623_STEREO_DAC_VOL, 13, 1, 1),
};
static const struct snd_kcontrol_new alc5623_speaker_mixer_controls[] = {
SOC_DAPM_SINGLE("LI2SPK Playback Switch", ALC5623_LINE_IN_VOL, 14, 1, 1),
SOC_DAPM_SINGLE("AUXI2SPK Playback Switch", ALC5623_AUXIN_VOL, 14, 1, 1),
SOC_DAPM_SINGLE("MIC12SPK Playback Switch", ALC5623_MIC_ROUTING_CTRL, 14, 1, 1),
SOC_DAPM_SINGLE("MIC22SPK Playback Switch", ALC5623_MIC_ROUTING_CTRL, 6, 1, 1),
SOC_DAPM_SINGLE("DAC2SPK Playback Switch", ALC5623_STEREO_DAC_VOL, 14, 1, 1),
};
/* Left Record Mixer */
static const struct snd_kcontrol_new alc5623_captureL_mixer_controls[] = {
SOC_DAPM_SINGLE("Mic1 Capture Switch", ALC5623_ADC_REC_MIXER, 14, 1, 1),
SOC_DAPM_SINGLE("Mic2 Capture Switch", ALC5623_ADC_REC_MIXER, 13, 1, 1),
SOC_DAPM_SINGLE("LineInL Capture Switch", ALC5623_ADC_REC_MIXER, 12, 1, 1),
SOC_DAPM_SINGLE("Left AuxI Capture Switch", ALC5623_ADC_REC_MIXER, 11, 1, 1),
SOC_DAPM_SINGLE("HPMixerL Capture Switch", ALC5623_ADC_REC_MIXER, 10, 1, 1),
SOC_DAPM_SINGLE("SPKMixer Capture Switch", ALC5623_ADC_REC_MIXER, 9, 1, 1),
SOC_DAPM_SINGLE("MonoMixer Capture Switch", ALC5623_ADC_REC_MIXER, 8, 1, 1),
};
/* Right Record Mixer */
static const struct snd_kcontrol_new alc5623_captureR_mixer_controls[] = {
SOC_DAPM_SINGLE("Mic1 Capture Switch", ALC5623_ADC_REC_MIXER, 6, 1, 1),
SOC_DAPM_SINGLE("Mic2 Capture Switch", ALC5623_ADC_REC_MIXER, 5, 1, 1),
SOC_DAPM_SINGLE("LineInR Capture Switch", ALC5623_ADC_REC_MIXER, 4, 1, 1),
SOC_DAPM_SINGLE("Right AuxI Capture Switch", ALC5623_ADC_REC_MIXER, 3, 1, 1),
SOC_DAPM_SINGLE("HPMixerR Capture Switch", ALC5623_ADC_REC_MIXER, 2, 1, 1),
SOC_DAPM_SINGLE("SPKMixer Capture Switch", ALC5623_ADC_REC_MIXER, 1, 1, 1),
SOC_DAPM_SINGLE("MonoMixer Capture Switch", ALC5623_ADC_REC_MIXER, 0, 1, 1),
};
static const char *alc5623_spk_n_sour_sel[] = {
"RN/-R", "RP/+R", "LN/-R", "Vmid" };
static const char *alc5623_hpl_out_input_sel[] = {
"Vmid", "HP Left Mix"};
static const char *alc5623_hpr_out_input_sel[] = {
"Vmid", "HP Right Mix"};
static const char *alc5623_spkout_input_sel[] = {
"Vmid", "HPOut Mix", "Speaker Mix", "Mono Mix"};
static const char *alc5623_aux_out_input_sel[] = {
"Vmid", "HPOut Mix", "Speaker Mix", "Mono Mix"};
/* auxout output mux */
static SOC_ENUM_SINGLE_DECL(alc5623_aux_out_input_enum,
ALC5623_OUTPUT_MIXER_CTRL, 6,
alc5623_aux_out_input_sel);
static const struct snd_kcontrol_new alc5623_auxout_mux_controls =
SOC_DAPM_ENUM("Route", alc5623_aux_out_input_enum);
/* speaker output mux */
static SOC_ENUM_SINGLE_DECL(alc5623_spkout_input_enum,
ALC5623_OUTPUT_MIXER_CTRL, 10,
alc5623_spkout_input_sel);
static const struct snd_kcontrol_new alc5623_spkout_mux_controls =
SOC_DAPM_ENUM("Route", alc5623_spkout_input_enum);
/* headphone left output mux */
static SOC_ENUM_SINGLE_DECL(alc5623_hpl_out_input_enum,
ALC5623_OUTPUT_MIXER_CTRL, 9,
alc5623_hpl_out_input_sel);
static const struct snd_kcontrol_new alc5623_hpl_out_mux_controls =
SOC_DAPM_ENUM("Route", alc5623_hpl_out_input_enum);
/* headphone right output mux */
static SOC_ENUM_SINGLE_DECL(alc5623_hpr_out_input_enum,
ALC5623_OUTPUT_MIXER_CTRL, 8,
alc5623_hpr_out_input_sel);
static const struct snd_kcontrol_new alc5623_hpr_out_mux_controls =
SOC_DAPM_ENUM("Route", alc5623_hpr_out_input_enum);
/* speaker output N select */
static SOC_ENUM_SINGLE_DECL(alc5623_spk_n_sour_enum,
ALC5623_OUTPUT_MIXER_CTRL, 14,
alc5623_spk_n_sour_sel);
static const struct snd_kcontrol_new alc5623_spkoutn_mux_controls =
SOC_DAPM_ENUM("Route", alc5623_spk_n_sour_enum);
static const struct snd_soc_dapm_widget alc5623_dapm_widgets[] = {
/* Muxes */
SND_SOC_DAPM_MUX("AuxOut Mux", SND_SOC_NOPM, 0, 0,
&alc5623_auxout_mux_controls),
SND_SOC_DAPM_MUX("SpeakerOut Mux", SND_SOC_NOPM, 0, 0,
&alc5623_spkout_mux_controls),
SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0,
&alc5623_hpl_out_mux_controls),
SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0,
&alc5623_hpr_out_mux_controls),
SND_SOC_DAPM_MUX("SpeakerOut N Mux", SND_SOC_NOPM, 0, 0,
&alc5623_spkoutn_mux_controls),
/* output mixers */
SND_SOC_DAPM_MIXER("HP Mix", SND_SOC_NOPM, 0, 0,
&alc5623_hp_mixer_controls[0],
ARRAY_SIZE(alc5623_hp_mixer_controls)),
SND_SOC_DAPM_MIXER("HPR Mix", ALC5623_PWR_MANAG_ADD2, 4, 0,
&alc5623_hpr_mixer_controls[0],
ARRAY_SIZE(alc5623_hpr_mixer_controls)),
SND_SOC_DAPM_MIXER("HPL Mix", ALC5623_PWR_MANAG_ADD2, 5, 0,
&alc5623_hpl_mixer_controls[0],
ARRAY_SIZE(alc5623_hpl_mixer_controls)),
SND_SOC_DAPM_MIXER("HPOut Mix", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Mono Mix", ALC5623_PWR_MANAG_ADD2, 2, 0,
&alc5623_mono_mixer_controls[0],
ARRAY_SIZE(alc5623_mono_mixer_controls)),
SND_SOC_DAPM_MIXER("Speaker Mix", ALC5623_PWR_MANAG_ADD2, 3, 0,
&alc5623_speaker_mixer_controls[0],
ARRAY_SIZE(alc5623_speaker_mixer_controls)),
/* input mixers */
SND_SOC_DAPM_MIXER("Left Capture Mix", ALC5623_PWR_MANAG_ADD2, 1, 0,
&alc5623_captureL_mixer_controls[0],
ARRAY_SIZE(alc5623_captureL_mixer_controls)),
SND_SOC_DAPM_MIXER("Right Capture Mix", ALC5623_PWR_MANAG_ADD2, 0, 0,
&alc5623_captureR_mixer_controls[0],
ARRAY_SIZE(alc5623_captureR_mixer_controls)),
SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback",
ALC5623_PWR_MANAG_ADD2, 9, 0),
SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback",
ALC5623_PWR_MANAG_ADD2, 8, 0),
SND_SOC_DAPM_MIXER("I2S Mix", ALC5623_PWR_MANAG_ADD1, 15, 0, NULL, 0),
SND_SOC_DAPM_MIXER("AuxI Mix", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Line Mix", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_ADC("Left ADC", "Left HiFi Capture",
ALC5623_PWR_MANAG_ADD2, 7, 0),
SND_SOC_DAPM_ADC("Right ADC", "Right HiFi Capture",
ALC5623_PWR_MANAG_ADD2, 6, 0),
SND_SOC_DAPM_PGA("Left Headphone", ALC5623_PWR_MANAG_ADD3, 10, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Headphone", ALC5623_PWR_MANAG_ADD3, 9, 0, NULL, 0),
SND_SOC_DAPM_PGA("SpeakerOut", ALC5623_PWR_MANAG_ADD3, 12, 0, NULL, 0),
SND_SOC_DAPM_PGA("Left AuxOut", ALC5623_PWR_MANAG_ADD3, 14, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right AuxOut", ALC5623_PWR_MANAG_ADD3, 13, 0, NULL, 0),
SND_SOC_DAPM_PGA("Left LineIn", ALC5623_PWR_MANAG_ADD3, 7, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right LineIn", ALC5623_PWR_MANAG_ADD3, 6, 0, NULL, 0),
SND_SOC_DAPM_PGA("Left AuxI", ALC5623_PWR_MANAG_ADD3, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right AuxI", ALC5623_PWR_MANAG_ADD3, 4, 0, NULL, 0),
SND_SOC_DAPM_PGA("MIC1 PGA", ALC5623_PWR_MANAG_ADD3, 3, 0, NULL, 0),
SND_SOC_DAPM_PGA("MIC2 PGA", ALC5623_PWR_MANAG_ADD3, 2, 0, NULL, 0),
SND_SOC_DAPM_PGA("MIC1 Pre Amp", ALC5623_PWR_MANAG_ADD3, 1, 0, NULL, 0),
SND_SOC_DAPM_PGA("MIC2 Pre Amp", ALC5623_PWR_MANAG_ADD3, 0, 0, NULL, 0),
SND_SOC_DAPM_MICBIAS("Mic Bias1", ALC5623_PWR_MANAG_ADD1, 11, 0),
SND_SOC_DAPM_OUTPUT("AUXOUTL"),
SND_SOC_DAPM_OUTPUT("AUXOUTR"),
SND_SOC_DAPM_OUTPUT("HPL"),
SND_SOC_DAPM_OUTPUT("HPR"),
SND_SOC_DAPM_OUTPUT("SPKOUT"),
SND_SOC_DAPM_OUTPUT("SPKOUTN"),
SND_SOC_DAPM_INPUT("LINEINL"),
SND_SOC_DAPM_INPUT("LINEINR"),
SND_SOC_DAPM_INPUT("AUXINL"),
SND_SOC_DAPM_INPUT("AUXINR"),
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_INPUT("MIC2"),
SND_SOC_DAPM_VMID("Vmid"),
};
static const char *alc5623_amp_names[] = {"AB Amp", "D Amp"};
static SOC_ENUM_SINGLE_DECL(alc5623_amp_enum,
ALC5623_OUTPUT_MIXER_CTRL, 13,
alc5623_amp_names);
static const struct snd_kcontrol_new alc5623_amp_mux_controls =
SOC_DAPM_ENUM("Route", alc5623_amp_enum);
static const struct snd_soc_dapm_widget alc5623_dapm_amp_widgets[] = {
SND_SOC_DAPM_PGA_E("D Amp", ALC5623_PWR_MANAG_ADD2, 14, 0, NULL, 0,
amp_mixer_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA("AB Amp", ALC5623_PWR_MANAG_ADD2, 15, 0, NULL, 0),
SND_SOC_DAPM_MUX("AB-D Amp Mux", SND_SOC_NOPM, 0, 0,
&alc5623_amp_mux_controls),
};
static const struct snd_soc_dapm_route intercon[] = {
/* virtual mixer - mixes left & right channels */
{"I2S Mix", NULL, "Left DAC"},
{"I2S Mix", NULL, "Right DAC"},
{"Line Mix", NULL, "Right LineIn"},
{"Line Mix", NULL, "Left LineIn"},
{"AuxI Mix", NULL, "Left AuxI"},
{"AuxI Mix", NULL, "Right AuxI"},
{"AUXOUTL", NULL, "Left AuxOut"},
{"AUXOUTR", NULL, "Right AuxOut"},
/* HP mixer */
{"HPL Mix", "ADC2HP_L Playback Switch", "Left Capture Mix"},
{"HPL Mix", NULL, "HP Mix"},
{"HPR Mix", "ADC2HP_R Playback Switch", "Right Capture Mix"},
{"HPR Mix", NULL, "HP Mix"},
{"HP Mix", "LI2HP Playback Switch", "Line Mix"},
{"HP Mix", "AUXI2HP Playback Switch", "AuxI Mix"},
{"HP Mix", "MIC12HP Playback Switch", "MIC1 PGA"},
{"HP Mix", "MIC22HP Playback Switch", "MIC2 PGA"},
{"HP Mix", "DAC2HP Playback Switch", "I2S Mix"},
/* speaker mixer */
{"Speaker Mix", "LI2SPK Playback Switch", "Line Mix"},
{"Speaker Mix", "AUXI2SPK Playback Switch", "AuxI Mix"},
{"Speaker Mix", "MIC12SPK Playback Switch", "MIC1 PGA"},
{"Speaker Mix", "MIC22SPK Playback Switch", "MIC2 PGA"},
{"Speaker Mix", "DAC2SPK Playback Switch", "I2S Mix"},
/* mono mixer */
{"Mono Mix", "ADC2MONO_L Playback Switch", "Left Capture Mix"},
{"Mono Mix", "ADC2MONO_R Playback Switch", "Right Capture Mix"},
{"Mono Mix", "LI2MONO Playback Switch", "Line Mix"},
{"Mono Mix", "AUXI2MONO Playback Switch", "AuxI Mix"},
{"Mono Mix", "MIC12MONO Playback Switch", "MIC1 PGA"},
{"Mono Mix", "MIC22MONO Playback Switch", "MIC2 PGA"},
{"Mono Mix", "DAC2MONO Playback Switch", "I2S Mix"},
/* Left record mixer */
{"Left Capture Mix", "LineInL Capture Switch", "LINEINL"},
{"Left Capture Mix", "Left AuxI Capture Switch", "AUXINL"},
{"Left Capture Mix", "Mic1 Capture Switch", "MIC1 Pre Amp"},
{"Left Capture Mix", "Mic2 Capture Switch", "MIC2 Pre Amp"},
{"Left Capture Mix", "HPMixerL Capture Switch", "HPL Mix"},
{"Left Capture Mix", "SPKMixer Capture Switch", "Speaker Mix"},
{"Left Capture Mix", "MonoMixer Capture Switch", "Mono Mix"},
/*Right record mixer */
{"Right Capture Mix", "LineInR Capture Switch", "LINEINR"},
{"Right Capture Mix", "Right AuxI Capture Switch", "AUXINR"},
{"Right Capture Mix", "Mic1 Capture Switch", "MIC1 Pre Amp"},
{"Right Capture Mix", "Mic2 Capture Switch", "MIC2 Pre Amp"},
{"Right Capture Mix", "HPMixerR Capture Switch", "HPR Mix"},
{"Right Capture Mix", "SPKMixer Capture Switch", "Speaker Mix"},
{"Right Capture Mix", "MonoMixer Capture Switch", "Mono Mix"},
/* headphone left mux */
{"Left Headphone Mux", "HP Left Mix", "HPL Mix"},
{"Left Headphone Mux", "Vmid", "Vmid"},
/* headphone right mux */
{"Right Headphone Mux", "HP Right Mix", "HPR Mix"},
{"Right Headphone Mux", "Vmid", "Vmid"},
/* speaker out mux */
{"SpeakerOut Mux", "Vmid", "Vmid"},
{"SpeakerOut Mux", "HPOut Mix", "HPOut Mix"},
{"SpeakerOut Mux", "Speaker Mix", "Speaker Mix"},
{"SpeakerOut Mux", "Mono Mix", "Mono Mix"},
/* Mono/Aux Out mux */
{"AuxOut Mux", "Vmid", "Vmid"},
{"AuxOut Mux", "HPOut Mix", "HPOut Mix"},
{"AuxOut Mux", "Speaker Mix", "Speaker Mix"},
{"AuxOut Mux", "Mono Mix", "Mono Mix"},
/* output pga */
{"HPL", NULL, "Left Headphone"},
{"Left Headphone", NULL, "Left Headphone Mux"},
{"HPR", NULL, "Right Headphone"},
{"Right Headphone", NULL, "Right Headphone Mux"},
{"Left AuxOut", NULL, "AuxOut Mux"},
{"Right AuxOut", NULL, "AuxOut Mux"},
/* input pga */
{"Left LineIn", NULL, "LINEINL"},
{"Right LineIn", NULL, "LINEINR"},
{"Left AuxI", NULL, "AUXINL"},
{"Right AuxI", NULL, "AUXINR"},
{"MIC1 Pre Amp", NULL, "MIC1"},
{"MIC2 Pre Amp", NULL, "MIC2"},
{"MIC1 PGA", NULL, "MIC1 Pre Amp"},
{"MIC2 PGA", NULL, "MIC2 Pre Amp"},
/* left ADC */
{"Left ADC", NULL, "Left Capture Mix"},
/* right ADC */
{"Right ADC", NULL, "Right Capture Mix"},
{"SpeakerOut N Mux", "RN/-R", "SpeakerOut"},
{"SpeakerOut N Mux", "RP/+R", "SpeakerOut"},
{"SpeakerOut N Mux", "LN/-R", "SpeakerOut"},
{"SpeakerOut N Mux", "Vmid", "Vmid"},
{"SPKOUT", NULL, "SpeakerOut"},
{"SPKOUTN", NULL, "SpeakerOut N Mux"},
};
static const struct snd_soc_dapm_route intercon_spk[] = {
{"SpeakerOut", NULL, "SpeakerOut Mux"},
};
static const struct snd_soc_dapm_route intercon_amp_spk[] = {
{"AB Amp", NULL, "SpeakerOut Mux"},
{"D Amp", NULL, "SpeakerOut Mux"},
{"AB-D Amp Mux", "AB Amp", "AB Amp"},
{"AB-D Amp Mux", "D Amp", "D Amp"},
{"SpeakerOut", NULL, "AB-D Amp Mux"},
};
/* PLL divisors */
struct _pll_div {
u32 pll_in;
u32 pll_out;
u16 regvalue;
};
/* Note : pll code from original alc5623 driver. Not sure of how good it is */
/* useful only for master mode */
static const struct _pll_div codec_master_pll_div[] = {
{ 2048000, 8192000, 0x0ea0},
{ 3686400, 8192000, 0x4e27},
{ 12000000, 8192000, 0x456b},
{ 13000000, 8192000, 0x495f},
{ 13100000, 8192000, 0x0320},
{ 2048000, 11289600, 0xf637},
{ 3686400, 11289600, 0x2f22},
{ 12000000, 11289600, 0x3e2f},
{ 13000000, 11289600, 0x4d5b},
{ 13100000, 11289600, 0x363b},
{ 2048000, 16384000, 0x1ea0},
{ 3686400, 16384000, 0x9e27},
{ 12000000, 16384000, 0x452b},
{ 13000000, 16384000, 0x542f},
{ 13100000, 16384000, 0x03a0},
{ 2048000, 16934400, 0xe625},
{ 3686400, 16934400, 0x9126},
{ 12000000, 16934400, 0x4d2c},
{ 13000000, 16934400, 0x742f},
{ 13100000, 16934400, 0x3c27},
{ 2048000, 22579200, 0x2aa0},
{ 3686400, 22579200, 0x2f20},
{ 12000000, 22579200, 0x7e2f},
{ 13000000, 22579200, 0x742f},
{ 13100000, 22579200, 0x3c27},
{ 2048000, 24576000, 0x2ea0},
{ 3686400, 24576000, 0xee27},
{ 12000000, 24576000, 0x2915},
{ 13000000, 24576000, 0x772e},
{ 13100000, 24576000, 0x0d20},
};
static const struct _pll_div codec_slave_pll_div[] = {
{ 1024000, 16384000, 0x3ea0},
{ 1411200, 22579200, 0x3ea0},
{ 1536000, 24576000, 0x3ea0},
{ 2048000, 16384000, 0x1ea0},
{ 2822400, 22579200, 0x1ea0},
{ 3072000, 24576000, 0x1ea0},
};
static int alc5623_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
int source, unsigned int freq_in, unsigned int freq_out)
{
int i;
struct snd_soc_component *component = codec_dai->component;
int gbl_clk = 0, pll_div = 0;
u16 reg;
if (pll_id < ALC5623_PLL_FR_MCLK || pll_id > ALC5623_PLL_FR_BCK)
return -ENODEV;
/* Disable PLL power */
snd_soc_component_update_bits(component, ALC5623_PWR_MANAG_ADD2,
ALC5623_PWR_ADD2_PLL,
0);
/* pll is not used in slave mode */
reg = snd_soc_component_read(component, ALC5623_DAI_CONTROL);
if (reg & ALC5623_DAI_SDP_SLAVE_MODE)
return 0;
if (!freq_in || !freq_out)
return 0;
switch (pll_id) {
case ALC5623_PLL_FR_MCLK:
for (i = 0; i < ARRAY_SIZE(codec_master_pll_div); i++) {
if (codec_master_pll_div[i].pll_in == freq_in
&& codec_master_pll_div[i].pll_out == freq_out) {
/* PLL source from MCLK */
pll_div = codec_master_pll_div[i].regvalue;
break;
}
}
break;
case ALC5623_PLL_FR_BCK:
for (i = 0; i < ARRAY_SIZE(codec_slave_pll_div); i++) {
if (codec_slave_pll_div[i].pll_in == freq_in
&& codec_slave_pll_div[i].pll_out == freq_out) {
/* PLL source from Bitclk */
gbl_clk = ALC5623_GBL_CLK_PLL_SOUR_SEL_BITCLK;
pll_div = codec_slave_pll_div[i].regvalue;
break;
}
}
break;
default:
return -EINVAL;
}
if (!pll_div)
return -EINVAL;
snd_soc_component_write(component, ALC5623_GLOBAL_CLK_CTRL_REG, gbl_clk);
snd_soc_component_write(component, ALC5623_PLL_CTRL, pll_div);
snd_soc_component_update_bits(component, ALC5623_PWR_MANAG_ADD2,
ALC5623_PWR_ADD2_PLL,
ALC5623_PWR_ADD2_PLL);
gbl_clk |= ALC5623_GBL_CLK_SYS_SOUR_SEL_PLL;
snd_soc_component_write(component, ALC5623_GLOBAL_CLK_CTRL_REG, gbl_clk);
return 0;
}
struct _coeff_div {
u16 fs;
u16 regvalue;
};
/* codec hifi mclk (after PLL) clock divider coefficients */
/* values inspired from column BCLK=32Fs of Appendix A table */
static const struct _coeff_div coeff_div[] = {
{256*8, 0x3a69},
{384*8, 0x3c6b},
{256*4, 0x2a69},
{384*4, 0x2c6b},
{256*2, 0x1a69},
{384*2, 0x1c6b},
{256*1, 0x0a69},
{384*1, 0x0c6b},
};
static int get_coeff(struct snd_soc_component *component, int rate)
{
struct alc5623_priv *alc5623 = snd_soc_component_get_drvdata(component);
int i;
for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
if (coeff_div[i].fs * rate == alc5623->sysclk)
return i;
}
return -EINVAL;
}
/*
* Clock after PLL and dividers
*/
static int alc5623_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct alc5623_priv *alc5623 = snd_soc_component_get_drvdata(component);
switch (freq) {
case 8192000:
case 11289600:
case 12288000:
case 16384000:
case 16934400:
case 18432000:
case 22579200:
case 24576000:
alc5623->sysclk = freq;
return 0;
}
return -EINVAL;
}
static int alc5623_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
u16 iface = 0;
/* set audio interface clocking */
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
iface = ALC5623_DAI_SDP_MASTER_MODE;
break;
case SND_SOC_DAIFMT_CBC_CFC:
iface = ALC5623_DAI_SDP_SLAVE_MODE;
break;
default:
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface |= ALC5623_DAI_I2S_DF_I2S;
break;
case SND_SOC_DAIFMT_RIGHT_J:
iface |= ALC5623_DAI_I2S_DF_RIGHT;
break;
case SND_SOC_DAIFMT_LEFT_J:
iface |= ALC5623_DAI_I2S_DF_LEFT;
break;
case SND_SOC_DAIFMT_DSP_A:
iface |= ALC5623_DAI_I2S_DF_PCM;
break;
case SND_SOC_DAIFMT_DSP_B:
iface |= ALC5623_DAI_I2S_DF_PCM | ALC5623_DAI_I2S_PCM_MODE;
break;
default:
return -EINVAL;
}
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
iface |= ALC5623_DAI_MAIN_I2S_BCLK_POL_CTRL;
break;
case SND_SOC_DAIFMT_IB_NF:
iface |= ALC5623_DAI_MAIN_I2S_BCLK_POL_CTRL;
break;
case SND_SOC_DAIFMT_NB_IF:
break;
default:
return -EINVAL;
}
return snd_soc_component_write(component, ALC5623_DAI_CONTROL, iface);
}
static int alc5623_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct alc5623_priv *alc5623 = snd_soc_component_get_drvdata(component);
int coeff, rate;
u16 iface;
iface = snd_soc_component_read(component, ALC5623_DAI_CONTROL);
iface &= ~ALC5623_DAI_I2S_DL_MASK;
/* bit size */
switch (params_width(params)) {
case 16:
iface |= ALC5623_DAI_I2S_DL_16;
break;
case 20:
iface |= ALC5623_DAI_I2S_DL_20;
break;
case 24:
iface |= ALC5623_DAI_I2S_DL_24;
break;
case 32:
iface |= ALC5623_DAI_I2S_DL_32;
break;
default:
return -EINVAL;
}
/* set iface & srate */
snd_soc_component_write(component, ALC5623_DAI_CONTROL, iface);
rate = params_rate(params);
coeff = get_coeff(component, rate);
if (coeff < 0)
return -EINVAL;
coeff = coeff_div[coeff].regvalue;
dev_dbg(component->dev, "%s: sysclk=%d,rate=%d,coeff=0x%04x\n",
__func__, alc5623->sysclk, rate, coeff);
snd_soc_component_write(component, ALC5623_STEREO_AD_DA_CLK_CTRL, coeff);
return 0;
}
static int alc5623_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
u16 hp_mute = ALC5623_MISC_M_DAC_L_INPUT | ALC5623_MISC_M_DAC_R_INPUT;
u16 mute_reg = snd_soc_component_read(component, ALC5623_MISC_CTRL) & ~hp_mute;
if (mute)
mute_reg |= hp_mute;
return snd_soc_component_write(component, ALC5623_MISC_CTRL, mute_reg);
}
#define ALC5623_ADD2_POWER_EN (ALC5623_PWR_ADD2_VREF \
| ALC5623_PWR_ADD2_DAC_REF_CIR)
#define ALC5623_ADD3_POWER_EN (ALC5623_PWR_ADD3_MAIN_BIAS \
| ALC5623_PWR_ADD3_MIC1_BOOST_AD)
#define ALC5623_ADD1_POWER_EN \
(ALC5623_PWR_ADD1_SHORT_CURR_DET_EN | ALC5623_PWR_ADD1_SOFTGEN_EN \
| ALC5623_PWR_ADD1_DEPOP_BUF_HP | ALC5623_PWR_ADD1_HP_OUT_AMP \
| ALC5623_PWR_ADD1_HP_OUT_ENH_AMP)
#define ALC5623_ADD1_POWER_EN_5622 \
(ALC5623_PWR_ADD1_SHORT_CURR_DET_EN \
| ALC5623_PWR_ADD1_HP_OUT_AMP)
static void enable_power_depop(struct snd_soc_component *component)
{
struct alc5623_priv *alc5623 = snd_soc_component_get_drvdata(component);
snd_soc_component_update_bits(component, ALC5623_PWR_MANAG_ADD1,
ALC5623_PWR_ADD1_SOFTGEN_EN,
ALC5623_PWR_ADD1_SOFTGEN_EN);
snd_soc_component_write(component, ALC5623_PWR_MANAG_ADD3, ALC5623_ADD3_POWER_EN);
snd_soc_component_update_bits(component, ALC5623_MISC_CTRL,
ALC5623_MISC_HP_DEPOP_MODE2_EN,
ALC5623_MISC_HP_DEPOP_MODE2_EN);
msleep(500);
snd_soc_component_write(component, ALC5623_PWR_MANAG_ADD2, ALC5623_ADD2_POWER_EN);
/* avoid writing '1' into 5622 reserved bits */
if (alc5623->id == 0x22)
snd_soc_component_write(component, ALC5623_PWR_MANAG_ADD1,
ALC5623_ADD1_POWER_EN_5622);
else
snd_soc_component_write(component, ALC5623_PWR_MANAG_ADD1,
ALC5623_ADD1_POWER_EN);
/* disable HP Depop2 */
snd_soc_component_update_bits(component, ALC5623_MISC_CTRL,
ALC5623_MISC_HP_DEPOP_MODE2_EN,
0);
}
static int alc5623_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
switch (level) {
case SND_SOC_BIAS_ON:
enable_power_depop(component);
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
/* everything off except vref/vmid, */
snd_soc_component_write(component, ALC5623_PWR_MANAG_ADD2,
ALC5623_PWR_ADD2_VREF);
snd_soc_component_write(component, ALC5623_PWR_MANAG_ADD3,
ALC5623_PWR_ADD3_MAIN_BIAS);
break;
case SND_SOC_BIAS_OFF:
/* everything off, dac mute, inactive */
snd_soc_component_write(component, ALC5623_PWR_MANAG_ADD2, 0);
snd_soc_component_write(component, ALC5623_PWR_MANAG_ADD3, 0);
snd_soc_component_write(component, ALC5623_PWR_MANAG_ADD1, 0);
break;
}
return 0;
}
#define ALC5623_FORMATS (SNDRV_PCM_FMTBIT_S16_LE \
| SNDRV_PCM_FMTBIT_S24_LE \
| SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops alc5623_dai_ops = {
.hw_params = alc5623_pcm_hw_params,
.mute_stream = alc5623_mute,
.set_fmt = alc5623_set_dai_fmt,
.set_sysclk = alc5623_set_dai_sysclk,
.set_pll = alc5623_set_dai_pll,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver alc5623_dai = {
.name = "alc5623-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 48000,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = ALC5623_FORMATS,},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 48000,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = ALC5623_FORMATS,},
.ops = &alc5623_dai_ops,
};
static int alc5623_suspend(struct snd_soc_component *component)
{
struct alc5623_priv *alc5623 = snd_soc_component_get_drvdata(component);
regcache_cache_only(alc5623->regmap, true);
return 0;
}
static int alc5623_resume(struct snd_soc_component *component)
{
struct alc5623_priv *alc5623 = snd_soc_component_get_drvdata(component);
int ret;
/* Sync reg_cache with the hardware */
regcache_cache_only(alc5623->regmap, false);
ret = regcache_sync(alc5623->regmap);
if (ret != 0) {
dev_err(component->dev, "Failed to sync register cache: %d\n",
ret);
regcache_cache_only(alc5623->regmap, true);
return ret;
}
return 0;
}
static int alc5623_probe(struct snd_soc_component *component)
{
struct alc5623_priv *alc5623 = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
alc5623_reset(component);
if (alc5623->add_ctrl) {
snd_soc_component_write(component, ALC5623_ADD_CTRL_REG,
alc5623->add_ctrl);
}
if (alc5623->jack_det_ctrl) {
snd_soc_component_write(component, ALC5623_JACK_DET_CTRL,
alc5623->jack_det_ctrl);
}
switch (alc5623->id) {
case 0x21:
snd_soc_add_component_controls(component, alc5621_vol_snd_controls,
ARRAY_SIZE(alc5621_vol_snd_controls));
break;
case 0x22:
snd_soc_add_component_controls(component, alc5622_vol_snd_controls,
ARRAY_SIZE(alc5622_vol_snd_controls));
break;
case 0x23:
snd_soc_add_component_controls(component, alc5623_vol_snd_controls,
ARRAY_SIZE(alc5623_vol_snd_controls));
break;
default:
return -EINVAL;
}
snd_soc_add_component_controls(component, alc5623_snd_controls,
ARRAY_SIZE(alc5623_snd_controls));
snd_soc_dapm_new_controls(dapm, alc5623_dapm_widgets,
ARRAY_SIZE(alc5623_dapm_widgets));
/* set up audio path interconnects */
snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
switch (alc5623->id) {
case 0x21:
case 0x22:
snd_soc_dapm_new_controls(dapm, alc5623_dapm_amp_widgets,
ARRAY_SIZE(alc5623_dapm_amp_widgets));
snd_soc_dapm_add_routes(dapm, intercon_amp_spk,
ARRAY_SIZE(intercon_amp_spk));
break;
case 0x23:
snd_soc_dapm_add_routes(dapm, intercon_spk,
ARRAY_SIZE(intercon_spk));
break;
default:
return -EINVAL;
}
return 0;
}
static const struct snd_soc_component_driver soc_component_device_alc5623 = {
.probe = alc5623_probe,
.suspend = alc5623_suspend,
.resume = alc5623_resume,
.set_bias_level = alc5623_set_bias_level,
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config alc5623_regmap = {
.reg_bits = 8,
.val_bits = 16,
.reg_stride = 2,
.max_register = ALC5623_VENDOR_ID2,
.cache_type = REGCACHE_RBTREE,
};
static const struct i2c_device_id alc5623_i2c_table[] = {
{"alc5621", 0x21},
{"alc5622", 0x22},
{"alc5623", 0x23},
{}
};
MODULE_DEVICE_TABLE(i2c, alc5623_i2c_table);
/*
* ALC5623 2 wire address is determined by A1 pin
* state during powerup.
* low = 0x1a
* high = 0x1b
*/
static int alc5623_i2c_probe(struct i2c_client *client)
{
struct alc5623_platform_data *pdata;
struct alc5623_priv *alc5623;
struct device_node *np;
unsigned int vid1, vid2;
int ret;
u32 val32;
const struct i2c_device_id *id;
alc5623 = devm_kzalloc(&client->dev, sizeof(struct alc5623_priv),
GFP_KERNEL);
if (alc5623 == NULL)
return -ENOMEM;
alc5623->regmap = devm_regmap_init_i2c(client, &alc5623_regmap);
if (IS_ERR(alc5623->regmap)) {
ret = PTR_ERR(alc5623->regmap);
dev_err(&client->dev, "Failed to initialise I/O: %d\n", ret);
return ret;
}
ret = regmap_read(alc5623->regmap, ALC5623_VENDOR_ID1, &vid1);
if (ret < 0) {
dev_err(&client->dev, "failed to read vendor ID1: %d\n", ret);
return ret;
}
ret = regmap_read(alc5623->regmap, ALC5623_VENDOR_ID2, &vid2);
if (ret < 0) {
dev_err(&client->dev, "failed to read vendor ID2: %d\n", ret);
return ret;
}
vid2 >>= 8;
id = i2c_match_id(alc5623_i2c_table, client);
if ((vid1 != 0x10ec) || (vid2 != id->driver_data)) {
dev_err(&client->dev, "unknown or wrong codec\n");
dev_err(&client->dev, "Expected %x:%lx, got %x:%x\n",
0x10ec, id->driver_data,
vid1, vid2);
return -ENODEV;
}
dev_dbg(&client->dev, "Found codec id : alc56%02x\n", vid2);
pdata = client->dev.platform_data;
if (pdata) {
alc5623->add_ctrl = pdata->add_ctrl;
alc5623->jack_det_ctrl = pdata->jack_det_ctrl;
} else {
if (client->dev.of_node) {
np = client->dev.of_node;
ret = of_property_read_u32(np, "add-ctrl", &val32);
if (!ret)
alc5623->add_ctrl = val32;
ret = of_property_read_u32(np, "jack-det-ctrl", &val32);
if (!ret)
alc5623->jack_det_ctrl = val32;
}
}
alc5623->id = vid2;
switch (alc5623->id) {
case 0x21:
alc5623_dai.name = "alc5621-hifi";
break;
case 0x22:
alc5623_dai.name = "alc5622-hifi";
break;
case 0x23:
alc5623_dai.name = "alc5623-hifi";
break;
default:
return -EINVAL;
}
i2c_set_clientdata(client, alc5623);
ret = devm_snd_soc_register_component(&client->dev,
&soc_component_device_alc5623, &alc5623_dai, 1);
if (ret != 0)
dev_err(&client->dev, "Failed to register codec: %d\n", ret);
return ret;
}
#ifdef CONFIG_OF
static const struct of_device_id alc5623_of_match[] = {
{ .compatible = "realtek,alc5623", },
{ }
};
MODULE_DEVICE_TABLE(of, alc5623_of_match);
#endif
/* i2c codec control layer */
static struct i2c_driver alc5623_i2c_driver = {
.driver = {
.name = "alc562x-codec",
.of_match_table = of_match_ptr(alc5623_of_match),
},
.probe = alc5623_i2c_probe,
.id_table = alc5623_i2c_table,
};
module_i2c_driver(alc5623_i2c_driver);
MODULE_DESCRIPTION("ASoC alc5621/2/3 driver");
MODULE_AUTHOR("Arnaud Patard <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/alc5623.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8350.c -- WM8350 ALSA SoC audio driver
*
* Copyright (C) 2007-12 Wolfson Microelectronics PLC.
*
* Author: Liam Girdwood <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/platform_device.h>
#include <linux/mfd/wm8350/audio.h>
#include <linux/mfd/wm8350/core.h>
#include <linux/regulator/consumer.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <trace/events/asoc.h>
#include "wm8350.h"
#define WM8350_OUTn_0dB 0x39
#define WM8350_RAMP_NONE 0
#define WM8350_RAMP_UP 1
#define WM8350_RAMP_DOWN 2
/* We only include the analogue supplies here; the digital supplies
* need to be available well before this driver can be probed.
*/
static const char *supply_names[] = {
"AVDD",
"HPVDD",
};
struct wm8350_output {
u16 active;
u16 left_vol;
u16 right_vol;
u16 ramp;
u16 mute;
};
struct wm8350_jack_data {
struct snd_soc_jack *jack;
struct delayed_work work;
int report;
int short_report;
};
struct wm8350_data {
struct wm8350 *wm8350;
struct wm8350_output out1;
struct wm8350_output out2;
struct wm8350_jack_data hpl;
struct wm8350_jack_data hpr;
struct wm8350_jack_data mic;
struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
int fll_freq_out;
int fll_freq_in;
struct delayed_work pga_work;
};
/*
* Ramp OUT1 PGA volume to minimise pops at stream startup and shutdown.
*/
static inline int wm8350_out1_ramp_step(struct wm8350_data *wm8350_data)
{
struct wm8350_output *out1 = &wm8350_data->out1;
struct wm8350 *wm8350 = wm8350_data->wm8350;
int left_complete = 0, right_complete = 0;
u16 reg, val;
/* left channel */
reg = wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME);
val = (reg & WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
if (out1->ramp == WM8350_RAMP_UP) {
/* ramp step up */
if (val < out1->left_vol) {
val++;
reg &= ~WM8350_OUT1L_VOL_MASK;
wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME,
reg | (val << WM8350_OUT1L_VOL_SHIFT));
} else
left_complete = 1;
} else if (out1->ramp == WM8350_RAMP_DOWN) {
/* ramp step down */
if (val > 0) {
val--;
reg &= ~WM8350_OUT1L_VOL_MASK;
wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME,
reg | (val << WM8350_OUT1L_VOL_SHIFT));
} else
left_complete = 1;
} else
return 1;
/* right channel */
reg = wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME);
val = (reg & WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
if (out1->ramp == WM8350_RAMP_UP) {
/* ramp step up */
if (val < out1->right_vol) {
val++;
reg &= ~WM8350_OUT1R_VOL_MASK;
wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME,
reg | (val << WM8350_OUT1R_VOL_SHIFT));
} else
right_complete = 1;
} else if (out1->ramp == WM8350_RAMP_DOWN) {
/* ramp step down */
if (val > 0) {
val--;
reg &= ~WM8350_OUT1R_VOL_MASK;
wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME,
reg | (val << WM8350_OUT1R_VOL_SHIFT));
} else
right_complete = 1;
}
/* only hit the update bit if either volume has changed this step */
if (!left_complete || !right_complete)
wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME, WM8350_OUT1_VU);
return left_complete & right_complete;
}
/*
* Ramp OUT2 PGA volume to minimise pops at stream startup and shutdown.
*/
static inline int wm8350_out2_ramp_step(struct wm8350_data *wm8350_data)
{
struct wm8350_output *out2 = &wm8350_data->out2;
struct wm8350 *wm8350 = wm8350_data->wm8350;
int left_complete = 0, right_complete = 0;
u16 reg, val;
/* left channel */
reg = wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME);
val = (reg & WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
if (out2->ramp == WM8350_RAMP_UP) {
/* ramp step up */
if (val < out2->left_vol) {
val++;
reg &= ~WM8350_OUT2L_VOL_MASK;
wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME,
reg | (val << WM8350_OUT1L_VOL_SHIFT));
} else
left_complete = 1;
} else if (out2->ramp == WM8350_RAMP_DOWN) {
/* ramp step down */
if (val > 0) {
val--;
reg &= ~WM8350_OUT2L_VOL_MASK;
wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME,
reg | (val << WM8350_OUT1L_VOL_SHIFT));
} else
left_complete = 1;
} else
return 1;
/* right channel */
reg = wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME);
val = (reg & WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
if (out2->ramp == WM8350_RAMP_UP) {
/* ramp step up */
if (val < out2->right_vol) {
val++;
reg &= ~WM8350_OUT2R_VOL_MASK;
wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME,
reg | (val << WM8350_OUT1R_VOL_SHIFT));
} else
right_complete = 1;
} else if (out2->ramp == WM8350_RAMP_DOWN) {
/* ramp step down */
if (val > 0) {
val--;
reg &= ~WM8350_OUT2R_VOL_MASK;
wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME,
reg | (val << WM8350_OUT1R_VOL_SHIFT));
} else
right_complete = 1;
}
/* only hit the update bit if either volume has changed this step */
if (!left_complete || !right_complete)
wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME, WM8350_OUT2_VU);
return left_complete & right_complete;
}
/*
* This work ramps both output PGAs at stream start/stop time to
* minimise pop associated with DAPM power switching.
* It's best to enable Zero Cross when ramping occurs to minimise any
* zipper noises.
*/
static void wm8350_pga_work(struct work_struct *work)
{
struct wm8350_data *wm8350_data =
container_of(work, struct wm8350_data, pga_work.work);
struct wm8350_output *out1 = &wm8350_data->out1,
*out2 = &wm8350_data->out2;
int i, out1_complete, out2_complete;
/* do we need to ramp at all ? */
if (out1->ramp == WM8350_RAMP_NONE && out2->ramp == WM8350_RAMP_NONE)
return;
/* PGA volumes have 6 bits of resolution to ramp */
for (i = 0; i <= 63; i++) {
out1_complete = 1;
out2_complete = 1;
if (out1->ramp != WM8350_RAMP_NONE)
out1_complete = wm8350_out1_ramp_step(wm8350_data);
if (out2->ramp != WM8350_RAMP_NONE)
out2_complete = wm8350_out2_ramp_step(wm8350_data);
/* ramp finished ? */
if (out1_complete && out2_complete)
break;
/* we need to delay longer on the up ramp */
if (out1->ramp == WM8350_RAMP_UP ||
out2->ramp == WM8350_RAMP_UP) {
/* delay is longer over 0dB as increases are larger */
if (i >= WM8350_OUTn_0dB)
schedule_timeout_interruptible(msecs_to_jiffies
(2));
else
schedule_timeout_interruptible(msecs_to_jiffies
(1));
} else
udelay(50); /* doesn't matter if we delay longer */
}
out1->ramp = WM8350_RAMP_NONE;
out2->ramp = WM8350_RAMP_NONE;
}
/*
* WM8350 Controls
*/
static int pga_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wm8350_data *wm8350_data = snd_soc_component_get_drvdata(component);
struct wm8350_output *out;
switch (w->shift) {
case 0:
case 1:
out = &wm8350_data->out1;
break;
case 2:
case 3:
out = &wm8350_data->out2;
break;
default:
WARN(1, "Invalid shift %d\n", w->shift);
return -1;
}
switch (event) {
case SND_SOC_DAPM_POST_PMU:
out->ramp = WM8350_RAMP_UP;
out->active = 1;
schedule_delayed_work(&wm8350_data->pga_work,
msecs_to_jiffies(1));
break;
case SND_SOC_DAPM_PRE_PMD:
out->ramp = WM8350_RAMP_DOWN;
out->active = 0;
schedule_delayed_work(&wm8350_data->pga_work,
msecs_to_jiffies(1));
break;
}
return 0;
}
static int wm8350_put_volsw_2r_vu(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8350_data *wm8350_priv = snd_soc_component_get_drvdata(component);
struct wm8350_output *out = NULL;
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
int ret;
unsigned int reg = mc->reg;
u16 val;
/* For OUT1 and OUT2 we shadow the values and only actually write
* them out when active in order to ensure the amplifier comes on
* as quietly as possible. */
switch (reg) {
case WM8350_LOUT1_VOLUME:
out = &wm8350_priv->out1;
break;
case WM8350_LOUT2_VOLUME:
out = &wm8350_priv->out2;
break;
default:
break;
}
if (out) {
out->left_vol = ucontrol->value.integer.value[0];
out->right_vol = ucontrol->value.integer.value[1];
if (!out->active)
return 1;
}
ret = snd_soc_put_volsw(kcontrol, ucontrol);
if (ret < 0)
return ret;
/* now hit the volume update bits (always bit 8) */
val = snd_soc_component_read(component, reg);
snd_soc_component_write(component, reg, val | WM8350_OUT1_VU);
return 1;
}
static int wm8350_get_volsw_2r(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8350_data *wm8350_priv = snd_soc_component_get_drvdata(component);
struct wm8350_output *out1 = &wm8350_priv->out1;
struct wm8350_output *out2 = &wm8350_priv->out2;
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
unsigned int reg = mc->reg;
/* If these are cached registers use the cache */
switch (reg) {
case WM8350_LOUT1_VOLUME:
ucontrol->value.integer.value[0] = out1->left_vol;
ucontrol->value.integer.value[1] = out1->right_vol;
return 0;
case WM8350_LOUT2_VOLUME:
ucontrol->value.integer.value[0] = out2->left_vol;
ucontrol->value.integer.value[1] = out2->right_vol;
return 0;
default:
break;
}
return snd_soc_get_volsw(kcontrol, ucontrol);
}
static const char *wm8350_deemp[] = { "None", "32kHz", "44.1kHz", "48kHz" };
static const char *wm8350_pol[] = { "Normal", "Inv R", "Inv L", "Inv L & R" };
static const char *wm8350_dacmutem[] = { "Normal", "Soft" };
static const char *wm8350_dacmutes[] = { "Fast", "Slow" };
static const char *wm8350_adcfilter[] = { "None", "High Pass" };
static const char *wm8350_adchp[] = { "44.1kHz", "8kHz", "16kHz", "32kHz" };
static const char *wm8350_lr[] = { "Left", "Right" };
static const struct soc_enum wm8350_enum[] = {
SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 4, 4, wm8350_deemp),
SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 0, 4, wm8350_pol),
SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 14, 2, wm8350_dacmutem),
SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 13, 2, wm8350_dacmutes),
SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 15, 2, wm8350_adcfilter),
SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 8, 4, wm8350_adchp),
SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 0, 4, wm8350_pol),
SOC_ENUM_SINGLE(WM8350_INPUT_MIXER_VOLUME, 15, 2, wm8350_lr),
};
static DECLARE_TLV_DB_SCALE(pre_amp_tlv, -1200, 3525, 0);
static DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 600, 0);
static DECLARE_TLV_DB_SCALE(dac_pcm_tlv, -7163, 36, 1);
static DECLARE_TLV_DB_SCALE(adc_pcm_tlv, -12700, 50, 1);
static DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 1);
static const DECLARE_TLV_DB_RANGE(capture_sd_tlv,
0, 12, TLV_DB_SCALE_ITEM(-3600, 300, 1),
13, 15, TLV_DB_SCALE_ITEM(0, 0, 0)
);
static const struct snd_kcontrol_new wm8350_snd_controls[] = {
SOC_ENUM("Playback Deemphasis", wm8350_enum[0]),
SOC_ENUM("Playback DAC Inversion", wm8350_enum[1]),
SOC_DOUBLE_R_EXT_TLV("Playback PCM Volume",
WM8350_DAC_DIGITAL_VOLUME_L,
WM8350_DAC_DIGITAL_VOLUME_R,
0, 255, 0, wm8350_get_volsw_2r,
wm8350_put_volsw_2r_vu, dac_pcm_tlv),
SOC_ENUM("Playback PCM Mute Function", wm8350_enum[2]),
SOC_ENUM("Playback PCM Mute Speed", wm8350_enum[3]),
SOC_ENUM("Capture PCM Filter", wm8350_enum[4]),
SOC_ENUM("Capture PCM HP Filter", wm8350_enum[5]),
SOC_ENUM("Capture ADC Inversion", wm8350_enum[6]),
SOC_DOUBLE_R_EXT_TLV("Capture PCM Volume",
WM8350_ADC_DIGITAL_VOLUME_L,
WM8350_ADC_DIGITAL_VOLUME_R,
0, 255, 0, wm8350_get_volsw_2r,
wm8350_put_volsw_2r_vu, adc_pcm_tlv),
SOC_DOUBLE_TLV("Capture Sidetone Volume",
WM8350_ADC_DIVIDER,
8, 4, 15, 1, capture_sd_tlv),
SOC_DOUBLE_R_EXT_TLV("Capture Volume",
WM8350_LEFT_INPUT_VOLUME,
WM8350_RIGHT_INPUT_VOLUME,
2, 63, 0, wm8350_get_volsw_2r,
wm8350_put_volsw_2r_vu, pre_amp_tlv),
SOC_DOUBLE_R("Capture ZC Switch",
WM8350_LEFT_INPUT_VOLUME,
WM8350_RIGHT_INPUT_VOLUME, 13, 1, 0),
SOC_SINGLE_TLV("Left Input Left Sidetone Volume",
WM8350_OUTPUT_LEFT_MIXER_VOLUME, 1, 7, 0, out_mix_tlv),
SOC_SINGLE_TLV("Left Input Right Sidetone Volume",
WM8350_OUTPUT_LEFT_MIXER_VOLUME,
5, 7, 0, out_mix_tlv),
SOC_SINGLE_TLV("Left Input Bypass Volume",
WM8350_OUTPUT_LEFT_MIXER_VOLUME,
9, 7, 0, out_mix_tlv),
SOC_SINGLE_TLV("Right Input Left Sidetone Volume",
WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
1, 7, 0, out_mix_tlv),
SOC_SINGLE_TLV("Right Input Right Sidetone Volume",
WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
5, 7, 0, out_mix_tlv),
SOC_SINGLE_TLV("Right Input Bypass Volume",
WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
13, 7, 0, out_mix_tlv),
SOC_SINGLE("Left Input Mixer +20dB Switch",
WM8350_INPUT_MIXER_VOLUME_L, 0, 1, 0),
SOC_SINGLE("Right Input Mixer +20dB Switch",
WM8350_INPUT_MIXER_VOLUME_R, 0, 1, 0),
SOC_SINGLE_TLV("Out4 Capture Volume",
WM8350_INPUT_MIXER_VOLUME,
1, 7, 0, out_mix_tlv),
SOC_DOUBLE_R_EXT_TLV("Out1 Playback Volume",
WM8350_LOUT1_VOLUME,
WM8350_ROUT1_VOLUME,
2, 63, 0, wm8350_get_volsw_2r,
wm8350_put_volsw_2r_vu, out_pga_tlv),
SOC_DOUBLE_R("Out1 Playback ZC Switch",
WM8350_LOUT1_VOLUME,
WM8350_ROUT1_VOLUME, 13, 1, 0),
SOC_DOUBLE_R_EXT_TLV("Out2 Playback Volume",
WM8350_LOUT2_VOLUME,
WM8350_ROUT2_VOLUME,
2, 63, 0, wm8350_get_volsw_2r,
wm8350_put_volsw_2r_vu, out_pga_tlv),
SOC_DOUBLE_R("Out2 Playback ZC Switch", WM8350_LOUT2_VOLUME,
WM8350_ROUT2_VOLUME, 13, 1, 0),
SOC_SINGLE("Out2 Right Invert Switch", WM8350_ROUT2_VOLUME, 10, 1, 0),
SOC_SINGLE_TLV("Out2 Beep Volume", WM8350_BEEP_VOLUME,
5, 7, 0, out_mix_tlv),
SOC_DOUBLE_R("Out1 Playback Switch",
WM8350_LOUT1_VOLUME,
WM8350_ROUT1_VOLUME,
14, 1, 1),
SOC_DOUBLE_R("Out2 Playback Switch",
WM8350_LOUT2_VOLUME,
WM8350_ROUT2_VOLUME,
14, 1, 1),
};
/*
* DAPM Controls
*/
/* Left Playback Mixer */
static const struct snd_kcontrol_new wm8350_left_play_mixer_controls[] = {
SOC_DAPM_SINGLE("Playback Switch",
WM8350_LEFT_MIXER_CONTROL, 11, 1, 0),
SOC_DAPM_SINGLE("Left Bypass Switch",
WM8350_LEFT_MIXER_CONTROL, 2, 1, 0),
SOC_DAPM_SINGLE("Right Playback Switch",
WM8350_LEFT_MIXER_CONTROL, 12, 1, 0),
SOC_DAPM_SINGLE("Left Sidetone Switch",
WM8350_LEFT_MIXER_CONTROL, 0, 1, 0),
SOC_DAPM_SINGLE("Right Sidetone Switch",
WM8350_LEFT_MIXER_CONTROL, 1, 1, 0),
};
/* Right Playback Mixer */
static const struct snd_kcontrol_new wm8350_right_play_mixer_controls[] = {
SOC_DAPM_SINGLE("Playback Switch",
WM8350_RIGHT_MIXER_CONTROL, 12, 1, 0),
SOC_DAPM_SINGLE("Right Bypass Switch",
WM8350_RIGHT_MIXER_CONTROL, 3, 1, 0),
SOC_DAPM_SINGLE("Left Playback Switch",
WM8350_RIGHT_MIXER_CONTROL, 11, 1, 0),
SOC_DAPM_SINGLE("Left Sidetone Switch",
WM8350_RIGHT_MIXER_CONTROL, 0, 1, 0),
SOC_DAPM_SINGLE("Right Sidetone Switch",
WM8350_RIGHT_MIXER_CONTROL, 1, 1, 0),
};
/* Out4 Mixer */
static const struct snd_kcontrol_new wm8350_out4_mixer_controls[] = {
SOC_DAPM_SINGLE("Right Playback Switch",
WM8350_OUT4_MIXER_CONTROL, 12, 1, 0),
SOC_DAPM_SINGLE("Left Playback Switch",
WM8350_OUT4_MIXER_CONTROL, 11, 1, 0),
SOC_DAPM_SINGLE("Right Capture Switch",
WM8350_OUT4_MIXER_CONTROL, 9, 1, 0),
SOC_DAPM_SINGLE("Out3 Playback Switch",
WM8350_OUT4_MIXER_CONTROL, 2, 1, 0),
SOC_DAPM_SINGLE("Right Mixer Switch",
WM8350_OUT4_MIXER_CONTROL, 1, 1, 0),
SOC_DAPM_SINGLE("Left Mixer Switch",
WM8350_OUT4_MIXER_CONTROL, 0, 1, 0),
};
/* Out3 Mixer */
static const struct snd_kcontrol_new wm8350_out3_mixer_controls[] = {
SOC_DAPM_SINGLE("Left Playback Switch",
WM8350_OUT3_MIXER_CONTROL, 11, 1, 0),
SOC_DAPM_SINGLE("Left Capture Switch",
WM8350_OUT3_MIXER_CONTROL, 8, 1, 0),
SOC_DAPM_SINGLE("Out4 Playback Switch",
WM8350_OUT3_MIXER_CONTROL, 3, 1, 0),
SOC_DAPM_SINGLE("Left Mixer Switch",
WM8350_OUT3_MIXER_CONTROL, 0, 1, 0),
};
/* Left Input Mixer */
static const struct snd_kcontrol_new wm8350_left_capt_mixer_controls[] = {
SOC_DAPM_SINGLE_TLV("L2 Capture Volume",
WM8350_INPUT_MIXER_VOLUME_L, 1, 7, 0, out_mix_tlv),
SOC_DAPM_SINGLE_TLV("L3 Capture Volume",
WM8350_INPUT_MIXER_VOLUME_L, 9, 7, 0, out_mix_tlv),
SOC_DAPM_SINGLE("PGA Capture Switch",
WM8350_LEFT_INPUT_VOLUME, 14, 1, 1),
};
/* Right Input Mixer */
static const struct snd_kcontrol_new wm8350_right_capt_mixer_controls[] = {
SOC_DAPM_SINGLE_TLV("L2 Capture Volume",
WM8350_INPUT_MIXER_VOLUME_R, 5, 7, 0, out_mix_tlv),
SOC_DAPM_SINGLE_TLV("L3 Capture Volume",
WM8350_INPUT_MIXER_VOLUME_R, 13, 7, 0, out_mix_tlv),
SOC_DAPM_SINGLE("PGA Capture Switch",
WM8350_RIGHT_INPUT_VOLUME, 14, 1, 1),
};
/* Left Mic Mixer */
static const struct snd_kcontrol_new wm8350_left_mic_mixer_controls[] = {
SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 1, 1, 0),
SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 0, 1, 0),
SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 2, 1, 0),
};
/* Right Mic Mixer */
static const struct snd_kcontrol_new wm8350_right_mic_mixer_controls[] = {
SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 9, 1, 0),
SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 8, 1, 0),
SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 10, 1, 0),
};
/* Beep Switch */
static const struct snd_kcontrol_new wm8350_beep_switch_controls =
SOC_DAPM_SINGLE("Switch", WM8350_BEEP_VOLUME, 15, 1, 1);
/* Out4 Capture Mux */
static const struct snd_kcontrol_new wm8350_out4_capture_controls =
SOC_DAPM_ENUM("Route", wm8350_enum[7]);
static const struct snd_soc_dapm_widget wm8350_dapm_widgets[] = {
SND_SOC_DAPM_PGA("IN3R PGA", WM8350_POWER_MGMT_2, 11, 0, NULL, 0),
SND_SOC_DAPM_PGA("IN3L PGA", WM8350_POWER_MGMT_2, 10, 0, NULL, 0),
SND_SOC_DAPM_PGA_E("Right Out2 PGA", WM8350_POWER_MGMT_3, 3, 0, NULL,
0, pga_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA_E("Left Out2 PGA", WM8350_POWER_MGMT_3, 2, 0, NULL, 0,
pga_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA_E("Right Out1 PGA", WM8350_POWER_MGMT_3, 1, 0, NULL,
0, pga_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA_E("Left Out1 PGA", WM8350_POWER_MGMT_3, 0, 0, NULL, 0,
pga_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_MIXER("Right Capture Mixer", WM8350_POWER_MGMT_2,
7, 0, &wm8350_right_capt_mixer_controls[0],
ARRAY_SIZE(wm8350_right_capt_mixer_controls)),
SND_SOC_DAPM_MIXER("Left Capture Mixer", WM8350_POWER_MGMT_2,
6, 0, &wm8350_left_capt_mixer_controls[0],
ARRAY_SIZE(wm8350_left_capt_mixer_controls)),
SND_SOC_DAPM_MIXER("Out4 Mixer", WM8350_POWER_MGMT_2, 5, 0,
&wm8350_out4_mixer_controls[0],
ARRAY_SIZE(wm8350_out4_mixer_controls)),
SND_SOC_DAPM_MIXER("Out3 Mixer", WM8350_POWER_MGMT_2, 4, 0,
&wm8350_out3_mixer_controls[0],
ARRAY_SIZE(wm8350_out3_mixer_controls)),
SND_SOC_DAPM_MIXER("Right Playback Mixer", WM8350_POWER_MGMT_2, 1, 0,
&wm8350_right_play_mixer_controls[0],
ARRAY_SIZE(wm8350_right_play_mixer_controls)),
SND_SOC_DAPM_MIXER("Left Playback Mixer", WM8350_POWER_MGMT_2, 0, 0,
&wm8350_left_play_mixer_controls[0],
ARRAY_SIZE(wm8350_left_play_mixer_controls)),
SND_SOC_DAPM_MIXER("Left Mic Mixer", WM8350_POWER_MGMT_2, 8, 0,
&wm8350_left_mic_mixer_controls[0],
ARRAY_SIZE(wm8350_left_mic_mixer_controls)),
SND_SOC_DAPM_MIXER("Right Mic Mixer", WM8350_POWER_MGMT_2, 9, 0,
&wm8350_right_mic_mixer_controls[0],
ARRAY_SIZE(wm8350_right_mic_mixer_controls)),
/* virtual mixer for Beep and Out2R */
SND_SOC_DAPM_MIXER("Out2 Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SWITCH("Beep", WM8350_POWER_MGMT_3, 7, 0,
&wm8350_beep_switch_controls),
SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
WM8350_POWER_MGMT_4, 3, 0),
SND_SOC_DAPM_ADC("Left ADC", "Left Capture",
WM8350_POWER_MGMT_4, 2, 0),
SND_SOC_DAPM_DAC("Right DAC", "Right Playback",
WM8350_POWER_MGMT_4, 5, 0),
SND_SOC_DAPM_DAC("Left DAC", "Left Playback",
WM8350_POWER_MGMT_4, 4, 0),
SND_SOC_DAPM_MICBIAS("Mic Bias", WM8350_POWER_MGMT_1, 4, 0),
SND_SOC_DAPM_MUX("Out4 Capture Channel", SND_SOC_NOPM, 0, 0,
&wm8350_out4_capture_controls),
SND_SOC_DAPM_OUTPUT("OUT1R"),
SND_SOC_DAPM_OUTPUT("OUT1L"),
SND_SOC_DAPM_OUTPUT("OUT2R"),
SND_SOC_DAPM_OUTPUT("OUT2L"),
SND_SOC_DAPM_OUTPUT("OUT3"),
SND_SOC_DAPM_OUTPUT("OUT4"),
SND_SOC_DAPM_INPUT("IN1RN"),
SND_SOC_DAPM_INPUT("IN1RP"),
SND_SOC_DAPM_INPUT("IN2R"),
SND_SOC_DAPM_INPUT("IN1LP"),
SND_SOC_DAPM_INPUT("IN1LN"),
SND_SOC_DAPM_INPUT("IN2L"),
SND_SOC_DAPM_INPUT("IN3R"),
SND_SOC_DAPM_INPUT("IN3L"),
};
static const struct snd_soc_dapm_route wm8350_dapm_routes[] = {
/* left playback mixer */
{"Left Playback Mixer", "Playback Switch", "Left DAC"},
{"Left Playback Mixer", "Left Bypass Switch", "IN3L PGA"},
{"Left Playback Mixer", "Right Playback Switch", "Right DAC"},
{"Left Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"},
{"Left Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"},
/* right playback mixer */
{"Right Playback Mixer", "Playback Switch", "Right DAC"},
{"Right Playback Mixer", "Right Bypass Switch", "IN3R PGA"},
{"Right Playback Mixer", "Left Playback Switch", "Left DAC"},
{"Right Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"},
{"Right Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"},
/* out4 playback mixer */
{"Out4 Mixer", "Right Playback Switch", "Right DAC"},
{"Out4 Mixer", "Left Playback Switch", "Left DAC"},
{"Out4 Mixer", "Right Capture Switch", "Right Capture Mixer"},
{"Out4 Mixer", "Out3 Playback Switch", "Out3 Mixer"},
{"Out4 Mixer", "Right Mixer Switch", "Right Playback Mixer"},
{"Out4 Mixer", "Left Mixer Switch", "Left Playback Mixer"},
{"OUT4", NULL, "Out4 Mixer"},
/* out3 playback mixer */
{"Out3 Mixer", "Left Playback Switch", "Left DAC"},
{"Out3 Mixer", "Left Capture Switch", "Left Capture Mixer"},
{"Out3 Mixer", "Left Mixer Switch", "Left Playback Mixer"},
{"Out3 Mixer", "Out4 Playback Switch", "Out4 Mixer"},
{"OUT3", NULL, "Out3 Mixer"},
/* out2 */
{"Right Out2 PGA", NULL, "Right Playback Mixer"},
{"Left Out2 PGA", NULL, "Left Playback Mixer"},
{"OUT2L", NULL, "Left Out2 PGA"},
{"OUT2R", NULL, "Right Out2 PGA"},
/* out1 */
{"Right Out1 PGA", NULL, "Right Playback Mixer"},
{"Left Out1 PGA", NULL, "Left Playback Mixer"},
{"OUT1L", NULL, "Left Out1 PGA"},
{"OUT1R", NULL, "Right Out1 PGA"},
/* ADCs */
{"Left ADC", NULL, "Left Capture Mixer"},
{"Right ADC", NULL, "Right Capture Mixer"},
/* Left capture mixer */
{"Left Capture Mixer", "L2 Capture Volume", "IN2L"},
{"Left Capture Mixer", "L3 Capture Volume", "IN3L PGA"},
{"Left Capture Mixer", "PGA Capture Switch", "Left Mic Mixer"},
{"Left Capture Mixer", NULL, "Out4 Capture Channel"},
/* Right capture mixer */
{"Right Capture Mixer", "L2 Capture Volume", "IN2R"},
{"Right Capture Mixer", "L3 Capture Volume", "IN3R PGA"},
{"Right Capture Mixer", "PGA Capture Switch", "Right Mic Mixer"},
{"Right Capture Mixer", NULL, "Out4 Capture Channel"},
/* L3 Inputs */
{"IN3L PGA", NULL, "IN3L"},
{"IN3R PGA", NULL, "IN3R"},
/* Left Mic mixer */
{"Left Mic Mixer", "INN Capture Switch", "IN1LN"},
{"Left Mic Mixer", "INP Capture Switch", "IN1LP"},
{"Left Mic Mixer", "IN2 Capture Switch", "IN2L"},
/* Right Mic mixer */
{"Right Mic Mixer", "INN Capture Switch", "IN1RN"},
{"Right Mic Mixer", "INP Capture Switch", "IN1RP"},
{"Right Mic Mixer", "IN2 Capture Switch", "IN2R"},
/* out 4 capture */
{"Out4 Capture Channel", NULL, "Out4 Mixer"},
/* Beep */
{"Beep", NULL, "IN3R PGA"},
};
static int wm8350_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct wm8350_data *wm8350_data = snd_soc_component_get_drvdata(component);
struct wm8350 *wm8350 = wm8350_data->wm8350;
u16 fll_4;
switch (clk_id) {
case WM8350_MCLK_SEL_MCLK:
wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_1,
WM8350_MCLK_SEL);
break;
case WM8350_MCLK_SEL_PLL_MCLK:
case WM8350_MCLK_SEL_PLL_DAC:
case WM8350_MCLK_SEL_PLL_ADC:
case WM8350_MCLK_SEL_PLL_32K:
wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_1,
WM8350_MCLK_SEL);
fll_4 = snd_soc_component_read(component, WM8350_FLL_CONTROL_4) &
~WM8350_FLL_CLK_SRC_MASK;
snd_soc_component_write(component, WM8350_FLL_CONTROL_4, fll_4 | clk_id);
break;
}
/* MCLK direction */
if (dir == SND_SOC_CLOCK_OUT)
wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_2,
WM8350_MCLK_DIR);
else
wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_2,
WM8350_MCLK_DIR);
return 0;
}
static int wm8350_set_clkdiv(struct snd_soc_dai *codec_dai, int div_id, int div)
{
struct snd_soc_component *component = codec_dai->component;
u16 val;
switch (div_id) {
case WM8350_ADC_CLKDIV:
val = snd_soc_component_read(component, WM8350_ADC_DIVIDER) &
~WM8350_ADC_CLKDIV_MASK;
snd_soc_component_write(component, WM8350_ADC_DIVIDER, val | div);
break;
case WM8350_DAC_CLKDIV:
val = snd_soc_component_read(component, WM8350_DAC_CLOCK_CONTROL) &
~WM8350_DAC_CLKDIV_MASK;
snd_soc_component_write(component, WM8350_DAC_CLOCK_CONTROL, val | div);
break;
case WM8350_BCLK_CLKDIV:
val = snd_soc_component_read(component, WM8350_CLOCK_CONTROL_1) &
~WM8350_BCLK_DIV_MASK;
snd_soc_component_write(component, WM8350_CLOCK_CONTROL_1, val | div);
break;
case WM8350_OPCLK_CLKDIV:
val = snd_soc_component_read(component, WM8350_CLOCK_CONTROL_1) &
~WM8350_OPCLK_DIV_MASK;
snd_soc_component_write(component, WM8350_CLOCK_CONTROL_1, val | div);
break;
case WM8350_SYS_CLKDIV:
val = snd_soc_component_read(component, WM8350_CLOCK_CONTROL_1) &
~WM8350_MCLK_DIV_MASK;
snd_soc_component_write(component, WM8350_CLOCK_CONTROL_1, val | div);
break;
case WM8350_DACLR_CLKDIV:
val = snd_soc_component_read(component, WM8350_DAC_LR_RATE) &
~WM8350_DACLRC_RATE_MASK;
snd_soc_component_write(component, WM8350_DAC_LR_RATE, val | div);
break;
case WM8350_ADCLR_CLKDIV:
val = snd_soc_component_read(component, WM8350_ADC_LR_RATE) &
~WM8350_ADCLRC_RATE_MASK;
snd_soc_component_write(component, WM8350_ADC_LR_RATE, val | div);
break;
default:
return -EINVAL;
}
return 0;
}
static int wm8350_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
u16 iface = snd_soc_component_read(component, WM8350_AI_FORMATING) &
~(WM8350_AIF_BCLK_INV | WM8350_AIF_LRCLK_INV | WM8350_AIF_FMT_MASK);
u16 master = snd_soc_component_read(component, WM8350_AI_DAC_CONTROL) &
~WM8350_BCLK_MSTR;
u16 dac_lrc = snd_soc_component_read(component, WM8350_DAC_LR_RATE) &
~WM8350_DACLRC_ENA;
u16 adc_lrc = snd_soc_component_read(component, WM8350_ADC_LR_RATE) &
~WM8350_ADCLRC_ENA;
/* set master/slave audio interface */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
master |= WM8350_BCLK_MSTR;
dac_lrc |= WM8350_DACLRC_ENA;
adc_lrc |= WM8350_ADCLRC_ENA;
break;
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface |= 0x2 << 8;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
iface |= 0x1 << 8;
break;
case SND_SOC_DAIFMT_DSP_A:
iface |= 0x3 << 8;
break;
case SND_SOC_DAIFMT_DSP_B:
iface |= 0x3 << 8 | WM8350_AIF_LRCLK_INV;
break;
default:
return -EINVAL;
}
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
iface |= WM8350_AIF_LRCLK_INV | WM8350_AIF_BCLK_INV;
break;
case SND_SOC_DAIFMT_IB_NF:
iface |= WM8350_AIF_BCLK_INV;
break;
case SND_SOC_DAIFMT_NB_IF:
iface |= WM8350_AIF_LRCLK_INV;
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, WM8350_AI_FORMATING, iface);
snd_soc_component_write(component, WM8350_AI_DAC_CONTROL, master);
snd_soc_component_write(component, WM8350_DAC_LR_RATE, dac_lrc);
snd_soc_component_write(component, WM8350_ADC_LR_RATE, adc_lrc);
return 0;
}
static int wm8350_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *codec_dai)
{
struct snd_soc_component *component = codec_dai->component;
struct wm8350_data *wm8350_data = snd_soc_component_get_drvdata(component);
struct wm8350 *wm8350 = wm8350_data->wm8350;
u16 iface = snd_soc_component_read(component, WM8350_AI_FORMATING) &
~WM8350_AIF_WL_MASK;
/* bit size */
switch (params_width(params)) {
case 16:
break;
case 20:
iface |= 0x1 << 10;
break;
case 24:
iface |= 0x2 << 10;
break;
case 32:
iface |= 0x3 << 10;
break;
}
snd_soc_component_write(component, WM8350_AI_FORMATING, iface);
/* The sloping stopband filter is recommended for use with
* lower sample rates to improve performance.
*/
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
if (params_rate(params) < 24000)
wm8350_set_bits(wm8350, WM8350_DAC_MUTE_VOLUME,
WM8350_DAC_SB_FILT);
else
wm8350_clear_bits(wm8350, WM8350_DAC_MUTE_VOLUME,
WM8350_DAC_SB_FILT);
}
return 0;
}
static int wm8350_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
unsigned int val;
if (mute)
val = WM8350_DAC_MUTE_ENA;
else
val = 0;
snd_soc_component_update_bits(component, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA, val);
return 0;
}
/* FLL divisors */
struct _fll_div {
int div; /* FLL_OUTDIV */
int n;
int k;
int ratio; /* FLL_FRATIO */
};
/* The size in bits of the fll divide multiplied by 10
* to allow rounding later */
#define FIXED_FLL_SIZE ((1 << 16) * 10)
static inline int fll_factors(struct _fll_div *fll_div, unsigned int input,
unsigned int output)
{
u64 Kpart;
unsigned int t1, t2, K, Nmod;
if (output >= 2815250 && output <= 3125000)
fll_div->div = 0x4;
else if (output >= 5625000 && output <= 6250000)
fll_div->div = 0x3;
else if (output >= 11250000 && output <= 12500000)
fll_div->div = 0x2;
else if (output >= 22500000 && output <= 25000000)
fll_div->div = 0x1;
else {
printk(KERN_ERR "wm8350: fll freq %d out of range\n", output);
return -EINVAL;
}
if (input > 48000)
fll_div->ratio = 1;
else
fll_div->ratio = 8;
t1 = output * (1 << (fll_div->div + 1));
t2 = input * fll_div->ratio;
fll_div->n = t1 / t2;
Nmod = t1 % t2;
if (Nmod) {
Kpart = FIXED_FLL_SIZE * (long long)Nmod;
do_div(Kpart, t2);
K = Kpart & 0xFFFFFFFF;
/* Check if we need to round */
if ((K % 10) >= 5)
K += 5;
/* Move down to proper range now rounding is done */
K /= 10;
fll_div->k = K;
} else
fll_div->k = 0;
return 0;
}
static int wm8350_set_fll(struct snd_soc_dai *codec_dai,
int pll_id, int source, unsigned int freq_in,
unsigned int freq_out)
{
struct snd_soc_component *component = codec_dai->component;
struct wm8350_data *priv = snd_soc_component_get_drvdata(component);
struct wm8350 *wm8350 = priv->wm8350;
struct _fll_div fll_div;
int ret = 0;
u16 fll_1, fll_4;
if (freq_in == priv->fll_freq_in && freq_out == priv->fll_freq_out)
return 0;
/* power down FLL - we need to do this for reconfiguration */
wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4,
WM8350_FLL_ENA | WM8350_FLL_OSC_ENA);
if (freq_out == 0 || freq_in == 0)
return ret;
ret = fll_factors(&fll_div, freq_in, freq_out);
if (ret < 0)
return ret;
dev_dbg(wm8350->dev,
"FLL in %u FLL out %u N 0x%x K 0x%x div %d ratio %d",
freq_in, freq_out, fll_div.n, fll_div.k, fll_div.div,
fll_div.ratio);
/* set up N.K & dividers */
fll_1 = snd_soc_component_read(component, WM8350_FLL_CONTROL_1) &
~(WM8350_FLL_OUTDIV_MASK | WM8350_FLL_RSP_RATE_MASK | 0xc000);
snd_soc_component_write(component, WM8350_FLL_CONTROL_1,
fll_1 | (fll_div.div << 8) | 0x50);
snd_soc_component_write(component, WM8350_FLL_CONTROL_2,
(fll_div.ratio << 11) | (fll_div.
n & WM8350_FLL_N_MASK));
snd_soc_component_write(component, WM8350_FLL_CONTROL_3, fll_div.k);
fll_4 = snd_soc_component_read(component, WM8350_FLL_CONTROL_4) &
~(WM8350_FLL_FRAC | WM8350_FLL_SLOW_LOCK_REF);
snd_soc_component_write(component, WM8350_FLL_CONTROL_4,
fll_4 | (fll_div.k ? WM8350_FLL_FRAC : 0) |
(fll_div.ratio == 8 ? WM8350_FLL_SLOW_LOCK_REF : 0));
/* power FLL on */
wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_OSC_ENA);
wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_ENA);
priv->fll_freq_out = freq_out;
priv->fll_freq_in = freq_in;
return 0;
}
static int wm8350_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct wm8350_data *priv = snd_soc_component_get_drvdata(component);
struct wm8350 *wm8350 = priv->wm8350;
struct wm8350_audio_platform_data *platform =
wm8350->codec.platform_data;
u16 pm1;
int ret;
switch (level) {
case SND_SOC_BIAS_ON:
pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
pm1 | WM8350_VMID_50K |
platform->codec_current_on << 14);
break;
case SND_SOC_BIAS_PREPARE:
pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1);
pm1 &= ~WM8350_VMID_MASK;
wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
pm1 | WM8350_VMID_50K);
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies),
priv->supplies);
if (ret != 0)
return ret;
/* Enable the system clock */
wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4,
WM8350_SYSCLK_ENA);
/* mute DAC & outputs */
wm8350_set_bits(wm8350, WM8350_DAC_MUTE,
WM8350_DAC_MUTE_ENA);
/* discharge cap memory */
wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
platform->dis_out1 |
(platform->dis_out2 << 2) |
(platform->dis_out3 << 4) |
(platform->dis_out4 << 6));
/* wait for discharge */
schedule_timeout_interruptible(msecs_to_jiffies
(platform->
cap_discharge_msecs));
/* enable antipop */
wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
(platform->vmid_s_curve << 8));
/* ramp up vmid */
wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
(platform->
codec_current_charge << 14) |
WM8350_VMID_5K | WM8350_VMIDEN |
WM8350_VBUFEN);
/* wait for vmid */
schedule_timeout_interruptible(msecs_to_jiffies
(platform->
vmid_charge_msecs));
/* turn on vmid 300k */
pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
pm1 |= WM8350_VMID_300K |
(platform->codec_current_standby << 14);
wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
pm1);
/* enable analogue bias */
pm1 |= WM8350_BIASEN;
wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
/* disable antipop */
wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0);
} else {
/* turn on vmid 300k and reduce current */
pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
pm1 | WM8350_VMID_300K |
(platform->
codec_current_standby << 14));
}
break;
case SND_SOC_BIAS_OFF:
/* mute DAC & enable outputs */
wm8350_set_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA);
wm8350_set_bits(wm8350, WM8350_POWER_MGMT_3,
WM8350_OUT1L_ENA | WM8350_OUT1R_ENA |
WM8350_OUT2L_ENA | WM8350_OUT2R_ENA);
/* enable anti pop S curve */
wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
(platform->vmid_s_curve << 8));
/* turn off vmid */
pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
~WM8350_VMIDEN;
wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
/* wait */
schedule_timeout_interruptible(msecs_to_jiffies
(platform->
vmid_discharge_msecs));
wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
(platform->vmid_s_curve << 8) |
platform->dis_out1 |
(platform->dis_out2 << 2) |
(platform->dis_out3 << 4) |
(platform->dis_out4 << 6));
/* turn off VBuf and drain */
pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
~(WM8350_VBUFEN | WM8350_VMID_MASK);
wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
pm1 | WM8350_OUTPUT_DRAIN_EN);
/* wait */
schedule_timeout_interruptible(msecs_to_jiffies
(platform->drain_msecs));
pm1 &= ~WM8350_BIASEN;
wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
/* disable anti-pop */
wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0);
wm8350_clear_bits(wm8350, WM8350_LOUT1_VOLUME,
WM8350_OUT1L_ENA);
wm8350_clear_bits(wm8350, WM8350_ROUT1_VOLUME,
WM8350_OUT1R_ENA);
wm8350_clear_bits(wm8350, WM8350_LOUT2_VOLUME,
WM8350_OUT2L_ENA);
wm8350_clear_bits(wm8350, WM8350_ROUT2_VOLUME,
WM8350_OUT2R_ENA);
/* disable clock gen */
wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4,
WM8350_SYSCLK_ENA);
regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
priv->supplies);
break;
}
return 0;
}
static void wm8350_hp_work(struct wm8350_data *priv,
struct wm8350_jack_data *jack,
u16 mask)
{
struct wm8350 *wm8350 = priv->wm8350;
u16 reg;
int report;
reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
if (reg & mask)
report = jack->report;
else
report = 0;
snd_soc_jack_report(jack->jack, report, jack->report);
}
static void wm8350_hpl_work(struct work_struct *work)
{
struct wm8350_data *priv =
container_of(work, struct wm8350_data, hpl.work.work);
wm8350_hp_work(priv, &priv->hpl, WM8350_JACK_L_LVL);
}
static void wm8350_hpr_work(struct work_struct *work)
{
struct wm8350_data *priv =
container_of(work, struct wm8350_data, hpr.work.work);
wm8350_hp_work(priv, &priv->hpr, WM8350_JACK_R_LVL);
}
static irqreturn_t wm8350_hpl_jack_handler(int irq, void *data)
{
struct wm8350_data *priv = data;
struct wm8350 *wm8350 = priv->wm8350;
#ifndef CONFIG_SND_SOC_WM8350_MODULE
trace_snd_soc_jack_irq("WM8350 HPL");
#endif
if (device_may_wakeup(wm8350->dev))
pm_wakeup_event(wm8350->dev, 250);
queue_delayed_work(system_power_efficient_wq,
&priv->hpl.work, msecs_to_jiffies(200));
return IRQ_HANDLED;
}
static irqreturn_t wm8350_hpr_jack_handler(int irq, void *data)
{
struct wm8350_data *priv = data;
struct wm8350 *wm8350 = priv->wm8350;
#ifndef CONFIG_SND_SOC_WM8350_MODULE
trace_snd_soc_jack_irq("WM8350 HPR");
#endif
if (device_may_wakeup(wm8350->dev))
pm_wakeup_event(wm8350->dev, 250);
queue_delayed_work(system_power_efficient_wq,
&priv->hpr.work, msecs_to_jiffies(200));
return IRQ_HANDLED;
}
/**
* wm8350_hp_jack_detect - Enable headphone jack detection.
*
* @component: WM8350 component
* @which: left or right jack detect signal
* @jack: jack to report detection events on
* @report: value to report
*
* Enables the headphone jack detection of the WM8350. If no report
* is specified then detection is disabled.
*/
int wm8350_hp_jack_detect(struct snd_soc_component *component, enum wm8350_jack which,
struct snd_soc_jack *jack, int report)
{
struct wm8350_data *priv = snd_soc_component_get_drvdata(component);
struct wm8350 *wm8350 = priv->wm8350;
int ena;
switch (which) {
case WM8350_JDL:
priv->hpl.jack = jack;
priv->hpl.report = report;
ena = WM8350_JDL_ENA;
break;
case WM8350_JDR:
priv->hpr.jack = jack;
priv->hpr.report = report;
ena = WM8350_JDR_ENA;
break;
default:
return -EINVAL;
}
if (report) {
wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
wm8350_set_bits(wm8350, WM8350_JACK_DETECT, ena);
} else {
wm8350_clear_bits(wm8350, WM8350_JACK_DETECT, ena);
}
/* Sync status */
switch (which) {
case WM8350_JDL:
wm8350_hpl_jack_handler(0, priv);
break;
case WM8350_JDR:
wm8350_hpr_jack_handler(0, priv);
break;
}
return 0;
}
EXPORT_SYMBOL_GPL(wm8350_hp_jack_detect);
static irqreturn_t wm8350_mic_handler(int irq, void *data)
{
struct wm8350_data *priv = data;
struct wm8350 *wm8350 = priv->wm8350;
u16 reg;
int report = 0;
#ifndef CONFIG_SND_SOC_WM8350_MODULE
trace_snd_soc_jack_irq("WM8350 mic");
#endif
reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
if (reg & WM8350_JACK_MICSCD_LVL)
report |= priv->mic.short_report;
if (reg & WM8350_JACK_MICSD_LVL)
report |= priv->mic.report;
snd_soc_jack_report(priv->mic.jack, report,
priv->mic.report | priv->mic.short_report);
return IRQ_HANDLED;
}
/**
* wm8350_mic_jack_detect - Enable microphone jack detection.
*
* @component: WM8350 component
* @jack: jack to report detection events on
* @detect_report: value to report when presence detected
* @short_report: value to report when microphone short detected
*
* Enables the microphone jack detection of the WM8350. If both reports
* are specified as zero then detection is disabled.
*/
int wm8350_mic_jack_detect(struct snd_soc_component *component,
struct snd_soc_jack *jack,
int detect_report, int short_report)
{
struct wm8350_data *priv = snd_soc_component_get_drvdata(component);
struct wm8350 *wm8350 = priv->wm8350;
priv->mic.jack = jack;
priv->mic.report = detect_report;
priv->mic.short_report = short_report;
if (detect_report || short_report) {
wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
wm8350_set_bits(wm8350, WM8350_POWER_MGMT_1,
WM8350_MIC_DET_ENA);
} else {
wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_1,
WM8350_MIC_DET_ENA);
}
return 0;
}
EXPORT_SYMBOL_GPL(wm8350_mic_jack_detect);
#define WM8350_RATES (SNDRV_PCM_RATE_8000_96000)
#define WM8350_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE)
static const struct snd_soc_dai_ops wm8350_dai_ops = {
.hw_params = wm8350_pcm_hw_params,
.mute_stream = wm8350_mute,
.set_fmt = wm8350_set_dai_fmt,
.set_sysclk = wm8350_set_dai_sysclk,
.set_pll = wm8350_set_fll,
.set_clkdiv = wm8350_set_clkdiv,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver wm8350_dai = {
.name = "wm8350-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM8350_RATES,
.formats = WM8350_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM8350_RATES,
.formats = WM8350_FORMATS,
},
.ops = &wm8350_dai_ops,
};
static int wm8350_component_probe(struct snd_soc_component *component)
{
struct wm8350 *wm8350 = dev_get_platdata(component->dev);
struct wm8350_data *priv;
struct wm8350_output *out1;
struct wm8350_output *out2;
int ret, i;
if (wm8350->codec.platform_data == NULL) {
dev_err(component->dev, "No audio platform data supplied\n");
return -EINVAL;
}
priv = devm_kzalloc(component->dev, sizeof(struct wm8350_data),
GFP_KERNEL);
if (priv == NULL)
return -ENOMEM;
snd_soc_component_init_regmap(component, wm8350->regmap);
snd_soc_component_set_drvdata(component, priv);
priv->wm8350 = wm8350;
for (i = 0; i < ARRAY_SIZE(supply_names); i++)
priv->supplies[i].supply = supply_names[i];
ret = devm_regulator_bulk_get(wm8350->dev, ARRAY_SIZE(priv->supplies),
priv->supplies);
if (ret != 0)
return ret;
/* Put the codec into reset if it wasn't already */
wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
INIT_DELAYED_WORK(&priv->pga_work, wm8350_pga_work);
INIT_DELAYED_WORK(&priv->hpl.work, wm8350_hpl_work);
INIT_DELAYED_WORK(&priv->hpr.work, wm8350_hpr_work);
/* Enable the codec */
wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
/* Enable robust clocking mode in ADC */
snd_soc_component_write(component, WM8350_SECURITY, 0xa7);
snd_soc_component_write(component, 0xde, 0x13);
snd_soc_component_write(component, WM8350_SECURITY, 0);
/* read OUT1 & OUT2 volumes */
out1 = &priv->out1;
out2 = &priv->out2;
out1->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME) &
WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
out1->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME) &
WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
out2->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME) &
WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
out2->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME) &
WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME, 0);
wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME, 0);
wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME, 0);
wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME, 0);
/* Latch VU bits & mute */
wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME,
WM8350_OUT1_VU | WM8350_OUT1L_MUTE);
wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME,
WM8350_OUT2_VU | WM8350_OUT2L_MUTE);
wm8350_set_bits(wm8350, WM8350_ROUT1_VOLUME,
WM8350_OUT1_VU | WM8350_OUT1R_MUTE);
wm8350_set_bits(wm8350, WM8350_ROUT2_VOLUME,
WM8350_OUT2_VU | WM8350_OUT2R_MUTE);
/* Make sure AIF tristating is disabled by default */
wm8350_clear_bits(wm8350, WM8350_AI_FORMATING, WM8350_AIF_TRI);
/* Make sure we've got a sane companding setup too */
wm8350_clear_bits(wm8350, WM8350_ADC_DAC_COMP,
WM8350_DAC_COMP | WM8350_LOOPBACK);
/* Make sure jack detect is disabled to start off with */
wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,
WM8350_JDL_ENA | WM8350_JDR_ENA);
ret = wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L,
wm8350_hpl_jack_handler, 0, "Left jack detect",
priv);
if (ret != 0)
goto err;
ret = wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R,
wm8350_hpr_jack_handler, 0, "Right jack detect",
priv);
if (ret != 0)
goto free_jck_det_l;
ret = wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICSCD,
wm8350_mic_handler, 0, "Microphone short", priv);
if (ret != 0)
goto free_jck_det_r;
ret = wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICD,
wm8350_mic_handler, 0, "Microphone detect", priv);
if (ret != 0)
goto free_micscd;
return 0;
free_micscd:
wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICSCD, priv);
free_jck_det_r:
wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R, priv);
free_jck_det_l:
wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L, priv);
err:
return ret;
}
static void wm8350_component_remove(struct snd_soc_component *component)
{
struct wm8350_data *priv = snd_soc_component_get_drvdata(component);
struct wm8350 *wm8350 = dev_get_platdata(component->dev);
wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,
WM8350_JDL_ENA | WM8350_JDR_ENA);
wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICD, priv);
wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICSCD, priv);
wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L, priv);
wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R, priv);
priv->hpl.jack = NULL;
priv->hpr.jack = NULL;
priv->mic.jack = NULL;
cancel_delayed_work_sync(&priv->hpl.work);
cancel_delayed_work_sync(&priv->hpr.work);
/* if there was any work waiting then we run it now and
* wait for its completion */
flush_delayed_work(&priv->pga_work);
wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
}
static const struct snd_soc_component_driver soc_component_dev_wm8350 = {
.probe = wm8350_component_probe,
.remove = wm8350_component_remove,
.set_bias_level = wm8350_set_bias_level,
.controls = wm8350_snd_controls,
.num_controls = ARRAY_SIZE(wm8350_snd_controls),
.dapm_widgets = wm8350_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8350_dapm_widgets),
.dapm_routes = wm8350_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(wm8350_dapm_routes),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int wm8350_probe(struct platform_device *pdev)
{
return devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_wm8350,
&wm8350_dai, 1);
}
static struct platform_driver wm8350_codec_driver = {
.driver = {
.name = "wm8350-codec",
},
.probe = wm8350_probe,
};
module_platform_driver(wm8350_codec_driver);
MODULE_DESCRIPTION("ASoC WM8350 driver");
MODULE_AUTHOR("Liam Girdwood");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:wm8350-codec");
| linux-master | sound/soc/codecs/wm8350.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Based on code by Hu Jin
* Copyright (C) 2014 Asahi Kasei Microdevices Corporation
*/
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <sound/soc.h>
#include <sound/tlv.h>
/* Registers and fields */
#define AK4375_00_POWER_MANAGEMENT1 0x00
#define PMPLL BIT(0) /* 0: PLL off, 1: PLL on */
#define AK4375_01_POWER_MANAGEMENT2 0x01
#define PMCP1 BIT(0) /* Charge Pump 1: LDO1 and DAC */
#define PMCP2 BIT(1) /* Charge Pump 2: Class-G HP Amp */
#define PMLDO1P BIT(4)
#define PMLDO1N BIT(5)
#define PMLDO (PMLDO1P | PMLDO1N)
#define AK4375_02_POWER_MANAGEMENT3 0x02
#define AK4375_03_POWER_MANAGEMENT4 0x03
#define AK4375_04_OUTPUT_MODE_SETTING 0x04
#define AK4375_05_CLOCK_MODE_SELECT 0x05
#define FS_MASK GENMASK(4, 0)
#define FS_8KHZ 0x00
#define FS_11_025KHZ 0x01
#define FS_16KHZ 0x04
#define FS_22_05KHZ 0x05
#define FS_32KHZ 0x08
#define FS_44_1KHZ 0x09
#define FS_48KHZ 0x0a
#define FS_88_2KHZ 0x0d
#define FS_96KHZ 0x0e
#define FS_176_4KHZ 0x11
#define FS_192KHZ 0x12
#define CM_MASK GENMASK(6, 5) /* For SRC Bypass mode */
#define CM_0 (0x0 << 5)
#define CM_1 (0x1 << 5)
#define CM_2 (0x2 << 5)
#define CM_3 (0x3 << 5)
#define AK4375_06_DIGITAL_FILTER_SELECT 0x06
#define DADFSEL BIT(5) /* 0: in SRC Bypass mode, 1: in SRC mode */
#define DASL BIT(6)
#define DASD BIT(7)
#define AK4375_07_DAC_MONO_MIXING 0x07
#define DACMUTE_MASK (GENMASK(5, 4) | GENMASK(1, 0)) /* Clear to mute */
#define AK4375_08_JITTER_CLEANER_SETTING1 0x08
#define AK4375_09_JITTER_CLEANER_SETTING2 0x09
#define AK4375_0A_JITTER_CLEANER_SETTING3 0x0a
#define SELDAIN BIT(1) /* 0: SRC Bypass mode, 1: SRC mode */
#define XCKSEL BIT(6) /* 0: PLL0, 1: MCKI */
#define XCKCPSEL BIT(7) /* Should be equal to SELDAIN and XCKSEL */
#define AK4375_0B_LCH_OUTPUT_VOLUME 0x0b
#define AK4375_0C_RCH_OUTPUT_VOLUME 0x0c
#define AK4375_0D_HP_VOLUME_CONTROL 0x0d
#define AK4375_0E_PLL_CLK_SOURCE_SELECT 0x0e
#define PLS BIT(0) /* 0: MCKI, 1: BCLK */
#define AK4375_0F_PLL_REF_CLK_DIVIDER1 0x0f /* Reference clock divider [15:8] bits */
#define AK4375_10_PLL_REF_CLK_DIVIDER2 0x10 /* Reference clock divider [7:0] bis */
#define AK4375_11_PLL_FB_CLK_DIVIDER1 0x11 /* Feedback clock divider [15:8] bits */
#define AK4375_12_PLL_FB_CLK_DIVIDER2 0x12 /* Feedback clock divider [7:0] bits */
#define AK4375_13_SRC_CLK_SOURCE 0x13 /* SRC Bypass: SRCCKS=XCKSEL=SELDAIN=0 */
#define SRCCKS BIT(0) /* SRC Clock source 0: MCKI, 1: PLL0 */
#define DIV BIT(4)
#define AK4375_14_DAC_CLK_DIVIDER 0x14
#define AK4375_15_AUDIO_IF_FORMAT 0x15
#define DEVICEID_MASK GENMASK(7, 5)
#define AK4375_24_MODE_CONTROL 0x24
#define AK4375_PLL_FREQ_OUT_112896000 112896000 /* 44.1 kHz base rate */
#define AK4375_PLL_FREQ_OUT_122880000 122880000 /* 32 and 48 kHz base rates */
#define DEVICEID_AK4375 0x00
#define DEVICEID_AK4375A 0x01
#define DEVICEID_AK4376A 0x02
#define DEVICEID_AK4377 0x03
#define DEVICEID_AK4331 0x07
static const char * const supply_names[] = {
"avdd", "tvdd"
};
struct ak4375_drvdata {
struct snd_soc_dai_driver *dai_drv;
const struct snd_soc_component_driver *comp_drv;
};
struct ak4375_priv {
struct device *dev;
struct regmap *regmap;
struct gpio_desc *pdn_gpiod;
struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
unsigned int rate;
unsigned int pld;
u8 mute_save;
};
static const struct reg_default ak4375_reg_defaults[] = {
{ 0x00, 0x00 }, { 0x01, 0x00 }, { 0x02, 0x00 },
{ 0x03, 0x00 }, { 0x04, 0x00 }, { 0x05, 0x00 },
{ 0x06, 0x00 }, { 0x07, 0x00 }, { 0x08, 0x00 },
{ 0x09, 0x00 }, { 0x0a, 0x00 }, { 0x0b, 0x19 },
{ 0x0c, 0x19 }, { 0x0d, 0x75 }, { 0x0e, 0x01 },
{ 0x0f, 0x00 }, { 0x10, 0x00 }, { 0x11, 0x00 },
{ 0x12, 0x00 }, { 0x13, 0x00 }, { 0x14, 0x00 },
{ 0x15, 0x00 }, { 0x24, 0x00 },
};
/*
* Output Digital volume control:
* from -12.5 to 3 dB in 0.5 dB steps (mute instead of -12.5 dB)
*/
static DECLARE_TLV_DB_SCALE(dac_tlv, -1250, 50, 0);
/*
* HP-Amp Analog volume control:
* from -4.2 to 6 dB in 2 dB steps (mute instead of -4.2 dB)
*/
static DECLARE_TLV_DB_SCALE(hpg_tlv, -4200, 20, 0);
static const char * const ak4375_ovolcn_select_texts[] = { "Dependent", "Independent" };
static const char * const ak4375_mdac_select_texts[] = { "x1", "x1/2" };
static const char * const ak4375_cpmode_select_texts[] = {
"Automatic Switching",
"+-VDD Operation",
"+-1/2VDD Operation"
};
/*
* DASD, DASL bits Digital Filter Setting
* 0, 0 : Sharp Roll-Off Filter
* 0, 1 : Slow Roll-Off Filter
* 1, 0 : Short delay Sharp Roll-Off Filter
* 1, 1 : Short delay Slow Roll-Off Filter
*/
static const char * const ak4375_digfil_select_texts[] = {
"Sharp Roll-Off Filter",
"Slow Roll-Off Filter",
"Short delay Sharp Roll-Off Filter",
"Short delay Slow Roll-Off Filter",
};
static const struct soc_enum ak4375_ovolcn_enum =
SOC_ENUM_SINGLE(AK4375_0B_LCH_OUTPUT_VOLUME, 7,
ARRAY_SIZE(ak4375_ovolcn_select_texts), ak4375_ovolcn_select_texts);
static const struct soc_enum ak4375_mdacl_enum =
SOC_ENUM_SINGLE(AK4375_07_DAC_MONO_MIXING, 2,
ARRAY_SIZE(ak4375_mdac_select_texts), ak4375_mdac_select_texts);
static const struct soc_enum ak4375_mdacr_enum =
SOC_ENUM_SINGLE(AK4375_07_DAC_MONO_MIXING, 6,
ARRAY_SIZE(ak4375_mdac_select_texts), ak4375_mdac_select_texts);
static const struct soc_enum ak4375_cpmode_enum =
SOC_ENUM_SINGLE(AK4375_03_POWER_MANAGEMENT4, 2,
ARRAY_SIZE(ak4375_cpmode_select_texts), ak4375_cpmode_select_texts);
static const struct soc_enum ak4375_digfil_enum =
SOC_ENUM_SINGLE(AK4375_06_DIGITAL_FILTER_SELECT, 6,
ARRAY_SIZE(ak4375_digfil_select_texts), ak4375_digfil_select_texts);
static const struct snd_kcontrol_new ak4375_snd_controls[] = {
SOC_DOUBLE_R_TLV("Digital Output Volume", AK4375_0B_LCH_OUTPUT_VOLUME,
AK4375_0C_RCH_OUTPUT_VOLUME, 0, 0x1f, 0, dac_tlv),
SOC_SINGLE_TLV("HP-Amp Analog Volume",
AK4375_0D_HP_VOLUME_CONTROL, 0, 0x1f, 0, hpg_tlv),
SOC_DOUBLE("DAC Signal Invert Switch", AK4375_07_DAC_MONO_MIXING, 3, 7, 1, 0),
SOC_ENUM("Digital Volume Control", ak4375_ovolcn_enum),
SOC_ENUM("DACL Signal Level", ak4375_mdacl_enum),
SOC_ENUM("DACR Signal Level", ak4375_mdacr_enum),
SOC_ENUM("Charge Pump Mode", ak4375_cpmode_enum),
SOC_ENUM("DAC Digital Filter Mode", ak4375_digfil_enum),
};
static const struct snd_kcontrol_new ak4375_hpl_mixer_controls[] = {
SOC_DAPM_SINGLE("LDACL Switch", AK4375_07_DAC_MONO_MIXING, 0, 1, 0),
SOC_DAPM_SINGLE("RDACL Switch", AK4375_07_DAC_MONO_MIXING, 1, 1, 0),
};
static const struct snd_kcontrol_new ak4375_hpr_mixer_controls[] = {
SOC_DAPM_SINGLE("LDACR Switch", AK4375_07_DAC_MONO_MIXING, 4, 1, 0),
SOC_DAPM_SINGLE("RDACR Switch", AK4375_07_DAC_MONO_MIXING, 5, 1, 0),
};
static int ak4375_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_component_update_bits(component, AK4375_00_POWER_MANAGEMENT1, PMPLL, PMPLL);
snd_soc_component_update_bits(component, AK4375_01_POWER_MANAGEMENT2, PMCP1, PMCP1);
usleep_range(6500, 7000);
snd_soc_component_update_bits(component, AK4375_01_POWER_MANAGEMENT2, PMLDO, PMLDO);
usleep_range(1000, 2000);
break;
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(component, AK4375_01_POWER_MANAGEMENT2, PMCP2, PMCP2);
usleep_range(4500, 5000);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, AK4375_01_POWER_MANAGEMENT2, PMCP2, 0x0);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component, AK4375_01_POWER_MANAGEMENT2, PMLDO, 0x0);
snd_soc_component_update_bits(component, AK4375_01_POWER_MANAGEMENT2, PMCP1, 0x0);
snd_soc_component_update_bits(component, AK4375_00_POWER_MANAGEMENT1, PMPLL, 0x0);
break;
}
return 0;
}
static const struct snd_soc_dapm_widget ak4375_dapm_widgets[] = {
SND_SOC_DAPM_DAC_E("DAC", NULL, AK4375_02_POWER_MANAGEMENT3, 0, 0, ak4375_dac_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_AIF_IN("SDTI", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_OUTPUT("HPL"),
SND_SOC_DAPM_OUTPUT("HPR"),
SND_SOC_DAPM_MIXER("HPR Mixer", AK4375_03_POWER_MANAGEMENT4, 1, 0,
&ak4375_hpr_mixer_controls[0], ARRAY_SIZE(ak4375_hpr_mixer_controls)),
SND_SOC_DAPM_MIXER("HPL Mixer", AK4375_03_POWER_MANAGEMENT4, 0, 0,
&ak4375_hpl_mixer_controls[0], ARRAY_SIZE(ak4375_hpl_mixer_controls)),
};
static const struct snd_soc_dapm_route ak4375_intercon[] = {
{ "DAC", NULL, "SDTI" },
{ "HPL Mixer", "LDACL Switch", "DAC" },
{ "HPL Mixer", "RDACL Switch", "DAC" },
{ "HPR Mixer", "LDACR Switch", "DAC" },
{ "HPR Mixer", "RDACR Switch", "DAC" },
{ "HPL", NULL, "HPL Mixer" },
{ "HPR", NULL, "HPR Mixer" },
};
static int ak4375_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct ak4375_priv *ak4375 = snd_soc_component_get_drvdata(component);
unsigned int freq_in, freq_out;
ak4375->rate = params_rate(params);
if (ak4375->rate <= 96000)
ak4375->pld = 0;
else
ak4375->pld = 1;
freq_in = 32 * ak4375->rate / (ak4375->pld + 1);
if ((ak4375->rate % 8000) == 0)
freq_out = AK4375_PLL_FREQ_OUT_122880000;
else
freq_out = AK4375_PLL_FREQ_OUT_112896000;
return snd_soc_dai_set_pll(dai, 0, 0, freq_in, freq_out);
}
static int ak4375_dai_set_pll(struct snd_soc_dai *dai, int pll_id, int source,
unsigned int freq_in, unsigned int freq_out)
{
struct snd_soc_component *component = dai->component;
struct ak4375_priv *ak4375 = snd_soc_component_get_drvdata(component);
unsigned int mclk, plm, mdiv, div;
u8 cms, fs, cm;
cms = snd_soc_component_read(component, AK4375_05_CLOCK_MODE_SELECT);
fs = cms & ~FS_MASK;
cm = cms & ~CM_MASK;
switch (ak4375->rate) {
case 8000:
fs |= FS_8KHZ;
break;
case 11025:
fs |= FS_11_025KHZ;
break;
case 16000:
fs |= FS_16KHZ;
break;
case 22050:
fs |= FS_22_05KHZ;
break;
case 32000:
fs |= FS_32KHZ;
break;
case 44100:
fs |= FS_44_1KHZ;
break;
case 48000:
fs |= FS_48KHZ;
break;
case 88200:
fs |= FS_88_2KHZ;
break;
case 96000:
fs |= FS_96KHZ;
break;
case 176400:
fs |= FS_176_4KHZ;
break;
case 192000:
fs |= FS_192KHZ;
break;
default:
return -EINVAL;
}
if (ak4375->rate <= 24000) {
cm |= CM_1;
mclk = 512 * ak4375->rate;
mdiv = freq_out / mclk - 1;
div = 0;
} else if (ak4375->rate <= 96000) {
cm |= CM_0;
mclk = 256 * ak4375->rate;
mdiv = freq_out / mclk - 1;
div = 0;
} else {
cm |= CM_3;
mclk = 128 * ak4375->rate;
mdiv = 4;
div = 1;
}
/* Writing both fields in one go seems to make playback choppy on start */
snd_soc_component_update_bits(component, AK4375_05_CLOCK_MODE_SELECT, FS_MASK, fs);
snd_soc_component_update_bits(component, AK4375_05_CLOCK_MODE_SELECT, CM_MASK, cm);
snd_soc_component_write(component, AK4375_0F_PLL_REF_CLK_DIVIDER1,
(ak4375->pld & 0xff00) >> 8);
snd_soc_component_write(component, AK4375_10_PLL_REF_CLK_DIVIDER2,
ak4375->pld & 0x00ff);
plm = freq_out / freq_in - 1;
snd_soc_component_write(component, AK4375_11_PLL_FB_CLK_DIVIDER1, (plm & 0xff00) >> 8);
snd_soc_component_write(component, AK4375_12_PLL_FB_CLK_DIVIDER2, plm & 0x00ff);
snd_soc_component_update_bits(component, AK4375_13_SRC_CLK_SOURCE, DIV, div);
/* SRCCKS bit: force to 1 for SRC PLL source clock */
snd_soc_component_update_bits(component, AK4375_13_SRC_CLK_SOURCE, SRCCKS, SRCCKS);
snd_soc_component_write(component, AK4375_14_DAC_CLK_DIVIDER, mdiv);
dev_dbg(ak4375->dev, "rate=%d mclk=%d f_in=%d f_out=%d PLD=%d PLM=%d MDIV=%d DIV=%d\n",
ak4375->rate, mclk, freq_in, freq_out, ak4375->pld, plm, mdiv, div);
return 0;
}
static int ak4375_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
struct ak4375_priv *ak4375 = snd_soc_component_get_drvdata(component);
u8 val = snd_soc_component_read(component, AK4375_07_DAC_MONO_MIXING);
dev_dbg(ak4375->dev, "mute=%d val=%d\n", mute, val);
if (mute) {
ak4375->mute_save = val & DACMUTE_MASK;
val &= ~DACMUTE_MASK;
} else {
val |= ak4375->mute_save;
}
snd_soc_component_write(component, AK4375_07_DAC_MONO_MIXING, val);
return 0;
}
#define AK4375_RATES (SNDRV_PCM_RATE_8000_48000 |\
SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000)
#define AK4375_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops ak4375_dai_ops = {
.hw_params = ak4375_hw_params,
.mute_stream = ak4375_mute,
.set_pll = ak4375_dai_set_pll,
};
static struct snd_soc_dai_driver ak4375_dai = {
.name = "ak4375-hifi",
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 1,
.channels_max = 2,
.rates = AK4375_RATES,
.rate_min = 8000,
.rate_max = 192000,
.formats = AK4375_FORMATS,
},
.ops = &ak4375_dai_ops,
};
static void ak4375_power_off(struct ak4375_priv *ak4375)
{
gpiod_set_value_cansleep(ak4375->pdn_gpiod, 0);
usleep_range(1000, 2000);
regulator_bulk_disable(ARRAY_SIZE(ak4375->supplies), ak4375->supplies);
}
static int ak4375_power_on(struct ak4375_priv *ak4375)
{
int ret;
ret = regulator_bulk_enable(ARRAY_SIZE(ak4375->supplies), ak4375->supplies);
if (ret < 0) {
dev_err(ak4375->dev, "Failed to enable regulators: %d\n", ret);
return ret;
}
usleep_range(3000, 4000);
gpiod_set_value_cansleep(ak4375->pdn_gpiod, 1);
usleep_range(1000, 2000);
return 0;
}
static int __maybe_unused ak4375_runtime_suspend(struct device *dev)
{
struct ak4375_priv *ak4375 = dev_get_drvdata(dev);
regcache_cache_only(ak4375->regmap, true);
ak4375_power_off(ak4375);
return 0;
}
static int __maybe_unused ak4375_runtime_resume(struct device *dev)
{
struct ak4375_priv *ak4375 = dev_get_drvdata(dev);
int ret;
ret = ak4375_power_on(ak4375);
if (ret < 0)
return ret;
regcache_cache_only(ak4375->regmap, false);
regcache_mark_dirty(ak4375->regmap);
return regcache_sync(ak4375->regmap);
}
static const struct snd_soc_component_driver soc_codec_dev_ak4375 = {
.controls = ak4375_snd_controls,
.num_controls = ARRAY_SIZE(ak4375_snd_controls),
.dapm_widgets = ak4375_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(ak4375_dapm_widgets),
.dapm_routes = ak4375_intercon,
.num_dapm_routes = ARRAY_SIZE(ak4375_intercon),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config ak4375_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = AK4375_24_MODE_CONTROL,
.reg_defaults = ak4375_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(ak4375_reg_defaults),
.cache_type = REGCACHE_RBTREE,
};
static const struct ak4375_drvdata ak4375_drvdata = {
.dai_drv = &ak4375_dai,
.comp_drv = &soc_codec_dev_ak4375,
};
static const struct dev_pm_ops ak4375_pm = {
SET_RUNTIME_PM_OPS(ak4375_runtime_suspend, ak4375_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static int ak4375_i2c_probe(struct i2c_client *i2c)
{
struct ak4375_priv *ak4375;
const struct ak4375_drvdata *drvdata;
unsigned int deviceid;
int ret, i;
ak4375 = devm_kzalloc(&i2c->dev, sizeof(*ak4375), GFP_KERNEL);
if (!ak4375)
return -ENOMEM;
ak4375->regmap = devm_regmap_init_i2c(i2c, &ak4375_regmap);
if (IS_ERR(ak4375->regmap))
return PTR_ERR(ak4375->regmap);
i2c_set_clientdata(i2c, ak4375);
ak4375->dev = &i2c->dev;
drvdata = of_device_get_match_data(&i2c->dev);
for (i = 0; i < ARRAY_SIZE(supply_names); i++)
ak4375->supplies[i].supply = supply_names[i];
ret = devm_regulator_bulk_get(ak4375->dev, ARRAY_SIZE(ak4375->supplies), ak4375->supplies);
if (ret < 0) {
dev_err(ak4375->dev, "Failed to get regulators: %d\n", ret);
return ret;
}
ak4375->pdn_gpiod = devm_gpiod_get_optional(ak4375->dev, "pdn", GPIOD_OUT_LOW);
if (IS_ERR(ak4375->pdn_gpiod))
return dev_err_probe(ak4375->dev, PTR_ERR(ak4375->pdn_gpiod),
"failed to get pdn\n");
ret = ak4375_power_on(ak4375);
if (ret < 0)
return ret;
/* Don't read deviceid from cache */
regcache_cache_bypass(ak4375->regmap, true);
ret = regmap_read(ak4375->regmap, AK4375_15_AUDIO_IF_FORMAT, &deviceid);
if (ret < 0) {
dev_err(ak4375->dev, "unable to read DEVICEID!\n");
return ret;
}
regcache_cache_bypass(ak4375->regmap, false);
deviceid = (deviceid & DEVICEID_MASK) >> 5;
switch (deviceid) {
case DEVICEID_AK4331:
dev_err(ak4375->dev, "found untested AK4331\n");
return -EINVAL;
case DEVICEID_AK4375:
dev_dbg(ak4375->dev, "found AK4375\n");
break;
case DEVICEID_AK4375A:
dev_dbg(ak4375->dev, "found AK4375A\n");
break;
case DEVICEID_AK4376A:
dev_err(ak4375->dev, "found unsupported AK4376/A!\n");
return -EINVAL;
case DEVICEID_AK4377:
dev_err(ak4375->dev, "found unsupported AK4377!\n");
return -EINVAL;
default:
dev_err(ak4375->dev, "unrecognized DEVICEID!\n");
return -EINVAL;
}
pm_runtime_set_active(ak4375->dev);
pm_runtime_enable(ak4375->dev);
ret = devm_snd_soc_register_component(ak4375->dev, drvdata->comp_drv,
drvdata->dai_drv, 1);
if (ret < 0) {
dev_err(ak4375->dev, "Failed to register CODEC: %d\n", ret);
return ret;
}
return 0;
}
static void ak4375_i2c_remove(struct i2c_client *i2c)
{
pm_runtime_disable(&i2c->dev);
}
static const struct of_device_id ak4375_of_match[] = {
{ .compatible = "asahi-kasei,ak4375", .data = &ak4375_drvdata },
{ },
};
MODULE_DEVICE_TABLE(of, ak4375_of_match);
static struct i2c_driver ak4375_i2c_driver = {
.driver = {
.name = "ak4375",
.pm = &ak4375_pm,
.of_match_table = ak4375_of_match,
},
.probe = ak4375_i2c_probe,
.remove = ak4375_i2c_remove,
};
module_i2c_driver(ak4375_i2c_driver);
MODULE_AUTHOR("Vincent Knecht <[email protected]>");
MODULE_DESCRIPTION("ASoC AK4375 DAC driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/ak4375.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8731.c -- WM8731 ALSA SoC Audio driver
*
* Copyright 2005 Openedhand Ltd.
* Copyright 2006-12 Wolfson Microelectronics, plc
*
* Author: Richard Purdie <[email protected]>
*
* Based on wm8753.c by Liam Girdwood
*/
#include <linux/spi/spi.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include "wm8731.h"
static const struct of_device_id wm8731_of_match[] = {
{ .compatible = "wlf,wm8731", },
{ }
};
MODULE_DEVICE_TABLE(of, wm8731_of_match);
static int wm8731_spi_probe(struct spi_device *spi)
{
struct wm8731_priv *wm8731;
int ret;
wm8731 = devm_kzalloc(&spi->dev, sizeof(*wm8731), GFP_KERNEL);
if (wm8731 == NULL)
return -ENOMEM;
spi_set_drvdata(spi, wm8731);
wm8731->regmap = devm_regmap_init_spi(spi, &wm8731_regmap);
if (IS_ERR(wm8731->regmap)) {
ret = PTR_ERR(wm8731->regmap);
dev_err(&spi->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
return wm8731_init(&spi->dev, wm8731);
}
static struct spi_driver wm8731_spi_driver = {
.driver = {
.name = "wm8731",
.of_match_table = wm8731_of_match,
},
.probe = wm8731_spi_probe,
};
module_spi_driver(wm8731_spi_driver);
MODULE_DESCRIPTION("ASoC WM8731 driver - SPI");
MODULE_AUTHOR("Richard Purdie");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8731-spi.c |
// SPDX-License-Identifier: GPL-2.0
/*
* ALSA SoC TLV320AIC31xx CODEC Driver
*
* Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
* Jyri Sarha <[email protected]>
*
* Based on ground work by: Ajit Kulkarni <[email protected]>
*
* The TLV320AIC31xx series of audio codecs are low-power, highly integrated
* high performance codecs which provides a stereo DAC, a mono ADC,
* and mono/stereo Class-D speaker driver.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/gpio/consumer.h>
#include <linux/regulator/consumer.h>
#include <linux/acpi.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/jack.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <dt-bindings/sound/tlv320aic31xx.h>
#include "tlv320aic31xx.h"
static int aic31xx_set_jack(struct snd_soc_component *component,
struct snd_soc_jack *jack, void *data);
static const struct reg_default aic31xx_reg_defaults[] = {
{ AIC31XX_CLKMUX, 0x00 },
{ AIC31XX_PLLPR, 0x11 },
{ AIC31XX_PLLJ, 0x04 },
{ AIC31XX_PLLDMSB, 0x00 },
{ AIC31XX_PLLDLSB, 0x00 },
{ AIC31XX_NDAC, 0x01 },
{ AIC31XX_MDAC, 0x01 },
{ AIC31XX_DOSRMSB, 0x00 },
{ AIC31XX_DOSRLSB, 0x80 },
{ AIC31XX_NADC, 0x01 },
{ AIC31XX_MADC, 0x01 },
{ AIC31XX_AOSR, 0x80 },
{ AIC31XX_IFACE1, 0x00 },
{ AIC31XX_DATA_OFFSET, 0x00 },
{ AIC31XX_IFACE2, 0x00 },
{ AIC31XX_BCLKN, 0x01 },
{ AIC31XX_DACSETUP, 0x14 },
{ AIC31XX_DACMUTE, 0x0c },
{ AIC31XX_LDACVOL, 0x00 },
{ AIC31XX_RDACVOL, 0x00 },
{ AIC31XX_ADCSETUP, 0x00 },
{ AIC31XX_ADCFGA, 0x80 },
{ AIC31XX_ADCVOL, 0x00 },
{ AIC31XX_HPDRIVER, 0x04 },
{ AIC31XX_SPKAMP, 0x06 },
{ AIC31XX_DACMIXERROUTE, 0x00 },
{ AIC31XX_LANALOGHPL, 0x7f },
{ AIC31XX_RANALOGHPR, 0x7f },
{ AIC31XX_LANALOGSPL, 0x7f },
{ AIC31XX_RANALOGSPR, 0x7f },
{ AIC31XX_HPLGAIN, 0x02 },
{ AIC31XX_HPRGAIN, 0x02 },
{ AIC31XX_SPLGAIN, 0x00 },
{ AIC31XX_SPRGAIN, 0x00 },
{ AIC31XX_MICBIAS, 0x00 },
{ AIC31XX_MICPGA, 0x80 },
{ AIC31XX_MICPGAPI, 0x00 },
{ AIC31XX_MICPGAMI, 0x00 },
};
static bool aic31xx_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case AIC31XX_PAGECTL: /* regmap implementation requires this */
case AIC31XX_RESET: /* always clears after write */
case AIC31XX_OT_FLAG:
case AIC31XX_ADCFLAG:
case AIC31XX_DACFLAG1:
case AIC31XX_DACFLAG2:
case AIC31XX_OFFLAG: /* Sticky interrupt flags */
case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */
case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */
case AIC31XX_INTRDACFLAG2:
case AIC31XX_INTRADCFLAG2:
case AIC31XX_HSDETECT:
return true;
}
return false;
}
static bool aic31xx_writeable(struct device *dev, unsigned int reg)
{
switch (reg) {
case AIC31XX_OT_FLAG:
case AIC31XX_ADCFLAG:
case AIC31XX_DACFLAG1:
case AIC31XX_DACFLAG2:
case AIC31XX_OFFLAG: /* Sticky interrupt flags */
case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */
case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */
case AIC31XX_INTRDACFLAG2:
case AIC31XX_INTRADCFLAG2:
return false;
}
return true;
}
static const struct regmap_range_cfg aic31xx_ranges[] = {
{
.range_min = 0,
.range_max = 12 * 128,
.selector_reg = AIC31XX_PAGECTL,
.selector_mask = 0xff,
.selector_shift = 0,
.window_start = 0,
.window_len = 128,
},
};
static const struct regmap_config aic31xx_i2c_regmap = {
.reg_bits = 8,
.val_bits = 8,
.writeable_reg = aic31xx_writeable,
.volatile_reg = aic31xx_volatile,
.reg_defaults = aic31xx_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(aic31xx_reg_defaults),
.cache_type = REGCACHE_RBTREE,
.ranges = aic31xx_ranges,
.num_ranges = ARRAY_SIZE(aic31xx_ranges),
.max_register = 12 * 128,
};
static const char * const aic31xx_supply_names[] = {
"HPVDD",
"SPRVDD",
"SPLVDD",
"AVDD",
"IOVDD",
"DVDD",
};
#define AIC31XX_NUM_SUPPLIES ARRAY_SIZE(aic31xx_supply_names)
struct aic31xx_disable_nb {
struct notifier_block nb;
struct aic31xx_priv *aic31xx;
};
struct aic31xx_priv {
struct snd_soc_component *component;
u8 i2c_regs_status;
struct device *dev;
struct regmap *regmap;
enum aic31xx_type codec_type;
struct gpio_desc *gpio_reset;
int micbias_vg;
struct aic31xx_pdata pdata;
struct regulator_bulk_data supplies[AIC31XX_NUM_SUPPLIES];
struct aic31xx_disable_nb disable_nb[AIC31XX_NUM_SUPPLIES];
struct snd_soc_jack *jack;
u32 sysclk_id;
unsigned int sysclk;
u8 p_div;
int rate_div_line;
bool master_dapm_route_applied;
int irq;
u8 ocmv; /* output common-mode voltage */
};
struct aic31xx_rate_divs {
u32 mclk_p;
u32 rate;
u8 pll_r;
u8 pll_j;
u16 pll_d;
u16 dosr;
u8 ndac;
u8 mdac;
u8 aosr;
u8 nadc;
u8 madc;
};
/* ADC dividers can be disabled by configuring them to 0 */
static const struct aic31xx_rate_divs aic31xx_divs[] = {
/* mclk/p rate pll: r j d dosr ndac mdac aors nadc madc */
/* 8k rate */
{ 512000, 8000, 4, 48, 0, 128, 48, 2, 128, 48, 2},
{12000000, 8000, 1, 8, 1920, 128, 48, 2, 128, 48, 2},
{12000000, 8000, 1, 8, 1920, 128, 32, 3, 128, 32, 3},
{12500000, 8000, 1, 7, 8643, 128, 48, 2, 128, 48, 2},
/* 11.025k rate */
{ 705600, 11025, 3, 48, 0, 128, 24, 3, 128, 24, 3},
{12000000, 11025, 1, 7, 5264, 128, 32, 2, 128, 32, 2},
{12000000, 11025, 1, 8, 4672, 128, 24, 3, 128, 24, 3},
{12500000, 11025, 1, 7, 2253, 128, 32, 2, 128, 32, 2},
/* 16k rate */
{ 512000, 16000, 4, 48, 0, 128, 16, 3, 128, 16, 3},
{ 1024000, 16000, 2, 48, 0, 128, 16, 3, 128, 16, 3},
{12000000, 16000, 1, 8, 1920, 128, 24, 2, 128, 24, 2},
{12000000, 16000, 1, 8, 1920, 128, 16, 3, 128, 16, 3},
{12500000, 16000, 1, 7, 8643, 128, 24, 2, 128, 24, 2},
/* 22.05k rate */
{ 705600, 22050, 4, 36, 0, 128, 12, 3, 128, 12, 3},
{ 1411200, 22050, 2, 36, 0, 128, 12, 3, 128, 12, 3},
{12000000, 22050, 1, 7, 5264, 128, 16, 2, 128, 16, 2},
{12000000, 22050, 1, 8, 4672, 128, 12, 3, 128, 12, 3},
{12500000, 22050, 1, 7, 2253, 128, 16, 2, 128, 16, 2},
/* 32k rate */
{ 1024000, 32000, 2, 48, 0, 128, 12, 2, 128, 12, 2},
{ 2048000, 32000, 1, 48, 0, 128, 12, 2, 128, 12, 2},
{12000000, 32000, 1, 8, 1920, 128, 12, 2, 128, 12, 2},
{12000000, 32000, 1, 8, 1920, 128, 8, 3, 128, 8, 3},
{12500000, 32000, 1, 7, 8643, 128, 12, 2, 128, 12, 2},
/* 44.1k rate */
{ 1411200, 44100, 2, 32, 0, 128, 8, 2, 128, 8, 2},
{ 2822400, 44100, 1, 32, 0, 128, 8, 2, 128, 8, 2},
{12000000, 44100, 1, 7, 5264, 128, 8, 2, 128, 8, 2},
{12000000, 44100, 1, 8, 4672, 128, 6, 3, 128, 6, 3},
{12500000, 44100, 1, 7, 2253, 128, 8, 2, 128, 8, 2},
/* 48k rate */
{ 1536000, 48000, 2, 32, 0, 128, 8, 2, 128, 8, 2},
{ 3072000, 48000, 1, 32, 0, 128, 8, 2, 128, 8, 2},
{12000000, 48000, 1, 8, 1920, 128, 8, 2, 128, 8, 2},
{12000000, 48000, 1, 7, 6800, 96, 5, 4, 96, 5, 4},
{12500000, 48000, 1, 7, 8643, 128, 8, 2, 128, 8, 2},
/* 88.2k rate */
{ 2822400, 88200, 2, 16, 0, 64, 8, 2, 64, 8, 2},
{ 5644800, 88200, 1, 16, 0, 64, 8, 2, 64, 8, 2},
{12000000, 88200, 1, 7, 5264, 64, 8, 2, 64, 8, 2},
{12000000, 88200, 1, 8, 4672, 64, 6, 3, 64, 6, 3},
{12500000, 88200, 1, 7, 2253, 64, 8, 2, 64, 8, 2},
/* 96k rate */
{ 3072000, 96000, 2, 16, 0, 64, 8, 2, 64, 8, 2},
{ 6144000, 96000, 1, 16, 0, 64, 8, 2, 64, 8, 2},
{12000000, 96000, 1, 8, 1920, 64, 8, 2, 64, 8, 2},
{12000000, 96000, 1, 7, 6800, 48, 5, 4, 48, 5, 4},
{12500000, 96000, 1, 7, 8643, 64, 8, 2, 64, 8, 2},
/* 176.4k rate */
{ 5644800, 176400, 2, 8, 0, 32, 8, 2, 32, 8, 2},
{11289600, 176400, 1, 8, 0, 32, 8, 2, 32, 8, 2},
{12000000, 176400, 1, 7, 5264, 32, 8, 2, 32, 8, 2},
{12000000, 176400, 1, 8, 4672, 32, 6, 3, 32, 6, 3},
{12500000, 176400, 1, 7, 2253, 32, 8, 2, 32, 8, 2},
/* 192k rate */
{ 6144000, 192000, 2, 8, 0, 32, 8, 2, 32, 8, 2},
{12288000, 192000, 1, 8, 0, 32, 8, 2, 32, 8, 2},
{12000000, 192000, 1, 8, 1920, 32, 8, 2, 32, 8, 2},
{12000000, 192000, 1, 7, 6800, 24, 5, 4, 24, 5, 4},
{12500000, 192000, 1, 7, 8643, 32, 8, 2, 32, 8, 2},
};
static const char * const ldac_in_text[] = {
"Off", "Left Data", "Right Data", "Mono"
};
static const char * const rdac_in_text[] = {
"Off", "Right Data", "Left Data", "Mono"
};
static SOC_ENUM_SINGLE_DECL(ldac_in_enum, AIC31XX_DACSETUP, 4, ldac_in_text);
static SOC_ENUM_SINGLE_DECL(rdac_in_enum, AIC31XX_DACSETUP, 2, rdac_in_text);
static const char * const mic_select_text[] = {
"Off", "FFR 10 Ohm", "FFR 20 Ohm", "FFR 40 Ohm"
};
static SOC_ENUM_SINGLE_DECL(mic1lp_p_enum, AIC31XX_MICPGAPI, 6,
mic_select_text);
static SOC_ENUM_SINGLE_DECL(mic1rp_p_enum, AIC31XX_MICPGAPI, 4,
mic_select_text);
static SOC_ENUM_SINGLE_DECL(mic1lm_p_enum, AIC31XX_MICPGAPI, 2,
mic_select_text);
static SOC_ENUM_SINGLE_DECL(mic1lm_m_enum, AIC31XX_MICPGAMI, 4,
mic_select_text);
static const char * const hp_poweron_time_text[] = {
"0us", "15.3us", "153us", "1.53ms", "15.3ms", "76.2ms",
"153ms", "304ms", "610ms", "1.22s", "3.04s", "6.1s" };
static SOC_ENUM_SINGLE_DECL(hp_poweron_time_enum, AIC31XX_HPPOP, 3,
hp_poweron_time_text);
static const char * const hp_rampup_step_text[] = {
"0ms", "0.98ms", "1.95ms", "3.9ms" };
static SOC_ENUM_SINGLE_DECL(hp_rampup_step_enum, AIC31XX_HPPOP, 1,
hp_rampup_step_text);
static const char * const vol_soft_step_mode_text[] = {
"fast", "slow", "disabled" };
static SOC_ENUM_SINGLE_DECL(vol_soft_step_mode_enum, AIC31XX_DACSETUP, 0,
vol_soft_step_mode_text);
static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6350, 50, 0);
static const DECLARE_TLV_DB_SCALE(adc_fgain_tlv, 0, 10, 0);
static const DECLARE_TLV_DB_SCALE(adc_cgain_tlv, -2000, 50, 0);
static const DECLARE_TLV_DB_SCALE(mic_pga_tlv, 0, 50, 0);
static const DECLARE_TLV_DB_SCALE(hp_drv_tlv, 0, 100, 0);
static const DECLARE_TLV_DB_SCALE(class_D_drv_tlv, 600, 600, 0);
static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -6350, 50, 0);
static const DECLARE_TLV_DB_SCALE(sp_vol_tlv, -6350, 50, 0);
/*
* controls to be exported to the user space
*/
static const struct snd_kcontrol_new common31xx_snd_controls[] = {
SOC_DOUBLE_R_S_TLV("DAC Playback Volume", AIC31XX_LDACVOL,
AIC31XX_RDACVOL, 0, -127, 48, 7, 0, dac_vol_tlv),
SOC_DOUBLE_R("HP Driver Playback Switch", AIC31XX_HPLGAIN,
AIC31XX_HPRGAIN, 2, 1, 0),
SOC_DOUBLE_R_TLV("HP Driver Playback Volume", AIC31XX_HPLGAIN,
AIC31XX_HPRGAIN, 3, 0x09, 0, hp_drv_tlv),
SOC_DOUBLE_R_TLV("HP Analog Playback Volume", AIC31XX_LANALOGHPL,
AIC31XX_RANALOGHPR, 0, 0x7F, 1, hp_vol_tlv),
/* HP de-pop control: apply power not immediately but via ramp
* function with these psarameters. Note that power up sequence
* has to wait for this to complete; this is implemented by
* polling HP driver status in aic31xx_dapm_power_event()
*/
SOC_ENUM("HP Output Driver Power-On time", hp_poweron_time_enum),
SOC_ENUM("HP Output Driver Ramp-up step", hp_rampup_step_enum),
SOC_ENUM("Volume Soft Stepping", vol_soft_step_mode_enum),
};
static const struct snd_kcontrol_new aic31xx_snd_controls[] = {
SOC_SINGLE_TLV("ADC Fine Capture Volume", AIC31XX_ADCFGA, 4, 4, 1,
adc_fgain_tlv),
SOC_SINGLE("ADC Capture Switch", AIC31XX_ADCFGA, 7, 1, 1),
SOC_DOUBLE_R_S_TLV("ADC Capture Volume", AIC31XX_ADCVOL, AIC31XX_ADCVOL,
0, -24, 40, 6, 0, adc_cgain_tlv),
SOC_SINGLE_TLV("Mic PGA Capture Volume", AIC31XX_MICPGA, 0,
119, 0, mic_pga_tlv),
};
static const struct snd_kcontrol_new aic311x_snd_controls[] = {
SOC_DOUBLE_R("Speaker Driver Playback Switch", AIC31XX_SPLGAIN,
AIC31XX_SPRGAIN, 2, 1, 0),
SOC_DOUBLE_R_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN,
AIC31XX_SPRGAIN, 3, 3, 0, class_D_drv_tlv),
SOC_DOUBLE_R_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL,
AIC31XX_RANALOGSPR, 0, 0x7F, 1, sp_vol_tlv),
};
static const struct snd_kcontrol_new aic310x_snd_controls[] = {
SOC_SINGLE("Speaker Driver Playback Switch", AIC31XX_SPLGAIN,
2, 1, 0),
SOC_SINGLE_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN,
3, 3, 0, class_D_drv_tlv),
SOC_SINGLE_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL,
0, 0x7F, 1, sp_vol_tlv),
};
static const struct snd_kcontrol_new ldac_in_control =
SOC_DAPM_ENUM("DAC Left Input", ldac_in_enum);
static const struct snd_kcontrol_new rdac_in_control =
SOC_DAPM_ENUM("DAC Right Input", rdac_in_enum);
static int aic31xx_wait_bits(struct aic31xx_priv *aic31xx, unsigned int reg,
unsigned int mask, unsigned int wbits, int sleep,
int count)
{
unsigned int bits;
int counter = count;
int ret = regmap_read(aic31xx->regmap, reg, &bits);
while ((bits & mask) != wbits && counter && !ret) {
usleep_range(sleep, sleep * 2);
ret = regmap_read(aic31xx->regmap, reg, &bits);
counter--;
}
if ((bits & mask) != wbits) {
dev_err(aic31xx->dev,
"%s: Failed! 0x%x was 0x%x expected 0x%x (%d, 0x%x, %d us)\n",
__func__, reg, bits, wbits, ret, mask,
(count - counter) * sleep);
ret = -1;
}
return ret;
}
#define WIDGET_BIT(reg, shift) (((shift) << 8) | (reg))
static int aic31xx_dapm_power_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
unsigned int reg = AIC31XX_DACFLAG1;
unsigned int mask;
unsigned int timeout = 500 * USEC_PER_MSEC;
switch (WIDGET_BIT(w->reg, w->shift)) {
case WIDGET_BIT(AIC31XX_DACSETUP, 7):
mask = AIC31XX_LDACPWRSTATUS_MASK;
break;
case WIDGET_BIT(AIC31XX_DACSETUP, 6):
mask = AIC31XX_RDACPWRSTATUS_MASK;
break;
case WIDGET_BIT(AIC31XX_HPDRIVER, 7):
mask = AIC31XX_HPLDRVPWRSTATUS_MASK;
if (event == SND_SOC_DAPM_POST_PMU)
timeout = 7 * USEC_PER_SEC;
break;
case WIDGET_BIT(AIC31XX_HPDRIVER, 6):
mask = AIC31XX_HPRDRVPWRSTATUS_MASK;
if (event == SND_SOC_DAPM_POST_PMU)
timeout = 7 * USEC_PER_SEC;
break;
case WIDGET_BIT(AIC31XX_SPKAMP, 7):
mask = AIC31XX_SPLDRVPWRSTATUS_MASK;
break;
case WIDGET_BIT(AIC31XX_SPKAMP, 6):
mask = AIC31XX_SPRDRVPWRSTATUS_MASK;
break;
case WIDGET_BIT(AIC31XX_ADCSETUP, 7):
mask = AIC31XX_ADCPWRSTATUS_MASK;
reg = AIC31XX_ADCFLAG;
break;
default:
dev_err(component->dev, "Unknown widget '%s' calling %s\n",
w->name, __func__);
return -EINVAL;
}
switch (event) {
case SND_SOC_DAPM_POST_PMU:
return aic31xx_wait_bits(aic31xx, reg, mask, mask,
5000, timeout / 5000);
case SND_SOC_DAPM_POST_PMD:
return aic31xx_wait_bits(aic31xx, reg, mask, 0,
5000, timeout / 5000);
default:
dev_dbg(component->dev,
"Unhandled dapm widget event %d from %s\n",
event, w->name);
}
return 0;
}
static const struct snd_kcontrol_new aic31xx_left_output_switches[] = {
SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0),
SOC_DAPM_SINGLE("From MIC1LP", AIC31XX_DACMIXERROUTE, 5, 1, 0),
SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 4, 1, 0),
};
static const struct snd_kcontrol_new aic31xx_right_output_switches[] = {
SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0),
SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 1, 1, 0),
};
static const struct snd_kcontrol_new dac31xx_left_output_switches[] = {
SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0),
SOC_DAPM_SINGLE("From AIN1", AIC31XX_DACMIXERROUTE, 5, 1, 0),
SOC_DAPM_SINGLE("From AIN2", AIC31XX_DACMIXERROUTE, 4, 1, 0),
};
static const struct snd_kcontrol_new dac31xx_right_output_switches[] = {
SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0),
SOC_DAPM_SINGLE("From AIN2", AIC31XX_DACMIXERROUTE, 1, 1, 0),
};
static const struct snd_kcontrol_new p_term_mic1lp =
SOC_DAPM_ENUM("MIC1LP P-Terminal", mic1lp_p_enum);
static const struct snd_kcontrol_new p_term_mic1rp =
SOC_DAPM_ENUM("MIC1RP P-Terminal", mic1rp_p_enum);
static const struct snd_kcontrol_new p_term_mic1lm =
SOC_DAPM_ENUM("MIC1LM P-Terminal", mic1lm_p_enum);
static const struct snd_kcontrol_new m_term_mic1lm =
SOC_DAPM_ENUM("MIC1LM M-Terminal", mic1lm_m_enum);
static const struct snd_kcontrol_new aic31xx_dapm_hpl_switch =
SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGHPL, 7, 1, 0);
static const struct snd_kcontrol_new aic31xx_dapm_hpr_switch =
SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGHPR, 7, 1, 0);
static const struct snd_kcontrol_new aic31xx_dapm_spl_switch =
SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGSPL, 7, 1, 0);
static const struct snd_kcontrol_new aic31xx_dapm_spr_switch =
SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGSPR, 7, 1, 0);
static int mic_bias_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
/* change mic bias voltage to user defined */
snd_soc_component_update_bits(component, AIC31XX_MICBIAS,
AIC31XX_MICBIAS_MASK,
aic31xx->micbias_vg <<
AIC31XX_MICBIAS_SHIFT);
dev_dbg(component->dev, "%s: turned on\n", __func__);
break;
case SND_SOC_DAPM_PRE_PMD:
/* turn mic bias off */
snd_soc_component_update_bits(component, AIC31XX_MICBIAS,
AIC31XX_MICBIAS_MASK, 0);
dev_dbg(component->dev, "%s: turned off\n", __func__);
break;
}
return 0;
}
static const struct snd_soc_dapm_widget common31xx_dapm_widgets[] = {
SND_SOC_DAPM_AIF_IN("AIF IN", "Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_MUX("DAC Left Input",
SND_SOC_NOPM, 0, 0, &ldac_in_control),
SND_SOC_DAPM_MUX("DAC Right Input",
SND_SOC_NOPM, 0, 0, &rdac_in_control),
/* DACs */
SND_SOC_DAPM_DAC_E("DAC Left", "Left Playback",
AIC31XX_DACSETUP, 7, 0, aic31xx_dapm_power_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_DAC_E("DAC Right", "Right Playback",
AIC31XX_DACSETUP, 6, 0, aic31xx_dapm_power_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
/* HP */
SND_SOC_DAPM_SWITCH("HP Left", SND_SOC_NOPM, 0, 0,
&aic31xx_dapm_hpl_switch),
SND_SOC_DAPM_SWITCH("HP Right", SND_SOC_NOPM, 0, 0,
&aic31xx_dapm_hpr_switch),
/* Output drivers */
SND_SOC_DAPM_OUT_DRV_E("HPL Driver", AIC31XX_HPDRIVER, 7, 0,
NULL, 0, aic31xx_dapm_power_event,
SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_OUT_DRV_E("HPR Driver", AIC31XX_HPDRIVER, 6, 0,
NULL, 0, aic31xx_dapm_power_event,
SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
/* Mic Bias */
SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, mic_bias_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
/* Keep BCLK/WCLK enabled even if DAC/ADC is powered down */
SND_SOC_DAPM_SUPPLY("Activate I2S clocks", AIC31XX_IFACE2, 2, 0,
NULL, 0),
/* Outputs */
SND_SOC_DAPM_OUTPUT("HPL"),
SND_SOC_DAPM_OUTPUT("HPR"),
};
static const struct snd_soc_dapm_widget dac31xx_dapm_widgets[] = {
/* Inputs */
SND_SOC_DAPM_INPUT("AIN1"),
SND_SOC_DAPM_INPUT("AIN2"),
/* Output Mixers */
SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0,
dac31xx_left_output_switches,
ARRAY_SIZE(dac31xx_left_output_switches)),
SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0,
dac31xx_right_output_switches,
ARRAY_SIZE(dac31xx_right_output_switches)),
};
static const struct snd_soc_dapm_widget aic31xx_dapm_widgets[] = {
/* Inputs */
SND_SOC_DAPM_INPUT("MIC1LP"),
SND_SOC_DAPM_INPUT("MIC1RP"),
SND_SOC_DAPM_INPUT("MIC1LM"),
/* Input Selection to MIC_PGA */
SND_SOC_DAPM_MUX("MIC1LP P-Terminal", SND_SOC_NOPM, 0, 0,
&p_term_mic1lp),
SND_SOC_DAPM_MUX("MIC1RP P-Terminal", SND_SOC_NOPM, 0, 0,
&p_term_mic1rp),
SND_SOC_DAPM_MUX("MIC1LM P-Terminal", SND_SOC_NOPM, 0, 0,
&p_term_mic1lm),
/* ADC */
SND_SOC_DAPM_ADC_E("ADC", "Capture", AIC31XX_ADCSETUP, 7, 0,
aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("MIC1LM M-Terminal", SND_SOC_NOPM, 0, 0,
&m_term_mic1lm),
/* Enabling & Disabling MIC Gain Ctl */
SND_SOC_DAPM_PGA("MIC_GAIN_CTL", AIC31XX_MICPGA,
7, 1, NULL, 0),
/* Output Mixers */
SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0,
aic31xx_left_output_switches,
ARRAY_SIZE(aic31xx_left_output_switches)),
SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0,
aic31xx_right_output_switches,
ARRAY_SIZE(aic31xx_right_output_switches)),
SND_SOC_DAPM_AIF_OUT("AIF OUT", "Capture", 0, SND_SOC_NOPM, 0, 0),
};
static const struct snd_soc_dapm_widget aic311x_dapm_widgets[] = {
/* AIC3111 and AIC3110 have stereo class-D amplifier */
SND_SOC_DAPM_OUT_DRV_E("SPL ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0,
aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_OUT_DRV_E("SPR ClassD", AIC31XX_SPKAMP, 6, 0, NULL, 0,
aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SWITCH("Speaker Left", SND_SOC_NOPM, 0, 0,
&aic31xx_dapm_spl_switch),
SND_SOC_DAPM_SWITCH("Speaker Right", SND_SOC_NOPM, 0, 0,
&aic31xx_dapm_spr_switch),
SND_SOC_DAPM_OUTPUT("SPL"),
SND_SOC_DAPM_OUTPUT("SPR"),
};
/* AIC3100 and AIC3120 have only mono class-D amplifier */
static const struct snd_soc_dapm_widget aic310x_dapm_widgets[] = {
SND_SOC_DAPM_OUT_DRV_E("SPK ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0,
aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SWITCH("Speaker", SND_SOC_NOPM, 0, 0,
&aic31xx_dapm_spl_switch),
SND_SOC_DAPM_OUTPUT("SPK"),
};
static const struct snd_soc_dapm_route
common31xx_audio_map[] = {
/* DAC Input Routing */
{"DAC Left Input", "Left Data", "AIF IN"},
{"DAC Left Input", "Right Data", "AIF IN"},
{"DAC Left Input", "Mono", "AIF IN"},
{"DAC Right Input", "Left Data", "AIF IN"},
{"DAC Right Input", "Right Data", "AIF IN"},
{"DAC Right Input", "Mono", "AIF IN"},
{"DAC Left", NULL, "DAC Left Input"},
{"DAC Right", NULL, "DAC Right Input"},
/* HPL path */
{"HP Left", "Switch", "Output Left"},
{"HPL Driver", NULL, "HP Left"},
{"HPL", NULL, "HPL Driver"},
/* HPR path */
{"HP Right", "Switch", "Output Right"},
{"HPR Driver", NULL, "HP Right"},
{"HPR", NULL, "HPR Driver"},
};
static const struct snd_soc_dapm_route
dac31xx_audio_map[] = {
/* Left Output */
{"Output Left", "From Left DAC", "DAC Left"},
{"Output Left", "From AIN1", "AIN1"},
{"Output Left", "From AIN2", "AIN2"},
/* Right Output */
{"Output Right", "From Right DAC", "DAC Right"},
{"Output Right", "From AIN2", "AIN2"},
};
static const struct snd_soc_dapm_route
aic31xx_audio_map[] = {
/* Mic input */
{"MIC1LP P-Terminal", "FFR 10 Ohm", "MIC1LP"},
{"MIC1LP P-Terminal", "FFR 20 Ohm", "MIC1LP"},
{"MIC1LP P-Terminal", "FFR 40 Ohm", "MIC1LP"},
{"MIC1RP P-Terminal", "FFR 10 Ohm", "MIC1RP"},
{"MIC1RP P-Terminal", "FFR 20 Ohm", "MIC1RP"},
{"MIC1RP P-Terminal", "FFR 40 Ohm", "MIC1RP"},
{"MIC1LM P-Terminal", "FFR 10 Ohm", "MIC1LM"},
{"MIC1LM P-Terminal", "FFR 20 Ohm", "MIC1LM"},
{"MIC1LM P-Terminal", "FFR 40 Ohm", "MIC1LM"},
{"MIC1LM M-Terminal", "FFR 10 Ohm", "MIC1LM"},
{"MIC1LM M-Terminal", "FFR 20 Ohm", "MIC1LM"},
{"MIC1LM M-Terminal", "FFR 40 Ohm", "MIC1LM"},
{"MIC_GAIN_CTL", NULL, "MIC1LP P-Terminal"},
{"MIC_GAIN_CTL", NULL, "MIC1RP P-Terminal"},
{"MIC_GAIN_CTL", NULL, "MIC1LM P-Terminal"},
{"MIC_GAIN_CTL", NULL, "MIC1LM M-Terminal"},
{"ADC", NULL, "MIC_GAIN_CTL"},
{"AIF OUT", NULL, "ADC"},
/* Left Output */
{"Output Left", "From Left DAC", "DAC Left"},
{"Output Left", "From MIC1LP", "MIC1LP"},
{"Output Left", "From MIC1RP", "MIC1RP"},
/* Right Output */
{"Output Right", "From Right DAC", "DAC Right"},
{"Output Right", "From MIC1RP", "MIC1RP"},
};
static const struct snd_soc_dapm_route
aic311x_audio_map[] = {
/* SP L path */
{"Speaker Left", "Switch", "Output Left"},
{"SPL ClassD", NULL, "Speaker Left"},
{"SPL", NULL, "SPL ClassD"},
/* SP R path */
{"Speaker Right", "Switch", "Output Right"},
{"SPR ClassD", NULL, "Speaker Right"},
{"SPR", NULL, "SPR ClassD"},
};
static const struct snd_soc_dapm_route
aic310x_audio_map[] = {
/* SP L path */
{"Speaker", "Switch", "Output Left"},
{"SPK ClassD", NULL, "Speaker"},
{"SPK", NULL, "SPK ClassD"},
};
/*
* Always connected DAPM routes for codec clock master modes.
* If the codec is the master on the I2S bus, we need to power up components
* to have valid DAC_CLK.
*
* In order to have the I2S clocks on the bus either the DACs/ADC need to be
* enabled, or the P0/R29/D2 (Keep bclk/wclk in power down) need to be set.
*
* Otherwise the codec will not generate clocks on the bus.
*/
static const struct snd_soc_dapm_route
common31xx_cm_audio_map[] = {
{"HPL", NULL, "AIF IN"},
{"HPR", NULL, "AIF IN"},
{"AIF IN", NULL, "Activate I2S clocks"},
};
static const struct snd_soc_dapm_route
aic31xx_cm_audio_map[] = {
{"AIF OUT", NULL, "MIC1LP"},
{"AIF OUT", NULL, "MIC1RP"},
{"AIF OUT", NULL, "MIC1LM"},
{"AIF OUT", NULL, "Activate I2S clocks"},
};
static int aic31xx_add_controls(struct snd_soc_component *component)
{
int ret = 0;
struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
if (!(aic31xx->codec_type & DAC31XX_BIT))
ret = snd_soc_add_component_controls(
component, aic31xx_snd_controls,
ARRAY_SIZE(aic31xx_snd_controls));
if (ret)
return ret;
if (aic31xx->codec_type & AIC31XX_STEREO_CLASS_D_BIT)
ret = snd_soc_add_component_controls(
component, aic311x_snd_controls,
ARRAY_SIZE(aic311x_snd_controls));
else
ret = snd_soc_add_component_controls(
component, aic310x_snd_controls,
ARRAY_SIZE(aic310x_snd_controls));
return ret;
}
static int aic31xx_add_widgets(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
int ret = 0;
if (aic31xx->codec_type & DAC31XX_BIT) {
ret = snd_soc_dapm_new_controls(
dapm, dac31xx_dapm_widgets,
ARRAY_SIZE(dac31xx_dapm_widgets));
if (ret)
return ret;
ret = snd_soc_dapm_add_routes(dapm, dac31xx_audio_map,
ARRAY_SIZE(dac31xx_audio_map));
if (ret)
return ret;
} else {
ret = snd_soc_dapm_new_controls(
dapm, aic31xx_dapm_widgets,
ARRAY_SIZE(aic31xx_dapm_widgets));
if (ret)
return ret;
ret = snd_soc_dapm_add_routes(dapm, aic31xx_audio_map,
ARRAY_SIZE(aic31xx_audio_map));
if (ret)
return ret;
}
if (aic31xx->codec_type & AIC31XX_STEREO_CLASS_D_BIT) {
ret = snd_soc_dapm_new_controls(
dapm, aic311x_dapm_widgets,
ARRAY_SIZE(aic311x_dapm_widgets));
if (ret)
return ret;
ret = snd_soc_dapm_add_routes(dapm, aic311x_audio_map,
ARRAY_SIZE(aic311x_audio_map));
if (ret)
return ret;
} else {
ret = snd_soc_dapm_new_controls(
dapm, aic310x_dapm_widgets,
ARRAY_SIZE(aic310x_dapm_widgets));
if (ret)
return ret;
ret = snd_soc_dapm_add_routes(dapm, aic310x_audio_map,
ARRAY_SIZE(aic310x_audio_map));
if (ret)
return ret;
}
return 0;
}
static int aic31xx_setup_pll(struct snd_soc_component *component,
struct snd_pcm_hw_params *params)
{
struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
int bclk_score = snd_soc_params_to_frame_size(params);
int mclk_p;
int bclk_n = 0;
int match = -1;
int i;
if (!aic31xx->sysclk || !aic31xx->p_div) {
dev_err(component->dev, "Master clock not supplied\n");
return -EINVAL;
}
mclk_p = aic31xx->sysclk / aic31xx->p_div;
/* Use PLL as CODEC_CLKIN and DAC_CLK as BDIV_CLKIN */
snd_soc_component_update_bits(component, AIC31XX_CLKMUX,
AIC31XX_CODEC_CLKIN_MASK, AIC31XX_CODEC_CLKIN_PLL);
snd_soc_component_update_bits(component, AIC31XX_IFACE2,
AIC31XX_BDIVCLK_MASK, AIC31XX_DAC2BCLK);
for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) {
if (aic31xx_divs[i].rate == params_rate(params) &&
aic31xx_divs[i].mclk_p == mclk_p) {
int s = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) %
snd_soc_params_to_frame_size(params);
int bn = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) /
snd_soc_params_to_frame_size(params);
if (s < bclk_score && bn > 0) {
match = i;
bclk_n = bn;
bclk_score = s;
}
}
}
if (match == -1) {
dev_err(component->dev,
"%s: Sample rate (%u) and format not supported\n",
__func__, params_rate(params));
/* See bellow for details how fix this. */
return -EINVAL;
}
if (bclk_score != 0) {
dev_warn(component->dev, "Can not produce exact bitclock");
/* This is fine if using dsp format, but if using i2s
there may be trouble. To fix the issue edit the
aic31xx_divs table for your mclk and sample
rate. Details can be found from:
https://www.ti.com/lit/ds/symlink/tlv320aic3100.pdf
Section: 5.6 CLOCK Generation and PLL
*/
}
i = match;
/* PLL configuration */
snd_soc_component_update_bits(component, AIC31XX_PLLPR, AIC31XX_PLL_MASK,
(aic31xx->p_div << 4) | aic31xx_divs[i].pll_r);
snd_soc_component_write(component, AIC31XX_PLLJ, aic31xx_divs[i].pll_j);
snd_soc_component_write(component, AIC31XX_PLLDMSB,
aic31xx_divs[i].pll_d >> 8);
snd_soc_component_write(component, AIC31XX_PLLDLSB,
aic31xx_divs[i].pll_d & 0xff);
/* DAC dividers configuration */
snd_soc_component_update_bits(component, AIC31XX_NDAC, AIC31XX_PLL_MASK,
aic31xx_divs[i].ndac);
snd_soc_component_update_bits(component, AIC31XX_MDAC, AIC31XX_PLL_MASK,
aic31xx_divs[i].mdac);
snd_soc_component_write(component, AIC31XX_DOSRMSB, aic31xx_divs[i].dosr >> 8);
snd_soc_component_write(component, AIC31XX_DOSRLSB, aic31xx_divs[i].dosr & 0xff);
/* ADC dividers configuration. Write reset value 1 if not used. */
snd_soc_component_update_bits(component, AIC31XX_NADC, AIC31XX_PLL_MASK,
aic31xx_divs[i].nadc ? aic31xx_divs[i].nadc : 1);
snd_soc_component_update_bits(component, AIC31XX_MADC, AIC31XX_PLL_MASK,
aic31xx_divs[i].madc ? aic31xx_divs[i].madc : 1);
snd_soc_component_write(component, AIC31XX_AOSR, aic31xx_divs[i].aosr);
/* Bit clock divider configuration. */
snd_soc_component_update_bits(component, AIC31XX_BCLKN,
AIC31XX_PLL_MASK, bclk_n);
aic31xx->rate_div_line = i;
dev_dbg(component->dev,
"pll %d.%04d/%d dosr %d n %d m %d aosr %d n %d m %d bclk_n %d\n",
aic31xx_divs[i].pll_j,
aic31xx_divs[i].pll_d,
aic31xx->p_div,
aic31xx_divs[i].dosr,
aic31xx_divs[i].ndac,
aic31xx_divs[i].mdac,
aic31xx_divs[i].aosr,
aic31xx_divs[i].nadc,
aic31xx_divs[i].madc,
bclk_n
);
return 0;
}
static int aic31xx_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
u8 data = 0;
dev_dbg(component->dev, "## %s: width %d rate %d\n",
__func__, params_width(params),
params_rate(params));
switch (params_width(params)) {
case 16:
break;
case 20:
data = (AIC31XX_WORD_LEN_20BITS <<
AIC31XX_IFACE1_DATALEN_SHIFT);
break;
case 24:
data = (AIC31XX_WORD_LEN_24BITS <<
AIC31XX_IFACE1_DATALEN_SHIFT);
break;
case 32:
data = (AIC31XX_WORD_LEN_32BITS <<
AIC31XX_IFACE1_DATALEN_SHIFT);
break;
default:
dev_err(component->dev, "%s: Unsupported width %d\n",
__func__, params_width(params));
return -EINVAL;
}
snd_soc_component_update_bits(component, AIC31XX_IFACE1,
AIC31XX_IFACE1_DATALEN_MASK,
data);
/*
* If BCLK is used as PLL input, the sysclk is determined by the hw
* params. So it must be updated here to match the input frequency.
*/
if (aic31xx->sysclk_id == AIC31XX_PLL_CLKIN_BCLK) {
aic31xx->sysclk = params_rate(params) * params_width(params) *
params_channels(params);
aic31xx->p_div = 1;
}
return aic31xx_setup_pll(component, params);
}
static int aic31xx_dac_mute(struct snd_soc_dai *codec_dai, int mute,
int direction)
{
struct snd_soc_component *component = codec_dai->component;
if (mute) {
snd_soc_component_update_bits(component, AIC31XX_DACMUTE,
AIC31XX_DACMUTE_MASK,
AIC31XX_DACMUTE_MASK);
} else {
snd_soc_component_update_bits(component, AIC31XX_DACMUTE,
AIC31XX_DACMUTE_MASK, 0x0);
}
return 0;
}
static int aic31xx_clock_master_routes(struct snd_soc_component *component,
unsigned int fmt)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
int ret;
fmt &= SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK;
if (fmt == SND_SOC_DAIFMT_CBC_CFC &&
aic31xx->master_dapm_route_applied) {
/*
* Remove the DAPM route(s) for codec clock master modes,
* if applied
*/
ret = snd_soc_dapm_del_routes(dapm, common31xx_cm_audio_map,
ARRAY_SIZE(common31xx_cm_audio_map));
if (!ret && !(aic31xx->codec_type & DAC31XX_BIT))
ret = snd_soc_dapm_del_routes(dapm,
aic31xx_cm_audio_map,
ARRAY_SIZE(aic31xx_cm_audio_map));
if (ret)
return ret;
aic31xx->master_dapm_route_applied = false;
} else if (fmt != SND_SOC_DAIFMT_CBC_CFC &&
!aic31xx->master_dapm_route_applied) {
/*
* Add the needed DAPM route(s) for codec clock master modes,
* if it is not done already
*/
ret = snd_soc_dapm_add_routes(dapm, common31xx_cm_audio_map,
ARRAY_SIZE(common31xx_cm_audio_map));
if (!ret && !(aic31xx->codec_type & DAC31XX_BIT))
ret = snd_soc_dapm_add_routes(dapm,
aic31xx_cm_audio_map,
ARRAY_SIZE(aic31xx_cm_audio_map));
if (ret)
return ret;
aic31xx->master_dapm_route_applied = true;
}
return 0;
}
static int aic31xx_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
u8 iface_reg1 = 0;
u8 iface_reg2 = 0;
u8 dsp_a_val = 0;
dev_dbg(component->dev, "## %s: fmt = 0x%x\n", __func__, fmt);
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
iface_reg1 |= AIC31XX_BCLK_MASTER | AIC31XX_WCLK_MASTER;
break;
case SND_SOC_DAIFMT_CBC_CFP:
iface_reg1 |= AIC31XX_WCLK_MASTER;
break;
case SND_SOC_DAIFMT_CBP_CFC:
iface_reg1 |= AIC31XX_BCLK_MASTER;
break;
case SND_SOC_DAIFMT_CBC_CFC:
break;
default:
dev_err(component->dev, "Invalid DAI clock provider\n");
return -EINVAL;
}
/* signal polarity */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
iface_reg2 |= AIC31XX_BCLKINV_MASK;
break;
default:
dev_err(component->dev, "Invalid DAI clock signal polarity\n");
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_DSP_A:
dsp_a_val = 0x1;
fallthrough;
case SND_SOC_DAIFMT_DSP_B:
/*
* NOTE: This CODEC samples on the falling edge of BCLK in
* DSP mode, this is inverted compared to what most DAIs
* expect, so we invert for this mode
*/
iface_reg2 ^= AIC31XX_BCLKINV_MASK;
iface_reg1 |= (AIC31XX_DSP_MODE <<
AIC31XX_IFACE1_DATATYPE_SHIFT);
break;
case SND_SOC_DAIFMT_RIGHT_J:
iface_reg1 |= (AIC31XX_RIGHT_JUSTIFIED_MODE <<
AIC31XX_IFACE1_DATATYPE_SHIFT);
break;
case SND_SOC_DAIFMT_LEFT_J:
iface_reg1 |= (AIC31XX_LEFT_JUSTIFIED_MODE <<
AIC31XX_IFACE1_DATATYPE_SHIFT);
break;
default:
dev_err(component->dev, "Invalid DAI interface format\n");
return -EINVAL;
}
snd_soc_component_update_bits(component, AIC31XX_IFACE1,
AIC31XX_IFACE1_DATATYPE_MASK |
AIC31XX_IFACE1_MASTER_MASK,
iface_reg1);
snd_soc_component_update_bits(component, AIC31XX_DATA_OFFSET,
AIC31XX_DATA_OFFSET_MASK,
dsp_a_val);
snd_soc_component_update_bits(component, AIC31XX_IFACE2,
AIC31XX_BCLKINV_MASK,
iface_reg2);
return aic31xx_clock_master_routes(component, fmt);
}
static int aic31xx_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
int i;
dev_dbg(component->dev, "## %s: clk_id = %d, freq = %d, dir = %d\n",
__func__, clk_id, freq, dir);
for (i = 1; i < 8; i++)
if (freq / i <= 20000000)
break;
if (freq/i > 20000000) {
dev_err(aic31xx->dev, "%s: Too high mclk frequency %u\n",
__func__, freq);
return -EINVAL;
}
aic31xx->p_div = i;
for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++)
if (aic31xx_divs[i].mclk_p == freq / aic31xx->p_div)
break;
if (i == ARRAY_SIZE(aic31xx_divs)) {
dev_err(aic31xx->dev, "%s: Unsupported frequency %d\n",
__func__, freq);
return -EINVAL;
}
/* set clock on MCLK, BCLK, or GPIO1 as PLL input */
snd_soc_component_update_bits(component, AIC31XX_CLKMUX, AIC31XX_PLL_CLKIN_MASK,
clk_id << AIC31XX_PLL_CLKIN_SHIFT);
aic31xx->sysclk_id = clk_id;
aic31xx->sysclk = freq;
return 0;
}
static int aic31xx_regulator_event(struct notifier_block *nb,
unsigned long event, void *data)
{
struct aic31xx_disable_nb *disable_nb =
container_of(nb, struct aic31xx_disable_nb, nb);
struct aic31xx_priv *aic31xx = disable_nb->aic31xx;
if (event & REGULATOR_EVENT_DISABLE) {
/*
* Put codec to reset and as at least one of the
* supplies was disabled.
*/
if (aic31xx->gpio_reset)
gpiod_set_value(aic31xx->gpio_reset, 1);
regcache_mark_dirty(aic31xx->regmap);
dev_dbg(aic31xx->dev, "## %s: DISABLE received\n", __func__);
}
return 0;
}
static int aic31xx_reset(struct aic31xx_priv *aic31xx)
{
int ret = 0;
if (aic31xx->gpio_reset) {
gpiod_set_value(aic31xx->gpio_reset, 1);
ndelay(10); /* At least 10ns */
gpiod_set_value(aic31xx->gpio_reset, 0);
} else {
ret = regmap_write(aic31xx->regmap, AIC31XX_RESET, 1);
}
mdelay(1); /* At least 1ms */
return ret;
}
static void aic31xx_clk_on(struct snd_soc_component *component)
{
struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
u8 mask = AIC31XX_PM_MASK;
u8 on = AIC31XX_PM_MASK;
dev_dbg(component->dev, "codec clock -> on (rate %d)\n",
aic31xx_divs[aic31xx->rate_div_line].rate);
snd_soc_component_update_bits(component, AIC31XX_PLLPR, mask, on);
mdelay(10);
snd_soc_component_update_bits(component, AIC31XX_NDAC, mask, on);
snd_soc_component_update_bits(component, AIC31XX_MDAC, mask, on);
if (aic31xx_divs[aic31xx->rate_div_line].nadc)
snd_soc_component_update_bits(component, AIC31XX_NADC, mask, on);
if (aic31xx_divs[aic31xx->rate_div_line].madc)
snd_soc_component_update_bits(component, AIC31XX_MADC, mask, on);
snd_soc_component_update_bits(component, AIC31XX_BCLKN, mask, on);
}
static void aic31xx_clk_off(struct snd_soc_component *component)
{
u8 mask = AIC31XX_PM_MASK;
u8 off = 0;
dev_dbg(component->dev, "codec clock -> off\n");
snd_soc_component_update_bits(component, AIC31XX_BCLKN, mask, off);
snd_soc_component_update_bits(component, AIC31XX_MADC, mask, off);
snd_soc_component_update_bits(component, AIC31XX_NADC, mask, off);
snd_soc_component_update_bits(component, AIC31XX_MDAC, mask, off);
snd_soc_component_update_bits(component, AIC31XX_NDAC, mask, off);
snd_soc_component_update_bits(component, AIC31XX_PLLPR, mask, off);
}
static int aic31xx_power_on(struct snd_soc_component *component)
{
struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
int ret;
ret = regulator_bulk_enable(ARRAY_SIZE(aic31xx->supplies),
aic31xx->supplies);
if (ret)
return ret;
regcache_cache_only(aic31xx->regmap, false);
/* Reset device registers for a consistent power-on like state */
ret = aic31xx_reset(aic31xx);
if (ret < 0)
dev_err(aic31xx->dev, "Could not reset device: %d\n", ret);
ret = regcache_sync(aic31xx->regmap);
if (ret) {
dev_err(component->dev,
"Failed to restore cache: %d\n", ret);
regcache_cache_only(aic31xx->regmap, true);
regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies),
aic31xx->supplies);
return ret;
}
/*
* The jack detection configuration is in the same register
* that is used to report jack detect status so is volatile
* and not covered by the cache sync, restore it separately.
*/
aic31xx_set_jack(component, aic31xx->jack, NULL);
return 0;
}
static void aic31xx_power_off(struct snd_soc_component *component)
{
struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
regcache_cache_only(aic31xx->regmap, true);
regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies),
aic31xx->supplies);
}
static int aic31xx_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
dev_dbg(component->dev, "## %s: %d -> %d\n", __func__,
snd_soc_component_get_bias_level(component), level);
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY)
aic31xx_clk_on(component);
break;
case SND_SOC_BIAS_STANDBY:
switch (snd_soc_component_get_bias_level(component)) {
case SND_SOC_BIAS_OFF:
aic31xx_power_on(component);
break;
case SND_SOC_BIAS_PREPARE:
aic31xx_clk_off(component);
break;
default:
BUG();
}
break;
case SND_SOC_BIAS_OFF:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY)
aic31xx_power_off(component);
break;
}
return 0;
}
static int aic31xx_set_jack(struct snd_soc_component *component,
struct snd_soc_jack *jack, void *data)
{
struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
aic31xx->jack = jack;
/* Enable/Disable jack detection */
regmap_write(aic31xx->regmap, AIC31XX_HSDETECT,
jack ? AIC31XX_HSD_ENABLE : 0);
return 0;
}
static int aic31xx_codec_probe(struct snd_soc_component *component)
{
struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
int i, ret;
dev_dbg(aic31xx->dev, "## %s\n", __func__);
aic31xx->component = component;
for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) {
aic31xx->disable_nb[i].nb.notifier_call =
aic31xx_regulator_event;
aic31xx->disable_nb[i].aic31xx = aic31xx;
ret = devm_regulator_register_notifier(
aic31xx->supplies[i].consumer,
&aic31xx->disable_nb[i].nb);
if (ret) {
dev_err(component->dev,
"Failed to request regulator notifier: %d\n",
ret);
return ret;
}
}
regcache_cache_only(aic31xx->regmap, true);
regcache_mark_dirty(aic31xx->regmap);
ret = aic31xx_add_controls(component);
if (ret)
return ret;
ret = aic31xx_add_widgets(component);
if (ret)
return ret;
/* set output common-mode voltage */
snd_soc_component_update_bits(component, AIC31XX_HPDRIVER,
AIC31XX_HPD_OCMV_MASK,
aic31xx->ocmv << AIC31XX_HPD_OCMV_SHIFT);
return 0;
}
static const struct snd_soc_component_driver soc_codec_driver_aic31xx = {
.probe = aic31xx_codec_probe,
.set_jack = aic31xx_set_jack,
.set_bias_level = aic31xx_set_bias_level,
.controls = common31xx_snd_controls,
.num_controls = ARRAY_SIZE(common31xx_snd_controls),
.dapm_widgets = common31xx_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(common31xx_dapm_widgets),
.dapm_routes = common31xx_audio_map,
.num_dapm_routes = ARRAY_SIZE(common31xx_audio_map),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct snd_soc_dai_ops aic31xx_dai_ops = {
.hw_params = aic31xx_hw_params,
.set_sysclk = aic31xx_set_dai_sysclk,
.set_fmt = aic31xx_set_dai_fmt,
.mute_stream = aic31xx_dac_mute,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver dac31xx_dai_driver[] = {
{
.name = "tlv320dac31xx-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = AIC31XX_RATES,
.formats = AIC31XX_FORMATS,
},
.ops = &aic31xx_dai_ops,
.symmetric_rate = 1,
}
};
static struct snd_soc_dai_driver aic31xx_dai_driver[] = {
{
.name = "tlv320aic31xx-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = AIC31XX_RATES,
.formats = AIC31XX_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = AIC31XX_RATES,
.formats = AIC31XX_FORMATS,
},
.ops = &aic31xx_dai_ops,
.symmetric_rate = 1,
}
};
#if defined(CONFIG_OF)
static const struct of_device_id tlv320aic31xx_of_match[] = {
{ .compatible = "ti,tlv320aic310x" },
{ .compatible = "ti,tlv320aic311x" },
{ .compatible = "ti,tlv320aic3100" },
{ .compatible = "ti,tlv320aic3110" },
{ .compatible = "ti,tlv320aic3120" },
{ .compatible = "ti,tlv320aic3111" },
{ .compatible = "ti,tlv320dac3100" },
{ .compatible = "ti,tlv320dac3101" },
{},
};
MODULE_DEVICE_TABLE(of, tlv320aic31xx_of_match);
#endif /* CONFIG_OF */
#ifdef CONFIG_ACPI
static const struct acpi_device_id aic31xx_acpi_match[] = {
{ "10TI3100", 0 },
{ }
};
MODULE_DEVICE_TABLE(acpi, aic31xx_acpi_match);
#endif
static irqreturn_t aic31xx_irq(int irq, void *data)
{
struct aic31xx_priv *aic31xx = data;
struct device *dev = aic31xx->dev;
unsigned int value;
bool handled = false;
int ret;
ret = regmap_read(aic31xx->regmap, AIC31XX_INTRDACFLAG, &value);
if (ret) {
dev_err(dev, "Failed to read interrupt mask: %d\n", ret);
goto exit;
}
if (value)
handled = true;
else
goto read_overflow;
if (value & AIC31XX_HPLSCDETECT)
dev_err(dev, "Short circuit on Left output is detected\n");
if (value & AIC31XX_HPRSCDETECT)
dev_err(dev, "Short circuit on Right output is detected\n");
if (value & (AIC31XX_HSPLUG | AIC31XX_BUTTONPRESS)) {
unsigned int val;
int status = 0;
ret = regmap_read(aic31xx->regmap, AIC31XX_INTRDACFLAG2,
&val);
if (ret) {
dev_err(dev, "Failed to read interrupt mask: %d\n",
ret);
goto exit;
}
if (val & AIC31XX_BUTTONPRESS)
status |= SND_JACK_BTN_0;
ret = regmap_read(aic31xx->regmap, AIC31XX_HSDETECT, &val);
if (ret) {
dev_err(dev, "Failed to read headset type: %d\n", ret);
goto exit;
}
switch ((val & AIC31XX_HSD_TYPE_MASK) >>
AIC31XX_HSD_TYPE_SHIFT) {
case AIC31XX_HSD_HP:
status |= SND_JACK_HEADPHONE;
break;
case AIC31XX_HSD_HS:
status |= SND_JACK_HEADSET;
break;
default:
break;
}
if (aic31xx->jack)
snd_soc_jack_report(aic31xx->jack, status,
AIC31XX_JACK_MASK);
}
if (value & ~(AIC31XX_HPLSCDETECT |
AIC31XX_HPRSCDETECT |
AIC31XX_HSPLUG |
AIC31XX_BUTTONPRESS))
dev_err(dev, "Unknown DAC interrupt flags: 0x%08x\n", value);
read_overflow:
ret = regmap_read(aic31xx->regmap, AIC31XX_OFFLAG, &value);
if (ret) {
dev_err(dev, "Failed to read overflow flag: %d\n", ret);
goto exit;
}
if (value)
handled = true;
else
goto exit;
if (value & AIC31XX_DAC_OF_LEFT)
dev_warn(dev, "Left-channel DAC overflow has occurred\n");
if (value & AIC31XX_DAC_OF_RIGHT)
dev_warn(dev, "Right-channel DAC overflow has occurred\n");
if (value & AIC31XX_DAC_OF_SHIFTER)
dev_warn(dev, "DAC barrel shifter overflow has occurred\n");
if (value & AIC31XX_ADC_OF)
dev_warn(dev, "ADC overflow has occurred\n");
if (value & AIC31XX_ADC_OF_SHIFTER)
dev_warn(dev, "ADC barrel shifter overflow has occurred\n");
if (value & ~(AIC31XX_DAC_OF_LEFT |
AIC31XX_DAC_OF_RIGHT |
AIC31XX_DAC_OF_SHIFTER |
AIC31XX_ADC_OF |
AIC31XX_ADC_OF_SHIFTER))
dev_warn(dev, "Unknown overflow interrupt flags: 0x%08x\n", value);
exit:
if (handled)
return IRQ_HANDLED;
else
return IRQ_NONE;
}
static void aic31xx_configure_ocmv(struct aic31xx_priv *priv)
{
struct device *dev = priv->dev;
int dvdd, avdd;
u32 value;
if (dev->fwnode &&
fwnode_property_read_u32(dev->fwnode, "ai31xx-ocmv", &value)) {
/* OCMV setting is forced by DT */
if (value <= 3) {
priv->ocmv = value;
return;
}
}
avdd = regulator_get_voltage(priv->supplies[3].consumer);
dvdd = regulator_get_voltage(priv->supplies[5].consumer);
if (avdd > 3600000 || dvdd > 1950000) {
dev_warn(dev,
"Too high supply voltage(s) AVDD: %d, DVDD: %d\n",
avdd, dvdd);
} else if (avdd == 3600000 && dvdd == 1950000) {
priv->ocmv = AIC31XX_HPD_OCMV_1_8V;
} else if (avdd >= 3300000 && dvdd >= 1800000) {
priv->ocmv = AIC31XX_HPD_OCMV_1_65V;
} else if (avdd >= 3000000 && dvdd >= 1650000) {
priv->ocmv = AIC31XX_HPD_OCMV_1_5V;
} else if (avdd >= 2700000 && dvdd >= 1525000) {
priv->ocmv = AIC31XX_HPD_OCMV_1_35V;
} else {
dev_warn(dev,
"Invalid supply voltage(s) AVDD: %d, DVDD: %d\n",
avdd, dvdd);
}
}
static const struct i2c_device_id aic31xx_i2c_id[] = {
{ "tlv320aic310x", AIC3100 },
{ "tlv320aic311x", AIC3110 },
{ "tlv320aic3100", AIC3100 },
{ "tlv320aic3110", AIC3110 },
{ "tlv320aic3120", AIC3120 },
{ "tlv320aic3111", AIC3111 },
{ "tlv320dac3100", DAC3100 },
{ "tlv320dac3101", DAC3101 },
{ }
};
MODULE_DEVICE_TABLE(i2c, aic31xx_i2c_id);
static int aic31xx_i2c_probe(struct i2c_client *i2c)
{
struct aic31xx_priv *aic31xx;
unsigned int micbias_value = MICBIAS_2_0V;
const struct i2c_device_id *id = i2c_match_id(aic31xx_i2c_id, i2c);
int i, ret;
dev_dbg(&i2c->dev, "## %s: %s codec_type = %d\n", __func__,
id->name, (int)id->driver_data);
aic31xx = devm_kzalloc(&i2c->dev, sizeof(*aic31xx), GFP_KERNEL);
if (!aic31xx)
return -ENOMEM;
aic31xx->regmap = devm_regmap_init_i2c(i2c, &aic31xx_i2c_regmap);
if (IS_ERR(aic31xx->regmap)) {
ret = PTR_ERR(aic31xx->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
regcache_cache_only(aic31xx->regmap, true);
aic31xx->dev = &i2c->dev;
aic31xx->irq = i2c->irq;
aic31xx->codec_type = id->driver_data;
dev_set_drvdata(aic31xx->dev, aic31xx);
fwnode_property_read_u32(aic31xx->dev->fwnode, "ai31xx-micbias-vg",
&micbias_value);
switch (micbias_value) {
case MICBIAS_2_0V:
case MICBIAS_2_5V:
case MICBIAS_AVDDV:
aic31xx->micbias_vg = micbias_value;
break;
default:
dev_err(aic31xx->dev, "Bad ai31xx-micbias-vg value %d\n",
micbias_value);
aic31xx->micbias_vg = MICBIAS_2_0V;
}
if (dev_get_platdata(aic31xx->dev)) {
memcpy(&aic31xx->pdata, dev_get_platdata(aic31xx->dev), sizeof(aic31xx->pdata));
aic31xx->codec_type = aic31xx->pdata.codec_type;
aic31xx->micbias_vg = aic31xx->pdata.micbias_vg;
}
aic31xx->gpio_reset = devm_gpiod_get_optional(aic31xx->dev, "reset",
GPIOD_OUT_LOW);
if (IS_ERR(aic31xx->gpio_reset))
return dev_err_probe(aic31xx->dev, PTR_ERR(aic31xx->gpio_reset),
"not able to acquire gpio\n");
for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++)
aic31xx->supplies[i].supply = aic31xx_supply_names[i];
ret = devm_regulator_bulk_get(aic31xx->dev,
ARRAY_SIZE(aic31xx->supplies),
aic31xx->supplies);
if (ret)
return dev_err_probe(aic31xx->dev, ret, "Failed to request supplies\n");
aic31xx_configure_ocmv(aic31xx);
if (aic31xx->irq > 0) {
regmap_update_bits(aic31xx->regmap, AIC31XX_GPIO1,
AIC31XX_GPIO1_FUNC_MASK,
AIC31XX_GPIO1_INT1 <<
AIC31XX_GPIO1_FUNC_SHIFT);
regmap_write(aic31xx->regmap, AIC31XX_INT1CTRL,
AIC31XX_HSPLUGDET |
AIC31XX_BUTTONPRESSDET |
AIC31XX_SC |
AIC31XX_ENGINE);
ret = devm_request_threaded_irq(aic31xx->dev, aic31xx->irq,
NULL, aic31xx_irq,
IRQF_ONESHOT, "aic31xx-irq",
aic31xx);
if (ret) {
dev_err(aic31xx->dev, "Unable to request IRQ\n");
return ret;
}
}
if (aic31xx->codec_type & DAC31XX_BIT)
return devm_snd_soc_register_component(&i2c->dev,
&soc_codec_driver_aic31xx,
dac31xx_dai_driver,
ARRAY_SIZE(dac31xx_dai_driver));
else
return devm_snd_soc_register_component(&i2c->dev,
&soc_codec_driver_aic31xx,
aic31xx_dai_driver,
ARRAY_SIZE(aic31xx_dai_driver));
}
static struct i2c_driver aic31xx_i2c_driver = {
.driver = {
.name = "tlv320aic31xx-codec",
.of_match_table = of_match_ptr(tlv320aic31xx_of_match),
.acpi_match_table = ACPI_PTR(aic31xx_acpi_match),
},
.probe = aic31xx_i2c_probe,
.id_table = aic31xx_i2c_id,
};
module_i2c_driver(aic31xx_i2c_driver);
MODULE_AUTHOR("Jyri Sarha <[email protected]>");
MODULE_DESCRIPTION("ASoC TLV320AIC31xx CODEC Driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/tlv320aic31xx.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Texas Instruments TLV320AIC26 low power audio CODEC
* ALSA SoC CODEC driver
*
* Copyright (C) 2008 Secret Lab Technologies Ltd.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/device.h>
#include <linux/sysfs.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include "tlv320aic26.h"
MODULE_DESCRIPTION("ASoC TLV320AIC26 codec driver");
MODULE_AUTHOR("Grant Likely <[email protected]>");
MODULE_LICENSE("GPL");
/* AIC26 driver private data */
struct aic26 {
struct spi_device *spi;
struct regmap *regmap;
struct snd_soc_component *component;
int clock_provider;
int datfm;
int mclk;
/* Keyclick parameters */
int keyclick_amplitude;
int keyclick_freq;
int keyclick_len;
};
static const struct snd_soc_dapm_widget tlv320aic26_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("MICIN"),
SND_SOC_DAPM_INPUT("AUX"),
SND_SOC_DAPM_OUTPUT("HPL"),
SND_SOC_DAPM_OUTPUT("HPR"),
};
static const struct snd_soc_dapm_route tlv320aic26_dapm_routes[] = {
{ "Capture", NULL, "MICIN" },
{ "Capture", NULL, "AUX" },
{ "HPL", NULL, "Playback" },
{ "HPR", NULL, "Playback" },
};
/* ---------------------------------------------------------------------
* Digital Audio Interface Operations
*/
static int aic26_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct aic26 *aic26 = snd_soc_component_get_drvdata(component);
int fsref, divisor, wlen, pval, jval, dval, qval;
u16 reg;
dev_dbg(&aic26->spi->dev, "aic26_hw_params(substream=%p, params=%p)\n",
substream, params);
dev_dbg(&aic26->spi->dev, "rate=%i width=%d\n", params_rate(params),
params_width(params));
switch (params_rate(params)) {
case 8000: fsref = 48000; divisor = AIC26_DIV_6; break;
case 11025: fsref = 44100; divisor = AIC26_DIV_4; break;
case 12000: fsref = 48000; divisor = AIC26_DIV_4; break;
case 16000: fsref = 48000; divisor = AIC26_DIV_3; break;
case 22050: fsref = 44100; divisor = AIC26_DIV_2; break;
case 24000: fsref = 48000; divisor = AIC26_DIV_2; break;
case 32000: fsref = 48000; divisor = AIC26_DIV_1_5; break;
case 44100: fsref = 44100; divisor = AIC26_DIV_1; break;
case 48000: fsref = 48000; divisor = AIC26_DIV_1; break;
default:
dev_dbg(&aic26->spi->dev, "bad rate\n"); return -EINVAL;
}
/* select data word length */
switch (params_width(params)) {
case 8: wlen = AIC26_WLEN_16; break;
case 16: wlen = AIC26_WLEN_16; break;
case 24: wlen = AIC26_WLEN_24; break;
case 32: wlen = AIC26_WLEN_32; break;
default:
dev_dbg(&aic26->spi->dev, "bad format\n"); return -EINVAL;
}
/**
* Configure PLL
* fsref = (mclk * PLLM) / 2048
* where PLLM = J.DDDD (DDDD register ranges from 0 to 9999, decimal)
*/
pval = 1;
/* compute J portion of multiplier */
jval = fsref / (aic26->mclk / 2048);
/* compute fractional DDDD component of multiplier */
dval = fsref - (jval * (aic26->mclk / 2048));
dval = (10000 * dval) / (aic26->mclk / 2048);
dev_dbg(&aic26->spi->dev, "Setting PLLM to %d.%04d\n", jval, dval);
qval = 0;
reg = 0x8000 | qval << 11 | pval << 8 | jval << 2;
snd_soc_component_write(component, AIC26_REG_PLL_PROG1, reg);
reg = dval << 2;
snd_soc_component_write(component, AIC26_REG_PLL_PROG2, reg);
/* Audio Control 3 (clock provider mode, fsref rate) */
if (aic26->clock_provider)
reg = 0x0800;
if (fsref == 48000)
reg = 0x2000;
snd_soc_component_update_bits(component, AIC26_REG_AUDIO_CTRL3, 0xf800, reg);
/* Audio Control 1 (FSref divisor) */
reg = wlen | aic26->datfm | (divisor << 3) | divisor;
snd_soc_component_update_bits(component, AIC26_REG_AUDIO_CTRL1, 0xfff, reg);
return 0;
}
/*
* aic26_mute - Mute control to reduce noise when changing audio format
*/
static int aic26_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
struct aic26 *aic26 = snd_soc_component_get_drvdata(component);
u16 reg;
dev_dbg(&aic26->spi->dev, "aic26_mute(dai=%p, mute=%i)\n",
dai, mute);
if (mute)
reg = 0x8080;
else
reg = 0;
snd_soc_component_update_bits(component, AIC26_REG_DAC_GAIN, 0x8000, reg);
return 0;
}
static int aic26_set_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct aic26 *aic26 = snd_soc_component_get_drvdata(component);
dev_dbg(&aic26->spi->dev, "aic26_set_sysclk(dai=%p, clk_id==%i,"
" freq=%i, dir=%i)\n",
codec_dai, clk_id, freq, dir);
/* MCLK needs to fall between 2MHz and 50 MHz */
if ((freq < 2000000) || (freq > 50000000))
return -EINVAL;
aic26->mclk = freq;
return 0;
}
static int aic26_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct aic26 *aic26 = snd_soc_component_get_drvdata(component);
dev_dbg(&aic26->spi->dev, "aic26_set_fmt(dai=%p, fmt==%i)\n",
codec_dai, fmt);
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP: aic26->clock_provider = 1; break;
case SND_SOC_DAIFMT_CBC_CFC: aic26->clock_provider = 0; break;
default:
dev_dbg(&aic26->spi->dev, "bad master\n"); return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S: aic26->datfm = AIC26_DATFM_I2S; break;
case SND_SOC_DAIFMT_DSP_A: aic26->datfm = AIC26_DATFM_DSP; break;
case SND_SOC_DAIFMT_RIGHT_J: aic26->datfm = AIC26_DATFM_RIGHTJ; break;
case SND_SOC_DAIFMT_LEFT_J: aic26->datfm = AIC26_DATFM_LEFTJ; break;
default:
dev_dbg(&aic26->spi->dev, "bad format\n"); return -EINVAL;
}
return 0;
}
/* ---------------------------------------------------------------------
* Digital Audio Interface Definition
*/
#define AIC26_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\
SNDRV_PCM_RATE_48000)
#define AIC26_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE |\
SNDRV_PCM_FMTBIT_S24_BE | SNDRV_PCM_FMTBIT_S32_BE)
static const struct snd_soc_dai_ops aic26_dai_ops = {
.hw_params = aic26_hw_params,
.mute_stream = aic26_mute,
.set_sysclk = aic26_set_sysclk,
.set_fmt = aic26_set_fmt,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver aic26_dai = {
.name = "tlv320aic26-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = AIC26_RATES,
.formats = AIC26_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = AIC26_RATES,
.formats = AIC26_FORMATS,
},
.ops = &aic26_dai_ops,
};
/* ---------------------------------------------------------------------
* ALSA controls
*/
static const char *aic26_capture_src_text[] = {"Mic", "Aux"};
static SOC_ENUM_SINGLE_DECL(aic26_capture_src_enum,
AIC26_REG_AUDIO_CTRL1, 12,
aic26_capture_src_text);
static const struct snd_kcontrol_new aic26_snd_controls[] = {
/* Output */
SOC_DOUBLE("PCM Playback Volume", AIC26_REG_DAC_GAIN, 8, 0, 0x7f, 1),
SOC_DOUBLE("PCM Playback Switch", AIC26_REG_DAC_GAIN, 15, 7, 1, 1),
SOC_SINGLE("PCM Capture Volume", AIC26_REG_ADC_GAIN, 8, 0x7f, 0),
SOC_SINGLE("PCM Capture Mute", AIC26_REG_ADC_GAIN, 15, 1, 1),
SOC_SINGLE("Keyclick activate", AIC26_REG_AUDIO_CTRL2, 15, 0x1, 0),
SOC_SINGLE("Keyclick amplitude", AIC26_REG_AUDIO_CTRL2, 12, 0x7, 0),
SOC_SINGLE("Keyclick frequency", AIC26_REG_AUDIO_CTRL2, 8, 0x7, 0),
SOC_SINGLE("Keyclick period", AIC26_REG_AUDIO_CTRL2, 4, 0xf, 0),
SOC_ENUM("Capture Source", aic26_capture_src_enum),
};
/* ---------------------------------------------------------------------
* SPI device portion of driver: sysfs files for debugging
*/
static ssize_t keyclick_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct aic26 *aic26 = dev_get_drvdata(dev);
int val, amp, freq, len;
val = snd_soc_component_read(aic26->component, AIC26_REG_AUDIO_CTRL2);
amp = (val >> 12) & 0x7;
freq = (125 << ((val >> 8) & 0x7)) >> 1;
len = 2 * (1 + ((val >> 4) & 0xf));
return sysfs_emit(buf, "amp=%x freq=%iHz len=%iclks\n", amp, freq, len);
}
/* Any write to the keyclick attribute will trigger the keyclick event */
static ssize_t keyclick_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct aic26 *aic26 = dev_get_drvdata(dev);
snd_soc_component_update_bits(aic26->component, AIC26_REG_AUDIO_CTRL2,
0x8000, 0x800);
return count;
}
static DEVICE_ATTR_RW(keyclick);
/* ---------------------------------------------------------------------
* SoC CODEC portion of driver: probe and release routines
*/
static int aic26_probe(struct snd_soc_component *component)
{
struct aic26 *aic26 = dev_get_drvdata(component->dev);
int ret, reg;
aic26->component = component;
/* Reset the codec to power on defaults */
snd_soc_component_write(component, AIC26_REG_RESET, 0xBB00);
/* Power up CODEC */
snd_soc_component_write(component, AIC26_REG_POWER_CTRL, 0);
/* Audio Control 3 (master mode, fsref rate) */
reg = snd_soc_component_read(component, AIC26_REG_AUDIO_CTRL3);
reg &= ~0xf800;
reg |= 0x0800; /* set master mode */
snd_soc_component_write(component, AIC26_REG_AUDIO_CTRL3, reg);
/* Register the sysfs files for debugging */
/* Create SysFS files */
ret = device_create_file(component->dev, &dev_attr_keyclick);
if (ret)
dev_info(component->dev, "error creating sysfs files\n");
return 0;
}
static const struct snd_soc_component_driver aic26_soc_component_dev = {
.probe = aic26_probe,
.controls = aic26_snd_controls,
.num_controls = ARRAY_SIZE(aic26_snd_controls),
.dapm_widgets = tlv320aic26_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(tlv320aic26_dapm_widgets),
.dapm_routes = tlv320aic26_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(tlv320aic26_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config aic26_regmap = {
.reg_bits = 16,
.val_bits = 16,
};
/* ---------------------------------------------------------------------
* SPI device portion of driver: probe and release routines and SPI
* driver registration.
*/
static int aic26_spi_probe(struct spi_device *spi)
{
struct aic26 *aic26;
int ret;
dev_dbg(&spi->dev, "probing tlv320aic26 spi device\n");
/* Allocate driver data */
aic26 = devm_kzalloc(&spi->dev, sizeof *aic26, GFP_KERNEL);
if (!aic26)
return -ENOMEM;
aic26->regmap = devm_regmap_init_spi(spi, &aic26_regmap);
if (IS_ERR(aic26->regmap))
return PTR_ERR(aic26->regmap);
/* Initialize the driver data */
aic26->spi = spi;
dev_set_drvdata(&spi->dev, aic26);
aic26->clock_provider = 1;
ret = devm_snd_soc_register_component(&spi->dev,
&aic26_soc_component_dev, &aic26_dai, 1);
return ret;
}
static struct spi_driver aic26_spi = {
.driver = {
.name = "tlv320aic26-codec",
},
.probe = aic26_spi_probe,
};
module_spi_driver(aic26_spi);
| linux-master | sound/soc/codecs/tlv320aic26.c |
// SPDX-License-Identifier: GPL-2.0
//
// rt1308-sdw.c -- rt1308 ALSA SoC audio driver
//
// Copyright(c) 2019 Realtek Semiconductor Corp.
//
//
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/pm_runtime.h>
#include <linux/mod_devicetable.h>
#include <linux/soundwire/sdw.h>
#include <linux/soundwire/sdw_type.h>
#include <linux/soundwire/sdw_registers.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/sdw.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include "rt1308.h"
#include "rt1308-sdw.h"
static bool rt1308_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x00e0:
case 0x00f0:
case 0x2f01 ... 0x2f07:
case 0x3000 ... 0x3001:
case 0x3004 ... 0x3005:
case 0x3008:
case 0x300a:
case 0xc000 ... 0xcff3:
return true;
default:
return false;
}
}
static bool rt1308_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x2f01 ... 0x2f07:
case 0x3000 ... 0x3001:
case 0x3004 ... 0x3005:
case 0x3008:
case 0x300a:
case 0xc000:
case 0xc710:
case 0xcf01:
case 0xc860 ... 0xc863:
case 0xc870 ... 0xc873:
return true;
default:
return false;
}
}
static const struct regmap_config rt1308_sdw_regmap = {
.reg_bits = 32,
.val_bits = 8,
.readable_reg = rt1308_readable_register,
.volatile_reg = rt1308_volatile_register,
.max_register = 0xcfff,
.reg_defaults = rt1308_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(rt1308_reg_defaults),
.cache_type = REGCACHE_MAPLE,
.use_single_read = true,
.use_single_write = true,
};
/* Bus clock frequency */
#define RT1308_CLK_FREQ_9600000HZ 9600000
#define RT1308_CLK_FREQ_12000000HZ 12000000
#define RT1308_CLK_FREQ_6000000HZ 6000000
#define RT1308_CLK_FREQ_4800000HZ 4800000
#define RT1308_CLK_FREQ_2400000HZ 2400000
#define RT1308_CLK_FREQ_12288000HZ 12288000
static int rt1308_clock_config(struct device *dev)
{
struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev);
unsigned int clk_freq, value;
clk_freq = (rt1308->params.curr_dr_freq >> 1);
switch (clk_freq) {
case RT1308_CLK_FREQ_12000000HZ:
value = 0x0;
break;
case RT1308_CLK_FREQ_6000000HZ:
value = 0x1;
break;
case RT1308_CLK_FREQ_9600000HZ:
value = 0x2;
break;
case RT1308_CLK_FREQ_4800000HZ:
value = 0x3;
break;
case RT1308_CLK_FREQ_2400000HZ:
value = 0x4;
break;
case RT1308_CLK_FREQ_12288000HZ:
value = 0x5;
break;
default:
return -EINVAL;
}
regmap_write(rt1308->regmap, 0xe0, value);
regmap_write(rt1308->regmap, 0xf0, value);
dev_dbg(dev, "%s complete, clk_freq=%d\n", __func__, clk_freq);
return 0;
}
static int rt1308_read_prop(struct sdw_slave *slave)
{
struct sdw_slave_prop *prop = &slave->prop;
int nval, i;
u32 bit;
unsigned long addr;
struct sdw_dpn_prop *dpn;
prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
prop->paging_support = true;
/* first we need to allocate memory for set bits in port lists */
prop->source_ports = 0x00; /* BITMAP: 00010100 (not enable yet) */
prop->sink_ports = 0x2; /* BITMAP: 00000010 */
/* for sink */
nval = hweight32(prop->sink_ports);
prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
sizeof(*prop->sink_dpn_prop),
GFP_KERNEL);
if (!prop->sink_dpn_prop)
return -ENOMEM;
i = 0;
dpn = prop->sink_dpn_prop;
addr = prop->sink_ports;
for_each_set_bit(bit, &addr, 32) {
dpn[i].num = bit;
dpn[i].type = SDW_DPN_FULL;
dpn[i].simple_ch_prep_sm = true;
dpn[i].ch_prep_timeout = 10;
i++;
}
/* set the timeout values */
prop->clk_stop_timeout = 20;
dev_dbg(&slave->dev, "%s\n", __func__);
return 0;
}
static void rt1308_apply_calib_params(struct rt1308_sdw_priv *rt1308)
{
unsigned int efuse_m_btl_l, efuse_m_btl_r, tmp;
unsigned int efuse_c_btl_l, efuse_c_btl_r;
/* read efuse to apply calibration parameters */
regmap_write(rt1308->regmap, 0xc7f0, 0x04);
regmap_write(rt1308->regmap, 0xc7f1, 0xfe);
msleep(100);
regmap_write(rt1308->regmap, 0xc7f0, 0x44);
msleep(20);
regmap_write(rt1308->regmap, 0xc240, 0x10);
regmap_read(rt1308->regmap, 0xc861, &tmp);
efuse_m_btl_l = tmp;
regmap_read(rt1308->regmap, 0xc860, &tmp);
efuse_m_btl_l = efuse_m_btl_l | (tmp << 8);
regmap_read(rt1308->regmap, 0xc863, &tmp);
efuse_c_btl_l = tmp;
regmap_read(rt1308->regmap, 0xc862, &tmp);
efuse_c_btl_l = efuse_c_btl_l | (tmp << 8);
regmap_read(rt1308->regmap, 0xc871, &tmp);
efuse_m_btl_r = tmp;
regmap_read(rt1308->regmap, 0xc870, &tmp);
efuse_m_btl_r = efuse_m_btl_r | (tmp << 8);
regmap_read(rt1308->regmap, 0xc873, &tmp);
efuse_c_btl_r = tmp;
regmap_read(rt1308->regmap, 0xc872, &tmp);
efuse_c_btl_r = efuse_c_btl_r | (tmp << 8);
dev_dbg(&rt1308->sdw_slave->dev, "%s m_btl_l=0x%x, m_btl_r=0x%x\n", __func__,
efuse_m_btl_l, efuse_m_btl_r);
dev_dbg(&rt1308->sdw_slave->dev, "%s c_btl_l=0x%x, c_btl_r=0x%x\n", __func__,
efuse_c_btl_l, efuse_c_btl_r);
}
static void rt1308_apply_bq_params(struct rt1308_sdw_priv *rt1308)
{
unsigned int i, reg, data;
for (i = 0; i < rt1308->bq_params_cnt; i += 3) {
reg = rt1308->bq_params[i] | (rt1308->bq_params[i + 1] << 8);
data = rt1308->bq_params[i + 2];
regmap_write(rt1308->regmap, reg, data);
}
}
static int rt1308_io_init(struct device *dev, struct sdw_slave *slave)
{
struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev);
int ret = 0;
unsigned int tmp, hibernation_flag;
if (rt1308->hw_init)
return 0;
regcache_cache_only(rt1308->regmap, false);
if (rt1308->first_hw_init)
regcache_cache_bypass(rt1308->regmap, true);
/*
* PM runtime status is marked as 'active' only when a Slave reports as Attached
*/
if (!rt1308->first_hw_init)
/* update count of parent 'active' children */
pm_runtime_set_active(&slave->dev);
pm_runtime_get_noresume(&slave->dev);
regmap_read(rt1308->regmap, 0xcf01, &hibernation_flag);
if ((hibernation_flag != 0x00) && rt1308->first_hw_init)
goto _preset_ready_;
/* sw reset */
regmap_write(rt1308->regmap, RT1308_SDW_RESET, 0);
regmap_read(rt1308->regmap, 0xc710, &tmp);
rt1308->hw_ver = tmp;
dev_dbg(dev, "%s, hw_ver=0x%x\n", __func__, rt1308->hw_ver);
/* initial settings */
regmap_write(rt1308->regmap, 0xc103, 0xc0);
regmap_write(rt1308->regmap, 0xc030, 0x17);
regmap_write(rt1308->regmap, 0xc031, 0x81);
regmap_write(rt1308->regmap, 0xc032, 0x26);
regmap_write(rt1308->regmap, 0xc040, 0x80);
regmap_write(rt1308->regmap, 0xc041, 0x80);
regmap_write(rt1308->regmap, 0xc042, 0x06);
regmap_write(rt1308->regmap, 0xc052, 0x0a);
regmap_write(rt1308->regmap, 0xc080, 0x0a);
regmap_write(rt1308->regmap, 0xc060, 0x02);
regmap_write(rt1308->regmap, 0xc061, 0x75);
regmap_write(rt1308->regmap, 0xc062, 0x05);
regmap_write(rt1308->regmap, 0xc171, 0x07);
regmap_write(rt1308->regmap, 0xc173, 0x0d);
if (rt1308->hw_ver == RT1308_VER_C) {
regmap_write(rt1308->regmap, 0xc311, 0x7f);
regmap_write(rt1308->regmap, 0xc300, 0x09);
} else {
regmap_write(rt1308->regmap, 0xc311, 0x4f);
regmap_write(rt1308->regmap, 0xc300, 0x0b);
}
regmap_write(rt1308->regmap, 0xc900, 0x5a);
regmap_write(rt1308->regmap, 0xc1a0, 0x84);
regmap_write(rt1308->regmap, 0xc1a1, 0x01);
regmap_write(rt1308->regmap, 0xc360, 0x78);
regmap_write(rt1308->regmap, 0xc361, 0x87);
regmap_write(rt1308->regmap, 0xc0a1, 0x71);
regmap_write(rt1308->regmap, 0xc210, 0x00);
regmap_write(rt1308->regmap, 0xc070, 0x00);
regmap_write(rt1308->regmap, 0xc100, 0xd7);
regmap_write(rt1308->regmap, 0xc101, 0xd7);
/* apply BQ params */
rt1308_apply_bq_params(rt1308);
regmap_write(rt1308->regmap, 0xcf01, 0x01);
_preset_ready_:
if (rt1308->first_hw_init) {
regcache_cache_bypass(rt1308->regmap, false);
regcache_mark_dirty(rt1308->regmap);
} else
rt1308->first_hw_init = true;
/* Mark Slave initialization complete */
rt1308->hw_init = true;
pm_runtime_mark_last_busy(&slave->dev);
pm_runtime_put_autosuspend(&slave->dev);
dev_dbg(&slave->dev, "%s hw_init complete\n", __func__);
return ret;
}
static int rt1308_update_status(struct sdw_slave *slave,
enum sdw_slave_status status)
{
struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(&slave->dev);
if (status == SDW_SLAVE_UNATTACHED)
rt1308->hw_init = false;
/*
* Perform initialization only if slave status is present and
* hw_init flag is false
*/
if (rt1308->hw_init || status != SDW_SLAVE_ATTACHED)
return 0;
/* perform I/O transfers required for Slave initialization */
return rt1308_io_init(&slave->dev, slave);
}
static int rt1308_bus_config(struct sdw_slave *slave,
struct sdw_bus_params *params)
{
struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(&slave->dev);
int ret;
memcpy(&rt1308->params, params, sizeof(*params));
ret = rt1308_clock_config(&slave->dev);
if (ret < 0)
dev_err(&slave->dev, "Invalid clk config");
return ret;
}
static int rt1308_interrupt_callback(struct sdw_slave *slave,
struct sdw_slave_intr_status *status)
{
dev_dbg(&slave->dev,
"%s control_port_stat=%x", __func__, status->control_port);
return 0;
}
static int rt1308_classd_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt1308_sdw_priv *rt1308 =
snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
msleep(30);
snd_soc_component_update_bits(component,
RT1308_SDW_OFFSET | (RT1308_POWER_STATUS << 4),
0x3, 0x3);
msleep(40);
rt1308_apply_calib_params(rt1308);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component,
RT1308_SDW_OFFSET | (RT1308_POWER_STATUS << 4),
0x3, 0);
usleep_range(150000, 200000);
break;
default:
break;
}
return 0;
}
static const char * const rt1308_rx_data_ch_select[] = {
"LR",
"LL",
"RL",
"RR",
};
static SOC_ENUM_SINGLE_DECL(rt1308_rx_data_ch_enum,
RT1308_SDW_OFFSET | (RT1308_DATA_PATH << 4), 0,
rt1308_rx_data_ch_select);
static const struct snd_kcontrol_new rt1308_snd_controls[] = {
/* I2S Data Channel Selection */
SOC_ENUM("RX Channel Select", rt1308_rx_data_ch_enum),
};
static const struct snd_kcontrol_new rt1308_sto_dac_l =
SOC_DAPM_SINGLE_AUTODISABLE("Switch",
RT1308_SDW_OFFSET_BYTE3 | (RT1308_DAC_SET << 4),
RT1308_DVOL_MUTE_L_EN_SFT, 1, 1);
static const struct snd_kcontrol_new rt1308_sto_dac_r =
SOC_DAPM_SINGLE_AUTODISABLE("Switch",
RT1308_SDW_OFFSET_BYTE3 | (RT1308_DAC_SET << 4),
RT1308_DVOL_MUTE_R_EN_SFT, 1, 1);
static const struct snd_soc_dapm_widget rt1308_dapm_widgets[] = {
/* Audio Interface */
SND_SOC_DAPM_AIF_IN("AIF1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0),
/* Supply Widgets */
SND_SOC_DAPM_SUPPLY("MBIAS20U",
RT1308_SDW_OFFSET | (RT1308_POWER << 4), 7, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ALDO",
RT1308_SDW_OFFSET | (RT1308_POWER << 4), 6, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DBG",
RT1308_SDW_OFFSET | (RT1308_POWER << 4), 5, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DACL",
RT1308_SDW_OFFSET | (RT1308_POWER << 4), 4, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CLK25M",
RT1308_SDW_OFFSET | (RT1308_POWER << 4), 2, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC_R",
RT1308_SDW_OFFSET | (RT1308_POWER << 4), 1, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC_L",
RT1308_SDW_OFFSET | (RT1308_POWER << 4), 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC Power",
RT1308_SDW_OFFSET | (RT1308_POWER << 4), 3, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DLDO",
RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 5, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("VREF",
RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 4, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MIXER_R",
RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 2, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MIXER_L",
RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 1, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MBIAS4U",
RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PLL2_LDO",
RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 4, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PLL2B",
RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 3, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PLL2F",
RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 2, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PLL2F2",
RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 1, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PLL2B2",
RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 0, 0, NULL, 0),
/* Digital Interface */
SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SWITCH("DAC L", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_l),
SND_SOC_DAPM_SWITCH("DAC R", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_r),
/* Output Lines */
SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
rt1308_classd_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_OUTPUT("SPOL"),
SND_SOC_DAPM_OUTPUT("SPOR"),
};
static const struct snd_soc_dapm_route rt1308_dapm_routes[] = {
{ "DAC", NULL, "AIF1RX" },
{ "DAC", NULL, "MBIAS20U" },
{ "DAC", NULL, "ALDO" },
{ "DAC", NULL, "DBG" },
{ "DAC", NULL, "DACL" },
{ "DAC", NULL, "CLK25M" },
{ "DAC", NULL, "ADC_R" },
{ "DAC", NULL, "ADC_L" },
{ "DAC", NULL, "DLDO" },
{ "DAC", NULL, "VREF" },
{ "DAC", NULL, "MIXER_R" },
{ "DAC", NULL, "MIXER_L" },
{ "DAC", NULL, "MBIAS4U" },
{ "DAC", NULL, "PLL2_LDO" },
{ "DAC", NULL, "PLL2B" },
{ "DAC", NULL, "PLL2F" },
{ "DAC", NULL, "PLL2F2" },
{ "DAC", NULL, "PLL2B2" },
{ "DAC L", "Switch", "DAC" },
{ "DAC R", "Switch", "DAC" },
{ "DAC L", NULL, "DAC Power" },
{ "DAC R", NULL, "DAC Power" },
{ "CLASS D", NULL, "DAC L" },
{ "CLASS D", NULL, "DAC R" },
{ "SPOL", NULL, "CLASS D" },
{ "SPOR", NULL, "CLASS D" },
};
static int rt1308_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
int direction)
{
snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
return 0;
}
static void rt1308_sdw_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
snd_soc_dai_set_dma_data(dai, substream, NULL);
}
static int rt1308_sdw_set_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask,
unsigned int rx_mask,
int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
struct rt1308_sdw_priv *rt1308 =
snd_soc_component_get_drvdata(component);
if (tx_mask)
return -EINVAL;
if (slots > 2)
return -EINVAL;
rt1308->rx_mask = rx_mask;
rt1308->slots = slots;
/* slot_width is not used since it's irrelevant for SoundWire */
return 0;
}
static int rt1308_sdw_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt1308_sdw_priv *rt1308 =
snd_soc_component_get_drvdata(component);
struct sdw_stream_config stream_config = {0};
struct sdw_port_config port_config = {0};
struct sdw_stream_runtime *sdw_stream;
int retval;
dev_dbg(dai->dev, "%s %s", __func__, dai->name);
sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
if (!sdw_stream)
return -EINVAL;
if (!rt1308->sdw_slave)
return -EINVAL;
/* SoundWire specific configuration */
snd_sdw_params_to_config(substream, params, &stream_config, &port_config);
/* port 1 for playback */
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
port_config.num = 1;
else
return -EINVAL;
if (rt1308->slots) {
stream_config.ch_count = rt1308->slots;
port_config.ch_mask = rt1308->rx_mask;
}
retval = sdw_stream_add_slave(rt1308->sdw_slave, &stream_config,
&port_config, 1, sdw_stream);
if (retval) {
dev_err(dai->dev, "Unable to configure port\n");
return retval;
}
return retval;
}
static int rt1308_sdw_pcm_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt1308_sdw_priv *rt1308 =
snd_soc_component_get_drvdata(component);
struct sdw_stream_runtime *sdw_stream =
snd_soc_dai_get_dma_data(dai, substream);
if (!rt1308->sdw_slave)
return -EINVAL;
sdw_stream_remove_slave(rt1308->sdw_slave, sdw_stream);
return 0;
}
/*
* slave_ops: callbacks for get_clock_stop_mode, clock_stop and
* port_prep are not defined for now
*/
static const struct sdw_slave_ops rt1308_slave_ops = {
.read_prop = rt1308_read_prop,
.interrupt_callback = rt1308_interrupt_callback,
.update_status = rt1308_update_status,
.bus_config = rt1308_bus_config,
};
static int rt1308_sdw_parse_dt(struct rt1308_sdw_priv *rt1308, struct device *dev)
{
int ret = 0;
device_property_read_u32(dev, "realtek,bq-params-cnt", &rt1308->bq_params_cnt);
if (rt1308->bq_params_cnt) {
rt1308->bq_params = devm_kzalloc(dev, rt1308->bq_params_cnt, GFP_KERNEL);
if (!rt1308->bq_params) {
dev_err(dev, "Could not allocate bq_params memory\n");
ret = -ENOMEM;
} else {
ret = device_property_read_u8_array(dev, "realtek,bq-params", rt1308->bq_params, rt1308->bq_params_cnt);
if (ret < 0)
dev_err(dev, "Could not read list of realtek,bq-params\n");
}
}
dev_dbg(dev, "bq_params_cnt=%d\n", rt1308->bq_params_cnt);
return ret;
}
static int rt1308_sdw_component_probe(struct snd_soc_component *component)
{
struct rt1308_sdw_priv *rt1308 = snd_soc_component_get_drvdata(component);
int ret;
rt1308->component = component;
rt1308_sdw_parse_dt(rt1308, &rt1308->sdw_slave->dev);
if (!rt1308->first_hw_init)
return 0;
ret = pm_runtime_resume(component->dev);
if (ret < 0 && ret != -EACCES)
return ret;
/* apply BQ params */
rt1308_apply_bq_params(rt1308);
return 0;
}
static const struct snd_soc_component_driver soc_component_sdw_rt1308 = {
.probe = rt1308_sdw_component_probe,
.controls = rt1308_snd_controls,
.num_controls = ARRAY_SIZE(rt1308_snd_controls),
.dapm_widgets = rt1308_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt1308_dapm_widgets),
.dapm_routes = rt1308_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(rt1308_dapm_routes),
.endianness = 1,
};
static const struct snd_soc_dai_ops rt1308_aif_dai_ops = {
.hw_params = rt1308_sdw_hw_params,
.hw_free = rt1308_sdw_pcm_hw_free,
.set_stream = rt1308_set_sdw_stream,
.shutdown = rt1308_sdw_shutdown,
.set_tdm_slot = rt1308_sdw_set_tdm_slot,
};
#define RT1308_STEREO_RATES SNDRV_PCM_RATE_48000
#define RT1308_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE)
static struct snd_soc_dai_driver rt1308_sdw_dai[] = {
{
.name = "rt1308-aif",
.playback = {
.stream_name = "DP1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT1308_STEREO_RATES,
.formats = RT1308_FORMATS,
},
.ops = &rt1308_aif_dai_ops,
},
};
static int rt1308_sdw_init(struct device *dev, struct regmap *regmap,
struct sdw_slave *slave)
{
struct rt1308_sdw_priv *rt1308;
int ret;
rt1308 = devm_kzalloc(dev, sizeof(*rt1308), GFP_KERNEL);
if (!rt1308)
return -ENOMEM;
dev_set_drvdata(dev, rt1308);
rt1308->sdw_slave = slave;
rt1308->regmap = regmap;
regcache_cache_only(rt1308->regmap, true);
/*
* Mark hw_init to false
* HW init will be performed when device reports present
*/
rt1308->hw_init = false;
rt1308->first_hw_init = false;
ret = devm_snd_soc_register_component(dev,
&soc_component_sdw_rt1308,
rt1308_sdw_dai,
ARRAY_SIZE(rt1308_sdw_dai));
if (ret < 0)
return ret;
/* set autosuspend parameters */
pm_runtime_set_autosuspend_delay(dev, 3000);
pm_runtime_use_autosuspend(dev);
/* make sure the device does not suspend immediately */
pm_runtime_mark_last_busy(dev);
pm_runtime_enable(dev);
/* important note: the device is NOT tagged as 'active' and will remain
* 'suspended' until the hardware is enumerated/initialized. This is required
* to make sure the ASoC framework use of pm_runtime_get_sync() does not silently
* fail with -EACCESS because of race conditions between card creation and enumeration
*/
dev_dbg(dev, "%s\n", __func__);
return 0;
}
static int rt1308_sdw_probe(struct sdw_slave *slave,
const struct sdw_device_id *id)
{
struct regmap *regmap;
/* Regmap Initialization */
regmap = devm_regmap_init_sdw(slave, &rt1308_sdw_regmap);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return rt1308_sdw_init(&slave->dev, regmap, slave);
}
static int rt1308_sdw_remove(struct sdw_slave *slave)
{
pm_runtime_disable(&slave->dev);
return 0;
}
static const struct sdw_device_id rt1308_id[] = {
SDW_SLAVE_ENTRY_EXT(0x025d, 0x1308, 0x2, 0, 0),
{},
};
MODULE_DEVICE_TABLE(sdw, rt1308_id);
static int __maybe_unused rt1308_dev_suspend(struct device *dev)
{
struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev);
if (!rt1308->hw_init)
return 0;
regcache_cache_only(rt1308->regmap, true);
return 0;
}
#define RT1308_PROBE_TIMEOUT 5000
static int __maybe_unused rt1308_dev_resume(struct device *dev)
{
struct sdw_slave *slave = dev_to_sdw_dev(dev);
struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev);
unsigned long time;
if (!rt1308->first_hw_init)
return 0;
if (!slave->unattach_request)
goto regmap_sync;
time = wait_for_completion_timeout(&slave->initialization_complete,
msecs_to_jiffies(RT1308_PROBE_TIMEOUT));
if (!time) {
dev_err(&slave->dev, "Initialization not complete, timed out\n");
sdw_show_ping_status(slave->bus, true);
return -ETIMEDOUT;
}
regmap_sync:
slave->unattach_request = 0;
regcache_cache_only(rt1308->regmap, false);
regcache_sync_region(rt1308->regmap, 0xc000, 0xcfff);
return 0;
}
static const struct dev_pm_ops rt1308_pm = {
SET_SYSTEM_SLEEP_PM_OPS(rt1308_dev_suspend, rt1308_dev_resume)
SET_RUNTIME_PM_OPS(rt1308_dev_suspend, rt1308_dev_resume, NULL)
};
static struct sdw_driver rt1308_sdw_driver = {
.driver = {
.name = "rt1308",
.owner = THIS_MODULE,
.pm = &rt1308_pm,
},
.probe = rt1308_sdw_probe,
.remove = rt1308_sdw_remove,
.ops = &rt1308_slave_ops,
.id_table = rt1308_id,
};
module_sdw_driver(rt1308_sdw_driver);
MODULE_DESCRIPTION("ASoC RT1308 driver SDW");
MODULE_AUTHOR("Shuming Fan <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/rt1308-sdw.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Analog Devices ADAU1372 Audio Codec driver
*
* Copyright 2016 Analog Devices Inc.
* Author: Lars-Peter Clausen <[email protected]>
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/pm.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/tlv.h>
#include <sound/soc.h>
#include "adau1372.h"
#include "adau-utils.h"
struct adau1372 {
struct regmap *regmap;
void (*switch_mode)(struct device *dev);
bool use_pll;
bool enabled;
bool clock_provider;
struct snd_pcm_hw_constraint_list rate_constraints;
unsigned int slot_width;
struct clk *mclk;
struct gpio_desc *pd_gpio;
struct device *dev;
};
#define ADAU1372_REG_CLK_CTRL 0x00
#define ADAU1372_REG_PLL(x) (0x01 + (x))
#define ADAU1372_REG_DAC_SOURCE 0x11
#define ADAU1372_REG_SOUT_SOURCE_0_1 0x13
#define ADAU1372_REG_SOUT_SOURCE_2_3 0x14
#define ADAU1372_REG_SOUT_SOURCE_4_5 0x15
#define ADAU1372_REG_SOUT_SOURCE_6_7 0x16
#define ADAU1372_REG_ADC_SDATA_CH 0x17
#define ADAU1372_REG_ASRCO_SOURCE_0_1 0x18
#define ADAU1372_REG_ASRCO_SOURCE_2_3 0x19
#define ADAU1372_REG_ASRC_MODE 0x1a
#define ADAU1372_REG_ADC_CTRL0 0x1b
#define ADAU1372_REG_ADC_CTRL1 0x1c
#define ADAU1372_REG_ADC_CTRL2 0x1d
#define ADAU1372_REG_ADC_CTRL3 0x1e
#define ADAU1372_REG_ADC_VOL(x) (0x1f + (x))
#define ADAU1372_REG_PGA_CTRL(x) (0x23 + (x))
#define ADAU1372_REG_PGA_BOOST 0x28
#define ADAU1372_REG_MICBIAS 0x2d
#define ADAU1372_REG_DAC_CTRL 0x2e
#define ADAU1372_REG_DAC_VOL(x) (0x2f + (x))
#define ADAU1372_REG_OP_STAGE_MUTE 0x31
#define ADAU1372_REG_SAI0 0x32
#define ADAU1372_REG_SAI1 0x33
#define ADAU1372_REG_SOUT_CTRL 0x34
#define ADAU1372_REG_MODE_MP(x) (0x38 + (x))
#define ADAU1372_REG_OP_STAGE_CTRL 0x43
#define ADAU1372_REG_DECIM_PWR 0x44
#define ADAU1372_REG_INTERP_PWR 0x45
#define ADAU1372_REG_BIAS_CTRL0 0x46
#define ADAU1372_REG_BIAS_CTRL1 0x47
#define ADAU1372_CLK_CTRL_PLL_EN BIT(7)
#define ADAU1372_CLK_CTRL_XTAL_DIS BIT(4)
#define ADAU1372_CLK_CTRL_CLKSRC BIT(3)
#define ADAU1372_CLK_CTRL_CC_MDIV BIT(1)
#define ADAU1372_CLK_CTRL_MCLK_EN BIT(0)
#define ADAU1372_SAI0_DELAY1 (0x0 << 6)
#define ADAU1372_SAI0_DELAY0 (0x1 << 6)
#define ADAU1372_SAI0_DELAY_MASK (0x3 << 6)
#define ADAU1372_SAI0_SAI_I2S (0x0 << 4)
#define ADAU1372_SAI0_SAI_TDM2 (0x1 << 4)
#define ADAU1372_SAI0_SAI_TDM4 (0x2 << 4)
#define ADAU1372_SAI0_SAI_TDM8 (0x3 << 4)
#define ADAU1372_SAI0_SAI_MASK (0x3 << 4)
#define ADAU1372_SAI0_FS_48 0x0
#define ADAU1372_SAI0_FS_8 0x1
#define ADAU1372_SAI0_FS_12 0x2
#define ADAU1372_SAI0_FS_16 0x3
#define ADAU1372_SAI0_FS_24 0x4
#define ADAU1372_SAI0_FS_32 0x5
#define ADAU1372_SAI0_FS_96 0x6
#define ADAU1372_SAI0_FS_192 0x7
#define ADAU1372_SAI0_FS_MASK 0xf
#define ADAU1372_SAI1_TDM_TS BIT(7)
#define ADAU1372_SAI1_BCLK_TDMC BIT(6)
#define ADAU1372_SAI1_LR_MODE BIT(5)
#define ADAU1372_SAI1_LR_POL BIT(4)
#define ADAU1372_SAI1_BCLKRATE BIT(2)
#define ADAU1372_SAI1_BCLKEDGE BIT(1)
#define ADAU1372_SAI1_MS BIT(0)
static const unsigned int adau1372_rates[] = {
[ADAU1372_SAI0_FS_8] = 8000,
[ADAU1372_SAI0_FS_12] = 12000,
[ADAU1372_SAI0_FS_16] = 16000,
[ADAU1372_SAI0_FS_24] = 24000,
[ADAU1372_SAI0_FS_32] = 32000,
[ADAU1372_SAI0_FS_48] = 48000,
[ADAU1372_SAI0_FS_96] = 96000,
[ADAU1372_SAI0_FS_192] = 192000,
};
/* 8k, 12k, 24k, 48k */
#define ADAU1372_RATE_MASK_TDM8 0x17
/* + 16k, 96k */
#define ADAU1372_RATE_MASK_TDM4_MASTER (ADAU1372_RATE_MASK_TDM8 | 0x48 | 0x20)
/* +32k */
#define ADAU1372_RATE_MASK_TDM4 (ADAU1372_RATE_MASK_TDM4_MASTER | 0x20)
/* + 192k */
#define ADAU1372_RATE_MASK_TDM2 (ADAU1372_RATE_MASK_TDM4 | 0x80)
static const DECLARE_TLV_DB_MINMAX(adau1372_digital_tlv, -9563, 0);
static const DECLARE_TLV_DB_SCALE(adau1372_pga_tlv, -1200, 75, 0);
static const DECLARE_TLV_DB_SCALE(adau1372_pga_boost_tlv, 0, 1000, 0);
static const char * const adau1372_bias_text[] = {
"Normal operation", "Extreme power saving", "Enhanced performance",
"Power saving",
};
static const unsigned int adau1372_bias_adc_values[] = {
0, 2, 3,
};
static const char * const adau1372_bias_adc_text[] = {
"Normal operation", "Enhanced performance", "Power saving",
};
static const char * const adau1372_bias_dac_text[] = {
"Normal operation", "Power saving", "Superior performance",
"Enhanced performance",
};
static SOC_ENUM_SINGLE_DECL(adau1372_bias_hp_enum,
ADAU1372_REG_BIAS_CTRL0, 6, adau1372_bias_text);
static SOC_ENUM_SINGLE_DECL(adau1372_bias_afe0_1_enum,
ADAU1372_REG_BIAS_CTRL0, 4, adau1372_bias_text);
static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_bias_adc2_3_enum,
ADAU1372_REG_BIAS_CTRL0, 2, 0x3, adau1372_bias_adc_text,
adau1372_bias_adc_values);
static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_bias_adc0_1_enum,
ADAU1372_REG_BIAS_CTRL0, 0, 0x3, adau1372_bias_adc_text,
adau1372_bias_adc_values);
static SOC_ENUM_SINGLE_DECL(adau1372_bias_afe2_3_enum,
ADAU1372_REG_BIAS_CTRL1, 4, adau1372_bias_text);
static SOC_ENUM_SINGLE_DECL(adau1372_bias_mic_enum,
ADAU1372_REG_BIAS_CTRL1, 2, adau1372_bias_text);
static SOC_ENUM_SINGLE_DECL(adau1372_bias_dac_enum,
ADAU1372_REG_BIAS_CTRL1, 0, adau1372_bias_dac_text);
static const char * const adau1372_hpf_text[] = {
"Off",
"1 Hz",
"4 Hz",
"8 Hz",
};
static SOC_ENUM_SINGLE_DECL(adau1372_hpf0_1_enum, ADAU1372_REG_ADC_CTRL2, 5,
adau1372_hpf_text);
static SOC_ENUM_SINGLE_DECL(adau1372_hpf2_3_enum, ADAU1372_REG_ADC_CTRL3, 5,
adau1372_hpf_text);
static const struct snd_kcontrol_new adau1372_controls[] = {
SOC_SINGLE_TLV("ADC 0 Capture Volume", ADAU1372_REG_ADC_VOL(0),
0, 0xff, 1, adau1372_digital_tlv),
SOC_SINGLE_TLV("ADC 1 Capture Volume", ADAU1372_REG_ADC_VOL(1),
0, 0xff, 1, adau1372_digital_tlv),
SOC_SINGLE_TLV("ADC 2 Capture Volume", ADAU1372_REG_ADC_VOL(2),
0, 0xff, 1, adau1372_digital_tlv),
SOC_SINGLE_TLV("ADC 3 Capture Volume", ADAU1372_REG_ADC_VOL(3),
0, 0xff, 1, adau1372_digital_tlv),
SOC_SINGLE("ADC 0 Capture Switch", ADAU1372_REG_ADC_CTRL0, 3, 1, 1),
SOC_SINGLE("ADC 1 Capture Switch", ADAU1372_REG_ADC_CTRL0, 4, 1, 1),
SOC_SINGLE("ADC 2 Capture Switch", ADAU1372_REG_ADC_CTRL1, 3, 1, 1),
SOC_SINGLE("ADC 3 Capture Switch", ADAU1372_REG_ADC_CTRL1, 4, 1, 1),
SOC_ENUM("ADC 0+1 High-Pass-Filter", adau1372_hpf0_1_enum),
SOC_ENUM("ADC 2+3 High-Pass-Filter", adau1372_hpf2_3_enum),
SOC_SINGLE_TLV("PGA 0 Capture Volume", ADAU1372_REG_PGA_CTRL(0),
0, 0x3f, 0, adau1372_pga_tlv),
SOC_SINGLE_TLV("PGA 1 Capture Volume", ADAU1372_REG_PGA_CTRL(1),
0, 0x3f, 0, adau1372_pga_tlv),
SOC_SINGLE_TLV("PGA 2 Capture Volume", ADAU1372_REG_PGA_CTRL(2),
0, 0x3f, 0, adau1372_pga_tlv),
SOC_SINGLE_TLV("PGA 3 Capture Volume", ADAU1372_REG_PGA_CTRL(3),
0, 0x3f, 0, adau1372_pga_tlv),
SOC_SINGLE_TLV("PGA 0 Boost Capture Volume", ADAU1372_REG_PGA_BOOST,
0, 1, 0, adau1372_pga_boost_tlv),
SOC_SINGLE_TLV("PGA 1 Boost Capture Volume", ADAU1372_REG_PGA_BOOST,
1, 1, 0, adau1372_pga_boost_tlv),
SOC_SINGLE_TLV("PGA 2 Boost Capture Volume", ADAU1372_REG_PGA_BOOST,
2, 1, 0, adau1372_pga_boost_tlv),
SOC_SINGLE_TLV("PGA 3 Boost Capture Volume", ADAU1372_REG_PGA_BOOST,
3, 1, 0, adau1372_pga_boost_tlv),
SOC_SINGLE("PGA 0 Capture Switch", ADAU1372_REG_PGA_CTRL(0), 7, 1, 0),
SOC_SINGLE("PGA 1 Capture Switch", ADAU1372_REG_PGA_CTRL(1), 7, 1, 0),
SOC_SINGLE("PGA 2 Capture Switch", ADAU1372_REG_PGA_CTRL(2), 7, 1, 0),
SOC_SINGLE("PGA 3 Capture Switch", ADAU1372_REG_PGA_CTRL(3), 7, 1, 0),
SOC_SINGLE_TLV("DAC 0 Playback Volume", ADAU1372_REG_DAC_VOL(0),
0, 0xff, 1, adau1372_digital_tlv),
SOC_SINGLE_TLV("DAC 1 Playback Volume", ADAU1372_REG_DAC_VOL(1),
0, 0xff, 1, adau1372_digital_tlv),
SOC_SINGLE("DAC 0 Playback Switch", ADAU1372_REG_DAC_CTRL, 3, 1, 1),
SOC_SINGLE("DAC 1 Playback Switch", ADAU1372_REG_DAC_CTRL, 4, 1, 1),
SOC_ENUM("Headphone Bias", adau1372_bias_hp_enum),
SOC_ENUM("Microphone Bias", adau1372_bias_mic_enum),
SOC_ENUM("AFE 0+1 Bias", adau1372_bias_afe0_1_enum),
SOC_ENUM("AFE 2+3 Bias", adau1372_bias_afe2_3_enum),
SOC_ENUM("ADC 0+1 Bias", adau1372_bias_adc0_1_enum),
SOC_ENUM("ADC 2+3 Bias", adau1372_bias_adc2_3_enum),
SOC_ENUM("DAC 0+1 Bias", adau1372_bias_dac_enum),
};
static const char * const adau1372_decimator_mux_text[] = {
"ADC",
"DMIC",
};
static SOC_ENUM_SINGLE_DECL(adau1372_decimator0_1_mux_enum, ADAU1372_REG_ADC_CTRL2,
2, adau1372_decimator_mux_text);
static const struct snd_kcontrol_new adau1372_decimator0_1_mux_control =
SOC_DAPM_ENUM("Decimator 0+1 Capture Mux", adau1372_decimator0_1_mux_enum);
static SOC_ENUM_SINGLE_DECL(adau1372_decimator2_3_mux_enum, ADAU1372_REG_ADC_CTRL3,
2, adau1372_decimator_mux_text);
static const struct snd_kcontrol_new adau1372_decimator2_3_mux_control =
SOC_DAPM_ENUM("Decimator 2+3 Capture Mux", adau1372_decimator2_3_mux_enum);
static const unsigned int adau1372_asrco_mux_values[] = {
4, 5, 6, 7,
};
static const char * const adau1372_asrco_mux_text[] = {
"Decimator0",
"Decimator1",
"Decimator2",
"Decimator3",
};
static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_asrco0_mux_enum, ADAU1372_REG_ASRCO_SOURCE_0_1,
0, 0xf, adau1372_asrco_mux_text, adau1372_asrco_mux_values);
static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_asrco1_mux_enum, ADAU1372_REG_ASRCO_SOURCE_0_1,
4, 0xf, adau1372_asrco_mux_text, adau1372_asrco_mux_values);
static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_asrco2_mux_enum, ADAU1372_REG_ASRCO_SOURCE_2_3,
0, 0xf, adau1372_asrco_mux_text, adau1372_asrco_mux_values);
static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_asrco3_mux_enum, ADAU1372_REG_ASRCO_SOURCE_2_3,
4, 0xf, adau1372_asrco_mux_text, adau1372_asrco_mux_values);
static const struct snd_kcontrol_new adau1372_asrco0_mux_control =
SOC_DAPM_ENUM("Output ASRC0 Capture Mux", adau1372_asrco0_mux_enum);
static const struct snd_kcontrol_new adau1372_asrco1_mux_control =
SOC_DAPM_ENUM("Output ASRC1 Capture Mux", adau1372_asrco1_mux_enum);
static const struct snd_kcontrol_new adau1372_asrco2_mux_control =
SOC_DAPM_ENUM("Output ASRC2 Capture Mux", adau1372_asrco2_mux_enum);
static const struct snd_kcontrol_new adau1372_asrco3_mux_control =
SOC_DAPM_ENUM("Output ASRC3 Capture Mux", adau1372_asrco3_mux_enum);
static const unsigned int adau1372_sout_mux_values[] = {
4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
};
static const char * const adau1372_sout_mux_text[] = {
"Output ASRC0",
"Output ASRC1",
"Output ASRC2",
"Output ASRC3",
"Serial Input 0",
"Serial Input 1",
"Serial Input 2",
"Serial Input 3",
"Serial Input 4",
"Serial Input 5",
"Serial Input 6",
"Serial Input 7",
};
static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout0_mux_enum, ADAU1372_REG_SOUT_SOURCE_0_1,
0, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout1_mux_enum, ADAU1372_REG_SOUT_SOURCE_0_1,
4, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout2_mux_enum, ADAU1372_REG_SOUT_SOURCE_2_3,
0, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout3_mux_enum, ADAU1372_REG_SOUT_SOURCE_2_3,
4, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout4_mux_enum, ADAU1372_REG_SOUT_SOURCE_4_5,
0, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout5_mux_enum, ADAU1372_REG_SOUT_SOURCE_4_5,
4, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout6_mux_enum, ADAU1372_REG_SOUT_SOURCE_6_7,
0, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout7_mux_enum, ADAU1372_REG_SOUT_SOURCE_6_7,
4, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
static const struct snd_kcontrol_new adau1372_sout0_mux_control =
SOC_DAPM_ENUM("Serial Output 0 Capture Mux", adau1372_sout0_mux_enum);
static const struct snd_kcontrol_new adau1372_sout1_mux_control =
SOC_DAPM_ENUM("Serial Output 1 Capture Mux", adau1372_sout1_mux_enum);
static const struct snd_kcontrol_new adau1372_sout2_mux_control =
SOC_DAPM_ENUM("Serial Output 2 Capture Mux", adau1372_sout2_mux_enum);
static const struct snd_kcontrol_new adau1372_sout3_mux_control =
SOC_DAPM_ENUM("Serial Output 3 Capture Mux", adau1372_sout3_mux_enum);
static const struct snd_kcontrol_new adau1372_sout4_mux_control =
SOC_DAPM_ENUM("Serial Output 4 Capture Mux", adau1372_sout4_mux_enum);
static const struct snd_kcontrol_new adau1372_sout5_mux_control =
SOC_DAPM_ENUM("Serial Output 5 Capture Mux", adau1372_sout5_mux_enum);
static const struct snd_kcontrol_new adau1372_sout6_mux_control =
SOC_DAPM_ENUM("Serial Output 6 Capture Mux", adau1372_sout6_mux_enum);
static const struct snd_kcontrol_new adau1372_sout7_mux_control =
SOC_DAPM_ENUM("Serial Output 7 Capture Mux", adau1372_sout7_mux_enum);
static const char * const adau1372_asrci_mux_text[] = {
"Serial Input 0+1",
"Serial Input 2+3",
"Serial Input 4+5",
"Serial Input 6+7",
};
static SOC_ENUM_SINGLE_DECL(adau1372_asrci_mux_enum,
ADAU1372_REG_ASRC_MODE, 2, adau1372_asrci_mux_text);
static const struct snd_kcontrol_new adau1372_asrci_mux_control =
SOC_DAPM_ENUM("Input ASRC Playback Mux", adau1372_asrci_mux_enum);
static const unsigned int adau1372_dac_mux_values[] = {
12, 13
};
static const char * const adau1372_dac_mux_text[] = {
"Input ASRC0",
"Input ASRC1",
};
static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_dac0_mux_enum, ADAU1372_REG_DAC_SOURCE,
0, 0xf, adau1372_dac_mux_text, adau1372_dac_mux_values);
static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_dac1_mux_enum, ADAU1372_REG_DAC_SOURCE,
4, 0xf, adau1372_dac_mux_text, adau1372_dac_mux_values);
static const struct snd_kcontrol_new adau1372_dac0_mux_control =
SOC_DAPM_ENUM("DAC 0 Playback Mux", adau1372_dac0_mux_enum);
static const struct snd_kcontrol_new adau1372_dac1_mux_control =
SOC_DAPM_ENUM("DAC 1 Playback Mux", adau1372_dac1_mux_enum);
static const struct snd_soc_dapm_widget adau1372_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("AIN0"),
SND_SOC_DAPM_INPUT("AIN1"),
SND_SOC_DAPM_INPUT("AIN2"),
SND_SOC_DAPM_INPUT("AIN3"),
SND_SOC_DAPM_INPUT("DMIC0_1"),
SND_SOC_DAPM_INPUT("DMIC2_3"),
SND_SOC_DAPM_SUPPLY("MICBIAS0", ADAU1372_REG_MICBIAS, 4, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS1", ADAU1372_REG_MICBIAS, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA("PGA0", ADAU1372_REG_PGA_CTRL(0), 6, 1, NULL, 0),
SND_SOC_DAPM_PGA("PGA1", ADAU1372_REG_PGA_CTRL(1), 6, 1, NULL, 0),
SND_SOC_DAPM_PGA("PGA2", ADAU1372_REG_PGA_CTRL(2), 6, 1, NULL, 0),
SND_SOC_DAPM_PGA("PGA3", ADAU1372_REG_PGA_CTRL(3), 6, 1, NULL, 0),
SND_SOC_DAPM_ADC("ADC0", NULL, ADAU1372_REG_ADC_CTRL2, 0, 0),
SND_SOC_DAPM_ADC("ADC1", NULL, ADAU1372_REG_ADC_CTRL2, 1, 0),
SND_SOC_DAPM_ADC("ADC2", NULL, ADAU1372_REG_ADC_CTRL3, 0, 0),
SND_SOC_DAPM_ADC("ADC3", NULL, ADAU1372_REG_ADC_CTRL3, 1, 0),
SND_SOC_DAPM_SUPPLY("ADC0 Filter", ADAU1372_REG_DECIM_PWR, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC1 Filter", ADAU1372_REG_DECIM_PWR, 1, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC2 Filter", ADAU1372_REG_DECIM_PWR, 2, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC3 Filter", ADAU1372_REG_DECIM_PWR, 3, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Output ASRC0 Decimator", ADAU1372_REG_DECIM_PWR, 4, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Output ASRC1 Decimator", ADAU1372_REG_DECIM_PWR, 5, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Output ASRC2 Decimator", ADAU1372_REG_DECIM_PWR, 6, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Output ASRC3 Decimator", ADAU1372_REG_DECIM_PWR, 7, 0, NULL, 0),
SND_SOC_DAPM_MUX("Decimator0 Mux", SND_SOC_NOPM, 0, 0, &adau1372_decimator0_1_mux_control),
SND_SOC_DAPM_MUX("Decimator1 Mux", SND_SOC_NOPM, 0, 0, &adau1372_decimator0_1_mux_control),
SND_SOC_DAPM_MUX("Decimator2 Mux", SND_SOC_NOPM, 0, 0, &adau1372_decimator2_3_mux_control),
SND_SOC_DAPM_MUX("Decimator3 Mux", SND_SOC_NOPM, 0, 0, &adau1372_decimator2_3_mux_control),
SND_SOC_DAPM_MUX("Output ASRC0 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrco0_mux_control),
SND_SOC_DAPM_MUX("Output ASRC1 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrco1_mux_control),
SND_SOC_DAPM_MUX("Output ASRC2 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrco2_mux_control),
SND_SOC_DAPM_MUX("Output ASRC3 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrco3_mux_control),
SND_SOC_DAPM_MUX("Serial Output 0 Capture Mux", SND_SOC_NOPM, 0, 0,
&adau1372_sout0_mux_control),
SND_SOC_DAPM_MUX("Serial Output 1 Capture Mux", SND_SOC_NOPM, 0, 0,
&adau1372_sout1_mux_control),
SND_SOC_DAPM_MUX("Serial Output 2 Capture Mux", SND_SOC_NOPM, 0, 0,
&adau1372_sout2_mux_control),
SND_SOC_DAPM_MUX("Serial Output 3 Capture Mux", SND_SOC_NOPM, 0, 0,
&adau1372_sout3_mux_control),
SND_SOC_DAPM_MUX("Serial Output 4 Capture Mux", SND_SOC_NOPM, 0, 0,
&adau1372_sout4_mux_control),
SND_SOC_DAPM_MUX("Serial Output 5 Capture Mux", SND_SOC_NOPM, 0, 0,
&adau1372_sout5_mux_control),
SND_SOC_DAPM_MUX("Serial Output 6 Capture Mux", SND_SOC_NOPM, 0, 0,
&adau1372_sout6_mux_control),
SND_SOC_DAPM_MUX("Serial Output 7 Capture Mux", SND_SOC_NOPM, 0, 0,
&adau1372_sout7_mux_control),
SND_SOC_DAPM_AIF_IN("Serial Input 0", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("Serial Input 1", NULL, 1, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("Serial Input 2", NULL, 2, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("Serial Input 3", NULL, 3, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("Serial Input 4", NULL, 4, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("Serial Input 5", NULL, 5, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("Serial Input 6", NULL, 6, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("Serial Input 7", NULL, 7, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("Serial Output 0", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("Serial Output 1", NULL, 1, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("Serial Output 2", NULL, 2, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("Serial Output 3", NULL, 3, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("Serial Output 4", NULL, 4, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("Serial Output 5", NULL, 5, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("Serial Output 6", NULL, 6, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("Serial Output 7", NULL, 7, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SUPPLY("Output ASRC Supply", ADAU1372_REG_ASRC_MODE, 1, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Input ASRC Supply", ADAU1372_REG_ASRC_MODE, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC1 Modulator", ADAU1372_REG_INTERP_PWR, 3, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC0 Modulator", ADAU1372_REG_INTERP_PWR, 2, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Input ASRC1 Interpolator", ADAU1372_REG_INTERP_PWR, 1, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Input ASRC0 Interpolator", ADAU1372_REG_INTERP_PWR, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX("Input ASRC0 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrci_mux_control),
SND_SOC_DAPM_MUX("Input ASRC1 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrci_mux_control),
SND_SOC_DAPM_MUX("DAC 0 Mux", SND_SOC_NOPM, 0, 0, &adau1372_dac0_mux_control),
SND_SOC_DAPM_MUX("DAC 1 Mux", SND_SOC_NOPM, 0, 0, &adau1372_dac1_mux_control),
SND_SOC_DAPM_DAC("DAC0", NULL, ADAU1372_REG_DAC_CTRL, 0, 0),
SND_SOC_DAPM_DAC("DAC1", NULL, ADAU1372_REG_DAC_CTRL, 1, 0),
SND_SOC_DAPM_OUT_DRV("OP_STAGE_LP", ADAU1372_REG_OP_STAGE_CTRL, 0, 1, NULL, 0),
SND_SOC_DAPM_OUT_DRV("OP_STAGE_LN", ADAU1372_REG_OP_STAGE_CTRL, 1, 1, NULL, 0),
SND_SOC_DAPM_OUT_DRV("OP_STAGE_RP", ADAU1372_REG_OP_STAGE_CTRL, 2, 1, NULL, 0),
SND_SOC_DAPM_OUT_DRV("OP_STAGE_RN", ADAU1372_REG_OP_STAGE_CTRL, 3, 1, NULL, 0),
SND_SOC_DAPM_OUTPUT("HPOUTL"),
SND_SOC_DAPM_OUTPUT("HPOUTR"),
};
#define ADAU1372_SOUT_ROUTES(x) \
{ "Serial Output " #x " Capture Mux", "Output ASRC0", "Output ASRC0 Mux" }, \
{ "Serial Output " #x " Capture Mux", "Output ASRC1", "Output ASRC1 Mux" }, \
{ "Serial Output " #x " Capture Mux", "Output ASRC2", "Output ASRC2 Mux" }, \
{ "Serial Output " #x " Capture Mux", "Output ASRC3", "Output ASRC3 Mux" }, \
{ "Serial Output " #x " Capture Mux", "Serial Input 0", "Serial Input 0" }, \
{ "Serial Output " #x " Capture Mux", "Serial Input 1", "Serial Input 1" }, \
{ "Serial Output " #x " Capture Mux", "Serial Input 2", "Serial Input 2" }, \
{ "Serial Output " #x " Capture Mux", "Serial Input 3", "Serial Input 3" }, \
{ "Serial Output " #x " Capture Mux", "Serial Input 4", "Serial Input 4" }, \
{ "Serial Output " #x " Capture Mux", "Serial Input 5", "Serial Input 5" }, \
{ "Serial Output " #x " Capture Mux", "Serial Input 6", "Serial Input 6" }, \
{ "Serial Output " #x " Capture Mux", "Serial Input 7", "Serial Input 7" }, \
{ "Serial Output " #x, NULL, "Serial Output " #x " Capture Mux" }, \
{ "Capture", NULL, "Serial Output " #x }
#define ADAU1372_ASRCO_ROUTES(x) \
{ "Output ASRC" #x " Mux", "Decimator0", "Decimator0 Mux" }, \
{ "Output ASRC" #x " Mux", "Decimator1", "Decimator1 Mux" }, \
{ "Output ASRC" #x " Mux", "Decimator2", "Decimator2 Mux" }, \
{ "Output ASRC" #x " Mux", "Decimator3", "Decimator3 Mux" }
static const struct snd_soc_dapm_route adau1372_dapm_routes[] = {
{ "PGA0", NULL, "AIN0" },
{ "PGA1", NULL, "AIN1" },
{ "PGA2", NULL, "AIN2" },
{ "PGA3", NULL, "AIN3" },
{ "ADC0", NULL, "PGA0" },
{ "ADC1", NULL, "PGA1" },
{ "ADC2", NULL, "PGA2" },
{ "ADC3", NULL, "PGA3" },
{ "Decimator0 Mux", "ADC", "ADC0" },
{ "Decimator1 Mux", "ADC", "ADC1" },
{ "Decimator2 Mux", "ADC", "ADC2" },
{ "Decimator3 Mux", "ADC", "ADC3" },
{ "Decimator0 Mux", "DMIC", "DMIC0_1" },
{ "Decimator1 Mux", "DMIC", "DMIC0_1" },
{ "Decimator2 Mux", "DMIC", "DMIC2_3" },
{ "Decimator3 Mux", "DMIC", "DMIC2_3" },
{ "Decimator0 Mux", NULL, "ADC0 Filter" },
{ "Decimator1 Mux", NULL, "ADC1 Filter" },
{ "Decimator2 Mux", NULL, "ADC2 Filter" },
{ "Decimator3 Mux", NULL, "ADC3 Filter" },
{ "Output ASRC0 Mux", NULL, "Output ASRC Supply" },
{ "Output ASRC1 Mux", NULL, "Output ASRC Supply" },
{ "Output ASRC2 Mux", NULL, "Output ASRC Supply" },
{ "Output ASRC3 Mux", NULL, "Output ASRC Supply" },
{ "Output ASRC0 Mux", NULL, "Output ASRC0 Decimator" },
{ "Output ASRC1 Mux", NULL, "Output ASRC1 Decimator" },
{ "Output ASRC2 Mux", NULL, "Output ASRC2 Decimator" },
{ "Output ASRC3 Mux", NULL, "Output ASRC3 Decimator" },
ADAU1372_ASRCO_ROUTES(0),
ADAU1372_ASRCO_ROUTES(1),
ADAU1372_ASRCO_ROUTES(2),
ADAU1372_ASRCO_ROUTES(3),
ADAU1372_SOUT_ROUTES(0),
ADAU1372_SOUT_ROUTES(1),
ADAU1372_SOUT_ROUTES(2),
ADAU1372_SOUT_ROUTES(3),
ADAU1372_SOUT_ROUTES(4),
ADAU1372_SOUT_ROUTES(5),
ADAU1372_SOUT_ROUTES(6),
ADAU1372_SOUT_ROUTES(7),
{ "Serial Input 0", NULL, "Playback" },
{ "Serial Input 1", NULL, "Playback" },
{ "Serial Input 2", NULL, "Playback" },
{ "Serial Input 3", NULL, "Playback" },
{ "Serial Input 4", NULL, "Playback" },
{ "Serial Input 5", NULL, "Playback" },
{ "Serial Input 6", NULL, "Playback" },
{ "Serial Input 7", NULL, "Playback" },
{ "Input ASRC0 Mux", "Serial Input 0+1", "Serial Input 0" },
{ "Input ASRC1 Mux", "Serial Input 0+1", "Serial Input 1" },
{ "Input ASRC0 Mux", "Serial Input 2+3", "Serial Input 2" },
{ "Input ASRC1 Mux", "Serial Input 2+3", "Serial Input 3" },
{ "Input ASRC0 Mux", "Serial Input 4+5", "Serial Input 4" },
{ "Input ASRC1 Mux", "Serial Input 4+5", "Serial Input 5" },
{ "Input ASRC0 Mux", "Serial Input 6+7", "Serial Input 6" },
{ "Input ASRC1 Mux", "Serial Input 6+7", "Serial Input 7" },
{ "Input ASRC0 Mux", NULL, "Input ASRC Supply" },
{ "Input ASRC1 Mux", NULL, "Input ASRC Supply" },
{ "Input ASRC0 Mux", NULL, "Input ASRC0 Interpolator" },
{ "Input ASRC1 Mux", NULL, "Input ASRC1 Interpolator" },
{ "DAC 0 Mux", "Input ASRC0", "Input ASRC0 Mux" },
{ "DAC 0 Mux", "Input ASRC1", "Input ASRC1 Mux" },
{ "DAC 1 Mux", "Input ASRC0", "Input ASRC0 Mux" },
{ "DAC 1 Mux", "Input ASRC1", "Input ASRC1 Mux" },
{ "DAC0", NULL, "DAC 0 Mux" },
{ "DAC1", NULL, "DAC 1 Mux" },
{ "DAC0", NULL, "DAC0 Modulator" },
{ "DAC1", NULL, "DAC1 Modulator" },
{ "OP_STAGE_LP", NULL, "DAC0" },
{ "OP_STAGE_LN", NULL, "DAC0" },
{ "OP_STAGE_RP", NULL, "DAC1" },
{ "OP_STAGE_RN", NULL, "DAC1" },
{ "HPOUTL", NULL, "OP_STAGE_LP" },
{ "HPOUTL", NULL, "OP_STAGE_LN" },
{ "HPOUTR", NULL, "OP_STAGE_RP" },
{ "HPOUTR", NULL, "OP_STAGE_RN" },
};
static int adau1372_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
unsigned int sai0 = 0, sai1 = 0;
bool invert_lrclk = false;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
adau1372->clock_provider = true;
sai1 |= ADAU1372_SAI1_MS;
break;
case SND_SOC_DAIFMT_CBC_CFC:
adau1372->clock_provider = false;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
invert_lrclk = false;
break;
case SND_SOC_DAIFMT_NB_IF:
invert_lrclk = true;
break;
case SND_SOC_DAIFMT_IB_NF:
invert_lrclk = false;
sai1 |= ADAU1372_SAI1_BCLKEDGE;
break;
case SND_SOC_DAIFMT_IB_IF:
invert_lrclk = true;
sai1 |= ADAU1372_SAI1_BCLKEDGE;
break;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
sai0 |= ADAU1372_SAI0_DELAY1;
break;
case SND_SOC_DAIFMT_LEFT_J:
sai0 |= ADAU1372_SAI0_DELAY0;
invert_lrclk = !invert_lrclk;
break;
case SND_SOC_DAIFMT_DSP_A:
sai0 |= ADAU1372_SAI0_DELAY1;
sai1 |= ADAU1372_SAI1_LR_MODE;
break;
case SND_SOC_DAIFMT_DSP_B:
sai0 |= ADAU1372_SAI0_DELAY0;
sai1 |= ADAU1372_SAI1_LR_MODE;
break;
}
if (invert_lrclk)
sai1 |= ADAU1372_SAI1_LR_POL;
regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0, ADAU1372_SAI0_DELAY_MASK, sai0);
regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1,
ADAU1372_SAI1_MS | ADAU1372_SAI1_BCLKEDGE |
ADAU1372_SAI1_LR_MODE | ADAU1372_SAI1_LR_POL, sai1);
return 0;
}
static int adau1372_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
unsigned int rate = params_rate(params);
unsigned int slot_width;
unsigned int sai0, sai1;
unsigned int i;
for (i = 0; i < ARRAY_SIZE(adau1372_rates); i++) {
if (rate == adau1372_rates[i])
break;
}
if (i == ARRAY_SIZE(adau1372_rates))
return -EINVAL;
sai0 = i;
slot_width = adau1372->slot_width;
if (slot_width == 0)
slot_width = params_width(params);
switch (slot_width) {
case 16:
sai1 = ADAU1372_SAI1_BCLKRATE;
break;
case 24:
case 32:
sai1 = 0;
break;
default:
return -EINVAL;
}
regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0, ADAU1372_SAI0_FS_MASK, sai0);
regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1, ADAU1372_SAI1_BCLKRATE, sai1);
return 0;
}
static int adau1372_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int width)
{
struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
unsigned int sai0, sai1;
/* I2S mode */
if (slots == 0) {
/* The other settings dont matter in I2S mode */
regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0,
ADAU1372_SAI0_SAI_MASK, ADAU1372_SAI0_SAI_I2S);
adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM2;
adau1372->slot_width = 0;
return 0;
}
/* We have 8 channels anything outside that is not supported */
if ((tx_mask & ~0xff) != 0 || (rx_mask & ~0xff) != 0)
return -EINVAL;
switch (width) {
case 16:
sai1 = ADAU1372_SAI1_BCLK_TDMC;
break;
case 24:
case 32:
sai1 = 0;
break;
default:
return -EINVAL;
}
switch (slots) {
case 2:
sai0 = ADAU1372_SAI0_SAI_TDM2;
adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM2;
break;
case 4:
sai0 = ADAU1372_SAI0_SAI_TDM4;
if (adau1372->clock_provider)
adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM4_MASTER;
else
adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM4;
break;
case 8:
sai0 = ADAU1372_SAI0_SAI_TDM8;
adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM8;
break;
default:
return -EINVAL;
}
adau1372->slot_width = width;
regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0, ADAU1372_SAI0_SAI_MASK, sai0);
regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1, ADAU1372_SAI1_BCLK_TDMC, sai1);
/* Mask is inverted in hardware */
regmap_write(adau1372->regmap, ADAU1372_REG_SOUT_CTRL, ~tx_mask);
return 0;
}
static int adau1372_set_tristate(struct snd_soc_dai *dai, int tristate)
{
struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
unsigned int sai1;
if (tristate)
sai1 = ADAU1372_SAI1_TDM_TS;
else
sai1 = 0;
return regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1, ADAU1372_SAI1_TDM_TS, sai1);
}
static int adau1372_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
{
struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
snd_pcm_hw_constraint_list(substream->runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
&adau1372->rate_constraints);
return 0;
}
static void adau1372_enable_pll(struct adau1372 *adau1372)
{
unsigned int val, timeout = 0;
int ret;
regmap_update_bits(adau1372->regmap, ADAU1372_REG_CLK_CTRL,
ADAU1372_CLK_CTRL_PLL_EN, ADAU1372_CLK_CTRL_PLL_EN);
do {
/* Takes about 1ms to lock */
usleep_range(1000, 2000);
ret = regmap_read(adau1372->regmap, ADAU1372_REG_PLL(5), &val);
if (ret)
break;
timeout++;
} while (!(val & 1) && timeout < 3);
if (ret < 0 || !(val & 1))
dev_err(adau1372->dev, "Failed to lock PLL\n");
}
static void adau1372_set_power(struct adau1372 *adau1372, bool enable)
{
if (adau1372->enabled == enable)
return;
if (enable) {
unsigned int clk_ctrl = ADAU1372_CLK_CTRL_MCLK_EN;
clk_prepare_enable(adau1372->mclk);
if (adau1372->pd_gpio)
gpiod_set_value(adau1372->pd_gpio, 0);
if (adau1372->switch_mode)
adau1372->switch_mode(adau1372->dev);
regcache_cache_only(adau1372->regmap, false);
/*
* Clocks needs to be enabled before any other register can be
* accessed.
*/
if (adau1372->use_pll) {
adau1372_enable_pll(adau1372);
clk_ctrl |= ADAU1372_CLK_CTRL_CLKSRC;
}
regmap_update_bits(adau1372->regmap, ADAU1372_REG_CLK_CTRL,
ADAU1372_CLK_CTRL_MCLK_EN | ADAU1372_CLK_CTRL_CLKSRC, clk_ctrl);
regcache_sync(adau1372->regmap);
} else {
if (adau1372->pd_gpio) {
/*
* This will turn everything off and reset the register
* map. No need to do any register writes to manually
* turn things off.
*/
gpiod_set_value(adau1372->pd_gpio, 1);
regcache_mark_dirty(adau1372->regmap);
} else {
regmap_update_bits(adau1372->regmap, ADAU1372_REG_CLK_CTRL,
ADAU1372_CLK_CTRL_MCLK_EN | ADAU1372_CLK_CTRL_PLL_EN, 0);
}
clk_disable_unprepare(adau1372->mclk);
regcache_cache_only(adau1372->regmap, true);
}
adau1372->enabled = enable;
}
static int adau1372_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct adau1372 *adau1372 = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
adau1372_set_power(adau1372, true);
break;
case SND_SOC_BIAS_OFF:
adau1372_set_power(adau1372, false);
break;
}
return 0;
}
static const struct snd_soc_component_driver adau1372_driver = {
.set_bias_level = adau1372_set_bias_level,
.controls = adau1372_controls,
.num_controls = ARRAY_SIZE(adau1372_controls),
.dapm_widgets = adau1372_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(adau1372_dapm_widgets),
.dapm_routes = adau1372_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(adau1372_dapm_routes),
.endianness = 1,
};
static const struct snd_soc_dai_ops adau1372_dai_ops = {
.set_fmt = adau1372_set_dai_fmt,
.set_tdm_slot = adau1372_set_tdm_slot,
.set_tristate = adau1372_set_tristate,
.hw_params = adau1372_hw_params,
.startup = adau1372_startup,
};
#define ADAU1372_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver adau1372_dai_driver = {
.name = "adau1372",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = ADAU1372_FORMATS,
.sig_bits = 24,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = ADAU1372_FORMATS,
.sig_bits = 24,
},
.ops = &adau1372_dai_ops,
.symmetric_rate = 1,
};
static int adau1372_setup_pll(struct adau1372 *adau1372, unsigned int rate)
{
u8 regs[5];
unsigned int i;
int ret;
ret = adau_calc_pll_cfg(rate, 49152000, regs);
if (ret < 0)
return ret;
for (i = 0; i < ARRAY_SIZE(regs); i++)
regmap_write(adau1372->regmap, ADAU1372_REG_PLL(i), regs[i]);
return 0;
}
int adau1372_probe(struct device *dev, struct regmap *regmap,
void (*switch_mode)(struct device *dev))
{
struct adau1372 *adau1372;
unsigned int clk_ctrl;
unsigned long rate;
int ret;
if (IS_ERR(regmap))
return PTR_ERR(regmap);
adau1372 = devm_kzalloc(dev, sizeof(*adau1372), GFP_KERNEL);
if (!adau1372)
return -ENOMEM;
adau1372->mclk = devm_clk_get(dev, "mclk");
if (IS_ERR(adau1372->mclk))
return PTR_ERR(adau1372->mclk);
adau1372->pd_gpio = devm_gpiod_get_optional(dev, "powerdown", GPIOD_OUT_HIGH);
if (IS_ERR(adau1372->pd_gpio))
return PTR_ERR(adau1372->pd_gpio);
adau1372->regmap = regmap;
adau1372->switch_mode = switch_mode;
adau1372->dev = dev;
adau1372->rate_constraints.list = adau1372_rates;
adau1372->rate_constraints.count = ARRAY_SIZE(adau1372_rates);
adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM2;
dev_set_drvdata(dev, adau1372);
/*
* The datasheet says that the internal MCLK always needs to run at
* 12.288MHz. Automatically choose a valid configuration from the
* external clock.
*/
rate = clk_get_rate(adau1372->mclk);
switch (rate) {
case 12288000:
clk_ctrl = ADAU1372_CLK_CTRL_CC_MDIV;
break;
case 24576000:
clk_ctrl = 0;
break;
default:
clk_ctrl = 0;
ret = adau1372_setup_pll(adau1372, rate);
if (ret < 0)
return ret;
adau1372->use_pll = true;
break;
}
/*
* Most of the registers are inaccessible unless the internal clock is
* enabled.
*/
regcache_cache_only(regmap, true);
regmap_update_bits(regmap, ADAU1372_REG_CLK_CTRL, ADAU1372_CLK_CTRL_CC_MDIV, clk_ctrl);
/*
* No pinctrl support yet, put the multi-purpose pins in the most
* sensible mode for general purpose CODEC operation.
*/
regmap_write(regmap, ADAU1372_REG_MODE_MP(1), 0x00); /* SDATA OUT */
regmap_write(regmap, ADAU1372_REG_MODE_MP(6), 0x12); /* CLOCKOUT */
regmap_write(regmap, ADAU1372_REG_OP_STAGE_MUTE, 0x0);
regmap_write(regmap, 0x7, 0x01); /* CLOCK OUT */
return devm_snd_soc_register_component(dev, &adau1372_driver, &adau1372_dai_driver, 1);
}
EXPORT_SYMBOL(adau1372_probe);
static const struct reg_default adau1372_reg_defaults[] = {
{ ADAU1372_REG_CLK_CTRL, 0x00 },
{ ADAU1372_REG_PLL(0), 0x00 },
{ ADAU1372_REG_PLL(1), 0x00 },
{ ADAU1372_REG_PLL(2), 0x00 },
{ ADAU1372_REG_PLL(3), 0x00 },
{ ADAU1372_REG_PLL(4), 0x00 },
{ ADAU1372_REG_PLL(5), 0x00 },
{ ADAU1372_REG_DAC_SOURCE, 0x10 },
{ ADAU1372_REG_SOUT_SOURCE_0_1, 0x54 },
{ ADAU1372_REG_SOUT_SOURCE_2_3, 0x76 },
{ ADAU1372_REG_SOUT_SOURCE_4_5, 0x54 },
{ ADAU1372_REG_SOUT_SOURCE_6_7, 0x76 },
{ ADAU1372_REG_ADC_SDATA_CH, 0x04 },
{ ADAU1372_REG_ASRCO_SOURCE_0_1, 0x10 },
{ ADAU1372_REG_ASRCO_SOURCE_2_3, 0x32 },
{ ADAU1372_REG_ASRC_MODE, 0x00 },
{ ADAU1372_REG_ADC_CTRL0, 0x19 },
{ ADAU1372_REG_ADC_CTRL1, 0x19 },
{ ADAU1372_REG_ADC_CTRL2, 0x00 },
{ ADAU1372_REG_ADC_CTRL3, 0x00 },
{ ADAU1372_REG_ADC_VOL(0), 0x00 },
{ ADAU1372_REG_ADC_VOL(1), 0x00 },
{ ADAU1372_REG_ADC_VOL(2), 0x00 },
{ ADAU1372_REG_ADC_VOL(3), 0x00 },
{ ADAU1372_REG_PGA_CTRL(0), 0x40 },
{ ADAU1372_REG_PGA_CTRL(1), 0x40 },
{ ADAU1372_REG_PGA_CTRL(2), 0x40 },
{ ADAU1372_REG_PGA_CTRL(3), 0x40 },
{ ADAU1372_REG_PGA_BOOST, 0x00 },
{ ADAU1372_REG_MICBIAS, 0x00 },
{ ADAU1372_REG_DAC_CTRL, 0x18 },
{ ADAU1372_REG_DAC_VOL(0), 0x00 },
{ ADAU1372_REG_DAC_VOL(1), 0x00 },
{ ADAU1372_REG_OP_STAGE_MUTE, 0x0f },
{ ADAU1372_REG_SAI0, 0x00 },
{ ADAU1372_REG_SAI1, 0x00 },
{ ADAU1372_REG_SOUT_CTRL, 0x00 },
{ ADAU1372_REG_MODE_MP(0), 0x00 },
{ ADAU1372_REG_MODE_MP(1), 0x10 },
{ ADAU1372_REG_MODE_MP(4), 0x00 },
{ ADAU1372_REG_MODE_MP(5), 0x00 },
{ ADAU1372_REG_MODE_MP(6), 0x11 },
{ ADAU1372_REG_OP_STAGE_CTRL, 0x0f },
{ ADAU1372_REG_DECIM_PWR, 0x00 },
{ ADAU1372_REG_INTERP_PWR, 0x00 },
{ ADAU1372_REG_BIAS_CTRL0, 0x00 },
{ ADAU1372_REG_BIAS_CTRL1, 0x00 },
};
static bool adau1372_volatile_register(struct device *dev, unsigned int reg)
{
if (reg == ADAU1372_REG_PLL(5))
return true;
return false;
}
const struct regmap_config adau1372_regmap_config = {
.val_bits = 8,
.reg_bits = 16,
.max_register = 0x4d,
.reg_defaults = adau1372_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(adau1372_reg_defaults),
.volatile_reg = adau1372_volatile_register,
.cache_type = REGCACHE_MAPLE,
};
EXPORT_SYMBOL_GPL(adau1372_regmap_config);
MODULE_DESCRIPTION("ASoC ADAU1372 CODEC driver");
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/adau1372.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* wm8400.c -- WM8400 ALSA Soc Audio driver
*
* Copyright 2008-11 Wolfson Microelectronics PLC.
* Author: Mark Brown <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/mfd/wm8400-audio.h>
#include <linux/mfd/wm8400-private.h>
#include <linux/mfd/core.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "wm8400.h"
static struct regulator_bulk_data power[] = {
{
.supply = "I2S1VDD",
},
{
.supply = "I2S2VDD",
},
{
.supply = "DCVDD",
},
{
.supply = "AVDD",
},
{
.supply = "FLLVDD",
},
{
.supply = "HPVDD",
},
{
.supply = "SPKVDD",
},
};
/* codec private data */
struct wm8400_priv {
struct wm8400 *wm8400;
u16 fake_register;
unsigned int sysclk;
unsigned int pcmclk;
int fll_in, fll_out;
};
static void wm8400_component_reset(struct snd_soc_component *component)
{
struct wm8400_priv *wm8400 = snd_soc_component_get_drvdata(component);
wm8400_reset_codec_reg_cache(wm8400->wm8400);
}
static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0);
static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -2100, 0, 0);
static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0);
static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0);
static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0);
static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0);
static int wm8400_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
int reg = mc->reg;
int ret;
u16 val;
ret = snd_soc_put_volsw(kcontrol, ucontrol);
if (ret < 0)
return ret;
/* now hit the volume update bits (always bit 8) */
val = snd_soc_component_read(component, reg);
return snd_soc_component_write(component, reg, val | 0x0100);
}
#define WM8400_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert, tlv_array) \
SOC_SINGLE_EXT_TLV(xname, reg, shift, max, invert, \
snd_soc_get_volsw, wm8400_outpga_put_volsw_vu, tlv_array)
static const char *wm8400_digital_sidetone[] =
{"None", "Left ADC", "Right ADC", "Reserved"};
static SOC_ENUM_SINGLE_DECL(wm8400_left_digital_sidetone_enum,
WM8400_DIGITAL_SIDE_TONE,
WM8400_ADC_TO_DACL_SHIFT,
wm8400_digital_sidetone);
static SOC_ENUM_SINGLE_DECL(wm8400_right_digital_sidetone_enum,
WM8400_DIGITAL_SIDE_TONE,
WM8400_ADC_TO_DACR_SHIFT,
wm8400_digital_sidetone);
static const char *wm8400_adcmode[] =
{"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"};
static SOC_ENUM_SINGLE_DECL(wm8400_right_adcmode_enum,
WM8400_ADC_CTRL,
WM8400_ADC_HPF_CUT_SHIFT,
wm8400_adcmode);
static const struct snd_kcontrol_new wm8400_snd_controls[] = {
/* INMIXL */
SOC_SINGLE("LIN12 PGA Boost", WM8400_INPUT_MIXER3, WM8400_L12MNBST_SHIFT,
1, 0),
SOC_SINGLE("LIN34 PGA Boost", WM8400_INPUT_MIXER3, WM8400_L34MNBST_SHIFT,
1, 0),
/* INMIXR */
SOC_SINGLE("RIN12 PGA Boost", WM8400_INPUT_MIXER3, WM8400_R12MNBST_SHIFT,
1, 0),
SOC_SINGLE("RIN34 PGA Boost", WM8400_INPUT_MIXER3, WM8400_R34MNBST_SHIFT,
1, 0),
/* LOMIX */
SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER3,
WM8400_LLI3LOVOL_SHIFT, 7, 0, out_mix_tlv),
SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3,
WM8400_LR12LOVOL_SHIFT, 7, 0, out_mix_tlv),
SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3,
WM8400_LL12LOVOL_SHIFT, 7, 0, out_mix_tlv),
SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER5,
WM8400_LRI3LOVOL_SHIFT, 7, 0, out_mix_tlv),
SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8400_OUTPUT_MIXER5,
WM8400_LRBLOVOL_SHIFT, 7, 0, out_mix_tlv),
SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8400_OUTPUT_MIXER5,
WM8400_LRBLOVOL_SHIFT, 7, 0, out_mix_tlv),
/* ROMIX */
SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER4,
WM8400_RRI3ROVOL_SHIFT, 7, 0, out_mix_tlv),
SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4,
WM8400_RL12ROVOL_SHIFT, 7, 0, out_mix_tlv),
SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4,
WM8400_RR12ROVOL_SHIFT, 7, 0, out_mix_tlv),
SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER6,
WM8400_RLI3ROVOL_SHIFT, 7, 0, out_mix_tlv),
SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8400_OUTPUT_MIXER6,
WM8400_RLBROVOL_SHIFT, 7, 0, out_mix_tlv),
SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8400_OUTPUT_MIXER6,
WM8400_RRBROVOL_SHIFT, 7, 0, out_mix_tlv),
/* LOUT */
WM8400_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8400_LEFT_OUTPUT_VOLUME,
WM8400_LOUTVOL_SHIFT, WM8400_LOUTVOL_MASK, 0, out_pga_tlv),
SOC_SINGLE("LOUT ZC", WM8400_LEFT_OUTPUT_VOLUME, WM8400_LOZC_SHIFT, 1, 0),
/* ROUT */
WM8400_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8400_RIGHT_OUTPUT_VOLUME,
WM8400_ROUTVOL_SHIFT, WM8400_ROUTVOL_MASK, 0, out_pga_tlv),
SOC_SINGLE("ROUT ZC", WM8400_RIGHT_OUTPUT_VOLUME, WM8400_ROZC_SHIFT, 1, 0),
/* LOPGA */
WM8400_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8400_LEFT_OPGA_VOLUME,
WM8400_LOPGAVOL_SHIFT, WM8400_LOPGAVOL_MASK, 0, out_pga_tlv),
SOC_SINGLE("LOPGA ZC Switch", WM8400_LEFT_OPGA_VOLUME,
WM8400_LOPGAZC_SHIFT, 1, 0),
/* ROPGA */
WM8400_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8400_RIGHT_OPGA_VOLUME,
WM8400_ROPGAVOL_SHIFT, WM8400_ROPGAVOL_MASK, 0, out_pga_tlv),
SOC_SINGLE("ROPGA ZC Switch", WM8400_RIGHT_OPGA_VOLUME,
WM8400_ROPGAZC_SHIFT, 1, 0),
SOC_SINGLE("LON Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
WM8400_LONMUTE_SHIFT, 1, 0),
SOC_SINGLE("LOP Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
WM8400_LOPMUTE_SHIFT, 1, 0),
SOC_SINGLE("LOP Attenuation Switch", WM8400_LINE_OUTPUTS_VOLUME,
WM8400_LOATTN_SHIFT, 1, 0),
SOC_SINGLE("RON Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
WM8400_RONMUTE_SHIFT, 1, 0),
SOC_SINGLE("ROP Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
WM8400_ROPMUTE_SHIFT, 1, 0),
SOC_SINGLE("ROP Attenuation Switch", WM8400_LINE_OUTPUTS_VOLUME,
WM8400_ROATTN_SHIFT, 1, 0),
SOC_SINGLE("OUT3 Mute Switch", WM8400_OUT3_4_VOLUME,
WM8400_OUT3MUTE_SHIFT, 1, 0),
SOC_SINGLE("OUT3 Attenuation Switch", WM8400_OUT3_4_VOLUME,
WM8400_OUT3ATTN_SHIFT, 1, 0),
SOC_SINGLE("OUT4 Mute Switch", WM8400_OUT3_4_VOLUME,
WM8400_OUT4MUTE_SHIFT, 1, 0),
SOC_SINGLE("OUT4 Attenuation Switch", WM8400_OUT3_4_VOLUME,
WM8400_OUT4ATTN_SHIFT, 1, 0),
SOC_SINGLE("Speaker Mode Switch", WM8400_CLASSD1,
WM8400_CDMODE_SHIFT, 1, 0),
SOC_SINGLE("Speaker Output Attenuation Volume", WM8400_SPEAKER_VOLUME,
WM8400_SPKATTN_SHIFT, WM8400_SPKATTN_MASK, 0),
SOC_SINGLE("Speaker DC Boost Volume", WM8400_CLASSD3,
WM8400_DCGAIN_SHIFT, 6, 0),
SOC_SINGLE("Speaker AC Boost Volume", WM8400_CLASSD3,
WM8400_ACGAIN_SHIFT, 6, 0),
WM8400_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume",
WM8400_LEFT_DAC_DIGITAL_VOLUME, WM8400_DACL_VOL_SHIFT,
127, 0, out_dac_tlv),
WM8400_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume",
WM8400_RIGHT_DAC_DIGITAL_VOLUME, WM8400_DACR_VOL_SHIFT,
127, 0, out_dac_tlv),
SOC_ENUM("Left Digital Sidetone", wm8400_left_digital_sidetone_enum),
SOC_ENUM("Right Digital Sidetone", wm8400_right_digital_sidetone_enum),
SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8400_DIGITAL_SIDE_TONE,
WM8400_ADCL_DAC_SVOL_SHIFT, 15, 0, out_sidetone_tlv),
SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8400_DIGITAL_SIDE_TONE,
WM8400_ADCR_DAC_SVOL_SHIFT, 15, 0, out_sidetone_tlv),
SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8400_ADC_CTRL,
WM8400_ADC_HPF_ENA_SHIFT, 1, 0),
SOC_ENUM("ADC HPF Mode", wm8400_right_adcmode_enum),
WM8400_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume",
WM8400_LEFT_ADC_DIGITAL_VOLUME,
WM8400_ADCL_VOL_SHIFT,
WM8400_ADCL_VOL_MASK,
0,
in_adc_tlv),
WM8400_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume",
WM8400_RIGHT_ADC_DIGITAL_VOLUME,
WM8400_ADCR_VOL_SHIFT,
WM8400_ADCR_VOL_MASK,
0,
in_adc_tlv),
WM8400_OUTPGA_SINGLE_R_TLV("LIN12 Volume",
WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
WM8400_LIN12VOL_SHIFT,
WM8400_LIN12VOL_MASK,
0,
in_pga_tlv),
SOC_SINGLE("LIN12 ZC Switch", WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
WM8400_LI12ZC_SHIFT, 1, 0),
SOC_SINGLE("LIN12 Mute Switch", WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
WM8400_LI12MUTE_SHIFT, 1, 0),
WM8400_OUTPGA_SINGLE_R_TLV("LIN34 Volume",
WM8400_LEFT_LINE_INPUT_3_4_VOLUME,
WM8400_LIN34VOL_SHIFT,
WM8400_LIN34VOL_MASK,
0,
in_pga_tlv),
SOC_SINGLE("LIN34 ZC Switch", WM8400_LEFT_LINE_INPUT_3_4_VOLUME,
WM8400_LI34ZC_SHIFT, 1, 0),
SOC_SINGLE("LIN34 Mute Switch", WM8400_LEFT_LINE_INPUT_3_4_VOLUME,
WM8400_LI34MUTE_SHIFT, 1, 0),
WM8400_OUTPGA_SINGLE_R_TLV("RIN12 Volume",
WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
WM8400_RIN12VOL_SHIFT,
WM8400_RIN12VOL_MASK,
0,
in_pga_tlv),
SOC_SINGLE("RIN12 ZC Switch", WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
WM8400_RI12ZC_SHIFT, 1, 0),
SOC_SINGLE("RIN12 Mute Switch", WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
WM8400_RI12MUTE_SHIFT, 1, 0),
WM8400_OUTPGA_SINGLE_R_TLV("RIN34 Volume",
WM8400_RIGHT_LINE_INPUT_3_4_VOLUME,
WM8400_RIN34VOL_SHIFT,
WM8400_RIN34VOL_MASK,
0,
in_pga_tlv),
SOC_SINGLE("RIN34 ZC Switch", WM8400_RIGHT_LINE_INPUT_3_4_VOLUME,
WM8400_RI34ZC_SHIFT, 1, 0),
SOC_SINGLE("RIN34 Mute Switch", WM8400_RIGHT_LINE_INPUT_3_4_VOLUME,
WM8400_RI34MUTE_SHIFT, 1, 0),
};
/*
* _DAPM_ Controls
*/
static int outmixer_event (struct snd_soc_dapm_widget *w,
struct snd_kcontrol * kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
u32 reg_shift = mc->shift;
int ret = 0;
u16 reg;
switch (reg_shift) {
case WM8400_SPEAKER_MIXER | (WM8400_LDSPK << 8) :
reg = snd_soc_component_read(component, WM8400_OUTPUT_MIXER1);
if (reg & WM8400_LDLO) {
printk(KERN_WARNING
"Cannot set as Output Mixer 1 LDLO Set\n");
ret = -1;
}
break;
case WM8400_SPEAKER_MIXER | (WM8400_RDSPK << 8):
reg = snd_soc_component_read(component, WM8400_OUTPUT_MIXER2);
if (reg & WM8400_RDRO) {
printk(KERN_WARNING
"Cannot set as Output Mixer 2 RDRO Set\n");
ret = -1;
}
break;
case WM8400_OUTPUT_MIXER1 | (WM8400_LDLO << 8):
reg = snd_soc_component_read(component, WM8400_SPEAKER_MIXER);
if (reg & WM8400_LDSPK) {
printk(KERN_WARNING
"Cannot set as Speaker Mixer LDSPK Set\n");
ret = -1;
}
break;
case WM8400_OUTPUT_MIXER2 | (WM8400_RDRO << 8):
reg = snd_soc_component_read(component, WM8400_SPEAKER_MIXER);
if (reg & WM8400_RDSPK) {
printk(KERN_WARNING
"Cannot set as Speaker Mixer RDSPK Set\n");
ret = -1;
}
break;
}
return ret;
}
/* INMIX dB values */
static const DECLARE_TLV_DB_SCALE(in_mix_tlv, -1200, 600, 0);
/* Left In PGA Connections */
static const struct snd_kcontrol_new wm8400_dapm_lin12_pga_controls[] = {
SOC_DAPM_SINGLE("LIN1 Switch", WM8400_INPUT_MIXER2, WM8400_LMN1_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LIN2 Switch", WM8400_INPUT_MIXER2, WM8400_LMP2_SHIFT, 1, 0),
};
static const struct snd_kcontrol_new wm8400_dapm_lin34_pga_controls[] = {
SOC_DAPM_SINGLE("LIN3 Switch", WM8400_INPUT_MIXER2, WM8400_LMN3_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LIN4 Switch", WM8400_INPUT_MIXER2, WM8400_LMP4_SHIFT, 1, 0),
};
/* Right In PGA Connections */
static const struct snd_kcontrol_new wm8400_dapm_rin12_pga_controls[] = {
SOC_DAPM_SINGLE("RIN1 Switch", WM8400_INPUT_MIXER2, WM8400_RMN1_SHIFT, 1, 0),
SOC_DAPM_SINGLE("RIN2 Switch", WM8400_INPUT_MIXER2, WM8400_RMP2_SHIFT, 1, 0),
};
static const struct snd_kcontrol_new wm8400_dapm_rin34_pga_controls[] = {
SOC_DAPM_SINGLE("RIN3 Switch", WM8400_INPUT_MIXER2, WM8400_RMN3_SHIFT, 1, 0),
SOC_DAPM_SINGLE("RIN4 Switch", WM8400_INPUT_MIXER2, WM8400_RMP4_SHIFT, 1, 0),
};
/* INMIXL */
static const struct snd_kcontrol_new wm8400_dapm_inmixl_controls[] = {
SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8400_INPUT_MIXER3,
WM8400_LDBVOL_SHIFT, WM8400_LDBVOL_MASK, 0, in_mix_tlv),
SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8400_INPUT_MIXER5, WM8400_LI2BVOL_SHIFT,
7, 0, in_mix_tlv),
SOC_DAPM_SINGLE("LINPGA12 Switch", WM8400_INPUT_MIXER3, WM8400_L12MNB_SHIFT,
1, 0),
SOC_DAPM_SINGLE("LINPGA34 Switch", WM8400_INPUT_MIXER3, WM8400_L34MNB_SHIFT,
1, 0),
};
/* INMIXR */
static const struct snd_kcontrol_new wm8400_dapm_inmixr_controls[] = {
SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8400_INPUT_MIXER4,
WM8400_RDBVOL_SHIFT, WM8400_RDBVOL_MASK, 0, in_mix_tlv),
SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8400_INPUT_MIXER6, WM8400_RI2BVOL_SHIFT,
7, 0, in_mix_tlv),
SOC_DAPM_SINGLE("RINPGA12 Switch", WM8400_INPUT_MIXER3, WM8400_L12MNB_SHIFT,
1, 0),
SOC_DAPM_SINGLE("RINPGA34 Switch", WM8400_INPUT_MIXER3, WM8400_L34MNB_SHIFT,
1, 0),
};
/* AINLMUX */
static const char *wm8400_ainlmux[] =
{"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"};
static SOC_ENUM_SINGLE_DECL(wm8400_ainlmux_enum,
WM8400_INPUT_MIXER1,
WM8400_AINLMODE_SHIFT,
wm8400_ainlmux);
static const struct snd_kcontrol_new wm8400_dapm_ainlmux_controls =
SOC_DAPM_ENUM("Route", wm8400_ainlmux_enum);
/* DIFFINL */
/* AINRMUX */
static const char *wm8400_ainrmux[] =
{"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"};
static SOC_ENUM_SINGLE_DECL(wm8400_ainrmux_enum,
WM8400_INPUT_MIXER1,
WM8400_AINRMODE_SHIFT,
wm8400_ainrmux);
static const struct snd_kcontrol_new wm8400_dapm_ainrmux_controls =
SOC_DAPM_ENUM("Route", wm8400_ainrmux_enum);
/* LOMIX */
static const struct snd_kcontrol_new wm8400_dapm_lomix_controls[] = {
SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8400_OUTPUT_MIXER1,
WM8400_LRBLO_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8400_OUTPUT_MIXER1,
WM8400_LLBLO_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8400_OUTPUT_MIXER1,
WM8400_LRI3LO_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8400_OUTPUT_MIXER1,
WM8400_LLI3LO_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER1,
WM8400_LR12LO_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER1,
WM8400_LL12LO_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8400_OUTPUT_MIXER1,
WM8400_LDLO_SHIFT, 1, 0),
};
/* ROMIX */
static const struct snd_kcontrol_new wm8400_dapm_romix_controls[] = {
SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8400_OUTPUT_MIXER2,
WM8400_RLBRO_SHIFT, 1, 0),
SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8400_OUTPUT_MIXER2,
WM8400_RRBRO_SHIFT, 1, 0),
SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8400_OUTPUT_MIXER2,
WM8400_RLI3RO_SHIFT, 1, 0),
SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8400_OUTPUT_MIXER2,
WM8400_RRI3RO_SHIFT, 1, 0),
SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER2,
WM8400_RL12RO_SHIFT, 1, 0),
SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER2,
WM8400_RR12RO_SHIFT, 1, 0),
SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8400_OUTPUT_MIXER2,
WM8400_RDRO_SHIFT, 1, 0),
};
/* LONMIX */
static const struct snd_kcontrol_new wm8400_dapm_lonmix_controls[] = {
SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8400_LINE_MIXER1,
WM8400_LLOPGALON_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8400_LINE_MIXER1,
WM8400_LROPGALON_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8400_LINE_MIXER1,
WM8400_LOPLON_SHIFT, 1, 0),
};
/* LOPMIX */
static const struct snd_kcontrol_new wm8400_dapm_lopmix_controls[] = {
SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8400_LINE_MIXER1,
WM8400_LR12LOP_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8400_LINE_MIXER1,
WM8400_LL12LOP_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8400_LINE_MIXER1,
WM8400_LLOPGALOP_SHIFT, 1, 0),
};
/* RONMIX */
static const struct snd_kcontrol_new wm8400_dapm_ronmix_controls[] = {
SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8400_LINE_MIXER2,
WM8400_RROPGARON_SHIFT, 1, 0),
SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8400_LINE_MIXER2,
WM8400_RLOPGARON_SHIFT, 1, 0),
SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8400_LINE_MIXER2,
WM8400_ROPRON_SHIFT, 1, 0),
};
/* ROPMIX */
static const struct snd_kcontrol_new wm8400_dapm_ropmix_controls[] = {
SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8400_LINE_MIXER2,
WM8400_RL12ROP_SHIFT, 1, 0),
SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8400_LINE_MIXER2,
WM8400_RR12ROP_SHIFT, 1, 0),
SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8400_LINE_MIXER2,
WM8400_RROPGAROP_SHIFT, 1, 0),
};
/* OUT3MIX */
static const struct snd_kcontrol_new wm8400_dapm_out3mix_controls[] = {
SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8400_OUT3_4_MIXER,
WM8400_LI4O3_SHIFT, 1, 0),
SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8400_OUT3_4_MIXER,
WM8400_LPGAO3_SHIFT, 1, 0),
};
/* OUT4MIX */
static const struct snd_kcontrol_new wm8400_dapm_out4mix_controls[] = {
SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8400_OUT3_4_MIXER,
WM8400_RPGAO4_SHIFT, 1, 0),
SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8400_OUT3_4_MIXER,
WM8400_RI4O4_SHIFT, 1, 0),
};
/* SPKMIX */
static const struct snd_kcontrol_new wm8400_dapm_spkmix_controls[] = {
SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8400_SPEAKER_MIXER,
WM8400_LI2SPK_SHIFT, 1, 0),
SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8400_SPEAKER_MIXER,
WM8400_LB2SPK_SHIFT, 1, 0),
SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8400_SPEAKER_MIXER,
WM8400_LOPGASPK_SHIFT, 1, 0),
SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8400_SPEAKER_MIXER,
WM8400_LDSPK_SHIFT, 1, 0),
SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8400_SPEAKER_MIXER,
WM8400_RDSPK_SHIFT, 1, 0),
SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8400_SPEAKER_MIXER,
WM8400_ROPGASPK_SHIFT, 1, 0),
SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8400_SPEAKER_MIXER,
WM8400_RL12ROP_SHIFT, 1, 0),
SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8400_SPEAKER_MIXER,
WM8400_RI2SPK_SHIFT, 1, 0),
};
static const struct snd_soc_dapm_widget wm8400_dapm_widgets[] = {
/* Input Side */
/* Input Lines */
SND_SOC_DAPM_INPUT("LIN1"),
SND_SOC_DAPM_INPUT("LIN2"),
SND_SOC_DAPM_INPUT("LIN3"),
SND_SOC_DAPM_INPUT("LIN4/RXN"),
SND_SOC_DAPM_INPUT("RIN3"),
SND_SOC_DAPM_INPUT("RIN4/RXP"),
SND_SOC_DAPM_INPUT("RIN1"),
SND_SOC_DAPM_INPUT("RIN2"),
SND_SOC_DAPM_INPUT("Internal ADC Source"),
/* DACs */
SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8400_POWER_MANAGEMENT_2,
WM8400_ADCL_ENA_SHIFT, 0),
SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8400_POWER_MANAGEMENT_2,
WM8400_ADCR_ENA_SHIFT, 0),
/* Input PGAs */
SND_SOC_DAPM_MIXER("LIN12 PGA", WM8400_POWER_MANAGEMENT_2,
WM8400_LIN12_ENA_SHIFT,
0, &wm8400_dapm_lin12_pga_controls[0],
ARRAY_SIZE(wm8400_dapm_lin12_pga_controls)),
SND_SOC_DAPM_MIXER("LIN34 PGA", WM8400_POWER_MANAGEMENT_2,
WM8400_LIN34_ENA_SHIFT,
0, &wm8400_dapm_lin34_pga_controls[0],
ARRAY_SIZE(wm8400_dapm_lin34_pga_controls)),
SND_SOC_DAPM_MIXER("RIN12 PGA", WM8400_POWER_MANAGEMENT_2,
WM8400_RIN12_ENA_SHIFT,
0, &wm8400_dapm_rin12_pga_controls[0],
ARRAY_SIZE(wm8400_dapm_rin12_pga_controls)),
SND_SOC_DAPM_MIXER("RIN34 PGA", WM8400_POWER_MANAGEMENT_2,
WM8400_RIN34_ENA_SHIFT,
0, &wm8400_dapm_rin34_pga_controls[0],
ARRAY_SIZE(wm8400_dapm_rin34_pga_controls)),
SND_SOC_DAPM_SUPPLY("INL", WM8400_POWER_MANAGEMENT_2, WM8400_AINL_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY("INR", WM8400_POWER_MANAGEMENT_2, WM8400_AINR_ENA_SHIFT,
0, NULL, 0),
/* INMIXL */
SND_SOC_DAPM_MIXER("INMIXL", SND_SOC_NOPM, 0, 0,
&wm8400_dapm_inmixl_controls[0],
ARRAY_SIZE(wm8400_dapm_inmixl_controls)),
/* AINLMUX */
SND_SOC_DAPM_MUX("AILNMUX", SND_SOC_NOPM, 0, 0, &wm8400_dapm_ainlmux_controls),
/* INMIXR */
SND_SOC_DAPM_MIXER("INMIXR", SND_SOC_NOPM, 0, 0,
&wm8400_dapm_inmixr_controls[0],
ARRAY_SIZE(wm8400_dapm_inmixr_controls)),
/* AINRMUX */
SND_SOC_DAPM_MUX("AIRNMUX", SND_SOC_NOPM, 0, 0, &wm8400_dapm_ainrmux_controls),
/* Output Side */
/* DACs */
SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8400_POWER_MANAGEMENT_3,
WM8400_DACL_ENA_SHIFT, 0),
SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8400_POWER_MANAGEMENT_3,
WM8400_DACR_ENA_SHIFT, 0),
/* LOMIX */
SND_SOC_DAPM_MIXER_E("LOMIX", WM8400_POWER_MANAGEMENT_3,
WM8400_LOMIX_ENA_SHIFT,
0, &wm8400_dapm_lomix_controls[0],
ARRAY_SIZE(wm8400_dapm_lomix_controls),
outmixer_event, SND_SOC_DAPM_PRE_REG),
/* LONMIX */
SND_SOC_DAPM_MIXER("LONMIX", WM8400_POWER_MANAGEMENT_3, WM8400_LON_ENA_SHIFT,
0, &wm8400_dapm_lonmix_controls[0],
ARRAY_SIZE(wm8400_dapm_lonmix_controls)),
/* LOPMIX */
SND_SOC_DAPM_MIXER("LOPMIX", WM8400_POWER_MANAGEMENT_3, WM8400_LOP_ENA_SHIFT,
0, &wm8400_dapm_lopmix_controls[0],
ARRAY_SIZE(wm8400_dapm_lopmix_controls)),
/* OUT3MIX */
SND_SOC_DAPM_MIXER("OUT3MIX", WM8400_POWER_MANAGEMENT_1, WM8400_OUT3_ENA_SHIFT,
0, &wm8400_dapm_out3mix_controls[0],
ARRAY_SIZE(wm8400_dapm_out3mix_controls)),
/* SPKMIX */
SND_SOC_DAPM_MIXER_E("SPKMIX", WM8400_POWER_MANAGEMENT_1, WM8400_SPK_ENA_SHIFT,
0, &wm8400_dapm_spkmix_controls[0],
ARRAY_SIZE(wm8400_dapm_spkmix_controls), outmixer_event,
SND_SOC_DAPM_PRE_REG),
/* OUT4MIX */
SND_SOC_DAPM_MIXER("OUT4MIX", WM8400_POWER_MANAGEMENT_1, WM8400_OUT4_ENA_SHIFT,
0, &wm8400_dapm_out4mix_controls[0],
ARRAY_SIZE(wm8400_dapm_out4mix_controls)),
/* ROPMIX */
SND_SOC_DAPM_MIXER("ROPMIX", WM8400_POWER_MANAGEMENT_3, WM8400_ROP_ENA_SHIFT,
0, &wm8400_dapm_ropmix_controls[0],
ARRAY_SIZE(wm8400_dapm_ropmix_controls)),
/* RONMIX */
SND_SOC_DAPM_MIXER("RONMIX", WM8400_POWER_MANAGEMENT_3, WM8400_RON_ENA_SHIFT,
0, &wm8400_dapm_ronmix_controls[0],
ARRAY_SIZE(wm8400_dapm_ronmix_controls)),
/* ROMIX */
SND_SOC_DAPM_MIXER_E("ROMIX", WM8400_POWER_MANAGEMENT_3,
WM8400_ROMIX_ENA_SHIFT,
0, &wm8400_dapm_romix_controls[0],
ARRAY_SIZE(wm8400_dapm_romix_controls),
outmixer_event, SND_SOC_DAPM_PRE_REG),
/* LOUT PGA */
SND_SOC_DAPM_PGA("LOUT PGA", WM8400_POWER_MANAGEMENT_1, WM8400_LOUT_ENA_SHIFT,
0, NULL, 0),
/* ROUT PGA */
SND_SOC_DAPM_PGA("ROUT PGA", WM8400_POWER_MANAGEMENT_1, WM8400_ROUT_ENA_SHIFT,
0, NULL, 0),
/* LOPGA */
SND_SOC_DAPM_PGA("LOPGA", WM8400_POWER_MANAGEMENT_3, WM8400_LOPGA_ENA_SHIFT, 0,
NULL, 0),
/* ROPGA */
SND_SOC_DAPM_PGA("ROPGA", WM8400_POWER_MANAGEMENT_3, WM8400_ROPGA_ENA_SHIFT, 0,
NULL, 0),
/* MICBIAS */
SND_SOC_DAPM_SUPPLY("MICBIAS", WM8400_POWER_MANAGEMENT_1,
WM8400_MIC1BIAS_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("LON"),
SND_SOC_DAPM_OUTPUT("LOP"),
SND_SOC_DAPM_OUTPUT("OUT3"),
SND_SOC_DAPM_OUTPUT("LOUT"),
SND_SOC_DAPM_OUTPUT("SPKN"),
SND_SOC_DAPM_OUTPUT("SPKP"),
SND_SOC_DAPM_OUTPUT("ROUT"),
SND_SOC_DAPM_OUTPUT("OUT4"),
SND_SOC_DAPM_OUTPUT("ROP"),
SND_SOC_DAPM_OUTPUT("RON"),
SND_SOC_DAPM_OUTPUT("Internal DAC Sink"),
};
static const struct snd_soc_dapm_route wm8400_dapm_routes[] = {
/* Make DACs turn on when playing even if not mixed into any outputs */
{"Internal DAC Sink", NULL, "Left DAC"},
{"Internal DAC Sink", NULL, "Right DAC"},
/* Make ADCs turn on when recording
* even if not mixed from any inputs */
{"Left ADC", NULL, "Internal ADC Source"},
{"Right ADC", NULL, "Internal ADC Source"},
/* Input Side */
/* LIN12 PGA */
{"LIN12 PGA", "LIN1 Switch", "LIN1"},
{"LIN12 PGA", "LIN2 Switch", "LIN2"},
/* LIN34 PGA */
{"LIN34 PGA", "LIN3 Switch", "LIN3"},
{"LIN34 PGA", "LIN4 Switch", "LIN4/RXN"},
/* INMIXL */
{"INMIXL", NULL, "INL"},
{"INMIXL", "Record Left Volume", "LOMIX"},
{"INMIXL", "LIN2 Volume", "LIN2"},
{"INMIXL", "LINPGA12 Switch", "LIN12 PGA"},
{"INMIXL", "LINPGA34 Switch", "LIN34 PGA"},
/* AILNMUX */
{"AILNMUX", NULL, "INL"},
{"AILNMUX", "INMIXL Mix", "INMIXL"},
{"AILNMUX", "DIFFINL Mix", "LIN12 PGA"},
{"AILNMUX", "DIFFINL Mix", "LIN34 PGA"},
{"AILNMUX", "RXVOICE Mix", "LIN4/RXN"},
{"AILNMUX", "RXVOICE Mix", "RIN4/RXP"},
/* ADC */
{"Left ADC", NULL, "AILNMUX"},
/* RIN12 PGA */
{"RIN12 PGA", "RIN1 Switch", "RIN1"},
{"RIN12 PGA", "RIN2 Switch", "RIN2"},
/* RIN34 PGA */
{"RIN34 PGA", "RIN3 Switch", "RIN3"},
{"RIN34 PGA", "RIN4 Switch", "RIN4/RXP"},
/* INMIXR */
{"INMIXR", NULL, "INR"},
{"INMIXR", "Record Right Volume", "ROMIX"},
{"INMIXR", "RIN2 Volume", "RIN2"},
{"INMIXR", "RINPGA12 Switch", "RIN12 PGA"},
{"INMIXR", "RINPGA34 Switch", "RIN34 PGA"},
/* AIRNMUX */
{"AIRNMUX", NULL, "INR"},
{"AIRNMUX", "INMIXR Mix", "INMIXR"},
{"AIRNMUX", "DIFFINR Mix", "RIN12 PGA"},
{"AIRNMUX", "DIFFINR Mix", "RIN34 PGA"},
{"AIRNMUX", "RXVOICE Mix", "LIN4/RXN"},
{"AIRNMUX", "RXVOICE Mix", "RIN4/RXP"},
/* ADC */
{"Right ADC", NULL, "AIRNMUX"},
/* LOMIX */
{"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"},
{"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"},
{"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
{"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
{"LOMIX", "LOMIX Right ADC Bypass Switch", "AIRNMUX"},
{"LOMIX", "LOMIX Left ADC Bypass Switch", "AILNMUX"},
{"LOMIX", "LOMIX Left DAC Switch", "Left DAC"},
/* ROMIX */
{"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"},
{"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"},
{"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
{"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
{"ROMIX", "ROMIX Right ADC Bypass Switch", "AIRNMUX"},
{"ROMIX", "ROMIX Left ADC Bypass Switch", "AILNMUX"},
{"ROMIX", "ROMIX Right DAC Switch", "Right DAC"},
/* SPKMIX */
{"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"},
{"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"},
{"SPKMIX", "SPKMIX LADC Bypass Switch", "AILNMUX"},
{"SPKMIX", "SPKMIX RADC Bypass Switch", "AIRNMUX"},
{"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"},
{"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"},
{"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"},
{"SPKMIX", "SPKMIX Left DAC Switch", "Right DAC"},
/* LONMIX */
{"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"},
{"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"},
{"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"},
/* LOPMIX */
{"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"},
{"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"},
{"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"},
/* OUT3MIX */
{"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXN"},
{"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"},
/* OUT4MIX */
{"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"},
{"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"},
/* RONMIX */
{"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"},
{"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"},
{"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"},
/* ROPMIX */
{"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"},
{"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"},
{"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"},
/* Out Mixer PGAs */
{"LOPGA", NULL, "LOMIX"},
{"ROPGA", NULL, "ROMIX"},
{"LOUT PGA", NULL, "LOMIX"},
{"ROUT PGA", NULL, "ROMIX"},
/* Output Pins */
{"LON", NULL, "LONMIX"},
{"LOP", NULL, "LOPMIX"},
{"OUT3", NULL, "OUT3MIX"},
{"LOUT", NULL, "LOUT PGA"},
{"SPKN", NULL, "SPKMIX"},
{"ROUT", NULL, "ROUT PGA"},
{"OUT4", NULL, "OUT4MIX"},
{"ROP", NULL, "ROPMIX"},
{"RON", NULL, "RONMIX"},
};
/*
* Clock after FLL and dividers
*/
static int wm8400_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct wm8400_priv *wm8400 = snd_soc_component_get_drvdata(component);
wm8400->sysclk = freq;
return 0;
}
struct fll_factors {
u16 n;
u16 k;
u16 outdiv;
u16 fratio;
u16 freq_ref;
};
#define FIXED_FLL_SIZE ((1 << 16) * 10)
static int fll_factors(struct wm8400_priv *wm8400, struct fll_factors *factors,
unsigned int Fref, unsigned int Fout)
{
u64 Kpart;
unsigned int K, Nmod, target;
factors->outdiv = 2;
while (Fout * factors->outdiv < 90000000 ||
Fout * factors->outdiv > 100000000) {
factors->outdiv *= 2;
if (factors->outdiv > 32) {
dev_err(wm8400->wm8400->dev,
"Unsupported FLL output frequency %uHz\n",
Fout);
return -EINVAL;
}
}
target = Fout * factors->outdiv;
factors->outdiv = factors->outdiv >> 2;
if (Fref < 48000)
factors->freq_ref = 1;
else
factors->freq_ref = 0;
if (Fref < 1000000)
factors->fratio = 9;
else
factors->fratio = 0;
/* Ensure we have a fractional part */
do {
if (Fref < 1000000)
factors->fratio--;
else
factors->fratio++;
if (factors->fratio < 1 || factors->fratio > 8) {
dev_err(wm8400->wm8400->dev,
"Unable to calculate FRATIO\n");
return -EINVAL;
}
factors->n = target / (Fref * factors->fratio);
Nmod = target % (Fref * factors->fratio);
} while (Nmod == 0);
/* Calculate fractional part - scale up so we can round. */
Kpart = FIXED_FLL_SIZE * (long long)Nmod;
do_div(Kpart, (Fref * factors->fratio));
K = Kpart & 0xFFFFFFFF;
if ((K % 10) >= 5)
K += 5;
/* Move down to proper range now rounding is done */
factors->k = K / 10;
dev_dbg(wm8400->wm8400->dev,
"FLL: Fref=%u Fout=%u N=%x K=%x, FRATIO=%x OUTDIV=%x\n",
Fref, Fout,
factors->n, factors->k, factors->fratio, factors->outdiv);
return 0;
}
static int wm8400_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
int source, unsigned int freq_in,
unsigned int freq_out)
{
struct snd_soc_component *component = codec_dai->component;
struct wm8400_priv *wm8400 = snd_soc_component_get_drvdata(component);
struct fll_factors factors;
int ret;
u16 reg;
if (freq_in == wm8400->fll_in && freq_out == wm8400->fll_out)
return 0;
if (freq_out) {
ret = fll_factors(wm8400, &factors, freq_in, freq_out);
if (ret != 0)
return ret;
} else {
/* Bodge GCC 4.4.0 uninitialised variable warning - it
* doesn't seem capable of working out that we exit if
* freq_out is 0 before any of the uses. */
memset(&factors, 0, sizeof(factors));
}
wm8400->fll_out = freq_out;
wm8400->fll_in = freq_in;
/* We *must* disable the FLL before any changes */
reg = snd_soc_component_read(component, WM8400_POWER_MANAGEMENT_2);
reg &= ~WM8400_FLL_ENA;
snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_2, reg);
reg = snd_soc_component_read(component, WM8400_FLL_CONTROL_1);
reg &= ~WM8400_FLL_OSC_ENA;
snd_soc_component_write(component, WM8400_FLL_CONTROL_1, reg);
if (!freq_out)
return 0;
reg &= ~(WM8400_FLL_REF_FREQ | WM8400_FLL_FRATIO_MASK);
reg |= WM8400_FLL_FRAC | factors.fratio;
reg |= factors.freq_ref << WM8400_FLL_REF_FREQ_SHIFT;
snd_soc_component_write(component, WM8400_FLL_CONTROL_1, reg);
snd_soc_component_write(component, WM8400_FLL_CONTROL_2, factors.k);
snd_soc_component_write(component, WM8400_FLL_CONTROL_3, factors.n);
reg = snd_soc_component_read(component, WM8400_FLL_CONTROL_4);
reg &= ~WM8400_FLL_OUTDIV_MASK;
reg |= factors.outdiv;
snd_soc_component_write(component, WM8400_FLL_CONTROL_4, reg);
return 0;
}
/*
* Sets ADC and Voice DAC format.
*/
static int wm8400_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
u16 audio1, audio3;
audio1 = snd_soc_component_read(component, WM8400_AUDIO_INTERFACE_1);
audio3 = snd_soc_component_read(component, WM8400_AUDIO_INTERFACE_3);
/* set master/slave audio interface */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
audio3 &= ~WM8400_AIF_MSTR1;
break;
case SND_SOC_DAIFMT_CBM_CFM:
audio3 |= WM8400_AIF_MSTR1;
break;
default:
return -EINVAL;
}
audio1 &= ~WM8400_AIF_FMT_MASK;
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
audio1 |= WM8400_AIF_FMT_I2S;
audio1 &= ~WM8400_AIF_LRCLK_INV;
break;
case SND_SOC_DAIFMT_RIGHT_J:
audio1 |= WM8400_AIF_FMT_RIGHTJ;
audio1 &= ~WM8400_AIF_LRCLK_INV;
break;
case SND_SOC_DAIFMT_LEFT_J:
audio1 |= WM8400_AIF_FMT_LEFTJ;
audio1 &= ~WM8400_AIF_LRCLK_INV;
break;
case SND_SOC_DAIFMT_DSP_A:
audio1 |= WM8400_AIF_FMT_DSP;
audio1 &= ~WM8400_AIF_LRCLK_INV;
break;
case SND_SOC_DAIFMT_DSP_B:
audio1 |= WM8400_AIF_FMT_DSP | WM8400_AIF_LRCLK_INV;
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, WM8400_AUDIO_INTERFACE_1, audio1);
snd_soc_component_write(component, WM8400_AUDIO_INTERFACE_3, audio3);
return 0;
}
static int wm8400_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
int div_id, int div)
{
struct snd_soc_component *component = codec_dai->component;
u16 reg;
switch (div_id) {
case WM8400_MCLK_DIV:
reg = snd_soc_component_read(component, WM8400_CLOCKING_2) &
~WM8400_MCLK_DIV_MASK;
snd_soc_component_write(component, WM8400_CLOCKING_2, reg | div);
break;
case WM8400_DACCLK_DIV:
reg = snd_soc_component_read(component, WM8400_CLOCKING_2) &
~WM8400_DAC_CLKDIV_MASK;
snd_soc_component_write(component, WM8400_CLOCKING_2, reg | div);
break;
case WM8400_ADCCLK_DIV:
reg = snd_soc_component_read(component, WM8400_CLOCKING_2) &
~WM8400_ADC_CLKDIV_MASK;
snd_soc_component_write(component, WM8400_CLOCKING_2, reg | div);
break;
case WM8400_BCLK_DIV:
reg = snd_soc_component_read(component, WM8400_CLOCKING_1) &
~WM8400_BCLK_DIV_MASK;
snd_soc_component_write(component, WM8400_CLOCKING_1, reg | div);
break;
default:
return -EINVAL;
}
return 0;
}
/*
* Set PCM DAI bit size and sample rate.
*/
static int wm8400_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
u16 audio1 = snd_soc_component_read(component, WM8400_AUDIO_INTERFACE_1);
audio1 &= ~WM8400_AIF_WL_MASK;
/* bit size */
switch (params_width(params)) {
case 16:
break;
case 20:
audio1 |= WM8400_AIF_WL_20BITS;
break;
case 24:
audio1 |= WM8400_AIF_WL_24BITS;
break;
case 32:
audio1 |= WM8400_AIF_WL_32BITS;
break;
}
snd_soc_component_write(component, WM8400_AUDIO_INTERFACE_1, audio1);
return 0;
}
static int wm8400_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
u16 val = snd_soc_component_read(component, WM8400_DAC_CTRL) & ~WM8400_DAC_MUTE;
if (mute)
snd_soc_component_write(component, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE);
else
snd_soc_component_write(component, WM8400_DAC_CTRL, val);
return 0;
}
/* TODO: set bias for best performance at standby */
static int wm8400_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct wm8400_priv *wm8400 = snd_soc_component_get_drvdata(component);
u16 val;
int ret;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
/* VMID=2*50k */
val = snd_soc_component_read(component, WM8400_POWER_MANAGEMENT_1) &
~WM8400_VMID_MODE_MASK;
snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1, val | 0x2);
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
ret = regulator_bulk_enable(ARRAY_SIZE(power),
&power[0]);
if (ret != 0) {
dev_err(wm8400->wm8400->dev,
"Failed to enable regulators: %d\n",
ret);
return ret;
}
snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1,
WM8400_CODEC_ENA | WM8400_SYSCLK_ENA);
/* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */
snd_soc_component_write(component, WM8400_ANTIPOP2, WM8400_SOFTST |
WM8400_BUFDCOPEN | WM8400_POBCTRL);
msleep(50);
/* Enable VREF & VMID at 2x50k */
val = snd_soc_component_read(component, WM8400_POWER_MANAGEMENT_1);
val |= 0x2 | WM8400_VREF_ENA;
snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1, val);
/* Enable BUFIOEN */
snd_soc_component_write(component, WM8400_ANTIPOP2, WM8400_SOFTST |
WM8400_BUFDCOPEN | WM8400_POBCTRL |
WM8400_BUFIOEN);
/* disable POBCTRL, SOFT_ST and BUFDCOPEN */
snd_soc_component_write(component, WM8400_ANTIPOP2, WM8400_BUFIOEN);
}
/* VMID=2*300k */
val = snd_soc_component_read(component, WM8400_POWER_MANAGEMENT_1) &
~WM8400_VMID_MODE_MASK;
snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1, val | 0x4);
break;
case SND_SOC_BIAS_OFF:
/* Enable POBCTRL and SOFT_ST */
snd_soc_component_write(component, WM8400_ANTIPOP2, WM8400_SOFTST |
WM8400_POBCTRL | WM8400_BUFIOEN);
/* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
snd_soc_component_write(component, WM8400_ANTIPOP2, WM8400_SOFTST |
WM8400_BUFDCOPEN | WM8400_POBCTRL |
WM8400_BUFIOEN);
/* mute DAC */
val = snd_soc_component_read(component, WM8400_DAC_CTRL);
snd_soc_component_write(component, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE);
/* Enable any disabled outputs */
val = snd_soc_component_read(component, WM8400_POWER_MANAGEMENT_1);
val |= WM8400_SPK_ENA | WM8400_OUT3_ENA |
WM8400_OUT4_ENA | WM8400_LOUT_ENA |
WM8400_ROUT_ENA;
snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1, val);
/* Disable VMID */
val &= ~WM8400_VMID_MODE_MASK;
snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1, val);
msleep(300);
/* Enable all output discharge bits */
snd_soc_component_write(component, WM8400_ANTIPOP1, WM8400_DIS_LLINE |
WM8400_DIS_RLINE | WM8400_DIS_OUT3 |
WM8400_DIS_OUT4 | WM8400_DIS_LOUT |
WM8400_DIS_ROUT);
/* Disable VREF */
val &= ~WM8400_VREF_ENA;
snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1, val);
/* disable POBCTRL, SOFT_ST and BUFDCOPEN */
snd_soc_component_write(component, WM8400_ANTIPOP2, 0x0);
ret = regulator_bulk_disable(ARRAY_SIZE(power),
&power[0]);
if (ret != 0)
return ret;
break;
}
return 0;
}
#define WM8400_RATES SNDRV_PCM_RATE_8000_96000
#define WM8400_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE)
static const struct snd_soc_dai_ops wm8400_dai_ops = {
.hw_params = wm8400_hw_params,
.mute_stream = wm8400_mute,
.set_fmt = wm8400_set_dai_fmt,
.set_clkdiv = wm8400_set_dai_clkdiv,
.set_sysclk = wm8400_set_dai_sysclk,
.set_pll = wm8400_set_dai_pll,
.no_capture_mute = 1,
};
/*
* The WM8400 supports 2 different and mutually exclusive DAI
* configurations.
*
* 1. ADC/DAC on Primary Interface
* 2. ADC on Primary Interface/DAC on secondary
*/
static struct snd_soc_dai_driver wm8400_dai = {
/* ADC/DAC on primary */
.name = "wm8400-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM8400_RATES,
.formats = WM8400_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM8400_RATES,
.formats = WM8400_FORMATS,
},
.ops = &wm8400_dai_ops,
};
static int wm8400_component_probe(struct snd_soc_component *component)
{
struct wm8400 *wm8400 = dev_get_platdata(component->dev);
struct wm8400_priv *priv;
int ret;
u16 reg;
priv = devm_kzalloc(component->dev, sizeof(struct wm8400_priv),
GFP_KERNEL);
if (priv == NULL)
return -ENOMEM;
snd_soc_component_init_regmap(component, wm8400->regmap);
snd_soc_component_set_drvdata(component, priv);
priv->wm8400 = wm8400;
ret = devm_regulator_bulk_get(wm8400->dev,
ARRAY_SIZE(power), &power[0]);
if (ret != 0) {
dev_err(component->dev, "Failed to get regulators: %d\n", ret);
return ret;
}
wm8400_component_reset(component);
reg = snd_soc_component_read(component, WM8400_POWER_MANAGEMENT_1);
snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1, reg | WM8400_CODEC_ENA);
/* Latch volume update bits */
reg = snd_soc_component_read(component, WM8400_LEFT_LINE_INPUT_1_2_VOLUME);
snd_soc_component_write(component, WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
reg & WM8400_IPVU);
reg = snd_soc_component_read(component, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME);
snd_soc_component_write(component, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
reg & WM8400_IPVU);
snd_soc_component_write(component, WM8400_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8));
snd_soc_component_write(component, WM8400_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8));
return 0;
}
static void wm8400_component_remove(struct snd_soc_component *component)
{
u16 reg;
reg = snd_soc_component_read(component, WM8400_POWER_MANAGEMENT_1);
snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1,
reg & (~WM8400_CODEC_ENA));
}
static const struct snd_soc_component_driver soc_component_dev_wm8400 = {
.probe = wm8400_component_probe,
.remove = wm8400_component_remove,
.set_bias_level = wm8400_set_bias_level,
.controls = wm8400_snd_controls,
.num_controls = ARRAY_SIZE(wm8400_snd_controls),
.dapm_widgets = wm8400_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8400_dapm_widgets),
.dapm_routes = wm8400_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(wm8400_dapm_routes),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int wm8400_probe(struct platform_device *pdev)
{
return devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_wm8400,
&wm8400_dai, 1);
}
static struct platform_driver wm8400_codec_driver = {
.driver = {
.name = "wm8400-codec",
},
.probe = wm8400_probe,
};
module_platform_driver(wm8400_codec_driver);
MODULE_DESCRIPTION("ASoC WM8400 driver");
MODULE_AUTHOR("Mark Brown");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:wm8400-codec");
| linux-master | sound/soc/codecs/wm8400.c |
// SPDX-License-Identifier: GPL-2.0
//
// rk817 ALSA SoC Audio driver
//
// Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd All rights reserved.
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/mfd/rk808.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
struct rk817_codec_priv {
struct snd_soc_component *component;
struct rk808 *rk808;
struct clk *mclk;
unsigned int stereo_sysclk;
bool mic_in_differential;
};
/*
* This sets the codec up with the values defined in the default implementation including the APLL
* from the Rockchip vendor kernel. I do not know if these values are universal despite differing
* from the default values defined above and taken from the datasheet, or implementation specific.
* I don't have another implementation to compare from the Rockchip sources. Hard-coding for now.
* Additionally, I do not know according to the documentation the units accepted for the clock
* values, so for the moment those are left unvalidated.
*/
static int rk817_init(struct snd_soc_component *component)
{
struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component);
snd_soc_component_write(component, RK817_CODEC_DDAC_POPD_DACST, 0x02);
snd_soc_component_write(component, RK817_CODEC_DDAC_SR_LMT0, 0x02);
snd_soc_component_write(component, RK817_CODEC_DADC_SR_ACL0, 0x02);
snd_soc_component_write(component, RK817_CODEC_DTOP_VUCTIME, 0xf4);
if (rk817->mic_in_differential) {
snd_soc_component_update_bits(component, RK817_CODEC_AMIC_CFG0, MIC_DIFF_MASK,
MIC_DIFF_EN);
}
return 0;
}
static int rk817_set_component_pll(struct snd_soc_component *component,
int pll_id, int source, unsigned int freq_in,
unsigned int freq_out)
{
/* Set resistor value and charge pump current for PLL. */
snd_soc_component_write(component, RK817_CODEC_APLL_CFG1, 0x58);
/* Set the PLL feedback clock divide value (values not documented). */
snd_soc_component_write(component, RK817_CODEC_APLL_CFG2, 0x2d);
/* Set the PLL pre-divide value (values not documented). */
snd_soc_component_write(component, RK817_CODEC_APLL_CFG3, 0x0c);
/* Set the PLL VCO output clock divide and PLL divided ratio of PLL High Clk (values not
* documented).
*/
snd_soc_component_write(component, RK817_CODEC_APLL_CFG4, 0xa5);
return 0;
}
/*
* DDAC/DADC L/R volume setting
* 0db~-95db, 0.375db/step, for example:
* 0x00: 0dB
* 0xff: -95dB
*/
static const DECLARE_TLV_DB_MINMAX(rk817_vol_tlv, -9500, 0);
/*
* PGA GAIN L/R volume setting
* 27db~-18db, 3db/step, for example:
* 0x0: -18dB
* 0xf: 27dB
*/
static const DECLARE_TLV_DB_MINMAX(rk817_gain_tlv, -1800, 2700);
static const struct snd_kcontrol_new rk817_volume_controls[] = {
SOC_DOUBLE_R_RANGE_TLV("Master Playback Volume", RK817_CODEC_DDAC_VOLL,
RK817_CODEC_DDAC_VOLR, 0, 0x00, 0xff, 1, rk817_vol_tlv),
SOC_DOUBLE_R_RANGE_TLV("Master Capture Volume", RK817_CODEC_DADC_VOLL,
RK817_CODEC_DADC_VOLR, 0, 0x00, 0xff, 1, rk817_vol_tlv),
SOC_DOUBLE_TLV("Mic Capture Gain", RK817_CODEC_DMIC_PGA_GAIN, 4, 0, 0xf, 0,
rk817_gain_tlv),
};
/* Since the speaker output and L headphone pin are internally the same, make audio path mutually
* exclusive with a mux.
*/
static const char *dac_mux_text[] = {
"HP",
"SPK",
};
static SOC_ENUM_SINGLE_VIRT_DECL(dac_enum, dac_mux_text);
static const struct snd_kcontrol_new dac_mux =
SOC_DAPM_ENUM("Playback Mux", dac_enum);
static const struct snd_soc_dapm_widget rk817_dapm_widgets[] = {
/* capture/playback common */
SND_SOC_DAPM_SUPPLY("LDO Regulator", RK817_CODEC_AREF_RTCFG1, 6, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("IBIAS Block", RK817_CODEC_AREF_RTCFG1, 2, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("VAvg Buffer", RK817_CODEC_AREF_RTCFG1, 1, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("PLL Power", RK817_CODEC_APLL_CFG5, 0, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("I2S TX1 Transfer Start", RK817_CODEC_DI2S_RXCMD_TSD, 5, 0, NULL, 0),
/* capture path common */
SND_SOC_DAPM_SUPPLY("ADC Clock", RK817_CODEC_DTOP_DIGEN_CLKE, 7, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("I2S TX Clock", RK817_CODEC_DTOP_DIGEN_CLKE, 6, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC Channel Enable", RK817_CODEC_DTOP_DIGEN_CLKE, 5, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("I2S TX Channel Enable", RK817_CODEC_DTOP_DIGEN_CLKE, 4, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MIC Power On", RK817_CODEC_AMIC_CFG0, 6, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("I2S TX3 Transfer Start", RK817_CODEC_DI2S_TXCR3_TXCMD, 7, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("I2S TX3 Right Justified", RK817_CODEC_DI2S_TXCR3_TXCMD, 3, 0, NULL, 0),
/* capture path L */
SND_SOC_DAPM_ADC("ADC L", "Capture", RK817_CODEC_AADC_CFG0, 7, 1),
SND_SOC_DAPM_SUPPLY("PGA L Power On", RK817_CODEC_AMIC_CFG0, 5, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("Mic Boost L1", RK817_CODEC_AMIC_CFG0, 3, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Mic Boost L2", RK817_CODEC_AMIC_CFG0, 2, 0, NULL, 0),
/* capture path R */
SND_SOC_DAPM_ADC("ADC R", "Capture", RK817_CODEC_AADC_CFG0, 6, 1),
SND_SOC_DAPM_SUPPLY("PGA R Power On", RK817_CODEC_AMIC_CFG0, 4, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("Mic Boost R1", RK817_CODEC_AMIC_CFG0, 3, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Mic Boost R2", RK817_CODEC_AMIC_CFG0, 3, 0, NULL, 0),
/* playback path common */
SND_SOC_DAPM_SUPPLY("DAC Clock", RK817_CODEC_DTOP_DIGEN_CLKE, 3, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("I2S RX Clock", RK817_CODEC_DTOP_DIGEN_CLKE, 2, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC Channel Enable", RK817_CODEC_DTOP_DIGEN_CLKE, 1, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("I2S RX Channel Enable", RK817_CODEC_DTOP_DIGEN_CLKE, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC Bias", RK817_CODEC_ADAC_CFG1, 3, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC Mute Off", RK817_CODEC_DDAC_MUTE_MIXCTL, 0, 1, NULL, 0),
/* playback path speaker */
SND_SOC_DAPM_SUPPLY("Class D Mode", RK817_CODEC_DDAC_MUTE_MIXCTL, 4, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("High Pass Filter", RK817_CODEC_DDAC_MUTE_MIXCTL, 7, 0, NULL, 0),
SND_SOC_DAPM_DAC("SPK DAC", "Playback", RK817_CODEC_ADAC_CFG1, 2, 1),
SND_SOC_DAPM_SUPPLY("Enable Class D", RK817_CODEC_ACLASSD_CFG1, 7, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Disable Class D Mute Ramp", RK817_CODEC_ACLASSD_CFG1, 6, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("Class D Mute Rate 1", RK817_CODEC_ACLASSD_CFG1, 3, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Class D Mute Rate 2", RK817_CODEC_ACLASSD_CFG1, 2, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("Class D OCPP 2", RK817_CODEC_ACLASSD_CFG2, 5, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Class D OCPP 3", RK817_CODEC_ACLASSD_CFG2, 4, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Class D OCPN 2", RK817_CODEC_ACLASSD_CFG2, 1, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Class D OCPN 3", RK817_CODEC_ACLASSD_CFG2, 0, 0, NULL, 0),
/* playback path headphones */
SND_SOC_DAPM_SUPPLY("Headphone Charge Pump", RK817_CODEC_AHP_CP, 4, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Headphone CP Discharge LDO", RK817_CODEC_AHP_CP, 3, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("Headphone OStage", RK817_CODEC_AHP_CFG0, 6, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("Headphone Pre Amp", RK817_CODEC_AHP_CFG0, 5, 1, NULL, 0),
SND_SOC_DAPM_DAC("DAC L", "Playback", RK817_CODEC_ADAC_CFG1, 1, 1),
SND_SOC_DAPM_DAC("DAC R", "Playback", RK817_CODEC_ADAC_CFG1, 0, 1),
/* Mux for input/output path selection */
SND_SOC_DAPM_MUX("Playback Mux", SND_SOC_NOPM, 1, 0, &dac_mux),
/* Pins for Simple Card Bindings */
SND_SOC_DAPM_INPUT("MICL"),
SND_SOC_DAPM_INPUT("MICR"),
SND_SOC_DAPM_OUTPUT("HPOL"),
SND_SOC_DAPM_OUTPUT("HPOR"),
SND_SOC_DAPM_OUTPUT("SPKO"),
};
static const struct snd_soc_dapm_route rk817_dapm_routes[] = {
/* capture path */
/* left mic */
{"ADC L", NULL, "LDO Regulator"},
{"ADC L", NULL, "IBIAS Block"},
{"ADC L", NULL, "VAvg Buffer"},
{"ADC L", NULL, "PLL Power"},
{"ADC L", NULL, "ADC Clock"},
{"ADC L", NULL, "I2S TX Clock"},
{"ADC L", NULL, "ADC Channel Enable"},
{"ADC L", NULL, "I2S TX Channel Enable"},
{"ADC L", NULL, "I2S TX1 Transfer Start"},
{"MICL", NULL, "MIC Power On"},
{"MICL", NULL, "PGA L Power On"},
{"MICL", NULL, "Mic Boost L1"},
{"MICL", NULL, "Mic Boost L2"},
{"MICL", NULL, "I2S TX3 Transfer Start"},
{"MICL", NULL, "I2S TX3 Right Justified"},
{"ADC L", NULL, "MICL"},
/* right mic */
{"ADC R", NULL, "LDO Regulator"},
{"ADC R", NULL, "IBIAS Block"},
{"ADC R", NULL, "VAvg Buffer"},
{"ADC R", NULL, "PLL Power"},
{"ADC R", NULL, "ADC Clock"},
{"ADC R", NULL, "I2S TX Clock"},
{"ADC R", NULL, "ADC Channel Enable"},
{"ADC R", NULL, "I2S TX Channel Enable"},
{"ADC R", NULL, "I2S TX1 Transfer Start"},
{"MICR", NULL, "MIC Power On"},
{"MICR", NULL, "PGA R Power On"},
{"MICR", NULL, "Mic Boost R1"},
{"MICR", NULL, "Mic Boost R2"},
{"MICR", NULL, "I2S TX3 Transfer Start"},
{"MICR", NULL, "I2S TX3 Right Justified"},
{"ADC R", NULL, "MICR"},
/* playback path */
/* speaker path */
{"SPK DAC", NULL, "LDO Regulator"},
{"SPK DAC", NULL, "IBIAS Block"},
{"SPK DAC", NULL, "VAvg Buffer"},
{"SPK DAC", NULL, "PLL Power"},
{"SPK DAC", NULL, "I2S TX1 Transfer Start"},
{"SPK DAC", NULL, "DAC Clock"},
{"SPK DAC", NULL, "I2S RX Clock"},
{"SPK DAC", NULL, "DAC Channel Enable"},
{"SPK DAC", NULL, "I2S RX Channel Enable"},
{"SPK DAC", NULL, "Class D Mode"},
{"SPK DAC", NULL, "DAC Bias"},
{"SPK DAC", NULL, "DAC Mute Off"},
{"SPK DAC", NULL, "Enable Class D"},
{"SPK DAC", NULL, "Disable Class D Mute Ramp"},
{"SPK DAC", NULL, "Class D Mute Rate 1"},
{"SPK DAC", NULL, "Class D Mute Rate 2"},
{"SPK DAC", NULL, "Class D OCPP 2"},
{"SPK DAC", NULL, "Class D OCPP 3"},
{"SPK DAC", NULL, "Class D OCPN 2"},
{"SPK DAC", NULL, "Class D OCPN 3"},
{"SPK DAC", NULL, "High Pass Filter"},
/* headphone path L */
{"DAC L", NULL, "LDO Regulator"},
{"DAC L", NULL, "IBIAS Block"},
{"DAC L", NULL, "VAvg Buffer"},
{"DAC L", NULL, "PLL Power"},
{"DAC L", NULL, "I2S TX1 Transfer Start"},
{"DAC L", NULL, "DAC Clock"},
{"DAC L", NULL, "I2S RX Clock"},
{"DAC L", NULL, "DAC Channel Enable"},
{"DAC L", NULL, "I2S RX Channel Enable"},
{"DAC L", NULL, "DAC Bias"},
{"DAC L", NULL, "DAC Mute Off"},
{"DAC L", NULL, "Headphone Charge Pump"},
{"DAC L", NULL, "Headphone CP Discharge LDO"},
{"DAC L", NULL, "Headphone OStage"},
{"DAC L", NULL, "Headphone Pre Amp"},
/* headphone path R */
{"DAC R", NULL, "LDO Regulator"},
{"DAC R", NULL, "IBIAS Block"},
{"DAC R", NULL, "VAvg Buffer"},
{"DAC R", NULL, "PLL Power"},
{"DAC R", NULL, "I2S TX1 Transfer Start"},
{"DAC R", NULL, "DAC Clock"},
{"DAC R", NULL, "I2S RX Clock"},
{"DAC R", NULL, "DAC Channel Enable"},
{"DAC R", NULL, "I2S RX Channel Enable"},
{"DAC R", NULL, "DAC Bias"},
{"DAC R", NULL, "DAC Mute Off"},
{"DAC R", NULL, "Headphone Charge Pump"},
{"DAC R", NULL, "Headphone CP Discharge LDO"},
{"DAC R", NULL, "Headphone OStage"},
{"DAC R", NULL, "Headphone Pre Amp"},
/* mux path for output selection */
{"Playback Mux", "HP", "DAC L"},
{"Playback Mux", "HP", "DAC R"},
{"Playback Mux", "SPK", "SPK DAC"},
{"SPKO", NULL, "Playback Mux"},
{"HPOL", NULL, "Playback Mux"},
{"HPOR", NULL, "Playback Mux"},
};
static int rk817_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component);
rk817->stereo_sysclk = freq;
return 0;
}
static int rk817_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
unsigned int i2s_mst = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
i2s_mst |= RK817_I2S_MODE_SLV;
break;
case SND_SOC_DAIFMT_CBM_CFM:
i2s_mst |= RK817_I2S_MODE_MST;
break;
default:
dev_err(component->dev, "%s : set master mask failed!\n", __func__);
return -EINVAL;
}
snd_soc_component_update_bits(component, RK817_CODEC_DI2S_CKM,
RK817_I2S_MODE_MASK, i2s_mst);
return 0;
}
static int rk817_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
snd_soc_component_write(component, RK817_CODEC_DI2S_RXCR2,
VDW_RX_16BITS);
snd_soc_component_write(component, RK817_CODEC_DI2S_TXCR2,
VDW_TX_16BITS);
break;
case SNDRV_PCM_FORMAT_S24_LE:
case SNDRV_PCM_FORMAT_S32_LE:
snd_soc_component_write(component, RK817_CODEC_DI2S_RXCR2,
VDW_RX_24BITS);
snd_soc_component_write(component, RK817_CODEC_DI2S_TXCR2,
VDW_TX_24BITS);
break;
default:
return -EINVAL;
}
return 0;
}
static int rk817_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
{
struct snd_soc_component *component = dai->component;
if (mute)
snd_soc_component_update_bits(component,
RK817_CODEC_DDAC_MUTE_MIXCTL,
DACMT_MASK, DACMT_ENABLE);
else
snd_soc_component_update_bits(component,
RK817_CODEC_DDAC_MUTE_MIXCTL,
DACMT_MASK, DACMT_DISABLE);
return 0;
}
#define RK817_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
SNDRV_PCM_RATE_16000 | \
SNDRV_PCM_RATE_32000 | \
SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000 | \
SNDRV_PCM_RATE_96000)
#define RK817_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
SNDRV_PCM_RATE_16000 | \
SNDRV_PCM_RATE_32000 | \
SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000 | \
SNDRV_PCM_RATE_96000)
#define RK817_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops rk817_dai_ops = {
.hw_params = rk817_hw_params,
.set_fmt = rk817_set_dai_fmt,
.set_sysclk = rk817_set_dai_sysclk,
.mute_stream = rk817_digital_mute,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver rk817_dai[] = {
{
.name = "rk817-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 8,
.rates = RK817_PLAYBACK_RATES,
.formats = RK817_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RK817_CAPTURE_RATES,
.formats = RK817_FORMATS,
},
.ops = &rk817_dai_ops,
},
};
static int rk817_probe(struct snd_soc_component *component)
{
struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component);
struct rk808 *rk808 = dev_get_drvdata(component->dev->parent);
snd_soc_component_init_regmap(component, rk808->regmap);
rk817->component = component;
snd_soc_component_write(component, RK817_CODEC_DTOP_LPT_SRST, 0x40);
rk817_init(component);
/* setting initial pll values so that we can continue to leverage simple-audio-card.
* The values aren't important since no parameters are used.
*/
snd_soc_component_set_pll(component, 0, 0, 0, 0);
return 0;
}
static void rk817_remove(struct snd_soc_component *component)
{
snd_soc_component_exit_regmap(component);
}
static const struct snd_soc_component_driver soc_codec_dev_rk817 = {
.probe = rk817_probe,
.remove = rk817_remove,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
.controls = rk817_volume_controls,
.num_controls = ARRAY_SIZE(rk817_volume_controls),
.dapm_routes = rk817_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(rk817_dapm_routes),
.dapm_widgets = rk817_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rk817_dapm_widgets),
.set_pll = rk817_set_component_pll,
};
static void rk817_codec_parse_dt_property(struct device *dev,
struct rk817_codec_priv *rk817)
{
struct device_node *node;
node = of_get_child_by_name(dev->parent->of_node, "codec");
if (!node) {
dev_dbg(dev, "%s() Can not get child: codec\n",
__func__);
}
rk817->mic_in_differential =
of_property_read_bool(node, "rockchip,mic-in-differential");
of_node_put(node);
}
static int rk817_platform_probe(struct platform_device *pdev)
{
struct rk808 *rk808 = dev_get_drvdata(pdev->dev.parent);
struct rk817_codec_priv *rk817_codec_data;
int ret;
rk817_codec_data = devm_kzalloc(&pdev->dev,
sizeof(struct rk817_codec_priv),
GFP_KERNEL);
if (!rk817_codec_data)
return -ENOMEM;
platform_set_drvdata(pdev, rk817_codec_data);
rk817_codec_data->rk808 = rk808;
rk817_codec_parse_dt_property(&pdev->dev, rk817_codec_data);
rk817_codec_data->mclk = devm_clk_get(pdev->dev.parent, "mclk");
if (IS_ERR(rk817_codec_data->mclk)) {
dev_dbg(&pdev->dev, "Unable to get mclk\n");
ret = -ENXIO;
goto err_;
}
ret = clk_prepare_enable(rk817_codec_data->mclk);
if (ret < 0) {
dev_err(&pdev->dev, "%s() clock prepare error %d\n",
__func__, ret);
goto err_;
}
ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_dev_rk817,
rk817_dai, ARRAY_SIZE(rk817_dai));
if (ret < 0) {
dev_err(&pdev->dev, "%s() register codec error %d\n",
__func__, ret);
goto err_clk;
}
return 0;
err_clk:
clk_disable_unprepare(rk817_codec_data->mclk);
err_:
return ret;
}
static void rk817_platform_remove(struct platform_device *pdev)
{
struct rk817_codec_priv *rk817 = platform_get_drvdata(pdev);
clk_disable_unprepare(rk817->mclk);
}
static struct platform_driver rk817_codec_driver = {
.driver = {
.name = "rk817-codec",
},
.probe = rk817_platform_probe,
.remove_new = rk817_platform_remove,
};
module_platform_driver(rk817_codec_driver);
MODULE_DESCRIPTION("ASoC RK817 codec driver");
MODULE_AUTHOR("binyuan <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:rk817-codec");
| linux-master | sound/soc/codecs/rk817_codec.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8955.c -- WM8955 ALSA SoC Audio driver
*
* Copyright 2009 Wolfson Microelectronics plc
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/wm8955.h>
#include "wm8955.h"
#define WM8955_NUM_SUPPLIES 4
static const char *wm8955_supply_names[WM8955_NUM_SUPPLIES] = {
"DCVDD",
"DBVDD",
"HPVDD",
"AVDD",
};
/* codec private data */
struct wm8955_priv {
struct regmap *regmap;
unsigned int mclk_rate;
int deemph;
int fs;
struct regulator_bulk_data supplies[WM8955_NUM_SUPPLIES];
};
static const struct reg_default wm8955_reg_defaults[] = {
{ 2, 0x0079 }, /* R2 - LOUT1 volume */
{ 3, 0x0079 }, /* R3 - ROUT1 volume */
{ 5, 0x0008 }, /* R5 - DAC Control */
{ 7, 0x000A }, /* R7 - Audio Interface */
{ 8, 0x0000 }, /* R8 - Sample Rate */
{ 10, 0x00FF }, /* R10 - Left DAC volume */
{ 11, 0x00FF }, /* R11 - Right DAC volume */
{ 12, 0x000F }, /* R12 - Bass control */
{ 13, 0x000F }, /* R13 - Treble control */
{ 23, 0x00C1 }, /* R23 - Additional control (1) */
{ 24, 0x0000 }, /* R24 - Additional control (2) */
{ 25, 0x0000 }, /* R25 - Power Management (1) */
{ 26, 0x0000 }, /* R26 - Power Management (2) */
{ 27, 0x0000 }, /* R27 - Additional Control (3) */
{ 34, 0x0050 }, /* R34 - Left out Mix (1) */
{ 35, 0x0050 }, /* R35 - Left out Mix (2) */
{ 36, 0x0050 }, /* R36 - Right out Mix (1) */
{ 37, 0x0050 }, /* R37 - Right Out Mix (2) */
{ 38, 0x0050 }, /* R38 - Mono out Mix (1) */
{ 39, 0x0050 }, /* R39 - Mono out Mix (2) */
{ 40, 0x0079 }, /* R40 - LOUT2 volume */
{ 41, 0x0079 }, /* R41 - ROUT2 volume */
{ 42, 0x0079 }, /* R42 - MONOOUT volume */
{ 43, 0x0000 }, /* R43 - Clocking / PLL */
{ 44, 0x0103 }, /* R44 - PLL Control 1 */
{ 45, 0x0024 }, /* R45 - PLL Control 2 */
{ 46, 0x01BA }, /* R46 - PLL Control 3 */
{ 59, 0x0000 }, /* R59 - PLL Control 4 */
};
static bool wm8955_writeable(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8955_LOUT1_VOLUME:
case WM8955_ROUT1_VOLUME:
case WM8955_DAC_CONTROL:
case WM8955_AUDIO_INTERFACE:
case WM8955_SAMPLE_RATE:
case WM8955_LEFT_DAC_VOLUME:
case WM8955_RIGHT_DAC_VOLUME:
case WM8955_BASS_CONTROL:
case WM8955_TREBLE_CONTROL:
case WM8955_RESET:
case WM8955_ADDITIONAL_CONTROL_1:
case WM8955_ADDITIONAL_CONTROL_2:
case WM8955_POWER_MANAGEMENT_1:
case WM8955_POWER_MANAGEMENT_2:
case WM8955_ADDITIONAL_CONTROL_3:
case WM8955_LEFT_OUT_MIX_1:
case WM8955_LEFT_OUT_MIX_2:
case WM8955_RIGHT_OUT_MIX_1:
case WM8955_RIGHT_OUT_MIX_2:
case WM8955_MONO_OUT_MIX_1:
case WM8955_MONO_OUT_MIX_2:
case WM8955_LOUT2_VOLUME:
case WM8955_ROUT2_VOLUME:
case WM8955_MONOOUT_VOLUME:
case WM8955_CLOCKING_PLL:
case WM8955_PLL_CONTROL_1:
case WM8955_PLL_CONTROL_2:
case WM8955_PLL_CONTROL_3:
case WM8955_PLL_CONTROL_4:
return true;
default:
return false;
}
}
static bool wm8955_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8955_RESET:
return true;
default:
return false;
}
}
static int wm8955_reset(struct snd_soc_component *component)
{
return snd_soc_component_write(component, WM8955_RESET, 0);
}
struct pll_factors {
int n;
int k;
int outdiv;
};
/* The size in bits of the FLL divide multiplied by 10
* to allow rounding later */
#define FIXED_FLL_SIZE ((1 << 22) * 10)
static int wm8955_pll_factors(struct device *dev,
int Fref, int Fout, struct pll_factors *pll)
{
u64 Kpart;
unsigned int K, Ndiv, Nmod, target;
dev_dbg(dev, "Fref=%u Fout=%u\n", Fref, Fout);
/* The oscilator should run at should be 90-100MHz, and
* there's a divide by 4 plus an optional divide by 2 in the
* output path to generate the system clock. The clock table
* is sortd so we should always generate a suitable target. */
target = Fout * 4;
if (target < 90000000) {
pll->outdiv = 1;
target *= 2;
} else {
pll->outdiv = 0;
}
WARN_ON(target < 90000000 || target > 100000000);
dev_dbg(dev, "Fvco=%dHz\n", target);
/* Now, calculate N.K */
Ndiv = target / Fref;
pll->n = Ndiv;
Nmod = target % Fref;
dev_dbg(dev, "Nmod=%d\n", Nmod);
/* Calculate fractional part - scale up so we can round. */
Kpart = FIXED_FLL_SIZE * (long long)Nmod;
do_div(Kpart, Fref);
K = Kpart & 0xFFFFFFFF;
if ((K % 10) >= 5)
K += 5;
/* Move down to proper range now rounding is done */
pll->k = K / 10;
dev_dbg(dev, "N=%x K=%x OUTDIV=%x\n", pll->n, pll->k, pll->outdiv);
return 0;
}
/* Lookup table specifying SRATE (table 25 in datasheet); some of the
* output frequencies have been rounded to the standard frequencies
* they are intended to match where the error is slight. */
static struct {
int mclk;
int fs;
int usb;
int sr;
} clock_cfgs[] = {
{ 18432000, 8000, 0, 3, },
{ 18432000, 12000, 0, 9, },
{ 18432000, 16000, 0, 11, },
{ 18432000, 24000, 0, 29, },
{ 18432000, 32000, 0, 13, },
{ 18432000, 48000, 0, 1, },
{ 18432000, 96000, 0, 15, },
{ 16934400, 8018, 0, 19, },
{ 16934400, 11025, 0, 25, },
{ 16934400, 22050, 0, 27, },
{ 16934400, 44100, 0, 17, },
{ 16934400, 88200, 0, 31, },
{ 12000000, 8000, 1, 2, },
{ 12000000, 11025, 1, 25, },
{ 12000000, 12000, 1, 8, },
{ 12000000, 16000, 1, 10, },
{ 12000000, 22050, 1, 27, },
{ 12000000, 24000, 1, 28, },
{ 12000000, 32000, 1, 12, },
{ 12000000, 44100, 1, 17, },
{ 12000000, 48000, 1, 0, },
{ 12000000, 88200, 1, 31, },
{ 12000000, 96000, 1, 14, },
{ 12288000, 8000, 0, 2, },
{ 12288000, 12000, 0, 8, },
{ 12288000, 16000, 0, 10, },
{ 12288000, 24000, 0, 28, },
{ 12288000, 32000, 0, 12, },
{ 12288000, 48000, 0, 0, },
{ 12288000, 96000, 0, 14, },
{ 12289600, 8018, 0, 18, },
{ 12289600, 11025, 0, 24, },
{ 12289600, 22050, 0, 26, },
{ 11289600, 44100, 0, 16, },
{ 11289600, 88200, 0, 31, },
};
static int wm8955_configure_clocking(struct snd_soc_component *component)
{
struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component);
int i, ret, val;
int clocking = 0;
int srate = 0;
int sr = -1;
struct pll_factors pll;
/* If we're not running a sample rate currently just pick one */
if (wm8955->fs == 0)
wm8955->fs = 8000;
/* Can we generate an exact output? */
for (i = 0; i < ARRAY_SIZE(clock_cfgs); i++) {
if (wm8955->fs != clock_cfgs[i].fs)
continue;
sr = i;
if (wm8955->mclk_rate == clock_cfgs[i].mclk)
break;
}
/* We should never get here with an unsupported sample rate */
if (sr == -1) {
dev_err(component->dev, "Sample rate %dHz unsupported\n",
wm8955->fs);
WARN_ON(sr == -1);
return -EINVAL;
}
if (i == ARRAY_SIZE(clock_cfgs)) {
/* If we can't generate the right clock from MCLK then
* we should configure the PLL to supply us with an
* appropriate clock.
*/
clocking |= WM8955_MCLKSEL;
/* Use the last divider configuration we saw for the
* sample rate. */
ret = wm8955_pll_factors(component->dev, wm8955->mclk_rate,
clock_cfgs[sr].mclk, &pll);
if (ret != 0) {
dev_err(component->dev,
"Unable to generate %dHz from %dHz MCLK\n",
wm8955->fs, wm8955->mclk_rate);
return -EINVAL;
}
snd_soc_component_update_bits(component, WM8955_PLL_CONTROL_1,
WM8955_N_MASK | WM8955_K_21_18_MASK,
(pll.n << WM8955_N_SHIFT) |
pll.k >> 18);
snd_soc_component_update_bits(component, WM8955_PLL_CONTROL_2,
WM8955_K_17_9_MASK,
(pll.k >> 9) & WM8955_K_17_9_MASK);
snd_soc_component_update_bits(component, WM8955_PLL_CONTROL_3,
WM8955_K_8_0_MASK,
pll.k & WM8955_K_8_0_MASK);
if (pll.k)
snd_soc_component_update_bits(component, WM8955_PLL_CONTROL_4,
WM8955_KEN, WM8955_KEN);
else
snd_soc_component_update_bits(component, WM8955_PLL_CONTROL_4,
WM8955_KEN, 0);
if (pll.outdiv)
val = WM8955_PLL_RB | WM8955_PLLOUTDIV2;
else
val = WM8955_PLL_RB;
/* Now start the PLL running */
snd_soc_component_update_bits(component, WM8955_CLOCKING_PLL,
WM8955_PLL_RB | WM8955_PLLOUTDIV2, val);
snd_soc_component_update_bits(component, WM8955_CLOCKING_PLL,
WM8955_PLLEN, WM8955_PLLEN);
}
srate = clock_cfgs[sr].usb | (clock_cfgs[sr].sr << WM8955_SR_SHIFT);
snd_soc_component_update_bits(component, WM8955_SAMPLE_RATE,
WM8955_USB | WM8955_SR_MASK, srate);
snd_soc_component_update_bits(component, WM8955_CLOCKING_PLL,
WM8955_MCLKSEL, clocking);
return 0;
}
static int wm8955_sysclk(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
int ret = 0;
/* Always disable the clocks - if we're doing reconfiguration this
* avoids misclocking.
*/
snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1,
WM8955_DIGENB, 0);
snd_soc_component_update_bits(component, WM8955_CLOCKING_PLL,
WM8955_PLL_RB | WM8955_PLLEN, 0);
switch (event) {
case SND_SOC_DAPM_POST_PMD:
break;
case SND_SOC_DAPM_PRE_PMU:
ret = wm8955_configure_clocking(component);
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static int deemph_settings[] = { 0, 32000, 44100, 48000 };
static int wm8955_set_deemph(struct snd_soc_component *component)
{
struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component);
int val, i, best;
/* If we're using deemphasis select the nearest available sample
* rate.
*/
if (wm8955->deemph) {
best = 1;
for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
if (abs(deemph_settings[i] - wm8955->fs) <
abs(deemph_settings[best] - wm8955->fs))
best = i;
}
val = best << WM8955_DEEMPH_SHIFT;
} else {
val = 0;
}
dev_dbg(component->dev, "Set deemphasis %d\n", val);
return snd_soc_component_update_bits(component, WM8955_DAC_CONTROL,
WM8955_DEEMPH_MASK, val);
}
static int wm8955_get_deemph(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = wm8955->deemph;
return 0;
}
static int wm8955_put_deemph(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component);
unsigned int deemph = ucontrol->value.integer.value[0];
if (deemph > 1)
return -EINVAL;
wm8955->deemph = deemph;
return wm8955_set_deemph(component);
}
static const char *bass_mode_text[] = {
"Linear", "Adaptive",
};
static SOC_ENUM_SINGLE_DECL(bass_mode, WM8955_BASS_CONTROL, 7, bass_mode_text);
static const char *bass_cutoff_text[] = {
"Low", "High"
};
static SOC_ENUM_SINGLE_DECL(bass_cutoff, WM8955_BASS_CONTROL, 6,
bass_cutoff_text);
static const char *treble_cutoff_text[] = {
"High", "Low"
};
static SOC_ENUM_SINGLE_DECL(treble_cutoff, WM8955_TREBLE_CONTROL, 2,
treble_cutoff_text);
static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
static const DECLARE_TLV_DB_SCALE(atten_tlv, -600, 600, 0);
static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
static const DECLARE_TLV_DB_SCALE(mono_tlv, -2100, 300, 0);
static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
static const DECLARE_TLV_DB_SCALE(treble_tlv, -1200, 150, 1);
static const struct snd_kcontrol_new wm8955_snd_controls[] = {
SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8955_LEFT_DAC_VOLUME,
WM8955_RIGHT_DAC_VOLUME, 0, 255, 0, digital_tlv),
SOC_SINGLE_TLV("Playback Attenuation Volume", WM8955_DAC_CONTROL, 7, 1, 1,
atten_tlv),
SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
wm8955_get_deemph, wm8955_put_deemph),
SOC_ENUM("Bass Mode", bass_mode),
SOC_ENUM("Bass Cutoff", bass_cutoff),
SOC_SINGLE("Bass Volume", WM8955_BASS_CONTROL, 0, 15, 1),
SOC_ENUM("Treble Cutoff", treble_cutoff),
SOC_SINGLE_TLV("Treble Volume", WM8955_TREBLE_CONTROL, 0, 14, 1, treble_tlv),
SOC_SINGLE_TLV("Left Bypass Volume", WM8955_LEFT_OUT_MIX_1, 4, 7, 1,
bypass_tlv),
SOC_SINGLE_TLV("Left Mono Volume", WM8955_LEFT_OUT_MIX_2, 4, 7, 1,
bypass_tlv),
SOC_SINGLE_TLV("Right Mono Volume", WM8955_RIGHT_OUT_MIX_1, 4, 7, 1,
bypass_tlv),
SOC_SINGLE_TLV("Right Bypass Volume", WM8955_RIGHT_OUT_MIX_2, 4, 7, 1,
bypass_tlv),
/* Not a stereo pair so they line up with the DAPM switches */
SOC_SINGLE_TLV("Mono Left Bypass Volume", WM8955_MONO_OUT_MIX_1, 4, 7, 1,
mono_tlv),
SOC_SINGLE_TLV("Mono Right Bypass Volume", WM8955_MONO_OUT_MIX_2, 4, 7, 1,
mono_tlv),
SOC_DOUBLE_R_TLV("Headphone Volume", WM8955_LOUT1_VOLUME,
WM8955_ROUT1_VOLUME, 0, 127, 0, out_tlv),
SOC_DOUBLE_R("Headphone ZC Switch", WM8955_LOUT1_VOLUME,
WM8955_ROUT1_VOLUME, 7, 1, 0),
SOC_DOUBLE_R_TLV("Speaker Volume", WM8955_LOUT2_VOLUME,
WM8955_ROUT2_VOLUME, 0, 127, 0, out_tlv),
SOC_DOUBLE_R("Speaker ZC Switch", WM8955_LOUT2_VOLUME,
WM8955_ROUT2_VOLUME, 7, 1, 0),
SOC_SINGLE_TLV("Mono Volume", WM8955_MONOOUT_VOLUME, 0, 127, 0, out_tlv),
SOC_SINGLE("Mono ZC Switch", WM8955_MONOOUT_VOLUME, 7, 1, 0),
};
static const struct snd_kcontrol_new lmixer[] = {
SOC_DAPM_SINGLE("Playback Switch", WM8955_LEFT_OUT_MIX_1, 8, 1, 0),
SOC_DAPM_SINGLE("Bypass Switch", WM8955_LEFT_OUT_MIX_1, 7, 1, 0),
SOC_DAPM_SINGLE("Right Playback Switch", WM8955_LEFT_OUT_MIX_2, 8, 1, 0),
SOC_DAPM_SINGLE("Mono Switch", WM8955_LEFT_OUT_MIX_2, 7, 1, 0),
};
static const struct snd_kcontrol_new rmixer[] = {
SOC_DAPM_SINGLE("Left Playback Switch", WM8955_RIGHT_OUT_MIX_1, 8, 1, 0),
SOC_DAPM_SINGLE("Mono Switch", WM8955_RIGHT_OUT_MIX_1, 7, 1, 0),
SOC_DAPM_SINGLE("Playback Switch", WM8955_RIGHT_OUT_MIX_2, 8, 1, 0),
SOC_DAPM_SINGLE("Bypass Switch", WM8955_RIGHT_OUT_MIX_2, 7, 1, 0),
};
static const struct snd_kcontrol_new mmixer[] = {
SOC_DAPM_SINGLE("Left Playback Switch", WM8955_MONO_OUT_MIX_1, 8, 1, 0),
SOC_DAPM_SINGLE("Left Bypass Switch", WM8955_MONO_OUT_MIX_1, 7, 1, 0),
SOC_DAPM_SINGLE("Right Playback Switch", WM8955_MONO_OUT_MIX_2, 8, 1, 0),
SOC_DAPM_SINGLE("Right Bypass Switch", WM8955_MONO_OUT_MIX_2, 7, 1, 0),
};
static const struct snd_soc_dapm_widget wm8955_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("MONOIN-"),
SND_SOC_DAPM_INPUT("MONOIN+"),
SND_SOC_DAPM_INPUT("LINEINR"),
SND_SOC_DAPM_INPUT("LINEINL"),
SND_SOC_DAPM_PGA("Mono Input", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("SYSCLK", WM8955_POWER_MANAGEMENT_1, 0, 1, wm8955_sysclk,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("TSDEN", WM8955_ADDITIONAL_CONTROL_1, 8, 0, NULL, 0),
SND_SOC_DAPM_DAC("DACL", "Playback", WM8955_POWER_MANAGEMENT_2, 8, 0),
SND_SOC_DAPM_DAC("DACR", "Playback", WM8955_POWER_MANAGEMENT_2, 7, 0),
SND_SOC_DAPM_PGA("LOUT1 PGA", WM8955_POWER_MANAGEMENT_2, 6, 0, NULL, 0),
SND_SOC_DAPM_PGA("ROUT1 PGA", WM8955_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA("LOUT2 PGA", WM8955_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
SND_SOC_DAPM_PGA("ROUT2 PGA", WM8955_POWER_MANAGEMENT_2, 3, 0, NULL, 0),
SND_SOC_DAPM_PGA("MOUT PGA", WM8955_POWER_MANAGEMENT_2, 2, 0, NULL, 0),
SND_SOC_DAPM_PGA("OUT3 PGA", WM8955_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
/* The names are chosen to make the control names nice */
SND_SOC_DAPM_MIXER("Left", SND_SOC_NOPM, 0, 0,
lmixer, ARRAY_SIZE(lmixer)),
SND_SOC_DAPM_MIXER("Right", SND_SOC_NOPM, 0, 0,
rmixer, ARRAY_SIZE(rmixer)),
SND_SOC_DAPM_MIXER("Mono", SND_SOC_NOPM, 0, 0,
mmixer, ARRAY_SIZE(mmixer)),
SND_SOC_DAPM_OUTPUT("LOUT1"),
SND_SOC_DAPM_OUTPUT("ROUT1"),
SND_SOC_DAPM_OUTPUT("LOUT2"),
SND_SOC_DAPM_OUTPUT("ROUT2"),
SND_SOC_DAPM_OUTPUT("MONOOUT"),
SND_SOC_DAPM_OUTPUT("OUT3"),
};
static const struct snd_soc_dapm_route wm8955_dapm_routes[] = {
{ "DACL", NULL, "SYSCLK" },
{ "DACR", NULL, "SYSCLK" },
{ "Mono Input", NULL, "MONOIN-" },
{ "Mono Input", NULL, "MONOIN+" },
{ "Left", "Playback Switch", "DACL" },
{ "Left", "Right Playback Switch", "DACR" },
{ "Left", "Bypass Switch", "LINEINL" },
{ "Left", "Mono Switch", "Mono Input" },
{ "Right", "Playback Switch", "DACR" },
{ "Right", "Left Playback Switch", "DACL" },
{ "Right", "Bypass Switch", "LINEINR" },
{ "Right", "Mono Switch", "Mono Input" },
{ "Mono", "Left Playback Switch", "DACL" },
{ "Mono", "Right Playback Switch", "DACR" },
{ "Mono", "Left Bypass Switch", "LINEINL" },
{ "Mono", "Right Bypass Switch", "LINEINR" },
{ "LOUT1 PGA", NULL, "Left" },
{ "LOUT1", NULL, "TSDEN" },
{ "LOUT1", NULL, "LOUT1 PGA" },
{ "ROUT1 PGA", NULL, "Right" },
{ "ROUT1", NULL, "TSDEN" },
{ "ROUT1", NULL, "ROUT1 PGA" },
{ "LOUT2 PGA", NULL, "Left" },
{ "LOUT2", NULL, "TSDEN" },
{ "LOUT2", NULL, "LOUT2 PGA" },
{ "ROUT2 PGA", NULL, "Right" },
{ "ROUT2", NULL, "TSDEN" },
{ "ROUT2", NULL, "ROUT2 PGA" },
{ "MOUT PGA", NULL, "Mono" },
{ "MONOOUT", NULL, "MOUT PGA" },
/* OUT3 not currently implemented */
{ "OUT3", NULL, "OUT3 PGA" },
};
static int wm8955_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component);
int ret;
int wl;
switch (params_width(params)) {
case 16:
wl = 0;
break;
case 20:
wl = 0x4;
break;
case 24:
wl = 0x8;
break;
case 32:
wl = 0xc;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, WM8955_AUDIO_INTERFACE,
WM8955_WL_MASK, wl);
wm8955->fs = params_rate(params);
wm8955_set_deemph(component);
/* If the chip is clocked then disable the clocks and force a
* reconfiguration, otherwise DAPM will power up the
* clocks for us later. */
ret = snd_soc_component_read(component, WM8955_POWER_MANAGEMENT_1);
if (ret < 0)
return ret;
if (ret & WM8955_DIGENB) {
snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1,
WM8955_DIGENB, 0);
snd_soc_component_update_bits(component, WM8955_CLOCKING_PLL,
WM8955_PLL_RB | WM8955_PLLEN, 0);
wm8955_configure_clocking(component);
}
return 0;
}
static int wm8955_set_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct wm8955_priv *priv = snd_soc_component_get_drvdata(component);
int div;
switch (clk_id) {
case WM8955_CLK_MCLK:
if (freq > 15000000) {
priv->mclk_rate = freq /= 2;
div = WM8955_MCLKDIV2;
} else {
priv->mclk_rate = freq;
div = 0;
}
snd_soc_component_update_bits(component, WM8955_SAMPLE_RATE,
WM8955_MCLKDIV2, div);
break;
default:
return -EINVAL;
}
dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
return 0;
}
static int wm8955_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
u16 aif = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
break;
case SND_SOC_DAIFMT_CBM_CFM:
aif |= WM8955_MS;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_B:
aif |= WM8955_LRP;
fallthrough;
case SND_SOC_DAIFMT_DSP_A:
aif |= 0x3;
break;
case SND_SOC_DAIFMT_I2S:
aif |= 0x2;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
aif |= 0x1;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B:
/* frame inversion not valid for DSP modes */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
aif |= WM8955_BCLKINV;
break;
default:
return -EINVAL;
}
break;
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_RIGHT_J:
case SND_SOC_DAIFMT_LEFT_J:
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
aif |= WM8955_BCLKINV | WM8955_LRP;
break;
case SND_SOC_DAIFMT_IB_NF:
aif |= WM8955_BCLKINV;
break;
case SND_SOC_DAIFMT_NB_IF:
aif |= WM8955_LRP;
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, WM8955_AUDIO_INTERFACE,
WM8955_MS | WM8955_FORMAT_MASK | WM8955_BCLKINV |
WM8955_LRP, aif);
return 0;
}
static int wm8955_mute(struct snd_soc_dai *codec_dai, int mute, int direction)
{
struct snd_soc_component *component = codec_dai->component;
int val;
if (mute)
val = WM8955_DACMU;
else
val = 0;
snd_soc_component_update_bits(component, WM8955_DAC_CONTROL, WM8955_DACMU, val);
return 0;
}
static int wm8955_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component);
int ret;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
/* VMID resistance 2*50k */
snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1,
WM8955_VMIDSEL_MASK,
0x1 << WM8955_VMIDSEL_SHIFT);
/* Default bias current */
snd_soc_component_update_bits(component, WM8955_ADDITIONAL_CONTROL_1,
WM8955_VSEL_MASK,
0x2 << WM8955_VSEL_SHIFT);
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies),
wm8955->supplies);
if (ret != 0) {
dev_err(component->dev,
"Failed to enable supplies: %d\n",
ret);
return ret;
}
regcache_sync(wm8955->regmap);
/* Enable VREF and VMID */
snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1,
WM8955_VREF |
WM8955_VMIDSEL_MASK,
WM8955_VREF |
0x3 << WM8955_VREF_SHIFT);
/* Let VMID ramp */
msleep(500);
/* High resistance VROI to maintain outputs */
snd_soc_component_update_bits(component,
WM8955_ADDITIONAL_CONTROL_3,
WM8955_VROI, WM8955_VROI);
}
/* Maintain VMID with 2*250k */
snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1,
WM8955_VMIDSEL_MASK,
0x2 << WM8955_VMIDSEL_SHIFT);
/* Minimum bias current */
snd_soc_component_update_bits(component, WM8955_ADDITIONAL_CONTROL_1,
WM8955_VSEL_MASK, 0);
break;
case SND_SOC_BIAS_OFF:
/* Low resistance VROI to help discharge */
snd_soc_component_update_bits(component,
WM8955_ADDITIONAL_CONTROL_3,
WM8955_VROI, 0);
/* Turn off VMID and VREF */
snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1,
WM8955_VREF |
WM8955_VMIDSEL_MASK, 0);
regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies),
wm8955->supplies);
break;
}
return 0;
}
#define WM8955_RATES SNDRV_PCM_RATE_8000_96000
#define WM8955_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops wm8955_dai_ops = {
.set_sysclk = wm8955_set_sysclk,
.set_fmt = wm8955_set_fmt,
.hw_params = wm8955_hw_params,
.mute_stream = wm8955_mute,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver wm8955_dai = {
.name = "wm8955-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = WM8955_RATES,
.formats = WM8955_FORMATS,
},
.ops = &wm8955_dai_ops,
};
static int wm8955_probe(struct snd_soc_component *component)
{
struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component);
struct wm8955_pdata *pdata = dev_get_platdata(component->dev);
int ret, i;
for (i = 0; i < ARRAY_SIZE(wm8955->supplies); i++)
wm8955->supplies[i].supply = wm8955_supply_names[i];
ret = devm_regulator_bulk_get(component->dev, ARRAY_SIZE(wm8955->supplies),
wm8955->supplies);
if (ret != 0) {
dev_err(component->dev, "Failed to request supplies: %d\n", ret);
return ret;
}
ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies),
wm8955->supplies);
if (ret != 0) {
dev_err(component->dev, "Failed to enable supplies: %d\n", ret);
return ret;
}
ret = wm8955_reset(component);
if (ret < 0) {
dev_err(component->dev, "Failed to issue reset: %d\n", ret);
goto err_enable;
}
/* Change some default settings - latch VU and enable ZC */
snd_soc_component_update_bits(component, WM8955_LEFT_DAC_VOLUME,
WM8955_LDVU, WM8955_LDVU);
snd_soc_component_update_bits(component, WM8955_RIGHT_DAC_VOLUME,
WM8955_RDVU, WM8955_RDVU);
snd_soc_component_update_bits(component, WM8955_LOUT1_VOLUME,
WM8955_LO1VU | WM8955_LO1ZC,
WM8955_LO1VU | WM8955_LO1ZC);
snd_soc_component_update_bits(component, WM8955_ROUT1_VOLUME,
WM8955_RO1VU | WM8955_RO1ZC,
WM8955_RO1VU | WM8955_RO1ZC);
snd_soc_component_update_bits(component, WM8955_LOUT2_VOLUME,
WM8955_LO2VU | WM8955_LO2ZC,
WM8955_LO2VU | WM8955_LO2ZC);
snd_soc_component_update_bits(component, WM8955_ROUT2_VOLUME,
WM8955_RO2VU | WM8955_RO2ZC,
WM8955_RO2VU | WM8955_RO2ZC);
snd_soc_component_update_bits(component, WM8955_MONOOUT_VOLUME,
WM8955_MOZC, WM8955_MOZC);
/* Also enable adaptive bass boost by default */
snd_soc_component_update_bits(component, WM8955_BASS_CONTROL, WM8955_BB, WM8955_BB);
/* Set platform data values */
if (pdata) {
if (pdata->out2_speaker)
snd_soc_component_update_bits(component, WM8955_ADDITIONAL_CONTROL_2,
WM8955_ROUT2INV, WM8955_ROUT2INV);
if (pdata->monoin_diff)
snd_soc_component_update_bits(component, WM8955_MONO_OUT_MIX_1,
WM8955_DMEN, WM8955_DMEN);
}
snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
/* Bias level configuration will have done an extra enable */
regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
return 0;
err_enable:
regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
return ret;
}
static const struct snd_soc_component_driver soc_component_dev_wm8955 = {
.probe = wm8955_probe,
.set_bias_level = wm8955_set_bias_level,
.controls = wm8955_snd_controls,
.num_controls = ARRAY_SIZE(wm8955_snd_controls),
.dapm_widgets = wm8955_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8955_dapm_widgets),
.dapm_routes = wm8955_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(wm8955_dapm_routes),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config wm8955_regmap = {
.reg_bits = 7,
.val_bits = 9,
.max_register = WM8955_MAX_REGISTER,
.volatile_reg = wm8955_volatile,
.writeable_reg = wm8955_writeable,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = wm8955_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8955_reg_defaults),
};
static int wm8955_i2c_probe(struct i2c_client *i2c)
{
struct wm8955_priv *wm8955;
int ret;
wm8955 = devm_kzalloc(&i2c->dev, sizeof(struct wm8955_priv),
GFP_KERNEL);
if (wm8955 == NULL)
return -ENOMEM;
wm8955->regmap = devm_regmap_init_i2c(i2c, &wm8955_regmap);
if (IS_ERR(wm8955->regmap)) {
ret = PTR_ERR(wm8955->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
i2c_set_clientdata(i2c, wm8955);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_wm8955, &wm8955_dai, 1);
return ret;
}
static const struct i2c_device_id wm8955_i2c_id[] = {
{ "wm8955", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8955_i2c_id);
static struct i2c_driver wm8955_i2c_driver = {
.driver = {
.name = "wm8955",
},
.probe = wm8955_i2c_probe,
.id_table = wm8955_i2c_id,
};
module_i2c_driver(wm8955_i2c_driver);
MODULE_DESCRIPTION("ASoC WM8955 driver");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8955.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
// Copyright (c) 2017-2018, Linaro Limited
#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/device.h>
#include <linux/wait.h>
#include <linux/bitops.h>
#include <linux/regulator/consumer.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/slimbus.h>
#include <sound/soc.h>
#include <sound/pcm_params.h>
#include <sound/soc-dapm.h>
#include <linux/of_gpio.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <sound/tlv.h>
#include <sound/info.h>
#include "wcd9335.h"
#include "wcd-clsh-v2.h"
#include <dt-bindings/sound/qcom,wcd9335.h>
#define WCD9335_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
/* Fractional Rates */
#define WCD9335_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100)
#define WCD9335_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE)
/* slave port water mark level
* (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes)
*/
#define SLAVE_PORT_WATER_MARK_6BYTES 0
#define SLAVE_PORT_WATER_MARK_9BYTES 1
#define SLAVE_PORT_WATER_MARK_12BYTES 2
#define SLAVE_PORT_WATER_MARK_15BYTES 3
#define SLAVE_PORT_WATER_MARK_SHIFT 1
#define SLAVE_PORT_ENABLE 1
#define SLAVE_PORT_DISABLE 0
#define WCD9335_SLIM_WATER_MARK_VAL \
((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \
(SLAVE_PORT_ENABLE))
#define WCD9335_SLIM_NUM_PORT_REG 3
#define WCD9335_SLIM_PGD_PORT_INT_TX_EN0 (WCD9335_SLIM_PGD_PORT_INT_EN0 + 2)
#define WCD9335_MCLK_CLK_12P288MHZ 12288000
#define WCD9335_MCLK_CLK_9P6MHZ 9600000
#define WCD9335_SLIM_CLOSE_TIMEOUT 1000
#define WCD9335_SLIM_IRQ_OVERFLOW (1 << 0)
#define WCD9335_SLIM_IRQ_UNDERFLOW (1 << 1)
#define WCD9335_SLIM_IRQ_PORT_CLOSED (1 << 2)
#define WCD9335_NUM_INTERPOLATORS 9
#define WCD9335_RX_START 16
#define WCD9335_SLIM_CH_START 128
#define WCD9335_MAX_MICBIAS 4
#define WCD9335_MAX_VALID_ADC_MUX 13
#define WCD9335_INVALID_ADC_MUX 9
#define TX_HPF_CUT_OFF_FREQ_MASK 0x60
#define CF_MIN_3DB_4HZ 0x0
#define CF_MIN_3DB_75HZ 0x1
#define CF_MIN_3DB_150HZ 0x2
#define WCD9335_DMIC_CLK_DIV_2 0x0
#define WCD9335_DMIC_CLK_DIV_3 0x1
#define WCD9335_DMIC_CLK_DIV_4 0x2
#define WCD9335_DMIC_CLK_DIV_6 0x3
#define WCD9335_DMIC_CLK_DIV_8 0x4
#define WCD9335_DMIC_CLK_DIV_16 0x5
#define WCD9335_DMIC_CLK_DRIVE_DEFAULT 0x02
#define WCD9335_AMIC_PWR_LEVEL_LP 0
#define WCD9335_AMIC_PWR_LEVEL_DEFAULT 1
#define WCD9335_AMIC_PWR_LEVEL_HP 2
#define WCD9335_AMIC_PWR_LVL_MASK 0x60
#define WCD9335_AMIC_PWR_LVL_SHIFT 0x5
#define WCD9335_DEC_PWR_LVL_MASK 0x06
#define WCD9335_DEC_PWR_LVL_LP 0x02
#define WCD9335_DEC_PWR_LVL_HP 0x04
#define WCD9335_DEC_PWR_LVL_DF 0x00
#define WCD9335_SLIM_RX_CH(p) \
{.port = p + WCD9335_RX_START, .shift = p,}
#define WCD9335_SLIM_TX_CH(p) \
{.port = p, .shift = p,}
/* vout step value */
#define WCD9335_CALCULATE_VOUT_D(req_mv) (((req_mv - 650) * 10) / 25)
#define WCD9335_INTERPOLATOR_PATH(id) \
{"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"}, \
{"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"}, \
{"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"}, \
{"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"}, \
{"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"}, \
{"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"}, \
{"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"}, \
{"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"}, \
{"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"}, \
{"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"}, \
{"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"}, \
{"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"}, \
{"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"}, \
{"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"}, \
{"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"}, \
{"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"}, \
{"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"}, \
{"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"}, \
{"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"}, \
{"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"}, \
{"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"}, \
{"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"}, \
{"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"}, \
{"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"}, \
{"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \
{"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \
{"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \
{"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"}, \
{"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"}, \
{"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"}, \
{"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"}, \
{"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"}, \
{"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \
{"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \
{"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \
{"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 MUX"}, \
{"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 MIX1"}, \
{"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \
{"RX INT" #id " INTERP", NULL, "RX INT" #id " MIX2"}
#define WCD9335_ADC_MUX_PATH(id) \
{"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \
{"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \
{"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \
{"SLIM TX" #id " MUX", "DEC" #id, "ADC MUX" #id}, \
{"ADC MUX" #id, "DMIC", "DMIC MUX" #id}, \
{"ADC MUX" #id, "AMIC", "AMIC MUX" #id}, \
{"DMIC MUX" #id, "DMIC0", "DMIC0"}, \
{"DMIC MUX" #id, "DMIC1", "DMIC1"}, \
{"DMIC MUX" #id, "DMIC2", "DMIC2"}, \
{"DMIC MUX" #id, "DMIC3", "DMIC3"}, \
{"DMIC MUX" #id, "DMIC4", "DMIC4"}, \
{"DMIC MUX" #id, "DMIC5", "DMIC5"}, \
{"AMIC MUX" #id, "ADC1", "ADC1"}, \
{"AMIC MUX" #id, "ADC2", "ADC2"}, \
{"AMIC MUX" #id, "ADC3", "ADC3"}, \
{"AMIC MUX" #id, "ADC4", "ADC4"}, \
{"AMIC MUX" #id, "ADC5", "ADC5"}, \
{"AMIC MUX" #id, "ADC6", "ADC6"}
enum {
WCD9335_RX0 = 0,
WCD9335_RX1,
WCD9335_RX2,
WCD9335_RX3,
WCD9335_RX4,
WCD9335_RX5,
WCD9335_RX6,
WCD9335_RX7,
WCD9335_RX8,
WCD9335_RX9,
WCD9335_RX10,
WCD9335_RX11,
WCD9335_RX12,
WCD9335_RX_MAX,
};
enum {
WCD9335_TX0 = 0,
WCD9335_TX1,
WCD9335_TX2,
WCD9335_TX3,
WCD9335_TX4,
WCD9335_TX5,
WCD9335_TX6,
WCD9335_TX7,
WCD9335_TX8,
WCD9335_TX9,
WCD9335_TX10,
WCD9335_TX11,
WCD9335_TX12,
WCD9335_TX13,
WCD9335_TX14,
WCD9335_TX15,
WCD9335_TX_MAX,
};
enum {
SIDO_SOURCE_INTERNAL = 0,
SIDO_SOURCE_RCO_BG,
};
enum wcd9335_sido_voltage {
SIDO_VOLTAGE_SVS_MV = 950,
SIDO_VOLTAGE_NOMINAL_MV = 1100,
};
enum {
COMPANDER_1, /* HPH_L */
COMPANDER_2, /* HPH_R */
COMPANDER_3, /* LO1_DIFF */
COMPANDER_4, /* LO2_DIFF */
COMPANDER_5, /* LO3_SE */
COMPANDER_6, /* LO4_SE */
COMPANDER_7, /* SWR SPK CH1 */
COMPANDER_8, /* SWR SPK CH2 */
COMPANDER_MAX,
};
enum {
INTn_2_INP_SEL_ZERO = 0,
INTn_2_INP_SEL_RX0,
INTn_2_INP_SEL_RX1,
INTn_2_INP_SEL_RX2,
INTn_2_INP_SEL_RX3,
INTn_2_INP_SEL_RX4,
INTn_2_INP_SEL_RX5,
INTn_2_INP_SEL_RX6,
INTn_2_INP_SEL_RX7,
INTn_2_INP_SEL_PROXIMITY,
};
enum {
INTn_1_MIX_INP_SEL_ZERO = 0,
INTn_1_MIX_INP_SEL_DEC0,
INTn_1_MIX_INP_SEL_DEC1,
INTn_1_MIX_INP_SEL_IIR0,
INTn_1_MIX_INP_SEL_IIR1,
INTn_1_MIX_INP_SEL_RX0,
INTn_1_MIX_INP_SEL_RX1,
INTn_1_MIX_INP_SEL_RX2,
INTn_1_MIX_INP_SEL_RX3,
INTn_1_MIX_INP_SEL_RX4,
INTn_1_MIX_INP_SEL_RX5,
INTn_1_MIX_INP_SEL_RX6,
INTn_1_MIX_INP_SEL_RX7,
};
enum {
INTERP_EAR = 0,
INTERP_HPHL,
INTERP_HPHR,
INTERP_LO1,
INTERP_LO2,
INTERP_LO3,
INTERP_LO4,
INTERP_SPKR1,
INTERP_SPKR2,
};
enum wcd_clock_type {
WCD_CLK_OFF,
WCD_CLK_RCO,
WCD_CLK_MCLK,
};
enum {
MIC_BIAS_1 = 1,
MIC_BIAS_2,
MIC_BIAS_3,
MIC_BIAS_4
};
enum {
MICB_PULLUP_ENABLE,
MICB_PULLUP_DISABLE,
MICB_ENABLE,
MICB_DISABLE,
};
struct wcd9335_slim_ch {
u32 ch_num;
u16 port;
u16 shift;
struct list_head list;
};
struct wcd_slim_codec_dai_data {
struct list_head slim_ch_list;
struct slim_stream_config sconfig;
struct slim_stream_runtime *sruntime;
};
struct wcd9335_codec {
struct device *dev;
struct clk *mclk;
struct clk *native_clk;
u32 mclk_rate;
u8 version;
struct slim_device *slim;
struct slim_device *slim_ifc_dev;
struct regmap *regmap;
struct regmap *if_regmap;
struct regmap_irq_chip_data *irq_data;
struct wcd9335_slim_ch rx_chs[WCD9335_RX_MAX];
struct wcd9335_slim_ch tx_chs[WCD9335_TX_MAX];
u32 num_rx_port;
u32 num_tx_port;
int sido_input_src;
enum wcd9335_sido_voltage sido_voltage;
struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS];
struct snd_soc_component *component;
int master_bias_users;
int clk_mclk_users;
int clk_rco_users;
int sido_ccl_cnt;
enum wcd_clock_type clk_type;
struct wcd_clsh_ctrl *clsh_ctrl;
u32 hph_mode;
int prim_int_users[WCD9335_NUM_INTERPOLATORS];
int comp_enabled[COMPANDER_MAX];
int intr1;
int reset_gpio;
struct regulator_bulk_data supplies[WCD9335_MAX_SUPPLY];
unsigned int rx_port_value[WCD9335_RX_MAX];
unsigned int tx_port_value[WCD9335_TX_MAX];
int hph_l_gain;
int hph_r_gain;
u32 rx_bias_count;
/*TX*/
int micb_ref[WCD9335_MAX_MICBIAS];
int pullup_ref[WCD9335_MAX_MICBIAS];
int dmic_0_1_clk_cnt;
int dmic_2_3_clk_cnt;
int dmic_4_5_clk_cnt;
int dmic_sample_rate;
int mad_dmic_sample_rate;
int native_clk_users;
};
struct wcd9335_irq {
int irq;
irqreturn_t (*handler)(int irq, void *data);
char *name;
};
static const struct wcd9335_slim_ch wcd9335_tx_chs[WCD9335_TX_MAX] = {
WCD9335_SLIM_TX_CH(0),
WCD9335_SLIM_TX_CH(1),
WCD9335_SLIM_TX_CH(2),
WCD9335_SLIM_TX_CH(3),
WCD9335_SLIM_TX_CH(4),
WCD9335_SLIM_TX_CH(5),
WCD9335_SLIM_TX_CH(6),
WCD9335_SLIM_TX_CH(7),
WCD9335_SLIM_TX_CH(8),
WCD9335_SLIM_TX_CH(9),
WCD9335_SLIM_TX_CH(10),
WCD9335_SLIM_TX_CH(11),
WCD9335_SLIM_TX_CH(12),
WCD9335_SLIM_TX_CH(13),
WCD9335_SLIM_TX_CH(14),
WCD9335_SLIM_TX_CH(15),
};
static const struct wcd9335_slim_ch wcd9335_rx_chs[WCD9335_RX_MAX] = {
WCD9335_SLIM_RX_CH(0), /* 16 */
WCD9335_SLIM_RX_CH(1), /* 17 */
WCD9335_SLIM_RX_CH(2),
WCD9335_SLIM_RX_CH(3),
WCD9335_SLIM_RX_CH(4),
WCD9335_SLIM_RX_CH(5),
WCD9335_SLIM_RX_CH(6),
WCD9335_SLIM_RX_CH(7),
WCD9335_SLIM_RX_CH(8),
WCD9335_SLIM_RX_CH(9),
WCD9335_SLIM_RX_CH(10),
WCD9335_SLIM_RX_CH(11),
WCD9335_SLIM_RX_CH(12),
};
struct interp_sample_rate {
int rate;
int rate_val;
};
static struct interp_sample_rate int_mix_rate_val[] = {
{48000, 0x4}, /* 48K */
{96000, 0x5}, /* 96K */
{192000, 0x6}, /* 192K */
};
static struct interp_sample_rate int_prim_rate_val[] = {
{8000, 0x0}, /* 8K */
{16000, 0x1}, /* 16K */
{24000, -EINVAL},/* 24K */
{32000, 0x3}, /* 32K */
{48000, 0x4}, /* 48K */
{96000, 0x5}, /* 96K */
{192000, 0x6}, /* 192K */
{384000, 0x7}, /* 384K */
{44100, 0x8}, /* 44.1K */
};
struct wcd9335_reg_mask_val {
u16 reg;
u8 mask;
u8 val;
};
static const struct wcd9335_reg_mask_val wcd9335_codec_reg_init[] = {
/* Rbuckfly/R_EAR(32) */
{WCD9335_CDC_CLSH_K2_MSB, 0x0F, 0x00},
{WCD9335_CDC_CLSH_K2_LSB, 0xFF, 0x60},
{WCD9335_CPE_SS_DMIC_CFG, 0x80, 0x00},
{WCD9335_CDC_BOOST0_BOOST_CTL, 0x70, 0x50},
{WCD9335_CDC_BOOST1_BOOST_CTL, 0x70, 0x50},
{WCD9335_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08},
{WCD9335_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08},
{WCD9335_ANA_LO_1_2, 0x3C, 0X3C},
{WCD9335_DIFF_LO_COM_SWCAP_REFBUF_FREQ, 0x70, 0x00},
{WCD9335_DIFF_LO_COM_PA_FREQ, 0x70, 0x40},
{WCD9335_SOC_MAD_AUDIO_CTL_2, 0x03, 0x03},
{WCD9335_CDC_TOP_TOP_CFG1, 0x02, 0x02},
{WCD9335_CDC_TOP_TOP_CFG1, 0x01, 0x01},
{WCD9335_EAR_CMBUFF, 0x08, 0x00},
{WCD9335_CDC_TX9_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
{WCD9335_CDC_TX10_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
{WCD9335_CDC_TX11_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
{WCD9335_CDC_TX12_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
{WCD9335_CDC_COMPANDER7_CTL3, 0x80, 0x80},
{WCD9335_CDC_COMPANDER8_CTL3, 0x80, 0x80},
{WCD9335_CDC_COMPANDER7_CTL7, 0x01, 0x01},
{WCD9335_CDC_COMPANDER8_CTL7, 0x01, 0x01},
{WCD9335_CDC_RX0_RX_PATH_CFG0, 0x01, 0x01},
{WCD9335_CDC_RX1_RX_PATH_CFG0, 0x01, 0x01},
{WCD9335_CDC_RX2_RX_PATH_CFG0, 0x01, 0x01},
{WCD9335_CDC_RX3_RX_PATH_CFG0, 0x01, 0x01},
{WCD9335_CDC_RX4_RX_PATH_CFG0, 0x01, 0x01},
{WCD9335_CDC_RX5_RX_PATH_CFG0, 0x01, 0x01},
{WCD9335_CDC_RX6_RX_PATH_CFG0, 0x01, 0x01},
{WCD9335_CDC_RX7_RX_PATH_CFG0, 0x01, 0x01},
{WCD9335_CDC_RX8_RX_PATH_CFG0, 0x01, 0x01},
{WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 0x01, 0x01},
{WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 0x01, 0x01},
{WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 0x01, 0x01},
{WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 0x01, 0x01},
{WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 0x01, 0x01},
{WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 0x01, 0x01},
{WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 0x01, 0x01},
{WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 0x01, 0x01},
{WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 0x01, 0x01},
{WCD9335_VBADC_IBIAS_FE, 0x0C, 0x08},
{WCD9335_RCO_CTRL_2, 0x0F, 0x08},
{WCD9335_RX_BIAS_FLYB_MID_RST, 0xF0, 0x10},
{WCD9335_FLYBACK_CTRL_1, 0x20, 0x20},
{WCD9335_HPH_OCP_CTL, 0xFF, 0x5A},
{WCD9335_HPH_L_TEST, 0x01, 0x01},
{WCD9335_HPH_R_TEST, 0x01, 0x01},
{WCD9335_CDC_BOOST0_BOOST_CFG1, 0x3F, 0x12},
{WCD9335_CDC_BOOST0_BOOST_CFG2, 0x1C, 0x08},
{WCD9335_CDC_COMPANDER7_CTL7, 0x1E, 0x18},
{WCD9335_CDC_BOOST1_BOOST_CFG1, 0x3F, 0x12},
{WCD9335_CDC_BOOST1_BOOST_CFG2, 0x1C, 0x08},
{WCD9335_CDC_COMPANDER8_CTL7, 0x1E, 0x18},
{WCD9335_CDC_TX0_TX_PATH_SEC7, 0xFF, 0x45},
{WCD9335_CDC_RX0_RX_PATH_SEC0, 0xFC, 0xF4},
{WCD9335_HPH_REFBUFF_LP_CTL, 0x08, 0x08},
{WCD9335_HPH_REFBUFF_LP_CTL, 0x06, 0x02},
};
/* Cutoff frequency for high pass filter */
static const char * const cf_text[] = {
"CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ"
};
static const char * const rx_cf_text[] = {
"CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ",
"CF_NEG_3DB_0P48HZ"
};
static const char * const rx_int0_7_mix_mux_text[] = {
"ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
"RX6", "RX7", "PROXIMITY"
};
static const char * const rx_int_mix_mux_text[] = {
"ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
"RX6", "RX7"
};
static const char * const rx_prim_mix_text[] = {
"ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2",
"RX3", "RX4", "RX5", "RX6", "RX7"
};
static const char * const rx_int_dem_inp_mux_text[] = {
"NORMAL_DSM_OUT", "CLSH_DSM_OUT",
};
static const char * const rx_int0_interp_mux_text[] = {
"ZERO", "RX INT0 MIX2",
};
static const char * const rx_int1_interp_mux_text[] = {
"ZERO", "RX INT1 MIX2",
};
static const char * const rx_int2_interp_mux_text[] = {
"ZERO", "RX INT2 MIX2",
};
static const char * const rx_int3_interp_mux_text[] = {
"ZERO", "RX INT3 MIX2",
};
static const char * const rx_int4_interp_mux_text[] = {
"ZERO", "RX INT4 MIX2",
};
static const char * const rx_int5_interp_mux_text[] = {
"ZERO", "RX INT5 MIX2",
};
static const char * const rx_int6_interp_mux_text[] = {
"ZERO", "RX INT6 MIX2",
};
static const char * const rx_int7_interp_mux_text[] = {
"ZERO", "RX INT7 MIX2",
};
static const char * const rx_int8_interp_mux_text[] = {
"ZERO", "RX INT8 SEC MIX"
};
static const char * const rx_hph_mode_mux_text[] = {
"Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB",
"Class-H Hi-Fi Low Power"
};
static const char *const slim_rx_mux_text[] = {
"ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB",
};
static const char * const adc_mux_text[] = {
"DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2"
};
static const char * const dmic_mux_text[] = {
"ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5",
"SMIC0", "SMIC1", "SMIC2", "SMIC3"
};
static const char * const dmic_mux_alt_text[] = {
"ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5",
};
static const char * const amic_mux_text[] = {
"ZERO", "ADC1", "ADC2", "ADC3", "ADC4", "ADC5", "ADC6"
};
static const char * const sb_tx0_mux_text[] = {
"ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192"
};
static const char * const sb_tx1_mux_text[] = {
"ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192"
};
static const char * const sb_tx2_mux_text[] = {
"ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192"
};
static const char * const sb_tx3_mux_text[] = {
"ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192"
};
static const char * const sb_tx4_mux_text[] = {
"ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192"
};
static const char * const sb_tx5_mux_text[] = {
"ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192"
};
static const char * const sb_tx6_mux_text[] = {
"ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192"
};
static const char * const sb_tx7_mux_text[] = {
"ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192"
};
static const char * const sb_tx8_mux_text[] = {
"ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192"
};
static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0);
static const struct soc_enum cf_dec0_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text);
static const struct soc_enum cf_dec1_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text);
static const struct soc_enum cf_dec2_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text);
static const struct soc_enum cf_dec3_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text);
static const struct soc_enum cf_dec4_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text);
static const struct soc_enum cf_dec5_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text);
static const struct soc_enum cf_dec6_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text);
static const struct soc_enum cf_dec7_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text);
static const struct soc_enum cf_dec8_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text);
static const struct soc_enum cf_int0_1_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text);
static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 2,
rx_cf_text);
static const struct soc_enum cf_int1_1_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text);
static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 2,
rx_cf_text);
static const struct soc_enum cf_int2_1_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text);
static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 2,
rx_cf_text);
static const struct soc_enum cf_int3_1_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text);
static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 2,
rx_cf_text);
static const struct soc_enum cf_int4_1_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text);
static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 2,
rx_cf_text);
static const struct soc_enum cf_int5_1_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CFG2, 0, 4, rx_cf_text);
static SOC_ENUM_SINGLE_DECL(cf_int5_2_enum, WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 2,
rx_cf_text);
static const struct soc_enum cf_int6_1_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CFG2, 0, 4, rx_cf_text);
static SOC_ENUM_SINGLE_DECL(cf_int6_2_enum, WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 2,
rx_cf_text);
static const struct soc_enum cf_int7_1_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text);
static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 2,
rx_cf_text);
static const struct soc_enum cf_int8_1_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text);
static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 2,
rx_cf_text);
static const struct soc_enum rx_hph_mode_mux_enum =
SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
rx_hph_mode_mux_text);
static const struct soc_enum slim_rx_mux_enum =
SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text);
static const struct soc_enum rx_int0_2_mux_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10,
rx_int0_7_mix_mux_text);
static const struct soc_enum rx_int1_2_mux_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9,
rx_int_mix_mux_text);
static const struct soc_enum rx_int2_2_mux_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9,
rx_int_mix_mux_text);
static const struct soc_enum rx_int3_2_mux_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9,
rx_int_mix_mux_text);
static const struct soc_enum rx_int4_2_mux_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9,
rx_int_mix_mux_text);
static const struct soc_enum rx_int5_2_mux_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 0, 9,
rx_int_mix_mux_text);
static const struct soc_enum rx_int6_2_mux_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 0, 9,
rx_int_mix_mux_text);
static const struct soc_enum rx_int7_2_mux_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10,
rx_int0_7_mix_mux_text);
static const struct soc_enum rx_int8_2_mux_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9,
rx_int_mix_mux_text);
static const struct soc_enum rx_int0_1_mix_inp0_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int0_1_mix_inp1_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int0_1_mix_inp2_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int1_1_mix_inp0_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int1_1_mix_inp1_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int1_1_mix_inp2_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int2_1_mix_inp0_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int2_1_mix_inp1_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int2_1_mix_inp2_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int3_1_mix_inp0_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int3_1_mix_inp1_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int3_1_mix_inp2_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int4_1_mix_inp0_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int4_1_mix_inp1_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int4_1_mix_inp2_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int5_1_mix_inp0_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 0, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int5_1_mix_inp1_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int5_1_mix_inp2_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int6_1_mix_inp0_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 0, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int6_1_mix_inp1_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int6_1_mix_inp2_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int7_1_mix_inp0_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int7_1_mix_inp1_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int7_1_mix_inp2_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int8_1_mix_inp0_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int8_1_mix_inp1_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int8_1_mix_inp2_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int0_dem_inp_mux_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_SEC0, 0,
ARRAY_SIZE(rx_int_dem_inp_mux_text),
rx_int_dem_inp_mux_text);
static const struct soc_enum rx_int1_dem_inp_mux_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_SEC0, 0,
ARRAY_SIZE(rx_int_dem_inp_mux_text),
rx_int_dem_inp_mux_text);
static const struct soc_enum rx_int2_dem_inp_mux_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_SEC0, 0,
ARRAY_SIZE(rx_int_dem_inp_mux_text),
rx_int_dem_inp_mux_text);
static const struct soc_enum rx_int0_interp_mux_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CTL, 5, 2,
rx_int0_interp_mux_text);
static const struct soc_enum rx_int1_interp_mux_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CTL, 5, 2,
rx_int1_interp_mux_text);
static const struct soc_enum rx_int2_interp_mux_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CTL, 5, 2,
rx_int2_interp_mux_text);
static const struct soc_enum rx_int3_interp_mux_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CTL, 5, 2,
rx_int3_interp_mux_text);
static const struct soc_enum rx_int4_interp_mux_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CTL, 5, 2,
rx_int4_interp_mux_text);
static const struct soc_enum rx_int5_interp_mux_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CTL, 5, 2,
rx_int5_interp_mux_text);
static const struct soc_enum rx_int6_interp_mux_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CTL, 5, 2,
rx_int6_interp_mux_text);
static const struct soc_enum rx_int7_interp_mux_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CTL, 5, 2,
rx_int7_interp_mux_text);
static const struct soc_enum rx_int8_interp_mux_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CTL, 5, 2,
rx_int8_interp_mux_text);
static const struct soc_enum tx_adc_mux0_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0, 4,
adc_mux_text);
static const struct soc_enum tx_adc_mux1_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0, 4,
adc_mux_text);
static const struct soc_enum tx_adc_mux2_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0, 4,
adc_mux_text);
static const struct soc_enum tx_adc_mux3_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0, 4,
adc_mux_text);
static const struct soc_enum tx_adc_mux4_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 6, 4,
adc_mux_text);
static const struct soc_enum tx_adc_mux5_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 6, 4,
adc_mux_text);
static const struct soc_enum tx_adc_mux6_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 6, 4,
adc_mux_text);
static const struct soc_enum tx_adc_mux7_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 6, 4,
adc_mux_text);
static const struct soc_enum tx_adc_mux8_chain_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 6, 4,
adc_mux_text);
static const struct soc_enum tx_dmic_mux0_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 11,
dmic_mux_text);
static const struct soc_enum tx_dmic_mux1_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 11,
dmic_mux_text);
static const struct soc_enum tx_dmic_mux2_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 11,
dmic_mux_text);
static const struct soc_enum tx_dmic_mux3_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 11,
dmic_mux_text);
static const struct soc_enum tx_dmic_mux4_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7,
dmic_mux_alt_text);
static const struct soc_enum tx_dmic_mux5_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7,
dmic_mux_alt_text);
static const struct soc_enum tx_dmic_mux6_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7,
dmic_mux_alt_text);
static const struct soc_enum tx_dmic_mux7_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7,
dmic_mux_alt_text);
static const struct soc_enum tx_dmic_mux8_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7,
dmic_mux_alt_text);
static const struct soc_enum tx_amic_mux0_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 7,
amic_mux_text);
static const struct soc_enum tx_amic_mux1_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 7,
amic_mux_text);
static const struct soc_enum tx_amic_mux2_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 7,
amic_mux_text);
static const struct soc_enum tx_amic_mux3_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 7,
amic_mux_text);
static const struct soc_enum tx_amic_mux4_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 7,
amic_mux_text);
static const struct soc_enum tx_amic_mux5_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 7,
amic_mux_text);
static const struct soc_enum tx_amic_mux6_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 7,
amic_mux_text);
static const struct soc_enum tx_amic_mux7_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 7,
amic_mux_text);
static const struct soc_enum tx_amic_mux8_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 7,
amic_mux_text);
static const struct soc_enum sb_tx0_mux_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 0, 4,
sb_tx0_mux_text);
static const struct soc_enum sb_tx1_mux_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 2, 4,
sb_tx1_mux_text);
static const struct soc_enum sb_tx2_mux_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 4, 4,
sb_tx2_mux_text);
static const struct soc_enum sb_tx3_mux_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 6, 4,
sb_tx3_mux_text);
static const struct soc_enum sb_tx4_mux_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 0, 4,
sb_tx4_mux_text);
static const struct soc_enum sb_tx5_mux_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 2, 4,
sb_tx5_mux_text);
static const struct soc_enum sb_tx6_mux_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 4, 4,
sb_tx6_mux_text);
static const struct soc_enum sb_tx7_mux_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 6, 4,
sb_tx7_mux_text);
static const struct soc_enum sb_tx8_mux_enum =
SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2, 0, 4,
sb_tx8_mux_text);
static const struct snd_kcontrol_new rx_int0_2_mux =
SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum);
static const struct snd_kcontrol_new rx_int1_2_mux =
SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum);
static const struct snd_kcontrol_new rx_int2_2_mux =
SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum);
static const struct snd_kcontrol_new rx_int3_2_mux =
SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum);
static const struct snd_kcontrol_new rx_int4_2_mux =
SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum);
static const struct snd_kcontrol_new rx_int5_2_mux =
SOC_DAPM_ENUM("RX INT5_2 MUX Mux", rx_int5_2_mux_chain_enum);
static const struct snd_kcontrol_new rx_int6_2_mux =
SOC_DAPM_ENUM("RX INT6_2 MUX Mux", rx_int6_2_mux_chain_enum);
static const struct snd_kcontrol_new rx_int7_2_mux =
SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum);
static const struct snd_kcontrol_new rx_int8_2_mux =
SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum);
static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux =
SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum);
static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux =
SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum);
static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux =
SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum);
static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux =
SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum);
static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux =
SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum);
static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux =
SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum);
static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux =
SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum);
static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux =
SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum);
static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux =
SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum);
static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux =
SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum);
static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux =
SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum);
static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux =
SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum);
static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux =
SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum);
static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux =
SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum);
static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux =
SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum);
static const struct snd_kcontrol_new rx_int5_1_mix_inp0_mux =
SOC_DAPM_ENUM("RX INT5_1 MIX1 INP0 Mux", rx_int5_1_mix_inp0_chain_enum);
static const struct snd_kcontrol_new rx_int5_1_mix_inp1_mux =
SOC_DAPM_ENUM("RX INT5_1 MIX1 INP1 Mux", rx_int5_1_mix_inp1_chain_enum);
static const struct snd_kcontrol_new rx_int5_1_mix_inp2_mux =
SOC_DAPM_ENUM("RX INT5_1 MIX1 INP2 Mux", rx_int5_1_mix_inp2_chain_enum);
static const struct snd_kcontrol_new rx_int6_1_mix_inp0_mux =
SOC_DAPM_ENUM("RX INT6_1 MIX1 INP0 Mux", rx_int6_1_mix_inp0_chain_enum);
static const struct snd_kcontrol_new rx_int6_1_mix_inp1_mux =
SOC_DAPM_ENUM("RX INT6_1 MIX1 INP1 Mux", rx_int6_1_mix_inp1_chain_enum);
static const struct snd_kcontrol_new rx_int6_1_mix_inp2_mux =
SOC_DAPM_ENUM("RX INT6_1 MIX1 INP2 Mux", rx_int6_1_mix_inp2_chain_enum);
static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux =
SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum);
static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux =
SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum);
static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux =
SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum);
static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux =
SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum);
static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux =
SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum);
static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux =
SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum);
static const struct snd_kcontrol_new rx_int0_interp_mux =
SOC_DAPM_ENUM("RX INT0 INTERP Mux", rx_int0_interp_mux_enum);
static const struct snd_kcontrol_new rx_int1_interp_mux =
SOC_DAPM_ENUM("RX INT1 INTERP Mux", rx_int1_interp_mux_enum);
static const struct snd_kcontrol_new rx_int2_interp_mux =
SOC_DAPM_ENUM("RX INT2 INTERP Mux", rx_int2_interp_mux_enum);
static const struct snd_kcontrol_new rx_int3_interp_mux =
SOC_DAPM_ENUM("RX INT3 INTERP Mux", rx_int3_interp_mux_enum);
static const struct snd_kcontrol_new rx_int4_interp_mux =
SOC_DAPM_ENUM("RX INT4 INTERP Mux", rx_int4_interp_mux_enum);
static const struct snd_kcontrol_new rx_int5_interp_mux =
SOC_DAPM_ENUM("RX INT5 INTERP Mux", rx_int5_interp_mux_enum);
static const struct snd_kcontrol_new rx_int6_interp_mux =
SOC_DAPM_ENUM("RX INT6 INTERP Mux", rx_int6_interp_mux_enum);
static const struct snd_kcontrol_new rx_int7_interp_mux =
SOC_DAPM_ENUM("RX INT7 INTERP Mux", rx_int7_interp_mux_enum);
static const struct snd_kcontrol_new rx_int8_interp_mux =
SOC_DAPM_ENUM("RX INT8 INTERP Mux", rx_int8_interp_mux_enum);
static const struct snd_kcontrol_new tx_dmic_mux0 =
SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum);
static const struct snd_kcontrol_new tx_dmic_mux1 =
SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum);
static const struct snd_kcontrol_new tx_dmic_mux2 =
SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum);
static const struct snd_kcontrol_new tx_dmic_mux3 =
SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum);
static const struct snd_kcontrol_new tx_dmic_mux4 =
SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum);
static const struct snd_kcontrol_new tx_dmic_mux5 =
SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum);
static const struct snd_kcontrol_new tx_dmic_mux6 =
SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum);
static const struct snd_kcontrol_new tx_dmic_mux7 =
SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum);
static const struct snd_kcontrol_new tx_dmic_mux8 =
SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum);
static const struct snd_kcontrol_new tx_amic_mux0 =
SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum);
static const struct snd_kcontrol_new tx_amic_mux1 =
SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum);
static const struct snd_kcontrol_new tx_amic_mux2 =
SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum);
static const struct snd_kcontrol_new tx_amic_mux3 =
SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum);
static const struct snd_kcontrol_new tx_amic_mux4 =
SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum);
static const struct snd_kcontrol_new tx_amic_mux5 =
SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum);
static const struct snd_kcontrol_new tx_amic_mux6 =
SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum);
static const struct snd_kcontrol_new tx_amic_mux7 =
SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum);
static const struct snd_kcontrol_new tx_amic_mux8 =
SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum);
static const struct snd_kcontrol_new sb_tx0_mux =
SOC_DAPM_ENUM("SLIM TX0 MUX Mux", sb_tx0_mux_enum);
static const struct snd_kcontrol_new sb_tx1_mux =
SOC_DAPM_ENUM("SLIM TX1 MUX Mux", sb_tx1_mux_enum);
static const struct snd_kcontrol_new sb_tx2_mux =
SOC_DAPM_ENUM("SLIM TX2 MUX Mux", sb_tx2_mux_enum);
static const struct snd_kcontrol_new sb_tx3_mux =
SOC_DAPM_ENUM("SLIM TX3 MUX Mux", sb_tx3_mux_enum);
static const struct snd_kcontrol_new sb_tx4_mux =
SOC_DAPM_ENUM("SLIM TX4 MUX Mux", sb_tx4_mux_enum);
static const struct snd_kcontrol_new sb_tx5_mux =
SOC_DAPM_ENUM("SLIM TX5 MUX Mux", sb_tx5_mux_enum);
static const struct snd_kcontrol_new sb_tx6_mux =
SOC_DAPM_ENUM("SLIM TX6 MUX Mux", sb_tx6_mux_enum);
static const struct snd_kcontrol_new sb_tx7_mux =
SOC_DAPM_ENUM("SLIM TX7 MUX Mux", sb_tx7_mux_enum);
static const struct snd_kcontrol_new sb_tx8_mux =
SOC_DAPM_ENUM("SLIM TX8 MUX Mux", sb_tx8_mux_enum);
static int slim_rx_mux_get(struct snd_kcontrol *kc,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
struct wcd9335_codec *wcd = dev_get_drvdata(w->dapm->dev);
u32 port_id = w->shift;
ucontrol->value.enumerated.item[0] = wcd->rx_port_value[port_id];
return 0;
}
static int slim_rx_mux_put(struct snd_kcontrol *kc,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
struct wcd9335_codec *wcd = dev_get_drvdata(w->dapm->dev);
struct soc_enum *e = (struct soc_enum *)kc->private_value;
struct snd_soc_dapm_update *update = NULL;
u32 port_id = w->shift;
if (wcd->rx_port_value[port_id] == ucontrol->value.enumerated.item[0])
return 0;
wcd->rx_port_value[port_id] = ucontrol->value.enumerated.item[0];
/* Remove channel from any list it's in before adding it to a new one */
list_del_init(&wcd->rx_chs[port_id].list);
switch (wcd->rx_port_value[port_id]) {
case 0:
/* Channel already removed from lists. Nothing to do here */
break;
case 1:
list_add_tail(&wcd->rx_chs[port_id].list,
&wcd->dai[AIF1_PB].slim_ch_list);
break;
case 2:
list_add_tail(&wcd->rx_chs[port_id].list,
&wcd->dai[AIF2_PB].slim_ch_list);
break;
case 3:
list_add_tail(&wcd->rx_chs[port_id].list,
&wcd->dai[AIF3_PB].slim_ch_list);
break;
case 4:
list_add_tail(&wcd->rx_chs[port_id].list,
&wcd->dai[AIF4_PB].slim_ch_list);
break;
default:
dev_err(wcd->dev, "Unknown AIF %d\n", wcd->rx_port_value[port_id]);
goto err;
}
snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value[port_id],
e, update);
return 0;
err:
return -EINVAL;
}
static int slim_tx_mixer_get(struct snd_kcontrol *kc,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
struct wcd9335_codec *wcd = dev_get_drvdata(dapm->dev);
struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc);
struct soc_mixer_control *mixer =
(struct soc_mixer_control *)kc->private_value;
int dai_id = widget->shift;
int port_id = mixer->shift;
ucontrol->value.integer.value[0] = wcd->tx_port_value[port_id] == dai_id;
return 0;
}
static int slim_tx_mixer_put(struct snd_kcontrol *kc,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc);
struct wcd9335_codec *wcd = dev_get_drvdata(widget->dapm->dev);
struct snd_soc_dapm_update *update = NULL;
struct soc_mixer_control *mixer =
(struct soc_mixer_control *)kc->private_value;
int enable = ucontrol->value.integer.value[0];
int dai_id = widget->shift;
int port_id = mixer->shift;
switch (dai_id) {
case AIF1_CAP:
case AIF2_CAP:
case AIF3_CAP:
/* only add to the list if value not set */
if (enable && wcd->tx_port_value[port_id] != dai_id) {
wcd->tx_port_value[port_id] = dai_id;
list_add_tail(&wcd->tx_chs[port_id].list,
&wcd->dai[dai_id].slim_ch_list);
} else if (!enable && wcd->tx_port_value[port_id] == dai_id) {
wcd->tx_port_value[port_id] = -1;
list_del_init(&wcd->tx_chs[port_id].list);
}
break;
default:
dev_err(wcd->dev, "Unknown AIF %d\n", dai_id);
return -EINVAL;
}
snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update);
return 0;
}
static const struct snd_kcontrol_new slim_rx_mux[WCD9335_RX_MAX] = {
SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum,
slim_rx_mux_get, slim_rx_mux_put),
SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum,
slim_rx_mux_get, slim_rx_mux_put),
SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum,
slim_rx_mux_get, slim_rx_mux_put),
SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum,
slim_rx_mux_get, slim_rx_mux_put),
SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum,
slim_rx_mux_get, slim_rx_mux_put),
SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum,
slim_rx_mux_get, slim_rx_mux_put),
SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum,
slim_rx_mux_get, slim_rx_mux_put),
SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum,
slim_rx_mux_get, slim_rx_mux_put),
};
static const struct snd_kcontrol_new aif1_cap_mixer[] = {
SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
};
static const struct snd_kcontrol_new aif2_cap_mixer[] = {
SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
};
static const struct snd_kcontrol_new aif3_cap_mixer[] = {
SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
};
static int wcd9335_put_dec_enum(struct snd_kcontrol *kc,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
struct soc_enum *e = (struct soc_enum *)kc->private_value;
unsigned int val, reg, sel;
val = ucontrol->value.enumerated.item[0];
switch (e->reg) {
case WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1:
reg = WCD9335_CDC_TX0_TX_PATH_CFG0;
break;
case WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1:
reg = WCD9335_CDC_TX1_TX_PATH_CFG0;
break;
case WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1:
reg = WCD9335_CDC_TX2_TX_PATH_CFG0;
break;
case WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1:
reg = WCD9335_CDC_TX3_TX_PATH_CFG0;
break;
case WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0:
reg = WCD9335_CDC_TX4_TX_PATH_CFG0;
break;
case WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0:
reg = WCD9335_CDC_TX5_TX_PATH_CFG0;
break;
case WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0:
reg = WCD9335_CDC_TX6_TX_PATH_CFG0;
break;
case WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0:
reg = WCD9335_CDC_TX7_TX_PATH_CFG0;
break;
case WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0:
reg = WCD9335_CDC_TX8_TX_PATH_CFG0;
break;
default:
return -EINVAL;
}
/* AMIC: 0, DMIC: 1 */
sel = val ? WCD9335_CDC_TX_ADC_AMIC_SEL : WCD9335_CDC_TX_ADC_DMIC_SEL;
snd_soc_component_update_bits(component, reg,
WCD9335_CDC_TX_ADC_AMIC_DMIC_SEL_MASK,
sel);
return snd_soc_dapm_put_enum_double(kc, ucontrol);
}
static int wcd9335_int_dem_inp_mux_put(struct snd_kcontrol *kc,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_enum *e = (struct soc_enum *)kc->private_value;
struct snd_soc_component *component;
int reg, val;
component = snd_soc_dapm_kcontrol_component(kc);
val = ucontrol->value.enumerated.item[0];
if (e->reg == WCD9335_CDC_RX0_RX_PATH_SEC0)
reg = WCD9335_CDC_RX0_RX_PATH_CFG0;
else if (e->reg == WCD9335_CDC_RX1_RX_PATH_SEC0)
reg = WCD9335_CDC_RX1_RX_PATH_CFG0;
else if (e->reg == WCD9335_CDC_RX2_RX_PATH_SEC0)
reg = WCD9335_CDC_RX2_RX_PATH_CFG0;
else
return -EINVAL;
/* Set Look Ahead Delay */
snd_soc_component_update_bits(component, reg,
WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN_MASK,
val ? WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN : 0);
/* Set DEM INP Select */
return snd_soc_dapm_put_enum_double(kc, ucontrol);
}
static const struct snd_kcontrol_new rx_int0_dem_inp_mux =
SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum,
snd_soc_dapm_get_enum_double,
wcd9335_int_dem_inp_mux_put);
static const struct snd_kcontrol_new rx_int1_dem_inp_mux =
SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum,
snd_soc_dapm_get_enum_double,
wcd9335_int_dem_inp_mux_put);
static const struct snd_kcontrol_new rx_int2_dem_inp_mux =
SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum,
snd_soc_dapm_get_enum_double,
wcd9335_int_dem_inp_mux_put);
static const struct snd_kcontrol_new tx_adc_mux0 =
SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_chain_enum,
snd_soc_dapm_get_enum_double,
wcd9335_put_dec_enum);
static const struct snd_kcontrol_new tx_adc_mux1 =
SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_chain_enum,
snd_soc_dapm_get_enum_double,
wcd9335_put_dec_enum);
static const struct snd_kcontrol_new tx_adc_mux2 =
SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_chain_enum,
snd_soc_dapm_get_enum_double,
wcd9335_put_dec_enum);
static const struct snd_kcontrol_new tx_adc_mux3 =
SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_chain_enum,
snd_soc_dapm_get_enum_double,
wcd9335_put_dec_enum);
static const struct snd_kcontrol_new tx_adc_mux4 =
SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_chain_enum,
snd_soc_dapm_get_enum_double,
wcd9335_put_dec_enum);
static const struct snd_kcontrol_new tx_adc_mux5 =
SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_chain_enum,
snd_soc_dapm_get_enum_double,
wcd9335_put_dec_enum);
static const struct snd_kcontrol_new tx_adc_mux6 =
SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_chain_enum,
snd_soc_dapm_get_enum_double,
wcd9335_put_dec_enum);
static const struct snd_kcontrol_new tx_adc_mux7 =
SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_chain_enum,
snd_soc_dapm_get_enum_double,
wcd9335_put_dec_enum);
static const struct snd_kcontrol_new tx_adc_mux8 =
SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_chain_enum,
snd_soc_dapm_get_enum_double,
wcd9335_put_dec_enum);
static int wcd9335_set_mix_interpolator_rate(struct snd_soc_dai *dai,
int rate_val,
u32 rate)
{
struct snd_soc_component *component = dai->component;
struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
struct wcd9335_slim_ch *ch;
int val, j;
list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) {
val = snd_soc_component_read(component,
WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j)) &
WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
if (val == (ch->shift + INTn_2_INP_SEL_RX0))
snd_soc_component_update_bits(component,
WCD9335_CDC_RX_PATH_MIX_CTL(j),
WCD9335_CDC_MIX_PCM_RATE_MASK,
rate_val);
}
}
return 0;
}
static int wcd9335_set_prim_interpolator_rate(struct snd_soc_dai *dai,
u8 rate_val,
u32 rate)
{
struct snd_soc_component *comp = dai->component;
struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
struct wcd9335_slim_ch *ch;
u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel;
int inp, j;
list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
inp = ch->shift + INTn_1_MIX_INP_SEL_RX0;
/*
* Loop through all interpolator MUX inputs and find out
* to which interpolator input, the slim rx port
* is connected
*/
for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) {
cfg0 = snd_soc_component_read(comp,
WCD9335_CDC_RX_INP_MUX_RX_INT_CFG0(j));
cfg1 = snd_soc_component_read(comp,
WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j));
inp0_sel = cfg0 &
WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
inp1_sel = (cfg0 >> 4) &
WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
inp2_sel = (cfg1 >> 4) &
WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
if ((inp0_sel == inp) || (inp1_sel == inp) ||
(inp2_sel == inp)) {
/* rate is in Hz */
if ((j == 0) && (rate == 44100))
dev_info(wcd->dev,
"Cannot set 44.1KHz on INT0\n");
else
snd_soc_component_update_bits(comp,
WCD9335_CDC_RX_PATH_CTL(j),
WCD9335_CDC_MIX_PCM_RATE_MASK,
rate_val);
}
}
}
return 0;
}
static int wcd9335_set_interpolator_rate(struct snd_soc_dai *dai, u32 rate)
{
int i;
/* set mixing path rate */
for (i = 0; i < ARRAY_SIZE(int_mix_rate_val); i++) {
if (rate == int_mix_rate_val[i].rate) {
wcd9335_set_mix_interpolator_rate(dai,
int_mix_rate_val[i].rate_val, rate);
break;
}
}
/* set primary path sample rate */
for (i = 0; i < ARRAY_SIZE(int_prim_rate_val); i++) {
if (rate == int_prim_rate_val[i].rate) {
wcd9335_set_prim_interpolator_rate(dai,
int_prim_rate_val[i].rate_val, rate);
break;
}
}
return 0;
}
static int wcd9335_slim_set_hw_params(struct wcd9335_codec *wcd,
struct wcd_slim_codec_dai_data *dai_data,
int direction)
{
struct list_head *slim_ch_list = &dai_data->slim_ch_list;
struct slim_stream_config *cfg = &dai_data->sconfig;
struct wcd9335_slim_ch *ch;
u16 payload = 0;
int ret, i;
cfg->ch_count = 0;
cfg->direction = direction;
cfg->port_mask = 0;
/* Configure slave interface device */
list_for_each_entry(ch, slim_ch_list, list) {
cfg->ch_count++;
payload |= 1 << ch->shift;
cfg->port_mask |= BIT(ch->port);
}
cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL);
if (!cfg->chs)
return -ENOMEM;
i = 0;
list_for_each_entry(ch, slim_ch_list, list) {
cfg->chs[i++] = ch->ch_num;
if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
/* write to interface device */
ret = regmap_write(wcd->if_regmap,
WCD9335_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port),
payload);
if (ret < 0)
goto err;
/* configure the slave port for water mark and enable*/
ret = regmap_write(wcd->if_regmap,
WCD9335_SLIM_PGD_RX_PORT_CFG(ch->port),
WCD9335_SLIM_WATER_MARK_VAL);
if (ret < 0)
goto err;
} else {
ret = regmap_write(wcd->if_regmap,
WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port),
payload & 0x00FF);
if (ret < 0)
goto err;
/* ports 8,9 */
ret = regmap_write(wcd->if_regmap,
WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port),
(payload & 0xFF00)>>8);
if (ret < 0)
goto err;
/* configure the slave port for water mark and enable*/
ret = regmap_write(wcd->if_regmap,
WCD9335_SLIM_PGD_TX_PORT_CFG(ch->port),
WCD9335_SLIM_WATER_MARK_VAL);
if (ret < 0)
goto err;
}
}
dai_data->sruntime = slim_stream_allocate(wcd->slim, "WCD9335-SLIM");
return 0;
err:
dev_err(wcd->dev, "Error Setting slim hw params\n");
kfree(cfg->chs);
cfg->chs = NULL;
return ret;
}
static int wcd9335_set_decimator_rate(struct snd_soc_dai *dai,
u8 rate_val, u32 rate)
{
struct snd_soc_component *comp = dai->component;
struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp);
u8 shift = 0, shift_val = 0, tx_mux_sel;
struct wcd9335_slim_ch *ch;
int tx_port, tx_port_reg;
int decimator = -1;
list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
tx_port = ch->port;
if ((tx_port == 12) || (tx_port >= 14)) {
dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n",
tx_port, dai->id);
return -EINVAL;
}
/* Find the SB TX MUX input - which decimator is connected */
if (tx_port < 4) {
tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0;
shift = (tx_port << 1);
shift_val = 0x03;
} else if (tx_port < 8) {
tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1;
shift = ((tx_port - 4) << 1);
shift_val = 0x03;
} else if (tx_port < 11) {
tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2;
shift = ((tx_port - 8) << 1);
shift_val = 0x03;
} else if (tx_port == 11) {
tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3;
shift = 0;
shift_val = 0x0F;
} else /* (tx_port == 13) */ {
tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3;
shift = 4;
shift_val = 0x03;
}
tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) &
(shift_val << shift);
tx_mux_sel = tx_mux_sel >> shift;
if (tx_port <= 8) {
if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3))
decimator = tx_port;
} else if (tx_port <= 10) {
if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
decimator = ((tx_port == 9) ? 7 : 6);
} else if (tx_port == 11) {
if ((tx_mux_sel >= 1) && (tx_mux_sel < 7))
decimator = tx_mux_sel - 1;
} else if (tx_port == 13) {
if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
decimator = 5;
}
if (decimator >= 0) {
snd_soc_component_update_bits(comp,
WCD9335_CDC_TX_PATH_CTL(decimator),
WCD9335_CDC_TX_PATH_CTL_PCM_RATE_MASK,
rate_val);
} else if ((tx_port <= 8) && (tx_mux_sel == 0x01)) {
/* Check if the TX Mux input is RX MIX TXn */
dev_err(wcd->dev, "RX_MIX_TX%u going to SLIM TX%u\n",
tx_port, tx_port);
} else {
dev_err(wcd->dev, "ERROR: Invalid decimator: %d\n",
decimator);
return -EINVAL;
}
}
return 0;
}
static int wcd9335_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct wcd9335_codec *wcd;
int ret, tx_fs_rate = 0;
wcd = snd_soc_component_get_drvdata(dai->component);
switch (substream->stream) {
case SNDRV_PCM_STREAM_PLAYBACK:
ret = wcd9335_set_interpolator_rate(dai, params_rate(params));
if (ret) {
dev_err(wcd->dev, "cannot set sample rate: %u\n",
params_rate(params));
return ret;
}
switch (params_width(params)) {
case 16 ... 24:
wcd->dai[dai->id].sconfig.bps = params_width(params);
break;
default:
dev_err(wcd->dev, "%s: Invalid format 0x%x\n",
__func__, params_width(params));
return -EINVAL;
}
break;
case SNDRV_PCM_STREAM_CAPTURE:
switch (params_rate(params)) {
case 8000:
tx_fs_rate = 0;
break;
case 16000:
tx_fs_rate = 1;
break;
case 32000:
tx_fs_rate = 3;
break;
case 48000:
tx_fs_rate = 4;
break;
case 96000:
tx_fs_rate = 5;
break;
case 192000:
tx_fs_rate = 6;
break;
case 384000:
tx_fs_rate = 7;
break;
default:
dev_err(wcd->dev, "%s: Invalid TX sample rate: %d\n",
__func__, params_rate(params));
return -EINVAL;
}
ret = wcd9335_set_decimator_rate(dai, tx_fs_rate,
params_rate(params));
if (ret < 0) {
dev_err(wcd->dev, "Cannot set TX Decimator rate\n");
return ret;
}
switch (params_width(params)) {
case 16 ... 32:
wcd->dai[dai->id].sconfig.bps = params_width(params);
break;
default:
dev_err(wcd->dev, "%s: Invalid format 0x%x\n",
__func__, params_width(params));
return -EINVAL;
}
break;
default:
dev_err(wcd->dev, "Invalid stream type %d\n",
substream->stream);
return -EINVAL;
}
wcd->dai[dai->id].sconfig.rate = params_rate(params);
wcd9335_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream);
return 0;
}
static int wcd9335_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct wcd_slim_codec_dai_data *dai_data;
struct wcd9335_codec *wcd;
struct slim_stream_config *cfg;
wcd = snd_soc_component_get_drvdata(dai->component);
dai_data = &wcd->dai[dai->id];
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
cfg = &dai_data->sconfig;
slim_stream_prepare(dai_data->sruntime, cfg);
slim_stream_enable(dai_data->sruntime);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
slim_stream_disable(dai_data->sruntime);
slim_stream_unprepare(dai_data->sruntime);
break;
default:
break;
}
return 0;
}
static int wcd9335_set_channel_map(struct snd_soc_dai *dai,
unsigned int tx_num, unsigned int *tx_slot,
unsigned int rx_num, unsigned int *rx_slot)
{
struct wcd9335_codec *wcd;
int i;
wcd = snd_soc_component_get_drvdata(dai->component);
if (!tx_slot || !rx_slot) {
dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n",
tx_slot, rx_slot);
return -EINVAL;
}
wcd->num_rx_port = rx_num;
for (i = 0; i < rx_num; i++) {
wcd->rx_chs[i].ch_num = rx_slot[i];
INIT_LIST_HEAD(&wcd->rx_chs[i].list);
}
wcd->num_tx_port = tx_num;
for (i = 0; i < tx_num; i++) {
wcd->tx_chs[i].ch_num = tx_slot[i];
INIT_LIST_HEAD(&wcd->tx_chs[i].list);
}
return 0;
}
static int wcd9335_get_channel_map(struct snd_soc_dai *dai,
unsigned int *tx_num, unsigned int *tx_slot,
unsigned int *rx_num, unsigned int *rx_slot)
{
struct wcd9335_slim_ch *ch;
struct wcd9335_codec *wcd;
int i = 0;
wcd = snd_soc_component_get_drvdata(dai->component);
switch (dai->id) {
case AIF1_PB:
case AIF2_PB:
case AIF3_PB:
case AIF4_PB:
if (!rx_slot || !rx_num) {
dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n",
rx_slot, rx_num);
return -EINVAL;
}
list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
rx_slot[i++] = ch->ch_num;
*rx_num = i;
break;
case AIF1_CAP:
case AIF2_CAP:
case AIF3_CAP:
if (!tx_slot || !tx_num) {
dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n",
tx_slot, tx_num);
return -EINVAL;
}
list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
tx_slot[i++] = ch->ch_num;
*tx_num = i;
break;
default:
dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id);
break;
}
return 0;
}
static const struct snd_soc_dai_ops wcd9335_dai_ops = {
.hw_params = wcd9335_hw_params,
.trigger = wcd9335_trigger,
.set_channel_map = wcd9335_set_channel_map,
.get_channel_map = wcd9335_get_channel_map,
};
static struct snd_soc_dai_driver wcd9335_slim_dais[] = {
[0] = {
.name = "wcd9335_rx1",
.id = AIF1_PB,
.playback = {
.stream_name = "AIF1 Playback",
.rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
SNDRV_PCM_RATE_384000,
.formats = WCD9335_FORMATS_S16_S24_LE,
.rate_max = 384000,
.rate_min = 8000,
.channels_min = 1,
.channels_max = 2,
},
.ops = &wcd9335_dai_ops,
},
[1] = {
.name = "wcd9335_tx1",
.id = AIF1_CAP,
.capture = {
.stream_name = "AIF1 Capture",
.rates = WCD9335_RATES_MASK,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.rate_min = 8000,
.rate_max = 192000,
.channels_min = 1,
.channels_max = 4,
},
.ops = &wcd9335_dai_ops,
},
[2] = {
.name = "wcd9335_rx2",
.id = AIF2_PB,
.playback = {
.stream_name = "AIF2 Playback",
.rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
SNDRV_PCM_RATE_384000,
.formats = WCD9335_FORMATS_S16_S24_LE,
.rate_min = 8000,
.rate_max = 384000,
.channels_min = 1,
.channels_max = 2,
},
.ops = &wcd9335_dai_ops,
},
[3] = {
.name = "wcd9335_tx2",
.id = AIF2_CAP,
.capture = {
.stream_name = "AIF2 Capture",
.rates = WCD9335_RATES_MASK,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.rate_min = 8000,
.rate_max = 192000,
.channels_min = 1,
.channels_max = 4,
},
.ops = &wcd9335_dai_ops,
},
[4] = {
.name = "wcd9335_rx3",
.id = AIF3_PB,
.playback = {
.stream_name = "AIF3 Playback",
.rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
SNDRV_PCM_RATE_384000,
.formats = WCD9335_FORMATS_S16_S24_LE,
.rate_min = 8000,
.rate_max = 384000,
.channels_min = 1,
.channels_max = 2,
},
.ops = &wcd9335_dai_ops,
},
[5] = {
.name = "wcd9335_tx3",
.id = AIF3_CAP,
.capture = {
.stream_name = "AIF3 Capture",
.rates = WCD9335_RATES_MASK,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.rate_min = 8000,
.rate_max = 192000,
.channels_min = 1,
.channels_max = 4,
},
.ops = &wcd9335_dai_ops,
},
[6] = {
.name = "wcd9335_rx4",
.id = AIF4_PB,
.playback = {
.stream_name = "AIF4 Playback",
.rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
SNDRV_PCM_RATE_384000,
.formats = WCD9335_FORMATS_S16_S24_LE,
.rate_min = 8000,
.rate_max = 384000,
.channels_min = 1,
.channels_max = 2,
},
.ops = &wcd9335_dai_ops,
},
};
static int wcd9335_get_compander(struct snd_kcontrol *kc,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
ucontrol->value.integer.value[0] = wcd->comp_enabled[comp];
return 0;
}
static int wcd9335_set_compander(struct snd_kcontrol *kc,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
int comp = ((struct soc_mixer_control *) kc->private_value)->shift;
int value = ucontrol->value.integer.value[0];
int sel;
wcd->comp_enabled[comp] = value;
sel = value ? WCD9335_HPH_GAIN_SRC_SEL_COMPANDER :
WCD9335_HPH_GAIN_SRC_SEL_REGISTER;
/* Any specific register configuration for compander */
switch (comp) {
case COMPANDER_1:
/* Set Gain Source Select based on compander enable/disable */
snd_soc_component_update_bits(component, WCD9335_HPH_L_EN,
WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
break;
case COMPANDER_2:
snd_soc_component_update_bits(component, WCD9335_HPH_R_EN,
WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
break;
case COMPANDER_5:
snd_soc_component_update_bits(component, WCD9335_SE_LO_LO3_GAIN,
WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
break;
case COMPANDER_6:
snd_soc_component_update_bits(component, WCD9335_SE_LO_LO4_GAIN,
WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
break;
default:
break;
}
return 0;
}
static int wcd9335_rx_hph_mode_get(struct snd_kcontrol *kc,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
ucontrol->value.enumerated.item[0] = wcd->hph_mode;
return 0;
}
static int wcd9335_rx_hph_mode_put(struct snd_kcontrol *kc,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
u32 mode_val;
mode_val = ucontrol->value.enumerated.item[0];
if (mode_val == 0) {
dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n");
mode_val = CLS_H_HIFI;
}
wcd->hph_mode = mode_val;
return 0;
}
static const struct snd_kcontrol_new wcd9335_snd_controls[] = {
/* -84dB min - 40dB max */
SOC_SINGLE_S8_TLV("RX0 Digital Volume", WCD9335_CDC_RX0_RX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX1 Digital Volume", WCD9335_CDC_RX1_RX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX2 Digital Volume", WCD9335_CDC_RX2_RX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX3 Digital Volume", WCD9335_CDC_RX3_RX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX4 Digital Volume", WCD9335_CDC_RX4_RX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX5 Digital Volume", WCD9335_CDC_RX5_RX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX6 Digital Volume", WCD9335_CDC_RX6_RX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX7 Digital Volume", WCD9335_CDC_RX7_RX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX8 Digital Volume", WCD9335_CDC_RX8_RX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX0 Mix Digital Volume", WCD9335_CDC_RX0_RX_VOL_MIX_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX1 Mix Digital Volume", WCD9335_CDC_RX1_RX_VOL_MIX_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX2 Mix Digital Volume", WCD9335_CDC_RX2_RX_VOL_MIX_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX3 Mix Digital Volume", WCD9335_CDC_RX3_RX_VOL_MIX_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX4 Mix Digital Volume", WCD9335_CDC_RX4_RX_VOL_MIX_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX5 Mix Digital Volume", WCD9335_CDC_RX5_RX_VOL_MIX_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX6 Mix Digital Volume", WCD9335_CDC_RX6_RX_VOL_MIX_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX7 Mix Digital Volume", WCD9335_CDC_RX7_RX_VOL_MIX_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX8 Mix Digital Volume", WCD9335_CDC_RX8_RX_VOL_MIX_CTL,
-84, 40, digital_gain),
SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum),
SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum),
SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum),
SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum),
SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum),
SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum),
SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum),
SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum),
SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum),
SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum),
SOC_ENUM("RX INT5_1 HPF cut off", cf_int5_1_enum),
SOC_ENUM("RX INT5_2 HPF cut off", cf_int5_2_enum),
SOC_ENUM("RX INT6_1 HPF cut off", cf_int6_1_enum),
SOC_ENUM("RX INT6_2 HPF cut off", cf_int6_2_enum),
SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum),
SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum),
SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum),
SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum),
SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0,
wcd9335_get_compander, wcd9335_set_compander),
SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0,
wcd9335_get_compander, wcd9335_set_compander),
SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0,
wcd9335_get_compander, wcd9335_set_compander),
SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0,
wcd9335_get_compander, wcd9335_set_compander),
SOC_SINGLE_EXT("COMP5 Switch", SND_SOC_NOPM, COMPANDER_5, 1, 0,
wcd9335_get_compander, wcd9335_set_compander),
SOC_SINGLE_EXT("COMP6 Switch", SND_SOC_NOPM, COMPANDER_6, 1, 0,
wcd9335_get_compander, wcd9335_set_compander),
SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0,
wcd9335_get_compander, wcd9335_set_compander),
SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0,
wcd9335_get_compander, wcd9335_set_compander),
SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
wcd9335_rx_hph_mode_get, wcd9335_rx_hph_mode_put),
/* Gain Controls */
SOC_SINGLE_TLV("EAR PA Volume", WCD9335_ANA_EAR, 4, 4, 1,
ear_pa_gain),
SOC_SINGLE_TLV("HPHL Volume", WCD9335_HPH_L_EN, 0, 20, 1,
line_gain),
SOC_SINGLE_TLV("HPHR Volume", WCD9335_HPH_R_EN, 0, 20, 1,
line_gain),
SOC_SINGLE_TLV("LINEOUT1 Volume", WCD9335_DIFF_LO_LO1_COMPANDER,
3, 16, 1, line_gain),
SOC_SINGLE_TLV("LINEOUT2 Volume", WCD9335_DIFF_LO_LO2_COMPANDER,
3, 16, 1, line_gain),
SOC_SINGLE_TLV("LINEOUT3 Volume", WCD9335_SE_LO_LO3_GAIN, 0, 20, 1,
line_gain),
SOC_SINGLE_TLV("LINEOUT4 Volume", WCD9335_SE_LO_LO4_GAIN, 0, 20, 1,
line_gain),
SOC_SINGLE_TLV("ADC1 Volume", WCD9335_ANA_AMIC1, 0, 20, 0,
analog_gain),
SOC_SINGLE_TLV("ADC2 Volume", WCD9335_ANA_AMIC2, 0, 20, 0,
analog_gain),
SOC_SINGLE_TLV("ADC3 Volume", WCD9335_ANA_AMIC3, 0, 20, 0,
analog_gain),
SOC_SINGLE_TLV("ADC4 Volume", WCD9335_ANA_AMIC4, 0, 20, 0,
analog_gain),
SOC_SINGLE_TLV("ADC5 Volume", WCD9335_ANA_AMIC5, 0, 20, 0,
analog_gain),
SOC_SINGLE_TLV("ADC6 Volume", WCD9335_ANA_AMIC6, 0, 20, 0,
analog_gain),
SOC_ENUM("TX0 HPF cut off", cf_dec0_enum),
SOC_ENUM("TX1 HPF cut off", cf_dec1_enum),
SOC_ENUM("TX2 HPF cut off", cf_dec2_enum),
SOC_ENUM("TX3 HPF cut off", cf_dec3_enum),
SOC_ENUM("TX4 HPF cut off", cf_dec4_enum),
SOC_ENUM("TX5 HPF cut off", cf_dec5_enum),
SOC_ENUM("TX6 HPF cut off", cf_dec6_enum),
SOC_ENUM("TX7 HPF cut off", cf_dec7_enum),
SOC_ENUM("TX8 HPF cut off", cf_dec8_enum),
};
static const struct snd_soc_dapm_route wcd9335_audio_map[] = {
{"SLIM RX0 MUX", "AIF1_PB", "AIF1 PB"},
{"SLIM RX1 MUX", "AIF1_PB", "AIF1 PB"},
{"SLIM RX2 MUX", "AIF1_PB", "AIF1 PB"},
{"SLIM RX3 MUX", "AIF1_PB", "AIF1 PB"},
{"SLIM RX4 MUX", "AIF1_PB", "AIF1 PB"},
{"SLIM RX5 MUX", "AIF1_PB", "AIF1 PB"},
{"SLIM RX6 MUX", "AIF1_PB", "AIF1 PB"},
{"SLIM RX7 MUX", "AIF1_PB", "AIF1 PB"},
{"SLIM RX0 MUX", "AIF2_PB", "AIF2 PB"},
{"SLIM RX1 MUX", "AIF2_PB", "AIF2 PB"},
{"SLIM RX2 MUX", "AIF2_PB", "AIF2 PB"},
{"SLIM RX3 MUX", "AIF2_PB", "AIF2 PB"},
{"SLIM RX4 MUX", "AIF2_PB", "AIF2 PB"},
{"SLIM RX5 MUX", "AIF2_PB", "AIF2 PB"},
{"SLIM RX6 MUX", "AIF2_PB", "AIF2 PB"},
{"SLIM RX7 MUX", "AIF2_PB", "AIF2 PB"},
{"SLIM RX0 MUX", "AIF3_PB", "AIF3 PB"},
{"SLIM RX1 MUX", "AIF3_PB", "AIF3 PB"},
{"SLIM RX2 MUX", "AIF3_PB", "AIF3 PB"},
{"SLIM RX3 MUX", "AIF3_PB", "AIF3 PB"},
{"SLIM RX4 MUX", "AIF3_PB", "AIF3 PB"},
{"SLIM RX5 MUX", "AIF3_PB", "AIF3 PB"},
{"SLIM RX6 MUX", "AIF3_PB", "AIF3 PB"},
{"SLIM RX7 MUX", "AIF3_PB", "AIF3 PB"},
{"SLIM RX0 MUX", "AIF4_PB", "AIF4 PB"},
{"SLIM RX1 MUX", "AIF4_PB", "AIF4 PB"},
{"SLIM RX2 MUX", "AIF4_PB", "AIF4 PB"},
{"SLIM RX3 MUX", "AIF4_PB", "AIF4 PB"},
{"SLIM RX4 MUX", "AIF4_PB", "AIF4 PB"},
{"SLIM RX5 MUX", "AIF4_PB", "AIF4 PB"},
{"SLIM RX6 MUX", "AIF4_PB", "AIF4 PB"},
{"SLIM RX7 MUX", "AIF4_PB", "AIF4 PB"},
{"SLIM RX0", NULL, "SLIM RX0 MUX"},
{"SLIM RX1", NULL, "SLIM RX1 MUX"},
{"SLIM RX2", NULL, "SLIM RX2 MUX"},
{"SLIM RX3", NULL, "SLIM RX3 MUX"},
{"SLIM RX4", NULL, "SLIM RX4 MUX"},
{"SLIM RX5", NULL, "SLIM RX5 MUX"},
{"SLIM RX6", NULL, "SLIM RX6 MUX"},
{"SLIM RX7", NULL, "SLIM RX7 MUX"},
WCD9335_INTERPOLATOR_PATH(0),
WCD9335_INTERPOLATOR_PATH(1),
WCD9335_INTERPOLATOR_PATH(2),
WCD9335_INTERPOLATOR_PATH(3),
WCD9335_INTERPOLATOR_PATH(4),
WCD9335_INTERPOLATOR_PATH(5),
WCD9335_INTERPOLATOR_PATH(6),
WCD9335_INTERPOLATOR_PATH(7),
WCD9335_INTERPOLATOR_PATH(8),
/* EAR PA */
{"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 INTERP"},
{"RX INT0 DAC", NULL, "RX INT0 DEM MUX"},
{"RX INT0 DAC", NULL, "RX_BIAS"},
{"EAR PA", NULL, "RX INT0 DAC"},
{"EAR", NULL, "EAR PA"},
/* HPHL */
{"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 INTERP"},
{"RX INT1 DAC", NULL, "RX INT1 DEM MUX"},
{"RX INT1 DAC", NULL, "RX_BIAS"},
{"HPHL PA", NULL, "RX INT1 DAC"},
{"HPHL", NULL, "HPHL PA"},
/* HPHR */
{"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 INTERP"},
{"RX INT2 DAC", NULL, "RX INT2 DEM MUX"},
{"RX INT2 DAC", NULL, "RX_BIAS"},
{"HPHR PA", NULL, "RX INT2 DAC"},
{"HPHR", NULL, "HPHR PA"},
/* LINEOUT1 */
{"RX INT3 DAC", NULL, "RX INT3 INTERP"},
{"RX INT3 DAC", NULL, "RX_BIAS"},
{"LINEOUT1 PA", NULL, "RX INT3 DAC"},
{"LINEOUT1", NULL, "LINEOUT1 PA"},
/* LINEOUT2 */
{"RX INT4 DAC", NULL, "RX INT4 INTERP"},
{"RX INT4 DAC", NULL, "RX_BIAS"},
{"LINEOUT2 PA", NULL, "RX INT4 DAC"},
{"LINEOUT2", NULL, "LINEOUT2 PA"},
/* LINEOUT3 */
{"RX INT5 DAC", NULL, "RX INT5 INTERP"},
{"RX INT5 DAC", NULL, "RX_BIAS"},
{"LINEOUT3 PA", NULL, "RX INT5 DAC"},
{"LINEOUT3", NULL, "LINEOUT3 PA"},
/* LINEOUT4 */
{"RX INT6 DAC", NULL, "RX INT6 INTERP"},
{"RX INT6 DAC", NULL, "RX_BIAS"},
{"LINEOUT4 PA", NULL, "RX INT6 DAC"},
{"LINEOUT4", NULL, "LINEOUT4 PA"},
/* SLIMBUS Connections */
{"AIF1 CAP", NULL, "AIF1_CAP Mixer"},
{"AIF2 CAP", NULL, "AIF2_CAP Mixer"},
{"AIF3 CAP", NULL, "AIF3_CAP Mixer"},
/* ADC Mux */
WCD9335_ADC_MUX_PATH(0),
WCD9335_ADC_MUX_PATH(1),
WCD9335_ADC_MUX_PATH(2),
WCD9335_ADC_MUX_PATH(3),
WCD9335_ADC_MUX_PATH(4),
WCD9335_ADC_MUX_PATH(5),
WCD9335_ADC_MUX_PATH(6),
WCD9335_ADC_MUX_PATH(7),
WCD9335_ADC_MUX_PATH(8),
/* ADC Connections */
{"ADC1", NULL, "AMIC1"},
{"ADC2", NULL, "AMIC2"},
{"ADC3", NULL, "AMIC3"},
{"ADC4", NULL, "AMIC4"},
{"ADC5", NULL, "AMIC5"},
{"ADC6", NULL, "AMIC6"},
};
static int wcd9335_micbias_control(struct snd_soc_component *component,
int micb_num, int req, bool is_dapm)
{
struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(component);
int micb_index = micb_num - 1;
u16 micb_reg;
if ((micb_index < 0) || (micb_index > WCD9335_MAX_MICBIAS - 1)) {
dev_err(wcd->dev, "Invalid micbias index, micb_ind:%d\n",
micb_index);
return -EINVAL;
}
switch (micb_num) {
case MIC_BIAS_1:
micb_reg = WCD9335_ANA_MICB1;
break;
case MIC_BIAS_2:
micb_reg = WCD9335_ANA_MICB2;
break;
case MIC_BIAS_3:
micb_reg = WCD9335_ANA_MICB3;
break;
case MIC_BIAS_4:
micb_reg = WCD9335_ANA_MICB4;
break;
default:
dev_err(component->dev, "%s: Invalid micbias number: %d\n",
__func__, micb_num);
return -EINVAL;
}
switch (req) {
case MICB_PULLUP_ENABLE:
wcd->pullup_ref[micb_index]++;
if ((wcd->pullup_ref[micb_index] == 1) &&
(wcd->micb_ref[micb_index] == 0))
snd_soc_component_update_bits(component, micb_reg,
0xC0, 0x80);
break;
case MICB_PULLUP_DISABLE:
wcd->pullup_ref[micb_index]--;
if ((wcd->pullup_ref[micb_index] == 0) &&
(wcd->micb_ref[micb_index] == 0))
snd_soc_component_update_bits(component, micb_reg,
0xC0, 0x00);
break;
case MICB_ENABLE:
wcd->micb_ref[micb_index]++;
if (wcd->micb_ref[micb_index] == 1)
snd_soc_component_update_bits(component, micb_reg,
0xC0, 0x40);
break;
case MICB_DISABLE:
wcd->micb_ref[micb_index]--;
if ((wcd->micb_ref[micb_index] == 0) &&
(wcd->pullup_ref[micb_index] > 0))
snd_soc_component_update_bits(component, micb_reg,
0xC0, 0x80);
else if ((wcd->micb_ref[micb_index] == 0) &&
(wcd->pullup_ref[micb_index] == 0)) {
snd_soc_component_update_bits(component, micb_reg,
0xC0, 0x00);
}
break;
}
return 0;
}
static int __wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w,
int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
int micb_num;
if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
micb_num = MIC_BIAS_1;
else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
micb_num = MIC_BIAS_2;
else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
micb_num = MIC_BIAS_3;
else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
micb_num = MIC_BIAS_4;
else
return -EINVAL;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/*
* MIC BIAS can also be requested by MBHC,
* so use ref count to handle micbias pullup
* and enable requests
*/
wcd9335_micbias_control(comp, micb_num, MICB_ENABLE, true);
break;
case SND_SOC_DAPM_POST_PMU:
/* wait for cnp time */
usleep_range(1000, 1100);
break;
case SND_SOC_DAPM_POST_PMD:
wcd9335_micbias_control(comp, micb_num, MICB_DISABLE, true);
break;
}
return 0;
}
static int wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kc, int event)
{
return __wcd9335_codec_enable_micbias(w, event);
}
static void wcd9335_codec_set_tx_hold(struct snd_soc_component *comp,
u16 amic_reg, bool set)
{
u8 mask = 0x20;
u8 val;
if (amic_reg == WCD9335_ANA_AMIC1 || amic_reg == WCD9335_ANA_AMIC3 ||
amic_reg == WCD9335_ANA_AMIC5)
mask = 0x40;
val = set ? mask : 0x00;
switch (amic_reg) {
case WCD9335_ANA_AMIC1:
case WCD9335_ANA_AMIC2:
snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC2, mask,
val);
break;
case WCD9335_ANA_AMIC3:
case WCD9335_ANA_AMIC4:
snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC4, mask,
val);
break;
case WCD9335_ANA_AMIC5:
case WCD9335_ANA_AMIC6:
snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC6, mask,
val);
break;
default:
dev_err(comp->dev, "%s: invalid amic: %d\n",
__func__, amic_reg);
break;
}
}
static int wcd9335_codec_enable_adc(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kc, int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
wcd9335_codec_set_tx_hold(comp, w->reg, true);
break;
default:
break;
}
return 0;
}
static int wcd9335_codec_find_amic_input(struct snd_soc_component *comp,
int adc_mux_n)
{
int mux_sel, reg, mreg;
if (adc_mux_n < 0 || adc_mux_n > WCD9335_MAX_VALID_ADC_MUX ||
adc_mux_n == WCD9335_INVALID_ADC_MUX)
return 0;
/* Check whether adc mux input is AMIC or DMIC */
if (adc_mux_n < 4) {
reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 2 * adc_mux_n;
mreg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 2 * adc_mux_n;
mux_sel = snd_soc_component_read(comp, reg) & 0x3;
} else {
reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + adc_mux_n - 4;
mreg = reg;
mux_sel = snd_soc_component_read(comp, reg) >> 6;
}
if (mux_sel != WCD9335_CDC_TX_INP_MUX_SEL_AMIC)
return 0;
return snd_soc_component_read(comp, mreg) & 0x07;
}
static u16 wcd9335_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp,
int amic)
{
u16 pwr_level_reg = 0;
switch (amic) {
case 1:
case 2:
pwr_level_reg = WCD9335_ANA_AMIC1;
break;
case 3:
case 4:
pwr_level_reg = WCD9335_ANA_AMIC3;
break;
case 5:
case 6:
pwr_level_reg = WCD9335_ANA_AMIC5;
break;
default:
dev_err(comp->dev, "invalid amic: %d\n", amic);
break;
}
return pwr_level_reg;
}
static int wcd9335_codec_enable_dec(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kc, int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
unsigned int decimator;
char *dec_adc_mux_name = NULL;
char *widget_name = NULL;
char *wname;
int ret = 0, amic_n;
u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg;
u16 tx_gain_ctl_reg;
char *dec;
u8 hpf_coff_freq;
widget_name = kmemdup_nul(w->name, 15, GFP_KERNEL);
if (!widget_name)
return -ENOMEM;
wname = widget_name;
dec_adc_mux_name = strsep(&widget_name, " ");
if (!dec_adc_mux_name) {
dev_err(comp->dev, "%s: Invalid decimator = %s\n",
__func__, w->name);
ret = -EINVAL;
goto out;
}
dec_adc_mux_name = widget_name;
dec = strpbrk(dec_adc_mux_name, "012345678");
if (!dec) {
dev_err(comp->dev, "%s: decimator index not found\n",
__func__);
ret = -EINVAL;
goto out;
}
ret = kstrtouint(dec, 10, &decimator);
if (ret < 0) {
dev_err(comp->dev, "%s: Invalid decimator = %s\n",
__func__, wname);
ret = -EINVAL;
goto out;
}
tx_vol_ctl_reg = WCD9335_CDC_TX0_TX_PATH_CTL + 16 * decimator;
hpf_gate_reg = WCD9335_CDC_TX0_TX_PATH_SEC2 + 16 * decimator;
dec_cfg_reg = WCD9335_CDC_TX0_TX_PATH_CFG0 + 16 * decimator;
tx_gain_ctl_reg = WCD9335_CDC_TX0_TX_VOL_CTL + 16 * decimator;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
amic_n = wcd9335_codec_find_amic_input(comp, decimator);
if (amic_n)
pwr_level_reg = wcd9335_codec_get_amic_pwlvl_reg(comp,
amic_n);
if (pwr_level_reg) {
switch ((snd_soc_component_read(comp, pwr_level_reg) &
WCD9335_AMIC_PWR_LVL_MASK) >>
WCD9335_AMIC_PWR_LVL_SHIFT) {
case WCD9335_AMIC_PWR_LEVEL_LP:
snd_soc_component_update_bits(comp, dec_cfg_reg,
WCD9335_DEC_PWR_LVL_MASK,
WCD9335_DEC_PWR_LVL_LP);
break;
case WCD9335_AMIC_PWR_LEVEL_HP:
snd_soc_component_update_bits(comp, dec_cfg_reg,
WCD9335_DEC_PWR_LVL_MASK,
WCD9335_DEC_PWR_LVL_HP);
break;
case WCD9335_AMIC_PWR_LEVEL_DEFAULT:
default:
snd_soc_component_update_bits(comp, dec_cfg_reg,
WCD9335_DEC_PWR_LVL_MASK,
WCD9335_DEC_PWR_LVL_DF);
break;
}
}
hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
if (hpf_coff_freq != CF_MIN_3DB_150HZ)
snd_soc_component_update_bits(comp, dec_cfg_reg,
TX_HPF_CUT_OFF_FREQ_MASK,
CF_MIN_3DB_150HZ << 5);
/* Enable TX PGA Mute */
snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
0x10, 0x10);
/* Enable APC */
snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x08);
break;
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(comp, hpf_gate_reg, 0x01, 0x00);
if (decimator == 0) {
snd_soc_component_write(comp,
WCD9335_MBHC_ZDET_RAMP_CTL, 0x83);
snd_soc_component_write(comp,
WCD9335_MBHC_ZDET_RAMP_CTL, 0xA3);
snd_soc_component_write(comp,
WCD9335_MBHC_ZDET_RAMP_CTL, 0x83);
snd_soc_component_write(comp,
WCD9335_MBHC_ZDET_RAMP_CTL, 0x03);
}
snd_soc_component_update_bits(comp, hpf_gate_reg,
0x01, 0x01);
snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
0x10, 0x00);
snd_soc_component_write(comp, tx_gain_ctl_reg,
snd_soc_component_read(comp, tx_gain_ctl_reg));
break;
case SND_SOC_DAPM_PRE_PMD:
hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x10);
snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x00);
if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
snd_soc_component_update_bits(comp, dec_cfg_reg,
TX_HPF_CUT_OFF_FREQ_MASK,
hpf_coff_freq << 5);
}
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x00);
break;
}
out:
kfree(wname);
return ret;
}
static u8 wcd9335_get_dmic_clk_val(struct snd_soc_component *component,
u32 mclk_rate, u32 dmic_clk_rate)
{
u32 div_factor;
u8 dmic_ctl_val;
dev_err(component->dev,
"%s: mclk_rate = %d, dmic_sample_rate = %d\n",
__func__, mclk_rate, dmic_clk_rate);
/* Default value to return in case of error */
if (mclk_rate == WCD9335_MCLK_CLK_9P6MHZ)
dmic_ctl_val = WCD9335_DMIC_CLK_DIV_2;
else
dmic_ctl_val = WCD9335_DMIC_CLK_DIV_3;
if (dmic_clk_rate == 0) {
dev_err(component->dev,
"%s: dmic_sample_rate cannot be 0\n",
__func__);
goto done;
}
div_factor = mclk_rate / dmic_clk_rate;
switch (div_factor) {
case 2:
dmic_ctl_val = WCD9335_DMIC_CLK_DIV_2;
break;
case 3:
dmic_ctl_val = WCD9335_DMIC_CLK_DIV_3;
break;
case 4:
dmic_ctl_val = WCD9335_DMIC_CLK_DIV_4;
break;
case 6:
dmic_ctl_val = WCD9335_DMIC_CLK_DIV_6;
break;
case 8:
dmic_ctl_val = WCD9335_DMIC_CLK_DIV_8;
break;
case 16:
dmic_ctl_val = WCD9335_DMIC_CLK_DIV_16;
break;
default:
dev_err(component->dev,
"%s: Invalid div_factor %u, clk_rate(%u), dmic_rate(%u)\n",
__func__, div_factor, mclk_rate, dmic_clk_rate);
break;
}
done:
return dmic_ctl_val;
}
static int wcd9335_codec_enable_dmic(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kc, int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp);
u8 dmic_clk_en = 0x01;
u16 dmic_clk_reg;
s32 *dmic_clk_cnt;
u8 dmic_rate_val, dmic_rate_shift = 1;
unsigned int dmic;
int ret;
char *wname;
wname = strpbrk(w->name, "012345");
if (!wname) {
dev_err(comp->dev, "%s: widget not found\n", __func__);
return -EINVAL;
}
ret = kstrtouint(wname, 10, &dmic);
if (ret < 0) {
dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n",
__func__);
return -EINVAL;
}
switch (dmic) {
case 0:
case 1:
dmic_clk_cnt = &(wcd->dmic_0_1_clk_cnt);
dmic_clk_reg = WCD9335_CPE_SS_DMIC0_CTL;
break;
case 2:
case 3:
dmic_clk_cnt = &(wcd->dmic_2_3_clk_cnt);
dmic_clk_reg = WCD9335_CPE_SS_DMIC1_CTL;
break;
case 4:
case 5:
dmic_clk_cnt = &(wcd->dmic_4_5_clk_cnt);
dmic_clk_reg = WCD9335_CPE_SS_DMIC2_CTL;
break;
default:
dev_err(comp->dev, "%s: Invalid DMIC Selection\n",
__func__);
return -EINVAL;
}
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
dmic_rate_val =
wcd9335_get_dmic_clk_val(comp,
wcd->mclk_rate,
wcd->dmic_sample_rate);
(*dmic_clk_cnt)++;
if (*dmic_clk_cnt == 1) {
snd_soc_component_update_bits(comp, dmic_clk_reg,
0x07 << dmic_rate_shift,
dmic_rate_val << dmic_rate_shift);
snd_soc_component_update_bits(comp, dmic_clk_reg,
dmic_clk_en, dmic_clk_en);
}
break;
case SND_SOC_DAPM_POST_PMD:
dmic_rate_val =
wcd9335_get_dmic_clk_val(comp,
wcd->mclk_rate,
wcd->mad_dmic_sample_rate);
(*dmic_clk_cnt)--;
if (*dmic_clk_cnt == 0) {
snd_soc_component_update_bits(comp, dmic_clk_reg,
dmic_clk_en, 0);
snd_soc_component_update_bits(comp, dmic_clk_reg,
0x07 << dmic_rate_shift,
dmic_rate_val << dmic_rate_shift);
}
break;
}
return 0;
}
static void wcd9335_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai,
struct snd_soc_component *component)
{
int port_num = 0;
unsigned short reg = 0;
unsigned int val = 0;
struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
struct wcd9335_slim_ch *ch;
list_for_each_entry(ch, &dai->slim_ch_list, list) {
if (ch->port >= WCD9335_RX_START) {
port_num = ch->port - WCD9335_RX_START;
reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + (port_num / 8);
} else {
port_num = ch->port;
reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8);
}
regmap_read(wcd->if_regmap, reg, &val);
if (!(val & BIT(port_num % 8)))
regmap_write(wcd->if_regmap, reg,
val | BIT(port_num % 8));
}
}
static int wcd9335_codec_enable_slim(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kc,
int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp);
struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift];
switch (event) {
case SND_SOC_DAPM_POST_PMU:
wcd9335_codec_enable_int_port(dai, comp);
break;
case SND_SOC_DAPM_POST_PMD:
kfree(dai->sconfig.chs);
break;
}
return 0;
}
static int wcd9335_codec_enable_mix_path(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kc, int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
u16 gain_reg;
int offset_val = 0;
int val = 0;
switch (w->reg) {
case WCD9335_CDC_RX0_RX_PATH_MIX_CTL:
gain_reg = WCD9335_CDC_RX0_RX_VOL_MIX_CTL;
break;
case WCD9335_CDC_RX1_RX_PATH_MIX_CTL:
gain_reg = WCD9335_CDC_RX1_RX_VOL_MIX_CTL;
break;
case WCD9335_CDC_RX2_RX_PATH_MIX_CTL:
gain_reg = WCD9335_CDC_RX2_RX_VOL_MIX_CTL;
break;
case WCD9335_CDC_RX3_RX_PATH_MIX_CTL:
gain_reg = WCD9335_CDC_RX3_RX_VOL_MIX_CTL;
break;
case WCD9335_CDC_RX4_RX_PATH_MIX_CTL:
gain_reg = WCD9335_CDC_RX4_RX_VOL_MIX_CTL;
break;
case WCD9335_CDC_RX5_RX_PATH_MIX_CTL:
gain_reg = WCD9335_CDC_RX5_RX_VOL_MIX_CTL;
break;
case WCD9335_CDC_RX6_RX_PATH_MIX_CTL:
gain_reg = WCD9335_CDC_RX6_RX_VOL_MIX_CTL;
break;
case WCD9335_CDC_RX7_RX_PATH_MIX_CTL:
gain_reg = WCD9335_CDC_RX7_RX_VOL_MIX_CTL;
break;
case WCD9335_CDC_RX8_RX_PATH_MIX_CTL:
gain_reg = WCD9335_CDC_RX8_RX_VOL_MIX_CTL;
break;
default:
dev_err(comp->dev, "%s: No gain register avail for %s\n",
__func__, w->name);
return 0;
}
switch (event) {
case SND_SOC_DAPM_POST_PMU:
val = snd_soc_component_read(comp, gain_reg);
val += offset_val;
snd_soc_component_write(comp, gain_reg, val);
break;
case SND_SOC_DAPM_POST_PMD:
break;
}
return 0;
}
static u16 wcd9335_interp_get_primary_reg(u16 reg, u16 *ind)
{
u16 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL;
switch (reg) {
case WCD9335_CDC_RX0_RX_PATH_CTL:
case WCD9335_CDC_RX0_RX_PATH_MIX_CTL:
prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL;
*ind = 0;
break;
case WCD9335_CDC_RX1_RX_PATH_CTL:
case WCD9335_CDC_RX1_RX_PATH_MIX_CTL:
prim_int_reg = WCD9335_CDC_RX1_RX_PATH_CTL;
*ind = 1;
break;
case WCD9335_CDC_RX2_RX_PATH_CTL:
case WCD9335_CDC_RX2_RX_PATH_MIX_CTL:
prim_int_reg = WCD9335_CDC_RX2_RX_PATH_CTL;
*ind = 2;
break;
case WCD9335_CDC_RX3_RX_PATH_CTL:
case WCD9335_CDC_RX3_RX_PATH_MIX_CTL:
prim_int_reg = WCD9335_CDC_RX3_RX_PATH_CTL;
*ind = 3;
break;
case WCD9335_CDC_RX4_RX_PATH_CTL:
case WCD9335_CDC_RX4_RX_PATH_MIX_CTL:
prim_int_reg = WCD9335_CDC_RX4_RX_PATH_CTL;
*ind = 4;
break;
case WCD9335_CDC_RX5_RX_PATH_CTL:
case WCD9335_CDC_RX5_RX_PATH_MIX_CTL:
prim_int_reg = WCD9335_CDC_RX5_RX_PATH_CTL;
*ind = 5;
break;
case WCD9335_CDC_RX6_RX_PATH_CTL:
case WCD9335_CDC_RX6_RX_PATH_MIX_CTL:
prim_int_reg = WCD9335_CDC_RX6_RX_PATH_CTL;
*ind = 6;
break;
case WCD9335_CDC_RX7_RX_PATH_CTL:
case WCD9335_CDC_RX7_RX_PATH_MIX_CTL:
prim_int_reg = WCD9335_CDC_RX7_RX_PATH_CTL;
*ind = 7;
break;
case WCD9335_CDC_RX8_RX_PATH_CTL:
case WCD9335_CDC_RX8_RX_PATH_MIX_CTL:
prim_int_reg = WCD9335_CDC_RX8_RX_PATH_CTL;
*ind = 8;
break;
}
return prim_int_reg;
}
static void wcd9335_codec_hd2_control(struct snd_soc_component *component,
u16 prim_int_reg, int event)
{
u16 hd2_scale_reg;
u16 hd2_enable_reg = 0;
if (prim_int_reg == WCD9335_CDC_RX1_RX_PATH_CTL) {
hd2_scale_reg = WCD9335_CDC_RX1_RX_PATH_SEC3;
hd2_enable_reg = WCD9335_CDC_RX1_RX_PATH_CFG0;
}
if (prim_int_reg == WCD9335_CDC_RX2_RX_PATH_CTL) {
hd2_scale_reg = WCD9335_CDC_RX2_RX_PATH_SEC3;
hd2_enable_reg = WCD9335_CDC_RX2_RX_PATH_CFG0;
}
if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) {
snd_soc_component_update_bits(component, hd2_scale_reg,
WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P2500);
snd_soc_component_update_bits(component, hd2_scale_reg,
WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK,
WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_2);
snd_soc_component_update_bits(component, hd2_enable_reg,
WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK,
WCD9335_CDC_RX_PATH_CFG_HD2_ENABLE);
}
if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) {
snd_soc_component_update_bits(component, hd2_enable_reg,
WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK,
WCD9335_CDC_RX_PATH_CFG_HD2_DISABLE);
snd_soc_component_update_bits(component, hd2_scale_reg,
WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK,
WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_1);
snd_soc_component_update_bits(component, hd2_scale_reg,
WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000);
}
}
static int wcd9335_codec_enable_prim_interpolator(
struct snd_soc_component *comp,
u16 reg, int event)
{
struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
u16 ind = 0;
int prim_int_reg = wcd9335_interp_get_primary_reg(reg, &ind);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
wcd->prim_int_users[ind]++;
if (wcd->prim_int_users[ind] == 1) {
snd_soc_component_update_bits(comp, prim_int_reg,
WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
WCD9335_CDC_RX_PGA_MUTE_ENABLE);
wcd9335_codec_hd2_control(comp, prim_int_reg, event);
snd_soc_component_update_bits(comp, prim_int_reg,
WCD9335_CDC_RX_CLK_EN_MASK,
WCD9335_CDC_RX_CLK_ENABLE);
}
if ((reg != prim_int_reg) &&
((snd_soc_component_read(comp, prim_int_reg)) &
WCD9335_CDC_RX_PGA_MUTE_EN_MASK))
snd_soc_component_update_bits(comp, reg,
WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
WCD9335_CDC_RX_PGA_MUTE_ENABLE);
break;
case SND_SOC_DAPM_POST_PMD:
wcd->prim_int_users[ind]--;
if (wcd->prim_int_users[ind] == 0) {
snd_soc_component_update_bits(comp, prim_int_reg,
WCD9335_CDC_RX_CLK_EN_MASK,
WCD9335_CDC_RX_CLK_DISABLE);
snd_soc_component_update_bits(comp, prim_int_reg,
WCD9335_CDC_RX_RESET_MASK,
WCD9335_CDC_RX_RESET_ENABLE);
snd_soc_component_update_bits(comp, prim_int_reg,
WCD9335_CDC_RX_RESET_MASK,
WCD9335_CDC_RX_RESET_DISABLE);
wcd9335_codec_hd2_control(comp, prim_int_reg, event);
}
break;
}
return 0;
}
static int wcd9335_config_compander(struct snd_soc_component *component,
int interp_n, int event)
{
struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
int comp;
u16 comp_ctl0_reg, rx_path_cfg0_reg;
/* EAR does not have compander */
if (!interp_n)
return 0;
comp = interp_n - 1;
if (!wcd->comp_enabled[comp])
return 0;
comp_ctl0_reg = WCD9335_CDC_COMPANDER1_CTL(comp);
rx_path_cfg0_reg = WCD9335_CDC_RX1_RX_PATH_CFG(comp);
if (SND_SOC_DAPM_EVENT_ON(event)) {
/* Enable Compander Clock */
snd_soc_component_update_bits(component, comp_ctl0_reg,
WCD9335_CDC_COMPANDER_CLK_EN_MASK,
WCD9335_CDC_COMPANDER_CLK_ENABLE);
/* Reset comander */
snd_soc_component_update_bits(component, comp_ctl0_reg,
WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE);
snd_soc_component_update_bits(component, comp_ctl0_reg,
WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE);
/* Enables DRE in this path */
snd_soc_component_update_bits(component, rx_path_cfg0_reg,
WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK,
WCD9335_CDC_RX_PATH_CFG_CMP_ENABLE);
}
if (SND_SOC_DAPM_EVENT_OFF(event)) {
snd_soc_component_update_bits(component, comp_ctl0_reg,
WCD9335_CDC_COMPANDER_HALT_MASK,
WCD9335_CDC_COMPANDER_HALT);
snd_soc_component_update_bits(component, rx_path_cfg0_reg,
WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK,
WCD9335_CDC_RX_PATH_CFG_CMP_DISABLE);
snd_soc_component_update_bits(component, comp_ctl0_reg,
WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE);
snd_soc_component_update_bits(component, comp_ctl0_reg,
WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE);
snd_soc_component_update_bits(component, comp_ctl0_reg,
WCD9335_CDC_COMPANDER_CLK_EN_MASK,
WCD9335_CDC_COMPANDER_CLK_DISABLE);
snd_soc_component_update_bits(component, comp_ctl0_reg,
WCD9335_CDC_COMPANDER_HALT_MASK,
WCD9335_CDC_COMPANDER_NOHALT);
}
return 0;
}
static int wcd9335_codec_enable_interpolator(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kc, int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
u16 gain_reg;
u16 reg;
int val;
int offset_val = 0;
if (!(strcmp(w->name, "RX INT0 INTERP"))) {
reg = WCD9335_CDC_RX0_RX_PATH_CTL;
gain_reg = WCD9335_CDC_RX0_RX_VOL_CTL;
} else if (!(strcmp(w->name, "RX INT1 INTERP"))) {
reg = WCD9335_CDC_RX1_RX_PATH_CTL;
gain_reg = WCD9335_CDC_RX1_RX_VOL_CTL;
} else if (!(strcmp(w->name, "RX INT2 INTERP"))) {
reg = WCD9335_CDC_RX2_RX_PATH_CTL;
gain_reg = WCD9335_CDC_RX2_RX_VOL_CTL;
} else if (!(strcmp(w->name, "RX INT3 INTERP"))) {
reg = WCD9335_CDC_RX3_RX_PATH_CTL;
gain_reg = WCD9335_CDC_RX3_RX_VOL_CTL;
} else if (!(strcmp(w->name, "RX INT4 INTERP"))) {
reg = WCD9335_CDC_RX4_RX_PATH_CTL;
gain_reg = WCD9335_CDC_RX4_RX_VOL_CTL;
} else if (!(strcmp(w->name, "RX INT5 INTERP"))) {
reg = WCD9335_CDC_RX5_RX_PATH_CTL;
gain_reg = WCD9335_CDC_RX5_RX_VOL_CTL;
} else if (!(strcmp(w->name, "RX INT6 INTERP"))) {
reg = WCD9335_CDC_RX6_RX_PATH_CTL;
gain_reg = WCD9335_CDC_RX6_RX_VOL_CTL;
} else if (!(strcmp(w->name, "RX INT7 INTERP"))) {
reg = WCD9335_CDC_RX7_RX_PATH_CTL;
gain_reg = WCD9335_CDC_RX7_RX_VOL_CTL;
} else if (!(strcmp(w->name, "RX INT8 INTERP"))) {
reg = WCD9335_CDC_RX8_RX_PATH_CTL;
gain_reg = WCD9335_CDC_RX8_RX_VOL_CTL;
} else {
dev_err(comp->dev, "%s: Interpolator reg not found\n",
__func__);
return -EINVAL;
}
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* Reset if needed */
wcd9335_codec_enable_prim_interpolator(comp, reg, event);
break;
case SND_SOC_DAPM_POST_PMU:
wcd9335_config_compander(comp, w->shift, event);
val = snd_soc_component_read(comp, gain_reg);
val += offset_val;
snd_soc_component_write(comp, gain_reg, val);
break;
case SND_SOC_DAPM_POST_PMD:
wcd9335_config_compander(comp, w->shift, event);
wcd9335_codec_enable_prim_interpolator(comp, reg, event);
break;
}
return 0;
}
static void wcd9335_codec_hph_mode_gain_opt(struct snd_soc_component *component,
u8 gain)
{
struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
u8 hph_l_en, hph_r_en;
u8 l_val, r_val;
u8 hph_pa_status;
bool is_hphl_pa, is_hphr_pa;
hph_pa_status = snd_soc_component_read(component, WCD9335_ANA_HPH);
is_hphl_pa = hph_pa_status >> 7;
is_hphr_pa = (hph_pa_status & 0x40) >> 6;
hph_l_en = snd_soc_component_read(component, WCD9335_HPH_L_EN);
hph_r_en = snd_soc_component_read(component, WCD9335_HPH_R_EN);
l_val = (hph_l_en & 0xC0) | 0x20 | gain;
r_val = (hph_r_en & 0xC0) | 0x20 | gain;
/*
* Set HPH_L & HPH_R gain source selection to REGISTER
* for better click and pop only if corresponding PAs are
* not enabled. Also cache the values of the HPHL/R
* PA gains to be applied after PAs are enabled
*/
if ((l_val != hph_l_en) && !is_hphl_pa) {
snd_soc_component_write(component, WCD9335_HPH_L_EN, l_val);
wcd->hph_l_gain = hph_l_en & 0x1F;
}
if ((r_val != hph_r_en) && !is_hphr_pa) {
snd_soc_component_write(component, WCD9335_HPH_R_EN, r_val);
wcd->hph_r_gain = hph_r_en & 0x1F;
}
}
static void wcd9335_codec_hph_lohifi_config(struct snd_soc_component *comp,
int event)
{
if (SND_SOC_DAPM_EVENT_ON(event)) {
snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA,
WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK,
0x06);
snd_soc_component_update_bits(comp,
WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2,
0xF0, 0x40);
snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000);
snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE);
snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1,
WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
0x0C);
wcd9335_codec_hph_mode_gain_opt(comp, 0x11);
}
if (SND_SOC_DAPM_EVENT_OFF(event)) {
snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE);
snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500);
snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2,
0x8A);
snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA,
WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK,
0x0A);
}
}
static void wcd9335_codec_hph_lp_config(struct snd_soc_component *comp,
int event)
{
if (SND_SOC_DAPM_EVENT_ON(event)) {
snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1,
WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
0x0C);
wcd9335_codec_hph_mode_gain_opt(comp, 0x10);
snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000);
snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE);
snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK,
WCD9335_HPH_PA_CTL2_FORCE_PSRREH_ENABLE);
snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK,
WCD9335_HPH_PA_CTL2_HPH_PSRR_ENABLE);
snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL,
WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_MASK,
WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_V_N1P60);
snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL,
WCD9335_HPH_RDAC_1P65_LD_OUTCTL_MASK,
WCD9335_HPH_RDAC_1P65_LD_OUTCTL_V_N1P60);
snd_soc_component_update_bits(comp,
WCD9335_RX_BIAS_HPH_RDAC_LDO, 0x0F, 0x01);
snd_soc_component_update_bits(comp,
WCD9335_RX_BIAS_HPH_RDAC_LDO, 0xF0, 0x10);
}
if (SND_SOC_DAPM_EVENT_OFF(event)) {
snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDAC_LDO,
0x88);
snd_soc_component_write(comp, WCD9335_HPH_RDAC_LDO_CTL,
0x33);
snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK,
WCD9335_HPH_PA_CTL2_HPH_PSRR_DISABLE);
snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK,
WCD9335_HPH_PA_CTL2_FORCE_PSRREH_DISABLE);
snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE);
snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500);
snd_soc_component_update_bits(comp, WCD9335_HPH_R_EN,
WCD9335_HPH_CONST_SEL_L_MASK,
WCD9335_HPH_CONST_SEL_L_HQ_PATH);
snd_soc_component_update_bits(comp, WCD9335_HPH_L_EN,
WCD9335_HPH_CONST_SEL_L_MASK,
WCD9335_HPH_CONST_SEL_L_HQ_PATH);
}
}
static void wcd9335_codec_hph_hifi_config(struct snd_soc_component *comp,
int event)
{
if (SND_SOC_DAPM_EVENT_ON(event)) {
snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000);
snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE);
snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1,
WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
0x0C);
wcd9335_codec_hph_mode_gain_opt(comp, 0x11);
}
if (SND_SOC_DAPM_EVENT_OFF(event)) {
snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE);
snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500);
}
}
static void wcd9335_codec_hph_mode_config(struct snd_soc_component *component,
int event, int mode)
{
switch (mode) {
case CLS_H_LP:
wcd9335_codec_hph_lp_config(component, event);
break;
case CLS_H_LOHIFI:
wcd9335_codec_hph_lohifi_config(component, event);
break;
case CLS_H_HIFI:
wcd9335_codec_hph_hifi_config(component, event);
break;
}
}
static int wcd9335_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kc,
int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
int hph_mode = wcd->hph_mode;
u8 dem_inp;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* Read DEM INP Select */
dem_inp = snd_soc_component_read(comp,
WCD9335_CDC_RX1_RX_PATH_SEC0) & 0x03;
if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
(hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
dev_err(comp->dev, "Incorrect DEM Input\n");
return -EINVAL;
}
wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
WCD_CLSH_STATE_HPHL,
((hph_mode == CLS_H_LOHIFI) ?
CLS_H_HIFI : hph_mode));
wcd9335_codec_hph_mode_config(comp, event, hph_mode);
break;
case SND_SOC_DAPM_POST_PMU:
usleep_range(1000, 1100);
break;
case SND_SOC_DAPM_PRE_PMD:
break;
case SND_SOC_DAPM_POST_PMD:
/* 1000us required as per HW requirement */
usleep_range(1000, 1100);
if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) &
WCD_CLSH_STATE_HPHR))
wcd9335_codec_hph_mode_config(comp, event, hph_mode);
wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
WCD_CLSH_STATE_HPHL,
((hph_mode == CLS_H_LOHIFI) ?
CLS_H_HIFI : hph_mode));
break;
}
return 0;
}
static int wcd9335_codec_lineout_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kc, int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
WCD_CLSH_STATE_LO, CLS_AB);
break;
case SND_SOC_DAPM_POST_PMD:
wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
WCD_CLSH_STATE_LO, CLS_AB);
break;
}
return 0;
}
static int wcd9335_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kc, int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
break;
case SND_SOC_DAPM_POST_PMD:
wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
break;
}
return 0;
}
static void wcd9335_codec_hph_post_pa_config(struct wcd9335_codec *wcd,
int mode, int event)
{
u8 scale_val = 0;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
switch (mode) {
case CLS_H_HIFI:
scale_val = 0x3;
break;
case CLS_H_LOHIFI:
scale_val = 0x1;
break;
}
break;
case SND_SOC_DAPM_PRE_PMD:
scale_val = 0x6;
break;
}
if (scale_val)
snd_soc_component_update_bits(wcd->component,
WCD9335_HPH_PA_CTL1,
WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
scale_val << 1);
if (SND_SOC_DAPM_EVENT_ON(event)) {
if (wcd->comp_enabled[COMPANDER_1] ||
wcd->comp_enabled[COMPANDER_2]) {
/* GAIN Source Selection */
snd_soc_component_update_bits(wcd->component,
WCD9335_HPH_L_EN,
WCD9335_HPH_GAIN_SRC_SEL_MASK,
WCD9335_HPH_GAIN_SRC_SEL_COMPANDER);
snd_soc_component_update_bits(wcd->component,
WCD9335_HPH_R_EN,
WCD9335_HPH_GAIN_SRC_SEL_MASK,
WCD9335_HPH_GAIN_SRC_SEL_COMPANDER);
snd_soc_component_update_bits(wcd->component,
WCD9335_HPH_AUTO_CHOP,
WCD9335_HPH_AUTO_CHOP_MASK,
WCD9335_HPH_AUTO_CHOP_FORCE_ENABLE);
}
snd_soc_component_update_bits(wcd->component,
WCD9335_HPH_L_EN,
WCD9335_HPH_PA_GAIN_MASK,
wcd->hph_l_gain);
snd_soc_component_update_bits(wcd->component,
WCD9335_HPH_R_EN,
WCD9335_HPH_PA_GAIN_MASK,
wcd->hph_r_gain);
}
if (SND_SOC_DAPM_EVENT_OFF(event))
snd_soc_component_update_bits(wcd->component,
WCD9335_HPH_AUTO_CHOP,
WCD9335_HPH_AUTO_CHOP_MASK,
WCD9335_HPH_AUTO_CHOP_ENABLE_BY_CMPDR_GAIN);
}
static int wcd9335_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kc,
int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
int hph_mode = wcd->hph_mode;
u8 dem_inp;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* Read DEM INP Select */
dem_inp = snd_soc_component_read(comp,
WCD9335_CDC_RX2_RX_PATH_SEC0) &
WCD9335_CDC_RX_PATH_DEM_INP_SEL_MASK;
if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
(hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
dev_err(comp->dev, "DEM Input not set correctly, hph_mode: %d\n",
hph_mode);
return -EINVAL;
}
wcd_clsh_ctrl_set_state(wcd->clsh_ctrl,
WCD_CLSH_EVENT_PRE_DAC,
WCD_CLSH_STATE_HPHR,
((hph_mode == CLS_H_LOHIFI) ?
CLS_H_HIFI : hph_mode));
wcd9335_codec_hph_mode_config(comp, event, hph_mode);
break;
case SND_SOC_DAPM_POST_PMD:
/* 1000us required as per HW requirement */
usleep_range(1000, 1100);
if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) &
WCD_CLSH_STATE_HPHL))
wcd9335_codec_hph_mode_config(comp, event, hph_mode);
wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
WCD_CLSH_STATE_HPHR, ((hph_mode == CLS_H_LOHIFI) ?
CLS_H_HIFI : hph_mode));
break;
}
return 0;
}
static int wcd9335_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kc,
int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
int hph_mode = wcd->hph_mode;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
break;
case SND_SOC_DAPM_POST_PMU:
/*
* 7ms sleep is required after PA is enabled as per
* HW requirement
*/
usleep_range(7000, 7100);
wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
snd_soc_component_update_bits(comp,
WCD9335_CDC_RX1_RX_PATH_CTL,
WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
WCD9335_CDC_RX_PGA_MUTE_DISABLE);
/* Remove mix path mute if it is enabled */
if ((snd_soc_component_read(comp,
WCD9335_CDC_RX1_RX_PATH_MIX_CTL)) &
WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
snd_soc_component_update_bits(comp,
WCD9335_CDC_RX1_RX_PATH_MIX_CTL,
WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
WCD9335_CDC_RX_PGA_MUTE_DISABLE);
break;
case SND_SOC_DAPM_PRE_PMD:
wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
break;
case SND_SOC_DAPM_POST_PMD:
/* 5ms sleep is required after PA is disabled as per
* HW requirement
*/
usleep_range(5000, 5500);
break;
}
return 0;
}
static int wcd9335_codec_enable_lineout_pa(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kc,
int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
int vol_reg = 0, mix_vol_reg = 0;
if (w->reg == WCD9335_ANA_LO_1_2) {
if (w->shift == 7) {
vol_reg = WCD9335_CDC_RX3_RX_PATH_CTL;
mix_vol_reg = WCD9335_CDC_RX3_RX_PATH_MIX_CTL;
} else if (w->shift == 6) {
vol_reg = WCD9335_CDC_RX4_RX_PATH_CTL;
mix_vol_reg = WCD9335_CDC_RX4_RX_PATH_MIX_CTL;
}
} else if (w->reg == WCD9335_ANA_LO_3_4) {
if (w->shift == 7) {
vol_reg = WCD9335_CDC_RX5_RX_PATH_CTL;
mix_vol_reg = WCD9335_CDC_RX5_RX_PATH_MIX_CTL;
} else if (w->shift == 6) {
vol_reg = WCD9335_CDC_RX6_RX_PATH_CTL;
mix_vol_reg = WCD9335_CDC_RX6_RX_PATH_MIX_CTL;
}
} else {
dev_err(comp->dev, "Error enabling lineout PA\n");
return -EINVAL;
}
switch (event) {
case SND_SOC_DAPM_POST_PMU:
/* 5ms sleep is required after PA is enabled as per
* HW requirement
*/
usleep_range(5000, 5500);
snd_soc_component_update_bits(comp, vol_reg,
WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
WCD9335_CDC_RX_PGA_MUTE_DISABLE);
/* Remove mix path mute if it is enabled */
if ((snd_soc_component_read(comp, mix_vol_reg)) &
WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
snd_soc_component_update_bits(comp, mix_vol_reg,
WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
WCD9335_CDC_RX_PGA_MUTE_DISABLE);
break;
case SND_SOC_DAPM_POST_PMD:
/* 5ms sleep is required after PA is disabled as per
* HW requirement
*/
usleep_range(5000, 5500);
break;
}
return 0;
}
static void wcd9335_codec_init_flyback(struct snd_soc_component *component)
{
snd_soc_component_update_bits(component, WCD9335_HPH_L_EN,
WCD9335_HPH_CONST_SEL_L_MASK,
WCD9335_HPH_CONST_SEL_L_BYPASS);
snd_soc_component_update_bits(component, WCD9335_HPH_R_EN,
WCD9335_HPH_CONST_SEL_L_MASK,
WCD9335_HPH_CONST_SEL_L_BYPASS);
snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF,
WCD9335_RX_BIAS_FLYB_VPOS_5_UA_MASK,
WCD9335_RX_BIAS_FLYB_I_0P0_UA);
snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF,
WCD9335_RX_BIAS_FLYB_VNEG_5_UA_MASK,
WCD9335_RX_BIAS_FLYB_I_0P0_UA);
}
static int wcd9335_codec_enable_rx_bias(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kc, int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
wcd->rx_bias_count++;
if (wcd->rx_bias_count == 1) {
wcd9335_codec_init_flyback(comp);
snd_soc_component_update_bits(comp,
WCD9335_ANA_RX_SUPPLIES,
WCD9335_ANA_RX_BIAS_ENABLE_MASK,
WCD9335_ANA_RX_BIAS_ENABLE);
}
break;
case SND_SOC_DAPM_POST_PMD:
wcd->rx_bias_count--;
if (!wcd->rx_bias_count)
snd_soc_component_update_bits(comp,
WCD9335_ANA_RX_SUPPLIES,
WCD9335_ANA_RX_BIAS_ENABLE_MASK,
WCD9335_ANA_RX_BIAS_DISABLE);
break;
}
return 0;
}
static int wcd9335_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kc, int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
int hph_mode = wcd->hph_mode;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
break;
case SND_SOC_DAPM_POST_PMU:
/*
* 7ms sleep is required after PA is enabled as per
* HW requirement
*/
usleep_range(7000, 7100);
wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
snd_soc_component_update_bits(comp,
WCD9335_CDC_RX2_RX_PATH_CTL,
WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
WCD9335_CDC_RX_PGA_MUTE_DISABLE);
/* Remove mix path mute if it is enabled */
if ((snd_soc_component_read(comp,
WCD9335_CDC_RX2_RX_PATH_MIX_CTL)) &
WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
snd_soc_component_update_bits(comp,
WCD9335_CDC_RX2_RX_PATH_MIX_CTL,
WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
WCD9335_CDC_RX_PGA_MUTE_DISABLE);
break;
case SND_SOC_DAPM_PRE_PMD:
wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
break;
case SND_SOC_DAPM_POST_PMD:
/* 5ms sleep is required after PA is disabled as per
* HW requirement
*/
usleep_range(5000, 5500);
break;
}
return 0;
}
static int wcd9335_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kc, int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
/* 5ms sleep is required after PA is enabled as per
* HW requirement
*/
usleep_range(5000, 5500);
snd_soc_component_update_bits(comp,
WCD9335_CDC_RX0_RX_PATH_CTL,
WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
WCD9335_CDC_RX_PGA_MUTE_DISABLE);
/* Remove mix path mute if it is enabled */
if ((snd_soc_component_read(comp,
WCD9335_CDC_RX0_RX_PATH_MIX_CTL)) &
WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
snd_soc_component_update_bits(comp,
WCD9335_CDC_RX0_RX_PATH_MIX_CTL,
WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
WCD9335_CDC_RX_PGA_MUTE_DISABLE);
break;
case SND_SOC_DAPM_POST_PMD:
/* 5ms sleep is required after PA is disabled as per
* HW requirement
*/
usleep_range(5000, 5500);
break;
}
return 0;
}
static irqreturn_t wcd9335_slimbus_irq(int irq, void *data)
{
struct wcd9335_codec *wcd = data;
unsigned long status = 0;
int i, j, port_id;
unsigned int val, int_val = 0;
irqreturn_t ret = IRQ_NONE;
bool tx;
unsigned short reg = 0;
for (i = WCD9335_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0;
i <= WCD9335_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) {
regmap_read(wcd->if_regmap, i, &val);
status |= ((u32)val << (8 * j));
}
for_each_set_bit(j, &status, 32) {
tx = (j >= 16);
port_id = (tx ? j - 16 : j);
regmap_read(wcd->if_regmap,
WCD9335_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val);
if (val) {
if (!tx)
reg = WCD9335_SLIM_PGD_PORT_INT_EN0 +
(port_id / 8);
else
reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 +
(port_id / 8);
regmap_read(
wcd->if_regmap, reg, &int_val);
/*
* Ignore interrupts for ports for which the
* interrupts are not specifically enabled.
*/
if (!(int_val & (1 << (port_id % 8))))
continue;
}
if (val & WCD9335_SLIM_IRQ_OVERFLOW)
dev_err_ratelimited(wcd->dev,
"%s: overflow error on %s port %d, value %x\n",
__func__, (tx ? "TX" : "RX"), port_id, val);
if (val & WCD9335_SLIM_IRQ_UNDERFLOW)
dev_err_ratelimited(wcd->dev,
"%s: underflow error on %s port %d, value %x\n",
__func__, (tx ? "TX" : "RX"), port_id, val);
if ((val & WCD9335_SLIM_IRQ_OVERFLOW) ||
(val & WCD9335_SLIM_IRQ_UNDERFLOW)) {
if (!tx)
reg = WCD9335_SLIM_PGD_PORT_INT_EN0 +
(port_id / 8);
else
reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 +
(port_id / 8);
regmap_read(
wcd->if_regmap, reg, &int_val);
if (int_val & (1 << (port_id % 8))) {
int_val = int_val ^ (1 << (port_id % 8));
regmap_write(wcd->if_regmap,
reg, int_val);
}
}
regmap_write(wcd->if_regmap,
WCD9335_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8),
BIT(j % 8));
ret = IRQ_HANDLED;
}
return ret;
}
static struct wcd9335_irq wcd9335_irqs[] = {
{
.irq = WCD9335_IRQ_SLIMBUS,
.handler = wcd9335_slimbus_irq,
.name = "SLIM Slave",
},
};
static int wcd9335_setup_irqs(struct wcd9335_codec *wcd)
{
int irq, ret, i;
for (i = 0; i < ARRAY_SIZE(wcd9335_irqs); i++) {
irq = regmap_irq_get_virq(wcd->irq_data, wcd9335_irqs[i].irq);
if (irq < 0) {
dev_err(wcd->dev, "Failed to get %s\n",
wcd9335_irqs[i].name);
return irq;
}
ret = devm_request_threaded_irq(wcd->dev, irq, NULL,
wcd9335_irqs[i].handler,
IRQF_TRIGGER_RISING |
IRQF_ONESHOT,
wcd9335_irqs[i].name, wcd);
if (ret) {
dev_err(wcd->dev, "Failed to request %s\n",
wcd9335_irqs[i].name);
return ret;
}
}
/* enable interrupts on all slave ports */
for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++)
regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i,
0xFF);
return ret;
}
static void wcd9335_teardown_irqs(struct wcd9335_codec *wcd)
{
int i;
/* disable interrupts on all slave ports */
for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++)
regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i,
0x00);
}
static void wcd9335_cdc_sido_ccl_enable(struct wcd9335_codec *wcd,
bool ccl_flag)
{
struct snd_soc_component *comp = wcd->component;
if (ccl_flag) {
if (++wcd->sido_ccl_cnt == 1)
snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10,
WCD9335_SIDO_SIDO_CCL_DEF_VALUE);
} else {
if (wcd->sido_ccl_cnt == 0) {
dev_err(wcd->dev, "sido_ccl already disabled\n");
return;
}
if (--wcd->sido_ccl_cnt == 0)
snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10,
WCD9335_SIDO_SIDO_CCL_10_ICHARG_PWR_SEL_C320FF);
}
}
static int wcd9335_enable_master_bias(struct wcd9335_codec *wcd)
{
wcd->master_bias_users++;
if (wcd->master_bias_users == 1) {
regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
WCD9335_ANA_BIAS_EN_MASK,
WCD9335_ANA_BIAS_ENABLE);
regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
WCD9335_ANA_BIAS_PRECHRG_EN_MASK,
WCD9335_ANA_BIAS_PRECHRG_ENABLE);
/*
* 1ms delay is required after pre-charge is enabled
* as per HW requirement
*/
usleep_range(1000, 1100);
regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
WCD9335_ANA_BIAS_PRECHRG_EN_MASK,
WCD9335_ANA_BIAS_PRECHRG_DISABLE);
regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
WCD9335_ANA_BIAS_PRECHRG_CTL_MODE,
WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL);
}
return 0;
}
static int wcd9335_enable_mclk(struct wcd9335_codec *wcd)
{
/* Enable mclk requires master bias to be enabled first */
if (wcd->master_bias_users <= 0)
return -EINVAL;
if (((wcd->clk_mclk_users == 0) && (wcd->clk_type == WCD_CLK_MCLK)) ||
((wcd->clk_mclk_users > 0) && (wcd->clk_type != WCD_CLK_MCLK))) {
dev_err(wcd->dev, "Error enabling MCLK, clk_type: %d\n",
wcd->clk_type);
return -EINVAL;
}
if (++wcd->clk_mclk_users == 1) {
regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK,
WCD9335_ANA_CLK_EXT_CLKBUF_ENABLE);
regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
WCD9335_ANA_CLK_MCLK_SRC_MASK,
WCD9335_ANA_CLK_MCLK_SRC_EXTERNAL);
regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
WCD9335_ANA_CLK_MCLK_EN_MASK,
WCD9335_ANA_CLK_MCLK_ENABLE);
regmap_update_bits(wcd->regmap,
WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL,
WCD9335_CDC_CLK_RST_CTRL_FS_CNT_EN_MASK,
WCD9335_CDC_CLK_RST_CTRL_FS_CNT_ENABLE);
regmap_update_bits(wcd->regmap,
WCD9335_CDC_CLK_RST_CTRL_MCLK_CONTROL,
WCD9335_CDC_CLK_RST_CTRL_MCLK_EN_MASK,
WCD9335_CDC_CLK_RST_CTRL_MCLK_ENABLE);
/*
* 10us sleep is required after clock is enabled
* as per HW requirement
*/
usleep_range(10, 15);
}
wcd->clk_type = WCD_CLK_MCLK;
return 0;
}
static int wcd9335_disable_mclk(struct wcd9335_codec *wcd)
{
if (wcd->clk_mclk_users <= 0)
return -EINVAL;
if (--wcd->clk_mclk_users == 0) {
if (wcd->clk_rco_users > 0) {
/* MCLK to RCO switch */
regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
WCD9335_ANA_CLK_MCLK_SRC_MASK,
WCD9335_ANA_CLK_MCLK_SRC_RCO);
wcd->clk_type = WCD_CLK_RCO;
} else {
regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
WCD9335_ANA_CLK_MCLK_EN_MASK,
WCD9335_ANA_CLK_MCLK_DISABLE);
wcd->clk_type = WCD_CLK_OFF;
}
regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK,
WCD9335_ANA_CLK_EXT_CLKBUF_DISABLE);
}
return 0;
}
static int wcd9335_disable_master_bias(struct wcd9335_codec *wcd)
{
if (wcd->master_bias_users <= 0)
return -EINVAL;
wcd->master_bias_users--;
if (wcd->master_bias_users == 0) {
regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
WCD9335_ANA_BIAS_EN_MASK,
WCD9335_ANA_BIAS_DISABLE);
regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
WCD9335_ANA_BIAS_PRECHRG_CTL_MODE,
WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL);
}
return 0;
}
static int wcd9335_cdc_req_mclk_enable(struct wcd9335_codec *wcd,
bool enable)
{
int ret = 0;
if (enable) {
wcd9335_cdc_sido_ccl_enable(wcd, true);
ret = clk_prepare_enable(wcd->mclk);
if (ret) {
dev_err(wcd->dev, "%s: ext clk enable failed\n",
__func__);
goto err;
}
/* get BG */
wcd9335_enable_master_bias(wcd);
/* get MCLK */
wcd9335_enable_mclk(wcd);
} else {
/* put MCLK */
wcd9335_disable_mclk(wcd);
/* put BG */
wcd9335_disable_master_bias(wcd);
clk_disable_unprepare(wcd->mclk);
wcd9335_cdc_sido_ccl_enable(wcd, false);
}
err:
return ret;
}
static void wcd9335_codec_apply_sido_voltage(struct wcd9335_codec *wcd,
enum wcd9335_sido_voltage req_mv)
{
struct snd_soc_component *comp = wcd->component;
int vout_d_val;
if (req_mv == wcd->sido_voltage)
return;
/* compute the vout_d step value */
vout_d_val = WCD9335_CALCULATE_VOUT_D(req_mv) &
WCD9335_ANA_BUCK_VOUT_MASK;
snd_soc_component_write(comp, WCD9335_ANA_BUCK_VOUT_D, vout_d_val);
snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL,
WCD9335_ANA_BUCK_CTL_RAMP_START_MASK,
WCD9335_ANA_BUCK_CTL_RAMP_START_ENABLE);
/* 1 msec sleep required after SIDO Vout_D voltage change */
usleep_range(1000, 1100);
wcd->sido_voltage = req_mv;
snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL,
WCD9335_ANA_BUCK_CTL_RAMP_START_MASK,
WCD9335_ANA_BUCK_CTL_RAMP_START_DISABLE);
}
static int wcd9335_codec_update_sido_voltage(struct wcd9335_codec *wcd,
enum wcd9335_sido_voltage req_mv)
{
int ret = 0;
/* enable mclk before setting SIDO voltage */
ret = wcd9335_cdc_req_mclk_enable(wcd, true);
if (ret) {
dev_err(wcd->dev, "Ext clk enable failed\n");
goto err;
}
wcd9335_codec_apply_sido_voltage(wcd, req_mv);
wcd9335_cdc_req_mclk_enable(wcd, false);
err:
return ret;
}
static int _wcd9335_codec_enable_mclk(struct snd_soc_component *component,
int enable)
{
struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
int ret;
if (enable) {
ret = wcd9335_cdc_req_mclk_enable(wcd, true);
if (ret)
return ret;
wcd9335_codec_apply_sido_voltage(wcd,
SIDO_VOLTAGE_NOMINAL_MV);
} else {
wcd9335_codec_update_sido_voltage(wcd,
wcd->sido_voltage);
wcd9335_cdc_req_mclk_enable(wcd, false);
}
return 0;
}
static int wcd9335_codec_enable_mclk(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kc, int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
return _wcd9335_codec_enable_mclk(comp, true);
case SND_SOC_DAPM_POST_PMD:
return _wcd9335_codec_enable_mclk(comp, false);
}
return 0;
}
static const struct snd_soc_dapm_widget wcd9335_dapm_widgets[] = {
/* TODO SPK1 & SPK2 OUT*/
SND_SOC_DAPM_OUTPUT("EAR"),
SND_SOC_DAPM_OUTPUT("HPHL"),
SND_SOC_DAPM_OUTPUT("HPHR"),
SND_SOC_DAPM_OUTPUT("LINEOUT1"),
SND_SOC_DAPM_OUTPUT("LINEOUT2"),
SND_SOC_DAPM_OUTPUT("LINEOUT3"),
SND_SOC_DAPM_OUTPUT("LINEOUT4"),
SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM,
AIF1_PB, 0, wcd9335_codec_enable_slim,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM,
AIF2_PB, 0, wcd9335_codec_enable_slim,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM,
AIF3_PB, 0, wcd9335_codec_enable_slim,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM,
AIF4_PB, 0, wcd9335_codec_enable_slim,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD9335_RX0, 0,
&slim_rx_mux[WCD9335_RX0]),
SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD9335_RX1, 0,
&slim_rx_mux[WCD9335_RX1]),
SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD9335_RX2, 0,
&slim_rx_mux[WCD9335_RX2]),
SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD9335_RX3, 0,
&slim_rx_mux[WCD9335_RX3]),
SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD9335_RX4, 0,
&slim_rx_mux[WCD9335_RX4]),
SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD9335_RX5, 0,
&slim_rx_mux[WCD9335_RX5]),
SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD9335_RX6, 0,
&slim_rx_mux[WCD9335_RX6]),
SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD9335_RX7, 0,
&slim_rx_mux[WCD9335_RX7]),
SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", WCD9335_CDC_RX0_RX_PATH_MIX_CTL,
5, 0, &rx_int0_2_mux, wcd9335_codec_enable_mix_path,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", WCD9335_CDC_RX1_RX_PATH_MIX_CTL,
5, 0, &rx_int1_2_mux, wcd9335_codec_enable_mix_path,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", WCD9335_CDC_RX2_RX_PATH_MIX_CTL,
5, 0, &rx_int2_2_mux, wcd9335_codec_enable_mix_path,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", WCD9335_CDC_RX3_RX_PATH_MIX_CTL,
5, 0, &rx_int3_2_mux, wcd9335_codec_enable_mix_path,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", WCD9335_CDC_RX4_RX_PATH_MIX_CTL,
5, 0, &rx_int4_2_mux, wcd9335_codec_enable_mix_path,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_MUX_E("RX INT5_2 MUX", WCD9335_CDC_RX5_RX_PATH_MIX_CTL,
5, 0, &rx_int5_2_mux, wcd9335_codec_enable_mix_path,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_MUX_E("RX INT6_2 MUX", WCD9335_CDC_RX6_RX_PATH_MIX_CTL,
5, 0, &rx_int6_2_mux, wcd9335_codec_enable_mix_path,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", WCD9335_CDC_RX7_RX_PATH_MIX_CTL,
5, 0, &rx_int7_2_mux, wcd9335_codec_enable_mix_path,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", WCD9335_CDC_RX8_RX_PATH_MIX_CTL,
5, 0, &rx_int8_2_mux, wcd9335_codec_enable_mix_path,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
&rx_int0_1_mix_inp0_mux),
SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
&rx_int0_1_mix_inp1_mux),
SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
&rx_int0_1_mix_inp2_mux),
SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
&rx_int1_1_mix_inp0_mux),
SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
&rx_int1_1_mix_inp1_mux),
SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
&rx_int1_1_mix_inp2_mux),
SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
&rx_int2_1_mix_inp0_mux),
SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
&rx_int2_1_mix_inp1_mux),
SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
&rx_int2_1_mix_inp2_mux),
SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
&rx_int3_1_mix_inp0_mux),
SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
&rx_int3_1_mix_inp1_mux),
SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
&rx_int3_1_mix_inp2_mux),
SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
&rx_int4_1_mix_inp0_mux),
SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
&rx_int4_1_mix_inp1_mux),
SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
&rx_int4_1_mix_inp2_mux),
SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
&rx_int5_1_mix_inp0_mux),
SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
&rx_int5_1_mix_inp1_mux),
SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
&rx_int5_1_mix_inp2_mux),
SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
&rx_int6_1_mix_inp0_mux),
SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
&rx_int6_1_mix_inp1_mux),
SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
&rx_int6_1_mix_inp2_mux),
SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
&rx_int7_1_mix_inp0_mux),
SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
&rx_int7_1_mix_inp1_mux),
SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
&rx_int7_1_mix_inp2_mux),
SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
&rx_int8_1_mix_inp0_mux),
SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
&rx_int8_1_mix_inp1_mux),
SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
&rx_int8_1_mix_inp2_mux),
SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT5_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT5 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT6_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT6 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT5 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT6 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT8 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
&rx_int0_dem_inp_mux),
SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
&rx_int1_dem_inp_mux),
SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0,
&rx_int2_dem_inp_mux),
SND_SOC_DAPM_MUX_E("RX INT0 INTERP", SND_SOC_NOPM,
INTERP_EAR, 0, &rx_int0_interp_mux,
wcd9335_codec_enable_interpolator,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("RX INT1 INTERP", SND_SOC_NOPM,
INTERP_HPHL, 0, &rx_int1_interp_mux,
wcd9335_codec_enable_interpolator,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("RX INT2 INTERP", SND_SOC_NOPM,
INTERP_HPHR, 0, &rx_int2_interp_mux,
wcd9335_codec_enable_interpolator,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("RX INT3 INTERP", SND_SOC_NOPM,
INTERP_LO1, 0, &rx_int3_interp_mux,
wcd9335_codec_enable_interpolator,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("RX INT4 INTERP", SND_SOC_NOPM,
INTERP_LO2, 0, &rx_int4_interp_mux,
wcd9335_codec_enable_interpolator,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("RX INT5 INTERP", SND_SOC_NOPM,
INTERP_LO3, 0, &rx_int5_interp_mux,
wcd9335_codec_enable_interpolator,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("RX INT6 INTERP", SND_SOC_NOPM,
INTERP_LO4, 0, &rx_int6_interp_mux,
wcd9335_codec_enable_interpolator,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("RX INT7 INTERP", SND_SOC_NOPM,
INTERP_SPKR1, 0, &rx_int7_interp_mux,
wcd9335_codec_enable_interpolator,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("RX INT8 INTERP", SND_SOC_NOPM,
INTERP_SPKR2, 0, &rx_int8_interp_mux,
wcd9335_codec_enable_interpolator,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM,
0, 0, wcd9335_codec_ear_dac_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD9335_ANA_HPH,
5, 0, wcd9335_codec_hphl_dac_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD9335_ANA_HPH,
4, 0, wcd9335_codec_hphr_dac_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM,
0, 0, wcd9335_codec_lineout_dac_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM,
0, 0, wcd9335_codec_lineout_dac_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_DAC_E("RX INT5 DAC", NULL, SND_SOC_NOPM,
0, 0, wcd9335_codec_lineout_dac_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_DAC_E("RX INT6 DAC", NULL, SND_SOC_NOPM,
0, 0, wcd9335_codec_lineout_dac_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("HPHL PA", WCD9335_ANA_HPH, 7, 0, NULL, 0,
wcd9335_codec_enable_hphl_pa,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("HPHR PA", WCD9335_ANA_HPH, 6, 0, NULL, 0,
wcd9335_codec_enable_hphr_pa,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("EAR PA", WCD9335_ANA_EAR, 7, 0, NULL, 0,
wcd9335_codec_enable_ear_pa,
SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD9335_ANA_LO_1_2, 7, 0, NULL, 0,
wcd9335_codec_enable_lineout_pa,
SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD9335_ANA_LO_1_2, 6, 0, NULL, 0,
wcd9335_codec_enable_lineout_pa,
SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("LINEOUT3 PA", WCD9335_ANA_LO_3_4, 7, 0, NULL, 0,
wcd9335_codec_enable_lineout_pa,
SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("LINEOUT4 PA", WCD9335_ANA_LO_3_4, 6, 0, NULL, 0,
wcd9335_codec_enable_lineout_pa,
SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("RX_BIAS", SND_SOC_NOPM, 0, 0,
wcd9335_codec_enable_rx_bias, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
wcd9335_codec_enable_mclk, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMD),
/* TX */
SND_SOC_DAPM_INPUT("AMIC1"),
SND_SOC_DAPM_INPUT("AMIC2"),
SND_SOC_DAPM_INPUT("AMIC3"),
SND_SOC_DAPM_INPUT("AMIC4"),
SND_SOC_DAPM_INPUT("AMIC5"),
SND_SOC_DAPM_INPUT("AMIC6"),
SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM,
AIF1_CAP, 0, wcd9335_codec_enable_slim,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM,
AIF2_CAP, 0, wcd9335_codec_enable_slim,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM,
AIF3_CAP, 0, wcd9335_codec_enable_slim,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
wcd9335_codec_enable_micbias,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
wcd9335_codec_enable_micbias,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
wcd9335_codec_enable_micbias,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0,
wcd9335_codec_enable_micbias,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD9335_ANA_AMIC1, 7, 0,
wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD9335_ANA_AMIC2, 7, 0,
wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD9335_ANA_AMIC3, 7, 0,
wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD9335_ANA_AMIC4, 7, 0,
wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_ADC_E("ADC5", NULL, WCD9335_ANA_AMIC5, 7, 0,
wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_ADC_E("ADC6", NULL, WCD9335_ANA_AMIC6, 7, 0,
wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
/* Digital Mic Inputs */
SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0,
wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0,
wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0,
wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0,
wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0,
&tx_dmic_mux0),
SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0,
&tx_dmic_mux1),
SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0,
&tx_dmic_mux2),
SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0,
&tx_dmic_mux3),
SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0,
&tx_dmic_mux4),
SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0,
&tx_dmic_mux5),
SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0,
&tx_dmic_mux6),
SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0,
&tx_dmic_mux7),
SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0,
&tx_dmic_mux8),
SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0,
&tx_amic_mux0),
SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0,
&tx_amic_mux1),
SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0,
&tx_amic_mux2),
SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0,
&tx_amic_mux3),
SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0,
&tx_amic_mux4),
SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0,
&tx_amic_mux5),
SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0,
&tx_amic_mux6),
SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0,
&tx_amic_mux7),
SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0,
&tx_amic_mux8),
SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0,
aif1_cap_mixer, ARRAY_SIZE(aif1_cap_mixer)),
SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0,
aif2_cap_mixer, ARRAY_SIZE(aif2_cap_mixer)),
SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0,
aif3_cap_mixer, ARRAY_SIZE(aif3_cap_mixer)),
SND_SOC_DAPM_MUX("SLIM TX0 MUX", SND_SOC_NOPM, WCD9335_TX0, 0,
&sb_tx0_mux),
SND_SOC_DAPM_MUX("SLIM TX1 MUX", SND_SOC_NOPM, WCD9335_TX1, 0,
&sb_tx1_mux),
SND_SOC_DAPM_MUX("SLIM TX2 MUX", SND_SOC_NOPM, WCD9335_TX2, 0,
&sb_tx2_mux),
SND_SOC_DAPM_MUX("SLIM TX3 MUX", SND_SOC_NOPM, WCD9335_TX3, 0,
&sb_tx3_mux),
SND_SOC_DAPM_MUX("SLIM TX4 MUX", SND_SOC_NOPM, WCD9335_TX4, 0,
&sb_tx4_mux),
SND_SOC_DAPM_MUX("SLIM TX5 MUX", SND_SOC_NOPM, WCD9335_TX5, 0,
&sb_tx5_mux),
SND_SOC_DAPM_MUX("SLIM TX6 MUX", SND_SOC_NOPM, WCD9335_TX6, 0,
&sb_tx6_mux),
SND_SOC_DAPM_MUX("SLIM TX7 MUX", SND_SOC_NOPM, WCD9335_TX7, 0,
&sb_tx7_mux),
SND_SOC_DAPM_MUX("SLIM TX8 MUX", SND_SOC_NOPM, WCD9335_TX8, 0,
&sb_tx8_mux),
SND_SOC_DAPM_MUX_E("ADC MUX0", WCD9335_CDC_TX0_TX_PATH_CTL, 5, 0,
&tx_adc_mux0, wcd9335_codec_enable_dec,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("ADC MUX1", WCD9335_CDC_TX1_TX_PATH_CTL, 5, 0,
&tx_adc_mux1, wcd9335_codec_enable_dec,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("ADC MUX2", WCD9335_CDC_TX2_TX_PATH_CTL, 5, 0,
&tx_adc_mux2, wcd9335_codec_enable_dec,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("ADC MUX3", WCD9335_CDC_TX3_TX_PATH_CTL, 5, 0,
&tx_adc_mux3, wcd9335_codec_enable_dec,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("ADC MUX4", WCD9335_CDC_TX4_TX_PATH_CTL, 5, 0,
&tx_adc_mux4, wcd9335_codec_enable_dec,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("ADC MUX5", WCD9335_CDC_TX5_TX_PATH_CTL, 5, 0,
&tx_adc_mux5, wcd9335_codec_enable_dec,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("ADC MUX6", WCD9335_CDC_TX6_TX_PATH_CTL, 5, 0,
&tx_adc_mux6, wcd9335_codec_enable_dec,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("ADC MUX7", WCD9335_CDC_TX7_TX_PATH_CTL, 5, 0,
&tx_adc_mux7, wcd9335_codec_enable_dec,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("ADC MUX8", WCD9335_CDC_TX8_TX_PATH_CTL, 5, 0,
&tx_adc_mux8, wcd9335_codec_enable_dec,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
};
static void wcd9335_enable_sido_buck(struct snd_soc_component *component)
{
struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
snd_soc_component_update_bits(component, WCD9335_ANA_RCO,
WCD9335_ANA_RCO_BG_EN_MASK,
WCD9335_ANA_RCO_BG_ENABLE);
snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL,
WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_MASK,
WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_EXT);
/* 100us sleep needed after IREF settings */
usleep_range(100, 110);
snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL,
WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_MASK,
WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_EXT);
/* 100us sleep needed after VREF settings */
usleep_range(100, 110);
wcd->sido_input_src = SIDO_SOURCE_RCO_BG;
}
static int wcd9335_enable_efuse_sensing(struct snd_soc_component *comp)
{
_wcd9335_codec_enable_mclk(comp, true);
snd_soc_component_update_bits(comp,
WCD9335_CHIP_TIER_CTRL_EFUSE_CTL,
WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK,
WCD9335_CHIP_TIER_CTRL_EFUSE_ENABLE);
/*
* 5ms sleep required after enabling efuse control
* before checking the status.
*/
usleep_range(5000, 5500);
if (!(snd_soc_component_read(comp,
WCD9335_CHIP_TIER_CTRL_EFUSE_STATUS) &
WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK))
WARN(1, "%s: Efuse sense is not complete\n", __func__);
wcd9335_enable_sido_buck(comp);
_wcd9335_codec_enable_mclk(comp, false);
return 0;
}
static void wcd9335_codec_init(struct snd_soc_component *component)
{
struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
int i;
/* ungate MCLK and set clk rate */
regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_GATE,
WCD9335_CODEC_RPM_CLK_GATE_MCLK_GATE_MASK, 0);
regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_MCLK_CFG,
WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
for (i = 0; i < ARRAY_SIZE(wcd9335_codec_reg_init); i++)
snd_soc_component_update_bits(component,
wcd9335_codec_reg_init[i].reg,
wcd9335_codec_reg_init[i].mask,
wcd9335_codec_reg_init[i].val);
wcd9335_enable_efuse_sensing(component);
}
static int wcd9335_codec_probe(struct snd_soc_component *component)
{
struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
int ret;
int i;
snd_soc_component_init_regmap(component, wcd->regmap);
/* Class-H Init*/
wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, WCD9335);
if (IS_ERR(wcd->clsh_ctrl))
return PTR_ERR(wcd->clsh_ctrl);
/* Default HPH Mode to Class-H HiFi */
wcd->hph_mode = CLS_H_HIFI;
wcd->component = component;
wcd9335_codec_init(component);
for (i = 0; i < NUM_CODEC_DAIS; i++)
INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list);
ret = wcd9335_setup_irqs(wcd);
if (ret)
goto free_clsh_ctrl;
return 0;
free_clsh_ctrl:
wcd_clsh_ctrl_free(wcd->clsh_ctrl);
return ret;
}
static void wcd9335_codec_remove(struct snd_soc_component *comp)
{
struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
wcd_clsh_ctrl_free(wcd->clsh_ctrl);
wcd9335_teardown_irqs(wcd);
}
static int wcd9335_codec_set_sysclk(struct snd_soc_component *comp,
int clk_id, int source,
unsigned int freq, int dir)
{
struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
wcd->mclk_rate = freq;
if (wcd->mclk_rate == WCD9335_MCLK_CLK_12P288MHZ)
snd_soc_component_update_bits(comp,
WCD9335_CODEC_RPM_CLK_MCLK_CFG,
WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
WCD9335_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ);
else if (wcd->mclk_rate == WCD9335_MCLK_CLK_9P6MHZ)
snd_soc_component_update_bits(comp,
WCD9335_CODEC_RPM_CLK_MCLK_CFG,
WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
return clk_set_rate(wcd->mclk, freq);
}
static const struct snd_soc_component_driver wcd9335_component_drv = {
.probe = wcd9335_codec_probe,
.remove = wcd9335_codec_remove,
.set_sysclk = wcd9335_codec_set_sysclk,
.controls = wcd9335_snd_controls,
.num_controls = ARRAY_SIZE(wcd9335_snd_controls),
.dapm_widgets = wcd9335_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wcd9335_dapm_widgets),
.dapm_routes = wcd9335_audio_map,
.num_dapm_routes = ARRAY_SIZE(wcd9335_audio_map),
.endianness = 1,
};
static int wcd9335_probe(struct wcd9335_codec *wcd)
{
struct device *dev = wcd->dev;
memcpy(wcd->rx_chs, wcd9335_rx_chs, sizeof(wcd9335_rx_chs));
memcpy(wcd->tx_chs, wcd9335_tx_chs, sizeof(wcd9335_tx_chs));
wcd->sido_input_src = SIDO_SOURCE_INTERNAL;
wcd->sido_voltage = SIDO_VOLTAGE_NOMINAL_MV;
return devm_snd_soc_register_component(dev, &wcd9335_component_drv,
wcd9335_slim_dais,
ARRAY_SIZE(wcd9335_slim_dais));
}
static const struct regmap_range_cfg wcd9335_ranges[] = {
{
.name = "WCD9335",
.range_min = 0x0,
.range_max = WCD9335_MAX_REGISTER,
.selector_reg = WCD9335_SEL_REGISTER,
.selector_mask = 0xff,
.selector_shift = 0,
.window_start = 0x800,
.window_len = 0x100,
},
};
static bool wcd9335_is_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case WCD9335_INTR_PIN1_STATUS0...WCD9335_INTR_PIN2_CLEAR3:
case WCD9335_ANA_MBHC_RESULT_3:
case WCD9335_ANA_MBHC_RESULT_2:
case WCD9335_ANA_MBHC_RESULT_1:
case WCD9335_ANA_MBHC_MECH:
case WCD9335_ANA_MBHC_ELECT:
case WCD9335_ANA_MBHC_ZDET:
case WCD9335_ANA_MICB2:
case WCD9335_ANA_RCO:
case WCD9335_ANA_BIAS:
return true;
default:
return false;
}
}
static struct regmap_config wcd9335_regmap_config = {
.reg_bits = 16,
.val_bits = 8,
.cache_type = REGCACHE_MAPLE,
.max_register = WCD9335_MAX_REGISTER,
.can_multi_write = true,
.ranges = wcd9335_ranges,
.num_ranges = ARRAY_SIZE(wcd9335_ranges),
.volatile_reg = wcd9335_is_volatile_register,
};
static const struct regmap_range_cfg wcd9335_ifc_ranges[] = {
{
.name = "WCD9335-IFC-DEV",
.range_min = 0x0,
.range_max = WCD9335_MAX_REGISTER,
.selector_reg = WCD9335_SEL_REGISTER,
.selector_mask = 0xfff,
.selector_shift = 0,
.window_start = 0x800,
.window_len = 0x400,
},
};
static struct regmap_config wcd9335_ifc_regmap_config = {
.reg_bits = 16,
.val_bits = 8,
.can_multi_write = true,
.max_register = WCD9335_MAX_REGISTER,
.ranges = wcd9335_ifc_ranges,
.num_ranges = ARRAY_SIZE(wcd9335_ifc_ranges),
};
static const struct regmap_irq wcd9335_codec_irqs[] = {
/* INTR_REG 0 */
[WCD9335_IRQ_SLIMBUS] = {
.reg_offset = 0,
.mask = BIT(0),
.type = {
.type_reg_offset = 0,
.types_supported = IRQ_TYPE_EDGE_BOTH,
.type_reg_mask = BIT(0),
},
},
};
static const unsigned int wcd9335_config_regs[] = {
WCD9335_INTR_LEVEL0,
};
static const struct regmap_irq_chip wcd9335_regmap_irq1_chip = {
.name = "wcd9335_pin1_irq",
.status_base = WCD9335_INTR_PIN1_STATUS0,
.mask_base = WCD9335_INTR_PIN1_MASK0,
.ack_base = WCD9335_INTR_PIN1_CLEAR0,
.num_regs = 4,
.irqs = wcd9335_codec_irqs,
.num_irqs = ARRAY_SIZE(wcd9335_codec_irqs),
.config_base = wcd9335_config_regs,
.num_config_bases = ARRAY_SIZE(wcd9335_config_regs),
.num_config_regs = 4,
.set_type_config = regmap_irq_set_type_config_simple,
};
static int wcd9335_parse_dt(struct wcd9335_codec *wcd)
{
struct device *dev = wcd->dev;
struct device_node *np = dev->of_node;
int ret;
wcd->reset_gpio = of_get_named_gpio(np, "reset-gpios", 0);
if (wcd->reset_gpio < 0) {
dev_err(dev, "Reset GPIO missing from DT\n");
return wcd->reset_gpio;
}
wcd->mclk = devm_clk_get(dev, "mclk");
if (IS_ERR(wcd->mclk)) {
dev_err(dev, "mclk not found\n");
return PTR_ERR(wcd->mclk);
}
wcd->native_clk = devm_clk_get(dev, "slimbus");
if (IS_ERR(wcd->native_clk)) {
dev_err(dev, "slimbus clock not found\n");
return PTR_ERR(wcd->native_clk);
}
wcd->supplies[0].supply = "vdd-buck";
wcd->supplies[1].supply = "vdd-buck-sido";
wcd->supplies[2].supply = "vdd-tx";
wcd->supplies[3].supply = "vdd-rx";
wcd->supplies[4].supply = "vdd-io";
ret = regulator_bulk_get(dev, WCD9335_MAX_SUPPLY, wcd->supplies);
if (ret) {
dev_err(dev, "Failed to get supplies: err = %d\n", ret);
return ret;
}
return 0;
}
static int wcd9335_power_on_reset(struct wcd9335_codec *wcd)
{
struct device *dev = wcd->dev;
int ret;
ret = regulator_bulk_enable(WCD9335_MAX_SUPPLY, wcd->supplies);
if (ret) {
dev_err(dev, "Failed to get supplies: err = %d\n", ret);
return ret;
}
/*
* For WCD9335, it takes about 600us for the Vout_A and
* Vout_D to be ready after BUCK_SIDO is powered up.
* SYS_RST_N shouldn't be pulled high during this time
* Toggle the reset line to make sure the reset pulse is
* correctly applied
*/
usleep_range(600, 650);
gpio_direction_output(wcd->reset_gpio, 0);
msleep(20);
gpio_set_value(wcd->reset_gpio, 1);
msleep(20);
return 0;
}
static int wcd9335_bring_up(struct wcd9335_codec *wcd)
{
struct regmap *rm = wcd->regmap;
int val, byte0;
regmap_read(rm, WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0, &val);
regmap_read(rm, WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0, &byte0);
if ((val < 0) || (byte0 < 0)) {
dev_err(wcd->dev, "WCD9335 CODEC version detection fail!\n");
return -EINVAL;
}
if (byte0 == 0x1) {
dev_info(wcd->dev, "WCD9335 CODEC version is v2.0\n");
wcd->version = WCD9335_VERSION_2_0;
regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x01);
regmap_write(rm, WCD9335_SIDO_SIDO_TEST_2, 0x00);
regmap_write(rm, WCD9335_SIDO_SIDO_CCL_8, 0x6F);
regmap_write(rm, WCD9335_BIAS_VBG_FINE_ADJ, 0x65);
regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x5);
regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x7);
regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x3);
regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x3);
} else {
dev_err(wcd->dev, "WCD9335 CODEC version not supported\n");
return -EINVAL;
}
return 0;
}
static int wcd9335_irq_init(struct wcd9335_codec *wcd)
{
int ret;
/*
* INTR1 consists of all possible interrupt sources Ear OCP,
* HPH OCP, MBHC, MAD, VBAT, and SVA
* INTR2 is a subset of first interrupt sources MAD, VBAT, and SVA
*/
wcd->intr1 = of_irq_get_byname(wcd->dev->of_node, "intr1");
if (wcd->intr1 < 0)
return dev_err_probe(wcd->dev, wcd->intr1,
"Unable to configure IRQ\n");
ret = devm_regmap_add_irq_chip(wcd->dev, wcd->regmap, wcd->intr1,
IRQF_TRIGGER_HIGH, 0,
&wcd9335_regmap_irq1_chip, &wcd->irq_data);
if (ret)
return dev_err_probe(wcd->dev, ret, "Failed to register IRQ chip\n");
return 0;
}
static int wcd9335_slim_probe(struct slim_device *slim)
{
struct device *dev = &slim->dev;
struct wcd9335_codec *wcd;
int ret;
wcd = devm_kzalloc(dev, sizeof(*wcd), GFP_KERNEL);
if (!wcd)
return -ENOMEM;
wcd->dev = dev;
ret = wcd9335_parse_dt(wcd);
if (ret) {
dev_err(dev, "Error parsing DT: %d\n", ret);
return ret;
}
ret = wcd9335_power_on_reset(wcd);
if (ret)
return ret;
dev_set_drvdata(dev, wcd);
return 0;
}
static int wcd9335_slim_status(struct slim_device *sdev,
enum slim_device_status status)
{
struct device *dev = &sdev->dev;
struct device_node *ifc_dev_np;
struct wcd9335_codec *wcd;
int ret;
wcd = dev_get_drvdata(dev);
ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0);
if (!ifc_dev_np) {
dev_err(dev, "No Interface device found\n");
return -EINVAL;
}
wcd->slim = sdev;
wcd->slim_ifc_dev = of_slim_get_device(sdev->ctrl, ifc_dev_np);
of_node_put(ifc_dev_np);
if (!wcd->slim_ifc_dev) {
dev_err(dev, "Unable to get SLIM Interface device\n");
return -EINVAL;
}
slim_get_logical_addr(wcd->slim_ifc_dev);
wcd->regmap = regmap_init_slimbus(sdev, &wcd9335_regmap_config);
if (IS_ERR(wcd->regmap))
return dev_err_probe(dev, PTR_ERR(wcd->regmap),
"Failed to allocate slim register map\n");
wcd->if_regmap = regmap_init_slimbus(wcd->slim_ifc_dev,
&wcd9335_ifc_regmap_config);
if (IS_ERR(wcd->if_regmap))
return dev_err_probe(dev, PTR_ERR(wcd->if_regmap),
"Failed to allocate ifc register map\n");
ret = wcd9335_bring_up(wcd);
if (ret) {
dev_err(dev, "Failed to bringup WCD9335\n");
return ret;
}
ret = wcd9335_irq_init(wcd);
if (ret)
return ret;
wcd9335_probe(wcd);
return 0;
}
static const struct slim_device_id wcd9335_slim_id[] = {
{SLIM_MANF_ID_QCOM, SLIM_PROD_CODE_WCD9335, 0x1, 0x0},
{}
};
MODULE_DEVICE_TABLE(slim, wcd9335_slim_id);
static struct slim_driver wcd9335_slim_driver = {
.driver = {
.name = "wcd9335-slim",
},
.probe = wcd9335_slim_probe,
.device_status = wcd9335_slim_status,
.id_table = wcd9335_slim_id,
};
module_slim_driver(wcd9335_slim_driver);
MODULE_DESCRIPTION("WCD9335 slim driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("slim:217:1a0:*");
| linux-master | sound/soc/codecs/wcd9335.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* rt298.c -- RT298 ALSA SoC audio codec driver
*
* Copyright 2015 Realtek Semiconductor Corp.
* Author: Bard Liao <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/dmi.h>
#include <linux/acpi.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/jack.h>
#include <linux/workqueue.h>
#include <sound/rt298.h>
#include "rl6347a.h"
#include "rt298.h"
#define RT298_VENDOR_ID 0x10ec0298
struct rt298_priv {
struct reg_default *index_cache;
int index_cache_size;
struct regmap *regmap;
struct snd_soc_component *component;
struct rt298_platform_data pdata;
struct i2c_client *i2c;
struct snd_soc_jack *jack;
struct delayed_work jack_detect_work;
int sys_clk;
int clk_id;
int is_hp_in;
};
static const struct reg_default rt298_index_def[] = {
{ 0x01, 0xa5a8 },
{ 0x02, 0x8e95 },
{ 0x03, 0x0002 },
{ 0x04, 0xaf67 },
{ 0x08, 0x200f },
{ 0x09, 0xd010 },
{ 0x0a, 0x0100 },
{ 0x0b, 0x0000 },
{ 0x0d, 0x2800 },
{ 0x0f, 0x0022 },
{ 0x19, 0x0217 },
{ 0x20, 0x0020 },
{ 0x33, 0x0208 },
{ 0x46, 0x0300 },
{ 0x49, 0x4004 },
{ 0x4f, 0x50c9 },
{ 0x50, 0x3000 },
{ 0x63, 0x1b02 },
{ 0x67, 0x1111 },
{ 0x68, 0x1016 },
{ 0x69, 0x273f },
};
#define INDEX_CACHE_SIZE ARRAY_SIZE(rt298_index_def)
static const struct reg_default rt298_reg[] = {
{ 0x00170500, 0x00000400 },
{ 0x00220000, 0x00000031 },
{ 0x00239000, 0x0000007f },
{ 0x0023a000, 0x0000007f },
{ 0x00270500, 0x00000400 },
{ 0x00370500, 0x00000400 },
{ 0x00870500, 0x00000400 },
{ 0x00920000, 0x00000031 },
{ 0x00935000, 0x000000c3 },
{ 0x00936000, 0x000000c3 },
{ 0x00970500, 0x00000400 },
{ 0x00b37000, 0x00000097 },
{ 0x00b37200, 0x00000097 },
{ 0x00b37300, 0x00000097 },
{ 0x00c37000, 0x00000000 },
{ 0x00c37100, 0x00000080 },
{ 0x01270500, 0x00000400 },
{ 0x01370500, 0x00000400 },
{ 0x01371f00, 0x411111f0 },
{ 0x01439000, 0x00000080 },
{ 0x0143a000, 0x00000080 },
{ 0x01470700, 0x00000000 },
{ 0x01470500, 0x00000400 },
{ 0x01470c00, 0x00000000 },
{ 0x01470100, 0x00000000 },
{ 0x01837000, 0x00000000 },
{ 0x01870500, 0x00000400 },
{ 0x02050000, 0x00000000 },
{ 0x02139000, 0x00000080 },
{ 0x0213a000, 0x00000080 },
{ 0x02170100, 0x00000000 },
{ 0x02170500, 0x00000400 },
{ 0x02170700, 0x00000000 },
{ 0x02270100, 0x00000000 },
{ 0x02370100, 0x00000000 },
{ 0x01870700, 0x00000020 },
{ 0x00830000, 0x000000c3 },
{ 0x00930000, 0x000000c3 },
{ 0x01270700, 0x00000000 },
};
static bool rt298_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0 ... 0xff:
case RT298_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
case RT298_GET_HP_SENSE:
case RT298_GET_MIC1_SENSE:
case RT298_PROC_COEF:
case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_MIC1, 0):
case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_SPK_OUT, 0):
case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_HP_OUT, 0):
return true;
default:
return false;
}
}
static bool rt298_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0 ... 0xff:
case RT298_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
case RT298_GET_HP_SENSE:
case RT298_GET_MIC1_SENSE:
case RT298_SET_AUDIO_POWER:
case RT298_SET_HPO_POWER:
case RT298_SET_SPK_POWER:
case RT298_SET_DMIC1_POWER:
case RT298_SPK_MUX:
case RT298_HPO_MUX:
case RT298_ADC0_MUX:
case RT298_ADC1_MUX:
case RT298_SET_MIC1:
case RT298_SET_PIN_HPO:
case RT298_SET_PIN_SPK:
case RT298_SET_PIN_DMIC1:
case RT298_SPK_EAPD:
case RT298_SET_AMP_GAIN_HPO:
case RT298_SET_DMIC2_DEFAULT:
case RT298_DACL_GAIN:
case RT298_DACR_GAIN:
case RT298_ADCL_GAIN:
case RT298_ADCR_GAIN:
case RT298_MIC_GAIN:
case RT298_SPOL_GAIN:
case RT298_SPOR_GAIN:
case RT298_HPOL_GAIN:
case RT298_HPOR_GAIN:
case RT298_F_DAC_SWITCH:
case RT298_F_RECMIX_SWITCH:
case RT298_REC_MIC_SWITCH:
case RT298_REC_I2S_SWITCH:
case RT298_REC_LINE_SWITCH:
case RT298_REC_BEEP_SWITCH:
case RT298_DAC_FORMAT:
case RT298_ADC_FORMAT:
case RT298_COEF_INDEX:
case RT298_PROC_COEF:
case RT298_SET_AMP_GAIN_ADC_IN1:
case RT298_SET_AMP_GAIN_ADC_IN2:
case RT298_SET_POWER(RT298_DAC_OUT1):
case RT298_SET_POWER(RT298_DAC_OUT2):
case RT298_SET_POWER(RT298_ADC_IN1):
case RT298_SET_POWER(RT298_ADC_IN2):
case RT298_SET_POWER(RT298_DMIC2):
case RT298_SET_POWER(RT298_MIC1):
case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_MIC1, 0):
case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_SPK_OUT, 0):
case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_HP_OUT, 0):
return true;
default:
return false;
}
}
#ifdef CONFIG_PM
static void rt298_index_sync(struct snd_soc_component *component)
{
struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component);
int i;
for (i = 0; i < INDEX_CACHE_SIZE; i++) {
snd_soc_component_write(component, rt298->index_cache[i].reg,
rt298->index_cache[i].def);
}
}
#endif
static int rt298_support_power_controls[] = {
RT298_DAC_OUT1,
RT298_DAC_OUT2,
RT298_ADC_IN1,
RT298_ADC_IN2,
RT298_MIC1,
RT298_DMIC1,
RT298_DMIC2,
RT298_SPK_OUT,
RT298_HP_OUT,
};
#define RT298_POWER_REG_LEN ARRAY_SIZE(rt298_support_power_controls)
static int rt298_jack_detect(struct rt298_priv *rt298, bool *hp, bool *mic)
{
struct snd_soc_dapm_context *dapm;
unsigned int val, buf;
*hp = false;
*mic = false;
if (!rt298->component)
return -EINVAL;
dapm = snd_soc_component_get_dapm(rt298->component);
if (rt298->pdata.cbj_en) {
regmap_read(rt298->regmap, RT298_GET_HP_SENSE, &buf);
*hp = buf & 0x80000000;
if (*hp == rt298->is_hp_in)
return -1;
rt298->is_hp_in = *hp;
if (*hp) {
/* power on HV,VERF */
regmap_update_bits(rt298->regmap,
RT298_DC_GAIN, 0x200, 0x200);
snd_soc_dapm_force_enable_pin(dapm, "HV");
snd_soc_dapm_force_enable_pin(dapm, "VREF");
/* power LDO1 */
snd_soc_dapm_force_enable_pin(dapm, "LDO1");
snd_soc_dapm_sync(dapm);
regmap_update_bits(rt298->regmap,
RT298_POWER_CTRL1, 0x1001, 0);
regmap_update_bits(rt298->regmap,
RT298_POWER_CTRL2, 0x4, 0x4);
regmap_write(rt298->regmap, RT298_SET_MIC1, 0x24);
msleep(50);
regmap_update_bits(rt298->regmap,
RT298_CBJ_CTRL1, 0xfcc0, 0xd400);
msleep(300);
regmap_read(rt298->regmap, RT298_CBJ_CTRL2, &val);
if (0x0070 == (val & 0x0070)) {
*mic = true;
} else {
regmap_update_bits(rt298->regmap,
RT298_CBJ_CTRL1, 0xfcc0, 0xe400);
msleep(300);
regmap_read(rt298->regmap,
RT298_CBJ_CTRL2, &val);
if (0x0070 == (val & 0x0070)) {
*mic = true;
} else {
*mic = false;
regmap_update_bits(rt298->regmap,
RT298_CBJ_CTRL1,
0xfcc0, 0xc400);
}
}
regmap_update_bits(rt298->regmap,
RT298_DC_GAIN, 0x200, 0x0);
} else {
*mic = false;
regmap_write(rt298->regmap, RT298_SET_MIC1, 0x20);
regmap_update_bits(rt298->regmap,
RT298_CBJ_CTRL1, 0x0400, 0x0000);
}
} else {
regmap_read(rt298->regmap, RT298_GET_HP_SENSE, &buf);
*hp = buf & 0x80000000;
regmap_read(rt298->regmap, RT298_GET_MIC1_SENSE, &buf);
*mic = buf & 0x80000000;
}
if (!*mic) {
snd_soc_dapm_disable_pin(dapm, "HV");
snd_soc_dapm_disable_pin(dapm, "VREF");
}
if (!*hp)
snd_soc_dapm_disable_pin(dapm, "LDO1");
snd_soc_dapm_sync(dapm);
pr_debug("*hp = %d *mic = %d\n", *hp, *mic);
return 0;
}
static void rt298_jack_detect_work(struct work_struct *work)
{
struct rt298_priv *rt298 =
container_of(work, struct rt298_priv, jack_detect_work.work);
int status = 0;
bool hp = false;
bool mic = false;
if (rt298_jack_detect(rt298, &hp, &mic) < 0)
return;
if (hp)
status |= SND_JACK_HEADPHONE;
if (mic)
status |= SND_JACK_MICROPHONE;
snd_soc_jack_report(rt298->jack, status,
SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
}
static int rt298_mic_detect(struct snd_soc_component *component,
struct snd_soc_jack *jack, void *data)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component);
rt298->jack = jack;
if (jack) {
/* Enable IRQ */
if (rt298->jack->status & SND_JACK_HEADPHONE)
snd_soc_dapm_force_enable_pin(dapm, "LDO1");
if (rt298->jack->status & SND_JACK_MICROPHONE) {
snd_soc_dapm_force_enable_pin(dapm, "HV");
snd_soc_dapm_force_enable_pin(dapm, "VREF");
}
regmap_update_bits(rt298->regmap, RT298_IRQ_CTRL, 0x2, 0x2);
/* Send an initial empty report */
snd_soc_jack_report(rt298->jack, rt298->jack->status,
SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
} else {
/* Disable IRQ */
regmap_update_bits(rt298->regmap, RT298_IRQ_CTRL, 0x2, 0x0);
snd_soc_dapm_disable_pin(dapm, "HV");
snd_soc_dapm_disable_pin(dapm, "VREF");
snd_soc_dapm_disable_pin(dapm, "LDO1");
}
snd_soc_dapm_sync(dapm);
return 0;
}
static int is_mclk_mode(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component);
if (rt298->clk_id == RT298_SCLK_S_MCLK)
return 1;
else
return 0;
}
static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0);
static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
static const struct snd_kcontrol_new rt298_snd_controls[] = {
SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT298_DACL_GAIN,
RT298_DACR_GAIN, 0, 0x7f, 0, out_vol_tlv),
SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT298_ADCL_GAIN,
RT298_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv),
SOC_SINGLE_TLV("AMIC Volume", RT298_MIC_GAIN,
0, 0x3, 0, mic_vol_tlv),
SOC_DOUBLE_R("Speaker Playback Switch", RT298_SPOL_GAIN,
RT298_SPOR_GAIN, RT298_MUTE_SFT, 1, 1),
};
/* Digital Mixer */
static const struct snd_kcontrol_new rt298_front_mix[] = {
SOC_DAPM_SINGLE("DAC Switch", RT298_F_DAC_SWITCH,
RT298_MUTE_SFT, 1, 1),
SOC_DAPM_SINGLE("RECMIX Switch", RT298_F_RECMIX_SWITCH,
RT298_MUTE_SFT, 1, 1),
};
/* Analog Input Mixer */
static const struct snd_kcontrol_new rt298_rec_mix[] = {
SOC_DAPM_SINGLE("Mic1 Switch", RT298_REC_MIC_SWITCH,
RT298_MUTE_SFT, 1, 1),
SOC_DAPM_SINGLE("I2S Switch", RT298_REC_I2S_SWITCH,
RT298_MUTE_SFT, 1, 1),
SOC_DAPM_SINGLE("Line1 Switch", RT298_REC_LINE_SWITCH,
RT298_MUTE_SFT, 1, 1),
SOC_DAPM_SINGLE("Beep Switch", RT298_REC_BEEP_SWITCH,
RT298_MUTE_SFT, 1, 1),
};
static const struct snd_kcontrol_new spo_enable_control =
SOC_DAPM_SINGLE("Switch", RT298_SET_PIN_SPK,
RT298_SET_PIN_SFT, 1, 0);
static const struct snd_kcontrol_new hpol_enable_control =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT298_HPOL_GAIN,
RT298_MUTE_SFT, 1, 1);
static const struct snd_kcontrol_new hpor_enable_control =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT298_HPOR_GAIN,
RT298_MUTE_SFT, 1, 1);
/* ADC0 source */
static const char * const rt298_adc_src[] = {
"Mic", "RECMIX", "Dmic"
};
static const int rt298_adc_values[] = {
0, 4, 5,
};
static SOC_VALUE_ENUM_SINGLE_DECL(
rt298_adc0_enum, RT298_ADC0_MUX, RT298_ADC_SEL_SFT,
RT298_ADC_SEL_MASK, rt298_adc_src, rt298_adc_values);
static const struct snd_kcontrol_new rt298_adc0_mux =
SOC_DAPM_ENUM("ADC 0 source", rt298_adc0_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(
rt298_adc1_enum, RT298_ADC1_MUX, RT298_ADC_SEL_SFT,
RT298_ADC_SEL_MASK, rt298_adc_src, rt298_adc_values);
static const struct snd_kcontrol_new rt298_adc1_mux =
SOC_DAPM_ENUM("ADC 1 source", rt298_adc1_enum);
static const char * const rt298_dac_src[] = {
"Front", "Surround"
};
/* HP-OUT source */
static SOC_ENUM_SINGLE_DECL(rt298_hpo_enum, RT298_HPO_MUX,
0, rt298_dac_src);
static const struct snd_kcontrol_new rt298_hpo_mux =
SOC_DAPM_ENUM("HPO source", rt298_hpo_enum);
/* SPK-OUT source */
static SOC_ENUM_SINGLE_DECL(rt298_spo_enum, RT298_SPK_MUX,
0, rt298_dac_src);
static const struct snd_kcontrol_new rt298_spo_mux =
SOC_DAPM_ENUM("SPO source", rt298_spo_enum);
static int rt298_spk_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_write(component,
RT298_SPK_EAPD, RT298_SET_EAPD_HIGH);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_write(component,
RT298_SPK_EAPD, RT298_SET_EAPD_LOW);
break;
default:
return 0;
}
return 0;
}
static int rt298_set_dmic1_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_write(component, RT298_SET_PIN_DMIC1, 0x20);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_write(component, RT298_SET_PIN_DMIC1, 0);
break;
default:
return 0;
}
return 0;
}
static int rt298_adc_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
unsigned int nid;
nid = (w->reg >> 20) & 0xff;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(component,
VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, nid, 0),
0x7080, 0x7000);
/* If MCLK doesn't exist, reset AD filter */
if (!(snd_soc_component_read(component, RT298_VAD_CTRL) & 0x200)) {
pr_info("NO MCLK\n");
switch (nid) {
case RT298_ADC_IN1:
snd_soc_component_update_bits(component,
RT298_D_FILTER_CTRL, 0x2, 0x2);
mdelay(10);
snd_soc_component_update_bits(component,
RT298_D_FILTER_CTRL, 0x2, 0x0);
break;
case RT298_ADC_IN2:
snd_soc_component_update_bits(component,
RT298_D_FILTER_CTRL, 0x4, 0x4);
mdelay(10);
snd_soc_component_update_bits(component,
RT298_D_FILTER_CTRL, 0x4, 0x0);
break;
}
}
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component,
VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, nid, 0),
0x7080, 0x7080);
break;
default:
return 0;
}
return 0;
}
static int rt298_mic1_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_component_update_bits(component,
RT298_A_BIAS_CTRL3, 0xc000, 0x8000);
snd_soc_component_update_bits(component,
RT298_A_BIAS_CTRL2, 0xc000, 0x8000);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component,
RT298_A_BIAS_CTRL3, 0xc000, 0x0000);
snd_soc_component_update_bits(component,
RT298_A_BIAS_CTRL2, 0xc000, 0x0000);
break;
default:
return 0;
}
return 0;
}
static const struct snd_soc_dapm_widget rt298_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY_S("HV", 1, RT298_POWER_CTRL1,
12, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("VREF", RT298_POWER_CTRL1,
0, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("BG_MBIAS", 1, RT298_POWER_CTRL2,
1, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("LDO1", 1, RT298_POWER_CTRL2,
2, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("LDO2", 1, RT298_POWER_CTRL2,
3, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("VREF1", 1, RT298_POWER_CTRL2,
4, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("LV", 2, RT298_POWER_CTRL1,
13, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("MCLK MODE", RT298_PLL_CTRL1,
5, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MIC1 Input Buffer", SND_SOC_NOPM,
0, 0, rt298_mic1_event, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMD),
/* Input Lines */
SND_SOC_DAPM_INPUT("DMIC1 Pin"),
SND_SOC_DAPM_INPUT("DMIC2 Pin"),
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_INPUT("LINE1"),
SND_SOC_DAPM_INPUT("Beep"),
/* DMIC */
SND_SOC_DAPM_PGA_E("DMIC1", RT298_SET_POWER(RT298_DMIC1), 0, 1,
NULL, 0, rt298_set_dmic1_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA("DMIC2", RT298_SET_POWER(RT298_DMIC2), 0, 1,
NULL, 0),
SND_SOC_DAPM_SUPPLY("DMIC Receiver", SND_SOC_NOPM,
0, 0, NULL, 0),
/* REC Mixer */
SND_SOC_DAPM_MIXER("RECMIX", SND_SOC_NOPM, 0, 0,
rt298_rec_mix, ARRAY_SIZE(rt298_rec_mix)),
/* ADCs */
SND_SOC_DAPM_ADC("ADC 0", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0),
/* ADC Mux */
SND_SOC_DAPM_MUX_E("ADC 0 Mux", RT298_SET_POWER(RT298_ADC_IN1), 0, 1,
&rt298_adc0_mux, rt298_adc_event, SND_SOC_DAPM_PRE_PMD |
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_MUX_E("ADC 1 Mux", RT298_SET_POWER(RT298_ADC_IN2), 0, 1,
&rt298_adc1_mux, rt298_adc_event, SND_SOC_DAPM_PRE_PMD |
SND_SOC_DAPM_POST_PMU),
/* Audio Interface */
SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
/* Output Side */
/* DACs */
SND_SOC_DAPM_DAC("DAC 0", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DAC 1", NULL, SND_SOC_NOPM, 0, 0),
/* Output Mux */
SND_SOC_DAPM_MUX("SPK Mux", SND_SOC_NOPM, 0, 0, &rt298_spo_mux),
SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt298_hpo_mux),
SND_SOC_DAPM_SUPPLY("HP Power", RT298_SET_PIN_HPO,
RT298_SET_PIN_SFT, 0, NULL, 0),
/* Output Mixer */
SND_SOC_DAPM_MIXER("Front", RT298_SET_POWER(RT298_DAC_OUT1), 0, 1,
rt298_front_mix, ARRAY_SIZE(rt298_front_mix)),
SND_SOC_DAPM_PGA("Surround", RT298_SET_POWER(RT298_DAC_OUT2), 0, 1,
NULL, 0),
/* Output Pga */
SND_SOC_DAPM_SWITCH_E("SPO", SND_SOC_NOPM, 0, 0,
&spo_enable_control, rt298_spk_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0,
&hpol_enable_control),
SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0,
&hpor_enable_control),
/* Output Lines */
SND_SOC_DAPM_OUTPUT("SPOL"),
SND_SOC_DAPM_OUTPUT("SPOR"),
SND_SOC_DAPM_OUTPUT("HPO Pin"),
SND_SOC_DAPM_OUTPUT("SPDIF"),
};
static const struct snd_soc_dapm_route rt298_dapm_routes[] = {
{"ADC 0", NULL, "MCLK MODE", is_mclk_mode},
{"ADC 1", NULL, "MCLK MODE", is_mclk_mode},
{"Front", NULL, "MCLK MODE", is_mclk_mode},
{"Surround", NULL, "MCLK MODE", is_mclk_mode},
{"HP Power", NULL, "LDO1"},
{"HP Power", NULL, "LDO2"},
{"HP Power", NULL, "LV"},
{"HP Power", NULL, "VREF1"},
{"HP Power", NULL, "BG_MBIAS"},
{"MIC1", NULL, "LDO1"},
{"MIC1", NULL, "LDO2"},
{"MIC1", NULL, "HV"},
{"MIC1", NULL, "LV"},
{"MIC1", NULL, "VREF"},
{"MIC1", NULL, "VREF1"},
{"MIC1", NULL, "BG_MBIAS"},
{"MIC1", NULL, "MIC1 Input Buffer"},
{"SPO", NULL, "LDO1"},
{"SPO", NULL, "LDO2"},
{"SPO", NULL, "HV"},
{"SPO", NULL, "LV"},
{"SPO", NULL, "VREF"},
{"SPO", NULL, "VREF1"},
{"SPO", NULL, "BG_MBIAS"},
{"DMIC1", NULL, "DMIC1 Pin"},
{"DMIC2", NULL, "DMIC2 Pin"},
{"DMIC1", NULL, "DMIC Receiver"},
{"DMIC2", NULL, "DMIC Receiver"},
{"RECMIX", "Beep Switch", "Beep"},
{"RECMIX", "Line1 Switch", "LINE1"},
{"RECMIX", "Mic1 Switch", "MIC1"},
{"ADC 0 Mux", "Dmic", "DMIC1"},
{"ADC 0 Mux", "RECMIX", "RECMIX"},
{"ADC 0 Mux", "Mic", "MIC1"},
{"ADC 1 Mux", "Dmic", "DMIC2"},
{"ADC 1 Mux", "RECMIX", "RECMIX"},
{"ADC 1 Mux", "Mic", "MIC1"},
{"ADC 0", NULL, "ADC 0 Mux"},
{"ADC 1", NULL, "ADC 1 Mux"},
{"AIF1TX", NULL, "ADC 0"},
{"AIF2TX", NULL, "ADC 1"},
{"DAC 0", NULL, "AIF1RX"},
{"DAC 1", NULL, "AIF2RX"},
{"Front", "DAC Switch", "DAC 0"},
{"Front", "RECMIX Switch", "RECMIX"},
{"Surround", NULL, "DAC 1"},
{"SPK Mux", "Front", "Front"},
{"SPK Mux", "Surround", "Surround"},
{"HPO Mux", "Front", "Front"},
{"HPO Mux", "Surround", "Surround"},
{"SPO", "Switch", "SPK Mux"},
{"HPO L", "Switch", "HPO Mux"},
{"HPO R", "Switch", "HPO Mux"},
{"HPO L", NULL, "HP Power"},
{"HPO R", NULL, "HP Power"},
{"SPOL", NULL, "SPO"},
{"SPOR", NULL, "SPO"},
{"HPO Pin", NULL, "HPO L"},
{"HPO Pin", NULL, "HPO R"},
};
static int rt298_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component);
unsigned int val = 0;
int d_len_code;
switch (params_rate(params)) {
/* bit 14 0:48K 1:44.1K */
case 44100:
case 48000:
break;
default:
dev_err(component->dev, "Unsupported sample rate %d\n",
params_rate(params));
return -EINVAL;
}
switch (rt298->sys_clk) {
case 12288000:
case 24576000:
if (params_rate(params) != 48000) {
dev_err(component->dev, "Sys_clk is not matched (%d %d)\n",
params_rate(params), rt298->sys_clk);
return -EINVAL;
}
break;
case 11289600:
case 22579200:
if (params_rate(params) != 44100) {
dev_err(component->dev, "Sys_clk is not matched (%d %d)\n",
params_rate(params), rt298->sys_clk);
return -EINVAL;
}
break;
}
if (params_channels(params) <= 16) {
/* bit 3:0 Number of Channel */
val |= (params_channels(params) - 1);
} else {
dev_err(component->dev, "Unsupported channels %d\n",
params_channels(params));
return -EINVAL;
}
d_len_code = 0;
switch (params_width(params)) {
/* bit 6:4 Bits per Sample */
case 16:
d_len_code = 0;
val |= (0x1 << 4);
break;
case 32:
d_len_code = 2;
val |= (0x4 << 4);
break;
case 20:
d_len_code = 1;
val |= (0x2 << 4);
break;
case 24:
d_len_code = 2;
val |= (0x3 << 4);
break;
case 8:
d_len_code = 3;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component,
RT298_I2S_CTRL1, 0x0018, d_len_code << 3);
dev_dbg(component->dev, "format val = 0x%x\n", val);
snd_soc_component_update_bits(component, RT298_DAC_FORMAT, 0x407f, val);
snd_soc_component_update_bits(component, RT298_ADC_FORMAT, 0x407f, val);
return 0;
}
static int rt298_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
snd_soc_component_update_bits(component,
RT298_I2S_CTRL1, 0x800, 0x800);
break;
case SND_SOC_DAIFMT_CBS_CFS:
snd_soc_component_update_bits(component,
RT298_I2S_CTRL1, 0x800, 0x0);
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
snd_soc_component_update_bits(component,
RT298_I2S_CTRL1, 0x300, 0x0);
break;
case SND_SOC_DAIFMT_LEFT_J:
snd_soc_component_update_bits(component,
RT298_I2S_CTRL1, 0x300, 0x1 << 8);
break;
case SND_SOC_DAIFMT_DSP_A:
snd_soc_component_update_bits(component,
RT298_I2S_CTRL1, 0x300, 0x2 << 8);
break;
case SND_SOC_DAIFMT_DSP_B:
snd_soc_component_update_bits(component,
RT298_I2S_CTRL1, 0x300, 0x3 << 8);
break;
default:
return -EINVAL;
}
/* bit 15 Stream Type 0:PCM 1:Non-PCM */
snd_soc_component_update_bits(component, RT298_DAC_FORMAT, 0x8000, 0);
snd_soc_component_update_bits(component, RT298_ADC_FORMAT, 0x8000, 0);
return 0;
}
static int rt298_set_dai_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component);
dev_dbg(component->dev, "%s freq=%d\n", __func__, freq);
if (RT298_SCLK_S_MCLK == clk_id) {
snd_soc_component_update_bits(component,
RT298_I2S_CTRL2, 0x0100, 0x0);
snd_soc_component_update_bits(component,
RT298_PLL_CTRL1, 0x20, 0x20);
} else {
snd_soc_component_update_bits(component,
RT298_I2S_CTRL2, 0x0100, 0x0100);
snd_soc_component_update_bits(component,
RT298_PLL_CTRL1, 0x20, 0x0);
}
switch (freq) {
case 19200000:
if (RT298_SCLK_S_MCLK == clk_id) {
dev_err(component->dev, "Should not use MCLK\n");
return -EINVAL;
}
snd_soc_component_update_bits(component,
RT298_I2S_CTRL2, 0x40, 0x40);
break;
case 24000000:
if (RT298_SCLK_S_MCLK == clk_id) {
dev_err(component->dev, "Should not use MCLK\n");
return -EINVAL;
}
snd_soc_component_update_bits(component,
RT298_I2S_CTRL2, 0x40, 0x0);
break;
case 12288000:
case 11289600:
snd_soc_component_update_bits(component,
RT298_I2S_CTRL2, 0x8, 0x0);
snd_soc_component_update_bits(component,
RT298_CLK_DIV, 0xfc1e, 0x0004);
break;
case 24576000:
case 22579200:
snd_soc_component_update_bits(component,
RT298_I2S_CTRL2, 0x8, 0x8);
snd_soc_component_update_bits(component,
RT298_CLK_DIV, 0xfc1e, 0x5406);
break;
default:
dev_err(component->dev, "Unsupported system clock\n");
return -EINVAL;
}
rt298->sys_clk = freq;
rt298->clk_id = clk_id;
return 0;
}
static int rt298_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
{
struct snd_soc_component *component = dai->component;
dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio);
if (50 == ratio)
snd_soc_component_update_bits(component,
RT298_I2S_CTRL1, 0x1000, 0x1000);
else
snd_soc_component_update_bits(component,
RT298_I2S_CTRL1, 0x1000, 0x0);
return 0;
}
static int rt298_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
switch (level) {
case SND_SOC_BIAS_PREPARE:
if (SND_SOC_BIAS_STANDBY ==
snd_soc_component_get_bias_level(component)) {
snd_soc_component_write(component,
RT298_SET_AUDIO_POWER, AC_PWRST_D0);
snd_soc_component_update_bits(component, 0x0d, 0x200, 0x200);
snd_soc_component_update_bits(component, 0x52, 0x80, 0x0);
mdelay(20);
snd_soc_component_update_bits(component, 0x0d, 0x200, 0x0);
snd_soc_component_update_bits(component, 0x52, 0x80, 0x80);
}
break;
case SND_SOC_BIAS_STANDBY:
snd_soc_component_write(component,
RT298_SET_AUDIO_POWER, AC_PWRST_D3);
break;
default:
break;
}
return 0;
}
static irqreturn_t rt298_irq(int irq, void *data)
{
struct rt298_priv *rt298 = data;
bool hp = false;
bool mic = false;
int ret, status = 0;
ret = rt298_jack_detect(rt298, &hp, &mic);
/* Clear IRQ */
regmap_update_bits(rt298->regmap, RT298_IRQ_CTRL, 0x1, 0x1);
if (ret == 0) {
if (hp)
status |= SND_JACK_HEADPHONE;
if (mic)
status |= SND_JACK_MICROPHONE;
snd_soc_jack_report(rt298->jack, status,
SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
pm_wakeup_event(&rt298->i2c->dev, 300);
}
return IRQ_HANDLED;
}
static int rt298_probe(struct snd_soc_component *component)
{
struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component);
rt298->component = component;
INIT_DELAYED_WORK(&rt298->jack_detect_work, rt298_jack_detect_work);
if (rt298->i2c->irq)
schedule_delayed_work(&rt298->jack_detect_work,
msecs_to_jiffies(1250));
return 0;
}
static void rt298_remove(struct snd_soc_component *component)
{
struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component);
cancel_delayed_work_sync(&rt298->jack_detect_work);
rt298->component = NULL;
}
#ifdef CONFIG_PM
static int rt298_suspend(struct snd_soc_component *component)
{
struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component);
rt298->is_hp_in = -1;
regcache_cache_only(rt298->regmap, true);
regcache_mark_dirty(rt298->regmap);
return 0;
}
static int rt298_resume(struct snd_soc_component *component)
{
struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component);
regcache_cache_only(rt298->regmap, false);
rt298_index_sync(component);
regcache_sync(rt298->regmap);
return 0;
}
#else
#define rt298_suspend NULL
#define rt298_resume NULL
#endif
#define RT298_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
#define RT298_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
static const struct snd_soc_dai_ops rt298_aif_dai_ops = {
.hw_params = rt298_hw_params,
.set_fmt = rt298_set_dai_fmt,
.set_sysclk = rt298_set_dai_sysclk,
.set_bclk_ratio = rt298_set_bclk_ratio,
};
static struct snd_soc_dai_driver rt298_dai[] = {
{
.name = "rt298-aif1",
.id = RT298_AIF1,
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT298_STEREO_RATES,
.formats = RT298_FORMATS,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT298_STEREO_RATES,
.formats = RT298_FORMATS,
},
.ops = &rt298_aif_dai_ops,
.symmetric_rate = 1,
},
{
.name = "rt298-aif2",
.id = RT298_AIF2,
.playback = {
.stream_name = "AIF2 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT298_STEREO_RATES,
.formats = RT298_FORMATS,
},
.capture = {
.stream_name = "AIF2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT298_STEREO_RATES,
.formats = RT298_FORMATS,
},
.ops = &rt298_aif_dai_ops,
.symmetric_rate = 1,
},
};
static const struct snd_soc_component_driver soc_component_dev_rt298 = {
.probe = rt298_probe,
.remove = rt298_remove,
.suspend = rt298_suspend,
.resume = rt298_resume,
.set_bias_level = rt298_set_bias_level,
.set_jack = rt298_mic_detect,
.controls = rt298_snd_controls,
.num_controls = ARRAY_SIZE(rt298_snd_controls),
.dapm_widgets = rt298_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt298_dapm_widgets),
.dapm_routes = rt298_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(rt298_dapm_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config rt298_regmap = {
.reg_bits = 32,
.val_bits = 32,
.max_register = 0x02370100,
.volatile_reg = rt298_volatile_register,
.readable_reg = rt298_readable_register,
.reg_write = rl6347a_hw_write,
.reg_read = rl6347a_hw_read,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = rt298_reg,
.num_reg_defaults = ARRAY_SIZE(rt298_reg),
};
static const struct i2c_device_id rt298_i2c_id[] = {
{"rt298", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, rt298_i2c_id);
#ifdef CONFIG_ACPI
static const struct acpi_device_id rt298_acpi_match[] = {
{ "INT343A", 0 },
{},
};
MODULE_DEVICE_TABLE(acpi, rt298_acpi_match);
#endif
static const struct dmi_system_id force_combo_jack_table[] = {
{
.ident = "Intel Broxton P",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Intel Corp"),
DMI_MATCH(DMI_PRODUCT_NAME, "Broxton P")
}
},
{
.ident = "Intel Gemini Lake",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Intel Corp"),
DMI_MATCH(DMI_PRODUCT_NAME, "Geminilake")
}
},
{
.ident = "Intel Kabylake R RVP",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Intel Corporation"),
DMI_MATCH(DMI_PRODUCT_NAME, "Kabylake Client platform")
}
},
{ }
};
static int rt298_i2c_probe(struct i2c_client *i2c)
{
struct rt298_platform_data *pdata = dev_get_platdata(&i2c->dev);
struct rt298_priv *rt298;
struct device *dev = &i2c->dev;
const struct acpi_device_id *acpiid;
int i, ret;
rt298 = devm_kzalloc(&i2c->dev, sizeof(*rt298),
GFP_KERNEL);
if (NULL == rt298)
return -ENOMEM;
rt298->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt298_regmap);
if (IS_ERR(rt298->regmap)) {
ret = PTR_ERR(rt298->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
regmap_read(rt298->regmap,
RT298_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &ret);
if (ret != RT298_VENDOR_ID) {
dev_err(&i2c->dev,
"Device with ID register %#x is not rt298\n", ret);
return -ENODEV;
}
rt298->index_cache = devm_kmemdup(&i2c->dev, rt298_index_def,
sizeof(rt298_index_def), GFP_KERNEL);
if (!rt298->index_cache)
return -ENOMEM;
rt298->index_cache_size = INDEX_CACHE_SIZE;
rt298->i2c = i2c;
i2c_set_clientdata(i2c, rt298);
/* restore codec default */
for (i = 0; i < INDEX_CACHE_SIZE; i++)
regmap_write(rt298->regmap, rt298->index_cache[i].reg,
rt298->index_cache[i].def);
for (i = 0; i < ARRAY_SIZE(rt298_reg); i++)
regmap_write(rt298->regmap, rt298_reg[i].reg,
rt298_reg[i].def);
if (pdata)
rt298->pdata = *pdata;
/* enable jack combo mode on supported devices */
acpiid = acpi_match_device(dev->driver->acpi_match_table, dev);
if (acpiid && acpiid->driver_data) {
rt298->pdata = *(struct rt298_platform_data *)
acpiid->driver_data;
}
if (dmi_check_system(force_combo_jack_table)) {
rt298->pdata.cbj_en = true;
rt298->pdata.gpio2_en = false;
}
/* VREF Charging */
regmap_update_bits(rt298->regmap, 0x04, 0x80, 0x80);
regmap_update_bits(rt298->regmap, 0x1b, 0x860, 0x860);
/* Vref2 */
regmap_update_bits(rt298->regmap, 0x08, 0x20, 0x20);
regmap_write(rt298->regmap, RT298_SET_AUDIO_POWER, AC_PWRST_D3);
for (i = 0; i < RT298_POWER_REG_LEN; i++)
regmap_write(rt298->regmap,
RT298_SET_POWER(rt298_support_power_controls[i]),
AC_PWRST_D1);
if (!rt298->pdata.cbj_en) {
regmap_write(rt298->regmap, RT298_CBJ_CTRL2, 0x0000);
regmap_write(rt298->regmap, RT298_MIC1_DET_CTRL, 0x0816);
regmap_update_bits(rt298->regmap,
RT298_CBJ_CTRL1, 0xf000, 0xb000);
} else {
regmap_update_bits(rt298->regmap,
RT298_CBJ_CTRL1, 0xf000, 0x5000);
}
mdelay(10);
if (!rt298->pdata.gpio2_en)
regmap_write(rt298->regmap, RT298_SET_DMIC2_DEFAULT, 0x40);
else
regmap_write(rt298->regmap, RT298_SET_DMIC2_DEFAULT, 0);
mdelay(10);
regmap_write(rt298->regmap, RT298_MISC_CTRL1, 0x0000);
regmap_update_bits(rt298->regmap,
RT298_WIND_FILTER_CTRL, 0x0082, 0x0082);
regmap_write(rt298->regmap, RT298_UNSOLICITED_INLINE_CMD, 0x81);
regmap_write(rt298->regmap, RT298_UNSOLICITED_HP_OUT, 0x82);
regmap_write(rt298->regmap, RT298_UNSOLICITED_MIC1, 0x84);
regmap_update_bits(rt298->regmap, RT298_IRQ_FLAG_CTRL, 0x2, 0x2);
rt298->is_hp_in = -1;
if (rt298->i2c->irq) {
ret = request_threaded_irq(rt298->i2c->irq, NULL, rt298_irq,
IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt298", rt298);
if (ret != 0) {
dev_err(&i2c->dev,
"Failed to reguest IRQ: %d\n", ret);
return ret;
}
}
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_rt298,
rt298_dai, ARRAY_SIZE(rt298_dai));
return ret;
}
static void rt298_i2c_remove(struct i2c_client *i2c)
{
struct rt298_priv *rt298 = i2c_get_clientdata(i2c);
if (i2c->irq)
free_irq(i2c->irq, rt298);
}
static struct i2c_driver rt298_i2c_driver = {
.driver = {
.name = "rt298",
.acpi_match_table = ACPI_PTR(rt298_acpi_match),
},
.probe = rt298_i2c_probe,
.remove = rt298_i2c_remove,
.id_table = rt298_i2c_id,
};
module_i2c_driver(rt298_i2c_driver);
MODULE_DESCRIPTION("ASoC RT298 driver");
MODULE_AUTHOR("Bard Liao <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/rt298.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* cs4349.c -- CS4349 ALSA Soc Audio driver
*
* Copyright 2015 Cirrus Logic, Inc.
*
* Authors: Tim Howe <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "cs4349.h"
static const struct reg_default cs4349_reg_defaults[] = {
{ 2, 0x00 }, /* r02 - Mode Control */
{ 3, 0x09 }, /* r03 - Volume, Mixing and Inversion Control */
{ 4, 0x81 }, /* r04 - Mute Control */
{ 5, 0x00 }, /* r05 - Channel A Volume Control */
{ 6, 0x00 }, /* r06 - Channel B Volume Control */
{ 7, 0xB1 }, /* r07 - Ramp and Filter Control */
{ 8, 0x1C }, /* r08 - Misc. Control */
};
/* Private data for the CS4349 */
struct cs4349_private {
struct regmap *regmap;
struct gpio_desc *reset_gpio;
unsigned int mode;
int rate;
};
static bool cs4349_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS4349_CHIPID ... CS4349_MISC:
return true;
default:
return false;
}
}
static bool cs4349_writeable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS4349_MODE ... CS4349_MISC:
return true;
default:
return false;
}
}
static int cs4349_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int format)
{
struct snd_soc_component *component = codec_dai->component;
struct cs4349_private *cs4349 = snd_soc_component_get_drvdata(component);
unsigned int fmt;
fmt = format & SND_SOC_DAIFMT_FORMAT_MASK;
switch (fmt) {
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_LEFT_J:
case SND_SOC_DAIFMT_RIGHT_J:
cs4349->mode = format & SND_SOC_DAIFMT_FORMAT_MASK;
break;
default:
return -EINVAL;
}
return 0;
}
static int cs4349_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct cs4349_private *cs4349 = snd_soc_component_get_drvdata(component);
int fmt, ret;
cs4349->rate = params_rate(params);
switch (cs4349->mode) {
case SND_SOC_DAIFMT_I2S:
fmt = DIF_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
fmt = DIF_LEFT_JST;
break;
case SND_SOC_DAIFMT_RIGHT_J:
switch (params_width(params)) {
case 16:
fmt = DIF_RGHT_JST16;
break;
case 24:
fmt = DIF_RGHT_JST24;
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
ret = snd_soc_component_update_bits(component, CS4349_MODE, DIF_MASK,
MODE_FORMAT(fmt));
if (ret < 0)
return ret;
return 0;
}
static int cs4349_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
int reg;
reg = 0;
if (mute)
reg = MUTE_AB_MASK;
return snd_soc_component_update_bits(component, CS4349_MUTE, MUTE_AB_MASK, reg);
}
static DECLARE_TLV_DB_SCALE(dig_tlv, -12750, 50, 0);
static const char * const chan_mix_texts[] = {
"Mute", "MuteA", "MuteA SwapB", "MuteA MonoB", "SwapA MuteB",
"BothR", "Swap", "SwapA MonoB", "MuteB", "Normal", "BothL",
"MonoB", "MonoA MuteB", "MonoA", "MonoA SwapB", "Mono",
/*Normal == Channel A = Left, Channel B = Right*/
};
static const char * const fm_texts[] = {
"Auto", "Single", "Double", "Quad",
};
static const char * const deemph_texts[] = {
"None", "44.1k", "48k", "32k",
};
static const char * const softr_zeroc_texts[] = {
"Immediate", "Zero Cross", "Soft Ramp", "SR on ZC",
};
static int deemph_values[] = {
0, 4, 8, 12,
};
static int softr_zeroc_values[] = {
0, 64, 128, 192,
};
static const struct soc_enum chan_mix_enum =
SOC_ENUM_SINGLE(CS4349_VMI, 0,
ARRAY_SIZE(chan_mix_texts),
chan_mix_texts);
static const struct soc_enum fm_mode_enum =
SOC_ENUM_SINGLE(CS4349_MODE, 0,
ARRAY_SIZE(fm_texts),
fm_texts);
static SOC_VALUE_ENUM_SINGLE_DECL(deemph_enum, CS4349_MODE, 0, DEM_MASK,
deemph_texts, deemph_values);
static SOC_VALUE_ENUM_SINGLE_DECL(softr_zeroc_enum, CS4349_RMPFLT, 0,
SR_ZC_MASK, softr_zeroc_texts,
softr_zeroc_values);
static const struct snd_kcontrol_new cs4349_snd_controls[] = {
SOC_DOUBLE_R_TLV("Master Playback Volume",
CS4349_VOLA, CS4349_VOLB, 0, 0xFF, 1, dig_tlv),
SOC_ENUM("Functional Mode", fm_mode_enum),
SOC_ENUM("De-Emphasis Control", deemph_enum),
SOC_ENUM("Soft Ramp Zero Cross Control", softr_zeroc_enum),
SOC_ENUM("Channel Mixer", chan_mix_enum),
SOC_SINGLE("VolA = VolB Switch", CS4349_VMI, 7, 1, 0),
SOC_SINGLE("InvertA Switch", CS4349_VMI, 6, 1, 0),
SOC_SINGLE("InvertB Switch", CS4349_VMI, 5, 1, 0),
SOC_SINGLE("Auto-Mute Switch", CS4349_MUTE, 7, 1, 0),
SOC_SINGLE("MUTEC A = B Switch", CS4349_MUTE, 5, 1, 0),
SOC_SINGLE("Soft Ramp Up Switch", CS4349_RMPFLT, 5, 1, 0),
SOC_SINGLE("Soft Ramp Down Switch", CS4349_RMPFLT, 4, 1, 0),
SOC_SINGLE("Slow Roll Off Filter Switch", CS4349_RMPFLT, 2, 1, 0),
SOC_SINGLE("Freeze Switch", CS4349_MISC, 5, 1, 0),
SOC_SINGLE("Popguard Switch", CS4349_MISC, 4, 1, 0),
};
static const struct snd_soc_dapm_widget cs4349_dapm_widgets[] = {
SND_SOC_DAPM_DAC("HiFi DAC", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_OUTPUT("OutputA"),
SND_SOC_DAPM_OUTPUT("OutputB"),
};
static const struct snd_soc_dapm_route cs4349_routes[] = {
{"DAC Playback", NULL, "OutputA"},
{"DAC Playback", NULL, "OutputB"},
{"OutputA", NULL, "HiFi DAC"},
{"OutputB", NULL, "HiFi DAC"},
};
#define CS4349_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE)
#define CS4349_PCM_RATES SNDRV_PCM_RATE_8000_192000
static const struct snd_soc_dai_ops cs4349_dai_ops = {
.hw_params = cs4349_pcm_hw_params,
.set_fmt = cs4349_set_dai_fmt,
.mute_stream = cs4349_mute,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver cs4349_dai = {
.name = "cs4349_hifi",
.playback = {
.stream_name = "DAC Playback",
.channels_min = 1,
.channels_max = 2,
.rates = CS4349_PCM_RATES,
.formats = CS4349_PCM_FORMATS,
},
.ops = &cs4349_dai_ops,
.symmetric_rate = 1,
};
static const struct snd_soc_component_driver soc_component_dev_cs4349 = {
.controls = cs4349_snd_controls,
.num_controls = ARRAY_SIZE(cs4349_snd_controls),
.dapm_widgets = cs4349_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(cs4349_dapm_widgets),
.dapm_routes = cs4349_routes,
.num_dapm_routes = ARRAY_SIZE(cs4349_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config cs4349_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = CS4349_MISC,
.reg_defaults = cs4349_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(cs4349_reg_defaults),
.readable_reg = cs4349_readable_register,
.writeable_reg = cs4349_writeable_register,
.cache_type = REGCACHE_MAPLE,
};
static int cs4349_i2c_probe(struct i2c_client *client)
{
struct cs4349_private *cs4349;
int ret;
cs4349 = devm_kzalloc(&client->dev, sizeof(*cs4349), GFP_KERNEL);
if (!cs4349)
return -ENOMEM;
cs4349->regmap = devm_regmap_init_i2c(client, &cs4349_regmap);
if (IS_ERR(cs4349->regmap)) {
ret = PTR_ERR(cs4349->regmap);
dev_err(&client->dev, "regmap_init() failed: %d\n", ret);
return ret;
}
/* Reset the Device */
cs4349->reset_gpio = devm_gpiod_get_optional(&client->dev,
"reset", GPIOD_OUT_LOW);
if (IS_ERR(cs4349->reset_gpio))
return PTR_ERR(cs4349->reset_gpio);
gpiod_set_value_cansleep(cs4349->reset_gpio, 1);
i2c_set_clientdata(client, cs4349);
return devm_snd_soc_register_component(&client->dev,
&soc_component_dev_cs4349,
&cs4349_dai, 1);
}
static void cs4349_i2c_remove(struct i2c_client *client)
{
struct cs4349_private *cs4349 = i2c_get_clientdata(client);
/* Hold down reset */
gpiod_set_value_cansleep(cs4349->reset_gpio, 0);
}
#ifdef CONFIG_PM
static int cs4349_runtime_suspend(struct device *dev)
{
struct cs4349_private *cs4349 = dev_get_drvdata(dev);
int ret;
ret = regmap_update_bits(cs4349->regmap, CS4349_MISC, PWR_DWN, PWR_DWN);
if (ret < 0)
return ret;
regcache_cache_only(cs4349->regmap, true);
/* Hold down reset */
gpiod_set_value_cansleep(cs4349->reset_gpio, 0);
return 0;
}
static int cs4349_runtime_resume(struct device *dev)
{
struct cs4349_private *cs4349 = dev_get_drvdata(dev);
int ret;
ret = regmap_update_bits(cs4349->regmap, CS4349_MISC, PWR_DWN, 0);
if (ret < 0)
return ret;
gpiod_set_value_cansleep(cs4349->reset_gpio, 1);
regcache_cache_only(cs4349->regmap, false);
regcache_sync(cs4349->regmap);
return 0;
}
#endif
static const struct dev_pm_ops cs4349_runtime_pm = {
SET_RUNTIME_PM_OPS(cs4349_runtime_suspend, cs4349_runtime_resume,
NULL)
};
static const struct of_device_id cs4349_of_match[] = {
{ .compatible = "cirrus,cs4349", },
{},
};
MODULE_DEVICE_TABLE(of, cs4349_of_match);
static const struct i2c_device_id cs4349_i2c_id[] = {
{"cs4349", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, cs4349_i2c_id);
static struct i2c_driver cs4349_i2c_driver = {
.driver = {
.name = "cs4349",
.of_match_table = cs4349_of_match,
.pm = &cs4349_runtime_pm,
},
.id_table = cs4349_i2c_id,
.probe = cs4349_i2c_probe,
.remove = cs4349_i2c_remove,
};
module_i2c_driver(cs4349_i2c_driver);
MODULE_AUTHOR("Tim Howe <[email protected]>");
MODULE_DESCRIPTION("Cirrus Logic CS4349 ALSA SoC Codec Driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cs4349.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* max9850.c -- codec driver for max9850
*
* Copyright (C) 2011 taskit GmbH
*
* Author: Christian Glindkamp <[email protected]>
*
* Initial development of this code was funded by
* MICRONIC Computer Systeme GmbH, https://www.mcsberlin.de/
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include "max9850.h"
struct max9850_priv {
struct regmap *regmap;
unsigned int sysclk;
};
/* these registers are not used at the moment but provided for the sake of
* completeness */
static bool max9850_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX9850_STATUSA:
case MAX9850_STATUSB:
return true;
default:
return false;
}
}
static const struct regmap_config max9850_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = MAX9850_DIGITAL_AUDIO,
.volatile_reg = max9850_volatile_register,
.cache_type = REGCACHE_RBTREE,
};
static const DECLARE_TLV_DB_RANGE(max9850_tlv,
0x18, 0x1f, TLV_DB_SCALE_ITEM(-7450, 400, 0),
0x20, 0x33, TLV_DB_SCALE_ITEM(-4150, 200, 0),
0x34, 0x37, TLV_DB_SCALE_ITEM(-150, 100, 0),
0x38, 0x3f, TLV_DB_SCALE_ITEM(250, 50, 0)
);
static const struct snd_kcontrol_new max9850_controls[] = {
SOC_SINGLE_TLV("Headphone Volume", MAX9850_VOLUME, 0, 0x3f, 1, max9850_tlv),
SOC_SINGLE("Headphone Switch", MAX9850_VOLUME, 7, 1, 1),
SOC_SINGLE("Mono Switch", MAX9850_GENERAL_PURPOSE, 2, 1, 0),
};
static const struct snd_kcontrol_new max9850_mixer_controls[] = {
SOC_DAPM_SINGLE("Line In Switch", MAX9850_ENABLE, 1, 1, 0),
};
static const struct snd_soc_dapm_widget max9850_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("Charge Pump 1", MAX9850_ENABLE, 4, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Charge Pump 2", MAX9850_ENABLE, 5, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MCLK", MAX9850_ENABLE, 6, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("SHDN", MAX9850_ENABLE, 7, 0, NULL, 0),
SND_SOC_DAPM_MIXER_NAMED_CTL("Output Mixer", MAX9850_ENABLE, 2, 0,
&max9850_mixer_controls[0],
ARRAY_SIZE(max9850_mixer_controls)),
SND_SOC_DAPM_PGA("Headphone Output", MAX9850_ENABLE, 3, 0, NULL, 0),
SND_SOC_DAPM_DAC("DAC", "HiFi Playback", MAX9850_ENABLE, 0, 0),
SND_SOC_DAPM_OUTPUT("OUTL"),
SND_SOC_DAPM_OUTPUT("HPL"),
SND_SOC_DAPM_OUTPUT("OUTR"),
SND_SOC_DAPM_OUTPUT("HPR"),
SND_SOC_DAPM_MIXER("Line Input", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_INPUT("INL"),
SND_SOC_DAPM_INPUT("INR"),
};
static const struct snd_soc_dapm_route max9850_dapm_routes[] = {
/* output mixer */
{"Output Mixer", NULL, "DAC"},
{"Output Mixer", "Line In Switch", "Line Input"},
/* outputs */
{"Headphone Output", NULL, "Output Mixer"},
{"HPL", NULL, "Headphone Output"},
{"HPR", NULL, "Headphone Output"},
{"OUTL", NULL, "Output Mixer"},
{"OUTR", NULL, "Output Mixer"},
/* inputs */
{"Line Input", NULL, "INL"},
{"Line Input", NULL, "INR"},
/* supplies */
{"Output Mixer", NULL, "Charge Pump 1"},
{"Output Mixer", NULL, "Charge Pump 2"},
{"Output Mixer", NULL, "SHDN"},
{"DAC", NULL, "MCLK"},
};
static int max9850_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct max9850_priv *max9850 = snd_soc_component_get_drvdata(component);
u64 lrclk_div;
u8 sf, da;
if (!max9850->sysclk)
return -EINVAL;
/* lrclk_div = 2^22 * rate / iclk with iclk = mclk / sf */
sf = (snd_soc_component_read(component, MAX9850_CLOCK) >> 2) + 1;
lrclk_div = (1 << 22);
lrclk_div *= params_rate(params);
lrclk_div *= sf;
do_div(lrclk_div, max9850->sysclk);
snd_soc_component_write(component, MAX9850_LRCLK_MSB, (lrclk_div >> 8) & 0x7f);
snd_soc_component_write(component, MAX9850_LRCLK_LSB, lrclk_div & 0xff);
switch (params_width(params)) {
case 16:
da = 0;
break;
case 20:
da = 0x2;
break;
case 24:
da = 0x3;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, MAX9850_DIGITAL_AUDIO, 0x3, da);
return 0;
}
static int max9850_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct max9850_priv *max9850 = snd_soc_component_get_drvdata(component);
/* calculate mclk -> iclk divider */
if (freq <= 13000000)
snd_soc_component_write(component, MAX9850_CLOCK, 0x0);
else if (freq <= 26000000)
snd_soc_component_write(component, MAX9850_CLOCK, 0x4);
else if (freq <= 40000000)
snd_soc_component_write(component, MAX9850_CLOCK, 0x8);
else
return -EINVAL;
max9850->sysclk = freq;
return 0;
}
static int max9850_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
u8 da = 0;
/* set clock provider for audio interface */
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
da |= MAX9850_MASTER;
break;
case SND_SOC_DAIFMT_CBC_CFC:
break;
default:
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
da |= MAX9850_DLY;
break;
case SND_SOC_DAIFMT_RIGHT_J:
da |= MAX9850_RTJ;
break;
case SND_SOC_DAIFMT_LEFT_J:
break;
default:
return -EINVAL;
}
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
da |= MAX9850_BCINV | MAX9850_INV;
break;
case SND_SOC_DAIFMT_IB_NF:
da |= MAX9850_BCINV;
break;
case SND_SOC_DAIFMT_NB_IF:
da |= MAX9850_INV;
break;
default:
return -EINVAL;
}
/* set da */
snd_soc_component_write(component, MAX9850_DIGITAL_AUDIO, da);
return 0;
}
static int max9850_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct max9850_priv *max9850 = snd_soc_component_get_drvdata(component);
int ret;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
ret = regcache_sync(max9850->regmap);
if (ret) {
dev_err(component->dev,
"Failed to sync cache: %d\n", ret);
return ret;
}
}
break;
case SND_SOC_BIAS_OFF:
break;
}
return 0;
}
#define MAX9850_RATES SNDRV_PCM_RATE_8000_48000
#define MAX9850_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE)
static const struct snd_soc_dai_ops max9850_dai_ops = {
.hw_params = max9850_hw_params,
.set_sysclk = max9850_set_dai_sysclk,
.set_fmt = max9850_set_dai_fmt,
};
static struct snd_soc_dai_driver max9850_dai = {
.name = "max9850-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MAX9850_RATES,
.formats = MAX9850_FORMATS
},
.ops = &max9850_dai_ops,
};
static int max9850_probe(struct snd_soc_component *component)
{
/* enable zero-detect */
snd_soc_component_update_bits(component, MAX9850_GENERAL_PURPOSE, 1, 1);
/* enable slew-rate control */
snd_soc_component_update_bits(component, MAX9850_VOLUME, 0x40, 0x40);
/* set slew-rate 125ms */
snd_soc_component_update_bits(component, MAX9850_CHARGE_PUMP, 0xff, 0xc0);
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_max9850 = {
.probe = max9850_probe,
.set_bias_level = max9850_set_bias_level,
.controls = max9850_controls,
.num_controls = ARRAY_SIZE(max9850_controls),
.dapm_widgets = max9850_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(max9850_dapm_widgets),
.dapm_routes = max9850_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(max9850_dapm_routes),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int max9850_i2c_probe(struct i2c_client *i2c)
{
struct max9850_priv *max9850;
int ret;
max9850 = devm_kzalloc(&i2c->dev, sizeof(struct max9850_priv),
GFP_KERNEL);
if (max9850 == NULL)
return -ENOMEM;
max9850->regmap = devm_regmap_init_i2c(i2c, &max9850_regmap);
if (IS_ERR(max9850->regmap))
return PTR_ERR(max9850->regmap);
i2c_set_clientdata(i2c, max9850);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_max9850, &max9850_dai, 1);
return ret;
}
static const struct i2c_device_id max9850_i2c_id[] = {
{ "max9850", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, max9850_i2c_id);
static struct i2c_driver max9850_i2c_driver = {
.driver = {
.name = "max9850",
},
.probe = max9850_i2c_probe,
.id_table = max9850_i2c_id,
};
module_i2c_driver(max9850_i2c_driver);
MODULE_AUTHOR("Christian Glindkamp <[email protected]>");
MODULE_DESCRIPTION("ASoC MAX9850 codec driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/max9850.c |
// SPDX-License-Identifier: GPL-2.0
// ak4554.c
//
// Copyright (C) 2013 Renesas Solutions Corp.
// Kuninori Morimoto <[email protected]>
#include <linux/module.h>
#include <sound/soc.h>
/*
* ak4554 is very simple DA/AD converter which has no setting register.
*
* CAUTION
*
* ak4554 playback format is SND_SOC_DAIFMT_RIGHT_J,
* and, capture format is SND_SOC_DAIFMT_LEFT_J
* on same bit clock, LR clock.
* But, this driver doesn't have snd_soc_dai_ops :: set_fmt
*
* CPU/Codec DAI image
*
* CPU-DAI1 (plaback only fmt = RIGHT_J) --+-- ak4554
* |
* CPU-DAI2 (capture only fmt = LEFT_J) ---+
*/
static const struct snd_soc_dapm_widget ak4554_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("AINL"),
SND_SOC_DAPM_INPUT("AINR"),
SND_SOC_DAPM_OUTPUT("AOUTL"),
SND_SOC_DAPM_OUTPUT("AOUTR"),
};
static const struct snd_soc_dapm_route ak4554_dapm_routes[] = {
{ "Capture", NULL, "AINL" },
{ "Capture", NULL, "AINR" },
{ "AOUTL", NULL, "Playback" },
{ "AOUTR", NULL, "Playback" },
};
static struct snd_soc_dai_driver ak4554_dai = {
.name = "ak4554-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.symmetric_rate = 1,
};
static const struct snd_soc_component_driver soc_component_dev_ak4554 = {
.dapm_widgets = ak4554_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(ak4554_dapm_widgets),
.dapm_routes = ak4554_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(ak4554_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int ak4554_soc_probe(struct platform_device *pdev)
{
return devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_ak4554,
&ak4554_dai, 1);
}
static const struct of_device_id ak4554_of_match[] = {
{ .compatible = "asahi-kasei,ak4554" },
{},
};
MODULE_DEVICE_TABLE(of, ak4554_of_match);
static struct platform_driver ak4554_driver = {
.driver = {
.name = "ak4554-adc-dac",
.of_match_table = ak4554_of_match,
},
.probe = ak4554_soc_probe,
};
module_platform_driver(ak4554_driver);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("SoC AK4554 driver");
MODULE_AUTHOR("Kuninori Morimoto <[email protected]>");
| linux-master | sound/soc/codecs/ak4554.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* ADAV80X Audio Codec driver supporting ADAV801, ADAV803
*
* Copyright 2011 Analog Devices Inc.
* Author: Yi Li <[email protected]>
* Author: Lars-Peter Clausen <[email protected]>
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include "adav80x.h"
#define ADAV80X_PLAYBACK_CTRL 0x04
#define ADAV80X_AUX_IN_CTRL 0x05
#define ADAV80X_REC_CTRL 0x06
#define ADAV80X_AUX_OUT_CTRL 0x07
#define ADAV80X_DPATH_CTRL1 0x62
#define ADAV80X_DPATH_CTRL2 0x63
#define ADAV80X_DAC_CTRL1 0x64
#define ADAV80X_DAC_CTRL2 0x65
#define ADAV80X_DAC_CTRL3 0x66
#define ADAV80X_DAC_L_VOL 0x68
#define ADAV80X_DAC_R_VOL 0x69
#define ADAV80X_PGA_L_VOL 0x6c
#define ADAV80X_PGA_R_VOL 0x6d
#define ADAV80X_ADC_CTRL1 0x6e
#define ADAV80X_ADC_CTRL2 0x6f
#define ADAV80X_ADC_L_VOL 0x70
#define ADAV80X_ADC_R_VOL 0x71
#define ADAV80X_PLL_CTRL1 0x74
#define ADAV80X_PLL_CTRL2 0x75
#define ADAV80X_ICLK_CTRL1 0x76
#define ADAV80X_ICLK_CTRL2 0x77
#define ADAV80X_PLL_CLK_SRC 0x78
#define ADAV80X_PLL_OUTE 0x7a
#define ADAV80X_PLL_CLK_SRC_PLL_XIN(pll) 0x00
#define ADAV80X_PLL_CLK_SRC_PLL_MCLKI(pll) (0x40 << (pll))
#define ADAV80X_PLL_CLK_SRC_PLL_MASK(pll) (0x40 << (pll))
#define ADAV80X_ICLK_CTRL1_DAC_SRC(src) ((src) << 5)
#define ADAV80X_ICLK_CTRL1_ADC_SRC(src) ((src) << 2)
#define ADAV80X_ICLK_CTRL1_ICLK2_SRC(src) (src)
#define ADAV80X_ICLK_CTRL2_ICLK1_SRC(src) ((src) << 3)
#define ADAV80X_PLL_CTRL1_PLLDIV 0x10
#define ADAV80X_PLL_CTRL1_PLLPD(pll) (0x04 << (pll))
#define ADAV80X_PLL_CTRL1_XTLPD 0x02
#define ADAV80X_PLL_CTRL2_FIELD(pll, x) ((x) << ((pll) * 4))
#define ADAV80X_PLL_CTRL2_FS_48(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x00)
#define ADAV80X_PLL_CTRL2_FS_32(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x08)
#define ADAV80X_PLL_CTRL2_FS_44(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x0c)
#define ADAV80X_PLL_CTRL2_SEL(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x02)
#define ADAV80X_PLL_CTRL2_DOUB(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x01)
#define ADAV80X_PLL_CTRL2_PLL_MASK(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x0f)
#define ADAV80X_ADC_CTRL1_MODULATOR_MASK 0x80
#define ADAV80X_ADC_CTRL1_MODULATOR_128FS 0x00
#define ADAV80X_ADC_CTRL1_MODULATOR_64FS 0x80
#define ADAV80X_DAC_CTRL1_PD 0x80
#define ADAV80X_DAC_CTRL2_DIV1 0x00
#define ADAV80X_DAC_CTRL2_DIV1_5 0x10
#define ADAV80X_DAC_CTRL2_DIV2 0x20
#define ADAV80X_DAC_CTRL2_DIV3 0x30
#define ADAV80X_DAC_CTRL2_DIV_MASK 0x30
#define ADAV80X_DAC_CTRL2_INTERPOL_256FS 0x00
#define ADAV80X_DAC_CTRL2_INTERPOL_128FS 0x40
#define ADAV80X_DAC_CTRL2_INTERPOL_64FS 0x80
#define ADAV80X_DAC_CTRL2_INTERPOL_MASK 0xc0
#define ADAV80X_DAC_CTRL2_DEEMPH_NONE 0x00
#define ADAV80X_DAC_CTRL2_DEEMPH_44 0x01
#define ADAV80X_DAC_CTRL2_DEEMPH_32 0x02
#define ADAV80X_DAC_CTRL2_DEEMPH_48 0x03
#define ADAV80X_DAC_CTRL2_DEEMPH_MASK 0x01
#define ADAV80X_CAPTURE_MODE_MASTER 0x20
#define ADAV80X_CAPTURE_WORD_LEN24 0x00
#define ADAV80X_CAPTURE_WORD_LEN20 0x04
#define ADAV80X_CAPTRUE_WORD_LEN18 0x08
#define ADAV80X_CAPTURE_WORD_LEN16 0x0c
#define ADAV80X_CAPTURE_WORD_LEN_MASK 0x0c
#define ADAV80X_CAPTURE_MODE_LEFT_J 0x00
#define ADAV80X_CAPTURE_MODE_I2S 0x01
#define ADAV80X_CAPTURE_MODE_RIGHT_J 0x03
#define ADAV80X_CAPTURE_MODE_MASK 0x03
#define ADAV80X_PLAYBACK_MODE_MASTER 0x10
#define ADAV80X_PLAYBACK_MODE_LEFT_J 0x00
#define ADAV80X_PLAYBACK_MODE_I2S 0x01
#define ADAV80X_PLAYBACK_MODE_RIGHT_J_24 0x04
#define ADAV80X_PLAYBACK_MODE_RIGHT_J_20 0x05
#define ADAV80X_PLAYBACK_MODE_RIGHT_J_18 0x06
#define ADAV80X_PLAYBACK_MODE_RIGHT_J_16 0x07
#define ADAV80X_PLAYBACK_MODE_MASK 0x07
#define ADAV80X_PLL_OUTE_SYSCLKPD(x) BIT(2 - (x))
static const struct reg_default adav80x_reg_defaults[] = {
{ ADAV80X_PLAYBACK_CTRL, 0x01 },
{ ADAV80X_AUX_IN_CTRL, 0x01 },
{ ADAV80X_REC_CTRL, 0x02 },
{ ADAV80X_AUX_OUT_CTRL, 0x01 },
{ ADAV80X_DPATH_CTRL1, 0xc0 },
{ ADAV80X_DPATH_CTRL2, 0x11 },
{ ADAV80X_DAC_CTRL1, 0x00 },
{ ADAV80X_DAC_CTRL2, 0x00 },
{ ADAV80X_DAC_CTRL3, 0x00 },
{ ADAV80X_DAC_L_VOL, 0xff },
{ ADAV80X_DAC_R_VOL, 0xff },
{ ADAV80X_PGA_L_VOL, 0x00 },
{ ADAV80X_PGA_R_VOL, 0x00 },
{ ADAV80X_ADC_CTRL1, 0x00 },
{ ADAV80X_ADC_CTRL2, 0x00 },
{ ADAV80X_ADC_L_VOL, 0xff },
{ ADAV80X_ADC_R_VOL, 0xff },
{ ADAV80X_PLL_CTRL1, 0x00 },
{ ADAV80X_PLL_CTRL2, 0x00 },
{ ADAV80X_ICLK_CTRL1, 0x00 },
{ ADAV80X_ICLK_CTRL2, 0x00 },
{ ADAV80X_PLL_CLK_SRC, 0x00 },
{ ADAV80X_PLL_OUTE, 0x00 },
};
struct adav80x {
struct regmap *regmap;
enum adav80x_clk_src clk_src;
unsigned int sysclk;
enum adav80x_pll_src pll_src;
unsigned int dai_fmt[2];
unsigned int rate;
bool deemph;
bool sysclk_pd[3];
};
static const char *adav80x_mux_text[] = {
"ADC",
"Playback",
"Aux Playback",
};
static const unsigned int adav80x_mux_values[] = {
0, 2, 3,
};
#define ADAV80X_MUX_ENUM_DECL(name, reg, shift) \
SOC_VALUE_ENUM_DOUBLE_DECL(name, reg, shift, 7, \
ARRAY_SIZE(adav80x_mux_text), adav80x_mux_text, \
adav80x_mux_values)
static ADAV80X_MUX_ENUM_DECL(adav80x_aux_capture_enum, ADAV80X_DPATH_CTRL1, 0);
static ADAV80X_MUX_ENUM_DECL(adav80x_capture_enum, ADAV80X_DPATH_CTRL1, 3);
static ADAV80X_MUX_ENUM_DECL(adav80x_dac_enum, ADAV80X_DPATH_CTRL2, 3);
static const struct snd_kcontrol_new adav80x_aux_capture_mux_ctrl =
SOC_DAPM_ENUM("Route", adav80x_aux_capture_enum);
static const struct snd_kcontrol_new adav80x_capture_mux_ctrl =
SOC_DAPM_ENUM("Route", adav80x_capture_enum);
static const struct snd_kcontrol_new adav80x_dac_mux_ctrl =
SOC_DAPM_ENUM("Route", adav80x_dac_enum);
#define ADAV80X_MUX(name, ctrl) \
SND_SOC_DAPM_MUX(name, SND_SOC_NOPM, 0, 0, ctrl)
static const struct snd_soc_dapm_widget adav80x_dapm_widgets[] = {
SND_SOC_DAPM_DAC("DAC", NULL, ADAV80X_DAC_CTRL1, 7, 1),
SND_SOC_DAPM_ADC("ADC", NULL, ADAV80X_ADC_CTRL1, 5, 1),
SND_SOC_DAPM_PGA("Right PGA", ADAV80X_ADC_CTRL1, 0, 1, NULL, 0),
SND_SOC_DAPM_PGA("Left PGA", ADAV80X_ADC_CTRL1, 1, 1, NULL, 0),
SND_SOC_DAPM_AIF_OUT("AIFOUT", "HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIFIN", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIFAUXOUT", "Aux Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIFAUXIN", "Aux Playback", 0, SND_SOC_NOPM, 0, 0),
ADAV80X_MUX("Aux Capture Select", &adav80x_aux_capture_mux_ctrl),
ADAV80X_MUX("Capture Select", &adav80x_capture_mux_ctrl),
ADAV80X_MUX("DAC Select", &adav80x_dac_mux_ctrl),
SND_SOC_DAPM_INPUT("VINR"),
SND_SOC_DAPM_INPUT("VINL"),
SND_SOC_DAPM_OUTPUT("VOUTR"),
SND_SOC_DAPM_OUTPUT("VOUTL"),
SND_SOC_DAPM_SUPPLY("SYSCLK", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PLL1", ADAV80X_PLL_CTRL1, 2, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("PLL2", ADAV80X_PLL_CTRL1, 3, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("OSC", ADAV80X_PLL_CTRL1, 1, 1, NULL, 0),
};
static int adav80x_dapm_sysclk_check(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
const char *clk;
switch (adav80x->clk_src) {
case ADAV80X_CLK_PLL1:
clk = "PLL1";
break;
case ADAV80X_CLK_PLL2:
clk = "PLL2";
break;
case ADAV80X_CLK_XTAL:
clk = "OSC";
break;
default:
return 0;
}
return strcmp(source->name, clk) == 0;
}
static int adav80x_dapm_pll_check(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
return adav80x->pll_src == ADAV80X_PLL_SRC_XTAL;
}
static const struct snd_soc_dapm_route adav80x_dapm_routes[] = {
{ "DAC Select", "ADC", "ADC" },
{ "DAC Select", "Playback", "AIFIN" },
{ "DAC Select", "Aux Playback", "AIFAUXIN" },
{ "DAC", NULL, "DAC Select" },
{ "Capture Select", "ADC", "ADC" },
{ "Capture Select", "Playback", "AIFIN" },
{ "Capture Select", "Aux Playback", "AIFAUXIN" },
{ "AIFOUT", NULL, "Capture Select" },
{ "Aux Capture Select", "ADC", "ADC" },
{ "Aux Capture Select", "Playback", "AIFIN" },
{ "Aux Capture Select", "Aux Playback", "AIFAUXIN" },
{ "AIFAUXOUT", NULL, "Aux Capture Select" },
{ "VOUTR", NULL, "DAC" },
{ "VOUTL", NULL, "DAC" },
{ "Left PGA", NULL, "VINL" },
{ "Right PGA", NULL, "VINR" },
{ "ADC", NULL, "Left PGA" },
{ "ADC", NULL, "Right PGA" },
{ "SYSCLK", NULL, "PLL1", adav80x_dapm_sysclk_check },
{ "SYSCLK", NULL, "PLL2", adav80x_dapm_sysclk_check },
{ "SYSCLK", NULL, "OSC", adav80x_dapm_sysclk_check },
{ "PLL1", NULL, "OSC", adav80x_dapm_pll_check },
{ "PLL2", NULL, "OSC", adav80x_dapm_pll_check },
{ "ADC", NULL, "SYSCLK" },
{ "DAC", NULL, "SYSCLK" },
{ "AIFOUT", NULL, "SYSCLK" },
{ "AIFAUXOUT", NULL, "SYSCLK" },
{ "AIFIN", NULL, "SYSCLK" },
{ "AIFAUXIN", NULL, "SYSCLK" },
};
static int adav80x_set_deemph(struct snd_soc_component *component)
{
struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
unsigned int val;
if (adav80x->deemph) {
switch (adav80x->rate) {
case 32000:
val = ADAV80X_DAC_CTRL2_DEEMPH_32;
break;
case 44100:
val = ADAV80X_DAC_CTRL2_DEEMPH_44;
break;
case 48000:
case 64000:
case 88200:
case 96000:
val = ADAV80X_DAC_CTRL2_DEEMPH_48;
break;
default:
val = ADAV80X_DAC_CTRL2_DEEMPH_NONE;
break;
}
} else {
val = ADAV80X_DAC_CTRL2_DEEMPH_NONE;
}
return regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL2,
ADAV80X_DAC_CTRL2_DEEMPH_MASK, val);
}
static int adav80x_put_deemph(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
unsigned int deemph = ucontrol->value.integer.value[0];
if (deemph > 1)
return -EINVAL;
adav80x->deemph = deemph;
return adav80x_set_deemph(component);
}
static int adav80x_get_deemph(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = adav80x->deemph;
return 0;
};
static const DECLARE_TLV_DB_SCALE(adav80x_inpga_tlv, 0, 50, 0);
static const DECLARE_TLV_DB_MINMAX(adav80x_digital_tlv, -9563, 0);
static const struct snd_kcontrol_new adav80x_controls[] = {
SOC_DOUBLE_R_TLV("Master Playback Volume", ADAV80X_DAC_L_VOL,
ADAV80X_DAC_R_VOL, 0, 0xff, 0, adav80x_digital_tlv),
SOC_DOUBLE_R_TLV("Master Capture Volume", ADAV80X_ADC_L_VOL,
ADAV80X_ADC_R_VOL, 0, 0xff, 0, adav80x_digital_tlv),
SOC_DOUBLE_R_TLV("PGA Capture Volume", ADAV80X_PGA_L_VOL,
ADAV80X_PGA_R_VOL, 0, 0x30, 0, adav80x_inpga_tlv),
SOC_DOUBLE("Master Playback Switch", ADAV80X_DAC_CTRL1, 0, 1, 1, 0),
SOC_DOUBLE("Master Capture Switch", ADAV80X_ADC_CTRL1, 2, 3, 1, 1),
SOC_SINGLE("ADC High Pass Filter Switch", ADAV80X_ADC_CTRL1, 6, 1, 0),
SOC_SINGLE_BOOL_EXT("Playback De-emphasis Switch", 0,
adav80x_get_deemph, adav80x_put_deemph),
};
static unsigned int adav80x_port_ctrl_regs[2][2] = {
{ ADAV80X_REC_CTRL, ADAV80X_PLAYBACK_CTRL, },
{ ADAV80X_AUX_OUT_CTRL, ADAV80X_AUX_IN_CTRL },
};
static int adav80x_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
unsigned int capture = 0x00;
unsigned int playback = 0x00;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
capture |= ADAV80X_CAPTURE_MODE_MASTER;
playback |= ADAV80X_PLAYBACK_MODE_MASTER;
break;
case SND_SOC_DAIFMT_CBC_CFC:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
capture |= ADAV80X_CAPTURE_MODE_I2S;
playback |= ADAV80X_PLAYBACK_MODE_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
capture |= ADAV80X_CAPTURE_MODE_LEFT_J;
playback |= ADAV80X_PLAYBACK_MODE_LEFT_J;
break;
case SND_SOC_DAIFMT_RIGHT_J:
capture |= ADAV80X_CAPTURE_MODE_RIGHT_J;
playback |= ADAV80X_PLAYBACK_MODE_RIGHT_J_24;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
default:
return -EINVAL;
}
regmap_update_bits(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][0],
ADAV80X_CAPTURE_MODE_MASK | ADAV80X_CAPTURE_MODE_MASTER,
capture);
regmap_write(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][1],
playback);
adav80x->dai_fmt[dai->id] = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
return 0;
}
static int adav80x_set_adc_clock(struct snd_soc_component *component,
unsigned int sample_rate)
{
struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
unsigned int val;
if (sample_rate <= 48000)
val = ADAV80X_ADC_CTRL1_MODULATOR_128FS;
else
val = ADAV80X_ADC_CTRL1_MODULATOR_64FS;
regmap_update_bits(adav80x->regmap, ADAV80X_ADC_CTRL1,
ADAV80X_ADC_CTRL1_MODULATOR_MASK, val);
return 0;
}
static int adav80x_set_dac_clock(struct snd_soc_component *component,
unsigned int sample_rate)
{
struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
unsigned int val;
if (sample_rate <= 48000)
val = ADAV80X_DAC_CTRL2_DIV1 | ADAV80X_DAC_CTRL2_INTERPOL_256FS;
else
val = ADAV80X_DAC_CTRL2_DIV2 | ADAV80X_DAC_CTRL2_INTERPOL_128FS;
regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL2,
ADAV80X_DAC_CTRL2_DIV_MASK | ADAV80X_DAC_CTRL2_INTERPOL_MASK,
val);
return 0;
}
static int adav80x_set_capture_pcm_format(struct snd_soc_component *component,
struct snd_soc_dai *dai, struct snd_pcm_hw_params *params)
{
struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
unsigned int val;
switch (params_width(params)) {
case 16:
val = ADAV80X_CAPTURE_WORD_LEN16;
break;
case 18:
val = ADAV80X_CAPTRUE_WORD_LEN18;
break;
case 20:
val = ADAV80X_CAPTURE_WORD_LEN20;
break;
case 24:
val = ADAV80X_CAPTURE_WORD_LEN24;
break;
default:
return -EINVAL;
}
regmap_update_bits(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][0],
ADAV80X_CAPTURE_WORD_LEN_MASK, val);
return 0;
}
static int adav80x_set_playback_pcm_format(struct snd_soc_component *component,
struct snd_soc_dai *dai, struct snd_pcm_hw_params *params)
{
struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
unsigned int val;
if (adav80x->dai_fmt[dai->id] != SND_SOC_DAIFMT_RIGHT_J)
return 0;
switch (params_width(params)) {
case 16:
val = ADAV80X_PLAYBACK_MODE_RIGHT_J_16;
break;
case 18:
val = ADAV80X_PLAYBACK_MODE_RIGHT_J_18;
break;
case 20:
val = ADAV80X_PLAYBACK_MODE_RIGHT_J_20;
break;
case 24:
val = ADAV80X_PLAYBACK_MODE_RIGHT_J_24;
break;
default:
return -EINVAL;
}
regmap_update_bits(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][1],
ADAV80X_PLAYBACK_MODE_MASK, val);
return 0;
}
static int adav80x_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
unsigned int rate = params_rate(params);
if (rate * 256 != adav80x->sysclk)
return -EINVAL;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
adav80x_set_playback_pcm_format(component, dai, params);
adav80x_set_dac_clock(component, rate);
} else {
adav80x_set_capture_pcm_format(component, dai, params);
adav80x_set_adc_clock(component, rate);
}
adav80x->rate = rate;
adav80x_set_deemph(component);
return 0;
}
static int adav80x_set_sysclk(struct snd_soc_component *component,
int clk_id, int source,
unsigned int freq, int dir)
{
struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
if (dir == SND_SOC_CLOCK_IN) {
switch (clk_id) {
case ADAV80X_CLK_XIN:
case ADAV80X_CLK_XTAL:
case ADAV80X_CLK_MCLKI:
case ADAV80X_CLK_PLL1:
case ADAV80X_CLK_PLL2:
break;
default:
return -EINVAL;
}
adav80x->sysclk = freq;
if (adav80x->clk_src != clk_id) {
unsigned int iclk_ctrl1, iclk_ctrl2;
adav80x->clk_src = clk_id;
if (clk_id == ADAV80X_CLK_XTAL)
clk_id = ADAV80X_CLK_XIN;
iclk_ctrl1 = ADAV80X_ICLK_CTRL1_DAC_SRC(clk_id) |
ADAV80X_ICLK_CTRL1_ADC_SRC(clk_id) |
ADAV80X_ICLK_CTRL1_ICLK2_SRC(clk_id);
iclk_ctrl2 = ADAV80X_ICLK_CTRL2_ICLK1_SRC(clk_id);
regmap_write(adav80x->regmap, ADAV80X_ICLK_CTRL1,
iclk_ctrl1);
regmap_write(adav80x->regmap, ADAV80X_ICLK_CTRL2,
iclk_ctrl2);
snd_soc_dapm_sync(dapm);
}
} else {
unsigned int mask;
switch (clk_id) {
case ADAV80X_CLK_SYSCLK1:
case ADAV80X_CLK_SYSCLK2:
case ADAV80X_CLK_SYSCLK3:
break;
default:
return -EINVAL;
}
clk_id -= ADAV80X_CLK_SYSCLK1;
mask = ADAV80X_PLL_OUTE_SYSCLKPD(clk_id);
if (freq == 0) {
regmap_update_bits(adav80x->regmap, ADAV80X_PLL_OUTE,
mask, mask);
adav80x->sysclk_pd[clk_id] = true;
} else {
regmap_update_bits(adav80x->regmap, ADAV80X_PLL_OUTE,
mask, 0);
adav80x->sysclk_pd[clk_id] = false;
}
snd_soc_dapm_mutex_lock(dapm);
if (adav80x->sysclk_pd[0])
snd_soc_dapm_disable_pin_unlocked(dapm, "PLL1");
else
snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL1");
if (adav80x->sysclk_pd[1] || adav80x->sysclk_pd[2])
snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2");
else
snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2");
snd_soc_dapm_sync_unlocked(dapm);
snd_soc_dapm_mutex_unlock(dapm);
}
return 0;
}
static int adav80x_set_pll(struct snd_soc_component *component, int pll_id,
int source, unsigned int freq_in, unsigned int freq_out)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
unsigned int pll_ctrl1 = 0;
unsigned int pll_ctrl2 = 0;
unsigned int pll_src;
switch (source) {
case ADAV80X_PLL_SRC_XTAL:
case ADAV80X_PLL_SRC_XIN:
case ADAV80X_PLL_SRC_MCLKI:
break;
default:
return -EINVAL;
}
if (!freq_out)
return 0;
switch (freq_in) {
case 27000000:
break;
case 54000000:
if (source == ADAV80X_PLL_SRC_XIN) {
pll_ctrl1 |= ADAV80X_PLL_CTRL1_PLLDIV;
break;
}
fallthrough;
default:
return -EINVAL;
}
if (freq_out > 12288000) {
pll_ctrl2 |= ADAV80X_PLL_CTRL2_DOUB(pll_id);
freq_out /= 2;
}
/* freq_out = sample_rate * 256 */
switch (freq_out) {
case 8192000:
pll_ctrl2 |= ADAV80X_PLL_CTRL2_FS_32(pll_id);
break;
case 11289600:
pll_ctrl2 |= ADAV80X_PLL_CTRL2_FS_44(pll_id);
break;
case 12288000:
pll_ctrl2 |= ADAV80X_PLL_CTRL2_FS_48(pll_id);
break;
default:
return -EINVAL;
}
regmap_update_bits(adav80x->regmap, ADAV80X_PLL_CTRL1,
ADAV80X_PLL_CTRL1_PLLDIV, pll_ctrl1);
regmap_update_bits(adav80x->regmap, ADAV80X_PLL_CTRL2,
ADAV80X_PLL_CTRL2_PLL_MASK(pll_id), pll_ctrl2);
if (source != adav80x->pll_src) {
if (source == ADAV80X_PLL_SRC_MCLKI)
pll_src = ADAV80X_PLL_CLK_SRC_PLL_MCLKI(pll_id);
else
pll_src = ADAV80X_PLL_CLK_SRC_PLL_XIN(pll_id);
regmap_update_bits(adav80x->regmap, ADAV80X_PLL_CLK_SRC,
ADAV80X_PLL_CLK_SRC_PLL_MASK(pll_id), pll_src);
adav80x->pll_src = source;
snd_soc_dapm_sync(dapm);
}
return 0;
}
static int adav80x_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
unsigned int mask = ADAV80X_DAC_CTRL1_PD;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL1, mask,
0x00);
break;
case SND_SOC_BIAS_OFF:
regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL1, mask,
mask);
break;
}
return 0;
}
/* Enforce the same sample rate on all audio interfaces */
static int adav80x_dai_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
if (!snd_soc_component_active(component) || !adav80x->rate)
return 0;
return snd_pcm_hw_constraint_single(substream->runtime,
SNDRV_PCM_HW_PARAM_RATE, adav80x->rate);
}
static void adav80x_dai_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
if (!snd_soc_component_active(component))
adav80x->rate = 0;
}
static const struct snd_soc_dai_ops adav80x_dai_ops = {
.set_fmt = adav80x_set_dai_fmt,
.hw_params = adav80x_hw_params,
.startup = adav80x_dai_startup,
.shutdown = adav80x_dai_shutdown,
};
#define ADAV80X_PLAYBACK_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | \
SNDRV_PCM_RATE_96000)
#define ADAV80X_CAPTURE_RATES (SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000)
#define ADAV80X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \
SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE)
static struct snd_soc_dai_driver adav80x_dais[] = {
{
.name = "adav80x-hifi",
.id = 0,
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 2,
.channels_max = 2,
.rates = ADAV80X_PLAYBACK_RATES,
.formats = ADAV80X_FORMATS,
},
.capture = {
.stream_name = "HiFi Capture",
.channels_min = 2,
.channels_max = 2,
.rates = ADAV80X_CAPTURE_RATES,
.formats = ADAV80X_FORMATS,
},
.ops = &adav80x_dai_ops,
},
{
.name = "adav80x-aux",
.id = 1,
.playback = {
.stream_name = "Aux Playback",
.channels_min = 2,
.channels_max = 2,
.rates = ADAV80X_PLAYBACK_RATES,
.formats = ADAV80X_FORMATS,
},
.capture = {
.stream_name = "Aux Capture",
.channels_min = 2,
.channels_max = 2,
.rates = ADAV80X_CAPTURE_RATES,
.formats = ADAV80X_FORMATS,
},
.ops = &adav80x_dai_ops,
},
};
static int adav80x_probe(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
/* Force PLLs on for SYSCLK output */
snd_soc_dapm_force_enable_pin(dapm, "PLL1");
snd_soc_dapm_force_enable_pin(dapm, "PLL2");
/* Power down S/PDIF receiver, since it is currently not supported */
regmap_write(adav80x->regmap, ADAV80X_PLL_OUTE, 0x20);
/* Disable DAC zero flag */
regmap_write(adav80x->regmap, ADAV80X_DAC_CTRL3, 0x6);
return 0;
}
static int adav80x_resume(struct snd_soc_component *component)
{
struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
regcache_sync(adav80x->regmap);
return 0;
}
static const struct snd_soc_component_driver adav80x_component_driver = {
.probe = adav80x_probe,
.resume = adav80x_resume,
.set_bias_level = adav80x_set_bias_level,
.set_pll = adav80x_set_pll,
.set_sysclk = adav80x_set_sysclk,
.controls = adav80x_controls,
.num_controls = ARRAY_SIZE(adav80x_controls),
.dapm_widgets = adav80x_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(adav80x_dapm_widgets),
.dapm_routes = adav80x_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(adav80x_dapm_routes),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
int adav80x_bus_probe(struct device *dev, struct regmap *regmap)
{
struct adav80x *adav80x;
if (IS_ERR(regmap))
return PTR_ERR(regmap);
adav80x = devm_kzalloc(dev, sizeof(*adav80x), GFP_KERNEL);
if (!adav80x)
return -ENOMEM;
dev_set_drvdata(dev, adav80x);
adav80x->regmap = regmap;
return devm_snd_soc_register_component(dev, &adav80x_component_driver,
adav80x_dais, ARRAY_SIZE(adav80x_dais));
}
EXPORT_SYMBOL_GPL(adav80x_bus_probe);
const struct regmap_config adav80x_regmap_config = {
.val_bits = 8,
.pad_bits = 1,
.reg_bits = 7,
.max_register = ADAV80X_PLL_OUTE,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = adav80x_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(adav80x_reg_defaults),
};
EXPORT_SYMBOL_GPL(adav80x_regmap_config);
MODULE_DESCRIPTION("ASoC ADAV80x driver");
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_AUTHOR("Yi Li <[email protected]>>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/adav80x.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2019, Linaro Limited
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mfd/wcd934x/registers.h>
#include <linux/mfd/wcd934x/wcd934x.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of_clk.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <linux/slimbus.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/tlv.h>
#include "wcd-clsh-v2.h"
#include "wcd-mbhc-v2.h"
#define WCD934X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
/* Fractional Rates */
#define WCD934X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
SNDRV_PCM_RATE_176400)
#define WCD934X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE)
/* slave port water mark level
* (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes)
*/
#define SLAVE_PORT_WATER_MARK_6BYTES 0
#define SLAVE_PORT_WATER_MARK_9BYTES 1
#define SLAVE_PORT_WATER_MARK_12BYTES 2
#define SLAVE_PORT_WATER_MARK_15BYTES 3
#define SLAVE_PORT_WATER_MARK_SHIFT 1
#define SLAVE_PORT_ENABLE 1
#define SLAVE_PORT_DISABLE 0
#define WCD934X_SLIM_WATER_MARK_VAL \
((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \
(SLAVE_PORT_ENABLE))
#define WCD934X_SLIM_NUM_PORT_REG 3
#define WCD934X_SLIM_PGD_PORT_INT_TX_EN0 (WCD934X_SLIM_PGD_PORT_INT_EN0 + 2)
#define WCD934X_SLIM_IRQ_OVERFLOW BIT(0)
#define WCD934X_SLIM_IRQ_UNDERFLOW BIT(1)
#define WCD934X_SLIM_IRQ_PORT_CLOSED BIT(2)
#define WCD934X_MCLK_CLK_12P288MHZ 12288000
#define WCD934X_MCLK_CLK_9P6MHZ 9600000
/* Only valid for 9.6 MHz mclk */
#define WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ 2400000
#define WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ 4800000
/* Only valid for 12.288 MHz mclk */
#define WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ 4096000
#define WCD934X_DMIC_CLK_DIV_2 0x0
#define WCD934X_DMIC_CLK_DIV_3 0x1
#define WCD934X_DMIC_CLK_DIV_4 0x2
#define WCD934X_DMIC_CLK_DIV_6 0x3
#define WCD934X_DMIC_CLK_DIV_8 0x4
#define WCD934X_DMIC_CLK_DIV_16 0x5
#define WCD934X_DMIC_CLK_DRIVE_DEFAULT 0x02
#define TX_HPF_CUT_OFF_FREQ_MASK 0x60
#define CF_MIN_3DB_4HZ 0x0
#define CF_MIN_3DB_75HZ 0x1
#define CF_MIN_3DB_150HZ 0x2
#define WCD934X_RX_START 16
#define WCD934X_NUM_INTERPOLATORS 9
#define WCD934X_RX_PATH_CTL_OFFSET 20
#define WCD934X_MAX_VALID_ADC_MUX 13
#define WCD934X_INVALID_ADC_MUX 9
#define WCD934X_SLIM_RX_CH(p) \
{.port = p + WCD934X_RX_START, .shift = p,}
#define WCD934X_SLIM_TX_CH(p) \
{.port = p, .shift = p,}
/* Feature masks to distinguish codec version */
#define DSD_DISABLED_MASK 0
#define SLNQ_DISABLED_MASK 1
#define DSD_DISABLED BIT(DSD_DISABLED_MASK)
#define SLNQ_DISABLED BIT(SLNQ_DISABLED_MASK)
/* As fine version info cannot be retrieved before wcd probe.
* Define three coarse versions for possible future use before wcd probe.
*/
#define WCD_VERSION_WCD9340_1_0 0x400
#define WCD_VERSION_WCD9341_1_0 0x410
#define WCD_VERSION_WCD9340_1_1 0x401
#define WCD_VERSION_WCD9341_1_1 0x411
#define WCD934X_AMIC_PWR_LEVEL_LP 0
#define WCD934X_AMIC_PWR_LEVEL_DEFAULT 1
#define WCD934X_AMIC_PWR_LEVEL_HP 2
#define WCD934X_AMIC_PWR_LEVEL_HYBRID 3
#define WCD934X_AMIC_PWR_LVL_MASK 0x60
#define WCD934X_AMIC_PWR_LVL_SHIFT 0x5
#define WCD934X_DEC_PWR_LVL_MASK 0x06
#define WCD934X_DEC_PWR_LVL_LP 0x02
#define WCD934X_DEC_PWR_LVL_HP 0x04
#define WCD934X_DEC_PWR_LVL_DF 0x00
#define WCD934X_DEC_PWR_LVL_HYBRID WCD934X_DEC_PWR_LVL_DF
#define WCD934X_DEF_MICBIAS_MV 1800
#define WCD934X_MAX_MICBIAS_MV 2850
#define WCD_IIR_FILTER_SIZE (sizeof(u32) * BAND_MAX)
#define WCD_IIR_FILTER_CTL(xname, iidx, bidx) \
{ \
.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
.info = wcd934x_iir_filter_info, \
.get = wcd934x_get_iir_band_audio_mixer, \
.put = wcd934x_put_iir_band_audio_mixer, \
.private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \
.iir_idx = iidx, \
.band_idx = bidx, \
.bytes_ext = {.max = WCD_IIR_FILTER_SIZE, }, \
} \
}
/* Z value defined in milliohm */
#define WCD934X_ZDET_VAL_32 32000
#define WCD934X_ZDET_VAL_400 400000
#define WCD934X_ZDET_VAL_1200 1200000
#define WCD934X_ZDET_VAL_100K 100000000
/* Z floating defined in ohms */
#define WCD934X_ZDET_FLOATING_IMPEDANCE 0x0FFFFFFE
#define WCD934X_ZDET_NUM_MEASUREMENTS 900
#define WCD934X_MBHC_GET_C1(c) ((c & 0xC000) >> 14)
#define WCD934X_MBHC_GET_X1(x) (x & 0x3FFF)
/* Z value compared in milliOhm */
#define WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z) ((z > 400000) || (z < 32000))
#define WCD934X_MBHC_ZDET_CONST (86 * 16384)
#define WCD934X_MBHC_MOISTURE_RREF R_24_KOHM
#define WCD934X_MBHC_MAX_BUTTONS (8)
#define WCD_MBHC_HS_V_MAX 1600
#define WCD934X_INTERPOLATOR_PATH(id) \
{"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"}, \
{"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"}, \
{"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"}, \
{"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"}, \
{"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"}, \
{"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"}, \
{"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"}, \
{"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"}, \
{"RX INT" #id "_1 MIX1 INP0", "IIR0", "IIR0"}, \
{"RX INT" #id "_1 MIX1 INP0", "IIR1", "IIR1"}, \
{"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"}, \
{"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"}, \
{"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"}, \
{"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"}, \
{"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"}, \
{"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"}, \
{"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"}, \
{"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"}, \
{"RX INT" #id "_1 MIX1 INP1", "IIR0", "IIR0"}, \
{"RX INT" #id "_1 MIX1 INP1", "IIR1", "IIR1"}, \
{"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"}, \
{"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"}, \
{"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"}, \
{"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"}, \
{"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"}, \
{"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"}, \
{"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"}, \
{"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"}, \
{"RX INT" #id "_1 MIX1 INP2", "IIR0", "IIR0"}, \
{"RX INT" #id "_1 MIX1 INP2", "IIR1", "IIR1"}, \
{"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \
{"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \
{"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \
{"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \
{"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \
{"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \
{"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"}, \
{"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"}, \
{"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"}, \
{"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"}, \
{"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"}, \
{"RX INT" #id "_2 MUX", NULL, "INT" #id "_CLK"}, \
{"RX INT" #id "_2 MUX", NULL, "DSMDEM" #id "_CLK"}, \
{"RX INT" #id "_2 INTERP", NULL, "RX INT" #id "_2 MUX"}, \
{"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 INTERP"}, \
{"RX INT" #id "_1 INTERP", NULL, "RX INT" #id "_1 MIX1"}, \
{"RX INT" #id "_1 INTERP", NULL, "INT" #id "_CLK"}, \
{"RX INT" #id "_1 INTERP", NULL, "DSMDEM" #id "_CLK"}, \
{"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 INTERP"}
#define WCD934X_INTERPOLATOR_MIX2(id) \
{"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \
{"RX INT" #id " MIX2", NULL, "RX INT" #id " MIX2 INP"}
#define WCD934X_SLIM_RX_AIF_PATH(id) \
{"SLIM RX"#id" MUX", "AIF1_PB", "AIF1 PB"}, \
{"SLIM RX"#id" MUX", "AIF2_PB", "AIF2 PB"}, \
{"SLIM RX"#id" MUX", "AIF3_PB", "AIF3 PB"}, \
{"SLIM RX"#id" MUX", "AIF4_PB", "AIF4 PB"}, \
{"SLIM RX"#id, NULL, "SLIM RX"#id" MUX"}
#define WCD934X_ADC_MUX(id) \
{"ADC MUX" #id, "DMIC", "DMIC MUX" #id }, \
{"ADC MUX" #id, "AMIC", "AMIC MUX" #id }, \
{"DMIC MUX" #id, "DMIC0", "DMIC0"}, \
{"DMIC MUX" #id, "DMIC1", "DMIC1"}, \
{"DMIC MUX" #id, "DMIC2", "DMIC2"}, \
{"DMIC MUX" #id, "DMIC3", "DMIC3"}, \
{"DMIC MUX" #id, "DMIC4", "DMIC4"}, \
{"DMIC MUX" #id, "DMIC5", "DMIC5"}, \
{"AMIC MUX" #id, "ADC1", "ADC1"}, \
{"AMIC MUX" #id, "ADC2", "ADC2"}, \
{"AMIC MUX" #id, "ADC3", "ADC3"}, \
{"AMIC MUX" #id, "ADC4", "ADC4"}
#define WCD934X_IIR_INP_MUX(id) \
{"IIR" #id, NULL, "IIR" #id " INP0 MUX"}, \
{"IIR" #id " INP0 MUX", "DEC0", "ADC MUX0"}, \
{"IIR" #id " INP0 MUX", "DEC1", "ADC MUX1"}, \
{"IIR" #id " INP0 MUX", "DEC2", "ADC MUX2"}, \
{"IIR" #id " INP0 MUX", "DEC3", "ADC MUX3"}, \
{"IIR" #id " INP0 MUX", "DEC4", "ADC MUX4"}, \
{"IIR" #id " INP0 MUX", "DEC5", "ADC MUX5"}, \
{"IIR" #id " INP0 MUX", "DEC6", "ADC MUX6"}, \
{"IIR" #id " INP0 MUX", "DEC7", "ADC MUX7"}, \
{"IIR" #id " INP0 MUX", "DEC8", "ADC MUX8"}, \
{"IIR" #id " INP0 MUX", "RX0", "SLIM RX0"}, \
{"IIR" #id " INP0 MUX", "RX1", "SLIM RX1"}, \
{"IIR" #id " INP0 MUX", "RX2", "SLIM RX2"}, \
{"IIR" #id " INP0 MUX", "RX3", "SLIM RX3"}, \
{"IIR" #id " INP0 MUX", "RX4", "SLIM RX4"}, \
{"IIR" #id " INP0 MUX", "RX5", "SLIM RX5"}, \
{"IIR" #id " INP0 MUX", "RX6", "SLIM RX6"}, \
{"IIR" #id " INP0 MUX", "RX7", "SLIM RX7"}, \
{"IIR" #id, NULL, "IIR" #id " INP1 MUX"}, \
{"IIR" #id " INP1 MUX", "DEC0", "ADC MUX0"}, \
{"IIR" #id " INP1 MUX", "DEC1", "ADC MUX1"}, \
{"IIR" #id " INP1 MUX", "DEC2", "ADC MUX2"}, \
{"IIR" #id " INP1 MUX", "DEC3", "ADC MUX3"}, \
{"IIR" #id " INP1 MUX", "DEC4", "ADC MUX4"}, \
{"IIR" #id " INP1 MUX", "DEC5", "ADC MUX5"}, \
{"IIR" #id " INP1 MUX", "DEC6", "ADC MUX6"}, \
{"IIR" #id " INP1 MUX", "DEC7", "ADC MUX7"}, \
{"IIR" #id " INP1 MUX", "DEC8", "ADC MUX8"}, \
{"IIR" #id " INP1 MUX", "RX0", "SLIM RX0"}, \
{"IIR" #id " INP1 MUX", "RX1", "SLIM RX1"}, \
{"IIR" #id " INP1 MUX", "RX2", "SLIM RX2"}, \
{"IIR" #id " INP1 MUX", "RX3", "SLIM RX3"}, \
{"IIR" #id " INP1 MUX", "RX4", "SLIM RX4"}, \
{"IIR" #id " INP1 MUX", "RX5", "SLIM RX5"}, \
{"IIR" #id " INP1 MUX", "RX6", "SLIM RX6"}, \
{"IIR" #id " INP1 MUX", "RX7", "SLIM RX7"}, \
{"IIR" #id, NULL, "IIR" #id " INP2 MUX"}, \
{"IIR" #id " INP2 MUX", "DEC0", "ADC MUX0"}, \
{"IIR" #id " INP2 MUX", "DEC1", "ADC MUX1"}, \
{"IIR" #id " INP2 MUX", "DEC2", "ADC MUX2"}, \
{"IIR" #id " INP2 MUX", "DEC3", "ADC MUX3"}, \
{"IIR" #id " INP2 MUX", "DEC4", "ADC MUX4"}, \
{"IIR" #id " INP2 MUX", "DEC5", "ADC MUX5"}, \
{"IIR" #id " INP2 MUX", "DEC6", "ADC MUX6"}, \
{"IIR" #id " INP2 MUX", "DEC7", "ADC MUX7"}, \
{"IIR" #id " INP2 MUX", "DEC8", "ADC MUX8"}, \
{"IIR" #id " INP2 MUX", "RX0", "SLIM RX0"}, \
{"IIR" #id " INP2 MUX", "RX1", "SLIM RX1"}, \
{"IIR" #id " INP2 MUX", "RX2", "SLIM RX2"}, \
{"IIR" #id " INP2 MUX", "RX3", "SLIM RX3"}, \
{"IIR" #id " INP2 MUX", "RX4", "SLIM RX4"}, \
{"IIR" #id " INP2 MUX", "RX5", "SLIM RX5"}, \
{"IIR" #id " INP2 MUX", "RX6", "SLIM RX6"}, \
{"IIR" #id " INP2 MUX", "RX7", "SLIM RX7"}, \
{"IIR" #id, NULL, "IIR" #id " INP3 MUX"}, \
{"IIR" #id " INP3 MUX", "DEC0", "ADC MUX0"}, \
{"IIR" #id " INP3 MUX", "DEC1", "ADC MUX1"}, \
{"IIR" #id " INP3 MUX", "DEC2", "ADC MUX2"}, \
{"IIR" #id " INP3 MUX", "DEC3", "ADC MUX3"}, \
{"IIR" #id " INP3 MUX", "DEC4", "ADC MUX4"}, \
{"IIR" #id " INP3 MUX", "DEC5", "ADC MUX5"}, \
{"IIR" #id " INP3 MUX", "DEC6", "ADC MUX6"}, \
{"IIR" #id " INP3 MUX", "DEC7", "ADC MUX7"}, \
{"IIR" #id " INP3 MUX", "DEC8", "ADC MUX8"}, \
{"IIR" #id " INP3 MUX", "RX0", "SLIM RX0"}, \
{"IIR" #id " INP3 MUX", "RX1", "SLIM RX1"}, \
{"IIR" #id " INP3 MUX", "RX2", "SLIM RX2"}, \
{"IIR" #id " INP3 MUX", "RX3", "SLIM RX3"}, \
{"IIR" #id " INP3 MUX", "RX4", "SLIM RX4"}, \
{"IIR" #id " INP3 MUX", "RX5", "SLIM RX5"}, \
{"IIR" #id " INP3 MUX", "RX6", "SLIM RX6"}, \
{"IIR" #id " INP3 MUX", "RX7", "SLIM RX7"}
#define WCD934X_SLIM_TX_AIF_PATH(id) \
{"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \
{"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \
{"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \
{"SLIM TX" #id, NULL, "CDC_IF TX" #id " MUX"}
#define WCD934X_MAX_MICBIAS MIC_BIAS_4
enum {
SIDO_SOURCE_INTERNAL,
SIDO_SOURCE_RCO_BG,
};
enum {
INTERP_EAR = 0,
INTERP_HPHL,
INTERP_HPHR,
INTERP_LO1,
INTERP_LO2,
INTERP_LO3_NA, /* LO3 not avalible in Tavil */
INTERP_LO4_NA,
INTERP_SPKR1, /*INT7 WSA Speakers via soundwire */
INTERP_SPKR2, /*INT8 WSA Speakers via soundwire */
INTERP_MAX,
};
enum {
WCD934X_RX0 = 0,
WCD934X_RX1,
WCD934X_RX2,
WCD934X_RX3,
WCD934X_RX4,
WCD934X_RX5,
WCD934X_RX6,
WCD934X_RX7,
WCD934X_RX8,
WCD934X_RX9,
WCD934X_RX10,
WCD934X_RX11,
WCD934X_RX12,
WCD934X_RX_MAX,
};
enum {
WCD934X_TX0 = 0,
WCD934X_TX1,
WCD934X_TX2,
WCD934X_TX3,
WCD934X_TX4,
WCD934X_TX5,
WCD934X_TX6,
WCD934X_TX7,
WCD934X_TX8,
WCD934X_TX9,
WCD934X_TX10,
WCD934X_TX11,
WCD934X_TX12,
WCD934X_TX13,
WCD934X_TX14,
WCD934X_TX15,
WCD934X_TX_MAX,
};
struct wcd934x_slim_ch {
u32 ch_num;
u16 port;
u16 shift;
struct list_head list;
};
static const struct wcd934x_slim_ch wcd934x_tx_chs[WCD934X_TX_MAX] = {
WCD934X_SLIM_TX_CH(0),
WCD934X_SLIM_TX_CH(1),
WCD934X_SLIM_TX_CH(2),
WCD934X_SLIM_TX_CH(3),
WCD934X_SLIM_TX_CH(4),
WCD934X_SLIM_TX_CH(5),
WCD934X_SLIM_TX_CH(6),
WCD934X_SLIM_TX_CH(7),
WCD934X_SLIM_TX_CH(8),
WCD934X_SLIM_TX_CH(9),
WCD934X_SLIM_TX_CH(10),
WCD934X_SLIM_TX_CH(11),
WCD934X_SLIM_TX_CH(12),
WCD934X_SLIM_TX_CH(13),
WCD934X_SLIM_TX_CH(14),
WCD934X_SLIM_TX_CH(15),
};
static const struct wcd934x_slim_ch wcd934x_rx_chs[WCD934X_RX_MAX] = {
WCD934X_SLIM_RX_CH(0), /* 16 */
WCD934X_SLIM_RX_CH(1), /* 17 */
WCD934X_SLIM_RX_CH(2),
WCD934X_SLIM_RX_CH(3),
WCD934X_SLIM_RX_CH(4),
WCD934X_SLIM_RX_CH(5),
WCD934X_SLIM_RX_CH(6),
WCD934X_SLIM_RX_CH(7),
WCD934X_SLIM_RX_CH(8),
WCD934X_SLIM_RX_CH(9),
WCD934X_SLIM_RX_CH(10),
WCD934X_SLIM_RX_CH(11),
WCD934X_SLIM_RX_CH(12),
};
/* Codec supports 2 IIR filters */
enum {
IIR0 = 0,
IIR1,
IIR_MAX,
};
/* Each IIR has 5 Filter Stages */
enum {
BAND1 = 0,
BAND2,
BAND3,
BAND4,
BAND5,
BAND_MAX,
};
enum {
COMPANDER_1, /* HPH_L */
COMPANDER_2, /* HPH_R */
COMPANDER_3, /* LO1_DIFF */
COMPANDER_4, /* LO2_DIFF */
COMPANDER_5, /* LO3_SE - not used in Tavil */
COMPANDER_6, /* LO4_SE - not used in Tavil */
COMPANDER_7, /* SWR SPK CH1 */
COMPANDER_8, /* SWR SPK CH2 */
COMPANDER_MAX,
};
enum {
AIF1_PB = 0,
AIF1_CAP,
AIF2_PB,
AIF2_CAP,
AIF3_PB,
AIF3_CAP,
AIF4_PB,
AIF4_VIFEED,
AIF4_MAD_TX,
NUM_CODEC_DAIS,
};
enum {
INTn_1_INP_SEL_ZERO = 0,
INTn_1_INP_SEL_DEC0,
INTn_1_INP_SEL_DEC1,
INTn_1_INP_SEL_IIR0,
INTn_1_INP_SEL_IIR1,
INTn_1_INP_SEL_RX0,
INTn_1_INP_SEL_RX1,
INTn_1_INP_SEL_RX2,
INTn_1_INP_SEL_RX3,
INTn_1_INP_SEL_RX4,
INTn_1_INP_SEL_RX5,
INTn_1_INP_SEL_RX6,
INTn_1_INP_SEL_RX7,
};
enum {
INTn_2_INP_SEL_ZERO = 0,
INTn_2_INP_SEL_RX0,
INTn_2_INP_SEL_RX1,
INTn_2_INP_SEL_RX2,
INTn_2_INP_SEL_RX3,
INTn_2_INP_SEL_RX4,
INTn_2_INP_SEL_RX5,
INTn_2_INP_SEL_RX6,
INTn_2_INP_SEL_RX7,
INTn_2_INP_SEL_PROXIMITY,
};
enum {
INTERP_MAIN_PATH,
INTERP_MIX_PATH,
};
struct interp_sample_rate {
int sample_rate;
int rate_val;
};
static struct interp_sample_rate sr_val_tbl[] = {
{8000, 0x0},
{16000, 0x1},
{32000, 0x3},
{48000, 0x4},
{96000, 0x5},
{192000, 0x6},
{384000, 0x7},
{44100, 0x9},
{88200, 0xA},
{176400, 0xB},
{352800, 0xC},
};
struct wcd934x_mbhc_zdet_param {
u16 ldo_ctl;
u16 noff;
u16 nshift;
u16 btn5;
u16 btn6;
u16 btn7;
};
struct wcd_slim_codec_dai_data {
struct list_head slim_ch_list;
struct slim_stream_config sconfig;
struct slim_stream_runtime *sruntime;
};
static const struct regmap_range_cfg wcd934x_ifc_ranges[] = {
{
.name = "WCD9335-IFC-DEV",
.range_min = 0x0,
.range_max = 0xffff,
.selector_reg = 0x800,
.selector_mask = 0xfff,
.selector_shift = 0,
.window_start = 0x800,
.window_len = 0x400,
},
};
static struct regmap_config wcd934x_ifc_regmap_config = {
.reg_bits = 16,
.val_bits = 8,
.max_register = 0xffff,
.ranges = wcd934x_ifc_ranges,
.num_ranges = ARRAY_SIZE(wcd934x_ifc_ranges),
};
struct wcd934x_codec {
struct device *dev;
struct clk_hw hw;
struct clk *extclk;
struct regmap *regmap;
struct regmap *if_regmap;
struct slim_device *sdev;
struct slim_device *sidev;
struct wcd_clsh_ctrl *clsh_ctrl;
struct snd_soc_component *component;
struct wcd934x_slim_ch rx_chs[WCD934X_RX_MAX];
struct wcd934x_slim_ch tx_chs[WCD934X_TX_MAX];
struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS];
int rate;
u32 version;
u32 hph_mode;
int num_rx_port;
int num_tx_port;
u32 tx_port_value[WCD934X_TX_MAX];
u32 rx_port_value[WCD934X_RX_MAX];
int sido_input_src;
int dmic_0_1_clk_cnt;
int dmic_2_3_clk_cnt;
int dmic_4_5_clk_cnt;
int dmic_sample_rate;
int comp_enabled[COMPANDER_MAX];
int sysclk_users;
struct mutex sysclk_mutex;
/* mbhc module */
struct wcd_mbhc *mbhc;
struct wcd_mbhc_config mbhc_cfg;
struct wcd_mbhc_intr intr_ids;
bool mbhc_started;
struct mutex micb_lock;
u32 micb_ref[WCD934X_MAX_MICBIAS];
u32 pullup_ref[WCD934X_MAX_MICBIAS];
u32 micb1_mv;
u32 micb2_mv;
u32 micb3_mv;
u32 micb4_mv;
};
#define to_wcd934x_codec(_hw) container_of(_hw, struct wcd934x_codec, hw)
struct wcd_iir_filter_ctl {
unsigned int iir_idx;
unsigned int band_idx;
struct soc_bytes_ext bytes_ext;
};
static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0);
/* Cutoff frequency for high pass filter */
static const char * const cf_text[] = {
"CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ"
};
static const char * const rx_cf_text[] = {
"CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ",
"CF_NEG_3DB_0P48HZ"
};
static const char * const rx_hph_mode_mux_text[] = {
"Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB",
"Class-H Hi-Fi Low Power"
};
static const char *const slim_rx_mux_text[] = {
"ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB",
};
static const char * const rx_int0_7_mix_mux_text[] = {
"ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
"RX6", "RX7", "PROXIMITY"
};
static const char * const rx_int_mix_mux_text[] = {
"ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
"RX6", "RX7"
};
static const char * const rx_prim_mix_text[] = {
"ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2",
"RX3", "RX4", "RX5", "RX6", "RX7"
};
static const char * const rx_sidetone_mix_text[] = {
"ZERO", "SRC0", "SRC1", "SRC_SUM"
};
static const char * const iir_inp_mux_text[] = {
"ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4", "DEC5", "DEC6",
"DEC7", "DEC8", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", "RX6", "RX7"
};
static const char * const rx_int_dem_inp_mux_text[] = {
"NORMAL_DSM_OUT", "CLSH_DSM_OUT",
};
static const char * const rx_int0_1_interp_mux_text[] = {
"ZERO", "RX INT0_1 MIX1",
};
static const char * const rx_int1_1_interp_mux_text[] = {
"ZERO", "RX INT1_1 MIX1",
};
static const char * const rx_int2_1_interp_mux_text[] = {
"ZERO", "RX INT2_1 MIX1",
};
static const char * const rx_int3_1_interp_mux_text[] = {
"ZERO", "RX INT3_1 MIX1",
};
static const char * const rx_int4_1_interp_mux_text[] = {
"ZERO", "RX INT4_1 MIX1",
};
static const char * const rx_int7_1_interp_mux_text[] = {
"ZERO", "RX INT7_1 MIX1",
};
static const char * const rx_int8_1_interp_mux_text[] = {
"ZERO", "RX INT8_1 MIX1",
};
static const char * const rx_int0_2_interp_mux_text[] = {
"ZERO", "RX INT0_2 MUX",
};
static const char * const rx_int1_2_interp_mux_text[] = {
"ZERO", "RX INT1_2 MUX",
};
static const char * const rx_int2_2_interp_mux_text[] = {
"ZERO", "RX INT2_2 MUX",
};
static const char * const rx_int3_2_interp_mux_text[] = {
"ZERO", "RX INT3_2 MUX",
};
static const char * const rx_int4_2_interp_mux_text[] = {
"ZERO", "RX INT4_2 MUX",
};
static const char * const rx_int7_2_interp_mux_text[] = {
"ZERO", "RX INT7_2 MUX",
};
static const char * const rx_int8_2_interp_mux_text[] = {
"ZERO", "RX INT8_2 MUX",
};
static const char * const dmic_mux_text[] = {
"ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5"
};
static const char * const amic_mux_text[] = {
"ZERO", "ADC1", "ADC2", "ADC3", "ADC4"
};
static const char * const amic4_5_sel_text[] = {
"AMIC4", "AMIC5"
};
static const char * const adc_mux_text[] = {
"DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2"
};
static const char * const cdc_if_tx0_mux_text[] = {
"ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192"
};
static const char * const cdc_if_tx1_mux_text[] = {
"ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192"
};
static const char * const cdc_if_tx2_mux_text[] = {
"ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192"
};
static const char * const cdc_if_tx3_mux_text[] = {
"ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192"
};
static const char * const cdc_if_tx4_mux_text[] = {
"ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192"
};
static const char * const cdc_if_tx5_mux_text[] = {
"ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192"
};
static const char * const cdc_if_tx6_mux_text[] = {
"ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192"
};
static const char * const cdc_if_tx7_mux_text[] = {
"ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192"
};
static const char * const cdc_if_tx8_mux_text[] = {
"ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192"
};
static const char * const cdc_if_tx9_mux_text[] = {
"ZERO", "DEC7", "DEC7_192"
};
static const char * const cdc_if_tx10_mux_text[] = {
"ZERO", "DEC6", "DEC6_192"
};
static const char * const cdc_if_tx11_mux_text[] = {
"DEC_0_5", "DEC_9_12", "MAD_AUDIO", "MAD_BRDCST"
};
static const char * const cdc_if_tx11_inp1_mux_text[] = {
"ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4",
"DEC5", "RX_MIX_TX5", "DEC9_10", "DEC11_12"
};
static const char * const cdc_if_tx13_mux_text[] = {
"CDC_DEC_5", "MAD_BRDCST"
};
static const char * const cdc_if_tx13_inp1_mux_text[] = {
"ZERO", "DEC5", "DEC5_192"
};
static const struct soc_enum cf_dec0_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text);
static const struct soc_enum cf_dec1_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text);
static const struct soc_enum cf_dec2_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text);
static const struct soc_enum cf_dec3_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text);
static const struct soc_enum cf_dec4_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text);
static const struct soc_enum cf_dec5_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text);
static const struct soc_enum cf_dec6_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text);
static const struct soc_enum cf_dec7_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text);
static const struct soc_enum cf_dec8_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text);
static const struct soc_enum cf_int0_1_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text);
static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD934X_CDC_RX0_RX_PATH_MIX_CFG, 2,
rx_cf_text);
static const struct soc_enum cf_int1_1_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text);
static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD934X_CDC_RX1_RX_PATH_MIX_CFG, 2,
rx_cf_text);
static const struct soc_enum cf_int2_1_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text);
static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD934X_CDC_RX2_RX_PATH_MIX_CFG, 2,
rx_cf_text);
static const struct soc_enum cf_int3_1_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text);
static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD934X_CDC_RX3_RX_PATH_MIX_CFG, 2,
rx_cf_text);
static const struct soc_enum cf_int4_1_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text);
static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD934X_CDC_RX4_RX_PATH_MIX_CFG, 2,
rx_cf_text);
static const struct soc_enum cf_int7_1_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text);
static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD934X_CDC_RX7_RX_PATH_MIX_CFG, 2,
rx_cf_text);
static const struct soc_enum cf_int8_1_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text);
static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD934X_CDC_RX8_RX_PATH_MIX_CFG, 2,
rx_cf_text);
static const struct soc_enum rx_hph_mode_mux_enum =
SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
rx_hph_mode_mux_text);
static const struct soc_enum slim_rx_mux_enum =
SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text);
static const struct soc_enum rx_int0_2_mux_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10,
rx_int0_7_mix_mux_text);
static const struct soc_enum rx_int1_2_mux_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9,
rx_int_mix_mux_text);
static const struct soc_enum rx_int2_2_mux_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9,
rx_int_mix_mux_text);
static const struct soc_enum rx_int3_2_mux_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9,
rx_int_mix_mux_text);
static const struct soc_enum rx_int4_2_mux_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9,
rx_int_mix_mux_text);
static const struct soc_enum rx_int7_2_mux_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10,
rx_int0_7_mix_mux_text);
static const struct soc_enum rx_int8_2_mux_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9,
rx_int_mix_mux_text);
static const struct soc_enum rx_int0_1_mix_inp0_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int0_1_mix_inp1_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int0_1_mix_inp2_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int1_1_mix_inp0_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int1_1_mix_inp1_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int1_1_mix_inp2_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int2_1_mix_inp0_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int2_1_mix_inp1_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int2_1_mix_inp2_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int3_1_mix_inp0_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int3_1_mix_inp1_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int3_1_mix_inp2_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int4_1_mix_inp0_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int4_1_mix_inp1_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int4_1_mix_inp2_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int7_1_mix_inp0_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int7_1_mix_inp1_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int7_1_mix_inp2_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int8_1_mix_inp0_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int8_1_mix_inp1_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int8_1_mix_inp2_chain_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13,
rx_prim_mix_text);
static const struct soc_enum rx_int0_mix2_inp_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0, 4,
rx_sidetone_mix_text);
static const struct soc_enum rx_int1_mix2_inp_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 2, 4,
rx_sidetone_mix_text);
static const struct soc_enum rx_int2_mix2_inp_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 4, 4,
rx_sidetone_mix_text);
static const struct soc_enum rx_int3_mix2_inp_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 6, 4,
rx_sidetone_mix_text);
static const struct soc_enum rx_int4_mix2_inp_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 0, 4,
rx_sidetone_mix_text);
static const struct soc_enum rx_int7_mix2_inp_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 2, 4,
rx_sidetone_mix_text);
static const struct soc_enum iir0_inp0_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0,
0, 18, iir_inp_mux_text);
static const struct soc_enum iir0_inp1_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG1,
0, 18, iir_inp_mux_text);
static const struct soc_enum iir0_inp2_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG2,
0, 18, iir_inp_mux_text);
static const struct soc_enum iir0_inp3_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG3,
0, 18, iir_inp_mux_text);
static const struct soc_enum iir1_inp0_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG0,
0, 18, iir_inp_mux_text);
static const struct soc_enum iir1_inp1_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG1,
0, 18, iir_inp_mux_text);
static const struct soc_enum iir1_inp2_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG2,
0, 18, iir_inp_mux_text);
static const struct soc_enum iir1_inp3_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG3,
0, 18, iir_inp_mux_text);
static const struct soc_enum rx_int0_dem_inp_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_SEC0, 0,
ARRAY_SIZE(rx_int_dem_inp_mux_text),
rx_int_dem_inp_mux_text);
static const struct soc_enum rx_int1_dem_inp_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_SEC0, 0,
ARRAY_SIZE(rx_int_dem_inp_mux_text),
rx_int_dem_inp_mux_text);
static const struct soc_enum rx_int2_dem_inp_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_SEC0, 0,
ARRAY_SIZE(rx_int_dem_inp_mux_text),
rx_int_dem_inp_mux_text);
static const struct soc_enum tx_adc_mux0_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0,
ARRAY_SIZE(adc_mux_text), adc_mux_text);
static const struct soc_enum tx_adc_mux1_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0,
ARRAY_SIZE(adc_mux_text), adc_mux_text);
static const struct soc_enum tx_adc_mux2_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0,
ARRAY_SIZE(adc_mux_text), adc_mux_text);
static const struct soc_enum tx_adc_mux3_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0,
ARRAY_SIZE(adc_mux_text), adc_mux_text);
static const struct soc_enum tx_adc_mux4_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 2,
ARRAY_SIZE(adc_mux_text), adc_mux_text);
static const struct soc_enum tx_adc_mux5_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 2,
ARRAY_SIZE(adc_mux_text), adc_mux_text);
static const struct soc_enum tx_adc_mux6_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 2,
ARRAY_SIZE(adc_mux_text), adc_mux_text);
static const struct soc_enum tx_adc_mux7_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 2,
ARRAY_SIZE(adc_mux_text), adc_mux_text);
static const struct soc_enum tx_adc_mux8_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 4,
ARRAY_SIZE(adc_mux_text), adc_mux_text);
static const struct soc_enum rx_int0_1_interp_mux_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2,
rx_int0_1_interp_mux_text);
static const struct soc_enum rx_int1_1_interp_mux_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2,
rx_int1_1_interp_mux_text);
static const struct soc_enum rx_int2_1_interp_mux_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2,
rx_int2_1_interp_mux_text);
static const struct soc_enum rx_int3_1_interp_mux_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int3_1_interp_mux_text);
static const struct soc_enum rx_int4_1_interp_mux_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int4_1_interp_mux_text);
static const struct soc_enum rx_int7_1_interp_mux_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int7_1_interp_mux_text);
static const struct soc_enum rx_int8_1_interp_mux_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int8_1_interp_mux_text);
static const struct soc_enum rx_int0_2_interp_mux_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int0_2_interp_mux_text);
static const struct soc_enum rx_int1_2_interp_mux_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int1_2_interp_mux_text);
static const struct soc_enum rx_int2_2_interp_mux_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int2_2_interp_mux_text);
static const struct soc_enum rx_int3_2_interp_mux_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int3_2_interp_mux_text);
static const struct soc_enum rx_int4_2_interp_mux_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int4_2_interp_mux_text);
static const struct soc_enum rx_int7_2_interp_mux_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int7_2_interp_mux_text);
static const struct soc_enum rx_int8_2_interp_mux_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int8_2_interp_mux_text);
static const struct soc_enum tx_dmic_mux0_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 7,
dmic_mux_text);
static const struct soc_enum tx_dmic_mux1_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 7,
dmic_mux_text);
static const struct soc_enum tx_dmic_mux2_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 7,
dmic_mux_text);
static const struct soc_enum tx_dmic_mux3_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 7,
dmic_mux_text);
static const struct soc_enum tx_dmic_mux4_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7,
dmic_mux_text);
static const struct soc_enum tx_dmic_mux5_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7,
dmic_mux_text);
static const struct soc_enum tx_dmic_mux6_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7,
dmic_mux_text);
static const struct soc_enum tx_dmic_mux7_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7,
dmic_mux_text);
static const struct soc_enum tx_dmic_mux8_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7,
dmic_mux_text);
static const struct soc_enum tx_amic_mux0_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 5,
amic_mux_text);
static const struct soc_enum tx_amic_mux1_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 5,
amic_mux_text);
static const struct soc_enum tx_amic_mux2_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 5,
amic_mux_text);
static const struct soc_enum tx_amic_mux3_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 5,
amic_mux_text);
static const struct soc_enum tx_amic_mux4_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 5,
amic_mux_text);
static const struct soc_enum tx_amic_mux5_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 5,
amic_mux_text);
static const struct soc_enum tx_amic_mux6_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 5,
amic_mux_text);
static const struct soc_enum tx_amic_mux7_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 5,
amic_mux_text);
static const struct soc_enum tx_amic_mux8_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 5,
amic_mux_text);
static const struct soc_enum tx_amic4_5_enum =
SOC_ENUM_SINGLE(WCD934X_TX_NEW_AMIC_4_5_SEL, 7, 2, amic4_5_sel_text);
static const struct soc_enum cdc_if_tx0_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 0,
ARRAY_SIZE(cdc_if_tx0_mux_text), cdc_if_tx0_mux_text);
static const struct soc_enum cdc_if_tx1_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 2,
ARRAY_SIZE(cdc_if_tx1_mux_text), cdc_if_tx1_mux_text);
static const struct soc_enum cdc_if_tx2_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 4,
ARRAY_SIZE(cdc_if_tx2_mux_text), cdc_if_tx2_mux_text);
static const struct soc_enum cdc_if_tx3_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 6,
ARRAY_SIZE(cdc_if_tx3_mux_text), cdc_if_tx3_mux_text);
static const struct soc_enum cdc_if_tx4_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 0,
ARRAY_SIZE(cdc_if_tx4_mux_text), cdc_if_tx4_mux_text);
static const struct soc_enum cdc_if_tx5_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 2,
ARRAY_SIZE(cdc_if_tx5_mux_text), cdc_if_tx5_mux_text);
static const struct soc_enum cdc_if_tx6_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 4,
ARRAY_SIZE(cdc_if_tx6_mux_text), cdc_if_tx6_mux_text);
static const struct soc_enum cdc_if_tx7_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 6,
ARRAY_SIZE(cdc_if_tx7_mux_text), cdc_if_tx7_mux_text);
static const struct soc_enum cdc_if_tx8_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 0,
ARRAY_SIZE(cdc_if_tx8_mux_text), cdc_if_tx8_mux_text);
static const struct soc_enum cdc_if_tx9_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 2,
ARRAY_SIZE(cdc_if_tx9_mux_text), cdc_if_tx9_mux_text);
static const struct soc_enum cdc_if_tx10_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 4,
ARRAY_SIZE(cdc_if_tx10_mux_text), cdc_if_tx10_mux_text);
static const struct soc_enum cdc_if_tx11_inp1_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 0,
ARRAY_SIZE(cdc_if_tx11_inp1_mux_text),
cdc_if_tx11_inp1_mux_text);
static const struct soc_enum cdc_if_tx11_mux_enum =
SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX11_INP_CFG, 0,
ARRAY_SIZE(cdc_if_tx11_mux_text), cdc_if_tx11_mux_text);
static const struct soc_enum cdc_if_tx13_inp1_mux_enum =
SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 4,
ARRAY_SIZE(cdc_if_tx13_inp1_mux_text),
cdc_if_tx13_inp1_mux_text);
static const struct soc_enum cdc_if_tx13_mux_enum =
SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX13_INP_CFG, 0,
ARRAY_SIZE(cdc_if_tx13_mux_text), cdc_if_tx13_mux_text);
static struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = {
WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD934X_ANA_MBHC_MECH, 0x80),
WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD934X_ANA_MBHC_MECH, 0x40),
WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD934X_ANA_MBHC_MECH, 0x20),
WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0x30),
WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD934X_ANA_MBHC_ELECT, 0x08),
WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0xC0),
WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD934X_ANA_MBHC_MECH, 0x04),
WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD934X_ANA_MBHC_MECH, 0x10),
WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD934X_ANA_MBHC_MECH, 0x08),
WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD934X_ANA_MBHC_MECH, 0x01),
WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD934X_ANA_MBHC_ELECT, 0x06),
WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD934X_ANA_MBHC_ELECT, 0x80),
WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F),
WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD934X_MBHC_NEW_CTL_1, 0x03),
WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD934X_MBHC_NEW_CTL_2, 0x03),
WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x08),
WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD934X_ANA_MBHC_RESULT_3, 0x10),
WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x20),
WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x80),
WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x40),
WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD934X_HPH_OCP_CTL, 0x10),
WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x07),
WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD934X_ANA_MBHC_ELECT, 0x70),
WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0xFF),
WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD934X_ANA_MICB2, 0xC0),
WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD934X_HPH_CNP_WG_TIME, 0xFF),
WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD934X_ANA_HPH, 0x40),
WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD934X_ANA_HPH, 0x80),
WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD934X_ANA_HPH, 0xC0),
WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD934X_ANA_MBHC_RESULT_3, 0x10),
WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD934X_MBHC_CTL_BCS, 0x02),
WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD934X_MBHC_STATUS_SPARE_1, 0x01),
WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD934X_MBHC_NEW_CTL_2, 0x70),
WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD934X_MBHC_NEW_FSM_STATUS, 0x20),
WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD934X_HPH_PA_CTL2, 0x40),
WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD934X_HPH_PA_CTL2, 0x10),
WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD934X_HPH_L_TEST, 0x01),
WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD934X_HPH_R_TEST, 0x01),
WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD934X_INTR_PIN1_STATUS0, 0x04),
WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD934X_INTR_PIN1_STATUS0, 0x08),
WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD934X_MBHC_NEW_CTL_1, 0x08),
WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD934X_MBHC_NEW_FSM_STATUS, 0x40),
WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD934X_MBHC_NEW_FSM_STATUS, 0x80),
WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD934X_MBHC_NEW_ADC_RESULT, 0xFF),
WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD934X_ANA_MICB2, 0x3F),
WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD934X_MBHC_NEW_CTL_1, 0x10),
WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD934X_MBHC_NEW_CTL_1, 0x04),
WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD934X_ANA_MBHC_ZDET, 0x02),
};
static int wcd934x_set_sido_input_src(struct wcd934x_codec *wcd, int sido_src)
{
if (sido_src == wcd->sido_input_src)
return 0;
if (sido_src == SIDO_SOURCE_RCO_BG) {
regmap_update_bits(wcd->regmap, WCD934X_ANA_RCO,
WCD934X_ANA_RCO_BG_EN_MASK,
WCD934X_ANA_RCO_BG_ENABLE);
usleep_range(100, 110);
}
wcd->sido_input_src = sido_src;
return 0;
}
static int wcd934x_enable_ana_bias_and_sysclk(struct wcd934x_codec *wcd)
{
mutex_lock(&wcd->sysclk_mutex);
if (++wcd->sysclk_users != 1) {
mutex_unlock(&wcd->sysclk_mutex);
return 0;
}
mutex_unlock(&wcd->sysclk_mutex);
regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
WCD934X_ANA_BIAS_EN_MASK,
WCD934X_ANA_BIAS_EN);
regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
WCD934X_ANA_PRECHRG_EN_MASK,
WCD934X_ANA_PRECHRG_EN);
/*
* 1ms delay is required after pre-charge is enabled
* as per HW requirement
*/
usleep_range(1000, 1100);
regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
WCD934X_ANA_PRECHRG_EN_MASK, 0);
regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
WCD934X_ANA_PRECHRG_MODE_MASK, 0);
/*
* In data clock contrl register is changed
* to CLK_SYS_MCLK_PRG
*/
regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
WCD934X_EXT_CLK_BUF_EN_MASK,
WCD934X_EXT_CLK_BUF_EN);
regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
WCD934X_EXT_CLK_DIV_RATIO_MASK,
WCD934X_EXT_CLK_DIV_BY_2);
regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
WCD934X_MCLK_SRC_MASK,
WCD934X_MCLK_SRC_EXT_CLK);
regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
WCD934X_MCLK_EN_MASK, WCD934X_MCLK_EN);
regmap_update_bits(wcd->regmap,
WCD934X_CDC_CLK_RST_CTRL_FS_CNT_CONTROL,
WCD934X_CDC_FS_MCLK_CNT_EN_MASK,
WCD934X_CDC_FS_MCLK_CNT_ENABLE);
regmap_update_bits(wcd->regmap,
WCD934X_CDC_CLK_RST_CTRL_MCLK_CONTROL,
WCD934X_MCLK_EN_MASK,
WCD934X_MCLK_EN);
regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_GATE,
WCD934X_CODEC_RPM_CLK_GATE_MASK, 0x0);
/*
* 10us sleep is required after clock is enabled
* as per HW requirement
*/
usleep_range(10, 15);
wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG);
return 0;
}
static int wcd934x_disable_ana_bias_and_syclk(struct wcd934x_codec *wcd)
{
mutex_lock(&wcd->sysclk_mutex);
if (--wcd->sysclk_users != 0) {
mutex_unlock(&wcd->sysclk_mutex);
return 0;
}
mutex_unlock(&wcd->sysclk_mutex);
regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
WCD934X_EXT_CLK_BUF_EN_MASK |
WCD934X_MCLK_EN_MASK, 0x0);
regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
WCD934X_ANA_BIAS_EN_MASK, 0);
regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
WCD934X_ANA_PRECHRG_EN_MASK, 0);
return 0;
}
static int __wcd934x_cdc_mclk_enable(struct wcd934x_codec *wcd, bool enable)
{
int ret = 0;
if (enable) {
ret = clk_prepare_enable(wcd->extclk);
if (ret) {
dev_err(wcd->dev, "%s: ext clk enable failed\n",
__func__);
return ret;
}
ret = wcd934x_enable_ana_bias_and_sysclk(wcd);
} else {
int val;
regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
&val);
/* Don't disable clock if soundwire using it.*/
if (val & WCD934X_CDC_SWR_CLK_EN_MASK)
return 0;
wcd934x_disable_ana_bias_and_syclk(wcd);
clk_disable_unprepare(wcd->extclk);
}
return ret;
}
static int wcd934x_codec_enable_mclk(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kc, int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
return __wcd934x_cdc_mclk_enable(wcd, true);
case SND_SOC_DAPM_POST_PMD:
return __wcd934x_cdc_mclk_enable(wcd, false);
}
return 0;
}
static int wcd934x_get_version(struct wcd934x_codec *wcd)
{
int val1, val2, ver, ret;
struct regmap *regmap;
u16 id_minor;
u32 version_mask = 0;
regmap = wcd->regmap;
ver = 0;
ret = regmap_bulk_read(regmap, WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0,
(u8 *)&id_minor, sizeof(u16));
if (ret)
return ret;
regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT14, &val1);
regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT15, &val2);
version_mask |= (!!((u8)val1 & 0x80)) << DSD_DISABLED_MASK;
version_mask |= (!!((u8)val2 & 0x01)) << SLNQ_DISABLED_MASK;
switch (version_mask) {
case DSD_DISABLED | SLNQ_DISABLED:
if (id_minor == 0)
ver = WCD_VERSION_WCD9340_1_0;
else if (id_minor == 0x01)
ver = WCD_VERSION_WCD9340_1_1;
break;
case SLNQ_DISABLED:
if (id_minor == 0)
ver = WCD_VERSION_WCD9341_1_0;
else if (id_minor == 0x01)
ver = WCD_VERSION_WCD9341_1_1;
break;
}
wcd->version = ver;
dev_info(wcd->dev, "WCD934X Minor:0x%x Version:0x%x\n", id_minor, ver);
return 0;
}
static void wcd934x_enable_efuse_sensing(struct wcd934x_codec *wcd)
{
int rc, val;
__wcd934x_cdc_mclk_enable(wcd, true);
regmap_update_bits(wcd->regmap,
WCD934X_CHIP_TIER_CTRL_EFUSE_CTL,
WCD934X_EFUSE_SENSE_STATE_MASK,
WCD934X_EFUSE_SENSE_STATE_DEF);
regmap_update_bits(wcd->regmap,
WCD934X_CHIP_TIER_CTRL_EFUSE_CTL,
WCD934X_EFUSE_SENSE_EN_MASK,
WCD934X_EFUSE_SENSE_ENABLE);
/*
* 5ms sleep required after enabling efuse control
* before checking the status.
*/
usleep_range(5000, 5500);
wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG);
rc = regmap_read(wcd->regmap,
WCD934X_CHIP_TIER_CTRL_EFUSE_STATUS, &val);
if (rc || (!(val & 0x01)))
WARN(1, "%s: Efuse sense is not complete val=%x, ret=%d\n",
__func__, val, rc);
__wcd934x_cdc_mclk_enable(wcd, false);
}
static int wcd934x_swrm_clock(struct wcd934x_codec *wcd, bool enable)
{
if (enable) {
__wcd934x_cdc_mclk_enable(wcd, true);
regmap_update_bits(wcd->regmap,
WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
WCD934X_CDC_SWR_CLK_EN_MASK,
WCD934X_CDC_SWR_CLK_ENABLE);
} else {
regmap_update_bits(wcd->regmap,
WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
WCD934X_CDC_SWR_CLK_EN_MASK, 0);
__wcd934x_cdc_mclk_enable(wcd, false);
}
return 0;
}
static int wcd934x_set_prim_interpolator_rate(struct snd_soc_dai *dai,
u8 rate_val, u32 rate)
{
struct snd_soc_component *comp = dai->component;
struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
struct wcd934x_slim_ch *ch;
u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel;
int inp, j;
list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
inp = ch->shift + INTn_1_INP_SEL_RX0;
/*
* Loop through all interpolator MUX inputs and find out
* to which interpolator input, the slim rx port
* is connected
*/
for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) {
/* Interpolators 5 and 6 are not aviliable in Tavil */
if (j == INTERP_LO3_NA || j == INTERP_LO4_NA)
continue;
cfg0 = snd_soc_component_read(comp,
WCD934X_CDC_RX_INP_MUX_RX_INT_CFG0(j));
cfg1 = snd_soc_component_read(comp,
WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j));
inp0_sel = cfg0 &
WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
inp1_sel = (cfg0 >> 4) &
WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
inp2_sel = (cfg1 >> 4) &
WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
if ((inp0_sel == inp) || (inp1_sel == inp) ||
(inp2_sel == inp)) {
/* rate is in Hz */
/*
* Ear and speaker primary path does not support
* native sample rates
*/
if ((j == INTERP_EAR || j == INTERP_SPKR1 ||
j == INTERP_SPKR2) && rate == 44100)
dev_err(wcd->dev,
"Cannot set 44.1KHz on INT%d\n",
j);
else
snd_soc_component_update_bits(comp,
WCD934X_CDC_RX_PATH_CTL(j),
WCD934X_CDC_MIX_PCM_RATE_MASK,
rate_val);
}
}
}
return 0;
}
static int wcd934x_set_mix_interpolator_rate(struct snd_soc_dai *dai,
int rate_val, u32 rate)
{
struct snd_soc_component *component = dai->component;
struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
struct wcd934x_slim_ch *ch;
int val, j;
list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) {
/* Interpolators 5 and 6 are not aviliable in Tavil */
if (j == INTERP_LO3_NA || j == INTERP_LO4_NA)
continue;
val = snd_soc_component_read(component,
WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j)) &
WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
if (val == (ch->shift + INTn_2_INP_SEL_RX0)) {
/*
* Ear mix path supports only 48, 96, 192,
* 384KHz only
*/
if ((j == INTERP_EAR) &&
(rate_val < 0x4 ||
rate_val > 0x7)) {
dev_err(component->dev,
"Invalid rate for AIF_PB DAI(%d)\n",
dai->id);
return -EINVAL;
}
snd_soc_component_update_bits(component,
WCD934X_CDC_RX_PATH_MIX_CTL(j),
WCD934X_CDC_MIX_PCM_RATE_MASK,
rate_val);
}
}
}
return 0;
}
static int wcd934x_set_interpolator_rate(struct snd_soc_dai *dai,
u32 sample_rate)
{
int rate_val = 0;
int i, ret;
for (i = 0; i < ARRAY_SIZE(sr_val_tbl); i++) {
if (sample_rate == sr_val_tbl[i].sample_rate) {
rate_val = sr_val_tbl[i].rate_val;
break;
}
}
if ((i == ARRAY_SIZE(sr_val_tbl)) || (rate_val < 0)) {
dev_err(dai->dev, "Unsupported sample rate: %d\n", sample_rate);
return -EINVAL;
}
ret = wcd934x_set_prim_interpolator_rate(dai, (u8)rate_val,
sample_rate);
if (ret)
return ret;
ret = wcd934x_set_mix_interpolator_rate(dai, (u8)rate_val,
sample_rate);
return ret;
}
static int wcd934x_set_decimator_rate(struct snd_soc_dai *dai,
u8 rate_val, u32 rate)
{
struct snd_soc_component *comp = dai->component;
struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
u8 shift = 0, shift_val = 0, tx_mux_sel;
struct wcd934x_slim_ch *ch;
int tx_port, tx_port_reg;
int decimator = -1;
list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
tx_port = ch->port;
/* Find the SB TX MUX input - which decimator is connected */
switch (tx_port) {
case 0 ... 3:
tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0;
shift = (tx_port << 1);
shift_val = 0x03;
break;
case 4 ... 7:
tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1;
shift = ((tx_port - 4) << 1);
shift_val = 0x03;
break;
case 8 ... 10:
tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2;
shift = ((tx_port - 8) << 1);
shift_val = 0x03;
break;
case 11:
tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3;
shift = 0;
shift_val = 0x0F;
break;
case 13:
tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3;
shift = 4;
shift_val = 0x03;
break;
default:
dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n",
tx_port, dai->id);
return -EINVAL;
}
tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) &
(shift_val << shift);
tx_mux_sel = tx_mux_sel >> shift;
switch (tx_port) {
case 0 ... 8:
if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3))
decimator = tx_port;
break;
case 9 ... 10:
if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
decimator = ((tx_port == 9) ? 7 : 6);
break;
case 11:
if ((tx_mux_sel >= 1) && (tx_mux_sel < 7))
decimator = tx_mux_sel - 1;
break;
case 13:
if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
decimator = 5;
break;
default:
dev_err(wcd->dev, "ERROR: Invalid tx_port: %d\n",
tx_port);
return -EINVAL;
}
snd_soc_component_update_bits(comp,
WCD934X_CDC_TX_PATH_CTL(decimator),
WCD934X_CDC_TX_PATH_CTL_PCM_RATE_MASK,
rate_val);
}
return 0;
}
static int wcd934x_slim_set_hw_params(struct wcd934x_codec *wcd,
struct wcd_slim_codec_dai_data *dai_data,
int direction)
{
struct list_head *slim_ch_list = &dai_data->slim_ch_list;
struct slim_stream_config *cfg = &dai_data->sconfig;
struct wcd934x_slim_ch *ch;
u16 payload = 0;
int ret, i;
cfg->ch_count = 0;
cfg->direction = direction;
cfg->port_mask = 0;
/* Configure slave interface device */
list_for_each_entry(ch, slim_ch_list, list) {
cfg->ch_count++;
payload |= 1 << ch->shift;
cfg->port_mask |= BIT(ch->port);
}
cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL);
if (!cfg->chs)
return -ENOMEM;
i = 0;
list_for_each_entry(ch, slim_ch_list, list) {
cfg->chs[i++] = ch->ch_num;
if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
/* write to interface device */
ret = regmap_write(wcd->if_regmap,
WCD934X_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port),
payload);
if (ret < 0)
goto err;
/* configure the slave port for water mark and enable*/
ret = regmap_write(wcd->if_regmap,
WCD934X_SLIM_PGD_RX_PORT_CFG(ch->port),
WCD934X_SLIM_WATER_MARK_VAL);
if (ret < 0)
goto err;
} else {
ret = regmap_write(wcd->if_regmap,
WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port),
payload & 0x00FF);
if (ret < 0)
goto err;
/* ports 8,9 */
ret = regmap_write(wcd->if_regmap,
WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port),
(payload & 0xFF00) >> 8);
if (ret < 0)
goto err;
/* configure the slave port for water mark and enable*/
ret = regmap_write(wcd->if_regmap,
WCD934X_SLIM_PGD_TX_PORT_CFG(ch->port),
WCD934X_SLIM_WATER_MARK_VAL);
if (ret < 0)
goto err;
}
}
dai_data->sruntime = slim_stream_allocate(wcd->sdev, "WCD934x-SLIM");
return 0;
err:
dev_err(wcd->dev, "Error Setting slim hw params\n");
kfree(cfg->chs);
cfg->chs = NULL;
return ret;
}
static int wcd934x_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct wcd934x_codec *wcd;
int ret, tx_fs_rate = 0;
wcd = snd_soc_component_get_drvdata(dai->component);
switch (substream->stream) {
case SNDRV_PCM_STREAM_PLAYBACK:
ret = wcd934x_set_interpolator_rate(dai, params_rate(params));
if (ret) {
dev_err(wcd->dev, "cannot set sample rate: %u\n",
params_rate(params));
return ret;
}
switch (params_width(params)) {
case 16 ... 24:
wcd->dai[dai->id].sconfig.bps = params_width(params);
break;
default:
dev_err(wcd->dev, "Invalid format 0x%x\n",
params_width(params));
return -EINVAL;
}
break;
case SNDRV_PCM_STREAM_CAPTURE:
switch (params_rate(params)) {
case 8000:
tx_fs_rate = 0;
break;
case 16000:
tx_fs_rate = 1;
break;
case 32000:
tx_fs_rate = 3;
break;
case 48000:
tx_fs_rate = 4;
break;
case 96000:
tx_fs_rate = 5;
break;
case 192000:
tx_fs_rate = 6;
break;
case 384000:
tx_fs_rate = 7;
break;
default:
dev_err(wcd->dev, "Invalid TX sample rate: %d\n",
params_rate(params));
return -EINVAL;
}
ret = wcd934x_set_decimator_rate(dai, tx_fs_rate,
params_rate(params));
if (ret < 0) {
dev_err(wcd->dev, "Cannot set TX Decimator rate\n");
return ret;
}
switch (params_width(params)) {
case 16 ... 32:
wcd->dai[dai->id].sconfig.bps = params_width(params);
break;
default:
dev_err(wcd->dev, "Invalid format 0x%x\n",
params_width(params));
return -EINVAL;
}
break;
default:
dev_err(wcd->dev, "Invalid stream type %d\n",
substream->stream);
return -EINVAL;
}
wcd->dai[dai->id].sconfig.rate = params_rate(params);
return wcd934x_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream);
}
static int wcd934x_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct wcd_slim_codec_dai_data *dai_data;
struct wcd934x_codec *wcd;
wcd = snd_soc_component_get_drvdata(dai->component);
dai_data = &wcd->dai[dai->id];
kfree(dai_data->sconfig.chs);
return 0;
}
static int wcd934x_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct wcd_slim_codec_dai_data *dai_data;
struct wcd934x_codec *wcd;
struct slim_stream_config *cfg;
wcd = snd_soc_component_get_drvdata(dai->component);
dai_data = &wcd->dai[dai->id];
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
cfg = &dai_data->sconfig;
slim_stream_prepare(dai_data->sruntime, cfg);
slim_stream_enable(dai_data->sruntime);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
slim_stream_disable(dai_data->sruntime);
slim_stream_unprepare(dai_data->sruntime);
break;
default:
break;
}
return 0;
}
static int wcd934x_set_channel_map(struct snd_soc_dai *dai,
unsigned int tx_num, unsigned int *tx_slot,
unsigned int rx_num, unsigned int *rx_slot)
{
struct wcd934x_codec *wcd;
int i;
wcd = snd_soc_component_get_drvdata(dai->component);
if (tx_num > WCD934X_TX_MAX || rx_num > WCD934X_RX_MAX) {
dev_err(wcd->dev, "Invalid tx %d or rx %d channel count\n",
tx_num, rx_num);
return -EINVAL;
}
if (!tx_slot || !rx_slot) {
dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n",
tx_slot, rx_slot);
return -EINVAL;
}
wcd->num_rx_port = rx_num;
for (i = 0; i < rx_num; i++) {
wcd->rx_chs[i].ch_num = rx_slot[i];
INIT_LIST_HEAD(&wcd->rx_chs[i].list);
}
wcd->num_tx_port = tx_num;
for (i = 0; i < tx_num; i++) {
wcd->tx_chs[i].ch_num = tx_slot[i];
INIT_LIST_HEAD(&wcd->tx_chs[i].list);
}
return 0;
}
static int wcd934x_get_channel_map(struct snd_soc_dai *dai,
unsigned int *tx_num, unsigned int *tx_slot,
unsigned int *rx_num, unsigned int *rx_slot)
{
struct wcd934x_slim_ch *ch;
struct wcd934x_codec *wcd;
int i = 0;
wcd = snd_soc_component_get_drvdata(dai->component);
switch (dai->id) {
case AIF1_PB:
case AIF2_PB:
case AIF3_PB:
case AIF4_PB:
if (!rx_slot || !rx_num) {
dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n",
rx_slot, rx_num);
return -EINVAL;
}
list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
rx_slot[i++] = ch->ch_num;
*rx_num = i;
break;
case AIF1_CAP:
case AIF2_CAP:
case AIF3_CAP:
if (!tx_slot || !tx_num) {
dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n",
tx_slot, tx_num);
return -EINVAL;
}
list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
tx_slot[i++] = ch->ch_num;
*tx_num = i;
break;
default:
dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id);
break;
}
return 0;
}
static const struct snd_soc_dai_ops wcd934x_dai_ops = {
.hw_params = wcd934x_hw_params,
.hw_free = wcd934x_hw_free,
.trigger = wcd934x_trigger,
.set_channel_map = wcd934x_set_channel_map,
.get_channel_map = wcd934x_get_channel_map,
};
static struct snd_soc_dai_driver wcd934x_slim_dais[] = {
[0] = {
.name = "wcd934x_rx1",
.id = AIF1_PB,
.playback = {
.stream_name = "AIF1 Playback",
.rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
.formats = WCD934X_FORMATS_S16_S24_LE,
.rate_max = 192000,
.rate_min = 8000,
.channels_min = 1,
.channels_max = 2,
},
.ops = &wcd934x_dai_ops,
},
[1] = {
.name = "wcd934x_tx1",
.id = AIF1_CAP,
.capture = {
.stream_name = "AIF1 Capture",
.rates = WCD934X_RATES_MASK,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.rate_min = 8000,
.rate_max = 192000,
.channels_min = 1,
.channels_max = 4,
},
.ops = &wcd934x_dai_ops,
},
[2] = {
.name = "wcd934x_rx2",
.id = AIF2_PB,
.playback = {
.stream_name = "AIF2 Playback",
.rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
.formats = WCD934X_FORMATS_S16_S24_LE,
.rate_min = 8000,
.rate_max = 192000,
.channels_min = 1,
.channels_max = 2,
},
.ops = &wcd934x_dai_ops,
},
[3] = {
.name = "wcd934x_tx2",
.id = AIF2_CAP,
.capture = {
.stream_name = "AIF2 Capture",
.rates = WCD934X_RATES_MASK,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.rate_min = 8000,
.rate_max = 192000,
.channels_min = 1,
.channels_max = 4,
},
.ops = &wcd934x_dai_ops,
},
[4] = {
.name = "wcd934x_rx3",
.id = AIF3_PB,
.playback = {
.stream_name = "AIF3 Playback",
.rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
.formats = WCD934X_FORMATS_S16_S24_LE,
.rate_min = 8000,
.rate_max = 192000,
.channels_min = 1,
.channels_max = 2,
},
.ops = &wcd934x_dai_ops,
},
[5] = {
.name = "wcd934x_tx3",
.id = AIF3_CAP,
.capture = {
.stream_name = "AIF3 Capture",
.rates = WCD934X_RATES_MASK,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.rate_min = 8000,
.rate_max = 192000,
.channels_min = 1,
.channels_max = 4,
},
.ops = &wcd934x_dai_ops,
},
[6] = {
.name = "wcd934x_rx4",
.id = AIF4_PB,
.playback = {
.stream_name = "AIF4 Playback",
.rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
.formats = WCD934X_FORMATS_S16_S24_LE,
.rate_min = 8000,
.rate_max = 192000,
.channels_min = 1,
.channels_max = 2,
},
.ops = &wcd934x_dai_ops,
},
};
static int swclk_gate_enable(struct clk_hw *hw)
{
return wcd934x_swrm_clock(to_wcd934x_codec(hw), true);
}
static void swclk_gate_disable(struct clk_hw *hw)
{
wcd934x_swrm_clock(to_wcd934x_codec(hw), false);
}
static int swclk_gate_is_enabled(struct clk_hw *hw)
{
struct wcd934x_codec *wcd = to_wcd934x_codec(hw);
int ret, val;
regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, &val);
ret = val & WCD934X_CDC_SWR_CLK_EN_MASK;
return ret;
}
static unsigned long swclk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
return parent_rate / 2;
}
static const struct clk_ops swclk_gate_ops = {
.prepare = swclk_gate_enable,
.unprepare = swclk_gate_disable,
.is_enabled = swclk_gate_is_enabled,
.recalc_rate = swclk_recalc_rate,
};
static struct clk *wcd934x_register_mclk_output(struct wcd934x_codec *wcd)
{
struct clk *parent = wcd->extclk;
struct device *dev = wcd->dev;
struct device_node *np = dev->parent->of_node;
const char *parent_clk_name = NULL;
const char *clk_name = "mclk";
struct clk_hw *hw;
struct clk_init_data init;
int ret;
if (of_property_read_u32(np, "clock-frequency", &wcd->rate))
return NULL;
parent_clk_name = __clk_get_name(parent);
of_property_read_string(np, "clock-output-names", &clk_name);
init.name = clk_name;
init.ops = &swclk_gate_ops;
init.flags = 0;
init.parent_names = &parent_clk_name;
init.num_parents = 1;
wcd->hw.init = &init;
hw = &wcd->hw;
ret = devm_clk_hw_register(wcd->dev->parent, hw);
if (ret)
return ERR_PTR(ret);
ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
if (ret)
return ERR_PTR(ret);
return NULL;
}
static int wcd934x_get_micbias_val(struct device *dev, const char *micbias,
u32 *micb_mv)
{
int mv;
if (of_property_read_u32(dev->parent->of_node, micbias, &mv)) {
dev_err(dev, "%s value not found, using default\n", micbias);
mv = WCD934X_DEF_MICBIAS_MV;
} else {
/* convert it to milli volts */
mv = mv/1000;
}
if (mv < 1000 || mv > 2850) {
dev_err(dev, "%s value not in valid range, using default\n",
micbias);
mv = WCD934X_DEF_MICBIAS_MV;
}
*micb_mv = mv;
return (mv - 1000) / 50;
}
static int wcd934x_init_dmic(struct snd_soc_component *comp)
{
int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4;
struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
u32 def_dmic_rate, dmic_clk_drv;
vout_ctl_1 = wcd934x_get_micbias_val(comp->dev,
"qcom,micbias1-microvolt",
&wcd->micb1_mv);
vout_ctl_2 = wcd934x_get_micbias_val(comp->dev,
"qcom,micbias2-microvolt",
&wcd->micb2_mv);
vout_ctl_3 = wcd934x_get_micbias_val(comp->dev,
"qcom,micbias3-microvolt",
&wcd->micb3_mv);
vout_ctl_4 = wcd934x_get_micbias_val(comp->dev,
"qcom,micbias4-microvolt",
&wcd->micb4_mv);
snd_soc_component_update_bits(comp, WCD934X_ANA_MICB1,
WCD934X_MICB_VAL_MASK, vout_ctl_1);
snd_soc_component_update_bits(comp, WCD934X_ANA_MICB2,
WCD934X_MICB_VAL_MASK, vout_ctl_2);
snd_soc_component_update_bits(comp, WCD934X_ANA_MICB3,
WCD934X_MICB_VAL_MASK, vout_ctl_3);
snd_soc_component_update_bits(comp, WCD934X_ANA_MICB4,
WCD934X_MICB_VAL_MASK, vout_ctl_4);
if (wcd->rate == WCD934X_MCLK_CLK_9P6MHZ)
def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ;
else
def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ;
wcd->dmic_sample_rate = def_dmic_rate;
dmic_clk_drv = 0;
snd_soc_component_update_bits(comp, WCD934X_TEST_DEBUG_PAD_DRVCTL_0,
0x0C, dmic_clk_drv << 2);
return 0;
}
static void wcd934x_hw_init(struct wcd934x_codec *wcd)
{
struct regmap *rm = wcd->regmap;
/* set SPKR rate to FS_2P4_3P072 */
regmap_update_bits(rm, WCD934X_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08);
regmap_update_bits(rm, WCD934X_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08);
/* Take DMICs out of reset */
regmap_update_bits(rm, WCD934X_CPE_SS_DMIC_CFG, 0x80, 0x00);
}
static int wcd934x_comp_init(struct snd_soc_component *component)
{
struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
wcd934x_hw_init(wcd);
wcd934x_enable_efuse_sensing(wcd);
wcd934x_get_version(wcd);
return 0;
}
static irqreturn_t wcd934x_slim_irq_handler(int irq, void *data)
{
struct wcd934x_codec *wcd = data;
unsigned long status = 0;
int i, j, port_id;
unsigned int val, int_val = 0;
irqreturn_t ret = IRQ_NONE;
bool tx;
unsigned short reg = 0;
for (i = WCD934X_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0;
i <= WCD934X_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) {
regmap_read(wcd->if_regmap, i, &val);
status |= ((u32)val << (8 * j));
}
for_each_set_bit(j, &status, 32) {
tx = false;
port_id = j;
if (j >= 16) {
tx = true;
port_id = j - 16;
}
regmap_read(wcd->if_regmap,
WCD934X_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val);
if (val) {
if (!tx)
reg = WCD934X_SLIM_PGD_PORT_INT_EN0 +
(port_id / 8);
else
reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 +
(port_id / 8);
regmap_read(wcd->if_regmap, reg, &int_val);
}
if (val & WCD934X_SLIM_IRQ_OVERFLOW)
dev_err_ratelimited(wcd->dev,
"overflow error on %s port %d, value %x\n",
(tx ? "TX" : "RX"), port_id, val);
if (val & WCD934X_SLIM_IRQ_UNDERFLOW)
dev_err_ratelimited(wcd->dev,
"underflow error on %s port %d, value %x\n",
(tx ? "TX" : "RX"), port_id, val);
if ((val & WCD934X_SLIM_IRQ_OVERFLOW) ||
(val & WCD934X_SLIM_IRQ_UNDERFLOW)) {
if (!tx)
reg = WCD934X_SLIM_PGD_PORT_INT_EN0 +
(port_id / 8);
else
reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 +
(port_id / 8);
regmap_read(
wcd->if_regmap, reg, &int_val);
if (int_val & (1 << (port_id % 8))) {
int_val = int_val ^ (1 << (port_id % 8));
regmap_write(wcd->if_regmap,
reg, int_val);
}
}
if (val & WCD934X_SLIM_IRQ_PORT_CLOSED)
dev_err_ratelimited(wcd->dev,
"Port Closed %s port %d, value %x\n",
(tx ? "TX" : "RX"), port_id, val);
regmap_write(wcd->if_regmap,
WCD934X_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8),
BIT(j % 8));
ret = IRQ_HANDLED;
}
return ret;
}
static void wcd934x_mbhc_clk_setup(struct snd_soc_component *component,
bool enable)
{
snd_soc_component_write_field(component, WCD934X_MBHC_NEW_CTL_1,
WCD934X_MBHC_CTL_RCO_EN_MASK, enable);
}
static void wcd934x_mbhc_mbhc_bias_control(struct snd_soc_component *component,
bool enable)
{
snd_soc_component_write_field(component, WCD934X_ANA_MBHC_ELECT,
WCD934X_ANA_MBHC_BIAS_EN, enable);
}
static void wcd934x_mbhc_program_btn_thr(struct snd_soc_component *component,
int *btn_low, int *btn_high,
int num_btn, bool is_micbias)
{
int i, vth;
if (num_btn > WCD_MBHC_DEF_BUTTONS) {
dev_err(component->dev, "%s: invalid number of buttons: %d\n",
__func__, num_btn);
return;
}
for (i = 0; i < num_btn; i++) {
vth = ((btn_high[i] * 2) / 25) & 0x3F;
snd_soc_component_write_field(component, WCD934X_ANA_MBHC_BTN0 + i,
WCD934X_MBHC_BTN_VTH_MASK, vth);
}
}
static bool wcd934x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num)
{
u8 val;
if (micb_num == MIC_BIAS_2) {
val = snd_soc_component_read_field(component, WCD934X_ANA_MICB2,
WCD934X_ANA_MICB2_ENABLE_MASK);
if (val == WCD934X_MICB_ENABLE)
return true;
}
return false;
}
static void wcd934x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component,
enum mbhc_hs_pullup_iref pull_up_cur)
{
/* Default pull up current to 2uA */
if (pull_up_cur < I_OFF || pull_up_cur > I_3P0_UA ||
pull_up_cur == I_DEFAULT)
pull_up_cur = I_2P0_UA;
snd_soc_component_write_field(component, WCD934X_MBHC_NEW_PLUG_DETECT_CTL,
WCD934X_HSDET_PULLUP_C_MASK, pull_up_cur);
}
static int wcd934x_micbias_control(struct snd_soc_component *component,
int micb_num, int req, bool is_dapm)
{
struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component);
int micb_index = micb_num - 1;
u16 micb_reg;
switch (micb_num) {
case MIC_BIAS_1:
micb_reg = WCD934X_ANA_MICB1;
break;
case MIC_BIAS_2:
micb_reg = WCD934X_ANA_MICB2;
break;
case MIC_BIAS_3:
micb_reg = WCD934X_ANA_MICB3;
break;
case MIC_BIAS_4:
micb_reg = WCD934X_ANA_MICB4;
break;
default:
dev_err(component->dev, "%s: Invalid micbias number: %d\n",
__func__, micb_num);
return -EINVAL;
}
mutex_lock(&wcd934x->micb_lock);
switch (req) {
case MICB_PULLUP_ENABLE:
wcd934x->pullup_ref[micb_index]++;
if ((wcd934x->pullup_ref[micb_index] == 1) &&
(wcd934x->micb_ref[micb_index] == 0))
snd_soc_component_write_field(component, micb_reg,
WCD934X_ANA_MICB_EN_MASK,
WCD934X_MICB_PULL_UP);
break;
case MICB_PULLUP_DISABLE:
if (wcd934x->pullup_ref[micb_index] > 0)
wcd934x->pullup_ref[micb_index]--;
if ((wcd934x->pullup_ref[micb_index] == 0) &&
(wcd934x->micb_ref[micb_index] == 0))
snd_soc_component_write_field(component, micb_reg,
WCD934X_ANA_MICB_EN_MASK, 0);
break;
case MICB_ENABLE:
wcd934x->micb_ref[micb_index]++;
if (wcd934x->micb_ref[micb_index] == 1) {
snd_soc_component_write_field(component, micb_reg,
WCD934X_ANA_MICB_EN_MASK,
WCD934X_MICB_ENABLE);
if (micb_num == MIC_BIAS_2)
wcd_mbhc_event_notify(wcd934x->mbhc,
WCD_EVENT_POST_MICBIAS_2_ON);
}
if (micb_num == MIC_BIAS_2 && is_dapm)
wcd_mbhc_event_notify(wcd934x->mbhc,
WCD_EVENT_POST_DAPM_MICBIAS_2_ON);
break;
case MICB_DISABLE:
if (wcd934x->micb_ref[micb_index] > 0)
wcd934x->micb_ref[micb_index]--;
if ((wcd934x->micb_ref[micb_index] == 0) &&
(wcd934x->pullup_ref[micb_index] > 0))
snd_soc_component_write_field(component, micb_reg,
WCD934X_ANA_MICB_EN_MASK,
WCD934X_MICB_PULL_UP);
else if ((wcd934x->micb_ref[micb_index] == 0) &&
(wcd934x->pullup_ref[micb_index] == 0)) {
if (micb_num == MIC_BIAS_2)
wcd_mbhc_event_notify(wcd934x->mbhc,
WCD_EVENT_PRE_MICBIAS_2_OFF);
snd_soc_component_write_field(component, micb_reg,
WCD934X_ANA_MICB_EN_MASK, 0);
if (micb_num == MIC_BIAS_2)
wcd_mbhc_event_notify(wcd934x->mbhc,
WCD_EVENT_POST_MICBIAS_2_OFF);
}
if (is_dapm && micb_num == MIC_BIAS_2)
wcd_mbhc_event_notify(wcd934x->mbhc,
WCD_EVENT_POST_DAPM_MICBIAS_2_OFF);
break;
}
mutex_unlock(&wcd934x->micb_lock);
return 0;
}
static int wcd934x_mbhc_request_micbias(struct snd_soc_component *component,
int micb_num, int req)
{
struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
int ret;
if (req == MICB_ENABLE)
__wcd934x_cdc_mclk_enable(wcd, true);
ret = wcd934x_micbias_control(component, micb_num, req, false);
if (req == MICB_DISABLE)
__wcd934x_cdc_mclk_enable(wcd, false);
return ret;
}
static void wcd934x_mbhc_micb_ramp_control(struct snd_soc_component *component,
bool enable)
{
if (enable) {
snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP,
WCD934X_RAMP_SHIFT_CTRL_MASK, 0x3);
snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP,
WCD934X_RAMP_EN_MASK, 1);
} else {
snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP,
WCD934X_RAMP_EN_MASK, 0);
snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP,
WCD934X_RAMP_SHIFT_CTRL_MASK, 0);
}
}
static int wcd934x_get_micb_vout_ctl_val(u32 micb_mv)
{
/* min micbias voltage is 1V and maximum is 2.85V */
if (micb_mv < 1000 || micb_mv > 2850)
return -EINVAL;
return (micb_mv - 1000) / 50;
}
static int wcd934x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
int req_volt, int micb_num)
{
struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component);
int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en, ret = 0;
switch (micb_num) {
case MIC_BIAS_1:
micb_reg = WCD934X_ANA_MICB1;
break;
case MIC_BIAS_2:
micb_reg = WCD934X_ANA_MICB2;
break;
case MIC_BIAS_3:
micb_reg = WCD934X_ANA_MICB3;
break;
case MIC_BIAS_4:
micb_reg = WCD934X_ANA_MICB4;
break;
default:
return -EINVAL;
}
mutex_lock(&wcd934x->micb_lock);
/*
* If requested micbias voltage is same as current micbias
* voltage, then just return. Otherwise, adjust voltage as
* per requested value. If micbias is already enabled, then
* to avoid slow micbias ramp-up or down enable pull-up
* momentarily, change the micbias value and then re-enable
* micbias.
*/
micb_en = snd_soc_component_read_field(component, micb_reg,
WCD934X_ANA_MICB_EN_MASK);
cur_vout_ctl = snd_soc_component_read_field(component, micb_reg,
WCD934X_MICB_VAL_MASK);
req_vout_ctl = wcd934x_get_micb_vout_ctl_val(req_volt);
if (req_vout_ctl < 0) {
ret = -EINVAL;
goto exit;
}
if (cur_vout_ctl == req_vout_ctl) {
ret = 0;
goto exit;
}
if (micb_en == WCD934X_MICB_ENABLE)
snd_soc_component_write_field(component, micb_reg,
WCD934X_ANA_MICB_EN_MASK,
WCD934X_MICB_PULL_UP);
snd_soc_component_write_field(component, micb_reg,
WCD934X_MICB_VAL_MASK,
req_vout_ctl);
if (micb_en == WCD934X_MICB_ENABLE) {
snd_soc_component_write_field(component, micb_reg,
WCD934X_ANA_MICB_EN_MASK,
WCD934X_MICB_ENABLE);
/*
* Add 2ms delay as per HW requirement after enabling
* micbias
*/
usleep_range(2000, 2100);
}
exit:
mutex_unlock(&wcd934x->micb_lock);
return ret;
}
static int wcd934x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component,
int micb_num, bool req_en)
{
struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component);
int rc, micb_mv;
if (micb_num != MIC_BIAS_2)
return -EINVAL;
/*
* If device tree micbias level is already above the minimum
* voltage needed to detect threshold microphone, then do
* not change the micbias, just return.
*/
if (wcd934x->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV)
return 0;
micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd934x->micb2_mv;
rc = wcd934x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2);
return rc;
}
static void wcd934x_mbhc_get_result_params(struct wcd934x_codec *wcd934x,
s16 *d1_a, u16 noff,
int32_t *zdet)
{
int i;
int val, val1;
s16 c1;
s32 x1, d1;
int32_t denom;
int minCode_param[] = {
3277, 1639, 820, 410, 205, 103, 52, 26
};
regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x20, 0x20);
for (i = 0; i < WCD934X_ZDET_NUM_MEASUREMENTS; i++) {
regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_2, &val);
if (val & 0x80)
break;
}
val = val << 0x8;
regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_1, &val1);
val |= val1;
regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x20, 0x00);
x1 = WCD934X_MBHC_GET_X1(val);
c1 = WCD934X_MBHC_GET_C1(val);
/* If ramp is not complete, give additional 5ms */
if ((c1 < 2) && x1)
usleep_range(5000, 5050);
if (!c1 || !x1) {
dev_err(wcd934x->dev, "%s: Impedance detect ramp error, c1=%d, x1=0x%x\n",
__func__, c1, x1);
goto ramp_down;
}
d1 = d1_a[c1];
denom = (x1 * d1) - (1 << (14 - noff));
if (denom > 0)
*zdet = (WCD934X_MBHC_ZDET_CONST * 1000) / denom;
else if (x1 < minCode_param[noff])
*zdet = WCD934X_ZDET_FLOATING_IMPEDANCE;
dev_dbg(wcd934x->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%di (milliohm)\n",
__func__, d1, c1, x1, *zdet);
ramp_down:
i = 0;
while (x1) {
regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_1, &val);
regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_2, &val1);
val = val << 0x08;
val |= val1;
x1 = WCD934X_MBHC_GET_X1(val);
i++;
if (i == WCD934X_ZDET_NUM_MEASUREMENTS)
break;
}
}
static void wcd934x_mbhc_zdet_ramp(struct snd_soc_component *component,
struct wcd934x_mbhc_zdet_param *zdet_param,
int32_t *zl, int32_t *zr, s16 *d1_a)
{
struct wcd934x_codec *wcd934x = dev_get_drvdata(component->dev);
int32_t zdet = 0;
snd_soc_component_write_field(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL,
WCD934X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl);
snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN5,
WCD934X_VTH_MASK, zdet_param->btn5);
snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN6,
WCD934X_VTH_MASK, zdet_param->btn6);
snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN7,
WCD934X_VTH_MASK, zdet_param->btn7);
snd_soc_component_write_field(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL,
WCD934X_ZDET_RANGE_CTL_MASK, zdet_param->noff);
snd_soc_component_update_bits(component, WCD934X_MBHC_NEW_ZDET_RAMP_CTL,
0x0F, zdet_param->nshift);
if (!zl)
goto z_right;
/* Start impedance measurement for HPH_L */
regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x80, 0x80);
wcd934x_mbhc_get_result_params(wcd934x, d1_a, zdet_param->noff, &zdet);
regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x80, 0x00);
*zl = zdet;
z_right:
if (!zr)
return;
/* Start impedance measurement for HPH_R */
regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x40, 0x40);
wcd934x_mbhc_get_result_params(wcd934x, d1_a, zdet_param->noff, &zdet);
regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x40, 0x00);
*zr = zdet;
}
static void wcd934x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component,
int32_t *z_val, int flag_l_r)
{
s16 q1;
int q1_cal;
if (*z_val < (WCD934X_ZDET_VAL_400/1000))
q1 = snd_soc_component_read(component,
WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT1 + (2 * flag_l_r));
else
q1 = snd_soc_component_read(component,
WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT2 + (2 * flag_l_r));
if (q1 & 0x80)
q1_cal = (10000 - ((q1 & 0x7F) * 25));
else
q1_cal = (10000 + (q1 * 25));
if (q1_cal > 0)
*z_val = ((*z_val) * 10000) / q1_cal;
}
static void wcd934x_wcd_mbhc_calc_impedance(struct snd_soc_component *component,
uint32_t *zl, uint32_t *zr)
{
struct wcd934x_codec *wcd934x = dev_get_drvdata(component->dev);
s16 reg0, reg1, reg2, reg3, reg4;
int32_t z1L, z1R, z1Ls;
int zMono, z_diff1, z_diff2;
bool is_fsm_disable = false;
struct wcd934x_mbhc_zdet_param zdet_param[] = {
{4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */
{2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */
{1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */
{1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */
};
struct wcd934x_mbhc_zdet_param *zdet_param_ptr = NULL;
s16 d1_a[][4] = {
{0, 30, 90, 30},
{0, 30, 30, 5},
{0, 30, 30, 5},
{0, 30, 30, 5},
};
s16 *d1 = NULL;
reg0 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN5);
reg1 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN6);
reg2 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN7);
reg3 = snd_soc_component_read(component, WCD934X_MBHC_CTL_CLK);
reg4 = snd_soc_component_read(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL);
if (snd_soc_component_read(component, WCD934X_ANA_MBHC_ELECT) & 0x80) {
is_fsm_disable = true;
regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ELECT, 0x80, 0x00);
}
/* For NO-jack, disable L_DET_EN before Z-det measurements */
if (wcd934x->mbhc_cfg.hphl_swh)
regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x80, 0x00);
/* Turn off 100k pull down on HPHL */
regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x01, 0x00);
/* First get impedance on Left */
d1 = d1_a[1];
zdet_param_ptr = &zdet_param[1];
wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1);
if (!WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z1L))
goto left_ch_impedance;
/* Second ramp for left ch */
if (z1L < WCD934X_ZDET_VAL_32) {
zdet_param_ptr = &zdet_param[0];
d1 = d1_a[0];
} else if ((z1L > WCD934X_ZDET_VAL_400) &&
(z1L <= WCD934X_ZDET_VAL_1200)) {
zdet_param_ptr = &zdet_param[2];
d1 = d1_a[2];
} else if (z1L > WCD934X_ZDET_VAL_1200) {
zdet_param_ptr = &zdet_param[3];
d1 = d1_a[3];
}
wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1);
left_ch_impedance:
if ((z1L == WCD934X_ZDET_FLOATING_IMPEDANCE) ||
(z1L > WCD934X_ZDET_VAL_100K)) {
*zl = WCD934X_ZDET_FLOATING_IMPEDANCE;
zdet_param_ptr = &zdet_param[1];
d1 = d1_a[1];
} else {
*zl = z1L/1000;
wcd934x_wcd_mbhc_qfuse_cal(component, zl, 0);
}
dev_info(component->dev, "%s: impedance on HPH_L = %d(ohms)\n",
__func__, *zl);
/* Start of right impedance ramp and calculation */
wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1);
if (WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z1R)) {
if (((z1R > WCD934X_ZDET_VAL_1200) &&
(zdet_param_ptr->noff == 0x6)) ||
((*zl) != WCD934X_ZDET_FLOATING_IMPEDANCE))
goto right_ch_impedance;
/* Second ramp for right ch */
if (z1R < WCD934X_ZDET_VAL_32) {
zdet_param_ptr = &zdet_param[0];
d1 = d1_a[0];
} else if ((z1R > WCD934X_ZDET_VAL_400) &&
(z1R <= WCD934X_ZDET_VAL_1200)) {
zdet_param_ptr = &zdet_param[2];
d1 = d1_a[2];
} else if (z1R > WCD934X_ZDET_VAL_1200) {
zdet_param_ptr = &zdet_param[3];
d1 = d1_a[3];
}
wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1);
}
right_ch_impedance:
if ((z1R == WCD934X_ZDET_FLOATING_IMPEDANCE) ||
(z1R > WCD934X_ZDET_VAL_100K)) {
*zr = WCD934X_ZDET_FLOATING_IMPEDANCE;
} else {
*zr = z1R/1000;
wcd934x_wcd_mbhc_qfuse_cal(component, zr, 1);
}
dev_err(component->dev, "%s: impedance on HPH_R = %d(ohms)\n",
__func__, *zr);
/* Mono/stereo detection */
if ((*zl == WCD934X_ZDET_FLOATING_IMPEDANCE) &&
(*zr == WCD934X_ZDET_FLOATING_IMPEDANCE)) {
dev_dbg(component->dev,
"%s: plug type is invalid or extension cable\n",
__func__);
goto zdet_complete;
}
if ((*zl == WCD934X_ZDET_FLOATING_IMPEDANCE) ||
(*zr == WCD934X_ZDET_FLOATING_IMPEDANCE) ||
((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) ||
((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) {
dev_dbg(component->dev,
"%s: Mono plug type with one ch floating or shorted to GND\n",
__func__);
wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_MONO);
goto zdet_complete;
}
snd_soc_component_write_field(component, WCD934X_HPH_R_ATEST,
WCD934X_HPHPA_GND_OVR_MASK, 1);
snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2,
WCD934X_HPHPA_GND_R_MASK, 1);
if (*zl < (WCD934X_ZDET_VAL_32/1000))
wcd934x_mbhc_zdet_ramp(component, &zdet_param[0], &z1Ls, NULL, d1);
else
wcd934x_mbhc_zdet_ramp(component, &zdet_param[1], &z1Ls, NULL, d1);
snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2,
WCD934X_HPHPA_GND_R_MASK, 0);
snd_soc_component_write_field(component, WCD934X_HPH_R_ATEST,
WCD934X_HPHPA_GND_OVR_MASK, 0);
z1Ls /= 1000;
wcd934x_wcd_mbhc_qfuse_cal(component, &z1Ls, 0);
/* Parallel of left Z and 9 ohm pull down resistor */
zMono = ((*zl) * 9) / ((*zl) + 9);
z_diff1 = (z1Ls > zMono) ? (z1Ls - zMono) : (zMono - z1Ls);
z_diff2 = ((*zl) > z1Ls) ? ((*zl) - z1Ls) : (z1Ls - (*zl));
if ((z_diff1 * (*zl + z1Ls)) > (z_diff2 * (z1Ls + zMono))) {
dev_err(component->dev, "%s: stereo plug type detected\n",
__func__);
wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_STEREO);
} else {
dev_err(component->dev, "%s: MONO plug type detected\n",
__func__);
wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_MONO);
}
zdet_complete:
snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN5, reg0);
snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN6, reg1);
snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN7, reg2);
/* Turn on 100k pull down on HPHL */
regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x01, 0x01);
/* For NO-jack, re-enable L_DET_EN after Z-det measurements */
if (wcd934x->mbhc_cfg.hphl_swh)
regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x80, 0x80);
snd_soc_component_write(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL, reg4);
snd_soc_component_write(component, WCD934X_MBHC_CTL_CLK, reg3);
if (is_fsm_disable)
regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ELECT, 0x80, 0x80);
}
static void wcd934x_mbhc_gnd_det_ctrl(struct snd_soc_component *component,
bool enable)
{
if (enable) {
snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH,
WCD934X_MBHC_HSG_PULLUP_COMP_EN, 1);
snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH,
WCD934X_MBHC_GND_DET_EN_MASK, 1);
} else {
snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH,
WCD934X_MBHC_GND_DET_EN_MASK, 0);
snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH,
WCD934X_MBHC_HSG_PULLUP_COMP_EN, 0);
}
}
static void wcd934x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component,
bool enable)
{
snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2,
WCD934X_HPHPA_GND_R_MASK, enable);
snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2,
WCD934X_HPHPA_GND_L_MASK, enable);
}
static const struct wcd_mbhc_cb mbhc_cb = {
.clk_setup = wcd934x_mbhc_clk_setup,
.mbhc_bias = wcd934x_mbhc_mbhc_bias_control,
.set_btn_thr = wcd934x_mbhc_program_btn_thr,
.micbias_enable_status = wcd934x_mbhc_micb_en_status,
.hph_pull_up_control = wcd934x_mbhc_hph_l_pull_up_control,
.mbhc_micbias_control = wcd934x_mbhc_request_micbias,
.mbhc_micb_ramp_control = wcd934x_mbhc_micb_ramp_control,
.mbhc_micb_ctrl_thr_mic = wcd934x_mbhc_micb_ctrl_threshold_mic,
.compute_impedance = wcd934x_wcd_mbhc_calc_impedance,
.mbhc_gnd_det_ctrl = wcd934x_mbhc_gnd_det_ctrl,
.hph_pull_down_ctrl = wcd934x_mbhc_hph_pull_down_ctrl,
};
static int wcd934x_get_hph_type(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd->mbhc);
return 0;
}
static int wcd934x_hph_impedance_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
uint32_t zl, zr;
bool hphr;
struct soc_mixer_control *mc;
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component);
mc = (struct soc_mixer_control *)(kcontrol->private_value);
hphr = mc->shift;
wcd_mbhc_get_impedance(wcd->mbhc, &zl, &zr);
dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr);
ucontrol->value.integer.value[0] = hphr ? zr : zl;
return 0;
}
static const struct snd_kcontrol_new hph_type_detect_controls[] = {
SOC_SINGLE_EXT("HPH Type", 0, 0, WCD_MBHC_HPH_STEREO, 0,
wcd934x_get_hph_type, NULL),
};
static const struct snd_kcontrol_new impedance_detect_controls[] = {
SOC_SINGLE_EXT("HPHL Impedance", 0, 0, INT_MAX, 0,
wcd934x_hph_impedance_get, NULL),
SOC_SINGLE_EXT("HPHR Impedance", 0, 1, INT_MAX, 0,
wcd934x_hph_impedance_get, NULL),
};
static int wcd934x_mbhc_init(struct snd_soc_component *component)
{
struct wcd934x_ddata *data = dev_get_drvdata(component->dev->parent);
struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component);
struct wcd_mbhc_intr *intr_ids = &wcd->intr_ids;
intr_ids->mbhc_sw_intr = regmap_irq_get_virq(data->irq_data,
WCD934X_IRQ_MBHC_SW_DET);
intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(data->irq_data,
WCD934X_IRQ_MBHC_BUTTON_PRESS_DET);
intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(data->irq_data,
WCD934X_IRQ_MBHC_BUTTON_RELEASE_DET);
intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(data->irq_data,
WCD934X_IRQ_MBHC_ELECT_INS_REM_LEG_DET);
intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(data->irq_data,
WCD934X_IRQ_MBHC_ELECT_INS_REM_DET);
intr_ids->hph_left_ocp = regmap_irq_get_virq(data->irq_data,
WCD934X_IRQ_HPH_PA_OCPL_FAULT);
intr_ids->hph_right_ocp = regmap_irq_get_virq(data->irq_data,
WCD934X_IRQ_HPH_PA_OCPR_FAULT);
wcd->mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true);
if (IS_ERR(wcd->mbhc)) {
wcd->mbhc = NULL;
return -EINVAL;
}
snd_soc_add_component_controls(component, impedance_detect_controls,
ARRAY_SIZE(impedance_detect_controls));
snd_soc_add_component_controls(component, hph_type_detect_controls,
ARRAY_SIZE(hph_type_detect_controls));
return 0;
}
static void wcd934x_mbhc_deinit(struct snd_soc_component *component)
{
struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component);
if (!wcd->mbhc)
return;
wcd_mbhc_deinit(wcd->mbhc);
}
static int wcd934x_comp_probe(struct snd_soc_component *component)
{
struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
int i;
snd_soc_component_init_regmap(component, wcd->regmap);
wcd->component = component;
/* Class-H Init*/
wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, wcd->version);
if (IS_ERR(wcd->clsh_ctrl))
return PTR_ERR(wcd->clsh_ctrl);
/* Default HPH Mode to Class-H Low HiFi */
wcd->hph_mode = CLS_H_LOHIFI;
wcd934x_comp_init(component);
for (i = 0; i < NUM_CODEC_DAIS; i++)
INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list);
wcd934x_init_dmic(component);
if (wcd934x_mbhc_init(component))
dev_err(component->dev, "Failed to Initialize MBHC\n");
return 0;
}
static void wcd934x_comp_remove(struct snd_soc_component *comp)
{
struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
wcd934x_mbhc_deinit(comp);
wcd_clsh_ctrl_free(wcd->clsh_ctrl);
}
static int wcd934x_comp_set_sysclk(struct snd_soc_component *comp,
int clk_id, int source,
unsigned int freq, int dir)
{
struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
int val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ;
wcd->rate = freq;
if (wcd->rate == WCD934X_MCLK_CLK_12P288MHZ)
val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ;
snd_soc_component_update_bits(comp, WCD934X_CODEC_RPM_CLK_MCLK_CFG,
WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
val);
return clk_set_rate(wcd->extclk, freq);
}
static uint32_t get_iir_band_coeff(struct snd_soc_component *component,
int iir_idx, int band_idx, int coeff_idx)
{
u32 value = 0;
int reg, b2_reg;
/* Address does not automatically update if reading */
reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx;
b2_reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx;
snd_soc_component_write(component, reg,
((band_idx * BAND_MAX + coeff_idx) *
sizeof(uint32_t)) & 0x7F);
value |= snd_soc_component_read(component, b2_reg);
snd_soc_component_write(component, reg,
((band_idx * BAND_MAX + coeff_idx)
* sizeof(uint32_t) + 1) & 0x7F);
value |= (snd_soc_component_read(component, b2_reg) << 8);
snd_soc_component_write(component, reg,
((band_idx * BAND_MAX + coeff_idx)
* sizeof(uint32_t) + 2) & 0x7F);
value |= (snd_soc_component_read(component, b2_reg) << 16);
snd_soc_component_write(component, reg,
((band_idx * BAND_MAX + coeff_idx)
* sizeof(uint32_t) + 3) & 0x7F);
/* Mask bits top 2 bits since they are reserved */
value |= (snd_soc_component_read(component, b2_reg) << 24);
return value;
}
static void set_iir_band_coeff(struct snd_soc_component *component,
int iir_idx, int band_idx, uint32_t value)
{
int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx;
snd_soc_component_write(component, reg, (value & 0xFF));
snd_soc_component_write(component, reg, (value >> 8) & 0xFF);
snd_soc_component_write(component, reg, (value >> 16) & 0xFF);
/* Mask top 2 bits, 7-8 are reserved */
snd_soc_component_write(component, reg, (value >> 24) & 0x3F);
}
static int wcd934x_put_iir_band_audio_mixer(
struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct wcd_iir_filter_ctl *ctl =
(struct wcd_iir_filter_ctl *)kcontrol->private_value;
struct soc_bytes_ext *params = &ctl->bytes_ext;
int iir_idx = ctl->iir_idx;
int band_idx = ctl->band_idx;
u32 coeff[BAND_MAX];
int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx;
memcpy(&coeff[0], ucontrol->value.bytes.data, params->max);
/* Mask top bit it is reserved */
/* Updates addr automatically for each B2 write */
snd_soc_component_write(component, reg, (band_idx * BAND_MAX *
sizeof(uint32_t)) & 0x7F);
set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]);
set_iir_band_coeff(component, iir_idx, band_idx, coeff[1]);
set_iir_band_coeff(component, iir_idx, band_idx, coeff[2]);
set_iir_band_coeff(component, iir_idx, band_idx, coeff[3]);
set_iir_band_coeff(component, iir_idx, band_idx, coeff[4]);
return 0;
}
static int wcd934x_get_iir_band_audio_mixer(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct wcd_iir_filter_ctl *ctl =
(struct wcd_iir_filter_ctl *)kcontrol->private_value;
struct soc_bytes_ext *params = &ctl->bytes_ext;
int iir_idx = ctl->iir_idx;
int band_idx = ctl->band_idx;
u32 coeff[BAND_MAX];
coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0);
coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, 1);
coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, 2);
coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, 3);
coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, 4);
memcpy(ucontrol->value.bytes.data, &coeff[0], params->max);
return 0;
}
static int wcd934x_iir_filter_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *ucontrol)
{
struct wcd_iir_filter_ctl *ctl =
(struct wcd_iir_filter_ctl *)kcontrol->private_value;
struct soc_bytes_ext *params = &ctl->bytes_ext;
ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
ucontrol->count = params->max;
return 0;
}
static int wcd934x_compander_get(struct snd_kcontrol *kc,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
ucontrol->value.integer.value[0] = wcd->comp_enabled[comp];
return 0;
}
static int wcd934x_compander_set(struct snd_kcontrol *kc,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
int value = ucontrol->value.integer.value[0];
int sel;
if (wcd->comp_enabled[comp] == value)
return 0;
wcd->comp_enabled[comp] = value;
sel = value ? WCD934X_HPH_GAIN_SRC_SEL_COMPANDER :
WCD934X_HPH_GAIN_SRC_SEL_REGISTER;
/* Any specific register configuration for compander */
switch (comp) {
case COMPANDER_1:
/* Set Gain Source Select based on compander enable/disable */
snd_soc_component_update_bits(component, WCD934X_HPH_L_EN,
WCD934X_HPH_GAIN_SRC_SEL_MASK,
sel);
break;
case COMPANDER_2:
snd_soc_component_update_bits(component, WCD934X_HPH_R_EN,
WCD934X_HPH_GAIN_SRC_SEL_MASK,
sel);
break;
case COMPANDER_3:
case COMPANDER_4:
case COMPANDER_7:
case COMPANDER_8:
break;
default:
return 0;
}
return 1;
}
static int wcd934x_rx_hph_mode_get(struct snd_kcontrol *kc,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
ucontrol->value.enumerated.item[0] = wcd->hph_mode;
return 0;
}
static int wcd934x_rx_hph_mode_put(struct snd_kcontrol *kc,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
u32 mode_val;
mode_val = ucontrol->value.enumerated.item[0];
if (mode_val == wcd->hph_mode)
return 0;
if (mode_val == 0) {
dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n");
mode_val = CLS_H_LOHIFI;
}
wcd->hph_mode = mode_val;
return 1;
}
static int slim_rx_mux_get(struct snd_kcontrol *kc,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev);
ucontrol->value.enumerated.item[0] = wcd->rx_port_value[w->shift];
return 0;
}
static int slim_rx_mux_to_dai_id(int mux)
{
int aif_id;
switch (mux) {
case 1:
aif_id = AIF1_PB;
break;
case 2:
aif_id = AIF2_PB;
break;
case 3:
aif_id = AIF3_PB;
break;
case 4:
aif_id = AIF4_PB;
break;
default:
aif_id = -1;
break;
}
return aif_id;
}
static int slim_rx_mux_put(struct snd_kcontrol *kc,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
struct wcd934x_codec *wcd = dev_get_drvdata(w->dapm->dev);
struct soc_enum *e = (struct soc_enum *)kc->private_value;
struct snd_soc_dapm_update *update = NULL;
struct wcd934x_slim_ch *ch, *c;
u32 port_id = w->shift;
bool found = false;
int mux_idx;
int prev_mux_idx = wcd->rx_port_value[port_id];
int aif_id;
mux_idx = ucontrol->value.enumerated.item[0];
if (mux_idx == prev_mux_idx)
return 0;
switch(mux_idx) {
case 0:
aif_id = slim_rx_mux_to_dai_id(prev_mux_idx);
if (aif_id < 0)
return 0;
list_for_each_entry_safe(ch, c, &wcd->dai[aif_id].slim_ch_list, list) {
if (ch->port == port_id + WCD934X_RX_START) {
found = true;
list_del_init(&ch->list);
break;
}
}
if (!found)
return 0;
break;
case 1 ... 4:
aif_id = slim_rx_mux_to_dai_id(mux_idx);
if (aif_id < 0)
return 0;
if (list_empty(&wcd->rx_chs[port_id].list)) {
list_add_tail(&wcd->rx_chs[port_id].list,
&wcd->dai[aif_id].slim_ch_list);
} else {
dev_err(wcd->dev ,"SLIM_RX%d PORT is busy\n", port_id);
return 0;
}
break;
default:
dev_err(wcd->dev, "Unknown AIF %d\n", mux_idx);
goto err;
}
wcd->rx_port_value[port_id] = mux_idx;
snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value[port_id],
e, update);
return 1;
err:
return -EINVAL;
}
static int wcd934x_int_dem_inp_mux_put(struct snd_kcontrol *kc,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_enum *e = (struct soc_enum *)kc->private_value;
struct snd_soc_component *component;
int reg, val;
component = snd_soc_dapm_kcontrol_component(kc);
val = ucontrol->value.enumerated.item[0];
if (e->reg == WCD934X_CDC_RX0_RX_PATH_SEC0)
reg = WCD934X_CDC_RX0_RX_PATH_CFG0;
else if (e->reg == WCD934X_CDC_RX1_RX_PATH_SEC0)
reg = WCD934X_CDC_RX1_RX_PATH_CFG0;
else if (e->reg == WCD934X_CDC_RX2_RX_PATH_SEC0)
reg = WCD934X_CDC_RX2_RX_PATH_CFG0;
else
return -EINVAL;
/* Set Look Ahead Delay */
if (val)
snd_soc_component_update_bits(component, reg,
WCD934X_RX_DLY_ZN_EN_MASK,
WCD934X_RX_DLY_ZN_ENABLE);
else
snd_soc_component_update_bits(component, reg,
WCD934X_RX_DLY_ZN_EN_MASK,
WCD934X_RX_DLY_ZN_DISABLE);
return snd_soc_dapm_put_enum_double(kc, ucontrol);
}
static int wcd934x_dec_enum_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *comp;
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int val;
u16 mic_sel_reg = 0;
u8 mic_sel;
comp = snd_soc_dapm_kcontrol_component(kcontrol);
val = ucontrol->value.enumerated.item[0];
if (val > e->items - 1)
return -EINVAL;
switch (e->reg) {
case WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1:
if (e->shift_l == 0)
mic_sel_reg = WCD934X_CDC_TX0_TX_PATH_CFG0;
else if (e->shift_l == 2)
mic_sel_reg = WCD934X_CDC_TX4_TX_PATH_CFG0;
else if (e->shift_l == 4)
mic_sel_reg = WCD934X_CDC_TX8_TX_PATH_CFG0;
break;
case WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1:
if (e->shift_l == 0)
mic_sel_reg = WCD934X_CDC_TX1_TX_PATH_CFG0;
else if (e->shift_l == 2)
mic_sel_reg = WCD934X_CDC_TX5_TX_PATH_CFG0;
break;
case WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1:
if (e->shift_l == 0)
mic_sel_reg = WCD934X_CDC_TX2_TX_PATH_CFG0;
else if (e->shift_l == 2)
mic_sel_reg = WCD934X_CDC_TX6_TX_PATH_CFG0;
break;
case WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1:
if (e->shift_l == 0)
mic_sel_reg = WCD934X_CDC_TX3_TX_PATH_CFG0;
else if (e->shift_l == 2)
mic_sel_reg = WCD934X_CDC_TX7_TX_PATH_CFG0;
break;
default:
dev_err(comp->dev, "%s: e->reg: 0x%x not expected\n",
__func__, e->reg);
return -EINVAL;
}
/* ADC: 0, DMIC: 1 */
mic_sel = val ? 0x0 : 0x1;
if (mic_sel_reg)
snd_soc_component_update_bits(comp, mic_sel_reg, BIT(7),
mic_sel << 7);
return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
}
static const struct snd_kcontrol_new rx_int0_2_mux =
SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum);
static const struct snd_kcontrol_new rx_int1_2_mux =
SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum);
static const struct snd_kcontrol_new rx_int2_2_mux =
SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum);
static const struct snd_kcontrol_new rx_int3_2_mux =
SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum);
static const struct snd_kcontrol_new rx_int4_2_mux =
SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum);
static const struct snd_kcontrol_new rx_int7_2_mux =
SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum);
static const struct snd_kcontrol_new rx_int8_2_mux =
SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum);
static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux =
SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum);
static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux =
SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum);
static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux =
SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum);
static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux =
SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum);
static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux =
SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum);
static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux =
SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum);
static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux =
SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum);
static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux =
SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum);
static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux =
SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum);
static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux =
SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum);
static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux =
SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum);
static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux =
SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum);
static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux =
SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum);
static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux =
SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum);
static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux =
SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum);
static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux =
SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum);
static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux =
SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum);
static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux =
SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum);
static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux =
SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum);
static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux =
SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum);
static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux =
SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum);
static const struct snd_kcontrol_new rx_int0_mix2_inp_mux =
SOC_DAPM_ENUM("RX INT0 MIX2 INP Mux", rx_int0_mix2_inp_mux_enum);
static const struct snd_kcontrol_new rx_int1_mix2_inp_mux =
SOC_DAPM_ENUM("RX INT1 MIX2 INP Mux", rx_int1_mix2_inp_mux_enum);
static const struct snd_kcontrol_new rx_int2_mix2_inp_mux =
SOC_DAPM_ENUM("RX INT2 MIX2 INP Mux", rx_int2_mix2_inp_mux_enum);
static const struct snd_kcontrol_new rx_int3_mix2_inp_mux =
SOC_DAPM_ENUM("RX INT3 MIX2 INP Mux", rx_int3_mix2_inp_mux_enum);
static const struct snd_kcontrol_new rx_int4_mix2_inp_mux =
SOC_DAPM_ENUM("RX INT4 MIX2 INP Mux", rx_int4_mix2_inp_mux_enum);
static const struct snd_kcontrol_new rx_int7_mix2_inp_mux =
SOC_DAPM_ENUM("RX INT7 MIX2 INP Mux", rx_int7_mix2_inp_mux_enum);
static const struct snd_kcontrol_new iir0_inp0_mux =
SOC_DAPM_ENUM("IIR0 INP0 Mux", iir0_inp0_mux_enum);
static const struct snd_kcontrol_new iir0_inp1_mux =
SOC_DAPM_ENUM("IIR0 INP1 Mux", iir0_inp1_mux_enum);
static const struct snd_kcontrol_new iir0_inp2_mux =
SOC_DAPM_ENUM("IIR0 INP2 Mux", iir0_inp2_mux_enum);
static const struct snd_kcontrol_new iir0_inp3_mux =
SOC_DAPM_ENUM("IIR0 INP3 Mux", iir0_inp3_mux_enum);
static const struct snd_kcontrol_new iir1_inp0_mux =
SOC_DAPM_ENUM("IIR1 INP0 Mux", iir1_inp0_mux_enum);
static const struct snd_kcontrol_new iir1_inp1_mux =
SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum);
static const struct snd_kcontrol_new iir1_inp2_mux =
SOC_DAPM_ENUM("IIR1 INP2 Mux", iir1_inp2_mux_enum);
static const struct snd_kcontrol_new iir1_inp3_mux =
SOC_DAPM_ENUM("IIR1 INP3 Mux", iir1_inp3_mux_enum);
static const struct snd_kcontrol_new slim_rx_mux[WCD934X_RX_MAX] = {
SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum,
slim_rx_mux_get, slim_rx_mux_put),
SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum,
slim_rx_mux_get, slim_rx_mux_put),
SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum,
slim_rx_mux_get, slim_rx_mux_put),
SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum,
slim_rx_mux_get, slim_rx_mux_put),
SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum,
slim_rx_mux_get, slim_rx_mux_put),
SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum,
slim_rx_mux_get, slim_rx_mux_put),
SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum,
slim_rx_mux_get, slim_rx_mux_put),
SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum,
slim_rx_mux_get, slim_rx_mux_put),
};
static const struct snd_kcontrol_new rx_int1_asrc_switch[] = {
SOC_DAPM_SINGLE("HPHL Switch", SND_SOC_NOPM, 0, 1, 0),
};
static const struct snd_kcontrol_new rx_int2_asrc_switch[] = {
SOC_DAPM_SINGLE("HPHR Switch", SND_SOC_NOPM, 0, 1, 0),
};
static const struct snd_kcontrol_new rx_int3_asrc_switch[] = {
SOC_DAPM_SINGLE("LO1 Switch", SND_SOC_NOPM, 0, 1, 0),
};
static const struct snd_kcontrol_new rx_int4_asrc_switch[] = {
SOC_DAPM_SINGLE("LO2 Switch", SND_SOC_NOPM, 0, 1, 0),
};
static const struct snd_kcontrol_new rx_int0_dem_inp_mux =
SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum,
snd_soc_dapm_get_enum_double,
wcd934x_int_dem_inp_mux_put);
static const struct snd_kcontrol_new rx_int1_dem_inp_mux =
SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum,
snd_soc_dapm_get_enum_double,
wcd934x_int_dem_inp_mux_put);
static const struct snd_kcontrol_new rx_int2_dem_inp_mux =
SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum,
snd_soc_dapm_get_enum_double,
wcd934x_int_dem_inp_mux_put);
static const struct snd_kcontrol_new rx_int0_1_interp_mux =
SOC_DAPM_ENUM("RX INT0_1 INTERP Mux", rx_int0_1_interp_mux_enum);
static const struct snd_kcontrol_new rx_int1_1_interp_mux =
SOC_DAPM_ENUM("RX INT1_1 INTERP Mux", rx_int1_1_interp_mux_enum);
static const struct snd_kcontrol_new rx_int2_1_interp_mux =
SOC_DAPM_ENUM("RX INT2_1 INTERP Mux", rx_int2_1_interp_mux_enum);
static const struct snd_kcontrol_new rx_int3_1_interp_mux =
SOC_DAPM_ENUM("RX INT3_1 INTERP Mux", rx_int3_1_interp_mux_enum);
static const struct snd_kcontrol_new rx_int4_1_interp_mux =
SOC_DAPM_ENUM("RX INT4_1 INTERP Mux", rx_int4_1_interp_mux_enum);
static const struct snd_kcontrol_new rx_int7_1_interp_mux =
SOC_DAPM_ENUM("RX INT7_1 INTERP Mux", rx_int7_1_interp_mux_enum);
static const struct snd_kcontrol_new rx_int8_1_interp_mux =
SOC_DAPM_ENUM("RX INT8_1 INTERP Mux", rx_int8_1_interp_mux_enum);
static const struct snd_kcontrol_new rx_int0_2_interp_mux =
SOC_DAPM_ENUM("RX INT0_2 INTERP Mux", rx_int0_2_interp_mux_enum);
static const struct snd_kcontrol_new rx_int1_2_interp_mux =
SOC_DAPM_ENUM("RX INT1_2 INTERP Mux", rx_int1_2_interp_mux_enum);
static const struct snd_kcontrol_new rx_int2_2_interp_mux =
SOC_DAPM_ENUM("RX INT2_2 INTERP Mux", rx_int2_2_interp_mux_enum);
static const struct snd_kcontrol_new rx_int3_2_interp_mux =
SOC_DAPM_ENUM("RX INT3_2 INTERP Mux", rx_int3_2_interp_mux_enum);
static const struct snd_kcontrol_new rx_int4_2_interp_mux =
SOC_DAPM_ENUM("RX INT4_2 INTERP Mux", rx_int4_2_interp_mux_enum);
static const struct snd_kcontrol_new rx_int7_2_interp_mux =
SOC_DAPM_ENUM("RX INT7_2 INTERP Mux", rx_int7_2_interp_mux_enum);
static const struct snd_kcontrol_new rx_int8_2_interp_mux =
SOC_DAPM_ENUM("RX INT8_2 INTERP Mux", rx_int8_2_interp_mux_enum);
static const struct snd_kcontrol_new tx_dmic_mux0 =
SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum);
static const struct snd_kcontrol_new tx_dmic_mux1 =
SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum);
static const struct snd_kcontrol_new tx_dmic_mux2 =
SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum);
static const struct snd_kcontrol_new tx_dmic_mux3 =
SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum);
static const struct snd_kcontrol_new tx_dmic_mux4 =
SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum);
static const struct snd_kcontrol_new tx_dmic_mux5 =
SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum);
static const struct snd_kcontrol_new tx_dmic_mux6 =
SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum);
static const struct snd_kcontrol_new tx_dmic_mux7 =
SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum);
static const struct snd_kcontrol_new tx_dmic_mux8 =
SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum);
static const struct snd_kcontrol_new tx_amic_mux0 =
SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum);
static const struct snd_kcontrol_new tx_amic_mux1 =
SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum);
static const struct snd_kcontrol_new tx_amic_mux2 =
SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum);
static const struct snd_kcontrol_new tx_amic_mux3 =
SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum);
static const struct snd_kcontrol_new tx_amic_mux4 =
SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum);
static const struct snd_kcontrol_new tx_amic_mux5 =
SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum);
static const struct snd_kcontrol_new tx_amic_mux6 =
SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum);
static const struct snd_kcontrol_new tx_amic_mux7 =
SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum);
static const struct snd_kcontrol_new tx_amic_mux8 =
SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum);
static const struct snd_kcontrol_new tx_amic4_5 =
SOC_DAPM_ENUM("AMIC4_5 SEL Mux", tx_amic4_5_enum);
static const struct snd_kcontrol_new tx_adc_mux0_mux =
SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_enum,
snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
static const struct snd_kcontrol_new tx_adc_mux1_mux =
SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_enum,
snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
static const struct snd_kcontrol_new tx_adc_mux2_mux =
SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_enum,
snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
static const struct snd_kcontrol_new tx_adc_mux3_mux =
SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_enum,
snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
static const struct snd_kcontrol_new tx_adc_mux4_mux =
SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_enum,
snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
static const struct snd_kcontrol_new tx_adc_mux5_mux =
SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_enum,
snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
static const struct snd_kcontrol_new tx_adc_mux6_mux =
SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_enum,
snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
static const struct snd_kcontrol_new tx_adc_mux7_mux =
SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_enum,
snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
static const struct snd_kcontrol_new tx_adc_mux8_mux =
SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_enum,
snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
static const struct snd_kcontrol_new cdc_if_tx0_mux =
SOC_DAPM_ENUM("CDC_IF TX0 MUX Mux", cdc_if_tx0_mux_enum);
static const struct snd_kcontrol_new cdc_if_tx1_mux =
SOC_DAPM_ENUM("CDC_IF TX1 MUX Mux", cdc_if_tx1_mux_enum);
static const struct snd_kcontrol_new cdc_if_tx2_mux =
SOC_DAPM_ENUM("CDC_IF TX2 MUX Mux", cdc_if_tx2_mux_enum);
static const struct snd_kcontrol_new cdc_if_tx3_mux =
SOC_DAPM_ENUM("CDC_IF TX3 MUX Mux", cdc_if_tx3_mux_enum);
static const struct snd_kcontrol_new cdc_if_tx4_mux =
SOC_DAPM_ENUM("CDC_IF TX4 MUX Mux", cdc_if_tx4_mux_enum);
static const struct snd_kcontrol_new cdc_if_tx5_mux =
SOC_DAPM_ENUM("CDC_IF TX5 MUX Mux", cdc_if_tx5_mux_enum);
static const struct snd_kcontrol_new cdc_if_tx6_mux =
SOC_DAPM_ENUM("CDC_IF TX6 MUX Mux", cdc_if_tx6_mux_enum);
static const struct snd_kcontrol_new cdc_if_tx7_mux =
SOC_DAPM_ENUM("CDC_IF TX7 MUX Mux", cdc_if_tx7_mux_enum);
static const struct snd_kcontrol_new cdc_if_tx8_mux =
SOC_DAPM_ENUM("CDC_IF TX8 MUX Mux", cdc_if_tx8_mux_enum);
static const struct snd_kcontrol_new cdc_if_tx9_mux =
SOC_DAPM_ENUM("CDC_IF TX9 MUX Mux", cdc_if_tx9_mux_enum);
static const struct snd_kcontrol_new cdc_if_tx10_mux =
SOC_DAPM_ENUM("CDC_IF TX10 MUX Mux", cdc_if_tx10_mux_enum);
static const struct snd_kcontrol_new cdc_if_tx11_mux =
SOC_DAPM_ENUM("CDC_IF TX11 MUX Mux", cdc_if_tx11_mux_enum);
static const struct snd_kcontrol_new cdc_if_tx11_inp1_mux =
SOC_DAPM_ENUM("CDC_IF TX11 INP1 MUX Mux", cdc_if_tx11_inp1_mux_enum);
static const struct snd_kcontrol_new cdc_if_tx13_mux =
SOC_DAPM_ENUM("CDC_IF TX13 MUX Mux", cdc_if_tx13_mux_enum);
static const struct snd_kcontrol_new cdc_if_tx13_inp1_mux =
SOC_DAPM_ENUM("CDC_IF TX13 INP1 MUX Mux", cdc_if_tx13_inp1_mux_enum);
static int slim_tx_mixer_get(struct snd_kcontrol *kc,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev);
struct soc_mixer_control *mixer =
(struct soc_mixer_control *)kc->private_value;
int port_id = mixer->shift;
ucontrol->value.integer.value[0] = wcd->tx_port_value[port_id];
return 0;
}
static int slim_tx_mixer_put(struct snd_kcontrol *kc,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc);
struct wcd934x_codec *wcd = dev_get_drvdata(widget->dapm->dev);
struct snd_soc_dapm_update *update = NULL;
struct soc_mixer_control *mixer =
(struct soc_mixer_control *)kc->private_value;
int enable = ucontrol->value.integer.value[0];
struct wcd934x_slim_ch *ch, *c;
int dai_id = widget->shift;
int port_id = mixer->shift;
/* only add to the list if value not set */
if (enable == wcd->tx_port_value[port_id])
return 0;
if (enable) {
if (list_empty(&wcd->tx_chs[port_id].list)) {
list_add_tail(&wcd->tx_chs[port_id].list,
&wcd->dai[dai_id].slim_ch_list);
} else {
dev_err(wcd->dev ,"SLIM_TX%d PORT is busy\n", port_id);
return 0;
}
} else {
bool found = false;
list_for_each_entry_safe(ch, c, &wcd->dai[dai_id].slim_ch_list, list) {
if (ch->port == port_id) {
found = true;
list_del_init(&wcd->tx_chs[port_id].list);
break;
}
}
if (!found)
return 0;
}
wcd->tx_port_value[port_id] = enable;
snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update);
return 1;
}
static const struct snd_kcontrol_new aif1_slim_cap_mixer[] = {
SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
};
static const struct snd_kcontrol_new aif2_slim_cap_mixer[] = {
SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
};
static const struct snd_kcontrol_new aif3_slim_cap_mixer[] = {
SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
slim_tx_mixer_get, slim_tx_mixer_put),
};
static const struct snd_kcontrol_new wcd934x_snd_controls[] = {
/* Gain Controls */
SOC_SINGLE_TLV("EAR PA Volume", WCD934X_ANA_EAR, 4, 4, 1, ear_pa_gain),
SOC_SINGLE_TLV("HPHL Volume", WCD934X_HPH_L_EN, 0, 24, 1, line_gain),
SOC_SINGLE_TLV("HPHR Volume", WCD934X_HPH_R_EN, 0, 24, 1, line_gain),
SOC_SINGLE_TLV("LINEOUT1 Volume", WCD934X_DIFF_LO_LO1_COMPANDER,
3, 16, 1, line_gain),
SOC_SINGLE_TLV("LINEOUT2 Volume", WCD934X_DIFF_LO_LO2_COMPANDER,
3, 16, 1, line_gain),
SOC_SINGLE_TLV("ADC1 Volume", WCD934X_ANA_AMIC1, 0, 20, 0, analog_gain),
SOC_SINGLE_TLV("ADC2 Volume", WCD934X_ANA_AMIC2, 0, 20, 0, analog_gain),
SOC_SINGLE_TLV("ADC3 Volume", WCD934X_ANA_AMIC3, 0, 20, 0, analog_gain),
SOC_SINGLE_TLV("ADC4 Volume", WCD934X_ANA_AMIC4, 0, 20, 0, analog_gain),
SOC_SINGLE_S8_TLV("RX0 Digital Volume", WCD934X_CDC_RX0_RX_VOL_CTL,
-84, 40, digital_gain), /* -84dB min - 40dB max */
SOC_SINGLE_S8_TLV("RX1 Digital Volume", WCD934X_CDC_RX1_RX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX2 Digital Volume", WCD934X_CDC_RX2_RX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX3 Digital Volume", WCD934X_CDC_RX3_RX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX4 Digital Volume", WCD934X_CDC_RX4_RX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX7 Digital Volume", WCD934X_CDC_RX7_RX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX8 Digital Volume", WCD934X_CDC_RX8_RX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX0 Mix Digital Volume",
WCD934X_CDC_RX0_RX_VOL_MIX_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX1 Mix Digital Volume",
WCD934X_CDC_RX1_RX_VOL_MIX_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX2 Mix Digital Volume",
WCD934X_CDC_RX2_RX_VOL_MIX_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX3 Mix Digital Volume",
WCD934X_CDC_RX3_RX_VOL_MIX_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX4 Mix Digital Volume",
WCD934X_CDC_RX4_RX_VOL_MIX_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX7 Mix Digital Volume",
WCD934X_CDC_RX7_RX_VOL_MIX_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX8 Mix Digital Volume",
WCD934X_CDC_RX8_RX_VOL_MIX_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("DEC0 Volume", WCD934X_CDC_TX0_TX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("DEC1 Volume", WCD934X_CDC_TX1_TX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("DEC2 Volume", WCD934X_CDC_TX2_TX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("DEC3 Volume", WCD934X_CDC_TX3_TX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("DEC4 Volume", WCD934X_CDC_TX4_TX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("DEC5 Volume", WCD934X_CDC_TX5_TX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("DEC6 Volume", WCD934X_CDC_TX6_TX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("DEC7 Volume", WCD934X_CDC_TX7_TX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("DEC8 Volume", WCD934X_CDC_TX8_TX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("IIR0 INP0 Volume",
WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40,
digital_gain),
SOC_SINGLE_S8_TLV("IIR0 INP1 Volume",
WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40,
digital_gain),
SOC_SINGLE_S8_TLV("IIR0 INP2 Volume",
WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40,
digital_gain),
SOC_SINGLE_S8_TLV("IIR0 INP3 Volume",
WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40,
digital_gain),
SOC_SINGLE_S8_TLV("IIR1 INP0 Volume",
WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40,
digital_gain),
SOC_SINGLE_S8_TLV("IIR1 INP1 Volume",
WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40,
digital_gain),
SOC_SINGLE_S8_TLV("IIR1 INP2 Volume",
WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40,
digital_gain),
SOC_SINGLE_S8_TLV("IIR1 INP3 Volume",
WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40,
digital_gain),
SOC_ENUM("TX0 HPF cut off", cf_dec0_enum),
SOC_ENUM("TX1 HPF cut off", cf_dec1_enum),
SOC_ENUM("TX2 HPF cut off", cf_dec2_enum),
SOC_ENUM("TX3 HPF cut off", cf_dec3_enum),
SOC_ENUM("TX4 HPF cut off", cf_dec4_enum),
SOC_ENUM("TX5 HPF cut off", cf_dec5_enum),
SOC_ENUM("TX6 HPF cut off", cf_dec6_enum),
SOC_ENUM("TX7 HPF cut off", cf_dec7_enum),
SOC_ENUM("TX8 HPF cut off", cf_dec8_enum),
SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum),
SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum),
SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum),
SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum),
SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum),
SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum),
SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum),
SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum),
SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum),
SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum),
SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum),
SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum),
SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum),
SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum),
SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
wcd934x_rx_hph_mode_get, wcd934x_rx_hph_mode_put),
SOC_SINGLE("IIR1 Band1 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
0, 1, 0),
SOC_SINGLE("IIR1 Band2 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
1, 1, 0),
SOC_SINGLE("IIR1 Band3 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
2, 1, 0),
SOC_SINGLE("IIR1 Band4 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
3, 1, 0),
SOC_SINGLE("IIR1 Band5 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4, 1, 0),
SOC_SINGLE("IIR2 Band1 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
0, 1, 0),
SOC_SINGLE("IIR2 Band2 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
1, 1, 0),
SOC_SINGLE("IIR2 Band3 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
2, 1, 0),
SOC_SINGLE("IIR2 Band4 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
3, 1, 0),
SOC_SINGLE("IIR2 Band5 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
4, 1, 0),
WCD_IIR_FILTER_CTL("IIR0 Band1", IIR0, BAND1),
WCD_IIR_FILTER_CTL("IIR0 Band2", IIR0, BAND2),
WCD_IIR_FILTER_CTL("IIR0 Band3", IIR0, BAND3),
WCD_IIR_FILTER_CTL("IIR0 Band4", IIR0, BAND4),
WCD_IIR_FILTER_CTL("IIR0 Band5", IIR0, BAND5),
WCD_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1),
WCD_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2),
WCD_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3),
WCD_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4),
WCD_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5),
SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0,
wcd934x_compander_get, wcd934x_compander_set),
SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0,
wcd934x_compander_get, wcd934x_compander_set),
SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0,
wcd934x_compander_get, wcd934x_compander_set),
SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0,
wcd934x_compander_get, wcd934x_compander_set),
SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0,
wcd934x_compander_get, wcd934x_compander_set),
SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0,
wcd934x_compander_get, wcd934x_compander_set),
};
static void wcd934x_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai,
struct snd_soc_component *component)
{
int port_num = 0;
unsigned short reg = 0;
unsigned int val = 0;
struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
struct wcd934x_slim_ch *ch;
list_for_each_entry(ch, &dai->slim_ch_list, list) {
if (ch->port >= WCD934X_RX_START) {
port_num = ch->port - WCD934X_RX_START;
reg = WCD934X_SLIM_PGD_PORT_INT_EN0 + (port_num / 8);
} else {
port_num = ch->port;
reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8);
}
regmap_read(wcd->if_regmap, reg, &val);
if (!(val & BIT(port_num % 8)))
regmap_write(wcd->if_regmap, reg,
val | BIT(port_num % 8));
}
}
static int wcd934x_codec_enable_slim(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kc, int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift];
switch (event) {
case SND_SOC_DAPM_POST_PMU:
wcd934x_codec_enable_int_port(dai, comp);
break;
}
return 0;
}
static void wcd934x_codec_hd2_control(struct snd_soc_component *component,
u16 interp_idx, int event)
{
u16 hd2_scale_reg;
u16 hd2_enable_reg = 0;
switch (interp_idx) {
case INTERP_HPHL:
hd2_scale_reg = WCD934X_CDC_RX1_RX_PATH_SEC3;
hd2_enable_reg = WCD934X_CDC_RX1_RX_PATH_CFG0;
break;
case INTERP_HPHR:
hd2_scale_reg = WCD934X_CDC_RX2_RX_PATH_SEC3;
hd2_enable_reg = WCD934X_CDC_RX2_RX_PATH_CFG0;
break;
default:
return;
}
if (SND_SOC_DAPM_EVENT_ON(event)) {
snd_soc_component_update_bits(component, hd2_scale_reg,
WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P3125);
snd_soc_component_update_bits(component, hd2_enable_reg,
WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK,
WCD934X_CDC_RX_PATH_CFG_HD2_ENABLE);
}
if (SND_SOC_DAPM_EVENT_OFF(event)) {
snd_soc_component_update_bits(component, hd2_enable_reg,
WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK,
WCD934X_CDC_RX_PATH_CFG_HD2_DISABLE);
snd_soc_component_update_bits(component, hd2_scale_reg,
WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000);
}
}
static void wcd934x_codec_hphdelay_lutbypass(struct snd_soc_component *comp,
u16 interp_idx, int event)
{
u8 hph_dly_mask;
u16 hph_lut_bypass_reg = 0;
switch (interp_idx) {
case INTERP_HPHL:
hph_dly_mask = 1;
hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHL_COMP_LUT;
break;
case INTERP_HPHR:
hph_dly_mask = 2;
hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHR_COMP_LUT;
break;
default:
return;
}
if (SND_SOC_DAPM_EVENT_ON(event)) {
snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0,
hph_dly_mask, 0x0);
snd_soc_component_update_bits(comp, hph_lut_bypass_reg,
WCD934X_HPH_LUT_BYPASS_MASK,
WCD934X_HPH_LUT_BYPASS_ENABLE);
}
if (SND_SOC_DAPM_EVENT_OFF(event)) {
snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0,
hph_dly_mask, hph_dly_mask);
snd_soc_component_update_bits(comp, hph_lut_bypass_reg,
WCD934X_HPH_LUT_BYPASS_MASK,
WCD934X_HPH_LUT_BYPASS_DISABLE);
}
}
static int wcd934x_config_compander(struct snd_soc_component *comp,
int interp_n, int event)
{
struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
int compander;
u16 comp_ctl0_reg, rx_path_cfg0_reg;
/* EAR does not have compander */
if (!interp_n)
return 0;
compander = interp_n - 1;
if (!wcd->comp_enabled[compander])
return 0;
comp_ctl0_reg = WCD934X_CDC_COMPANDER1_CTL0 + (compander * 8);
rx_path_cfg0_reg = WCD934X_CDC_RX1_RX_PATH_CFG0 + (compander * 20);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* Enable Compander Clock */
snd_soc_component_update_bits(comp, comp_ctl0_reg,
WCD934X_COMP_CLK_EN_MASK,
WCD934X_COMP_CLK_ENABLE);
snd_soc_component_update_bits(comp, comp_ctl0_reg,
WCD934X_COMP_SOFT_RST_MASK,
WCD934X_COMP_SOFT_RST_ENABLE);
snd_soc_component_update_bits(comp, comp_ctl0_reg,
WCD934X_COMP_SOFT_RST_MASK,
WCD934X_COMP_SOFT_RST_DISABLE);
snd_soc_component_update_bits(comp, rx_path_cfg0_reg,
WCD934X_HPH_CMP_EN_MASK,
WCD934X_HPH_CMP_ENABLE);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(comp, rx_path_cfg0_reg,
WCD934X_HPH_CMP_EN_MASK,
WCD934X_HPH_CMP_DISABLE);
snd_soc_component_update_bits(comp, comp_ctl0_reg,
WCD934X_COMP_HALT_MASK,
WCD934X_COMP_HALT);
snd_soc_component_update_bits(comp, comp_ctl0_reg,
WCD934X_COMP_SOFT_RST_MASK,
WCD934X_COMP_SOFT_RST_ENABLE);
snd_soc_component_update_bits(comp, comp_ctl0_reg,
WCD934X_COMP_SOFT_RST_MASK,
WCD934X_COMP_SOFT_RST_DISABLE);
snd_soc_component_update_bits(comp, comp_ctl0_reg,
WCD934X_COMP_CLK_EN_MASK, 0x0);
snd_soc_component_update_bits(comp, comp_ctl0_reg,
WCD934X_COMP_SOFT_RST_MASK, 0x0);
break;
}
return 0;
}
static int wcd934x_codec_enable_interp_clk(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kc, int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
int interp_idx = w->shift;
u16 main_reg = WCD934X_CDC_RX0_RX_PATH_CTL + (interp_idx * 20);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* Clk enable */
snd_soc_component_update_bits(comp, main_reg,
WCD934X_RX_CLK_EN_MASK,
WCD934X_RX_CLK_ENABLE);
wcd934x_codec_hd2_control(comp, interp_idx, event);
wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event);
wcd934x_config_compander(comp, interp_idx, event);
break;
case SND_SOC_DAPM_POST_PMD:
wcd934x_config_compander(comp, interp_idx, event);
wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event);
wcd934x_codec_hd2_control(comp, interp_idx, event);
/* Clk Disable */
snd_soc_component_update_bits(comp, main_reg,
WCD934X_RX_CLK_EN_MASK, 0);
/* Reset enable and disable */
snd_soc_component_update_bits(comp, main_reg,
WCD934X_RX_RESET_MASK,
WCD934X_RX_RESET_ENABLE);
snd_soc_component_update_bits(comp, main_reg,
WCD934X_RX_RESET_MASK,
WCD934X_RX_RESET_DISABLE);
/* Reset rate to 48K*/
snd_soc_component_update_bits(comp, main_reg,
WCD934X_RX_PCM_RATE_MASK,
WCD934X_RX_PCM_RATE_F_48K);
break;
}
return 0;
}
static int wcd934x_codec_enable_mix_path(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kc, int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
int offset_val = 0;
u16 gain_reg, mix_reg;
int val = 0;
gain_reg = WCD934X_CDC_RX0_RX_VOL_MIX_CTL +
(w->shift * WCD934X_RX_PATH_CTL_OFFSET);
mix_reg = WCD934X_CDC_RX0_RX_PATH_MIX_CTL +
(w->shift * WCD934X_RX_PATH_CTL_OFFSET);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* Clk enable */
snd_soc_component_update_bits(comp, mix_reg,
WCD934X_CDC_RX_MIX_CLK_EN_MASK,
WCD934X_CDC_RX_MIX_CLK_ENABLE);
break;
case SND_SOC_DAPM_POST_PMU:
val = snd_soc_component_read(comp, gain_reg);
val += offset_val;
snd_soc_component_write(comp, gain_reg, val);
break;
}
return 0;
}
static int wcd934x_codec_set_iir_gain(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
int reg = w->reg;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
/* B1 GAIN */
snd_soc_component_write(comp, reg,
snd_soc_component_read(comp, reg));
/* B2 GAIN */
reg++;
snd_soc_component_write(comp, reg,
snd_soc_component_read(comp, reg));
/* B3 GAIN */
reg++;
snd_soc_component_write(comp, reg,
snd_soc_component_read(comp, reg));
/* B4 GAIN */
reg++;
snd_soc_component_write(comp, reg,
snd_soc_component_read(comp, reg));
/* B5 GAIN */
reg++;
snd_soc_component_write(comp, reg,
snd_soc_component_read(comp, reg));
break;
default:
break;
}
return 0;
}
static int wcd934x_codec_enable_main_path(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
u16 gain_reg;
gain_reg = WCD934X_CDC_RX0_RX_VOL_CTL + (w->shift *
WCD934X_RX_PATH_CTL_OFFSET);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_write(comp, gain_reg,
snd_soc_component_read(comp, gain_reg));
break;
}
return 0;
}
static int wcd934x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kc, int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* Disable AutoChop timer during power up */
snd_soc_component_update_bits(comp,
WCD934X_HPH_NEW_INT_HPH_TIMER1,
WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
break;
case SND_SOC_DAPM_POST_PMD:
wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
break;
}
return 0;
}
static int wcd934x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
int hph_mode = wcd->hph_mode;
u8 dem_inp;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* Read DEM INP Select */
dem_inp = snd_soc_component_read(comp,
WCD934X_CDC_RX1_RX_PATH_SEC0) & 0x03;
if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
(hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
return -EINVAL;
}
if (hph_mode != CLS_H_LP)
/* Ripple freq control enable */
snd_soc_component_update_bits(comp,
WCD934X_SIDO_NEW_VOUT_D_FREQ2,
WCD934X_SIDO_RIPPLE_FREQ_EN_MASK,
WCD934X_SIDO_RIPPLE_FREQ_ENABLE);
/* Disable AutoChop timer during power up */
snd_soc_component_update_bits(comp,
WCD934X_HPH_NEW_INT_HPH_TIMER1,
WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
WCD_CLSH_STATE_HPHL, hph_mode);
break;
case SND_SOC_DAPM_POST_PMD:
/* 1000us required as per HW requirement */
usleep_range(1000, 1100);
wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
WCD_CLSH_STATE_HPHL, hph_mode);
if (hph_mode != CLS_H_LP)
/* Ripple freq control disable */
snd_soc_component_update_bits(comp,
WCD934X_SIDO_NEW_VOUT_D_FREQ2,
WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0);
break;
default:
break;
}
return 0;
}
static int wcd934x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
int hph_mode = wcd->hph_mode;
u8 dem_inp;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
dem_inp = snd_soc_component_read(comp,
WCD934X_CDC_RX2_RX_PATH_SEC0) & 0x03;
if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
(hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
return -EINVAL;
}
if (hph_mode != CLS_H_LP)
/* Ripple freq control enable */
snd_soc_component_update_bits(comp,
WCD934X_SIDO_NEW_VOUT_D_FREQ2,
WCD934X_SIDO_RIPPLE_FREQ_EN_MASK,
WCD934X_SIDO_RIPPLE_FREQ_ENABLE);
/* Disable AutoChop timer during power up */
snd_soc_component_update_bits(comp,
WCD934X_HPH_NEW_INT_HPH_TIMER1,
WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
WCD_CLSH_STATE_HPHR,
hph_mode);
break;
case SND_SOC_DAPM_POST_PMD:
/* 1000us required as per HW requirement */
usleep_range(1000, 1100);
wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
WCD_CLSH_STATE_HPHR, hph_mode);
if (hph_mode != CLS_H_LP)
/* Ripple freq control disable */
snd_soc_component_update_bits(comp,
WCD934X_SIDO_NEW_VOUT_D_FREQ2,
WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0);
break;
default:
break;
}
return 0;
}
static int wcd934x_codec_lineout_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kc, int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
WCD_CLSH_STATE_LO, CLS_AB);
break;
case SND_SOC_DAPM_POST_PMD:
wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
WCD_CLSH_STATE_LO, CLS_AB);
break;
}
return 0;
}
static int wcd934x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
/*
* 7ms sleep is required after PA is enabled as per
* HW requirement. If compander is disabled, then
* 20ms delay is needed.
*/
usleep_range(20000, 20100);
snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST,
WCD934X_HPH_OCP_DET_MASK,
WCD934X_HPH_OCP_DET_ENABLE);
/* Remove Mute on primary path */
snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL,
WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
0);
/* Enable GM3 boost */
snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL,
WCD934X_HPH_GM3_BOOST_EN_MASK,
WCD934X_HPH_GM3_BOOST_ENABLE);
/* Enable AutoChop timer at the end of power up */
snd_soc_component_update_bits(comp,
WCD934X_HPH_NEW_INT_HPH_TIMER1,
WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK,
WCD934X_HPH_AUTOCHOP_TIMER_ENABLE);
/* Remove mix path mute */
snd_soc_component_update_bits(comp,
WCD934X_CDC_RX1_RX_PATH_MIX_CTL,
WCD934X_CDC_RX_PGA_MUTE_EN_MASK, 0x00);
break;
case SND_SOC_DAPM_PRE_PMD:
wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHL_PA_OFF);
/* Enable DSD Mute before PA disable */
snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST,
WCD934X_HPH_OCP_DET_MASK,
WCD934X_HPH_OCP_DET_DISABLE);
snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL,
WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
WCD934X_RX_PATH_PGA_MUTE_ENABLE);
snd_soc_component_update_bits(comp,
WCD934X_CDC_RX1_RX_PATH_MIX_CTL,
WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
WCD934X_RX_PATH_PGA_MUTE_ENABLE);
break;
case SND_SOC_DAPM_POST_PMD:
/*
* 5ms sleep is required after PA disable. If compander is
* disabled, then 20ms delay is needed after PA disable.
*/
usleep_range(20000, 20100);
wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHL_PA_OFF);
break;
}
return 0;
}
static int wcd934x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
/*
* 7ms sleep is required after PA is enabled as per
* HW requirement. If compander is disabled, then
* 20ms delay is needed.
*/
usleep_range(20000, 20100);
snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST,
WCD934X_HPH_OCP_DET_MASK,
WCD934X_HPH_OCP_DET_ENABLE);
/* Remove mute */
snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL,
WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
0);
/* Enable GM3 boost */
snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL,
WCD934X_HPH_GM3_BOOST_EN_MASK,
WCD934X_HPH_GM3_BOOST_ENABLE);
/* Enable AutoChop timer at the end of power up */
snd_soc_component_update_bits(comp,
WCD934X_HPH_NEW_INT_HPH_TIMER1,
WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK,
WCD934X_HPH_AUTOCHOP_TIMER_ENABLE);
/* Remove mix path mute if it is enabled */
if ((snd_soc_component_read(comp,
WCD934X_CDC_RX2_RX_PATH_MIX_CTL)) & 0x10)
snd_soc_component_update_bits(comp,
WCD934X_CDC_RX2_RX_PATH_MIX_CTL,
WCD934X_CDC_RX_PGA_MUTE_EN_MASK,
WCD934X_CDC_RX_PGA_MUTE_DISABLE);
break;
case SND_SOC_DAPM_PRE_PMD:
wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_PRE_HPHR_PA_OFF);
snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST,
WCD934X_HPH_OCP_DET_MASK,
WCD934X_HPH_OCP_DET_DISABLE);
snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL,
WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
WCD934X_RX_PATH_PGA_MUTE_ENABLE);
snd_soc_component_update_bits(comp,
WCD934X_CDC_RX2_RX_PATH_MIX_CTL,
WCD934X_CDC_RX_PGA_MUTE_EN_MASK,
WCD934X_CDC_RX_PGA_MUTE_ENABLE);
break;
case SND_SOC_DAPM_POST_PMD:
/*
* 5ms sleep is required after PA disable. If compander is
* disabled, then 20ms delay is needed after PA disable.
*/
usleep_range(20000, 20100);
wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHR_PA_OFF);
break;
}
return 0;
}
static u32 wcd934x_get_dmic_sample_rate(struct snd_soc_component *comp,
unsigned int dmic,
struct wcd934x_codec *wcd)
{
u8 tx_stream_fs;
u8 adc_mux_index = 0, adc_mux_sel = 0;
bool dec_found = false;
u16 adc_mux_ctl_reg, tx_fs_reg;
u32 dmic_fs;
while (!dec_found && adc_mux_index < WCD934X_MAX_VALID_ADC_MUX) {
if (adc_mux_index < 4) {
adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
(adc_mux_index * 2);
} else if (adc_mux_index < WCD934X_INVALID_ADC_MUX) {
adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
adc_mux_index - 4;
} else if (adc_mux_index == WCD934X_INVALID_ADC_MUX) {
++adc_mux_index;
continue;
}
adc_mux_sel = ((snd_soc_component_read(comp, adc_mux_ctl_reg)
& 0xF8) >> 3) - 1;
if (adc_mux_sel == dmic) {
dec_found = true;
break;
}
++adc_mux_index;
}
if (dec_found && adc_mux_index <= 8) {
tx_fs_reg = WCD934X_CDC_TX0_TX_PATH_CTL + (16 * adc_mux_index);
tx_stream_fs = snd_soc_component_read(comp, tx_fs_reg) & 0x0F;
if (tx_stream_fs <= 4)
dmic_fs = min(wcd->dmic_sample_rate, WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ);
else
dmic_fs = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ;
} else {
dmic_fs = wcd->dmic_sample_rate;
}
return dmic_fs;
}
static u8 wcd934x_get_dmic_clk_val(struct snd_soc_component *comp,
u32 mclk_rate, u32 dmic_clk_rate)
{
u32 div_factor;
u8 dmic_ctl_val;
/* Default value to return in case of error */
if (mclk_rate == WCD934X_MCLK_CLK_9P6MHZ)
dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2;
else
dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3;
if (dmic_clk_rate == 0) {
dev_err(comp->dev,
"%s: dmic_sample_rate cannot be 0\n",
__func__);
goto done;
}
div_factor = mclk_rate / dmic_clk_rate;
switch (div_factor) {
case 2:
dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2;
break;
case 3:
dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3;
break;
case 4:
dmic_ctl_val = WCD934X_DMIC_CLK_DIV_4;
break;
case 6:
dmic_ctl_val = WCD934X_DMIC_CLK_DIV_6;
break;
case 8:
dmic_ctl_val = WCD934X_DMIC_CLK_DIV_8;
break;
case 16:
dmic_ctl_val = WCD934X_DMIC_CLK_DIV_16;
break;
default:
dev_err(comp->dev,
"%s: Invalid div_factor %u, clk_rate(%u), dmic_rate(%u)\n",
__func__, div_factor, mclk_rate, dmic_clk_rate);
break;
}
done:
return dmic_ctl_val;
}
static int wcd934x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
u8 dmic_clk_en = 0x01;
u16 dmic_clk_reg;
s32 *dmic_clk_cnt;
u8 dmic_rate_val, dmic_rate_shift = 1;
unsigned int dmic;
u32 dmic_sample_rate;
int ret;
char *wname;
wname = strpbrk(w->name, "012345");
if (!wname) {
dev_err(comp->dev, "%s: widget not found\n", __func__);
return -EINVAL;
}
ret = kstrtouint(wname, 10, &dmic);
if (ret < 0) {
dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n",
__func__);
return -EINVAL;
}
switch (dmic) {
case 0:
case 1:
dmic_clk_cnt = &wcd->dmic_0_1_clk_cnt;
dmic_clk_reg = WCD934X_CPE_SS_DMIC0_CTL;
break;
case 2:
case 3:
dmic_clk_cnt = &wcd->dmic_2_3_clk_cnt;
dmic_clk_reg = WCD934X_CPE_SS_DMIC1_CTL;
break;
case 4:
case 5:
dmic_clk_cnt = &wcd->dmic_4_5_clk_cnt;
dmic_clk_reg = WCD934X_CPE_SS_DMIC2_CTL;
break;
default:
dev_err(comp->dev, "%s: Invalid DMIC Selection\n",
__func__);
return -EINVAL;
}
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
dmic_sample_rate = wcd934x_get_dmic_sample_rate(comp, dmic,
wcd);
dmic_rate_val = wcd934x_get_dmic_clk_val(comp, wcd->rate,
dmic_sample_rate);
(*dmic_clk_cnt)++;
if (*dmic_clk_cnt == 1) {
dmic_rate_val = dmic_rate_val << dmic_rate_shift;
snd_soc_component_update_bits(comp, dmic_clk_reg,
WCD934X_DMIC_RATE_MASK,
dmic_rate_val);
snd_soc_component_update_bits(comp, dmic_clk_reg,
dmic_clk_en, dmic_clk_en);
}
break;
case SND_SOC_DAPM_POST_PMD:
(*dmic_clk_cnt)--;
if (*dmic_clk_cnt == 0)
snd_soc_component_update_bits(comp, dmic_clk_reg,
dmic_clk_en, 0);
break;
}
return 0;
}
static int wcd934x_codec_find_amic_input(struct snd_soc_component *comp,
int adc_mux_n)
{
u16 mask, shift, adc_mux_in_reg;
u16 amic_mux_sel_reg;
bool is_amic;
if (adc_mux_n < 0 || adc_mux_n > WCD934X_MAX_VALID_ADC_MUX ||
adc_mux_n == WCD934X_INVALID_ADC_MUX)
return 0;
if (adc_mux_n < 3) {
adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
adc_mux_n;
mask = 0x03;
shift = 0;
amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
2 * adc_mux_n;
} else if (adc_mux_n < 4) {
adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
mask = 0x03;
shift = 0;
amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
2 * adc_mux_n;
} else if (adc_mux_n < 7) {
adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
(adc_mux_n - 4);
mask = 0x0C;
shift = 2;
amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
adc_mux_n - 4;
} else if (adc_mux_n < 8) {
adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
mask = 0x0C;
shift = 2;
amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
adc_mux_n - 4;
} else if (adc_mux_n < 12) {
adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
((adc_mux_n == 8) ? (adc_mux_n - 8) :
(adc_mux_n - 9));
mask = 0x30;
shift = 4;
amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
adc_mux_n - 4;
} else if (adc_mux_n < 13) {
adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
mask = 0x30;
shift = 4;
amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
adc_mux_n - 4;
} else {
adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1;
mask = 0xC0;
shift = 6;
amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
adc_mux_n - 4;
}
is_amic = (((snd_soc_component_read(comp, adc_mux_in_reg)
& mask) >> shift) == 1);
if (!is_amic)
return 0;
return snd_soc_component_read(comp, amic_mux_sel_reg) & 0x07;
}
static u16 wcd934x_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp,
int amic)
{
u16 pwr_level_reg = 0;
switch (amic) {
case 1:
case 2:
pwr_level_reg = WCD934X_ANA_AMIC1;
break;
case 3:
case 4:
pwr_level_reg = WCD934X_ANA_AMIC3;
break;
default:
break;
}
return pwr_level_reg;
}
static int wcd934x_codec_enable_dec(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
unsigned int decimator;
char *dec_adc_mux_name = NULL;
char *widget_name = NULL;
char *wname;
int ret = 0, amic_n;
u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg;
u16 tx_gain_ctl_reg;
char *dec;
u8 hpf_coff_freq;
widget_name = kstrndup(w->name, 15, GFP_KERNEL);
if (!widget_name)
return -ENOMEM;
wname = widget_name;
dec_adc_mux_name = strsep(&widget_name, " ");
if (!dec_adc_mux_name) {
dev_err(comp->dev, "%s: Invalid decimator = %s\n",
__func__, w->name);
ret = -EINVAL;
goto out;
}
dec_adc_mux_name = widget_name;
dec = strpbrk(dec_adc_mux_name, "012345678");
if (!dec) {
dev_err(comp->dev, "%s: decimator index not found\n",
__func__);
ret = -EINVAL;
goto out;
}
ret = kstrtouint(dec, 10, &decimator);
if (ret < 0) {
dev_err(comp->dev, "%s: Invalid decimator = %s\n",
__func__, wname);
ret = -EINVAL;
goto out;
}
tx_vol_ctl_reg = WCD934X_CDC_TX0_TX_PATH_CTL + 16 * decimator;
hpf_gate_reg = WCD934X_CDC_TX0_TX_PATH_SEC2 + 16 * decimator;
dec_cfg_reg = WCD934X_CDC_TX0_TX_PATH_CFG0 + 16 * decimator;
tx_gain_ctl_reg = WCD934X_CDC_TX0_TX_VOL_CTL + 16 * decimator;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
amic_n = wcd934x_codec_find_amic_input(comp, decimator);
if (amic_n)
pwr_level_reg = wcd934x_codec_get_amic_pwlvl_reg(comp,
amic_n);
if (!pwr_level_reg)
break;
switch ((snd_soc_component_read(comp, pwr_level_reg) &
WCD934X_AMIC_PWR_LVL_MASK) >>
WCD934X_AMIC_PWR_LVL_SHIFT) {
case WCD934X_AMIC_PWR_LEVEL_LP:
snd_soc_component_update_bits(comp, dec_cfg_reg,
WCD934X_DEC_PWR_LVL_MASK,
WCD934X_DEC_PWR_LVL_LP);
break;
case WCD934X_AMIC_PWR_LEVEL_HP:
snd_soc_component_update_bits(comp, dec_cfg_reg,
WCD934X_DEC_PWR_LVL_MASK,
WCD934X_DEC_PWR_LVL_HP);
break;
case WCD934X_AMIC_PWR_LEVEL_DEFAULT:
case WCD934X_AMIC_PWR_LEVEL_HYBRID:
default:
snd_soc_component_update_bits(comp, dec_cfg_reg,
WCD934X_DEC_PWR_LVL_MASK,
WCD934X_DEC_PWR_LVL_DF);
break;
}
break;
case SND_SOC_DAPM_POST_PMU:
hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
snd_soc_component_update_bits(comp, dec_cfg_reg,
TX_HPF_CUT_OFF_FREQ_MASK,
CF_MIN_3DB_150HZ << 5);
snd_soc_component_update_bits(comp, hpf_gate_reg,
WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ);
/*
* Minimum 1 clk cycle delay is required as per
* HW spec.
*/
usleep_range(1000, 1010);
snd_soc_component_update_bits(comp, hpf_gate_reg,
WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
0);
}
/* apply gain after decimator is enabled */
snd_soc_component_write(comp, tx_gain_ctl_reg,
snd_soc_component_read(comp,
tx_gain_ctl_reg));
break;
case SND_SOC_DAPM_PRE_PMD:
hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
snd_soc_component_update_bits(comp, dec_cfg_reg,
TX_HPF_CUT_OFF_FREQ_MASK,
hpf_coff_freq << 5);
snd_soc_component_update_bits(comp, hpf_gate_reg,
WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ);
/*
* Minimum 1 clk cycle delay is required as per
* HW spec.
*/
usleep_range(1000, 1010);
snd_soc_component_update_bits(comp, hpf_gate_reg,
WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
0);
}
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
0x10, 0x00);
snd_soc_component_update_bits(comp, dec_cfg_reg,
WCD934X_DEC_PWR_LVL_MASK,
WCD934X_DEC_PWR_LVL_DF);
break;
}
out:
kfree(wname);
return ret;
}
static void wcd934x_codec_set_tx_hold(struct snd_soc_component *comp,
u16 amic_reg, bool set)
{
u8 mask = 0x20;
u8 val;
if (amic_reg == WCD934X_ANA_AMIC1 ||
amic_reg == WCD934X_ANA_AMIC3)
mask = 0x40;
val = set ? mask : 0x00;
switch (amic_reg) {
case WCD934X_ANA_AMIC1:
case WCD934X_ANA_AMIC2:
snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC2,
mask, val);
break;
case WCD934X_ANA_AMIC3:
case WCD934X_ANA_AMIC4:
snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC4,
mask, val);
break;
default:
break;
}
}
static int wcd934x_codec_enable_adc(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
wcd934x_codec_set_tx_hold(comp, w->reg, true);
break;
default:
break;
}
return 0;
}
static int wcd934x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
int micb_num = w->shift;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
wcd934x_micbias_control(component, micb_num, MICB_ENABLE, true);
break;
case SND_SOC_DAPM_POST_PMU:
/* 1 msec delay as per HW requirement */
usleep_range(1000, 1100);
break;
case SND_SOC_DAPM_POST_PMD:
wcd934x_micbias_control(component, micb_num, MICB_DISABLE, true);
break;
}
return 0;
}
static const struct snd_soc_dapm_widget wcd934x_dapm_widgets[] = {
/* Analog Outputs */
SND_SOC_DAPM_OUTPUT("EAR"),
SND_SOC_DAPM_OUTPUT("HPHL"),
SND_SOC_DAPM_OUTPUT("HPHR"),
SND_SOC_DAPM_OUTPUT("LINEOUT1"),
SND_SOC_DAPM_OUTPUT("LINEOUT2"),
SND_SOC_DAPM_OUTPUT("SPK1 OUT"),
SND_SOC_DAPM_OUTPUT("SPK2 OUT"),
SND_SOC_DAPM_OUTPUT("ANC EAR"),
SND_SOC_DAPM_OUTPUT("ANC HPHL"),
SND_SOC_DAPM_OUTPUT("ANC HPHR"),
SND_SOC_DAPM_OUTPUT("WDMA3_OUT"),
SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT1"),
SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT2"),
SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM,
AIF1_PB, 0, wcd934x_codec_enable_slim,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM,
AIF2_PB, 0, wcd934x_codec_enable_slim,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM,
AIF3_PB, 0, wcd934x_codec_enable_slim,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM,
AIF4_PB, 0, wcd934x_codec_enable_slim,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD934X_RX0, 0,
&slim_rx_mux[WCD934X_RX0]),
SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD934X_RX1, 0,
&slim_rx_mux[WCD934X_RX1]),
SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD934X_RX2, 0,
&slim_rx_mux[WCD934X_RX2]),
SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD934X_RX3, 0,
&slim_rx_mux[WCD934X_RX3]),
SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD934X_RX4, 0,
&slim_rx_mux[WCD934X_RX4]),
SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD934X_RX5, 0,
&slim_rx_mux[WCD934X_RX5]),
SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD934X_RX6, 0,
&slim_rx_mux[WCD934X_RX6]),
SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD934X_RX7, 0,
&slim_rx_mux[WCD934X_RX7]),
SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_EAR, 0,
&rx_int0_2_mux, wcd934x_codec_enable_mix_path,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0,
&rx_int1_2_mux, wcd934x_codec_enable_mix_path,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0,
&rx_int2_2_mux, wcd934x_codec_enable_mix_path,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", SND_SOC_NOPM, INTERP_LO1, 0,
&rx_int3_2_mux, wcd934x_codec_enable_mix_path,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", SND_SOC_NOPM, INTERP_LO2, 0,
&rx_int4_2_mux, wcd934x_codec_enable_mix_path,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", SND_SOC_NOPM, INTERP_SPKR1, 0,
&rx_int7_2_mux, wcd934x_codec_enable_mix_path,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", SND_SOC_NOPM, INTERP_SPKR2, 0,
&rx_int8_2_mux, wcd934x_codec_enable_mix_path,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
&rx_int0_1_mix_inp0_mux),
SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
&rx_int0_1_mix_inp1_mux),
SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
&rx_int0_1_mix_inp2_mux),
SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
&rx_int1_1_mix_inp0_mux),
SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
&rx_int1_1_mix_inp1_mux),
SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
&rx_int1_1_mix_inp2_mux),
SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
&rx_int2_1_mix_inp0_mux),
SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
&rx_int2_1_mix_inp1_mux),
SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
&rx_int2_1_mix_inp2_mux),
SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
&rx_int3_1_mix_inp0_mux),
SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
&rx_int3_1_mix_inp1_mux),
SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
&rx_int3_1_mix_inp2_mux),
SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
&rx_int4_1_mix_inp0_mux),
SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
&rx_int4_1_mix_inp1_mux),
SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
&rx_int4_1_mix_inp2_mux),
SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
&rx_int7_1_mix_inp0_mux),
SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
&rx_int7_1_mix_inp1_mux),
SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
&rx_int7_1_mix_inp2_mux),
SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
&rx_int8_1_mix_inp0_mux),
SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
&rx_int8_1_mix_inp1_mux),
SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
&rx_int8_1_mix_inp2_mux),
SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0,
rx_int1_asrc_switch,
ARRAY_SIZE(rx_int1_asrc_switch)),
SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0,
rx_int2_asrc_switch,
ARRAY_SIZE(rx_int2_asrc_switch)),
SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0,
rx_int3_asrc_switch,
ARRAY_SIZE(rx_int3_asrc_switch)),
SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0,
rx_int4_asrc_switch,
ARRAY_SIZE(rx_int4_asrc_switch)),
SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT1 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT2 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT3 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT4 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER_E("RX INT7 CHAIN", SND_SOC_NOPM, 0, 0,
NULL, 0, NULL, 0),
SND_SOC_DAPM_MIXER_E("RX INT8 CHAIN", SND_SOC_NOPM, 0, 0,
NULL, 0, NULL, 0),
SND_SOC_DAPM_MUX_E("RX INT0 MIX2 INP", WCD934X_CDC_RX0_RX_PATH_CFG0, 4,
0, &rx_int0_mix2_inp_mux, NULL,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("RX INT1 MIX2 INP", WCD934X_CDC_RX1_RX_PATH_CFG0, 4,
0, &rx_int1_mix2_inp_mux, NULL,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("RX INT2 MIX2 INP", WCD934X_CDC_RX2_RX_PATH_CFG0, 4,
0, &rx_int2_mix2_inp_mux, NULL,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("RX INT3 MIX2 INP", WCD934X_CDC_RX3_RX_PATH_CFG0, 4,
0, &rx_int3_mix2_inp_mux, NULL,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("RX INT4 MIX2 INP", WCD934X_CDC_RX4_RX_PATH_CFG0, 4,
0, &rx_int4_mix2_inp_mux, NULL,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("RX INT7 MIX2 INP", WCD934X_CDC_RX7_RX_PATH_CFG0, 4,
0, &rx_int7_mix2_inp_mux, NULL,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("IIR0 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp0_mux),
SND_SOC_DAPM_MUX("IIR0 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp1_mux),
SND_SOC_DAPM_MUX("IIR0 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp2_mux),
SND_SOC_DAPM_MUX("IIR0 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp3_mux),
SND_SOC_DAPM_MUX("IIR1 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp0_mux),
SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux),
SND_SOC_DAPM_MUX("IIR1 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp2_mux),
SND_SOC_DAPM_MUX("IIR1 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp3_mux),
SND_SOC_DAPM_PGA_E("IIR0", WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL,
0, 0, NULL, 0, wcd934x_codec_set_iir_gain,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IIR1", WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL,
1, 0, NULL, 0, wcd934x_codec_set_iir_gain,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_MIXER("SRC0", WCD934X_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL,
4, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SRC1", WCD934X_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL,
4, 0, NULL, 0),
SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
&rx_int0_dem_inp_mux),
SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
&rx_int1_dem_inp_mux),
SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0,
&rx_int2_dem_inp_mux),
SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_EAR, 0,
&rx_int0_1_interp_mux,
wcd934x_codec_enable_main_path,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0,
&rx_int1_1_interp_mux,
wcd934x_codec_enable_main_path,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0,
&rx_int2_1_interp_mux,
wcd934x_codec_enable_main_path,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("RX INT3_1 INTERP", SND_SOC_NOPM, INTERP_LO1, 0,
&rx_int3_1_interp_mux,
wcd934x_codec_enable_main_path,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("RX INT4_1 INTERP", SND_SOC_NOPM, INTERP_LO2, 0,
&rx_int4_1_interp_mux,
wcd934x_codec_enable_main_path,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("RX INT7_1 INTERP", SND_SOC_NOPM, INTERP_SPKR1, 0,
&rx_int7_1_interp_mux,
wcd934x_codec_enable_main_path,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("RX INT8_1 INTERP", SND_SOC_NOPM, INTERP_SPKR2, 0,
&rx_int8_1_interp_mux,
wcd934x_codec_enable_main_path,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("RX INT0_2 INTERP", SND_SOC_NOPM, 0, 0,
&rx_int0_2_interp_mux),
SND_SOC_DAPM_MUX("RX INT1_2 INTERP", SND_SOC_NOPM, 0, 0,
&rx_int1_2_interp_mux),
SND_SOC_DAPM_MUX("RX INT2_2 INTERP", SND_SOC_NOPM, 0, 0,
&rx_int2_2_interp_mux),
SND_SOC_DAPM_MUX("RX INT3_2 INTERP", SND_SOC_NOPM, 0, 0,
&rx_int3_2_interp_mux),
SND_SOC_DAPM_MUX("RX INT4_2 INTERP", SND_SOC_NOPM, 0, 0,
&rx_int4_2_interp_mux),
SND_SOC_DAPM_MUX("RX INT7_2 INTERP", SND_SOC_NOPM, 0, 0,
&rx_int7_2_interp_mux),
SND_SOC_DAPM_MUX("RX INT8_2 INTERP", SND_SOC_NOPM, 0, 0,
&rx_int8_2_interp_mux),
SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM,
0, 0, wcd934x_codec_ear_dac_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD934X_ANA_HPH,
5, 0, wcd934x_codec_hphl_dac_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD934X_ANA_HPH,
4, 0, wcd934x_codec_hphr_dac_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM,
0, 0, wcd934x_codec_lineout_dac_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM,
0, 0, wcd934x_codec_lineout_dac_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("EAR PA", WCD934X_ANA_EAR, 7, 0, NULL, 0, NULL, 0),
SND_SOC_DAPM_PGA_E("HPHL PA", WCD934X_ANA_HPH, 7, 0, NULL, 0,
wcd934x_codec_enable_hphl_pa,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("HPHR PA", WCD934X_ANA_HPH, 6, 0, NULL, 0,
wcd934x_codec_enable_hphr_pa,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD934X_ANA_LO_1_2, 7, 0, NULL, 0,
NULL, 0),
SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD934X_ANA_LO_1_2, 6, 0, NULL, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("RX_BIAS", WCD934X_ANA_RX_SUPPLIES, 0, 0, NULL,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("SBOOST0", WCD934X_CDC_RX7_RX_PATH_CFG1,
0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("SBOOST0_CLK", WCD934X_CDC_BOOST0_BOOST_PATH_CTL,
0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("SBOOST1", WCD934X_CDC_RX8_RX_PATH_CFG1,
0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("SBOOST1_CLK", WCD934X_CDC_BOOST1_BOOST_PATH_CTL,
0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("INT0_CLK", SND_SOC_NOPM, INTERP_EAR, 0,
wcd934x_codec_enable_interp_clk,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("INT1_CLK", SND_SOC_NOPM, INTERP_HPHL, 0,
wcd934x_codec_enable_interp_clk,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("INT2_CLK", SND_SOC_NOPM, INTERP_HPHR, 0,
wcd934x_codec_enable_interp_clk,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("INT3_CLK", SND_SOC_NOPM, INTERP_LO1, 0,
wcd934x_codec_enable_interp_clk,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("INT4_CLK", SND_SOC_NOPM, INTERP_LO2, 0,
wcd934x_codec_enable_interp_clk,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("INT7_CLK", SND_SOC_NOPM, INTERP_SPKR1, 0,
wcd934x_codec_enable_interp_clk,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("INT8_CLK", SND_SOC_NOPM, INTERP_SPKR2, 0,
wcd934x_codec_enable_interp_clk,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("DSMDEM0_CLK", WCD934X_CDC_RX0_RX_PATH_DSMDEM_CTL,
0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DSMDEM1_CLK", WCD934X_CDC_RX1_RX_PATH_DSMDEM_CTL,
0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DSMDEM2_CLK", WCD934X_CDC_RX2_RX_PATH_DSMDEM_CTL,
0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DSMDEM3_CLK", WCD934X_CDC_RX3_RX_PATH_DSMDEM_CTL,
0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DSMDEM4_CLK", WCD934X_CDC_RX4_RX_PATH_DSMDEM_CTL,
0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DSMDEM7_CLK", WCD934X_CDC_RX7_RX_PATH_DSMDEM_CTL,
0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DSMDEM8_CLK", WCD934X_CDC_RX8_RX_PATH_DSMDEM_CTL,
0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
wcd934x_codec_enable_mclk,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
/* TX */
SND_SOC_DAPM_INPUT("AMIC1"),
SND_SOC_DAPM_INPUT("AMIC2"),
SND_SOC_DAPM_INPUT("AMIC3"),
SND_SOC_DAPM_INPUT("AMIC4"),
SND_SOC_DAPM_INPUT("AMIC5"),
SND_SOC_DAPM_INPUT("DMIC0 Pin"),
SND_SOC_DAPM_INPUT("DMIC1 Pin"),
SND_SOC_DAPM_INPUT("DMIC2 Pin"),
SND_SOC_DAPM_INPUT("DMIC3 Pin"),
SND_SOC_DAPM_INPUT("DMIC4 Pin"),
SND_SOC_DAPM_INPUT("DMIC5 Pin"),
SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM,
AIF1_CAP, 0, wcd934x_codec_enable_slim,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM,
AIF2_CAP, 0, wcd934x_codec_enable_slim,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM,
AIF3_CAP, 0, wcd934x_codec_enable_slim,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER("SLIM TX0", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SLIM TX1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SLIM TX2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SLIM TX3", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SLIM TX4", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SLIM TX5", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SLIM TX6", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SLIM TX7", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SLIM TX8", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SLIM TX9", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SLIM TX10", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SLIM TX11", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SLIM TX13", SND_SOC_NOPM, 0, 0, NULL, 0),
/* Digital Mic Inputs */
SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0,
wcd934x_codec_enable_dmic,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
wcd934x_codec_enable_dmic,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
wcd934x_codec_enable_dmic,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0,
wcd934x_codec_enable_dmic,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0,
wcd934x_codec_enable_dmic,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0,
wcd934x_codec_enable_dmic,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_dmic_mux0),
SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_dmic_mux1),
SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_dmic_mux2),
SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_dmic_mux3),
SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_dmic_mux4),
SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_dmic_mux5),
SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_dmic_mux6),
SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_dmic_mux7),
SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_dmic_mux8),
SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_amic_mux0),
SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_amic_mux1),
SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_amic_mux2),
SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_amic_mux3),
SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_amic_mux4),
SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_amic_mux5),
SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_amic_mux6),
SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_amic_mux7),
SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_amic_mux8),
SND_SOC_DAPM_MUX_E("ADC MUX0", WCD934X_CDC_TX0_TX_PATH_CTL, 5, 0,
&tx_adc_mux0_mux, wcd934x_codec_enable_dec,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("ADC MUX1", WCD934X_CDC_TX1_TX_PATH_CTL, 5, 0,
&tx_adc_mux1_mux, wcd934x_codec_enable_dec,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("ADC MUX2", WCD934X_CDC_TX2_TX_PATH_CTL, 5, 0,
&tx_adc_mux2_mux, wcd934x_codec_enable_dec,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("ADC MUX3", WCD934X_CDC_TX3_TX_PATH_CTL, 5, 0,
&tx_adc_mux3_mux, wcd934x_codec_enable_dec,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("ADC MUX4", WCD934X_CDC_TX4_TX_PATH_CTL, 5, 0,
&tx_adc_mux4_mux, wcd934x_codec_enable_dec,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("ADC MUX5", WCD934X_CDC_TX5_TX_PATH_CTL, 5, 0,
&tx_adc_mux5_mux, wcd934x_codec_enable_dec,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("ADC MUX6", WCD934X_CDC_TX6_TX_PATH_CTL, 5, 0,
&tx_adc_mux6_mux, wcd934x_codec_enable_dec,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("ADC MUX7", WCD934X_CDC_TX7_TX_PATH_CTL, 5, 0,
&tx_adc_mux7_mux, wcd934x_codec_enable_dec,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("ADC MUX8", WCD934X_CDC_TX8_TX_PATH_CTL, 5, 0,
&tx_adc_mux8_mux, wcd934x_codec_enable_dec,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD934X_ANA_AMIC1, 7, 0,
wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD934X_ANA_AMIC2, 7, 0,
wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD934X_ANA_AMIC3, 7, 0,
wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD934X_ANA_AMIC4, 7, 0,
wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0,
wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0,
wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0,
wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0,
wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("AMIC4_5 SEL", SND_SOC_NOPM, 0, 0, &tx_amic4_5),
SND_SOC_DAPM_MUX("CDC_IF TX0 MUX", SND_SOC_NOPM, WCD934X_TX0, 0,
&cdc_if_tx0_mux),
SND_SOC_DAPM_MUX("CDC_IF TX1 MUX", SND_SOC_NOPM, WCD934X_TX1, 0,
&cdc_if_tx1_mux),
SND_SOC_DAPM_MUX("CDC_IF TX2 MUX", SND_SOC_NOPM, WCD934X_TX2, 0,
&cdc_if_tx2_mux),
SND_SOC_DAPM_MUX("CDC_IF TX3 MUX", SND_SOC_NOPM, WCD934X_TX3, 0,
&cdc_if_tx3_mux),
SND_SOC_DAPM_MUX("CDC_IF TX4 MUX", SND_SOC_NOPM, WCD934X_TX4, 0,
&cdc_if_tx4_mux),
SND_SOC_DAPM_MUX("CDC_IF TX5 MUX", SND_SOC_NOPM, WCD934X_TX5, 0,
&cdc_if_tx5_mux),
SND_SOC_DAPM_MUX("CDC_IF TX6 MUX", SND_SOC_NOPM, WCD934X_TX6, 0,
&cdc_if_tx6_mux),
SND_SOC_DAPM_MUX("CDC_IF TX7 MUX", SND_SOC_NOPM, WCD934X_TX7, 0,
&cdc_if_tx7_mux),
SND_SOC_DAPM_MUX("CDC_IF TX8 MUX", SND_SOC_NOPM, WCD934X_TX8, 0,
&cdc_if_tx8_mux),
SND_SOC_DAPM_MUX("CDC_IF TX9 MUX", SND_SOC_NOPM, WCD934X_TX9, 0,
&cdc_if_tx9_mux),
SND_SOC_DAPM_MUX("CDC_IF TX10 MUX", SND_SOC_NOPM, WCD934X_TX10, 0,
&cdc_if_tx10_mux),
SND_SOC_DAPM_MUX("CDC_IF TX11 MUX", SND_SOC_NOPM, WCD934X_TX11, 0,
&cdc_if_tx11_mux),
SND_SOC_DAPM_MUX("CDC_IF TX11 INP1 MUX", SND_SOC_NOPM, WCD934X_TX11, 0,
&cdc_if_tx11_inp1_mux),
SND_SOC_DAPM_MUX("CDC_IF TX13 MUX", SND_SOC_NOPM, WCD934X_TX13, 0,
&cdc_if_tx13_mux),
SND_SOC_DAPM_MUX("CDC_IF TX13 INP1 MUX", SND_SOC_NOPM, WCD934X_TX13, 0,
&cdc_if_tx13_inp1_mux),
SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0,
aif1_slim_cap_mixer,
ARRAY_SIZE(aif1_slim_cap_mixer)),
SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0,
aif2_slim_cap_mixer,
ARRAY_SIZE(aif2_slim_cap_mixer)),
SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0,
aif3_slim_cap_mixer,
ARRAY_SIZE(aif3_slim_cap_mixer)),
};
static const struct snd_soc_dapm_route wcd934x_audio_map[] = {
/* RX0-RX7 */
WCD934X_SLIM_RX_AIF_PATH(0),
WCD934X_SLIM_RX_AIF_PATH(1),
WCD934X_SLIM_RX_AIF_PATH(2),
WCD934X_SLIM_RX_AIF_PATH(3),
WCD934X_SLIM_RX_AIF_PATH(4),
WCD934X_SLIM_RX_AIF_PATH(5),
WCD934X_SLIM_RX_AIF_PATH(6),
WCD934X_SLIM_RX_AIF_PATH(7),
/* RX0 Ear out */
WCD934X_INTERPOLATOR_PATH(0),
WCD934X_INTERPOLATOR_MIX2(0),
{"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"},
{"RX INT0 DAC", NULL, "RX INT0 DEM MUX"},
{"RX INT0 DAC", NULL, "RX_BIAS"},
{"EAR PA", NULL, "RX INT0 DAC"},
{"EAR", NULL, "EAR PA"},
/* RX1 Headphone left */
WCD934X_INTERPOLATOR_PATH(1),
WCD934X_INTERPOLATOR_MIX2(1),
{"RX INT1 MIX3", NULL, "RX INT1 MIX2"},
{"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX3"},
{"RX INT1 DAC", NULL, "RX INT1 DEM MUX"},
{"RX INT1 DAC", NULL, "RX_BIAS"},
{"HPHL PA", NULL, "RX INT1 DAC"},
{"HPHL", NULL, "HPHL PA"},
/* RX2 Headphone right */
WCD934X_INTERPOLATOR_PATH(2),
WCD934X_INTERPOLATOR_MIX2(2),
{"RX INT2 MIX3", NULL, "RX INT2 MIX2"},
{"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 MIX3"},
{"RX INT2 DAC", NULL, "RX INT2 DEM MUX"},
{"RX INT2 DAC", NULL, "RX_BIAS"},
{"HPHR PA", NULL, "RX INT2 DAC"},
{"HPHR", NULL, "HPHR PA"},
/* RX3 HIFi LineOut1 */
WCD934X_INTERPOLATOR_PATH(3),
WCD934X_INTERPOLATOR_MIX2(3),
{"RX INT3 MIX3", NULL, "RX INT3 MIX2"},
{"RX INT3 DAC", NULL, "RX INT3 MIX3"},
{"RX INT3 DAC", NULL, "RX_BIAS"},
{"LINEOUT1 PA", NULL, "RX INT3 DAC"},
{"LINEOUT1", NULL, "LINEOUT1 PA"},
/* RX4 HIFi LineOut2 */
WCD934X_INTERPOLATOR_PATH(4),
WCD934X_INTERPOLATOR_MIX2(4),
{"RX INT4 MIX3", NULL, "RX INT4 MIX2"},
{"RX INT4 DAC", NULL, "RX INT4 MIX3"},
{"RX INT4 DAC", NULL, "RX_BIAS"},
{"LINEOUT2 PA", NULL, "RX INT4 DAC"},
{"LINEOUT2", NULL, "LINEOUT2 PA"},
/* RX7 Speaker Left Out PA */
WCD934X_INTERPOLATOR_PATH(7),
WCD934X_INTERPOLATOR_MIX2(7),
{"RX INT7 CHAIN", NULL, "RX INT7 MIX2"},
{"RX INT7 CHAIN", NULL, "RX_BIAS"},
{"RX INT7 CHAIN", NULL, "SBOOST0"},
{"RX INT7 CHAIN", NULL, "SBOOST0_CLK"},
{"SPK1 OUT", NULL, "RX INT7 CHAIN"},
/* RX8 Speaker Right Out PA */
WCD934X_INTERPOLATOR_PATH(8),
{"RX INT8 CHAIN", NULL, "RX INT8 SEC MIX"},
{"RX INT8 CHAIN", NULL, "RX_BIAS"},
{"RX INT8 CHAIN", NULL, "SBOOST1"},
{"RX INT8 CHAIN", NULL, "SBOOST1_CLK"},
{"SPK2 OUT", NULL, "RX INT8 CHAIN"},
/* Tx */
{"AIF1 CAP", NULL, "AIF1_CAP Mixer"},
{"AIF2 CAP", NULL, "AIF2_CAP Mixer"},
{"AIF3 CAP", NULL, "AIF3_CAP Mixer"},
WCD934X_SLIM_TX_AIF_PATH(0),
WCD934X_SLIM_TX_AIF_PATH(1),
WCD934X_SLIM_TX_AIF_PATH(2),
WCD934X_SLIM_TX_AIF_PATH(3),
WCD934X_SLIM_TX_AIF_PATH(4),
WCD934X_SLIM_TX_AIF_PATH(5),
WCD934X_SLIM_TX_AIF_PATH(6),
WCD934X_SLIM_TX_AIF_PATH(7),
WCD934X_SLIM_TX_AIF_PATH(8),
WCD934X_ADC_MUX(0),
WCD934X_ADC_MUX(1),
WCD934X_ADC_MUX(2),
WCD934X_ADC_MUX(3),
WCD934X_ADC_MUX(4),
WCD934X_ADC_MUX(5),
WCD934X_ADC_MUX(6),
WCD934X_ADC_MUX(7),
WCD934X_ADC_MUX(8),
{"CDC_IF TX0 MUX", "DEC0", "ADC MUX0"},
{"CDC_IF TX1 MUX", "DEC1", "ADC MUX1"},
{"CDC_IF TX2 MUX", "DEC2", "ADC MUX2"},
{"CDC_IF TX3 MUX", "DEC3", "ADC MUX3"},
{"CDC_IF TX4 MUX", "DEC4", "ADC MUX4"},
{"CDC_IF TX5 MUX", "DEC5", "ADC MUX5"},
{"CDC_IF TX6 MUX", "DEC6", "ADC MUX6"},
{"CDC_IF TX7 MUX", "DEC7", "ADC MUX7"},
{"CDC_IF TX8 MUX", "DEC8", "ADC MUX8"},
{"AMIC4_5 SEL", "AMIC4", "AMIC4"},
{"AMIC4_5 SEL", "AMIC5", "AMIC5"},
{ "DMIC0", NULL, "DMIC0 Pin" },
{ "DMIC1", NULL, "DMIC1 Pin" },
{ "DMIC2", NULL, "DMIC2 Pin" },
{ "DMIC3", NULL, "DMIC3 Pin" },
{ "DMIC4", NULL, "DMIC4 Pin" },
{ "DMIC5", NULL, "DMIC5 Pin" },
{"ADC1", NULL, "AMIC1"},
{"ADC2", NULL, "AMIC2"},
{"ADC3", NULL, "AMIC3"},
{"ADC4", NULL, "AMIC4_5 SEL"},
WCD934X_IIR_INP_MUX(0),
WCD934X_IIR_INP_MUX(1),
{"SRC0", NULL, "IIR0"},
{"SRC1", NULL, "IIR1"},
};
static int wcd934x_codec_set_jack(struct snd_soc_component *comp,
struct snd_soc_jack *jack, void *data)
{
struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
int ret = 0;
if (!wcd->mbhc)
return -ENOTSUPP;
if (jack && !wcd->mbhc_started) {
ret = wcd_mbhc_start(wcd->mbhc, &wcd->mbhc_cfg, jack);
wcd->mbhc_started = true;
} else if (wcd->mbhc_started) {
wcd_mbhc_stop(wcd->mbhc);
wcd->mbhc_started = false;
}
return ret;
}
static const struct snd_soc_component_driver wcd934x_component_drv = {
.probe = wcd934x_comp_probe,
.remove = wcd934x_comp_remove,
.set_sysclk = wcd934x_comp_set_sysclk,
.controls = wcd934x_snd_controls,
.num_controls = ARRAY_SIZE(wcd934x_snd_controls),
.dapm_widgets = wcd934x_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wcd934x_dapm_widgets),
.dapm_routes = wcd934x_audio_map,
.num_dapm_routes = ARRAY_SIZE(wcd934x_audio_map),
.set_jack = wcd934x_codec_set_jack,
.endianness = 1,
};
static int wcd934x_codec_parse_data(struct wcd934x_codec *wcd)
{
struct device *dev = &wcd->sdev->dev;
struct wcd_mbhc_config *cfg = &wcd->mbhc_cfg;
struct device_node *ifc_dev_np;
ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0);
if (!ifc_dev_np) {
dev_err(dev, "No Interface device found\n");
return -EINVAL;
}
wcd->sidev = of_slim_get_device(wcd->sdev->ctrl, ifc_dev_np);
of_node_put(ifc_dev_np);
if (!wcd->sidev) {
dev_err(dev, "Unable to get SLIM Interface device\n");
return -EINVAL;
}
slim_get_logical_addr(wcd->sidev);
wcd->if_regmap = regmap_init_slimbus(wcd->sidev,
&wcd934x_ifc_regmap_config);
if (IS_ERR(wcd->if_regmap))
return dev_err_probe(dev, PTR_ERR(wcd->if_regmap),
"Failed to allocate ifc register map\n");
of_property_read_u32(dev->parent->of_node, "qcom,dmic-sample-rate",
&wcd->dmic_sample_rate);
cfg->mbhc_micbias = MIC_BIAS_2;
cfg->anc_micbias = MIC_BIAS_2;
cfg->v_hs_max = WCD_MBHC_HS_V_MAX;
cfg->num_btn = WCD934X_MBHC_MAX_BUTTONS;
cfg->micb_mv = wcd->micb2_mv;
cfg->linein_th = 5000;
cfg->hs_thr = 1700;
cfg->hph_thr = 50;
wcd_dt_parse_mbhc_data(dev, cfg);
return 0;
}
static int wcd934x_codec_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct wcd934x_ddata *data = dev_get_drvdata(dev->parent);
struct wcd934x_codec *wcd;
int ret, irq;
wcd = devm_kzalloc(dev, sizeof(*wcd), GFP_KERNEL);
if (!wcd)
return -ENOMEM;
wcd->dev = dev;
wcd->regmap = data->regmap;
wcd->extclk = data->extclk;
wcd->sdev = to_slim_device(data->dev);
mutex_init(&wcd->sysclk_mutex);
mutex_init(&wcd->micb_lock);
ret = wcd934x_codec_parse_data(wcd);
if (ret) {
dev_err(wcd->dev, "Failed to get SLIM IRQ\n");
return ret;
}
/* set default rate 9P6MHz */
regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_MCLK_CFG,
WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
memcpy(wcd->rx_chs, wcd934x_rx_chs, sizeof(wcd934x_rx_chs));
memcpy(wcd->tx_chs, wcd934x_tx_chs, sizeof(wcd934x_tx_chs));
irq = regmap_irq_get_virq(data->irq_data, WCD934X_IRQ_SLIMBUS);
if (irq < 0)
return dev_err_probe(wcd->dev, irq, "Failed to get SLIM IRQ\n");
ret = devm_request_threaded_irq(dev, irq, NULL,
wcd934x_slim_irq_handler,
IRQF_TRIGGER_RISING | IRQF_ONESHOT,
"slim", wcd);
if (ret)
return dev_err_probe(dev, ret, "Failed to request slimbus irq\n");
wcd934x_register_mclk_output(wcd);
platform_set_drvdata(pdev, wcd);
return devm_snd_soc_register_component(dev, &wcd934x_component_drv,
wcd934x_slim_dais,
ARRAY_SIZE(wcd934x_slim_dais));
}
static const struct platform_device_id wcd934x_driver_id[] = {
{
.name = "wcd934x-codec",
},
{},
};
MODULE_DEVICE_TABLE(platform, wcd934x_driver_id);
static struct platform_driver wcd934x_codec_driver = {
.probe = &wcd934x_codec_probe,
.id_table = wcd934x_driver_id,
.driver = {
.name = "wcd934x-codec",
}
};
MODULE_ALIAS("platform:wcd934x-codec");
module_platform_driver(wcd934x_codec_driver);
MODULE_DESCRIPTION("WCD934x codec driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/wcd934x.c |
// SPDX-License-Identifier: GPL-2.0
//
// CS42L43 CODEC driver
//
// Copyright (C) 2022-2023 Cirrus Logic, Inc. and
// Cirrus Logic International Semiconductor Ltd.
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/gcd.h>
#include <linux/irq.h>
#include <linux/jiffies.h>
#include <linux/mfd/cs42l43.h>
#include <linux/mfd/cs42l43-regs.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/string.h>
#include <sound/control.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc-component.h>
#include <sound/soc-dapm.h>
#include <sound/soc-dai.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include "cs42l43.h"
#define CS42L43_DECL_MUX(name, reg) \
static SOC_VALUE_ENUM_SINGLE_DECL(cs42l43_##name##_enum, reg, \
0, CS42L43_MIXER_SRC_MASK, \
cs42l43_mixer_texts, cs42l43_mixer_values); \
static const struct snd_kcontrol_new cs42l43_##name##_mux = \
SOC_DAPM_ENUM("Route", cs42l43_##name##_enum)
#define CS42L43_DECL_MIXER(name, reg) \
CS42L43_DECL_MUX(name##_in1, reg); \
CS42L43_DECL_MUX(name##_in2, reg + 0x4); \
CS42L43_DECL_MUX(name##_in3, reg + 0x8); \
CS42L43_DECL_MUX(name##_in4, reg + 0xC)
#define CS42L43_DAPM_MUX(name_str, name) \
SND_SOC_DAPM_MUX(name_str " Input", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_mux)
#define CS42L43_DAPM_MIXER(name_str, name) \
SND_SOC_DAPM_MUX(name_str " Input 1", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in1_mux), \
SND_SOC_DAPM_MUX(name_str " Input 2", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in2_mux), \
SND_SOC_DAPM_MUX(name_str " Input 3", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in3_mux), \
SND_SOC_DAPM_MUX(name_str " Input 4", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in4_mux), \
SND_SOC_DAPM_MIXER(name_str " Mixer", SND_SOC_NOPM, 0, 0, NULL, 0)
#define CS42L43_BASE_ROUTES(name_str) \
{ name_str, "Tone Generator 1", "Tone 1" }, \
{ name_str, "Tone Generator 2", "Tone 2" }, \
{ name_str, "Decimator 1", "Decimator 1" }, \
{ name_str, "Decimator 2", "Decimator 2" }, \
{ name_str, "Decimator 3", "Decimator 3" }, \
{ name_str, "Decimator 4", "Decimator 4" }, \
{ name_str, "ASPRX1", "ASPRX1" }, \
{ name_str, "ASPRX2", "ASPRX2" }, \
{ name_str, "ASPRX3", "ASPRX3" }, \
{ name_str, "ASPRX4", "ASPRX4" }, \
{ name_str, "ASPRX5", "ASPRX5" }, \
{ name_str, "ASPRX6", "ASPRX6" }, \
{ name_str, "DP5RX1", "DP5RX1" }, \
{ name_str, "DP5RX2", "DP5RX2" }, \
{ name_str, "DP6RX1", "DP6RX1" }, \
{ name_str, "DP6RX2", "DP6RX2" }, \
{ name_str, "DP7RX1", "DP7RX1" }, \
{ name_str, "DP7RX2", "DP7RX2" }, \
{ name_str, "ASRC INT1", "ASRC_INT1" }, \
{ name_str, "ASRC INT2", "ASRC_INT2" }, \
{ name_str, "ASRC INT3", "ASRC_INT3" }, \
{ name_str, "ASRC INT4", "ASRC_INT4" }, \
{ name_str, "ASRC DEC1", "ASRC_DEC1" }, \
{ name_str, "ASRC DEC2", "ASRC_DEC2" }, \
{ name_str, "ASRC DEC3", "ASRC_DEC3" }, \
{ name_str, "ASRC DEC4", "ASRC_DEC4" }, \
{ name_str, "ISRC1 INT1", "ISRC1INT1" }, \
{ name_str, "ISRC1 INT2", "ISRC1INT2" }, \
{ name_str, "ISRC1 DEC1", "ISRC1DEC1" }, \
{ name_str, "ISRC1 DEC2", "ISRC1DEC2" }, \
{ name_str, "ISRC2 INT1", "ISRC2INT1" }, \
{ name_str, "ISRC2 INT2", "ISRC2INT2" }, \
{ name_str, "ISRC2 DEC1", "ISRC2DEC1" }, \
{ name_str, "ISRC2 DEC2", "ISRC2DEC2" }, \
{ name_str, "EQ1", "EQ" }, \
{ name_str, "EQ2", "EQ" }
#define CS42L43_MUX_ROUTES(name_str, widget) \
{ widget, NULL, name_str " Input" }, \
{ name_str " Input", NULL, "Mixer Core" }, \
CS42L43_BASE_ROUTES(name_str " Input")
#define CS42L43_MIXER_ROUTES(name_str, widget) \
{ name_str " Mixer", NULL, name_str " Input 1" }, \
{ name_str " Mixer", NULL, name_str " Input 2" }, \
{ name_str " Mixer", NULL, name_str " Input 3" }, \
{ name_str " Mixer", NULL, name_str " Input 4" }, \
{ widget, NULL, name_str " Mixer" }, \
{ name_str " Mixer", NULL, "Mixer Core" }, \
CS42L43_BASE_ROUTES(name_str " Input 1"), \
CS42L43_BASE_ROUTES(name_str " Input 2"), \
CS42L43_BASE_ROUTES(name_str " Input 3"), \
CS42L43_BASE_ROUTES(name_str " Input 4")
#define CS42L43_MIXER_VOLUMES(name_str, base) \
SOC_SINGLE_RANGE_TLV(name_str " Input 1 Volume", base, \
CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \
cs42l43_mixer_tlv), \
SOC_SINGLE_RANGE_TLV(name_str " Input 2 Volume", base + 4, \
CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \
cs42l43_mixer_tlv), \
SOC_SINGLE_RANGE_TLV(name_str " Input 3 Volume", base + 8, \
CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \
cs42l43_mixer_tlv), \
SOC_SINGLE_RANGE_TLV(name_str " Input 4 Volume", base + 12, \
CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \
cs42l43_mixer_tlv)
#define CS42L43_IRQ_ERROR(name) \
static irqreturn_t cs42l43_##name(int irq, void *data) \
{ \
struct cs42l43_codec *priv = data; \
dev_err(priv->dev, "Error " #name " IRQ\n"); \
return IRQ_HANDLED; \
}
CS42L43_IRQ_ERROR(pll_lost_lock)
CS42L43_IRQ_ERROR(spkr_clock_stop)
CS42L43_IRQ_ERROR(spkl_clock_stop)
CS42L43_IRQ_ERROR(spkr_brown_out)
CS42L43_IRQ_ERROR(spkl_brown_out)
CS42L43_IRQ_ERROR(spkr_therm_shutdown)
CS42L43_IRQ_ERROR(spkl_therm_shutdown)
CS42L43_IRQ_ERROR(spkr_therm_warm)
CS42L43_IRQ_ERROR(spkl_therm_warm)
CS42L43_IRQ_ERROR(spkr_sc_detect)
CS42L43_IRQ_ERROR(spkl_sc_detect)
CS42L43_IRQ_ERROR(hp_ilimit)
#define CS42L43_IRQ_COMPLETE(name) \
static irqreturn_t cs42l43_##name(int irq, void *data) \
{ \
struct cs42l43_codec *priv = data; \
dev_dbg(priv->dev, #name " completed\n"); \
complete(&priv->name); \
return IRQ_HANDLED; \
}
CS42L43_IRQ_COMPLETE(pll_ready)
CS42L43_IRQ_COMPLETE(hp_startup)
CS42L43_IRQ_COMPLETE(hp_shutdown)
CS42L43_IRQ_COMPLETE(type_detect)
CS42L43_IRQ_COMPLETE(spkr_shutdown)
CS42L43_IRQ_COMPLETE(spkl_shutdown)
CS42L43_IRQ_COMPLETE(spkr_startup)
CS42L43_IRQ_COMPLETE(spkl_startup)
CS42L43_IRQ_COMPLETE(load_detect)
static irqreturn_t cs42l43_mic_shutter(int irq, void *data)
{
struct cs42l43_codec *priv = data;
const char * const controls[] = {
"Decimator 1 Switch",
"Decimator 2 Switch",
"Decimator 3 Switch",
"Decimator 4 Switch",
};
int i, ret;
dev_dbg(priv->dev, "Microphone shutter changed\n");
if (!priv->component)
return IRQ_NONE;
for (i = 0; i < ARRAY_SIZE(controls); i++) {
ret = snd_soc_component_notify_control(priv->component,
controls[i]);
if (ret)
return IRQ_NONE;
}
return IRQ_HANDLED;
}
static irqreturn_t cs42l43_spk_shutter(int irq, void *data)
{
struct cs42l43_codec *priv = data;
int ret;
dev_dbg(priv->dev, "Speaker shutter changed\n");
if (!priv->component)
return IRQ_NONE;
ret = snd_soc_component_notify_control(priv->component,
"Speaker Digital Switch");
if (ret)
return IRQ_NONE;
return IRQ_HANDLED;
}
static const unsigned int cs42l43_sample_rates[] = {
8000, 16000, 24000, 32000, 44100, 48000, 96000, 192000,
};
#define CS42L43_CONSUMER_RATE_MASK 0xFF
#define CS42L43_PROVIDER_RATE_MASK 0xEF // 44.1k only supported as consumer
static const struct snd_pcm_hw_constraint_list cs42l43_constraint = {
.count = ARRAY_SIZE(cs42l43_sample_rates),
.list = cs42l43_sample_rates,
};
static int cs42l43_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
struct cs42l43 *cs42l43 = priv->core;
int provider = !!regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2,
CS42L43_ASP_MASTER_MODE_MASK);
if (provider)
priv->constraint.mask = CS42L43_PROVIDER_RATE_MASK;
else
priv->constraint.mask = CS42L43_CONSUMER_RATE_MASK;
return snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&priv->constraint);
}
static int cs42l43_convert_sample_rate(unsigned int rate)
{
switch (rate) {
case 8000:
return 0x11;
case 16000:
return 0x12;
case 24000:
return 0x02;
case 32000:
return 0x13;
case 44100:
return 0x0B;
case 48000:
return 0x03;
case 96000:
return 0x04;
case 192000:
return 0x05;
default:
return -EINVAL;
}
}
static int cs42l43_set_sample_rate(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct cs42l43_codec *priv = snd_soc_component_get_drvdata(dai->component);
struct cs42l43 *cs42l43 = priv->core;
int ret;
ret = cs42l43_convert_sample_rate(params_rate(params));
if (ret < 0) {
dev_err(priv->dev, "Failed to convert sample rate: %d\n", ret);
return ret;
}
//FIXME: For now lets just set sample rate 1, this needs expanded in the future
regmap_update_bits(cs42l43->regmap, CS42L43_SAMPLE_RATE1,
CS42L43_SAMPLE_RATE_MASK, ret);
return 0;
}
static int cs42l43_asp_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct cs42l43_codec *priv = snd_soc_component_get_drvdata(dai->component);
struct cs42l43 *cs42l43 = priv->core;
int dsp_mode = !!regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CTRL,
CS42L43_ASP_FSYNC_MODE_MASK);
int provider = !!regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2,
CS42L43_ASP_MASTER_MODE_MASK);
int n_chans = params_channels(params);
int data_width = params_width(params);
int n_slots = n_chans;
int slot_width = data_width;
int frame, bclk_target, i;
unsigned int reg;
int *slots;
if (priv->n_slots) {
n_slots = priv->n_slots;
slot_width = priv->slot_width;
}
if (!dsp_mode && (n_slots & 0x1)) {
dev_dbg(priv->dev, "Forcing balanced channels on ASP\n");
n_slots++;
}
frame = n_slots * slot_width;
bclk_target = params_rate(params) * frame;
if (provider) {
unsigned int gcd_nm = gcd(bclk_target, CS42L43_INTERNAL_SYSCLK);
int n = bclk_target / gcd_nm;
int m = CS42L43_INTERNAL_SYSCLK / gcd_nm;
if (n > (CS42L43_ASP_BCLK_N_MASK >> CS42L43_ASP_BCLK_N_SHIFT) ||
m > CS42L43_ASP_BCLK_M_MASK) {
dev_err(priv->dev, "Can't produce %dHz bclk\n", bclk_target);
return -EINVAL;
}
dev_dbg(priv->dev, "bclk %d/%d = %dHz, with %dx%d frame\n",
n, m, bclk_target, n_slots, slot_width);
regmap_update_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG1,
CS42L43_ASP_BCLK_N_MASK | CS42L43_ASP_BCLK_M_MASK,
n << CS42L43_ASP_BCLK_N_SHIFT |
m << CS42L43_ASP_BCLK_M_SHIFT);
regmap_update_bits(cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL1,
CS42L43_ASP_FSYNC_M_MASK, frame);
}
regmap_update_bits(cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL4,
CS42L43_ASP_NUM_BCLKS_PER_FSYNC_MASK,
frame << CS42L43_ASP_NUM_BCLKS_PER_FSYNC_SHIFT);
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
reg = CS42L43_ASP_TX_CH1_CTRL;
slots = priv->tx_slots;
} else {
reg = CS42L43_ASP_RX_CH1_CTRL;
slots = priv->rx_slots;
}
for (i = 0; i < n_chans; i++, reg += 4) {
int slot_phase = dsp_mode | (i & CS42L43_ASP_CH_SLOT_PHASE_MASK);
int slot_pos;
if (dsp_mode)
slot_pos = slots[i] * slot_width;
else
slot_pos = (slots[i] / 2) * slot_width;
dev_dbg(priv->dev, "Configure channel %d at slot %d (%d,%d)\n",
i, slots[i], slot_pos, slot_phase);
regmap_update_bits(cs42l43->regmap, reg,
CS42L43_ASP_CH_WIDTH_MASK |
CS42L43_ASP_CH_SLOT_MASK |
CS42L43_ASP_CH_SLOT_PHASE_MASK,
((data_width - 1) << CS42L43_ASP_CH_WIDTH_SHIFT) |
(slot_pos << CS42L43_ASP_CH_SLOT_SHIFT) |
slot_phase);
}
return cs42l43_set_sample_rate(substream, params, dai);
}
static int cs42l43_asp_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
struct cs42l43 *cs42l43 = priv->core;
int provider = regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2,
CS42L43_ASP_MASTER_MODE_MASK);
struct snd_soc_dapm_route routes[] = {
{ "BCLK", NULL, "FSYNC" },
};
unsigned int asp_ctrl = 0;
unsigned int data_ctrl = 0;
unsigned int fsync_ctrl = 0;
unsigned int clk_config = 0;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
data_ctrl |= 2 << CS42L43_ASP_FSYNC_FRAME_START_DLY_SHIFT;
fallthrough;
case SND_SOC_DAIFMT_DSP_B:
asp_ctrl |= CS42L43_ASP_FSYNC_MODE_MASK;
data_ctrl |= CS42L43_ASP_FSYNC_FRAME_START_PHASE_MASK;
break;
case SND_SOC_DAIFMT_I2S:
data_ctrl |= 2 << CS42L43_ASP_FSYNC_FRAME_START_DLY_SHIFT;
break;
case SND_SOC_DAIFMT_LEFT_J:
data_ctrl |= CS42L43_ASP_FSYNC_FRAME_START_PHASE_MASK;
break;
default:
dev_err(priv->dev, "Unsupported DAI format 0x%x\n",
fmt & SND_SOC_DAIFMT_FORMAT_MASK);
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC:
if (provider)
snd_soc_dapm_del_routes(dapm, routes, ARRAY_SIZE(routes));
break;
case SND_SOC_DAIFMT_CBP_CFP:
if (!provider)
snd_soc_dapm_add_routes(dapm, routes, ARRAY_SIZE(routes));
clk_config |= CS42L43_ASP_MASTER_MODE_MASK;
break;
default:
dev_err(priv->dev, "Unsupported ASP mode 0x%x\n",
fmt & SND_SOC_DAIFMT_MASTER_MASK);
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
clk_config |= CS42L43_ASP_BCLK_INV_MASK; /* Yes BCLK_INV = NB */
break;
case SND_SOC_DAIFMT_IB_NF:
break;
case SND_SOC_DAIFMT_NB_IF:
clk_config |= CS42L43_ASP_BCLK_INV_MASK;
fsync_ctrl |= CS42L43_ASP_FSYNC_IN_INV_MASK |
CS42L43_ASP_FSYNC_OUT_INV_MASK;
break;
case SND_SOC_DAIFMT_IB_IF:
fsync_ctrl |= CS42L43_ASP_FSYNC_IN_INV_MASK |
CS42L43_ASP_FSYNC_OUT_INV_MASK;
break;
default:
dev_err(priv->dev, "Unsupported invert mode 0x%x\n",
fmt & SND_SOC_DAIFMT_INV_MASK);
return -EINVAL;
}
regmap_update_bits(cs42l43->regmap, CS42L43_ASP_CTRL,
CS42L43_ASP_FSYNC_MODE_MASK,
asp_ctrl);
regmap_update_bits(cs42l43->regmap, CS42L43_ASP_DATA_CTRL,
CS42L43_ASP_FSYNC_FRAME_START_DLY_MASK |
CS42L43_ASP_FSYNC_FRAME_START_PHASE_MASK,
data_ctrl);
regmap_update_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2,
CS42L43_ASP_MASTER_MODE_MASK |
CS42L43_ASP_BCLK_INV_MASK,
clk_config);
regmap_update_bits(cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL3,
CS42L43_ASP_FSYNC_IN_INV_MASK |
CS42L43_ASP_FSYNC_OUT_INV_MASK,
fsync_ctrl);
return 0;
}
static void cs42l43_mask_to_slots(struct cs42l43_codec *priv, unsigned int mask, int *slots)
{
int i;
for (i = 0; i < CS42L43_ASP_MAX_CHANNELS; ++i) {
int slot = ffs(mask) - 1;
if (slot < 0)
return;
slots[i] = slot;
mask &= ~(1 << slot);
}
if (mask)
dev_warn(priv->dev, "Too many channels in TDM mask\n");
}
static int cs42l43_asp_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
priv->n_slots = slots;
priv->slot_width = slot_width;
if (!slots) {
tx_mask = CS42L43_DEFAULT_SLOTS;
rx_mask = CS42L43_DEFAULT_SLOTS;
}
cs42l43_mask_to_slots(priv, tx_mask, priv->tx_slots);
cs42l43_mask_to_slots(priv, rx_mask, priv->rx_slots);
return 0;
}
static const struct snd_soc_dai_ops cs42l43_asp_ops = {
.startup = cs42l43_startup,
.hw_params = cs42l43_asp_hw_params,
.set_fmt = cs42l43_asp_set_fmt,
.set_tdm_slot = cs42l43_asp_set_tdm_slot,
};
static int cs42l43_sdw_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
int ret;
ret = cs42l43_sdw_add_peripheral(substream, params, dai);
if (ret)
return ret;
return cs42l43_set_sample_rate(substream, params, dai);
};
static const struct snd_soc_dai_ops cs42l43_sdw_ops = {
.startup = cs42l43_startup,
.set_stream = cs42l43_sdw_set_stream,
.hw_params = cs42l43_sdw_hw_params,
.hw_free = cs42l43_sdw_remove_peripheral,
};
#define CS42L43_ASP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE)
#define CS42L43_SDW_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
static struct snd_soc_dai_driver cs42l43_dais[] = {
{
.name = "cs42l43-asp",
.ops = &cs42l43_asp_ops,
.symmetric_rate = 1,
.capture = {
.stream_name = "ASP Capture",
.channels_min = 1,
.channels_max = CS42L43_ASP_MAX_CHANNELS,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = CS42L43_ASP_FORMATS,
},
.playback = {
.stream_name = "ASP Playback",
.channels_min = 1,
.channels_max = CS42L43_ASP_MAX_CHANNELS,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = CS42L43_ASP_FORMATS,
},
},
{
.name = "cs42l43-dp1",
.id = 1,
.ops = &cs42l43_sdw_ops,
.capture = {
.stream_name = "DP1 Capture",
.channels_min = 1,
.channels_max = 4,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = CS42L43_SDW_FORMATS,
},
},
{
.name = "cs42l43-dp2",
.id = 2,
.ops = &cs42l43_sdw_ops,
.capture = {
.stream_name = "DP2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = CS42L43_SDW_FORMATS,
},
},
{
.name = "cs42l43-dp3",
.id = 3,
.ops = &cs42l43_sdw_ops,
.capture = {
.stream_name = "DP3 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = CS42L43_SDW_FORMATS,
},
},
{
.name = "cs42l43-dp4",
.id = 4,
.ops = &cs42l43_sdw_ops,
.capture = {
.stream_name = "DP4 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = CS42L43_SDW_FORMATS,
},
},
{
.name = "cs42l43-dp5",
.id = 5,
.ops = &cs42l43_sdw_ops,
.playback = {
.stream_name = "DP5 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = CS42L43_SDW_FORMATS,
},
},
{
.name = "cs42l43-dp6",
.id = 6,
.ops = &cs42l43_sdw_ops,
.playback = {
.stream_name = "DP6 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = CS42L43_SDW_FORMATS,
},
},
{
.name = "cs42l43-dp7",
.id = 7,
.ops = &cs42l43_sdw_ops,
.playback = {
.stream_name = "DP7 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = CS42L43_SDW_FORMATS,
},
},
};
static const DECLARE_TLV_DB_SCALE(cs42l43_mixer_tlv, -3200, 100, 0);
static const char * const cs42l43_ramp_text[] = {
"0ms/6dB", "0.5ms/6dB", "1ms/6dB", "2ms/6dB", "4ms/6dB", "8ms/6dB",
"15ms/6dB", "30ms/6dB",
};
static const char * const cs42l43_adc1_input_text[] = { "IN1", "IN2" };
static SOC_ENUM_SINGLE_DECL(cs42l43_adc1_input, CS42L43_ADC_B_CTRL1,
CS42L43_ADC_AIN_SEL_SHIFT,
cs42l43_adc1_input_text);
static const struct snd_kcontrol_new cs42l43_adc1_input_ctl =
SOC_DAPM_ENUM("ADC1 Input", cs42l43_adc1_input);
static const char * const cs42l43_dec_mode_text[] = { "ADC", "PDM" };
static SOC_ENUM_SINGLE_VIRT_DECL(cs42l43_dec1_mode, cs42l43_dec_mode_text);
static SOC_ENUM_SINGLE_VIRT_DECL(cs42l43_dec2_mode, cs42l43_dec_mode_text);
static const struct snd_kcontrol_new cs42l43_dec_mode_ctl[] = {
SOC_DAPM_ENUM("Decimator 1 Mode", cs42l43_dec1_mode),
SOC_DAPM_ENUM("Decimator 2 Mode", cs42l43_dec2_mode),
};
static const char * const cs42l43_pdm_clk_text[] = {
"3.072MHz", "1.536MHz", "768kHz",
};
static SOC_ENUM_SINGLE_DECL(cs42l43_pdm1_clk, CS42L43_PDM_CONTROL,
CS42L43_PDM1_CLK_DIV_SHIFT, cs42l43_pdm_clk_text);
static SOC_ENUM_SINGLE_DECL(cs42l43_pdm2_clk, CS42L43_PDM_CONTROL,
CS42L43_PDM2_CLK_DIV_SHIFT, cs42l43_pdm_clk_text);
static DECLARE_TLV_DB_SCALE(cs42l43_adc_tlv, -600, 600, 0);
static DECLARE_TLV_DB_SCALE(cs42l43_dec_tlv, -6400, 50, 0);
static const char * const cs42l43_wnf_corner_text[] = {
"160Hz", "180Hz", "200Hz", "220Hz", "240Hz", "260Hz", "280Hz", "300Hz",
};
static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL1,
CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text);
static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL2,
CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text);
static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL3,
CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text);
static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL4,
CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text);
static const char * const cs42l43_hpf_corner_text[] = {
"3Hz", "12Hz", "48Hz", "96Hz",
};
static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL1,
CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text);
static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL2,
CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text);
static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL3,
CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text);
static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL4,
CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text);
static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_ramp_up, CS42L43_DECIM_VOL_CTRL_CH1_CH2,
CS42L43_DECIM1_VI_RAMP_SHIFT, cs42l43_ramp_text);
static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_ramp_down, CS42L43_DECIM_VOL_CTRL_CH1_CH2,
CS42L43_DECIM1_VD_RAMP_SHIFT, cs42l43_ramp_text);
static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_ramp_up, CS42L43_DECIM_VOL_CTRL_CH1_CH2,
CS42L43_DECIM2_VI_RAMP_SHIFT, cs42l43_ramp_text);
static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_ramp_down, CS42L43_DECIM_VOL_CTRL_CH1_CH2,
CS42L43_DECIM2_VD_RAMP_SHIFT, cs42l43_ramp_text);
static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_ramp_up, CS42L43_DECIM_VOL_CTRL_CH3_CH4,
CS42L43_DECIM3_VI_RAMP_SHIFT, cs42l43_ramp_text);
static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_ramp_down, CS42L43_DECIM_VOL_CTRL_CH3_CH4,
CS42L43_DECIM3_VD_RAMP_SHIFT, cs42l43_ramp_text);
static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_ramp_up, CS42L43_DECIM_VOL_CTRL_CH3_CH4,
CS42L43_DECIM4_VI_RAMP_SHIFT, cs42l43_ramp_text);
static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_ramp_down, CS42L43_DECIM_VOL_CTRL_CH3_CH4,
CS42L43_DECIM4_VD_RAMP_SHIFT, cs42l43_ramp_text);
static DECLARE_TLV_DB_SCALE(cs42l43_speaker_tlv, -6400, 50, 0);
static SOC_ENUM_SINGLE_DECL(cs42l43_speaker_ramp_up, CS42L43_AMP1_2_VOL_RAMP,
CS42L43_AMP1_2_VI_RAMP_SHIFT, cs42l43_ramp_text);
static SOC_ENUM_SINGLE_DECL(cs42l43_speaker_ramp_down, CS42L43_AMP1_2_VOL_RAMP,
CS42L43_AMP1_2_VD_RAMP_SHIFT, cs42l43_ramp_text);
static DECLARE_TLV_DB_SCALE(cs42l43_headphone_tlv, -11450, 50, 1);
static const char * const cs42l43_headphone_ramp_text[] = {
"1", "2", "4", "6", "8", "11", "12", "16", "22", "24", "33", "36", "44",
"48", "66", "72",
};
static SOC_ENUM_SINGLE_DECL(cs42l43_headphone_ramp, CS42L43_PGAVOL,
CS42L43_HP_PATH_VOL_RAMP_SHIFT,
cs42l43_headphone_ramp_text);
static const char * const cs42l43_tone_freq_text[] = {
"1kHz", "2kHz", "4kHz", "6kHz", "8kHz",
};
static SOC_ENUM_SINGLE_DECL(cs42l43_tone1_freq, CS42L43_TONE_CH1_CTRL,
CS42L43_TONE_FREQ_SHIFT, cs42l43_tone_freq_text);
static SOC_ENUM_SINGLE_DECL(cs42l43_tone2_freq, CS42L43_TONE_CH2_CTRL,
CS42L43_TONE_FREQ_SHIFT, cs42l43_tone_freq_text);
static const char * const cs42l43_mixer_texts[] = {
"None",
"Tone Generator 1", "Tone Generator 2",
"Decimator 1", "Decimator 2", "Decimator 3", "Decimator 4",
"ASPRX1", "ASPRX2", "ASPRX3", "ASPRX4", "ASPRX5", "ASPRX6",
"DP5RX1", "DP5RX2", "DP6RX1", "DP6RX2", "DP7RX1", "DP7RX2",
"ASRC INT1", "ASRC INT2", "ASRC INT3", "ASRC INT4",
"ASRC DEC1", "ASRC DEC2", "ASRC DEC3", "ASRC DEC4",
"ISRC1 INT1", "ISRC1 INT2",
"ISRC1 DEC1", "ISRC1 DEC2",
"ISRC2 INT1", "ISRC2 INT2",
"ISRC2 DEC1", "ISRC2 DEC2",
"EQ1", "EQ2",
};
static const unsigned int cs42l43_mixer_values[] = {
0x00, // None
0x04, 0x05, // Tone Generator 1, 2
0x10, 0x11, 0x12, 0x13, // Decimator 1, 2, 3, 4
0x20, 0x21, 0x22, 0x23, 0x24, 0x25, // ASPRX1,2,3,4,5,6
0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, // DP5, 6, 7RX1, 2
0x40, 0x41, 0x42, 0x43, // ASRC INT1, 2, 3, 4
0x44, 0x45, 0x46, 0x47, // ASRC DEC1, 2, 3, 4
0x50, 0x51, // ISRC1 INT1, 2
0x52, 0x53, // ISRC1 DEC1, 2
0x54, 0x55, // ISRC2 INT1, 2
0x56, 0x57, // ISRC2 DEC1, 2
0x58, 0x59, // EQ1, 2
};
CS42L43_DECL_MUX(asptx1, CS42L43_ASPTX1_INPUT);
CS42L43_DECL_MUX(asptx2, CS42L43_ASPTX2_INPUT);
CS42L43_DECL_MUX(asptx3, CS42L43_ASPTX3_INPUT);
CS42L43_DECL_MUX(asptx4, CS42L43_ASPTX4_INPUT);
CS42L43_DECL_MUX(asptx5, CS42L43_ASPTX5_INPUT);
CS42L43_DECL_MUX(asptx6, CS42L43_ASPTX6_INPUT);
CS42L43_DECL_MUX(dp1tx1, CS42L43_SWIRE_DP1_CH1_INPUT);
CS42L43_DECL_MUX(dp1tx2, CS42L43_SWIRE_DP1_CH2_INPUT);
CS42L43_DECL_MUX(dp1tx3, CS42L43_SWIRE_DP1_CH3_INPUT);
CS42L43_DECL_MUX(dp1tx4, CS42L43_SWIRE_DP1_CH4_INPUT);
CS42L43_DECL_MUX(dp2tx1, CS42L43_SWIRE_DP2_CH1_INPUT);
CS42L43_DECL_MUX(dp2tx2, CS42L43_SWIRE_DP2_CH2_INPUT);
CS42L43_DECL_MUX(dp3tx1, CS42L43_SWIRE_DP3_CH1_INPUT);
CS42L43_DECL_MUX(dp3tx2, CS42L43_SWIRE_DP3_CH2_INPUT);
CS42L43_DECL_MUX(dp4tx1, CS42L43_SWIRE_DP4_CH1_INPUT);
CS42L43_DECL_MUX(dp4tx2, CS42L43_SWIRE_DP4_CH2_INPUT);
CS42L43_DECL_MUX(asrcint1, CS42L43_ASRC_INT1_INPUT1);
CS42L43_DECL_MUX(asrcint2, CS42L43_ASRC_INT2_INPUT1);
CS42L43_DECL_MUX(asrcint3, CS42L43_ASRC_INT3_INPUT1);
CS42L43_DECL_MUX(asrcint4, CS42L43_ASRC_INT4_INPUT1);
CS42L43_DECL_MUX(asrcdec1, CS42L43_ASRC_DEC1_INPUT1);
CS42L43_DECL_MUX(asrcdec2, CS42L43_ASRC_DEC2_INPUT1);
CS42L43_DECL_MUX(asrcdec3, CS42L43_ASRC_DEC3_INPUT1);
CS42L43_DECL_MUX(asrcdec4, CS42L43_ASRC_DEC4_INPUT1);
CS42L43_DECL_MUX(isrc1int1, CS42L43_ISRC1INT1_INPUT1);
CS42L43_DECL_MUX(isrc1int2, CS42L43_ISRC1INT2_INPUT1);
CS42L43_DECL_MUX(isrc1dec1, CS42L43_ISRC1DEC1_INPUT1);
CS42L43_DECL_MUX(isrc1dec2, CS42L43_ISRC1DEC2_INPUT1);
CS42L43_DECL_MUX(isrc2int1, CS42L43_ISRC2INT1_INPUT1);
CS42L43_DECL_MUX(isrc2int2, CS42L43_ISRC2INT2_INPUT1);
CS42L43_DECL_MUX(isrc2dec1, CS42L43_ISRC2DEC1_INPUT1);
CS42L43_DECL_MUX(isrc2dec2, CS42L43_ISRC2DEC2_INPUT1);
CS42L43_DECL_MUX(spdif1, CS42L43_SPDIF1_INPUT1);
CS42L43_DECL_MUX(spdif2, CS42L43_SPDIF2_INPUT1);
CS42L43_DECL_MIXER(eq1, CS42L43_EQ1MIX_INPUT1);
CS42L43_DECL_MIXER(eq2, CS42L43_EQ2MIX_INPUT1);
CS42L43_DECL_MIXER(amp1, CS42L43_AMP1MIX_INPUT1);
CS42L43_DECL_MIXER(amp2, CS42L43_AMP2MIX_INPUT1);
CS42L43_DECL_MIXER(amp3, CS42L43_AMP3MIX_INPUT1);
CS42L43_DECL_MIXER(amp4, CS42L43_AMP4MIX_INPUT1);
static int cs42l43_dapm_get_volsw(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
int ret;
snd_soc_dapm_mutex_lock(dapm);
ret = snd_soc_get_volsw(kcontrol, ucontrol);
snd_soc_dapm_mutex_unlock(dapm);
return ret;
}
static int cs42l43_dapm_put_volsw(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
int ret;
snd_soc_dapm_mutex_lock(dapm);
ret = snd_soc_put_volsw(kcontrol, ucontrol);
snd_soc_dapm_mutex_unlock(dapm);
return ret;
}
static int cs42l43_dapm_get_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
int ret;
snd_soc_dapm_mutex_lock(dapm);
ret = snd_soc_get_enum_double(kcontrol, ucontrol);
snd_soc_dapm_mutex_unlock(dapm);
return ret;
}
static int cs42l43_dapm_put_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
int ret;
snd_soc_dapm_mutex_lock(dapm);
ret = snd_soc_put_enum_double(kcontrol, ucontrol);
snd_soc_dapm_mutex_unlock(dapm);
return ret;
}
static int cs42l43_eq_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
memcpy(ucontrol->value.integer.value, priv->eq_coeffs, sizeof(priv->eq_coeffs));
return 0;
}
static int cs42l43_eq_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
snd_soc_dapm_mutex_lock(dapm);
memcpy(priv->eq_coeffs, ucontrol->value.integer.value, sizeof(priv->eq_coeffs));
snd_soc_dapm_mutex_unlock(dapm);
return 0;
}
static void cs42l43_spk_vu_sync(struct cs42l43_codec *priv)
{
struct cs42l43 *cs42l43 = priv->core;
mutex_lock(&priv->spk_vu_lock);
regmap_update_bits(cs42l43->regmap, CS42L43_INTP_VOLUME_CTRL1,
CS42L43_AMP1_2_VU_MASK, CS42L43_AMP1_2_VU_MASK);
regmap_update_bits(cs42l43->regmap, CS42L43_INTP_VOLUME_CTRL1,
CS42L43_AMP1_2_VU_MASK, 0);
mutex_unlock(&priv->spk_vu_lock);
}
static int cs42l43_shutter_get(struct cs42l43_codec *priv, unsigned int shift)
{
struct cs42l43 *cs42l43 = priv->core;
unsigned int val;
int ret;
ret = pm_runtime_resume_and_get(priv->dev);
if (ret) {
dev_err(priv->dev, "Failed to resume for shutters: %d\n", ret);
return ret;
}
/*
* SHUTTER_CONTROL is a mix of volatile and non-volatile bits, so must
* be cached for the non-volatiles, so drop it from the cache here so
* we force a read.
*/
ret = regcache_drop_region(cs42l43->regmap, CS42L43_SHUTTER_CONTROL,
CS42L43_SHUTTER_CONTROL);
if (ret) {
dev_err(priv->dev, "Failed to drop shutter from cache: %d\n", ret);
goto error;
}
ret = regmap_read(cs42l43->regmap, CS42L43_SHUTTER_CONTROL, &val);
if (ret) {
dev_err(priv->dev, "Failed to check shutter status: %d\n", ret);
goto error;
}
ret = !(val & BIT(shift));
dev_dbg(priv->dev, "%s shutter is %s\n",
BIT(shift) == CS42L43_STATUS_MIC_SHUTTER_MUTE_MASK ? "Mic" : "Speaker",
ret ? "open" : "closed");
error:
pm_runtime_mark_last_busy(priv->dev);
pm_runtime_put_autosuspend(priv->dev);
return ret;
}
static int cs42l43_decim_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
int ret;
ret = cs42l43_shutter_get(priv, CS42L43_STATUS_MIC_SHUTTER_MUTE_SHIFT);
if (ret < 0)
return ret;
else if (!ret)
ucontrol->value.integer.value[0] = ret;
else
ret = cs42l43_dapm_get_volsw(kcontrol, ucontrol);
return ret;
}
static int cs42l43_spk_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
int ret;
ret = cs42l43_shutter_get(priv, CS42L43_STATUS_SPK_SHUTTER_MUTE_SHIFT);
if (ret < 0)
return ret;
else if (!ret)
ucontrol->value.integer.value[0] = ret;
else
ret = snd_soc_get_volsw(kcontrol, ucontrol);
return ret;
}
static int cs42l43_spk_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
int ret;
ret = snd_soc_put_volsw(kcontrol, ucontrol);
if (ret > 0)
cs42l43_spk_vu_sync(priv);
return ret;
}
static const struct snd_kcontrol_new cs42l43_controls[] = {
SOC_ENUM_EXT("Jack Override", cs42l43_jack_enum,
cs42l43_jack_get, cs42l43_jack_put),
SOC_DOUBLE_R_SX_TLV("ADC Volume", CS42L43_ADC_B_CTRL1, CS42L43_ADC_B_CTRL2,
CS42L43_ADC_PGA_GAIN_SHIFT,
0xF, 5, cs42l43_adc_tlv),
SOC_DOUBLE("PDM1 Invert Switch", CS42L43_DMIC_PDM_CTRL,
CS42L43_PDM1L_INV_SHIFT, CS42L43_PDM1R_INV_SHIFT, 1, 0),
SOC_DOUBLE("PDM2 Invert Switch", CS42L43_DMIC_PDM_CTRL,
CS42L43_PDM2L_INV_SHIFT, CS42L43_PDM2R_INV_SHIFT, 1, 0),
SOC_ENUM("PDM1 Clock", cs42l43_pdm1_clk),
SOC_ENUM("PDM2 Clock", cs42l43_pdm2_clk),
SOC_SINGLE("Decimator 1 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL1,
CS42L43_DECIM_WNF_EN_SHIFT, 1, 0),
SOC_SINGLE("Decimator 2 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL2,
CS42L43_DECIM_WNF_EN_SHIFT, 1, 0),
SOC_SINGLE("Decimator 3 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL3,
CS42L43_DECIM_WNF_EN_SHIFT, 1, 0),
SOC_SINGLE("Decimator 4 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL4,
CS42L43_DECIM_WNF_EN_SHIFT, 1, 0),
SOC_ENUM("Decimator 1 WNF Corner Frequency", cs42l43_dec1_wnf_corner),
SOC_ENUM("Decimator 2 WNF Corner Frequency", cs42l43_dec2_wnf_corner),
SOC_ENUM("Decimator 3 WNF Corner Frequency", cs42l43_dec3_wnf_corner),
SOC_ENUM("Decimator 4 WNF Corner Frequency", cs42l43_dec4_wnf_corner),
SOC_SINGLE("Decimator 1 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL1,
CS42L43_DECIM_HPF_EN_SHIFT, 1, 0),
SOC_SINGLE("Decimator 2 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL2,
CS42L43_DECIM_HPF_EN_SHIFT, 1, 0),
SOC_SINGLE("Decimator 3 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL3,
CS42L43_DECIM_HPF_EN_SHIFT, 1, 0),
SOC_SINGLE("Decimator 4 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL4,
CS42L43_DECIM_HPF_EN_SHIFT, 1, 0),
SOC_ENUM("Decimator 1 HPF Corner Frequency", cs42l43_dec1_hpf_corner),
SOC_ENUM("Decimator 2 HPF Corner Frequency", cs42l43_dec2_hpf_corner),
SOC_ENUM("Decimator 3 HPF Corner Frequency", cs42l43_dec3_hpf_corner),
SOC_ENUM("Decimator 4 HPF Corner Frequency", cs42l43_dec4_hpf_corner),
SOC_SINGLE_TLV("Decimator 1 Volume", CS42L43_DECIM_VOL_CTRL_CH1_CH2,
CS42L43_DECIM1_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv),
SOC_SINGLE_EXT("Decimator 1 Switch", CS42L43_DECIM_VOL_CTRL_CH1_CH2,
CS42L43_DECIM1_MUTE_SHIFT, 1, 1,
cs42l43_decim_get, cs42l43_dapm_put_volsw),
SOC_SINGLE_TLV("Decimator 2 Volume", CS42L43_DECIM_VOL_CTRL_CH1_CH2,
CS42L43_DECIM2_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv),
SOC_SINGLE_EXT("Decimator 2 Switch", CS42L43_DECIM_VOL_CTRL_CH1_CH2,
CS42L43_DECIM2_MUTE_SHIFT, 1, 1,
cs42l43_decim_get, cs42l43_dapm_put_volsw),
SOC_SINGLE_TLV("Decimator 3 Volume", CS42L43_DECIM_VOL_CTRL_CH3_CH4,
CS42L43_DECIM3_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv),
SOC_SINGLE_EXT("Decimator 3 Switch", CS42L43_DECIM_VOL_CTRL_CH3_CH4,
CS42L43_DECIM3_MUTE_SHIFT, 1, 1,
cs42l43_decim_get, cs42l43_dapm_put_volsw),
SOC_SINGLE_TLV("Decimator 4 Volume", CS42L43_DECIM_VOL_CTRL_CH3_CH4,
CS42L43_DECIM4_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv),
SOC_SINGLE_EXT("Decimator 4 Switch", CS42L43_DECIM_VOL_CTRL_CH3_CH4,
CS42L43_DECIM4_MUTE_SHIFT, 1, 1,
cs42l43_decim_get, cs42l43_dapm_put_volsw),
SOC_ENUM_EXT("Decimator 1 Ramp Up", cs42l43_dec1_ramp_up,
cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
SOC_ENUM_EXT("Decimator 1 Ramp Down", cs42l43_dec1_ramp_down,
cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
SOC_ENUM_EXT("Decimator 2 Ramp Up", cs42l43_dec2_ramp_up,
cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
SOC_ENUM_EXT("Decimator 2 Ramp Down", cs42l43_dec2_ramp_down,
cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
SOC_ENUM_EXT("Decimator 3 Ramp Up", cs42l43_dec3_ramp_up,
cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
SOC_ENUM_EXT("Decimator 3 Ramp Down", cs42l43_dec3_ramp_down,
cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
SOC_ENUM_EXT("Decimator 4 Ramp Up", cs42l43_dec4_ramp_up,
cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
SOC_ENUM_EXT("Decimator 4 Ramp Down", cs42l43_dec4_ramp_down,
cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
SOC_DOUBLE_R_EXT("Speaker Digital Switch",
CS42L43_INTP_VOLUME_CTRL1, CS42L43_INTP_VOLUME_CTRL2,
CS42L43_AMP_MUTE_SHIFT, 1, 1,
cs42l43_spk_get, cs42l43_spk_put),
SOC_DOUBLE_R_EXT_TLV("Speaker Digital Volume",
CS42L43_INTP_VOLUME_CTRL1, CS42L43_INTP_VOLUME_CTRL2,
CS42L43_AMP_VOL_SHIFT,
0xBF, 0, snd_soc_get_volsw, cs42l43_spk_put,
cs42l43_speaker_tlv),
SOC_ENUM("Speaker Ramp Up", cs42l43_speaker_ramp_up),
SOC_ENUM("Speaker Ramp Down", cs42l43_speaker_ramp_down),
CS42L43_MIXER_VOLUMES("Speaker L", CS42L43_AMP1MIX_INPUT1),
CS42L43_MIXER_VOLUMES("Speaker R", CS42L43_AMP2MIX_INPUT1),
SOC_DOUBLE_SX_TLV("Headphone Digital Volume", CS42L43_HPPATHVOL,
CS42L43_AMP3_PATH_VOL_SHIFT, CS42L43_AMP4_PATH_VOL_SHIFT,
0x11B, 229, cs42l43_headphone_tlv),
SOC_DOUBLE("Headphone Invert Switch", CS42L43_DACCNFG1,
CS42L43_AMP3_INV_SHIFT, CS42L43_AMP4_INV_SHIFT, 1, 0),
SOC_SINGLE("Headphone Zero Cross Switch", CS42L43_PGAVOL,
CS42L43_HP_PATH_VOL_ZC_SHIFT, 1, 0),
SOC_SINGLE("Headphone Ramp Switch", CS42L43_PGAVOL,
CS42L43_HP_PATH_VOL_SFT_SHIFT, 1, 0),
SOC_ENUM("Headphone Ramp Rate", cs42l43_headphone_ramp),
CS42L43_MIXER_VOLUMES("Headphone L", CS42L43_AMP3MIX_INPUT1),
CS42L43_MIXER_VOLUMES("Headphone R", CS42L43_AMP4MIX_INPUT1),
SOC_ENUM("Tone 1 Frequency", cs42l43_tone1_freq),
SOC_ENUM("Tone 2 Frequency", cs42l43_tone2_freq),
SOC_DOUBLE_EXT("EQ Switch",
CS42L43_MUTE_EQ_IN0, CS42L43_MUTE_EQ_CH1_SHIFT,
CS42L43_MUTE_EQ_CH2_SHIFT, 1, 1,
cs42l43_dapm_get_volsw, cs42l43_dapm_put_volsw),
SND_SOC_BYTES_E("EQ Coefficients", 0, CS42L43_N_EQ_COEFFS,
cs42l43_eq_get, cs42l43_eq_put),
CS42L43_MIXER_VOLUMES("EQ1", CS42L43_EQ1MIX_INPUT1),
CS42L43_MIXER_VOLUMES("EQ2", CS42L43_EQ2MIX_INPUT1),
};
static int cs42l43_eq_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
struct cs42l43 *cs42l43 = priv->core;
unsigned int val;
int i, ret;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
regmap_update_bits(cs42l43->regmap, CS42L43_MUTE_EQ_IN0,
CS42L43_MUTE_EQ_CH1_MASK | CS42L43_MUTE_EQ_CH2_MASK,
CS42L43_MUTE_EQ_CH1_MASK | CS42L43_MUTE_EQ_CH2_MASK);
regmap_update_bits(cs42l43->regmap, CS42L43_COEFF_RD_WR0,
CS42L43_WRITE_MODE_MASK, CS42L43_WRITE_MODE_MASK);
for (i = 0; i < CS42L43_N_EQ_COEFFS; i++)
regmap_write(cs42l43->regmap, CS42L43_COEFF_DATA_IN0,
priv->eq_coeffs[i]);
regmap_update_bits(cs42l43->regmap, CS42L43_COEFF_RD_WR0,
CS42L43_WRITE_MODE_MASK, 0);
return 0;
case SND_SOC_DAPM_POST_PMU:
ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_INIT_DONE0,
val, (val & CS42L43_INITIALIZE_DONE_MASK),
2000, 10000);
if (ret)
dev_err(priv->dev, "Failed to start EQs: %d\n", ret);
regmap_update_bits(cs42l43->regmap, CS42L43_MUTE_EQ_IN0,
CS42L43_MUTE_EQ_CH1_MASK | CS42L43_MUTE_EQ_CH2_MASK, 0);
return ret;
default:
return 0;
}
}
struct cs42l43_pll_config {
unsigned int freq;
unsigned int div;
unsigned int mode;
unsigned int cal;
};
static const struct cs42l43_pll_config cs42l43_pll_configs[] = {
{ 2400000, 0x50000000, 0x1, 0xA4 },
{ 3000000, 0x40000000, 0x1, 0x83 },
{ 3072000, 0x40000000, 0x3, 0x80 },
};
static int cs42l43_set_pll(struct cs42l43_codec *priv, unsigned int src,
unsigned int freq)
{
struct cs42l43 *cs42l43 = priv->core;
lockdep_assert_held(&cs42l43->pll_lock);
if (priv->refclk_src == src && priv->refclk_freq == freq)
return 0;
if (regmap_test_bits(cs42l43->regmap, CS42L43_CTRL_REG, CS42L43_PLL_EN_MASK)) {
dev_err(priv->dev, "PLL active, can't change configuration\n");
return -EBUSY;
}
switch (src) {
case CS42L43_SYSCLK_MCLK:
case CS42L43_SYSCLK_SDW:
dev_dbg(priv->dev, "Source PLL from %s at %uHz\n",
src ? "SoundWire" : "MCLK", freq);
priv->refclk_src = src;
priv->refclk_freq = freq;
return 0;
default:
dev_err(priv->dev, "Invalid PLL source: 0x%x\n", src);
return -EINVAL;
}
}
static int cs42l43_enable_pll(struct cs42l43_codec *priv)
{
static const struct reg_sequence enable_seq[] = {
{ CS42L43_OSC_DIV_SEL, 0x0, },
{ CS42L43_MCLK_SRC_SEL, CS42L43_OSC_PLL_MCLK_SEL_MASK, 5, },
};
struct cs42l43 *cs42l43 = priv->core;
const struct cs42l43_pll_config *config = NULL;
unsigned int div = 0;
unsigned int freq = priv->refclk_freq;
unsigned long time_left;
lockdep_assert_held(&cs42l43->pll_lock);
if (priv->refclk_src == CS42L43_SYSCLK_SDW) {
if (!freq)
freq = cs42l43->sdw_freq;
else if (!cs42l43->sdw_freq)
cs42l43->sdw_freq = freq;
}
dev_dbg(priv->dev, "Enabling PLL at %uHz\n", freq);
while (freq > cs42l43_pll_configs[ARRAY_SIZE(cs42l43_pll_configs) - 1].freq) {
div++;
freq /= 2;
}
if (div <= CS42L43_PLL_REFCLK_DIV_MASK) {
int i;
for (i = 0; i < ARRAY_SIZE(cs42l43_pll_configs); i++) {
if (freq == cs42l43_pll_configs[i].freq) {
config = &cs42l43_pll_configs[i];
break;
}
}
}
if (!config) {
dev_err(priv->dev, "No suitable PLL config: 0x%x, %uHz\n", div, freq);
return -EINVAL;
}
regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL,
CS42L43_PLL_REFCLK_DIV_MASK | CS42L43_PLL_REFCLK_SRC_MASK,
div << CS42L43_PLL_REFCLK_DIV_SHIFT |
priv->refclk_src << CS42L43_PLL_REFCLK_SRC_SHIFT);
regmap_write(cs42l43->regmap, CS42L43_FDIV_FRAC, config->div);
regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG,
CS42L43_PLL_MODE_BYPASS_500_MASK |
CS42L43_PLL_MODE_BYPASS_1029_MASK,
config->mode << CS42L43_PLL_MODE_BYPASS_1029_SHIFT);
regmap_update_bits(cs42l43->regmap, CS42L43_CAL_RATIO,
CS42L43_PLL_CAL_RATIO_MASK, config->cal);
regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL,
CS42L43_PLL_REFCLK_EN_MASK, CS42L43_PLL_REFCLK_EN_MASK);
reinit_completion(&priv->pll_ready);
regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG,
CS42L43_PLL_EN_MASK, CS42L43_PLL_EN_MASK);
time_left = wait_for_completion_timeout(&priv->pll_ready,
msecs_to_jiffies(CS42L43_PLL_TIMEOUT_MS));
if (!time_left) {
regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG,
CS42L43_PLL_EN_MASK, 0);
regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL,
CS42L43_PLL_REFCLK_EN_MASK, 0);
dev_err(priv->dev, "Timeout out waiting for PLL\n");
return -ETIMEDOUT;
}
if (priv->refclk_src == CS42L43_SYSCLK_SDW)
cs42l43->sdw_pll_active = true;
dev_dbg(priv->dev, "PLL locked in %ums\n", 200 - jiffies_to_msecs(time_left));
/*
* Reads are not allowed over Soundwire without OSC_DIV2_EN or the PLL,
* but you can not change to PLL with OSC_DIV2_EN set. So ensure the whole
* change over happens under the regmap lock to prevent any reads.
*/
regmap_multi_reg_write(cs42l43->regmap, enable_seq, ARRAY_SIZE(enable_seq));
return 0;
}
static int cs42l43_disable_pll(struct cs42l43_codec *priv)
{
static const struct reg_sequence disable_seq[] = {
{ CS42L43_MCLK_SRC_SEL, 0x0, 5, },
{ CS42L43_OSC_DIV_SEL, CS42L43_OSC_DIV2_EN_MASK, },
};
struct cs42l43 *cs42l43 = priv->core;
dev_dbg(priv->dev, "Disabling PLL\n");
lockdep_assert_held(&cs42l43->pll_lock);
regmap_multi_reg_write(cs42l43->regmap, disable_seq, ARRAY_SIZE(disable_seq));
regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG, CS42L43_PLL_EN_MASK, 0);
regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL,
CS42L43_PLL_REFCLK_EN_MASK, 0);
cs42l43->sdw_pll_active = false;
return 0;
}
static int cs42l43_pll_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
struct cs42l43 *cs42l43 = priv->core;
int ret;
mutex_lock(&cs42l43->pll_lock);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
if (priv->refclk_src == CS42L43_SYSCLK_MCLK) {
ret = clk_prepare_enable(priv->mclk);
if (ret) {
dev_err(priv->dev, "Failed to enable MCLK: %d\n", ret);
break;
}
}
ret = cs42l43_enable_pll(priv);
break;
case SND_SOC_DAPM_POST_PMD:
ret = cs42l43_disable_pll(priv);
if (priv->refclk_src == CS42L43_SYSCLK_MCLK)
clk_disable_unprepare(priv->mclk);
break;
default:
ret = 0;
break;
}
mutex_unlock(&cs42l43->pll_lock);
return ret;
}
static int cs42l43_dapm_wait_completion(struct completion *pmu, struct completion *pmd,
int event, int timeout_ms)
{
unsigned long time_left;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
reinit_completion(pmu);
return 0;
case SND_SOC_DAPM_PRE_PMD:
reinit_completion(pmd);
return 0;
case SND_SOC_DAPM_POST_PMU:
time_left = wait_for_completion_timeout(pmu, msecs_to_jiffies(timeout_ms));
break;
case SND_SOC_DAPM_POST_PMD:
time_left = wait_for_completion_timeout(pmd, msecs_to_jiffies(timeout_ms));
break;
default:
return 0;
}
if (!time_left)
return -ETIMEDOUT;
else
return 0;
}
static int cs42l43_spkr_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
return cs42l43_dapm_wait_completion(&priv->spkr_startup,
&priv->spkr_shutdown, event,
CS42L43_SPK_TIMEOUT_MS);
}
static int cs42l43_spkl_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
return cs42l43_dapm_wait_completion(&priv->spkl_startup,
&priv->spkl_shutdown, event,
CS42L43_SPK_TIMEOUT_MS);
}
static int cs42l43_hp_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
struct cs42l43 *cs42l43 = priv->core;
unsigned int mask = 1 << w->shift;
unsigned int val = 0;
int ret;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
val = mask;
fallthrough;
case SND_SOC_DAPM_PRE_PMD:
priv->hp_ena &= ~mask;
priv->hp_ena |= val;
ret = cs42l43_dapm_wait_completion(&priv->hp_startup,
&priv->hp_shutdown, event,
CS42L43_HP_TIMEOUT_MS);
if (ret)
return ret;
if (!priv->load_detect_running)
regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN8,
mask, val);
break;
case SND_SOC_DAPM_POST_PMU:
case SND_SOC_DAPM_POST_PMD:
if (priv->load_detect_running)
break;
ret = cs42l43_dapm_wait_completion(&priv->hp_startup,
&priv->hp_shutdown, event,
CS42L43_HP_TIMEOUT_MS);
if (ret)
return ret;
break;
default:
break;
}
return 0;
}
static int cs42l43_mic_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
struct cs42l43 *cs42l43 = priv->core;
unsigned int reg, ramp, mute;
unsigned int *val;
int ret;
switch (w->shift) {
case CS42L43_ADC1_EN_SHIFT:
case CS42L43_PDM1_DIN_L_EN_SHIFT:
reg = CS42L43_DECIM_VOL_CTRL_CH1_CH2;
ramp = CS42L43_DECIM1_VD_RAMP_MASK;
mute = CS42L43_DECIM1_MUTE_MASK;
val = &priv->decim_cache[0];
break;
case CS42L43_ADC2_EN_SHIFT:
case CS42L43_PDM1_DIN_R_EN_SHIFT:
reg = CS42L43_DECIM_VOL_CTRL_CH1_CH2;
ramp = CS42L43_DECIM2_VD_RAMP_MASK;
mute = CS42L43_DECIM2_MUTE_MASK;
val = &priv->decim_cache[1];
break;
case CS42L43_PDM2_DIN_L_EN_SHIFT:
reg = CS42L43_DECIM_VOL_CTRL_CH3_CH4;
ramp = CS42L43_DECIM3_VD_RAMP_MASK;
mute = CS42L43_DECIM3_MUTE_MASK;
val = &priv->decim_cache[2];
break;
case CS42L43_PDM2_DIN_R_EN_SHIFT:
reg = CS42L43_DECIM_VOL_CTRL_CH3_CH4;
ramp = CS42L43_DECIM4_VD_RAMP_MASK;
mute = CS42L43_DECIM4_MUTE_MASK;
val = &priv->decim_cache[3];
break;
default:
dev_err(priv->dev, "Invalid microphone shift: %d\n", w->shift);
return -EINVAL;
}
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
ret = regmap_read(cs42l43->regmap, reg, val);
if (ret) {
dev_err(priv->dev,
"Failed to cache decimator settings: %d\n",
ret);
return ret;
}
regmap_update_bits(cs42l43->regmap, reg, mute | ramp, mute);
break;
case SND_SOC_DAPM_POST_PMU:
regmap_update_bits(cs42l43->regmap, reg, mute | ramp, *val);
break;
default:
break;
}
return 0;
}
static int cs42l43_adc_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
struct cs42l43 *cs42l43 = priv->core;
unsigned int mask = 1 << w->shift;
unsigned int val = 0;
int ret;
ret = cs42l43_mic_ev(w, kcontrol, event);
if (ret)
return ret;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
val = mask;
fallthrough;
case SND_SOC_DAPM_PRE_PMD:
priv->adc_ena &= ~mask;
priv->adc_ena |= val;
if (!priv->load_detect_running)
regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN3,
mask, val);
fallthrough;
default:
return 0;
}
}
static const struct snd_soc_dapm_widget cs42l43_widgets[] = {
SND_SOC_DAPM_SUPPLY("PLL", SND_SOC_NOPM, 0, 0, cs42l43_pll_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_INPUT("ADC1_IN1_P"),
SND_SOC_DAPM_INPUT("ADC1_IN1_N"),
SND_SOC_DAPM_INPUT("ADC1_IN2_P"),
SND_SOC_DAPM_INPUT("ADC1_IN2_N"),
SND_SOC_DAPM_INPUT("ADC2_IN_P"),
SND_SOC_DAPM_INPUT("ADC2_IN_N"),
SND_SOC_DAPM_INPUT("PDM1_DIN"),
SND_SOC_DAPM_INPUT("PDM2_DIN"),
SND_SOC_DAPM_MUX("ADC1 Input", SND_SOC_NOPM, 0, 0, &cs42l43_adc1_input_ctl),
SND_SOC_DAPM_PGA_E("ADC1", SND_SOC_NOPM, CS42L43_ADC1_EN_SHIFT, 0, NULL, 0,
cs42l43_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA_E("ADC2", SND_SOC_NOPM, CS42L43_ADC2_EN_SHIFT, 0, NULL, 0,
cs42l43_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA_E("PDM1L", CS42L43_BLOCK_EN3, CS42L43_PDM1_DIN_L_EN_SHIFT,
0, NULL, 0, cs42l43_mic_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("PDM1R", CS42L43_BLOCK_EN3, CS42L43_PDM1_DIN_R_EN_SHIFT,
0, NULL, 0, cs42l43_mic_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("PDM2L", CS42L43_BLOCK_EN3, CS42L43_PDM2_DIN_L_EN_SHIFT,
0, NULL, 0, cs42l43_mic_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("PDM2R", CS42L43_BLOCK_EN3, CS42L43_PDM2_DIN_R_EN_SHIFT,
0, NULL, 0, cs42l43_mic_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_MUX("Decimator 1 Mode", SND_SOC_NOPM, 0, 0,
&cs42l43_dec_mode_ctl[0]),
SND_SOC_DAPM_MUX("Decimator 2 Mode", SND_SOC_NOPM, 0, 0,
&cs42l43_dec_mode_ctl[1]),
SND_SOC_DAPM_PGA("Decimator 1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Decimator 2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Decimator 3", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Decimator 4", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("FSYNC", 0, CS42L43_ASP_CTRL, CS42L43_ASP_FSYNC_EN_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("BCLK", 1, CS42L43_ASP_CTRL, CS42L43_ASP_BCLK_EN_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_AIF_OUT("ASPTX1", NULL, 0,
CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH1_EN_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("ASPTX2", NULL, 1,
CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH2_EN_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("ASPTX3", NULL, 2,
CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH3_EN_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("ASPTX4", NULL, 3,
CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH4_EN_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("ASPTX5", NULL, 4,
CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH5_EN_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("ASPTX6", NULL, 5,
CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH6_EN_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("ASPRX1", NULL, 0,
CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH1_EN_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("ASPRX2", NULL, 1,
CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH2_EN_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("ASPRX3", NULL, 2,
CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH3_EN_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("ASPRX4", NULL, 3,
CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH4_EN_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("ASPRX5", NULL, 4,
CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH5_EN_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("ASPRX6", NULL, 5,
CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH6_EN_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("DP1TX1", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("DP1TX2", NULL, 1, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("DP1TX3", NULL, 2, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("DP1TX4", NULL, 3, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("DP2TX1", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("DP2TX2", NULL, 1, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("DP3TX1", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("DP3TX2", NULL, 1, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("DP4TX1", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("DP4TX2", NULL, 1, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("DP5RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("DP5RX2", NULL, 1, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("DP6RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("DP6RX2", NULL, 1, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("DP7RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("DP7RX2", NULL, 1, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-amp", 0, 0),
SND_SOC_DAPM_PGA_E("AMP1", CS42L43_BLOCK_EN10, CS42L43_AMP1_EN_SHIFT, 0, NULL, 0,
cs42l43_spkl_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("AMP2", CS42L43_BLOCK_EN10, CS42L43_AMP2_EN_SHIFT, 0, NULL, 0,
cs42l43_spkr_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_OUTPUT("AMP1_OUT_P"),
SND_SOC_DAPM_OUTPUT("AMP1_OUT_N"),
SND_SOC_DAPM_OUTPUT("AMP2_OUT_P"),
SND_SOC_DAPM_OUTPUT("AMP2_OUT_N"),
SND_SOC_DAPM_PGA("SPDIF", CS42L43_BLOCK_EN11, CS42L43_SPDIF_EN_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_OUTPUT("SPDIF_TX"),
SND_SOC_DAPM_PGA_E("HP", SND_SOC_NOPM, CS42L43_HP_EN_SHIFT, 0, NULL, 0,
cs42l43_hp_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_OUTPUT("AMP3_OUT"),
SND_SOC_DAPM_OUTPUT("AMP4_OUT"),
SND_SOC_DAPM_SIGGEN("Tone"),
SND_SOC_DAPM_SUPPLY("Tone Generator", CS42L43_BLOCK_EN9, CS42L43_TONE_EN_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_REG(snd_soc_dapm_pga, "Tone 1", CS42L43_TONE_CH1_CTRL,
CS42L43_TONE_SEL_SHIFT, CS42L43_TONE_SEL_MASK, 0xA, 0),
SND_SOC_DAPM_REG(snd_soc_dapm_pga, "Tone 2", CS42L43_TONE_CH2_CTRL,
CS42L43_TONE_SEL_SHIFT, CS42L43_TONE_SEL_MASK, 0xA, 0),
SND_SOC_DAPM_SUPPLY("ISRC1", CS42L43_BLOCK_EN5, CS42L43_ISRC1_BANK_EN_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ISRC2", CS42L43_BLOCK_EN5, CS42L43_ISRC2_BANK_EN_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1INT2", CS42L43_ISRC1_CTRL,
CS42L43_ISRC_INT2_EN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1INT1", CS42L43_ISRC1_CTRL,
CS42L43_ISRC_INT1_EN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC2", CS42L43_ISRC1_CTRL,
CS42L43_ISRC_DEC2_EN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC1", CS42L43_ISRC1_CTRL,
CS42L43_ISRC_DEC1_EN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2INT2", CS42L43_ISRC2_CTRL,
CS42L43_ISRC_INT2_EN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2INT1", CS42L43_ISRC2_CTRL,
CS42L43_ISRC_INT1_EN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2DEC2", CS42L43_ISRC2_CTRL,
CS42L43_ISRC_DEC2_EN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2DEC1", CS42L43_ISRC2_CTRL,
CS42L43_ISRC_DEC1_EN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ASRC_INT", CS42L43_BLOCK_EN4,
CS42L43_ASRC_INT_BANK_EN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ASRC_DEC", CS42L43_BLOCK_EN4,
CS42L43_ASRC_DEC_BANK_EN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ASRC_INT1", CS42L43_ASRC_INT_ENABLES,
CS42L43_ASRC_INT1_EN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ASRC_INT2", CS42L43_ASRC_INT_ENABLES,
CS42L43_ASRC_INT2_EN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ASRC_INT3", CS42L43_ASRC_INT_ENABLES,
CS42L43_ASRC_INT3_EN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ASRC_INT4", CS42L43_ASRC_INT_ENABLES,
CS42L43_ASRC_INT4_EN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ASRC_DEC1", CS42L43_ASRC_DEC_ENABLES,
CS42L43_ASRC_DEC1_EN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ASRC_DEC2", CS42L43_ASRC_DEC_ENABLES,
CS42L43_ASRC_DEC2_EN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ASRC_DEC3", CS42L43_ASRC_DEC_ENABLES,
CS42L43_ASRC_DEC3_EN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ASRC_DEC4", CS42L43_ASRC_DEC_ENABLES,
CS42L43_ASRC_DEC4_EN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("EQ Clock", CS42L43_BLOCK_EN7, CS42L43_EQ_EN_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA_E("EQ", CS42L43_START_EQZ0, CS42L43_START_FILTER_SHIFT,
0, NULL, 0, cs42l43_eq_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY("Mixer Core", CS42L43_BLOCK_EN6, CS42L43_MIXER_EN_SHIFT,
0, NULL, 0),
CS42L43_DAPM_MUX("ASPTX1", asptx1),
CS42L43_DAPM_MUX("ASPTX2", asptx2),
CS42L43_DAPM_MUX("ASPTX3", asptx3),
CS42L43_DAPM_MUX("ASPTX4", asptx4),
CS42L43_DAPM_MUX("ASPTX5", asptx5),
CS42L43_DAPM_MUX("ASPTX6", asptx6),
CS42L43_DAPM_MUX("DP1TX1", dp1tx1),
CS42L43_DAPM_MUX("DP1TX2", dp1tx2),
CS42L43_DAPM_MUX("DP1TX3", dp1tx3),
CS42L43_DAPM_MUX("DP1TX4", dp1tx4),
CS42L43_DAPM_MUX("DP2TX1", dp2tx1),
CS42L43_DAPM_MUX("DP2TX2", dp2tx2),
CS42L43_DAPM_MUX("DP3TX1", dp3tx1),
CS42L43_DAPM_MUX("DP3TX2", dp3tx2),
CS42L43_DAPM_MUX("DP4TX1", dp4tx1),
CS42L43_DAPM_MUX("DP4TX2", dp4tx2),
CS42L43_DAPM_MUX("ASRC INT1", asrcint1),
CS42L43_DAPM_MUX("ASRC INT2", asrcint2),
CS42L43_DAPM_MUX("ASRC INT3", asrcint3),
CS42L43_DAPM_MUX("ASRC INT4", asrcint4),
CS42L43_DAPM_MUX("ASRC DEC1", asrcdec1),
CS42L43_DAPM_MUX("ASRC DEC2", asrcdec2),
CS42L43_DAPM_MUX("ASRC DEC3", asrcdec3),
CS42L43_DAPM_MUX("ASRC DEC4", asrcdec4),
CS42L43_DAPM_MUX("ISRC1INT1", isrc1int1),
CS42L43_DAPM_MUX("ISRC1INT2", isrc1int2),
CS42L43_DAPM_MUX("ISRC1DEC1", isrc1dec1),
CS42L43_DAPM_MUX("ISRC1DEC2", isrc1dec2),
CS42L43_DAPM_MUX("ISRC2INT1", isrc2int1),
CS42L43_DAPM_MUX("ISRC2INT2", isrc2int2),
CS42L43_DAPM_MUX("ISRC2DEC1", isrc2dec1),
CS42L43_DAPM_MUX("ISRC2DEC2", isrc2dec2),
CS42L43_DAPM_MUX("SPDIF1", spdif1),
CS42L43_DAPM_MUX("SPDIF2", spdif2),
CS42L43_DAPM_MIXER("EQ1", eq1),
CS42L43_DAPM_MIXER("EQ2", eq2),
CS42L43_DAPM_MIXER("Speaker L", amp1),
CS42L43_DAPM_MIXER("Speaker R", amp2),
CS42L43_DAPM_MIXER("Headphone L", amp3),
CS42L43_DAPM_MIXER("Headphone R", amp4),
};
static const struct snd_soc_dapm_route cs42l43_routes[] = {
{ "ADC1_IN1_P", NULL, "PLL" },
{ "ADC1_IN1_N", NULL, "PLL" },
{ "ADC1_IN2_P", NULL, "PLL" },
{ "ADC1_IN2_N", NULL, "PLL" },
{ "ADC2_IN_P", NULL, "PLL" },
{ "ADC2_IN_N", NULL, "PLL" },
{ "PDM1_DIN", NULL, "PLL" },
{ "PDM2_DIN", NULL, "PLL" },
{ "AMP1_OUT_P", NULL, "PLL" },
{ "AMP1_OUT_N", NULL, "PLL" },
{ "AMP2_OUT_P", NULL, "PLL" },
{ "AMP2_OUT_N", NULL, "PLL" },
{ "SPDIF_TX", NULL, "PLL" },
{ "HP", NULL, "PLL" },
{ "AMP3_OUT", NULL, "PLL" },
{ "AMP4_OUT", NULL, "PLL" },
{ "Tone 1", NULL, "PLL" },
{ "Tone 2", NULL, "PLL" },
{ "ASP Playback", NULL, "PLL" },
{ "ASP Capture", NULL, "PLL" },
{ "DP1 Capture", NULL, "PLL" },
{ "DP2 Capture", NULL, "PLL" },
{ "DP3 Capture", NULL, "PLL" },
{ "DP4 Capture", NULL, "PLL" },
{ "DP5 Playback", NULL, "PLL" },
{ "DP6 Playback", NULL, "PLL" },
{ "DP7 Playback", NULL, "PLL" },
{ "ADC1 Input", "IN1", "ADC1_IN1_P" },
{ "ADC1 Input", "IN1", "ADC1_IN1_N" },
{ "ADC1 Input", "IN2", "ADC1_IN2_P" },
{ "ADC1 Input", "IN2", "ADC1_IN2_N" },
{ "ADC1", NULL, "ADC1 Input" },
{ "ADC2", NULL, "ADC2_IN_P" },
{ "ADC2", NULL, "ADC2_IN_N" },
{ "PDM1L", NULL, "PDM1_DIN" },
{ "PDM1R", NULL, "PDM1_DIN" },
{ "PDM2L", NULL, "PDM2_DIN" },
{ "PDM2R", NULL, "PDM2_DIN" },
{ "Decimator 1 Mode", "PDM", "PDM1L" },
{ "Decimator 1 Mode", "ADC", "ADC1" },
{ "Decimator 2 Mode", "PDM", "PDM1R" },
{ "Decimator 2 Mode", "ADC", "ADC2" },
{ "Decimator 1", NULL, "Decimator 1 Mode" },
{ "Decimator 2", NULL, "Decimator 2 Mode" },
{ "Decimator 3", NULL, "PDM2L" },
{ "Decimator 4", NULL, "PDM2R" },
{ "ASP Capture", NULL, "ASPTX1" },
{ "ASP Capture", NULL, "ASPTX2" },
{ "ASP Capture", NULL, "ASPTX3" },
{ "ASP Capture", NULL, "ASPTX4" },
{ "ASP Capture", NULL, "ASPTX5" },
{ "ASP Capture", NULL, "ASPTX6" },
{ "ASPTX1", NULL, "BCLK" },
{ "ASPTX2", NULL, "BCLK" },
{ "ASPTX3", NULL, "BCLK" },
{ "ASPTX4", NULL, "BCLK" },
{ "ASPTX5", NULL, "BCLK" },
{ "ASPTX6", NULL, "BCLK" },
{ "ASPRX1", NULL, "ASP Playback" },
{ "ASPRX2", NULL, "ASP Playback" },
{ "ASPRX3", NULL, "ASP Playback" },
{ "ASPRX4", NULL, "ASP Playback" },
{ "ASPRX5", NULL, "ASP Playback" },
{ "ASPRX6", NULL, "ASP Playback" },
{ "ASPRX1", NULL, "BCLK" },
{ "ASPRX2", NULL, "BCLK" },
{ "ASPRX3", NULL, "BCLK" },
{ "ASPRX4", NULL, "BCLK" },
{ "ASPRX5", NULL, "BCLK" },
{ "ASPRX6", NULL, "BCLK" },
{ "DP1 Capture", NULL, "DP1TX1" },
{ "DP1 Capture", NULL, "DP1TX2" },
{ "DP1 Capture", NULL, "DP1TX3" },
{ "DP1 Capture", NULL, "DP1TX4" },
{ "DP2 Capture", NULL, "DP2TX1" },
{ "DP2 Capture", NULL, "DP2TX2" },
{ "DP3 Capture", NULL, "DP3TX1" },
{ "DP3 Capture", NULL, "DP3TX2" },
{ "DP4 Capture", NULL, "DP4TX1" },
{ "DP4 Capture", NULL, "DP4TX2" },
{ "DP5RX1", NULL, "DP5 Playback" },
{ "DP5RX2", NULL, "DP5 Playback" },
{ "DP6RX1", NULL, "DP6 Playback" },
{ "DP6RX2", NULL, "DP6 Playback" },
{ "DP7RX1", NULL, "DP7 Playback" },
{ "DP7RX2", NULL, "DP7 Playback" },
{ "AMP1", NULL, "vdd-amp" },
{ "AMP2", NULL, "vdd-amp" },
{ "AMP1_OUT_P", NULL, "AMP1" },
{ "AMP1_OUT_N", NULL, "AMP1" },
{ "AMP2_OUT_P", NULL, "AMP2" },
{ "AMP2_OUT_N", NULL, "AMP2" },
{ "SPDIF_TX", NULL, "SPDIF" },
{ "AMP3_OUT", NULL, "HP" },
{ "AMP4_OUT", NULL, "HP" },
{ "Tone 1", NULL, "Tone" },
{ "Tone 1", NULL, "Tone Generator" },
{ "Tone 2", NULL, "Tone" },
{ "Tone 2", NULL, "Tone Generator" },
{ "ISRC1INT2", NULL, "ISRC1" },
{ "ISRC1INT1", NULL, "ISRC1" },
{ "ISRC1DEC2", NULL, "ISRC1" },
{ "ISRC1DEC1", NULL, "ISRC1" },
{ "ISRC2INT2", NULL, "ISRC2" },
{ "ISRC2INT1", NULL, "ISRC2" },
{ "ISRC2DEC2", NULL, "ISRC2" },
{ "ISRC2DEC1", NULL, "ISRC2" },
{ "ASRC_INT1", NULL, "ASRC_INT" },
{ "ASRC_INT2", NULL, "ASRC_INT" },
{ "ASRC_INT3", NULL, "ASRC_INT" },
{ "ASRC_INT4", NULL, "ASRC_INT" },
{ "ASRC_DEC1", NULL, "ASRC_DEC" },
{ "ASRC_DEC2", NULL, "ASRC_DEC" },
{ "ASRC_DEC3", NULL, "ASRC_DEC" },
{ "ASRC_DEC4", NULL, "ASRC_DEC" },
{ "EQ", NULL, "EQ Clock" },
CS42L43_MUX_ROUTES("ASPTX1", "ASPTX1"),
CS42L43_MUX_ROUTES("ASPTX2", "ASPTX2"),
CS42L43_MUX_ROUTES("ASPTX3", "ASPTX3"),
CS42L43_MUX_ROUTES("ASPTX4", "ASPTX4"),
CS42L43_MUX_ROUTES("ASPTX5", "ASPTX5"),
CS42L43_MUX_ROUTES("ASPTX6", "ASPTX6"),
CS42L43_MUX_ROUTES("DP1TX1", "DP1TX1"),
CS42L43_MUX_ROUTES("DP1TX2", "DP1TX2"),
CS42L43_MUX_ROUTES("DP1TX3", "DP1TX3"),
CS42L43_MUX_ROUTES("DP1TX4", "DP1TX4"),
CS42L43_MUX_ROUTES("DP2TX1", "DP2TX1"),
CS42L43_MUX_ROUTES("DP2TX2", "DP2TX2"),
CS42L43_MUX_ROUTES("DP3TX1", "DP3TX1"),
CS42L43_MUX_ROUTES("DP3TX2", "DP3TX2"),
CS42L43_MUX_ROUTES("DP4TX1", "DP4TX1"),
CS42L43_MUX_ROUTES("DP4TX2", "DP4TX2"),
CS42L43_MUX_ROUTES("ASRC INT1", "ASRC_INT1"),
CS42L43_MUX_ROUTES("ASRC INT2", "ASRC_INT2"),
CS42L43_MUX_ROUTES("ASRC INT3", "ASRC_INT3"),
CS42L43_MUX_ROUTES("ASRC INT4", "ASRC_INT4"),
CS42L43_MUX_ROUTES("ASRC DEC1", "ASRC_DEC1"),
CS42L43_MUX_ROUTES("ASRC DEC2", "ASRC_DEC2"),
CS42L43_MUX_ROUTES("ASRC DEC3", "ASRC_DEC3"),
CS42L43_MUX_ROUTES("ASRC DEC4", "ASRC_DEC4"),
CS42L43_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"),
CS42L43_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"),
CS42L43_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"),
CS42L43_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"),
CS42L43_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"),
CS42L43_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"),
CS42L43_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"),
CS42L43_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"),
CS42L43_MUX_ROUTES("SPDIF1", "SPDIF"),
CS42L43_MUX_ROUTES("SPDIF2", "SPDIF"),
CS42L43_MIXER_ROUTES("EQ1", "EQ"),
CS42L43_MIXER_ROUTES("EQ2", "EQ"),
CS42L43_MIXER_ROUTES("Speaker L", "AMP1"),
CS42L43_MIXER_ROUTES("Speaker R", "AMP2"),
CS42L43_MIXER_ROUTES("Headphone L", "HP"),
CS42L43_MIXER_ROUTES("Headphone R", "HP"),
};
static int cs42l43_set_sysclk(struct snd_soc_component *component, int clk_id,
int src, unsigned int freq, int dir)
{
struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
struct cs42l43 *cs42l43 = priv->core;
int ret;
mutex_lock(&cs42l43->pll_lock);
ret = cs42l43_set_pll(priv, src, freq);
mutex_unlock(&cs42l43->pll_lock);
return ret;
}
static int cs42l43_component_probe(struct snd_soc_component *component)
{
struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
struct cs42l43 *cs42l43 = priv->core;
snd_soc_component_init_regmap(component, cs42l43->regmap);
cs42l43_mask_to_slots(priv, CS42L43_DEFAULT_SLOTS, priv->tx_slots);
cs42l43_mask_to_slots(priv, CS42L43_DEFAULT_SLOTS, priv->rx_slots);
priv->component = component;
priv->constraint = cs42l43_constraint;
return 0;
}
static const struct snd_soc_component_driver cs42l43_component_drv = {
.name = "cs42l43-codec",
.probe = cs42l43_component_probe,
.set_sysclk = cs42l43_set_sysclk,
.set_jack = cs42l43_set_jack,
.endianness = 1,
.controls = cs42l43_controls,
.num_controls = ARRAY_SIZE(cs42l43_controls),
.dapm_widgets = cs42l43_widgets,
.num_dapm_widgets = ARRAY_SIZE(cs42l43_widgets),
.dapm_routes = cs42l43_routes,
.num_dapm_routes = ARRAY_SIZE(cs42l43_routes),
};
struct cs42l43_irq {
unsigned int irq;
const char *name;
irq_handler_t handler;
};
static const struct cs42l43_irq cs42l43_irqs[] = {
{ CS42L43_PLL_LOST_LOCK, "pll lost lock", cs42l43_pll_lost_lock },
{ CS42L43_PLL_READY, "pll ready", cs42l43_pll_ready },
{ CS42L43_HP_STARTUP_DONE, "hp startup", cs42l43_hp_startup },
{ CS42L43_HP_SHUTDOWN_DONE, "hp shutdown", cs42l43_hp_shutdown },
{ CS42L43_HSDET_DONE, "type detect", cs42l43_type_detect },
{ CS42L43_TIPSENSE_UNPLUG_PDET, "tip sense unplug", cs42l43_tip_sense },
{ CS42L43_TIPSENSE_PLUG_PDET, "tip sense plug", cs42l43_tip_sense },
{ CS42L43_DC_DETECT1_TRUE, "button press", cs42l43_button_press },
{ CS42L43_DC_DETECT1_FALSE, "button release", cs42l43_button_release },
{ CS42L43_HSBIAS_CLAMPED, "hsbias detect clamp", cs42l43_bias_detect_clamp },
{ CS42L43_AMP2_CLK_STOP_FAULT, "spkr clock stop", cs42l43_spkr_clock_stop },
{ CS42L43_AMP1_CLK_STOP_FAULT, "spkl clock stop", cs42l43_spkl_clock_stop },
{ CS42L43_AMP2_VDDSPK_FAULT, "spkr brown out", cs42l43_spkr_brown_out },
{ CS42L43_AMP1_VDDSPK_FAULT, "spkl brown out", cs42l43_spkl_brown_out },
{ CS42L43_AMP2_SHUTDOWN_DONE, "spkr shutdown", cs42l43_spkr_shutdown },
{ CS42L43_AMP1_SHUTDOWN_DONE, "spkl shutdown", cs42l43_spkl_shutdown },
{ CS42L43_AMP2_STARTUP_DONE, "spkr startup", cs42l43_spkr_startup },
{ CS42L43_AMP1_STARTUP_DONE, "spkl startup", cs42l43_spkl_startup },
{ CS42L43_AMP2_THERM_SHDN, "spkr thermal shutdown", cs42l43_spkr_therm_shutdown },
{ CS42L43_AMP1_THERM_SHDN, "spkl thermal shutdown", cs42l43_spkl_therm_shutdown },
{ CS42L43_AMP2_THERM_WARN, "spkr thermal warning", cs42l43_spkr_therm_warm },
{ CS42L43_AMP1_THERM_WARN, "spkl thermal warning", cs42l43_spkl_therm_warm },
{ CS42L43_AMP2_SCDET, "spkr short circuit", cs42l43_spkr_sc_detect },
{ CS42L43_AMP1_SCDET, "spkl short circuit", cs42l43_spkl_sc_detect },
{ CS42L43_HP_ILIMIT, "hp ilimit", cs42l43_hp_ilimit },
{ CS42L43_HP_LOADDET_DONE, "load detect done", cs42l43_load_detect },
};
static int cs42l43_request_irq(struct cs42l43_codec *priv,
struct irq_domain *dom, const char * const name,
unsigned int irq, irq_handler_t handler,
unsigned long flags)
{
int ret;
ret = irq_create_mapping(dom, irq);
if (ret < 0)
return dev_err_probe(priv->dev, ret, "Failed to map IRQ %s\n", name);
dev_dbg(priv->dev, "Request IRQ %d for %s\n", ret, name);
ret = devm_request_threaded_irq(priv->dev, ret, NULL, handler,
IRQF_ONESHOT | flags, name, priv);
if (ret)
return dev_err_probe(priv->dev, ret, "Failed to request IRQ %s\n", name);
return 0;
}
static int cs42l43_shutter_irq(struct cs42l43_codec *priv,
struct irq_domain *dom, unsigned int shutter,
const char * const open_name,
const char * const close_name,
irq_handler_t handler)
{
unsigned int open_irq, close_irq;
int ret;
switch (shutter) {
case 0x1:
dev_warn(priv->dev, "Manual shutters, notifications not available\n");
return 0;
case 0x2:
open_irq = CS42L43_GPIO1_RISE;
close_irq = CS42L43_GPIO1_FALL;
break;
case 0x4:
open_irq = CS42L43_GPIO2_RISE;
close_irq = CS42L43_GPIO2_FALL;
break;
case 0x8:
open_irq = CS42L43_GPIO3_RISE;
close_irq = CS42L43_GPIO3_FALL;
break;
default:
return 0;
}
ret = cs42l43_request_irq(priv, dom, close_name, close_irq, handler, IRQF_SHARED);
if (ret)
return ret;
return cs42l43_request_irq(priv, dom, open_name, open_irq, handler, IRQF_SHARED);
}
static int cs42l43_codec_probe(struct platform_device *pdev)
{
struct cs42l43 *cs42l43 = dev_get_drvdata(pdev->dev.parent);
struct cs42l43_codec *priv;
struct irq_domain *dom;
unsigned int val;
int i, ret;
dom = irq_find_matching_fwnode(dev_fwnode(cs42l43->dev), DOMAIN_BUS_ANY);
if (!dom)
return -EPROBE_DEFER;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->dev = &pdev->dev;
priv->core = cs42l43;
platform_set_drvdata(pdev, priv);
mutex_init(&priv->jack_lock);
mutex_init(&priv->spk_vu_lock);
init_completion(&priv->hp_startup);
init_completion(&priv->hp_shutdown);
init_completion(&priv->spkr_shutdown);
init_completion(&priv->spkl_shutdown);
init_completion(&priv->spkr_startup);
init_completion(&priv->spkl_startup);
init_completion(&priv->pll_ready);
init_completion(&priv->type_detect);
init_completion(&priv->load_detect);
INIT_DELAYED_WORK(&priv->tip_sense_work, cs42l43_tip_sense_work);
INIT_DELAYED_WORK(&priv->bias_sense_timeout, cs42l43_bias_sense_timeout);
INIT_DELAYED_WORK(&priv->button_press_work, cs42l43_button_press_work);
INIT_WORK(&priv->button_release_work, cs42l43_button_release_work);
pm_runtime_set_autosuspend_delay(priv->dev, 100);
pm_runtime_use_autosuspend(priv->dev);
pm_runtime_set_active(priv->dev);
pm_runtime_get_noresume(priv->dev);
devm_pm_runtime_enable(priv->dev);
for (i = 0; i < ARRAY_SIZE(cs42l43_irqs); i++) {
ret = cs42l43_request_irq(priv, dom, cs42l43_irqs[i].name,
cs42l43_irqs[i].irq,
cs42l43_irqs[i].handler, 0);
if (ret)
goto err_pm;
}
ret = regmap_read(cs42l43->regmap, CS42L43_SHUTTER_CONTROL, &val);
if (ret) {
dev_err(priv->dev, "Failed to check shutter source: %d\n", ret);
goto err_pm;
}
ret = cs42l43_shutter_irq(priv, dom, val & CS42L43_MIC_SHUTTER_CFG_MASK,
"mic shutter open", "mic shutter close",
cs42l43_mic_shutter);
if (ret)
goto err_pm;
ret = cs42l43_shutter_irq(priv, dom, (val & CS42L43_SPK_SHUTTER_CFG_MASK) >>
CS42L43_SPK_SHUTTER_CFG_SHIFT,
"spk shutter open", "spk shutter close",
cs42l43_spk_shutter);
if (ret)
goto err_pm;
// Don't use devm as we need to get against the MFD device
priv->mclk = clk_get_optional(cs42l43->dev, "mclk");
if (IS_ERR(priv->mclk)) {
ret = PTR_ERR(priv->mclk);
dev_err_probe(priv->dev, ret, "Failed to get mclk\n");
goto err_pm;
}
ret = devm_snd_soc_register_component(priv->dev, &cs42l43_component_drv,
cs42l43_dais, ARRAY_SIZE(cs42l43_dais));
if (ret) {
dev_err_probe(priv->dev, ret, "Failed to register component\n");
goto err_clk;
}
pm_runtime_mark_last_busy(priv->dev);
pm_runtime_put_autosuspend(priv->dev);
return 0;
err_clk:
clk_put(priv->mclk);
err_pm:
pm_runtime_put_sync(priv->dev);
return ret;
}
static int cs42l43_codec_remove(struct platform_device *pdev)
{
struct cs42l43_codec *priv = platform_get_drvdata(pdev);
clk_put(priv->mclk);
return 0;
}
static int cs42l43_codec_runtime_resume(struct device *dev)
{
struct cs42l43_codec *priv = dev_get_drvdata(dev);
dev_dbg(priv->dev, "Runtime resume\n");
// Toggle the speaker volume update incase the speaker volume was synced
cs42l43_spk_vu_sync(priv);
return 0;
}
DEFINE_RUNTIME_DEV_PM_OPS(cs42l43_codec_pm_ops, NULL,
cs42l43_codec_runtime_resume, NULL);
static const struct platform_device_id cs42l43_codec_id_table[] = {
{ "cs42l43-codec", },
{}
};
MODULE_DEVICE_TABLE(platform, cs42l43_codec_id_table);
static struct platform_driver cs42l43_codec_driver = {
.driver = {
.name = "cs42l43-codec",
.pm = &cs42l43_codec_pm_ops,
},
.probe = cs42l43_codec_probe,
.remove = cs42l43_codec_remove,
.id_table = cs42l43_codec_id_table,
};
module_platform_driver(cs42l43_codec_driver);
MODULE_IMPORT_NS(SND_SOC_CS42L43);
MODULE_DESCRIPTION("CS42L43 CODEC Driver");
MODULE_AUTHOR("Charles Keepax <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cs42l43.c |
// SPDX-License-Identifier: GPL-2.0
//
// mt6359-accdet.c -- ALSA SoC mt6359 accdet driver
//
// Copyright (C) 2021 MediaTek Inc.
// Author: Argus Lin <[email protected]>
//
#include <linux/of_gpio.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_device.h>
#include <linux/of_address.h>
#include <linux/input.h>
#include <linux/kthread.h>
#include <linux/io.h>
#include <linux/sched/clock.h>
#include <linux/workqueue.h>
#include <linux/timer.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/irqdomain.h>
#include <linux/irq.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include <sound/jack.h>
#include <linux/mfd/mt6397/core.h>
#include "mt6359-accdet.h"
#include "mt6359.h"
/* global variable definitions */
#define REGISTER_VAL(x) ((x) - 1)
/* mt6359 accdet capability */
#define ACCDET_PMIC_EINT_IRQ BIT(0)
#define ACCDET_AP_GPIO_EINT BIT(1)
#define ACCDET_PMIC_EINT0 BIT(2)
#define ACCDET_PMIC_EINT1 BIT(3)
#define ACCDET_PMIC_BI_EINT BIT(4)
#define ACCDET_PMIC_GPIO_TRIG_EINT BIT(5)
#define ACCDET_PMIC_INVERTER_TRIG_EINT BIT(6)
#define ACCDET_PMIC_RSV_EINT BIT(7)
#define ACCDET_THREE_KEY BIT(8)
#define ACCDET_FOUR_KEY BIT(9)
#define ACCDET_TRI_KEY_CDD BIT(10)
#define ACCDET_RSV_KEY BIT(11)
#define ACCDET_ANALOG_FASTDISCHARGE BIT(12)
#define ACCDET_DIGITAL_FASTDISCHARGE BIT(13)
#define ACCDET_AD_FASTDISCHRAGE BIT(14)
static struct platform_driver mt6359_accdet_driver;
static const struct snd_soc_component_driver mt6359_accdet_soc_driver;
/* local function declaration */
static void accdet_set_debounce(struct mt6359_accdet *priv, int state,
unsigned int debounce);
static unsigned int adjust_eint_analog_setting(struct mt6359_accdet *priv);
static void config_digital_init_by_mode(struct mt6359_accdet *priv);
static void config_eint_init_by_mode(struct mt6359_accdet *priv);
static inline void mt6359_accdet_init(struct mt6359_accdet *priv);
static unsigned int mt6359_accdet_jd_setting(struct mt6359_accdet *priv);
static void mt6359_accdet_recover_jd_setting(struct mt6359_accdet *priv);
static void mt6359_accdet_jack_report(struct mt6359_accdet *priv);
static void recover_eint_analog_setting(struct mt6359_accdet *priv);
static void recover_eint_digital_setting(struct mt6359_accdet *priv);
static void recover_eint_setting(struct mt6359_accdet *priv);
static unsigned int adjust_eint_analog_setting(struct mt6359_accdet *priv)
{
if (priv->data->eint_detect_mode == 0x3 ||
priv->data->eint_detect_mode == 0x4) {
/* ESD switches off */
regmap_update_bits(priv->regmap,
RG_ACCDETSPARE_ADDR, 1 << 8, 0);
}
if (priv->data->eint_detect_mode == 0x4) {
if (priv->caps & ACCDET_PMIC_EINT0) {
/* enable RG_EINT0CONFIGACCDET */
regmap_update_bits(priv->regmap,
RG_EINT0CONFIGACCDET_ADDR,
RG_EINT0CONFIGACCDET_MASK_SFT,
BIT(RG_EINT0CONFIGACCDET_SFT));
} else if (priv->caps & ACCDET_PMIC_EINT1) {
/* enable RG_EINT1CONFIGACCDET */
regmap_update_bits(priv->regmap,
RG_EINT1CONFIGACCDET_ADDR,
RG_EINT1CONFIGACCDET_MASK_SFT,
BIT(RG_EINT1CONFIGACCDET_SFT));
}
if (priv->data->eint_use_ext_res == 0x3 ||
priv->data->eint_use_ext_res == 0x4) {
/*select 500k, use internal resistor */
regmap_update_bits(priv->regmap,
RG_EINT0HIRENB_ADDR,
RG_EINT0HIRENB_MASK_SFT,
BIT(RG_EINT0HIRENB_SFT));
}
}
return 0;
}
static unsigned int adjust_eint_digital_setting(struct mt6359_accdet *priv)
{
if (priv->caps & ACCDET_PMIC_EINT0) {
/* disable inverter */
regmap_update_bits(priv->regmap,
ACCDET_EINT0_INVERTER_SW_EN_ADDR,
ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT, 0);
} else if (priv->caps & ACCDET_PMIC_EINT1) {
/* disable inverter */
regmap_update_bits(priv->regmap,
ACCDET_EINT1_INVERTER_SW_EN_ADDR,
ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT, 0);
}
if (priv->data->eint_detect_mode == 0x4) {
if (priv->caps & ACCDET_PMIC_EINT0) {
/* set DA stable signal */
regmap_update_bits(priv->regmap,
ACCDET_DA_STABLE_ADDR,
ACCDET_EINT0_CEN_STABLE_MASK_SFT, 0);
} else if (priv->caps & ACCDET_PMIC_EINT1) {
/* set DA stable signal */
regmap_update_bits(priv->regmap,
ACCDET_DA_STABLE_ADDR,
ACCDET_EINT1_CEN_STABLE_MASK_SFT, 0);
}
}
return 0;
}
static unsigned int mt6359_accdet_jd_setting(struct mt6359_accdet *priv)
{
if (priv->jd_sts == M_PLUG_IN) {
/* adjust digital setting */
adjust_eint_digital_setting(priv);
/* adjust analog setting */
adjust_eint_analog_setting(priv);
} else if (priv->jd_sts == M_PLUG_OUT) {
/* set debounce to 1ms */
accdet_set_debounce(priv, eint_state000,
priv->data->pwm_deb->eint_debounce0);
} else {
dev_dbg(priv->dev, "should not be here %s()\n", __func__);
}
return 0;
}
static void recover_eint_analog_setting(struct mt6359_accdet *priv)
{
if (priv->data->eint_detect_mode == 0x3 ||
priv->data->eint_detect_mode == 0x4) {
/* ESD switches on */
regmap_update_bits(priv->regmap, RG_ACCDETSPARE_ADDR,
1 << 8, 1 << 8);
}
if (priv->data->eint_detect_mode == 0x4) {
if (priv->caps & ACCDET_PMIC_EINT0) {
/* disable RG_EINT0CONFIGACCDET */
regmap_update_bits(priv->regmap,
RG_EINT0CONFIGACCDET_ADDR,
RG_EINT0CONFIGACCDET_MASK_SFT, 0);
} else if (priv->caps & ACCDET_PMIC_EINT1) {
/* disable RG_EINT1CONFIGACCDET */
regmap_update_bits(priv->regmap,
RG_EINT1CONFIGACCDET_ADDR,
RG_EINT1CONFIGACCDET_MASK_SFT, 0);
}
regmap_update_bits(priv->regmap, RG_EINT0HIRENB_ADDR,
RG_EINT0HIRENB_MASK_SFT, 0);
}
}
static void recover_eint_digital_setting(struct mt6359_accdet *priv)
{
if (priv->caps & ACCDET_PMIC_EINT0) {
regmap_update_bits(priv->regmap,
ACCDET_EINT0_M_SW_EN_ADDR,
ACCDET_EINT0_M_SW_EN_MASK_SFT, 0);
} else if (priv->caps & ACCDET_PMIC_EINT1) {
regmap_update_bits(priv->regmap,
ACCDET_EINT1_M_SW_EN_ADDR,
ACCDET_EINT1_M_SW_EN_MASK_SFT, 0);
}
if (priv->data->eint_detect_mode == 0x4) {
/* enable eint0cen */
if (priv->caps & ACCDET_PMIC_EINT0) {
/* enable eint0cen */
regmap_update_bits(priv->regmap,
ACCDET_DA_STABLE_ADDR,
ACCDET_EINT0_CEN_STABLE_MASK_SFT,
BIT(ACCDET_EINT0_CEN_STABLE_SFT));
} else if (priv->caps & ACCDET_PMIC_EINT1) {
/* enable eint1cen */
regmap_update_bits(priv->regmap,
ACCDET_DA_STABLE_ADDR,
ACCDET_EINT1_CEN_STABLE_MASK_SFT,
BIT(ACCDET_EINT1_CEN_STABLE_SFT));
}
}
if (priv->data->eint_detect_mode != 0x1) {
if (priv->caps & ACCDET_PMIC_EINT0) {
/* enable inverter */
regmap_update_bits(priv->regmap,
ACCDET_EINT0_INVERTER_SW_EN_ADDR,
ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT,
BIT(ACCDET_EINT0_INVERTER_SW_EN_SFT));
} else if (priv->caps & ACCDET_PMIC_EINT1) {
/* enable inverter */
regmap_update_bits(priv->regmap,
ACCDET_EINT1_INVERTER_SW_EN_ADDR,
ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT,
BIT(ACCDET_EINT1_INVERTER_SW_EN_SFT));
}
}
}
static void recover_eint_setting(struct mt6359_accdet *priv)
{
if (priv->jd_sts == M_PLUG_OUT) {
recover_eint_analog_setting(priv);
recover_eint_digital_setting(priv);
}
}
static void mt6359_accdet_recover_jd_setting(struct mt6359_accdet *priv)
{
int ret;
unsigned int value = 0;
regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR,
ACCDET_IRQ_CLR_MASK_SFT, BIT(ACCDET_IRQ_CLR_SFT));
usleep_range(200, 300);
ret = regmap_read_poll_timeout(priv->regmap,
ACCDET_IRQ_ADDR,
value,
(value & ACCDET_IRQ_MASK_SFT) == 0,
0,
1000);
if (ret)
dev_warn(priv->dev, "%s(), ret %d\n", __func__, ret);
/* clear accdet int, modify for fix interrupt trigger twice error */
regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR,
ACCDET_IRQ_CLR_MASK_SFT, 0);
regmap_update_bits(priv->regmap, RG_INT_STATUS_ACCDET_ADDR,
RG_INT_STATUS_ACCDET_MASK_SFT,
BIT(RG_INT_STATUS_ACCDET_SFT));
/* recover accdet debounce0,3 */
accdet_set_debounce(priv, accdet_state000,
priv->data->pwm_deb->debounce0);
accdet_set_debounce(priv, accdet_state001,
priv->data->pwm_deb->debounce1);
accdet_set_debounce(priv, accdet_state011,
priv->data->pwm_deb->debounce3);
priv->jack_type = 0;
priv->btn_type = 0;
priv->accdet_status = 0x3;
mt6359_accdet_jack_report(priv);
}
static void accdet_set_debounce(struct mt6359_accdet *priv, int state,
unsigned int debounce)
{
switch (state) {
case accdet_state000:
regmap_write(priv->regmap, ACCDET_DEBOUNCE0_ADDR, debounce);
break;
case accdet_state001:
regmap_write(priv->regmap, ACCDET_DEBOUNCE1_ADDR, debounce);
break;
case accdet_state010:
regmap_write(priv->regmap, ACCDET_DEBOUNCE2_ADDR, debounce);
break;
case accdet_state011:
regmap_write(priv->regmap, ACCDET_DEBOUNCE3_ADDR, debounce);
break;
case accdet_auxadc:
regmap_write(priv->regmap,
ACCDET_CONNECT_AUXADC_TIME_DIG_ADDR, debounce);
break;
case eint_state000:
regmap_update_bits(priv->regmap, ACCDET_EINT_DEBOUNCE0_ADDR,
0xF << ACCDET_EINT_DEBOUNCE0_SFT,
debounce << ACCDET_EINT_DEBOUNCE0_SFT);
break;
case eint_state001:
regmap_update_bits(priv->regmap, ACCDET_EINT_DEBOUNCE1_ADDR,
0xF << ACCDET_EINT_DEBOUNCE1_SFT,
debounce << ACCDET_EINT_DEBOUNCE1_SFT);
break;
case eint_state010:
regmap_update_bits(priv->regmap, ACCDET_EINT_DEBOUNCE2_ADDR,
0xF << ACCDET_EINT_DEBOUNCE2_SFT,
debounce << ACCDET_EINT_DEBOUNCE2_SFT);
break;
case eint_state011:
regmap_update_bits(priv->regmap, ACCDET_EINT_DEBOUNCE3_ADDR,
0xF << ACCDET_EINT_DEBOUNCE3_SFT,
debounce << ACCDET_EINT_DEBOUNCE3_SFT);
break;
case eint_inverter_state000:
regmap_write(priv->regmap, ACCDET_EINT_INVERTER_DEBOUNCE_ADDR,
debounce);
break;
default:
dev_warn(priv->dev, "Error: %s error state (%d)\n", __func__,
state);
break;
}
}
static void mt6359_accdet_jack_report(struct mt6359_accdet *priv)
{
int report = 0;
if (!priv->jack)
return;
report = priv->jack_type | priv->btn_type;
snd_soc_jack_report(priv->jack, report, MT6359_ACCDET_JACK_MASK);
}
static unsigned int check_button(struct mt6359_accdet *priv, unsigned int v)
{
if (priv->caps & ACCDET_FOUR_KEY) {
if (v < priv->data->four_key.down &&
v >= priv->data->four_key.up)
priv->btn_type = SND_JACK_BTN_1;
if (v < priv->data->four_key.up &&
v >= priv->data->four_key.voice)
priv->btn_type = SND_JACK_BTN_2;
if (v < priv->data->four_key.voice &&
v >= priv->data->four_key.mid)
priv->btn_type = SND_JACK_BTN_3;
if (v < priv->data->four_key.mid)
priv->btn_type = SND_JACK_BTN_0;
} else {
if (v < priv->data->three_key.down &&
v >= priv->data->three_key.up)
priv->btn_type = SND_JACK_BTN_1;
if (v < priv->data->three_key.up &&
v >= priv->data->three_key.mid)
priv->btn_type = SND_JACK_BTN_2;
if (v < priv->data->three_key.mid)
priv->btn_type = SND_JACK_BTN_0;
}
return 0;
}
static void is_key_pressed(struct mt6359_accdet *priv, bool pressed)
{
priv->btn_type = priv->jack_type & ~MT6359_ACCDET_BTN_MASK;
if (pressed)
check_button(priv, priv->cali_voltage);
}
static inline void check_jack_btn_type(struct mt6359_accdet *priv)
{
unsigned int val = 0;
regmap_read(priv->regmap, ACCDET_MEM_IN_ADDR, &val);
priv->accdet_status =
(val >> ACCDET_STATE_MEM_IN_OFFSET) & ACCDET_STATE_AB_MASK;
switch (priv->accdet_status) {
case 0:
if (priv->jack_type == SND_JACK_HEADSET)
is_key_pressed(priv, true);
else
priv->jack_type = SND_JACK_HEADPHONE;
break;
case 1:
if (priv->jack_type == SND_JACK_HEADSET) {
is_key_pressed(priv, false);
} else {
priv->jack_type = SND_JACK_HEADSET;
accdet_set_debounce(priv, eint_state011, 0x1);
}
break;
case 3:
default:
priv->jack_type = 0;
break;
}
}
static void mt6359_accdet_work(struct work_struct *work)
{
struct mt6359_accdet *priv =
container_of(work, struct mt6359_accdet, accdet_work);
mutex_lock(&priv->res_lock);
priv->pre_accdet_status = priv->accdet_status;
check_jack_btn_type(priv);
if (priv->jack_plugged &&
priv->pre_accdet_status != priv->accdet_status)
mt6359_accdet_jack_report(priv);
mutex_unlock(&priv->res_lock);
}
static void mt6359_accdet_jd_work(struct work_struct *work)
{
int ret;
unsigned int value = 0;
struct mt6359_accdet *priv =
container_of(work, struct mt6359_accdet, jd_work);
mutex_lock(&priv->res_lock);
if (priv->jd_sts == M_PLUG_IN) {
priv->jack_plugged = true;
/* set and clear initial bit every eint interrupt */
regmap_update_bits(priv->regmap, ACCDET_SEQ_INIT_ADDR,
ACCDET_SEQ_INIT_MASK_SFT,
BIT(ACCDET_SEQ_INIT_SFT));
regmap_update_bits(priv->regmap, ACCDET_SEQ_INIT_ADDR,
ACCDET_SEQ_INIT_MASK_SFT, 0);
ret = regmap_read_poll_timeout(priv->regmap,
ACCDET_SEQ_INIT_ADDR,
value,
(value & ACCDET_SEQ_INIT_MASK_SFT) == 0,
0,
1000);
if (ret)
dev_err(priv->dev, "%s(), ret %d\n", __func__, ret);
/* enable ACCDET unit */
regmap_update_bits(priv->regmap, ACCDET_SW_EN_ADDR,
ACCDET_SW_EN_MASK_SFT, BIT(ACCDET_SW_EN_SFT));
} else if (priv->jd_sts == M_PLUG_OUT) {
priv->jack_plugged = false;
accdet_set_debounce(priv, accdet_state011,
priv->data->pwm_deb->debounce3);
regmap_update_bits(priv->regmap, ACCDET_SW_EN_ADDR,
ACCDET_SW_EN_MASK_SFT, 0);
mt6359_accdet_recover_jd_setting(priv);
}
if (priv->caps & ACCDET_PMIC_EINT_IRQ)
recover_eint_setting(priv);
mutex_unlock(&priv->res_lock);
}
static irqreturn_t mt6359_accdet_irq(int irq, void *data)
{
struct mt6359_accdet *priv = data;
unsigned int irq_val = 0, val = 0, value = 0;
int ret;
mutex_lock(&priv->res_lock);
regmap_read(priv->regmap, ACCDET_IRQ_ADDR, &irq_val);
if (irq_val & ACCDET_IRQ_MASK_SFT) {
regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR,
ACCDET_IRQ_CLR_MASK_SFT,
BIT(ACCDET_IRQ_CLR_SFT));
ret = regmap_read_poll_timeout(priv->regmap,
ACCDET_IRQ_ADDR,
value,
(value & ACCDET_IRQ_MASK_SFT) == 0,
0,
1000);
if (ret) {
dev_err(priv->dev, "%s(), ret %d\n", __func__, ret);
mutex_unlock(&priv->res_lock);
return IRQ_NONE;
}
regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR,
ACCDET_IRQ_CLR_MASK_SFT, 0);
regmap_update_bits(priv->regmap, RG_INT_STATUS_ACCDET_ADDR,
RG_INT_STATUS_ACCDET_MASK_SFT,
BIT(RG_INT_STATUS_ACCDET_SFT));
queue_work(priv->accdet_workqueue, &priv->accdet_work);
} else {
if (irq_val & ACCDET_EINT0_IRQ_MASK_SFT) {
regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR,
ACCDET_EINT0_IRQ_CLR_MASK_SFT,
BIT(ACCDET_EINT0_IRQ_CLR_SFT));
ret = regmap_read_poll_timeout(priv->regmap,
ACCDET_IRQ_ADDR,
value,
(value & ACCDET_EINT0_IRQ_MASK_SFT) == 0,
0,
1000);
if (ret) {
dev_err(priv->dev, "%s(), ret %d\n", __func__,
ret);
mutex_unlock(&priv->res_lock);
return IRQ_NONE;
}
regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR,
ACCDET_EINT0_IRQ_CLR_MASK_SFT, 0);
regmap_update_bits(priv->regmap,
RG_INT_STATUS_ACCDET_ADDR,
RG_INT_STATUS_ACCDET_EINT0_MASK_SFT,
BIT(RG_INT_STATUS_ACCDET_EINT0_SFT));
}
if (irq_val & ACCDET_EINT1_IRQ_MASK_SFT) {
regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR,
ACCDET_EINT1_IRQ_CLR_MASK_SFT,
BIT(ACCDET_EINT1_IRQ_CLR_SFT));
ret = regmap_read_poll_timeout(priv->regmap,
ACCDET_IRQ_ADDR,
value,
(value & ACCDET_EINT1_IRQ_MASK_SFT) == 0,
0,
1000);
if (ret) {
dev_err(priv->dev, "%s(), ret %d\n", __func__,
ret);
mutex_unlock(&priv->res_lock);
return IRQ_NONE;
}
regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR,
ACCDET_EINT1_IRQ_CLR_MASK_SFT, 0);
regmap_update_bits(priv->regmap,
RG_INT_STATUS_ACCDET_ADDR,
RG_INT_STATUS_ACCDET_EINT1_MASK_SFT,
BIT(RG_INT_STATUS_ACCDET_EINT1_SFT));
}
/* get jack detection status */
regmap_read(priv->regmap, ACCDET_EINT0_MEM_IN_ADDR, &val);
priv->jd_sts = ((val >> ACCDET_EINT0_MEM_IN_SFT) &
ACCDET_EINT0_MEM_IN_MASK);
/* adjust eint digital/analog setting */
mt6359_accdet_jd_setting(priv);
queue_work(priv->jd_workqueue, &priv->jd_work);
}
mutex_unlock(&priv->res_lock);
return IRQ_HANDLED;
}
static int mt6359_accdet_parse_dt(struct mt6359_accdet *priv)
{
int ret;
struct device *dev = priv->dev;
struct device_node *node = NULL;
int pwm_deb[15] = {0};
unsigned int tmp = 0;
node = of_get_child_by_name(dev->parent->of_node, "accdet");
if (!node)
return -EINVAL;
ret = of_property_read_u32(node, "mediatek,mic-vol",
&priv->data->mic_vol);
if (ret)
priv->data->mic_vol = 8;
ret = of_property_read_u32(node, "mediatek,plugout-debounce",
&priv->data->plugout_deb);
if (ret)
priv->data->plugout_deb = 1;
ret = of_property_read_u32(node, "mediatek,mic-mode",
&priv->data->mic_mode);
if (ret)
priv->data->mic_mode = 2;
ret = of_property_read_u32_array(node, "mediatek,pwm-deb-setting",
pwm_deb, ARRAY_SIZE(pwm_deb));
/* debounce8(auxadc debounce) is default, needn't get from dts */
if (!ret)
memcpy(priv->data->pwm_deb, pwm_deb, sizeof(pwm_deb));
ret = of_property_read_u32(node, "mediatek,eint-level-pol",
&priv->data->eint_pol);
if (ret)
priv->data->eint_pol = 8;
ret = of_property_read_u32(node, "mediatek,eint-use-ap", &tmp);
if (ret)
tmp = 0;
if (tmp == 0)
priv->caps |= ACCDET_PMIC_EINT_IRQ;
else if (tmp == 1)
priv->caps |= ACCDET_AP_GPIO_EINT;
ret = of_property_read_u32(node, "mediatek,eint-detect-mode",
&priv->data->eint_detect_mode);
if (ret) {
/* eint detection mode equals to EINT HW Mode */
priv->data->eint_detect_mode = 0x4;
}
ret = of_property_read_u32(node, "mediatek,eint-num", &tmp);
if (ret)
tmp = 0;
if (tmp == 0)
priv->caps |= ACCDET_PMIC_EINT0;
else if (tmp == 1)
priv->caps |= ACCDET_PMIC_EINT1;
else if (tmp == 2)
priv->caps |= ACCDET_PMIC_BI_EINT;
ret = of_property_read_u32(node, "mediatek,eint-trig-mode",
&tmp);
if (ret)
tmp = 0;
if (tmp == 0)
priv->caps |= ACCDET_PMIC_GPIO_TRIG_EINT;
else if (tmp == 1)
priv->caps |= ACCDET_PMIC_INVERTER_TRIG_EINT;
ret = of_property_read_u32(node, "mediatek,eint-use-ext-res",
&priv->data->eint_use_ext_res);
if (ret) {
/* eint use internal resister */
priv->data->eint_use_ext_res = 0x0;
}
ret = of_property_read_u32(node, "mediatek,eint-comp-vth",
&priv->data->eint_comp_vth);
if (ret)
priv->data->eint_comp_vth = 0x0;
ret = of_property_read_u32(node, "mediatek,key-mode", &tmp);
if (ret)
tmp = 0;
if (tmp == 0) {
int three_key[4];
priv->caps |= ACCDET_THREE_KEY;
ret = of_property_read_u32_array(node,
"mediatek,three-key-thr",
three_key,
ARRAY_SIZE(three_key));
if (!ret)
memcpy(&priv->data->three_key, three_key + 1,
sizeof(struct three_key_threshold));
} else if (tmp == 1) {
int four_key[5];
priv->caps |= ACCDET_FOUR_KEY;
ret = of_property_read_u32_array(node,
"mediatek,four-key-thr",
four_key,
ARRAY_SIZE(four_key));
if (!ret) {
memcpy(&priv->data->four_key, four_key + 1,
sizeof(struct four_key_threshold));
} else {
dev_warn(priv->dev,
"accdet no 4-key-thrsh dts, use efuse\n");
}
} else if (tmp == 2) {
int three_key[4];
priv->caps |= ACCDET_TRI_KEY_CDD;
ret = of_property_read_u32_array(node,
"mediatek,tri-key-cdd-thr",
three_key,
ARRAY_SIZE(three_key));
if (!ret)
memcpy(&priv->data->three_key, three_key + 1,
sizeof(struct three_key_threshold));
}
of_node_put(node);
dev_warn(priv->dev, "accdet caps=%x\n", priv->caps);
return 0;
}
static void config_digital_init_by_mode(struct mt6359_accdet *priv)
{
/* enable eint cmpmem pwm */
regmap_write(priv->regmap, ACCDET_EINT_CMPMEN_PWM_THRESH_ADDR,
(priv->data->pwm_deb->eint_pwm_width << 4 |
priv->data->pwm_deb->eint_pwm_thresh));
/* DA signal stable */
if (priv->caps & ACCDET_PMIC_EINT0) {
regmap_write(priv->regmap, ACCDET_DA_STABLE_ADDR,
ACCDET_EINT0_STABLE_VAL);
} else if (priv->caps & ACCDET_PMIC_EINT1) {
regmap_write(priv->regmap, ACCDET_DA_STABLE_ADDR,
ACCDET_EINT1_STABLE_VAL);
}
/* after receive n+1 number, interrupt issued. */
regmap_update_bits(priv->regmap, ACCDET_EINT_M_PLUG_IN_NUM_ADDR,
ACCDET_EINT_M_PLUG_IN_NUM_MASK_SFT,
BIT(ACCDET_EINT_M_PLUG_IN_NUM_SFT));
/* setting HW mode, enable digital fast discharge
* if use EINT0 & EINT1 detection, please modify
* ACCDET_HWMODE_EN_ADDR[2:1]
*/
regmap_write(priv->regmap, ACCDET_HWMODE_EN_ADDR, 0x100);
regmap_update_bits(priv->regmap, ACCDET_EINT_M_DETECT_EN_ADDR,
ACCDET_EINT_M_DETECT_EN_MASK_SFT, 0);
/* enable PWM */
regmap_write(priv->regmap, ACCDET_CMP_PWM_EN_ADDR, 0x67);
/* enable inverter detection */
if (priv->data->eint_detect_mode == 0x1) {
/* disable inverter detection */
if (priv->caps & ACCDET_PMIC_EINT0) {
regmap_update_bits(priv->regmap,
ACCDET_EINT0_INVERTER_SW_EN_ADDR,
ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT,
0);
} else if (priv->caps & ACCDET_PMIC_EINT1) {
regmap_update_bits(priv->regmap,
ACCDET_EINT1_INVERTER_SW_EN_ADDR,
ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT,
0);
}
} else {
if (priv->caps & ACCDET_PMIC_EINT0) {
regmap_update_bits(priv->regmap,
ACCDET_EINT0_INVERTER_SW_EN_ADDR,
ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT,
BIT(ACCDET_EINT0_INVERTER_SW_EN_SFT));
} else if (priv->caps & ACCDET_PMIC_EINT1) {
regmap_update_bits(priv->regmap,
ACCDET_EINT1_INVERTER_SW_EN_ADDR,
ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT,
BIT(ACCDET_EINT1_INVERTER_SW_EN_SFT));
}
}
}
static void config_eint_init_by_mode(struct mt6359_accdet *priv)
{
unsigned int val = 0;
if (priv->caps & ACCDET_PMIC_EINT0) {
regmap_update_bits(priv->regmap, RG_EINT0EN_ADDR,
RG_EINT0EN_MASK_SFT, BIT(RG_EINT0EN_SFT));
} else if (priv->caps & ACCDET_PMIC_EINT1) {
regmap_update_bits(priv->regmap, RG_EINT1EN_ADDR,
RG_EINT1EN_MASK_SFT, BIT(RG_EINT1EN_SFT));
}
/* ESD switches on */
regmap_update_bits(priv->regmap, RG_ACCDETSPARE_ADDR,
1 << 8, 1 << 8);
/* before playback, set NCP pull low before nagative voltage */
regmap_update_bits(priv->regmap, RG_NCP_PDDIS_EN_ADDR,
RG_NCP_PDDIS_EN_MASK_SFT, BIT(RG_NCP_PDDIS_EN_SFT));
if (priv->data->eint_detect_mode == 0x1 ||
priv->data->eint_detect_mode == 0x2 ||
priv->data->eint_detect_mode == 0x3) {
if (priv->data->eint_use_ext_res == 0x1) {
if (priv->caps & ACCDET_PMIC_EINT0) {
regmap_update_bits(priv->regmap,
RG_EINT0CONFIGACCDET_ADDR,
RG_EINT0CONFIGACCDET_MASK_SFT,
0);
} else if (priv->caps & ACCDET_PMIC_EINT1) {
regmap_update_bits(priv->regmap,
RG_EINT1CONFIGACCDET_ADDR,
RG_EINT1CONFIGACCDET_MASK_SFT,
0);
}
} else {
if (priv->caps & ACCDET_PMIC_EINT0) {
regmap_update_bits(priv->regmap,
RG_EINT0CONFIGACCDET_ADDR,
RG_EINT0CONFIGACCDET_MASK_SFT,
BIT(RG_EINT0CONFIGACCDET_SFT));
} else if (priv->caps & ACCDET_PMIC_EINT1) {
regmap_update_bits(priv->regmap,
RG_EINT1CONFIGACCDET_ADDR,
RG_EINT1CONFIGACCDET_MASK_SFT,
BIT(RG_EINT1CONFIGACCDET_SFT));
}
}
}
if (priv->data->eint_detect_mode != 0x1) {
/* current detect set 0.25uA */
regmap_update_bits(priv->regmap, RG_ACCDETSPARE_ADDR,
0x3 << RG_ACCDETSPARE_SFT,
0x3 << RG_ACCDETSPARE_SFT);
}
regmap_write(priv->regmap, RG_EINTCOMPVTH_ADDR,
val | priv->data->eint_comp_vth << RG_EINTCOMPVTH_SFT);
}
static void mt6359_accdet_init(struct mt6359_accdet *priv)
{
unsigned int reg = 0;
regmap_update_bits(priv->regmap, ACCDET_SEQ_INIT_ADDR,
ACCDET_SEQ_INIT_MASK_SFT, BIT(ACCDET_SEQ_INIT_SFT));
mdelay(2);
regmap_update_bits(priv->regmap, ACCDET_SEQ_INIT_ADDR,
ACCDET_SEQ_INIT_MASK_SFT, 0);
mdelay(1);
/* init the debounce time (debounce/32768)sec */
accdet_set_debounce(priv, accdet_state000,
priv->data->pwm_deb->debounce0);
accdet_set_debounce(priv, accdet_state001,
priv->data->pwm_deb->debounce1);
accdet_set_debounce(priv, accdet_state011,
priv->data->pwm_deb->debounce3);
accdet_set_debounce(priv, accdet_auxadc,
priv->data->pwm_deb->debounce4);
accdet_set_debounce(priv, eint_state000,
priv->data->pwm_deb->eint_debounce0);
accdet_set_debounce(priv, eint_state001,
priv->data->pwm_deb->eint_debounce1);
accdet_set_debounce(priv, eint_state011,
priv->data->pwm_deb->eint_debounce3);
accdet_set_debounce(priv, eint_inverter_state000,
priv->data->pwm_deb->eint_inverter_debounce);
regmap_update_bits(priv->regmap, RG_ACCDET_RST_ADDR,
RG_ACCDET_RST_MASK_SFT, BIT(RG_ACCDET_RST_SFT));
regmap_update_bits(priv->regmap, RG_ACCDET_RST_ADDR,
RG_ACCDET_RST_MASK_SFT, 0);
/* clear high micbias1 voltage setting */
regmap_update_bits(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR,
0x3 << RG_AUDMICBIAS1HVEN_SFT, 0);
regmap_update_bits(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR,
0x7 << RG_AUDMICBIAS1VREF_SFT, 0);
/* init pwm frequency, duty & rise/falling delay */
regmap_write(priv->regmap, ACCDET_PWM_WIDTH_ADDR,
REGISTER_VAL(priv->data->pwm_deb->pwm_width));
regmap_write(priv->regmap, ACCDET_PWM_THRESH_ADDR,
REGISTER_VAL(priv->data->pwm_deb->pwm_thresh));
regmap_write(priv->regmap, ACCDET_RISE_DELAY_ADDR,
(priv->data->pwm_deb->fall_delay << 15 |
priv->data->pwm_deb->rise_delay));
regmap_read(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR, ®);
if (priv->data->mic_vol <= 7) {
/* micbias1 <= 2.7V */
regmap_write(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR,
reg | (priv->data->mic_vol << RG_AUDMICBIAS1VREF_SFT) |
RG_AUDMICBIAS1LOWPEN_MASK_SFT);
} else if (priv->data->mic_vol == 8) {
/* micbias1 = 2.8v */
regmap_write(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR,
reg | (3 << RG_AUDMICBIAS1HVEN_SFT) |
RG_AUDMICBIAS1LOWPEN_MASK_SFT);
} else if (priv->data->mic_vol == 9) {
/* micbias1 = 2.85v */
regmap_write(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR,
reg | (1 << RG_AUDMICBIAS1HVEN_SFT) |
RG_AUDMICBIAS1LOWPEN_MASK_SFT);
}
/* mic mode setting */
regmap_read(priv->regmap, RG_AUDACCDETMICBIAS0PULLLOW_ADDR, ®);
if (priv->data->mic_mode == HEADSET_MODE_1) {
/* ACC mode*/
regmap_write(priv->regmap, RG_AUDACCDETMICBIAS0PULLLOW_ADDR,
reg | RG_ACCDET_MODE_ANA11_MODE1);
/* enable analog fast discharge */
regmap_update_bits(priv->regmap, RG_ANALOGFDEN_ADDR,
RG_ANALOGFDEN_MASK_SFT,
BIT(RG_ANALOGFDEN_SFT));
regmap_update_bits(priv->regmap, RG_ACCDETSPARE_ADDR,
0x3 << 11, 0x3 << 11);
} else if (priv->data->mic_mode == HEADSET_MODE_2) {
/* DCC mode Low cost mode without internal bias */
regmap_write(priv->regmap, RG_AUDACCDETMICBIAS0PULLLOW_ADDR,
reg | RG_ACCDET_MODE_ANA11_MODE2);
/* enable analog fast discharge */
regmap_update_bits(priv->regmap, RG_ANALOGFDEN_ADDR,
0x3 << RG_ANALOGFDEN_SFT,
0x3 << RG_ANALOGFDEN_SFT);
} else if (priv->data->mic_mode == HEADSET_MODE_6) {
/* DCC mode Low cost mode with internal bias,
* bit8 = 1 to use internal bias
*/
regmap_write(priv->regmap, RG_AUDACCDETMICBIAS0PULLLOW_ADDR,
reg | RG_ACCDET_MODE_ANA11_MODE6);
regmap_update_bits(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR,
RG_AUDMICBIAS1DCSW1PEN_MASK_SFT,
BIT(RG_AUDMICBIAS1DCSW1PEN_SFT));
/* enable analog fast discharge */
regmap_update_bits(priv->regmap, RG_ANALOGFDEN_ADDR,
0x3 << RG_ANALOGFDEN_SFT,
0x3 << RG_ANALOGFDEN_SFT);
}
if (priv->caps & ACCDET_PMIC_EINT_IRQ) {
config_eint_init_by_mode(priv);
config_digital_init_by_mode(priv);
}
}
int mt6359_accdet_enable_jack_detect(struct snd_soc_component *component,
struct snd_soc_jack *jack)
{
struct mt6359_accdet *priv =
snd_soc_component_get_drvdata(component);
snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOLUMEDOWN);
snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEUP);
snd_jack_set_key(jack->jack, SND_JACK_BTN_3, KEY_VOICECOMMAND);
priv->jack = jack;
mt6359_accdet_jack_report(priv);
return 0;
}
EXPORT_SYMBOL_GPL(mt6359_accdet_enable_jack_detect);
static int mt6359_accdet_probe(struct platform_device *pdev)
{
struct mt6359_accdet *priv;
struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
int ret;
dev_dbg(&pdev->dev, "%s(), dev name %s\n",
__func__, dev_name(&pdev->dev));
priv = devm_kzalloc(&pdev->dev, sizeof(struct mt6359_accdet),
GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->data = devm_kzalloc(&pdev->dev, sizeof(struct dts_data),
GFP_KERNEL);
if (!priv->data)
return -ENOMEM;
priv->data->pwm_deb = devm_kzalloc(&pdev->dev,
sizeof(struct pwm_deb_settings),
GFP_KERNEL);
if (!priv->data->pwm_deb)
return -ENOMEM;
priv->regmap = mt6397->regmap;
if (IS_ERR(priv->regmap)) {
ret = PTR_ERR(priv->regmap);
dev_err(&pdev->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
priv->dev = &pdev->dev;
ret = mt6359_accdet_parse_dt(priv);
if (ret) {
dev_err(&pdev->dev, "Failed to parse dts\n");
return ret;
}
mutex_init(&priv->res_lock);
priv->accdet_irq = platform_get_irq(pdev, 0);
if (priv->accdet_irq >= 0) {
ret = devm_request_threaded_irq(&pdev->dev, priv->accdet_irq,
NULL, mt6359_accdet_irq,
IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
"ACCDET_IRQ", priv);
if (ret) {
dev_err(&pdev->dev,
"Failed to request IRQ: (%d)\n", ret);
return ret;
}
}
if (priv->caps & ACCDET_PMIC_EINT0) {
priv->accdet_eint0 = platform_get_irq(pdev, 1);
if (priv->accdet_eint0 >= 0) {
ret = devm_request_threaded_irq(&pdev->dev,
priv->accdet_eint0,
NULL, mt6359_accdet_irq,
IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
"ACCDET_EINT0", priv);
if (ret) {
dev_err(&pdev->dev,
"Failed to request eint0 IRQ (%d)\n",
ret);
return ret;
}
}
} else if (priv->caps & ACCDET_PMIC_EINT1) {
priv->accdet_eint1 = platform_get_irq(pdev, 2);
if (priv->accdet_eint1 >= 0) {
ret = devm_request_threaded_irq(&pdev->dev,
priv->accdet_eint1,
NULL, mt6359_accdet_irq,
IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
"ACCDET_EINT1", priv);
if (ret) {
dev_err(&pdev->dev,
"Failed to request eint1 IRQ (%d)\n",
ret);
return ret;
}
}
}
priv->accdet_workqueue = create_singlethread_workqueue("accdet");
INIT_WORK(&priv->accdet_work, mt6359_accdet_work);
if (!priv->accdet_workqueue) {
dev_err(&pdev->dev, "Failed to create accdet workqueue\n");
ret = -1;
goto err_accdet_wq;
}
priv->jd_workqueue = create_singlethread_workqueue("mt6359_accdet_jd");
INIT_WORK(&priv->jd_work, mt6359_accdet_jd_work);
if (!priv->jd_workqueue) {
dev_err(&pdev->dev, "Failed to create jack detect workqueue\n");
ret = -1;
goto err_eint_wq;
}
platform_set_drvdata(pdev, priv);
ret = devm_snd_soc_register_component(&pdev->dev,
&mt6359_accdet_soc_driver,
NULL, 0);
if (ret) {
dev_err(&pdev->dev, "Failed to register component\n");
return ret;
}
priv->jd_sts = M_PLUG_OUT;
priv->jack_type = 0;
priv->btn_type = 0;
priv->accdet_status = 0x3;
mt6359_accdet_init(priv);
mt6359_accdet_jack_report(priv);
return 0;
err_eint_wq:
destroy_workqueue(priv->accdet_workqueue);
err_accdet_wq:
dev_err(&pdev->dev, "%s error. now exit.!\n", __func__);
return ret;
}
static struct platform_driver mt6359_accdet_driver = {
.driver = {
.name = "pmic-codec-accdet",
},
.probe = mt6359_accdet_probe,
};
module_platform_driver(mt6359_accdet_driver)
/* Module information */
MODULE_DESCRIPTION("MT6359 ALSA SoC codec jack driver");
MODULE_AUTHOR("Argus Lin <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/mt6359-accdet.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8804-i2c.c -- WM8804 S/PDIF transceiver driver - I2C
*
* Copyright 2015 Cirrus Logic Inc
*
* Author: Charles Keepax <[email protected]>
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/acpi.h>
#include "wm8804.h"
static int wm8804_i2c_probe(struct i2c_client *i2c)
{
struct regmap *regmap;
regmap = devm_regmap_init_i2c(i2c, &wm8804_regmap_config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return wm8804_probe(&i2c->dev, regmap);
}
static void wm8804_i2c_remove(struct i2c_client *i2c)
{
wm8804_remove(&i2c->dev);
}
static const struct i2c_device_id wm8804_i2c_id[] = {
{ "wm8804", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8804_i2c_id);
#if defined(CONFIG_OF)
static const struct of_device_id wm8804_of_match[] = {
{ .compatible = "wlf,wm8804", },
{ }
};
MODULE_DEVICE_TABLE(of, wm8804_of_match);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id wm8804_acpi_match[] = {
{ "1AEC8804", 0 }, /* Wolfson PCI ID + part ID */
{ "10138804", 0 }, /* Cirrus Logic PCI ID + part ID */
{ },
};
MODULE_DEVICE_TABLE(acpi, wm8804_acpi_match);
#endif
static struct i2c_driver wm8804_i2c_driver = {
.driver = {
.name = "wm8804",
.pm = &wm8804_pm,
.of_match_table = of_match_ptr(wm8804_of_match),
.acpi_match_table = ACPI_PTR(wm8804_acpi_match),
},
.probe = wm8804_i2c_probe,
.remove = wm8804_i2c_remove,
.id_table = wm8804_i2c_id
};
module_i2c_driver(wm8804_i2c_driver);
MODULE_DESCRIPTION("ASoC WM8804 driver - I2C");
MODULE_AUTHOR("Charles Keepax <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8804-i2c.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8510.c -- WM8510 ALSA Soc Audio driver
*
* Copyright 2006 Wolfson Microelectronics PLC.
*
* Author: Liam Girdwood <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include "wm8510.h"
/*
* wm8510 register cache
* We can't read the WM8510 register space when we are
* using 2 wire for device control, so we cache them instead.
*/
static const struct reg_default wm8510_reg_defaults[] = {
{ 1, 0x0000 },
{ 2, 0x0000 },
{ 3, 0x0000 },
{ 4, 0x0050 },
{ 5, 0x0000 },
{ 6, 0x0140 },
{ 7, 0x0000 },
{ 8, 0x0000 },
{ 9, 0x0000 },
{ 10, 0x0000 },
{ 11, 0x00ff },
{ 12, 0x0000 },
{ 13, 0x0000 },
{ 14, 0x0100 },
{ 15, 0x00ff },
{ 16, 0x0000 },
{ 17, 0x0000 },
{ 18, 0x012c },
{ 19, 0x002c },
{ 20, 0x002c },
{ 21, 0x002c },
{ 22, 0x002c },
{ 23, 0x0000 },
{ 24, 0x0032 },
{ 25, 0x0000 },
{ 26, 0x0000 },
{ 27, 0x0000 },
{ 28, 0x0000 },
{ 29, 0x0000 },
{ 30, 0x0000 },
{ 31, 0x0000 },
{ 32, 0x0038 },
{ 33, 0x000b },
{ 34, 0x0032 },
{ 35, 0x0000 },
{ 36, 0x0008 },
{ 37, 0x000c },
{ 38, 0x0093 },
{ 39, 0x00e9 },
{ 40, 0x0000 },
{ 41, 0x0000 },
{ 42, 0x0000 },
{ 43, 0x0000 },
{ 44, 0x0003 },
{ 45, 0x0010 },
{ 46, 0x0000 },
{ 47, 0x0000 },
{ 48, 0x0000 },
{ 49, 0x0002 },
{ 50, 0x0001 },
{ 51, 0x0000 },
{ 52, 0x0000 },
{ 53, 0x0000 },
{ 54, 0x0039 },
{ 55, 0x0000 },
{ 56, 0x0001 },
};
static bool wm8510_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8510_RESET:
return true;
default:
return false;
}
}
#define WM8510_POWER1_BIASEN 0x08
#define WM8510_POWER1_BUFIOEN 0x10
#define wm8510_reset(c) snd_soc_component_write(c, WM8510_RESET, 0)
/* codec private data */
struct wm8510_priv {
struct regmap *regmap;
};
static const char *wm8510_companding[] = { "Off", "NC", "u-law", "A-law" };
static const char *wm8510_deemp[] = { "None", "32kHz", "44.1kHz", "48kHz" };
static const char *wm8510_alc[] = { "ALC", "Limiter" };
static const struct soc_enum wm8510_enum[] = {
SOC_ENUM_SINGLE(WM8510_COMP, 1, 4, wm8510_companding), /* adc */
SOC_ENUM_SINGLE(WM8510_COMP, 3, 4, wm8510_companding), /* dac */
SOC_ENUM_SINGLE(WM8510_DAC, 4, 4, wm8510_deemp),
SOC_ENUM_SINGLE(WM8510_ALC3, 8, 2, wm8510_alc),
};
static const struct snd_kcontrol_new wm8510_snd_controls[] = {
SOC_SINGLE("Digital Loopback Switch", WM8510_COMP, 0, 1, 0),
SOC_ENUM("DAC Companding", wm8510_enum[1]),
SOC_ENUM("ADC Companding", wm8510_enum[0]),
SOC_ENUM("Playback De-emphasis", wm8510_enum[2]),
SOC_SINGLE("DAC Inversion Switch", WM8510_DAC, 0, 1, 0),
SOC_SINGLE("Master Playback Volume", WM8510_DACVOL, 0, 127, 0),
SOC_SINGLE("High Pass Filter Switch", WM8510_ADC, 8, 1, 0),
SOC_SINGLE("High Pass Cut Off", WM8510_ADC, 4, 7, 0),
SOC_SINGLE("ADC Inversion Switch", WM8510_COMP, 0, 1, 0),
SOC_SINGLE("Capture Volume", WM8510_ADCVOL, 0, 127, 0),
SOC_SINGLE("DAC Playback Limiter Switch", WM8510_DACLIM1, 8, 1, 0),
SOC_SINGLE("DAC Playback Limiter Decay", WM8510_DACLIM1, 4, 15, 0),
SOC_SINGLE("DAC Playback Limiter Attack", WM8510_DACLIM1, 0, 15, 0),
SOC_SINGLE("DAC Playback Limiter Threshold", WM8510_DACLIM2, 4, 7, 0),
SOC_SINGLE("DAC Playback Limiter Boost", WM8510_DACLIM2, 0, 15, 0),
SOC_SINGLE("ALC Enable Switch", WM8510_ALC1, 8, 1, 0),
SOC_SINGLE("ALC Capture Max Gain", WM8510_ALC1, 3, 7, 0),
SOC_SINGLE("ALC Capture Min Gain", WM8510_ALC1, 0, 7, 0),
SOC_SINGLE("ALC Capture ZC Switch", WM8510_ALC2, 8, 1, 0),
SOC_SINGLE("ALC Capture Hold", WM8510_ALC2, 4, 7, 0),
SOC_SINGLE("ALC Capture Target", WM8510_ALC2, 0, 15, 0),
SOC_ENUM("ALC Capture Mode", wm8510_enum[3]),
SOC_SINGLE("ALC Capture Decay", WM8510_ALC3, 4, 15, 0),
SOC_SINGLE("ALC Capture Attack", WM8510_ALC3, 0, 15, 0),
SOC_SINGLE("ALC Capture Noise Gate Switch", WM8510_NGATE, 3, 1, 0),
SOC_SINGLE("ALC Capture Noise Gate Threshold", WM8510_NGATE, 0, 7, 0),
SOC_SINGLE("Capture PGA ZC Switch", WM8510_INPPGA, 7, 1, 0),
SOC_SINGLE("Capture PGA Volume", WM8510_INPPGA, 0, 63, 0),
SOC_SINGLE("Speaker Playback ZC Switch", WM8510_SPKVOL, 7, 1, 0),
SOC_SINGLE("Speaker Playback Switch", WM8510_SPKVOL, 6, 1, 1),
SOC_SINGLE("Speaker Playback Volume", WM8510_SPKVOL, 0, 63, 0),
SOC_SINGLE("Speaker Boost", WM8510_OUTPUT, 2, 1, 0),
SOC_SINGLE("Capture Boost(+20dB)", WM8510_ADCBOOST, 8, 1, 0),
SOC_SINGLE("Mono Playback Switch", WM8510_MONOMIX, 6, 1, 1),
};
/* Speaker Output Mixer */
static const struct snd_kcontrol_new wm8510_speaker_mixer_controls[] = {
SOC_DAPM_SINGLE("Line Bypass Switch", WM8510_SPKMIX, 1, 1, 0),
SOC_DAPM_SINGLE("Aux Playback Switch", WM8510_SPKMIX, 5, 1, 0),
SOC_DAPM_SINGLE("PCM Playback Switch", WM8510_SPKMIX, 0, 1, 0),
};
/* Mono Output Mixer */
static const struct snd_kcontrol_new wm8510_mono_mixer_controls[] = {
SOC_DAPM_SINGLE("Line Bypass Switch", WM8510_MONOMIX, 1, 1, 0),
SOC_DAPM_SINGLE("Aux Playback Switch", WM8510_MONOMIX, 2, 1, 0),
SOC_DAPM_SINGLE("PCM Playback Switch", WM8510_MONOMIX, 0, 1, 0),
};
static const struct snd_kcontrol_new wm8510_boost_controls[] = {
SOC_DAPM_SINGLE("Mic PGA Switch", WM8510_INPPGA, 6, 1, 1),
SOC_DAPM_SINGLE("Aux Volume", WM8510_ADCBOOST, 0, 7, 0),
SOC_DAPM_SINGLE("Mic Volume", WM8510_ADCBOOST, 4, 7, 0),
};
static const struct snd_kcontrol_new wm8510_micpga_controls[] = {
SOC_DAPM_SINGLE("MICP Switch", WM8510_INPUT, 0, 1, 0),
SOC_DAPM_SINGLE("MICN Switch", WM8510_INPUT, 1, 1, 0),
SOC_DAPM_SINGLE("AUX Switch", WM8510_INPUT, 2, 1, 0),
};
static const struct snd_soc_dapm_widget wm8510_dapm_widgets[] = {
SND_SOC_DAPM_MIXER("Speaker Mixer", WM8510_POWER3, 2, 0,
&wm8510_speaker_mixer_controls[0],
ARRAY_SIZE(wm8510_speaker_mixer_controls)),
SND_SOC_DAPM_MIXER("Mono Mixer", WM8510_POWER3, 3, 0,
&wm8510_mono_mixer_controls[0],
ARRAY_SIZE(wm8510_mono_mixer_controls)),
SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM8510_POWER3, 0, 0),
SND_SOC_DAPM_ADC("ADC", "HiFi Capture", WM8510_POWER2, 0, 0),
SND_SOC_DAPM_PGA("Aux Input", WM8510_POWER1, 6, 0, NULL, 0),
SND_SOC_DAPM_PGA("SpkN Out", WM8510_POWER3, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA("SpkP Out", WM8510_POWER3, 6, 0, NULL, 0),
SND_SOC_DAPM_PGA("Mono Out", WM8510_POWER3, 7, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Mic PGA", WM8510_POWER2, 2, 0,
&wm8510_micpga_controls[0],
ARRAY_SIZE(wm8510_micpga_controls)),
SND_SOC_DAPM_MIXER("Boost Mixer", WM8510_POWER2, 4, 0,
&wm8510_boost_controls[0],
ARRAY_SIZE(wm8510_boost_controls)),
SND_SOC_DAPM_MICBIAS("Mic Bias", WM8510_POWER1, 4, 0),
SND_SOC_DAPM_INPUT("MICN"),
SND_SOC_DAPM_INPUT("MICP"),
SND_SOC_DAPM_INPUT("AUX"),
SND_SOC_DAPM_OUTPUT("MONOOUT"),
SND_SOC_DAPM_OUTPUT("SPKOUTP"),
SND_SOC_DAPM_OUTPUT("SPKOUTN"),
};
static const struct snd_soc_dapm_route wm8510_dapm_routes[] = {
/* Mono output mixer */
{"Mono Mixer", "PCM Playback Switch", "DAC"},
{"Mono Mixer", "Aux Playback Switch", "Aux Input"},
{"Mono Mixer", "Line Bypass Switch", "Boost Mixer"},
/* Speaker output mixer */
{"Speaker Mixer", "PCM Playback Switch", "DAC"},
{"Speaker Mixer", "Aux Playback Switch", "Aux Input"},
{"Speaker Mixer", "Line Bypass Switch", "Boost Mixer"},
/* Outputs */
{"Mono Out", NULL, "Mono Mixer"},
{"MONOOUT", NULL, "Mono Out"},
{"SpkN Out", NULL, "Speaker Mixer"},
{"SpkP Out", NULL, "Speaker Mixer"},
{"SPKOUTN", NULL, "SpkN Out"},
{"SPKOUTP", NULL, "SpkP Out"},
/* Microphone PGA */
{"Mic PGA", "MICN Switch", "MICN"},
{"Mic PGA", "MICP Switch", "MICP"},
{ "Mic PGA", "AUX Switch", "Aux Input" },
/* Boost Mixer */
{"Boost Mixer", "Mic PGA Switch", "Mic PGA"},
{"Boost Mixer", "Mic Volume", "MICP"},
{"Boost Mixer", "Aux Volume", "Aux Input"},
{"ADC", NULL, "Boost Mixer"},
};
struct pll_ {
unsigned int pre_div:4; /* prescale - 1 */
unsigned int n:4;
unsigned int k;
};
static struct pll_ pll_div;
/* The size in bits of the pll divide multiplied by 10
* to allow rounding later */
#define FIXED_PLL_SIZE ((1 << 24) * 10)
static void pll_factors(unsigned int target, unsigned int source)
{
unsigned long long Kpart;
unsigned int K, Ndiv, Nmod;
Ndiv = target / source;
if (Ndiv < 6) {
source >>= 1;
pll_div.pre_div = 1;
Ndiv = target / source;
} else
pll_div.pre_div = 0;
if ((Ndiv < 6) || (Ndiv > 12))
printk(KERN_WARNING
"WM8510 N value %u outwith recommended range!d\n",
Ndiv);
pll_div.n = Ndiv;
Nmod = target % source;
Kpart = FIXED_PLL_SIZE * (long long)Nmod;
do_div(Kpart, source);
K = Kpart & 0xFFFFFFFF;
/* Check if we need to round */
if ((K % 10) >= 5)
K += 5;
/* Move down to proper range now rounding is done */
K /= 10;
pll_div.k = K;
}
static int wm8510_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
int source, unsigned int freq_in, unsigned int freq_out)
{
struct snd_soc_component *component = codec_dai->component;
u16 reg;
if (freq_in == 0 || freq_out == 0) {
/* Clock CODEC directly from MCLK */
reg = snd_soc_component_read(component, WM8510_CLOCK);
snd_soc_component_write(component, WM8510_CLOCK, reg & 0x0ff);
/* Turn off PLL */
reg = snd_soc_component_read(component, WM8510_POWER1);
snd_soc_component_write(component, WM8510_POWER1, reg & 0x1df);
return 0;
}
pll_factors(freq_out*4, freq_in);
snd_soc_component_write(component, WM8510_PLLN, (pll_div.pre_div << 4) | pll_div.n);
snd_soc_component_write(component, WM8510_PLLK1, pll_div.k >> 18);
snd_soc_component_write(component, WM8510_PLLK2, (pll_div.k >> 9) & 0x1ff);
snd_soc_component_write(component, WM8510_PLLK3, pll_div.k & 0x1ff);
reg = snd_soc_component_read(component, WM8510_POWER1);
snd_soc_component_write(component, WM8510_POWER1, reg | 0x020);
/* Run CODEC from PLL instead of MCLK */
reg = snd_soc_component_read(component, WM8510_CLOCK);
snd_soc_component_write(component, WM8510_CLOCK, reg | 0x100);
return 0;
}
/*
* Configure WM8510 clock dividers.
*/
static int wm8510_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
int div_id, int div)
{
struct snd_soc_component *component = codec_dai->component;
u16 reg;
switch (div_id) {
case WM8510_OPCLKDIV:
reg = snd_soc_component_read(component, WM8510_GPIO) & 0x1cf;
snd_soc_component_write(component, WM8510_GPIO, reg | div);
break;
case WM8510_MCLKDIV:
reg = snd_soc_component_read(component, WM8510_CLOCK) & 0x11f;
snd_soc_component_write(component, WM8510_CLOCK, reg | div);
break;
case WM8510_ADCCLK:
reg = snd_soc_component_read(component, WM8510_ADC) & 0x1f7;
snd_soc_component_write(component, WM8510_ADC, reg | div);
break;
case WM8510_DACCLK:
reg = snd_soc_component_read(component, WM8510_DAC) & 0x1f7;
snd_soc_component_write(component, WM8510_DAC, reg | div);
break;
case WM8510_BCLKDIV:
reg = snd_soc_component_read(component, WM8510_CLOCK) & 0x1e3;
snd_soc_component_write(component, WM8510_CLOCK, reg | div);
break;
default:
return -EINVAL;
}
return 0;
}
static int wm8510_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
u16 iface = 0;
u16 clk = snd_soc_component_read(component, WM8510_CLOCK) & 0x1fe;
/* set master/slave audio interface */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
clk |= 0x0001;
break;
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface |= 0x0010;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
iface |= 0x0008;
break;
case SND_SOC_DAIFMT_DSP_A:
iface |= 0x00018;
break;
default:
return -EINVAL;
}
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
iface |= 0x0180;
break;
case SND_SOC_DAIFMT_IB_NF:
iface |= 0x0100;
break;
case SND_SOC_DAIFMT_NB_IF:
iface |= 0x0080;
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, WM8510_IFACE, iface);
snd_soc_component_write(component, WM8510_CLOCK, clk);
return 0;
}
static int wm8510_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
u16 iface = snd_soc_component_read(component, WM8510_IFACE) & 0x19f;
u16 adn = snd_soc_component_read(component, WM8510_ADD) & 0x1f1;
/* bit size */
switch (params_width(params)) {
case 16:
break;
case 20:
iface |= 0x0020;
break;
case 24:
iface |= 0x0040;
break;
case 32:
iface |= 0x0060;
break;
}
/* filter coefficient */
switch (params_rate(params)) {
case 8000:
adn |= 0x5 << 1;
break;
case 11025:
adn |= 0x4 << 1;
break;
case 16000:
adn |= 0x3 << 1;
break;
case 22050:
adn |= 0x2 << 1;
break;
case 32000:
adn |= 0x1 << 1;
break;
case 44100:
case 48000:
break;
}
snd_soc_component_write(component, WM8510_IFACE, iface);
snd_soc_component_write(component, WM8510_ADD, adn);
return 0;
}
static int wm8510_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
u16 mute_reg = snd_soc_component_read(component, WM8510_DAC) & 0xffbf;
if (mute)
snd_soc_component_write(component, WM8510_DAC, mute_reg | 0x40);
else
snd_soc_component_write(component, WM8510_DAC, mute_reg);
return 0;
}
/* liam need to make this lower power with dapm */
static int wm8510_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct wm8510_priv *wm8510 = snd_soc_component_get_drvdata(component);
u16 power1 = snd_soc_component_read(component, WM8510_POWER1) & ~0x3;
switch (level) {
case SND_SOC_BIAS_ON:
case SND_SOC_BIAS_PREPARE:
power1 |= 0x1; /* VMID 50k */
snd_soc_component_write(component, WM8510_POWER1, power1);
break;
case SND_SOC_BIAS_STANDBY:
power1 |= WM8510_POWER1_BIASEN | WM8510_POWER1_BUFIOEN;
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
regcache_sync(wm8510->regmap);
/* Initial cap charge at VMID 5k */
snd_soc_component_write(component, WM8510_POWER1, power1 | 0x3);
mdelay(100);
}
power1 |= 0x2; /* VMID 500k */
snd_soc_component_write(component, WM8510_POWER1, power1);
break;
case SND_SOC_BIAS_OFF:
snd_soc_component_write(component, WM8510_POWER1, 0);
snd_soc_component_write(component, WM8510_POWER2, 0);
snd_soc_component_write(component, WM8510_POWER3, 0);
break;
}
return 0;
}
#define WM8510_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
#define WM8510_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops wm8510_dai_ops = {
.hw_params = wm8510_pcm_hw_params,
.mute_stream = wm8510_mute,
.set_fmt = wm8510_set_dai_fmt,
.set_clkdiv = wm8510_set_dai_clkdiv,
.set_pll = wm8510_set_dai_pll,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver wm8510_dai = {
.name = "wm8510-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = WM8510_RATES,
.formats = WM8510_FORMATS,},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = WM8510_RATES,
.formats = WM8510_FORMATS,},
.ops = &wm8510_dai_ops,
.symmetric_rate = 1,
};
static int wm8510_probe(struct snd_soc_component *component)
{
wm8510_reset(component);
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_wm8510 = {
.probe = wm8510_probe,
.set_bias_level = wm8510_set_bias_level,
.controls = wm8510_snd_controls,
.num_controls = ARRAY_SIZE(wm8510_snd_controls),
.dapm_widgets = wm8510_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8510_dapm_widgets),
.dapm_routes = wm8510_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(wm8510_dapm_routes),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct of_device_id wm8510_of_match[] = {
{ .compatible = "wlf,wm8510" },
{ },
};
MODULE_DEVICE_TABLE(of, wm8510_of_match);
static const struct regmap_config wm8510_regmap = {
.reg_bits = 7,
.val_bits = 9,
.max_register = WM8510_MONOMIX,
.reg_defaults = wm8510_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8510_reg_defaults),
.cache_type = REGCACHE_MAPLE,
.volatile_reg = wm8510_volatile,
};
#if defined(CONFIG_SPI_MASTER)
static int wm8510_spi_probe(struct spi_device *spi)
{
struct wm8510_priv *wm8510;
int ret;
wm8510 = devm_kzalloc(&spi->dev, sizeof(struct wm8510_priv),
GFP_KERNEL);
if (wm8510 == NULL)
return -ENOMEM;
wm8510->regmap = devm_regmap_init_spi(spi, &wm8510_regmap);
if (IS_ERR(wm8510->regmap))
return PTR_ERR(wm8510->regmap);
spi_set_drvdata(spi, wm8510);
ret = devm_snd_soc_register_component(&spi->dev,
&soc_component_dev_wm8510, &wm8510_dai, 1);
return ret;
}
static struct spi_driver wm8510_spi_driver = {
.driver = {
.name = "wm8510",
.of_match_table = wm8510_of_match,
},
.probe = wm8510_spi_probe,
};
#endif /* CONFIG_SPI_MASTER */
#if IS_ENABLED(CONFIG_I2C)
static int wm8510_i2c_probe(struct i2c_client *i2c)
{
struct wm8510_priv *wm8510;
int ret;
wm8510 = devm_kzalloc(&i2c->dev, sizeof(struct wm8510_priv),
GFP_KERNEL);
if (wm8510 == NULL)
return -ENOMEM;
wm8510->regmap = devm_regmap_init_i2c(i2c, &wm8510_regmap);
if (IS_ERR(wm8510->regmap))
return PTR_ERR(wm8510->regmap);
i2c_set_clientdata(i2c, wm8510);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_wm8510, &wm8510_dai, 1);
return ret;
}
static const struct i2c_device_id wm8510_i2c_id[] = {
{ "wm8510", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8510_i2c_id);
static struct i2c_driver wm8510_i2c_driver = {
.driver = {
.name = "wm8510",
.of_match_table = wm8510_of_match,
},
.probe = wm8510_i2c_probe,
.id_table = wm8510_i2c_id,
};
#endif
static int __init wm8510_modinit(void)
{
int ret = 0;
#if IS_ENABLED(CONFIG_I2C)
ret = i2c_add_driver(&wm8510_i2c_driver);
if (ret != 0) {
printk(KERN_ERR "Failed to register WM8510 I2C driver: %d\n",
ret);
}
#endif
#if defined(CONFIG_SPI_MASTER)
ret = spi_register_driver(&wm8510_spi_driver);
if (ret != 0) {
printk(KERN_ERR "Failed to register WM8510 SPI driver: %d\n",
ret);
}
#endif
return ret;
}
module_init(wm8510_modinit);
static void __exit wm8510_exit(void)
{
#if IS_ENABLED(CONFIG_I2C)
i2c_del_driver(&wm8510_i2c_driver);
#endif
#if defined(CONFIG_SPI_MASTER)
spi_unregister_driver(&wm8510_spi_driver);
#endif
}
module_exit(wm8510_exit);
MODULE_DESCRIPTION("ASoC WM8510 driver");
MODULE_AUTHOR("Liam Girdwood");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8510.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* cx20442.c -- CX20442 ALSA Soc Audio driver
*
* Copyright 2009 Janusz Krzysztofik <[email protected]>
*
* Initially based on sound/soc/codecs/wm8400.c
* Copyright 2008, 2009 Wolfson Microelectronics PLC.
* Author: Mark Brown <[email protected]>
*/
#include <linux/tty.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/regulator/consumer.h>
#include <sound/core.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include "cx20442.h"
struct cx20442_priv {
struct tty_struct *tty;
struct regulator *por;
u8 reg_cache;
};
#define CX20442_PM 0x0
#define CX20442_TELIN 0
#define CX20442_TELOUT 1
#define CX20442_MIC 2
#define CX20442_SPKOUT 3
#define CX20442_AGC 4
static const struct snd_soc_dapm_widget cx20442_dapm_widgets[] = {
SND_SOC_DAPM_OUTPUT("TELOUT"),
SND_SOC_DAPM_OUTPUT("SPKOUT"),
SND_SOC_DAPM_OUTPUT("AGCOUT"),
SND_SOC_DAPM_MIXER("SPKOUT Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("TELOUT Amp", CX20442_PM, CX20442_TELOUT, 0, NULL, 0),
SND_SOC_DAPM_PGA("SPKOUT Amp", CX20442_PM, CX20442_SPKOUT, 0, NULL, 0),
SND_SOC_DAPM_PGA("SPKOUT AGC", CX20442_PM, CX20442_AGC, 0, NULL, 0),
SND_SOC_DAPM_DAC("DAC", "Playback", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("ADC", "Capture", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_MIXER("Input Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MICBIAS("TELIN Bias", CX20442_PM, CX20442_TELIN, 0),
SND_SOC_DAPM_MICBIAS("MIC Bias", CX20442_PM, CX20442_MIC, 0),
SND_SOC_DAPM_PGA("MIC AGC", CX20442_PM, CX20442_AGC, 0, NULL, 0),
SND_SOC_DAPM_INPUT("TELIN"),
SND_SOC_DAPM_INPUT("MIC"),
SND_SOC_DAPM_INPUT("AGCIN"),
};
static const struct snd_soc_dapm_route cx20442_audio_map[] = {
{"TELOUT", NULL, "TELOUT Amp"},
{"SPKOUT", NULL, "SPKOUT Mixer"},
{"SPKOUT Mixer", NULL, "SPKOUT Amp"},
{"TELOUT Amp", NULL, "DAC"},
{"SPKOUT Amp", NULL, "DAC"},
{"SPKOUT Mixer", NULL, "SPKOUT AGC"},
{"SPKOUT AGC", NULL, "AGCIN"},
{"AGCOUT", NULL, "MIC AGC"},
{"MIC AGC", NULL, "MIC"},
{"MIC Bias", NULL, "MIC"},
{"Input Mixer", NULL, "MIC Bias"},
{"TELIN Bias", NULL, "TELIN"},
{"Input Mixer", NULL, "TELIN Bias"},
{"ADC", NULL, "Input Mixer"},
};
static unsigned int cx20442_read_reg_cache(struct snd_soc_component *component,
unsigned int reg)
{
struct cx20442_priv *cx20442 = snd_soc_component_get_drvdata(component);
if (reg >= 1)
return -EINVAL;
return cx20442->reg_cache;
}
enum v253_vls {
V253_VLS_NONE = 0,
V253_VLS_T,
V253_VLS_L,
V253_VLS_LT,
V253_VLS_S,
V253_VLS_ST,
V253_VLS_M,
V253_VLS_MST,
V253_VLS_S1,
V253_VLS_S1T,
V253_VLS_MS1T,
V253_VLS_M1,
V253_VLS_M1ST,
V253_VLS_M1S1T,
V253_VLS_H,
V253_VLS_HT,
V253_VLS_MS,
V253_VLS_MS1,
V253_VLS_M1S,
V253_VLS_M1S1,
V253_VLS_TEST,
};
static int cx20442_pm_to_v253_vls(u8 value)
{
switch (value & ~(1 << CX20442_AGC)) {
case 0:
return V253_VLS_T;
case (1 << CX20442_SPKOUT):
case (1 << CX20442_MIC):
case (1 << CX20442_SPKOUT) | (1 << CX20442_MIC):
return V253_VLS_M1S1;
case (1 << CX20442_TELOUT):
case (1 << CX20442_TELIN):
case (1 << CX20442_TELOUT) | (1 << CX20442_TELIN):
return V253_VLS_L;
case (1 << CX20442_TELOUT) | (1 << CX20442_MIC):
return V253_VLS_NONE;
}
return -EINVAL;
}
static int cx20442_pm_to_v253_vsp(u8 value)
{
switch (value & ~(1 << CX20442_AGC)) {
case (1 << CX20442_SPKOUT):
case (1 << CX20442_MIC):
case (1 << CX20442_SPKOUT) | (1 << CX20442_MIC):
return (bool)(value & (1 << CX20442_AGC));
}
return (value & (1 << CX20442_AGC)) ? -EINVAL : 0;
}
static int cx20442_write(struct snd_soc_component *component, unsigned int reg,
unsigned int value)
{
struct cx20442_priv *cx20442 = snd_soc_component_get_drvdata(component);
int vls, vsp, old, len;
char buf[18];
if (reg >= 1)
return -EINVAL;
/* tty and write pointers required for talking to the modem
* are expected to be set by the line discipline initialization code */
if (!cx20442->tty || !cx20442->tty->ops->write)
return -EIO;
old = cx20442->reg_cache;
cx20442->reg_cache = value;
vls = cx20442_pm_to_v253_vls(value);
if (vls < 0)
return vls;
vsp = cx20442_pm_to_v253_vsp(value);
if (vsp < 0)
return vsp;
if ((vls == V253_VLS_T) ||
(vls == cx20442_pm_to_v253_vls(old))) {
if (vsp == cx20442_pm_to_v253_vsp(old))
return 0;
len = snprintf(buf, ARRAY_SIZE(buf), "at+vsp=%d\r", vsp);
} else if (vsp == cx20442_pm_to_v253_vsp(old))
len = snprintf(buf, ARRAY_SIZE(buf), "at+vls=%d\r", vls);
else
len = snprintf(buf, ARRAY_SIZE(buf),
"at+vls=%d;+vsp=%d\r", vls, vsp);
if (unlikely(len > (ARRAY_SIZE(buf) - 1)))
return -ENOMEM;
dev_dbg(component->dev, "%s: %s\n", __func__, buf);
if (cx20442->tty->ops->write(cx20442->tty, buf, len) != len)
return -EIO;
return 0;
}
/*
* Line discpline related code
*
* Any of the callback functions below can be used in two ways:
* 1) registerd by a machine driver as one of line discipline operations,
* 2) called from a machine's provided line discipline callback function
* in case when extra machine specific code must be run as well.
*/
/* Modem init: echo off, digital speaker off, quiet off, voice mode */
static const char v253_init[] = "ate0m0q0+fclass=8\r";
/* Line discipline .open() */
static int v253_open(struct tty_struct *tty)
{
int ret, len = strlen(v253_init);
/* Doesn't make sense without write callback */
if (!tty->ops->write)
return -EINVAL;
/* Won't work if no codec pointer has been passed by a card driver */
if (!tty->disc_data)
return -ENODEV;
tty->receive_room = 16;
if (tty->ops->write(tty, v253_init, len) != len) {
ret = -EIO;
goto err;
}
/* Actual setup will be performed after the modem responds. */
return 0;
err:
tty->disc_data = NULL;
return ret;
}
/* Line discipline .close() */
static void v253_close(struct tty_struct *tty)
{
struct snd_soc_component *component = tty->disc_data;
struct cx20442_priv *cx20442;
tty->disc_data = NULL;
if (!component)
return;
cx20442 = snd_soc_component_get_drvdata(component);
/* Prevent the codec driver from further accessing the modem */
cx20442->tty = NULL;
component->card->pop_time = 0;
}
/* Line discipline .hangup() */
static void v253_hangup(struct tty_struct *tty)
{
v253_close(tty);
}
/* Line discipline .receive_buf() */
static void v253_receive(struct tty_struct *tty, const u8 *cp, const u8 *fp,
size_t count)
{
struct snd_soc_component *component = tty->disc_data;
struct cx20442_priv *cx20442;
if (!component)
return;
cx20442 = snd_soc_component_get_drvdata(component);
if (!cx20442->tty) {
/* First modem response, complete setup procedure */
/* Set up codec driver access to modem controls */
cx20442->tty = tty;
component->card->pop_time = 1;
}
}
struct tty_ldisc_ops v253_ops = {
.name = "cx20442",
.owner = THIS_MODULE,
.open = v253_open,
.close = v253_close,
.hangup = v253_hangup,
.receive_buf = v253_receive,
};
EXPORT_SYMBOL_GPL(v253_ops);
/*
* Codec DAI
*/
static struct snd_soc_dai_driver cx20442_dai = {
.name = "cx20442-voice",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 1,
.rates = SNDRV_PCM_RATE_8000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 1,
.rates = SNDRV_PCM_RATE_8000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
};
static int cx20442_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct cx20442_priv *cx20442 = snd_soc_component_get_drvdata(component);
int err = 0;
switch (level) {
case SND_SOC_BIAS_PREPARE:
if (snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_STANDBY)
break;
if (IS_ERR(cx20442->por))
err = PTR_ERR(cx20442->por);
else
err = regulator_enable(cx20442->por);
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_PREPARE)
break;
if (IS_ERR(cx20442->por))
err = PTR_ERR(cx20442->por);
else
err = regulator_disable(cx20442->por);
break;
default:
break;
}
return err;
}
static int cx20442_component_probe(struct snd_soc_component *component)
{
struct cx20442_priv *cx20442;
cx20442 = kzalloc(sizeof(struct cx20442_priv), GFP_KERNEL);
if (cx20442 == NULL)
return -ENOMEM;
cx20442->por = regulator_get(component->dev, "POR");
if (IS_ERR(cx20442->por)) {
int err = PTR_ERR(cx20442->por);
dev_warn(component->dev, "failed to get POR supply (%d)", err);
/*
* When running on a non-dt platform and requested regulator
* is not available, regulator_get() never returns
* -EPROBE_DEFER as it is not able to justify if the regulator
* may still appear later. On the other hand, the board can
* still set full constraints flag at late_initcall in order
* to instruct regulator_get() to return a dummy one if
* sufficient. Hence, if we get -ENODEV here, let's convert
* it to -EPROBE_DEFER and wait for the board to decide or
* let Deferred Probe infrastructure handle this error.
*/
if (err == -ENODEV)
err = -EPROBE_DEFER;
kfree(cx20442);
return err;
}
cx20442->tty = NULL;
snd_soc_component_set_drvdata(component, cx20442);
component->card->pop_time = 0;
return 0;
}
/* power down chip */
static void cx20442_component_remove(struct snd_soc_component *component)
{
struct cx20442_priv *cx20442 = snd_soc_component_get_drvdata(component);
if (cx20442->tty) {
struct tty_struct *tty = cx20442->tty;
tty_hangup(tty);
}
if (!IS_ERR(cx20442->por)) {
/* should be already in STANDBY, hence disabled */
regulator_put(cx20442->por);
}
snd_soc_component_set_drvdata(component, NULL);
kfree(cx20442);
}
static const struct snd_soc_component_driver cx20442_component_dev = {
.probe = cx20442_component_probe,
.remove = cx20442_component_remove,
.set_bias_level = cx20442_set_bias_level,
.read = cx20442_read_reg_cache,
.write = cx20442_write,
.dapm_widgets = cx20442_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(cx20442_dapm_widgets),
.dapm_routes = cx20442_audio_map,
.num_dapm_routes = ARRAY_SIZE(cx20442_audio_map),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int cx20442_platform_probe(struct platform_device *pdev)
{
return devm_snd_soc_register_component(&pdev->dev,
&cx20442_component_dev, &cx20442_dai, 1);
}
static struct platform_driver cx20442_platform_driver = {
.driver = {
.name = "cx20442-codec",
},
.probe = cx20442_platform_probe,
};
module_platform_driver(cx20442_platform_driver);
MODULE_DESCRIPTION("ASoC CX20442-11 voice modem codec driver");
MODULE_AUTHOR("Janusz Krzysztofik");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:cx20442-codec");
| linux-master | sound/soc/codecs/cx20442.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ak4535.c -- AK4535 ALSA Soc Audio driver
*
* Copyright 2005 Openedhand Ltd.
*
* Author: Richard Purdie <[email protected]>
*
* Based on wm8753.c by Liam Girdwood
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include "ak4535.h"
/* codec private data */
struct ak4535_priv {
struct regmap *regmap;
unsigned int sysclk;
};
/*
* ak4535 register cache
*/
static const struct reg_default ak4535_reg_defaults[] = {
{ 0, 0x00 },
{ 1, 0x80 },
{ 2, 0x00 },
{ 3, 0x03 },
{ 4, 0x02 },
{ 5, 0x00 },
{ 6, 0x11 },
{ 7, 0x01 },
{ 8, 0x00 },
{ 9, 0x40 },
{ 10, 0x36 },
{ 11, 0x10 },
{ 12, 0x00 },
{ 13, 0x00 },
{ 14, 0x57 },
};
static bool ak4535_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case AK4535_STATUS:
return true;
default:
return false;
}
}
static const char *ak4535_mono_gain[] = {"+6dB", "-17dB"};
static const char *ak4535_mono_out[] = {"(L + R)/2", "Hi-Z"};
static const char *ak4535_hp_out[] = {"Stereo", "Mono"};
static const char *ak4535_deemp[] = {"44.1kHz", "Off", "48kHz", "32kHz"};
static const char *ak4535_mic_select[] = {"Internal", "External"};
static const struct soc_enum ak4535_enum[] = {
SOC_ENUM_SINGLE(AK4535_SIG1, 7, 2, ak4535_mono_gain),
SOC_ENUM_SINGLE(AK4535_SIG1, 6, 2, ak4535_mono_out),
SOC_ENUM_SINGLE(AK4535_MODE2, 2, 2, ak4535_hp_out),
SOC_ENUM_SINGLE(AK4535_DAC, 0, 4, ak4535_deemp),
SOC_ENUM_SINGLE(AK4535_MIC, 1, 2, ak4535_mic_select),
};
static const struct snd_kcontrol_new ak4535_snd_controls[] = {
SOC_SINGLE("ALC2 Switch", AK4535_SIG1, 1, 1, 0),
SOC_ENUM("Mono 1 Output", ak4535_enum[1]),
SOC_ENUM("Mono 1 Gain", ak4535_enum[0]),
SOC_ENUM("Headphone Output", ak4535_enum[2]),
SOC_ENUM("Playback Deemphasis", ak4535_enum[3]),
SOC_SINGLE("Bass Volume", AK4535_DAC, 2, 3, 0),
SOC_SINGLE("Mic Boost (+20dB) Switch", AK4535_MIC, 0, 1, 0),
SOC_ENUM("Mic Select", ak4535_enum[4]),
SOC_SINGLE("ALC Operation Time", AK4535_TIMER, 0, 3, 0),
SOC_SINGLE("ALC Recovery Time", AK4535_TIMER, 2, 3, 0),
SOC_SINGLE("ALC ZC Time", AK4535_TIMER, 4, 3, 0),
SOC_SINGLE("ALC 1 Switch", AK4535_ALC1, 5, 1, 0),
SOC_SINGLE("ALC 2 Switch", AK4535_ALC1, 6, 1, 0),
SOC_SINGLE("ALC Volume", AK4535_ALC2, 0, 127, 0),
SOC_SINGLE("Capture Volume", AK4535_PGA, 0, 127, 0),
SOC_SINGLE("Left Playback Volume", AK4535_LATT, 0, 127, 1),
SOC_SINGLE("Right Playback Volume", AK4535_RATT, 0, 127, 1),
SOC_SINGLE("AUX Bypass Volume", AK4535_VOL, 0, 15, 0),
SOC_SINGLE("Mic Sidetone Volume", AK4535_VOL, 4, 7, 0),
};
/* Mono 1 Mixer */
static const struct snd_kcontrol_new ak4535_mono1_mixer_controls[] = {
SOC_DAPM_SINGLE("Mic Sidetone Switch", AK4535_SIG1, 4, 1, 0),
SOC_DAPM_SINGLE("Mono Playback Switch", AK4535_SIG1, 5, 1, 0),
};
/* Stereo Mixer */
static const struct snd_kcontrol_new ak4535_stereo_mixer_controls[] = {
SOC_DAPM_SINGLE("Mic Sidetone Switch", AK4535_SIG2, 4, 1, 0),
SOC_DAPM_SINGLE("Playback Switch", AK4535_SIG2, 7, 1, 0),
SOC_DAPM_SINGLE("Aux Bypass Switch", AK4535_SIG2, 5, 1, 0),
};
/* Input Mixer */
static const struct snd_kcontrol_new ak4535_input_mixer_controls[] = {
SOC_DAPM_SINGLE("Mic Capture Switch", AK4535_MIC, 2, 1, 0),
SOC_DAPM_SINGLE("Aux Capture Switch", AK4535_MIC, 5, 1, 0),
};
/* Input mux */
static const struct snd_kcontrol_new ak4535_input_mux_control =
SOC_DAPM_ENUM("Input Select", ak4535_enum[4]);
/* HP L switch */
static const struct snd_kcontrol_new ak4535_hpl_control =
SOC_DAPM_SINGLE("Switch", AK4535_SIG2, 1, 1, 1);
/* HP R switch */
static const struct snd_kcontrol_new ak4535_hpr_control =
SOC_DAPM_SINGLE("Switch", AK4535_SIG2, 0, 1, 1);
/* mono 2 switch */
static const struct snd_kcontrol_new ak4535_mono2_control =
SOC_DAPM_SINGLE("Switch", AK4535_SIG1, 0, 1, 0);
/* Line out switch */
static const struct snd_kcontrol_new ak4535_line_control =
SOC_DAPM_SINGLE("Switch", AK4535_SIG2, 6, 1, 0);
/* ak4535 dapm widgets */
static const struct snd_soc_dapm_widget ak4535_dapm_widgets[] = {
SND_SOC_DAPM_MIXER("Stereo Mixer", SND_SOC_NOPM, 0, 0,
&ak4535_stereo_mixer_controls[0],
ARRAY_SIZE(ak4535_stereo_mixer_controls)),
SND_SOC_DAPM_MIXER("Mono1 Mixer", SND_SOC_NOPM, 0, 0,
&ak4535_mono1_mixer_controls[0],
ARRAY_SIZE(ak4535_mono1_mixer_controls)),
SND_SOC_DAPM_MIXER("Input Mixer", SND_SOC_NOPM, 0, 0,
&ak4535_input_mixer_controls[0],
ARRAY_SIZE(ak4535_input_mixer_controls)),
SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0,
&ak4535_input_mux_control),
SND_SOC_DAPM_DAC("DAC", "Playback", AK4535_PM2, 0, 0),
SND_SOC_DAPM_SWITCH("Mono 2 Enable", SND_SOC_NOPM, 0, 0,
&ak4535_mono2_control),
/* speaker powersave bit */
SND_SOC_DAPM_PGA("Speaker Enable", AK4535_MODE2, 0, 0, NULL, 0),
SND_SOC_DAPM_SWITCH("Line Out Enable", SND_SOC_NOPM, 0, 0,
&ak4535_line_control),
SND_SOC_DAPM_SWITCH("Left HP Enable", SND_SOC_NOPM, 0, 0,
&ak4535_hpl_control),
SND_SOC_DAPM_SWITCH("Right HP Enable", SND_SOC_NOPM, 0, 0,
&ak4535_hpr_control),
SND_SOC_DAPM_OUTPUT("LOUT"),
SND_SOC_DAPM_OUTPUT("HPL"),
SND_SOC_DAPM_OUTPUT("ROUT"),
SND_SOC_DAPM_OUTPUT("HPR"),
SND_SOC_DAPM_OUTPUT("SPP"),
SND_SOC_DAPM_OUTPUT("SPN"),
SND_SOC_DAPM_OUTPUT("MOUT1"),
SND_SOC_DAPM_OUTPUT("MOUT2"),
SND_SOC_DAPM_OUTPUT("MICOUT"),
SND_SOC_DAPM_ADC("ADC", "Capture", AK4535_PM1, 0, 0),
SND_SOC_DAPM_PGA("Spk Amp", AK4535_PM2, 3, 0, NULL, 0),
SND_SOC_DAPM_PGA("HP R Amp", AK4535_PM2, 1, 0, NULL, 0),
SND_SOC_DAPM_PGA("HP L Amp", AK4535_PM2, 2, 0, NULL, 0),
SND_SOC_DAPM_PGA("Mic", AK4535_PM1, 1, 0, NULL, 0),
SND_SOC_DAPM_PGA("Line Out", AK4535_PM1, 4, 0, NULL, 0),
SND_SOC_DAPM_PGA("Mono Out", AK4535_PM1, 3, 0, NULL, 0),
SND_SOC_DAPM_PGA("AUX In", AK4535_PM1, 2, 0, NULL, 0),
SND_SOC_DAPM_MICBIAS("Mic Int Bias", AK4535_MIC, 3, 0),
SND_SOC_DAPM_MICBIAS("Mic Ext Bias", AK4535_MIC, 4, 0),
SND_SOC_DAPM_INPUT("MICIN"),
SND_SOC_DAPM_INPUT("MICEXT"),
SND_SOC_DAPM_INPUT("AUX"),
SND_SOC_DAPM_INPUT("MIN"),
SND_SOC_DAPM_INPUT("AIN"),
};
static const struct snd_soc_dapm_route ak4535_audio_map[] = {
/*stereo mixer */
{"Stereo Mixer", "Playback Switch", "DAC"},
{"Stereo Mixer", "Mic Sidetone Switch", "Mic"},
{"Stereo Mixer", "Aux Bypass Switch", "AUX In"},
/* mono1 mixer */
{"Mono1 Mixer", "Mic Sidetone Switch", "Mic"},
{"Mono1 Mixer", "Mono Playback Switch", "DAC"},
/* Mic */
{"Mic", NULL, "AIN"},
{"Input Mux", "Internal", "Mic Int Bias"},
{"Input Mux", "External", "Mic Ext Bias"},
{"Mic Int Bias", NULL, "MICIN"},
{"Mic Ext Bias", NULL, "MICEXT"},
{"MICOUT", NULL, "Input Mux"},
/* line out */
{"LOUT", NULL, "Line Out Enable"},
{"ROUT", NULL, "Line Out Enable"},
{"Line Out Enable", "Switch", "Line Out"},
{"Line Out", NULL, "Stereo Mixer"},
/* mono1 out */
{"MOUT1", NULL, "Mono Out"},
{"Mono Out", NULL, "Mono1 Mixer"},
/* left HP */
{"HPL", NULL, "Left HP Enable"},
{"Left HP Enable", "Switch", "HP L Amp"},
{"HP L Amp", NULL, "Stereo Mixer"},
/* right HP */
{"HPR", NULL, "Right HP Enable"},
{"Right HP Enable", "Switch", "HP R Amp"},
{"HP R Amp", NULL, "Stereo Mixer"},
/* speaker */
{"SPP", NULL, "Speaker Enable"},
{"SPN", NULL, "Speaker Enable"},
{"Speaker Enable", "Switch", "Spk Amp"},
{"Spk Amp", NULL, "MIN"},
/* mono 2 */
{"MOUT2", NULL, "Mono 2 Enable"},
{"Mono 2 Enable", "Switch", "Stereo Mixer"},
/* Aux In */
{"Aux In", NULL, "AUX"},
/* ADC */
{"ADC", NULL, "Input Mixer"},
{"Input Mixer", "Mic Capture Switch", "Mic"},
{"Input Mixer", "Aux Capture Switch", "Aux In"},
};
static int ak4535_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct ak4535_priv *ak4535 = snd_soc_component_get_drvdata(component);
ak4535->sysclk = freq;
return 0;
}
static int ak4535_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct ak4535_priv *ak4535 = snd_soc_component_get_drvdata(component);
u8 mode2 = snd_soc_component_read(component, AK4535_MODE2) & ~(0x3 << 5);
int rate = params_rate(params), fs = 256;
if (rate)
fs = ak4535->sysclk / rate;
/* set fs */
switch (fs) {
case 1024:
mode2 |= (0x2 << 5);
break;
case 512:
mode2 |= (0x1 << 5);
break;
case 256:
break;
}
/* set rate */
snd_soc_component_write(component, AK4535_MODE2, mode2);
return 0;
}
static int ak4535_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
u8 mode1 = 0;
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
mode1 = 0x0002;
break;
case SND_SOC_DAIFMT_LEFT_J:
mode1 = 0x0001;
break;
default:
return -EINVAL;
}
/* use 32 fs for BCLK to save power */
mode1 |= 0x4;
snd_soc_component_write(component, AK4535_MODE1, mode1);
return 0;
}
static int ak4535_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
u16 mute_reg = snd_soc_component_read(component, AK4535_DAC);
if (!mute)
snd_soc_component_write(component, AK4535_DAC, mute_reg & ~0x20);
else
snd_soc_component_write(component, AK4535_DAC, mute_reg | 0x20);
return 0;
}
static int ak4535_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
switch (level) {
case SND_SOC_BIAS_ON:
snd_soc_component_update_bits(component, AK4535_DAC, 0x20, 0);
break;
case SND_SOC_BIAS_PREPARE:
snd_soc_component_update_bits(component, AK4535_DAC, 0x20, 0x20);
break;
case SND_SOC_BIAS_STANDBY:
snd_soc_component_update_bits(component, AK4535_PM1, 0x80, 0x80);
snd_soc_component_update_bits(component, AK4535_PM2, 0x80, 0);
break;
case SND_SOC_BIAS_OFF:
snd_soc_component_update_bits(component, AK4535_PM1, 0x80, 0);
break;
}
return 0;
}
#define AK4535_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
static const struct snd_soc_dai_ops ak4535_dai_ops = {
.hw_params = ak4535_hw_params,
.set_fmt = ak4535_set_dai_fmt,
.mute_stream = ak4535_mute,
.set_sysclk = ak4535_set_dai_sysclk,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver ak4535_dai = {
.name = "ak4535-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = AK4535_RATES,
.formats = SNDRV_PCM_FMTBIT_S16_LE,},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = AK4535_RATES,
.formats = SNDRV_PCM_FMTBIT_S16_LE,},
.ops = &ak4535_dai_ops,
};
static int ak4535_resume(struct snd_soc_component *component)
{
snd_soc_component_cache_sync(component);
return 0;
}
static const struct regmap_config ak4535_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = AK4535_STATUS,
.volatile_reg = ak4535_volatile,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = ak4535_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(ak4535_reg_defaults),
};
static const struct snd_soc_component_driver soc_component_dev_ak4535 = {
.resume = ak4535_resume,
.set_bias_level = ak4535_set_bias_level,
.controls = ak4535_snd_controls,
.num_controls = ARRAY_SIZE(ak4535_snd_controls),
.dapm_widgets = ak4535_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(ak4535_dapm_widgets),
.dapm_routes = ak4535_audio_map,
.num_dapm_routes = ARRAY_SIZE(ak4535_audio_map),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int ak4535_i2c_probe(struct i2c_client *i2c)
{
struct ak4535_priv *ak4535;
int ret;
ak4535 = devm_kzalloc(&i2c->dev, sizeof(struct ak4535_priv),
GFP_KERNEL);
if (ak4535 == NULL)
return -ENOMEM;
ak4535->regmap = devm_regmap_init_i2c(i2c, &ak4535_regmap);
if (IS_ERR(ak4535->regmap)) {
ret = PTR_ERR(ak4535->regmap);
dev_err(&i2c->dev, "Failed to init regmap: %d\n", ret);
return ret;
}
i2c_set_clientdata(i2c, ak4535);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_ak4535, &ak4535_dai, 1);
return ret;
}
static const struct i2c_device_id ak4535_i2c_id[] = {
{ "ak4535", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, ak4535_i2c_id);
static struct i2c_driver ak4535_i2c_driver = {
.driver = {
.name = "ak4535",
},
.probe = ak4535_i2c_probe,
.id_table = ak4535_i2c_id,
};
module_i2c_driver(ak4535_i2c_driver);
MODULE_DESCRIPTION("Soc AK4535 driver");
MODULE_AUTHOR("Richard Purdie");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/ak4535.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* da732x.c --- Dialog DA732X ALSA SoC Audio Driver
*
* Copyright (C) 2012 Dialog Semiconductor GmbH
*
* Author: Michal Hajduk <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <asm/div64.h>
#include "da732x.h"
#include "da732x_reg.h"
struct da732x_priv {
struct regmap *regmap;
unsigned int sysclk;
bool pll_en;
};
/*
* da732x register cache - default settings
*/
static const struct reg_default da732x_reg_cache[] = {
{ DA732X_REG_REF1 , 0x02 },
{ DA732X_REG_BIAS_EN , 0x80 },
{ DA732X_REG_BIAS1 , 0x00 },
{ DA732X_REG_BIAS2 , 0x00 },
{ DA732X_REG_BIAS3 , 0x00 },
{ DA732X_REG_BIAS4 , 0x00 },
{ DA732X_REG_MICBIAS2 , 0x00 },
{ DA732X_REG_MICBIAS1 , 0x00 },
{ DA732X_REG_MICDET , 0x00 },
{ DA732X_REG_MIC1_PRE , 0x01 },
{ DA732X_REG_MIC1 , 0x40 },
{ DA732X_REG_MIC2_PRE , 0x01 },
{ DA732X_REG_MIC2 , 0x40 },
{ DA732X_REG_AUX1L , 0x75 },
{ DA732X_REG_AUX1R , 0x75 },
{ DA732X_REG_MIC3_PRE , 0x01 },
{ DA732X_REG_MIC3 , 0x40 },
{ DA732X_REG_INP_PINBIAS , 0x00 },
{ DA732X_REG_INP_ZC_EN , 0x00 },
{ DA732X_REG_INP_MUX , 0x50 },
{ DA732X_REG_HP_DET , 0x00 },
{ DA732X_REG_HPL_DAC_OFFSET , 0x00 },
{ DA732X_REG_HPL_DAC_OFF_CNTL , 0x00 },
{ DA732X_REG_HPL_OUT_OFFSET , 0x00 },
{ DA732X_REG_HPL , 0x40 },
{ DA732X_REG_HPL_VOL , 0x0F },
{ DA732X_REG_HPR_DAC_OFFSET , 0x00 },
{ DA732X_REG_HPR_DAC_OFF_CNTL , 0x00 },
{ DA732X_REG_HPR_OUT_OFFSET , 0x00 },
{ DA732X_REG_HPR , 0x40 },
{ DA732X_REG_HPR_VOL , 0x0F },
{ DA732X_REG_LIN2 , 0x4F },
{ DA732X_REG_LIN3 , 0x4F },
{ DA732X_REG_LIN4 , 0x4F },
{ DA732X_REG_OUT_ZC_EN , 0x00 },
{ DA732X_REG_HP_LIN1_GNDSEL , 0x00 },
{ DA732X_REG_CP_HP1 , 0x0C },
{ DA732X_REG_CP_HP2 , 0x03 },
{ DA732X_REG_CP_CTRL1 , 0x00 },
{ DA732X_REG_CP_CTRL2 , 0x99 },
{ DA732X_REG_CP_CTRL3 , 0x25 },
{ DA732X_REG_CP_LEVEL_MASK , 0x3F },
{ DA732X_REG_CP_DET , 0x00 },
{ DA732X_REG_CP_STATUS , 0x00 },
{ DA732X_REG_CP_THRESH1 , 0x00 },
{ DA732X_REG_CP_THRESH2 , 0x00 },
{ DA732X_REG_CP_THRESH3 , 0x00 },
{ DA732X_REG_CP_THRESH4 , 0x00 },
{ DA732X_REG_CP_THRESH5 , 0x00 },
{ DA732X_REG_CP_THRESH6 , 0x00 },
{ DA732X_REG_CP_THRESH7 , 0x00 },
{ DA732X_REG_CP_THRESH8 , 0x00 },
{ DA732X_REG_PLL_DIV_LO , 0x00 },
{ DA732X_REG_PLL_DIV_MID , 0x00 },
{ DA732X_REG_PLL_DIV_HI , 0x00 },
{ DA732X_REG_PLL_CTRL , 0x02 },
{ DA732X_REG_CLK_CTRL , 0xaa },
{ DA732X_REG_CLK_DSP , 0x07 },
{ DA732X_REG_CLK_EN1 , 0x00 },
{ DA732X_REG_CLK_EN2 , 0x00 },
{ DA732X_REG_CLK_EN3 , 0x00 },
{ DA732X_REG_CLK_EN4 , 0x00 },
{ DA732X_REG_CLK_EN5 , 0x00 },
{ DA732X_REG_AIF_MCLK , 0x00 },
{ DA732X_REG_AIFA1 , 0x02 },
{ DA732X_REG_AIFA2 , 0x00 },
{ DA732X_REG_AIFA3 , 0x08 },
{ DA732X_REG_AIFB1 , 0x02 },
{ DA732X_REG_AIFB2 , 0x00 },
{ DA732X_REG_AIFB3 , 0x08 },
{ DA732X_REG_PC_CTRL , 0xC0 },
{ DA732X_REG_DATA_ROUTE , 0x00 },
{ DA732X_REG_DSP_CTRL , 0x00 },
{ DA732X_REG_CIF_CTRL2 , 0x00 },
{ DA732X_REG_HANDSHAKE , 0x00 },
{ DA732X_REG_SPARE1_OUT , 0x00 },
{ DA732X_REG_SPARE2_OUT , 0x00 },
{ DA732X_REG_SPARE1_IN , 0x00 },
{ DA732X_REG_ADC1_PD , 0x00 },
{ DA732X_REG_ADC1_HPF , 0x00 },
{ DA732X_REG_ADC1_SEL , 0x00 },
{ DA732X_REG_ADC1_EQ12 , 0x00 },
{ DA732X_REG_ADC1_EQ34 , 0x00 },
{ DA732X_REG_ADC1_EQ5 , 0x00 },
{ DA732X_REG_ADC2_PD , 0x00 },
{ DA732X_REG_ADC2_HPF , 0x00 },
{ DA732X_REG_ADC2_SEL , 0x00 },
{ DA732X_REG_ADC2_EQ12 , 0x00 },
{ DA732X_REG_ADC2_EQ34 , 0x00 },
{ DA732X_REG_ADC2_EQ5 , 0x00 },
{ DA732X_REG_DAC1_HPF , 0x00 },
{ DA732X_REG_DAC1_L_VOL , 0x00 },
{ DA732X_REG_DAC1_R_VOL , 0x00 },
{ DA732X_REG_DAC1_SEL , 0x00 },
{ DA732X_REG_DAC1_SOFTMUTE , 0x00 },
{ DA732X_REG_DAC1_EQ12 , 0x00 },
{ DA732X_REG_DAC1_EQ34 , 0x00 },
{ DA732X_REG_DAC1_EQ5 , 0x00 },
{ DA732X_REG_DAC2_HPF , 0x00 },
{ DA732X_REG_DAC2_L_VOL , 0x00 },
{ DA732X_REG_DAC2_R_VOL , 0x00 },
{ DA732X_REG_DAC2_SEL , 0x00 },
{ DA732X_REG_DAC2_SOFTMUTE , 0x00 },
{ DA732X_REG_DAC2_EQ12 , 0x00 },
{ DA732X_REG_DAC2_EQ34 , 0x00 },
{ DA732X_REG_DAC2_EQ5 , 0x00 },
{ DA732X_REG_DAC3_HPF , 0x00 },
{ DA732X_REG_DAC3_VOL , 0x00 },
{ DA732X_REG_DAC3_SEL , 0x00 },
{ DA732X_REG_DAC3_SOFTMUTE , 0x00 },
{ DA732X_REG_DAC3_EQ12 , 0x00 },
{ DA732X_REG_DAC3_EQ34 , 0x00 },
{ DA732X_REG_DAC3_EQ5 , 0x00 },
{ DA732X_REG_BIQ_BYP , 0x00 },
{ DA732X_REG_DMA_CMD , 0x00 },
{ DA732X_REG_DMA_ADDR0 , 0x00 },
{ DA732X_REG_DMA_ADDR1 , 0x00 },
{ DA732X_REG_DMA_DATA0 , 0x00 },
{ DA732X_REG_DMA_DATA1 , 0x00 },
{ DA732X_REG_DMA_DATA2 , 0x00 },
{ DA732X_REG_DMA_DATA3 , 0x00 },
{ DA732X_REG_UNLOCK , 0x00 },
};
static inline int da732x_get_input_div(struct snd_soc_component *component, int sysclk)
{
int val;
if (sysclk < DA732X_MCLK_10MHZ) {
val = DA732X_MCLK_VAL_0_10MHZ;
} else if ((sysclk >= DA732X_MCLK_10MHZ) &&
(sysclk < DA732X_MCLK_20MHZ)) {
val = DA732X_MCLK_VAL_10_20MHZ;
} else if ((sysclk >= DA732X_MCLK_20MHZ) &&
(sysclk < DA732X_MCLK_40MHZ)) {
val = DA732X_MCLK_VAL_20_40MHZ;
} else if ((sysclk >= DA732X_MCLK_40MHZ) &&
(sysclk <= DA732X_MCLK_54MHZ)) {
val = DA732X_MCLK_VAL_40_54MHZ;
} else {
return -EINVAL;
}
snd_soc_component_write(component, DA732X_REG_PLL_CTRL, val);
return val;
}
static void da732x_set_charge_pump(struct snd_soc_component *component, int state)
{
switch (state) {
case DA732X_ENABLE_CP:
snd_soc_component_write(component, DA732X_REG_CLK_EN2, DA732X_CP_CLK_EN);
snd_soc_component_write(component, DA732X_REG_CP_HP2, DA732X_HP_CP_EN |
DA732X_HP_CP_REG | DA732X_HP_CP_PULSESKIP);
snd_soc_component_write(component, DA732X_REG_CP_CTRL1, DA732X_CP_EN |
DA732X_CP_CTRL_CPVDD1);
snd_soc_component_write(component, DA732X_REG_CP_CTRL2,
DA732X_CP_MANAGE_MAGNITUDE | DA732X_CP_BOOST);
snd_soc_component_write(component, DA732X_REG_CP_CTRL3, DA732X_CP_1MHZ);
break;
case DA732X_DISABLE_CP:
snd_soc_component_write(component, DA732X_REG_CLK_EN2, DA732X_CP_CLK_DIS);
snd_soc_component_write(component, DA732X_REG_CP_HP2, DA732X_HP_CP_DIS);
snd_soc_component_write(component, DA732X_REG_CP_CTRL1, DA723X_CP_DIS);
break;
default:
pr_err("Wrong charge pump state\n");
break;
}
}
static const DECLARE_TLV_DB_SCALE(mic_boost_tlv, DA732X_MIC_PRE_VOL_DB_MIN,
DA732X_MIC_PRE_VOL_DB_INC, 0);
static const DECLARE_TLV_DB_SCALE(mic_pga_tlv, DA732X_MIC_VOL_DB_MIN,
DA732X_MIC_VOL_DB_INC, 0);
static const DECLARE_TLV_DB_SCALE(aux_pga_tlv, DA732X_AUX_VOL_DB_MIN,
DA732X_AUX_VOL_DB_INC, 0);
static const DECLARE_TLV_DB_SCALE(hp_pga_tlv, DA732X_HP_VOL_DB_MIN,
DA732X_AUX_VOL_DB_INC, 0);
static const DECLARE_TLV_DB_SCALE(lin2_pga_tlv, DA732X_LIN2_VOL_DB_MIN,
DA732X_LIN2_VOL_DB_INC, 0);
static const DECLARE_TLV_DB_SCALE(lin3_pga_tlv, DA732X_LIN3_VOL_DB_MIN,
DA732X_LIN3_VOL_DB_INC, 0);
static const DECLARE_TLV_DB_SCALE(lin4_pga_tlv, DA732X_LIN4_VOL_DB_MIN,
DA732X_LIN4_VOL_DB_INC, 0);
static const DECLARE_TLV_DB_SCALE(adc_pga_tlv, DA732X_ADC_VOL_DB_MIN,
DA732X_ADC_VOL_DB_INC, 0);
static const DECLARE_TLV_DB_SCALE(dac_pga_tlv, DA732X_DAC_VOL_DB_MIN,
DA732X_DAC_VOL_DB_INC, 0);
static const DECLARE_TLV_DB_SCALE(eq_band_pga_tlv, DA732X_EQ_BAND_VOL_DB_MIN,
DA732X_EQ_BAND_VOL_DB_INC, 0);
static const DECLARE_TLV_DB_SCALE(eq_overall_tlv, DA732X_EQ_OVERALL_VOL_DB_MIN,
DA732X_EQ_OVERALL_VOL_DB_INC, 0);
/* High Pass Filter */
static const char *da732x_hpf_mode[] = {
"Disable", "Music", "Voice",
};
static const char *da732x_hpf_music[] = {
"1.8Hz", "3.75Hz", "7.5Hz", "15Hz",
};
static const char *da732x_hpf_voice[] = {
"2.5Hz", "25Hz", "50Hz", "100Hz",
"150Hz", "200Hz", "300Hz", "400Hz"
};
static SOC_ENUM_SINGLE_DECL(da732x_dac1_hpf_mode_enum,
DA732X_REG_DAC1_HPF, DA732X_HPF_MODE_SHIFT,
da732x_hpf_mode);
static SOC_ENUM_SINGLE_DECL(da732x_dac2_hpf_mode_enum,
DA732X_REG_DAC2_HPF, DA732X_HPF_MODE_SHIFT,
da732x_hpf_mode);
static SOC_ENUM_SINGLE_DECL(da732x_dac3_hpf_mode_enum,
DA732X_REG_DAC3_HPF, DA732X_HPF_MODE_SHIFT,
da732x_hpf_mode);
static SOC_ENUM_SINGLE_DECL(da732x_adc1_hpf_mode_enum,
DA732X_REG_ADC1_HPF, DA732X_HPF_MODE_SHIFT,
da732x_hpf_mode);
static SOC_ENUM_SINGLE_DECL(da732x_adc2_hpf_mode_enum,
DA732X_REG_ADC2_HPF, DA732X_HPF_MODE_SHIFT,
da732x_hpf_mode);
static SOC_ENUM_SINGLE_DECL(da732x_dac1_hp_filter_enum,
DA732X_REG_DAC1_HPF, DA732X_HPF_MUSIC_SHIFT,
da732x_hpf_music);
static SOC_ENUM_SINGLE_DECL(da732x_dac2_hp_filter_enum,
DA732X_REG_DAC2_HPF, DA732X_HPF_MUSIC_SHIFT,
da732x_hpf_music);
static SOC_ENUM_SINGLE_DECL(da732x_dac3_hp_filter_enum,
DA732X_REG_DAC3_HPF, DA732X_HPF_MUSIC_SHIFT,
da732x_hpf_music);
static SOC_ENUM_SINGLE_DECL(da732x_adc1_hp_filter_enum,
DA732X_REG_ADC1_HPF, DA732X_HPF_MUSIC_SHIFT,
da732x_hpf_music);
static SOC_ENUM_SINGLE_DECL(da732x_adc2_hp_filter_enum,
DA732X_REG_ADC2_HPF, DA732X_HPF_MUSIC_SHIFT,
da732x_hpf_music);
static SOC_ENUM_SINGLE_DECL(da732x_dac1_voice_filter_enum,
DA732X_REG_DAC1_HPF, DA732X_HPF_VOICE_SHIFT,
da732x_hpf_voice);
static SOC_ENUM_SINGLE_DECL(da732x_dac2_voice_filter_enum,
DA732X_REG_DAC2_HPF, DA732X_HPF_VOICE_SHIFT,
da732x_hpf_voice);
static SOC_ENUM_SINGLE_DECL(da732x_dac3_voice_filter_enum,
DA732X_REG_DAC3_HPF, DA732X_HPF_VOICE_SHIFT,
da732x_hpf_voice);
static SOC_ENUM_SINGLE_DECL(da732x_adc1_voice_filter_enum,
DA732X_REG_ADC1_HPF, DA732X_HPF_VOICE_SHIFT,
da732x_hpf_voice);
static SOC_ENUM_SINGLE_DECL(da732x_adc2_voice_filter_enum,
DA732X_REG_ADC2_HPF, DA732X_HPF_VOICE_SHIFT,
da732x_hpf_voice);
static int da732x_hpf_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct soc_enum *enum_ctrl = (struct soc_enum *)kcontrol->private_value;
unsigned int reg = enum_ctrl->reg;
unsigned int sel = ucontrol->value.enumerated.item[0];
unsigned int bits;
switch (sel) {
case DA732X_HPF_DISABLED:
bits = DA732X_HPF_DIS;
break;
case DA732X_HPF_VOICE:
bits = DA732X_HPF_VOICE_EN;
break;
case DA732X_HPF_MUSIC:
bits = DA732X_HPF_MUSIC_EN;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, reg, DA732X_HPF_MASK, bits);
return 0;
}
static int da732x_hpf_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct soc_enum *enum_ctrl = (struct soc_enum *)kcontrol->private_value;
unsigned int reg = enum_ctrl->reg;
int val;
val = snd_soc_component_read(component, reg) & DA732X_HPF_MASK;
switch (val) {
case DA732X_HPF_VOICE_EN:
ucontrol->value.enumerated.item[0] = DA732X_HPF_VOICE;
break;
case DA732X_HPF_MUSIC_EN:
ucontrol->value.enumerated.item[0] = DA732X_HPF_MUSIC;
break;
default:
ucontrol->value.enumerated.item[0] = DA732X_HPF_DISABLED;
break;
}
return 0;
}
static const struct snd_kcontrol_new da732x_snd_controls[] = {
/* Input PGAs */
SOC_SINGLE_RANGE_TLV("MIC1 Boost Volume", DA732X_REG_MIC1_PRE,
DA732X_MICBOOST_SHIFT, DA732X_MICBOOST_MIN,
DA732X_MICBOOST_MAX, 0, mic_boost_tlv),
SOC_SINGLE_RANGE_TLV("MIC2 Boost Volume", DA732X_REG_MIC2_PRE,
DA732X_MICBOOST_SHIFT, DA732X_MICBOOST_MIN,
DA732X_MICBOOST_MAX, 0, mic_boost_tlv),
SOC_SINGLE_RANGE_TLV("MIC3 Boost Volume", DA732X_REG_MIC3_PRE,
DA732X_MICBOOST_SHIFT, DA732X_MICBOOST_MIN,
DA732X_MICBOOST_MAX, 0, mic_boost_tlv),
/* MICs */
SOC_SINGLE("MIC1 Switch", DA732X_REG_MIC1, DA732X_MIC_MUTE_SHIFT,
DA732X_SWITCH_MAX, DA732X_INVERT),
SOC_SINGLE_RANGE_TLV("MIC1 Volume", DA732X_REG_MIC1,
DA732X_MIC_VOL_SHIFT, DA732X_MIC_VOL_VAL_MIN,
DA732X_MIC_VOL_VAL_MAX, 0, mic_pga_tlv),
SOC_SINGLE("MIC2 Switch", DA732X_REG_MIC2, DA732X_MIC_MUTE_SHIFT,
DA732X_SWITCH_MAX, DA732X_INVERT),
SOC_SINGLE_RANGE_TLV("MIC2 Volume", DA732X_REG_MIC2,
DA732X_MIC_VOL_SHIFT, DA732X_MIC_VOL_VAL_MIN,
DA732X_MIC_VOL_VAL_MAX, 0, mic_pga_tlv),
SOC_SINGLE("MIC3 Switch", DA732X_REG_MIC3, DA732X_MIC_MUTE_SHIFT,
DA732X_SWITCH_MAX, DA732X_INVERT),
SOC_SINGLE_RANGE_TLV("MIC3 Volume", DA732X_REG_MIC3,
DA732X_MIC_VOL_SHIFT, DA732X_MIC_VOL_VAL_MIN,
DA732X_MIC_VOL_VAL_MAX, 0, mic_pga_tlv),
/* AUXs */
SOC_SINGLE("AUX1L Switch", DA732X_REG_AUX1L, DA732X_AUX_MUTE_SHIFT,
DA732X_SWITCH_MAX, DA732X_INVERT),
SOC_SINGLE_TLV("AUX1L Volume", DA732X_REG_AUX1L,
DA732X_AUX_VOL_SHIFT, DA732X_AUX_VOL_VAL_MAX,
DA732X_NO_INVERT, aux_pga_tlv),
SOC_SINGLE("AUX1R Switch", DA732X_REG_AUX1R, DA732X_AUX_MUTE_SHIFT,
DA732X_SWITCH_MAX, DA732X_INVERT),
SOC_SINGLE_TLV("AUX1R Volume", DA732X_REG_AUX1R,
DA732X_AUX_VOL_SHIFT, DA732X_AUX_VOL_VAL_MAX,
DA732X_NO_INVERT, aux_pga_tlv),
/* ADCs */
SOC_DOUBLE_TLV("ADC1 Volume", DA732X_REG_ADC1_SEL,
DA732X_ADCL_VOL_SHIFT, DA732X_ADCR_VOL_SHIFT,
DA732X_ADC_VOL_VAL_MAX, DA732X_INVERT, adc_pga_tlv),
SOC_DOUBLE_TLV("ADC2 Volume", DA732X_REG_ADC2_SEL,
DA732X_ADCL_VOL_SHIFT, DA732X_ADCR_VOL_SHIFT,
DA732X_ADC_VOL_VAL_MAX, DA732X_INVERT, adc_pga_tlv),
/* DACs */
SOC_DOUBLE("Digital Playback DAC12 Switch", DA732X_REG_DAC1_SEL,
DA732X_DACL_MUTE_SHIFT, DA732X_DACR_MUTE_SHIFT,
DA732X_SWITCH_MAX, DA732X_INVERT),
SOC_DOUBLE_R_TLV("Digital Playback DAC12 Volume", DA732X_REG_DAC1_L_VOL,
DA732X_REG_DAC1_R_VOL, DA732X_DAC_VOL_SHIFT,
DA732X_DAC_VOL_VAL_MAX, DA732X_INVERT, dac_pga_tlv),
SOC_SINGLE("Digital Playback DAC3 Switch", DA732X_REG_DAC2_SEL,
DA732X_DACL_MUTE_SHIFT, DA732X_SWITCH_MAX, DA732X_INVERT),
SOC_SINGLE_TLV("Digital Playback DAC3 Volume", DA732X_REG_DAC2_L_VOL,
DA732X_DAC_VOL_SHIFT, DA732X_DAC_VOL_VAL_MAX,
DA732X_INVERT, dac_pga_tlv),
SOC_SINGLE("Digital Playback DAC4 Switch", DA732X_REG_DAC2_SEL,
DA732X_DACR_MUTE_SHIFT, DA732X_SWITCH_MAX, DA732X_INVERT),
SOC_SINGLE_TLV("Digital Playback DAC4 Volume", DA732X_REG_DAC2_R_VOL,
DA732X_DAC_VOL_SHIFT, DA732X_DAC_VOL_VAL_MAX,
DA732X_INVERT, dac_pga_tlv),
SOC_SINGLE("Digital Playback DAC5 Switch", DA732X_REG_DAC3_SEL,
DA732X_DACL_MUTE_SHIFT, DA732X_SWITCH_MAX, DA732X_INVERT),
SOC_SINGLE_TLV("Digital Playback DAC5 Volume", DA732X_REG_DAC3_VOL,
DA732X_DAC_VOL_SHIFT, DA732X_DAC_VOL_VAL_MAX,
DA732X_INVERT, dac_pga_tlv),
/* High Pass Filters */
SOC_ENUM_EXT("DAC1 High Pass Filter Mode",
da732x_dac1_hpf_mode_enum, da732x_hpf_get, da732x_hpf_set),
SOC_ENUM("DAC1 High Pass Filter", da732x_dac1_hp_filter_enum),
SOC_ENUM("DAC1 Voice Filter", da732x_dac1_voice_filter_enum),
SOC_ENUM_EXT("DAC2 High Pass Filter Mode",
da732x_dac2_hpf_mode_enum, da732x_hpf_get, da732x_hpf_set),
SOC_ENUM("DAC2 High Pass Filter", da732x_dac2_hp_filter_enum),
SOC_ENUM("DAC2 Voice Filter", da732x_dac2_voice_filter_enum),
SOC_ENUM_EXT("DAC3 High Pass Filter Mode",
da732x_dac3_hpf_mode_enum, da732x_hpf_get, da732x_hpf_set),
SOC_ENUM("DAC3 High Pass Filter", da732x_dac3_hp_filter_enum),
SOC_ENUM("DAC3 Filter Mode", da732x_dac3_voice_filter_enum),
SOC_ENUM_EXT("ADC1 High Pass Filter Mode",
da732x_adc1_hpf_mode_enum, da732x_hpf_get, da732x_hpf_set),
SOC_ENUM("ADC1 High Pass Filter", da732x_adc1_hp_filter_enum),
SOC_ENUM("ADC1 Voice Filter", da732x_adc1_voice_filter_enum),
SOC_ENUM_EXT("ADC2 High Pass Filter Mode",
da732x_adc2_hpf_mode_enum, da732x_hpf_get, da732x_hpf_set),
SOC_ENUM("ADC2 High Pass Filter", da732x_adc2_hp_filter_enum),
SOC_ENUM("ADC2 Voice Filter", da732x_adc2_voice_filter_enum),
/* Equalizers */
SOC_SINGLE("ADC1 EQ Switch", DA732X_REG_ADC1_EQ5,
DA732X_EQ_EN_SHIFT, DA732X_EQ_EN_MAX, DA732X_NO_INVERT),
SOC_SINGLE_TLV("ADC1 EQ Band 1 Volume", DA732X_REG_ADC1_EQ12,
DA732X_EQ_BAND1_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("ADC1 EQ Band 2 Volume", DA732X_REG_ADC1_EQ12,
DA732X_EQ_BAND2_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("ADC1 EQ Band 3 Volume", DA732X_REG_ADC1_EQ34,
DA732X_EQ_BAND3_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("ADC1 EQ Band 4 Volume", DA732X_REG_ADC1_EQ34,
DA732X_EQ_BAND4_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("ADC1 EQ Band 5 Volume", DA732X_REG_ADC1_EQ5,
DA732X_EQ_BAND5_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("ADC1 EQ Overall Volume", DA732X_REG_ADC1_EQ5,
DA732X_EQ_OVERALL_SHIFT, DA732X_EQ_OVERALL_VOL_VAL_MAX,
DA732X_INVERT, eq_overall_tlv),
SOC_SINGLE("ADC2 EQ Switch", DA732X_REG_ADC2_EQ5,
DA732X_EQ_EN_SHIFT, DA732X_EQ_EN_MAX, DA732X_NO_INVERT),
SOC_SINGLE_TLV("ADC2 EQ Band 1 Volume", DA732X_REG_ADC2_EQ12,
DA732X_EQ_BAND1_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("ADC2 EQ Band 2 Volume", DA732X_REG_ADC2_EQ12,
DA732X_EQ_BAND2_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("ADC2 EQ Band 3 Volume", DA732X_REG_ADC2_EQ34,
DA732X_EQ_BAND3_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("ACD2 EQ Band 4 Volume", DA732X_REG_ADC2_EQ34,
DA732X_EQ_BAND4_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("ACD2 EQ Band 5 Volume", DA732X_REG_ADC2_EQ5,
DA732X_EQ_BAND5_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("ADC2 EQ Overall Volume", DA732X_REG_ADC1_EQ5,
DA732X_EQ_OVERALL_SHIFT, DA732X_EQ_OVERALL_VOL_VAL_MAX,
DA732X_INVERT, eq_overall_tlv),
SOC_SINGLE("DAC1 EQ Switch", DA732X_REG_DAC1_EQ5,
DA732X_EQ_EN_SHIFT, DA732X_EQ_EN_MAX, DA732X_NO_INVERT),
SOC_SINGLE_TLV("DAC1 EQ Band 1 Volume", DA732X_REG_DAC1_EQ12,
DA732X_EQ_BAND1_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("DAC1 EQ Band 2 Volume", DA732X_REG_DAC1_EQ12,
DA732X_EQ_BAND2_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("DAC1 EQ Band 3 Volume", DA732X_REG_DAC1_EQ34,
DA732X_EQ_BAND3_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("DAC1 EQ Band 4 Volume", DA732X_REG_DAC1_EQ34,
DA732X_EQ_BAND4_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("DAC1 EQ Band 5 Volume", DA732X_REG_DAC1_EQ5,
DA732X_EQ_BAND5_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE("DAC2 EQ Switch", DA732X_REG_DAC2_EQ5,
DA732X_EQ_EN_SHIFT, DA732X_EQ_EN_MAX, DA732X_NO_INVERT),
SOC_SINGLE_TLV("DAC2 EQ Band 1 Volume", DA732X_REG_DAC2_EQ12,
DA732X_EQ_BAND1_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("DAC2 EQ Band 2 Volume", DA732X_REG_DAC2_EQ12,
DA732X_EQ_BAND2_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("DAC2 EQ Band 3 Volume", DA732X_REG_DAC2_EQ34,
DA732X_EQ_BAND3_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("DAC2 EQ Band 4 Volume", DA732X_REG_DAC2_EQ34,
DA732X_EQ_BAND4_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("DAC2 EQ Band 5 Volume", DA732X_REG_DAC2_EQ5,
DA732X_EQ_BAND5_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE("DAC3 EQ Switch", DA732X_REG_DAC3_EQ5,
DA732X_EQ_EN_SHIFT, DA732X_EQ_EN_MAX, DA732X_NO_INVERT),
SOC_SINGLE_TLV("DAC3 EQ Band 1 Volume", DA732X_REG_DAC3_EQ12,
DA732X_EQ_BAND1_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("DAC3 EQ Band 2 Volume", DA732X_REG_DAC3_EQ12,
DA732X_EQ_BAND2_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("DAC3 EQ Band 3 Volume", DA732X_REG_DAC3_EQ34,
DA732X_EQ_BAND3_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("DAC3 EQ Band 4 Volume", DA732X_REG_DAC3_EQ34,
DA732X_EQ_BAND4_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("DAC3 EQ Band 5 Volume", DA732X_REG_DAC3_EQ5,
DA732X_EQ_BAND5_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
/* Lineout 2 Reciever*/
SOC_SINGLE("Lineout 2 Switch", DA732X_REG_LIN2, DA732X_LOUT_MUTE_SHIFT,
DA732X_SWITCH_MAX, DA732X_INVERT),
SOC_SINGLE_TLV("Lineout 2 Volume", DA732X_REG_LIN2,
DA732X_LOUT_VOL_SHIFT, DA732X_LOUT_VOL_VAL_MAX,
DA732X_NO_INVERT, lin2_pga_tlv),
/* Lineout 3 SPEAKER*/
SOC_SINGLE("Lineout 3 Switch", DA732X_REG_LIN3, DA732X_LOUT_MUTE_SHIFT,
DA732X_SWITCH_MAX, DA732X_INVERT),
SOC_SINGLE_TLV("Lineout 3 Volume", DA732X_REG_LIN3,
DA732X_LOUT_VOL_SHIFT, DA732X_LOUT_VOL_VAL_MAX,
DA732X_NO_INVERT, lin3_pga_tlv),
/* Lineout 4 */
SOC_SINGLE("Lineout 4 Switch", DA732X_REG_LIN4, DA732X_LOUT_MUTE_SHIFT,
DA732X_SWITCH_MAX, DA732X_INVERT),
SOC_SINGLE_TLV("Lineout 4 Volume", DA732X_REG_LIN4,
DA732X_LOUT_VOL_SHIFT, DA732X_LOUT_VOL_VAL_MAX,
DA732X_NO_INVERT, lin4_pga_tlv),
/* Headphones */
SOC_DOUBLE_R("Headphone Switch", DA732X_REG_HPR, DA732X_REG_HPL,
DA732X_HP_MUTE_SHIFT, DA732X_SWITCH_MAX, DA732X_INVERT),
SOC_DOUBLE_R_TLV("Headphone Volume", DA732X_REG_HPL_VOL,
DA732X_REG_HPR_VOL, DA732X_HP_VOL_SHIFT,
DA732X_HP_VOL_VAL_MAX, DA732X_NO_INVERT, hp_pga_tlv),
};
static int da732x_adc_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
switch (w->reg) {
case DA732X_REG_ADC1_PD:
snd_soc_component_update_bits(component, DA732X_REG_CLK_EN3,
DA732X_ADCA_BB_CLK_EN,
DA732X_ADCA_BB_CLK_EN);
break;
case DA732X_REG_ADC2_PD:
snd_soc_component_update_bits(component, DA732X_REG_CLK_EN3,
DA732X_ADCC_BB_CLK_EN,
DA732X_ADCC_BB_CLK_EN);
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, w->reg, DA732X_ADC_RST_MASK,
DA732X_ADC_SET_ACT);
snd_soc_component_update_bits(component, w->reg, DA732X_ADC_PD_MASK,
DA732X_ADC_ON);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component, w->reg, DA732X_ADC_PD_MASK,
DA732X_ADC_OFF);
snd_soc_component_update_bits(component, w->reg, DA732X_ADC_RST_MASK,
DA732X_ADC_SET_RST);
switch (w->reg) {
case DA732X_REG_ADC1_PD:
snd_soc_component_update_bits(component, DA732X_REG_CLK_EN3,
DA732X_ADCA_BB_CLK_EN, 0);
break;
case DA732X_REG_ADC2_PD:
snd_soc_component_update_bits(component, DA732X_REG_CLK_EN3,
DA732X_ADCC_BB_CLK_EN, 0);
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
return 0;
}
static int da732x_out_pga_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(component, w->reg,
(1 << w->shift) | DA732X_OUT_HIZ_EN,
(1 << w->shift) | DA732X_OUT_HIZ_EN);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component, w->reg,
(1 << w->shift) | DA732X_OUT_HIZ_EN,
(1 << w->shift) | DA732X_OUT_HIZ_DIS);
break;
default:
return -EINVAL;
}
return 0;
}
static const char *adcl_text[] = {
"AUX1L", "MIC1"
};
static const char *adcr_text[] = {
"AUX1R", "MIC2", "MIC3"
};
static const char *enable_text[] = {
"Disabled",
"Enabled"
};
/* ADC1LMUX */
static SOC_ENUM_SINGLE_DECL(adc1l_enum,
DA732X_REG_INP_MUX, DA732X_ADC1L_MUX_SEL_SHIFT,
adcl_text);
static const struct snd_kcontrol_new adc1l_mux =
SOC_DAPM_ENUM("ADC Route", adc1l_enum);
/* ADC1RMUX */
static SOC_ENUM_SINGLE_DECL(adc1r_enum,
DA732X_REG_INP_MUX, DA732X_ADC1R_MUX_SEL_SHIFT,
adcr_text);
static const struct snd_kcontrol_new adc1r_mux =
SOC_DAPM_ENUM("ADC Route", adc1r_enum);
/* ADC2LMUX */
static SOC_ENUM_SINGLE_DECL(adc2l_enum,
DA732X_REG_INP_MUX, DA732X_ADC2L_MUX_SEL_SHIFT,
adcl_text);
static const struct snd_kcontrol_new adc2l_mux =
SOC_DAPM_ENUM("ADC Route", adc2l_enum);
/* ADC2RMUX */
static SOC_ENUM_SINGLE_DECL(adc2r_enum,
DA732X_REG_INP_MUX, DA732X_ADC2R_MUX_SEL_SHIFT,
adcr_text);
static const struct snd_kcontrol_new adc2r_mux =
SOC_DAPM_ENUM("ADC Route", adc2r_enum);
static SOC_ENUM_SINGLE_DECL(da732x_hp_left_output,
DA732X_REG_HPL, DA732X_HP_OUT_DAC_EN_SHIFT,
enable_text);
static const struct snd_kcontrol_new hpl_mux =
SOC_DAPM_ENUM("HPL Switch", da732x_hp_left_output);
static SOC_ENUM_SINGLE_DECL(da732x_hp_right_output,
DA732X_REG_HPR, DA732X_HP_OUT_DAC_EN_SHIFT,
enable_text);
static const struct snd_kcontrol_new hpr_mux =
SOC_DAPM_ENUM("HPR Switch", da732x_hp_right_output);
static SOC_ENUM_SINGLE_DECL(da732x_speaker_output,
DA732X_REG_LIN3, DA732X_LOUT_DAC_EN_SHIFT,
enable_text);
static const struct snd_kcontrol_new spk_mux =
SOC_DAPM_ENUM("SPK Switch", da732x_speaker_output);
static SOC_ENUM_SINGLE_DECL(da732x_lout4_output,
DA732X_REG_LIN4, DA732X_LOUT_DAC_EN_SHIFT,
enable_text);
static const struct snd_kcontrol_new lout4_mux =
SOC_DAPM_ENUM("LOUT4 Switch", da732x_lout4_output);
static SOC_ENUM_SINGLE_DECL(da732x_lout2_output,
DA732X_REG_LIN2, DA732X_LOUT_DAC_EN_SHIFT,
enable_text);
static const struct snd_kcontrol_new lout2_mux =
SOC_DAPM_ENUM("LOUT2 Switch", da732x_lout2_output);
static const struct snd_soc_dapm_widget da732x_dapm_widgets[] = {
/* Supplies */
SND_SOC_DAPM_SUPPLY("ADC1 Supply", DA732X_REG_ADC1_PD, 0,
DA732X_NO_INVERT, da732x_adc_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("ADC2 Supply", DA732X_REG_ADC2_PD, 0,
DA732X_NO_INVERT, da732x_adc_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("DAC1 CLK", DA732X_REG_CLK_EN4,
DA732X_DACA_BB_CLK_SHIFT, DA732X_NO_INVERT,
NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC2 CLK", DA732X_REG_CLK_EN4,
DA732X_DACC_BB_CLK_SHIFT, DA732X_NO_INVERT,
NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC3 CLK", DA732X_REG_CLK_EN5,
DA732X_DACE_BB_CLK_SHIFT, DA732X_NO_INVERT,
NULL, 0),
/* Micbias */
SND_SOC_DAPM_SUPPLY("MICBIAS1", DA732X_REG_MICBIAS1,
DA732X_MICBIAS_EN_SHIFT,
DA732X_NO_INVERT, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS2", DA732X_REG_MICBIAS2,
DA732X_MICBIAS_EN_SHIFT,
DA732X_NO_INVERT, NULL, 0),
/* Inputs */
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_INPUT("MIC2"),
SND_SOC_DAPM_INPUT("MIC3"),
SND_SOC_DAPM_INPUT("AUX1L"),
SND_SOC_DAPM_INPUT("AUX1R"),
/* Outputs */
SND_SOC_DAPM_OUTPUT("HPL"),
SND_SOC_DAPM_OUTPUT("HPR"),
SND_SOC_DAPM_OUTPUT("LOUTL"),
SND_SOC_DAPM_OUTPUT("LOUTR"),
SND_SOC_DAPM_OUTPUT("ClassD"),
/* ADCs */
SND_SOC_DAPM_ADC("ADC1L", NULL, DA732X_REG_ADC1_SEL,
DA732X_ADCL_EN_SHIFT, DA732X_NO_INVERT),
SND_SOC_DAPM_ADC("ADC1R", NULL, DA732X_REG_ADC1_SEL,
DA732X_ADCR_EN_SHIFT, DA732X_NO_INVERT),
SND_SOC_DAPM_ADC("ADC2L", NULL, DA732X_REG_ADC2_SEL,
DA732X_ADCL_EN_SHIFT, DA732X_NO_INVERT),
SND_SOC_DAPM_ADC("ADC2R", NULL, DA732X_REG_ADC2_SEL,
DA732X_ADCR_EN_SHIFT, DA732X_NO_INVERT),
/* DACs */
SND_SOC_DAPM_DAC("DAC1L", NULL, DA732X_REG_DAC1_SEL,
DA732X_DACL_EN_SHIFT, DA732X_NO_INVERT),
SND_SOC_DAPM_DAC("DAC1R", NULL, DA732X_REG_DAC1_SEL,
DA732X_DACR_EN_SHIFT, DA732X_NO_INVERT),
SND_SOC_DAPM_DAC("DAC2L", NULL, DA732X_REG_DAC2_SEL,
DA732X_DACL_EN_SHIFT, DA732X_NO_INVERT),
SND_SOC_DAPM_DAC("DAC2R", NULL, DA732X_REG_DAC2_SEL,
DA732X_DACR_EN_SHIFT, DA732X_NO_INVERT),
SND_SOC_DAPM_DAC("DAC3", NULL, DA732X_REG_DAC3_SEL,
DA732X_DACL_EN_SHIFT, DA732X_NO_INVERT),
/* Input Pgas */
SND_SOC_DAPM_PGA("MIC1 PGA", DA732X_REG_MIC1, DA732X_MIC_EN_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA("MIC2 PGA", DA732X_REG_MIC2, DA732X_MIC_EN_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA("MIC3 PGA", DA732X_REG_MIC3, DA732X_MIC_EN_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA("AUX1L PGA", DA732X_REG_AUX1L, DA732X_AUX_EN_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA("AUX1R PGA", DA732X_REG_AUX1R, DA732X_AUX_EN_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA_E("HP Left", DA732X_REG_HPL, DA732X_HP_OUT_EN_SHIFT,
0, NULL, 0, da732x_out_pga_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("HP Right", DA732X_REG_HPR, DA732X_HP_OUT_EN_SHIFT,
0, NULL, 0, da732x_out_pga_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("LIN2", DA732X_REG_LIN2, DA732X_LIN_OUT_EN_SHIFT,
0, NULL, 0, da732x_out_pga_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("LIN3", DA732X_REG_LIN3, DA732X_LIN_OUT_EN_SHIFT,
0, NULL, 0, da732x_out_pga_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("LIN4", DA732X_REG_LIN4, DA732X_LIN_OUT_EN_SHIFT,
0, NULL, 0, da732x_out_pga_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
/* MUXs */
SND_SOC_DAPM_MUX("ADC1 Left MUX", SND_SOC_NOPM, 0, 0, &adc1l_mux),
SND_SOC_DAPM_MUX("ADC1 Right MUX", SND_SOC_NOPM, 0, 0, &adc1r_mux),
SND_SOC_DAPM_MUX("ADC2 Left MUX", SND_SOC_NOPM, 0, 0, &adc2l_mux),
SND_SOC_DAPM_MUX("ADC2 Right MUX", SND_SOC_NOPM, 0, 0, &adc2r_mux),
SND_SOC_DAPM_MUX("HP Left MUX", SND_SOC_NOPM, 0, 0, &hpl_mux),
SND_SOC_DAPM_MUX("HP Right MUX", SND_SOC_NOPM, 0, 0, &hpr_mux),
SND_SOC_DAPM_MUX("Speaker MUX", SND_SOC_NOPM, 0, 0, &spk_mux),
SND_SOC_DAPM_MUX("LOUT2 MUX", SND_SOC_NOPM, 0, 0, &lout2_mux),
SND_SOC_DAPM_MUX("LOUT4 MUX", SND_SOC_NOPM, 0, 0, &lout4_mux),
/* AIF interfaces */
SND_SOC_DAPM_AIF_OUT("AIFA Output", "AIFA Capture", 0, DA732X_REG_AIFA3,
DA732X_AIF_EN_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIFA Input", "AIFA Playback", 0, DA732X_REG_AIFA3,
DA732X_AIF_EN_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIFB Output", "AIFB Capture", 0, DA732X_REG_AIFB3,
DA732X_AIF_EN_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIFB Input", "AIFB Playback", 0, DA732X_REG_AIFB3,
DA732X_AIF_EN_SHIFT, 0),
};
static const struct snd_soc_dapm_route da732x_dapm_routes[] = {
/* Inputs */
{"AUX1L PGA", NULL, "AUX1L"},
{"AUX1R PGA", NULL, "AUX1R"},
{"MIC1 PGA", NULL, "MIC1"},
{"MIC2 PGA", NULL, "MIC2"},
{"MIC3 PGA", NULL, "MIC3"},
/* Capture Path */
{"ADC1 Left MUX", "MIC1", "MIC1 PGA"},
{"ADC1 Left MUX", "AUX1L", "AUX1L PGA"},
{"ADC1 Right MUX", "AUX1R", "AUX1R PGA"},
{"ADC1 Right MUX", "MIC2", "MIC2 PGA"},
{"ADC1 Right MUX", "MIC3", "MIC3 PGA"},
{"ADC2 Left MUX", "AUX1L", "AUX1L PGA"},
{"ADC2 Left MUX", "MIC1", "MIC1 PGA"},
{"ADC2 Right MUX", "AUX1R", "AUX1R PGA"},
{"ADC2 Right MUX", "MIC2", "MIC2 PGA"},
{"ADC2 Right MUX", "MIC3", "MIC3 PGA"},
{"ADC1L", NULL, "ADC1 Supply"},
{"ADC1R", NULL, "ADC1 Supply"},
{"ADC2L", NULL, "ADC2 Supply"},
{"ADC2R", NULL, "ADC2 Supply"},
{"ADC1L", NULL, "ADC1 Left MUX"},
{"ADC1R", NULL, "ADC1 Right MUX"},
{"ADC2L", NULL, "ADC2 Left MUX"},
{"ADC2R", NULL, "ADC2 Right MUX"},
{"AIFA Output", NULL, "ADC1L"},
{"AIFA Output", NULL, "ADC1R"},
{"AIFB Output", NULL, "ADC2L"},
{"AIFB Output", NULL, "ADC2R"},
{"HP Left MUX", "Enabled", "AIFA Input"},
{"HP Right MUX", "Enabled", "AIFA Input"},
{"Speaker MUX", "Enabled", "AIFB Input"},
{"LOUT2 MUX", "Enabled", "AIFB Input"},
{"LOUT4 MUX", "Enabled", "AIFB Input"},
{"DAC1L", NULL, "DAC1 CLK"},
{"DAC1R", NULL, "DAC1 CLK"},
{"DAC2L", NULL, "DAC2 CLK"},
{"DAC2R", NULL, "DAC2 CLK"},
{"DAC3", NULL, "DAC3 CLK"},
{"DAC1L", NULL, "HP Left MUX"},
{"DAC1R", NULL, "HP Right MUX"},
{"DAC2L", NULL, "Speaker MUX"},
{"DAC2R", NULL, "LOUT4 MUX"},
{"DAC3", NULL, "LOUT2 MUX"},
/* Output Pgas */
{"HP Left", NULL, "DAC1L"},
{"HP Right", NULL, "DAC1R"},
{"LIN3", NULL, "DAC2L"},
{"LIN4", NULL, "DAC2R"},
{"LIN2", NULL, "DAC3"},
/* Outputs */
{"ClassD", NULL, "LIN3"},
{"LOUTL", NULL, "LIN2"},
{"LOUTR", NULL, "LIN4"},
{"HPL", NULL, "HP Left"},
{"HPR", NULL, "HP Right"},
};
static int da732x_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
u32 aif = 0;
u32 reg_aif;
u32 fs;
reg_aif = dai->driver->base;
switch (params_width(params)) {
case 16:
aif |= DA732X_AIF_WORD_16;
break;
case 20:
aif |= DA732X_AIF_WORD_20;
break;
case 24:
aif |= DA732X_AIF_WORD_24;
break;
case 32:
aif |= DA732X_AIF_WORD_32;
break;
default:
return -EINVAL;
}
switch (params_rate(params)) {
case 8000:
fs = DA732X_SR_8KHZ;
break;
case 11025:
fs = DA732X_SR_11_025KHZ;
break;
case 12000:
fs = DA732X_SR_12KHZ;
break;
case 16000:
fs = DA732X_SR_16KHZ;
break;
case 22050:
fs = DA732X_SR_22_05KHZ;
break;
case 24000:
fs = DA732X_SR_24KHZ;
break;
case 32000:
fs = DA732X_SR_32KHZ;
break;
case 44100:
fs = DA732X_SR_44_1KHZ;
break;
case 48000:
fs = DA732X_SR_48KHZ;
break;
case 88100:
fs = DA732X_SR_88_1KHZ;
break;
case 96000:
fs = DA732X_SR_96KHZ;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, reg_aif, DA732X_AIF_WORD_MASK, aif);
snd_soc_component_update_bits(component, DA732X_REG_CLK_CTRL, DA732X_SR1_MASK, fs);
return 0;
}
static int da732x_set_dai_fmt(struct snd_soc_dai *dai, u32 fmt)
{
struct snd_soc_component *component = dai->component;
u32 aif_mclk, pc_count;
u32 reg_aif1, aif1;
u32 reg_aif3, aif3;
switch (dai->id) {
case DA732X_DAI_ID1:
reg_aif1 = DA732X_REG_AIFA1;
reg_aif3 = DA732X_REG_AIFA3;
pc_count = DA732X_PC_PULSE_AIFA | DA732X_PC_RESYNC_NOT_AUT |
DA732X_PC_SAME;
break;
case DA732X_DAI_ID2:
reg_aif1 = DA732X_REG_AIFB1;
reg_aif3 = DA732X_REG_AIFB3;
pc_count = DA732X_PC_PULSE_AIFB | DA732X_PC_RESYNC_NOT_AUT |
DA732X_PC_SAME;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
aif1 = DA732X_AIF_SLAVE;
aif_mclk = DA732X_AIFM_FRAME_64 | DA732X_AIFM_SRC_SEL_AIFA;
break;
case SND_SOC_DAIFMT_CBM_CFM:
aif1 = DA732X_AIF_CLK_FROM_SRC;
aif_mclk = DA732X_CLK_GENERATION_AIF_A;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
aif3 = DA732X_AIF_I2S_MODE;
break;
case SND_SOC_DAIFMT_RIGHT_J:
aif3 = DA732X_AIF_RIGHT_J_MODE;
break;
case SND_SOC_DAIFMT_LEFT_J:
aif3 = DA732X_AIF_LEFT_J_MODE;
break;
case SND_SOC_DAIFMT_DSP_B:
aif3 = DA732X_AIF_DSP_MODE;
break;
default:
return -EINVAL;
}
/* Clock inversion */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_B:
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
aif3 |= DA732X_AIF_BCLK_INV;
break;
default:
return -EINVAL;
}
break;
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_RIGHT_J:
case SND_SOC_DAIFMT_LEFT_J:
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
aif3 |= DA732X_AIF_BCLK_INV | DA732X_AIF_WCLK_INV;
break;
case SND_SOC_DAIFMT_IB_NF:
aif3 |= DA732X_AIF_BCLK_INV;
break;
case SND_SOC_DAIFMT_NB_IF:
aif3 |= DA732X_AIF_WCLK_INV;
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, DA732X_REG_AIF_MCLK, aif_mclk);
snd_soc_component_update_bits(component, reg_aif1, DA732X_AIF1_CLK_MASK, aif1);
snd_soc_component_update_bits(component, reg_aif3, DA732X_AIF_BCLK_INV |
DA732X_AIF_WCLK_INV | DA732X_AIF_MODE_MASK, aif3);
snd_soc_component_write(component, DA732X_REG_PC_CTRL, pc_count);
return 0;
}
static int da732x_set_dai_pll(struct snd_soc_component *component, int pll_id,
int source, unsigned int freq_in,
unsigned int freq_out)
{
struct da732x_priv *da732x = snd_soc_component_get_drvdata(component);
int fref, indiv;
u8 div_lo, div_mid, div_hi;
u64 frac_div;
/* Disable PLL */
if (freq_out == 0) {
snd_soc_component_update_bits(component, DA732X_REG_PLL_CTRL,
DA732X_PLL_EN, 0);
da732x->pll_en = false;
return 0;
}
if (da732x->pll_en)
return -EBUSY;
if (source == DA732X_SRCCLK_MCLK) {
/* Validate Sysclk rate */
switch (da732x->sysclk) {
case 11290000:
case 12288000:
case 22580000:
case 24576000:
case 45160000:
case 49152000:
snd_soc_component_write(component, DA732X_REG_PLL_CTRL,
DA732X_PLL_BYPASS);
return 0;
default:
dev_err(component->dev,
"Cannot use PLL Bypass, invalid SYSCLK rate\n");
return -EINVAL;
}
}
indiv = da732x_get_input_div(component, da732x->sysclk);
if (indiv < 0)
return indiv;
fref = da732x->sysclk / BIT(indiv);
div_hi = freq_out / fref;
frac_div = (u64)(freq_out % fref) * 8192ULL;
do_div(frac_div, fref);
div_mid = (frac_div >> DA732X_1BYTE_SHIFT) & DA732X_U8_MASK;
div_lo = (frac_div) & DA732X_U8_MASK;
snd_soc_component_write(component, DA732X_REG_PLL_DIV_LO, div_lo);
snd_soc_component_write(component, DA732X_REG_PLL_DIV_MID, div_mid);
snd_soc_component_write(component, DA732X_REG_PLL_DIV_HI, div_hi);
snd_soc_component_update_bits(component, DA732X_REG_PLL_CTRL, DA732X_PLL_EN,
DA732X_PLL_EN);
da732x->pll_en = true;
return 0;
}
static int da732x_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct da732x_priv *da732x = snd_soc_component_get_drvdata(component);
da732x->sysclk = freq;
return 0;
}
#define DA732X_RATES SNDRV_PCM_RATE_8000_96000
#define DA732X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops da732x_dai_ops = {
.hw_params = da732x_hw_params,
.set_fmt = da732x_set_dai_fmt,
.set_sysclk = da732x_set_dai_sysclk,
};
static struct snd_soc_dai_driver da732x_dai[] = {
{
.name = "DA732X_AIFA",
.id = DA732X_DAI_ID1,
.base = DA732X_REG_AIFA1,
.playback = {
.stream_name = "AIFA Playback",
.channels_min = 1,
.channels_max = 2,
.rates = DA732X_RATES,
.formats = DA732X_FORMATS,
},
.capture = {
.stream_name = "AIFA Capture",
.channels_min = 1,
.channels_max = 2,
.rates = DA732X_RATES,
.formats = DA732X_FORMATS,
},
.ops = &da732x_dai_ops,
},
{
.name = "DA732X_AIFB",
.id = DA732X_DAI_ID2,
.base = DA732X_REG_AIFB1,
.playback = {
.stream_name = "AIFB Playback",
.channels_min = 1,
.channels_max = 2,
.rates = DA732X_RATES,
.formats = DA732X_FORMATS,
},
.capture = {
.stream_name = "AIFB Capture",
.channels_min = 1,
.channels_max = 2,
.rates = DA732X_RATES,
.formats = DA732X_FORMATS,
},
.ops = &da732x_dai_ops,
},
};
static bool da732x_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case DA732X_REG_HPL_DAC_OFF_CNTL:
case DA732X_REG_HPR_DAC_OFF_CNTL:
return true;
default:
return false;
}
}
static const struct regmap_config da732x_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = DA732X_MAX_REG,
.volatile_reg = da732x_volatile,
.reg_defaults = da732x_reg_cache,
.num_reg_defaults = ARRAY_SIZE(da732x_reg_cache),
.cache_type = REGCACHE_RBTREE,
};
static void da732x_dac_offset_adjust(struct snd_soc_component *component)
{
u8 offset[DA732X_HP_DACS];
u8 sign[DA732X_HP_DACS];
u8 step = DA732X_DAC_OFFSET_STEP;
/* Initialize DAC offset calibration circuits and registers */
snd_soc_component_write(component, DA732X_REG_HPL_DAC_OFFSET,
DA732X_HP_DAC_OFFSET_TRIM_VAL);
snd_soc_component_write(component, DA732X_REG_HPR_DAC_OFFSET,
DA732X_HP_DAC_OFFSET_TRIM_VAL);
snd_soc_component_write(component, DA732X_REG_HPL_DAC_OFF_CNTL,
DA732X_HP_DAC_OFF_CALIBRATION |
DA732X_HP_DAC_OFF_SCALE_STEPS);
snd_soc_component_write(component, DA732X_REG_HPR_DAC_OFF_CNTL,
DA732X_HP_DAC_OFF_CALIBRATION |
DA732X_HP_DAC_OFF_SCALE_STEPS);
/* Wait for voltage stabilization */
msleep(DA732X_WAIT_FOR_STABILIZATION);
/* Check DAC offset sign */
sign[DA732X_HPL_DAC] = (snd_soc_component_read(component, DA732X_REG_HPL_DAC_OFF_CNTL) &
DA732X_HP_DAC_OFF_CNTL_COMPO);
sign[DA732X_HPR_DAC] = (snd_soc_component_read(component, DA732X_REG_HPR_DAC_OFF_CNTL) &
DA732X_HP_DAC_OFF_CNTL_COMPO);
/* Binary search DAC offset values (both channels at once) */
offset[DA732X_HPL_DAC] = sign[DA732X_HPL_DAC] << DA732X_HP_DAC_COMPO_SHIFT;
offset[DA732X_HPR_DAC] = sign[DA732X_HPR_DAC] << DA732X_HP_DAC_COMPO_SHIFT;
do {
offset[DA732X_HPL_DAC] |= step;
offset[DA732X_HPR_DAC] |= step;
snd_soc_component_write(component, DA732X_REG_HPL_DAC_OFFSET,
~offset[DA732X_HPL_DAC] & DA732X_HP_DAC_OFF_MASK);
snd_soc_component_write(component, DA732X_REG_HPR_DAC_OFFSET,
~offset[DA732X_HPR_DAC] & DA732X_HP_DAC_OFF_MASK);
msleep(DA732X_WAIT_FOR_STABILIZATION);
if ((snd_soc_component_read(component, DA732X_REG_HPL_DAC_OFF_CNTL) &
DA732X_HP_DAC_OFF_CNTL_COMPO) ^ sign[DA732X_HPL_DAC])
offset[DA732X_HPL_DAC] &= ~step;
if ((snd_soc_component_read(component, DA732X_REG_HPR_DAC_OFF_CNTL) &
DA732X_HP_DAC_OFF_CNTL_COMPO) ^ sign[DA732X_HPR_DAC])
offset[DA732X_HPR_DAC] &= ~step;
step >>= 1;
} while (step);
/* Write final DAC offsets to registers */
snd_soc_component_write(component, DA732X_REG_HPL_DAC_OFFSET,
~offset[DA732X_HPL_DAC] & DA732X_HP_DAC_OFF_MASK);
snd_soc_component_write(component, DA732X_REG_HPR_DAC_OFFSET,
~offset[DA732X_HPR_DAC] & DA732X_HP_DAC_OFF_MASK);
/* End DAC calibration mode */
snd_soc_component_write(component, DA732X_REG_HPL_DAC_OFF_CNTL,
DA732X_HP_DAC_OFF_SCALE_STEPS);
snd_soc_component_write(component, DA732X_REG_HPR_DAC_OFF_CNTL,
DA732X_HP_DAC_OFF_SCALE_STEPS);
}
static void da732x_output_offset_adjust(struct snd_soc_component *component)
{
u8 offset[DA732X_HP_AMPS];
u8 sign[DA732X_HP_AMPS];
u8 step = DA732X_OUTPUT_OFFSET_STEP;
offset[DA732X_HPL_AMP] = DA732X_HP_OUT_TRIM_VAL;
offset[DA732X_HPR_AMP] = DA732X_HP_OUT_TRIM_VAL;
/* Initialize output offset calibration circuits and registers */
snd_soc_component_write(component, DA732X_REG_HPL_OUT_OFFSET, DA732X_HP_OUT_TRIM_VAL);
snd_soc_component_write(component, DA732X_REG_HPR_OUT_OFFSET, DA732X_HP_OUT_TRIM_VAL);
snd_soc_component_write(component, DA732X_REG_HPL,
DA732X_HP_OUT_COMP | DA732X_HP_OUT_EN);
snd_soc_component_write(component, DA732X_REG_HPR,
DA732X_HP_OUT_COMP | DA732X_HP_OUT_EN);
/* Wait for voltage stabilization */
msleep(DA732X_WAIT_FOR_STABILIZATION);
/* Check output offset sign */
sign[DA732X_HPL_AMP] = snd_soc_component_read(component, DA732X_REG_HPL) &
DA732X_HP_OUT_COMPO;
sign[DA732X_HPR_AMP] = snd_soc_component_read(component, DA732X_REG_HPR) &
DA732X_HP_OUT_COMPO;
snd_soc_component_write(component, DA732X_REG_HPL, DA732X_HP_OUT_COMP |
(sign[DA732X_HPL_AMP] >> DA732X_HP_OUT_COMPO_SHIFT) |
DA732X_HP_OUT_EN);
snd_soc_component_write(component, DA732X_REG_HPR, DA732X_HP_OUT_COMP |
(sign[DA732X_HPR_AMP] >> DA732X_HP_OUT_COMPO_SHIFT) |
DA732X_HP_OUT_EN);
/* Binary search output offset values (both channels at once) */
do {
offset[DA732X_HPL_AMP] |= step;
offset[DA732X_HPR_AMP] |= step;
snd_soc_component_write(component, DA732X_REG_HPL_OUT_OFFSET,
offset[DA732X_HPL_AMP]);
snd_soc_component_write(component, DA732X_REG_HPR_OUT_OFFSET,
offset[DA732X_HPR_AMP]);
msleep(DA732X_WAIT_FOR_STABILIZATION);
if ((snd_soc_component_read(component, DA732X_REG_HPL) &
DA732X_HP_OUT_COMPO) ^ sign[DA732X_HPL_AMP])
offset[DA732X_HPL_AMP] &= ~step;
if ((snd_soc_component_read(component, DA732X_REG_HPR) &
DA732X_HP_OUT_COMPO) ^ sign[DA732X_HPR_AMP])
offset[DA732X_HPR_AMP] &= ~step;
step >>= 1;
} while (step);
/* Write final DAC offsets to registers */
snd_soc_component_write(component, DA732X_REG_HPL_OUT_OFFSET, offset[DA732X_HPL_AMP]);
snd_soc_component_write(component, DA732X_REG_HPR_OUT_OFFSET, offset[DA732X_HPR_AMP]);
}
static void da732x_hp_dc_offset_cancellation(struct snd_soc_component *component)
{
/* Make sure that we have Soft Mute enabled */
snd_soc_component_write(component, DA732X_REG_DAC1_SOFTMUTE, DA732X_SOFTMUTE_EN |
DA732X_GAIN_RAMPED | DA732X_16_SAMPLES);
snd_soc_component_write(component, DA732X_REG_DAC1_SEL, DA732X_DACL_EN |
DA732X_DACR_EN | DA732X_DACL_SDM | DA732X_DACR_SDM |
DA732X_DACL_MUTE | DA732X_DACR_MUTE);
snd_soc_component_write(component, DA732X_REG_HPL, DA732X_HP_OUT_DAC_EN |
DA732X_HP_OUT_MUTE | DA732X_HP_OUT_EN);
snd_soc_component_write(component, DA732X_REG_HPR, DA732X_HP_OUT_EN |
DA732X_HP_OUT_MUTE | DA732X_HP_OUT_DAC_EN);
da732x_dac_offset_adjust(component);
da732x_output_offset_adjust(component);
snd_soc_component_write(component, DA732X_REG_DAC1_SEL, DA732X_DACS_DIS);
snd_soc_component_write(component, DA732X_REG_HPL, DA732X_HP_DIS);
snd_soc_component_write(component, DA732X_REG_HPR, DA732X_HP_DIS);
}
static int da732x_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct da732x_priv *da732x = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_ON:
snd_soc_component_update_bits(component, DA732X_REG_BIAS_EN,
DA732X_BIAS_BOOST_MASK,
DA732X_BIAS_BOOST_100PC);
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
/* Init Codec */
snd_soc_component_write(component, DA732X_REG_REF1,
DA732X_VMID_FASTCHG);
snd_soc_component_write(component, DA732X_REG_BIAS_EN,
DA732X_BIAS_EN);
mdelay(DA732X_STARTUP_DELAY);
/* Disable Fast Charge and enable DAC ref voltage */
snd_soc_component_write(component, DA732X_REG_REF1,
DA732X_REFBUFX2_EN);
/* Enable bypass DSP routing */
snd_soc_component_write(component, DA732X_REG_DATA_ROUTE,
DA732X_BYPASS_DSP);
/* Enable Digital subsystem */
snd_soc_component_write(component, DA732X_REG_DSP_CTRL,
DA732X_DIGITAL_EN);
snd_soc_component_write(component, DA732X_REG_SPARE1_OUT,
DA732X_HP_DRIVER_EN |
DA732X_HP_GATE_LOW |
DA732X_HP_LOOP_GAIN_CTRL);
snd_soc_component_write(component, DA732X_REG_HP_LIN1_GNDSEL,
DA732X_HP_OUT_GNDSEL);
da732x_set_charge_pump(component, DA732X_ENABLE_CP);
snd_soc_component_write(component, DA732X_REG_CLK_EN1,
DA732X_SYS3_CLK_EN | DA732X_PC_CLK_EN);
/* Enable Zero Crossing */
snd_soc_component_write(component, DA732X_REG_INP_ZC_EN,
DA732X_MIC1_PRE_ZC_EN |
DA732X_MIC1_ZC_EN |
DA732X_MIC2_PRE_ZC_EN |
DA732X_MIC2_ZC_EN |
DA732X_AUXL_ZC_EN |
DA732X_AUXR_ZC_EN |
DA732X_MIC3_PRE_ZC_EN |
DA732X_MIC3_ZC_EN);
snd_soc_component_write(component, DA732X_REG_OUT_ZC_EN,
DA732X_HPL_ZC_EN | DA732X_HPR_ZC_EN |
DA732X_LIN2_ZC_EN | DA732X_LIN3_ZC_EN |
DA732X_LIN4_ZC_EN);
da732x_hp_dc_offset_cancellation(component);
regcache_cache_only(da732x->regmap, false);
regcache_sync(da732x->regmap);
} else {
snd_soc_component_update_bits(component, DA732X_REG_BIAS_EN,
DA732X_BIAS_BOOST_MASK,
DA732X_BIAS_BOOST_50PC);
snd_soc_component_update_bits(component, DA732X_REG_PLL_CTRL,
DA732X_PLL_EN, 0);
da732x->pll_en = false;
}
break;
case SND_SOC_BIAS_OFF:
regcache_cache_only(da732x->regmap, true);
da732x_set_charge_pump(component, DA732X_DISABLE_CP);
snd_soc_component_update_bits(component, DA732X_REG_BIAS_EN, DA732X_BIAS_EN,
DA732X_BIAS_DIS);
da732x->pll_en = false;
break;
}
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_da732x = {
.set_bias_level = da732x_set_bias_level,
.controls = da732x_snd_controls,
.num_controls = ARRAY_SIZE(da732x_snd_controls),
.dapm_widgets = da732x_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(da732x_dapm_widgets),
.dapm_routes = da732x_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(da732x_dapm_routes),
.set_pll = da732x_set_dai_pll,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int da732x_i2c_probe(struct i2c_client *i2c)
{
struct da732x_priv *da732x;
unsigned int reg;
int ret;
da732x = devm_kzalloc(&i2c->dev, sizeof(struct da732x_priv),
GFP_KERNEL);
if (!da732x)
return -ENOMEM;
i2c_set_clientdata(i2c, da732x);
da732x->regmap = devm_regmap_init_i2c(i2c, &da732x_regmap);
if (IS_ERR(da732x->regmap)) {
ret = PTR_ERR(da732x->regmap);
dev_err(&i2c->dev, "Failed to initialize regmap\n");
goto err;
}
ret = regmap_read(da732x->regmap, DA732X_REG_ID, ®);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
goto err;
}
dev_info(&i2c->dev, "Revision: %d.%d\n",
(reg & DA732X_ID_MAJOR_MASK) >> 4,
(reg & DA732X_ID_MINOR_MASK));
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_da732x,
da732x_dai, ARRAY_SIZE(da732x_dai));
if (ret != 0)
dev_err(&i2c->dev, "Failed to register component.\n");
err:
return ret;
}
static const struct i2c_device_id da732x_i2c_id[] = {
{ "da7320", 0},
{ }
};
MODULE_DEVICE_TABLE(i2c, da732x_i2c_id);
static struct i2c_driver da732x_i2c_driver = {
.driver = {
.name = "da7320",
},
.probe = da732x_i2c_probe,
.id_table = da732x_i2c_id,
};
module_i2c_driver(da732x_i2c_driver);
MODULE_DESCRIPTION("ASoC DA732X driver");
MODULE_AUTHOR("Michal Hajduk <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/da732x.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8958-dsp2.c -- WM8958 DSP2 support
*
* Copyright 2011 Wolfson Microelectronics plc
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <trace/events/asoc.h>
#include <linux/mfd/wm8994/core.h>
#include <linux/mfd/wm8994/registers.h>
#include <linux/mfd/wm8994/pdata.h>
#include <linux/mfd/wm8994/gpio.h>
#include <asm/unaligned.h>
#include "wm8994.h"
#define WM_FW_BLOCK_INFO 0xff
#define WM_FW_BLOCK_PM 0x00
#define WM_FW_BLOCK_X 0x01
#define WM_FW_BLOCK_Y 0x02
#define WM_FW_BLOCK_Z 0x03
#define WM_FW_BLOCK_I 0x06
#define WM_FW_BLOCK_A 0x08
#define WM_FW_BLOCK_C 0x0c
static int wm8958_dsp2_fw(struct snd_soc_component *component, const char *name,
const struct firmware *fw, bool check)
{
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
u64 data64;
u32 data32;
const u8 *data;
char *str;
size_t block_len, len;
int ret = 0;
/* Suppress unneeded downloads */
if (wm8994->cur_fw == fw)
return 0;
if (fw->size < 32) {
dev_err(component->dev, "%s: firmware too short (%zd bytes)\n",
name, fw->size);
goto err;
}
if (memcmp(fw->data, "WMFW", 4) != 0) {
data32 = get_unaligned_be32(fw->data);
dev_err(component->dev, "%s: firmware has bad file magic %08x\n",
name, data32);
goto err;
}
len = get_unaligned_be32(fw->data + 4);
data32 = get_unaligned_be32(fw->data + 8);
if ((data32 >> 24) & 0xff) {
dev_err(component->dev, "%s: unsupported firmware version %d\n",
name, (data32 >> 24) & 0xff);
goto err;
}
if ((data32 & 0xffff) != 8958) {
dev_err(component->dev, "%s: unsupported target device %d\n",
name, data32 & 0xffff);
goto err;
}
if (((data32 >> 16) & 0xff) != 0xc) {
dev_err(component->dev, "%s: unsupported target core %d\n",
name, (data32 >> 16) & 0xff);
goto err;
}
if (check) {
data64 = get_unaligned_be64(fw->data + 24);
dev_info(component->dev, "%s timestamp %llx\n", name, data64);
} else {
snd_soc_component_write(component, 0x102, 0x2);
snd_soc_component_write(component, 0x900, 0x2);
}
data = fw->data + len;
len = fw->size - len;
while (len) {
if (len < 12) {
dev_err(component->dev, "%s short data block of %zd\n",
name, len);
goto err;
}
block_len = get_unaligned_be32(data + 4);
if (block_len + 8 > len) {
dev_err(component->dev, "%zd byte block longer than file\n",
block_len);
goto err;
}
if (block_len == 0) {
dev_err(component->dev, "Zero length block\n");
goto err;
}
data32 = get_unaligned_be32(data);
switch ((data32 >> 24) & 0xff) {
case WM_FW_BLOCK_INFO:
/* Informational text */
if (!check)
break;
str = kzalloc(block_len + 1, GFP_KERNEL);
if (str) {
memcpy(str, data + 8, block_len);
dev_info(component->dev, "%s: %s\n", name, str);
kfree(str);
} else {
dev_err(component->dev, "Out of memory\n");
}
break;
case WM_FW_BLOCK_PM:
case WM_FW_BLOCK_X:
case WM_FW_BLOCK_Y:
case WM_FW_BLOCK_Z:
case WM_FW_BLOCK_I:
case WM_FW_BLOCK_A:
case WM_FW_BLOCK_C:
dev_dbg(component->dev, "%s: %zd bytes of %x@%x\n", name,
block_len, (data32 >> 24) & 0xff,
data32 & 0xffffff);
if (check)
break;
data32 &= 0xffffff;
wm8994_bulk_write(wm8994->wm8994,
data32 & 0xffffff,
block_len / 2,
(void *)(data + 8));
break;
default:
dev_warn(component->dev, "%s: unknown block type %d\n",
name, (data32 >> 24) & 0xff);
break;
}
/* Round up to the next 32 bit word */
block_len += block_len % 4;
data += block_len + 8;
len -= block_len + 8;
}
if (!check) {
dev_dbg(component->dev, "%s: download done\n", name);
wm8994->cur_fw = fw;
} else {
dev_info(component->dev, "%s: got firmware\n", name);
}
goto ok;
err:
ret = -EINVAL;
ok:
if (!check) {
snd_soc_component_write(component, 0x900, 0x0);
snd_soc_component_write(component, 0x102, 0x0);
}
return ret;
}
static void wm8958_dsp_start_mbc(struct snd_soc_component *component, int path)
{
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
struct wm8994 *control = wm8994->wm8994;
int i;
/* If the DSP is already running then noop */
if (snd_soc_component_read(component, WM8958_DSP2_PROGRAM) & WM8958_DSP2_ENA)
return;
/* If we have MBC firmware download it */
if (wm8994->mbc)
wm8958_dsp2_fw(component, "MBC", wm8994->mbc, false);
snd_soc_component_update_bits(component, WM8958_DSP2_PROGRAM,
WM8958_DSP2_ENA, WM8958_DSP2_ENA);
/* If we've got user supplied MBC settings use them */
if (control->pdata.num_mbc_cfgs) {
struct wm8958_mbc_cfg *cfg
= &control->pdata.mbc_cfgs[wm8994->mbc_cfg];
for (i = 0; i < ARRAY_SIZE(cfg->coeff_regs); i++)
snd_soc_component_write(component, i + WM8958_MBC_BAND_1_K_1,
cfg->coeff_regs[i]);
for (i = 0; i < ARRAY_SIZE(cfg->cutoff_regs); i++)
snd_soc_component_write(component,
i + WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1,
cfg->cutoff_regs[i]);
}
/* Run the DSP */
snd_soc_component_write(component, WM8958_DSP2_EXECCONTROL,
WM8958_DSP2_RUNR);
/* And we're off! */
snd_soc_component_update_bits(component, WM8958_DSP2_CONFIG,
WM8958_MBC_ENA |
WM8958_MBC_SEL_MASK,
path << WM8958_MBC_SEL_SHIFT |
WM8958_MBC_ENA);
}
static void wm8958_dsp_start_vss(struct snd_soc_component *component, int path)
{
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
struct wm8994 *control = wm8994->wm8994;
int i, ena;
if (wm8994->mbc_vss)
wm8958_dsp2_fw(component, "MBC+VSS", wm8994->mbc_vss, false);
snd_soc_component_update_bits(component, WM8958_DSP2_PROGRAM,
WM8958_DSP2_ENA, WM8958_DSP2_ENA);
/* If we've got user supplied settings use them */
if (control->pdata.num_mbc_cfgs) {
struct wm8958_mbc_cfg *cfg
= &control->pdata.mbc_cfgs[wm8994->mbc_cfg];
for (i = 0; i < ARRAY_SIZE(cfg->combined_regs); i++)
snd_soc_component_write(component, i + 0x2800,
cfg->combined_regs[i]);
}
if (control->pdata.num_vss_cfgs) {
struct wm8958_vss_cfg *cfg
= &control->pdata.vss_cfgs[wm8994->vss_cfg];
for (i = 0; i < ARRAY_SIZE(cfg->regs); i++)
snd_soc_component_write(component, i + 0x2600, cfg->regs[i]);
}
if (control->pdata.num_vss_hpf_cfgs) {
struct wm8958_vss_hpf_cfg *cfg
= &control->pdata.vss_hpf_cfgs[wm8994->vss_hpf_cfg];
for (i = 0; i < ARRAY_SIZE(cfg->regs); i++)
snd_soc_component_write(component, i + 0x2400, cfg->regs[i]);
}
/* Run the DSP */
snd_soc_component_write(component, WM8958_DSP2_EXECCONTROL,
WM8958_DSP2_RUNR);
/* Enable the algorithms we've selected */
ena = 0;
if (wm8994->mbc_ena[path])
ena |= 0x8;
if (wm8994->hpf2_ena[path])
ena |= 0x4;
if (wm8994->hpf1_ena[path])
ena |= 0x2;
if (wm8994->vss_ena[path])
ena |= 0x1;
snd_soc_component_write(component, 0x2201, ena);
/* Switch the DSP into the data path */
snd_soc_component_update_bits(component, WM8958_DSP2_CONFIG,
WM8958_MBC_SEL_MASK | WM8958_MBC_ENA,
path << WM8958_MBC_SEL_SHIFT | WM8958_MBC_ENA);
}
static void wm8958_dsp_start_enh_eq(struct snd_soc_component *component, int path)
{
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
struct wm8994 *control = wm8994->wm8994;
int i;
wm8958_dsp2_fw(component, "ENH_EQ", wm8994->enh_eq, false);
snd_soc_component_update_bits(component, WM8958_DSP2_PROGRAM,
WM8958_DSP2_ENA, WM8958_DSP2_ENA);
/* If we've got user supplied settings use them */
if (control->pdata.num_enh_eq_cfgs) {
struct wm8958_enh_eq_cfg *cfg
= &control->pdata.enh_eq_cfgs[wm8994->enh_eq_cfg];
for (i = 0; i < ARRAY_SIZE(cfg->regs); i++)
snd_soc_component_write(component, i + 0x2200,
cfg->regs[i]);
}
/* Run the DSP */
snd_soc_component_write(component, WM8958_DSP2_EXECCONTROL,
WM8958_DSP2_RUNR);
/* Switch the DSP into the data path */
snd_soc_component_update_bits(component, WM8958_DSP2_CONFIG,
WM8958_MBC_SEL_MASK | WM8958_MBC_ENA,
path << WM8958_MBC_SEL_SHIFT | WM8958_MBC_ENA);
}
static void wm8958_dsp_apply(struct snd_soc_component *component, int path, int start)
{
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
int pwr_reg = snd_soc_component_read(component, WM8994_POWER_MANAGEMENT_5);
int ena, reg, aif;
switch (path) {
case 0:
pwr_reg &= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA);
aif = 0;
break;
case 1:
pwr_reg &= (WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
aif = 0;
break;
case 2:
pwr_reg &= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA);
aif = 1;
break;
default:
WARN(1, "Invalid path %d\n", path);
return;
}
/* Do we have both an active AIF and an active algorithm? */
ena = wm8994->mbc_ena[path] || wm8994->vss_ena[path] ||
wm8994->hpf1_ena[path] || wm8994->hpf2_ena[path] ||
wm8994->enh_eq_ena[path];
if (!pwr_reg)
ena = 0;
reg = snd_soc_component_read(component, WM8958_DSP2_PROGRAM);
dev_dbg(component->dev, "DSP path %d %d startup: %d, power: %x, DSP: %x\n",
path, wm8994->dsp_active, start, pwr_reg, reg);
if (start && ena) {
/* If the DSP is already running then noop */
if (reg & WM8958_DSP2_ENA)
return;
/* If either AIFnCLK is not yet enabled postpone */
if (!(snd_soc_component_read(component, WM8994_AIF1_CLOCKING_1)
& WM8994_AIF1CLK_ENA_MASK) &&
!(snd_soc_component_read(component, WM8994_AIF2_CLOCKING_1)
& WM8994_AIF2CLK_ENA_MASK))
return;
/* Switch the clock over to the appropriate AIF */
snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
WM8958_DSP2CLK_SRC | WM8958_DSP2CLK_ENA,
aif << WM8958_DSP2CLK_SRC_SHIFT |
WM8958_DSP2CLK_ENA);
if (wm8994->enh_eq_ena[path])
wm8958_dsp_start_enh_eq(component, path);
else if (wm8994->vss_ena[path] || wm8994->hpf1_ena[path] ||
wm8994->hpf2_ena[path])
wm8958_dsp_start_vss(component, path);
else if (wm8994->mbc_ena[path])
wm8958_dsp_start_mbc(component, path);
wm8994->dsp_active = path;
dev_dbg(component->dev, "DSP running in path %d\n", path);
}
if (!start && wm8994->dsp_active == path) {
/* If the DSP is already stopped then noop */
if (!(reg & WM8958_DSP2_ENA))
return;
snd_soc_component_update_bits(component, WM8958_DSP2_CONFIG,
WM8958_MBC_ENA, 0);
snd_soc_component_write(component, WM8958_DSP2_EXECCONTROL,
WM8958_DSP2_STOP);
snd_soc_component_update_bits(component, WM8958_DSP2_PROGRAM,
WM8958_DSP2_ENA, 0);
snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
WM8958_DSP2CLK_ENA, 0);
wm8994->dsp_active = -1;
dev_dbg(component->dev, "DSP stopped\n");
}
}
int wm8958_aif_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wm8994 *control = dev_get_drvdata(component->dev->parent);
int i;
if (control->type != WM8958)
return 0;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
case SND_SOC_DAPM_PRE_PMU:
for (i = 0; i < 3; i++)
wm8958_dsp_apply(component, i, 1);
break;
case SND_SOC_DAPM_POST_PMD:
case SND_SOC_DAPM_PRE_PMD:
for (i = 0; i < 3; i++)
wm8958_dsp_apply(component, i, 0);
break;
}
return 0;
}
/* Check if DSP2 is in use on another AIF */
static int wm8958_dsp2_busy(struct wm8994_priv *wm8994, int aif)
{
int i;
for (i = 0; i < ARRAY_SIZE(wm8994->mbc_ena); i++) {
if (i == aif)
continue;
if (wm8994->mbc_ena[i] || wm8994->vss_ena[i] ||
wm8994->hpf1_ena[i] || wm8994->hpf2_ena[i])
return 1;
}
return 0;
}
static int wm8958_put_mbc_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
struct wm8994 *control = wm8994->wm8994;
int value = ucontrol->value.enumerated.item[0];
int reg;
/* Don't allow on the fly reconfiguration */
reg = snd_soc_component_read(component, WM8994_CLOCKING_1);
if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
return -EBUSY;
if (value >= control->pdata.num_mbc_cfgs)
return -EINVAL;
wm8994->mbc_cfg = value;
return 0;
}
static int wm8958_get_mbc_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
ucontrol->value.enumerated.item[0] = wm8994->mbc_cfg;
return 0;
}
static int wm8958_mbc_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
uinfo->count = 1;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = 1;
return 0;
}
static int wm8958_mbc_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
int mbc = kcontrol->private_value;
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = wm8994->mbc_ena[mbc];
return 0;
}
static int wm8958_mbc_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
int mbc = kcontrol->private_value;
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
if (wm8994->mbc_ena[mbc] == ucontrol->value.integer.value[0])
return 0;
if (ucontrol->value.integer.value[0] > 1)
return -EINVAL;
if (wm8958_dsp2_busy(wm8994, mbc)) {
dev_dbg(component->dev, "DSP2 active on %d already\n", mbc);
return -EBUSY;
}
if (wm8994->enh_eq_ena[mbc])
return -EBUSY;
wm8994->mbc_ena[mbc] = ucontrol->value.integer.value[0];
wm8958_dsp_apply(component, mbc, wm8994->mbc_ena[mbc]);
return 1;
}
#define WM8958_MBC_SWITCH(xname, xval) {\
.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
.access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
.info = wm8958_mbc_info, \
.get = wm8958_mbc_get, .put = wm8958_mbc_put, \
.private_value = xval }
static int wm8958_put_vss_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
struct wm8994 *control = wm8994->wm8994;
int value = ucontrol->value.enumerated.item[0];
int reg;
/* Don't allow on the fly reconfiguration */
reg = snd_soc_component_read(component, WM8994_CLOCKING_1);
if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
return -EBUSY;
if (value >= control->pdata.num_vss_cfgs)
return -EINVAL;
wm8994->vss_cfg = value;
return 0;
}
static int wm8958_get_vss_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
ucontrol->value.enumerated.item[0] = wm8994->vss_cfg;
return 0;
}
static int wm8958_put_vss_hpf_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
struct wm8994 *control = wm8994->wm8994;
int value = ucontrol->value.enumerated.item[0];
int reg;
/* Don't allow on the fly reconfiguration */
reg = snd_soc_component_read(component, WM8994_CLOCKING_1);
if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
return -EBUSY;
if (value >= control->pdata.num_vss_hpf_cfgs)
return -EINVAL;
wm8994->vss_hpf_cfg = value;
return 0;
}
static int wm8958_get_vss_hpf_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
ucontrol->value.enumerated.item[0] = wm8994->vss_hpf_cfg;
return 0;
}
static int wm8958_vss_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
uinfo->count = 1;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = 1;
return 0;
}
static int wm8958_vss_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
int vss = kcontrol->private_value;
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = wm8994->vss_ena[vss];
return 0;
}
static int wm8958_vss_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
int vss = kcontrol->private_value;
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
if (wm8994->vss_ena[vss] == ucontrol->value.integer.value[0])
return 0;
if (ucontrol->value.integer.value[0] > 1)
return -EINVAL;
if (!wm8994->mbc_vss)
return -ENODEV;
if (wm8958_dsp2_busy(wm8994, vss)) {
dev_dbg(component->dev, "DSP2 active on %d already\n", vss);
return -EBUSY;
}
if (wm8994->enh_eq_ena[vss])
return -EBUSY;
wm8994->vss_ena[vss] = ucontrol->value.integer.value[0];
wm8958_dsp_apply(component, vss, wm8994->vss_ena[vss]);
return 1;
}
#define WM8958_VSS_SWITCH(xname, xval) {\
.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
.access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
.info = wm8958_vss_info, \
.get = wm8958_vss_get, .put = wm8958_vss_put, \
.private_value = xval }
static int wm8958_hpf_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
uinfo->count = 1;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = 1;
return 0;
}
static int wm8958_hpf_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
int hpf = kcontrol->private_value;
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
if (hpf < 3)
ucontrol->value.integer.value[0] = wm8994->hpf1_ena[hpf % 3];
else
ucontrol->value.integer.value[0] = wm8994->hpf2_ena[hpf % 3];
return 0;
}
static int wm8958_hpf_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
int hpf = kcontrol->private_value;
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
if (hpf < 3) {
if (wm8994->hpf1_ena[hpf % 3] ==
ucontrol->value.integer.value[0])
return 0;
} else {
if (wm8994->hpf2_ena[hpf % 3] ==
ucontrol->value.integer.value[0])
return 0;
}
if (ucontrol->value.integer.value[0] > 1)
return -EINVAL;
if (!wm8994->mbc_vss)
return -ENODEV;
if (wm8958_dsp2_busy(wm8994, hpf % 3)) {
dev_dbg(component->dev, "DSP2 active on %d already\n", hpf);
return -EBUSY;
}
if (wm8994->enh_eq_ena[hpf % 3])
return -EBUSY;
if (hpf < 3)
wm8994->hpf1_ena[hpf % 3] = ucontrol->value.integer.value[0];
else
wm8994->hpf2_ena[hpf % 3] = ucontrol->value.integer.value[0];
wm8958_dsp_apply(component, hpf % 3, ucontrol->value.integer.value[0]);
return 1;
}
#define WM8958_HPF_SWITCH(xname, xval) {\
.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
.access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
.info = wm8958_hpf_info, \
.get = wm8958_hpf_get, .put = wm8958_hpf_put, \
.private_value = xval }
static int wm8958_put_enh_eq_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
struct wm8994 *control = wm8994->wm8994;
int value = ucontrol->value.enumerated.item[0];
int reg;
/* Don't allow on the fly reconfiguration */
reg = snd_soc_component_read(component, WM8994_CLOCKING_1);
if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
return -EBUSY;
if (value >= control->pdata.num_enh_eq_cfgs)
return -EINVAL;
wm8994->enh_eq_cfg = value;
return 0;
}
static int wm8958_get_enh_eq_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
ucontrol->value.enumerated.item[0] = wm8994->enh_eq_cfg;
return 0;
}
static int wm8958_enh_eq_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
uinfo->count = 1;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = 1;
return 0;
}
static int wm8958_enh_eq_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
int eq = kcontrol->private_value;
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = wm8994->enh_eq_ena[eq];
return 0;
}
static int wm8958_enh_eq_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
int eq = kcontrol->private_value;
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
if (wm8994->enh_eq_ena[eq] == ucontrol->value.integer.value[0])
return 0;
if (ucontrol->value.integer.value[0] > 1)
return -EINVAL;
if (!wm8994->enh_eq)
return -ENODEV;
if (wm8958_dsp2_busy(wm8994, eq)) {
dev_dbg(component->dev, "DSP2 active on %d already\n", eq);
return -EBUSY;
}
if (wm8994->mbc_ena[eq] || wm8994->vss_ena[eq] ||
wm8994->hpf1_ena[eq] || wm8994->hpf2_ena[eq])
return -EBUSY;
wm8994->enh_eq_ena[eq] = ucontrol->value.integer.value[0];
wm8958_dsp_apply(component, eq, ucontrol->value.integer.value[0]);
return 1;
}
#define WM8958_ENH_EQ_SWITCH(xname, xval) {\
.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
.access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
.info = wm8958_enh_eq_info, \
.get = wm8958_enh_eq_get, .put = wm8958_enh_eq_put, \
.private_value = xval }
static const struct snd_kcontrol_new wm8958_mbc_snd_controls[] = {
WM8958_MBC_SWITCH("AIF1DAC1 MBC Switch", 0),
WM8958_MBC_SWITCH("AIF1DAC2 MBC Switch", 1),
WM8958_MBC_SWITCH("AIF2DAC MBC Switch", 2),
};
static const struct snd_kcontrol_new wm8958_vss_snd_controls[] = {
WM8958_VSS_SWITCH("AIF1DAC1 VSS Switch", 0),
WM8958_VSS_SWITCH("AIF1DAC2 VSS Switch", 1),
WM8958_VSS_SWITCH("AIF2DAC VSS Switch", 2),
WM8958_HPF_SWITCH("AIF1DAC1 HPF1 Switch", 0),
WM8958_HPF_SWITCH("AIF1DAC2 HPF1 Switch", 1),
WM8958_HPF_SWITCH("AIF2DAC HPF1 Switch", 2),
WM8958_HPF_SWITCH("AIF1DAC1 HPF2 Switch", 3),
WM8958_HPF_SWITCH("AIF1DAC2 HPF2 Switch", 4),
WM8958_HPF_SWITCH("AIF2DAC HPF2 Switch", 5),
};
static const struct snd_kcontrol_new wm8958_enh_eq_snd_controls[] = {
WM8958_ENH_EQ_SWITCH("AIF1DAC1 Enhanced EQ Switch", 0),
WM8958_ENH_EQ_SWITCH("AIF1DAC2 Enhanced EQ Switch", 1),
WM8958_ENH_EQ_SWITCH("AIF2DAC Enhanced EQ Switch", 2),
};
static void wm8958_enh_eq_loaded(const struct firmware *fw, void *context)
{
struct snd_soc_component *component = context;
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
if (fw && (wm8958_dsp2_fw(component, "ENH_EQ", fw, true) == 0)) {
mutex_lock(&wm8994->fw_lock);
wm8994->enh_eq = fw;
mutex_unlock(&wm8994->fw_lock);
}
}
static void wm8958_mbc_vss_loaded(const struct firmware *fw, void *context)
{
struct snd_soc_component *component = context;
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
if (fw && (wm8958_dsp2_fw(component, "MBC+VSS", fw, true) == 0)) {
mutex_lock(&wm8994->fw_lock);
wm8994->mbc_vss = fw;
mutex_unlock(&wm8994->fw_lock);
}
}
static void wm8958_mbc_loaded(const struct firmware *fw, void *context)
{
struct snd_soc_component *component = context;
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
if (fw && (wm8958_dsp2_fw(component, "MBC", fw, true) == 0)) {
mutex_lock(&wm8994->fw_lock);
wm8994->mbc = fw;
mutex_unlock(&wm8994->fw_lock);
}
}
void wm8958_dsp2_init(struct snd_soc_component *component)
{
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
struct wm8994 *control = wm8994->wm8994;
struct wm8994_pdata *pdata = &control->pdata;
int ret, i;
wm8994->dsp_active = -1;
snd_soc_add_component_controls(component, wm8958_mbc_snd_controls,
ARRAY_SIZE(wm8958_mbc_snd_controls));
snd_soc_add_component_controls(component, wm8958_vss_snd_controls,
ARRAY_SIZE(wm8958_vss_snd_controls));
snd_soc_add_component_controls(component, wm8958_enh_eq_snd_controls,
ARRAY_SIZE(wm8958_enh_eq_snd_controls));
/* We don't *require* firmware and don't want to delay boot */
request_firmware_nowait(THIS_MODULE, FW_ACTION_UEVENT,
"wm8958_mbc.wfw", component->dev, GFP_KERNEL,
component, wm8958_mbc_loaded);
request_firmware_nowait(THIS_MODULE, FW_ACTION_UEVENT,
"wm8958_mbc_vss.wfw", component->dev, GFP_KERNEL,
component, wm8958_mbc_vss_loaded);
request_firmware_nowait(THIS_MODULE, FW_ACTION_UEVENT,
"wm8958_enh_eq.wfw", component->dev, GFP_KERNEL,
component, wm8958_enh_eq_loaded);
if (pdata->num_mbc_cfgs) {
struct snd_kcontrol_new mbc_control[] = {
SOC_ENUM_EXT("MBC Mode", wm8994->mbc_enum,
wm8958_get_mbc_enum, wm8958_put_mbc_enum),
};
/* We need an array of texts for the enum API */
wm8994->mbc_texts = kmalloc_array(pdata->num_mbc_cfgs,
sizeof(char *),
GFP_KERNEL);
if (!wm8994->mbc_texts)
return;
for (i = 0; i < pdata->num_mbc_cfgs; i++)
wm8994->mbc_texts[i] = pdata->mbc_cfgs[i].name;
wm8994->mbc_enum.items = pdata->num_mbc_cfgs;
wm8994->mbc_enum.texts = wm8994->mbc_texts;
ret = snd_soc_add_component_controls(wm8994->hubs.component,
mbc_control, 1);
if (ret != 0)
dev_err(wm8994->hubs.component->dev,
"Failed to add MBC mode controls: %d\n", ret);
}
if (pdata->num_vss_cfgs) {
struct snd_kcontrol_new vss_control[] = {
SOC_ENUM_EXT("VSS Mode", wm8994->vss_enum,
wm8958_get_vss_enum, wm8958_put_vss_enum),
};
/* We need an array of texts for the enum API */
wm8994->vss_texts = kmalloc_array(pdata->num_vss_cfgs,
sizeof(char *),
GFP_KERNEL);
if (!wm8994->vss_texts)
return;
for (i = 0; i < pdata->num_vss_cfgs; i++)
wm8994->vss_texts[i] = pdata->vss_cfgs[i].name;
wm8994->vss_enum.items = pdata->num_vss_cfgs;
wm8994->vss_enum.texts = wm8994->vss_texts;
ret = snd_soc_add_component_controls(wm8994->hubs.component,
vss_control, 1);
if (ret != 0)
dev_err(wm8994->hubs.component->dev,
"Failed to add VSS mode controls: %d\n", ret);
}
if (pdata->num_vss_hpf_cfgs) {
struct snd_kcontrol_new hpf_control[] = {
SOC_ENUM_EXT("VSS HPF Mode", wm8994->vss_hpf_enum,
wm8958_get_vss_hpf_enum,
wm8958_put_vss_hpf_enum),
};
/* We need an array of texts for the enum API */
wm8994->vss_hpf_texts = kmalloc_array(pdata->num_vss_hpf_cfgs,
sizeof(char *),
GFP_KERNEL);
if (!wm8994->vss_hpf_texts)
return;
for (i = 0; i < pdata->num_vss_hpf_cfgs; i++)
wm8994->vss_hpf_texts[i] = pdata->vss_hpf_cfgs[i].name;
wm8994->vss_hpf_enum.items = pdata->num_vss_hpf_cfgs;
wm8994->vss_hpf_enum.texts = wm8994->vss_hpf_texts;
ret = snd_soc_add_component_controls(wm8994->hubs.component,
hpf_control, 1);
if (ret != 0)
dev_err(wm8994->hubs.component->dev,
"Failed to add VSS HPFmode controls: %d\n",
ret);
}
if (pdata->num_enh_eq_cfgs) {
struct snd_kcontrol_new eq_control[] = {
SOC_ENUM_EXT("Enhanced EQ Mode", wm8994->enh_eq_enum,
wm8958_get_enh_eq_enum,
wm8958_put_enh_eq_enum),
};
/* We need an array of texts for the enum API */
wm8994->enh_eq_texts = kmalloc_array(pdata->num_enh_eq_cfgs,
sizeof(char *),
GFP_KERNEL);
if (!wm8994->enh_eq_texts)
return;
for (i = 0; i < pdata->num_enh_eq_cfgs; i++)
wm8994->enh_eq_texts[i] = pdata->enh_eq_cfgs[i].name;
wm8994->enh_eq_enum.items = pdata->num_enh_eq_cfgs;
wm8994->enh_eq_enum.texts = wm8994->enh_eq_texts;
ret = snd_soc_add_component_controls(wm8994->hubs.component,
eq_control, 1);
if (ret != 0)
dev_err(wm8994->hubs.component->dev,
"Failed to add enhanced EQ controls: %d\n",
ret);
}
}
| linux-master | sound/soc/codecs/wm8958-dsp2.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* rt5651.c -- RT5651 ALSA SoC audio codec driver
*
* Copyright 2014 Realtek Semiconductor Corp.
* Author: Bard Liao <[email protected]>
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/acpi.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/jack.h>
#include "rl6231.h"
#include "rt5651.h"
#define RT5651_DEVICE_ID_VALUE 0x6281
#define RT5651_PR_RANGE_BASE (0xff + 1)
#define RT5651_PR_SPACING 0x100
#define RT5651_PR_BASE (RT5651_PR_RANGE_BASE + (0 * RT5651_PR_SPACING))
static const struct regmap_range_cfg rt5651_ranges[] = {
{ .name = "PR", .range_min = RT5651_PR_BASE,
.range_max = RT5651_PR_BASE + 0xb4,
.selector_reg = RT5651_PRIV_INDEX,
.selector_mask = 0xff,
.selector_shift = 0x0,
.window_start = RT5651_PRIV_DATA,
.window_len = 0x1, },
};
static const struct reg_sequence init_list[] = {
{RT5651_PR_BASE + 0x3d, 0x3e00},
};
static const struct reg_default rt5651_reg[] = {
{ 0x00, 0x0000 },
{ 0x02, 0xc8c8 },
{ 0x03, 0xc8c8 },
{ 0x05, 0x0000 },
{ 0x0d, 0x0000 },
{ 0x0e, 0x0000 },
{ 0x0f, 0x0808 },
{ 0x10, 0x0808 },
{ 0x19, 0xafaf },
{ 0x1a, 0xafaf },
{ 0x1b, 0x0c00 },
{ 0x1c, 0x2f2f },
{ 0x1d, 0x2f2f },
{ 0x1e, 0x0000 },
{ 0x27, 0x7860 },
{ 0x28, 0x7070 },
{ 0x29, 0x8080 },
{ 0x2a, 0x5252 },
{ 0x2b, 0x5454 },
{ 0x2f, 0x0000 },
{ 0x30, 0x5000 },
{ 0x3b, 0x0000 },
{ 0x3c, 0x006f },
{ 0x3d, 0x0000 },
{ 0x3e, 0x006f },
{ 0x45, 0x6000 },
{ 0x4d, 0x0000 },
{ 0x4e, 0x0000 },
{ 0x4f, 0x0279 },
{ 0x50, 0x0000 },
{ 0x51, 0x0000 },
{ 0x52, 0x0279 },
{ 0x53, 0xf000 },
{ 0x61, 0x0000 },
{ 0x62, 0x0000 },
{ 0x63, 0x00c0 },
{ 0x64, 0x0000 },
{ 0x65, 0x0000 },
{ 0x66, 0x0000 },
{ 0x70, 0x8000 },
{ 0x71, 0x8000 },
{ 0x73, 0x1104 },
{ 0x74, 0x0c00 },
{ 0x75, 0x1400 },
{ 0x77, 0x0c00 },
{ 0x78, 0x4000 },
{ 0x79, 0x0123 },
{ 0x80, 0x0000 },
{ 0x81, 0x0000 },
{ 0x82, 0x0000 },
{ 0x83, 0x0800 },
{ 0x84, 0x0000 },
{ 0x85, 0x0008 },
{ 0x89, 0x0000 },
{ 0x8e, 0x0004 },
{ 0x8f, 0x1100 },
{ 0x90, 0x0000 },
{ 0x93, 0x2000 },
{ 0x94, 0x0200 },
{ 0xb0, 0x2080 },
{ 0xb1, 0x0000 },
{ 0xb4, 0x2206 },
{ 0xb5, 0x1f00 },
{ 0xb6, 0x0000 },
{ 0xbb, 0x0000 },
{ 0xbc, 0x0000 },
{ 0xbd, 0x0000 },
{ 0xbe, 0x0000 },
{ 0xbf, 0x0000 },
{ 0xc0, 0x0400 },
{ 0xc1, 0x0000 },
{ 0xc2, 0x0000 },
{ 0xcf, 0x0013 },
{ 0xd0, 0x0680 },
{ 0xd1, 0x1c17 },
{ 0xd3, 0xb320 },
{ 0xd9, 0x0809 },
{ 0xfa, 0x0010 },
{ 0xfe, 0x10ec },
{ 0xff, 0x6281 },
};
static bool rt5651_volatile_register(struct device *dev, unsigned int reg)
{
int i;
for (i = 0; i < ARRAY_SIZE(rt5651_ranges); i++) {
if ((reg >= rt5651_ranges[i].window_start &&
reg <= rt5651_ranges[i].window_start +
rt5651_ranges[i].window_len) ||
(reg >= rt5651_ranges[i].range_min &&
reg <= rt5651_ranges[i].range_max)) {
return true;
}
}
switch (reg) {
case RT5651_RESET:
case RT5651_PRIV_DATA:
case RT5651_EQ_CTRL1:
case RT5651_ALC_1:
case RT5651_IRQ_CTRL2:
case RT5651_INT_IRQ_ST:
case RT5651_PGM_REG_ARR1:
case RT5651_PGM_REG_ARR3:
case RT5651_VENDOR_ID:
case RT5651_DEVICE_ID:
return true;
default:
return false;
}
}
static bool rt5651_readable_register(struct device *dev, unsigned int reg)
{
int i;
for (i = 0; i < ARRAY_SIZE(rt5651_ranges); i++) {
if ((reg >= rt5651_ranges[i].window_start &&
reg <= rt5651_ranges[i].window_start +
rt5651_ranges[i].window_len) ||
(reg >= rt5651_ranges[i].range_min &&
reg <= rt5651_ranges[i].range_max)) {
return true;
}
}
switch (reg) {
case RT5651_RESET:
case RT5651_VERSION_ID:
case RT5651_VENDOR_ID:
case RT5651_DEVICE_ID:
case RT5651_HP_VOL:
case RT5651_LOUT_CTRL1:
case RT5651_LOUT_CTRL2:
case RT5651_IN1_IN2:
case RT5651_IN3:
case RT5651_INL1_INR1_VOL:
case RT5651_INL2_INR2_VOL:
case RT5651_DAC1_DIG_VOL:
case RT5651_DAC2_DIG_VOL:
case RT5651_DAC2_CTRL:
case RT5651_ADC_DIG_VOL:
case RT5651_ADC_DATA:
case RT5651_ADC_BST_VOL:
case RT5651_STO1_ADC_MIXER:
case RT5651_STO2_ADC_MIXER:
case RT5651_AD_DA_MIXER:
case RT5651_STO_DAC_MIXER:
case RT5651_DD_MIXER:
case RT5651_DIG_INF_DATA:
case RT5651_PDM_CTL:
case RT5651_REC_L1_MIXER:
case RT5651_REC_L2_MIXER:
case RT5651_REC_R1_MIXER:
case RT5651_REC_R2_MIXER:
case RT5651_HPO_MIXER:
case RT5651_OUT_L1_MIXER:
case RT5651_OUT_L2_MIXER:
case RT5651_OUT_L3_MIXER:
case RT5651_OUT_R1_MIXER:
case RT5651_OUT_R2_MIXER:
case RT5651_OUT_R3_MIXER:
case RT5651_LOUT_MIXER:
case RT5651_PWR_DIG1:
case RT5651_PWR_DIG2:
case RT5651_PWR_ANLG1:
case RT5651_PWR_ANLG2:
case RT5651_PWR_MIXER:
case RT5651_PWR_VOL:
case RT5651_PRIV_INDEX:
case RT5651_PRIV_DATA:
case RT5651_I2S1_SDP:
case RT5651_I2S2_SDP:
case RT5651_ADDA_CLK1:
case RT5651_ADDA_CLK2:
case RT5651_DMIC:
case RT5651_TDM_CTL_1:
case RT5651_TDM_CTL_2:
case RT5651_TDM_CTL_3:
case RT5651_GLB_CLK:
case RT5651_PLL_CTRL1:
case RT5651_PLL_CTRL2:
case RT5651_PLL_MODE_1:
case RT5651_PLL_MODE_2:
case RT5651_PLL_MODE_3:
case RT5651_PLL_MODE_4:
case RT5651_PLL_MODE_5:
case RT5651_PLL_MODE_6:
case RT5651_PLL_MODE_7:
case RT5651_DEPOP_M1:
case RT5651_DEPOP_M2:
case RT5651_DEPOP_M3:
case RT5651_CHARGE_PUMP:
case RT5651_MICBIAS:
case RT5651_A_JD_CTL1:
case RT5651_EQ_CTRL1:
case RT5651_EQ_CTRL2:
case RT5651_ALC_1:
case RT5651_ALC_2:
case RT5651_ALC_3:
case RT5651_JD_CTRL1:
case RT5651_JD_CTRL2:
case RT5651_IRQ_CTRL1:
case RT5651_IRQ_CTRL2:
case RT5651_INT_IRQ_ST:
case RT5651_GPIO_CTRL1:
case RT5651_GPIO_CTRL2:
case RT5651_GPIO_CTRL3:
case RT5651_PGM_REG_ARR1:
case RT5651_PGM_REG_ARR2:
case RT5651_PGM_REG_ARR3:
case RT5651_PGM_REG_ARR4:
case RT5651_PGM_REG_ARR5:
case RT5651_SCB_FUNC:
case RT5651_SCB_CTRL:
case RT5651_BASE_BACK:
case RT5651_MP3_PLUS1:
case RT5651_MP3_PLUS2:
case RT5651_ADJ_HPF_CTRL1:
case RT5651_ADJ_HPF_CTRL2:
case RT5651_HP_CALIB_AMP_DET:
case RT5651_HP_CALIB2:
case RT5651_SV_ZCD1:
case RT5651_SV_ZCD2:
case RT5651_D_MISC:
case RT5651_DUMMY2:
case RT5651_DUMMY3:
return true;
default:
return false;
}
}
static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
static const DECLARE_TLV_DB_MINMAX(dac_vol_tlv, -6562, 0);
static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
static const DECLARE_TLV_DB_MINMAX(adc_vol_tlv, -1762, 3000);
static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
static const DECLARE_TLV_DB_RANGE(bst_tlv,
0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
);
/* Interface data select */
static const char * const rt5651_data_select[] = {
"Normal", "Swap", "left copy to right", "right copy to left"};
static SOC_ENUM_SINGLE_DECL(rt5651_if2_dac_enum, RT5651_DIG_INF_DATA,
RT5651_IF2_DAC_SEL_SFT, rt5651_data_select);
static SOC_ENUM_SINGLE_DECL(rt5651_if2_adc_enum, RT5651_DIG_INF_DATA,
RT5651_IF2_ADC_SEL_SFT, rt5651_data_select);
static const struct snd_kcontrol_new rt5651_snd_controls[] = {
/* Headphone Output Volume */
SOC_DOUBLE_TLV("HP Playback Volume", RT5651_HP_VOL,
RT5651_L_VOL_SFT, RT5651_R_VOL_SFT, 39, 1, out_vol_tlv),
/* OUTPUT Control */
SOC_DOUBLE_TLV("OUT Playback Volume", RT5651_LOUT_CTRL1,
RT5651_L_VOL_SFT, RT5651_R_VOL_SFT, 39, 1, out_vol_tlv),
/* DAC Digital Volume */
SOC_DOUBLE("DAC2 Playback Switch", RT5651_DAC2_CTRL,
RT5651_M_DAC_L2_VOL_SFT, RT5651_M_DAC_R2_VOL_SFT, 1, 1),
SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5651_DAC1_DIG_VOL,
RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
175, 0, dac_vol_tlv),
SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5651_DAC2_DIG_VOL,
RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
175, 0, dac_vol_tlv),
/* IN1/IN2/IN3 Control */
SOC_SINGLE_TLV("IN1 Boost", RT5651_IN1_IN2,
RT5651_BST_SFT1, 8, 0, bst_tlv),
SOC_SINGLE_TLV("IN2 Boost", RT5651_IN1_IN2,
RT5651_BST_SFT2, 8, 0, bst_tlv),
SOC_SINGLE_TLV("IN3 Boost", RT5651_IN3,
RT5651_BST_SFT1, 8, 0, bst_tlv),
/* INL/INR Volume Control */
SOC_DOUBLE_TLV("IN Capture Volume", RT5651_INL1_INR1_VOL,
RT5651_INL_VOL_SFT, RT5651_INR_VOL_SFT,
31, 1, in_vol_tlv),
/* ADC Digital Volume Control */
SOC_DOUBLE("ADC Capture Switch", RT5651_ADC_DIG_VOL,
RT5651_L_MUTE_SFT, RT5651_R_MUTE_SFT, 1, 1),
SOC_DOUBLE_TLV("ADC Capture Volume", RT5651_ADC_DIG_VOL,
RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
127, 0, adc_vol_tlv),
SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5651_ADC_DATA,
RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
127, 0, adc_vol_tlv),
/* ADC Boost Volume Control */
SOC_DOUBLE_TLV("ADC Boost Gain", RT5651_ADC_BST_VOL,
RT5651_ADC_L_BST_SFT, RT5651_ADC_R_BST_SFT,
3, 0, adc_bst_tlv),
/* ASRC */
SOC_SINGLE("IF1 ASRC Switch", RT5651_PLL_MODE_1,
RT5651_STO1_T_SFT, 1, 0),
SOC_SINGLE("IF2 ASRC Switch", RT5651_PLL_MODE_1,
RT5651_STO2_T_SFT, 1, 0),
SOC_SINGLE("DMIC ASRC Switch", RT5651_PLL_MODE_1,
RT5651_DMIC_1_M_SFT, 1, 0),
SOC_ENUM("ADC IF2 Data Switch", rt5651_if2_adc_enum),
SOC_ENUM("DAC IF2 Data Switch", rt5651_if2_dac_enum),
};
/**
* set_dmic_clk - Set parameter of dmic.
*
* @w: DAPM widget.
* @kcontrol: The kcontrol of this widget.
* @event: Event id.
*
*/
static int set_dmic_clk(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
int idx, rate;
rate = rt5651->sysclk / rl6231_get_pre_div(rt5651->regmap,
RT5651_ADDA_CLK1, RT5651_I2S_PD1_SFT);
idx = rl6231_calc_dmic_clk(rate);
if (idx < 0)
dev_err(component->dev, "Failed to set DMIC clock\n");
else
snd_soc_component_update_bits(component, RT5651_DMIC, RT5651_DMIC_CLK_MASK,
idx << RT5651_DMIC_CLK_SFT);
return idx;
}
/* Digital Mixer */
static const struct snd_kcontrol_new rt5651_sto1_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO1_ADC_MIXER,
RT5651_M_STO1_ADC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO1_ADC_MIXER,
RT5651_M_STO1_ADC_L2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5651_sto1_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO1_ADC_MIXER,
RT5651_M_STO1_ADC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO1_ADC_MIXER,
RT5651_M_STO1_ADC_R2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5651_sto2_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO2_ADC_MIXER,
RT5651_M_STO2_ADC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO2_ADC_MIXER,
RT5651_M_STO2_ADC_L2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5651_sto2_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO2_ADC_MIXER,
RT5651_M_STO2_ADC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO2_ADC_MIXER,
RT5651_M_STO2_ADC_R2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5651_dac_l_mix[] = {
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5651_AD_DA_MIXER,
RT5651_M_ADCMIX_L_SFT, 1, 1),
SOC_DAPM_SINGLE("INF1 Switch", RT5651_AD_DA_MIXER,
RT5651_M_IF1_DAC_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5651_dac_r_mix[] = {
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5651_AD_DA_MIXER,
RT5651_M_ADCMIX_R_SFT, 1, 1),
SOC_DAPM_SINGLE("INF1 Switch", RT5651_AD_DA_MIXER,
RT5651_M_IF1_DAC_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5651_sto_dac_l_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_STO_DAC_MIXER,
RT5651_M_DAC_L1_MIXL_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_STO_DAC_MIXER,
RT5651_M_DAC_L2_MIXL_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_STO_DAC_MIXER,
RT5651_M_DAC_R1_MIXL_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5651_sto_dac_r_mix[] = {
SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_STO_DAC_MIXER,
RT5651_M_DAC_R1_MIXR_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_STO_DAC_MIXER,
RT5651_M_DAC_R2_MIXR_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_STO_DAC_MIXER,
RT5651_M_DAC_L1_MIXR_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5651_dd_dac_l_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_DD_MIXER,
RT5651_M_STO_DD_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_DD_MIXER,
RT5651_M_STO_DD_L2_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_DD_MIXER,
RT5651_M_STO_DD_R2_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5651_dd_dac_r_mix[] = {
SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_DD_MIXER,
RT5651_M_STO_DD_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_DD_MIXER,
RT5651_M_STO_DD_R2_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_DD_MIXER,
RT5651_M_STO_DD_L2_R_SFT, 1, 1),
};
/* Analog Input Mixer */
static const struct snd_kcontrol_new rt5651_rec_l_mix[] = {
SOC_DAPM_SINGLE("INL1 Switch", RT5651_REC_L2_MIXER,
RT5651_M_IN1_L_RM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST3 Switch", RT5651_REC_L2_MIXER,
RT5651_M_BST3_RM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5651_REC_L2_MIXER,
RT5651_M_BST2_RM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5651_REC_L2_MIXER,
RT5651_M_BST1_RM_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5651_rec_r_mix[] = {
SOC_DAPM_SINGLE("INR1 Switch", RT5651_REC_R2_MIXER,
RT5651_M_IN1_R_RM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST3 Switch", RT5651_REC_R2_MIXER,
RT5651_M_BST3_RM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5651_REC_R2_MIXER,
RT5651_M_BST2_RM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5651_REC_R2_MIXER,
RT5651_M_BST1_RM_R_SFT, 1, 1),
};
/* Analog Output Mixer */
static const struct snd_kcontrol_new rt5651_out_l_mix[] = {
SOC_DAPM_SINGLE("BST1 Switch", RT5651_OUT_L3_MIXER,
RT5651_M_BST1_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5651_OUT_L3_MIXER,
RT5651_M_BST2_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("INL1 Switch", RT5651_OUT_L3_MIXER,
RT5651_M_IN1_L_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("REC MIXL Switch", RT5651_OUT_L3_MIXER,
RT5651_M_RM_L_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_OUT_L3_MIXER,
RT5651_M_DAC_L1_OM_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5651_out_r_mix[] = {
SOC_DAPM_SINGLE("BST2 Switch", RT5651_OUT_R3_MIXER,
RT5651_M_BST2_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5651_OUT_R3_MIXER,
RT5651_M_BST1_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("INR1 Switch", RT5651_OUT_R3_MIXER,
RT5651_M_IN1_R_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("REC MIXR Switch", RT5651_OUT_R3_MIXER,
RT5651_M_RM_R_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_OUT_R3_MIXER,
RT5651_M_DAC_R1_OM_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5651_hpo_mix[] = {
SOC_DAPM_SINGLE("HPO MIX DAC1 Switch", RT5651_HPO_MIXER,
RT5651_M_DAC1_HM_SFT, 1, 1),
SOC_DAPM_SINGLE("HPO MIX HPVOL Switch", RT5651_HPO_MIXER,
RT5651_M_HPVOL_HM_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5651_lout_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_LOUT_MIXER,
RT5651_M_DAC_L1_LM_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_LOUT_MIXER,
RT5651_M_DAC_R1_LM_SFT, 1, 1),
SOC_DAPM_SINGLE("OUTVOL L Switch", RT5651_LOUT_MIXER,
RT5651_M_OV_L_LM_SFT, 1, 1),
SOC_DAPM_SINGLE("OUTVOL R Switch", RT5651_LOUT_MIXER,
RT5651_M_OV_R_LM_SFT, 1, 1),
};
static const struct snd_kcontrol_new outvol_l_control =
SOC_DAPM_SINGLE("Switch", RT5651_LOUT_CTRL1,
RT5651_VOL_L_SFT, 1, 1);
static const struct snd_kcontrol_new outvol_r_control =
SOC_DAPM_SINGLE("Switch", RT5651_LOUT_CTRL1,
RT5651_VOL_R_SFT, 1, 1);
static const struct snd_kcontrol_new lout_l_mute_control =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_LOUT_CTRL1,
RT5651_L_MUTE_SFT, 1, 1);
static const struct snd_kcontrol_new lout_r_mute_control =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_LOUT_CTRL1,
RT5651_R_MUTE_SFT, 1, 1);
static const struct snd_kcontrol_new hpovol_l_control =
SOC_DAPM_SINGLE("Switch", RT5651_HP_VOL,
RT5651_VOL_L_SFT, 1, 1);
static const struct snd_kcontrol_new hpovol_r_control =
SOC_DAPM_SINGLE("Switch", RT5651_HP_VOL,
RT5651_VOL_R_SFT, 1, 1);
static const struct snd_kcontrol_new hpo_l_mute_control =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_HP_VOL,
RT5651_L_MUTE_SFT, 1, 1);
static const struct snd_kcontrol_new hpo_r_mute_control =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_HP_VOL,
RT5651_R_MUTE_SFT, 1, 1);
/* Stereo ADC source */
static const char * const rt5651_stereo1_adc1_src[] = {"DD MIX", "ADC"};
static SOC_ENUM_SINGLE_DECL(
rt5651_stereo1_adc1_enum, RT5651_STO1_ADC_MIXER,
RT5651_STO1_ADC_1_SRC_SFT, rt5651_stereo1_adc1_src);
static const struct snd_kcontrol_new rt5651_sto1_adc_l1_mux =
SOC_DAPM_ENUM("Stereo1 ADC L1 source", rt5651_stereo1_adc1_enum);
static const struct snd_kcontrol_new rt5651_sto1_adc_r1_mux =
SOC_DAPM_ENUM("Stereo1 ADC R1 source", rt5651_stereo1_adc1_enum);
static const char * const rt5651_stereo1_adc2_src[] = {"DMIC", "DD MIX"};
static SOC_ENUM_SINGLE_DECL(
rt5651_stereo1_adc2_enum, RT5651_STO1_ADC_MIXER,
RT5651_STO1_ADC_2_SRC_SFT, rt5651_stereo1_adc2_src);
static const struct snd_kcontrol_new rt5651_sto1_adc_l2_mux =
SOC_DAPM_ENUM("Stereo1 ADC L2 source", rt5651_stereo1_adc2_enum);
static const struct snd_kcontrol_new rt5651_sto1_adc_r2_mux =
SOC_DAPM_ENUM("Stereo1 ADC R2 source", rt5651_stereo1_adc2_enum);
/* Mono ADC source */
static const char * const rt5651_sto2_adc_l1_src[] = {"DD MIXL", "ADCL"};
static SOC_ENUM_SINGLE_DECL(
rt5651_sto2_adc_l1_enum, RT5651_STO1_ADC_MIXER,
RT5651_STO2_ADC_L1_SRC_SFT, rt5651_sto2_adc_l1_src);
static const struct snd_kcontrol_new rt5651_sto2_adc_l1_mux =
SOC_DAPM_ENUM("Stereo2 ADC1 left source", rt5651_sto2_adc_l1_enum);
static const char * const rt5651_sto2_adc_l2_src[] = {"DMIC L", "DD MIXL"};
static SOC_ENUM_SINGLE_DECL(
rt5651_sto2_adc_l2_enum, RT5651_STO1_ADC_MIXER,
RT5651_STO2_ADC_L2_SRC_SFT, rt5651_sto2_adc_l2_src);
static const struct snd_kcontrol_new rt5651_sto2_adc_l2_mux =
SOC_DAPM_ENUM("Stereo2 ADC2 left source", rt5651_sto2_adc_l2_enum);
static const char * const rt5651_sto2_adc_r1_src[] = {"DD MIXR", "ADCR"};
static SOC_ENUM_SINGLE_DECL(
rt5651_sto2_adc_r1_enum, RT5651_STO1_ADC_MIXER,
RT5651_STO2_ADC_R1_SRC_SFT, rt5651_sto2_adc_r1_src);
static const struct snd_kcontrol_new rt5651_sto2_adc_r1_mux =
SOC_DAPM_ENUM("Stereo2 ADC1 right source", rt5651_sto2_adc_r1_enum);
static const char * const rt5651_sto2_adc_r2_src[] = {"DMIC R", "DD MIXR"};
static SOC_ENUM_SINGLE_DECL(
rt5651_sto2_adc_r2_enum, RT5651_STO1_ADC_MIXER,
RT5651_STO2_ADC_R2_SRC_SFT, rt5651_sto2_adc_r2_src);
static const struct snd_kcontrol_new rt5651_sto2_adc_r2_mux =
SOC_DAPM_ENUM("Stereo2 ADC2 right source", rt5651_sto2_adc_r2_enum);
/* DAC2 channel source */
static const char * const rt5651_dac_src[] = {"IF1", "IF2"};
static SOC_ENUM_SINGLE_DECL(rt5651_dac_l2_enum, RT5651_DAC2_CTRL,
RT5651_SEL_DAC_L2_SFT, rt5651_dac_src);
static const struct snd_kcontrol_new rt5651_dac_l2_mux =
SOC_DAPM_ENUM("DAC2 left channel source", rt5651_dac_l2_enum);
static SOC_ENUM_SINGLE_DECL(
rt5651_dac_r2_enum, RT5651_DAC2_CTRL,
RT5651_SEL_DAC_R2_SFT, rt5651_dac_src);
static const struct snd_kcontrol_new rt5651_dac_r2_mux =
SOC_DAPM_ENUM("DAC2 right channel source", rt5651_dac_r2_enum);
/* IF2_ADC channel source */
static const char * const rt5651_adc_src[] = {"IF1 ADC1", "IF1 ADC2"};
static SOC_ENUM_SINGLE_DECL(rt5651_if2_adc_src_enum, RT5651_DIG_INF_DATA,
RT5651_IF2_ADC_SRC_SFT, rt5651_adc_src);
static const struct snd_kcontrol_new rt5651_if2_adc_src_mux =
SOC_DAPM_ENUM("IF2 ADC channel source", rt5651_if2_adc_src_enum);
/* PDM select */
static const char * const rt5651_pdm_sel[] = {"DD MIX", "Stereo DAC MIX"};
static SOC_ENUM_SINGLE_DECL(
rt5651_pdm_l_sel_enum, RT5651_PDM_CTL,
RT5651_PDM_L_SEL_SFT, rt5651_pdm_sel);
static SOC_ENUM_SINGLE_DECL(
rt5651_pdm_r_sel_enum, RT5651_PDM_CTL,
RT5651_PDM_R_SEL_SFT, rt5651_pdm_sel);
static const struct snd_kcontrol_new rt5651_pdm_l_mux =
SOC_DAPM_ENUM("PDM L select", rt5651_pdm_l_sel_enum);
static const struct snd_kcontrol_new rt5651_pdm_r_mux =
SOC_DAPM_ENUM("PDM R select", rt5651_pdm_r_sel_enum);
static int rt5651_amp_power_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
/* depop parameters */
regmap_update_bits(rt5651->regmap, RT5651_PR_BASE +
RT5651_CHPUMP_INT_REG1, 0x0700, 0x0200);
regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M2,
RT5651_DEPOP_MASK, RT5651_DEPOP_MAN);
regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M1,
RT5651_HP_CP_MASK | RT5651_HP_SG_MASK |
RT5651_HP_CB_MASK, RT5651_HP_CP_PU |
RT5651_HP_SG_DIS | RT5651_HP_CB_PU);
regmap_write(rt5651->regmap, RT5651_PR_BASE +
RT5651_HP_DCC_INT1, 0x9f00);
/* headphone amp power on */
regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1,
RT5651_PWR_FV1 | RT5651_PWR_FV2, 0);
regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1,
RT5651_PWR_HA,
RT5651_PWR_HA);
usleep_range(10000, 15000);
regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1,
RT5651_PWR_FV1 | RT5651_PWR_FV2 ,
RT5651_PWR_FV1 | RT5651_PWR_FV2);
break;
default:
return 0;
}
return 0;
}
static int rt5651_hp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
/* headphone unmute sequence */
regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M2,
RT5651_DEPOP_MASK | RT5651_DIG_DP_MASK,
RT5651_DEPOP_AUTO | RT5651_DIG_DP_EN);
regmap_update_bits(rt5651->regmap, RT5651_CHARGE_PUMP,
RT5651_PM_HP_MASK, RT5651_PM_HP_HV);
regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M3,
RT5651_CP_FQ1_MASK | RT5651_CP_FQ2_MASK |
RT5651_CP_FQ3_MASK,
(RT5651_CP_FQ_192_KHZ << RT5651_CP_FQ1_SFT) |
(RT5651_CP_FQ_12_KHZ << RT5651_CP_FQ2_SFT) |
(RT5651_CP_FQ_192_KHZ << RT5651_CP_FQ3_SFT));
regmap_write(rt5651->regmap, RT5651_PR_BASE +
RT5651_MAMP_INT_REG2, 0x1c00);
regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M1,
RT5651_HP_CP_MASK | RT5651_HP_SG_MASK,
RT5651_HP_CP_PD | RT5651_HP_SG_EN);
regmap_update_bits(rt5651->regmap, RT5651_PR_BASE +
RT5651_CHPUMP_INT_REG1, 0x0700, 0x0400);
rt5651->hp_mute = false;
break;
case SND_SOC_DAPM_PRE_PMD:
rt5651->hp_mute = true;
usleep_range(70000, 75000);
break;
default:
return 0;
}
return 0;
}
static int rt5651_hp_post_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
if (!rt5651->hp_mute)
usleep_range(80000, 85000);
break;
default:
return 0;
}
return 0;
}
static int rt5651_bst1_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
RT5651_PWR_BST1_OP2, RT5651_PWR_BST1_OP2);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
RT5651_PWR_BST1_OP2, 0);
break;
default:
return 0;
}
return 0;
}
static int rt5651_bst2_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
RT5651_PWR_BST2_OP2, RT5651_PWR_BST2_OP2);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
RT5651_PWR_BST2_OP2, 0);
break;
default:
return 0;
}
return 0;
}
static int rt5651_bst3_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
RT5651_PWR_BST3_OP2, RT5651_PWR_BST3_OP2);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
RT5651_PWR_BST3_OP2, 0);
break;
default:
return 0;
}
return 0;
}
static const struct snd_soc_dapm_widget rt5651_dapm_widgets[] = {
/* ASRC */
SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5651_PLL_MODE_2,
15, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5651_PLL_MODE_2,
14, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("STO1 DAC ASRC", 1, RT5651_PLL_MODE_2,
13, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("STO2 DAC ASRC", 1, RT5651_PLL_MODE_2,
12, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADC ASRC", 1, RT5651_PLL_MODE_2,
11, 0, NULL, 0),
/* micbias */
SND_SOC_DAPM_SUPPLY("LDO", RT5651_PWR_ANLG1,
RT5651_PWR_LDO_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("micbias1", RT5651_PWR_ANLG2,
RT5651_PWR_MB1_BIT, 0, NULL, 0),
/* Input Lines */
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_INPUT("MIC2"),
SND_SOC_DAPM_INPUT("MIC3"),
SND_SOC_DAPM_INPUT("IN1P"),
SND_SOC_DAPM_INPUT("IN2P"),
SND_SOC_DAPM_INPUT("IN2N"),
SND_SOC_DAPM_INPUT("IN3P"),
SND_SOC_DAPM_INPUT("DMIC L1"),
SND_SOC_DAPM_INPUT("DMIC R1"),
SND_SOC_DAPM_SUPPLY("DMIC CLK", RT5651_DMIC, RT5651_DMIC_1_EN_SFT,
0, set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
/* Boost */
SND_SOC_DAPM_PGA_E("BST1", RT5651_PWR_ANLG2,
RT5651_PWR_BST1_BIT, 0, NULL, 0, rt5651_bst1_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("BST2", RT5651_PWR_ANLG2,
RT5651_PWR_BST2_BIT, 0, NULL, 0, rt5651_bst2_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("BST3", RT5651_PWR_ANLG2,
RT5651_PWR_BST3_BIT, 0, NULL, 0, rt5651_bst3_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
/* Input Volume */
SND_SOC_DAPM_PGA("INL1 VOL", RT5651_PWR_VOL,
RT5651_PWR_IN1_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("INR1 VOL", RT5651_PWR_VOL,
RT5651_PWR_IN1_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("INL2 VOL", RT5651_PWR_VOL,
RT5651_PWR_IN2_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("INR2 VOL", RT5651_PWR_VOL,
RT5651_PWR_IN2_R_BIT, 0, NULL, 0),
/* REC Mixer */
SND_SOC_DAPM_MIXER("RECMIXL", RT5651_PWR_MIXER, RT5651_PWR_RM_L_BIT, 0,
rt5651_rec_l_mix, ARRAY_SIZE(rt5651_rec_l_mix)),
SND_SOC_DAPM_MIXER("RECMIXR", RT5651_PWR_MIXER, RT5651_PWR_RM_R_BIT, 0,
rt5651_rec_r_mix, ARRAY_SIZE(rt5651_rec_r_mix)),
/* ADCs */
SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SUPPLY("ADC L Power", RT5651_PWR_DIG1,
RT5651_PWR_ADC_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC R Power", RT5651_PWR_DIG1,
RT5651_PWR_ADC_R_BIT, 0, NULL, 0),
/* ADC Mux */
SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
&rt5651_sto1_adc_l2_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
&rt5651_sto1_adc_r2_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
&rt5651_sto1_adc_l1_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
&rt5651_sto1_adc_r1_mux),
SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
&rt5651_sto2_adc_l2_mux),
SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
&rt5651_sto2_adc_l1_mux),
SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
&rt5651_sto2_adc_r1_mux),
SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
&rt5651_sto2_adc_r2_mux),
/* ADC Mixer */
SND_SOC_DAPM_SUPPLY("Stereo1 Filter", RT5651_PWR_DIG2,
RT5651_PWR_ADC_STO1_F_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Stereo2 Filter", RT5651_PWR_DIG2,
RT5651_PWR_ADC_STO2_F_BIT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0,
rt5651_sto1_adc_l_mix,
ARRAY_SIZE(rt5651_sto1_adc_l_mix)),
SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0,
rt5651_sto1_adc_r_mix,
ARRAY_SIZE(rt5651_sto1_adc_r_mix)),
SND_SOC_DAPM_MIXER("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0,
rt5651_sto2_adc_l_mix,
ARRAY_SIZE(rt5651_sto2_adc_l_mix)),
SND_SOC_DAPM_MIXER("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0,
rt5651_sto2_adc_r_mix,
ARRAY_SIZE(rt5651_sto2_adc_r_mix)),
/* Digital Interface */
SND_SOC_DAPM_SUPPLY("I2S1", RT5651_PWR_DIG1,
RT5651_PWR_I2S1_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("I2S2", RT5651_PWR_DIG1,
RT5651_PWR_I2S2_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX("IF2 ADC", SND_SOC_NOPM, 0, 0,
&rt5651_if2_adc_src_mux),
/* Digital Interface Select */
SND_SOC_DAPM_MUX("PDM L Mux", RT5651_PDM_CTL,
RT5651_M_PDM_L_SFT, 1, &rt5651_pdm_l_mux),
SND_SOC_DAPM_MUX("PDM R Mux", RT5651_PDM_CTL,
RT5651_M_PDM_R_SFT, 1, &rt5651_pdm_r_mux),
/* Audio Interface */
SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
/* Audio DSP */
SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
/* Output Side */
/* DAC mixer before sound effect */
SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
rt5651_dac_l_mix, ARRAY_SIZE(rt5651_dac_l_mix)),
SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
rt5651_dac_r_mix, ARRAY_SIZE(rt5651_dac_r_mix)),
/* DAC2 channel Mux */
SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_dac_l2_mux),
SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_dac_r2_mux),
SND_SOC_DAPM_PGA("DAC L2 Volume", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DAC R2 Volume", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Stero1 DAC Power", RT5651_PWR_DIG2,
RT5651_PWR_DAC_STO1_F_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Stero2 DAC Power", RT5651_PWR_DIG2,
RT5651_PWR_DAC_STO2_F_BIT, 0, NULL, 0),
/* DAC Mixer */
SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
rt5651_sto_dac_l_mix,
ARRAY_SIZE(rt5651_sto_dac_l_mix)),
SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
rt5651_sto_dac_r_mix,
ARRAY_SIZE(rt5651_sto_dac_r_mix)),
SND_SOC_DAPM_MIXER("DD MIXL", SND_SOC_NOPM, 0, 0,
rt5651_dd_dac_l_mix,
ARRAY_SIZE(rt5651_dd_dac_l_mix)),
SND_SOC_DAPM_MIXER("DD MIXR", SND_SOC_NOPM, 0, 0,
rt5651_dd_dac_r_mix,
ARRAY_SIZE(rt5651_dd_dac_r_mix)),
/* DACs */
SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SUPPLY("DAC L1 Power", RT5651_PWR_DIG1,
RT5651_PWR_DAC_L1_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC R1 Power", RT5651_PWR_DIG1,
RT5651_PWR_DAC_R1_BIT, 0, NULL, 0),
/* OUT Mixer */
SND_SOC_DAPM_MIXER("OUT MIXL", RT5651_PWR_MIXER, RT5651_PWR_OM_L_BIT,
0, rt5651_out_l_mix, ARRAY_SIZE(rt5651_out_l_mix)),
SND_SOC_DAPM_MIXER("OUT MIXR", RT5651_PWR_MIXER, RT5651_PWR_OM_R_BIT,
0, rt5651_out_r_mix, ARRAY_SIZE(rt5651_out_r_mix)),
/* Ouput Volume */
SND_SOC_DAPM_SWITCH("OUTVOL L", RT5651_PWR_VOL,
RT5651_PWR_OV_L_BIT, 0, &outvol_l_control),
SND_SOC_DAPM_SWITCH("OUTVOL R", RT5651_PWR_VOL,
RT5651_PWR_OV_R_BIT, 0, &outvol_r_control),
SND_SOC_DAPM_SWITCH("HPOVOL L", RT5651_PWR_VOL,
RT5651_PWR_HV_L_BIT, 0, &hpovol_l_control),
SND_SOC_DAPM_SWITCH("HPOVOL R", RT5651_PWR_VOL,
RT5651_PWR_HV_R_BIT, 0, &hpovol_r_control),
SND_SOC_DAPM_PGA("INL1", RT5651_PWR_VOL,
RT5651_PWR_IN1_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("INR1", RT5651_PWR_VOL,
RT5651_PWR_IN1_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("INL2", RT5651_PWR_VOL,
RT5651_PWR_IN2_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("INR2", RT5651_PWR_VOL,
RT5651_PWR_IN2_R_BIT, 0, NULL, 0),
/* HPO/LOUT/Mono Mixer */
SND_SOC_DAPM_MIXER("HPOL MIX", SND_SOC_NOPM, 0, 0,
rt5651_hpo_mix, ARRAY_SIZE(rt5651_hpo_mix)),
SND_SOC_DAPM_MIXER("HPOR MIX", SND_SOC_NOPM, 0, 0,
rt5651_hpo_mix, ARRAY_SIZE(rt5651_hpo_mix)),
SND_SOC_DAPM_SUPPLY("HP L Amp", RT5651_PWR_ANLG1,
RT5651_PWR_HP_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("HP R Amp", RT5651_PWR_ANLG1,
RT5651_PWR_HP_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("LOUT MIX", RT5651_PWR_ANLG1, RT5651_PWR_LM_BIT, 0,
rt5651_lout_mix, ARRAY_SIZE(rt5651_lout_mix)),
SND_SOC_DAPM_SUPPLY("Amp Power", RT5651_PWR_ANLG1,
RT5651_PWR_HA_BIT, 0, rt5651_amp_power_event,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5651_hp_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SWITCH("HPO L Playback", SND_SOC_NOPM, 0, 0,
&hpo_l_mute_control),
SND_SOC_DAPM_SWITCH("HPO R Playback", SND_SOC_NOPM, 0, 0,
&hpo_r_mute_control),
SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
&lout_l_mute_control),
SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
&lout_r_mute_control),
SND_SOC_DAPM_POST("HP Post", rt5651_hp_post_event),
/* Output Lines */
SND_SOC_DAPM_OUTPUT("HPOL"),
SND_SOC_DAPM_OUTPUT("HPOR"),
SND_SOC_DAPM_OUTPUT("LOUTL"),
SND_SOC_DAPM_OUTPUT("LOUTR"),
SND_SOC_DAPM_OUTPUT("PDML"),
SND_SOC_DAPM_OUTPUT("PDMR"),
};
static const struct snd_soc_dapm_route rt5651_dapm_routes[] = {
{"Stero1 DAC Power", NULL, "STO1 DAC ASRC"},
{"Stero2 DAC Power", NULL, "STO2 DAC ASRC"},
{"I2S1", NULL, "I2S1 ASRC"},
{"I2S2", NULL, "I2S2 ASRC"},
{"IN1P", NULL, "LDO"},
{"IN2P", NULL, "LDO"},
{"IN3P", NULL, "LDO"},
{"IN1P", NULL, "MIC1"},
{"IN2P", NULL, "MIC2"},
{"IN2N", NULL, "MIC2"},
{"IN3P", NULL, "MIC3"},
{"BST1", NULL, "IN1P"},
{"BST2", NULL, "IN2P"},
{"BST2", NULL, "IN2N"},
{"BST3", NULL, "IN3P"},
{"INL1 VOL", NULL, "IN2P"},
{"INR1 VOL", NULL, "IN2N"},
{"RECMIXL", "INL1 Switch", "INL1 VOL"},
{"RECMIXL", "BST3 Switch", "BST3"},
{"RECMIXL", "BST2 Switch", "BST2"},
{"RECMIXL", "BST1 Switch", "BST1"},
{"RECMIXR", "INR1 Switch", "INR1 VOL"},
{"RECMIXR", "BST3 Switch", "BST3"},
{"RECMIXR", "BST2 Switch", "BST2"},
{"RECMIXR", "BST1 Switch", "BST1"},
{"ADC L", NULL, "RECMIXL"},
{"ADC L", NULL, "ADC L Power"},
{"ADC R", NULL, "RECMIXR"},
{"ADC R", NULL, "ADC R Power"},
{"DMIC L1", NULL, "DMIC CLK"},
{"DMIC R1", NULL, "DMIC CLK"},
{"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
{"Stereo1 ADC L2 Mux", "DD MIX", "DD MIXL"},
{"Stereo1 ADC L1 Mux", "ADC", "ADC L"},
{"Stereo1 ADC L1 Mux", "DD MIX", "DD MIXL"},
{"Stereo1 ADC R1 Mux", "ADC", "ADC R"},
{"Stereo1 ADC R1 Mux", "DD MIX", "DD MIXR"},
{"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
{"Stereo1 ADC R2 Mux", "DD MIX", "DD MIXR"},
{"Stereo2 ADC L2 Mux", "DMIC L", "DMIC L1"},
{"Stereo2 ADC L2 Mux", "DD MIXL", "DD MIXL"},
{"Stereo2 ADC L1 Mux", "DD MIXL", "DD MIXL"},
{"Stereo2 ADC L1 Mux", "ADCL", "ADC L"},
{"Stereo2 ADC R1 Mux", "DD MIXR", "DD MIXR"},
{"Stereo2 ADC R1 Mux", "ADCR", "ADC R"},
{"Stereo2 ADC R2 Mux", "DMIC R", "DMIC R1"},
{"Stereo2 ADC R2 Mux", "DD MIXR", "DD MIXR"},
{"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
{"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
{"Stereo1 ADC MIXL", NULL, "Stereo1 Filter"},
{"Stereo1 Filter", NULL, "ADC ASRC"},
{"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
{"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
{"Stereo1 ADC MIXR", NULL, "Stereo1 Filter"},
{"Stereo2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux"},
{"Stereo2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux"},
{"Stereo2 ADC MIXL", NULL, "Stereo2 Filter"},
{"Stereo2 Filter", NULL, "ADC ASRC"},
{"Stereo2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux"},
{"Stereo2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux"},
{"Stereo2 ADC MIXR", NULL, "Stereo2 Filter"},
{"IF1 ADC2", NULL, "Stereo2 ADC MIXL"},
{"IF1 ADC2", NULL, "Stereo2 ADC MIXR"},
{"IF1 ADC1", NULL, "Stereo1 ADC MIXL"},
{"IF1 ADC1", NULL, "Stereo1 ADC MIXR"},
{"IF1 ADC1", NULL, "I2S1"},
{"IF2 ADC", "IF1 ADC1", "IF1 ADC1"},
{"IF2 ADC", "IF1 ADC2", "IF1 ADC2"},
{"IF2 ADC", NULL, "I2S2"},
{"AIF1TX", NULL, "IF1 ADC1"},
{"AIF1TX", NULL, "IF1 ADC2"},
{"AIF2TX", NULL, "IF2 ADC"},
{"IF1 DAC", NULL, "AIF1RX"},
{"IF1 DAC", NULL, "I2S1"},
{"IF2 DAC", NULL, "AIF2RX"},
{"IF2 DAC", NULL, "I2S2"},
{"IF1 DAC1 L", NULL, "IF1 DAC"},
{"IF1 DAC1 R", NULL, "IF1 DAC"},
{"IF1 DAC2 L", NULL, "IF1 DAC"},
{"IF1 DAC2 R", NULL, "IF1 DAC"},
{"IF2 DAC L", NULL, "IF2 DAC"},
{"IF2 DAC R", NULL, "IF2 DAC"},
{"DAC MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
{"DAC MIXL", "INF1 Switch", "IF1 DAC1 L"},
{"DAC MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
{"DAC MIXR", "INF1 Switch", "IF1 DAC1 R"},
{"Audio DSP", NULL, "DAC MIXL"},
{"Audio DSP", NULL, "DAC MIXR"},
{"DAC L2 Mux", "IF1", "IF1 DAC2 L"},
{"DAC L2 Mux", "IF2", "IF2 DAC L"},
{"DAC L2 Volume", NULL, "DAC L2 Mux"},
{"DAC R2 Mux", "IF1", "IF1 DAC2 R"},
{"DAC R2 Mux", "IF2", "IF2 DAC R"},
{"DAC R2 Volume", NULL, "DAC R2 Mux"},
{"Stereo DAC MIXL", "DAC L1 Switch", "Audio DSP"},
{"Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume"},
{"Stereo DAC MIXL", "DAC R1 Switch", "DAC MIXR"},
{"Stereo DAC MIXL", NULL, "Stero1 DAC Power"},
{"Stereo DAC MIXL", NULL, "Stero2 DAC Power"},
{"Stereo DAC MIXR", "DAC R1 Switch", "Audio DSP"},
{"Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume"},
{"Stereo DAC MIXR", "DAC L1 Switch", "DAC MIXL"},
{"Stereo DAC MIXR", NULL, "Stero1 DAC Power"},
{"Stereo DAC MIXR", NULL, "Stero2 DAC Power"},
{"PDM L Mux", "Stereo DAC MIX", "Stereo DAC MIXL"},
{"PDM L Mux", "DD MIX", "DAC MIXL"},
{"PDM R Mux", "Stereo DAC MIX", "Stereo DAC MIXR"},
{"PDM R Mux", "DD MIX", "DAC MIXR"},
{"DAC L1", NULL, "Stereo DAC MIXL"},
{"DAC L1", NULL, "DAC L1 Power"},
{"DAC R1", NULL, "Stereo DAC MIXR"},
{"DAC R1", NULL, "DAC R1 Power"},
{"DD MIXL", "DAC L1 Switch", "DAC MIXL"},
{"DD MIXL", "DAC L2 Switch", "DAC L2 Volume"},
{"DD MIXL", "DAC R2 Switch", "DAC R2 Volume"},
{"DD MIXL", NULL, "Stero2 DAC Power"},
{"DD MIXR", "DAC R1 Switch", "DAC MIXR"},
{"DD MIXR", "DAC R2 Switch", "DAC R2 Volume"},
{"DD MIXR", "DAC L2 Switch", "DAC L2 Volume"},
{"DD MIXR", NULL, "Stero2 DAC Power"},
{"OUT MIXL", "BST1 Switch", "BST1"},
{"OUT MIXL", "BST2 Switch", "BST2"},
{"OUT MIXL", "INL1 Switch", "INL1 VOL"},
{"OUT MIXL", "REC MIXL Switch", "RECMIXL"},
{"OUT MIXL", "DAC L1 Switch", "DAC L1"},
{"OUT MIXR", "BST2 Switch", "BST2"},
{"OUT MIXR", "BST1 Switch", "BST1"},
{"OUT MIXR", "INR1 Switch", "INR1 VOL"},
{"OUT MIXR", "REC MIXR Switch", "RECMIXR"},
{"OUT MIXR", "DAC R1 Switch", "DAC R1"},
{"HPOVOL L", "Switch", "OUT MIXL"},
{"HPOVOL R", "Switch", "OUT MIXR"},
{"OUTVOL L", "Switch", "OUT MIXL"},
{"OUTVOL R", "Switch", "OUT MIXR"},
{"HPOL MIX", "HPO MIX DAC1 Switch", "DAC L1"},
{"HPOL MIX", "HPO MIX HPVOL Switch", "HPOVOL L"},
{"HPOL MIX", NULL, "HP L Amp"},
{"HPOR MIX", "HPO MIX DAC1 Switch", "DAC R1"},
{"HPOR MIX", "HPO MIX HPVOL Switch", "HPOVOL R"},
{"HPOR MIX", NULL, "HP R Amp"},
{"LOUT MIX", "DAC L1 Switch", "DAC L1"},
{"LOUT MIX", "DAC R1 Switch", "DAC R1"},
{"LOUT MIX", "OUTVOL L Switch", "OUTVOL L"},
{"LOUT MIX", "OUTVOL R Switch", "OUTVOL R"},
{"HP Amp", NULL, "HPOL MIX"},
{"HP Amp", NULL, "HPOR MIX"},
{"HP Amp", NULL, "Amp Power"},
{"HPO L Playback", "Switch", "HP Amp"},
{"HPO R Playback", "Switch", "HP Amp"},
{"HPOL", NULL, "HPO L Playback"},
{"HPOR", NULL, "HPO R Playback"},
{"LOUT L Playback", "Switch", "LOUT MIX"},
{"LOUT R Playback", "Switch", "LOUT MIX"},
{"LOUTL", NULL, "LOUT L Playback"},
{"LOUTL", NULL, "Amp Power"},
{"LOUTR", NULL, "LOUT R Playback"},
{"LOUTR", NULL, "Amp Power"},
{"PDML", NULL, "PDM L Mux"},
{"PDMR", NULL, "PDM R Mux"},
};
static int rt5651_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
unsigned int val_len = 0, val_clk, mask_clk;
int pre_div, bclk_ms, frame_size;
rt5651->lrck[dai->id] = params_rate(params);
pre_div = rl6231_get_clk_info(rt5651->sysclk, rt5651->lrck[dai->id]);
if (pre_div < 0) {
dev_err(component->dev, "Unsupported clock setting\n");
return -EINVAL;
}
frame_size = snd_soc_params_to_frame_size(params);
if (frame_size < 0) {
dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
return -EINVAL;
}
bclk_ms = frame_size > 32 ? 1 : 0;
rt5651->bclk[dai->id] = rt5651->lrck[dai->id] * (32 << bclk_ms);
dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
rt5651->bclk[dai->id], rt5651->lrck[dai->id]);
dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
bclk_ms, pre_div, dai->id);
switch (params_width(params)) {
case 16:
break;
case 20:
val_len |= RT5651_I2S_DL_20;
break;
case 24:
val_len |= RT5651_I2S_DL_24;
break;
case 8:
val_len |= RT5651_I2S_DL_8;
break;
default:
return -EINVAL;
}
switch (dai->id) {
case RT5651_AIF1:
mask_clk = RT5651_I2S_PD1_MASK;
val_clk = pre_div << RT5651_I2S_PD1_SFT;
snd_soc_component_update_bits(component, RT5651_I2S1_SDP,
RT5651_I2S_DL_MASK, val_len);
snd_soc_component_update_bits(component, RT5651_ADDA_CLK1, mask_clk, val_clk);
break;
case RT5651_AIF2:
mask_clk = RT5651_I2S_BCLK_MS2_MASK | RT5651_I2S_PD2_MASK;
val_clk = pre_div << RT5651_I2S_PD2_SFT;
snd_soc_component_update_bits(component, RT5651_I2S2_SDP,
RT5651_I2S_DL_MASK, val_len);
snd_soc_component_update_bits(component, RT5651_ADDA_CLK1, mask_clk, val_clk);
break;
default:
dev_err(component->dev, "Wrong dai->id: %d\n", dai->id);
return -EINVAL;
}
return 0;
}
static int rt5651_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
rt5651->master[dai->id] = 1;
break;
case SND_SOC_DAIFMT_CBS_CFS:
reg_val |= RT5651_I2S_MS_S;
rt5651->master[dai->id] = 0;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
reg_val |= RT5651_I2S_BP_INV;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_LEFT_J:
reg_val |= RT5651_I2S_DF_LEFT;
break;
case SND_SOC_DAIFMT_DSP_A:
reg_val |= RT5651_I2S_DF_PCM_A;
break;
case SND_SOC_DAIFMT_DSP_B:
reg_val |= RT5651_I2S_DF_PCM_B;
break;
default:
return -EINVAL;
}
switch (dai->id) {
case RT5651_AIF1:
snd_soc_component_update_bits(component, RT5651_I2S1_SDP,
RT5651_I2S_MS_MASK | RT5651_I2S_BP_MASK |
RT5651_I2S_DF_MASK, reg_val);
break;
case RT5651_AIF2:
snd_soc_component_update_bits(component, RT5651_I2S2_SDP,
RT5651_I2S_MS_MASK | RT5651_I2S_BP_MASK |
RT5651_I2S_DF_MASK, reg_val);
break;
default:
dev_err(component->dev, "Wrong dai->id: %d\n", dai->id);
return -EINVAL;
}
return 0;
}
static int rt5651_set_dai_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0;
unsigned int pll_bit = 0;
if (freq == rt5651->sysclk && clk_id == rt5651->sysclk_src)
return 0;
switch (clk_id) {
case RT5651_SCLK_S_MCLK:
reg_val |= RT5651_SCLK_SRC_MCLK;
break;
case RT5651_SCLK_S_PLL1:
reg_val |= RT5651_SCLK_SRC_PLL1;
pll_bit |= RT5651_PWR_PLL;
break;
case RT5651_SCLK_S_RCCLK:
reg_val |= RT5651_SCLK_SRC_RCCLK;
break;
default:
dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
return -EINVAL;
}
snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
RT5651_PWR_PLL, pll_bit);
snd_soc_component_update_bits(component, RT5651_GLB_CLK,
RT5651_SCLK_SRC_MASK, reg_val);
rt5651->sysclk = freq;
rt5651->sysclk_src = clk_id;
dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
return 0;
}
static int rt5651_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
unsigned int freq_in, unsigned int freq_out)
{
struct snd_soc_component *component = dai->component;
struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
struct rl6231_pll_code pll_code;
int ret;
if (source == rt5651->pll_src && freq_in == rt5651->pll_in &&
freq_out == rt5651->pll_out)
return 0;
if (!freq_in || !freq_out) {
dev_dbg(component->dev, "PLL disabled\n");
rt5651->pll_in = 0;
rt5651->pll_out = 0;
snd_soc_component_update_bits(component, RT5651_GLB_CLK,
RT5651_SCLK_SRC_MASK, RT5651_SCLK_SRC_MCLK);
return 0;
}
switch (source) {
case RT5651_PLL1_S_MCLK:
snd_soc_component_update_bits(component, RT5651_GLB_CLK,
RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_MCLK);
break;
case RT5651_PLL1_S_BCLK1:
snd_soc_component_update_bits(component, RT5651_GLB_CLK,
RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_BCLK1);
break;
case RT5651_PLL1_S_BCLK2:
snd_soc_component_update_bits(component, RT5651_GLB_CLK,
RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_BCLK2);
break;
default:
dev_err(component->dev, "Unknown PLL source %d\n", source);
return -EINVAL;
}
ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
if (ret < 0) {
dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
return ret;
}
dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
pll_code.n_code, pll_code.k_code);
snd_soc_component_write(component, RT5651_PLL_CTRL1,
pll_code.n_code << RT5651_PLL_N_SFT | pll_code.k_code);
snd_soc_component_write(component, RT5651_PLL_CTRL2,
((pll_code.m_bp ? 0 : pll_code.m_code) << RT5651_PLL_M_SFT) |
(pll_code.m_bp << RT5651_PLL_M_BP_SFT));
rt5651->pll_in = freq_in;
rt5651->pll_out = freq_out;
rt5651->pll_src = source;
return 0;
}
static int rt5651_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
switch (level) {
case SND_SOC_BIAS_PREPARE:
if (SND_SOC_BIAS_STANDBY == snd_soc_component_get_bias_level(component)) {
if (snd_soc_component_read(component, RT5651_PLL_MODE_1) & 0x9200)
snd_soc_component_update_bits(component, RT5651_D_MISC,
0xc00, 0xc00);
}
break;
case SND_SOC_BIAS_STANDBY:
if (SND_SOC_BIAS_OFF == snd_soc_component_get_bias_level(component)) {
snd_soc_component_update_bits(component, RT5651_PWR_ANLG1,
RT5651_PWR_VREF1 | RT5651_PWR_MB |
RT5651_PWR_BG | RT5651_PWR_VREF2,
RT5651_PWR_VREF1 | RT5651_PWR_MB |
RT5651_PWR_BG | RT5651_PWR_VREF2);
usleep_range(10000, 15000);
snd_soc_component_update_bits(component, RT5651_PWR_ANLG1,
RT5651_PWR_FV1 | RT5651_PWR_FV2,
RT5651_PWR_FV1 | RT5651_PWR_FV2);
snd_soc_component_update_bits(component, RT5651_D_MISC, 0x1, 0x1);
}
break;
case SND_SOC_BIAS_OFF:
snd_soc_component_write(component, RT5651_D_MISC, 0x0010);
snd_soc_component_write(component, RT5651_PWR_DIG1, 0x0000);
snd_soc_component_write(component, RT5651_PWR_DIG2, 0x0000);
snd_soc_component_write(component, RT5651_PWR_VOL, 0x0000);
snd_soc_component_write(component, RT5651_PWR_MIXER, 0x0000);
/* Do not touch the LDO voltage select bits on bias-off */
snd_soc_component_update_bits(component, RT5651_PWR_ANLG1,
~RT5651_PWR_LDO_DVO_MASK, 0);
/* Leave PLL1 and jack-detect power as is, all others off */
snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
~(RT5651_PWR_PLL | RT5651_PWR_JD_M), 0);
break;
default:
break;
}
return 0;
}
static void rt5651_enable_micbias1_for_ovcd(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
snd_soc_dapm_mutex_lock(dapm);
snd_soc_dapm_force_enable_pin_unlocked(dapm, "LDO");
snd_soc_dapm_force_enable_pin_unlocked(dapm, "micbias1");
/* OVCD is unreliable when used with RCCLK as sysclk-source */
snd_soc_dapm_force_enable_pin_unlocked(dapm, "Platform Clock");
snd_soc_dapm_sync_unlocked(dapm);
snd_soc_dapm_mutex_unlock(dapm);
}
static void rt5651_disable_micbias1_for_ovcd(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
snd_soc_dapm_mutex_lock(dapm);
snd_soc_dapm_disable_pin_unlocked(dapm, "Platform Clock");
snd_soc_dapm_disable_pin_unlocked(dapm, "micbias1");
snd_soc_dapm_disable_pin_unlocked(dapm, "LDO");
snd_soc_dapm_sync_unlocked(dapm);
snd_soc_dapm_mutex_unlock(dapm);
}
static void rt5651_enable_micbias1_ovcd_irq(struct snd_soc_component *component)
{
struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
snd_soc_component_update_bits(component, RT5651_IRQ_CTRL2,
RT5651_IRQ_MB1_OC_MASK, RT5651_IRQ_MB1_OC_NOR);
rt5651->ovcd_irq_enabled = true;
}
static void rt5651_disable_micbias1_ovcd_irq(struct snd_soc_component *component)
{
struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
snd_soc_component_update_bits(component, RT5651_IRQ_CTRL2,
RT5651_IRQ_MB1_OC_MASK, RT5651_IRQ_MB1_OC_BP);
rt5651->ovcd_irq_enabled = false;
}
static void rt5651_clear_micbias1_ovcd(struct snd_soc_component *component)
{
snd_soc_component_update_bits(component, RT5651_IRQ_CTRL2,
RT5651_MB1_OC_CLR, 0);
}
static bool rt5651_micbias1_ovcd(struct snd_soc_component *component)
{
int val;
val = snd_soc_component_read(component, RT5651_IRQ_CTRL2);
dev_dbg(component->dev, "irq ctrl2 %#04x\n", val);
return (val & RT5651_MB1_OC_CLR);
}
static bool rt5651_jack_inserted(struct snd_soc_component *component)
{
struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
int val;
if (rt5651->gpiod_hp_det) {
val = gpiod_get_value_cansleep(rt5651->gpiod_hp_det);
dev_dbg(component->dev, "jack-detect gpio %d\n", val);
return val;
}
val = snd_soc_component_read(component, RT5651_INT_IRQ_ST);
dev_dbg(component->dev, "irq status %#04x\n", val);
switch (rt5651->jd_src) {
case RT5651_JD1_1:
val &= 0x1000;
break;
case RT5651_JD1_2:
val &= 0x2000;
break;
case RT5651_JD2:
val &= 0x4000;
break;
default:
break;
}
if (rt5651->jd_active_high)
return val != 0;
else
return val == 0;
}
/* Jack detect and button-press timings */
#define JACK_SETTLE_TIME 100 /* milli seconds */
#define JACK_DETECT_COUNT 5
#define JACK_DETECT_MAXCOUNT 20 /* Aprox. 2 seconds worth of tries */
#define JACK_UNPLUG_TIME 80 /* milli seconds */
#define BP_POLL_TIME 10 /* milli seconds */
#define BP_POLL_MAXCOUNT 200 /* assume something is wrong after this */
#define BP_THRESHOLD 3
static void rt5651_start_button_press_work(struct snd_soc_component *component)
{
struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
rt5651->poll_count = 0;
rt5651->press_count = 0;
rt5651->release_count = 0;
rt5651->pressed = false;
rt5651->press_reported = false;
rt5651_clear_micbias1_ovcd(component);
schedule_delayed_work(&rt5651->bp_work, msecs_to_jiffies(BP_POLL_TIME));
}
static void rt5651_button_press_work(struct work_struct *work)
{
struct rt5651_priv *rt5651 =
container_of(work, struct rt5651_priv, bp_work.work);
struct snd_soc_component *component = rt5651->component;
/* Check the jack was not removed underneath us */
if (!rt5651_jack_inserted(component))
return;
if (rt5651_micbias1_ovcd(component)) {
rt5651->release_count = 0;
rt5651->press_count++;
/* Remember till after JACK_UNPLUG_TIME wait */
if (rt5651->press_count >= BP_THRESHOLD)
rt5651->pressed = true;
rt5651_clear_micbias1_ovcd(component);
} else {
rt5651->press_count = 0;
rt5651->release_count++;
}
/*
* The pins get temporarily shorted on jack unplug, so we poll for
* at least JACK_UNPLUG_TIME milli-seconds before reporting a press.
*/
rt5651->poll_count++;
if (rt5651->poll_count < (JACK_UNPLUG_TIME / BP_POLL_TIME)) {
schedule_delayed_work(&rt5651->bp_work,
msecs_to_jiffies(BP_POLL_TIME));
return;
}
if (rt5651->pressed && !rt5651->press_reported) {
dev_dbg(component->dev, "headset button press\n");
snd_soc_jack_report(rt5651->hp_jack, SND_JACK_BTN_0,
SND_JACK_BTN_0);
rt5651->press_reported = true;
}
if (rt5651->release_count >= BP_THRESHOLD) {
if (rt5651->press_reported) {
dev_dbg(component->dev, "headset button release\n");
snd_soc_jack_report(rt5651->hp_jack, 0, SND_JACK_BTN_0);
}
/* Re-enable OVCD IRQ to detect next press */
rt5651_enable_micbias1_ovcd_irq(component);
return; /* Stop polling */
}
schedule_delayed_work(&rt5651->bp_work, msecs_to_jiffies(BP_POLL_TIME));
}
static int rt5651_detect_headset(struct snd_soc_component *component)
{
int i, headset_count = 0, headphone_count = 0;
/*
* We get the insertion event before the jack is fully inserted at which
* point the second ring on a TRRS connector may short the 2nd ring and
* sleeve contacts, also the overcurrent detection is not entirely
* reliable. So we try several times with a wait in between until we
* detect the same type JACK_DETECT_COUNT times in a row.
*/
for (i = 0; i < JACK_DETECT_MAXCOUNT; i++) {
/* Clear any previous over-current status flag */
rt5651_clear_micbias1_ovcd(component);
msleep(JACK_SETTLE_TIME);
/* Check the jack is still connected before checking ovcd */
if (!rt5651_jack_inserted(component))
return 0;
if (rt5651_micbias1_ovcd(component)) {
/*
* Over current detected, there is a short between the
* 2nd ring contact and the ground, so a TRS connector
* without a mic contact and thus plain headphones.
*/
dev_dbg(component->dev, "mic-gnd shorted\n");
headset_count = 0;
headphone_count++;
if (headphone_count == JACK_DETECT_COUNT)
return SND_JACK_HEADPHONE;
} else {
dev_dbg(component->dev, "mic-gnd open\n");
headphone_count = 0;
headset_count++;
if (headset_count == JACK_DETECT_COUNT)
return SND_JACK_HEADSET;
}
}
dev_err(component->dev, "Error detecting headset vs headphones, bad contact?, assuming headphones\n");
return SND_JACK_HEADPHONE;
}
static bool rt5651_support_button_press(struct rt5651_priv *rt5651)
{
if (!rt5651->hp_jack)
return false;
/* Button press support only works with internal jack-detection */
return (rt5651->hp_jack->status & SND_JACK_MICROPHONE) &&
rt5651->gpiod_hp_det == NULL;
}
static void rt5651_jack_detect_work(struct work_struct *work)
{
struct rt5651_priv *rt5651 =
container_of(work, struct rt5651_priv, jack_detect_work);
struct snd_soc_component *component = rt5651->component;
int report;
if (!rt5651_jack_inserted(component)) {
/* Jack removed, or spurious IRQ? */
if (rt5651->hp_jack->status & SND_JACK_HEADPHONE) {
if (rt5651->hp_jack->status & SND_JACK_MICROPHONE) {
cancel_delayed_work_sync(&rt5651->bp_work);
rt5651_disable_micbias1_ovcd_irq(component);
rt5651_disable_micbias1_for_ovcd(component);
}
snd_soc_jack_report(rt5651->hp_jack, 0,
SND_JACK_HEADSET | SND_JACK_BTN_0);
dev_dbg(component->dev, "jack unplugged\n");
}
} else if (!(rt5651->hp_jack->status & SND_JACK_HEADPHONE)) {
/* Jack inserted */
WARN_ON(rt5651->ovcd_irq_enabled);
rt5651_enable_micbias1_for_ovcd(component);
report = rt5651_detect_headset(component);
dev_dbg(component->dev, "detect report %#02x\n", report);
snd_soc_jack_report(rt5651->hp_jack, report, SND_JACK_HEADSET);
if (rt5651_support_button_press(rt5651)) {
/* Enable ovcd IRQ for button press detect. */
rt5651_enable_micbias1_ovcd_irq(component);
} else {
/* No more need for overcurrent detect. */
rt5651_disable_micbias1_for_ovcd(component);
}
} else if (rt5651->ovcd_irq_enabled && rt5651_micbias1_ovcd(component)) {
dev_dbg(component->dev, "OVCD IRQ\n");
/*
* The ovcd IRQ keeps firing while the button is pressed, so
* we disable it and start polling the button until released.
*
* The disable will make the IRQ pin 0 again and since we get
* IRQs on both edges (so as to detect both jack plugin and
* unplug) this means we will immediately get another IRQ.
* The ovcd_irq_enabled check above makes the 2ND IRQ a NOP.
*/
rt5651_disable_micbias1_ovcd_irq(component);
rt5651_start_button_press_work(component);
/*
* If the jack-detect IRQ flag goes high (unplug) after our
* above rt5651_jack_inserted() check and before we have
* disabled the OVCD IRQ, the IRQ pin will stay high and as
* we react to edges, we miss the unplug event -> recheck.
*/
queue_work(system_long_wq, &rt5651->jack_detect_work);
}
}
static irqreturn_t rt5651_irq(int irq, void *data)
{
struct rt5651_priv *rt5651 = data;
queue_work(system_power_efficient_wq, &rt5651->jack_detect_work);
return IRQ_HANDLED;
}
static void rt5651_cancel_work(void *data)
{
struct rt5651_priv *rt5651 = data;
cancel_work_sync(&rt5651->jack_detect_work);
cancel_delayed_work_sync(&rt5651->bp_work);
}
static void rt5651_enable_jack_detect(struct snd_soc_component *component,
struct snd_soc_jack *hp_jack,
struct gpio_desc *gpiod_hp_det)
{
struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
bool using_internal_jack_detect = true;
/* Select jack detect source */
switch (rt5651->jd_src) {
case RT5651_JD_NULL:
rt5651->gpiod_hp_det = gpiod_hp_det;
if (!rt5651->gpiod_hp_det)
return; /* No jack detect */
using_internal_jack_detect = false;
break;
case RT5651_JD1_1:
snd_soc_component_update_bits(component, RT5651_JD_CTRL2,
RT5651_JD_TRG_SEL_MASK, RT5651_JD_TRG_SEL_JD1_1);
/* active-low is normal, set inv flag for active-high */
if (rt5651->jd_active_high)
snd_soc_component_update_bits(component,
RT5651_IRQ_CTRL1,
RT5651_JD1_1_IRQ_EN | RT5651_JD1_1_INV,
RT5651_JD1_1_IRQ_EN | RT5651_JD1_1_INV);
else
snd_soc_component_update_bits(component,
RT5651_IRQ_CTRL1,
RT5651_JD1_1_IRQ_EN | RT5651_JD1_1_INV,
RT5651_JD1_1_IRQ_EN);
break;
case RT5651_JD1_2:
snd_soc_component_update_bits(component, RT5651_JD_CTRL2,
RT5651_JD_TRG_SEL_MASK, RT5651_JD_TRG_SEL_JD1_2);
/* active-low is normal, set inv flag for active-high */
if (rt5651->jd_active_high)
snd_soc_component_update_bits(component,
RT5651_IRQ_CTRL1,
RT5651_JD1_2_IRQ_EN | RT5651_JD1_2_INV,
RT5651_JD1_2_IRQ_EN | RT5651_JD1_2_INV);
else
snd_soc_component_update_bits(component,
RT5651_IRQ_CTRL1,
RT5651_JD1_2_IRQ_EN | RT5651_JD1_2_INV,
RT5651_JD1_2_IRQ_EN);
break;
case RT5651_JD2:
snd_soc_component_update_bits(component, RT5651_JD_CTRL2,
RT5651_JD_TRG_SEL_MASK, RT5651_JD_TRG_SEL_JD2);
/* active-low is normal, set inv flag for active-high */
if (rt5651->jd_active_high)
snd_soc_component_update_bits(component,
RT5651_IRQ_CTRL1,
RT5651_JD2_IRQ_EN | RT5651_JD2_INV,
RT5651_JD2_IRQ_EN | RT5651_JD2_INV);
else
snd_soc_component_update_bits(component,
RT5651_IRQ_CTRL1,
RT5651_JD2_IRQ_EN | RT5651_JD2_INV,
RT5651_JD2_IRQ_EN);
break;
default:
dev_err(component->dev, "Currently only JD1_1 / JD1_2 / JD2 are supported\n");
return;
}
if (using_internal_jack_detect) {
/* IRQ output on GPIO1 */
snd_soc_component_update_bits(component, RT5651_GPIO_CTRL1,
RT5651_GP1_PIN_MASK, RT5651_GP1_PIN_IRQ);
/* Enable jack detect power */
snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
RT5651_PWR_JD_M, RT5651_PWR_JD_M);
}
/* Set OVCD threshold current and scale-factor */
snd_soc_component_write(component, RT5651_PR_BASE + RT5651_BIAS_CUR4,
0xa800 | rt5651->ovcd_sf);
snd_soc_component_update_bits(component, RT5651_MICBIAS,
RT5651_MIC1_OVCD_MASK |
RT5651_MIC1_OVTH_MASK |
RT5651_PWR_CLK12M_MASK |
RT5651_PWR_MB_MASK,
RT5651_MIC1_OVCD_EN |
rt5651->ovcd_th |
RT5651_PWR_MB_PU |
RT5651_PWR_CLK12M_PU);
/*
* The over-current-detect is only reliable in detecting the absence
* of over-current, when the mic-contact in the jack is short-circuited,
* the hardware periodically retries if it can apply the bias-current
* leading to the ovcd status flip-flopping 1-0-1 with it being 0 about
* 10% of the time, as we poll the ovcd status bit we might hit that
* 10%, so we enable sticky mode and when checking OVCD we clear the
* status, msleep() a bit and then check to get a reliable reading.
*/
snd_soc_component_update_bits(component, RT5651_IRQ_CTRL2,
RT5651_MB1_OC_STKY_MASK, RT5651_MB1_OC_STKY_EN);
rt5651->hp_jack = hp_jack;
if (rt5651_support_button_press(rt5651)) {
rt5651_enable_micbias1_for_ovcd(component);
rt5651_enable_micbias1_ovcd_irq(component);
}
enable_irq(rt5651->irq);
/* sync initial jack state */
queue_work(system_power_efficient_wq, &rt5651->jack_detect_work);
}
static void rt5651_disable_jack_detect(struct snd_soc_component *component)
{
struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
disable_irq(rt5651->irq);
rt5651_cancel_work(rt5651);
if (rt5651_support_button_press(rt5651)) {
rt5651_disable_micbias1_ovcd_irq(component);
rt5651_disable_micbias1_for_ovcd(component);
snd_soc_jack_report(rt5651->hp_jack, 0, SND_JACK_BTN_0);
}
rt5651->hp_jack = NULL;
}
static int rt5651_set_jack(struct snd_soc_component *component,
struct snd_soc_jack *jack, void *data)
{
if (jack)
rt5651_enable_jack_detect(component, jack, data);
else
rt5651_disable_jack_detect(component);
return 0;
}
/*
* Note on some platforms the platform code may need to add device-properties,
* rather then relying only on properties set by the firmware. Therefor the
* property parsing MUST be done from the component driver's probe function,
* rather then from the i2c driver's probe function, so that the platform-code
* can attach extra properties before calling snd_soc_register_card().
*/
static void rt5651_apply_properties(struct snd_soc_component *component)
{
struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
u32 val;
if (device_property_read_bool(component->dev, "realtek,in2-differential"))
snd_soc_component_update_bits(component, RT5651_IN1_IN2,
RT5651_IN_DF2, RT5651_IN_DF2);
if (device_property_read_bool(component->dev, "realtek,dmic-en"))
snd_soc_component_update_bits(component, RT5651_GPIO_CTRL1,
RT5651_GP2_PIN_MASK, RT5651_GP2_PIN_DMIC1_SCL);
if (device_property_read_u32(component->dev,
"realtek,jack-detect-source", &val) == 0)
rt5651->jd_src = val;
if (device_property_read_bool(component->dev, "realtek,jack-detect-not-inverted"))
rt5651->jd_active_high = true;
/*
* Testing on various boards has shown that good defaults for the OVCD
* threshold and scale-factor are 2000µA and 0.75. For an effective
* limit of 1500µA, this seems to be more reliable then 1500µA and 1.0.
*/
rt5651->ovcd_th = RT5651_MIC1_OVTH_2000UA;
rt5651->ovcd_sf = RT5651_MIC_OVCD_SF_0P75;
if (device_property_read_u32(component->dev,
"realtek,over-current-threshold-microamp", &val) == 0) {
switch (val) {
case 600:
rt5651->ovcd_th = RT5651_MIC1_OVTH_600UA;
break;
case 1500:
rt5651->ovcd_th = RT5651_MIC1_OVTH_1500UA;
break;
case 2000:
rt5651->ovcd_th = RT5651_MIC1_OVTH_2000UA;
break;
default:
dev_warn(component->dev, "Warning: Invalid over-current-threshold-microamp value: %d, defaulting to 2000uA\n",
val);
}
}
if (device_property_read_u32(component->dev,
"realtek,over-current-scale-factor", &val) == 0) {
if (val <= RT5651_OVCD_SF_1P5)
rt5651->ovcd_sf = val << RT5651_MIC_OVCD_SF_SFT;
else
dev_warn(component->dev, "Warning: Invalid over-current-scale-factor value: %d, defaulting to 0.75\n",
val);
}
}
static int rt5651_probe(struct snd_soc_component *component)
{
struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
rt5651->component = component;
snd_soc_component_update_bits(component, RT5651_PWR_ANLG1,
RT5651_PWR_LDO_DVO_MASK, RT5651_PWR_LDO_DVO_1_2V);
snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
rt5651_apply_properties(component);
return 0;
}
#ifdef CONFIG_PM
static int rt5651_suspend(struct snd_soc_component *component)
{
struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
regcache_cache_only(rt5651->regmap, true);
regcache_mark_dirty(rt5651->regmap);
return 0;
}
static int rt5651_resume(struct snd_soc_component *component)
{
struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
regcache_cache_only(rt5651->regmap, false);
snd_soc_component_cache_sync(component);
return 0;
}
#else
#define rt5651_suspend NULL
#define rt5651_resume NULL
#endif
#define RT5651_STEREO_RATES SNDRV_PCM_RATE_8000_96000
#define RT5651_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
static const struct snd_soc_dai_ops rt5651_aif_dai_ops = {
.hw_params = rt5651_hw_params,
.set_fmt = rt5651_set_dai_fmt,
.set_sysclk = rt5651_set_dai_sysclk,
.set_pll = rt5651_set_dai_pll,
};
static struct snd_soc_dai_driver rt5651_dai[] = {
{
.name = "rt5651-aif1",
.id = RT5651_AIF1,
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT5651_STEREO_RATES,
.formats = RT5651_FORMATS,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT5651_STEREO_RATES,
.formats = RT5651_FORMATS,
},
.ops = &rt5651_aif_dai_ops,
},
{
.name = "rt5651-aif2",
.id = RT5651_AIF2,
.playback = {
.stream_name = "AIF2 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT5651_STEREO_RATES,
.formats = RT5651_FORMATS,
},
.capture = {
.stream_name = "AIF2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT5651_STEREO_RATES,
.formats = RT5651_FORMATS,
},
.ops = &rt5651_aif_dai_ops,
},
};
static const struct snd_soc_component_driver soc_component_dev_rt5651 = {
.probe = rt5651_probe,
.suspend = rt5651_suspend,
.resume = rt5651_resume,
.set_bias_level = rt5651_set_bias_level,
.set_jack = rt5651_set_jack,
.controls = rt5651_snd_controls,
.num_controls = ARRAY_SIZE(rt5651_snd_controls),
.dapm_widgets = rt5651_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt5651_dapm_widgets),
.dapm_routes = rt5651_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(rt5651_dapm_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config rt5651_regmap = {
.reg_bits = 8,
.val_bits = 16,
.max_register = RT5651_DEVICE_ID + 1 + (ARRAY_SIZE(rt5651_ranges) *
RT5651_PR_SPACING),
.volatile_reg = rt5651_volatile_register,
.readable_reg = rt5651_readable_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = rt5651_reg,
.num_reg_defaults = ARRAY_SIZE(rt5651_reg),
.ranges = rt5651_ranges,
.num_ranges = ARRAY_SIZE(rt5651_ranges),
.use_single_read = true,
.use_single_write = true,
};
#if defined(CONFIG_OF)
static const struct of_device_id rt5651_of_match[] = {
{ .compatible = "realtek,rt5651", },
{},
};
MODULE_DEVICE_TABLE(of, rt5651_of_match);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id rt5651_acpi_match[] = {
{ "10EC5651", 0 },
{ "10EC5640", 0 },
{ },
};
MODULE_DEVICE_TABLE(acpi, rt5651_acpi_match);
#endif
static const struct i2c_device_id rt5651_i2c_id[] = {
{ "rt5651", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, rt5651_i2c_id);
/*
* Note this function MUST not look at device-properties, see the comment
* above rt5651_apply_properties().
*/
static int rt5651_i2c_probe(struct i2c_client *i2c)
{
struct rt5651_priv *rt5651;
int ret;
int err;
rt5651 = devm_kzalloc(&i2c->dev, sizeof(*rt5651),
GFP_KERNEL);
if (NULL == rt5651)
return -ENOMEM;
i2c_set_clientdata(i2c, rt5651);
rt5651->regmap = devm_regmap_init_i2c(i2c, &rt5651_regmap);
if (IS_ERR(rt5651->regmap)) {
ret = PTR_ERR(rt5651->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
err = regmap_read(rt5651->regmap, RT5651_DEVICE_ID, &ret);
if (err)
return err;
if (ret != RT5651_DEVICE_ID_VALUE) {
dev_err(&i2c->dev,
"Device with ID register %#x is not rt5651\n", ret);
return -ENODEV;
}
regmap_write(rt5651->regmap, RT5651_RESET, 0);
ret = regmap_register_patch(rt5651->regmap, init_list,
ARRAY_SIZE(init_list));
if (ret != 0)
dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
rt5651->irq = i2c->irq;
rt5651->hp_mute = true;
INIT_DELAYED_WORK(&rt5651->bp_work, rt5651_button_press_work);
INIT_WORK(&rt5651->jack_detect_work, rt5651_jack_detect_work);
/* Make sure work is stopped on probe-error / remove */
ret = devm_add_action_or_reset(&i2c->dev, rt5651_cancel_work, rt5651);
if (ret)
return ret;
ret = devm_request_irq(&i2c->dev, rt5651->irq, rt5651_irq,
IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
| IRQF_ONESHOT | IRQF_NO_AUTOEN, "rt5651", rt5651);
if (ret) {
dev_warn(&i2c->dev, "Failed to reguest IRQ %d: %d\n",
rt5651->irq, ret);
rt5651->irq = -ENXIO;
}
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_rt5651,
rt5651_dai, ARRAY_SIZE(rt5651_dai));
return ret;
}
static struct i2c_driver rt5651_i2c_driver = {
.driver = {
.name = "rt5651",
.acpi_match_table = ACPI_PTR(rt5651_acpi_match),
.of_match_table = of_match_ptr(rt5651_of_match),
},
.probe = rt5651_i2c_probe,
.id_table = rt5651_i2c_id,
};
module_i2c_driver(rt5651_i2c_driver);
MODULE_DESCRIPTION("ASoC RT5651 driver");
MODULE_AUTHOR("Bard Liao <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/rt5651.c |
// SPDX-License-Identifier: GPL-2.0
//
// Driver for the Texas Instruments TAS2764 CODEC
// Copyright (C) 2020 Texas Instruments Inc.
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/regulator/consumer.h>
#include <linux/regmap.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/slab.h>
#include <sound/soc.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "tas2764.h"
struct tas2764_priv {
struct snd_soc_component *component;
struct gpio_desc *reset_gpio;
struct gpio_desc *sdz_gpio;
struct regmap *regmap;
struct device *dev;
int irq;
int v_sense_slot;
int i_sense_slot;
bool dac_powered;
bool unmuted;
};
static const char *tas2764_int_ltch0_msgs[8] = {
"fault: over temperature", /* INT_LTCH0 & BIT(0) */
"fault: over current",
"fault: bad TDM clock",
"limiter active",
"fault: PVDD below limiter inflection point",
"fault: limiter max attenuation",
"fault: BOP infinite hold",
"fault: BOP mute", /* INT_LTCH0 & BIT(7) */
};
static const unsigned int tas2764_int_readout_regs[6] = {
TAS2764_INT_LTCH0,
TAS2764_INT_LTCH1,
TAS2764_INT_LTCH1_0,
TAS2764_INT_LTCH2,
TAS2764_INT_LTCH3,
TAS2764_INT_LTCH4,
};
static irqreturn_t tas2764_irq(int irq, void *data)
{
struct tas2764_priv *tas2764 = data;
u8 latched[6] = {0, 0, 0, 0, 0, 0};
int ret = IRQ_NONE;
int i;
for (i = 0; i < ARRAY_SIZE(latched); i++)
latched[i] = snd_soc_component_read(tas2764->component,
tas2764_int_readout_regs[i]);
for (i = 0; i < 8; i++) {
if (latched[0] & BIT(i)) {
dev_crit_ratelimited(tas2764->dev, "%s\n",
tas2764_int_ltch0_msgs[i]);
ret = IRQ_HANDLED;
}
}
if (latched[0]) {
dev_err_ratelimited(tas2764->dev, "other context to the fault: %02x,%02x,%02x,%02x,%02x",
latched[1], latched[2], latched[3], latched[4], latched[5]);
snd_soc_component_update_bits(tas2764->component,
TAS2764_INT_CLK_CFG,
TAS2764_INT_CLK_CFG_IRQZ_CLR,
TAS2764_INT_CLK_CFG_IRQZ_CLR);
}
return ret;
}
static void tas2764_reset(struct tas2764_priv *tas2764)
{
if (tas2764->reset_gpio) {
gpiod_set_value_cansleep(tas2764->reset_gpio, 0);
msleep(20);
gpiod_set_value_cansleep(tas2764->reset_gpio, 1);
usleep_range(1000, 2000);
}
snd_soc_component_write(tas2764->component, TAS2764_SW_RST,
TAS2764_RST);
usleep_range(1000, 2000);
}
static int tas2764_update_pwr_ctrl(struct tas2764_priv *tas2764)
{
struct snd_soc_component *component = tas2764->component;
unsigned int val;
int ret;
if (tas2764->dac_powered)
val = tas2764->unmuted ?
TAS2764_PWR_CTRL_ACTIVE : TAS2764_PWR_CTRL_MUTE;
else
val = TAS2764_PWR_CTRL_SHUTDOWN;
ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
TAS2764_PWR_CTRL_MASK, val);
if (ret < 0)
return ret;
return 0;
}
#ifdef CONFIG_PM
static int tas2764_codec_suspend(struct snd_soc_component *component)
{
struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component);
int ret;
ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
TAS2764_PWR_CTRL_MASK,
TAS2764_PWR_CTRL_SHUTDOWN);
if (ret < 0)
return ret;
if (tas2764->sdz_gpio)
gpiod_set_value_cansleep(tas2764->sdz_gpio, 0);
regcache_cache_only(tas2764->regmap, true);
regcache_mark_dirty(tas2764->regmap);
return 0;
}
static int tas2764_codec_resume(struct snd_soc_component *component)
{
struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component);
int ret;
if (tas2764->sdz_gpio) {
gpiod_set_value_cansleep(tas2764->sdz_gpio, 1);
usleep_range(1000, 2000);
}
ret = tas2764_update_pwr_ctrl(tas2764);
if (ret < 0)
return ret;
regcache_cache_only(tas2764->regmap, false);
return regcache_sync(tas2764->regmap);
}
#else
#define tas2764_codec_suspend NULL
#define tas2764_codec_resume NULL
#endif
static const char * const tas2764_ASI1_src[] = {
"I2C offset", "Left", "Right", "LeftRightDiv2",
};
static SOC_ENUM_SINGLE_DECL(
tas2764_ASI1_src_enum, TAS2764_TDM_CFG2, TAS2764_TDM_CFG2_SCFG_SHIFT,
tas2764_ASI1_src);
static const struct snd_kcontrol_new tas2764_asi1_mux =
SOC_DAPM_ENUM("ASI1 Source", tas2764_ASI1_src_enum);
static int tas2764_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component);
int ret;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
tas2764->dac_powered = true;
ret = tas2764_update_pwr_ctrl(tas2764);
break;
case SND_SOC_DAPM_PRE_PMD:
tas2764->dac_powered = false;
ret = tas2764_update_pwr_ctrl(tas2764);
break;
default:
dev_err(tas2764->dev, "Unsupported event\n");
return -EINVAL;
}
if (ret < 0)
return ret;
return 0;
}
static const struct snd_kcontrol_new isense_switch =
SOC_DAPM_SINGLE("Switch", TAS2764_PWR_CTRL, TAS2764_ISENSE_POWER_EN, 1, 1);
static const struct snd_kcontrol_new vsense_switch =
SOC_DAPM_SINGLE("Switch", TAS2764_PWR_CTRL, TAS2764_VSENSE_POWER_EN, 1, 1);
static const struct snd_soc_dapm_widget tas2764_dapm_widgets[] = {
SND_SOC_DAPM_AIF_IN("ASI1", "ASI1 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_MUX("ASI1 Sel", SND_SOC_NOPM, 0, 0, &tas2764_asi1_mux),
SND_SOC_DAPM_SWITCH("ISENSE", TAS2764_PWR_CTRL, TAS2764_ISENSE_POWER_EN,
1, &isense_switch),
SND_SOC_DAPM_SWITCH("VSENSE", TAS2764_PWR_CTRL, TAS2764_VSENSE_POWER_EN,
1, &vsense_switch),
SND_SOC_DAPM_DAC_E("DAC", NULL, SND_SOC_NOPM, 0, 0, tas2764_dac_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_OUTPUT("OUT"),
SND_SOC_DAPM_SIGGEN("VMON"),
SND_SOC_DAPM_SIGGEN("IMON")
};
static const struct snd_soc_dapm_route tas2764_audio_map[] = {
{"ASI1 Sel", "I2C offset", "ASI1"},
{"ASI1 Sel", "Left", "ASI1"},
{"ASI1 Sel", "Right", "ASI1"},
{"ASI1 Sel", "LeftRightDiv2", "ASI1"},
{"DAC", NULL, "ASI1 Sel"},
{"OUT", NULL, "DAC"},
{"ISENSE", "Switch", "IMON"},
{"VSENSE", "Switch", "VMON"},
};
static int tas2764_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct tas2764_priv *tas2764 =
snd_soc_component_get_drvdata(dai->component);
tas2764->unmuted = !mute;
return tas2764_update_pwr_ctrl(tas2764);
}
static int tas2764_set_bitwidth(struct tas2764_priv *tas2764, int bitwidth)
{
struct snd_soc_component *component = tas2764->component;
int sense_en;
int val;
int ret;
switch (bitwidth) {
case SNDRV_PCM_FORMAT_S16_LE:
ret = snd_soc_component_update_bits(component,
TAS2764_TDM_CFG2,
TAS2764_TDM_CFG2_RXW_MASK,
TAS2764_TDM_CFG2_RXW_16BITS);
break;
case SNDRV_PCM_FORMAT_S24_LE:
ret = snd_soc_component_update_bits(component,
TAS2764_TDM_CFG2,
TAS2764_TDM_CFG2_RXW_MASK,
TAS2764_TDM_CFG2_RXW_24BITS);
break;
case SNDRV_PCM_FORMAT_S32_LE:
ret = snd_soc_component_update_bits(component,
TAS2764_TDM_CFG2,
TAS2764_TDM_CFG2_RXW_MASK,
TAS2764_TDM_CFG2_RXW_32BITS);
break;
default:
return -EINVAL;
}
if (ret < 0)
return ret;
val = snd_soc_component_read(tas2764->component, TAS2764_PWR_CTRL);
if (val < 0)
return val;
if (val & (1 << TAS2764_VSENSE_POWER_EN))
sense_en = 0;
else
sense_en = TAS2764_TDM_CFG5_VSNS_ENABLE;
ret = snd_soc_component_update_bits(tas2764->component, TAS2764_TDM_CFG5,
TAS2764_TDM_CFG5_VSNS_ENABLE,
sense_en);
if (ret < 0)
return ret;
if (val & (1 << TAS2764_ISENSE_POWER_EN))
sense_en = 0;
else
sense_en = TAS2764_TDM_CFG6_ISNS_ENABLE;
ret = snd_soc_component_update_bits(tas2764->component, TAS2764_TDM_CFG6,
TAS2764_TDM_CFG6_ISNS_ENABLE,
sense_en);
if (ret < 0)
return ret;
return 0;
}
static int tas2764_set_samplerate(struct tas2764_priv *tas2764, int samplerate)
{
struct snd_soc_component *component = tas2764->component;
int ramp_rate_val;
int ret;
switch (samplerate) {
case 48000:
ramp_rate_val = TAS2764_TDM_CFG0_SMP_48KHZ |
TAS2764_TDM_CFG0_44_1_48KHZ;
break;
case 44100:
ramp_rate_val = TAS2764_TDM_CFG0_SMP_44_1KHZ |
TAS2764_TDM_CFG0_44_1_48KHZ;
break;
case 96000:
ramp_rate_val = TAS2764_TDM_CFG0_SMP_48KHZ |
TAS2764_TDM_CFG0_88_2_96KHZ;
break;
case 88200:
ramp_rate_val = TAS2764_TDM_CFG0_SMP_44_1KHZ |
TAS2764_TDM_CFG0_88_2_96KHZ;
break;
default:
return -EINVAL;
}
ret = snd_soc_component_update_bits(component, TAS2764_TDM_CFG0,
TAS2764_TDM_CFG0_SMP_MASK |
TAS2764_TDM_CFG0_MASK,
ramp_rate_val);
if (ret < 0)
return ret;
return 0;
}
static int tas2764_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component);
int ret;
ret = tas2764_set_bitwidth(tas2764, params_format(params));
if (ret < 0)
return ret;
return tas2764_set_samplerate(tas2764, params_rate(params));
}
static int tas2764_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component);
u8 tdm_rx_start_slot = 0, asi_cfg_0 = 0, asi_cfg_1 = 0;
int ret;
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_IF:
asi_cfg_0 ^= TAS2764_TDM_CFG0_FRAME_START;
fallthrough;
case SND_SOC_DAIFMT_NB_NF:
asi_cfg_1 = TAS2764_TDM_CFG1_RX_RISING;
break;
case SND_SOC_DAIFMT_IB_IF:
asi_cfg_0 ^= TAS2764_TDM_CFG0_FRAME_START;
fallthrough;
case SND_SOC_DAIFMT_IB_NF:
asi_cfg_1 = TAS2764_TDM_CFG1_RX_FALLING;
break;
}
ret = snd_soc_component_update_bits(component, TAS2764_TDM_CFG1,
TAS2764_TDM_CFG1_RX_MASK,
asi_cfg_1);
if (ret < 0)
return ret;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
asi_cfg_0 ^= TAS2764_TDM_CFG0_FRAME_START;
fallthrough;
case SND_SOC_DAIFMT_DSP_A:
tdm_rx_start_slot = 1;
break;
case SND_SOC_DAIFMT_DSP_B:
case SND_SOC_DAIFMT_LEFT_J:
tdm_rx_start_slot = 0;
break;
default:
dev_err(tas2764->dev,
"DAI Format is not found, fmt=0x%x\n", fmt);
return -EINVAL;
}
ret = snd_soc_component_update_bits(component, TAS2764_TDM_CFG0,
TAS2764_TDM_CFG0_FRAME_START,
asi_cfg_0);
if (ret < 0)
return ret;
ret = snd_soc_component_update_bits(component, TAS2764_TDM_CFG1,
TAS2764_TDM_CFG1_MASK,
(tdm_rx_start_slot << TAS2764_TDM_CFG1_51_SHIFT));
if (ret < 0)
return ret;
return 0;
}
static int tas2764_set_dai_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask,
unsigned int rx_mask,
int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component);
int left_slot, right_slot;
int slots_cfg;
int slot_size;
int ret;
if (tx_mask == 0 || rx_mask != 0)
return -EINVAL;
left_slot = __ffs(tx_mask);
tx_mask &= ~(1 << left_slot);
if (tx_mask == 0) {
right_slot = left_slot;
} else {
right_slot = __ffs(tx_mask);
tx_mask &= ~(1 << right_slot);
}
if (tx_mask != 0 || left_slot >= slots || right_slot >= slots)
return -EINVAL;
slots_cfg = (right_slot << TAS2764_TDM_CFG3_RXS_SHIFT) | left_slot;
ret = snd_soc_component_write(component, TAS2764_TDM_CFG3, slots_cfg);
if (ret)
return ret;
switch (slot_width) {
case 16:
slot_size = TAS2764_TDM_CFG2_RXS_16BITS;
break;
case 24:
slot_size = TAS2764_TDM_CFG2_RXS_24BITS;
break;
case 32:
slot_size = TAS2764_TDM_CFG2_RXS_32BITS;
break;
default:
return -EINVAL;
}
ret = snd_soc_component_update_bits(component, TAS2764_TDM_CFG2,
TAS2764_TDM_CFG2_RXS_MASK,
slot_size);
if (ret < 0)
return ret;
ret = snd_soc_component_update_bits(component, TAS2764_TDM_CFG5,
TAS2764_TDM_CFG5_50_MASK,
tas2764->v_sense_slot);
if (ret < 0)
return ret;
ret = snd_soc_component_update_bits(component, TAS2764_TDM_CFG6,
TAS2764_TDM_CFG6_50_MASK,
tas2764->i_sense_slot);
if (ret < 0)
return ret;
return 0;
}
static const struct snd_soc_dai_ops tas2764_dai_ops = {
.mute_stream = tas2764_mute,
.hw_params = tas2764_hw_params,
.set_fmt = tas2764_set_fmt,
.set_tdm_slot = tas2764_set_dai_tdm_slot,
.no_capture_mute = 1,
};
#define TAS2764_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
#define TAS2764_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_88200)
static struct snd_soc_dai_driver tas2764_dai_driver[] = {
{
.name = "tas2764 ASI1",
.id = 0,
.playback = {
.stream_name = "ASI1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = TAS2764_RATES,
.formats = TAS2764_FORMATS,
},
.capture = {
.stream_name = "ASI1 Capture",
.channels_min = 0,
.channels_max = 2,
.rates = TAS2764_RATES,
.formats = TAS2764_FORMATS,
},
.ops = &tas2764_dai_ops,
.symmetric_rate = 1,
},
};
static int tas2764_codec_probe(struct snd_soc_component *component)
{
struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component);
int ret;
tas2764->component = component;
if (tas2764->sdz_gpio) {
gpiod_set_value_cansleep(tas2764->sdz_gpio, 1);
usleep_range(1000, 2000);
}
tas2764_reset(tas2764);
if (tas2764->irq) {
ret = snd_soc_component_write(tas2764->component, TAS2764_INT_MASK0, 0xff);
if (ret < 0)
return ret;
ret = snd_soc_component_write(tas2764->component, TAS2764_INT_MASK1, 0xff);
if (ret < 0)
return ret;
ret = snd_soc_component_write(tas2764->component, TAS2764_INT_MASK2, 0xff);
if (ret < 0)
return ret;
ret = snd_soc_component_write(tas2764->component, TAS2764_INT_MASK3, 0xff);
if (ret < 0)
return ret;
ret = snd_soc_component_write(tas2764->component, TAS2764_INT_MASK4, 0xff);
if (ret < 0)
return ret;
ret = devm_request_threaded_irq(tas2764->dev, tas2764->irq, NULL, tas2764_irq,
IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_LOW,
"tas2764", tas2764);
if (ret)
dev_warn(tas2764->dev, "failed to request IRQ: %d\n", ret);
}
ret = snd_soc_component_update_bits(tas2764->component, TAS2764_TDM_CFG5,
TAS2764_TDM_CFG5_VSNS_ENABLE, 0);
if (ret < 0)
return ret;
ret = snd_soc_component_update_bits(tas2764->component, TAS2764_TDM_CFG6,
TAS2764_TDM_CFG6_ISNS_ENABLE, 0);
if (ret < 0)
return ret;
return 0;
}
static DECLARE_TLV_DB_SCALE(tas2764_digital_tlv, 1100, 50, 0);
static DECLARE_TLV_DB_SCALE(tas2764_playback_volume, -10050, 50, 1);
static const char * const tas2764_hpf_texts[] = {
"Disabled", "2 Hz", "50 Hz", "100 Hz", "200 Hz",
"400 Hz", "800 Hz"
};
static SOC_ENUM_SINGLE_DECL(
tas2764_hpf_enum, TAS2764_DC_BLK0,
TAS2764_DC_BLK0_HPF_FREQ_PB_SHIFT, tas2764_hpf_texts);
static const struct snd_kcontrol_new tas2764_snd_controls[] = {
SOC_SINGLE_TLV("Speaker Volume", TAS2764_DVC, 0,
TAS2764_DVC_MAX, 1, tas2764_playback_volume),
SOC_SINGLE_TLV("Amp Gain Volume", TAS2764_CHNL_0, 1, 0x14, 0,
tas2764_digital_tlv),
SOC_ENUM("HPF Corner Frequency", tas2764_hpf_enum),
};
static const struct snd_soc_component_driver soc_component_driver_tas2764 = {
.probe = tas2764_codec_probe,
.suspend = tas2764_codec_suspend,
.resume = tas2764_codec_resume,
.controls = tas2764_snd_controls,
.num_controls = ARRAY_SIZE(tas2764_snd_controls),
.dapm_widgets = tas2764_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(tas2764_dapm_widgets),
.dapm_routes = tas2764_audio_map,
.num_dapm_routes = ARRAY_SIZE(tas2764_audio_map),
.idle_bias_on = 1,
.endianness = 1,
};
static const struct reg_default tas2764_reg_defaults[] = {
{ TAS2764_PAGE, 0x00 },
{ TAS2764_SW_RST, 0x00 },
{ TAS2764_PWR_CTRL, 0x1a },
{ TAS2764_DVC, 0x00 },
{ TAS2764_CHNL_0, 0x28 },
{ TAS2764_TDM_CFG0, 0x09 },
{ TAS2764_TDM_CFG1, 0x02 },
{ TAS2764_TDM_CFG2, 0x0a },
{ TAS2764_TDM_CFG3, 0x10 },
{ TAS2764_TDM_CFG5, 0x42 },
};
static const struct regmap_range_cfg tas2764_regmap_ranges[] = {
{
.range_min = 0,
.range_max = 1 * 128,
.selector_reg = TAS2764_PAGE,
.selector_mask = 0xff,
.selector_shift = 0,
.window_start = 0,
.window_len = 128,
},
};
static bool tas2764_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case TAS2764_INT_LTCH0 ... TAS2764_INT_LTCH4:
case TAS2764_INT_CLK_CFG:
return true;
default:
return false;
}
}
static const struct regmap_config tas2764_i2c_regmap = {
.reg_bits = 8,
.val_bits = 8,
.volatile_reg = tas2764_volatile_register,
.reg_defaults = tas2764_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tas2764_reg_defaults),
.cache_type = REGCACHE_RBTREE,
.ranges = tas2764_regmap_ranges,
.num_ranges = ARRAY_SIZE(tas2764_regmap_ranges),
.max_register = 1 * 128,
};
static int tas2764_parse_dt(struct device *dev, struct tas2764_priv *tas2764)
{
int ret = 0;
tas2764->reset_gpio = devm_gpiod_get_optional(tas2764->dev, "reset",
GPIOD_OUT_HIGH);
if (IS_ERR(tas2764->reset_gpio)) {
if (PTR_ERR(tas2764->reset_gpio) == -EPROBE_DEFER) {
tas2764->reset_gpio = NULL;
return -EPROBE_DEFER;
}
}
tas2764->sdz_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH);
if (IS_ERR(tas2764->sdz_gpio)) {
if (PTR_ERR(tas2764->sdz_gpio) == -EPROBE_DEFER)
return -EPROBE_DEFER;
tas2764->sdz_gpio = NULL;
}
ret = fwnode_property_read_u32(dev->fwnode, "ti,imon-slot-no",
&tas2764->i_sense_slot);
if (ret)
tas2764->i_sense_slot = 0;
ret = fwnode_property_read_u32(dev->fwnode, "ti,vmon-slot-no",
&tas2764->v_sense_slot);
if (ret)
tas2764->v_sense_slot = 2;
return 0;
}
static int tas2764_i2c_probe(struct i2c_client *client)
{
struct tas2764_priv *tas2764;
int result;
tas2764 = devm_kzalloc(&client->dev, sizeof(struct tas2764_priv),
GFP_KERNEL);
if (!tas2764)
return -ENOMEM;
tas2764->dev = &client->dev;
tas2764->irq = client->irq;
i2c_set_clientdata(client, tas2764);
dev_set_drvdata(&client->dev, tas2764);
tas2764->regmap = devm_regmap_init_i2c(client, &tas2764_i2c_regmap);
if (IS_ERR(tas2764->regmap)) {
result = PTR_ERR(tas2764->regmap);
dev_err(&client->dev, "Failed to allocate register map: %d\n",
result);
return result;
}
if (client->dev.of_node) {
result = tas2764_parse_dt(&client->dev, tas2764);
if (result) {
dev_err(tas2764->dev, "%s: Failed to parse devicetree\n",
__func__);
return result;
}
}
return devm_snd_soc_register_component(tas2764->dev,
&soc_component_driver_tas2764,
tas2764_dai_driver,
ARRAY_SIZE(tas2764_dai_driver));
}
static const struct i2c_device_id tas2764_i2c_id[] = {
{ "tas2764", 0},
{ }
};
MODULE_DEVICE_TABLE(i2c, tas2764_i2c_id);
#if defined(CONFIG_OF)
static const struct of_device_id tas2764_of_match[] = {
{ .compatible = "ti,tas2764" },
{},
};
MODULE_DEVICE_TABLE(of, tas2764_of_match);
#endif
static struct i2c_driver tas2764_i2c_driver = {
.driver = {
.name = "tas2764",
.of_match_table = of_match_ptr(tas2764_of_match),
},
.probe = tas2764_i2c_probe,
.id_table = tas2764_i2c_id,
};
module_i2c_driver(tas2764_i2c_driver);
MODULE_AUTHOR("Dan Murphy <[email protected]>");
MODULE_DESCRIPTION("TAS2764 I2C Smart Amplifier driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/tas2764.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8960.c -- WM8960 ALSA SoC Audio driver
*
* Copyright 2007-11 Wolfson Microelectronics, plc
*
* Author: Liam Girdwood
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/clk.h>
#include <linux/i2c.h>
#include <linux/acpi.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/wm8960.h>
#include "wm8960.h"
/* R25 - Power 1 */
#define WM8960_VMID_MASK 0x180
#define WM8960_VREF 0x40
/* R26 - Power 2 */
#define WM8960_PWR2_LOUT1 0x40
#define WM8960_PWR2_ROUT1 0x20
#define WM8960_PWR2_OUT3 0x02
/* R28 - Anti-pop 1 */
#define WM8960_POBCTRL 0x80
#define WM8960_BUFDCOPEN 0x10
#define WM8960_BUFIOEN 0x08
#define WM8960_SOFT_ST 0x04
#define WM8960_HPSTBY 0x01
/* R29 - Anti-pop 2 */
#define WM8960_DISOP 0x40
#define WM8960_DRES_MASK 0x30
#define WM8960_DSCH_TOUT 600 /* discharge timeout, ms */
static bool is_pll_freq_available(unsigned int source, unsigned int target);
static int wm8960_set_pll(struct snd_soc_component *component,
unsigned int freq_in, unsigned int freq_out);
/*
* wm8960 register cache
* We can't read the WM8960 register space when we are
* using 2 wire for device control, so we cache them instead.
*/
static const struct reg_default wm8960_reg_defaults[] = {
{ 0x0, 0x00a7 },
{ 0x1, 0x00a7 },
{ 0x2, 0x0000 },
{ 0x3, 0x0000 },
{ 0x4, 0x0000 },
{ 0x5, 0x0008 },
{ 0x6, 0x0000 },
{ 0x7, 0x000a },
{ 0x8, 0x01c0 },
{ 0x9, 0x0000 },
{ 0xa, 0x00ff },
{ 0xb, 0x00ff },
{ 0x10, 0x0000 },
{ 0x11, 0x007b },
{ 0x12, 0x0100 },
{ 0x13, 0x0032 },
{ 0x14, 0x0000 },
{ 0x15, 0x00c3 },
{ 0x16, 0x00c3 },
{ 0x17, 0x01c0 },
{ 0x18, 0x0000 },
{ 0x19, 0x0000 },
{ 0x1a, 0x0000 },
{ 0x1b, 0x0000 },
{ 0x1c, 0x0000 },
{ 0x1d, 0x0000 },
{ 0x20, 0x0100 },
{ 0x21, 0x0100 },
{ 0x22, 0x0050 },
{ 0x25, 0x0050 },
{ 0x26, 0x0000 },
{ 0x27, 0x0000 },
{ 0x28, 0x0000 },
{ 0x29, 0x0000 },
{ 0x2a, 0x0040 },
{ 0x2b, 0x0000 },
{ 0x2c, 0x0000 },
{ 0x2d, 0x0050 },
{ 0x2e, 0x0050 },
{ 0x2f, 0x0000 },
{ 0x30, 0x0002 },
{ 0x31, 0x0037 },
{ 0x33, 0x0080 },
{ 0x34, 0x0008 },
{ 0x35, 0x0031 },
{ 0x36, 0x0026 },
{ 0x37, 0x00e9 },
};
static bool wm8960_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8960_RESET:
return true;
default:
return false;
}
}
#define WM8960_NUM_SUPPLIES 5
static const char *wm8960_supply_names[WM8960_NUM_SUPPLIES] = {
"DCVDD",
"DBVDD",
"AVDD",
"SPKVDD1",
"SPKVDD2",
};
struct wm8960_priv {
struct clk *mclk;
struct regmap *regmap;
int (*set_bias_level)(struct snd_soc_component *,
enum snd_soc_bias_level level);
struct snd_soc_dapm_widget *lout1;
struct snd_soc_dapm_widget *rout1;
struct snd_soc_dapm_widget *out3;
bool deemph;
int lrclk;
int bclk;
int sysclk;
int clk_id;
int freq_in;
bool is_stream_in_use[2];
struct wm8960_data pdata;
ktime_t dsch_start;
struct regulator_bulk_data supplies[WM8960_NUM_SUPPLIES];
};
#define wm8960_reset(c) regmap_write(c, WM8960_RESET, 0)
/* enumerated controls */
static const char *wm8960_polarity[] = {"No Inversion", "Left Inverted",
"Right Inverted", "Stereo Inversion"};
static const char *wm8960_3d_upper_cutoff[] = {"High", "Low"};
static const char *wm8960_3d_lower_cutoff[] = {"Low", "High"};
static const char *wm8960_alcfunc[] = {"Off", "Right", "Left", "Stereo"};
static const char *wm8960_alcmode[] = {"ALC", "Limiter"};
static const char *wm8960_adc_data_output_sel[] = {
"Left Data = Left ADC; Right Data = Right ADC",
"Left Data = Left ADC; Right Data = Left ADC",
"Left Data = Right ADC; Right Data = Right ADC",
"Left Data = Right ADC; Right Data = Left ADC",
};
static const char *wm8960_dmonomix[] = {"Stereo", "Mono"};
static const char *wm8960_dacslope[] = {"Normal", "Sloping"};
static const struct soc_enum wm8960_enum[] = {
SOC_ENUM_SINGLE(WM8960_DACCTL1, 5, 4, wm8960_polarity),
SOC_ENUM_SINGLE(WM8960_DACCTL2, 5, 4, wm8960_polarity),
SOC_ENUM_SINGLE(WM8960_3D, 6, 2, wm8960_3d_upper_cutoff),
SOC_ENUM_SINGLE(WM8960_3D, 5, 2, wm8960_3d_lower_cutoff),
SOC_ENUM_SINGLE(WM8960_ALC1, 7, 4, wm8960_alcfunc),
SOC_ENUM_SINGLE(WM8960_ALC3, 8, 2, wm8960_alcmode),
SOC_ENUM_SINGLE(WM8960_ADDCTL1, 2, 4, wm8960_adc_data_output_sel),
SOC_ENUM_SINGLE(WM8960_ADDCTL1, 4, 2, wm8960_dmonomix),
SOC_ENUM_SINGLE(WM8960_DACCTL2, 1, 2, wm8960_dacslope),
};
static const int deemph_settings[] = { 0, 32000, 44100, 48000 };
static int wm8960_set_deemph(struct snd_soc_component *component)
{
struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component);
int val, i, best;
/* If we're using deemphasis select the nearest available sample
* rate.
*/
if (wm8960->deemph) {
best = 1;
for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
if (abs(deemph_settings[i] - wm8960->lrclk) <
abs(deemph_settings[best] - wm8960->lrclk))
best = i;
}
val = best << 1;
} else {
val = 0;
}
dev_dbg(component->dev, "Set deemphasis %d\n", val);
return snd_soc_component_update_bits(component, WM8960_DACCTL1,
0x6, val);
}
static int wm8960_get_deemph(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = wm8960->deemph;
return 0;
}
static int wm8960_put_deemph(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component);
unsigned int deemph = ucontrol->value.integer.value[0];
if (deemph > 1)
return -EINVAL;
wm8960->deemph = deemph;
return wm8960_set_deemph(component);
}
static const DECLARE_TLV_DB_SCALE(adc_tlv, -9750, 50, 1);
static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1725, 75, 0);
static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
static const DECLARE_TLV_DB_SCALE(bypass_tlv, -2100, 300, 0);
static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
static const DECLARE_TLV_DB_SCALE(lineinboost_tlv, -1500, 300, 1);
static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(micboost_tlv,
0, 1, TLV_DB_SCALE_ITEM(0, 1300, 0),
2, 3, TLV_DB_SCALE_ITEM(2000, 900, 0),
);
static const struct snd_kcontrol_new wm8960_snd_controls[] = {
SOC_DOUBLE_R_TLV("Capture Volume", WM8960_LINVOL, WM8960_RINVOL,
0, 63, 0, inpga_tlv),
SOC_DOUBLE_R("Capture Volume ZC Switch", WM8960_LINVOL, WM8960_RINVOL,
6, 1, 0),
SOC_DOUBLE_R("Capture Switch", WM8960_LINVOL, WM8960_RINVOL,
7, 1, 1),
SOC_SINGLE_TLV("Left Input Boost Mixer LINPUT3 Volume",
WM8960_INBMIX1, 4, 7, 0, lineinboost_tlv),
SOC_SINGLE_TLV("Left Input Boost Mixer LINPUT2 Volume",
WM8960_INBMIX1, 1, 7, 0, lineinboost_tlv),
SOC_SINGLE_TLV("Right Input Boost Mixer RINPUT3 Volume",
WM8960_INBMIX2, 4, 7, 0, lineinboost_tlv),
SOC_SINGLE_TLV("Right Input Boost Mixer RINPUT2 Volume",
WM8960_INBMIX2, 1, 7, 0, lineinboost_tlv),
SOC_SINGLE_TLV("Right Input Boost Mixer RINPUT1 Volume",
WM8960_RINPATH, 4, 3, 0, micboost_tlv),
SOC_SINGLE_TLV("Left Input Boost Mixer LINPUT1 Volume",
WM8960_LINPATH, 4, 3, 0, micboost_tlv),
SOC_DOUBLE_R_TLV("Playback Volume", WM8960_LDAC, WM8960_RDAC,
0, 255, 0, dac_tlv),
SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8960_LOUT1, WM8960_ROUT1,
0, 127, 0, out_tlv),
SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8960_LOUT1, WM8960_ROUT1,
7, 1, 0),
SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8960_LOUT2, WM8960_ROUT2,
0, 127, 0, out_tlv),
SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8960_LOUT2, WM8960_ROUT2,
7, 1, 0),
SOC_SINGLE("Speaker DC Volume", WM8960_CLASSD3, 3, 5, 0),
SOC_SINGLE("Speaker AC Volume", WM8960_CLASSD3, 0, 5, 0),
SOC_SINGLE("PCM Playback -6dB Switch", WM8960_DACCTL1, 7, 1, 0),
SOC_ENUM("ADC Polarity", wm8960_enum[0]),
SOC_SINGLE("ADC High Pass Filter Switch", WM8960_DACCTL1, 0, 1, 0),
SOC_ENUM("DAC Polarity", wm8960_enum[1]),
SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
wm8960_get_deemph, wm8960_put_deemph),
SOC_ENUM("3D Filter Upper Cut-Off", wm8960_enum[2]),
SOC_ENUM("3D Filter Lower Cut-Off", wm8960_enum[3]),
SOC_SINGLE("3D Volume", WM8960_3D, 1, 15, 0),
SOC_SINGLE("3D Switch", WM8960_3D, 0, 1, 0),
SOC_ENUM("ALC Function", wm8960_enum[4]),
SOC_SINGLE("ALC Max Gain", WM8960_ALC1, 4, 7, 0),
SOC_SINGLE("ALC Target", WM8960_ALC1, 0, 15, 1),
SOC_SINGLE("ALC Min Gain", WM8960_ALC2, 4, 7, 0),
SOC_SINGLE("ALC Hold Time", WM8960_ALC2, 0, 15, 0),
SOC_ENUM("ALC Mode", wm8960_enum[5]),
SOC_SINGLE("ALC Decay", WM8960_ALC3, 4, 15, 0),
SOC_SINGLE("ALC Attack", WM8960_ALC3, 0, 15, 0),
SOC_SINGLE("Noise Gate Threshold", WM8960_NOISEG, 3, 31, 0),
SOC_SINGLE("Noise Gate Switch", WM8960_NOISEG, 0, 1, 0),
SOC_DOUBLE_R_TLV("ADC PCM Capture Volume", WM8960_LADC, WM8960_RADC,
0, 255, 0, adc_tlv),
SOC_SINGLE_TLV("Left Output Mixer Boost Bypass Volume",
WM8960_BYPASS1, 4, 7, 1, bypass_tlv),
SOC_SINGLE_TLV("Left Output Mixer LINPUT3 Volume",
WM8960_LOUTMIX, 4, 7, 1, bypass_tlv),
SOC_SINGLE_TLV("Right Output Mixer Boost Bypass Volume",
WM8960_BYPASS2, 4, 7, 1, bypass_tlv),
SOC_SINGLE_TLV("Right Output Mixer RINPUT3 Volume",
WM8960_ROUTMIX, 4, 7, 1, bypass_tlv),
SOC_ENUM("ADC Data Output Select", wm8960_enum[6]),
SOC_ENUM("DAC Mono Mix", wm8960_enum[7]),
SOC_ENUM("DAC Filter Characteristics", wm8960_enum[8]),
};
static const struct snd_kcontrol_new wm8960_lin_boost[] = {
SOC_DAPM_SINGLE("LINPUT2 Switch", WM8960_LINPATH, 6, 1, 0),
SOC_DAPM_SINGLE("LINPUT3 Switch", WM8960_LINPATH, 7, 1, 0),
SOC_DAPM_SINGLE("LINPUT1 Switch", WM8960_LINPATH, 8, 1, 0),
};
static const struct snd_kcontrol_new wm8960_lin[] = {
SOC_DAPM_SINGLE("Boost Switch", WM8960_LINPATH, 3, 1, 0),
};
static const struct snd_kcontrol_new wm8960_rin_boost[] = {
SOC_DAPM_SINGLE("RINPUT2 Switch", WM8960_RINPATH, 6, 1, 0),
SOC_DAPM_SINGLE("RINPUT3 Switch", WM8960_RINPATH, 7, 1, 0),
SOC_DAPM_SINGLE("RINPUT1 Switch", WM8960_RINPATH, 8, 1, 0),
};
static const struct snd_kcontrol_new wm8960_rin[] = {
SOC_DAPM_SINGLE("Boost Switch", WM8960_RINPATH, 3, 1, 0),
};
static const struct snd_kcontrol_new wm8960_loutput_mixer[] = {
SOC_DAPM_SINGLE("PCM Playback Switch", WM8960_LOUTMIX, 8, 1, 0),
SOC_DAPM_SINGLE("LINPUT3 Switch", WM8960_LOUTMIX, 7, 1, 0),
SOC_DAPM_SINGLE("Boost Bypass Switch", WM8960_BYPASS1, 7, 1, 0),
};
static const struct snd_kcontrol_new wm8960_routput_mixer[] = {
SOC_DAPM_SINGLE("PCM Playback Switch", WM8960_ROUTMIX, 8, 1, 0),
SOC_DAPM_SINGLE("RINPUT3 Switch", WM8960_ROUTMIX, 7, 1, 0),
SOC_DAPM_SINGLE("Boost Bypass Switch", WM8960_BYPASS2, 7, 1, 0),
};
static const struct snd_kcontrol_new wm8960_mono_out[] = {
SOC_DAPM_SINGLE("Left Switch", WM8960_MONOMIX1, 7, 1, 0),
SOC_DAPM_SINGLE("Right Switch", WM8960_MONOMIX2, 7, 1, 0),
};
static const struct snd_soc_dapm_widget wm8960_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("LINPUT1"),
SND_SOC_DAPM_INPUT("RINPUT1"),
SND_SOC_DAPM_INPUT("LINPUT2"),
SND_SOC_DAPM_INPUT("RINPUT2"),
SND_SOC_DAPM_INPUT("LINPUT3"),
SND_SOC_DAPM_INPUT("RINPUT3"),
SND_SOC_DAPM_SUPPLY("MICB", WM8960_POWER1, 1, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8960_POWER1, 5, 0,
wm8960_lin_boost, ARRAY_SIZE(wm8960_lin_boost)),
SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8960_POWER1, 4, 0,
wm8960_rin_boost, ARRAY_SIZE(wm8960_rin_boost)),
SND_SOC_DAPM_MIXER("Left Input Mixer", WM8960_POWER3, 5, 0,
wm8960_lin, ARRAY_SIZE(wm8960_lin)),
SND_SOC_DAPM_MIXER("Right Input Mixer", WM8960_POWER3, 4, 0,
wm8960_rin, ARRAY_SIZE(wm8960_rin)),
SND_SOC_DAPM_ADC("Left ADC", "Capture", WM8960_POWER1, 3, 0),
SND_SOC_DAPM_ADC("Right ADC", "Capture", WM8960_POWER1, 2, 0),
SND_SOC_DAPM_DAC("Left DAC", "Playback", WM8960_POWER2, 8, 0),
SND_SOC_DAPM_DAC("Right DAC", "Playback", WM8960_POWER2, 7, 0),
SND_SOC_DAPM_MIXER("Left Output Mixer", WM8960_POWER3, 3, 0,
&wm8960_loutput_mixer[0],
ARRAY_SIZE(wm8960_loutput_mixer)),
SND_SOC_DAPM_MIXER("Right Output Mixer", WM8960_POWER3, 2, 0,
&wm8960_routput_mixer[0],
ARRAY_SIZE(wm8960_routput_mixer)),
SND_SOC_DAPM_PGA("LOUT1 PGA", WM8960_POWER2, 6, 0, NULL, 0),
SND_SOC_DAPM_PGA("ROUT1 PGA", WM8960_POWER2, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA("Left Speaker PGA", WM8960_POWER2, 4, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Speaker PGA", WM8960_POWER2, 3, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Speaker Output", WM8960_CLASSD1, 7, 0, NULL, 0),
SND_SOC_DAPM_PGA("Left Speaker Output", WM8960_CLASSD1, 6, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("SPK_LP"),
SND_SOC_DAPM_OUTPUT("SPK_LN"),
SND_SOC_DAPM_OUTPUT("HP_L"),
SND_SOC_DAPM_OUTPUT("HP_R"),
SND_SOC_DAPM_OUTPUT("SPK_RP"),
SND_SOC_DAPM_OUTPUT("SPK_RN"),
SND_SOC_DAPM_OUTPUT("OUT3"),
};
static const struct snd_soc_dapm_widget wm8960_dapm_widgets_out3[] = {
SND_SOC_DAPM_MIXER("Mono Output Mixer", WM8960_POWER2, 1, 0,
&wm8960_mono_out[0],
ARRAY_SIZE(wm8960_mono_out)),
};
/* Represent OUT3 as a PGA so that it gets turned on with LOUT1/ROUT1 */
static const struct snd_soc_dapm_widget wm8960_dapm_widgets_capless[] = {
SND_SOC_DAPM_PGA("OUT3 VMID", WM8960_POWER2, 1, 0, NULL, 0),
};
static const struct snd_soc_dapm_route audio_paths[] = {
{ "Left Boost Mixer", "LINPUT1 Switch", "LINPUT1" },
{ "Left Boost Mixer", "LINPUT2 Switch", "LINPUT2" },
{ "Left Boost Mixer", "LINPUT3 Switch", "LINPUT3" },
{ "Left Input Mixer", "Boost Switch", "Left Boost Mixer" },
{ "Left Input Mixer", "Boost Switch", "LINPUT1" }, /* Really Boost Switch */
{ "Left Input Mixer", NULL, "LINPUT2" },
{ "Left Input Mixer", NULL, "LINPUT3" },
{ "Right Boost Mixer", "RINPUT1 Switch", "RINPUT1" },
{ "Right Boost Mixer", "RINPUT2 Switch", "RINPUT2" },
{ "Right Boost Mixer", "RINPUT3 Switch", "RINPUT3" },
{ "Right Input Mixer", "Boost Switch", "Right Boost Mixer" },
{ "Right Input Mixer", "Boost Switch", "RINPUT1" }, /* Really Boost Switch */
{ "Right Input Mixer", NULL, "RINPUT2" },
{ "Right Input Mixer", NULL, "RINPUT3" },
{ "Left ADC", NULL, "Left Input Mixer" },
{ "Right ADC", NULL, "Right Input Mixer" },
{ "Left Output Mixer", "LINPUT3 Switch", "LINPUT3" },
{ "Left Output Mixer", "Boost Bypass Switch", "Left Boost Mixer" },
{ "Left Output Mixer", "PCM Playback Switch", "Left DAC" },
{ "Right Output Mixer", "RINPUT3 Switch", "RINPUT3" },
{ "Right Output Mixer", "Boost Bypass Switch", "Right Boost Mixer" },
{ "Right Output Mixer", "PCM Playback Switch", "Right DAC" },
{ "LOUT1 PGA", NULL, "Left Output Mixer" },
{ "ROUT1 PGA", NULL, "Right Output Mixer" },
{ "HP_L", NULL, "LOUT1 PGA" },
{ "HP_R", NULL, "ROUT1 PGA" },
{ "Left Speaker PGA", NULL, "Left Output Mixer" },
{ "Right Speaker PGA", NULL, "Right Output Mixer" },
{ "Left Speaker Output", NULL, "Left Speaker PGA" },
{ "Right Speaker Output", NULL, "Right Speaker PGA" },
{ "SPK_LN", NULL, "Left Speaker Output" },
{ "SPK_LP", NULL, "Left Speaker Output" },
{ "SPK_RN", NULL, "Right Speaker Output" },
{ "SPK_RP", NULL, "Right Speaker Output" },
};
static const struct snd_soc_dapm_route audio_paths_out3[] = {
{ "Mono Output Mixer", "Left Switch", "Left Output Mixer" },
{ "Mono Output Mixer", "Right Switch", "Right Output Mixer" },
{ "OUT3", NULL, "Mono Output Mixer", }
};
static const struct snd_soc_dapm_route audio_paths_capless[] = {
{ "HP_L", NULL, "OUT3 VMID" },
{ "HP_R", NULL, "OUT3 VMID" },
{ "OUT3 VMID", NULL, "Left Output Mixer" },
{ "OUT3 VMID", NULL, "Right Output Mixer" },
};
static int wm8960_add_widgets(struct snd_soc_component *component)
{
struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component);
struct wm8960_data *pdata = &wm8960->pdata;
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct snd_soc_dapm_widget *w;
snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets,
ARRAY_SIZE(wm8960_dapm_widgets));
snd_soc_dapm_add_routes(dapm, audio_paths, ARRAY_SIZE(audio_paths));
/* In capless mode OUT3 is used to provide VMID for the
* headphone outputs, otherwise it is used as a mono mixer.
*/
if (pdata && pdata->capless) {
snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets_capless,
ARRAY_SIZE(wm8960_dapm_widgets_capless));
snd_soc_dapm_add_routes(dapm, audio_paths_capless,
ARRAY_SIZE(audio_paths_capless));
} else {
snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets_out3,
ARRAY_SIZE(wm8960_dapm_widgets_out3));
snd_soc_dapm_add_routes(dapm, audio_paths_out3,
ARRAY_SIZE(audio_paths_out3));
}
/* We need to power up the headphone output stage out of
* sequence for capless mode. To save scanning the widget
* list each time to find the desired power state do so now
* and save the result.
*/
list_for_each_entry(w, &component->card->widgets, list) {
if (w->dapm != dapm)
continue;
if (strcmp(w->name, "LOUT1 PGA") == 0)
wm8960->lout1 = w;
if (strcmp(w->name, "ROUT1 PGA") == 0)
wm8960->rout1 = w;
if (strcmp(w->name, "OUT3 VMID") == 0)
wm8960->out3 = w;
}
return 0;
}
static int wm8960_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
u16 iface = 0;
/* set master/slave audio interface */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
iface |= 0x0040;
break;
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface |= 0x0002;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
iface |= 0x0001;
break;
case SND_SOC_DAIFMT_DSP_A:
iface |= 0x0003;
break;
case SND_SOC_DAIFMT_DSP_B:
iface |= 0x0013;
break;
default:
return -EINVAL;
}
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
iface |= 0x0090;
break;
case SND_SOC_DAIFMT_IB_NF:
iface |= 0x0080;
break;
case SND_SOC_DAIFMT_NB_IF:
iface |= 0x0010;
break;
default:
return -EINVAL;
}
/* set iface */
snd_soc_component_write(component, WM8960_IFACE1, iface);
return 0;
}
static struct {
int rate;
unsigned int val;
} alc_rates[] = {
{ 48000, 0 },
{ 44100, 0 },
{ 32000, 1 },
{ 22050, 2 },
{ 24000, 2 },
{ 16000, 3 },
{ 11025, 4 },
{ 12000, 4 },
{ 8000, 5 },
};
/* -1 for reserved value */
static const int sysclk_divs[] = { 1, -1, 2, -1 };
/* Multiply 256 for internal 256 div */
static const int dac_divs[] = { 256, 384, 512, 768, 1024, 1408, 1536 };
/* Multiply 10 to eliminate decimials */
static const int bclk_divs[] = {
10, 15, 20, 30, 40, 55, 60, 80, 110,
120, 160, 220, 240, 320, 320, 320
};
/**
* wm8960_configure_sysclk - checks if there is a sysclk frequency available
* The sysclk must be chosen such that:
* - sysclk = MCLK / sysclk_divs
* - lrclk = sysclk / dac_divs
* - 10 * bclk = sysclk / bclk_divs
*
* @wm8960: codec private data
* @mclk: MCLK used to derive sysclk
* @sysclk_idx: sysclk_divs index for found sysclk
* @dac_idx: dac_divs index for found lrclk
* @bclk_idx: bclk_divs index for found bclk
*
* Returns:
* -1, in case no sysclk frequency available found
* >=0, in case we could derive bclk and lrclk from sysclk using
* (@sysclk_idx, @dac_idx, @bclk_idx) dividers
*/
static
int wm8960_configure_sysclk(struct wm8960_priv *wm8960, int mclk,
int *sysclk_idx, int *dac_idx, int *bclk_idx)
{
int sysclk, bclk, lrclk;
int i, j, k;
int diff;
/* marker for no match */
*bclk_idx = -1;
bclk = wm8960->bclk;
lrclk = wm8960->lrclk;
/* check if the sysclk frequency is available. */
for (i = 0; i < ARRAY_SIZE(sysclk_divs); ++i) {
if (sysclk_divs[i] == -1)
continue;
sysclk = mclk / sysclk_divs[i];
for (j = 0; j < ARRAY_SIZE(dac_divs); ++j) {
if (sysclk != dac_divs[j] * lrclk)
continue;
for (k = 0; k < ARRAY_SIZE(bclk_divs); ++k) {
diff = sysclk - bclk * bclk_divs[k] / 10;
if (diff == 0) {
*sysclk_idx = i;
*dac_idx = j;
*bclk_idx = k;
break;
}
}
if (k != ARRAY_SIZE(bclk_divs))
break;
}
if (j != ARRAY_SIZE(dac_divs))
break;
}
return *bclk_idx;
}
/**
* wm8960_configure_pll - checks if there is a PLL out frequency available
* The PLL out frequency must be chosen such that:
* - sysclk = lrclk * dac_divs
* - freq_out = sysclk * sysclk_divs
* - 10 * sysclk = bclk * bclk_divs
*
* If we cannot find an exact match for (sysclk, lrclk, bclk)
* triplet, we relax the bclk such that bclk is chosen as the
* closest available frequency greater than expected bclk.
*
* @component: component structure
* @freq_in: input frequency used to derive freq out via PLL
* @sysclk_idx: sysclk_divs index for found sysclk
* @dac_idx: dac_divs index for found lrclk
* @bclk_idx: bclk_divs index for found bclk
*
* Returns:
* < 0, in case no PLL frequency out available was found
* >=0, in case we could derive bclk, lrclk, sysclk from PLL out using
* (@sysclk_idx, @dac_idx, @bclk_idx) dividers
*/
static
int wm8960_configure_pll(struct snd_soc_component *component, int freq_in,
int *sysclk_idx, int *dac_idx, int *bclk_idx)
{
struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component);
int sysclk, bclk, lrclk, freq_out;
int diff, closest, best_freq_out;
int i, j, k;
bclk = wm8960->bclk;
lrclk = wm8960->lrclk;
closest = freq_in;
best_freq_out = -EINVAL;
*sysclk_idx = *dac_idx = *bclk_idx = -1;
/*
* From Datasheet, the PLL performs best when f2 is between
* 90MHz and 100MHz, the desired sysclk output is 11.2896MHz
* or 12.288MHz, then sysclkdiv = 2 is the best choice.
* So search sysclk_divs from 2 to 1 other than from 1 to 2.
*/
for (i = ARRAY_SIZE(sysclk_divs) - 1; i >= 0; --i) {
if (sysclk_divs[i] == -1)
continue;
for (j = 0; j < ARRAY_SIZE(dac_divs); ++j) {
sysclk = lrclk * dac_divs[j];
freq_out = sysclk * sysclk_divs[i];
for (k = 0; k < ARRAY_SIZE(bclk_divs); ++k) {
if (!is_pll_freq_available(freq_in, freq_out))
continue;
diff = sysclk - bclk * bclk_divs[k] / 10;
if (diff == 0) {
*sysclk_idx = i;
*dac_idx = j;
*bclk_idx = k;
return freq_out;
}
if (diff > 0 && closest > diff) {
*sysclk_idx = i;
*dac_idx = j;
*bclk_idx = k;
closest = diff;
best_freq_out = freq_out;
}
}
}
}
return best_freq_out;
}
static int wm8960_configure_clocking(struct snd_soc_component *component)
{
struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component);
int freq_out, freq_in;
u16 iface1 = snd_soc_component_read(component, WM8960_IFACE1);
int i, j, k;
int ret;
/*
* For Slave mode clocking should still be configured,
* so this if statement should be removed, but some platform
* may not work if the sysclk is not configured, to avoid such
* compatible issue, just add '!wm8960->sysclk' condition in
* this if statement.
*/
if (!(iface1 & (1 << 6)) && !wm8960->sysclk) {
dev_warn(component->dev,
"slave mode, but proceeding with no clock configuration\n");
return 0;
}
if (wm8960->clk_id != WM8960_SYSCLK_MCLK && !wm8960->freq_in) {
dev_err(component->dev, "No MCLK configured\n");
return -EINVAL;
}
freq_in = wm8960->freq_in;
/*
* If it's sysclk auto mode, check if the MCLK can provide sysclk or
* not. If MCLK can provide sysclk, using MCLK to provide sysclk
* directly. Otherwise, auto select a available pll out frequency
* and set PLL.
*/
if (wm8960->clk_id == WM8960_SYSCLK_AUTO) {
/* disable the PLL and using MCLK to provide sysclk */
wm8960_set_pll(component, 0, 0);
freq_out = freq_in;
} else if (wm8960->sysclk) {
freq_out = wm8960->sysclk;
} else {
dev_err(component->dev, "No SYSCLK configured\n");
return -EINVAL;
}
if (wm8960->clk_id != WM8960_SYSCLK_PLL) {
ret = wm8960_configure_sysclk(wm8960, freq_out, &i, &j, &k);
if (ret >= 0) {
goto configure_clock;
} else if (wm8960->clk_id != WM8960_SYSCLK_AUTO) {
dev_err(component->dev, "failed to configure clock\n");
return -EINVAL;
}
}
freq_out = wm8960_configure_pll(component, freq_in, &i, &j, &k);
if (freq_out < 0) {
dev_err(component->dev, "failed to configure clock via PLL\n");
return freq_out;
}
wm8960_set_pll(component, freq_in, freq_out);
configure_clock:
/* configure sysclk clock */
snd_soc_component_update_bits(component, WM8960_CLOCK1, 3 << 1, i << 1);
/* configure frame clock */
snd_soc_component_update_bits(component, WM8960_CLOCK1, 0x7 << 3, j << 3);
snd_soc_component_update_bits(component, WM8960_CLOCK1, 0x7 << 6, j << 6);
/* configure bit clock */
snd_soc_component_update_bits(component, WM8960_CLOCK2, 0xf, k);
return 0;
}
static int wm8960_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component);
u16 iface = snd_soc_component_read(component, WM8960_IFACE1) & 0xfff3;
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
int i;
wm8960->bclk = snd_soc_params_to_bclk(params);
if (params_channels(params) == 1)
wm8960->bclk *= 2;
/* bit size */
switch (params_width(params)) {
case 16:
break;
case 20:
iface |= 0x0004;
break;
case 24:
iface |= 0x0008;
break;
case 32:
/* right justify mode does not support 32 word length */
if ((iface & 0x3) != 0) {
iface |= 0x000c;
break;
}
fallthrough;
default:
dev_err(component->dev, "unsupported width %d\n",
params_width(params));
return -EINVAL;
}
wm8960->lrclk = params_rate(params);
/* Update filters for the new rate */
if (tx) {
wm8960_set_deemph(component);
} else {
for (i = 0; i < ARRAY_SIZE(alc_rates); i++)
if (alc_rates[i].rate == params_rate(params))
snd_soc_component_update_bits(component,
WM8960_ADDCTL3, 0x7,
alc_rates[i].val);
}
/* set iface */
snd_soc_component_write(component, WM8960_IFACE1, iface);
wm8960->is_stream_in_use[tx] = true;
if (!wm8960->is_stream_in_use[!tx])
return wm8960_configure_clocking(component);
return 0;
}
static int wm8960_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component);
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
wm8960->is_stream_in_use[tx] = false;
return 0;
}
static int wm8960_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
if (mute)
snd_soc_component_update_bits(component, WM8960_DACCTL1, 0x8, 0x8);
else
snd_soc_component_update_bits(component, WM8960_DACCTL1, 0x8, 0);
return 0;
}
static int wm8960_set_bias_level_out3(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component);
u16 pm2 = snd_soc_component_read(component, WM8960_POWER2);
int ret;
ktime_t tout;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
switch (snd_soc_component_get_bias_level(component)) {
case SND_SOC_BIAS_STANDBY:
if (!IS_ERR(wm8960->mclk)) {
ret = clk_prepare_enable(wm8960->mclk);
if (ret) {
dev_err(component->dev,
"Failed to enable MCLK: %d\n",
ret);
return ret;
}
}
ret = wm8960_configure_clocking(component);
if (ret)
return ret;
/* Set VMID to 2x50k */
snd_soc_component_update_bits(component, WM8960_POWER1, 0x180, 0x80);
break;
case SND_SOC_BIAS_ON:
/*
* If it's sysclk auto mode, and the pll is enabled,
* disable the pll
*/
if (wm8960->clk_id == WM8960_SYSCLK_AUTO && (pm2 & 0x1))
wm8960_set_pll(component, 0, 0);
if (!IS_ERR(wm8960->mclk))
clk_disable_unprepare(wm8960->mclk);
break;
default:
break;
}
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
/* ensure discharge is complete */
tout = WM8960_DSCH_TOUT - ktime_ms_delta(ktime_get(), wm8960->dsch_start);
if (tout > 0)
msleep(tout);
regcache_sync(wm8960->regmap);
/* Enable anti-pop features */
snd_soc_component_write(component, WM8960_APOP1,
WM8960_POBCTRL | WM8960_SOFT_ST |
WM8960_BUFDCOPEN | WM8960_BUFIOEN);
/* Enable & ramp VMID at 2x50k */
snd_soc_component_update_bits(component, WM8960_POWER1, 0x80, 0x80);
msleep(100);
/* Enable VREF */
snd_soc_component_update_bits(component, WM8960_POWER1, WM8960_VREF,
WM8960_VREF);
/* Disable anti-pop features */
snd_soc_component_write(component, WM8960_APOP1, WM8960_BUFIOEN);
}
/* Set VMID to 2x250k */
snd_soc_component_update_bits(component, WM8960_POWER1, 0x180, 0x100);
break;
case SND_SOC_BIAS_OFF:
/* Enable anti-pop features */
snd_soc_component_write(component, WM8960_APOP1,
WM8960_POBCTRL | WM8960_SOFT_ST |
WM8960_BUFDCOPEN | WM8960_BUFIOEN);
/* Disable VMID and VREF, mark discharge */
snd_soc_component_write(component, WM8960_POWER1, 0);
wm8960->dsch_start = ktime_get();
break;
}
return 0;
}
static int wm8960_set_bias_level_capless(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component);
u16 pm2 = snd_soc_component_read(component, WM8960_POWER2);
int reg, ret;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
switch (snd_soc_component_get_bias_level(component)) {
case SND_SOC_BIAS_STANDBY:
/* Enable anti pop mode */
snd_soc_component_update_bits(component, WM8960_APOP1,
WM8960_POBCTRL | WM8960_SOFT_ST |
WM8960_BUFDCOPEN,
WM8960_POBCTRL | WM8960_SOFT_ST |
WM8960_BUFDCOPEN);
/* Enable LOUT1, ROUT1 and OUT3 if they're enabled */
reg = 0;
if (wm8960->lout1 && wm8960->lout1->power)
reg |= WM8960_PWR2_LOUT1;
if (wm8960->rout1 && wm8960->rout1->power)
reg |= WM8960_PWR2_ROUT1;
if (wm8960->out3 && wm8960->out3->power)
reg |= WM8960_PWR2_OUT3;
snd_soc_component_update_bits(component, WM8960_POWER2,
WM8960_PWR2_LOUT1 |
WM8960_PWR2_ROUT1 |
WM8960_PWR2_OUT3, reg);
/* Enable VMID at 2*50k */
snd_soc_component_update_bits(component, WM8960_POWER1,
WM8960_VMID_MASK, 0x80);
/* Ramp */
msleep(100);
/* Enable VREF */
snd_soc_component_update_bits(component, WM8960_POWER1,
WM8960_VREF, WM8960_VREF);
msleep(100);
if (!IS_ERR(wm8960->mclk)) {
ret = clk_prepare_enable(wm8960->mclk);
if (ret) {
dev_err(component->dev,
"Failed to enable MCLK: %d\n",
ret);
return ret;
}
}
ret = wm8960_configure_clocking(component);
if (ret)
return ret;
break;
case SND_SOC_BIAS_ON:
/*
* If it's sysclk auto mode, and the pll is enabled,
* disable the pll
*/
if (wm8960->clk_id == WM8960_SYSCLK_AUTO && (pm2 & 0x1))
wm8960_set_pll(component, 0, 0);
if (!IS_ERR(wm8960->mclk))
clk_disable_unprepare(wm8960->mclk);
/* Enable anti-pop mode */
snd_soc_component_update_bits(component, WM8960_APOP1,
WM8960_POBCTRL | WM8960_SOFT_ST |
WM8960_BUFDCOPEN,
WM8960_POBCTRL | WM8960_SOFT_ST |
WM8960_BUFDCOPEN);
/* Disable VMID and VREF */
snd_soc_component_update_bits(component, WM8960_POWER1,
WM8960_VREF | WM8960_VMID_MASK, 0);
break;
case SND_SOC_BIAS_OFF:
regcache_sync(wm8960->regmap);
break;
default:
break;
}
break;
case SND_SOC_BIAS_STANDBY:
switch (snd_soc_component_get_bias_level(component)) {
case SND_SOC_BIAS_PREPARE:
/* Disable HP discharge */
snd_soc_component_update_bits(component, WM8960_APOP2,
WM8960_DISOP | WM8960_DRES_MASK,
0);
/* Disable anti-pop features */
snd_soc_component_update_bits(component, WM8960_APOP1,
WM8960_POBCTRL | WM8960_SOFT_ST |
WM8960_BUFDCOPEN,
WM8960_POBCTRL | WM8960_SOFT_ST |
WM8960_BUFDCOPEN);
break;
default:
break;
}
break;
case SND_SOC_BIAS_OFF:
break;
}
return 0;
}
/* PLL divisors */
struct _pll_div {
u32 pre_div:1;
u32 n:4;
u32 k:24;
};
static bool is_pll_freq_available(unsigned int source, unsigned int target)
{
unsigned int Ndiv;
if (source == 0 || target == 0)
return false;
/* Scale up target to PLL operating frequency */
target *= 4;
Ndiv = target / source;
if (Ndiv < 6) {
source >>= 1;
Ndiv = target / source;
}
if ((Ndiv < 6) || (Ndiv > 12))
return false;
return true;
}
/* The size in bits of the pll divide multiplied by 10
* to allow rounding later */
#define FIXED_PLL_SIZE ((1 << 24) * 10)
static int pll_factors(unsigned int source, unsigned int target,
struct _pll_div *pll_div)
{
unsigned long long Kpart;
unsigned int K, Ndiv, Nmod;
pr_debug("WM8960 PLL: setting %dHz->%dHz\n", source, target);
/* Scale up target to PLL operating frequency */
target *= 4;
Ndiv = target / source;
if (Ndiv < 6) {
source >>= 1;
pll_div->pre_div = 1;
Ndiv = target / source;
} else
pll_div->pre_div = 0;
if ((Ndiv < 6) || (Ndiv > 12)) {
pr_err("WM8960 PLL: Unsupported N=%d\n", Ndiv);
return -EINVAL;
}
pll_div->n = Ndiv;
Nmod = target % source;
Kpart = FIXED_PLL_SIZE * (long long)Nmod;
do_div(Kpart, source);
K = Kpart & 0xFFFFFFFF;
/* Check if we need to round */
if ((K % 10) >= 5)
K += 5;
/* Move down to proper range now rounding is done */
K /= 10;
pll_div->k = K;
pr_debug("WM8960 PLL: N=%x K=%x pre_div=%d\n",
pll_div->n, pll_div->k, pll_div->pre_div);
return 0;
}
static int wm8960_set_pll(struct snd_soc_component *component,
unsigned int freq_in, unsigned int freq_out)
{
u16 reg;
static struct _pll_div pll_div;
int ret;
if (freq_in && freq_out) {
ret = pll_factors(freq_in, freq_out, &pll_div);
if (ret != 0)
return ret;
}
/* Disable the PLL: even if we are changing the frequency the
* PLL needs to be disabled while we do so. */
snd_soc_component_update_bits(component, WM8960_CLOCK1, 0x1, 0);
snd_soc_component_update_bits(component, WM8960_POWER2, 0x1, 0);
if (!freq_in || !freq_out)
return 0;
reg = snd_soc_component_read(component, WM8960_PLL1) & ~0x3f;
reg |= pll_div.pre_div << 4;
reg |= pll_div.n;
if (pll_div.k) {
reg |= 0x20;
snd_soc_component_write(component, WM8960_PLL2, (pll_div.k >> 16) & 0xff);
snd_soc_component_write(component, WM8960_PLL3, (pll_div.k >> 8) & 0xff);
snd_soc_component_write(component, WM8960_PLL4, pll_div.k & 0xff);
}
snd_soc_component_write(component, WM8960_PLL1, reg);
/* Turn it on */
snd_soc_component_update_bits(component, WM8960_POWER2, 0x1, 0x1);
msleep(250);
snd_soc_component_update_bits(component, WM8960_CLOCK1, 0x1, 0x1);
return 0;
}
static int wm8960_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
int source, unsigned int freq_in, unsigned int freq_out)
{
struct snd_soc_component *component = codec_dai->component;
struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component);
wm8960->freq_in = freq_in;
if (pll_id == WM8960_SYSCLK_AUTO)
return 0;
return wm8960_set_pll(component, freq_in, freq_out);
}
static int wm8960_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
int div_id, int div)
{
struct snd_soc_component *component = codec_dai->component;
u16 reg;
switch (div_id) {
case WM8960_SYSCLKDIV:
reg = snd_soc_component_read(component, WM8960_CLOCK1) & 0x1f9;
snd_soc_component_write(component, WM8960_CLOCK1, reg | div);
break;
case WM8960_DACDIV:
reg = snd_soc_component_read(component, WM8960_CLOCK1) & 0x1c7;
snd_soc_component_write(component, WM8960_CLOCK1, reg | div);
break;
case WM8960_OPCLKDIV:
reg = snd_soc_component_read(component, WM8960_PLL1) & 0x03f;
snd_soc_component_write(component, WM8960_PLL1, reg | div);
break;
case WM8960_DCLKDIV:
reg = snd_soc_component_read(component, WM8960_CLOCK2) & 0x03f;
snd_soc_component_write(component, WM8960_CLOCK2, reg | div);
break;
case WM8960_TOCLKSEL:
reg = snd_soc_component_read(component, WM8960_ADDCTL1) & 0x1fd;
snd_soc_component_write(component, WM8960_ADDCTL1, reg | div);
break;
default:
return -EINVAL;
}
return 0;
}
static int wm8960_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component);
return wm8960->set_bias_level(component, level);
}
static int wm8960_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component);
switch (clk_id) {
case WM8960_SYSCLK_MCLK:
snd_soc_component_update_bits(component, WM8960_CLOCK1,
0x1, WM8960_SYSCLK_MCLK);
break;
case WM8960_SYSCLK_PLL:
snd_soc_component_update_bits(component, WM8960_CLOCK1,
0x1, WM8960_SYSCLK_PLL);
break;
case WM8960_SYSCLK_AUTO:
break;
default:
return -EINVAL;
}
wm8960->sysclk = freq;
wm8960->clk_id = clk_id;
return 0;
}
#define WM8960_RATES SNDRV_PCM_RATE_8000_48000
#define WM8960_FORMATS \
(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops wm8960_dai_ops = {
.hw_params = wm8960_hw_params,
.hw_free = wm8960_hw_free,
.mute_stream = wm8960_mute,
.set_fmt = wm8960_set_dai_fmt,
.set_clkdiv = wm8960_set_dai_clkdiv,
.set_pll = wm8960_set_dai_pll,
.set_sysclk = wm8960_set_dai_sysclk,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver wm8960_dai = {
.name = "wm8960-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM8960_RATES,
.formats = WM8960_FORMATS,},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM8960_RATES,
.formats = WM8960_FORMATS,},
.ops = &wm8960_dai_ops,
.symmetric_rate = 1,
};
static int wm8960_probe(struct snd_soc_component *component)
{
struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component);
struct wm8960_data *pdata = &wm8960->pdata;
if (pdata->capless)
wm8960->set_bias_level = wm8960_set_bias_level_capless;
else
wm8960->set_bias_level = wm8960_set_bias_level_out3;
snd_soc_add_component_controls(component, wm8960_snd_controls,
ARRAY_SIZE(wm8960_snd_controls));
wm8960_add_widgets(component);
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_wm8960 = {
.probe = wm8960_probe,
.set_bias_level = wm8960_set_bias_level,
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config wm8960_regmap = {
.reg_bits = 7,
.val_bits = 9,
.max_register = WM8960_PLL4,
.reg_defaults = wm8960_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8960_reg_defaults),
.cache_type = REGCACHE_MAPLE,
.volatile_reg = wm8960_volatile,
};
static void wm8960_set_pdata_from_of(struct i2c_client *i2c,
struct wm8960_data *pdata)
{
const struct device_node *np = i2c->dev.of_node;
if (of_property_read_bool(np, "wlf,capless"))
pdata->capless = true;
if (of_property_read_bool(np, "wlf,shared-lrclk"))
pdata->shared_lrclk = true;
of_property_read_u32_array(np, "wlf,gpio-cfg", pdata->gpio_cfg,
ARRAY_SIZE(pdata->gpio_cfg));
of_property_read_u32_array(np, "wlf,hp-cfg", pdata->hp_cfg,
ARRAY_SIZE(pdata->hp_cfg));
}
static int wm8960_i2c_probe(struct i2c_client *i2c)
{
struct wm8960_data *pdata = dev_get_platdata(&i2c->dev);
struct wm8960_priv *wm8960;
unsigned int i;
int ret;
u8 val;
wm8960 = devm_kzalloc(&i2c->dev, sizeof(struct wm8960_priv),
GFP_KERNEL);
if (wm8960 == NULL)
return -ENOMEM;
wm8960->mclk = devm_clk_get(&i2c->dev, "mclk");
if (IS_ERR(wm8960->mclk)) {
if (PTR_ERR(wm8960->mclk) == -EPROBE_DEFER)
return -EPROBE_DEFER;
} else {
ret = clk_get_rate(wm8960->mclk);
if (ret >= 0) {
wm8960->freq_in = ret;
} else {
dev_err(&i2c->dev, "Failed to read MCLK rate: %d\n",
ret);
}
}
for (i = 0; i < ARRAY_SIZE(wm8960->supplies); i++)
wm8960->supplies[i].supply = wm8960_supply_names[i];
ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8960->supplies),
wm8960->supplies);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
return ret;
}
ret = regulator_bulk_enable(ARRAY_SIZE(wm8960->supplies),
wm8960->supplies);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
return ret;
}
wm8960->regmap = devm_regmap_init_i2c(i2c, &wm8960_regmap);
if (IS_ERR(wm8960->regmap)) {
ret = PTR_ERR(wm8960->regmap);
goto bulk_disable;
}
if (pdata)
memcpy(&wm8960->pdata, pdata, sizeof(struct wm8960_data));
else if (i2c->dev.of_node)
wm8960_set_pdata_from_of(i2c, &wm8960->pdata);
ret = i2c_master_recv(i2c, &val, sizeof(val));
if (ret >= 0) {
dev_err(&i2c->dev, "Not wm8960, wm8960 reg can not read by i2c\n");
ret = -EINVAL;
goto bulk_disable;
}
ret = wm8960_reset(wm8960->regmap);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to issue reset\n");
goto bulk_disable;
}
if (wm8960->pdata.shared_lrclk) {
ret = regmap_update_bits(wm8960->regmap, WM8960_ADDCTL2,
0x4, 0x4);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to enable LRCM: %d\n",
ret);
goto bulk_disable;
}
}
/* Latch the update bits */
regmap_update_bits(wm8960->regmap, WM8960_LINVOL, 0x100, 0x100);
regmap_update_bits(wm8960->regmap, WM8960_RINVOL, 0x100, 0x100);
regmap_update_bits(wm8960->regmap, WM8960_LADC, 0x100, 0x100);
regmap_update_bits(wm8960->regmap, WM8960_RADC, 0x100, 0x100);
regmap_update_bits(wm8960->regmap, WM8960_LDAC, 0x100, 0x100);
regmap_update_bits(wm8960->regmap, WM8960_RDAC, 0x100, 0x100);
regmap_update_bits(wm8960->regmap, WM8960_LOUT1, 0x100, 0x100);
regmap_update_bits(wm8960->regmap, WM8960_ROUT1, 0x100, 0x100);
regmap_update_bits(wm8960->regmap, WM8960_LOUT2, 0x100, 0x100);
regmap_update_bits(wm8960->regmap, WM8960_ROUT2, 0x100, 0x100);
/* ADCLRC pin configured as GPIO. */
regmap_update_bits(wm8960->regmap, WM8960_IFACE2, 1 << 6,
wm8960->pdata.gpio_cfg[0] << 6);
regmap_update_bits(wm8960->regmap, WM8960_ADDCTL4, 0xF << 4,
wm8960->pdata.gpio_cfg[1] << 4);
/* Enable headphone jack detect */
regmap_update_bits(wm8960->regmap, WM8960_ADDCTL4, 3 << 2,
wm8960->pdata.hp_cfg[0] << 2);
regmap_update_bits(wm8960->regmap, WM8960_ADDCTL2, 3 << 5,
wm8960->pdata.hp_cfg[1] << 5);
regmap_update_bits(wm8960->regmap, WM8960_ADDCTL1, 3,
wm8960->pdata.hp_cfg[2]);
i2c_set_clientdata(i2c, wm8960);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_wm8960, &wm8960_dai, 1);
if (ret)
goto bulk_disable;
return 0;
bulk_disable:
regulator_bulk_disable(ARRAY_SIZE(wm8960->supplies), wm8960->supplies);
return ret;
}
static void wm8960_i2c_remove(struct i2c_client *client)
{
struct wm8960_priv *wm8960 = i2c_get_clientdata(client);
regulator_bulk_disable(ARRAY_SIZE(wm8960->supplies), wm8960->supplies);
}
static const struct i2c_device_id wm8960_i2c_id[] = {
{ "wm8960", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8960_i2c_id);
#if defined(CONFIG_OF)
static const struct of_device_id wm8960_of_match[] = {
{ .compatible = "wlf,wm8960", },
{ }
};
MODULE_DEVICE_TABLE(of, wm8960_of_match);
#endif
#if defined(CONFIG_ACPI)
static const struct acpi_device_id wm8960_acpi_match[] = {
{ "1AEC8960", 0 }, /* Wolfson PCI ID + part ID */
{ "10138960", 0 }, /* Cirrus Logic PCI ID + part ID */
{ },
};
MODULE_DEVICE_TABLE(acpi, wm8960_acpi_match);
#endif
static struct i2c_driver wm8960_i2c_driver = {
.driver = {
.name = "wm8960",
.of_match_table = of_match_ptr(wm8960_of_match),
.acpi_match_table = ACPI_PTR(wm8960_acpi_match),
},
.probe = wm8960_i2c_probe,
.remove = wm8960_i2c_remove,
.id_table = wm8960_i2c_id,
};
module_i2c_driver(wm8960_i2c_driver);
MODULE_DESCRIPTION("ASoC WM8960 driver");
MODULE_AUTHOR("Liam Girdwood");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8960.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* PCM179X ASoC codec driver
*
* Copyright (c) Amarula Solutions B.V. 2013
*
* Michael Trimarchi <[email protected]>
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <linux/of.h>
#include "pcm179x.h"
#define PCM179X_DAC_VOL_LEFT 0x10
#define PCM179X_DAC_VOL_RIGHT 0x11
#define PCM179X_FMT_CONTROL 0x12
#define PCM179X_MODE_CONTROL 0x13
#define PCM179X_SOFT_MUTE PCM179X_FMT_CONTROL
#define PCM179X_FMT_MASK 0x70
#define PCM179X_FMT_SHIFT 4
#define PCM179X_MUTE_MASK 0x01
#define PCM179X_MUTE_SHIFT 0
#define PCM179X_ATLD_ENABLE (1 << 7)
static const struct reg_default pcm179x_reg_defaults[] = {
{ 0x10, 0xff },
{ 0x11, 0xff },
{ 0x12, 0x50 },
{ 0x13, 0x00 },
{ 0x14, 0x00 },
{ 0x15, 0x01 },
{ 0x16, 0x00 },
{ 0x17, 0x00 },
};
static bool pcm179x_accessible_reg(struct device *dev, unsigned int reg)
{
return reg >= 0x10 && reg <= 0x17;
}
static bool pcm179x_writeable_reg(struct device *dev, unsigned int reg)
{
bool accessible;
accessible = pcm179x_accessible_reg(dev, reg);
return accessible && reg != 0x16 && reg != 0x17;
}
struct pcm179x_private {
struct regmap *regmap;
unsigned int format;
unsigned int rate;
};
static int pcm179x_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int format)
{
struct snd_soc_component *component = codec_dai->component;
struct pcm179x_private *priv = snd_soc_component_get_drvdata(component);
priv->format = format;
return 0;
}
static int pcm179x_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
struct pcm179x_private *priv = snd_soc_component_get_drvdata(component);
int ret;
ret = regmap_update_bits(priv->regmap, PCM179X_SOFT_MUTE,
PCM179X_MUTE_MASK, !!mute);
if (ret < 0)
return ret;
return 0;
}
static int pcm179x_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct pcm179x_private *priv = snd_soc_component_get_drvdata(component);
int val = 0, ret;
priv->rate = params_rate(params);
switch (priv->format & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_RIGHT_J:
switch (params_width(params)) {
case 24:
case 32:
val = 2;
break;
case 16:
val = 0;
break;
default:
return -EINVAL;
}
break;
case SND_SOC_DAIFMT_I2S:
switch (params_width(params)) {
case 24:
case 32:
val = 5;
break;
case 16:
val = 4;
break;
default:
return -EINVAL;
}
break;
default:
dev_err(component->dev, "Invalid DAI format\n");
return -EINVAL;
}
val = val << PCM179X_FMT_SHIFT | PCM179X_ATLD_ENABLE;
ret = regmap_update_bits(priv->regmap, PCM179X_FMT_CONTROL,
PCM179X_FMT_MASK | PCM179X_ATLD_ENABLE, val);
if (ret < 0)
return ret;
return 0;
}
static const struct snd_soc_dai_ops pcm179x_dai_ops = {
.set_fmt = pcm179x_set_dai_fmt,
.hw_params = pcm179x_hw_params,
.mute_stream = pcm179x_mute,
.no_capture_mute = 1,
};
static const DECLARE_TLV_DB_SCALE(pcm179x_dac_tlv, -12000, 50, 1);
static const struct snd_kcontrol_new pcm179x_controls[] = {
SOC_DOUBLE_R_RANGE_TLV("DAC Playback Volume", PCM179X_DAC_VOL_LEFT,
PCM179X_DAC_VOL_RIGHT, 0, 0xf, 0xff, 0,
pcm179x_dac_tlv),
SOC_SINGLE("DAC Invert Output Switch", PCM179X_MODE_CONTROL, 7, 1, 0),
SOC_SINGLE("DAC Rolloff Filter Switch", PCM179X_MODE_CONTROL, 1, 1, 0),
};
static const struct snd_soc_dapm_widget pcm179x_dapm_widgets[] = {
SND_SOC_DAPM_OUTPUT("IOUTL+"),
SND_SOC_DAPM_OUTPUT("IOUTL-"),
SND_SOC_DAPM_OUTPUT("IOUTR+"),
SND_SOC_DAPM_OUTPUT("IOUTR-"),
};
static const struct snd_soc_dapm_route pcm179x_dapm_routes[] = {
{ "IOUTL+", NULL, "Playback" },
{ "IOUTL-", NULL, "Playback" },
{ "IOUTR+", NULL, "Playback" },
{ "IOUTR-", NULL, "Playback" },
};
static struct snd_soc_dai_driver pcm179x_dai = {
.name = "pcm179x-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.rate_min = 10000,
.rate_max = 200000,
.formats = PCM1792A_FORMATS, },
.ops = &pcm179x_dai_ops,
};
const struct regmap_config pcm179x_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = 23,
.reg_defaults = pcm179x_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(pcm179x_reg_defaults),
.writeable_reg = pcm179x_writeable_reg,
.readable_reg = pcm179x_accessible_reg,
};
EXPORT_SYMBOL_GPL(pcm179x_regmap_config);
static const struct snd_soc_component_driver soc_component_dev_pcm179x = {
.controls = pcm179x_controls,
.num_controls = ARRAY_SIZE(pcm179x_controls),
.dapm_widgets = pcm179x_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(pcm179x_dapm_widgets),
.dapm_routes = pcm179x_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(pcm179x_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
int pcm179x_common_init(struct device *dev, struct regmap *regmap)
{
struct pcm179x_private *pcm179x;
pcm179x = devm_kzalloc(dev, sizeof(struct pcm179x_private),
GFP_KERNEL);
if (!pcm179x)
return -ENOMEM;
pcm179x->regmap = regmap;
dev_set_drvdata(dev, pcm179x);
return devm_snd_soc_register_component(dev,
&soc_component_dev_pcm179x, &pcm179x_dai, 1);
}
EXPORT_SYMBOL_GPL(pcm179x_common_init);
MODULE_DESCRIPTION("ASoC PCM179X driver");
MODULE_AUTHOR("Michael Trimarchi <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/pcm179x.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8750.c -- WM8750 ALSA SoC audio driver
*
* Copyright 2005 Openedhand Ltd.
*
* Author: Richard Purdie <[email protected]>
*
* Based on WM8753.c
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <linux/of_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include "wm8750.h"
/*
* wm8750 register cache
* We can't read the WM8750 register space when we
* are using 2 wire for device control, so we cache them instead.
*/
static const struct reg_default wm8750_reg_defaults[] = {
{ 0, 0x0097 },
{ 1, 0x0097 },
{ 2, 0x0079 },
{ 3, 0x0079 },
{ 4, 0x0000 },
{ 5, 0x0008 },
{ 6, 0x0000 },
{ 7, 0x000a },
{ 8, 0x0000 },
{ 9, 0x0000 },
{ 10, 0x00ff },
{ 11, 0x00ff },
{ 12, 0x000f },
{ 13, 0x000f },
{ 14, 0x0000 },
{ 15, 0x0000 },
{ 16, 0x0000 },
{ 17, 0x007b },
{ 18, 0x0000 },
{ 19, 0x0032 },
{ 20, 0x0000 },
{ 21, 0x00c3 },
{ 22, 0x00c3 },
{ 23, 0x00c0 },
{ 24, 0x0000 },
{ 25, 0x0000 },
{ 26, 0x0000 },
{ 27, 0x0000 },
{ 28, 0x0000 },
{ 29, 0x0000 },
{ 30, 0x0000 },
{ 31, 0x0000 },
{ 32, 0x0000 },
{ 33, 0x0000 },
{ 34, 0x0050 },
{ 35, 0x0050 },
{ 36, 0x0050 },
{ 37, 0x0050 },
{ 38, 0x0050 },
{ 39, 0x0050 },
{ 40, 0x0079 },
{ 41, 0x0079 },
{ 42, 0x0079 },
};
/* codec private data */
struct wm8750_priv {
unsigned int sysclk;
};
#define wm8750_reset(c) snd_soc_component_write(c, WM8750_RESET, 0)
/*
* WM8750 Controls
*/
static const char *wm8750_bass[] = {"Linear Control", "Adaptive Boost"};
static const char *wm8750_bass_filter[] = { "130Hz @ 48kHz", "200Hz @ 48kHz" };
static const char *wm8750_treble[] = {"8kHz", "4kHz"};
static const char *wm8750_3d_lc[] = {"200Hz", "500Hz"};
static const char *wm8750_3d_uc[] = {"2.2kHz", "1.5kHz"};
static const char *wm8750_3d_func[] = {"Capture", "Playback"};
static const char *wm8750_alc_func[] = {"Off", "Right", "Left", "Stereo"};
static const char *wm8750_ng_type[] = {"Constant PGA Gain",
"Mute ADC Output"};
static const char *wm8750_line_mux[] = {"Line 1", "Line 2", "Line 3", "PGA",
"Differential"};
static const char *wm8750_pga_sel[] = {"Line 1", "Line 2", "Line 3",
"Differential"};
static const char *wm8750_out3[] = {"VREF", "ROUT1 + Vol", "MonoOut",
"ROUT1"};
static const char *wm8750_diff_sel[] = {"Line 1", "Line 2"};
static const char *wm8750_adcpol[] = {"Normal", "L Invert", "R Invert",
"L + R Invert"};
static const char *wm8750_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"};
static const char *wm8750_mono_mux[] = {"Stereo", "Mono (Left)",
"Mono (Right)", "Digital Mono"};
static const struct soc_enum wm8750_enum[] = {
SOC_ENUM_SINGLE(WM8750_BASS, 7, 2, wm8750_bass),
SOC_ENUM_SINGLE(WM8750_BASS, 6, 2, wm8750_bass_filter),
SOC_ENUM_SINGLE(WM8750_TREBLE, 6, 2, wm8750_treble),
SOC_ENUM_SINGLE(WM8750_3D, 5, 2, wm8750_3d_lc),
SOC_ENUM_SINGLE(WM8750_3D, 6, 2, wm8750_3d_uc),
SOC_ENUM_SINGLE(WM8750_3D, 7, 2, wm8750_3d_func),
SOC_ENUM_SINGLE(WM8750_ALC1, 7, 4, wm8750_alc_func),
SOC_ENUM_SINGLE(WM8750_NGATE, 1, 2, wm8750_ng_type),
SOC_ENUM_SINGLE(WM8750_LOUTM1, 0, 5, wm8750_line_mux),
SOC_ENUM_SINGLE(WM8750_ROUTM1, 0, 5, wm8750_line_mux),
SOC_ENUM_SINGLE(WM8750_LADCIN, 6, 4, wm8750_pga_sel), /* 10 */
SOC_ENUM_SINGLE(WM8750_RADCIN, 6, 4, wm8750_pga_sel),
SOC_ENUM_SINGLE(WM8750_ADCTL2, 7, 4, wm8750_out3),
SOC_ENUM_SINGLE(WM8750_ADCIN, 8, 2, wm8750_diff_sel),
SOC_ENUM_SINGLE(WM8750_ADCDAC, 5, 4, wm8750_adcpol),
SOC_ENUM_SINGLE(WM8750_ADCDAC, 1, 4, wm8750_deemph),
SOC_ENUM_SINGLE(WM8750_ADCIN, 6, 4, wm8750_mono_mux), /* 16 */
};
static const struct snd_kcontrol_new wm8750_snd_controls[] = {
SOC_DOUBLE_R("Capture Volume", WM8750_LINVOL, WM8750_RINVOL, 0, 63, 0),
SOC_DOUBLE_R("Capture ZC Switch", WM8750_LINVOL, WM8750_RINVOL, 6, 1, 0),
SOC_DOUBLE_R("Capture Switch", WM8750_LINVOL, WM8750_RINVOL, 7, 1, 1),
SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8750_LOUT1V,
WM8750_ROUT1V, 7, 1, 0),
SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8750_LOUT2V,
WM8750_ROUT2V, 7, 1, 0),
SOC_ENUM("Playback De-emphasis", wm8750_enum[15]),
SOC_ENUM("Capture Polarity", wm8750_enum[14]),
SOC_SINGLE("Playback 6dB Attenuate", WM8750_ADCDAC, 7, 1, 0),
SOC_SINGLE("Capture 6dB Attenuate", WM8750_ADCDAC, 8, 1, 0),
SOC_DOUBLE_R("PCM Volume", WM8750_LDAC, WM8750_RDAC, 0, 255, 0),
SOC_ENUM("Bass Boost", wm8750_enum[0]),
SOC_ENUM("Bass Filter", wm8750_enum[1]),
SOC_SINGLE("Bass Volume", WM8750_BASS, 0, 15, 1),
SOC_SINGLE("Treble Volume", WM8750_TREBLE, 0, 15, 1),
SOC_ENUM("Treble Cut-off", wm8750_enum[2]),
SOC_SINGLE("3D Switch", WM8750_3D, 0, 1, 0),
SOC_SINGLE("3D Volume", WM8750_3D, 1, 15, 0),
SOC_ENUM("3D Lower Cut-off", wm8750_enum[3]),
SOC_ENUM("3D Upper Cut-off", wm8750_enum[4]),
SOC_ENUM("3D Mode", wm8750_enum[5]),
SOC_SINGLE("ALC Capture Target Volume", WM8750_ALC1, 0, 7, 0),
SOC_SINGLE("ALC Capture Max Volume", WM8750_ALC1, 4, 7, 0),
SOC_ENUM("ALC Capture Function", wm8750_enum[6]),
SOC_SINGLE("ALC Capture ZC Switch", WM8750_ALC2, 7, 1, 0),
SOC_SINGLE("ALC Capture Hold Time", WM8750_ALC2, 0, 15, 0),
SOC_SINGLE("ALC Capture Decay Time", WM8750_ALC3, 4, 15, 0),
SOC_SINGLE("ALC Capture Attack Time", WM8750_ALC3, 0, 15, 0),
SOC_SINGLE("ALC Capture NG Threshold", WM8750_NGATE, 3, 31, 0),
SOC_ENUM("ALC Capture NG Type", wm8750_enum[4]),
SOC_SINGLE("ALC Capture NG Switch", WM8750_NGATE, 0, 1, 0),
SOC_SINGLE("Left ADC Capture Volume", WM8750_LADC, 0, 255, 0),
SOC_SINGLE("Right ADC Capture Volume", WM8750_RADC, 0, 255, 0),
SOC_SINGLE("ZC Timeout Switch", WM8750_ADCTL1, 0, 1, 0),
SOC_SINGLE("Playback Invert Switch", WM8750_ADCTL1, 1, 1, 0),
SOC_SINGLE("Right Speaker Playback Invert Switch", WM8750_ADCTL2, 4, 1, 0),
/* Unimplemented */
/* ADCDAC Bit 0 - ADCHPD */
/* ADCDAC Bit 4 - HPOR */
/* ADCTL1 Bit 2,3 - DATSEL */
/* ADCTL1 Bit 4,5 - DMONOMIX */
/* ADCTL1 Bit 6,7 - VSEL */
/* ADCTL2 Bit 2 - LRCM */
/* ADCTL2 Bit 3 - TRI */
/* ADCTL3 Bit 5 - HPFLREN */
/* ADCTL3 Bit 6 - VROI */
/* ADCTL3 Bit 7,8 - ADCLRM */
/* ADCIN Bit 4 - LDCM */
/* ADCIN Bit 5 - RDCM */
SOC_DOUBLE_R("Mic Boost", WM8750_LADCIN, WM8750_RADCIN, 4, 3, 0),
SOC_DOUBLE_R("Bypass Left Playback Volume", WM8750_LOUTM1,
WM8750_LOUTM2, 4, 7, 1),
SOC_DOUBLE_R("Bypass Right Playback Volume", WM8750_ROUTM1,
WM8750_ROUTM2, 4, 7, 1),
SOC_DOUBLE_R("Bypass Mono Playback Volume", WM8750_MOUTM1,
WM8750_MOUTM2, 4, 7, 1),
SOC_SINGLE("Mono Playback ZC Switch", WM8750_MOUTV, 7, 1, 0),
SOC_DOUBLE_R("Headphone Playback Volume", WM8750_LOUT1V, WM8750_ROUT1V,
0, 127, 0),
SOC_DOUBLE_R("Speaker Playback Volume", WM8750_LOUT2V, WM8750_ROUT2V,
0, 127, 0),
SOC_SINGLE("Mono Playback Volume", WM8750_MOUTV, 0, 127, 0),
};
/*
* DAPM Controls
*/
/* Left Mixer */
static const struct snd_kcontrol_new wm8750_left_mixer_controls[] = {
SOC_DAPM_SINGLE("Playback Switch", WM8750_LOUTM1, 8, 1, 0),
SOC_DAPM_SINGLE("Left Bypass Switch", WM8750_LOUTM1, 7, 1, 0),
SOC_DAPM_SINGLE("Right Playback Switch", WM8750_LOUTM2, 8, 1, 0),
SOC_DAPM_SINGLE("Right Bypass Switch", WM8750_LOUTM2, 7, 1, 0),
};
/* Right Mixer */
static const struct snd_kcontrol_new wm8750_right_mixer_controls[] = {
SOC_DAPM_SINGLE("Left Playback Switch", WM8750_ROUTM1, 8, 1, 0),
SOC_DAPM_SINGLE("Left Bypass Switch", WM8750_ROUTM1, 7, 1, 0),
SOC_DAPM_SINGLE("Playback Switch", WM8750_ROUTM2, 8, 1, 0),
SOC_DAPM_SINGLE("Right Bypass Switch", WM8750_ROUTM2, 7, 1, 0),
};
/* Mono Mixer */
static const struct snd_kcontrol_new wm8750_mono_mixer_controls[] = {
SOC_DAPM_SINGLE("Left Playback Switch", WM8750_MOUTM1, 8, 1, 0),
SOC_DAPM_SINGLE("Left Bypass Switch", WM8750_MOUTM1, 7, 1, 0),
SOC_DAPM_SINGLE("Right Playback Switch", WM8750_MOUTM2, 8, 1, 0),
SOC_DAPM_SINGLE("Right Bypass Switch", WM8750_MOUTM2, 7, 1, 0),
};
/* Left Line Mux */
static const struct snd_kcontrol_new wm8750_left_line_controls =
SOC_DAPM_ENUM("Route", wm8750_enum[8]);
/* Right Line Mux */
static const struct snd_kcontrol_new wm8750_right_line_controls =
SOC_DAPM_ENUM("Route", wm8750_enum[9]);
/* Left PGA Mux */
static const struct snd_kcontrol_new wm8750_left_pga_controls =
SOC_DAPM_ENUM("Route", wm8750_enum[10]);
/* Right PGA Mux */
static const struct snd_kcontrol_new wm8750_right_pga_controls =
SOC_DAPM_ENUM("Route", wm8750_enum[11]);
/* Out 3 Mux */
static const struct snd_kcontrol_new wm8750_out3_controls =
SOC_DAPM_ENUM("Route", wm8750_enum[12]);
/* Differential Mux */
static const struct snd_kcontrol_new wm8750_diffmux_controls =
SOC_DAPM_ENUM("Route", wm8750_enum[13]);
/* Mono ADC Mux */
static const struct snd_kcontrol_new wm8750_monomux_controls =
SOC_DAPM_ENUM("Route", wm8750_enum[16]);
static const struct snd_soc_dapm_widget wm8750_dapm_widgets[] = {
SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
&wm8750_left_mixer_controls[0],
ARRAY_SIZE(wm8750_left_mixer_controls)),
SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
&wm8750_right_mixer_controls[0],
ARRAY_SIZE(wm8750_right_mixer_controls)),
SND_SOC_DAPM_MIXER("Mono Mixer", WM8750_PWR2, 2, 0,
&wm8750_mono_mixer_controls[0],
ARRAY_SIZE(wm8750_mono_mixer_controls)),
SND_SOC_DAPM_PGA("Right Out 2", WM8750_PWR2, 3, 0, NULL, 0),
SND_SOC_DAPM_PGA("Left Out 2", WM8750_PWR2, 4, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Out 1", WM8750_PWR2, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA("Left Out 1", WM8750_PWR2, 6, 0, NULL, 0),
SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8750_PWR2, 7, 0),
SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8750_PWR2, 8, 0),
SND_SOC_DAPM_MICBIAS("Mic Bias", WM8750_PWR1, 1, 0),
SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8750_PWR1, 2, 0),
SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8750_PWR1, 3, 0),
SND_SOC_DAPM_MUX("Left PGA Mux", WM8750_PWR1, 5, 0,
&wm8750_left_pga_controls),
SND_SOC_DAPM_MUX("Right PGA Mux", WM8750_PWR1, 4, 0,
&wm8750_right_pga_controls),
SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
&wm8750_left_line_controls),
SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
&wm8750_right_line_controls),
SND_SOC_DAPM_MUX("Out3 Mux", SND_SOC_NOPM, 0, 0, &wm8750_out3_controls),
SND_SOC_DAPM_PGA("Out 3", WM8750_PWR2, 1, 0, NULL, 0),
SND_SOC_DAPM_PGA("Mono Out 1", WM8750_PWR2, 2, 0, NULL, 0),
SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
&wm8750_diffmux_controls),
SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
&wm8750_monomux_controls),
SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
&wm8750_monomux_controls),
SND_SOC_DAPM_OUTPUT("LOUT1"),
SND_SOC_DAPM_OUTPUT("ROUT1"),
SND_SOC_DAPM_OUTPUT("LOUT2"),
SND_SOC_DAPM_OUTPUT("ROUT2"),
SND_SOC_DAPM_OUTPUT("MONO1"),
SND_SOC_DAPM_OUTPUT("OUT3"),
SND_SOC_DAPM_VMID("VREF"),
SND_SOC_DAPM_INPUT("LINPUT1"),
SND_SOC_DAPM_INPUT("LINPUT2"),
SND_SOC_DAPM_INPUT("LINPUT3"),
SND_SOC_DAPM_INPUT("RINPUT1"),
SND_SOC_DAPM_INPUT("RINPUT2"),
SND_SOC_DAPM_INPUT("RINPUT3"),
};
static const struct snd_soc_dapm_route wm8750_dapm_routes[] = {
/* left mixer */
{"Left Mixer", "Playback Switch", "Left DAC"},
{"Left Mixer", "Left Bypass Switch", "Left Line Mux"},
{"Left Mixer", "Right Playback Switch", "Right DAC"},
{"Left Mixer", "Right Bypass Switch", "Right Line Mux"},
/* right mixer */
{"Right Mixer", "Left Playback Switch", "Left DAC"},
{"Right Mixer", "Left Bypass Switch", "Left Line Mux"},
{"Right Mixer", "Playback Switch", "Right DAC"},
{"Right Mixer", "Right Bypass Switch", "Right Line Mux"},
/* left out 1 */
{"Left Out 1", NULL, "Left Mixer"},
{"LOUT1", NULL, "Left Out 1"},
/* left out 2 */
{"Left Out 2", NULL, "Left Mixer"},
{"LOUT2", NULL, "Left Out 2"},
/* right out 1 */
{"Right Out 1", NULL, "Right Mixer"},
{"ROUT1", NULL, "Right Out 1"},
/* right out 2 */
{"Right Out 2", NULL, "Right Mixer"},
{"ROUT2", NULL, "Right Out 2"},
/* mono mixer */
{"Mono Mixer", "Left Playback Switch", "Left DAC"},
{"Mono Mixer", "Left Bypass Switch", "Left Line Mux"},
{"Mono Mixer", "Right Playback Switch", "Right DAC"},
{"Mono Mixer", "Right Bypass Switch", "Right Line Mux"},
/* mono out */
{"Mono Out 1", NULL, "Mono Mixer"},
{"MONO1", NULL, "Mono Out 1"},
/* out 3 */
{"Out3 Mux", "VREF", "VREF"},
{"Out3 Mux", "ROUT1 + Vol", "ROUT1"},
{"Out3 Mux", "ROUT1", "Right Mixer"},
{"Out3 Mux", "MonoOut", "MONO1"},
{"Out 3", NULL, "Out3 Mux"},
{"OUT3", NULL, "Out 3"},
/* Left Line Mux */
{"Left Line Mux", "Line 1", "LINPUT1"},
{"Left Line Mux", "Line 2", "LINPUT2"},
{"Left Line Mux", "Line 3", "LINPUT3"},
{"Left Line Mux", "PGA", "Left PGA Mux"},
{"Left Line Mux", "Differential", "Differential Mux"},
/* Right Line Mux */
{"Right Line Mux", "Line 1", "RINPUT1"},
{"Right Line Mux", "Line 2", "RINPUT2"},
{"Right Line Mux", "Line 3", "RINPUT3"},
{"Right Line Mux", "PGA", "Right PGA Mux"},
{"Right Line Mux", "Differential", "Differential Mux"},
/* Left PGA Mux */
{"Left PGA Mux", "Line 1", "LINPUT1"},
{"Left PGA Mux", "Line 2", "LINPUT2"},
{"Left PGA Mux", "Line 3", "LINPUT3"},
{"Left PGA Mux", "Differential", "Differential Mux"},
/* Right PGA Mux */
{"Right PGA Mux", "Line 1", "RINPUT1"},
{"Right PGA Mux", "Line 2", "RINPUT2"},
{"Right PGA Mux", "Line 3", "RINPUT3"},
{"Right PGA Mux", "Differential", "Differential Mux"},
/* Differential Mux */
{"Differential Mux", "Line 1", "LINPUT1"},
{"Differential Mux", "Line 1", "RINPUT1"},
{"Differential Mux", "Line 2", "LINPUT2"},
{"Differential Mux", "Line 2", "RINPUT2"},
/* Left ADC Mux */
{"Left ADC Mux", "Stereo", "Left PGA Mux"},
{"Left ADC Mux", "Mono (Left)", "Left PGA Mux"},
{"Left ADC Mux", "Digital Mono", "Left PGA Mux"},
/* Right ADC Mux */
{"Right ADC Mux", "Stereo", "Right PGA Mux"},
{"Right ADC Mux", "Mono (Right)", "Right PGA Mux"},
{"Right ADC Mux", "Digital Mono", "Right PGA Mux"},
/* ADC */
{"Left ADC", NULL, "Left ADC Mux"},
{"Right ADC", NULL, "Right ADC Mux"},
};
struct _coeff_div {
u32 mclk;
u32 rate;
u16 fs;
u8 sr:5;
u8 usb:1;
};
/* codec hifi mclk clock divider coefficients */
static const struct _coeff_div coeff_div[] = {
/* 8k */
{12288000, 8000, 1536, 0x6, 0x0},
{11289600, 8000, 1408, 0x16, 0x0},
{18432000, 8000, 2304, 0x7, 0x0},
{16934400, 8000, 2112, 0x17, 0x0},
{12000000, 8000, 1500, 0x6, 0x1},
/* 11.025k */
{11289600, 11025, 1024, 0x18, 0x0},
{16934400, 11025, 1536, 0x19, 0x0},
{12000000, 11025, 1088, 0x19, 0x1},
/* 16k */
{12288000, 16000, 768, 0xa, 0x0},
{18432000, 16000, 1152, 0xb, 0x0},
{12000000, 16000, 750, 0xa, 0x1},
/* 22.05k */
{11289600, 22050, 512, 0x1a, 0x0},
{16934400, 22050, 768, 0x1b, 0x0},
{12000000, 22050, 544, 0x1b, 0x1},
/* 32k */
{12288000, 32000, 384, 0xc, 0x0},
{18432000, 32000, 576, 0xd, 0x0},
{12000000, 32000, 375, 0xa, 0x1},
/* 44.1k */
{11289600, 44100, 256, 0x10, 0x0},
{16934400, 44100, 384, 0x11, 0x0},
{12000000, 44100, 272, 0x11, 0x1},
/* 48k */
{12288000, 48000, 256, 0x0, 0x0},
{18432000, 48000, 384, 0x1, 0x0},
{12000000, 48000, 250, 0x0, 0x1},
/* 88.2k */
{11289600, 88200, 128, 0x1e, 0x0},
{16934400, 88200, 192, 0x1f, 0x0},
{12000000, 88200, 136, 0x1f, 0x1},
/* 96k */
{12288000, 96000, 128, 0xe, 0x0},
{18432000, 96000, 192, 0xf, 0x0},
{12000000, 96000, 125, 0xe, 0x1},
};
static inline int get_coeff(int mclk, int rate)
{
int i;
for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
return i;
}
printk(KERN_ERR "wm8750: could not get coeff for mclk %d @ rate %d\n",
mclk, rate);
return -EINVAL;
}
static int wm8750_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct wm8750_priv *wm8750 = snd_soc_component_get_drvdata(component);
switch (freq) {
case 11289600:
case 12000000:
case 12288000:
case 16934400:
case 18432000:
wm8750->sysclk = freq;
return 0;
}
return -EINVAL;
}
static int wm8750_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
u16 iface = 0;
/* set master/slave audio interface */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
iface = 0x0040;
break;
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface |= 0x0002;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
iface |= 0x0001;
break;
case SND_SOC_DAIFMT_DSP_A:
iface |= 0x0003;
break;
case SND_SOC_DAIFMT_DSP_B:
iface |= 0x0013;
break;
default:
return -EINVAL;
}
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
iface |= 0x0090;
break;
case SND_SOC_DAIFMT_IB_NF:
iface |= 0x0080;
break;
case SND_SOC_DAIFMT_NB_IF:
iface |= 0x0010;
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, WM8750_IFACE, iface);
return 0;
}
static int wm8750_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm8750_priv *wm8750 = snd_soc_component_get_drvdata(component);
u16 iface = snd_soc_component_read(component, WM8750_IFACE) & 0x1f3;
u16 srate = snd_soc_component_read(component, WM8750_SRATE) & 0x1c0;
int coeff = get_coeff(wm8750->sysclk, params_rate(params));
/* bit size */
switch (params_width(params)) {
case 16:
break;
case 20:
iface |= 0x0004;
break;
case 24:
iface |= 0x0008;
break;
case 32:
iface |= 0x000c;
break;
}
/* set iface & srate */
snd_soc_component_write(component, WM8750_IFACE, iface);
if (coeff >= 0)
snd_soc_component_write(component, WM8750_SRATE, srate |
(coeff_div[coeff].sr << 1) | coeff_div[coeff].usb);
return 0;
}
static int wm8750_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
u16 mute_reg = snd_soc_component_read(component, WM8750_ADCDAC) & 0xfff7;
if (mute)
snd_soc_component_write(component, WM8750_ADCDAC, mute_reg | 0x8);
else
snd_soc_component_write(component, WM8750_ADCDAC, mute_reg);
return 0;
}
static int wm8750_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
u16 pwr_reg = snd_soc_component_read(component, WM8750_PWR1) & 0xfe3e;
switch (level) {
case SND_SOC_BIAS_ON:
/* set vmid to 50k and unmute dac */
snd_soc_component_write(component, WM8750_PWR1, pwr_reg | 0x00c0);
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
snd_soc_component_cache_sync(component);
/* Set VMID to 5k */
snd_soc_component_write(component, WM8750_PWR1, pwr_reg | 0x01c1);
/* ...and ramp */
msleep(1000);
}
/* mute dac and set vmid to 500k, enable VREF */
snd_soc_component_write(component, WM8750_PWR1, pwr_reg | 0x0141);
break;
case SND_SOC_BIAS_OFF:
snd_soc_component_write(component, WM8750_PWR1, 0x0001);
break;
}
return 0;
}
#define WM8750_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
#define WM8750_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE)
static const struct snd_soc_dai_ops wm8750_dai_ops = {
.hw_params = wm8750_pcm_hw_params,
.mute_stream = wm8750_mute,
.set_fmt = wm8750_set_dai_fmt,
.set_sysclk = wm8750_set_dai_sysclk,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver wm8750_dai = {
.name = "wm8750-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM8750_RATES,
.formats = WM8750_FORMATS,},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM8750_RATES,
.formats = WM8750_FORMATS,},
.ops = &wm8750_dai_ops,
};
static int wm8750_probe(struct snd_soc_component *component)
{
int ret;
ret = wm8750_reset(component);
if (ret < 0) {
printk(KERN_ERR "wm8750: failed to reset: %d\n", ret);
return ret;
}
/* set the update bits */
snd_soc_component_update_bits(component, WM8750_LDAC, 0x0100, 0x0100);
snd_soc_component_update_bits(component, WM8750_RDAC, 0x0100, 0x0100);
snd_soc_component_update_bits(component, WM8750_LOUT1V, 0x0100, 0x0100);
snd_soc_component_update_bits(component, WM8750_ROUT1V, 0x0100, 0x0100);
snd_soc_component_update_bits(component, WM8750_LOUT2V, 0x0100, 0x0100);
snd_soc_component_update_bits(component, WM8750_ROUT2V, 0x0100, 0x0100);
snd_soc_component_update_bits(component, WM8750_LINVOL, 0x0100, 0x0100);
snd_soc_component_update_bits(component, WM8750_RINVOL, 0x0100, 0x0100);
return ret;
}
static const struct snd_soc_component_driver soc_component_dev_wm8750 = {
.probe = wm8750_probe,
.set_bias_level = wm8750_set_bias_level,
.controls = wm8750_snd_controls,
.num_controls = ARRAY_SIZE(wm8750_snd_controls),
.dapm_widgets = wm8750_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8750_dapm_widgets),
.dapm_routes = wm8750_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(wm8750_dapm_routes),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct of_device_id wm8750_of_match[] = {
{ .compatible = "wlf,wm8750", },
{ .compatible = "wlf,wm8987", },
{ }
};
MODULE_DEVICE_TABLE(of, wm8750_of_match);
static const struct regmap_config wm8750_regmap = {
.reg_bits = 7,
.val_bits = 9,
.max_register = WM8750_MOUTV,
.reg_defaults = wm8750_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8750_reg_defaults),
.cache_type = REGCACHE_MAPLE,
};
#if defined(CONFIG_SPI_MASTER)
static int wm8750_spi_probe(struct spi_device *spi)
{
struct wm8750_priv *wm8750;
struct regmap *regmap;
int ret;
wm8750 = devm_kzalloc(&spi->dev, sizeof(struct wm8750_priv),
GFP_KERNEL);
if (wm8750 == NULL)
return -ENOMEM;
regmap = devm_regmap_init_spi(spi, &wm8750_regmap);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
spi_set_drvdata(spi, wm8750);
ret = devm_snd_soc_register_component(&spi->dev,
&soc_component_dev_wm8750, &wm8750_dai, 1);
return ret;
}
static const struct spi_device_id wm8750_spi_ids[] = {
{ "wm8750", 0 },
{ "wm8987", 0 },
{ },
};
MODULE_DEVICE_TABLE(spi, wm8750_spi_ids);
static struct spi_driver wm8750_spi_driver = {
.driver = {
.name = "wm8750",
.of_match_table = wm8750_of_match,
},
.id_table = wm8750_spi_ids,
.probe = wm8750_spi_probe,
};
#endif /* CONFIG_SPI_MASTER */
#if IS_ENABLED(CONFIG_I2C)
static int wm8750_i2c_probe(struct i2c_client *i2c)
{
struct wm8750_priv *wm8750;
struct regmap *regmap;
int ret;
wm8750 = devm_kzalloc(&i2c->dev, sizeof(struct wm8750_priv),
GFP_KERNEL);
if (wm8750 == NULL)
return -ENOMEM;
i2c_set_clientdata(i2c, wm8750);
regmap = devm_regmap_init_i2c(i2c, &wm8750_regmap);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_wm8750, &wm8750_dai, 1);
return ret;
}
static const struct i2c_device_id wm8750_i2c_id[] = {
{ "wm8750", 0 },
{ "wm8987", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8750_i2c_id);
static struct i2c_driver wm8750_i2c_driver = {
.driver = {
.name = "wm8750",
.of_match_table = wm8750_of_match,
},
.probe = wm8750_i2c_probe,
.id_table = wm8750_i2c_id,
};
#endif
static int __init wm8750_modinit(void)
{
int ret = 0;
#if IS_ENABLED(CONFIG_I2C)
ret = i2c_add_driver(&wm8750_i2c_driver);
if (ret != 0) {
printk(KERN_ERR "Failed to register wm8750 I2C driver: %d\n",
ret);
}
#endif
#if defined(CONFIG_SPI_MASTER)
ret = spi_register_driver(&wm8750_spi_driver);
if (ret != 0) {
printk(KERN_ERR "Failed to register wm8750 SPI driver: %d\n",
ret);
}
#endif
return ret;
}
module_init(wm8750_modinit);
static void __exit wm8750_exit(void)
{
#if IS_ENABLED(CONFIG_I2C)
i2c_del_driver(&wm8750_i2c_driver);
#endif
#if defined(CONFIG_SPI_MASTER)
spi_unregister_driver(&wm8750_spi_driver);
#endif
}
module_exit(wm8750_exit);
MODULE_DESCRIPTION("ASoC WM8750 driver");
MODULE_AUTHOR("Liam Girdwood");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8750.c |
// SPDX-License-Identifier: GPL-2.0
//
// mt6351.c -- mt6351 ALSA SoC audio codec driver
//
// Copyright (c) 2018 MediaTek Inc.
// Author: KaiChieh Chuang <[email protected]>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/delay.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include "mt6351.h"
/* MT6351_TOP_CLKSQ */
#define RG_CLKSQ_EN_AUD_BIT (0)
/* MT6351_TOP_CKPDN_CON0 */
#define RG_AUDNCP_CK_PDN_BIT (12)
#define RG_AUDIF_CK_PDN_BIT (13)
#define RG_AUD_CK_PDN_BIT (14)
#define RG_ZCD13M_CK_PDN_BIT (15)
/* MT6351_AUDDEC_ANA_CON0 */
#define RG_AUDDACLPWRUP_VAUDP32_BIT (0)
#define RG_AUDDACRPWRUP_VAUDP32_BIT (1)
#define RG_AUD_DAC_PWR_UP_VA32_BIT (2)
#define RG_AUD_DAC_PWL_UP_VA32_BIT (3)
#define RG_AUDHSPWRUP_VAUDP32_BIT (4)
#define RG_AUDHPLPWRUP_VAUDP32_BIT (5)
#define RG_AUDHPRPWRUP_VAUDP32_BIT (6)
#define RG_AUDHSMUXINPUTSEL_VAUDP32_SFT (7)
#define RG_AUDHSMUXINPUTSEL_VAUDP32_MASK (0x3)
#define RG_AUDHPLMUXINPUTSEL_VAUDP32_SFT (9)
#define RG_AUDHPLMUXINPUTSEL_VAUDP32_MASK (0x3)
#define RG_AUDHPRMUXINPUTSEL_VAUDP32_SFT (11)
#define RG_AUDHPRMUXINPUTSEL_VAUDP32_MASK (0x3)
#define RG_AUDHSSCDISABLE_VAUDP32 (13)
#define RG_AUDHPLSCDISABLE_VAUDP32_BIT (14)
#define RG_AUDHPRSCDISABLE_VAUDP32_BIT (15)
/* MT6351_AUDDEC_ANA_CON1 */
#define RG_HSOUTPUTSTBENH_VAUDP32_BIT (8)
/* MT6351_AUDDEC_ANA_CON3 */
#define RG_AUDLOLPWRUP_VAUDP32_BIT (2)
#define RG_AUDLOLMUXINPUTSEL_VAUDP32_SFT (3)
#define RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK (0x3)
#define RG_AUDLOLSCDISABLE_VAUDP32_BIT (5)
#define RG_LOOUTPUTSTBENH_VAUDP32_BIT (9)
/* MT6351_AUDDEC_ANA_CON6 */
#define RG_ABIDEC_RSVD0_VAUDP32_HPL_BIT (8)
#define RG_ABIDEC_RSVD0_VAUDP32_HPR_BIT (9)
#define RG_ABIDEC_RSVD0_VAUDP32_HS_BIT (10)
#define RG_ABIDEC_RSVD0_VAUDP32_LOL_BIT (11)
/* MT6351_AUDDEC_ANA_CON9 */
#define RG_AUDIBIASPWRDN_VAUDP32_BIT (8)
#define RG_RSTB_DECODER_VA32_BIT (9)
#define RG_AUDGLB_PWRDN_VA32_BIT (12)
#define RG_LCLDO_DEC_EN_VA32_BIT (13)
#define RG_LCLDO_DEC_REMOTE_SENSE_VA18_BIT (15)
/* MT6351_AUDDEC_ANA_CON10 */
#define RG_NVREG_EN_VAUDP32_BIT (8)
#define RG_AUDGLB_LP2_VOW_EN_VA32 10
/* MT6351_AFE_UL_DL_CON0 */
#define RG_AFE_ON_BIT (0)
/* MT6351_AFE_DL_SRC2_CON0_L */
#define RG_DL_2_SRC_ON_TMP_CTL_PRE_BIT (0)
/* MT6351_AFE_UL_SRC_CON0_L */
#define UL_SRC_ON_TMP_CTL (0)
/* MT6351_AFE_TOP_CON0 */
#define RG_DL_SINE_ON_SFT (0)
#define RG_DL_SINE_ON_MASK (0x1)
#define RG_UL_SINE_ON_SFT (1)
#define RG_UL_SINE_ON_MASK (0x1)
/* MT6351_AUDIO_TOP_CON0 */
#define AUD_TOP_PDN_RESERVED_BIT 0
#define AUD_TOP_PWR_CLK_DIS_CTL_BIT 2
#define AUD_TOP_PDN_ADC_CTL_BIT 5
#define AUD_TOP_PDN_DAC_CTL_BIT 6
#define AUD_TOP_PDN_AFE_CTL_BIT 7
/* MT6351_AFE_SGEN_CFG0 */
#define SGEN_C_MUTE_SW_CTL_BIT 6
#define SGEN_C_DAC_EN_CTL_BIT 7
/* MT6351_AFE_NCP_CFG0 */
#define RG_NCP_ON_BIT 0
/* MT6351_LDO_VUSB33_CON0 */
#define RG_VUSB33_EN 1
#define RG_VUSB33_ON_CTRL 3
/* MT6351_LDO_VA18_CON0 */
#define RG_VA18_EN 1
#define RG_VA18_ON_CTRL 3
/* MT6351_AUDENC_ANA_CON0 */
#define RG_AUDPREAMPLON 0
#define RG_AUDPREAMPLDCCEN 1
#define RG_AUDPREAMPLDCPRECHARGE 2
#define RG_AUDPREAMPLINPUTSEL_SFT (4)
#define RG_AUDPREAMPLINPUTSEL_MASK (0x3)
#define RG_AUDADCLPWRUP 12
#define RG_AUDADCLINPUTSEL_SFT (13)
#define RG_AUDADCLINPUTSEL_MASK (0x3)
/* MT6351_AUDENC_ANA_CON1 */
#define RG_AUDPREAMPRON 0
#define RG_AUDPREAMPRDCCEN 1
#define RG_AUDPREAMPRDCPRECHARGE 2
#define RG_AUDPREAMPRINPUTSEL_SFT (4)
#define RG_AUDPREAMPRINPUTSEL_MASK (0x3)
#define RG_AUDADCRPWRUP 12
#define RG_AUDADCRINPUTSEL_SFT (13)
#define RG_AUDADCRINPUTSEL_MASK (0x3)
/* MT6351_AUDENC_ANA_CON3 */
#define RG_AUDADCCLKRSTB 6
/* MT6351_AUDENC_ANA_CON9 */
#define RG_AUDPWDBMICBIAS0 0
#define RG_AUDMICBIAS0VREF 4
#define RG_AUDMICBIAS0LOWPEN 7
#define RG_AUDPWDBMICBIAS2 8
#define RG_AUDMICBIAS2VREF 12
#define RG_AUDMICBIAS2LOWPEN 15
/* MT6351_AUDENC_ANA_CON10 */
#define RG_AUDPWDBMICBIAS1 0
#define RG_AUDMICBIAS1DCSW1NEN 2
#define RG_AUDMICBIAS1VREF 4
#define RG_AUDMICBIAS1LOWPEN 7
enum {
AUDIO_ANALOG_VOLUME_HSOUTL,
AUDIO_ANALOG_VOLUME_HSOUTR,
AUDIO_ANALOG_VOLUME_HPOUTL,
AUDIO_ANALOG_VOLUME_HPOUTR,
AUDIO_ANALOG_VOLUME_LINEOUTL,
AUDIO_ANALOG_VOLUME_LINEOUTR,
AUDIO_ANALOG_VOLUME_MICAMP1,
AUDIO_ANALOG_VOLUME_MICAMP2,
AUDIO_ANALOG_VOLUME_TYPE_MAX
};
/* Supply subseq */
enum {
SUPPLY_SUBSEQ_SETTING,
SUPPLY_SUBSEQ_ENABLE,
SUPPLY_SUBSEQ_MICBIAS,
};
#define REG_STRIDE 2
struct mt6351_priv {
struct device *dev;
struct regmap *regmap;
unsigned int dl_rate;
unsigned int ul_rate;
int ana_gain[AUDIO_ANALOG_VOLUME_TYPE_MAX];
int hp_en_counter;
};
static void set_hp_gain_zero(struct snd_soc_component *cmpnt)
{
regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON2,
0x1f << 7, 0x8 << 7);
regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON2,
0x1f << 0, 0x8 << 0);
}
static unsigned int get_cap_reg_val(struct snd_soc_component *cmpnt,
unsigned int rate)
{
switch (rate) {
case 8000:
return 0;
case 16000:
return 1;
case 32000:
return 2;
case 48000:
return 3;
case 96000:
return 4;
case 192000:
return 5;
default:
dev_warn(cmpnt->dev, "%s(), error rate %d, return 3",
__func__, rate);
return 3;
}
}
static unsigned int get_play_reg_val(struct snd_soc_component *cmpnt,
unsigned int rate)
{
switch (rate) {
case 8000:
return 0;
case 11025:
return 1;
case 12000:
return 2;
case 16000:
return 3;
case 22050:
return 4;
case 24000:
return 5;
case 32000:
return 6;
case 44100:
return 7;
case 48000:
case 96000:
case 192000:
return 8;
default:
dev_warn(cmpnt->dev, "%s(), error rate %d, return 8",
__func__, rate);
return 8;
}
}
static int mt6351_codec_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *cmpnt = dai->component;
struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt);
unsigned int rate = params_rate(params);
dev_dbg(priv->dev, "%s(), substream->stream %d, rate %d\n",
__func__, substream->stream, rate);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
priv->dl_rate = rate;
else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
priv->ul_rate = rate;
return 0;
}
static const struct snd_soc_dai_ops mt6351_codec_dai_ops = {
.hw_params = mt6351_codec_dai_hw_params,
};
#define MT6351_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_U24_LE |\
SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_U32_LE)
static struct snd_soc_dai_driver mt6351_dai_driver[] = {
{
.name = "mt6351-snd-codec-aif1",
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000 |
SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = MT6351_FORMATS,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_32000 |
SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = MT6351_FORMATS,
},
.ops = &mt6351_codec_dai_ops,
},
};
enum {
HP_GAIN_SET_ZERO,
HP_GAIN_RESTORE,
};
static void hp_gain_ramp_set(struct snd_soc_component *cmpnt, int hp_gain_ctl)
{
struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt);
int idx, old_idx, offset, reg_idx;
if (hp_gain_ctl == HP_GAIN_SET_ZERO) {
idx = 8; /* 0dB */
old_idx = priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL];
} else {
idx = priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL];
old_idx = 8; /* 0dB */
}
dev_dbg(priv->dev, "%s(), idx %d, old_idx %d\n",
__func__, idx, old_idx);
if (idx > old_idx)
offset = idx - old_idx;
else
offset = old_idx - idx;
reg_idx = old_idx;
while (offset > 0) {
reg_idx = idx > old_idx ? reg_idx + 1 : reg_idx - 1;
/* check valid range, and set value */
if ((reg_idx >= 0 && reg_idx <= 0x12) || reg_idx == 0x1f) {
regmap_update_bits(cmpnt->regmap,
MT6351_ZCD_CON2,
0xf9f,
(reg_idx << 7) | reg_idx);
usleep_range(100, 120);
}
offset--;
}
}
static void hp_zcd_enable(struct snd_soc_component *cmpnt)
{
/* Enable ZCD, for minimize pop noise */
/* when adjust gain during HP buffer on */
regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x7 << 8, 0x1 << 8);
regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x1 << 7, 0x0 << 7);
/* timeout, 1=5ms, 0=30ms */
regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x1 << 6, 0x1 << 6);
regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x3 << 4, 0x0 << 4);
regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x7 << 1, 0x5 << 1);
regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x1 << 0, 0x1 << 0);
}
static void hp_zcd_disable(struct snd_soc_component *cmpnt)
{
regmap_write(cmpnt->regmap, MT6351_ZCD_CON0, 0x0000);
}
static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0);
static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 600, 0);
static const struct snd_kcontrol_new mt6351_snd_controls[] = {
/* dl pga gain */
SOC_DOUBLE_TLV("Headphone Volume",
MT6351_ZCD_CON2, 0, 7, 0x12, 1,
playback_tlv),
SOC_DOUBLE_TLV("Lineout Volume",
MT6351_ZCD_CON1, 0, 7, 0x12, 1,
playback_tlv),
SOC_SINGLE_TLV("Handset Volume",
MT6351_ZCD_CON3, 0, 0x12, 1,
playback_tlv),
/* ul pga gain */
SOC_DOUBLE_R_TLV("PGA Volume",
MT6351_AUDENC_ANA_CON0, MT6351_AUDENC_ANA_CON1,
8, 4, 0,
pga_tlv),
};
/* MUX */
/* LOL MUX */
static const char *const lo_in_mux_map[] = {
"Open", "Mute", "Playback", "Test Mode",
};
static int lo_in_mux_map_value[] = {
0x0, 0x1, 0x2, 0x3,
};
static SOC_VALUE_ENUM_SINGLE_DECL(lo_in_mux_map_enum,
MT6351_AUDDEC_ANA_CON3,
RG_AUDLOLMUXINPUTSEL_VAUDP32_SFT,
RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK,
lo_in_mux_map,
lo_in_mux_map_value);
static const struct snd_kcontrol_new lo_in_mux_control =
SOC_DAPM_ENUM("In Select", lo_in_mux_map_enum);
/*HP MUX */
static const char *const hp_in_mux_map[] = {
"Open", "LoudSPK Playback", "Audio Playback", "Test Mode",
};
static int hp_in_mux_map_value[] = {
0x0, 0x1, 0x2, 0x3,
};
static SOC_VALUE_ENUM_SINGLE_DECL(hpl_in_mux_map_enum,
MT6351_AUDDEC_ANA_CON0,
RG_AUDHPLMUXINPUTSEL_VAUDP32_SFT,
RG_AUDHPLMUXINPUTSEL_VAUDP32_MASK,
hp_in_mux_map,
hp_in_mux_map_value);
static const struct snd_kcontrol_new hpl_in_mux_control =
SOC_DAPM_ENUM("HPL Select", hpl_in_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(hpr_in_mux_map_enum,
MT6351_AUDDEC_ANA_CON0,
RG_AUDHPRMUXINPUTSEL_VAUDP32_SFT,
RG_AUDHPRMUXINPUTSEL_VAUDP32_MASK,
hp_in_mux_map,
hp_in_mux_map_value);
static const struct snd_kcontrol_new hpr_in_mux_control =
SOC_DAPM_ENUM("HPR Select", hpr_in_mux_map_enum);
/* RCV MUX */
static const char *const rcv_in_mux_map[] = {
"Open", "Mute", "Voice Playback", "Test Mode",
};
static int rcv_in_mux_map_value[] = {
0x0, 0x1, 0x2, 0x3,
};
static SOC_VALUE_ENUM_SINGLE_DECL(rcv_in_mux_map_enum,
MT6351_AUDDEC_ANA_CON0,
RG_AUDHSMUXINPUTSEL_VAUDP32_SFT,
RG_AUDHSMUXINPUTSEL_VAUDP32_MASK,
rcv_in_mux_map,
rcv_in_mux_map_value);
static const struct snd_kcontrol_new rcv_in_mux_control =
SOC_DAPM_ENUM("RCV Select", rcv_in_mux_map_enum);
/* DAC In MUX */
static const char *const dac_in_mux_map[] = {
"Normal Path", "Sgen",
};
static int dac_in_mux_map_value[] = {
0x0, 0x1,
};
static SOC_VALUE_ENUM_SINGLE_DECL(dac_in_mux_map_enum,
MT6351_AFE_TOP_CON0,
RG_DL_SINE_ON_SFT,
RG_DL_SINE_ON_MASK,
dac_in_mux_map,
dac_in_mux_map_value);
static const struct snd_kcontrol_new dac_in_mux_control =
SOC_DAPM_ENUM("DAC Select", dac_in_mux_map_enum);
/* AIF Out MUX */
static SOC_VALUE_ENUM_SINGLE_DECL(aif_out_mux_map_enum,
MT6351_AFE_TOP_CON0,
RG_UL_SINE_ON_SFT,
RG_UL_SINE_ON_MASK,
dac_in_mux_map,
dac_in_mux_map_value);
static const struct snd_kcontrol_new aif_out_mux_control =
SOC_DAPM_ENUM("AIF Out Select", aif_out_mux_map_enum);
/* ADC L MUX */
static const char *const adc_left_mux_map[] = {
"Idle", "AIN0", "Left Preamplifier", "Idle_1",
};
static int adc_left_mux_map_value[] = {
0x0, 0x1, 0x2, 0x3,
};
static SOC_VALUE_ENUM_SINGLE_DECL(adc_left_mux_map_enum,
MT6351_AUDENC_ANA_CON0,
RG_AUDADCLINPUTSEL_SFT,
RG_AUDADCLINPUTSEL_MASK,
adc_left_mux_map,
adc_left_mux_map_value);
static const struct snd_kcontrol_new adc_left_mux_control =
SOC_DAPM_ENUM("ADC L Select", adc_left_mux_map_enum);
/* ADC R MUX */
static const char *const adc_right_mux_map[] = {
"Idle", "AIN0", "Right Preamplifier", "Idle_1",
};
static int adc_right_mux_map_value[] = {
0x0, 0x1, 0x2, 0x3,
};
static SOC_VALUE_ENUM_SINGLE_DECL(adc_right_mux_map_enum,
MT6351_AUDENC_ANA_CON1,
RG_AUDADCRINPUTSEL_SFT,
RG_AUDADCRINPUTSEL_MASK,
adc_right_mux_map,
adc_right_mux_map_value);
static const struct snd_kcontrol_new adc_right_mux_control =
SOC_DAPM_ENUM("ADC R Select", adc_right_mux_map_enum);
/* PGA L MUX */
static const char *const pga_left_mux_map[] = {
"None", "AIN0", "AIN1", "AIN2",
};
static int pga_left_mux_map_value[] = {
0x0, 0x1, 0x2, 0x3,
};
static SOC_VALUE_ENUM_SINGLE_DECL(pga_left_mux_map_enum,
MT6351_AUDENC_ANA_CON0,
RG_AUDPREAMPLINPUTSEL_SFT,
RG_AUDPREAMPLINPUTSEL_MASK,
pga_left_mux_map,
pga_left_mux_map_value);
static const struct snd_kcontrol_new pga_left_mux_control =
SOC_DAPM_ENUM("PGA L Select", pga_left_mux_map_enum);
/* PGA R MUX */
static const char *const pga_right_mux_map[] = {
"None", "AIN0", "AIN3", "AIN2",
};
static int pga_right_mux_map_value[] = {
0x0, 0x1, 0x2, 0x3,
};
static SOC_VALUE_ENUM_SINGLE_DECL(pga_right_mux_map_enum,
MT6351_AUDENC_ANA_CON1,
RG_AUDPREAMPRINPUTSEL_SFT,
RG_AUDPREAMPRINPUTSEL_MASK,
pga_right_mux_map,
pga_right_mux_map_value);
static const struct snd_kcontrol_new pga_right_mux_control =
SOC_DAPM_ENUM("PGA R Select", pga_right_mux_map_enum);
static int mt_reg_set_clr_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
if (w->on_val) {
/* SET REG */
regmap_update_bits(cmpnt->regmap,
w->reg + REG_STRIDE,
0x1 << w->shift,
0x1 << w->shift);
} else {
/* CLR REG */
regmap_update_bits(cmpnt->regmap,
w->reg + REG_STRIDE * 2,
0x1 << w->shift,
0x1 << w->shift);
}
break;
case SND_SOC_DAPM_PRE_PMD:
if (w->off_val) {
/* SET REG */
regmap_update_bits(cmpnt->regmap,
w->reg + REG_STRIDE,
0x1 << w->shift,
0x1 << w->shift);
} else {
/* CLR REG */
regmap_update_bits(cmpnt->regmap,
w->reg + REG_STRIDE * 2,
0x1 << w->shift,
0x1 << w->shift);
}
break;
default:
break;
}
return 0;
}
static int mt_ncp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
regmap_update_bits(cmpnt->regmap, MT6351_AFE_NCP_CFG1,
0xffff, 0x1515);
/* NCP: ck1 and ck2 clock frequecy adjust configure */
regmap_update_bits(cmpnt->regmap, MT6351_AFE_NCP_CFG0,
0xfffe, 0x8C00);
break;
case SND_SOC_DAPM_POST_PMU:
usleep_range(250, 270);
break;
default:
break;
}
return 0;
}
static int mt_sgen_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
regmap_update_bits(cmpnt->regmap, MT6351_AFE_SGEN_CFG0,
0xffef, 0x0008);
regmap_update_bits(cmpnt->regmap, MT6351_AFE_SGEN_CFG1,
0xffff, 0x0101);
break;
default:
break;
}
return 0;
}
static int mt_aif_in_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt);
dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n",
__func__, event, priv->dl_rate);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* sdm audio fifo clock power on */
regmap_update_bits(cmpnt->regmap, MT6351_AFUNC_AUD_CON2,
0xffff, 0x0006);
/* scrambler clock on enable */
regmap_update_bits(cmpnt->regmap, MT6351_AFUNC_AUD_CON0,
0xffff, 0xC3A1);
/* sdm power on */
regmap_update_bits(cmpnt->regmap, MT6351_AFUNC_AUD_CON2,
0xffff, 0x0003);
/* sdm fifo enable */
regmap_update_bits(cmpnt->regmap, MT6351_AFUNC_AUD_CON2,
0xffff, 0x000B);
/* set attenuation gain */
regmap_update_bits(cmpnt->regmap, MT6351_AFE_DL_SDM_CON1,
0xffff, 0x001E);
regmap_write(cmpnt->regmap, MT6351_AFE_PMIC_NEWIF_CFG0,
(get_play_reg_val(cmpnt, priv->dl_rate) << 12) |
0x330);
regmap_write(cmpnt->regmap, MT6351_AFE_DL_SRC2_CON0_H,
(get_play_reg_val(cmpnt, priv->dl_rate) << 12) |
0x300);
regmap_update_bits(cmpnt->regmap, MT6351_AFE_PMIC_NEWIF_CFG2,
0x8000, 0x8000);
break;
default:
break;
}
return 0;
}
static int mt_hp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt);
int reg;
dev_dbg(priv->dev, "%s(), event 0x%x, hp_en_counter %d\n",
__func__, event, priv->hp_en_counter);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
priv->hp_en_counter++;
if (priv->hp_en_counter > 1)
break; /* already enabled, do nothing */
else if (priv->hp_en_counter <= 0)
dev_err(priv->dev, "%s(), hp_en_counter %d <= 0\n",
__func__,
priv->hp_en_counter);
hp_zcd_disable(cmpnt);
/* from yoyo HQA script */
regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON6,
0x0700, 0x0700);
/* save target gain to restore after hardware open complete */
regmap_read(cmpnt->regmap, MT6351_ZCD_CON2, ®);
priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] = reg & 0x1f;
priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] = (reg >> 7) & 0x1f;
/* Set HPR/HPL gain as minimum (~ -40dB) */
regmap_update_bits(cmpnt->regmap,
MT6351_ZCD_CON2, 0xffff, 0x0F9F);
/* Set HS gain as minimum (~ -40dB) */
regmap_update_bits(cmpnt->regmap,
MT6351_ZCD_CON3, 0xffff, 0x001F);
/* De_OSC of HP */
regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON2,
0x0001, 0x0001);
/* enable output STBENH */
regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON1,
0xffff, 0x2000);
/* De_OSC of voice, enable output STBENH */
regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON1,
0xffff, 0x2100);
/* Enable voice driver */
regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON0,
0x0010, 0xE090);
/* Enable pre-charge buffer */
regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON1,
0xffff, 0x2140);
usleep_range(50, 60);
/* Apply digital DC compensation value to DAC */
set_hp_gain_zero(cmpnt);
/* Enable HPR/HPL */
regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON1,
0xffff, 0x2100);
/* Disable pre-charge buffer */
regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON1,
0xffff, 0x2000);
/* Disable De_OSC of voice */
regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON0,
0x0010, 0xF4EF);
/* Disable voice buffer */
/* from yoyo HQ */
regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON6,
0x0700, 0x0300);
/* Enable ZCD, for minimize pop noise */
/* when adjust gain during HP buffer on */
hp_zcd_enable(cmpnt);
/* apply volume setting */
hp_gain_ramp_set(cmpnt, HP_GAIN_RESTORE);
break;
case SND_SOC_DAPM_PRE_PMD:
priv->hp_en_counter--;
if (priv->hp_en_counter > 0)
break; /* still being used, don't close */
else if (priv->hp_en_counter < 0)
dev_err(priv->dev, "%s(), hp_en_counter %d <= 0\n",
__func__,
priv->hp_en_counter);
/* Disable AUD_ZCD */
hp_zcd_disable(cmpnt);
/* Set HPR/HPL gain as -1dB, step by step */
hp_gain_ramp_set(cmpnt, HP_GAIN_SET_ZERO);
set_hp_gain_zero(cmpnt);
break;
case SND_SOC_DAPM_POST_PMD:
if (priv->hp_en_counter > 0)
break; /* still being used, don't close */
else if (priv->hp_en_counter < 0)
dev_err(priv->dev, "%s(), hp_en_counter %d <= 0\n",
__func__,
priv->hp_en_counter);
/* reset*/
regmap_update_bits(cmpnt->regmap,
MT6351_AUDDEC_ANA_CON6,
0x0700,
0x0000);
/* De_OSC of HP */
regmap_update_bits(cmpnt->regmap,
MT6351_AUDDEC_ANA_CON2,
0x0001,
0x0000);
/* apply volume setting */
hp_gain_ramp_set(cmpnt, HP_GAIN_RESTORE);
break;
default:
break;
}
return 0;
}
static int mt_aif_out_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt);
dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n",
__func__, event, priv->ul_rate);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* dcclk_div=11'b00100000011, dcclk_ref_ck_sel=2'b00 */
regmap_update_bits(cmpnt->regmap, MT6351_AFE_DCCLK_CFG0,
0xffff, 0x2062);
/* dcclk_pdn=1'b0 */
regmap_update_bits(cmpnt->regmap, MT6351_AFE_DCCLK_CFG0,
0xffff, 0x2060);
/* dcclk_gen_on=1'b1 */
regmap_update_bits(cmpnt->regmap, MT6351_AFE_DCCLK_CFG0,
0xffff, 0x2061);
/* UL sample rate and mode configure */
regmap_update_bits(cmpnt->regmap, MT6351_AFE_UL_SRC_CON0_H,
0x000E,
get_cap_reg_val(cmpnt, priv->ul_rate) << 1);
/* fixed 260k path for 8/16/32/48 */
if (priv->ul_rate <= 48000) {
/* anc ul path src on */
regmap_update_bits(cmpnt->regmap,
MT6351_AFE_HPANC_CFG0,
0x1 << 1,
0x1 << 1);
/* ANC clk pdn release */
regmap_update_bits(cmpnt->regmap,
MT6351_AFE_HPANC_CFG0,
0x1 << 0,
0x0 << 0);
}
break;
case SND_SOC_DAPM_PRE_PMD:
/* fixed 260k path for 8/16/32/48 */
if (priv->ul_rate <= 48000) {
/* anc ul path src on */
regmap_update_bits(cmpnt->regmap,
MT6351_AFE_HPANC_CFG0,
0x1 << 1,
0x0 << 1);
/* ANC clk pdn release */
regmap_update_bits(cmpnt->regmap,
MT6351_AFE_HPANC_CFG0,
0x1 << 0,
0x1 << 0);
}
break;
default:
break;
}
return 0;
}
static int mt_adc_clkgen_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* Audio ADC clock gen. mode: 00_divided by 2 (Normal) */
regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON3,
0x3 << 4, 0x0);
break;
case SND_SOC_DAPM_POST_PMU:
/* ADC CLK from: 00_13MHz from CLKSQ (Default) */
regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON3,
0x3 << 2, 0x0);
break;
default:
break;
}
return 0;
}
static int mt_pga_left_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* Audio L PGA precharge on */
regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON0,
0x3 << RG_AUDPREAMPLDCPRECHARGE,
0x1 << RG_AUDPREAMPLDCPRECHARGE);
/* Audio L PGA mode: 1_DCC */
regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON0,
0x3 << RG_AUDPREAMPLDCCEN,
0x1 << RG_AUDPREAMPLDCCEN);
break;
case SND_SOC_DAPM_POST_PMU:
usleep_range(100, 120);
/* Audio L PGA precharge off */
regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON0,
0x3 << RG_AUDPREAMPLDCPRECHARGE,
0x0 << RG_AUDPREAMPLDCPRECHARGE);
break;
default:
break;
}
return 0;
}
static int mt_pga_right_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* Audio R PGA precharge on */
regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON1,
0x3 << RG_AUDPREAMPRDCPRECHARGE,
0x1 << RG_AUDPREAMPRDCPRECHARGE);
/* Audio R PGA mode: 1_DCC */
regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON1,
0x3 << RG_AUDPREAMPRDCCEN,
0x1 << RG_AUDPREAMPRDCCEN);
break;
case SND_SOC_DAPM_POST_PMU:
usleep_range(100, 120);
/* Audio R PGA precharge off */
regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON1,
0x3 << RG_AUDPREAMPRDCPRECHARGE,
0x0 << RG_AUDPREAMPRDCPRECHARGE);
break;
default:
break;
}
return 0;
}
static int mt_mic_bias_0_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* MIC Bias 0 LowPower: 0_Normal */
regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9,
0x3 << RG_AUDMICBIAS0LOWPEN, 0x0);
/* MISBIAS0 = 1P9V */
regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9,
0x7 << RG_AUDMICBIAS0VREF,
0x2 << RG_AUDMICBIAS0VREF);
break;
case SND_SOC_DAPM_POST_PMD:
/* MISBIAS0 = 1P97 */
regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9,
0x7 << RG_AUDMICBIAS0VREF,
0x0 << RG_AUDMICBIAS0VREF);
break;
default:
break;
}
return 0;
}
static int mt_mic_bias_1_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* MIC Bias 1 LowPower: 0_Normal */
regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON10,
0x3 << RG_AUDMICBIAS1LOWPEN, 0x0);
/* MISBIAS1 = 2P7V */
regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON10,
0x7 << RG_AUDMICBIAS1VREF,
0x7 << RG_AUDMICBIAS1VREF);
break;
case SND_SOC_DAPM_POST_PMD:
/* MISBIAS1 = 1P7V */
regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON10,
0x7 << RG_AUDMICBIAS1VREF,
0x0 << RG_AUDMICBIAS1VREF);
break;
default:
break;
}
return 0;
}
static int mt_mic_bias_2_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* MIC Bias 2 LowPower: 0_Normal */
regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9,
0x3 << RG_AUDMICBIAS2LOWPEN, 0x0);
/* MISBIAS2 = 1P9V */
regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9,
0x7 << RG_AUDMICBIAS2VREF,
0x2 << RG_AUDMICBIAS2VREF);
break;
case SND_SOC_DAPM_POST_PMD:
/* MISBIAS2 = 1P97 */
regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9,
0x7 << RG_AUDMICBIAS2VREF,
0x0 << RG_AUDMICBIAS2VREF);
break;
default:
break;
}
return 0;
}
/* DAPM Widgets */
static const struct snd_soc_dapm_widget mt6351_dapm_widgets[] = {
/* Digital Clock */
SND_SOC_DAPM_SUPPLY("AUDIO_TOP_AFE_CTL", MT6351_AUDIO_TOP_CON0,
AUD_TOP_PDN_AFE_CTL_BIT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("AUDIO_TOP_DAC_CTL", MT6351_AUDIO_TOP_CON0,
AUD_TOP_PDN_DAC_CTL_BIT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("AUDIO_TOP_ADC_CTL", MT6351_AUDIO_TOP_CON0,
AUD_TOP_PDN_ADC_CTL_BIT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("AUDIO_TOP_PWR_CLK", MT6351_AUDIO_TOP_CON0,
AUD_TOP_PWR_CLK_DIS_CTL_BIT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("AUDIO_TOP_PDN_RESERVED", MT6351_AUDIO_TOP_CON0,
AUD_TOP_PDN_RESERVED_BIT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("NCP", MT6351_AFE_NCP_CFG0,
RG_NCP_ON_BIT, 0,
mt_ncp_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY("DL Digital Clock", SND_SOC_NOPM,
0, 0, NULL, 0),
/* Global Supply*/
SND_SOC_DAPM_SUPPLY("AUDGLB", MT6351_AUDDEC_ANA_CON9,
RG_AUDGLB_PWRDN_VA32_BIT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("CLKSQ Audio", MT6351_TOP_CLKSQ,
RG_CLKSQ_EN_AUD_BIT, 0,
mt_reg_set_clr_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SUPPLY("ZCD13M_CK", MT6351_TOP_CKPDN_CON0,
RG_ZCD13M_CK_PDN_BIT, 1,
mt_reg_set_clr_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SUPPLY("AUD_CK", MT6351_TOP_CKPDN_CON0,
RG_AUD_CK_PDN_BIT, 1,
mt_reg_set_clr_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SUPPLY("AUDIF_CK", MT6351_TOP_CKPDN_CON0,
RG_AUDIF_CK_PDN_BIT, 1,
mt_reg_set_clr_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SUPPLY("AUDNCP_CK", MT6351_TOP_CKPDN_CON0,
RG_AUDNCP_CK_PDN_BIT, 1,
mt_reg_set_clr_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SUPPLY("AFE_ON", MT6351_AFE_UL_DL_CON0, RG_AFE_ON_BIT, 0,
NULL, 0),
/* AIF Rx*/
SND_SOC_DAPM_AIF_IN_E("AIF_RX", "AIF1 Playback", 0,
MT6351_AFE_DL_SRC2_CON0_L,
RG_DL_2_SRC_ON_TMP_CTL_PRE_BIT, 0,
mt_aif_in_event, SND_SOC_DAPM_PRE_PMU),
/* DL Supply */
SND_SOC_DAPM_SUPPLY("DL Power Supply", SND_SOC_NOPM,
0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("NV Regulator", MT6351_AUDDEC_ANA_CON10,
RG_NVREG_EN_VAUDP32_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("AUD_CLK", MT6351_AUDDEC_ANA_CON9,
RG_RSTB_DECODER_VA32_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("IBIST", MT6351_AUDDEC_ANA_CON9,
RG_AUDIBIASPWRDN_VAUDP32_BIT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("LDO", MT6351_AUDDEC_ANA_CON9,
RG_LCLDO_DEC_EN_VA32_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("LDO_REMOTE_SENSE", MT6351_AUDDEC_ANA_CON9,
RG_LCLDO_DEC_REMOTE_SENSE_VA18_BIT, 0, NULL, 0),
/* DAC */
SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control),
SND_SOC_DAPM_DAC("DACL", NULL, MT6351_AUDDEC_ANA_CON0,
RG_AUDDACLPWRUP_VAUDP32_BIT, 0),
SND_SOC_DAPM_SUPPLY("DACL_BIASGEN", MT6351_AUDDEC_ANA_CON0,
RG_AUD_DAC_PWL_UP_VA32_BIT, 0, NULL, 0),
SND_SOC_DAPM_DAC("DACR", NULL, MT6351_AUDDEC_ANA_CON0,
RG_AUDDACRPWRUP_VAUDP32_BIT, 0),
SND_SOC_DAPM_SUPPLY("DACR_BIASGEN", MT6351_AUDDEC_ANA_CON0,
RG_AUD_DAC_PWR_UP_VA32_BIT, 0, NULL, 0),
/* LOL */
SND_SOC_DAPM_MUX("LOL Mux", SND_SOC_NOPM, 0, 0, &lo_in_mux_control),
SND_SOC_DAPM_SUPPLY("LO Stability Enh", MT6351_AUDDEC_ANA_CON3,
RG_LOOUTPUTSTBENH_VAUDP32_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("LOL Bias Gen", MT6351_AUDDEC_ANA_CON6,
RG_ABIDEC_RSVD0_VAUDP32_LOL_BIT, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("LOL Buffer", MT6351_AUDDEC_ANA_CON3,
RG_AUDLOLPWRUP_VAUDP32_BIT, 0, NULL, 0),
/* Headphone */
SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_in_mux_control),
SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_in_mux_control),
SND_SOC_DAPM_OUT_DRV_E("HPL Power", MT6351_AUDDEC_ANA_CON0,
RG_AUDHPLPWRUP_VAUDP32_BIT, 0, NULL, 0,
mt_hp_event,
SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_PRE_PMD |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_OUT_DRV_E("HPR Power", MT6351_AUDDEC_ANA_CON0,
RG_AUDHPRPWRUP_VAUDP32_BIT, 0, NULL, 0,
mt_hp_event,
SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_PRE_PMD |
SND_SOC_DAPM_POST_PMD),
/* Receiver */
SND_SOC_DAPM_MUX("RCV Mux", SND_SOC_NOPM, 0, 0, &rcv_in_mux_control),
SND_SOC_DAPM_SUPPLY("RCV Stability Enh", MT6351_AUDDEC_ANA_CON1,
RG_HSOUTPUTSTBENH_VAUDP32_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("RCV Bias Gen", MT6351_AUDDEC_ANA_CON6,
RG_ABIDEC_RSVD0_VAUDP32_HS_BIT, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("RCV Buffer", MT6351_AUDDEC_ANA_CON0,
RG_AUDHSPWRUP_VAUDP32_BIT, 0, NULL, 0),
/* Outputs */
SND_SOC_DAPM_OUTPUT("Receiver"),
SND_SOC_DAPM_OUTPUT("Headphone L"),
SND_SOC_DAPM_OUTPUT("Headphone R"),
SND_SOC_DAPM_OUTPUT("LINEOUT L"),
/* SGEN */
SND_SOC_DAPM_SUPPLY("SGEN DL Enable", MT6351_AFE_SGEN_CFG0,
SGEN_C_DAC_EN_CTL_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("SGEN MUTE", MT6351_AFE_SGEN_CFG0,
SGEN_C_MUTE_SW_CTL_BIT, 1,
mt_sgen_event, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_SUPPLY("SGEN DL SRC", MT6351_AFE_DL_SRC2_CON0_L,
RG_DL_2_SRC_ON_TMP_CTL_PRE_BIT, 0, NULL, 0),
SND_SOC_DAPM_INPUT("SGEN DL"),
/* Uplinks */
SND_SOC_DAPM_AIF_OUT_E("AIF1TX", "AIF1 Capture", 0,
MT6351_AFE_UL_SRC_CON0_L,
UL_SRC_ON_TMP_CTL, 0,
mt_aif_out_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SUPPLY_S("VUSB33_LDO", SUPPLY_SUBSEQ_ENABLE,
MT6351_LDO_VUSB33_CON0, RG_VUSB33_EN, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY_S("VUSB33_LDO_CTRL", SUPPLY_SUBSEQ_SETTING,
MT6351_LDO_VUSB33_CON0, RG_VUSB33_ON_CTRL, 1,
NULL, 0),
SND_SOC_DAPM_SUPPLY_S("VA18_LDO", SUPPLY_SUBSEQ_ENABLE,
MT6351_LDO_VA18_CON0, RG_VA18_EN, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("VA18_LDO_CTRL", SUPPLY_SUBSEQ_SETTING,
MT6351_LDO_VA18_CON0, RG_VA18_ON_CTRL, 1,
NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADC CLKGEN", SUPPLY_SUBSEQ_ENABLE,
MT6351_AUDENC_ANA_CON3, RG_AUDADCCLKRSTB, 0,
mt_adc_clkgen_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
/* Uplinks MUX */
SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0,
&aif_out_mux_control),
SND_SOC_DAPM_MUX("ADC L Mux", SND_SOC_NOPM, 0, 0,
&adc_left_mux_control),
SND_SOC_DAPM_MUX("ADC R Mux", SND_SOC_NOPM, 0, 0,
&adc_right_mux_control),
SND_SOC_DAPM_ADC("ADC L", NULL,
MT6351_AUDENC_ANA_CON0, RG_AUDADCLPWRUP, 0),
SND_SOC_DAPM_ADC("ADC R", NULL,
MT6351_AUDENC_ANA_CON1, RG_AUDADCRPWRUP, 0),
SND_SOC_DAPM_MUX("PGA L Mux", SND_SOC_NOPM, 0, 0,
&pga_left_mux_control),
SND_SOC_DAPM_MUX("PGA R Mux", SND_SOC_NOPM, 0, 0,
&pga_right_mux_control),
SND_SOC_DAPM_PGA_E("PGA L", MT6351_AUDENC_ANA_CON0, RG_AUDPREAMPLON, 0,
NULL, 0,
mt_pga_left_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("PGA R", MT6351_AUDENC_ANA_CON1, RG_AUDPREAMPRON, 0,
NULL, 0,
mt_pga_right_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
/* main mic mic bias */
SND_SOC_DAPM_SUPPLY_S("Mic Bias 0", SUPPLY_SUBSEQ_MICBIAS,
MT6351_AUDENC_ANA_CON9, RG_AUDPWDBMICBIAS0, 0,
mt_mic_bias_0_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
/* ref mic mic bias */
SND_SOC_DAPM_SUPPLY_S("Mic Bias 2", SUPPLY_SUBSEQ_MICBIAS,
MT6351_AUDENC_ANA_CON9, RG_AUDPWDBMICBIAS2, 0,
mt_mic_bias_2_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
/* headset mic1/2 mic bias */
SND_SOC_DAPM_SUPPLY_S("Mic Bias 1", SUPPLY_SUBSEQ_MICBIAS,
MT6351_AUDENC_ANA_CON10, RG_AUDPWDBMICBIAS1, 0,
mt_mic_bias_1_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("Mic Bias 1 DCC pull high", SUPPLY_SUBSEQ_MICBIAS,
MT6351_AUDENC_ANA_CON10,
RG_AUDMICBIAS1DCSW1NEN, 0,
NULL, 0),
/* UL input */
SND_SOC_DAPM_INPUT("AIN0"),
SND_SOC_DAPM_INPUT("AIN1"),
SND_SOC_DAPM_INPUT("AIN2"),
SND_SOC_DAPM_INPUT("AIN3"),
};
static const struct snd_soc_dapm_route mt6351_dapm_routes[] = {
/* Capture */
{"AIF1TX", NULL, "AIF Out Mux"},
{"AIF1TX", NULL, "VUSB33_LDO"},
{"VUSB33_LDO", NULL, "VUSB33_LDO_CTRL"},
{"AIF1TX", NULL, "VA18_LDO"},
{"VA18_LDO", NULL, "VA18_LDO_CTRL"},
{"AIF1TX", NULL, "AUDGLB"},
{"AIF1TX", NULL, "CLKSQ Audio"},
{"AIF1TX", NULL, "AFE_ON"},
{"AIF1TX", NULL, "AUDIO_TOP_AFE_CTL"},
{"AIF1TX", NULL, "AUDIO_TOP_ADC_CTL"},
{"AIF1TX", NULL, "AUDIO_TOP_PWR_CLK"},
{"AIF1TX", NULL, "AUDIO_TOP_PDN_RESERVED"},
{"AIF Out Mux", "Normal Path", "ADC L"},
{"AIF Out Mux", "Normal Path", "ADC R"},
{"ADC L", NULL, "ADC L Mux"},
{"ADC L", NULL, "AUD_CK"},
{"ADC L", NULL, "AUDIF_CK"},
{"ADC L", NULL, "ADC CLKGEN"},
{"ADC R", NULL, "ADC R Mux"},
{"ADC R", NULL, "AUD_CK"},
{"ADC R", NULL, "AUDIF_CK"},
{"ADC R", NULL, "ADC CLKGEN"},
{"ADC L Mux", "AIN0", "AIN0"},
{"ADC L Mux", "Left Preamplifier", "PGA L"},
{"ADC R Mux", "AIN0", "AIN0"},
{"ADC R Mux", "Right Preamplifier", "PGA R"},
{"PGA L", NULL, "PGA L Mux"},
{"PGA R", NULL, "PGA R Mux"},
{"PGA L Mux", "AIN0", "AIN0"},
{"PGA L Mux", "AIN1", "AIN1"},
{"PGA L Mux", "AIN2", "AIN2"},
{"PGA R Mux", "AIN0", "AIN0"},
{"PGA R Mux", "AIN3", "AIN3"},
{"PGA R Mux", "AIN2", "AIN2"},
{"AIN0", NULL, "Mic Bias 0"},
{"AIN2", NULL, "Mic Bias 2"},
{"AIN1", NULL, "Mic Bias 1"},
{"AIN1", NULL, "Mic Bias 1 DCC pull high"},
/* DL Supply */
{"DL Power Supply", NULL, "AUDGLB"},
{"DL Power Supply", NULL, "CLKSQ Audio"},
{"DL Power Supply", NULL, "ZCD13M_CK"},
{"DL Power Supply", NULL, "AUD_CK"},
{"DL Power Supply", NULL, "AUDIF_CK"},
{"DL Power Supply", NULL, "AUDNCP_CK"},
{"DL Power Supply", NULL, "NV Regulator"},
{"DL Power Supply", NULL, "AUD_CLK"},
{"DL Power Supply", NULL, "IBIST"},
{"DL Power Supply", NULL, "LDO"},
{"LDO", NULL, "LDO_REMOTE_SENSE"},
/* DL Digital Supply */
{"DL Digital Clock", NULL, "AUDIO_TOP_AFE_CTL"},
{"DL Digital Clock", NULL, "AUDIO_TOP_DAC_CTL"},
{"DL Digital Clock", NULL, "AUDIO_TOP_PWR_CLK"},
{"DL Digital Clock", NULL, "AUDIO_TOP_PDN_RESERVED"},
{"DL Digital Clock", NULL, "NCP"},
{"DL Digital Clock", NULL, "AFE_ON"},
{"AIF_RX", NULL, "DL Digital Clock"},
/* DL Path */
{"DAC In Mux", "Normal Path", "AIF_RX"},
{"DAC In Mux", "Sgen", "SGEN DL"},
{"SGEN DL", NULL, "SGEN DL SRC"},
{"SGEN DL", NULL, "SGEN MUTE"},
{"SGEN DL", NULL, "SGEN DL Enable"},
{"SGEN DL", NULL, "DL Digital Clock"},
{"DACL", NULL, "DAC In Mux"},
{"DACL", NULL, "DL Power Supply"},
{"DACL", NULL, "DACL_BIASGEN"},
{"DACR", NULL, "DAC In Mux"},
{"DACR", NULL, "DL Power Supply"},
{"DACR", NULL, "DACR_BIASGEN"},
{"LOL Mux", "Playback", "DACL"},
{"LOL Buffer", NULL, "LOL Mux"},
{"LOL Buffer", NULL, "LO Stability Enh"},
{"LOL Buffer", NULL, "LOL Bias Gen"},
{"LINEOUT L", NULL, "LOL Buffer"},
/* Headphone Path */
{"HPL Mux", "Audio Playback", "DACL"},
{"HPR Mux", "Audio Playback", "DACR"},
{"HPL Mux", "LoudSPK Playback", "DACL"},
{"HPR Mux", "LoudSPK Playback", "DACR"},
{"HPL Power", NULL, "HPL Mux"},
{"HPR Power", NULL, "HPR Mux"},
{"Headphone L", NULL, "HPL Power"},
{"Headphone R", NULL, "HPR Power"},
/* Receiver Path */
{"RCV Mux", "Voice Playback", "DACL"},
{"RCV Buffer", NULL, "RCV Mux"},
{"RCV Buffer", NULL, "RCV Stability Enh"},
{"RCV Buffer", NULL, "RCV Bias Gen"},
{"Receiver", NULL, "RCV Buffer"},
};
static int mt6351_codec_init_reg(struct snd_soc_component *cmpnt)
{
/* Disable CLKSQ 26MHz */
regmap_update_bits(cmpnt->regmap, MT6351_TOP_CLKSQ, 0x0001, 0x0);
/* disable AUDGLB */
regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON9,
0x1000, 0x1000);
/* Turn off AUDNCP_CLKDIV engine clock,Turn off AUD 26M */
regmap_update_bits(cmpnt->regmap, MT6351_TOP_CKPDN_CON0_SET,
0x3800, 0x3800);
/* Disable HeadphoneL/HeadphoneR/voice short circuit protection */
regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON0,
0xe000, 0xe000);
/* [5] = 1, disable LO buffer left short circuit protection */
regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON3,
0x20, 0x20);
/* Reverse the PMIC clock*/
regmap_update_bits(cmpnt->regmap, MT6351_AFE_PMIC_NEWIF_CFG2,
0x8000, 0x8000);
return 0;
}
static int mt6351_codec_probe(struct snd_soc_component *cmpnt)
{
struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt);
snd_soc_component_init_regmap(cmpnt, priv->regmap);
mt6351_codec_init_reg(cmpnt);
return 0;
}
static const struct snd_soc_component_driver mt6351_soc_component_driver = {
.probe = mt6351_codec_probe,
.controls = mt6351_snd_controls,
.num_controls = ARRAY_SIZE(mt6351_snd_controls),
.dapm_widgets = mt6351_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(mt6351_dapm_widgets),
.dapm_routes = mt6351_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(mt6351_dapm_routes),
.endianness = 1,
};
static int mt6351_codec_driver_probe(struct platform_device *pdev)
{
struct mt6351_priv *priv;
priv = devm_kzalloc(&pdev->dev,
sizeof(struct mt6351_priv),
GFP_KERNEL);
if (!priv)
return -ENOMEM;
dev_set_drvdata(&pdev->dev, priv);
priv->dev = &pdev->dev;
priv->regmap = dev_get_regmap(pdev->dev.parent, NULL);
if (!priv->regmap)
return -ENODEV;
dev_dbg(priv->dev, "%s(), dev name %s\n",
__func__, dev_name(&pdev->dev));
return devm_snd_soc_register_component(&pdev->dev,
&mt6351_soc_component_driver,
mt6351_dai_driver,
ARRAY_SIZE(mt6351_dai_driver));
}
static const struct of_device_id mt6351_of_match[] = {
{.compatible = "mediatek,mt6351-sound",},
{}
};
static struct platform_driver mt6351_codec_driver = {
.driver = {
.name = "mt6351-sound",
.of_match_table = mt6351_of_match,
},
.probe = mt6351_codec_driver_probe,
};
module_platform_driver(mt6351_codec_driver)
/* Module information */
MODULE_DESCRIPTION("MT6351 ALSA SoC codec driver");
MODULE_AUTHOR("KaiChieh Chuang <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/mt6351.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* NAU85L40 ALSA SoC audio driver
*
* Copyright 2016 Nuvoton Technology Corp.
* Author: John Hsu <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <linux/of_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "nau8540.h"
#define NAU_FREF_MAX 13500000
#define NAU_FVCO_MAX 100000000
#define NAU_FVCO_MIN 90000000
/* the maximum frequency of CLK_ADC */
#define CLK_ADC_MAX 6144000
/* scaling for mclk from sysclk_src output */
static const struct nau8540_fll_attr mclk_src_scaling[] = {
{ 1, 0x0 },
{ 2, 0x2 },
{ 4, 0x3 },
{ 8, 0x4 },
{ 16, 0x5 },
{ 32, 0x6 },
{ 3, 0x7 },
{ 6, 0xa },
{ 12, 0xb },
{ 24, 0xc },
};
/* ratio for input clk freq */
static const struct nau8540_fll_attr fll_ratio[] = {
{ 512000, 0x01 },
{ 256000, 0x02 },
{ 128000, 0x04 },
{ 64000, 0x08 },
{ 32000, 0x10 },
{ 8000, 0x20 },
{ 4000, 0x40 },
};
static const struct nau8540_fll_attr fll_pre_scalar[] = {
{ 1, 0x0 },
{ 2, 0x1 },
{ 4, 0x2 },
{ 8, 0x3 },
};
/* over sampling rate */
static const struct nau8540_osr_attr osr_adc_sel[] = {
{ 32, 3 }, /* OSR 32, SRC 1/8 */
{ 64, 2 }, /* OSR 64, SRC 1/4 */
{ 128, 1 }, /* OSR 128, SRC 1/2 */
{ 256, 0 }, /* OSR 256, SRC 1 */
};
static const struct reg_default nau8540_reg_defaults[] = {
{NAU8540_REG_POWER_MANAGEMENT, 0x0000},
{NAU8540_REG_CLOCK_CTRL, 0x0000},
{NAU8540_REG_CLOCK_SRC, 0x0000},
{NAU8540_REG_FLL1, 0x0001},
{NAU8540_REG_FLL2, 0x3126},
{NAU8540_REG_FLL3, 0x0008},
{NAU8540_REG_FLL4, 0x0010},
{NAU8540_REG_FLL5, 0xC000},
{NAU8540_REG_FLL6, 0x6000},
{NAU8540_REG_FLL_VCO_RSV, 0xF13C},
{NAU8540_REG_PCM_CTRL0, 0x000B},
{NAU8540_REG_PCM_CTRL1, 0x3010},
{NAU8540_REG_PCM_CTRL2, 0x0800},
{NAU8540_REG_PCM_CTRL3, 0x0000},
{NAU8540_REG_PCM_CTRL4, 0x000F},
{NAU8540_REG_ALC_CONTROL_1, 0x0000},
{NAU8540_REG_ALC_CONTROL_2, 0x700B},
{NAU8540_REG_ALC_CONTROL_3, 0x0022},
{NAU8540_REG_ALC_CONTROL_4, 0x1010},
{NAU8540_REG_ALC_CONTROL_5, 0x1010},
{NAU8540_REG_NOTCH_FIL1_CH1, 0x0000},
{NAU8540_REG_NOTCH_FIL2_CH1, 0x0000},
{NAU8540_REG_NOTCH_FIL1_CH2, 0x0000},
{NAU8540_REG_NOTCH_FIL2_CH2, 0x0000},
{NAU8540_REG_NOTCH_FIL1_CH3, 0x0000},
{NAU8540_REG_NOTCH_FIL2_CH3, 0x0000},
{NAU8540_REG_NOTCH_FIL1_CH4, 0x0000},
{NAU8540_REG_NOTCH_FIL2_CH4, 0x0000},
{NAU8540_REG_HPF_FILTER_CH12, 0x0000},
{NAU8540_REG_HPF_FILTER_CH34, 0x0000},
{NAU8540_REG_ADC_SAMPLE_RATE, 0x0002},
{NAU8540_REG_DIGITAL_GAIN_CH1, 0x0400},
{NAU8540_REG_DIGITAL_GAIN_CH2, 0x0400},
{NAU8540_REG_DIGITAL_GAIN_CH3, 0x0400},
{NAU8540_REG_DIGITAL_GAIN_CH4, 0x0400},
{NAU8540_REG_DIGITAL_MUX, 0x00E4},
{NAU8540_REG_GPIO_CTRL, 0x0000},
{NAU8540_REG_MISC_CTRL, 0x0000},
{NAU8540_REG_I2C_CTRL, 0xEFFF},
{NAU8540_REG_VMID_CTRL, 0x0000},
{NAU8540_REG_MUTE, 0x0000},
{NAU8540_REG_ANALOG_ADC1, 0x0011},
{NAU8540_REG_ANALOG_ADC2, 0x0020},
{NAU8540_REG_ANALOG_PWR, 0x0000},
{NAU8540_REG_MIC_BIAS, 0x0004},
{NAU8540_REG_REFERENCE, 0x0000},
{NAU8540_REG_FEPGA1, 0x0000},
{NAU8540_REG_FEPGA2, 0x0000},
{NAU8540_REG_FEPGA3, 0x0101},
{NAU8540_REG_FEPGA4, 0x0101},
{NAU8540_REG_PWR, 0x0000},
};
static bool nau8540_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case NAU8540_REG_POWER_MANAGEMENT ... NAU8540_REG_FLL_VCO_RSV:
case NAU8540_REG_PCM_CTRL0 ... NAU8540_REG_PCM_CTRL4:
case NAU8540_REG_ALC_CONTROL_1 ... NAU8540_REG_ALC_CONTROL_5:
case NAU8540_REG_ALC_GAIN_CH12 ... NAU8540_REG_ADC_SAMPLE_RATE:
case NAU8540_REG_DIGITAL_GAIN_CH1 ... NAU8540_REG_DIGITAL_MUX:
case NAU8540_REG_P2P_CH1 ... NAU8540_REG_I2C_CTRL:
case NAU8540_REG_I2C_DEVICE_ID:
case NAU8540_REG_VMID_CTRL ... NAU8540_REG_MUTE:
case NAU8540_REG_ANALOG_ADC1 ... NAU8540_REG_PWR:
return true;
default:
return false;
}
}
static bool nau8540_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case NAU8540_REG_SW_RESET ... NAU8540_REG_FLL_VCO_RSV:
case NAU8540_REG_PCM_CTRL0 ... NAU8540_REG_PCM_CTRL4:
case NAU8540_REG_ALC_CONTROL_1 ... NAU8540_REG_ALC_CONTROL_5:
case NAU8540_REG_NOTCH_FIL1_CH1 ... NAU8540_REG_ADC_SAMPLE_RATE:
case NAU8540_REG_DIGITAL_GAIN_CH1 ... NAU8540_REG_DIGITAL_MUX:
case NAU8540_REG_GPIO_CTRL ... NAU8540_REG_I2C_CTRL:
case NAU8540_REG_RST:
case NAU8540_REG_VMID_CTRL ... NAU8540_REG_MUTE:
case NAU8540_REG_ANALOG_ADC1 ... NAU8540_REG_PWR:
return true;
default:
return false;
}
}
static bool nau8540_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case NAU8540_REG_SW_RESET:
case NAU8540_REG_ALC_GAIN_CH12 ... NAU8540_REG_ALC_STATUS:
case NAU8540_REG_P2P_CH1 ... NAU8540_REG_PEAK_CH4:
case NAU8540_REG_I2C_DEVICE_ID:
case NAU8540_REG_RST:
return true;
default:
return false;
}
}
static const DECLARE_TLV_DB_MINMAX(adc_vol_tlv, -12800, 3600);
static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
static const struct snd_kcontrol_new nau8540_snd_controls[] = {
SOC_SINGLE_TLV("Mic1 Volume", NAU8540_REG_DIGITAL_GAIN_CH1,
0, 0x520, 0, adc_vol_tlv),
SOC_SINGLE_TLV("Mic2 Volume", NAU8540_REG_DIGITAL_GAIN_CH2,
0, 0x520, 0, adc_vol_tlv),
SOC_SINGLE_TLV("Mic3 Volume", NAU8540_REG_DIGITAL_GAIN_CH3,
0, 0x520, 0, adc_vol_tlv),
SOC_SINGLE_TLV("Mic4 Volume", NAU8540_REG_DIGITAL_GAIN_CH4,
0, 0x520, 0, adc_vol_tlv),
SOC_SINGLE_TLV("Frontend PGA1 Volume", NAU8540_REG_FEPGA3,
0, 0x25, 0, fepga_gain_tlv),
SOC_SINGLE_TLV("Frontend PGA2 Volume", NAU8540_REG_FEPGA3,
8, 0x25, 0, fepga_gain_tlv),
SOC_SINGLE_TLV("Frontend PGA3 Volume", NAU8540_REG_FEPGA4,
0, 0x25, 0, fepga_gain_tlv),
SOC_SINGLE_TLV("Frontend PGA4 Volume", NAU8540_REG_FEPGA4,
8, 0x25, 0, fepga_gain_tlv),
};
static const char * const adc_channel[] = {
"ADC channel 1", "ADC channel 2", "ADC channel 3", "ADC channel 4"
};
static SOC_ENUM_SINGLE_DECL(
digital_ch4_enum, NAU8540_REG_DIGITAL_MUX, 6, adc_channel);
static const struct snd_kcontrol_new digital_ch4_mux =
SOC_DAPM_ENUM("Digital CH4 Select", digital_ch4_enum);
static SOC_ENUM_SINGLE_DECL(
digital_ch3_enum, NAU8540_REG_DIGITAL_MUX, 4, adc_channel);
static const struct snd_kcontrol_new digital_ch3_mux =
SOC_DAPM_ENUM("Digital CH3 Select", digital_ch3_enum);
static SOC_ENUM_SINGLE_DECL(
digital_ch2_enum, NAU8540_REG_DIGITAL_MUX, 2, adc_channel);
static const struct snd_kcontrol_new digital_ch2_mux =
SOC_DAPM_ENUM("Digital CH2 Select", digital_ch2_enum);
static SOC_ENUM_SINGLE_DECL(
digital_ch1_enum, NAU8540_REG_DIGITAL_MUX, 0, adc_channel);
static const struct snd_kcontrol_new digital_ch1_mux =
SOC_DAPM_ENUM("Digital CH1 Select", digital_ch1_enum);
static int adc_power_control(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *k, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
if (SND_SOC_DAPM_EVENT_ON(event)) {
msleep(300);
/* DO12 and DO34 pad output enable */
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
NAU8540_I2S_DO12_TRI, 0);
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
NAU8540_I2S_DO34_TRI, 0);
} else if (SND_SOC_DAPM_EVENT_OFF(event)) {
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
NAU8540_I2S_DO12_TRI, NAU8540_I2S_DO12_TRI);
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
NAU8540_I2S_DO34_TRI, NAU8540_I2S_DO34_TRI);
}
return 0;
}
static int aiftx_power_control(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *k, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
if (SND_SOC_DAPM_EVENT_OFF(event)) {
regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0001);
regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0000);
}
return 0;
}
static const struct snd_soc_dapm_widget nau8540_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("MICBIAS2", NAU8540_REG_MIC_BIAS, 11, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS1", NAU8540_REG_MIC_BIAS, 10, 0, NULL, 0),
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_INPUT("MIC2"),
SND_SOC_DAPM_INPUT("MIC3"),
SND_SOC_DAPM_INPUT("MIC4"),
SND_SOC_DAPM_PGA("Frontend PGA1", NAU8540_REG_PWR, 12, 0, NULL, 0),
SND_SOC_DAPM_PGA("Frontend PGA2", NAU8540_REG_PWR, 13, 0, NULL, 0),
SND_SOC_DAPM_PGA("Frontend PGA3", NAU8540_REG_PWR, 14, 0, NULL, 0),
SND_SOC_DAPM_PGA("Frontend PGA4", NAU8540_REG_PWR, 15, 0, NULL, 0),
SND_SOC_DAPM_ADC_E("ADC1", NULL,
NAU8540_REG_POWER_MANAGEMENT, 0, 0, adc_power_control,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_ADC_E("ADC2", NULL,
NAU8540_REG_POWER_MANAGEMENT, 1, 0, adc_power_control,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_ADC_E("ADC3", NULL,
NAU8540_REG_POWER_MANAGEMENT, 2, 0, adc_power_control,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_ADC_E("ADC4", NULL,
NAU8540_REG_POWER_MANAGEMENT, 3, 0, adc_power_control,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA("ADC CH1", NAU8540_REG_ANALOG_PWR, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("ADC CH2", NAU8540_REG_ANALOG_PWR, 1, 0, NULL, 0),
SND_SOC_DAPM_PGA("ADC CH3", NAU8540_REG_ANALOG_PWR, 2, 0, NULL, 0),
SND_SOC_DAPM_PGA("ADC CH4", NAU8540_REG_ANALOG_PWR, 3, 0, NULL, 0),
SND_SOC_DAPM_MUX("Digital CH4 Mux",
SND_SOC_NOPM, 0, 0, &digital_ch4_mux),
SND_SOC_DAPM_MUX("Digital CH3 Mux",
SND_SOC_NOPM, 0, 0, &digital_ch3_mux),
SND_SOC_DAPM_MUX("Digital CH2 Mux",
SND_SOC_NOPM, 0, 0, &digital_ch2_mux),
SND_SOC_DAPM_MUX("Digital CH1 Mux",
SND_SOC_NOPM, 0, 0, &digital_ch1_mux),
SND_SOC_DAPM_AIF_OUT_E("AIFTX", "Capture", 0, SND_SOC_NOPM, 0, 0,
aiftx_power_control, SND_SOC_DAPM_POST_PMD),
};
static const struct snd_soc_dapm_route nau8540_dapm_routes[] = {
{"Frontend PGA1", NULL, "MIC1"},
{"Frontend PGA2", NULL, "MIC2"},
{"Frontend PGA3", NULL, "MIC3"},
{"Frontend PGA4", NULL, "MIC4"},
{"ADC1", NULL, "Frontend PGA1"},
{"ADC2", NULL, "Frontend PGA2"},
{"ADC3", NULL, "Frontend PGA3"},
{"ADC4", NULL, "Frontend PGA4"},
{"ADC CH1", NULL, "ADC1"},
{"ADC CH2", NULL, "ADC2"},
{"ADC CH3", NULL, "ADC3"},
{"ADC CH4", NULL, "ADC4"},
{"ADC1", NULL, "MICBIAS1"},
{"ADC2", NULL, "MICBIAS1"},
{"ADC3", NULL, "MICBIAS2"},
{"ADC4", NULL, "MICBIAS2"},
{"Digital CH1 Mux", "ADC channel 1", "ADC CH1"},
{"Digital CH1 Mux", "ADC channel 2", "ADC CH2"},
{"Digital CH1 Mux", "ADC channel 3", "ADC CH3"},
{"Digital CH1 Mux", "ADC channel 4", "ADC CH4"},
{"Digital CH2 Mux", "ADC channel 1", "ADC CH1"},
{"Digital CH2 Mux", "ADC channel 2", "ADC CH2"},
{"Digital CH2 Mux", "ADC channel 3", "ADC CH3"},
{"Digital CH2 Mux", "ADC channel 4", "ADC CH4"},
{"Digital CH3 Mux", "ADC channel 1", "ADC CH1"},
{"Digital CH3 Mux", "ADC channel 2", "ADC CH2"},
{"Digital CH3 Mux", "ADC channel 3", "ADC CH3"},
{"Digital CH3 Mux", "ADC channel 4", "ADC CH4"},
{"Digital CH4 Mux", "ADC channel 1", "ADC CH1"},
{"Digital CH4 Mux", "ADC channel 2", "ADC CH2"},
{"Digital CH4 Mux", "ADC channel 3", "ADC CH3"},
{"Digital CH4 Mux", "ADC channel 4", "ADC CH4"},
{"AIFTX", NULL, "Digital CH1 Mux"},
{"AIFTX", NULL, "Digital CH2 Mux"},
{"AIFTX", NULL, "Digital CH3 Mux"},
{"AIFTX", NULL, "Digital CH4 Mux"},
};
static const struct nau8540_osr_attr *
nau8540_get_osr(struct nau8540 *nau8540)
{
unsigned int osr;
regmap_read(nau8540->regmap, NAU8540_REG_ADC_SAMPLE_RATE, &osr);
osr &= NAU8540_ADC_OSR_MASK;
if (osr >= ARRAY_SIZE(osr_adc_sel))
return NULL;
return &osr_adc_sel[osr];
}
static int nau8540_dai_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
const struct nau8540_osr_attr *osr;
osr = nau8540_get_osr(nau8540);
if (!osr || !osr->osr)
return -EINVAL;
return snd_pcm_hw_constraint_minmax(substream->runtime,
SNDRV_PCM_HW_PARAM_RATE,
0, CLK_ADC_MAX / osr->osr);
}
static int nau8540_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
unsigned int val_len = 0;
const struct nau8540_osr_attr *osr;
/* CLK_ADC = OSR * FS
* ADC clock frequency is defined as Over Sampling Rate (OSR)
* multiplied by the audio sample rate (Fs). Note that the OSR and Fs
* values must be selected such that the maximum frequency is less
* than 6.144 MHz.
*/
osr = nau8540_get_osr(nau8540);
if (!osr || !osr->osr)
return -EINVAL;
if (params_rate(params) * osr->osr > CLK_ADC_MAX)
return -EINVAL;
regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
NAU8540_CLK_ADC_SRC_MASK,
osr->clk_src << NAU8540_CLK_ADC_SRC_SFT);
switch (params_width(params)) {
case 16:
val_len |= NAU8540_I2S_DL_16;
break;
case 20:
val_len |= NAU8540_I2S_DL_20;
break;
case 24:
val_len |= NAU8540_I2S_DL_24;
break;
case 32:
val_len |= NAU8540_I2S_DL_32;
break;
default:
return -EINVAL;
}
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0,
NAU8540_I2S_DL_MASK, val_len);
return 0;
}
static int nau8540_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
unsigned int ctrl1_val = 0, ctrl2_val = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
ctrl2_val |= NAU8540_I2S_MS_MASTER;
break;
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
ctrl1_val |= NAU8540_I2S_BP_INV;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
ctrl1_val |= NAU8540_I2S_DF_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
ctrl1_val |= NAU8540_I2S_DF_LEFT;
break;
case SND_SOC_DAIFMT_RIGHT_J:
ctrl1_val |= NAU8540_I2S_DF_RIGTH;
break;
case SND_SOC_DAIFMT_DSP_A:
ctrl1_val |= NAU8540_I2S_DF_PCM_AB;
break;
case SND_SOC_DAIFMT_DSP_B:
ctrl1_val |= NAU8540_I2S_DF_PCM_AB;
ctrl1_val |= NAU8540_I2S_PCMB_EN;
break;
default:
return -EINVAL;
}
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0,
NAU8540_I2S_DL_MASK | NAU8540_I2S_DF_MASK |
NAU8540_I2S_BP_INV | NAU8540_I2S_PCMB_EN, ctrl1_val);
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
NAU8540_I2S_MS_MASK | NAU8540_I2S_DO12_OE, ctrl2_val);
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
NAU8540_I2S_DO34_OE, 0);
return 0;
}
/**
* nau8540_set_tdm_slot - configure DAI TX TDM.
* @dai: DAI
* @tx_mask: bitmask representing active TX slots. Ex.
* 0xf for normal 4 channel TDM.
* 0xf0 for shifted 4 channel TDM
* @rx_mask: no used.
* @slots: Number of slots in use.
* @slot_width: Width in bits for each slot.
*
* Configures a DAI for TDM operation. Only support 4 slots TDM.
*/
static int nau8540_set_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
unsigned int ctrl2_val = 0, ctrl4_val = 0;
if (slots > 4 || ((tx_mask & 0xf0) && (tx_mask & 0xf)))
return -EINVAL;
ctrl4_val |= (NAU8540_TDM_MODE | NAU8540_TDM_OFFSET_EN);
if (tx_mask & 0xf0) {
ctrl2_val = 4 * slot_width;
ctrl4_val |= (tx_mask >> 4);
} else {
ctrl4_val |= tx_mask;
}
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL4,
NAU8540_TDM_MODE | NAU8540_TDM_OFFSET_EN |
NAU8540_TDM_TX_MASK, ctrl4_val);
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
NAU8540_I2S_DO12_OE, NAU8540_I2S_DO12_OE);
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
NAU8540_I2S_DO34_OE | NAU8540_I2S_TSLOT_L_MASK,
NAU8540_I2S_DO34_OE | ctrl2_val);
return 0;
}
static const struct snd_soc_dai_ops nau8540_dai_ops = {
.startup = nau8540_dai_startup,
.hw_params = nau8540_hw_params,
.set_fmt = nau8540_set_fmt,
.set_tdm_slot = nau8540_set_tdm_slot,
};
#define NAU8540_RATES SNDRV_PCM_RATE_8000_48000
#define NAU8540_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
| SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver nau8540_dai = {
.name = "nau8540-hifi",
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 4,
.rates = NAU8540_RATES,
.formats = NAU8540_FORMATS,
},
.ops = &nau8540_dai_ops,
};
/**
* nau8540_calc_fll_param - Calculate FLL parameters.
* @fll_in: external clock provided to codec.
* @fs: sampling rate.
* @fll_param: Pointer to structure of FLL parameters.
*
* Calculate FLL parameters to configure codec.
*
* Returns 0 for success or negative error code.
*/
static int nau8540_calc_fll_param(unsigned int fll_in,
unsigned int fs, struct nau8540_fll *fll_param)
{
u64 fvco, fvco_max;
unsigned int fref, i, fvco_sel;
/* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing
* freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
* FREF = freq_in / NAU8540_FLL_REF_DIV_MASK
*/
for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
fref = fll_in / fll_pre_scalar[i].param;
if (fref <= NAU_FREF_MAX)
break;
}
if (i == ARRAY_SIZE(fll_pre_scalar))
return -EINVAL;
fll_param->clk_ref_div = fll_pre_scalar[i].val;
/* Choose the FLL ratio based on FREF */
for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
if (fref >= fll_ratio[i].param)
break;
}
if (i == ARRAY_SIZE(fll_ratio))
return -EINVAL;
fll_param->ratio = fll_ratio[i].val;
/* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.
* FDCO must be within the 90MHz - 124MHz or the FFL cannot be
* guaranteed across the full range of operation.
* FDCO = freq_out * 2 * mclk_src_scaling
*/
fvco_max = 0;
fvco_sel = ARRAY_SIZE(mclk_src_scaling);
for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param;
if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&
fvco_max < fvco) {
fvco_max = fvco;
fvco_sel = i;
}
}
if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel)
return -EINVAL;
fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
/* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional
* input based on FDCO, FREF and FLL ratio.
*/
fvco = div_u64(fvco_max << 16, fref * fll_param->ratio);
fll_param->fll_int = (fvco >> 16) & 0x3FF;
fll_param->fll_frac = fvco & 0xFFFF;
return 0;
}
static void nau8540_fll_apply(struct regmap *regmap,
struct nau8540_fll *fll_param)
{
regmap_update_bits(regmap, NAU8540_REG_CLOCK_SRC,
NAU8540_CLK_SRC_MASK | NAU8540_CLK_MCLK_SRC_MASK,
NAU8540_CLK_SRC_MCLK | fll_param->mclk_src);
regmap_update_bits(regmap, NAU8540_REG_FLL1,
NAU8540_FLL_RATIO_MASK | NAU8540_ICTRL_LATCH_MASK,
fll_param->ratio | (0x6 << NAU8540_ICTRL_LATCH_SFT));
/* FLL 16-bit fractional input */
regmap_write(regmap, NAU8540_REG_FLL2, fll_param->fll_frac);
/* FLL 10-bit integer input */
regmap_update_bits(regmap, NAU8540_REG_FLL3,
NAU8540_FLL_INTEGER_MASK, fll_param->fll_int);
/* FLL pre-scaler */
regmap_update_bits(regmap, NAU8540_REG_FLL4,
NAU8540_FLL_REF_DIV_MASK,
fll_param->clk_ref_div << NAU8540_FLL_REF_DIV_SFT);
regmap_update_bits(regmap, NAU8540_REG_FLL5,
NAU8540_FLL_CLK_SW_MASK, NAU8540_FLL_CLK_SW_REF);
regmap_update_bits(regmap,
NAU8540_REG_FLL6, NAU8540_DCO_EN, 0);
if (fll_param->fll_frac) {
regmap_update_bits(regmap, NAU8540_REG_FLL5,
NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN |
NAU8540_FLL_FTR_SW_MASK,
NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN |
NAU8540_FLL_FTR_SW_FILTER);
regmap_update_bits(regmap, NAU8540_REG_FLL6,
NAU8540_SDM_EN | NAU8540_CUTOFF500,
NAU8540_SDM_EN | NAU8540_CUTOFF500);
} else {
regmap_update_bits(regmap, NAU8540_REG_FLL5,
NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN |
NAU8540_FLL_FTR_SW_MASK, NAU8540_FLL_FTR_SW_ACCU);
regmap_update_bits(regmap, NAU8540_REG_FLL6,
NAU8540_SDM_EN | NAU8540_CUTOFF500, 0);
}
}
/* freq_out must be 256*Fs in order to achieve the best performance */
static int nau8540_set_pll(struct snd_soc_component *component, int pll_id, int source,
unsigned int freq_in, unsigned int freq_out)
{
struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
struct nau8540_fll fll_param;
int ret, fs;
switch (pll_id) {
case NAU8540_CLK_FLL_MCLK:
regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK,
NAU8540_FLL_CLK_SRC_MCLK | 0);
break;
case NAU8540_CLK_FLL_BLK:
regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK,
NAU8540_FLL_CLK_SRC_BLK |
(0xf << NAU8540_GAIN_ERR_SFT));
break;
case NAU8540_CLK_FLL_FS:
regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK,
NAU8540_FLL_CLK_SRC_FS |
(0xf << NAU8540_GAIN_ERR_SFT));
break;
default:
dev_err(nau8540->dev, "Invalid clock id (%d)\n", pll_id);
return -EINVAL;
}
dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n",
freq_out, pll_id);
fs = freq_out / 256;
ret = nau8540_calc_fll_param(freq_in, fs, &fll_param);
if (ret < 0) {
dev_err(nau8540->dev, "Unsupported input clock %d\n", freq_in);
return ret;
}
dev_dbg(nau8540->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac,
fll_param.fll_int, fll_param.clk_ref_div);
nau8540_fll_apply(nau8540->regmap, &fll_param);
mdelay(2);
regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_VCO);
return 0;
}
static int nau8540_set_sysclk(struct snd_soc_component *component,
int clk_id, int source, unsigned int freq, int dir)
{
struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
switch (clk_id) {
case NAU8540_CLK_DIS:
case NAU8540_CLK_MCLK:
regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_MCLK);
regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6,
NAU8540_DCO_EN, 0);
break;
case NAU8540_CLK_INTERNAL:
regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6,
NAU8540_DCO_EN, NAU8540_DCO_EN);
regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_VCO);
break;
default:
dev_err(nau8540->dev, "Invalid clock id (%d)\n", clk_id);
return -EINVAL;
}
dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n",
freq, clk_id);
return 0;
}
static void nau8540_reset_chip(struct regmap *regmap)
{
regmap_write(regmap, NAU8540_REG_SW_RESET, 0x00);
regmap_write(regmap, NAU8540_REG_SW_RESET, 0x00);
}
static void nau8540_init_regs(struct nau8540 *nau8540)
{
struct regmap *regmap = nau8540->regmap;
/* Enable Bias/VMID/VMID Tieoff */
regmap_update_bits(regmap, NAU8540_REG_VMID_CTRL,
NAU8540_VMID_EN | NAU8540_VMID_SEL_MASK,
NAU8540_VMID_EN | (0x2 << NAU8540_VMID_SEL_SFT));
regmap_update_bits(regmap, NAU8540_REG_REFERENCE,
NAU8540_PRECHARGE_DIS | NAU8540_GLOBAL_BIAS_EN,
NAU8540_PRECHARGE_DIS | NAU8540_GLOBAL_BIAS_EN);
mdelay(2);
regmap_update_bits(regmap, NAU8540_REG_MIC_BIAS,
NAU8540_PU_PRE, NAU8540_PU_PRE);
regmap_update_bits(regmap, NAU8540_REG_CLOCK_CTRL,
NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN,
NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN);
/* ADC OSR selection, CLK_ADC = Fs * OSR;
* Channel time alignment enable.
*/
regmap_update_bits(regmap, NAU8540_REG_ADC_SAMPLE_RATE,
NAU8540_CH_SYNC | NAU8540_ADC_OSR_MASK,
NAU8540_CH_SYNC | NAU8540_ADC_OSR_64);
/* PGA input mode selection */
regmap_update_bits(regmap, NAU8540_REG_FEPGA1,
NAU8540_FEPGA1_MODCH2_SHT | NAU8540_FEPGA1_MODCH1_SHT,
NAU8540_FEPGA1_MODCH2_SHT | NAU8540_FEPGA1_MODCH1_SHT);
regmap_update_bits(regmap, NAU8540_REG_FEPGA2,
NAU8540_FEPGA2_MODCH4_SHT | NAU8540_FEPGA2_MODCH3_SHT,
NAU8540_FEPGA2_MODCH4_SHT | NAU8540_FEPGA2_MODCH3_SHT);
/* DO12 and DO34 pad output disable */
regmap_update_bits(regmap, NAU8540_REG_PCM_CTRL1,
NAU8540_I2S_DO12_TRI, NAU8540_I2S_DO12_TRI);
regmap_update_bits(regmap, NAU8540_REG_PCM_CTRL2,
NAU8540_I2S_DO34_TRI, NAU8540_I2S_DO34_TRI);
}
static int __maybe_unused nau8540_suspend(struct snd_soc_component *component)
{
struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
regcache_cache_only(nau8540->regmap, true);
regcache_mark_dirty(nau8540->regmap);
return 0;
}
static int __maybe_unused nau8540_resume(struct snd_soc_component *component)
{
struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
regcache_cache_only(nau8540->regmap, false);
regcache_sync(nau8540->regmap);
return 0;
}
static const struct snd_soc_component_driver nau8540_component_driver = {
.set_sysclk = nau8540_set_sysclk,
.set_pll = nau8540_set_pll,
.suspend = nau8540_suspend,
.resume = nau8540_resume,
.controls = nau8540_snd_controls,
.num_controls = ARRAY_SIZE(nau8540_snd_controls),
.dapm_widgets = nau8540_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(nau8540_dapm_widgets),
.dapm_routes = nau8540_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(nau8540_dapm_routes),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config nau8540_regmap_config = {
.val_bits = 16,
.reg_bits = 16,
.max_register = NAU8540_REG_MAX,
.readable_reg = nau8540_readable_reg,
.writeable_reg = nau8540_writeable_reg,
.volatile_reg = nau8540_volatile_reg,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = nau8540_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(nau8540_reg_defaults),
};
static int nau8540_i2c_probe(struct i2c_client *i2c)
{
struct device *dev = &i2c->dev;
struct nau8540 *nau8540 = dev_get_platdata(dev);
int ret, value;
if (!nau8540) {
nau8540 = devm_kzalloc(dev, sizeof(*nau8540), GFP_KERNEL);
if (!nau8540)
return -ENOMEM;
}
i2c_set_clientdata(i2c, nau8540);
nau8540->regmap = devm_regmap_init_i2c(i2c, &nau8540_regmap_config);
if (IS_ERR(nau8540->regmap))
return PTR_ERR(nau8540->regmap);
ret = regmap_read(nau8540->regmap, NAU8540_REG_I2C_DEVICE_ID, &value);
if (ret < 0) {
dev_err(dev, "Failed to read device id from the NAU85L40: %d\n",
ret);
return ret;
}
nau8540->dev = dev;
nau8540_reset_chip(nau8540->regmap);
nau8540_init_regs(nau8540);
return devm_snd_soc_register_component(dev,
&nau8540_component_driver, &nau8540_dai, 1);
}
static const struct i2c_device_id nau8540_i2c_ids[] = {
{ "nau8540", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, nau8540_i2c_ids);
#ifdef CONFIG_OF
static const struct of_device_id nau8540_of_ids[] = {
{ .compatible = "nuvoton,nau8540", },
{}
};
MODULE_DEVICE_TABLE(of, nau8540_of_ids);
#endif
static struct i2c_driver nau8540_i2c_driver = {
.driver = {
.name = "nau8540",
.of_match_table = of_match_ptr(nau8540_of_ids),
},
.probe = nau8540_i2c_probe,
.id_table = nau8540_i2c_ids,
};
module_i2c_driver(nau8540_i2c_driver);
MODULE_DESCRIPTION("ASoC NAU85L40 driver");
MODULE_AUTHOR("John Hsu <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/nau8540.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* LM4857 AMP driver
*
* Copyright 2007 Wolfson Microelectronics PLC.
* Author: Graeme Gregory
* [email protected]
* Copyright 2011 Lars-Peter Clausen <[email protected]>
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/soc.h>
#include <sound/tlv.h>
static const struct reg_default lm4857_default_regs[] = {
{ 0x0, 0x00 },
{ 0x1, 0x00 },
{ 0x2, 0x00 },
{ 0x3, 0x00 },
};
/* The register offsets in the cache array */
#define LM4857_MVOL 0
#define LM4857_LVOL 1
#define LM4857_RVOL 2
#define LM4857_CTRL 3
/* the shifts required to set these bits */
#define LM4857_3D 5
#define LM4857_WAKEUP 5
#define LM4857_EPGAIN 4
static const unsigned int lm4857_mode_values[] = {
0,
6,
7,
8,
9,
};
static const char * const lm4857_mode_texts[] = {
"Off",
"Earpiece",
"Loudspeaker",
"Loudspeaker + Headphone",
"Headphone",
};
static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(lm4857_mode_enum,
LM4857_CTRL, 0, 0xf, lm4857_mode_texts, lm4857_mode_values);
static const struct snd_kcontrol_new lm4857_mode_ctrl =
SOC_DAPM_ENUM("Mode", lm4857_mode_enum);
static const struct snd_soc_dapm_widget lm4857_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("IN"),
SND_SOC_DAPM_DEMUX("Mode", SND_SOC_NOPM, 0, 0, &lm4857_mode_ctrl),
SND_SOC_DAPM_OUTPUT("LS"),
SND_SOC_DAPM_OUTPUT("HP"),
SND_SOC_DAPM_OUTPUT("EP"),
};
static const DECLARE_TLV_DB_SCALE(stereo_tlv, -4050, 150, 0);
static const DECLARE_TLV_DB_SCALE(mono_tlv, -3450, 150, 0);
static const struct snd_kcontrol_new lm4857_controls[] = {
SOC_SINGLE_TLV("Left Playback Volume", LM4857_LVOL, 0, 31, 0,
stereo_tlv),
SOC_SINGLE_TLV("Right Playback Volume", LM4857_RVOL, 0, 31, 0,
stereo_tlv),
SOC_SINGLE_TLV("Mono Playback Volume", LM4857_MVOL, 0, 31, 0,
mono_tlv),
SOC_SINGLE("Spk 3D Playback Switch", LM4857_LVOL, LM4857_3D, 1, 0),
SOC_SINGLE("HP 3D Playback Switch", LM4857_RVOL, LM4857_3D, 1, 0),
SOC_SINGLE("Fast Wakeup Playback Switch", LM4857_CTRL,
LM4857_WAKEUP, 1, 0),
SOC_SINGLE("Earpiece 6dB Playback Switch", LM4857_CTRL,
LM4857_EPGAIN, 1, 0),
};
static const struct snd_soc_dapm_route lm4857_routes[] = {
{ "Mode", NULL, "IN" },
{ "LS", "Loudspeaker", "Mode" },
{ "LS", "Loudspeaker + Headphone", "Mode" },
{ "HP", "Headphone", "Mode" },
{ "HP", "Loudspeaker + Headphone", "Mode" },
{ "EP", "Earpiece", "Mode" },
};
static const struct snd_soc_component_driver lm4857_component_driver = {
.controls = lm4857_controls,
.num_controls = ARRAY_SIZE(lm4857_controls),
.dapm_widgets = lm4857_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(lm4857_dapm_widgets),
.dapm_routes = lm4857_routes,
.num_dapm_routes = ARRAY_SIZE(lm4857_routes),
};
static const struct regmap_config lm4857_regmap_config = {
.val_bits = 6,
.reg_bits = 2,
.max_register = LM4857_CTRL,
.cache_type = REGCACHE_FLAT,
.reg_defaults = lm4857_default_regs,
.num_reg_defaults = ARRAY_SIZE(lm4857_default_regs),
};
static int lm4857_i2c_probe(struct i2c_client *i2c)
{
struct regmap *regmap;
regmap = devm_regmap_init_i2c(i2c, &lm4857_regmap_config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return devm_snd_soc_register_component(&i2c->dev,
&lm4857_component_driver, NULL, 0);
}
static const struct i2c_device_id lm4857_i2c_id[] = {
{ "lm4857", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, lm4857_i2c_id);
static struct i2c_driver lm4857_i2c_driver = {
.driver = {
.name = "lm4857",
},
.probe = lm4857_i2c_probe,
.id_table = lm4857_i2c_id,
};
module_i2c_driver(lm4857_i2c_driver);
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_DESCRIPTION("LM4857 amplifier driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/lm4857.c |
Subsets and Splits