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// SPDX-License-Identifier: GPL-2.0
#include <linux/bits.h>
#include <linux/bitfield.h>
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#define RT9120_REG_DEVID 0x00
#define RT9120_REG_I2SFMT 0x02
#define RT9120_REG_I2SWL 0x03
#define RT9120_REG_SDIOSEL 0x04
#define RT9120_REG_SYSCTL 0x05
#define RT9120_REG_SPKGAIN 0x07
#define RT9120_REG_VOLRAMP 0x0A
#define RT9120_REG_ERRRPT 0x10
#define RT9120_REG_MSVOL 0x20
#define RT9120_REG_SWRESET 0x40
#define RT9120_REG_INTERCFG 0x63
#define RT9120_REG_INTERNAL0 0x65
#define RT9120_REG_INTERNAL1 0x69
#define RT9120_REG_UVPOPT 0x6C
#define RT9120_REG_DIGCFG 0xF8
#define RT9120_VID_MASK GENMASK(15, 8)
#define RT9120_SWRST_MASK BIT(7)
#define RT9120_MUTE_MASK GENMASK(5, 4)
#define RT9120_I2SFMT_MASK GENMASK(4, 2)
#define RT9120_I2SFMT_SHIFT 2
#define RT9120_CFG_FMT_I2S 0
#define RT9120_CFG_FMT_LEFTJ 1
#define RT9120_CFG_FMT_RIGHTJ 2
#define RT9120_CFG_FMT_DSPA 3
#define RT9120_CFG_FMT_DSPB 7
#define RT9120_AUDBIT_MASK GENMASK(1, 0)
#define RT9120_CFG_AUDBIT_16 0
#define RT9120_CFG_AUDBIT_20 1
#define RT9120_CFG_AUDBIT_24 2
#define RT9120_AUDWL_MASK GENMASK(5, 0)
#define RT9120_CFG_WORDLEN_16 16
#define RT9120_CFG_WORDLEN_24 24
#define RT9120_CFG_WORDLEN_32 32
#define RT9120_DVDD_UVSEL_MASK GENMASK(5, 4)
#define RT9120_AUTOSYNC_MASK BIT(6)
#define RT9120_VENDOR_ID 0x42
#define RT9120S_VENDOR_ID 0x43
#define RT9120_RESET_WAITMS 20
#define RT9120_CHIPON_WAITMS 20
#define RT9120_AMPON_WAITMS 50
#define RT9120_AMPOFF_WAITMS 100
#define RT9120_LVAPP_THRESUV 2000000
/* 8000 to 192000 supported , only 176400 not support */
#define RT9120_RATES_MASK (SNDRV_PCM_RATE_8000_192000 &\
~SNDRV_PCM_RATE_176400)
#define RT9120_FMTS_MASK (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
enum {
CHIP_IDX_RT9120 = 0,
CHIP_IDX_RT9120S,
CHIP_IDX_MAX
};
struct rt9120_data {
struct device *dev;
struct regmap *regmap;
struct gpio_desc *pwdnn_gpio;
int chip_idx;
};
/* 11bit [min,max,step] = [-103.9375dB, 24dB, 0.0625dB] */
static const DECLARE_TLV_DB_SCALE(digital_tlv, -1039375, 625, 1);
/* {6, 8, 10, 12, 13, 14, 15, 16}dB */
static const DECLARE_TLV_DB_RANGE(classd_tlv,
0, 3, TLV_DB_SCALE_ITEM(600, 200, 0),
4, 7, TLV_DB_SCALE_ITEM(1300, 100, 0)
);
static const char * const sdo_select_text[] = {
"None", "INTF", "Final", "RMS Detect"
};
static const struct soc_enum sdo_select_enum =
SOC_ENUM_SINGLE(RT9120_REG_SDIOSEL, 4, ARRAY_SIZE(sdo_select_text),
sdo_select_text);
static const struct snd_kcontrol_new rt9120_snd_controls[] = {
SOC_SINGLE_TLV("MS Volume", RT9120_REG_MSVOL, 0, 2047, 1, digital_tlv),
SOC_SINGLE_TLV("SPK Gain Volume", RT9120_REG_SPKGAIN, 0, 7, 0, classd_tlv),
SOC_SINGLE("PBTL Switch", RT9120_REG_SYSCTL, 3, 1, 0),
SOC_ENUM("SDO Select", sdo_select_enum),
};
static int internal_power_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_component_write(comp, RT9120_REG_ERRRPT, 0);
break;
case SND_SOC_DAPM_POST_PMU:
msleep(RT9120_AMPON_WAITMS);
break;
case SND_SOC_DAPM_POST_PMD:
msleep(RT9120_AMPOFF_WAITMS);
break;
default:
break;
}
return 0;
}
static const struct snd_soc_dapm_widget rt9120_dapm_widgets[] = {
SND_SOC_DAPM_MIXER("DMIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_DAC("LDAC", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("RDAC", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SUPPLY("PWND", RT9120_REG_SYSCTL, 6, 1,
internal_power_event, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA("SPKL PA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("SPKR PA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("SPKL"),
SND_SOC_DAPM_OUTPUT("SPKR"),
};
static const struct snd_soc_dapm_route rt9120_dapm_routes[] = {
{ "DMIX", NULL, "AIF Playback" },
/* SPKL */
{ "LDAC", NULL, "PWND" },
{ "LDAC", NULL, "DMIX" },
{ "SPKL PA", NULL, "LDAC" },
{ "SPKL", NULL, "SPKL PA" },
/* SPKR */
{ "RDAC", NULL, "PWND" },
{ "RDAC", NULL, "DMIX" },
{ "SPKR PA", NULL, "RDAC" },
{ "SPKR", NULL, "SPKR PA" },
/* Cap */
{ "AIF Capture", NULL, "LDAC" },
{ "AIF Capture", NULL, "RDAC" },
};
static int rt9120_codec_probe(struct snd_soc_component *comp)
{
struct rt9120_data *data = snd_soc_component_get_drvdata(comp);
snd_soc_component_init_regmap(comp, data->regmap);
pm_runtime_get_sync(comp->dev);
/* Internal setting */
if (data->chip_idx == CHIP_IDX_RT9120S) {
snd_soc_component_write(comp, RT9120_REG_INTERCFG, 0xde);
snd_soc_component_write(comp, RT9120_REG_INTERNAL0, 0x66);
} else
snd_soc_component_write(comp, RT9120_REG_INTERNAL0, 0x04);
pm_runtime_mark_last_busy(comp->dev);
pm_runtime_put(comp->dev);
return 0;
}
static int rt9120_codec_suspend(struct snd_soc_component *comp)
{
return pm_runtime_force_suspend(comp->dev);
}
static int rt9120_codec_resume(struct snd_soc_component *comp)
{
return pm_runtime_force_resume(comp->dev);
}
static const struct snd_soc_component_driver rt9120_component_driver = {
.probe = rt9120_codec_probe,
.suspend = rt9120_codec_suspend,
.resume = rt9120_codec_resume,
.controls = rt9120_snd_controls,
.num_controls = ARRAY_SIZE(rt9120_snd_controls),
.dapm_widgets = rt9120_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt9120_dapm_widgets),
.dapm_routes = rt9120_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(rt9120_dapm_routes),
.endianness = 1,
};
static int rt9120_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *comp = dai->component;
unsigned int format;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
format = RT9120_CFG_FMT_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
format = RT9120_CFG_FMT_LEFTJ;
break;
case SND_SOC_DAIFMT_RIGHT_J:
format = RT9120_CFG_FMT_RIGHTJ;
break;
case SND_SOC_DAIFMT_DSP_A:
format = RT9120_CFG_FMT_DSPA;
break;
case SND_SOC_DAIFMT_DSP_B:
format = RT9120_CFG_FMT_DSPB;
break;
default:
dev_err(dai->dev, "Unknown dai format\n");
return -EINVAL;
}
snd_soc_component_update_bits(comp, RT9120_REG_I2SFMT,
RT9120_I2SFMT_MASK,
format << RT9120_I2SFMT_SHIFT);
return 0;
}
static int rt9120_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *param,
struct snd_soc_dai *dai)
{
struct snd_soc_component *comp = dai->component;
unsigned int param_width, param_slot_width, auto_sync;
int width, fs;
switch (width = params_width(param)) {
case 16:
param_width = RT9120_CFG_AUDBIT_16;
break;
case 20:
param_width = RT9120_CFG_AUDBIT_20;
break;
case 24:
case 32:
param_width = RT9120_CFG_AUDBIT_24;
break;
default:
dev_err(dai->dev, "Unsupported data width [%d]\n", width);
return -EINVAL;
}
snd_soc_component_update_bits(comp, RT9120_REG_I2SFMT,
RT9120_AUDBIT_MASK, param_width);
switch (width = params_physical_width(param)) {
case 16:
param_slot_width = RT9120_CFG_WORDLEN_16;
break;
case 24:
param_slot_width = RT9120_CFG_WORDLEN_24;
break;
case 32:
param_slot_width = RT9120_CFG_WORDLEN_32;
break;
default:
dev_err(dai->dev, "Unsupported slot width [%d]\n", width);
return -EINVAL;
}
snd_soc_component_update_bits(comp, RT9120_REG_I2SWL,
RT9120_AUDWL_MASK, param_slot_width);
fs = width * params_channels(param);
/* If fs is divided by 48, disable auto sync */
if (fs % 48 == 0)
auto_sync = 0;
else
auto_sync = RT9120_AUTOSYNC_MASK;
snd_soc_component_update_bits(comp, RT9120_REG_DIGCFG,
RT9120_AUTOSYNC_MASK, auto_sync);
return 0;
}
static const struct snd_soc_dai_ops rt9120_dai_ops = {
.set_fmt = rt9120_set_fmt,
.hw_params = rt9120_hw_params,
};
static struct snd_soc_dai_driver rt9120_dai = {
.name = "rt9120_aif",
.playback = {
.stream_name = "AIF Playback",
.rates = RT9120_RATES_MASK,
.formats = RT9120_FMTS_MASK,
.rate_max = 192000,
.rate_min = 8000,
.channels_min = 1,
.channels_max = 2,
},
.capture = {
.stream_name = "AIF Capture",
.rates = RT9120_RATES_MASK,
.formats = RT9120_FMTS_MASK,
.rate_max = 192000,
.rate_min = 8000,
.channels_min = 1,
.channels_max = 2,
},
.ops = &rt9120_dai_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
};
static const struct regmap_range rt9120_rd_yes_ranges[] = {
regmap_reg_range(0x00, 0x0C),
regmap_reg_range(0x10, 0x15),
regmap_reg_range(0x20, 0x27),
regmap_reg_range(0x30, 0x38),
regmap_reg_range(0x3A, 0x40),
regmap_reg_range(0x63, 0x63),
regmap_reg_range(0x65, 0x65),
regmap_reg_range(0x69, 0x69),
regmap_reg_range(0x6C, 0x6C),
regmap_reg_range(0xF8, 0xF8)
};
static const struct regmap_access_table rt9120_rd_table = {
.yes_ranges = rt9120_rd_yes_ranges,
.n_yes_ranges = ARRAY_SIZE(rt9120_rd_yes_ranges),
};
static const struct regmap_range rt9120_wr_yes_ranges[] = {
regmap_reg_range(0x00, 0x00),
regmap_reg_range(0x02, 0x0A),
regmap_reg_range(0x10, 0x15),
regmap_reg_range(0x20, 0x27),
regmap_reg_range(0x30, 0x38),
regmap_reg_range(0x3A, 0x3D),
regmap_reg_range(0x40, 0x40),
regmap_reg_range(0x63, 0x63),
regmap_reg_range(0x65, 0x65),
regmap_reg_range(0x69, 0x69),
regmap_reg_range(0x6C, 0x6C),
regmap_reg_range(0xF8, 0xF8)
};
static const struct regmap_access_table rt9120_wr_table = {
.yes_ranges = rt9120_wr_yes_ranges,
.n_yes_ranges = ARRAY_SIZE(rt9120_wr_yes_ranges),
};
static bool rt9120_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x00 ... 0x01:
case 0x10:
case 0x30 ... 0x40:
return true;
default:
return false;
}
}
static int rt9120_get_reg_size(unsigned int reg)
{
switch (reg) {
case 0x00:
case 0x20 ... 0x27:
return 2;
case 0x30 ... 0x3D:
return 3;
case 0x3E ... 0x3F:
return 4;
default:
return 1;
}
}
static int rt9120_reg_read(void *context, unsigned int reg, unsigned int *val)
{
struct rt9120_data *data = context;
struct i2c_client *i2c = to_i2c_client(data->dev);
int size = rt9120_get_reg_size(reg);
u8 raw[4] = {0};
int ret;
ret = i2c_smbus_read_i2c_block_data(i2c, reg, size, raw);
if (ret < 0)
return ret;
else if (ret != size)
return -EIO;
switch (size) {
case 4:
*val = be32_to_cpup((__be32 *)raw);
break;
case 3:
*val = raw[0] << 16 | raw[1] << 8 | raw[2];
break;
case 2:
*val = be16_to_cpup((__be16 *)raw);
break;
default:
*val = raw[0];
}
return 0;
}
static int rt9120_reg_write(void *context, unsigned int reg, unsigned int val)
{
struct rt9120_data *data = context;
struct i2c_client *i2c = to_i2c_client(data->dev);
int size = rt9120_get_reg_size(reg);
__be32 be32_val;
u8 *rawp = (u8 *)&be32_val;
int offs = 4 - size;
be32_val = cpu_to_be32(val);
return i2c_smbus_write_i2c_block_data(i2c, reg, size, rawp + offs);
}
static const struct reg_default rt9120_reg_defaults[] = {
{ .reg = 0x02, .def = 0x02 },
{ .reg = 0x03, .def = 0xf2 },
{ .reg = 0x04, .def = 0x01 },
{ .reg = 0x05, .def = 0xc0 },
{ .reg = 0x06, .def = 0x28 },
{ .reg = 0x07, .def = 0x04 },
{ .reg = 0x08, .def = 0xff },
{ .reg = 0x09, .def = 0x01 },
{ .reg = 0x0a, .def = 0x01 },
{ .reg = 0x0b, .def = 0x00 },
{ .reg = 0x0c, .def = 0x04 },
{ .reg = 0x11, .def = 0x30 },
{ .reg = 0x12, .def = 0x08 },
{ .reg = 0x13, .def = 0x12 },
{ .reg = 0x14, .def = 0x09 },
{ .reg = 0x15, .def = 0x00 },
{ .reg = 0x20, .def = 0x7ff },
{ .reg = 0x21, .def = 0x180 },
{ .reg = 0x22, .def = 0x180 },
{ .reg = 0x23, .def = 0x00 },
{ .reg = 0x24, .def = 0x80 },
{ .reg = 0x25, .def = 0x180 },
{ .reg = 0x26, .def = 0x640 },
{ .reg = 0x27, .def = 0x180 },
{ .reg = 0x63, .def = 0x5e },
{ .reg = 0x65, .def = 0x66 },
{ .reg = 0x6c, .def = 0xe0 },
{ .reg = 0xf8, .def = 0x44 },
};
static const struct regmap_config rt9120_regmap_config = {
.reg_bits = 8,
.val_bits = 32,
.max_register = RT9120_REG_DIGCFG,
.reg_defaults = rt9120_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(rt9120_reg_defaults),
.cache_type = REGCACHE_RBTREE,
.reg_read = rt9120_reg_read,
.reg_write = rt9120_reg_write,
.volatile_reg = rt9120_volatile_reg,
.wr_table = &rt9120_wr_table,
.rd_table = &rt9120_rd_table,
};
static int rt9120_check_vendor_info(struct rt9120_data *data)
{
unsigned int devid;
int ret;
ret = regmap_read(data->regmap, RT9120_REG_DEVID, &devid);
if (ret)
return ret;
devid = FIELD_GET(RT9120_VID_MASK, devid);
switch (devid) {
case RT9120_VENDOR_ID:
data->chip_idx = CHIP_IDX_RT9120;
break;
case RT9120S_VENDOR_ID:
data->chip_idx = CHIP_IDX_RT9120S;
break;
default:
dev_err(data->dev, "DEVID not correct [0x%0x]\n", devid);
return -ENODEV;
}
return 0;
}
static int rt9120_do_register_reset(struct rt9120_data *data)
{
int ret;
ret = regmap_write(data->regmap, RT9120_REG_SWRESET,
RT9120_SWRST_MASK);
if (ret)
return ret;
msleep(RT9120_RESET_WAITMS);
return 0;
}
static int rt9120_probe(struct i2c_client *i2c)
{
struct rt9120_data *data;
struct regulator *dvdd_supply;
int dvdd_supply_volt, ret;
data = devm_kzalloc(&i2c->dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->dev = &i2c->dev;
i2c_set_clientdata(i2c, data);
data->pwdnn_gpio = devm_gpiod_get_optional(&i2c->dev, "pwdnn",
GPIOD_OUT_HIGH);
if (IS_ERR(data->pwdnn_gpio)) {
dev_err(&i2c->dev, "Failed to initialize 'pwdnn' gpio\n");
return PTR_ERR(data->pwdnn_gpio);
} else if (data->pwdnn_gpio) {
dev_dbg(&i2c->dev, "'pwdnn' from low to high, wait chip on\n");
msleep(RT9120_CHIPON_WAITMS);
}
data->regmap = devm_regmap_init(&i2c->dev, NULL, data,
&rt9120_regmap_config);
if (IS_ERR(data->regmap)) {
ret = PTR_ERR(data->regmap);
dev_err(&i2c->dev, "Failed to init regmap [%d]\n", ret);
return ret;
}
ret = rt9120_check_vendor_info(data);
if (ret) {
dev_err(&i2c->dev, "Failed to check vendor info\n");
return ret;
}
ret = rt9120_do_register_reset(data);
if (ret) {
dev_err(&i2c->dev, "Failed to do register reset\n");
return ret;
}
dvdd_supply = devm_regulator_get(&i2c->dev, "dvdd");
if (IS_ERR(dvdd_supply)) {
dev_err(&i2c->dev, "No dvdd regulator found\n");
return PTR_ERR(dvdd_supply);
}
dvdd_supply_volt = regulator_get_voltage(dvdd_supply);
if (dvdd_supply_volt <= RT9120_LVAPP_THRESUV) {
dev_dbg(&i2c->dev, "dvdd low voltage design\n");
ret = regmap_update_bits(data->regmap, RT9120_REG_UVPOPT,
RT9120_DVDD_UVSEL_MASK, 0);
if (ret) {
dev_err(&i2c->dev, "Failed to config dvdd uvsel\n");
return ret;
}
}
pm_runtime_set_autosuspend_delay(&i2c->dev, 1000);
pm_runtime_use_autosuspend(&i2c->dev);
pm_runtime_set_active(&i2c->dev);
pm_runtime_mark_last_busy(&i2c->dev);
pm_runtime_enable(&i2c->dev);
return devm_snd_soc_register_component(&i2c->dev,
&rt9120_component_driver,
&rt9120_dai, 1);
}
static void rt9120_remove(struct i2c_client *i2c)
{
pm_runtime_disable(&i2c->dev);
pm_runtime_set_suspended(&i2c->dev);
}
static int __maybe_unused rt9120_runtime_suspend(struct device *dev)
{
struct rt9120_data *data = dev_get_drvdata(dev);
if (data->pwdnn_gpio) {
regcache_cache_only(data->regmap, true);
regcache_mark_dirty(data->regmap);
gpiod_set_value(data->pwdnn_gpio, 0);
}
return 0;
}
static int __maybe_unused rt9120_runtime_resume(struct device *dev)
{
struct rt9120_data *data = dev_get_drvdata(dev);
if (data->pwdnn_gpio) {
gpiod_set_value(data->pwdnn_gpio, 1);
msleep(RT9120_CHIPON_WAITMS);
regcache_cache_only(data->regmap, false);
regcache_sync(data->regmap);
}
return 0;
}
static const struct dev_pm_ops rt9120_pm_ops = {
SET_RUNTIME_PM_OPS(rt9120_runtime_suspend, rt9120_runtime_resume, NULL)
};
static const struct of_device_id __maybe_unused rt9120_device_table[] = {
{ .compatible = "richtek,rt9120", },
{ }
};
MODULE_DEVICE_TABLE(of, rt9120_device_table);
static struct i2c_driver rt9120_driver = {
.driver = {
.name = "rt9120",
.of_match_table = rt9120_device_table,
.pm = &rt9120_pm_ops,
},
.probe = rt9120_probe,
.remove = rt9120_remove,
};
module_i2c_driver(rt9120_driver);
MODULE_AUTHOR("ChiYuan Huang <[email protected]>");
MODULE_DESCRIPTION("RT9120 Audio Amplifier Driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/rt9120.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8731.c -- WM8731 ALSA SoC Audio driver
*
* Copyright 2005 Openedhand Ltd.
* Copyright 2006-12 Wolfson Microelectronics, plc
*
* Author: Richard Purdie <[email protected]>
*
* Based on wm8753.c by Liam Girdwood
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/slab.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/clk.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "wm8731.h"
static const char *wm8731_supply_names[WM8731_NUM_SUPPLIES] = {
"AVDD",
"HPVDD",
"DCVDD",
"DBVDD",
};
/*
* wm8731 register cache
*/
static const struct reg_default wm8731_reg_defaults[] = {
{ 0, 0x0097 },
{ 1, 0x0097 },
{ 2, 0x0079 },
{ 3, 0x0079 },
{ 4, 0x000a },
{ 5, 0x0008 },
{ 6, 0x009f },
{ 7, 0x000a },
{ 8, 0x0000 },
{ 9, 0x0000 },
};
static bool wm8731_volatile(struct device *dev, unsigned int reg)
{
return reg == WM8731_RESET;
}
#define wm8731_reset(m) regmap_write(m, WM8731_RESET, 0)
static const char *wm8731_input_select[] = {"Line In", "Mic"};
static SOC_ENUM_SINGLE_DECL(wm8731_insel_enum,
WM8731_APANA, 2, wm8731_input_select);
static int wm8731_deemph[] = { 0, 32000, 44100, 48000 };
static int wm8731_set_deemph(struct snd_soc_component *component)
{
struct wm8731_priv *wm8731 = snd_soc_component_get_drvdata(component);
int val, i, best;
/* If we're using deemphasis select the nearest available sample
* rate.
*/
if (wm8731->deemph) {
best = 1;
for (i = 2; i < ARRAY_SIZE(wm8731_deemph); i++) {
if (abs(wm8731_deemph[i] - wm8731->playback_fs) <
abs(wm8731_deemph[best] - wm8731->playback_fs))
best = i;
}
val = best << 1;
} else {
best = 0;
val = 0;
}
dev_dbg(component->dev, "Set deemphasis %d (%dHz)\n",
best, wm8731_deemph[best]);
return snd_soc_component_update_bits(component, WM8731_APDIGI, 0x6, val);
}
static int wm8731_get_deemph(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8731_priv *wm8731 = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = wm8731->deemph;
return 0;
}
static int wm8731_put_deemph(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8731_priv *wm8731 = snd_soc_component_get_drvdata(component);
unsigned int deemph = ucontrol->value.integer.value[0];
int ret = 0;
if (deemph > 1)
return -EINVAL;
mutex_lock(&wm8731->lock);
if (wm8731->deemph != deemph) {
wm8731->deemph = deemph;
wm8731_set_deemph(component);
ret = 1;
}
mutex_unlock(&wm8731->lock);
return ret;
}
static const DECLARE_TLV_DB_SCALE(in_tlv, -3450, 150, 0);
static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -1500, 300, 0);
static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 2000, 0);
static const struct snd_kcontrol_new wm8731_snd_controls[] = {
SOC_DOUBLE_R_TLV("Master Playback Volume", WM8731_LOUT1V, WM8731_ROUT1V,
0, 127, 0, out_tlv),
SOC_DOUBLE_R("Master Playback ZC Switch", WM8731_LOUT1V, WM8731_ROUT1V,
7, 1, 0),
SOC_DOUBLE_R_TLV("Capture Volume", WM8731_LINVOL, WM8731_RINVOL, 0, 31, 0,
in_tlv),
SOC_DOUBLE_R("Line Capture Switch", WM8731_LINVOL, WM8731_RINVOL, 7, 1, 1),
SOC_SINGLE_TLV("Mic Boost Volume", WM8731_APANA, 0, 1, 0, mic_tlv),
SOC_SINGLE("Mic Capture Switch", WM8731_APANA, 1, 1, 1),
SOC_SINGLE_TLV("Sidetone Playback Volume", WM8731_APANA, 6, 3, 1,
sidetone_tlv),
SOC_SINGLE("ADC High Pass Filter Switch", WM8731_APDIGI, 0, 1, 1),
SOC_SINGLE("Store DC Offset Switch", WM8731_APDIGI, 4, 1, 0),
SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
wm8731_get_deemph, wm8731_put_deemph),
};
/* Output Mixer */
static const struct snd_kcontrol_new wm8731_output_mixer_controls[] = {
SOC_DAPM_SINGLE("Line Bypass Switch", WM8731_APANA, 3, 1, 0),
SOC_DAPM_SINGLE("Mic Sidetone Switch", WM8731_APANA, 5, 1, 0),
SOC_DAPM_SINGLE("HiFi Playback Switch", WM8731_APANA, 4, 1, 0),
};
/* Input mux */
static const struct snd_kcontrol_new wm8731_input_mux_controls =
SOC_DAPM_ENUM("Input Select", wm8731_insel_enum);
static const struct snd_soc_dapm_widget wm8731_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("ACTIVE",WM8731_ACTIVE, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("OSC", WM8731_PWR, 5, 1, NULL, 0),
SND_SOC_DAPM_MIXER("Output Mixer", WM8731_PWR, 4, 1,
&wm8731_output_mixer_controls[0],
ARRAY_SIZE(wm8731_output_mixer_controls)),
SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM8731_PWR, 3, 1),
SND_SOC_DAPM_OUTPUT("LOUT"),
SND_SOC_DAPM_OUTPUT("LHPOUT"),
SND_SOC_DAPM_OUTPUT("ROUT"),
SND_SOC_DAPM_OUTPUT("RHPOUT"),
SND_SOC_DAPM_ADC("ADC", "HiFi Capture", WM8731_PWR, 2, 1),
SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0, &wm8731_input_mux_controls),
SND_SOC_DAPM_PGA("Line Input", WM8731_PWR, 0, 1, NULL, 0),
SND_SOC_DAPM_MICBIAS("Mic Bias", WM8731_PWR, 1, 1),
SND_SOC_DAPM_INPUT("MICIN"),
SND_SOC_DAPM_INPUT("RLINEIN"),
SND_SOC_DAPM_INPUT("LLINEIN"),
};
static int wm8731_check_osc(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
struct wm8731_priv *wm8731 = snd_soc_component_get_drvdata(component);
return wm8731->sysclk_type == WM8731_SYSCLK_XTAL;
}
static const struct snd_soc_dapm_route wm8731_intercon[] = {
{"DAC", NULL, "OSC", wm8731_check_osc},
{"ADC", NULL, "OSC", wm8731_check_osc},
{"DAC", NULL, "ACTIVE"},
{"ADC", NULL, "ACTIVE"},
/* output mixer */
{"Output Mixer", "Line Bypass Switch", "Line Input"},
{"Output Mixer", "HiFi Playback Switch", "DAC"},
{"Output Mixer", "Mic Sidetone Switch", "Mic Bias"},
/* outputs */
{"RHPOUT", NULL, "Output Mixer"},
{"ROUT", NULL, "Output Mixer"},
{"LHPOUT", NULL, "Output Mixer"},
{"LOUT", NULL, "Output Mixer"},
/* input mux */
{"Input Mux", "Line In", "Line Input"},
{"Input Mux", "Mic", "Mic Bias"},
{"ADC", NULL, "Input Mux"},
/* inputs */
{"Line Input", NULL, "LLINEIN"},
{"Line Input", NULL, "RLINEIN"},
{"Mic Bias", NULL, "MICIN"},
};
struct _coeff_div {
u32 mclk;
u32 rate;
u16 fs;
u8 sr:4;
u8 bosr:1;
u8 usb:1;
};
/* codec mclk clock divider coefficients */
static const struct _coeff_div coeff_div[] = {
/* 48k */
{12288000, 48000, 256, 0x0, 0x0, 0x0},
{18432000, 48000, 384, 0x0, 0x1, 0x0},
{12000000, 48000, 250, 0x0, 0x0, 0x1},
/* 32k */
{12288000, 32000, 384, 0x6, 0x0, 0x0},
{18432000, 32000, 576, 0x6, 0x1, 0x0},
{12000000, 32000, 375, 0x6, 0x0, 0x1},
/* 8k */
{12288000, 8000, 1536, 0x3, 0x0, 0x0},
{18432000, 8000, 2304, 0x3, 0x1, 0x0},
{11289600, 8000, 1408, 0xb, 0x0, 0x0},
{16934400, 8000, 2112, 0xb, 0x1, 0x0},
{12000000, 8000, 1500, 0x3, 0x0, 0x1},
/* 96k */
{12288000, 96000, 128, 0x7, 0x0, 0x0},
{18432000, 96000, 192, 0x7, 0x1, 0x0},
{12000000, 96000, 125, 0x7, 0x0, 0x1},
/* 44.1k */
{11289600, 44100, 256, 0x8, 0x0, 0x0},
{16934400, 44100, 384, 0x8, 0x1, 0x0},
{12000000, 44100, 272, 0x8, 0x1, 0x1},
/* 88.2k */
{11289600, 88200, 128, 0xf, 0x0, 0x0},
{16934400, 88200, 192, 0xf, 0x1, 0x0},
{12000000, 88200, 136, 0xf, 0x1, 0x1},
};
/* rates constraints */
static const unsigned int wm8731_rates_12000000[] = {
8000, 32000, 44100, 48000, 96000, 88200,
};
static const unsigned int wm8731_rates_12288000_18432000[] = {
8000, 32000, 48000, 96000,
};
static const unsigned int wm8731_rates_11289600_16934400[] = {
8000, 44100, 88200,
};
static const struct snd_pcm_hw_constraint_list wm8731_constraints_12000000 = {
.list = wm8731_rates_12000000,
.count = ARRAY_SIZE(wm8731_rates_12000000),
};
static const
struct snd_pcm_hw_constraint_list wm8731_constraints_12288000_18432000 = {
.list = wm8731_rates_12288000_18432000,
.count = ARRAY_SIZE(wm8731_rates_12288000_18432000),
};
static const
struct snd_pcm_hw_constraint_list wm8731_constraints_11289600_16934400 = {
.list = wm8731_rates_11289600_16934400,
.count = ARRAY_SIZE(wm8731_rates_11289600_16934400),
};
static inline int get_coeff(int mclk, int rate)
{
int i;
for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
return i;
}
return 0;
}
static int wm8731_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm8731_priv *wm8731 = snd_soc_component_get_drvdata(component);
u16 iface = snd_soc_component_read(component, WM8731_IFACE) & 0xfff3;
int i = get_coeff(wm8731->sysclk, params_rate(params));
u16 srate = (coeff_div[i].sr << 2) |
(coeff_div[i].bosr << 1) | coeff_div[i].usb;
wm8731->playback_fs = params_rate(params);
snd_soc_component_write(component, WM8731_SRATE, srate);
/* bit size */
switch (params_width(params)) {
case 16:
break;
case 20:
iface |= 0x0004;
break;
case 24:
iface |= 0x0008;
break;
case 32:
iface |= 0x000c;
break;
}
wm8731_set_deemph(component);
snd_soc_component_write(component, WM8731_IFACE, iface);
return 0;
}
static int wm8731_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
u16 mute_reg = snd_soc_component_read(component, WM8731_APDIGI) & 0xfff7;
if (mute)
snd_soc_component_write(component, WM8731_APDIGI, mute_reg | 0x8);
else
snd_soc_component_write(component, WM8731_APDIGI, mute_reg);
return 0;
}
static int wm8731_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct wm8731_priv *wm8731 = snd_soc_component_get_drvdata(component);
switch (clk_id) {
case WM8731_SYSCLK_XTAL:
case WM8731_SYSCLK_MCLK:
if (wm8731->mclk && clk_set_rate(wm8731->mclk, freq))
return -EINVAL;
wm8731->sysclk_type = clk_id;
break;
default:
return -EINVAL;
}
switch (freq) {
case 0:
wm8731->constraints = NULL;
break;
case 12000000:
wm8731->constraints = &wm8731_constraints_12000000;
break;
case 12288000:
case 18432000:
wm8731->constraints = &wm8731_constraints_12288000_18432000;
break;
case 16934400:
case 11289600:
wm8731->constraints = &wm8731_constraints_11289600_16934400;
break;
default:
return -EINVAL;
}
wm8731->sysclk = freq;
snd_soc_dapm_sync(dapm);
return 0;
}
static int wm8731_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
u16 iface = 0;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
iface |= 0x0040;
break;
case SND_SOC_DAIFMT_CBC_CFC:
break;
default:
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface |= 0x0002;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
iface |= 0x0001;
break;
case SND_SOC_DAIFMT_DSP_A:
iface |= 0x0013;
break;
case SND_SOC_DAIFMT_DSP_B:
iface |= 0x0003;
break;
default:
return -EINVAL;
}
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
iface |= 0x0090;
break;
case SND_SOC_DAIFMT_IB_NF:
iface |= 0x0080;
break;
case SND_SOC_DAIFMT_NB_IF:
iface |= 0x0010;
break;
default:
return -EINVAL;
}
/* set iface */
snd_soc_component_write(component, WM8731_IFACE, iface);
return 0;
}
static int wm8731_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct wm8731_priv *wm8731 = snd_soc_component_get_drvdata(component);
int ret;
u16 reg;
switch (level) {
case SND_SOC_BIAS_ON:
if (wm8731->mclk) {
ret = clk_prepare_enable(wm8731->mclk);
if (ret)
return ret;
}
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
ret = regulator_bulk_enable(ARRAY_SIZE(wm8731->supplies),
wm8731->supplies);
if (ret != 0)
return ret;
regcache_sync(wm8731->regmap);
}
/* Clear PWROFF, gate CLKOUT, everything else as-is */
reg = snd_soc_component_read(component, WM8731_PWR) & 0xff7f;
snd_soc_component_write(component, WM8731_PWR, reg | 0x0040);
break;
case SND_SOC_BIAS_OFF:
if (wm8731->mclk)
clk_disable_unprepare(wm8731->mclk);
snd_soc_component_write(component, WM8731_PWR, 0xffff);
regulator_bulk_disable(ARRAY_SIZE(wm8731->supplies),
wm8731->supplies);
regcache_mark_dirty(wm8731->regmap);
break;
}
return 0;
}
static int wm8731_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct wm8731_priv *wm8731 = snd_soc_component_get_drvdata(dai->component);
if (wm8731->constraints)
snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
wm8731->constraints);
return 0;
}
#define WM8731_RATES SNDRV_PCM_RATE_8000_96000
#define WM8731_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops wm8731_dai_ops = {
.startup = wm8731_startup,
.hw_params = wm8731_hw_params,
.mute_stream = wm8731_mute,
.set_sysclk = wm8731_set_dai_sysclk,
.set_fmt = wm8731_set_dai_fmt,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver wm8731_dai = {
.name = "wm8731-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM8731_RATES,
.formats = WM8731_FORMATS,},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM8731_RATES,
.formats = WM8731_FORMATS,},
.ops = &wm8731_dai_ops,
.symmetric_rate = 1,
};
static const struct snd_soc_component_driver soc_component_dev_wm8731 = {
.set_bias_level = wm8731_set_bias_level,
.controls = wm8731_snd_controls,
.num_controls = ARRAY_SIZE(wm8731_snd_controls),
.dapm_widgets = wm8731_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8731_dapm_widgets),
.dapm_routes = wm8731_intercon,
.num_dapm_routes = ARRAY_SIZE(wm8731_intercon),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
int wm8731_init(struct device *dev, struct wm8731_priv *wm8731)
{
int ret = 0, i;
wm8731->mclk = devm_clk_get(dev, "mclk");
if (IS_ERR(wm8731->mclk)) {
ret = PTR_ERR(wm8731->mclk);
if (ret == -ENOENT) {
wm8731->mclk = NULL;
dev_warn(dev, "Assuming static MCLK\n");
} else {
dev_err(dev, "Failed to get MCLK: %d\n", ret);
return ret;
}
}
mutex_init(&wm8731->lock);
for (i = 0; i < ARRAY_SIZE(wm8731->supplies); i++)
wm8731->supplies[i].supply = wm8731_supply_names[i];
ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(wm8731->supplies),
wm8731->supplies);
if (ret != 0) {
dev_err(dev, "Failed to request supplies: %d\n", ret);
return ret;
}
ret = regulator_bulk_enable(ARRAY_SIZE(wm8731->supplies),
wm8731->supplies);
if (ret != 0) {
dev_err(dev, "Failed to enable supplies: %d\n", ret);
return ret;
}
ret = wm8731_reset(wm8731->regmap);
if (ret < 0) {
dev_err(dev, "Failed to issue reset: %d\n", ret);
goto err_regulator_enable;
}
/* Clear POWEROFF, keep everything else disabled */
regmap_write(wm8731->regmap, WM8731_PWR, 0x7f);
/* Latch the update bits */
regmap_update_bits(wm8731->regmap, WM8731_LOUT1V, 0x100, 0);
regmap_update_bits(wm8731->regmap, WM8731_ROUT1V, 0x100, 0);
regmap_update_bits(wm8731->regmap, WM8731_LINVOL, 0x100, 0);
regmap_update_bits(wm8731->regmap, WM8731_RINVOL, 0x100, 0);
/* Disable bypass path by default */
regmap_update_bits(wm8731->regmap, WM8731_APANA, 0x8, 0);
regcache_mark_dirty(wm8731->regmap);
ret = devm_snd_soc_register_component(dev,
&soc_component_dev_wm8731, &wm8731_dai, 1);
if (ret != 0) {
dev_err(dev, "Failed to register CODEC: %d\n", ret);
goto err_regulator_enable;
}
return 0;
err_regulator_enable:
/* Regulators will be enabled by bias management */
regulator_bulk_disable(ARRAY_SIZE(wm8731->supplies), wm8731->supplies);
return ret;
}
EXPORT_SYMBOL_GPL(wm8731_init);
const struct regmap_config wm8731_regmap = {
.reg_bits = 7,
.val_bits = 9,
.max_register = WM8731_RESET,
.volatile_reg = wm8731_volatile,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = wm8731_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8731_reg_defaults),
};
EXPORT_SYMBOL_GPL(wm8731_regmap);
MODULE_DESCRIPTION("ASoC WM8731 driver");
MODULE_AUTHOR("Richard Purdie");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8731.c |
// SPDX-License-Identifier: GPL-2.0
//
// Analog Devices ADAU7118 8 channel PDM-to-I2S/TDM Converter driver over I2C
//
// Copyright 2019 Analog Devices Inc.
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include "adau7118.h"
static const struct reg_default adau7118_reg_defaults[] = {
{ ADAU7118_REG_VENDOR_ID, 0x41 },
{ ADAU7118_REG_DEVICE_ID1, 0x71 },
{ ADAU7118_REG_DEVICE_ID2, 0x18 },
{ ADAU7118_REG_REVISION_ID, 0x00 },
{ ADAU7118_REG_ENABLES, 0x3F },
{ ADAU7118_REG_DEC_RATIO_CLK_MAP, 0xC0 },
{ ADAU7118_REG_HPF_CONTROL, 0xD0 },
{ ADAU7118_REG_SPT_CTRL1, 0x41 },
{ ADAU7118_REG_SPT_CTRL2, 0x00 },
{ ADAU7118_REG_SPT_CX(0), 0x01 },
{ ADAU7118_REG_SPT_CX(1), 0x11 },
{ ADAU7118_REG_SPT_CX(2), 0x21 },
{ ADAU7118_REG_SPT_CX(3), 0x31 },
{ ADAU7118_REG_SPT_CX(4), 0x41 },
{ ADAU7118_REG_SPT_CX(5), 0x51 },
{ ADAU7118_REG_SPT_CX(6), 0x61 },
{ ADAU7118_REG_SPT_CX(7), 0x71 },
{ ADAU7118_REG_DRIVE_STRENGTH, 0x2a },
{ ADAU7118_REG_RESET, 0x00 },
};
static bool adau7118_volatile(struct device *dev, unsigned int reg)
{
return (reg == ADAU7118_REG_RESET);
}
static const struct regmap_config adau7118_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.reg_defaults = adau7118_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(adau7118_reg_defaults),
.cache_type = REGCACHE_MAPLE,
.max_register = ADAU7118_REG_RESET,
.volatile_reg = adau7118_volatile,
};
static int adau7118_probe_i2c(struct i2c_client *i2c)
{
struct regmap *map;
map = devm_regmap_init_i2c(i2c, &adau7118_regmap_config);
if (IS_ERR(map)) {
dev_err(&i2c->dev, "Failed to init regmap %ld\n", PTR_ERR(map));
return PTR_ERR(map);
}
return adau7118_probe(&i2c->dev, map, false);
}
static const struct of_device_id adau7118_of_match[] = {
{ .compatible = "adi,adau7118" },
{}
};
MODULE_DEVICE_TABLE(of, adau7118_of_match);
static const struct i2c_device_id adau7118_id[] = {
{"adau7118", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, adau7118_id);
static struct i2c_driver adau7118_driver = {
.driver = {
.name = "adau7118",
.of_match_table = adau7118_of_match,
},
.probe = adau7118_probe_i2c,
.id_table = adau7118_id,
};
module_i2c_driver(adau7118_driver);
MODULE_AUTHOR("Nuno Sa <[email protected]>");
MODULE_DESCRIPTION("ADAU7118 8 channel PDM-to-I2S/TDM Converter driver over I2C");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/adau7118-i2c.c |
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright (c) 2018 BayLibre, SAS.
// Author: Jerome Brunet <[email protected]>
#include <linux/gpio/consumer.h>
#include <linux/of_platform.h>
#include <linux/module.h>
#include <sound/soc.h>
struct es7241_clock_mode {
unsigned int rate_min;
unsigned int rate_max;
unsigned int *slv_mfs;
unsigned int slv_mfs_num;
unsigned int mst_mfs;
unsigned int mst_m0:1;
unsigned int mst_m1:1;
};
struct es7241_chip {
const struct es7241_clock_mode *modes;
unsigned int mode_num;
};
struct es7241_data {
struct gpio_desc *reset;
struct gpio_desc *m0;
struct gpio_desc *m1;
unsigned int fmt;
unsigned int mclk;
bool is_consumer;
const struct es7241_chip *chip;
};
static void es7241_set_mode(struct es7241_data *priv, int m0, int m1)
{
/* put the device in reset */
gpiod_set_value_cansleep(priv->reset, 0);
/* set the mode */
gpiod_set_value_cansleep(priv->m0, m0);
gpiod_set_value_cansleep(priv->m1, m1);
/* take the device out of reset - datasheet does not specify a delay */
gpiod_set_value_cansleep(priv->reset, 1);
}
static int es7241_set_consumer_mode(struct es7241_data *priv,
const struct es7241_clock_mode *mode,
unsigned int mfs)
{
int j;
if (!mfs)
goto out_ok;
for (j = 0; j < mode->slv_mfs_num; j++) {
if (mode->slv_mfs[j] == mfs)
goto out_ok;
}
return -EINVAL;
out_ok:
es7241_set_mode(priv, 1, 1);
return 0;
}
static int es7241_set_provider_mode(struct es7241_data *priv,
const struct es7241_clock_mode *mode,
unsigned int mfs)
{
/*
* We can't really set clock ratio, if the mclk/lrclk is different
* from what we provide, then error out
*/
if (mfs && mfs != mode->mst_mfs)
return -EINVAL;
es7241_set_mode(priv, mode->mst_m0, mode->mst_m1);
return 0;
}
static int es7241_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct es7241_data *priv = snd_soc_dai_get_drvdata(dai);
unsigned int rate = params_rate(params);
unsigned int mfs = priv->mclk / rate;
int i;
for (i = 0; i < priv->chip->mode_num; i++) {
const struct es7241_clock_mode *mode = &priv->chip->modes[i];
if (rate < mode->rate_min || rate >= mode->rate_max)
continue;
if (priv->is_consumer)
return es7241_set_consumer_mode(priv, mode, mfs);
else
return es7241_set_provider_mode(priv, mode, mfs);
}
/* should not happen */
dev_err(dai->dev, "unsupported rate: %u\n", rate);
return -EINVAL;
}
static int es7241_set_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct es7241_data *priv = snd_soc_dai_get_drvdata(dai);
if (dir == SND_SOC_CLOCK_IN && clk_id == 0) {
priv->mclk = freq;
return 0;
}
return -ENOTSUPP;
}
static int es7241_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct es7241_data *priv = snd_soc_dai_get_drvdata(dai);
if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF) {
dev_err(dai->dev, "Unsupported dai clock inversion\n");
return -EINVAL;
}
if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) != priv->fmt) {
dev_err(dai->dev, "Invalid dai format\n");
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC:
priv->is_consumer = true;
break;
case SND_SOC_DAIFMT_CBP_CFP:
priv->is_consumer = false;
break;
default:
dev_err(dai->dev, "Unsupported clock configuration\n");
return -EINVAL;
}
return 0;
}
static const struct snd_soc_dai_ops es7241_dai_ops = {
.set_fmt = es7241_set_fmt,
.hw_params = es7241_hw_params,
.set_sysclk = es7241_set_sysclk,
};
static struct snd_soc_dai_driver es7241_dai = {
.name = "es7241-hifi",
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = (SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_3LE |
SNDRV_PCM_FMTBIT_S24_LE),
},
.ops = &es7241_dai_ops,
};
static const struct es7241_clock_mode es7241_modes[] = {
{
/* Single speed mode */
.rate_min = 8000,
.rate_max = 50000,
.slv_mfs = (unsigned int[]) { 256, 384, 512, 768, 1024 },
.slv_mfs_num = 5,
.mst_mfs = 256,
.mst_m0 = 0,
.mst_m1 = 0,
}, {
/* Double speed mode */
.rate_min = 50000,
.rate_max = 100000,
.slv_mfs = (unsigned int[]) { 128, 192 },
.slv_mfs_num = 2,
.mst_mfs = 128,
.mst_m0 = 1,
.mst_m1 = 0,
}, {
/* Quad speed mode */
.rate_min = 100000,
.rate_max = 200000,
.slv_mfs = (unsigned int[]) { 64 },
.slv_mfs_num = 1,
.mst_mfs = 64,
.mst_m0 = 0,
.mst_m1 = 1,
},
};
static const struct es7241_chip es7241_chip __maybe_unused = {
.modes = es7241_modes,
.mode_num = ARRAY_SIZE(es7241_modes),
};
static const struct snd_soc_dapm_widget es7241_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("AINL"),
SND_SOC_DAPM_INPUT("AINR"),
SND_SOC_DAPM_DAC("ADC", "Capture", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("VDDP", 0, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("VDDD", 0, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("VDDA", 0, 0),
};
static const struct snd_soc_dapm_route es7241_dapm_routes[] = {
{ "ADC", NULL, "AINL", },
{ "ADC", NULL, "AINR", },
{ "ADC", NULL, "VDDA", },
{ "Capture", NULL, "VDDP", },
{ "Capture", NULL, "VDDD", },
};
static const struct snd_soc_component_driver es7241_component_driver = {
.dapm_widgets = es7241_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(es7241_dapm_widgets),
.dapm_routes = es7241_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(es7241_dapm_routes),
.idle_bias_on = 1,
.endianness = 1,
};
static void es7241_parse_fmt(struct device *dev, struct es7241_data *priv)
{
bool is_leftj;
/*
* The format is given by a pull resistor on the SDOUT pin:
* pull-up for i2s, pull-down for left justified.
*/
is_leftj = of_property_read_bool(dev->of_node,
"everest,sdout-pull-down");
if (is_leftj)
priv->fmt = SND_SOC_DAIFMT_LEFT_J;
else
priv->fmt = SND_SOC_DAIFMT_I2S;
}
static int es7241_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct es7241_data *priv;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
platform_set_drvdata(pdev, priv);
priv->chip = of_device_get_match_data(dev);
if (!priv->chip) {
dev_err(dev, "failed to match device\n");
return -ENODEV;
}
es7241_parse_fmt(dev, priv);
priv->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
if (IS_ERR(priv->reset))
return dev_err_probe(dev, PTR_ERR(priv->reset),
"Failed to get 'reset' gpio");
priv->m0 = devm_gpiod_get_optional(dev, "m0", GPIOD_OUT_LOW);
if (IS_ERR(priv->m0))
return dev_err_probe(dev, PTR_ERR(priv->m0),
"Failed to get 'm0' gpio");
priv->m1 = devm_gpiod_get_optional(dev, "m1", GPIOD_OUT_LOW);
if (IS_ERR(priv->m1))
return dev_err_probe(dev, PTR_ERR(priv->m1),
"Failed to get 'm1' gpio");
return devm_snd_soc_register_component(&pdev->dev,
&es7241_component_driver,
&es7241_dai, 1);
}
#ifdef CONFIG_OF
static const struct of_device_id es7241_ids[] = {
{ .compatible = "everest,es7241", .data = &es7241_chip },
{ }
};
MODULE_DEVICE_TABLE(of, es7241_ids);
#endif
static struct platform_driver es7241_driver = {
.driver = {
.name = "es7241",
.of_match_table = of_match_ptr(es7241_ids),
},
.probe = es7241_probe,
};
module_platform_driver(es7241_driver);
MODULE_DESCRIPTION("ASoC ES7241 audio codec driver");
MODULE_AUTHOR("Jerome Brunet <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/es7241.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* rt5670.c -- RT5670 ALSA SoC audio codec driver
*
* Copyright 2014 Realtek Semiconductor Corp.
* Author: Bard Liao <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/acpi.h>
#include <linux/spi/spi.h>
#include <linux/dmi.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/jack.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "rl6231.h"
#include "rt5670.h"
#include "rt5670-dsp.h"
#define RT5670_GPIO1_IS_IRQ BIT(0)
#define RT5670_IN2_DIFF BIT(1)
#define RT5670_DMIC_EN BIT(2)
#define RT5670_DMIC1_IN2P BIT(3)
#define RT5670_DMIC1_GPIO6 BIT(4)
#define RT5670_DMIC1_GPIO7 BIT(5)
#define RT5670_DMIC2_INR BIT(6)
#define RT5670_DMIC2_GPIO8 BIT(7)
#define RT5670_DMIC3_GPIO5 BIT(8)
#define RT5670_JD_MODE1 BIT(9)
#define RT5670_JD_MODE2 BIT(10)
#define RT5670_JD_MODE3 BIT(11)
#define RT5670_GPIO1_IS_EXT_SPK_EN BIT(12)
static unsigned long rt5670_quirk;
static unsigned int quirk_override;
module_param_named(quirk, quirk_override, uint, 0444);
MODULE_PARM_DESC(quirk, "Board-specific quirk override");
#define RT5670_DEVICE_ID 0x6271
#define RT5670_PR_RANGE_BASE (0xff + 1)
#define RT5670_PR_SPACING 0x100
#define RT5670_PR_BASE (RT5670_PR_RANGE_BASE + (0 * RT5670_PR_SPACING))
static const struct regmap_range_cfg rt5670_ranges[] = {
{ .name = "PR", .range_min = RT5670_PR_BASE,
.range_max = RT5670_PR_BASE + 0xf8,
.selector_reg = RT5670_PRIV_INDEX,
.selector_mask = 0xff,
.selector_shift = 0x0,
.window_start = RT5670_PRIV_DATA,
.window_len = 0x1, },
};
static const struct reg_sequence init_list[] = {
{ RT5670_PR_BASE + 0x14, 0x9a8a },
{ RT5670_PR_BASE + 0x38, 0x1fe1 },
{ RT5670_PR_BASE + 0x3d, 0x3640 },
{ 0x8a, 0x0123 },
};
static const struct reg_default rt5670_reg[] = {
{ 0x00, 0x0000 },
{ 0x02, 0x8888 },
{ 0x03, 0x8888 },
{ 0x0a, 0x0001 },
{ 0x0b, 0x0827 },
{ 0x0c, 0x0000 },
{ 0x0d, 0x0008 },
{ 0x0e, 0x0000 },
{ 0x0f, 0x0808 },
{ 0x19, 0xafaf },
{ 0x1a, 0xafaf },
{ 0x1b, 0x0011 },
{ 0x1c, 0x2f2f },
{ 0x1d, 0x2f2f },
{ 0x1e, 0x0000 },
{ 0x1f, 0x2f2f },
{ 0x20, 0x0000 },
{ 0x26, 0x7860 },
{ 0x27, 0x7860 },
{ 0x28, 0x7871 },
{ 0x29, 0x8080 },
{ 0x2a, 0x5656 },
{ 0x2b, 0x5454 },
{ 0x2c, 0xaaa0 },
{ 0x2d, 0x0000 },
{ 0x2e, 0x2f2f },
{ 0x2f, 0x1002 },
{ 0x30, 0x0000 },
{ 0x31, 0x5f00 },
{ 0x32, 0x0000 },
{ 0x33, 0x0000 },
{ 0x34, 0x0000 },
{ 0x35, 0x0000 },
{ 0x36, 0x0000 },
{ 0x37, 0x0000 },
{ 0x38, 0x0000 },
{ 0x3b, 0x0000 },
{ 0x3c, 0x007f },
{ 0x3d, 0x0000 },
{ 0x3e, 0x007f },
{ 0x45, 0xe00f },
{ 0x4c, 0x5380 },
{ 0x4f, 0x0073 },
{ 0x52, 0x00d3 },
{ 0x53, 0xf000 },
{ 0x61, 0x0000 },
{ 0x62, 0x0001 },
{ 0x63, 0x00c3 },
{ 0x64, 0x0000 },
{ 0x65, 0x0001 },
{ 0x66, 0x0000 },
{ 0x6f, 0x8000 },
{ 0x70, 0x8000 },
{ 0x71, 0x8000 },
{ 0x72, 0x8000 },
{ 0x73, 0x7770 },
{ 0x74, 0x0e00 },
{ 0x75, 0x1505 },
{ 0x76, 0x0015 },
{ 0x77, 0x0c00 },
{ 0x78, 0x4000 },
{ 0x79, 0x0123 },
{ 0x7f, 0x1100 },
{ 0x80, 0x0000 },
{ 0x81, 0x0000 },
{ 0x82, 0x0000 },
{ 0x83, 0x0000 },
{ 0x84, 0x0000 },
{ 0x85, 0x0000 },
{ 0x86, 0x0004 },
{ 0x87, 0x0000 },
{ 0x88, 0x0000 },
{ 0x89, 0x0000 },
{ 0x8a, 0x0123 },
{ 0x8b, 0x0000 },
{ 0x8c, 0x0003 },
{ 0x8d, 0x0000 },
{ 0x8e, 0x0004 },
{ 0x8f, 0x1100 },
{ 0x90, 0x0646 },
{ 0x91, 0x0c06 },
{ 0x93, 0x0000 },
{ 0x94, 0x1270 },
{ 0x95, 0x1000 },
{ 0x97, 0x0000 },
{ 0x98, 0x0000 },
{ 0x99, 0x0000 },
{ 0x9a, 0x2184 },
{ 0x9b, 0x010a },
{ 0x9c, 0x0aea },
{ 0x9d, 0x000c },
{ 0x9e, 0x0400 },
{ 0xae, 0x7000 },
{ 0xaf, 0x0000 },
{ 0xb0, 0x7000 },
{ 0xb1, 0x0000 },
{ 0xb2, 0x0000 },
{ 0xb3, 0x001f },
{ 0xb4, 0x220c },
{ 0xb5, 0x1f00 },
{ 0xb6, 0x0000 },
{ 0xb7, 0x0000 },
{ 0xbb, 0x0000 },
{ 0xbc, 0x0000 },
{ 0xbd, 0x0000 },
{ 0xbe, 0x0000 },
{ 0xbf, 0x0000 },
{ 0xc0, 0x0000 },
{ 0xc1, 0x0000 },
{ 0xc2, 0x0000 },
{ 0xcd, 0x0000 },
{ 0xce, 0x0000 },
{ 0xcf, 0x1813 },
{ 0xd0, 0x0690 },
{ 0xd1, 0x1c17 },
{ 0xd3, 0xa220 },
{ 0xd4, 0x0000 },
{ 0xd6, 0x0400 },
{ 0xd9, 0x0809 },
{ 0xda, 0x0000 },
{ 0xdb, 0x0001 },
{ 0xdc, 0x0049 },
{ 0xdd, 0x0024 },
{ 0xe6, 0x8000 },
{ 0xe7, 0x0000 },
{ 0xec, 0xa200 },
{ 0xed, 0x0000 },
{ 0xee, 0xa200 },
{ 0xef, 0x0000 },
{ 0xf8, 0x0000 },
{ 0xf9, 0x0000 },
{ 0xfa, 0x8010 },
{ 0xfb, 0x0033 },
{ 0xfc, 0x0100 },
};
static bool rt5670_volatile_register(struct device *dev, unsigned int reg)
{
int i;
for (i = 0; i < ARRAY_SIZE(rt5670_ranges); i++) {
if ((reg >= rt5670_ranges[i].window_start &&
reg <= rt5670_ranges[i].window_start +
rt5670_ranges[i].window_len) ||
(reg >= rt5670_ranges[i].range_min &&
reg <= rt5670_ranges[i].range_max)) {
return true;
}
}
switch (reg) {
case RT5670_RESET:
case RT5670_PDM_DATA_CTRL1:
case RT5670_PDM1_DATA_CTRL4:
case RT5670_PDM2_DATA_CTRL4:
case RT5670_PRIV_DATA:
case RT5670_ASRC_5:
case RT5670_CJ_CTRL1:
case RT5670_CJ_CTRL2:
case RT5670_CJ_CTRL3:
case RT5670_A_JD_CTRL1:
case RT5670_A_JD_CTRL2:
case RT5670_VAD_CTRL5:
case RT5670_ADC_EQ_CTRL1:
case RT5670_EQ_CTRL1:
case RT5670_ALC_CTRL_1:
case RT5670_IRQ_CTRL2:
case RT5670_INT_IRQ_ST:
case RT5670_IL_CMD:
case RT5670_DSP_CTRL1:
case RT5670_DSP_CTRL2:
case RT5670_DSP_CTRL3:
case RT5670_DSP_CTRL4:
case RT5670_DSP_CTRL5:
case RT5670_VENDOR_ID:
case RT5670_VENDOR_ID1:
case RT5670_VENDOR_ID2:
return true;
default:
return false;
}
}
static bool rt5670_readable_register(struct device *dev, unsigned int reg)
{
int i;
for (i = 0; i < ARRAY_SIZE(rt5670_ranges); i++) {
if ((reg >= rt5670_ranges[i].window_start &&
reg <= rt5670_ranges[i].window_start +
rt5670_ranges[i].window_len) ||
(reg >= rt5670_ranges[i].range_min &&
reg <= rt5670_ranges[i].range_max)) {
return true;
}
}
switch (reg) {
case RT5670_RESET:
case RT5670_HP_VOL:
case RT5670_LOUT1:
case RT5670_CJ_CTRL1:
case RT5670_CJ_CTRL2:
case RT5670_CJ_CTRL3:
case RT5670_IN2:
case RT5670_INL1_INR1_VOL:
case RT5670_DAC1_DIG_VOL:
case RT5670_DAC2_DIG_VOL:
case RT5670_DAC_CTRL:
case RT5670_STO1_ADC_DIG_VOL:
case RT5670_MONO_ADC_DIG_VOL:
case RT5670_STO2_ADC_DIG_VOL:
case RT5670_ADC_BST_VOL1:
case RT5670_ADC_BST_VOL2:
case RT5670_STO2_ADC_MIXER:
case RT5670_STO1_ADC_MIXER:
case RT5670_MONO_ADC_MIXER:
case RT5670_AD_DA_MIXER:
case RT5670_STO_DAC_MIXER:
case RT5670_DD_MIXER:
case RT5670_DIG_MIXER:
case RT5670_DSP_PATH1:
case RT5670_DSP_PATH2:
case RT5670_DIG_INF1_DATA:
case RT5670_DIG_INF2_DATA:
case RT5670_PDM_OUT_CTRL:
case RT5670_PDM_DATA_CTRL1:
case RT5670_PDM1_DATA_CTRL2:
case RT5670_PDM1_DATA_CTRL3:
case RT5670_PDM1_DATA_CTRL4:
case RT5670_PDM2_DATA_CTRL2:
case RT5670_PDM2_DATA_CTRL3:
case RT5670_PDM2_DATA_CTRL4:
case RT5670_REC_L1_MIXER:
case RT5670_REC_L2_MIXER:
case RT5670_REC_R1_MIXER:
case RT5670_REC_R2_MIXER:
case RT5670_HPO_MIXER:
case RT5670_MONO_MIXER:
case RT5670_OUT_L1_MIXER:
case RT5670_OUT_R1_MIXER:
case RT5670_LOUT_MIXER:
case RT5670_PWR_DIG1:
case RT5670_PWR_DIG2:
case RT5670_PWR_ANLG1:
case RT5670_PWR_ANLG2:
case RT5670_PWR_MIXER:
case RT5670_PWR_VOL:
case RT5670_PRIV_INDEX:
case RT5670_PRIV_DATA:
case RT5670_I2S4_SDP:
case RT5670_I2S1_SDP:
case RT5670_I2S2_SDP:
case RT5670_I2S3_SDP:
case RT5670_ADDA_CLK1:
case RT5670_ADDA_CLK2:
case RT5670_DMIC_CTRL1:
case RT5670_DMIC_CTRL2:
case RT5670_TDM_CTRL_1:
case RT5670_TDM_CTRL_2:
case RT5670_TDM_CTRL_3:
case RT5670_DSP_CLK:
case RT5670_GLB_CLK:
case RT5670_PLL_CTRL1:
case RT5670_PLL_CTRL2:
case RT5670_ASRC_1:
case RT5670_ASRC_2:
case RT5670_ASRC_3:
case RT5670_ASRC_4:
case RT5670_ASRC_5:
case RT5670_ASRC_7:
case RT5670_ASRC_8:
case RT5670_ASRC_9:
case RT5670_ASRC_10:
case RT5670_ASRC_11:
case RT5670_ASRC_12:
case RT5670_ASRC_13:
case RT5670_ASRC_14:
case RT5670_DEPOP_M1:
case RT5670_DEPOP_M2:
case RT5670_DEPOP_M3:
case RT5670_CHARGE_PUMP:
case RT5670_MICBIAS:
case RT5670_A_JD_CTRL1:
case RT5670_A_JD_CTRL2:
case RT5670_VAD_CTRL1:
case RT5670_VAD_CTRL2:
case RT5670_VAD_CTRL3:
case RT5670_VAD_CTRL4:
case RT5670_VAD_CTRL5:
case RT5670_ADC_EQ_CTRL1:
case RT5670_ADC_EQ_CTRL2:
case RT5670_EQ_CTRL1:
case RT5670_EQ_CTRL2:
case RT5670_ALC_DRC_CTRL1:
case RT5670_ALC_DRC_CTRL2:
case RT5670_ALC_CTRL_1:
case RT5670_ALC_CTRL_2:
case RT5670_ALC_CTRL_3:
case RT5670_JD_CTRL:
case RT5670_IRQ_CTRL1:
case RT5670_IRQ_CTRL2:
case RT5670_INT_IRQ_ST:
case RT5670_GPIO_CTRL1:
case RT5670_GPIO_CTRL2:
case RT5670_GPIO_CTRL3:
case RT5670_SCRABBLE_FUN:
case RT5670_SCRABBLE_CTRL:
case RT5670_BASE_BACK:
case RT5670_MP3_PLUS1:
case RT5670_MP3_PLUS2:
case RT5670_ADJ_HPF1:
case RT5670_ADJ_HPF2:
case RT5670_HP_CALIB_AMP_DET:
case RT5670_SV_ZCD1:
case RT5670_SV_ZCD2:
case RT5670_IL_CMD:
case RT5670_IL_CMD2:
case RT5670_IL_CMD3:
case RT5670_DRC_HL_CTRL1:
case RT5670_DRC_HL_CTRL2:
case RT5670_ADC_MONO_HP_CTRL1:
case RT5670_ADC_MONO_HP_CTRL2:
case RT5670_ADC_STO2_HP_CTRL1:
case RT5670_ADC_STO2_HP_CTRL2:
case RT5670_JD_CTRL3:
case RT5670_JD_CTRL4:
case RT5670_DIG_MISC:
case RT5670_DSP_CTRL1:
case RT5670_DSP_CTRL2:
case RT5670_DSP_CTRL3:
case RT5670_DSP_CTRL4:
case RT5670_DSP_CTRL5:
case RT5670_GEN_CTRL2:
case RT5670_GEN_CTRL3:
case RT5670_VENDOR_ID:
case RT5670_VENDOR_ID1:
case RT5670_VENDOR_ID2:
return true;
default:
return false;
}
}
/**
* rt5670_headset_detect - Detect headset.
* @component: SoC audio component device.
* @jack_insert: Jack insert or not.
*
* Detect whether is headset or not when jack inserted.
*
* Returns detect status.
*/
static int rt5670_headset_detect(struct snd_soc_component *component, int jack_insert)
{
int val;
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
if (jack_insert) {
snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power");
snd_soc_dapm_sync(dapm);
snd_soc_component_update_bits(component, RT5670_GEN_CTRL3, 0x4, 0x0);
snd_soc_component_update_bits(component, RT5670_CJ_CTRL2,
RT5670_CBJ_DET_MODE | RT5670_CBJ_MN_JD,
RT5670_CBJ_MN_JD);
snd_soc_component_write(component, RT5670_GPIO_CTRL2, 0x0004);
snd_soc_component_update_bits(component, RT5670_GPIO_CTRL1,
RT5670_GP1_PIN_MASK, RT5670_GP1_PIN_IRQ);
snd_soc_component_update_bits(component, RT5670_CJ_CTRL1,
RT5670_CBJ_BST1_EN, RT5670_CBJ_BST1_EN);
snd_soc_component_write(component, RT5670_JD_CTRL3, 0x00f0);
snd_soc_component_update_bits(component, RT5670_CJ_CTRL2,
RT5670_CBJ_MN_JD, RT5670_CBJ_MN_JD);
snd_soc_component_update_bits(component, RT5670_CJ_CTRL2,
RT5670_CBJ_MN_JD, 0);
msleep(300);
val = snd_soc_component_read(component, RT5670_CJ_CTRL3) & 0x7;
if (val == 0x1 || val == 0x2) {
rt5670->jack_type = SND_JACK_HEADSET;
/* for push button */
snd_soc_component_update_bits(component, RT5670_INT_IRQ_ST, 0x8, 0x8);
snd_soc_component_update_bits(component, RT5670_IL_CMD, 0x40, 0x40);
snd_soc_component_read(component, RT5670_IL_CMD);
} else {
snd_soc_component_update_bits(component, RT5670_GEN_CTRL3, 0x4, 0x4);
rt5670->jack_type = SND_JACK_HEADPHONE;
snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
snd_soc_dapm_sync(dapm);
}
} else {
snd_soc_component_update_bits(component, RT5670_INT_IRQ_ST, 0x8, 0x0);
snd_soc_component_update_bits(component, RT5670_GEN_CTRL3, 0x4, 0x4);
rt5670->jack_type = 0;
snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
snd_soc_dapm_sync(dapm);
}
return rt5670->jack_type;
}
void rt5670_jack_suspend(struct snd_soc_component *component)
{
struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
rt5670->jack_type_saved = rt5670->jack_type;
rt5670_headset_detect(component, 0);
}
EXPORT_SYMBOL_GPL(rt5670_jack_suspend);
void rt5670_jack_resume(struct snd_soc_component *component)
{
struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
if (rt5670->jack_type_saved)
rt5670_headset_detect(component, 1);
}
EXPORT_SYMBOL_GPL(rt5670_jack_resume);
static int rt5670_button_detect(struct snd_soc_component *component)
{
int btn_type, val;
val = snd_soc_component_read(component, RT5670_IL_CMD);
btn_type = val & 0xff80;
snd_soc_component_write(component, RT5670_IL_CMD, val);
if (btn_type != 0) {
msleep(20);
val = snd_soc_component_read(component, RT5670_IL_CMD);
snd_soc_component_write(component, RT5670_IL_CMD, val);
}
return btn_type;
}
static int rt5670_irq_detection(void *data)
{
struct rt5670_priv *rt5670 = (struct rt5670_priv *)data;
struct snd_soc_jack_gpio *gpio = &rt5670->hp_gpio;
struct snd_soc_jack *jack = rt5670->jack;
int val, btn_type, report = jack->status;
if (rt5670->jd_mode == 1) /* 2 port */
val = snd_soc_component_read(rt5670->component, RT5670_A_JD_CTRL1) & 0x0070;
else
val = snd_soc_component_read(rt5670->component, RT5670_A_JD_CTRL1) & 0x0020;
switch (val) {
/* jack in */
case 0x30: /* 2 port */
case 0x0: /* 1 port or 2 port */
if (rt5670->jack_type == 0) {
report = rt5670_headset_detect(rt5670->component, 1);
/* for push button and jack out */
gpio->debounce_time = 25;
break;
}
btn_type = 0;
if (snd_soc_component_read(rt5670->component, RT5670_INT_IRQ_ST) & 0x4) {
/* button pressed */
report = SND_JACK_HEADSET;
btn_type = rt5670_button_detect(rt5670->component);
switch (btn_type) {
case 0x2000: /* up */
report |= SND_JACK_BTN_1;
break;
case 0x0400: /* center */
report |= SND_JACK_BTN_0;
break;
case 0x0080: /* down */
report |= SND_JACK_BTN_2;
break;
default:
dev_err(rt5670->component->dev,
"Unexpected button code 0x%04x\n",
btn_type);
break;
}
}
if (btn_type == 0)/* button release */
report = rt5670->jack_type;
break;
/* jack out */
case 0x70: /* 2 port */
case 0x10: /* 2 port */
case 0x20: /* 1 port */
report = 0;
snd_soc_component_update_bits(rt5670->component, RT5670_INT_IRQ_ST, 0x1, 0x0);
rt5670_headset_detect(rt5670->component, 0);
gpio->debounce_time = 150; /* for jack in */
break;
default:
break;
}
return report;
}
int rt5670_set_jack_detect(struct snd_soc_component *component,
struct snd_soc_jack *jack)
{
struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
int ret;
rt5670->jack = jack;
rt5670->hp_gpio.gpiod_dev = component->dev;
rt5670->hp_gpio.name = "headset";
rt5670->hp_gpio.report = SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2;
rt5670->hp_gpio.debounce_time = 150;
rt5670->hp_gpio.wake = true;
rt5670->hp_gpio.data = (struct rt5670_priv *)rt5670;
rt5670->hp_gpio.jack_status_check = rt5670_irq_detection;
ret = snd_soc_jack_add_gpios(rt5670->jack, 1,
&rt5670->hp_gpio);
if (ret) {
dev_err(component->dev, "Adding jack GPIO failed\n");
return ret;
}
return 0;
}
EXPORT_SYMBOL_GPL(rt5670_set_jack_detect);
static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
static const DECLARE_TLV_DB_MINMAX(dac_vol_tlv, -6562, 0);
static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
static const DECLARE_TLV_DB_MINMAX(adc_vol_tlv, -1762, 3000);
static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
static const DECLARE_TLV_DB_RANGE(bst_tlv,
0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
);
/* Interface data select */
static const char * const rt5670_data_select[] = {
"Normal", "Swap", "left copy to right", "right copy to left"
};
static SOC_ENUM_SINGLE_DECL(rt5670_if2_dac_enum, RT5670_DIG_INF1_DATA,
RT5670_IF2_DAC_SEL_SFT, rt5670_data_select);
static SOC_ENUM_SINGLE_DECL(rt5670_if2_adc_enum, RT5670_DIG_INF1_DATA,
RT5670_IF2_ADC_SEL_SFT, rt5670_data_select);
/*
* For reliable output-mute LED control we need a "DAC1 Playback Switch" control.
* We emulate this by only clearing the RT5670_M_DAC1_L/_R AD_DA_MIXER register
* bits when both our emulated DAC1 Playback Switch control and the DAC1 MIXL/R
* DAPM-mixer DAC1 input are enabled.
*/
static void rt5670_update_ad_da_mixer_dac1_m_bits(struct rt5670_priv *rt5670)
{
int val = RT5670_M_DAC1_L | RT5670_M_DAC1_R;
if (rt5670->dac1_mixl_dac1_switch && rt5670->dac1_playback_switch_l)
val &= ~RT5670_M_DAC1_L;
if (rt5670->dac1_mixr_dac1_switch && rt5670->dac1_playback_switch_r)
val &= ~RT5670_M_DAC1_R;
regmap_update_bits(rt5670->regmap, RT5670_AD_DA_MIXER,
RT5670_M_DAC1_L | RT5670_M_DAC1_R, val);
}
static int rt5670_dac1_playback_switch_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = rt5670->dac1_playback_switch_l;
ucontrol->value.integer.value[1] = rt5670->dac1_playback_switch_r;
return 0;
}
static int rt5670_dac1_playback_switch_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
if (rt5670->dac1_playback_switch_l == ucontrol->value.integer.value[0] &&
rt5670->dac1_playback_switch_r == ucontrol->value.integer.value[1])
return 0;
rt5670->dac1_playback_switch_l = ucontrol->value.integer.value[0];
rt5670->dac1_playback_switch_r = ucontrol->value.integer.value[1];
rt5670_update_ad_da_mixer_dac1_m_bits(rt5670);
return 1;
}
static const struct snd_kcontrol_new rt5670_snd_controls[] = {
/* Headphone Output Volume */
SOC_DOUBLE_TLV("HP Playback Volume", RT5670_HP_VOL,
RT5670_L_VOL_SFT, RT5670_R_VOL_SFT,
39, 1, out_vol_tlv),
/* OUTPUT Control */
SOC_DOUBLE_TLV("OUT Playback Volume", RT5670_LOUT1,
RT5670_L_VOL_SFT, RT5670_R_VOL_SFT, 39, 1, out_vol_tlv),
/* DAC Digital Volume */
SOC_DOUBLE("DAC2 Playback Switch", RT5670_DAC_CTRL,
RT5670_M_DAC_L2_VOL_SFT, RT5670_M_DAC_R2_VOL_SFT, 1, 1),
SOC_DOUBLE_EXT("DAC1 Playback Switch", SND_SOC_NOPM, 0, 1, 1, 0,
rt5670_dac1_playback_switch_get, rt5670_dac1_playback_switch_put),
SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5670_DAC1_DIG_VOL,
RT5670_L_VOL_SFT, RT5670_R_VOL_SFT,
175, 0, dac_vol_tlv),
SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5670_DAC2_DIG_VOL,
RT5670_L_VOL_SFT, RT5670_R_VOL_SFT,
175, 0, dac_vol_tlv),
/* IN1/IN2 Control */
SOC_SINGLE_TLV("IN1 Boost Volume", RT5670_CJ_CTRL1,
RT5670_BST_SFT1, 8, 0, bst_tlv),
SOC_SINGLE_TLV("IN2 Boost Volume", RT5670_IN2,
RT5670_BST_SFT1, 8, 0, bst_tlv),
/* INL/INR Volume Control */
SOC_DOUBLE_TLV("IN Capture Volume", RT5670_INL1_INR1_VOL,
RT5670_INL_VOL_SFT, RT5670_INR_VOL_SFT,
31, 1, in_vol_tlv),
/* ADC Digital Volume Control */
SOC_DOUBLE("ADC Capture Switch", RT5670_STO1_ADC_DIG_VOL,
RT5670_L_MUTE_SFT, RT5670_R_MUTE_SFT, 1, 1),
SOC_DOUBLE_TLV("ADC Capture Volume", RT5670_STO1_ADC_DIG_VOL,
RT5670_L_VOL_SFT, RT5670_R_VOL_SFT,
127, 0, adc_vol_tlv),
SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5670_MONO_ADC_DIG_VOL,
RT5670_L_VOL_SFT, RT5670_R_VOL_SFT,
127, 0, adc_vol_tlv),
/* ADC Boost Volume Control */
SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5670_ADC_BST_VOL1,
RT5670_STO1_ADC_L_BST_SFT, RT5670_STO1_ADC_R_BST_SFT,
3, 0, adc_bst_tlv),
SOC_DOUBLE_TLV("STO2 ADC Boost Gain Volume", RT5670_ADC_BST_VOL1,
RT5670_STO2_ADC_L_BST_SFT, RT5670_STO2_ADC_R_BST_SFT,
3, 0, adc_bst_tlv),
SOC_ENUM("ADC IF2 Data Switch", rt5670_if2_adc_enum),
SOC_ENUM("DAC IF2 Data Switch", rt5670_if2_dac_enum),
};
/**
* set_dmic_clk - Set parameter of dmic.
*
* @w: DAPM widget.
* @kcontrol: The kcontrol of this widget.
* @event: Event id.
*
* Choose dmic clock between 1MHz and 3MHz.
* It is better for clock to approximate 3MHz.
*/
static int set_dmic_clk(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
int idx, rate;
rate = rt5670->sysclk / rl6231_get_pre_div(rt5670->regmap,
RT5670_ADDA_CLK1, RT5670_I2S_PD1_SFT);
idx = rl6231_calc_dmic_clk(rate);
if (idx < 0)
dev_err(component->dev, "Failed to set DMIC clock\n");
else
snd_soc_component_update_bits(component, RT5670_DMIC_CTRL1,
RT5670_DMIC_CLK_MASK, idx << RT5670_DMIC_CLK_SFT);
return idx;
}
static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
if (rt5670->sysclk_src == RT5670_SCLK_S_PLL1)
return 1;
else
return 0;
}
static int is_using_asrc(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
unsigned int reg, shift, val;
switch (source->shift) {
case 0:
reg = RT5670_ASRC_3;
shift = 0;
break;
case 1:
reg = RT5670_ASRC_3;
shift = 4;
break;
case 2:
reg = RT5670_ASRC_5;
shift = 12;
break;
case 3:
reg = RT5670_ASRC_2;
shift = 0;
break;
case 8:
reg = RT5670_ASRC_2;
shift = 4;
break;
case 9:
reg = RT5670_ASRC_2;
shift = 8;
break;
case 10:
reg = RT5670_ASRC_2;
shift = 12;
break;
default:
return 0;
}
val = (snd_soc_component_read(component, reg) >> shift) & 0xf;
switch (val) {
case 1:
case 2:
case 3:
case 4:
return 1;
default:
return 0;
}
}
static int can_use_asrc(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
if (rt5670->sysclk > rt5670->lrck[RT5670_AIF1] * 384)
return 1;
return 0;
}
/**
* rt5670_sel_asrc_clk_src - select ASRC clock source for a set of filters
* @component: SoC audio component device.
* @filter_mask: mask of filters.
* @clk_src: clock source
*
* The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5670 can
* only support standard 32fs or 64fs i2s format, ASRC should be enabled to
* support special i2s clock format such as Intel's 100fs(100 * sampling rate).
* ASRC function will track i2s clock and generate a corresponding system clock
* for codec. This function provides an API to select the clock source for a
* set of filters specified by the mask. And the codec driver will turn on ASRC
* for these filters if ASRC is selected as their clock source.
*/
int rt5670_sel_asrc_clk_src(struct snd_soc_component *component,
unsigned int filter_mask, unsigned int clk_src)
{
unsigned int asrc2_mask = 0, asrc2_value = 0;
unsigned int asrc3_mask = 0, asrc3_value = 0;
if (clk_src > RT5670_CLK_SEL_SYS3)
return -EINVAL;
if (filter_mask & RT5670_DA_STEREO_FILTER) {
asrc2_mask |= RT5670_DA_STO_CLK_SEL_MASK;
asrc2_value = (asrc2_value & ~RT5670_DA_STO_CLK_SEL_MASK)
| (clk_src << RT5670_DA_STO_CLK_SEL_SFT);
}
if (filter_mask & RT5670_DA_MONO_L_FILTER) {
asrc2_mask |= RT5670_DA_MONOL_CLK_SEL_MASK;
asrc2_value = (asrc2_value & ~RT5670_DA_MONOL_CLK_SEL_MASK)
| (clk_src << RT5670_DA_MONOL_CLK_SEL_SFT);
}
if (filter_mask & RT5670_DA_MONO_R_FILTER) {
asrc2_mask |= RT5670_DA_MONOR_CLK_SEL_MASK;
asrc2_value = (asrc2_value & ~RT5670_DA_MONOR_CLK_SEL_MASK)
| (clk_src << RT5670_DA_MONOR_CLK_SEL_SFT);
}
if (filter_mask & RT5670_AD_STEREO_FILTER) {
asrc2_mask |= RT5670_AD_STO1_CLK_SEL_MASK;
asrc2_value = (asrc2_value & ~RT5670_AD_STO1_CLK_SEL_MASK)
| (clk_src << RT5670_AD_STO1_CLK_SEL_SFT);
}
if (filter_mask & RT5670_AD_MONO_L_FILTER) {
asrc3_mask |= RT5670_AD_MONOL_CLK_SEL_MASK;
asrc3_value = (asrc3_value & ~RT5670_AD_MONOL_CLK_SEL_MASK)
| (clk_src << RT5670_AD_MONOL_CLK_SEL_SFT);
}
if (filter_mask & RT5670_AD_MONO_R_FILTER) {
asrc3_mask |= RT5670_AD_MONOR_CLK_SEL_MASK;
asrc3_value = (asrc3_value & ~RT5670_AD_MONOR_CLK_SEL_MASK)
| (clk_src << RT5670_AD_MONOR_CLK_SEL_SFT);
}
if (filter_mask & RT5670_UP_RATE_FILTER) {
asrc3_mask |= RT5670_UP_CLK_SEL_MASK;
asrc3_value = (asrc3_value & ~RT5670_UP_CLK_SEL_MASK)
| (clk_src << RT5670_UP_CLK_SEL_SFT);
}
if (filter_mask & RT5670_DOWN_RATE_FILTER) {
asrc3_mask |= RT5670_DOWN_CLK_SEL_MASK;
asrc3_value = (asrc3_value & ~RT5670_DOWN_CLK_SEL_MASK)
| (clk_src << RT5670_DOWN_CLK_SEL_SFT);
}
if (asrc2_mask)
snd_soc_component_update_bits(component, RT5670_ASRC_2,
asrc2_mask, asrc2_value);
if (asrc3_mask)
snd_soc_component_update_bits(component, RT5670_ASRC_3,
asrc3_mask, asrc3_value);
return 0;
}
EXPORT_SYMBOL_GPL(rt5670_sel_asrc_clk_src);
/* Digital Mixer */
static const struct snd_kcontrol_new rt5670_sto1_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5670_STO1_ADC_MIXER,
RT5670_M_ADC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5670_STO1_ADC_MIXER,
RT5670_M_ADC_L2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_sto1_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5670_STO1_ADC_MIXER,
RT5670_M_ADC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5670_STO1_ADC_MIXER,
RT5670_M_ADC_R2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_sto2_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5670_STO2_ADC_MIXER,
RT5670_M_ADC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5670_STO2_ADC_MIXER,
RT5670_M_ADC_L2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_sto2_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5670_STO2_ADC_MIXER,
RT5670_M_ADC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5670_STO2_ADC_MIXER,
RT5670_M_ADC_R2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_mono_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5670_MONO_ADC_MIXER,
RT5670_M_MONO_ADC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5670_MONO_ADC_MIXER,
RT5670_M_MONO_ADC_L2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_mono_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5670_MONO_ADC_MIXER,
RT5670_M_MONO_ADC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5670_MONO_ADC_MIXER,
RT5670_M_MONO_ADC_R2_SFT, 1, 1),
};
/* See comment above rt5670_update_ad_da_mixer_dac1_m_bits() */
static int rt5670_put_dac1_mix_dac1_switch(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
int ret;
if (mc->shift == 0)
rt5670->dac1_mixl_dac1_switch = ucontrol->value.integer.value[0];
else
rt5670->dac1_mixr_dac1_switch = ucontrol->value.integer.value[0];
/* Apply the update (if any) */
ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
if (ret == 0)
return 0;
rt5670_update_ad_da_mixer_dac1_m_bits(rt5670);
return 1;
}
#define SOC_DAPM_SINGLE_RT5670_DAC1_SW(name, shift) \
SOC_SINGLE_EXT(name, SND_SOC_NOPM, shift, 1, 0, \
snd_soc_dapm_get_volsw, rt5670_put_dac1_mix_dac1_switch)
static const struct snd_kcontrol_new rt5670_dac_l_mix[] = {
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5670_AD_DA_MIXER,
RT5670_M_ADCMIX_L_SFT, 1, 1),
SOC_DAPM_SINGLE_RT5670_DAC1_SW("DAC1 Switch", 0),
};
static const struct snd_kcontrol_new rt5670_dac_r_mix[] = {
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5670_AD_DA_MIXER,
RT5670_M_ADCMIX_R_SFT, 1, 1),
SOC_DAPM_SINGLE_RT5670_DAC1_SW("DAC1 Switch", 1),
};
static const struct snd_kcontrol_new rt5670_sto_dac_l_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5670_STO_DAC_MIXER,
RT5670_M_DAC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_STO_DAC_MIXER,
RT5670_M_DAC_L2_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_STO_DAC_MIXER,
RT5670_M_DAC_R1_STO_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_sto_dac_r_mix[] = {
SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_STO_DAC_MIXER,
RT5670_M_DAC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_STO_DAC_MIXER,
RT5670_M_DAC_R2_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L1 Switch", RT5670_STO_DAC_MIXER,
RT5670_M_DAC_L1_STO_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_mono_dac_l_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5670_DD_MIXER,
RT5670_M_DAC_L1_MONO_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_DD_MIXER,
RT5670_M_DAC_L2_MONO_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_DD_MIXER,
RT5670_M_DAC_R2_MONO_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_mono_dac_r_mix[] = {
SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_DD_MIXER,
RT5670_M_DAC_R1_MONO_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_DD_MIXER,
RT5670_M_DAC_R2_MONO_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_DD_MIXER,
RT5670_M_DAC_L2_MONO_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_dig_l_mix[] = {
SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5670_DIG_MIXER,
RT5670_M_STO_L_DAC_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_DIG_MIXER,
RT5670_M_DAC_L2_DAC_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_DIG_MIXER,
RT5670_M_DAC_R2_DAC_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_dig_r_mix[] = {
SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5670_DIG_MIXER,
RT5670_M_STO_R_DAC_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_DIG_MIXER,
RT5670_M_DAC_R2_DAC_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_DIG_MIXER,
RT5670_M_DAC_L2_DAC_R_SFT, 1, 1),
};
/* Analog Input Mixer */
static const struct snd_kcontrol_new rt5670_rec_l_mix[] = {
SOC_DAPM_SINGLE("INL Switch", RT5670_REC_L2_MIXER,
RT5670_M_IN_L_RM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5670_REC_L2_MIXER,
RT5670_M_BST2_RM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5670_REC_L2_MIXER,
RT5670_M_BST1_RM_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_rec_r_mix[] = {
SOC_DAPM_SINGLE("INR Switch", RT5670_REC_R2_MIXER,
RT5670_M_IN_R_RM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5670_REC_R2_MIXER,
RT5670_M_BST2_RM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5670_REC_R2_MIXER,
RT5670_M_BST1_RM_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_out_l_mix[] = {
SOC_DAPM_SINGLE("BST1 Switch", RT5670_OUT_L1_MIXER,
RT5670_M_BST1_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("INL Switch", RT5670_OUT_L1_MIXER,
RT5670_M_IN_L_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_OUT_L1_MIXER,
RT5670_M_DAC_L2_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L1 Switch", RT5670_OUT_L1_MIXER,
RT5670_M_DAC_L1_OM_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_out_r_mix[] = {
SOC_DAPM_SINGLE("BST2 Switch", RT5670_OUT_R1_MIXER,
RT5670_M_BST2_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("INR Switch", RT5670_OUT_R1_MIXER,
RT5670_M_IN_R_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_OUT_R1_MIXER,
RT5670_M_DAC_R2_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_OUT_R1_MIXER,
RT5670_M_DAC_R1_OM_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_hpo_mix[] = {
SOC_DAPM_SINGLE("DAC1 Switch", RT5670_HPO_MIXER,
RT5670_M_DAC1_HM_SFT, 1, 1),
SOC_DAPM_SINGLE("HPVOL Switch", RT5670_HPO_MIXER,
RT5670_M_HPVOL_HM_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_hpvoll_mix[] = {
SOC_DAPM_SINGLE("DAC1 Switch", RT5670_HPO_MIXER,
RT5670_M_DACL1_HML_SFT, 1, 1),
SOC_DAPM_SINGLE("INL Switch", RT5670_HPO_MIXER,
RT5670_M_INL1_HML_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_hpvolr_mix[] = {
SOC_DAPM_SINGLE("DAC1 Switch", RT5670_HPO_MIXER,
RT5670_M_DACR1_HMR_SFT, 1, 1),
SOC_DAPM_SINGLE("INR Switch", RT5670_HPO_MIXER,
RT5670_M_INR1_HMR_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_lout_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5670_LOUT_MIXER,
RT5670_M_DAC_L1_LM_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_LOUT_MIXER,
RT5670_M_DAC_R1_LM_SFT, 1, 1),
SOC_DAPM_SINGLE("OUTMIX L Switch", RT5670_LOUT_MIXER,
RT5670_M_OV_L_LM_SFT, 1, 1),
SOC_DAPM_SINGLE("OUTMIX R Switch", RT5670_LOUT_MIXER,
RT5670_M_OV_R_LM_SFT, 1, 1),
};
static const struct snd_kcontrol_new lout_l_enable_control =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5670_LOUT1,
RT5670_L_MUTE_SFT, 1, 1);
static const struct snd_kcontrol_new lout_r_enable_control =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5670_LOUT1,
RT5670_R_MUTE_SFT, 1, 1);
/* DAC1 L/R source */ /* MX-29 [9:8] [11:10] */
static const char * const rt5670_dac1_src[] = {
"IF1 DAC", "IF2 DAC"
};
static SOC_ENUM_SINGLE_DECL(rt5670_dac1l_enum, RT5670_AD_DA_MIXER,
RT5670_DAC1_L_SEL_SFT, rt5670_dac1_src);
static const struct snd_kcontrol_new rt5670_dac1l_mux =
SOC_DAPM_ENUM("DAC1 L source", rt5670_dac1l_enum);
static SOC_ENUM_SINGLE_DECL(rt5670_dac1r_enum, RT5670_AD_DA_MIXER,
RT5670_DAC1_R_SEL_SFT, rt5670_dac1_src);
static const struct snd_kcontrol_new rt5670_dac1r_mux =
SOC_DAPM_ENUM("DAC1 R source", rt5670_dac1r_enum);
/*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */
/* TODO Use SOC_VALUE_ENUM_SINGLE_DECL */
static const char * const rt5670_dac12_src[] = {
"IF1 DAC", "IF2 DAC", "IF3 DAC", "TxDC DAC",
"Bass", "VAD_ADC", "IF4 DAC"
};
static SOC_ENUM_SINGLE_DECL(rt5670_dac2l_enum, RT5670_DAC_CTRL,
RT5670_DAC2_L_SEL_SFT, rt5670_dac12_src);
static const struct snd_kcontrol_new rt5670_dac_l2_mux =
SOC_DAPM_ENUM("DAC2 L source", rt5670_dac2l_enum);
static const char * const rt5670_dacr2_src[] = {
"IF1 DAC", "IF2 DAC", "IF3 DAC", "TxDC DAC", "TxDP ADC", "IF4 DAC"
};
static SOC_ENUM_SINGLE_DECL(rt5670_dac2r_enum, RT5670_DAC_CTRL,
RT5670_DAC2_R_SEL_SFT, rt5670_dacr2_src);
static const struct snd_kcontrol_new rt5670_dac_r2_mux =
SOC_DAPM_ENUM("DAC2 R source", rt5670_dac2r_enum);
/*RxDP source*/ /* MX-2D [15:13] */
static const char * const rt5670_rxdp_src[] = {
"IF2 DAC", "IF1 DAC", "STO1 ADC Mixer", "STO2 ADC Mixer",
"Mono ADC Mixer L", "Mono ADC Mixer R", "DAC1"
};
static SOC_ENUM_SINGLE_DECL(rt5670_rxdp_enum, RT5670_DSP_PATH1,
RT5670_RXDP_SEL_SFT, rt5670_rxdp_src);
static const struct snd_kcontrol_new rt5670_rxdp_mux =
SOC_DAPM_ENUM("DAC2 L source", rt5670_rxdp_enum);
/* MX-2D [1] [0] */
static const char * const rt5670_dsp_bypass_src[] = {
"DSP", "Bypass"
};
static SOC_ENUM_SINGLE_DECL(rt5670_dsp_ul_enum, RT5670_DSP_PATH1,
RT5670_DSP_UL_SFT, rt5670_dsp_bypass_src);
static const struct snd_kcontrol_new rt5670_dsp_ul_mux =
SOC_DAPM_ENUM("DSP UL source", rt5670_dsp_ul_enum);
static SOC_ENUM_SINGLE_DECL(rt5670_dsp_dl_enum, RT5670_DSP_PATH1,
RT5670_DSP_DL_SFT, rt5670_dsp_bypass_src);
static const struct snd_kcontrol_new rt5670_dsp_dl_mux =
SOC_DAPM_ENUM("DSP DL source", rt5670_dsp_dl_enum);
/* Stereo2 ADC source */
/* MX-26 [15] */
static const char * const rt5670_stereo2_adc_lr_src[] = {
"L", "LR"
};
static SOC_ENUM_SINGLE_DECL(rt5670_stereo2_adc_lr_enum, RT5670_STO2_ADC_MIXER,
RT5670_STO2_ADC_SRC_SFT, rt5670_stereo2_adc_lr_src);
static const struct snd_kcontrol_new rt5670_sto2_adc_lr_mux =
SOC_DAPM_ENUM("Stereo2 ADC LR source", rt5670_stereo2_adc_lr_enum);
/* Stereo1 ADC source */
/* MX-27 MX-26 [12] */
static const char * const rt5670_stereo_adc1_src[] = {
"DAC MIX", "ADC"
};
static SOC_ENUM_SINGLE_DECL(rt5670_stereo1_adc1_enum, RT5670_STO1_ADC_MIXER,
RT5670_ADC_1_SRC_SFT, rt5670_stereo_adc1_src);
static const struct snd_kcontrol_new rt5670_sto_adc_1_mux =
SOC_DAPM_ENUM("Stereo1 ADC 1 Mux", rt5670_stereo1_adc1_enum);
static SOC_ENUM_SINGLE_DECL(rt5670_stereo2_adc1_enum, RT5670_STO2_ADC_MIXER,
RT5670_ADC_1_SRC_SFT, rt5670_stereo_adc1_src);
static const struct snd_kcontrol_new rt5670_sto2_adc_1_mux =
SOC_DAPM_ENUM("Stereo2 ADC 1 Mux", rt5670_stereo2_adc1_enum);
/* MX-27 MX-26 [11] */
static const char * const rt5670_stereo_adc2_src[] = {
"DAC MIX", "DMIC"
};
static SOC_ENUM_SINGLE_DECL(rt5670_stereo1_adc2_enum, RT5670_STO1_ADC_MIXER,
RT5670_ADC_2_SRC_SFT, rt5670_stereo_adc2_src);
static const struct snd_kcontrol_new rt5670_sto_adc_2_mux =
SOC_DAPM_ENUM("Stereo1 ADC 2 Mux", rt5670_stereo1_adc2_enum);
static SOC_ENUM_SINGLE_DECL(rt5670_stereo2_adc2_enum, RT5670_STO2_ADC_MIXER,
RT5670_ADC_2_SRC_SFT, rt5670_stereo_adc2_src);
static const struct snd_kcontrol_new rt5670_sto2_adc_2_mux =
SOC_DAPM_ENUM("Stereo2 ADC 2 Mux", rt5670_stereo2_adc2_enum);
/* MX-27 MX-26 [9:8] */
static const char * const rt5670_stereo_dmic_src[] = {
"DMIC1", "DMIC2", "DMIC3"
};
static SOC_ENUM_SINGLE_DECL(rt5670_stereo1_dmic_enum, RT5670_STO1_ADC_MIXER,
RT5670_DMIC_SRC_SFT, rt5670_stereo_dmic_src);
static const struct snd_kcontrol_new rt5670_sto1_dmic_mux =
SOC_DAPM_ENUM("Stereo1 DMIC source", rt5670_stereo1_dmic_enum);
static SOC_ENUM_SINGLE_DECL(rt5670_stereo2_dmic_enum, RT5670_STO2_ADC_MIXER,
RT5670_DMIC_SRC_SFT, rt5670_stereo_dmic_src);
static const struct snd_kcontrol_new rt5670_sto2_dmic_mux =
SOC_DAPM_ENUM("Stereo2 DMIC source", rt5670_stereo2_dmic_enum);
/* Mono ADC source */
/* MX-28 [12] */
static const char * const rt5670_mono_adc_l1_src[] = {
"Mono DAC MIXL", "ADC1"
};
static SOC_ENUM_SINGLE_DECL(rt5670_mono_adc_l1_enum, RT5670_MONO_ADC_MIXER,
RT5670_MONO_ADC_L1_SRC_SFT, rt5670_mono_adc_l1_src);
static const struct snd_kcontrol_new rt5670_mono_adc_l1_mux =
SOC_DAPM_ENUM("Mono ADC1 left source", rt5670_mono_adc_l1_enum);
/* MX-28 [11] */
static const char * const rt5670_mono_adc_l2_src[] = {
"Mono DAC MIXL", "DMIC"
};
static SOC_ENUM_SINGLE_DECL(rt5670_mono_adc_l2_enum, RT5670_MONO_ADC_MIXER,
RT5670_MONO_ADC_L2_SRC_SFT, rt5670_mono_adc_l2_src);
static const struct snd_kcontrol_new rt5670_mono_adc_l2_mux =
SOC_DAPM_ENUM("Mono ADC2 left source", rt5670_mono_adc_l2_enum);
/* MX-28 [9:8] */
static const char * const rt5670_mono_dmic_src[] = {
"DMIC1", "DMIC2", "DMIC3"
};
static SOC_ENUM_SINGLE_DECL(rt5670_mono_dmic_l_enum, RT5670_MONO_ADC_MIXER,
RT5670_MONO_DMIC_L_SRC_SFT, rt5670_mono_dmic_src);
static const struct snd_kcontrol_new rt5670_mono_dmic_l_mux =
SOC_DAPM_ENUM("Mono DMIC left source", rt5670_mono_dmic_l_enum);
/* MX-28 [1:0] */
static SOC_ENUM_SINGLE_DECL(rt5670_mono_dmic_r_enum, RT5670_MONO_ADC_MIXER,
RT5670_MONO_DMIC_R_SRC_SFT, rt5670_mono_dmic_src);
static const struct snd_kcontrol_new rt5670_mono_dmic_r_mux =
SOC_DAPM_ENUM("Mono DMIC Right source", rt5670_mono_dmic_r_enum);
/* MX-28 [4] */
static const char * const rt5670_mono_adc_r1_src[] = {
"Mono DAC MIXR", "ADC2"
};
static SOC_ENUM_SINGLE_DECL(rt5670_mono_adc_r1_enum, RT5670_MONO_ADC_MIXER,
RT5670_MONO_ADC_R1_SRC_SFT, rt5670_mono_adc_r1_src);
static const struct snd_kcontrol_new rt5670_mono_adc_r1_mux =
SOC_DAPM_ENUM("Mono ADC1 right source", rt5670_mono_adc_r1_enum);
/* MX-28 [3] */
static const char * const rt5670_mono_adc_r2_src[] = {
"Mono DAC MIXR", "DMIC"
};
static SOC_ENUM_SINGLE_DECL(rt5670_mono_adc_r2_enum, RT5670_MONO_ADC_MIXER,
RT5670_MONO_ADC_R2_SRC_SFT, rt5670_mono_adc_r2_src);
static const struct snd_kcontrol_new rt5670_mono_adc_r2_mux =
SOC_DAPM_ENUM("Mono ADC2 right source", rt5670_mono_adc_r2_enum);
/* MX-2D [3:2] */
static const char * const rt5670_txdp_slot_src[] = {
"Slot 0-1", "Slot 2-3", "Slot 4-5", "Slot 6-7"
};
static SOC_ENUM_SINGLE_DECL(rt5670_txdp_slot_enum, RT5670_DSP_PATH1,
RT5670_TXDP_SLOT_SEL_SFT, rt5670_txdp_slot_src);
static const struct snd_kcontrol_new rt5670_txdp_slot_mux =
SOC_DAPM_ENUM("TxDP Slot source", rt5670_txdp_slot_enum);
/* MX-2F [15] */
static const char * const rt5670_if1_adc2_in_src[] = {
"IF_ADC2", "VAD_ADC"
};
static SOC_ENUM_SINGLE_DECL(rt5670_if1_adc2_in_enum, RT5670_DIG_INF1_DATA,
RT5670_IF1_ADC2_IN_SFT, rt5670_if1_adc2_in_src);
static const struct snd_kcontrol_new rt5670_if1_adc2_in_mux =
SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5670_if1_adc2_in_enum);
/* MX-2F [14:12] */
static const char * const rt5670_if2_adc_in_src[] = {
"IF_ADC1", "IF_ADC2", "IF_ADC3", "TxDC_DAC", "TxDP_ADC", "VAD_ADC"
};
static SOC_ENUM_SINGLE_DECL(rt5670_if2_adc_in_enum, RT5670_DIG_INF1_DATA,
RT5670_IF2_ADC_IN_SFT, rt5670_if2_adc_in_src);
static const struct snd_kcontrol_new rt5670_if2_adc_in_mux =
SOC_DAPM_ENUM("IF2 ADC IN source", rt5670_if2_adc_in_enum);
/* MX-31 [15] [13] [11] [9] */
static const char * const rt5670_pdm_src[] = {
"Mono DAC", "Stereo DAC"
};
static SOC_ENUM_SINGLE_DECL(rt5670_pdm1_l_enum, RT5670_PDM_OUT_CTRL,
RT5670_PDM1_L_SFT, rt5670_pdm_src);
static const struct snd_kcontrol_new rt5670_pdm1_l_mux =
SOC_DAPM_ENUM("PDM1 L source", rt5670_pdm1_l_enum);
static SOC_ENUM_SINGLE_DECL(rt5670_pdm1_r_enum, RT5670_PDM_OUT_CTRL,
RT5670_PDM1_R_SFT, rt5670_pdm_src);
static const struct snd_kcontrol_new rt5670_pdm1_r_mux =
SOC_DAPM_ENUM("PDM1 R source", rt5670_pdm1_r_enum);
static SOC_ENUM_SINGLE_DECL(rt5670_pdm2_l_enum, RT5670_PDM_OUT_CTRL,
RT5670_PDM2_L_SFT, rt5670_pdm_src);
static const struct snd_kcontrol_new rt5670_pdm2_l_mux =
SOC_DAPM_ENUM("PDM2 L source", rt5670_pdm2_l_enum);
static SOC_ENUM_SINGLE_DECL(rt5670_pdm2_r_enum, RT5670_PDM_OUT_CTRL,
RT5670_PDM2_R_SFT, rt5670_pdm_src);
static const struct snd_kcontrol_new rt5670_pdm2_r_mux =
SOC_DAPM_ENUM("PDM2 R source", rt5670_pdm2_r_enum);
/* MX-FA [12] */
static const char * const rt5670_if1_adc1_in1_src[] = {
"IF_ADC1", "IF1_ADC3"
};
static SOC_ENUM_SINGLE_DECL(rt5670_if1_adc1_in1_enum, RT5670_DIG_MISC,
RT5670_IF1_ADC1_IN1_SFT, rt5670_if1_adc1_in1_src);
static const struct snd_kcontrol_new rt5670_if1_adc1_in1_mux =
SOC_DAPM_ENUM("IF1 ADC1 IN1 source", rt5670_if1_adc1_in1_enum);
/* MX-FA [11] */
static const char * const rt5670_if1_adc1_in2_src[] = {
"IF1_ADC1_IN1", "IF1_ADC4"
};
static SOC_ENUM_SINGLE_DECL(rt5670_if1_adc1_in2_enum, RT5670_DIG_MISC,
RT5670_IF1_ADC1_IN2_SFT, rt5670_if1_adc1_in2_src);
static const struct snd_kcontrol_new rt5670_if1_adc1_in2_mux =
SOC_DAPM_ENUM("IF1 ADC1 IN2 source", rt5670_if1_adc1_in2_enum);
/* MX-FA [10] */
static const char * const rt5670_if1_adc2_in1_src[] = {
"IF1_ADC2_IN", "IF1_ADC4"
};
static SOC_ENUM_SINGLE_DECL(rt5670_if1_adc2_in1_enum, RT5670_DIG_MISC,
RT5670_IF1_ADC2_IN1_SFT, rt5670_if1_adc2_in1_src);
static const struct snd_kcontrol_new rt5670_if1_adc2_in1_mux =
SOC_DAPM_ENUM("IF1 ADC2 IN1 source", rt5670_if1_adc2_in1_enum);
/* MX-9D [9:8] */
static const char * const rt5670_vad_adc_src[] = {
"Sto1 ADC L", "Mono ADC L", "Mono ADC R", "Sto2 ADC L"
};
static SOC_ENUM_SINGLE_DECL(rt5670_vad_adc_enum, RT5670_VAD_CTRL4,
RT5670_VAD_SEL_SFT, rt5670_vad_adc_src);
static const struct snd_kcontrol_new rt5670_vad_adc_mux =
SOC_DAPM_ENUM("VAD ADC source", rt5670_vad_adc_enum);
static int rt5670_hp_power_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_update_bits(rt5670->regmap, RT5670_CHARGE_PUMP,
RT5670_PM_HP_MASK, RT5670_PM_HP_HV);
regmap_update_bits(rt5670->regmap, RT5670_GEN_CTRL2,
0x0400, 0x0400);
/* headphone amp power on */
regmap_update_bits(rt5670->regmap, RT5670_PWR_ANLG1,
RT5670_PWR_HA | RT5670_PWR_FV1 |
RT5670_PWR_FV2, RT5670_PWR_HA |
RT5670_PWR_FV1 | RT5670_PWR_FV2);
/* depop parameters */
regmap_write(rt5670->regmap, RT5670_DEPOP_M2, 0x3100);
regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x8009);
regmap_write(rt5670->regmap, RT5670_PR_BASE +
RT5670_HP_DCC_INT1, 0x9f00);
mdelay(20);
regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x8019);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x0004);
msleep(30);
break;
default:
return 0;
}
return 0;
}
static int rt5670_hp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
/* headphone unmute sequence */
regmap_write(rt5670->regmap, RT5670_PR_BASE +
RT5670_MAMP_INT_REG2, 0xb400);
regmap_write(rt5670->regmap, RT5670_DEPOP_M3, 0x0772);
regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x805d);
regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x831d);
regmap_update_bits(rt5670->regmap, RT5670_GEN_CTRL2,
0x0300, 0x0300);
regmap_update_bits(rt5670->regmap, RT5670_HP_VOL,
RT5670_L_MUTE | RT5670_R_MUTE, 0);
msleep(80);
regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x8019);
break;
case SND_SOC_DAPM_PRE_PMD:
/* headphone mute sequence */
regmap_write(rt5670->regmap, RT5670_PR_BASE +
RT5670_MAMP_INT_REG2, 0xb400);
regmap_write(rt5670->regmap, RT5670_DEPOP_M3, 0x0772);
regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x803d);
mdelay(10);
regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x831d);
mdelay(10);
regmap_update_bits(rt5670->regmap, RT5670_HP_VOL,
RT5670_L_MUTE | RT5670_R_MUTE,
RT5670_L_MUTE | RT5670_R_MUTE);
msleep(20);
regmap_update_bits(rt5670->regmap,
RT5670_GEN_CTRL2, 0x0300, 0x0);
regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x8019);
regmap_write(rt5670->regmap, RT5670_DEPOP_M3, 0x0707);
regmap_write(rt5670->regmap, RT5670_PR_BASE +
RT5670_MAMP_INT_REG2, 0xfc00);
break;
default:
return 0;
}
return 0;
}
static int rt5670_spk_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
if (!rt5670->gpio1_is_ext_spk_en)
return 0;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL2,
RT5670_GP1_OUT_MASK, RT5670_GP1_OUT_HI);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL2,
RT5670_GP1_OUT_MASK, RT5670_GP1_OUT_LO);
break;
default:
return 0;
}
return 0;
}
static int rt5670_bst1_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(component, RT5670_PWR_ANLG2,
RT5670_PWR_BST1_P, RT5670_PWR_BST1_P);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, RT5670_PWR_ANLG2,
RT5670_PWR_BST1_P, 0);
break;
default:
return 0;
}
return 0;
}
static int rt5670_bst2_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(component, RT5670_PWR_ANLG2,
RT5670_PWR_BST2_P, RT5670_PWR_BST2_P);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, RT5670_PWR_ANLG2,
RT5670_PWR_BST2_P, 0);
break;
default:
return 0;
}
return 0;
}
static const struct snd_soc_dapm_widget rt5670_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("PLL1", RT5670_PWR_ANLG2,
RT5670_PWR_PLL_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("I2S DSP", RT5670_PWR_DIG2,
RT5670_PWR_I2S_DSP_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5670_PWR_VOL,
RT5670_PWR_MIC_DET_BIT, 0, NULL, 0),
/* ASRC */
SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5670_ASRC_1,
11, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5670_ASRC_1,
12, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5670_ASRC_1,
10, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5670_ASRC_1,
9, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5670_ASRC_1,
8, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5670_ASRC_1,
7, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5670_ASRC_1,
6, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5670_ASRC_1,
5, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5670_ASRC_1,
4, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5670_ASRC_1,
3, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5670_ASRC_1,
2, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5670_ASRC_1,
1, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5670_ASRC_1,
0, 0, NULL, 0),
/* Input Side */
/* micbias */
SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5670_PWR_ANLG2,
RT5670_PWR_MB1_BIT, 0, NULL, 0),
/* Input Lines */
SND_SOC_DAPM_INPUT("DMIC L1"),
SND_SOC_DAPM_INPUT("DMIC R1"),
SND_SOC_DAPM_INPUT("DMIC L2"),
SND_SOC_DAPM_INPUT("DMIC R2"),
SND_SOC_DAPM_INPUT("DMIC L3"),
SND_SOC_DAPM_INPUT("DMIC R3"),
SND_SOC_DAPM_INPUT("IN1P"),
SND_SOC_DAPM_INPUT("IN1N"),
SND_SOC_DAPM_INPUT("IN2P"),
SND_SOC_DAPM_INPUT("IN2N"),
SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5670_DMIC_CTRL1,
RT5670_DMIC_1_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5670_DMIC_CTRL1,
RT5670_DMIC_2_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DMIC3 Power", RT5670_DMIC_CTRL1,
RT5670_DMIC_3_EN_SFT, 0, NULL, 0),
/* Boost */
SND_SOC_DAPM_PGA_E("BST1", RT5670_PWR_ANLG2, RT5670_PWR_BST1_BIT,
0, NULL, 0, rt5670_bst1_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("BST2", RT5670_PWR_ANLG2, RT5670_PWR_BST2_BIT,
0, NULL, 0, rt5670_bst2_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
/* Input Volume */
SND_SOC_DAPM_PGA("INL VOL", RT5670_PWR_VOL,
RT5670_PWR_IN_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("INR VOL", RT5670_PWR_VOL,
RT5670_PWR_IN_R_BIT, 0, NULL, 0),
/* REC Mixer */
SND_SOC_DAPM_MIXER("RECMIXL", RT5670_PWR_MIXER, RT5670_PWR_RM_L_BIT, 0,
rt5670_rec_l_mix, ARRAY_SIZE(rt5670_rec_l_mix)),
SND_SOC_DAPM_MIXER("RECMIXR", RT5670_PWR_MIXER, RT5670_PWR_RM_R_BIT, 0,
rt5670_rec_r_mix, ARRAY_SIZE(rt5670_rec_r_mix)),
/* ADCs */
SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5670_PWR_DIG1,
RT5670_PWR_ADC_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5670_PWR_DIG1,
RT5670_PWR_ADC_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC clock", RT5670_PR_BASE +
RT5670_CHOP_DAC_ADC, 12, 0, NULL, 0),
/* ADC Mux */
SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
&rt5670_sto1_dmic_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
&rt5670_sto_adc_2_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
&rt5670_sto_adc_2_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
&rt5670_sto_adc_1_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
&rt5670_sto_adc_1_mux),
SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
&rt5670_sto2_dmic_mux),
SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
&rt5670_sto2_adc_2_mux),
SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
&rt5670_sto2_adc_2_mux),
SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
&rt5670_sto2_adc_1_mux),
SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
&rt5670_sto2_adc_1_mux),
SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
&rt5670_sto2_adc_lr_mux),
SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
&rt5670_mono_dmic_l_mux),
SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
&rt5670_mono_dmic_r_mux),
SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
&rt5670_mono_adc_l2_mux),
SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
&rt5670_mono_adc_l1_mux),
SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
&rt5670_mono_adc_r1_mux),
SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
&rt5670_mono_adc_r2_mux),
/* ADC Mixer */
SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5670_PWR_DIG2,
RT5670_PWR_ADC_S1F_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC Stereo2 Filter", RT5670_PWR_DIG2,
RT5670_PWR_ADC_S2F_BIT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
rt5670_sto1_adc_l_mix, ARRAY_SIZE(rt5670_sto1_adc_l_mix)),
SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
rt5670_sto1_adc_r_mix, ARRAY_SIZE(rt5670_sto1_adc_r_mix)),
SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
rt5670_sto2_adc_l_mix,
ARRAY_SIZE(rt5670_sto2_adc_l_mix)),
SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
rt5670_sto2_adc_r_mix,
ARRAY_SIZE(rt5670_sto2_adc_r_mix)),
SND_SOC_DAPM_SUPPLY("ADC Mono Left Filter", RT5670_PWR_DIG2,
RT5670_PWR_ADC_MF_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Mono ADC MIXL", RT5670_MONO_ADC_DIG_VOL,
RT5670_L_MUTE_SFT, 1, rt5670_mono_adc_l_mix,
ARRAY_SIZE(rt5670_mono_adc_l_mix)),
SND_SOC_DAPM_SUPPLY("ADC Mono Right Filter", RT5670_PWR_DIG2,
RT5670_PWR_ADC_MF_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Mono ADC MIXR", RT5670_MONO_ADC_DIG_VOL,
RT5670_R_MUTE_SFT, 1, rt5670_mono_adc_r_mix,
ARRAY_SIZE(rt5670_mono_adc_r_mix)),
/* ADC PGA */
SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
/* DSP */
SND_SOC_DAPM_PGA("TxDP_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("TxDP_ADC_L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("TxDP_ADC_R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("TxDC_DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX("TDM Data Mux", SND_SOC_NOPM, 0, 0,
&rt5670_txdp_slot_mux),
SND_SOC_DAPM_MUX("DSP UL Mux", SND_SOC_NOPM, 0, 0,
&rt5670_dsp_ul_mux),
SND_SOC_DAPM_MUX("DSP DL Mux", SND_SOC_NOPM, 0, 0,
&rt5670_dsp_dl_mux),
SND_SOC_DAPM_MUX("RxDP Mux", SND_SOC_NOPM, 0, 0,
&rt5670_rxdp_mux),
/* IF2 Mux */
SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM, 0, 0,
&rt5670_if2_adc_in_mux),
/* Digital Interface */
SND_SOC_DAPM_SUPPLY("I2S1", RT5670_PWR_DIG1,
RT5670_PWR_I2S1_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("I2S2", RT5670_PWR_DIG1,
RT5670_PWR_I2S2_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
/* Digital Interface Select */
SND_SOC_DAPM_MUX("IF1 ADC1 IN1 Mux", SND_SOC_NOPM, 0, 0,
&rt5670_if1_adc1_in1_mux),
SND_SOC_DAPM_MUX("IF1 ADC1 IN2 Mux", SND_SOC_NOPM, 0, 0,
&rt5670_if1_adc1_in2_mux),
SND_SOC_DAPM_MUX("IF1 ADC2 IN Mux", SND_SOC_NOPM, 0, 0,
&rt5670_if1_adc2_in_mux),
SND_SOC_DAPM_MUX("IF1 ADC2 IN1 Mux", SND_SOC_NOPM, 0, 0,
&rt5670_if1_adc2_in1_mux),
SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
&rt5670_vad_adc_mux),
/* Audio Interface */
SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
RT5670_GPIO_CTRL1, RT5670_I2S2_PIN_SFT, 1),
/* Audio DSP */
SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
/* Output Side */
/* DAC mixer before sound effect */
SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
rt5670_dac_l_mix, ARRAY_SIZE(rt5670_dac_l_mix)),
SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
rt5670_dac_r_mix, ARRAY_SIZE(rt5670_dac_r_mix)),
SND_SOC_DAPM_PGA("DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
/* DAC2 channel Mux */
SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0,
&rt5670_dac_l2_mux),
SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0,
&rt5670_dac_r2_mux),
SND_SOC_DAPM_PGA("DAC L2 Volume", RT5670_PWR_DIG1,
RT5670_PWR_DAC_L2_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("DAC R2 Volume", RT5670_PWR_DIG1,
RT5670_PWR_DAC_R2_BIT, 0, NULL, 0),
SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5670_dac1l_mux),
SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5670_dac1r_mux),
/* DAC Mixer */
SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5670_PWR_DIG2,
RT5670_PWR_DAC_S1F_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC Mono Left Filter", RT5670_PWR_DIG2,
RT5670_PWR_DAC_MF_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC Mono Right Filter", RT5670_PWR_DIG2,
RT5670_PWR_DAC_MF_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
rt5670_sto_dac_l_mix,
ARRAY_SIZE(rt5670_sto_dac_l_mix)),
SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
rt5670_sto_dac_r_mix,
ARRAY_SIZE(rt5670_sto_dac_r_mix)),
SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
rt5670_mono_dac_l_mix,
ARRAY_SIZE(rt5670_mono_dac_l_mix)),
SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
rt5670_mono_dac_r_mix,
ARRAY_SIZE(rt5670_mono_dac_r_mix)),
SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
rt5670_dig_l_mix,
ARRAY_SIZE(rt5670_dig_l_mix)),
SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
rt5670_dig_r_mix,
ARRAY_SIZE(rt5670_dig_r_mix)),
/* DACs */
SND_SOC_DAPM_SUPPLY("DAC L1 Power", RT5670_PWR_DIG1,
RT5670_PWR_DAC_L1_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC R1 Power", RT5670_PWR_DIG1,
RT5670_PWR_DAC_R1_BIT, 0, NULL, 0),
SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DAC L2", NULL, RT5670_PWR_DIG1,
RT5670_PWR_DAC_L2_BIT, 0),
SND_SOC_DAPM_DAC("DAC R2", NULL, RT5670_PWR_DIG1,
RT5670_PWR_DAC_R2_BIT, 0),
/* OUT Mixer */
SND_SOC_DAPM_MIXER("OUT MIXL", RT5670_PWR_MIXER, RT5670_PWR_OM_L_BIT,
0, rt5670_out_l_mix, ARRAY_SIZE(rt5670_out_l_mix)),
SND_SOC_DAPM_MIXER("OUT MIXR", RT5670_PWR_MIXER, RT5670_PWR_OM_R_BIT,
0, rt5670_out_r_mix, ARRAY_SIZE(rt5670_out_r_mix)),
/* Ouput Volume */
SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5670_PWR_VOL,
RT5670_PWR_HV_L_BIT, 0,
rt5670_hpvoll_mix, ARRAY_SIZE(rt5670_hpvoll_mix)),
SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5670_PWR_VOL,
RT5670_PWR_HV_R_BIT, 0,
rt5670_hpvolr_mix, ARRAY_SIZE(rt5670_hpvolr_mix)),
SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0),
/* HPO/LOUT/Mono Mixer */
SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0,
rt5670_hpo_mix, ARRAY_SIZE(rt5670_hpo_mix)),
SND_SOC_DAPM_MIXER("LOUT MIX", RT5670_PWR_ANLG1, RT5670_PWR_LM_BIT,
0, rt5670_lout_mix, ARRAY_SIZE(rt5670_lout_mix)),
SND_SOC_DAPM_SUPPLY_S("Improve HP Amp Drv", 1, SND_SOC_NOPM, 0, 0,
rt5670_hp_power_event, SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SUPPLY("HP L Amp", RT5670_PWR_ANLG1,
RT5670_PWR_HP_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("HP R Amp", RT5670_PWR_ANLG1,
RT5670_PWR_HP_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0,
rt5670_hp_event, SND_SOC_DAPM_PRE_PMD |
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
&lout_l_enable_control),
SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
&lout_r_enable_control),
SND_SOC_DAPM_PGA("LOUT Amp", SND_SOC_NOPM, 0, 0, NULL, 0),
/* PDM */
SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5670_PWR_DIG2,
RT5670_PWR_PDM1_BIT, 0, NULL, 0),
SND_SOC_DAPM_MUX("PDM1 L Mux", RT5670_PDM_OUT_CTRL,
RT5670_M_PDM1_L_SFT, 1, &rt5670_pdm1_l_mux),
SND_SOC_DAPM_MUX("PDM1 R Mux", RT5670_PDM_OUT_CTRL,
RT5670_M_PDM1_R_SFT, 1, &rt5670_pdm1_r_mux),
/* Output Lines */
SND_SOC_DAPM_OUTPUT("HPOL"),
SND_SOC_DAPM_OUTPUT("HPOR"),
SND_SOC_DAPM_OUTPUT("LOUTL"),
SND_SOC_DAPM_OUTPUT("LOUTR"),
};
static const struct snd_soc_dapm_widget rt5670_specific_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5670_PWR_DIG2,
RT5670_PWR_PDM2_BIT, 0, NULL, 0),
SND_SOC_DAPM_MUX("PDM2 L Mux", RT5670_PDM_OUT_CTRL,
RT5670_M_PDM2_L_SFT, 1, &rt5670_pdm2_l_mux),
SND_SOC_DAPM_MUX("PDM2 R Mux", RT5670_PDM_OUT_CTRL,
RT5670_M_PDM2_R_SFT, 1, &rt5670_pdm2_r_mux),
SND_SOC_DAPM_OUTPUT("PDM1L"),
SND_SOC_DAPM_OUTPUT("PDM1R"),
SND_SOC_DAPM_OUTPUT("PDM2L"),
SND_SOC_DAPM_OUTPUT("PDM2R"),
};
static const struct snd_soc_dapm_widget rt5672_specific_dapm_widgets[] = {
SND_SOC_DAPM_PGA_E("SPO Amp", SND_SOC_NOPM, 0, 0, NULL, 0,
rt5670_spk_event, SND_SOC_DAPM_PRE_PMD |
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_OUTPUT("SPOLP"),
SND_SOC_DAPM_OUTPUT("SPOLN"),
SND_SOC_DAPM_OUTPUT("SPORP"),
SND_SOC_DAPM_OUTPUT("SPORN"),
};
static const struct snd_soc_dapm_route rt5670_dapm_routes[] = {
{ "ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc },
{ "ADC Stereo2 Filter", NULL, "ADC STO2 ASRC", is_using_asrc },
{ "ADC Mono Left Filter", NULL, "ADC MONO L ASRC", is_using_asrc },
{ "ADC Mono Right Filter", NULL, "ADC MONO R ASRC", is_using_asrc },
{ "DAC Mono Left Filter", NULL, "DAC MONO L ASRC", is_using_asrc },
{ "DAC Mono Right Filter", NULL, "DAC MONO R ASRC", is_using_asrc },
{ "DAC Stereo1 Filter", NULL, "DAC STO ASRC", is_using_asrc },
{ "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", can_use_asrc },
{ "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", can_use_asrc },
{ "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", can_use_asrc },
{ "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", can_use_asrc },
{ "I2S1", NULL, "I2S1 ASRC", can_use_asrc},
{ "I2S2", NULL, "I2S2 ASRC", can_use_asrc},
{ "DMIC1", NULL, "DMIC L1" },
{ "DMIC1", NULL, "DMIC R1" },
{ "DMIC2", NULL, "DMIC L2" },
{ "DMIC2", NULL, "DMIC R2" },
{ "DMIC3", NULL, "DMIC L3" },
{ "DMIC3", NULL, "DMIC R3" },
{ "BST1", NULL, "IN1P" },
{ "BST1", NULL, "IN1N" },
{ "BST1", NULL, "Mic Det Power" },
{ "BST2", NULL, "IN2P" },
{ "BST2", NULL, "IN2N" },
{ "INL VOL", NULL, "IN2P" },
{ "INR VOL", NULL, "IN2N" },
{ "RECMIXL", "INL Switch", "INL VOL" },
{ "RECMIXL", "BST2 Switch", "BST2" },
{ "RECMIXL", "BST1 Switch", "BST1" },
{ "RECMIXR", "INR Switch", "INR VOL" },
{ "RECMIXR", "BST2 Switch", "BST2" },
{ "RECMIXR", "BST1 Switch", "BST1" },
{ "ADC 1", NULL, "RECMIXL" },
{ "ADC 1", NULL, "ADC 1 power" },
{ "ADC 1", NULL, "ADC clock" },
{ "ADC 2", NULL, "RECMIXR" },
{ "ADC 2", NULL, "ADC 2 power" },
{ "ADC 2", NULL, "ADC clock" },
{ "DMIC L1", NULL, "DMIC CLK" },
{ "DMIC L1", NULL, "DMIC1 Power" },
{ "DMIC R1", NULL, "DMIC CLK" },
{ "DMIC R1", NULL, "DMIC1 Power" },
{ "DMIC L2", NULL, "DMIC CLK" },
{ "DMIC L2", NULL, "DMIC2 Power" },
{ "DMIC R2", NULL, "DMIC CLK" },
{ "DMIC R2", NULL, "DMIC2 Power" },
{ "DMIC L3", NULL, "DMIC CLK" },
{ "DMIC L3", NULL, "DMIC3 Power" },
{ "DMIC R3", NULL, "DMIC CLK" },
{ "DMIC R3", NULL, "DMIC3 Power" },
{ "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
{ "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
{ "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
{ "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
{ "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
{ "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
{ "Mono DMIC L Mux", "DMIC1", "DMIC L1" },
{ "Mono DMIC L Mux", "DMIC2", "DMIC L2" },
{ "Mono DMIC L Mux", "DMIC3", "DMIC L3" },
{ "Mono DMIC R Mux", "DMIC1", "DMIC R1" },
{ "Mono DMIC R Mux", "DMIC2", "DMIC R2" },
{ "Mono DMIC R Mux", "DMIC3", "DMIC R3" },
{ "ADC 1_2", NULL, "ADC 1" },
{ "ADC 1_2", NULL, "ADC 2" },
{ "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" },
{ "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
{ "Stereo1 ADC L1 Mux", "ADC", "ADC 1_2" },
{ "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
{ "Stereo1 ADC R1 Mux", "ADC", "ADC 1_2" },
{ "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
{ "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" },
{ "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
{ "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
{ "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
{ "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
{ "Mono ADC L1 Mux", "ADC1", "ADC 1" },
{ "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
{ "Mono ADC R1 Mux", "ADC2", "ADC 2" },
{ "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
{ "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
{ "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
{ "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
{ "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
{ "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
{ "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
{ "Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter" },
{ "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
{ "Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter" },
{ "ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll },
{ "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
{ "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
{ "Mono ADC MIXL", NULL, "ADC Mono Left Filter" },
{ "ADC Mono Left Filter", NULL, "PLL1", is_sys_clk_from_pll },
{ "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
{ "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
{ "Mono ADC MIXR", NULL, "ADC Mono Right Filter" },
{ "ADC Mono Right Filter", NULL, "PLL1", is_sys_clk_from_pll },
{ "Stereo2 ADC L2 Mux", "DMIC", "Stereo2 DMIC Mux" },
{ "Stereo2 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
{ "Stereo2 ADC L1 Mux", "ADC", "ADC 1_2" },
{ "Stereo2 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
{ "Stereo2 ADC R1 Mux", "ADC", "ADC 1_2" },
{ "Stereo2 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
{ "Stereo2 ADC R2 Mux", "DMIC", "Stereo2 DMIC Mux" },
{ "Stereo2 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
{ "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux" },
{ "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux" },
{ "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux" },
{ "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux" },
{ "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
{ "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
{ "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
{ "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
{ "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
{ "Stereo2 ADC MIXL", NULL, "ADC Stereo2 Filter" },
{ "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
{ "Stereo2 ADC MIXR", NULL, "ADC Stereo2 Filter" },
{ "ADC Stereo2 Filter", NULL, "PLL1", is_sys_clk_from_pll },
{ "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" },
{ "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" },
{ "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" },
{ "VAD ADC Mux", "Sto2 ADC L", "Sto2 ADC MIXL" },
{ "VAD_ADC", NULL, "VAD ADC Mux" },
{ "IF_ADC1", NULL, "Stereo1 ADC MIXL" },
{ "IF_ADC1", NULL, "Stereo1 ADC MIXR" },
{ "IF_ADC2", NULL, "Mono ADC MIXL" },
{ "IF_ADC2", NULL, "Mono ADC MIXR" },
{ "IF_ADC3", NULL, "Stereo2 ADC MIXL" },
{ "IF_ADC3", NULL, "Stereo2 ADC MIXR" },
{ "IF1 ADC1 IN1 Mux", "IF_ADC1", "IF_ADC1" },
{ "IF1 ADC1 IN1 Mux", "IF1_ADC3", "IF1_ADC3" },
{ "IF1 ADC1 IN2 Mux", "IF1_ADC1_IN1", "IF1 ADC1 IN1 Mux" },
{ "IF1 ADC1 IN2 Mux", "IF1_ADC4", "TxDP_ADC" },
{ "IF1 ADC2 IN Mux", "IF_ADC2", "IF_ADC2" },
{ "IF1 ADC2 IN Mux", "VAD_ADC", "VAD_ADC" },
{ "IF1 ADC2 IN1 Mux", "IF1_ADC2_IN", "IF1 ADC2 IN Mux" },
{ "IF1 ADC2 IN1 Mux", "IF1_ADC4", "TxDP_ADC" },
{ "IF1_ADC1" , NULL, "IF1 ADC1 IN2 Mux" },
{ "IF1_ADC2" , NULL, "IF1 ADC2 IN1 Mux" },
{ "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
{ "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
{ "Stereo2 ADC MIX", NULL, "Sto2 ADC MIXL" },
{ "Stereo2 ADC MIX", NULL, "Sto2 ADC MIXR" },
{ "Mono ADC MIX", NULL, "Mono ADC MIXL" },
{ "Mono ADC MIX", NULL, "Mono ADC MIXR" },
{ "RxDP Mux", "IF2 DAC", "IF2 DAC" },
{ "RxDP Mux", "IF1 DAC", "IF1 DAC2" },
{ "RxDP Mux", "STO1 ADC Mixer", "Stereo1 ADC MIX" },
{ "RxDP Mux", "STO2 ADC Mixer", "Stereo2 ADC MIX" },
{ "RxDP Mux", "Mono ADC Mixer L", "Mono ADC MIXL" },
{ "RxDP Mux", "Mono ADC Mixer R", "Mono ADC MIXR" },
{ "RxDP Mux", "DAC1", "DAC MIX" },
{ "TDM Data Mux", "Slot 0-1", "Stereo1 ADC MIX" },
{ "TDM Data Mux", "Slot 2-3", "Mono ADC MIX" },
{ "TDM Data Mux", "Slot 4-5", "Stereo2 ADC MIX" },
{ "TDM Data Mux", "Slot 6-7", "IF2 DAC" },
{ "DSP UL Mux", "Bypass", "TDM Data Mux" },
{ "DSP UL Mux", NULL, "I2S DSP" },
{ "DSP DL Mux", "Bypass", "RxDP Mux" },
{ "DSP DL Mux", NULL, "I2S DSP" },
{ "TxDP_ADC_L", NULL, "DSP UL Mux" },
{ "TxDP_ADC_R", NULL, "DSP UL Mux" },
{ "TxDC_DAC", NULL, "DSP DL Mux" },
{ "TxDP_ADC", NULL, "TxDP_ADC_L" },
{ "TxDP_ADC", NULL, "TxDP_ADC_R" },
{ "IF1 ADC", NULL, "I2S1" },
{ "IF1 ADC", NULL, "IF1_ADC1" },
{ "IF1 ADC", NULL, "IF1_ADC2" },
{ "IF1 ADC", NULL, "IF_ADC3" },
{ "IF1 ADC", NULL, "TxDP_ADC" },
{ "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
{ "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
{ "IF2 ADC Mux", "IF_ADC3", "IF_ADC3" },
{ "IF2 ADC Mux", "TxDC_DAC", "TxDC_DAC" },
{ "IF2 ADC Mux", "TxDP_ADC", "TxDP_ADC" },
{ "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" },
{ "IF2 ADC L", NULL, "IF2 ADC Mux" },
{ "IF2 ADC R", NULL, "IF2 ADC Mux" },
{ "IF2 ADC", NULL, "I2S2" },
{ "IF2 ADC", NULL, "IF2 ADC L" },
{ "IF2 ADC", NULL, "IF2 ADC R" },
{ "AIF1TX", NULL, "IF1 ADC" },
{ "AIF2TX", NULL, "IF2 ADC" },
{ "IF1 DAC1", NULL, "AIF1RX" },
{ "IF1 DAC2", NULL, "AIF1RX" },
{ "IF2 DAC", NULL, "AIF2RX" },
{ "IF1 DAC1", NULL, "I2S1" },
{ "IF1 DAC2", NULL, "I2S1" },
{ "IF2 DAC", NULL, "I2S2" },
{ "IF1 DAC2 L", NULL, "IF1 DAC2" },
{ "IF1 DAC2 R", NULL, "IF1 DAC2" },
{ "IF1 DAC1 L", NULL, "IF1 DAC1" },
{ "IF1 DAC1 R", NULL, "IF1 DAC1" },
{ "IF2 DAC L", NULL, "IF2 DAC" },
{ "IF2 DAC R", NULL, "IF2 DAC" },
{ "DAC1 L Mux", "IF1 DAC", "IF1 DAC1 L" },
{ "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" },
{ "DAC1 R Mux", "IF1 DAC", "IF1 DAC1 R" },
{ "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" },
{ "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },
{ "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" },
{ "DAC1 MIXL", NULL, "DAC Stereo1 Filter" },
{ "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" },
{ "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" },
{ "DAC1 MIXR", NULL, "DAC Stereo1 Filter" },
{ "DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll },
{ "DAC Mono Left Filter", NULL, "PLL1", is_sys_clk_from_pll },
{ "DAC Mono Right Filter", NULL, "PLL1", is_sys_clk_from_pll },
{ "DAC MIX", NULL, "DAC1 MIXL" },
{ "DAC MIX", NULL, "DAC1 MIXR" },
{ "Audio DSP", NULL, "DAC1 MIXL" },
{ "Audio DSP", NULL, "DAC1 MIXR" },
{ "DAC L2 Mux", "IF1 DAC", "IF1 DAC2 L" },
{ "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
{ "DAC L2 Mux", "TxDC DAC", "TxDC_DAC" },
{ "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },
{ "DAC L2 Volume", NULL, "DAC L2 Mux" },
{ "DAC L2 Volume", NULL, "DAC Mono Left Filter" },
{ "DAC R2 Mux", "IF1 DAC", "IF1 DAC2 R" },
{ "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
{ "DAC R2 Mux", "TxDC DAC", "TxDC_DAC" },
{ "DAC R2 Mux", "TxDP ADC", "TxDP_ADC" },
{ "DAC R2 Volume", NULL, "DAC R2 Mux" },
{ "DAC R2 Volume", NULL, "DAC Mono Right Filter" },
{ "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
{ "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
{ "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
{ "Stereo DAC MIXL", NULL, "DAC Stereo1 Filter" },
{ "Stereo DAC MIXL", NULL, "DAC L1 Power" },
{ "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
{ "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
{ "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
{ "Stereo DAC MIXR", NULL, "DAC Stereo1 Filter" },
{ "Stereo DAC MIXR", NULL, "DAC R1 Power" },
{ "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
{ "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
{ "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
{ "Mono DAC MIXL", NULL, "DAC Mono Left Filter" },
{ "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
{ "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
{ "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
{ "Mono DAC MIXR", NULL, "DAC Mono Right Filter" },
{ "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
{ "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
{ "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
{ "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
{ "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
{ "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
{ "DAC L1", NULL, "DAC L1 Power" },
{ "DAC L1", NULL, "Stereo DAC MIXL" },
{ "DAC R1", NULL, "DAC R1 Power" },
{ "DAC R1", NULL, "Stereo DAC MIXR" },
{ "DAC L2", NULL, "Mono DAC MIXL" },
{ "DAC R2", NULL, "Mono DAC MIXR" },
{ "OUT MIXL", "BST1 Switch", "BST1" },
{ "OUT MIXL", "INL Switch", "INL VOL" },
{ "OUT MIXL", "DAC L2 Switch", "DAC L2" },
{ "OUT MIXL", "DAC L1 Switch", "DAC L1" },
{ "OUT MIXR", "BST2 Switch", "BST2" },
{ "OUT MIXR", "INR Switch", "INR VOL" },
{ "OUT MIXR", "DAC R2 Switch", "DAC R2" },
{ "OUT MIXR", "DAC R1 Switch", "DAC R1" },
{ "HPOVOL MIXL", "DAC1 Switch", "DAC L1" },
{ "HPOVOL MIXL", "INL Switch", "INL VOL" },
{ "HPOVOL MIXR", "DAC1 Switch", "DAC R1" },
{ "HPOVOL MIXR", "INR Switch", "INR VOL" },
{ "DAC 2", NULL, "DAC L2" },
{ "DAC 2", NULL, "DAC R2" },
{ "DAC 1", NULL, "DAC L1" },
{ "DAC 1", NULL, "DAC R1" },
{ "HPOVOL", NULL, "HPOVOL MIXL" },
{ "HPOVOL", NULL, "HPOVOL MIXR" },
{ "HPO MIX", "DAC1 Switch", "DAC 1" },
{ "HPO MIX", "HPVOL Switch", "HPOVOL" },
{ "LOUT MIX", "DAC L1 Switch", "DAC L1" },
{ "LOUT MIX", "DAC R1 Switch", "DAC R1" },
{ "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" },
{ "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" },
{ "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
{ "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" },
{ "PDM1 L Mux", NULL, "PDM1 Power" },
{ "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
{ "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" },
{ "PDM1 R Mux", NULL, "PDM1 Power" },
{ "HP Amp", NULL, "HPO MIX" },
{ "HP Amp", NULL, "Mic Det Power" },
{ "HPOL", NULL, "HP Amp" },
{ "HPOL", NULL, "HP L Amp" },
{ "HPOL", NULL, "Improve HP Amp Drv" },
{ "HPOR", NULL, "HP Amp" },
{ "HPOR", NULL, "HP R Amp" },
{ "HPOR", NULL, "Improve HP Amp Drv" },
{ "LOUT Amp", NULL, "LOUT MIX" },
{ "LOUT L Playback", "Switch", "LOUT Amp" },
{ "LOUT R Playback", "Switch", "LOUT Amp" },
{ "LOUTL", NULL, "LOUT L Playback" },
{ "LOUTR", NULL, "LOUT R Playback" },
{ "LOUTL", NULL, "Improve HP Amp Drv" },
{ "LOUTR", NULL, "Improve HP Amp Drv" },
};
static const struct snd_soc_dapm_route rt5670_specific_dapm_routes[] = {
{ "PDM2 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
{ "PDM2 L Mux", "Mono DAC", "Mono DAC MIXL" },
{ "PDM2 L Mux", NULL, "PDM2 Power" },
{ "PDM2 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
{ "PDM2 R Mux", "Mono DAC", "Mono DAC MIXR" },
{ "PDM2 R Mux", NULL, "PDM2 Power" },
{ "PDM1L", NULL, "PDM1 L Mux" },
{ "PDM1R", NULL, "PDM1 R Mux" },
{ "PDM2L", NULL, "PDM2 L Mux" },
{ "PDM2R", NULL, "PDM2 R Mux" },
};
static const struct snd_soc_dapm_route rt5672_specific_dapm_routes[] = {
{ "SPO Amp", NULL, "PDM1 L Mux" },
{ "SPO Amp", NULL, "PDM1 R Mux" },
{ "SPOLP", NULL, "SPO Amp" },
{ "SPOLN", NULL, "SPO Amp" },
{ "SPORP", NULL, "SPO Amp" },
{ "SPORN", NULL, "SPO Amp" },
};
static int rt5670_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
unsigned int val_len = 0, val_clk, mask_clk;
int pre_div, bclk_ms, frame_size;
rt5670->lrck[dai->id] = params_rate(params);
pre_div = rl6231_get_clk_info(rt5670->sysclk, rt5670->lrck[dai->id]);
if (pre_div < 0) {
dev_err(component->dev, "Unsupported clock setting %d for DAI %d\n",
rt5670->lrck[dai->id], dai->id);
return -EINVAL;
}
frame_size = snd_soc_params_to_frame_size(params);
if (frame_size < 0) {
dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
return -EINVAL;
}
bclk_ms = frame_size > 32;
rt5670->bclk[dai->id] = rt5670->lrck[dai->id] * (32 << bclk_ms);
dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
rt5670->bclk[dai->id], rt5670->lrck[dai->id]);
dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
bclk_ms, pre_div, dai->id);
switch (params_width(params)) {
case 16:
break;
case 20:
val_len |= RT5670_I2S_DL_20;
break;
case 24:
val_len |= RT5670_I2S_DL_24;
break;
case 8:
val_len |= RT5670_I2S_DL_8;
break;
default:
return -EINVAL;
}
switch (dai->id) {
case RT5670_AIF1:
mask_clk = RT5670_I2S_BCLK_MS1_MASK | RT5670_I2S_PD1_MASK;
val_clk = bclk_ms << RT5670_I2S_BCLK_MS1_SFT |
pre_div << RT5670_I2S_PD1_SFT;
snd_soc_component_update_bits(component, RT5670_I2S1_SDP,
RT5670_I2S_DL_MASK, val_len);
snd_soc_component_update_bits(component, RT5670_ADDA_CLK1, mask_clk, val_clk);
break;
case RT5670_AIF2:
mask_clk = RT5670_I2S_BCLK_MS2_MASK | RT5670_I2S_PD2_MASK;
val_clk = bclk_ms << RT5670_I2S_BCLK_MS2_SFT |
pre_div << RT5670_I2S_PD2_SFT;
snd_soc_component_update_bits(component, RT5670_I2S2_SDP,
RT5670_I2S_DL_MASK, val_len);
snd_soc_component_update_bits(component, RT5670_ADDA_CLK1, mask_clk, val_clk);
break;
default:
dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
return -EINVAL;
}
return 0;
}
static int rt5670_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
rt5670->master[dai->id] = 1;
break;
case SND_SOC_DAIFMT_CBS_CFS:
reg_val |= RT5670_I2S_MS_S;
rt5670->master[dai->id] = 0;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
reg_val |= RT5670_I2S_BP_INV;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_LEFT_J:
reg_val |= RT5670_I2S_DF_LEFT;
break;
case SND_SOC_DAIFMT_DSP_A:
reg_val |= RT5670_I2S_DF_PCM_A;
break;
case SND_SOC_DAIFMT_DSP_B:
reg_val |= RT5670_I2S_DF_PCM_B;
break;
default:
return -EINVAL;
}
switch (dai->id) {
case RT5670_AIF1:
snd_soc_component_update_bits(component, RT5670_I2S1_SDP,
RT5670_I2S_MS_MASK | RT5670_I2S_BP_MASK |
RT5670_I2S_DF_MASK, reg_val);
break;
case RT5670_AIF2:
snd_soc_component_update_bits(component, RT5670_I2S2_SDP,
RT5670_I2S_MS_MASK | RT5670_I2S_BP_MASK |
RT5670_I2S_DF_MASK, reg_val);
break;
default:
dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
return -EINVAL;
}
return 0;
}
static int rt5670_set_codec_sysclk(struct snd_soc_component *component, int clk_id,
int source, unsigned int freq, int dir)
{
struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0;
switch (clk_id) {
case RT5670_SCLK_S_MCLK:
reg_val |= RT5670_SCLK_SRC_MCLK;
break;
case RT5670_SCLK_S_PLL1:
reg_val |= RT5670_SCLK_SRC_PLL1;
break;
case RT5670_SCLK_S_RCCLK:
reg_val |= RT5670_SCLK_SRC_RCCLK;
break;
default:
dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
return -EINVAL;
}
snd_soc_component_update_bits(component, RT5670_GLB_CLK,
RT5670_SCLK_SRC_MASK, reg_val);
rt5670->sysclk = freq;
if (clk_id != RT5670_SCLK_S_RCCLK)
rt5670->sysclk_src = clk_id;
dev_dbg(component->dev, "Sysclk : %dHz clock id : %d\n", freq, clk_id);
return 0;
}
static int rt5670_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
unsigned int freq_in, unsigned int freq_out)
{
struct snd_soc_component *component = dai->component;
struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
struct rl6231_pll_code pll_code;
int ret;
if (source == rt5670->pll_src && freq_in == rt5670->pll_in &&
freq_out == rt5670->pll_out)
return 0;
if (!freq_in || !freq_out) {
dev_dbg(component->dev, "PLL disabled\n");
rt5670->pll_in = 0;
rt5670->pll_out = 0;
snd_soc_component_update_bits(component, RT5670_GLB_CLK,
RT5670_SCLK_SRC_MASK, RT5670_SCLK_SRC_MCLK);
return 0;
}
switch (source) {
case RT5670_PLL1_S_MCLK:
snd_soc_component_update_bits(component, RT5670_GLB_CLK,
RT5670_PLL1_SRC_MASK, RT5670_PLL1_SRC_MCLK);
break;
case RT5670_PLL1_S_BCLK1:
case RT5670_PLL1_S_BCLK2:
case RT5670_PLL1_S_BCLK3:
case RT5670_PLL1_S_BCLK4:
switch (dai->id) {
case RT5670_AIF1:
snd_soc_component_update_bits(component, RT5670_GLB_CLK,
RT5670_PLL1_SRC_MASK, RT5670_PLL1_SRC_BCLK1);
break;
case RT5670_AIF2:
snd_soc_component_update_bits(component, RT5670_GLB_CLK,
RT5670_PLL1_SRC_MASK, RT5670_PLL1_SRC_BCLK2);
break;
default:
dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
return -EINVAL;
}
break;
default:
dev_err(component->dev, "Unknown PLL source %d\n", source);
return -EINVAL;
}
ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
if (ret < 0) {
dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
return ret;
}
dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
pll_code.n_code, pll_code.k_code);
snd_soc_component_write(component, RT5670_PLL_CTRL1,
pll_code.n_code << RT5670_PLL_N_SFT | pll_code.k_code);
snd_soc_component_write(component, RT5670_PLL_CTRL2,
((pll_code.m_bp ? 0 : pll_code.m_code) << RT5670_PLL_M_SFT) |
(pll_code.m_bp << RT5670_PLL_M_BP_SFT));
rt5670->pll_in = freq_in;
rt5670->pll_out = freq_out;
rt5670->pll_src = source;
return 0;
}
static int rt5670_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
unsigned int val = 0;
if (rx_mask || tx_mask)
val |= (1 << 14);
switch (slots) {
case 4:
val |= (1 << 12);
break;
case 6:
val |= (2 << 12);
break;
case 8:
val |= (3 << 12);
break;
case 2:
break;
default:
return -EINVAL;
}
switch (slot_width) {
case 20:
val |= (1 << 10);
break;
case 24:
val |= (2 << 10);
break;
case 32:
val |= (3 << 10);
break;
case 16:
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, RT5670_TDM_CTRL_1, 0x7c00, val);
return 0;
}
static int rt5670_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
{
struct snd_soc_component *component = dai->component;
dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio);
if (dai->id != RT5670_AIF1)
return 0;
if ((ratio % 50) == 0)
snd_soc_component_update_bits(component, RT5670_GEN_CTRL3,
RT5670_TDM_DATA_MODE_SEL, RT5670_TDM_DATA_MODE_50FS);
else
snd_soc_component_update_bits(component, RT5670_GEN_CTRL3,
RT5670_TDM_DATA_MODE_SEL, RT5670_TDM_DATA_MODE_NOR);
return 0;
}
static int rt5670_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_PREPARE:
if (SND_SOC_BIAS_STANDBY == snd_soc_component_get_bias_level(component)) {
snd_soc_component_update_bits(component, RT5670_PWR_ANLG1,
RT5670_PWR_VREF1 | RT5670_PWR_MB |
RT5670_PWR_BG | RT5670_PWR_VREF2,
RT5670_PWR_VREF1 | RT5670_PWR_MB |
RT5670_PWR_BG | RT5670_PWR_VREF2);
mdelay(10);
snd_soc_component_update_bits(component, RT5670_PWR_ANLG1,
RT5670_PWR_FV1 | RT5670_PWR_FV2,
RT5670_PWR_FV1 | RT5670_PWR_FV2);
snd_soc_component_update_bits(component, RT5670_CHARGE_PUMP,
RT5670_OSW_L_MASK | RT5670_OSW_R_MASK,
RT5670_OSW_L_DIS | RT5670_OSW_R_DIS);
snd_soc_component_update_bits(component, RT5670_DIG_MISC, 0x1, 0x1);
snd_soc_component_update_bits(component, RT5670_PWR_ANLG1,
RT5670_LDO_SEL_MASK, 0x5);
}
break;
case SND_SOC_BIAS_STANDBY:
snd_soc_component_update_bits(component, RT5670_PWR_ANLG1,
RT5670_PWR_VREF1 | RT5670_PWR_VREF2 |
RT5670_PWR_FV1 | RT5670_PWR_FV2, 0);
snd_soc_component_update_bits(component, RT5670_PWR_ANLG1,
RT5670_LDO_SEL_MASK, 0x3);
break;
case SND_SOC_BIAS_OFF:
if (rt5670->jd_mode)
snd_soc_component_update_bits(component, RT5670_PWR_ANLG1,
RT5670_PWR_VREF1 | RT5670_PWR_MB |
RT5670_PWR_BG | RT5670_PWR_VREF2 |
RT5670_PWR_FV1 | RT5670_PWR_FV2,
RT5670_PWR_MB | RT5670_PWR_BG);
else
snd_soc_component_update_bits(component, RT5670_PWR_ANLG1,
RT5670_PWR_VREF1 | RT5670_PWR_MB |
RT5670_PWR_BG | RT5670_PWR_VREF2 |
RT5670_PWR_FV1 | RT5670_PWR_FV2, 0);
snd_soc_component_update_bits(component, RT5670_DIG_MISC, 0x1, 0x0);
break;
default:
break;
}
return 0;
}
static int rt5670_probe(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
switch (snd_soc_component_read(component, RT5670_RESET) & RT5670_ID_MASK) {
case RT5670_ID_5670:
case RT5670_ID_5671:
snd_soc_dapm_new_controls(dapm,
rt5670_specific_dapm_widgets,
ARRAY_SIZE(rt5670_specific_dapm_widgets));
snd_soc_dapm_add_routes(dapm,
rt5670_specific_dapm_routes,
ARRAY_SIZE(rt5670_specific_dapm_routes));
break;
case RT5670_ID_5672:
snd_soc_dapm_new_controls(dapm,
rt5672_specific_dapm_widgets,
ARRAY_SIZE(rt5672_specific_dapm_widgets));
snd_soc_dapm_add_routes(dapm,
rt5672_specific_dapm_routes,
ARRAY_SIZE(rt5672_specific_dapm_routes));
break;
default:
dev_err(component->dev,
"The driver is for RT5670 RT5671 or RT5672 only\n");
return -ENODEV;
}
rt5670->component = component;
return 0;
}
static void rt5670_remove(struct snd_soc_component *component)
{
struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
regmap_write(rt5670->regmap, RT5670_RESET, 0);
snd_soc_jack_free_gpios(rt5670->jack, 1, &rt5670->hp_gpio);
}
#ifdef CONFIG_PM
static int rt5670_suspend(struct snd_soc_component *component)
{
struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
regcache_cache_only(rt5670->regmap, true);
regcache_mark_dirty(rt5670->regmap);
return 0;
}
static int rt5670_resume(struct snd_soc_component *component)
{
struct rt5670_priv *rt5670 = snd_soc_component_get_drvdata(component);
regcache_cache_only(rt5670->regmap, false);
regcache_sync(rt5670->regmap);
return 0;
}
#else
#define rt5670_suspend NULL
#define rt5670_resume NULL
#endif
#define RT5670_STEREO_RATES SNDRV_PCM_RATE_8000_96000
#define RT5670_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
static const struct snd_soc_dai_ops rt5670_aif_dai_ops = {
.hw_params = rt5670_hw_params,
.set_fmt = rt5670_set_dai_fmt,
.set_tdm_slot = rt5670_set_tdm_slot,
.set_pll = rt5670_set_dai_pll,
.set_bclk_ratio = rt5670_set_bclk_ratio,
};
static struct snd_soc_dai_driver rt5670_dai[] = {
{
.name = "rt5670-aif1",
.id = RT5670_AIF1,
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT5670_STEREO_RATES,
.formats = RT5670_FORMATS,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT5670_STEREO_RATES,
.formats = RT5670_FORMATS,
},
.ops = &rt5670_aif_dai_ops,
.symmetric_rate = 1,
},
{
.name = "rt5670-aif2",
.id = RT5670_AIF2,
.playback = {
.stream_name = "AIF2 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT5670_STEREO_RATES,
.formats = RT5670_FORMATS,
},
.capture = {
.stream_name = "AIF2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT5670_STEREO_RATES,
.formats = RT5670_FORMATS,
},
.ops = &rt5670_aif_dai_ops,
.symmetric_rate = 1,
},
};
static const struct snd_soc_component_driver soc_component_dev_rt5670 = {
.probe = rt5670_probe,
.remove = rt5670_remove,
.suspend = rt5670_suspend,
.resume = rt5670_resume,
.set_bias_level = rt5670_set_bias_level,
.set_sysclk = rt5670_set_codec_sysclk,
.controls = rt5670_snd_controls,
.num_controls = ARRAY_SIZE(rt5670_snd_controls),
.dapm_widgets = rt5670_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt5670_dapm_widgets),
.dapm_routes = rt5670_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(rt5670_dapm_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config rt5670_regmap = {
.reg_bits = 8,
.val_bits = 16,
.use_single_read = true,
.use_single_write = true,
.max_register = RT5670_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5670_ranges) *
RT5670_PR_SPACING),
.volatile_reg = rt5670_volatile_register,
.readable_reg = rt5670_readable_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = rt5670_reg,
.num_reg_defaults = ARRAY_SIZE(rt5670_reg),
.ranges = rt5670_ranges,
.num_ranges = ARRAY_SIZE(rt5670_ranges),
};
static const struct i2c_device_id rt5670_i2c_id[] = {
{ "rt5670", 0 },
{ "rt5671", 0 },
{ "rt5672", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, rt5670_i2c_id);
#ifdef CONFIG_ACPI
static const struct acpi_device_id rt5670_acpi_match[] = {
{ "10EC5670", 0},
{ "10EC5672", 0},
{ "10EC5640", 0}, /* quirk */
{ },
};
MODULE_DEVICE_TABLE(acpi, rt5670_acpi_match);
#endif
static int rt5670_quirk_cb(const struct dmi_system_id *id)
{
rt5670_quirk = (unsigned long)id->driver_data;
return 1;
}
static const struct dmi_system_id dmi_platform_intel_quirks[] = {
{
.callback = rt5670_quirk_cb,
.ident = "Intel Braswell",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Intel Corporation"),
DMI_MATCH(DMI_BOARD_NAME, "Braswell CRB"),
},
.driver_data = (unsigned long *)(RT5670_DMIC_EN |
RT5670_DMIC1_IN2P |
RT5670_GPIO1_IS_IRQ |
RT5670_JD_MODE1),
},
{
.callback = rt5670_quirk_cb,
.ident = "Dell Wyse 3040",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
DMI_MATCH(DMI_PRODUCT_NAME, "Wyse 3040"),
},
.driver_data = (unsigned long *)(RT5670_DMIC_EN |
RT5670_DMIC1_IN2P |
RT5670_GPIO1_IS_IRQ |
RT5670_JD_MODE1),
},
{
.callback = rt5670_quirk_cb,
.ident = "Lenovo Thinkpad Tablet 8",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad 8"),
},
.driver_data = (unsigned long *)(RT5670_DMIC_EN |
RT5670_DMIC2_INR |
RT5670_GPIO1_IS_IRQ |
RT5670_JD_MODE1),
},
{
.callback = rt5670_quirk_cb,
.ident = "Lenovo Thinkpad Tablet 10",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad 10"),
},
.driver_data = (unsigned long *)(RT5670_DMIC_EN |
RT5670_DMIC1_IN2P |
RT5670_GPIO1_IS_IRQ |
RT5670_JD_MODE1),
},
{
.callback = rt5670_quirk_cb,
.ident = "Lenovo Thinkpad Tablet 10",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad Tablet B"),
},
.driver_data = (unsigned long *)(RT5670_DMIC_EN |
RT5670_DMIC1_IN2P |
RT5670_GPIO1_IS_IRQ |
RT5670_JD_MODE1),
},
{
.callback = rt5670_quirk_cb,
.ident = "Lenovo Miix 2 10",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo Miix 2 10"),
},
.driver_data = (unsigned long *)(RT5670_DMIC_EN |
RT5670_DMIC1_IN2P |
RT5670_GPIO1_IS_EXT_SPK_EN |
RT5670_JD_MODE2),
},
{
.callback = rt5670_quirk_cb,
.ident = "Dell Venue 8 Pro 5855",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
DMI_MATCH(DMI_PRODUCT_NAME, "Venue 8 Pro 5855"),
},
.driver_data = (unsigned long *)(RT5670_DMIC_EN |
RT5670_DMIC2_INR |
RT5670_GPIO1_IS_IRQ |
RT5670_JD_MODE3),
},
{
.callback = rt5670_quirk_cb,
.ident = "Dell Venue 10 Pro 5055",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
DMI_MATCH(DMI_PRODUCT_NAME, "Venue 10 Pro 5055"),
},
.driver_data = (unsigned long *)(RT5670_DMIC_EN |
RT5670_DMIC2_INR |
RT5670_GPIO1_IS_IRQ |
RT5670_JD_MODE1),
},
{
.callback = rt5670_quirk_cb,
.ident = "Aegex 10 tablet (RU2)",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "AEGEX"),
DMI_MATCH(DMI_PRODUCT_VERSION, "RU2"),
},
.driver_data = (unsigned long *)(RT5670_DMIC_EN |
RT5670_DMIC2_INR |
RT5670_GPIO1_IS_IRQ |
RT5670_JD_MODE3),
},
{}
};
const char *rt5670_components(void)
{
unsigned long quirk;
bool dmic1 = false;
bool dmic2 = false;
bool dmic3 = false;
if (quirk_override) {
quirk = quirk_override;
} else {
dmi_check_system(dmi_platform_intel_quirks);
quirk = rt5670_quirk;
}
if ((quirk & RT5670_DMIC1_IN2P) ||
(quirk & RT5670_DMIC1_GPIO6) ||
(quirk & RT5670_DMIC1_GPIO7))
dmic1 = true;
if ((quirk & RT5670_DMIC2_INR) ||
(quirk & RT5670_DMIC2_GPIO8))
dmic2 = true;
if (quirk & RT5670_DMIC3_GPIO5)
dmic3 = true;
if (dmic1 && dmic2)
return "cfg-spk:2 cfg-mic:dmics12";
else if (dmic1)
return "cfg-spk:2 cfg-mic:dmic1";
else if (dmic2)
return "cfg-spk:2 cfg-mic:dmic2";
else if (dmic3)
return "cfg-spk:2 cfg-mic:dmic3";
return NULL;
}
EXPORT_SYMBOL_GPL(rt5670_components);
static int rt5670_i2c_probe(struct i2c_client *i2c)
{
struct rt5670_priv *rt5670;
int ret;
unsigned int val;
rt5670 = devm_kzalloc(&i2c->dev,
sizeof(struct rt5670_priv),
GFP_KERNEL);
if (NULL == rt5670)
return -ENOMEM;
i2c_set_clientdata(i2c, rt5670);
dmi_check_system(dmi_platform_intel_quirks);
if (quirk_override) {
dev_info(&i2c->dev, "Overriding quirk 0x%x => 0x%x\n",
(unsigned int)rt5670_quirk, quirk_override);
rt5670_quirk = quirk_override;
}
if (rt5670_quirk & RT5670_GPIO1_IS_IRQ) {
rt5670->gpio1_is_irq = true;
dev_info(&i2c->dev, "quirk GPIO1 is IRQ\n");
}
if (rt5670_quirk & RT5670_GPIO1_IS_EXT_SPK_EN) {
rt5670->gpio1_is_ext_spk_en = true;
dev_info(&i2c->dev, "quirk GPIO1 is external speaker enable\n");
}
if (rt5670_quirk & RT5670_IN2_DIFF) {
rt5670->in2_diff = true;
dev_info(&i2c->dev, "quirk IN2_DIFF\n");
}
if (rt5670_quirk & RT5670_DMIC_EN) {
rt5670->dmic_en = true;
dev_info(&i2c->dev, "quirk DMIC enabled\n");
}
if (rt5670_quirk & RT5670_DMIC1_IN2P) {
rt5670->dmic1_data_pin = RT5670_DMIC_DATA_IN2P;
dev_info(&i2c->dev, "quirk DMIC1 on IN2P pin\n");
}
if (rt5670_quirk & RT5670_DMIC1_GPIO6) {
rt5670->dmic1_data_pin = RT5670_DMIC_DATA_GPIO6;
dev_info(&i2c->dev, "quirk DMIC1 on GPIO6 pin\n");
}
if (rt5670_quirk & RT5670_DMIC1_GPIO7) {
rt5670->dmic1_data_pin = RT5670_DMIC_DATA_GPIO7;
dev_info(&i2c->dev, "quirk DMIC1 on GPIO7 pin\n");
}
if (rt5670_quirk & RT5670_DMIC2_INR) {
rt5670->dmic2_data_pin = RT5670_DMIC_DATA_IN3N;
dev_info(&i2c->dev, "quirk DMIC2 on INR pin\n");
}
if (rt5670_quirk & RT5670_DMIC2_GPIO8) {
rt5670->dmic2_data_pin = RT5670_DMIC_DATA_GPIO8;
dev_info(&i2c->dev, "quirk DMIC2 on GPIO8 pin\n");
}
if (rt5670_quirk & RT5670_DMIC3_GPIO5) {
rt5670->dmic3_data_pin = RT5670_DMIC_DATA_GPIO5;
dev_info(&i2c->dev, "quirk DMIC3 on GPIO5 pin\n");
}
if (rt5670_quirk & RT5670_JD_MODE1) {
rt5670->jd_mode = 1;
dev_info(&i2c->dev, "quirk JD mode 1\n");
}
if (rt5670_quirk & RT5670_JD_MODE2) {
rt5670->jd_mode = 2;
dev_info(&i2c->dev, "quirk JD mode 2\n");
}
if (rt5670_quirk & RT5670_JD_MODE3) {
rt5670->jd_mode = 3;
dev_info(&i2c->dev, "quirk JD mode 3\n");
}
/*
* Enable the emulated "DAC1 Playback Switch" by default to avoid
* muting the output with older UCM profiles.
*/
rt5670->dac1_playback_switch_l = true;
rt5670->dac1_playback_switch_r = true;
/* The Power-On-Reset values for the DAC1 mixer have the DAC1 input enabled. */
rt5670->dac1_mixl_dac1_switch = true;
rt5670->dac1_mixr_dac1_switch = true;
rt5670->regmap = devm_regmap_init_i2c(i2c, &rt5670_regmap);
if (IS_ERR(rt5670->regmap)) {
ret = PTR_ERR(rt5670->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
regmap_read(rt5670->regmap, RT5670_VENDOR_ID2, &val);
if (val != RT5670_DEVICE_ID) {
dev_err(&i2c->dev,
"Device with ID register %#x is not rt5670/72\n", val);
return -ENODEV;
}
regmap_write(rt5670->regmap, RT5670_RESET, 0);
regmap_update_bits(rt5670->regmap, RT5670_PWR_ANLG1,
RT5670_PWR_HP_L | RT5670_PWR_HP_R |
RT5670_PWR_VREF2, RT5670_PWR_VREF2);
msleep(100);
regmap_write(rt5670->regmap, RT5670_RESET, 0);
regmap_read(rt5670->regmap, RT5670_VENDOR_ID, &val);
if (val >= 4)
regmap_write(rt5670->regmap, RT5670_GPIO_CTRL3, 0x0980);
else
regmap_write(rt5670->regmap, RT5670_GPIO_CTRL3, 0x0d00);
ret = regmap_register_patch(rt5670->regmap, init_list,
ARRAY_SIZE(init_list));
if (ret != 0)
dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
regmap_update_bits(rt5670->regmap, RT5670_DIG_MISC,
RT5670_MCLK_DET, RT5670_MCLK_DET);
if (rt5670->in2_diff)
regmap_update_bits(rt5670->regmap, RT5670_IN2,
RT5670_IN_DF2, RT5670_IN_DF2);
if (rt5670->gpio1_is_irq) {
/* for push button */
regmap_write(rt5670->regmap, RT5670_IL_CMD, 0x0000);
regmap_write(rt5670->regmap, RT5670_IL_CMD2, 0x0010);
regmap_write(rt5670->regmap, RT5670_IL_CMD3, 0x0014);
/* for irq */
regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
RT5670_GP1_PIN_MASK, RT5670_GP1_PIN_IRQ);
regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL2,
RT5670_GP1_PF_MASK, RT5670_GP1_PF_OUT);
}
if (rt5670->gpio1_is_ext_spk_en) {
regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
RT5670_GP1_PIN_MASK, RT5670_GP1_PIN_GPIO1);
regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL2,
RT5670_GP1_PF_MASK, RT5670_GP1_PF_OUT);
}
if (rt5670->jd_mode) {
regmap_update_bits(rt5670->regmap, RT5670_GLB_CLK,
RT5670_SCLK_SRC_MASK, RT5670_SCLK_SRC_RCCLK);
rt5670->sysclk = 0;
rt5670->sysclk_src = RT5670_SCLK_S_RCCLK;
regmap_update_bits(rt5670->regmap, RT5670_PWR_ANLG1,
RT5670_PWR_MB, RT5670_PWR_MB);
regmap_update_bits(rt5670->regmap, RT5670_PWR_ANLG2,
RT5670_PWR_JD1, RT5670_PWR_JD1);
regmap_update_bits(rt5670->regmap, RT5670_IRQ_CTRL1,
RT5670_JD1_1_EN_MASK, RT5670_JD1_1_EN);
regmap_update_bits(rt5670->regmap, RT5670_JD_CTRL3,
RT5670_JD_TRI_CBJ_SEL_MASK |
RT5670_JD_TRI_HPO_SEL_MASK,
RT5670_JD_CBJ_JD1_1 | RT5670_JD_HPO_JD1_1);
switch (rt5670->jd_mode) {
case 1:
regmap_update_bits(rt5670->regmap, RT5670_A_JD_CTRL1,
RT5670_JD1_MODE_MASK,
RT5670_JD1_MODE_0);
break;
case 2:
regmap_update_bits(rt5670->regmap, RT5670_A_JD_CTRL1,
RT5670_JD1_MODE_MASK,
RT5670_JD1_MODE_1);
break;
case 3:
regmap_update_bits(rt5670->regmap, RT5670_A_JD_CTRL1,
RT5670_JD1_MODE_MASK,
RT5670_JD1_MODE_2);
break;
default:
break;
}
}
if (rt5670->dmic_en) {
regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
RT5670_GP2_PIN_MASK,
RT5670_GP2_PIN_DMIC1_SCL);
switch (rt5670->dmic1_data_pin) {
case RT5670_DMIC_DATA_IN2P:
regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL1,
RT5670_DMIC_1_DP_MASK,
RT5670_DMIC_1_DP_IN2P);
break;
case RT5670_DMIC_DATA_GPIO6:
regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL1,
RT5670_DMIC_1_DP_MASK,
RT5670_DMIC_1_DP_GPIO6);
regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
RT5670_GP6_PIN_MASK,
RT5670_GP6_PIN_DMIC1_SDA);
break;
case RT5670_DMIC_DATA_GPIO7:
regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL1,
RT5670_DMIC_1_DP_MASK,
RT5670_DMIC_1_DP_GPIO7);
regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
RT5670_GP7_PIN_MASK,
RT5670_GP7_PIN_DMIC1_SDA);
break;
default:
break;
}
switch (rt5670->dmic2_data_pin) {
case RT5670_DMIC_DATA_IN3N:
regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL1,
RT5670_DMIC_2_DP_MASK,
RT5670_DMIC_2_DP_IN3N);
break;
case RT5670_DMIC_DATA_GPIO8:
regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL1,
RT5670_DMIC_2_DP_MASK,
RT5670_DMIC_2_DP_GPIO8);
regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
RT5670_GP8_PIN_MASK,
RT5670_GP8_PIN_DMIC2_SDA);
break;
default:
break;
}
switch (rt5670->dmic3_data_pin) {
case RT5670_DMIC_DATA_GPIO5:
regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL2,
RT5670_DMIC_3_DP_MASK,
RT5670_DMIC_3_DP_GPIO5);
regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
RT5670_GP5_PIN_MASK,
RT5670_GP5_PIN_DMIC3_SDA);
break;
case RT5670_DMIC_DATA_GPIO9:
case RT5670_DMIC_DATA_GPIO10:
dev_err(&i2c->dev,
"Always use GPIO5 as DMIC3 data pin\n");
break;
default:
break;
}
}
pm_runtime_enable(&i2c->dev);
pm_request_idle(&i2c->dev);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_rt5670,
rt5670_dai, ARRAY_SIZE(rt5670_dai));
if (ret < 0)
goto err;
return 0;
err:
pm_runtime_disable(&i2c->dev);
return ret;
}
static void rt5670_i2c_remove(struct i2c_client *i2c)
{
pm_runtime_disable(&i2c->dev);
}
static struct i2c_driver rt5670_i2c_driver = {
.driver = {
.name = "rt5670",
.acpi_match_table = ACPI_PTR(rt5670_acpi_match),
},
.probe = rt5670_i2c_probe,
.remove = rt5670_i2c_remove,
.id_table = rt5670_i2c_id,
};
module_i2c_driver(rt5670_i2c_driver);
MODULE_DESCRIPTION("ASoC RT5670 driver");
MODULE_AUTHOR("Bard Liao <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/rt5670.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// ALSA SoC Audio driver for CS47L15 codec
//
// Copyright (C) 2016-2019 Cirrus Logic, Inc. and
// Cirrus Logic International Semiconductor Ltd.
//
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <linux/irqchip/irq-madera.h>
#include <linux/mfd/madera/core.h>
#include <linux/mfd/madera/registers.h>
#include "madera.h"
#include "wm_adsp.h"
#define CS47L15_NUM_ADSP 1
#define CS47L15_MONO_OUTPUTS 1
/* Mid-mode registers */
#define CS47L15_ADC_INT_BIAS_MASK 0x3800
#define CS47L15_ADC_INT_BIAS_SHIFT 11
#define CS47L15_PGA_BIAS_SEL_MASK 0x03
#define CS47L15_PGA_BIAS_SEL_SHIFT 0
#define DRV_NAME "cs47l15-codec"
struct cs47l15 {
struct madera_priv core;
struct madera_fll fll[2];
bool in1_lp_mode;
};
static const struct cs_dsp_region cs47l15_dsp1_regions[] = {
{ .type = WMFW_ADSP2_PM, .base = 0x080000 },
{ .type = WMFW_ADSP2_ZM, .base = 0x0e0000 },
{ .type = WMFW_ADSP2_XM, .base = 0x0a0000 },
{ .type = WMFW_ADSP2_YM, .base = 0x0c0000 },
};
static const char * const cs47l15_outdemux_texts[] = {
"HPOUT",
"EPOUT",
};
static SOC_ENUM_SINGLE_DECL(cs47l15_outdemux_enum, SND_SOC_NOPM, 0,
cs47l15_outdemux_texts);
static const struct snd_kcontrol_new cs47l15_outdemux =
SOC_DAPM_ENUM_EXT("HPOUT1 Demux", cs47l15_outdemux_enum,
madera_out1_demux_get, madera_out1_demux_put);
static int cs47l15_adsp_power_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct cs47l15 *cs47l15 = snd_soc_component_get_drvdata(component);
struct madera_priv *priv = &cs47l15->core;
struct madera *madera = priv->madera;
unsigned int freq;
int ret;
ret = regmap_read(madera->regmap, MADERA_DSP_CLOCK_2, &freq);
if (ret != 0) {
dev_err(madera->dev,
"Failed to read MADERA_DSP_CLOCK_2: %d\n", ret);
return ret;
}
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
ret = madera_set_adsp_clk(&cs47l15->core, w->shift, freq);
if (ret)
return ret;
break;
default:
break;
}
return wm_adsp_early_event(w, kcontrol, event);
}
#define CS47L15_NG_SRC(name, base) \
SOC_SINGLE(name " NG HPOUT1L Switch", base, 0, 1, 0), \
SOC_SINGLE(name " NG HPOUT1R Switch", base, 1, 1, 0), \
SOC_SINGLE(name " NG SPKOUTL Switch", base, 6, 1, 0), \
SOC_SINGLE(name " NG SPKDAT1L Switch", base, 8, 1, 0), \
SOC_SINGLE(name " NG SPKDAT1R Switch", base, 9, 1, 0)
static int cs47l15_in1_adc_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct cs47l15 *cs47l15 = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = !!cs47l15->in1_lp_mode;
return 0;
}
static int cs47l15_in1_adc_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct cs47l15 *cs47l15 = snd_soc_component_get_drvdata(component);
if (!!ucontrol->value.integer.value[0] == cs47l15->in1_lp_mode)
return 0;
switch (ucontrol->value.integer.value[0]) {
case 0:
/* Set IN1 to normal mode */
snd_soc_component_update_bits(component, MADERA_DMIC1L_CONTROL,
MADERA_IN1_OSR_MASK,
5 << MADERA_IN1_OSR_SHIFT);
snd_soc_component_update_bits(component, CS47L15_ADC_INT_BIAS,
CS47L15_ADC_INT_BIAS_MASK,
4 << CS47L15_ADC_INT_BIAS_SHIFT);
snd_soc_component_update_bits(component, CS47L15_PGA_BIAS_SEL,
CS47L15_PGA_BIAS_SEL_MASK, 0);
cs47l15->in1_lp_mode = false;
break;
default:
/* Set IN1 to LP mode */
snd_soc_component_update_bits(component, MADERA_DMIC1L_CONTROL,
MADERA_IN1_OSR_MASK,
4 << MADERA_IN1_OSR_SHIFT);
snd_soc_component_update_bits(component, CS47L15_ADC_INT_BIAS,
CS47L15_ADC_INT_BIAS_MASK,
1 << CS47L15_ADC_INT_BIAS_SHIFT);
snd_soc_component_update_bits(component, CS47L15_PGA_BIAS_SEL,
CS47L15_PGA_BIAS_SEL_MASK,
3 << CS47L15_PGA_BIAS_SEL_SHIFT);
cs47l15->in1_lp_mode = true;
break;
}
return 1;
}
static const struct snd_kcontrol_new cs47l15_snd_controls[] = {
SOC_ENUM("IN1 OSR", madera_in_dmic_osr[0]),
SOC_ENUM("IN2 OSR", madera_in_dmic_osr[1]),
SOC_SINGLE_RANGE_TLV("IN1L Volume", MADERA_IN1L_CONTROL,
MADERA_IN1L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
SOC_SINGLE_RANGE_TLV("IN1R Volume", MADERA_IN1R_CONTROL,
MADERA_IN1R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
SOC_ENUM("IN HPF Cutoff Frequency", madera_in_hpf_cut_enum),
SOC_SINGLE("IN1L HPF Switch", MADERA_IN1L_CONTROL, MADERA_IN1L_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN1R HPF Switch", MADERA_IN1R_CONTROL, MADERA_IN1R_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN2L HPF Switch", MADERA_IN2L_CONTROL, MADERA_IN2L_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN2R HPF Switch", MADERA_IN2R_CONTROL, MADERA_IN2R_HPF_SHIFT, 1, 0),
SOC_SINGLE_TLV("IN1L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_1L,
MADERA_IN1L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_SINGLE_TLV("IN1R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_1R,
MADERA_IN1R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_SINGLE_TLV("IN2L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_2L,
MADERA_IN2L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_SINGLE_TLV("IN2R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_2R,
MADERA_IN2R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_ENUM("Input Ramp Up", madera_in_vi_ramp),
SOC_ENUM("Input Ramp Down", madera_in_vd_ramp),
MADERA_MIXER_CONTROLS("EQ1", MADERA_EQ1MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("EQ2", MADERA_EQ2MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("EQ3", MADERA_EQ3MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("EQ4", MADERA_EQ4MIX_INPUT_1_SOURCE),
MADERA_EQ_CONTROL("EQ1 Coefficients", MADERA_EQ1_2),
SOC_SINGLE_TLV("EQ1 B1 Volume", MADERA_EQ1_1, MADERA_EQ1_B1_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ1 B2 Volume", MADERA_EQ1_1, MADERA_EQ1_B2_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ1 B3 Volume", MADERA_EQ1_1, MADERA_EQ1_B3_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ1 B4 Volume", MADERA_EQ1_2, MADERA_EQ1_B4_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ1 B5 Volume", MADERA_EQ1_2, MADERA_EQ1_B5_GAIN_SHIFT,
24, 0, madera_eq_tlv),
MADERA_EQ_CONTROL("EQ2 Coefficients", MADERA_EQ2_2),
SOC_SINGLE_TLV("EQ2 B1 Volume", MADERA_EQ2_1, MADERA_EQ2_B1_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ2 B2 Volume", MADERA_EQ2_1, MADERA_EQ2_B2_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ2 B3 Volume", MADERA_EQ2_1, MADERA_EQ2_B3_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ2 B4 Volume", MADERA_EQ2_2, MADERA_EQ2_B4_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ2 B5 Volume", MADERA_EQ2_2, MADERA_EQ2_B5_GAIN_SHIFT,
24, 0, madera_eq_tlv),
MADERA_EQ_CONTROL("EQ3 Coefficients", MADERA_EQ3_2),
SOC_SINGLE_TLV("EQ3 B1 Volume", MADERA_EQ3_1, MADERA_EQ3_B1_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ3 B2 Volume", MADERA_EQ3_1, MADERA_EQ3_B2_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ3 B3 Volume", MADERA_EQ3_1, MADERA_EQ3_B3_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ3 B4 Volume", MADERA_EQ3_2, MADERA_EQ3_B4_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ3 B5 Volume", MADERA_EQ3_2, MADERA_EQ3_B5_GAIN_SHIFT,
24, 0, madera_eq_tlv),
MADERA_EQ_CONTROL("EQ4 Coefficients", MADERA_EQ4_2),
SOC_SINGLE_TLV("EQ4 B1 Volume", MADERA_EQ4_1, MADERA_EQ4_B1_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ4 B2 Volume", MADERA_EQ4_1, MADERA_EQ4_B2_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ4 B3 Volume", MADERA_EQ4_1, MADERA_EQ4_B3_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ4 B4 Volume", MADERA_EQ4_2, MADERA_EQ4_B4_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ4 B5 Volume", MADERA_EQ4_2, MADERA_EQ4_B5_GAIN_SHIFT,
24, 0, madera_eq_tlv),
MADERA_MIXER_CONTROLS("DRC1L", MADERA_DRC1LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DRC1R", MADERA_DRC1RMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DRC2L", MADERA_DRC2LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DRC2R", MADERA_DRC2RMIX_INPUT_1_SOURCE),
SND_SOC_BYTES_MASK("DRC1", MADERA_DRC1_CTRL1, 5,
MADERA_DRC1R_ENA | MADERA_DRC1L_ENA),
SND_SOC_BYTES_MASK("DRC2", MADERA_DRC2_CTRL1, 5,
MADERA_DRC2R_ENA | MADERA_DRC2L_ENA),
MADERA_MIXER_CONTROLS("LHPF1", MADERA_HPLP1MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("LHPF2", MADERA_HPLP2MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("LHPF3", MADERA_HPLP3MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("LHPF4", MADERA_HPLP4MIX_INPUT_1_SOURCE),
MADERA_LHPF_CONTROL("LHPF1 Coefficients", MADERA_HPLPF1_2),
MADERA_LHPF_CONTROL("LHPF2 Coefficients", MADERA_HPLPF2_2),
MADERA_LHPF_CONTROL("LHPF3 Coefficients", MADERA_HPLPF3_2),
MADERA_LHPF_CONTROL("LHPF4 Coefficients", MADERA_HPLPF4_2),
SOC_ENUM("LHPF1 Mode", madera_lhpf1_mode),
SOC_ENUM("LHPF2 Mode", madera_lhpf2_mode),
SOC_ENUM("LHPF3 Mode", madera_lhpf3_mode),
SOC_ENUM("LHPF4 Mode", madera_lhpf4_mode),
MADERA_RATE_ENUM("ISRC1 FSL", madera_isrc_fsl[0]),
MADERA_RATE_ENUM("ISRC2 FSL", madera_isrc_fsl[1]),
MADERA_RATE_ENUM("ISRC1 FSH", madera_isrc_fsh[0]),
MADERA_RATE_ENUM("ISRC2 FSH", madera_isrc_fsh[1]),
WM_ADSP2_PRELOAD_SWITCH("DSP1", 1),
MADERA_MIXER_CONTROLS("DSP1L", MADERA_DSP1LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DSP1R", MADERA_DSP1RMIX_INPUT_1_SOURCE),
SOC_SINGLE_TLV("Noise Generator Volume", MADERA_COMFORT_NOISE_GENERATOR,
MADERA_NOISE_GEN_GAIN_SHIFT, 0x16, 0, madera_noise_tlv),
MADERA_MIXER_CONTROLS("HPOUT1L", MADERA_OUT1LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("HPOUT1R", MADERA_OUT1RMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SPKOUTL", MADERA_OUT4LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SPKDAT1L", MADERA_OUT5LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SPKDAT1R", MADERA_OUT5RMIX_INPUT_1_SOURCE),
SOC_SINGLE("HPOUT1 SC Protect Switch", MADERA_HP1_SHORT_CIRCUIT_CTRL,
MADERA_HP1_SC_ENA_SHIFT, 1, 0),
SOC_SINGLE("SPKDAT1 High Performance Switch", MADERA_OUTPUT_PATH_CONFIG_5L,
MADERA_OUT5_OSR_SHIFT, 1, 0),
SOC_DOUBLE_R("HPOUT1 Digital Switch", MADERA_DAC_DIGITAL_VOLUME_1L,
MADERA_DAC_DIGITAL_VOLUME_1R, MADERA_OUT1L_MUTE_SHIFT, 1, 1),
SOC_SINGLE("Speaker Digital Switch", MADERA_DAC_DIGITAL_VOLUME_4L,
MADERA_OUT4L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R("SPKDAT1 Digital Switch", MADERA_DAC_DIGITAL_VOLUME_5L,
MADERA_DAC_DIGITAL_VOLUME_5R, MADERA_OUT5L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", MADERA_DAC_DIGITAL_VOLUME_1L,
MADERA_DAC_DIGITAL_VOLUME_1R, MADERA_OUT1L_VOL_SHIFT,
0xbf, 0, madera_digital_tlv),
SOC_SINGLE_TLV("Speaker Digital Volume", MADERA_DAC_DIGITAL_VOLUME_4L,
MADERA_OUT4L_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", MADERA_DAC_DIGITAL_VOLUME_5L,
MADERA_DAC_DIGITAL_VOLUME_5R, MADERA_OUT5L_VOL_SHIFT,
0xbf, 0, madera_digital_tlv),
SOC_DOUBLE("SPKDAT1 Switch", MADERA_PDM_SPK1_CTRL_1, MADERA_SPK1L_MUTE_SHIFT,
MADERA_SPK1R_MUTE_SHIFT, 1, 1),
SOC_ENUM("Output Ramp Up", madera_out_vi_ramp),
SOC_ENUM("Output Ramp Down", madera_out_vd_ramp),
SOC_SINGLE("Noise Gate Switch", MADERA_NOISE_GATE_CONTROL,
MADERA_NGATE_ENA_SHIFT, 1, 0),
SOC_SINGLE_TLV("Noise Gate Threshold Volume", MADERA_NOISE_GATE_CONTROL,
MADERA_NGATE_THR_SHIFT, 7, 1, madera_ng_tlv),
SOC_ENUM("Noise Gate Hold", madera_ng_hold),
SOC_SINGLE_BOOL_EXT("IN1 LP Mode Switch", 0,
cs47l15_in1_adc_get, cs47l15_in1_adc_put),
CS47L15_NG_SRC("HPOUT1L", MADERA_NOISE_GATE_SELECT_1L),
CS47L15_NG_SRC("HPOUT1R", MADERA_NOISE_GATE_SELECT_1R),
CS47L15_NG_SRC("SPKOUTL", MADERA_NOISE_GATE_SELECT_4L),
CS47L15_NG_SRC("SPKDAT1L", MADERA_NOISE_GATE_SELECT_5L),
CS47L15_NG_SRC("SPKDAT1R", MADERA_NOISE_GATE_SELECT_5R),
MADERA_MIXER_CONTROLS("AIF1TX1", MADERA_AIF1TX1MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF1TX2", MADERA_AIF1TX2MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF1TX3", MADERA_AIF1TX3MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF1TX4", MADERA_AIF1TX4MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF1TX5", MADERA_AIF1TX5MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF1TX6", MADERA_AIF1TX6MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF2TX1", MADERA_AIF2TX1MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF2TX2", MADERA_AIF2TX2MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF2TX3", MADERA_AIF2TX3MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF2TX4", MADERA_AIF2TX4MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF3TX1", MADERA_AIF3TX1MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF3TX2", MADERA_AIF3TX2MIX_INPUT_1_SOURCE),
MADERA_GAINMUX_CONTROLS("SPDIF1TX1", MADERA_SPDIF1TX1MIX_INPUT_1_SOURCE),
MADERA_GAINMUX_CONTROLS("SPDIF1TX2", MADERA_SPDIF1TX2MIX_INPUT_1_SOURCE),
WM_ADSP_FW_CONTROL("DSP1", 0),
};
MADERA_MIXER_ENUMS(EQ1, MADERA_EQ1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(EQ2, MADERA_EQ2MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(EQ3, MADERA_EQ3MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(EQ4, MADERA_EQ4MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DRC1L, MADERA_DRC1LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DRC1R, MADERA_DRC1RMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DRC2L, MADERA_DRC2LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DRC2R, MADERA_DRC2RMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(LHPF1, MADERA_HPLP1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(LHPF2, MADERA_HPLP2MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(LHPF3, MADERA_HPLP3MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(LHPF4, MADERA_HPLP4MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP1L, MADERA_DSP1LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP1R, MADERA_DSP1RMIX_INPUT_1_SOURCE);
MADERA_DSP_AUX_ENUMS(DSP1, MADERA_DSP1AUX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(PWM1, MADERA_PWM1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(PWM2, MADERA_PWM2MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(OUT1L, MADERA_OUT1LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(OUT1R, MADERA_OUT1RMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SPKOUTL, MADERA_OUT4LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SPKDAT1L, MADERA_OUT5LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SPKDAT1R, MADERA_OUT5RMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX1, MADERA_AIF1TX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX2, MADERA_AIF1TX2MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX3, MADERA_AIF1TX3MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX4, MADERA_AIF1TX4MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX5, MADERA_AIF1TX5MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX6, MADERA_AIF1TX6MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF2TX1, MADERA_AIF2TX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF2TX2, MADERA_AIF2TX2MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF2TX3, MADERA_AIF2TX3MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF2TX4, MADERA_AIF2TX4MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF3TX1, MADERA_AIF3TX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF3TX2, MADERA_AIF3TX2MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(SPD1TX1, MADERA_SPDIF1TX1MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(SPD1TX2, MADERA_SPDIF1TX2MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1INT1, MADERA_ISRC1INT1MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1INT2, MADERA_ISRC1INT2MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1INT3, MADERA_ISRC1INT3MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1INT4, MADERA_ISRC1INT4MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1DEC1, MADERA_ISRC1DEC1MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1DEC2, MADERA_ISRC1DEC2MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1DEC3, MADERA_ISRC1DEC3MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1DEC4, MADERA_ISRC1DEC4MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2INT1, MADERA_ISRC2INT1MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2INT2, MADERA_ISRC2INT2MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2INT3, MADERA_ISRC2INT3MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2INT4, MADERA_ISRC2INT4MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2DEC1, MADERA_ISRC2DEC1MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2DEC2, MADERA_ISRC2DEC2MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2DEC3, MADERA_ISRC2DEC3MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2DEC4, MADERA_ISRC2DEC4MIX_INPUT_1_SOURCE);
static const char * const cs47l15_aec_loopback_texts[] = {
"HPOUT1L", "HPOUT1R", "SPKOUTL", "SPKDAT1L", "SPKDAT1R",
};
static const unsigned int cs47l15_aec_loopback_values[] = {
0, 1, 6, 8, 9,
};
static const struct soc_enum cs47l15_aec1_loopback =
SOC_VALUE_ENUM_SINGLE(MADERA_DAC_AEC_CONTROL_1,
MADERA_AEC1_LOOPBACK_SRC_SHIFT, 0xf,
ARRAY_SIZE(cs47l15_aec_loopback_texts),
cs47l15_aec_loopback_texts,
cs47l15_aec_loopback_values);
static const struct soc_enum cs47l15_aec2_loopback =
SOC_VALUE_ENUM_SINGLE(MADERA_DAC_AEC_CONTROL_2,
MADERA_AEC2_LOOPBACK_SRC_SHIFT, 0xf,
ARRAY_SIZE(cs47l15_aec_loopback_texts),
cs47l15_aec_loopback_texts,
cs47l15_aec_loopback_values);
static const struct snd_kcontrol_new cs47l15_aec_loopback_mux[] = {
SOC_DAPM_ENUM("AEC1 Loopback", cs47l15_aec1_loopback),
SOC_DAPM_ENUM("AEC2 Loopback", cs47l15_aec2_loopback),
};
static const struct snd_soc_dapm_widget cs47l15_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("SYSCLK", MADERA_SYSTEM_CLOCK_1, MADERA_SYSCLK_ENA_SHIFT,
0, madera_sysclk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("OPCLK", MADERA_OUTPUT_SYSTEM_CLOCK,
MADERA_OPCLK_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DSPCLK", MADERA_DSP_CLOCK_1, MADERA_DSP_CLK_ENA_SHIFT,
0, madera_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD1", 20, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("MICVDD", 0, SND_SOC_DAPM_REGULATOR_BYPASS),
SND_SOC_DAPM_REGULATOR_SUPPLY("SPKVDD", 0, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS1", MADERA_MIC_BIAS_CTRL_1,
MADERA_MICB1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS1A", MADERA_MIC_BIAS_CTRL_5,
MADERA_MICB1A_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS1B", MADERA_MIC_BIAS_CTRL_5,
MADERA_MICB1B_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS1C", MADERA_MIC_BIAS_CTRL_5,
MADERA_MICB1C_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("FXCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_FX, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("ISRC1CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_ISRC1, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("ISRC2CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_ISRC2, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("OUTCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_OUT, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("SPDCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_SPD, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_DSP1, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("AIF1TXCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_AIF1, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("AIF2TXCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_AIF2, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("AIF3TXCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_AIF3, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("PWMCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_PWM, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SIGGEN("TONE"),
SND_SOC_DAPM_SIGGEN("NOISE"),
SND_SOC_DAPM_INPUT("IN1ALN"),
SND_SOC_DAPM_INPUT("IN1ALP"),
SND_SOC_DAPM_INPUT("IN1BLN"),
SND_SOC_DAPM_INPUT("IN1BLP"),
SND_SOC_DAPM_INPUT("IN1ARN"),
SND_SOC_DAPM_INPUT("IN1ARP"),
SND_SOC_DAPM_INPUT("IN1BRN"),
SND_SOC_DAPM_INPUT("IN1BRP"),
SND_SOC_DAPM_INPUT("IN2N"),
SND_SOC_DAPM_INPUT("IN2P"),
SND_SOC_DAPM_INPUT("SPKRXDAT"),
SND_SOC_DAPM_MUX("IN1L Analog Mux", SND_SOC_NOPM, 0, 0, &madera_inmux[0]),
SND_SOC_DAPM_MUX("IN1R Analog Mux", SND_SOC_NOPM, 0, 0, &madera_inmux[1]),
SND_SOC_DAPM_MUX("IN1L Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[0]),
SND_SOC_DAPM_MUX("IN1R Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[0]),
SND_SOC_DAPM_MUX("IN2L Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[1]),
SND_SOC_DAPM_MUX("IN2R Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[1]),
SND_SOC_DAPM_OUTPUT("DRC1 Signal Activity"),
SND_SOC_DAPM_OUTPUT("DRC2 Signal Activity"),
SND_SOC_DAPM_OUTPUT("DSP Trigger Out"),
SND_SOC_DAPM_DEMUX("HPOUT1 Demux", SND_SOC_NOPM, 0, 0, &cs47l15_outdemux),
SND_SOC_DAPM_MUX("HPOUT1 Mono Mux", SND_SOC_NOPM, 0, 0, &cs47l15_outdemux),
SND_SOC_DAPM_PGA("PWM1 Driver", MADERA_PWM_DRIVE_1, MADERA_PWM1_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA("PWM2 Driver", MADERA_PWM_DRIVE_1, MADERA_PWM2_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 0,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 1,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 2,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 3,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 4,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX6", NULL, 5,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0,
MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX2", NULL, 1,
MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX3", NULL, 2,
MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX4", NULL, 3,
MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF3TX1", NULL, 0,
MADERA_AIF3_TX_ENABLES, MADERA_AIF3TX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF3TX2", NULL, 1,
MADERA_AIF3_TX_ENABLES, MADERA_AIF3TX2_ENA_SHIFT, 0),
SND_SOC_DAPM_PGA_E("OUT1L", SND_SOC_NOPM,
MADERA_OUT1L_ENA_SHIFT, 0, NULL, 0, madera_hp_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT1R", SND_SOC_NOPM,
MADERA_OUT1R_ENA_SHIFT, 0, NULL, 0, madera_hp_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT4L", SND_SOC_NOPM,
MADERA_OUT4L_ENA_SHIFT, 0, NULL, 0, madera_spk_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT5L", MADERA_OUTPUT_ENABLES_1,
MADERA_OUT5L_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT5R", MADERA_OUTPUT_ENABLES_1,
MADERA_OUT5R_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA("SPD1TX1", MADERA_SPD1_TX_CONTROL,
MADERA_SPD1_VAL1_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("SPD1TX2", MADERA_SPD1_TX_CONTROL,
MADERA_SPD1_VAL2_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("SPD1", MADERA_SPD1_TX_CONTROL,
MADERA_SPD1_ENA_SHIFT, 0, NULL, 0),
/*
* mux_in widgets : arranged in the order of sources
* specified in MADERA_MIXER_INPUT_ROUTES
*/
SND_SOC_DAPM_PGA("Noise Generator", MADERA_COMFORT_NOISE_GENERATOR,
MADERA_NOISE_GEN_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("Tone Generator 1", MADERA_TONE_GENERATOR_1,
MADERA_TONE1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("Tone Generator 2", MADERA_TONE_GENERATOR_1,
MADERA_TONE2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SIGGEN("HAPTICS"),
SND_SOC_DAPM_MUX("AEC1 Loopback", MADERA_DAC_AEC_CONTROL_1,
MADERA_AEC1_LOOPBACK_ENA_SHIFT, 0,
&cs47l15_aec_loopback_mux[0]),
SND_SOC_DAPM_MUX("AEC2 Loopback", MADERA_DAC_AEC_CONTROL_2,
MADERA_AEC2_LOOPBACK_ENA_SHIFT, 0,
&cs47l15_aec_loopback_mux[1]),
SND_SOC_DAPM_PGA_E("IN1L", MADERA_INPUT_ENABLES, MADERA_IN1L_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN1R", MADERA_INPUT_ENABLES, MADERA_IN1R_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN2L", MADERA_INPUT_ENABLES, MADERA_IN2L_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN2R", MADERA_INPUT_ENABLES, MADERA_IN2R_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 0,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 1,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 2,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 3,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 4,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX6", NULL, 5,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0,
MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX2", NULL, 1,
MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX3", NULL, 2,
MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX4", NULL, 3,
MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF3RX1", NULL, 0,
MADERA_AIF3_RX_ENABLES, MADERA_AIF3RX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF3RX2", NULL, 1,
MADERA_AIF3_RX_ENABLES, MADERA_AIF3RX2_ENA_SHIFT, 0),
SND_SOC_DAPM_PGA("EQ1", MADERA_EQ1_1, MADERA_EQ1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ2", MADERA_EQ2_1, MADERA_EQ2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ3", MADERA_EQ3_1, MADERA_EQ3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ4", MADERA_EQ4_1, MADERA_EQ4_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("DRC1L", MADERA_DRC1_CTRL1, MADERA_DRC1L_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("DRC1R", MADERA_DRC1_CTRL1, MADERA_DRC1R_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("DRC2L", MADERA_DRC2_CTRL1, MADERA_DRC2L_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("DRC2R", MADERA_DRC2_CTRL1, MADERA_DRC2R_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF1", MADERA_HPLPF1_1, MADERA_LHPF1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("LHPF2", MADERA_HPLPF2_1, MADERA_LHPF2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("LHPF3", MADERA_HPLPF3_1, MADERA_LHPF3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("LHPF4", MADERA_HPLPF4_1, MADERA_LHPF4_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC1", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_DEC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC2", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_DEC2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC3", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_DEC3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC4", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_DEC4_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1INT1", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_INT1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1INT2", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_INT2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1INT3", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_INT3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1INT4", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_INT4_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2DEC1", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_DEC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2DEC2", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_DEC2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2DEC3", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_DEC3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2DEC4", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_DEC4_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2INT1", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_INT1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2INT2", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_INT2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2INT3", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_INT3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2INT4", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_INT4_ENA_SHIFT, 0, NULL, 0),
WM_ADSP2("DSP1", 0, cs47l15_adsp_power_ev),
/* end of ordered widget list */
MADERA_MIXER_WIDGETS(EQ1, "EQ1"),
MADERA_MIXER_WIDGETS(EQ2, "EQ2"),
MADERA_MIXER_WIDGETS(EQ3, "EQ3"),
MADERA_MIXER_WIDGETS(EQ4, "EQ4"),
MADERA_MIXER_WIDGETS(DRC1L, "DRC1L"),
MADERA_MIXER_WIDGETS(DRC1R, "DRC1R"),
MADERA_MIXER_WIDGETS(DRC2L, "DRC2L"),
MADERA_MIXER_WIDGETS(DRC2R, "DRC2R"),
SND_SOC_DAPM_SWITCH("DRC1 Activity Output", SND_SOC_NOPM, 0, 0,
&madera_drc_activity_output_mux[0]),
SND_SOC_DAPM_SWITCH("DRC2 Activity Output", SND_SOC_NOPM, 0, 0,
&madera_drc_activity_output_mux[1]),
MADERA_MIXER_WIDGETS(LHPF1, "LHPF1"),
MADERA_MIXER_WIDGETS(LHPF2, "LHPF2"),
MADERA_MIXER_WIDGETS(LHPF3, "LHPF3"),
MADERA_MIXER_WIDGETS(LHPF4, "LHPF4"),
MADERA_MIXER_WIDGETS(PWM1, "PWM1"),
MADERA_MIXER_WIDGETS(PWM2, "PWM2"),
MADERA_MIXER_WIDGETS(OUT1L, "HPOUT1L"),
MADERA_MIXER_WIDGETS(OUT1R, "HPOUT1R"),
MADERA_MIXER_WIDGETS(SPKOUTL, "SPKOUTL"),
MADERA_MIXER_WIDGETS(SPKDAT1L, "SPKDAT1L"),
MADERA_MIXER_WIDGETS(SPKDAT1R, "SPKDAT1R"),
MADERA_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"),
MADERA_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"),
MADERA_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"),
MADERA_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"),
MADERA_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"),
MADERA_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"),
MADERA_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"),
MADERA_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"),
MADERA_MIXER_WIDGETS(AIF2TX3, "AIF2TX3"),
MADERA_MIXER_WIDGETS(AIF2TX4, "AIF2TX4"),
MADERA_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"),
MADERA_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"),
MADERA_MUX_WIDGETS(SPD1TX1, "SPDIF1TX1"),
MADERA_MUX_WIDGETS(SPD1TX2, "SPDIF1TX2"),
MADERA_DSP_WIDGETS(DSP1, "DSP1"),
SND_SOC_DAPM_SWITCH("DSP1 Trigger Output", SND_SOC_NOPM, 0, 0,
&madera_dsp_trigger_output_mux[0]),
MADERA_MUX_WIDGETS(ISRC1DEC1, "ISRC1DEC1"),
MADERA_MUX_WIDGETS(ISRC1DEC2, "ISRC1DEC2"),
MADERA_MUX_WIDGETS(ISRC1DEC3, "ISRC1DEC3"),
MADERA_MUX_WIDGETS(ISRC1DEC4, "ISRC1DEC4"),
MADERA_MUX_WIDGETS(ISRC1INT1, "ISRC1INT1"),
MADERA_MUX_WIDGETS(ISRC1INT2, "ISRC1INT2"),
MADERA_MUX_WIDGETS(ISRC1INT3, "ISRC1INT3"),
MADERA_MUX_WIDGETS(ISRC1INT4, "ISRC1INT4"),
MADERA_MUX_WIDGETS(ISRC2DEC1, "ISRC2DEC1"),
MADERA_MUX_WIDGETS(ISRC2DEC2, "ISRC2DEC2"),
MADERA_MUX_WIDGETS(ISRC2DEC3, "ISRC2DEC3"),
MADERA_MUX_WIDGETS(ISRC2DEC4, "ISRC2DEC4"),
MADERA_MUX_WIDGETS(ISRC2INT1, "ISRC2INT1"),
MADERA_MUX_WIDGETS(ISRC2INT2, "ISRC2INT2"),
MADERA_MUX_WIDGETS(ISRC2INT3, "ISRC2INT3"),
MADERA_MUX_WIDGETS(ISRC2INT4, "ISRC2INT4"),
SND_SOC_DAPM_OUTPUT("HPOUTL"),
SND_SOC_DAPM_OUTPUT("HPOUTR"),
SND_SOC_DAPM_OUTPUT("EPOUTP"),
SND_SOC_DAPM_OUTPUT("EPOUTN"),
SND_SOC_DAPM_OUTPUT("SPKOUTN"),
SND_SOC_DAPM_OUTPUT("SPKOUTP"),
SND_SOC_DAPM_OUTPUT("SPKDAT1L"),
SND_SOC_DAPM_OUTPUT("SPKDAT1R"),
SND_SOC_DAPM_OUTPUT("SPDIF1"),
SND_SOC_DAPM_OUTPUT("MICSUPP"),
};
#define MADERA_MIXER_INPUT_ROUTES(name) \
{ name, "Noise Generator", "Noise Generator" }, \
{ name, "Tone Generator 1", "Tone Generator 1" }, \
{ name, "Tone Generator 2", "Tone Generator 2" }, \
{ name, "Haptics", "HAPTICS" }, \
{ name, "AEC1", "AEC1 Loopback" }, \
{ name, "AEC2", "AEC2 Loopback" }, \
{ name, "IN1L", "IN1L" }, \
{ name, "IN1R", "IN1R" }, \
{ name, "IN2L", "IN2L" }, \
{ name, "IN2R", "IN2R" }, \
{ name, "AIF1RX1", "AIF1RX1" }, \
{ name, "AIF1RX2", "AIF1RX2" }, \
{ name, "AIF1RX3", "AIF1RX3" }, \
{ name, "AIF1RX4", "AIF1RX4" }, \
{ name, "AIF1RX5", "AIF1RX5" }, \
{ name, "AIF1RX6", "AIF1RX6" }, \
{ name, "AIF2RX1", "AIF2RX1" }, \
{ name, "AIF2RX2", "AIF2RX2" }, \
{ name, "AIF2RX3", "AIF2RX3" }, \
{ name, "AIF2RX4", "AIF2RX4" }, \
{ name, "AIF3RX1", "AIF3RX1" }, \
{ name, "AIF3RX2", "AIF3RX2" }, \
{ name, "EQ1", "EQ1" }, \
{ name, "EQ2", "EQ2" }, \
{ name, "EQ3", "EQ3" }, \
{ name, "EQ4", "EQ4" }, \
{ name, "DRC1L", "DRC1L" }, \
{ name, "DRC1R", "DRC1R" }, \
{ name, "DRC2L", "DRC2L" }, \
{ name, "DRC2R", "DRC2R" }, \
{ name, "LHPF1", "LHPF1" }, \
{ name, "LHPF2", "LHPF2" }, \
{ name, "LHPF3", "LHPF3" }, \
{ name, "LHPF4", "LHPF4" }, \
{ name, "ISRC1DEC1", "ISRC1DEC1" }, \
{ name, "ISRC1DEC2", "ISRC1DEC2" }, \
{ name, "ISRC1DEC3", "ISRC1DEC3" }, \
{ name, "ISRC1DEC4", "ISRC1DEC4" }, \
{ name, "ISRC1INT1", "ISRC1INT1" }, \
{ name, "ISRC1INT2", "ISRC1INT2" }, \
{ name, "ISRC1INT3", "ISRC1INT3" }, \
{ name, "ISRC1INT4", "ISRC1INT4" }, \
{ name, "ISRC2DEC1", "ISRC2DEC1" }, \
{ name, "ISRC2DEC2", "ISRC2DEC2" }, \
{ name, "ISRC2DEC3", "ISRC2DEC3" }, \
{ name, "ISRC2DEC4", "ISRC2DEC4" }, \
{ name, "ISRC2INT1", "ISRC2INT1" }, \
{ name, "ISRC2INT2", "ISRC2INT2" }, \
{ name, "ISRC2INT3", "ISRC2INT3" }, \
{ name, "ISRC2INT4", "ISRC2INT4" }, \
{ name, "DSP1.1", "DSP1" }, \
{ name, "DSP1.2", "DSP1" }, \
{ name, "DSP1.3", "DSP1" }, \
{ name, "DSP1.4", "DSP1" }, \
{ name, "DSP1.5", "DSP1" }, \
{ name, "DSP1.6", "DSP1" }
static const struct snd_soc_dapm_route cs47l15_dapm_routes[] = {
/* Internal clock domains */
{ "EQ1", NULL, "FXCLK" },
{ "EQ2", NULL, "FXCLK" },
{ "EQ3", NULL, "FXCLK" },
{ "EQ4", NULL, "FXCLK" },
{ "DRC1L", NULL, "FXCLK" },
{ "DRC1R", NULL, "FXCLK" },
{ "DRC2L", NULL, "FXCLK" },
{ "DRC2R", NULL, "FXCLK" },
{ "LHPF1", NULL, "FXCLK" },
{ "LHPF2", NULL, "FXCLK" },
{ "LHPF3", NULL, "FXCLK" },
{ "LHPF4", NULL, "FXCLK" },
{ "PWM1 Mixer", NULL, "PWMCLK" },
{ "PWM2 Mixer", NULL, "PWMCLK" },
{ "OUT1L", NULL, "OUTCLK" },
{ "OUT1R", NULL, "OUTCLK" },
{ "OUT4L", NULL, "OUTCLK" },
{ "OUT5L", NULL, "OUTCLK" },
{ "OUT5R", NULL, "OUTCLK" },
{ "AIF1TX1", NULL, "AIF1TXCLK" },
{ "AIF1TX2", NULL, "AIF1TXCLK" },
{ "AIF1TX3", NULL, "AIF1TXCLK" },
{ "AIF1TX4", NULL, "AIF1TXCLK" },
{ "AIF1TX5", NULL, "AIF1TXCLK" },
{ "AIF1TX6", NULL, "AIF1TXCLK" },
{ "AIF2TX1", NULL, "AIF2TXCLK" },
{ "AIF2TX2", NULL, "AIF2TXCLK" },
{ "AIF2TX3", NULL, "AIF2TXCLK" },
{ "AIF2TX4", NULL, "AIF2TXCLK" },
{ "AIF3TX1", NULL, "AIF3TXCLK" },
{ "AIF3TX2", NULL, "AIF3TXCLK" },
{ "SPD1TX1", NULL, "SPDCLK" },
{ "SPD1TX2", NULL, "SPDCLK" },
{ "DSP1", NULL, "DSP1CLK" },
{ "ISRC1DEC1", NULL, "ISRC1CLK" },
{ "ISRC1DEC2", NULL, "ISRC1CLK" },
{ "ISRC1DEC3", NULL, "ISRC1CLK" },
{ "ISRC1DEC4", NULL, "ISRC1CLK" },
{ "ISRC1INT1", NULL, "ISRC1CLK" },
{ "ISRC1INT2", NULL, "ISRC1CLK" },
{ "ISRC1INT3", NULL, "ISRC1CLK" },
{ "ISRC1INT4", NULL, "ISRC1CLK" },
{ "ISRC2DEC1", NULL, "ISRC2CLK" },
{ "ISRC2DEC2", NULL, "ISRC2CLK" },
{ "ISRC2DEC3", NULL, "ISRC2CLK" },
{ "ISRC2DEC4", NULL, "ISRC2CLK" },
{ "ISRC2INT1", NULL, "ISRC2CLK" },
{ "ISRC2INT2", NULL, "ISRC2CLK" },
{ "ISRC2INT3", NULL, "ISRC2CLK" },
{ "ISRC2INT4", NULL, "ISRC2CLK" },
{ "OUT1L", NULL, "CPVDD1" },
{ "OUT1R", NULL, "CPVDD1" },
{ "OUT4L", NULL, "SPKVDD" },
{ "OUT1L", NULL, "SYSCLK" },
{ "OUT1R", NULL, "SYSCLK" },
{ "OUT4L", NULL, "SYSCLK" },
{ "OUT5L", NULL, "SYSCLK" },
{ "OUT5R", NULL, "SYSCLK" },
{ "SPD1", NULL, "SYSCLK" },
{ "SPD1", NULL, "SPD1TX1" },
{ "SPD1", NULL, "SPD1TX2" },
{ "IN1L", NULL, "SYSCLK" },
{ "IN1R", NULL, "SYSCLK" },
{ "IN2L", NULL, "SYSCLK" },
{ "IN2R", NULL, "SYSCLK" },
{ "MICBIAS1", NULL, "MICVDD" },
{ "MICBIAS1A", NULL, "MICBIAS1" },
{ "MICBIAS1B", NULL, "MICBIAS1" },
{ "MICBIAS1C", NULL, "MICBIAS1" },
{ "Noise Generator", NULL, "SYSCLK" },
{ "Tone Generator 1", NULL, "SYSCLK" },
{ "Tone Generator 2", NULL, "SYSCLK" },
{ "Noise Generator", NULL, "NOISE" },
{ "Tone Generator 1", NULL, "TONE" },
{ "Tone Generator 2", NULL, "TONE" },
{ "AIF1 Capture", NULL, "AIF1TX1" },
{ "AIF1 Capture", NULL, "AIF1TX2" },
{ "AIF1 Capture", NULL, "AIF1TX3" },
{ "AIF1 Capture", NULL, "AIF1TX4" },
{ "AIF1 Capture", NULL, "AIF1TX5" },
{ "AIF1 Capture", NULL, "AIF1TX6" },
{ "AIF1RX1", NULL, "AIF1 Playback" },
{ "AIF1RX2", NULL, "AIF1 Playback" },
{ "AIF1RX3", NULL, "AIF1 Playback" },
{ "AIF1RX4", NULL, "AIF1 Playback" },
{ "AIF1RX5", NULL, "AIF1 Playback" },
{ "AIF1RX6", NULL, "AIF1 Playback" },
{ "AIF2 Capture", NULL, "AIF2TX1" },
{ "AIF2 Capture", NULL, "AIF2TX2" },
{ "AIF2 Capture", NULL, "AIF2TX3" },
{ "AIF2 Capture", NULL, "AIF2TX4" },
{ "AIF2RX1", NULL, "AIF2 Playback" },
{ "AIF2RX2", NULL, "AIF2 Playback" },
{ "AIF2RX3", NULL, "AIF2 Playback" },
{ "AIF2RX4", NULL, "AIF2 Playback" },
{ "AIF3 Capture", NULL, "AIF3TX1" },
{ "AIF3 Capture", NULL, "AIF3TX2" },
{ "AIF3RX1", NULL, "AIF3 Playback" },
{ "AIF3RX2", NULL, "AIF3 Playback" },
{ "AIF1 Playback", NULL, "SYSCLK" },
{ "AIF2 Playback", NULL, "SYSCLK" },
{ "AIF3 Playback", NULL, "SYSCLK" },
{ "AIF1 Capture", NULL, "SYSCLK" },
{ "AIF2 Capture", NULL, "SYSCLK" },
{ "AIF3 Capture", NULL, "SYSCLK" },
{ "Audio Trace DSP", NULL, "DSP1" },
{ "IN1L Analog Mux", "A", "IN1ALN" },
{ "IN1L Analog Mux", "A", "IN1ALP" },
{ "IN1L Analog Mux", "B", "IN1BLN" },
{ "IN1L Analog Mux", "B", "IN1BLP" },
{ "IN1R Analog Mux", "A", "IN1ARN" },
{ "IN1R Analog Mux", "A", "IN1ARP" },
{ "IN1R Analog Mux", "B", "IN1BRN" },
{ "IN1R Analog Mux", "B", "IN1BRP" },
{ "IN1L Mode", "Analog", "IN1L Analog Mux" },
{ "IN1R Mode", "Analog", "IN1R Analog Mux" },
{ "IN1L Mode", "Digital", "IN1ALN" },
{ "IN1L Mode", "Digital", "IN1ALP" },
{ "IN1R Mode", "Digital", "IN1ALN" },
{ "IN1R Mode", "Digital", "IN1ALP" },
{ "IN1L", NULL, "IN1L Mode" },
{ "IN1R", NULL, "IN1R Mode" },
{ "IN2L Mode", "Analog", "IN2N" },
{ "IN2L Mode", "Analog", "IN2P" },
{ "IN2L Mode", "Digital", "SPKRXDAT" },
{ "IN2R Mode", "Digital", "SPKRXDAT" },
{ "IN2L", NULL, "IN2L Mode" },
{ "IN2R", NULL, "IN2R Mode" },
MADERA_MIXER_ROUTES("OUT1L", "HPOUT1L"),
MADERA_MIXER_ROUTES("OUT1R", "HPOUT1R"),
MADERA_MIXER_ROUTES("OUT4L", "SPKOUTL"),
MADERA_MIXER_ROUTES("OUT5L", "SPKDAT1L"),
MADERA_MIXER_ROUTES("OUT5R", "SPKDAT1R"),
MADERA_MIXER_ROUTES("PWM1 Driver", "PWM1"),
MADERA_MIXER_ROUTES("PWM2 Driver", "PWM2"),
MADERA_MIXER_ROUTES("AIF1TX1", "AIF1TX1"),
MADERA_MIXER_ROUTES("AIF1TX2", "AIF1TX2"),
MADERA_MIXER_ROUTES("AIF1TX3", "AIF1TX3"),
MADERA_MIXER_ROUTES("AIF1TX4", "AIF1TX4"),
MADERA_MIXER_ROUTES("AIF1TX5", "AIF1TX5"),
MADERA_MIXER_ROUTES("AIF1TX6", "AIF1TX6"),
MADERA_MIXER_ROUTES("AIF2TX1", "AIF2TX1"),
MADERA_MIXER_ROUTES("AIF2TX2", "AIF2TX2"),
MADERA_MIXER_ROUTES("AIF2TX3", "AIF2TX3"),
MADERA_MIXER_ROUTES("AIF2TX4", "AIF2TX4"),
MADERA_MIXER_ROUTES("AIF3TX1", "AIF3TX1"),
MADERA_MIXER_ROUTES("AIF3TX2", "AIF3TX2"),
MADERA_MUX_ROUTES("SPD1TX1", "SPDIF1TX1"),
MADERA_MUX_ROUTES("SPD1TX2", "SPDIF1TX2"),
MADERA_MIXER_ROUTES("EQ1", "EQ1"),
MADERA_MIXER_ROUTES("EQ2", "EQ2"),
MADERA_MIXER_ROUTES("EQ3", "EQ3"),
MADERA_MIXER_ROUTES("EQ4", "EQ4"),
MADERA_MIXER_ROUTES("DRC1L", "DRC1L"),
MADERA_MIXER_ROUTES("DRC1R", "DRC1R"),
MADERA_MIXER_ROUTES("DRC2L", "DRC2L"),
MADERA_MIXER_ROUTES("DRC2R", "DRC2R"),
MADERA_MIXER_ROUTES("LHPF1", "LHPF1"),
MADERA_MIXER_ROUTES("LHPF2", "LHPF2"),
MADERA_MIXER_ROUTES("LHPF3", "LHPF3"),
MADERA_MIXER_ROUTES("LHPF4", "LHPF4"),
MADERA_DSP_ROUTES("DSP1"),
{ "DSP Trigger Out", NULL, "DSP1 Trigger Output" },
{ "DSP1 Trigger Output", "Switch", "DSP1" },
MADERA_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"),
MADERA_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"),
MADERA_MUX_ROUTES("ISRC1INT3", "ISRC1INT3"),
MADERA_MUX_ROUTES("ISRC1INT4", "ISRC1INT4"),
MADERA_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"),
MADERA_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"),
MADERA_MUX_ROUTES("ISRC1DEC3", "ISRC1DEC3"),
MADERA_MUX_ROUTES("ISRC1DEC4", "ISRC1DEC4"),
MADERA_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"),
MADERA_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"),
MADERA_MUX_ROUTES("ISRC2INT3", "ISRC2INT3"),
MADERA_MUX_ROUTES("ISRC2INT4", "ISRC2INT4"),
MADERA_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"),
MADERA_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"),
MADERA_MUX_ROUTES("ISRC2DEC3", "ISRC2DEC3"),
MADERA_MUX_ROUTES("ISRC2DEC4", "ISRC2DEC4"),
{ "AEC1 Loopback", "HPOUT1L", "OUT1L" },
{ "AEC1 Loopback", "HPOUT1R", "OUT1R" },
{ "AEC2 Loopback", "HPOUT1L", "OUT1L" },
{ "AEC2 Loopback", "HPOUT1R", "OUT1R" },
{ "HPOUT1 Demux", NULL, "OUT1L" },
{ "HPOUT1 Demux", NULL, "OUT1R" },
{ "OUT1R", NULL, "HPOUT1 Mono Mux" },
{ "HPOUT1 Mono Mux", "EPOUT", "OUT1L" },
{ "HPOUTL", "HPOUT", "HPOUT1 Demux" },
{ "HPOUTR", "HPOUT", "HPOUT1 Demux" },
{ "EPOUTP", "EPOUT", "HPOUT1 Demux" },
{ "EPOUTN", "EPOUT", "HPOUT1 Demux" },
{ "AEC1 Loopback", "SPKOUTL", "OUT4L" },
{ "AEC2 Loopback", "SPKOUTL", "OUT4L" },
{ "SPKOUTN", NULL, "OUT4L" },
{ "SPKOUTP", NULL, "OUT4L" },
{ "AEC1 Loopback", "SPKDAT1L", "OUT5L" },
{ "AEC1 Loopback", "SPKDAT1R", "OUT5R" },
{ "AEC2 Loopback", "SPKDAT1L", "OUT5L" },
{ "AEC2 Loopback", "SPKDAT1R", "OUT5R" },
{ "SPKDAT1L", NULL, "OUT5L" },
{ "SPKDAT1R", NULL, "OUT5R" },
{ "SPDIF1", NULL, "SPD1" },
{ "MICSUPP", NULL, "SYSCLK" },
{ "DRC1 Signal Activity", NULL, "DRC1 Activity Output" },
{ "DRC2 Signal Activity", NULL, "DRC2 Activity Output" },
{ "DRC1 Activity Output", "Switch", "DRC1L" },
{ "DRC1 Activity Output", "Switch", "DRC1R" },
{ "DRC2 Activity Output", "Switch", "DRC2L" },
{ "DRC2 Activity Output", "Switch", "DRC2R" },
};
static int cs47l15_set_fll(struct snd_soc_component *component, int fll_id,
int source, unsigned int fref, unsigned int fout)
{
struct cs47l15 *cs47l15 = snd_soc_component_get_drvdata(component);
switch (fll_id) {
case MADERA_FLL1_REFCLK:
return madera_set_fll_refclk(&cs47l15->fll[0], source, fref,
fout);
case MADERA_FLLAO_REFCLK:
return madera_set_fll_ao_refclk(&cs47l15->fll[1], source, fref,
fout);
case MADERA_FLL1_SYNCCLK:
return madera_set_fll_syncclk(&cs47l15->fll[0], source, fref,
fout);
default:
return -EINVAL;
}
}
static const struct snd_soc_dai_ops cs47l15_dai_ops = {
.compress_new = snd_soc_new_compress,
};
static struct snd_soc_dai_driver cs47l15_dai[] = {
{
.name = "cs47l15-aif1",
.id = 1,
.base = MADERA_AIF1_BCLK_CTRL,
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 6,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 1,
.channels_max = 6,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &madera_dai_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
{
.name = "cs47l15-aif2",
.id = 2,
.base = MADERA_AIF2_BCLK_CTRL,
.playback = {
.stream_name = "AIF2 Playback",
.channels_min = 1,
.channels_max = 4,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.capture = {
.stream_name = "AIF2 Capture",
.channels_min = 1,
.channels_max = 4,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &madera_dai_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
{
.name = "cs47l15-aif3",
.id = 3,
.base = MADERA_AIF3_BCLK_CTRL,
.playback = {
.stream_name = "AIF3 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.capture = {
.stream_name = "AIF3 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &madera_dai_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
{
.name = "cs47l15-cpu-trace",
.capture = {
.stream_name = "Audio Trace CPU",
.channels_min = 1,
.channels_max = 6,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &cs47l15_dai_ops,
},
{
.name = "cs47l15-dsp-trace",
.capture = {
.stream_name = "Audio Trace DSP",
.channels_min = 1,
.channels_max = 6,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
},
};
static int cs47l15_open(struct snd_soc_component *component,
struct snd_compr_stream *stream)
{
struct snd_soc_pcm_runtime *rtd = stream->private_data;
struct cs47l15 *cs47l15 = snd_soc_component_get_drvdata(component);
struct madera_priv *priv = &cs47l15->core;
struct madera *madera = priv->madera;
int n_adsp;
if (strcmp(asoc_rtd_to_codec(rtd, 0)->name, "cs47l15-dsp-trace") == 0) {
n_adsp = 0;
} else {
dev_err(madera->dev,
"No suitable compressed stream for DAI '%s'\n",
asoc_rtd_to_codec(rtd, 0)->name);
return -EINVAL;
}
return wm_adsp_compr_open(&priv->adsp[n_adsp], stream);
}
static irqreturn_t cs47l15_adsp2_irq(int irq, void *data)
{
struct cs47l15 *cs47l15 = data;
struct madera_priv *priv = &cs47l15->core;
struct madera *madera = priv->madera;
int ret;
ret = wm_adsp_compr_handle_irq(&priv->adsp[0]);
if (ret == -ENODEV) {
dev_err(madera->dev, "Spurious compressed data IRQ\n");
return IRQ_NONE;
}
return IRQ_HANDLED;
}
static const struct snd_soc_dapm_route cs47l15_mono_routes[] = {
{ "HPOUT1 Mono Mux", "HPOUT", "OUT1L" },
};
static int cs47l15_component_probe(struct snd_soc_component *component)
{
struct cs47l15 *cs47l15 = snd_soc_component_get_drvdata(component);
struct madera *madera = cs47l15->core.madera;
int ret;
snd_soc_component_init_regmap(component, madera->regmap);
mutex_lock(&madera->dapm_ptr_lock);
madera->dapm = snd_soc_component_get_dapm(component);
mutex_unlock(&madera->dapm_ptr_lock);
ret = madera_init_inputs(component);
if (ret)
return ret;
ret = madera_init_outputs(component, cs47l15_mono_routes,
ARRAY_SIZE(cs47l15_mono_routes),
CS47L15_MONO_OUTPUTS);
if (ret)
return ret;
snd_soc_component_disable_pin(component, "HAPTICS");
ret = snd_soc_add_component_controls(component,
madera_adsp_rate_controls,
CS47L15_NUM_ADSP);
if (ret)
return ret;
wm_adsp2_component_probe(&cs47l15->core.adsp[0], component);
return 0;
}
static void cs47l15_component_remove(struct snd_soc_component *component)
{
struct cs47l15 *cs47l15 = snd_soc_component_get_drvdata(component);
struct madera *madera = cs47l15->core.madera;
mutex_lock(&madera->dapm_ptr_lock);
madera->dapm = NULL;
mutex_unlock(&madera->dapm_ptr_lock);
wm_adsp2_component_remove(&cs47l15->core.adsp[0], component);
}
#define CS47L15_DIG_VU 0x0200
static unsigned int cs47l15_digital_vu[] = {
MADERA_DAC_DIGITAL_VOLUME_1L,
MADERA_DAC_DIGITAL_VOLUME_1R,
MADERA_DAC_DIGITAL_VOLUME_4L,
MADERA_DAC_DIGITAL_VOLUME_5L,
MADERA_DAC_DIGITAL_VOLUME_5R,
};
static const struct snd_compress_ops cs47l15_compress_ops = {
.open = &cs47l15_open,
.free = &wm_adsp_compr_free,
.set_params = &wm_adsp_compr_set_params,
.get_caps = &wm_adsp_compr_get_caps,
.trigger = &wm_adsp_compr_trigger,
.pointer = &wm_adsp_compr_pointer,
.copy = &wm_adsp_compr_copy,
};
static const struct snd_soc_component_driver soc_component_dev_cs47l15 = {
.probe = &cs47l15_component_probe,
.remove = &cs47l15_component_remove,
.set_sysclk = &madera_set_sysclk,
.set_pll = &cs47l15_set_fll,
.name = DRV_NAME,
.compress_ops = &cs47l15_compress_ops,
.controls = cs47l15_snd_controls,
.num_controls = ARRAY_SIZE(cs47l15_snd_controls),
.dapm_widgets = cs47l15_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(cs47l15_dapm_widgets),
.dapm_routes = cs47l15_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(cs47l15_dapm_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
static int cs47l15_probe(struct platform_device *pdev)
{
struct madera *madera = dev_get_drvdata(pdev->dev.parent);
struct cs47l15 *cs47l15;
int i, ret;
BUILD_BUG_ON(ARRAY_SIZE(cs47l15_dai) > MADERA_MAX_DAI);
/* quick exit if Madera irqchip driver hasn't completed probe */
if (!madera->irq_dev) {
dev_dbg(&pdev->dev, "irqchip driver not ready\n");
return -EPROBE_DEFER;
}
cs47l15 = devm_kzalloc(&pdev->dev, sizeof(struct cs47l15),
GFP_KERNEL);
if (!cs47l15)
return -ENOMEM;
platform_set_drvdata(pdev, cs47l15);
cs47l15->core.madera = madera;
cs47l15->core.dev = &pdev->dev;
cs47l15->core.num_inputs = 4;
ret = madera_core_init(&cs47l15->core);
if (ret)
return ret;
ret = madera_init_overheat(&cs47l15->core);
if (ret)
goto error_core;
ret = madera_request_irq(madera, MADERA_IRQ_DSP_IRQ1,
"ADSP2 Compressed IRQ", cs47l15_adsp2_irq,
cs47l15);
if (ret != 0) {
dev_err(&pdev->dev, "Failed to request DSP IRQ: %d\n", ret);
goto error_overheat;
}
ret = madera_set_irq_wake(madera, MADERA_IRQ_DSP_IRQ1, 1);
if (ret)
dev_warn(&pdev->dev, "Failed to set DSP IRQ wake: %d\n", ret);
cs47l15->core.adsp[0].part = "cs47l15";
cs47l15->core.adsp[0].cs_dsp.num = 1;
cs47l15->core.adsp[0].cs_dsp.type = WMFW_ADSP2;
cs47l15->core.adsp[0].cs_dsp.rev = 2;
cs47l15->core.adsp[0].cs_dsp.dev = madera->dev;
cs47l15->core.adsp[0].cs_dsp.regmap = madera->regmap_32bit;
cs47l15->core.adsp[0].cs_dsp.base = MADERA_DSP1_CONFIG_1;
cs47l15->core.adsp[0].cs_dsp.mem = cs47l15_dsp1_regions;
cs47l15->core.adsp[0].cs_dsp.num_mems = ARRAY_SIZE(cs47l15_dsp1_regions);
cs47l15->core.adsp[0].cs_dsp.lock_regions =
CS_ADSP2_REGION_1 | CS_ADSP2_REGION_2 | CS_ADSP2_REGION_3;
ret = wm_adsp2_init(&cs47l15->core.adsp[0]);
if (ret != 0)
goto error_dsp_irq;
ret = madera_init_bus_error_irq(&cs47l15->core, 0, wm_adsp2_bus_error);
if (ret)
goto error_adsp;
madera_init_fll(madera, 1, MADERA_FLL1_CONTROL_1 - 1,
&cs47l15->fll[0]);
madera_init_fll(madera, 4, MADERA_FLLAO_CONTROL_1 - 1,
&cs47l15->fll[1]);
for (i = 0; i < ARRAY_SIZE(cs47l15_dai); i++)
madera_init_dai(&cs47l15->core, i);
/* Latch volume update bits */
for (i = 0; i < ARRAY_SIZE(cs47l15_digital_vu); i++)
regmap_update_bits(madera->regmap, cs47l15_digital_vu[i],
CS47L15_DIG_VU, CS47L15_DIG_VU);
pm_runtime_enable(&pdev->dev);
pm_runtime_idle(&pdev->dev);
ret = devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_cs47l15,
cs47l15_dai,
ARRAY_SIZE(cs47l15_dai));
if (ret < 0) {
dev_err(&pdev->dev, "Failed to register component: %d\n", ret);
goto error_pm_runtime;
}
return ret;
error_pm_runtime:
pm_runtime_disable(&pdev->dev);
madera_free_bus_error_irq(&cs47l15->core, 0);
error_adsp:
wm_adsp2_remove(&cs47l15->core.adsp[0]);
error_dsp_irq:
madera_set_irq_wake(madera, MADERA_IRQ_DSP_IRQ1, 0);
madera_free_irq(madera, MADERA_IRQ_DSP_IRQ1, cs47l15);
error_overheat:
madera_free_overheat(&cs47l15->core);
error_core:
madera_core_free(&cs47l15->core);
return ret;
}
static void cs47l15_remove(struct platform_device *pdev)
{
struct cs47l15 *cs47l15 = platform_get_drvdata(pdev);
pm_runtime_disable(&pdev->dev);
madera_free_bus_error_irq(&cs47l15->core, 0);
wm_adsp2_remove(&cs47l15->core.adsp[0]);
madera_set_irq_wake(cs47l15->core.madera, MADERA_IRQ_DSP_IRQ1, 0);
madera_free_irq(cs47l15->core.madera, MADERA_IRQ_DSP_IRQ1, cs47l15);
madera_free_overheat(&cs47l15->core);
madera_core_free(&cs47l15->core);
}
static struct platform_driver cs47l15_codec_driver = {
.driver = {
.name = "cs47l15-codec",
},
.probe = &cs47l15_probe,
.remove_new = cs47l15_remove,
};
module_platform_driver(cs47l15_codec_driver);
MODULE_SOFTDEP("pre: madera irq-madera arizona-micsupp");
MODULE_DESCRIPTION("ASoC CS47L15 driver");
MODULE_AUTHOR("Richard Fitzgerald <[email protected]>");
MODULE_AUTHOR("Jaswinder Jassal <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:cs47l15-codec");
| linux-master | sound/soc/codecs/cs47l15.c |
// SPDX-License-Identifier: GPL-2.0-only
// Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
#include <linux/module.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/of_clk.h>
#include <linux/clk-provider.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <linux/pm_runtime.h>
#include <linux/of_platform.h>
#include <sound/tlv.h>
#include "lpass-macro-common.h"
#include "lpass-wsa-macro.h"
#define CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL (0x0000)
#define CDC_WSA_MCLK_EN_MASK BIT(0)
#define CDC_WSA_MCLK_ENABLE BIT(0)
#define CDC_WSA_MCLK_DISABLE 0
#define CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL (0x0004)
#define CDC_WSA_FS_CNT_EN_MASK BIT(0)
#define CDC_WSA_FS_CNT_ENABLE BIT(0)
#define CDC_WSA_FS_CNT_DISABLE 0
#define CDC_WSA_CLK_RST_CTRL_SWR_CONTROL (0x0008)
#define CDC_WSA_SWR_CLK_EN_MASK BIT(0)
#define CDC_WSA_SWR_CLK_ENABLE BIT(0)
#define CDC_WSA_SWR_RST_EN_MASK BIT(1)
#define CDC_WSA_SWR_RST_ENABLE BIT(1)
#define CDC_WSA_SWR_RST_DISABLE 0
#define CDC_WSA_TOP_TOP_CFG0 (0x0080)
#define CDC_WSA_TOP_TOP_CFG1 (0x0084)
#define CDC_WSA_TOP_FREQ_MCLK (0x0088)
#define CDC_WSA_TOP_DEBUG_BUS_SEL (0x008C)
#define CDC_WSA_TOP_DEBUG_EN0 (0x0090)
#define CDC_WSA_TOP_DEBUG_EN1 (0x0094)
#define CDC_WSA_TOP_DEBUG_DSM_LB (0x0098)
#define CDC_WSA_TOP_RX_I2S_CTL (0x009C)
#define CDC_WSA_TOP_TX_I2S_CTL (0x00A0)
#define CDC_WSA_TOP_I2S_CLK (0x00A4)
#define CDC_WSA_TOP_I2S_RESET (0x00A8)
#define CDC_WSA_RX_INP_MUX_RX_INT0_CFG0 (0x0100)
#define CDC_WSA_RX_INTX_1_MIX_INP0_SEL_MASK GENMASK(2, 0)
#define CDC_WSA_RX_INTX_1_MIX_INP1_SEL_MASK GENMASK(5, 3)
#define CDC_WSA_RX_INP_MUX_RX_INT0_CFG1 (0x0104)
#define CDC_WSA_RX_INTX_2_SEL_MASK GENMASK(2, 0)
#define CDC_WSA_RX_INTX_1_MIX_INP2_SEL_MASK GENMASK(5, 3)
#define CDC_WSA_RX_INP_MUX_RX_INT1_CFG0 (0x0108)
#define CDC_WSA_RX_INP_MUX_RX_INT1_CFG1 (0x010C)
#define CDC_WSA_RX_INP_MUX_RX_MIX_CFG0 (0x0110)
#define CDC_WSA_RX_MIX_TX1_SEL_MASK GENMASK(5, 3)
#define CDC_WSA_RX_MIX_TX1_SEL_SHFT 3
#define CDC_WSA_RX_MIX_TX0_SEL_MASK GENMASK(2, 0)
#define CDC_WSA_RX_INP_MUX_RX_EC_CFG0 (0x0114)
#define CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0 (0x0118)
#define CDC_WSA_TX0_SPKR_PROT_PATH_CTL (0x0244)
#define CDC_WSA_TX_SPKR_PROT_RESET_MASK BIT(5)
#define CDC_WSA_TX_SPKR_PROT_RESET BIT(5)
#define CDC_WSA_TX_SPKR_PROT_NO_RESET 0
#define CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK BIT(4)
#define CDC_WSA_TX_SPKR_PROT_CLK_ENABLE BIT(4)
#define CDC_WSA_TX_SPKR_PROT_CLK_DISABLE 0
#define CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK GENMASK(3, 0)
#define CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K 0
#define CDC_WSA_TX0_SPKR_PROT_PATH_CFG0 (0x0248)
#define CDC_WSA_TX1_SPKR_PROT_PATH_CTL (0x0264)
#define CDC_WSA_TX1_SPKR_PROT_PATH_CFG0 (0x0268)
#define CDC_WSA_TX2_SPKR_PROT_PATH_CTL (0x0284)
#define CDC_WSA_TX2_SPKR_PROT_PATH_CFG0 (0x0288)
#define CDC_WSA_TX3_SPKR_PROT_PATH_CTL (0x02A4)
#define CDC_WSA_TX3_SPKR_PROT_PATH_CFG0 (0x02A8)
#define CDC_WSA_INTR_CTRL_CFG (0x0340)
#define CDC_WSA_INTR_CTRL_CLR_COMMIT (0x0344)
#define CDC_WSA_INTR_CTRL_PIN1_MASK0 (0x0360)
#define CDC_WSA_INTR_CTRL_PIN1_STATUS0 (0x0368)
#define CDC_WSA_INTR_CTRL_PIN1_CLEAR0 (0x0370)
#define CDC_WSA_INTR_CTRL_PIN2_MASK0 (0x0380)
#define CDC_WSA_INTR_CTRL_PIN2_STATUS0 (0x0388)
#define CDC_WSA_INTR_CTRL_PIN2_CLEAR0 (0x0390)
#define CDC_WSA_INTR_CTRL_LEVEL0 (0x03C0)
#define CDC_WSA_INTR_CTRL_BYPASS0 (0x03C8)
#define CDC_WSA_INTR_CTRL_SET0 (0x03D0)
#define CDC_WSA_RX0_RX_PATH_CTL (0x0400)
#define CDC_WSA_RX_PATH_CLK_EN_MASK BIT(5)
#define CDC_WSA_RX_PATH_CLK_ENABLE BIT(5)
#define CDC_WSA_RX_PATH_CLK_DISABLE 0
#define CDC_WSA_RX_PATH_PGA_MUTE_EN_MASK BIT(4)
#define CDC_WSA_RX_PATH_PGA_MUTE_ENABLE BIT(4)
#define CDC_WSA_RX_PATH_PGA_MUTE_DISABLE 0
#define CDC_WSA_RX0_RX_PATH_CFG0 (0x0404)
#define CDC_WSA_RX_PATH_COMP_EN_MASK BIT(1)
#define CDC_WSA_RX_PATH_COMP_ENABLE BIT(1)
#define CDC_WSA_RX_PATH_HD2_EN_MASK BIT(2)
#define CDC_WSA_RX_PATH_HD2_ENABLE BIT(2)
#define CDC_WSA_RX_PATH_SPKR_RATE_MASK BIT(3)
#define CDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072 BIT(3)
#define CDC_WSA_RX0_RX_PATH_CFG1 (0x0408)
#define CDC_WSA_RX_PATH_SMART_BST_EN_MASK BIT(0)
#define CDC_WSA_RX_PATH_SMART_BST_ENABLE BIT(0)
#define CDC_WSA_RX_PATH_SMART_BST_DISABLE 0
#define CDC_WSA_RX0_RX_PATH_CFG2 (0x040C)
#define CDC_WSA_RX0_RX_PATH_CFG3 (0x0410)
#define CDC_WSA_RX_DC_DCOEFF_MASK GENMASK(1, 0)
#define CDC_WSA_RX0_RX_VOL_CTL (0x0414)
#define CDC_WSA_RX0_RX_PATH_MIX_CTL (0x0418)
#define CDC_WSA_RX_PATH_MIX_CLK_EN_MASK BIT(5)
#define CDC_WSA_RX_PATH_MIX_CLK_ENABLE BIT(5)
#define CDC_WSA_RX_PATH_MIX_CLK_DISABLE 0
#define CDC_WSA_RX0_RX_PATH_MIX_CFG (0x041C)
#define CDC_WSA_RX0_RX_VOL_MIX_CTL (0x0420)
#define CDC_WSA_RX0_RX_PATH_SEC0 (0x0424)
#define CDC_WSA_RX0_RX_PATH_SEC1 (0x0428)
#define CDC_WSA_RX_PGA_HALF_DB_MASK BIT(0)
#define CDC_WSA_RX_PGA_HALF_DB_ENABLE BIT(0)
#define CDC_WSA_RX_PGA_HALF_DB_DISABLE 0
#define CDC_WSA_RX0_RX_PATH_SEC2 (0x042C)
#define CDC_WSA_RX0_RX_PATH_SEC3 (0x0430)
#define CDC_WSA_RX_PATH_HD2_SCALE_MASK GENMASK(1, 0)
#define CDC_WSA_RX_PATH_HD2_ALPHA_MASK GENMASK(5, 2)
#define CDC_WSA_RX0_RX_PATH_SEC5 (0x0438)
#define CDC_WSA_RX0_RX_PATH_SEC6 (0x043C)
#define CDC_WSA_RX0_RX_PATH_SEC7 (0x0440)
#define CDC_WSA_RX0_RX_PATH_MIX_SEC0 (0x0444)
#define CDC_WSA_RX0_RX_PATH_MIX_SEC1 (0x0448)
#define CDC_WSA_RX0_RX_PATH_DSMDEM_CTL (0x044C)
#define CDC_WSA_RX_DSMDEM_CLK_EN_MASK BIT(0)
#define CDC_WSA_RX_DSMDEM_CLK_ENABLE BIT(0)
#define CDC_WSA_RX1_RX_PATH_CTL (0x0480)
#define CDC_WSA_RX1_RX_PATH_CFG0 (0x0484)
#define CDC_WSA_RX1_RX_PATH_CFG1 (0x0488)
#define CDC_WSA_RX1_RX_PATH_CFG2 (0x048C)
#define CDC_WSA_RX1_RX_PATH_CFG3 (0x0490)
#define CDC_WSA_RX1_RX_VOL_CTL (0x0494)
#define CDC_WSA_RX1_RX_PATH_MIX_CTL (0x0498)
#define CDC_WSA_RX1_RX_PATH_MIX_CFG (0x049C)
#define CDC_WSA_RX1_RX_VOL_MIX_CTL (0x04A0)
#define CDC_WSA_RX1_RX_PATH_SEC0 (0x04A4)
#define CDC_WSA_RX1_RX_PATH_SEC1 (0x04A8)
#define CDC_WSA_RX1_RX_PATH_SEC2 (0x04AC)
#define CDC_WSA_RX1_RX_PATH_SEC3 (0x04B0)
#define CDC_WSA_RX1_RX_PATH_SEC5 (0x04B8)
#define CDC_WSA_RX1_RX_PATH_SEC6 (0x04BC)
#define CDC_WSA_RX1_RX_PATH_SEC7 (0x04C0)
#define CDC_WSA_RX1_RX_PATH_MIX_SEC0 (0x04C4)
#define CDC_WSA_RX1_RX_PATH_MIX_SEC1 (0x04C8)
#define CDC_WSA_RX1_RX_PATH_DSMDEM_CTL (0x04CC)
#define CDC_WSA_BOOST0_BOOST_PATH_CTL (0x0500)
#define CDC_WSA_BOOST_PATH_CLK_EN_MASK BIT(4)
#define CDC_WSA_BOOST_PATH_CLK_ENABLE BIT(4)
#define CDC_WSA_BOOST_PATH_CLK_DISABLE 0
#define CDC_WSA_BOOST0_BOOST_CTL (0x0504)
#define CDC_WSA_BOOST0_BOOST_CFG1 (0x0508)
#define CDC_WSA_BOOST0_BOOST_CFG2 (0x050C)
#define CDC_WSA_BOOST1_BOOST_PATH_CTL (0x0540)
#define CDC_WSA_BOOST1_BOOST_CTL (0x0544)
#define CDC_WSA_BOOST1_BOOST_CFG1 (0x0548)
#define CDC_WSA_BOOST1_BOOST_CFG2 (0x054C)
#define CDC_WSA_COMPANDER0_CTL0 (0x0580)
#define CDC_WSA_COMPANDER_CLK_EN_MASK BIT(0)
#define CDC_WSA_COMPANDER_CLK_ENABLE BIT(0)
#define CDC_WSA_COMPANDER_SOFT_RST_MASK BIT(1)
#define CDC_WSA_COMPANDER_SOFT_RST_ENABLE BIT(1)
#define CDC_WSA_COMPANDER_HALT_MASK BIT(2)
#define CDC_WSA_COMPANDER_HALT BIT(2)
#define CDC_WSA_COMPANDER0_CTL1 (0x0584)
#define CDC_WSA_COMPANDER0_CTL2 (0x0588)
#define CDC_WSA_COMPANDER0_CTL3 (0x058C)
#define CDC_WSA_COMPANDER0_CTL4 (0x0590)
#define CDC_WSA_COMPANDER0_CTL5 (0x0594)
#define CDC_WSA_COMPANDER0_CTL6 (0x0598)
#define CDC_WSA_COMPANDER0_CTL7 (0x059C)
#define CDC_WSA_COMPANDER1_CTL0 (0x05C0)
#define CDC_WSA_COMPANDER1_CTL1 (0x05C4)
#define CDC_WSA_COMPANDER1_CTL2 (0x05C8)
#define CDC_WSA_COMPANDER1_CTL3 (0x05CC)
#define CDC_WSA_COMPANDER1_CTL4 (0x05D0)
#define CDC_WSA_COMPANDER1_CTL5 (0x05D4)
#define CDC_WSA_COMPANDER1_CTL6 (0x05D8)
#define CDC_WSA_COMPANDER1_CTL7 (0x05DC)
#define CDC_WSA_SOFTCLIP0_CRC (0x0600)
#define CDC_WSA_SOFTCLIP_CLK_EN_MASK BIT(0)
#define CDC_WSA_SOFTCLIP_CLK_ENABLE BIT(0)
#define CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL (0x0604)
#define CDC_WSA_SOFTCLIP_EN_MASK BIT(0)
#define CDC_WSA_SOFTCLIP_ENABLE BIT(0)
#define CDC_WSA_SOFTCLIP1_CRC (0x0640)
#define CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL (0x0644)
#define CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL (0x0680)
#define CDC_WSA_EC_HQ_EC_CLK_EN_MASK BIT(0)
#define CDC_WSA_EC_HQ_EC_CLK_ENABLE BIT(0)
#define CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0 (0x0684)
#define CDC_WSA_EC_HQ_EC_REF_PCM_RATE_MASK GENMASK(4, 1)
#define CDC_WSA_EC_HQ_EC_REF_PCM_RATE_48K BIT(3)
#define CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL (0x06C0)
#define CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0 (0x06C4)
#define CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL (0x0700)
#define CDC_WSA_SPLINE_ASRC0_CTL0 (0x0704)
#define CDC_WSA_SPLINE_ASRC0_CTL1 (0x0708)
#define CDC_WSA_SPLINE_ASRC0_FIFO_CTL (0x070C)
#define CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB (0x0710)
#define CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB (0x0714)
#define CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB (0x0718)
#define CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB (0x071C)
#define CDC_WSA_SPLINE_ASRC0_STATUS_FIFO (0x0720)
#define CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL (0x0740)
#define CDC_WSA_SPLINE_ASRC1_CTL0 (0x0744)
#define CDC_WSA_SPLINE_ASRC1_CTL1 (0x0748)
#define CDC_WSA_SPLINE_ASRC1_FIFO_CTL (0x074C)
#define CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB (0x0750)
#define CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB (0x0754)
#define CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB (0x0758)
#define CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB (0x075C)
#define CDC_WSA_SPLINE_ASRC1_STATUS_FIFO (0x0760)
#define WSA_MAX_OFFSET (0x0760)
#define WSA_MACRO_RX_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
#define WSA_MACRO_RX_MIX_RATES (SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
#define WSA_MACRO_RX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
#define WSA_MACRO_ECHO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_48000)
#define WSA_MACRO_ECHO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S24_3LE)
#define NUM_INTERPOLATORS 2
#define WSA_NUM_CLKS_MAX 5
#define WSA_MACRO_MCLK_FREQ 19200000
#define WSA_MACRO_MUX_INP_MASK2 0x38
#define WSA_MACRO_MUX_CFG_OFFSET 0x8
#define WSA_MACRO_MUX_CFG1_OFFSET 0x4
#define WSA_MACRO_RX_COMP_OFFSET 0x40
#define WSA_MACRO_RX_SOFTCLIP_OFFSET 0x40
#define WSA_MACRO_RX_PATH_OFFSET 0x80
#define WSA_MACRO_RX_PATH_CFG3_OFFSET 0x10
#define WSA_MACRO_RX_PATH_DSMDEM_OFFSET 0x4C
#define WSA_MACRO_FS_RATE_MASK 0x0F
#define WSA_MACRO_EC_MIX_TX0_MASK 0x03
#define WSA_MACRO_EC_MIX_TX1_MASK 0x18
#define WSA_MACRO_MAX_DMA_CH_PER_PORT 0x2
enum {
WSA_MACRO_GAIN_OFFSET_M1P5_DB,
WSA_MACRO_GAIN_OFFSET_0_DB,
};
enum {
WSA_MACRO_RX0 = 0,
WSA_MACRO_RX1,
WSA_MACRO_RX_MIX,
WSA_MACRO_RX_MIX0 = WSA_MACRO_RX_MIX,
WSA_MACRO_RX_MIX1,
WSA_MACRO_RX_MAX,
};
enum {
WSA_MACRO_TX0 = 0,
WSA_MACRO_TX1,
WSA_MACRO_TX_MAX,
};
enum {
WSA_MACRO_EC0_MUX = 0,
WSA_MACRO_EC1_MUX,
WSA_MACRO_EC_MUX_MAX,
};
enum {
WSA_MACRO_COMP1, /* SPK_L */
WSA_MACRO_COMP2, /* SPK_R */
WSA_MACRO_COMP_MAX
};
enum {
WSA_MACRO_SOFTCLIP0, /* RX0 */
WSA_MACRO_SOFTCLIP1, /* RX1 */
WSA_MACRO_SOFTCLIP_MAX
};
enum {
INTn_1_INP_SEL_ZERO = 0,
INTn_1_INP_SEL_RX0,
INTn_1_INP_SEL_RX1,
INTn_1_INP_SEL_RX2,
INTn_1_INP_SEL_RX3,
INTn_1_INP_SEL_DEC0,
INTn_1_INP_SEL_DEC1,
};
enum {
INTn_2_INP_SEL_ZERO = 0,
INTn_2_INP_SEL_RX0,
INTn_2_INP_SEL_RX1,
INTn_2_INP_SEL_RX2,
INTn_2_INP_SEL_RX3,
};
struct interp_sample_rate {
int sample_rate;
int rate_val;
};
static struct interp_sample_rate int_prim_sample_rate_val[] = {
{8000, 0x0}, /* 8K */
{16000, 0x1}, /* 16K */
{24000, -EINVAL},/* 24K */
{32000, 0x3}, /* 32K */
{48000, 0x4}, /* 48K */
{96000, 0x5}, /* 96K */
{192000, 0x6}, /* 192K */
{384000, 0x7}, /* 384K */
{44100, 0x8}, /* 44.1K */
};
static struct interp_sample_rate int_mix_sample_rate_val[] = {
{48000, 0x4}, /* 48K */
{96000, 0x5}, /* 96K */
{192000, 0x6}, /* 192K */
};
enum {
WSA_MACRO_AIF_INVALID = 0,
WSA_MACRO_AIF1_PB,
WSA_MACRO_AIF_MIX1_PB,
WSA_MACRO_AIF_VI,
WSA_MACRO_AIF_ECHO,
WSA_MACRO_MAX_DAIS,
};
struct wsa_macro {
struct device *dev;
int comp_enabled[WSA_MACRO_COMP_MAX];
int ec_hq[WSA_MACRO_RX1 + 1];
u16 prim_int_users[WSA_MACRO_RX1 + 1];
u16 wsa_mclk_users;
unsigned long active_ch_mask[WSA_MACRO_MAX_DAIS];
unsigned long active_ch_cnt[WSA_MACRO_MAX_DAIS];
int rx_port_value[WSA_MACRO_RX_MAX];
int ear_spkr_gain;
int spkr_gain_offset;
int spkr_mode;
int is_softclip_on[WSA_MACRO_SOFTCLIP_MAX];
int softclip_clk_users[WSA_MACRO_SOFTCLIP_MAX];
struct regmap *regmap;
struct clk *mclk;
struct clk *npl;
struct clk *macro;
struct clk *dcodec;
struct clk *fsgen;
struct clk_hw hw;
};
#define to_wsa_macro(_hw) container_of(_hw, struct wsa_macro, hw)
static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
static const char *const rx_text[] = {
"ZERO", "RX0", "RX1", "RX_MIX0", "RX_MIX1", "DEC0", "DEC1"
};
static const char *const rx_mix_text[] = {
"ZERO", "RX0", "RX1", "RX_MIX0", "RX_MIX1"
};
static const char *const rx_mix_ec_text[] = {
"ZERO", "RX_MIX_TX0", "RX_MIX_TX1"
};
static const char *const rx_mux_text[] = {
"ZERO", "AIF1_PB", "AIF_MIX1_PB"
};
static const char *const rx_sidetone_mix_text[] = {
"ZERO", "SRC0"
};
static const char * const wsa_macro_ear_spkr_pa_gain_text[] = {
"G_DEFAULT", "G_0_DB", "G_1_DB", "G_2_DB", "G_3_DB",
"G_4_DB", "G_5_DB", "G_6_DB"
};
static SOC_ENUM_SINGLE_EXT_DECL(wsa_macro_ear_spkr_pa_gain_enum,
wsa_macro_ear_spkr_pa_gain_text);
/* RX INT0 */
static const struct soc_enum rx0_prim_inp0_chain_enum =
SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG0,
0, 7, rx_text);
static const struct soc_enum rx0_prim_inp1_chain_enum =
SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG0,
3, 7, rx_text);
static const struct soc_enum rx0_prim_inp2_chain_enum =
SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG1,
3, 7, rx_text);
static const struct soc_enum rx0_mix_chain_enum =
SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG1,
0, 5, rx_mix_text);
static const struct soc_enum rx0_sidetone_mix_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_sidetone_mix_text);
static const struct snd_kcontrol_new rx0_prim_inp0_mux =
SOC_DAPM_ENUM("WSA_RX0 INP0 Mux", rx0_prim_inp0_chain_enum);
static const struct snd_kcontrol_new rx0_prim_inp1_mux =
SOC_DAPM_ENUM("WSA_RX0 INP1 Mux", rx0_prim_inp1_chain_enum);
static const struct snd_kcontrol_new rx0_prim_inp2_mux =
SOC_DAPM_ENUM("WSA_RX0 INP2 Mux", rx0_prim_inp2_chain_enum);
static const struct snd_kcontrol_new rx0_mix_mux =
SOC_DAPM_ENUM("WSA_RX0 MIX Mux", rx0_mix_chain_enum);
static const struct snd_kcontrol_new rx0_sidetone_mix_mux =
SOC_DAPM_ENUM("WSA_RX0 SIDETONE MIX Mux", rx0_sidetone_mix_enum);
/* RX INT1 */
static const struct soc_enum rx1_prim_inp0_chain_enum =
SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG0,
0, 7, rx_text);
static const struct soc_enum rx1_prim_inp1_chain_enum =
SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG0,
3, 7, rx_text);
static const struct soc_enum rx1_prim_inp2_chain_enum =
SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG1,
3, 7, rx_text);
static const struct soc_enum rx1_mix_chain_enum =
SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG1,
0, 5, rx_mix_text);
static const struct snd_kcontrol_new rx1_prim_inp0_mux =
SOC_DAPM_ENUM("WSA_RX1 INP0 Mux", rx1_prim_inp0_chain_enum);
static const struct snd_kcontrol_new rx1_prim_inp1_mux =
SOC_DAPM_ENUM("WSA_RX1 INP1 Mux", rx1_prim_inp1_chain_enum);
static const struct snd_kcontrol_new rx1_prim_inp2_mux =
SOC_DAPM_ENUM("WSA_RX1 INP2 Mux", rx1_prim_inp2_chain_enum);
static const struct snd_kcontrol_new rx1_mix_mux =
SOC_DAPM_ENUM("WSA_RX1 MIX Mux", rx1_mix_chain_enum);
static const struct soc_enum rx_mix_ec0_enum =
SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_MIX_CFG0,
0, 3, rx_mix_ec_text);
static const struct soc_enum rx_mix_ec1_enum =
SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_MIX_CFG0,
3, 3, rx_mix_ec_text);
static const struct snd_kcontrol_new rx_mix_ec0_mux =
SOC_DAPM_ENUM("WSA RX_MIX EC0_Mux", rx_mix_ec0_enum);
static const struct snd_kcontrol_new rx_mix_ec1_mux =
SOC_DAPM_ENUM("WSA RX_MIX EC1_Mux", rx_mix_ec1_enum);
static const struct reg_default wsa_defaults[] = {
/* WSA Macro */
{ CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL, 0x00},
{ CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00},
{ CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 0x00},
{ CDC_WSA_TOP_TOP_CFG0, 0x00},
{ CDC_WSA_TOP_TOP_CFG1, 0x00},
{ CDC_WSA_TOP_FREQ_MCLK, 0x00},
{ CDC_WSA_TOP_DEBUG_BUS_SEL, 0x00},
{ CDC_WSA_TOP_DEBUG_EN0, 0x00},
{ CDC_WSA_TOP_DEBUG_EN1, 0x00},
{ CDC_WSA_TOP_DEBUG_DSM_LB, 0x88},
{ CDC_WSA_TOP_RX_I2S_CTL, 0x0C},
{ CDC_WSA_TOP_TX_I2S_CTL, 0x0C},
{ CDC_WSA_TOP_I2S_CLK, 0x02},
{ CDC_WSA_TOP_I2S_RESET, 0x00},
{ CDC_WSA_RX_INP_MUX_RX_INT0_CFG0, 0x00},
{ CDC_WSA_RX_INP_MUX_RX_INT0_CFG1, 0x00},
{ CDC_WSA_RX_INP_MUX_RX_INT1_CFG0, 0x00},
{ CDC_WSA_RX_INP_MUX_RX_INT1_CFG1, 0x00},
{ CDC_WSA_RX_INP_MUX_RX_MIX_CFG0, 0x00},
{ CDC_WSA_RX_INP_MUX_RX_EC_CFG0, 0x00},
{ CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0, 0x00},
{ CDC_WSA_TX0_SPKR_PROT_PATH_CTL, 0x02},
{ CDC_WSA_TX0_SPKR_PROT_PATH_CFG0, 0x00},
{ CDC_WSA_TX1_SPKR_PROT_PATH_CTL, 0x02},
{ CDC_WSA_TX1_SPKR_PROT_PATH_CFG0, 0x00},
{ CDC_WSA_TX2_SPKR_PROT_PATH_CTL, 0x02},
{ CDC_WSA_TX2_SPKR_PROT_PATH_CFG0, 0x00},
{ CDC_WSA_TX3_SPKR_PROT_PATH_CTL, 0x02},
{ CDC_WSA_TX3_SPKR_PROT_PATH_CFG0, 0x00},
{ CDC_WSA_INTR_CTRL_CFG, 0x00},
{ CDC_WSA_INTR_CTRL_CLR_COMMIT, 0x00},
{ CDC_WSA_INTR_CTRL_PIN1_MASK0, 0xFF},
{ CDC_WSA_INTR_CTRL_PIN1_STATUS0, 0x00},
{ CDC_WSA_INTR_CTRL_PIN1_CLEAR0, 0x00},
{ CDC_WSA_INTR_CTRL_PIN2_MASK0, 0xFF},
{ CDC_WSA_INTR_CTRL_PIN2_STATUS0, 0x00},
{ CDC_WSA_INTR_CTRL_PIN2_CLEAR0, 0x00},
{ CDC_WSA_INTR_CTRL_LEVEL0, 0x00},
{ CDC_WSA_INTR_CTRL_BYPASS0, 0x00},
{ CDC_WSA_INTR_CTRL_SET0, 0x00},
{ CDC_WSA_RX0_RX_PATH_CTL, 0x04},
{ CDC_WSA_RX0_RX_PATH_CFG0, 0x00},
{ CDC_WSA_RX0_RX_PATH_CFG1, 0x64},
{ CDC_WSA_RX0_RX_PATH_CFG2, 0x8F},
{ CDC_WSA_RX0_RX_PATH_CFG3, 0x00},
{ CDC_WSA_RX0_RX_VOL_CTL, 0x00},
{ CDC_WSA_RX0_RX_PATH_MIX_CTL, 0x04},
{ CDC_WSA_RX0_RX_PATH_MIX_CFG, 0x7E},
{ CDC_WSA_RX0_RX_VOL_MIX_CTL, 0x00},
{ CDC_WSA_RX0_RX_PATH_SEC0, 0x04},
{ CDC_WSA_RX0_RX_PATH_SEC1, 0x08},
{ CDC_WSA_RX0_RX_PATH_SEC2, 0x00},
{ CDC_WSA_RX0_RX_PATH_SEC3, 0x00},
{ CDC_WSA_RX0_RX_PATH_SEC5, 0x00},
{ CDC_WSA_RX0_RX_PATH_SEC6, 0x00},
{ CDC_WSA_RX0_RX_PATH_SEC7, 0x00},
{ CDC_WSA_RX0_RX_PATH_MIX_SEC0, 0x08},
{ CDC_WSA_RX0_RX_PATH_MIX_SEC1, 0x00},
{ CDC_WSA_RX0_RX_PATH_DSMDEM_CTL, 0x00},
{ CDC_WSA_RX1_RX_PATH_CFG0, 0x00},
{ CDC_WSA_RX1_RX_PATH_CFG1, 0x64},
{ CDC_WSA_RX1_RX_PATH_CFG2, 0x8F},
{ CDC_WSA_RX1_RX_PATH_CFG3, 0x00},
{ CDC_WSA_RX1_RX_VOL_CTL, 0x00},
{ CDC_WSA_RX1_RX_PATH_MIX_CTL, 0x04},
{ CDC_WSA_RX1_RX_PATH_MIX_CFG, 0x7E},
{ CDC_WSA_RX1_RX_VOL_MIX_CTL, 0x00},
{ CDC_WSA_RX1_RX_PATH_SEC0, 0x04},
{ CDC_WSA_RX1_RX_PATH_SEC1, 0x08},
{ CDC_WSA_RX1_RX_PATH_SEC2, 0x00},
{ CDC_WSA_RX1_RX_PATH_SEC3, 0x00},
{ CDC_WSA_RX1_RX_PATH_SEC5, 0x00},
{ CDC_WSA_RX1_RX_PATH_SEC6, 0x00},
{ CDC_WSA_RX1_RX_PATH_SEC7, 0x00},
{ CDC_WSA_RX1_RX_PATH_MIX_SEC0, 0x08},
{ CDC_WSA_RX1_RX_PATH_MIX_SEC1, 0x00},
{ CDC_WSA_RX1_RX_PATH_DSMDEM_CTL, 0x00},
{ CDC_WSA_BOOST0_BOOST_PATH_CTL, 0x00},
{ CDC_WSA_BOOST0_BOOST_CTL, 0xD0},
{ CDC_WSA_BOOST0_BOOST_CFG1, 0x89},
{ CDC_WSA_BOOST0_BOOST_CFG2, 0x04},
{ CDC_WSA_BOOST1_BOOST_PATH_CTL, 0x00},
{ CDC_WSA_BOOST1_BOOST_CTL, 0xD0},
{ CDC_WSA_BOOST1_BOOST_CFG1, 0x89},
{ CDC_WSA_BOOST1_BOOST_CFG2, 0x04},
{ CDC_WSA_COMPANDER0_CTL0, 0x60},
{ CDC_WSA_COMPANDER0_CTL1, 0xDB},
{ CDC_WSA_COMPANDER0_CTL2, 0xFF},
{ CDC_WSA_COMPANDER0_CTL3, 0x35},
{ CDC_WSA_COMPANDER0_CTL4, 0xFF},
{ CDC_WSA_COMPANDER0_CTL5, 0x00},
{ CDC_WSA_COMPANDER0_CTL6, 0x01},
{ CDC_WSA_COMPANDER0_CTL7, 0x28},
{ CDC_WSA_COMPANDER1_CTL0, 0x60},
{ CDC_WSA_COMPANDER1_CTL1, 0xDB},
{ CDC_WSA_COMPANDER1_CTL2, 0xFF},
{ CDC_WSA_COMPANDER1_CTL3, 0x35},
{ CDC_WSA_COMPANDER1_CTL4, 0xFF},
{ CDC_WSA_COMPANDER1_CTL5, 0x00},
{ CDC_WSA_COMPANDER1_CTL6, 0x01},
{ CDC_WSA_COMPANDER1_CTL7, 0x28},
{ CDC_WSA_SOFTCLIP0_CRC, 0x00},
{ CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL, 0x38},
{ CDC_WSA_SOFTCLIP1_CRC, 0x00},
{ CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL, 0x38},
{ CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL, 0x00},
{ CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0, 0x01},
{ CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL, 0x00},
{ CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0, 0x01},
{ CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL, 0x00},
{ CDC_WSA_SPLINE_ASRC0_CTL0, 0x00},
{ CDC_WSA_SPLINE_ASRC0_CTL1, 0x00},
{ CDC_WSA_SPLINE_ASRC0_FIFO_CTL, 0xA8},
{ CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB, 0x00},
{ CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB, 0x00},
{ CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB, 0x00},
{ CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB, 0x00},
{ CDC_WSA_SPLINE_ASRC0_STATUS_FIFO, 0x00},
{ CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL, 0x00},
{ CDC_WSA_SPLINE_ASRC1_CTL0, 0x00},
{ CDC_WSA_SPLINE_ASRC1_CTL1, 0x00},
{ CDC_WSA_SPLINE_ASRC1_FIFO_CTL, 0xA8},
{ CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB, 0x00},
{ CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB, 0x00},
{ CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB, 0x00},
{ CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB, 0x00},
{ CDC_WSA_SPLINE_ASRC1_STATUS_FIFO, 0x00},
};
static bool wsa_is_wronly_register(struct device *dev,
unsigned int reg)
{
switch (reg) {
case CDC_WSA_INTR_CTRL_CLR_COMMIT:
case CDC_WSA_INTR_CTRL_PIN1_CLEAR0:
case CDC_WSA_INTR_CTRL_PIN2_CLEAR0:
return true;
}
return false;
}
static bool wsa_is_rw_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL:
case CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL:
case CDC_WSA_CLK_RST_CTRL_SWR_CONTROL:
case CDC_WSA_TOP_TOP_CFG0:
case CDC_WSA_TOP_TOP_CFG1:
case CDC_WSA_TOP_FREQ_MCLK:
case CDC_WSA_TOP_DEBUG_BUS_SEL:
case CDC_WSA_TOP_DEBUG_EN0:
case CDC_WSA_TOP_DEBUG_EN1:
case CDC_WSA_TOP_DEBUG_DSM_LB:
case CDC_WSA_TOP_RX_I2S_CTL:
case CDC_WSA_TOP_TX_I2S_CTL:
case CDC_WSA_TOP_I2S_CLK:
case CDC_WSA_TOP_I2S_RESET:
case CDC_WSA_RX_INP_MUX_RX_INT0_CFG0:
case CDC_WSA_RX_INP_MUX_RX_INT0_CFG1:
case CDC_WSA_RX_INP_MUX_RX_INT1_CFG0:
case CDC_WSA_RX_INP_MUX_RX_INT1_CFG1:
case CDC_WSA_RX_INP_MUX_RX_MIX_CFG0:
case CDC_WSA_RX_INP_MUX_RX_EC_CFG0:
case CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0:
case CDC_WSA_TX0_SPKR_PROT_PATH_CTL:
case CDC_WSA_TX0_SPKR_PROT_PATH_CFG0:
case CDC_WSA_TX1_SPKR_PROT_PATH_CTL:
case CDC_WSA_TX1_SPKR_PROT_PATH_CFG0:
case CDC_WSA_TX2_SPKR_PROT_PATH_CTL:
case CDC_WSA_TX2_SPKR_PROT_PATH_CFG0:
case CDC_WSA_TX3_SPKR_PROT_PATH_CTL:
case CDC_WSA_TX3_SPKR_PROT_PATH_CFG0:
case CDC_WSA_INTR_CTRL_CFG:
case CDC_WSA_INTR_CTRL_PIN1_MASK0:
case CDC_WSA_INTR_CTRL_PIN2_MASK0:
case CDC_WSA_INTR_CTRL_LEVEL0:
case CDC_WSA_INTR_CTRL_BYPASS0:
case CDC_WSA_INTR_CTRL_SET0:
case CDC_WSA_RX0_RX_PATH_CTL:
case CDC_WSA_RX0_RX_PATH_CFG0:
case CDC_WSA_RX0_RX_PATH_CFG1:
case CDC_WSA_RX0_RX_PATH_CFG2:
case CDC_WSA_RX0_RX_PATH_CFG3:
case CDC_WSA_RX0_RX_VOL_CTL:
case CDC_WSA_RX0_RX_PATH_MIX_CTL:
case CDC_WSA_RX0_RX_PATH_MIX_CFG:
case CDC_WSA_RX0_RX_VOL_MIX_CTL:
case CDC_WSA_RX0_RX_PATH_SEC0:
case CDC_WSA_RX0_RX_PATH_SEC1:
case CDC_WSA_RX0_RX_PATH_SEC2:
case CDC_WSA_RX0_RX_PATH_SEC3:
case CDC_WSA_RX0_RX_PATH_SEC5:
case CDC_WSA_RX0_RX_PATH_SEC6:
case CDC_WSA_RX0_RX_PATH_SEC7:
case CDC_WSA_RX0_RX_PATH_MIX_SEC0:
case CDC_WSA_RX0_RX_PATH_MIX_SEC1:
case CDC_WSA_RX0_RX_PATH_DSMDEM_CTL:
case CDC_WSA_RX1_RX_PATH_CTL:
case CDC_WSA_RX1_RX_PATH_CFG0:
case CDC_WSA_RX1_RX_PATH_CFG1:
case CDC_WSA_RX1_RX_PATH_CFG2:
case CDC_WSA_RX1_RX_PATH_CFG3:
case CDC_WSA_RX1_RX_VOL_CTL:
case CDC_WSA_RX1_RX_PATH_MIX_CTL:
case CDC_WSA_RX1_RX_PATH_MIX_CFG:
case CDC_WSA_RX1_RX_VOL_MIX_CTL:
case CDC_WSA_RX1_RX_PATH_SEC0:
case CDC_WSA_RX1_RX_PATH_SEC1:
case CDC_WSA_RX1_RX_PATH_SEC2:
case CDC_WSA_RX1_RX_PATH_SEC3:
case CDC_WSA_RX1_RX_PATH_SEC5:
case CDC_WSA_RX1_RX_PATH_SEC6:
case CDC_WSA_RX1_RX_PATH_SEC7:
case CDC_WSA_RX1_RX_PATH_MIX_SEC0:
case CDC_WSA_RX1_RX_PATH_MIX_SEC1:
case CDC_WSA_RX1_RX_PATH_DSMDEM_CTL:
case CDC_WSA_BOOST0_BOOST_PATH_CTL:
case CDC_WSA_BOOST0_BOOST_CTL:
case CDC_WSA_BOOST0_BOOST_CFG1:
case CDC_WSA_BOOST0_BOOST_CFG2:
case CDC_WSA_BOOST1_BOOST_PATH_CTL:
case CDC_WSA_BOOST1_BOOST_CTL:
case CDC_WSA_BOOST1_BOOST_CFG1:
case CDC_WSA_BOOST1_BOOST_CFG2:
case CDC_WSA_COMPANDER0_CTL0:
case CDC_WSA_COMPANDER0_CTL1:
case CDC_WSA_COMPANDER0_CTL2:
case CDC_WSA_COMPANDER0_CTL3:
case CDC_WSA_COMPANDER0_CTL4:
case CDC_WSA_COMPANDER0_CTL5:
case CDC_WSA_COMPANDER0_CTL7:
case CDC_WSA_COMPANDER1_CTL0:
case CDC_WSA_COMPANDER1_CTL1:
case CDC_WSA_COMPANDER1_CTL2:
case CDC_WSA_COMPANDER1_CTL3:
case CDC_WSA_COMPANDER1_CTL4:
case CDC_WSA_COMPANDER1_CTL5:
case CDC_WSA_COMPANDER1_CTL7:
case CDC_WSA_SOFTCLIP0_CRC:
case CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL:
case CDC_WSA_SOFTCLIP1_CRC:
case CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL:
case CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL:
case CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0:
case CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL:
case CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0:
case CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL:
case CDC_WSA_SPLINE_ASRC0_CTL0:
case CDC_WSA_SPLINE_ASRC0_CTL1:
case CDC_WSA_SPLINE_ASRC0_FIFO_CTL:
case CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL:
case CDC_WSA_SPLINE_ASRC1_CTL0:
case CDC_WSA_SPLINE_ASRC1_CTL1:
case CDC_WSA_SPLINE_ASRC1_FIFO_CTL:
return true;
}
return false;
}
static bool wsa_is_writeable_register(struct device *dev, unsigned int reg)
{
bool ret;
ret = wsa_is_rw_register(dev, reg);
if (!ret)
return wsa_is_wronly_register(dev, reg);
return ret;
}
static bool wsa_is_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CDC_WSA_INTR_CTRL_CLR_COMMIT:
case CDC_WSA_INTR_CTRL_PIN1_CLEAR0:
case CDC_WSA_INTR_CTRL_PIN2_CLEAR0:
case CDC_WSA_INTR_CTRL_PIN1_STATUS0:
case CDC_WSA_INTR_CTRL_PIN2_STATUS0:
case CDC_WSA_COMPANDER0_CTL6:
case CDC_WSA_COMPANDER1_CTL6:
case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB:
case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB:
case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB:
case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB:
case CDC_WSA_SPLINE_ASRC0_STATUS_FIFO:
case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB:
case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB:
case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB:
case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB:
case CDC_WSA_SPLINE_ASRC1_STATUS_FIFO:
return true;
}
return wsa_is_rw_register(dev, reg);
}
static bool wsa_is_volatile_register(struct device *dev, unsigned int reg)
{
/* Update volatile list for rx/tx macros */
switch (reg) {
case CDC_WSA_INTR_CTRL_PIN1_STATUS0:
case CDC_WSA_INTR_CTRL_PIN2_STATUS0:
case CDC_WSA_COMPANDER0_CTL6:
case CDC_WSA_COMPANDER1_CTL6:
case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB:
case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB:
case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB:
case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB:
case CDC_WSA_SPLINE_ASRC0_STATUS_FIFO:
case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB:
case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB:
case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB:
case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB:
case CDC_WSA_SPLINE_ASRC1_STATUS_FIFO:
return true;
}
return false;
}
static const struct regmap_config wsa_regmap_config = {
.name = "wsa_macro",
.reg_bits = 16,
.val_bits = 32, /* 8 but with 32 bit read/write */
.reg_stride = 4,
.cache_type = REGCACHE_FLAT,
.reg_defaults = wsa_defaults,
.num_reg_defaults = ARRAY_SIZE(wsa_defaults),
.max_register = WSA_MAX_OFFSET,
.writeable_reg = wsa_is_writeable_register,
.volatile_reg = wsa_is_volatile_register,
.readable_reg = wsa_is_readable_register,
};
/**
* wsa_macro_set_spkr_mode - Configures speaker compander and smartboost
* settings based on speaker mode.
*
* @component: codec instance
* @mode: Indicates speaker configuration mode.
*
* Returns 0 on success or -EINVAL on error.
*/
int wsa_macro_set_spkr_mode(struct snd_soc_component *component, int mode)
{
struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
wsa->spkr_mode = mode;
switch (mode) {
case WSA_MACRO_SPKR_MODE_1:
snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL3, 0x80, 0x00);
snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL3, 0x80, 0x00);
snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL7, 0x01, 0x00);
snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL7, 0x01, 0x00);
snd_soc_component_update_bits(component, CDC_WSA_BOOST0_BOOST_CTL, 0x7C, 0x44);
snd_soc_component_update_bits(component, CDC_WSA_BOOST1_BOOST_CTL, 0x7C, 0x44);
break;
default:
snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL3, 0x80, 0x80);
snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL3, 0x80, 0x80);
snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL7, 0x01, 0x01);
snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL7, 0x01, 0x01);
snd_soc_component_update_bits(component, CDC_WSA_BOOST0_BOOST_CTL, 0x7C, 0x58);
snd_soc_component_update_bits(component, CDC_WSA_BOOST1_BOOST_CTL, 0x7C, 0x58);
break;
}
return 0;
}
EXPORT_SYMBOL(wsa_macro_set_spkr_mode);
static int wsa_macro_set_prim_interpolator_rate(struct snd_soc_dai *dai,
u8 int_prim_fs_rate_reg_val,
u32 sample_rate)
{
u8 int_1_mix1_inp;
u32 j, port;
u16 int_mux_cfg0, int_mux_cfg1;
u16 int_fs_reg;
u8 inp0_sel, inp1_sel, inp2_sel;
struct snd_soc_component *component = dai->component;
struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
for_each_set_bit(port, &wsa->active_ch_mask[dai->id], WSA_MACRO_RX_MAX) {
int_1_mix1_inp = port;
if ((int_1_mix1_inp < WSA_MACRO_RX0) || (int_1_mix1_inp > WSA_MACRO_RX_MIX1)) {
dev_err(component->dev, "%s: Invalid RX port, Dai ID is %d\n",
__func__, dai->id);
return -EINVAL;
}
int_mux_cfg0 = CDC_WSA_RX_INP_MUX_RX_INT0_CFG0;
/*
* Loop through all interpolator MUX inputs and find out
* to which interpolator input, the cdc_dma rx port
* is connected
*/
for (j = 0; j < NUM_INTERPOLATORS; j++) {
int_mux_cfg1 = int_mux_cfg0 + WSA_MACRO_MUX_CFG1_OFFSET;
inp0_sel = snd_soc_component_read_field(component, int_mux_cfg0,
CDC_WSA_RX_INTX_1_MIX_INP0_SEL_MASK);
inp1_sel = snd_soc_component_read_field(component, int_mux_cfg0,
CDC_WSA_RX_INTX_1_MIX_INP1_SEL_MASK);
inp2_sel = snd_soc_component_read_field(component, int_mux_cfg1,
CDC_WSA_RX_INTX_1_MIX_INP2_SEL_MASK);
if ((inp0_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) ||
(inp1_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) ||
(inp2_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0)) {
int_fs_reg = CDC_WSA_RX0_RX_PATH_CTL +
WSA_MACRO_RX_PATH_OFFSET * j;
/* sample_rate is in Hz */
snd_soc_component_update_bits(component, int_fs_reg,
WSA_MACRO_FS_RATE_MASK,
int_prim_fs_rate_reg_val);
}
int_mux_cfg0 += WSA_MACRO_MUX_CFG_OFFSET;
}
}
return 0;
}
static int wsa_macro_set_mix_interpolator_rate(struct snd_soc_dai *dai,
u8 int_mix_fs_rate_reg_val,
u32 sample_rate)
{
u8 int_2_inp;
u32 j, port;
u16 int_mux_cfg1, int_fs_reg;
u8 int_mux_cfg1_val;
struct snd_soc_component *component = dai->component;
struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
for_each_set_bit(port, &wsa->active_ch_mask[dai->id], WSA_MACRO_RX_MAX) {
int_2_inp = port;
if ((int_2_inp < WSA_MACRO_RX0) || (int_2_inp > WSA_MACRO_RX_MIX1)) {
dev_err(component->dev, "%s: Invalid RX port, Dai ID is %d\n",
__func__, dai->id);
return -EINVAL;
}
int_mux_cfg1 = CDC_WSA_RX_INP_MUX_RX_INT0_CFG1;
for (j = 0; j < NUM_INTERPOLATORS; j++) {
int_mux_cfg1_val = snd_soc_component_read_field(component, int_mux_cfg1,
CDC_WSA_RX_INTX_2_SEL_MASK);
if (int_mux_cfg1_val == int_2_inp + INTn_2_INP_SEL_RX0) {
int_fs_reg = CDC_WSA_RX0_RX_PATH_MIX_CTL +
WSA_MACRO_RX_PATH_OFFSET * j;
snd_soc_component_update_bits(component,
int_fs_reg,
WSA_MACRO_FS_RATE_MASK,
int_mix_fs_rate_reg_val);
}
int_mux_cfg1 += WSA_MACRO_MUX_CFG_OFFSET;
}
}
return 0;
}
static int wsa_macro_set_interpolator_rate(struct snd_soc_dai *dai,
u32 sample_rate)
{
int rate_val = 0;
int i, ret;
/* set mixing path rate */
for (i = 0; i < ARRAY_SIZE(int_mix_sample_rate_val); i++) {
if (sample_rate == int_mix_sample_rate_val[i].sample_rate) {
rate_val = int_mix_sample_rate_val[i].rate_val;
break;
}
}
if ((i == ARRAY_SIZE(int_mix_sample_rate_val)) || (rate_val < 0))
goto prim_rate;
ret = wsa_macro_set_mix_interpolator_rate(dai, (u8) rate_val, sample_rate);
if (ret < 0)
return ret;
prim_rate:
/* set primary path sample rate */
for (i = 0; i < ARRAY_SIZE(int_prim_sample_rate_val); i++) {
if (sample_rate == int_prim_sample_rate_val[i].sample_rate) {
rate_val = int_prim_sample_rate_val[i].rate_val;
break;
}
}
if ((i == ARRAY_SIZE(int_prim_sample_rate_val)) || (rate_val < 0))
return -EINVAL;
ret = wsa_macro_set_prim_interpolator_rate(dai, (u8) rate_val, sample_rate);
return ret;
}
static int wsa_macro_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
int ret;
switch (substream->stream) {
case SNDRV_PCM_STREAM_PLAYBACK:
ret = wsa_macro_set_interpolator_rate(dai, params_rate(params));
if (ret) {
dev_err(component->dev,
"%s: cannot set sample rate: %u\n",
__func__, params_rate(params));
return ret;
}
break;
default:
break;
}
return 0;
}
static int wsa_macro_get_channel_map(struct snd_soc_dai *dai,
unsigned int *tx_num, unsigned int *tx_slot,
unsigned int *rx_num, unsigned int *rx_slot)
{
struct snd_soc_component *component = dai->component;
struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
u16 val, mask = 0, cnt = 0, temp;
switch (dai->id) {
case WSA_MACRO_AIF_VI:
*tx_slot = wsa->active_ch_mask[dai->id];
*tx_num = wsa->active_ch_cnt[dai->id];
break;
case WSA_MACRO_AIF1_PB:
case WSA_MACRO_AIF_MIX1_PB:
for_each_set_bit(temp, &wsa->active_ch_mask[dai->id],
WSA_MACRO_RX_MAX) {
mask |= (1 << temp);
if (++cnt == WSA_MACRO_MAX_DMA_CH_PER_PORT)
break;
}
if (mask & 0x0C)
mask = mask >> 0x2;
*rx_slot = mask;
*rx_num = cnt;
break;
case WSA_MACRO_AIF_ECHO:
val = snd_soc_component_read(component, CDC_WSA_RX_INP_MUX_RX_MIX_CFG0);
if (val & WSA_MACRO_EC_MIX_TX1_MASK) {
mask |= 0x2;
cnt++;
}
if (val & WSA_MACRO_EC_MIX_TX0_MASK) {
mask |= 0x1;
cnt++;
}
*tx_slot = mask;
*tx_num = cnt;
break;
default:
dev_err(component->dev, "%s: Invalid AIF\n", __func__);
break;
}
return 0;
}
static const struct snd_soc_dai_ops wsa_macro_dai_ops = {
.hw_params = wsa_macro_hw_params,
.get_channel_map = wsa_macro_get_channel_map,
};
static struct snd_soc_dai_driver wsa_macro_dai[] = {
{
.name = "wsa_macro_rx1",
.id = WSA_MACRO_AIF1_PB,
.playback = {
.stream_name = "WSA_AIF1 Playback",
.rates = WSA_MACRO_RX_RATES,
.formats = WSA_MACRO_RX_FORMATS,
.rate_max = 384000,
.rate_min = 8000,
.channels_min = 1,
.channels_max = 2,
},
.ops = &wsa_macro_dai_ops,
},
{
.name = "wsa_macro_rx_mix",
.id = WSA_MACRO_AIF_MIX1_PB,
.playback = {
.stream_name = "WSA_AIF_MIX1 Playback",
.rates = WSA_MACRO_RX_MIX_RATES,
.formats = WSA_MACRO_RX_FORMATS,
.rate_max = 192000,
.rate_min = 48000,
.channels_min = 1,
.channels_max = 2,
},
.ops = &wsa_macro_dai_ops,
},
{
.name = "wsa_macro_vifeedback",
.id = WSA_MACRO_AIF_VI,
.capture = {
.stream_name = "WSA_AIF_VI Capture",
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
.formats = WSA_MACRO_RX_FORMATS,
.rate_max = 48000,
.rate_min = 8000,
.channels_min = 1,
.channels_max = 4,
},
.ops = &wsa_macro_dai_ops,
},
{
.name = "wsa_macro_echo",
.id = WSA_MACRO_AIF_ECHO,
.capture = {
.stream_name = "WSA_AIF_ECHO Capture",
.rates = WSA_MACRO_ECHO_RATES,
.formats = WSA_MACRO_ECHO_FORMATS,
.rate_max = 48000,
.rate_min = 8000,
.channels_min = 1,
.channels_max = 2,
},
.ops = &wsa_macro_dai_ops,
},
};
static void wsa_macro_mclk_enable(struct wsa_macro *wsa, bool mclk_enable)
{
struct regmap *regmap = wsa->regmap;
if (mclk_enable) {
if (wsa->wsa_mclk_users == 0) {
regcache_mark_dirty(regmap);
regcache_sync(regmap);
/* 9.6MHz MCLK, set value 0x00 if other frequency */
regmap_update_bits(regmap, CDC_WSA_TOP_FREQ_MCLK, 0x01, 0x01);
regmap_update_bits(regmap,
CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL,
CDC_WSA_MCLK_EN_MASK,
CDC_WSA_MCLK_ENABLE);
regmap_update_bits(regmap,
CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL,
CDC_WSA_FS_CNT_EN_MASK,
CDC_WSA_FS_CNT_ENABLE);
}
wsa->wsa_mclk_users++;
} else {
if (wsa->wsa_mclk_users <= 0) {
dev_err(wsa->dev, "clock already disabled\n");
wsa->wsa_mclk_users = 0;
return;
}
wsa->wsa_mclk_users--;
if (wsa->wsa_mclk_users == 0) {
regmap_update_bits(regmap,
CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL,
CDC_WSA_FS_CNT_EN_MASK,
CDC_WSA_FS_CNT_DISABLE);
regmap_update_bits(regmap,
CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL,
CDC_WSA_MCLK_EN_MASK,
CDC_WSA_MCLK_DISABLE);
}
}
}
static int wsa_macro_mclk_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
wsa_macro_mclk_enable(wsa, event == SND_SOC_DAPM_PRE_PMU);
return 0;
}
static int wsa_macro_enable_vi_feedback(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
u32 tx_reg0, tx_reg1;
if (test_bit(WSA_MACRO_TX0, &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
tx_reg0 = CDC_WSA_TX0_SPKR_PROT_PATH_CTL;
tx_reg1 = CDC_WSA_TX1_SPKR_PROT_PATH_CTL;
} else if (test_bit(WSA_MACRO_TX1, &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
tx_reg0 = CDC_WSA_TX2_SPKR_PROT_PATH_CTL;
tx_reg1 = CDC_WSA_TX3_SPKR_PROT_PATH_CTL;
}
switch (event) {
case SND_SOC_DAPM_POST_PMU:
/* Enable V&I sensing */
snd_soc_component_update_bits(component, tx_reg0,
CDC_WSA_TX_SPKR_PROT_RESET_MASK,
CDC_WSA_TX_SPKR_PROT_RESET);
snd_soc_component_update_bits(component, tx_reg1,
CDC_WSA_TX_SPKR_PROT_RESET_MASK,
CDC_WSA_TX_SPKR_PROT_RESET);
snd_soc_component_update_bits(component, tx_reg0,
CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK,
CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K);
snd_soc_component_update_bits(component, tx_reg1,
CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK,
CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K);
snd_soc_component_update_bits(component, tx_reg0,
CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
CDC_WSA_TX_SPKR_PROT_CLK_ENABLE);
snd_soc_component_update_bits(component, tx_reg1,
CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
CDC_WSA_TX_SPKR_PROT_CLK_ENABLE);
snd_soc_component_update_bits(component, tx_reg0,
CDC_WSA_TX_SPKR_PROT_RESET_MASK,
CDC_WSA_TX_SPKR_PROT_NO_RESET);
snd_soc_component_update_bits(component, tx_reg1,
CDC_WSA_TX_SPKR_PROT_RESET_MASK,
CDC_WSA_TX_SPKR_PROT_NO_RESET);
break;
case SND_SOC_DAPM_POST_PMD:
/* Disable V&I sensing */
snd_soc_component_update_bits(component, tx_reg0,
CDC_WSA_TX_SPKR_PROT_RESET_MASK,
CDC_WSA_TX_SPKR_PROT_RESET);
snd_soc_component_update_bits(component, tx_reg1,
CDC_WSA_TX_SPKR_PROT_RESET_MASK,
CDC_WSA_TX_SPKR_PROT_RESET);
snd_soc_component_update_bits(component, tx_reg0,
CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
CDC_WSA_TX_SPKR_PROT_CLK_DISABLE);
snd_soc_component_update_bits(component, tx_reg1,
CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
CDC_WSA_TX_SPKR_PROT_CLK_DISABLE);
break;
}
return 0;
}
static int wsa_macro_enable_mix_path(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
u16 path_reg, gain_reg;
int val;
switch (w->shift) {
case WSA_MACRO_RX_MIX0:
path_reg = CDC_WSA_RX0_RX_PATH_MIX_CTL;
gain_reg = CDC_WSA_RX0_RX_VOL_MIX_CTL;
break;
case WSA_MACRO_RX_MIX1:
path_reg = CDC_WSA_RX1_RX_PATH_MIX_CTL;
gain_reg = CDC_WSA_RX1_RX_VOL_MIX_CTL;
break;
default:
return 0;
}
switch (event) {
case SND_SOC_DAPM_POST_PMU:
val = snd_soc_component_read(component, gain_reg);
snd_soc_component_write(component, gain_reg, val);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component, path_reg,
CDC_WSA_RX_PATH_MIX_CLK_EN_MASK,
CDC_WSA_RX_PATH_MIX_CLK_DISABLE);
break;
}
return 0;
}
static void wsa_macro_hd2_control(struct snd_soc_component *component,
u16 reg, int event)
{
u16 hd2_scale_reg;
u16 hd2_enable_reg;
if (reg == CDC_WSA_RX0_RX_PATH_CTL) {
hd2_scale_reg = CDC_WSA_RX0_RX_PATH_SEC3;
hd2_enable_reg = CDC_WSA_RX0_RX_PATH_CFG0;
}
if (reg == CDC_WSA_RX1_RX_PATH_CTL) {
hd2_scale_reg = CDC_WSA_RX1_RX_PATH_SEC3;
hd2_enable_reg = CDC_WSA_RX1_RX_PATH_CFG0;
}
if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) {
snd_soc_component_update_bits(component, hd2_scale_reg,
CDC_WSA_RX_PATH_HD2_ALPHA_MASK,
0x10);
snd_soc_component_update_bits(component, hd2_scale_reg,
CDC_WSA_RX_PATH_HD2_SCALE_MASK,
0x1);
snd_soc_component_update_bits(component, hd2_enable_reg,
CDC_WSA_RX_PATH_HD2_EN_MASK,
CDC_WSA_RX_PATH_HD2_ENABLE);
}
if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) {
snd_soc_component_update_bits(component, hd2_enable_reg,
CDC_WSA_RX_PATH_HD2_EN_MASK, 0);
snd_soc_component_update_bits(component, hd2_scale_reg,
CDC_WSA_RX_PATH_HD2_SCALE_MASK,
0);
snd_soc_component_update_bits(component, hd2_scale_reg,
CDC_WSA_RX_PATH_HD2_ALPHA_MASK,
0);
}
}
static int wsa_macro_config_compander(struct snd_soc_component *component,
int comp, int event)
{
u16 comp_ctl0_reg, rx_path_cfg0_reg;
struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
if (!wsa->comp_enabled[comp])
return 0;
comp_ctl0_reg = CDC_WSA_COMPANDER0_CTL0 +
(comp * WSA_MACRO_RX_COMP_OFFSET);
rx_path_cfg0_reg = CDC_WSA_RX0_RX_PATH_CFG0 +
(comp * WSA_MACRO_RX_PATH_OFFSET);
if (SND_SOC_DAPM_EVENT_ON(event)) {
/* Enable Compander Clock */
snd_soc_component_update_bits(component, comp_ctl0_reg,
CDC_WSA_COMPANDER_CLK_EN_MASK,
CDC_WSA_COMPANDER_CLK_ENABLE);
snd_soc_component_update_bits(component, comp_ctl0_reg,
CDC_WSA_COMPANDER_SOFT_RST_MASK,
CDC_WSA_COMPANDER_SOFT_RST_ENABLE);
snd_soc_component_update_bits(component, comp_ctl0_reg,
CDC_WSA_COMPANDER_SOFT_RST_MASK,
0);
snd_soc_component_update_bits(component, rx_path_cfg0_reg,
CDC_WSA_RX_PATH_COMP_EN_MASK,
CDC_WSA_RX_PATH_COMP_ENABLE);
}
if (SND_SOC_DAPM_EVENT_OFF(event)) {
snd_soc_component_update_bits(component, comp_ctl0_reg,
CDC_WSA_COMPANDER_HALT_MASK,
CDC_WSA_COMPANDER_HALT);
snd_soc_component_update_bits(component, rx_path_cfg0_reg,
CDC_WSA_RX_PATH_COMP_EN_MASK, 0);
snd_soc_component_update_bits(component, comp_ctl0_reg,
CDC_WSA_COMPANDER_SOFT_RST_MASK,
CDC_WSA_COMPANDER_SOFT_RST_ENABLE);
snd_soc_component_update_bits(component, comp_ctl0_reg,
CDC_WSA_COMPANDER_SOFT_RST_MASK,
0);
snd_soc_component_update_bits(component, comp_ctl0_reg,
CDC_WSA_COMPANDER_CLK_EN_MASK, 0);
snd_soc_component_update_bits(component, comp_ctl0_reg,
CDC_WSA_COMPANDER_HALT_MASK, 0);
}
return 0;
}
static void wsa_macro_enable_softclip_clk(struct snd_soc_component *component,
struct wsa_macro *wsa,
int path,
bool enable)
{
u16 softclip_clk_reg = CDC_WSA_SOFTCLIP0_CRC +
(path * WSA_MACRO_RX_SOFTCLIP_OFFSET);
u8 softclip_mux_mask = (1 << path);
u8 softclip_mux_value = (1 << path);
if (enable) {
if (wsa->softclip_clk_users[path] == 0) {
snd_soc_component_update_bits(component,
softclip_clk_reg,
CDC_WSA_SOFTCLIP_CLK_EN_MASK,
CDC_WSA_SOFTCLIP_CLK_ENABLE);
snd_soc_component_update_bits(component,
CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0,
softclip_mux_mask, softclip_mux_value);
}
wsa->softclip_clk_users[path]++;
} else {
wsa->softclip_clk_users[path]--;
if (wsa->softclip_clk_users[path] == 0) {
snd_soc_component_update_bits(component,
softclip_clk_reg,
CDC_WSA_SOFTCLIP_CLK_EN_MASK,
0);
snd_soc_component_update_bits(component,
CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0,
softclip_mux_mask, 0x00);
}
}
}
static int wsa_macro_config_softclip(struct snd_soc_component *component,
int path, int event)
{
u16 softclip_ctrl_reg;
struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
int softclip_path = 0;
if (path == WSA_MACRO_COMP1)
softclip_path = WSA_MACRO_SOFTCLIP0;
else if (path == WSA_MACRO_COMP2)
softclip_path = WSA_MACRO_SOFTCLIP1;
if (!wsa->is_softclip_on[softclip_path])
return 0;
softclip_ctrl_reg = CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL +
(softclip_path * WSA_MACRO_RX_SOFTCLIP_OFFSET);
if (SND_SOC_DAPM_EVENT_ON(event)) {
/* Enable Softclip clock and mux */
wsa_macro_enable_softclip_clk(component, wsa, softclip_path,
true);
/* Enable Softclip control */
snd_soc_component_update_bits(component, softclip_ctrl_reg,
CDC_WSA_SOFTCLIP_EN_MASK,
CDC_WSA_SOFTCLIP_ENABLE);
}
if (SND_SOC_DAPM_EVENT_OFF(event)) {
snd_soc_component_update_bits(component, softclip_ctrl_reg,
CDC_WSA_SOFTCLIP_EN_MASK, 0);
wsa_macro_enable_softclip_clk(component, wsa, softclip_path,
false);
}
return 0;
}
static bool wsa_macro_adie_lb(struct snd_soc_component *component,
int interp_idx)
{
u16 int_mux_cfg0, int_mux_cfg1;
u8 int_n_inp0, int_n_inp1, int_n_inp2;
int_mux_cfg0 = CDC_WSA_RX_INP_MUX_RX_INT0_CFG0 + interp_idx * 8;
int_mux_cfg1 = int_mux_cfg0 + 4;
int_n_inp0 = snd_soc_component_read_field(component, int_mux_cfg0,
CDC_WSA_RX_INTX_1_MIX_INP0_SEL_MASK);
if (int_n_inp0 == INTn_1_INP_SEL_DEC0 ||
int_n_inp0 == INTn_1_INP_SEL_DEC1)
return true;
int_n_inp1 = snd_soc_component_read_field(component, int_mux_cfg0,
CDC_WSA_RX_INTX_1_MIX_INP1_SEL_MASK);
if (int_n_inp1 == INTn_1_INP_SEL_DEC0 ||
int_n_inp1 == INTn_1_INP_SEL_DEC1)
return true;
int_n_inp2 = snd_soc_component_read_field(component, int_mux_cfg1,
CDC_WSA_RX_INTX_1_MIX_INP2_SEL_MASK);
if (int_n_inp2 == INTn_1_INP_SEL_DEC0 ||
int_n_inp2 == INTn_1_INP_SEL_DEC1)
return true;
return false;
}
static int wsa_macro_enable_main_path(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
u16 reg;
reg = CDC_WSA_RX0_RX_PATH_CTL + WSA_MACRO_RX_PATH_OFFSET * w->shift;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
if (wsa_macro_adie_lb(component, w->shift)) {
snd_soc_component_update_bits(component, reg,
CDC_WSA_RX_PATH_CLK_EN_MASK,
CDC_WSA_RX_PATH_CLK_ENABLE);
}
break;
default:
break;
}
return 0;
}
static int wsa_macro_interp_get_primary_reg(u16 reg, u16 *ind)
{
u16 prim_int_reg = 0;
switch (reg) {
case CDC_WSA_RX0_RX_PATH_CTL:
case CDC_WSA_RX0_RX_PATH_MIX_CTL:
prim_int_reg = CDC_WSA_RX0_RX_PATH_CTL;
*ind = 0;
break;
case CDC_WSA_RX1_RX_PATH_CTL:
case CDC_WSA_RX1_RX_PATH_MIX_CTL:
prim_int_reg = CDC_WSA_RX1_RX_PATH_CTL;
*ind = 1;
break;
}
return prim_int_reg;
}
static int wsa_macro_enable_prim_interpolator(struct snd_soc_component *component,
u16 reg, int event)
{
u16 prim_int_reg;
u16 ind = 0;
struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
prim_int_reg = wsa_macro_interp_get_primary_reg(reg, &ind);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
wsa->prim_int_users[ind]++;
if (wsa->prim_int_users[ind] == 1) {
snd_soc_component_update_bits(component,
prim_int_reg + WSA_MACRO_RX_PATH_CFG3_OFFSET,
CDC_WSA_RX_DC_DCOEFF_MASK,
0x3);
snd_soc_component_update_bits(component, prim_int_reg,
CDC_WSA_RX_PATH_PGA_MUTE_EN_MASK,
CDC_WSA_RX_PATH_PGA_MUTE_ENABLE);
wsa_macro_hd2_control(component, prim_int_reg, event);
snd_soc_component_update_bits(component,
prim_int_reg + WSA_MACRO_RX_PATH_DSMDEM_OFFSET,
CDC_WSA_RX_DSMDEM_CLK_EN_MASK,
CDC_WSA_RX_DSMDEM_CLK_ENABLE);
}
if ((reg != prim_int_reg) &&
((snd_soc_component_read(
component, prim_int_reg)) & 0x10))
snd_soc_component_update_bits(component, reg,
0x10, 0x10);
break;
case SND_SOC_DAPM_POST_PMD:
wsa->prim_int_users[ind]--;
if (wsa->prim_int_users[ind] == 0) {
snd_soc_component_update_bits(component,
prim_int_reg + WSA_MACRO_RX_PATH_DSMDEM_OFFSET,
CDC_WSA_RX_DSMDEM_CLK_EN_MASK, 0);
wsa_macro_hd2_control(component, prim_int_reg, event);
}
break;
}
return 0;
}
static int wsa_macro_config_ear_spkr_gain(struct snd_soc_component *component,
struct wsa_macro *wsa,
int event, int gain_reg)
{
int comp_gain_offset, val;
switch (wsa->spkr_mode) {
/* Compander gain in WSA_MACRO_SPKR_MODE1 case is 12 dB */
case WSA_MACRO_SPKR_MODE_1:
comp_gain_offset = -12;
break;
/* Default case compander gain is 15 dB */
default:
comp_gain_offset = -15;
break;
}
switch (event) {
case SND_SOC_DAPM_POST_PMU:
/* Apply ear spkr gain only if compander is enabled */
if (wsa->comp_enabled[WSA_MACRO_COMP1] &&
(gain_reg == CDC_WSA_RX0_RX_VOL_CTL) &&
(wsa->ear_spkr_gain != 0)) {
/* For example, val is -8(-12+5-1) for 4dB of gain */
val = comp_gain_offset + wsa->ear_spkr_gain - 1;
snd_soc_component_write(component, gain_reg, val);
}
break;
case SND_SOC_DAPM_POST_PMD:
/*
* Reset RX0 volume to 0 dB if compander is enabled and
* ear_spkr_gain is non-zero.
*/
if (wsa->comp_enabled[WSA_MACRO_COMP1] &&
(gain_reg == CDC_WSA_RX0_RX_VOL_CTL) &&
(wsa->ear_spkr_gain != 0)) {
snd_soc_component_write(component, gain_reg, 0x0);
}
break;
}
return 0;
}
static int wsa_macro_enable_interpolator(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
u16 gain_reg;
u16 reg;
int val;
int offset_val = 0;
struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
if (w->shift == WSA_MACRO_COMP1) {
reg = CDC_WSA_RX0_RX_PATH_CTL;
gain_reg = CDC_WSA_RX0_RX_VOL_CTL;
} else if (w->shift == WSA_MACRO_COMP2) {
reg = CDC_WSA_RX1_RX_PATH_CTL;
gain_reg = CDC_WSA_RX1_RX_VOL_CTL;
}
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* Reset if needed */
wsa_macro_enable_prim_interpolator(component, reg, event);
break;
case SND_SOC_DAPM_POST_PMU:
wsa_macro_config_compander(component, w->shift, event);
wsa_macro_config_softclip(component, w->shift, event);
/* apply gain after int clk is enabled */
if ((wsa->spkr_gain_offset == WSA_MACRO_GAIN_OFFSET_M1P5_DB) &&
(wsa->comp_enabled[WSA_MACRO_COMP1] ||
wsa->comp_enabled[WSA_MACRO_COMP2])) {
snd_soc_component_update_bits(component,
CDC_WSA_RX0_RX_PATH_SEC1,
CDC_WSA_RX_PGA_HALF_DB_MASK,
CDC_WSA_RX_PGA_HALF_DB_ENABLE);
snd_soc_component_update_bits(component,
CDC_WSA_RX0_RX_PATH_MIX_SEC0,
CDC_WSA_RX_PGA_HALF_DB_MASK,
CDC_WSA_RX_PGA_HALF_DB_ENABLE);
snd_soc_component_update_bits(component,
CDC_WSA_RX1_RX_PATH_SEC1,
CDC_WSA_RX_PGA_HALF_DB_MASK,
CDC_WSA_RX_PGA_HALF_DB_ENABLE);
snd_soc_component_update_bits(component,
CDC_WSA_RX1_RX_PATH_MIX_SEC0,
CDC_WSA_RX_PGA_HALF_DB_MASK,
CDC_WSA_RX_PGA_HALF_DB_ENABLE);
offset_val = -2;
}
val = snd_soc_component_read(component, gain_reg);
val += offset_val;
snd_soc_component_write(component, gain_reg, val);
wsa_macro_config_ear_spkr_gain(component, wsa,
event, gain_reg);
break;
case SND_SOC_DAPM_POST_PMD:
wsa_macro_config_compander(component, w->shift, event);
wsa_macro_config_softclip(component, w->shift, event);
wsa_macro_enable_prim_interpolator(component, reg, event);
if ((wsa->spkr_gain_offset == WSA_MACRO_GAIN_OFFSET_M1P5_DB) &&
(wsa->comp_enabled[WSA_MACRO_COMP1] ||
wsa->comp_enabled[WSA_MACRO_COMP2])) {
snd_soc_component_update_bits(component,
CDC_WSA_RX0_RX_PATH_SEC1,
CDC_WSA_RX_PGA_HALF_DB_MASK,
CDC_WSA_RX_PGA_HALF_DB_DISABLE);
snd_soc_component_update_bits(component,
CDC_WSA_RX0_RX_PATH_MIX_SEC0,
CDC_WSA_RX_PGA_HALF_DB_MASK,
CDC_WSA_RX_PGA_HALF_DB_DISABLE);
snd_soc_component_update_bits(component,
CDC_WSA_RX1_RX_PATH_SEC1,
CDC_WSA_RX_PGA_HALF_DB_MASK,
CDC_WSA_RX_PGA_HALF_DB_DISABLE);
snd_soc_component_update_bits(component,
CDC_WSA_RX1_RX_PATH_MIX_SEC0,
CDC_WSA_RX_PGA_HALF_DB_MASK,
CDC_WSA_RX_PGA_HALF_DB_DISABLE);
offset_val = 2;
val = snd_soc_component_read(component, gain_reg);
val += offset_val;
snd_soc_component_write(component, gain_reg, val);
}
wsa_macro_config_ear_spkr_gain(component, wsa,
event, gain_reg);
break;
}
return 0;
}
static int wsa_macro_spk_boost_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
u16 boost_path_ctl, boost_path_cfg1;
u16 reg, reg_mix;
if (!strcmp(w->name, "WSA_RX INT0 CHAIN")) {
boost_path_ctl = CDC_WSA_BOOST0_BOOST_PATH_CTL;
boost_path_cfg1 = CDC_WSA_RX0_RX_PATH_CFG1;
reg = CDC_WSA_RX0_RX_PATH_CTL;
reg_mix = CDC_WSA_RX0_RX_PATH_MIX_CTL;
} else if (!strcmp(w->name, "WSA_RX INT1 CHAIN")) {
boost_path_ctl = CDC_WSA_BOOST1_BOOST_PATH_CTL;
boost_path_cfg1 = CDC_WSA_RX1_RX_PATH_CFG1;
reg = CDC_WSA_RX1_RX_PATH_CTL;
reg_mix = CDC_WSA_RX1_RX_PATH_MIX_CTL;
}
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_component_update_bits(component, boost_path_cfg1,
CDC_WSA_RX_PATH_SMART_BST_EN_MASK,
CDC_WSA_RX_PATH_SMART_BST_ENABLE);
snd_soc_component_update_bits(component, boost_path_ctl,
CDC_WSA_BOOST_PATH_CLK_EN_MASK,
CDC_WSA_BOOST_PATH_CLK_ENABLE);
if ((snd_soc_component_read(component, reg_mix)) & 0x10)
snd_soc_component_update_bits(component, reg_mix,
0x10, 0x00);
break;
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(component, reg, 0x10, 0x00);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component, boost_path_ctl,
CDC_WSA_BOOST_PATH_CLK_EN_MASK,
CDC_WSA_BOOST_PATH_CLK_DISABLE);
snd_soc_component_update_bits(component, boost_path_cfg1,
CDC_WSA_RX_PATH_SMART_BST_EN_MASK,
CDC_WSA_RX_PATH_SMART_BST_DISABLE);
break;
}
return 0;
}
static int wsa_macro_enable_echo(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
u16 val, ec_tx, ec_hq_reg;
val = snd_soc_component_read(component, CDC_WSA_RX_INP_MUX_RX_MIX_CFG0);
switch (w->shift) {
case WSA_MACRO_EC0_MUX:
val = val & CDC_WSA_RX_MIX_TX0_SEL_MASK;
ec_tx = val - 1;
break;
case WSA_MACRO_EC1_MUX:
val = val & CDC_WSA_RX_MIX_TX1_SEL_MASK;
ec_tx = (val >> CDC_WSA_RX_MIX_TX1_SEL_SHFT) - 1;
break;
default:
dev_err(component->dev, "%s: Invalid shift %u\n",
__func__, w->shift);
return -EINVAL;
}
if (wsa->ec_hq[ec_tx]) {
ec_hq_reg = CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL + 0x40 * ec_tx;
snd_soc_component_update_bits(component, ec_hq_reg,
CDC_WSA_EC_HQ_EC_CLK_EN_MASK,
CDC_WSA_EC_HQ_EC_CLK_ENABLE);
ec_hq_reg = CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0 + 0x40 * ec_tx;
/* default set to 48k */
snd_soc_component_update_bits(component, ec_hq_reg,
CDC_WSA_EC_HQ_EC_REF_PCM_RATE_MASK,
CDC_WSA_EC_HQ_EC_REF_PCM_RATE_48K);
}
return 0;
}
static int wsa_macro_get_ec_hq(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
int ec_tx = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = wsa->ec_hq[ec_tx];
return 0;
}
static int wsa_macro_set_ec_hq(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
int ec_tx = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
int value = ucontrol->value.integer.value[0];
struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
wsa->ec_hq[ec_tx] = value;
return 0;
}
static int wsa_macro_get_compander(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = wsa->comp_enabled[comp];
return 0;
}
static int wsa_macro_set_compander(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
int value = ucontrol->value.integer.value[0];
struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
wsa->comp_enabled[comp] = value;
return 0;
}
static int wsa_macro_ear_spkr_pa_gain_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = wsa->ear_spkr_gain;
return 0;
}
static int wsa_macro_ear_spkr_pa_gain_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
wsa->ear_spkr_gain = ucontrol->value.integer.value[0];
return 0;
}
static int wsa_macro_rx_mux_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_widget *widget =
snd_soc_dapm_kcontrol_widget(kcontrol);
struct snd_soc_component *component =
snd_soc_dapm_to_component(widget->dapm);
struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] =
wsa->rx_port_value[widget->shift];
return 0;
}
static int wsa_macro_rx_mux_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_widget *widget =
snd_soc_dapm_kcontrol_widget(kcontrol);
struct snd_soc_component *component =
snd_soc_dapm_to_component(widget->dapm);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
struct snd_soc_dapm_update *update = NULL;
u32 rx_port_value = ucontrol->value.integer.value[0];
u32 bit_input;
u32 aif_rst;
struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
aif_rst = wsa->rx_port_value[widget->shift];
if (!rx_port_value) {
if (aif_rst == 0)
return 0;
if (aif_rst >= WSA_MACRO_RX_MAX) {
dev_err(component->dev, "%s: Invalid AIF reset\n", __func__);
return 0;
}
}
wsa->rx_port_value[widget->shift] = rx_port_value;
bit_input = widget->shift;
switch (rx_port_value) {
case 0:
if (wsa->active_ch_cnt[aif_rst]) {
clear_bit(bit_input,
&wsa->active_ch_mask[aif_rst]);
wsa->active_ch_cnt[aif_rst]--;
}
break;
case 1:
case 2:
set_bit(bit_input,
&wsa->active_ch_mask[rx_port_value]);
wsa->active_ch_cnt[rx_port_value]++;
break;
default:
dev_err(component->dev,
"%s: Invalid AIF_ID for WSA RX MUX %d\n",
__func__, rx_port_value);
return -EINVAL;
}
snd_soc_dapm_mux_update_power(widget->dapm, kcontrol,
rx_port_value, e, update);
return 0;
}
static int wsa_macro_soft_clip_enable_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
int path = ((struct soc_mixer_control *)kcontrol->private_value)->shift;
ucontrol->value.integer.value[0] = wsa->is_softclip_on[path];
return 0;
}
static int wsa_macro_soft_clip_enable_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
int path = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
wsa->is_softclip_on[path] = ucontrol->value.integer.value[0];
return 0;
}
static const struct snd_kcontrol_new wsa_macro_snd_controls[] = {
SOC_ENUM_EXT("EAR SPKR PA Gain", wsa_macro_ear_spkr_pa_gain_enum,
wsa_macro_ear_spkr_pa_gain_get,
wsa_macro_ear_spkr_pa_gain_put),
SOC_SINGLE_EXT("WSA_Softclip0 Enable", SND_SOC_NOPM,
WSA_MACRO_SOFTCLIP0, 1, 0,
wsa_macro_soft_clip_enable_get,
wsa_macro_soft_clip_enable_put),
SOC_SINGLE_EXT("WSA_Softclip1 Enable", SND_SOC_NOPM,
WSA_MACRO_SOFTCLIP1, 1, 0,
wsa_macro_soft_clip_enable_get,
wsa_macro_soft_clip_enable_put),
SOC_SINGLE_S8_TLV("WSA_RX0 Digital Volume", CDC_WSA_RX0_RX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("WSA_RX1 Digital Volume", CDC_WSA_RX1_RX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE("WSA_RX0 Digital Mute", CDC_WSA_RX0_RX_PATH_CTL, 4, 1, 0),
SOC_SINGLE("WSA_RX1 Digital Mute", CDC_WSA_RX1_RX_PATH_CTL, 4, 1, 0),
SOC_SINGLE("WSA_RX0_MIX Digital Mute", CDC_WSA_RX0_RX_PATH_MIX_CTL, 4,
1, 0),
SOC_SINGLE("WSA_RX1_MIX Digital Mute", CDC_WSA_RX1_RX_PATH_MIX_CTL, 4,
1, 0),
SOC_SINGLE_EXT("WSA_COMP1 Switch", SND_SOC_NOPM, WSA_MACRO_COMP1, 1, 0,
wsa_macro_get_compander, wsa_macro_set_compander),
SOC_SINGLE_EXT("WSA_COMP2 Switch", SND_SOC_NOPM, WSA_MACRO_COMP2, 1, 0,
wsa_macro_get_compander, wsa_macro_set_compander),
SOC_SINGLE_EXT("WSA_RX0 EC_HQ Switch", SND_SOC_NOPM, WSA_MACRO_RX0, 1, 0,
wsa_macro_get_ec_hq, wsa_macro_set_ec_hq),
SOC_SINGLE_EXT("WSA_RX1 EC_HQ Switch", SND_SOC_NOPM, WSA_MACRO_RX1, 1, 0,
wsa_macro_get_ec_hq, wsa_macro_set_ec_hq),
};
static const struct soc_enum rx_mux_enum =
SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_mux_text), rx_mux_text);
static const struct snd_kcontrol_new rx_mux[WSA_MACRO_RX_MAX] = {
SOC_DAPM_ENUM_EXT("WSA RX0 Mux", rx_mux_enum,
wsa_macro_rx_mux_get, wsa_macro_rx_mux_put),
SOC_DAPM_ENUM_EXT("WSA RX1 Mux", rx_mux_enum,
wsa_macro_rx_mux_get, wsa_macro_rx_mux_put),
SOC_DAPM_ENUM_EXT("WSA RX_MIX0 Mux", rx_mux_enum,
wsa_macro_rx_mux_get, wsa_macro_rx_mux_put),
SOC_DAPM_ENUM_EXT("WSA RX_MIX1 Mux", rx_mux_enum,
wsa_macro_rx_mux_get, wsa_macro_rx_mux_put),
};
static int wsa_macro_vi_feed_mixer_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
u32 spk_tx_id = mixer->shift;
u32 dai_id = widget->shift;
if (test_bit(spk_tx_id, &wsa->active_ch_mask[dai_id]))
ucontrol->value.integer.value[0] = 1;
else
ucontrol->value.integer.value[0] = 0;
return 0;
}
static int wsa_macro_vi_feed_mixer_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
u32 enable = ucontrol->value.integer.value[0];
u32 spk_tx_id = mixer->shift;
if (enable) {
if (spk_tx_id == WSA_MACRO_TX0 &&
!test_bit(WSA_MACRO_TX0,
&wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
set_bit(WSA_MACRO_TX0,
&wsa->active_ch_mask[WSA_MACRO_AIF_VI]);
wsa->active_ch_cnt[WSA_MACRO_AIF_VI]++;
}
if (spk_tx_id == WSA_MACRO_TX1 &&
!test_bit(WSA_MACRO_TX1,
&wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
set_bit(WSA_MACRO_TX1,
&wsa->active_ch_mask[WSA_MACRO_AIF_VI]);
wsa->active_ch_cnt[WSA_MACRO_AIF_VI]++;
}
} else {
if (spk_tx_id == WSA_MACRO_TX0 &&
test_bit(WSA_MACRO_TX0,
&wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
clear_bit(WSA_MACRO_TX0,
&wsa->active_ch_mask[WSA_MACRO_AIF_VI]);
wsa->active_ch_cnt[WSA_MACRO_AIF_VI]--;
}
if (spk_tx_id == WSA_MACRO_TX1 &&
test_bit(WSA_MACRO_TX1,
&wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
clear_bit(WSA_MACRO_TX1,
&wsa->active_ch_mask[WSA_MACRO_AIF_VI]);
wsa->active_ch_cnt[WSA_MACRO_AIF_VI]--;
}
}
snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, NULL);
return 0;
}
static const struct snd_kcontrol_new aif_vi_mixer[] = {
SOC_SINGLE_EXT("WSA_SPKR_VI_1", SND_SOC_NOPM, WSA_MACRO_TX0, 1, 0,
wsa_macro_vi_feed_mixer_get,
wsa_macro_vi_feed_mixer_put),
SOC_SINGLE_EXT("WSA_SPKR_VI_2", SND_SOC_NOPM, WSA_MACRO_TX1, 1, 0,
wsa_macro_vi_feed_mixer_get,
wsa_macro_vi_feed_mixer_put),
};
static const struct snd_soc_dapm_widget wsa_macro_dapm_widgets[] = {
SND_SOC_DAPM_AIF_IN("WSA AIF1 PB", "WSA_AIF1 Playback", 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("WSA AIF_MIX1 PB", "WSA_AIF_MIX1 Playback", 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT_E("WSA AIF_VI", "WSA_AIF_VI Capture", 0,
SND_SOC_NOPM, WSA_MACRO_AIF_VI, 0,
wsa_macro_enable_vi_feedback,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_AIF_OUT("WSA AIF_ECHO", "WSA_AIF_ECHO Capture", 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_MIXER("WSA_AIF_VI Mixer", SND_SOC_NOPM, WSA_MACRO_AIF_VI,
0, aif_vi_mixer, ARRAY_SIZE(aif_vi_mixer)),
SND_SOC_DAPM_MUX_E("WSA RX_MIX EC0_MUX", SND_SOC_NOPM,
WSA_MACRO_EC0_MUX, 0,
&rx_mix_ec0_mux, wsa_macro_enable_echo,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("WSA RX_MIX EC1_MUX", SND_SOC_NOPM,
WSA_MACRO_EC1_MUX, 0,
&rx_mix_ec1_mux, wsa_macro_enable_echo,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("WSA RX0 MUX", SND_SOC_NOPM, WSA_MACRO_RX0, 0,
&rx_mux[WSA_MACRO_RX0]),
SND_SOC_DAPM_MUX("WSA RX1 MUX", SND_SOC_NOPM, WSA_MACRO_RX1, 0,
&rx_mux[WSA_MACRO_RX1]),
SND_SOC_DAPM_MUX("WSA RX_MIX0 MUX", SND_SOC_NOPM, WSA_MACRO_RX_MIX0, 0,
&rx_mux[WSA_MACRO_RX_MIX0]),
SND_SOC_DAPM_MUX("WSA RX_MIX1 MUX", SND_SOC_NOPM, WSA_MACRO_RX_MIX1, 0,
&rx_mux[WSA_MACRO_RX_MIX1]),
SND_SOC_DAPM_MIXER("WSA RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("WSA RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("WSA RX_MIX0", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("WSA RX_MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX("WSA_RX0 INP0", SND_SOC_NOPM, 0, 0, &rx0_prim_inp0_mux),
SND_SOC_DAPM_MUX("WSA_RX0 INP1", SND_SOC_NOPM, 0, 0, &rx0_prim_inp1_mux),
SND_SOC_DAPM_MUX("WSA_RX0 INP2", SND_SOC_NOPM, 0, 0, &rx0_prim_inp2_mux),
SND_SOC_DAPM_MUX_E("WSA_RX0 MIX INP", SND_SOC_NOPM, WSA_MACRO_RX_MIX0,
0, &rx0_mix_mux, wsa_macro_enable_mix_path,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("WSA_RX1 INP0", SND_SOC_NOPM, 0, 0, &rx1_prim_inp0_mux),
SND_SOC_DAPM_MUX("WSA_RX1 INP1", SND_SOC_NOPM, 0, 0, &rx1_prim_inp1_mux),
SND_SOC_DAPM_MUX("WSA_RX1 INP2", SND_SOC_NOPM, 0, 0, &rx1_prim_inp2_mux),
SND_SOC_DAPM_MUX_E("WSA_RX1 MIX INP", SND_SOC_NOPM, WSA_MACRO_RX_MIX1,
0, &rx1_mix_mux, wsa_macro_enable_mix_path,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER_E("WSA_RX INT0 MIX", SND_SOC_NOPM, 0, 0, NULL, 0,
wsa_macro_enable_main_path, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_MIXER_E("WSA_RX INT1 MIX", SND_SOC_NOPM, 1, 0, NULL, 0,
wsa_macro_enable_main_path, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_MIXER("WSA_RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("WSA_RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX("WSA_RX0 INT0 SIDETONE MIX", CDC_WSA_RX0_RX_PATH_CFG1,
4, 0, &rx0_sidetone_mix_mux),
SND_SOC_DAPM_INPUT("WSA SRC0_INP"),
SND_SOC_DAPM_INPUT("WSA_TX DEC0_INP"),
SND_SOC_DAPM_INPUT("WSA_TX DEC1_INP"),
SND_SOC_DAPM_MIXER_E("WSA_RX INT0 INTERP", SND_SOC_NOPM,
WSA_MACRO_COMP1, 0, NULL, 0,
wsa_macro_enable_interpolator,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER_E("WSA_RX INT1 INTERP", SND_SOC_NOPM,
WSA_MACRO_COMP2, 0, NULL, 0,
wsa_macro_enable_interpolator,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER_E("WSA_RX INT0 CHAIN", SND_SOC_NOPM, 0, 0,
NULL, 0, wsa_macro_spk_boost_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER_E("WSA_RX INT1 CHAIN", SND_SOC_NOPM, 0, 0,
NULL, 0, wsa_macro_spk_boost_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_INPUT("VIINPUT_WSA"),
SND_SOC_DAPM_OUTPUT("WSA_SPK1 OUT"),
SND_SOC_DAPM_OUTPUT("WSA_SPK2 OUT"),
SND_SOC_DAPM_SUPPLY("WSA_RX0_CLK", CDC_WSA_RX0_RX_PATH_CTL, 5, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("WSA_RX1_CLK", CDC_WSA_RX1_RX_PATH_CTL, 5, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("WSA_RX_MIX0_CLK", CDC_WSA_RX0_RX_PATH_MIX_CTL, 5, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("WSA_RX_MIX1_CLK", CDC_WSA_RX1_RX_PATH_MIX_CTL, 5, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("WSA_MCLK", 0, SND_SOC_NOPM, 0, 0,
wsa_macro_mclk_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
};
static const struct snd_soc_dapm_route wsa_audio_map[] = {
/* VI Feedback */
{"WSA_AIF_VI Mixer", "WSA_SPKR_VI_1", "VIINPUT_WSA"},
{"WSA_AIF_VI Mixer", "WSA_SPKR_VI_2", "VIINPUT_WSA"},
{"WSA AIF_VI", NULL, "WSA_AIF_VI Mixer"},
{"WSA AIF_VI", NULL, "WSA_MCLK"},
{"WSA RX_MIX EC0_MUX", "RX_MIX_TX0", "WSA_RX INT0 SEC MIX"},
{"WSA RX_MIX EC1_MUX", "RX_MIX_TX0", "WSA_RX INT0 SEC MIX"},
{"WSA RX_MIX EC0_MUX", "RX_MIX_TX1", "WSA_RX INT1 SEC MIX"},
{"WSA RX_MIX EC1_MUX", "RX_MIX_TX1", "WSA_RX INT1 SEC MIX"},
{"WSA AIF_ECHO", NULL, "WSA RX_MIX EC0_MUX"},
{"WSA AIF_ECHO", NULL, "WSA RX_MIX EC1_MUX"},
{"WSA AIF_ECHO", NULL, "WSA_MCLK"},
{"WSA AIF1 PB", NULL, "WSA_MCLK"},
{"WSA AIF_MIX1 PB", NULL, "WSA_MCLK"},
{"WSA RX0 MUX", "AIF1_PB", "WSA AIF1 PB"},
{"WSA RX1 MUX", "AIF1_PB", "WSA AIF1 PB"},
{"WSA RX_MIX0 MUX", "AIF1_PB", "WSA AIF1 PB"},
{"WSA RX_MIX1 MUX", "AIF1_PB", "WSA AIF1 PB"},
{"WSA RX0 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"},
{"WSA RX1 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"},
{"WSA RX_MIX0 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"},
{"WSA RX_MIX1 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"},
{"WSA RX0", NULL, "WSA RX0 MUX"},
{"WSA RX1", NULL, "WSA RX1 MUX"},
{"WSA RX_MIX0", NULL, "WSA RX_MIX0 MUX"},
{"WSA RX_MIX1", NULL, "WSA RX_MIX1 MUX"},
{"WSA RX0", NULL, "WSA_RX0_CLK"},
{"WSA RX1", NULL, "WSA_RX1_CLK"},
{"WSA RX_MIX0", NULL, "WSA_RX_MIX0_CLK"},
{"WSA RX_MIX1", NULL, "WSA_RX_MIX1_CLK"},
{"WSA_RX0 INP0", "RX0", "WSA RX0"},
{"WSA_RX0 INP0", "RX1", "WSA RX1"},
{"WSA_RX0 INP0", "RX_MIX0", "WSA RX_MIX0"},
{"WSA_RX0 INP0", "RX_MIX1", "WSA RX_MIX1"},
{"WSA_RX0 INP0", "DEC0", "WSA_TX DEC0_INP"},
{"WSA_RX0 INP0", "DEC1", "WSA_TX DEC1_INP"},
{"WSA_RX INT0 MIX", NULL, "WSA_RX0 INP0"},
{"WSA_RX0 INP1", "RX0", "WSA RX0"},
{"WSA_RX0 INP1", "RX1", "WSA RX1"},
{"WSA_RX0 INP1", "RX_MIX0", "WSA RX_MIX0"},
{"WSA_RX0 INP1", "RX_MIX1", "WSA RX_MIX1"},
{"WSA_RX0 INP1", "DEC0", "WSA_TX DEC0_INP"},
{"WSA_RX0 INP1", "DEC1", "WSA_TX DEC1_INP"},
{"WSA_RX INT0 MIX", NULL, "WSA_RX0 INP1"},
{"WSA_RX0 INP2", "RX0", "WSA RX0"},
{"WSA_RX0 INP2", "RX1", "WSA RX1"},
{"WSA_RX0 INP2", "RX_MIX0", "WSA RX_MIX0"},
{"WSA_RX0 INP2", "RX_MIX1", "WSA RX_MIX1"},
{"WSA_RX0 INP2", "DEC0", "WSA_TX DEC0_INP"},
{"WSA_RX0 INP2", "DEC1", "WSA_TX DEC1_INP"},
{"WSA_RX INT0 MIX", NULL, "WSA_RX0 INP2"},
{"WSA_RX0 MIX INP", "RX0", "WSA RX0"},
{"WSA_RX0 MIX INP", "RX1", "WSA RX1"},
{"WSA_RX0 MIX INP", "RX_MIX0", "WSA RX_MIX0"},
{"WSA_RX0 MIX INP", "RX_MIX1", "WSA RX_MIX1"},
{"WSA_RX INT0 SEC MIX", NULL, "WSA_RX0 MIX INP"},
{"WSA_RX INT0 SEC MIX", NULL, "WSA_RX INT0 MIX"},
{"WSA_RX INT0 INTERP", NULL, "WSA_RX INT0 SEC MIX"},
{"WSA_RX0 INT0 SIDETONE MIX", "SRC0", "WSA SRC0_INP"},
{"WSA_RX INT0 INTERP", NULL, "WSA_RX0 INT0 SIDETONE MIX"},
{"WSA_RX INT0 CHAIN", NULL, "WSA_RX INT0 INTERP"},
{"WSA_SPK1 OUT", NULL, "WSA_RX INT0 CHAIN"},
{"WSA_SPK1 OUT", NULL, "WSA_MCLK"},
{"WSA_RX1 INP0", "RX0", "WSA RX0"},
{"WSA_RX1 INP0", "RX1", "WSA RX1"},
{"WSA_RX1 INP0", "RX_MIX0", "WSA RX_MIX0"},
{"WSA_RX1 INP0", "RX_MIX1", "WSA RX_MIX1"},
{"WSA_RX1 INP0", "DEC0", "WSA_TX DEC0_INP"},
{"WSA_RX1 INP0", "DEC1", "WSA_TX DEC1_INP"},
{"WSA_RX INT1 MIX", NULL, "WSA_RX1 INP0"},
{"WSA_RX1 INP1", "RX0", "WSA RX0"},
{"WSA_RX1 INP1", "RX1", "WSA RX1"},
{"WSA_RX1 INP1", "RX_MIX0", "WSA RX_MIX0"},
{"WSA_RX1 INP1", "RX_MIX1", "WSA RX_MIX1"},
{"WSA_RX1 INP1", "DEC0", "WSA_TX DEC0_INP"},
{"WSA_RX1 INP1", "DEC1", "WSA_TX DEC1_INP"},
{"WSA_RX INT1 MIX", NULL, "WSA_RX1 INP1"},
{"WSA_RX1 INP2", "RX0", "WSA RX0"},
{"WSA_RX1 INP2", "RX1", "WSA RX1"},
{"WSA_RX1 INP2", "RX_MIX0", "WSA RX_MIX0"},
{"WSA_RX1 INP2", "RX_MIX1", "WSA RX_MIX1"},
{"WSA_RX1 INP2", "DEC0", "WSA_TX DEC0_INP"},
{"WSA_RX1 INP2", "DEC1", "WSA_TX DEC1_INP"},
{"WSA_RX INT1 MIX", NULL, "WSA_RX1 INP2"},
{"WSA_RX1 MIX INP", "RX0", "WSA RX0"},
{"WSA_RX1 MIX INP", "RX1", "WSA RX1"},
{"WSA_RX1 MIX INP", "RX_MIX0", "WSA RX_MIX0"},
{"WSA_RX1 MIX INP", "RX_MIX1", "WSA RX_MIX1"},
{"WSA_RX INT1 SEC MIX", NULL, "WSA_RX1 MIX INP"},
{"WSA_RX INT1 SEC MIX", NULL, "WSA_RX INT1 MIX"},
{"WSA_RX INT1 INTERP", NULL, "WSA_RX INT1 SEC MIX"},
{"WSA_RX INT1 CHAIN", NULL, "WSA_RX INT1 INTERP"},
{"WSA_SPK2 OUT", NULL, "WSA_RX INT1 CHAIN"},
{"WSA_SPK2 OUT", NULL, "WSA_MCLK"},
};
static int wsa_swrm_clock(struct wsa_macro *wsa, bool enable)
{
struct regmap *regmap = wsa->regmap;
if (enable) {
int ret;
ret = clk_prepare_enable(wsa->mclk);
if (ret) {
dev_err(wsa->dev, "failed to enable mclk\n");
return ret;
}
wsa_macro_mclk_enable(wsa, true);
regmap_update_bits(regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
CDC_WSA_SWR_CLK_EN_MASK,
CDC_WSA_SWR_CLK_ENABLE);
} else {
regmap_update_bits(regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
CDC_WSA_SWR_CLK_EN_MASK, 0);
wsa_macro_mclk_enable(wsa, false);
clk_disable_unprepare(wsa->mclk);
}
return 0;
}
static int wsa_macro_component_probe(struct snd_soc_component *comp)
{
struct wsa_macro *wsa = snd_soc_component_get_drvdata(comp);
snd_soc_component_init_regmap(comp, wsa->regmap);
wsa->spkr_gain_offset = WSA_MACRO_GAIN_OFFSET_M1P5_DB;
/* set SPKR rate to FS_2P4_3P072 */
snd_soc_component_update_bits(comp, CDC_WSA_RX0_RX_PATH_CFG1,
CDC_WSA_RX_PATH_SPKR_RATE_MASK,
CDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072);
snd_soc_component_update_bits(comp, CDC_WSA_RX1_RX_PATH_CFG1,
CDC_WSA_RX_PATH_SPKR_RATE_MASK,
CDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072);
wsa_macro_set_spkr_mode(comp, WSA_MACRO_SPKR_MODE_1);
return 0;
}
static int swclk_gate_enable(struct clk_hw *hw)
{
return wsa_swrm_clock(to_wsa_macro(hw), true);
}
static void swclk_gate_disable(struct clk_hw *hw)
{
wsa_swrm_clock(to_wsa_macro(hw), false);
}
static int swclk_gate_is_enabled(struct clk_hw *hw)
{
struct wsa_macro *wsa = to_wsa_macro(hw);
int ret, val;
regmap_read(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, &val);
ret = val & BIT(0);
return ret;
}
static unsigned long swclk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
return parent_rate / 2;
}
static const struct clk_ops swclk_gate_ops = {
.prepare = swclk_gate_enable,
.unprepare = swclk_gate_disable,
.is_enabled = swclk_gate_is_enabled,
.recalc_rate = swclk_recalc_rate,
};
static int wsa_macro_register_mclk_output(struct wsa_macro *wsa)
{
struct device *dev = wsa->dev;
const char *parent_clk_name;
struct clk_hw *hw;
struct clk_init_data init;
int ret;
if (wsa->npl)
parent_clk_name = __clk_get_name(wsa->npl);
else
parent_clk_name = __clk_get_name(wsa->mclk);
init.name = "mclk";
of_property_read_string(dev_of_node(dev), "clock-output-names",
&init.name);
init.ops = &swclk_gate_ops;
init.flags = 0;
init.parent_names = &parent_clk_name;
init.num_parents = 1;
wsa->hw.init = &init;
hw = &wsa->hw;
ret = clk_hw_register(wsa->dev, hw);
if (ret)
return ret;
return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
}
static const struct snd_soc_component_driver wsa_macro_component_drv = {
.name = "WSA MACRO",
.probe = wsa_macro_component_probe,
.controls = wsa_macro_snd_controls,
.num_controls = ARRAY_SIZE(wsa_macro_snd_controls),
.dapm_widgets = wsa_macro_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wsa_macro_dapm_widgets),
.dapm_routes = wsa_audio_map,
.num_dapm_routes = ARRAY_SIZE(wsa_audio_map),
};
static int wsa_macro_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct wsa_macro *wsa;
kernel_ulong_t flags;
void __iomem *base;
int ret;
flags = (kernel_ulong_t)device_get_match_data(dev);
wsa = devm_kzalloc(dev, sizeof(*wsa), GFP_KERNEL);
if (!wsa)
return -ENOMEM;
wsa->macro = devm_clk_get_optional(dev, "macro");
if (IS_ERR(wsa->macro))
return dev_err_probe(dev, PTR_ERR(wsa->macro), "unable to get macro clock\n");
wsa->dcodec = devm_clk_get_optional(dev, "dcodec");
if (IS_ERR(wsa->dcodec))
return dev_err_probe(dev, PTR_ERR(wsa->dcodec), "unable to get dcodec clock\n");
wsa->mclk = devm_clk_get(dev, "mclk");
if (IS_ERR(wsa->mclk))
return dev_err_probe(dev, PTR_ERR(wsa->mclk), "unable to get mclk clock\n");
if (flags & LPASS_MACRO_FLAG_HAS_NPL_CLOCK) {
wsa->npl = devm_clk_get(dev, "npl");
if (IS_ERR(wsa->npl))
return dev_err_probe(dev, PTR_ERR(wsa->npl), "unable to get npl clock\n");
}
wsa->fsgen = devm_clk_get(dev, "fsgen");
if (IS_ERR(wsa->fsgen))
return dev_err_probe(dev, PTR_ERR(wsa->fsgen), "unable to get fsgen clock\n");
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
wsa->regmap = devm_regmap_init_mmio(dev, base, &wsa_regmap_config);
if (IS_ERR(wsa->regmap))
return PTR_ERR(wsa->regmap);
dev_set_drvdata(dev, wsa);
wsa->dev = dev;
/* set MCLK and NPL rates */
clk_set_rate(wsa->mclk, WSA_MACRO_MCLK_FREQ);
clk_set_rate(wsa->npl, WSA_MACRO_MCLK_FREQ);
ret = clk_prepare_enable(wsa->macro);
if (ret)
goto err;
ret = clk_prepare_enable(wsa->dcodec);
if (ret)
goto err_dcodec;
ret = clk_prepare_enable(wsa->mclk);
if (ret)
goto err_mclk;
ret = clk_prepare_enable(wsa->npl);
if (ret)
goto err_npl;
ret = clk_prepare_enable(wsa->fsgen);
if (ret)
goto err_fsgen;
/* reset swr ip */
regmap_update_bits(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
CDC_WSA_SWR_RST_EN_MASK, CDC_WSA_SWR_RST_ENABLE);
regmap_update_bits(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
CDC_WSA_SWR_CLK_EN_MASK, CDC_WSA_SWR_CLK_ENABLE);
/* Bring out of reset */
regmap_update_bits(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
CDC_WSA_SWR_RST_EN_MASK, CDC_WSA_SWR_RST_DISABLE);
ret = devm_snd_soc_register_component(dev, &wsa_macro_component_drv,
wsa_macro_dai,
ARRAY_SIZE(wsa_macro_dai));
if (ret)
goto err_clkout;
pm_runtime_set_autosuspend_delay(dev, 3000);
pm_runtime_use_autosuspend(dev);
pm_runtime_mark_last_busy(dev);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
ret = wsa_macro_register_mclk_output(wsa);
if (ret)
goto err_clkout;
return 0;
err_clkout:
clk_disable_unprepare(wsa->fsgen);
err_fsgen:
clk_disable_unprepare(wsa->npl);
err_npl:
clk_disable_unprepare(wsa->mclk);
err_mclk:
clk_disable_unprepare(wsa->dcodec);
err_dcodec:
clk_disable_unprepare(wsa->macro);
err:
return ret;
}
static void wsa_macro_remove(struct platform_device *pdev)
{
struct wsa_macro *wsa = dev_get_drvdata(&pdev->dev);
clk_disable_unprepare(wsa->macro);
clk_disable_unprepare(wsa->dcodec);
clk_disable_unprepare(wsa->mclk);
clk_disable_unprepare(wsa->npl);
clk_disable_unprepare(wsa->fsgen);
}
static int __maybe_unused wsa_macro_runtime_suspend(struct device *dev)
{
struct wsa_macro *wsa = dev_get_drvdata(dev);
regcache_cache_only(wsa->regmap, true);
regcache_mark_dirty(wsa->regmap);
clk_disable_unprepare(wsa->fsgen);
clk_disable_unprepare(wsa->npl);
clk_disable_unprepare(wsa->mclk);
return 0;
}
static int __maybe_unused wsa_macro_runtime_resume(struct device *dev)
{
struct wsa_macro *wsa = dev_get_drvdata(dev);
int ret;
ret = clk_prepare_enable(wsa->mclk);
if (ret) {
dev_err(dev, "unable to prepare mclk\n");
return ret;
}
ret = clk_prepare_enable(wsa->npl);
if (ret) {
dev_err(dev, "unable to prepare mclkx2\n");
goto err_npl;
}
ret = clk_prepare_enable(wsa->fsgen);
if (ret) {
dev_err(dev, "unable to prepare fsgen\n");
goto err_fsgen;
}
regcache_cache_only(wsa->regmap, false);
regcache_sync(wsa->regmap);
return 0;
err_fsgen:
clk_disable_unprepare(wsa->npl);
err_npl:
clk_disable_unprepare(wsa->mclk);
return ret;
}
static const struct dev_pm_ops wsa_macro_pm_ops = {
SET_RUNTIME_PM_OPS(wsa_macro_runtime_suspend, wsa_macro_runtime_resume, NULL)
};
static const struct of_device_id wsa_macro_dt_match[] = {
{
.compatible = "qcom,sc7280-lpass-wsa-macro",
.data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
}, {
.compatible = "qcom,sm8250-lpass-wsa-macro",
.data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
}, {
.compatible = "qcom,sm8450-lpass-wsa-macro",
.data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
}, {
.compatible = "qcom,sm8550-lpass-wsa-macro",
}, {
.compatible = "qcom,sc8280xp-lpass-wsa-macro",
.data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
},
{}
};
MODULE_DEVICE_TABLE(of, wsa_macro_dt_match);
static struct platform_driver wsa_macro_driver = {
.driver = {
.name = "wsa_macro",
.of_match_table = wsa_macro_dt_match,
.pm = &wsa_macro_pm_ops,
},
.probe = wsa_macro_probe,
.remove_new = wsa_macro_remove,
};
module_platform_driver(wsa_macro_driver);
MODULE_DESCRIPTION("WSA macro driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/lpass-wsa-macro.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* MAX98504 ALSA SoC Audio driver
*
* Copyright 2013 - 2014 Maxim Integrated Products
* Copyright 2016 Samsung Electronics Co., Ltd.
*/
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <sound/soc.h>
#include "max98504.h"
static const char * const max98504_supply_names[] = {
"DVDD",
"DIOVDD",
"PVDD",
};
#define MAX98504_NUM_SUPPLIES ARRAY_SIZE(max98504_supply_names)
struct max98504_priv {
struct regmap *regmap;
struct regulator_bulk_data supplies[MAX98504_NUM_SUPPLIES];
unsigned int pcm_rx_channels;
bool brownout_enable;
unsigned int brownout_threshold;
unsigned int brownout_attenuation;
unsigned int brownout_attack_hold;
unsigned int brownout_timed_hold;
unsigned int brownout_release_rate;
};
static struct reg_default max98504_reg_defaults[] = {
{ 0x01, 0},
{ 0x02, 0},
{ 0x03, 0},
{ 0x04, 0},
{ 0x10, 0},
{ 0x11, 0},
{ 0x12, 0},
{ 0x13, 0},
{ 0x14, 0},
{ 0x15, 0},
{ 0x16, 0},
{ 0x17, 0},
{ 0x18, 0},
{ 0x19, 0},
{ 0x1A, 0},
{ 0x20, 0},
{ 0x21, 0},
{ 0x22, 0},
{ 0x23, 0},
{ 0x24, 0},
{ 0x25, 0},
{ 0x26, 0},
{ 0x27, 0},
{ 0x28, 0},
{ 0x30, 0},
{ 0x31, 0},
{ 0x32, 0},
{ 0x33, 0},
{ 0x34, 0},
{ 0x35, 0},
{ 0x36, 0},
{ 0x37, 0},
{ 0x38, 0},
{ 0x39, 0},
{ 0x40, 0},
{ 0x41, 0},
};
static bool max98504_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX98504_INTERRUPT_STATUS:
case MAX98504_INTERRUPT_FLAGS:
case MAX98504_INTERRUPT_FLAG_CLEARS:
case MAX98504_WATCHDOG_CLEAR:
case MAX98504_GLOBAL_ENABLE:
case MAX98504_SOFTWARE_RESET:
return true;
default:
return false;
}
}
static bool max98504_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX98504_SOFTWARE_RESET:
case MAX98504_WATCHDOG_CLEAR:
case MAX98504_INTERRUPT_FLAG_CLEARS:
return false;
default:
return true;
}
}
static int max98504_pcm_rx_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *c = snd_soc_dapm_to_component(w->dapm);
struct max98504_priv *max98504 = snd_soc_component_get_drvdata(c);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
regmap_write(max98504->regmap, MAX98504_PCM_RX_ENABLE,
max98504->pcm_rx_channels);
break;
case SND_SOC_DAPM_POST_PMD:
regmap_write(max98504->regmap, MAX98504_PCM_RX_ENABLE, 0);
break;
}
return 0;
}
static int max98504_component_probe(struct snd_soc_component *c)
{
struct max98504_priv *max98504 = snd_soc_component_get_drvdata(c);
struct regmap *map = max98504->regmap;
int ret;
ret = regulator_bulk_enable(MAX98504_NUM_SUPPLIES, max98504->supplies);
if (ret < 0)
return ret;
regmap_write(map, MAX98504_SOFTWARE_RESET, 0x1);
msleep(20);
if (!max98504->brownout_enable)
return 0;
regmap_write(map, MAX98504_PVDD_BROWNOUT_ENABLE, 0x1);
regmap_write(map, MAX98504_PVDD_BROWNOUT_CONFIG_1,
(max98504->brownout_threshold & 0x1f) << 3 |
(max98504->brownout_attenuation & 0x3));
regmap_write(map, MAX98504_PVDD_BROWNOUT_CONFIG_2,
max98504->brownout_attack_hold & 0xff);
regmap_write(map, MAX98504_PVDD_BROWNOUT_CONFIG_3,
max98504->brownout_timed_hold & 0xff);
regmap_write(map, MAX98504_PVDD_BROWNOUT_CONFIG_4,
max98504->brownout_release_rate & 0xff);
return 0;
}
static void max98504_component_remove(struct snd_soc_component *c)
{
struct max98504_priv *max98504 = snd_soc_component_get_drvdata(c);
regulator_bulk_disable(MAX98504_NUM_SUPPLIES, max98504->supplies);
}
static const char *spk_source_mux_text[] = {
"PCM Monomix", "Analog In", "PDM Left", "PDM Right"
};
static const struct soc_enum spk_source_mux_enum =
SOC_ENUM_SINGLE(MAX98504_SPEAKER_SOURCE_SELECT,
0, ARRAY_SIZE(spk_source_mux_text),
spk_source_mux_text);
static const struct snd_kcontrol_new spk_source_mux =
SOC_DAPM_ENUM("SPK Source", spk_source_mux_enum);
static const struct snd_soc_dapm_route max98504_dapm_routes[] = {
{ "SPKOUT", NULL, "Global Enable" },
{ "SPK Source", "PCM Monomix", "DAC PCM" },
{ "SPK Source", "Analog In", "AIN" },
{ "SPK Source", "PDM Left", "DAC PDM" },
{ "SPK Source", "PDM Right", "DAC PDM" },
};
static const struct snd_soc_dapm_widget max98504_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("Global Enable", MAX98504_GLOBAL_ENABLE,
0, 0, NULL, 0),
SND_SOC_DAPM_INPUT("AIN"),
SND_SOC_DAPM_AIF_OUT("AIF2OUTL", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF2OUTR", "AIF2 Capture", 1, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC_E("DAC PCM", NULL, SND_SOC_NOPM, 0, 0,
max98504_pcm_rx_ev,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_DAC("DAC PDM", NULL, MAX98504_PDM_RX_ENABLE, 0, 0),
SND_SOC_DAPM_MUX("SPK Source", SND_SOC_NOPM, 0, 0, &spk_source_mux),
SND_SOC_DAPM_REG(snd_soc_dapm_spk, "SPKOUT",
MAX98504_SPEAKER_ENABLE, 0, 1, 1, 0),
};
static int max98504_set_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask,
int slots, int slot_width)
{
struct max98504_priv *max98504 = snd_soc_dai_get_drvdata(dai);
struct regmap *map = max98504->regmap;
switch (dai->id) {
case MAX98504_DAI_ID_PCM:
regmap_write(map, MAX98504_PCM_TX_ENABLE, tx_mask);
max98504->pcm_rx_channels = rx_mask;
break;
case MAX98504_DAI_ID_PDM:
regmap_write(map, MAX98504_PDM_TX_ENABLE, tx_mask);
break;
default:
WARN_ON(1);
}
return 0;
}
static int max98504_set_channel_map(struct snd_soc_dai *dai,
unsigned int tx_num, unsigned int *tx_slot,
unsigned int rx_num, unsigned int *rx_slot)
{
struct max98504_priv *max98504 = snd_soc_dai_get_drvdata(dai);
struct regmap *map = max98504->regmap;
unsigned int i, sources = 0;
for (i = 0; i < tx_num; i++)
if (tx_slot[i])
sources |= (1 << i);
switch (dai->id) {
case MAX98504_DAI_ID_PCM:
regmap_write(map, MAX98504_PCM_TX_CHANNEL_SOURCES,
sources);
break;
case MAX98504_DAI_ID_PDM:
regmap_write(map, MAX98504_PDM_TX_CONTROL, sources);
break;
default:
WARN_ON(1);
}
regmap_write(map, MAX98504_MEASUREMENT_ENABLE, sources ? 0x3 : 0x01);
return 0;
}
static const struct snd_soc_dai_ops max98504_dai_ops = {
.set_tdm_slot = max98504_set_tdm_slot,
.set_channel_map = max98504_set_channel_map,
};
#define MAX98504_FORMATS (SNDRV_PCM_FMTBIT_S8|SNDRV_PCM_FMTBIT_S16_LE|\
SNDRV_PCM_FMTBIT_S24_LE|SNDRV_PCM_FMTBIT_S32_LE)
#define MAX98504_PDM_RATES (SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|\
SNDRV_PCM_RATE_32000|SNDRV_PCM_RATE_44100|\
SNDRV_PCM_RATE_48000|SNDRV_PCM_RATE_88200|\
SNDRV_PCM_RATE_96000)
static struct snd_soc_dai_driver max98504_dai[] = {
/* TODO: Add the PCM interface definitions */
{
.name = "max98504-aif2",
.id = MAX98504_DAI_ID_PDM,
.playback = {
.stream_name = "AIF2 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MAX98504_PDM_RATES,
.formats = MAX98504_FORMATS,
},
.capture = {
.stream_name = "AIF2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MAX98504_PDM_RATES,
.formats = MAX98504_FORMATS,
},
.ops = &max98504_dai_ops,
},
};
static const struct snd_soc_component_driver max98504_component_driver = {
.probe = max98504_component_probe,
.remove = max98504_component_remove,
.dapm_widgets = max98504_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(max98504_dapm_widgets),
.dapm_routes = max98504_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(max98504_dapm_routes),
.endianness = 1,
};
static const struct regmap_config max98504_regmap = {
.reg_bits = 16,
.val_bits = 8,
.max_register = MAX98504_MAX_REGISTER,
.reg_defaults = max98504_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(max98504_reg_defaults),
.volatile_reg = max98504_volatile_register,
.readable_reg = max98504_readable_register,
.cache_type = REGCACHE_RBTREE,
};
static int max98504_i2c_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct device_node *node = dev->of_node;
struct max98504_priv *max98504;
int i, ret;
max98504 = devm_kzalloc(dev, sizeof(*max98504), GFP_KERNEL);
if (!max98504)
return -ENOMEM;
if (node) {
if (!of_property_read_u32(node, "maxim,brownout-threshold",
&max98504->brownout_threshold))
max98504->brownout_enable = true;
of_property_read_u32(node, "maxim,brownout-attenuation",
&max98504->brownout_attenuation);
of_property_read_u32(node, "maxim,brownout-attack-hold-ms",
&max98504->brownout_attack_hold);
of_property_read_u32(node, "maxim,brownout-timed-hold-ms",
&max98504->brownout_timed_hold);
of_property_read_u32(node, "maxim,brownout-release-rate-ms",
&max98504->brownout_release_rate);
}
max98504->regmap = devm_regmap_init_i2c(client, &max98504_regmap);
if (IS_ERR(max98504->regmap)) {
ret = PTR_ERR(max98504->regmap);
dev_err(&client->dev, "regmap initialization failed: %d\n", ret);
return ret;
}
for (i = 0; i < MAX98504_NUM_SUPPLIES; i++)
max98504->supplies[i].supply = max98504_supply_names[i];
ret = devm_regulator_bulk_get(dev, MAX98504_NUM_SUPPLIES,
max98504->supplies);
if (ret < 0)
return ret;
i2c_set_clientdata(client, max98504);
return devm_snd_soc_register_component(dev, &max98504_component_driver,
max98504_dai, ARRAY_SIZE(max98504_dai));
}
#ifdef CONFIG_OF
static const struct of_device_id max98504_of_match[] = {
{ .compatible = "maxim,max98504" },
{ },
};
MODULE_DEVICE_TABLE(of, max98504_of_match);
#endif
static const struct i2c_device_id max98504_i2c_id[] = {
{ "max98504" },
{ }
};
MODULE_DEVICE_TABLE(i2c, max98504_i2c_id);
static struct i2c_driver max98504_i2c_driver = {
.driver = {
.name = "max98504",
.of_match_table = of_match_ptr(max98504_of_match),
},
.probe = max98504_i2c_probe,
.id_table = max98504_i2c_id,
};
module_i2c_driver(max98504_i2c_driver);
MODULE_DESCRIPTION("ASoC MAX98504 driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/max98504.c |
/*
* ASoC codec driver for spear platform
*
* sound/soc/codecs/sta529.c -- spear ALSA Soc codec driver
*
* Copyright (C) 2012 ST Microelectronics
* Rajeev Kumar <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/clk.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/pm.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/initval.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/tlv.h>
/* STA529 Register offsets */
#define STA529_FFXCFG0 0x00
#define STA529_FFXCFG1 0x01
#define STA529_MVOL 0x02
#define STA529_LVOL 0x03
#define STA529_RVOL 0x04
#define STA529_TTF0 0x05
#define STA529_TTF1 0x06
#define STA529_TTP0 0x07
#define STA529_TTP1 0x08
#define STA529_S2PCFG0 0x0A
#define STA529_S2PCFG1 0x0B
#define STA529_P2SCFG0 0x0C
#define STA529_P2SCFG1 0x0D
#define STA529_PLLCFG0 0x14
#define STA529_PLLCFG1 0x15
#define STA529_PLLCFG2 0x16
#define STA529_PLLCFG3 0x17
#define STA529_PLLPFE 0x18
#define STA529_PLLST 0x19
#define STA529_ADCCFG 0x1E /*mic_select*/
#define STA529_CKOCFG 0x1F
#define STA529_MISC 0x20
#define STA529_PADST0 0x21
#define STA529_PADST1 0x22
#define STA529_FFXST 0x23
#define STA529_PWMIN1 0x2D
#define STA529_PWMIN2 0x2E
#define STA529_POWST 0x32
#define STA529_MAX_REGISTER 0x32
#define STA529_RATES (SNDRV_PCM_RATE_8000 | \
SNDRV_PCM_RATE_11025 | \
SNDRV_PCM_RATE_16000 | \
SNDRV_PCM_RATE_22050 | \
SNDRV_PCM_RATE_32000 | \
SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000)
#define STA529_FORMAT (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE)
#define S2PC_VALUE 0x98
#define CLOCK_OUT 0x60
#define DATA_FORMAT_MSK 0x0E
#define LEFT_J_DATA_FORMAT 0x00
#define I2S_DATA_FORMAT 0x02
#define RIGHT_J_DATA_FORMAT 0x04
#define CODEC_MUTE_VAL 0x80
#define POWER_CNTLMSAK 0x40
#define POWER_STDBY 0x40
#define FFX_MASK 0x80
#define FFX_OFF 0x80
#define POWER_UP 0x00
#define FFX_CLK_ENB 0x01
#define FFX_CLK_DIS 0x00
#define FFX_CLK_MSK 0x01
#define PLAY_FREQ_RANGE_MSK 0x70
#define CAP_FREQ_RANGE_MSK 0x0C
#define PDATA_LEN_MSK 0xC0
#define BCLK_TO_FS_MSK 0x30
#define AUDIO_MUTE_MSK 0x80
static const struct reg_default sta529_reg_defaults[] = {
{ 0, 0x35 }, /* R0 - FFX Configuration reg 0 */
{ 1, 0xc8 }, /* R1 - FFX Configuration reg 1 */
{ 2, 0x50 }, /* R2 - Master Volume */
{ 3, 0x00 }, /* R3 - Left Volume */
{ 4, 0x00 }, /* R4 - Right Volume */
{ 10, 0xb2 }, /* R10 - S2P Config Reg 0 */
{ 11, 0x41 }, /* R11 - S2P Config Reg 1 */
{ 12, 0x92 }, /* R12 - P2S Config Reg 0 */
{ 13, 0x41 }, /* R13 - P2S Config Reg 1 */
{ 30, 0xd2 }, /* R30 - ADC Config Reg */
{ 31, 0x40 }, /* R31 - clock Out Reg */
{ 32, 0x21 }, /* R32 - Misc Register */
};
struct sta529 {
struct regmap *regmap;
};
static bool sta529_readable(struct device *dev, unsigned int reg)
{
switch (reg) {
case STA529_FFXCFG0:
case STA529_FFXCFG1:
case STA529_MVOL:
case STA529_LVOL:
case STA529_RVOL:
case STA529_S2PCFG0:
case STA529_S2PCFG1:
case STA529_P2SCFG0:
case STA529_P2SCFG1:
case STA529_ADCCFG:
case STA529_CKOCFG:
case STA529_MISC:
return true;
default:
return false;
}
}
static const char *pwm_mode_text[] = { "Binary", "Headphone", "Ternary",
"Phase-shift"};
static const DECLARE_TLV_DB_SCALE(out_gain_tlv, -9150, 50, 0);
static const DECLARE_TLV_DB_SCALE(master_vol_tlv, -12750, 50, 0);
static SOC_ENUM_SINGLE_DECL(pwm_src, STA529_FFXCFG1, 4, pwm_mode_text);
static const struct snd_kcontrol_new sta529_snd_controls[] = {
SOC_DOUBLE_R_TLV("Digital Playback Volume", STA529_LVOL, STA529_RVOL, 0,
127, 0, out_gain_tlv),
SOC_SINGLE_TLV("Master Playback Volume", STA529_MVOL, 0, 127, 1,
master_vol_tlv),
SOC_ENUM("PWM Select", pwm_src),
};
static int sta529_set_bias_level(struct snd_soc_component *component, enum
snd_soc_bias_level level)
{
struct sta529 *sta529 = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_ON:
case SND_SOC_BIAS_PREPARE:
snd_soc_component_update_bits(component, STA529_FFXCFG0, POWER_CNTLMSAK,
POWER_UP);
snd_soc_component_update_bits(component, STA529_MISC, FFX_CLK_MSK,
FFX_CLK_ENB);
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
regcache_sync(sta529->regmap);
snd_soc_component_update_bits(component, STA529_FFXCFG0,
POWER_CNTLMSAK, POWER_STDBY);
/* Making FFX output to zero */
snd_soc_component_update_bits(component, STA529_FFXCFG0, FFX_MASK,
FFX_OFF);
snd_soc_component_update_bits(component, STA529_MISC, FFX_CLK_MSK,
FFX_CLK_DIS);
break;
case SND_SOC_BIAS_OFF:
break;
}
return 0;
}
static int sta529_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
int pdata, play_freq_val, record_freq_val;
int bclk_to_fs_ratio;
switch (params_width(params)) {
case 16:
pdata = 1;
bclk_to_fs_ratio = 0;
break;
case 24:
pdata = 2;
bclk_to_fs_ratio = 1;
break;
case 32:
pdata = 3;
bclk_to_fs_ratio = 2;
break;
default:
dev_err(component->dev, "Unsupported format\n");
return -EINVAL;
}
switch (params_rate(params)) {
case 8000:
case 11025:
play_freq_val = 0;
record_freq_val = 2;
break;
case 16000:
case 22050:
play_freq_val = 1;
record_freq_val = 0;
break;
case 32000:
case 44100:
case 48000:
play_freq_val = 2;
record_freq_val = 0;
break;
default:
dev_err(component->dev, "Unsupported rate\n");
return -EINVAL;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
snd_soc_component_update_bits(component, STA529_S2PCFG1, PDATA_LEN_MSK,
pdata << 6);
snd_soc_component_update_bits(component, STA529_S2PCFG1, BCLK_TO_FS_MSK,
bclk_to_fs_ratio << 4);
snd_soc_component_update_bits(component, STA529_MISC, PLAY_FREQ_RANGE_MSK,
play_freq_val << 4);
} else {
snd_soc_component_update_bits(component, STA529_P2SCFG1, PDATA_LEN_MSK,
pdata << 6);
snd_soc_component_update_bits(component, STA529_P2SCFG1, BCLK_TO_FS_MSK,
bclk_to_fs_ratio << 4);
snd_soc_component_update_bits(component, STA529_MISC, CAP_FREQ_RANGE_MSK,
record_freq_val << 2);
}
return 0;
}
static int sta529_mute(struct snd_soc_dai *dai, int mute, int direction)
{
u8 val = 0;
if (mute)
val |= CODEC_MUTE_VAL;
snd_soc_component_update_bits(dai->component, STA529_FFXCFG0, AUDIO_MUTE_MSK, val);
return 0;
}
static int sta529_set_dai_fmt(struct snd_soc_dai *codec_dai, u32 fmt)
{
struct snd_soc_component *component = codec_dai->component;
u8 mode = 0;
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_LEFT_J:
mode = LEFT_J_DATA_FORMAT;
break;
case SND_SOC_DAIFMT_I2S:
mode = I2S_DATA_FORMAT;
break;
case SND_SOC_DAIFMT_RIGHT_J:
mode = RIGHT_J_DATA_FORMAT;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, STA529_S2PCFG0, DATA_FORMAT_MSK, mode);
return 0;
}
static const struct snd_soc_dai_ops sta529_dai_ops = {
.hw_params = sta529_hw_params,
.set_fmt = sta529_set_dai_fmt,
.mute_stream = sta529_mute,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver sta529_dai = {
.name = "sta529-audio",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = STA529_RATES,
.formats = STA529_FORMAT,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = STA529_RATES,
.formats = STA529_FORMAT,
},
.ops = &sta529_dai_ops,
};
static const struct snd_soc_component_driver sta529_component_driver = {
.set_bias_level = sta529_set_bias_level,
.controls = sta529_snd_controls,
.num_controls = ARRAY_SIZE(sta529_snd_controls),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config sta529_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = STA529_MAX_REGISTER,
.readable_reg = sta529_readable,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = sta529_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(sta529_reg_defaults),
};
static int sta529_i2c_probe(struct i2c_client *i2c)
{
struct sta529 *sta529;
int ret;
sta529 = devm_kzalloc(&i2c->dev, sizeof(struct sta529), GFP_KERNEL);
if (!sta529)
return -ENOMEM;
sta529->regmap = devm_regmap_init_i2c(i2c, &sta529_regmap);
if (IS_ERR(sta529->regmap)) {
ret = PTR_ERR(sta529->regmap);
dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
return ret;
}
i2c_set_clientdata(i2c, sta529);
ret = devm_snd_soc_register_component(&i2c->dev,
&sta529_component_driver, &sta529_dai, 1);
if (ret != 0)
dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
return ret;
}
static const struct i2c_device_id sta529_i2c_id[] = {
{ "sta529", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, sta529_i2c_id);
static const struct of_device_id sta529_of_match[] = {
{ .compatible = "st,sta529", },
{ }
};
MODULE_DEVICE_TABLE(of, sta529_of_match);
static struct i2c_driver sta529_i2c_driver = {
.driver = {
.name = "sta529",
.of_match_table = sta529_of_match,
},
.probe = sta529_i2c_probe,
.id_table = sta529_i2c_id,
};
module_i2c_driver(sta529_i2c_driver);
MODULE_DESCRIPTION("ASoC STA529 codec driver");
MODULE_AUTHOR("Rajeev Kumar <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/sta529.c |
// SPDX-License-Identifier: GPL-2.0
// Audio driver for PCM1789 I2C
// Copyright (C) 2018 Bootlin
// Mylène Josserand <[email protected]>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include "pcm1789.h"
static int pcm1789_i2c_probe(struct i2c_client *client)
{
struct regmap *regmap;
int ret;
regmap = devm_regmap_init_i2c(client, &pcm1789_regmap_config);
if (IS_ERR(regmap)) {
ret = PTR_ERR(regmap);
dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret);
return ret;
}
return pcm1789_common_init(&client->dev, regmap);
}
static void pcm1789_i2c_remove(struct i2c_client *client)
{
pcm1789_common_exit(&client->dev);
}
#ifdef CONFIG_OF
static const struct of_device_id pcm1789_of_match[] = {
{ .compatible = "ti,pcm1789", },
{ }
};
MODULE_DEVICE_TABLE(of, pcm1789_of_match);
#endif
static const struct i2c_device_id pcm1789_i2c_ids[] = {
{ "pcm1789", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, pcm1789_i2c_ids);
static struct i2c_driver pcm1789_i2c_driver = {
.driver = {
.name = "pcm1789",
.of_match_table = of_match_ptr(pcm1789_of_match),
},
.id_table = pcm1789_i2c_ids,
.probe = pcm1789_i2c_probe,
.remove = pcm1789_i2c_remove,
};
module_i2c_driver(pcm1789_i2c_driver);
MODULE_DESCRIPTION("ASoC PCM1789 I2C driver");
MODULE_AUTHOR("Mylène Josserand <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/pcm1789-i2c.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* rt286.c -- RT286 ALSA SoC audio codec driver
*
* Copyright 2013 Realtek Semiconductor Corp.
* Author: Bard Liao <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/dmi.h>
#include <linux/acpi.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/jack.h>
#include <linux/workqueue.h>
#include <sound/rt286.h>
#include "rl6347a.h"
#include "rt286.h"
#define RT286_VENDOR_ID 0x10ec0286
#define RT288_VENDOR_ID 0x10ec0288
struct rt286_priv {
struct reg_default *index_cache;
int index_cache_size;
struct regmap *regmap;
struct snd_soc_component *component;
struct rt286_platform_data pdata;
struct i2c_client *i2c;
struct snd_soc_jack *jack;
struct delayed_work jack_detect_work;
int sys_clk;
int clk_id;
};
static const struct reg_default rt286_index_def[] = {
{ 0x01, 0xaaaa },
{ 0x02, 0x8aaa },
{ 0x03, 0x0002 },
{ 0x04, 0xaf01 },
{ 0x08, 0x000d },
{ 0x09, 0xd810 },
{ 0x0a, 0x0120 },
{ 0x0b, 0x0000 },
{ 0x0d, 0x2800 },
{ 0x0f, 0x0000 },
{ 0x19, 0x0a17 },
{ 0x20, 0x0020 },
{ 0x33, 0x0208 },
{ 0x49, 0x0004 },
{ 0x4f, 0x50e9 },
{ 0x50, 0x2000 },
{ 0x63, 0x2902 },
{ 0x67, 0x1111 },
{ 0x68, 0x1016 },
{ 0x69, 0x273f },
};
#define INDEX_CACHE_SIZE ARRAY_SIZE(rt286_index_def)
static const struct reg_default rt286_reg[] = {
{ 0x00170500, 0x00000400 },
{ 0x00220000, 0x00000031 },
{ 0x00239000, 0x0000007f },
{ 0x0023a000, 0x0000007f },
{ 0x00270500, 0x00000400 },
{ 0x00370500, 0x00000400 },
{ 0x00870500, 0x00000400 },
{ 0x00920000, 0x00000031 },
{ 0x00935000, 0x000000c3 },
{ 0x00936000, 0x000000c3 },
{ 0x00970500, 0x00000400 },
{ 0x00b37000, 0x00000097 },
{ 0x00b37200, 0x00000097 },
{ 0x00b37300, 0x00000097 },
{ 0x00c37000, 0x00000000 },
{ 0x00c37100, 0x00000080 },
{ 0x01270500, 0x00000400 },
{ 0x01370500, 0x00000400 },
{ 0x01371f00, 0x411111f0 },
{ 0x01439000, 0x00000080 },
{ 0x0143a000, 0x00000080 },
{ 0x01470700, 0x00000000 },
{ 0x01470500, 0x00000400 },
{ 0x01470c00, 0x00000000 },
{ 0x01470100, 0x00000000 },
{ 0x01837000, 0x00000000 },
{ 0x01870500, 0x00000400 },
{ 0x02050000, 0x00000000 },
{ 0x02139000, 0x00000080 },
{ 0x0213a000, 0x00000080 },
{ 0x02170100, 0x00000000 },
{ 0x02170500, 0x00000400 },
{ 0x02170700, 0x00000000 },
{ 0x02270100, 0x00000000 },
{ 0x02370100, 0x00000000 },
{ 0x01870700, 0x00000020 },
{ 0x00830000, 0x000000c3 },
{ 0x00930000, 0x000000c3 },
{ 0x01270700, 0x00000000 },
};
static bool rt286_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0 ... 0xff:
case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
case RT286_GET_HP_SENSE:
case RT286_GET_MIC1_SENSE:
case RT286_PROC_COEF:
return true;
default:
return false;
}
}
static bool rt286_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0 ... 0xff:
case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
case RT286_GET_HP_SENSE:
case RT286_GET_MIC1_SENSE:
case RT286_SET_AUDIO_POWER:
case RT286_SET_HPO_POWER:
case RT286_SET_SPK_POWER:
case RT286_SET_DMIC1_POWER:
case RT286_SPK_MUX:
case RT286_HPO_MUX:
case RT286_ADC0_MUX:
case RT286_ADC1_MUX:
case RT286_SET_MIC1:
case RT286_SET_PIN_HPO:
case RT286_SET_PIN_SPK:
case RT286_SET_PIN_DMIC1:
case RT286_SPK_EAPD:
case RT286_SET_AMP_GAIN_HPO:
case RT286_SET_DMIC2_DEFAULT:
case RT286_DACL_GAIN:
case RT286_DACR_GAIN:
case RT286_ADCL_GAIN:
case RT286_ADCR_GAIN:
case RT286_MIC_GAIN:
case RT286_SPOL_GAIN:
case RT286_SPOR_GAIN:
case RT286_HPOL_GAIN:
case RT286_HPOR_GAIN:
case RT286_F_DAC_SWITCH:
case RT286_F_RECMIX_SWITCH:
case RT286_REC_MIC_SWITCH:
case RT286_REC_I2S_SWITCH:
case RT286_REC_LINE_SWITCH:
case RT286_REC_BEEP_SWITCH:
case RT286_DAC_FORMAT:
case RT286_ADC_FORMAT:
case RT286_COEF_INDEX:
case RT286_PROC_COEF:
case RT286_SET_AMP_GAIN_ADC_IN1:
case RT286_SET_AMP_GAIN_ADC_IN2:
case RT286_SET_GPIO_MASK:
case RT286_SET_GPIO_DIRECTION:
case RT286_SET_GPIO_DATA:
case RT286_SET_POWER(RT286_DAC_OUT1):
case RT286_SET_POWER(RT286_DAC_OUT2):
case RT286_SET_POWER(RT286_ADC_IN1):
case RT286_SET_POWER(RT286_ADC_IN2):
case RT286_SET_POWER(RT286_DMIC2):
case RT286_SET_POWER(RT286_MIC1):
return true;
default:
return false;
}
}
#ifdef CONFIG_PM
static void rt286_index_sync(struct snd_soc_component *component)
{
struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
int i;
for (i = 0; i < INDEX_CACHE_SIZE; i++) {
snd_soc_component_write(component, rt286->index_cache[i].reg,
rt286->index_cache[i].def);
}
}
#endif
static int rt286_support_power_controls[] = {
RT286_DAC_OUT1,
RT286_DAC_OUT2,
RT286_ADC_IN1,
RT286_ADC_IN2,
RT286_MIC1,
RT286_DMIC1,
RT286_DMIC2,
RT286_SPK_OUT,
RT286_HP_OUT,
};
#define RT286_POWER_REG_LEN ARRAY_SIZE(rt286_support_power_controls)
static int rt286_jack_detect(struct rt286_priv *rt286, bool *hp, bool *mic)
{
struct snd_soc_dapm_context *dapm;
unsigned int val, buf;
*hp = false;
*mic = false;
if (!rt286->component)
return -EINVAL;
dapm = snd_soc_component_get_dapm(rt286->component);
if (rt286->pdata.cbj_en) {
regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
*hp = buf & 0x80000000;
if (*hp) {
/* power on HV,VERF */
regmap_update_bits(rt286->regmap,
RT286_DC_GAIN, 0x200, 0x200);
snd_soc_dapm_force_enable_pin(dapm, "HV");
snd_soc_dapm_force_enable_pin(dapm, "VREF");
/* power LDO1 */
snd_soc_dapm_force_enable_pin(dapm, "LDO1");
snd_soc_dapm_sync(dapm);
regmap_write(rt286->regmap, RT286_SET_MIC1, 0x24);
msleep(50);
regmap_update_bits(rt286->regmap,
RT286_CBJ_CTRL1, 0xfcc0, 0xd400);
msleep(300);
regmap_read(rt286->regmap, RT286_CBJ_CTRL2, &val);
if (0x0070 == (val & 0x0070)) {
*mic = true;
} else {
regmap_update_bits(rt286->regmap,
RT286_CBJ_CTRL1, 0xfcc0, 0xe400);
msleep(300);
regmap_read(rt286->regmap,
RT286_CBJ_CTRL2, &val);
if (0x0070 == (val & 0x0070)) {
*mic = true;
} else {
*mic = false;
regmap_update_bits(rt286->regmap,
RT286_CBJ_CTRL1,
0xfcc0, 0xc400);
}
}
regmap_update_bits(rt286->regmap,
RT286_DC_GAIN, 0x200, 0x0);
} else {
*mic = false;
regmap_write(rt286->regmap, RT286_SET_MIC1, 0x20);
regmap_update_bits(rt286->regmap,
RT286_CBJ_CTRL1, 0x0400, 0x0000);
}
} else {
regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
*hp = buf & 0x80000000;
regmap_read(rt286->regmap, RT286_GET_MIC1_SENSE, &buf);
*mic = buf & 0x80000000;
}
if (!*hp) {
snd_soc_dapm_disable_pin(dapm, "HV");
snd_soc_dapm_disable_pin(dapm, "VREF");
snd_soc_dapm_disable_pin(dapm, "LDO1");
snd_soc_dapm_sync(dapm);
}
return 0;
}
static void rt286_jack_detect_work(struct work_struct *work)
{
struct rt286_priv *rt286 =
container_of(work, struct rt286_priv, jack_detect_work.work);
int status = 0;
bool hp = false;
bool mic = false;
rt286_jack_detect(rt286, &hp, &mic);
if (hp)
status |= SND_JACK_HEADPHONE;
if (mic)
status |= SND_JACK_MICROPHONE;
snd_soc_jack_report(rt286->jack, status,
SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
}
static int rt286_mic_detect(struct snd_soc_component *component,
struct snd_soc_jack *jack, void *data)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
rt286->jack = jack;
if (jack) {
/* enable IRQ */
if (rt286->jack->status & SND_JACK_HEADPHONE)
snd_soc_dapm_force_enable_pin(dapm, "LDO1");
regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x2, 0x2);
/* Send an initial empty report */
snd_soc_jack_report(rt286->jack, rt286->jack->status,
SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
} else {
/* disable IRQ */
regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x2, 0x0);
snd_soc_dapm_disable_pin(dapm, "LDO1");
}
snd_soc_dapm_sync(dapm);
return 0;
}
static int is_mclk_mode(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
if (rt286->clk_id == RT286_SCLK_S_MCLK)
return 1;
else
return 0;
}
static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0);
static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
static const struct snd_kcontrol_new rt286_snd_controls[] = {
SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT286_DACL_GAIN,
RT286_DACR_GAIN, 0, 0x7f, 0, out_vol_tlv),
SOC_DOUBLE_R("ADC0 Capture Switch", RT286_ADCL_GAIN,
RT286_ADCR_GAIN, 7, 1, 1),
SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT286_ADCL_GAIN,
RT286_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv),
SOC_SINGLE_TLV("AMIC Volume", RT286_MIC_GAIN,
0, 0x3, 0, mic_vol_tlv),
SOC_DOUBLE_R("Speaker Playback Switch", RT286_SPOL_GAIN,
RT286_SPOR_GAIN, RT286_MUTE_SFT, 1, 1),
};
/* Digital Mixer */
static const struct snd_kcontrol_new rt286_front_mix[] = {
SOC_DAPM_SINGLE("DAC Switch", RT286_F_DAC_SWITCH,
RT286_MUTE_SFT, 1, 1),
SOC_DAPM_SINGLE("RECMIX Switch", RT286_F_RECMIX_SWITCH,
RT286_MUTE_SFT, 1, 1),
};
/* Analog Input Mixer */
static const struct snd_kcontrol_new rt286_rec_mix[] = {
SOC_DAPM_SINGLE("Mic1 Switch", RT286_REC_MIC_SWITCH,
RT286_MUTE_SFT, 1, 1),
SOC_DAPM_SINGLE("I2S Switch", RT286_REC_I2S_SWITCH,
RT286_MUTE_SFT, 1, 1),
SOC_DAPM_SINGLE("Line1 Switch", RT286_REC_LINE_SWITCH,
RT286_MUTE_SFT, 1, 1),
SOC_DAPM_SINGLE("Beep Switch", RT286_REC_BEEP_SWITCH,
RT286_MUTE_SFT, 1, 1),
};
static const struct snd_kcontrol_new spo_enable_control =
SOC_DAPM_SINGLE("Switch", RT286_SET_PIN_SPK,
RT286_SET_PIN_SFT, 1, 0);
static const struct snd_kcontrol_new hpol_enable_control =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOL_GAIN,
RT286_MUTE_SFT, 1, 1);
static const struct snd_kcontrol_new hpor_enable_control =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOR_GAIN,
RT286_MUTE_SFT, 1, 1);
/* ADC0 source */
static const char * const rt286_adc_src[] = {
"Mic", "RECMIX", "Dmic"
};
static const int rt286_adc_values[] = {
0, 4, 5,
};
static SOC_VALUE_ENUM_SINGLE_DECL(
rt286_adc0_enum, RT286_ADC0_MUX, RT286_ADC_SEL_SFT,
RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
static const struct snd_kcontrol_new rt286_adc0_mux =
SOC_DAPM_ENUM("ADC 0 source", rt286_adc0_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(
rt286_adc1_enum, RT286_ADC1_MUX, RT286_ADC_SEL_SFT,
RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
static const struct snd_kcontrol_new rt286_adc1_mux =
SOC_DAPM_ENUM("ADC 1 source", rt286_adc1_enum);
static const char * const rt286_dac_src[] = {
"Front", "Surround"
};
/* HP-OUT source */
static SOC_ENUM_SINGLE_DECL(rt286_hpo_enum, RT286_HPO_MUX,
0, rt286_dac_src);
static const struct snd_kcontrol_new rt286_hpo_mux =
SOC_DAPM_ENUM("HPO source", rt286_hpo_enum);
/* SPK-OUT source */
static SOC_ENUM_SINGLE_DECL(rt286_spo_enum, RT286_SPK_MUX,
0, rt286_dac_src);
static const struct snd_kcontrol_new rt286_spo_mux =
SOC_DAPM_ENUM("SPO source", rt286_spo_enum);
static int rt286_spk_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_write(component,
RT286_SPK_EAPD, RT286_SET_EAPD_HIGH);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_write(component,
RT286_SPK_EAPD, RT286_SET_EAPD_LOW);
break;
default:
return 0;
}
return 0;
}
static int rt286_set_dmic1_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_write(component, RT286_SET_PIN_DMIC1, 0x20);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_write(component, RT286_SET_PIN_DMIC1, 0);
break;
default:
return 0;
}
return 0;
}
static int rt286_ldo2_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(component, RT286_POWER_CTRL2, 0x38, 0x08);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, RT286_POWER_CTRL2, 0x38, 0x30);
break;
default:
return 0;
}
return 0;
}
static int rt286_mic1_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_component_update_bits(component,
RT286_A_BIAS_CTRL3, 0xc000, 0x8000);
snd_soc_component_update_bits(component,
RT286_A_BIAS_CTRL2, 0xc000, 0x8000);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component,
RT286_A_BIAS_CTRL3, 0xc000, 0x0000);
snd_soc_component_update_bits(component,
RT286_A_BIAS_CTRL2, 0xc000, 0x0000);
break;
default:
return 0;
}
return 0;
}
static const struct snd_soc_dapm_widget rt286_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY_S("HV", 1, RT286_POWER_CTRL1,
12, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("VREF", RT286_POWER_CTRL1,
0, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("LDO1", 1, RT286_POWER_CTRL2,
2, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("LDO2", 2, RT286_POWER_CTRL1,
13, 1, rt286_ldo2_event, SND_SOC_DAPM_PRE_PMD |
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY("MCLK MODE", RT286_PLL_CTRL1,
5, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MIC1 Input Buffer", SND_SOC_NOPM,
0, 0, rt286_mic1_event, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMD),
/* Input Lines */
SND_SOC_DAPM_INPUT("DMIC1 Pin"),
SND_SOC_DAPM_INPUT("DMIC2 Pin"),
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_INPUT("LINE1"),
SND_SOC_DAPM_INPUT("Beep"),
/* DMIC */
SND_SOC_DAPM_PGA_E("DMIC1", RT286_SET_POWER(RT286_DMIC1), 0, 1,
NULL, 0, rt286_set_dmic1_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA("DMIC2", RT286_SET_POWER(RT286_DMIC2), 0, 1,
NULL, 0),
SND_SOC_DAPM_SUPPLY("DMIC Receiver", SND_SOC_NOPM,
0, 0, NULL, 0),
/* REC Mixer */
SND_SOC_DAPM_MIXER("RECMIX", SND_SOC_NOPM, 0, 0,
rt286_rec_mix, ARRAY_SIZE(rt286_rec_mix)),
/* ADCs */
SND_SOC_DAPM_ADC("ADC 0", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0),
/* ADC Mux */
SND_SOC_DAPM_MUX("ADC 0 Mux", RT286_SET_POWER(RT286_ADC_IN1), 0, 1,
&rt286_adc0_mux),
SND_SOC_DAPM_MUX("ADC 1 Mux", RT286_SET_POWER(RT286_ADC_IN2), 0, 1,
&rt286_adc1_mux),
/* Audio Interface */
SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
/* Output Side */
/* DACs */
SND_SOC_DAPM_DAC("DAC 0", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DAC 1", NULL, SND_SOC_NOPM, 0, 0),
/* Output Mux */
SND_SOC_DAPM_MUX("SPK Mux", SND_SOC_NOPM, 0, 0, &rt286_spo_mux),
SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt286_hpo_mux),
SND_SOC_DAPM_SUPPLY("HP Power", RT286_SET_PIN_HPO,
RT286_SET_PIN_SFT, 0, NULL, 0),
/* Output Mixer */
SND_SOC_DAPM_MIXER("Front", RT286_SET_POWER(RT286_DAC_OUT1), 0, 1,
rt286_front_mix, ARRAY_SIZE(rt286_front_mix)),
SND_SOC_DAPM_PGA("Surround", RT286_SET_POWER(RT286_DAC_OUT2), 0, 1,
NULL, 0),
/* Output Pga */
SND_SOC_DAPM_SWITCH_E("SPO", SND_SOC_NOPM, 0, 0,
&spo_enable_control, rt286_spk_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0,
&hpol_enable_control),
SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0,
&hpor_enable_control),
/* Output Lines */
SND_SOC_DAPM_OUTPUT("SPOL"),
SND_SOC_DAPM_OUTPUT("SPOR"),
SND_SOC_DAPM_OUTPUT("HPO Pin"),
SND_SOC_DAPM_OUTPUT("SPDIF"),
};
static const struct snd_soc_dapm_route rt286_dapm_routes[] = {
{"ADC 0", NULL, "MCLK MODE", is_mclk_mode},
{"ADC 1", NULL, "MCLK MODE", is_mclk_mode},
{"Front", NULL, "MCLK MODE", is_mclk_mode},
{"Surround", NULL, "MCLK MODE", is_mclk_mode},
{"HP Power", NULL, "LDO1"},
{"HP Power", NULL, "LDO2"},
{"MIC1", NULL, "LDO1"},
{"MIC1", NULL, "LDO2"},
{"MIC1", NULL, "HV"},
{"MIC1", NULL, "VREF"},
{"MIC1", NULL, "MIC1 Input Buffer"},
{"SPO", NULL, "LDO1"},
{"SPO", NULL, "LDO2"},
{"SPO", NULL, "HV"},
{"SPO", NULL, "VREF"},
{"DMIC1", NULL, "DMIC1 Pin"},
{"DMIC2", NULL, "DMIC2 Pin"},
{"DMIC1", NULL, "DMIC Receiver"},
{"DMIC2", NULL, "DMIC Receiver"},
{"RECMIX", "Beep Switch", "Beep"},
{"RECMIX", "Line1 Switch", "LINE1"},
{"RECMIX", "Mic1 Switch", "MIC1"},
{"ADC 0 Mux", "Dmic", "DMIC1"},
{"ADC 0 Mux", "RECMIX", "RECMIX"},
{"ADC 0 Mux", "Mic", "MIC1"},
{"ADC 1 Mux", "Dmic", "DMIC2"},
{"ADC 1 Mux", "RECMIX", "RECMIX"},
{"ADC 1 Mux", "Mic", "MIC1"},
{"ADC 0", NULL, "ADC 0 Mux"},
{"ADC 1", NULL, "ADC 1 Mux"},
{"AIF1TX", NULL, "ADC 0"},
{"AIF2TX", NULL, "ADC 1"},
{"DAC 0", NULL, "AIF1RX"},
{"DAC 1", NULL, "AIF2RX"},
{"Front", "DAC Switch", "DAC 0"},
{"Front", "RECMIX Switch", "RECMIX"},
{"Surround", NULL, "DAC 1"},
{"SPK Mux", "Front", "Front"},
{"SPK Mux", "Surround", "Surround"},
{"HPO Mux", "Front", "Front"},
{"HPO Mux", "Surround", "Surround"},
{"SPO", "Switch", "SPK Mux"},
{"HPO L", "Switch", "HPO Mux"},
{"HPO R", "Switch", "HPO Mux"},
{"HPO L", NULL, "HP Power"},
{"HPO R", NULL, "HP Power"},
{"SPOL", NULL, "SPO"},
{"SPOR", NULL, "SPO"},
{"HPO Pin", NULL, "HPO L"},
{"HPO Pin", NULL, "HPO R"},
};
static int rt286_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
unsigned int val = 0;
int d_len_code;
switch (params_rate(params)) {
/* bit 14 0:48K 1:44.1K */
case 44100:
val |= 0x4000;
break;
case 48000:
break;
default:
dev_err(component->dev, "Unsupported sample rate %d\n",
params_rate(params));
return -EINVAL;
}
switch (rt286->sys_clk) {
case 12288000:
case 24576000:
if (params_rate(params) != 48000) {
dev_err(component->dev, "Sys_clk is not matched (%d %d)\n",
params_rate(params), rt286->sys_clk);
return -EINVAL;
}
break;
case 11289600:
case 22579200:
if (params_rate(params) != 44100) {
dev_err(component->dev, "Sys_clk is not matched (%d %d)\n",
params_rate(params), rt286->sys_clk);
return -EINVAL;
}
break;
}
if (params_channels(params) <= 16) {
/* bit 3:0 Number of Channel */
val |= (params_channels(params) - 1);
} else {
dev_err(component->dev, "Unsupported channels %d\n",
params_channels(params));
return -EINVAL;
}
switch (params_width(params)) {
/* bit 6:4 Bits per Sample */
case 16:
d_len_code = 0;
val |= (0x1 << 4);
break;
case 32:
d_len_code = 2;
val |= (0x4 << 4);
break;
case 20:
d_len_code = 1;
val |= (0x2 << 4);
break;
case 24:
d_len_code = 2;
val |= (0x3 << 4);
break;
case 8:
d_len_code = 3;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component,
RT286_I2S_CTRL1, 0x0018, d_len_code << 3);
dev_dbg(component->dev, "format val = 0x%x\n", val);
snd_soc_component_update_bits(component, RT286_DAC_FORMAT, 0x407f, val);
snd_soc_component_update_bits(component, RT286_ADC_FORMAT, 0x407f, val);
return 0;
}
static int rt286_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
snd_soc_component_update_bits(component,
RT286_I2S_CTRL1, 0x800, 0x800);
break;
case SND_SOC_DAIFMT_CBS_CFS:
snd_soc_component_update_bits(component,
RT286_I2S_CTRL1, 0x800, 0x0);
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
snd_soc_component_update_bits(component,
RT286_I2S_CTRL1, 0x300, 0x0);
break;
case SND_SOC_DAIFMT_LEFT_J:
snd_soc_component_update_bits(component,
RT286_I2S_CTRL1, 0x300, 0x1 << 8);
break;
case SND_SOC_DAIFMT_DSP_A:
snd_soc_component_update_bits(component,
RT286_I2S_CTRL1, 0x300, 0x2 << 8);
break;
case SND_SOC_DAIFMT_DSP_B:
snd_soc_component_update_bits(component,
RT286_I2S_CTRL1, 0x300, 0x3 << 8);
break;
default:
return -EINVAL;
}
/* bit 15 Stream Type 0:PCM 1:Non-PCM */
snd_soc_component_update_bits(component, RT286_DAC_FORMAT, 0x8000, 0);
snd_soc_component_update_bits(component, RT286_ADC_FORMAT, 0x8000, 0);
return 0;
}
static int rt286_set_dai_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
dev_dbg(component->dev, "%s freq=%d\n", __func__, freq);
if (RT286_SCLK_S_MCLK == clk_id) {
snd_soc_component_update_bits(component,
RT286_I2S_CTRL2, 0x0100, 0x0);
snd_soc_component_update_bits(component,
RT286_PLL_CTRL1, 0x20, 0x20);
} else {
snd_soc_component_update_bits(component,
RT286_I2S_CTRL2, 0x0100, 0x0100);
snd_soc_component_update_bits(component,
RT286_PLL_CTRL, 0x4, 0x4);
snd_soc_component_update_bits(component,
RT286_PLL_CTRL1, 0x20, 0x0);
}
switch (freq) {
case 19200000:
if (RT286_SCLK_S_MCLK == clk_id) {
dev_err(component->dev, "Should not use MCLK\n");
return -EINVAL;
}
snd_soc_component_update_bits(component,
RT286_I2S_CTRL2, 0x40, 0x40);
break;
case 24000000:
if (RT286_SCLK_S_MCLK == clk_id) {
dev_err(component->dev, "Should not use MCLK\n");
return -EINVAL;
}
snd_soc_component_update_bits(component,
RT286_I2S_CTRL2, 0x40, 0x0);
break;
case 12288000:
case 11289600:
snd_soc_component_update_bits(component,
RT286_I2S_CTRL2, 0x8, 0x0);
snd_soc_component_update_bits(component,
RT286_CLK_DIV, 0xfc1e, 0x0004);
break;
case 24576000:
case 22579200:
snd_soc_component_update_bits(component,
RT286_I2S_CTRL2, 0x8, 0x8);
snd_soc_component_update_bits(component,
RT286_CLK_DIV, 0xfc1e, 0x5406);
break;
default:
dev_err(component->dev, "Unsupported system clock\n");
return -EINVAL;
}
rt286->sys_clk = freq;
rt286->clk_id = clk_id;
return 0;
}
static int rt286_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
{
struct snd_soc_component *component = dai->component;
dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio);
if (50 == ratio)
snd_soc_component_update_bits(component,
RT286_I2S_CTRL1, 0x1000, 0x1000);
else
snd_soc_component_update_bits(component,
RT286_I2S_CTRL1, 0x1000, 0x0);
return 0;
}
static int rt286_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
switch (level) {
case SND_SOC_BIAS_PREPARE:
if (SND_SOC_BIAS_STANDBY == snd_soc_component_get_bias_level(component)) {
snd_soc_component_write(component,
RT286_SET_AUDIO_POWER, AC_PWRST_D0);
snd_soc_component_update_bits(component,
RT286_DC_GAIN, 0x200, 0x200);
}
break;
case SND_SOC_BIAS_ON:
mdelay(10);
snd_soc_component_update_bits(component,
RT286_DC_GAIN, 0x200, 0x0);
break;
case SND_SOC_BIAS_STANDBY:
snd_soc_component_write(component,
RT286_SET_AUDIO_POWER, AC_PWRST_D3);
break;
default:
break;
}
return 0;
}
static irqreturn_t rt286_irq(int irq, void *data)
{
struct rt286_priv *rt286 = data;
bool hp = false;
bool mic = false;
int status = 0;
rt286_jack_detect(rt286, &hp, &mic);
/* Clear IRQ */
regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x1, 0x1);
if (hp)
status |= SND_JACK_HEADPHONE;
if (mic)
status |= SND_JACK_MICROPHONE;
snd_soc_jack_report(rt286->jack, status,
SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
pm_wakeup_event(&rt286->i2c->dev, 300);
return IRQ_HANDLED;
}
static int rt286_probe(struct snd_soc_component *component)
{
struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
rt286->component = component;
INIT_DELAYED_WORK(&rt286->jack_detect_work, rt286_jack_detect_work);
if (rt286->i2c->irq)
schedule_delayed_work(&rt286->jack_detect_work,
msecs_to_jiffies(50));
return 0;
}
static void rt286_remove(struct snd_soc_component *component)
{
struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
cancel_delayed_work_sync(&rt286->jack_detect_work);
rt286->component = NULL;
}
#ifdef CONFIG_PM
static int rt286_suspend(struct snd_soc_component *component)
{
struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
regcache_cache_only(rt286->regmap, true);
regcache_mark_dirty(rt286->regmap);
return 0;
}
static int rt286_resume(struct snd_soc_component *component)
{
struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
regcache_cache_only(rt286->regmap, false);
rt286_index_sync(component);
regcache_sync(rt286->regmap);
return 0;
}
#else
#define rt286_suspend NULL
#define rt286_resume NULL
#endif
#define RT286_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
#define RT286_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
static const struct snd_soc_dai_ops rt286_aif_dai_ops = {
.hw_params = rt286_hw_params,
.set_fmt = rt286_set_dai_fmt,
.set_sysclk = rt286_set_dai_sysclk,
.set_bclk_ratio = rt286_set_bclk_ratio,
};
static struct snd_soc_dai_driver rt286_dai[] = {
{
.name = "rt286-aif1",
.id = RT286_AIF1,
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT286_STEREO_RATES,
.formats = RT286_FORMATS,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT286_STEREO_RATES,
.formats = RT286_FORMATS,
},
.ops = &rt286_aif_dai_ops,
.symmetric_rate = 1,
},
{
.name = "rt286-aif2",
.id = RT286_AIF2,
.playback = {
.stream_name = "AIF2 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT286_STEREO_RATES,
.formats = RT286_FORMATS,
},
.capture = {
.stream_name = "AIF2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT286_STEREO_RATES,
.formats = RT286_FORMATS,
},
.ops = &rt286_aif_dai_ops,
.symmetric_rate = 1,
},
};
static const struct snd_soc_component_driver soc_component_dev_rt286 = {
.probe = rt286_probe,
.remove = rt286_remove,
.suspend = rt286_suspend,
.resume = rt286_resume,
.set_bias_level = rt286_set_bias_level,
.set_jack = rt286_mic_detect,
.controls = rt286_snd_controls,
.num_controls = ARRAY_SIZE(rt286_snd_controls),
.dapm_widgets = rt286_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt286_dapm_widgets),
.dapm_routes = rt286_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(rt286_dapm_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config rt286_regmap = {
.reg_bits = 32,
.val_bits = 32,
.max_register = 0x02370100,
.volatile_reg = rt286_volatile_register,
.readable_reg = rt286_readable_register,
.reg_write = rl6347a_hw_write,
.reg_read = rl6347a_hw_read,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = rt286_reg,
.num_reg_defaults = ARRAY_SIZE(rt286_reg),
};
static const struct i2c_device_id rt286_i2c_id[] = {
{"rt286", 0},
{"rt288", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, rt286_i2c_id);
#ifdef CONFIG_ACPI
static const struct acpi_device_id rt286_acpi_match[] = {
{ "INT343A", 0 },
{},
};
MODULE_DEVICE_TABLE(acpi, rt286_acpi_match);
#endif
static const struct dmi_system_id force_combo_jack_table[] = {
{
.ident = "Intel Wilson Beach",
.matches = {
DMI_MATCH(DMI_BOARD_NAME, "Wilson Beach SDS")
}
},
{
.ident = "Intel Skylake RVP",
.matches = {
DMI_MATCH(DMI_PRODUCT_NAME, "Skylake Client platform")
}
},
{
.ident = "Intel Kabylake RVP",
.matches = {
DMI_MATCH(DMI_PRODUCT_NAME, "Kabylake Client platform")
}
},
{
.ident = "Thinkpad Helix 2nd",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad Helix 2nd")
}
},
{ }
};
static const struct dmi_system_id dmi_dell[] = {
{
.ident = "Dell",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
}
},
{ }
};
static int rt286_i2c_probe(struct i2c_client *i2c)
{
struct rt286_platform_data *pdata = dev_get_platdata(&i2c->dev);
struct rt286_priv *rt286;
int i, ret, vendor_id;
rt286 = devm_kzalloc(&i2c->dev, sizeof(*rt286),
GFP_KERNEL);
if (NULL == rt286)
return -ENOMEM;
rt286->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt286_regmap);
if (IS_ERR(rt286->regmap)) {
ret = PTR_ERR(rt286->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
ret = regmap_read(rt286->regmap,
RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &vendor_id);
if (ret != 0) {
dev_err(&i2c->dev, "I2C error %d\n", ret);
return ret;
}
if (vendor_id != RT286_VENDOR_ID && vendor_id != RT288_VENDOR_ID) {
dev_err(&i2c->dev,
"Device with ID register %#x is not rt286\n",
vendor_id);
return -ENODEV;
}
rt286->index_cache = devm_kmemdup(&i2c->dev, rt286_index_def,
sizeof(rt286_index_def), GFP_KERNEL);
if (!rt286->index_cache)
return -ENOMEM;
rt286->index_cache_size = INDEX_CACHE_SIZE;
rt286->i2c = i2c;
i2c_set_clientdata(i2c, rt286);
/* restore codec default */
for (i = 0; i < INDEX_CACHE_SIZE; i++)
regmap_write(rt286->regmap, rt286->index_cache[i].reg,
rt286->index_cache[i].def);
for (i = 0; i < ARRAY_SIZE(rt286_reg); i++)
regmap_write(rt286->regmap, rt286_reg[i].reg,
rt286_reg[i].def);
if (pdata)
rt286->pdata = *pdata;
if ((vendor_id == RT288_VENDOR_ID && dmi_check_system(dmi_dell)) ||
dmi_check_system(force_combo_jack_table))
rt286->pdata.cbj_en = true;
regmap_write(rt286->regmap, RT286_SET_AUDIO_POWER, AC_PWRST_D3);
for (i = 0; i < RT286_POWER_REG_LEN; i++)
regmap_write(rt286->regmap,
RT286_SET_POWER(rt286_support_power_controls[i]),
AC_PWRST_D1);
if (!rt286->pdata.cbj_en) {
regmap_write(rt286->regmap, RT286_CBJ_CTRL2, 0x0000);
regmap_write(rt286->regmap, RT286_MIC1_DET_CTRL, 0x0816);
regmap_update_bits(rt286->regmap,
RT286_CBJ_CTRL1, 0xf000, 0xb000);
} else {
regmap_update_bits(rt286->regmap,
RT286_CBJ_CTRL1, 0xf000, 0x5000);
}
mdelay(10);
if (!rt286->pdata.gpio2_en)
regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0x40);
else
regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0);
mdelay(10);
regmap_write(rt286->regmap, RT286_MISC_CTRL1, 0x0000);
/* Power down LDO, VREF */
regmap_update_bits(rt286->regmap, RT286_POWER_CTRL2, 0xc, 0x0);
regmap_update_bits(rt286->regmap, RT286_POWER_CTRL1, 0x1001, 0x1001);
/* Set depop parameter */
regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL2, 0x403a, 0x401a);
regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL3, 0xf777, 0x4737);
regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL4, 0x00ff, 0x003f);
if (vendor_id == RT288_VENDOR_ID && dmi_check_system(dmi_dell)) {
regmap_update_bits(rt286->regmap,
RT286_SET_GPIO_MASK, 0x40, 0x40);
regmap_update_bits(rt286->regmap,
RT286_SET_GPIO_DIRECTION, 0x40, 0x40);
regmap_update_bits(rt286->regmap,
RT286_SET_GPIO_DATA, 0x40, 0x40);
regmap_update_bits(rt286->regmap,
RT286_GPIO_CTRL, 0xc, 0x8);
}
if (rt286->i2c->irq) {
ret = request_threaded_irq(rt286->i2c->irq, NULL, rt286_irq,
IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt286", rt286);
if (ret != 0) {
dev_err(&i2c->dev,
"Failed to reguest IRQ: %d\n", ret);
return ret;
}
}
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_rt286,
rt286_dai, ARRAY_SIZE(rt286_dai));
return ret;
}
static void rt286_i2c_remove(struct i2c_client *i2c)
{
struct rt286_priv *rt286 = i2c_get_clientdata(i2c);
if (i2c->irq)
free_irq(i2c->irq, rt286);
}
static struct i2c_driver rt286_i2c_driver = {
.driver = {
.name = "rt286",
.acpi_match_table = ACPI_PTR(rt286_acpi_match),
},
.probe = rt286_i2c_probe,
.remove = rt286_i2c_remove,
.id_table = rt286_i2c_id,
};
module_i2c_driver(rt286_i2c_driver);
MODULE_DESCRIPTION("ASoC RT286 driver");
MODULE_AUTHOR("Bard Liao <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/rt286.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm5110.c -- WM5110 ALSA SoC Audio driver
*
* Copyright 2012 Wolfson Microelectronics plc
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/jack.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <linux/mfd/arizona/core.h>
#include <linux/mfd/arizona/registers.h>
#include "arizona.h"
#include "wm_adsp.h"
#include "wm5110.h"
#define WM5110_NUM_ADSP 4
#define DRV_NAME "wm5110-codec"
struct wm5110_priv {
struct arizona_priv core;
struct arizona_fll fll[2];
unsigned int in_value;
int in_pre_pending;
int in_post_pending;
unsigned int in_pga_cache[6];
};
static const struct cs_dsp_region wm5110_dsp1_regions[] = {
{ .type = WMFW_ADSP2_PM, .base = 0x100000 },
{ .type = WMFW_ADSP2_ZM, .base = 0x180000 },
{ .type = WMFW_ADSP2_XM, .base = 0x190000 },
{ .type = WMFW_ADSP2_YM, .base = 0x1a8000 },
};
static const struct cs_dsp_region wm5110_dsp2_regions[] = {
{ .type = WMFW_ADSP2_PM, .base = 0x200000 },
{ .type = WMFW_ADSP2_ZM, .base = 0x280000 },
{ .type = WMFW_ADSP2_XM, .base = 0x290000 },
{ .type = WMFW_ADSP2_YM, .base = 0x2a8000 },
};
static const struct cs_dsp_region wm5110_dsp3_regions[] = {
{ .type = WMFW_ADSP2_PM, .base = 0x300000 },
{ .type = WMFW_ADSP2_ZM, .base = 0x380000 },
{ .type = WMFW_ADSP2_XM, .base = 0x390000 },
{ .type = WMFW_ADSP2_YM, .base = 0x3a8000 },
};
static const struct cs_dsp_region wm5110_dsp4_regions[] = {
{ .type = WMFW_ADSP2_PM, .base = 0x400000 },
{ .type = WMFW_ADSP2_ZM, .base = 0x480000 },
{ .type = WMFW_ADSP2_XM, .base = 0x490000 },
{ .type = WMFW_ADSP2_YM, .base = 0x4a8000 },
};
static const struct cs_dsp_region *wm5110_dsp_regions[] = {
wm5110_dsp1_regions,
wm5110_dsp2_regions,
wm5110_dsp3_regions,
wm5110_dsp4_regions,
};
static const struct reg_default wm5110_sysclk_revd_patch[] = {
{ 0x3093, 0x1001 },
{ 0x30E3, 0x1301 },
{ 0x3133, 0x1201 },
{ 0x3183, 0x1501 },
{ 0x31D3, 0x1401 },
{ 0x0049, 0x01ea },
{ 0x004a, 0x01f2 },
{ 0x0057, 0x01e7 },
{ 0x0058, 0x01fb },
{ 0x33ce, 0xc4f5 },
{ 0x33cf, 0x1361 },
{ 0x33d0, 0x0402 },
{ 0x33d1, 0x4700 },
{ 0x33d2, 0x026d },
{ 0x33d3, 0xff00 },
{ 0x33d4, 0x026d },
{ 0x33d5, 0x0101 },
{ 0x33d6, 0xc4f5 },
{ 0x33d7, 0x0361 },
{ 0x33d8, 0x0402 },
{ 0x33d9, 0x6701 },
{ 0x33da, 0xc4f5 },
{ 0x33db, 0x136f },
{ 0x33dc, 0xc4f5 },
{ 0x33dd, 0x134f },
{ 0x33de, 0xc4f5 },
{ 0x33df, 0x131f },
{ 0x33e0, 0x026d },
{ 0x33e1, 0x4f01 },
{ 0x33e2, 0x026d },
{ 0x33e3, 0xf100 },
{ 0x33e4, 0x026d },
{ 0x33e5, 0x0001 },
{ 0x33e6, 0xc4f5 },
{ 0x33e7, 0x0361 },
{ 0x33e8, 0x0402 },
{ 0x33e9, 0x6601 },
{ 0x33ea, 0xc4f5 },
{ 0x33eb, 0x136f },
{ 0x33ec, 0xc4f5 },
{ 0x33ed, 0x134f },
{ 0x33ee, 0xc4f5 },
{ 0x33ef, 0x131f },
{ 0x33f0, 0x026d },
{ 0x33f1, 0x4e01 },
{ 0x33f2, 0x026d },
{ 0x33f3, 0xf000 },
{ 0x33f6, 0xc4f5 },
{ 0x33f7, 0x1361 },
{ 0x33f8, 0x0402 },
{ 0x33f9, 0x4600 },
{ 0x33fa, 0x026d },
{ 0x33fb, 0xfe00 },
};
static const struct reg_default wm5110_sysclk_reve_patch[] = {
{ 0x3270, 0xE410 },
{ 0x3271, 0x3078 },
{ 0x3272, 0xE410 },
{ 0x3273, 0x3070 },
{ 0x3274, 0xE410 },
{ 0x3275, 0x3066 },
{ 0x3276, 0xE410 },
{ 0x3277, 0x3056 },
{ 0x327A, 0xE414 },
{ 0x327B, 0x3078 },
{ 0x327C, 0xE414 },
{ 0x327D, 0x3070 },
{ 0x327E, 0xE414 },
{ 0x327F, 0x3066 },
{ 0x3280, 0xE414 },
{ 0x3281, 0x3056 },
};
static int wm5110_sysclk_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct arizona *arizona = dev_get_drvdata(component->dev->parent);
struct regmap *regmap = arizona->regmap;
const struct reg_default *patch = NULL;
int i, patch_size;
switch (arizona->rev) {
case 3:
patch = wm5110_sysclk_revd_patch;
patch_size = ARRAY_SIZE(wm5110_sysclk_revd_patch);
break;
default:
patch = wm5110_sysclk_reve_patch;
patch_size = ARRAY_SIZE(wm5110_sysclk_reve_patch);
break;
}
switch (event) {
case SND_SOC_DAPM_POST_PMU:
if (patch)
for (i = 0; i < patch_size; i++)
regmap_write_async(regmap, patch[i].reg,
patch[i].def);
break;
case SND_SOC_DAPM_PRE_PMU:
case SND_SOC_DAPM_POST_PMD:
return arizona_clk_ev(w, kcontrol, event);
default:
break;
}
return 0;
}
static int wm5110_adsp_power_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct arizona *arizona = dev_get_drvdata(component->dev->parent);
unsigned int v;
int ret;
ret = regmap_read(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, &v);
if (ret != 0) {
dev_err(component->dev, "Failed to read SYSCLK state: %d\n", ret);
return ret;
}
v = (v & ARIZONA_SYSCLK_FREQ_MASK) >> ARIZONA_SYSCLK_FREQ_SHIFT;
wm_adsp2_set_dspclk(w, v);
return wm_adsp_early_event(w, kcontrol, event);
}
static const struct reg_sequence wm5110_no_dre_left_enable[] = {
{ 0x3024, 0xE410 },
{ 0x3025, 0x0056 },
{ 0x301B, 0x0224 },
{ 0x301F, 0x4263 },
{ 0x3021, 0x5291 },
{ 0x3030, 0xE410 },
{ 0x3031, 0x3066 },
{ 0x3032, 0xE410 },
{ 0x3033, 0x3070 },
{ 0x3034, 0xE410 },
{ 0x3035, 0x3078 },
{ 0x3036, 0xE410 },
{ 0x3037, 0x3080 },
{ 0x3038, 0xE410 },
{ 0x3039, 0x3080 },
};
static const struct reg_sequence wm5110_dre_left_enable[] = {
{ 0x3024, 0x0231 },
{ 0x3025, 0x0B00 },
{ 0x301B, 0x0227 },
{ 0x301F, 0x4266 },
{ 0x3021, 0x5294 },
{ 0x3030, 0xE231 },
{ 0x3031, 0x0266 },
{ 0x3032, 0x8231 },
{ 0x3033, 0x4B15 },
{ 0x3034, 0x8231 },
{ 0x3035, 0x0B15 },
{ 0x3036, 0xE231 },
{ 0x3037, 0x5294 },
{ 0x3038, 0x0231 },
{ 0x3039, 0x0B00 },
};
static const struct reg_sequence wm5110_no_dre_right_enable[] = {
{ 0x3074, 0xE414 },
{ 0x3075, 0x0056 },
{ 0x306B, 0x0224 },
{ 0x306F, 0x4263 },
{ 0x3071, 0x5291 },
{ 0x3080, 0xE414 },
{ 0x3081, 0x3066 },
{ 0x3082, 0xE414 },
{ 0x3083, 0x3070 },
{ 0x3084, 0xE414 },
{ 0x3085, 0x3078 },
{ 0x3086, 0xE414 },
{ 0x3087, 0x3080 },
{ 0x3088, 0xE414 },
{ 0x3089, 0x3080 },
};
static const struct reg_sequence wm5110_dre_right_enable[] = {
{ 0x3074, 0x0231 },
{ 0x3075, 0x0B00 },
{ 0x306B, 0x0227 },
{ 0x306F, 0x4266 },
{ 0x3071, 0x5294 },
{ 0x3080, 0xE231 },
{ 0x3081, 0x0266 },
{ 0x3082, 0x8231 },
{ 0x3083, 0x4B17 },
{ 0x3084, 0x8231 },
{ 0x3085, 0x0B17 },
{ 0x3086, 0xE231 },
{ 0x3087, 0x5294 },
{ 0x3088, 0x0231 },
{ 0x3089, 0x0B00 },
};
static int wm5110_hp_pre_enable(struct snd_soc_dapm_widget *w)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct arizona_priv *priv = snd_soc_component_get_drvdata(component);
struct arizona *arizona = priv->arizona;
unsigned int val = snd_soc_component_read(component, ARIZONA_DRE_ENABLE);
const struct reg_sequence *wseq;
int nregs;
switch (w->shift) {
case ARIZONA_OUT1L_ENA_SHIFT:
if (val & ARIZONA_DRE1L_ENA_MASK) {
wseq = wm5110_dre_left_enable;
nregs = ARRAY_SIZE(wm5110_dre_left_enable);
} else {
wseq = wm5110_no_dre_left_enable;
nregs = ARRAY_SIZE(wm5110_no_dre_left_enable);
priv->out_up_delay += 10;
}
break;
case ARIZONA_OUT1R_ENA_SHIFT:
if (val & ARIZONA_DRE1R_ENA_MASK) {
wseq = wm5110_dre_right_enable;
nregs = ARRAY_SIZE(wm5110_dre_right_enable);
} else {
wseq = wm5110_no_dre_right_enable;
nregs = ARRAY_SIZE(wm5110_no_dre_right_enable);
priv->out_up_delay += 10;
}
break;
default:
return 0;
}
return regmap_multi_reg_write(arizona->regmap, wseq, nregs);
}
static int wm5110_hp_pre_disable(struct snd_soc_dapm_widget *w)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct arizona_priv *priv = snd_soc_component_get_drvdata(component);
unsigned int val = snd_soc_component_read(component, ARIZONA_DRE_ENABLE);
switch (w->shift) {
case ARIZONA_OUT1L_ENA_SHIFT:
if (!(val & ARIZONA_DRE1L_ENA_MASK)) {
snd_soc_component_update_bits(component,
ARIZONA_SPARE_TRIGGERS,
ARIZONA_WS_TRG1,
ARIZONA_WS_TRG1);
snd_soc_component_update_bits(component,
ARIZONA_SPARE_TRIGGERS,
ARIZONA_WS_TRG1, 0);
priv->out_down_delay += 27;
}
break;
case ARIZONA_OUT1R_ENA_SHIFT:
if (!(val & ARIZONA_DRE1R_ENA_MASK)) {
snd_soc_component_update_bits(component,
ARIZONA_SPARE_TRIGGERS,
ARIZONA_WS_TRG2,
ARIZONA_WS_TRG2);
snd_soc_component_update_bits(component,
ARIZONA_SPARE_TRIGGERS,
ARIZONA_WS_TRG2, 0);
priv->out_down_delay += 27;
}
break;
default:
break;
}
return 0;
}
static int wm5110_hp_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct arizona_priv *priv = snd_soc_component_get_drvdata(component);
switch (priv->arizona->rev) {
case 0 ... 3:
break;
default:
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
wm5110_hp_pre_enable(w);
break;
case SND_SOC_DAPM_PRE_PMD:
wm5110_hp_pre_disable(w);
break;
default:
break;
}
break;
}
return arizona_hp_ev(w, kcontrol, event);
}
static int wm5110_clear_pga_volume(struct arizona *arizona, int output)
{
unsigned int reg = ARIZONA_OUTPUT_PATH_CONFIG_1L + output * 4;
int ret;
ret = regmap_write(arizona->regmap, reg, 0x80);
if (ret)
dev_err(arizona->dev, "Failed to clear PGA (0x%x): %d\n",
reg, ret);
return ret;
}
static int wm5110_put_dre(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct arizona *arizona = dev_get_drvdata(component->dev->parent);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
unsigned int ena, dre;
unsigned int mask = (0x1 << mc->shift) | (0x1 << mc->rshift);
unsigned int lnew = (!!ucontrol->value.integer.value[0]) << mc->shift;
unsigned int rnew = (!!ucontrol->value.integer.value[1]) << mc->rshift;
unsigned int lold, rold;
unsigned int lena, rena;
bool change = false;
int ret;
snd_soc_dapm_mutex_lock(dapm);
ret = regmap_read(arizona->regmap, ARIZONA_OUTPUT_ENABLES_1, &ena);
if (ret) {
dev_err(arizona->dev, "Failed to read output state: %d\n", ret);
goto err;
}
ret = regmap_read(arizona->regmap, ARIZONA_DRE_ENABLE, &dre);
if (ret) {
dev_err(arizona->dev, "Failed to read DRE state: %d\n", ret);
goto err;
}
lold = dre & (1 << mc->shift);
rold = dre & (1 << mc->rshift);
/* Enables are channel wise swapped from the DRE enables */
lena = ena & (1 << mc->rshift);
rena = ena & (1 << mc->shift);
if ((lena && lnew != lold) || (rena && rnew != rold)) {
dev_err(arizona->dev, "Can't change DRE on active outputs\n");
ret = -EBUSY;
goto err;
}
ret = regmap_update_bits_check(arizona->regmap, ARIZONA_DRE_ENABLE,
mask, lnew | rnew, &change);
if (ret) {
dev_err(arizona->dev, "Failed to set DRE: %d\n", ret);
goto err;
}
/* Force reset of PGA volumes, if turning DRE off */
if (!lnew && lold)
wm5110_clear_pga_volume(arizona, mc->shift);
if (!rnew && rold)
wm5110_clear_pga_volume(arizona, mc->rshift);
if (change)
ret = 1;
err:
snd_soc_dapm_mutex_unlock(dapm);
return ret;
}
static int wm5110_in_pga_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
int ret;
/*
* PGA Volume is also used as part of the enable sequence, so
* usage of it should be avoided whilst that is running.
*/
snd_soc_dapm_mutex_lock(dapm);
ret = snd_soc_get_volsw_range(kcontrol, ucontrol);
snd_soc_dapm_mutex_unlock(dapm);
return ret;
}
static int wm5110_in_pga_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
int ret;
/*
* PGA Volume is also used as part of the enable sequence, so
* usage of it should be avoided whilst that is running.
*/
snd_soc_dapm_mutex_lock(dapm);
ret = snd_soc_put_volsw_range(kcontrol, ucontrol);
snd_soc_dapm_mutex_unlock(dapm);
return ret;
}
static int wm5110_in_analog_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct arizona_priv *priv = snd_soc_component_get_drvdata(component);
struct wm5110_priv *wm5110 = snd_soc_component_get_drvdata(component);
struct arizona *arizona = priv->arizona;
unsigned int reg, mask;
struct reg_sequence analog_seq[] = {
{ 0x80, 0x3 },
{ 0x35d, 0 },
{ 0x80, 0x0 },
};
reg = ARIZONA_IN1L_CONTROL + ((w->shift ^ 0x1) * 4);
mask = ARIZONA_IN1L_PGA_VOL_MASK;
switch (event) {
case SND_SOC_DAPM_WILL_PMU:
wm5110->in_value |= 0x3 << ((w->shift ^ 0x1) * 2);
wm5110->in_pre_pending++;
wm5110->in_post_pending++;
return 0;
case SND_SOC_DAPM_PRE_PMU:
wm5110->in_pga_cache[w->shift] = snd_soc_component_read(component, reg);
snd_soc_component_update_bits(component, reg, mask,
0x40 << ARIZONA_IN1L_PGA_VOL_SHIFT);
wm5110->in_pre_pending--;
if (wm5110->in_pre_pending == 0) {
analog_seq[1].def = wm5110->in_value;
regmap_multi_reg_write_bypassed(arizona->regmap,
analog_seq,
ARRAY_SIZE(analog_seq));
msleep(55);
wm5110->in_value = 0;
}
break;
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(component, reg, mask,
wm5110->in_pga_cache[w->shift]);
wm5110->in_post_pending--;
if (wm5110->in_post_pending == 0)
regmap_multi_reg_write_bypassed(arizona->regmap,
analog_seq,
ARRAY_SIZE(analog_seq));
break;
default:
break;
}
return 0;
}
static int wm5110_in_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct arizona_priv *priv = snd_soc_component_get_drvdata(component);
struct arizona *arizona = priv->arizona;
switch (arizona->rev) {
case 0 ... 4:
if (arizona_input_analog(component, w->shift))
wm5110_in_analog_ev(w, kcontrol, event);
break;
default:
break;
}
return arizona_in_ev(w, kcontrol, event);
}
static DECLARE_TLV_DB_SCALE(ana_tlv, 0, 100, 0);
static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0);
static DECLARE_TLV_DB_SCALE(noise_tlv, -13200, 600, 0);
static DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
#define WM5110_NG_SRC(name, base) \
SOC_SINGLE(name " NG HPOUT1L Switch", base, 0, 1, 0), \
SOC_SINGLE(name " NG HPOUT1R Switch", base, 1, 1, 0), \
SOC_SINGLE(name " NG HPOUT2L Switch", base, 2, 1, 0), \
SOC_SINGLE(name " NG HPOUT2R Switch", base, 3, 1, 0), \
SOC_SINGLE(name " NG HPOUT3L Switch", base, 4, 1, 0), \
SOC_SINGLE(name " NG HPOUT3R Switch", base, 5, 1, 0), \
SOC_SINGLE(name " NG SPKOUTL Switch", base, 6, 1, 0), \
SOC_SINGLE(name " NG SPKOUTR Switch", base, 7, 1, 0), \
SOC_SINGLE(name " NG SPKDAT1L Switch", base, 8, 1, 0), \
SOC_SINGLE(name " NG SPKDAT1R Switch", base, 9, 1, 0), \
SOC_SINGLE(name " NG SPKDAT2L Switch", base, 10, 1, 0), \
SOC_SINGLE(name " NG SPKDAT2R Switch", base, 11, 1, 0)
#define WM5110_RXANC_INPUT_ROUTES(widget, name) \
{ widget, NULL, name " NG Mux" }, \
{ name " NG Internal", NULL, "RXANC NG Clock" }, \
{ name " NG Internal", NULL, name " Channel" }, \
{ name " NG External", NULL, "RXANC NG External Clock" }, \
{ name " NG External", NULL, name " Channel" }, \
{ name " NG Mux", "None", name " Channel" }, \
{ name " NG Mux", "Internal", name " NG Internal" }, \
{ name " NG Mux", "External", name " NG External" }, \
{ name " Channel", "Left", name " Left Input" }, \
{ name " Channel", "Combine", name " Left Input" }, \
{ name " Channel", "Right", name " Right Input" }, \
{ name " Channel", "Combine", name " Right Input" }, \
{ name " Left Input", "IN1", "IN1L PGA" }, \
{ name " Right Input", "IN1", "IN1R PGA" }, \
{ name " Left Input", "IN2", "IN2L PGA" }, \
{ name " Right Input", "IN2", "IN2R PGA" }, \
{ name " Left Input", "IN3", "IN3L PGA" }, \
{ name " Right Input", "IN3", "IN3R PGA" }, \
{ name " Left Input", "IN4", "IN4L PGA" }, \
{ name " Right Input", "IN4", "IN4R PGA" }
#define WM5110_RXANC_OUTPUT_ROUTES(widget, name) \
{ widget, NULL, name " ANC Source" }, \
{ name " ANC Source", "RXANCL", "RXANCL" }, \
{ name " ANC Source", "RXANCR", "RXANCR" }
static const struct snd_kcontrol_new wm5110_snd_controls[] = {
SOC_ENUM("IN1 OSR", arizona_in_dmic_osr[0]),
SOC_ENUM("IN2 OSR", arizona_in_dmic_osr[1]),
SOC_ENUM("IN3 OSR", arizona_in_dmic_osr[2]),
SOC_ENUM("IN4 OSR", arizona_in_dmic_osr[3]),
SOC_SINGLE_RANGE_EXT_TLV("IN1L Volume", ARIZONA_IN1L_CONTROL,
ARIZONA_IN1L_PGA_VOL_SHIFT, 0x40, 0x5f, 0,
wm5110_in_pga_get, wm5110_in_pga_put, ana_tlv),
SOC_SINGLE_RANGE_EXT_TLV("IN1R Volume", ARIZONA_IN1R_CONTROL,
ARIZONA_IN1R_PGA_VOL_SHIFT, 0x40, 0x5f, 0,
wm5110_in_pga_get, wm5110_in_pga_put, ana_tlv),
SOC_SINGLE_RANGE_EXT_TLV("IN2L Volume", ARIZONA_IN2L_CONTROL,
ARIZONA_IN2L_PGA_VOL_SHIFT, 0x40, 0x5f, 0,
wm5110_in_pga_get, wm5110_in_pga_put, ana_tlv),
SOC_SINGLE_RANGE_EXT_TLV("IN2R Volume", ARIZONA_IN2R_CONTROL,
ARIZONA_IN2R_PGA_VOL_SHIFT, 0x40, 0x5f, 0,
wm5110_in_pga_get, wm5110_in_pga_put, ana_tlv),
SOC_SINGLE_RANGE_EXT_TLV("IN3L Volume", ARIZONA_IN3L_CONTROL,
ARIZONA_IN3L_PGA_VOL_SHIFT, 0x40, 0x5f, 0,
wm5110_in_pga_get, wm5110_in_pga_put, ana_tlv),
SOC_SINGLE_RANGE_EXT_TLV("IN3R Volume", ARIZONA_IN3R_CONTROL,
ARIZONA_IN3R_PGA_VOL_SHIFT, 0x40, 0x5f, 0,
wm5110_in_pga_get, wm5110_in_pga_put, ana_tlv),
SOC_ENUM("IN HPF Cutoff Frequency", arizona_in_hpf_cut_enum),
SOC_SINGLE("IN1L HPF Switch", ARIZONA_IN1L_CONTROL,
ARIZONA_IN1L_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN1R HPF Switch", ARIZONA_IN1R_CONTROL,
ARIZONA_IN1R_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN2L HPF Switch", ARIZONA_IN2L_CONTROL,
ARIZONA_IN2L_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN2R HPF Switch", ARIZONA_IN2R_CONTROL,
ARIZONA_IN2R_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN3L HPF Switch", ARIZONA_IN3L_CONTROL,
ARIZONA_IN3L_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN3R HPF Switch", ARIZONA_IN3R_CONTROL,
ARIZONA_IN3R_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN4L HPF Switch", ARIZONA_IN4L_CONTROL,
ARIZONA_IN4L_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN4R HPF Switch", ARIZONA_IN4R_CONTROL,
ARIZONA_IN4R_HPF_SHIFT, 1, 0),
SOC_SINGLE_TLV("IN1L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1L,
ARIZONA_IN1L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
SOC_SINGLE_TLV("IN1R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1R,
ARIZONA_IN1R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
SOC_SINGLE_TLV("IN2L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2L,
ARIZONA_IN2L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
SOC_SINGLE_TLV("IN2R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2R,
ARIZONA_IN2R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
SOC_SINGLE_TLV("IN3L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_3L,
ARIZONA_IN3L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
SOC_SINGLE_TLV("IN3R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_3R,
ARIZONA_IN3R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
SOC_SINGLE_TLV("IN4L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_4L,
ARIZONA_IN4L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
SOC_SINGLE_TLV("IN4R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_4R,
ARIZONA_IN4R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
SOC_ENUM("Input Ramp Up", arizona_in_vi_ramp),
SOC_ENUM("Input Ramp Down", arizona_in_vd_ramp),
SND_SOC_BYTES("RXANC Coefficients", ARIZONA_ANC_COEFF_START,
ARIZONA_ANC_COEFF_END - ARIZONA_ANC_COEFF_START + 1),
SND_SOC_BYTES("RXANCL Config", ARIZONA_FCL_FILTER_CONTROL, 1),
SND_SOC_BYTES("RXANCL Coefficients", ARIZONA_FCL_COEFF_START,
ARIZONA_FCL_COEFF_END - ARIZONA_FCL_COEFF_START + 1),
SND_SOC_BYTES("RXANCR Config", ARIZONA_FCR_FILTER_CONTROL, 1),
SND_SOC_BYTES("RXANCR Coefficients", ARIZONA_FCR_COEFF_START,
ARIZONA_FCR_COEFF_END - ARIZONA_FCR_COEFF_START + 1),
ARIZONA_MIXER_CONTROLS("EQ1", ARIZONA_EQ1MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("EQ2", ARIZONA_EQ2MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("EQ3", ARIZONA_EQ3MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("EQ4", ARIZONA_EQ4MIX_INPUT_1_SOURCE),
ARIZONA_EQ_CONTROL("EQ1 Coefficients", ARIZONA_EQ1_2),
SOC_SINGLE_TLV("EQ1 B1 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B1_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ1 B2 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B2_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ1 B3 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B3_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ1 B4 Volume", ARIZONA_EQ1_2, ARIZONA_EQ1_B4_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ1 B5 Volume", ARIZONA_EQ1_2, ARIZONA_EQ1_B5_GAIN_SHIFT,
24, 0, eq_tlv),
ARIZONA_EQ_CONTROL("EQ2 Coefficients", ARIZONA_EQ2_2),
SOC_SINGLE_TLV("EQ2 B1 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B1_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ2 B2 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B2_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ2 B3 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B3_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ2 B4 Volume", ARIZONA_EQ2_2, ARIZONA_EQ2_B4_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ2 B5 Volume", ARIZONA_EQ2_2, ARIZONA_EQ2_B5_GAIN_SHIFT,
24, 0, eq_tlv),
ARIZONA_EQ_CONTROL("EQ3 Coefficients", ARIZONA_EQ3_2),
SOC_SINGLE_TLV("EQ3 B1 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B1_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ3 B2 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B2_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ3 B3 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B3_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ3 B4 Volume", ARIZONA_EQ3_2, ARIZONA_EQ3_B4_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ3 B5 Volume", ARIZONA_EQ3_2, ARIZONA_EQ3_B5_GAIN_SHIFT,
24, 0, eq_tlv),
ARIZONA_EQ_CONTROL("EQ4 Coefficients", ARIZONA_EQ4_2),
SOC_SINGLE_TLV("EQ4 B1 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B1_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ4 B2 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B2_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ4 B3 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B3_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ4 B4 Volume", ARIZONA_EQ4_2, ARIZONA_EQ4_B4_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ4 B5 Volume", ARIZONA_EQ4_2, ARIZONA_EQ4_B5_GAIN_SHIFT,
24, 0, eq_tlv),
ARIZONA_MIXER_CONTROLS("DRC1L", ARIZONA_DRC1LMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("DRC1R", ARIZONA_DRC1RMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("DRC2L", ARIZONA_DRC2LMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("DRC2R", ARIZONA_DRC2RMIX_INPUT_1_SOURCE),
SND_SOC_BYTES_MASK("DRC1", ARIZONA_DRC1_CTRL1, 5,
ARIZONA_DRC1R_ENA | ARIZONA_DRC1L_ENA),
SND_SOC_BYTES_MASK("DRC2", ARIZONA_DRC2_CTRL1, 5,
ARIZONA_DRC2R_ENA | ARIZONA_DRC2L_ENA),
ARIZONA_MIXER_CONTROLS("LHPF1", ARIZONA_HPLP1MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("LHPF2", ARIZONA_HPLP2MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("LHPF3", ARIZONA_HPLP3MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("LHPF4", ARIZONA_HPLP4MIX_INPUT_1_SOURCE),
ARIZONA_LHPF_CONTROL("LHPF1 Coefficients", ARIZONA_HPLPF1_2),
ARIZONA_LHPF_CONTROL("LHPF2 Coefficients", ARIZONA_HPLPF2_2),
ARIZONA_LHPF_CONTROL("LHPF3 Coefficients", ARIZONA_HPLPF3_2),
ARIZONA_LHPF_CONTROL("LHPF4 Coefficients", ARIZONA_HPLPF4_2),
SOC_ENUM("LHPF1 Mode", arizona_lhpf1_mode),
SOC_ENUM("LHPF2 Mode", arizona_lhpf2_mode),
SOC_ENUM("LHPF3 Mode", arizona_lhpf3_mode),
SOC_ENUM("LHPF4 Mode", arizona_lhpf4_mode),
SOC_ENUM("ISRC1 FSL", arizona_isrc_fsl[0]),
SOC_ENUM("ISRC2 FSL", arizona_isrc_fsl[1]),
SOC_ENUM("ISRC3 FSL", arizona_isrc_fsl[2]),
SOC_ENUM("ISRC1 FSH", arizona_isrc_fsh[0]),
SOC_ENUM("ISRC2 FSH", arizona_isrc_fsh[1]),
SOC_ENUM("ISRC3 FSH", arizona_isrc_fsh[2]),
SOC_ENUM("ASRC RATE 1", arizona_asrc_rate1),
WM_ADSP2_PRELOAD_SWITCH("DSP1", 1),
WM_ADSP2_PRELOAD_SWITCH("DSP2", 2),
WM_ADSP2_PRELOAD_SWITCH("DSP3", 3),
WM_ADSP2_PRELOAD_SWITCH("DSP4", 4),
ARIZONA_MIXER_CONTROLS("DSP1L", ARIZONA_DSP1LMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("DSP1R", ARIZONA_DSP1RMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("DSP2L", ARIZONA_DSP2LMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("DSP2R", ARIZONA_DSP2RMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("DSP3L", ARIZONA_DSP3LMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("DSP3R", ARIZONA_DSP3RMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("DSP4L", ARIZONA_DSP4LMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("DSP4R", ARIZONA_DSP4RMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("Mic", ARIZONA_MICMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("Noise", ARIZONA_NOISEMIX_INPUT_1_SOURCE),
SOC_SINGLE_TLV("Noise Generator Volume", ARIZONA_COMFORT_NOISE_GENERATOR,
ARIZONA_NOISE_GEN_GAIN_SHIFT, 0x16, 0, noise_tlv),
ARIZONA_MIXER_CONTROLS("HPOUT1L", ARIZONA_OUT1LMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("HPOUT1R", ARIZONA_OUT1RMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("HPOUT2L", ARIZONA_OUT2LMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("HPOUT2R", ARIZONA_OUT2RMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("HPOUT3L", ARIZONA_OUT3LMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("HPOUT3R", ARIZONA_OUT3RMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SPKOUTL", ARIZONA_OUT4LMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SPKOUTR", ARIZONA_OUT4RMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SPKDAT1L", ARIZONA_OUT5LMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SPKDAT1R", ARIZONA_OUT5RMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SPKDAT2L", ARIZONA_OUT6LMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SPKDAT2R", ARIZONA_OUT6RMIX_INPUT_1_SOURCE),
SOC_SINGLE("HPOUT1 SC Protect Switch", ARIZONA_HP1_SHORT_CIRCUIT_CTRL,
ARIZONA_HP1_SC_ENA_SHIFT, 1, 0),
SOC_SINGLE("HPOUT2 SC Protect Switch", ARIZONA_HP2_SHORT_CIRCUIT_CTRL,
ARIZONA_HP2_SC_ENA_SHIFT, 1, 0),
SOC_SINGLE("HPOUT3 SC Protect Switch", ARIZONA_HP3_SHORT_CIRCUIT_CTRL,
ARIZONA_HP3_SC_ENA_SHIFT, 1, 0),
SOC_SINGLE("SPKDAT1 High Performance Switch", ARIZONA_OUTPUT_PATH_CONFIG_5L,
ARIZONA_OUT5_OSR_SHIFT, 1, 0),
SOC_SINGLE("SPKDAT2 High Performance Switch", ARIZONA_OUTPUT_PATH_CONFIG_6L,
ARIZONA_OUT6_OSR_SHIFT, 1, 0),
SOC_DOUBLE_R("HPOUT1 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_1L,
ARIZONA_DAC_DIGITAL_VOLUME_1R, ARIZONA_OUT1L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R("HPOUT2 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_2L,
ARIZONA_DAC_DIGITAL_VOLUME_2R, ARIZONA_OUT2L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R("HPOUT3 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_3L,
ARIZONA_DAC_DIGITAL_VOLUME_3R, ARIZONA_OUT3L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R("Speaker Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_4L,
ARIZONA_DAC_DIGITAL_VOLUME_4R, ARIZONA_OUT4L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R("SPKDAT1 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_5L,
ARIZONA_DAC_DIGITAL_VOLUME_5R, ARIZONA_OUT5L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R("SPKDAT2 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_6L,
ARIZONA_DAC_DIGITAL_VOLUME_6R, ARIZONA_OUT6L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_1L,
ARIZONA_DAC_DIGITAL_VOLUME_1R, ARIZONA_OUT1L_VOL_SHIFT,
0xbf, 0, digital_tlv),
SOC_DOUBLE_R_TLV("HPOUT2 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_2L,
ARIZONA_DAC_DIGITAL_VOLUME_2R, ARIZONA_OUT2L_VOL_SHIFT,
0xbf, 0, digital_tlv),
SOC_DOUBLE_R_TLV("HPOUT3 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_3L,
ARIZONA_DAC_DIGITAL_VOLUME_3R, ARIZONA_OUT3L_VOL_SHIFT,
0xbf, 0, digital_tlv),
SOC_DOUBLE_R_TLV("Speaker Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_4L,
ARIZONA_DAC_DIGITAL_VOLUME_4R, ARIZONA_OUT4L_VOL_SHIFT,
0xbf, 0, digital_tlv),
SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_5L,
ARIZONA_DAC_DIGITAL_VOLUME_5R, ARIZONA_OUT5L_VOL_SHIFT,
0xbf, 0, digital_tlv),
SOC_DOUBLE_R_TLV("SPKDAT2 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_6L,
ARIZONA_DAC_DIGITAL_VOLUME_6R, ARIZONA_OUT6L_VOL_SHIFT,
0xbf, 0, digital_tlv),
SOC_DOUBLE("SPKDAT1 Switch", ARIZONA_PDM_SPK1_CTRL_1, ARIZONA_SPK1L_MUTE_SHIFT,
ARIZONA_SPK1R_MUTE_SHIFT, 1, 1),
SOC_DOUBLE("SPKDAT2 Switch", ARIZONA_PDM_SPK2_CTRL_1, ARIZONA_SPK2L_MUTE_SHIFT,
ARIZONA_SPK2R_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_EXT("HPOUT1 DRE Switch", ARIZONA_DRE_ENABLE,
ARIZONA_DRE1L_ENA_SHIFT, ARIZONA_DRE1R_ENA_SHIFT, 1, 0,
snd_soc_get_volsw, wm5110_put_dre),
SOC_DOUBLE_EXT("HPOUT2 DRE Switch", ARIZONA_DRE_ENABLE,
ARIZONA_DRE2L_ENA_SHIFT, ARIZONA_DRE2R_ENA_SHIFT, 1, 0,
snd_soc_get_volsw, wm5110_put_dre),
SOC_DOUBLE_EXT("HPOUT3 DRE Switch", ARIZONA_DRE_ENABLE,
ARIZONA_DRE3L_ENA_SHIFT, ARIZONA_DRE3R_ENA_SHIFT, 1, 0,
snd_soc_get_volsw, wm5110_put_dre),
SOC_ENUM("Output Ramp Up", arizona_out_vi_ramp),
SOC_ENUM("Output Ramp Down", arizona_out_vd_ramp),
SOC_SINGLE("Noise Gate Switch", ARIZONA_NOISE_GATE_CONTROL,
ARIZONA_NGATE_ENA_SHIFT, 1, 0),
SOC_SINGLE_TLV("Noise Gate Threshold Volume", ARIZONA_NOISE_GATE_CONTROL,
ARIZONA_NGATE_THR_SHIFT, 7, 1, ng_tlv),
SOC_ENUM("Noise Gate Hold", arizona_ng_hold),
WM5110_NG_SRC("HPOUT1L", ARIZONA_NOISE_GATE_SELECT_1L),
WM5110_NG_SRC("HPOUT1R", ARIZONA_NOISE_GATE_SELECT_1R),
WM5110_NG_SRC("HPOUT2L", ARIZONA_NOISE_GATE_SELECT_2L),
WM5110_NG_SRC("HPOUT2R", ARIZONA_NOISE_GATE_SELECT_2R),
WM5110_NG_SRC("HPOUT3L", ARIZONA_NOISE_GATE_SELECT_3L),
WM5110_NG_SRC("HPOUT3R", ARIZONA_NOISE_GATE_SELECT_3R),
WM5110_NG_SRC("SPKOUTL", ARIZONA_NOISE_GATE_SELECT_4L),
WM5110_NG_SRC("SPKOUTR", ARIZONA_NOISE_GATE_SELECT_4R),
WM5110_NG_SRC("SPKDAT1L", ARIZONA_NOISE_GATE_SELECT_5L),
WM5110_NG_SRC("SPKDAT1R", ARIZONA_NOISE_GATE_SELECT_5R),
WM5110_NG_SRC("SPKDAT2L", ARIZONA_NOISE_GATE_SELECT_6L),
WM5110_NG_SRC("SPKDAT2R", ARIZONA_NOISE_GATE_SELECT_6R),
ARIZONA_MIXER_CONTROLS("AIF1TX1", ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF1TX2", ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF1TX3", ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF1TX4", ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF1TX5", ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF1TX6", ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF1TX7", ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF1TX8", ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF2TX1", ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF2TX2", ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF2TX3", ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF2TX4", ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF2TX5", ARIZONA_AIF2TX5MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF2TX6", ARIZONA_AIF2TX6MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF3TX1", ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF3TX2", ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SLIMTX1", ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SLIMTX2", ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SLIMTX3", ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SLIMTX4", ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SLIMTX5", ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SLIMTX6", ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SLIMTX7", ARIZONA_SLIMTX7MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SLIMTX8", ARIZONA_SLIMTX8MIX_INPUT_1_SOURCE),
WM_ADSP_FW_CONTROL("DSP1", 0),
WM_ADSP_FW_CONTROL("DSP2", 1),
WM_ADSP_FW_CONTROL("DSP3", 2),
WM_ADSP_FW_CONTROL("DSP4", 3),
};
ARIZONA_MIXER_ENUMS(EQ1, ARIZONA_EQ1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(EQ2, ARIZONA_EQ2MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(EQ3, ARIZONA_EQ3MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(EQ4, ARIZONA_EQ4MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(DRC1L, ARIZONA_DRC1LMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(DRC1R, ARIZONA_DRC1RMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(DRC2L, ARIZONA_DRC2LMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(DRC2R, ARIZONA_DRC2RMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(LHPF1, ARIZONA_HPLP1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(LHPF2, ARIZONA_HPLP2MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(LHPF3, ARIZONA_HPLP3MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(LHPF4, ARIZONA_HPLP4MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(DSP1L, ARIZONA_DSP1LMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(DSP1R, ARIZONA_DSP1RMIX_INPUT_1_SOURCE);
ARIZONA_DSP_AUX_ENUMS(DSP1, ARIZONA_DSP1AUX1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(DSP2L, ARIZONA_DSP2LMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(DSP2R, ARIZONA_DSP2RMIX_INPUT_1_SOURCE);
ARIZONA_DSP_AUX_ENUMS(DSP2, ARIZONA_DSP2AUX1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(DSP3L, ARIZONA_DSP3LMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(DSP3R, ARIZONA_DSP3RMIX_INPUT_1_SOURCE);
ARIZONA_DSP_AUX_ENUMS(DSP3, ARIZONA_DSP3AUX1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(DSP4L, ARIZONA_DSP4LMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(DSP4R, ARIZONA_DSP4RMIX_INPUT_1_SOURCE);
ARIZONA_DSP_AUX_ENUMS(DSP4, ARIZONA_DSP4AUX1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(Mic, ARIZONA_MICMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(Noise, ARIZONA_NOISEMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(PWM1, ARIZONA_PWM1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(PWM2, ARIZONA_PWM2MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(OUT1L, ARIZONA_OUT1LMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(OUT1R, ARIZONA_OUT1RMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(OUT2L, ARIZONA_OUT2LMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(OUT2R, ARIZONA_OUT2RMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(OUT3L, ARIZONA_OUT3LMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(OUT3R, ARIZONA_OUT3RMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SPKOUTL, ARIZONA_OUT4LMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SPKOUTR, ARIZONA_OUT4RMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SPKDAT1L, ARIZONA_OUT5LMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SPKDAT1R, ARIZONA_OUT5RMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SPKDAT2L, ARIZONA_OUT6LMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SPKDAT2R, ARIZONA_OUT6RMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX1, ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX2, ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX3, ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX4, ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX5, ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX6, ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX7, ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX8, ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF2TX1, ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF2TX2, ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF2TX3, ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF2TX4, ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF2TX5, ARIZONA_AIF2TX5MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF2TX6, ARIZONA_AIF2TX6MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF3TX1, ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF3TX2, ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SLIMTX1, ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SLIMTX2, ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SLIMTX3, ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SLIMTX4, ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SLIMTX5, ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SLIMTX6, ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SLIMTX7, ARIZONA_SLIMTX7MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SLIMTX8, ARIZONA_SLIMTX8MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ASRC1L, ARIZONA_ASRC1LMIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ASRC1R, ARIZONA_ASRC1RMIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ASRC2L, ARIZONA_ASRC2LMIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ASRC2R, ARIZONA_ASRC2RMIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC1INT1, ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC1INT2, ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC1INT3, ARIZONA_ISRC1INT3MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC1INT4, ARIZONA_ISRC1INT4MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC1DEC1, ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC1DEC2, ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC1DEC3, ARIZONA_ISRC1DEC3MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC1DEC4, ARIZONA_ISRC1DEC4MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC2INT1, ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC2INT2, ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC2INT3, ARIZONA_ISRC2INT3MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC2INT4, ARIZONA_ISRC2INT4MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC2DEC1, ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC2DEC2, ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC2DEC3, ARIZONA_ISRC2DEC3MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC2DEC4, ARIZONA_ISRC2DEC4MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC3INT1, ARIZONA_ISRC3INT1MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC3INT2, ARIZONA_ISRC3INT2MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC3INT3, ARIZONA_ISRC3INT3MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC3INT4, ARIZONA_ISRC3INT4MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC3DEC1, ARIZONA_ISRC3DEC1MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC3DEC2, ARIZONA_ISRC3DEC2MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC3DEC3, ARIZONA_ISRC3DEC3MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC3DEC4, ARIZONA_ISRC3DEC4MIX_INPUT_1_SOURCE);
static const char * const wm5110_aec_loopback_texts[] = {
"HPOUT1L", "HPOUT1R", "HPOUT2L", "HPOUT2R", "HPOUT3L", "HPOUT3R",
"SPKOUTL", "SPKOUTR", "SPKDAT1L", "SPKDAT1R", "SPKDAT2L", "SPKDAT2R",
};
static const unsigned int wm5110_aec_loopback_values[] = {
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,
};
static const struct soc_enum wm5110_aec_loopback =
SOC_VALUE_ENUM_SINGLE(ARIZONA_DAC_AEC_CONTROL_1,
ARIZONA_AEC_LOOPBACK_SRC_SHIFT, 0xf,
ARRAY_SIZE(wm5110_aec_loopback_texts),
wm5110_aec_loopback_texts,
wm5110_aec_loopback_values);
static const struct snd_kcontrol_new wm5110_aec_loopback_mux =
SOC_DAPM_ENUM("AEC Loopback", wm5110_aec_loopback);
static const struct snd_kcontrol_new wm5110_anc_input_mux[] = {
SOC_DAPM_ENUM("RXANCL Input", arizona_anc_input_src[0]),
SOC_DAPM_ENUM("RXANCL Channel", arizona_anc_input_src[1]),
SOC_DAPM_ENUM("RXANCR Input", arizona_anc_input_src[2]),
SOC_DAPM_ENUM("RXANCR Channel", arizona_anc_input_src[3]),
};
static const struct snd_kcontrol_new wm5110_anc_ng_mux =
SOC_DAPM_ENUM("RXANC NG Source", arizona_anc_ng_enum);
static const struct snd_kcontrol_new wm5110_output_anc_src[] = {
SOC_DAPM_ENUM("HPOUT1L ANC Source", arizona_output_anc_src[0]),
SOC_DAPM_ENUM("HPOUT1R ANC Source", arizona_output_anc_src[1]),
SOC_DAPM_ENUM("HPOUT2L ANC Source", arizona_output_anc_src[2]),
SOC_DAPM_ENUM("HPOUT2R ANC Source", arizona_output_anc_src[3]),
SOC_DAPM_ENUM("HPOUT3L ANC Source", arizona_output_anc_src[4]),
SOC_DAPM_ENUM("HPOUT3R ANC Source", arizona_output_anc_src[5]),
SOC_DAPM_ENUM("SPKOUTL ANC Source", arizona_output_anc_src[6]),
SOC_DAPM_ENUM("SPKOUTR ANC Source", arizona_output_anc_src[7]),
SOC_DAPM_ENUM("SPKDAT1L ANC Source", arizona_output_anc_src[8]),
SOC_DAPM_ENUM("SPKDAT1R ANC Source", arizona_output_anc_src[9]),
SOC_DAPM_ENUM("SPKDAT2L ANC Source", arizona_output_anc_src[10]),
SOC_DAPM_ENUM("SPKDAT2R ANC Source", arizona_output_anc_src[11]),
};
static const struct snd_soc_dapm_widget wm5110_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("SYSCLK", ARIZONA_SYSTEM_CLOCK_1, ARIZONA_SYSCLK_ENA_SHIFT,
0, wm5110_sysclk_ev, SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("ASYNCCLK", ARIZONA_ASYNC_CLOCK_1,
ARIZONA_ASYNC_CLK_ENA_SHIFT, 0, arizona_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("OPCLK", ARIZONA_OUTPUT_SYSTEM_CLOCK,
ARIZONA_OPCLK_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ASYNCOPCLK", ARIZONA_OUTPUT_ASYNC_CLOCK,
ARIZONA_OPCLK_ASYNC_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD2", 0, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD3", 0, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("MICVDD", 0, SND_SOC_DAPM_REGULATOR_BYPASS),
SND_SOC_DAPM_REGULATOR_SUPPLY("SPKVDDL", 0, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("SPKVDDR", 0, 0),
SND_SOC_DAPM_SIGGEN("TONE"),
SND_SOC_DAPM_SIGGEN("NOISE"),
SND_SOC_DAPM_SIGGEN("HAPTICS"),
SND_SOC_DAPM_INPUT("IN1L"),
SND_SOC_DAPM_INPUT("IN1R"),
SND_SOC_DAPM_INPUT("IN2L"),
SND_SOC_DAPM_INPUT("IN2R"),
SND_SOC_DAPM_INPUT("IN3L"),
SND_SOC_DAPM_INPUT("IN3R"),
SND_SOC_DAPM_INPUT("IN4L"),
SND_SOC_DAPM_INPUT("IN4R"),
SND_SOC_DAPM_OUTPUT("DRC1 Signal Activity"),
SND_SOC_DAPM_OUTPUT("DRC2 Signal Activity"),
SND_SOC_DAPM_OUTPUT("DSP Voice Trigger"),
SND_SOC_DAPM_SWITCH("DSP3 Voice Trigger", SND_SOC_NOPM, 2, 0,
&arizona_voice_trigger_switch[2]),
SND_SOC_DAPM_PGA_E("IN1L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN1L_ENA_SHIFT,
0, NULL, 0, wm5110_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_WILL_PMU),
SND_SOC_DAPM_PGA_E("IN1R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN1R_ENA_SHIFT,
0, NULL, 0, wm5110_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_WILL_PMU),
SND_SOC_DAPM_PGA_E("IN2L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN2L_ENA_SHIFT,
0, NULL, 0, wm5110_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_WILL_PMU),
SND_SOC_DAPM_PGA_E("IN2R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN2R_ENA_SHIFT,
0, NULL, 0, wm5110_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_WILL_PMU),
SND_SOC_DAPM_PGA_E("IN3L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN3L_ENA_SHIFT,
0, NULL, 0, wm5110_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_WILL_PMU),
SND_SOC_DAPM_PGA_E("IN3R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN3R_ENA_SHIFT,
0, NULL, 0, wm5110_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_WILL_PMU),
SND_SOC_DAPM_PGA_E("IN4L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN4L_ENA_SHIFT,
0, NULL, 0, arizona_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN4R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN4R_ENA_SHIFT,
0, NULL, 0, arizona_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY("MICBIAS1", ARIZONA_MIC_BIAS_CTRL_1,
ARIZONA_MICB1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS2", ARIZONA_MIC_BIAS_CTRL_2,
ARIZONA_MICB1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS3", ARIZONA_MIC_BIAS_CTRL_3,
ARIZONA_MICB1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("Noise Generator", ARIZONA_COMFORT_NOISE_GENERATOR,
ARIZONA_NOISE_GEN_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("Tone Generator 1", ARIZONA_TONE_GENERATOR_1,
ARIZONA_TONE1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("Tone Generator 2", ARIZONA_TONE_GENERATOR_1,
ARIZONA_TONE2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("Mic Mute Mixer", ARIZONA_MIC_NOISE_MIX_CONTROL_1,
ARIZONA_MICMUTE_MIX_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ1", ARIZONA_EQ1_1, ARIZONA_EQ1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ2", ARIZONA_EQ2_1, ARIZONA_EQ2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ3", ARIZONA_EQ3_1, ARIZONA_EQ3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ4", ARIZONA_EQ4_1, ARIZONA_EQ4_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("DRC1L", ARIZONA_DRC1_CTRL1, ARIZONA_DRC1L_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("DRC1R", ARIZONA_DRC1_CTRL1, ARIZONA_DRC1R_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("DRC2L", ARIZONA_DRC2_CTRL1, ARIZONA_DRC2L_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("DRC2R", ARIZONA_DRC2_CTRL1, ARIZONA_DRC2R_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF1", ARIZONA_HPLPF1_1, ARIZONA_LHPF1_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF2", ARIZONA_HPLPF2_1, ARIZONA_LHPF2_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF3", ARIZONA_HPLPF3_1, ARIZONA_LHPF3_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF4", ARIZONA_HPLPF4_1, ARIZONA_LHPF4_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("PWM1 Driver", ARIZONA_PWM_DRIVE_1, ARIZONA_PWM1_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA("PWM2 Driver", ARIZONA_PWM_DRIVE_1, ARIZONA_PWM2_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA("ASRC1L", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC1L_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("ASRC1R", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC1R_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("ASRC2L", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC2L_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("ASRC2R", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC2R_ENA_SHIFT, 0,
NULL, 0),
WM_ADSP2("DSP1", 0, wm5110_adsp_power_ev),
WM_ADSP2("DSP2", 1, wm5110_adsp_power_ev),
WM_ADSP2("DSP3", 2, wm5110_adsp_power_ev),
WM_ADSP2("DSP4", 3, wm5110_adsp_power_ev),
SND_SOC_DAPM_PGA("ISRC1INT1", ARIZONA_ISRC_1_CTRL_3,
ARIZONA_ISRC1_INT0_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1INT2", ARIZONA_ISRC_1_CTRL_3,
ARIZONA_ISRC1_INT1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1INT3", ARIZONA_ISRC_1_CTRL_3,
ARIZONA_ISRC1_INT2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1INT4", ARIZONA_ISRC_1_CTRL_3,
ARIZONA_ISRC1_INT3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC1", ARIZONA_ISRC_1_CTRL_3,
ARIZONA_ISRC1_DEC0_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC2", ARIZONA_ISRC_1_CTRL_3,
ARIZONA_ISRC1_DEC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC3", ARIZONA_ISRC_1_CTRL_3,
ARIZONA_ISRC1_DEC2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC4", ARIZONA_ISRC_1_CTRL_3,
ARIZONA_ISRC1_DEC3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2INT1", ARIZONA_ISRC_2_CTRL_3,
ARIZONA_ISRC2_INT0_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2INT2", ARIZONA_ISRC_2_CTRL_3,
ARIZONA_ISRC2_INT1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2INT3", ARIZONA_ISRC_2_CTRL_3,
ARIZONA_ISRC2_INT2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2INT4", ARIZONA_ISRC_2_CTRL_3,
ARIZONA_ISRC2_INT3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2DEC1", ARIZONA_ISRC_2_CTRL_3,
ARIZONA_ISRC2_DEC0_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2DEC2", ARIZONA_ISRC_2_CTRL_3,
ARIZONA_ISRC2_DEC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2DEC3", ARIZONA_ISRC_2_CTRL_3,
ARIZONA_ISRC2_DEC2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2DEC4", ARIZONA_ISRC_2_CTRL_3,
ARIZONA_ISRC2_DEC3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC3INT1", ARIZONA_ISRC_3_CTRL_3,
ARIZONA_ISRC3_INT0_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC3INT2", ARIZONA_ISRC_3_CTRL_3,
ARIZONA_ISRC3_INT1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC3INT3", ARIZONA_ISRC_3_CTRL_3,
ARIZONA_ISRC3_INT2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC3INT4", ARIZONA_ISRC_3_CTRL_3,
ARIZONA_ISRC3_INT3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC3DEC1", ARIZONA_ISRC_3_CTRL_3,
ARIZONA_ISRC3_DEC0_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC3DEC2", ARIZONA_ISRC_3_CTRL_3,
ARIZONA_ISRC3_DEC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC3DEC3", ARIZONA_ISRC_3_CTRL_3,
ARIZONA_ISRC3_DEC2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC3DEC4", ARIZONA_ISRC_3_CTRL_3,
ARIZONA_ISRC3_DEC3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_MUX("AEC Loopback", ARIZONA_DAC_AEC_CONTROL_1,
ARIZONA_AEC_LOOPBACK_ENA_SHIFT, 0, &wm5110_aec_loopback_mux),
SND_SOC_DAPM_SUPPLY("RXANC NG External Clock", SND_SOC_NOPM,
ARIZONA_EXT_NG_SEL_SET_SHIFT, 0, arizona_anc_ev,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA("RXANCL NG External", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("RXANCR NG External", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("RXANC NG Clock", SND_SOC_NOPM,
ARIZONA_CLK_NG_ENA_SET_SHIFT, 0, arizona_anc_ev,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA("RXANCL NG Internal", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("RXANCR NG Internal", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX("RXANCL Left Input", SND_SOC_NOPM, 0, 0,
&wm5110_anc_input_mux[0]),
SND_SOC_DAPM_MUX("RXANCL Right Input", SND_SOC_NOPM, 0, 0,
&wm5110_anc_input_mux[0]),
SND_SOC_DAPM_MUX("RXANCL Channel", SND_SOC_NOPM, 0, 0,
&wm5110_anc_input_mux[1]),
SND_SOC_DAPM_MUX("RXANCL NG Mux", SND_SOC_NOPM, 0, 0, &wm5110_anc_ng_mux),
SND_SOC_DAPM_MUX("RXANCR Left Input", SND_SOC_NOPM, 0, 0,
&wm5110_anc_input_mux[2]),
SND_SOC_DAPM_MUX("RXANCR Right Input", SND_SOC_NOPM, 0, 0,
&wm5110_anc_input_mux[2]),
SND_SOC_DAPM_MUX("RXANCR Channel", SND_SOC_NOPM, 0, 0,
&wm5110_anc_input_mux[3]),
SND_SOC_DAPM_MUX("RXANCR NG Mux", SND_SOC_NOPM, 0, 0, &wm5110_anc_ng_mux),
SND_SOC_DAPM_PGA_E("RXANCL", SND_SOC_NOPM, ARIZONA_CLK_L_ENA_SET_SHIFT,
0, NULL, 0, arizona_anc_ev,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA_E("RXANCR", SND_SOC_NOPM, ARIZONA_CLK_R_ENA_SET_SHIFT,
0, NULL, 0, arizona_anc_ev,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_MUX("HPOUT1L ANC Source", SND_SOC_NOPM, 0, 0,
&wm5110_output_anc_src[0]),
SND_SOC_DAPM_MUX("HPOUT1R ANC Source", SND_SOC_NOPM, 0, 0,
&wm5110_output_anc_src[1]),
SND_SOC_DAPM_MUX("HPOUT2L ANC Source", SND_SOC_NOPM, 0, 0,
&wm5110_output_anc_src[2]),
SND_SOC_DAPM_MUX("HPOUT2R ANC Source", SND_SOC_NOPM, 0, 0,
&wm5110_output_anc_src[3]),
SND_SOC_DAPM_MUX("HPOUT3L ANC Source", SND_SOC_NOPM, 0, 0,
&wm5110_output_anc_src[4]),
SND_SOC_DAPM_MUX("HPOUT3R ANC Source", SND_SOC_NOPM, 0, 0,
&wm5110_output_anc_src[5]),
SND_SOC_DAPM_MUX("SPKOUTL ANC Source", SND_SOC_NOPM, 0, 0,
&wm5110_output_anc_src[6]),
SND_SOC_DAPM_MUX("SPKOUTR ANC Source", SND_SOC_NOPM, 0, 0,
&wm5110_output_anc_src[7]),
SND_SOC_DAPM_MUX("SPKDAT1L ANC Source", SND_SOC_NOPM, 0, 0,
&wm5110_output_anc_src[8]),
SND_SOC_DAPM_MUX("SPKDAT1R ANC Source", SND_SOC_NOPM, 0, 0,
&wm5110_output_anc_src[9]),
SND_SOC_DAPM_MUX("SPKDAT2L ANC Source", SND_SOC_NOPM, 0, 0,
&wm5110_output_anc_src[10]),
SND_SOC_DAPM_MUX("SPKDAT2R ANC Source", SND_SOC_NOPM, 0, 0,
&wm5110_output_anc_src[11]),
SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 0,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 1,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 2,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 3,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 4,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX6", NULL, 5,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX7", NULL, 6,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX7_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX8", NULL, 7,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX8_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 0,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 1,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 2,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 3,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 4,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX6", NULL, 5,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX7", NULL, 6,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX7_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX8", NULL, 7,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX8_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0,
ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX2", NULL, 1,
ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX3", NULL, 2,
ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX4", NULL, 3,
ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX5", NULL, 4,
ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX6", NULL, 5,
ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0,
ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX2", NULL, 1,
ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX3", NULL, 2,
ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX4", NULL, 3,
ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX5", NULL, 4,
ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX6", NULL, 5,
ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX1", NULL, 0,
ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE,
ARIZONA_SLIMRX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX2", NULL, 1,
ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE,
ARIZONA_SLIMRX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX3", NULL, 2,
ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE,
ARIZONA_SLIMRX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX4", NULL, 3,
ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE,
ARIZONA_SLIMRX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX5", NULL, 4,
ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE,
ARIZONA_SLIMRX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX6", NULL, 5,
ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE,
ARIZONA_SLIMRX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX7", NULL, 6,
ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE,
ARIZONA_SLIMRX7_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX8", NULL, 7,
ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE,
ARIZONA_SLIMRX8_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX1", NULL, 0,
ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE,
ARIZONA_SLIMTX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX2", NULL, 1,
ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE,
ARIZONA_SLIMTX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX3", NULL, 2,
ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE,
ARIZONA_SLIMTX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX4", NULL, 3,
ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE,
ARIZONA_SLIMTX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX5", NULL, 4,
ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE,
ARIZONA_SLIMTX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX6", NULL, 5,
ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE,
ARIZONA_SLIMTX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX7", NULL, 6,
ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE,
ARIZONA_SLIMTX7_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX8", NULL, 7,
ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE,
ARIZONA_SLIMTX8_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF3TX1", NULL, 0,
ARIZONA_AIF3_TX_ENABLES, ARIZONA_AIF3TX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF3TX2", NULL, 1,
ARIZONA_AIF3_TX_ENABLES, ARIZONA_AIF3TX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF3RX1", NULL, 0,
ARIZONA_AIF3_RX_ENABLES, ARIZONA_AIF3RX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF3RX2", NULL, 1,
ARIZONA_AIF3_RX_ENABLES, ARIZONA_AIF3RX2_ENA_SHIFT, 0),
SND_SOC_DAPM_PGA_E("OUT1L", SND_SOC_NOPM,
ARIZONA_OUT1L_ENA_SHIFT, 0, NULL, 0, wm5110_hp_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT1R", SND_SOC_NOPM,
ARIZONA_OUT1R_ENA_SHIFT, 0, NULL, 0, wm5110_hp_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT2L", ARIZONA_OUTPUT_ENABLES_1,
ARIZONA_OUT2L_ENA_SHIFT, 0, NULL, 0, arizona_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT2R", ARIZONA_OUTPUT_ENABLES_1,
ARIZONA_OUT2R_ENA_SHIFT, 0, NULL, 0, arizona_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT3L", ARIZONA_OUTPUT_ENABLES_1,
ARIZONA_OUT3L_ENA_SHIFT, 0, NULL, 0, arizona_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT3R", ARIZONA_OUTPUT_ENABLES_1,
ARIZONA_OUT3R_ENA_SHIFT, 0, NULL, 0, arizona_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT5L", ARIZONA_OUTPUT_ENABLES_1,
ARIZONA_OUT5L_ENA_SHIFT, 0, NULL, 0, arizona_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT5R", ARIZONA_OUTPUT_ENABLES_1,
ARIZONA_OUT5R_ENA_SHIFT, 0, NULL, 0, arizona_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT6L", ARIZONA_OUTPUT_ENABLES_1,
ARIZONA_OUT6L_ENA_SHIFT, 0, NULL, 0, arizona_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT6R", ARIZONA_OUTPUT_ENABLES_1,
ARIZONA_OUT6R_ENA_SHIFT, 0, NULL, 0, arizona_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
ARIZONA_MIXER_WIDGETS(EQ1, "EQ1"),
ARIZONA_MIXER_WIDGETS(EQ2, "EQ2"),
ARIZONA_MIXER_WIDGETS(EQ3, "EQ3"),
ARIZONA_MIXER_WIDGETS(EQ4, "EQ4"),
ARIZONA_MIXER_WIDGETS(DRC1L, "DRC1L"),
ARIZONA_MIXER_WIDGETS(DRC1R, "DRC1R"),
ARIZONA_MIXER_WIDGETS(DRC2L, "DRC2L"),
ARIZONA_MIXER_WIDGETS(DRC2R, "DRC2R"),
ARIZONA_MIXER_WIDGETS(LHPF1, "LHPF1"),
ARIZONA_MIXER_WIDGETS(LHPF2, "LHPF2"),
ARIZONA_MIXER_WIDGETS(LHPF3, "LHPF3"),
ARIZONA_MIXER_WIDGETS(LHPF4, "LHPF4"),
ARIZONA_MIXER_WIDGETS(Mic, "Mic"),
ARIZONA_MIXER_WIDGETS(Noise, "Noise"),
ARIZONA_MIXER_WIDGETS(PWM1, "PWM1"),
ARIZONA_MIXER_WIDGETS(PWM2, "PWM2"),
ARIZONA_MIXER_WIDGETS(OUT1L, "HPOUT1L"),
ARIZONA_MIXER_WIDGETS(OUT1R, "HPOUT1R"),
ARIZONA_MIXER_WIDGETS(OUT2L, "HPOUT2L"),
ARIZONA_MIXER_WIDGETS(OUT2R, "HPOUT2R"),
ARIZONA_MIXER_WIDGETS(OUT3L, "HPOUT3L"),
ARIZONA_MIXER_WIDGETS(OUT3R, "HPOUT3R"),
ARIZONA_MIXER_WIDGETS(SPKOUTL, "SPKOUTL"),
ARIZONA_MIXER_WIDGETS(SPKOUTR, "SPKOUTR"),
ARIZONA_MIXER_WIDGETS(SPKDAT1L, "SPKDAT1L"),
ARIZONA_MIXER_WIDGETS(SPKDAT1R, "SPKDAT1R"),
ARIZONA_MIXER_WIDGETS(SPKDAT2L, "SPKDAT2L"),
ARIZONA_MIXER_WIDGETS(SPKDAT2R, "SPKDAT2R"),
ARIZONA_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"),
ARIZONA_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"),
ARIZONA_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"),
ARIZONA_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"),
ARIZONA_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"),
ARIZONA_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"),
ARIZONA_MIXER_WIDGETS(AIF1TX7, "AIF1TX7"),
ARIZONA_MIXER_WIDGETS(AIF1TX8, "AIF1TX8"),
ARIZONA_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"),
ARIZONA_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"),
ARIZONA_MIXER_WIDGETS(AIF2TX3, "AIF2TX3"),
ARIZONA_MIXER_WIDGETS(AIF2TX4, "AIF2TX4"),
ARIZONA_MIXER_WIDGETS(AIF2TX5, "AIF2TX5"),
ARIZONA_MIXER_WIDGETS(AIF2TX6, "AIF2TX6"),
ARIZONA_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"),
ARIZONA_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"),
ARIZONA_MIXER_WIDGETS(SLIMTX1, "SLIMTX1"),
ARIZONA_MIXER_WIDGETS(SLIMTX2, "SLIMTX2"),
ARIZONA_MIXER_WIDGETS(SLIMTX3, "SLIMTX3"),
ARIZONA_MIXER_WIDGETS(SLIMTX4, "SLIMTX4"),
ARIZONA_MIXER_WIDGETS(SLIMTX5, "SLIMTX5"),
ARIZONA_MIXER_WIDGETS(SLIMTX6, "SLIMTX6"),
ARIZONA_MIXER_WIDGETS(SLIMTX7, "SLIMTX7"),
ARIZONA_MIXER_WIDGETS(SLIMTX8, "SLIMTX8"),
ARIZONA_MUX_WIDGETS(ASRC1L, "ASRC1L"),
ARIZONA_MUX_WIDGETS(ASRC1R, "ASRC1R"),
ARIZONA_MUX_WIDGETS(ASRC2L, "ASRC2L"),
ARIZONA_MUX_WIDGETS(ASRC2R, "ASRC2R"),
ARIZONA_DSP_WIDGETS(DSP1, "DSP1"),
ARIZONA_DSP_WIDGETS(DSP2, "DSP2"),
ARIZONA_DSP_WIDGETS(DSP3, "DSP3"),
ARIZONA_DSP_WIDGETS(DSP4, "DSP4"),
ARIZONA_MUX_WIDGETS(ISRC1DEC1, "ISRC1DEC1"),
ARIZONA_MUX_WIDGETS(ISRC1DEC2, "ISRC1DEC2"),
ARIZONA_MUX_WIDGETS(ISRC1DEC3, "ISRC1DEC3"),
ARIZONA_MUX_WIDGETS(ISRC1DEC4, "ISRC1DEC4"),
ARIZONA_MUX_WIDGETS(ISRC1INT1, "ISRC1INT1"),
ARIZONA_MUX_WIDGETS(ISRC1INT2, "ISRC1INT2"),
ARIZONA_MUX_WIDGETS(ISRC1INT3, "ISRC1INT3"),
ARIZONA_MUX_WIDGETS(ISRC1INT4, "ISRC1INT4"),
ARIZONA_MUX_WIDGETS(ISRC2DEC1, "ISRC2DEC1"),
ARIZONA_MUX_WIDGETS(ISRC2DEC2, "ISRC2DEC2"),
ARIZONA_MUX_WIDGETS(ISRC2DEC3, "ISRC2DEC3"),
ARIZONA_MUX_WIDGETS(ISRC2DEC4, "ISRC2DEC4"),
ARIZONA_MUX_WIDGETS(ISRC2INT1, "ISRC2INT1"),
ARIZONA_MUX_WIDGETS(ISRC2INT2, "ISRC2INT2"),
ARIZONA_MUX_WIDGETS(ISRC2INT3, "ISRC2INT3"),
ARIZONA_MUX_WIDGETS(ISRC2INT4, "ISRC2INT4"),
ARIZONA_MUX_WIDGETS(ISRC3DEC1, "ISRC3DEC1"),
ARIZONA_MUX_WIDGETS(ISRC3DEC2, "ISRC3DEC2"),
ARIZONA_MUX_WIDGETS(ISRC3DEC3, "ISRC3DEC3"),
ARIZONA_MUX_WIDGETS(ISRC3DEC4, "ISRC3DEC4"),
ARIZONA_MUX_WIDGETS(ISRC3INT1, "ISRC3INT1"),
ARIZONA_MUX_WIDGETS(ISRC3INT2, "ISRC3INT2"),
ARIZONA_MUX_WIDGETS(ISRC3INT3, "ISRC3INT3"),
ARIZONA_MUX_WIDGETS(ISRC3INT4, "ISRC3INT4"),
SND_SOC_DAPM_OUTPUT("HPOUT1L"),
SND_SOC_DAPM_OUTPUT("HPOUT1R"),
SND_SOC_DAPM_OUTPUT("HPOUT2L"),
SND_SOC_DAPM_OUTPUT("HPOUT2R"),
SND_SOC_DAPM_OUTPUT("HPOUT3L"),
SND_SOC_DAPM_OUTPUT("HPOUT3R"),
SND_SOC_DAPM_OUTPUT("SPKOUTLN"),
SND_SOC_DAPM_OUTPUT("SPKOUTLP"),
SND_SOC_DAPM_OUTPUT("SPKOUTRN"),
SND_SOC_DAPM_OUTPUT("SPKOUTRP"),
SND_SOC_DAPM_OUTPUT("SPKDAT1L"),
SND_SOC_DAPM_OUTPUT("SPKDAT1R"),
SND_SOC_DAPM_OUTPUT("SPKDAT2L"),
SND_SOC_DAPM_OUTPUT("SPKDAT2R"),
SND_SOC_DAPM_OUTPUT("MICSUPP"),
};
#define ARIZONA_MIXER_INPUT_ROUTES(name) \
{ name, "Noise Generator", "Noise Generator" }, \
{ name, "Tone Generator 1", "Tone Generator 1" }, \
{ name, "Tone Generator 2", "Tone Generator 2" }, \
{ name, "Haptics", "HAPTICS" }, \
{ name, "AEC", "AEC Loopback" }, \
{ name, "IN1L", "IN1L PGA" }, \
{ name, "IN1R", "IN1R PGA" }, \
{ name, "IN2L", "IN2L PGA" }, \
{ name, "IN2R", "IN2R PGA" }, \
{ name, "IN3L", "IN3L PGA" }, \
{ name, "IN3R", "IN3R PGA" }, \
{ name, "IN4L", "IN4L PGA" }, \
{ name, "IN4R", "IN4R PGA" }, \
{ name, "Mic Mute Mixer", "Mic Mute Mixer" }, \
{ name, "AIF1RX1", "AIF1RX1" }, \
{ name, "AIF1RX2", "AIF1RX2" }, \
{ name, "AIF1RX3", "AIF1RX3" }, \
{ name, "AIF1RX4", "AIF1RX4" }, \
{ name, "AIF1RX5", "AIF1RX5" }, \
{ name, "AIF1RX6", "AIF1RX6" }, \
{ name, "AIF1RX7", "AIF1RX7" }, \
{ name, "AIF1RX8", "AIF1RX8" }, \
{ name, "AIF2RX1", "AIF2RX1" }, \
{ name, "AIF2RX2", "AIF2RX2" }, \
{ name, "AIF2RX3", "AIF2RX3" }, \
{ name, "AIF2RX4", "AIF2RX4" }, \
{ name, "AIF2RX5", "AIF2RX5" }, \
{ name, "AIF2RX6", "AIF2RX6" }, \
{ name, "AIF3RX1", "AIF3RX1" }, \
{ name, "AIF3RX2", "AIF3RX2" }, \
{ name, "SLIMRX1", "SLIMRX1" }, \
{ name, "SLIMRX2", "SLIMRX2" }, \
{ name, "SLIMRX3", "SLIMRX3" }, \
{ name, "SLIMRX4", "SLIMRX4" }, \
{ name, "SLIMRX5", "SLIMRX5" }, \
{ name, "SLIMRX6", "SLIMRX6" }, \
{ name, "SLIMRX7", "SLIMRX7" }, \
{ name, "SLIMRX8", "SLIMRX8" }, \
{ name, "EQ1", "EQ1" }, \
{ name, "EQ2", "EQ2" }, \
{ name, "EQ3", "EQ3" }, \
{ name, "EQ4", "EQ4" }, \
{ name, "DRC1L", "DRC1L" }, \
{ name, "DRC1R", "DRC1R" }, \
{ name, "DRC2L", "DRC2L" }, \
{ name, "DRC2R", "DRC2R" }, \
{ name, "LHPF1", "LHPF1" }, \
{ name, "LHPF2", "LHPF2" }, \
{ name, "LHPF3", "LHPF3" }, \
{ name, "LHPF4", "LHPF4" }, \
{ name, "ASRC1L", "ASRC1L" }, \
{ name, "ASRC1R", "ASRC1R" }, \
{ name, "ASRC2L", "ASRC2L" }, \
{ name, "ASRC2R", "ASRC2R" }, \
{ name, "ISRC1DEC1", "ISRC1DEC1" }, \
{ name, "ISRC1DEC2", "ISRC1DEC2" }, \
{ name, "ISRC1DEC3", "ISRC1DEC3" }, \
{ name, "ISRC1DEC4", "ISRC1DEC4" }, \
{ name, "ISRC1INT1", "ISRC1INT1" }, \
{ name, "ISRC1INT2", "ISRC1INT2" }, \
{ name, "ISRC1INT3", "ISRC1INT3" }, \
{ name, "ISRC1INT4", "ISRC1INT4" }, \
{ name, "ISRC2DEC1", "ISRC2DEC1" }, \
{ name, "ISRC2DEC2", "ISRC2DEC2" }, \
{ name, "ISRC2DEC3", "ISRC2DEC3" }, \
{ name, "ISRC2DEC4", "ISRC2DEC4" }, \
{ name, "ISRC2INT1", "ISRC2INT1" }, \
{ name, "ISRC2INT2", "ISRC2INT2" }, \
{ name, "ISRC2INT3", "ISRC2INT3" }, \
{ name, "ISRC2INT4", "ISRC2INT4" }, \
{ name, "ISRC3DEC1", "ISRC3DEC1" }, \
{ name, "ISRC3DEC2", "ISRC3DEC2" }, \
{ name, "ISRC3DEC3", "ISRC3DEC3" }, \
{ name, "ISRC3DEC4", "ISRC3DEC4" }, \
{ name, "ISRC3INT1", "ISRC3INT1" }, \
{ name, "ISRC3INT2", "ISRC3INT2" }, \
{ name, "ISRC3INT3", "ISRC3INT3" }, \
{ name, "ISRC3INT4", "ISRC3INT4" }, \
{ name, "DSP1.1", "DSP1" }, \
{ name, "DSP1.2", "DSP1" }, \
{ name, "DSP1.3", "DSP1" }, \
{ name, "DSP1.4", "DSP1" }, \
{ name, "DSP1.5", "DSP1" }, \
{ name, "DSP1.6", "DSP1" }, \
{ name, "DSP2.1", "DSP2" }, \
{ name, "DSP2.2", "DSP2" }, \
{ name, "DSP2.3", "DSP2" }, \
{ name, "DSP2.4", "DSP2" }, \
{ name, "DSP2.5", "DSP2" }, \
{ name, "DSP2.6", "DSP2" }, \
{ name, "DSP3.1", "DSP3" }, \
{ name, "DSP3.2", "DSP3" }, \
{ name, "DSP3.3", "DSP3" }, \
{ name, "DSP3.4", "DSP3" }, \
{ name, "DSP3.5", "DSP3" }, \
{ name, "DSP3.6", "DSP3" }, \
{ name, "DSP4.1", "DSP4" }, \
{ name, "DSP4.2", "DSP4" }, \
{ name, "DSP4.3", "DSP4" }, \
{ name, "DSP4.4", "DSP4" }, \
{ name, "DSP4.5", "DSP4" }, \
{ name, "DSP4.6", "DSP4" }
static const struct snd_soc_dapm_route wm5110_dapm_routes[] = {
{ "AIF2 Capture", NULL, "DBVDD2" },
{ "AIF2 Playback", NULL, "DBVDD2" },
{ "AIF3 Capture", NULL, "DBVDD3" },
{ "AIF3 Playback", NULL, "DBVDD3" },
{ "OUT1L", NULL, "CPVDD" },
{ "OUT1R", NULL, "CPVDD" },
{ "OUT2L", NULL, "CPVDD" },
{ "OUT2R", NULL, "CPVDD" },
{ "OUT3L", NULL, "CPVDD" },
{ "OUT3R", NULL, "CPVDD" },
{ "OUT4L", NULL, "SPKVDDL" },
{ "OUT4R", NULL, "SPKVDDR" },
{ "OUT1L", NULL, "SYSCLK" },
{ "OUT1R", NULL, "SYSCLK" },
{ "OUT2L", NULL, "SYSCLK" },
{ "OUT2R", NULL, "SYSCLK" },
{ "OUT3L", NULL, "SYSCLK" },
{ "OUT3R", NULL, "SYSCLK" },
{ "OUT4L", NULL, "SYSCLK" },
{ "OUT4R", NULL, "SYSCLK" },
{ "OUT5L", NULL, "SYSCLK" },
{ "OUT5R", NULL, "SYSCLK" },
{ "OUT6L", NULL, "SYSCLK" },
{ "OUT6R", NULL, "SYSCLK" },
{ "IN1L", NULL, "SYSCLK" },
{ "IN1R", NULL, "SYSCLK" },
{ "IN2L", NULL, "SYSCLK" },
{ "IN2R", NULL, "SYSCLK" },
{ "IN3L", NULL, "SYSCLK" },
{ "IN3R", NULL, "SYSCLK" },
{ "IN4L", NULL, "SYSCLK" },
{ "IN4R", NULL, "SYSCLK" },
{ "ASRC1L", NULL, "SYSCLK" },
{ "ASRC1R", NULL, "SYSCLK" },
{ "ASRC2L", NULL, "SYSCLK" },
{ "ASRC2R", NULL, "SYSCLK" },
{ "ASRC1L", NULL, "ASYNCCLK" },
{ "ASRC1R", NULL, "ASYNCCLK" },
{ "ASRC2L", NULL, "ASYNCCLK" },
{ "ASRC2R", NULL, "ASYNCCLK" },
{ "MICBIAS1", NULL, "MICVDD" },
{ "MICBIAS2", NULL, "MICVDD" },
{ "MICBIAS3", NULL, "MICVDD" },
{ "Noise Generator", NULL, "SYSCLK" },
{ "Tone Generator 1", NULL, "SYSCLK" },
{ "Tone Generator 2", NULL, "SYSCLK" },
{ "Noise Generator", NULL, "NOISE" },
{ "Tone Generator 1", NULL, "TONE" },
{ "Tone Generator 2", NULL, "TONE" },
{ "AIF1 Capture", NULL, "AIF1TX1" },
{ "AIF1 Capture", NULL, "AIF1TX2" },
{ "AIF1 Capture", NULL, "AIF1TX3" },
{ "AIF1 Capture", NULL, "AIF1TX4" },
{ "AIF1 Capture", NULL, "AIF1TX5" },
{ "AIF1 Capture", NULL, "AIF1TX6" },
{ "AIF1 Capture", NULL, "AIF1TX7" },
{ "AIF1 Capture", NULL, "AIF1TX8" },
{ "AIF1RX1", NULL, "AIF1 Playback" },
{ "AIF1RX2", NULL, "AIF1 Playback" },
{ "AIF1RX3", NULL, "AIF1 Playback" },
{ "AIF1RX4", NULL, "AIF1 Playback" },
{ "AIF1RX5", NULL, "AIF1 Playback" },
{ "AIF1RX6", NULL, "AIF1 Playback" },
{ "AIF1RX7", NULL, "AIF1 Playback" },
{ "AIF1RX8", NULL, "AIF1 Playback" },
{ "AIF2 Capture", NULL, "AIF2TX1" },
{ "AIF2 Capture", NULL, "AIF2TX2" },
{ "AIF2 Capture", NULL, "AIF2TX3" },
{ "AIF2 Capture", NULL, "AIF2TX4" },
{ "AIF2 Capture", NULL, "AIF2TX5" },
{ "AIF2 Capture", NULL, "AIF2TX6" },
{ "AIF2RX1", NULL, "AIF2 Playback" },
{ "AIF2RX2", NULL, "AIF2 Playback" },
{ "AIF2RX3", NULL, "AIF2 Playback" },
{ "AIF2RX4", NULL, "AIF2 Playback" },
{ "AIF2RX5", NULL, "AIF2 Playback" },
{ "AIF2RX6", NULL, "AIF2 Playback" },
{ "AIF3 Capture", NULL, "AIF3TX1" },
{ "AIF3 Capture", NULL, "AIF3TX2" },
{ "AIF3RX1", NULL, "AIF3 Playback" },
{ "AIF3RX2", NULL, "AIF3 Playback" },
{ "Slim1 Capture", NULL, "SLIMTX1" },
{ "Slim1 Capture", NULL, "SLIMTX2" },
{ "Slim1 Capture", NULL, "SLIMTX3" },
{ "Slim1 Capture", NULL, "SLIMTX4" },
{ "SLIMRX1", NULL, "Slim1 Playback" },
{ "SLIMRX2", NULL, "Slim1 Playback" },
{ "SLIMRX3", NULL, "Slim1 Playback" },
{ "SLIMRX4", NULL, "Slim1 Playback" },
{ "Slim2 Capture", NULL, "SLIMTX5" },
{ "Slim2 Capture", NULL, "SLIMTX6" },
{ "SLIMRX5", NULL, "Slim2 Playback" },
{ "SLIMRX6", NULL, "Slim2 Playback" },
{ "Slim3 Capture", NULL, "SLIMTX7" },
{ "Slim3 Capture", NULL, "SLIMTX8" },
{ "SLIMRX7", NULL, "Slim3 Playback" },
{ "SLIMRX8", NULL, "Slim3 Playback" },
{ "AIF1 Playback", NULL, "SYSCLK" },
{ "AIF2 Playback", NULL, "SYSCLK" },
{ "AIF3 Playback", NULL, "SYSCLK" },
{ "Slim1 Playback", NULL, "SYSCLK" },
{ "Slim2 Playback", NULL, "SYSCLK" },
{ "Slim3 Playback", NULL, "SYSCLK" },
{ "AIF1 Capture", NULL, "SYSCLK" },
{ "AIF2 Capture", NULL, "SYSCLK" },
{ "AIF3 Capture", NULL, "SYSCLK" },
{ "Slim1 Capture", NULL, "SYSCLK" },
{ "Slim2 Capture", NULL, "SYSCLK" },
{ "Slim3 Capture", NULL, "SYSCLK" },
{ "Voice Control DSP", NULL, "DSP3" },
{ "Audio Trace DSP", NULL, "DSP1" },
{ "IN1L PGA", NULL, "IN1L" },
{ "IN1R PGA", NULL, "IN1R" },
{ "IN2L PGA", NULL, "IN2L" },
{ "IN2R PGA", NULL, "IN2R" },
{ "IN3L PGA", NULL, "IN3L" },
{ "IN3R PGA", NULL, "IN3R" },
{ "IN4L PGA", NULL, "IN4L" },
{ "IN4R PGA", NULL, "IN4R" },
ARIZONA_MIXER_ROUTES("OUT1L", "HPOUT1L"),
ARIZONA_MIXER_ROUTES("OUT1R", "HPOUT1R"),
ARIZONA_MIXER_ROUTES("OUT2L", "HPOUT2L"),
ARIZONA_MIXER_ROUTES("OUT2R", "HPOUT2R"),
ARIZONA_MIXER_ROUTES("OUT3L", "HPOUT3L"),
ARIZONA_MIXER_ROUTES("OUT3R", "HPOUT3R"),
ARIZONA_MIXER_ROUTES("OUT4L", "SPKOUTL"),
ARIZONA_MIXER_ROUTES("OUT4R", "SPKOUTR"),
ARIZONA_MIXER_ROUTES("OUT5L", "SPKDAT1L"),
ARIZONA_MIXER_ROUTES("OUT5R", "SPKDAT1R"),
ARIZONA_MIXER_ROUTES("OUT6L", "SPKDAT2L"),
ARIZONA_MIXER_ROUTES("OUT6R", "SPKDAT2R"),
ARIZONA_MIXER_ROUTES("PWM1 Driver", "PWM1"),
ARIZONA_MIXER_ROUTES("PWM2 Driver", "PWM2"),
ARIZONA_MIXER_ROUTES("AIF1TX1", "AIF1TX1"),
ARIZONA_MIXER_ROUTES("AIF1TX2", "AIF1TX2"),
ARIZONA_MIXER_ROUTES("AIF1TX3", "AIF1TX3"),
ARIZONA_MIXER_ROUTES("AIF1TX4", "AIF1TX4"),
ARIZONA_MIXER_ROUTES("AIF1TX5", "AIF1TX5"),
ARIZONA_MIXER_ROUTES("AIF1TX6", "AIF1TX6"),
ARIZONA_MIXER_ROUTES("AIF1TX7", "AIF1TX7"),
ARIZONA_MIXER_ROUTES("AIF1TX8", "AIF1TX8"),
ARIZONA_MIXER_ROUTES("AIF2TX1", "AIF2TX1"),
ARIZONA_MIXER_ROUTES("AIF2TX2", "AIF2TX2"),
ARIZONA_MIXER_ROUTES("AIF2TX3", "AIF2TX3"),
ARIZONA_MIXER_ROUTES("AIF2TX4", "AIF2TX4"),
ARIZONA_MIXER_ROUTES("AIF2TX5", "AIF2TX5"),
ARIZONA_MIXER_ROUTES("AIF2TX6", "AIF2TX6"),
ARIZONA_MIXER_ROUTES("AIF3TX1", "AIF3TX1"),
ARIZONA_MIXER_ROUTES("AIF3TX2", "AIF3TX2"),
ARIZONA_MIXER_ROUTES("SLIMTX1", "SLIMTX1"),
ARIZONA_MIXER_ROUTES("SLIMTX2", "SLIMTX2"),
ARIZONA_MIXER_ROUTES("SLIMTX3", "SLIMTX3"),
ARIZONA_MIXER_ROUTES("SLIMTX4", "SLIMTX4"),
ARIZONA_MIXER_ROUTES("SLIMTX5", "SLIMTX5"),
ARIZONA_MIXER_ROUTES("SLIMTX6", "SLIMTX6"),
ARIZONA_MIXER_ROUTES("SLIMTX7", "SLIMTX7"),
ARIZONA_MIXER_ROUTES("SLIMTX8", "SLIMTX8"),
ARIZONA_MIXER_ROUTES("EQ1", "EQ1"),
ARIZONA_MIXER_ROUTES("EQ2", "EQ2"),
ARIZONA_MIXER_ROUTES("EQ3", "EQ3"),
ARIZONA_MIXER_ROUTES("EQ4", "EQ4"),
ARIZONA_MIXER_ROUTES("DRC1L", "DRC1L"),
ARIZONA_MIXER_ROUTES("DRC1R", "DRC1R"),
ARIZONA_MIXER_ROUTES("DRC2L", "DRC2L"),
ARIZONA_MIXER_ROUTES("DRC2R", "DRC2R"),
ARIZONA_MIXER_ROUTES("LHPF1", "LHPF1"),
ARIZONA_MIXER_ROUTES("LHPF2", "LHPF2"),
ARIZONA_MIXER_ROUTES("LHPF3", "LHPF3"),
ARIZONA_MIXER_ROUTES("LHPF4", "LHPF4"),
ARIZONA_MIXER_ROUTES("Mic Mute Mixer", "Noise"),
ARIZONA_MIXER_ROUTES("Mic Mute Mixer", "Mic"),
ARIZONA_MUX_ROUTES("ASRC1L", "ASRC1L"),
ARIZONA_MUX_ROUTES("ASRC1R", "ASRC1R"),
ARIZONA_MUX_ROUTES("ASRC2L", "ASRC2L"),
ARIZONA_MUX_ROUTES("ASRC2R", "ASRC2R"),
ARIZONA_DSP_ROUTES("DSP1"),
ARIZONA_DSP_ROUTES("DSP2"),
ARIZONA_DSP_ROUTES("DSP3"),
ARIZONA_DSP_ROUTES("DSP4"),
ARIZONA_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"),
ARIZONA_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"),
ARIZONA_MUX_ROUTES("ISRC1INT3", "ISRC1INT3"),
ARIZONA_MUX_ROUTES("ISRC1INT4", "ISRC1INT4"),
ARIZONA_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"),
ARIZONA_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"),
ARIZONA_MUX_ROUTES("ISRC1DEC3", "ISRC1DEC3"),
ARIZONA_MUX_ROUTES("ISRC1DEC4", "ISRC1DEC4"),
ARIZONA_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"),
ARIZONA_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"),
ARIZONA_MUX_ROUTES("ISRC2INT3", "ISRC2INT3"),
ARIZONA_MUX_ROUTES("ISRC2INT4", "ISRC2INT4"),
ARIZONA_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"),
ARIZONA_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"),
ARIZONA_MUX_ROUTES("ISRC2DEC3", "ISRC2DEC3"),
ARIZONA_MUX_ROUTES("ISRC2DEC4", "ISRC2DEC4"),
ARIZONA_MUX_ROUTES("ISRC3INT1", "ISRC3INT1"),
ARIZONA_MUX_ROUTES("ISRC3INT2", "ISRC3INT2"),
ARIZONA_MUX_ROUTES("ISRC3INT3", "ISRC3INT3"),
ARIZONA_MUX_ROUTES("ISRC3INT4", "ISRC3INT4"),
ARIZONA_MUX_ROUTES("ISRC3DEC1", "ISRC3DEC1"),
ARIZONA_MUX_ROUTES("ISRC3DEC2", "ISRC3DEC2"),
ARIZONA_MUX_ROUTES("ISRC3DEC3", "ISRC3DEC3"),
ARIZONA_MUX_ROUTES("ISRC3DEC4", "ISRC3DEC4"),
{ "AEC Loopback", "HPOUT1L", "OUT1L" },
{ "AEC Loopback", "HPOUT1R", "OUT1R" },
{ "HPOUT1L", NULL, "OUT1L" },
{ "HPOUT1R", NULL, "OUT1R" },
{ "AEC Loopback", "HPOUT2L", "OUT2L" },
{ "AEC Loopback", "HPOUT2R", "OUT2R" },
{ "HPOUT2L", NULL, "OUT2L" },
{ "HPOUT2R", NULL, "OUT2R" },
{ "AEC Loopback", "HPOUT3L", "OUT3L" },
{ "AEC Loopback", "HPOUT3R", "OUT3R" },
{ "HPOUT3L", NULL, "OUT3L" },
{ "HPOUT3R", NULL, "OUT3R" },
{ "AEC Loopback", "SPKOUTL", "OUT4L" },
{ "SPKOUTLN", NULL, "OUT4L" },
{ "SPKOUTLP", NULL, "OUT4L" },
{ "AEC Loopback", "SPKOUTR", "OUT4R" },
{ "SPKOUTRN", NULL, "OUT4R" },
{ "SPKOUTRP", NULL, "OUT4R" },
{ "AEC Loopback", "SPKDAT1L", "OUT5L" },
{ "AEC Loopback", "SPKDAT1R", "OUT5R" },
{ "SPKDAT1L", NULL, "OUT5L" },
{ "SPKDAT1R", NULL, "OUT5R" },
{ "AEC Loopback", "SPKDAT2L", "OUT6L" },
{ "AEC Loopback", "SPKDAT2R", "OUT6R" },
{ "SPKDAT2L", NULL, "OUT6L" },
{ "SPKDAT2R", NULL, "OUT6R" },
WM5110_RXANC_INPUT_ROUTES("RXANCL", "RXANCL"),
WM5110_RXANC_INPUT_ROUTES("RXANCR", "RXANCR"),
WM5110_RXANC_OUTPUT_ROUTES("OUT1L", "HPOUT1L"),
WM5110_RXANC_OUTPUT_ROUTES("OUT1R", "HPOUT1R"),
WM5110_RXANC_OUTPUT_ROUTES("OUT2L", "HPOUT2L"),
WM5110_RXANC_OUTPUT_ROUTES("OUT2R", "HPOUT2R"),
WM5110_RXANC_OUTPUT_ROUTES("OUT3L", "HPOUT3L"),
WM5110_RXANC_OUTPUT_ROUTES("OUT3R", "HPOUT3R"),
WM5110_RXANC_OUTPUT_ROUTES("OUT4L", "SPKOUTL"),
WM5110_RXANC_OUTPUT_ROUTES("OUT4R", "SPKOUTR"),
WM5110_RXANC_OUTPUT_ROUTES("OUT5L", "SPKDAT1L"),
WM5110_RXANC_OUTPUT_ROUTES("OUT5R", "SPKDAT1R"),
WM5110_RXANC_OUTPUT_ROUTES("OUT6L", "SPKDAT2L"),
WM5110_RXANC_OUTPUT_ROUTES("OUT6R", "SPKDAT2R"),
{ "MICSUPP", NULL, "SYSCLK" },
{ "DRC1 Signal Activity", NULL, "SYSCLK" },
{ "DRC2 Signal Activity", NULL, "SYSCLK" },
{ "DRC1 Signal Activity", NULL, "DRC1L" },
{ "DRC1 Signal Activity", NULL, "DRC1R" },
{ "DRC2 Signal Activity", NULL, "DRC2L" },
{ "DRC2 Signal Activity", NULL, "DRC2R" },
{ "DSP Voice Trigger", NULL, "SYSCLK" },
{ "DSP Voice Trigger", NULL, "DSP3 Voice Trigger" },
{ "DSP3 Voice Trigger", "Switch", "DSP3" },
};
static int wm5110_set_fll(struct snd_soc_component *component, int fll_id,
int source, unsigned int Fref, unsigned int Fout)
{
struct wm5110_priv *wm5110 = snd_soc_component_get_drvdata(component);
switch (fll_id) {
case WM5110_FLL1:
return arizona_set_fll(&wm5110->fll[0], source, Fref, Fout);
case WM5110_FLL2:
return arizona_set_fll(&wm5110->fll[1], source, Fref, Fout);
case WM5110_FLL1_REFCLK:
return arizona_set_fll_refclk(&wm5110->fll[0], source, Fref,
Fout);
case WM5110_FLL2_REFCLK:
return arizona_set_fll_refclk(&wm5110->fll[1], source, Fref,
Fout);
default:
return -EINVAL;
}
}
#define WM5110_RATES SNDRV_PCM_RATE_KNOT
#define WM5110_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops wm5110_dai_ops = {
.compress_new = snd_soc_new_compress,
};
static struct snd_soc_dai_driver wm5110_dai[] = {
{
.name = "wm5110-aif1",
.id = 1,
.base = ARIZONA_AIF1_BCLK_CTRL,
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 8,
.rates = WM5110_RATES,
.formats = WM5110_FORMATS,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 1,
.channels_max = 8,
.rates = WM5110_RATES,
.formats = WM5110_FORMATS,
},
.ops = &arizona_dai_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
{
.name = "wm5110-aif2",
.id = 2,
.base = ARIZONA_AIF2_BCLK_CTRL,
.playback = {
.stream_name = "AIF2 Playback",
.channels_min = 1,
.channels_max = 6,
.rates = WM5110_RATES,
.formats = WM5110_FORMATS,
},
.capture = {
.stream_name = "AIF2 Capture",
.channels_min = 1,
.channels_max = 6,
.rates = WM5110_RATES,
.formats = WM5110_FORMATS,
},
.ops = &arizona_dai_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
{
.name = "wm5110-aif3",
.id = 3,
.base = ARIZONA_AIF3_BCLK_CTRL,
.playback = {
.stream_name = "AIF3 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM5110_RATES,
.formats = WM5110_FORMATS,
},
.capture = {
.stream_name = "AIF3 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM5110_RATES,
.formats = WM5110_FORMATS,
},
.ops = &arizona_dai_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
{
.name = "wm5110-slim1",
.id = 4,
.playback = {
.stream_name = "Slim1 Playback",
.channels_min = 1,
.channels_max = 4,
.rates = WM5110_RATES,
.formats = WM5110_FORMATS,
},
.capture = {
.stream_name = "Slim1 Capture",
.channels_min = 1,
.channels_max = 4,
.rates = WM5110_RATES,
.formats = WM5110_FORMATS,
},
.ops = &arizona_simple_dai_ops,
},
{
.name = "wm5110-slim2",
.id = 5,
.playback = {
.stream_name = "Slim2 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM5110_RATES,
.formats = WM5110_FORMATS,
},
.capture = {
.stream_name = "Slim2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM5110_RATES,
.formats = WM5110_FORMATS,
},
.ops = &arizona_simple_dai_ops,
},
{
.name = "wm5110-slim3",
.id = 6,
.playback = {
.stream_name = "Slim3 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM5110_RATES,
.formats = WM5110_FORMATS,
},
.capture = {
.stream_name = "Slim3 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM5110_RATES,
.formats = WM5110_FORMATS,
},
.ops = &arizona_simple_dai_ops,
},
{
.name = "wm5110-cpu-voicectrl",
.capture = {
.stream_name = "Voice Control CPU",
.channels_min = 1,
.channels_max = 1,
.rates = WM5110_RATES,
.formats = WM5110_FORMATS,
},
.ops = &wm5110_dai_ops,
},
{
.name = "wm5110-dsp-voicectrl",
.capture = {
.stream_name = "Voice Control DSP",
.channels_min = 1,
.channels_max = 1,
.rates = WM5110_RATES,
.formats = WM5110_FORMATS,
},
},
{
.name = "wm5110-cpu-trace",
.capture = {
.stream_name = "Audio Trace CPU",
.channels_min = 1,
.channels_max = 6,
.rates = WM5110_RATES,
.formats = WM5110_FORMATS,
},
.ops = &wm5110_dai_ops,
},
{
.name = "wm5110-dsp-trace",
.capture = {
.stream_name = "Audio Trace DSP",
.channels_min = 1,
.channels_max = 6,
.rates = WM5110_RATES,
.formats = WM5110_FORMATS,
},
},
};
static int wm5110_open(struct snd_soc_component *component,
struct snd_compr_stream *stream)
{
struct snd_soc_pcm_runtime *rtd = stream->private_data;
struct wm5110_priv *priv = snd_soc_component_get_drvdata(component);
struct arizona *arizona = priv->core.arizona;
int n_adsp;
if (strcmp(asoc_rtd_to_codec(rtd, 0)->name, "wm5110-dsp-voicectrl") == 0) {
n_adsp = 2;
} else if (strcmp(asoc_rtd_to_codec(rtd, 0)->name, "wm5110-dsp-trace") == 0) {
n_adsp = 0;
} else {
dev_err(arizona->dev,
"No suitable compressed stream for DAI '%s'\n",
asoc_rtd_to_codec(rtd, 0)->name);
return -EINVAL;
}
return wm_adsp_compr_open(&priv->core.adsp[n_adsp], stream);
}
static irqreturn_t wm5110_adsp2_irq(int irq, void *data)
{
struct wm5110_priv *priv = data;
struct arizona *arizona = priv->core.arizona;
struct arizona_voice_trigger_info info;
int serviced = 0;
int i, ret;
for (i = 0; i < WM5110_NUM_ADSP; ++i) {
ret = wm_adsp_compr_handle_irq(&priv->core.adsp[i]);
if (ret != -ENODEV)
serviced++;
if (ret == WM_ADSP_COMPR_VOICE_TRIGGER) {
info.core = i;
arizona_call_notifiers(arizona,
ARIZONA_NOTIFY_VOICE_TRIGGER,
&info);
}
}
if (!serviced) {
dev_err(arizona->dev, "Spurious compressed data IRQ\n");
return IRQ_NONE;
}
return IRQ_HANDLED;
}
static int wm5110_component_probe(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct wm5110_priv *priv = snd_soc_component_get_drvdata(component);
struct arizona *arizona = priv->core.arizona;
int i, ret;
arizona->dapm = dapm;
snd_soc_component_init_regmap(component, arizona->regmap);
ret = arizona_init_spk(component);
if (ret < 0)
return ret;
arizona_init_gpio(component);
arizona_init_mono(component);
for (i = 0; i < WM5110_NUM_ADSP; ++i) {
ret = wm_adsp2_component_probe(&priv->core.adsp[i], component);
if (ret)
goto err_adsp2_codec_probe;
}
ret = snd_soc_add_component_controls(component,
arizona_adsp2_rate_controls,
WM5110_NUM_ADSP);
if (ret)
goto err_adsp2_codec_probe;
snd_soc_component_disable_pin(component, "HAPTICS");
return 0;
err_adsp2_codec_probe:
for (--i; i >= 0; --i)
wm_adsp2_component_remove(&priv->core.adsp[i], component);
return ret;
}
static void wm5110_component_remove(struct snd_soc_component *component)
{
struct wm5110_priv *priv = snd_soc_component_get_drvdata(component);
int i;
for (i = 0; i < WM5110_NUM_ADSP; ++i)
wm_adsp2_component_remove(&priv->core.adsp[i], component);
priv->core.arizona->dapm = NULL;
}
#define WM5110_DIG_VU 0x0200
static unsigned int wm5110_digital_vu[] = {
ARIZONA_DAC_DIGITAL_VOLUME_1L,
ARIZONA_DAC_DIGITAL_VOLUME_1R,
ARIZONA_DAC_DIGITAL_VOLUME_2L,
ARIZONA_DAC_DIGITAL_VOLUME_2R,
ARIZONA_DAC_DIGITAL_VOLUME_3L,
ARIZONA_DAC_DIGITAL_VOLUME_3R,
ARIZONA_DAC_DIGITAL_VOLUME_4L,
ARIZONA_DAC_DIGITAL_VOLUME_4R,
ARIZONA_DAC_DIGITAL_VOLUME_5L,
ARIZONA_DAC_DIGITAL_VOLUME_5R,
ARIZONA_DAC_DIGITAL_VOLUME_6L,
ARIZONA_DAC_DIGITAL_VOLUME_6R,
};
static const struct snd_compress_ops wm5110_compress_ops = {
.open = wm5110_open,
.free = wm_adsp_compr_free,
.set_params = wm_adsp_compr_set_params,
.get_caps = wm_adsp_compr_get_caps,
.trigger = wm_adsp_compr_trigger,
.pointer = wm_adsp_compr_pointer,
.copy = wm_adsp_compr_copy,
};
static const struct snd_soc_component_driver soc_component_dev_wm5110 = {
.probe = wm5110_component_probe,
.remove = wm5110_component_remove,
.set_sysclk = arizona_set_sysclk,
.set_pll = wm5110_set_fll,
.set_jack = arizona_jack_set_jack,
.name = DRV_NAME,
.compress_ops = &wm5110_compress_ops,
.controls = wm5110_snd_controls,
.num_controls = ARRAY_SIZE(wm5110_snd_controls),
.dapm_widgets = wm5110_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm5110_dapm_widgets),
.dapm_routes = wm5110_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(wm5110_dapm_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
static int wm5110_probe(struct platform_device *pdev)
{
struct arizona *arizona = dev_get_drvdata(pdev->dev.parent);
struct wm5110_priv *wm5110;
int i, ret;
wm5110 = devm_kzalloc(&pdev->dev, sizeof(struct wm5110_priv),
GFP_KERNEL);
if (wm5110 == NULL)
return -ENOMEM;
platform_set_drvdata(pdev, wm5110);
if (IS_ENABLED(CONFIG_OF)) {
if (!dev_get_platdata(arizona->dev)) {
ret = arizona_of_get_audio_pdata(arizona);
if (ret < 0)
return ret;
}
}
wm5110->core.arizona = arizona;
wm5110->core.num_inputs = 8;
for (i = 0; i < WM5110_NUM_ADSP; i++) {
wm5110->core.adsp[i].part = "wm5110";
wm5110->core.adsp[i].cs_dsp.num = i + 1;
wm5110->core.adsp[i].cs_dsp.type = WMFW_ADSP2;
wm5110->core.adsp[i].cs_dsp.dev = arizona->dev;
wm5110->core.adsp[i].cs_dsp.regmap = arizona->regmap;
wm5110->core.adsp[i].cs_dsp.base = ARIZONA_DSP1_CONTROL_1
+ (0x100 * i);
wm5110->core.adsp[i].cs_dsp.mem = wm5110_dsp_regions[i];
wm5110->core.adsp[i].cs_dsp.num_mems
= ARRAY_SIZE(wm5110_dsp1_regions);
ret = wm_adsp2_init(&wm5110->core.adsp[i]);
if (ret != 0)
return ret;
}
/* This may return -EPROBE_DEFER, so do this early on */
ret = arizona_jack_codec_dev_probe(&wm5110->core, &pdev->dev);
if (ret)
return ret;
for (i = 0; i < ARRAY_SIZE(wm5110->fll); i++)
wm5110->fll[i].vco_mult = 3;
arizona_init_fll(arizona, 1, ARIZONA_FLL1_CONTROL_1 - 1,
ARIZONA_IRQ_FLL1_LOCK, ARIZONA_IRQ_FLL1_CLOCK_OK,
&wm5110->fll[0]);
arizona_init_fll(arizona, 2, ARIZONA_FLL2_CONTROL_1 - 1,
ARIZONA_IRQ_FLL2_LOCK, ARIZONA_IRQ_FLL2_CLOCK_OK,
&wm5110->fll[1]);
/* SR2 fixed at 8kHz, SR3 fixed at 16kHz */
regmap_update_bits(arizona->regmap, ARIZONA_SAMPLE_RATE_2,
ARIZONA_SAMPLE_RATE_2_MASK, 0x11);
regmap_update_bits(arizona->regmap, ARIZONA_SAMPLE_RATE_3,
ARIZONA_SAMPLE_RATE_3_MASK, 0x12);
for (i = 0; i < ARRAY_SIZE(wm5110_dai); i++)
arizona_init_dai(&wm5110->core, i);
/* Latch volume update bits */
for (i = 0; i < ARRAY_SIZE(wm5110_digital_vu); i++)
regmap_update_bits(arizona->regmap, wm5110_digital_vu[i],
WM5110_DIG_VU, WM5110_DIG_VU);
pm_runtime_enable(&pdev->dev);
pm_runtime_idle(&pdev->dev);
ret = arizona_request_irq(arizona, ARIZONA_IRQ_DSP_IRQ1,
"ADSP2 Compressed IRQ", wm5110_adsp2_irq,
wm5110);
if (ret != 0) {
dev_err(&pdev->dev, "Failed to request DSP IRQ: %d\n", ret);
goto err_jack_codec_dev;
}
ret = arizona_set_irq_wake(arizona, ARIZONA_IRQ_DSP_IRQ1, 1);
if (ret != 0)
dev_warn(&pdev->dev,
"Failed to set compressed IRQ as a wake source: %d\n",
ret);
arizona_init_common(arizona);
ret = arizona_init_vol_limit(arizona);
if (ret < 0)
goto err_dsp_irq;
ret = arizona_init_spk_irqs(arizona);
if (ret < 0)
goto err_dsp_irq;
ret = devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_wm5110,
wm5110_dai,
ARRAY_SIZE(wm5110_dai));
if (ret < 0) {
dev_err(&pdev->dev, "Failed to register component: %d\n", ret);
goto err_spk_irqs;
}
return ret;
err_spk_irqs:
arizona_free_spk_irqs(arizona);
err_dsp_irq:
arizona_set_irq_wake(arizona, ARIZONA_IRQ_DSP_IRQ1, 0);
arizona_free_irq(arizona, ARIZONA_IRQ_DSP_IRQ1, wm5110);
err_jack_codec_dev:
pm_runtime_disable(&pdev->dev);
arizona_jack_codec_dev_remove(&wm5110->core);
return ret;
}
static void wm5110_remove(struct platform_device *pdev)
{
struct wm5110_priv *wm5110 = platform_get_drvdata(pdev);
struct arizona *arizona = wm5110->core.arizona;
int i;
pm_runtime_disable(&pdev->dev);
for (i = 0; i < WM5110_NUM_ADSP; i++)
wm_adsp2_remove(&wm5110->core.adsp[i]);
arizona_free_spk_irqs(arizona);
arizona_set_irq_wake(arizona, ARIZONA_IRQ_DSP_IRQ1, 0);
arizona_free_irq(arizona, ARIZONA_IRQ_DSP_IRQ1, wm5110);
arizona_jack_codec_dev_remove(&wm5110->core);
}
static struct platform_driver wm5110_codec_driver = {
.driver = {
.name = "wm5110-codec",
},
.probe = wm5110_probe,
.remove_new = wm5110_remove,
};
module_platform_driver(wm5110_codec_driver);
MODULE_DESCRIPTION("ASoC WM5110 driver");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:wm5110-codec");
| linux-master | sound/soc/codecs/wm5110.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Driver for the PCM512x CODECs
*
* Author: Mark Brown <[email protected]>
* Copyright 2014 Linaro Ltd
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/spi/spi.h>
#include "pcm512x.h"
static int pcm512x_spi_probe(struct spi_device *spi)
{
struct regmap *regmap;
int ret;
regmap = devm_regmap_init_spi(spi, &pcm512x_regmap);
if (IS_ERR(regmap)) {
ret = PTR_ERR(regmap);
return ret;
}
return pcm512x_probe(&spi->dev, regmap);
}
static void pcm512x_spi_remove(struct spi_device *spi)
{
pcm512x_remove(&spi->dev);
}
static const struct spi_device_id pcm512x_spi_id[] = {
{ "pcm5121", },
{ "pcm5122", },
{ "pcm5141", },
{ "pcm5142", },
{ },
};
MODULE_DEVICE_TABLE(spi, pcm512x_spi_id);
static const struct of_device_id pcm512x_of_match[] = {
{ .compatible = "ti,pcm5121", },
{ .compatible = "ti,pcm5122", },
{ .compatible = "ti,pcm5141", },
{ .compatible = "ti,pcm5142", },
{ }
};
MODULE_DEVICE_TABLE(of, pcm512x_of_match);
static struct spi_driver pcm512x_spi_driver = {
.probe = pcm512x_spi_probe,
.remove = pcm512x_spi_remove,
.id_table = pcm512x_spi_id,
.driver = {
.name = "pcm512x",
.of_match_table = pcm512x_of_match,
.pm = &pcm512x_pm_ops,
},
};
module_spi_driver(pcm512x_spi_driver);
MODULE_DESCRIPTION("ASoC PCM512x codec driver - SPI");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/pcm512x-spi.c |
// SPDX-License-Identifier: GPL-2.0
//
// Driver for the TAS5805M Audio Amplifier
//
// Author: Andy Liu <[email protected]>
// Author: Daniel Beer <[email protected]>
//
// This is based on a driver originally written by Andy Liu at TI and
// posted here:
//
// https://e2e.ti.com/support/audio-group/audio/f/audio-forum/722027/linux-tas5825m-linux-drivers
//
// It has been simplified a little and reworked for the 5.x ALSA SoC API.
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/firmware.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/gpio/consumer.h>
#include <linux/regulator/consumer.h>
#include <linux/atomic.h>
#include <linux/workqueue.h>
#include <sound/soc.h>
#include <sound/pcm.h>
#include <sound/initval.h>
/* Datasheet-defined registers on page 0, book 0 */
#define REG_PAGE 0x00
#define REG_DEVICE_CTRL_1 0x02
#define REG_DEVICE_CTRL_2 0x03
#define REG_SIG_CH_CTRL 0x28
#define REG_SAP_CTRL_1 0x33
#define REG_FS_MON 0x37
#define REG_BCK_MON 0x38
#define REG_CLKDET_STATUS 0x39
#define REG_VOL_CTL 0x4c
#define REG_AGAIN 0x54
#define REG_ADR_PIN_CTRL 0x60
#define REG_ADR_PIN_CONFIG 0x61
#define REG_CHAN_FAULT 0x70
#define REG_GLOBAL_FAULT1 0x71
#define REG_GLOBAL_FAULT2 0x72
#define REG_FAULT 0x78
#define REG_BOOK 0x7f
/* DEVICE_CTRL_2 register values */
#define DCTRL2_MODE_DEEP_SLEEP 0x00
#define DCTRL2_MODE_SLEEP 0x01
#define DCTRL2_MODE_HIZ 0x02
#define DCTRL2_MODE_PLAY 0x03
#define DCTRL2_MUTE 0x08
#define DCTRL2_DIS_DSP 0x10
/* This sequence of register writes must always be sent, prior to the
* 5ms delay while we wait for the DSP to boot.
*/
static const uint8_t dsp_cfg_preboot[] = {
0x00, 0x00, 0x7f, 0x00, 0x03, 0x02, 0x01, 0x11,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x7f, 0x00, 0x03, 0x02,
};
static const uint32_t tas5805m_volume[] = {
0x0000001B, /* 0, -110dB */ 0x0000001E, /* 1, -109dB */
0x00000021, /* 2, -108dB */ 0x00000025, /* 3, -107dB */
0x0000002A, /* 4, -106dB */ 0x0000002F, /* 5, -105dB */
0x00000035, /* 6, -104dB */ 0x0000003B, /* 7, -103dB */
0x00000043, /* 8, -102dB */ 0x0000004B, /* 9, -101dB */
0x00000054, /* 10, -100dB */ 0x0000005E, /* 11, -99dB */
0x0000006A, /* 12, -98dB */ 0x00000076, /* 13, -97dB */
0x00000085, /* 14, -96dB */ 0x00000095, /* 15, -95dB */
0x000000A7, /* 16, -94dB */ 0x000000BC, /* 17, -93dB */
0x000000D3, /* 18, -92dB */ 0x000000EC, /* 19, -91dB */
0x00000109, /* 20, -90dB */ 0x0000012A, /* 21, -89dB */
0x0000014E, /* 22, -88dB */ 0x00000177, /* 23, -87dB */
0x000001A4, /* 24, -86dB */ 0x000001D8, /* 25, -85dB */
0x00000211, /* 26, -84dB */ 0x00000252, /* 27, -83dB */
0x0000029A, /* 28, -82dB */ 0x000002EC, /* 29, -81dB */
0x00000347, /* 30, -80dB */ 0x000003AD, /* 31, -79dB */
0x00000420, /* 32, -78dB */ 0x000004A1, /* 33, -77dB */
0x00000532, /* 34, -76dB */ 0x000005D4, /* 35, -75dB */
0x0000068A, /* 36, -74dB */ 0x00000756, /* 37, -73dB */
0x0000083B, /* 38, -72dB */ 0x0000093C, /* 39, -71dB */
0x00000A5D, /* 40, -70dB */ 0x00000BA0, /* 41, -69dB */
0x00000D0C, /* 42, -68dB */ 0x00000EA3, /* 43, -67dB */
0x0000106C, /* 44, -66dB */ 0x0000126D, /* 45, -65dB */
0x000014AD, /* 46, -64dB */ 0x00001733, /* 47, -63dB */
0x00001A07, /* 48, -62dB */ 0x00001D34, /* 49, -61dB */
0x000020C5, /* 50, -60dB */ 0x000024C4, /* 51, -59dB */
0x00002941, /* 52, -58dB */ 0x00002E49, /* 53, -57dB */
0x000033EF, /* 54, -56dB */ 0x00003A45, /* 55, -55dB */
0x00004161, /* 56, -54dB */ 0x0000495C, /* 57, -53dB */
0x0000524F, /* 58, -52dB */ 0x00005C5A, /* 59, -51dB */
0x0000679F, /* 60, -50dB */ 0x00007444, /* 61, -49dB */
0x00008274, /* 62, -48dB */ 0x0000925F, /* 63, -47dB */
0x0000A43B, /* 64, -46dB */ 0x0000B845, /* 65, -45dB */
0x0000CEC1, /* 66, -44dB */ 0x0000E7FB, /* 67, -43dB */
0x00010449, /* 68, -42dB */ 0x0001240C, /* 69, -41dB */
0x000147AE, /* 70, -40dB */ 0x00016FAA, /* 71, -39dB */
0x00019C86, /* 72, -38dB */ 0x0001CEDC, /* 73, -37dB */
0x00020756, /* 74, -36dB */ 0x000246B5, /* 75, -35dB */
0x00028DCF, /* 76, -34dB */ 0x0002DD96, /* 77, -33dB */
0x00033718, /* 78, -32dB */ 0x00039B87, /* 79, -31dB */
0x00040C37, /* 80, -30dB */ 0x00048AA7, /* 81, -29dB */
0x00051884, /* 82, -28dB */ 0x0005B7B1, /* 83, -27dB */
0x00066A4A, /* 84, -26dB */ 0x000732AE, /* 85, -25dB */
0x00081385, /* 86, -24dB */ 0x00090FCC, /* 87, -23dB */
0x000A2ADB, /* 88, -22dB */ 0x000B6873, /* 89, -21dB */
0x000CCCCD, /* 90, -20dB */ 0x000E5CA1, /* 91, -19dB */
0x00101D3F, /* 92, -18dB */ 0x0012149A, /* 93, -17dB */
0x00144961, /* 94, -16dB */ 0x0016C311, /* 95, -15dB */
0x00198A13, /* 96, -14dB */ 0x001CA7D7, /* 97, -13dB */
0x002026F3, /* 98, -12dB */ 0x00241347, /* 99, -11dB */
0x00287A27, /* 100, -10dB */ 0x002D6A86, /* 101, -9dB */
0x0032F52D, /* 102, -8dB */ 0x00392CEE, /* 103, -7dB */
0x004026E7, /* 104, -6dB */ 0x0047FACD, /* 105, -5dB */
0x0050C336, /* 106, -4dB */ 0x005A9DF8, /* 107, -3dB */
0x0065AC8C, /* 108, -2dB */ 0x00721483, /* 109, -1dB */
0x00800000, /* 110, 0dB */ 0x008F9E4D, /* 111, 1dB */
0x00A12478, /* 112, 2dB */ 0x00B4CE08, /* 113, 3dB */
0x00CADDC8, /* 114, 4dB */ 0x00E39EA9, /* 115, 5dB */
0x00FF64C1, /* 116, 6dB */ 0x011E8E6A, /* 117, 7dB */
0x0141857F, /* 118, 8dB */ 0x0168C0C6, /* 119, 9dB */
0x0194C584, /* 120, 10dB */ 0x01C62940, /* 121, 11dB */
0x01FD93C2, /* 122, 12dB */ 0x023BC148, /* 123, 13dB */
0x02818508, /* 124, 14dB */ 0x02CFCC01, /* 125, 15dB */
0x0327A01A, /* 126, 16dB */ 0x038A2BAD, /* 127, 17dB */
0x03F8BD7A, /* 128, 18dB */ 0x0474CD1B, /* 129, 19dB */
0x05000000, /* 130, 20dB */ 0x059C2F02, /* 131, 21dB */
0x064B6CAE, /* 132, 22dB */ 0x07100C4D, /* 133, 23dB */
0x07ECA9CD, /* 134, 24dB */ 0x08E43299, /* 135, 25dB */
0x09F9EF8E, /* 136, 26dB */ 0x0B319025, /* 137, 27dB */
0x0C8F36F2, /* 138, 28dB */ 0x0E1787B8, /* 139, 29dB */
0x0FCFB725, /* 140, 30dB */ 0x11BD9C84, /* 141, 31dB */
0x13E7C594, /* 142, 32dB */ 0x16558CCB, /* 143, 33dB */
0x190F3254, /* 144, 34dB */ 0x1C1DF80E, /* 145, 35dB */
0x1F8C4107, /* 146, 36dB */ 0x2365B4BF, /* 147, 37dB */
0x27B766C2, /* 148, 38dB */ 0x2C900313, /* 149, 39dB */
0x32000000, /* 150, 40dB */ 0x3819D612, /* 151, 41dB */
0x3EF23ECA, /* 152, 42dB */ 0x46A07B07, /* 153, 43dB */
0x4F3EA203, /* 154, 44dB */ 0x58E9F9F9, /* 155, 45dB */
0x63C35B8E, /* 156, 46dB */ 0x6FEFA16D, /* 157, 47dB */
0x7D982575, /* 158, 48dB */
};
#define TAS5805M_VOLUME_MAX ((int)ARRAY_SIZE(tas5805m_volume) - 1)
#define TAS5805M_VOLUME_MIN 0
struct tas5805m_priv {
struct i2c_client *i2c;
struct regulator *pvdd;
struct gpio_desc *gpio_pdn_n;
uint8_t *dsp_cfg_data;
int dsp_cfg_len;
struct regmap *regmap;
int vol[2];
bool is_powered;
bool is_muted;
struct work_struct work;
struct mutex lock;
};
static void set_dsp_scale(struct regmap *rm, int offset, int vol)
{
uint8_t v[4];
uint32_t x = tas5805m_volume[vol];
int i;
for (i = 0; i < 4; i++) {
v[3 - i] = x;
x >>= 8;
}
regmap_bulk_write(rm, offset, v, ARRAY_SIZE(v));
}
static void tas5805m_refresh(struct tas5805m_priv *tas5805m)
{
struct regmap *rm = tas5805m->regmap;
dev_dbg(&tas5805m->i2c->dev, "refresh: is_muted=%d, vol=%d/%d\n",
tas5805m->is_muted, tas5805m->vol[0], tas5805m->vol[1]);
regmap_write(rm, REG_PAGE, 0x00);
regmap_write(rm, REG_BOOK, 0x8c);
regmap_write(rm, REG_PAGE, 0x2a);
/* Refresh volume. The actual volume control documented in the
* datasheet doesn't seem to work correctly. This is a pair of
* DSP registers which are *not* documented in the datasheet.
*/
set_dsp_scale(rm, 0x24, tas5805m->vol[0]);
set_dsp_scale(rm, 0x28, tas5805m->vol[1]);
regmap_write(rm, REG_PAGE, 0x00);
regmap_write(rm, REG_BOOK, 0x00);
/* Set/clear digital soft-mute */
regmap_write(rm, REG_DEVICE_CTRL_2,
(tas5805m->is_muted ? DCTRL2_MUTE : 0) |
DCTRL2_MODE_PLAY);
}
static int tas5805m_vol_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = 2;
uinfo->value.integer.min = TAS5805M_VOLUME_MIN;
uinfo->value.integer.max = TAS5805M_VOLUME_MAX;
return 0;
}
static int tas5805m_vol_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct tas5805m_priv *tas5805m =
snd_soc_component_get_drvdata(component);
mutex_lock(&tas5805m->lock);
ucontrol->value.integer.value[0] = tas5805m->vol[0];
ucontrol->value.integer.value[1] = tas5805m->vol[1];
mutex_unlock(&tas5805m->lock);
return 0;
}
static inline int volume_is_valid(int v)
{
return (v >= TAS5805M_VOLUME_MIN) && (v <= TAS5805M_VOLUME_MAX);
}
static int tas5805m_vol_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct tas5805m_priv *tas5805m =
snd_soc_component_get_drvdata(component);
int ret = 0;
if (!(volume_is_valid(ucontrol->value.integer.value[0]) &&
volume_is_valid(ucontrol->value.integer.value[1])))
return -EINVAL;
mutex_lock(&tas5805m->lock);
if (tas5805m->vol[0] != ucontrol->value.integer.value[0] ||
tas5805m->vol[1] != ucontrol->value.integer.value[1]) {
tas5805m->vol[0] = ucontrol->value.integer.value[0];
tas5805m->vol[1] = ucontrol->value.integer.value[1];
dev_dbg(component->dev, "set vol=%d/%d (is_powered=%d)\n",
tas5805m->vol[0], tas5805m->vol[1],
tas5805m->is_powered);
if (tas5805m->is_powered)
tas5805m_refresh(tas5805m);
ret = 1;
}
mutex_unlock(&tas5805m->lock);
return ret;
}
static const struct snd_kcontrol_new tas5805m_snd_controls[] = {
{
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "Master Playback Volume",
.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
SNDRV_CTL_ELEM_ACCESS_READWRITE,
.info = tas5805m_vol_info,
.get = tas5805m_vol_get,
.put = tas5805m_vol_put,
},
};
static void send_cfg(struct regmap *rm,
const uint8_t *s, unsigned int len)
{
unsigned int i;
for (i = 0; i + 1 < len; i += 2)
regmap_write(rm, s[i], s[i + 1]);
}
/* The TAS5805M DSP can't be configured until the I2S clock has been
* present and stable for 5ms, or else it won't boot and we get no
* sound.
*/
static int tas5805m_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct tas5805m_priv *tas5805m =
snd_soc_component_get_drvdata(component);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
dev_dbg(component->dev, "clock start\n");
schedule_work(&tas5805m->work);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
break;
default:
return -EINVAL;
}
return 0;
}
static void do_work(struct work_struct *work)
{
struct tas5805m_priv *tas5805m =
container_of(work, struct tas5805m_priv, work);
struct regmap *rm = tas5805m->regmap;
dev_dbg(&tas5805m->i2c->dev, "DSP startup\n");
mutex_lock(&tas5805m->lock);
/* We mustn't issue any I2C transactions until the I2S
* clock is stable. Furthermore, we must allow a 5ms
* delay after the first set of register writes to
* allow the DSP to boot before configuring it.
*/
usleep_range(5000, 10000);
send_cfg(rm, dsp_cfg_preboot, ARRAY_SIZE(dsp_cfg_preboot));
usleep_range(5000, 15000);
send_cfg(rm, tas5805m->dsp_cfg_data, tas5805m->dsp_cfg_len);
tas5805m->is_powered = true;
tas5805m_refresh(tas5805m);
mutex_unlock(&tas5805m->lock);
}
static int tas5805m_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct tas5805m_priv *tas5805m =
snd_soc_component_get_drvdata(component);
struct regmap *rm = tas5805m->regmap;
if (event & SND_SOC_DAPM_PRE_PMD) {
unsigned int chan, global1, global2;
dev_dbg(component->dev, "DSP shutdown\n");
cancel_work_sync(&tas5805m->work);
mutex_lock(&tas5805m->lock);
if (tas5805m->is_powered) {
tas5805m->is_powered = false;
regmap_write(rm, REG_PAGE, 0x00);
regmap_write(rm, REG_BOOK, 0x00);
regmap_read(rm, REG_CHAN_FAULT, &chan);
regmap_read(rm, REG_GLOBAL_FAULT1, &global1);
regmap_read(rm, REG_GLOBAL_FAULT2, &global2);
dev_dbg(component->dev, "fault regs: CHAN=%02x, "
"GLOBAL1=%02x, GLOBAL2=%02x\n",
chan, global1, global2);
regmap_write(rm, REG_DEVICE_CTRL_2, DCTRL2_MODE_HIZ);
}
mutex_unlock(&tas5805m->lock);
}
return 0;
}
static const struct snd_soc_dapm_route tas5805m_audio_map[] = {
{ "DAC", NULL, "DAC IN" },
{ "OUT", NULL, "DAC" },
};
static const struct snd_soc_dapm_widget tas5805m_dapm_widgets[] = {
SND_SOC_DAPM_AIF_IN("DAC IN", "Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC_E("DAC", NULL, SND_SOC_NOPM, 0, 0,
tas5805m_dac_event, SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_OUTPUT("OUT")
};
static const struct snd_soc_component_driver soc_codec_dev_tas5805m = {
.controls = tas5805m_snd_controls,
.num_controls = ARRAY_SIZE(tas5805m_snd_controls),
.dapm_widgets = tas5805m_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(tas5805m_dapm_widgets),
.dapm_routes = tas5805m_audio_map,
.num_dapm_routes = ARRAY_SIZE(tas5805m_audio_map),
.use_pmdown_time = 1,
.endianness = 1,
};
static int tas5805m_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
struct tas5805m_priv *tas5805m =
snd_soc_component_get_drvdata(component);
mutex_lock(&tas5805m->lock);
dev_dbg(component->dev, "set mute=%d (is_powered=%d)\n",
mute, tas5805m->is_powered);
tas5805m->is_muted = mute;
if (tas5805m->is_powered)
tas5805m_refresh(tas5805m);
mutex_unlock(&tas5805m->lock);
return 0;
}
static const struct snd_soc_dai_ops tas5805m_dai_ops = {
.trigger = tas5805m_trigger,
.mute_stream = tas5805m_mute,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver tas5805m_dai = {
.name = "tas5805m-amplifier",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_48000,
.formats = SNDRV_PCM_FMTBIT_S32_LE,
},
.ops = &tas5805m_dai_ops,
};
static const struct regmap_config tas5805m_regmap = {
.reg_bits = 8,
.val_bits = 8,
/* We have quite a lot of multi-level bank switching and a
* relatively small number of register writes between bank
* switches.
*/
.cache_type = REGCACHE_NONE,
};
static int tas5805m_i2c_probe(struct i2c_client *i2c)
{
struct device *dev = &i2c->dev;
struct regmap *regmap;
struct tas5805m_priv *tas5805m;
char filename[128];
const char *config_name;
const struct firmware *fw;
int ret;
regmap = devm_regmap_init_i2c(i2c, &tas5805m_regmap);
if (IS_ERR(regmap)) {
ret = PTR_ERR(regmap);
dev_err(dev, "unable to allocate register map: %d\n", ret);
return ret;
}
tas5805m = devm_kzalloc(dev, sizeof(struct tas5805m_priv), GFP_KERNEL);
if (!tas5805m)
return -ENOMEM;
tas5805m->i2c = i2c;
tas5805m->pvdd = devm_regulator_get(dev, "pvdd");
if (IS_ERR(tas5805m->pvdd)) {
dev_err(dev, "failed to get pvdd supply: %ld\n",
PTR_ERR(tas5805m->pvdd));
return PTR_ERR(tas5805m->pvdd);
}
dev_set_drvdata(dev, tas5805m);
tas5805m->regmap = regmap;
tas5805m->gpio_pdn_n = devm_gpiod_get(dev, "pdn", GPIOD_OUT_LOW);
if (IS_ERR(tas5805m->gpio_pdn_n)) {
dev_err(dev, "error requesting PDN gpio: %ld\n",
PTR_ERR(tas5805m->gpio_pdn_n));
return PTR_ERR(tas5805m->gpio_pdn_n);
}
/* This configuration must be generated by PPC3. The file loaded
* consists of a sequence of register writes, where bytes at
* even indices are register addresses and those at odd indices
* are register values.
*
* The fixed portion of PPC3's output prior to the 5ms delay
* should be omitted.
*/
if (device_property_read_string(dev, "ti,dsp-config-name",
&config_name))
config_name = "default";
snprintf(filename, sizeof(filename), "tas5805m_dsp_%s.bin",
config_name);
ret = request_firmware(&fw, filename, dev);
if (ret)
return ret;
if ((fw->size < 2) || (fw->size & 1)) {
dev_err(dev, "firmware is invalid\n");
release_firmware(fw);
return -EINVAL;
}
tas5805m->dsp_cfg_len = fw->size;
tas5805m->dsp_cfg_data = devm_kmemdup(dev, fw->data, fw->size, GFP_KERNEL);
if (!tas5805m->dsp_cfg_data) {
release_firmware(fw);
return -ENOMEM;
}
release_firmware(fw);
/* Do the first part of the power-on here, while we can expect
* the I2S interface to be quiet. We must raise PDN# and then
* wait 5ms before any I2S clock is sent, or else the internal
* regulator apparently won't come on.
*
* Also, we must keep the device in power down for 100ms or so
* after PVDD is applied, or else the ADR pin is sampled
* incorrectly and the device comes up with an unpredictable I2C
* address.
*/
tas5805m->vol[0] = TAS5805M_VOLUME_MIN;
tas5805m->vol[1] = TAS5805M_VOLUME_MIN;
ret = regulator_enable(tas5805m->pvdd);
if (ret < 0) {
dev_err(dev, "failed to enable pvdd: %d\n", ret);
return ret;
}
usleep_range(100000, 150000);
gpiod_set_value(tas5805m->gpio_pdn_n, 1);
usleep_range(10000, 15000);
INIT_WORK(&tas5805m->work, do_work);
mutex_init(&tas5805m->lock);
/* Don't register through devm. We need to be able to unregister
* the component prior to deasserting PDN#
*/
ret = snd_soc_register_component(dev, &soc_codec_dev_tas5805m,
&tas5805m_dai, 1);
if (ret < 0) {
dev_err(dev, "unable to register codec: %d\n", ret);
gpiod_set_value(tas5805m->gpio_pdn_n, 0);
regulator_disable(tas5805m->pvdd);
return ret;
}
return 0;
}
static void tas5805m_i2c_remove(struct i2c_client *i2c)
{
struct device *dev = &i2c->dev;
struct tas5805m_priv *tas5805m = dev_get_drvdata(dev);
cancel_work_sync(&tas5805m->work);
snd_soc_unregister_component(dev);
gpiod_set_value(tas5805m->gpio_pdn_n, 0);
usleep_range(10000, 15000);
regulator_disable(tas5805m->pvdd);
}
static const struct i2c_device_id tas5805m_i2c_id[] = {
{ "tas5805m", },
{ }
};
MODULE_DEVICE_TABLE(i2c, tas5805m_i2c_id);
#if IS_ENABLED(CONFIG_OF)
static const struct of_device_id tas5805m_of_match[] = {
{ .compatible = "ti,tas5805m", },
{ }
};
MODULE_DEVICE_TABLE(of, tas5805m_of_match);
#endif
static struct i2c_driver tas5805m_i2c_driver = {
.probe = tas5805m_i2c_probe,
.remove = tas5805m_i2c_remove,
.id_table = tas5805m_i2c_id,
.driver = {
.name = "tas5805m",
.of_match_table = of_match_ptr(tas5805m_of_match),
},
};
module_i2c_driver(tas5805m_i2c_driver);
MODULE_AUTHOR("Andy Liu <[email protected]>");
MODULE_AUTHOR("Daniel Beer <[email protected]>");
MODULE_DESCRIPTION("TAS5805M Audio Amplifier Driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/tas5805m.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* rt5514-spi.c -- RT5514 SPI driver
*
* Copyright 2015 Realtek Semiconductor Corp.
* Author: Oder Chiou <[email protected]>
*/
#include <linux/module.h>
#include <linux/input.h>
#include <linux/spi/spi.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <linux/sched.h>
#include <linux/uaccess.h>
#include <linux/regulator/consumer.h>
#include <linux/pm_qos.h>
#include <linux/sysfs.h>
#include <linux/clk.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "rt5514-spi.h"
#define DRV_NAME "rt5514-spi"
static struct spi_device *rt5514_spi;
struct rt5514_dsp {
struct device *dev;
struct delayed_work copy_work;
struct mutex dma_lock;
struct snd_pcm_substream *substream;
unsigned int buf_base, buf_limit, buf_rp;
size_t buf_size, get_size, dma_offset;
};
static const struct snd_pcm_hardware rt5514_spi_pcm_hardware = {
.info = SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_INTERLEAVED,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.period_bytes_min = PAGE_SIZE,
.period_bytes_max = 0x20000 / 8,
.periods_min = 8,
.periods_max = 8,
.channels_min = 1,
.channels_max = 1,
.buffer_bytes_max = 0x20000,
};
static struct snd_soc_dai_driver rt5514_spi_dai = {
.name = "rt5514-dsp-cpu-dai",
.id = 0,
.capture = {
.stream_name = "DSP Capture",
.channels_min = 1,
.channels_max = 1,
.rates = SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
};
static void rt5514_spi_copy_work(struct work_struct *work)
{
struct rt5514_dsp *rt5514_dsp =
container_of(work, struct rt5514_dsp, copy_work.work);
struct snd_pcm_runtime *runtime;
size_t period_bytes, truncated_bytes = 0;
unsigned int cur_wp, remain_data;
u8 buf[8];
mutex_lock(&rt5514_dsp->dma_lock);
if (!rt5514_dsp->substream) {
dev_err(rt5514_dsp->dev, "No pcm substream\n");
goto done;
}
runtime = rt5514_dsp->substream->runtime;
period_bytes = snd_pcm_lib_period_bytes(rt5514_dsp->substream);
if (!period_bytes) {
schedule_delayed_work(&rt5514_dsp->copy_work, 5);
goto done;
}
if (rt5514_dsp->buf_size % period_bytes)
rt5514_dsp->buf_size = (rt5514_dsp->buf_size / period_bytes) *
period_bytes;
if (rt5514_dsp->get_size >= rt5514_dsp->buf_size) {
rt5514_spi_burst_read(RT5514_BUFFER_VOICE_WP, (u8 *)&buf,
sizeof(buf));
cur_wp = buf[0] | buf[1] << 8 | buf[2] << 16 |
buf[3] << 24;
if (cur_wp >= rt5514_dsp->buf_rp)
remain_data = (cur_wp - rt5514_dsp->buf_rp);
else
remain_data =
(rt5514_dsp->buf_limit - rt5514_dsp->buf_rp) +
(cur_wp - rt5514_dsp->buf_base);
if (remain_data < period_bytes) {
schedule_delayed_work(&rt5514_dsp->copy_work, 5);
goto done;
}
}
if (rt5514_dsp->buf_rp + period_bytes <= rt5514_dsp->buf_limit) {
rt5514_spi_burst_read(rt5514_dsp->buf_rp,
runtime->dma_area + rt5514_dsp->dma_offset,
period_bytes);
if (rt5514_dsp->buf_rp + period_bytes == rt5514_dsp->buf_limit)
rt5514_dsp->buf_rp = rt5514_dsp->buf_base;
else
rt5514_dsp->buf_rp += period_bytes;
} else {
truncated_bytes = rt5514_dsp->buf_limit - rt5514_dsp->buf_rp;
rt5514_spi_burst_read(rt5514_dsp->buf_rp,
runtime->dma_area + rt5514_dsp->dma_offset,
truncated_bytes);
rt5514_spi_burst_read(rt5514_dsp->buf_base,
runtime->dma_area + rt5514_dsp->dma_offset +
truncated_bytes, period_bytes - truncated_bytes);
rt5514_dsp->buf_rp = rt5514_dsp->buf_base + period_bytes -
truncated_bytes;
}
rt5514_dsp->get_size += period_bytes;
rt5514_dsp->dma_offset += period_bytes;
if (rt5514_dsp->dma_offset >= runtime->dma_bytes)
rt5514_dsp->dma_offset = 0;
snd_pcm_period_elapsed(rt5514_dsp->substream);
schedule_delayed_work(&rt5514_dsp->copy_work, 5);
done:
mutex_unlock(&rt5514_dsp->dma_lock);
}
static void rt5514_schedule_copy(struct rt5514_dsp *rt5514_dsp)
{
u8 buf[8];
if (!rt5514_dsp->substream)
return;
rt5514_dsp->get_size = 0;
/**
* The address area x1800XXXX is the register address, and it cannot
* support spi burst read perfectly. So we use the spi burst read
* individually to make sure the data correctly.
*/
rt5514_spi_burst_read(RT5514_BUFFER_VOICE_BASE, (u8 *)&buf,
sizeof(buf));
rt5514_dsp->buf_base = buf[0] | buf[1] << 8 | buf[2] << 16 |
buf[3] << 24;
rt5514_spi_burst_read(RT5514_BUFFER_VOICE_LIMIT, (u8 *)&buf,
sizeof(buf));
rt5514_dsp->buf_limit = buf[0] | buf[1] << 8 | buf[2] << 16 |
buf[3] << 24;
rt5514_spi_burst_read(RT5514_BUFFER_VOICE_WP, (u8 *)&buf,
sizeof(buf));
rt5514_dsp->buf_rp = buf[0] | buf[1] << 8 | buf[2] << 16 |
buf[3] << 24;
if (rt5514_dsp->buf_rp % 8)
rt5514_dsp->buf_rp = (rt5514_dsp->buf_rp / 8) * 8;
rt5514_dsp->buf_size = rt5514_dsp->buf_limit - rt5514_dsp->buf_base;
if (rt5514_dsp->buf_base && rt5514_dsp->buf_limit &&
rt5514_dsp->buf_rp && rt5514_dsp->buf_size)
schedule_delayed_work(&rt5514_dsp->copy_work, 0);
}
static irqreturn_t rt5514_spi_irq(int irq, void *data)
{
struct rt5514_dsp *rt5514_dsp = data;
rt5514_schedule_copy(rt5514_dsp);
return IRQ_HANDLED;
}
/* PCM for streaming audio from the DSP buffer */
static int rt5514_spi_pcm_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
snd_soc_set_runtime_hwparams(substream, &rt5514_spi_pcm_hardware);
return 0;
}
static int rt5514_spi_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *hw_params)
{
struct rt5514_dsp *rt5514_dsp =
snd_soc_component_get_drvdata(component);
u8 buf[8];
mutex_lock(&rt5514_dsp->dma_lock);
rt5514_dsp->substream = substream;
rt5514_dsp->dma_offset = 0;
/* Read IRQ status and schedule copy accordingly. */
rt5514_spi_burst_read(RT5514_IRQ_CTRL, (u8 *)&buf, sizeof(buf));
if (buf[0] & RT5514_IRQ_STATUS_BIT)
rt5514_schedule_copy(rt5514_dsp);
mutex_unlock(&rt5514_dsp->dma_lock);
return 0;
}
static int rt5514_spi_hw_free(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct rt5514_dsp *rt5514_dsp =
snd_soc_component_get_drvdata(component);
mutex_lock(&rt5514_dsp->dma_lock);
rt5514_dsp->substream = NULL;
mutex_unlock(&rt5514_dsp->dma_lock);
cancel_delayed_work_sync(&rt5514_dsp->copy_work);
return 0;
}
static snd_pcm_uframes_t rt5514_spi_pcm_pointer(
struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct rt5514_dsp *rt5514_dsp =
snd_soc_component_get_drvdata(component);
return bytes_to_frames(runtime, rt5514_dsp->dma_offset);
}
static int rt5514_spi_pcm_probe(struct snd_soc_component *component)
{
struct rt5514_dsp *rt5514_dsp;
int ret;
rt5514_dsp = devm_kzalloc(component->dev, sizeof(*rt5514_dsp),
GFP_KERNEL);
if (!rt5514_dsp)
return -ENOMEM;
rt5514_dsp->dev = &rt5514_spi->dev;
mutex_init(&rt5514_dsp->dma_lock);
INIT_DELAYED_WORK(&rt5514_dsp->copy_work, rt5514_spi_copy_work);
snd_soc_component_set_drvdata(component, rt5514_dsp);
if (rt5514_spi->irq) {
ret = devm_request_threaded_irq(&rt5514_spi->dev,
rt5514_spi->irq, NULL, rt5514_spi_irq,
IRQF_TRIGGER_RISING | IRQF_ONESHOT, "rt5514-spi",
rt5514_dsp);
if (ret)
dev_err(&rt5514_spi->dev,
"%s Failed to reguest IRQ: %d\n", __func__,
ret);
else
device_init_wakeup(rt5514_dsp->dev, true);
}
return 0;
}
static int rt5514_spi_pcm_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_VMALLOC,
NULL, 0, 0);
return 0;
}
static const struct snd_soc_component_driver rt5514_spi_component = {
.name = DRV_NAME,
.probe = rt5514_spi_pcm_probe,
.open = rt5514_spi_pcm_open,
.hw_params = rt5514_spi_hw_params,
.hw_free = rt5514_spi_hw_free,
.pointer = rt5514_spi_pcm_pointer,
.pcm_construct = rt5514_spi_pcm_new,
.legacy_dai_naming = 1,
};
/**
* rt5514_spi_burst_read - Read data from SPI by rt5514 address.
* @addr: Start address.
* @rxbuf: Data Buffer for reading.
* @len: Data length, it must be a multiple of 8.
*
*
* Returns true for success.
*/
int rt5514_spi_burst_read(unsigned int addr, u8 *rxbuf, size_t len)
{
u8 spi_cmd = RT5514_SPI_CMD_BURST_READ;
int status;
u8 write_buf[8];
unsigned int i, end, offset = 0;
struct spi_message message;
struct spi_transfer x[3];
while (offset < len) {
if (offset + RT5514_SPI_BUF_LEN <= len)
end = RT5514_SPI_BUF_LEN;
else
end = len % RT5514_SPI_BUF_LEN;
write_buf[0] = spi_cmd;
write_buf[1] = ((addr + offset) & 0xff000000) >> 24;
write_buf[2] = ((addr + offset) & 0x00ff0000) >> 16;
write_buf[3] = ((addr + offset) & 0x0000ff00) >> 8;
write_buf[4] = ((addr + offset) & 0x000000ff) >> 0;
spi_message_init(&message);
memset(x, 0, sizeof(x));
x[0].len = 5;
x[0].tx_buf = write_buf;
spi_message_add_tail(&x[0], &message);
x[1].len = 4;
x[1].tx_buf = write_buf;
spi_message_add_tail(&x[1], &message);
x[2].len = end;
x[2].rx_buf = rxbuf + offset;
spi_message_add_tail(&x[2], &message);
status = spi_sync(rt5514_spi, &message);
if (status)
return false;
offset += RT5514_SPI_BUF_LEN;
}
for (i = 0; i < len; i += 8) {
write_buf[0] = rxbuf[i + 0];
write_buf[1] = rxbuf[i + 1];
write_buf[2] = rxbuf[i + 2];
write_buf[3] = rxbuf[i + 3];
write_buf[4] = rxbuf[i + 4];
write_buf[5] = rxbuf[i + 5];
write_buf[6] = rxbuf[i + 6];
write_buf[7] = rxbuf[i + 7];
rxbuf[i + 0] = write_buf[7];
rxbuf[i + 1] = write_buf[6];
rxbuf[i + 2] = write_buf[5];
rxbuf[i + 3] = write_buf[4];
rxbuf[i + 4] = write_buf[3];
rxbuf[i + 5] = write_buf[2];
rxbuf[i + 6] = write_buf[1];
rxbuf[i + 7] = write_buf[0];
}
return true;
}
EXPORT_SYMBOL_GPL(rt5514_spi_burst_read);
/**
* rt5514_spi_burst_write - Write data to SPI by rt5514 address.
* @addr: Start address.
* @txbuf: Data Buffer for writng.
* @len: Data length, it must be a multiple of 8.
*
*
* Returns true for success.
*/
int rt5514_spi_burst_write(u32 addr, const u8 *txbuf, size_t len)
{
u8 spi_cmd = RT5514_SPI_CMD_BURST_WRITE;
u8 *write_buf;
unsigned int i, end, offset = 0;
write_buf = kmalloc(RT5514_SPI_BUF_LEN + 6, GFP_KERNEL);
if (write_buf == NULL)
return -ENOMEM;
while (offset < len) {
if (offset + RT5514_SPI_BUF_LEN <= len)
end = RT5514_SPI_BUF_LEN;
else
end = len % RT5514_SPI_BUF_LEN;
write_buf[0] = spi_cmd;
write_buf[1] = ((addr + offset) & 0xff000000) >> 24;
write_buf[2] = ((addr + offset) & 0x00ff0000) >> 16;
write_buf[3] = ((addr + offset) & 0x0000ff00) >> 8;
write_buf[4] = ((addr + offset) & 0x000000ff) >> 0;
for (i = 0; i < end; i += 8) {
write_buf[i + 12] = txbuf[offset + i + 0];
write_buf[i + 11] = txbuf[offset + i + 1];
write_buf[i + 10] = txbuf[offset + i + 2];
write_buf[i + 9] = txbuf[offset + i + 3];
write_buf[i + 8] = txbuf[offset + i + 4];
write_buf[i + 7] = txbuf[offset + i + 5];
write_buf[i + 6] = txbuf[offset + i + 6];
write_buf[i + 5] = txbuf[offset + i + 7];
}
write_buf[end + 5] = spi_cmd;
spi_write(rt5514_spi, write_buf, end + 6);
offset += RT5514_SPI_BUF_LEN;
}
kfree(write_buf);
return 0;
}
EXPORT_SYMBOL_GPL(rt5514_spi_burst_write);
static int rt5514_spi_probe(struct spi_device *spi)
{
int ret;
rt5514_spi = spi;
ret = devm_snd_soc_register_component(&spi->dev,
&rt5514_spi_component,
&rt5514_spi_dai, 1);
if (ret < 0) {
dev_err(&spi->dev, "Failed to register component.\n");
return ret;
}
return 0;
}
static int __maybe_unused rt5514_suspend(struct device *dev)
{
int irq = to_spi_device(dev)->irq;
if (device_may_wakeup(dev))
enable_irq_wake(irq);
return 0;
}
static int __maybe_unused rt5514_resume(struct device *dev)
{
struct rt5514_dsp *rt5514_dsp = dev_get_drvdata(dev);
int irq = to_spi_device(dev)->irq;
u8 buf[8];
if (device_may_wakeup(dev))
disable_irq_wake(irq);
if (rt5514_dsp) {
if (rt5514_dsp->substream) {
rt5514_spi_burst_read(RT5514_IRQ_CTRL, (u8 *)&buf,
sizeof(buf));
if (buf[0] & RT5514_IRQ_STATUS_BIT)
rt5514_schedule_copy(rt5514_dsp);
}
}
return 0;
}
static const struct dev_pm_ops rt5514_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(rt5514_suspend, rt5514_resume)
};
static const struct of_device_id rt5514_of_match[] = {
{ .compatible = "realtek,rt5514", },
{},
};
MODULE_DEVICE_TABLE(of, rt5514_of_match);
static struct spi_driver rt5514_spi_driver = {
.driver = {
.name = "rt5514",
.pm = &rt5514_pm_ops,
.of_match_table = of_match_ptr(rt5514_of_match),
},
.probe = rt5514_spi_probe,
};
module_spi_driver(rt5514_spi_driver);
MODULE_DESCRIPTION("RT5514 SPI driver");
MODULE_AUTHOR("Oder Chiou <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/rt5514-spi.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* PCM3168A codec spi driver
*
* Copyright (C) 2015 Imagination Technologies Ltd.
*
* Author: Damien Horsley <[email protected]>
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/spi/spi.h>
#include <sound/soc.h>
#include "pcm3168a.h"
static int pcm3168a_spi_probe(struct spi_device *spi)
{
struct regmap *regmap;
regmap = devm_regmap_init_spi(spi, &pcm3168a_regmap);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return pcm3168a_probe(&spi->dev, regmap);
}
static void pcm3168a_spi_remove(struct spi_device *spi)
{
pcm3168a_remove(&spi->dev);
}
static const struct spi_device_id pcm3168a_spi_id[] = {
{ "pcm3168a", },
{ },
};
MODULE_DEVICE_TABLE(spi, pcm3168a_spi_id);
static const struct of_device_id pcm3168a_of_match[] = {
{ .compatible = "ti,pcm3168a", },
{ }
};
MODULE_DEVICE_TABLE(of, pcm3168a_of_match);
static struct spi_driver pcm3168a_spi_driver = {
.probe = pcm3168a_spi_probe,
.remove = pcm3168a_spi_remove,
.id_table = pcm3168a_spi_id,
.driver = {
.name = "pcm3168a",
.of_match_table = pcm3168a_of_match,
.pm = &pcm3168a_pm_ops,
},
};
module_spi_driver(pcm3168a_spi_driver);
MODULE_DESCRIPTION("PCM3168A SPI codec driver");
MODULE_AUTHOR("Damien Horsley <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/pcm3168a-spi.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for the 1250-EV1 audio I/O module
*
* Copyright 2011 Wolfson Microelectronics plc
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/gpio.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/wm1250-ev1.h>
static const char *wm1250_gpio_names[WM1250_EV1_NUM_GPIOS] = {
"WM1250 CLK_ENA",
"WM1250 CLK_SEL0",
"WM1250 CLK_SEL1",
"WM1250 OSR",
"WM1250 MASTER",
};
struct wm1250_priv {
struct gpio gpios[WM1250_EV1_NUM_GPIOS];
};
static int wm1250_ev1_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct wm1250_priv *wm1250 = dev_get_drvdata(component->dev);
int ena;
if (wm1250)
ena = wm1250->gpios[WM1250_EV1_GPIO_CLK_ENA].gpio;
else
ena = -1;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
if (ena >= 0)
gpio_set_value_cansleep(ena, 1);
break;
case SND_SOC_BIAS_OFF:
if (ena >= 0)
gpio_set_value_cansleep(ena, 0);
break;
}
return 0;
}
static const struct snd_soc_dapm_widget wm1250_ev1_dapm_widgets[] = {
SND_SOC_DAPM_ADC("ADC", "wm1250-ev1 Capture", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DAC", "wm1250-ev1 Playback", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_INPUT("WM1250 Input"),
SND_SOC_DAPM_OUTPUT("WM1250 Output"),
};
static const struct snd_soc_dapm_route wm1250_ev1_dapm_routes[] = {
{ "ADC", NULL, "WM1250 Input" },
{ "WM1250 Output", NULL, "DAC" },
};
static int wm1250_ev1_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct wm1250_priv *wm1250 = snd_soc_component_get_drvdata(dai->component);
switch (params_rate(params)) {
case 8000:
gpio_set_value(wm1250->gpios[WM1250_EV1_GPIO_CLK_SEL0].gpio,
1);
gpio_set_value(wm1250->gpios[WM1250_EV1_GPIO_CLK_SEL1].gpio,
1);
break;
case 16000:
gpio_set_value(wm1250->gpios[WM1250_EV1_GPIO_CLK_SEL0].gpio,
0);
gpio_set_value(wm1250->gpios[WM1250_EV1_GPIO_CLK_SEL1].gpio,
1);
break;
case 32000:
gpio_set_value(wm1250->gpios[WM1250_EV1_GPIO_CLK_SEL0].gpio,
1);
gpio_set_value(wm1250->gpios[WM1250_EV1_GPIO_CLK_SEL1].gpio,
0);
break;
case 64000:
gpio_set_value(wm1250->gpios[WM1250_EV1_GPIO_CLK_SEL0].gpio,
0);
gpio_set_value(wm1250->gpios[WM1250_EV1_GPIO_CLK_SEL1].gpio,
0);
break;
default:
return -EINVAL;
}
return 0;
}
static const struct snd_soc_dai_ops wm1250_ev1_ops = {
.hw_params = wm1250_ev1_hw_params,
};
#define WM1250_EV1_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_64000)
static struct snd_soc_dai_driver wm1250_ev1_dai = {
.name = "wm1250-ev1",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM1250_EV1_RATES,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM1250_EV1_RATES,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.ops = &wm1250_ev1_ops,
};
static const struct snd_soc_component_driver soc_component_dev_wm1250_ev1 = {
.dapm_widgets = wm1250_ev1_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm1250_ev1_dapm_widgets),
.dapm_routes = wm1250_ev1_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(wm1250_ev1_dapm_routes),
.set_bias_level = wm1250_ev1_set_bias_level,
.use_pmdown_time = 1,
.endianness = 1,
};
static int wm1250_ev1_pdata(struct i2c_client *i2c)
{
struct wm1250_ev1_pdata *pdata = dev_get_platdata(&i2c->dev);
struct wm1250_priv *wm1250;
int i, ret;
if (!pdata)
return 0;
wm1250 = devm_kzalloc(&i2c->dev, sizeof(*wm1250), GFP_KERNEL);
if (!wm1250) {
ret = -ENOMEM;
goto err;
}
for (i = 0; i < ARRAY_SIZE(wm1250->gpios); i++) {
wm1250->gpios[i].gpio = pdata->gpios[i];
wm1250->gpios[i].label = wm1250_gpio_names[i];
wm1250->gpios[i].flags = GPIOF_OUT_INIT_LOW;
}
wm1250->gpios[WM1250_EV1_GPIO_CLK_SEL0].flags = GPIOF_OUT_INIT_HIGH;
wm1250->gpios[WM1250_EV1_GPIO_CLK_SEL1].flags = GPIOF_OUT_INIT_HIGH;
ret = gpio_request_array(wm1250->gpios, ARRAY_SIZE(wm1250->gpios));
if (ret != 0) {
dev_err(&i2c->dev, "Failed to get GPIOs: %d\n", ret);
goto err;
}
dev_set_drvdata(&i2c->dev, wm1250);
return ret;
err:
return ret;
}
static void wm1250_ev1_free(struct i2c_client *i2c)
{
struct wm1250_priv *wm1250 = dev_get_drvdata(&i2c->dev);
if (wm1250)
gpio_free_array(wm1250->gpios, ARRAY_SIZE(wm1250->gpios));
}
static int wm1250_ev1_probe(struct i2c_client *i2c)
{
int id, board, rev, ret;
dev_set_drvdata(&i2c->dev, NULL);
board = i2c_smbus_read_byte_data(i2c, 0);
if (board < 0) {
dev_err(&i2c->dev, "Failed to read ID: %d\n", board);
return board;
}
id = (board & 0xfe) >> 2;
rev = board & 0x3;
if (id != 1) {
dev_err(&i2c->dev, "Unknown board ID %d\n", id);
return -ENODEV;
}
dev_info(&i2c->dev, "revision %d\n", rev + 1);
ret = wm1250_ev1_pdata(i2c);
if (ret != 0)
return ret;
ret = devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_wm1250_ev1,
&wm1250_ev1_dai, 1);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
wm1250_ev1_free(i2c);
return ret;
}
return 0;
}
static void wm1250_ev1_remove(struct i2c_client *i2c)
{
wm1250_ev1_free(i2c);
}
static const struct i2c_device_id wm1250_ev1_i2c_id[] = {
{ "wm1250-ev1", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm1250_ev1_i2c_id);
static struct i2c_driver wm1250_ev1_i2c_driver = {
.driver = {
.name = "wm1250-ev1",
},
.probe = wm1250_ev1_probe,
.remove = wm1250_ev1_remove,
.id_table = wm1250_ev1_i2c_id,
};
module_i2c_driver(wm1250_ev1_i2c_driver);
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_DESCRIPTION("WM1250-EV1 audio I/O module driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm1250-ev1.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2022, Analog Devices Inc.
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <sound/pcm_params.h>
#include <linux/regulator/consumer.h>
#include <sound/soc.h>
#include <linux/gpio.h>
#include <sound/tlv.h>
#include "max98396.h"
static const char * const max98396_core_supplies[MAX98396_NUM_CORE_SUPPLIES] = {
"avdd",
"dvdd",
"dvddio",
};
static struct reg_default max98396_reg[] = {
{MAX98396_R2000_SW_RESET, 0x00},
{MAX98396_R2001_INT_RAW1, 0x00},
{MAX98396_R2002_INT_RAW2, 0x00},
{MAX98396_R2003_INT_RAW3, 0x00},
{MAX98396_R2004_INT_RAW4, 0x00},
{MAX98396_R2006_INT_STATE1, 0x00},
{MAX98396_R2007_INT_STATE2, 0x00},
{MAX98396_R2008_INT_STATE3, 0x00},
{MAX98396_R2009_INT_STATE4, 0x00},
{MAX98396_R200B_INT_FLAG1, 0x00},
{MAX98396_R200C_INT_FLAG2, 0x00},
{MAX98396_R200D_INT_FLAG3, 0x00},
{MAX98396_R200E_INT_FLAG4, 0x00},
{MAX98396_R2010_INT_EN1, 0x02},
{MAX98396_R2011_INT_EN2, 0x00},
{MAX98396_R2012_INT_EN3, 0x00},
{MAX98396_R2013_INT_EN4, 0x00},
{MAX98396_R2015_INT_FLAG_CLR1, 0x00},
{MAX98396_R2016_INT_FLAG_CLR2, 0x00},
{MAX98396_R2017_INT_FLAG_CLR3, 0x00},
{MAX98396_R2018_INT_FLAG_CLR4, 0x00},
{MAX98396_R201F_IRQ_CTRL, 0x00},
{MAX98396_R2020_THERM_WARN_THRESH, 0x46},
{MAX98396_R2021_THERM_WARN_THRESH2, 0x46},
{MAX98396_R2022_THERM_SHDN_THRESH, 0x64},
{MAX98396_R2023_THERM_HYSTERESIS, 0x02},
{MAX98396_R2024_THERM_FOLDBACK_SET, 0xC5},
{MAX98396_R2027_THERM_FOLDBACK_EN, 0x01},
{MAX98396_R2030_NOISEGATE_MODE_CTRL, 0x32},
{MAX98396_R2033_NOISEGATE_MODE_EN, 0x00},
{MAX98396_R2038_CLK_MON_CTRL, 0x00},
{MAX98396_R2039_DATA_MON_CTRL, 0x00},
{MAX98396_R203F_ENABLE_CTRLS, 0x0F},
{MAX98396_R2040_PIN_CFG, 0x55},
{MAX98396_R2041_PCM_MODE_CFG, 0xC0},
{MAX98396_R2042_PCM_CLK_SETUP, 0x04},
{MAX98396_R2043_PCM_SR_SETUP, 0x88},
{MAX98396_R2044_PCM_TX_CTRL_1, 0x00},
{MAX98396_R2045_PCM_TX_CTRL_2, 0x00},
{MAX98396_R2046_PCM_TX_CTRL_3, 0x00},
{MAX98396_R2047_PCM_TX_CTRL_4, 0x00},
{MAX98396_R2048_PCM_TX_CTRL_5, 0x00},
{MAX98396_R2049_PCM_TX_CTRL_6, 0x00},
{MAX98396_R204A_PCM_TX_CTRL_7, 0x00},
{MAX98396_R204B_PCM_TX_CTRL_8, 0x00},
{MAX98396_R204C_PCM_TX_HIZ_CTRL_1, 0xFF},
{MAX98396_R204D_PCM_TX_HIZ_CTRL_2, 0xFF},
{MAX98396_R204E_PCM_TX_HIZ_CTRL_3, 0xFF},
{MAX98396_R204F_PCM_TX_HIZ_CTRL_4, 0xFF},
{MAX98396_R2050_PCM_TX_HIZ_CTRL_5, 0xFF},
{MAX98396_R2051_PCM_TX_HIZ_CTRL_6, 0xFF},
{MAX98396_R2052_PCM_TX_HIZ_CTRL_7, 0xFF},
{MAX98396_R2053_PCM_TX_HIZ_CTRL_8, 0xFF},
{MAX98396_R2055_PCM_RX_SRC1, 0x00},
{MAX98396_R2056_PCM_RX_SRC2, 0x00},
{MAX98396_R2058_PCM_BYPASS_SRC, 0x00},
{MAX98396_R205D_PCM_TX_SRC_EN, 0x00},
{MAX98396_R205E_PCM_RX_EN, 0x00},
{MAX98396_R205F_PCM_TX_EN, 0x00},
{MAX98396_R2070_ICC_RX_EN_A, 0x00},
{MAX98396_R2071_ICC_RX_EN_B, 0x00},
{MAX98396_R2072_ICC_TX_CTRL, 0x00},
{MAX98396_R207F_ICC_EN, 0x00},
{MAX98396_R2083_TONE_GEN_DC_CFG, 0x04},
{MAX98396_R2084_TONE_GEN_DC_LVL1, 0x00},
{MAX98396_R2085_TONE_GEN_DC_LVL2, 0x00},
{MAX98396_R2086_TONE_GEN_DC_LVL3, 0x00},
{MAX98396_R208F_TONE_GEN_EN, 0x00},
{MAX98396_R2090_AMP_VOL_CTRL, 0x00},
{MAX98396_R2091_AMP_PATH_GAIN, 0x0B},
{MAX98396_R2092_AMP_DSP_CFG, 0x23},
{MAX98396_R2093_SSM_CFG, 0x0D},
{MAX98396_R2094_SPK_CLS_DG_THRESH, 0x12},
{MAX98396_R2095_SPK_CLS_DG_HDR, 0x17},
{MAX98396_R2096_SPK_CLS_DG_HOLD_TIME, 0x17},
{MAX98396_R2097_SPK_CLS_DG_DELAY, 0x00},
{MAX98396_R2098_SPK_CLS_DG_MODE, 0x00},
{MAX98396_R2099_SPK_CLS_DG_VBAT_LVL, 0x03},
{MAX98396_R209A_SPK_EDGE_CTRL, 0x00},
{MAX98396_R209C_SPK_EDGE_CTRL1, 0x0A},
{MAX98396_R209D_SPK_EDGE_CTRL2, 0xAA},
{MAX98396_R209E_AMP_CLIP_GAIN, 0x00},
{MAX98396_R209F_BYPASS_PATH_CFG, 0x00},
{MAX98396_R20A0_AMP_SUPPLY_CTL, 0x00},
{MAX98396_R20AF_AMP_EN, 0x00},
{MAX98396_R20B0_ADC_SR, 0x30},
{MAX98396_R20B1_ADC_PVDD_CFG, 0x00},
{MAX98396_R20B2_ADC_VBAT_CFG, 0x00},
{MAX98396_R20B3_ADC_THERMAL_CFG, 0x00},
{MAX98396_R20B4_ADC_READBACK_CTRL1, 0x00},
{MAX98396_R20B5_ADC_READBACK_CTRL2, 0x00},
{MAX98396_R20B6_ADC_PVDD_READBACK_MSB, 0x00},
{MAX98396_R20B7_ADC_PVDD_READBACK_LSB, 0x00},
{MAX98396_R20B8_ADC_VBAT_READBACK_MSB, 0x00},
{MAX98396_R20B9_ADC_VBAT_READBACK_LSB, 0x00},
{MAX98396_R20BA_ADC_TEMP_READBACK_MSB, 0x00},
{MAX98396_R20BB_ADC_TEMP_READBACK_LSB, 0x00},
{MAX98396_R20BC_ADC_LO_PVDD_READBACK_MSB, 0x00},
{MAX98396_R20BD_ADC_LO_PVDD_READBACK_LSB, 0x00},
{MAX98396_R20BE_ADC_LO_VBAT_READBACK_MSB, 0x00},
{MAX98396_R20BF_ADC_LO_VBAT_READBACK_LSB, 0x00},
{MAX98396_R20C7_ADC_CFG, 0x00},
{MAX98396_R20D0_DHT_CFG1, 0x00},
{MAX98396_R20D1_LIMITER_CFG1, 0x08},
{MAX98396_R20D2_LIMITER_CFG2, 0x00},
{MAX98396_R20D3_DHT_CFG2, 0x14},
{MAX98396_R20D4_DHT_CFG3, 0x02},
{MAX98396_R20D5_DHT_CFG4, 0x04},
{MAX98396_R20D6_DHT_HYSTERESIS_CFG, 0x07},
{MAX98396_R20DF_DHT_EN, 0x00},
{MAX98396_R20E0_IV_SENSE_PATH_CFG, 0x04},
{MAX98396_R20E4_IV_SENSE_PATH_EN, 0x00},
{MAX98396_R20E5_BPE_STATE, 0x00},
{MAX98396_R20E6_BPE_L3_THRESH_MSB, 0x00},
{MAX98396_R20E7_BPE_L3_THRESH_LSB, 0x00},
{MAX98396_R20E8_BPE_L2_THRESH_MSB, 0x00},
{MAX98396_R20E9_BPE_L2_THRESH_LSB, 0x00},
{MAX98396_R20EA_BPE_L1_THRESH_MSB, 0x00},
{MAX98396_R20EB_BPE_L1_THRESH_LSB, 0x00},
{MAX98396_R20EC_BPE_L0_THRESH_MSB, 0x00},
{MAX98396_R20ED_BPE_L0_THRESH_LSB, 0x00},
{MAX98396_R20EE_BPE_L3_DWELL_HOLD_TIME, 0x00},
{MAX98396_R20EF_BPE_L2_DWELL_HOLD_TIME, 0x00},
{MAX98396_R20F0_BPE_L1_DWELL_HOLD_TIME, 0x00},
{MAX98396_R20F1_BPE_L0_HOLD_TIME, 0x00},
{MAX98396_R20F2_BPE_L3_ATTACK_REL_STEP, 0x00},
{MAX98396_R20F3_BPE_L2_ATTACK_REL_STEP, 0x00},
{MAX98396_R20F4_BPE_L1_ATTACK_REL_STEP, 0x00},
{MAX98396_R20F5_BPE_L0_ATTACK_REL_STEP, 0x00},
{MAX98396_R20F6_BPE_L3_MAX_GAIN_ATTN, 0x00},
{MAX98396_R20F7_BPE_L2_MAX_GAIN_ATTN, 0x00},
{MAX98396_R20F8_BPE_L1_MAX_GAIN_ATTN, 0x00},
{MAX98396_R20F9_BPE_L0_MAX_GAIN_ATTN, 0x00},
{MAX98396_R20FA_BPE_L3_ATT_REL_RATE, 0x00},
{MAX98396_R20FB_BPE_L2_ATT_REL_RATE, 0x00},
{MAX98396_R20FC_BPE_L1_ATT_REL_RATE, 0x00},
{MAX98396_R20FD_BPE_L0_ATT_REL_RATE, 0x00},
{MAX98396_R20FE_BPE_L3_LIMITER_CFG, 0x00},
{MAX98396_R20FF_BPE_L2_LIMITER_CFG, 0x00},
{MAX98396_R2100_BPE_L1_LIMITER_CFG, 0x00},
{MAX98396_R2101_BPE_L0_LIMITER_CFG, 0x00},
{MAX98396_R2102_BPE_L3_LIM_ATT_REL_RATE, 0x00},
{MAX98396_R2103_BPE_L2_LIM_ATT_REL_RATE, 0x00},
{MAX98396_R2104_BPE_L1_LIM_ATT_REL_RATE, 0x00},
{MAX98396_R2105_BPE_L0_LIM_ATT_REL_RATE, 0x00},
{MAX98396_R2106_BPE_THRESH_HYSTERESIS, 0x00},
{MAX98396_R2107_BPE_INFINITE_HOLD_CLR, 0x00},
{MAX98396_R2108_BPE_SUPPLY_SRC, 0x00},
{MAX98396_R2109_BPE_LOW_STATE, 0x00},
{MAX98396_R210A_BPE_LOW_GAIN, 0x00},
{MAX98396_R210B_BPE_LOW_LIMITER, 0x00},
{MAX98396_R210D_BPE_EN, 0x00},
{MAX98396_R210E_AUTO_RESTART, 0x00},
{MAX98396_R210F_GLOBAL_EN, 0x00},
{MAX98396_R21FF_REVISION_ID, 0x00},
};
static struct reg_default max98397_reg[] = {
{MAX98396_R2000_SW_RESET, 0x00},
{MAX98396_R2001_INT_RAW1, 0x00},
{MAX98396_R2002_INT_RAW2, 0x00},
{MAX98396_R2003_INT_RAW3, 0x00},
{MAX98396_R2004_INT_RAW4, 0x00},
{MAX98396_R2006_INT_STATE1, 0x00},
{MAX98396_R2007_INT_STATE2, 0x00},
{MAX98396_R2008_INT_STATE3, 0x00},
{MAX98396_R2009_INT_STATE4, 0x00},
{MAX98396_R200B_INT_FLAG1, 0x00},
{MAX98396_R200C_INT_FLAG2, 0x00},
{MAX98396_R200D_INT_FLAG3, 0x00},
{MAX98396_R200E_INT_FLAG4, 0x00},
{MAX98396_R2010_INT_EN1, 0x02},
{MAX98396_R2011_INT_EN2, 0x00},
{MAX98396_R2012_INT_EN3, 0x00},
{MAX98396_R2013_INT_EN4, 0x00},
{MAX98396_R2015_INT_FLAG_CLR1, 0x00},
{MAX98396_R2016_INT_FLAG_CLR2, 0x00},
{MAX98396_R2017_INT_FLAG_CLR3, 0x00},
{MAX98396_R2018_INT_FLAG_CLR4, 0x00},
{MAX98396_R201F_IRQ_CTRL, 0x00},
{MAX98396_R2020_THERM_WARN_THRESH, 0x46},
{MAX98396_R2021_THERM_WARN_THRESH2, 0x46},
{MAX98396_R2022_THERM_SHDN_THRESH, 0x64},
{MAX98396_R2023_THERM_HYSTERESIS, 0x02},
{MAX98396_R2024_THERM_FOLDBACK_SET, 0xC5},
{MAX98396_R2027_THERM_FOLDBACK_EN, 0x01},
{MAX98396_R2030_NOISEGATE_MODE_CTRL, 0x32},
{MAX98396_R2033_NOISEGATE_MODE_EN, 0x00},
{MAX98396_R2038_CLK_MON_CTRL, 0x00},
{MAX98396_R2039_DATA_MON_CTRL, 0x00},
{MAX98397_R203A_SPK_MON_THRESH, 0x03},
{MAX98396_R203F_ENABLE_CTRLS, 0x0F},
{MAX98396_R2040_PIN_CFG, 0x55},
{MAX98396_R2041_PCM_MODE_CFG, 0xC0},
{MAX98396_R2042_PCM_CLK_SETUP, 0x04},
{MAX98396_R2043_PCM_SR_SETUP, 0x88},
{MAX98396_R2044_PCM_TX_CTRL_1, 0x00},
{MAX98396_R2045_PCM_TX_CTRL_2, 0x00},
{MAX98396_R2046_PCM_TX_CTRL_3, 0x00},
{MAX98396_R2047_PCM_TX_CTRL_4, 0x00},
{MAX98396_R2048_PCM_TX_CTRL_5, 0x00},
{MAX98396_R2049_PCM_TX_CTRL_6, 0x00},
{MAX98396_R204A_PCM_TX_CTRL_7, 0x00},
{MAX98396_R204B_PCM_TX_CTRL_8, 0x00},
{MAX98397_R204C_PCM_TX_CTRL_9, 0x00},
{MAX98397_R204D_PCM_TX_HIZ_CTRL_1, 0xFF},
{MAX98397_R204E_PCM_TX_HIZ_CTRL_2, 0xFF},
{MAX98397_R204F_PCM_TX_HIZ_CTRL_3, 0xFF},
{MAX98397_R2050_PCM_TX_HIZ_CTRL_4, 0xFF},
{MAX98397_R2051_PCM_TX_HIZ_CTRL_5, 0xFF},
{MAX98397_R2052_PCM_TX_HIZ_CTRL_6, 0xFF},
{MAX98397_R2053_PCM_TX_HIZ_CTRL_7, 0xFF},
{MAX98397_R2054_PCM_TX_HIZ_CTRL_8, 0xFF},
{MAX98397_R2056_PCM_RX_SRC1, 0x00},
{MAX98397_R2057_PCM_RX_SRC2, 0x00},
{MAX98396_R2058_PCM_BYPASS_SRC, 0x00},
{MAX98396_R205D_PCM_TX_SRC_EN, 0x00},
{MAX98396_R205E_PCM_RX_EN, 0x00},
{MAX98396_R205F_PCM_TX_EN, 0x00},
{MAX98397_R2060_PCM_TX_SUPPLY_SEL, 0x00},
{MAX98396_R2070_ICC_RX_EN_A, 0x00},
{MAX98396_R2071_ICC_RX_EN_B, 0x00},
{MAX98396_R2072_ICC_TX_CTRL, 0x00},
{MAX98396_R207F_ICC_EN, 0x00},
{MAX98396_R2083_TONE_GEN_DC_CFG, 0x04},
{MAX98396_R2084_TONE_GEN_DC_LVL1, 0x00},
{MAX98396_R2085_TONE_GEN_DC_LVL2, 0x00},
{MAX98396_R2086_TONE_GEN_DC_LVL3, 0x00},
{MAX98396_R208F_TONE_GEN_EN, 0x00},
{MAX98396_R2090_AMP_VOL_CTRL, 0x00},
{MAX98396_R2091_AMP_PATH_GAIN, 0x12},
{MAX98396_R2092_AMP_DSP_CFG, 0x22},
{MAX98396_R2093_SSM_CFG, 0x08},
{MAX98396_R2094_SPK_CLS_DG_THRESH, 0x12},
{MAX98396_R2095_SPK_CLS_DG_HDR, 0x17},
{MAX98396_R2096_SPK_CLS_DG_HOLD_TIME, 0x17},
{MAX98396_R2097_SPK_CLS_DG_DELAY, 0x00},
{MAX98396_R2098_SPK_CLS_DG_MODE, 0x00},
{MAX98396_R2099_SPK_CLS_DG_VBAT_LVL, 0x03},
{MAX98396_R209A_SPK_EDGE_CTRL, 0x00},
{MAX98397_R209B_SPK_PATH_WB_ONLY, 0x00},
{MAX98396_R209C_SPK_EDGE_CTRL1, 0x03},
{MAX98396_R209D_SPK_EDGE_CTRL2, 0xFC},
{MAX98396_R209E_AMP_CLIP_GAIN, 0x00},
{MAX98396_R209F_BYPASS_PATH_CFG, 0x00},
{MAX98396_R20AF_AMP_EN, 0x00},
{MAX98396_R20B0_ADC_SR, 0x30},
{MAX98396_R20B1_ADC_PVDD_CFG, 0x00},
{MAX98396_R20B2_ADC_VBAT_CFG, 0x00},
{MAX98396_R20B3_ADC_THERMAL_CFG, 0x00},
{MAX98397_R20B4_ADC_VDDH_CFG, 0x00},
{MAX98397_R20B5_ADC_READBACK_CTRL1, 0x00},
{MAX98397_R20B6_ADC_READBACK_CTRL2, 0x00},
{MAX98397_R20B7_ADC_PVDD_READBACK_MSB, 0x00},
{MAX98397_R20B8_ADC_PVDD_READBACK_LSB, 0x00},
{MAX98397_R20B9_ADC_VBAT_READBACK_MSB, 0x00},
{MAX98397_R20BA_ADC_VBAT_READBACK_LSB, 0x00},
{MAX98397_R20BB_ADC_TEMP_READBACK_MSB, 0x00},
{MAX98397_R20BC_ADC_TEMP_READBACK_LSB, 0x00},
{MAX98397_R20BD_ADC_VDDH__READBACK_MSB, 0x00},
{MAX98397_R20BE_ADC_VDDH_READBACK_LSB, 0x00},
{MAX98396_R20BF_ADC_LO_VBAT_READBACK_LSB, 0x00},
{MAX98397_R20C3_ADC_LO_VDDH_READBACK_MSB, 0x00},
{MAX98397_R20C4_ADC_LO_VDDH_READBACK_LSB, 0x00},
{MAX98397_R20C5_MEAS_ADC_OPTIMAL_MODE, 0x04},
{MAX98396_R20C7_ADC_CFG, 0x00},
{MAX98396_R20D0_DHT_CFG1, 0x00},
{MAX98396_R20D1_LIMITER_CFG1, 0x08},
{MAX98396_R20D2_LIMITER_CFG2, 0x00},
{MAX98396_R20D3_DHT_CFG2, 0x14},
{MAX98396_R20D4_DHT_CFG3, 0x02},
{MAX98396_R20D5_DHT_CFG4, 0x04},
{MAX98396_R20D6_DHT_HYSTERESIS_CFG, 0x07},
{MAX98396_R20DF_DHT_EN, 0x00},
{MAX98396_R20E0_IV_SENSE_PATH_CFG, 0x04},
{MAX98396_R20E4_IV_SENSE_PATH_EN, 0x00},
{MAX98396_R20E5_BPE_STATE, 0x00},
{MAX98396_R20E6_BPE_L3_THRESH_MSB, 0x00},
{MAX98396_R20E7_BPE_L3_THRESH_LSB, 0x00},
{MAX98396_R20E8_BPE_L2_THRESH_MSB, 0x00},
{MAX98396_R20E9_BPE_L2_THRESH_LSB, 0x00},
{MAX98396_R20EA_BPE_L1_THRESH_MSB, 0x00},
{MAX98396_R20EB_BPE_L1_THRESH_LSB, 0x00},
{MAX98396_R20EC_BPE_L0_THRESH_MSB, 0x00},
{MAX98396_R20ED_BPE_L0_THRESH_LSB, 0x00},
{MAX98396_R20EE_BPE_L3_DWELL_HOLD_TIME, 0x00},
{MAX98396_R20EF_BPE_L2_DWELL_HOLD_TIME, 0x00},
{MAX98396_R20F0_BPE_L1_DWELL_HOLD_TIME, 0x00},
{MAX98396_R20F1_BPE_L0_HOLD_TIME, 0x00},
{MAX98396_R20F2_BPE_L3_ATTACK_REL_STEP, 0x00},
{MAX98396_R20F3_BPE_L2_ATTACK_REL_STEP, 0x00},
{MAX98396_R20F4_BPE_L1_ATTACK_REL_STEP, 0x00},
{MAX98396_R20F5_BPE_L0_ATTACK_REL_STEP, 0x00},
{MAX98396_R20F6_BPE_L3_MAX_GAIN_ATTN, 0x00},
{MAX98396_R20F7_BPE_L2_MAX_GAIN_ATTN, 0x00},
{MAX98396_R20F8_BPE_L1_MAX_GAIN_ATTN, 0x00},
{MAX98396_R20F9_BPE_L0_MAX_GAIN_ATTN, 0x00},
{MAX98396_R20FA_BPE_L3_ATT_REL_RATE, 0x00},
{MAX98396_R20FB_BPE_L2_ATT_REL_RATE, 0x00},
{MAX98396_R20FC_BPE_L1_ATT_REL_RATE, 0x00},
{MAX98396_R20FD_BPE_L0_ATT_REL_RATE, 0x00},
{MAX98396_R20FE_BPE_L3_LIMITER_CFG, 0x00},
{MAX98396_R20FF_BPE_L2_LIMITER_CFG, 0x00},
{MAX98396_R2100_BPE_L1_LIMITER_CFG, 0x00},
{MAX98396_R2101_BPE_L0_LIMITER_CFG, 0x00},
{MAX98396_R2102_BPE_L3_LIM_ATT_REL_RATE, 0x00},
{MAX98396_R2103_BPE_L2_LIM_ATT_REL_RATE, 0x00},
{MAX98396_R2104_BPE_L1_LIM_ATT_REL_RATE, 0x00},
{MAX98396_R2105_BPE_L0_LIM_ATT_REL_RATE, 0x00},
{MAX98396_R2106_BPE_THRESH_HYSTERESIS, 0x00},
{MAX98396_R2107_BPE_INFINITE_HOLD_CLR, 0x00},
{MAX98396_R2108_BPE_SUPPLY_SRC, 0x00},
{MAX98396_R2109_BPE_LOW_STATE, 0x00},
{MAX98396_R210A_BPE_LOW_GAIN, 0x00},
{MAX98396_R210B_BPE_LOW_LIMITER, 0x00},
{MAX98396_R210D_BPE_EN, 0x00},
{MAX98396_R210E_AUTO_RESTART, 0x00},
{MAX98396_R210F_GLOBAL_EN, 0x00},
{MAX98397_R22FF_REVISION_ID, 0x00},
};
static void max98396_global_enable_onoff(struct regmap *regmap, bool onoff)
{
regmap_write(regmap, MAX98396_R210F_GLOBAL_EN, onoff ? 1 : 0);
usleep_range(11000, 12000);
}
static int max98396_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct max98396_priv *max98396 = snd_soc_component_get_drvdata(component);
unsigned int format_mask, format = 0;
unsigned int bclk_pol = 0;
int ret, status;
int reg;
bool update = false;
format_mask = MAX98396_PCM_MODE_CFG_FORMAT_MASK |
MAX98396_PCM_MODE_CFG_LRCLKEDGE;
dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt);
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_NB_IF:
format = MAX98396_PCM_MODE_CFG_LRCLKEDGE;
break;
case SND_SOC_DAIFMT_IB_NF:
bclk_pol = MAX98396_PCM_MODE_CFG_BCLKEDGE;
break;
case SND_SOC_DAIFMT_IB_IF:
bclk_pol = MAX98396_PCM_MODE_CFG_BCLKEDGE;
format = MAX98396_PCM_MODE_CFG_LRCLKEDGE;
break;
default:
dev_err(component->dev, "DAI invert mode %d unsupported\n",
fmt & SND_SOC_DAIFMT_INV_MASK);
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
format |= MAX98396_PCM_FORMAT_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
format |= MAX98396_PCM_FORMAT_LJ;
break;
case SND_SOC_DAIFMT_DSP_A:
format |= MAX98396_PCM_FORMAT_TDM_MODE1;
break;
case SND_SOC_DAIFMT_DSP_B:
format |= MAX98396_PCM_FORMAT_TDM_MODE0;
break;
default:
dev_err(component->dev, "DAI format %d unsupported\n",
fmt & SND_SOC_DAIFMT_FORMAT_MASK);
return -EINVAL;
}
ret = regmap_read(max98396->regmap, MAX98396_R210F_GLOBAL_EN, &status);
if (ret < 0)
return -EINVAL;
if (status) {
ret = regmap_read(max98396->regmap, MAX98396_R2041_PCM_MODE_CFG, ®);
if (ret < 0)
return -EINVAL;
if (format != (reg & format_mask)) {
update = true;
} else {
ret = regmap_read(max98396->regmap,
MAX98396_R2042_PCM_CLK_SETUP, ®);
if (ret < 0)
return -EINVAL;
if (bclk_pol != (reg & MAX98396_PCM_MODE_CFG_BCLKEDGE))
update = true;
}
/* GLOBAL_EN OFF prior to pcm mode, clock configuration change */
if (update)
max98396_global_enable_onoff(max98396->regmap, false);
}
regmap_update_bits(max98396->regmap,
MAX98396_R2041_PCM_MODE_CFG,
format_mask, format);
regmap_update_bits(max98396->regmap,
MAX98396_R2042_PCM_CLK_SETUP,
MAX98396_PCM_MODE_CFG_BCLKEDGE,
bclk_pol);
if (status && update)
max98396_global_enable_onoff(max98396->regmap, true);
return 0;
}
#define MAX98396_BSEL_32 0x2
#define MAX98396_BSEL_48 0x3
#define MAX98396_BSEL_64 0x4
#define MAX98396_BSEL_96 0x5
#define MAX98396_BSEL_128 0x6
#define MAX98396_BSEL_192 0x7
#define MAX98396_BSEL_256 0x8
#define MAX98396_BSEL_384 0x9
#define MAX98396_BSEL_512 0xa
#define MAX98396_BSEL_320 0xb
#define MAX98396_BSEL_250 0xc
#define MAX98396_BSEL_125 0xd
/* Refer to table 5 in the datasheet */
static const struct max98396_pcm_config {
int in, out, width, bsel, max_sr;
} max98396_pcm_configs[] = {
{ .in = 2, .out = 4, .width = 16, .bsel = MAX98396_BSEL_32, .max_sr = 192000 },
{ .in = 2, .out = 6, .width = 24, .bsel = MAX98396_BSEL_48, .max_sr = 192000 },
{ .in = 2, .out = 8, .width = 32, .bsel = MAX98396_BSEL_64, .max_sr = 192000 },
{ .in = 3, .out = 15, .width = 32, .bsel = MAX98396_BSEL_125, .max_sr = 192000 },
{ .in = 4, .out = 8, .width = 16, .bsel = MAX98396_BSEL_64, .max_sr = 192000 },
{ .in = 4, .out = 12, .width = 24, .bsel = MAX98396_BSEL_96, .max_sr = 192000 },
{ .in = 4, .out = 16, .width = 32, .bsel = MAX98396_BSEL_128, .max_sr = 192000 },
{ .in = 5, .out = 15, .width = 24, .bsel = MAX98396_BSEL_125, .max_sr = 192000 },
{ .in = 7, .out = 15, .width = 16, .bsel = MAX98396_BSEL_125, .max_sr = 192000 },
{ .in = 2, .out = 4, .width = 16, .bsel = MAX98396_BSEL_32, .max_sr = 96000 },
{ .in = 2, .out = 6, .width = 24, .bsel = MAX98396_BSEL_48, .max_sr = 96000 },
{ .in = 2, .out = 8, .width = 32, .bsel = MAX98396_BSEL_64, .max_sr = 96000 },
{ .in = 3, .out = 15, .width = 32, .bsel = MAX98396_BSEL_125, .max_sr = 96000 },
{ .in = 4, .out = 8, .width = 16, .bsel = MAX98396_BSEL_64, .max_sr = 96000 },
{ .in = 4, .out = 12, .width = 24, .bsel = MAX98396_BSEL_96, .max_sr = 96000 },
{ .in = 4, .out = 16, .width = 32, .bsel = MAX98396_BSEL_128, .max_sr = 96000 },
{ .in = 5, .out = 15, .width = 24, .bsel = MAX98396_BSEL_125, .max_sr = 96000 },
{ .in = 7, .out = 15, .width = 16, .bsel = MAX98396_BSEL_125, .max_sr = 96000 },
{ .in = 7, .out = 31, .width = 32, .bsel = MAX98396_BSEL_250, .max_sr = 96000 },
{ .in = 8, .out = 16, .width = 16, .bsel = MAX98396_BSEL_128, .max_sr = 96000 },
{ .in = 8, .out = 24, .width = 24, .bsel = MAX98396_BSEL_192, .max_sr = 96000 },
{ .in = 8, .out = 32, .width = 32, .bsel = MAX98396_BSEL_256, .max_sr = 96000 },
{ .in = 10, .out = 31, .width = 24, .bsel = MAX98396_BSEL_250, .max_sr = 96000 },
{ .in = 15, .out = 31, .width = 16, .bsel = MAX98396_BSEL_250, .max_sr = 96000 },
{ .in = 16, .out = 32, .width = 16, .bsel = MAX98396_BSEL_256, .max_sr = 96000 },
{ .in = 7, .out = 31, .width = 32, .bsel = MAX98396_BSEL_250, .max_sr = 48000 },
{ .in = 10, .out = 31, .width = 24, .bsel = MAX98396_BSEL_250, .max_sr = 48000 },
{ .in = 10, .out = 40, .width = 32, .bsel = MAX98396_BSEL_320, .max_sr = 48000 },
{ .in = 15, .out = 31, .width = 16, .bsel = MAX98396_BSEL_250, .max_sr = 48000 },
{ .in = 16, .out = 48, .width = 24, .bsel = MAX98396_BSEL_384, .max_sr = 48000 },
{ .in = 16, .out = 64, .width = 32, .bsel = MAX98396_BSEL_512, .max_sr = 48000 },
};
static int max98396_pcm_config_index(int in_slots, int out_slots, int width)
{
int i;
for (i = 0; i < ARRAY_SIZE(max98396_pcm_configs); i++) {
const struct max98396_pcm_config *c = &max98396_pcm_configs[i];
if (in_slots == c->in && out_slots <= c->out && width == c->width)
return i;
}
return -1;
}
static int max98396_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct max98396_priv *max98396 = snd_soc_component_get_drvdata(component);
unsigned int sampling_rate = 0;
unsigned int chan_sz = 0;
int ret, reg, status, bsel = 0;
bool update = false;
/* pcm mode configuration */
switch (snd_pcm_format_width(params_format(params))) {
case 16:
chan_sz = MAX98396_PCM_MODE_CFG_CHANSZ_16;
break;
case 24:
chan_sz = MAX98396_PCM_MODE_CFG_CHANSZ_24;
break;
case 32:
chan_sz = MAX98396_PCM_MODE_CFG_CHANSZ_32;
break;
default:
dev_err(component->dev, "format unsupported %d\n",
params_format(params));
goto err;
}
dev_dbg(component->dev, "format supported %d",
params_format(params));
/* sampling rate configuration */
switch (params_rate(params)) {
case 8000:
sampling_rate = MAX98396_PCM_SR_8000;
break;
case 11025:
sampling_rate = MAX98396_PCM_SR_11025;
break;
case 12000:
sampling_rate = MAX98396_PCM_SR_12000;
break;
case 16000:
sampling_rate = MAX98396_PCM_SR_16000;
break;
case 22050:
sampling_rate = MAX98396_PCM_SR_22050;
break;
case 24000:
sampling_rate = MAX98396_PCM_SR_24000;
break;
case 32000:
sampling_rate = MAX98396_PCM_SR_32000;
break;
case 44100:
sampling_rate = MAX98396_PCM_SR_44100;
break;
case 48000:
sampling_rate = MAX98396_PCM_SR_48000;
break;
case 88200:
sampling_rate = MAX98396_PCM_SR_88200;
break;
case 96000:
sampling_rate = MAX98396_PCM_SR_96000;
break;
case 192000:
sampling_rate = MAX98396_PCM_SR_192000;
break;
default:
dev_err(component->dev, "rate %d not supported\n",
params_rate(params));
goto err;
}
if (max98396->tdm_mode) {
if (params_rate(params) > max98396->tdm_max_samplerate) {
dev_err(component->dev, "TDM sample rate %d too high",
params_rate(params));
goto err;
}
} else {
/* BCLK configuration */
ret = max98396_pcm_config_index(params_channels(params),
params_channels(params),
snd_pcm_format_width(params_format(params)));
if (ret < 0) {
dev_err(component->dev,
"no PCM config for %d channels, format %d\n",
params_channels(params), params_format(params));
goto err;
}
bsel = max98396_pcm_configs[ret].bsel;
if (params_rate(params) > max98396_pcm_configs[ret].max_sr) {
dev_err(component->dev, "sample rate %d too high",
params_rate(params));
goto err;
}
}
ret = regmap_read(max98396->regmap, MAX98396_R210F_GLOBAL_EN, &status);
if (ret < 0)
goto err;
if (status) {
ret = regmap_read(max98396->regmap, MAX98396_R2041_PCM_MODE_CFG, ®);
if (ret < 0)
goto err;
if (chan_sz != (reg & MAX98396_PCM_MODE_CFG_CHANSZ_MASK)) {
update = true;
} else {
ret = regmap_read(max98396->regmap, MAX98396_R2043_PCM_SR_SETUP, ®);
if (ret < 0)
goto err;
if (sampling_rate != (reg & MAX98396_PCM_SR_MASK))
update = true;
}
/* GLOBAL_EN OFF prior to channel size and sampling rate change */
if (update)
max98396_global_enable_onoff(max98396->regmap, false);
}
/* set channel size */
regmap_update_bits(max98396->regmap, MAX98396_R2041_PCM_MODE_CFG,
MAX98396_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
/* set DAI_SR to correct LRCLK frequency */
regmap_update_bits(max98396->regmap, MAX98396_R2043_PCM_SR_SETUP,
MAX98396_PCM_SR_MASK, sampling_rate);
/* set sampling rate of IV */
if (max98396->interleave_mode &&
sampling_rate > MAX98396_PCM_SR_16000)
regmap_update_bits(max98396->regmap,
MAX98396_R2043_PCM_SR_SETUP,
MAX98396_IVADC_SR_MASK,
(sampling_rate - 3)
<< MAX98396_IVADC_SR_SHIFT);
else
regmap_update_bits(max98396->regmap,
MAX98396_R2043_PCM_SR_SETUP,
MAX98396_IVADC_SR_MASK,
sampling_rate << MAX98396_IVADC_SR_SHIFT);
if (bsel)
regmap_update_bits(max98396->regmap,
MAX98396_R2042_PCM_CLK_SETUP,
MAX98396_PCM_CLK_SETUP_BSEL_MASK,
bsel);
if (status && update)
max98396_global_enable_onoff(max98396->regmap, true);
return 0;
err:
return -EINVAL;
}
static int max98396_dai_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask,
int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
struct max98396_priv *max98396 =
snd_soc_component_get_drvdata(component);
int bsel;
unsigned int chan_sz = 0;
int ret, status;
int reg;
bool update = false;
if (!tx_mask && !rx_mask && !slots && !slot_width)
max98396->tdm_mode = false;
else
max98396->tdm_mode = true;
/* BCLK configuration */
ret = max98396_pcm_config_index(slots, slots, slot_width);
if (ret < 0) {
dev_err(component->dev, "no TDM config for %d slots %d bits\n",
slots, slot_width);
return -EINVAL;
}
bsel = max98396_pcm_configs[ret].bsel;
max98396->tdm_max_samplerate = max98396_pcm_configs[ret].max_sr;
/* Channel size configuration */
switch (slot_width) {
case 16:
chan_sz = MAX98396_PCM_MODE_CFG_CHANSZ_16;
break;
case 24:
chan_sz = MAX98396_PCM_MODE_CFG_CHANSZ_24;
break;
case 32:
chan_sz = MAX98396_PCM_MODE_CFG_CHANSZ_32;
break;
default:
dev_err(component->dev, "slot width %d unsupported\n",
slot_width);
return -EINVAL;
}
ret = regmap_read(max98396->regmap, MAX98396_R210F_GLOBAL_EN, &status);
if (ret < 0)
return -EINVAL;
if (status) {
ret = regmap_read(max98396->regmap, MAX98396_R2042_PCM_CLK_SETUP, ®);
if (ret < 0)
return -EINVAL;
if (bsel != (reg & MAX98396_PCM_CLK_SETUP_BSEL_MASK)) {
update = true;
} else {
ret = regmap_read(max98396->regmap, MAX98396_R2041_PCM_MODE_CFG, ®);
if (ret < 0)
return -EINVAL;
if (chan_sz != (reg & MAX98396_PCM_MODE_CFG_CHANSZ_MASK))
update = true;
}
/* GLOBAL_EN OFF prior to channel size and BCLK per LRCLK change */
if (update)
max98396_global_enable_onoff(max98396->regmap, false);
}
regmap_update_bits(max98396->regmap,
MAX98396_R2042_PCM_CLK_SETUP,
MAX98396_PCM_CLK_SETUP_BSEL_MASK,
bsel);
regmap_update_bits(max98396->regmap,
MAX98396_R2041_PCM_MODE_CFG,
MAX98396_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
/* Rx slot configuration */
if (max98396->device_id == CODEC_TYPE_MAX98396) {
regmap_update_bits(max98396->regmap,
MAX98396_R2056_PCM_RX_SRC2,
MAX98396_PCM_DMIX_CH0_SRC_MASK,
rx_mask);
regmap_update_bits(max98396->regmap,
MAX98396_R2056_PCM_RX_SRC2,
MAX98396_PCM_DMIX_CH1_SRC_MASK,
rx_mask << MAX98396_PCM_DMIX_CH1_SHIFT);
} else {
regmap_update_bits(max98396->regmap,
MAX98397_R2057_PCM_RX_SRC2,
MAX98396_PCM_DMIX_CH0_SRC_MASK,
rx_mask);
regmap_update_bits(max98396->regmap,
MAX98397_R2057_PCM_RX_SRC2,
MAX98396_PCM_DMIX_CH1_SRC_MASK,
rx_mask << MAX98396_PCM_DMIX_CH1_SHIFT);
}
/* Tx slot Hi-Z configuration */
if (max98396->device_id == CODEC_TYPE_MAX98396) {
regmap_write(max98396->regmap,
MAX98396_R2053_PCM_TX_HIZ_CTRL_8,
~tx_mask & 0xFF);
regmap_write(max98396->regmap,
MAX98396_R2052_PCM_TX_HIZ_CTRL_7,
(~tx_mask & 0xFF00) >> 8);
} else {
regmap_write(max98396->regmap,
MAX98397_R2054_PCM_TX_HIZ_CTRL_8,
~tx_mask & 0xFF);
regmap_write(max98396->regmap,
MAX98397_R2053_PCM_TX_HIZ_CTRL_7,
(~tx_mask & 0xFF00) >> 8);
}
if (status && update)
max98396_global_enable_onoff(max98396->regmap, true);
return 0;
}
#define MAX98396_RATES SNDRV_PCM_RATE_8000_192000
#define MAX98396_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops max98396_dai_ops = {
.set_fmt = max98396_dai_set_fmt,
.hw_params = max98396_dai_hw_params,
.set_tdm_slot = max98396_dai_tdm_slot,
};
static int max98396_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct max98396_priv *max98396 =
snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
max98396_global_enable_onoff(max98396->regmap, true);
break;
case SND_SOC_DAPM_PRE_PMD:
max98396_global_enable_onoff(max98396->regmap, false);
max98396->tdm_mode = false;
break;
default:
return 0;
}
return 0;
}
static bool max98396_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX98396_R2001_INT_RAW1 ... MAX98396_R2004_INT_RAW4:
case MAX98396_R2006_INT_STATE1 ... MAX98396_R2009_INT_STATE4:
case MAX98396_R200B_INT_FLAG1 ... MAX98396_R200E_INT_FLAG4:
case MAX98396_R2010_INT_EN1 ... MAX98396_R2013_INT_EN4:
case MAX98396_R2015_INT_FLAG_CLR1 ... MAX98396_R2018_INT_FLAG_CLR4:
case MAX98396_R201F_IRQ_CTRL ... MAX98396_R2024_THERM_FOLDBACK_SET:
case MAX98396_R2027_THERM_FOLDBACK_EN:
case MAX98396_R2030_NOISEGATE_MODE_CTRL:
case MAX98396_R2033_NOISEGATE_MODE_EN:
case MAX98396_R2038_CLK_MON_CTRL ... MAX98396_R2039_DATA_MON_CTRL:
case MAX98396_R203F_ENABLE_CTRLS ... MAX98396_R2053_PCM_TX_HIZ_CTRL_8:
case MAX98396_R2055_PCM_RX_SRC1 ... MAX98396_R2056_PCM_RX_SRC2:
case MAX98396_R2058_PCM_BYPASS_SRC:
case MAX98396_R205D_PCM_TX_SRC_EN ... MAX98396_R205F_PCM_TX_EN:
case MAX98396_R2070_ICC_RX_EN_A... MAX98396_R2072_ICC_TX_CTRL:
case MAX98396_R207F_ICC_EN:
case MAX98396_R2083_TONE_GEN_DC_CFG ... MAX98396_R2086_TONE_GEN_DC_LVL3:
case MAX98396_R208F_TONE_GEN_EN ... MAX98396_R209A_SPK_EDGE_CTRL:
case MAX98396_R209C_SPK_EDGE_CTRL1 ... MAX98396_R20A0_AMP_SUPPLY_CTL:
case MAX98396_R20AF_AMP_EN ... MAX98396_R20BF_ADC_LO_VBAT_READBACK_LSB:
case MAX98396_R20C7_ADC_CFG:
case MAX98396_R20D0_DHT_CFG1 ... MAX98396_R20D6_DHT_HYSTERESIS_CFG:
case MAX98396_R20DF_DHT_EN:
case MAX98396_R20E0_IV_SENSE_PATH_CFG:
case MAX98396_R20E4_IV_SENSE_PATH_EN
... MAX98396_R2106_BPE_THRESH_HYSTERESIS:
case MAX98396_R2108_BPE_SUPPLY_SRC ... MAX98396_R210B_BPE_LOW_LIMITER:
case MAX98396_R210D_BPE_EN ... MAX98396_R210F_GLOBAL_EN:
case MAX98396_R21FF_REVISION_ID:
return true;
default:
return false;
}
};
static bool max98396_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX98396_R2000_SW_RESET:
case MAX98396_R2001_INT_RAW1 ... MAX98396_R200E_INT_FLAG4:
case MAX98396_R2041_PCM_MODE_CFG:
case MAX98396_R20B6_ADC_PVDD_READBACK_MSB
... MAX98396_R20BF_ADC_LO_VBAT_READBACK_LSB:
case MAX98396_R20E5_BPE_STATE:
case MAX98396_R2109_BPE_LOW_STATE
... MAX98396_R210B_BPE_LOW_LIMITER:
case MAX98396_R210F_GLOBAL_EN:
case MAX98396_R21FF_REVISION_ID:
return true;
default:
return false;
}
}
static bool max98397_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX98396_R2001_INT_RAW1 ... MAX98396_R2004_INT_RAW4:
case MAX98396_R2006_INT_STATE1 ... MAX98396_R2009_INT_STATE4:
case MAX98396_R200B_INT_FLAG1 ... MAX98396_R200E_INT_FLAG4:
case MAX98396_R2010_INT_EN1 ... MAX98396_R2013_INT_EN4:
case MAX98396_R2015_INT_FLAG_CLR1 ... MAX98396_R2018_INT_FLAG_CLR4:
case MAX98396_R201F_IRQ_CTRL ... MAX98396_R2024_THERM_FOLDBACK_SET:
case MAX98396_R2027_THERM_FOLDBACK_EN:
case MAX98396_R2030_NOISEGATE_MODE_CTRL:
case MAX98396_R2033_NOISEGATE_MODE_EN:
case MAX98396_R2038_CLK_MON_CTRL ... MAX98397_R203A_SPK_MON_THRESH:
case MAX98396_R203F_ENABLE_CTRLS ... MAX98397_R2054_PCM_TX_HIZ_CTRL_8:
case MAX98397_R2056_PCM_RX_SRC1... MAX98396_R2058_PCM_BYPASS_SRC:
case MAX98396_R205D_PCM_TX_SRC_EN ... MAX98397_R2060_PCM_TX_SUPPLY_SEL:
case MAX98396_R2070_ICC_RX_EN_A... MAX98396_R2072_ICC_TX_CTRL:
case MAX98396_R207F_ICC_EN:
case MAX98396_R2083_TONE_GEN_DC_CFG ... MAX98396_R2086_TONE_GEN_DC_LVL3:
case MAX98396_R208F_TONE_GEN_EN ... MAX98396_R209F_BYPASS_PATH_CFG:
case MAX98396_R20AF_AMP_EN ... MAX98397_R20C5_MEAS_ADC_OPTIMAL_MODE:
case MAX98396_R20C7_ADC_CFG:
case MAX98396_R20D0_DHT_CFG1 ... MAX98396_R20D6_DHT_HYSTERESIS_CFG:
case MAX98396_R20DF_DHT_EN:
case MAX98396_R20E0_IV_SENSE_PATH_CFG:
case MAX98396_R20E4_IV_SENSE_PATH_EN
... MAX98396_R2106_BPE_THRESH_HYSTERESIS:
case MAX98396_R2108_BPE_SUPPLY_SRC ... MAX98396_R210B_BPE_LOW_LIMITER:
case MAX98396_R210D_BPE_EN ... MAX98396_R210F_GLOBAL_EN:
case MAX98397_R22FF_REVISION_ID:
return true;
default:
return false;
}
};
static bool max98397_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX98396_R2001_INT_RAW1 ... MAX98396_R200E_INT_FLAG4:
case MAX98396_R2041_PCM_MODE_CFG:
case MAX98397_R20B7_ADC_PVDD_READBACK_MSB
... MAX98397_R20C4_ADC_LO_VDDH_READBACK_LSB:
case MAX98396_R20E5_BPE_STATE:
case MAX98396_R2109_BPE_LOW_STATE
... MAX98396_R210B_BPE_LOW_LIMITER:
case MAX98396_R210F_GLOBAL_EN:
case MAX98397_R22FF_REVISION_ID:
return true;
default:
return false;
}
}
static const char * const max98396_op_mod_text[] = {
"DG", "PVDD", "VBAT",
};
static SOC_ENUM_SINGLE_DECL(max98396_op_mod_enum,
MAX98396_R2098_SPK_CLS_DG_MODE,
0, max98396_op_mod_text);
static DECLARE_TLV_DB_SCALE(max98396_digital_tlv, -6350, 50, 1);
static const DECLARE_TLV_DB_RANGE(max98396_spk_tlv,
0, 0x11, TLV_DB_SCALE_ITEM(400, 100, 0),
);
static DECLARE_TLV_DB_RANGE(max98397_digital_tlv,
0, 0x4A, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
0x4B, 0xFF, TLV_DB_SCALE_ITEM(-9000, 50, 0),
);
static const DECLARE_TLV_DB_RANGE(max98397_spk_tlv,
0, 0x15, TLV_DB_SCALE_ITEM(600, 100, 0),
);
static int max98396_mux_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_dapm_kcontrol_component(kcontrol);
struct max98396_priv *max98396 = snd_soc_component_get_drvdata(component);
int reg, val;
if (max98396->device_id == CODEC_TYPE_MAX98396)
reg = MAX98396_R2055_PCM_RX_SRC1;
else
reg = MAX98397_R2056_PCM_RX_SRC1;
regmap_read(max98396->regmap, reg, &val);
ucontrol->value.enumerated.item[0] = val;
return 0;
}
static int max98396_mux_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_dapm_kcontrol_component(kcontrol);
struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kcontrol);
struct max98396_priv *max98396 = snd_soc_component_get_drvdata(component);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int *item = ucontrol->value.enumerated.item;
int reg, val;
int change;
if (item[0] >= e->items)
return -EINVAL;
val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
if (max98396->device_id == CODEC_TYPE_MAX98396)
reg = MAX98396_R2055_PCM_RX_SRC1;
else
reg = MAX98397_R2056_PCM_RX_SRC1;
change = snd_soc_component_test_bits(component, reg,
MAX98396_PCM_RX_MASK, val);
if (change)
regmap_update_bits(max98396->regmap, reg,
MAX98396_PCM_RX_MASK, val);
snd_soc_dapm_mux_update_power(dapm, kcontrol, item[0], e, NULL);
return change;
}
static const char * const max98396_switch_text[] = {
"Left", "Right", "LeftRight"};
static SOC_ENUM_SINGLE_DECL(dai_sel_enum, SND_SOC_NOPM, 0,
max98396_switch_text);
static const struct snd_kcontrol_new max98396_dai_mux =
SOC_DAPM_ENUM_EXT("DAI Sel Mux", dai_sel_enum,
max98396_mux_get, max98396_mux_put);
static const struct snd_kcontrol_new max98396_vi_control =
SOC_DAPM_SINGLE("Switch", MAX98396_R205F_PCM_TX_EN, 0, 1, 0);
static const struct snd_soc_dapm_widget max98396_dapm_widgets[] = {
SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback",
MAX98396_R20AF_AMP_EN, 0, 0, max98396_dac_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0,
&max98396_dai_mux),
SND_SOC_DAPM_OUTPUT("BE_OUT"),
SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0,
MAX98396_R20E4_IV_SENSE_PATH_EN, 0, 0),
SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0,
MAX98396_R20E4_IV_SENSE_PATH_EN, 1, 0),
SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0,
&max98396_vi_control),
SND_SOC_DAPM_SIGGEN("VMON"),
SND_SOC_DAPM_SIGGEN("IMON"),
SND_SOC_DAPM_SIGGEN("FBMON"),
};
static const char * const max98396_thermal_thresh_text[] = {
"50C", "51C", "52C", "53C", "54C", "55C", "56C", "57C",
"58C", "59C", "60C", "61C", "62C", "63C", "64C", "65C",
"66C", "67C", "68C", "69C", "70C", "71C", "72C", "73C",
"74C", "75C", "76C", "77C", "78C", "79C", "80C", "81C",
"82C", "83C", "84C", "85C", "86C", "87C", "88C", "89C",
"90C", "91C", "92C", "93C", "94C", "95C", "96C", "97C",
"98C", "99C", "100C", "101C", "102C", "103C", "104C", "105C",
"106C", "107C", "108C", "109C", "110C", "111C", "112C", "113C",
"114C", "115C", "116C", "117C", "118C", "119C", "120C", "121C",
"122C", "123C", "124C", "125C", "126C", "127C", "128C", "129C",
"130C", "131C", "132C", "133C", "134C", "135C", "136C", "137C",
"138C", "139C", "140C", "141C", "142C", "143C", "144C", "145C",
"146C", "147C", "148C", "149C", "150C"
};
static SOC_ENUM_SINGLE_DECL(max98396_thermal_warn_thresh1_enum,
MAX98396_R2020_THERM_WARN_THRESH, 0,
max98396_thermal_thresh_text);
static SOC_ENUM_SINGLE_DECL(max98396_thermal_warn_thresh2_enum,
MAX98396_R2021_THERM_WARN_THRESH2, 0,
max98396_thermal_thresh_text);
static SOC_ENUM_SINGLE_DECL(max98396_thermal_shdn_thresh_enum,
MAX98396_R2022_THERM_SHDN_THRESH, 0,
max98396_thermal_thresh_text);
static const char * const max98396_thermal_hyteresis_text[] = {
"2C", "5C", "7C", "10C"
};
static SOC_ENUM_SINGLE_DECL(max98396_thermal_hysteresis_enum,
MAX98396_R2023_THERM_HYSTERESIS, 0,
max98396_thermal_hyteresis_text);
static const char * const max98396_foldback_slope_text[] = {
"0.25", "0.5", "1.0", "2.0"
};
static SOC_ENUM_SINGLE_DECL(max98396_thermal_fb_slope1_enum,
MAX98396_R2024_THERM_FOLDBACK_SET,
MAX98396_THERM_FB_SLOPE1_SHIFT,
max98396_foldback_slope_text);
static SOC_ENUM_SINGLE_DECL(max98396_thermal_fb_slope2_enum,
MAX98396_R2024_THERM_FOLDBACK_SET,
MAX98396_THERM_FB_SLOPE2_SHIFT,
max98396_foldback_slope_text);
static const char * const max98396_foldback_reltime_text[] = {
"3ms", "10ms", "100ms", "300ms"
};
static SOC_ENUM_SINGLE_DECL(max98396_thermal_fb_reltime_enum,
MAX98396_R2024_THERM_FOLDBACK_SET,
MAX98396_THERM_FB_REL_SHIFT,
max98396_foldback_reltime_text);
static const char * const max98396_foldback_holdtime_text[] = {
"0ms", "20ms", "40ms", "80ms"
};
static SOC_ENUM_SINGLE_DECL(max98396_thermal_fb_holdtime_enum,
MAX98396_R2024_THERM_FOLDBACK_SET,
MAX98396_THERM_FB_HOLD_SHIFT,
max98396_foldback_holdtime_text);
static int max98396_adc_value_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct max98396_priv *max98396 = snd_soc_component_get_drvdata(component);
int ret;
u8 val[2];
int reg = mc->reg;
/* ADC value is not available if the device is powered down */
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
goto exit;
if (max98396->device_id == CODEC_TYPE_MAX98397) {
switch (mc->reg) {
case MAX98396_R20B6_ADC_PVDD_READBACK_MSB:
reg = MAX98397_R20B7_ADC_PVDD_READBACK_MSB;
break;
case MAX98396_R20B8_ADC_VBAT_READBACK_MSB:
reg = MAX98397_R20B9_ADC_VBAT_READBACK_MSB;
break;
case MAX98396_R20BA_ADC_TEMP_READBACK_MSB:
reg = MAX98397_R20BB_ADC_TEMP_READBACK_MSB;
break;
default:
goto exit;
}
}
ret = regmap_raw_read(max98396->regmap, reg, &val, 2);
if (ret)
goto exit;
/* ADC readback bits[8:0] rearrangement */
ucontrol->value.integer.value[0] = (val[0] << 1) | (val[1] & 1);
return 0;
exit:
ucontrol->value.integer.value[0] = 0;
return 0;
}
static const struct snd_kcontrol_new max98396_snd_controls[] = {
/* Volume */
SOC_SINGLE_TLV("Digital Volume", MAX98396_R2090_AMP_VOL_CTRL,
0, 0x7F, 1, max98396_digital_tlv),
SOC_SINGLE_TLV("Speaker Volume", MAX98396_R2091_AMP_PATH_GAIN,
0, 0x11, 0, max98396_spk_tlv),
/* Volume Ramp Up/Down Enable*/
SOC_SINGLE("Ramp Up Switch", MAX98396_R2092_AMP_DSP_CFG,
MAX98396_DSP_SPK_VOL_RMPUP_SHIFT, 1, 0),
SOC_SINGLE("Ramp Down Switch", MAX98396_R2092_AMP_DSP_CFG,
MAX98396_DSP_SPK_VOL_RMPDN_SHIFT, 1, 0),
/* Clock Monitor Enable */
SOC_SINGLE("CLK Monitor Switch", MAX98396_R203F_ENABLE_CTRLS,
MAX98396_CTRL_CMON_EN_SHIFT, 1, 0),
/* Dither Enable */
SOC_SINGLE("Dither Switch", MAX98396_R2092_AMP_DSP_CFG,
MAX98396_DSP_SPK_DITH_EN_SHIFT, 1, 0),
SOC_SINGLE("IV Dither Switch", MAX98396_R20E0_IV_SENSE_PATH_CFG,
MAX98396_IV_SENSE_DITH_EN_SHIFT, 1, 0),
/* DC Blocker Enable */
SOC_SINGLE("DC Blocker Switch", MAX98396_R2092_AMP_DSP_CFG,
MAX98396_DSP_SPK_DCBLK_EN_SHIFT, 1, 0),
SOC_SINGLE("IV DC Blocker Switch", MAX98396_R20E0_IV_SENSE_PATH_CFG,
MAX98396_IV_SENSE_DCBLK_EN_SHIFT, 3, 0),
/* Speaker Safe Mode Enable */
SOC_SINGLE("Safe Mode Switch", MAX98396_R2092_AMP_DSP_CFG,
MAX98396_DSP_SPK_SAFE_EN_SHIFT, 1, 0),
/* Wideband Filter Enable */
SOC_SINGLE("WB Filter Switch", MAX98396_R2092_AMP_DSP_CFG,
MAX98396_DSP_SPK_WB_FLT_EN_SHIFT, 1, 0),
SOC_SINGLE("IV WB Filter Switch", MAX98396_R20E0_IV_SENSE_PATH_CFG,
MAX98396_IV_SENSE_WB_FLT_EN_SHIFT, 1, 0),
/* Dynamic Headroom Tracking */
SOC_SINGLE("DHT Switch", MAX98396_R20DF_DHT_EN, 0, 1, 0),
/* Brownout Protection Engine */
SOC_SINGLE("BPE Switch", MAX98396_R210D_BPE_EN, 0, 1, 0),
SOC_SINGLE("BPE Limiter Switch", MAX98396_R210D_BPE_EN, 1, 1, 0),
/* Bypass Path Enable */
SOC_SINGLE("Bypass Path Switch",
MAX98396_R205E_PCM_RX_EN, 1, 1, 0),
/* Speaker Operation Mode */
SOC_ENUM("OP Mode", max98396_op_mod_enum),
/* Auto Restart functions */
SOC_SINGLE("CMON Auto Restart Switch", MAX98396_R2038_CLK_MON_CTRL,
MAX98396_CLK_MON_AUTO_RESTART_SHIFT, 1, 0),
SOC_SINGLE("PVDD Auto Restart Switch", MAX98396_R210E_AUTO_RESTART,
MAX98396_PVDD_UVLO_RESTART_SHFT, 1, 0),
SOC_SINGLE("VBAT Auto Restart Switch", MAX98396_R210E_AUTO_RESTART,
MAX98396_VBAT_UVLO_RESTART_SHFT, 1, 0),
SOC_SINGLE("THERM Auto Restart Switch", MAX98396_R210E_AUTO_RESTART,
MAX98396_THEM_SHDN_RESTART_SHFT, 1, 0),
SOC_SINGLE("OVC Auto Restart Switch", MAX98396_R210E_AUTO_RESTART,
MAX98396_OVC_RESTART_SHFT, 1, 0),
/* Thermal Threshold */
SOC_ENUM("THERM Thresh1", max98396_thermal_warn_thresh1_enum),
SOC_ENUM("THERM Thresh2", max98396_thermal_warn_thresh2_enum),
SOC_ENUM("THERM SHDN Thresh", max98396_thermal_shdn_thresh_enum),
SOC_ENUM("THERM Hysteresis", max98396_thermal_hysteresis_enum),
SOC_SINGLE("THERM Foldback Switch",
MAX98396_R2027_THERM_FOLDBACK_EN, 0, 1, 0),
SOC_ENUM("THERM Slope1", max98396_thermal_fb_slope1_enum),
SOC_ENUM("THERM Slope2", max98396_thermal_fb_slope2_enum),
SOC_ENUM("THERM Release", max98396_thermal_fb_reltime_enum),
SOC_ENUM("THERM Hold", max98396_thermal_fb_holdtime_enum),
/* ADC */
SOC_SINGLE_EXT("ADC PVDD", MAX98396_R20B6_ADC_PVDD_READBACK_MSB, 0, 0x1FF, 0,
max98396_adc_value_get, NULL),
SOC_SINGLE_EXT("ADC VBAT", MAX98396_R20B8_ADC_VBAT_READBACK_MSB, 0, 0x1FF, 0,
max98396_adc_value_get, NULL),
SOC_SINGLE_EXT("ADC TEMP", MAX98396_R20BA_ADC_TEMP_READBACK_MSB, 0, 0x1FF, 0,
max98396_adc_value_get, NULL),
};
static const struct snd_kcontrol_new max98397_snd_controls[] = {
/* Volume */
SOC_SINGLE_TLV("Digital Volume", MAX98396_R2090_AMP_VOL_CTRL,
0, 0xFF, 1, max98397_digital_tlv),
SOC_SINGLE_TLV("Speaker Volume", MAX98396_R2091_AMP_PATH_GAIN,
0, 0x15, 0, max98397_spk_tlv),
/* Volume Ramp Up/Down Enable*/
SOC_SINGLE("Ramp Up Switch", MAX98396_R2092_AMP_DSP_CFG,
MAX98396_DSP_SPK_VOL_RMPUP_SHIFT, 1, 0),
SOC_SINGLE("Ramp Down Switch", MAX98396_R2092_AMP_DSP_CFG,
MAX98396_DSP_SPK_VOL_RMPDN_SHIFT, 1, 0),
/* Clock Monitor Enable */
SOC_SINGLE("CLK Monitor Switch", MAX98396_R203F_ENABLE_CTRLS,
MAX98396_CTRL_CMON_EN_SHIFT, 1, 0),
/* Dither Enable */
SOC_SINGLE("Dither Switch", MAX98396_R2092_AMP_DSP_CFG,
MAX98396_DSP_SPK_DITH_EN_SHIFT, 1, 0),
SOC_SINGLE("IV Dither Switch", MAX98396_R20E0_IV_SENSE_PATH_CFG,
MAX98396_IV_SENSE_DITH_EN_SHIFT, 1, 0),
/* DC Blocker Enable */
SOC_SINGLE("DC Blocker Switch", MAX98396_R2092_AMP_DSP_CFG,
MAX98396_DSP_SPK_DCBLK_EN_SHIFT, 1, 0),
SOC_SINGLE("IV DC Blocker Switch", MAX98396_R20E0_IV_SENSE_PATH_CFG,
MAX98396_IV_SENSE_DCBLK_EN_SHIFT, 3, 0),
/* Speaker Safe Mode Enable */
SOC_SINGLE("Safe Mode Switch", MAX98396_R2092_AMP_DSP_CFG,
MAX98396_DSP_SPK_SAFE_EN_SHIFT, 1, 0),
/* Wideband Filter Enable */
SOC_SINGLE("WB Filter Switch", MAX98396_R2092_AMP_DSP_CFG,
MAX98396_DSP_SPK_WB_FLT_EN_SHIFT, 1, 0),
SOC_SINGLE("IV WB Filter Switch", MAX98396_R20E0_IV_SENSE_PATH_CFG,
MAX98396_IV_SENSE_WB_FLT_EN_SHIFT, 1, 0),
/* Dynamic Headroom Tracking */
SOC_SINGLE("DHT Switch", MAX98396_R20DF_DHT_EN, 0, 1, 0),
/* Brownout Protection Engine */
SOC_SINGLE("BPE Switch", MAX98396_R210D_BPE_EN, 0, 1, 0),
SOC_SINGLE("BPE Limiter Switch", MAX98396_R210D_BPE_EN, 1, 1, 0),
/* Bypass Path Enable */
SOC_SINGLE("Bypass Path Switch",
MAX98396_R205E_PCM_RX_EN, 1, 1, 0),
/* Speaker Operation Mode */
SOC_ENUM("OP Mode", max98396_op_mod_enum),
/* Auto Restart functions */
SOC_SINGLE("CMON Auto Restart Switch", MAX98396_R2038_CLK_MON_CTRL,
MAX98396_CLK_MON_AUTO_RESTART_SHIFT, 1, 0),
SOC_SINGLE("PVDD Auto Restart Switch", MAX98396_R210E_AUTO_RESTART,
MAX98396_PVDD_UVLO_RESTART_SHFT, 1, 0),
SOC_SINGLE("VBAT Auto Restart Switch", MAX98396_R210E_AUTO_RESTART,
MAX98396_VBAT_UVLO_RESTART_SHFT, 1, 0),
SOC_SINGLE("THERM Auto Restart Switch", MAX98396_R210E_AUTO_RESTART,
MAX98396_THEM_SHDN_RESTART_SHFT, 1, 0),
SOC_SINGLE("OVC Auto Restart Switch", MAX98396_R210E_AUTO_RESTART,
MAX98396_OVC_RESTART_SHFT, 1, 0),
/* Thermal Threshold */
SOC_ENUM("THERM Thresh1", max98396_thermal_warn_thresh1_enum),
SOC_ENUM("THERM Thresh2", max98396_thermal_warn_thresh2_enum),
SOC_ENUM("THERM SHDN Thresh", max98396_thermal_shdn_thresh_enum),
SOC_ENUM("THERM Hysteresis", max98396_thermal_hysteresis_enum),
SOC_SINGLE("THERM Foldback Switch",
MAX98396_R2027_THERM_FOLDBACK_EN, 0, 1, 0),
SOC_ENUM("THERM Slope1", max98396_thermal_fb_slope1_enum),
SOC_ENUM("THERM Slope2", max98396_thermal_fb_slope2_enum),
SOC_ENUM("THERM Release", max98396_thermal_fb_reltime_enum),
SOC_ENUM("THERM Hold", max98396_thermal_fb_holdtime_enum),
/* ADC */
SOC_SINGLE_EXT("ADC PVDD", MAX98396_R20B6_ADC_PVDD_READBACK_MSB, 0, 0x1FF, 0,
max98396_adc_value_get, NULL),
SOC_SINGLE_EXT("ADC VBAT", MAX98396_R20B8_ADC_VBAT_READBACK_MSB, 0, 0x1FF, 0,
max98396_adc_value_get, NULL),
SOC_SINGLE_EXT("ADC TEMP", MAX98396_R20BA_ADC_TEMP_READBACK_MSB, 0, 0x1FF, 0,
max98396_adc_value_get, NULL),
};
static const struct snd_soc_dapm_route max98396_audio_map[] = {
/* Plabyack */
{"DAI Sel Mux", "Left", "Amp Enable"},
{"DAI Sel Mux", "Right", "Amp Enable"},
{"DAI Sel Mux", "LeftRight", "Amp Enable"},
{"BE_OUT", NULL, "DAI Sel Mux"},
/* Capture */
{ "VI Sense", "Switch", "VMON" },
{ "VI Sense", "Switch", "IMON" },
{ "Voltage Sense", NULL, "VI Sense" },
{ "Current Sense", NULL, "VI Sense" },
};
static struct snd_soc_dai_driver max98396_dai[] = {
{
.name = "max98396-aif1",
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MAX98396_RATES,
.formats = MAX98396_FORMATS,
},
.capture = {
.stream_name = "HiFi Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MAX98396_RATES,
.formats = MAX98396_FORMATS,
},
.ops = &max98396_dai_ops,
}
};
static struct snd_soc_dai_driver max98397_dai[] = {
{
.name = "max98397-aif1",
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MAX98396_RATES,
.formats = MAX98396_FORMATS,
},
.capture = {
.stream_name = "HiFi Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MAX98396_RATES,
.formats = MAX98396_FORMATS,
},
.ops = &max98396_dai_ops,
}
};
static void max98396_reset(struct max98396_priv *max98396, struct device *dev)
{
int ret, reg, count;
/* Software Reset */
ret = regmap_write(max98396->regmap,
MAX98396_R2000_SW_RESET, 1);
if (ret)
dev_err(dev, "Reset command failed. (ret:%d)\n", ret);
count = 0;
while (count < 3) {
usleep_range(5000, 6000);
/* Software Reset Verification */
ret = regmap_read(max98396->regmap,
GET_REG_ADDR_REV_ID(max98396->device_id), ®);
if (!ret) {
dev_info(dev, "Reset completed (retry:%d)\n", count);
return;
}
count++;
}
dev_err(dev, "Reset failed. (ret:%d)\n", ret);
}
static int max98396_probe(struct snd_soc_component *component)
{
struct max98396_priv *max98396 =
snd_soc_component_get_drvdata(component);
/* Software Reset */
max98396_reset(max98396, component->dev);
/* L/R mix configuration */
if (max98396->device_id == CODEC_TYPE_MAX98396) {
regmap_write(max98396->regmap,
MAX98396_R2055_PCM_RX_SRC1, 0x02);
regmap_write(max98396->regmap,
MAX98396_R2056_PCM_RX_SRC2, 0x10);
} else {
regmap_write(max98396->regmap,
MAX98397_R2056_PCM_RX_SRC1, 0x02);
regmap_write(max98396->regmap,
MAX98397_R2057_PCM_RX_SRC2, 0x10);
}
/* Supply control */
regmap_update_bits(max98396->regmap,
MAX98396_R20A0_AMP_SUPPLY_CTL,
MAX98396_AMP_SUPPLY_NOVBAT,
(max98396->vbat == NULL) ?
MAX98396_AMP_SUPPLY_NOVBAT : 0);
/* Enable DC blocker */
regmap_update_bits(max98396->regmap,
MAX98396_R2092_AMP_DSP_CFG, 1, 1);
/* Enable IV Monitor DC blocker */
regmap_update_bits(max98396->regmap,
MAX98396_R20E0_IV_SENSE_PATH_CFG,
MAX98396_IV_SENSE_DCBLK_EN_MASK,
MAX98396_IV_SENSE_DCBLK_EN_MASK);
/* Configure default data output sources */
regmap_write(max98396->regmap,
MAX98396_R205D_PCM_TX_SRC_EN, 3);
/* Enable Wideband Filter */
regmap_update_bits(max98396->regmap,
MAX98396_R2092_AMP_DSP_CFG, 0x40, 0x40);
/* Enable IV Wideband Filter */
regmap_update_bits(max98396->regmap,
MAX98396_R20E0_IV_SENSE_PATH_CFG, 8, 8);
/* Enable Bypass Source */
regmap_write(max98396->regmap,
MAX98396_R2058_PCM_BYPASS_SRC,
max98396->bypass_slot);
/* Voltage, current slot configuration */
regmap_write(max98396->regmap,
MAX98396_R2044_PCM_TX_CTRL_1,
max98396->v_slot);
regmap_write(max98396->regmap,
MAX98396_R2045_PCM_TX_CTRL_2,
max98396->i_slot);
regmap_write(max98396->regmap,
MAX98396_R204A_PCM_TX_CTRL_7,
max98396->spkfb_slot);
if (max98396->v_slot < 8)
if (max98396->device_id == CODEC_TYPE_MAX98396)
regmap_update_bits(max98396->regmap,
MAX98396_R2053_PCM_TX_HIZ_CTRL_8,
1 << max98396->v_slot, 0);
else
regmap_update_bits(max98396->regmap,
MAX98397_R2054_PCM_TX_HIZ_CTRL_8,
1 << max98396->v_slot, 0);
else
if (max98396->device_id == CODEC_TYPE_MAX98396)
regmap_update_bits(max98396->regmap,
MAX98396_R2052_PCM_TX_HIZ_CTRL_7,
1 << (max98396->v_slot - 8), 0);
else
regmap_update_bits(max98396->regmap,
MAX98397_R2053_PCM_TX_HIZ_CTRL_7,
1 << (max98396->v_slot - 8), 0);
if (max98396->i_slot < 8)
if (max98396->device_id == CODEC_TYPE_MAX98396)
regmap_update_bits(max98396->regmap,
MAX98396_R2053_PCM_TX_HIZ_CTRL_8,
1 << max98396->i_slot, 0);
else
regmap_update_bits(max98396->regmap,
MAX98397_R2054_PCM_TX_HIZ_CTRL_8,
1 << max98396->i_slot, 0);
else
if (max98396->device_id == CODEC_TYPE_MAX98396)
regmap_update_bits(max98396->regmap,
MAX98396_R2052_PCM_TX_HIZ_CTRL_7,
1 << (max98396->i_slot - 8), 0);
else
regmap_update_bits(max98396->regmap,
MAX98397_R2053_PCM_TX_HIZ_CTRL_7,
1 << (max98396->i_slot - 8), 0);
/* Set interleave mode */
if (max98396->interleave_mode)
regmap_update_bits(max98396->regmap,
MAX98396_R2041_PCM_MODE_CFG,
MAX98396_PCM_TX_CH_INTERLEAVE_MASK,
MAX98396_PCM_TX_CH_INTERLEAVE_MASK);
regmap_update_bits(max98396->regmap,
MAX98396_R2038_CLK_MON_CTRL,
MAX98396_CLK_MON_AUTO_RESTART_MASK,
MAX98396_CLK_MON_AUTO_RESTART_MASK);
regmap_update_bits(max98396->regmap,
MAX98396_R203F_ENABLE_CTRLS,
MAX98396_CTRL_DMON_STUCK_EN_MASK,
max98396->dmon_stuck_enable ?
MAX98396_CTRL_DMON_STUCK_EN_MASK : 0);
regmap_update_bits(max98396->regmap,
MAX98396_R203F_ENABLE_CTRLS,
MAX98396_CTRL_DMON_MAG_EN_MASK,
max98396->dmon_mag_enable ?
MAX98396_CTRL_DMON_MAG_EN_MASK : 0);
switch (max98396->dmon_duration) {
case 64:
regmap_update_bits(max98396->regmap,
MAX98396_R2039_DATA_MON_CTRL,
MAX98396_DMON_DURATION_MASK, 0);
break;
case 256:
regmap_update_bits(max98396->regmap,
MAX98396_R2039_DATA_MON_CTRL,
MAX98396_DMON_DURATION_MASK, 1);
break;
case 1024:
regmap_update_bits(max98396->regmap,
MAX98396_R2039_DATA_MON_CTRL,
MAX98396_DMON_DURATION_MASK, 2);
break;
case 4096:
regmap_update_bits(max98396->regmap,
MAX98396_R2039_DATA_MON_CTRL,
MAX98396_DMON_DURATION_MASK, 3);
break;
default:
dev_err(component->dev, "Invalid DMON duration %d\n",
max98396->dmon_duration);
}
switch (max98396->dmon_stuck_threshold) {
case 15:
regmap_update_bits(max98396->regmap,
MAX98396_R2039_DATA_MON_CTRL,
MAX98396_DMON_STUCK_THRESH_MASK,
0 << MAX98396_DMON_STUCK_THRESH_SHIFT);
break;
case 13:
regmap_update_bits(max98396->regmap,
MAX98396_R2039_DATA_MON_CTRL,
MAX98396_DMON_STUCK_THRESH_MASK,
1 << MAX98396_DMON_STUCK_THRESH_SHIFT);
break;
case 22:
regmap_update_bits(max98396->regmap,
MAX98396_R2039_DATA_MON_CTRL,
MAX98396_DMON_STUCK_THRESH_MASK,
2 << MAX98396_DMON_STUCK_THRESH_SHIFT);
break;
case 9:
regmap_update_bits(max98396->regmap,
MAX98396_R2039_DATA_MON_CTRL,
MAX98396_DMON_STUCK_THRESH_MASK,
3 << MAX98396_DMON_STUCK_THRESH_SHIFT);
break;
default:
dev_err(component->dev, "Invalid DMON stuck threshold %d\n",
max98396->dmon_stuck_threshold);
}
switch (max98396->dmon_mag_threshold) {
case 2 ... 5:
regmap_update_bits(max98396->regmap,
MAX98396_R2039_DATA_MON_CTRL,
MAX98396_DMON_STUCK_THRESH_MASK,
(5 - max98396->dmon_mag_threshold)
<< MAX98396_DMON_MAG_THRESH_SHIFT);
break;
default:
dev_err(component->dev, "Invalid DMON magnitude threshold %d\n",
max98396->dmon_mag_threshold);
}
/* Speaker Amplifier PCM RX Enable by default */
regmap_update_bits(max98396->regmap,
MAX98396_R205E_PCM_RX_EN,
MAX98396_PCM_RX_EN_MASK, 1);
return 0;
}
#ifdef CONFIG_PM_SLEEP
static int max98396_suspend(struct device *dev)
{
struct max98396_priv *max98396 = dev_get_drvdata(dev);
regcache_cache_only(max98396->regmap, true);
regcache_mark_dirty(max98396->regmap);
regulator_bulk_disable(MAX98396_NUM_CORE_SUPPLIES,
max98396->core_supplies);
if (max98396->pvdd)
regulator_disable(max98396->pvdd);
if (max98396->vbat)
regulator_disable(max98396->vbat);
return 0;
}
static int max98396_resume(struct device *dev)
{
struct max98396_priv *max98396 = dev_get_drvdata(dev);
int ret;
ret = regulator_bulk_enable(MAX98396_NUM_CORE_SUPPLIES,
max98396->core_supplies);
if (ret < 0)
return ret;
if (max98396->pvdd) {
ret = regulator_enable(max98396->pvdd);
if (ret < 0)
return ret;
}
if (max98396->vbat) {
ret = regulator_enable(max98396->vbat);
if (ret < 0)
return ret;
}
regcache_cache_only(max98396->regmap, false);
max98396_reset(max98396, dev);
regcache_sync(max98396->regmap);
return 0;
}
#endif
static const struct dev_pm_ops max98396_pm = {
SET_SYSTEM_SLEEP_PM_OPS(max98396_suspend, max98396_resume)
};
static const struct snd_soc_component_driver soc_codec_dev_max98396 = {
.probe = max98396_probe,
.controls = max98396_snd_controls,
.num_controls = ARRAY_SIZE(max98396_snd_controls),
.dapm_widgets = max98396_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(max98396_dapm_widgets),
.dapm_routes = max98396_audio_map,
.num_dapm_routes = ARRAY_SIZE(max98396_audio_map),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct snd_soc_component_driver soc_codec_dev_max98397 = {
.probe = max98396_probe,
.controls = max98397_snd_controls,
.num_controls = ARRAY_SIZE(max98397_snd_controls),
.dapm_widgets = max98396_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(max98396_dapm_widgets),
.dapm_routes = max98396_audio_map,
.num_dapm_routes = ARRAY_SIZE(max98396_audio_map),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config max98396_regmap = {
.reg_bits = 16,
.val_bits = 8,
.max_register = MAX98396_R21FF_REVISION_ID,
.reg_defaults = max98396_reg,
.num_reg_defaults = ARRAY_SIZE(max98396_reg),
.readable_reg = max98396_readable_register,
.volatile_reg = max98396_volatile_reg,
.cache_type = REGCACHE_RBTREE,
};
static const struct regmap_config max98397_regmap = {
.reg_bits = 16,
.val_bits = 8,
.max_register = MAX98397_R22FF_REVISION_ID,
.reg_defaults = max98397_reg,
.num_reg_defaults = ARRAY_SIZE(max98397_reg),
.readable_reg = max98397_readable_register,
.volatile_reg = max98397_volatile_reg,
.cache_type = REGCACHE_RBTREE,
};
static void max98396_read_device_property(struct device *dev,
struct max98396_priv *max98396)
{
int value;
if (!device_property_read_u32(dev, "adi,vmon-slot-no", &value))
max98396->v_slot = value & 0xF;
else
max98396->v_slot = 0;
if (!device_property_read_u32(dev, "adi,imon-slot-no", &value))
max98396->i_slot = value & 0xF;
else
max98396->i_slot = 1;
if (!device_property_read_u32(dev, "adi,spkfb-slot-no", &value))
max98396->spkfb_slot = value & 0xF;
else
max98396->spkfb_slot = 2;
if (!device_property_read_u32(dev, "adi,bypass-slot-no", &value))
max98396->bypass_slot = value & 0xF;
else
max98396->bypass_slot = 0;
max98396->dmon_stuck_enable =
device_property_read_bool(dev, "adi,dmon-stuck-enable");
if (!device_property_read_u32(dev, "adi,dmon-stuck-threshold-bits", &value))
max98396->dmon_stuck_threshold = value;
else
max98396->dmon_stuck_threshold = 15;
max98396->dmon_mag_enable =
device_property_read_bool(dev, "adi,dmon-magnitude-enable");
if (!device_property_read_u32(dev, "adi,dmon-magnitude-threshold-bits", &value))
max98396->dmon_mag_threshold = value;
else
max98396->dmon_mag_threshold = 5;
if (!device_property_read_u32(dev, "adi,dmon-duration-ms", &value))
max98396->dmon_duration = value;
else
max98396->dmon_duration = 64;
}
static void max98396_core_supplies_disable(void *priv)
{
struct max98396_priv *max98396 = priv;
regulator_bulk_disable(MAX98396_NUM_CORE_SUPPLIES,
max98396->core_supplies);
}
static void max98396_supply_disable(void *r)
{
regulator_disable((struct regulator *) r);
}
static int max98396_i2c_probe(struct i2c_client *i2c)
{
const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
struct max98396_priv *max98396 = NULL;
int i, ret, reg;
max98396 = devm_kzalloc(&i2c->dev, sizeof(*max98396), GFP_KERNEL);
if (!max98396) {
ret = -ENOMEM;
return ret;
}
i2c_set_clientdata(i2c, max98396);
max98396->device_id = id->driver_data;
/* regmap initialization */
if (max98396->device_id == CODEC_TYPE_MAX98396)
max98396->regmap = devm_regmap_init_i2c(i2c, &max98396_regmap);
else
max98396->regmap = devm_regmap_init_i2c(i2c, &max98397_regmap);
if (IS_ERR(max98396->regmap)) {
ret = PTR_ERR(max98396->regmap);
dev_err(&i2c->dev,
"Failed to allocate regmap: %d\n", ret);
return ret;
}
/* Obtain regulator supplies */
for (i = 0; i < MAX98396_NUM_CORE_SUPPLIES; i++)
max98396->core_supplies[i].supply = max98396_core_supplies[i];
ret = devm_regulator_bulk_get(&i2c->dev, MAX98396_NUM_CORE_SUPPLIES,
max98396->core_supplies);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to request core supplies: %d\n", ret);
return ret;
}
max98396->vbat = devm_regulator_get_optional(&i2c->dev, "vbat");
if (IS_ERR(max98396->vbat)) {
if (PTR_ERR(max98396->vbat) == -EPROBE_DEFER)
return -EPROBE_DEFER;
max98396->vbat = NULL;
}
max98396->pvdd = devm_regulator_get_optional(&i2c->dev, "pvdd");
if (IS_ERR(max98396->pvdd)) {
if (PTR_ERR(max98396->pvdd) == -EPROBE_DEFER)
return -EPROBE_DEFER;
max98396->pvdd = NULL;
}
ret = regulator_bulk_enable(MAX98396_NUM_CORE_SUPPLIES,
max98396->core_supplies);
if (ret < 0) {
dev_err(&i2c->dev, "Unable to enable core supplies: %d", ret);
return ret;
}
ret = devm_add_action_or_reset(&i2c->dev, max98396_core_supplies_disable,
max98396);
if (ret < 0)
return ret;
if (max98396->pvdd) {
ret = regulator_enable(max98396->pvdd);
if (ret < 0)
return ret;
ret = devm_add_action_or_reset(&i2c->dev,
max98396_supply_disable,
max98396->pvdd);
if (ret < 0)
return ret;
}
if (max98396->vbat) {
ret = regulator_enable(max98396->vbat);
if (ret < 0)
return ret;
ret = devm_add_action_or_reset(&i2c->dev,
max98396_supply_disable,
max98396->vbat);
if (ret < 0)
return ret;
}
/* update interleave mode info */
if (device_property_read_bool(&i2c->dev, "adi,interleave_mode"))
max98396->interleave_mode = true;
else
max98396->interleave_mode = false;
/* voltage/current slot & gpio configuration */
max98396_read_device_property(&i2c->dev, max98396);
/* Reset the Device */
max98396->reset_gpio = devm_gpiod_get_optional(&i2c->dev,
"reset", GPIOD_OUT_HIGH);
if (IS_ERR(max98396->reset_gpio)) {
ret = PTR_ERR(max98396->reset_gpio);
dev_err(&i2c->dev, "Unable to request GPIO pin: %d.\n", ret);
return ret;
}
if (max98396->reset_gpio) {
usleep_range(5000, 6000);
gpiod_set_value_cansleep(max98396->reset_gpio, 0);
/* Wait for the hw reset done */
usleep_range(5000, 6000);
}
ret = regmap_read(max98396->regmap,
GET_REG_ADDR_REV_ID(max98396->device_id), ®);
if (ret < 0) {
dev_err(&i2c->dev, "%s: failed to read revision of the device.\n", id->name);
return ret;
}
dev_info(&i2c->dev, "%s revision ID: 0x%02X\n", id->name, reg);
/* codec registration */
if (max98396->device_id == CODEC_TYPE_MAX98396)
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_codec_dev_max98396,
max98396_dai,
ARRAY_SIZE(max98396_dai));
else
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_codec_dev_max98397,
max98397_dai,
ARRAY_SIZE(max98397_dai));
if (ret < 0)
dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
return ret;
}
static const struct i2c_device_id max98396_i2c_id[] = {
{ "max98396", CODEC_TYPE_MAX98396},
{ "max98397", CODEC_TYPE_MAX98397},
{ },
};
MODULE_DEVICE_TABLE(i2c, max98396_i2c_id);
#if defined(CONFIG_OF)
static const struct of_device_id max98396_of_match[] = {
{ .compatible = "adi,max98396", },
{ .compatible = "adi,max98397", },
{ }
};
MODULE_DEVICE_TABLE(of, max98396_of_match);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id max98396_acpi_match[] = {
{ "ADS8396", 0 },
{ "ADS8397", 0 },
{},
};
MODULE_DEVICE_TABLE(acpi, max98396_acpi_match);
#endif
static struct i2c_driver max98396_i2c_driver = {
.driver = {
.name = "max98396",
.of_match_table = of_match_ptr(max98396_of_match),
.acpi_match_table = ACPI_PTR(max98396_acpi_match),
.pm = &max98396_pm,
},
.probe = max98396_i2c_probe,
.id_table = max98396_i2c_id,
};
module_i2c_driver(max98396_i2c_driver)
MODULE_DESCRIPTION("ALSA SoC MAX98396 driver");
MODULE_AUTHOR("Ryan Lee <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/max98396.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8983.c -- WM8983 ALSA SoC Audio driver
*
* Copyright 2011 Wolfson Microelectronics plc
*
* Author: Dimitris Papastamos <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "wm8983.h"
static const struct reg_default wm8983_defaults[] = {
{ 0x01, 0x0000 }, /* R1 - Power management 1 */
{ 0x02, 0x0000 }, /* R2 - Power management 2 */
{ 0x03, 0x0000 }, /* R3 - Power management 3 */
{ 0x04, 0x0050 }, /* R4 - Audio Interface */
{ 0x05, 0x0000 }, /* R5 - Companding control */
{ 0x06, 0x0140 }, /* R6 - Clock Gen control */
{ 0x07, 0x0000 }, /* R7 - Additional control */
{ 0x08, 0x0000 }, /* R8 - GPIO Control */
{ 0x09, 0x0000 }, /* R9 - Jack Detect Control 1 */
{ 0x0A, 0x0000 }, /* R10 - DAC Control */
{ 0x0B, 0x00FF }, /* R11 - Left DAC digital Vol */
{ 0x0C, 0x00FF }, /* R12 - Right DAC digital vol */
{ 0x0D, 0x0000 }, /* R13 - Jack Detect Control 2 */
{ 0x0E, 0x0100 }, /* R14 - ADC Control */
{ 0x0F, 0x00FF }, /* R15 - Left ADC Digital Vol */
{ 0x10, 0x00FF }, /* R16 - Right ADC Digital Vol */
{ 0x12, 0x012C }, /* R18 - EQ1 - low shelf */
{ 0x13, 0x002C }, /* R19 - EQ2 - peak 1 */
{ 0x14, 0x002C }, /* R20 - EQ3 - peak 2 */
{ 0x15, 0x002C }, /* R21 - EQ4 - peak 3 */
{ 0x16, 0x002C }, /* R22 - EQ5 - high shelf */
{ 0x18, 0x0032 }, /* R24 - DAC Limiter 1 */
{ 0x19, 0x0000 }, /* R25 - DAC Limiter 2 */
{ 0x1B, 0x0000 }, /* R27 - Notch Filter 1 */
{ 0x1C, 0x0000 }, /* R28 - Notch Filter 2 */
{ 0x1D, 0x0000 }, /* R29 - Notch Filter 3 */
{ 0x1E, 0x0000 }, /* R30 - Notch Filter 4 */
{ 0x20, 0x0038 }, /* R32 - ALC control 1 */
{ 0x21, 0x000B }, /* R33 - ALC control 2 */
{ 0x22, 0x0032 }, /* R34 - ALC control 3 */
{ 0x23, 0x0000 }, /* R35 - Noise Gate */
{ 0x24, 0x0008 }, /* R36 - PLL N */
{ 0x25, 0x000C }, /* R37 - PLL K 1 */
{ 0x26, 0x0093 }, /* R38 - PLL K 2 */
{ 0x27, 0x00E9 }, /* R39 - PLL K 3 */
{ 0x29, 0x0000 }, /* R41 - 3D control */
{ 0x2A, 0x0000 }, /* R42 - OUT4 to ADC */
{ 0x2B, 0x0000 }, /* R43 - Beep control */
{ 0x2C, 0x0033 }, /* R44 - Input ctrl */
{ 0x2D, 0x0010 }, /* R45 - Left INP PGA gain ctrl */
{ 0x2E, 0x0010 }, /* R46 - Right INP PGA gain ctrl */
{ 0x2F, 0x0100 }, /* R47 - Left ADC BOOST ctrl */
{ 0x30, 0x0100 }, /* R48 - Right ADC BOOST ctrl */
{ 0x31, 0x0002 }, /* R49 - Output ctrl */
{ 0x32, 0x0001 }, /* R50 - Left mixer ctrl */
{ 0x33, 0x0001 }, /* R51 - Right mixer ctrl */
{ 0x34, 0x0039 }, /* R52 - LOUT1 (HP) volume ctrl */
{ 0x35, 0x0039 }, /* R53 - ROUT1 (HP) volume ctrl */
{ 0x36, 0x0039 }, /* R54 - LOUT2 (SPK) volume ctrl */
{ 0x37, 0x0039 }, /* R55 - ROUT2 (SPK) volume ctrl */
{ 0x38, 0x0001 }, /* R56 - OUT3 mixer ctrl */
{ 0x39, 0x0001 }, /* R57 - OUT4 (MONO) mix ctrl */
{ 0x3D, 0x0000 }, /* R61 - BIAS CTRL */
};
/* vol/gain update regs */
static const int vol_update_regs[] = {
WM8983_LEFT_DAC_DIGITAL_VOL,
WM8983_RIGHT_DAC_DIGITAL_VOL,
WM8983_LEFT_ADC_DIGITAL_VOL,
WM8983_RIGHT_ADC_DIGITAL_VOL,
WM8983_LOUT1_HP_VOLUME_CTRL,
WM8983_ROUT1_HP_VOLUME_CTRL,
WM8983_LOUT2_SPK_VOLUME_CTRL,
WM8983_ROUT2_SPK_VOLUME_CTRL,
WM8983_LEFT_INP_PGA_GAIN_CTRL,
WM8983_RIGHT_INP_PGA_GAIN_CTRL
};
struct wm8983_priv {
struct regmap *regmap;
u32 sysclk;
u32 bclk;
};
static const struct {
int div;
int ratio;
} fs_ratios[] = {
{ 10, 128 },
{ 15, 192 },
{ 20, 256 },
{ 30, 384 },
{ 40, 512 },
{ 60, 768 },
{ 80, 1024 },
{ 120, 1536 }
};
static const int srates[] = { 48000, 32000, 24000, 16000, 12000, 8000 };
static const int bclk_divs[] = {
1, 2, 4, 8, 16, 32
};
static int eqmode_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
static int eqmode_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
static const DECLARE_TLV_DB_SCALE(dac_tlv, -12700, 50, 1);
static const DECLARE_TLV_DB_SCALE(adc_tlv, -12700, 50, 1);
static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
static const DECLARE_TLV_DB_SCALE(lim_thresh_tlv, -600, 100, 0);
static const DECLARE_TLV_DB_SCALE(lim_boost_tlv, 0, 100, 0);
static const DECLARE_TLV_DB_SCALE(alc_min_tlv, -1200, 600, 0);
static const DECLARE_TLV_DB_SCALE(alc_max_tlv, -675, 600, 0);
static const DECLARE_TLV_DB_SCALE(alc_tar_tlv, -2250, 150, 0);
static const DECLARE_TLV_DB_SCALE(pga_vol_tlv, -1200, 75, 0);
static const DECLARE_TLV_DB_SCALE(boost_tlv, -1200, 300, 1);
static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
static const DECLARE_TLV_DB_SCALE(aux_tlv, -1500, 300, 0);
static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
static const DECLARE_TLV_DB_SCALE(pga_boost_tlv, 0, 2000, 0);
static const char *alc_sel_text[] = { "Off", "Right", "Left", "Stereo" };
static SOC_ENUM_SINGLE_DECL(alc_sel, WM8983_ALC_CONTROL_1, 7, alc_sel_text);
static const char *alc_mode_text[] = { "ALC", "Limiter" };
static SOC_ENUM_SINGLE_DECL(alc_mode, WM8983_ALC_CONTROL_3, 8, alc_mode_text);
static const char *filter_mode_text[] = { "Audio", "Application" };
static SOC_ENUM_SINGLE_DECL(filter_mode, WM8983_ADC_CONTROL, 7,
filter_mode_text);
static const char *eq_bw_text[] = { "Narrow", "Wide" };
static const char *eqmode_text[] = { "Capture", "Playback" };
static SOC_ENUM_SINGLE_EXT_DECL(eqmode, eqmode_text);
static const char *eq1_cutoff_text[] = {
"80Hz", "105Hz", "135Hz", "175Hz"
};
static SOC_ENUM_SINGLE_DECL(eq1_cutoff, WM8983_EQ1_LOW_SHELF, 5,
eq1_cutoff_text);
static const char *eq2_cutoff_text[] = {
"230Hz", "300Hz", "385Hz", "500Hz"
};
static SOC_ENUM_SINGLE_DECL(eq2_bw, WM8983_EQ2_PEAK_1, 8, eq_bw_text);
static SOC_ENUM_SINGLE_DECL(eq2_cutoff, WM8983_EQ2_PEAK_1, 5, eq2_cutoff_text);
static const char *eq3_cutoff_text[] = {
"650Hz", "850Hz", "1.1kHz", "1.4kHz"
};
static SOC_ENUM_SINGLE_DECL(eq3_bw, WM8983_EQ3_PEAK_2, 8, eq_bw_text);
static SOC_ENUM_SINGLE_DECL(eq3_cutoff, WM8983_EQ3_PEAK_2, 5, eq3_cutoff_text);
static const char *eq4_cutoff_text[] = {
"1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz"
};
static SOC_ENUM_SINGLE_DECL(eq4_bw, WM8983_EQ4_PEAK_3, 8, eq_bw_text);
static SOC_ENUM_SINGLE_DECL(eq4_cutoff, WM8983_EQ4_PEAK_3, 5, eq4_cutoff_text);
static const char *eq5_cutoff_text[] = {
"5.3kHz", "6.9kHz", "9kHz", "11.7kHz"
};
static SOC_ENUM_SINGLE_DECL(eq5_cutoff, WM8983_EQ5_HIGH_SHELF, 5,
eq5_cutoff_text);
static const char *depth_3d_text[] = {
"Off",
"6.67%",
"13.3%",
"20%",
"26.7%",
"33.3%",
"40%",
"46.6%",
"53.3%",
"60%",
"66.7%",
"73.3%",
"80%",
"86.7%",
"93.3%",
"100%"
};
static SOC_ENUM_SINGLE_DECL(depth_3d, WM8983_3D_CONTROL, 0,
depth_3d_text);
static const struct snd_kcontrol_new wm8983_snd_controls[] = {
SOC_SINGLE("Digital Loopback Switch", WM8983_COMPANDING_CONTROL,
0, 1, 0),
SOC_ENUM("ALC Capture Function", alc_sel),
SOC_SINGLE_TLV("ALC Capture Max Volume", WM8983_ALC_CONTROL_1,
3, 7, 0, alc_max_tlv),
SOC_SINGLE_TLV("ALC Capture Min Volume", WM8983_ALC_CONTROL_1,
0, 7, 0, alc_min_tlv),
SOC_SINGLE_TLV("ALC Capture Target Volume", WM8983_ALC_CONTROL_2,
0, 15, 0, alc_tar_tlv),
SOC_SINGLE("ALC Capture Attack", WM8983_ALC_CONTROL_3, 0, 10, 0),
SOC_SINGLE("ALC Capture Hold", WM8983_ALC_CONTROL_2, 4, 10, 0),
SOC_SINGLE("ALC Capture Decay", WM8983_ALC_CONTROL_3, 4, 10, 0),
SOC_ENUM("ALC Mode", alc_mode),
SOC_SINGLE("ALC Capture NG Switch", WM8983_NOISE_GATE,
3, 1, 0),
SOC_SINGLE("ALC Capture NG Threshold", WM8983_NOISE_GATE,
0, 7, 1),
SOC_DOUBLE_R_TLV("Capture Volume", WM8983_LEFT_ADC_DIGITAL_VOL,
WM8983_RIGHT_ADC_DIGITAL_VOL, 0, 255, 0, adc_tlv),
SOC_DOUBLE_R("Capture PGA ZC Switch", WM8983_LEFT_INP_PGA_GAIN_CTRL,
WM8983_RIGHT_INP_PGA_GAIN_CTRL, 7, 1, 0),
SOC_DOUBLE_R_TLV("Capture PGA Volume", WM8983_LEFT_INP_PGA_GAIN_CTRL,
WM8983_RIGHT_INP_PGA_GAIN_CTRL, 0, 63, 0, pga_vol_tlv),
SOC_DOUBLE_R_TLV("Capture PGA Boost Volume",
WM8983_LEFT_ADC_BOOST_CTRL, WM8983_RIGHT_ADC_BOOST_CTRL,
8, 1, 0, pga_boost_tlv),
SOC_DOUBLE("ADC Inversion Switch", WM8983_ADC_CONTROL, 0, 1, 1, 0),
SOC_SINGLE("ADC 128x Oversampling Switch", WM8983_ADC_CONTROL, 8, 1, 0),
SOC_DOUBLE_R_TLV("Playback Volume", WM8983_LEFT_DAC_DIGITAL_VOL,
WM8983_RIGHT_DAC_DIGITAL_VOL, 0, 255, 0, dac_tlv),
SOC_SINGLE("DAC Playback Limiter Switch", WM8983_DAC_LIMITER_1, 8, 1, 0),
SOC_SINGLE("DAC Playback Limiter Decay", WM8983_DAC_LIMITER_1, 4, 10, 0),
SOC_SINGLE("DAC Playback Limiter Attack", WM8983_DAC_LIMITER_1, 0, 11, 0),
SOC_SINGLE_TLV("DAC Playback Limiter Threshold", WM8983_DAC_LIMITER_2,
4, 7, 1, lim_thresh_tlv),
SOC_SINGLE_TLV("DAC Playback Limiter Boost Volume", WM8983_DAC_LIMITER_2,
0, 12, 0, lim_boost_tlv),
SOC_DOUBLE("DAC Inversion Switch", WM8983_DAC_CONTROL, 0, 1, 1, 0),
SOC_SINGLE("DAC Auto Mute Switch", WM8983_DAC_CONTROL, 2, 1, 0),
SOC_SINGLE("DAC 128x Oversampling Switch", WM8983_DAC_CONTROL, 3, 1, 0),
SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8983_LOUT1_HP_VOLUME_CTRL,
WM8983_ROUT1_HP_VOLUME_CTRL, 0, 63, 0, out_tlv),
SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8983_LOUT1_HP_VOLUME_CTRL,
WM8983_ROUT1_HP_VOLUME_CTRL, 7, 1, 0),
SOC_DOUBLE_R("Headphone Switch", WM8983_LOUT1_HP_VOLUME_CTRL,
WM8983_ROUT1_HP_VOLUME_CTRL, 6, 1, 1),
SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8983_LOUT2_SPK_VOLUME_CTRL,
WM8983_ROUT2_SPK_VOLUME_CTRL, 0, 63, 0, out_tlv),
SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8983_LOUT2_SPK_VOLUME_CTRL,
WM8983_ROUT2_SPK_VOLUME_CTRL, 7, 1, 0),
SOC_DOUBLE_R("Speaker Switch", WM8983_LOUT2_SPK_VOLUME_CTRL,
WM8983_ROUT2_SPK_VOLUME_CTRL, 6, 1, 1),
SOC_SINGLE("OUT3 Switch", WM8983_OUT3_MIXER_CTRL,
6, 1, 1),
SOC_SINGLE("OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL,
6, 1, 1),
SOC_SINGLE("High Pass Filter Switch", WM8983_ADC_CONTROL, 8, 1, 0),
SOC_ENUM("High Pass Filter Mode", filter_mode),
SOC_SINGLE("High Pass Filter Cutoff", WM8983_ADC_CONTROL, 4, 7, 0),
SOC_DOUBLE_R_TLV("Aux Bypass Volume",
WM8983_LEFT_MIXER_CTRL, WM8983_RIGHT_MIXER_CTRL, 6, 7, 0,
aux_tlv),
SOC_DOUBLE_R_TLV("Input PGA Bypass Volume",
WM8983_LEFT_MIXER_CTRL, WM8983_RIGHT_MIXER_CTRL, 2, 7, 0,
bypass_tlv),
SOC_ENUM_EXT("Equalizer Function", eqmode, eqmode_get, eqmode_put),
SOC_ENUM("EQ1 Cutoff", eq1_cutoff),
SOC_SINGLE_TLV("EQ1 Volume", WM8983_EQ1_LOW_SHELF, 0, 24, 1, eq_tlv),
SOC_ENUM("EQ2 Bandwidth", eq2_bw),
SOC_ENUM("EQ2 Cutoff", eq2_cutoff),
SOC_SINGLE_TLV("EQ2 Volume", WM8983_EQ2_PEAK_1, 0, 24, 1, eq_tlv),
SOC_ENUM("EQ3 Bandwidth", eq3_bw),
SOC_ENUM("EQ3 Cutoff", eq3_cutoff),
SOC_SINGLE_TLV("EQ3 Volume", WM8983_EQ3_PEAK_2, 0, 24, 1, eq_tlv),
SOC_ENUM("EQ4 Bandwidth", eq4_bw),
SOC_ENUM("EQ4 Cutoff", eq4_cutoff),
SOC_SINGLE_TLV("EQ4 Volume", WM8983_EQ4_PEAK_3, 0, 24, 1, eq_tlv),
SOC_ENUM("EQ5 Cutoff", eq5_cutoff),
SOC_SINGLE_TLV("EQ5 Volume", WM8983_EQ5_HIGH_SHELF, 0, 24, 1, eq_tlv),
SOC_ENUM("3D Depth", depth_3d),
};
static const struct snd_kcontrol_new left_out_mixer[] = {
SOC_DAPM_SINGLE("Line Switch", WM8983_LEFT_MIXER_CTRL, 1, 1, 0),
SOC_DAPM_SINGLE("Aux Switch", WM8983_LEFT_MIXER_CTRL, 5, 1, 0),
SOC_DAPM_SINGLE("PCM Switch", WM8983_LEFT_MIXER_CTRL, 0, 1, 0),
};
static const struct snd_kcontrol_new right_out_mixer[] = {
SOC_DAPM_SINGLE("Line Switch", WM8983_RIGHT_MIXER_CTRL, 1, 1, 0),
SOC_DAPM_SINGLE("Aux Switch", WM8983_RIGHT_MIXER_CTRL, 5, 1, 0),
SOC_DAPM_SINGLE("PCM Switch", WM8983_RIGHT_MIXER_CTRL, 0, 1, 0),
};
static const struct snd_kcontrol_new left_input_mixer[] = {
SOC_DAPM_SINGLE("L2 Switch", WM8983_INPUT_CTRL, 2, 1, 0),
SOC_DAPM_SINGLE("MicN Switch", WM8983_INPUT_CTRL, 1, 1, 0),
SOC_DAPM_SINGLE("MicP Switch", WM8983_INPUT_CTRL, 0, 1, 0),
};
static const struct snd_kcontrol_new right_input_mixer[] = {
SOC_DAPM_SINGLE("R2 Switch", WM8983_INPUT_CTRL, 6, 1, 0),
SOC_DAPM_SINGLE("MicN Switch", WM8983_INPUT_CTRL, 5, 1, 0),
SOC_DAPM_SINGLE("MicP Switch", WM8983_INPUT_CTRL, 4, 1, 0),
};
static const struct snd_kcontrol_new left_boost_mixer[] = {
SOC_DAPM_SINGLE_TLV("L2 Volume", WM8983_LEFT_ADC_BOOST_CTRL,
4, 7, 0, boost_tlv),
SOC_DAPM_SINGLE_TLV("AUXL Volume", WM8983_LEFT_ADC_BOOST_CTRL,
0, 7, 0, boost_tlv)
};
static const struct snd_kcontrol_new out3_mixer[] = {
SOC_DAPM_SINGLE("LMIX2OUT3 Switch", WM8983_OUT3_MIXER_CTRL,
1, 1, 0),
SOC_DAPM_SINGLE("LDAC2OUT3 Switch", WM8983_OUT3_MIXER_CTRL,
0, 1, 0),
};
static const struct snd_kcontrol_new out4_mixer[] = {
SOC_DAPM_SINGLE("LMIX2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL,
4, 1, 0),
SOC_DAPM_SINGLE("RMIX2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL,
1, 1, 0),
SOC_DAPM_SINGLE("LDAC2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL,
3, 1, 0),
SOC_DAPM_SINGLE("RDAC2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL,
0, 1, 0),
};
static const struct snd_kcontrol_new right_boost_mixer[] = {
SOC_DAPM_SINGLE_TLV("R2 Volume", WM8983_RIGHT_ADC_BOOST_CTRL,
4, 7, 0, boost_tlv),
SOC_DAPM_SINGLE_TLV("AUXR Volume", WM8983_RIGHT_ADC_BOOST_CTRL,
0, 7, 0, boost_tlv)
};
static const struct snd_soc_dapm_widget wm8983_dapm_widgets[] = {
SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8983_POWER_MANAGEMENT_3,
0, 0),
SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8983_POWER_MANAGEMENT_3,
1, 0),
SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8983_POWER_MANAGEMENT_2,
0, 0),
SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8983_POWER_MANAGEMENT_2,
1, 0),
SND_SOC_DAPM_MIXER("Left Output Mixer", WM8983_POWER_MANAGEMENT_3,
2, 0, left_out_mixer, ARRAY_SIZE(left_out_mixer)),
SND_SOC_DAPM_MIXER("Right Output Mixer", WM8983_POWER_MANAGEMENT_3,
3, 0, right_out_mixer, ARRAY_SIZE(right_out_mixer)),
SND_SOC_DAPM_MIXER("Left Input Mixer", WM8983_POWER_MANAGEMENT_2,
2, 0, left_input_mixer, ARRAY_SIZE(left_input_mixer)),
SND_SOC_DAPM_MIXER("Right Input Mixer", WM8983_POWER_MANAGEMENT_2,
3, 0, right_input_mixer, ARRAY_SIZE(right_input_mixer)),
SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8983_POWER_MANAGEMENT_2,
4, 0, left_boost_mixer, ARRAY_SIZE(left_boost_mixer)),
SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8983_POWER_MANAGEMENT_2,
5, 0, right_boost_mixer, ARRAY_SIZE(right_boost_mixer)),
SND_SOC_DAPM_MIXER("OUT3 Mixer", WM8983_POWER_MANAGEMENT_1,
6, 0, out3_mixer, ARRAY_SIZE(out3_mixer)),
SND_SOC_DAPM_MIXER("OUT4 Mixer", WM8983_POWER_MANAGEMENT_1,
7, 0, out4_mixer, ARRAY_SIZE(out4_mixer)),
SND_SOC_DAPM_PGA("Left Capture PGA", WM8983_LEFT_INP_PGA_GAIN_CTRL,
6, 1, NULL, 0),
SND_SOC_DAPM_PGA("Right Capture PGA", WM8983_RIGHT_INP_PGA_GAIN_CTRL,
6, 1, NULL, 0),
SND_SOC_DAPM_PGA("Left Headphone Out", WM8983_POWER_MANAGEMENT_2,
7, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Headphone Out", WM8983_POWER_MANAGEMENT_2,
8, 0, NULL, 0),
SND_SOC_DAPM_PGA("Left Speaker Out", WM8983_POWER_MANAGEMENT_3,
5, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Speaker Out", WM8983_POWER_MANAGEMENT_3,
6, 0, NULL, 0),
SND_SOC_DAPM_PGA("OUT3 Out", WM8983_POWER_MANAGEMENT_3,
7, 0, NULL, 0),
SND_SOC_DAPM_PGA("OUT4 Out", WM8983_POWER_MANAGEMENT_3,
8, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Mic Bias", WM8983_POWER_MANAGEMENT_1, 4, 0,
NULL, 0),
SND_SOC_DAPM_INPUT("LIN"),
SND_SOC_DAPM_INPUT("LIP"),
SND_SOC_DAPM_INPUT("RIN"),
SND_SOC_DAPM_INPUT("RIP"),
SND_SOC_DAPM_INPUT("AUXL"),
SND_SOC_DAPM_INPUT("AUXR"),
SND_SOC_DAPM_INPUT("L2"),
SND_SOC_DAPM_INPUT("R2"),
SND_SOC_DAPM_OUTPUT("HPL"),
SND_SOC_DAPM_OUTPUT("HPR"),
SND_SOC_DAPM_OUTPUT("SPKL"),
SND_SOC_DAPM_OUTPUT("SPKR"),
SND_SOC_DAPM_OUTPUT("OUT3"),
SND_SOC_DAPM_OUTPUT("OUT4")
};
static const struct snd_soc_dapm_route wm8983_audio_map[] = {
{ "OUT3 Mixer", "LMIX2OUT3 Switch", "Left Output Mixer" },
{ "OUT3 Mixer", "LDAC2OUT3 Switch", "Left DAC" },
{ "OUT3 Out", NULL, "OUT3 Mixer" },
{ "OUT3", NULL, "OUT3 Out" },
{ "OUT4 Mixer", "LMIX2OUT4 Switch", "Left Output Mixer" },
{ "OUT4 Mixer", "RMIX2OUT4 Switch", "Right Output Mixer" },
{ "OUT4 Mixer", "LDAC2OUT4 Switch", "Left DAC" },
{ "OUT4 Mixer", "RDAC2OUT4 Switch", "Right DAC" },
{ "OUT4 Out", NULL, "OUT4 Mixer" },
{ "OUT4", NULL, "OUT4 Out" },
{ "Right Output Mixer", "PCM Switch", "Right DAC" },
{ "Right Output Mixer", "Aux Switch", "AUXR" },
{ "Right Output Mixer", "Line Switch", "Right Boost Mixer" },
{ "Left Output Mixer", "PCM Switch", "Left DAC" },
{ "Left Output Mixer", "Aux Switch", "AUXL" },
{ "Left Output Mixer", "Line Switch", "Left Boost Mixer" },
{ "Right Headphone Out", NULL, "Right Output Mixer" },
{ "HPR", NULL, "Right Headphone Out" },
{ "Left Headphone Out", NULL, "Left Output Mixer" },
{ "HPL", NULL, "Left Headphone Out" },
{ "Right Speaker Out", NULL, "Right Output Mixer" },
{ "SPKR", NULL, "Right Speaker Out" },
{ "Left Speaker Out", NULL, "Left Output Mixer" },
{ "SPKL", NULL, "Left Speaker Out" },
{ "Right ADC", NULL, "Right Boost Mixer" },
{ "Right Boost Mixer", "AUXR Volume", "AUXR" },
{ "Right Boost Mixer", NULL, "Right Capture PGA" },
{ "Right Boost Mixer", "R2 Volume", "R2" },
{ "Left ADC", NULL, "Left Boost Mixer" },
{ "Left Boost Mixer", "AUXL Volume", "AUXL" },
{ "Left Boost Mixer", NULL, "Left Capture PGA" },
{ "Left Boost Mixer", "L2 Volume", "L2" },
{ "Right Capture PGA", NULL, "Right Input Mixer" },
{ "Left Capture PGA", NULL, "Left Input Mixer" },
{ "Right Input Mixer", "R2 Switch", "R2" },
{ "Right Input Mixer", "MicN Switch", "RIN" },
{ "Right Input Mixer", "MicP Switch", "RIP" },
{ "Left Input Mixer", "L2 Switch", "L2" },
{ "Left Input Mixer", "MicN Switch", "LIN" },
{ "Left Input Mixer", "MicP Switch", "LIP" },
};
static int eqmode_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
unsigned int reg;
reg = snd_soc_component_read(component, WM8983_EQ1_LOW_SHELF);
if (reg & WM8983_EQ3DMODE)
ucontrol->value.enumerated.item[0] = 1;
else
ucontrol->value.enumerated.item[0] = 0;
return 0;
}
static int eqmode_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
unsigned int regpwr2, regpwr3;
unsigned int reg_eq;
if (ucontrol->value.enumerated.item[0] != 0
&& ucontrol->value.enumerated.item[0] != 1)
return -EINVAL;
reg_eq = snd_soc_component_read(component, WM8983_EQ1_LOW_SHELF);
switch ((reg_eq & WM8983_EQ3DMODE) >> WM8983_EQ3DMODE_SHIFT) {
case 0:
if (!ucontrol->value.enumerated.item[0])
return 0;
break;
case 1:
if (ucontrol->value.enumerated.item[0])
return 0;
break;
}
regpwr2 = snd_soc_component_read(component, WM8983_POWER_MANAGEMENT_2);
regpwr3 = snd_soc_component_read(component, WM8983_POWER_MANAGEMENT_3);
/* disable the DACs and ADCs */
snd_soc_component_update_bits(component, WM8983_POWER_MANAGEMENT_2,
WM8983_ADCENR_MASK | WM8983_ADCENL_MASK, 0);
snd_soc_component_update_bits(component, WM8983_POWER_MANAGEMENT_3,
WM8983_DACENR_MASK | WM8983_DACENL_MASK, 0);
/* set the desired eqmode */
snd_soc_component_update_bits(component, WM8983_EQ1_LOW_SHELF,
WM8983_EQ3DMODE_MASK,
ucontrol->value.enumerated.item[0]
<< WM8983_EQ3DMODE_SHIFT);
/* restore DAC/ADC configuration */
snd_soc_component_write(component, WM8983_POWER_MANAGEMENT_2, regpwr2);
snd_soc_component_write(component, WM8983_POWER_MANAGEMENT_3, regpwr3);
return 0;
}
static bool wm8983_writeable(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8983_SOFTWARE_RESET ... WM8983_RIGHT_ADC_DIGITAL_VOL:
case WM8983_EQ1_LOW_SHELF ... WM8983_DAC_LIMITER_2:
case WM8983_NOTCH_FILTER_1 ... WM8983_NOTCH_FILTER_4:
case WM8983_ALC_CONTROL_1 ... WM8983_PLL_K_3:
case WM8983_3D_CONTROL ... WM8983_OUT4_MONO_MIX_CTRL:
case WM8983_BIAS_CTRL:
return true;
default:
return false;
}
}
static int wm8983_dac_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
return snd_soc_component_update_bits(component, WM8983_DAC_CONTROL,
WM8983_SOFTMUTE_MASK,
!!mute << WM8983_SOFTMUTE_SHIFT);
}
static int wm8983_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
u16 format, master, bcp, lrp;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
format = 0x2;
break;
case SND_SOC_DAIFMT_RIGHT_J:
format = 0x0;
break;
case SND_SOC_DAIFMT_LEFT_J:
format = 0x1;
break;
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B:
format = 0x3;
break;
default:
dev_err(dai->dev, "Unknown dai format\n");
return -EINVAL;
}
snd_soc_component_update_bits(component, WM8983_AUDIO_INTERFACE,
WM8983_FMT_MASK, format << WM8983_FMT_SHIFT);
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
master = 1;
break;
case SND_SOC_DAIFMT_CBS_CFS:
master = 0;
break;
default:
dev_err(dai->dev, "Unknown master/slave configuration\n");
return -EINVAL;
}
snd_soc_component_update_bits(component, WM8983_CLOCK_GEN_CONTROL,
WM8983_MS_MASK, master << WM8983_MS_SHIFT);
/* FIXME: We don't currently support DSP A/B modes */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B:
dev_err(dai->dev, "DSP A/B modes are not supported\n");
return -EINVAL;
default:
break;
}
bcp = lrp = 0;
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
bcp = lrp = 1;
break;
case SND_SOC_DAIFMT_IB_NF:
bcp = 1;
break;
case SND_SOC_DAIFMT_NB_IF:
lrp = 1;
break;
default:
dev_err(dai->dev, "Unknown polarity configuration\n");
return -EINVAL;
}
snd_soc_component_update_bits(component, WM8983_AUDIO_INTERFACE,
WM8983_LRCP_MASK, lrp << WM8983_LRCP_SHIFT);
snd_soc_component_update_bits(component, WM8983_AUDIO_INTERFACE,
WM8983_BCP_MASK, bcp << WM8983_BCP_SHIFT);
return 0;
}
static int wm8983_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
int i;
struct snd_soc_component *component = dai->component;
struct wm8983_priv *wm8983 = snd_soc_component_get_drvdata(component);
u16 blen, srate_idx;
u32 tmp;
int srate_best;
int ret;
ret = snd_soc_params_to_bclk(params);
if (ret < 0) {
dev_err(component->dev, "Failed to convert params to bclk: %d\n", ret);
return ret;
}
wm8983->bclk = ret;
switch (params_width(params)) {
case 16:
blen = 0x0;
break;
case 20:
blen = 0x1;
break;
case 24:
blen = 0x2;
break;
case 32:
blen = 0x3;
break;
default:
dev_err(dai->dev, "Unsupported word length %u\n",
params_width(params));
return -EINVAL;
}
snd_soc_component_update_bits(component, WM8983_AUDIO_INTERFACE,
WM8983_WL_MASK, blen << WM8983_WL_SHIFT);
/*
* match to the nearest possible sample rate and rely
* on the array index to configure the SR register
*/
srate_idx = 0;
srate_best = abs(srates[0] - params_rate(params));
for (i = 1; i < ARRAY_SIZE(srates); ++i) {
if (abs(srates[i] - params_rate(params)) >= srate_best)
continue;
srate_idx = i;
srate_best = abs(srates[i] - params_rate(params));
}
dev_dbg(dai->dev, "Selected SRATE = %d\n", srates[srate_idx]);
snd_soc_component_update_bits(component, WM8983_ADDITIONAL_CONTROL,
WM8983_SR_MASK, srate_idx << WM8983_SR_SHIFT);
dev_dbg(dai->dev, "Target BCLK = %uHz\n", wm8983->bclk);
dev_dbg(dai->dev, "SYSCLK = %uHz\n", wm8983->sysclk);
for (i = 0; i < ARRAY_SIZE(fs_ratios); ++i) {
if (wm8983->sysclk / params_rate(params)
== fs_ratios[i].ratio)
break;
}
if (i == ARRAY_SIZE(fs_ratios)) {
dev_err(dai->dev, "Unable to configure MCLK ratio %u/%u\n",
wm8983->sysclk, params_rate(params));
return -EINVAL;
}
dev_dbg(dai->dev, "MCLK ratio = %dfs\n", fs_ratios[i].ratio);
snd_soc_component_update_bits(component, WM8983_CLOCK_GEN_CONTROL,
WM8983_MCLKDIV_MASK, i << WM8983_MCLKDIV_SHIFT);
/* select the appropriate bclk divider */
tmp = (wm8983->sysclk / fs_ratios[i].div) * 10;
for (i = 0; i < ARRAY_SIZE(bclk_divs); ++i) {
if (wm8983->bclk == tmp / bclk_divs[i])
break;
}
if (i == ARRAY_SIZE(bclk_divs)) {
dev_err(dai->dev, "No matching BCLK divider found\n");
return -EINVAL;
}
dev_dbg(dai->dev, "BCLK div = %d\n", i);
snd_soc_component_update_bits(component, WM8983_CLOCK_GEN_CONTROL,
WM8983_BCLKDIV_MASK, i << WM8983_BCLKDIV_SHIFT);
return 0;
}
struct pll_div {
u32 div2:1;
u32 n:4;
u32 k:24;
};
#define FIXED_PLL_SIZE ((1ULL << 24) * 10)
static int pll_factors(struct pll_div *pll_div, unsigned int target,
unsigned int source)
{
u64 Kpart;
unsigned long int K, Ndiv, Nmod;
pll_div->div2 = 0;
Ndiv = target / source;
if (Ndiv < 6) {
source >>= 1;
pll_div->div2 = 1;
Ndiv = target / source;
}
if (Ndiv < 6 || Ndiv > 12) {
printk(KERN_ERR "%s: WM8983 N value is not within"
" the recommended range: %lu\n", __func__, Ndiv);
return -EINVAL;
}
pll_div->n = Ndiv;
Nmod = target % source;
Kpart = FIXED_PLL_SIZE * (u64)Nmod;
do_div(Kpart, source);
K = Kpart & 0xffffffff;
if ((K % 10) >= 5)
K += 5;
K /= 10;
pll_div->k = K;
return 0;
}
static int wm8983_set_pll(struct snd_soc_dai *dai, int pll_id,
int source, unsigned int freq_in,
unsigned int freq_out)
{
int ret;
struct snd_soc_component *component;
struct pll_div pll_div;
component = dai->component;
if (!freq_in || !freq_out) {
/* disable the PLL */
snd_soc_component_update_bits(component, WM8983_POWER_MANAGEMENT_1,
WM8983_PLLEN_MASK, 0);
return 0;
} else {
ret = pll_factors(&pll_div, freq_out * 4 * 2, freq_in);
if (ret)
return ret;
/* disable the PLL before re-programming it */
snd_soc_component_update_bits(component, WM8983_POWER_MANAGEMENT_1,
WM8983_PLLEN_MASK, 0);
/* set PLLN and PRESCALE */
snd_soc_component_write(component, WM8983_PLL_N,
(pll_div.div2 << WM8983_PLL_PRESCALE_SHIFT)
| pll_div.n);
/* set PLLK */
snd_soc_component_write(component, WM8983_PLL_K_3, pll_div.k & 0x1ff);
snd_soc_component_write(component, WM8983_PLL_K_2, (pll_div.k >> 9) & 0x1ff);
snd_soc_component_write(component, WM8983_PLL_K_1, (pll_div.k >> 18));
/* enable the PLL */
snd_soc_component_update_bits(component, WM8983_POWER_MANAGEMENT_1,
WM8983_PLLEN_MASK, WM8983_PLLEN);
}
return 0;
}
static int wm8983_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct wm8983_priv *wm8983 = snd_soc_component_get_drvdata(component);
switch (clk_id) {
case WM8983_CLKSRC_MCLK:
snd_soc_component_update_bits(component, WM8983_CLOCK_GEN_CONTROL,
WM8983_CLKSEL_MASK, 0);
break;
case WM8983_CLKSRC_PLL:
snd_soc_component_update_bits(component, WM8983_CLOCK_GEN_CONTROL,
WM8983_CLKSEL_MASK, WM8983_CLKSEL);
break;
default:
dev_err(dai->dev, "Unknown clock source: %d\n", clk_id);
return -EINVAL;
}
wm8983->sysclk = freq;
return 0;
}
static int wm8983_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct wm8983_priv *wm8983 = snd_soc_component_get_drvdata(component);
int ret;
switch (level) {
case SND_SOC_BIAS_ON:
case SND_SOC_BIAS_PREPARE:
/* VMID at 100k */
snd_soc_component_update_bits(component, WM8983_POWER_MANAGEMENT_1,
WM8983_VMIDSEL_MASK,
1 << WM8983_VMIDSEL_SHIFT);
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
ret = regcache_sync(wm8983->regmap);
if (ret < 0) {
dev_err(component->dev, "Failed to sync cache: %d\n", ret);
return ret;
}
/* enable anti-pop features */
snd_soc_component_update_bits(component, WM8983_OUT4_TO_ADC,
WM8983_POBCTRL_MASK | WM8983_DELEN_MASK,
WM8983_POBCTRL | WM8983_DELEN);
/* enable thermal shutdown */
snd_soc_component_update_bits(component, WM8983_OUTPUT_CTRL,
WM8983_TSDEN_MASK, WM8983_TSDEN);
/* enable BIASEN */
snd_soc_component_update_bits(component, WM8983_POWER_MANAGEMENT_1,
WM8983_BIASEN_MASK, WM8983_BIASEN);
/* VMID at 100k */
snd_soc_component_update_bits(component, WM8983_POWER_MANAGEMENT_1,
WM8983_VMIDSEL_MASK,
1 << WM8983_VMIDSEL_SHIFT);
msleep(250);
/* disable anti-pop features */
snd_soc_component_update_bits(component, WM8983_OUT4_TO_ADC,
WM8983_POBCTRL_MASK |
WM8983_DELEN_MASK, 0);
}
/* VMID at 500k */
snd_soc_component_update_bits(component, WM8983_POWER_MANAGEMENT_1,
WM8983_VMIDSEL_MASK,
2 << WM8983_VMIDSEL_SHIFT);
break;
case SND_SOC_BIAS_OFF:
/* disable thermal shutdown */
snd_soc_component_update_bits(component, WM8983_OUTPUT_CTRL,
WM8983_TSDEN_MASK, 0);
/* disable VMIDSEL and BIASEN */
snd_soc_component_update_bits(component, WM8983_POWER_MANAGEMENT_1,
WM8983_VMIDSEL_MASK | WM8983_BIASEN_MASK,
0);
/* wait for VMID to discharge */
msleep(100);
snd_soc_component_write(component, WM8983_POWER_MANAGEMENT_1, 0);
snd_soc_component_write(component, WM8983_POWER_MANAGEMENT_2, 0);
snd_soc_component_write(component, WM8983_POWER_MANAGEMENT_3, 0);
break;
}
return 0;
}
static int wm8983_probe(struct snd_soc_component *component)
{
int ret;
int i;
ret = snd_soc_component_write(component, WM8983_SOFTWARE_RESET, 0);
if (ret < 0) {
dev_err(component->dev, "Failed to issue reset: %d\n", ret);
return ret;
}
/* set the vol/gain update bits */
for (i = 0; i < ARRAY_SIZE(vol_update_regs); ++i)
snd_soc_component_update_bits(component, vol_update_regs[i],
0x100, 0x100);
/* mute all outputs and set PGAs to minimum gain */
for (i = WM8983_LOUT1_HP_VOLUME_CTRL;
i <= WM8983_OUT4_MONO_MIX_CTRL; ++i)
snd_soc_component_update_bits(component, i, 0x40, 0x40);
/* enable soft mute */
snd_soc_component_update_bits(component, WM8983_DAC_CONTROL,
WM8983_SOFTMUTE_MASK,
WM8983_SOFTMUTE);
/* enable BIASCUT */
snd_soc_component_update_bits(component, WM8983_BIAS_CTRL,
WM8983_BIASCUT, WM8983_BIASCUT);
return 0;
}
static const struct snd_soc_dai_ops wm8983_dai_ops = {
.mute_stream = wm8983_dac_mute,
.hw_params = wm8983_hw_params,
.set_fmt = wm8983_set_fmt,
.set_sysclk = wm8983_set_sysclk,
.set_pll = wm8983_set_pll,
.no_capture_mute = 1,
};
#define WM8983_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver wm8983_dai = {
.name = "wm8983-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = WM8983_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = WM8983_FORMATS,
},
.ops = &wm8983_dai_ops,
.symmetric_rate = 1
};
static const struct snd_soc_component_driver soc_component_dev_wm8983 = {
.probe = wm8983_probe,
.set_bias_level = wm8983_set_bias_level,
.controls = wm8983_snd_controls,
.num_controls = ARRAY_SIZE(wm8983_snd_controls),
.dapm_widgets = wm8983_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8983_dapm_widgets),
.dapm_routes = wm8983_audio_map,
.num_dapm_routes = ARRAY_SIZE(wm8983_audio_map),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config wm8983_regmap = {
.reg_bits = 7,
.val_bits = 9,
.reg_defaults = wm8983_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8983_defaults),
.cache_type = REGCACHE_MAPLE,
.max_register = WM8983_MAX_REGISTER,
.writeable_reg = wm8983_writeable,
};
#if defined(CONFIG_SPI_MASTER)
static int wm8983_spi_probe(struct spi_device *spi)
{
struct wm8983_priv *wm8983;
int ret;
wm8983 = devm_kzalloc(&spi->dev, sizeof *wm8983, GFP_KERNEL);
if (!wm8983)
return -ENOMEM;
wm8983->regmap = devm_regmap_init_spi(spi, &wm8983_regmap);
if (IS_ERR(wm8983->regmap)) {
ret = PTR_ERR(wm8983->regmap);
dev_err(&spi->dev, "Failed to init regmap: %d\n", ret);
return ret;
}
spi_set_drvdata(spi, wm8983);
ret = devm_snd_soc_register_component(&spi->dev,
&soc_component_dev_wm8983, &wm8983_dai, 1);
return ret;
}
static struct spi_driver wm8983_spi_driver = {
.driver = {
.name = "wm8983",
},
.probe = wm8983_spi_probe,
};
#endif
#if IS_ENABLED(CONFIG_I2C)
static int wm8983_i2c_probe(struct i2c_client *i2c)
{
struct wm8983_priv *wm8983;
int ret;
wm8983 = devm_kzalloc(&i2c->dev, sizeof *wm8983, GFP_KERNEL);
if (!wm8983)
return -ENOMEM;
wm8983->regmap = devm_regmap_init_i2c(i2c, &wm8983_regmap);
if (IS_ERR(wm8983->regmap)) {
ret = PTR_ERR(wm8983->regmap);
dev_err(&i2c->dev, "Failed to init regmap: %d\n", ret);
return ret;
}
i2c_set_clientdata(i2c, wm8983);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_wm8983, &wm8983_dai, 1);
return ret;
}
static const struct i2c_device_id wm8983_i2c_id[] = {
{ "wm8983", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8983_i2c_id);
static struct i2c_driver wm8983_i2c_driver = {
.driver = {
.name = "wm8983",
},
.probe = wm8983_i2c_probe,
.id_table = wm8983_i2c_id
};
#endif
static int __init wm8983_modinit(void)
{
int ret = 0;
#if IS_ENABLED(CONFIG_I2C)
ret = i2c_add_driver(&wm8983_i2c_driver);
if (ret) {
printk(KERN_ERR "Failed to register wm8983 I2C driver: %d\n",
ret);
}
#endif
#if defined(CONFIG_SPI_MASTER)
ret = spi_register_driver(&wm8983_spi_driver);
if (ret != 0) {
printk(KERN_ERR "Failed to register wm8983 SPI driver: %d\n",
ret);
}
#endif
return ret;
}
module_init(wm8983_modinit);
static void __exit wm8983_exit(void)
{
#if IS_ENABLED(CONFIG_I2C)
i2c_del_driver(&wm8983_i2c_driver);
#endif
#if defined(CONFIG_SPI_MASTER)
spi_unregister_driver(&wm8983_spi_driver);
#endif
}
module_exit(wm8983_exit);
MODULE_DESCRIPTION("ASoC WM8983 driver");
MODULE_AUTHOR("Dimitris Papastamos <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8983.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
*/
#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/gpio/consumer.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_gpio.h>
#include <linux/pm_runtime.h>
#include <linux/printk.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <linux/soundwire/sdw.h>
#include <linux/soundwire/sdw_registers.h>
#include <linux/soundwire/sdw_type.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc-dapm.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#define WSA883X_BASE 0x3000
#define WSA883X_ANA_BG_TSADC_BASE (WSA883X_BASE + 0x00000001)
#define WSA883X_REF_CTRL (WSA883X_ANA_BG_TSADC_BASE + 0x0000)
#define WSA883X_TEST_CTL_0 (WSA883X_ANA_BG_TSADC_BASE + 0x0001)
#define WSA883X_BIAS_0 (WSA883X_ANA_BG_TSADC_BASE + 0x0002)
#define WSA883X_OP_CTL (WSA883X_ANA_BG_TSADC_BASE + 0x0003)
#define WSA883X_IREF_CTL (WSA883X_ANA_BG_TSADC_BASE + 0x0004)
#define WSA883X_ISENS_CTL (WSA883X_ANA_BG_TSADC_BASE + 0x0005)
#define WSA883X_CLK_CTL (WSA883X_ANA_BG_TSADC_BASE + 0x0006)
#define WSA883X_TEST_CTL_1 (WSA883X_ANA_BG_TSADC_BASE + 0x0007)
#define WSA883X_BIAS_1 (WSA883X_ANA_BG_TSADC_BASE + 0x0008)
#define WSA883X_ADC_CTL (WSA883X_ANA_BG_TSADC_BASE + 0x0009)
#define WSA883X_DOUT_MSB (WSA883X_ANA_BG_TSADC_BASE + 0x000A)
#define WSA883X_DOUT_LSB (WSA883X_ANA_BG_TSADC_BASE + 0x000B)
#define WSA883X_VBAT_SNS (WSA883X_ANA_BG_TSADC_BASE + 0x000C)
#define WSA883X_ITRIM_CODE (WSA883X_ANA_BG_TSADC_BASE + 0x000D)
#define WSA883X_ANA_IVSENSE_BASE (WSA883X_BASE + 0x0000000F)
#define WSA883X_EN (WSA883X_ANA_IVSENSE_BASE + 0x0000)
#define WSA883X_OVERRIDE1 (WSA883X_ANA_IVSENSE_BASE + 0x0001)
#define WSA883X_OVERRIDE2 (WSA883X_ANA_IVSENSE_BASE + 0x0002)
#define WSA883X_VSENSE1 (WSA883X_ANA_IVSENSE_BASE + 0x0003)
#define WSA883X_ISENSE1 (WSA883X_ANA_IVSENSE_BASE + 0x0004)
#define WSA883X_ISENSE2 (WSA883X_ANA_IVSENSE_BASE + 0x0005)
#define WSA883X_ISENSE_CAL (WSA883X_ANA_IVSENSE_BASE + 0x0006)
#define WSA883X_MISC (WSA883X_ANA_IVSENSE_BASE + 0x0007)
#define WSA883X_ADC_0 (WSA883X_ANA_IVSENSE_BASE + 0x0008)
#define WSA883X_ADC_1 (WSA883X_ANA_IVSENSE_BASE + 0x0009)
#define WSA883X_ADC_2 (WSA883X_ANA_IVSENSE_BASE + 0x000A)
#define WSA883X_ADC_3 (WSA883X_ANA_IVSENSE_BASE + 0x000B)
#define WSA883X_ADC_4 (WSA883X_ANA_IVSENSE_BASE + 0x000C)
#define WSA883X_ADC_5 (WSA883X_ANA_IVSENSE_BASE + 0x000D)
#define WSA883X_ADC_6 (WSA883X_ANA_IVSENSE_BASE + 0x000E)
#define WSA883X_ADC_7 (WSA883X_ANA_IVSENSE_BASE + 0x000F)
#define WSA883X_STATUS (WSA883X_ANA_IVSENSE_BASE + 0x0010)
#define WSA883X_ANA_SPK_TOP_BASE (WSA883X_BASE + 0x00000025)
#define WSA883X_DAC_CTRL_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0000)
#define WSA883X_DAC_EN_DEBUG_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0001)
#define WSA883X_DAC_OPAMP_BIAS1_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0002)
#define WSA883X_DAC_OPAMP_BIAS2_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0003)
#define WSA883X_DAC_VCM_CTRL_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0004)
#define WSA883X_DAC_VOLTAGE_CTRL_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0005)
#define WSA883X_ATEST1_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0006)
#define WSA883X_ATEST2_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0007)
#define WSA883X_SPKR_TOP_BIAS_REG1 (WSA883X_ANA_SPK_TOP_BASE + 0x0008)
#define WSA883X_SPKR_TOP_BIAS_REG2 (WSA883X_ANA_SPK_TOP_BASE + 0x0009)
#define WSA883X_SPKR_TOP_BIAS_REG3 (WSA883X_ANA_SPK_TOP_BASE + 0x000A)
#define WSA883X_SPKR_TOP_BIAS_REG4 (WSA883X_ANA_SPK_TOP_BASE + 0x000B)
#define WSA883X_SPKR_CLIP_DET_REG (WSA883X_ANA_SPK_TOP_BASE + 0x000C)
#define WSA883X_SPKR_DRV_LF_BLK_EN (WSA883X_ANA_SPK_TOP_BASE + 0x000D)
#define WSA883X_SPKR_DRV_LF_EN (WSA883X_ANA_SPK_TOP_BASE + 0x000E)
#define WSA883X_SPKR_DRV_LF_MASK_DCC_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x000F)
#define WSA883X_SPKR_DRV_LF_MISC_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0010)
#define WSA883X_SPKR_DRV_LF_REG_GAIN (WSA883X_ANA_SPK_TOP_BASE + 0x0011)
#define WSA883X_SPKR_DRV_OS_CAL_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0012)
#define WSA883X_SPKR_DRV_OS_CAL_CTL1 (WSA883X_ANA_SPK_TOP_BASE + 0x0013)
#define WSA883X_SPKR_PWM_CLK_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0014)
#define WSA883X_SPKR_PWM_FREQ_SEL_MASK BIT(3)
#define WSA883X_SPKR_PWM_FREQ_F300KHZ 0
#define WSA883X_SPKR_PWM_FREQ_F600KHZ 1
#define WSA883X_SPKR_PDRV_HS_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0015)
#define WSA883X_SPKR_PDRV_LS_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0016)
#define WSA883X_SPKR_PWRSTG_DBG (WSA883X_ANA_SPK_TOP_BASE + 0x0017)
#define WSA883X_SPKR_OCP_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0018)
#define WSA883X_SPKR_BBM_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0019)
#define WSA883X_PA_STATUS0 (WSA883X_ANA_SPK_TOP_BASE + 0x001A)
#define WSA883X_PA_STATUS1 (WSA883X_ANA_SPK_TOP_BASE + 0x001B)
#define WSA883X_PA_STATUS2 (WSA883X_ANA_SPK_TOP_BASE + 0x001C)
#define WSA883X_ANA_BOOST_BASE (WSA883X_BASE + 0x00000043)
#define WSA883X_EN_CTRL (WSA883X_ANA_BOOST_BASE + 0x0000)
#define WSA883X_CURRENT_LIMIT (WSA883X_ANA_BOOST_BASE + 0x0001)
#define WSA883X_IBIAS1 (WSA883X_ANA_BOOST_BASE + 0x0002)
#define WSA883X_IBIAS2 (WSA883X_ANA_BOOST_BASE + 0x0003)
#define WSA883X_IBIAS3 (WSA883X_ANA_BOOST_BASE + 0x0004)
#define WSA883X_LDO_PROG (WSA883X_ANA_BOOST_BASE + 0x0005)
#define WSA883X_STABILITY_CTRL1 (WSA883X_ANA_BOOST_BASE + 0x0006)
#define WSA883X_STABILITY_CTRL2 (WSA883X_ANA_BOOST_BASE + 0x0007)
#define WSA883X_PWRSTAGE_CTRL1 (WSA883X_ANA_BOOST_BASE + 0x0008)
#define WSA883X_PWRSTAGE_CTRL2 (WSA883X_ANA_BOOST_BASE + 0x0009)
#define WSA883X_BYPASS_1 (WSA883X_ANA_BOOST_BASE + 0x000A)
#define WSA883X_BYPASS_2 (WSA883X_ANA_BOOST_BASE + 0x000B)
#define WSA883X_ZX_CTRL_1 (WSA883X_ANA_BOOST_BASE + 0x000C)
#define WSA883X_ZX_CTRL_2 (WSA883X_ANA_BOOST_BASE + 0x000D)
#define WSA883X_MISC1 (WSA883X_ANA_BOOST_BASE + 0x000E)
#define WSA883X_MISC2 (WSA883X_ANA_BOOST_BASE + 0x000F)
#define WSA883X_GMAMP_SUP1 (WSA883X_ANA_BOOST_BASE + 0x0010)
#define WSA883X_PWRSTAGE_CTRL3 (WSA883X_ANA_BOOST_BASE + 0x0011)
#define WSA883X_PWRSTAGE_CTRL4 (WSA883X_ANA_BOOST_BASE + 0x0012)
#define WSA883X_TEST1 (WSA883X_ANA_BOOST_BASE + 0x0013)
#define WSA883X_SPARE1 (WSA883X_ANA_BOOST_BASE + 0x0014)
#define WSA883X_SPARE2 (WSA883X_ANA_BOOST_BASE + 0x0015)
#define WSA883X_ANA_PON_LDOL_BASE (WSA883X_BASE + 0x00000059)
#define WSA883X_PON_CTL_0 (WSA883X_ANA_PON_LDOL_BASE + 0x0000)
#define WSA883X_PON_CLT_1 (WSA883X_ANA_PON_LDOL_BASE + 0x0001)
#define WSA883X_PON_CTL_2 (WSA883X_ANA_PON_LDOL_BASE + 0x0002)
#define WSA883X_PON_CTL_3 (WSA883X_ANA_PON_LDOL_BASE + 0x0003)
#define WSA883X_CKWD_CTL_0 (WSA883X_ANA_PON_LDOL_BASE + 0x0004)
#define WSA883X_CKWD_CTL_1 (WSA883X_ANA_PON_LDOL_BASE + 0x0005)
#define WSA883X_CKWD_CTL_2 (WSA883X_ANA_PON_LDOL_BASE + 0x0006)
#define WSA883X_CKSK_CTL_0 (WSA883X_ANA_PON_LDOL_BASE + 0x0007)
#define WSA883X_PADSW_CTL_0 (WSA883X_ANA_PON_LDOL_BASE + 0x0008)
#define WSA883X_TEST_0 (WSA883X_ANA_PON_LDOL_BASE + 0x0009)
#define WSA883X_TEST_1 (WSA883X_ANA_PON_LDOL_BASE + 0x000A)
#define WSA883X_STATUS_0 (WSA883X_ANA_PON_LDOL_BASE + 0x000B)
#define WSA883X_STATUS_1 (WSA883X_ANA_PON_LDOL_BASE + 0x000C)
#define WSA883X_DIG_CTRL_BASE (WSA883X_BASE + 0x00000400)
#define WSA883X_CHIP_ID0 (WSA883X_DIG_CTRL_BASE + 0x0001)
#define WSA883X_CHIP_ID1 (WSA883X_DIG_CTRL_BASE + 0x0002)
#define WSA883X_CHIP_ID2 (WSA883X_DIG_CTRL_BASE + 0x0003)
#define WSA883X_CHIP_ID3 (WSA883X_DIG_CTRL_BASE + 0x0004)
#define WSA883X_BUS_ID (WSA883X_DIG_CTRL_BASE + 0x0005)
#define WSA883X_CDC_RST_CTL (WSA883X_DIG_CTRL_BASE + 0x0006)
#define WSA883X_TOP_CLK_CFG (WSA883X_DIG_CTRL_BASE + 0x0007)
#define WSA883X_CDC_PATH_MODE (WSA883X_DIG_CTRL_BASE + 0x0008)
#define WSA883X_RXD_MODE_MASK BIT(1)
#define WSA883X_RXD_MODE_NORMAL 0
#define WSA883X_RXD_MODE_HIFI 1
#define WSA883X_CDC_CLK_CTL (WSA883X_DIG_CTRL_BASE + 0x0009)
#define WSA883X_SWR_RESET_EN (WSA883X_DIG_CTRL_BASE + 0x000A)
#define WSA883X_RESET_CTL (WSA883X_DIG_CTRL_BASE + 0x000B)
#define WSA883X_PA_FSM_CTL (WSA883X_DIG_CTRL_BASE + 0x0010)
#define WSA883X_GLOBAL_PA_EN_MASK BIT(0)
#define WSA883X_GLOBAL_PA_ENABLE 1
#define WSA883X_PA_FSM_TIMER0 (WSA883X_DIG_CTRL_BASE + 0x0011)
#define WSA883X_PA_FSM_TIMER1 (WSA883X_DIG_CTRL_BASE + 0x0012)
#define WSA883X_PA_FSM_STA (WSA883X_DIG_CTRL_BASE + 0x0013)
#define WSA883X_PA_FSM_ERR_COND (WSA883X_DIG_CTRL_BASE + 0x0014)
#define WSA883X_PA_FSM_MSK (WSA883X_DIG_CTRL_BASE + 0x0015)
#define WSA883X_PA_FSM_BYP (WSA883X_DIG_CTRL_BASE + 0x0016)
#define WSA883X_PA_FSM_DBG (WSA883X_DIG_CTRL_BASE + 0x0017)
#define WSA883X_TADC_VALUE_CTL (WSA883X_DIG_CTRL_BASE + 0x0020)
#define WSA883X_TEMP_DETECT_CTL (WSA883X_DIG_CTRL_BASE + 0x0021)
#define WSA883X_TEMP_MSB (WSA883X_DIG_CTRL_BASE + 0x0022)
#define WSA883X_TEMP_LSB (WSA883X_DIG_CTRL_BASE + 0x0023)
#define WSA883X_TEMP_CONFIG0 (WSA883X_DIG_CTRL_BASE + 0x0024)
#define WSA883X_TEMP_CONFIG1 (WSA883X_DIG_CTRL_BASE + 0x0025)
#define WSA883X_VBAT_ADC_FLT_CTL (WSA883X_DIG_CTRL_BASE + 0x0026)
#define WSA883X_VBAT_ADC_FLT_EN_MASK BIT(0)
#define WSA883X_VBAT_ADC_COEF_SEL_MASK GENMASK(3, 1)
#define WSA883X_VBAT_ADC_COEF_F_1DIV2 0x0
#define WSA883X_VBAT_ADC_COEF_F_1DIV16 0x3
#define WSA883X_VBAT_DIN_MSB (WSA883X_DIG_CTRL_BASE + 0x0027)
#define WSA883X_VBAT_DIN_LSB (WSA883X_DIG_CTRL_BASE + 0x0028)
#define WSA883X_VBAT_DOUT (WSA883X_DIG_CTRL_BASE + 0x0029)
#define WSA883X_SDM_PDM9_LSB (WSA883X_DIG_CTRL_BASE + 0x002A)
#define WSA883X_SDM_PDM9_MSB (WSA883X_DIG_CTRL_BASE + 0x002B)
#define WSA883X_CDC_RX_CTL (WSA883X_DIG_CTRL_BASE + 0x0030)
#define WSA883X_CDC_SPK_DSM_A1_0 (WSA883X_DIG_CTRL_BASE + 0x0031)
#define WSA883X_CDC_SPK_DSM_A1_1 (WSA883X_DIG_CTRL_BASE + 0x0032)
#define WSA883X_CDC_SPK_DSM_A2_0 (WSA883X_DIG_CTRL_BASE + 0x0033)
#define WSA883X_CDC_SPK_DSM_A2_1 (WSA883X_DIG_CTRL_BASE + 0x0034)
#define WSA883X_CDC_SPK_DSM_A3_0 (WSA883X_DIG_CTRL_BASE + 0x0035)
#define WSA883X_CDC_SPK_DSM_A3_1 (WSA883X_DIG_CTRL_BASE + 0x0036)
#define WSA883X_CDC_SPK_DSM_A4_0 (WSA883X_DIG_CTRL_BASE + 0x0037)
#define WSA883X_CDC_SPK_DSM_A4_1 (WSA883X_DIG_CTRL_BASE + 0x0038)
#define WSA883X_CDC_SPK_DSM_A5_0 (WSA883X_DIG_CTRL_BASE + 0x0039)
#define WSA883X_CDC_SPK_DSM_A5_1 (WSA883X_DIG_CTRL_BASE + 0x003A)
#define WSA883X_CDC_SPK_DSM_A6_0 (WSA883X_DIG_CTRL_BASE + 0x003B)
#define WSA883X_CDC_SPK_DSM_A7_0 (WSA883X_DIG_CTRL_BASE + 0x003C)
#define WSA883X_CDC_SPK_DSM_C_0 (WSA883X_DIG_CTRL_BASE + 0x003D)
#define WSA883X_CDC_SPK_DSM_C_1 (WSA883X_DIG_CTRL_BASE + 0x003E)
#define WSA883X_CDC_SPK_DSM_C_2 (WSA883X_DIG_CTRL_BASE + 0x003F)
#define WSA883X_CDC_SPK_DSM_C_3 (WSA883X_DIG_CTRL_BASE + 0x0040)
#define WSA883X_CDC_SPK_DSM_R1 (WSA883X_DIG_CTRL_BASE + 0x0041)
#define WSA883X_CDC_SPK_DSM_R2 (WSA883X_DIG_CTRL_BASE + 0x0042)
#define WSA883X_CDC_SPK_DSM_R3 (WSA883X_DIG_CTRL_BASE + 0x0043)
#define WSA883X_CDC_SPK_DSM_R4 (WSA883X_DIG_CTRL_BASE + 0x0044)
#define WSA883X_CDC_SPK_DSM_R5 (WSA883X_DIG_CTRL_BASE + 0x0045)
#define WSA883X_CDC_SPK_DSM_R6 (WSA883X_DIG_CTRL_BASE + 0x0046)
#define WSA883X_CDC_SPK_DSM_R7 (WSA883X_DIG_CTRL_BASE + 0x0047)
#define WSA883X_CDC_SPK_GAIN_PDM_0 (WSA883X_DIG_CTRL_BASE + 0x0048)
#define WSA883X_CDC_SPK_GAIN_PDM_1 (WSA883X_DIG_CTRL_BASE + 0x0049)
#define WSA883X_CDC_SPK_GAIN_PDM_2 (WSA883X_DIG_CTRL_BASE + 0x004A)
#define WSA883X_PDM_WD_CTL (WSA883X_DIG_CTRL_BASE + 0x004B)
#define WSA883X_PDM_EN_MASK BIT(0)
#define WSA883X_PDM_ENABLE BIT(0)
#define WSA883X_DEM_BYPASS_DATA0 (WSA883X_DIG_CTRL_BASE + 0x004C)
#define WSA883X_DEM_BYPASS_DATA1 (WSA883X_DIG_CTRL_BASE + 0x004D)
#define WSA883X_DEM_BYPASS_DATA2 (WSA883X_DIG_CTRL_BASE + 0x004E)
#define WSA883X_DEM_BYPASS_DATA3 (WSA883X_DIG_CTRL_BASE + 0x004F)
#define WSA883X_WAVG_CTL (WSA883X_DIG_CTRL_BASE + 0x0050)
#define WSA883X_WAVG_LRA_PER_0 (WSA883X_DIG_CTRL_BASE + 0x0051)
#define WSA883X_WAVG_LRA_PER_1 (WSA883X_DIG_CTRL_BASE + 0x0052)
#define WSA883X_WAVG_DELTA_THETA_0 (WSA883X_DIG_CTRL_BASE + 0x0053)
#define WSA883X_WAVG_DELTA_THETA_1 (WSA883X_DIG_CTRL_BASE + 0x0054)
#define WSA883X_WAVG_DIRECT_AMP_0 (WSA883X_DIG_CTRL_BASE + 0x0055)
#define WSA883X_WAVG_DIRECT_AMP_1 (WSA883X_DIG_CTRL_BASE + 0x0056)
#define WSA883X_WAVG_PTRN_AMP0_0 (WSA883X_DIG_CTRL_BASE + 0x0057)
#define WSA883X_WAVG_PTRN_AMP0_1 (WSA883X_DIG_CTRL_BASE + 0x0058)
#define WSA883X_WAVG_PTRN_AMP1_0 (WSA883X_DIG_CTRL_BASE + 0x0059)
#define WSA883X_WAVG_PTRN_AMP1_1 (WSA883X_DIG_CTRL_BASE + 0x005A)
#define WSA883X_WAVG_PTRN_AMP2_0 (WSA883X_DIG_CTRL_BASE + 0x005B)
#define WSA883X_WAVG_PTRN_AMP2_1 (WSA883X_DIG_CTRL_BASE + 0x005C)
#define WSA883X_WAVG_PTRN_AMP3_0 (WSA883X_DIG_CTRL_BASE + 0x005D)
#define WSA883X_WAVG_PTRN_AMP3_1 (WSA883X_DIG_CTRL_BASE + 0x005E)
#define WSA883X_WAVG_PTRN_AMP4_0 (WSA883X_DIG_CTRL_BASE + 0x005F)
#define WSA883X_WAVG_PTRN_AMP4_1 (WSA883X_DIG_CTRL_BASE + 0x0060)
#define WSA883X_WAVG_PTRN_AMP5_0 (WSA883X_DIG_CTRL_BASE + 0x0061)
#define WSA883X_WAVG_PTRN_AMP5_1 (WSA883X_DIG_CTRL_BASE + 0x0062)
#define WSA883X_WAVG_PTRN_AMP6_0 (WSA883X_DIG_CTRL_BASE + 0x0063)
#define WSA883X_WAVG_PTRN_AMP6_1 (WSA883X_DIG_CTRL_BASE + 0x0064)
#define WSA883X_WAVG_PTRN_AMP7_0 (WSA883X_DIG_CTRL_BASE + 0x0065)
#define WSA883X_WAVG_PTRN_AMP7_1 (WSA883X_DIG_CTRL_BASE + 0x0066)
#define WSA883X_WAVG_PER_0_1 (WSA883X_DIG_CTRL_BASE + 0x0067)
#define WSA883X_WAVG_PER_2_3 (WSA883X_DIG_CTRL_BASE + 0x0068)
#define WSA883X_WAVG_PER_4_5 (WSA883X_DIG_CTRL_BASE + 0x0069)
#define WSA883X_WAVG_PER_6_7 (WSA883X_DIG_CTRL_BASE + 0x006A)
#define WSA883X_WAVG_STA (WSA883X_DIG_CTRL_BASE + 0x006B)
#define WSA883X_DRE_CTL_0 (WSA883X_DIG_CTRL_BASE + 0x006C)
#define WSA883X_DRE_OFFSET_MASK GENMASK(2, 0)
#define WSA883X_DRE_PROG_DELAY_MASK GENMASK(7, 4)
#define WSA883X_DRE_CTL_1 (WSA883X_DIG_CTRL_BASE + 0x006D)
#define WSA883X_DRE_GAIN_EN_MASK BIT(0)
#define WSA883X_DRE_GAIN_FROM_CSR 1
#define WSA883X_DRE_IDLE_DET_CTL (WSA883X_DIG_CTRL_BASE + 0x006E)
#define WSA883X_CLSH_CTL_0 (WSA883X_DIG_CTRL_BASE + 0x0070)
#define WSA883X_CLSH_CTL_1 (WSA883X_DIG_CTRL_BASE + 0x0071)
#define WSA883X_CLSH_V_HD_PA (WSA883X_DIG_CTRL_BASE + 0x0072)
#define WSA883X_CLSH_V_PA_MIN (WSA883X_DIG_CTRL_BASE + 0x0073)
#define WSA883X_CLSH_OVRD_VAL (WSA883X_DIG_CTRL_BASE + 0x0074)
#define WSA883X_CLSH_HARD_MAX (WSA883X_DIG_CTRL_BASE + 0x0075)
#define WSA883X_CLSH_SOFT_MAX (WSA883X_DIG_CTRL_BASE + 0x0076)
#define WSA883X_CLSH_SIG_DP (WSA883X_DIG_CTRL_BASE + 0x0077)
#define WSA883X_TAGC_CTL (WSA883X_DIG_CTRL_BASE + 0x0078)
#define WSA883X_TAGC_TIME (WSA883X_DIG_CTRL_BASE + 0x0079)
#define WSA883X_TAGC_E2E_GAIN (WSA883X_DIG_CTRL_BASE + 0x007A)
#define WSA883X_TAGC_FORCE_VAL (WSA883X_DIG_CTRL_BASE + 0x007B)
#define WSA883X_VAGC_CTL (WSA883X_DIG_CTRL_BASE + 0x007C)
#define WSA883X_VAGC_TIME (WSA883X_DIG_CTRL_BASE + 0x007D)
#define WSA883X_VAGC_ATTN_LVL_1_2 (WSA883X_DIG_CTRL_BASE + 0x007E)
#define WSA883X_VAGC_ATTN_LVL_3 (WSA883X_DIG_CTRL_BASE + 0x007F)
#define WSA883X_INTR_MODE (WSA883X_DIG_CTRL_BASE + 0x0080)
#define WSA883X_INTR_MASK0 (WSA883X_DIG_CTRL_BASE + 0x0081)
#define WSA883X_INTR_MASK1 (WSA883X_DIG_CTRL_BASE + 0x0082)
#define WSA883X_INTR_STATUS0 (WSA883X_DIG_CTRL_BASE + 0x0083)
#define WSA883X_INTR_STATUS1 (WSA883X_DIG_CTRL_BASE + 0x0084)
#define WSA883X_INTR_CLEAR0 (WSA883X_DIG_CTRL_BASE + 0x0085)
#define WSA883X_INTR_CLEAR1 (WSA883X_DIG_CTRL_BASE + 0x0086)
#define WSA883X_INTR_LEVEL0 (WSA883X_DIG_CTRL_BASE + 0x0087)
#define WSA883X_INTR_LEVEL1 (WSA883X_DIG_CTRL_BASE + 0x0088)
#define WSA883X_INTR_SET0 (WSA883X_DIG_CTRL_BASE + 0x0089)
#define WSA883X_INTR_SET1 (WSA883X_DIG_CTRL_BASE + 0x008A)
#define WSA883X_INTR_TEST0 (WSA883X_DIG_CTRL_BASE + 0x008B)
#define WSA883X_INTR_TEST1 (WSA883X_DIG_CTRL_BASE + 0x008C)
#define WSA883X_OTP_CTRL0 (WSA883X_DIG_CTRL_BASE + 0x0090)
#define WSA883X_OTP_CTRL1 (WSA883X_DIG_CTRL_BASE + 0x0091)
#define WSA883X_HDRIVE_CTL_GROUP1 (WSA883X_DIG_CTRL_BASE + 0x0092)
#define WSA883X_PIN_CTL (WSA883X_DIG_CTRL_BASE + 0x0093)
#define WSA883X_PIN_CTL_OE (WSA883X_DIG_CTRL_BASE + 0x0094)
#define WSA883X_PIN_WDATA_IOPAD (WSA883X_DIG_CTRL_BASE + 0x0095)
#define WSA883X_PIN_STATUS (WSA883X_DIG_CTRL_BASE + 0x0096)
#define WSA883X_I2C_SLAVE_CTL (WSA883X_DIG_CTRL_BASE + 0x0097)
#define WSA883X_PDM_TEST_MODE (WSA883X_DIG_CTRL_BASE + 0x00A0)
#define WSA883X_ATE_TEST_MODE (WSA883X_DIG_CTRL_BASE + 0x00A1)
#define WSA883X_DIG_DEBUG_MODE (WSA883X_DIG_CTRL_BASE + 0x00A3)
#define WSA883X_DIG_DEBUG_SEL (WSA883X_DIG_CTRL_BASE + 0x00A4)
#define WSA883X_DIG_DEBUG_EN (WSA883X_DIG_CTRL_BASE + 0x00A5)
#define WSA883X_SWR_HM_TEST0 (WSA883X_DIG_CTRL_BASE + 0x00A6)
#define WSA883X_SWR_HM_TEST1 (WSA883X_DIG_CTRL_BASE + 0x00A7)
#define WSA883X_SWR_PAD_CTL (WSA883X_DIG_CTRL_BASE + 0x00A8)
#define WSA883X_TADC_DETECT_DBG_CTL (WSA883X_DIG_CTRL_BASE + 0x00A9)
#define WSA883X_TADC_DEBUG_MSB (WSA883X_DIG_CTRL_BASE + 0x00AA)
#define WSA883X_TADC_DEBUG_LSB (WSA883X_DIG_CTRL_BASE + 0x00AB)
#define WSA883X_SAMPLE_EDGE_SEL (WSA883X_DIG_CTRL_BASE + 0x00AC)
#define WSA883X_SWR_EDGE_SEL (WSA883X_DIG_CTRL_BASE + 0x00AD)
#define WSA883X_TEST_MODE_CTL (WSA883X_DIG_CTRL_BASE + 0x00AE)
#define WSA883X_IOPAD_CTL (WSA883X_DIG_CTRL_BASE + 0x00AF)
#define WSA883X_ANA_CSR_DBG_ADD (WSA883X_DIG_CTRL_BASE + 0x00B0)
#define WSA883X_ANA_CSR_DBG_CTL (WSA883X_DIG_CTRL_BASE + 0x00B1)
#define WSA883X_SPARE_R (WSA883X_DIG_CTRL_BASE + 0x00BC)
#define WSA883X_SPARE_0 (WSA883X_DIG_CTRL_BASE + 0x00BD)
#define WSA883X_SPARE_1 (WSA883X_DIG_CTRL_BASE + 0x00BE)
#define WSA883X_SPARE_2 (WSA883X_DIG_CTRL_BASE + 0x00BF)
#define WSA883X_SCODE (WSA883X_DIG_CTRL_BASE + 0x00C0)
#define WSA883X_DIG_TRIM_BASE (WSA883X_BASE + 0x00000500)
#define WSA883X_OTP_REG_0 (WSA883X_DIG_TRIM_BASE + 0x0080)
#define WSA883X_ID_MASK GENMASK(3, 0)
#define WSA883X_OTP_REG_1 (WSA883X_DIG_TRIM_BASE + 0x0081)
#define WSA883X_OTP_REG_2 (WSA883X_DIG_TRIM_BASE + 0x0082)
#define WSA883X_OTP_REG_3 (WSA883X_DIG_TRIM_BASE + 0x0083)
#define WSA883X_OTP_REG_4 (WSA883X_DIG_TRIM_BASE + 0x0084)
#define WSA883X_OTP_REG_5 (WSA883X_DIG_TRIM_BASE + 0x0085)
#define WSA883X_OTP_REG_6 (WSA883X_DIG_TRIM_BASE + 0x0086)
#define WSA883X_OTP_REG_7 (WSA883X_DIG_TRIM_BASE + 0x0087)
#define WSA883X_OTP_REG_8 (WSA883X_DIG_TRIM_BASE + 0x0088)
#define WSA883X_OTP_REG_9 (WSA883X_DIG_TRIM_BASE + 0x0089)
#define WSA883X_OTP_REG_10 (WSA883X_DIG_TRIM_BASE + 0x008A)
#define WSA883X_OTP_REG_11 (WSA883X_DIG_TRIM_BASE + 0x008B)
#define WSA883X_OTP_REG_12 (WSA883X_DIG_TRIM_BASE + 0x008C)
#define WSA883X_OTP_REG_13 (WSA883X_DIG_TRIM_BASE + 0x008D)
#define WSA883X_OTP_REG_14 (WSA883X_DIG_TRIM_BASE + 0x008E)
#define WSA883X_OTP_REG_15 (WSA883X_DIG_TRIM_BASE + 0x008F)
#define WSA883X_OTP_REG_16 (WSA883X_DIG_TRIM_BASE + 0x0090)
#define WSA883X_OTP_REG_17 (WSA883X_DIG_TRIM_BASE + 0x0091)
#define WSA883X_OTP_REG_18 (WSA883X_DIG_TRIM_BASE + 0x0092)
#define WSA883X_OTP_REG_19 (WSA883X_DIG_TRIM_BASE + 0x0093)
#define WSA883X_OTP_REG_20 (WSA883X_DIG_TRIM_BASE + 0x0094)
#define WSA883X_OTP_REG_21 (WSA883X_DIG_TRIM_BASE + 0x0095)
#define WSA883X_OTP_REG_22 (WSA883X_DIG_TRIM_BASE + 0x0096)
#define WSA883X_OTP_REG_23 (WSA883X_DIG_TRIM_BASE + 0x0097)
#define WSA883X_OTP_REG_24 (WSA883X_DIG_TRIM_BASE + 0x0098)
#define WSA883X_OTP_REG_25 (WSA883X_DIG_TRIM_BASE + 0x0099)
#define WSA883X_OTP_REG_26 (WSA883X_DIG_TRIM_BASE + 0x009A)
#define WSA883X_OTP_REG_27 (WSA883X_DIG_TRIM_BASE + 0x009B)
#define WSA883X_OTP_REG_28 (WSA883X_DIG_TRIM_BASE + 0x009C)
#define WSA883X_OTP_REG_29 (WSA883X_DIG_TRIM_BASE + 0x009D)
#define WSA883X_OTP_REG_30 (WSA883X_DIG_TRIM_BASE + 0x009E)
#define WSA883X_OTP_REG_31 (WSA883X_DIG_TRIM_BASE + 0x009F)
#define WSA883X_OTP_REG_32 (WSA883X_DIG_TRIM_BASE + 0x00A0)
#define WSA883X_OTP_REG_33 (WSA883X_DIG_TRIM_BASE + 0x00A1)
#define WSA883X_OTP_REG_34 (WSA883X_DIG_TRIM_BASE + 0x00A2)
#define WSA883X_OTP_REG_35 (WSA883X_DIG_TRIM_BASE + 0x00A3)
#define WSA883X_OTP_REG_63 (WSA883X_DIG_TRIM_BASE + 0x00BF)
#define WSA883X_DIG_EMEM_BASE (WSA883X_BASE + 0x000005C0)
#define WSA883X_EMEM_0 (WSA883X_DIG_EMEM_BASE + 0x0000)
#define WSA883X_EMEM_1 (WSA883X_DIG_EMEM_BASE + 0x0001)
#define WSA883X_EMEM_2 (WSA883X_DIG_EMEM_BASE + 0x0002)
#define WSA883X_EMEM_3 (WSA883X_DIG_EMEM_BASE + 0x0003)
#define WSA883X_EMEM_4 (WSA883X_DIG_EMEM_BASE + 0x0004)
#define WSA883X_EMEM_5 (WSA883X_DIG_EMEM_BASE + 0x0005)
#define WSA883X_EMEM_6 (WSA883X_DIG_EMEM_BASE + 0x0006)
#define WSA883X_EMEM_7 (WSA883X_DIG_EMEM_BASE + 0x0007)
#define WSA883X_EMEM_8 (WSA883X_DIG_EMEM_BASE + 0x0008)
#define WSA883X_EMEM_9 (WSA883X_DIG_EMEM_BASE + 0x0009)
#define WSA883X_EMEM_10 (WSA883X_DIG_EMEM_BASE + 0x000A)
#define WSA883X_EMEM_11 (WSA883X_DIG_EMEM_BASE + 0x000B)
#define WSA883X_EMEM_12 (WSA883X_DIG_EMEM_BASE + 0x000C)
#define WSA883X_EMEM_13 (WSA883X_DIG_EMEM_BASE + 0x000D)
#define WSA883X_EMEM_14 (WSA883X_DIG_EMEM_BASE + 0x000E)
#define WSA883X_EMEM_15 (WSA883X_DIG_EMEM_BASE + 0x000F)
#define WSA883X_EMEM_16 (WSA883X_DIG_EMEM_BASE + 0x0010)
#define WSA883X_EMEM_17 (WSA883X_DIG_EMEM_BASE + 0x0011)
#define WSA883X_EMEM_18 (WSA883X_DIG_EMEM_BASE + 0x0012)
#define WSA883X_EMEM_19 (WSA883X_DIG_EMEM_BASE + 0x0013)
#define WSA883X_EMEM_20 (WSA883X_DIG_EMEM_BASE + 0x0014)
#define WSA883X_EMEM_21 (WSA883X_DIG_EMEM_BASE + 0x0015)
#define WSA883X_EMEM_22 (WSA883X_DIG_EMEM_BASE + 0x0016)
#define WSA883X_EMEM_23 (WSA883X_DIG_EMEM_BASE + 0x0017)
#define WSA883X_EMEM_24 (WSA883X_DIG_EMEM_BASE + 0x0018)
#define WSA883X_EMEM_25 (WSA883X_DIG_EMEM_BASE + 0x0019)
#define WSA883X_EMEM_26 (WSA883X_DIG_EMEM_BASE + 0x001A)
#define WSA883X_EMEM_27 (WSA883X_DIG_EMEM_BASE + 0x001B)
#define WSA883X_EMEM_28 (WSA883X_DIG_EMEM_BASE + 0x001C)
#define WSA883X_EMEM_29 (WSA883X_DIG_EMEM_BASE + 0x001D)
#define WSA883X_EMEM_30 (WSA883X_DIG_EMEM_BASE + 0x001E)
#define WSA883X_EMEM_31 (WSA883X_DIG_EMEM_BASE + 0x001F)
#define WSA883X_EMEM_32 (WSA883X_DIG_EMEM_BASE + 0x0020)
#define WSA883X_EMEM_33 (WSA883X_DIG_EMEM_BASE + 0x0021)
#define WSA883X_EMEM_34 (WSA883X_DIG_EMEM_BASE + 0x0022)
#define WSA883X_EMEM_35 (WSA883X_DIG_EMEM_BASE + 0x0023)
#define WSA883X_EMEM_36 (WSA883X_DIG_EMEM_BASE + 0x0024)
#define WSA883X_EMEM_37 (WSA883X_DIG_EMEM_BASE + 0x0025)
#define WSA883X_EMEM_38 (WSA883X_DIG_EMEM_BASE + 0x0026)
#define WSA883X_EMEM_39 (WSA883X_DIG_EMEM_BASE + 0x0027)
#define WSA883X_EMEM_40 (WSA883X_DIG_EMEM_BASE + 0x0028)
#define WSA883X_EMEM_41 (WSA883X_DIG_EMEM_BASE + 0x0029)
#define WSA883X_EMEM_42 (WSA883X_DIG_EMEM_BASE + 0x002A)
#define WSA883X_EMEM_43 (WSA883X_DIG_EMEM_BASE + 0x002B)
#define WSA883X_EMEM_44 (WSA883X_DIG_EMEM_BASE + 0x002C)
#define WSA883X_EMEM_45 (WSA883X_DIG_EMEM_BASE + 0x002D)
#define WSA883X_EMEM_46 (WSA883X_DIG_EMEM_BASE + 0x002E)
#define WSA883X_EMEM_47 (WSA883X_DIG_EMEM_BASE + 0x002F)
#define WSA883X_EMEM_48 (WSA883X_DIG_EMEM_BASE + 0x0030)
#define WSA883X_EMEM_49 (WSA883X_DIG_EMEM_BASE + 0x0031)
#define WSA883X_EMEM_50 (WSA883X_DIG_EMEM_BASE + 0x0032)
#define WSA883X_EMEM_51 (WSA883X_DIG_EMEM_BASE + 0x0033)
#define WSA883X_EMEM_52 (WSA883X_DIG_EMEM_BASE + 0x0034)
#define WSA883X_EMEM_53 (WSA883X_DIG_EMEM_BASE + 0x0035)
#define WSA883X_EMEM_54 (WSA883X_DIG_EMEM_BASE + 0x0036)
#define WSA883X_EMEM_55 (WSA883X_DIG_EMEM_BASE + 0x0037)
#define WSA883X_EMEM_56 (WSA883X_DIG_EMEM_BASE + 0x0038)
#define WSA883X_EMEM_57 (WSA883X_DIG_EMEM_BASE + 0x0039)
#define WSA883X_EMEM_58 (WSA883X_DIG_EMEM_BASE + 0x003A)
#define WSA883X_EMEM_59 (WSA883X_DIG_EMEM_BASE + 0x003B)
#define WSA883X_EMEM_60 (WSA883X_DIG_EMEM_BASE + 0x003C)
#define WSA883X_EMEM_61 (WSA883X_DIG_EMEM_BASE + 0x003D)
#define WSA883X_EMEM_62 (WSA883X_DIG_EMEM_BASE + 0x003E)
#define WSA883X_EMEM_63 (WSA883X_DIG_EMEM_BASE + 0x003F)
#define WSA883X_NUM_REGISTERS (WSA883X_EMEM_63 + 1)
#define WSA883X_MAX_REGISTER (WSA883X_NUM_REGISTERS - 1)
#define WSA883X_VERSION_1_0 0
#define WSA883X_VERSION_1_1 1
#define WSA883X_MAX_SWR_PORTS 4
#define WSA883X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
SNDRV_PCM_RATE_384000)
/* Fractional Rates */
#define WSA883X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
#define WSA883X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
struct wsa883x_priv {
struct regmap *regmap;
struct device *dev;
struct regulator *vdd;
struct sdw_slave *slave;
struct sdw_stream_config sconfig;
struct sdw_stream_runtime *sruntime;
struct sdw_port_config port_config[WSA883X_MAX_SWR_PORTS];
struct gpio_desc *sd_n;
bool port_prepared[WSA883X_MAX_SWR_PORTS];
bool port_enable[WSA883X_MAX_SWR_PORTS];
int version;
int variant;
int active_ports;
int dev_mode;
int comp_offset;
};
enum {
WSA8830 = 0,
WSA8835,
WSA8832,
WSA8835_V2 = 5,
};
enum {
COMP_OFFSET0,
COMP_OFFSET1,
COMP_OFFSET2,
COMP_OFFSET3,
COMP_OFFSET4,
};
enum wsa_port_ids {
WSA883X_PORT_DAC,
WSA883X_PORT_COMP,
WSA883X_PORT_BOOST,
WSA883X_PORT_VISENSE,
};
static const char * const wsa_dev_mode_text[] = {
"Speaker", "Receiver", "Ultrasound"
};
enum {
SPEAKER,
RECEIVER,
ULTRASOUND,
};
static const struct soc_enum wsa_dev_mode_enum =
SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(wsa_dev_mode_text), wsa_dev_mode_text);
/* 4 ports */
static struct sdw_dpn_prop wsa_sink_dpn_prop[WSA883X_MAX_SWR_PORTS] = {
{
/* DAC */
.num = 1,
.type = SDW_DPN_SIMPLE,
.min_ch = 1,
.max_ch = 1,
.simple_ch_prep_sm = true,
.read_only_wordlength = true,
}, {
/* COMP */
.num = 2,
.type = SDW_DPN_SIMPLE,
.min_ch = 1,
.max_ch = 1,
.simple_ch_prep_sm = true,
.read_only_wordlength = true,
}, {
/* BOOST */
.num = 3,
.type = SDW_DPN_SIMPLE,
.min_ch = 1,
.max_ch = 1,
.simple_ch_prep_sm = true,
.read_only_wordlength = true,
}, {
/* VISENSE */
.num = 4,
.type = SDW_DPN_SIMPLE,
.min_ch = 1,
.max_ch = 1,
.simple_ch_prep_sm = true,
.read_only_wordlength = true,
}
};
static const struct sdw_port_config wsa883x_pconfig[WSA883X_MAX_SWR_PORTS] = {
{
.num = 1,
.ch_mask = 0x1,
}, {
.num = 2,
.ch_mask = 0xf,
}, {
.num = 3,
.ch_mask = 0x3,
}, { /* IV feedback */
.num = 4,
.ch_mask = 0x3,
},
};
static struct reg_default wsa883x_defaults[] = {
{ WSA883X_REF_CTRL, 0xD5 },
{ WSA883X_TEST_CTL_0, 0x06 },
{ WSA883X_BIAS_0, 0xD2 },
{ WSA883X_OP_CTL, 0xE0 },
{ WSA883X_IREF_CTL, 0x57 },
{ WSA883X_ISENS_CTL, 0x47 },
{ WSA883X_CLK_CTL, 0x87 },
{ WSA883X_TEST_CTL_1, 0x00 },
{ WSA883X_BIAS_1, 0x51 },
{ WSA883X_ADC_CTL, 0x01 },
{ WSA883X_DOUT_MSB, 0x00 },
{ WSA883X_DOUT_LSB, 0x00 },
{ WSA883X_VBAT_SNS, 0x40 },
{ WSA883X_ITRIM_CODE, 0x9F },
{ WSA883X_EN, 0x20 },
{ WSA883X_OVERRIDE1, 0x00 },
{ WSA883X_OVERRIDE2, 0x08 },
{ WSA883X_VSENSE1, 0xD3 },
{ WSA883X_ISENSE1, 0xD4 },
{ WSA883X_ISENSE2, 0x20 },
{ WSA883X_ISENSE_CAL, 0x00 },
{ WSA883X_MISC, 0x08 },
{ WSA883X_ADC_0, 0x00 },
{ WSA883X_ADC_1, 0x00 },
{ WSA883X_ADC_2, 0x40 },
{ WSA883X_ADC_3, 0x80 },
{ WSA883X_ADC_4, 0x25 },
{ WSA883X_ADC_5, 0x25 },
{ WSA883X_ADC_6, 0x08 },
{ WSA883X_ADC_7, 0x81 },
{ WSA883X_STATUS, 0x00 },
{ WSA883X_DAC_CTRL_REG, 0x53 },
{ WSA883X_DAC_EN_DEBUG_REG, 0x00 },
{ WSA883X_DAC_OPAMP_BIAS1_REG, 0x48 },
{ WSA883X_DAC_OPAMP_BIAS2_REG, 0x48 },
{ WSA883X_DAC_VCM_CTRL_REG, 0x88 },
{ WSA883X_DAC_VOLTAGE_CTRL_REG, 0xA5 },
{ WSA883X_ATEST1_REG, 0x00 },
{ WSA883X_ATEST2_REG, 0x00 },
{ WSA883X_SPKR_TOP_BIAS_REG1, 0x6A },
{ WSA883X_SPKR_TOP_BIAS_REG2, 0x65 },
{ WSA883X_SPKR_TOP_BIAS_REG3, 0x55 },
{ WSA883X_SPKR_TOP_BIAS_REG4, 0xA9 },
{ WSA883X_SPKR_CLIP_DET_REG, 0x9C },
{ WSA883X_SPKR_DRV_LF_BLK_EN, 0x0F },
{ WSA883X_SPKR_DRV_LF_EN, 0x0A },
{ WSA883X_SPKR_DRV_LF_MASK_DCC_CTL, 0x00 },
{ WSA883X_SPKR_DRV_LF_MISC_CTL, 0x3A },
{ WSA883X_SPKR_DRV_LF_REG_GAIN, 0x00 },
{ WSA883X_SPKR_DRV_OS_CAL_CTL, 0x00 },
{ WSA883X_SPKR_DRV_OS_CAL_CTL1, 0x90 },
{ WSA883X_SPKR_PWM_CLK_CTL, 0x00 },
{ WSA883X_SPKR_PDRV_HS_CTL, 0x52 },
{ WSA883X_SPKR_PDRV_LS_CTL, 0x48 },
{ WSA883X_SPKR_PWRSTG_DBG, 0x08 },
{ WSA883X_SPKR_OCP_CTL, 0xE2 },
{ WSA883X_SPKR_BBM_CTL, 0x92 },
{ WSA883X_PA_STATUS0, 0x00 },
{ WSA883X_PA_STATUS1, 0x00 },
{ WSA883X_PA_STATUS2, 0x80 },
{ WSA883X_EN_CTRL, 0x44 },
{ WSA883X_CURRENT_LIMIT, 0xCC },
{ WSA883X_IBIAS1, 0x00 },
{ WSA883X_IBIAS2, 0x00 },
{ WSA883X_IBIAS3, 0x00 },
{ WSA883X_LDO_PROG, 0x02 },
{ WSA883X_STABILITY_CTRL1, 0x8E },
{ WSA883X_STABILITY_CTRL2, 0x10 },
{ WSA883X_PWRSTAGE_CTRL1, 0x06 },
{ WSA883X_PWRSTAGE_CTRL2, 0x00 },
{ WSA883X_BYPASS_1, 0x19 },
{ WSA883X_BYPASS_2, 0x13 },
{ WSA883X_ZX_CTRL_1, 0xF0 },
{ WSA883X_ZX_CTRL_2, 0x04 },
{ WSA883X_MISC1, 0x06 },
{ WSA883X_MISC2, 0xA0 },
{ WSA883X_GMAMP_SUP1, 0x82 },
{ WSA883X_PWRSTAGE_CTRL3, 0x39 },
{ WSA883X_PWRSTAGE_CTRL4, 0x5F },
{ WSA883X_TEST1, 0x00 },
{ WSA883X_SPARE1, 0x00 },
{ WSA883X_SPARE2, 0x00 },
{ WSA883X_PON_CTL_0, 0x10 },
{ WSA883X_PON_CLT_1, 0xE0 },
{ WSA883X_PON_CTL_2, 0x90 },
{ WSA883X_PON_CTL_3, 0x70 },
{ WSA883X_CKWD_CTL_0, 0x34 },
{ WSA883X_CKWD_CTL_1, 0x0F },
{ WSA883X_CKWD_CTL_2, 0x00 },
{ WSA883X_CKSK_CTL_0, 0x00 },
{ WSA883X_PADSW_CTL_0, 0x00 },
{ WSA883X_TEST_0, 0x00 },
{ WSA883X_TEST_1, 0x00 },
{ WSA883X_STATUS_0, 0x00 },
{ WSA883X_STATUS_1, 0x00 },
{ WSA883X_CHIP_ID0, 0x00 },
{ WSA883X_CHIP_ID1, 0x00 },
{ WSA883X_CHIP_ID2, 0x02 },
{ WSA883X_CHIP_ID3, 0x02 },
{ WSA883X_BUS_ID, 0x00 },
{ WSA883X_CDC_RST_CTL, 0x01 },
{ WSA883X_TOP_CLK_CFG, 0x00 },
{ WSA883X_CDC_PATH_MODE, 0x00 },
{ WSA883X_CDC_CLK_CTL, 0xFF },
{ WSA883X_SWR_RESET_EN, 0x00 },
{ WSA883X_RESET_CTL, 0x00 },
{ WSA883X_PA_FSM_CTL, 0x00 },
{ WSA883X_PA_FSM_TIMER0, 0x80 },
{ WSA883X_PA_FSM_TIMER1, 0x80 },
{ WSA883X_PA_FSM_STA, 0x00 },
{ WSA883X_PA_FSM_ERR_COND, 0x00 },
{ WSA883X_PA_FSM_MSK, 0x00 },
{ WSA883X_PA_FSM_BYP, 0x01 },
{ WSA883X_PA_FSM_DBG, 0x00 },
{ WSA883X_TADC_VALUE_CTL, 0x03 },
{ WSA883X_TEMP_DETECT_CTL, 0x01 },
{ WSA883X_TEMP_MSB, 0x00 },
{ WSA883X_TEMP_LSB, 0x00 },
{ WSA883X_TEMP_CONFIG0, 0x00 },
{ WSA883X_TEMP_CONFIG1, 0x00 },
{ WSA883X_VBAT_ADC_FLT_CTL, 0x00 },
{ WSA883X_VBAT_DIN_MSB, 0x00 },
{ WSA883X_VBAT_DIN_LSB, 0x00 },
{ WSA883X_VBAT_DOUT, 0x00 },
{ WSA883X_SDM_PDM9_LSB, 0x00 },
{ WSA883X_SDM_PDM9_MSB, 0x00 },
{ WSA883X_CDC_RX_CTL, 0xFE },
{ WSA883X_CDC_SPK_DSM_A1_0, 0x00 },
{ WSA883X_CDC_SPK_DSM_A1_1, 0x01 },
{ WSA883X_CDC_SPK_DSM_A2_0, 0x96 },
{ WSA883X_CDC_SPK_DSM_A2_1, 0x09 },
{ WSA883X_CDC_SPK_DSM_A3_0, 0xAB },
{ WSA883X_CDC_SPK_DSM_A3_1, 0x05 },
{ WSA883X_CDC_SPK_DSM_A4_0, 0x1C },
{ WSA883X_CDC_SPK_DSM_A4_1, 0x02 },
{ WSA883X_CDC_SPK_DSM_A5_0, 0x17 },
{ WSA883X_CDC_SPK_DSM_A5_1, 0x02 },
{ WSA883X_CDC_SPK_DSM_A6_0, 0xAA },
{ WSA883X_CDC_SPK_DSM_A7_0, 0xE3 },
{ WSA883X_CDC_SPK_DSM_C_0, 0x69 },
{ WSA883X_CDC_SPK_DSM_C_1, 0x54 },
{ WSA883X_CDC_SPK_DSM_C_2, 0x02 },
{ WSA883X_CDC_SPK_DSM_C_3, 0x15 },
{ WSA883X_CDC_SPK_DSM_R1, 0xA4 },
{ WSA883X_CDC_SPK_DSM_R2, 0xB5 },
{ WSA883X_CDC_SPK_DSM_R3, 0x86 },
{ WSA883X_CDC_SPK_DSM_R4, 0x85 },
{ WSA883X_CDC_SPK_DSM_R5, 0xAA },
{ WSA883X_CDC_SPK_DSM_R6, 0xE2 },
{ WSA883X_CDC_SPK_DSM_R7, 0x62 },
{ WSA883X_CDC_SPK_GAIN_PDM_0, 0x00 },
{ WSA883X_CDC_SPK_GAIN_PDM_1, 0xFC },
{ WSA883X_CDC_SPK_GAIN_PDM_2, 0x05 },
{ WSA883X_PDM_WD_CTL, 0x00 },
{ WSA883X_DEM_BYPASS_DATA0, 0x00 },
{ WSA883X_DEM_BYPASS_DATA1, 0x00 },
{ WSA883X_DEM_BYPASS_DATA2, 0x00 },
{ WSA883X_DEM_BYPASS_DATA3, 0x00 },
{ WSA883X_WAVG_CTL, 0x06 },
{ WSA883X_WAVG_LRA_PER_0, 0xD1 },
{ WSA883X_WAVG_LRA_PER_1, 0x00 },
{ WSA883X_WAVG_DELTA_THETA_0, 0xE6 },
{ WSA883X_WAVG_DELTA_THETA_1, 0x04 },
{ WSA883X_WAVG_DIRECT_AMP_0, 0x50 },
{ WSA883X_WAVG_DIRECT_AMP_1, 0x00 },
{ WSA883X_WAVG_PTRN_AMP0_0, 0x50 },
{ WSA883X_WAVG_PTRN_AMP0_1, 0x00 },
{ WSA883X_WAVG_PTRN_AMP1_0, 0x50 },
{ WSA883X_WAVG_PTRN_AMP1_1, 0x00 },
{ WSA883X_WAVG_PTRN_AMP2_0, 0x50 },
{ WSA883X_WAVG_PTRN_AMP2_1, 0x00 },
{ WSA883X_WAVG_PTRN_AMP3_0, 0x50 },
{ WSA883X_WAVG_PTRN_AMP3_1, 0x00 },
{ WSA883X_WAVG_PTRN_AMP4_0, 0x50 },
{ WSA883X_WAVG_PTRN_AMP4_1, 0x00 },
{ WSA883X_WAVG_PTRN_AMP5_0, 0x50 },
{ WSA883X_WAVG_PTRN_AMP5_1, 0x00 },
{ WSA883X_WAVG_PTRN_AMP6_0, 0x50 },
{ WSA883X_WAVG_PTRN_AMP6_1, 0x00 },
{ WSA883X_WAVG_PTRN_AMP7_0, 0x50 },
{ WSA883X_WAVG_PTRN_AMP7_1, 0x00 },
{ WSA883X_WAVG_PER_0_1, 0x88 },
{ WSA883X_WAVG_PER_2_3, 0x88 },
{ WSA883X_WAVG_PER_4_5, 0x88 },
{ WSA883X_WAVG_PER_6_7, 0x88 },
{ WSA883X_WAVG_STA, 0x00 },
{ WSA883X_DRE_CTL_0, 0x70 },
{ WSA883X_DRE_CTL_1, 0x08 },
{ WSA883X_DRE_IDLE_DET_CTL, 0x1F },
{ WSA883X_CLSH_CTL_0, 0x37 },
{ WSA883X_CLSH_CTL_1, 0x81 },
{ WSA883X_CLSH_V_HD_PA, 0x0F },
{ WSA883X_CLSH_V_PA_MIN, 0x00 },
{ WSA883X_CLSH_OVRD_VAL, 0x00 },
{ WSA883X_CLSH_HARD_MAX, 0xFF },
{ WSA883X_CLSH_SOFT_MAX, 0xF5 },
{ WSA883X_CLSH_SIG_DP, 0x00 },
{ WSA883X_TAGC_CTL, 0x10 },
{ WSA883X_TAGC_TIME, 0x20 },
{ WSA883X_TAGC_E2E_GAIN, 0x02 },
{ WSA883X_TAGC_FORCE_VAL, 0x00 },
{ WSA883X_VAGC_CTL, 0x00 },
{ WSA883X_VAGC_TIME, 0x08 },
{ WSA883X_VAGC_ATTN_LVL_1_2, 0x21 },
{ WSA883X_VAGC_ATTN_LVL_3, 0x03 },
{ WSA883X_INTR_MODE, 0x00 },
{ WSA883X_INTR_MASK0, 0x90 },
{ WSA883X_INTR_MASK1, 0x00 },
{ WSA883X_INTR_STATUS0, 0x00 },
{ WSA883X_INTR_STATUS1, 0x00 },
{ WSA883X_INTR_CLEAR0, 0x00 },
{ WSA883X_INTR_CLEAR1, 0x00 },
{ WSA883X_INTR_LEVEL0, 0x00 },
{ WSA883X_INTR_LEVEL1, 0x00 },
{ WSA883X_INTR_SET0, 0x00 },
{ WSA883X_INTR_SET1, 0x00 },
{ WSA883X_INTR_TEST0, 0x00 },
{ WSA883X_INTR_TEST1, 0x00 },
{ WSA883X_OTP_CTRL0, 0x00 },
{ WSA883X_OTP_CTRL1, 0x00 },
{ WSA883X_HDRIVE_CTL_GROUP1, 0x00 },
{ WSA883X_PIN_CTL, 0x04 },
{ WSA883X_PIN_CTL_OE, 0x00 },
{ WSA883X_PIN_WDATA_IOPAD, 0x00 },
{ WSA883X_PIN_STATUS, 0x00 },
{ WSA883X_I2C_SLAVE_CTL, 0x00 },
{ WSA883X_PDM_TEST_MODE, 0x00 },
{ WSA883X_ATE_TEST_MODE, 0x00 },
{ WSA883X_DIG_DEBUG_MODE, 0x00 },
{ WSA883X_DIG_DEBUG_SEL, 0x00 },
{ WSA883X_DIG_DEBUG_EN, 0x00 },
{ WSA883X_SWR_HM_TEST0, 0x08 },
{ WSA883X_SWR_HM_TEST1, 0x00 },
{ WSA883X_SWR_PAD_CTL, 0x37 },
{ WSA883X_TADC_DETECT_DBG_CTL, 0x00 },
{ WSA883X_TADC_DEBUG_MSB, 0x00 },
{ WSA883X_TADC_DEBUG_LSB, 0x00 },
{ WSA883X_SAMPLE_EDGE_SEL, 0x7F },
{ WSA883X_SWR_EDGE_SEL, 0x00 },
{ WSA883X_TEST_MODE_CTL, 0x04 },
{ WSA883X_IOPAD_CTL, 0x00 },
{ WSA883X_ANA_CSR_DBG_ADD, 0x00 },
{ WSA883X_ANA_CSR_DBG_CTL, 0x12 },
{ WSA883X_SPARE_R, 0x00 },
{ WSA883X_SPARE_0, 0x00 },
{ WSA883X_SPARE_1, 0x00 },
{ WSA883X_SPARE_2, 0x00 },
{ WSA883X_SCODE, 0x00 },
{ WSA883X_OTP_REG_0, 0x05 },
{ WSA883X_OTP_REG_1, 0xFF },
{ WSA883X_OTP_REG_2, 0xC0 },
{ WSA883X_OTP_REG_3, 0xFF },
{ WSA883X_OTP_REG_4, 0xC0 },
{ WSA883X_OTP_REG_5, 0xFF },
{ WSA883X_OTP_REG_6, 0xFF },
{ WSA883X_OTP_REG_7, 0xFF },
{ WSA883X_OTP_REG_8, 0xFF },
{ WSA883X_OTP_REG_9, 0xFF },
{ WSA883X_OTP_REG_10, 0xFF },
{ WSA883X_OTP_REG_11, 0xFF },
{ WSA883X_OTP_REG_12, 0xFF },
{ WSA883X_OTP_REG_13, 0xFF },
{ WSA883X_OTP_REG_14, 0xFF },
{ WSA883X_OTP_REG_15, 0xFF },
{ WSA883X_OTP_REG_16, 0xFF },
{ WSA883X_OTP_REG_17, 0xFF },
{ WSA883X_OTP_REG_18, 0xFF },
{ WSA883X_OTP_REG_19, 0xFF },
{ WSA883X_OTP_REG_20, 0xFF },
{ WSA883X_OTP_REG_21, 0xFF },
{ WSA883X_OTP_REG_22, 0xFF },
{ WSA883X_OTP_REG_23, 0xFF },
{ WSA883X_OTP_REG_24, 0x37 },
{ WSA883X_OTP_REG_25, 0x3F },
{ WSA883X_OTP_REG_26, 0x03 },
{ WSA883X_OTP_REG_27, 0x00 },
{ WSA883X_OTP_REG_28, 0x00 },
{ WSA883X_OTP_REG_29, 0x00 },
{ WSA883X_OTP_REG_30, 0x00 },
{ WSA883X_OTP_REG_31, 0x03 },
{ WSA883X_OTP_REG_32, 0x00 },
{ WSA883X_OTP_REG_33, 0xFF },
{ WSA883X_OTP_REG_34, 0x00 },
{ WSA883X_OTP_REG_35, 0x00 },
{ WSA883X_OTP_REG_63, 0x40 },
{ WSA883X_EMEM_0, 0x00 },
{ WSA883X_EMEM_1, 0x00 },
{ WSA883X_EMEM_2, 0x00 },
{ WSA883X_EMEM_3, 0x00 },
{ WSA883X_EMEM_4, 0x00 },
{ WSA883X_EMEM_5, 0x00 },
{ WSA883X_EMEM_6, 0x00 },
{ WSA883X_EMEM_7, 0x00 },
{ WSA883X_EMEM_8, 0x00 },
{ WSA883X_EMEM_9, 0x00 },
{ WSA883X_EMEM_10, 0x00 },
{ WSA883X_EMEM_11, 0x00 },
{ WSA883X_EMEM_12, 0x00 },
{ WSA883X_EMEM_13, 0x00 },
{ WSA883X_EMEM_14, 0x00 },
{ WSA883X_EMEM_15, 0x00 },
{ WSA883X_EMEM_16, 0x00 },
{ WSA883X_EMEM_17, 0x00 },
{ WSA883X_EMEM_18, 0x00 },
{ WSA883X_EMEM_19, 0x00 },
{ WSA883X_EMEM_20, 0x00 },
{ WSA883X_EMEM_21, 0x00 },
{ WSA883X_EMEM_22, 0x00 },
{ WSA883X_EMEM_23, 0x00 },
{ WSA883X_EMEM_24, 0x00 },
{ WSA883X_EMEM_25, 0x00 },
{ WSA883X_EMEM_26, 0x00 },
{ WSA883X_EMEM_27, 0x00 },
{ WSA883X_EMEM_28, 0x00 },
{ WSA883X_EMEM_29, 0x00 },
{ WSA883X_EMEM_30, 0x00 },
{ WSA883X_EMEM_31, 0x00 },
{ WSA883X_EMEM_32, 0x00 },
{ WSA883X_EMEM_33, 0x00 },
{ WSA883X_EMEM_34, 0x00 },
{ WSA883X_EMEM_35, 0x00 },
{ WSA883X_EMEM_36, 0x00 },
{ WSA883X_EMEM_37, 0x00 },
{ WSA883X_EMEM_38, 0x00 },
{ WSA883X_EMEM_39, 0x00 },
{ WSA883X_EMEM_40, 0x00 },
{ WSA883X_EMEM_41, 0x00 },
{ WSA883X_EMEM_42, 0x00 },
{ WSA883X_EMEM_43, 0x00 },
{ WSA883X_EMEM_44, 0x00 },
{ WSA883X_EMEM_45, 0x00 },
{ WSA883X_EMEM_46, 0x00 },
{ WSA883X_EMEM_47, 0x00 },
{ WSA883X_EMEM_48, 0x00 },
{ WSA883X_EMEM_49, 0x00 },
{ WSA883X_EMEM_50, 0x00 },
{ WSA883X_EMEM_51, 0x00 },
{ WSA883X_EMEM_52, 0x00 },
{ WSA883X_EMEM_53, 0x00 },
{ WSA883X_EMEM_54, 0x00 },
{ WSA883X_EMEM_55, 0x00 },
{ WSA883X_EMEM_56, 0x00 },
{ WSA883X_EMEM_57, 0x00 },
{ WSA883X_EMEM_58, 0x00 },
{ WSA883X_EMEM_59, 0x00 },
{ WSA883X_EMEM_60, 0x00 },
{ WSA883X_EMEM_61, 0x00 },
{ WSA883X_EMEM_62, 0x00 },
{ WSA883X_EMEM_63, 0x00 },
};
static bool wsa883x_readonly_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case WSA883X_DOUT_MSB:
case WSA883X_DOUT_LSB:
case WSA883X_STATUS:
case WSA883X_PA_STATUS0:
case WSA883X_PA_STATUS1:
case WSA883X_PA_STATUS2:
case WSA883X_STATUS_0:
case WSA883X_STATUS_1:
case WSA883X_CHIP_ID0:
case WSA883X_CHIP_ID1:
case WSA883X_CHIP_ID2:
case WSA883X_CHIP_ID3:
case WSA883X_BUS_ID:
case WSA883X_PA_FSM_STA:
case WSA883X_PA_FSM_ERR_COND:
case WSA883X_TEMP_MSB:
case WSA883X_TEMP_LSB:
case WSA883X_VBAT_DIN_MSB:
case WSA883X_VBAT_DIN_LSB:
case WSA883X_VBAT_DOUT:
case WSA883X_SDM_PDM9_LSB:
case WSA883X_SDM_PDM9_MSB:
case WSA883X_WAVG_STA:
case WSA883X_INTR_STATUS0:
case WSA883X_INTR_STATUS1:
case WSA883X_OTP_CTRL1:
case WSA883X_PIN_STATUS:
case WSA883X_ATE_TEST_MODE:
case WSA883X_SWR_HM_TEST1:
case WSA883X_SPARE_R:
case WSA883X_OTP_REG_0:
return true;
}
return false;
}
static bool wsa883x_writeable_register(struct device *dev, unsigned int reg)
{
return !wsa883x_readonly_register(dev, reg);
}
static bool wsa883x_volatile_register(struct device *dev, unsigned int reg)
{
return wsa883x_readonly_register(dev, reg);
}
static struct regmap_config wsa883x_regmap_config = {
.reg_bits = 32,
.val_bits = 8,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = wsa883x_defaults,
.max_register = WSA883X_MAX_REGISTER,
.num_reg_defaults = ARRAY_SIZE(wsa883x_defaults),
.volatile_reg = wsa883x_volatile_register,
.writeable_reg = wsa883x_writeable_register,
.reg_format_endian = REGMAP_ENDIAN_NATIVE,
.val_format_endian = REGMAP_ENDIAN_NATIVE,
.use_single_read = true,
};
static const struct reg_sequence reg_init[] = {
{WSA883X_PA_FSM_BYP, 0x00},
{WSA883X_ADC_6, 0x02},
{WSA883X_CDC_SPK_DSM_A2_0, 0x0A},
{WSA883X_CDC_SPK_DSM_A2_1, 0x08},
{WSA883X_CDC_SPK_DSM_A3_0, 0xF3},
{WSA883X_CDC_SPK_DSM_A3_1, 0x07},
{WSA883X_CDC_SPK_DSM_A4_0, 0x79},
{WSA883X_CDC_SPK_DSM_A4_1, 0x02},
{WSA883X_CDC_SPK_DSM_A5_0, 0x0B},
{WSA883X_CDC_SPK_DSM_A5_1, 0x02},
{WSA883X_CDC_SPK_DSM_A6_0, 0x8A},
{WSA883X_CDC_SPK_DSM_A7_0, 0x9B},
{WSA883X_CDC_SPK_DSM_C_0, 0x68},
{WSA883X_CDC_SPK_DSM_C_1, 0x54},
{WSA883X_CDC_SPK_DSM_C_2, 0xF2},
{WSA883X_CDC_SPK_DSM_C_3, 0x20},
{WSA883X_CDC_SPK_DSM_R1, 0x83},
{WSA883X_CDC_SPK_DSM_R2, 0x7F},
{WSA883X_CDC_SPK_DSM_R3, 0x9D},
{WSA883X_CDC_SPK_DSM_R4, 0x82},
{WSA883X_CDC_SPK_DSM_R5, 0x8B},
{WSA883X_CDC_SPK_DSM_R6, 0x9B},
{WSA883X_CDC_SPK_DSM_R7, 0x3F},
{WSA883X_VBAT_SNS, 0x20},
{WSA883X_DRE_CTL_0, 0x92},
{WSA883X_DRE_IDLE_DET_CTL, 0x0F},
{WSA883X_CURRENT_LIMIT, 0xC4},
{WSA883X_VAGC_TIME, 0x0F},
{WSA883X_VAGC_ATTN_LVL_1_2, 0x00},
{WSA883X_VAGC_ATTN_LVL_3, 0x01},
{WSA883X_VAGC_CTL, 0x01},
{WSA883X_TAGC_CTL, 0x1A},
{WSA883X_TAGC_TIME, 0x2C},
{WSA883X_TEMP_CONFIG0, 0x02},
{WSA883X_TEMP_CONFIG1, 0x02},
{WSA883X_OTP_REG_1, 0x49},
{WSA883X_OTP_REG_2, 0x80},
{WSA883X_OTP_REG_3, 0xC9},
{WSA883X_OTP_REG_4, 0x40},
{WSA883X_TAGC_CTL, 0x1B},
{WSA883X_ADC_2, 0x00},
{WSA883X_ADC_7, 0x85},
{WSA883X_ADC_7, 0x87},
{WSA883X_CKWD_CTL_0, 0x14},
{WSA883X_CKWD_CTL_1, 0x1B},
{WSA883X_GMAMP_SUP1, 0xE2},
};
static void wsa883x_init(struct wsa883x_priv *wsa883x)
{
struct regmap *regmap = wsa883x->regmap;
int variant, version;
regmap_read(regmap, WSA883X_OTP_REG_0, &variant);
wsa883x->variant = variant & WSA883X_ID_MASK;
regmap_read(regmap, WSA883X_CHIP_ID0, &version);
wsa883x->version = version;
switch (wsa883x->variant) {
case WSA8830:
dev_info(wsa883x->dev, "WSA883X Version 1_%d, Variant: WSA8830\n",
wsa883x->version);
break;
case WSA8835:
dev_info(wsa883x->dev, "WSA883X Version 1_%d, Variant: WSA8835\n",
wsa883x->version);
break;
case WSA8832:
dev_info(wsa883x->dev, "WSA883X Version 1_%d, Variant: WSA8832\n",
wsa883x->version);
break;
case WSA8835_V2:
dev_info(wsa883x->dev, "WSA883X Version 1_%d, Variant: WSA8835_V2\n",
wsa883x->version);
break;
default:
break;
}
wsa883x->comp_offset = COMP_OFFSET2;
/* Initial settings */
regmap_multi_reg_write(regmap, reg_init, ARRAY_SIZE(reg_init));
if (wsa883x->variant == WSA8830 || wsa883x->variant == WSA8832) {
wsa883x->comp_offset = COMP_OFFSET3;
regmap_update_bits(regmap, WSA883X_DRE_CTL_0,
WSA883X_DRE_OFFSET_MASK,
wsa883x->comp_offset);
}
}
static int wsa883x_update_status(struct sdw_slave *slave,
enum sdw_slave_status status)
{
struct wsa883x_priv *wsa883x = dev_get_drvdata(&slave->dev);
if (status == SDW_SLAVE_ATTACHED && slave->dev_num > 0)
wsa883x_init(wsa883x);
return 0;
}
static int wsa883x_port_prep(struct sdw_slave *slave,
struct sdw_prepare_ch *prepare_ch,
enum sdw_port_prep_ops state)
{
struct wsa883x_priv *wsa883x = dev_get_drvdata(&slave->dev);
if (state == SDW_OPS_PORT_POST_PREP)
wsa883x->port_prepared[prepare_ch->num - 1] = true;
else
wsa883x->port_prepared[prepare_ch->num - 1] = false;
return 0;
}
static const struct sdw_slave_ops wsa883x_slave_ops = {
.update_status = wsa883x_update_status,
.port_prep = wsa883x_port_prep,
};
static int wsa_dev_mode_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(component);
ucontrol->value.enumerated.item[0] = wsa883x->dev_mode;
return 0;
}
static int wsa_dev_mode_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(component);
if (wsa883x->dev_mode == ucontrol->value.enumerated.item[0])
return 0;
wsa883x->dev_mode = ucontrol->value.enumerated.item[0];
return 1;
}
static const DECLARE_TLV_DB_SCALE(pa_gain, -300, 150, -300);
static int wsa883x_get_swr_port(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
struct wsa883x_priv *data = snd_soc_component_get_drvdata(comp);
struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
int portidx = mixer->reg;
ucontrol->value.integer.value[0] = data->port_enable[portidx];
return 0;
}
static int wsa883x_set_swr_port(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
struct wsa883x_priv *data = snd_soc_component_get_drvdata(comp);
struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
int portidx = mixer->reg;
if (ucontrol->value.integer.value[0]) {
if (data->port_enable[portidx])
return 0;
data->port_enable[portidx] = true;
} else {
if (!data->port_enable[portidx])
return 0;
data->port_enable[portidx] = false;
}
return 1;
}
static int wsa883x_get_comp_offset(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = wsa883x->comp_offset;
return 0;
}
static int wsa883x_set_comp_offset(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(component);
if (wsa883x->comp_offset == ucontrol->value.integer.value[0])
return 0;
wsa883x->comp_offset = ucontrol->value.integer.value[0];
return 1;
}
static int wsa883x_codec_probe(struct snd_soc_component *comp)
{
struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(comp);
snd_soc_component_init_regmap(comp, wsa883x->regmap);
return 0;
}
static int wsa883x_spkr_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
switch (wsa883x->dev_mode) {
case RECEIVER:
snd_soc_component_write_field(component, WSA883X_CDC_PATH_MODE,
WSA883X_RXD_MODE_MASK,
WSA883X_RXD_MODE_HIFI);
snd_soc_component_write_field(component, WSA883X_SPKR_PWM_CLK_CTL,
WSA883X_SPKR_PWM_FREQ_SEL_MASK,
WSA883X_SPKR_PWM_FREQ_F600KHZ);
snd_soc_component_write_field(component, WSA883X_DRE_CTL_0,
WSA883X_DRE_PROG_DELAY_MASK, 0x0);
break;
case SPEAKER:
snd_soc_component_write_field(component, WSA883X_CDC_PATH_MODE,
WSA883X_RXD_MODE_MASK,
WSA883X_RXD_MODE_NORMAL);
snd_soc_component_write_field(component, WSA883X_SPKR_PWM_CLK_CTL,
WSA883X_SPKR_PWM_FREQ_SEL_MASK,
WSA883X_SPKR_PWM_FREQ_F300KHZ);
snd_soc_component_write_field(component, WSA883X_DRE_CTL_0,
WSA883X_DRE_PROG_DELAY_MASK, 0x9);
break;
default:
break;
}
snd_soc_component_write_field(component, WSA883X_DRE_CTL_1,
WSA883X_DRE_GAIN_EN_MASK,
WSA883X_DRE_GAIN_FROM_CSR);
if (wsa883x->port_enable[WSA883X_PORT_COMP])
snd_soc_component_write_field(component, WSA883X_DRE_CTL_0,
WSA883X_DRE_OFFSET_MASK,
wsa883x->comp_offset);
snd_soc_component_write_field(component, WSA883X_VBAT_ADC_FLT_CTL,
WSA883X_VBAT_ADC_COEF_SEL_MASK,
WSA883X_VBAT_ADC_COEF_F_1DIV16);
snd_soc_component_write_field(component, WSA883X_VBAT_ADC_FLT_CTL,
WSA883X_VBAT_ADC_FLT_EN_MASK, 0x1);
snd_soc_component_write_field(component, WSA883X_PDM_WD_CTL,
WSA883X_PDM_EN_MASK,
WSA883X_PDM_ENABLE);
snd_soc_component_write_field(component, WSA883X_PA_FSM_CTL,
WSA883X_GLOBAL_PA_EN_MASK,
WSA883X_GLOBAL_PA_ENABLE);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_write_field(component, WSA883X_VBAT_ADC_FLT_CTL,
WSA883X_VBAT_ADC_FLT_EN_MASK, 0x0);
snd_soc_component_write_field(component, WSA883X_VBAT_ADC_FLT_CTL,
WSA883X_VBAT_ADC_COEF_SEL_MASK,
WSA883X_VBAT_ADC_COEF_F_1DIV2);
snd_soc_component_write_field(component, WSA883X_PA_FSM_CTL,
WSA883X_GLOBAL_PA_EN_MASK, 0);
snd_soc_component_write_field(component, WSA883X_PDM_WD_CTL,
WSA883X_PDM_EN_MASK, 0);
break;
}
return 0;
}
static const struct snd_soc_dapm_widget wsa883x_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("IN"),
SND_SOC_DAPM_SPK("SPKR", wsa883x_spkr_event),
};
static const struct snd_kcontrol_new wsa883x_snd_controls[] = {
SOC_SINGLE_RANGE_TLV("PA Volume", WSA883X_DRE_CTL_1, 1,
0x0, 0x1f, 1, pa_gain),
SOC_ENUM_EXT("WSA MODE", wsa_dev_mode_enum,
wsa_dev_mode_get, wsa_dev_mode_put),
SOC_SINGLE_EXT("COMP Offset", SND_SOC_NOPM, 0, 4, 0,
wsa883x_get_comp_offset, wsa883x_set_comp_offset),
SOC_SINGLE_EXT("DAC Switch", WSA883X_PORT_DAC, 0, 1, 0,
wsa883x_get_swr_port, wsa883x_set_swr_port),
SOC_SINGLE_EXT("COMP Switch", WSA883X_PORT_COMP, 0, 1, 0,
wsa883x_get_swr_port, wsa883x_set_swr_port),
SOC_SINGLE_EXT("BOOST Switch", WSA883X_PORT_BOOST, 0, 1, 0,
wsa883x_get_swr_port, wsa883x_set_swr_port),
SOC_SINGLE_EXT("VISENSE Switch", WSA883X_PORT_VISENSE, 0, 1, 0,
wsa883x_get_swr_port, wsa883x_set_swr_port),
};
static const struct snd_soc_dapm_route wsa883x_audio_map[] = {
{"SPKR", NULL, "IN"},
};
static const struct snd_soc_component_driver wsa883x_component_drv = {
.name = "WSA883x",
.probe = wsa883x_codec_probe,
.controls = wsa883x_snd_controls,
.num_controls = ARRAY_SIZE(wsa883x_snd_controls),
.dapm_widgets = wsa883x_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wsa883x_dapm_widgets),
.dapm_routes = wsa883x_audio_map,
.num_dapm_routes = ARRAY_SIZE(wsa883x_audio_map),
};
static int wsa883x_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct wsa883x_priv *wsa883x = dev_get_drvdata(dai->dev);
int i;
wsa883x->active_ports = 0;
for (i = 0; i < WSA883X_MAX_SWR_PORTS; i++) {
if (!wsa883x->port_enable[i])
continue;
wsa883x->port_config[wsa883x->active_ports] = wsa883x_pconfig[i];
wsa883x->active_ports++;
}
wsa883x->sconfig.frame_rate = params_rate(params);
return sdw_stream_add_slave(wsa883x->slave, &wsa883x->sconfig,
wsa883x->port_config, wsa883x->active_ports,
wsa883x->sruntime);
}
static int wsa883x_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct wsa883x_priv *wsa883x = dev_get_drvdata(dai->dev);
sdw_stream_remove_slave(wsa883x->slave, wsa883x->sruntime);
return 0;
}
static int wsa883x_set_sdw_stream(struct snd_soc_dai *dai,
void *stream, int direction)
{
struct wsa883x_priv *wsa883x = dev_get_drvdata(dai->dev);
wsa883x->sruntime = stream;
return 0;
}
static int wsa883x_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
{
struct snd_soc_component *component = dai->component;
if (mute) {
snd_soc_component_write_field(component, WSA883X_DRE_CTL_1,
WSA883X_DRE_GAIN_EN_MASK, 0);
snd_soc_component_write_field(component, WSA883X_PA_FSM_CTL,
WSA883X_GLOBAL_PA_EN_MASK, 0);
} else {
snd_soc_component_write_field(component, WSA883X_DRE_CTL_1,
WSA883X_DRE_GAIN_EN_MASK,
WSA883X_DRE_GAIN_FROM_CSR);
snd_soc_component_write_field(component, WSA883X_PA_FSM_CTL,
WSA883X_GLOBAL_PA_EN_MASK,
WSA883X_GLOBAL_PA_ENABLE);
}
return 0;
}
static const struct snd_soc_dai_ops wsa883x_dai_ops = {
.hw_params = wsa883x_hw_params,
.hw_free = wsa883x_hw_free,
.mute_stream = wsa883x_digital_mute,
.set_stream = wsa883x_set_sdw_stream,
};
static struct snd_soc_dai_driver wsa883x_dais[] = {
{
.name = "SPKR",
.playback = {
.stream_name = "SPKR Playback",
.rates = WSA883X_RATES | WSA883X_FRAC_RATES,
.formats = WSA883X_FORMATS,
.rate_min = 8000,
.rate_max = 352800,
.channels_min = 1,
.channels_max = 1,
},
.ops = &wsa883x_dai_ops,
},
};
static int wsa883x_probe(struct sdw_slave *pdev,
const struct sdw_device_id *id)
{
struct wsa883x_priv *wsa883x;
struct device *dev = &pdev->dev;
int ret;
wsa883x = devm_kzalloc(dev, sizeof(*wsa883x), GFP_KERNEL);
if (!wsa883x)
return -ENOMEM;
wsa883x->vdd = devm_regulator_get(dev, "vdd");
if (IS_ERR(wsa883x->vdd))
return dev_err_probe(dev, PTR_ERR(wsa883x->vdd),
"No vdd regulator found\n");
ret = regulator_enable(wsa883x->vdd);
if (ret)
return dev_err_probe(dev, ret, "Failed to enable vdd regulator\n");
wsa883x->sd_n = devm_gpiod_get_optional(dev, "powerdown",
GPIOD_FLAGS_BIT_NONEXCLUSIVE | GPIOD_OUT_HIGH);
if (IS_ERR(wsa883x->sd_n)) {
ret = dev_err_probe(dev, PTR_ERR(wsa883x->sd_n),
"Shutdown Control GPIO not found\n");
goto err;
}
dev_set_drvdata(dev, wsa883x);
wsa883x->slave = pdev;
wsa883x->dev = dev;
wsa883x->sconfig.ch_count = 1;
wsa883x->sconfig.bps = 1;
wsa883x->sconfig.direction = SDW_DATA_DIR_RX;
wsa883x->sconfig.type = SDW_STREAM_PDM;
pdev->prop.sink_ports = GENMASK(WSA883X_MAX_SWR_PORTS, 0);
pdev->prop.simple_clk_stop_capable = true;
pdev->prop.sink_dpn_prop = wsa_sink_dpn_prop;
pdev->prop.scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
gpiod_direction_output(wsa883x->sd_n, 0);
wsa883x->regmap = devm_regmap_init_sdw(pdev, &wsa883x_regmap_config);
if (IS_ERR(wsa883x->regmap)) {
gpiod_direction_output(wsa883x->sd_n, 1);
ret = dev_err_probe(dev, PTR_ERR(wsa883x->regmap),
"regmap_init failed\n");
goto err;
}
pm_runtime_set_autosuspend_delay(dev, 3000);
pm_runtime_use_autosuspend(dev);
pm_runtime_mark_last_busy(dev);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
ret = devm_snd_soc_register_component(dev,
&wsa883x_component_drv,
wsa883x_dais,
ARRAY_SIZE(wsa883x_dais));
err:
if (ret)
regulator_disable(wsa883x->vdd);
return ret;
}
static int __maybe_unused wsa883x_runtime_suspend(struct device *dev)
{
struct regmap *regmap = dev_get_regmap(dev, NULL);
regcache_cache_only(regmap, true);
regcache_mark_dirty(regmap);
return 0;
}
static int __maybe_unused wsa883x_runtime_resume(struct device *dev)
{
struct regmap *regmap = dev_get_regmap(dev, NULL);
regcache_cache_only(regmap, false);
regcache_sync(regmap);
return 0;
}
static const struct dev_pm_ops wsa883x_pm_ops = {
SET_RUNTIME_PM_OPS(wsa883x_runtime_suspend, wsa883x_runtime_resume, NULL)
};
static const struct sdw_device_id wsa883x_swr_id[] = {
SDW_SLAVE_ENTRY(0x0217, 0x0202, 0),
{},
};
MODULE_DEVICE_TABLE(sdw, wsa883x_swr_id);
static struct sdw_driver wsa883x_codec_driver = {
.driver = {
.name = "wsa883x-codec",
.pm = &wsa883x_pm_ops,
.suppress_bind_attrs = true,
},
.probe = wsa883x_probe,
.ops = &wsa883x_slave_ops,
.id_table = wsa883x_swr_id,
};
module_sdw_driver(wsa883x_codec_driver);
MODULE_DESCRIPTION("WSA883x codec driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wsa883x.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* ak4671.c -- audio driver for AK4671
*
* Copyright (C) 2009 Samsung Electronics Co.Ltd
* Author: Joonyoung Shim <[email protected]>
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/delay.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "ak4671.h"
/* ak4671 register cache & default register settings */
static const struct reg_default ak4671_reg_defaults[] = {
{ 0x00, 0x00 }, /* AK4671_AD_DA_POWER_MANAGEMENT (0x00) */
{ 0x01, 0xf6 }, /* AK4671_PLL_MODE_SELECT0 (0x01) */
{ 0x02, 0x00 }, /* AK4671_PLL_MODE_SELECT1 (0x02) */
{ 0x03, 0x02 }, /* AK4671_FORMAT_SELECT (0x03) */
{ 0x04, 0x00 }, /* AK4671_MIC_SIGNAL_SELECT (0x04) */
{ 0x05, 0x55 }, /* AK4671_MIC_AMP_GAIN (0x05) */
{ 0x06, 0x00 }, /* AK4671_MIXING_POWER_MANAGEMENT0 (0x06) */
{ 0x07, 0x00 }, /* AK4671_MIXING_POWER_MANAGEMENT1 (0x07) */
{ 0x08, 0xb5 }, /* AK4671_OUTPUT_VOLUME_CONTROL (0x08) */
{ 0x09, 0x00 }, /* AK4671_LOUT1_SIGNAL_SELECT (0x09) */
{ 0x0a, 0x00 }, /* AK4671_ROUT1_SIGNAL_SELECT (0x0a) */
{ 0x0b, 0x00 }, /* AK4671_LOUT2_SIGNAL_SELECT (0x0b) */
{ 0x0c, 0x00 }, /* AK4671_ROUT2_SIGNAL_SELECT (0x0c) */
{ 0x0d, 0x00 }, /* AK4671_LOUT3_SIGNAL_SELECT (0x0d) */
{ 0x0e, 0x00 }, /* AK4671_ROUT3_SIGNAL_SELECT (0x0e) */
{ 0x0f, 0x00 }, /* AK4671_LOUT1_POWER_MANAGERMENT (0x0f) */
{ 0x10, 0x00 }, /* AK4671_LOUT2_POWER_MANAGERMENT (0x10) */
{ 0x11, 0x80 }, /* AK4671_LOUT3_POWER_MANAGERMENT (0x11) */
{ 0x12, 0x91 }, /* AK4671_LCH_INPUT_VOLUME_CONTROL (0x12) */
{ 0x13, 0x91 }, /* AK4671_RCH_INPUT_VOLUME_CONTROL (0x13) */
{ 0x14, 0xe1 }, /* AK4671_ALC_REFERENCE_SELECT (0x14) */
{ 0x15, 0x00 }, /* AK4671_DIGITAL_MIXING_CONTROL (0x15) */
{ 0x16, 0x00 }, /* AK4671_ALC_TIMER_SELECT (0x16) */
{ 0x17, 0x00 }, /* AK4671_ALC_MODE_CONTROL (0x17) */
{ 0x18, 0x02 }, /* AK4671_MODE_CONTROL1 (0x18) */
{ 0x19, 0x01 }, /* AK4671_MODE_CONTROL2 (0x19) */
{ 0x1a, 0x18 }, /* AK4671_LCH_OUTPUT_VOLUME_CONTROL (0x1a) */
{ 0x1b, 0x18 }, /* AK4671_RCH_OUTPUT_VOLUME_CONTROL (0x1b) */
{ 0x1c, 0x00 }, /* AK4671_SIDETONE_A_CONTROL (0x1c) */
{ 0x1d, 0x02 }, /* AK4671_DIGITAL_FILTER_SELECT (0x1d) */
{ 0x1e, 0x00 }, /* AK4671_FIL3_COEFFICIENT0 (0x1e) */
{ 0x1f, 0x00 }, /* AK4671_FIL3_COEFFICIENT1 (0x1f) */
{ 0x20, 0x00 }, /* AK4671_FIL3_COEFFICIENT2 (0x20) */
{ 0x21, 0x00 }, /* AK4671_FIL3_COEFFICIENT3 (0x21) */
{ 0x22, 0x00 }, /* AK4671_EQ_COEFFICIENT0 (0x22) */
{ 0x23, 0x00 }, /* AK4671_EQ_COEFFICIENT1 (0x23) */
{ 0x24, 0x00 }, /* AK4671_EQ_COEFFICIENT2 (0x24) */
{ 0x25, 0x00 }, /* AK4671_EQ_COEFFICIENT3 (0x25) */
{ 0x26, 0x00 }, /* AK4671_EQ_COEFFICIENT4 (0x26) */
{ 0x27, 0x00 }, /* AK4671_EQ_COEFFICIENT5 (0x27) */
{ 0x28, 0xa9 }, /* AK4671_FIL1_COEFFICIENT0 (0x28) */
{ 0x29, 0x1f }, /* AK4671_FIL1_COEFFICIENT1 (0x29) */
{ 0x2a, 0xad }, /* AK4671_FIL1_COEFFICIENT2 (0x2a) */
{ 0x2b, 0x20 }, /* AK4671_FIL1_COEFFICIENT3 (0x2b) */
{ 0x2c, 0x00 }, /* AK4671_FIL2_COEFFICIENT0 (0x2c) */
{ 0x2d, 0x00 }, /* AK4671_FIL2_COEFFICIENT1 (0x2d) */
{ 0x2e, 0x00 }, /* AK4671_FIL2_COEFFICIENT2 (0x2e) */
{ 0x2f, 0x00 }, /* AK4671_FIL2_COEFFICIENT3 (0x2f) */
{ 0x30, 0x00 }, /* AK4671_DIGITAL_FILTER_SELECT2 (0x30) */
{ 0x32, 0x00 }, /* AK4671_E1_COEFFICIENT0 (0x32) */
{ 0x33, 0x00 }, /* AK4671_E1_COEFFICIENT1 (0x33) */
{ 0x34, 0x00 }, /* AK4671_E1_COEFFICIENT2 (0x34) */
{ 0x35, 0x00 }, /* AK4671_E1_COEFFICIENT3 (0x35) */
{ 0x36, 0x00 }, /* AK4671_E1_COEFFICIENT4 (0x36) */
{ 0x37, 0x00 }, /* AK4671_E1_COEFFICIENT5 (0x37) */
{ 0x38, 0x00 }, /* AK4671_E2_COEFFICIENT0 (0x38) */
{ 0x39, 0x00 }, /* AK4671_E2_COEFFICIENT1 (0x39) */
{ 0x3a, 0x00 }, /* AK4671_E2_COEFFICIENT2 (0x3a) */
{ 0x3b, 0x00 }, /* AK4671_E2_COEFFICIENT3 (0x3b) */
{ 0x3c, 0x00 }, /* AK4671_E2_COEFFICIENT4 (0x3c) */
{ 0x3d, 0x00 }, /* AK4671_E2_COEFFICIENT5 (0x3d) */
{ 0x3e, 0x00 }, /* AK4671_E3_COEFFICIENT0 (0x3e) */
{ 0x3f, 0x00 }, /* AK4671_E3_COEFFICIENT1 (0x3f) */
{ 0x40, 0x00 }, /* AK4671_E3_COEFFICIENT2 (0x40) */
{ 0x41, 0x00 }, /* AK4671_E3_COEFFICIENT3 (0x41) */
{ 0x42, 0x00 }, /* AK4671_E3_COEFFICIENT4 (0x42) */
{ 0x43, 0x00 }, /* AK4671_E3_COEFFICIENT5 (0x43) */
{ 0x44, 0x00 }, /* AK4671_E4_COEFFICIENT0 (0x44) */
{ 0x45, 0x00 }, /* AK4671_E4_COEFFICIENT1 (0x45) */
{ 0x46, 0x00 }, /* AK4671_E4_COEFFICIENT2 (0x46) */
{ 0x47, 0x00 }, /* AK4671_E4_COEFFICIENT3 (0x47) */
{ 0x48, 0x00 }, /* AK4671_E4_COEFFICIENT4 (0x48) */
{ 0x49, 0x00 }, /* AK4671_E4_COEFFICIENT5 (0x49) */
{ 0x4a, 0x00 }, /* AK4671_E5_COEFFICIENT0 (0x4a) */
{ 0x4b, 0x00 }, /* AK4671_E5_COEFFICIENT1 (0x4b) */
{ 0x4c, 0x00 }, /* AK4671_E5_COEFFICIENT2 (0x4c) */
{ 0x4d, 0x00 }, /* AK4671_E5_COEFFICIENT3 (0x4d) */
{ 0x4e, 0x00 }, /* AK4671_E5_COEFFICIENT4 (0x4e) */
{ 0x4f, 0x00 }, /* AK4671_E5_COEFFICIENT5 (0x4f) */
{ 0x50, 0x88 }, /* AK4671_EQ_CONTROL_250HZ_100HZ (0x50) */
{ 0x51, 0x88 }, /* AK4671_EQ_CONTROL_3500HZ_1KHZ (0x51) */
{ 0x52, 0x08 }, /* AK4671_EQ_CONTRO_10KHZ (0x52) */
{ 0x53, 0x00 }, /* AK4671_PCM_IF_CONTROL0 (0x53) */
{ 0x54, 0x00 }, /* AK4671_PCM_IF_CONTROL1 (0x54) */
{ 0x55, 0x00 }, /* AK4671_PCM_IF_CONTROL2 (0x55) */
{ 0x56, 0x18 }, /* AK4671_DIGITAL_VOLUME_B_CONTROL (0x56) */
{ 0x57, 0x18 }, /* AK4671_DIGITAL_VOLUME_C_CONTROL (0x57) */
{ 0x58, 0x00 }, /* AK4671_SIDETONE_VOLUME_CONTROL (0x58) */
{ 0x59, 0x00 }, /* AK4671_DIGITAL_MIXING_CONTROL2 (0x59) */
{ 0x5a, 0x00 }, /* AK4671_SAR_ADC_CONTROL (0x5a) */
};
/*
* LOUT1/ROUT1 output volume control:
* from -24 to 6 dB in 6 dB steps (mute instead of -30 dB)
*/
static DECLARE_TLV_DB_SCALE(out1_tlv, -3000, 600, 1);
/*
* LOUT2/ROUT2 output volume control:
* from -33 to 6 dB in 3 dB steps (mute instead of -33 dB)
*/
static DECLARE_TLV_DB_SCALE(out2_tlv, -3300, 300, 1);
/*
* LOUT3/ROUT3 output volume control:
* from -6 to 3 dB in 3 dB steps
*/
static DECLARE_TLV_DB_SCALE(out3_tlv, -600, 300, 0);
/*
* Mic amp gain control:
* from -15 to 30 dB in 3 dB steps
* REVISIT: The actual min value(0x01) is -12 dB and the reg value 0x00 is not
* available
*/
static DECLARE_TLV_DB_SCALE(mic_amp_tlv, -1500, 300, 0);
static const struct snd_kcontrol_new ak4671_snd_controls[] = {
/* Common playback gain controls */
SOC_SINGLE_TLV("Line Output1 Playback Volume",
AK4671_OUTPUT_VOLUME_CONTROL, 0, 0x6, 0, out1_tlv),
SOC_SINGLE_TLV("Headphone Output2 Playback Volume",
AK4671_OUTPUT_VOLUME_CONTROL, 4, 0xd, 0, out2_tlv),
SOC_SINGLE_TLV("Line Output3 Playback Volume",
AK4671_LOUT3_POWER_MANAGERMENT, 6, 0x3, 0, out3_tlv),
/* Common capture gain controls */
SOC_DOUBLE_TLV("Mic Amp Capture Volume",
AK4671_MIC_AMP_GAIN, 0, 4, 0xf, 0, mic_amp_tlv),
};
/* event handlers */
static int ak4671_out2_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(component, AK4671_LOUT2_POWER_MANAGERMENT,
AK4671_MUTEN, AK4671_MUTEN);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, AK4671_LOUT2_POWER_MANAGERMENT,
AK4671_MUTEN, 0);
break;
}
return 0;
}
/* Output Mixers */
static const struct snd_kcontrol_new ak4671_lout1_mixer_controls[] = {
SOC_DAPM_SINGLE("DACL", AK4671_LOUT1_SIGNAL_SELECT, 0, 1, 0),
SOC_DAPM_SINGLE("LINL1", AK4671_LOUT1_SIGNAL_SELECT, 1, 1, 0),
SOC_DAPM_SINGLE("LINL2", AK4671_LOUT1_SIGNAL_SELECT, 2, 1, 0),
SOC_DAPM_SINGLE("LINL3", AK4671_LOUT1_SIGNAL_SELECT, 3, 1, 0),
SOC_DAPM_SINGLE("LINL4", AK4671_LOUT1_SIGNAL_SELECT, 4, 1, 0),
SOC_DAPM_SINGLE("LOOPL", AK4671_LOUT1_SIGNAL_SELECT, 5, 1, 0),
};
static const struct snd_kcontrol_new ak4671_rout1_mixer_controls[] = {
SOC_DAPM_SINGLE("DACR", AK4671_ROUT1_SIGNAL_SELECT, 0, 1, 0),
SOC_DAPM_SINGLE("RINR1", AK4671_ROUT1_SIGNAL_SELECT, 1, 1, 0),
SOC_DAPM_SINGLE("RINR2", AK4671_ROUT1_SIGNAL_SELECT, 2, 1, 0),
SOC_DAPM_SINGLE("RINR3", AK4671_ROUT1_SIGNAL_SELECT, 3, 1, 0),
SOC_DAPM_SINGLE("RINR4", AK4671_ROUT1_SIGNAL_SELECT, 4, 1, 0),
SOC_DAPM_SINGLE("LOOPR", AK4671_ROUT1_SIGNAL_SELECT, 5, 1, 0),
};
static const struct snd_kcontrol_new ak4671_lout2_mixer_controls[] = {
SOC_DAPM_SINGLE("DACHL", AK4671_LOUT2_SIGNAL_SELECT, 0, 1, 0),
SOC_DAPM_SINGLE("LINH1", AK4671_LOUT2_SIGNAL_SELECT, 1, 1, 0),
SOC_DAPM_SINGLE("LINH2", AK4671_LOUT2_SIGNAL_SELECT, 2, 1, 0),
SOC_DAPM_SINGLE("LINH3", AK4671_LOUT2_SIGNAL_SELECT, 3, 1, 0),
SOC_DAPM_SINGLE("LINH4", AK4671_LOUT2_SIGNAL_SELECT, 4, 1, 0),
SOC_DAPM_SINGLE("LOOPHL", AK4671_LOUT2_SIGNAL_SELECT, 5, 1, 0),
};
static const struct snd_kcontrol_new ak4671_rout2_mixer_controls[] = {
SOC_DAPM_SINGLE("DACHR", AK4671_ROUT2_SIGNAL_SELECT, 0, 1, 0),
SOC_DAPM_SINGLE("RINH1", AK4671_ROUT2_SIGNAL_SELECT, 1, 1, 0),
SOC_DAPM_SINGLE("RINH2", AK4671_ROUT2_SIGNAL_SELECT, 2, 1, 0),
SOC_DAPM_SINGLE("RINH3", AK4671_ROUT2_SIGNAL_SELECT, 3, 1, 0),
SOC_DAPM_SINGLE("RINH4", AK4671_ROUT2_SIGNAL_SELECT, 4, 1, 0),
SOC_DAPM_SINGLE("LOOPHR", AK4671_ROUT2_SIGNAL_SELECT, 5, 1, 0),
};
static const struct snd_kcontrol_new ak4671_lout3_mixer_controls[] = {
SOC_DAPM_SINGLE("DACSL", AK4671_LOUT3_SIGNAL_SELECT, 0, 1, 0),
SOC_DAPM_SINGLE("LINS1", AK4671_LOUT3_SIGNAL_SELECT, 1, 1, 0),
SOC_DAPM_SINGLE("LINS2", AK4671_LOUT3_SIGNAL_SELECT, 2, 1, 0),
SOC_DAPM_SINGLE("LINS3", AK4671_LOUT3_SIGNAL_SELECT, 3, 1, 0),
SOC_DAPM_SINGLE("LINS4", AK4671_LOUT3_SIGNAL_SELECT, 4, 1, 0),
SOC_DAPM_SINGLE("LOOPSL", AK4671_LOUT3_SIGNAL_SELECT, 5, 1, 0),
};
static const struct snd_kcontrol_new ak4671_rout3_mixer_controls[] = {
SOC_DAPM_SINGLE("DACSR", AK4671_ROUT3_SIGNAL_SELECT, 0, 1, 0),
SOC_DAPM_SINGLE("RINS1", AK4671_ROUT3_SIGNAL_SELECT, 1, 1, 0),
SOC_DAPM_SINGLE("RINS2", AK4671_ROUT3_SIGNAL_SELECT, 2, 1, 0),
SOC_DAPM_SINGLE("RINS3", AK4671_ROUT3_SIGNAL_SELECT, 3, 1, 0),
SOC_DAPM_SINGLE("RINS4", AK4671_ROUT3_SIGNAL_SELECT, 4, 1, 0),
SOC_DAPM_SINGLE("LOOPSR", AK4671_ROUT3_SIGNAL_SELECT, 5, 1, 0),
};
/* Input MUXs */
static const char *ak4671_lin_mux_texts[] =
{"LIN1", "LIN2", "LIN3", "LIN4"};
static SOC_ENUM_SINGLE_DECL(ak4671_lin_mux_enum,
AK4671_MIC_SIGNAL_SELECT, 0,
ak4671_lin_mux_texts);
static const struct snd_kcontrol_new ak4671_lin_mux_control =
SOC_DAPM_ENUM("Route", ak4671_lin_mux_enum);
static const char *ak4671_rin_mux_texts[] =
{"RIN1", "RIN2", "RIN3", "RIN4"};
static SOC_ENUM_SINGLE_DECL(ak4671_rin_mux_enum,
AK4671_MIC_SIGNAL_SELECT, 2,
ak4671_rin_mux_texts);
static const struct snd_kcontrol_new ak4671_rin_mux_control =
SOC_DAPM_ENUM("Route", ak4671_rin_mux_enum);
static const struct snd_soc_dapm_widget ak4671_dapm_widgets[] = {
/* Inputs */
SND_SOC_DAPM_INPUT("LIN1"),
SND_SOC_DAPM_INPUT("RIN1"),
SND_SOC_DAPM_INPUT("LIN2"),
SND_SOC_DAPM_INPUT("RIN2"),
SND_SOC_DAPM_INPUT("LIN3"),
SND_SOC_DAPM_INPUT("RIN3"),
SND_SOC_DAPM_INPUT("LIN4"),
SND_SOC_DAPM_INPUT("RIN4"),
/* Outputs */
SND_SOC_DAPM_OUTPUT("LOUT1"),
SND_SOC_DAPM_OUTPUT("ROUT1"),
SND_SOC_DAPM_OUTPUT("LOUT2"),
SND_SOC_DAPM_OUTPUT("ROUT2"),
SND_SOC_DAPM_OUTPUT("LOUT3"),
SND_SOC_DAPM_OUTPUT("ROUT3"),
/* DAC */
SND_SOC_DAPM_DAC("DAC Left", "Left HiFi Playback",
AK4671_AD_DA_POWER_MANAGEMENT, 6, 0),
SND_SOC_DAPM_DAC("DAC Right", "Right HiFi Playback",
AK4671_AD_DA_POWER_MANAGEMENT, 7, 0),
/* ADC */
SND_SOC_DAPM_ADC("ADC Left", "Left HiFi Capture",
AK4671_AD_DA_POWER_MANAGEMENT, 4, 0),
SND_SOC_DAPM_ADC("ADC Right", "Right HiFi Capture",
AK4671_AD_DA_POWER_MANAGEMENT, 5, 0),
/* PGA */
SND_SOC_DAPM_PGA("LOUT2 Mix Amp",
AK4671_LOUT2_POWER_MANAGERMENT, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA("ROUT2 Mix Amp",
AK4671_LOUT2_POWER_MANAGERMENT, 6, 0, NULL, 0),
SND_SOC_DAPM_PGA("LIN1 Mixing Circuit",
AK4671_MIXING_POWER_MANAGEMENT1, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("RIN1 Mixing Circuit",
AK4671_MIXING_POWER_MANAGEMENT1, 1, 0, NULL, 0),
SND_SOC_DAPM_PGA("LIN2 Mixing Circuit",
AK4671_MIXING_POWER_MANAGEMENT1, 2, 0, NULL, 0),
SND_SOC_DAPM_PGA("RIN2 Mixing Circuit",
AK4671_MIXING_POWER_MANAGEMENT1, 3, 0, NULL, 0),
SND_SOC_DAPM_PGA("LIN3 Mixing Circuit",
AK4671_MIXING_POWER_MANAGEMENT1, 4, 0, NULL, 0),
SND_SOC_DAPM_PGA("RIN3 Mixing Circuit",
AK4671_MIXING_POWER_MANAGEMENT1, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA("LIN4 Mixing Circuit",
AK4671_MIXING_POWER_MANAGEMENT1, 6, 0, NULL, 0),
SND_SOC_DAPM_PGA("RIN4 Mixing Circuit",
AK4671_MIXING_POWER_MANAGEMENT1, 7, 0, NULL, 0),
/* Output Mixers */
SND_SOC_DAPM_MIXER("LOUT1 Mixer", AK4671_LOUT1_POWER_MANAGERMENT, 0, 0,
&ak4671_lout1_mixer_controls[0],
ARRAY_SIZE(ak4671_lout1_mixer_controls)),
SND_SOC_DAPM_MIXER("ROUT1 Mixer", AK4671_LOUT1_POWER_MANAGERMENT, 1, 0,
&ak4671_rout1_mixer_controls[0],
ARRAY_SIZE(ak4671_rout1_mixer_controls)),
SND_SOC_DAPM_MIXER_E("LOUT2 Mixer", AK4671_LOUT2_POWER_MANAGERMENT,
0, 0, &ak4671_lout2_mixer_controls[0],
ARRAY_SIZE(ak4671_lout2_mixer_controls),
ak4671_out2_event,
SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_MIXER_E("ROUT2 Mixer", AK4671_LOUT2_POWER_MANAGERMENT,
1, 0, &ak4671_rout2_mixer_controls[0],
ARRAY_SIZE(ak4671_rout2_mixer_controls),
ak4671_out2_event,
SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_MIXER("LOUT3 Mixer", AK4671_LOUT3_POWER_MANAGERMENT, 0, 0,
&ak4671_lout3_mixer_controls[0],
ARRAY_SIZE(ak4671_lout3_mixer_controls)),
SND_SOC_DAPM_MIXER("ROUT3 Mixer", AK4671_LOUT3_POWER_MANAGERMENT, 1, 0,
&ak4671_rout3_mixer_controls[0],
ARRAY_SIZE(ak4671_rout3_mixer_controls)),
/* Input MUXs */
SND_SOC_DAPM_MUX("LIN MUX", AK4671_AD_DA_POWER_MANAGEMENT, 2, 0,
&ak4671_lin_mux_control),
SND_SOC_DAPM_MUX("RIN MUX", AK4671_AD_DA_POWER_MANAGEMENT, 3, 0,
&ak4671_rin_mux_control),
/* Mic Power */
SND_SOC_DAPM_MICBIAS("Mic Bias", AK4671_AD_DA_POWER_MANAGEMENT, 1, 0),
/* Supply */
SND_SOC_DAPM_SUPPLY("PMPLL", AK4671_PLL_MODE_SELECT1, 0, 0, NULL, 0),
};
static const struct snd_soc_dapm_route ak4671_intercon[] = {
{"DAC Left", NULL, "PMPLL"},
{"DAC Right", NULL, "PMPLL"},
{"ADC Left", NULL, "PMPLL"},
{"ADC Right", NULL, "PMPLL"},
/* Outputs */
{"LOUT1", NULL, "LOUT1 Mixer"},
{"ROUT1", NULL, "ROUT1 Mixer"},
{"LOUT2", NULL, "LOUT2 Mix Amp"},
{"ROUT2", NULL, "ROUT2 Mix Amp"},
{"LOUT3", NULL, "LOUT3 Mixer"},
{"ROUT3", NULL, "ROUT3 Mixer"},
{"LOUT1 Mixer", "DACL", "DAC Left"},
{"ROUT1 Mixer", "DACR", "DAC Right"},
{"LOUT2 Mixer", "DACHL", "DAC Left"},
{"ROUT2 Mixer", "DACHR", "DAC Right"},
{"LOUT2 Mix Amp", NULL, "LOUT2 Mixer"},
{"ROUT2 Mix Amp", NULL, "ROUT2 Mixer"},
{"LOUT3 Mixer", "DACSL", "DAC Left"},
{"ROUT3 Mixer", "DACSR", "DAC Right"},
/* Inputs */
{"LIN MUX", "LIN1", "LIN1"},
{"LIN MUX", "LIN2", "LIN2"},
{"LIN MUX", "LIN3", "LIN3"},
{"LIN MUX", "LIN4", "LIN4"},
{"RIN MUX", "RIN1", "RIN1"},
{"RIN MUX", "RIN2", "RIN2"},
{"RIN MUX", "RIN3", "RIN3"},
{"RIN MUX", "RIN4", "RIN4"},
{"LIN1", NULL, "Mic Bias"},
{"RIN1", NULL, "Mic Bias"},
{"LIN2", NULL, "Mic Bias"},
{"RIN2", NULL, "Mic Bias"},
{"ADC Left", NULL, "LIN MUX"},
{"ADC Right", NULL, "RIN MUX"},
/* Analog Loops */
{"LIN1 Mixing Circuit", NULL, "LIN1"},
{"RIN1 Mixing Circuit", NULL, "RIN1"},
{"LIN2 Mixing Circuit", NULL, "LIN2"},
{"RIN2 Mixing Circuit", NULL, "RIN2"},
{"LIN3 Mixing Circuit", NULL, "LIN3"},
{"RIN3 Mixing Circuit", NULL, "RIN3"},
{"LIN4 Mixing Circuit", NULL, "LIN4"},
{"RIN4 Mixing Circuit", NULL, "RIN4"},
{"LOUT1 Mixer", "LINL1", "LIN1 Mixing Circuit"},
{"ROUT1 Mixer", "RINR1", "RIN1 Mixing Circuit"},
{"LOUT2 Mixer", "LINH1", "LIN1 Mixing Circuit"},
{"ROUT2 Mixer", "RINH1", "RIN1 Mixing Circuit"},
{"LOUT3 Mixer", "LINS1", "LIN1 Mixing Circuit"},
{"ROUT3 Mixer", "RINS1", "RIN1 Mixing Circuit"},
{"LOUT1 Mixer", "LINL2", "LIN2 Mixing Circuit"},
{"ROUT1 Mixer", "RINR2", "RIN2 Mixing Circuit"},
{"LOUT2 Mixer", "LINH2", "LIN2 Mixing Circuit"},
{"ROUT2 Mixer", "RINH2", "RIN2 Mixing Circuit"},
{"LOUT3 Mixer", "LINS2", "LIN2 Mixing Circuit"},
{"ROUT3 Mixer", "RINS2", "RIN2 Mixing Circuit"},
{"LOUT1 Mixer", "LINL3", "LIN3 Mixing Circuit"},
{"ROUT1 Mixer", "RINR3", "RIN3 Mixing Circuit"},
{"LOUT2 Mixer", "LINH3", "LIN3 Mixing Circuit"},
{"ROUT2 Mixer", "RINH3", "RIN3 Mixing Circuit"},
{"LOUT3 Mixer", "LINS3", "LIN3 Mixing Circuit"},
{"ROUT3 Mixer", "RINS3", "RIN3 Mixing Circuit"},
{"LOUT1 Mixer", "LINL4", "LIN4 Mixing Circuit"},
{"ROUT1 Mixer", "RINR4", "RIN4 Mixing Circuit"},
{"LOUT2 Mixer", "LINH4", "LIN4 Mixing Circuit"},
{"ROUT2 Mixer", "RINH4", "RIN4 Mixing Circuit"},
{"LOUT3 Mixer", "LINS4", "LIN4 Mixing Circuit"},
{"ROUT3 Mixer", "RINS4", "RIN4 Mixing Circuit"},
};
static int ak4671_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
u8 fs;
fs = snd_soc_component_read(component, AK4671_PLL_MODE_SELECT0);
fs &= ~AK4671_FS;
switch (params_rate(params)) {
case 8000:
fs |= AK4671_FS_8KHZ;
break;
case 12000:
fs |= AK4671_FS_12KHZ;
break;
case 16000:
fs |= AK4671_FS_16KHZ;
break;
case 24000:
fs |= AK4671_FS_24KHZ;
break;
case 11025:
fs |= AK4671_FS_11_025KHZ;
break;
case 22050:
fs |= AK4671_FS_22_05KHZ;
break;
case 32000:
fs |= AK4671_FS_32KHZ;
break;
case 44100:
fs |= AK4671_FS_44_1KHZ;
break;
case 48000:
fs |= AK4671_FS_48KHZ;
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, AK4671_PLL_MODE_SELECT0, fs);
return 0;
}
static int ak4671_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
u8 pll;
pll = snd_soc_component_read(component, AK4671_PLL_MODE_SELECT0);
pll &= ~AK4671_PLL;
switch (freq) {
case 11289600:
pll |= AK4671_PLL_11_2896MHZ;
break;
case 12000000:
pll |= AK4671_PLL_12MHZ;
break;
case 12288000:
pll |= AK4671_PLL_12_288MHZ;
break;
case 13000000:
pll |= AK4671_PLL_13MHZ;
break;
case 13500000:
pll |= AK4671_PLL_13_5MHZ;
break;
case 19200000:
pll |= AK4671_PLL_19_2MHZ;
break;
case 24000000:
pll |= AK4671_PLL_24MHZ;
break;
case 26000000:
pll |= AK4671_PLL_26MHZ;
break;
case 27000000:
pll |= AK4671_PLL_27MHZ;
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, AK4671_PLL_MODE_SELECT0, pll);
return 0;
}
static int ak4671_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
u8 mode;
u8 format;
/* set master/slave audio interface */
mode = snd_soc_component_read(component, AK4671_PLL_MODE_SELECT1);
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
mode |= AK4671_M_S;
break;
case SND_SOC_DAIFMT_CBP_CFC:
mode &= ~(AK4671_M_S);
break;
default:
return -EINVAL;
}
/* interface format */
format = snd_soc_component_read(component, AK4671_FORMAT_SELECT);
format &= ~AK4671_DIF;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
format |= AK4671_DIF_I2S_MODE;
break;
case SND_SOC_DAIFMT_LEFT_J:
format |= AK4671_DIF_MSB_MODE;
break;
case SND_SOC_DAIFMT_DSP_A:
format |= AK4671_DIF_DSP_MODE;
format |= AK4671_BCKP;
format |= AK4671_MSBS;
break;
default:
return -EINVAL;
}
/* set mode and format */
snd_soc_component_write(component, AK4671_PLL_MODE_SELECT1, mode);
snd_soc_component_write(component, AK4671_FORMAT_SELECT, format);
return 0;
}
static int ak4671_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
switch (level) {
case SND_SOC_BIAS_ON:
case SND_SOC_BIAS_PREPARE:
case SND_SOC_BIAS_STANDBY:
snd_soc_component_update_bits(component, AK4671_AD_DA_POWER_MANAGEMENT,
AK4671_PMVCM, AK4671_PMVCM);
break;
case SND_SOC_BIAS_OFF:
snd_soc_component_write(component, AK4671_AD_DA_POWER_MANAGEMENT, 0x00);
break;
}
return 0;
}
#define AK4671_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\
SNDRV_PCM_RATE_48000)
#define AK4671_FORMATS SNDRV_PCM_FMTBIT_S16_LE
static const struct snd_soc_dai_ops ak4671_dai_ops = {
.hw_params = ak4671_hw_params,
.set_sysclk = ak4671_set_dai_sysclk,
.set_fmt = ak4671_set_dai_fmt,
};
static struct snd_soc_dai_driver ak4671_dai = {
.name = "ak4671-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = AK4671_RATES,
.formats = AK4671_FORMATS,},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = AK4671_RATES,
.formats = AK4671_FORMATS,},
.ops = &ak4671_dai_ops,
};
static const struct snd_soc_component_driver soc_component_dev_ak4671 = {
.set_bias_level = ak4671_set_bias_level,
.controls = ak4671_snd_controls,
.num_controls = ARRAY_SIZE(ak4671_snd_controls),
.dapm_widgets = ak4671_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(ak4671_dapm_widgets),
.dapm_routes = ak4671_intercon,
.num_dapm_routes = ARRAY_SIZE(ak4671_intercon),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config ak4671_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = AK4671_SAR_ADC_CONTROL,
.reg_defaults = ak4671_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(ak4671_reg_defaults),
.cache_type = REGCACHE_RBTREE,
};
static int ak4671_i2c_probe(struct i2c_client *client)
{
struct regmap *regmap;
int ret;
regmap = devm_regmap_init_i2c(client, &ak4671_regmap);
if (IS_ERR(regmap)) {
ret = PTR_ERR(regmap);
dev_err(&client->dev, "Failed to create regmap: %d\n", ret);
return ret;
}
ret = devm_snd_soc_register_component(&client->dev,
&soc_component_dev_ak4671, &ak4671_dai, 1);
return ret;
}
static const struct i2c_device_id ak4671_i2c_id[] = {
{ "ak4671", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, ak4671_i2c_id);
static struct i2c_driver ak4671_i2c_driver = {
.driver = {
.name = "ak4671-codec",
},
.probe = ak4671_i2c_probe,
.id_table = ak4671_i2c_id,
};
module_i2c_driver(ak4671_i2c_driver);
MODULE_DESCRIPTION("ASoC AK4671 codec driver");
MODULE_AUTHOR("Joonyoung Shim <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/ak4671.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* max98371.c -- ALSA SoC Stereo MAX98371 driver
*
* Copyright 2015-16 Maxim Integrated Products
*/
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include "max98371.h"
static const char *const monomix_text[] = {
"Left", "Right", "LeftRightDiv2",
};
static const char *const hpf_cutoff_txt[] = {
"Disable", "DC Block", "50Hz",
"100Hz", "200Hz", "400Hz", "800Hz",
};
static SOC_ENUM_SINGLE_DECL(max98371_monomix, MAX98371_MONOMIX_CFG, 0,
monomix_text);
static SOC_ENUM_SINGLE_DECL(max98371_hpf_cutoff, MAX98371_HPF, 0,
hpf_cutoff_txt);
static const DECLARE_TLV_DB_RANGE(max98371_dht_min_gain,
0, 1, TLV_DB_SCALE_ITEM(537, 66, 0),
2, 3, TLV_DB_SCALE_ITEM(677, 82, 0),
4, 5, TLV_DB_SCALE_ITEM(852, 104, 0),
6, 7, TLV_DB_SCALE_ITEM(1072, 131, 0),
8, 9, TLV_DB_SCALE_ITEM(1350, 165, 0),
10, 11, TLV_DB_SCALE_ITEM(1699, 101, 0),
);
static const DECLARE_TLV_DB_RANGE(max98371_dht_max_gain,
0, 1, TLV_DB_SCALE_ITEM(537, 66, 0),
2, 3, TLV_DB_SCALE_ITEM(677, 82, 0),
4, 5, TLV_DB_SCALE_ITEM(852, 104, 0),
6, 7, TLV_DB_SCALE_ITEM(1072, 131, 0),
8, 9, TLV_DB_SCALE_ITEM(1350, 165, 0),
10, 11, TLV_DB_SCALE_ITEM(1699, 208, 0),
);
static const DECLARE_TLV_DB_RANGE(max98371_dht_rot_gain,
0, 1, TLV_DB_SCALE_ITEM(-50, -50, 0),
2, 6, TLV_DB_SCALE_ITEM(-100, -100, 0),
7, 8, TLV_DB_SCALE_ITEM(-800, -200, 0),
9, 11, TLV_DB_SCALE_ITEM(-1200, -300, 0),
12, 13, TLV_DB_SCALE_ITEM(-2000, -200, 0),
14, 15, TLV_DB_SCALE_ITEM(-2500, -500, 0),
);
static const struct reg_default max98371_reg[] = {
{ 0x01, 0x00 },
{ 0x02, 0x00 },
{ 0x03, 0x00 },
{ 0x04, 0x00 },
{ 0x05, 0x00 },
{ 0x06, 0x00 },
{ 0x07, 0x00 },
{ 0x08, 0x00 },
{ 0x09, 0x00 },
{ 0x0A, 0x00 },
{ 0x10, 0x06 },
{ 0x11, 0x08 },
{ 0x14, 0x80 },
{ 0x15, 0x00 },
{ 0x16, 0x00 },
{ 0x18, 0x00 },
{ 0x19, 0x00 },
{ 0x1C, 0x00 },
{ 0x1D, 0x00 },
{ 0x1E, 0x00 },
{ 0x1F, 0x00 },
{ 0x20, 0x00 },
{ 0x21, 0x00 },
{ 0x22, 0x00 },
{ 0x23, 0x00 },
{ 0x24, 0x00 },
{ 0x25, 0x00 },
{ 0x26, 0x00 },
{ 0x27, 0x00 },
{ 0x28, 0x00 },
{ 0x29, 0x00 },
{ 0x2A, 0x00 },
{ 0x2B, 0x00 },
{ 0x2C, 0x00 },
{ 0x2D, 0x00 },
{ 0x2E, 0x0B },
{ 0x31, 0x00 },
{ 0x32, 0x18 },
{ 0x33, 0x00 },
{ 0x34, 0x00 },
{ 0x36, 0x00 },
{ 0x37, 0x00 },
{ 0x38, 0x00 },
{ 0x39, 0x00 },
{ 0x3A, 0x00 },
{ 0x3B, 0x00 },
{ 0x3C, 0x00 },
{ 0x3D, 0x00 },
{ 0x3E, 0x00 },
{ 0x3F, 0x00 },
{ 0x40, 0x00 },
{ 0x41, 0x00 },
{ 0x42, 0x00 },
{ 0x43, 0x00 },
{ 0x4A, 0x00 },
{ 0x4B, 0x00 },
{ 0x4C, 0x00 },
{ 0x4D, 0x00 },
{ 0x4E, 0x00 },
{ 0x50, 0x00 },
{ 0x51, 0x00 },
{ 0x55, 0x00 },
{ 0x58, 0x00 },
{ 0x59, 0x00 },
{ 0x5C, 0x00 },
{ 0xFF, 0x43 },
};
static bool max98371_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX98371_IRQ_CLEAR1:
case MAX98371_IRQ_CLEAR2:
case MAX98371_IRQ_CLEAR3:
case MAX98371_VERSION:
return true;
default:
return false;
}
}
static bool max98371_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX98371_SOFT_RESET:
return false;
default:
return true;
}
};
static const DECLARE_TLV_DB_RANGE(max98371_gain_tlv,
0, 7, TLV_DB_SCALE_ITEM(0, 50, 0),
8, 10, TLV_DB_SCALE_ITEM(400, 100, 0)
);
static const DECLARE_TLV_DB_SCALE(digital_tlv, -6300, 50, 1);
static const struct snd_kcontrol_new max98371_snd_controls[] = {
SOC_SINGLE_TLV("Speaker Volume", MAX98371_GAIN,
MAX98371_GAIN_SHIFT, (1<<MAX98371_GAIN_WIDTH)-1, 0,
max98371_gain_tlv),
SOC_SINGLE_TLV("Digital Volume", MAX98371_DIGITAL_GAIN, 0,
(1<<MAX98371_DIGITAL_GAIN_WIDTH)-1, 1, digital_tlv),
SOC_SINGLE_TLV("Speaker DHT Max Volume", MAX98371_GAIN,
0, (1<<MAX98371_DHT_MAX_WIDTH)-1, 0,
max98371_dht_max_gain),
SOC_SINGLE_TLV("Speaker DHT Min Volume", MAX98371_DHT_GAIN,
0, (1<<MAX98371_DHT_GAIN_WIDTH)-1, 0,
max98371_dht_min_gain),
SOC_SINGLE_TLV("Speaker DHT Rotation Volume", MAX98371_DHT_GAIN,
0, (1<<MAX98371_DHT_ROT_WIDTH)-1, 0,
max98371_dht_rot_gain),
SOC_SINGLE("DHT Attack Step", MAX98371_DHT, MAX98371_DHT_STEP, 3, 0),
SOC_SINGLE("DHT Attack Rate", MAX98371_DHT, 0, 7, 0),
SOC_ENUM("Monomix Select", max98371_monomix),
SOC_ENUM("HPF Cutoff", max98371_hpf_cutoff),
};
static int max98371_dai_set_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct max98371_priv *max98371 = snd_soc_component_get_drvdata(component);
unsigned int val = 0;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC:
break;
default:
dev_err(component->dev, "DAI clock mode unsupported");
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
val |= 0;
break;
case SND_SOC_DAIFMT_RIGHT_J:
val |= MAX98371_DAI_RIGHT;
break;
case SND_SOC_DAIFMT_LEFT_J:
val |= MAX98371_DAI_LEFT;
break;
default:
dev_err(component->dev, "DAI wrong mode unsupported");
return -EINVAL;
}
regmap_update_bits(max98371->regmap, MAX98371_FMT,
MAX98371_FMT_MODE_MASK, val);
return 0;
}
static int max98371_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct max98371_priv *max98371 = snd_soc_component_get_drvdata(component);
int blr_clk_ratio, ch_size, channels = params_channels(params);
int rate = params_rate(params);
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S8:
regmap_update_bits(max98371->regmap, MAX98371_FMT,
MAX98371_FMT_MASK, MAX98371_DAI_CHANSZ_16);
ch_size = 8;
break;
case SNDRV_PCM_FORMAT_S16_LE:
regmap_update_bits(max98371->regmap, MAX98371_FMT,
MAX98371_FMT_MASK, MAX98371_DAI_CHANSZ_16);
ch_size = 16;
break;
case SNDRV_PCM_FORMAT_S24_LE:
regmap_update_bits(max98371->regmap, MAX98371_FMT,
MAX98371_FMT_MASK, MAX98371_DAI_CHANSZ_32);
ch_size = 24;
break;
case SNDRV_PCM_FORMAT_S32_LE:
regmap_update_bits(max98371->regmap, MAX98371_FMT,
MAX98371_FMT_MASK, MAX98371_DAI_CHANSZ_32);
ch_size = 32;
break;
default:
return -EINVAL;
}
/* BCLK/LRCLK ratio calculation */
blr_clk_ratio = channels * ch_size;
switch (blr_clk_ratio) {
case 32:
regmap_update_bits(max98371->regmap,
MAX98371_DAI_CLK,
MAX98371_DAI_BSEL_MASK, MAX98371_DAI_BSEL_32);
break;
case 48:
regmap_update_bits(max98371->regmap,
MAX98371_DAI_CLK,
MAX98371_DAI_BSEL_MASK, MAX98371_DAI_BSEL_48);
break;
case 64:
regmap_update_bits(max98371->regmap,
MAX98371_DAI_CLK,
MAX98371_DAI_BSEL_MASK, MAX98371_DAI_BSEL_64);
break;
default:
return -EINVAL;
}
switch (rate) {
case 32000:
regmap_update_bits(max98371->regmap,
MAX98371_SPK_SR,
MAX98371_SPK_SR_MASK, MAX98371_SPK_SR_32);
break;
case 44100:
regmap_update_bits(max98371->regmap,
MAX98371_SPK_SR,
MAX98371_SPK_SR_MASK, MAX98371_SPK_SR_44);
break;
case 48000:
regmap_update_bits(max98371->regmap,
MAX98371_SPK_SR,
MAX98371_SPK_SR_MASK, MAX98371_SPK_SR_48);
break;
case 88200:
regmap_update_bits(max98371->regmap,
MAX98371_SPK_SR,
MAX98371_SPK_SR_MASK, MAX98371_SPK_SR_88);
break;
case 96000:
regmap_update_bits(max98371->regmap,
MAX98371_SPK_SR,
MAX98371_SPK_SR_MASK, MAX98371_SPK_SR_96);
break;
default:
return -EINVAL;
}
/* enabling both the RX channels*/
regmap_update_bits(max98371->regmap, MAX98371_MONOMIX_SRC,
MAX98371_MONOMIX_SRC_MASK, MONOMIX_RX_0_1);
regmap_update_bits(max98371->regmap, MAX98371_DAI_CHANNEL,
MAX98371_CHANNEL_MASK, MAX98371_CHANNEL_MASK);
return 0;
}
static const struct snd_soc_dapm_widget max98371_dapm_widgets[] = {
SND_SOC_DAPM_DAC("DAC", NULL, MAX98371_SPK_ENABLE, 0, 0),
SND_SOC_DAPM_SUPPLY("Global Enable", MAX98371_GLOBAL_ENABLE,
0, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("SPK_OUT"),
};
static const struct snd_soc_dapm_route max98371_audio_map[] = {
{"DAC", NULL, "HiFi Playback"},
{"SPK_OUT", NULL, "DAC"},
{"SPK_OUT", NULL, "Global Enable"},
};
#define MAX98371_RATES SNDRV_PCM_RATE_8000_48000
#define MAX98371_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
SNDRV_PCM_FMTBIT_S24_BE | SNDRV_PCM_FMTBIT_S32_BE)
static const struct snd_soc_dai_ops max98371_dai_ops = {
.set_fmt = max98371_dai_set_fmt,
.hw_params = max98371_dai_hw_params,
};
static struct snd_soc_dai_driver max98371_dai[] = {
{
.name = "max98371-aif1",
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = MAX98371_FORMATS,
},
.ops = &max98371_dai_ops,
}
};
static const struct snd_soc_component_driver max98371_component = {
.controls = max98371_snd_controls,
.num_controls = ARRAY_SIZE(max98371_snd_controls),
.dapm_routes = max98371_audio_map,
.num_dapm_routes = ARRAY_SIZE(max98371_audio_map),
.dapm_widgets = max98371_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(max98371_dapm_widgets),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config max98371_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = MAX98371_VERSION,
.reg_defaults = max98371_reg,
.num_reg_defaults = ARRAY_SIZE(max98371_reg),
.volatile_reg = max98371_volatile_register,
.readable_reg = max98371_readable_register,
.cache_type = REGCACHE_RBTREE,
};
static int max98371_i2c_probe(struct i2c_client *i2c)
{
struct max98371_priv *max98371;
int ret, reg;
max98371 = devm_kzalloc(&i2c->dev,
sizeof(*max98371), GFP_KERNEL);
if (!max98371)
return -ENOMEM;
i2c_set_clientdata(i2c, max98371);
max98371->regmap = devm_regmap_init_i2c(i2c, &max98371_regmap);
if (IS_ERR(max98371->regmap)) {
ret = PTR_ERR(max98371->regmap);
dev_err(&i2c->dev,
"Failed to allocate regmap: %d\n", ret);
return ret;
}
ret = regmap_read(max98371->regmap, MAX98371_VERSION, ®);
if (ret < 0) {
dev_info(&i2c->dev, "device error %d\n", ret);
return ret;
}
dev_info(&i2c->dev, "device version %x\n", reg);
ret = devm_snd_soc_register_component(&i2c->dev, &max98371_component,
max98371_dai, ARRAY_SIZE(max98371_dai));
if (ret < 0) {
dev_err(&i2c->dev, "Failed to register component: %d\n", ret);
return ret;
}
return ret;
}
static const struct i2c_device_id max98371_i2c_id[] = {
{ "max98371", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, max98371_i2c_id);
#ifdef CONFIG_OF
static const struct of_device_id max98371_of_match[] = {
{ .compatible = "maxim,max98371", },
{ }
};
MODULE_DEVICE_TABLE(of, max98371_of_match);
#endif
static struct i2c_driver max98371_i2c_driver = {
.driver = {
.name = "max98371",
.of_match_table = of_match_ptr(max98371_of_match),
},
.probe = max98371_i2c_probe,
.id_table = max98371_i2c_id,
};
module_i2c_driver(max98371_i2c_driver);
MODULE_AUTHOR("anish kumar <[email protected]>");
MODULE_DESCRIPTION("ALSA SoC MAX98371 driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/max98371.c |
// SPDX-License-Identifier: GPL-2.0
//
// IDT821034 ALSA SoC driver
//
// Copyright 2022 CS GROUP France
//
// Author: Herve Codina <[email protected]>
#include <linux/bitrev.h>
#include <linux/gpio/driver.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/spi/spi.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#define IDT821034_NB_CHANNEL 4
struct idt821034_amp {
u16 gain;
bool is_muted;
};
struct idt821034 {
struct spi_device *spi;
struct mutex mutex;
u8 spi_tx_buf; /* Cannot use stack area for SPI (dma-safe memory) */
u8 spi_rx_buf; /* Cannot use stack area for SPI (dma-safe memory) */
struct {
u8 codec_conf;
struct {
u8 power;
u8 tx_slot;
u8 rx_slot;
u8 slic_conf;
u8 slic_control;
} ch[IDT821034_NB_CHANNEL];
} cache;
struct {
struct {
struct idt821034_amp amp_out;
struct idt821034_amp amp_in;
} ch[IDT821034_NB_CHANNEL];
} amps;
int max_ch_playback;
int max_ch_capture;
struct gpio_chip gpio_chip;
};
static int idt821034_8bit_write(struct idt821034 *idt821034, u8 val)
{
struct spi_transfer xfer[] = {
{
.tx_buf = &idt821034->spi_tx_buf,
.len = 1,
}, {
.cs_off = 1,
.tx_buf = &idt821034->spi_tx_buf,
.len = 1,
}
};
idt821034->spi_tx_buf = val;
dev_vdbg(&idt821034->spi->dev, "spi xfer wr 0x%x\n", val);
return spi_sync_transfer(idt821034->spi, xfer, 2);
}
static int idt821034_2x8bit_write(struct idt821034 *idt821034, u8 val1, u8 val2)
{
int ret;
ret = idt821034_8bit_write(idt821034, val1);
if (ret)
return ret;
return idt821034_8bit_write(idt821034, val2);
}
static int idt821034_8bit_read(struct idt821034 *idt821034, u8 valw, u8 *valr)
{
struct spi_transfer xfer[] = {
{
.tx_buf = &idt821034->spi_tx_buf,
.rx_buf = &idt821034->spi_rx_buf,
.len = 1,
}, {
.cs_off = 1,
.tx_buf = &idt821034->spi_tx_buf,
.len = 1,
}
};
int ret;
idt821034->spi_tx_buf = valw;
ret = spi_sync_transfer(idt821034->spi, xfer, 2);
if (ret)
return ret;
*valr = idt821034->spi_rx_buf;
dev_vdbg(&idt821034->spi->dev, "spi xfer wr 0x%x, rd 0x%x\n",
valw, *valr);
return 0;
}
/* Available mode for the programming sequence */
#define IDT821034_MODE_CODEC(_ch) (0x80 | ((_ch) << 2))
#define IDT821034_MODE_SLIC(_ch) (0xD0 | ((_ch) << 2))
#define IDT821034_MODE_GAIN(_ch) (0xC0 | ((_ch) << 2))
/* Power values that can be used in 'power' (can be ORed) */
#define IDT821034_CONF_PWRUP_TX BIT(1) /* from analog input to PCM */
#define IDT821034_CONF_PWRUP_RX BIT(0) /* from PCM to analog output */
static int idt821034_set_channel_power(struct idt821034 *idt821034, u8 ch, u8 power)
{
u8 conf;
int ret;
dev_dbg(&idt821034->spi->dev, "set_channel_power(%u, 0x%x)\n", ch, power);
conf = IDT821034_MODE_CODEC(ch) | idt821034->cache.codec_conf;
if (power & IDT821034_CONF_PWRUP_RX) {
ret = idt821034_2x8bit_write(idt821034,
conf | IDT821034_CONF_PWRUP_RX,
idt821034->cache.ch[ch].rx_slot);
if (ret)
return ret;
}
if (power & IDT821034_CONF_PWRUP_TX) {
ret = idt821034_2x8bit_write(idt821034,
conf | IDT821034_CONF_PWRUP_TX,
idt821034->cache.ch[ch].tx_slot);
if (ret)
return ret;
}
if (!(power & (IDT821034_CONF_PWRUP_TX | IDT821034_CONF_PWRUP_RX))) {
ret = idt821034_2x8bit_write(idt821034, conf, 0);
if (ret)
return ret;
}
idt821034->cache.ch[ch].power = power;
return 0;
}
static u8 idt821034_get_channel_power(struct idt821034 *idt821034, u8 ch)
{
return idt821034->cache.ch[ch].power;
}
/* Codec configuration values that can be used in 'codec_conf' (can be ORed) */
#define IDT821034_CONF_ALAW_MODE BIT(5)
#define IDT821034_CONF_DELAY_MODE BIT(4)
static int idt821034_set_codec_conf(struct idt821034 *idt821034, u8 codec_conf)
{
u8 conf;
u8 ts;
int ret;
dev_dbg(&idt821034->spi->dev, "set_codec_conf(0x%x)\n", codec_conf);
/* codec conf fields are common to all channel.
* Arbitrary use of channel 0 for this configuration.
*/
/* Set Configuration Register */
conf = IDT821034_MODE_CODEC(0) | codec_conf;
/* Update conf value and timeslot register value according
* to cache values
*/
if (idt821034->cache.ch[0].power & IDT821034_CONF_PWRUP_RX) {
conf |= IDT821034_CONF_PWRUP_RX;
ts = idt821034->cache.ch[0].rx_slot;
} else if (idt821034->cache.ch[0].power & IDT821034_CONF_PWRUP_TX) {
conf |= IDT821034_CONF_PWRUP_TX;
ts = idt821034->cache.ch[0].tx_slot;
} else {
ts = 0x00;
}
/* Write configuration register and time-slot register */
ret = idt821034_2x8bit_write(idt821034, conf, ts);
if (ret)
return ret;
idt821034->cache.codec_conf = codec_conf;
return 0;
}
static u8 idt821034_get_codec_conf(struct idt821034 *idt821034)
{
return idt821034->cache.codec_conf;
}
/* Channel direction values that can be used in 'ch_dir' (can be ORed) */
#define IDT821034_CH_RX BIT(0) /* from PCM to analog output */
#define IDT821034_CH_TX BIT(1) /* from analog input to PCM */
static int idt821034_set_channel_ts(struct idt821034 *idt821034, u8 ch, u8 ch_dir, u8 ts_num)
{
u8 conf;
int ret;
dev_dbg(&idt821034->spi->dev, "set_channel_ts(%u, 0x%x, %d)\n", ch, ch_dir, ts_num);
conf = IDT821034_MODE_CODEC(ch) | idt821034->cache.codec_conf;
if (ch_dir & IDT821034_CH_RX) {
if (idt821034->cache.ch[ch].power & IDT821034_CONF_PWRUP_RX) {
ret = idt821034_2x8bit_write(idt821034,
conf | IDT821034_CONF_PWRUP_RX,
ts_num);
if (ret)
return ret;
}
idt821034->cache.ch[ch].rx_slot = ts_num;
}
if (ch_dir & IDT821034_CH_TX) {
if (idt821034->cache.ch[ch].power & IDT821034_CONF_PWRUP_TX) {
ret = idt821034_2x8bit_write(idt821034,
conf | IDT821034_CONF_PWRUP_TX,
ts_num);
if (ret)
return ret;
}
idt821034->cache.ch[ch].tx_slot = ts_num;
}
return 0;
}
/* SLIC direction values that can be used in 'slic_dir' (can be ORed) */
#define IDT821034_SLIC_IO1_IN BIT(1)
#define IDT821034_SLIC_IO0_IN BIT(0)
static int idt821034_set_slic_conf(struct idt821034 *idt821034, u8 ch, u8 slic_dir)
{
u8 conf;
int ret;
dev_dbg(&idt821034->spi->dev, "set_slic_conf(%u, 0x%x)\n", ch, slic_dir);
conf = IDT821034_MODE_SLIC(ch) | slic_dir;
ret = idt821034_2x8bit_write(idt821034, conf, idt821034->cache.ch[ch].slic_control);
if (ret)
return ret;
idt821034->cache.ch[ch].slic_conf = slic_dir;
return 0;
}
static u8 idt821034_get_slic_conf(struct idt821034 *idt821034, u8 ch)
{
return idt821034->cache.ch[ch].slic_conf;
}
static int idt821034_write_slic_raw(struct idt821034 *idt821034, u8 ch, u8 slic_raw)
{
u8 conf;
int ret;
dev_dbg(&idt821034->spi->dev, "write_slic_raw(%u, 0x%x)\n", ch, slic_raw);
/*
* On write, slic_raw is mapped as follow :
* b4: O_4
* b3: O_3
* b2: O_2
* b1: I/O_1
* b0: I/O_0
*/
conf = IDT821034_MODE_SLIC(ch) | idt821034->cache.ch[ch].slic_conf;
ret = idt821034_2x8bit_write(idt821034, conf, slic_raw);
if (ret)
return ret;
idt821034->cache.ch[ch].slic_control = slic_raw;
return 0;
}
static u8 idt821034_get_written_slic_raw(struct idt821034 *idt821034, u8 ch)
{
return idt821034->cache.ch[ch].slic_control;
}
static int idt821034_read_slic_raw(struct idt821034 *idt821034, u8 ch, u8 *slic_raw)
{
u8 val;
int ret;
/*
* On read, slic_raw is mapped as follow :
* b7: I/O_0
* b6: I/O_1
* b5: O_2
* b4: O_3
* b3: O_4
* b2: I/O1_0, I/O_0 from channel 1 (no matter ch value)
* b1: I/O2_0, I/O_0 from channel 2 (no matter ch value)
* b2: I/O3_0, I/O_0 from channel 3 (no matter ch value)
*/
val = IDT821034_MODE_SLIC(ch) | idt821034->cache.ch[ch].slic_conf;
ret = idt821034_8bit_write(idt821034, val);
if (ret)
return ret;
ret = idt821034_8bit_read(idt821034, idt821034->cache.ch[ch].slic_control, slic_raw);
if (ret)
return ret;
dev_dbg(&idt821034->spi->dev, "read_slic_raw(%i) 0x%x\n", ch, *slic_raw);
return 0;
}
/* Gain type values that can be used in 'gain_type' (cannot be ORed) */
#define IDT821034_GAIN_RX (0 << 1) /* from PCM to analog output */
#define IDT821034_GAIN_TX (1 << 1) /* from analog input to PCM */
static int idt821034_set_gain_channel(struct idt821034 *idt821034, u8 ch,
u8 gain_type, u16 gain_val)
{
u8 conf;
int ret;
dev_dbg(&idt821034->spi->dev, "set_gain_channel(%u, 0x%x, 0x%x-%d)\n",
ch, gain_type, gain_val, gain_val);
/*
* The gain programming coefficients should be calculated as:
* Transmit : Coeff_X = round [ gain_X0dB × gain_X ]
* Receive: Coeff_R = round [ gain_R0dB × gain_R ]
* where:
* gain_X0dB = 1820;
* gain_X is the target gain;
* Coeff_X should be in the range of 0 to 8192.
* gain_R0dB = 2506;
* gain_R is the target gain;
* Coeff_R should be in the range of 0 to 8192.
*
* A gain programming coefficient is 14-bit wide and in binary format.
* The 7 Most Significant Bits of the coefficient is called
* GA_MSB_Transmit for transmit path, or is called GA_MSB_Receive for
* receive path; The 7 Least Significant Bits of the coefficient is
* called GA_LSB_ Transmit for transmit path, or is called
* GA_LSB_Receive for receive path.
*
* An example is given below to clarify the calculation of the
* coefficient. To program a +3 dB gain in transmit path and a -3.5 dB
* gain in receive path:
*
* Linear Code of +3dB = 10^(3/20)= 1.412537545
* Coeff_X = round (1820 × 1.412537545) = 2571
* = 0b001010_00001011
* GA_MSB_Transmit = 0b0010100
* GA_LSB_Transmit = 0b0001011
*
* Linear Code of -3.5dB = 10^(-3.5/20) = 0.668343917
* Coeff_R= round (2506 × 0.668343917) = 1675
* = 0b0001101_0001011
* GA_MSB_Receive = 0b0001101
* GA_LSB_Receive = 0b0001011
*/
conf = IDT821034_MODE_GAIN(ch) | gain_type;
ret = idt821034_2x8bit_write(idt821034, conf | 0x00, gain_val & 0x007F);
if (ret)
return ret;
ret = idt821034_2x8bit_write(idt821034, conf | 0x01, (gain_val >> 7) & 0x7F);
if (ret)
return ret;
return 0;
}
/* Id helpers used in controls and dapm */
#define IDT821034_DIR_OUT (1 << 3)
#define IDT821034_DIR_IN (0 << 3)
#define IDT821034_ID(_ch, _dir) (((_ch) & 0x03) | (_dir))
#define IDT821034_ID_OUT(_ch) IDT821034_ID(_ch, IDT821034_DIR_OUT)
#define IDT821034_ID_IN(_ch) IDT821034_ID(_ch, IDT821034_DIR_IN)
#define IDT821034_ID_GET_CHAN(_id) ((_id) & 0x03)
#define IDT821034_ID_GET_DIR(_id) ((_id) & (1 << 3))
#define IDT821034_ID_IS_OUT(_id) (IDT821034_ID_GET_DIR(_id) == IDT821034_DIR_OUT)
static int idt821034_kctrl_gain_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct idt821034 *idt821034 = snd_soc_component_get_drvdata(component);
int min = mc->min;
int max = mc->max;
unsigned int mask = (1 << fls(max)) - 1;
unsigned int invert = mc->invert;
int val;
u8 ch;
ch = IDT821034_ID_GET_CHAN(mc->reg);
mutex_lock(&idt821034->mutex);
if (IDT821034_ID_IS_OUT(mc->reg))
val = idt821034->amps.ch[ch].amp_out.gain;
else
val = idt821034->amps.ch[ch].amp_in.gain;
mutex_unlock(&idt821034->mutex);
ucontrol->value.integer.value[0] = val & mask;
if (invert)
ucontrol->value.integer.value[0] = max - ucontrol->value.integer.value[0];
else
ucontrol->value.integer.value[0] = ucontrol->value.integer.value[0] - min;
return 0;
}
static int idt821034_kctrl_gain_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct idt821034 *idt821034 = snd_soc_component_get_drvdata(component);
struct idt821034_amp *amp;
int min = mc->min;
int max = mc->max;
unsigned int mask = (1 << fls(max)) - 1;
unsigned int invert = mc->invert;
unsigned int val;
int ret;
u8 gain_type;
u8 ch;
val = ucontrol->value.integer.value[0];
if (val > max - min)
return -EINVAL;
if (invert)
val = (max - val) & mask;
else
val = (val + min) & mask;
ch = IDT821034_ID_GET_CHAN(mc->reg);
mutex_lock(&idt821034->mutex);
if (IDT821034_ID_IS_OUT(mc->reg)) {
amp = &idt821034->amps.ch[ch].amp_out;
gain_type = IDT821034_GAIN_RX;
} else {
amp = &idt821034->amps.ch[ch].amp_in;
gain_type = IDT821034_GAIN_TX;
}
if (amp->gain == val) {
ret = 0;
goto end;
}
if (!amp->is_muted) {
ret = idt821034_set_gain_channel(idt821034, ch, gain_type, val);
if (ret)
goto end;
}
amp->gain = val;
ret = 1; /* The value changed */
end:
mutex_unlock(&idt821034->mutex);
return ret;
}
static int idt821034_kctrl_mute_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct idt821034 *idt821034 = snd_soc_component_get_drvdata(component);
int id = kcontrol->private_value;
bool is_muted;
u8 ch;
ch = IDT821034_ID_GET_CHAN(id);
mutex_lock(&idt821034->mutex);
is_muted = IDT821034_ID_IS_OUT(id) ?
idt821034->amps.ch[ch].amp_out.is_muted :
idt821034->amps.ch[ch].amp_in.is_muted;
mutex_unlock(&idt821034->mutex);
ucontrol->value.integer.value[0] = !is_muted;
return 0;
}
static int idt821034_kctrl_mute_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct idt821034 *idt821034 = snd_soc_component_get_drvdata(component);
int id = kcontrol->private_value;
struct idt821034_amp *amp;
bool is_mute;
u8 gain_type;
int ret;
u8 ch;
ch = IDT821034_ID_GET_CHAN(id);
is_mute = !ucontrol->value.integer.value[0];
mutex_lock(&idt821034->mutex);
if (IDT821034_ID_IS_OUT(id)) {
amp = &idt821034->amps.ch[ch].amp_out;
gain_type = IDT821034_GAIN_RX;
} else {
amp = &idt821034->amps.ch[ch].amp_in;
gain_type = IDT821034_GAIN_TX;
}
if (amp->is_muted == is_mute) {
ret = 0;
goto end;
}
ret = idt821034_set_gain_channel(idt821034, ch, gain_type,
is_mute ? 0 : amp->gain);
if (ret)
goto end;
amp->is_muted = is_mute;
ret = 1; /* The value changed */
end:
mutex_unlock(&idt821034->mutex);
return ret;
}
static const DECLARE_TLV_DB_LINEAR(idt821034_gain_in, -6520, 1306);
#define IDT821034_GAIN_IN_MIN_RAW 1 /* -65.20 dB -> 10^(-65.2/20.0) * 1820 = 1 */
#define IDT821034_GAIN_IN_MAX_RAW 8191 /* 13.06 dB -> 10^(13.06/20.0) * 1820 = 8191 */
#define IDT821034_GAIN_IN_INIT_RAW 1820 /* 0dB -> 10^(0/20) * 1820 = 1820 */
static const DECLARE_TLV_DB_LINEAR(idt821034_gain_out, -6798, 1029);
#define IDT821034_GAIN_OUT_MIN_RAW 1 /* -67.98 dB -> 10^(-67.98/20.0) * 2506 = 1*/
#define IDT821034_GAIN_OUT_MAX_RAW 8191 /* 10.29 dB -> 10^(10.29/20.0) * 2506 = 8191 */
#define IDT821034_GAIN_OUT_INIT_RAW 2506 /* 0dB -> 10^(0/20) * 2506 = 2506 */
static const struct snd_kcontrol_new idt821034_controls[] = {
/* DAC volume control */
SOC_SINGLE_RANGE_EXT_TLV("DAC0 Playback Volume", IDT821034_ID_OUT(0), 0,
IDT821034_GAIN_OUT_MIN_RAW, IDT821034_GAIN_OUT_MAX_RAW,
0, idt821034_kctrl_gain_get, idt821034_kctrl_gain_put,
idt821034_gain_out),
SOC_SINGLE_RANGE_EXT_TLV("DAC1 Playback Volume", IDT821034_ID_OUT(1), 0,
IDT821034_GAIN_OUT_MIN_RAW, IDT821034_GAIN_OUT_MAX_RAW,
0, idt821034_kctrl_gain_get, idt821034_kctrl_gain_put,
idt821034_gain_out),
SOC_SINGLE_RANGE_EXT_TLV("DAC2 Playback Volume", IDT821034_ID_OUT(2), 0,
IDT821034_GAIN_OUT_MIN_RAW, IDT821034_GAIN_OUT_MAX_RAW,
0, idt821034_kctrl_gain_get, idt821034_kctrl_gain_put,
idt821034_gain_out),
SOC_SINGLE_RANGE_EXT_TLV("DAC3 Playback Volume", IDT821034_ID_OUT(3), 0,
IDT821034_GAIN_OUT_MIN_RAW, IDT821034_GAIN_OUT_MAX_RAW,
0, idt821034_kctrl_gain_get, idt821034_kctrl_gain_put,
idt821034_gain_out),
/* DAC mute control */
SOC_SINGLE_BOOL_EXT("DAC0 Playback Switch", IDT821034_ID_OUT(0),
idt821034_kctrl_mute_get, idt821034_kctrl_mute_put),
SOC_SINGLE_BOOL_EXT("DAC1 Playback Switch", IDT821034_ID_OUT(1),
idt821034_kctrl_mute_get, idt821034_kctrl_mute_put),
SOC_SINGLE_BOOL_EXT("DAC2 Playback Switch", IDT821034_ID_OUT(2),
idt821034_kctrl_mute_get, idt821034_kctrl_mute_put),
SOC_SINGLE_BOOL_EXT("DAC3 Playback Switch", IDT821034_ID_OUT(3),
idt821034_kctrl_mute_get, idt821034_kctrl_mute_put),
/* ADC volume control */
SOC_SINGLE_RANGE_EXT_TLV("ADC0 Capture Volume", IDT821034_ID_IN(0), 0,
IDT821034_GAIN_IN_MIN_RAW, IDT821034_GAIN_IN_MAX_RAW,
0, idt821034_kctrl_gain_get, idt821034_kctrl_gain_put,
idt821034_gain_in),
SOC_SINGLE_RANGE_EXT_TLV("ADC1 Capture Volume", IDT821034_ID_IN(1), 0,
IDT821034_GAIN_IN_MIN_RAW, IDT821034_GAIN_IN_MAX_RAW,
0, idt821034_kctrl_gain_get, idt821034_kctrl_gain_put,
idt821034_gain_in),
SOC_SINGLE_RANGE_EXT_TLV("ADC2 Capture Volume", IDT821034_ID_IN(2), 0,
IDT821034_GAIN_IN_MIN_RAW, IDT821034_GAIN_IN_MAX_RAW,
0, idt821034_kctrl_gain_get, idt821034_kctrl_gain_put,
idt821034_gain_in),
SOC_SINGLE_RANGE_EXT_TLV("ADC3 Capture Volume", IDT821034_ID_IN(3), 0,
IDT821034_GAIN_IN_MIN_RAW, IDT821034_GAIN_IN_MAX_RAW,
0, idt821034_kctrl_gain_get, idt821034_kctrl_gain_put,
idt821034_gain_in),
/* ADC mute control */
SOC_SINGLE_BOOL_EXT("ADC0 Capture Switch", IDT821034_ID_IN(0),
idt821034_kctrl_mute_get, idt821034_kctrl_mute_put),
SOC_SINGLE_BOOL_EXT("ADC1 Capture Switch", IDT821034_ID_IN(1),
idt821034_kctrl_mute_get, idt821034_kctrl_mute_put),
SOC_SINGLE_BOOL_EXT("ADC2 Capture Switch", IDT821034_ID_IN(2),
idt821034_kctrl_mute_get, idt821034_kctrl_mute_put),
SOC_SINGLE_BOOL_EXT("ADC3 Capture Switch", IDT821034_ID_IN(3),
idt821034_kctrl_mute_get, idt821034_kctrl_mute_put),
};
static int idt821034_power_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct idt821034 *idt821034 = snd_soc_component_get_drvdata(component);
unsigned int id = w->shift;
u8 power, mask;
int ret;
u8 ch;
ch = IDT821034_ID_GET_CHAN(id);
mask = IDT821034_ID_IS_OUT(id) ? IDT821034_CONF_PWRUP_RX : IDT821034_CONF_PWRUP_TX;
mutex_lock(&idt821034->mutex);
power = idt821034_get_channel_power(idt821034, ch);
if (SND_SOC_DAPM_EVENT_ON(event))
power |= mask;
else
power &= ~mask;
ret = idt821034_set_channel_power(idt821034, ch, power);
mutex_unlock(&idt821034->mutex);
return ret;
}
static const struct snd_soc_dapm_widget idt821034_dapm_widgets[] = {
SND_SOC_DAPM_DAC_E("DAC0", "Playback", SND_SOC_NOPM, IDT821034_ID_OUT(0), 0,
idt821034_power_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_DAC_E("DAC1", "Playback", SND_SOC_NOPM, IDT821034_ID_OUT(1), 0,
idt821034_power_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_DAC_E("DAC2", "Playback", SND_SOC_NOPM, IDT821034_ID_OUT(2), 0,
idt821034_power_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_DAC_E("DAC3", "Playback", SND_SOC_NOPM, IDT821034_ID_OUT(3), 0,
idt821034_power_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_OUTPUT("OUT0"),
SND_SOC_DAPM_OUTPUT("OUT1"),
SND_SOC_DAPM_OUTPUT("OUT2"),
SND_SOC_DAPM_OUTPUT("OUT3"),
SND_SOC_DAPM_DAC_E("ADC0", "Capture", SND_SOC_NOPM, IDT821034_ID_IN(0), 0,
idt821034_power_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_DAC_E("ADC1", "Capture", SND_SOC_NOPM, IDT821034_ID_IN(1), 0,
idt821034_power_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_DAC_E("ADC2", "Capture", SND_SOC_NOPM, IDT821034_ID_IN(2), 0,
idt821034_power_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_DAC_E("ADC3", "Capture", SND_SOC_NOPM, IDT821034_ID_IN(3), 0,
idt821034_power_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_INPUT("IN0"),
SND_SOC_DAPM_INPUT("IN1"),
SND_SOC_DAPM_INPUT("IN2"),
SND_SOC_DAPM_INPUT("IN3"),
};
static const struct snd_soc_dapm_route idt821034_dapm_routes[] = {
{ "OUT0", NULL, "DAC0" },
{ "OUT1", NULL, "DAC1" },
{ "OUT2", NULL, "DAC2" },
{ "OUT3", NULL, "DAC3" },
{ "ADC0", NULL, "IN0" },
{ "ADC1", NULL, "IN1" },
{ "ADC2", NULL, "IN2" },
{ "ADC3", NULL, "IN3" },
};
static int idt821034_dai_set_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask,
int slots, int width)
{
struct idt821034 *idt821034 = snd_soc_component_get_drvdata(dai->component);
unsigned int mask;
u8 slot;
int ret;
u8 ch;
switch (width) {
case 0: /* Not set -> default 8 */
case 8:
break;
default:
dev_err(dai->dev, "tdm slot width %d not supported\n", width);
return -EINVAL;
}
mask = tx_mask;
slot = 0;
ch = 0;
while (mask && ch < IDT821034_NB_CHANNEL) {
if (mask & 0x1) {
mutex_lock(&idt821034->mutex);
ret = idt821034_set_channel_ts(idt821034, ch, IDT821034_CH_RX, slot);
mutex_unlock(&idt821034->mutex);
if (ret) {
dev_err(dai->dev, "ch%u set tx tdm slot failed (%d)\n",
ch, ret);
return ret;
}
ch++;
}
mask >>= 1;
slot++;
}
if (mask) {
dev_err(dai->dev, "too much tx slots defined (mask = 0x%x) support max %d\n",
tx_mask, IDT821034_NB_CHANNEL);
return -EINVAL;
}
idt821034->max_ch_playback = ch;
mask = rx_mask;
slot = 0;
ch = 0;
while (mask && ch < IDT821034_NB_CHANNEL) {
if (mask & 0x1) {
mutex_lock(&idt821034->mutex);
ret = idt821034_set_channel_ts(idt821034, ch, IDT821034_CH_TX, slot);
mutex_unlock(&idt821034->mutex);
if (ret) {
dev_err(dai->dev, "ch%u set rx tdm slot failed (%d)\n",
ch, ret);
return ret;
}
ch++;
}
mask >>= 1;
slot++;
}
if (mask) {
dev_err(dai->dev, "too much rx slots defined (mask = 0x%x) support max %d\n",
rx_mask, IDT821034_NB_CHANNEL);
return -EINVAL;
}
idt821034->max_ch_capture = ch;
return 0;
}
static int idt821034_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct idt821034 *idt821034 = snd_soc_component_get_drvdata(dai->component);
u8 conf;
int ret;
mutex_lock(&idt821034->mutex);
conf = idt821034_get_codec_conf(idt821034);
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
conf |= IDT821034_CONF_DELAY_MODE;
break;
case SND_SOC_DAIFMT_DSP_B:
conf &= ~IDT821034_CONF_DELAY_MODE;
break;
default:
dev_err(dai->dev, "Unsupported DAI format 0x%x\n",
fmt & SND_SOC_DAIFMT_FORMAT_MASK);
ret = -EINVAL;
goto end;
}
ret = idt821034_set_codec_conf(idt821034, conf);
end:
mutex_unlock(&idt821034->mutex);
return ret;
}
static int idt821034_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct idt821034 *idt821034 = snd_soc_component_get_drvdata(dai->component);
u8 conf;
int ret;
mutex_lock(&idt821034->mutex);
conf = idt821034_get_codec_conf(idt821034);
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_A_LAW:
conf |= IDT821034_CONF_ALAW_MODE;
break;
case SNDRV_PCM_FORMAT_MU_LAW:
conf &= ~IDT821034_CONF_ALAW_MODE;
break;
default:
dev_err(dai->dev, "Unsupported PCM format 0x%x\n",
params_format(params));
ret = -EINVAL;
goto end;
}
ret = idt821034_set_codec_conf(idt821034, conf);
end:
mutex_unlock(&idt821034->mutex);
return ret;
}
static const unsigned int idt821034_sample_bits[] = {8};
static struct snd_pcm_hw_constraint_list idt821034_sample_bits_constr = {
.list = idt821034_sample_bits,
.count = ARRAY_SIZE(idt821034_sample_bits),
};
static int idt821034_dai_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct idt821034 *idt821034 = snd_soc_component_get_drvdata(dai->component);
unsigned int max_ch = 0;
int ret;
max_ch = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
idt821034->max_ch_playback : idt821034->max_ch_capture;
/*
* Disable stream support (min = 0, max = 0) if no timeslots were
* configured otherwise, limit the number of channels to those
* configured.
*/
ret = snd_pcm_hw_constraint_minmax(substream->runtime, SNDRV_PCM_HW_PARAM_CHANNELS,
max_ch ? 1 : 0, max_ch);
if (ret < 0)
return ret;
ret = snd_pcm_hw_constraint_list(substream->runtime, 0, SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
&idt821034_sample_bits_constr);
if (ret)
return ret;
return 0;
}
static u64 idt821034_dai_formats[] = {
SND_SOC_POSSIBLE_DAIFMT_DSP_A |
SND_SOC_POSSIBLE_DAIFMT_DSP_B,
};
static const struct snd_soc_dai_ops idt821034_dai_ops = {
.startup = idt821034_dai_startup,
.hw_params = idt821034_dai_hw_params,
.set_tdm_slot = idt821034_dai_set_tdm_slot,
.set_fmt = idt821034_dai_set_fmt,
.auto_selectable_formats = idt821034_dai_formats,
.num_auto_selectable_formats = ARRAY_SIZE(idt821034_dai_formats),
};
static struct snd_soc_dai_driver idt821034_dai_driver = {
.name = "idt821034",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = IDT821034_NB_CHANNEL,
.rates = SNDRV_PCM_RATE_8000,
.formats = SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = IDT821034_NB_CHANNEL,
.rates = SNDRV_PCM_RATE_8000,
.formats = SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW,
},
.ops = &idt821034_dai_ops,
};
static int idt821034_reset_audio(struct idt821034 *idt821034)
{
int ret;
u8 i;
mutex_lock(&idt821034->mutex);
ret = idt821034_set_codec_conf(idt821034, 0);
if (ret)
goto end;
for (i = 0; i < IDT821034_NB_CHANNEL; i++) {
idt821034->amps.ch[i].amp_out.gain = IDT821034_GAIN_OUT_INIT_RAW;
idt821034->amps.ch[i].amp_out.is_muted = false;
ret = idt821034_set_gain_channel(idt821034, i, IDT821034_GAIN_RX,
idt821034->amps.ch[i].amp_out.gain);
if (ret)
goto end;
idt821034->amps.ch[i].amp_in.gain = IDT821034_GAIN_IN_INIT_RAW;
idt821034->amps.ch[i].amp_in.is_muted = false;
ret = idt821034_set_gain_channel(idt821034, i, IDT821034_GAIN_TX,
idt821034->amps.ch[i].amp_in.gain);
if (ret)
goto end;
ret = idt821034_set_channel_power(idt821034, i, 0);
if (ret)
goto end;
}
ret = 0;
end:
mutex_unlock(&idt821034->mutex);
return ret;
}
static int idt821034_component_probe(struct snd_soc_component *component)
{
struct idt821034 *idt821034 = snd_soc_component_get_drvdata(component);
int ret;
/* reset idt821034 audio part*/
ret = idt821034_reset_audio(idt821034);
if (ret)
return ret;
return 0;
}
static const struct snd_soc_component_driver idt821034_component_driver = {
.probe = idt821034_component_probe,
.controls = idt821034_controls,
.num_controls = ARRAY_SIZE(idt821034_controls),
.dapm_widgets = idt821034_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(idt821034_dapm_widgets),
.dapm_routes = idt821034_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(idt821034_dapm_routes),
.endianness = 1,
};
#define IDT821034_GPIO_OFFSET_TO_SLIC_CHANNEL(_offset) (((_offset) / 5) % 4)
#define IDT821034_GPIO_OFFSET_TO_SLIC_MASK(_offset) BIT((_offset) % 5)
static void idt821034_chip_gpio_set(struct gpio_chip *c, unsigned int offset, int val)
{
u8 ch = IDT821034_GPIO_OFFSET_TO_SLIC_CHANNEL(offset);
u8 mask = IDT821034_GPIO_OFFSET_TO_SLIC_MASK(offset);
struct idt821034 *idt821034 = gpiochip_get_data(c);
u8 slic_raw;
int ret;
mutex_lock(&idt821034->mutex);
slic_raw = idt821034_get_written_slic_raw(idt821034, ch);
if (val)
slic_raw |= mask;
else
slic_raw &= ~mask;
ret = idt821034_write_slic_raw(idt821034, ch, slic_raw);
if (ret) {
dev_err(&idt821034->spi->dev, "set gpio %d (%u, 0x%x) failed (%d)\n",
offset, ch, mask, ret);
}
mutex_unlock(&idt821034->mutex);
}
static int idt821034_chip_gpio_get(struct gpio_chip *c, unsigned int offset)
{
u8 ch = IDT821034_GPIO_OFFSET_TO_SLIC_CHANNEL(offset);
u8 mask = IDT821034_GPIO_OFFSET_TO_SLIC_MASK(offset);
struct idt821034 *idt821034 = gpiochip_get_data(c);
u8 slic_raw;
int ret;
mutex_lock(&idt821034->mutex);
ret = idt821034_read_slic_raw(idt821034, ch, &slic_raw);
mutex_unlock(&idt821034->mutex);
if (ret) {
dev_err(&idt821034->spi->dev, "get gpio %d (%u, 0x%x) failed (%d)\n",
offset, ch, mask, ret);
return ret;
}
/*
* SLIC IOs are read in reverse order compared to write.
* Reverse the read value here in order to have IO0 at lsb (ie same
* order as write)
*/
return !!(bitrev8(slic_raw) & mask);
}
static int idt821034_chip_get_direction(struct gpio_chip *c, unsigned int offset)
{
u8 ch = IDT821034_GPIO_OFFSET_TO_SLIC_CHANNEL(offset);
u8 mask = IDT821034_GPIO_OFFSET_TO_SLIC_MASK(offset);
struct idt821034 *idt821034 = gpiochip_get_data(c);
u8 slic_dir;
mutex_lock(&idt821034->mutex);
slic_dir = idt821034_get_slic_conf(idt821034, ch);
mutex_unlock(&idt821034->mutex);
return slic_dir & mask ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT;
}
static int idt821034_chip_direction_input(struct gpio_chip *c, unsigned int offset)
{
u8 ch = IDT821034_GPIO_OFFSET_TO_SLIC_CHANNEL(offset);
u8 mask = IDT821034_GPIO_OFFSET_TO_SLIC_MASK(offset);
struct idt821034 *idt821034 = gpiochip_get_data(c);
u8 slic_conf;
int ret;
/* Only IO0 and IO1 can be set as input */
if (mask & ~(IDT821034_SLIC_IO1_IN | IDT821034_SLIC_IO0_IN))
return -EPERM;
mutex_lock(&idt821034->mutex);
slic_conf = idt821034_get_slic_conf(idt821034, ch) | mask;
ret = idt821034_set_slic_conf(idt821034, ch, slic_conf);
if (ret) {
dev_err(&idt821034->spi->dev, "dir in gpio %d (%u, 0x%x) failed (%d)\n",
offset, ch, mask, ret);
}
mutex_unlock(&idt821034->mutex);
return ret;
}
static int idt821034_chip_direction_output(struct gpio_chip *c, unsigned int offset, int val)
{
u8 ch = IDT821034_GPIO_OFFSET_TO_SLIC_CHANNEL(offset);
u8 mask = IDT821034_GPIO_OFFSET_TO_SLIC_MASK(offset);
struct idt821034 *idt821034 = gpiochip_get_data(c);
u8 slic_conf;
int ret;
idt821034_chip_gpio_set(c, offset, val);
mutex_lock(&idt821034->mutex);
slic_conf = idt821034_get_slic_conf(idt821034, ch) & ~mask;
ret = idt821034_set_slic_conf(idt821034, ch, slic_conf);
if (ret) {
dev_err(&idt821034->spi->dev, "dir in gpio %d (%u, 0x%x) failed (%d)\n",
offset, ch, mask, ret);
}
mutex_unlock(&idt821034->mutex);
return ret;
}
static int idt821034_reset_gpio(struct idt821034 *idt821034)
{
int ret;
u8 i;
mutex_lock(&idt821034->mutex);
/* IO0 and IO1 as input for all channels and output IO set to 0 */
for (i = 0; i < IDT821034_NB_CHANNEL; i++) {
ret = idt821034_set_slic_conf(idt821034, i,
IDT821034_SLIC_IO1_IN | IDT821034_SLIC_IO0_IN);
if (ret)
goto end;
ret = idt821034_write_slic_raw(idt821034, i, 0);
if (ret)
goto end;
}
ret = 0;
end:
mutex_unlock(&idt821034->mutex);
return ret;
}
static int idt821034_gpio_init(struct idt821034 *idt821034)
{
int ret;
ret = idt821034_reset_gpio(idt821034);
if (ret)
return ret;
idt821034->gpio_chip.owner = THIS_MODULE;
idt821034->gpio_chip.label = dev_name(&idt821034->spi->dev);
idt821034->gpio_chip.parent = &idt821034->spi->dev;
idt821034->gpio_chip.base = -1;
idt821034->gpio_chip.ngpio = 5 * 4; /* 5 GPIOs on 4 channels */
idt821034->gpio_chip.get_direction = idt821034_chip_get_direction;
idt821034->gpio_chip.direction_input = idt821034_chip_direction_input;
idt821034->gpio_chip.direction_output = idt821034_chip_direction_output;
idt821034->gpio_chip.get = idt821034_chip_gpio_get;
idt821034->gpio_chip.set = idt821034_chip_gpio_set;
idt821034->gpio_chip.can_sleep = true;
return devm_gpiochip_add_data(&idt821034->spi->dev, &idt821034->gpio_chip,
idt821034);
}
static int idt821034_spi_probe(struct spi_device *spi)
{
struct idt821034 *idt821034;
int ret;
spi->bits_per_word = 8;
ret = spi_setup(spi);
if (ret < 0)
return ret;
idt821034 = devm_kzalloc(&spi->dev, sizeof(*idt821034), GFP_KERNEL);
if (!idt821034)
return -ENOMEM;
idt821034->spi = spi;
mutex_init(&idt821034->mutex);
spi_set_drvdata(spi, idt821034);
ret = devm_snd_soc_register_component(&spi->dev, &idt821034_component_driver,
&idt821034_dai_driver, 1);
if (ret)
return ret;
if (IS_ENABLED(CONFIG_GPIOLIB))
return idt821034_gpio_init(idt821034);
return 0;
}
static const struct of_device_id idt821034_of_match[] = {
{ .compatible = "renesas,idt821034", },
{ }
};
MODULE_DEVICE_TABLE(of, idt821034_of_match);
static const struct spi_device_id idt821034_id_table[] = {
{ "idt821034", 0 },
{ }
};
MODULE_DEVICE_TABLE(spi, idt821034_id_table);
static struct spi_driver idt821034_spi_driver = {
.driver = {
.name = "idt821034",
.of_match_table = idt821034_of_match,
},
.id_table = idt821034_id_table,
.probe = idt821034_spi_probe,
};
module_spi_driver(idt821034_spi_driver);
MODULE_AUTHOR("Herve Codina <[email protected]>");
MODULE_DESCRIPTION("IDT821034 ALSA SoC driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/idt821034.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2019 MediaTek Inc.
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/pm_runtime.h>
#include <linux/delay.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <sound/pcm_params.h>
#include "mt6660.h"
struct reg_size_table {
u32 addr;
u8 size;
};
static const struct reg_size_table mt6660_reg_size_table[] = {
{ MT6660_REG_HPF1_COEF, 4 },
{ MT6660_REG_HPF2_COEF, 4 },
{ MT6660_REG_TDM_CFG3, 2 },
{ MT6660_REG_RESV17, 2 },
{ MT6660_REG_RESV23, 2 },
{ MT6660_REG_SIGMAX, 2 },
{ MT6660_REG_DEVID, 2 },
{ MT6660_REG_HCLIP_CTRL, 2 },
{ MT6660_REG_DA_GAIN, 2 },
};
static int mt6660_get_reg_size(uint32_t addr)
{
int i;
for (i = 0; i < ARRAY_SIZE(mt6660_reg_size_table); i++) {
if (mt6660_reg_size_table[i].addr == addr)
return mt6660_reg_size_table[i].size;
}
return 1;
}
static int mt6660_reg_write(void *context, unsigned int reg, unsigned int val)
{
struct mt6660_chip *chip = context;
int size = mt6660_get_reg_size(reg);
u8 reg_data[4];
int i;
for (i = 0; i < size; i++)
reg_data[size - i - 1] = (val >> (8 * i)) & 0xff;
return i2c_smbus_write_i2c_block_data(chip->i2c, reg, size, reg_data);
}
static int mt6660_reg_read(void *context, unsigned int reg, unsigned int *val)
{
struct mt6660_chip *chip = context;
int size = mt6660_get_reg_size(reg);
int i, ret;
u8 data[4];
u32 reg_data = 0;
ret = i2c_smbus_read_i2c_block_data(chip->i2c, reg, size, data);
if (ret < 0)
return ret;
for (i = 0; i < size; i++) {
reg_data <<= 8;
reg_data |= data[i];
}
*val = reg_data;
return 0;
}
static const struct regmap_config mt6660_regmap_config = {
.reg_bits = 8,
.val_bits = 32,
.reg_write = mt6660_reg_write,
.reg_read = mt6660_reg_read,
};
static int mt6660_codec_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
if (event == SND_SOC_DAPM_POST_PMU)
usleep_range(1000, 1100);
return 0;
}
static int mt6660_codec_classd_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
int ret;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
dev_dbg(component->dev,
"%s: before classd turn on\n", __func__);
/* config to adaptive mode */
ret = snd_soc_component_update_bits(component,
MT6660_REG_BST_CTRL, 0x03, 0x03);
if (ret < 0) {
dev_err(component->dev, "config mode adaptive fail\n");
return ret;
}
break;
case SND_SOC_DAPM_POST_PMU:
/* voltage sensing enable */
ret = snd_soc_component_update_bits(component,
MT6660_REG_RESV7, 0x04, 0x04);
if (ret < 0) {
dev_err(component->dev,
"enable voltage sensing fail\n");
return ret;
}
dev_dbg(component->dev, "Amp on\n");
break;
case SND_SOC_DAPM_PRE_PMD:
dev_dbg(component->dev, "Amp off\n");
/* voltage sensing disable */
ret = snd_soc_component_update_bits(component,
MT6660_REG_RESV7, 0x04, 0x00);
if (ret < 0) {
dev_err(component->dev,
"disable voltage sensing fail\n");
return ret;
}
/* pop-noise improvement 1 */
ret = snd_soc_component_update_bits(component,
MT6660_REG_RESV10, 0x10, 0x10);
if (ret < 0) {
dev_err(component->dev,
"pop-noise improvement 1 fail\n");
return ret;
}
break;
case SND_SOC_DAPM_POST_PMD:
dev_dbg(component->dev,
"%s: after classd turn off\n", __func__);
/* pop-noise improvement 2 */
ret = snd_soc_component_update_bits(component,
MT6660_REG_RESV10, 0x10, 0x00);
if (ret < 0) {
dev_err(component->dev,
"pop-noise improvement 2 fail\n");
return ret;
}
/* config to off mode */
ret = snd_soc_component_update_bits(component,
MT6660_REG_BST_CTRL, 0x03, 0x00);
if (ret < 0) {
dev_err(component->dev, "config mode off fail\n");
return ret;
}
break;
}
return 0;
}
static const struct snd_soc_dapm_widget mt6660_component_dapm_widgets[] = {
SND_SOC_DAPM_DAC_E("DAC", NULL, MT6660_REG_PLL_CFG1,
0, 1, mt6660_codec_dac_event, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_ADC("VI ADC", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_PGA("PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV_E("ClassD", MT6660_REG_SYSTEM_CTRL, 2, 0,
NULL, 0, mt6660_codec_classd_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_OUTPUT("OUTP"),
SND_SOC_DAPM_OUTPUT("OUTN"),
};
static const struct snd_soc_dapm_route mt6660_component_dapm_routes[] = {
{ "DAC", NULL, "aif_playback" },
{ "PGA", NULL, "DAC" },
{ "ClassD", NULL, "PGA" },
{ "OUTP", NULL, "ClassD" },
{ "OUTN", NULL, "ClassD" },
{ "VI ADC", NULL, "ClassD" },
{ "aif_capture", NULL, "VI ADC" },
};
static int mt6660_component_get_volsw(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct mt6660_chip *chip = (struct mt6660_chip *)
snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = chip->chip_rev & 0x0f;
return 0;
}
static const DECLARE_TLV_DB_SCALE(vol_ctl_tlv, -1155, 5, 0);
static const struct snd_kcontrol_new mt6660_component_snd_controls[] = {
SOC_SINGLE_TLV("Digital Volume", MT6660_REG_VOL_CTRL, 0, 255,
1, vol_ctl_tlv),
SOC_SINGLE("Hard Clip Switch", MT6660_REG_HCLIP_CTRL, 8, 1, 0),
SOC_SINGLE("Clip Switch", MT6660_REG_SPS_CTRL, 0, 1, 0),
SOC_SINGLE("Boost Mode", MT6660_REG_BST_CTRL, 0, 3, 0),
SOC_SINGLE("DRE Switch", MT6660_REG_DRE_CTRL, 0, 1, 0),
SOC_SINGLE("DC Protect Switch", MT6660_REG_DC_PROTECT_CTRL, 3, 1, 0),
SOC_SINGLE("Data Output Left Channel Selection",
MT6660_REG_DATAO_SEL, 3, 7, 0),
SOC_SINGLE("Data Output Right Channel Selection",
MT6660_REG_DATAO_SEL, 0, 7, 0),
SOC_SINGLE_EXT("T0 SEL", MT6660_REG_CALI_T0, 0, 7, 0,
snd_soc_get_volsw, NULL),
SOC_SINGLE_EXT("Chip Rev", MT6660_REG_DEVID, 8, 15, 0,
mt6660_component_get_volsw, NULL),
};
static int _mt6660_chip_power_on(struct mt6660_chip *chip, int on_off)
{
return regmap_write_bits(chip->regmap, MT6660_REG_SYSTEM_CTRL,
0x01, on_off ? 0x00 : 0x01);
}
struct reg_table {
uint32_t addr;
uint32_t mask;
uint32_t val;
};
static const struct reg_table mt6660_setting_table[] = {
{ 0x20, 0x80, 0x00 },
{ 0x30, 0x01, 0x00 },
{ 0x50, 0x1c, 0x04 },
{ 0xB1, 0x0c, 0x00 },
{ 0xD3, 0x03, 0x03 },
{ 0xE0, 0x01, 0x00 },
{ 0x98, 0x44, 0x04 },
{ 0xB9, 0xff, 0x82 },
{ 0xB7, 0x7777, 0x7273 },
{ 0xB6, 0x07, 0x03 },
{ 0x6B, 0xe0, 0x20 },
{ 0x07, 0xff, 0x70 },
{ 0xBB, 0xff, 0x20 },
{ 0x69, 0xff, 0x40 },
{ 0xBD, 0xffff, 0x17f8 },
{ 0x70, 0xff, 0x15 },
{ 0x7C, 0xff, 0x00 },
{ 0x46, 0xff, 0x1d },
{ 0x1A, 0xffffffff, 0x7fdb7ffe },
{ 0x1B, 0xffffffff, 0x7fdb7ffe },
{ 0x51, 0xff, 0x58 },
{ 0xA2, 0xff, 0xce },
{ 0x33, 0xffff, 0x7fff },
{ 0x4C, 0xffff, 0x0116 },
{ 0x16, 0x1800, 0x0800 },
{ 0x68, 0x1f, 0x07 },
};
static int mt6660_component_setting(struct snd_soc_component *component)
{
struct mt6660_chip *chip = snd_soc_component_get_drvdata(component);
int ret = 0;
size_t i = 0;
ret = _mt6660_chip_power_on(chip, 1);
if (ret < 0) {
dev_err(component->dev, "%s chip power on failed\n", __func__);
return ret;
}
for (i = 0; i < ARRAY_SIZE(mt6660_setting_table); i++) {
ret = snd_soc_component_update_bits(component,
mt6660_setting_table[i].addr,
mt6660_setting_table[i].mask,
mt6660_setting_table[i].val);
if (ret < 0) {
dev_err(component->dev, "%s update 0x%02x failed\n",
__func__, mt6660_setting_table[i].addr);
return ret;
}
}
ret = _mt6660_chip_power_on(chip, 0);
if (ret < 0) {
dev_err(component->dev, "%s chip power off failed\n", __func__);
return ret;
}
return 0;
}
static int mt6660_component_probe(struct snd_soc_component *component)
{
struct mt6660_chip *chip = snd_soc_component_get_drvdata(component);
int ret;
dev_dbg(component->dev, "%s\n", __func__);
snd_soc_component_init_regmap(component, chip->regmap);
ret = mt6660_component_setting(component);
if (ret < 0)
dev_err(chip->dev, "mt6660 component setting failed\n");
return ret;
}
static void mt6660_component_remove(struct snd_soc_component *component)
{
dev_dbg(component->dev, "%s\n", __func__);
snd_soc_component_exit_regmap(component);
}
static const struct snd_soc_component_driver mt6660_component_driver = {
.probe = mt6660_component_probe,
.remove = mt6660_component_remove,
.controls = mt6660_component_snd_controls,
.num_controls = ARRAY_SIZE(mt6660_component_snd_controls),
.dapm_widgets = mt6660_component_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(mt6660_component_dapm_widgets),
.dapm_routes = mt6660_component_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(mt6660_component_dapm_routes),
.idle_bias_on = false, /* idle_bias_off = true */
.endianness = 1,
};
static int mt6660_component_aif_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *dai)
{
int word_len = params_physical_width(hw_params);
int aud_bit = params_width(hw_params);
u16 reg_data = 0;
int ret;
dev_dbg(dai->dev, "%s: ++\n", __func__);
dev_dbg(dai->dev, "format: 0x%08x\n", params_format(hw_params));
dev_dbg(dai->dev, "rate: 0x%08x\n", params_rate(hw_params));
dev_dbg(dai->dev, "word_len: %d, aud_bit: %d\n", word_len, aud_bit);
if (word_len > 32 || word_len < 16) {
dev_err(dai->dev, "not supported word length\n");
return -ENOTSUPP;
}
switch (aud_bit) {
case 16:
reg_data = 3;
break;
case 18:
reg_data = 2;
break;
case 20:
reg_data = 1;
break;
case 24:
case 32:
reg_data = 0;
break;
default:
return -ENOTSUPP;
}
ret = snd_soc_component_update_bits(dai->component,
MT6660_REG_SERIAL_CFG1, 0xc0, (reg_data << 6));
if (ret < 0) {
dev_err(dai->dev, "config aud bit fail\n");
return ret;
}
ret = snd_soc_component_update_bits(dai->component,
MT6660_REG_TDM_CFG3, 0x3f0, word_len << 4);
if (ret < 0) {
dev_err(dai->dev, "config word len fail\n");
return ret;
}
dev_dbg(dai->dev, "%s: --\n", __func__);
return 0;
}
static const struct snd_soc_dai_ops mt6660_component_aif_ops = {
.hw_params = mt6660_component_aif_hw_params,
};
#define STUB_RATES SNDRV_PCM_RATE_8000_192000
#define STUB_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_U16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_U24_LE | \
SNDRV_PCM_FMTBIT_S32_LE | \
SNDRV_PCM_FMTBIT_U32_LE)
static struct snd_soc_dai_driver mt6660_codec_dai = {
.name = "mt6660-aif",
.playback = {
.stream_name = "aif_playback",
.channels_min = 1,
.channels_max = 2,
.rates = STUB_RATES,
.formats = STUB_FORMATS,
},
.capture = {
.stream_name = "aif_capture",
.channels_min = 1,
.channels_max = 2,
.rates = STUB_RATES,
.formats = STUB_FORMATS,
},
/* dai properties */
.symmetric_rate = 1,
.symmetric_channels = 1,
.symmetric_sample_bits = 1,
/* dai operations */
.ops = &mt6660_component_aif_ops,
};
static int _mt6660_chip_id_check(struct mt6660_chip *chip)
{
int ret;
unsigned int val;
ret = regmap_read(chip->regmap, MT6660_REG_DEVID, &val);
if (ret < 0)
return ret;
val &= 0x0ff0;
if (val != 0x00e0 && val != 0x01e0) {
dev_err(chip->dev, "%s id(%x) not match\n", __func__, val);
return -ENODEV;
}
return 0;
}
static int _mt6660_chip_sw_reset(struct mt6660_chip *chip)
{
int ret;
/* turn on main pll first, then trigger reset */
ret = regmap_write(chip->regmap, MT6660_REG_SYSTEM_CTRL, 0x00);
if (ret < 0)
return ret;
ret = regmap_write(chip->regmap, MT6660_REG_SYSTEM_CTRL, 0x80);
if (ret < 0)
return ret;
msleep(30);
return 0;
}
static int _mt6660_read_chip_revision(struct mt6660_chip *chip)
{
int ret;
unsigned int val;
ret = regmap_read(chip->regmap, MT6660_REG_DEVID, &val);
if (ret < 0) {
dev_err(chip->dev, "get chip revision fail\n");
return ret;
}
chip->chip_rev = val&0xff;
dev_info(chip->dev, "%s chip_rev = %x\n", __func__, chip->chip_rev);
return 0;
}
static int mt6660_i2c_probe(struct i2c_client *client)
{
struct mt6660_chip *chip = NULL;
int ret;
dev_dbg(&client->dev, "%s\n", __func__);
chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
if (!chip)
return -ENOMEM;
chip->i2c = client;
chip->dev = &client->dev;
mutex_init(&chip->io_lock);
i2c_set_clientdata(client, chip);
chip->regmap = devm_regmap_init(&client->dev,
NULL, chip, &mt6660_regmap_config);
if (IS_ERR(chip->regmap)) {
ret = PTR_ERR(chip->regmap);
dev_err(&client->dev, "failed to initialise regmap: %d\n", ret);
return ret;
}
/* chip reset first */
ret = _mt6660_chip_sw_reset(chip);
if (ret < 0) {
dev_err(chip->dev, "chip reset fail\n");
goto probe_fail;
}
/* chip power on */
ret = _mt6660_chip_power_on(chip, 1);
if (ret < 0) {
dev_err(chip->dev, "chip power on 2 fail\n");
goto probe_fail;
}
/* chip devid check */
ret = _mt6660_chip_id_check(chip);
if (ret < 0) {
dev_err(chip->dev, "chip id check fail\n");
goto probe_fail;
}
/* chip revision get */
ret = _mt6660_read_chip_revision(chip);
if (ret < 0) {
dev_err(chip->dev, "read chip revision fail\n");
goto probe_fail;
}
pm_runtime_set_active(chip->dev);
pm_runtime_enable(chip->dev);
ret = devm_snd_soc_register_component(chip->dev,
&mt6660_component_driver,
&mt6660_codec_dai, 1);
if (ret)
pm_runtime_disable(chip->dev);
return ret;
probe_fail:
_mt6660_chip_power_on(chip, 0);
mutex_destroy(&chip->io_lock);
return ret;
}
static void mt6660_i2c_remove(struct i2c_client *client)
{
struct mt6660_chip *chip = i2c_get_clientdata(client);
pm_runtime_disable(chip->dev);
pm_runtime_set_suspended(chip->dev);
mutex_destroy(&chip->io_lock);
}
static int __maybe_unused mt6660_i2c_runtime_suspend(struct device *dev)
{
struct mt6660_chip *chip = dev_get_drvdata(dev);
dev_dbg(dev, "enter low power mode\n");
return regmap_update_bits(chip->regmap,
MT6660_REG_SYSTEM_CTRL, 0x01, 0x01);
}
static int __maybe_unused mt6660_i2c_runtime_resume(struct device *dev)
{
struct mt6660_chip *chip = dev_get_drvdata(dev);
dev_dbg(dev, "exit low power mode\n");
return regmap_update_bits(chip->regmap,
MT6660_REG_SYSTEM_CTRL, 0x01, 0x00);
}
static const struct dev_pm_ops mt6660_dev_pm_ops = {
SET_RUNTIME_PM_OPS(mt6660_i2c_runtime_suspend,
mt6660_i2c_runtime_resume, NULL)
};
static const struct of_device_id __maybe_unused mt6660_of_id[] = {
{ .compatible = "mediatek,mt6660",},
{},
};
MODULE_DEVICE_TABLE(of, mt6660_of_id);
static const struct i2c_device_id mt6660_i2c_id[] = {
{"mt6660", 0 },
{},
};
MODULE_DEVICE_TABLE(i2c, mt6660_i2c_id);
static struct i2c_driver mt6660_i2c_driver = {
.driver = {
.name = "mt6660",
.of_match_table = of_match_ptr(mt6660_of_id),
.pm = &mt6660_dev_pm_ops,
},
.probe = mt6660_i2c_probe,
.remove = mt6660_i2c_remove,
.id_table = mt6660_i2c_id,
};
module_i2c_driver(mt6660_i2c_driver);
MODULE_AUTHOR("Jeff Chang <[email protected]>");
MODULE_DESCRIPTION("MT6660 SPKAMP Driver");
MODULE_LICENSE("GPL");
MODULE_VERSION("1.0.8_G");
| linux-master | sound/soc/codecs/mt6660.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* AK4104 ALSA SoC (ASoC) driver
*
* Copyright (c) 2009 Daniel Mack <[email protected]>
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/spi/spi.h>
#include <linux/of_device.h>
#include <linux/gpio/consumer.h>
#include <linux/regulator/consumer.h>
#include <sound/asoundef.h>
#include <sound/core.h>
#include <sound/soc.h>
#include <sound/initval.h>
/* AK4104 registers addresses */
#define AK4104_REG_CONTROL1 0x00
#define AK4104_REG_RESERVED 0x01
#define AK4104_REG_CONTROL2 0x02
#define AK4104_REG_TX 0x03
#define AK4104_REG_CHN_STATUS(x) ((x) + 0x04)
#define AK4104_NUM_REGS 10
#define AK4104_REG_MASK 0x1f
#define AK4104_READ 0xc0
#define AK4104_WRITE 0xe0
#define AK4104_RESERVED_VAL 0x5b
/* Bit masks for AK4104 registers */
#define AK4104_CONTROL1_RSTN (1 << 0)
#define AK4104_CONTROL1_PW (1 << 1)
#define AK4104_CONTROL1_DIF0 (1 << 2)
#define AK4104_CONTROL1_DIF1 (1 << 3)
#define AK4104_CONTROL2_SEL0 (1 << 0)
#define AK4104_CONTROL2_SEL1 (1 << 1)
#define AK4104_CONTROL2_MODE (1 << 2)
#define AK4104_TX_TXE (1 << 0)
#define AK4104_TX_V (1 << 1)
struct ak4104_private {
struct regmap *regmap;
struct regulator *regulator;
};
static const struct snd_soc_dapm_widget ak4104_dapm_widgets[] = {
SND_SOC_DAPM_PGA("TXE", AK4104_REG_TX, AK4104_TX_TXE, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("TX"),
};
static const struct snd_soc_dapm_route ak4104_dapm_routes[] = {
{ "TXE", NULL, "Playback" },
{ "TX", NULL, "TXE" },
};
static int ak4104_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int format)
{
struct snd_soc_component *component = codec_dai->component;
struct ak4104_private *ak4104 = snd_soc_component_get_drvdata(component);
int val = 0;
int ret;
/* set DAI format */
switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
val |= AK4104_CONTROL1_DIF0;
break;
case SND_SOC_DAIFMT_I2S:
val |= AK4104_CONTROL1_DIF0 | AK4104_CONTROL1_DIF1;
break;
default:
dev_err(component->dev, "invalid dai format\n");
return -EINVAL;
}
/* This device can only be consumer */
if ((format & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) != SND_SOC_DAIFMT_CBC_CFC)
return -EINVAL;
ret = regmap_update_bits(ak4104->regmap, AK4104_REG_CONTROL1,
AK4104_CONTROL1_DIF0 | AK4104_CONTROL1_DIF1,
val);
if (ret < 0)
return ret;
return 0;
}
static int ak4104_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct ak4104_private *ak4104 = snd_soc_component_get_drvdata(component);
int ret, val = 0;
/* set the IEC958 bits: consumer mode, no copyright bit */
val |= IEC958_AES0_CON_NOT_COPYRIGHT;
regmap_write(ak4104->regmap, AK4104_REG_CHN_STATUS(0), val);
val = 0;
switch (params_rate(params)) {
case 22050:
val |= IEC958_AES3_CON_FS_22050;
break;
case 24000:
val |= IEC958_AES3_CON_FS_24000;
break;
case 32000:
val |= IEC958_AES3_CON_FS_32000;
break;
case 44100:
val |= IEC958_AES3_CON_FS_44100;
break;
case 48000:
val |= IEC958_AES3_CON_FS_48000;
break;
case 88200:
val |= IEC958_AES3_CON_FS_88200;
break;
case 96000:
val |= IEC958_AES3_CON_FS_96000;
break;
case 176400:
val |= IEC958_AES3_CON_FS_176400;
break;
case 192000:
val |= IEC958_AES3_CON_FS_192000;
break;
default:
dev_err(component->dev, "unsupported sampling rate\n");
return -EINVAL;
}
ret = regmap_write(ak4104->regmap, AK4104_REG_CHN_STATUS(3), val);
if (ret < 0)
return ret;
return 0;
}
static const struct snd_soc_dai_ops ak4101_dai_ops = {
.hw_params = ak4104_hw_params,
.set_fmt = ak4104_set_dai_fmt,
};
static struct snd_soc_dai_driver ak4104_dai = {
.name = "ak4104-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 |
SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_3LE |
SNDRV_PCM_FMTBIT_S24_LE
},
.ops = &ak4101_dai_ops,
};
static int ak4104_probe(struct snd_soc_component *component)
{
struct ak4104_private *ak4104 = snd_soc_component_get_drvdata(component);
int ret;
ret = regulator_enable(ak4104->regulator);
if (ret < 0) {
dev_err(component->dev, "Unable to enable regulator: %d\n", ret);
return ret;
}
/* set power-up and non-reset bits */
ret = regmap_update_bits(ak4104->regmap, AK4104_REG_CONTROL1,
AK4104_CONTROL1_PW | AK4104_CONTROL1_RSTN,
AK4104_CONTROL1_PW | AK4104_CONTROL1_RSTN);
if (ret < 0)
goto exit_disable_regulator;
/* enable transmitter */
ret = regmap_update_bits(ak4104->regmap, AK4104_REG_TX,
AK4104_TX_TXE, AK4104_TX_TXE);
if (ret < 0)
goto exit_disable_regulator;
return 0;
exit_disable_regulator:
regulator_disable(ak4104->regulator);
return ret;
}
static void ak4104_remove(struct snd_soc_component *component)
{
struct ak4104_private *ak4104 = snd_soc_component_get_drvdata(component);
regmap_update_bits(ak4104->regmap, AK4104_REG_CONTROL1,
AK4104_CONTROL1_PW | AK4104_CONTROL1_RSTN, 0);
regulator_disable(ak4104->regulator);
}
#ifdef CONFIG_PM
static int ak4104_soc_suspend(struct snd_soc_component *component)
{
struct ak4104_private *priv = snd_soc_component_get_drvdata(component);
regulator_disable(priv->regulator);
return 0;
}
static int ak4104_soc_resume(struct snd_soc_component *component)
{
struct ak4104_private *priv = snd_soc_component_get_drvdata(component);
int ret;
ret = regulator_enable(priv->regulator);
if (ret < 0)
return ret;
return 0;
}
#else
#define ak4104_soc_suspend NULL
#define ak4104_soc_resume NULL
#endif /* CONFIG_PM */
static const struct snd_soc_component_driver soc_component_device_ak4104 = {
.probe = ak4104_probe,
.remove = ak4104_remove,
.suspend = ak4104_soc_suspend,
.resume = ak4104_soc_resume,
.dapm_widgets = ak4104_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(ak4104_dapm_widgets),
.dapm_routes = ak4104_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(ak4104_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config ak4104_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = AK4104_NUM_REGS - 1,
.read_flag_mask = AK4104_READ,
.write_flag_mask = AK4104_WRITE,
.cache_type = REGCACHE_RBTREE,
};
static int ak4104_spi_probe(struct spi_device *spi)
{
struct ak4104_private *ak4104;
struct gpio_desc *reset_gpiod;
unsigned int val;
int ret;
spi->bits_per_word = 8;
spi->mode = SPI_MODE_0;
ret = spi_setup(spi);
if (ret < 0)
return ret;
ak4104 = devm_kzalloc(&spi->dev, sizeof(struct ak4104_private),
GFP_KERNEL);
if (ak4104 == NULL)
return -ENOMEM;
ak4104->regulator = devm_regulator_get(&spi->dev, "vdd");
if (IS_ERR(ak4104->regulator)) {
ret = PTR_ERR(ak4104->regulator);
dev_err(&spi->dev, "Unable to get Vdd regulator: %d\n", ret);
return ret;
}
ak4104->regmap = devm_regmap_init_spi(spi, &ak4104_regmap);
if (IS_ERR(ak4104->regmap)) {
ret = PTR_ERR(ak4104->regmap);
return ret;
}
reset_gpiod = devm_gpiod_get_optional(&spi->dev, "reset",
GPIOD_OUT_HIGH);
if (PTR_ERR(reset_gpiod) == -EPROBE_DEFER)
return -EPROBE_DEFER;
/* read the 'reserved' register - according to the datasheet, it
* should contain 0x5b. Not a good way to verify the presence of
* the device, but there is no hardware ID register. */
ret = regmap_read(ak4104->regmap, AK4104_REG_RESERVED, &val);
if (ret != 0)
return ret;
if (val != AK4104_RESERVED_VAL)
return -ENODEV;
spi_set_drvdata(spi, ak4104);
ret = devm_snd_soc_register_component(&spi->dev,
&soc_component_device_ak4104, &ak4104_dai, 1);
return ret;
}
static const struct of_device_id ak4104_of_match[] = {
{ .compatible = "asahi-kasei,ak4104", },
{ }
};
MODULE_DEVICE_TABLE(of, ak4104_of_match);
static const struct spi_device_id ak4104_id_table[] = {
{ "ak4104", 0 },
{ }
};
MODULE_DEVICE_TABLE(spi, ak4104_id_table);
static struct spi_driver ak4104_spi_driver = {
.driver = {
.name = "ak4104",
.of_match_table = ak4104_of_match,
},
.id_table = ak4104_id_table,
.probe = ak4104_spi_probe,
};
module_spi_driver(ak4104_spi_driver);
MODULE_AUTHOR("Daniel Mack <[email protected]>");
MODULE_DESCRIPTION("Asahi Kasei AK4104 ALSA SoC driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/ak4104.c |
// SPDX-License-Identifier: GPL-2.0
//
// cs35l45-i2c.c -- CS35L45 I2C driver
//
// Copyright 2019-2022 Cirrus Logic, Inc.
//
// Author: James Schulman <[email protected]>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include "cs35l45.h"
static int cs35l45_i2c_probe(struct i2c_client *client)
{
struct cs35l45_private *cs35l45;
struct device *dev = &client->dev;
int ret;
cs35l45 = devm_kzalloc(dev, sizeof(struct cs35l45_private), GFP_KERNEL);
if (!cs35l45)
return -ENOMEM;
i2c_set_clientdata(client, cs35l45);
cs35l45->regmap = devm_regmap_init_i2c(client, &cs35l45_i2c_regmap);
if (IS_ERR(cs35l45->regmap)) {
ret = PTR_ERR(cs35l45->regmap);
dev_err(dev, "Failed to allocate register map: %d\n", ret);
return ret;
}
cs35l45->dev = dev;
cs35l45->irq = client->irq;
cs35l45->bus_type = CONTROL_BUS_I2C;
cs35l45->i2c_addr = client->addr;
return cs35l45_probe(cs35l45);
}
static void cs35l45_i2c_remove(struct i2c_client *client)
{
struct cs35l45_private *cs35l45 = i2c_get_clientdata(client);
cs35l45_remove(cs35l45);
}
static const struct of_device_id cs35l45_of_match[] = {
{ .compatible = "cirrus,cs35l45" },
{},
};
MODULE_DEVICE_TABLE(of, cs35l45_of_match);
static const struct i2c_device_id cs35l45_id_i2c[] = {
{ "cs35l45", 0 },
{}
};
MODULE_DEVICE_TABLE(i2c, cs35l45_id_i2c);
static struct i2c_driver cs35l45_i2c_driver = {
.driver = {
.name = "cs35l45",
.of_match_table = cs35l45_of_match,
.pm = &cs35l45_pm_ops,
},
.id_table = cs35l45_id_i2c,
.probe = cs35l45_i2c_probe,
.remove = cs35l45_i2c_remove,
};
module_i2c_driver(cs35l45_i2c_driver);
MODULE_DESCRIPTION("I2C CS35L45 driver");
MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_IMPORT_NS(SND_SOC_CS35L45);
| linux-master | sound/soc/codecs/cs35l45-i2c.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* ads117x.c -- Driver for ads1174/8 ADC chips
*
* Copyright 2009 ShotSpotter Inc.
* Author: Graeme Gregory <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/module.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <linux/of.h>
#define ADS117X_RATES (SNDRV_PCM_RATE_8000_48000)
#define ADS117X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
static const struct snd_soc_dapm_widget ads117x_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("Input1"),
SND_SOC_DAPM_INPUT("Input2"),
SND_SOC_DAPM_INPUT("Input3"),
SND_SOC_DAPM_INPUT("Input4"),
SND_SOC_DAPM_INPUT("Input5"),
SND_SOC_DAPM_INPUT("Input6"),
SND_SOC_DAPM_INPUT("Input7"),
SND_SOC_DAPM_INPUT("Input8"),
};
static const struct snd_soc_dapm_route ads117x_dapm_routes[] = {
{ "Capture", NULL, "Input1" },
{ "Capture", NULL, "Input2" },
{ "Capture", NULL, "Input3" },
{ "Capture", NULL, "Input4" },
{ "Capture", NULL, "Input5" },
{ "Capture", NULL, "Input6" },
{ "Capture", NULL, "Input7" },
{ "Capture", NULL, "Input8" },
};
static struct snd_soc_dai_driver ads117x_dai = {
/* ADC */
.name = "ads117x-hifi",
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 32,
.rates = ADS117X_RATES,
.formats = ADS117X_FORMATS,},
};
static const struct snd_soc_component_driver soc_component_dev_ads117x = {
.dapm_widgets = ads117x_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(ads117x_dapm_widgets),
.dapm_routes = ads117x_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(ads117x_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int ads117x_probe(struct platform_device *pdev)
{
return devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_ads117x, &ads117x_dai, 1);
}
#if defined(CONFIG_OF)
static const struct of_device_id ads117x_dt_ids[] = {
{ .compatible = "ti,ads1174" },
{ .compatible = "ti,ads1178" },
{ },
};
MODULE_DEVICE_TABLE(of, ads117x_dt_ids);
#endif
static struct platform_driver ads117x_codec_driver = {
.driver = {
.name = "ads117x-codec",
.of_match_table = of_match_ptr(ads117x_dt_ids),
},
.probe = ads117x_probe,
};
module_platform_driver(ads117x_codec_driver);
MODULE_DESCRIPTION("ASoC ads117x driver");
MODULE_AUTHOR("Graeme Gregory");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/ads117x.c |
// SPDX-License-Identifier: GPL-2.0-only
// cs42l42-sdw.c -- CS42L42 ALSA SoC audio driver SoundWire driver
//
// Copyright (C) 2022 Cirrus Logic, Inc. and
// Cirrus Logic International Semiconductor Ltd.
#include <linux/acpi.h>
#include <linux/device.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/of_irq.h>
#include <linux/pm_runtime.h>
#include <linux/soundwire/sdw.h>
#include <linux/soundwire/sdw_registers.h>
#include <linux/soundwire/sdw_type.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/sdw.h>
#include <sound/soc.h>
#include "cs42l42.h"
#define CS42L42_SDW_CAPTURE_PORT 1
#define CS42L42_SDW_PLAYBACK_PORT 2
/* Register addresses are offset when sent over SoundWire */
#define CS42L42_SDW_ADDR_OFFSET 0x8000
#define CS42L42_SDW_MEM_ACCESS_STATUS 0xd0
#define CS42L42_SDW_MEM_READ_DATA 0xd8
#define CS42L42_SDW_LAST_LATE BIT(3)
#define CS42L42_SDW_CMD_IN_PROGRESS BIT(2)
#define CS42L42_SDW_RDATA_RDY BIT(0)
#define CS42L42_DELAYED_READ_POLL_US 1
#define CS42L42_DELAYED_READ_TIMEOUT_US 100
static const struct snd_soc_dapm_route cs42l42_sdw_audio_map[] = {
/* Playback Path */
{ "HP", NULL, "MIXER" },
{ "MIXER", NULL, "DACSRC" },
{ "DACSRC", NULL, "Playback" },
/* Capture Path */
{ "ADCSRC", NULL, "HS" },
{ "Capture", NULL, "ADCSRC" },
};
static int cs42l42_sdw_dai_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(dai->component);
if (!cs42l42->init_done)
return -ENODEV;
return 0;
}
static int cs42l42_sdw_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(dai->component);
struct sdw_stream_runtime *sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
struct sdw_stream_config stream_config = {0};
struct sdw_port_config port_config = {0};
int ret;
if (!sdw_stream)
return -EINVAL;
/* Needed for PLL configuration when we are notified of new bus config */
cs42l42->sample_rate = params_rate(params);
snd_sdw_params_to_config(substream, params, &stream_config, &port_config);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
port_config.num = CS42L42_SDW_PLAYBACK_PORT;
else
port_config.num = CS42L42_SDW_CAPTURE_PORT;
ret = sdw_stream_add_slave(cs42l42->sdw_peripheral, &stream_config, &port_config, 1,
sdw_stream);
if (ret) {
dev_err(dai->dev, "Failed to add sdw stream: %d\n", ret);
return ret;
}
cs42l42_src_config(dai->component, params_rate(params));
return 0;
}
static int cs42l42_sdw_dai_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(dai->component);
dev_dbg(dai->dev, "dai_prepare: sclk=%u rate=%u\n", cs42l42->sclk, cs42l42->sample_rate);
if (!cs42l42->sclk || !cs42l42->sample_rate)
return -EINVAL;
/*
* At this point we know the sample rate from hw_params, and the SWIRE_CLK from bus_config()
* callback. This could only fail if the ACPI or machine driver are misconfigured to allow
* an unsupported SWIRE_CLK and sample_rate combination.
*/
return cs42l42_pll_config(dai->component, cs42l42->sclk, cs42l42->sample_rate);
}
static int cs42l42_sdw_dai_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(dai->component);
struct sdw_stream_runtime *sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
sdw_stream_remove_slave(cs42l42->sdw_peripheral, sdw_stream);
cs42l42->sample_rate = 0;
return 0;
}
static int cs42l42_sdw_port_prep(struct sdw_slave *slave,
struct sdw_prepare_ch *prepare_ch,
enum sdw_port_prep_ops state)
{
struct cs42l42_private *cs42l42 = dev_get_drvdata(&slave->dev);
unsigned int pdn_mask;
if (prepare_ch->num == CS42L42_SDW_PLAYBACK_PORT)
pdn_mask = CS42L42_HP_PDN_MASK;
else
pdn_mask = CS42L42_ADC_PDN_MASK;
if (state == SDW_OPS_PORT_PRE_PREP) {
dev_dbg(cs42l42->dev, "Prep Port pdn_mask:%x\n", pdn_mask);
regmap_clear_bits(cs42l42->regmap, CS42L42_PWR_CTL1, pdn_mask);
usleep_range(CS42L42_HP_ADC_EN_TIME_US, CS42L42_HP_ADC_EN_TIME_US + 1000);
} else if (state == SDW_OPS_PORT_POST_DEPREP) {
dev_dbg(cs42l42->dev, "Deprep Port pdn_mask:%x\n", pdn_mask);
regmap_set_bits(cs42l42->regmap, CS42L42_PWR_CTL1, pdn_mask);
}
return 0;
}
static int cs42l42_sdw_dai_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
int direction)
{
snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
return 0;
}
static void cs42l42_sdw_dai_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
snd_soc_dai_set_dma_data(dai, substream, NULL);
}
static const struct snd_soc_dai_ops cs42l42_sdw_dai_ops = {
.startup = cs42l42_sdw_dai_startup,
.shutdown = cs42l42_sdw_dai_shutdown,
.hw_params = cs42l42_sdw_dai_hw_params,
.prepare = cs42l42_sdw_dai_prepare,
.hw_free = cs42l42_sdw_dai_hw_free,
.mute_stream = cs42l42_mute_stream,
.set_stream = cs42l42_sdw_dai_set_sdw_stream,
};
static struct snd_soc_dai_driver cs42l42_sdw_dai = {
.name = "cs42l42-sdw",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
/* Restrict which rates and formats are supported */
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S32_LE,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 1,
/* Restrict which rates and formats are supported */
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S32_LE,
},
.symmetric_rate = 1,
.ops = &cs42l42_sdw_dai_ops,
};
static int cs42l42_sdw_poll_status(struct sdw_slave *peripheral, u8 mask, u8 match)
{
int ret, sdwret;
ret = read_poll_timeout(sdw_read_no_pm, sdwret,
(sdwret < 0) || ((sdwret & mask) == match),
CS42L42_DELAYED_READ_POLL_US, CS42L42_DELAYED_READ_TIMEOUT_US,
false, peripheral, CS42L42_SDW_MEM_ACCESS_STATUS);
if (ret == 0)
ret = sdwret;
if (ret < 0)
dev_err(&peripheral->dev, "MEM_ACCESS_STATUS & %#x for %#x fail: %d\n",
mask, match, ret);
return ret;
}
static int cs42l42_sdw_read(void *context, unsigned int reg, unsigned int *val)
{
struct sdw_slave *peripheral = context;
u8 data;
int ret;
reg += CS42L42_SDW_ADDR_OFFSET;
ret = cs42l42_sdw_poll_status(peripheral, CS42L42_SDW_CMD_IN_PROGRESS, 0);
if (ret < 0)
return ret;
ret = sdw_read_no_pm(peripheral, reg);
if (ret < 0) {
dev_err(&peripheral->dev, "Failed to issue read @0x%x: %d\n", reg, ret);
return ret;
}
data = (u8)ret; /* possible non-delayed read value */
ret = sdw_read_no_pm(peripheral, CS42L42_SDW_MEM_ACCESS_STATUS);
if (ret < 0) {
dev_err(&peripheral->dev, "Failed to read MEM_ACCESS_STATUS: %d\n", ret);
return ret;
}
/* If read was not delayed we already have the result */
if ((ret & CS42L42_SDW_LAST_LATE) == 0) {
*val = data;
return 0;
}
/* Poll for delayed read completion */
if ((ret & CS42L42_SDW_RDATA_RDY) == 0) {
ret = cs42l42_sdw_poll_status(peripheral,
CS42L42_SDW_RDATA_RDY, CS42L42_SDW_RDATA_RDY);
if (ret < 0)
return ret;
}
ret = sdw_read_no_pm(peripheral, CS42L42_SDW_MEM_READ_DATA);
if (ret < 0) {
dev_err(&peripheral->dev, "Failed to read READ_DATA: %d\n", ret);
return ret;
}
*val = (u8)ret;
return 0;
}
static int cs42l42_sdw_write(void *context, unsigned int reg, unsigned int val)
{
struct sdw_slave *peripheral = context;
int ret;
ret = cs42l42_sdw_poll_status(peripheral, CS42L42_SDW_CMD_IN_PROGRESS, 0);
if (ret < 0)
return ret;
return sdw_write_no_pm(peripheral, reg + CS42L42_SDW_ADDR_OFFSET, (u8)val);
}
/* Initialise cs42l42 using SoundWire - this is only called once, during initialisation */
static void cs42l42_sdw_init(struct sdw_slave *peripheral)
{
struct cs42l42_private *cs42l42 = dev_get_drvdata(&peripheral->dev);
int ret;
regcache_cache_only(cs42l42->regmap, false);
ret = cs42l42_init(cs42l42);
if (ret < 0) {
regcache_cache_only(cs42l42->regmap, true);
goto err;
}
/* Write out any cached changes that happened between probe and attach */
ret = regcache_sync(cs42l42->regmap);
if (ret < 0)
dev_warn(cs42l42->dev, "Failed to sync cache: %d\n", ret);
/* Disable internal logic that makes clock-stop conditional */
regmap_clear_bits(cs42l42->regmap, CS42L42_PWR_CTL3, CS42L42_SW_CLK_STP_STAT_SEL_MASK);
err:
/* This cancels the pm_runtime_get_noresume() call from cs42l42_sdw_probe(). */
pm_runtime_put_autosuspend(cs42l42->dev);
}
static int cs42l42_sdw_read_prop(struct sdw_slave *peripheral)
{
struct cs42l42_private *cs42l42 = dev_get_drvdata(&peripheral->dev);
struct sdw_slave_prop *prop = &peripheral->prop;
struct sdw_dpn_prop *ports;
ports = devm_kcalloc(cs42l42->dev, 2, sizeof(*ports), GFP_KERNEL);
if (!ports)
return -ENOMEM;
prop->source_ports = BIT(CS42L42_SDW_CAPTURE_PORT);
prop->sink_ports = BIT(CS42L42_SDW_PLAYBACK_PORT);
prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
/* DP1 - capture */
ports[0].num = CS42L42_SDW_CAPTURE_PORT,
ports[0].type = SDW_DPN_FULL,
ports[0].ch_prep_timeout = 10,
prop->src_dpn_prop = &ports[0];
/* DP2 - playback */
ports[1].num = CS42L42_SDW_PLAYBACK_PORT,
ports[1].type = SDW_DPN_FULL,
ports[1].ch_prep_timeout = 10,
prop->sink_dpn_prop = &ports[1];
return 0;
}
static int cs42l42_sdw_update_status(struct sdw_slave *peripheral,
enum sdw_slave_status status)
{
struct cs42l42_private *cs42l42 = dev_get_drvdata(&peripheral->dev);
switch (status) {
case SDW_SLAVE_ATTACHED:
dev_dbg(cs42l42->dev, "ATTACHED\n");
/*
* The SoundWire core can report stale ATTACH notifications
* if we hard-reset CS42L42 in probe() but it had already been
* enumerated. Reject the ATTACH if we haven't yet seen an
* UNATTACH report for the device being in reset.
*/
if (cs42l42->sdw_waiting_first_unattach)
break;
/*
* Initialise codec, this only needs to be done once.
* When resuming from suspend, resume callback will handle re-init of codec,
* using regcache_sync().
*/
if (!cs42l42->init_done)
cs42l42_sdw_init(peripheral);
break;
case SDW_SLAVE_UNATTACHED:
dev_dbg(cs42l42->dev, "UNATTACHED\n");
if (cs42l42->sdw_waiting_first_unattach) {
/*
* SoundWire core has seen that CS42L42 is not on
* the bus so release RESET and wait for ATTACH.
*/
cs42l42->sdw_waiting_first_unattach = false;
gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
}
break;
default:
break;
}
return 0;
}
static int cs42l42_sdw_bus_config(struct sdw_slave *peripheral,
struct sdw_bus_params *params)
{
struct cs42l42_private *cs42l42 = dev_get_drvdata(&peripheral->dev);
unsigned int new_sclk = params->curr_dr_freq / 2;
/* The cs42l42 cannot support a glitchless SWIRE_CLK change. */
if ((new_sclk != cs42l42->sclk) && cs42l42->stream_use) {
dev_warn(cs42l42->dev, "Rejected SCLK change while audio active\n");
return -EBUSY;
}
cs42l42->sclk = new_sclk;
dev_dbg(cs42l42->dev, "bus_config: sclk=%u c=%u r=%u\n",
cs42l42->sclk, params->col, params->row);
return 0;
}
static const struct sdw_slave_ops cs42l42_sdw_ops = {
/* No interrupt callback because only hardware INT is supported for Jack Detect in the CS42L42 */
.read_prop = cs42l42_sdw_read_prop,
.update_status = cs42l42_sdw_update_status,
.bus_config = cs42l42_sdw_bus_config,
.port_prep = cs42l42_sdw_port_prep,
};
static int __maybe_unused cs42l42_sdw_runtime_suspend(struct device *dev)
{
struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
dev_dbg(dev, "Runtime suspend\n");
if (!cs42l42->init_done)
return 0;
/* The host controller could suspend, which would mean no register access */
regcache_cache_only(cs42l42->regmap, true);
return 0;
}
static const struct reg_sequence __maybe_unused cs42l42_soft_reboot_seq[] = {
REG_SEQ0(CS42L42_SOFT_RESET_REBOOT, 0x1e),
};
static int __maybe_unused cs42l42_sdw_handle_unattach(struct cs42l42_private *cs42l42)
{
struct sdw_slave *peripheral = cs42l42->sdw_peripheral;
if (!peripheral->unattach_request)
return 0;
/* Cannot access registers until master re-attaches. */
dev_dbg(&peripheral->dev, "Wait for initialization_complete\n");
if (!wait_for_completion_timeout(&peripheral->initialization_complete,
msecs_to_jiffies(5000))) {
dev_err(&peripheral->dev, "initialization_complete timed out\n");
return -ETIMEDOUT;
}
peripheral->unattach_request = 0;
/*
* After a bus reset there must be a reconfiguration reset to
* reinitialize the internal state of CS42L42.
*/
regmap_multi_reg_write_bypassed(cs42l42->regmap,
cs42l42_soft_reboot_seq,
ARRAY_SIZE(cs42l42_soft_reboot_seq));
usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
regcache_mark_dirty(cs42l42->regmap);
return 0;
}
static int __maybe_unused cs42l42_sdw_runtime_resume(struct device *dev)
{
static const unsigned int ts_dbnce_ms[] = { 0, 125, 250, 500, 750, 1000, 1250, 1500};
struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
unsigned int dbnce;
int ret;
dev_dbg(dev, "Runtime resume\n");
if (!cs42l42->init_done)
return 0;
ret = cs42l42_sdw_handle_unattach(cs42l42);
if (ret < 0) {
return ret;
} else if (ret > 0) {
dbnce = max(cs42l42->ts_dbnc_rise, cs42l42->ts_dbnc_fall);
if (dbnce > 0)
msleep(ts_dbnce_ms[dbnce]);
}
regcache_cache_only(cs42l42->regmap, false);
/* Sync LATCH_TO_VP first so the VP domain registers sync correctly */
regcache_sync_region(cs42l42->regmap, CS42L42_MIC_DET_CTL1, CS42L42_MIC_DET_CTL1);
regcache_sync(cs42l42->regmap);
return 0;
}
static int __maybe_unused cs42l42_sdw_resume(struct device *dev)
{
struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
int ret;
dev_dbg(dev, "System resume\n");
/* Power-up so it can re-enumerate */
ret = cs42l42_resume(dev);
if (ret)
return ret;
/* Wait for re-attach */
ret = cs42l42_sdw_handle_unattach(cs42l42);
if (ret < 0)
return ret;
cs42l42_resume_restore(dev);
return 0;
}
static int cs42l42_sdw_probe(struct sdw_slave *peripheral, const struct sdw_device_id *id)
{
struct snd_soc_component_driver *component_drv;
struct device *dev = &peripheral->dev;
struct cs42l42_private *cs42l42;
struct regmap_config *regmap_conf;
struct regmap *regmap;
int irq, ret;
cs42l42 = devm_kzalloc(dev, sizeof(*cs42l42), GFP_KERNEL);
if (!cs42l42)
return -ENOMEM;
if (has_acpi_companion(dev))
irq = acpi_dev_gpio_irq_get(ACPI_COMPANION(dev), 0);
else
irq = of_irq_get(dev->of_node, 0);
if (irq == -ENOENT)
irq = 0;
else if (irq < 0)
return dev_err_probe(dev, irq, "Failed to get IRQ\n");
regmap_conf = devm_kmemdup(dev, &cs42l42_regmap, sizeof(cs42l42_regmap), GFP_KERNEL);
if (!regmap_conf)
return -ENOMEM;
regmap_conf->reg_bits = 16;
regmap_conf->num_ranges = 0;
regmap_conf->reg_read = cs42l42_sdw_read;
regmap_conf->reg_write = cs42l42_sdw_write;
regmap = devm_regmap_init(dev, NULL, peripheral, regmap_conf);
if (IS_ERR(regmap))
return dev_err_probe(dev, PTR_ERR(regmap), "Failed to allocate register map\n");
/* Start in cache-only until device is enumerated */
regcache_cache_only(regmap, true);
component_drv = devm_kmemdup(dev,
&cs42l42_soc_component,
sizeof(cs42l42_soc_component),
GFP_KERNEL);
if (!component_drv)
return -ENOMEM;
component_drv->dapm_routes = cs42l42_sdw_audio_map;
component_drv->num_dapm_routes = ARRAY_SIZE(cs42l42_sdw_audio_map);
cs42l42->dev = dev;
cs42l42->regmap = regmap;
cs42l42->sdw_peripheral = peripheral;
cs42l42->irq = irq;
cs42l42->devid = CS42L42_CHIP_ID;
/*
* pm_runtime is needed to control bus manager suspend, and to
* recover from an unattach_request when the manager suspends.
*/
pm_runtime_set_autosuspend_delay(cs42l42->dev, 3000);
pm_runtime_use_autosuspend(cs42l42->dev);
pm_runtime_mark_last_busy(cs42l42->dev);
pm_runtime_set_active(cs42l42->dev);
pm_runtime_get_noresume(cs42l42->dev);
pm_runtime_enable(cs42l42->dev);
ret = cs42l42_common_probe(cs42l42, component_drv, &cs42l42_sdw_dai);
if (ret < 0)
return ret;
return 0;
}
static int cs42l42_sdw_remove(struct sdw_slave *peripheral)
{
struct cs42l42_private *cs42l42 = dev_get_drvdata(&peripheral->dev);
cs42l42_common_remove(cs42l42);
pm_runtime_disable(cs42l42->dev);
return 0;
}
static const struct dev_pm_ops cs42l42_sdw_pm = {
SET_SYSTEM_SLEEP_PM_OPS(cs42l42_suspend, cs42l42_sdw_resume)
SET_RUNTIME_PM_OPS(cs42l42_sdw_runtime_suspend, cs42l42_sdw_runtime_resume, NULL)
};
static const struct sdw_device_id cs42l42_sdw_id[] = {
SDW_SLAVE_ENTRY(0x01FA, 0x4242, 0),
{},
};
MODULE_DEVICE_TABLE(sdw, cs42l42_sdw_id);
static struct sdw_driver cs42l42_sdw_driver = {
.driver = {
.name = "cs42l42-sdw",
.pm = &cs42l42_sdw_pm,
},
.probe = cs42l42_sdw_probe,
.remove = cs42l42_sdw_remove,
.ops = &cs42l42_sdw_ops,
.id_table = cs42l42_sdw_id,
};
module_sdw_driver(cs42l42_sdw_driver);
MODULE_DESCRIPTION("ASoC CS42L42 SoundWire driver");
MODULE_AUTHOR("Richard Fitzgerald <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_IMPORT_NS(SND_SOC_CS42L42_CORE);
| linux-master | sound/soc/codecs/cs42l42-sdw.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* wm8990.c -- WM8990 ALSA Soc Audio driver
*
* Copyright 2008 Wolfson Microelectronics PLC.
* Author: Liam Girdwood <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <asm/div64.h>
#include "wm8990.h"
/* codec private data */
struct wm8990_priv {
struct regmap *regmap;
unsigned int sysclk;
unsigned int pcmclk;
};
#define wm8990_reset(c) snd_soc_component_write(c, WM8990_RESET, 0)
static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0);
static const DECLARE_TLV_DB_SCALE(out_mix_tlv, 0, -2100, 0);
static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0);
static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0);
static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0);
static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0);
static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
int reg = mc->reg;
int ret;
u16 val;
ret = snd_soc_put_volsw(kcontrol, ucontrol);
if (ret < 0)
return ret;
/* now hit the volume update bits (always bit 8) */
val = snd_soc_component_read(component, reg);
return snd_soc_component_write(component, reg, val | 0x0100);
}
#define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert,\
tlv_array) \
SOC_SINGLE_EXT_TLV(xname, reg, shift, max, invert, \
snd_soc_get_volsw, wm899x_outpga_put_volsw_vu, tlv_array)
static const char *wm8990_digital_sidetone[] =
{"None", "Left ADC", "Right ADC", "Reserved"};
static SOC_ENUM_SINGLE_DECL(wm8990_left_digital_sidetone_enum,
WM8990_DIGITAL_SIDE_TONE,
WM8990_ADC_TO_DACL_SHIFT,
wm8990_digital_sidetone);
static SOC_ENUM_SINGLE_DECL(wm8990_right_digital_sidetone_enum,
WM8990_DIGITAL_SIDE_TONE,
WM8990_ADC_TO_DACR_SHIFT,
wm8990_digital_sidetone);
static const char *wm8990_adcmode[] =
{"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"};
static SOC_ENUM_SINGLE_DECL(wm8990_right_adcmode_enum,
WM8990_ADC_CTRL,
WM8990_ADC_HPF_CUT_SHIFT,
wm8990_adcmode);
static const struct snd_kcontrol_new wm8990_snd_controls[] = {
/* INMIXL */
SOC_SINGLE("LIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L12MNBST_BIT, 1, 0),
SOC_SINGLE("LIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L34MNBST_BIT, 1, 0),
/* INMIXR */
SOC_SINGLE("RIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R12MNBST_BIT, 1, 0),
SOC_SINGLE("RIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R34MNBST_BIT, 1, 0),
/* LOMIX */
SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER3,
WM8990_LLI3LOVOL_SHIFT, WM8990_LLI3LOVOL_MASK, 1, out_mix_tlv),
SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
WM8990_LR12LOVOL_SHIFT, WM8990_LR12LOVOL_MASK, 1, out_mix_tlv),
SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
WM8990_LL12LOVOL_SHIFT, WM8990_LL12LOVOL_MASK, 1, out_mix_tlv),
SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER5,
WM8990_LRI3LOVOL_SHIFT, WM8990_LRI3LOVOL_MASK, 1, out_mix_tlv),
SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv),
SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv),
/* ROMIX */
SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER4,
WM8990_RRI3ROVOL_SHIFT, WM8990_RRI3ROVOL_MASK, 1, out_mix_tlv),
SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
WM8990_RL12ROVOL_SHIFT, WM8990_RL12ROVOL_MASK, 1, out_mix_tlv),
SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
WM8990_RR12ROVOL_SHIFT, WM8990_RR12ROVOL_MASK, 1, out_mix_tlv),
SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER6,
WM8990_RLI3ROVOL_SHIFT, WM8990_RLI3ROVOL_MASK, 1, out_mix_tlv),
SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER6,
WM8990_RLBROVOL_SHIFT, WM8990_RLBROVOL_MASK, 1, out_mix_tlv),
SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER6,
WM8990_RRBROVOL_SHIFT, WM8990_RRBROVOL_MASK, 1, out_mix_tlv),
/* LOUT */
SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8990_LEFT_OUTPUT_VOLUME,
WM8990_LOUTVOL_SHIFT, WM8990_LOUTVOL_MASK, 0, out_pga_tlv),
SOC_SINGLE("LOUT ZC", WM8990_LEFT_OUTPUT_VOLUME, WM8990_LOZC_BIT, 1, 0),
/* ROUT */
SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8990_RIGHT_OUTPUT_VOLUME,
WM8990_ROUTVOL_SHIFT, WM8990_ROUTVOL_MASK, 0, out_pga_tlv),
SOC_SINGLE("ROUT ZC", WM8990_RIGHT_OUTPUT_VOLUME, WM8990_ROZC_BIT, 1, 0),
/* LOPGA */
SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8990_LEFT_OPGA_VOLUME,
WM8990_LOPGAVOL_SHIFT, WM8990_LOPGAVOL_MASK, 0, out_pga_tlv),
SOC_SINGLE("LOPGA ZC Switch", WM8990_LEFT_OPGA_VOLUME,
WM8990_LOPGAZC_BIT, 1, 0),
/* ROPGA */
SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8990_RIGHT_OPGA_VOLUME,
WM8990_ROPGAVOL_SHIFT, WM8990_ROPGAVOL_MASK, 0, out_pga_tlv),
SOC_SINGLE("ROPGA ZC Switch", WM8990_RIGHT_OPGA_VOLUME,
WM8990_ROPGAZC_BIT, 1, 0),
SOC_SINGLE("LON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
WM8990_LONMUTE_BIT, 1, 0),
SOC_SINGLE("LOP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
WM8990_LOPMUTE_BIT, 1, 0),
SOC_SINGLE("LOP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME,
WM8990_LOATTN_BIT, 1, 0),
SOC_SINGLE("RON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
WM8990_RONMUTE_BIT, 1, 0),
SOC_SINGLE("ROP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
WM8990_ROPMUTE_BIT, 1, 0),
SOC_SINGLE("ROP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME,
WM8990_ROATTN_BIT, 1, 0),
SOC_SINGLE("OUT3 Mute Switch", WM8990_OUT3_4_VOLUME,
WM8990_OUT3MUTE_BIT, 1, 0),
SOC_SINGLE("OUT3 Attenuation Switch", WM8990_OUT3_4_VOLUME,
WM8990_OUT3ATTN_BIT, 1, 0),
SOC_SINGLE("OUT4 Mute Switch", WM8990_OUT3_4_VOLUME,
WM8990_OUT4MUTE_BIT, 1, 0),
SOC_SINGLE("OUT4 Attenuation Switch", WM8990_OUT3_4_VOLUME,
WM8990_OUT4ATTN_BIT, 1, 0),
SOC_SINGLE("Speaker Mode Switch", WM8990_CLASSD1,
WM8990_CDMODE_BIT, 1, 0),
SOC_SINGLE("Speaker Output Attenuation Volume", WM8990_SPEAKER_VOLUME,
WM8990_SPKATTN_SHIFT, WM8990_SPKATTN_MASK, 0),
SOC_SINGLE("Speaker DC Boost Volume", WM8990_CLASSD3,
WM8990_DCGAIN_SHIFT, WM8990_DCGAIN_MASK, 0),
SOC_SINGLE("Speaker AC Boost Volume", WM8990_CLASSD3,
WM8990_ACGAIN_SHIFT, WM8990_ACGAIN_MASK, 0),
SOC_SINGLE_TLV("Speaker Volume", WM8990_CLASSD4,
WM8990_SPKVOL_SHIFT, WM8990_SPKVOL_MASK, 0, out_pga_tlv),
SOC_SINGLE("Speaker ZC Switch", WM8990_CLASSD4,
WM8990_SPKZC_SHIFT, WM8990_SPKZC_MASK, 0),
SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume",
WM8990_LEFT_DAC_DIGITAL_VOLUME,
WM8990_DACL_VOL_SHIFT,
WM8990_DACL_VOL_MASK,
0,
out_dac_tlv),
SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume",
WM8990_RIGHT_DAC_DIGITAL_VOLUME,
WM8990_DACR_VOL_SHIFT,
WM8990_DACR_VOL_MASK,
0,
out_dac_tlv),
SOC_ENUM("Left Digital Sidetone", wm8990_left_digital_sidetone_enum),
SOC_ENUM("Right Digital Sidetone", wm8990_right_digital_sidetone_enum),
SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE,
WM8990_ADCL_DAC_SVOL_SHIFT, WM8990_ADCL_DAC_SVOL_MASK, 0,
out_sidetone_tlv),
SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE,
WM8990_ADCR_DAC_SVOL_SHIFT, WM8990_ADCR_DAC_SVOL_MASK, 0,
out_sidetone_tlv),
SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8990_ADC_CTRL,
WM8990_ADC_HPF_ENA_BIT, 1, 0),
SOC_ENUM("ADC HPF Mode", wm8990_right_adcmode_enum),
SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume",
WM8990_LEFT_ADC_DIGITAL_VOLUME,
WM8990_ADCL_VOL_SHIFT,
WM8990_ADCL_VOL_MASK,
0,
in_adc_tlv),
SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume",
WM8990_RIGHT_ADC_DIGITAL_VOLUME,
WM8990_ADCR_VOL_SHIFT,
WM8990_ADCR_VOL_MASK,
0,
in_adc_tlv),
SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume",
WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
WM8990_LIN12VOL_SHIFT,
WM8990_LIN12VOL_MASK,
0,
in_pga_tlv),
SOC_SINGLE("LIN12 ZC Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
WM8990_LI12ZC_BIT, 1, 0),
SOC_SINGLE("LIN12 Mute Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
WM8990_LI12MUTE_BIT, 1, 0),
SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume",
WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
WM8990_LIN34VOL_SHIFT,
WM8990_LIN34VOL_MASK,
0,
in_pga_tlv),
SOC_SINGLE("LIN34 ZC Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
WM8990_LI34ZC_BIT, 1, 0),
SOC_SINGLE("LIN34 Mute Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
WM8990_LI34MUTE_BIT, 1, 0),
SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume",
WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
WM8990_RIN12VOL_SHIFT,
WM8990_RIN12VOL_MASK,
0,
in_pga_tlv),
SOC_SINGLE("RIN12 ZC Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
WM8990_RI12ZC_BIT, 1, 0),
SOC_SINGLE("RIN12 Mute Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
WM8990_RI12MUTE_BIT, 1, 0),
SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume",
WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
WM8990_RIN34VOL_SHIFT,
WM8990_RIN34VOL_MASK,
0,
in_pga_tlv),
SOC_SINGLE("RIN34 ZC Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
WM8990_RI34ZC_BIT, 1, 0),
SOC_SINGLE("RIN34 Mute Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
WM8990_RI34MUTE_BIT, 1, 0),
};
/*
* _DAPM_ Controls
*/
static int outmixer_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
u32 reg_shift = kcontrol->private_value & 0xfff;
int ret = 0;
u16 reg;
switch (reg_shift) {
case WM8990_SPEAKER_MIXER | (WM8990_LDSPK_BIT << 8) :
reg = snd_soc_component_read(component, WM8990_OUTPUT_MIXER1);
if (reg & WM8990_LDLO) {
printk(KERN_WARNING
"Cannot set as Output Mixer 1 LDLO Set\n");
ret = -1;
}
break;
case WM8990_SPEAKER_MIXER | (WM8990_RDSPK_BIT << 8):
reg = snd_soc_component_read(component, WM8990_OUTPUT_MIXER2);
if (reg & WM8990_RDRO) {
printk(KERN_WARNING
"Cannot set as Output Mixer 2 RDRO Set\n");
ret = -1;
}
break;
case WM8990_OUTPUT_MIXER1 | (WM8990_LDLO_BIT << 8):
reg = snd_soc_component_read(component, WM8990_SPEAKER_MIXER);
if (reg & WM8990_LDSPK) {
printk(KERN_WARNING
"Cannot set as Speaker Mixer LDSPK Set\n");
ret = -1;
}
break;
case WM8990_OUTPUT_MIXER2 | (WM8990_RDRO_BIT << 8):
reg = snd_soc_component_read(component, WM8990_SPEAKER_MIXER);
if (reg & WM8990_RDSPK) {
printk(KERN_WARNING
"Cannot set as Speaker Mixer RDSPK Set\n");
ret = -1;
}
break;
}
return ret;
}
/* INMIX dB values */
static const DECLARE_TLV_DB_SCALE(in_mix_tlv, -1200, 600, 0);
/* Left In PGA Connections */
static const struct snd_kcontrol_new wm8990_dapm_lin12_pga_controls[] = {
SOC_DAPM_SINGLE("LIN1 Switch", WM8990_INPUT_MIXER2, WM8990_LMN1_BIT, 1, 0),
SOC_DAPM_SINGLE("LIN2 Switch", WM8990_INPUT_MIXER2, WM8990_LMP2_BIT, 1, 0),
};
static const struct snd_kcontrol_new wm8990_dapm_lin34_pga_controls[] = {
SOC_DAPM_SINGLE("LIN3 Switch", WM8990_INPUT_MIXER2, WM8990_LMN3_BIT, 1, 0),
SOC_DAPM_SINGLE("LIN4 Switch", WM8990_INPUT_MIXER2, WM8990_LMP4_BIT, 1, 0),
};
/* Right In PGA Connections */
static const struct snd_kcontrol_new wm8990_dapm_rin12_pga_controls[] = {
SOC_DAPM_SINGLE("RIN1 Switch", WM8990_INPUT_MIXER2, WM8990_RMN1_BIT, 1, 0),
SOC_DAPM_SINGLE("RIN2 Switch", WM8990_INPUT_MIXER2, WM8990_RMP2_BIT, 1, 0),
};
static const struct snd_kcontrol_new wm8990_dapm_rin34_pga_controls[] = {
SOC_DAPM_SINGLE("RIN3 Switch", WM8990_INPUT_MIXER2, WM8990_RMN3_BIT, 1, 0),
SOC_DAPM_SINGLE("RIN4 Switch", WM8990_INPUT_MIXER2, WM8990_RMP4_BIT, 1, 0),
};
/* INMIXL */
static const struct snd_kcontrol_new wm8990_dapm_inmixl_controls[] = {
SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8990_INPUT_MIXER3,
WM8990_LDBVOL_SHIFT, WM8990_LDBVOL_MASK, 0, in_mix_tlv),
SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8990_INPUT_MIXER5, WM8990_LI2BVOL_SHIFT,
7, 0, in_mix_tlv),
SOC_DAPM_SINGLE("LINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT,
1, 0),
SOC_DAPM_SINGLE("LINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT,
1, 0),
};
/* INMIXR */
static const struct snd_kcontrol_new wm8990_dapm_inmixr_controls[] = {
SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8990_INPUT_MIXER4,
WM8990_RDBVOL_SHIFT, WM8990_RDBVOL_MASK, 0, in_mix_tlv),
SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8990_INPUT_MIXER6, WM8990_RI2BVOL_SHIFT,
7, 0, in_mix_tlv),
SOC_DAPM_SINGLE("RINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT,
1, 0),
SOC_DAPM_SINGLE("RINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT,
1, 0),
};
/* AINLMUX */
static const char *wm8990_ainlmux[] =
{"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"};
static SOC_ENUM_SINGLE_DECL(wm8990_ainlmux_enum,
WM8990_INPUT_MIXER1, WM8990_AINLMODE_SHIFT,
wm8990_ainlmux);
static const struct snd_kcontrol_new wm8990_dapm_ainlmux_controls =
SOC_DAPM_ENUM("Route", wm8990_ainlmux_enum);
/* DIFFINL */
/* AINRMUX */
static const char *wm8990_ainrmux[] =
{"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"};
static SOC_ENUM_SINGLE_DECL(wm8990_ainrmux_enum,
WM8990_INPUT_MIXER1, WM8990_AINRMODE_SHIFT,
wm8990_ainrmux);
static const struct snd_kcontrol_new wm8990_dapm_ainrmux_controls =
SOC_DAPM_ENUM("Route", wm8990_ainrmux_enum);
/* LOMIX */
static const struct snd_kcontrol_new wm8990_dapm_lomix_controls[] = {
SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER1,
WM8990_LRBLO_BIT, 1, 0),
SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER1,
WM8990_LLBLO_BIT, 1, 0),
SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER1,
WM8990_LRI3LO_BIT, 1, 0),
SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER1,
WM8990_LLI3LO_BIT, 1, 0),
SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1,
WM8990_LR12LO_BIT, 1, 0),
SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1,
WM8990_LL12LO_BIT, 1, 0),
SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8990_OUTPUT_MIXER1,
WM8990_LDLO_BIT, 1, 0),
};
/* ROMIX */
static const struct snd_kcontrol_new wm8990_dapm_romix_controls[] = {
SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER2,
WM8990_RLBRO_BIT, 1, 0),
SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER2,
WM8990_RRBRO_BIT, 1, 0),
SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER2,
WM8990_RLI3RO_BIT, 1, 0),
SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER2,
WM8990_RRI3RO_BIT, 1, 0),
SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2,
WM8990_RL12RO_BIT, 1, 0),
SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2,
WM8990_RR12RO_BIT, 1, 0),
SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8990_OUTPUT_MIXER2,
WM8990_RDRO_BIT, 1, 0),
};
/* LONMIX */
static const struct snd_kcontrol_new wm8990_dapm_lonmix_controls[] = {
SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1,
WM8990_LLOPGALON_BIT, 1, 0),
SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER1,
WM8990_LROPGALON_BIT, 1, 0),
SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8990_LINE_MIXER1,
WM8990_LOPLON_BIT, 1, 0),
};
/* LOPMIX */
static const struct snd_kcontrol_new wm8990_dapm_lopmix_controls[] = {
SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER1,
WM8990_LR12LOP_BIT, 1, 0),
SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER1,
WM8990_LL12LOP_BIT, 1, 0),
SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1,
WM8990_LLOPGALOP_BIT, 1, 0),
};
/* RONMIX */
static const struct snd_kcontrol_new wm8990_dapm_ronmix_controls[] = {
SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2,
WM8990_RROPGARON_BIT, 1, 0),
SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER2,
WM8990_RLOPGARON_BIT, 1, 0),
SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8990_LINE_MIXER2,
WM8990_ROPRON_BIT, 1, 0),
};
/* ROPMIX */
static const struct snd_kcontrol_new wm8990_dapm_ropmix_controls[] = {
SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER2,
WM8990_RL12ROP_BIT, 1, 0),
SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER2,
WM8990_RR12ROP_BIT, 1, 0),
SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2,
WM8990_RROPGAROP_BIT, 1, 0),
};
/* OUT3MIX */
static const struct snd_kcontrol_new wm8990_dapm_out3mix_controls[] = {
SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER,
WM8990_LI4O3_BIT, 1, 0),
SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8990_OUT3_4_MIXER,
WM8990_LPGAO3_BIT, 1, 0),
};
/* OUT4MIX */
static const struct snd_kcontrol_new wm8990_dapm_out4mix_controls[] = {
SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8990_OUT3_4_MIXER,
WM8990_RPGAO4_BIT, 1, 0),
SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER,
WM8990_RI4O4_BIT, 1, 0),
};
/* SPKMIX */
static const struct snd_kcontrol_new wm8990_dapm_spkmix_controls[] = {
SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8990_SPEAKER_MIXER,
WM8990_LI2SPK_BIT, 1, 0),
SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8990_SPEAKER_MIXER,
WM8990_LB2SPK_BIT, 1, 0),
SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8990_SPEAKER_MIXER,
WM8990_LOPGASPK_BIT, 1, 0),
SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8990_SPEAKER_MIXER,
WM8990_LDSPK_BIT, 1, 0),
SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8990_SPEAKER_MIXER,
WM8990_RDSPK_BIT, 1, 0),
SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8990_SPEAKER_MIXER,
WM8990_ROPGASPK_BIT, 1, 0),
SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8990_SPEAKER_MIXER,
WM8990_RL12ROP_BIT, 1, 0),
SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8990_SPEAKER_MIXER,
WM8990_RI2SPK_BIT, 1, 0),
};
static const struct snd_soc_dapm_widget wm8990_dapm_widgets[] = {
/* Input Side */
/* Input Lines */
SND_SOC_DAPM_INPUT("LIN1"),
SND_SOC_DAPM_INPUT("LIN2"),
SND_SOC_DAPM_INPUT("LIN3"),
SND_SOC_DAPM_INPUT("LIN4/RXN"),
SND_SOC_DAPM_INPUT("RIN3"),
SND_SOC_DAPM_INPUT("RIN4/RXP"),
SND_SOC_DAPM_INPUT("RIN1"),
SND_SOC_DAPM_INPUT("RIN2"),
SND_SOC_DAPM_INPUT("Internal ADC Source"),
SND_SOC_DAPM_SUPPLY("INL", WM8990_POWER_MANAGEMENT_2, WM8990_AINL_ENA_BIT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("INR", WM8990_POWER_MANAGEMENT_2, WM8990_AINR_ENA_BIT, 0,
NULL, 0),
/* DACs */
SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8990_POWER_MANAGEMENT_2,
WM8990_ADCL_ENA_BIT, 0),
SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8990_POWER_MANAGEMENT_2,
WM8990_ADCR_ENA_BIT, 0),
/* Input PGAs */
SND_SOC_DAPM_MIXER("LIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN12_ENA_BIT,
0, &wm8990_dapm_lin12_pga_controls[0],
ARRAY_SIZE(wm8990_dapm_lin12_pga_controls)),
SND_SOC_DAPM_MIXER("LIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN34_ENA_BIT,
0, &wm8990_dapm_lin34_pga_controls[0],
ARRAY_SIZE(wm8990_dapm_lin34_pga_controls)),
SND_SOC_DAPM_MIXER("RIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN12_ENA_BIT,
0, &wm8990_dapm_rin12_pga_controls[0],
ARRAY_SIZE(wm8990_dapm_rin12_pga_controls)),
SND_SOC_DAPM_MIXER("RIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN34_ENA_BIT,
0, &wm8990_dapm_rin34_pga_controls[0],
ARRAY_SIZE(wm8990_dapm_rin34_pga_controls)),
/* INMIXL */
SND_SOC_DAPM_MIXER("INMIXL", SND_SOC_NOPM, 0, 0,
&wm8990_dapm_inmixl_controls[0],
ARRAY_SIZE(wm8990_dapm_inmixl_controls)),
/* AINLMUX */
SND_SOC_DAPM_MUX("AINLMUX", SND_SOC_NOPM, 0, 0, &wm8990_dapm_ainlmux_controls),
/* INMIXR */
SND_SOC_DAPM_MIXER("INMIXR", SND_SOC_NOPM, 0, 0,
&wm8990_dapm_inmixr_controls[0],
ARRAY_SIZE(wm8990_dapm_inmixr_controls)),
/* AINRMUX */
SND_SOC_DAPM_MUX("AINRMUX", SND_SOC_NOPM, 0, 0, &wm8990_dapm_ainrmux_controls),
/* Output Side */
/* DACs */
SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8990_POWER_MANAGEMENT_3,
WM8990_DACL_ENA_BIT, 0),
SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8990_POWER_MANAGEMENT_3,
WM8990_DACR_ENA_BIT, 0),
/* LOMIX */
SND_SOC_DAPM_MIXER_E("LOMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOMIX_ENA_BIT,
0, &wm8990_dapm_lomix_controls[0],
ARRAY_SIZE(wm8990_dapm_lomix_controls),
outmixer_event, SND_SOC_DAPM_PRE_REG),
/* LONMIX */
SND_SOC_DAPM_MIXER("LONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LON_ENA_BIT, 0,
&wm8990_dapm_lonmix_controls[0],
ARRAY_SIZE(wm8990_dapm_lonmix_controls)),
/* LOPMIX */
SND_SOC_DAPM_MIXER("LOPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOP_ENA_BIT, 0,
&wm8990_dapm_lopmix_controls[0],
ARRAY_SIZE(wm8990_dapm_lopmix_controls)),
/* OUT3MIX */
SND_SOC_DAPM_MIXER("OUT3MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT3_ENA_BIT, 0,
&wm8990_dapm_out3mix_controls[0],
ARRAY_SIZE(wm8990_dapm_out3mix_controls)),
/* SPKMIX */
SND_SOC_DAPM_MIXER_E("SPKMIX", WM8990_POWER_MANAGEMENT_1, WM8990_SPK_ENA_BIT, 0,
&wm8990_dapm_spkmix_controls[0],
ARRAY_SIZE(wm8990_dapm_spkmix_controls), outmixer_event,
SND_SOC_DAPM_PRE_REG),
/* OUT4MIX */
SND_SOC_DAPM_MIXER("OUT4MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT4_ENA_BIT, 0,
&wm8990_dapm_out4mix_controls[0],
ARRAY_SIZE(wm8990_dapm_out4mix_controls)),
/* ROPMIX */
SND_SOC_DAPM_MIXER("ROPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROP_ENA_BIT, 0,
&wm8990_dapm_ropmix_controls[0],
ARRAY_SIZE(wm8990_dapm_ropmix_controls)),
/* RONMIX */
SND_SOC_DAPM_MIXER("RONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_RON_ENA_BIT, 0,
&wm8990_dapm_ronmix_controls[0],
ARRAY_SIZE(wm8990_dapm_ronmix_controls)),
/* ROMIX */
SND_SOC_DAPM_MIXER_E("ROMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROMIX_ENA_BIT,
0, &wm8990_dapm_romix_controls[0],
ARRAY_SIZE(wm8990_dapm_romix_controls),
outmixer_event, SND_SOC_DAPM_PRE_REG),
/* LOUT PGA */
SND_SOC_DAPM_PGA("LOUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_LOUT_ENA_BIT, 0,
NULL, 0),
/* ROUT PGA */
SND_SOC_DAPM_PGA("ROUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_ROUT_ENA_BIT, 0,
NULL, 0),
/* LOPGA */
SND_SOC_DAPM_PGA("LOPGA", WM8990_POWER_MANAGEMENT_3, WM8990_LOPGA_ENA_BIT, 0,
NULL, 0),
/* ROPGA */
SND_SOC_DAPM_PGA("ROPGA", WM8990_POWER_MANAGEMENT_3, WM8990_ROPGA_ENA_BIT, 0,
NULL, 0),
/* MICBIAS */
SND_SOC_DAPM_SUPPLY("MICBIAS", WM8990_POWER_MANAGEMENT_1,
WM8990_MICBIAS_ENA_BIT, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("LON"),
SND_SOC_DAPM_OUTPUT("LOP"),
SND_SOC_DAPM_OUTPUT("OUT3"),
SND_SOC_DAPM_OUTPUT("LOUT"),
SND_SOC_DAPM_OUTPUT("SPKN"),
SND_SOC_DAPM_OUTPUT("SPKP"),
SND_SOC_DAPM_OUTPUT("ROUT"),
SND_SOC_DAPM_OUTPUT("OUT4"),
SND_SOC_DAPM_OUTPUT("ROP"),
SND_SOC_DAPM_OUTPUT("RON"),
SND_SOC_DAPM_OUTPUT("Internal DAC Sink"),
};
static const struct snd_soc_dapm_route wm8990_dapm_routes[] = {
/* Make DACs turn on when playing even if not mixed into any outputs */
{"Internal DAC Sink", NULL, "Left DAC"},
{"Internal DAC Sink", NULL, "Right DAC"},
/* Make ADCs turn on when recording even if not mixed from any inputs */
{"Left ADC", NULL, "Internal ADC Source"},
{"Right ADC", NULL, "Internal ADC Source"},
{"AINLMUX", NULL, "INL"},
{"INMIXL", NULL, "INL"},
{"AINRMUX", NULL, "INR"},
{"INMIXR", NULL, "INR"},
/* Input Side */
/* LIN12 PGA */
{"LIN12 PGA", "LIN1 Switch", "LIN1"},
{"LIN12 PGA", "LIN2 Switch", "LIN2"},
/* LIN34 PGA */
{"LIN34 PGA", "LIN3 Switch", "LIN3"},
{"LIN34 PGA", "LIN4 Switch", "LIN4/RXN"},
/* INMIXL */
{"INMIXL", "Record Left Volume", "LOMIX"},
{"INMIXL", "LIN2 Volume", "LIN2"},
{"INMIXL", "LINPGA12 Switch", "LIN12 PGA"},
{"INMIXL", "LINPGA34 Switch", "LIN34 PGA"},
/* AINLMUX */
{"AINLMUX", "INMIXL Mix", "INMIXL"},
{"AINLMUX", "DIFFINL Mix", "LIN12 PGA"},
{"AINLMUX", "DIFFINL Mix", "LIN34 PGA"},
{"AINLMUX", "RXVOICE Mix", "LIN4/RXN"},
{"AINLMUX", "RXVOICE Mix", "RIN4/RXP"},
/* ADC */
{"Left ADC", NULL, "AINLMUX"},
/* RIN12 PGA */
{"RIN12 PGA", "RIN1 Switch", "RIN1"},
{"RIN12 PGA", "RIN2 Switch", "RIN2"},
/* RIN34 PGA */
{"RIN34 PGA", "RIN3 Switch", "RIN3"},
{"RIN34 PGA", "RIN4 Switch", "RIN4/RXP"},
/* INMIXL */
{"INMIXR", "Record Right Volume", "ROMIX"},
{"INMIXR", "RIN2 Volume", "RIN2"},
{"INMIXR", "RINPGA12 Switch", "RIN12 PGA"},
{"INMIXR", "RINPGA34 Switch", "RIN34 PGA"},
/* AINRMUX */
{"AINRMUX", "INMIXR Mix", "INMIXR"},
{"AINRMUX", "DIFFINR Mix", "RIN12 PGA"},
{"AINRMUX", "DIFFINR Mix", "RIN34 PGA"},
{"AINRMUX", "RXVOICE Mix", "LIN4/RXN"},
{"AINRMUX", "RXVOICE Mix", "RIN4/RXP"},
/* ADC */
{"Right ADC", NULL, "AINRMUX"},
/* LOMIX */
{"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"},
{"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"},
{"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
{"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
{"LOMIX", "LOMIX Right ADC Bypass Switch", "AINRMUX"},
{"LOMIX", "LOMIX Left ADC Bypass Switch", "AINLMUX"},
{"LOMIX", "LOMIX Left DAC Switch", "Left DAC"},
/* ROMIX */
{"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"},
{"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"},
{"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
{"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
{"ROMIX", "ROMIX Right ADC Bypass Switch", "AINRMUX"},
{"ROMIX", "ROMIX Left ADC Bypass Switch", "AINLMUX"},
{"ROMIX", "ROMIX Right DAC Switch", "Right DAC"},
/* SPKMIX */
{"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"},
{"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"},
{"SPKMIX", "SPKMIX LADC Bypass Switch", "AINLMUX"},
{"SPKMIX", "SPKMIX RADC Bypass Switch", "AINRMUX"},
{"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"},
{"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"},
{"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"},
{"SPKMIX", "SPKMIX Left DAC Switch", "Left DAC"},
/* LONMIX */
{"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"},
{"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"},
{"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"},
/* LOPMIX */
{"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"},
{"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"},
{"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"},
/* OUT3MIX */
{"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXN"},
{"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"},
/* OUT4MIX */
{"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"},
{"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"},
/* RONMIX */
{"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"},
{"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"},
{"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"},
/* ROPMIX */
{"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"},
{"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"},
{"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"},
/* Out Mixer PGAs */
{"LOPGA", NULL, "LOMIX"},
{"ROPGA", NULL, "ROMIX"},
{"LOUT PGA", NULL, "LOMIX"},
{"ROUT PGA", NULL, "ROMIX"},
/* Output Pins */
{"LON", NULL, "LONMIX"},
{"LOP", NULL, "LOPMIX"},
{"OUT3", NULL, "OUT3MIX"},
{"LOUT", NULL, "LOUT PGA"},
{"SPKN", NULL, "SPKMIX"},
{"ROUT", NULL, "ROUT PGA"},
{"OUT4", NULL, "OUT4MIX"},
{"ROP", NULL, "ROPMIX"},
{"RON", NULL, "RONMIX"},
};
/* PLL divisors */
struct _pll_div {
u32 div2;
u32 n;
u32 k;
};
/* The size in bits of the pll divide multiplied by 10
* to allow rounding later */
#define FIXED_PLL_SIZE ((1 << 16) * 10)
static void pll_factors(struct _pll_div *pll_div, unsigned int target,
unsigned int source)
{
u64 Kpart;
unsigned int K, Ndiv, Nmod;
Ndiv = target / source;
if (Ndiv < 6) {
source >>= 1;
pll_div->div2 = 1;
Ndiv = target / source;
} else
pll_div->div2 = 0;
if ((Ndiv < 6) || (Ndiv > 12))
printk(KERN_WARNING
"WM8990 N value outwith recommended range! N = %u\n", Ndiv);
pll_div->n = Ndiv;
Nmod = target % source;
Kpart = FIXED_PLL_SIZE * (long long)Nmod;
do_div(Kpart, source);
K = Kpart & 0xFFFFFFFF;
/* Check if we need to round */
if ((K % 10) >= 5)
K += 5;
/* Move down to proper range now rounding is done */
K /= 10;
pll_div->k = K;
}
static int wm8990_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
int source, unsigned int freq_in, unsigned int freq_out)
{
struct snd_soc_component *component = codec_dai->component;
struct _pll_div pll_div;
if (freq_in && freq_out) {
pll_factors(&pll_div, freq_out * 4, freq_in);
/* Turn on PLL */
snd_soc_component_update_bits(component, WM8990_POWER_MANAGEMENT_2,
WM8990_PLL_ENA, WM8990_PLL_ENA);
/* sysclk comes from PLL */
snd_soc_component_update_bits(component, WM8990_CLOCKING_2,
WM8990_SYSCLK_SRC, WM8990_SYSCLK_SRC);
/* set up N , fractional mode and pre-divisor if necessary */
snd_soc_component_write(component, WM8990_PLL1, pll_div.n | WM8990_SDM |
(pll_div.div2?WM8990_PRESCALE:0));
snd_soc_component_write(component, WM8990_PLL2, (u8)(pll_div.k>>8));
snd_soc_component_write(component, WM8990_PLL3, (u8)(pll_div.k & 0xFF));
} else {
/* Turn off PLL */
snd_soc_component_update_bits(component, WM8990_POWER_MANAGEMENT_2,
WM8990_PLL_ENA, 0);
}
return 0;
}
/*
* Clock after PLL and dividers
*/
static int wm8990_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct wm8990_priv *wm8990 = snd_soc_component_get_drvdata(component);
wm8990->sysclk = freq;
return 0;
}
/*
* Set's ADC and Voice DAC format.
*/
static int wm8990_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
u16 audio1, audio3;
audio1 = snd_soc_component_read(component, WM8990_AUDIO_INTERFACE_1);
audio3 = snd_soc_component_read(component, WM8990_AUDIO_INTERFACE_3);
/* set master/slave audio interface */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
audio3 &= ~WM8990_AIF_MSTR1;
break;
case SND_SOC_DAIFMT_CBM_CFM:
audio3 |= WM8990_AIF_MSTR1;
break;
default:
return -EINVAL;
}
audio1 &= ~WM8990_AIF_FMT_MASK;
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
audio1 |= WM8990_AIF_TMF_I2S;
audio1 &= ~WM8990_AIF_LRCLK_INV;
break;
case SND_SOC_DAIFMT_RIGHT_J:
audio1 |= WM8990_AIF_TMF_RIGHTJ;
audio1 &= ~WM8990_AIF_LRCLK_INV;
break;
case SND_SOC_DAIFMT_LEFT_J:
audio1 |= WM8990_AIF_TMF_LEFTJ;
audio1 &= ~WM8990_AIF_LRCLK_INV;
break;
case SND_SOC_DAIFMT_DSP_A:
audio1 |= WM8990_AIF_TMF_DSP;
audio1 &= ~WM8990_AIF_LRCLK_INV;
break;
case SND_SOC_DAIFMT_DSP_B:
audio1 |= WM8990_AIF_TMF_DSP | WM8990_AIF_LRCLK_INV;
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, WM8990_AUDIO_INTERFACE_1, audio1);
snd_soc_component_write(component, WM8990_AUDIO_INTERFACE_3, audio3);
return 0;
}
static int wm8990_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
int div_id, int div)
{
struct snd_soc_component *component = codec_dai->component;
switch (div_id) {
case WM8990_MCLK_DIV:
snd_soc_component_update_bits(component, WM8990_CLOCKING_2,
WM8990_MCLK_DIV_MASK, div);
break;
case WM8990_DACCLK_DIV:
snd_soc_component_update_bits(component, WM8990_CLOCKING_2,
WM8990_DAC_CLKDIV_MASK, div);
break;
case WM8990_ADCCLK_DIV:
snd_soc_component_update_bits(component, WM8990_CLOCKING_2,
WM8990_ADC_CLKDIV_MASK, div);
break;
case WM8990_BCLK_DIV:
snd_soc_component_update_bits(component, WM8990_CLOCKING_1,
WM8990_BCLK_DIV_MASK, div);
break;
default:
return -EINVAL;
}
return 0;
}
/*
* Set PCM DAI bit size and sample rate.
*/
static int wm8990_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
u16 audio1 = snd_soc_component_read(component, WM8990_AUDIO_INTERFACE_1);
audio1 &= ~WM8990_AIF_WL_MASK;
/* bit size */
switch (params_width(params)) {
case 16:
break;
case 20:
audio1 |= WM8990_AIF_WL_20BITS;
break;
case 24:
audio1 |= WM8990_AIF_WL_24BITS;
break;
case 32:
audio1 |= WM8990_AIF_WL_32BITS;
break;
}
snd_soc_component_write(component, WM8990_AUDIO_INTERFACE_1, audio1);
return 0;
}
static int wm8990_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
u16 val;
val = snd_soc_component_read(component, WM8990_DAC_CTRL) & ~WM8990_DAC_MUTE;
if (mute)
snd_soc_component_write(component, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE);
else
snd_soc_component_write(component, WM8990_DAC_CTRL, val);
return 0;
}
static int wm8990_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct wm8990_priv *wm8990 = snd_soc_component_get_drvdata(component);
int ret;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
/* VMID=2*50k */
snd_soc_component_update_bits(component, WM8990_POWER_MANAGEMENT_1,
WM8990_VMID_MODE_MASK, 0x2);
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
ret = regcache_sync(wm8990->regmap);
if (ret < 0) {
dev_err(component->dev, "Failed to sync cache: %d\n", ret);
return ret;
}
/* Enable all output discharge bits */
snd_soc_component_write(component, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
WM8990_DIS_ROUT);
/* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */
snd_soc_component_write(component, WM8990_ANTIPOP2, WM8990_SOFTST |
WM8990_BUFDCOPEN | WM8990_POBCTRL |
WM8990_VMIDTOG);
/* Delay to allow output caps to discharge */
msleep(300);
/* Disable VMIDTOG */
snd_soc_component_write(component, WM8990_ANTIPOP2, WM8990_SOFTST |
WM8990_BUFDCOPEN | WM8990_POBCTRL);
/* disable all output discharge bits */
snd_soc_component_write(component, WM8990_ANTIPOP1, 0);
/* Enable outputs */
snd_soc_component_write(component, WM8990_POWER_MANAGEMENT_1, 0x1b00);
msleep(50);
/* Enable VMID at 2x50k */
snd_soc_component_write(component, WM8990_POWER_MANAGEMENT_1, 0x1f02);
msleep(100);
/* Enable VREF */
snd_soc_component_write(component, WM8990_POWER_MANAGEMENT_1, 0x1f03);
msleep(600);
/* Enable BUFIOEN */
snd_soc_component_write(component, WM8990_ANTIPOP2, WM8990_SOFTST |
WM8990_BUFDCOPEN | WM8990_POBCTRL |
WM8990_BUFIOEN);
/* Disable outputs */
snd_soc_component_write(component, WM8990_POWER_MANAGEMENT_1, 0x3);
/* disable POBCTRL, SOFT_ST and BUFDCOPEN */
snd_soc_component_write(component, WM8990_ANTIPOP2, WM8990_BUFIOEN);
/* Enable workaround for ADC clocking issue. */
snd_soc_component_write(component, WM8990_EXT_ACCESS_ENA, 0x2);
snd_soc_component_write(component, WM8990_EXT_CTL1, 0xa003);
snd_soc_component_write(component, WM8990_EXT_ACCESS_ENA, 0);
}
/* VMID=2*250k */
snd_soc_component_update_bits(component, WM8990_POWER_MANAGEMENT_1,
WM8990_VMID_MODE_MASK, 0x4);
break;
case SND_SOC_BIAS_OFF:
/* Enable POBCTRL and SOFT_ST */
snd_soc_component_write(component, WM8990_ANTIPOP2, WM8990_SOFTST |
WM8990_POBCTRL | WM8990_BUFIOEN);
/* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
snd_soc_component_write(component, WM8990_ANTIPOP2, WM8990_SOFTST |
WM8990_BUFDCOPEN | WM8990_POBCTRL |
WM8990_BUFIOEN);
/* mute DAC */
snd_soc_component_update_bits(component, WM8990_DAC_CTRL,
WM8990_DAC_MUTE, WM8990_DAC_MUTE);
/* Enable any disabled outputs */
snd_soc_component_write(component, WM8990_POWER_MANAGEMENT_1, 0x1f03);
/* Disable VMID */
snd_soc_component_write(component, WM8990_POWER_MANAGEMENT_1, 0x1f01);
msleep(300);
/* Enable all output discharge bits */
snd_soc_component_write(component, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
WM8990_DIS_ROUT);
/* Disable VREF */
snd_soc_component_write(component, WM8990_POWER_MANAGEMENT_1, 0x0);
/* disable POBCTRL, SOFT_ST and BUFDCOPEN */
snd_soc_component_write(component, WM8990_ANTIPOP2, 0x0);
regcache_mark_dirty(wm8990->regmap);
break;
}
return 0;
}
#define WM8990_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000)
#define WM8990_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
/*
* The WM8990 supports 2 different and mutually exclusive DAI
* configurations.
*
* 1. ADC/DAC on Primary Interface
* 2. ADC on Primary Interface/DAC on secondary
*/
static const struct snd_soc_dai_ops wm8990_dai_ops = {
.hw_params = wm8990_hw_params,
.mute_stream = wm8990_mute,
.set_fmt = wm8990_set_dai_fmt,
.set_clkdiv = wm8990_set_dai_clkdiv,
.set_pll = wm8990_set_dai_pll,
.set_sysclk = wm8990_set_dai_sysclk,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver wm8990_dai = {
/* ADC/DAC on primary */
.name = "wm8990-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM8990_RATES,
.formats = WM8990_FORMATS,},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM8990_RATES,
.formats = WM8990_FORMATS,},
.ops = &wm8990_dai_ops,
};
/*
* initialise the WM8990 driver
* register the mixer and dsp interfaces with the kernel
*/
static int wm8990_probe(struct snd_soc_component *component)
{
wm8990_reset(component);
/* charge output caps */
snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
snd_soc_component_update_bits(component, WM8990_AUDIO_INTERFACE_4,
WM8990_ALRCGPIO1, WM8990_ALRCGPIO1);
snd_soc_component_update_bits(component, WM8990_GPIO1_GPIO2,
WM8990_GPIO1_SEL_MASK, 1);
snd_soc_component_update_bits(component, WM8990_POWER_MANAGEMENT_2,
WM8990_OPCLK_ENA, WM8990_OPCLK_ENA);
snd_soc_component_write(component, WM8990_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8));
snd_soc_component_write(component, WM8990_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8));
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_wm8990 = {
.probe = wm8990_probe,
.set_bias_level = wm8990_set_bias_level,
.controls = wm8990_snd_controls,
.num_controls = ARRAY_SIZE(wm8990_snd_controls),
.dapm_widgets = wm8990_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8990_dapm_widgets),
.dapm_routes = wm8990_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(wm8990_dapm_routes),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int wm8990_i2c_probe(struct i2c_client *i2c)
{
struct wm8990_priv *wm8990;
int ret;
wm8990 = devm_kzalloc(&i2c->dev, sizeof(struct wm8990_priv),
GFP_KERNEL);
if (wm8990 == NULL)
return -ENOMEM;
i2c_set_clientdata(i2c, wm8990);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_wm8990, &wm8990_dai, 1);
return ret;
}
static const struct i2c_device_id wm8990_i2c_id[] = {
{ "wm8990", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8990_i2c_id);
static struct i2c_driver wm8990_i2c_driver = {
.driver = {
.name = "wm8990",
},
.probe = wm8990_i2c_probe,
.id_table = wm8990_i2c_id,
};
module_i2c_driver(wm8990_i2c_driver);
MODULE_DESCRIPTION("ASoC WM8990 driver");
MODULE_AUTHOR("Liam Girdwood");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8990.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* PCM3168A codec driver
*
* Copyright (C) 2015 Imagination Technologies Ltd.
*
* Author: Damien Horsley <[email protected]>
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/of_gpio.h>
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include "pcm3168a.h"
#define PCM3168A_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_3LE | \
SNDRV_PCM_FMTBIT_S24_LE)
#define PCM3168A_FMT_I2S 0x0
#define PCM3168A_FMT_LEFT_J 0x1
#define PCM3168A_FMT_RIGHT_J 0x2
#define PCM3168A_FMT_RIGHT_J_16 0x3
#define PCM3168A_FMT_DSP_A 0x4
#define PCM3168A_FMT_DSP_B 0x5
#define PCM3168A_FMT_I2S_TDM 0x6
#define PCM3168A_FMT_LEFT_J_TDM 0x7
static const char *const pcm3168a_supply_names[] = {
"VDD1",
"VDD2",
"VCCAD1",
"VCCAD2",
"VCCDA1",
"VCCDA2"
};
#define PCM3168A_DAI_DAC 0
#define PCM3168A_DAI_ADC 1
/* ADC/DAC side parameters */
struct pcm3168a_io_params {
bool provider_mode;
unsigned int format;
int tdm_slots;
u32 tdm_mask;
int slot_width;
};
struct pcm3168a_priv {
struct regulator_bulk_data supplies[ARRAY_SIZE(pcm3168a_supply_names)];
struct regmap *regmap;
struct clk *scki;
struct gpio_desc *gpio_rst;
unsigned long sysclk;
struct pcm3168a_io_params io_params[2];
struct snd_soc_dai_driver dai_drv[2];
};
static const char *const pcm3168a_roll_off[] = { "Sharp", "Slow" };
static SOC_ENUM_SINGLE_DECL(pcm3168a_d1_roll_off, PCM3168A_DAC_OP_FLT,
PCM3168A_DAC_FLT_SHIFT, pcm3168a_roll_off);
static SOC_ENUM_SINGLE_DECL(pcm3168a_d2_roll_off, PCM3168A_DAC_OP_FLT,
PCM3168A_DAC_FLT_SHIFT + 1, pcm3168a_roll_off);
static SOC_ENUM_SINGLE_DECL(pcm3168a_d3_roll_off, PCM3168A_DAC_OP_FLT,
PCM3168A_DAC_FLT_SHIFT + 2, pcm3168a_roll_off);
static SOC_ENUM_SINGLE_DECL(pcm3168a_d4_roll_off, PCM3168A_DAC_OP_FLT,
PCM3168A_DAC_FLT_SHIFT + 3, pcm3168a_roll_off);
static const char *const pcm3168a_volume_type[] = {
"Individual", "Master + Individual" };
static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_volume_type, PCM3168A_DAC_ATT_DEMP_ZF,
PCM3168A_DAC_ATMDDA_SHIFT, pcm3168a_volume_type);
static const char *const pcm3168a_att_speed_mult[] = { "2048", "4096" };
static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_att_mult, PCM3168A_DAC_ATT_DEMP_ZF,
PCM3168A_DAC_ATSPDA_SHIFT, pcm3168a_att_speed_mult);
static const char *const pcm3168a_demp[] = {
"Disabled", "48khz", "44.1khz", "32khz" };
static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_demp, PCM3168A_DAC_ATT_DEMP_ZF,
PCM3168A_DAC_DEMP_SHIFT, pcm3168a_demp);
static const char *const pcm3168a_zf_func[] = {
"DAC 1/2/3/4 AND", "DAC 1/2/3/4 OR", "DAC 1/2/3 AND",
"DAC 1/2/3 OR", "DAC 4 AND", "DAC 4 OR" };
static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_zf_func, PCM3168A_DAC_ATT_DEMP_ZF,
PCM3168A_DAC_AZRO_SHIFT, pcm3168a_zf_func);
static const char *const pcm3168a_pol[] = { "Active High", "Active Low" };
static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_zf_pol, PCM3168A_DAC_ATT_DEMP_ZF,
PCM3168A_DAC_ATSPDA_SHIFT, pcm3168a_pol);
static const char *const pcm3168a_con[] = { "Differential", "Single-Ended" };
static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc1_con, PCM3168A_ADC_SEAD,
0, 1, pcm3168a_con);
static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc2_con, PCM3168A_ADC_SEAD,
2, 3, pcm3168a_con);
static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc3_con, PCM3168A_ADC_SEAD,
4, 5, pcm3168a_con);
static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_volume_type, PCM3168A_ADC_ATT_OVF,
PCM3168A_ADC_ATMDAD_SHIFT, pcm3168a_volume_type);
static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_att_mult, PCM3168A_ADC_ATT_OVF,
PCM3168A_ADC_ATSPAD_SHIFT, pcm3168a_att_speed_mult);
static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_ov_pol, PCM3168A_ADC_ATT_OVF,
PCM3168A_ADC_OVFP_SHIFT, pcm3168a_pol);
/* -100db to 0db, register values 0-54 cause mute */
static const DECLARE_TLV_DB_SCALE(pcm3168a_dac_tlv, -10050, 50, 1);
/* -100db to 20db, register values 0-14 cause mute */
static const DECLARE_TLV_DB_SCALE(pcm3168a_adc_tlv, -10050, 50, 1);
static const struct snd_kcontrol_new pcm3168a_snd_controls[] = {
SOC_SINGLE("DAC Power-Save Switch", PCM3168A_DAC_PWR_MST_FMT,
PCM3168A_DAC_PSMDA_SHIFT, 1, 1),
SOC_ENUM("DAC1 Digital Filter roll-off", pcm3168a_d1_roll_off),
SOC_ENUM("DAC2 Digital Filter roll-off", pcm3168a_d2_roll_off),
SOC_ENUM("DAC3 Digital Filter roll-off", pcm3168a_d3_roll_off),
SOC_ENUM("DAC4 Digital Filter roll-off", pcm3168a_d4_roll_off),
SOC_DOUBLE("DAC1 Invert Switch", PCM3168A_DAC_INV, 0, 1, 1, 0),
SOC_DOUBLE("DAC2 Invert Switch", PCM3168A_DAC_INV, 2, 3, 1, 0),
SOC_DOUBLE("DAC3 Invert Switch", PCM3168A_DAC_INV, 4, 5, 1, 0),
SOC_DOUBLE("DAC4 Invert Switch", PCM3168A_DAC_INV, 6, 7, 1, 0),
SOC_ENUM("DAC Volume Control Type", pcm3168a_dac_volume_type),
SOC_ENUM("DAC Volume Rate Multiplier", pcm3168a_dac_att_mult),
SOC_ENUM("DAC De-Emphasis", pcm3168a_dac_demp),
SOC_ENUM("DAC Zero Flag Function", pcm3168a_dac_zf_func),
SOC_ENUM("DAC Zero Flag Polarity", pcm3168a_dac_zf_pol),
SOC_SINGLE_RANGE_TLV("Master Playback Volume",
PCM3168A_DAC_VOL_MASTER, 0, 54, 255, 0,
pcm3168a_dac_tlv),
SOC_DOUBLE_R_RANGE_TLV("DAC1 Playback Volume",
PCM3168A_DAC_VOL_CHAN_START,
PCM3168A_DAC_VOL_CHAN_START + 1,
0, 54, 255, 0, pcm3168a_dac_tlv),
SOC_DOUBLE_R_RANGE_TLV("DAC2 Playback Volume",
PCM3168A_DAC_VOL_CHAN_START + 2,
PCM3168A_DAC_VOL_CHAN_START + 3,
0, 54, 255, 0, pcm3168a_dac_tlv),
SOC_DOUBLE_R_RANGE_TLV("DAC3 Playback Volume",
PCM3168A_DAC_VOL_CHAN_START + 4,
PCM3168A_DAC_VOL_CHAN_START + 5,
0, 54, 255, 0, pcm3168a_dac_tlv),
SOC_DOUBLE_R_RANGE_TLV("DAC4 Playback Volume",
PCM3168A_DAC_VOL_CHAN_START + 6,
PCM3168A_DAC_VOL_CHAN_START + 7,
0, 54, 255, 0, pcm3168a_dac_tlv),
SOC_SINGLE("ADC1 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB,
PCM3168A_ADC_BYP_SHIFT, 1, 1),
SOC_SINGLE("ADC2 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB,
PCM3168A_ADC_BYP_SHIFT + 1, 1, 1),
SOC_SINGLE("ADC3 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB,
PCM3168A_ADC_BYP_SHIFT + 2, 1, 1),
SOC_ENUM("ADC1 Connection Type", pcm3168a_adc1_con),
SOC_ENUM("ADC2 Connection Type", pcm3168a_adc2_con),
SOC_ENUM("ADC3 Connection Type", pcm3168a_adc3_con),
SOC_DOUBLE("ADC1 Invert Switch", PCM3168A_ADC_INV, 0, 1, 1, 0),
SOC_DOUBLE("ADC2 Invert Switch", PCM3168A_ADC_INV, 2, 3, 1, 0),
SOC_DOUBLE("ADC3 Invert Switch", PCM3168A_ADC_INV, 4, 5, 1, 0),
SOC_DOUBLE("ADC1 Mute Switch", PCM3168A_ADC_MUTE, 0, 1, 1, 0),
SOC_DOUBLE("ADC2 Mute Switch", PCM3168A_ADC_MUTE, 2, 3, 1, 0),
SOC_DOUBLE("ADC3 Mute Switch", PCM3168A_ADC_MUTE, 4, 5, 1, 0),
SOC_ENUM("ADC Volume Control Type", pcm3168a_adc_volume_type),
SOC_ENUM("ADC Volume Rate Multiplier", pcm3168a_adc_att_mult),
SOC_ENUM("ADC Overflow Flag Polarity", pcm3168a_adc_ov_pol),
SOC_SINGLE_RANGE_TLV("Master Capture Volume",
PCM3168A_ADC_VOL_MASTER, 0, 14, 255, 0,
pcm3168a_adc_tlv),
SOC_DOUBLE_R_RANGE_TLV("ADC1 Capture Volume",
PCM3168A_ADC_VOL_CHAN_START,
PCM3168A_ADC_VOL_CHAN_START + 1,
0, 14, 255, 0, pcm3168a_adc_tlv),
SOC_DOUBLE_R_RANGE_TLV("ADC2 Capture Volume",
PCM3168A_ADC_VOL_CHAN_START + 2,
PCM3168A_ADC_VOL_CHAN_START + 3,
0, 14, 255, 0, pcm3168a_adc_tlv),
SOC_DOUBLE_R_RANGE_TLV("ADC3 Capture Volume",
PCM3168A_ADC_VOL_CHAN_START + 4,
PCM3168A_ADC_VOL_CHAN_START + 5,
0, 14, 255, 0, pcm3168a_adc_tlv)
};
static const struct snd_soc_dapm_widget pcm3168a_dapm_widgets[] = {
SND_SOC_DAPM_DAC("DAC1", "Playback", PCM3168A_DAC_OP_FLT,
PCM3168A_DAC_OPEDA_SHIFT, 1),
SND_SOC_DAPM_DAC("DAC2", "Playback", PCM3168A_DAC_OP_FLT,
PCM3168A_DAC_OPEDA_SHIFT + 1, 1),
SND_SOC_DAPM_DAC("DAC3", "Playback", PCM3168A_DAC_OP_FLT,
PCM3168A_DAC_OPEDA_SHIFT + 2, 1),
SND_SOC_DAPM_DAC("DAC4", "Playback", PCM3168A_DAC_OP_FLT,
PCM3168A_DAC_OPEDA_SHIFT + 3, 1),
SND_SOC_DAPM_OUTPUT("AOUT1L"),
SND_SOC_DAPM_OUTPUT("AOUT1R"),
SND_SOC_DAPM_OUTPUT("AOUT2L"),
SND_SOC_DAPM_OUTPUT("AOUT2R"),
SND_SOC_DAPM_OUTPUT("AOUT3L"),
SND_SOC_DAPM_OUTPUT("AOUT3R"),
SND_SOC_DAPM_OUTPUT("AOUT4L"),
SND_SOC_DAPM_OUTPUT("AOUT4R"),
SND_SOC_DAPM_ADC("ADC1", "Capture", PCM3168A_ADC_PWR_HPFB,
PCM3168A_ADC_PSVAD_SHIFT, 1),
SND_SOC_DAPM_ADC("ADC2", "Capture", PCM3168A_ADC_PWR_HPFB,
PCM3168A_ADC_PSVAD_SHIFT + 1, 1),
SND_SOC_DAPM_ADC("ADC3", "Capture", PCM3168A_ADC_PWR_HPFB,
PCM3168A_ADC_PSVAD_SHIFT + 2, 1),
SND_SOC_DAPM_INPUT("AIN1L"),
SND_SOC_DAPM_INPUT("AIN1R"),
SND_SOC_DAPM_INPUT("AIN2L"),
SND_SOC_DAPM_INPUT("AIN2R"),
SND_SOC_DAPM_INPUT("AIN3L"),
SND_SOC_DAPM_INPUT("AIN3R")
};
static const struct snd_soc_dapm_route pcm3168a_dapm_routes[] = {
/* Playback */
{ "AOUT1L", NULL, "DAC1" },
{ "AOUT1R", NULL, "DAC1" },
{ "AOUT2L", NULL, "DAC2" },
{ "AOUT2R", NULL, "DAC2" },
{ "AOUT3L", NULL, "DAC3" },
{ "AOUT3R", NULL, "DAC3" },
{ "AOUT4L", NULL, "DAC4" },
{ "AOUT4R", NULL, "DAC4" },
/* Capture */
{ "ADC1", NULL, "AIN1L" },
{ "ADC1", NULL, "AIN1R" },
{ "ADC2", NULL, "AIN2L" },
{ "ADC2", NULL, "AIN2R" },
{ "ADC3", NULL, "AIN3L" },
{ "ADC3", NULL, "AIN3R" }
};
static unsigned int pcm3168a_scki_ratios[] = {
768,
512,
384,
256,
192,
128
};
#define PCM3168A_NUM_SCKI_RATIOS_DAC ARRAY_SIZE(pcm3168a_scki_ratios)
#define PCM3168A_NUM_SCKI_RATIOS_ADC (ARRAY_SIZE(pcm3168a_scki_ratios) - 2)
#define PCM3168A_MAX_SYSCLK 36864000
static int pcm3168a_reset(struct pcm3168a_priv *pcm3168a)
{
int ret;
ret = regmap_write(pcm3168a->regmap, PCM3168A_RST_SMODE, 0);
if (ret)
return ret;
/* Internal reset is de-asserted after 3846 SCKI cycles */
msleep(DIV_ROUND_UP(3846 * 1000, pcm3168a->sysclk));
return regmap_write(pcm3168a->regmap, PCM3168A_RST_SMODE,
PCM3168A_MRST_MASK | PCM3168A_SRST_MASK);
}
static int pcm3168a_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component);
regmap_write(pcm3168a->regmap, PCM3168A_DAC_MUTE, mute ? 0xff : 0);
return 0;
}
static int pcm3168a_set_dai_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(dai->component);
int ret;
/*
* Some sound card sets 0 Hz as reset,
* but it is impossible to set. Ignore it here
*/
if (freq == 0)
return 0;
if (freq > PCM3168A_MAX_SYSCLK)
return -EINVAL;
ret = clk_set_rate(pcm3168a->scki, freq);
if (ret)
return ret;
pcm3168a->sysclk = freq;
return 0;
}
static void pcm3168a_update_fixup_pcm_stream(struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component);
struct pcm3168a_io_params *io_params = &pcm3168a->io_params[dai->id];
u64 formats = SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE;
unsigned int channel_max = dai->id == PCM3168A_DAI_DAC ? 8 : 6;
if (io_params->format == SND_SOC_DAIFMT_RIGHT_J) {
/* S16_LE is only supported in RIGHT_J mode */
formats |= SNDRV_PCM_FMTBIT_S16_LE;
/*
* If multi DIN/DOUT is not selected, RIGHT_J can only support
* two channels (no TDM support)
*/
if (io_params->tdm_slots != 2)
channel_max = 2;
}
if (dai->id == PCM3168A_DAI_DAC) {
dai->driver->playback.channels_max = channel_max;
dai->driver->playback.formats = formats;
} else {
dai->driver->capture.channels_max = channel_max;
dai->driver->capture.formats = formats;
}
}
static int pcm3168a_set_dai_fmt(struct snd_soc_dai *dai, unsigned int format)
{
struct snd_soc_component *component = dai->component;
struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component);
struct pcm3168a_io_params *io_params = &pcm3168a->io_params[dai->id];
bool provider_mode;
switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_LEFT_J:
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_RIGHT_J:
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B:
break;
default:
dev_err(component->dev, "unsupported dai format\n");
return -EINVAL;
}
switch (format & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC:
provider_mode = false;
break;
case SND_SOC_DAIFMT_CBP_CFP:
provider_mode = true;
break;
default:
dev_err(component->dev, "unsupported provider mode\n");
return -EINVAL;
}
switch (format & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
default:
return -EINVAL;
}
io_params->provider_mode = provider_mode;
io_params->format = format & SND_SOC_DAIFMT_FORMAT_MASK;
pcm3168a_update_fixup_pcm_stream(dai);
return 0;
}
static int pcm3168a_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots,
int slot_width)
{
struct snd_soc_component *component = dai->component;
struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component);
struct pcm3168a_io_params *io_params = &pcm3168a->io_params[dai->id];
if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) {
dev_err(component->dev,
"Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n",
tx_mask, rx_mask, slots);
return -EINVAL;
}
if (slot_width &&
(slot_width != 16 && slot_width != 24 && slot_width != 32 )) {
dev_err(component->dev, "Unsupported slot_width %d\n",
slot_width);
return -EINVAL;
}
io_params->tdm_slots = slots;
io_params->slot_width = slot_width;
/* Ignore the not relevant mask for the DAI/direction */
if (dai->id == PCM3168A_DAI_DAC)
io_params->tdm_mask = tx_mask;
else
io_params->tdm_mask = rx_mask;
pcm3168a_update_fixup_pcm_stream(dai);
return 0;
}
static int pcm3168a_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component);
struct pcm3168a_io_params *io_params = &pcm3168a->io_params[dai->id];
bool provider_mode, tdm_mode;
unsigned int format;
unsigned int reg, mask, ms, ms_shift, fmt, fmt_shift, ratio, tdm_slots;
int i, num_scki_ratios, slot_width;
if (dai->id == PCM3168A_DAI_DAC) {
num_scki_ratios = PCM3168A_NUM_SCKI_RATIOS_DAC;
reg = PCM3168A_DAC_PWR_MST_FMT;
mask = PCM3168A_DAC_MSDA_MASK | PCM3168A_DAC_FMT_MASK;
ms_shift = PCM3168A_DAC_MSDA_SHIFT;
fmt_shift = PCM3168A_DAC_FMT_SHIFT;
} else {
num_scki_ratios = PCM3168A_NUM_SCKI_RATIOS_ADC;
reg = PCM3168A_ADC_MST_FMT;
mask = PCM3168A_ADC_MSAD_MASK | PCM3168A_ADC_FMTAD_MASK;
ms_shift = PCM3168A_ADC_MSAD_SHIFT;
fmt_shift = PCM3168A_ADC_FMTAD_SHIFT;
}
provider_mode = io_params->provider_mode;
if (provider_mode) {
ratio = pcm3168a->sysclk / params_rate(params);
for (i = 0; i < num_scki_ratios; i++) {
if (pcm3168a_scki_ratios[i] == ratio)
break;
}
if (i == num_scki_ratios) {
dev_err(component->dev, "unsupported sysclk ratio\n");
return -EINVAL;
}
ms = (i + 1);
} else {
ms = 0;
}
format = io_params->format;
if (io_params->slot_width)
slot_width = io_params->slot_width;
else
slot_width = params_width(params);
switch (slot_width) {
case 16:
if (provider_mode || (format != SND_SOC_DAIFMT_RIGHT_J)) {
dev_err(component->dev, "16-bit slots are supported only for consumer mode using right justified\n");
return -EINVAL;
}
break;
case 24:
if (provider_mode || (format == SND_SOC_DAIFMT_DSP_A) ||
(format == SND_SOC_DAIFMT_DSP_B)) {
dev_err(component->dev, "24-bit slots not supported in provider mode, or consumer mode using DSP\n");
return -EINVAL;
}
break;
case 32:
break;
default:
dev_err(component->dev, "unsupported frame size: %d\n", slot_width);
return -EINVAL;
}
if (io_params->tdm_slots)
tdm_slots = io_params->tdm_slots;
else
tdm_slots = params_channels(params);
/*
* Switch the codec to TDM mode when more than 2 TDM slots are needed
* for the stream.
* If pcm3168a->tdm_slots is not set or set to more than 2 (8/6 usually)
* then DIN1/DOUT1 is used in TDM mode.
* If pcm3168a->tdm_slots is set to 2 then DIN1/2/3/4 and DOUT1/2/3 is
* used in normal mode, no need to switch to TDM modes.
*/
tdm_mode = (tdm_slots > 2);
if (tdm_mode) {
switch (format) {
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_LEFT_J:
case SND_SOC_DAIFMT_DSP_B:
break;
default:
dev_err(component->dev,
"TDM is supported under DSP/I2S/Left_J only\n");
return -EINVAL;
}
}
switch (format) {
case SND_SOC_DAIFMT_I2S:
fmt = tdm_mode ? PCM3168A_FMT_I2S_TDM : PCM3168A_FMT_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
fmt = tdm_mode ? PCM3168A_FMT_LEFT_J_TDM : PCM3168A_FMT_LEFT_J;
break;
case SND_SOC_DAIFMT_RIGHT_J:
fmt = (slot_width == 16) ? PCM3168A_FMT_RIGHT_J_16 :
PCM3168A_FMT_RIGHT_J;
break;
case SND_SOC_DAIFMT_DSP_A:
fmt = tdm_mode ? PCM3168A_FMT_I2S_TDM : PCM3168A_FMT_DSP_A;
break;
case SND_SOC_DAIFMT_DSP_B:
fmt = tdm_mode ? PCM3168A_FMT_LEFT_J_TDM : PCM3168A_FMT_DSP_B;
break;
default:
return -EINVAL;
}
regmap_update_bits(pcm3168a->regmap, reg, mask,
(ms << ms_shift) | (fmt << fmt_shift));
return 0;
}
static u64 pcm3168a_dai_formats[] = {
/*
* Select below from Sound Card, not here
* SND_SOC_DAIFMT_CBC_CFC
* SND_SOC_DAIFMT_CBP_CFP
*/
/*
* First Priority
*/
SND_SOC_POSSIBLE_DAIFMT_I2S |
SND_SOC_POSSIBLE_DAIFMT_LEFT_J,
/*
* Second Priority
*
* These have picky limitation.
* see
* pcm3168a_hw_params()
*/
SND_SOC_POSSIBLE_DAIFMT_RIGHT_J |
SND_SOC_POSSIBLE_DAIFMT_DSP_A |
SND_SOC_POSSIBLE_DAIFMT_DSP_B,
};
static const struct snd_soc_dai_ops pcm3168a_dai_ops = {
.set_fmt = pcm3168a_set_dai_fmt,
.set_sysclk = pcm3168a_set_dai_sysclk,
.hw_params = pcm3168a_hw_params,
.mute_stream = pcm3168a_mute,
.set_tdm_slot = pcm3168a_set_tdm_slot,
.no_capture_mute = 1,
.auto_selectable_formats = pcm3168a_dai_formats,
.num_auto_selectable_formats = ARRAY_SIZE(pcm3168a_dai_formats),
};
static struct snd_soc_dai_driver pcm3168a_dais[] = {
{
.name = "pcm3168a-dac",
.id = PCM3168A_DAI_DAC,
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = PCM3168A_FORMATS
},
.ops = &pcm3168a_dai_ops
},
{
.name = "pcm3168a-adc",
.id = PCM3168A_DAI_ADC,
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 6,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = PCM3168A_FORMATS
},
.ops = &pcm3168a_dai_ops
},
};
static const struct reg_default pcm3168a_reg_default[] = {
{ PCM3168A_RST_SMODE, PCM3168A_MRST_MASK | PCM3168A_SRST_MASK },
{ PCM3168A_DAC_PWR_MST_FMT, 0x00 },
{ PCM3168A_DAC_OP_FLT, 0x00 },
{ PCM3168A_DAC_INV, 0x00 },
{ PCM3168A_DAC_MUTE, 0x00 },
{ PCM3168A_DAC_ZERO, 0x00 },
{ PCM3168A_DAC_ATT_DEMP_ZF, 0x00 },
{ PCM3168A_DAC_VOL_MASTER, 0xff },
{ PCM3168A_DAC_VOL_CHAN_START, 0xff },
{ PCM3168A_DAC_VOL_CHAN_START + 1, 0xff },
{ PCM3168A_DAC_VOL_CHAN_START + 2, 0xff },
{ PCM3168A_DAC_VOL_CHAN_START + 3, 0xff },
{ PCM3168A_DAC_VOL_CHAN_START + 4, 0xff },
{ PCM3168A_DAC_VOL_CHAN_START + 5, 0xff },
{ PCM3168A_DAC_VOL_CHAN_START + 6, 0xff },
{ PCM3168A_DAC_VOL_CHAN_START + 7, 0xff },
{ PCM3168A_ADC_SMODE, 0x00 },
{ PCM3168A_ADC_MST_FMT, 0x00 },
{ PCM3168A_ADC_PWR_HPFB, 0x00 },
{ PCM3168A_ADC_SEAD, 0x00 },
{ PCM3168A_ADC_INV, 0x00 },
{ PCM3168A_ADC_MUTE, 0x00 },
{ PCM3168A_ADC_OV, 0x00 },
{ PCM3168A_ADC_ATT_OVF, 0x00 },
{ PCM3168A_ADC_VOL_MASTER, 0xd3 },
{ PCM3168A_ADC_VOL_CHAN_START, 0xd3 },
{ PCM3168A_ADC_VOL_CHAN_START + 1, 0xd3 },
{ PCM3168A_ADC_VOL_CHAN_START + 2, 0xd3 },
{ PCM3168A_ADC_VOL_CHAN_START + 3, 0xd3 },
{ PCM3168A_ADC_VOL_CHAN_START + 4, 0xd3 },
{ PCM3168A_ADC_VOL_CHAN_START + 5, 0xd3 }
};
static bool pcm3168a_readable_register(struct device *dev, unsigned int reg)
{
if (reg >= PCM3168A_RST_SMODE)
return true;
else
return false;
}
static bool pcm3168a_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case PCM3168A_RST_SMODE:
case PCM3168A_DAC_ZERO:
case PCM3168A_ADC_OV:
return true;
default:
return false;
}
}
static bool pcm3168a_writeable_register(struct device *dev, unsigned int reg)
{
if (reg < PCM3168A_RST_SMODE)
return false;
switch (reg) {
case PCM3168A_DAC_ZERO:
case PCM3168A_ADC_OV:
return false;
default:
return true;
}
}
const struct regmap_config pcm3168a_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = PCM3168A_ADC_VOL_CHAN_START + 5,
.reg_defaults = pcm3168a_reg_default,
.num_reg_defaults = ARRAY_SIZE(pcm3168a_reg_default),
.readable_reg = pcm3168a_readable_register,
.volatile_reg = pcm3168a_volatile_register,
.writeable_reg = pcm3168a_writeable_register,
.cache_type = REGCACHE_FLAT
};
EXPORT_SYMBOL_GPL(pcm3168a_regmap);
static const struct snd_soc_component_driver pcm3168a_driver = {
.controls = pcm3168a_snd_controls,
.num_controls = ARRAY_SIZE(pcm3168a_snd_controls),
.dapm_widgets = pcm3168a_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(pcm3168a_dapm_widgets),
.dapm_routes = pcm3168a_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(pcm3168a_dapm_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
int pcm3168a_probe(struct device *dev, struct regmap *regmap)
{
struct pcm3168a_priv *pcm3168a;
int ret, i;
pcm3168a = devm_kzalloc(dev, sizeof(*pcm3168a), GFP_KERNEL);
if (pcm3168a == NULL)
return -ENOMEM;
dev_set_drvdata(dev, pcm3168a);
/*
* Request the reset (connected to RST pin) gpio line as non exclusive
* as the same reset line might be connected to multiple pcm3168a codec
*
* The RST is low active, we want the GPIO line to be high initially, so
* request the initial level to LOW which in practice means DEASSERTED:
* The deasserted level of GPIO_ACTIVE_LOW is HIGH.
*/
pcm3168a->gpio_rst = devm_gpiod_get_optional(dev, "reset",
GPIOD_OUT_LOW |
GPIOD_FLAGS_BIT_NONEXCLUSIVE);
if (IS_ERR(pcm3168a->gpio_rst))
return dev_err_probe(dev, PTR_ERR(pcm3168a->gpio_rst),
"failed to acquire RST gpio\n");
pcm3168a->scki = devm_clk_get(dev, "scki");
if (IS_ERR(pcm3168a->scki))
return dev_err_probe(dev, PTR_ERR(pcm3168a->scki),
"failed to acquire clock 'scki'\n");
ret = clk_prepare_enable(pcm3168a->scki);
if (ret) {
dev_err(dev, "Failed to enable mclk: %d\n", ret);
return ret;
}
pcm3168a->sysclk = clk_get_rate(pcm3168a->scki);
for (i = 0; i < ARRAY_SIZE(pcm3168a->supplies); i++)
pcm3168a->supplies[i].supply = pcm3168a_supply_names[i];
ret = devm_regulator_bulk_get(dev,
ARRAY_SIZE(pcm3168a->supplies), pcm3168a->supplies);
if (ret) {
dev_err_probe(dev, ret, "failed to request supplies\n");
goto err_clk;
}
ret = regulator_bulk_enable(ARRAY_SIZE(pcm3168a->supplies),
pcm3168a->supplies);
if (ret) {
dev_err(dev, "failed to enable supplies: %d\n", ret);
goto err_clk;
}
pcm3168a->regmap = regmap;
if (IS_ERR(pcm3168a->regmap)) {
ret = PTR_ERR(pcm3168a->regmap);
dev_err(dev, "failed to allocate regmap: %d\n", ret);
goto err_regulator;
}
if (pcm3168a->gpio_rst) {
/*
* The device is taken out from reset via GPIO line, wait for
* 3846 SCKI clock cycles for the internal reset de-assertion
*/
msleep(DIV_ROUND_UP(3846 * 1000, pcm3168a->sysclk));
} else {
ret = pcm3168a_reset(pcm3168a);
if (ret) {
dev_err(dev, "Failed to reset device: %d\n", ret);
goto err_regulator;
}
}
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
pm_runtime_idle(dev);
memcpy(pcm3168a->dai_drv, pcm3168a_dais, sizeof(pcm3168a->dai_drv));
ret = devm_snd_soc_register_component(dev, &pcm3168a_driver,
pcm3168a->dai_drv,
ARRAY_SIZE(pcm3168a->dai_drv));
if (ret) {
dev_err(dev, "failed to register component: %d\n", ret);
goto err_regulator;
}
return 0;
err_regulator:
regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies),
pcm3168a->supplies);
err_clk:
clk_disable_unprepare(pcm3168a->scki);
return ret;
}
EXPORT_SYMBOL_GPL(pcm3168a_probe);
static void pcm3168a_disable(struct device *dev)
{
struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev);
regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies),
pcm3168a->supplies);
clk_disable_unprepare(pcm3168a->scki);
}
void pcm3168a_remove(struct device *dev)
{
struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev);
/*
* The RST is low active, we want the GPIO line to be low when the
* driver is removed, so set level to 1 which in practice means
* ASSERTED:
* The asserted level of GPIO_ACTIVE_LOW is LOW.
*/
gpiod_set_value_cansleep(pcm3168a->gpio_rst, 1);
pm_runtime_disable(dev);
#ifndef CONFIG_PM
pcm3168a_disable(dev);
#endif
}
EXPORT_SYMBOL_GPL(pcm3168a_remove);
#ifdef CONFIG_PM
static int pcm3168a_rt_resume(struct device *dev)
{
struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev);
int ret;
ret = clk_prepare_enable(pcm3168a->scki);
if (ret) {
dev_err(dev, "Failed to enable mclk: %d\n", ret);
return ret;
}
ret = regulator_bulk_enable(ARRAY_SIZE(pcm3168a->supplies),
pcm3168a->supplies);
if (ret) {
dev_err(dev, "Failed to enable supplies: %d\n", ret);
goto err_clk;
}
ret = pcm3168a_reset(pcm3168a);
if (ret) {
dev_err(dev, "Failed to reset device: %d\n", ret);
goto err_regulator;
}
regcache_cache_only(pcm3168a->regmap, false);
regcache_mark_dirty(pcm3168a->regmap);
ret = regcache_sync(pcm3168a->regmap);
if (ret) {
dev_err(dev, "Failed to sync regmap: %d\n", ret);
goto err_regulator;
}
return 0;
err_regulator:
regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies),
pcm3168a->supplies);
err_clk:
clk_disable_unprepare(pcm3168a->scki);
return ret;
}
static int pcm3168a_rt_suspend(struct device *dev)
{
struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev);
regcache_cache_only(pcm3168a->regmap, true);
pcm3168a_disable(dev);
return 0;
}
#endif
const struct dev_pm_ops pcm3168a_pm_ops = {
SET_RUNTIME_PM_OPS(pcm3168a_rt_suspend, pcm3168a_rt_resume, NULL)
};
EXPORT_SYMBOL_GPL(pcm3168a_pm_ops);
MODULE_DESCRIPTION("PCM3168A codec driver");
MODULE_AUTHOR("Damien Horsley <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/pcm3168a.c |
// SPDX-License-Identifier: GPL-2.0
// Audio driver for PCM1789
// Copyright (C) 2018 Bootlin
// Mylène Josserand <[email protected]>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/workqueue.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include "pcm1789.h"
#define PCM1789_MUTE_CONTROL 0x10
#define PCM1789_FMT_CONTROL 0x11
#define PCM1789_SOFT_MUTE 0x14
#define PCM1789_DAC_VOL_LEFT 0x18
#define PCM1789_DAC_VOL_RIGHT 0x19
#define PCM1789_FMT_MASK 0x07
#define PCM1789_MUTE_MASK 0x03
#define PCM1789_MUTE_SRET 0x06
struct pcm1789_private {
struct regmap *regmap;
unsigned int format;
unsigned int rate;
struct gpio_desc *reset;
struct work_struct work;
struct device *dev;
};
static const struct reg_default pcm1789_reg_defaults[] = {
{ PCM1789_FMT_CONTROL, 0x00 },
{ PCM1789_SOFT_MUTE, 0x00 },
{ PCM1789_DAC_VOL_LEFT, 0xff },
{ PCM1789_DAC_VOL_RIGHT, 0xff },
};
static bool pcm1789_accessible_reg(struct device *dev, unsigned int reg)
{
return reg >= PCM1789_MUTE_CONTROL && reg <= PCM1789_DAC_VOL_RIGHT;
}
static bool pcm1789_writeable_reg(struct device *dev, unsigned int reg)
{
return pcm1789_accessible_reg(dev, reg);
}
static int pcm1789_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int format)
{
struct snd_soc_component *component = codec_dai->component;
struct pcm1789_private *priv = snd_soc_component_get_drvdata(component);
priv->format = format;
return 0;
}
static int pcm1789_mute(struct snd_soc_dai *codec_dai, int mute, int direction)
{
struct snd_soc_component *component = codec_dai->component;
struct pcm1789_private *priv = snd_soc_component_get_drvdata(component);
return regmap_update_bits(priv->regmap, PCM1789_SOFT_MUTE,
PCM1789_MUTE_MASK,
mute ? 0 : PCM1789_MUTE_MASK);
}
static int pcm1789_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *codec_dai)
{
struct snd_soc_component *component = codec_dai->component;
struct pcm1789_private *priv = snd_soc_component_get_drvdata(component);
int val = 0, ret;
priv->rate = params_rate(params);
switch (priv->format & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_RIGHT_J:
switch (params_width(params)) {
case 24:
val = 2;
break;
case 16:
val = 3;
break;
default:
return -EINVAL;
}
break;
case SND_SOC_DAIFMT_I2S:
switch (params_width(params)) {
case 16:
case 24:
case 32:
val = 0;
break;
default:
return -EINVAL;
}
break;
case SND_SOC_DAIFMT_LEFT_J:
switch (params_width(params)) {
case 16:
case 24:
case 32:
val = 1;
break;
default:
return -EINVAL;
}
break;
default:
dev_err(component->dev, "Invalid DAI format\n");
return -EINVAL;
}
ret = regmap_update_bits(priv->regmap, PCM1789_FMT_CONTROL,
PCM1789_FMT_MASK, val);
if (ret < 0)
return ret;
return 0;
}
static void pcm1789_work_queue(struct work_struct *work)
{
struct pcm1789_private *priv = container_of(work,
struct pcm1789_private,
work);
/* Perform a software reset to remove codec from desynchronized state */
if (regmap_update_bits(priv->regmap, PCM1789_MUTE_CONTROL,
0x3 << PCM1789_MUTE_SRET, 0) < 0)
dev_err(priv->dev, "Error while setting SRET");
}
static int pcm1789_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct pcm1789_private *priv = snd_soc_component_get_drvdata(component);
int ret = 0;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
schedule_work(&priv->work);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
break;
default:
ret = -EINVAL;
}
return ret;
}
static const struct snd_soc_dai_ops pcm1789_dai_ops = {
.set_fmt = pcm1789_set_dai_fmt,
.hw_params = pcm1789_hw_params,
.mute_stream = pcm1789_mute,
.trigger = pcm1789_trigger,
.no_capture_mute = 1,
};
static const DECLARE_TLV_DB_SCALE(pcm1789_dac_tlv, -12000, 50, 1);
static const struct snd_kcontrol_new pcm1789_controls[] = {
SOC_DOUBLE_R_RANGE_TLV("DAC Playback Volume", PCM1789_DAC_VOL_LEFT,
PCM1789_DAC_VOL_RIGHT, 0, 0xf, 0xff, 0,
pcm1789_dac_tlv),
};
static const struct snd_soc_dapm_widget pcm1789_dapm_widgets[] = {
SND_SOC_DAPM_OUTPUT("IOUTL+"),
SND_SOC_DAPM_OUTPUT("IOUTL-"),
SND_SOC_DAPM_OUTPUT("IOUTR+"),
SND_SOC_DAPM_OUTPUT("IOUTR-"),
};
static const struct snd_soc_dapm_route pcm1789_dapm_routes[] = {
{ "IOUTL+", NULL, "Playback" },
{ "IOUTL-", NULL, "Playback" },
{ "IOUTR+", NULL, "Playback" },
{ "IOUTR-", NULL, "Playback" },
};
static struct snd_soc_dai_driver pcm1789_dai = {
.name = "pcm1789-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.rate_min = 10000,
.rate_max = 200000,
.formats = PCM1789_FORMATS,
},
.ops = &pcm1789_dai_ops,
};
const struct regmap_config pcm1789_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = PCM1789_DAC_VOL_RIGHT,
.reg_defaults = pcm1789_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(pcm1789_reg_defaults),
.writeable_reg = pcm1789_writeable_reg,
.readable_reg = pcm1789_accessible_reg,
};
EXPORT_SYMBOL_GPL(pcm1789_regmap_config);
static const struct snd_soc_component_driver soc_component_dev_pcm1789 = {
.controls = pcm1789_controls,
.num_controls = ARRAY_SIZE(pcm1789_controls),
.dapm_widgets = pcm1789_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(pcm1789_dapm_widgets),
.dapm_routes = pcm1789_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(pcm1789_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
int pcm1789_common_init(struct device *dev, struct regmap *regmap)
{
struct pcm1789_private *pcm1789;
pcm1789 = devm_kzalloc(dev, sizeof(struct pcm1789_private),
GFP_KERNEL);
if (!pcm1789)
return -ENOMEM;
pcm1789->regmap = regmap;
pcm1789->dev = dev;
dev_set_drvdata(dev, pcm1789);
pcm1789->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
if (IS_ERR(pcm1789->reset))
return PTR_ERR(pcm1789->reset);
gpiod_set_value_cansleep(pcm1789->reset, 0);
msleep(300);
INIT_WORK(&pcm1789->work, pcm1789_work_queue);
return devm_snd_soc_register_component(dev, &soc_component_dev_pcm1789,
&pcm1789_dai, 1);
}
EXPORT_SYMBOL_GPL(pcm1789_common_init);
void pcm1789_common_exit(struct device *dev)
{
struct pcm1789_private *priv = dev_get_drvdata(dev);
flush_work(&priv->work);
}
EXPORT_SYMBOL_GPL(pcm1789_common_exit);
MODULE_DESCRIPTION("ASoC PCM1789 driver");
MODULE_AUTHOR("Mylène Josserand <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/pcm1789.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* AD1936/AD1937 audio driver
*
* Copyright 2014 Analog Devices Inc.
*/
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include "ad193x.h"
static const struct i2c_device_id ad193x_id[] = {
{ "ad1936", AD193X },
{ "ad1937", AD193X },
{ }
};
MODULE_DEVICE_TABLE(i2c, ad193x_id);
static int ad193x_i2c_probe(struct i2c_client *client)
{
struct regmap_config config;
const struct i2c_device_id *id = i2c_match_id(ad193x_id, client);
config = ad193x_regmap_config;
config.val_bits = 8;
config.reg_bits = 8;
return ad193x_probe(&client->dev,
devm_regmap_init_i2c(client, &config),
(enum ad193x_type)id->driver_data);
}
static struct i2c_driver ad193x_i2c_driver = {
.driver = {
.name = "ad193x",
},
.probe = ad193x_i2c_probe,
.id_table = ad193x_id,
};
module_i2c_driver(ad193x_i2c_driver);
MODULE_DESCRIPTION("ASoC AD1936/AD1937 audio CODEC driver");
MODULE_AUTHOR("Barry Song <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/ad193x-i2c.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* cs42l42-i2c.c -- CS42L42 ALSA SoC audio driver for I2C
*
* Copyright 2016, 2022 Cirrus Logic, Inc.
*/
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/types.h>
#include "cs42l42.h"
static int cs42l42_i2c_probe(struct i2c_client *i2c_client)
{
struct device *dev = &i2c_client->dev;
struct cs42l42_private *cs42l42;
struct regmap *regmap;
int ret;
cs42l42 = devm_kzalloc(dev, sizeof(*cs42l42), GFP_KERNEL);
if (!cs42l42)
return -ENOMEM;
regmap = devm_regmap_init_i2c(i2c_client, &cs42l42_regmap);
if (IS_ERR(regmap))
return dev_err_probe(&i2c_client->dev, PTR_ERR(regmap),
"regmap_init() failed\n");
cs42l42->devid = CS42L42_CHIP_ID;
cs42l42->dev = dev;
cs42l42->regmap = regmap;
cs42l42->irq = i2c_client->irq;
ret = cs42l42_common_probe(cs42l42, &cs42l42_soc_component, &cs42l42_dai);
if (ret)
return ret;
return cs42l42_init(cs42l42);
}
static void cs42l42_i2c_remove(struct i2c_client *i2c_client)
{
struct cs42l42_private *cs42l42 = dev_get_drvdata(&i2c_client->dev);
cs42l42_common_remove(cs42l42);
}
static int __maybe_unused cs42l42_i2c_resume(struct device *dev)
{
int ret;
ret = cs42l42_resume(dev);
if (ret)
return ret;
cs42l42_resume_restore(dev);
return 0;
}
static const struct dev_pm_ops cs42l42_i2c_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(cs42l42_suspend, cs42l42_i2c_resume)
};
static const struct of_device_id __maybe_unused cs42l42_of_match[] = {
{ .compatible = "cirrus,cs42l42", },
{}
};
MODULE_DEVICE_TABLE(of, cs42l42_of_match);
static const struct acpi_device_id __maybe_unused cs42l42_acpi_match[] = {
{"10134242", 0,},
{}
};
MODULE_DEVICE_TABLE(acpi, cs42l42_acpi_match);
static const struct i2c_device_id cs42l42_id[] = {
{"cs42l42", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, cs42l42_id);
static struct i2c_driver cs42l42_i2c_driver = {
.driver = {
.name = "cs42l42",
.pm = &cs42l42_i2c_pm_ops,
.of_match_table = of_match_ptr(cs42l42_of_match),
.acpi_match_table = ACPI_PTR(cs42l42_acpi_match),
},
.id_table = cs42l42_id,
.probe = cs42l42_i2c_probe,
.remove = cs42l42_i2c_remove,
};
module_i2c_driver(cs42l42_i2c_driver);
MODULE_DESCRIPTION("ASoC CS42L42 I2C driver");
MODULE_AUTHOR("Richard Fitzgerald <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_IMPORT_NS(SND_SOC_CS42L42_CORE);
| linux-master | sound/soc/codecs/cs42l42-i2c.c |
/* SPDX-License-Identifier: GPL-2.0
*
* Clock Tree for the Texas Instruments TLV320AIC32x4
*
* Copyright 2019 Annaliese McDermond
*
* Author: Annaliese McDermond <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/regmap.h>
#include <linux/device.h>
#include "tlv320aic32x4.h"
#define to_clk_aic32x4(_hw) container_of(_hw, struct clk_aic32x4, hw)
struct clk_aic32x4 {
struct clk_hw hw;
struct device *dev;
struct regmap *regmap;
unsigned int reg;
};
/*
* struct clk_aic32x4_pll_muldiv - Multiplier/divider settings
* @p: Divider
* @r: first multiplier
* @j: integer part of second multiplier
* @d: decimal part of second multiplier
*/
struct clk_aic32x4_pll_muldiv {
u8 p;
u16 r;
u8 j;
u16 d;
};
struct aic32x4_clkdesc {
const char *name;
const char * const *parent_names;
unsigned int num_parents;
const struct clk_ops *ops;
unsigned int reg;
};
static int clk_aic32x4_pll_prepare(struct clk_hw *hw)
{
struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
return regmap_update_bits(pll->regmap, AIC32X4_PLLPR,
AIC32X4_PLLEN, AIC32X4_PLLEN);
}
static void clk_aic32x4_pll_unprepare(struct clk_hw *hw)
{
struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
regmap_update_bits(pll->regmap, AIC32X4_PLLPR,
AIC32X4_PLLEN, 0);
}
static int clk_aic32x4_pll_is_prepared(struct clk_hw *hw)
{
struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
unsigned int val;
int ret;
ret = regmap_read(pll->regmap, AIC32X4_PLLPR, &val);
if (ret < 0)
return ret;
return !!(val & AIC32X4_PLLEN);
}
static int clk_aic32x4_pll_get_muldiv(struct clk_aic32x4 *pll,
struct clk_aic32x4_pll_muldiv *settings)
{
/* Change to use regmap_bulk_read? */
unsigned int val;
int ret;
ret = regmap_read(pll->regmap, AIC32X4_PLLPR, &val);
if (ret < 0)
return ret;
settings->r = val & AIC32X4_PLL_R_MASK;
settings->p = (val & AIC32X4_PLL_P_MASK) >> AIC32X4_PLL_P_SHIFT;
ret = regmap_read(pll->regmap, AIC32X4_PLLJ, &val);
if (ret < 0)
return ret;
settings->j = val;
ret = regmap_read(pll->regmap, AIC32X4_PLLDMSB, &val);
if (ret < 0)
return ret;
settings->d = val << 8;
ret = regmap_read(pll->regmap, AIC32X4_PLLDLSB, &val);
if (ret < 0)
return ret;
settings->d |= val;
return 0;
}
static int clk_aic32x4_pll_set_muldiv(struct clk_aic32x4 *pll,
struct clk_aic32x4_pll_muldiv *settings)
{
int ret;
/* Change to use regmap_bulk_write for some if not all? */
ret = regmap_update_bits(pll->regmap, AIC32X4_PLLPR,
AIC32X4_PLL_R_MASK, settings->r);
if (ret < 0)
return ret;
ret = regmap_update_bits(pll->regmap, AIC32X4_PLLPR,
AIC32X4_PLL_P_MASK,
settings->p << AIC32X4_PLL_P_SHIFT);
if (ret < 0)
return ret;
ret = regmap_write(pll->regmap, AIC32X4_PLLJ, settings->j);
if (ret < 0)
return ret;
ret = regmap_write(pll->regmap, AIC32X4_PLLDMSB, (settings->d >> 8));
if (ret < 0)
return ret;
ret = regmap_write(pll->regmap, AIC32X4_PLLDLSB, (settings->d & 0xff));
if (ret < 0)
return ret;
return 0;
}
static unsigned long clk_aic32x4_pll_calc_rate(
struct clk_aic32x4_pll_muldiv *settings,
unsigned long parent_rate)
{
u64 rate;
/*
* We scale j by 10000 to account for the decimal part of P and divide
* it back out later.
*/
rate = (u64) parent_rate * settings->r *
((settings->j * 10000) + settings->d);
return (unsigned long) DIV_ROUND_UP_ULL(rate, settings->p * 10000);
}
static int clk_aic32x4_pll_calc_muldiv(struct clk_aic32x4_pll_muldiv *settings,
unsigned long rate, unsigned long parent_rate)
{
u64 multiplier;
settings->p = parent_rate / AIC32X4_MAX_PLL_CLKIN + 1;
if (settings->p > 8)
return -1;
/*
* We scale this figure by 10000 so that we can get the decimal part
* of the multiplier. This is because we can't do floating point
* math in the kernel.
*/
multiplier = (u64) rate * settings->p * 10000;
do_div(multiplier, parent_rate);
/*
* J can't be over 64, so R can scale this.
* R can't be greater than 4.
*/
settings->r = ((u32) multiplier / 640000) + 1;
if (settings->r > 4)
return -1;
do_div(multiplier, settings->r);
/*
* J can't be < 1.
*/
if (multiplier < 10000)
return -1;
/* Figure out the integer part, J, and the fractional part, D. */
settings->j = (u32) multiplier / 10000;
settings->d = (u32) multiplier % 10000;
return 0;
}
static unsigned long clk_aic32x4_pll_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
struct clk_aic32x4_pll_muldiv settings;
int ret;
ret = clk_aic32x4_pll_get_muldiv(pll, &settings);
if (ret < 0)
return 0;
return clk_aic32x4_pll_calc_rate(&settings, parent_rate);
}
static int clk_aic32x4_pll_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_aic32x4_pll_muldiv settings;
int ret;
ret = clk_aic32x4_pll_calc_muldiv(&settings, req->rate, req->best_parent_rate);
if (ret < 0)
return -EINVAL;
req->rate = clk_aic32x4_pll_calc_rate(&settings, req->best_parent_rate);
return 0;
}
static int clk_aic32x4_pll_set_rate(struct clk_hw *hw,
unsigned long rate,
unsigned long parent_rate)
{
struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
struct clk_aic32x4_pll_muldiv settings;
int ret;
ret = clk_aic32x4_pll_calc_muldiv(&settings, rate, parent_rate);
if (ret < 0)
return -EINVAL;
ret = clk_aic32x4_pll_set_muldiv(pll, &settings);
if (ret)
return ret;
/* 10ms is the delay to wait before the clocks are stable */
msleep(10);
return 0;
}
static int clk_aic32x4_pll_set_parent(struct clk_hw *hw, u8 index)
{
struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
return regmap_update_bits(pll->regmap,
AIC32X4_CLKMUX,
AIC32X4_PLL_CLKIN_MASK,
index << AIC32X4_PLL_CLKIN_SHIFT);
}
static u8 clk_aic32x4_pll_get_parent(struct clk_hw *hw)
{
struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
unsigned int val;
regmap_read(pll->regmap, AIC32X4_PLLPR, &val);
return (val & AIC32X4_PLL_CLKIN_MASK) >> AIC32X4_PLL_CLKIN_SHIFT;
}
static const struct clk_ops aic32x4_pll_ops = {
.prepare = clk_aic32x4_pll_prepare,
.unprepare = clk_aic32x4_pll_unprepare,
.is_prepared = clk_aic32x4_pll_is_prepared,
.recalc_rate = clk_aic32x4_pll_recalc_rate,
.determine_rate = clk_aic32x4_pll_determine_rate,
.set_rate = clk_aic32x4_pll_set_rate,
.set_parent = clk_aic32x4_pll_set_parent,
.get_parent = clk_aic32x4_pll_get_parent,
};
static int clk_aic32x4_codec_clkin_set_parent(struct clk_hw *hw, u8 index)
{
struct clk_aic32x4 *mux = to_clk_aic32x4(hw);
return regmap_update_bits(mux->regmap,
AIC32X4_CLKMUX,
AIC32X4_CODEC_CLKIN_MASK, index << AIC32X4_CODEC_CLKIN_SHIFT);
}
static u8 clk_aic32x4_codec_clkin_get_parent(struct clk_hw *hw)
{
struct clk_aic32x4 *mux = to_clk_aic32x4(hw);
unsigned int val;
regmap_read(mux->regmap, AIC32X4_CLKMUX, &val);
return (val & AIC32X4_CODEC_CLKIN_MASK) >> AIC32X4_CODEC_CLKIN_SHIFT;
}
static const struct clk_ops aic32x4_codec_clkin_ops = {
.determine_rate = clk_hw_determine_rate_no_reparent,
.set_parent = clk_aic32x4_codec_clkin_set_parent,
.get_parent = clk_aic32x4_codec_clkin_get_parent,
};
static int clk_aic32x4_div_prepare(struct clk_hw *hw)
{
struct clk_aic32x4 *div = to_clk_aic32x4(hw);
return regmap_update_bits(div->regmap, div->reg,
AIC32X4_DIVEN, AIC32X4_DIVEN);
}
static void clk_aic32x4_div_unprepare(struct clk_hw *hw)
{
struct clk_aic32x4 *div = to_clk_aic32x4(hw);
regmap_update_bits(div->regmap, div->reg,
AIC32X4_DIVEN, 0);
}
static int clk_aic32x4_div_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_aic32x4 *div = to_clk_aic32x4(hw);
u8 divisor;
divisor = DIV_ROUND_UP(parent_rate, rate);
if (divisor > AIC32X4_DIV_MAX)
return -EINVAL;
return regmap_update_bits(div->regmap, div->reg,
AIC32X4_DIV_MASK, divisor);
}
static int clk_aic32x4_div_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
unsigned long divisor;
divisor = DIV_ROUND_UP(req->best_parent_rate, req->rate);
if (divisor > AIC32X4_DIV_MAX)
return -EINVAL;
req->rate = DIV_ROUND_UP(req->best_parent_rate, divisor);
return 0;
}
static unsigned long clk_aic32x4_div_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_aic32x4 *div = to_clk_aic32x4(hw);
unsigned int val;
int err;
err = regmap_read(div->regmap, div->reg, &val);
if (err)
return 0;
val &= AIC32X4_DIV_MASK;
if (!val)
val = AIC32X4_DIV_MAX;
return DIV_ROUND_UP(parent_rate, val);
}
static const struct clk_ops aic32x4_div_ops = {
.prepare = clk_aic32x4_div_prepare,
.unprepare = clk_aic32x4_div_unprepare,
.set_rate = clk_aic32x4_div_set_rate,
.determine_rate = clk_aic32x4_div_determine_rate,
.recalc_rate = clk_aic32x4_div_recalc_rate,
};
static int clk_aic32x4_bdiv_set_parent(struct clk_hw *hw, u8 index)
{
struct clk_aic32x4 *mux = to_clk_aic32x4(hw);
return regmap_update_bits(mux->regmap, AIC32X4_IFACE3,
AIC32X4_BDIVCLK_MASK, index);
}
static u8 clk_aic32x4_bdiv_get_parent(struct clk_hw *hw)
{
struct clk_aic32x4 *mux = to_clk_aic32x4(hw);
unsigned int val;
regmap_read(mux->regmap, AIC32X4_IFACE3, &val);
return val & AIC32X4_BDIVCLK_MASK;
}
static const struct clk_ops aic32x4_bdiv_ops = {
.prepare = clk_aic32x4_div_prepare,
.unprepare = clk_aic32x4_div_unprepare,
.set_parent = clk_aic32x4_bdiv_set_parent,
.get_parent = clk_aic32x4_bdiv_get_parent,
.set_rate = clk_aic32x4_div_set_rate,
.determine_rate = clk_aic32x4_div_determine_rate,
.recalc_rate = clk_aic32x4_div_recalc_rate,
};
static struct aic32x4_clkdesc aic32x4_clkdesc_array[] = {
{
.name = "pll",
.parent_names =
(const char* []) { "mclk", "bclk", "gpio", "din" },
.num_parents = 4,
.ops = &aic32x4_pll_ops,
.reg = 0,
},
{
.name = "codec_clkin",
.parent_names =
(const char *[]) { "mclk", "bclk", "gpio", "pll" },
.num_parents = 4,
.ops = &aic32x4_codec_clkin_ops,
.reg = 0,
},
{
.name = "ndac",
.parent_names = (const char * []) { "codec_clkin" },
.num_parents = 1,
.ops = &aic32x4_div_ops,
.reg = AIC32X4_NDAC,
},
{
.name = "mdac",
.parent_names = (const char * []) { "ndac" },
.num_parents = 1,
.ops = &aic32x4_div_ops,
.reg = AIC32X4_MDAC,
},
{
.name = "nadc",
.parent_names = (const char * []) { "codec_clkin" },
.num_parents = 1,
.ops = &aic32x4_div_ops,
.reg = AIC32X4_NADC,
},
{
.name = "madc",
.parent_names = (const char * []) { "nadc" },
.num_parents = 1,
.ops = &aic32x4_div_ops,
.reg = AIC32X4_MADC,
},
{
.name = "bdiv",
.parent_names =
(const char *[]) { "ndac", "mdac", "nadc", "madc" },
.num_parents = 4,
.ops = &aic32x4_bdiv_ops,
.reg = AIC32X4_BCLKN,
},
};
static struct clk *aic32x4_register_clk(struct device *dev,
struct aic32x4_clkdesc *desc)
{
struct clk_init_data init;
struct clk_aic32x4 *priv;
const char *devname = dev_name(dev);
init.ops = desc->ops;
init.name = desc->name;
init.parent_names = desc->parent_names;
init.num_parents = desc->num_parents;
init.flags = 0;
priv = devm_kzalloc(dev, sizeof(struct clk_aic32x4), GFP_KERNEL);
if (priv == NULL)
return (struct clk *) -ENOMEM;
priv->dev = dev;
priv->hw.init = &init;
priv->regmap = dev_get_regmap(dev, NULL);
priv->reg = desc->reg;
clk_hw_register_clkdev(&priv->hw, desc->name, devname);
return devm_clk_register(dev, &priv->hw);
}
int aic32x4_register_clocks(struct device *dev, const char *mclk_name)
{
int i;
/*
* These lines are here to preserve the current functionality of
* the driver with regard to the DT. These should eventually be set
* by DT nodes so that the connections can be set up in configuration
* rather than code.
*/
aic32x4_clkdesc_array[0].parent_names =
(const char* []) { mclk_name, "bclk", "gpio", "din" };
aic32x4_clkdesc_array[1].parent_names =
(const char *[]) { mclk_name, "bclk", "gpio", "pll" };
for (i = 0; i < ARRAY_SIZE(aic32x4_clkdesc_array); ++i)
aic32x4_register_clk(dev, &aic32x4_clkdesc_array[i]);
return 0;
}
EXPORT_SYMBOL_GPL(aic32x4_register_clocks);
| linux-master | sound/soc/codecs/tlv320aic32x4-clk.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for generic Bluetooth SCO link
* Copyright 2011 Lars-Peter Clausen <[email protected]>
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <sound/soc.h>
static const struct snd_soc_dapm_widget bt_sco_widgets[] = {
SND_SOC_DAPM_INPUT("RX"),
SND_SOC_DAPM_OUTPUT("TX"),
SND_SOC_DAPM_AIF_IN("BT_SCO_RX", "Playback", 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("BT_SCO_TX", "Capture", 0,
SND_SOC_NOPM, 0, 0),
};
static const struct snd_soc_dapm_route bt_sco_routes[] = {
{ "BT_SCO_TX", NULL, "RX" },
{ "TX", NULL, "BT_SCO_RX" },
};
static struct snd_soc_dai_driver bt_sco_dai[] = {
{
.name = "bt-sco-pcm",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 1,
.rates = SNDRV_PCM_RATE_8000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 1,
.rates = SNDRV_PCM_RATE_8000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
},
{
.name = "bt-sco-pcm-wb",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 1,
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 1,
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
}
};
static const struct snd_soc_component_driver soc_component_dev_bt_sco = {
.dapm_widgets = bt_sco_widgets,
.num_dapm_widgets = ARRAY_SIZE(bt_sco_widgets),
.dapm_routes = bt_sco_routes,
.num_dapm_routes = ARRAY_SIZE(bt_sco_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int bt_sco_probe(struct platform_device *pdev)
{
return devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_bt_sco,
bt_sco_dai, ARRAY_SIZE(bt_sco_dai));
}
static const struct platform_device_id bt_sco_driver_ids[] = {
{
.name = "dfbmcs320",
},
{
.name = "bt-sco",
},
{},
};
MODULE_DEVICE_TABLE(platform, bt_sco_driver_ids);
#if defined(CONFIG_OF)
static const struct of_device_id bt_sco_codec_of_match[] = {
{ .compatible = "delta,dfbmcs320", },
{ .compatible = "linux,bt-sco", },
{},
};
MODULE_DEVICE_TABLE(of, bt_sco_codec_of_match);
#endif
static struct platform_driver bt_sco_driver = {
.driver = {
.name = "bt-sco",
.of_match_table = of_match_ptr(bt_sco_codec_of_match),
},
.probe = bt_sco_probe,
.id_table = bt_sco_driver_ids,
};
module_platform_driver(bt_sco_driver);
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_DESCRIPTION("ASoC generic bluetooth sco link driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/bt-sco.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* tas5720.c - ALSA SoC Texas Instruments TAS5720 Mono Audio Amplifier
*
* Copyright (C)2015-2016 Texas Instruments Incorporated - https://www.ti.com
*
* Author: Andreas Dannenberg <[email protected]>
*/
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/device.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/regulator/consumer.h>
#include <linux/delay.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/tlv.h>
#include "tas5720.h"
/* Define how often to check (and clear) the fault status register (in ms) */
#define TAS5720_FAULT_CHECK_INTERVAL 200
enum tas572x_type {
TAS5720,
TAS5720A_Q1,
TAS5722,
};
static const char * const tas5720_supply_names[] = {
"dvdd", /* Digital power supply. Connect to 3.3-V supply. */
"pvdd", /* Class-D amp and analog power supply (connected). */
};
#define TAS5720_NUM_SUPPLIES ARRAY_SIZE(tas5720_supply_names)
struct tas5720_data {
struct snd_soc_component *component;
struct regmap *regmap;
struct i2c_client *tas5720_client;
enum tas572x_type devtype;
struct regulator_bulk_data supplies[TAS5720_NUM_SUPPLIES];
struct delayed_work fault_check_work;
unsigned int last_fault;
};
static int tas5720_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
unsigned int rate = params_rate(params);
bool ssz_ds;
int ret;
switch (rate) {
case 44100:
case 48000:
ssz_ds = false;
break;
case 88200:
case 96000:
ssz_ds = true;
break;
default:
dev_err(component->dev, "unsupported sample rate: %u\n", rate);
return -EINVAL;
}
ret = snd_soc_component_update_bits(component, TAS5720_DIGITAL_CTRL1_REG,
TAS5720_SSZ_DS, ssz_ds);
if (ret < 0) {
dev_err(component->dev, "error setting sample rate: %d\n", ret);
return ret;
}
return 0;
}
static int tas5720_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
u8 serial_format;
int ret;
if ((fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) != SND_SOC_DAIFMT_CBC_CFC) {
dev_vdbg(component->dev, "DAI clocking invalid\n");
return -EINVAL;
}
switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
SND_SOC_DAIFMT_INV_MASK)) {
case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
/* 1st data bit occur one BCLK cycle after the frame sync */
serial_format = TAS5720_SAIF_I2S;
break;
case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_NB_NF):
/*
* Note that although the TAS5720 does not have a dedicated DSP
* mode it doesn't care about the LRCLK duty cycle during TDM
* operation. Therefore we can use the device's I2S mode with
* its delaying of the 1st data bit to receive DSP_A formatted
* data. See device datasheet for additional details.
*/
serial_format = TAS5720_SAIF_I2S;
break;
case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_NB_NF):
/*
* Similar to DSP_A, we can use the fact that the TAS5720 does
* not care about the LRCLK duty cycle during TDM to receive
* DSP_B formatted data in LEFTJ mode (no delaying of the 1st
* data bit).
*/
serial_format = TAS5720_SAIF_LEFTJ;
break;
case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
/* No delay after the frame sync */
serial_format = TAS5720_SAIF_LEFTJ;
break;
default:
dev_vdbg(component->dev, "DAI Format is not found\n");
return -EINVAL;
}
ret = snd_soc_component_update_bits(component, TAS5720_DIGITAL_CTRL1_REG,
TAS5720_SAIF_FORMAT_MASK,
serial_format);
if (ret < 0) {
dev_err(component->dev, "error setting SAIF format: %d\n", ret);
return ret;
}
return 0;
}
static int tas5720_set_dai_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask,
int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
struct tas5720_data *tas5720 = snd_soc_component_get_drvdata(component);
unsigned int first_slot;
int ret;
if (!tx_mask) {
dev_err(component->dev, "tx masks must not be 0\n");
return -EINVAL;
}
/*
* Determine the first slot that is being requested. We will only
* use the first slot that is found since the TAS5720 is a mono
* amplifier.
*/
first_slot = __ffs(tx_mask);
if (first_slot > 7) {
dev_err(component->dev, "slot selection out of bounds (%u)\n",
first_slot);
return -EINVAL;
}
/*
* Enable manual TDM slot selection (instead of I2C ID based).
* This is not applicable to TAS5720A-Q1.
*/
switch (tas5720->devtype) {
case TAS5720A_Q1:
break;
default:
ret = snd_soc_component_update_bits(component, TAS5720_DIGITAL_CTRL1_REG,
TAS5720_TDM_CFG_SRC, TAS5720_TDM_CFG_SRC);
if (ret < 0)
goto error_snd_soc_component_update_bits;
/* Configure the TDM slot to process audio from */
ret = snd_soc_component_update_bits(component, TAS5720_DIGITAL_CTRL2_REG,
TAS5720_TDM_SLOT_SEL_MASK, first_slot);
if (ret < 0)
goto error_snd_soc_component_update_bits;
break;
}
/* Configure TDM slot width. This is only applicable to TAS5722. */
switch (tas5720->devtype) {
case TAS5722:
ret = snd_soc_component_update_bits(component, TAS5722_DIGITAL_CTRL2_REG,
TAS5722_TDM_SLOT_16B,
slot_width == 16 ?
TAS5722_TDM_SLOT_16B : 0);
if (ret < 0)
goto error_snd_soc_component_update_bits;
break;
default:
break;
}
return 0;
error_snd_soc_component_update_bits:
dev_err(component->dev, "error configuring TDM mode: %d\n", ret);
return ret;
}
static int tas5720_mute_soc_component(struct snd_soc_component *component, int mute)
{
struct tas5720_data *tas5720 = snd_soc_component_get_drvdata(component);
unsigned int reg, mask;
int ret;
switch (tas5720->devtype) {
case TAS5720A_Q1:
reg = TAS5720_Q1_VOLUME_CTRL_CFG_REG;
mask = TAS5720_Q1_MUTE;
break;
default:
reg = TAS5720_DIGITAL_CTRL2_REG;
mask = TAS5720_MUTE;
break;
}
ret = snd_soc_component_update_bits(component, reg, mask, mute ? mask : 0);
if (ret < 0) {
dev_err(component->dev, "error (un-)muting device: %d\n", ret);
return ret;
}
return 0;
}
static int tas5720_mute(struct snd_soc_dai *dai, int mute, int direction)
{
return tas5720_mute_soc_component(dai->component, mute);
}
static void tas5720_fault_check_work(struct work_struct *work)
{
struct tas5720_data *tas5720 = container_of(work, struct tas5720_data,
fault_check_work.work);
struct device *dev = tas5720->component->dev;
unsigned int curr_fault;
int ret;
ret = regmap_read(tas5720->regmap, TAS5720_FAULT_REG, &curr_fault);
if (ret < 0) {
dev_err(dev, "failed to read FAULT register: %d\n", ret);
goto out;
}
/* Check/handle all errors except SAIF clock errors */
curr_fault &= TAS5720_OCE | TAS5720_DCE | TAS5720_OTE;
/*
* Only flag errors once for a given occurrence. This is needed as
* the TAS5720 will take time clearing the fault condition internally
* during which we don't want to bombard the system with the same
* error message over and over.
*/
if ((curr_fault & TAS5720_OCE) && !(tas5720->last_fault & TAS5720_OCE))
dev_crit(dev, "experienced an over current hardware fault\n");
if ((curr_fault & TAS5720_DCE) && !(tas5720->last_fault & TAS5720_DCE))
dev_crit(dev, "experienced a DC detection fault\n");
if ((curr_fault & TAS5720_OTE) && !(tas5720->last_fault & TAS5720_OTE))
dev_crit(dev, "experienced an over temperature fault\n");
/* Store current fault value so we can detect any changes next time */
tas5720->last_fault = curr_fault;
if (!curr_fault)
goto out;
/*
* Periodically toggle SDZ (shutdown bit) H->L->H to clear any latching
* faults as long as a fault condition persists. Always going through
* the full sequence no matter the first return value to minimizes
* chances for the device to end up in shutdown mode.
*/
ret = regmap_write_bits(tas5720->regmap, TAS5720_POWER_CTRL_REG,
TAS5720_SDZ, 0);
if (ret < 0)
dev_err(dev, "failed to write POWER_CTRL register: %d\n", ret);
ret = regmap_write_bits(tas5720->regmap, TAS5720_POWER_CTRL_REG,
TAS5720_SDZ, TAS5720_SDZ);
if (ret < 0)
dev_err(dev, "failed to write POWER_CTRL register: %d\n", ret);
out:
/* Schedule the next fault check at the specified interval */
schedule_delayed_work(&tas5720->fault_check_work,
msecs_to_jiffies(TAS5720_FAULT_CHECK_INTERVAL));
}
static int tas5720_codec_probe(struct snd_soc_component *component)
{
struct tas5720_data *tas5720 = snd_soc_component_get_drvdata(component);
unsigned int device_id, expected_device_id;
int ret;
tas5720->component = component;
ret = regulator_bulk_enable(ARRAY_SIZE(tas5720->supplies),
tas5720->supplies);
if (ret != 0) {
dev_err(component->dev, "failed to enable supplies: %d\n", ret);
return ret;
}
/*
* Take a liberal approach to checking the device ID to allow the
* driver to be used even if the device ID does not match, however
* issue a warning if there is a mismatch.
*/
ret = regmap_read(tas5720->regmap, TAS5720_DEVICE_ID_REG, &device_id);
if (ret < 0) {
dev_err(component->dev, "failed to read device ID register: %d\n",
ret);
goto probe_fail;
}
switch (tas5720->devtype) {
case TAS5720:
expected_device_id = TAS5720_DEVICE_ID;
break;
case TAS5720A_Q1:
expected_device_id = TAS5720A_Q1_DEVICE_ID;
break;
case TAS5722:
expected_device_id = TAS5722_DEVICE_ID;
break;
default:
dev_err(component->dev, "unexpected private driver data\n");
ret = -EINVAL;
goto probe_fail;
}
if (device_id != expected_device_id)
dev_warn(component->dev, "wrong device ID. expected: %u read: %u\n",
expected_device_id, device_id);
/* Set device to mute */
ret = tas5720_mute_soc_component(component, 1);
if (ret < 0)
goto error_snd_soc_component_update_bits;
/* Set Bit 7 in TAS5720_ANALOG_CTRL_REG to 1 for TAS5720A_Q1 */
switch (tas5720->devtype) {
case TAS5720A_Q1:
ret = snd_soc_component_update_bits(component, TAS5720_ANALOG_CTRL_REG,
TAS5720_Q1_RESERVED7_BIT,
TAS5720_Q1_RESERVED7_BIT);
break;
default:
break;
}
if (ret < 0)
goto error_snd_soc_component_update_bits;
/*
* Enter shutdown mode - our default when not playing audio - to
* minimize current consumption. On the TAS5720 there is no real down
* side doing so as all device registers are preserved and the wakeup
* of the codec is rather quick which we do using a dapm widget.
*/
ret = snd_soc_component_update_bits(component, TAS5720_POWER_CTRL_REG,
TAS5720_SDZ, 0);
if (ret < 0)
goto error_snd_soc_component_update_bits;
INIT_DELAYED_WORK(&tas5720->fault_check_work, tas5720_fault_check_work);
return 0;
error_snd_soc_component_update_bits:
dev_err(component->dev, "error configuring device registers: %d\n", ret);
probe_fail:
regulator_bulk_disable(ARRAY_SIZE(tas5720->supplies),
tas5720->supplies);
return ret;
}
static void tas5720_codec_remove(struct snd_soc_component *component)
{
struct tas5720_data *tas5720 = snd_soc_component_get_drvdata(component);
int ret;
cancel_delayed_work_sync(&tas5720->fault_check_work);
ret = regulator_bulk_disable(ARRAY_SIZE(tas5720->supplies),
tas5720->supplies);
if (ret < 0)
dev_err(component->dev, "failed to disable supplies: %d\n", ret);
};
static int tas5720_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct tas5720_data *tas5720 = snd_soc_component_get_drvdata(component);
int ret;
if (event & SND_SOC_DAPM_POST_PMU) {
/* Take TAS5720 out of shutdown mode */
ret = snd_soc_component_update_bits(component, TAS5720_POWER_CTRL_REG,
TAS5720_SDZ, TAS5720_SDZ);
if (ret < 0) {
dev_err(component->dev, "error waking component: %d\n", ret);
return ret;
}
/*
* Observe codec shutdown-to-active time. The datasheet only
* lists a nominal value however just use-it as-is without
* additional padding to minimize the delay introduced in
* starting to play audio (actually there is other setup done
* by the ASoC framework that will provide additional delays,
* so we should always be safe).
*/
msleep(25);
/* Turn on TAS5720 periodic fault checking/handling */
tas5720->last_fault = 0;
schedule_delayed_work(&tas5720->fault_check_work,
msecs_to_jiffies(TAS5720_FAULT_CHECK_INTERVAL));
} else if (event & SND_SOC_DAPM_PRE_PMD) {
/* Disable TAS5720 periodic fault checking/handling */
cancel_delayed_work_sync(&tas5720->fault_check_work);
/* Place TAS5720 in shutdown mode to minimize current draw */
ret = snd_soc_component_update_bits(component, TAS5720_POWER_CTRL_REG,
TAS5720_SDZ, 0);
if (ret < 0) {
dev_err(component->dev, "error shutting down component: %d\n",
ret);
return ret;
}
}
return 0;
}
#ifdef CONFIG_PM
static int tas5720_suspend(struct snd_soc_component *component)
{
struct tas5720_data *tas5720 = snd_soc_component_get_drvdata(component);
int ret;
regcache_cache_only(tas5720->regmap, true);
regcache_mark_dirty(tas5720->regmap);
ret = regulator_bulk_disable(ARRAY_SIZE(tas5720->supplies),
tas5720->supplies);
if (ret < 0)
dev_err(component->dev, "failed to disable supplies: %d\n", ret);
return ret;
}
static int tas5720_resume(struct snd_soc_component *component)
{
struct tas5720_data *tas5720 = snd_soc_component_get_drvdata(component);
int ret;
ret = regulator_bulk_enable(ARRAY_SIZE(tas5720->supplies),
tas5720->supplies);
if (ret < 0) {
dev_err(component->dev, "failed to enable supplies: %d\n", ret);
return ret;
}
regcache_cache_only(tas5720->regmap, false);
ret = regcache_sync(tas5720->regmap);
if (ret < 0) {
dev_err(component->dev, "failed to sync regcache: %d\n", ret);
return ret;
}
return 0;
}
#else
#define tas5720_suspend NULL
#define tas5720_resume NULL
#endif
static bool tas5720_is_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TAS5720_DEVICE_ID_REG:
case TAS5720_FAULT_REG:
return true;
default:
return false;
}
}
static const struct regmap_config tas5720_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = TAS5720_MAX_REG,
.cache_type = REGCACHE_RBTREE,
.volatile_reg = tas5720_is_volatile_reg,
};
static const struct regmap_config tas5720a_q1_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = TAS5720_MAX_REG,
.cache_type = REGCACHE_RBTREE,
.volatile_reg = tas5720_is_volatile_reg,
};
static const struct regmap_config tas5722_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = TAS5722_MAX_REG,
.cache_type = REGCACHE_RBTREE,
.volatile_reg = tas5720_is_volatile_reg,
};
/*
* DAC analog gain. There are four discrete values to select from, ranging
* from 19.2 dB to 26.3dB.
*/
static const DECLARE_TLV_DB_RANGE(dac_analog_tlv,
0x0, 0x0, TLV_DB_SCALE_ITEM(1920, 0, 0),
0x1, 0x1, TLV_DB_SCALE_ITEM(2070, 0, 0),
0x2, 0x2, TLV_DB_SCALE_ITEM(2350, 0, 0),
0x3, 0x3, TLV_DB_SCALE_ITEM(2630, 0, 0),
);
/*
* DAC analog gain for TAS5720A-Q1. There are three discrete values to select from, ranging
* from 19.2 dB to 25.0dB.
*/
static const DECLARE_TLV_DB_RANGE(dac_analog_tlv_a_q1,
0x0, 0x0, TLV_DB_SCALE_ITEM(1920, 0, 0),
0x1, 0x1, TLV_DB_SCALE_ITEM(2260, 0, 0),
0x2, 0x2, TLV_DB_SCALE_ITEM(2500, 0, 0),
);
/*
* DAC digital volumes. From -103.5 to 24 dB in 0.5 dB or 0.25 dB steps
* depending on the device. Note that setting the gain below -100 dB
* (register value <0x7) is effectively a MUTE as per device datasheet.
*
* Note that for the TAS5722 the digital volume controls are actually split
* over two registers, so we need custom getters/setters for access.
*/
static DECLARE_TLV_DB_SCALE(tas5720_dac_tlv, -10350, 50, 0);
static DECLARE_TLV_DB_SCALE(tas5722_dac_tlv, -10350, 25, 0);
static int tas5722_volume_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
unsigned int val;
val = snd_soc_component_read(component, TAS5720_VOLUME_CTRL_REG);
ucontrol->value.integer.value[0] = val << 1;
val = snd_soc_component_read(component, TAS5722_DIGITAL_CTRL2_REG);
ucontrol->value.integer.value[0] |= val & TAS5722_VOL_CONTROL_LSB;
return 0;
}
static int tas5722_volume_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
unsigned int sel = ucontrol->value.integer.value[0];
snd_soc_component_write(component, TAS5720_VOLUME_CTRL_REG, sel >> 1);
snd_soc_component_update_bits(component, TAS5722_DIGITAL_CTRL2_REG,
TAS5722_VOL_CONTROL_LSB, sel);
return 0;
}
static const struct snd_kcontrol_new tas5720_snd_controls[] = {
SOC_SINGLE_TLV("Speaker Driver Playback Volume",
TAS5720_VOLUME_CTRL_REG, 0, 0xff, 0, tas5720_dac_tlv),
SOC_SINGLE_TLV("Speaker Driver Analog Gain", TAS5720_ANALOG_CTRL_REG,
TAS5720_ANALOG_GAIN_SHIFT, 3, 0, dac_analog_tlv),
};
static const struct snd_kcontrol_new tas5720a_q1_snd_controls[] = {
SOC_DOUBLE_R_TLV("Speaker Driver Playback Volume",
TAS5720_Q1_VOLUME_CTRL_LEFT_REG,
TAS5720_Q1_VOLUME_CTRL_RIGHT_REG,
0, 0xff, 0, tas5720_dac_tlv),
SOC_SINGLE_TLV("Speaker Driver Analog Gain", TAS5720_ANALOG_CTRL_REG,
TAS5720_ANALOG_GAIN_SHIFT, 3, 0, dac_analog_tlv_a_q1),
};
static const struct snd_kcontrol_new tas5722_snd_controls[] = {
SOC_SINGLE_EXT_TLV("Speaker Driver Playback Volume",
0, 0, 511, 0,
tas5722_volume_get, tas5722_volume_set,
tas5722_dac_tlv),
SOC_SINGLE_TLV("Speaker Driver Analog Gain", TAS5720_ANALOG_CTRL_REG,
TAS5720_ANALOG_GAIN_SHIFT, 3, 0, dac_analog_tlv),
};
static const struct snd_soc_dapm_widget tas5720_dapm_widgets[] = {
SND_SOC_DAPM_AIF_IN("DAC IN", "Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC_E("DAC", NULL, SND_SOC_NOPM, 0, 0, tas5720_dac_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_OUTPUT("OUT")
};
static const struct snd_soc_dapm_route tas5720_audio_map[] = {
{ "DAC", NULL, "DAC IN" },
{ "OUT", NULL, "DAC" },
};
static const struct snd_soc_component_driver soc_component_dev_tas5720 = {
.probe = tas5720_codec_probe,
.remove = tas5720_codec_remove,
.suspend = tas5720_suspend,
.resume = tas5720_resume,
.controls = tas5720_snd_controls,
.num_controls = ARRAY_SIZE(tas5720_snd_controls),
.dapm_widgets = tas5720_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(tas5720_dapm_widgets),
.dapm_routes = tas5720_audio_map,
.num_dapm_routes = ARRAY_SIZE(tas5720_audio_map),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct snd_soc_component_driver soc_component_dev_tas5720_a_q1 = {
.probe = tas5720_codec_probe,
.remove = tas5720_codec_remove,
.suspend = tas5720_suspend,
.resume = tas5720_resume,
.controls = tas5720a_q1_snd_controls,
.num_controls = ARRAY_SIZE(tas5720a_q1_snd_controls),
.dapm_widgets = tas5720_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(tas5720_dapm_widgets),
.dapm_routes = tas5720_audio_map,
.num_dapm_routes = ARRAY_SIZE(tas5720_audio_map),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct snd_soc_component_driver soc_component_dev_tas5722 = {
.probe = tas5720_codec_probe,
.remove = tas5720_codec_remove,
.suspend = tas5720_suspend,
.resume = tas5720_resume,
.controls = tas5722_snd_controls,
.num_controls = ARRAY_SIZE(tas5722_snd_controls),
.dapm_widgets = tas5720_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(tas5720_dapm_widgets),
.dapm_routes = tas5720_audio_map,
.num_dapm_routes = ARRAY_SIZE(tas5720_audio_map),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
/* PCM rates supported by the TAS5720 driver */
#define TAS5720_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
/* Formats supported by TAS5720 driver */
#define TAS5720_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE |\
SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE)
static const struct snd_soc_dai_ops tas5720_speaker_dai_ops = {
.hw_params = tas5720_hw_params,
.set_fmt = tas5720_set_dai_fmt,
.set_tdm_slot = tas5720_set_dai_tdm_slot,
.mute_stream = tas5720_mute,
.no_capture_mute = 1,
};
/*
* TAS5720 DAI structure
*
* Note that were are advertising .playback.channels_max = 2 despite this being
* a mono amplifier. The reason for that is that some serial ports such as TI's
* McASP module have a minimum number of channels (2) that they can output.
* Advertising more channels than we have will allow us to interface with such
* a serial port without really any negative side effects as the TAS5720 will
* simply ignore any extra channel(s) asides from the one channel that is
* configured to be played back.
*/
static struct snd_soc_dai_driver tas5720_dai[] = {
{
.name = "tas5720-amplifier",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = TAS5720_RATES,
.formats = TAS5720_FORMATS,
},
.ops = &tas5720_speaker_dai_ops,
},
};
static const struct i2c_device_id tas5720_id[] = {
{ "tas5720", TAS5720 },
{ "tas5720a-q1", TAS5720A_Q1 },
{ "tas5722", TAS5722 },
{ }
};
MODULE_DEVICE_TABLE(i2c, tas5720_id);
static int tas5720_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct tas5720_data *data;
const struct regmap_config *regmap_config;
const struct i2c_device_id *id;
int ret;
int i;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
id = i2c_match_id(tas5720_id, client);
data->tas5720_client = client;
data->devtype = id->driver_data;
switch (id->driver_data) {
case TAS5720:
regmap_config = &tas5720_regmap_config;
break;
case TAS5720A_Q1:
regmap_config = &tas5720a_q1_regmap_config;
break;
case TAS5722:
regmap_config = &tas5722_regmap_config;
break;
default:
dev_err(dev, "unexpected private driver data\n");
return -EINVAL;
}
data->regmap = devm_regmap_init_i2c(client, regmap_config);
if (IS_ERR(data->regmap)) {
ret = PTR_ERR(data->regmap);
dev_err(dev, "failed to allocate register map: %d\n", ret);
return ret;
}
for (i = 0; i < ARRAY_SIZE(data->supplies); i++)
data->supplies[i].supply = tas5720_supply_names[i];
ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(data->supplies),
data->supplies);
if (ret != 0) {
dev_err(dev, "failed to request supplies: %d\n", ret);
return ret;
}
dev_set_drvdata(dev, data);
switch (id->driver_data) {
case TAS5720:
ret = devm_snd_soc_register_component(&client->dev,
&soc_component_dev_tas5720,
tas5720_dai,
ARRAY_SIZE(tas5720_dai));
break;
case TAS5720A_Q1:
ret = devm_snd_soc_register_component(&client->dev,
&soc_component_dev_tas5720_a_q1,
tas5720_dai,
ARRAY_SIZE(tas5720_dai));
break;
case TAS5722:
ret = devm_snd_soc_register_component(&client->dev,
&soc_component_dev_tas5722,
tas5720_dai,
ARRAY_SIZE(tas5720_dai));
break;
default:
dev_err(dev, "unexpected private driver data\n");
return -EINVAL;
}
if (ret < 0) {
dev_err(dev, "failed to register component: %d\n", ret);
return ret;
}
return 0;
}
#if IS_ENABLED(CONFIG_OF)
static const struct of_device_id tas5720_of_match[] = {
{ .compatible = "ti,tas5720", },
{ .compatible = "ti,tas5720a-q1", },
{ .compatible = "ti,tas5722", },
{ },
};
MODULE_DEVICE_TABLE(of, tas5720_of_match);
#endif
static struct i2c_driver tas5720_i2c_driver = {
.driver = {
.name = "tas5720",
.of_match_table = of_match_ptr(tas5720_of_match),
},
.probe = tas5720_probe,
.id_table = tas5720_id,
};
module_i2c_driver(tas5720_i2c_driver);
MODULE_AUTHOR("Andreas Dannenberg <[email protected]>");
MODULE_DESCRIPTION("TAS5720 Audio amplifier driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/tas5720.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* rt5663.c -- RT5663 ALSA SoC audio codec driver
*
* Copyright 2016 Realtek Semiconductor Corp.
* Author: Jack Yu <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/acpi.h>
#include <linux/regulator/consumer.h>
#include <linux/workqueue.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/jack.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "rt5663.h"
#include "rl6231.h"
#define RT5663_DEVICE_ID_2 0x6451
#define RT5663_DEVICE_ID_1 0x6406
#define RT5663_POWER_ON_DELAY_MS 300
#define RT5663_SUPPLY_CURRENT_UA 500000
enum {
CODEC_VER_1,
CODEC_VER_0,
};
struct impedance_mapping_table {
unsigned int imp_min;
unsigned int imp_max;
unsigned int vol;
unsigned int dc_offset_l_manual;
unsigned int dc_offset_r_manual;
unsigned int dc_offset_l_manual_mic;
unsigned int dc_offset_r_manual_mic;
};
static const char *const rt5663_supply_names[] = {
"avdd",
"cpvdd",
};
struct rt5663_priv {
struct snd_soc_component *component;
struct rt5663_platform_data pdata;
struct regmap *regmap;
struct delayed_work jack_detect_work, jd_unplug_work;
struct snd_soc_jack *hs_jack;
struct timer_list btn_check_timer;
struct impedance_mapping_table *imp_table;
struct regulator_bulk_data supplies[ARRAY_SIZE(rt5663_supply_names)];
int codec_ver;
int sysclk;
int sysclk_src;
int lrck;
int pll_src;
int pll_in;
int pll_out;
int jack_type;
};
static const struct reg_sequence rt5663_patch_list[] = {
{ 0x002a, 0x8020 },
{ 0x0086, 0x0028 },
{ 0x0100, 0xa020 },
{ 0x0117, 0x0f28 },
{ 0x02fb, 0x8089 },
};
static const struct reg_default rt5663_v2_reg[] = {
{ 0x0000, 0x0000 },
{ 0x0001, 0xc8c8 },
{ 0x0002, 0x8080 },
{ 0x0003, 0x8000 },
{ 0x0004, 0xc80a },
{ 0x0005, 0x0000 },
{ 0x0006, 0x0000 },
{ 0x0007, 0x0000 },
{ 0x000a, 0x0000 },
{ 0x000b, 0x0000 },
{ 0x000c, 0x0000 },
{ 0x000d, 0x0000 },
{ 0x000f, 0x0808 },
{ 0x0010, 0x4000 },
{ 0x0011, 0x0000 },
{ 0x0012, 0x1404 },
{ 0x0013, 0x1000 },
{ 0x0014, 0xa00a },
{ 0x0015, 0x0404 },
{ 0x0016, 0x0404 },
{ 0x0017, 0x0011 },
{ 0x0018, 0xafaf },
{ 0x0019, 0xafaf },
{ 0x001a, 0xafaf },
{ 0x001b, 0x0011 },
{ 0x001c, 0x2f2f },
{ 0x001d, 0x2f2f },
{ 0x001e, 0x2f2f },
{ 0x001f, 0x0000 },
{ 0x0020, 0x0000 },
{ 0x0021, 0x0000 },
{ 0x0022, 0x5757 },
{ 0x0023, 0x0039 },
{ 0x0024, 0x000b },
{ 0x0026, 0xc0c0 },
{ 0x0027, 0xc0c0 },
{ 0x0028, 0xc0c0 },
{ 0x0029, 0x8080 },
{ 0x002a, 0xaaaa },
{ 0x002b, 0xaaaa },
{ 0x002c, 0xaba8 },
{ 0x002d, 0x0000 },
{ 0x002e, 0x0000 },
{ 0x002f, 0x0000 },
{ 0x0030, 0x0000 },
{ 0x0031, 0x5000 },
{ 0x0032, 0x0000 },
{ 0x0033, 0x0000 },
{ 0x0034, 0x0000 },
{ 0x0035, 0x0000 },
{ 0x003a, 0x0000 },
{ 0x003b, 0x0000 },
{ 0x003c, 0x00ff },
{ 0x003d, 0x0000 },
{ 0x003e, 0x00ff },
{ 0x003f, 0x0000 },
{ 0x0040, 0x0000 },
{ 0x0041, 0x00ff },
{ 0x0042, 0x0000 },
{ 0x0043, 0x00ff },
{ 0x0044, 0x0c0c },
{ 0x0049, 0xc00b },
{ 0x004a, 0x0000 },
{ 0x004b, 0x031f },
{ 0x004d, 0x0000 },
{ 0x004e, 0x001f },
{ 0x004f, 0x0000 },
{ 0x0050, 0x001f },
{ 0x0052, 0xf000 },
{ 0x0061, 0x0000 },
{ 0x0062, 0x0000 },
{ 0x0063, 0x003e },
{ 0x0064, 0x0000 },
{ 0x0065, 0x0000 },
{ 0x0066, 0x003f },
{ 0x0067, 0x0000 },
{ 0x006b, 0x0000 },
{ 0x006d, 0xff00 },
{ 0x006e, 0x2808 },
{ 0x006f, 0x000a },
{ 0x0070, 0x8000 },
{ 0x0071, 0x8000 },
{ 0x0072, 0x8000 },
{ 0x0073, 0x7000 },
{ 0x0074, 0x7770 },
{ 0x0075, 0x0002 },
{ 0x0076, 0x0001 },
{ 0x0078, 0x00f0 },
{ 0x0079, 0x0000 },
{ 0x007a, 0x0000 },
{ 0x007b, 0x0000 },
{ 0x007c, 0x0000 },
{ 0x007d, 0x0123 },
{ 0x007e, 0x4500 },
{ 0x007f, 0x8003 },
{ 0x0080, 0x0000 },
{ 0x0081, 0x0000 },
{ 0x0082, 0x0000 },
{ 0x0083, 0x0000 },
{ 0x0084, 0x0000 },
{ 0x0085, 0x0000 },
{ 0x0086, 0x0008 },
{ 0x0087, 0x0000 },
{ 0x0088, 0x0000 },
{ 0x0089, 0x0000 },
{ 0x008a, 0x0000 },
{ 0x008b, 0x0000 },
{ 0x008c, 0x0003 },
{ 0x008e, 0x0060 },
{ 0x008f, 0x1000 },
{ 0x0091, 0x0c26 },
{ 0x0092, 0x0073 },
{ 0x0093, 0x0000 },
{ 0x0094, 0x0080 },
{ 0x0098, 0x0000 },
{ 0x0099, 0x0000 },
{ 0x009a, 0x0007 },
{ 0x009f, 0x0000 },
{ 0x00a0, 0x0000 },
{ 0x00a1, 0x0002 },
{ 0x00a2, 0x0001 },
{ 0x00a3, 0x0002 },
{ 0x00a4, 0x0001 },
{ 0x00ae, 0x2040 },
{ 0x00af, 0x0000 },
{ 0x00b6, 0x0000 },
{ 0x00b7, 0x0000 },
{ 0x00b8, 0x0000 },
{ 0x00b9, 0x0000 },
{ 0x00ba, 0x0002 },
{ 0x00bb, 0x0000 },
{ 0x00be, 0x0000 },
{ 0x00c0, 0x0000 },
{ 0x00c1, 0x0aaa },
{ 0x00c2, 0xaa80 },
{ 0x00c3, 0x0003 },
{ 0x00c4, 0x0000 },
{ 0x00d0, 0x0000 },
{ 0x00d1, 0x2244 },
{ 0x00d2, 0x0000 },
{ 0x00d3, 0x3300 },
{ 0x00d4, 0x2200 },
{ 0x00d9, 0x0809 },
{ 0x00da, 0x0000 },
{ 0x00db, 0x0008 },
{ 0x00dc, 0x00c0 },
{ 0x00dd, 0x6724 },
{ 0x00de, 0x3131 },
{ 0x00df, 0x0008 },
{ 0x00e0, 0x4000 },
{ 0x00e1, 0x3131 },
{ 0x00e2, 0x600c },
{ 0x00ea, 0xb320 },
{ 0x00eb, 0x0000 },
{ 0x00ec, 0xb300 },
{ 0x00ed, 0x0000 },
{ 0x00ee, 0xb320 },
{ 0x00ef, 0x0000 },
{ 0x00f0, 0x0201 },
{ 0x00f1, 0x0ddd },
{ 0x00f2, 0x0ddd },
{ 0x00f6, 0x0000 },
{ 0x00f7, 0x0000 },
{ 0x00f8, 0x0000 },
{ 0x00fa, 0x0000 },
{ 0x00fb, 0x0000 },
{ 0x00fc, 0x0000 },
{ 0x00fd, 0x0000 },
{ 0x00fe, 0x10ec },
{ 0x00ff, 0x6451 },
{ 0x0100, 0xaaaa },
{ 0x0101, 0x000a },
{ 0x010a, 0xaaaa },
{ 0x010b, 0xa0a0 },
{ 0x010c, 0xaeae },
{ 0x010d, 0xaaaa },
{ 0x010e, 0xaaaa },
{ 0x010f, 0xaaaa },
{ 0x0110, 0xe002 },
{ 0x0111, 0xa602 },
{ 0x0112, 0xaaaa },
{ 0x0113, 0x2000 },
{ 0x0117, 0x0f00 },
{ 0x0125, 0x0420 },
{ 0x0132, 0x0000 },
{ 0x0133, 0x0000 },
{ 0x0136, 0x5555 },
{ 0x0137, 0x5540 },
{ 0x0138, 0x3700 },
{ 0x0139, 0x79a1 },
{ 0x013a, 0x2020 },
{ 0x013b, 0x2020 },
{ 0x013c, 0x2005 },
{ 0x013f, 0x0000 },
{ 0x0145, 0x0002 },
{ 0x0146, 0x0000 },
{ 0x0147, 0x0000 },
{ 0x0148, 0x0000 },
{ 0x0160, 0x4ec0 },
{ 0x0161, 0x0080 },
{ 0x0162, 0x0200 },
{ 0x0163, 0x0800 },
{ 0x0164, 0x0000 },
{ 0x0165, 0x0000 },
{ 0x0166, 0x0000 },
{ 0x0167, 0x000f },
{ 0x0168, 0x000f },
{ 0x0170, 0x4e80 },
{ 0x0171, 0x0080 },
{ 0x0172, 0x0200 },
{ 0x0173, 0x0800 },
{ 0x0174, 0x00ff },
{ 0x0175, 0x0000 },
{ 0x0190, 0x4131 },
{ 0x0191, 0x4131 },
{ 0x0192, 0x4131 },
{ 0x0193, 0x4131 },
{ 0x0194, 0x0000 },
{ 0x0195, 0x0000 },
{ 0x0196, 0x0000 },
{ 0x0197, 0x0000 },
{ 0x0198, 0x0000 },
{ 0x0199, 0x0000 },
{ 0x01a0, 0x1e64 },
{ 0x01a1, 0x06a3 },
{ 0x01a2, 0x0000 },
{ 0x01a3, 0x0000 },
{ 0x01a4, 0x0000 },
{ 0x01a5, 0x0000 },
{ 0x01a6, 0x0000 },
{ 0x01a7, 0x0000 },
{ 0x01a8, 0x0000 },
{ 0x01a9, 0x0000 },
{ 0x01aa, 0x0000 },
{ 0x01ab, 0x0000 },
{ 0x01b5, 0x0000 },
{ 0x01b6, 0x01c3 },
{ 0x01b7, 0x02a0 },
{ 0x01b8, 0x03e9 },
{ 0x01b9, 0x1389 },
{ 0x01ba, 0xc351 },
{ 0x01bb, 0x0009 },
{ 0x01bc, 0x0018 },
{ 0x01bd, 0x002a },
{ 0x01be, 0x004c },
{ 0x01bf, 0x0097 },
{ 0x01c0, 0x433d },
{ 0x01c1, 0x0000 },
{ 0x01c2, 0x0000 },
{ 0x01c3, 0x0000 },
{ 0x01c4, 0x0000 },
{ 0x01c5, 0x0000 },
{ 0x01c6, 0x0000 },
{ 0x01c7, 0x0000 },
{ 0x01c8, 0x40af },
{ 0x01c9, 0x0702 },
{ 0x01ca, 0x0000 },
{ 0x01cb, 0x0000 },
{ 0x01cc, 0x5757 },
{ 0x01cd, 0x5757 },
{ 0x01ce, 0x5757 },
{ 0x01cf, 0x5757 },
{ 0x01d0, 0x5757 },
{ 0x01d1, 0x5757 },
{ 0x01d2, 0x5757 },
{ 0x01d3, 0x5757 },
{ 0x01d4, 0x5757 },
{ 0x01d5, 0x5757 },
{ 0x01d6, 0x003c },
{ 0x01da, 0x0000 },
{ 0x01db, 0x0000 },
{ 0x01dc, 0x0000 },
{ 0x01de, 0x7c00 },
{ 0x01df, 0x0320 },
{ 0x01e0, 0x06a1 },
{ 0x01e1, 0x0000 },
{ 0x01e2, 0x0000 },
{ 0x01e3, 0x0000 },
{ 0x01e4, 0x0000 },
{ 0x01e5, 0x0000 },
{ 0x01e6, 0x0001 },
{ 0x01e7, 0x0000 },
{ 0x01e8, 0x0000 },
{ 0x01ea, 0x0000 },
{ 0x01eb, 0x0000 },
{ 0x01ec, 0x0000 },
{ 0x01ed, 0x0000 },
{ 0x01ee, 0x0000 },
{ 0x01ef, 0x0000 },
{ 0x01f0, 0x0000 },
{ 0x01f1, 0x0000 },
{ 0x01f2, 0x0000 },
{ 0x01f3, 0x0000 },
{ 0x01f4, 0x0000 },
{ 0x0200, 0x0000 },
{ 0x0201, 0x0000 },
{ 0x0202, 0x0000 },
{ 0x0203, 0x0000 },
{ 0x0204, 0x0000 },
{ 0x0205, 0x0000 },
{ 0x0206, 0x0000 },
{ 0x0207, 0x0000 },
{ 0x0208, 0x0000 },
{ 0x0210, 0x60b1 },
{ 0x0211, 0xa000 },
{ 0x0212, 0x024c },
{ 0x0213, 0xf7ff },
{ 0x0214, 0x024c },
{ 0x0215, 0x0102 },
{ 0x0216, 0x00a3 },
{ 0x0217, 0x0048 },
{ 0x0218, 0x92c0 },
{ 0x0219, 0x0000 },
{ 0x021a, 0x00c8 },
{ 0x021b, 0x0020 },
{ 0x02fa, 0x0000 },
{ 0x02fb, 0x0000 },
{ 0x02fc, 0x0000 },
{ 0x02ff, 0x0110 },
{ 0x0300, 0x001f },
{ 0x0301, 0x032c },
{ 0x0302, 0x5f21 },
{ 0x0303, 0x4000 },
{ 0x0304, 0x4000 },
{ 0x0305, 0x06d5 },
{ 0x0306, 0x8000 },
{ 0x0307, 0x0700 },
{ 0x0310, 0x4560 },
{ 0x0311, 0xa4a8 },
{ 0x0312, 0x7418 },
{ 0x0313, 0x0000 },
{ 0x0314, 0x0006 },
{ 0x0315, 0xffff },
{ 0x0316, 0xc400 },
{ 0x0317, 0x0000 },
{ 0x0330, 0x00a6 },
{ 0x0331, 0x04c3 },
{ 0x0332, 0x27c8 },
{ 0x0333, 0xbf50 },
{ 0x0334, 0x0045 },
{ 0x0335, 0x0007 },
{ 0x0336, 0x7418 },
{ 0x0337, 0x0501 },
{ 0x0338, 0x0000 },
{ 0x0339, 0x0010 },
{ 0x033a, 0x1010 },
{ 0x03c0, 0x7e00 },
{ 0x03c1, 0x8000 },
{ 0x03c2, 0x8000 },
{ 0x03c3, 0x8000 },
{ 0x03c4, 0x8000 },
{ 0x03c5, 0x8000 },
{ 0x03c6, 0x8000 },
{ 0x03c7, 0x8000 },
{ 0x03c8, 0x8000 },
{ 0x03c9, 0x8000 },
{ 0x03ca, 0x8000 },
{ 0x03cb, 0x8000 },
{ 0x03cc, 0x8000 },
{ 0x03d0, 0x0000 },
{ 0x03d1, 0x0000 },
{ 0x03d2, 0x0000 },
{ 0x03d3, 0x0000 },
{ 0x03d4, 0x2000 },
{ 0x03d5, 0x2000 },
{ 0x03d6, 0x0000 },
{ 0x03d7, 0x0000 },
{ 0x03d8, 0x2000 },
{ 0x03d9, 0x2000 },
{ 0x03da, 0x2000 },
{ 0x03db, 0x2000 },
{ 0x03dc, 0x0000 },
{ 0x03dd, 0x0000 },
{ 0x03de, 0x0000 },
{ 0x03df, 0x2000 },
{ 0x03e0, 0x0000 },
{ 0x03e1, 0x0000 },
{ 0x03e2, 0x0000 },
{ 0x03e3, 0x0000 },
{ 0x03e4, 0x0000 },
{ 0x03e5, 0x0000 },
{ 0x03e6, 0x0000 },
{ 0x03e7, 0x0000 },
{ 0x03e8, 0x0000 },
{ 0x03e9, 0x0000 },
{ 0x03ea, 0x0000 },
{ 0x03eb, 0x0000 },
{ 0x03ec, 0x0000 },
{ 0x03ed, 0x0000 },
{ 0x03ee, 0x0000 },
{ 0x03ef, 0x0000 },
{ 0x03f0, 0x0800 },
{ 0x03f1, 0x0800 },
{ 0x03f2, 0x0800 },
{ 0x03f3, 0x0800 },
{ 0x03fe, 0x0000 },
{ 0x03ff, 0x0000 },
{ 0x07f0, 0x0000 },
{ 0x07fa, 0x0000 },
};
static const struct reg_default rt5663_reg[] = {
{ 0x0000, 0x0000 },
{ 0x0002, 0x0008 },
{ 0x0005, 0x1000 },
{ 0x0006, 0x1000 },
{ 0x000a, 0x0000 },
{ 0x0010, 0x000f },
{ 0x0015, 0x42f1 },
{ 0x0016, 0x0000 },
{ 0x0018, 0x000b },
{ 0x0019, 0xafaf },
{ 0x001c, 0x2f2f },
{ 0x001f, 0x0000 },
{ 0x0022, 0x5757 },
{ 0x0023, 0x0039 },
{ 0x0026, 0xc0c0 },
{ 0x0029, 0x8080 },
{ 0x002a, 0x8020 },
{ 0x002c, 0x000c },
{ 0x002d, 0x0000 },
{ 0x0040, 0x0808 },
{ 0x0061, 0x0000 },
{ 0x0062, 0x0000 },
{ 0x0063, 0x003e },
{ 0x0064, 0x0000 },
{ 0x0065, 0x0000 },
{ 0x0066, 0x0000 },
{ 0x006b, 0x0000 },
{ 0x006e, 0x0000 },
{ 0x006f, 0x0000 },
{ 0x0070, 0x8020 },
{ 0x0073, 0x1000 },
{ 0x0074, 0xe400 },
{ 0x0075, 0x0002 },
{ 0x0076, 0x0001 },
{ 0x0077, 0x00f0 },
{ 0x0078, 0x0000 },
{ 0x0079, 0x0000 },
{ 0x007a, 0x0123 },
{ 0x007b, 0x8003 },
{ 0x0080, 0x0000 },
{ 0x0081, 0x0000 },
{ 0x0082, 0x0000 },
{ 0x0083, 0x0000 },
{ 0x0084, 0x0000 },
{ 0x0086, 0x0028 },
{ 0x0087, 0x0000 },
{ 0x008a, 0x0000 },
{ 0x008b, 0x0000 },
{ 0x008c, 0x0003 },
{ 0x008e, 0x0008 },
{ 0x008f, 0x1000 },
{ 0x0090, 0x0646 },
{ 0x0091, 0x0e3e },
{ 0x0092, 0x1071 },
{ 0x0093, 0x0000 },
{ 0x0094, 0x0080 },
{ 0x0097, 0x0000 },
{ 0x0098, 0x0000 },
{ 0x009a, 0x0000 },
{ 0x009f, 0x0000 },
{ 0x00ae, 0x6000 },
{ 0x00af, 0x0000 },
{ 0x00b6, 0x0000 },
{ 0x00b7, 0x0000 },
{ 0x00b8, 0x0000 },
{ 0x00ba, 0x0000 },
{ 0x00bb, 0x0000 },
{ 0x00be, 0x0000 },
{ 0x00bf, 0x0000 },
{ 0x00c0, 0x0000 },
{ 0x00c1, 0x0000 },
{ 0x00c5, 0x0000 },
{ 0x00cb, 0xa02f },
{ 0x00cc, 0x0000 },
{ 0x00cd, 0x0e02 },
{ 0x00d9, 0x08f9 },
{ 0x00db, 0x0008 },
{ 0x00dc, 0x00c0 },
{ 0x00dd, 0x6729 },
{ 0x00de, 0x3131 },
{ 0x00df, 0x0008 },
{ 0x00e0, 0x4000 },
{ 0x00e1, 0x3131 },
{ 0x00e2, 0x0043 },
{ 0x00e4, 0x400b },
{ 0x00e5, 0x8031 },
{ 0x00e6, 0x3080 },
{ 0x00e7, 0x4100 },
{ 0x00e8, 0x1400 },
{ 0x00e9, 0xe00a },
{ 0x00ea, 0x0404 },
{ 0x00eb, 0x0404 },
{ 0x00ec, 0xb320 },
{ 0x00ed, 0x0000 },
{ 0x00f4, 0x0000 },
{ 0x00f6, 0x0000 },
{ 0x00f8, 0x0000 },
{ 0x00fa, 0x8000 },
{ 0x00fd, 0x0001 },
{ 0x00fe, 0x10ec },
{ 0x00ff, 0x6406 },
{ 0x0100, 0xa020 },
{ 0x0108, 0x4444 },
{ 0x0109, 0x4444 },
{ 0x010a, 0xaaaa },
{ 0x010b, 0x00a0 },
{ 0x010c, 0x8aaa },
{ 0x010d, 0xaaaa },
{ 0x010e, 0x2aaa },
{ 0x010f, 0x002a },
{ 0x0110, 0xa0a4 },
{ 0x0111, 0x4602 },
{ 0x0112, 0x0101 },
{ 0x0113, 0x2000 },
{ 0x0114, 0x0000 },
{ 0x0116, 0x0000 },
{ 0x0117, 0x0f28 },
{ 0x0118, 0x0006 },
{ 0x0125, 0x2424 },
{ 0x0126, 0x5550 },
{ 0x0127, 0x0400 },
{ 0x0128, 0x7711 },
{ 0x0132, 0x0004 },
{ 0x0137, 0x5441 },
{ 0x0139, 0x79a1 },
{ 0x013a, 0x30c0 },
{ 0x013b, 0x2000 },
{ 0x013c, 0x2005 },
{ 0x013d, 0x30c0 },
{ 0x013e, 0x0000 },
{ 0x0140, 0x3700 },
{ 0x0141, 0x1f00 },
{ 0x0144, 0x0000 },
{ 0x0145, 0x0002 },
{ 0x0146, 0x0000 },
{ 0x0160, 0x0e80 },
{ 0x0161, 0x0080 },
{ 0x0162, 0x0200 },
{ 0x0163, 0x0800 },
{ 0x0164, 0x0000 },
{ 0x0165, 0x0000 },
{ 0x0166, 0x0000 },
{ 0x0167, 0x1417 },
{ 0x0168, 0x0017 },
{ 0x0169, 0x0017 },
{ 0x0180, 0x2000 },
{ 0x0181, 0x0000 },
{ 0x0182, 0x0000 },
{ 0x0183, 0x2000 },
{ 0x0184, 0x0000 },
{ 0x0185, 0x0000 },
{ 0x01b0, 0x4b30 },
{ 0x01b1, 0x0000 },
{ 0x01b2, 0xd870 },
{ 0x01b3, 0x0000 },
{ 0x01b4, 0x0030 },
{ 0x01b5, 0x5757 },
{ 0x01b6, 0x5757 },
{ 0x01b7, 0x5757 },
{ 0x01b8, 0x5757 },
{ 0x01c0, 0x433d },
{ 0x01c1, 0x0540 },
{ 0x01c2, 0x0000 },
{ 0x01c3, 0x0000 },
{ 0x01c4, 0x0000 },
{ 0x01c5, 0x0009 },
{ 0x01c6, 0x0018 },
{ 0x01c7, 0x002a },
{ 0x01c8, 0x004c },
{ 0x01c9, 0x0097 },
{ 0x01ca, 0x01c3 },
{ 0x01cb, 0x03e9 },
{ 0x01cc, 0x1389 },
{ 0x01cd, 0xc351 },
{ 0x01ce, 0x0000 },
{ 0x01cf, 0x0000 },
{ 0x01d0, 0x0000 },
{ 0x01d1, 0x0000 },
{ 0x01d2, 0x0000 },
{ 0x01d3, 0x003c },
{ 0x01d4, 0x5757 },
{ 0x01d5, 0x5757 },
{ 0x01d6, 0x5757 },
{ 0x01d7, 0x5757 },
{ 0x01d8, 0x5757 },
{ 0x01d9, 0x5757 },
{ 0x01da, 0x0000 },
{ 0x01db, 0x0000 },
{ 0x01dd, 0x0009 },
{ 0x01de, 0x7f00 },
{ 0x01df, 0x00c8 },
{ 0x01e0, 0x0691 },
{ 0x01e1, 0x0000 },
{ 0x01e2, 0x0000 },
{ 0x01e3, 0x0000 },
{ 0x01e4, 0x0000 },
{ 0x01e5, 0x0040 },
{ 0x01e6, 0x0000 },
{ 0x01e7, 0x0000 },
{ 0x01e8, 0x0000 },
{ 0x01ea, 0x0000 },
{ 0x01eb, 0x0000 },
{ 0x01ec, 0x0000 },
{ 0x01ed, 0x0000 },
{ 0x01ee, 0x0000 },
{ 0x01ef, 0x0000 },
{ 0x01f0, 0x0000 },
{ 0x01f1, 0x0000 },
{ 0x01f2, 0x0000 },
{ 0x0200, 0x0000 },
{ 0x0201, 0x2244 },
{ 0x0202, 0xaaaa },
{ 0x0250, 0x8010 },
{ 0x0251, 0x0000 },
{ 0x0252, 0x028a },
{ 0x02fa, 0x0000 },
{ 0x02fb, 0x8089 },
{ 0x02fc, 0x0300 },
{ 0x0300, 0x0000 },
{ 0x03d0, 0x0000 },
{ 0x03d1, 0x0000 },
{ 0x03d2, 0x0000 },
{ 0x03d3, 0x0000 },
{ 0x03d4, 0x2000 },
{ 0x03d5, 0x2000 },
{ 0x03d6, 0x0000 },
{ 0x03d7, 0x0000 },
{ 0x03d8, 0x2000 },
{ 0x03d9, 0x2000 },
{ 0x03da, 0x2000 },
{ 0x03db, 0x2000 },
{ 0x03dc, 0x0000 },
{ 0x03dd, 0x0000 },
{ 0x03de, 0x0000 },
{ 0x03df, 0x2000 },
{ 0x03e0, 0x0000 },
{ 0x03e1, 0x0000 },
{ 0x03e2, 0x0000 },
{ 0x03e3, 0x0000 },
{ 0x03e4, 0x0000 },
{ 0x03e5, 0x0000 },
{ 0x03e6, 0x0000 },
{ 0x03e7, 0x0000 },
{ 0x03e8, 0x0000 },
{ 0x03e9, 0x0000 },
{ 0x03ea, 0x0000 },
{ 0x03eb, 0x0000 },
{ 0x03ec, 0x0000 },
{ 0x03ed, 0x0000 },
{ 0x03ee, 0x0000 },
{ 0x03ef, 0x0000 },
{ 0x03f0, 0x0800 },
{ 0x03f1, 0x0800 },
{ 0x03f2, 0x0800 },
{ 0x03f3, 0x0800 },
};
static bool rt5663_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case RT5663_RESET:
case RT5663_SIL_DET_CTL:
case RT5663_HP_IMP_GAIN_2:
case RT5663_AD_DA_MIXER:
case RT5663_FRAC_DIV_2:
case RT5663_MICBIAS_1:
case RT5663_ASRC_11_2:
case RT5663_ADC_EQ_1:
case RT5663_INT_ST_1:
case RT5663_INT_ST_2:
case RT5663_GPIO_STA1:
case RT5663_SIN_GEN_1:
case RT5663_IL_CMD_1:
case RT5663_IL_CMD_5:
case RT5663_IL_CMD_PWRSAV1:
case RT5663_EM_JACK_TYPE_1:
case RT5663_EM_JACK_TYPE_2:
case RT5663_EM_JACK_TYPE_3:
case RT5663_JD_CTRL2:
case RT5663_VENDOR_ID:
case RT5663_VENDOR_ID_1:
case RT5663_VENDOR_ID_2:
case RT5663_PLL_INT_REG:
case RT5663_SOFT_RAMP:
case RT5663_STO_DRE_1:
case RT5663_STO_DRE_5:
case RT5663_STO_DRE_6:
case RT5663_STO_DRE_7:
case RT5663_MIC_DECRO_1:
case RT5663_MIC_DECRO_4:
case RT5663_HP_IMP_SEN_1:
case RT5663_HP_IMP_SEN_3:
case RT5663_HP_IMP_SEN_4:
case RT5663_HP_IMP_SEN_5:
case RT5663_HP_CALIB_1_1:
case RT5663_HP_CALIB_9:
case RT5663_HP_CALIB_ST1:
case RT5663_HP_CALIB_ST2:
case RT5663_HP_CALIB_ST3:
case RT5663_HP_CALIB_ST4:
case RT5663_HP_CALIB_ST5:
case RT5663_HP_CALIB_ST6:
case RT5663_HP_CALIB_ST7:
case RT5663_HP_CALIB_ST8:
case RT5663_HP_CALIB_ST9:
case RT5663_ANA_JD:
return true;
default:
return false;
}
}
static bool rt5663_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case RT5663_RESET:
case RT5663_HP_OUT_EN:
case RT5663_HP_LCH_DRE:
case RT5663_HP_RCH_DRE:
case RT5663_CALIB_BST:
case RT5663_RECMIX:
case RT5663_SIL_DET_CTL:
case RT5663_PWR_SAV_SILDET:
case RT5663_SIDETONE_CTL:
case RT5663_STO1_DAC_DIG_VOL:
case RT5663_STO1_ADC_DIG_VOL:
case RT5663_STO1_BOOST:
case RT5663_HP_IMP_GAIN_1:
case RT5663_HP_IMP_GAIN_2:
case RT5663_STO1_ADC_MIXER:
case RT5663_AD_DA_MIXER:
case RT5663_STO_DAC_MIXER:
case RT5663_DIG_SIDE_MIXER:
case RT5663_BYPASS_STO_DAC:
case RT5663_CALIB_REC_MIX:
case RT5663_PWR_DIG_1:
case RT5663_PWR_DIG_2:
case RT5663_PWR_ANLG_1:
case RT5663_PWR_ANLG_2:
case RT5663_PWR_ANLG_3:
case RT5663_PWR_MIXER:
case RT5663_SIG_CLK_DET:
case RT5663_PRE_DIV_GATING_1:
case RT5663_PRE_DIV_GATING_2:
case RT5663_I2S1_SDP:
case RT5663_ADDA_CLK_1:
case RT5663_ADDA_RST:
case RT5663_FRAC_DIV_1:
case RT5663_FRAC_DIV_2:
case RT5663_TDM_1:
case RT5663_TDM_2:
case RT5663_TDM_3:
case RT5663_TDM_4:
case RT5663_TDM_5:
case RT5663_GLB_CLK:
case RT5663_PLL_1:
case RT5663_PLL_2:
case RT5663_ASRC_1:
case RT5663_ASRC_2:
case RT5663_ASRC_4:
case RT5663_DUMMY_REG:
case RT5663_ASRC_8:
case RT5663_ASRC_9:
case RT5663_ASRC_11:
case RT5663_DEPOP_1:
case RT5663_DEPOP_2:
case RT5663_DEPOP_3:
case RT5663_HP_CHARGE_PUMP_1:
case RT5663_HP_CHARGE_PUMP_2:
case RT5663_MICBIAS_1:
case RT5663_RC_CLK:
case RT5663_ASRC_11_2:
case RT5663_DUMMY_REG_2:
case RT5663_REC_PATH_GAIN:
case RT5663_AUTO_1MRC_CLK:
case RT5663_ADC_EQ_1:
case RT5663_ADC_EQ_2:
case RT5663_IRQ_1:
case RT5663_IRQ_2:
case RT5663_IRQ_3:
case RT5663_IRQ_4:
case RT5663_IRQ_5:
case RT5663_INT_ST_1:
case RT5663_INT_ST_2:
case RT5663_GPIO_1:
case RT5663_GPIO_2:
case RT5663_GPIO_STA1:
case RT5663_SIN_GEN_1:
case RT5663_SIN_GEN_2:
case RT5663_SIN_GEN_3:
case RT5663_SOF_VOL_ZC1:
case RT5663_IL_CMD_1:
case RT5663_IL_CMD_2:
case RT5663_IL_CMD_3:
case RT5663_IL_CMD_4:
case RT5663_IL_CMD_5:
case RT5663_IL_CMD_6:
case RT5663_IL_CMD_7:
case RT5663_IL_CMD_8:
case RT5663_IL_CMD_PWRSAV1:
case RT5663_IL_CMD_PWRSAV2:
case RT5663_EM_JACK_TYPE_1:
case RT5663_EM_JACK_TYPE_2:
case RT5663_EM_JACK_TYPE_3:
case RT5663_EM_JACK_TYPE_4:
case RT5663_EM_JACK_TYPE_5:
case RT5663_EM_JACK_TYPE_6:
case RT5663_STO1_HPF_ADJ1:
case RT5663_STO1_HPF_ADJ2:
case RT5663_FAST_OFF_MICBIAS:
case RT5663_JD_CTRL1:
case RT5663_JD_CTRL2:
case RT5663_DIG_MISC:
case RT5663_VENDOR_ID:
case RT5663_VENDOR_ID_1:
case RT5663_VENDOR_ID_2:
case RT5663_DIG_VOL_ZCD:
case RT5663_ANA_BIAS_CUR_1:
case RT5663_ANA_BIAS_CUR_2:
case RT5663_ANA_BIAS_CUR_3:
case RT5663_ANA_BIAS_CUR_4:
case RT5663_ANA_BIAS_CUR_5:
case RT5663_ANA_BIAS_CUR_6:
case RT5663_BIAS_CUR_5:
case RT5663_BIAS_CUR_6:
case RT5663_BIAS_CUR_7:
case RT5663_BIAS_CUR_8:
case RT5663_DACREF_LDO:
case RT5663_DUMMY_REG_3:
case RT5663_BIAS_CUR_9:
case RT5663_DUMMY_REG_4:
case RT5663_VREFADJ_OP:
case RT5663_VREF_RECMIX:
case RT5663_CHARGE_PUMP_1:
case RT5663_CHARGE_PUMP_1_2:
case RT5663_CHARGE_PUMP_1_3:
case RT5663_CHARGE_PUMP_2:
case RT5663_DIG_IN_PIN1:
case RT5663_PAD_DRV_CTL:
case RT5663_PLL_INT_REG:
case RT5663_CHOP_DAC_L:
case RT5663_CHOP_ADC:
case RT5663_CALIB_ADC:
case RT5663_CHOP_DAC_R:
case RT5663_DUMMY_CTL_DACLR:
case RT5663_DUMMY_REG_5:
case RT5663_SOFT_RAMP:
case RT5663_TEST_MODE_1:
case RT5663_TEST_MODE_2:
case RT5663_TEST_MODE_3:
case RT5663_STO_DRE_1:
case RT5663_STO_DRE_2:
case RT5663_STO_DRE_3:
case RT5663_STO_DRE_4:
case RT5663_STO_DRE_5:
case RT5663_STO_DRE_6:
case RT5663_STO_DRE_7:
case RT5663_STO_DRE_8:
case RT5663_STO_DRE_9:
case RT5663_STO_DRE_10:
case RT5663_MIC_DECRO_1:
case RT5663_MIC_DECRO_2:
case RT5663_MIC_DECRO_3:
case RT5663_MIC_DECRO_4:
case RT5663_MIC_DECRO_5:
case RT5663_MIC_DECRO_6:
case RT5663_HP_DECRO_1:
case RT5663_HP_DECRO_2:
case RT5663_HP_DECRO_3:
case RT5663_HP_DECRO_4:
case RT5663_HP_DECOUP:
case RT5663_HP_IMP_SEN_MAP8:
case RT5663_HP_IMP_SEN_MAP9:
case RT5663_HP_IMP_SEN_MAP10:
case RT5663_HP_IMP_SEN_MAP11:
case RT5663_HP_IMP_SEN_1:
case RT5663_HP_IMP_SEN_2:
case RT5663_HP_IMP_SEN_3:
case RT5663_HP_IMP_SEN_4:
case RT5663_HP_IMP_SEN_5:
case RT5663_HP_IMP_SEN_6:
case RT5663_HP_IMP_SEN_7:
case RT5663_HP_IMP_SEN_8:
case RT5663_HP_IMP_SEN_9:
case RT5663_HP_IMP_SEN_10:
case RT5663_HP_IMP_SEN_11:
case RT5663_HP_IMP_SEN_12:
case RT5663_HP_IMP_SEN_13:
case RT5663_HP_IMP_SEN_14:
case RT5663_HP_IMP_SEN_15:
case RT5663_HP_IMP_SEN_16:
case RT5663_HP_IMP_SEN_17:
case RT5663_HP_IMP_SEN_18:
case RT5663_HP_IMP_SEN_19:
case RT5663_HP_IMPSEN_DIG5:
case RT5663_HP_IMPSEN_MAP1:
case RT5663_HP_IMPSEN_MAP2:
case RT5663_HP_IMPSEN_MAP3:
case RT5663_HP_IMPSEN_MAP4:
case RT5663_HP_IMPSEN_MAP5:
case RT5663_HP_IMPSEN_MAP7:
case RT5663_HP_LOGIC_1:
case RT5663_HP_LOGIC_2:
case RT5663_HP_CALIB_1:
case RT5663_HP_CALIB_1_1:
case RT5663_HP_CALIB_2:
case RT5663_HP_CALIB_3:
case RT5663_HP_CALIB_4:
case RT5663_HP_CALIB_5:
case RT5663_HP_CALIB_5_1:
case RT5663_HP_CALIB_6:
case RT5663_HP_CALIB_7:
case RT5663_HP_CALIB_9:
case RT5663_HP_CALIB_10:
case RT5663_HP_CALIB_11:
case RT5663_HP_CALIB_ST1:
case RT5663_HP_CALIB_ST2:
case RT5663_HP_CALIB_ST3:
case RT5663_HP_CALIB_ST4:
case RT5663_HP_CALIB_ST5:
case RT5663_HP_CALIB_ST6:
case RT5663_HP_CALIB_ST7:
case RT5663_HP_CALIB_ST8:
case RT5663_HP_CALIB_ST9:
case RT5663_HP_AMP_DET:
case RT5663_DUMMY_REG_6:
case RT5663_HP_BIAS:
case RT5663_CBJ_1:
case RT5663_CBJ_2:
case RT5663_CBJ_3:
case RT5663_DUMMY_1:
case RT5663_DUMMY_2:
case RT5663_DUMMY_3:
case RT5663_ANA_JD:
case RT5663_ADC_LCH_LPF1_A1:
case RT5663_ADC_RCH_LPF1_A1:
case RT5663_ADC_LCH_LPF1_H0:
case RT5663_ADC_RCH_LPF1_H0:
case RT5663_ADC_LCH_BPF1_A1:
case RT5663_ADC_RCH_BPF1_A1:
case RT5663_ADC_LCH_BPF1_A2:
case RT5663_ADC_RCH_BPF1_A2:
case RT5663_ADC_LCH_BPF1_H0:
case RT5663_ADC_RCH_BPF1_H0:
case RT5663_ADC_LCH_BPF2_A1:
case RT5663_ADC_RCH_BPF2_A1:
case RT5663_ADC_LCH_BPF2_A2:
case RT5663_ADC_RCH_BPF2_A2:
case RT5663_ADC_LCH_BPF2_H0:
case RT5663_ADC_RCH_BPF2_H0:
case RT5663_ADC_LCH_BPF3_A1:
case RT5663_ADC_RCH_BPF3_A1:
case RT5663_ADC_LCH_BPF3_A2:
case RT5663_ADC_RCH_BPF3_A2:
case RT5663_ADC_LCH_BPF3_H0:
case RT5663_ADC_RCH_BPF3_H0:
case RT5663_ADC_LCH_BPF4_A1:
case RT5663_ADC_RCH_BPF4_A1:
case RT5663_ADC_LCH_BPF4_A2:
case RT5663_ADC_RCH_BPF4_A2:
case RT5663_ADC_LCH_BPF4_H0:
case RT5663_ADC_RCH_BPF4_H0:
case RT5663_ADC_LCH_HPF1_A1:
case RT5663_ADC_RCH_HPF1_A1:
case RT5663_ADC_LCH_HPF1_H0:
case RT5663_ADC_RCH_HPF1_H0:
case RT5663_ADC_EQ_PRE_VOL_L:
case RT5663_ADC_EQ_PRE_VOL_R:
case RT5663_ADC_EQ_POST_VOL_L:
case RT5663_ADC_EQ_POST_VOL_R:
return true;
default:
return false;
}
}
static bool rt5663_v2_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case RT5663_RESET:
case RT5663_CBJ_TYPE_2:
case RT5663_PDM_OUT_CTL:
case RT5663_PDM_I2C_DATA_CTL1:
case RT5663_PDM_I2C_DATA_CTL4:
case RT5663_ALC_BK_GAIN:
case RT5663_PLL_2:
case RT5663_MICBIAS_1:
case RT5663_ADC_EQ_1:
case RT5663_INT_ST_1:
case RT5663_GPIO_STA2:
case RT5663_IL_CMD_1:
case RT5663_IL_CMD_5:
case RT5663_A_JD_CTRL:
case RT5663_JD_CTRL2:
case RT5663_VENDOR_ID:
case RT5663_VENDOR_ID_1:
case RT5663_VENDOR_ID_2:
case RT5663_STO_DRE_1:
case RT5663_STO_DRE_5:
case RT5663_STO_DRE_6:
case RT5663_STO_DRE_7:
case RT5663_MONO_DYNA_6:
case RT5663_STO1_SIL_DET:
case RT5663_MONOL_SIL_DET:
case RT5663_MONOR_SIL_DET:
case RT5663_STO2_DAC_SIL:
case RT5663_MONO_AMP_CAL_ST1:
case RT5663_MONO_AMP_CAL_ST2:
case RT5663_MONO_AMP_CAL_ST3:
case RT5663_MONO_AMP_CAL_ST4:
case RT5663_HP_IMP_SEN_2:
case RT5663_HP_IMP_SEN_3:
case RT5663_HP_IMP_SEN_4:
case RT5663_HP_IMP_SEN_10:
case RT5663_HP_CALIB_1:
case RT5663_HP_CALIB_10:
case RT5663_HP_CALIB_ST1:
case RT5663_HP_CALIB_ST4:
case RT5663_HP_CALIB_ST5:
case RT5663_HP_CALIB_ST6:
case RT5663_HP_CALIB_ST7:
case RT5663_HP_CALIB_ST8:
case RT5663_HP_CALIB_ST9:
case RT5663_HP_CALIB_ST10:
case RT5663_HP_CALIB_ST11:
return true;
default:
return false;
}
}
static bool rt5663_v2_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case RT5663_LOUT_CTRL:
case RT5663_HP_AMP_2:
case RT5663_MONO_OUT:
case RT5663_MONO_GAIN:
case RT5663_AEC_BST:
case RT5663_IN1_IN2:
case RT5663_IN3_IN4:
case RT5663_INL1_INR1:
case RT5663_CBJ_TYPE_2:
case RT5663_CBJ_TYPE_3:
case RT5663_CBJ_TYPE_4:
case RT5663_CBJ_TYPE_5:
case RT5663_CBJ_TYPE_8:
case RT5663_DAC3_DIG_VOL:
case RT5663_DAC3_CTRL:
case RT5663_MONO_ADC_DIG_VOL:
case RT5663_STO2_ADC_DIG_VOL:
case RT5663_MONO_ADC_BST_GAIN:
case RT5663_STO2_ADC_BST_GAIN:
case RT5663_SIDETONE_CTRL:
case RT5663_MONO1_ADC_MIXER:
case RT5663_STO2_ADC_MIXER:
case RT5663_MONO_DAC_MIXER:
case RT5663_DAC2_SRC_CTRL:
case RT5663_IF_3_4_DATA_CTL:
case RT5663_IF_5_DATA_CTL:
case RT5663_PDM_OUT_CTL:
case RT5663_PDM_I2C_DATA_CTL1:
case RT5663_PDM_I2C_DATA_CTL2:
case RT5663_PDM_I2C_DATA_CTL3:
case RT5663_PDM_I2C_DATA_CTL4:
case RT5663_RECMIX1_NEW:
case RT5663_RECMIX1L_0:
case RT5663_RECMIX1L:
case RT5663_RECMIX1R_0:
case RT5663_RECMIX1R:
case RT5663_RECMIX2_NEW:
case RT5663_RECMIX2_L_2:
case RT5663_RECMIX2_R:
case RT5663_RECMIX2_R_2:
case RT5663_CALIB_REC_LR:
case RT5663_ALC_BK_GAIN:
case RT5663_MONOMIX_GAIN:
case RT5663_MONOMIX_IN_GAIN:
case RT5663_OUT_MIXL_GAIN:
case RT5663_OUT_LMIX_IN_GAIN:
case RT5663_OUT_RMIX_IN_GAIN:
case RT5663_OUT_RMIX_IN_GAIN1:
case RT5663_LOUT_MIXER_CTRL:
case RT5663_PWR_VOL:
case RT5663_ADCDAC_RST:
case RT5663_I2S34_SDP:
case RT5663_I2S5_SDP:
case RT5663_TDM_6:
case RT5663_TDM_7:
case RT5663_TDM_8:
case RT5663_TDM_9:
case RT5663_ASRC_3:
case RT5663_ASRC_6:
case RT5663_ASRC_7:
case RT5663_PLL_TRK_13:
case RT5663_I2S_M_CLK_CTL:
case RT5663_FDIV_I2S34_M_CLK:
case RT5663_FDIV_I2S34_M_CLK2:
case RT5663_FDIV_I2S5_M_CLK:
case RT5663_FDIV_I2S5_M_CLK2:
case RT5663_V2_IRQ_4:
case RT5663_GPIO_3:
case RT5663_GPIO_4:
case RT5663_GPIO_STA2:
case RT5663_HP_AMP_DET1:
case RT5663_HP_AMP_DET2:
case RT5663_HP_AMP_DET3:
case RT5663_MID_BD_HP_AMP:
case RT5663_LOW_BD_HP_AMP:
case RT5663_SOF_VOL_ZC2:
case RT5663_ADC_STO2_ADJ1:
case RT5663_ADC_STO2_ADJ2:
case RT5663_A_JD_CTRL:
case RT5663_JD1_TRES_CTRL:
case RT5663_JD2_TRES_CTRL:
case RT5663_V2_JD_CTRL2:
case RT5663_DUM_REG_2:
case RT5663_DUM_REG_3:
case RT5663_VENDOR_ID:
case RT5663_VENDOR_ID_1:
case RT5663_VENDOR_ID_2:
case RT5663_DACADC_DIG_VOL2:
case RT5663_DIG_IN_PIN2:
case RT5663_PAD_DRV_CTL1:
case RT5663_SOF_RAM_DEPOP:
case RT5663_VOL_TEST:
case RT5663_TEST_MODE_4:
case RT5663_TEST_MODE_5:
case RT5663_STO_DRE_9:
case RT5663_MONO_DYNA_1:
case RT5663_MONO_DYNA_2:
case RT5663_MONO_DYNA_3:
case RT5663_MONO_DYNA_4:
case RT5663_MONO_DYNA_5:
case RT5663_MONO_DYNA_6:
case RT5663_STO1_SIL_DET:
case RT5663_MONOL_SIL_DET:
case RT5663_MONOR_SIL_DET:
case RT5663_STO2_DAC_SIL:
case RT5663_PWR_SAV_CTL1:
case RT5663_PWR_SAV_CTL2:
case RT5663_PWR_SAV_CTL3:
case RT5663_PWR_SAV_CTL4:
case RT5663_PWR_SAV_CTL5:
case RT5663_PWR_SAV_CTL6:
case RT5663_MONO_AMP_CAL1:
case RT5663_MONO_AMP_CAL2:
case RT5663_MONO_AMP_CAL3:
case RT5663_MONO_AMP_CAL4:
case RT5663_MONO_AMP_CAL5:
case RT5663_MONO_AMP_CAL6:
case RT5663_MONO_AMP_CAL7:
case RT5663_MONO_AMP_CAL_ST1:
case RT5663_MONO_AMP_CAL_ST2:
case RT5663_MONO_AMP_CAL_ST3:
case RT5663_MONO_AMP_CAL_ST4:
case RT5663_MONO_AMP_CAL_ST5:
case RT5663_V2_HP_IMP_SEN_13:
case RT5663_V2_HP_IMP_SEN_14:
case RT5663_V2_HP_IMP_SEN_6:
case RT5663_V2_HP_IMP_SEN_7:
case RT5663_V2_HP_IMP_SEN_8:
case RT5663_V2_HP_IMP_SEN_9:
case RT5663_V2_HP_IMP_SEN_10:
case RT5663_HP_LOGIC_3:
case RT5663_HP_CALIB_ST10:
case RT5663_HP_CALIB_ST11:
case RT5663_PRO_REG_TBL_4:
case RT5663_PRO_REG_TBL_5:
case RT5663_PRO_REG_TBL_6:
case RT5663_PRO_REG_TBL_7:
case RT5663_PRO_REG_TBL_8:
case RT5663_PRO_REG_TBL_9:
case RT5663_SAR_ADC_INL_1:
case RT5663_SAR_ADC_INL_2:
case RT5663_SAR_ADC_INL_3:
case RT5663_SAR_ADC_INL_4:
case RT5663_SAR_ADC_INL_5:
case RT5663_SAR_ADC_INL_6:
case RT5663_SAR_ADC_INL_7:
case RT5663_SAR_ADC_INL_8:
case RT5663_SAR_ADC_INL_9:
case RT5663_SAR_ADC_INL_10:
case RT5663_SAR_ADC_INL_11:
case RT5663_SAR_ADC_INL_12:
case RT5663_DRC_CTRL_1:
case RT5663_DRC1_CTRL_2:
case RT5663_DRC1_CTRL_3:
case RT5663_DRC1_CTRL_4:
case RT5663_DRC1_CTRL_5:
case RT5663_DRC1_CTRL_6:
case RT5663_DRC1_HD_CTRL_1:
case RT5663_DRC1_HD_CTRL_2:
case RT5663_DRC1_PRI_REG_1:
case RT5663_DRC1_PRI_REG_2:
case RT5663_DRC1_PRI_REG_3:
case RT5663_DRC1_PRI_REG_4:
case RT5663_DRC1_PRI_REG_5:
case RT5663_DRC1_PRI_REG_6:
case RT5663_DRC1_PRI_REG_7:
case RT5663_DRC1_PRI_REG_8:
case RT5663_ALC_PGA_CTL_1:
case RT5663_ALC_PGA_CTL_2:
case RT5663_ALC_PGA_CTL_3:
case RT5663_ALC_PGA_CTL_4:
case RT5663_ALC_PGA_CTL_5:
case RT5663_ALC_PGA_CTL_6:
case RT5663_ALC_PGA_CTL_7:
case RT5663_ALC_PGA_CTL_8:
case RT5663_ALC_PGA_REG_1:
case RT5663_ALC_PGA_REG_2:
case RT5663_ALC_PGA_REG_3:
case RT5663_ADC_EQ_RECOV_1:
case RT5663_ADC_EQ_RECOV_2:
case RT5663_ADC_EQ_RECOV_3:
case RT5663_ADC_EQ_RECOV_4:
case RT5663_ADC_EQ_RECOV_5:
case RT5663_ADC_EQ_RECOV_6:
case RT5663_ADC_EQ_RECOV_7:
case RT5663_ADC_EQ_RECOV_8:
case RT5663_ADC_EQ_RECOV_9:
case RT5663_ADC_EQ_RECOV_10:
case RT5663_ADC_EQ_RECOV_11:
case RT5663_ADC_EQ_RECOV_12:
case RT5663_ADC_EQ_RECOV_13:
case RT5663_VID_HIDDEN:
case RT5663_VID_CUSTOMER:
case RT5663_SCAN_MODE:
case RT5663_I2C_BYPA:
return true;
case RT5663_TDM_1:
case RT5663_DEPOP_3:
case RT5663_ASRC_11_2:
case RT5663_INT_ST_2:
case RT5663_GPIO_STA1:
case RT5663_SIN_GEN_1:
case RT5663_SIN_GEN_2:
case RT5663_SIN_GEN_3:
case RT5663_IL_CMD_PWRSAV1:
case RT5663_IL_CMD_PWRSAV2:
case RT5663_EM_JACK_TYPE_1:
case RT5663_EM_JACK_TYPE_2:
case RT5663_EM_JACK_TYPE_3:
case RT5663_EM_JACK_TYPE_4:
case RT5663_FAST_OFF_MICBIAS:
case RT5663_ANA_BIAS_CUR_1:
case RT5663_ANA_BIAS_CUR_2:
case RT5663_BIAS_CUR_9:
case RT5663_DUMMY_REG_4:
case RT5663_VREF_RECMIX:
case RT5663_CHARGE_PUMP_1_2:
case RT5663_CHARGE_PUMP_1_3:
case RT5663_CHARGE_PUMP_2:
case RT5663_CHOP_DAC_R:
case RT5663_DUMMY_CTL_DACLR:
case RT5663_DUMMY_REG_5:
case RT5663_SOFT_RAMP:
case RT5663_TEST_MODE_1:
case RT5663_STO_DRE_10:
case RT5663_MIC_DECRO_1:
case RT5663_MIC_DECRO_2:
case RT5663_MIC_DECRO_3:
case RT5663_MIC_DECRO_4:
case RT5663_MIC_DECRO_5:
case RT5663_MIC_DECRO_6:
case RT5663_HP_DECRO_1:
case RT5663_HP_DECRO_2:
case RT5663_HP_DECRO_3:
case RT5663_HP_DECRO_4:
case RT5663_HP_DECOUP:
case RT5663_HP_IMPSEN_MAP4:
case RT5663_HP_IMPSEN_MAP5:
case RT5663_HP_IMPSEN_MAP7:
case RT5663_HP_CALIB_1:
case RT5663_CBJ_1:
case RT5663_CBJ_2:
case RT5663_CBJ_3:
return false;
default:
return rt5663_readable_register(dev, reg);
}
}
static const DECLARE_TLV_DB_SCALE(rt5663_hp_vol_tlv, -2400, 150, 0);
static const DECLARE_TLV_DB_SCALE(rt5663_v2_hp_vol_tlv, -2250, 150, 0);
static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
static const DECLARE_TLV_DB_RANGE(in_bst_tlv,
0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
);
/* Interface data select */
static const char * const rt5663_if1_adc_data_select[] = {
"L/R", "R/L", "L/L", "R/R"
};
static SOC_ENUM_SINGLE_DECL(rt5663_if1_adc_enum, RT5663_TDM_2,
RT5663_DATA_SWAP_ADCDAT1_SHIFT, rt5663_if1_adc_data_select);
static void rt5663_enable_push_button_irq(struct snd_soc_component *component,
bool enable)
{
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
if (enable) {
snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_EN);
/* reset in-line command */
snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
RT5663_RESET_4BTN_INL_MASK,
RT5663_RESET_4BTN_INL_RESET);
snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
RT5663_RESET_4BTN_INL_MASK,
RT5663_RESET_4BTN_INL_NOR);
switch (rt5663->codec_ver) {
case CODEC_VER_1:
snd_soc_component_update_bits(component, RT5663_IRQ_3,
RT5663_V2_EN_IRQ_INLINE_MASK,
RT5663_V2_EN_IRQ_INLINE_NOR);
break;
case CODEC_VER_0:
snd_soc_component_update_bits(component, RT5663_IRQ_2,
RT5663_EN_IRQ_INLINE_MASK,
RT5663_EN_IRQ_INLINE_NOR);
break;
default:
dev_err(component->dev, "Unknown CODEC Version\n");
}
} else {
switch (rt5663->codec_ver) {
case CODEC_VER_1:
snd_soc_component_update_bits(component, RT5663_IRQ_3,
RT5663_V2_EN_IRQ_INLINE_MASK,
RT5663_V2_EN_IRQ_INLINE_BYP);
break;
case CODEC_VER_0:
snd_soc_component_update_bits(component, RT5663_IRQ_2,
RT5663_EN_IRQ_INLINE_MASK,
RT5663_EN_IRQ_INLINE_BYP);
break;
default:
dev_err(component->dev, "Unknown CODEC Version\n");
}
snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_DIS);
/* reset in-line command */
snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
RT5663_RESET_4BTN_INL_MASK,
RT5663_RESET_4BTN_INL_RESET);
snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
RT5663_RESET_4BTN_INL_MASK,
RT5663_RESET_4BTN_INL_NOR);
}
}
/**
* rt5663_v2_jack_detect - Detect headset.
* @component: SoC audio component device.
* @jack_insert: Jack insert or not.
*
* Detect whether is headset or not when jack inserted.
*
* Returns detect status.
*/
static int rt5663_v2_jack_detect(struct snd_soc_component *component, int jack_insert)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30};
dev_dbg(component->dev, "%s jack_insert:%d\n", __func__, jack_insert);
if (jack_insert) {
snd_soc_component_write(component, RT5663_CBJ_TYPE_2, 0x8040);
snd_soc_component_write(component, RT5663_CBJ_TYPE_3, 0x1484);
snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2");
snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power");
snd_soc_dapm_force_enable_pin(dapm, "CBJ Power");
snd_soc_dapm_sync(dapm);
snd_soc_component_update_bits(component, RT5663_RC_CLK,
RT5663_DIG_1M_CLK_MASK, RT5663_DIG_1M_CLK_EN);
snd_soc_component_update_bits(component, RT5663_RECMIX, 0x8, 0x8);
while (i < 5) {
msleep(sleep_time[i]);
val = snd_soc_component_read(component, RT5663_CBJ_TYPE_2) & 0x0003;
if (val == 0x1 || val == 0x2 || val == 0x3)
break;
dev_dbg(component->dev, "%s: MX-0011 val=%x sleep %d\n",
__func__, val, sleep_time[i]);
i++;
}
dev_dbg(component->dev, "%s val = %d\n", __func__, val);
switch (val) {
case 1:
case 2:
rt5663->jack_type = SND_JACK_HEADSET;
rt5663_enable_push_button_irq(component, true);
break;
default:
snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
snd_soc_dapm_disable_pin(dapm, "CBJ Power");
snd_soc_dapm_sync(dapm);
rt5663->jack_type = SND_JACK_HEADPHONE;
break;
}
} else {
snd_soc_component_update_bits(component, RT5663_RECMIX, 0x8, 0x0);
if (rt5663->jack_type == SND_JACK_HEADSET) {
rt5663_enable_push_button_irq(component, false);
snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
snd_soc_dapm_disable_pin(dapm, "CBJ Power");
snd_soc_dapm_sync(dapm);
}
rt5663->jack_type = 0;
}
dev_dbg(component->dev, "jack_type = %d\n", rt5663->jack_type);
return rt5663->jack_type;
}
/**
* rt5663_jack_detect - Detect headset.
* @component: SoC audio component device.
* @jack_insert: Jack insert or not.
*
* Detect whether is headset or not when jack inserted.
*
* Returns detect status.
*/
static int rt5663_jack_detect(struct snd_soc_component *component, int jack_insert)
{
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
int val, i = 0;
dev_dbg(component->dev, "%s jack_insert:%d\n", __func__, jack_insert);
if (jack_insert) {
snd_soc_component_update_bits(component, RT5663_DIG_MISC,
RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
RT5663_SI_HP_MASK | RT5663_OSW_HP_L_MASK |
RT5663_OSW_HP_R_MASK, RT5663_SI_HP_EN |
RT5663_OSW_HP_L_DIS | RT5663_OSW_HP_R_DIS);
snd_soc_component_update_bits(component, RT5663_DUMMY_1,
RT5663_EMB_CLK_MASK | RT5663_HPA_CPL_BIAS_MASK |
RT5663_HPA_CPR_BIAS_MASK, RT5663_EMB_CLK_EN |
RT5663_HPA_CPL_BIAS_1 | RT5663_HPA_CPR_BIAS_1);
snd_soc_component_update_bits(component, RT5663_CBJ_1,
RT5663_INBUF_CBJ_BST1_MASK | RT5663_CBJ_SENSE_BST1_MASK,
RT5663_INBUF_CBJ_BST1_ON | RT5663_CBJ_SENSE_BST1_L);
snd_soc_component_update_bits(component, RT5663_IL_CMD_2,
RT5663_PWR_MIC_DET_MASK, RT5663_PWR_MIC_DET_ON);
/* BST1 power on for JD */
snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
RT5663_PWR_BST1_MASK, RT5663_PWR_BST1_ON);
snd_soc_component_update_bits(component, RT5663_EM_JACK_TYPE_1,
RT5663_CBJ_DET_MASK | RT5663_EXT_JD_MASK |
RT5663_POL_EXT_JD_MASK, RT5663_CBJ_DET_EN |
RT5663_EXT_JD_EN | RT5663_POL_EXT_JD_EN);
snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
RT5663_PWR_MB_MASK | RT5663_LDO1_DVO_MASK |
RT5663_AMP_HP_MASK, RT5663_PWR_MB |
RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
RT5663_PWR_VREF1 | RT5663_PWR_VREF2);
msleep(20);
snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
RT5663_PWR_FV1 | RT5663_PWR_FV2);
snd_soc_component_update_bits(component, RT5663_AUTO_1MRC_CLK,
RT5663_IRQ_POW_SAV_MASK, RT5663_IRQ_POW_SAV_EN);
snd_soc_component_update_bits(component, RT5663_IRQ_1,
RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
snd_soc_component_update_bits(component, RT5663_EM_JACK_TYPE_1,
RT5663_EM_JD_MASK, RT5663_EM_JD_RST);
snd_soc_component_update_bits(component, RT5663_EM_JACK_TYPE_1,
RT5663_EM_JD_MASK, RT5663_EM_JD_NOR);
while (true) {
regmap_read(rt5663->regmap, RT5663_INT_ST_2, &val);
if (!(val & 0x80))
usleep_range(10000, 10005);
else
break;
if (i > 200)
break;
i++;
}
val = snd_soc_component_read(component, RT5663_EM_JACK_TYPE_2) & 0x0003;
dev_dbg(component->dev, "%s val = %d\n", __func__, val);
snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
RT5663_OSW_HP_L_MASK | RT5663_OSW_HP_R_MASK,
RT5663_OSW_HP_L_EN | RT5663_OSW_HP_R_EN);
switch (val) {
case 1:
case 2:
rt5663->jack_type = SND_JACK_HEADSET;
rt5663_enable_push_button_irq(component, true);
if (rt5663->pdata.impedance_sensing_num)
break;
if (rt5663->pdata.dc_offset_l_manual_mic) {
regmap_write(rt5663->regmap, RT5663_MIC_DECRO_2,
rt5663->pdata.dc_offset_l_manual_mic >>
16);
regmap_write(rt5663->regmap, RT5663_MIC_DECRO_3,
rt5663->pdata.dc_offset_l_manual_mic &
0xffff);
}
if (rt5663->pdata.dc_offset_r_manual_mic) {
regmap_write(rt5663->regmap, RT5663_MIC_DECRO_5,
rt5663->pdata.dc_offset_r_manual_mic >>
16);
regmap_write(rt5663->regmap, RT5663_MIC_DECRO_6,
rt5663->pdata.dc_offset_r_manual_mic &
0xffff);
}
break;
default:
rt5663->jack_type = SND_JACK_HEADPHONE;
snd_soc_component_update_bits(component,
RT5663_PWR_ANLG_1,
RT5663_PWR_MB_MASK | RT5663_PWR_VREF1_MASK |
RT5663_PWR_VREF2_MASK, 0);
if (rt5663->pdata.impedance_sensing_num)
break;
if (rt5663->pdata.dc_offset_l_manual) {
regmap_write(rt5663->regmap, RT5663_MIC_DECRO_2,
rt5663->pdata.dc_offset_l_manual >> 16);
regmap_write(rt5663->regmap, RT5663_MIC_DECRO_3,
rt5663->pdata.dc_offset_l_manual &
0xffff);
}
if (rt5663->pdata.dc_offset_r_manual) {
regmap_write(rt5663->regmap, RT5663_MIC_DECRO_5,
rt5663->pdata.dc_offset_r_manual >> 16);
regmap_write(rt5663->regmap, RT5663_MIC_DECRO_6,
rt5663->pdata.dc_offset_r_manual &
0xffff);
}
break;
}
} else {
if (rt5663->jack_type == SND_JACK_HEADSET)
rt5663_enable_push_button_irq(component, false);
rt5663->jack_type = 0;
snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
RT5663_PWR_MB_MASK | RT5663_PWR_VREF1_MASK |
RT5663_PWR_VREF2_MASK, 0);
}
dev_dbg(component->dev, "jack_type = %d\n", rt5663->jack_type);
return rt5663->jack_type;
}
static int rt5663_impedance_sensing(struct snd_soc_component *component)
{
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
unsigned int value, i, reg84, reg26, reg2fa, reg91, reg10, reg80;
for (i = 0; i < rt5663->pdata.impedance_sensing_num; i++) {
if (rt5663->imp_table[i].vol == 7)
break;
}
if (rt5663->jack_type == SND_JACK_HEADSET) {
snd_soc_component_write(component, RT5663_MIC_DECRO_2,
rt5663->imp_table[i].dc_offset_l_manual_mic >> 16);
snd_soc_component_write(component, RT5663_MIC_DECRO_3,
rt5663->imp_table[i].dc_offset_l_manual_mic & 0xffff);
snd_soc_component_write(component, RT5663_MIC_DECRO_5,
rt5663->imp_table[i].dc_offset_r_manual_mic >> 16);
snd_soc_component_write(component, RT5663_MIC_DECRO_6,
rt5663->imp_table[i].dc_offset_r_manual_mic & 0xffff);
} else {
snd_soc_component_write(component, RT5663_MIC_DECRO_2,
rt5663->imp_table[i].dc_offset_l_manual >> 16);
snd_soc_component_write(component, RT5663_MIC_DECRO_3,
rt5663->imp_table[i].dc_offset_l_manual & 0xffff);
snd_soc_component_write(component, RT5663_MIC_DECRO_5,
rt5663->imp_table[i].dc_offset_r_manual >> 16);
snd_soc_component_write(component, RT5663_MIC_DECRO_6,
rt5663->imp_table[i].dc_offset_r_manual & 0xffff);
}
reg84 = snd_soc_component_read(component, RT5663_ASRC_2);
reg26 = snd_soc_component_read(component, RT5663_STO1_ADC_MIXER);
reg2fa = snd_soc_component_read(component, RT5663_DUMMY_1);
reg91 = snd_soc_component_read(component, RT5663_HP_CHARGE_PUMP_1);
reg10 = snd_soc_component_read(component, RT5663_RECMIX);
reg80 = snd_soc_component_read(component, RT5663_GLB_CLK);
snd_soc_component_update_bits(component, RT5663_STO_DRE_1, 0x8000, 0);
snd_soc_component_write(component, RT5663_ASRC_2, 0);
snd_soc_component_write(component, RT5663_STO1_ADC_MIXER, 0x4040);
snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
RT5663_PWR_VREF1 | RT5663_PWR_VREF2);
usleep_range(10000, 10005);
snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
RT5663_PWR_FV1 | RT5663_PWR_FV2);
snd_soc_component_update_bits(component, RT5663_GLB_CLK, RT5663_SCLK_SRC_MASK,
RT5663_SCLK_SRC_RCCLK);
snd_soc_component_update_bits(component, RT5663_RC_CLK, RT5663_DIG_25M_CLK_MASK,
RT5663_DIG_25M_CLK_EN);
snd_soc_component_update_bits(component, RT5663_ADDA_CLK_1, RT5663_I2S_PD1_MASK, 0);
snd_soc_component_write(component, RT5663_PRE_DIV_GATING_1, 0xff00);
snd_soc_component_write(component, RT5663_PRE_DIV_GATING_2, 0xfffc);
snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_1, 0x1232);
snd_soc_component_write(component, RT5663_HP_LOGIC_2, 0x0005);
snd_soc_component_write(component, RT5663_DEPOP_2, 0x3003);
snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030, 0x0030);
snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003, 0x0003);
snd_soc_component_update_bits(component, RT5663_PWR_DIG_2,
RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F,
RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F);
snd_soc_component_update_bits(component, RT5663_PWR_DIG_1,
RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 |
RT5663_PWR_LDO_DACREF_MASK | RT5663_PWR_ADC_L1 |
RT5663_PWR_ADC_R1,
RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 |
RT5663_PWR_LDO_DACREF_ON | RT5663_PWR_ADC_L1 |
RT5663_PWR_ADC_R1);
msleep(40);
snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2,
RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2);
msleep(30);
snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_2, 0x1371);
snd_soc_component_write(component, RT5663_STO_DAC_MIXER, 0);
snd_soc_component_write(component, RT5663_BYPASS_STO_DAC, 0x000c);
snd_soc_component_write(component, RT5663_HP_BIAS, 0xafaa);
snd_soc_component_write(component, RT5663_CHARGE_PUMP_1, 0x2224);
snd_soc_component_write(component, RT5663_HP_OUT_EN, 0x8088);
snd_soc_component_write(component, RT5663_CHOP_ADC, 0x3000);
snd_soc_component_write(component, RT5663_ADDA_RST, 0xc000);
snd_soc_component_write(component, RT5663_STO1_HPF_ADJ1, 0x3320);
snd_soc_component_write(component, RT5663_HP_CALIB_2, 0x00c9);
snd_soc_component_write(component, RT5663_DUMMY_1, 0x004c);
snd_soc_component_write(component, RT5663_ANA_BIAS_CUR_1, 0x7733);
snd_soc_component_write(component, RT5663_CHARGE_PUMP_2, 0x7777);
snd_soc_component_write(component, RT5663_STO_DRE_9, 0x0007);
snd_soc_component_write(component, RT5663_STO_DRE_10, 0x0007);
snd_soc_component_write(component, RT5663_DUMMY_2, 0x02a4);
snd_soc_component_write(component, RT5663_RECMIX, 0x0005);
snd_soc_component_write(component, RT5663_HP_IMP_SEN_1, 0x4334);
snd_soc_component_update_bits(component, RT5663_IRQ_3, 0x0004, 0x0004);
snd_soc_component_write(component, RT5663_HP_LOGIC_1, 0x2200);
snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000, 0x3000);
snd_soc_component_write(component, RT5663_HP_LOGIC_1, 0x6200);
for (i = 0; i < 100; i++) {
msleep(20);
if (snd_soc_component_read(component, RT5663_INT_ST_1) & 0x2)
break;
}
value = snd_soc_component_read(component, RT5663_HP_IMP_SEN_4);
snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000, 0);
snd_soc_component_write(component, RT5663_INT_ST_1, 0);
snd_soc_component_write(component, RT5663_HP_LOGIC_1, 0);
snd_soc_component_update_bits(component, RT5663_RC_CLK, RT5663_DIG_25M_CLK_MASK,
RT5663_DIG_25M_CLK_DIS);
snd_soc_component_write(component, RT5663_GLB_CLK, reg80);
snd_soc_component_write(component, RT5663_RECMIX, reg10);
snd_soc_component_write(component, RT5663_DUMMY_2, 0x00a4);
snd_soc_component_write(component, RT5663_DUMMY_1, reg2fa);
snd_soc_component_write(component, RT5663_HP_CALIB_2, 0x00c8);
snd_soc_component_write(component, RT5663_STO1_HPF_ADJ1, 0xb320);
snd_soc_component_write(component, RT5663_ADDA_RST, 0xe400);
snd_soc_component_write(component, RT5663_CHOP_ADC, 0x2000);
snd_soc_component_write(component, RT5663_HP_OUT_EN, 0x0008);
snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2, 0);
snd_soc_component_update_bits(component, RT5663_PWR_DIG_1,
RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 |
RT5663_PWR_LDO_DACREF_MASK | RT5663_PWR_ADC_L1 |
RT5663_PWR_ADC_R1, 0);
snd_soc_component_update_bits(component, RT5663_PWR_DIG_2,
RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F, 0);
snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003, 0);
snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030, 0);
snd_soc_component_write(component, RT5663_HP_LOGIC_2, 0);
snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_1, reg91);
snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK, 0);
snd_soc_component_write(component, RT5663_STO1_ADC_MIXER, reg26);
snd_soc_component_write(component, RT5663_ASRC_2, reg84);
for (i = 0; i < rt5663->pdata.impedance_sensing_num; i++) {
if (value >= rt5663->imp_table[i].imp_min &&
value <= rt5663->imp_table[i].imp_max)
break;
}
snd_soc_component_update_bits(component, RT5663_STO_DRE_9, RT5663_DRE_GAIN_HP_MASK,
rt5663->imp_table[i].vol);
snd_soc_component_update_bits(component, RT5663_STO_DRE_10, RT5663_DRE_GAIN_HP_MASK,
rt5663->imp_table[i].vol);
if (rt5663->jack_type == SND_JACK_HEADSET) {
snd_soc_component_write(component, RT5663_MIC_DECRO_2,
rt5663->imp_table[i].dc_offset_l_manual_mic >> 16);
snd_soc_component_write(component, RT5663_MIC_DECRO_3,
rt5663->imp_table[i].dc_offset_l_manual_mic & 0xffff);
snd_soc_component_write(component, RT5663_MIC_DECRO_5,
rt5663->imp_table[i].dc_offset_r_manual_mic >> 16);
snd_soc_component_write(component, RT5663_MIC_DECRO_6,
rt5663->imp_table[i].dc_offset_r_manual_mic & 0xffff);
} else {
snd_soc_component_write(component, RT5663_MIC_DECRO_2,
rt5663->imp_table[i].dc_offset_l_manual >> 16);
snd_soc_component_write(component, RT5663_MIC_DECRO_3,
rt5663->imp_table[i].dc_offset_l_manual & 0xffff);
snd_soc_component_write(component, RT5663_MIC_DECRO_5,
rt5663->imp_table[i].dc_offset_r_manual >> 16);
snd_soc_component_write(component, RT5663_MIC_DECRO_6,
rt5663->imp_table[i].dc_offset_r_manual & 0xffff);
}
return 0;
}
static int rt5663_button_detect(struct snd_soc_component *component)
{
int btn_type, val;
val = snd_soc_component_read(component, RT5663_IL_CMD_5);
dev_dbg(component->dev, "%s: val=0x%x\n", __func__, val);
btn_type = val & 0xfff0;
snd_soc_component_write(component, RT5663_IL_CMD_5, val);
return btn_type;
}
static irqreturn_t rt5663_irq(int irq, void *data)
{
struct rt5663_priv *rt5663 = data;
dev_dbg(regmap_get_device(rt5663->regmap), "%s IRQ queue work\n",
__func__);
queue_delayed_work(system_wq, &rt5663->jack_detect_work,
msecs_to_jiffies(250));
return IRQ_HANDLED;
}
static int rt5663_set_jack_detect(struct snd_soc_component *component,
struct snd_soc_jack *hs_jack, void *data)
{
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
rt5663->hs_jack = hs_jack;
rt5663_irq(0, rt5663);
return 0;
}
static bool rt5663_check_jd_status(struct snd_soc_component *component)
{
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
int val = snd_soc_component_read(component, RT5663_INT_ST_1);
dev_dbg(component->dev, "%s val=%x\n", __func__, val);
/* JD1 */
switch (rt5663->codec_ver) {
case CODEC_VER_1:
return !(val & 0x2000);
case CODEC_VER_0:
return !(val & 0x1000);
default:
dev_err(component->dev, "Unknown CODEC Version\n");
}
return false;
}
static void rt5663_jack_detect_work(struct work_struct *work)
{
struct rt5663_priv *rt5663 =
container_of(work, struct rt5663_priv, jack_detect_work.work);
struct snd_soc_component *component = rt5663->component;
int btn_type, report = 0;
if (!component)
return;
if (rt5663_check_jd_status(component)) {
/* jack in */
if (rt5663->jack_type == 0) {
/* jack was out, report jack type */
switch (rt5663->codec_ver) {
case CODEC_VER_1:
report = rt5663_v2_jack_detect(
rt5663->component, 1);
break;
case CODEC_VER_0:
report = rt5663_jack_detect(rt5663->component, 1);
if (rt5663->pdata.impedance_sensing_num)
rt5663_impedance_sensing(rt5663->component);
break;
default:
dev_err(component->dev, "Unknown CODEC Version\n");
}
/* Delay the jack insert report to avoid pop noise */
msleep(30);
} else {
/* jack is already in, report button event */
report = SND_JACK_HEADSET;
btn_type = rt5663_button_detect(rt5663->component);
/**
* rt5663 can report three kinds of button behavior,
* one click, double click and hold. However,
* currently we will report button pressed/released
* event. So all the three button behaviors are
* treated as button pressed.
*/
switch (btn_type) {
case 0x8000:
case 0x4000:
case 0x2000:
report |= SND_JACK_BTN_0;
break;
case 0x1000:
case 0x0800:
case 0x0400:
report |= SND_JACK_BTN_1;
break;
case 0x0200:
case 0x0100:
case 0x0080:
report |= SND_JACK_BTN_2;
break;
case 0x0040:
case 0x0020:
case 0x0010:
report |= SND_JACK_BTN_3;
break;
case 0x0000: /* unpressed */
break;
default:
btn_type = 0;
dev_err(rt5663->component->dev,
"Unexpected button code 0x%04x\n",
btn_type);
break;
}
/* button release or spurious interrput*/
if (btn_type == 0) {
report = rt5663->jack_type;
cancel_delayed_work_sync(
&rt5663->jd_unplug_work);
} else {
queue_delayed_work(system_wq,
&rt5663->jd_unplug_work,
msecs_to_jiffies(500));
}
}
} else {
/* jack out */
switch (rt5663->codec_ver) {
case CODEC_VER_1:
report = rt5663_v2_jack_detect(rt5663->component, 0);
break;
case CODEC_VER_0:
report = rt5663_jack_detect(rt5663->component, 0);
break;
default:
dev_err(component->dev, "Unknown CODEC Version\n");
}
}
dev_dbg(component->dev, "%s jack report: 0x%04x\n", __func__, report);
snd_soc_jack_report(rt5663->hs_jack, report, SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3);
}
static void rt5663_jd_unplug_work(struct work_struct *work)
{
struct rt5663_priv *rt5663 =
container_of(work, struct rt5663_priv, jd_unplug_work.work);
struct snd_soc_component *component = rt5663->component;
if (!component)
return;
if (!rt5663_check_jd_status(component)) {
/* jack out */
switch (rt5663->codec_ver) {
case CODEC_VER_1:
rt5663_v2_jack_detect(rt5663->component, 0);
break;
case CODEC_VER_0:
rt5663_jack_detect(rt5663->component, 0);
break;
default:
dev_err(component->dev, "Unknown CODEC Version\n");
}
snd_soc_jack_report(rt5663->hs_jack, 0, SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3);
} else {
queue_delayed_work(system_wq, &rt5663->jd_unplug_work,
msecs_to_jiffies(500));
}
}
static const struct snd_kcontrol_new rt5663_snd_controls[] = {
/* DAC Digital Volume */
SOC_DOUBLE_TLV("DAC Playback Volume", RT5663_STO1_DAC_DIG_VOL,
RT5663_DAC_L1_VOL_SHIFT + 1, RT5663_DAC_R1_VOL_SHIFT + 1,
87, 0, dac_vol_tlv),
/* ADC Digital Volume Control */
SOC_DOUBLE("ADC Capture Switch", RT5663_STO1_ADC_DIG_VOL,
RT5663_ADC_L_MUTE_SHIFT, RT5663_ADC_R_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_TLV("ADC Capture Volume", RT5663_STO1_ADC_DIG_VOL,
RT5663_ADC_L_VOL_SHIFT + 1, RT5663_ADC_R_VOL_SHIFT + 1,
63, 0, adc_vol_tlv),
};
static const struct snd_kcontrol_new rt5663_v2_specific_controls[] = {
/* Headphone Output Volume */
SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_HP_LCH_DRE,
RT5663_HP_RCH_DRE, RT5663_GAIN_HP_SHIFT, 15, 1,
rt5663_v2_hp_vol_tlv),
/* Mic Boost Volume */
SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_AEC_BST,
RT5663_GAIN_CBJ_SHIFT, 8, 0, in_bst_tlv),
};
static const struct snd_kcontrol_new rt5663_specific_controls[] = {
/* Mic Boost Volume*/
SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_CBJ_2,
RT5663_GAIN_BST1_SHIFT, 8, 0, in_bst_tlv),
/* Data Swap for Slot0/1 in ADCDAT1 */
SOC_ENUM("IF1 ADC Data Swap", rt5663_if1_adc_enum),
};
static const struct snd_kcontrol_new rt5663_hpvol_controls[] = {
/* Headphone Output Volume */
SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_STO_DRE_9,
RT5663_STO_DRE_10, RT5663_DRE_GAIN_HP_SHIFT, 23, 1,
rt5663_hp_vol_tlv),
};
static int rt5663_is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
struct snd_soc_dapm_widget *sink)
{
unsigned int val;
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
val = snd_soc_component_read(component, RT5663_GLB_CLK);
val &= RT5663_SCLK_SRC_MASK;
if (val == RT5663_SCLK_SRC_PLL1)
return 1;
else
return 0;
}
static int rt5663_is_using_asrc(struct snd_soc_dapm_widget *w,
struct snd_soc_dapm_widget *sink)
{
unsigned int reg, shift, val;
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
if (rt5663->codec_ver == CODEC_VER_1) {
switch (w->shift) {
case RT5663_ADC_STO1_ASRC_SHIFT:
reg = RT5663_ASRC_3;
shift = RT5663_V2_AD_STO1_TRACK_SHIFT;
break;
case RT5663_DAC_STO1_ASRC_SHIFT:
reg = RT5663_ASRC_2;
shift = RT5663_DA_STO1_TRACK_SHIFT;
break;
default:
return 0;
}
} else {
switch (w->shift) {
case RT5663_ADC_STO1_ASRC_SHIFT:
reg = RT5663_ASRC_2;
shift = RT5663_AD_STO1_TRACK_SHIFT;
break;
case RT5663_DAC_STO1_ASRC_SHIFT:
reg = RT5663_ASRC_2;
shift = RT5663_DA_STO1_TRACK_SHIFT;
break;
default:
return 0;
}
}
val = (snd_soc_component_read(component, reg) >> shift) & 0x7;
if (val)
return 1;
return 0;
}
static int rt5663_i2s_use_asrc(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
int da_asrc_en, ad_asrc_en;
da_asrc_en = (snd_soc_component_read(component, RT5663_ASRC_2) &
RT5663_DA_STO1_TRACK_MASK) ? 1 : 0;
switch (rt5663->codec_ver) {
case CODEC_VER_1:
ad_asrc_en = (snd_soc_component_read(component, RT5663_ASRC_3) &
RT5663_V2_AD_STO1_TRACK_MASK) ? 1 : 0;
break;
case CODEC_VER_0:
ad_asrc_en = (snd_soc_component_read(component, RT5663_ASRC_2) &
RT5663_AD_STO1_TRACK_MASK) ? 1 : 0;
break;
default:
dev_err(component->dev, "Unknown CODEC Version\n");
return 1;
}
if (da_asrc_en || ad_asrc_en)
if (rt5663->sysclk > rt5663->lrck * 384)
return 1;
dev_err(component->dev, "sysclk < 384 x fs, disable i2s asrc\n");
return 0;
}
/**
* rt5663_sel_asrc_clk_src - select ASRC clock source for a set of filters
* @component: SoC audio component device.
* @filter_mask: mask of filters.
* @clk_src: clock source
*
* The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5663 can
* only support standard 32fs or 64fs i2s format, ASRC should be enabled to
* support special i2s clock format such as Intel's 100fs(100 * sampling rate).
* ASRC function will track i2s clock and generate a corresponding system clock
* for codec. This function provides an API to select the clock source for a
* set of filters specified by the mask. And the codec driver will turn on ASRC
* for these filters if ASRC is selected as their clock source.
*/
int rt5663_sel_asrc_clk_src(struct snd_soc_component *component,
unsigned int filter_mask, unsigned int clk_src)
{
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
unsigned int asrc2_mask = 0;
unsigned int asrc2_value = 0;
unsigned int asrc3_mask = 0;
unsigned int asrc3_value = 0;
switch (clk_src) {
case RT5663_CLK_SEL_SYS:
case RT5663_CLK_SEL_I2S1_ASRC:
break;
default:
return -EINVAL;
}
if (filter_mask & RT5663_DA_STEREO_FILTER) {
asrc2_mask |= RT5663_DA_STO1_TRACK_MASK;
asrc2_value |= clk_src << RT5663_DA_STO1_TRACK_SHIFT;
}
if (filter_mask & RT5663_AD_STEREO_FILTER) {
switch (rt5663->codec_ver) {
case CODEC_VER_1:
asrc3_mask |= RT5663_V2_AD_STO1_TRACK_MASK;
asrc3_value |= clk_src << RT5663_V2_AD_STO1_TRACK_SHIFT;
break;
case CODEC_VER_0:
asrc2_mask |= RT5663_AD_STO1_TRACK_MASK;
asrc2_value |= clk_src << RT5663_AD_STO1_TRACK_SHIFT;
break;
default:
dev_err(component->dev, "Unknown CODEC Version\n");
}
}
if (asrc2_mask)
snd_soc_component_update_bits(component, RT5663_ASRC_2, asrc2_mask,
asrc2_value);
if (asrc3_mask)
snd_soc_component_update_bits(component, RT5663_ASRC_3, asrc3_mask,
asrc3_value);
return 0;
}
EXPORT_SYMBOL_GPL(rt5663_sel_asrc_clk_src);
/* Analog Mixer */
static const struct snd_kcontrol_new rt5663_recmix1l[] = {
SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1L,
RT5663_RECMIX1L_BST2_SHIFT, 1, 1),
SOC_DAPM_SINGLE("BST1 CBJ Switch", RT5663_RECMIX1L,
RT5663_RECMIX1L_BST1_CBJ_SHIFT, 1, 1),
};
static const struct snd_kcontrol_new rt5663_recmix1r[] = {
SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1R,
RT5663_RECMIX1R_BST2_SHIFT, 1, 1),
};
/* Digital Mixer */
static const struct snd_kcontrol_new rt5663_sto1_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
RT5663_M_STO1_ADC_L1_SHIFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
RT5663_M_STO1_ADC_L2_SHIFT, 1, 1),
};
static const struct snd_kcontrol_new rt5663_sto1_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
RT5663_M_STO1_ADC_R1_SHIFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
RT5663_M_STO1_ADC_R2_SHIFT, 1, 1),
};
static const struct snd_kcontrol_new rt5663_adda_l_mix[] = {
SOC_DAPM_SINGLE("ADC L Switch", RT5663_AD_DA_MIXER,
RT5663_M_ADCMIX_L_SHIFT, 1, 1),
SOC_DAPM_SINGLE("DAC L Switch", RT5663_AD_DA_MIXER,
RT5663_M_DAC1_L_SHIFT, 1, 1),
};
static const struct snd_kcontrol_new rt5663_adda_r_mix[] = {
SOC_DAPM_SINGLE("ADC R Switch", RT5663_AD_DA_MIXER,
RT5663_M_ADCMIX_R_SHIFT, 1, 1),
SOC_DAPM_SINGLE("DAC R Switch", RT5663_AD_DA_MIXER,
RT5663_M_DAC1_R_SHIFT, 1, 1),
};
static const struct snd_kcontrol_new rt5663_sto1_dac_l_mix[] = {
SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER,
RT5663_M_DAC_L1_STO_L_SHIFT, 1, 1),
};
static const struct snd_kcontrol_new rt5663_sto1_dac_r_mix[] = {
SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER,
RT5663_M_DAC_R1_STO_R_SHIFT, 1, 1),
};
/* Out Switch */
static const struct snd_kcontrol_new rt5663_hpo_switch =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5663_HP_AMP_2,
RT5663_EN_DAC_HPO_SHIFT, 1, 0);
/* Stereo ADC source */
static const char * const rt5663_sto1_adc_src[] = {
"ADC L", "ADC R"
};
static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcl_enum, RT5663_STO1_ADC_MIXER,
RT5663_STO1_ADC_L_SRC_SHIFT, rt5663_sto1_adc_src);
static const struct snd_kcontrol_new rt5663_sto1_adcl_mux =
SOC_DAPM_ENUM("STO1 ADC L Mux", rt5663_sto1_adcl_enum);
static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcr_enum, RT5663_STO1_ADC_MIXER,
RT5663_STO1_ADC_R_SRC_SHIFT, rt5663_sto1_adc_src);
static const struct snd_kcontrol_new rt5663_sto1_adcr_mux =
SOC_DAPM_ENUM("STO1 ADC R Mux", rt5663_sto1_adcr_enum);
/* RT5663: Analog DACL1 input source */
static const char * const rt5663_alg_dacl_src[] = {
"DAC L", "STO DAC MIXL"
};
static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacl_enum, RT5663_BYPASS_STO_DAC,
RT5663_DACL1_SRC_SHIFT, rt5663_alg_dacl_src);
static const struct snd_kcontrol_new rt5663_alg_dacl_mux =
SOC_DAPM_ENUM("DAC L Mux", rt5663_alg_dacl_enum);
/* RT5663: Analog DACR1 input source */
static const char * const rt5663_alg_dacr_src[] = {
"DAC R", "STO DAC MIXR"
};
static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacr_enum, RT5663_BYPASS_STO_DAC,
RT5663_DACR1_SRC_SHIFT, rt5663_alg_dacr_src);
static const struct snd_kcontrol_new rt5663_alg_dacr_mux =
SOC_DAPM_ENUM("DAC R Mux", rt5663_alg_dacr_enum);
static int rt5663_hp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
if (rt5663->codec_ver == CODEC_VER_1) {
snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
RT5663_SEL_PM_HP_SHIFT, RT5663_SEL_PM_HP_HIGH);
snd_soc_component_update_bits(component, RT5663_HP_LOGIC_2,
RT5663_HP_SIG_SRC1_MASK,
RT5663_HP_SIG_SRC1_SILENCE);
} else {
snd_soc_component_update_bits(component,
RT5663_DACREF_LDO, 0x3e0e, 0x3a0a);
snd_soc_component_write(component, RT5663_DEPOP_2, 0x3003);
snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_DIS);
snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_2, 0x1371);
snd_soc_component_write(component, RT5663_HP_BIAS, 0xabba);
snd_soc_component_write(component, RT5663_CHARGE_PUMP_1, 0x2224);
snd_soc_component_write(component, RT5663_ANA_BIAS_CUR_1, 0x7766);
snd_soc_component_write(component, RT5663_HP_BIAS, 0xafaa);
snd_soc_component_write(component, RT5663_CHARGE_PUMP_2, 0x7777);
snd_soc_component_update_bits(component, RT5663_STO_DRE_1, 0x8000,
0x8000);
snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000,
0x3000);
snd_soc_component_update_bits(component,
RT5663_DIG_VOL_ZCD, 0x00c0, 0x0080);
}
break;
case SND_SOC_DAPM_PRE_PMD:
if (rt5663->codec_ver == CODEC_VER_1) {
snd_soc_component_update_bits(component, RT5663_HP_LOGIC_2,
RT5663_HP_SIG_SRC1_MASK,
RT5663_HP_SIG_SRC1_REG);
} else {
snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000, 0x0);
snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_EN);
snd_soc_component_update_bits(component,
RT5663_DACREF_LDO, 0x3e0e, 0);
snd_soc_component_update_bits(component,
RT5663_DIG_VOL_ZCD, 0x00c0, 0);
}
break;
default:
return 0;
}
return 0;
}
static int rt5663_charge_pump_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
if (rt5663->codec_ver == CODEC_VER_0) {
snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030,
0x0030);
snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003,
0x0003);
}
break;
case SND_SOC_DAPM_POST_PMD:
if (rt5663->codec_ver == CODEC_VER_0) {
snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003, 0);
snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030, 0);
}
break;
default:
return 0;
}
return 0;
}
static int rt5663_bst2_power(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK,
RT5663_PWR_BST2 | RT5663_PWR_BST2_OP);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK, 0);
break;
default:
return 0;
}
return 0;
}
static int rt5663_pre_div_power(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_write(component, RT5663_PRE_DIV_GATING_1, 0xff00);
snd_soc_component_write(component, RT5663_PRE_DIV_GATING_2, 0xfffc);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_write(component, RT5663_PRE_DIV_GATING_1, 0x0000);
snd_soc_component_write(component, RT5663_PRE_DIV_GATING_2, 0x0000);
break;
default:
return 0;
}
return 0;
}
static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("PLL", RT5663_PWR_ANLG_3, RT5663_PWR_PLL_SHIFT, 0,
NULL, 0),
/* micbias */
SND_SOC_DAPM_MICBIAS("MICBIAS1", RT5663_PWR_ANLG_2,
RT5663_PWR_MB1_SHIFT, 0),
SND_SOC_DAPM_MICBIAS("MICBIAS2", RT5663_PWR_ANLG_2,
RT5663_PWR_MB2_SHIFT, 0),
/* Input Lines */
SND_SOC_DAPM_INPUT("IN1P"),
SND_SOC_DAPM_INPUT("IN1N"),
/* REC Mixer Power */
SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5663_PWR_ANLG_2,
RT5663_PWR_RECMIX1_SHIFT, 0, NULL, 0),
/* ADCs */
SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SUPPLY("ADC L Power", RT5663_PWR_DIG_1,
RT5663_PWR_ADC_L1_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC Clock", RT5663_CHOP_ADC,
RT5663_CKGEN_ADCC_SHIFT, 0, NULL, 0),
/* ADC Mixer */
SND_SOC_DAPM_MIXER("STO1 ADC MIXL", SND_SOC_NOPM,
0, 0, rt5663_sto1_adc_l_mix,
ARRAY_SIZE(rt5663_sto1_adc_l_mix)),
/* ADC Filter Power */
SND_SOC_DAPM_SUPPLY("STO1 ADC Filter", RT5663_PWR_DIG_2,
RT5663_PWR_ADC_S1F_SHIFT, 0, NULL, 0),
/* Digital Interface */
SND_SOC_DAPM_SUPPLY("I2S", RT5663_PWR_DIG_1, RT5663_PWR_I2S1_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("IF DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
/* Audio Interface */
SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIFTX", "AIF Capture", 0, SND_SOC_NOPM, 0, 0),
/* DAC mixer before sound effect */
SND_SOC_DAPM_MIXER("ADDA MIXL", SND_SOC_NOPM, 0, 0, rt5663_adda_l_mix,
ARRAY_SIZE(rt5663_adda_l_mix)),
SND_SOC_DAPM_MIXER("ADDA MIXR", SND_SOC_NOPM, 0, 0, rt5663_adda_r_mix,
ARRAY_SIZE(rt5663_adda_r_mix)),
SND_SOC_DAPM_PGA("DAC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DAC R1", SND_SOC_NOPM, 0, 0, NULL, 0),
/* DAC Mixer */
SND_SOC_DAPM_SUPPLY("STO1 DAC Filter", RT5663_PWR_DIG_2,
RT5663_PWR_DAC_S1F_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("STO1 DAC MIXL", SND_SOC_NOPM, 0, 0,
rt5663_sto1_dac_l_mix, ARRAY_SIZE(rt5663_sto1_dac_l_mix)),
SND_SOC_DAPM_MIXER("STO1 DAC MIXR", SND_SOC_NOPM, 0, 0,
rt5663_sto1_dac_r_mix, ARRAY_SIZE(rt5663_sto1_dac_r_mix)),
/* DACs */
SND_SOC_DAPM_SUPPLY("STO1 DAC L Power", RT5663_PWR_DIG_1,
RT5663_PWR_DAC_L1_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("STO1 DAC R Power", RT5663_PWR_DIG_1,
RT5663_PWR_DAC_R1_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_DAC("DAC L", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DAC R", NULL, SND_SOC_NOPM, 0, 0),
/* Headphone*/
SND_SOC_DAPM_SUPPLY("HP Charge Pump", SND_SOC_NOPM, 0, 0,
rt5663_charge_pump_event, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5663_hp_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
/* Output Lines */
SND_SOC_DAPM_OUTPUT("HPOL"),
SND_SOC_DAPM_OUTPUT("HPOR"),
};
static const struct snd_soc_dapm_widget rt5663_v2_specific_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("LDO2", RT5663_PWR_ANLG_3,
RT5663_PWR_LDO2_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5663_PWR_VOL,
RT5663_V2_PWR_MIC_DET_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("LDO DAC", RT5663_PWR_DIG_1,
RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
/* ASRC */
SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
/* Input Lines */
SND_SOC_DAPM_INPUT("IN2P"),
SND_SOC_DAPM_INPUT("IN2N"),
/* Boost */
SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CBJ Power", RT5663_PWR_ANLG_3,
RT5663_PWR_CBJ_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("BST2 Power", SND_SOC_NOPM, 0, 0,
rt5663_bst2_power, SND_SOC_DAPM_PRE_PMD |
SND_SOC_DAPM_POST_PMU),
/* REC Mixer */
SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5663_recmix1l,
ARRAY_SIZE(rt5663_recmix1l)),
SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5663_recmix1r,
ARRAY_SIZE(rt5663_recmix1r)),
SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5663_PWR_ANLG_2,
RT5663_PWR_RECMIX2_SHIFT, 0, NULL, 0),
/* ADC */
SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SUPPLY("ADC R Power", RT5663_PWR_DIG_1,
RT5663_PWR_ADC_R1_SHIFT, 0, NULL, 0),
/* ADC Mux */
SND_SOC_DAPM_PGA("STO1 ADC L1", RT5663_STO1_ADC_MIXER,
RT5663_STO1_ADC_L1_SRC_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("STO1 ADC R1", RT5663_STO1_ADC_MIXER,
RT5663_STO1_ADC_R1_SRC_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("STO1 ADC L2", RT5663_STO1_ADC_MIXER,
RT5663_STO1_ADC_L2_SRC_SHIFT, 1, NULL, 0),
SND_SOC_DAPM_PGA("STO1 ADC R2", RT5663_STO1_ADC_MIXER,
RT5663_STO1_ADC_R2_SRC_SHIFT, 1, NULL, 0),
SND_SOC_DAPM_MUX("STO1 ADC L Mux", SND_SOC_NOPM, 0, 0,
&rt5663_sto1_adcl_mux),
SND_SOC_DAPM_MUX("STO1 ADC R Mux", SND_SOC_NOPM, 0, 0,
&rt5663_sto1_adcr_mux),
/* ADC Mix */
SND_SOC_DAPM_MIXER("STO1 ADC MIXR", SND_SOC_NOPM, 0, 0,
rt5663_sto1_adc_r_mix, ARRAY_SIZE(rt5663_sto1_adc_r_mix)),
/* Analog DAC Clock */
SND_SOC_DAPM_SUPPLY("DAC Clock", RT5663_CHOP_DAC_L,
RT5663_CKGEN_DAC1_SHIFT, 0, NULL, 0),
/* Headphone out */
SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
&rt5663_hpo_switch),
};
static const struct snd_soc_dapm_widget rt5663_specific_dapm_widgets[] = {
/* System Clock Pre Divider Gating */
SND_SOC_DAPM_SUPPLY("Pre Div Power", SND_SOC_NOPM, 0, 0,
rt5663_pre_div_power, SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD),
/* LDO */
SND_SOC_DAPM_SUPPLY("LDO ADC", RT5663_PWR_DIG_1,
RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
/* ASRC */
SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
/* Boost */
SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM, 0, 0, NULL, 0),
/* STO ADC */
SND_SOC_DAPM_PGA("STO1 ADC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("STO1 ADC L2", SND_SOC_NOPM, 0, 0, NULL, 0),
/* Analog DAC source */
SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacl_mux),
SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacr_mux),
};
static const struct snd_soc_dapm_route rt5663_dapm_routes[] = {
/* PLL */
{ "I2S", NULL, "PLL", rt5663_is_sys_clk_from_pll },
/* ASRC */
{ "STO1 ADC Filter", NULL, "ADC ASRC", rt5663_is_using_asrc },
{ "STO1 DAC Filter", NULL, "DAC ASRC", rt5663_is_using_asrc },
{ "I2S", NULL, "I2S ASRC", rt5663_i2s_use_asrc },
{ "ADC L", NULL, "ADC L Power" },
{ "ADC L", NULL, "ADC Clock" },
{ "STO1 ADC L2", NULL, "STO1 DAC MIXL" },
{ "STO1 ADC MIXL", "ADC1 Switch", "STO1 ADC L1" },
{ "STO1 ADC MIXL", "ADC2 Switch", "STO1 ADC L2" },
{ "STO1 ADC MIXL", NULL, "STO1 ADC Filter" },
{ "IF1 ADC1", NULL, "STO1 ADC MIXL" },
{ "IF ADC", NULL, "IF1 ADC1" },
{ "AIFTX", NULL, "IF ADC" },
{ "AIFTX", NULL, "I2S" },
{ "AIFRX", NULL, "I2S" },
{ "IF DAC", NULL, "AIFRX" },
{ "IF1 DAC1 L", NULL, "IF DAC" },
{ "IF1 DAC1 R", NULL, "IF DAC" },
{ "ADDA MIXL", "ADC L Switch", "STO1 ADC MIXL" },
{ "ADDA MIXL", "DAC L Switch", "IF1 DAC1 L" },
{ "ADDA MIXL", NULL, "STO1 DAC Filter" },
{ "ADDA MIXL", NULL, "STO1 DAC L Power" },
{ "ADDA MIXR", "DAC R Switch", "IF1 DAC1 R" },
{ "ADDA MIXR", NULL, "STO1 DAC Filter" },
{ "ADDA MIXR", NULL, "STO1 DAC R Power" },
{ "DAC L1", NULL, "ADDA MIXL" },
{ "DAC R1", NULL, "ADDA MIXR" },
{ "STO1 DAC MIXL", "DAC L Switch", "DAC L1" },
{ "STO1 DAC MIXL", NULL, "STO1 DAC L Power" },
{ "STO1 DAC MIXL", NULL, "STO1 DAC Filter" },
{ "STO1 DAC MIXR", "DAC R Switch", "DAC R1" },
{ "STO1 DAC MIXR", NULL, "STO1 DAC R Power" },
{ "STO1 DAC MIXR", NULL, "STO1 DAC Filter" },
{ "HP Amp", NULL, "HP Charge Pump" },
{ "HP Amp", NULL, "DAC L" },
{ "HP Amp", NULL, "DAC R" },
};
static const struct snd_soc_dapm_route rt5663_v2_specific_dapm_routes[] = {
{ "MICBIAS1", NULL, "LDO2" },
{ "MICBIAS2", NULL, "LDO2" },
{ "BST1 CBJ", NULL, "IN1P" },
{ "BST1 CBJ", NULL, "IN1N" },
{ "BST1 CBJ", NULL, "CBJ Power" },
{ "BST2", NULL, "IN2P" },
{ "BST2", NULL, "IN2N" },
{ "BST2", NULL, "BST2 Power" },
{ "RECMIX1L", "BST2 Switch", "BST2" },
{ "RECMIX1L", "BST1 CBJ Switch", "BST1 CBJ" },
{ "RECMIX1L", NULL, "RECMIX1L Power" },
{ "RECMIX1R", "BST2 Switch", "BST2" },
{ "RECMIX1R", NULL, "RECMIX1R Power" },
{ "ADC L", NULL, "RECMIX1L" },
{ "ADC R", NULL, "RECMIX1R" },
{ "ADC R", NULL, "ADC R Power" },
{ "ADC R", NULL, "ADC Clock" },
{ "STO1 ADC L Mux", "ADC L", "ADC L" },
{ "STO1 ADC L Mux", "ADC R", "ADC R" },
{ "STO1 ADC L1", NULL, "STO1 ADC L Mux" },
{ "STO1 ADC R Mux", "ADC L", "ADC L" },
{ "STO1 ADC R Mux", "ADC R", "ADC R" },
{ "STO1 ADC R1", NULL, "STO1 ADC R Mux" },
{ "STO1 ADC R2", NULL, "STO1 DAC MIXR" },
{ "STO1 ADC MIXR", "ADC1 Switch", "STO1 ADC R1" },
{ "STO1 ADC MIXR", "ADC2 Switch", "STO1 ADC R2" },
{ "STO1 ADC MIXR", NULL, "STO1 ADC Filter" },
{ "IF1 ADC1", NULL, "STO1 ADC MIXR" },
{ "ADDA MIXR", "ADC R Switch", "STO1 ADC MIXR" },
{ "DAC L", NULL, "STO1 DAC MIXL" },
{ "DAC L", NULL, "LDO DAC" },
{ "DAC L", NULL, "DAC Clock" },
{ "DAC R", NULL, "STO1 DAC MIXR" },
{ "DAC R", NULL, "LDO DAC" },
{ "DAC R", NULL, "DAC Clock" },
{ "HPO Playback", "Switch", "HP Amp" },
{ "HPOL", NULL, "HPO Playback" },
{ "HPOR", NULL, "HPO Playback" },
};
static const struct snd_soc_dapm_route rt5663_specific_dapm_routes[] = {
{ "I2S", NULL, "Pre Div Power" },
{ "BST1", NULL, "IN1P" },
{ "BST1", NULL, "IN1N" },
{ "BST1", NULL, "RECMIX1L Power" },
{ "ADC L", NULL, "BST1" },
{ "STO1 ADC L1", NULL, "ADC L" },
{ "DAC L Mux", "DAC L", "DAC L1" },
{ "DAC L Mux", "STO DAC MIXL", "STO1 DAC MIXL" },
{ "DAC R Mux", "DAC R", "DAC R1"},
{ "DAC R Mux", "STO DAC MIXR", "STO1 DAC MIXR" },
{ "DAC L", NULL, "DAC L Mux" },
{ "DAC R", NULL, "DAC R Mux" },
{ "HPOL", NULL, "HP Amp" },
{ "HPOR", NULL, "HP Amp" },
};
static int rt5663_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
unsigned int val_len = 0;
int pre_div;
rt5663->lrck = params_rate(params);
dev_dbg(dai->dev, "bclk is %dHz and sysclk is %dHz\n",
rt5663->lrck, rt5663->sysclk);
pre_div = rl6231_get_clk_info(rt5663->sysclk, rt5663->lrck);
if (pre_div < 0) {
dev_err(component->dev, "Unsupported clock setting %d for DAI %d\n",
rt5663->lrck, dai->id);
return -EINVAL;
}
dev_dbg(dai->dev, "pre_div is %d for iis %d\n", pre_div, dai->id);
switch (params_width(params)) {
case 8:
val_len = RT5663_I2S_DL_8;
break;
case 16:
val_len = RT5663_I2S_DL_16;
break;
case 20:
val_len = RT5663_I2S_DL_20;
break;
case 24:
val_len = RT5663_I2S_DL_24;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, RT5663_I2S1_SDP,
RT5663_I2S_DL_MASK, val_len);
snd_soc_component_update_bits(component, RT5663_ADDA_CLK_1,
RT5663_I2S_PD1_MASK, pre_div << RT5663_I2S_PD1_SHIFT);
return 0;
}
static int rt5663_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
unsigned int reg_val = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
break;
case SND_SOC_DAIFMT_CBS_CFS:
reg_val |= RT5663_I2S_MS_S;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
reg_val |= RT5663_I2S_BP_INV;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_LEFT_J:
reg_val |= RT5663_I2S_DF_LEFT;
break;
case SND_SOC_DAIFMT_DSP_A:
reg_val |= RT5663_I2S_DF_PCM_A;
break;
case SND_SOC_DAIFMT_DSP_B:
reg_val |= RT5663_I2S_DF_PCM_B;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, RT5663_I2S1_SDP, RT5663_I2S_MS_MASK |
RT5663_I2S_BP_MASK | RT5663_I2S_DF_MASK, reg_val);
return 0;
}
static int rt5663_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0;
if (freq == rt5663->sysclk && clk_id == rt5663->sysclk_src)
return 0;
switch (clk_id) {
case RT5663_SCLK_S_MCLK:
reg_val |= RT5663_SCLK_SRC_MCLK;
break;
case RT5663_SCLK_S_PLL1:
reg_val |= RT5663_SCLK_SRC_PLL1;
break;
case RT5663_SCLK_S_RCCLK:
reg_val |= RT5663_SCLK_SRC_RCCLK;
break;
default:
dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
return -EINVAL;
}
snd_soc_component_update_bits(component, RT5663_GLB_CLK, RT5663_SCLK_SRC_MASK,
reg_val);
rt5663->sysclk = freq;
rt5663->sysclk_src = clk_id;
dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
freq, clk_id);
return 0;
}
static int rt5663_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
unsigned int freq_in, unsigned int freq_out)
{
struct snd_soc_component *component = dai->component;
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
struct rl6231_pll_code pll_code;
int ret;
int mask, shift, val;
if (source == rt5663->pll_src && freq_in == rt5663->pll_in &&
freq_out == rt5663->pll_out)
return 0;
if (!freq_in || !freq_out) {
dev_dbg(component->dev, "PLL disabled\n");
rt5663->pll_in = 0;
rt5663->pll_out = 0;
snd_soc_component_update_bits(component, RT5663_GLB_CLK,
RT5663_SCLK_SRC_MASK, RT5663_SCLK_SRC_MCLK);
return 0;
}
switch (rt5663->codec_ver) {
case CODEC_VER_1:
mask = RT5663_V2_PLL1_SRC_MASK;
shift = RT5663_V2_PLL1_SRC_SHIFT;
break;
case CODEC_VER_0:
mask = RT5663_PLL1_SRC_MASK;
shift = RT5663_PLL1_SRC_SHIFT;
break;
default:
dev_err(component->dev, "Unknown CODEC Version\n");
return -EINVAL;
}
switch (source) {
case RT5663_PLL1_S_MCLK:
val = 0x0;
break;
case RT5663_PLL1_S_BCLK1:
val = 0x1;
break;
default:
dev_err(component->dev, "Unknown PLL source %d\n", source);
return -EINVAL;
}
snd_soc_component_update_bits(component, RT5663_GLB_CLK, mask, (val << shift));
ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
if (ret < 0) {
dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
return ret;
}
dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", pll_code.m_bp,
(pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code,
pll_code.k_code);
snd_soc_component_write(component, RT5663_PLL_1,
pll_code.n_code << RT5663_PLL_N_SHIFT | pll_code.k_code);
snd_soc_component_write(component, RT5663_PLL_2,
((pll_code.m_bp ? 0 : pll_code.m_code) << RT5663_PLL_M_SHIFT) |
(pll_code.m_bp << RT5663_PLL_M_BP_SHIFT));
rt5663->pll_in = freq_in;
rt5663->pll_out = freq_out;
rt5663->pll_src = source;
return 0;
}
static int rt5663_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
unsigned int val = 0, reg;
if (rx_mask || tx_mask)
val |= RT5663_TDM_MODE_TDM;
switch (slots) {
case 4:
val |= RT5663_TDM_IN_CH_4;
val |= RT5663_TDM_OUT_CH_4;
break;
case 6:
val |= RT5663_TDM_IN_CH_6;
val |= RT5663_TDM_OUT_CH_6;
break;
case 8:
val |= RT5663_TDM_IN_CH_8;
val |= RT5663_TDM_OUT_CH_8;
break;
case 2:
break;
default:
return -EINVAL;
}
switch (slot_width) {
case 20:
val |= RT5663_TDM_IN_LEN_20;
val |= RT5663_TDM_OUT_LEN_20;
break;
case 24:
val |= RT5663_TDM_IN_LEN_24;
val |= RT5663_TDM_OUT_LEN_24;
break;
case 32:
val |= RT5663_TDM_IN_LEN_32;
val |= RT5663_TDM_OUT_LEN_32;
break;
case 16:
break;
default:
return -EINVAL;
}
switch (rt5663->codec_ver) {
case CODEC_VER_1:
reg = RT5663_TDM_2;
break;
case CODEC_VER_0:
reg = RT5663_TDM_1;
break;
default:
dev_err(component->dev, "Unknown CODEC Version\n");
return -EINVAL;
}
snd_soc_component_update_bits(component, reg, RT5663_TDM_MODE_MASK |
RT5663_TDM_IN_CH_MASK | RT5663_TDM_OUT_CH_MASK |
RT5663_TDM_IN_LEN_MASK | RT5663_TDM_OUT_LEN_MASK, val);
return 0;
}
static int rt5663_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
{
struct snd_soc_component *component = dai->component;
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
unsigned int reg;
dev_dbg(component->dev, "%s ratio = %d\n", __func__, ratio);
if (rt5663->codec_ver == CODEC_VER_1)
reg = RT5663_TDM_9;
else
reg = RT5663_TDM_5;
switch (ratio) {
case 32:
snd_soc_component_update_bits(component, reg,
RT5663_TDM_LENGTN_MASK,
RT5663_TDM_LENGTN_16);
break;
case 40:
snd_soc_component_update_bits(component, reg,
RT5663_TDM_LENGTN_MASK,
RT5663_TDM_LENGTN_20);
break;
case 48:
snd_soc_component_update_bits(component, reg,
RT5663_TDM_LENGTN_MASK,
RT5663_TDM_LENGTN_24);
break;
case 64:
snd_soc_component_update_bits(component, reg,
RT5663_TDM_LENGTN_MASK,
RT5663_TDM_LENGTN_32);
break;
default:
dev_err(component->dev, "Invalid ratio!\n");
return -EINVAL;
}
return 0;
}
static int rt5663_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_ON:
snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
RT5663_PWR_FV1 | RT5663_PWR_FV2);
break;
case SND_SOC_BIAS_PREPARE:
if (rt5663->codec_ver == CODEC_VER_1) {
snd_soc_component_update_bits(component, RT5663_DIG_MISC,
RT5663_DIG_GATE_CTRL_MASK,
RT5663_DIG_GATE_CTRL_EN);
snd_soc_component_update_bits(component, RT5663_SIG_CLK_DET,
RT5663_EN_ANA_CLK_DET_MASK |
RT5663_PWR_CLK_DET_MASK,
RT5663_EN_ANA_CLK_DET_AUTO |
RT5663_PWR_CLK_DET_EN);
}
break;
case SND_SOC_BIAS_STANDBY:
if (rt5663->codec_ver == CODEC_VER_1)
snd_soc_component_update_bits(component, RT5663_DIG_MISC,
RT5663_DIG_GATE_CTRL_MASK,
RT5663_DIG_GATE_CTRL_DIS);
snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK |
RT5663_PWR_MB_MASK, RT5663_PWR_VREF1 |
RT5663_PWR_VREF2 | RT5663_PWR_MB);
usleep_range(10000, 10005);
if (rt5663->codec_ver == CODEC_VER_1) {
snd_soc_component_update_bits(component, RT5663_SIG_CLK_DET,
RT5663_EN_ANA_CLK_DET_MASK |
RT5663_PWR_CLK_DET_MASK,
RT5663_EN_ANA_CLK_DET_DIS |
RT5663_PWR_CLK_DET_DIS);
}
break;
case SND_SOC_BIAS_OFF:
if (rt5663->jack_type != SND_JACK_HEADSET)
snd_soc_component_update_bits(component,
RT5663_PWR_ANLG_1,
RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
RT5663_PWR_FV1 | RT5663_PWR_FV2 |
RT5663_PWR_MB_MASK, 0);
else
snd_soc_component_update_bits(component,
RT5663_PWR_ANLG_1,
RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
RT5663_PWR_FV1 | RT5663_PWR_FV2);
break;
default:
break;
}
return 0;
}
static int rt5663_probe(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
rt5663->component = component;
switch (rt5663->codec_ver) {
case CODEC_VER_1:
snd_soc_dapm_new_controls(dapm,
rt5663_v2_specific_dapm_widgets,
ARRAY_SIZE(rt5663_v2_specific_dapm_widgets));
snd_soc_dapm_add_routes(dapm,
rt5663_v2_specific_dapm_routes,
ARRAY_SIZE(rt5663_v2_specific_dapm_routes));
snd_soc_add_component_controls(component, rt5663_v2_specific_controls,
ARRAY_SIZE(rt5663_v2_specific_controls));
break;
case CODEC_VER_0:
snd_soc_dapm_new_controls(dapm,
rt5663_specific_dapm_widgets,
ARRAY_SIZE(rt5663_specific_dapm_widgets));
snd_soc_dapm_add_routes(dapm,
rt5663_specific_dapm_routes,
ARRAY_SIZE(rt5663_specific_dapm_routes));
snd_soc_add_component_controls(component, rt5663_specific_controls,
ARRAY_SIZE(rt5663_specific_controls));
if (!rt5663->imp_table)
snd_soc_add_component_controls(component, rt5663_hpvol_controls,
ARRAY_SIZE(rt5663_hpvol_controls));
break;
}
return 0;
}
static void rt5663_remove(struct snd_soc_component *component)
{
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
regmap_write(rt5663->regmap, RT5663_RESET, 0);
}
#ifdef CONFIG_PM
static int rt5663_suspend(struct snd_soc_component *component)
{
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
regcache_cache_only(rt5663->regmap, true);
regcache_mark_dirty(rt5663->regmap);
return 0;
}
static int rt5663_resume(struct snd_soc_component *component)
{
struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
regcache_cache_only(rt5663->regmap, false);
regcache_sync(rt5663->regmap);
rt5663_irq(0, rt5663);
return 0;
}
#else
#define rt5663_suspend NULL
#define rt5663_resume NULL
#endif
#define RT5663_STEREO_RATES SNDRV_PCM_RATE_8000_192000
#define RT5663_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
static const struct snd_soc_dai_ops rt5663_aif_dai_ops = {
.hw_params = rt5663_hw_params,
.set_fmt = rt5663_set_dai_fmt,
.set_sysclk = rt5663_set_dai_sysclk,
.set_pll = rt5663_set_dai_pll,
.set_tdm_slot = rt5663_set_tdm_slot,
.set_bclk_ratio = rt5663_set_bclk_ratio,
};
static struct snd_soc_dai_driver rt5663_dai[] = {
{
.name = "rt5663-aif",
.id = RT5663_AIF,
.playback = {
.stream_name = "AIF Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT5663_STEREO_RATES,
.formats = RT5663_FORMATS,
},
.capture = {
.stream_name = "AIF Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT5663_STEREO_RATES,
.formats = RT5663_FORMATS,
},
.ops = &rt5663_aif_dai_ops,
},
};
static const struct snd_soc_component_driver soc_component_dev_rt5663 = {
.probe = rt5663_probe,
.remove = rt5663_remove,
.suspend = rt5663_suspend,
.resume = rt5663_resume,
.set_bias_level = rt5663_set_bias_level,
.controls = rt5663_snd_controls,
.num_controls = ARRAY_SIZE(rt5663_snd_controls),
.dapm_widgets = rt5663_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt5663_dapm_widgets),
.dapm_routes = rt5663_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(rt5663_dapm_routes),
.set_jack = rt5663_set_jack_detect,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config rt5663_v2_regmap = {
.reg_bits = 16,
.val_bits = 16,
.use_single_read = true,
.use_single_write = true,
.max_register = 0x07fa,
.volatile_reg = rt5663_v2_volatile_register,
.readable_reg = rt5663_v2_readable_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = rt5663_v2_reg,
.num_reg_defaults = ARRAY_SIZE(rt5663_v2_reg),
};
static const struct regmap_config rt5663_regmap = {
.reg_bits = 16,
.val_bits = 16,
.use_single_read = true,
.use_single_write = true,
.max_register = 0x03f3,
.volatile_reg = rt5663_volatile_register,
.readable_reg = rt5663_readable_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = rt5663_reg,
.num_reg_defaults = ARRAY_SIZE(rt5663_reg),
};
static const struct regmap_config temp_regmap = {
.name = "nocache",
.reg_bits = 16,
.val_bits = 16,
.use_single_read = true,
.use_single_write = true,
.max_register = 0x03f3,
.cache_type = REGCACHE_NONE,
};
static const struct i2c_device_id rt5663_i2c_id[] = {
{ "rt5663", 0 },
{}
};
MODULE_DEVICE_TABLE(i2c, rt5663_i2c_id);
#if defined(CONFIG_OF)
static const struct of_device_id rt5663_of_match[] = {
{ .compatible = "realtek,rt5663", },
{},
};
MODULE_DEVICE_TABLE(of, rt5663_of_match);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id rt5663_acpi_match[] = {
{ "10EC5663", 0},
{},
};
MODULE_DEVICE_TABLE(acpi, rt5663_acpi_match);
#endif
static void rt5663_v2_calibrate(struct rt5663_priv *rt5663)
{
regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0100);
regmap_write(rt5663->regmap, RT5663_RECMIX, 0x4040);
regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x0001);
regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380);
regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000);
regmap_write(rt5663->regmap, RT5663_CHOP_DAC_L, 0x3030);
regmap_write(rt5663->regmap, RT5663_CALIB_ADC, 0x3c05);
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23e);
msleep(40);
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23e);
regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x0321);
regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0xfc00);
msleep(500);
}
static void rt5663_calibrate(struct rt5663_priv *rt5663)
{
int value, count;
regmap_write(rt5663->regmap, RT5663_RESET, 0x0000);
msleep(20);
regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_4, 0x00a1);
regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380);
regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000);
regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x000c);
regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x0324);
regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x8001);
regmap_write(rt5663->regmap, RT5663_VREFADJ_OP, 0x0f28);
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23b);
msleep(30);
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23b);
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8000);
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x0008);
regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_1, 0xffff);
regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_2, 0xffff);
regmap_write(rt5663->regmap, RT5663_CBJ_1, 0x8c10);
regmap_write(rt5663->regmap, RT5663_IL_CMD_2, 0x00c1);
regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb880);
regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4110);
regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4118);
count = 0;
while (true) {
regmap_read(rt5663->regmap, RT5663_INT_ST_2, &value);
if (!(value & 0x80))
usleep_range(10000, 10005);
else
break;
if (++count > 200)
break;
}
regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x0000);
regmap_write(rt5663->regmap, RT5663_DEPOP_2, 0x3003);
regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0038);
regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x003b);
regmap_write(rt5663->regmap, RT5663_PWR_DIG_2, 0x8400);
regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x8df8);
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8003);
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x018c);
regmap_write(rt5663->regmap, RT5663_HP_CHARGE_PUMP_1, 0x1e32);
regmap_write(rt5663->regmap, RT5663_DUMMY_2, 0x8089);
regmap_write(rt5663->regmap, RT5663_DACREF_LDO, 0x3b0b);
msleep(40);
regmap_write(rt5663->regmap, RT5663_STO_DAC_MIXER, 0x0000);
regmap_write(rt5663->regmap, RT5663_BYPASS_STO_DAC, 0x000c);
regmap_write(rt5663->regmap, RT5663_HP_BIAS, 0xafaa);
regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_1, 0x2224);
regmap_write(rt5663->regmap, RT5663_HP_OUT_EN, 0x8088);
regmap_write(rt5663->regmap, RT5663_STO_DRE_9, 0x0017);
regmap_write(rt5663->regmap, RT5663_STO_DRE_10, 0x0017);
regmap_write(rt5663->regmap, RT5663_STO1_ADC_MIXER, 0x4040);
regmap_write(rt5663->regmap, RT5663_CHOP_ADC, 0x3000);
regmap_write(rt5663->regmap, RT5663_RECMIX, 0x0005);
regmap_write(rt5663->regmap, RT5663_ADDA_RST, 0xc000);
regmap_write(rt5663->regmap, RT5663_STO1_HPF_ADJ1, 0x3320);
regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x00c9);
regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x004c);
regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_1, 0x1111);
regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0x4402);
regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x3311);
regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0x0069);
regmap_write(rt5663->regmap, RT5663_HP_CALIB_3, 0x06ce);
regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6800);
regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x1100);
regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0057);
regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe800);
count = 0;
while (true) {
regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value);
if (value & 0x8000)
usleep_range(10000, 10005);
else
break;
if (count > 200)
return;
count++;
}
regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6200);
regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0059);
regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe200);
count = 0;
while (true) {
regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value);
if (value & 0x8000)
usleep_range(10000, 10005);
else
break;
if (count > 200)
return;
count++;
}
regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb8e0);
usleep_range(10000, 10005);
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0x003b);
usleep_range(10000, 10005);
regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0000);
usleep_range(10000, 10005);
regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x000b);
usleep_range(10000, 10005);
regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0008);
usleep_range(10000, 10005);
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x0000);
usleep_range(10000, 10005);
}
static int rt5663_parse_dp(struct rt5663_priv *rt5663, struct device *dev)
{
int table_size;
int ret;
device_property_read_u32(dev, "realtek,dc_offset_l_manual",
&rt5663->pdata.dc_offset_l_manual);
device_property_read_u32(dev, "realtek,dc_offset_r_manual",
&rt5663->pdata.dc_offset_r_manual);
device_property_read_u32(dev, "realtek,dc_offset_l_manual_mic",
&rt5663->pdata.dc_offset_l_manual_mic);
device_property_read_u32(dev, "realtek,dc_offset_r_manual_mic",
&rt5663->pdata.dc_offset_r_manual_mic);
device_property_read_u32(dev, "realtek,impedance_sensing_num",
&rt5663->pdata.impedance_sensing_num);
if (rt5663->pdata.impedance_sensing_num) {
table_size = sizeof(struct impedance_mapping_table) *
rt5663->pdata.impedance_sensing_num;
rt5663->imp_table = devm_kzalloc(dev, table_size, GFP_KERNEL);
if (!rt5663->imp_table)
return -ENOMEM;
ret = device_property_read_u32_array(dev,
"realtek,impedance_sensing_table",
(u32 *)rt5663->imp_table, table_size);
if (ret)
return ret;
}
return 0;
}
static int rt5663_i2c_probe(struct i2c_client *i2c)
{
struct rt5663_platform_data *pdata = dev_get_platdata(&i2c->dev);
struct rt5663_priv *rt5663;
int ret, i;
unsigned int val;
struct regmap *regmap;
rt5663 = devm_kzalloc(&i2c->dev, sizeof(struct rt5663_priv),
GFP_KERNEL);
if (rt5663 == NULL)
return -ENOMEM;
i2c_set_clientdata(i2c, rt5663);
if (pdata)
rt5663->pdata = *pdata;
else {
ret = rt5663_parse_dp(rt5663, &i2c->dev);
if (ret)
return ret;
}
for (i = 0; i < ARRAY_SIZE(rt5663->supplies); i++)
rt5663->supplies[i].supply = rt5663_supply_names[i];
ret = devm_regulator_bulk_get(&i2c->dev,
ARRAY_SIZE(rt5663->supplies),
rt5663->supplies);
if (ret) {
dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
return ret;
}
/* Set load for regulator. */
for (i = 0; i < ARRAY_SIZE(rt5663->supplies); i++) {
ret = regulator_set_load(rt5663->supplies[i].consumer,
RT5663_SUPPLY_CURRENT_UA);
if (ret < 0) {
dev_err(&i2c->dev,
"Failed to set regulator load on %s, ret: %d\n",
rt5663->supplies[i].supply, ret);
return ret;
}
}
ret = regulator_bulk_enable(ARRAY_SIZE(rt5663->supplies),
rt5663->supplies);
if (ret) {
dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
return ret;
}
msleep(RT5663_POWER_ON_DELAY_MS);
regmap = devm_regmap_init_i2c(i2c, &temp_regmap);
if (IS_ERR(regmap)) {
ret = PTR_ERR(regmap);
dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n",
ret);
goto err_enable;
}
ret = regmap_read(regmap, RT5663_VENDOR_ID_2, &val);
if (ret || (val != RT5663_DEVICE_ID_2 && val != RT5663_DEVICE_ID_1)) {
dev_err(&i2c->dev,
"Device with ID register %#x is not rt5663, retry one time.\n",
val);
msleep(100);
regmap_read(regmap, RT5663_VENDOR_ID_2, &val);
}
switch (val) {
case RT5663_DEVICE_ID_2:
rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_v2_regmap);
rt5663->codec_ver = CODEC_VER_1;
break;
case RT5663_DEVICE_ID_1:
rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_regmap);
rt5663->codec_ver = CODEC_VER_0;
break;
default:
dev_err(&i2c->dev,
"Device with ID register %#x is not rt5663\n",
val);
ret = -ENODEV;
goto err_enable;
}
if (IS_ERR(rt5663->regmap)) {
ret = PTR_ERR(rt5663->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
goto err_enable;
}
/* reset and calibrate */
regmap_write(rt5663->regmap, RT5663_RESET, 0);
regcache_cache_bypass(rt5663->regmap, true);
switch (rt5663->codec_ver) {
case CODEC_VER_1:
rt5663_v2_calibrate(rt5663);
break;
case CODEC_VER_0:
rt5663_calibrate(rt5663);
break;
default:
dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
}
regcache_cache_bypass(rt5663->regmap, false);
regmap_write(rt5663->regmap, RT5663_RESET, 0);
dev_dbg(&i2c->dev, "calibrate done\n");
switch (rt5663->codec_ver) {
case CODEC_VER_1:
break;
case CODEC_VER_0:
ret = regmap_register_patch(rt5663->regmap, rt5663_patch_list,
ARRAY_SIZE(rt5663_patch_list));
if (ret != 0)
dev_warn(&i2c->dev,
"Failed to apply regmap patch: %d\n", ret);
break;
default:
dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
}
/* GPIO1 as IRQ */
regmap_update_bits(rt5663->regmap, RT5663_GPIO_1, RT5663_GP1_PIN_MASK,
RT5663_GP1_PIN_IRQ);
/* 4btn inline command debounce */
regmap_update_bits(rt5663->regmap, RT5663_IL_CMD_5,
RT5663_4BTN_CLK_DEB_MASK, RT5663_4BTN_CLK_DEB_65MS);
switch (rt5663->codec_ver) {
case CODEC_VER_1:
regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
/* JD1 */
regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
RT5663_IRQ_POW_SAV_MASK | RT5663_IRQ_POW_SAV_JD1_MASK,
RT5663_IRQ_POW_SAV_EN | RT5663_IRQ_POW_SAV_JD1_EN);
regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_2,
RT5663_PWR_JD1_MASK, RT5663_PWR_JD1);
regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
RT5663_EN_CB_JD_MASK, RT5663_EN_CB_JD_EN);
regmap_update_bits(rt5663->regmap, RT5663_HP_LOGIC_2,
RT5663_HP_SIG_SRC1_MASK, RT5663_HP_SIG_SRC1_REG);
regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
RT5663_VREF_BIAS_MASK | RT5663_CBJ_DET_MASK |
RT5663_DET_TYPE_MASK, RT5663_VREF_BIAS_REG |
RT5663_CBJ_DET_EN | RT5663_DET_TYPE_QFN);
/* Set GPIO4 and GPIO8 as input for combo jack */
regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
RT5663_GP4_PIN_CONF_MASK, RT5663_GP4_PIN_CONF_INPUT);
regmap_update_bits(rt5663->regmap, RT5663_GPIO_3,
RT5663_GP8_PIN_CONF_MASK, RT5663_GP8_PIN_CONF_INPUT);
regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_1,
RT5663_LDO1_DVO_MASK | RT5663_AMP_HP_MASK,
RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
break;
case CODEC_VER_0:
regmap_update_bits(rt5663->regmap, RT5663_DIG_MISC,
RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
RT5663_IRQ_MANUAL_MASK, RT5663_IRQ_MANUAL_EN);
regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
regmap_update_bits(rt5663->regmap, RT5663_GPIO_1,
RT5663_GPIO1_TYPE_MASK, RT5663_GPIO1_TYPE_EN);
regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
RT5663_GP1_PIN_CONF_MASK | RT5663_SEL_GPIO1_MASK,
RT5663_GP1_PIN_CONF_OUTPUT | RT5663_SEL_GPIO1_EN);
regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
RT5663_RECMIX1_BST1_MASK, RT5663_RECMIX1_BST1_ON);
regmap_update_bits(rt5663->regmap, RT5663_TDM_2,
RT5663_DATA_SWAP_ADCDAT1_MASK,
RT5663_DATA_SWAP_ADCDAT1_LL);
break;
default:
dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
}
INIT_DELAYED_WORK(&rt5663->jack_detect_work, rt5663_jack_detect_work);
INIT_DELAYED_WORK(&rt5663->jd_unplug_work, rt5663_jd_unplug_work);
if (i2c->irq) {
ret = request_irq(i2c->irq, rt5663_irq,
IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
| IRQF_ONESHOT, "rt5663", rt5663);
if (ret) {
dev_err(&i2c->dev, "%s Failed to reguest IRQ: %d\n",
__func__, ret);
goto err_enable;
}
}
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_rt5663,
rt5663_dai, ARRAY_SIZE(rt5663_dai));
if (ret)
goto err_enable;
return 0;
/*
* Error after enabling regulators should goto err_enable
* to disable regulators.
*/
err_enable:
if (i2c->irq)
free_irq(i2c->irq, rt5663);
regulator_bulk_disable(ARRAY_SIZE(rt5663->supplies), rt5663->supplies);
return ret;
}
static void rt5663_i2c_remove(struct i2c_client *i2c)
{
struct rt5663_priv *rt5663 = i2c_get_clientdata(i2c);
if (i2c->irq)
free_irq(i2c->irq, rt5663);
regulator_bulk_disable(ARRAY_SIZE(rt5663->supplies), rt5663->supplies);
}
static void rt5663_i2c_shutdown(struct i2c_client *client)
{
struct rt5663_priv *rt5663 = i2c_get_clientdata(client);
regmap_write(rt5663->regmap, RT5663_RESET, 0);
}
static struct i2c_driver rt5663_i2c_driver = {
.driver = {
.name = "rt5663",
.acpi_match_table = ACPI_PTR(rt5663_acpi_match),
.of_match_table = of_match_ptr(rt5663_of_match),
},
.probe = rt5663_i2c_probe,
.remove = rt5663_i2c_remove,
.shutdown = rt5663_i2c_shutdown,
.id_table = rt5663_i2c_id,
};
module_i2c_driver(rt5663_i2c_driver);
MODULE_DESCRIPTION("ASoC RT5663 driver");
MODULE_AUTHOR("Jack Yu <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/rt5663.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// es8326.c -- es8326 ALSA SoC audio driver
// Copyright Everest Semiconductor Co., Ltd
//
// Authors: David Yang <[email protected]>
//
#include <linux/clk.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <sound/jack.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/tlv.h>
#include "es8326.h"
struct es8326_priv {
struct clk *mclk;
struct i2c_client *i2c;
struct regmap *regmap;
struct snd_soc_component *component;
struct delayed_work jack_detect_work;
struct delayed_work button_press_work;
struct snd_soc_jack *jack;
int irq;
/* The lock protects the situation that an irq is generated
* while enabling or disabling or during an irq.
*/
struct mutex lock;
u8 mic1_src;
u8 mic2_src;
u8 jack_pol;
u8 interrupt_src;
u8 interrupt_clk;
bool jd_inverted;
unsigned int sysclk;
bool calibrated;
int version;
int hp;
int jack_remove_retry;
};
static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(dac_vol_tlv, -9550, 50, 0);
static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(adc_vol_tlv, -9550, 50, 0);
static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(adc_analog_pga_tlv, 0, 300, 0);
static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(adc_pga_tlv, 0, 600, 0);
static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(softramp_rate, 0, 100, 0);
static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(drc_target_tlv, -3200, 200, 0);
static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(drc_recovery_tlv, -125, 250, 0);
static const char *const winsize[] = {
"0.25db/2 LRCK",
"0.25db/4 LRCK",
"0.25db/8 LRCK",
"0.25db/16 LRCK",
"0.25db/32 LRCK",
"0.25db/64 LRCK",
"0.25db/128 LRCK",
"0.25db/256 LRCK",
"0.25db/512 LRCK",
"0.25db/1024 LRCK",
"0.25db/2048 LRCK",
"0.25db/4096 LRCK",
"0.25db/8192 LRCK",
"0.25db/16384 LRCK",
"0.25db/32768 LRCK",
"0.25db/65536 LRCK",
};
static const char *const dacpol_txt[] = {
"Normal", "R Invert", "L Invert", "L + R Invert" };
static const struct soc_enum dacpol =
SOC_ENUM_SINGLE(ES8326_DAC_DSM, 4, 4, dacpol_txt);
static const struct soc_enum alc_winsize =
SOC_ENUM_SINGLE(ES8326_ADC_RAMPRATE, 4, 16, winsize);
static const struct soc_enum drc_winsize =
SOC_ENUM_SINGLE(ES8326_DRC_WINSIZE, 4, 16, winsize);
static const struct snd_kcontrol_new es8326_snd_controls[] = {
SOC_SINGLE_TLV("DAC Playback Volume", ES8326_DAC_VOL, 0, 0xbf, 0, dac_vol_tlv),
SOC_ENUM("Playback Polarity", dacpol),
SOC_SINGLE_TLV("DAC Ramp Rate", ES8326_DAC_RAMPRATE, 0, 0x0f, 0, softramp_rate),
SOC_SINGLE_TLV("DRC Recovery Level", ES8326_DRC_RECOVERY, 0, 4, 0, drc_recovery_tlv),
SOC_ENUM("DRC Winsize", drc_winsize),
SOC_SINGLE_TLV("DRC Target Level", ES8326_DRC_WINSIZE, 0, 0x0f, 0, drc_target_tlv),
SOC_DOUBLE_R_TLV("ADC Capture Volume", ES8326_ADC1_VOL, ES8326_ADC2_VOL, 0, 0xff, 0,
adc_vol_tlv),
SOC_DOUBLE_TLV("ADC PGA Volume", ES8326_ADC_SCALE, 4, 0, 5, 0, adc_pga_tlv),
SOC_SINGLE_TLV("ADC PGA Gain Volume", ES8326_PGAGAIN, 0, 10, 0, adc_analog_pga_tlv),
SOC_SINGLE_TLV("ADC Ramp Rate", ES8326_ADC_RAMPRATE, 0, 0x0f, 0, softramp_rate),
SOC_SINGLE("ALC Capture Switch", ES8326_ALC_RECOVERY, 3, 1, 0),
SOC_SINGLE_TLV("ALC Capture Recovery Level", ES8326_ALC_LEVEL,
0, 4, 0, drc_recovery_tlv),
SOC_ENUM("ALC Capture Winsize", alc_winsize),
SOC_SINGLE_TLV("ALC Capture Target Level", ES8326_ALC_LEVEL,
0, 0x0f, 0, drc_target_tlv),
};
static const struct snd_soc_dapm_widget es8326_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_INPUT("MIC2"),
SND_SOC_DAPM_INPUT("MIC3"),
SND_SOC_DAPM_INPUT("MIC4"),
SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
/* Digital Interface */
SND_SOC_DAPM_AIF_OUT("I2S OUT", "I2S1 Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("I2S IN", "I2S1 Playback", 0, SND_SOC_NOPM, 0, 0),
/* ADC Digital Mute */
SND_SOC_DAPM_PGA("ADC L1", ES8326_ADC_MUTE, 0, 1, NULL, 0),
SND_SOC_DAPM_PGA("ADC R1", ES8326_ADC_MUTE, 1, 1, NULL, 0),
SND_SOC_DAPM_PGA("ADC L2", ES8326_ADC_MUTE, 2, 1, NULL, 0),
SND_SOC_DAPM_PGA("ADC R2", ES8326_ADC_MUTE, 3, 1, NULL, 0),
/* Analog Power Supply*/
SND_SOC_DAPM_DAC("Right DAC", NULL, ES8326_ANA_PDN, 0, 1),
SND_SOC_DAPM_DAC("Left DAC", NULL, ES8326_ANA_PDN, 1, 1),
SND_SOC_DAPM_SUPPLY("MICBIAS1", ES8326_ANA_MICBIAS, 2, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS2", ES8326_ANA_MICBIAS, 3, 0, NULL, 0),
SND_SOC_DAPM_PGA("LHPMIX", ES8326_DAC2HPMIX, 7, 0, NULL, 0),
SND_SOC_DAPM_PGA("RHPMIX", ES8326_DAC2HPMIX, 3, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("HPOL"),
SND_SOC_DAPM_OUTPUT("HPOR"),
};
static const struct snd_soc_dapm_route es8326_dapm_routes[] = {
{"ADC L1", NULL, "MIC1"},
{"ADC R1", NULL, "MIC2"},
{"ADC L2", NULL, "MIC3"},
{"ADC R2", NULL, "MIC4"},
{"ADC L", NULL, "ADC L1"},
{"ADC R", NULL, "ADC R1"},
{"ADC L", NULL, "ADC L2"},
{"ADC R", NULL, "ADC R2"},
{"I2S OUT", NULL, "ADC L"},
{"I2S OUT", NULL, "ADC R"},
{"Right DAC", NULL, "I2S IN"},
{"Left DAC", NULL, "I2S IN"},
{"LHPMIX", NULL, "Left DAC"},
{"RHPMIX", NULL, "Right DAC"},
{"HPOL", NULL, "LHPMIX"},
{"HPOR", NULL, "RHPMIX"},
};
static bool es8326_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case ES8326_HPL_OFFSET_INI:
case ES8326_HPR_OFFSET_INI:
case ES8326_HPDET_STA:
case ES8326_CTIA_OMTP_STA:
case ES8326_CSM_MUTE_STA:
return true;
default:
return false;
}
}
static const struct regmap_config es8326_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = 0xff,
.volatile_reg = es8326_volatile_register,
.cache_type = REGCACHE_RBTREE,
};
struct _coeff_div {
u16 fs;
u32 rate;
u32 mclk;
u8 reg4;
u8 reg5;
u8 reg6;
u8 reg7;
u8 reg8;
u8 reg9;
u8 rega;
u8 regb;
};
/* codec hifi mclk clock divider coefficients */
/* {ratio, LRCK, MCLK, REG04, REG05, REG06, REG07, REG08, REG09, REG10, REG11} */
static const struct _coeff_div coeff_div[] = {
{32, 8000, 256000, 0x60, 0x00, 0x0F, 0x75, 0x0A, 0x1B, 0x1F, 0x7F},
{32, 16000, 512000, 0x20, 0x00, 0x0D, 0x75, 0x0A, 0x1B, 0x1F, 0x3F},
{32, 44100, 1411200, 0x00, 0x00, 0x13, 0x2D, 0x0A, 0x0A, 0x1F, 0x1F},
{32, 48000, 1536000, 0x00, 0x00, 0x13, 0x2D, 0x0A, 0x0A, 0x1F, 0x1F},
{36, 8000, 288000, 0x20, 0x00, 0x0D, 0x75, 0x0A, 0x1B, 0x23, 0x47},
{36, 16000, 576000, 0x20, 0x00, 0x0D, 0x75, 0x0A, 0x1B, 0x23, 0x47},
{48, 8000, 384000, 0x60, 0x02, 0x1F, 0x75, 0x0A, 0x1B, 0x1F, 0x7F},
{48, 16000, 768000, 0x20, 0x02, 0x0F, 0x75, 0x0A, 0x1B, 0x1F, 0x3F},
{48, 48000, 2304000, 0x00, 0x02, 0x0D, 0x2D, 0x0A, 0x0A, 0x1F, 0x1F},
{64, 8000, 512000, 0x60, 0x00, 0x0D, 0x75, 0x0A, 0x1B, 0x1F, 0x7F},
{64, 16000, 1024000, 0x20, 0x00, 0x05, 0x75, 0x0A, 0x1B, 0x1F, 0x3F},
{64, 44100, 2822400, 0x00, 0x00, 0x11, 0x2D, 0x0A, 0x0A, 0x1F, 0x1F},
{64, 48000, 3072000, 0x00, 0x00, 0x11, 0x2D, 0x0A, 0x0A, 0x1F, 0x1F},
{72, 8000, 576000, 0x20, 0x00, 0x13, 0x35, 0x0A, 0x1B, 0x23, 0x47},
{72, 16000, 1152000, 0x20, 0x00, 0x05, 0x75, 0x0A, 0x1B, 0x23, 0x47},
{96, 8000, 768000, 0x60, 0x02, 0x1D, 0x75, 0x0A, 0x1B, 0x1F, 0x7F},
{96, 16000, 1536000, 0x20, 0x02, 0x0D, 0x75, 0x0A, 0x1B, 0x1F, 0x3F},
{100, 48000, 4800000, 0x04, 0x04, 0x3F, 0x6D, 0x38, 0x08, 0x4f, 0x1f},
{125, 48000, 6000000, 0x04, 0x04, 0x1F, 0x2D, 0x0A, 0x0A, 0x27, 0x27},
{128, 8000, 1024000, 0x60, 0x00, 0x13, 0x35, 0x0A, 0x1B, 0x1F, 0x7F},
{128, 16000, 2048000, 0x20, 0x00, 0x11, 0x35, 0x0A, 0x1B, 0x1F, 0x3F},
{128, 44100, 5644800, 0x00, 0x00, 0x01, 0x2D, 0x0A, 0x0A, 0x1F, 0x1F},
{128, 48000, 6144000, 0x00, 0x00, 0x01, 0x2D, 0x0A, 0x0A, 0x1F, 0x1F},
{144, 8000, 1152000, 0x20, 0x00, 0x03, 0x35, 0x0A, 0x1B, 0x23, 0x47},
{144, 16000, 2304000, 0x20, 0x00, 0x11, 0x35, 0x0A, 0x1B, 0x23, 0x47},
{192, 8000, 1536000, 0x60, 0x02, 0x0D, 0x75, 0x0A, 0x1B, 0x1F, 0x7F},
{192, 16000, 3072000, 0x20, 0x02, 0x05, 0x75, 0x0A, 0x1B, 0x1F, 0x3F},
{200, 48000, 9600000, 0x04, 0x04, 0x0F, 0x2D, 0x0A, 0x0A, 0x1F, 0x1F},
{250, 48000, 12000000, 0x04, 0x04, 0x0F, 0x2D, 0x0A, 0x0A, 0x27, 0x27},
{256, 8000, 2048000, 0x60, 0x00, 0x11, 0x35, 0x0A, 0x1B, 0x1F, 0x7F},
{256, 16000, 4096000, 0x20, 0x00, 0x01, 0x35, 0x0A, 0x1B, 0x1F, 0x3F},
{256, 44100, 11289600, 0x00, 0x00, 0x10, 0x2D, 0x0A, 0x0A, 0x1F, 0x1F},
{256, 48000, 12288000, 0x00, 0x00, 0x30, 0x2D, 0x0A, 0x0A, 0x1F, 0x1F},
{288, 8000, 2304000, 0x20, 0x00, 0x01, 0x35, 0x0A, 0x1B, 0x23, 0x47},
{384, 8000, 3072000, 0x60, 0x02, 0x05, 0x75, 0x0A, 0x1B, 0x1F, 0x7F},
{384, 16000, 6144000, 0x20, 0x02, 0x03, 0x35, 0x0A, 0x1B, 0x1F, 0x3F},
{384, 48000, 18432000, 0x00, 0x02, 0x01, 0x2D, 0x0A, 0x0A, 0x1F, 0x1F},
{400, 48000, 19200000, 0x09, 0x04, 0x0f, 0x6d, 0x3a, 0x0A, 0x4F, 0x1F},
{500, 48000, 24000000, 0x18, 0x04, 0x1F, 0x2D, 0x0A, 0x0A, 0x1F, 0x1F},
{512, 8000, 4096000, 0x60, 0x00, 0x01, 0x35, 0x0A, 0x1B, 0x1F, 0x7F},
{512, 16000, 8192000, 0x20, 0x00, 0x10, 0x35, 0x0A, 0x1B, 0x1F, 0x3F},
{512, 44100, 22579200, 0x00, 0x00, 0x00, 0x2D, 0x0A, 0x0A, 0x1F, 0x1F},
{512, 48000, 24576000, 0x00, 0x00, 0x00, 0x2D, 0x0A, 0x0A, 0x1F, 0x1F},
{768, 8000, 6144000, 0x60, 0x02, 0x11, 0x35, 0x0A, 0x1B, 0x1F, 0x7F},
{768, 16000, 12288000, 0x20, 0x02, 0x01, 0x35, 0x0A, 0x1B, 0x1F, 0x3F},
{800, 48000, 38400000, 0x00, 0x18, 0x13, 0x2D, 0x0A, 0x0A, 0x1F, 0x1F},
{1024, 8000, 8192000, 0x60, 0x00, 0x10, 0x35, 0x0A, 0x1B, 0x1F, 0x7F},
{1024, 16000, 16384000, 0x20, 0x00, 0x00, 0x35, 0x0A, 0x1B, 0x1F, 0x3F},
{1152, 16000, 18432000, 0x20, 0x08, 0x11, 0x35, 0x0A, 0x1B, 0x1F, 0x3F},
{1536, 8000, 12288000, 0x60, 0x02, 0x01, 0x35, 0x0A, 0x1B, 0x1F, 0x7F},
{1536, 16000, 24576000, 0x20, 0x02, 0x10, 0x35, 0x0A, 0x1B, 0x1F, 0x3F},
{1625, 8000, 13000000, 0x0C, 0x18, 0x1F, 0x2D, 0x0A, 0x0A, 0x27, 0x27},
{1625, 16000, 26000000, 0x0C, 0x18, 0x1F, 0x2D, 0x0A, 0x0A, 0x27, 0x27},
{2048, 8000, 16384000, 0x60, 0x00, 0x00, 0x35, 0x0A, 0x1B, 0x1F, 0x7F},
{2304, 8000, 18432000, 0x40, 0x02, 0x10, 0x35, 0x0A, 0x1B, 0x1F, 0x5F},
{3072, 8000, 24576000, 0x60, 0x02, 0x10, 0x35, 0x0A, 0x1B, 0x1F, 0x7F},
{3250, 8000, 26000000, 0x0C, 0x18, 0x0F, 0x2D, 0x0A, 0x0A, 0x27, 0x27},
};
static inline int get_coeff(int mclk, int rate)
{
int i;
for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
return i;
}
return -EINVAL;
}
static int es8326_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *codec = codec_dai->component;
struct es8326_priv *es8326 = snd_soc_component_get_drvdata(codec);
es8326->sysclk = freq;
return 0;
}
static int es8326_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
u8 iface = 0;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFP:
snd_soc_component_update_bits(component, ES8326_RESET,
ES8326_MASTER_MODE_EN, ES8326_MASTER_MODE_EN);
break;
case SND_SOC_DAIFMT_CBC_CFC:
break;
default:
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_RIGHT_J:
dev_err(component->dev, "Codec driver does not support right justified\n");
return -EINVAL;
case SND_SOC_DAIFMT_LEFT_J:
iface |= ES8326_DAIFMT_LEFT_J;
break;
case SND_SOC_DAIFMT_DSP_A:
iface |= ES8326_DAIFMT_DSP_A;
break;
case SND_SOC_DAIFMT_DSP_B:
iface |= ES8326_DAIFMT_DSP_B;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, ES8326_FMT, ES8326_DAIFMT_MASK, iface);
return 0;
}
static int es8326_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
u8 srate = 0;
int coeff;
coeff = get_coeff(es8326->sysclk, params_rate(params));
/* bit size */
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
srate |= ES8326_S16_LE;
break;
case SNDRV_PCM_FORMAT_S20_3LE:
srate |= ES8326_S20_3_LE;
break;
case SNDRV_PCM_FORMAT_S18_3LE:
srate |= ES8326_S18_LE;
break;
case SNDRV_PCM_FORMAT_S24_LE:
srate |= ES8326_S24_LE;
break;
case SNDRV_PCM_FORMAT_S32_LE:
srate |= ES8326_S32_LE;
break;
default:
return -EINVAL;
}
/* set iface & srate */
snd_soc_component_update_bits(component, ES8326_FMT, ES8326_DATA_LEN_MASK, srate);
if (coeff >= 0) {
regmap_write(es8326->regmap, ES8326_CLK_DIV1,
coeff_div[coeff].reg4);
regmap_write(es8326->regmap, ES8326_CLK_DIV2,
coeff_div[coeff].reg5);
regmap_write(es8326->regmap, ES8326_CLK_DLL,
coeff_div[coeff].reg6);
regmap_write(es8326->regmap, ES8326_CLK_MUX,
coeff_div[coeff].reg7);
regmap_write(es8326->regmap, ES8326_CLK_ADC_SEL,
coeff_div[coeff].reg8);
regmap_write(es8326->regmap, ES8326_CLK_DAC_SEL,
coeff_div[coeff].reg9);
regmap_write(es8326->regmap, ES8326_CLK_ADC_OSR,
coeff_div[coeff].rega);
regmap_write(es8326->regmap, ES8326_CLK_DAC_OSR,
coeff_div[coeff].regb);
} else {
dev_warn(component->dev, "Clock coefficients do not match");
}
return 0;
}
static int es8326_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
unsigned int offset_l, offset_r;
if (mute) {
regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_OFF);
regmap_update_bits(es8326->regmap, ES8326_DAC_MUTE,
ES8326_MUTE_MASK, ES8326_MUTE);
regmap_write(es8326->regmap, ES8326_HP_DRIVER, 0xf0);
} else {
if (!es8326->calibrated) {
regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_FORCE_CAL);
msleep(30);
regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_OFF);
regmap_read(es8326->regmap, ES8326_HPL_OFFSET_INI, &offset_l);
regmap_read(es8326->regmap, ES8326_HPR_OFFSET_INI, &offset_r);
regmap_write(es8326->regmap, ES8326_HP_OFFSET_CAL, 0x8c);
regmap_write(es8326->regmap, ES8326_HPL_OFFSET_INI, offset_l);
regmap_write(es8326->regmap, ES8326_HPR_OFFSET_INI, offset_r);
es8326->calibrated = true;
}
regmap_write(es8326->regmap, ES8326_HP_DRIVER, 0xa0);
regmap_write(es8326->regmap, ES8326_HP_VOL, 0x80);
regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_ON);
regmap_update_bits(es8326->regmap, ES8326_DAC_MUTE,
ES8326_MUTE_MASK, ~(ES8326_MUTE));
}
return 0;
}
static int es8326_set_bias_level(struct snd_soc_component *codec,
enum snd_soc_bias_level level)
{
struct es8326_priv *es8326 = snd_soc_component_get_drvdata(codec);
int ret;
switch (level) {
case SND_SOC_BIAS_ON:
ret = clk_prepare_enable(es8326->mclk);
if (ret)
return ret;
regmap_write(es8326->regmap, ES8326_RESET, 0x9f);
msleep(20);
regmap_update_bits(es8326->regmap, ES8326_DAC_DSM, 0x01, 0x00);
regmap_write(es8326->regmap, ES8326_INTOUT_IO, es8326->interrupt_clk);
regmap_write(es8326->regmap, ES8326_SDINOUT1_IO,
(ES8326_IO_DMIC_CLK << ES8326_SDINOUT1_SHIFT));
regmap_write(es8326->regmap, ES8326_VMIDSEL, 0x0E);
regmap_write(es8326->regmap, ES8326_PGA_PDN, 0x40);
regmap_write(es8326->regmap, ES8326_ANA_PDN, 0x00);
regmap_update_bits(es8326->regmap, ES8326_CLK_CTL, 0x20, 0x20);
regmap_write(es8326->regmap, ES8326_RESET, ES8326_CSM_ON);
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
break;
case SND_SOC_BIAS_OFF:
clk_disable_unprepare(es8326->mclk);
regmap_write(es8326->regmap, ES8326_ANA_PDN, 0x3b);
regmap_write(es8326->regmap, ES8326_VMIDSEL, 0x00);
regmap_update_bits(es8326->regmap, ES8326_CLK_CTL, 0x20, 0x00);
regmap_write(es8326->regmap, ES8326_SDINOUT1_IO, ES8326_IO_INPUT);
break;
}
return 0;
}
#define es8326_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE)
static const struct snd_soc_dai_ops es8326_ops = {
.hw_params = es8326_pcm_hw_params,
.set_fmt = es8326_set_dai_fmt,
.set_sysclk = es8326_set_dai_sysclk,
.mute_stream = es8326_mute,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver es8326_dai = {
.name = "ES8326 HiFi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = es8326_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = es8326_FORMATS,
},
.ops = &es8326_ops,
.symmetric_rate = 1,
};
static void es8326_enable_micbias(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
snd_soc_dapm_mutex_lock(dapm);
snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS1");
snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS2");
snd_soc_dapm_sync_unlocked(dapm);
snd_soc_dapm_mutex_unlock(dapm);
}
static void es8326_disable_micbias(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
snd_soc_dapm_mutex_lock(dapm);
snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS1");
snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS2");
snd_soc_dapm_sync_unlocked(dapm);
snd_soc_dapm_mutex_unlock(dapm);
}
/*
* For button detection, set the following in soundcard
* snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
* snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOLUMEUP);
* snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEDOWN);
*/
static void es8326_jack_button_handler(struct work_struct *work)
{
struct es8326_priv *es8326 =
container_of(work, struct es8326_priv, button_press_work.work);
struct snd_soc_component *comp = es8326->component;
unsigned int iface;
static int button_to_report, press_count;
static int prev_button, cur_button;
if (!(es8326->jack->status & SND_JACK_HEADSET)) /* Jack unplugged */
return;
mutex_lock(&es8326->lock);
iface = snd_soc_component_read(comp, ES8326_HPDET_STA);
switch (iface) {
case 0x93:
/* pause button detected */
cur_button = SND_JACK_BTN_0;
break;
case 0x6f:
case 0x4b:
/* button volume up */
cur_button = SND_JACK_BTN_1;
break;
case 0x27:
/* button volume down */
cur_button = SND_JACK_BTN_2;
break;
case 0x1e:
case 0xe2:
/* button released or not pressed */
cur_button = 0;
break;
default:
break;
}
if ((prev_button == cur_button) && (cur_button != 0)) {
press_count++;
if (press_count > 3) {
/* report a press every 120ms */
snd_soc_jack_report(es8326->jack, cur_button,
SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2);
press_count = 0;
}
button_to_report = cur_button;
queue_delayed_work(system_wq, &es8326->button_press_work,
msecs_to_jiffies(35));
} else if (prev_button != cur_button) {
/* mismatch, detect again */
prev_button = cur_button;
queue_delayed_work(system_wq, &es8326->button_press_work,
msecs_to_jiffies(35));
} else {
/* released or no pressed */
if (button_to_report != 0) {
snd_soc_jack_report(es8326->jack, button_to_report,
SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2);
snd_soc_jack_report(es8326->jack, 0,
SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2);
button_to_report = 0;
}
}
mutex_unlock(&es8326->lock);
}
static void es8326_jack_detect_handler(struct work_struct *work)
{
struct es8326_priv *es8326 =
container_of(work, struct es8326_priv, jack_detect_work.work);
struct snd_soc_component *comp = es8326->component;
unsigned int iface;
mutex_lock(&es8326->lock);
iface = snd_soc_component_read(comp, ES8326_HPDET_STA);
dev_dbg(comp->dev, "gpio flag %#04x", iface);
if (es8326->jack_remove_retry == 1) {
if (iface & ES8326_HPINSERT_FLAG)
es8326->jack_remove_retry = 2;
else
es8326->jack_remove_retry = 0;
dev_dbg(comp->dev, "remove event check, set HPJACK_POL normal, cnt = %d\n",
es8326->jack_remove_retry);
/*
* Inverted HPJACK_POL bit to trigger one IRQ to double check HP Removal event
*/
regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE,
ES8326_HP_DET_JACK_POL, (es8326->jd_inverted ?
~es8326->jack_pol : es8326->jack_pol));
goto exit;
}
if ((iface & ES8326_HPINSERT_FLAG) == 0) {
/* Jack unplugged or spurious IRQ */
dev_dbg(comp->dev, "No headset detected\n");
es8326_disable_micbias(es8326->component);
if (es8326->jack->status & SND_JACK_HEADPHONE) {
dev_dbg(comp->dev, "Report hp remove event\n");
snd_soc_jack_report(es8326->jack, 0, SND_JACK_HEADSET);
/* mute adc when mic path switch */
regmap_write(es8326->regmap, ES8326_ADC_SCALE, 0x33);
regmap_write(es8326->regmap, ES8326_ADC1_SRC, 0x44);
regmap_write(es8326->regmap, ES8326_ADC2_SRC, 0x66);
es8326->hp = 0;
}
regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 0x03, 0x01);
/*
* Inverted HPJACK_POL bit to trigger one IRQ to double check HP Removal event
*/
if (es8326->jack_remove_retry == 0) {
es8326->jack_remove_retry = 1;
dev_dbg(comp->dev, "remove event check, invert HPJACK_POL, cnt = %d\n",
es8326->jack_remove_retry);
regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE,
ES8326_HP_DET_JACK_POL, (es8326->jd_inverted ?
es8326->jack_pol : ~es8326->jack_pol));
} else {
es8326->jack_remove_retry = 0;
}
} else if ((iface & ES8326_HPINSERT_FLAG) == ES8326_HPINSERT_FLAG) {
es8326->jack_remove_retry = 0;
if (es8326->hp == 0) {
dev_dbg(comp->dev, "First insert, start OMTP/CTIA type check\n");
/*
* set auto-check mode, then restart jack_detect_work after 100ms.
* Don't report jack status.
*/
regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 0x03, 0x01);
usleep_range(50000, 70000);
regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 0x03, 0x00);
queue_delayed_work(system_wq, &es8326->jack_detect_work,
msecs_to_jiffies(100));
es8326->hp = 1;
goto exit;
}
if (es8326->jack->status & SND_JACK_HEADSET) {
/* detect button */
dev_dbg(comp->dev, "button pressed\n");
queue_delayed_work(system_wq, &es8326->button_press_work, 10);
goto exit;
}
if ((iface & ES8326_HPBUTTON_FLAG) == 0x01) {
dev_dbg(comp->dev, "Headphone detected\n");
snd_soc_jack_report(es8326->jack,
SND_JACK_HEADPHONE, SND_JACK_HEADSET);
} else {
dev_dbg(comp->dev, "Headset detected\n");
snd_soc_jack_report(es8326->jack,
SND_JACK_HEADSET, SND_JACK_HEADSET);
regmap_write(es8326->regmap, ES8326_ADC_SCALE, 0x33);
regmap_update_bits(es8326->regmap, ES8326_PGA_PDN,
0x08, 0x08);
regmap_update_bits(es8326->regmap, ES8326_PGAGAIN,
0x80, 0x80);
regmap_write(es8326->regmap, ES8326_ADC1_SRC, 0x00);
regmap_write(es8326->regmap, ES8326_ADC2_SRC, 0x00);
regmap_update_bits(es8326->regmap, ES8326_PGA_PDN,
0x08, 0x00);
usleep_range(10000, 15000);
}
}
exit:
mutex_unlock(&es8326->lock);
}
static irqreturn_t es8326_irq(int irq, void *dev_id)
{
struct es8326_priv *es8326 = dev_id;
struct snd_soc_component *comp = es8326->component;
if (!es8326->jack)
goto out;
es8326_enable_micbias(comp);
if (es8326->jack->status & SND_JACK_HEADSET)
queue_delayed_work(system_wq, &es8326->jack_detect_work,
msecs_to_jiffies(10));
else
queue_delayed_work(system_wq, &es8326->jack_detect_work,
msecs_to_jiffies(600));
out:
return IRQ_HANDLED;
}
static int es8326_calibrate(struct snd_soc_component *component)
{
struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
unsigned int reg;
unsigned int offset_l, offset_r;
regmap_read(es8326->regmap, ES8326_CHIP_VERSION, ®);
es8326->version = reg;
if ((es8326->version == ES8326_VERSION_B) && (es8326->calibrated == false)) {
dev_dbg(component->dev, "ES8326_VERSION_B, calibrating\n");
regmap_write(es8326->regmap, ES8326_CLK_INV, 0xc0);
regmap_write(es8326->regmap, ES8326_CLK_DIV1, 0x01);
regmap_write(es8326->regmap, ES8326_CLK_DLL, 0x30);
regmap_write(es8326->regmap, ES8326_CLK_MUX, 0xed);
regmap_write(es8326->regmap, ES8326_CLK_TRI, 0xc1);
regmap_write(es8326->regmap, ES8326_DAC_MUTE, 0x03);
regmap_write(es8326->regmap, ES8326_ANA_VSEL, 0x7f);
regmap_write(es8326->regmap, ES8326_VMIDLOW, 0x33);
regmap_write(es8326->regmap, ES8326_DAC2HPMIX, 0x88);
regmap_write(es8326->regmap, ES8326_HP_VOL, 0x80);
regmap_write(es8326->regmap, ES8326_HP_OFFSET_CAL, 0x8c);
regmap_write(es8326->regmap, ES8326_RESET, 0xc0);
usleep_range(15000, 20000);
regmap_write(es8326->regmap, ES8326_HP_OFFSET_CAL, ES8326_HP_OFF);
regmap_read(es8326->regmap, ES8326_CSM_MUTE_STA, ®);
if ((reg & 0xf0) != 0x40)
msleep(50);
regmap_write(es8326->regmap, ES8326_HP_CAL, 0xd4);
msleep(200);
regmap_write(es8326->regmap, ES8326_HP_CAL, 0x4d);
msleep(200);
regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_OFF);
regmap_read(es8326->regmap, ES8326_HPL_OFFSET_INI, &offset_l);
regmap_read(es8326->regmap, ES8326_HPR_OFFSET_INI, &offset_r);
regmap_write(es8326->regmap, ES8326_HP_OFFSET_CAL, 0x8c);
regmap_write(es8326->regmap, ES8326_HPL_OFFSET_INI, offset_l);
regmap_write(es8326->regmap, ES8326_HPR_OFFSET_INI, offset_r);
regmap_write(es8326->regmap, ES8326_CLK_INV, 0x00);
es8326->calibrated = true;
}
return 0;
}
static int es8326_resume(struct snd_soc_component *component)
{
struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
regcache_cache_only(es8326->regmap, false);
regcache_sync(es8326->regmap);
/* reset internal clock state */
regmap_write(es8326->regmap, ES8326_RESET, 0x1f);
regmap_write(es8326->regmap, ES8326_VMIDSEL, 0x0E);
usleep_range(10000, 15000);
regmap_write(es8326->regmap, ES8326_HPJACK_TIMER, 0x88);
/* set headphone default type and detect pin */
regmap_write(es8326->regmap, ES8326_HPDET_TYPE, 0x81);
regmap_write(es8326->regmap, ES8326_CLK_RESAMPLE, 0x05);
/* set internal oscillator as clock source of headpone cp */
regmap_write(es8326->regmap, ES8326_CLK_DIV_CPC, 0x84);
regmap_write(es8326->regmap, ES8326_CLK_CTL, ES8326_CLK_ON);
/* clock manager reset release */
regmap_write(es8326->regmap, ES8326_RESET, 0x17);
/* set headphone detection as half scan mode */
regmap_write(es8326->regmap, ES8326_HP_MISC, 0x08);
regmap_write(es8326->regmap, ES8326_PULLUP_CTL, 0x00);
/* enable headphone driver */
regmap_write(es8326->regmap, ES8326_HP_DRIVER, 0xa7);
usleep_range(2000, 5000);
regmap_write(es8326->regmap, ES8326_HP_DRIVER_REF, 0xab);
usleep_range(2000, 5000);
regmap_write(es8326->regmap, ES8326_HP_DRIVER_REF, 0xbb);
usleep_range(2000, 5000);
regmap_write(es8326->regmap, ES8326_HP_DRIVER, 0xa1);
regmap_write(es8326->regmap, ES8326_CLK_INV, 0x00);
regmap_write(es8326->regmap, ES8326_CLK_VMIDS1, 0xc4);
regmap_write(es8326->regmap, ES8326_CLK_VMIDS2, 0x81);
regmap_write(es8326->regmap, ES8326_CLK_CAL_TIME, 0x00);
/* calibrate for B version */
es8326_calibrate(component);
/* turn off headphone out */
regmap_write(es8326->regmap, ES8326_HP_CAL, 0x00);
/* set ADC and DAC in low power mode */
regmap_write(es8326->regmap, ES8326_ANA_LP, 0xf0);
/* force micbias on */
regmap_write(es8326->regmap, ES8326_ANA_MICBIAS, 0x4f);
regmap_write(es8326->regmap, ES8326_SYS_BIAS, 0x08);
regmap_write(es8326->regmap, ES8326_ANA_VSEL, 0x7F);
/* select vdda as micbias source */
regmap_write(es8326->regmap, ES8326_VMIDLOW, 0x23);
/* set dac dsmclip = 1 */
regmap_write(es8326->regmap, ES8326_DAC_DSM, 0x08);
regmap_write(es8326->regmap, ES8326_DAC_VPPSCALE, 0x15);
regmap_write(es8326->regmap, ES8326_INT_SOURCE,
(ES8326_INT_SRC_PIN9 | ES8326_INT_SRC_BUTTON));
regmap_write(es8326->regmap, ES8326_INTOUT_IO,
es8326->interrupt_clk);
regmap_write(es8326->regmap, ES8326_SDINOUT1_IO,
(ES8326_IO_DMIC_CLK << ES8326_SDINOUT1_SHIFT));
regmap_write(es8326->regmap, ES8326_SDINOUT23_IO, ES8326_IO_INPUT);
regmap_write(es8326->regmap, ES8326_ANA_PDN, 0x3b);
regmap_write(es8326->regmap, ES8326_RESET, ES8326_CSM_ON);
regmap_update_bits(es8326->regmap, ES8326_PGAGAIN, ES8326_MIC_SEL_MASK,
ES8326_MIC1_SEL);
regmap_update_bits(es8326->regmap, ES8326_DAC_MUTE, ES8326_MUTE_MASK,
ES8326_MUTE);
regmap_write(es8326->regmap, ES8326_HPDET_TYPE, 0x80 |
((es8326->version == ES8326_VERSION_B) ?
(ES8326_HP_DET_SRC_PIN9 | es8326->jack_pol) :
(ES8326_HP_DET_SRC_PIN9 | es8326->jack_pol | 0x04)));
es8326->jack_remove_retry = 0;
es8326->hp = 0;
return 0;
}
static int es8326_suspend(struct snd_soc_component *component)
{
struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
cancel_delayed_work_sync(&es8326->jack_detect_work);
es8326_disable_micbias(component);
es8326->calibrated = false;
regmap_write(es8326->regmap, ES8326_CLK_CTL, ES8326_CLK_OFF);
regcache_cache_only(es8326->regmap, true);
regcache_mark_dirty(es8326->regmap);
/* reset register value to default */
regmap_write(es8326->regmap, ES8326_CSM_I2C_STA, 0x01);
usleep_range(1000, 3000);
regmap_write(es8326->regmap, ES8326_CSM_I2C_STA, 0x00);
return 0;
}
static int es8326_probe(struct snd_soc_component *component)
{
struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
int ret;
es8326->component = component;
es8326->jd_inverted = device_property_read_bool(component->dev,
"everest,jack-detect-inverted");
ret = device_property_read_u8(component->dev, "everest,mic1-src", &es8326->mic1_src);
if (ret != 0) {
dev_dbg(component->dev, "mic1-src return %d", ret);
es8326->mic1_src = ES8326_ADC_AMIC;
}
dev_dbg(component->dev, "mic1-src %x", es8326->mic1_src);
ret = device_property_read_u8(component->dev, "everest,mic2-src", &es8326->mic2_src);
if (ret != 0) {
dev_dbg(component->dev, "mic2-src return %d", ret);
es8326->mic2_src = ES8326_ADC_DMIC;
}
dev_dbg(component->dev, "mic2-src %x", es8326->mic2_src);
ret = device_property_read_u8(component->dev, "everest,jack-pol", &es8326->jack_pol);
if (ret != 0) {
dev_dbg(component->dev, "jack-pol return %d", ret);
es8326->jack_pol = ES8326_HP_TYPE_AUTO;
}
dev_dbg(component->dev, "jack-pol %x", es8326->jack_pol);
ret = device_property_read_u8(component->dev, "everest,interrupt-src",
&es8326->interrupt_src);
if (ret != 0) {
dev_dbg(component->dev, "interrupt-src return %d", ret);
es8326->interrupt_src = ES8326_HP_DET_SRC_PIN9;
}
dev_dbg(component->dev, "interrupt-src %x", es8326->interrupt_src);
ret = device_property_read_u8(component->dev, "everest,interrupt-clk",
&es8326->interrupt_clk);
if (ret != 0) {
dev_dbg(component->dev, "interrupt-clk return %d", ret);
es8326->interrupt_clk = 0x45;
}
dev_dbg(component->dev, "interrupt-clk %x", es8326->interrupt_clk);
es8326_resume(component);
return 0;
}
static void es8326_enable_jack_detect(struct snd_soc_component *component,
struct snd_soc_jack *jack)
{
struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
mutex_lock(&es8326->lock);
if (es8326->jd_inverted)
snd_soc_component_update_bits(component, ES8326_HPDET_TYPE,
ES8326_HP_DET_JACK_POL, ~es8326->jack_pol);
es8326->jack = jack;
mutex_unlock(&es8326->lock);
es8326_irq(es8326->irq, es8326);
}
static void es8326_disable_jack_detect(struct snd_soc_component *component)
{
struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
dev_dbg(component->dev, "Enter into %s\n", __func__);
if (!es8326->jack)
return; /* Already disabled (or never enabled) */
cancel_delayed_work_sync(&es8326->jack_detect_work);
mutex_lock(&es8326->lock);
if (es8326->jack->status & SND_JACK_MICROPHONE) {
es8326_disable_micbias(component);
snd_soc_jack_report(es8326->jack, 0, SND_JACK_HEADSET);
}
es8326->jack = NULL;
mutex_unlock(&es8326->lock);
}
static int es8326_set_jack(struct snd_soc_component *component,
struct snd_soc_jack *jack, void *data)
{
if (jack)
es8326_enable_jack_detect(component, jack);
else
es8326_disable_jack_detect(component);
return 0;
}
static void es8326_remove(struct snd_soc_component *component)
{
es8326_disable_jack_detect(component);
es8326_set_bias_level(component, SND_SOC_BIAS_OFF);
}
static const struct snd_soc_component_driver soc_component_dev_es8326 = {
.probe = es8326_probe,
.remove = es8326_remove,
.resume = es8326_resume,
.suspend = es8326_suspend,
.set_bias_level = es8326_set_bias_level,
.set_jack = es8326_set_jack,
.dapm_widgets = es8326_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(es8326_dapm_widgets),
.dapm_routes = es8326_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(es8326_dapm_routes),
.controls = es8326_snd_controls,
.num_controls = ARRAY_SIZE(es8326_snd_controls),
.use_pmdown_time = 1,
.endianness = 1,
};
static int es8326_i2c_probe(struct i2c_client *i2c)
{
struct es8326_priv *es8326;
int ret;
es8326 = devm_kzalloc(&i2c->dev, sizeof(struct es8326_priv), GFP_KERNEL);
if (!es8326)
return -ENOMEM;
i2c_set_clientdata(i2c, es8326);
es8326->i2c = i2c;
mutex_init(&es8326->lock);
es8326->regmap = devm_regmap_init_i2c(i2c, &es8326_regmap_config);
if (IS_ERR(es8326->regmap)) {
ret = PTR_ERR(es8326->regmap);
dev_err(&i2c->dev, "Failed to init regmap: %d\n", ret);
return ret;
}
es8326->irq = i2c->irq;
INIT_DELAYED_WORK(&es8326->jack_detect_work,
es8326_jack_detect_handler);
INIT_DELAYED_WORK(&es8326->button_press_work,
es8326_jack_button_handler);
/* ES8316 is level-based while ES8326 is edge-based */
ret = devm_request_threaded_irq(&i2c->dev, es8326->irq, NULL, es8326_irq,
IRQF_TRIGGER_RISING | IRQF_ONESHOT,
"es8326", es8326);
if (ret) {
dev_warn(&i2c->dev, "Failed to request IRQ: %d: %d\n",
es8326->irq, ret);
es8326->irq = -ENXIO;
}
es8326->mclk = devm_clk_get_optional(&i2c->dev, "mclk");
if (IS_ERR(es8326->mclk)) {
dev_err(&i2c->dev, "unable to get mclk\n");
return PTR_ERR(es8326->mclk);
}
if (!es8326->mclk)
dev_warn(&i2c->dev, "assuming static mclk\n");
ret = clk_prepare_enable(es8326->mclk);
if (ret) {
dev_err(&i2c->dev, "unable to enable mclk\n");
return ret;
}
return devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_es8326,
&es8326_dai, 1);
}
static const struct i2c_device_id es8326_i2c_id[] = {
{"es8326", 0 },
{}
};
MODULE_DEVICE_TABLE(i2c, es8326_i2c_id);
#ifdef CONFIG_OF
static const struct of_device_id es8326_of_match[] = {
{ .compatible = "everest,es8326", },
{}
};
MODULE_DEVICE_TABLE(of, es8326_of_match);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id es8326_acpi_match[] = {
{"ESSX8326", 0},
{},
};
MODULE_DEVICE_TABLE(acpi, es8326_acpi_match);
#endif
static struct i2c_driver es8326_i2c_driver = {
.driver = {
.name = "es8326",
.acpi_match_table = ACPI_PTR(es8326_acpi_match),
.of_match_table = of_match_ptr(es8326_of_match),
},
.probe = es8326_i2c_probe,
.id_table = es8326_i2c_id,
};
module_i2c_driver(es8326_i2c_driver);
MODULE_DESCRIPTION("ASoC es8326 driver");
MODULE_AUTHOR("David Yang <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/es8326.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm9081.c -- WM9081 ALSA SoC Audio driver
*
* Author: Mark Brown
*
* Copyright 2009-12 Wolfson Microelectronics plc
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/wm9081.h>
#include "wm9081.h"
static const struct reg_default wm9081_reg[] = {
{ 2, 0x00B9 }, /* R2 - Analogue Lineout */
{ 3, 0x00B9 }, /* R3 - Analogue Speaker PGA */
{ 4, 0x0001 }, /* R4 - VMID Control */
{ 5, 0x0068 }, /* R5 - Bias Control 1 */
{ 7, 0x0000 }, /* R7 - Analogue Mixer */
{ 8, 0x0000 }, /* R8 - Anti Pop Control */
{ 9, 0x01DB }, /* R9 - Analogue Speaker 1 */
{ 10, 0x0018 }, /* R10 - Analogue Speaker 2 */
{ 11, 0x0180 }, /* R11 - Power Management */
{ 12, 0x0000 }, /* R12 - Clock Control 1 */
{ 13, 0x0038 }, /* R13 - Clock Control 2 */
{ 14, 0x4000 }, /* R14 - Clock Control 3 */
{ 16, 0x0000 }, /* R16 - FLL Control 1 */
{ 17, 0x0200 }, /* R17 - FLL Control 2 */
{ 18, 0x0000 }, /* R18 - FLL Control 3 */
{ 19, 0x0204 }, /* R19 - FLL Control 4 */
{ 20, 0x0000 }, /* R20 - FLL Control 5 */
{ 22, 0x0000 }, /* R22 - Audio Interface 1 */
{ 23, 0x0002 }, /* R23 - Audio Interface 2 */
{ 24, 0x0008 }, /* R24 - Audio Interface 3 */
{ 25, 0x0022 }, /* R25 - Audio Interface 4 */
{ 27, 0x0006 }, /* R27 - Interrupt Status Mask */
{ 28, 0x0000 }, /* R28 - Interrupt Polarity */
{ 29, 0x0000 }, /* R29 - Interrupt Control */
{ 30, 0x00C0 }, /* R30 - DAC Digital 1 */
{ 31, 0x0008 }, /* R31 - DAC Digital 2 */
{ 32, 0x09AF }, /* R32 - DRC 1 */
{ 33, 0x4201 }, /* R33 - DRC 2 */
{ 34, 0x0000 }, /* R34 - DRC 3 */
{ 35, 0x0000 }, /* R35 - DRC 4 */
{ 38, 0x0000 }, /* R38 - Write Sequencer 1 */
{ 39, 0x0000 }, /* R39 - Write Sequencer 2 */
{ 40, 0x0002 }, /* R40 - MW Slave 1 */
{ 42, 0x0000 }, /* R42 - EQ 1 */
{ 43, 0x0000 }, /* R43 - EQ 2 */
{ 44, 0x0FCA }, /* R44 - EQ 3 */
{ 45, 0x0400 }, /* R45 - EQ 4 */
{ 46, 0x00B8 }, /* R46 - EQ 5 */
{ 47, 0x1EB5 }, /* R47 - EQ 6 */
{ 48, 0xF145 }, /* R48 - EQ 7 */
{ 49, 0x0B75 }, /* R49 - EQ 8 */
{ 50, 0x01C5 }, /* R50 - EQ 9 */
{ 51, 0x169E }, /* R51 - EQ 10 */
{ 52, 0xF829 }, /* R52 - EQ 11 */
{ 53, 0x07AD }, /* R53 - EQ 12 */
{ 54, 0x1103 }, /* R54 - EQ 13 */
{ 55, 0x1C58 }, /* R55 - EQ 14 */
{ 56, 0xF373 }, /* R56 - EQ 15 */
{ 57, 0x0A54 }, /* R57 - EQ 16 */
{ 58, 0x0558 }, /* R58 - EQ 17 */
{ 59, 0x0564 }, /* R59 - EQ 18 */
{ 60, 0x0559 }, /* R60 - EQ 19 */
{ 61, 0x4000 }, /* R61 - EQ 20 */
};
static struct {
int ratio;
int clk_sys_rate;
} clk_sys_rates[] = {
{ 64, 0 },
{ 128, 1 },
{ 192, 2 },
{ 256, 3 },
{ 384, 4 },
{ 512, 5 },
{ 768, 6 },
{ 1024, 7 },
{ 1408, 8 },
{ 1536, 9 },
};
static struct {
int rate;
int sample_rate;
} sample_rates[] = {
{ 8000, 0 },
{ 11025, 1 },
{ 12000, 2 },
{ 16000, 3 },
{ 22050, 4 },
{ 24000, 5 },
{ 32000, 6 },
{ 44100, 7 },
{ 48000, 8 },
{ 88200, 9 },
{ 96000, 10 },
};
static struct {
int div; /* *10 due to .5s */
int bclk_div;
} bclk_divs[] = {
{ 10, 0 },
{ 15, 1 },
{ 20, 2 },
{ 30, 3 },
{ 40, 4 },
{ 50, 5 },
{ 55, 6 },
{ 60, 7 },
{ 80, 8 },
{ 100, 9 },
{ 110, 10 },
{ 120, 11 },
{ 160, 12 },
{ 200, 13 },
{ 220, 14 },
{ 240, 15 },
{ 250, 16 },
{ 300, 17 },
{ 320, 18 },
{ 440, 19 },
{ 480, 20 },
};
struct wm9081_priv {
struct regmap *regmap;
int sysclk_source;
int mclk_rate;
int sysclk_rate;
int fs;
int bclk;
int master;
int fll_fref;
int fll_fout;
int tdm_width;
struct wm9081_pdata pdata;
};
static bool wm9081_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM9081_SOFTWARE_RESET:
case WM9081_INTERRUPT_STATUS:
return true;
default:
return false;
}
}
static bool wm9081_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM9081_SOFTWARE_RESET:
case WM9081_ANALOGUE_LINEOUT:
case WM9081_ANALOGUE_SPEAKER_PGA:
case WM9081_VMID_CONTROL:
case WM9081_BIAS_CONTROL_1:
case WM9081_ANALOGUE_MIXER:
case WM9081_ANTI_POP_CONTROL:
case WM9081_ANALOGUE_SPEAKER_1:
case WM9081_ANALOGUE_SPEAKER_2:
case WM9081_POWER_MANAGEMENT:
case WM9081_CLOCK_CONTROL_1:
case WM9081_CLOCK_CONTROL_2:
case WM9081_CLOCK_CONTROL_3:
case WM9081_FLL_CONTROL_1:
case WM9081_FLL_CONTROL_2:
case WM9081_FLL_CONTROL_3:
case WM9081_FLL_CONTROL_4:
case WM9081_FLL_CONTROL_5:
case WM9081_AUDIO_INTERFACE_1:
case WM9081_AUDIO_INTERFACE_2:
case WM9081_AUDIO_INTERFACE_3:
case WM9081_AUDIO_INTERFACE_4:
case WM9081_INTERRUPT_STATUS:
case WM9081_INTERRUPT_STATUS_MASK:
case WM9081_INTERRUPT_POLARITY:
case WM9081_INTERRUPT_CONTROL:
case WM9081_DAC_DIGITAL_1:
case WM9081_DAC_DIGITAL_2:
case WM9081_DRC_1:
case WM9081_DRC_2:
case WM9081_DRC_3:
case WM9081_DRC_4:
case WM9081_WRITE_SEQUENCER_1:
case WM9081_WRITE_SEQUENCER_2:
case WM9081_MW_SLAVE_1:
case WM9081_EQ_1:
case WM9081_EQ_2:
case WM9081_EQ_3:
case WM9081_EQ_4:
case WM9081_EQ_5:
case WM9081_EQ_6:
case WM9081_EQ_7:
case WM9081_EQ_8:
case WM9081_EQ_9:
case WM9081_EQ_10:
case WM9081_EQ_11:
case WM9081_EQ_12:
case WM9081_EQ_13:
case WM9081_EQ_14:
case WM9081_EQ_15:
case WM9081_EQ_16:
case WM9081_EQ_17:
case WM9081_EQ_18:
case WM9081_EQ_19:
case WM9081_EQ_20:
return true;
default:
return false;
}
}
static int wm9081_reset(struct regmap *map)
{
return regmap_write(map, WM9081_SOFTWARE_RESET, 0x9081);
}
static const DECLARE_TLV_DB_SCALE(drc_in_tlv, -4500, 75, 0);
static const DECLARE_TLV_DB_SCALE(drc_out_tlv, -2250, 75, 0);
static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
static const DECLARE_TLV_DB_RANGE(drc_max_tlv,
0, 0, TLV_DB_SCALE_ITEM(1200, 0, 0),
1, 1, TLV_DB_SCALE_ITEM(1800, 0, 0),
2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0)
);
static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -300, 50, 0);
static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
static const DECLARE_TLV_DB_SCALE(in_tlv, -600, 600, 0);
static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
static const char *drc_high_text[] = {
"1",
"1/2",
"1/4",
"1/8",
"1/16",
"0",
};
static SOC_ENUM_SINGLE_DECL(drc_high, WM9081_DRC_3, 3, drc_high_text);
static const char *drc_low_text[] = {
"1",
"1/2",
"1/4",
"1/8",
"0",
};
static SOC_ENUM_SINGLE_DECL(drc_low, WM9081_DRC_3, 0, drc_low_text);
static const char *drc_atk_text[] = {
"181us",
"181us",
"363us",
"726us",
"1.45ms",
"2.9ms",
"5.8ms",
"11.6ms",
"23.2ms",
"46.4ms",
"92.8ms",
"185.6ms",
};
static SOC_ENUM_SINGLE_DECL(drc_atk, WM9081_DRC_2, 12, drc_atk_text);
static const char *drc_dcy_text[] = {
"186ms",
"372ms",
"743ms",
"1.49s",
"2.97s",
"5.94s",
"11.89s",
"23.78s",
"47.56s",
};
static SOC_ENUM_SINGLE_DECL(drc_dcy, WM9081_DRC_2, 8, drc_dcy_text);
static const char *drc_qr_dcy_text[] = {
"0.725ms",
"1.45ms",
"5.8ms",
};
static SOC_ENUM_SINGLE_DECL(drc_qr_dcy, WM9081_DRC_2, 4, drc_qr_dcy_text);
static const char *dac_deemph_text[] = {
"None",
"32kHz",
"44.1kHz",
"48kHz",
};
static SOC_ENUM_SINGLE_DECL(dac_deemph, WM9081_DAC_DIGITAL_2, 1,
dac_deemph_text);
static const char *speaker_mode_text[] = {
"Class D",
"Class AB",
};
static SOC_ENUM_SINGLE_DECL(speaker_mode, WM9081_ANALOGUE_SPEAKER_2, 6,
speaker_mode_text);
static int speaker_mode_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
unsigned int reg;
reg = snd_soc_component_read(component, WM9081_ANALOGUE_SPEAKER_2);
if (reg & WM9081_SPK_MODE)
ucontrol->value.enumerated.item[0] = 1;
else
ucontrol->value.enumerated.item[0] = 0;
return 0;
}
/*
* Stop any attempts to change speaker mode while the speaker is enabled.
*
* We also have some special anti-pop controls dependent on speaker
* mode which must be changed along with the mode.
*/
static int speaker_mode_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
unsigned int reg_pwr = snd_soc_component_read(component, WM9081_POWER_MANAGEMENT);
unsigned int reg2 = snd_soc_component_read(component, WM9081_ANALOGUE_SPEAKER_2);
/* Are we changing anything? */
if (ucontrol->value.enumerated.item[0] ==
((reg2 & WM9081_SPK_MODE) != 0))
return 0;
/* Don't try to change modes while enabled */
if (reg_pwr & WM9081_SPK_ENA)
return -EINVAL;
if (ucontrol->value.enumerated.item[0]) {
/* Class AB */
reg2 &= ~(WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL);
reg2 |= WM9081_SPK_MODE;
} else {
/* Class D */
reg2 |= WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL;
reg2 &= ~WM9081_SPK_MODE;
}
snd_soc_component_write(component, WM9081_ANALOGUE_SPEAKER_2, reg2);
return 0;
}
static const struct snd_kcontrol_new wm9081_snd_controls[] = {
SOC_SINGLE_TLV("IN1 Volume", WM9081_ANALOGUE_MIXER, 1, 1, 1, in_tlv),
SOC_SINGLE_TLV("IN2 Volume", WM9081_ANALOGUE_MIXER, 3, 1, 1, in_tlv),
SOC_SINGLE_TLV("Playback Volume", WM9081_DAC_DIGITAL_1, 1, 96, 0, dac_tlv),
SOC_SINGLE("LINEOUT Switch", WM9081_ANALOGUE_LINEOUT, 7, 1, 1),
SOC_SINGLE("LINEOUT ZC Switch", WM9081_ANALOGUE_LINEOUT, 6, 1, 0),
SOC_SINGLE_TLV("LINEOUT Volume", WM9081_ANALOGUE_LINEOUT, 0, 63, 0, out_tlv),
SOC_SINGLE("DRC Switch", WM9081_DRC_1, 15, 1, 0),
SOC_ENUM("DRC High Slope", drc_high),
SOC_ENUM("DRC Low Slope", drc_low),
SOC_SINGLE_TLV("DRC Input Volume", WM9081_DRC_4, 5, 60, 1, drc_in_tlv),
SOC_SINGLE_TLV("DRC Output Volume", WM9081_DRC_4, 0, 30, 1, drc_out_tlv),
SOC_SINGLE_TLV("DRC Minimum Volume", WM9081_DRC_2, 2, 3, 1, drc_min_tlv),
SOC_SINGLE_TLV("DRC Maximum Volume", WM9081_DRC_2, 0, 3, 0, drc_max_tlv),
SOC_ENUM("DRC Attack", drc_atk),
SOC_ENUM("DRC Decay", drc_dcy),
SOC_SINGLE("DRC Quick Release Switch", WM9081_DRC_1, 2, 1, 0),
SOC_SINGLE_TLV("DRC Quick Release Volume", WM9081_DRC_2, 6, 3, 0, drc_qr_tlv),
SOC_ENUM("DRC Quick Release Decay", drc_qr_dcy),
SOC_SINGLE_TLV("DRC Startup Volume", WM9081_DRC_1, 6, 18, 0, drc_startup_tlv),
SOC_SINGLE("EQ Switch", WM9081_EQ_1, 0, 1, 0),
SOC_SINGLE("Speaker DC Volume", WM9081_ANALOGUE_SPEAKER_1, 3, 5, 0),
SOC_SINGLE("Speaker AC Volume", WM9081_ANALOGUE_SPEAKER_1, 0, 5, 0),
SOC_SINGLE("Speaker Switch", WM9081_ANALOGUE_SPEAKER_PGA, 7, 1, 1),
SOC_SINGLE("Speaker ZC Switch", WM9081_ANALOGUE_SPEAKER_PGA, 6, 1, 0),
SOC_SINGLE_TLV("Speaker Volume", WM9081_ANALOGUE_SPEAKER_PGA, 0, 63, 0,
out_tlv),
SOC_ENUM("DAC Deemphasis", dac_deemph),
SOC_ENUM_EXT("Speaker Mode", speaker_mode, speaker_mode_get, speaker_mode_put),
};
static const struct snd_kcontrol_new wm9081_eq_controls[] = {
SOC_SINGLE_TLV("EQ1 Volume", WM9081_EQ_1, 11, 24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ2 Volume", WM9081_EQ_1, 6, 24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ3 Volume", WM9081_EQ_1, 1, 24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ4 Volume", WM9081_EQ_2, 11, 24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ5 Volume", WM9081_EQ_2, 6, 24, 0, eq_tlv),
};
static const struct snd_kcontrol_new mixer[] = {
SOC_DAPM_SINGLE("IN1 Switch", WM9081_ANALOGUE_MIXER, 0, 1, 0),
SOC_DAPM_SINGLE("IN2 Switch", WM9081_ANALOGUE_MIXER, 2, 1, 0),
SOC_DAPM_SINGLE("Playback Switch", WM9081_ANALOGUE_MIXER, 4, 1, 0),
};
struct _fll_div {
u16 fll_fratio;
u16 fll_outdiv;
u16 fll_clk_ref_div;
u16 n;
u16 k;
};
/* The size in bits of the FLL divide multiplied by 10
* to allow rounding later */
#define FIXED_FLL_SIZE ((1 << 16) * 10)
static struct {
unsigned int min;
unsigned int max;
u16 fll_fratio;
int ratio;
} fll_fratios[] = {
{ 0, 64000, 4, 16 },
{ 64000, 128000, 3, 8 },
{ 128000, 256000, 2, 4 },
{ 256000, 1000000, 1, 2 },
{ 1000000, 13500000, 0, 1 },
};
static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
unsigned int Fout)
{
u64 Kpart;
unsigned int K, Ndiv, Nmod, target;
unsigned int div;
int i;
/* Fref must be <=13.5MHz */
div = 1;
while ((Fref / div) > 13500000) {
div *= 2;
if (div > 8) {
pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
Fref);
return -EINVAL;
}
}
fll_div->fll_clk_ref_div = div / 2;
pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
/* Apply the division for our remaining calculations */
Fref /= div;
/* Fvco should be 90-100MHz; don't check the upper bound */
div = 0;
target = Fout * 2;
while (target < 90000000) {
div++;
target *= 2;
if (div > 7) {
pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
Fout);
return -EINVAL;
}
}
fll_div->fll_outdiv = div;
pr_debug("Fvco=%dHz\n", target);
/* Find an appropriate FLL_FRATIO and factor it out of the target */
for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
fll_div->fll_fratio = fll_fratios[i].fll_fratio;
target /= fll_fratios[i].ratio;
break;
}
}
if (i == ARRAY_SIZE(fll_fratios)) {
pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
return -EINVAL;
}
/* Now, calculate N.K */
Ndiv = target / Fref;
fll_div->n = Ndiv;
Nmod = target % Fref;
pr_debug("Nmod=%d\n", Nmod);
/* Calculate fractional part - scale up so we can round. */
Kpart = FIXED_FLL_SIZE * (long long)Nmod;
do_div(Kpart, Fref);
K = Kpart & 0xFFFFFFFF;
if ((K % 10) >= 5)
K += 5;
/* Move down to proper range now rounding is done */
fll_div->k = K / 10;
pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
fll_div->n, fll_div->k,
fll_div->fll_fratio, fll_div->fll_outdiv,
fll_div->fll_clk_ref_div);
return 0;
}
static int wm9081_set_fll(struct snd_soc_component *component, int fll_id,
unsigned int Fref, unsigned int Fout)
{
struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
u16 reg1, reg4, reg5;
struct _fll_div fll_div;
int ret;
int clk_sys_reg;
/* Any change? */
if (Fref == wm9081->fll_fref && Fout == wm9081->fll_fout)
return 0;
/* Disable the FLL */
if (Fout == 0) {
dev_dbg(component->dev, "FLL disabled\n");
wm9081->fll_fref = 0;
wm9081->fll_fout = 0;
return 0;
}
ret = fll_factors(&fll_div, Fref, Fout);
if (ret != 0)
return ret;
reg5 = snd_soc_component_read(component, WM9081_FLL_CONTROL_5);
reg5 &= ~WM9081_FLL_CLK_SRC_MASK;
switch (fll_id) {
case WM9081_SYSCLK_FLL_MCLK:
reg5 |= 0x1;
break;
default:
dev_err(component->dev, "Unknown FLL ID %d\n", fll_id);
return -EINVAL;
}
/* Disable CLK_SYS while we reconfigure */
clk_sys_reg = snd_soc_component_read(component, WM9081_CLOCK_CONTROL_3);
if (clk_sys_reg & WM9081_CLK_SYS_ENA)
snd_soc_component_write(component, WM9081_CLOCK_CONTROL_3,
clk_sys_reg & ~WM9081_CLK_SYS_ENA);
/* Any FLL configuration change requires that the FLL be
* disabled first. */
reg1 = snd_soc_component_read(component, WM9081_FLL_CONTROL_1);
reg1 &= ~WM9081_FLL_ENA;
snd_soc_component_write(component, WM9081_FLL_CONTROL_1, reg1);
/* Apply the configuration */
if (fll_div.k)
reg1 |= WM9081_FLL_FRAC_MASK;
else
reg1 &= ~WM9081_FLL_FRAC_MASK;
snd_soc_component_write(component, WM9081_FLL_CONTROL_1, reg1);
snd_soc_component_write(component, WM9081_FLL_CONTROL_2,
(fll_div.fll_outdiv << WM9081_FLL_OUTDIV_SHIFT) |
(fll_div.fll_fratio << WM9081_FLL_FRATIO_SHIFT));
snd_soc_component_write(component, WM9081_FLL_CONTROL_3, fll_div.k);
reg4 = snd_soc_component_read(component, WM9081_FLL_CONTROL_4);
reg4 &= ~WM9081_FLL_N_MASK;
reg4 |= fll_div.n << WM9081_FLL_N_SHIFT;
snd_soc_component_write(component, WM9081_FLL_CONTROL_4, reg4);
reg5 &= ~WM9081_FLL_CLK_REF_DIV_MASK;
reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT;
snd_soc_component_write(component, WM9081_FLL_CONTROL_5, reg5);
/* Set gain to the recommended value */
snd_soc_component_update_bits(component, WM9081_FLL_CONTROL_4,
WM9081_FLL_GAIN_MASK, 0);
/* Enable the FLL */
snd_soc_component_write(component, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA);
/* Then bring CLK_SYS up again if it was disabled */
if (clk_sys_reg & WM9081_CLK_SYS_ENA)
snd_soc_component_write(component, WM9081_CLOCK_CONTROL_3, clk_sys_reg);
dev_dbg(component->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
wm9081->fll_fref = Fref;
wm9081->fll_fout = Fout;
return 0;
}
static int configure_clock(struct snd_soc_component *component)
{
struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
int new_sysclk, i, target;
unsigned int reg;
int ret = 0;
int mclkdiv = 0;
int fll = 0;
switch (wm9081->sysclk_source) {
case WM9081_SYSCLK_MCLK:
if (wm9081->mclk_rate > 12225000) {
mclkdiv = 1;
wm9081->sysclk_rate = wm9081->mclk_rate / 2;
} else {
wm9081->sysclk_rate = wm9081->mclk_rate;
}
wm9081_set_fll(component, WM9081_SYSCLK_FLL_MCLK, 0, 0);
break;
case WM9081_SYSCLK_FLL_MCLK:
/* If we have a sample rate calculate a CLK_SYS that
* gives us a suitable DAC configuration, plus BCLK.
* Ideally we would check to see if we can clock
* directly from MCLK and only use the FLL if this is
* not the case, though care must be taken with free
* running mode.
*/
if (wm9081->master && wm9081->bclk) {
/* Make sure we can generate CLK_SYS and BCLK
* and that we've got 3MHz for optimal
* performance. */
for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
target = wm9081->fs * clk_sys_rates[i].ratio;
new_sysclk = target;
if (target >= wm9081->bclk &&
target > 3000000)
break;
}
if (i == ARRAY_SIZE(clk_sys_rates))
return -EINVAL;
} else if (wm9081->fs) {
for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
new_sysclk = clk_sys_rates[i].ratio
* wm9081->fs;
if (new_sysclk > 3000000)
break;
}
if (i == ARRAY_SIZE(clk_sys_rates))
return -EINVAL;
} else {
new_sysclk = 12288000;
}
ret = wm9081_set_fll(component, WM9081_SYSCLK_FLL_MCLK,
wm9081->mclk_rate, new_sysclk);
if (ret == 0) {
wm9081->sysclk_rate = new_sysclk;
/* Switch SYSCLK over to FLL */
fll = 1;
} else {
wm9081->sysclk_rate = wm9081->mclk_rate;
}
break;
default:
return -EINVAL;
}
reg = snd_soc_component_read(component, WM9081_CLOCK_CONTROL_1);
if (mclkdiv)
reg |= WM9081_MCLKDIV2;
else
reg &= ~WM9081_MCLKDIV2;
snd_soc_component_write(component, WM9081_CLOCK_CONTROL_1, reg);
reg = snd_soc_component_read(component, WM9081_CLOCK_CONTROL_3);
if (fll)
reg |= WM9081_CLK_SRC_SEL;
else
reg &= ~WM9081_CLK_SRC_SEL;
snd_soc_component_write(component, WM9081_CLOCK_CONTROL_3, reg);
dev_dbg(component->dev, "CLK_SYS is %dHz\n", wm9081->sysclk_rate);
return ret;
}
static int clk_sys_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
/* This should be done on init() for bypass paths */
switch (wm9081->sysclk_source) {
case WM9081_SYSCLK_MCLK:
dev_dbg(component->dev, "Using %dHz MCLK\n", wm9081->mclk_rate);
break;
case WM9081_SYSCLK_FLL_MCLK:
dev_dbg(component->dev, "Using %dHz MCLK with FLL\n",
wm9081->mclk_rate);
break;
default:
dev_err(component->dev, "System clock not configured\n");
return -EINVAL;
}
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
configure_clock(component);
break;
case SND_SOC_DAPM_POST_PMD:
/* Disable the FLL if it's running */
wm9081_set_fll(component, 0, 0, 0);
break;
}
return 0;
}
static const struct snd_soc_dapm_widget wm9081_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("IN1"),
SND_SOC_DAPM_INPUT("IN2"),
SND_SOC_DAPM_DAC("DAC", NULL, WM9081_POWER_MANAGEMENT, 0, 0),
SND_SOC_DAPM_MIXER_NAMED_CTL("Mixer", SND_SOC_NOPM, 0, 0,
mixer, ARRAY_SIZE(mixer)),
SND_SOC_DAPM_PGA("LINEOUT PGA", WM9081_POWER_MANAGEMENT, 4, 0, NULL, 0),
SND_SOC_DAPM_PGA("Speaker PGA", WM9081_POWER_MANAGEMENT, 2, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("Speaker", WM9081_POWER_MANAGEMENT, 1, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("LINEOUT"),
SND_SOC_DAPM_OUTPUT("SPKN"),
SND_SOC_DAPM_OUTPUT("SPKP"),
SND_SOC_DAPM_SUPPLY("CLK_SYS", WM9081_CLOCK_CONTROL_3, 0, 0, clk_sys_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("CLK_DSP", WM9081_CLOCK_CONTROL_3, 1, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("TOCLK", WM9081_CLOCK_CONTROL_3, 2, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("TSENSE", WM9081_POWER_MANAGEMENT, 7, 0, NULL, 0),
};
static const struct snd_soc_dapm_route wm9081_audio_paths[] = {
{ "DAC", NULL, "CLK_SYS" },
{ "DAC", NULL, "CLK_DSP" },
{ "DAC", NULL, "AIF" },
{ "Mixer", "IN1 Switch", "IN1" },
{ "Mixer", "IN2 Switch", "IN2" },
{ "Mixer", "Playback Switch", "DAC" },
{ "LINEOUT PGA", NULL, "Mixer" },
{ "LINEOUT PGA", NULL, "TOCLK" },
{ "LINEOUT PGA", NULL, "CLK_SYS" },
{ "LINEOUT", NULL, "LINEOUT PGA" },
{ "Speaker PGA", NULL, "Mixer" },
{ "Speaker PGA", NULL, "TOCLK" },
{ "Speaker PGA", NULL, "CLK_SYS" },
{ "Speaker", NULL, "Speaker PGA" },
{ "Speaker", NULL, "TSENSE" },
{ "SPKN", NULL, "Speaker" },
{ "SPKP", NULL, "Speaker" },
};
static int wm9081_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
/* VMID=2*40k */
snd_soc_component_update_bits(component, WM9081_VMID_CONTROL,
WM9081_VMID_SEL_MASK, 0x2);
/* Normal bias current */
snd_soc_component_update_bits(component, WM9081_BIAS_CONTROL_1,
WM9081_STBY_BIAS_ENA, 0);
break;
case SND_SOC_BIAS_STANDBY:
/* Initial cold start */
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
regcache_cache_only(wm9081->regmap, false);
regcache_sync(wm9081->regmap);
/* Disable LINEOUT discharge */
snd_soc_component_update_bits(component, WM9081_ANTI_POP_CONTROL,
WM9081_LINEOUT_DISCH, 0);
/* Select startup bias source */
snd_soc_component_update_bits(component, WM9081_BIAS_CONTROL_1,
WM9081_BIAS_SRC | WM9081_BIAS_ENA,
WM9081_BIAS_SRC | WM9081_BIAS_ENA);
/* VMID 2*4k; Soft VMID ramp enable */
snd_soc_component_update_bits(component, WM9081_VMID_CONTROL,
WM9081_VMID_RAMP |
WM9081_VMID_SEL_MASK,
WM9081_VMID_RAMP | 0x6);
mdelay(100);
/* Normal bias enable & soft start off */
snd_soc_component_update_bits(component, WM9081_VMID_CONTROL,
WM9081_VMID_RAMP, 0);
/* Standard bias source */
snd_soc_component_update_bits(component, WM9081_BIAS_CONTROL_1,
WM9081_BIAS_SRC, 0);
}
/* VMID 2*240k */
snd_soc_component_update_bits(component, WM9081_VMID_CONTROL,
WM9081_VMID_SEL_MASK, 0x04);
/* Standby bias current on */
snd_soc_component_update_bits(component, WM9081_BIAS_CONTROL_1,
WM9081_STBY_BIAS_ENA,
WM9081_STBY_BIAS_ENA);
break;
case SND_SOC_BIAS_OFF:
/* Startup bias source and disable bias */
snd_soc_component_update_bits(component, WM9081_BIAS_CONTROL_1,
WM9081_BIAS_SRC | WM9081_BIAS_ENA,
WM9081_BIAS_SRC);
/* Disable VMID with soft ramping */
snd_soc_component_update_bits(component, WM9081_VMID_CONTROL,
WM9081_VMID_RAMP | WM9081_VMID_SEL_MASK,
WM9081_VMID_RAMP);
/* Actively discharge LINEOUT */
snd_soc_component_update_bits(component, WM9081_ANTI_POP_CONTROL,
WM9081_LINEOUT_DISCH,
WM9081_LINEOUT_DISCH);
regcache_cache_only(wm9081->regmap, true);
break;
}
return 0;
}
static int wm9081_set_dai_fmt(struct snd_soc_dai *dai,
unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
unsigned int aif2 = snd_soc_component_read(component, WM9081_AUDIO_INTERFACE_2);
aif2 &= ~(WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV |
WM9081_BCLK_DIR | WM9081_LRCLK_DIR | WM9081_AIF_FMT_MASK);
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
wm9081->master = 0;
break;
case SND_SOC_DAIFMT_CBS_CFM:
aif2 |= WM9081_LRCLK_DIR;
wm9081->master = 1;
break;
case SND_SOC_DAIFMT_CBM_CFS:
aif2 |= WM9081_BCLK_DIR;
wm9081->master = 1;
break;
case SND_SOC_DAIFMT_CBM_CFM:
aif2 |= WM9081_LRCLK_DIR | WM9081_BCLK_DIR;
wm9081->master = 1;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_B:
aif2 |= WM9081_AIF_LRCLK_INV;
fallthrough;
case SND_SOC_DAIFMT_DSP_A:
aif2 |= 0x3;
break;
case SND_SOC_DAIFMT_I2S:
aif2 |= 0x2;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
aif2 |= 0x1;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B:
/* frame inversion not valid for DSP modes */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
aif2 |= WM9081_AIF_BCLK_INV;
break;
default:
return -EINVAL;
}
break;
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_RIGHT_J:
case SND_SOC_DAIFMT_LEFT_J:
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
aif2 |= WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV;
break;
case SND_SOC_DAIFMT_IB_NF:
aif2 |= WM9081_AIF_BCLK_INV;
break;
case SND_SOC_DAIFMT_NB_IF:
aif2 |= WM9081_AIF_LRCLK_INV;
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, WM9081_AUDIO_INTERFACE_2, aif2);
return 0;
}
static int wm9081_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
int ret, i, best, best_val, cur_val;
unsigned int clk_ctrl2, aif1, aif2, aif3, aif4;
clk_ctrl2 = snd_soc_component_read(component, WM9081_CLOCK_CONTROL_2);
clk_ctrl2 &= ~(WM9081_CLK_SYS_RATE_MASK | WM9081_SAMPLE_RATE_MASK);
aif1 = snd_soc_component_read(component, WM9081_AUDIO_INTERFACE_1);
aif2 = snd_soc_component_read(component, WM9081_AUDIO_INTERFACE_2);
aif2 &= ~WM9081_AIF_WL_MASK;
aif3 = snd_soc_component_read(component, WM9081_AUDIO_INTERFACE_3);
aif3 &= ~WM9081_BCLK_DIV_MASK;
aif4 = snd_soc_component_read(component, WM9081_AUDIO_INTERFACE_4);
aif4 &= ~WM9081_LRCLK_RATE_MASK;
wm9081->fs = params_rate(params);
if (wm9081->tdm_width) {
/* If TDM is set up then that fixes our BCLK. */
int slots = ((aif1 & WM9081_AIFDAC_TDM_MODE_MASK) >>
WM9081_AIFDAC_TDM_MODE_SHIFT) + 1;
wm9081->bclk = wm9081->fs * wm9081->tdm_width * slots;
} else {
/* Otherwise work out a BCLK from the sample size */
wm9081->bclk = 2 * wm9081->fs;
switch (params_width(params)) {
case 16:
wm9081->bclk *= 16;
break;
case 20:
wm9081->bclk *= 20;
aif2 |= 0x4;
break;
case 24:
wm9081->bclk *= 24;
aif2 |= 0x8;
break;
case 32:
wm9081->bclk *= 32;
aif2 |= 0xc;
break;
default:
return -EINVAL;
}
}
dev_dbg(component->dev, "Target BCLK is %dHz\n", wm9081->bclk);
ret = configure_clock(component);
if (ret != 0)
return ret;
/* Select nearest CLK_SYS_RATE */
best = 0;
best_val = abs((wm9081->sysclk_rate / clk_sys_rates[0].ratio)
- wm9081->fs);
for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
cur_val = abs((wm9081->sysclk_rate /
clk_sys_rates[i].ratio) - wm9081->fs);
if (cur_val < best_val) {
best = i;
best_val = cur_val;
}
}
dev_dbg(component->dev, "Selected CLK_SYS_RATIO of %d\n",
clk_sys_rates[best].ratio);
clk_ctrl2 |= (clk_sys_rates[best].clk_sys_rate
<< WM9081_CLK_SYS_RATE_SHIFT);
/* SAMPLE_RATE */
best = 0;
best_val = abs(wm9081->fs - sample_rates[0].rate);
for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
/* Closest match */
cur_val = abs(wm9081->fs - sample_rates[i].rate);
if (cur_val < best_val) {
best = i;
best_val = cur_val;
}
}
dev_dbg(component->dev, "Selected SAMPLE_RATE of %dHz\n",
sample_rates[best].rate);
clk_ctrl2 |= (sample_rates[best].sample_rate
<< WM9081_SAMPLE_RATE_SHIFT);
/* BCLK_DIV */
best = 0;
best_val = INT_MAX;
for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
cur_val = ((wm9081->sysclk_rate * 10) / bclk_divs[i].div)
- wm9081->bclk;
if (cur_val < 0) /* Table is sorted */
break;
if (cur_val < best_val) {
best = i;
best_val = cur_val;
}
}
wm9081->bclk = (wm9081->sysclk_rate * 10) / bclk_divs[best].div;
dev_dbg(component->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
bclk_divs[best].div, wm9081->bclk);
aif3 |= bclk_divs[best].bclk_div;
/* LRCLK is a simple fraction of BCLK */
dev_dbg(component->dev, "LRCLK_RATE is %d\n", wm9081->bclk / wm9081->fs);
aif4 |= wm9081->bclk / wm9081->fs;
/* Apply a ReTune Mobile configuration if it's in use */
if (wm9081->pdata.num_retune_configs) {
struct wm9081_pdata *pdata = &wm9081->pdata;
struct wm9081_retune_mobile_setting *s;
int eq1;
best = 0;
best_val = abs(pdata->retune_configs[0].rate - wm9081->fs);
for (i = 0; i < pdata->num_retune_configs; i++) {
cur_val = abs(pdata->retune_configs[i].rate -
wm9081->fs);
if (cur_val < best_val) {
best_val = cur_val;
best = i;
}
}
s = &pdata->retune_configs[best];
dev_dbg(component->dev, "ReTune Mobile %s tuned for %dHz\n",
s->name, s->rate);
/* If the EQ is enabled then disable it while we write out */
eq1 = snd_soc_component_read(component, WM9081_EQ_1) & WM9081_EQ_ENA;
if (eq1 & WM9081_EQ_ENA)
snd_soc_component_write(component, WM9081_EQ_1, 0);
/* Write out the other values */
for (i = 1; i < ARRAY_SIZE(s->config); i++)
snd_soc_component_write(component, WM9081_EQ_1 + i, s->config[i]);
eq1 |= (s->config[0] & ~WM9081_EQ_ENA);
snd_soc_component_write(component, WM9081_EQ_1, eq1);
}
snd_soc_component_write(component, WM9081_CLOCK_CONTROL_2, clk_ctrl2);
snd_soc_component_write(component, WM9081_AUDIO_INTERFACE_2, aif2);
snd_soc_component_write(component, WM9081_AUDIO_INTERFACE_3, aif3);
snd_soc_component_write(component, WM9081_AUDIO_INTERFACE_4, aif4);
return 0;
}
static int wm9081_mute(struct snd_soc_dai *codec_dai, int mute, int direction)
{
struct snd_soc_component *component = codec_dai->component;
unsigned int reg;
reg = snd_soc_component_read(component, WM9081_DAC_DIGITAL_2);
if (mute)
reg |= WM9081_DAC_MUTE;
else
reg &= ~WM9081_DAC_MUTE;
snd_soc_component_write(component, WM9081_DAC_DIGITAL_2, reg);
return 0;
}
static int wm9081_set_sysclk(struct snd_soc_component *component, int clk_id,
int source, unsigned int freq, int dir)
{
struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
switch (clk_id) {
case WM9081_SYSCLK_MCLK:
case WM9081_SYSCLK_FLL_MCLK:
wm9081->sysclk_source = clk_id;
wm9081->mclk_rate = freq;
break;
default:
return -EINVAL;
}
return 0;
}
static int wm9081_set_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
unsigned int aif1 = snd_soc_component_read(component, WM9081_AUDIO_INTERFACE_1);
aif1 &= ~(WM9081_AIFDAC_TDM_SLOT_MASK | WM9081_AIFDAC_TDM_MODE_MASK);
if (slots < 0 || slots > 4)
return -EINVAL;
wm9081->tdm_width = slot_width;
if (slots == 0)
slots = 1;
aif1 |= (slots - 1) << WM9081_AIFDAC_TDM_MODE_SHIFT;
switch (rx_mask) {
case 1:
break;
case 2:
aif1 |= 0x10;
break;
case 4:
aif1 |= 0x20;
break;
case 8:
aif1 |= 0x30;
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, WM9081_AUDIO_INTERFACE_1, aif1);
return 0;
}
#define WM9081_RATES SNDRV_PCM_RATE_8000_96000
#define WM9081_FORMATS \
(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops wm9081_dai_ops = {
.hw_params = wm9081_hw_params,
.set_fmt = wm9081_set_dai_fmt,
.mute_stream = wm9081_mute,
.set_tdm_slot = wm9081_set_tdm_slot,
.no_capture_mute = 1,
};
/* We report two channels because the CODEC processes a stereo signal, even
* though it is only capable of handling a mono output.
*/
static struct snd_soc_dai_driver wm9081_dai = {
.name = "wm9081-hifi",
.playback = {
.stream_name = "AIF",
.channels_min = 1,
.channels_max = 2,
.rates = WM9081_RATES,
.formats = WM9081_FORMATS,
},
.ops = &wm9081_dai_ops,
};
static int wm9081_probe(struct snd_soc_component *component)
{
struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
/* Enable zero cross by default */
snd_soc_component_update_bits(component, WM9081_ANALOGUE_LINEOUT,
WM9081_LINEOUTZC, WM9081_LINEOUTZC);
snd_soc_component_update_bits(component, WM9081_ANALOGUE_SPEAKER_PGA,
WM9081_SPKPGAZC, WM9081_SPKPGAZC);
if (!wm9081->pdata.num_retune_configs) {
dev_dbg(component->dev,
"No ReTune Mobile data, using normal EQ\n");
snd_soc_add_component_controls(component, wm9081_eq_controls,
ARRAY_SIZE(wm9081_eq_controls));
}
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_wm9081 = {
.probe = wm9081_probe,
.set_sysclk = wm9081_set_sysclk,
.set_bias_level = wm9081_set_bias_level,
.controls = wm9081_snd_controls,
.num_controls = ARRAY_SIZE(wm9081_snd_controls),
.dapm_widgets = wm9081_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm9081_dapm_widgets),
.dapm_routes = wm9081_audio_paths,
.num_dapm_routes = ARRAY_SIZE(wm9081_audio_paths),
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config wm9081_regmap = {
.reg_bits = 8,
.val_bits = 16,
.max_register = WM9081_MAX_REGISTER,
.reg_defaults = wm9081_reg,
.num_reg_defaults = ARRAY_SIZE(wm9081_reg),
.volatile_reg = wm9081_volatile_register,
.readable_reg = wm9081_readable_register,
.cache_type = REGCACHE_MAPLE,
};
static int wm9081_i2c_probe(struct i2c_client *i2c)
{
struct wm9081_priv *wm9081;
unsigned int reg;
int ret;
wm9081 = devm_kzalloc(&i2c->dev, sizeof(struct wm9081_priv),
GFP_KERNEL);
if (wm9081 == NULL)
return -ENOMEM;
i2c_set_clientdata(i2c, wm9081);
wm9081->regmap = devm_regmap_init_i2c(i2c, &wm9081_regmap);
if (IS_ERR(wm9081->regmap)) {
ret = PTR_ERR(wm9081->regmap);
dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);
return ret;
}
ret = regmap_read(wm9081->regmap, WM9081_SOFTWARE_RESET, ®);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret);
return ret;
}
if (reg != 0x9081) {
dev_err(&i2c->dev, "Device is not a WM9081: ID=0x%x\n", reg);
return -EINVAL;
}
ret = wm9081_reset(wm9081->regmap);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to issue reset\n");
return ret;
}
if (dev_get_platdata(&i2c->dev))
memcpy(&wm9081->pdata, dev_get_platdata(&i2c->dev),
sizeof(wm9081->pdata));
reg = 0;
if (wm9081->pdata.irq_high)
reg |= WM9081_IRQ_POL;
if (!wm9081->pdata.irq_cmos)
reg |= WM9081_IRQ_OP_CTRL;
regmap_update_bits(wm9081->regmap, WM9081_INTERRUPT_CONTROL,
WM9081_IRQ_POL | WM9081_IRQ_OP_CTRL, reg);
regcache_cache_only(wm9081->regmap, true);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_wm9081, &wm9081_dai, 1);
if (ret < 0)
return ret;
return 0;
}
static void wm9081_i2c_remove(struct i2c_client *client)
{}
static const struct i2c_device_id wm9081_i2c_id[] = {
{ "wm9081", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm9081_i2c_id);
static struct i2c_driver wm9081_i2c_driver = {
.driver = {
.name = "wm9081",
},
.probe = wm9081_i2c_probe,
.remove = wm9081_i2c_remove,
.id_table = wm9081_i2c_id,
};
module_i2c_driver(wm9081_i2c_driver);
MODULE_DESCRIPTION("ASoC WM9081 driver");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm9081.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Based on sound/soc/codecs/tlv320aic3x.c by Vladimir Barinov
//
// Copyright (C) 2010 Mistral Solutions Pvt Ltd.
// Author: Shahina Shaik <[email protected]>
//
// Copyright (C) 2014-2018, Ambarella, Inc.
// Author: Dongge wu <[email protected]>
//
// Copyright (C) 2021 Axis Communications AB
// Author: Ricard Wanderlof <[email protected]>
//
#include <dt-bindings/sound/tlv320adc3xxx.h>
#include <linux/clk.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/io.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/gpio/driver.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/cdev.h>
#include <linux/of_gpio.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/tlv.h>
#include <sound/initval.h>
/*
* General definitions defining exported functionality.
*/
#define ADC3XXX_MICBIAS_PINS 2
/* Number of GPIO pins exposed via the gpiolib interface */
#define ADC3XXX_GPIOS_MAX 2
#define ADC3XXX_RATES SNDRV_PCM_RATE_8000_96000
#define ADC3XXX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_3LE | \
SNDRV_PCM_FMTBIT_S32_LE)
/*
* PLL modes, to be used for clk_id for set_sysclk callback.
*
* The default behavior (AUTO) is to take the first matching entry in the clock
* table, which is intended to be the PLL based one if there is more than one.
*
* Setting the clock source using simple-card (clocks or
* system-clock-frequency property) sets clk_id = 0 = ADC3XXX_PLL_AUTO.
*/
#define ADC3XXX_PLL_AUTO 0 /* Use first available mode */
#define ADC3XXX_PLL_ENABLE 1 /* Use PLL for clock generation */
#define ADC3XXX_PLL_BYPASS 2 /* Don't use PLL for clock generation */
/* Register definitions. */
#define ADC3XXX_PAGE_SIZE 128
#define ADC3XXX_REG(page, reg) ((page * ADC3XXX_PAGE_SIZE) + reg)
/*
* Page 0 registers.
*/
#define ADC3XXX_PAGE_SELECT ADC3XXX_REG(0, 0)
#define ADC3XXX_RESET ADC3XXX_REG(0, 1)
/* 2-3 Reserved */
#define ADC3XXX_CLKGEN_MUX ADC3XXX_REG(0, 4)
#define ADC3XXX_PLL_PROG_PR ADC3XXX_REG(0, 5)
#define ADC3XXX_PLL_PROG_J ADC3XXX_REG(0, 6)
#define ADC3XXX_PLL_PROG_D_MSB ADC3XXX_REG(0, 7)
#define ADC3XXX_PLL_PROG_D_LSB ADC3XXX_REG(0, 8)
/* 9-17 Reserved */
#define ADC3XXX_ADC_NADC ADC3XXX_REG(0, 18)
#define ADC3XXX_ADC_MADC ADC3XXX_REG(0, 19)
#define ADC3XXX_ADC_AOSR ADC3XXX_REG(0, 20)
#define ADC3XXX_ADC_IADC ADC3XXX_REG(0, 21)
/* 23-24 Reserved */
#define ADC3XXX_CLKOUT_MUX ADC3XXX_REG(0, 25)
#define ADC3XXX_CLKOUT_M_DIV ADC3XXX_REG(0, 26)
#define ADC3XXX_INTERFACE_CTRL_1 ADC3XXX_REG(0, 27)
#define ADC3XXX_CH_OFFSET_1 ADC3XXX_REG(0, 28)
#define ADC3XXX_INTERFACE_CTRL_2 ADC3XXX_REG(0, 29)
#define ADC3XXX_BCLK_N_DIV ADC3XXX_REG(0, 30)
#define ADC3XXX_INTERFACE_CTRL_3 ADC3XXX_REG(0, 31)
#define ADC3XXX_INTERFACE_CTRL_4 ADC3XXX_REG(0, 32)
#define ADC3XXX_INTERFACE_CTRL_5 ADC3XXX_REG(0, 33)
#define ADC3XXX_I2S_SYNC ADC3XXX_REG(0, 34)
/* 35 Reserved */
#define ADC3XXX_ADC_FLAG ADC3XXX_REG(0, 36)
#define ADC3XXX_CH_OFFSET_2 ADC3XXX_REG(0, 37)
#define ADC3XXX_I2S_TDM_CTRL ADC3XXX_REG(0, 38)
/* 39-41 Reserved */
#define ADC3XXX_INTR_FLAG_1 ADC3XXX_REG(0, 42)
#define ADC3XXX_INTR_FLAG_2 ADC3XXX_REG(0, 43)
/* 44 Reserved */
#define ADC3XXX_INTR_FLAG_ADC1 ADC3XXX_REG(0, 45)
/* 46 Reserved */
#define ADC3XXX_INTR_FLAG_ADC2 ADC3XXX_REG(0, 47)
#define ADC3XXX_INT1_CTRL ADC3XXX_REG(0, 48)
#define ADC3XXX_INT2_CTRL ADC3XXX_REG(0, 49)
/* 50 Reserved */
#define ADC3XXX_GPIO2_CTRL ADC3XXX_REG(0, 51)
#define ADC3XXX_GPIO1_CTRL ADC3XXX_REG(0, 52)
#define ADC3XXX_DOUT_CTRL ADC3XXX_REG(0, 53)
/* 54-56 Reserved */
#define ADC3XXX_SYNC_CTRL_1 ADC3XXX_REG(0, 57)
#define ADC3XXX_SYNC_CTRL_2 ADC3XXX_REG(0, 58)
#define ADC3XXX_CIC_GAIN_CTRL ADC3XXX_REG(0, 59)
/* 60 Reserved */
#define ADC3XXX_PRB_SELECT ADC3XXX_REG(0, 61)
#define ADC3XXX_INST_MODE_CTRL ADC3XXX_REG(0, 62)
/* 63-79 Reserved */
#define ADC3XXX_MIC_POLARITY_CTRL ADC3XXX_REG(0, 80)
#define ADC3XXX_ADC_DIGITAL ADC3XXX_REG(0, 81)
#define ADC3XXX_ADC_FGA ADC3XXX_REG(0, 82)
#define ADC3XXX_LADC_VOL ADC3XXX_REG(0, 83)
#define ADC3XXX_RADC_VOL ADC3XXX_REG(0, 84)
#define ADC3XXX_ADC_PHASE_COMP ADC3XXX_REG(0, 85)
#define ADC3XXX_LEFT_CHN_AGC_1 ADC3XXX_REG(0, 86)
#define ADC3XXX_LEFT_CHN_AGC_2 ADC3XXX_REG(0, 87)
#define ADC3XXX_LEFT_CHN_AGC_3 ADC3XXX_REG(0, 88)
#define ADC3XXX_LEFT_CHN_AGC_4 ADC3XXX_REG(0, 89)
#define ADC3XXX_LEFT_CHN_AGC_5 ADC3XXX_REG(0, 90)
#define ADC3XXX_LEFT_CHN_AGC_6 ADC3XXX_REG(0, 91)
#define ADC3XXX_LEFT_CHN_AGC_7 ADC3XXX_REG(0, 92)
#define ADC3XXX_LEFT_AGC_GAIN ADC3XXX_REG(0, 93)
#define ADC3XXX_RIGHT_CHN_AGC_1 ADC3XXX_REG(0, 94)
#define ADC3XXX_RIGHT_CHN_AGC_2 ADC3XXX_REG(0, 95)
#define ADC3XXX_RIGHT_CHN_AGC_3 ADC3XXX_REG(0, 96)
#define ADC3XXX_RIGHT_CHN_AGC_4 ADC3XXX_REG(0, 97)
#define ADC3XXX_RIGHT_CHN_AGC_5 ADC3XXX_REG(0, 98)
#define ADC3XXX_RIGHT_CHN_AGC_6 ADC3XXX_REG(0, 99)
#define ADC3XXX_RIGHT_CHN_AGC_7 ADC3XXX_REG(0, 100)
#define ADC3XXX_RIGHT_AGC_GAIN ADC3XXX_REG(0, 101)
/* 102-127 Reserved */
/*
* Page 1 registers.
*/
/* 1-25 Reserved */
#define ADC3XXX_DITHER_CTRL ADC3XXX_REG(1, 26)
/* 27-50 Reserved */
#define ADC3XXX_MICBIAS_CTRL ADC3XXX_REG(1, 51)
#define ADC3XXX_LEFT_PGA_SEL_1 ADC3XXX_REG(1, 52)
/* 53 Reserved */
#define ADC3XXX_LEFT_PGA_SEL_2 ADC3XXX_REG(1, 54)
#define ADC3XXX_RIGHT_PGA_SEL_1 ADC3XXX_REG(1, 55)
#define ADC3XXX_RIGHT_PGA_SEL_2 ADC3XXX_REG(1, 57)
#define ADC3XXX_LEFT_APGA_CTRL ADC3XXX_REG(1, 59)
#define ADC3XXX_RIGHT_APGA_CTRL ADC3XXX_REG(1, 60)
#define ADC3XXX_LOW_CURRENT_MODES ADC3XXX_REG(1, 61)
#define ADC3XXX_ANALOG_PGA_FLAGS ADC3XXX_REG(1, 62)
/* 63-127 Reserved */
/*
* Page 4 registers. First page of coefficient memory for the miniDSP.
*/
#define ADC3XXX_LEFT_ADC_IIR_COEFF_N0_MSB ADC3XXX_REG(4, 8)
#define ADC3XXX_LEFT_ADC_IIR_COEFF_N0_LSB ADC3XXX_REG(4, 9)
#define ADC3XXX_LEFT_ADC_IIR_COEFF_N1_MSB ADC3XXX_REG(4, 10)
#define ADC3XXX_LEFT_ADC_IIR_COEFF_N1_LSB ADC3XXX_REG(4, 11)
#define ADC3XXX_LEFT_ADC_IIR_COEFF_D1_MSB ADC3XXX_REG(4, 12)
#define ADC3XXX_LEFT_ADC_IIR_COEFF_D1_LSB ADC3XXX_REG(4, 13)
#define ADC3XXX_RIGHT_ADC_IIR_COEFF_N0_MSB ADC3XXX_REG(4, 72)
#define ADC3XXX_RIGHT_ADC_IIR_COEFF_N0_LSB ADC3XXX_REG(4, 73)
#define ADC3XXX_RIGHT_ADC_IIR_COEFF_N1_MSB ADC3XXX_REG(4, 74)
#define ADC3XXX_RIGHT_ADC_IIR_COEFF_N1_LSB ADC3XXX_REG(4, 75)
#define ADC3XXX_RIGHT_ADC_IIR_COEFF_D1_MSB ADC3XXX_REG(4, 76)
#define ADC3XXX_RIGHT_ADC_IIR_COEFF_D1_LSB ADC3XXX_REG(4, 77)
/*
* Register bits.
*/
/* PLL Enable bits */
#define ADC3XXX_ENABLE_PLL_SHIFT 7
#define ADC3XXX_ENABLE_PLL (1 << ADC3XXX_ENABLE_PLL_SHIFT)
#define ADC3XXX_ENABLE_NADC_SHIFT 7
#define ADC3XXX_ENABLE_NADC (1 << ADC3XXX_ENABLE_NADC_SHIFT)
#define ADC3XXX_ENABLE_MADC_SHIFT 7
#define ADC3XXX_ENABLE_MADC (1 << ADC3XXX_ENABLE_MADC_SHIFT)
#define ADC3XXX_ENABLE_BCLK_SHIFT 7
#define ADC3XXX_ENABLE_BCLK (1 << ADC3XXX_ENABLE_BCLK_SHIFT)
/* Power bits */
#define ADC3XXX_LADC_PWR_ON 0x80
#define ADC3XXX_RADC_PWR_ON 0x40
#define ADC3XXX_SOFT_RESET 0x01
#define ADC3XXX_BCLK_MASTER 0x08
#define ADC3XXX_WCLK_MASTER 0x04
/* Interface register masks */
#define ADC3XXX_FORMAT_MASK 0xc0
#define ADC3XXX_FORMAT_SHIFT 6
#define ADC3XXX_WLENGTH_MASK 0x30
#define ADC3XXX_WLENGTH_SHIFT 4
#define ADC3XXX_CLKDIR_MASK 0x0c
#define ADC3XXX_CLKDIR_SHIFT 2
/* Interface register bit patterns */
#define ADC3XXX_FORMAT_I2S (0 << ADC3XXX_FORMAT_SHIFT)
#define ADC3XXX_FORMAT_DSP (1 << ADC3XXX_FORMAT_SHIFT)
#define ADC3XXX_FORMAT_RJF (2 << ADC3XXX_FORMAT_SHIFT)
#define ADC3XXX_FORMAT_LJF (3 << ADC3XXX_FORMAT_SHIFT)
#define ADC3XXX_IFACE_16BITS (0 << ADC3XXX_WLENGTH_SHIFT)
#define ADC3XXX_IFACE_20BITS (1 << ADC3XXX_WLENGTH_SHIFT)
#define ADC3XXX_IFACE_24BITS (2 << ADC3XXX_WLENGTH_SHIFT)
#define ADC3XXX_IFACE_32BITS (3 << ADC3XXX_WLENGTH_SHIFT)
/* PLL P/R bit offsets */
#define ADC3XXX_PLLP_SHIFT 4
#define ADC3XXX_PLLR_SHIFT 0
#define ADC3XXX_PLL_PR_MASK 0x7f
#define ADC3XXX_PLLJ_MASK 0x3f
#define ADC3XXX_PLLD_MSB_MASK 0x3f
#define ADC3XXX_PLLD_LSB_MASK 0xff
#define ADC3XXX_NADC_MASK 0x7f
#define ADC3XXX_MADC_MASK 0x7f
#define ADC3XXX_AOSR_MASK 0xff
#define ADC3XXX_IADC_MASK 0xff
#define ADC3XXX_BDIV_MASK 0x7f
/* PLL_CLKIN bits */
#define ADC3XXX_PLL_CLKIN_SHIFT 2
#define ADC3XXX_PLL_CLKIN_MCLK 0x0
#define ADC3XXX_PLL_CLKIN_BCLK 0x1
#define ADC3XXX_PLL_CLKIN_ZERO 0x3
/* CODEC_CLKIN bits */
#define ADC3XXX_CODEC_CLKIN_SHIFT 0
#define ADC3XXX_CODEC_CLKIN_MCLK 0x0
#define ADC3XXX_CODEC_CLKIN_BCLK 0x1
#define ADC3XXX_CODEC_CLKIN_PLL_CLK 0x3
#define ADC3XXX_USE_PLL ((ADC3XXX_PLL_CLKIN_MCLK << ADC3XXX_PLL_CLKIN_SHIFT) | \
(ADC3XXX_CODEC_CLKIN_PLL_CLK << ADC3XXX_CODEC_CLKIN_SHIFT))
#define ADC3XXX_NO_PLL ((ADC3XXX_PLL_CLKIN_ZERO << ADC3XXX_PLL_CLKIN_SHIFT) | \
(ADC3XXX_CODEC_CLKIN_MCLK << ADC3XXX_CODEC_CLKIN_SHIFT))
/* Analog PGA control bits */
#define ADC3XXX_LPGA_MUTE 0x80
#define ADC3XXX_RPGA_MUTE 0x80
#define ADC3XXX_LPGA_GAIN_MASK 0x7f
#define ADC3XXX_RPGA_GAIN_MASK 0x7f
/* ADC current modes */
#define ADC3XXX_ADC_LOW_CURR_MODE 0x01
/* Left ADC Input selection bits */
#define ADC3XXX_LCH_SEL1_SHIFT 0
#define ADC3XXX_LCH_SEL2_SHIFT 2
#define ADC3XXX_LCH_SEL3_SHIFT 4
#define ADC3XXX_LCH_SEL4_SHIFT 6
#define ADC3XXX_LCH_SEL1X_SHIFT 0
#define ADC3XXX_LCH_SEL2X_SHIFT 2
#define ADC3XXX_LCH_SEL3X_SHIFT 4
#define ADC3XXX_LCH_COMMON_MODE 0x40
#define ADC3XXX_BYPASS_LPGA 0x80
/* Right ADC Input selection bits */
#define ADC3XXX_RCH_SEL1_SHIFT 0
#define ADC3XXX_RCH_SEL2_SHIFT 2
#define ADC3XXX_RCH_SEL3_SHIFT 4
#define ADC3XXX_RCH_SEL4_SHIFT 6
#define ADC3XXX_RCH_SEL1X_SHIFT 0
#define ADC3XXX_RCH_SEL2X_SHIFT 2
#define ADC3XXX_RCH_SEL3X_SHIFT 4
#define ADC3XXX_RCH_COMMON_MODE 0x40
#define ADC3XXX_BYPASS_RPGA 0x80
/* MICBIAS control bits */
#define ADC3XXX_MICBIAS_MASK 0x2
#define ADC3XXX_MICBIAS1_SHIFT 5
#define ADC3XXX_MICBIAS2_SHIFT 3
#define ADC3XXX_ADC_MAX_VOLUME 64
#define ADC3XXX_ADC_POS_VOL 24
/* GPIO control bits (GPIO1_CTRL and GPIO2_CTRL) */
#define ADC3XXX_GPIO_CTRL_CFG_MASK 0x3c
#define ADC3XXX_GPIO_CTRL_CFG_SHIFT 2
#define ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_MASK 0x01
#define ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_SHIFT 0
#define ADC3XXX_GPIO_CTRL_INPUT_VALUE_MASK 0x02
#define ADC3XXX_GPIO_CTRL_INPUT_VALUE_SHIFT 1
enum adc3xxx_type {
ADC3001 = 0,
ADC3101
};
struct adc3xxx {
struct device *dev;
enum adc3xxx_type type;
struct clk *mclk;
struct regmap *regmap;
struct gpio_desc *rst_pin;
unsigned int pll_mode;
unsigned int sysclk;
unsigned int gpio_cfg[ADC3XXX_GPIOS_MAX]; /* value+1 (0 => not set) */
unsigned int micbias_vg[ADC3XXX_MICBIAS_PINS];
int master;
u8 page_no;
int use_pll;
struct gpio_chip gpio_chip;
};
static const unsigned int adc3xxx_gpio_ctrl_reg[ADC3XXX_GPIOS_MAX] = {
ADC3XXX_GPIO1_CTRL,
ADC3XXX_GPIO2_CTRL
};
static const unsigned int adc3xxx_micbias_shift[ADC3XXX_MICBIAS_PINS] = {
ADC3XXX_MICBIAS1_SHIFT,
ADC3XXX_MICBIAS2_SHIFT
};
static const struct reg_default adc3xxx_defaults[] = {
/* Page 0 */
{ 0, 0x00 }, { 1, 0x00 }, { 2, 0x00 }, { 3, 0x00 },
{ 4, 0x00 }, { 5, 0x11 }, { 6, 0x04 }, { 7, 0x00 },
{ 8, 0x00 }, { 9, 0x00 }, { 10, 0x00 }, { 11, 0x00 },
{ 12, 0x00 }, { 13, 0x00 }, { 14, 0x00 }, { 15, 0x00 },
{ 16, 0x00 }, { 17, 0x00 }, { 18, 0x01 }, { 19, 0x01 },
{ 20, 0x80 }, { 21, 0x80 }, { 22, 0x04 }, { 23, 0x00 },
{ 24, 0x00 }, { 25, 0x00 }, { 26, 0x01 }, { 27, 0x00 },
{ 28, 0x00 }, { 29, 0x02 }, { 30, 0x01 }, { 31, 0x00 },
{ 32, 0x00 }, { 33, 0x10 }, { 34, 0x00 }, { 35, 0x00 },
{ 36, 0x00 }, { 37, 0x00 }, { 38, 0x02 }, { 39, 0x00 },
{ 40, 0x00 }, { 41, 0x00 }, { 42, 0x00 }, { 43, 0x00 },
{ 44, 0x00 }, { 45, 0x00 }, { 46, 0x00 }, { 47, 0x00 },
{ 48, 0x00 }, { 49, 0x00 }, { 50, 0x00 }, { 51, 0x00 },
{ 52, 0x00 }, { 53, 0x12 }, { 54, 0x00 }, { 55, 0x00 },
{ 56, 0x00 }, { 57, 0x00 }, { 58, 0x00 }, { 59, 0x44 },
{ 60, 0x00 }, { 61, 0x01 }, { 62, 0x00 }, { 63, 0x00 },
{ 64, 0x00 }, { 65, 0x00 }, { 66, 0x00 }, { 67, 0x00 },
{ 68, 0x00 }, { 69, 0x00 }, { 70, 0x00 }, { 71, 0x00 },
{ 72, 0x00 }, { 73, 0x00 }, { 74, 0x00 }, { 75, 0x00 },
{ 76, 0x00 }, { 77, 0x00 }, { 78, 0x00 }, { 79, 0x00 },
{ 80, 0x00 }, { 81, 0x00 }, { 82, 0x88 }, { 83, 0x00 },
{ 84, 0x00 }, { 85, 0x00 }, { 86, 0x00 }, { 87, 0x00 },
{ 88, 0x7f }, { 89, 0x00 }, { 90, 0x00 }, { 91, 0x00 },
{ 92, 0x00 }, { 93, 0x00 }, { 94, 0x00 }, { 95, 0x00 },
{ 96, 0x7f }, { 97, 0x00 }, { 98, 0x00 }, { 99, 0x00 },
{ 100, 0x00 }, { 101, 0x00 }, { 102, 0x00 }, { 103, 0x00 },
{ 104, 0x00 }, { 105, 0x00 }, { 106, 0x00 }, { 107, 0x00 },
{ 108, 0x00 }, { 109, 0x00 }, { 110, 0x00 }, { 111, 0x00 },
{ 112, 0x00 }, { 113, 0x00 }, { 114, 0x00 }, { 115, 0x00 },
{ 116, 0x00 }, { 117, 0x00 }, { 118, 0x00 }, { 119, 0x00 },
{ 120, 0x00 }, { 121, 0x00 }, { 122, 0x00 }, { 123, 0x00 },
{ 124, 0x00 }, { 125, 0x00 }, { 126, 0x00 }, { 127, 0x00 },
/* Page 1 */
{ 128, 0x00 }, { 129, 0x00 }, { 130, 0x00 }, { 131, 0x00 },
{ 132, 0x00 }, { 133, 0x00 }, { 134, 0x00 }, { 135, 0x00 },
{ 136, 0x00 }, { 137, 0x00 }, { 138, 0x00 }, { 139, 0x00 },
{ 140, 0x00 }, { 141, 0x00 }, { 142, 0x00 }, { 143, 0x00 },
{ 144, 0x00 }, { 145, 0x00 }, { 146, 0x00 }, { 147, 0x00 },
{ 148, 0x00 }, { 149, 0x00 }, { 150, 0x00 }, { 151, 0x00 },
{ 152, 0x00 }, { 153, 0x00 }, { 154, 0x00 }, { 155, 0x00 },
{ 156, 0x00 }, { 157, 0x00 }, { 158, 0x00 }, { 159, 0x00 },
{ 160, 0x00 }, { 161, 0x00 }, { 162, 0x00 }, { 163, 0x00 },
{ 164, 0x00 }, { 165, 0x00 }, { 166, 0x00 }, { 167, 0x00 },
{ 168, 0x00 }, { 169, 0x00 }, { 170, 0x00 }, { 171, 0x00 },
{ 172, 0x00 }, { 173, 0x00 }, { 174, 0x00 }, { 175, 0x00 },
{ 176, 0x00 }, { 177, 0x00 }, { 178, 0x00 }, { 179, 0x00 },
{ 180, 0xff }, { 181, 0x00 }, { 182, 0x3f }, { 183, 0xff },
{ 184, 0x00 }, { 185, 0x3f }, { 186, 0x00 }, { 187, 0x80 },
{ 188, 0x80 }, { 189, 0x00 }, { 190, 0x00 }, { 191, 0x00 },
/* Page 4 */
{ 1024, 0x00 }, { 1026, 0x01 }, { 1027, 0x17 },
{ 1028, 0x01 }, { 1029, 0x17 }, { 1030, 0x7d }, { 1031, 0xd3 },
{ 1032, 0x7f }, { 1033, 0xff }, { 1034, 0x00 }, { 1035, 0x00 },
{ 1036, 0x00 }, { 1037, 0x00 }, { 1038, 0x7f }, { 1039, 0xff },
{ 1040, 0x00 }, { 1041, 0x00 }, { 1042, 0x00 }, { 1043, 0x00 },
{ 1044, 0x00 }, { 1045, 0x00 }, { 1046, 0x00 }, { 1047, 0x00 },
{ 1048, 0x7f }, { 1049, 0xff }, { 1050, 0x00 }, { 1051, 0x00 },
{ 1052, 0x00 }, { 1053, 0x00 }, { 1054, 0x00 }, { 1055, 0x00 },
{ 1056, 0x00 }, { 1057, 0x00 }, { 1058, 0x7f }, { 1059, 0xff },
{ 1060, 0x00 }, { 1061, 0x00 }, { 1062, 0x00 }, { 1063, 0x00 },
{ 1064, 0x00 }, { 1065, 0x00 }, { 1066, 0x00 }, { 1067, 0x00 },
{ 1068, 0x7f }, { 1069, 0xff }, { 1070, 0x00 }, { 1071, 0x00 },
{ 1072, 0x00 }, { 1073, 0x00 }, { 1074, 0x00 }, { 1075, 0x00 },
{ 1076, 0x00 }, { 1077, 0x00 }, { 1078, 0x7f }, { 1079, 0xff },
{ 1080, 0x00 }, { 1081, 0x00 }, { 1082, 0x00 }, { 1083, 0x00 },
{ 1084, 0x00 }, { 1085, 0x00 }, { 1086, 0x00 }, { 1087, 0x00 },
{ 1088, 0x00 }, { 1089, 0x00 }, { 1090, 0x00 }, { 1091, 0x00 },
{ 1092, 0x00 }, { 1093, 0x00 }, { 1094, 0x00 }, { 1095, 0x00 },
{ 1096, 0x00 }, { 1097, 0x00 }, { 1098, 0x00 }, { 1099, 0x00 },
{ 1100, 0x00 }, { 1101, 0x00 }, { 1102, 0x00 }, { 1103, 0x00 },
{ 1104, 0x00 }, { 1105, 0x00 }, { 1106, 0x00 }, { 1107, 0x00 },
{ 1108, 0x00 }, { 1109, 0x00 }, { 1110, 0x00 }, { 1111, 0x00 },
{ 1112, 0x00 }, { 1113, 0x00 }, { 1114, 0x00 }, { 1115, 0x00 },
{ 1116, 0x00 }, { 1117, 0x00 }, { 1118, 0x00 }, { 1119, 0x00 },
{ 1120, 0x00 }, { 1121, 0x00 }, { 1122, 0x00 }, { 1123, 0x00 },
{ 1124, 0x00 }, { 1125, 0x00 }, { 1126, 0x00 }, { 1127, 0x00 },
{ 1128, 0x00 }, { 1129, 0x00 }, { 1130, 0x00 }, { 1131, 0x00 },
{ 1132, 0x00 }, { 1133, 0x00 }, { 1134, 0x00 }, { 1135, 0x00 },
{ 1136, 0x00 }, { 1137, 0x00 }, { 1138, 0x00 }, { 1139, 0x00 },
{ 1140, 0x00 }, { 1141, 0x00 }, { 1142, 0x00 }, { 1143, 0x00 },
{ 1144, 0x00 }, { 1145, 0x00 }, { 1146, 0x00 }, { 1147, 0x00 },
{ 1148, 0x00 }, { 1149, 0x00 }, { 1150, 0x00 }, { 1151, 0x00 },
};
static bool adc3xxx_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case ADC3XXX_RESET:
return true;
default:
return false;
}
}
static const struct regmap_range_cfg adc3xxx_ranges[] = {
{
.range_min = 0,
.range_max = 5 * ADC3XXX_PAGE_SIZE,
.selector_reg = ADC3XXX_PAGE_SELECT,
.selector_mask = 0xff,
.selector_shift = 0,
.window_start = 0,
.window_len = ADC3XXX_PAGE_SIZE,
}
};
static const struct regmap_config adc3xxx_regmap = {
.reg_bits = 8,
.val_bits = 8,
.reg_defaults = adc3xxx_defaults,
.num_reg_defaults = ARRAY_SIZE(adc3xxx_defaults),
.volatile_reg = adc3xxx_volatile_reg,
.cache_type = REGCACHE_RBTREE,
.ranges = adc3xxx_ranges,
.num_ranges = ARRAY_SIZE(adc3xxx_ranges),
.max_register = 5 * ADC3XXX_PAGE_SIZE,
};
struct adc3xxx_rate_divs {
u32 mclk;
u32 rate;
u8 pll_p;
u8 pll_r;
u8 pll_j;
u16 pll_d;
u8 nadc;
u8 madc;
u8 aosr;
};
/*
* PLL and Clock settings.
* If p member is 0, PLL is not used.
* The order of the entries in this table have the PLL entries before
* the non-PLL entries, so that the PLL modes are preferred unless
* the PLL mode setting says otherwise.
*/
static const struct adc3xxx_rate_divs adc3xxx_divs[] = {
/* mclk, rate, p, r, j, d, nadc, madc, aosr */
/* 8k rate */
{ 12000000, 8000, 1, 1, 7, 1680, 42, 2, 128 },
{ 12288000, 8000, 1, 1, 7, 0000, 42, 2, 128 },
/* 11.025k rate */
{ 12000000, 11025, 1, 1, 6, 8208, 29, 2, 128 },
/* 16k rate */
{ 12000000, 16000, 1, 1, 7, 1680, 21, 2, 128 },
{ 12288000, 16000, 1, 1, 7, 0000, 21, 2, 128 },
/* 22.05k rate */
{ 12000000, 22050, 1, 1, 7, 560, 15, 2, 128 },
/* 32k rate */
{ 12000000, 32000, 1, 1, 8, 1920, 12, 2, 128 },
{ 12288000, 32000, 1, 1, 8, 0000, 12, 2, 128 },
/* 44.1k rate */
{ 12000000, 44100, 1, 1, 7, 5264, 8, 2, 128 },
/* 48k rate */
{ 12000000, 48000, 1, 1, 7, 1680, 7, 2, 128 },
{ 12288000, 48000, 1, 1, 7, 0000, 7, 2, 128 },
{ 24576000, 48000, 1, 1, 3, 5000, 7, 2, 128 }, /* With PLL */
{ 24576000, 48000, 0, 0, 0, 0000, 2, 2, 128 }, /* Without PLL */
/* 88.2k rate */
{ 12000000, 88200, 1, 1, 7, 5264, 4, 4, 64 },
/* 96k rate */
{ 12000000, 96000, 1, 1, 8, 1920, 4, 4, 64 },
};
static int adc3xxx_get_divs(struct device *dev, int mclk, int rate, int pll_mode)
{
int i;
dev_dbg(dev, "mclk = %d, rate = %d, clock mode %u\n",
mclk, rate, pll_mode);
for (i = 0; i < ARRAY_SIZE(adc3xxx_divs); i++) {
const struct adc3xxx_rate_divs *mode = &adc3xxx_divs[i];
/* Skip this entry if it doesn't fulfill the intended clock
* mode requirement. We consider anything besides the two
* modes below to be the same as ADC3XXX_PLL_AUTO.
*/
if ((pll_mode == ADC3XXX_PLL_BYPASS && mode->pll_p) ||
(pll_mode == ADC3XXX_PLL_ENABLE && !mode->pll_p))
continue;
if (mode->rate == rate && mode->mclk == mclk)
return i;
}
dev_info(dev, "Master clock rate %d and sample rate %d is not supported\n",
mclk, rate);
return -EINVAL;
}
static int adc3xxx_pll_delay(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
/* 10msec delay needed after PLL power-up to allow
* PLL and dividers to stabilize (datasheet p13).
*/
usleep_range(10000, 20000);
return 0;
}
static int adc3xxx_coefficient_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
int numcoeff = kcontrol->private_value >> 16;
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = numcoeff;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = 0xffff; /* all coefficients are 16 bit */
return 0;
}
static int adc3xxx_coefficient_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
int numcoeff = kcontrol->private_value >> 16;
int reg = kcontrol->private_value & 0xffff;
int index = 0;
for (index = 0; index < numcoeff; index++) {
unsigned int value_msb, value_lsb, value;
value_msb = snd_soc_component_read(component, reg++);
if ((int)value_msb < 0)
return (int)value_msb;
value_lsb = snd_soc_component_read(component, reg++);
if ((int)value_lsb < 0)
return (int)value_lsb;
value = (value_msb << 8) | value_lsb;
ucontrol->value.integer.value[index] = value;
}
return 0;
}
static int adc3xxx_coefficient_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
int numcoeff = kcontrol->private_value >> 16;
int reg = kcontrol->private_value & 0xffff;
int index = 0;
int ret;
for (index = 0; index < numcoeff; index++) {
unsigned int value = ucontrol->value.integer.value[index];
unsigned int value_msb = (value >> 8) & 0xff;
unsigned int value_lsb = value & 0xff;
ret = snd_soc_component_write(component, reg++, value_msb);
if (ret)
return ret;
ret = snd_soc_component_write(component, reg++, value_lsb);
if (ret)
return ret;
}
return 0;
}
/* All on-chip filters have coefficients which are expressed in terms of
* 16 bit values, so represent them as strings of 16-bit integers.
*/
#define TI_COEFFICIENTS(xname, reg, numcoeffs) { \
.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
.name = xname, \
.info = adc3xxx_coefficient_info, \
.get = adc3xxx_coefficient_get,\
.put = adc3xxx_coefficient_put, \
.access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
.private_value = reg | (numcoeffs << 16) \
}
static const char * const adc_softstepping_text[] = { "1 step", "2 step", "off" };
static SOC_ENUM_SINGLE_DECL(adc_softstepping_enum, ADC3XXX_ADC_DIGITAL, 0,
adc_softstepping_text);
static const char * const multiplier_text[] = { "1", "2", "4", "8", "16", "32", "64", "128" };
static SOC_ENUM_SINGLE_DECL(left_agc_attack_mult_enum,
ADC3XXX_LEFT_CHN_AGC_4, 0, multiplier_text);
static SOC_ENUM_SINGLE_DECL(right_agc_attack_mult_enum,
ADC3XXX_RIGHT_CHN_AGC_4, 0, multiplier_text);
static SOC_ENUM_SINGLE_DECL(left_agc_decay_mult_enum,
ADC3XXX_LEFT_CHN_AGC_5, 0, multiplier_text);
static SOC_ENUM_SINGLE_DECL(right_agc_decay_mult_enum,
ADC3XXX_RIGHT_CHN_AGC_5, 0, multiplier_text);
static const char * const dither_dc_offset_text[] = {
"0mV", "15mV", "30mV", "45mV", "60mV", "75mV", "90mV", "105mV",
"-15mV", "-30mV", "-45mV", "-60mV", "-75mV", "-90mV", "-105mV"
};
static const unsigned int dither_dc_offset_values[] = {
0, 1, 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15
};
static SOC_VALUE_ENUM_DOUBLE_DECL(dither_dc_offset_enum,
ADC3XXX_DITHER_CTRL,
4, 0, 0xf, dither_dc_offset_text,
dither_dc_offset_values);
static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 50, 0);
static const DECLARE_TLV_DB_SCALE(adc_tlv, -1200, 50, 0);
static const DECLARE_TLV_DB_SCALE(adc_fine_tlv, -40, 10, 0);
/* AGC target: 8 values: -5.5, -8, -10, -12, -14, -17, -20, -24 dB */
/* It would be nice to declare these in the order above, but empirically
* TLV_DB_SCALE_ITEM doesn't take lightly to the increment (second) parameter
* being negative, despite there being examples to the contrary in other
* drivers. So declare these in the order from lowest to highest, and
* set the invert flag in the SOC_DOUBLE_R_TLV declaration instead.
*/
static const DECLARE_TLV_DB_RANGE(agc_target_tlv,
0, 0, TLV_DB_SCALE_ITEM(-2400, 0, 0),
1, 3, TLV_DB_SCALE_ITEM(-2000, 300, 0),
4, 6, TLV_DB_SCALE_ITEM(-1200, 200, 0),
7, 7, TLV_DB_SCALE_ITEM(-550, 0, 0));
/* Since the 'disabled' value (mute) is at the highest value in the dB
* range (i.e. just before -32 dB) rather than the lowest, we need to resort
* to using a TLV_DB_RANGE in order to get the mute value in the right place.
*/
static const DECLARE_TLV_DB_RANGE(agc_thresh_tlv,
0, 30, TLV_DB_SCALE_ITEM(-9000, 200, 0),
31, 31, TLV_DB_SCALE_ITEM(0, 0, 1)); /* disabled = mute */
/* AGC hysteresis: 4 values: 1, 2, 4 dB, disabled (= mute) */
static const DECLARE_TLV_DB_RANGE(agc_hysteresis_tlv,
0, 1, TLV_DB_SCALE_ITEM(100, 100, 0),
2, 2, TLV_DB_SCALE_ITEM(400, 0, 0),
3, 3, TLV_DB_SCALE_ITEM(0, 0, 1)); /* disabled = mute */
static const DECLARE_TLV_DB_SCALE(agc_max_tlv, 0, 50, 0);
/* Input attenuation: -6 dB or 0 dB */
static const DECLARE_TLV_DB_SCALE(input_attenuation_tlv, -600, 600, 0);
static const struct snd_kcontrol_new adc3xxx_snd_controls[] = {
SOC_DOUBLE_R_TLV("PGA Capture Volume", ADC3XXX_LEFT_APGA_CTRL,
ADC3XXX_RIGHT_APGA_CTRL, 0, 80, 0, pga_tlv),
SOC_DOUBLE("PGA Capture Switch", ADC3XXX_ADC_FGA, 7, 3, 1, 1),
SOC_DOUBLE_R("AGC Capture Switch", ADC3XXX_LEFT_CHN_AGC_1,
ADC3XXX_RIGHT_CHN_AGC_1, 7, 1, 0),
SOC_DOUBLE_R_TLV("AGC Target Level Capture Volume", ADC3XXX_LEFT_CHN_AGC_1,
ADC3XXX_RIGHT_CHN_AGC_2, 4, 0x07, 1, agc_target_tlv),
SOC_DOUBLE_R_TLV("AGC Noise Threshold Capture Volume", ADC3XXX_LEFT_CHN_AGC_2,
ADC3XXX_RIGHT_CHN_AGC_2, 1, 0x1f, 1, agc_thresh_tlv),
SOC_DOUBLE_R_TLV("AGC Hysteresis Capture Volume", ADC3XXX_LEFT_CHN_AGC_2,
ADC3XXX_RIGHT_CHN_AGC_2, 6, 3, 0, agc_hysteresis_tlv),
SOC_DOUBLE_R("AGC Clip Stepping Capture Switch", ADC3XXX_LEFT_CHN_AGC_2,
ADC3XXX_RIGHT_CHN_AGC_2, 0, 1, 0),
/*
* Oddly enough, the data sheet says the default value
* for the left/right AGC maximum gain register field
* (ADC3XXX_LEFT/RIGHT_CHN_AGC_3 bits 0..6) is 0x7f = 127
* (verified empirically) even though this value (indeed, above
* 0x50) is specified as 'Reserved. Do not use.' in the accompanying
* table in the data sheet.
*/
SOC_DOUBLE_R_TLV("AGC Maximum Capture Volume", ADC3XXX_LEFT_CHN_AGC_3,
ADC3XXX_RIGHT_CHN_AGC_3, 0, 0x50, 0, agc_max_tlv),
SOC_DOUBLE_R("AGC Attack Time", ADC3XXX_LEFT_CHN_AGC_4,
ADC3XXX_RIGHT_CHN_AGC_4, 3, 0x1f, 0),
/* Would like to have the multipliers as LR pairs, but there is
* no SOC_ENUM_foo which accepts two values in separate registers.
*/
SOC_ENUM("AGC Left Attack Time Multiplier", left_agc_attack_mult_enum),
SOC_ENUM("AGC Right Attack Time Multiplier", right_agc_attack_mult_enum),
SOC_DOUBLE_R("AGC Decay Time", ADC3XXX_LEFT_CHN_AGC_5,
ADC3XXX_RIGHT_CHN_AGC_5, 3, 0x1f, 0),
SOC_ENUM("AGC Left Decay Time Multiplier", left_agc_decay_mult_enum),
SOC_ENUM("AGC Right Decay Time Multiplier", right_agc_decay_mult_enum),
SOC_DOUBLE_R("AGC Noise Debounce", ADC3XXX_LEFT_CHN_AGC_6,
ADC3XXX_RIGHT_CHN_AGC_6, 0, 0x1f, 0),
SOC_DOUBLE_R("AGC Signal Debounce", ADC3XXX_LEFT_CHN_AGC_7,
ADC3XXX_RIGHT_CHN_AGC_7, 0, 0x0f, 0),
/* Read only register */
SOC_DOUBLE_R_S_TLV("AGC Applied Capture Volume", ADC3XXX_LEFT_AGC_GAIN,
ADC3XXX_RIGHT_AGC_GAIN, 0, -24, 40, 6, 0, adc_tlv),
/* ADC soft stepping */
SOC_ENUM("ADC Soft Stepping", adc_softstepping_enum),
/* Left/Right Input attenuation */
SOC_SINGLE_TLV("Left Input IN_1L Capture Volume",
ADC3XXX_LEFT_PGA_SEL_1, 0, 1, 1, input_attenuation_tlv),
SOC_SINGLE_TLV("Left Input IN_2L Capture Volume",
ADC3XXX_LEFT_PGA_SEL_1, 2, 1, 1, input_attenuation_tlv),
SOC_SINGLE_TLV("Left Input IN_3L Capture Volume",
ADC3XXX_LEFT_PGA_SEL_1, 4, 1, 1, input_attenuation_tlv),
SOC_SINGLE_TLV("Left Input IN_1R Capture Volume",
ADC3XXX_LEFT_PGA_SEL_2, 0, 1, 1, input_attenuation_tlv),
SOC_SINGLE_TLV("Left Input DIF_2L_3L Capture Volume",
ADC3XXX_LEFT_PGA_SEL_1, 6, 1, 1, input_attenuation_tlv),
SOC_SINGLE_TLV("Left Input DIF_1L_1R Capture Volume",
ADC3XXX_LEFT_PGA_SEL_2, 4, 1, 1, input_attenuation_tlv),
SOC_SINGLE_TLV("Left Input DIF_2R_3R Capture Volume",
ADC3XXX_LEFT_PGA_SEL_2, 2, 1, 1, input_attenuation_tlv),
SOC_SINGLE_TLV("Right Input IN_1R Capture Volume",
ADC3XXX_RIGHT_PGA_SEL_1, 0, 1, 1, input_attenuation_tlv),
SOC_SINGLE_TLV("Right Input IN_2R Capture Volume",
ADC3XXX_RIGHT_PGA_SEL_1, 2, 1, 1, input_attenuation_tlv),
SOC_SINGLE_TLV("Right Input IN_3R Capture Volume",
ADC3XXX_RIGHT_PGA_SEL_1, 4, 1, 1, input_attenuation_tlv),
SOC_SINGLE_TLV("Right Input IN_1L Capture Volume",
ADC3XXX_RIGHT_PGA_SEL_2, 0, 1, 1, input_attenuation_tlv),
SOC_SINGLE_TLV("Right Input DIF_2R_3R Capture Volume",
ADC3XXX_RIGHT_PGA_SEL_1, 6, 1, 1, input_attenuation_tlv),
SOC_SINGLE_TLV("Right Input DIF_1L_1R Capture Volume",
ADC3XXX_RIGHT_PGA_SEL_2, 4, 1, 1, input_attenuation_tlv),
SOC_SINGLE_TLV("Right Input DIF_2L_3L Capture Volume",
ADC3XXX_RIGHT_PGA_SEL_2, 2, 1, 1, input_attenuation_tlv),
SOC_DOUBLE_R_S_TLV("ADC Volume Control Capture Volume", ADC3XXX_LADC_VOL,
ADC3XXX_RADC_VOL, 0, -24, 40, 6, 0, adc_tlv),
/* Empirically, the following doesn't work the way it's supposed
* to. Values 0, -0.1, -0.2 and -0.3 dB result in the same level, and
* -0.4 dB drops about 0.12 dB on a specific chip.
*/
SOC_DOUBLE_TLV("ADC Fine Volume Control Capture Volume", ADC3XXX_ADC_FGA,
4, 0, 4, 1, adc_fine_tlv),
SOC_SINGLE("Left ADC Unselected CM Bias Capture Switch",
ADC3XXX_LEFT_PGA_SEL_2, 6, 1, 0),
SOC_SINGLE("Right ADC Unselected CM Bias Capture Switch",
ADC3XXX_RIGHT_PGA_SEL_2, 6, 1, 0),
SOC_ENUM("Dither Control DC Offset", dither_dc_offset_enum),
/* Coefficient memory for miniDSP. */
/* For the default PRB_R1 processing block, the only available
* filter is the first order IIR.
*/
TI_COEFFICIENTS("Left ADC IIR Coefficients N0 N1 D1",
ADC3XXX_LEFT_ADC_IIR_COEFF_N0_MSB, 3),
TI_COEFFICIENTS("Right ADC IIR Coefficients N0 N1 D1",
ADC3XXX_RIGHT_ADC_IIR_COEFF_N0_MSB, 3),
};
/* Left input selection, Single Ended inputs and Differential inputs */
static const struct snd_kcontrol_new left_input_mixer_controls[] = {
SOC_DAPM_SINGLE("IN_1L Capture Switch",
ADC3XXX_LEFT_PGA_SEL_1, 1, 0x1, 1),
SOC_DAPM_SINGLE("IN_2L Capture Switch",
ADC3XXX_LEFT_PGA_SEL_1, 3, 0x1, 1),
SOC_DAPM_SINGLE("IN_3L Capture Switch",
ADC3XXX_LEFT_PGA_SEL_1, 5, 0x1, 1),
SOC_DAPM_SINGLE("DIF_2L_3L Capture Switch",
ADC3XXX_LEFT_PGA_SEL_1, 7, 0x1, 1),
SOC_DAPM_SINGLE("DIF_1L_1R Capture Switch",
ADC3XXX_LEFT_PGA_SEL_2, 5, 0x1, 1),
SOC_DAPM_SINGLE("DIF_2R_3R Capture Switch",
ADC3XXX_LEFT_PGA_SEL_2, 3, 0x1, 1),
SOC_DAPM_SINGLE("IN_1R Capture Switch",
ADC3XXX_LEFT_PGA_SEL_2, 1, 0x1, 1),
};
/* Right input selection, Single Ended inputs and Differential inputs */
static const struct snd_kcontrol_new right_input_mixer_controls[] = {
SOC_DAPM_SINGLE("IN_1R Capture Switch",
ADC3XXX_RIGHT_PGA_SEL_1, 1, 0x1, 1),
SOC_DAPM_SINGLE("IN_2R Capture Switch",
ADC3XXX_RIGHT_PGA_SEL_1, 3, 0x1, 1),
SOC_DAPM_SINGLE("IN_3R Capture Switch",
ADC3XXX_RIGHT_PGA_SEL_1, 5, 0x1, 1),
SOC_DAPM_SINGLE("DIF_2R_3R Capture Switch",
ADC3XXX_RIGHT_PGA_SEL_1, 7, 0x1, 1),
SOC_DAPM_SINGLE("DIF_1L_1R Capture Switch",
ADC3XXX_RIGHT_PGA_SEL_2, 5, 0x1, 1),
SOC_DAPM_SINGLE("DIF_2L_3L Capture Switch",
ADC3XXX_RIGHT_PGA_SEL_2, 3, 0x1, 1),
SOC_DAPM_SINGLE("IN_1L Capture Switch",
ADC3XXX_RIGHT_PGA_SEL_2, 1, 0x1, 1),
};
/* Left Digital Mic input for left ADC */
static const struct snd_kcontrol_new left_input_dmic_controls[] = {
SOC_DAPM_SINGLE("Left ADC Capture Switch",
ADC3XXX_ADC_DIGITAL, 3, 0x1, 0),
};
/* Right Digital Mic input for Right ADC */
static const struct snd_kcontrol_new right_input_dmic_controls[] = {
SOC_DAPM_SINGLE("Right ADC Capture Switch",
ADC3XXX_ADC_DIGITAL, 2, 0x1, 0),
};
/* DAPM widgets */
static const struct snd_soc_dapm_widget adc3xxx_dapm_widgets[] = {
/* Left Input Selection */
SND_SOC_DAPM_MIXER("Left Input", SND_SOC_NOPM, 0, 0,
&left_input_mixer_controls[0],
ARRAY_SIZE(left_input_mixer_controls)),
/* Right Input Selection */
SND_SOC_DAPM_MIXER("Right Input", SND_SOC_NOPM, 0, 0,
&right_input_mixer_controls[0],
ARRAY_SIZE(right_input_mixer_controls)),
/* PGA selection */
SND_SOC_DAPM_PGA("Left PGA", ADC3XXX_LEFT_APGA_CTRL, 7, 1, NULL, 0),
SND_SOC_DAPM_PGA("Right PGA", ADC3XXX_RIGHT_APGA_CTRL, 7, 1, NULL, 0),
/* Digital Microphone Input Control for Left/Right ADC */
SND_SOC_DAPM_MIXER("Left DMic Input", SND_SOC_NOPM, 0, 0,
&left_input_dmic_controls[0],
ARRAY_SIZE(left_input_dmic_controls)),
SND_SOC_DAPM_MIXER("Right DMic Input", SND_SOC_NOPM, 0, 0,
&right_input_dmic_controls[0],
ARRAY_SIZE(right_input_dmic_controls)),
/* Left/Right ADC */
SND_SOC_DAPM_ADC("Left ADC", "Left Capture", ADC3XXX_ADC_DIGITAL, 7, 0),
SND_SOC_DAPM_ADC("Right ADC", "Right Capture", ADC3XXX_ADC_DIGITAL, 6, 0),
/* Inputs */
SND_SOC_DAPM_INPUT("IN_1L"),
SND_SOC_DAPM_INPUT("IN_1R"),
SND_SOC_DAPM_INPUT("IN_2L"),
SND_SOC_DAPM_INPUT("IN_2R"),
SND_SOC_DAPM_INPUT("IN_3L"),
SND_SOC_DAPM_INPUT("IN_3R"),
SND_SOC_DAPM_INPUT("DIFL_1L_1R"),
SND_SOC_DAPM_INPUT("DIFL_2L_3L"),
SND_SOC_DAPM_INPUT("DIFL_2R_3R"),
SND_SOC_DAPM_INPUT("DIFR_1L_1R"),
SND_SOC_DAPM_INPUT("DIFR_2L_3L"),
SND_SOC_DAPM_INPUT("DIFR_2R_3R"),
SND_SOC_DAPM_INPUT("DMic_L"),
SND_SOC_DAPM_INPUT("DMic_R"),
/* Digital audio interface output */
SND_SOC_DAPM_AIF_OUT("AIF_OUT", "Capture", 0, SND_SOC_NOPM, 0, 0),
/* Clocks */
SND_SOC_DAPM_SUPPLY("PLL_CLK", ADC3XXX_PLL_PROG_PR, ADC3XXX_ENABLE_PLL_SHIFT,
0, adc3xxx_pll_delay, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY("ADC_CLK", ADC3XXX_ADC_NADC, ADC3XXX_ENABLE_NADC_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC_MOD_CLK", ADC3XXX_ADC_MADC, ADC3XXX_ENABLE_MADC_SHIFT,
0, NULL, 0),
/* This refers to the generated BCLK in master mode. */
SND_SOC_DAPM_SUPPLY("BCLK", ADC3XXX_BCLK_N_DIV, ADC3XXX_ENABLE_BCLK_SHIFT,
0, NULL, 0),
};
static const struct snd_soc_dapm_route adc3xxx_intercon[] = {
/* Left input selection from switches */
{ "Left Input", "IN_1L Capture Switch", "IN_1L" },
{ "Left Input", "IN_2L Capture Switch", "IN_2L" },
{ "Left Input", "IN_3L Capture Switch", "IN_3L" },
{ "Left Input", "DIF_2L_3L Capture Switch", "DIFL_2L_3L" },
{ "Left Input", "DIF_1L_1R Capture Switch", "DIFL_1L_1R" },
{ "Left Input", "DIF_2R_3R Capture Switch", "DIFL_2R_3R" },
{ "Left Input", "IN_1R Capture Switch", "IN_1R" },
/* Left input selection to left PGA */
{ "Left PGA", NULL, "Left Input" },
/* Left PGA to left ADC */
{ "Left ADC", NULL, "Left PGA" },
/* Right input selection from switches */
{ "Right Input", "IN_1R Capture Switch", "IN_1R" },
{ "Right Input", "IN_2R Capture Switch", "IN_2R" },
{ "Right Input", "IN_3R Capture Switch", "IN_3R" },
{ "Right Input", "DIF_2R_3R Capture Switch", "DIFR_2R_3R" },
{ "Right Input", "DIF_1L_1R Capture Switch", "DIFR_1L_1R" },
{ "Right Input", "DIF_2L_3L Capture Switch", "DIFR_2L_3L" },
{ "Right Input", "IN_1L Capture Switch", "IN_1L" },
/* Right input selection to right PGA */
{ "Right PGA", NULL, "Right Input" },
/* Right PGA to right ADC */
{ "Right ADC", NULL, "Right PGA" },
/* Left DMic Input selection from switch */
{ "Left DMic Input", "Left ADC Capture Switch", "DMic_L" },
/* Left DMic to left ADC */
{ "Left ADC", NULL, "Left DMic Input" },
/* Right DMic Input selection from switch */
{ "Right DMic Input", "Right ADC Capture Switch", "DMic_R" },
/* Right DMic to right ADC */
{ "Right ADC", NULL, "Right DMic Input" },
/* ADC to AIF output */
{ "AIF_OUT", NULL, "Left ADC" },
{ "AIF_OUT", NULL, "Right ADC" },
/* Clocking */
{ "ADC_MOD_CLK", NULL, "ADC_CLK" },
{ "Left ADC", NULL, "ADC_MOD_CLK" },
{ "Right ADC", NULL, "ADC_MOD_CLK" },
{ "BCLK", NULL, "ADC_CLK" },
};
static const struct snd_soc_dapm_route adc3xxx_pll_intercon[] = {
{ "ADC_CLK", NULL, "PLL_CLK" },
};
static const struct snd_soc_dapm_route adc3xxx_bclk_out_intercon[] = {
{ "AIF_OUT", NULL, "BCLK" }
};
static int adc3xxx_gpio_request(struct gpio_chip *chip, unsigned int offset)
{
struct adc3xxx *adc3xxx = gpiochip_get_data(chip);
if (offset >= ADC3XXX_GPIOS_MAX)
return -EINVAL;
/* GPIO1 is offset 0, GPIO2 is offset 1 */
/* We check here that the GPIO pins are either not configured in the
* DT, or that they purposely are set as outputs.
* (Input mode not yet implemented).
*/
if (adc3xxx->gpio_cfg[offset] != 0 &&
adc3xxx->gpio_cfg[offset] != ADC3XXX_GPIO_GPO + 1)
return -EINVAL;
return 0;
}
static int adc3xxx_gpio_direction_out(struct gpio_chip *chip,
unsigned int offset, int value)
{
struct adc3xxx *adc3xxx = gpiochip_get_data(chip);
/* Set GPIO output function. */
return regmap_update_bits(adc3xxx->regmap,
adc3xxx_gpio_ctrl_reg[offset],
ADC3XXX_GPIO_CTRL_CFG_MASK |
ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_MASK,
ADC3XXX_GPIO_GPO << ADC3XXX_GPIO_CTRL_CFG_SHIFT |
!!value << ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_SHIFT);
}
/* With only GPIO outputs configured, we never get the .direction_out call,
* so we set the output mode and output value in the same call. Hence
* .set in practice does the same thing as .direction_out .
*/
static void adc3xxx_gpio_set(struct gpio_chip *chip, unsigned int offset,
int value)
{
(void) adc3xxx_gpio_direction_out(chip, offset, value);
}
/* Even though we only support GPIO output for now, some GPIO clients
* want to read the current pin state using the .get callback.
*/
static int adc3xxx_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
struct adc3xxx *adc3xxx = gpiochip_get_data(chip);
unsigned int regval;
int ret;
/* We only allow output pins, so just read the value set in the output
* pin register field.
*/
ret = regmap_read(adc3xxx->regmap, adc3xxx_gpio_ctrl_reg[offset], ®val);
if (ret)
return ret;
return !!(regval & ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_MASK);
}
static const struct gpio_chip adc3xxx_gpio_chip = {
.label = "adc3xxx",
.owner = THIS_MODULE,
.request = adc3xxx_gpio_request,
.direction_output = adc3xxx_gpio_direction_out,
.set = adc3xxx_gpio_set,
.get = adc3xxx_gpio_get,
.can_sleep = 1,
};
static void adc3xxx_free_gpio(struct adc3xxx *adc3xxx)
{
#ifdef CONFIG_GPIOLIB
gpiochip_remove(&adc3xxx->gpio_chip);
#endif
}
static void adc3xxx_init_gpio(struct adc3xxx *adc3xxx)
{
int gpio, micbias;
int ret;
adc3xxx->gpio_chip = adc3xxx_gpio_chip;
adc3xxx->gpio_chip.ngpio = ADC3XXX_GPIOS_MAX;
adc3xxx->gpio_chip.parent = adc3xxx->dev;
adc3xxx->gpio_chip.base = -1;
ret = gpiochip_add_data(&adc3xxx->gpio_chip, adc3xxx);
if (ret)
dev_err(adc3xxx->dev, "Failed to add gpios: %d\n", ret);
/* Set up potential GPIO configuration from the devicetree.
* This allows us to set up things which are not software
* controllable GPIOs, such as PDM microphone I/O,
*/
for (gpio = 0; gpio < ADC3XXX_GPIOS_MAX; gpio++) {
unsigned int cfg = adc3xxx->gpio_cfg[gpio];
if (cfg) {
cfg--; /* actual value to use is stored +1 */
regmap_update_bits(adc3xxx->regmap,
adc3xxx_gpio_ctrl_reg[gpio],
ADC3XXX_GPIO_CTRL_CFG_MASK,
cfg << ADC3XXX_GPIO_CTRL_CFG_SHIFT);
}
}
/* Set up micbias voltage */
for (micbias = 0; micbias < ADC3XXX_MICBIAS_PINS; micbias++) {
unsigned int vg = adc3xxx->micbias_vg[micbias];
regmap_update_bits(adc3xxx->regmap,
ADC3XXX_MICBIAS_CTRL,
ADC3XXX_MICBIAS_MASK << adc3xxx_micbias_shift[micbias],
vg << adc3xxx_micbias_shift[micbias]);
}
}
static int adc3xxx_parse_dt_gpio(struct adc3xxx *adc3xxx,
const char *propname, unsigned int *cfg)
{
struct device *dev = adc3xxx->dev;
struct device_node *np = dev->of_node;
unsigned int val;
if (!of_property_read_u32(np, propname, &val)) {
if (val & ~15 || val == 7 || val >= 11) {
dev_err(dev, "Invalid property value for '%s'\n", propname);
return -EINVAL;
}
if (val == ADC3XXX_GPIO_GPI)
dev_warn(dev, "GPIO Input read not yet implemented\n");
*cfg = val + 1; /* 0 => not set up, all others shifted +1 */
}
return 0;
}
static int adc3xxx_parse_dt_micbias(struct adc3xxx *adc3xxx,
const char *propname, unsigned int *vg)
{
struct device *dev = adc3xxx->dev;
struct device_node *np = dev->of_node;
unsigned int val;
if (!of_property_read_u32(np, propname, &val)) {
if (val >= ADC3XXX_MICBIAS_AVDD) {
dev_err(dev, "Invalid property value for '%s'\n", propname);
return -EINVAL;
}
*vg = val;
}
return 0;
}
static int adc3xxx_parse_pll_mode(uint32_t val, unsigned int *pll_mode)
{
if (val != ADC3XXX_PLL_ENABLE && val != ADC3XXX_PLL_BYPASS &&
val != ADC3XXX_PLL_AUTO)
return -EINVAL;
*pll_mode = val;
return 0;
}
static void adc3xxx_setup_pll(struct snd_soc_component *component,
int div_entry)
{
int i = div_entry;
/* P & R values */
snd_soc_component_write(component, ADC3XXX_PLL_PROG_PR,
(adc3xxx_divs[i].pll_p << ADC3XXX_PLLP_SHIFT) |
(adc3xxx_divs[i].pll_r << ADC3XXX_PLLR_SHIFT));
/* J value */
snd_soc_component_write(component, ADC3XXX_PLL_PROG_J,
adc3xxx_divs[i].pll_j & ADC3XXX_PLLJ_MASK);
/* D value */
snd_soc_component_write(component, ADC3XXX_PLL_PROG_D_LSB,
adc3xxx_divs[i].pll_d & ADC3XXX_PLLD_LSB_MASK);
snd_soc_component_write(component, ADC3XXX_PLL_PROG_D_MSB,
(adc3xxx_divs[i].pll_d >> 8) & ADC3XXX_PLLD_MSB_MASK);
}
static int adc3xxx_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(dai->component);
struct adc3xxx *adc3xxx = snd_soc_component_get_drvdata(component);
int i, width = 16;
u8 iface_len, bdiv;
i = adc3xxx_get_divs(component->dev, adc3xxx->sysclk,
params_rate(params), adc3xxx->pll_mode);
if (i < 0)
return i;
/* select data word length */
switch (params_width(params)) {
case 16:
iface_len = ADC3XXX_IFACE_16BITS;
width = 16;
break;
case 20:
iface_len = ADC3XXX_IFACE_20BITS;
width = 20;
break;
case 24:
iface_len = ADC3XXX_IFACE_24BITS;
width = 24;
break;
case 32:
iface_len = ADC3XXX_IFACE_32BITS;
width = 32;
break;
default:
dev_err(component->dev, "Unsupported serial data format\n");
return -EINVAL;
}
snd_soc_component_update_bits(component, ADC3XXX_INTERFACE_CTRL_1,
ADC3XXX_WLENGTH_MASK, iface_len);
if (adc3xxx_divs[i].pll_p) { /* If PLL used for this mode */
adc3xxx_setup_pll(component, i);
snd_soc_component_write(component, ADC3XXX_CLKGEN_MUX, ADC3XXX_USE_PLL);
if (!adc3xxx->use_pll) {
snd_soc_dapm_add_routes(dapm, adc3xxx_pll_intercon,
ARRAY_SIZE(adc3xxx_pll_intercon));
adc3xxx->use_pll = 1;
}
} else {
snd_soc_component_write(component, ADC3XXX_CLKGEN_MUX, ADC3XXX_NO_PLL);
if (adc3xxx->use_pll) {
snd_soc_dapm_del_routes(dapm, adc3xxx_pll_intercon,
ARRAY_SIZE(adc3xxx_pll_intercon));
adc3xxx->use_pll = 0;
}
}
/* NADC */
snd_soc_component_update_bits(component, ADC3XXX_ADC_NADC,
ADC3XXX_NADC_MASK, adc3xxx_divs[i].nadc);
/* MADC */
snd_soc_component_update_bits(component, ADC3XXX_ADC_MADC,
ADC3XXX_MADC_MASK, adc3xxx_divs[i].madc);
/* AOSR */
snd_soc_component_update_bits(component, ADC3XXX_ADC_AOSR,
ADC3XXX_AOSR_MASK, adc3xxx_divs[i].aosr);
/* BDIV N Value */
/* BCLK is (by default) set up to be derived from ADC_CLK */
bdiv = (adc3xxx_divs[i].aosr * adc3xxx_divs[i].madc) / (2 * width);
snd_soc_component_update_bits(component, ADC3XXX_BCLK_N_DIV,
ADC3XXX_BDIV_MASK, bdiv);
return 0;
}
static const char *adc3xxx_pll_mode_text(int pll_mode)
{
switch (pll_mode) {
case ADC3XXX_PLL_AUTO:
return "PLL auto";
case ADC3XXX_PLL_ENABLE:
return "PLL enable";
case ADC3XXX_PLL_BYPASS:
return "PLL bypass";
default:
break;
}
return "PLL unknown";
}
static int adc3xxx_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct adc3xxx *adc3xxx = snd_soc_component_get_drvdata(component);
int ret;
ret = adc3xxx_parse_pll_mode(clk_id, &adc3xxx->pll_mode);
if (ret < 0)
return ret;
adc3xxx->sysclk = freq;
dev_dbg(component->dev, "Set sysclk to %u Hz, %s\n",
freq, adc3xxx_pll_mode_text(adc3xxx->pll_mode));
return 0;
}
static int adc3xxx_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct adc3xxx *adc3xxx = snd_soc_component_get_drvdata(component);
u8 clkdir = 0, format = 0;
int master = 0;
int ret;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
master = 1;
clkdir = ADC3XXX_BCLK_MASTER | ADC3XXX_WCLK_MASTER;
break;
case SND_SOC_DAIFMT_CBC_CFC:
master = 0;
break;
default:
dev_err(component->dev, "Invalid DAI clock setup\n");
return -EINVAL;
}
/*
* match both interface format and signal polarities since they
* are fixed
*/
switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_INV_MASK)) {
case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF:
format = ADC3XXX_FORMAT_I2S;
break;
case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF:
format = ADC3XXX_FORMAT_DSP;
break;
case SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF:
format = ADC3XXX_FORMAT_DSP;
break;
case SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF:
format = ADC3XXX_FORMAT_RJF;
break;
case SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF:
format = ADC3XXX_FORMAT_LJF;
break;
default:
dev_err(component->dev, "Invalid DAI format\n");
return -EINVAL;
}
/* Add/del route enabling BCLK output as applicable */
if (master && !adc3xxx->master)
snd_soc_dapm_add_routes(dapm, adc3xxx_bclk_out_intercon,
ARRAY_SIZE(adc3xxx_bclk_out_intercon));
else if (!master && adc3xxx->master)
snd_soc_dapm_del_routes(dapm, adc3xxx_bclk_out_intercon,
ARRAY_SIZE(adc3xxx_bclk_out_intercon));
adc3xxx->master = master;
/* set clock direction and format */
ret = snd_soc_component_update_bits(component,
ADC3XXX_INTERFACE_CTRL_1,
ADC3XXX_CLKDIR_MASK | ADC3XXX_FORMAT_MASK,
clkdir | format);
if (ret < 0)
return ret;
return 0;
}
static const struct snd_soc_dai_ops adc3xxx_dai_ops = {
.hw_params = adc3xxx_hw_params,
.set_sysclk = adc3xxx_set_dai_sysclk,
.set_fmt = adc3xxx_set_dai_fmt,
};
static struct snd_soc_dai_driver adc3xxx_dai = {
.name = "tlv320adc3xxx-hifi",
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = ADC3XXX_RATES,
.formats = ADC3XXX_FORMATS,
},
.ops = &adc3xxx_dai_ops,
};
static const struct snd_soc_component_driver soc_component_dev_adc3xxx = {
.controls = adc3xxx_snd_controls,
.num_controls = ARRAY_SIZE(adc3xxx_snd_controls),
.dapm_widgets = adc3xxx_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(adc3xxx_dapm_widgets),
.dapm_routes = adc3xxx_intercon,
.num_dapm_routes = ARRAY_SIZE(adc3xxx_intercon),
.endianness = 1,
};
static const struct i2c_device_id adc3xxx_i2c_id[] = {
{ "tlv320adc3001", ADC3001 },
{ "tlv320adc3101", ADC3101 },
{}
};
MODULE_DEVICE_TABLE(i2c, adc3xxx_i2c_id);
static int adc3xxx_i2c_probe(struct i2c_client *i2c)
{
struct device *dev = &i2c->dev;
struct adc3xxx *adc3xxx = NULL;
const struct i2c_device_id *id;
int ret;
adc3xxx = devm_kzalloc(dev, sizeof(struct adc3xxx), GFP_KERNEL);
if (!adc3xxx)
return -ENOMEM;
adc3xxx->dev = dev;
adc3xxx->rst_pin = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
if (IS_ERR(adc3xxx->rst_pin)) {
return dev_err_probe(dev, PTR_ERR(adc3xxx->rst_pin),
"Failed to request rst_pin\n");
}
adc3xxx->mclk = devm_clk_get(dev, NULL);
if (IS_ERR(adc3xxx->mclk)) {
/*
* The chip itself supports running off the BCLK either
* directly or via the PLL, but the driver does not (yet), so
* having a specified mclk is required. Otherwise, we could
* use the lack of a clocks property to indicate when BCLK is
* intended as the clock source.
*/
return dev_err_probe(dev, PTR_ERR(adc3xxx->mclk),
"Failed to acquire MCLK\n");
} else if (adc3xxx->mclk) {
ret = clk_prepare_enable(adc3xxx->mclk);
if (ret < 0)
return ret;
dev_dbg(dev, "Enabled MCLK, freq %lu Hz\n", clk_get_rate(adc3xxx->mclk));
}
ret = adc3xxx_parse_dt_gpio(adc3xxx, "ti,dmdin-gpio1", &adc3xxx->gpio_cfg[0]);
if (ret < 0)
goto err_unprepare_mclk;
ret = adc3xxx_parse_dt_gpio(adc3xxx, "ti,dmclk-gpio2", &adc3xxx->gpio_cfg[1]);
if (ret < 0)
goto err_unprepare_mclk;
ret = adc3xxx_parse_dt_micbias(adc3xxx, "ti,micbias1-vg", &adc3xxx->micbias_vg[0]);
if (ret < 0)
goto err_unprepare_mclk;
ret = adc3xxx_parse_dt_micbias(adc3xxx, "ti,micbias2-vg", &adc3xxx->micbias_vg[1]);
if (ret < 0)
goto err_unprepare_mclk;
adc3xxx->regmap = devm_regmap_init_i2c(i2c, &adc3xxx_regmap);
if (IS_ERR(adc3xxx->regmap)) {
ret = PTR_ERR(adc3xxx->regmap);
goto err_unprepare_mclk;
}
i2c_set_clientdata(i2c, adc3xxx);
id = i2c_match_id(adc3xxx_i2c_id, i2c);
adc3xxx->type = id->driver_data;
/* Reset codec chip */
gpiod_set_value_cansleep(adc3xxx->rst_pin, 1);
usleep_range(2000, 100000); /* Requirement: > 10 ns (datasheet p13) */
gpiod_set_value_cansleep(adc3xxx->rst_pin, 0);
/* Potentially set up pins used as GPIOs */
adc3xxx_init_gpio(adc3xxx);
ret = snd_soc_register_component(dev,
&soc_component_dev_adc3xxx, &adc3xxx_dai, 1);
if (ret < 0) {
dev_err(dev, "Failed to register codec: %d\n", ret);
goto err_unprepare_mclk;
}
return 0;
err_unprepare_mclk:
clk_disable_unprepare(adc3xxx->mclk);
return ret;
}
static void __exit adc3xxx_i2c_remove(struct i2c_client *client)
{
struct adc3xxx *adc3xxx = i2c_get_clientdata(client);
if (adc3xxx->mclk)
clk_disable_unprepare(adc3xxx->mclk);
adc3xxx_free_gpio(adc3xxx);
snd_soc_unregister_component(&client->dev);
}
static const struct of_device_id tlv320adc3xxx_of_match[] = {
{ .compatible = "ti,tlv320adc3001", },
{ .compatible = "ti,tlv320adc3101", },
{},
};
MODULE_DEVICE_TABLE(of, tlv320adc3xxx_of_match);
static struct i2c_driver adc3xxx_i2c_driver = {
.driver = {
.name = "tlv320adc3xxx-codec",
.of_match_table = tlv320adc3xxx_of_match,
},
.probe = adc3xxx_i2c_probe,
.remove = __exit_p(adc3xxx_i2c_remove),
.id_table = adc3xxx_i2c_id,
};
module_i2c_driver(adc3xxx_i2c_driver);
MODULE_DESCRIPTION("ASoC TLV320ADC3xxx codec driver");
MODULE_AUTHOR("[email protected]");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/tlv320adc3xxx.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* tas2552.c - ALSA SoC Texas Instruments TAS2552 Mono Audio Amplifier
*
* Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com
*
* Author: Dan Murphy <[email protected]>
*/
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/device.h>
#include <linux/i2c.h>
#include <linux/gpio.h>
#include <linux/of_gpio.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/gpio/consumer.h>
#include <linux/regulator/consumer.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/tlv.h>
#include <sound/tas2552-plat.h>
#include <dt-bindings/sound/tas2552.h>
#include "tas2552.h"
static const struct reg_default tas2552_reg_defs[] = {
{TAS2552_CFG_1, 0x22},
{TAS2552_CFG_3, 0x80},
{TAS2552_DOUT, 0x00},
{TAS2552_OUTPUT_DATA, 0xc0},
{TAS2552_PDM_CFG, 0x01},
{TAS2552_PGA_GAIN, 0x00},
{TAS2552_BOOST_APT_CTRL, 0x0f},
{TAS2552_RESERVED_0D, 0xbe},
{TAS2552_LIMIT_RATE_HYS, 0x08},
{TAS2552_CFG_2, 0xef},
{TAS2552_SER_CTRL_1, 0x00},
{TAS2552_SER_CTRL_2, 0x00},
{TAS2552_PLL_CTRL_1, 0x10},
{TAS2552_PLL_CTRL_2, 0x00},
{TAS2552_PLL_CTRL_3, 0x00},
{TAS2552_BTIP, 0x8f},
{TAS2552_BTS_CTRL, 0x80},
{TAS2552_LIMIT_RELEASE, 0x04},
{TAS2552_LIMIT_INT_COUNT, 0x00},
{TAS2552_EDGE_RATE_CTRL, 0x40},
{TAS2552_VBAT_DATA, 0x00},
};
#define TAS2552_NUM_SUPPLIES 3
static const char *tas2552_supply_names[TAS2552_NUM_SUPPLIES] = {
"vbat", /* vbat voltage */
"iovdd", /* I/O Voltage */
"avdd", /* Analog DAC Voltage */
};
struct tas2552_data {
struct snd_soc_component *component;
struct regmap *regmap;
struct i2c_client *tas2552_client;
struct regulator_bulk_data supplies[TAS2552_NUM_SUPPLIES];
struct gpio_desc *enable_gpio;
unsigned char regs[TAS2552_VBAT_DATA];
unsigned int pll_clkin;
int pll_clk_id;
unsigned int pdm_clk;
int pdm_clk_id;
unsigned int dai_fmt;
unsigned int tdm_delay;
};
static int tas2552_post_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_write(component, TAS2552_RESERVED_0D, 0xc0);
snd_soc_component_update_bits(component, TAS2552_LIMIT_RATE_HYS, (1 << 5),
(1 << 5));
snd_soc_component_update_bits(component, TAS2552_CFG_2, 1, 0);
snd_soc_component_update_bits(component, TAS2552_CFG_1, TAS2552_SWS, 0);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component, TAS2552_CFG_1, TAS2552_SWS,
TAS2552_SWS);
snd_soc_component_update_bits(component, TAS2552_CFG_2, 1, 1);
snd_soc_component_update_bits(component, TAS2552_LIMIT_RATE_HYS, (1 << 5), 0);
snd_soc_component_write(component, TAS2552_RESERVED_0D, 0xbe);
break;
}
return 0;
}
/* Input mux controls */
static const char * const tas2552_input_texts[] = {
"Digital", "Analog" };
static SOC_ENUM_SINGLE_DECL(tas2552_input_mux_enum, TAS2552_CFG_3, 7,
tas2552_input_texts);
static const struct snd_kcontrol_new tas2552_input_mux_control =
SOC_DAPM_ENUM("Route", tas2552_input_mux_enum);
static const struct snd_soc_dapm_widget tas2552_dapm_widgets[] =
{
SND_SOC_DAPM_INPUT("IN"),
/* MUX Controls */
SND_SOC_DAPM_MUX("Input selection", SND_SOC_NOPM, 0, 0,
&tas2552_input_mux_control),
SND_SOC_DAPM_AIF_IN("DAC IN", "DAC Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_OUT_DRV("ClassD", TAS2552_CFG_2, 7, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PLL", TAS2552_CFG_2, 3, 0, NULL, 0),
SND_SOC_DAPM_POST("Post Event", tas2552_post_event),
SND_SOC_DAPM_OUTPUT("OUT")
};
static const struct snd_soc_dapm_route tas2552_audio_map[] = {
{"DAC", NULL, "DAC IN"},
{"Input selection", "Digital", "DAC"},
{"Input selection", "Analog", "IN"},
{"ClassD", NULL, "Input selection"},
{"OUT", NULL, "ClassD"},
{"ClassD", NULL, "PLL"},
};
#ifdef CONFIG_PM
static void tas2552_sw_shutdown(struct tas2552_data *tas2552, int sw_shutdown)
{
u8 cfg1_reg = 0;
if (!tas2552->component)
return;
if (sw_shutdown)
cfg1_reg = TAS2552_SWS;
snd_soc_component_update_bits(tas2552->component, TAS2552_CFG_1, TAS2552_SWS,
cfg1_reg);
}
#endif
static int tas2552_setup_pll(struct snd_soc_component *component,
struct snd_pcm_hw_params *params)
{
struct tas2552_data *tas2552 = dev_get_drvdata(component->dev);
bool bypass_pll = false;
unsigned int pll_clk = params_rate(params) * 512;
unsigned int pll_clkin = tas2552->pll_clkin;
u8 pll_enable;
if (!pll_clkin) {
if (tas2552->pll_clk_id != TAS2552_PLL_CLKIN_BCLK)
return -EINVAL;
pll_clkin = snd_soc_params_to_bclk(params);
pll_clkin += tas2552->tdm_delay;
}
pll_enable = snd_soc_component_read(component, TAS2552_CFG_2) & TAS2552_PLL_ENABLE;
snd_soc_component_update_bits(component, TAS2552_CFG_2, TAS2552_PLL_ENABLE, 0);
if (pll_clkin == pll_clk)
bypass_pll = true;
if (bypass_pll) {
/* By pass the PLL configuration */
snd_soc_component_update_bits(component, TAS2552_PLL_CTRL_2,
TAS2552_PLL_BYPASS, TAS2552_PLL_BYPASS);
} else {
/* Fill in the PLL control registers for J & D
* pll_clk = (.5 * pll_clkin * J.D) / 2^p
* Need to fill in J and D here based on incoming freq
*/
unsigned int d, q, t;
u8 j;
u8 pll_sel = (tas2552->pll_clk_id << 3) & TAS2552_PLL_SRC_MASK;
u8 p = snd_soc_component_read(component, TAS2552_PLL_CTRL_1);
p = (p >> 7);
recalc:
t = (pll_clk * 2) << p;
j = t / pll_clkin;
d = t % pll_clkin;
t = pll_clkin / 10000;
q = d / (t + 1);
d = q + ((9999 - pll_clkin % 10000) * (d / t - q)) / 10000;
if (d && (pll_clkin < 512000 || pll_clkin > 9200000)) {
if (tas2552->pll_clk_id == TAS2552_PLL_CLKIN_BCLK) {
pll_clkin = 1800000;
pll_sel = (TAS2552_PLL_CLKIN_1_8_FIXED << 3) &
TAS2552_PLL_SRC_MASK;
} else {
pll_clkin = snd_soc_params_to_bclk(params);
pll_clkin += tas2552->tdm_delay;
pll_sel = (TAS2552_PLL_CLKIN_BCLK << 3) &
TAS2552_PLL_SRC_MASK;
}
goto recalc;
}
snd_soc_component_update_bits(component, TAS2552_CFG_1, TAS2552_PLL_SRC_MASK,
pll_sel);
snd_soc_component_update_bits(component, TAS2552_PLL_CTRL_1,
TAS2552_PLL_J_MASK, j);
/* Will clear the PLL_BYPASS bit */
snd_soc_component_write(component, TAS2552_PLL_CTRL_2,
TAS2552_PLL_D_UPPER(d));
snd_soc_component_write(component, TAS2552_PLL_CTRL_3,
TAS2552_PLL_D_LOWER(d));
}
/* Restore PLL status */
snd_soc_component_update_bits(component, TAS2552_CFG_2, TAS2552_PLL_ENABLE,
pll_enable);
return 0;
}
static int tas2552_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct tas2552_data *tas2552 = dev_get_drvdata(component->dev);
int cpf;
u8 ser_ctrl1_reg, wclk_rate;
switch (params_width(params)) {
case 16:
ser_ctrl1_reg = TAS2552_WORDLENGTH_16BIT;
cpf = 32 + tas2552->tdm_delay;
break;
case 20:
ser_ctrl1_reg = TAS2552_WORDLENGTH_20BIT;
cpf = 64 + tas2552->tdm_delay;
break;
case 24:
ser_ctrl1_reg = TAS2552_WORDLENGTH_24BIT;
cpf = 64 + tas2552->tdm_delay;
break;
case 32:
ser_ctrl1_reg = TAS2552_WORDLENGTH_32BIT;
cpf = 64 + tas2552->tdm_delay;
break;
default:
dev_err(component->dev, "Not supported sample size: %d\n",
params_width(params));
return -EINVAL;
}
if (cpf <= 32)
ser_ctrl1_reg |= TAS2552_CLKSPERFRAME_32;
else if (cpf <= 64)
ser_ctrl1_reg |= TAS2552_CLKSPERFRAME_64;
else if (cpf <= 128)
ser_ctrl1_reg |= TAS2552_CLKSPERFRAME_128;
else
ser_ctrl1_reg |= TAS2552_CLKSPERFRAME_256;
snd_soc_component_update_bits(component, TAS2552_SER_CTRL_1,
TAS2552_WORDLENGTH_MASK | TAS2552_CLKSPERFRAME_MASK,
ser_ctrl1_reg);
switch (params_rate(params)) {
case 8000:
wclk_rate = TAS2552_WCLK_FREQ_8KHZ;
break;
case 11025:
case 12000:
wclk_rate = TAS2552_WCLK_FREQ_11_12KHZ;
break;
case 16000:
wclk_rate = TAS2552_WCLK_FREQ_16KHZ;
break;
case 22050:
case 24000:
wclk_rate = TAS2552_WCLK_FREQ_22_24KHZ;
break;
case 32000:
wclk_rate = TAS2552_WCLK_FREQ_32KHZ;
break;
case 44100:
case 48000:
wclk_rate = TAS2552_WCLK_FREQ_44_48KHZ;
break;
case 88200:
case 96000:
wclk_rate = TAS2552_WCLK_FREQ_88_96KHZ;
break;
case 176400:
case 192000:
wclk_rate = TAS2552_WCLK_FREQ_176_192KHZ;
break;
default:
dev_err(component->dev, "Not supported sample rate: %d\n",
params_rate(params));
return -EINVAL;
}
snd_soc_component_update_bits(component, TAS2552_CFG_3, TAS2552_WCLK_FREQ_MASK,
wclk_rate);
return tas2552_setup_pll(component, params);
}
#define TAS2552_DAI_FMT_MASK (TAS2552_BCLKDIR | \
TAS2552_WCLKDIR | \
TAS2552_DATAFORMAT_MASK)
static int tas2552_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct tas2552_data *tas2552 = snd_soc_component_get_drvdata(component);
int delay = 0;
/* TDM slot selection only valid in DSP_A/_B mode */
if (tas2552->dai_fmt == SND_SOC_DAIFMT_DSP_A)
delay += (tas2552->tdm_delay + 1);
else if (tas2552->dai_fmt == SND_SOC_DAIFMT_DSP_B)
delay += tas2552->tdm_delay;
/* Configure data delay */
snd_soc_component_write(component, TAS2552_SER_CTRL_2, delay);
return 0;
}
static int tas2552_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct tas2552_data *tas2552 = dev_get_drvdata(component->dev);
u8 serial_format;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC:
serial_format = 0x00;
break;
case SND_SOC_DAIFMT_CBC_CFP:
serial_format = TAS2552_WCLKDIR;
break;
case SND_SOC_DAIFMT_CBP_CFC:
serial_format = TAS2552_BCLKDIR;
break;
case SND_SOC_DAIFMT_CBP_CFP:
serial_format = (TAS2552_BCLKDIR | TAS2552_WCLKDIR);
break;
default:
dev_vdbg(component->dev, "DAI Format master is not found\n");
return -EINVAL;
}
switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
SND_SOC_DAIFMT_INV_MASK)) {
case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
break;
case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
serial_format |= TAS2552_DATAFORMAT_DSP;
break;
case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
serial_format |= TAS2552_DATAFORMAT_RIGHT_J;
break;
case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
serial_format |= TAS2552_DATAFORMAT_LEFT_J;
break;
default:
dev_vdbg(component->dev, "DAI Format is not found\n");
return -EINVAL;
}
tas2552->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
snd_soc_component_update_bits(component, TAS2552_SER_CTRL_1, TAS2552_DAI_FMT_MASK,
serial_format);
return 0;
}
static int tas2552_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct tas2552_data *tas2552 = dev_get_drvdata(component->dev);
u8 reg, mask, val;
switch (clk_id) {
case TAS2552_PLL_CLKIN_MCLK:
case TAS2552_PLL_CLKIN_IVCLKIN:
if (freq < 512000 || freq > 24576000) {
/* out of range PLL_CLKIN, fall back to use BCLK */
dev_warn(component->dev, "Out of range PLL_CLKIN: %u\n",
freq);
clk_id = TAS2552_PLL_CLKIN_BCLK;
freq = 0;
}
fallthrough;
case TAS2552_PLL_CLKIN_BCLK:
case TAS2552_PLL_CLKIN_1_8_FIXED:
mask = TAS2552_PLL_SRC_MASK;
val = (clk_id << 3) & mask; /* bit 4:5 in the register */
reg = TAS2552_CFG_1;
tas2552->pll_clk_id = clk_id;
tas2552->pll_clkin = freq;
break;
case TAS2552_PDM_CLK_PLL:
case TAS2552_PDM_CLK_IVCLKIN:
case TAS2552_PDM_CLK_BCLK:
case TAS2552_PDM_CLK_MCLK:
mask = TAS2552_PDM_CLK_SEL_MASK;
val = (clk_id >> 1) & mask; /* bit 0:1 in the register */
reg = TAS2552_PDM_CFG;
tas2552->pdm_clk_id = clk_id;
tas2552->pdm_clk = freq;
break;
default:
dev_err(component->dev, "Invalid clk id: %d\n", clk_id);
return -EINVAL;
}
snd_soc_component_update_bits(component, reg, mask, val);
return 0;
}
static int tas2552_set_dai_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask,
int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
struct tas2552_data *tas2552 = snd_soc_component_get_drvdata(component);
unsigned int lsb;
if (unlikely(!tx_mask)) {
dev_err(component->dev, "tx masks need to be non 0\n");
return -EINVAL;
}
/* TDM based on DSP mode requires slots to be adjacent */
lsb = __ffs(tx_mask);
if ((lsb + 1) != __fls(tx_mask)) {
dev_err(component->dev, "Invalid mask, slots must be adjacent\n");
return -EINVAL;
}
tas2552->tdm_delay = lsb * slot_width;
/* DOUT in high-impedance on inactive bit clocks */
snd_soc_component_update_bits(component, TAS2552_DOUT,
TAS2552_SDOUT_TRISTATE, TAS2552_SDOUT_TRISTATE);
return 0;
}
static int tas2552_mute(struct snd_soc_dai *dai, int mute, int direction)
{
u8 cfg1_reg = 0;
struct snd_soc_component *component = dai->component;
if (mute)
cfg1_reg |= TAS2552_MUTE;
snd_soc_component_update_bits(component, TAS2552_CFG_1, TAS2552_MUTE, cfg1_reg);
return 0;
}
#ifdef CONFIG_PM
static int tas2552_runtime_suspend(struct device *dev)
{
struct tas2552_data *tas2552 = dev_get_drvdata(dev);
tas2552_sw_shutdown(tas2552, 1);
regcache_cache_only(tas2552->regmap, true);
regcache_mark_dirty(tas2552->regmap);
gpiod_set_value(tas2552->enable_gpio, 0);
return 0;
}
static int tas2552_runtime_resume(struct device *dev)
{
struct tas2552_data *tas2552 = dev_get_drvdata(dev);
gpiod_set_value(tas2552->enable_gpio, 1);
tas2552_sw_shutdown(tas2552, 0);
regcache_cache_only(tas2552->regmap, false);
regcache_sync(tas2552->regmap);
return 0;
}
#endif
static const struct dev_pm_ops tas2552_pm = {
SET_RUNTIME_PM_OPS(tas2552_runtime_suspend, tas2552_runtime_resume,
NULL)
};
static const struct snd_soc_dai_ops tas2552_speaker_dai_ops = {
.hw_params = tas2552_hw_params,
.prepare = tas2552_prepare,
.set_sysclk = tas2552_set_dai_sysclk,
.set_fmt = tas2552_set_dai_fmt,
.set_tdm_slot = tas2552_set_dai_tdm_slot,
.mute_stream = tas2552_mute,
.no_capture_mute = 1,
};
/* Formats supported by TAS2552 driver. */
#define TAS2552_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
/* TAS2552 dai structure. */
static struct snd_soc_dai_driver tas2552_dai[] = {
{
.name = "tas2552-amplifier",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = TAS2552_FORMATS,
},
.ops = &tas2552_speaker_dai_ops,
},
};
/*
* DAC digital volumes. From -7 to 24 dB in 1 dB steps
*/
static DECLARE_TLV_DB_SCALE(dac_tlv, -700, 100, 0);
static const char * const tas2552_din_source_select[] = {
"Muted",
"Left",
"Right",
"Left + Right average",
};
static SOC_ENUM_SINGLE_DECL(tas2552_din_source_enum,
TAS2552_CFG_3, 3,
tas2552_din_source_select);
static const struct snd_kcontrol_new tas2552_snd_controls[] = {
SOC_SINGLE_TLV("Speaker Driver Playback Volume",
TAS2552_PGA_GAIN, 0, 0x1f, 0, dac_tlv),
SOC_ENUM("DIN source", tas2552_din_source_enum),
};
static int tas2552_component_probe(struct snd_soc_component *component)
{
struct tas2552_data *tas2552 = snd_soc_component_get_drvdata(component);
int ret;
tas2552->component = component;
ret = regulator_bulk_enable(ARRAY_SIZE(tas2552->supplies),
tas2552->supplies);
if (ret != 0) {
dev_err(component->dev, "Failed to enable supplies: %d\n",
ret);
return ret;
}
gpiod_set_value(tas2552->enable_gpio, 1);
ret = pm_runtime_resume_and_get(component->dev);
if (ret < 0) {
dev_err(component->dev, "Enabling device failed: %d\n",
ret);
goto probe_fail;
}
snd_soc_component_update_bits(component, TAS2552_CFG_1, TAS2552_MUTE, TAS2552_MUTE);
snd_soc_component_write(component, TAS2552_CFG_3, TAS2552_I2S_OUT_SEL |
TAS2552_DIN_SRC_SEL_AVG_L_R);
snd_soc_component_write(component, TAS2552_OUTPUT_DATA,
TAS2552_PDM_DATA_SEL_V_I |
TAS2552_R_DATA_OUT(TAS2552_DATA_OUT_V_DATA));
snd_soc_component_write(component, TAS2552_BOOST_APT_CTRL, TAS2552_APT_DELAY_200 |
TAS2552_APT_THRESH_20_17);
snd_soc_component_write(component, TAS2552_CFG_2, TAS2552_BOOST_EN | TAS2552_APT_EN |
TAS2552_LIM_EN);
return 0;
probe_fail:
pm_runtime_put_noidle(component->dev);
gpiod_set_value(tas2552->enable_gpio, 0);
regulator_bulk_disable(ARRAY_SIZE(tas2552->supplies),
tas2552->supplies);
return ret;
}
static void tas2552_component_remove(struct snd_soc_component *component)
{
struct tas2552_data *tas2552 = snd_soc_component_get_drvdata(component);
pm_runtime_put(component->dev);
gpiod_set_value(tas2552->enable_gpio, 0);
};
#ifdef CONFIG_PM
static int tas2552_suspend(struct snd_soc_component *component)
{
struct tas2552_data *tas2552 = snd_soc_component_get_drvdata(component);
int ret;
ret = regulator_bulk_disable(ARRAY_SIZE(tas2552->supplies),
tas2552->supplies);
if (ret != 0)
dev_err(component->dev, "Failed to disable supplies: %d\n",
ret);
return ret;
}
static int tas2552_resume(struct snd_soc_component *component)
{
struct tas2552_data *tas2552 = snd_soc_component_get_drvdata(component);
int ret;
ret = regulator_bulk_enable(ARRAY_SIZE(tas2552->supplies),
tas2552->supplies);
if (ret != 0) {
dev_err(component->dev, "Failed to enable supplies: %d\n",
ret);
}
return ret;
}
#else
#define tas2552_suspend NULL
#define tas2552_resume NULL
#endif
static const struct snd_soc_component_driver soc_component_dev_tas2552 = {
.probe = tas2552_component_probe,
.remove = tas2552_component_remove,
.suspend = tas2552_suspend,
.resume = tas2552_resume,
.controls = tas2552_snd_controls,
.num_controls = ARRAY_SIZE(tas2552_snd_controls),
.dapm_widgets = tas2552_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(tas2552_dapm_widgets),
.dapm_routes = tas2552_audio_map,
.num_dapm_routes = ARRAY_SIZE(tas2552_audio_map),
.idle_bias_on = 1,
.endianness = 1,
};
static const struct regmap_config tas2552_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = TAS2552_MAX_REG,
.reg_defaults = tas2552_reg_defs,
.num_reg_defaults = ARRAY_SIZE(tas2552_reg_defs),
.cache_type = REGCACHE_RBTREE,
};
static int tas2552_probe(struct i2c_client *client)
{
struct device *dev;
struct tas2552_data *data;
int ret;
int i;
dev = &client->dev;
data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
if (data == NULL)
return -ENOMEM;
data->enable_gpio = devm_gpiod_get_optional(dev, "enable",
GPIOD_OUT_LOW);
if (IS_ERR(data->enable_gpio))
return PTR_ERR(data->enable_gpio);
data->tas2552_client = client;
data->regmap = devm_regmap_init_i2c(client, &tas2552_regmap_config);
if (IS_ERR(data->regmap)) {
ret = PTR_ERR(data->regmap);
dev_err(&client->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
for (i = 0; i < ARRAY_SIZE(data->supplies); i++)
data->supplies[i].supply = tas2552_supply_names[i];
ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(data->supplies),
data->supplies);
if (ret != 0) {
dev_err(dev, "Failed to request supplies: %d\n", ret);
return ret;
}
pm_runtime_set_active(&client->dev);
pm_runtime_set_autosuspend_delay(&client->dev, 1000);
pm_runtime_use_autosuspend(&client->dev);
pm_runtime_enable(&client->dev);
pm_runtime_mark_last_busy(&client->dev);
pm_runtime_put_sync_autosuspend(&client->dev);
dev_set_drvdata(&client->dev, data);
ret = devm_snd_soc_register_component(&client->dev,
&soc_component_dev_tas2552,
tas2552_dai, ARRAY_SIZE(tas2552_dai));
if (ret < 0) {
dev_err(&client->dev, "Failed to register component: %d\n", ret);
pm_runtime_get_noresume(&client->dev);
}
return ret;
}
static void tas2552_i2c_remove(struct i2c_client *client)
{
pm_runtime_disable(&client->dev);
}
static const struct i2c_device_id tas2552_id[] = {
{ "tas2552", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, tas2552_id);
#if IS_ENABLED(CONFIG_OF)
static const struct of_device_id tas2552_of_match[] = {
{ .compatible = "ti,tas2552", },
{},
};
MODULE_DEVICE_TABLE(of, tas2552_of_match);
#endif
static struct i2c_driver tas2552_i2c_driver = {
.driver = {
.name = "tas2552",
.of_match_table = of_match_ptr(tas2552_of_match),
.pm = &tas2552_pm,
},
.probe = tas2552_probe,
.remove = tas2552_i2c_remove,
.id_table = tas2552_id,
};
module_i2c_driver(tas2552_i2c_driver);
MODULE_AUTHOR("Dan Muprhy <[email protected]>");
MODULE_DESCRIPTION("TAS2552 Audio amplifier driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/tas2552.c |
// SPDX-License-Identifier: GPL-2.0
/*
* rt715-sdw.c -- rt715 ALSA SoC audio driver
*
* Copyright(c) 2019 Realtek Semiconductor Corp.
*
* ALC715 ASoC Codec Driver based Intel Dummy SdW codec driver
*
*/
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/mod_devicetable.h>
#include <linux/soundwire/sdw.h>
#include <linux/soundwire/sdw_type.h>
#include <linux/soundwire/sdw_registers.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include "rt715.h"
#include "rt715-sdw.h"
static bool rt715_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x00e0 ... 0x00e5:
case 0x00ee ... 0x00ef:
case 0x00f0 ... 0x00f5:
case 0x00fe ... 0x00ff:
case 0x02e0:
case 0x02f0:
case 0x04e0:
case 0x04f0:
case 0x06e0:
case 0x06f0:
case 0x2000 ... 0x2016:
case 0x201a ... 0x2027:
case 0x2029 ... 0x202a:
case 0x202d ... 0x2034:
case 0x2200 ... 0x2204:
case 0x2206 ... 0x2212:
case 0x2220 ... 0x2223:
case 0x2230 ... 0x2239:
case 0x22f0 ... 0x22f3:
case 0x3122:
case 0x3123:
case 0x3124:
case 0x3125:
case 0x3607:
case 0x3608:
case 0x3609:
case 0x3610:
case 0x3611:
case 0x3627:
case 0x3712:
case 0x3713:
case 0x3718:
case 0x3719:
case 0x371a:
case 0x371b:
case 0x371d:
case 0x3729:
case 0x385e:
case 0x3859:
case 0x4c12:
case 0x4c13:
case 0x4c1d:
case 0x4c29:
case 0x4d12:
case 0x4d13:
case 0x4d1d:
case 0x4d29:
case 0x4e12:
case 0x4e13:
case 0x4e1d:
case 0x4e29:
case 0x4f12:
case 0x4f13:
case 0x4f1d:
case 0x4f29:
case 0x7207:
case 0x7208:
case 0x7209:
case 0x7227:
case 0x7307:
case 0x7308:
case 0x7309:
case 0x7312:
case 0x7313:
case 0x7318:
case 0x7319:
case 0x731a:
case 0x731b:
case 0x731d:
case 0x7327:
case 0x7329:
case 0x8287:
case 0x8288:
case 0x8289:
case 0x82a7:
case 0x8387:
case 0x8388:
case 0x8389:
case 0x8392:
case 0x8393:
case 0x8398:
case 0x8399:
case 0x839a:
case 0x839b:
case 0x839d:
case 0x83a7:
case 0x83a9:
case 0x752039:
return true;
default:
return false;
}
}
static bool rt715_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x00e5:
case 0x00f0:
case 0x00f3:
case 0x00f5:
case 0x2009:
case 0x2016:
case 0x201b:
case 0x201c:
case 0x201d:
case 0x201f:
case 0x2023:
case 0x2230:
case 0x200b ... 0x200e: /* i2c read */
case 0x2012 ... 0x2015: /* HD-A read */
case 0x202d ... 0x202f: /* BRA */
case 0x2201 ... 0x2212: /* i2c debug */
case 0x2220 ... 0x2223: /* decoded HD-A */
return true;
default:
return false;
}
}
static int rt715_sdw_read(void *context, unsigned int reg, unsigned int *val)
{
struct device *dev = context;
struct rt715_priv *rt715 = dev_get_drvdata(dev);
unsigned int sdw_data_3, sdw_data_2, sdw_data_1, sdw_data_0;
unsigned int reg2 = 0, reg3 = 0, reg4 = 0, mask, nid, val2;
unsigned int is_hda_reg = 1, is_index_reg = 0;
int ret;
if (reg > 0xffff)
is_index_reg = 1;
mask = reg & 0xf000;
if (is_index_reg) { /* index registers */
val2 = reg & 0xff;
reg = reg >> 8;
nid = reg & 0xff;
ret = regmap_write(rt715->sdw_regmap, reg, 0);
if (ret < 0)
return ret;
reg2 = reg + 0x1000;
reg2 |= 0x80;
ret = regmap_write(rt715->sdw_regmap, reg2, val2);
if (ret < 0)
return ret;
reg3 = RT715_PRIV_DATA_R_H | nid;
ret = regmap_write(rt715->sdw_regmap, reg3,
((*val >> 8) & 0xff));
if (ret < 0)
return ret;
reg4 = reg3 + 0x1000;
reg4 |= 0x80;
ret = regmap_write(rt715->sdw_regmap, reg4, (*val & 0xff));
if (ret < 0)
return ret;
} else if (mask == 0x3000) {
reg += 0x8000;
ret = regmap_write(rt715->sdw_regmap, reg, *val);
if (ret < 0)
return ret;
} else if (mask == 0x7000) {
reg += 0x2000;
reg |= 0x800;
ret = regmap_write(rt715->sdw_regmap, reg,
((*val >> 8) & 0xff));
if (ret < 0)
return ret;
reg2 = reg + 0x1000;
reg2 |= 0x80;
ret = regmap_write(rt715->sdw_regmap, reg2, (*val & 0xff));
if (ret < 0)
return ret;
} else if ((reg & 0xff00) == 0x8300) { /* for R channel */
reg2 = reg - 0x1000;
reg2 &= ~0x80;
ret = regmap_write(rt715->sdw_regmap, reg2,
((*val >> 8) & 0xff));
if (ret < 0)
return ret;
ret = regmap_write(rt715->sdw_regmap, reg, (*val & 0xff));
if (ret < 0)
return ret;
} else if (mask == 0x9000) {
ret = regmap_write(rt715->sdw_regmap, reg,
((*val >> 8) & 0xff));
if (ret < 0)
return ret;
reg2 = reg + 0x1000;
reg2 |= 0x80;
ret = regmap_write(rt715->sdw_regmap, reg2, (*val & 0xff));
if (ret < 0)
return ret;
} else if (mask == 0xb000) {
ret = regmap_write(rt715->sdw_regmap, reg, *val);
if (ret < 0)
return ret;
} else {
ret = regmap_read(rt715->sdw_regmap, reg, val);
if (ret < 0)
return ret;
is_hda_reg = 0;
}
if (is_hda_reg || is_index_reg) {
sdw_data_3 = 0;
sdw_data_2 = 0;
sdw_data_1 = 0;
sdw_data_0 = 0;
ret = regmap_read(rt715->sdw_regmap, RT715_READ_HDA_3,
&sdw_data_3);
if (ret < 0)
return ret;
ret = regmap_read(rt715->sdw_regmap, RT715_READ_HDA_2,
&sdw_data_2);
if (ret < 0)
return ret;
ret = regmap_read(rt715->sdw_regmap, RT715_READ_HDA_1,
&sdw_data_1);
if (ret < 0)
return ret;
ret = regmap_read(rt715->sdw_regmap, RT715_READ_HDA_0,
&sdw_data_0);
if (ret < 0)
return ret;
*val = ((sdw_data_3 & 0xff) << 24) |
((sdw_data_2 & 0xff) << 16) |
((sdw_data_1 & 0xff) << 8) | (sdw_data_0 & 0xff);
}
if (is_hda_reg == 0)
dev_dbg(dev, "[%s] %04x => %08x\n", __func__, reg, *val);
else if (is_index_reg)
dev_dbg(dev, "[%s] %04x %04x %04x %04x => %08x\n", __func__,
reg, reg2, reg3, reg4, *val);
else
dev_dbg(dev, "[%s] %04x %04x => %08x\n",
__func__, reg, reg2, *val);
return 0;
}
static int rt715_sdw_write(void *context, unsigned int reg, unsigned int val)
{
struct device *dev = context;
struct rt715_priv *rt715 = dev_get_drvdata(dev);
unsigned int reg2 = 0, reg3, reg4, nid, mask, val2;
unsigned int is_index_reg = 0;
int ret;
if (reg > 0xffff)
is_index_reg = 1;
mask = reg & 0xf000;
if (is_index_reg) { /* index registers */
val2 = reg & 0xff;
reg = reg >> 8;
nid = reg & 0xff;
ret = regmap_write(rt715->sdw_regmap, reg, 0);
if (ret < 0)
return ret;
reg2 = reg + 0x1000;
reg2 |= 0x80;
ret = regmap_write(rt715->sdw_regmap, reg2, val2);
if (ret < 0)
return ret;
reg3 = RT715_PRIV_DATA_W_H | nid;
ret = regmap_write(rt715->sdw_regmap, reg3,
((val >> 8) & 0xff));
if (ret < 0)
return ret;
reg4 = reg3 + 0x1000;
reg4 |= 0x80;
ret = regmap_write(rt715->sdw_regmap, reg4, (val & 0xff));
if (ret < 0)
return ret;
is_index_reg = 1;
} else if (reg < 0x4fff) {
ret = regmap_write(rt715->sdw_regmap, reg, val);
if (ret < 0)
return ret;
} else if (reg == RT715_FUNC_RESET) {
ret = regmap_write(rt715->sdw_regmap, reg, val);
if (ret < 0)
return ret;
} else if (mask == 0x7000) {
ret = regmap_write(rt715->sdw_regmap, reg,
((val >> 8) & 0xff));
if (ret < 0)
return ret;
reg2 = reg + 0x1000;
reg2 |= 0x80;
ret = regmap_write(rt715->sdw_regmap, reg2, (val & 0xff));
if (ret < 0)
return ret;
} else if ((reg & 0xff00) == 0x8300) { /* for R channel */
reg2 = reg - 0x1000;
reg2 &= ~0x80;
ret = regmap_write(rt715->sdw_regmap, reg2,
((val >> 8) & 0xff));
if (ret < 0)
return ret;
ret = regmap_write(rt715->sdw_regmap, reg, (val & 0xff));
if (ret < 0)
return ret;
}
if (reg2 == 0)
dev_dbg(dev, "[%s] %04x <= %04x\n", __func__, reg, val);
else if (is_index_reg)
dev_dbg(dev, "[%s] %04x %04x %04x %04x <= %04x %04x\n",
__func__, reg, reg2, reg3, reg4, val2, val);
else
dev_dbg(dev, "[%s] %04x %04x <= %04x\n",
__func__, reg, reg2, val);
return 0;
}
static const struct regmap_config rt715_regmap = {
.reg_bits = 24,
.val_bits = 32,
.readable_reg = rt715_readable_register, /* Readable registers */
.volatile_reg = rt715_volatile_register, /* volatile register */
.max_register = 0x752039, /* Maximum number of register */
.reg_defaults = rt715_reg_defaults, /* Defaults */
.num_reg_defaults = ARRAY_SIZE(rt715_reg_defaults),
.cache_type = REGCACHE_MAPLE,
.use_single_read = true,
.use_single_write = true,
.reg_read = rt715_sdw_read,
.reg_write = rt715_sdw_write,
};
static const struct regmap_config rt715_sdw_regmap = {
.name = "sdw",
.reg_bits = 32, /* Total register space for SDW */
.val_bits = 8, /* Total number of bits in register */
.max_register = 0xff01, /* Maximum number of register */
.cache_type = REGCACHE_NONE,
.use_single_read = true,
.use_single_write = true,
};
int hda_to_sdw(unsigned int nid, unsigned int verb, unsigned int payload,
unsigned int *sdw_addr_h, unsigned int *sdw_data_h,
unsigned int *sdw_addr_l, unsigned int *sdw_data_l)
{
unsigned int offset_h, offset_l, e_verb;
if (((verb & 0xff) != 0) || verb == 0xf00) { /* 12 bits command */
if (verb == 0x7ff) /* special case */
offset_h = 0;
else
offset_h = 0x3000;
if (verb & 0x800) /* get command */
e_verb = (verb - 0xf00) | 0x80;
else /* set command */
e_verb = (verb - 0x700);
*sdw_data_h = payload; /* 7 bits payload */
*sdw_addr_l = *sdw_data_l = 0;
} else { /* 4 bits command */
if ((verb & 0x800) == 0x800) { /* read */
offset_h = 0x9000;
offset_l = 0xa000;
} else { /* write */
offset_h = 0x7000;
offset_l = 0x8000;
}
e_verb = verb >> 8;
*sdw_data_h = (payload >> 8); /* 16 bits payload [15:8] */
*sdw_addr_l = (e_verb << 8) | nid | 0x80; /* 0x80: valid bit */
*sdw_addr_l += offset_l;
*sdw_data_l = payload & 0xff;
}
*sdw_addr_h = (e_verb << 8) | nid;
*sdw_addr_h += offset_h;
return 0;
}
EXPORT_SYMBOL(hda_to_sdw);
static int rt715_update_status(struct sdw_slave *slave,
enum sdw_slave_status status)
{
struct rt715_priv *rt715 = dev_get_drvdata(&slave->dev);
/*
* Perform initialization only if slave status is present and
* hw_init flag is false
*/
if (rt715->hw_init || status != SDW_SLAVE_ATTACHED)
return 0;
/* perform I/O transfers required for Slave initialization */
return rt715_io_init(&slave->dev, slave);
}
static int rt715_read_prop(struct sdw_slave *slave)
{
struct sdw_slave_prop *prop = &slave->prop;
int nval, i;
u32 bit;
unsigned long addr;
struct sdw_dpn_prop *dpn;
prop->scp_int1_mask = SDW_SCP_INT1_IMPL_DEF | SDW_SCP_INT1_BUS_CLASH |
SDW_SCP_INT1_PARITY;
prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
prop->paging_support = false;
/* first we need to allocate memory for set bits in port lists */
prop->source_ports = 0x50;/* BITMAP: 01010000 */
prop->sink_ports = 0x0; /* BITMAP: 00000000 */
nval = hweight32(prop->source_ports);
prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
sizeof(*prop->src_dpn_prop),
GFP_KERNEL);
if (!prop->src_dpn_prop)
return -ENOMEM;
dpn = prop->src_dpn_prop;
i = 0;
addr = prop->source_ports;
for_each_set_bit(bit, &addr, 32) {
dpn[i].num = bit;
dpn[i].simple_ch_prep_sm = true;
dpn[i].ch_prep_timeout = 10;
i++;
}
/* set the timeout values */
prop->clk_stop_timeout = 20;
/* wake-up event */
prop->wake_capable = 1;
return 0;
}
static int rt715_bus_config(struct sdw_slave *slave,
struct sdw_bus_params *params)
{
struct rt715_priv *rt715 = dev_get_drvdata(&slave->dev);
int ret;
memcpy(&rt715->params, params, sizeof(*params));
ret = rt715_clock_config(&slave->dev);
if (ret < 0)
dev_err(&slave->dev, "Invalid clk config");
return 0;
}
static const struct sdw_slave_ops rt715_slave_ops = {
.read_prop = rt715_read_prop,
.update_status = rt715_update_status,
.bus_config = rt715_bus_config,
};
static int rt715_sdw_probe(struct sdw_slave *slave,
const struct sdw_device_id *id)
{
struct regmap *sdw_regmap, *regmap;
/* Regmap Initialization */
sdw_regmap = devm_regmap_init_sdw(slave, &rt715_sdw_regmap);
if (IS_ERR(sdw_regmap))
return PTR_ERR(sdw_regmap);
regmap = devm_regmap_init(&slave->dev, NULL, &slave->dev,
&rt715_regmap);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return rt715_init(&slave->dev, sdw_regmap, regmap, slave);
}
static int rt715_sdw_remove(struct sdw_slave *slave)
{
pm_runtime_disable(&slave->dev);
return 0;
}
static const struct sdw_device_id rt715_id[] = {
SDW_SLAVE_ENTRY_EXT(0x025d, 0x714, 0x2, 0, 0),
SDW_SLAVE_ENTRY_EXT(0x025d, 0x715, 0x2, 0, 0),
{},
};
MODULE_DEVICE_TABLE(sdw, rt715_id);
static int __maybe_unused rt715_dev_suspend(struct device *dev)
{
struct rt715_priv *rt715 = dev_get_drvdata(dev);
if (!rt715->hw_init)
return 0;
regcache_cache_only(rt715->regmap, true);
return 0;
}
#define RT715_PROBE_TIMEOUT 5000
static int __maybe_unused rt715_dev_resume(struct device *dev)
{
struct sdw_slave *slave = dev_to_sdw_dev(dev);
struct rt715_priv *rt715 = dev_get_drvdata(dev);
unsigned long time;
if (!rt715->first_hw_init)
return 0;
if (!slave->unattach_request)
goto regmap_sync;
time = wait_for_completion_timeout(&slave->initialization_complete,
msecs_to_jiffies(RT715_PROBE_TIMEOUT));
if (!time) {
dev_err(&slave->dev, "Initialization not complete, timed out\n");
sdw_show_ping_status(slave->bus, true);
return -ETIMEDOUT;
}
regmap_sync:
slave->unattach_request = 0;
regcache_cache_only(rt715->regmap, false);
regcache_sync_region(rt715->regmap, 0x3000, 0x8fff);
regcache_sync_region(rt715->regmap, 0x752039, 0x752039);
return 0;
}
static const struct dev_pm_ops rt715_pm = {
SET_SYSTEM_SLEEP_PM_OPS(rt715_dev_suspend, rt715_dev_resume)
SET_RUNTIME_PM_OPS(rt715_dev_suspend, rt715_dev_resume, NULL)
};
static struct sdw_driver rt715_sdw_driver = {
.driver = {
.name = "rt715",
.owner = THIS_MODULE,
.pm = &rt715_pm,
},
.probe = rt715_sdw_probe,
.remove = rt715_sdw_remove,
.ops = &rt715_slave_ops,
.id_table = rt715_id,
};
module_sdw_driver(rt715_sdw_driver);
MODULE_DESCRIPTION("ASoC RT715 driver SDW");
MODULE_AUTHOR("Jack Yu <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/rt715-sdw.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Load Analog Devices SigmaStudio firmware files
*
* Copyright 2009-2011 Analog Devices Inc.
*/
#include <linux/regmap.h>
#include <linux/export.h>
#include <linux/module.h>
#include "sigmadsp.h"
static int sigmadsp_write_regmap(void *control_data,
unsigned int addr, const uint8_t data[], size_t len)
{
return regmap_raw_write(control_data, addr,
data, len);
}
static int sigmadsp_read_regmap(void *control_data,
unsigned int addr, uint8_t data[], size_t len)
{
return regmap_raw_read(control_data, addr,
data, len);
}
/**
* devm_sigmadsp_init_regmap() - Initialize SigmaDSP instance
* @dev: The parent device
* @regmap: Regmap instance to use
* @ops: The sigmadsp_ops to use for this instance
* @firmware_name: Name of the firmware file to load
*
* Allocates a SigmaDSP instance and loads the specified firmware file.
*
* Returns a pointer to a struct sigmadsp on success, or a PTR_ERR() on error.
*/
struct sigmadsp *devm_sigmadsp_init_regmap(struct device *dev,
struct regmap *regmap, const struct sigmadsp_ops *ops,
const char *firmware_name)
{
struct sigmadsp *sigmadsp;
sigmadsp = devm_sigmadsp_init(dev, ops, firmware_name);
if (IS_ERR(sigmadsp))
return sigmadsp;
sigmadsp->control_data = regmap;
sigmadsp->write = sigmadsp_write_regmap;
sigmadsp->read = sigmadsp_read_regmap;
return sigmadsp;
}
EXPORT_SYMBOL_GPL(devm_sigmadsp_init_regmap);
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_DESCRIPTION("SigmaDSP regmap firmware loader");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/sigmadsp-regmap.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* wm9713.c -- ALSA Soc WM9713 codec support
*
* Copyright 2006-10 Wolfson Microelectronics PLC.
* Author: Liam Girdwood <[email protected]>
*
* Features:-
*
* o Support for AC97 Codec, Voice DAC and Aux DAC
* o Support for DAPM
*/
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/mfd/wm97xx.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/ac97_codec.h>
#include <sound/ac97/codec.h>
#include <sound/ac97/compat.h>
#include <sound/initval.h>
#include <sound/pcm_params.h>
#include <sound/tlv.h>
#include <sound/soc.h>
#include "wm9713.h"
#define WM9713_VENDOR_ID 0x574d4c13
#define WM9713_VENDOR_ID_MASK 0xffffffff
struct wm9713_priv {
struct snd_ac97 *ac97;
u32 pll_in; /* PLL input frequency */
unsigned int hp_mixer[2];
struct mutex lock;
struct wm97xx_platform_data *mfd_pdata;
};
#define HPL_MIXER 0
#define HPR_MIXER 1
static const char *wm9713_mic_mixer[] = {"Stereo", "Mic 1", "Mic 2", "Mute"};
static const char *wm9713_rec_mux[] = {"Stereo", "Left", "Right", "Mute"};
static const char *wm9713_rec_src[] =
{"Mic 1", "Mic 2", "Line", "Mono In", "Headphone", "Speaker",
"Mono Out", "Zh"};
static const char *wm9713_rec_gain[] = {"+1.5dB Steps", "+0.75dB Steps"};
static const char *wm9713_alc_select[] = {"None", "Left", "Right", "Stereo"};
static const char *wm9713_mono_pga[] = {"Vmid", "Zh", "Mono", "Inv"};
static const char *wm9713_spk_pga[] =
{"Vmid", "Zh", "Headphone", "Speaker", "Inv", "Headphone Vmid",
"Speaker Vmid", "Inv Vmid"};
static const char *wm9713_hp_pga[] = {"Vmid", "Zh", "Headphone",
"Headphone Vmid"};
static const char *wm9713_out3_pga[] = {"Vmid", "Zh", "Inv 1", "Inv 1 Vmid"};
static const char *wm9713_out4_pga[] = {"Vmid", "Zh", "Inv 2", "Inv 2 Vmid"};
static const char *wm9713_dac_inv[] =
{"Off", "Mono", "Speaker", "Left Headphone", "Right Headphone",
"Headphone Mono", "NC", "Vmid"};
static const char *wm9713_bass[] = {"Linear Control", "Adaptive Boost"};
static const char *wm9713_ng_type[] = {"Constant Gain", "Mute"};
static const char *wm9713_mic_select[] = {"Mic 1", "Mic 2 A", "Mic 2 B"};
static const char *wm9713_micb_select[] = {"MPB", "MPA"};
static const struct soc_enum wm9713_enum[] = {
SOC_ENUM_SINGLE(AC97_LINE, 3, 4, wm9713_mic_mixer), /* record mic mixer 0 */
SOC_ENUM_SINGLE(AC97_VIDEO, 14, 4, wm9713_rec_mux), /* record mux hp 1 */
SOC_ENUM_SINGLE(AC97_VIDEO, 9, 4, wm9713_rec_mux), /* record mux mono 2 */
SOC_ENUM_SINGLE(AC97_VIDEO, 3, 8, wm9713_rec_src), /* record mux left 3 */
SOC_ENUM_SINGLE(AC97_VIDEO, 0, 8, wm9713_rec_src), /* record mux right 4*/
SOC_ENUM_DOUBLE(AC97_CD, 14, 6, 2, wm9713_rec_gain), /* record step size 5 */
SOC_ENUM_SINGLE(AC97_PCI_SVID, 14, 4, wm9713_alc_select), /* alc source select 6*/
SOC_ENUM_SINGLE(AC97_REC_GAIN, 14, 4, wm9713_mono_pga), /* mono input select 7 */
SOC_ENUM_SINGLE(AC97_REC_GAIN, 11, 8, wm9713_spk_pga), /* speaker left input select 8 */
SOC_ENUM_SINGLE(AC97_REC_GAIN, 8, 8, wm9713_spk_pga), /* speaker right input select 9 */
SOC_ENUM_SINGLE(AC97_REC_GAIN, 6, 3, wm9713_hp_pga), /* headphone left input 10 */
SOC_ENUM_SINGLE(AC97_REC_GAIN, 4, 3, wm9713_hp_pga), /* headphone right input 11 */
SOC_ENUM_SINGLE(AC97_REC_GAIN, 2, 4, wm9713_out3_pga), /* out 3 source 12 */
SOC_ENUM_SINGLE(AC97_REC_GAIN, 0, 4, wm9713_out4_pga), /* out 4 source 13 */
SOC_ENUM_SINGLE(AC97_REC_GAIN_MIC, 13, 8, wm9713_dac_inv), /* dac invert 1 14 */
SOC_ENUM_SINGLE(AC97_REC_GAIN_MIC, 10, 8, wm9713_dac_inv), /* dac invert 2 15 */
SOC_ENUM_SINGLE(AC97_GENERAL_PURPOSE, 15, 2, wm9713_bass), /* bass control 16 */
SOC_ENUM_SINGLE(AC97_PCI_SVID, 5, 2, wm9713_ng_type), /* noise gate type 17 */
SOC_ENUM_SINGLE(AC97_3D_CONTROL, 12, 3, wm9713_mic_select), /* mic selection 18 */
SOC_ENUM_SINGLE_VIRT(2, wm9713_micb_select), /* mic selection 19 */
};
static const DECLARE_TLV_DB_SCALE(out_tlv, -4650, 150, 0);
static const DECLARE_TLV_DB_SCALE(main_tlv, -3450, 150, 0);
static const DECLARE_TLV_DB_SCALE(misc_tlv, -1500, 300, 0);
static const DECLARE_TLV_DB_RANGE(mic_tlv,
0, 2, TLV_DB_SCALE_ITEM(1200, 600, 0),
3, 3, TLV_DB_SCALE_ITEM(3000, 0, 0)
);
static const struct snd_kcontrol_new wm9713_snd_ac97_controls[] = {
SOC_DOUBLE_TLV("Speaker Playback Volume", AC97_MASTER, 8, 0, 31, 1, out_tlv),
SOC_DOUBLE("Speaker Playback Switch", AC97_MASTER, 15, 7, 1, 1),
SOC_DOUBLE_TLV("Headphone Playback Volume", AC97_HEADPHONE, 8, 0, 31, 1,
out_tlv),
SOC_DOUBLE("Headphone Playback Switch", AC97_HEADPHONE, 15, 7, 1, 1),
SOC_DOUBLE_TLV("Line In Volume", AC97_PC_BEEP, 8, 0, 31, 1, main_tlv),
SOC_DOUBLE_TLV("PCM Playback Volume", AC97_PHONE, 8, 0, 31, 1, main_tlv),
SOC_SINGLE_TLV("Mic 1 Volume", AC97_MIC, 8, 31, 1, main_tlv),
SOC_SINGLE_TLV("Mic 2 Volume", AC97_MIC, 0, 31, 1, main_tlv),
SOC_SINGLE_TLV("Mic 1 Preamp Volume", AC97_3D_CONTROL, 10, 3, 0, mic_tlv),
SOC_SINGLE_TLV("Mic 2 Preamp Volume", AC97_3D_CONTROL, 12, 3, 0, mic_tlv),
SOC_SINGLE("Mic Boost (+20dB) Switch", AC97_LINE, 5, 1, 0),
SOC_SINGLE("Mic Headphone Mixer Volume", AC97_LINE, 0, 7, 1),
SOC_SINGLE("Capture Switch", AC97_CD, 15, 1, 1),
SOC_ENUM("Capture Volume Steps", wm9713_enum[5]),
SOC_DOUBLE("Capture Volume", AC97_CD, 8, 0, 31, 0),
SOC_SINGLE("Capture ZC Switch", AC97_CD, 7, 1, 0),
SOC_SINGLE_TLV("Capture to Headphone Volume", AC97_VIDEO, 11, 7, 1, misc_tlv),
SOC_SINGLE("Capture to Mono Boost (+20dB) Switch", AC97_VIDEO, 8, 1, 0),
SOC_SINGLE("Capture ADC Boost (+20dB) Switch", AC97_VIDEO, 6, 1, 0),
SOC_SINGLE("ALC Target Volume", AC97_CODEC_CLASS_REV, 12, 15, 0),
SOC_SINGLE("ALC Hold Time", AC97_CODEC_CLASS_REV, 8, 15, 0),
SOC_SINGLE("ALC Decay Time", AC97_CODEC_CLASS_REV, 4, 15, 0),
SOC_SINGLE("ALC Attack Time", AC97_CODEC_CLASS_REV, 0, 15, 0),
SOC_ENUM("ALC Function", wm9713_enum[6]),
SOC_SINGLE("ALC Max Volume", AC97_PCI_SVID, 11, 7, 0),
SOC_SINGLE("ALC ZC Timeout", AC97_PCI_SVID, 9, 3, 0),
SOC_SINGLE("ALC ZC Switch", AC97_PCI_SVID, 8, 1, 0),
SOC_SINGLE("ALC NG Switch", AC97_PCI_SVID, 7, 1, 0),
SOC_ENUM("ALC NG Type", wm9713_enum[17]),
SOC_SINGLE("ALC NG Threshold", AC97_PCI_SVID, 0, 31, 0),
SOC_DOUBLE("Speaker Playback ZC Switch", AC97_MASTER, 14, 6, 1, 0),
SOC_DOUBLE("Headphone Playback ZC Switch", AC97_HEADPHONE, 14, 6, 1, 0),
SOC_SINGLE("Out4 Playback Switch", AC97_MASTER_MONO, 15, 1, 1),
SOC_SINGLE("Out4 Playback ZC Switch", AC97_MASTER_MONO, 14, 1, 0),
SOC_SINGLE_TLV("Out4 Playback Volume", AC97_MASTER_MONO, 8, 31, 1, out_tlv),
SOC_SINGLE("Out3 Playback Switch", AC97_MASTER_MONO, 7, 1, 1),
SOC_SINGLE("Out3 Playback ZC Switch", AC97_MASTER_MONO, 6, 1, 0),
SOC_SINGLE_TLV("Out3 Playback Volume", AC97_MASTER_MONO, 0, 31, 1, out_tlv),
SOC_SINGLE_TLV("Mono Capture Volume", AC97_MASTER_TONE, 8, 31, 1, main_tlv),
SOC_SINGLE("Mono Playback Switch", AC97_MASTER_TONE, 7, 1, 1),
SOC_SINGLE("Mono Playback ZC Switch", AC97_MASTER_TONE, 6, 1, 0),
SOC_SINGLE_TLV("Mono Playback Volume", AC97_MASTER_TONE, 0, 31, 1, out_tlv),
SOC_SINGLE_TLV("Headphone Mixer Beep Playback Volume", AC97_AUX, 12, 7, 1,
misc_tlv),
SOC_SINGLE_TLV("Speaker Mixer Beep Playback Volume", AC97_AUX, 8, 7, 1,
misc_tlv),
SOC_SINGLE_TLV("Mono Mixer Beep Playback Volume", AC97_AUX, 4, 7, 1, misc_tlv),
SOC_SINGLE_TLV("Voice Playback Headphone Volume", AC97_PCM, 12, 7, 1,
misc_tlv),
SOC_SINGLE("Voice Playback Master Volume", AC97_PCM, 8, 7, 1),
SOC_SINGLE("Voice Playback Mono Volume", AC97_PCM, 4, 7, 1),
SOC_SINGLE_TLV("Headphone Mixer Aux Playback Volume", AC97_REC_SEL, 12, 7, 1,
misc_tlv),
SOC_SINGLE_TLV("Speaker Mixer Voice Playback Volume", AC97_PCM, 8, 7, 1,
misc_tlv),
SOC_SINGLE_TLV("Speaker Mixer Aux Playback Volume", AC97_REC_SEL, 8, 7, 1,
misc_tlv),
SOC_SINGLE_TLV("Mono Mixer Voice Playback Volume", AC97_PCM, 4, 7, 1,
misc_tlv),
SOC_SINGLE_TLV("Mono Mixer Aux Playback Volume", AC97_REC_SEL, 4, 7, 1,
misc_tlv),
SOC_SINGLE("Aux Playback Headphone Volume", AC97_REC_SEL, 12, 7, 1),
SOC_SINGLE("Aux Playback Master Volume", AC97_REC_SEL, 8, 7, 1),
SOC_ENUM("Bass Control", wm9713_enum[16]),
SOC_SINGLE("Bass Cut-off Switch", AC97_GENERAL_PURPOSE, 12, 1, 1),
SOC_SINGLE("Tone Cut-off Switch", AC97_GENERAL_PURPOSE, 4, 1, 1),
SOC_SINGLE("Playback Attenuate (-6dB) Switch", AC97_GENERAL_PURPOSE, 6, 1, 0),
SOC_SINGLE("Bass Volume", AC97_GENERAL_PURPOSE, 8, 15, 1),
SOC_SINGLE("Tone Volume", AC97_GENERAL_PURPOSE, 0, 15, 1),
SOC_SINGLE("3D Upper Cut-off Switch", AC97_REC_GAIN_MIC, 5, 1, 0),
SOC_SINGLE("3D Lower Cut-off Switch", AC97_REC_GAIN_MIC, 4, 1, 0),
SOC_SINGLE("3D Depth", AC97_REC_GAIN_MIC, 0, 15, 1),
};
static int wm9713_voice_shutdown(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
if (WARN_ON(event != SND_SOC_DAPM_PRE_PMD))
return -EINVAL;
/* Gracefully shut down the voice interface. */
snd_soc_component_update_bits(component, AC97_HANDSET_RATE, 0x0f00, 0x0200);
schedule_timeout_interruptible(msecs_to_jiffies(1));
snd_soc_component_update_bits(component, AC97_HANDSET_RATE, 0x0f00, 0x0f00);
snd_soc_component_update_bits(component, AC97_EXTENDED_MID, 0x1000, 0x1000);
return 0;
}
static const unsigned int wm9713_mixer_mute_regs[] = {
AC97_PC_BEEP,
AC97_MASTER_TONE,
AC97_PHONE,
AC97_REC_SEL,
AC97_PCM,
AC97_AUX,
};
/* We have to create a fake left and right HP mixers because
* the codec only has a single control that is shared by both channels.
* This makes it impossible to determine the audio path using the current
* register map, thus we add a new (virtual) register to help determine the
* audio route within the device.
*/
static int wm9713_hp_mixer_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kcontrol);
struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
struct wm9713_priv *wm9713 = snd_soc_component_get_drvdata(component);
unsigned int val = ucontrol->value.integer.value[0];
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
unsigned int mixer, mask, shift, old;
struct snd_soc_dapm_update update = {};
bool change;
mixer = mc->shift >> 8;
shift = mc->shift & 0xff;
mask = (1 << shift);
mutex_lock(&wm9713->lock);
old = wm9713->hp_mixer[mixer];
if (ucontrol->value.integer.value[0])
wm9713->hp_mixer[mixer] |= mask;
else
wm9713->hp_mixer[mixer] &= ~mask;
change = old != wm9713->hp_mixer[mixer];
if (change) {
update.kcontrol = kcontrol;
update.reg = wm9713_mixer_mute_regs[shift];
update.mask = 0x8000;
if ((wm9713->hp_mixer[0] & mask) ||
(wm9713->hp_mixer[1] & mask))
update.val = 0x0;
else
update.val = 0x8000;
snd_soc_dapm_mixer_update_power(dapm, kcontrol, val,
&update);
}
mutex_unlock(&wm9713->lock);
return change;
}
static int wm9713_hp_mixer_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kcontrol);
struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
struct wm9713_priv *wm9713 = snd_soc_component_get_drvdata(component);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
unsigned int mixer, shift;
mixer = mc->shift >> 8;
shift = mc->shift & 0xff;
ucontrol->value.integer.value[0] =
(wm9713->hp_mixer[mixer] >> shift) & 1;
return 0;
}
#define WM9713_HP_MIXER_CTRL(xname, xmixer, xshift) { \
.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
.info = snd_soc_info_volsw, \
.get = wm9713_hp_mixer_get, .put = wm9713_hp_mixer_put, \
.private_value = SOC_DOUBLE_VALUE(SND_SOC_NOPM, \
xshift, xmixer, 1, 0, 0) \
}
/* Left Headphone Mixers */
static const struct snd_kcontrol_new wm9713_hpl_mixer_controls[] = {
WM9713_HP_MIXER_CTRL("Beep Playback Switch", HPL_MIXER, 5),
WM9713_HP_MIXER_CTRL("Voice Playback Switch", HPL_MIXER, 4),
WM9713_HP_MIXER_CTRL("Aux Playback Switch", HPL_MIXER, 3),
WM9713_HP_MIXER_CTRL("PCM Playback Switch", HPL_MIXER, 2),
WM9713_HP_MIXER_CTRL("MonoIn Playback Switch", HPL_MIXER, 1),
WM9713_HP_MIXER_CTRL("Bypass Playback Switch", HPL_MIXER, 0),
};
/* Right Headphone Mixers */
static const struct snd_kcontrol_new wm9713_hpr_mixer_controls[] = {
WM9713_HP_MIXER_CTRL("Beep Playback Switch", HPR_MIXER, 5),
WM9713_HP_MIXER_CTRL("Voice Playback Switch", HPR_MIXER, 4),
WM9713_HP_MIXER_CTRL("Aux Playback Switch", HPR_MIXER, 3),
WM9713_HP_MIXER_CTRL("PCM Playback Switch", HPR_MIXER, 2),
WM9713_HP_MIXER_CTRL("MonoIn Playback Switch", HPR_MIXER, 1),
WM9713_HP_MIXER_CTRL("Bypass Playback Switch", HPR_MIXER, 0),
};
/* headphone capture mux */
static const struct snd_kcontrol_new wm9713_hp_rec_mux_controls =
SOC_DAPM_ENUM("Route", wm9713_enum[1]);
/* headphone mic mux */
static const struct snd_kcontrol_new wm9713_hp_mic_mux_controls =
SOC_DAPM_ENUM("Route", wm9713_enum[0]);
/* Speaker Mixer */
static const struct snd_kcontrol_new wm9713_speaker_mixer_controls[] = {
SOC_DAPM_SINGLE("Beep Playback Switch", AC97_AUX, 11, 1, 1),
SOC_DAPM_SINGLE("Voice Playback Switch", AC97_PCM, 11, 1, 1),
SOC_DAPM_SINGLE("Aux Playback Switch", AC97_REC_SEL, 11, 1, 1),
SOC_DAPM_SINGLE("PCM Playback Switch", AC97_PHONE, 14, 1, 1),
SOC_DAPM_SINGLE("MonoIn Playback Switch", AC97_MASTER_TONE, 14, 1, 1),
SOC_DAPM_SINGLE("Bypass Playback Switch", AC97_PC_BEEP, 14, 1, 1),
};
/* Mono Mixer */
static const struct snd_kcontrol_new wm9713_mono_mixer_controls[] = {
SOC_DAPM_SINGLE("Beep Playback Switch", AC97_AUX, 7, 1, 1),
SOC_DAPM_SINGLE("Voice Playback Switch", AC97_PCM, 7, 1, 1),
SOC_DAPM_SINGLE("Aux Playback Switch", AC97_REC_SEL, 7, 1, 1),
SOC_DAPM_SINGLE("PCM Playback Switch", AC97_PHONE, 13, 1, 1),
SOC_DAPM_SINGLE("MonoIn Playback Switch", AC97_MASTER_TONE, 13, 1, 1),
SOC_DAPM_SINGLE("Bypass Playback Switch", AC97_PC_BEEP, 13, 1, 1),
SOC_DAPM_SINGLE("Mic 1 Sidetone Switch", AC97_LINE, 7, 1, 1),
SOC_DAPM_SINGLE("Mic 2 Sidetone Switch", AC97_LINE, 6, 1, 1),
};
/* mono mic mux */
static const struct snd_kcontrol_new wm9713_mono_mic_mux_controls =
SOC_DAPM_ENUM("Route", wm9713_enum[2]);
/* mono output mux */
static const struct snd_kcontrol_new wm9713_mono_mux_controls =
SOC_DAPM_ENUM("Route", wm9713_enum[7]);
/* speaker left output mux */
static const struct snd_kcontrol_new wm9713_hp_spkl_mux_controls =
SOC_DAPM_ENUM("Route", wm9713_enum[8]);
/* speaker right output mux */
static const struct snd_kcontrol_new wm9713_hp_spkr_mux_controls =
SOC_DAPM_ENUM("Route", wm9713_enum[9]);
/* headphone left output mux */
static const struct snd_kcontrol_new wm9713_hpl_out_mux_controls =
SOC_DAPM_ENUM("Route", wm9713_enum[10]);
/* headphone right output mux */
static const struct snd_kcontrol_new wm9713_hpr_out_mux_controls =
SOC_DAPM_ENUM("Route", wm9713_enum[11]);
/* Out3 mux */
static const struct snd_kcontrol_new wm9713_out3_mux_controls =
SOC_DAPM_ENUM("Route", wm9713_enum[12]);
/* Out4 mux */
static const struct snd_kcontrol_new wm9713_out4_mux_controls =
SOC_DAPM_ENUM("Route", wm9713_enum[13]);
/* DAC inv mux 1 */
static const struct snd_kcontrol_new wm9713_dac_inv1_mux_controls =
SOC_DAPM_ENUM("Route", wm9713_enum[14]);
/* DAC inv mux 2 */
static const struct snd_kcontrol_new wm9713_dac_inv2_mux_controls =
SOC_DAPM_ENUM("Route", wm9713_enum[15]);
/* Capture source left */
static const struct snd_kcontrol_new wm9713_rec_srcl_mux_controls =
SOC_DAPM_ENUM("Route", wm9713_enum[3]);
/* Capture source right */
static const struct snd_kcontrol_new wm9713_rec_srcr_mux_controls =
SOC_DAPM_ENUM("Route", wm9713_enum[4]);
/* mic source */
static const struct snd_kcontrol_new wm9713_mic_sel_mux_controls =
SOC_DAPM_ENUM("Route", wm9713_enum[18]);
/* mic source B virtual control */
static const struct snd_kcontrol_new wm9713_micb_sel_mux_controls =
SOC_DAPM_ENUM("Route", wm9713_enum[19]);
static const struct snd_soc_dapm_widget wm9713_dapm_widgets[] = {
SND_SOC_DAPM_MUX("Capture Headphone Mux", SND_SOC_NOPM, 0, 0,
&wm9713_hp_rec_mux_controls),
SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
&wm9713_hp_mic_mux_controls),
SND_SOC_DAPM_MUX("Capture Mono Mux", SND_SOC_NOPM, 0, 0,
&wm9713_mono_mic_mux_controls),
SND_SOC_DAPM_MUX("Mono Out Mux", SND_SOC_NOPM, 0, 0,
&wm9713_mono_mux_controls),
SND_SOC_DAPM_MUX("Left Speaker Out Mux", SND_SOC_NOPM, 0, 0,
&wm9713_hp_spkl_mux_controls),
SND_SOC_DAPM_MUX("Right Speaker Out Mux", SND_SOC_NOPM, 0, 0,
&wm9713_hp_spkr_mux_controls),
SND_SOC_DAPM_MUX("Left Headphone Out Mux", SND_SOC_NOPM, 0, 0,
&wm9713_hpl_out_mux_controls),
SND_SOC_DAPM_MUX("Right Headphone Out Mux", SND_SOC_NOPM, 0, 0,
&wm9713_hpr_out_mux_controls),
SND_SOC_DAPM_MUX("Out 3 Mux", SND_SOC_NOPM, 0, 0,
&wm9713_out3_mux_controls),
SND_SOC_DAPM_MUX("Out 4 Mux", SND_SOC_NOPM, 0, 0,
&wm9713_out4_mux_controls),
SND_SOC_DAPM_MUX("DAC Inv Mux 1", SND_SOC_NOPM, 0, 0,
&wm9713_dac_inv1_mux_controls),
SND_SOC_DAPM_MUX("DAC Inv Mux 2", SND_SOC_NOPM, 0, 0,
&wm9713_dac_inv2_mux_controls),
SND_SOC_DAPM_MUX("Left Capture Source", SND_SOC_NOPM, 0, 0,
&wm9713_rec_srcl_mux_controls),
SND_SOC_DAPM_MUX("Right Capture Source", SND_SOC_NOPM, 0, 0,
&wm9713_rec_srcr_mux_controls),
SND_SOC_DAPM_MUX("Mic A Source", SND_SOC_NOPM, 0, 0,
&wm9713_mic_sel_mux_controls),
SND_SOC_DAPM_MUX("Mic B Source", SND_SOC_NOPM, 0, 0,
&wm9713_micb_sel_mux_controls),
SND_SOC_DAPM_MIXER("Left HP Mixer", AC97_EXTENDED_MID, 3, 1,
&wm9713_hpl_mixer_controls[0], ARRAY_SIZE(wm9713_hpl_mixer_controls)),
SND_SOC_DAPM_MIXER("Right HP Mixer", AC97_EXTENDED_MID, 2, 1,
&wm9713_hpr_mixer_controls[0], ARRAY_SIZE(wm9713_hpr_mixer_controls)),
SND_SOC_DAPM_MIXER("Mono Mixer", AC97_EXTENDED_MID, 0, 1,
&wm9713_mono_mixer_controls[0], ARRAY_SIZE(wm9713_mono_mixer_controls)),
SND_SOC_DAPM_MIXER("Speaker Mixer", AC97_EXTENDED_MID, 1, 1,
&wm9713_speaker_mixer_controls[0],
ARRAY_SIZE(wm9713_speaker_mixer_controls)),
SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback", AC97_EXTENDED_MID, 7, 1),
SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback", AC97_EXTENDED_MID, 6, 1),
SND_SOC_DAPM_MIXER("AC97 Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("HP Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Line Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Capture Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_DAC_E("Voice DAC", "Voice Playback", AC97_EXTENDED_MID, 12, 1,
wm9713_voice_shutdown, SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_DAC("Aux DAC", "Aux Playback", AC97_EXTENDED_MID, 11, 1),
SND_SOC_DAPM_PGA("Left ADC", AC97_EXTENDED_MID, 5, 1, NULL, 0),
SND_SOC_DAPM_PGA("Right ADC", AC97_EXTENDED_MID, 4, 1, NULL, 0),
SND_SOC_DAPM_ADC("Left HiFi ADC", "Left HiFi Capture", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("Right HiFi ADC", "Right HiFi Capture", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("Left Voice ADC", "Left Voice Capture", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("Right Voice ADC", "Right Voice Capture", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_PGA("Left Headphone", AC97_EXTENDED_MSTATUS, 10, 1, NULL, 0),
SND_SOC_DAPM_PGA("Right Headphone", AC97_EXTENDED_MSTATUS, 9, 1, NULL, 0),
SND_SOC_DAPM_PGA("Left Speaker", AC97_EXTENDED_MSTATUS, 8, 1, NULL, 0),
SND_SOC_DAPM_PGA("Right Speaker", AC97_EXTENDED_MSTATUS, 7, 1, NULL, 0),
SND_SOC_DAPM_PGA("Out 3", AC97_EXTENDED_MSTATUS, 11, 1, NULL, 0),
SND_SOC_DAPM_PGA("Out 4", AC97_EXTENDED_MSTATUS, 12, 1, NULL, 0),
SND_SOC_DAPM_PGA("Mono Out", AC97_EXTENDED_MSTATUS, 13, 1, NULL, 0),
SND_SOC_DAPM_PGA("Left Line In", AC97_EXTENDED_MSTATUS, 6, 1, NULL, 0),
SND_SOC_DAPM_PGA("Right Line In", AC97_EXTENDED_MSTATUS, 5, 1, NULL, 0),
SND_SOC_DAPM_PGA("Mono In", AC97_EXTENDED_MSTATUS, 4, 1, NULL, 0),
SND_SOC_DAPM_PGA("Mic A PGA", AC97_EXTENDED_MSTATUS, 3, 1, NULL, 0),
SND_SOC_DAPM_PGA("Mic B PGA", AC97_EXTENDED_MSTATUS, 2, 1, NULL, 0),
SND_SOC_DAPM_PGA("Mic A Pre Amp", AC97_EXTENDED_MSTATUS, 1, 1, NULL, 0),
SND_SOC_DAPM_PGA("Mic B Pre Amp", AC97_EXTENDED_MSTATUS, 0, 1, NULL, 0),
SND_SOC_DAPM_MICBIAS("Mic Bias", AC97_EXTENDED_MSTATUS, 14, 1),
SND_SOC_DAPM_OUTPUT("MONO"),
SND_SOC_DAPM_OUTPUT("HPL"),
SND_SOC_DAPM_OUTPUT("HPR"),
SND_SOC_DAPM_OUTPUT("SPKL"),
SND_SOC_DAPM_OUTPUT("SPKR"),
SND_SOC_DAPM_OUTPUT("OUT3"),
SND_SOC_DAPM_OUTPUT("OUT4"),
SND_SOC_DAPM_INPUT("LINEL"),
SND_SOC_DAPM_INPUT("LINER"),
SND_SOC_DAPM_INPUT("MONOIN"),
SND_SOC_DAPM_INPUT("PCBEEP"),
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_INPUT("MIC2A"),
SND_SOC_DAPM_INPUT("MIC2B"),
SND_SOC_DAPM_VMID("VMID"),
};
static const struct snd_soc_dapm_route wm9713_audio_map[] = {
/* left HP mixer */
{"Left HP Mixer", "Beep Playback Switch", "PCBEEP"},
{"Left HP Mixer", "Voice Playback Switch", "Voice DAC"},
{"Left HP Mixer", "Aux Playback Switch", "Aux DAC"},
{"Left HP Mixer", "Bypass Playback Switch", "Left Line In"},
{"Left HP Mixer", "PCM Playback Switch", "Left DAC"},
{"Left HP Mixer", "MonoIn Playback Switch", "Mono In"},
{"Left HP Mixer", NULL, "Capture Headphone Mux"},
/* right HP mixer */
{"Right HP Mixer", "Beep Playback Switch", "PCBEEP"},
{"Right HP Mixer", "Voice Playback Switch", "Voice DAC"},
{"Right HP Mixer", "Aux Playback Switch", "Aux DAC"},
{"Right HP Mixer", "Bypass Playback Switch", "Right Line In"},
{"Right HP Mixer", "PCM Playback Switch", "Right DAC"},
{"Right HP Mixer", "MonoIn Playback Switch", "Mono In"},
{"Right HP Mixer", NULL, "Capture Headphone Mux"},
/* virtual mixer - mixes left & right channels for spk and mono */
{"AC97 Mixer", NULL, "Left DAC"},
{"AC97 Mixer", NULL, "Right DAC"},
{"Line Mixer", NULL, "Right Line In"},
{"Line Mixer", NULL, "Left Line In"},
{"HP Mixer", NULL, "Left HP Mixer"},
{"HP Mixer", NULL, "Right HP Mixer"},
{"Capture Mixer", NULL, "Left Capture Source"},
{"Capture Mixer", NULL, "Right Capture Source"},
/* speaker mixer */
{"Speaker Mixer", "Beep Playback Switch", "PCBEEP"},
{"Speaker Mixer", "Voice Playback Switch", "Voice DAC"},
{"Speaker Mixer", "Aux Playback Switch", "Aux DAC"},
{"Speaker Mixer", "Bypass Playback Switch", "Line Mixer"},
{"Speaker Mixer", "PCM Playback Switch", "AC97 Mixer"},
{"Speaker Mixer", "MonoIn Playback Switch", "Mono In"},
/* mono mixer */
{"Mono Mixer", "Beep Playback Switch", "PCBEEP"},
{"Mono Mixer", "Voice Playback Switch", "Voice DAC"},
{"Mono Mixer", "Aux Playback Switch", "Aux DAC"},
{"Mono Mixer", "Bypass Playback Switch", "Line Mixer"},
{"Mono Mixer", "PCM Playback Switch", "AC97 Mixer"},
{"Mono Mixer", "Mic 1 Sidetone Switch", "Mic A PGA"},
{"Mono Mixer", "Mic 2 Sidetone Switch", "Mic B PGA"},
{"Mono Mixer", NULL, "Capture Mono Mux"},
/* DAC inv mux 1 */
{"DAC Inv Mux 1", "Mono", "Mono Mixer"},
{"DAC Inv Mux 1", "Speaker", "Speaker Mixer"},
{"DAC Inv Mux 1", "Left Headphone", "Left HP Mixer"},
{"DAC Inv Mux 1", "Right Headphone", "Right HP Mixer"},
{"DAC Inv Mux 1", "Headphone Mono", "HP Mixer"},
/* DAC inv mux 2 */
{"DAC Inv Mux 2", "Mono", "Mono Mixer"},
{"DAC Inv Mux 2", "Speaker", "Speaker Mixer"},
{"DAC Inv Mux 2", "Left Headphone", "Left HP Mixer"},
{"DAC Inv Mux 2", "Right Headphone", "Right HP Mixer"},
{"DAC Inv Mux 2", "Headphone Mono", "HP Mixer"},
/* headphone left mux */
{"Left Headphone Out Mux", "Headphone", "Left HP Mixer"},
/* headphone right mux */
{"Right Headphone Out Mux", "Headphone", "Right HP Mixer"},
/* speaker left mux */
{"Left Speaker Out Mux", "Headphone", "Left HP Mixer"},
{"Left Speaker Out Mux", "Speaker", "Speaker Mixer"},
{"Left Speaker Out Mux", "Inv", "DAC Inv Mux 1"},
/* speaker right mux */
{"Right Speaker Out Mux", "Headphone", "Right HP Mixer"},
{"Right Speaker Out Mux", "Speaker", "Speaker Mixer"},
{"Right Speaker Out Mux", "Inv", "DAC Inv Mux 2"},
/* mono mux */
{"Mono Out Mux", "Mono", "Mono Mixer"},
{"Mono Out Mux", "Inv", "DAC Inv Mux 1"},
/* out 3 mux */
{"Out 3 Mux", "Inv 1", "DAC Inv Mux 1"},
/* out 4 mux */
{"Out 4 Mux", "Inv 2", "DAC Inv Mux 2"},
/* output pga */
{"HPL", NULL, "Left Headphone"},
{"Left Headphone", NULL, "Left Headphone Out Mux"},
{"HPR", NULL, "Right Headphone"},
{"Right Headphone", NULL, "Right Headphone Out Mux"},
{"OUT3", NULL, "Out 3"},
{"Out 3", NULL, "Out 3 Mux"},
{"OUT4", NULL, "Out 4"},
{"Out 4", NULL, "Out 4 Mux"},
{"SPKL", NULL, "Left Speaker"},
{"Left Speaker", NULL, "Left Speaker Out Mux"},
{"SPKR", NULL, "Right Speaker"},
{"Right Speaker", NULL, "Right Speaker Out Mux"},
{"MONO", NULL, "Mono Out"},
{"Mono Out", NULL, "Mono Out Mux"},
/* input pga */
{"Left Line In", NULL, "LINEL"},
{"Right Line In", NULL, "LINER"},
{"Mono In", NULL, "MONOIN"},
{"Mic A PGA", NULL, "Mic A Pre Amp"},
{"Mic B PGA", NULL, "Mic B Pre Amp"},
/* left capture select */
{"Left Capture Source", "Mic 1", "Mic A Pre Amp"},
{"Left Capture Source", "Mic 2", "Mic B Pre Amp"},
{"Left Capture Source", "Line", "LINEL"},
{"Left Capture Source", "Mono In", "MONOIN"},
{"Left Capture Source", "Headphone", "Left HP Mixer"},
{"Left Capture Source", "Speaker", "Speaker Mixer"},
{"Left Capture Source", "Mono Out", "Mono Mixer"},
/* right capture select */
{"Right Capture Source", "Mic 1", "Mic A Pre Amp"},
{"Right Capture Source", "Mic 2", "Mic B Pre Amp"},
{"Right Capture Source", "Line", "LINER"},
{"Right Capture Source", "Mono In", "MONOIN"},
{"Right Capture Source", "Headphone", "Right HP Mixer"},
{"Right Capture Source", "Speaker", "Speaker Mixer"},
{"Right Capture Source", "Mono Out", "Mono Mixer"},
/* left ADC */
{"Left ADC", NULL, "Left Capture Source"},
{"Left Voice ADC", NULL, "Left ADC"},
{"Left HiFi ADC", NULL, "Left ADC"},
/* right ADC */
{"Right ADC", NULL, "Right Capture Source"},
{"Right Voice ADC", NULL, "Right ADC"},
{"Right HiFi ADC", NULL, "Right ADC"},
/* mic */
{"Mic A Pre Amp", NULL, "Mic A Source"},
{"Mic A Source", "Mic 1", "MIC1"},
{"Mic A Source", "Mic 2 A", "MIC2A"},
{"Mic A Source", "Mic 2 B", "Mic B Source"},
{"Mic B Pre Amp", "MPB", "Mic B Source"},
{"Mic B Source", NULL, "MIC2B"},
/* headphone capture */
{"Capture Headphone Mux", "Stereo", "Capture Mixer"},
{"Capture Headphone Mux", "Left", "Left Capture Source"},
{"Capture Headphone Mux", "Right", "Right Capture Source"},
/* mono capture */
{"Capture Mono Mux", "Stereo", "Capture Mixer"},
{"Capture Mono Mux", "Left", "Left Capture Source"},
{"Capture Mono Mux", "Right", "Right Capture Source"},
};
static bool wm9713_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case AC97_RESET ... AC97_PCM_SURR_DAC_RATE:
case AC97_PCM_LR_ADC_RATE:
case AC97_CENTER_LFE_MASTER:
case AC97_SPDIF ... AC97_LINE1_LEVEL:
case AC97_GPIO_CFG ... 0x5c:
case AC97_CODEC_CLASS_REV ... AC97_PCI_SID:
case 0x74 ... AC97_VENDOR_ID2:
return true;
default:
return false;
}
}
static bool wm9713_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case AC97_VENDOR_ID1:
case AC97_VENDOR_ID2:
return false;
default:
return wm9713_readable_reg(dev, reg);
}
}
static const struct reg_default wm9713_reg_defaults[] = {
{ 0x02, 0x8080 }, /* Speaker Output Volume */
{ 0x04, 0x8080 }, /* Headphone Output Volume */
{ 0x06, 0x8080 }, /* Out3/OUT4 Volume */
{ 0x08, 0xc880 }, /* Mono Volume */
{ 0x0a, 0xe808 }, /* LINEIN Volume */
{ 0x0c, 0xe808 }, /* DAC PGA Volume */
{ 0x0e, 0x0808 }, /* MIC PGA Volume */
{ 0x10, 0x00da }, /* MIC Routing Control */
{ 0x12, 0x8000 }, /* Record PGA Volume */
{ 0x14, 0xd600 }, /* Record Routing */
{ 0x16, 0xaaa0 }, /* PCBEEP Volume */
{ 0x18, 0xaaa0 }, /* VxDAC Volume */
{ 0x1a, 0xaaa0 }, /* AUXDAC Volume */
{ 0x1c, 0x0000 }, /* Output PGA Mux */
{ 0x1e, 0x0000 }, /* DAC 3D control */
{ 0x20, 0x0f0f }, /* DAC Tone Control*/
{ 0x22, 0x0040 }, /* MIC Input Select & Bias */
{ 0x24, 0x0000 }, /* Output Volume Mapping & Jack */
{ 0x26, 0x7f00 }, /* Powerdown Ctrl/Stat*/
{ 0x28, 0x0405 }, /* Extended Audio ID */
{ 0x2a, 0x0410 }, /* Extended Audio Start/Ctrl */
{ 0x2c, 0xbb80 }, /* Audio DACs Sample Rate */
{ 0x2e, 0xbb80 }, /* AUXDAC Sample Rate */
{ 0x32, 0xbb80 }, /* Audio ADCs Sample Rate */
{ 0x36, 0x4523 }, /* PCM codec control */
{ 0x3a, 0x2000 }, /* SPDIF control */
{ 0x3c, 0xfdff }, /* Powerdown 1 */
{ 0x3e, 0xffff }, /* Powerdown 2 */
{ 0x40, 0x0000 }, /* General Purpose */
{ 0x42, 0x0000 }, /* Fast Power-Up Control */
{ 0x44, 0x0080 }, /* MCLK/PLL Control */
{ 0x46, 0x0000 }, /* MCLK/PLL Control */
{ 0x4c, 0xfffe }, /* GPIO Pin Configuration */
{ 0x4e, 0xffff }, /* GPIO Pin Polarity / Type */
{ 0x50, 0x0000 }, /* GPIO Pin Sticky */
{ 0x52, 0x0000 }, /* GPIO Pin Wake-Up */
/* GPIO Pin Status */
{ 0x56, 0xfffe }, /* GPIO Pin Sharing */
{ 0x58, 0x4000 }, /* GPIO PullUp/PullDown */
{ 0x5a, 0x0000 }, /* Additional Functions 1 */
{ 0x5c, 0x0000 }, /* Additional Functions 2 */
{ 0x60, 0xb032 }, /* ALC Control */
{ 0x62, 0x3e00 }, /* ALC / Noise Gate Control */
{ 0x64, 0x0000 }, /* AUXDAC input control */
{ 0x74, 0x0000 }, /* Digitiser Reg 1 */
{ 0x76, 0x0006 }, /* Digitiser Reg 2 */
{ 0x78, 0x0001 }, /* Digitiser Reg 3 */
{ 0x7a, 0x0000 }, /* Digitiser Read Back */
};
static const struct regmap_config wm9713_regmap_config = {
.reg_bits = 16,
.reg_stride = 2,
.val_bits = 16,
.max_register = 0x7e,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = wm9713_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm9713_reg_defaults),
.volatile_reg = regmap_ac97_default_volatile,
.readable_reg = wm9713_readable_reg,
.writeable_reg = wm9713_writeable_reg,
};
/* PLL divisors */
struct _pll_div {
u32 divsel:1;
u32 divctl:1;
u32 lf:1;
u32 n:4;
u32 k:24;
};
/* The size in bits of the PLL divide multiplied by 10
* to allow rounding later */
#define FIXED_PLL_SIZE ((1 << 22) * 10)
static void pll_factors(struct snd_soc_component *component,
struct _pll_div *pll_div, unsigned int source)
{
u64 Kpart;
unsigned int K, Ndiv, Nmod, target;
/* The PLL output is always 98.304MHz. */
target = 98304000;
/* If the input frequency is over 14.4MHz then scale it down. */
if (source > 14400000) {
source >>= 1;
pll_div->divsel = 1;
if (source > 14400000) {
source >>= 1;
pll_div->divctl = 1;
} else
pll_div->divctl = 0;
} else {
pll_div->divsel = 0;
pll_div->divctl = 0;
}
/* Low frequency sources require an additional divide in the
* loop.
*/
if (source < 8192000) {
pll_div->lf = 1;
target >>= 2;
} else
pll_div->lf = 0;
Ndiv = target / source;
if ((Ndiv < 5) || (Ndiv > 12))
dev_warn(component->dev,
"WM9713 PLL N value %u out of recommended range!\n",
Ndiv);
pll_div->n = Ndiv;
Nmod = target % source;
Kpart = FIXED_PLL_SIZE * (long long)Nmod;
do_div(Kpart, source);
K = Kpart & 0xFFFFFFFF;
/* Check if we need to round */
if ((K % 10) >= 5)
K += 5;
/* Move down to proper range now rounding is done */
K /= 10;
pll_div->k = K;
}
/*
* Please note that changing the PLL input frequency may require
* resynchronisation with the AC97 controller.
*/
static int wm9713_set_pll(struct snd_soc_component *component,
int pll_id, unsigned int freq_in, unsigned int freq_out)
{
struct wm9713_priv *wm9713 = snd_soc_component_get_drvdata(component);
u16 reg, reg2;
struct _pll_div pll_div;
/* turn PLL off ? */
if (freq_in == 0) {
/* disable PLL power and select ext source */
snd_soc_component_update_bits(component, AC97_HANDSET_RATE, 0x0080, 0x0080);
snd_soc_component_update_bits(component, AC97_EXTENDED_MID, 0x0200, 0x0200);
wm9713->pll_in = 0;
return 0;
}
pll_factors(component, &pll_div, freq_in);
if (pll_div.k == 0) {
reg = (pll_div.n << 12) | (pll_div.lf << 11) |
(pll_div.divsel << 9) | (pll_div.divctl << 8);
snd_soc_component_write(component, AC97_LINE1_LEVEL, reg);
} else {
/* write the fractional k to the reg 0x46 pages */
reg2 = (pll_div.n << 12) | (pll_div.lf << 11) | (1 << 10) |
(pll_div.divsel << 9) | (pll_div.divctl << 8);
/* K [21:20] */
reg = reg2 | (0x5 << 4) | (pll_div.k >> 20);
snd_soc_component_write(component, AC97_LINE1_LEVEL, reg);
/* K [19:16] */
reg = reg2 | (0x4 << 4) | ((pll_div.k >> 16) & 0xf);
snd_soc_component_write(component, AC97_LINE1_LEVEL, reg);
/* K [15:12] */
reg = reg2 | (0x3 << 4) | ((pll_div.k >> 12) & 0xf);
snd_soc_component_write(component, AC97_LINE1_LEVEL, reg);
/* K [11:8] */
reg = reg2 | (0x2 << 4) | ((pll_div.k >> 8) & 0xf);
snd_soc_component_write(component, AC97_LINE1_LEVEL, reg);
/* K [7:4] */
reg = reg2 | (0x1 << 4) | ((pll_div.k >> 4) & 0xf);
snd_soc_component_write(component, AC97_LINE1_LEVEL, reg);
reg = reg2 | (0x0 << 4) | (pll_div.k & 0xf); /* K [3:0] */
snd_soc_component_write(component, AC97_LINE1_LEVEL, reg);
}
/* turn PLL on and select as source */
snd_soc_component_update_bits(component, AC97_EXTENDED_MID, 0x0200, 0x0000);
snd_soc_component_update_bits(component, AC97_HANDSET_RATE, 0x0080, 0x0000);
wm9713->pll_in = freq_in;
/* wait 10ms AC97 link frames for the link to stabilise */
schedule_timeout_interruptible(msecs_to_jiffies(10));
return 0;
}
static int wm9713_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
int source, unsigned int freq_in, unsigned int freq_out)
{
struct snd_soc_component *component = codec_dai->component;
return wm9713_set_pll(component, pll_id, freq_in, freq_out);
}
/*
* Tristate the PCM DAI lines, tristate can be disabled by calling
* wm9713_set_dai_fmt()
*/
static int wm9713_set_dai_tristate(struct snd_soc_dai *codec_dai,
int tristate)
{
struct snd_soc_component *component = codec_dai->component;
if (tristate)
snd_soc_component_update_bits(component, AC97_CENTER_LFE_MASTER,
0x6000, 0x0000);
return 0;
}
/*
* Configure WM9713 clock dividers.
* Voice DAC needs 256 FS
*/
static int wm9713_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
int div_id, int div)
{
struct snd_soc_component *component = codec_dai->component;
switch (div_id) {
case WM9713_PCMCLK_DIV:
snd_soc_component_update_bits(component, AC97_HANDSET_RATE, 0x0f00, div);
break;
case WM9713_CLKA_MULT:
snd_soc_component_update_bits(component, AC97_HANDSET_RATE, 0x0002, div);
break;
case WM9713_CLKB_MULT:
snd_soc_component_update_bits(component, AC97_HANDSET_RATE, 0x0004, div);
break;
case WM9713_HIFI_DIV:
snd_soc_component_update_bits(component, AC97_HANDSET_RATE, 0x7000, div);
break;
case WM9713_PCMBCLK_DIV:
snd_soc_component_update_bits(component, AC97_CENTER_LFE_MASTER, 0x0e00, div);
break;
case WM9713_PCMCLK_PLL_DIV:
snd_soc_component_update_bits(component, AC97_LINE1_LEVEL,
0x007f, div | 0x60);
break;
case WM9713_HIFI_PLL_DIV:
snd_soc_component_update_bits(component, AC97_LINE1_LEVEL,
0x007f, div | 0x70);
break;
default:
return -EINVAL;
}
return 0;
}
static int wm9713_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
u16 gpio = snd_soc_component_read(component, AC97_GPIO_CFG) & 0xffc5;
u16 reg = 0x8000;
/* clock masters */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
reg |= 0x4000;
gpio |= 0x0010;
break;
case SND_SOC_DAIFMT_CBM_CFS:
reg |= 0x6000;
gpio |= 0x0018;
break;
case SND_SOC_DAIFMT_CBS_CFS:
reg |= 0x2000;
gpio |= 0x001a;
break;
case SND_SOC_DAIFMT_CBS_CFM:
gpio |= 0x0012;
break;
}
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_IB_IF:
reg |= 0x00c0;
break;
case SND_SOC_DAIFMT_IB_NF:
reg |= 0x0080;
break;
case SND_SOC_DAIFMT_NB_IF:
reg |= 0x0040;
break;
}
/* DAI format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
reg |= 0x0002;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
reg |= 0x0001;
break;
case SND_SOC_DAIFMT_DSP_A:
reg |= 0x0003;
break;
case SND_SOC_DAIFMT_DSP_B:
reg |= 0x0043;
break;
}
snd_soc_component_write(component, AC97_GPIO_CFG, gpio);
snd_soc_component_write(component, AC97_CENTER_LFE_MASTER, reg);
return 0;
}
static int wm9713_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
/* enable PCM interface in master mode */
switch (params_width(params)) {
case 16:
break;
case 20:
snd_soc_component_update_bits(component, AC97_CENTER_LFE_MASTER,
0x000c, 0x0004);
break;
case 24:
snd_soc_component_update_bits(component, AC97_CENTER_LFE_MASTER,
0x000c, 0x0008);
break;
case 32:
snd_soc_component_update_bits(component, AC97_CENTER_LFE_MASTER,
0x000c, 0x000c);
break;
}
return 0;
}
static int ac97_hifi_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct snd_pcm_runtime *runtime = substream->runtime;
int reg;
snd_soc_component_update_bits(component, AC97_EXTENDED_STATUS, 0x0001, 0x0001);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
reg = AC97_PCM_FRONT_DAC_RATE;
else
reg = AC97_PCM_LR_ADC_RATE;
return snd_soc_component_write(component, reg, runtime->rate);
}
static int ac97_aux_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct snd_pcm_runtime *runtime = substream->runtime;
snd_soc_component_update_bits(component, AC97_EXTENDED_STATUS, 0x0001, 0x0001);
snd_soc_component_update_bits(component, AC97_PCI_SID, 0x8000, 0x8000);
if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
return -ENODEV;
return snd_soc_component_write(component, AC97_PCM_SURR_DAC_RATE, runtime->rate);
}
#define WM9713_RATES (SNDRV_PCM_RATE_8000 | \
SNDRV_PCM_RATE_11025 | \
SNDRV_PCM_RATE_22050 | \
SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000)
#define WM9713_PCM_RATES (SNDRV_PCM_RATE_8000 | \
SNDRV_PCM_RATE_11025 | \
SNDRV_PCM_RATE_16000 | \
SNDRV_PCM_RATE_22050 | \
SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000)
#define WM9713_PCM_FORMATS \
(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE)
static const struct snd_soc_dai_ops wm9713_dai_ops_hifi = {
.prepare = ac97_hifi_prepare,
.set_clkdiv = wm9713_set_dai_clkdiv,
.set_pll = wm9713_set_dai_pll,
};
static const struct snd_soc_dai_ops wm9713_dai_ops_aux = {
.prepare = ac97_aux_prepare,
.set_clkdiv = wm9713_set_dai_clkdiv,
.set_pll = wm9713_set_dai_pll,
};
static const struct snd_soc_dai_ops wm9713_dai_ops_voice = {
.hw_params = wm9713_pcm_hw_params,
.set_clkdiv = wm9713_set_dai_clkdiv,
.set_pll = wm9713_set_dai_pll,
.set_fmt = wm9713_set_dai_fmt,
.set_tristate = wm9713_set_dai_tristate,
};
static struct snd_soc_dai_driver wm9713_dai[] = {
{
.name = "wm9713-hifi",
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM9713_RATES,
.formats = SND_SOC_STD_AC97_FMTS,},
.capture = {
.stream_name = "HiFi Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM9713_RATES,
.formats = SND_SOC_STD_AC97_FMTS,},
.ops = &wm9713_dai_ops_hifi,
},
{
.name = "wm9713-aux",
.playback = {
.stream_name = "Aux Playback",
.channels_min = 1,
.channels_max = 1,
.rates = WM9713_RATES,
.formats = SND_SOC_STD_AC97_FMTS,},
.ops = &wm9713_dai_ops_aux,
},
{
.name = "wm9713-voice",
.playback = {
.stream_name = "Voice Playback",
.channels_min = 1,
.channels_max = 1,
.rates = WM9713_PCM_RATES,
.formats = WM9713_PCM_FORMATS,},
.capture = {
.stream_name = "Voice Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM9713_PCM_RATES,
.formats = WM9713_PCM_FORMATS,},
.ops = &wm9713_dai_ops_voice,
.symmetric_rate = 1,
},
};
static int wm9713_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
switch (level) {
case SND_SOC_BIAS_ON:
/* enable thermal shutdown */
snd_soc_component_update_bits(component, AC97_EXTENDED_MID, 0xe400, 0x0000);
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
/* enable master bias and vmid */
snd_soc_component_update_bits(component, AC97_EXTENDED_MID, 0xc400, 0x0000);
snd_soc_component_write(component, AC97_POWERDOWN, 0x0000);
break;
case SND_SOC_BIAS_OFF:
/* disable everything including AC link */
snd_soc_component_write(component, AC97_EXTENDED_MID, 0xffff);
snd_soc_component_write(component, AC97_EXTENDED_MSTATUS, 0xffff);
snd_soc_component_write(component, AC97_POWERDOWN, 0xffff);
break;
}
return 0;
}
static int wm9713_soc_suspend(struct snd_soc_component *component)
{
/* Disable everything except touchpanel - that will be handled
* by the touch driver and left disabled if touch is not in
* use. */
snd_soc_component_update_bits(component, AC97_EXTENDED_MID, 0x7fff,
0x7fff);
snd_soc_component_write(component, AC97_EXTENDED_MSTATUS, 0xffff);
snd_soc_component_write(component, AC97_POWERDOWN, 0x6f00);
snd_soc_component_write(component, AC97_POWERDOWN, 0xffff);
return 0;
}
static int wm9713_soc_resume(struct snd_soc_component *component)
{
struct wm9713_priv *wm9713 = snd_soc_component_get_drvdata(component);
int ret;
ret = snd_ac97_reset(wm9713->ac97, true, WM9713_VENDOR_ID,
WM9713_VENDOR_ID_MASK);
if (ret < 0)
return ret;
snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
/* do we need to re-start the PLL ? */
if (wm9713->pll_in)
wm9713_set_pll(component, 0, wm9713->pll_in, 0);
/* only synchronise the codec if warm reset failed */
if (ret == 0) {
regcache_mark_dirty(component->regmap);
snd_soc_component_cache_sync(component);
}
return ret;
}
static int wm9713_soc_probe(struct snd_soc_component *component)
{
struct wm9713_priv *wm9713 = snd_soc_component_get_drvdata(component);
struct regmap *regmap = NULL;
if (wm9713->mfd_pdata) {
wm9713->ac97 = wm9713->mfd_pdata->ac97;
regmap = wm9713->mfd_pdata->regmap;
} else if (IS_ENABLED(CONFIG_SND_SOC_AC97_BUS)) {
wm9713->ac97 = snd_soc_new_ac97_component(component, WM9713_VENDOR_ID,
WM9713_VENDOR_ID_MASK);
if (IS_ERR(wm9713->ac97))
return PTR_ERR(wm9713->ac97);
regmap = regmap_init_ac97(wm9713->ac97, &wm9713_regmap_config);
if (IS_ERR(regmap)) {
snd_soc_free_ac97_component(wm9713->ac97);
return PTR_ERR(regmap);
}
} else {
return -ENXIO;
}
snd_soc_component_init_regmap(component, regmap);
/* unmute the adc - move to kcontrol */
snd_soc_component_update_bits(component, AC97_CD, 0x7fff, 0x0000);
return 0;
}
static void wm9713_soc_remove(struct snd_soc_component *component)
{
struct wm9713_priv *wm9713 = snd_soc_component_get_drvdata(component);
if (IS_ENABLED(CONFIG_SND_SOC_AC97_BUS) && !wm9713->mfd_pdata) {
snd_soc_component_exit_regmap(component);
snd_soc_free_ac97_component(wm9713->ac97);
}
}
static const struct snd_soc_component_driver soc_component_dev_wm9713 = {
.probe = wm9713_soc_probe,
.remove = wm9713_soc_remove,
.suspend = wm9713_soc_suspend,
.resume = wm9713_soc_resume,
.set_bias_level = wm9713_set_bias_level,
.controls = wm9713_snd_ac97_controls,
.num_controls = ARRAY_SIZE(wm9713_snd_ac97_controls),
.dapm_widgets = wm9713_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm9713_dapm_widgets),
.dapm_routes = wm9713_audio_map,
.num_dapm_routes = ARRAY_SIZE(wm9713_audio_map),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int wm9713_probe(struct platform_device *pdev)
{
struct wm9713_priv *wm9713;
wm9713 = devm_kzalloc(&pdev->dev, sizeof(*wm9713), GFP_KERNEL);
if (wm9713 == NULL)
return -ENOMEM;
mutex_init(&wm9713->lock);
wm9713->mfd_pdata = dev_get_platdata(&pdev->dev);
platform_set_drvdata(pdev, wm9713);
return devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_wm9713, wm9713_dai, ARRAY_SIZE(wm9713_dai));
}
static struct platform_driver wm9713_codec_driver = {
.driver = {
.name = "wm9713-codec",
},
.probe = wm9713_probe,
};
module_platform_driver(wm9713_codec_driver);
MODULE_DESCRIPTION("ASoC WM9713/WM9714 driver");
MODULE_AUTHOR("Liam Girdwood");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm9713.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright(c) 2021-2022 Intel Corporation. All rights reserved.
//
// Author: Cezary Rojewski <[email protected]>
//
#include <sound/soc.h>
#include <sound/hda_codec.h>
#include "hda.h"
static int hda_codec_dai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
{
struct hda_pcm_stream *stream_info;
struct hda_codec *codec;
struct hda_pcm *pcm;
int ret;
codec = dev_to_hda_codec(dai->dev);
stream_info = snd_soc_dai_get_dma_data(dai, substream);
pcm = container_of(stream_info, struct hda_pcm, stream[substream->stream]);
dev_dbg(dai->dev, "open stream codec: %08x, info: %p, pcm: %p %s substream: %p\n",
codec->core.vendor_id, stream_info, pcm, pcm->name, substream);
snd_hda_codec_pcm_get(pcm);
ret = stream_info->ops.open(stream_info, codec, substream);
if (ret < 0) {
dev_err(dai->dev, "codec open failed: %d\n", ret);
snd_hda_codec_pcm_put(pcm);
return ret;
}
return 0;
}
static void hda_codec_dai_shutdown(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
{
struct hda_pcm_stream *stream_info;
struct hda_codec *codec;
struct hda_pcm *pcm;
int ret;
codec = dev_to_hda_codec(dai->dev);
stream_info = snd_soc_dai_get_dma_data(dai, substream);
pcm = container_of(stream_info, struct hda_pcm, stream[substream->stream]);
dev_dbg(dai->dev, "close stream codec: %08x, info: %p, pcm: %p %s substream: %p\n",
codec->core.vendor_id, stream_info, pcm, pcm->name, substream);
ret = stream_info->ops.close(stream_info, codec, substream);
if (ret < 0)
dev_err(dai->dev, "codec close failed: %d\n", ret);
snd_hda_codec_pcm_put(pcm);
}
static int hda_codec_dai_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
{
struct hda_pcm_stream *stream_info;
struct hda_codec *codec;
codec = dev_to_hda_codec(dai->dev);
stream_info = snd_soc_dai_get_dma_data(dai, substream);
snd_hda_codec_cleanup(codec, stream_info, substream);
return 0;
}
static int hda_codec_dai_prepare(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct hda_pcm_stream *stream_info;
struct hdac_stream *stream;
struct hda_codec *codec;
unsigned int format;
int ret;
codec = dev_to_hda_codec(dai->dev);
stream = substream->runtime->private_data;
stream_info = snd_soc_dai_get_dma_data(dai, substream);
format = snd_hdac_calc_stream_format(runtime->rate, runtime->channels, runtime->format,
runtime->sample_bits, 0);
ret = snd_hda_codec_prepare(codec, stream_info, stream->stream_tag, format, substream);
if (ret < 0) {
dev_err(dai->dev, "codec prepare failed: %d\n", ret);
return ret;
}
return 0;
}
const struct snd_soc_dai_ops snd_soc_hda_codec_dai_ops = {
.startup = hda_codec_dai_startup,
.shutdown = hda_codec_dai_shutdown,
.hw_free = hda_codec_dai_hw_free,
.prepare = hda_codec_dai_prepare,
};
EXPORT_SYMBOL_GPL(snd_soc_hda_codec_dai_ops);
| linux-master | sound/soc/codecs/hda-dai.c |
// SPDX-License-Identifier: GPL-2.0
//
// cs35l41-spi.c -- CS35l41 SPI driver
//
// Copyright 2017-2021 Cirrus Logic, Inc.
//
// Author: David Rhodes <[email protected]>
#include <linux/acpi.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include "cs35l41.h"
static const struct spi_device_id cs35l41_id_spi[] = {
{ "cs35l40", 0 },
{ "cs35l41", 0 },
{ "cs35l51", 0 },
{ "cs35l53", 0 },
{}
};
MODULE_DEVICE_TABLE(spi, cs35l41_id_spi);
static int cs35l41_spi_probe(struct spi_device *spi)
{
const struct regmap_config *regmap_config = &cs35l41_regmap_spi;
struct cs35l41_hw_cfg *hw_cfg = dev_get_platdata(&spi->dev);
struct cs35l41_private *cs35l41;
int ret;
cs35l41 = devm_kzalloc(&spi->dev, sizeof(struct cs35l41_private), GFP_KERNEL);
if (!cs35l41)
return -ENOMEM;
spi->max_speed_hz = CS35L41_SPI_MAX_FREQ;
spi_setup(spi);
spi_set_drvdata(spi, cs35l41);
cs35l41->regmap = devm_regmap_init_spi(spi, regmap_config);
if (IS_ERR(cs35l41->regmap)) {
ret = PTR_ERR(cs35l41->regmap);
dev_err(&spi->dev, "Failed to allocate register map: %d\n", ret);
return ret;
}
cs35l41->dev = &spi->dev;
cs35l41->irq = spi->irq;
return cs35l41_probe(cs35l41, hw_cfg);
}
static void cs35l41_spi_remove(struct spi_device *spi)
{
struct cs35l41_private *cs35l41 = spi_get_drvdata(spi);
cs35l41_remove(cs35l41);
}
#ifdef CONFIG_OF
static const struct of_device_id cs35l41_of_match[] = {
{ .compatible = "cirrus,cs35l40" },
{ .compatible = "cirrus,cs35l41" },
{},
};
MODULE_DEVICE_TABLE(of, cs35l41_of_match);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id cs35l41_acpi_match[] = {
{ "CSC3541", 0 }, /* Cirrus Logic PnP ID + part ID */
{ "CLSA3541", 0 }, /* Cirrus Logic PnP ID + part ID */
{},
};
MODULE_DEVICE_TABLE(acpi, cs35l41_acpi_match);
#endif
static struct spi_driver cs35l41_spi_driver = {
.driver = {
.name = "cs35l41",
.pm = &cs35l41_pm_ops,
.of_match_table = of_match_ptr(cs35l41_of_match),
.acpi_match_table = ACPI_PTR(cs35l41_acpi_match),
},
.id_table = cs35l41_id_spi,
.probe = cs35l41_spi_probe,
.remove = cs35l41_spi_remove,
};
module_spi_driver(cs35l41_spi_driver);
MODULE_DESCRIPTION("SPI CS35L41 driver");
MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cs35l41-spi.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Codec driver for ST STA32x 2.1-channel high-efficiency digital audio system
*
* Copyright: 2011 Raumfeld GmbH
* Author: Johannes Stezenbach <[email protected]>
*
* based on code from:
* Wolfson Microelectronics PLC.
* Mark Brown <[email protected]>
* Freescale Semiconductor, Inc.
* Timur Tabi <[email protected]>
*/
#define pr_fmt(fmt) KBUILD_MODNAME ":%s:%d: " fmt, __func__, __LINE__
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/gpio/consumer.h>
#include <linux/slab.h>
#include <linux/workqueue.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/sta32x.h>
#include "sta32x.h"
#define STA32X_RATES (SNDRV_PCM_RATE_32000 | \
SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000 | \
SNDRV_PCM_RATE_88200 | \
SNDRV_PCM_RATE_96000 | \
SNDRV_PCM_RATE_176400 | \
SNDRV_PCM_RATE_192000)
#define STA32X_FORMATS \
(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \
SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
/* Power-up register defaults */
static const struct reg_default sta32x_regs[] = {
{ 0x0, 0x63 },
{ 0x1, 0x80 },
{ 0x2, 0xc2 },
{ 0x3, 0x40 },
{ 0x4, 0xc2 },
{ 0x5, 0x5c },
{ 0x6, 0x10 },
{ 0x7, 0xff },
{ 0x8, 0x60 },
{ 0x9, 0x60 },
{ 0xa, 0x60 },
{ 0xb, 0x80 },
{ 0xc, 0x00 },
{ 0xd, 0x00 },
{ 0xe, 0x00 },
{ 0xf, 0x40 },
{ 0x10, 0x80 },
{ 0x11, 0x77 },
{ 0x12, 0x6a },
{ 0x13, 0x69 },
{ 0x14, 0x6a },
{ 0x15, 0x69 },
{ 0x16, 0x00 },
{ 0x17, 0x00 },
{ 0x18, 0x00 },
{ 0x19, 0x00 },
{ 0x1a, 0x00 },
{ 0x1b, 0x00 },
{ 0x1c, 0x00 },
{ 0x1d, 0x00 },
{ 0x1e, 0x00 },
{ 0x1f, 0x00 },
{ 0x20, 0x00 },
{ 0x21, 0x00 },
{ 0x22, 0x00 },
{ 0x23, 0x00 },
{ 0x24, 0x00 },
{ 0x25, 0x00 },
{ 0x26, 0x00 },
{ 0x27, 0x2d },
{ 0x28, 0xc0 },
{ 0x2b, 0x00 },
{ 0x2c, 0x0c },
};
static const struct regmap_range sta32x_write_regs_range[] = {
regmap_reg_range(STA32X_CONFA, STA32X_FDRC2),
};
static const struct regmap_range sta32x_read_regs_range[] = {
regmap_reg_range(STA32X_CONFA, STA32X_FDRC2),
};
static const struct regmap_range sta32x_volatile_regs_range[] = {
regmap_reg_range(STA32X_CFADDR2, STA32X_CFUD),
};
static const struct regmap_access_table sta32x_write_regs = {
.yes_ranges = sta32x_write_regs_range,
.n_yes_ranges = ARRAY_SIZE(sta32x_write_regs_range),
};
static const struct regmap_access_table sta32x_read_regs = {
.yes_ranges = sta32x_read_regs_range,
.n_yes_ranges = ARRAY_SIZE(sta32x_read_regs_range),
};
static const struct regmap_access_table sta32x_volatile_regs = {
.yes_ranges = sta32x_volatile_regs_range,
.n_yes_ranges = ARRAY_SIZE(sta32x_volatile_regs_range),
};
/* regulator power supply names */
static const char *sta32x_supply_names[] = {
"Vdda", /* analog supply, 3.3VV */
"Vdd3", /* digital supply, 3.3V */
"Vcc" /* power amp spply, 10V - 36V */
};
/* codec private data */
struct sta32x_priv {
struct regmap *regmap;
struct clk *xti_clk;
struct regulator_bulk_data supplies[ARRAY_SIZE(sta32x_supply_names)];
struct snd_soc_component *component;
struct sta32x_platform_data *pdata;
unsigned int mclk;
unsigned int format;
u32 coef_shadow[STA32X_COEF_COUNT];
struct delayed_work watchdog_work;
int shutdown;
struct gpio_desc *gpiod_nreset;
struct mutex coeff_lock;
};
static const DECLARE_TLV_DB_SCALE(mvol_tlv, -12700, 50, 1);
static const DECLARE_TLV_DB_SCALE(chvol_tlv, -7950, 50, 1);
static const DECLARE_TLV_DB_SCALE(tone_tlv, -120, 200, 0);
static const char *sta32x_drc_ac[] = {
"Anti-Clipping", "Dynamic Range Compression" };
static const char *sta32x_auto_eq_mode[] = {
"User", "Preset", "Loudness" };
static const char *sta32x_auto_gc_mode[] = {
"User", "AC no clipping", "AC limited clipping (10%)",
"DRC nighttime listening mode" };
static const char *sta32x_auto_xo_mode[] = {
"User", "80Hz", "100Hz", "120Hz", "140Hz", "160Hz", "180Hz", "200Hz",
"220Hz", "240Hz", "260Hz", "280Hz", "300Hz", "320Hz", "340Hz", "360Hz" };
static const char *sta32x_preset_eq_mode[] = {
"Flat", "Rock", "Soft Rock", "Jazz", "Classical", "Dance", "Pop", "Soft",
"Hard", "Party", "Vocal", "Hip-Hop", "Dialog", "Bass-boost #1",
"Bass-boost #2", "Bass-boost #3", "Loudness 1", "Loudness 2",
"Loudness 3", "Loudness 4", "Loudness 5", "Loudness 6", "Loudness 7",
"Loudness 8", "Loudness 9", "Loudness 10", "Loudness 11", "Loudness 12",
"Loudness 13", "Loudness 14", "Loudness 15", "Loudness 16" };
static const char *sta32x_limiter_select[] = {
"Limiter Disabled", "Limiter #1", "Limiter #2" };
static const char *sta32x_limiter_attack_rate[] = {
"3.1584", "2.7072", "2.2560", "1.8048", "1.3536", "0.9024",
"0.4512", "0.2256", "0.1504", "0.1123", "0.0902", "0.0752",
"0.0645", "0.0564", "0.0501", "0.0451" };
static const char *sta32x_limiter_release_rate[] = {
"0.5116", "0.1370", "0.0744", "0.0499", "0.0360", "0.0299",
"0.0264", "0.0208", "0.0198", "0.0172", "0.0147", "0.0137",
"0.0134", "0.0117", "0.0110", "0.0104" };
static DECLARE_TLV_DB_RANGE(sta32x_limiter_ac_attack_tlv,
0, 7, TLV_DB_SCALE_ITEM(-1200, 200, 0),
8, 16, TLV_DB_SCALE_ITEM(300, 100, 0),
);
static DECLARE_TLV_DB_RANGE(sta32x_limiter_ac_release_tlv,
0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0),
1, 1, TLV_DB_SCALE_ITEM(-2900, 0, 0),
2, 2, TLV_DB_SCALE_ITEM(-2000, 0, 0),
3, 8, TLV_DB_SCALE_ITEM(-1400, 200, 0),
8, 16, TLV_DB_SCALE_ITEM(-700, 100, 0),
);
static DECLARE_TLV_DB_RANGE(sta32x_limiter_drc_attack_tlv,
0, 7, TLV_DB_SCALE_ITEM(-3100, 200, 0),
8, 13, TLV_DB_SCALE_ITEM(-1600, 100, 0),
14, 16, TLV_DB_SCALE_ITEM(-1000, 300, 0),
);
static DECLARE_TLV_DB_RANGE(sta32x_limiter_drc_release_tlv,
0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0),
1, 2, TLV_DB_SCALE_ITEM(-3800, 200, 0),
3, 4, TLV_DB_SCALE_ITEM(-3300, 200, 0),
5, 12, TLV_DB_SCALE_ITEM(-3000, 200, 0),
13, 16, TLV_DB_SCALE_ITEM(-1500, 300, 0),
);
static SOC_ENUM_SINGLE_DECL(sta32x_drc_ac_enum,
STA32X_CONFD, STA32X_CONFD_DRC_SHIFT,
sta32x_drc_ac);
static SOC_ENUM_SINGLE_DECL(sta32x_auto_eq_enum,
STA32X_AUTO1, STA32X_AUTO1_AMEQ_SHIFT,
sta32x_auto_eq_mode);
static SOC_ENUM_SINGLE_DECL(sta32x_auto_gc_enum,
STA32X_AUTO1, STA32X_AUTO1_AMGC_SHIFT,
sta32x_auto_gc_mode);
static SOC_ENUM_SINGLE_DECL(sta32x_auto_xo_enum,
STA32X_AUTO2, STA32X_AUTO2_XO_SHIFT,
sta32x_auto_xo_mode);
static SOC_ENUM_SINGLE_DECL(sta32x_preset_eq_enum,
STA32X_AUTO3, STA32X_AUTO3_PEQ_SHIFT,
sta32x_preset_eq_mode);
static SOC_ENUM_SINGLE_DECL(sta32x_limiter_ch1_enum,
STA32X_C1CFG, STA32X_CxCFG_LS_SHIFT,
sta32x_limiter_select);
static SOC_ENUM_SINGLE_DECL(sta32x_limiter_ch2_enum,
STA32X_C2CFG, STA32X_CxCFG_LS_SHIFT,
sta32x_limiter_select);
static SOC_ENUM_SINGLE_DECL(sta32x_limiter_ch3_enum,
STA32X_C3CFG, STA32X_CxCFG_LS_SHIFT,
sta32x_limiter_select);
static SOC_ENUM_SINGLE_DECL(sta32x_limiter1_attack_rate_enum,
STA32X_L1AR, STA32X_LxA_SHIFT,
sta32x_limiter_attack_rate);
static SOC_ENUM_SINGLE_DECL(sta32x_limiter2_attack_rate_enum,
STA32X_L2AR, STA32X_LxA_SHIFT,
sta32x_limiter_attack_rate);
static SOC_ENUM_SINGLE_DECL(sta32x_limiter1_release_rate_enum,
STA32X_L1AR, STA32X_LxR_SHIFT,
sta32x_limiter_release_rate);
static SOC_ENUM_SINGLE_DECL(sta32x_limiter2_release_rate_enum,
STA32X_L2AR, STA32X_LxR_SHIFT,
sta32x_limiter_release_rate);
/* byte array controls for setting biquad, mixer, scaling coefficients;
* for biquads all five coefficients need to be set in one go,
* mixer and pre/postscale coefs can be set individually;
* each coef is 24bit, the bytes are ordered in the same way
* as given in the STA32x data sheet (big endian; b1, b2, a1, a2, b0)
*/
static int sta32x_coefficient_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
int numcoef = kcontrol->private_value >> 16;
uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
uinfo->count = 3 * numcoef;
return 0;
}
static int sta32x_coefficient_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
int numcoef = kcontrol->private_value >> 16;
int index = kcontrol->private_value & 0xffff;
unsigned int cfud, val;
int i, ret = 0;
mutex_lock(&sta32x->coeff_lock);
/* preserve reserved bits in STA32X_CFUD */
regmap_read(sta32x->regmap, STA32X_CFUD, &cfud);
cfud &= 0xf0;
/*
* chip documentation does not say if the bits are self clearing,
* so do it explicitly
*/
regmap_write(sta32x->regmap, STA32X_CFUD, cfud);
regmap_write(sta32x->regmap, STA32X_CFADDR2, index);
if (numcoef == 1) {
regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x04);
} else if (numcoef == 5) {
regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x08);
} else {
ret = -EINVAL;
goto exit_unlock;
}
for (i = 0; i < 3 * numcoef; i++) {
regmap_read(sta32x->regmap, STA32X_B1CF1 + i, &val);
ucontrol->value.bytes.data[i] = val;
}
exit_unlock:
mutex_unlock(&sta32x->coeff_lock);
return ret;
}
static int sta32x_coefficient_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
int numcoef = kcontrol->private_value >> 16;
int index = kcontrol->private_value & 0xffff;
unsigned int cfud;
int i;
/* preserve reserved bits in STA32X_CFUD */
regmap_read(sta32x->regmap, STA32X_CFUD, &cfud);
cfud &= 0xf0;
/*
* chip documentation does not say if the bits are self clearing,
* so do it explicitly
*/
regmap_write(sta32x->regmap, STA32X_CFUD, cfud);
regmap_write(sta32x->regmap, STA32X_CFADDR2, index);
for (i = 0; i < numcoef && (index + i < STA32X_COEF_COUNT); i++)
sta32x->coef_shadow[index + i] =
(ucontrol->value.bytes.data[3 * i] << 16)
| (ucontrol->value.bytes.data[3 * i + 1] << 8)
| (ucontrol->value.bytes.data[3 * i + 2]);
for (i = 0; i < 3 * numcoef; i++)
regmap_write(sta32x->regmap, STA32X_B1CF1 + i,
ucontrol->value.bytes.data[i]);
if (numcoef == 1)
regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x01);
else if (numcoef == 5)
regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x02);
else
return -EINVAL;
return 0;
}
static int sta32x_sync_coef_shadow(struct snd_soc_component *component)
{
struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
unsigned int cfud;
int i;
/* preserve reserved bits in STA32X_CFUD */
regmap_read(sta32x->regmap, STA32X_CFUD, &cfud);
cfud &= 0xf0;
for (i = 0; i < STA32X_COEF_COUNT; i++) {
regmap_write(sta32x->regmap, STA32X_CFADDR2, i);
regmap_write(sta32x->regmap, STA32X_B1CF1,
(sta32x->coef_shadow[i] >> 16) & 0xff);
regmap_write(sta32x->regmap, STA32X_B1CF2,
(sta32x->coef_shadow[i] >> 8) & 0xff);
regmap_write(sta32x->regmap, STA32X_B1CF3,
(sta32x->coef_shadow[i]) & 0xff);
/*
* chip documentation does not say if the bits are
* self-clearing, so do it explicitly
*/
regmap_write(sta32x->regmap, STA32X_CFUD, cfud);
regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x01);
}
return 0;
}
static int sta32x_cache_sync(struct snd_soc_component *component)
{
struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
unsigned int mute;
int rc;
/* mute during register sync */
regmap_read(sta32x->regmap, STA32X_MMUTE, &mute);
regmap_write(sta32x->regmap, STA32X_MMUTE, mute | STA32X_MMUTE_MMUTE);
sta32x_sync_coef_shadow(component);
rc = regcache_sync(sta32x->regmap);
regmap_write(sta32x->regmap, STA32X_MMUTE, mute);
return rc;
}
/* work around ESD issue where sta32x resets and loses all configuration */
static void sta32x_watchdog(struct work_struct *work)
{
struct sta32x_priv *sta32x = container_of(work, struct sta32x_priv,
watchdog_work.work);
struct snd_soc_component *component = sta32x->component;
unsigned int confa, confa_cached;
/* check if sta32x has reset itself */
confa_cached = snd_soc_component_read(component, STA32X_CONFA);
regcache_cache_bypass(sta32x->regmap, true);
confa = snd_soc_component_read(component, STA32X_CONFA);
regcache_cache_bypass(sta32x->regmap, false);
if (confa != confa_cached) {
regcache_mark_dirty(sta32x->regmap);
sta32x_cache_sync(component);
}
if (!sta32x->shutdown)
queue_delayed_work(system_power_efficient_wq,
&sta32x->watchdog_work,
round_jiffies_relative(HZ));
}
static void sta32x_watchdog_start(struct sta32x_priv *sta32x)
{
if (sta32x->pdata->needs_esd_watchdog) {
sta32x->shutdown = 0;
queue_delayed_work(system_power_efficient_wq,
&sta32x->watchdog_work,
round_jiffies_relative(HZ));
}
}
static void sta32x_watchdog_stop(struct sta32x_priv *sta32x)
{
if (sta32x->pdata->needs_esd_watchdog) {
sta32x->shutdown = 1;
cancel_delayed_work_sync(&sta32x->watchdog_work);
}
}
#define SINGLE_COEF(xname, index) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
.info = sta32x_coefficient_info, \
.get = sta32x_coefficient_get,\
.put = sta32x_coefficient_put, \
.private_value = index | (1 << 16) }
#define BIQUAD_COEFS(xname, index) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
.info = sta32x_coefficient_info, \
.get = sta32x_coefficient_get,\
.put = sta32x_coefficient_put, \
.private_value = index | (5 << 16) }
static const struct snd_kcontrol_new sta32x_snd_controls[] = {
SOC_SINGLE_TLV("Master Volume", STA32X_MVOL, 0, 0xff, 1, mvol_tlv),
SOC_SINGLE("Master Switch", STA32X_MMUTE, 0, 1, 1),
SOC_SINGLE("Ch1 Switch", STA32X_MMUTE, 1, 1, 1),
SOC_SINGLE("Ch2 Switch", STA32X_MMUTE, 2, 1, 1),
SOC_SINGLE("Ch3 Switch", STA32X_MMUTE, 3, 1, 1),
SOC_SINGLE_TLV("Ch1 Volume", STA32X_C1VOL, 0, 0xff, 1, chvol_tlv),
SOC_SINGLE_TLV("Ch2 Volume", STA32X_C2VOL, 0, 0xff, 1, chvol_tlv),
SOC_SINGLE_TLV("Ch3 Volume", STA32X_C3VOL, 0, 0xff, 1, chvol_tlv),
SOC_SINGLE("De-emphasis Filter Switch", STA32X_CONFD, STA32X_CONFD_DEMP_SHIFT, 1, 0),
SOC_ENUM("Compressor/Limiter Switch", sta32x_drc_ac_enum),
SOC_SINGLE("Miami Mode Switch", STA32X_CONFD, STA32X_CONFD_MME_SHIFT, 1, 0),
SOC_SINGLE("Zero Cross Switch", STA32X_CONFE, STA32X_CONFE_ZCE_SHIFT, 1, 0),
SOC_SINGLE("Soft Ramp Switch", STA32X_CONFE, STA32X_CONFE_SVE_SHIFT, 1, 0),
SOC_SINGLE("Auto-Mute Switch", STA32X_CONFF, STA32X_CONFF_IDE_SHIFT, 1, 0),
SOC_ENUM("Automode EQ", sta32x_auto_eq_enum),
SOC_ENUM("Automode GC", sta32x_auto_gc_enum),
SOC_ENUM("Automode XO", sta32x_auto_xo_enum),
SOC_ENUM("Preset EQ", sta32x_preset_eq_enum),
SOC_SINGLE("Ch1 Tone Control Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_TCB_SHIFT, 1, 0),
SOC_SINGLE("Ch2 Tone Control Bypass Switch", STA32X_C2CFG, STA32X_CxCFG_TCB_SHIFT, 1, 0),
SOC_SINGLE("Ch1 EQ Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_EQBP_SHIFT, 1, 0),
SOC_SINGLE("Ch2 EQ Bypass Switch", STA32X_C2CFG, STA32X_CxCFG_EQBP_SHIFT, 1, 0),
SOC_SINGLE("Ch1 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0),
SOC_SINGLE("Ch2 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0),
SOC_SINGLE("Ch3 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0),
SOC_ENUM("Ch1 Limiter Select", sta32x_limiter_ch1_enum),
SOC_ENUM("Ch2 Limiter Select", sta32x_limiter_ch2_enum),
SOC_ENUM("Ch3 Limiter Select", sta32x_limiter_ch3_enum),
SOC_SINGLE_TLV("Bass Tone Control", STA32X_TONE, STA32X_TONE_BTC_SHIFT, 15, 0, tone_tlv),
SOC_SINGLE_TLV("Treble Tone Control", STA32X_TONE, STA32X_TONE_TTC_SHIFT, 15, 0, tone_tlv),
SOC_ENUM("Limiter1 Attack Rate (dB/ms)", sta32x_limiter1_attack_rate_enum),
SOC_ENUM("Limiter2 Attack Rate (dB/ms)", sta32x_limiter2_attack_rate_enum),
SOC_ENUM("Limiter1 Release Rate (dB/ms)", sta32x_limiter1_release_rate_enum),
SOC_ENUM("Limiter2 Release Rate (dB/ms)", sta32x_limiter2_release_rate_enum),
/* depending on mode, the attack/release thresholds have
* two different enum definitions; provide both
*/
SOC_SINGLE_TLV("Limiter1 Attack Threshold (AC Mode)", STA32X_L1ATRT, STA32X_LxA_SHIFT,
16, 0, sta32x_limiter_ac_attack_tlv),
SOC_SINGLE_TLV("Limiter2 Attack Threshold (AC Mode)", STA32X_L2ATRT, STA32X_LxA_SHIFT,
16, 0, sta32x_limiter_ac_attack_tlv),
SOC_SINGLE_TLV("Limiter1 Release Threshold (AC Mode)", STA32X_L1ATRT, STA32X_LxR_SHIFT,
16, 0, sta32x_limiter_ac_release_tlv),
SOC_SINGLE_TLV("Limiter2 Release Threshold (AC Mode)", STA32X_L2ATRT, STA32X_LxR_SHIFT,
16, 0, sta32x_limiter_ac_release_tlv),
SOC_SINGLE_TLV("Limiter1 Attack Threshold (DRC Mode)", STA32X_L1ATRT, STA32X_LxA_SHIFT,
16, 0, sta32x_limiter_drc_attack_tlv),
SOC_SINGLE_TLV("Limiter2 Attack Threshold (DRC Mode)", STA32X_L2ATRT, STA32X_LxA_SHIFT,
16, 0, sta32x_limiter_drc_attack_tlv),
SOC_SINGLE_TLV("Limiter1 Release Threshold (DRC Mode)", STA32X_L1ATRT, STA32X_LxR_SHIFT,
16, 0, sta32x_limiter_drc_release_tlv),
SOC_SINGLE_TLV("Limiter2 Release Threshold (DRC Mode)", STA32X_L2ATRT, STA32X_LxR_SHIFT,
16, 0, sta32x_limiter_drc_release_tlv),
BIQUAD_COEFS("Ch1 - Biquad 1", 0),
BIQUAD_COEFS("Ch1 - Biquad 2", 5),
BIQUAD_COEFS("Ch1 - Biquad 3", 10),
BIQUAD_COEFS("Ch1 - Biquad 4", 15),
BIQUAD_COEFS("Ch2 - Biquad 1", 20),
BIQUAD_COEFS("Ch2 - Biquad 2", 25),
BIQUAD_COEFS("Ch2 - Biquad 3", 30),
BIQUAD_COEFS("Ch2 - Biquad 4", 35),
BIQUAD_COEFS("High-pass", 40),
BIQUAD_COEFS("Low-pass", 45),
SINGLE_COEF("Ch1 - Prescale", 50),
SINGLE_COEF("Ch2 - Prescale", 51),
SINGLE_COEF("Ch1 - Postscale", 52),
SINGLE_COEF("Ch2 - Postscale", 53),
SINGLE_COEF("Ch3 - Postscale", 54),
SINGLE_COEF("Thermal warning - Postscale", 55),
SINGLE_COEF("Ch1 - Mix 1", 56),
SINGLE_COEF("Ch1 - Mix 2", 57),
SINGLE_COEF("Ch2 - Mix 1", 58),
SINGLE_COEF("Ch2 - Mix 2", 59),
SINGLE_COEF("Ch3 - Mix 1", 60),
SINGLE_COEF("Ch3 - Mix 2", 61),
};
static const struct snd_soc_dapm_widget sta32x_dapm_widgets[] = {
SND_SOC_DAPM_DAC("DAC", "Playback", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_OUTPUT("LEFT"),
SND_SOC_DAPM_OUTPUT("RIGHT"),
SND_SOC_DAPM_OUTPUT("SUB"),
};
static const struct snd_soc_dapm_route sta32x_dapm_routes[] = {
{ "LEFT", NULL, "DAC" },
{ "RIGHT", NULL, "DAC" },
{ "SUB", NULL, "DAC" },
};
/* MCLK interpolation ratio per fs */
static struct {
int fs;
int ir;
} interpolation_ratios[] = {
{ 32000, 0 },
{ 44100, 0 },
{ 48000, 0 },
{ 88200, 1 },
{ 96000, 1 },
{ 176400, 2 },
{ 192000, 2 },
};
/* MCLK to fs clock ratios */
static int mcs_ratio_table[3][7] = {
{ 768, 512, 384, 256, 128, 576, 0 },
{ 384, 256, 192, 128, 64, 0 },
{ 384, 256, 192, 128, 64, 0 },
};
/**
* sta32x_set_dai_sysclk - configure MCLK
* @codec_dai: the codec DAI
* @clk_id: the clock ID (ignored)
* @freq: the MCLK input frequency
* @dir: the clock direction (ignored)
*
* The value of MCLK is used to determine which sample rates are supported
* by the STA32X, based on the mclk_ratios table.
*
* This function must be called by the machine driver's 'startup' function,
* otherwise the list of supported sample rates will not be available in
* time for ALSA.
*
* For setups with variable MCLKs, pass 0 as 'freq' argument. This will cause
* theoretically possible sample rates to be enabled. Call it again with a
* proper value set one the external clock is set (most probably you would do
* that from a machine's driver 'hw_param' hook.
*/
static int sta32x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
dev_dbg(component->dev, "mclk=%u\n", freq);
sta32x->mclk = freq;
return 0;
}
/**
* sta32x_set_dai_fmt - configure the codec for the selected audio format
* @codec_dai: the codec DAI
* @fmt: a SND_SOC_DAIFMT_x value indicating the data format
*
* This function takes a bitmask of SND_SOC_DAIFMT_x bits and programs the
* codec accordingly.
*/
static int sta32x_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
u8 confb = 0;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_RIGHT_J:
case SND_SOC_DAIFMT_LEFT_J:
sta32x->format = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
confb |= STA32X_CONFB_C2IM;
break;
case SND_SOC_DAIFMT_NB_IF:
confb |= STA32X_CONFB_C1IM;
break;
default:
return -EINVAL;
}
return regmap_update_bits(sta32x->regmap, STA32X_CONFB,
STA32X_CONFB_C1IM | STA32X_CONFB_C2IM, confb);
}
/**
* sta32x_hw_params - program the STA32X with the given hardware parameters.
* @substream: the audio stream
* @params: the hardware parameters to set
* @dai: the SOC DAI (ignored)
*
* This function programs the hardware with the values provided.
* Specifically, the sample rate and the data format.
*/
static int sta32x_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
int i, mcs = -EINVAL, ir = -EINVAL;
unsigned int confa, confb;
unsigned int rate, ratio;
int ret;
if (!sta32x->mclk) {
dev_err(component->dev,
"sta32x->mclk is unset. Unable to determine ratio\n");
return -EIO;
}
rate = params_rate(params);
ratio = sta32x->mclk / rate;
dev_dbg(component->dev, "rate: %u, ratio: %u\n", rate, ratio);
for (i = 0; i < ARRAY_SIZE(interpolation_ratios); i++) {
if (interpolation_ratios[i].fs == rate) {
ir = interpolation_ratios[i].ir;
break;
}
}
if (ir < 0) {
dev_err(component->dev, "Unsupported samplerate: %u\n", rate);
return -EINVAL;
}
for (i = 0; i < 6; i++) {
if (mcs_ratio_table[ir][i] == ratio) {
mcs = i;
break;
}
}
if (mcs < 0) {
dev_err(component->dev, "Unresolvable ratio: %u\n", ratio);
return -EINVAL;
}
confa = (ir << STA32X_CONFA_IR_SHIFT) |
(mcs << STA32X_CONFA_MCS_SHIFT);
confb = 0;
switch (params_width(params)) {
case 24:
dev_dbg(component->dev, "24bit\n");
fallthrough;
case 32:
dev_dbg(component->dev, "24bit or 32bit\n");
switch (sta32x->format) {
case SND_SOC_DAIFMT_I2S:
confb |= 0x0;
break;
case SND_SOC_DAIFMT_LEFT_J:
confb |= 0x1;
break;
case SND_SOC_DAIFMT_RIGHT_J:
confb |= 0x2;
break;
}
break;
case 20:
dev_dbg(component->dev, "20bit\n");
switch (sta32x->format) {
case SND_SOC_DAIFMT_I2S:
confb |= 0x4;
break;
case SND_SOC_DAIFMT_LEFT_J:
confb |= 0x5;
break;
case SND_SOC_DAIFMT_RIGHT_J:
confb |= 0x6;
break;
}
break;
case 18:
dev_dbg(component->dev, "18bit\n");
switch (sta32x->format) {
case SND_SOC_DAIFMT_I2S:
confb |= 0x8;
break;
case SND_SOC_DAIFMT_LEFT_J:
confb |= 0x9;
break;
case SND_SOC_DAIFMT_RIGHT_J:
confb |= 0xa;
break;
}
break;
case 16:
dev_dbg(component->dev, "16bit\n");
switch (sta32x->format) {
case SND_SOC_DAIFMT_I2S:
confb |= 0x0;
break;
case SND_SOC_DAIFMT_LEFT_J:
confb |= 0xd;
break;
case SND_SOC_DAIFMT_RIGHT_J:
confb |= 0xe;
break;
}
break;
default:
return -EINVAL;
}
ret = regmap_update_bits(sta32x->regmap, STA32X_CONFA,
STA32X_CONFA_MCS_MASK | STA32X_CONFA_IR_MASK,
confa);
if (ret < 0)
return ret;
ret = regmap_update_bits(sta32x->regmap, STA32X_CONFB,
STA32X_CONFB_SAI_MASK | STA32X_CONFB_SAIFB,
confb);
if (ret < 0)
return ret;
return 0;
}
static int sta32x_startup_sequence(struct sta32x_priv *sta32x)
{
if (sta32x->gpiod_nreset) {
gpiod_set_value(sta32x->gpiod_nreset, 0);
mdelay(1);
gpiod_set_value(sta32x->gpiod_nreset, 1);
mdelay(1);
}
return 0;
}
/**
* sta32x_set_bias_level - DAPM callback
* @component: the component device
* @level: DAPM power level
*
* This is called by ALSA to put the component into low power mode
* or to wake it up. If the component is powered off completely
* all registers must be restored after power on.
*/
static int sta32x_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
int ret;
struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
dev_dbg(component->dev, "level = %d\n", level);
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
/* Full power on */
regmap_update_bits(sta32x->regmap, STA32X_CONFF,
STA32X_CONFF_PWDN | STA32X_CONFF_EAPD,
STA32X_CONFF_PWDN | STA32X_CONFF_EAPD);
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
ret = regulator_bulk_enable(ARRAY_SIZE(sta32x->supplies),
sta32x->supplies);
if (ret != 0) {
dev_err(component->dev,
"Failed to enable supplies: %d\n", ret);
return ret;
}
sta32x_startup_sequence(sta32x);
sta32x_cache_sync(component);
sta32x_watchdog_start(sta32x);
}
/* Power down */
regmap_update_bits(sta32x->regmap, STA32X_CONFF,
STA32X_CONFF_PWDN | STA32X_CONFF_EAPD,
0);
break;
case SND_SOC_BIAS_OFF:
/* The chip runs through the power down sequence for us. */
regmap_update_bits(sta32x->regmap, STA32X_CONFF,
STA32X_CONFF_PWDN | STA32X_CONFF_EAPD, 0);
msleep(300);
sta32x_watchdog_stop(sta32x);
gpiod_set_value(sta32x->gpiod_nreset, 0);
regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies),
sta32x->supplies);
break;
}
return 0;
}
static const struct snd_soc_dai_ops sta32x_dai_ops = {
.hw_params = sta32x_hw_params,
.set_sysclk = sta32x_set_dai_sysclk,
.set_fmt = sta32x_set_dai_fmt,
};
static struct snd_soc_dai_driver sta32x_dai = {
.name = "sta32x-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = STA32X_RATES,
.formats = STA32X_FORMATS,
},
.ops = &sta32x_dai_ops,
};
static int sta32x_probe(struct snd_soc_component *component)
{
struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
struct sta32x_platform_data *pdata = sta32x->pdata;
int i, ret = 0, thermal = 0;
sta32x->component = component;
if (sta32x->xti_clk) {
ret = clk_prepare_enable(sta32x->xti_clk);
if (ret != 0) {
dev_err(component->dev,
"Failed to enable clock: %d\n", ret);
return ret;
}
}
ret = regulator_bulk_enable(ARRAY_SIZE(sta32x->supplies),
sta32x->supplies);
if (ret != 0) {
dev_err(component->dev, "Failed to enable supplies: %d\n", ret);
goto err_clk_disable_unprepare;
}
ret = sta32x_startup_sequence(sta32x);
if (ret < 0) {
dev_err(component->dev, "Failed to startup device\n");
goto err_regulator_bulk_disable;
}
/* CONFA */
if (!pdata->thermal_warning_recovery)
thermal |= STA32X_CONFA_TWAB;
if (!pdata->thermal_warning_adjustment)
thermal |= STA32X_CONFA_TWRB;
if (!pdata->fault_detect_recovery)
thermal |= STA32X_CONFA_FDRB;
regmap_update_bits(sta32x->regmap, STA32X_CONFA,
STA32X_CONFA_TWAB | STA32X_CONFA_TWRB |
STA32X_CONFA_FDRB,
thermal);
/* CONFC */
regmap_update_bits(sta32x->regmap, STA32X_CONFC,
STA32X_CONFC_CSZ_MASK,
pdata->drop_compensation_ns
<< STA32X_CONFC_CSZ_SHIFT);
/* CONFE */
regmap_update_bits(sta32x->regmap, STA32X_CONFE,
STA32X_CONFE_MPCV,
pdata->max_power_use_mpcc ?
STA32X_CONFE_MPCV : 0);
regmap_update_bits(sta32x->regmap, STA32X_CONFE,
STA32X_CONFE_MPC,
pdata->max_power_correction ?
STA32X_CONFE_MPC : 0);
regmap_update_bits(sta32x->regmap, STA32X_CONFE,
STA32X_CONFE_AME,
pdata->am_reduction_mode ?
STA32X_CONFE_AME : 0);
regmap_update_bits(sta32x->regmap, STA32X_CONFE,
STA32X_CONFE_PWMS,
pdata->odd_pwm_speed_mode ?
STA32X_CONFE_PWMS : 0);
/* CONFF */
regmap_update_bits(sta32x->regmap, STA32X_CONFF,
STA32X_CONFF_IDE,
pdata->invalid_input_detect_mute ?
STA32X_CONFF_IDE : 0);
/* select output configuration */
regmap_update_bits(sta32x->regmap, STA32X_CONFF,
STA32X_CONFF_OCFG_MASK,
pdata->output_conf
<< STA32X_CONFF_OCFG_SHIFT);
/* channel to output mapping */
regmap_update_bits(sta32x->regmap, STA32X_C1CFG,
STA32X_CxCFG_OM_MASK,
pdata->ch1_output_mapping
<< STA32X_CxCFG_OM_SHIFT);
regmap_update_bits(sta32x->regmap, STA32X_C2CFG,
STA32X_CxCFG_OM_MASK,
pdata->ch2_output_mapping
<< STA32X_CxCFG_OM_SHIFT);
regmap_update_bits(sta32x->regmap, STA32X_C3CFG,
STA32X_CxCFG_OM_MASK,
pdata->ch3_output_mapping
<< STA32X_CxCFG_OM_SHIFT);
/* initialize coefficient shadow RAM with reset values */
for (i = 4; i <= 49; i += 5)
sta32x->coef_shadow[i] = 0x400000;
for (i = 50; i <= 54; i++)
sta32x->coef_shadow[i] = 0x7fffff;
sta32x->coef_shadow[55] = 0x5a9df7;
sta32x->coef_shadow[56] = 0x7fffff;
sta32x->coef_shadow[59] = 0x7fffff;
sta32x->coef_shadow[60] = 0x400000;
sta32x->coef_shadow[61] = 0x400000;
if (sta32x->pdata->needs_esd_watchdog)
INIT_DELAYED_WORK(&sta32x->watchdog_work, sta32x_watchdog);
snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
/* Bias level configuration will have done an extra enable */
regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies);
return 0;
err_regulator_bulk_disable:
regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies);
err_clk_disable_unprepare:
if (sta32x->xti_clk)
clk_disable_unprepare(sta32x->xti_clk);
return ret;
}
static void sta32x_remove(struct snd_soc_component *component)
{
struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
sta32x_watchdog_stop(sta32x);
regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies);
if (sta32x->xti_clk)
clk_disable_unprepare(sta32x->xti_clk);
}
static const struct snd_soc_component_driver sta32x_component = {
.probe = sta32x_probe,
.remove = sta32x_remove,
.set_bias_level = sta32x_set_bias_level,
.controls = sta32x_snd_controls,
.num_controls = ARRAY_SIZE(sta32x_snd_controls),
.dapm_widgets = sta32x_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(sta32x_dapm_widgets),
.dapm_routes = sta32x_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(sta32x_dapm_routes),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config sta32x_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = STA32X_FDRC2,
.reg_defaults = sta32x_regs,
.num_reg_defaults = ARRAY_SIZE(sta32x_regs),
.cache_type = REGCACHE_MAPLE,
.wr_table = &sta32x_write_regs,
.rd_table = &sta32x_read_regs,
.volatile_table = &sta32x_volatile_regs,
};
#ifdef CONFIG_OF
static const struct of_device_id st32x_dt_ids[] = {
{ .compatible = "st,sta32x", },
{ }
};
MODULE_DEVICE_TABLE(of, st32x_dt_ids);
static int sta32x_probe_dt(struct device *dev, struct sta32x_priv *sta32x)
{
struct device_node *np = dev->of_node;
struct sta32x_platform_data *pdata;
u16 tmp;
pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return -ENOMEM;
of_property_read_u8(np, "st,output-conf",
&pdata->output_conf);
of_property_read_u8(np, "st,ch1-output-mapping",
&pdata->ch1_output_mapping);
of_property_read_u8(np, "st,ch2-output-mapping",
&pdata->ch2_output_mapping);
of_property_read_u8(np, "st,ch3-output-mapping",
&pdata->ch3_output_mapping);
pdata->fault_detect_recovery =
of_property_read_bool(np, "st,fault-detect-recovery");
pdata->thermal_warning_recovery =
of_property_read_bool(np, "st,thermal-warning-recovery");
pdata->thermal_warning_adjustment =
of_property_read_bool(np, "st,thermal-warning-adjustment");
pdata->needs_esd_watchdog =
of_property_read_bool(np, "st,needs_esd_watchdog");
tmp = 140;
of_property_read_u16(np, "st,drop-compensation-ns", &tmp);
pdata->drop_compensation_ns = clamp_t(u16, tmp, 0, 300) / 20;
/* CONFE */
pdata->max_power_use_mpcc =
of_property_read_bool(np, "st,max-power-use-mpcc");
pdata->max_power_correction =
of_property_read_bool(np, "st,max-power-correction");
pdata->am_reduction_mode =
of_property_read_bool(np, "st,am-reduction-mode");
pdata->odd_pwm_speed_mode =
of_property_read_bool(np, "st,odd-pwm-speed-mode");
/* CONFF */
pdata->invalid_input_detect_mute =
of_property_read_bool(np, "st,invalid-input-detect-mute");
sta32x->pdata = pdata;
return 0;
}
#endif
static int sta32x_i2c_probe(struct i2c_client *i2c)
{
struct device *dev = &i2c->dev;
struct sta32x_priv *sta32x;
int ret, i;
sta32x = devm_kzalloc(&i2c->dev, sizeof(struct sta32x_priv),
GFP_KERNEL);
if (!sta32x)
return -ENOMEM;
mutex_init(&sta32x->coeff_lock);
sta32x->pdata = dev_get_platdata(dev);
#ifdef CONFIG_OF
if (dev->of_node) {
ret = sta32x_probe_dt(dev, sta32x);
if (ret < 0)
return ret;
}
#endif
/* Clock */
sta32x->xti_clk = devm_clk_get(dev, "xti");
if (IS_ERR(sta32x->xti_clk)) {
ret = PTR_ERR(sta32x->xti_clk);
if (ret == -EPROBE_DEFER)
return ret;
sta32x->xti_clk = NULL;
}
/* GPIOs */
sta32x->gpiod_nreset = devm_gpiod_get_optional(dev, "reset",
GPIOD_OUT_LOW);
if (IS_ERR(sta32x->gpiod_nreset))
return PTR_ERR(sta32x->gpiod_nreset);
/* regulators */
for (i = 0; i < ARRAY_SIZE(sta32x->supplies); i++)
sta32x->supplies[i].supply = sta32x_supply_names[i];
ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(sta32x->supplies),
sta32x->supplies);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
return ret;
}
sta32x->regmap = devm_regmap_init_i2c(i2c, &sta32x_regmap);
if (IS_ERR(sta32x->regmap)) {
ret = PTR_ERR(sta32x->regmap);
dev_err(dev, "Failed to init regmap: %d\n", ret);
return ret;
}
i2c_set_clientdata(i2c, sta32x);
ret = devm_snd_soc_register_component(dev, &sta32x_component,
&sta32x_dai, 1);
if (ret < 0)
dev_err(dev, "Failed to register component (%d)\n", ret);
return ret;
}
static const struct i2c_device_id sta32x_i2c_id[] = {
{ "sta326", 0 },
{ "sta328", 0 },
{ "sta329", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, sta32x_i2c_id);
static struct i2c_driver sta32x_i2c_driver = {
.driver = {
.name = "sta32x",
.of_match_table = of_match_ptr(st32x_dt_ids),
},
.probe = sta32x_i2c_probe,
.id_table = sta32x_i2c_id,
};
module_i2c_driver(sta32x_i2c_driver);
MODULE_DESCRIPTION("ASoC STA32X driver");
MODULE_AUTHOR("Johannes Stezenbach <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/sta32x.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) ST-Ericsson SA 2012
*
* Author: Ola Lilja <[email protected]>,
* Kristoffer Karlsson <[email protected]>,
* Roger Nilsson <[email protected]>,
* for ST-Ericsson.
*
* Based on the early work done by:
* Mikko J. Lehto <[email protected]>,
* Mikko Sarmanne <[email protected]>,
* Jarmo K. Kuronen <[email protected]>,
* for ST-Ericsson.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/slab.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/platform_device.h>
#include <linux/mutex.h>
#include <linux/mfd/abx500/ab8500.h>
#include <linux/mfd/abx500.h>
#include <linux/mfd/abx500/ab8500-sysctrl.h>
#include <linux/mfd/abx500/ab8500-codec.h>
#include <linux/regulator/consumer.h>
#include <linux/of.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/tlv.h>
#include "ab8500-codec.h"
/* Macrocell value definitions */
#define CLK_32K_OUT2_DISABLE 0x01
#define INACTIVE_RESET_AUDIO 0x02
#define ENABLE_AUDIO_CLK_TO_AUDIO_BLK 0x10
#define ENABLE_VINTCORE12_SUPPLY 0x04
#define GPIO27_DIR_OUTPUT 0x04
#define GPIO29_DIR_OUTPUT 0x10
#define GPIO31_DIR_OUTPUT 0x40
/* Macrocell register definitions */
#define AB8500_GPIO_DIR4_REG 0x13 /* Bank AB8500_MISC */
/* Nr of FIR/IIR-coeff banks in ANC-block */
#define AB8500_NR_OF_ANC_COEFF_BANKS 2
/* Minimum duration to keep ANC IIR Init bit high or
low before proceeding with the configuration sequence */
#define AB8500_ANC_SM_DELAY 2000
#define AB8500_FILTER_CONTROL(xname, xcount, xmin, xmax) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
.info = filter_control_info, \
.get = filter_control_get, .put = filter_control_put, \
.private_value = (unsigned long)&(struct filter_control) \
{.count = xcount, .min = xmin, .max = xmax} }
struct filter_control {
long min, max;
unsigned int count;
long value[128];
};
/* Sidetone states */
static const char * const enum_sid_state[] = {
"Unconfigured",
"Apply FIR",
"FIR is configured",
};
enum sid_state {
SID_UNCONFIGURED = 0,
SID_APPLY_FIR = 1,
SID_FIR_CONFIGURED = 2,
};
static const char * const enum_anc_state[] = {
"Unconfigured",
"Apply FIR and IIR",
"FIR and IIR are configured",
"Apply FIR",
"FIR is configured",
"Apply IIR",
"IIR is configured"
};
enum anc_state {
ANC_UNCONFIGURED = 0,
ANC_APPLY_FIR_IIR = 1,
ANC_FIR_IIR_CONFIGURED = 2,
ANC_APPLY_FIR = 3,
ANC_FIR_CONFIGURED = 4,
ANC_APPLY_IIR = 5,
ANC_IIR_CONFIGURED = 6
};
/* Analog microphones */
enum amic_idx {
AMIC_IDX_1A,
AMIC_IDX_1B,
AMIC_IDX_2
};
/* Private data for AB8500 device-driver */
struct ab8500_codec_drvdata {
struct regmap *regmap;
struct mutex ctrl_lock;
/* Sidetone */
long *sid_fir_values;
enum sid_state sid_status;
/* ANC */
long *anc_fir_values;
long *anc_iir_values;
enum anc_state anc_status;
};
static inline const char *amic_micbias_str(enum amic_micbias micbias)
{
switch (micbias) {
case AMIC_MICBIAS_VAMIC1:
return "VAMIC1";
case AMIC_MICBIAS_VAMIC2:
return "VAMIC2";
default:
return "Unknown";
}
}
static inline const char *amic_type_str(enum amic_type type)
{
switch (type) {
case AMIC_TYPE_DIFFERENTIAL:
return "DIFFERENTIAL";
case AMIC_TYPE_SINGLE_ENDED:
return "SINGLE ENDED";
default:
return "Unknown";
}
}
/*
* Read'n'write functions
*/
/* Read a register from the audio-bank of AB8500 */
static int ab8500_codec_read_reg(void *context, unsigned int reg,
unsigned int *value)
{
struct device *dev = context;
int status;
u8 value8;
status = abx500_get_register_interruptible(dev, AB8500_AUDIO,
reg, &value8);
*value = (unsigned int)value8;
return status;
}
/* Write to a register in the audio-bank of AB8500 */
static int ab8500_codec_write_reg(void *context, unsigned int reg,
unsigned int value)
{
struct device *dev = context;
return abx500_set_register_interruptible(dev, AB8500_AUDIO,
reg, value);
}
static const struct regmap_config ab8500_codec_regmap = {
.reg_read = ab8500_codec_read_reg,
.reg_write = ab8500_codec_write_reg,
};
/*
* Controls - DAPM
*/
/* Earpiece */
/* Earpiece source selector */
static const char * const enum_ear_lineout_source[] = {"Headset Left",
"Speaker Left"};
static SOC_ENUM_SINGLE_DECL(dapm_enum_ear_lineout_source, AB8500_DMICFILTCONF,
AB8500_DMICFILTCONF_DA3TOEAR, enum_ear_lineout_source);
static const struct snd_kcontrol_new dapm_ear_lineout_source =
SOC_DAPM_ENUM("Earpiece or LineOut Mono Source",
dapm_enum_ear_lineout_source);
/* LineOut */
/* LineOut source selector */
static const char * const enum_lineout_source[] = {"Mono Path", "Stereo Path"};
static SOC_ENUM_DOUBLE_DECL(dapm_enum_lineout_source, AB8500_ANACONF5,
AB8500_ANACONF5_HSLDACTOLOL,
AB8500_ANACONF5_HSRDACTOLOR, enum_lineout_source);
static const struct snd_kcontrol_new dapm_lineout_source[] = {
SOC_DAPM_ENUM("LineOut Source", dapm_enum_lineout_source),
};
/* Handsfree */
/* Speaker Left - ANC selector */
static const char * const enum_HFx_sel[] = {"Audio Path", "ANC"};
static SOC_ENUM_SINGLE_DECL(dapm_enum_HFl_sel, AB8500_DIGMULTCONF2,
AB8500_DIGMULTCONF2_HFLSEL, enum_HFx_sel);
static const struct snd_kcontrol_new dapm_HFl_select[] = {
SOC_DAPM_ENUM("Speaker Left Source", dapm_enum_HFl_sel),
};
/* Speaker Right - ANC selector */
static SOC_ENUM_SINGLE_DECL(dapm_enum_HFr_sel, AB8500_DIGMULTCONF2,
AB8500_DIGMULTCONF2_HFRSEL, enum_HFx_sel);
static const struct snd_kcontrol_new dapm_HFr_select[] = {
SOC_DAPM_ENUM("Speaker Right Source", dapm_enum_HFr_sel),
};
/* Mic 1 */
/* Mic 1 - Mic 1a or 1b selector */
static const char * const enum_mic1ab_sel[] = {"Mic 1b", "Mic 1a"};
static SOC_ENUM_SINGLE_DECL(dapm_enum_mic1ab_sel, AB8500_ANACONF3,
AB8500_ANACONF3_MIC1SEL, enum_mic1ab_sel);
static const struct snd_kcontrol_new dapm_mic1ab_mux[] = {
SOC_DAPM_ENUM("Mic 1a or 1b Select", dapm_enum_mic1ab_sel),
};
/* Mic 1 - AD3 - Mic 1 or DMic 3 selector */
static const char * const enum_ad3_sel[] = {"Mic 1", "DMic 3"};
static SOC_ENUM_SINGLE_DECL(dapm_enum_ad3_sel, AB8500_DIGMULTCONF1,
AB8500_DIGMULTCONF1_AD3SEL, enum_ad3_sel);
static const struct snd_kcontrol_new dapm_ad3_select[] = {
SOC_DAPM_ENUM("AD3 Source Select", dapm_enum_ad3_sel),
};
/* Mic 1 - AD6 - Mic 1 or DMic 6 selector */
static const char * const enum_ad6_sel[] = {"Mic 1", "DMic 6"};
static SOC_ENUM_SINGLE_DECL(dapm_enum_ad6_sel, AB8500_DIGMULTCONF1,
AB8500_DIGMULTCONF1_AD6SEL, enum_ad6_sel);
static const struct snd_kcontrol_new dapm_ad6_select[] = {
SOC_DAPM_ENUM("AD6 Source Select", dapm_enum_ad6_sel),
};
/* Mic 2 */
/* Mic 2 - AD5 - Mic 2 or DMic 5 selector */
static const char * const enum_ad5_sel[] = {"Mic 2", "DMic 5"};
static SOC_ENUM_SINGLE_DECL(dapm_enum_ad5_sel, AB8500_DIGMULTCONF1,
AB8500_DIGMULTCONF1_AD5SEL, enum_ad5_sel);
static const struct snd_kcontrol_new dapm_ad5_select[] = {
SOC_DAPM_ENUM("AD5 Source Select", dapm_enum_ad5_sel),
};
/* LineIn */
/* LineIn left - AD1 - LineIn Left or DMic 1 selector */
static const char * const enum_ad1_sel[] = {"LineIn Left", "DMic 1"};
static SOC_ENUM_SINGLE_DECL(dapm_enum_ad1_sel, AB8500_DIGMULTCONF1,
AB8500_DIGMULTCONF1_AD1SEL, enum_ad1_sel);
static const struct snd_kcontrol_new dapm_ad1_select[] = {
SOC_DAPM_ENUM("AD1 Source Select", dapm_enum_ad1_sel),
};
/* LineIn right - Mic 2 or LineIn Right selector */
static const char * const enum_mic2lr_sel[] = {"Mic 2", "LineIn Right"};
static SOC_ENUM_SINGLE_DECL(dapm_enum_mic2lr_sel, AB8500_ANACONF3,
AB8500_ANACONF3_LINRSEL, enum_mic2lr_sel);
static const struct snd_kcontrol_new dapm_mic2lr_select[] = {
SOC_DAPM_ENUM("Mic 2 or LINR Select", dapm_enum_mic2lr_sel),
};
/* LineIn right - AD2 - LineIn Right or DMic2 selector */
static const char * const enum_ad2_sel[] = {"LineIn Right", "DMic 2"};
static SOC_ENUM_SINGLE_DECL(dapm_enum_ad2_sel, AB8500_DIGMULTCONF1,
AB8500_DIGMULTCONF1_AD2SEL, enum_ad2_sel);
static const struct snd_kcontrol_new dapm_ad2_select[] = {
SOC_DAPM_ENUM("AD2 Source Select", dapm_enum_ad2_sel),
};
/* ANC */
static const char * const enum_anc_in_sel[] = {"Mic 1 / DMic 6",
"Mic 2 / DMic 5"};
static SOC_ENUM_SINGLE_DECL(dapm_enum_anc_in_sel, AB8500_DMICFILTCONF,
AB8500_DMICFILTCONF_ANCINSEL, enum_anc_in_sel);
static const struct snd_kcontrol_new dapm_anc_in_select[] = {
SOC_DAPM_ENUM("ANC Source", dapm_enum_anc_in_sel),
};
/* ANC - Enable/Disable */
static const struct snd_kcontrol_new dapm_anc_enable[] = {
SOC_DAPM_SINGLE("Switch", AB8500_ANCCONF1,
AB8500_ANCCONF1_ENANC, 0, 0),
};
/* ANC to Earpiece - Mute */
static const struct snd_kcontrol_new dapm_anc_ear_mute[] = {
SOC_DAPM_SINGLE("Switch", AB8500_DIGMULTCONF1,
AB8500_DIGMULTCONF1_ANCSEL, 1, 0),
};
/* Sidetone left */
/* Sidetone left - Input selector */
static const char * const enum_stfir1_in_sel[] = {
"LineIn Left", "LineIn Right", "Mic 1", "Headset Left"
};
static SOC_ENUM_SINGLE_DECL(dapm_enum_stfir1_in_sel, AB8500_DIGMULTCONF2,
AB8500_DIGMULTCONF2_FIRSID1SEL, enum_stfir1_in_sel);
static const struct snd_kcontrol_new dapm_stfir1_in_select[] = {
SOC_DAPM_ENUM("Sidetone Left Source", dapm_enum_stfir1_in_sel),
};
/* Sidetone right path */
/* Sidetone right - Input selector */
static const char * const enum_stfir2_in_sel[] = {
"LineIn Right", "Mic 1", "DMic 4", "Headset Right"
};
static SOC_ENUM_SINGLE_DECL(dapm_enum_stfir2_in_sel, AB8500_DIGMULTCONF2,
AB8500_DIGMULTCONF2_FIRSID2SEL, enum_stfir2_in_sel);
static const struct snd_kcontrol_new dapm_stfir2_in_select[] = {
SOC_DAPM_ENUM("Sidetone Right Source", dapm_enum_stfir2_in_sel),
};
/* Vibra */
static const char * const enum_pwm2vibx[] = {"Audio Path", "PWM Generator"};
static SOC_ENUM_SINGLE_DECL(dapm_enum_pwm2vib1, AB8500_PWMGENCONF1,
AB8500_PWMGENCONF1_PWMTOVIB1, enum_pwm2vibx);
static const struct snd_kcontrol_new dapm_pwm2vib1[] = {
SOC_DAPM_ENUM("Vibra 1 Controller", dapm_enum_pwm2vib1),
};
static SOC_ENUM_SINGLE_DECL(dapm_enum_pwm2vib2, AB8500_PWMGENCONF1,
AB8500_PWMGENCONF1_PWMTOVIB2, enum_pwm2vibx);
static const struct snd_kcontrol_new dapm_pwm2vib2[] = {
SOC_DAPM_ENUM("Vibra 2 Controller", dapm_enum_pwm2vib2),
};
/*
* DAPM-widgets
*/
static const struct snd_soc_dapm_widget ab8500_dapm_widgets[] = {
/* Clocks */
SND_SOC_DAPM_CLOCK_SUPPLY("audioclk"),
/* Regulators */
SND_SOC_DAPM_REGULATOR_SUPPLY("V-AUD", 0, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("V-AMIC1", 0, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("V-AMIC2", 0, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("V-DMIC", 0, 0),
/* Power */
SND_SOC_DAPM_SUPPLY("Audio Power",
AB8500_POWERUP, AB8500_POWERUP_POWERUP, 0,
NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("Audio Analog Power",
AB8500_POWERUP, AB8500_POWERUP_ENANA, 0,
NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
/* Main supply node */
SND_SOC_DAPM_SUPPLY("Main Supply", SND_SOC_NOPM, 0, 0,
NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
/* DA/AD */
SND_SOC_DAPM_INPUT("ADC Input"),
SND_SOC_DAPM_ADC("ADC", "ab8500_0c", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_OUTPUT("DAC Output"),
SND_SOC_DAPM_AIF_IN("DA_IN1", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("DA_IN2", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("DA_IN3", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("DA_IN4", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("DA_IN5", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("DA_IN6", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AD_OUT1", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AD_OUT2", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AD_OUT3", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AD_OUT4", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AD_OUT57", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AD_OUT68", NULL, 0, SND_SOC_NOPM, 0, 0),
/* Headset path */
SND_SOC_DAPM_SUPPLY("Charge Pump", AB8500_ANACONF5,
AB8500_ANACONF5_ENCPHS, 0, NULL, 0),
SND_SOC_DAPM_DAC("DA1 Enable", "ab8500_0p",
AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA1, 0),
SND_SOC_DAPM_DAC("DA2 Enable", "ab8500_0p",
AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA2, 0),
SND_SOC_DAPM_PGA("HSL Digital Volume", SND_SOC_NOPM, 0, 0,
NULL, 0),
SND_SOC_DAPM_PGA("HSR Digital Volume", SND_SOC_NOPM, 0, 0,
NULL, 0),
SND_SOC_DAPM_DAC("HSL DAC", "ab8500_0p",
AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHSL, 0),
SND_SOC_DAPM_DAC("HSR DAC", "ab8500_0p",
AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHSR, 0),
SND_SOC_DAPM_MIXER("HSL DAC Mute", AB8500_MUTECONF,
AB8500_MUTECONF_MUTDACHSL, 1,
NULL, 0),
SND_SOC_DAPM_MIXER("HSR DAC Mute", AB8500_MUTECONF,
AB8500_MUTECONF_MUTDACHSR, 1,
NULL, 0),
SND_SOC_DAPM_DAC("HSL DAC Driver", "ab8500_0p",
AB8500_ANACONF3, AB8500_ANACONF3_ENDRVHSL, 0),
SND_SOC_DAPM_DAC("HSR DAC Driver", "ab8500_0p",
AB8500_ANACONF3, AB8500_ANACONF3_ENDRVHSR, 0),
SND_SOC_DAPM_MIXER("HSL Mute",
AB8500_MUTECONF, AB8500_MUTECONF_MUTHSL, 1,
NULL, 0),
SND_SOC_DAPM_MIXER("HSR Mute",
AB8500_MUTECONF, AB8500_MUTECONF_MUTHSR, 1,
NULL, 0),
SND_SOC_DAPM_MIXER("HSL Enable",
AB8500_ANACONF4, AB8500_ANACONF4_ENHSL, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("HSR Enable",
AB8500_ANACONF4, AB8500_ANACONF4_ENHSR, 0,
NULL, 0),
SND_SOC_DAPM_PGA("HSL Volume",
SND_SOC_NOPM, 0, 0,
NULL, 0),
SND_SOC_DAPM_PGA("HSR Volume",
SND_SOC_NOPM, 0, 0,
NULL, 0),
SND_SOC_DAPM_OUTPUT("Headset Left"),
SND_SOC_DAPM_OUTPUT("Headset Right"),
/* LineOut path */
SND_SOC_DAPM_MUX("LineOut Source",
SND_SOC_NOPM, 0, 0, dapm_lineout_source),
SND_SOC_DAPM_MIXER("LOL Disable HFL",
AB8500_ANACONF4, AB8500_ANACONF4_ENHFL, 1,
NULL, 0),
SND_SOC_DAPM_MIXER("LOR Disable HFR",
AB8500_ANACONF4, AB8500_ANACONF4_ENHFR, 1,
NULL, 0),
SND_SOC_DAPM_MIXER("LOL Enable",
AB8500_ANACONF5, AB8500_ANACONF5_ENLOL, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("LOR Enable",
AB8500_ANACONF5, AB8500_ANACONF5_ENLOR, 0,
NULL, 0),
SND_SOC_DAPM_OUTPUT("LineOut Left"),
SND_SOC_DAPM_OUTPUT("LineOut Right"),
/* Earpiece path */
SND_SOC_DAPM_MUX("Earpiece or LineOut Mono Source",
SND_SOC_NOPM, 0, 0, &dapm_ear_lineout_source),
SND_SOC_DAPM_MIXER("EAR DAC",
AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACEAR, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("EAR Mute",
AB8500_MUTECONF, AB8500_MUTECONF_MUTEAR, 1,
NULL, 0),
SND_SOC_DAPM_MIXER("EAR Enable",
AB8500_ANACONF4, AB8500_ANACONF4_ENEAR, 0,
NULL, 0),
SND_SOC_DAPM_OUTPUT("Earpiece"),
/* Handsfree path */
SND_SOC_DAPM_MIXER("DA3 Channel Volume",
AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA3, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("DA4 Channel Volume",
AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA4, 0,
NULL, 0),
SND_SOC_DAPM_MUX("Speaker Left Source",
SND_SOC_NOPM, 0, 0, dapm_HFl_select),
SND_SOC_DAPM_MUX("Speaker Right Source",
SND_SOC_NOPM, 0, 0, dapm_HFr_select),
SND_SOC_DAPM_MIXER("HFL DAC", AB8500_DAPATHCONF,
AB8500_DAPATHCONF_ENDACHFL, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("HFR DAC",
AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHFR, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("DA4 or ANC path to HfR",
AB8500_DIGMULTCONF2, AB8500_DIGMULTCONF2_DATOHFREN, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("DA3 or ANC path to HfL",
AB8500_DIGMULTCONF2, AB8500_DIGMULTCONF2_DATOHFLEN, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("HFL Enable",
AB8500_ANACONF4, AB8500_ANACONF4_ENHFL, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("HFR Enable",
AB8500_ANACONF4, AB8500_ANACONF4_ENHFR, 0,
NULL, 0),
SND_SOC_DAPM_OUTPUT("Speaker Left"),
SND_SOC_DAPM_OUTPUT("Speaker Right"),
/* Vibrator path */
SND_SOC_DAPM_INPUT("PWMGEN1"),
SND_SOC_DAPM_INPUT("PWMGEN2"),
SND_SOC_DAPM_MIXER("DA5 Channel Volume",
AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA5, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("DA6 Channel Volume",
AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA6, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("VIB1 DAC",
AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACVIB1, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("VIB2 DAC",
AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACVIB2, 0,
NULL, 0),
SND_SOC_DAPM_MUX("Vibra 1 Controller",
SND_SOC_NOPM, 0, 0, dapm_pwm2vib1),
SND_SOC_DAPM_MUX("Vibra 2 Controller",
SND_SOC_NOPM, 0, 0, dapm_pwm2vib2),
SND_SOC_DAPM_MIXER("VIB1 Enable",
AB8500_ANACONF4, AB8500_ANACONF4_ENVIB1, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("VIB2 Enable",
AB8500_ANACONF4, AB8500_ANACONF4_ENVIB2, 0,
NULL, 0),
SND_SOC_DAPM_OUTPUT("Vibra 1"),
SND_SOC_DAPM_OUTPUT("Vibra 2"),
/* Mic 1 */
SND_SOC_DAPM_INPUT("Mic 1"),
SND_SOC_DAPM_MUX("Mic 1a or 1b Select",
SND_SOC_NOPM, 0, 0, dapm_mic1ab_mux),
SND_SOC_DAPM_MIXER("MIC1 Mute",
AB8500_ANACONF2, AB8500_ANACONF2_MUTMIC1, 1,
NULL, 0),
SND_SOC_DAPM_MIXER("MIC1A V-AMICx Enable",
AB8500_ANACONF2, AB8500_ANACONF2_ENMIC1, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("MIC1B V-AMICx Enable",
AB8500_ANACONF2, AB8500_ANACONF2_ENMIC1, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("MIC1 ADC",
AB8500_ANACONF3, AB8500_ANACONF3_ENADCMIC, 0,
NULL, 0),
SND_SOC_DAPM_MUX("AD3 Source Select",
SND_SOC_NOPM, 0, 0, dapm_ad3_select),
SND_SOC_DAPM_MIXER("AD3 Channel Volume",
SND_SOC_NOPM, 0, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("AD3 Enable",
AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD34, 0,
NULL, 0),
/* Mic 2 */
SND_SOC_DAPM_INPUT("Mic 2"),
SND_SOC_DAPM_MIXER("MIC2 Mute",
AB8500_ANACONF2, AB8500_ANACONF2_MUTMIC2, 1,
NULL, 0),
SND_SOC_DAPM_MIXER("MIC2 V-AMICx Enable", AB8500_ANACONF2,
AB8500_ANACONF2_ENMIC2, 0,
NULL, 0),
/* LineIn */
SND_SOC_DAPM_INPUT("LineIn Left"),
SND_SOC_DAPM_INPUT("LineIn Right"),
SND_SOC_DAPM_MIXER("LINL Mute",
AB8500_ANACONF2, AB8500_ANACONF2_MUTLINL, 1,
NULL, 0),
SND_SOC_DAPM_MIXER("LINR Mute",
AB8500_ANACONF2, AB8500_ANACONF2_MUTLINR, 1,
NULL, 0),
SND_SOC_DAPM_MIXER("LINL Enable", AB8500_ANACONF2,
AB8500_ANACONF2_ENLINL, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("LINR Enable", AB8500_ANACONF2,
AB8500_ANACONF2_ENLINR, 0,
NULL, 0),
/* LineIn Bypass path */
SND_SOC_DAPM_MIXER("LINL to HSL Volume",
SND_SOC_NOPM, 0, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("LINR to HSR Volume",
SND_SOC_NOPM, 0, 0,
NULL, 0),
/* LineIn, Mic 2 */
SND_SOC_DAPM_MUX("Mic 2 or LINR Select",
SND_SOC_NOPM, 0, 0, dapm_mic2lr_select),
SND_SOC_DAPM_MIXER("LINL ADC", AB8500_ANACONF3,
AB8500_ANACONF3_ENADCLINL, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("LINR ADC", AB8500_ANACONF3,
AB8500_ANACONF3_ENADCLINR, 0,
NULL, 0),
SND_SOC_DAPM_MUX("AD1 Source Select",
SND_SOC_NOPM, 0, 0, dapm_ad1_select),
SND_SOC_DAPM_MUX("AD2 Source Select",
SND_SOC_NOPM, 0, 0, dapm_ad2_select),
SND_SOC_DAPM_MIXER("AD1 Channel Volume",
SND_SOC_NOPM, 0, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("AD2 Channel Volume",
SND_SOC_NOPM, 0, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("AD12 Enable",
AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD12, 0,
NULL, 0),
/* HD Capture path */
SND_SOC_DAPM_MUX("AD5 Source Select",
SND_SOC_NOPM, 0, 0, dapm_ad5_select),
SND_SOC_DAPM_MUX("AD6 Source Select",
SND_SOC_NOPM, 0, 0, dapm_ad6_select),
SND_SOC_DAPM_MIXER("AD5 Channel Volume",
SND_SOC_NOPM, 0, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("AD6 Channel Volume",
SND_SOC_NOPM, 0, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("AD57 Enable",
AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD5768, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("AD68 Enable",
AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD5768, 0,
NULL, 0),
/* Digital Microphone path */
SND_SOC_DAPM_INPUT("DMic 1"),
SND_SOC_DAPM_INPUT("DMic 2"),
SND_SOC_DAPM_INPUT("DMic 3"),
SND_SOC_DAPM_INPUT("DMic 4"),
SND_SOC_DAPM_INPUT("DMic 5"),
SND_SOC_DAPM_INPUT("DMic 6"),
SND_SOC_DAPM_MIXER("DMIC1",
AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC1, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("DMIC2",
AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC2, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("DMIC3",
AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC3, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("DMIC4",
AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC4, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("DMIC5",
AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC5, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("DMIC6",
AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC6, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("AD4 Channel Volume",
SND_SOC_NOPM, 0, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("AD4 Enable",
AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD34,
0, NULL, 0),
/* Acoustical Noise Cancellation path */
SND_SOC_DAPM_INPUT("ANC Configure Input"),
SND_SOC_DAPM_OUTPUT("ANC Configure Output"),
SND_SOC_DAPM_MUX("ANC Source",
SND_SOC_NOPM, 0, 0,
dapm_anc_in_select),
SND_SOC_DAPM_SWITCH("ANC",
SND_SOC_NOPM, 0, 0,
dapm_anc_enable),
SND_SOC_DAPM_SWITCH("ANC to Earpiece",
SND_SOC_NOPM, 0, 0,
dapm_anc_ear_mute),
/* Sidetone Filter path */
SND_SOC_DAPM_MUX("Sidetone Left Source",
SND_SOC_NOPM, 0, 0,
dapm_stfir1_in_select),
SND_SOC_DAPM_MUX("Sidetone Right Source",
SND_SOC_NOPM, 0, 0,
dapm_stfir2_in_select),
SND_SOC_DAPM_MIXER("STFIR1 Control",
SND_SOC_NOPM, 0, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("STFIR2 Control",
SND_SOC_NOPM, 0, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("STFIR1 Volume",
SND_SOC_NOPM, 0, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("STFIR2 Volume",
SND_SOC_NOPM, 0, 0,
NULL, 0),
};
/*
* DAPM-routes
*/
static const struct snd_soc_dapm_route ab8500_dapm_routes[] = {
/* Power AB8500 audio-block when AD/DA is active */
{"Main Supply", NULL, "V-AUD"},
{"Main Supply", NULL, "audioclk"},
{"Main Supply", NULL, "Audio Power"},
{"Main Supply", NULL, "Audio Analog Power"},
{"DAC", NULL, "ab8500_0p"},
{"DAC", NULL, "Main Supply"},
{"ADC", NULL, "ab8500_0c"},
{"ADC", NULL, "Main Supply"},
/* ANC Configure */
{"ANC Configure Input", NULL, "Main Supply"},
{"ANC Configure Output", NULL, "ANC Configure Input"},
/* AD/DA */
{"ADC", NULL, "ADC Input"},
{"DAC Output", NULL, "DAC"},
/* Powerup charge pump if DA1/2 is in use */
{"DA_IN1", NULL, "ab8500_0p"},
{"DA_IN1", NULL, "Charge Pump"},
{"DA_IN2", NULL, "ab8500_0p"},
{"DA_IN2", NULL, "Charge Pump"},
/* Headset path */
{"DA1 Enable", NULL, "DA_IN1"},
{"DA2 Enable", NULL, "DA_IN2"},
{"HSL Digital Volume", NULL, "DA1 Enable"},
{"HSR Digital Volume", NULL, "DA2 Enable"},
{"HSL DAC", NULL, "HSL Digital Volume"},
{"HSR DAC", NULL, "HSR Digital Volume"},
{"HSL DAC Mute", NULL, "HSL DAC"},
{"HSR DAC Mute", NULL, "HSR DAC"},
{"HSL DAC Driver", NULL, "HSL DAC Mute"},
{"HSR DAC Driver", NULL, "HSR DAC Mute"},
{"HSL Mute", NULL, "HSL DAC Driver"},
{"HSR Mute", NULL, "HSR DAC Driver"},
{"HSL Enable", NULL, "HSL Mute"},
{"HSR Enable", NULL, "HSR Mute"},
{"HSL Volume", NULL, "HSL Enable"},
{"HSR Volume", NULL, "HSR Enable"},
{"Headset Left", NULL, "HSL Volume"},
{"Headset Right", NULL, "HSR Volume"},
/* HF or LineOut path */
{"DA_IN3", NULL, "ab8500_0p"},
{"DA3 Channel Volume", NULL, "DA_IN3"},
{"DA_IN4", NULL, "ab8500_0p"},
{"DA4 Channel Volume", NULL, "DA_IN4"},
{"Speaker Left Source", "Audio Path", "DA3 Channel Volume"},
{"Speaker Right Source", "Audio Path", "DA4 Channel Volume"},
{"DA3 or ANC path to HfL", NULL, "Speaker Left Source"},
{"DA4 or ANC path to HfR", NULL, "Speaker Right Source"},
/* HF path */
{"HFL DAC", NULL, "DA3 or ANC path to HfL"},
{"HFR DAC", NULL, "DA4 or ANC path to HfR"},
{"HFL Enable", NULL, "HFL DAC"},
{"HFR Enable", NULL, "HFR DAC"},
{"Speaker Left", NULL, "HFL Enable"},
{"Speaker Right", NULL, "HFR Enable"},
/* Earpiece path */
{"Earpiece or LineOut Mono Source", "Headset Left",
"HSL Digital Volume"},
{"Earpiece or LineOut Mono Source", "Speaker Left",
"DA3 or ANC path to HfL"},
{"EAR DAC", NULL, "Earpiece or LineOut Mono Source"},
{"EAR Mute", NULL, "EAR DAC"},
{"EAR Enable", NULL, "EAR Mute"},
{"Earpiece", NULL, "EAR Enable"},
/* LineOut path stereo */
{"LineOut Source", "Stereo Path", "HSL DAC Driver"},
{"LineOut Source", "Stereo Path", "HSR DAC Driver"},
/* LineOut path mono */
{"LineOut Source", "Mono Path", "EAR DAC"},
/* LineOut path */
{"LOL Disable HFL", NULL, "LineOut Source"},
{"LOR Disable HFR", NULL, "LineOut Source"},
{"LOL Enable", NULL, "LOL Disable HFL"},
{"LOR Enable", NULL, "LOR Disable HFR"},
{"LineOut Left", NULL, "LOL Enable"},
{"LineOut Right", NULL, "LOR Enable"},
/* Vibrator path */
{"DA_IN5", NULL, "ab8500_0p"},
{"DA5 Channel Volume", NULL, "DA_IN5"},
{"DA_IN6", NULL, "ab8500_0p"},
{"DA6 Channel Volume", NULL, "DA_IN6"},
{"VIB1 DAC", NULL, "DA5 Channel Volume"},
{"VIB2 DAC", NULL, "DA6 Channel Volume"},
{"Vibra 1 Controller", "Audio Path", "VIB1 DAC"},
{"Vibra 2 Controller", "Audio Path", "VIB2 DAC"},
{"Vibra 1 Controller", "PWM Generator", "PWMGEN1"},
{"Vibra 2 Controller", "PWM Generator", "PWMGEN2"},
{"VIB1 Enable", NULL, "Vibra 1 Controller"},
{"VIB2 Enable", NULL, "Vibra 2 Controller"},
{"Vibra 1", NULL, "VIB1 Enable"},
{"Vibra 2", NULL, "VIB2 Enable"},
/* Mic 2 */
{"MIC2 V-AMICx Enable", NULL, "Mic 2"},
/* LineIn */
{"LINL Mute", NULL, "LineIn Left"},
{"LINR Mute", NULL, "LineIn Right"},
{"LINL Enable", NULL, "LINL Mute"},
{"LINR Enable", NULL, "LINR Mute"},
/* LineIn, Mic 2 */
{"Mic 2 or LINR Select", "LineIn Right", "LINR Enable"},
{"Mic 2 or LINR Select", "Mic 2", "MIC2 V-AMICx Enable"},
{"LINL ADC", NULL, "LINL Enable"},
{"LINR ADC", NULL, "Mic 2 or LINR Select"},
{"AD1 Source Select", "LineIn Left", "LINL ADC"},
{"AD2 Source Select", "LineIn Right", "LINR ADC"},
{"AD1 Channel Volume", NULL, "AD1 Source Select"},
{"AD2 Channel Volume", NULL, "AD2 Source Select"},
{"AD12 Enable", NULL, "AD1 Channel Volume"},
{"AD12 Enable", NULL, "AD2 Channel Volume"},
{"AD_OUT1", NULL, "ab8500_0c"},
{"AD_OUT1", NULL, "AD12 Enable"},
{"AD_OUT2", NULL, "ab8500_0c"},
{"AD_OUT2", NULL, "AD12 Enable"},
/* Mic 1 */
{"MIC1 Mute", NULL, "Mic 1"},
{"MIC1A V-AMICx Enable", NULL, "MIC1 Mute"},
{"MIC1B V-AMICx Enable", NULL, "MIC1 Mute"},
{"Mic 1a or 1b Select", "Mic 1a", "MIC1A V-AMICx Enable"},
{"Mic 1a or 1b Select", "Mic 1b", "MIC1B V-AMICx Enable"},
{"MIC1 ADC", NULL, "Mic 1a or 1b Select"},
{"AD3 Source Select", "Mic 1", "MIC1 ADC"},
{"AD3 Channel Volume", NULL, "AD3 Source Select"},
{"AD3 Enable", NULL, "AD3 Channel Volume"},
{"AD_OUT3", NULL, "ab8500_0c"},
{"AD_OUT3", NULL, "AD3 Enable"},
/* HD Capture path */
{"AD5 Source Select", "Mic 2", "LINR ADC"},
{"AD6 Source Select", "Mic 1", "MIC1 ADC"},
{"AD5 Channel Volume", NULL, "AD5 Source Select"},
{"AD6 Channel Volume", NULL, "AD6 Source Select"},
{"AD57 Enable", NULL, "AD5 Channel Volume"},
{"AD68 Enable", NULL, "AD6 Channel Volume"},
{"AD_OUT57", NULL, "ab8500_0c"},
{"AD_OUT57", NULL, "AD57 Enable"},
{"AD_OUT68", NULL, "ab8500_0c"},
{"AD_OUT68", NULL, "AD68 Enable"},
/* Digital Microphone path */
{"DMic 1", NULL, "V-DMIC"},
{"DMic 2", NULL, "V-DMIC"},
{"DMic 3", NULL, "V-DMIC"},
{"DMic 4", NULL, "V-DMIC"},
{"DMic 5", NULL, "V-DMIC"},
{"DMic 6", NULL, "V-DMIC"},
{"AD1 Source Select", NULL, "DMic 1"},
{"AD2 Source Select", NULL, "DMic 2"},
{"AD3 Source Select", NULL, "DMic 3"},
{"AD5 Source Select", NULL, "DMic 5"},
{"AD6 Source Select", NULL, "DMic 6"},
{"AD4 Channel Volume", NULL, "DMic 4"},
{"AD4 Enable", NULL, "AD4 Channel Volume"},
{"AD_OUT4", NULL, "ab8500_0c"},
{"AD_OUT4", NULL, "AD4 Enable"},
/* LineIn Bypass path */
{"LINL to HSL Volume", NULL, "LINL Enable"},
{"LINR to HSR Volume", NULL, "LINR Enable"},
{"HSL DAC Driver", NULL, "LINL to HSL Volume"},
{"HSR DAC Driver", NULL, "LINR to HSR Volume"},
/* ANC path (Acoustic Noise Cancellation) */
{"ANC Source", "Mic 2 / DMic 5", "AD5 Channel Volume"},
{"ANC Source", "Mic 1 / DMic 6", "AD6 Channel Volume"},
{"ANC", "Switch", "ANC Source"},
{"Speaker Left Source", "ANC", "ANC"},
{"Speaker Right Source", "ANC", "ANC"},
{"ANC to Earpiece", "Switch", "ANC"},
{"HSL Digital Volume", NULL, "ANC to Earpiece"},
/* Sidetone Filter path */
{"Sidetone Left Source", "LineIn Left", "AD12 Enable"},
{"Sidetone Left Source", "LineIn Right", "AD12 Enable"},
{"Sidetone Left Source", "Mic 1", "AD3 Enable"},
{"Sidetone Left Source", "Headset Left", "DA_IN1"},
{"Sidetone Right Source", "LineIn Right", "AD12 Enable"},
{"Sidetone Right Source", "Mic 1", "AD3 Enable"},
{"Sidetone Right Source", "DMic 4", "AD4 Enable"},
{"Sidetone Right Source", "Headset Right", "DA_IN2"},
{"STFIR1 Control", NULL, "Sidetone Left Source"},
{"STFIR2 Control", NULL, "Sidetone Right Source"},
{"STFIR1 Volume", NULL, "STFIR1 Control"},
{"STFIR2 Volume", NULL, "STFIR2 Control"},
{"DA1 Enable", NULL, "STFIR1 Volume"},
{"DA2 Enable", NULL, "STFIR2 Volume"},
};
static const struct snd_soc_dapm_route ab8500_dapm_routes_mic1a_vamicx[] = {
{"MIC1A V-AMICx Enable", NULL, "V-AMIC1"},
{"MIC1A V-AMICx Enable", NULL, "V-AMIC2"},
};
static const struct snd_soc_dapm_route ab8500_dapm_routes_mic1b_vamicx[] = {
{"MIC1B V-AMICx Enable", NULL, "V-AMIC1"},
{"MIC1B V-AMICx Enable", NULL, "V-AMIC2"},
};
static const struct snd_soc_dapm_route ab8500_dapm_routes_mic2_vamicx[] = {
{"MIC2 V-AMICx Enable", NULL, "V-AMIC1"},
{"MIC2 V-AMICx Enable", NULL, "V-AMIC2"},
};
/* ANC FIR-coefficients configuration sequence */
static void anc_fir(struct snd_soc_component *component,
unsigned int bnk, unsigned int par, unsigned int val)
{
if (par == 0 && bnk == 0)
snd_soc_component_update_bits(component, AB8500_ANCCONF1,
BIT(AB8500_ANCCONF1_ANCFIRUPDATE),
BIT(AB8500_ANCCONF1_ANCFIRUPDATE));
snd_soc_component_write(component, AB8500_ANCCONF5, val >> 8 & 0xff);
snd_soc_component_write(component, AB8500_ANCCONF6, val & 0xff);
if (par == AB8500_ANC_FIR_COEFFS - 1 && bnk == 1)
snd_soc_component_update_bits(component, AB8500_ANCCONF1,
BIT(AB8500_ANCCONF1_ANCFIRUPDATE), 0);
}
/* ANC IIR-coefficients configuration sequence */
static void anc_iir(struct snd_soc_component *component, unsigned int bnk,
unsigned int par, unsigned int val)
{
if (par == 0) {
if (bnk == 0) {
snd_soc_component_update_bits(component, AB8500_ANCCONF1,
BIT(AB8500_ANCCONF1_ANCIIRINIT),
BIT(AB8500_ANCCONF1_ANCIIRINIT));
usleep_range(AB8500_ANC_SM_DELAY, AB8500_ANC_SM_DELAY*2);
snd_soc_component_update_bits(component, AB8500_ANCCONF1,
BIT(AB8500_ANCCONF1_ANCIIRINIT), 0);
usleep_range(AB8500_ANC_SM_DELAY, AB8500_ANC_SM_DELAY*2);
} else {
snd_soc_component_update_bits(component, AB8500_ANCCONF1,
BIT(AB8500_ANCCONF1_ANCIIRUPDATE),
BIT(AB8500_ANCCONF1_ANCIIRUPDATE));
}
} else if (par > 3) {
snd_soc_component_write(component, AB8500_ANCCONF7, 0);
snd_soc_component_write(component, AB8500_ANCCONF8, val >> 16 & 0xff);
}
snd_soc_component_write(component, AB8500_ANCCONF7, val >> 8 & 0xff);
snd_soc_component_write(component, AB8500_ANCCONF8, val & 0xff);
if (par == AB8500_ANC_IIR_COEFFS - 1 && bnk == 1)
snd_soc_component_update_bits(component, AB8500_ANCCONF1,
BIT(AB8500_ANCCONF1_ANCIIRUPDATE), 0);
}
/* ANC IIR-/FIR-coefficients configuration sequence */
static void anc_configure(struct snd_soc_component *component,
bool apply_fir, bool apply_iir)
{
struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(component->dev);
unsigned int bnk, par, val;
dev_dbg(component->dev, "%s: Enter.\n", __func__);
if (apply_fir)
snd_soc_component_update_bits(component, AB8500_ANCCONF1,
BIT(AB8500_ANCCONF1_ENANC), 0);
snd_soc_component_update_bits(component, AB8500_ANCCONF1,
BIT(AB8500_ANCCONF1_ENANC), BIT(AB8500_ANCCONF1_ENANC));
if (apply_fir)
for (bnk = 0; bnk < AB8500_NR_OF_ANC_COEFF_BANKS; bnk++)
for (par = 0; par < AB8500_ANC_FIR_COEFFS; par++) {
val = snd_soc_component_read(component,
drvdata->anc_fir_values[par]);
anc_fir(component, bnk, par, val);
}
if (apply_iir)
for (bnk = 0; bnk < AB8500_NR_OF_ANC_COEFF_BANKS; bnk++)
for (par = 0; par < AB8500_ANC_IIR_COEFFS; par++) {
val = snd_soc_component_read(component,
drvdata->anc_iir_values[par]);
anc_iir(component, bnk, par, val);
}
dev_dbg(component->dev, "%s: Exit.\n", __func__);
}
/*
* Control-events
*/
static int sid_status_control_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(component->dev);
mutex_lock(&drvdata->ctrl_lock);
ucontrol->value.enumerated.item[0] = drvdata->sid_status;
mutex_unlock(&drvdata->ctrl_lock);
return 0;
}
/* Write sidetone FIR-coefficients configuration sequence */
static int sid_status_control_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(component->dev);
unsigned int param, sidconf, val;
int status = 1;
dev_dbg(component->dev, "%s: Enter\n", __func__);
if (ucontrol->value.enumerated.item[0] != SID_APPLY_FIR) {
dev_err(component->dev,
"%s: ERROR: This control supports '%s' only!\n",
__func__, enum_sid_state[SID_APPLY_FIR]);
return -EIO;
}
mutex_lock(&drvdata->ctrl_lock);
sidconf = snd_soc_component_read(component, AB8500_SIDFIRCONF);
if (((sidconf & BIT(AB8500_SIDFIRCONF_FIRSIDBUSY)) != 0)) {
if ((sidconf & BIT(AB8500_SIDFIRCONF_ENFIRSIDS)) == 0) {
dev_err(component->dev, "%s: Sidetone busy while off!\n",
__func__);
status = -EPERM;
} else {
status = -EBUSY;
}
goto out;
}
snd_soc_component_write(component, AB8500_SIDFIRADR, 0);
for (param = 0; param < AB8500_SID_FIR_COEFFS; param++) {
val = snd_soc_component_read(component, drvdata->sid_fir_values[param]);
snd_soc_component_write(component, AB8500_SIDFIRCOEF1, val >> 8 & 0xff);
snd_soc_component_write(component, AB8500_SIDFIRCOEF2, val & 0xff);
}
snd_soc_component_update_bits(component, AB8500_SIDFIRADR,
BIT(AB8500_SIDFIRADR_FIRSIDSET),
BIT(AB8500_SIDFIRADR_FIRSIDSET));
snd_soc_component_update_bits(component, AB8500_SIDFIRADR,
BIT(AB8500_SIDFIRADR_FIRSIDSET), 0);
drvdata->sid_status = SID_FIR_CONFIGURED;
out:
mutex_unlock(&drvdata->ctrl_lock);
dev_dbg(component->dev, "%s: Exit\n", __func__);
return status;
}
static int anc_status_control_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(component->dev);
mutex_lock(&drvdata->ctrl_lock);
ucontrol->value.enumerated.item[0] = drvdata->anc_status;
mutex_unlock(&drvdata->ctrl_lock);
return 0;
}
static int anc_status_control_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(component->dev);
struct device *dev = component->dev;
bool apply_fir, apply_iir;
unsigned int req;
int status;
dev_dbg(dev, "%s: Enter.\n", __func__);
mutex_lock(&drvdata->ctrl_lock);
req = ucontrol->value.enumerated.item[0];
if (req >= ARRAY_SIZE(enum_anc_state)) {
status = -EINVAL;
goto cleanup;
}
if (req != ANC_APPLY_FIR_IIR && req != ANC_APPLY_FIR &&
req != ANC_APPLY_IIR) {
dev_err(dev, "%s: ERROR: Unsupported status to set '%s'!\n",
__func__, enum_anc_state[req]);
status = -EINVAL;
goto cleanup;
}
apply_fir = req == ANC_APPLY_FIR || req == ANC_APPLY_FIR_IIR;
apply_iir = req == ANC_APPLY_IIR || req == ANC_APPLY_FIR_IIR;
status = snd_soc_dapm_force_enable_pin(dapm, "ANC Configure Input");
if (status < 0) {
dev_err(dev,
"%s: ERROR: Failed to enable power (status = %d)!\n",
__func__, status);
goto cleanup;
}
snd_soc_dapm_sync(dapm);
anc_configure(component, apply_fir, apply_iir);
if (apply_fir) {
if (drvdata->anc_status == ANC_IIR_CONFIGURED)
drvdata->anc_status = ANC_FIR_IIR_CONFIGURED;
else if (drvdata->anc_status != ANC_FIR_IIR_CONFIGURED)
drvdata->anc_status = ANC_FIR_CONFIGURED;
}
if (apply_iir) {
if (drvdata->anc_status == ANC_FIR_CONFIGURED)
drvdata->anc_status = ANC_FIR_IIR_CONFIGURED;
else if (drvdata->anc_status != ANC_FIR_IIR_CONFIGURED)
drvdata->anc_status = ANC_IIR_CONFIGURED;
}
status = snd_soc_dapm_disable_pin(dapm, "ANC Configure Input");
snd_soc_dapm_sync(dapm);
cleanup:
mutex_unlock(&drvdata->ctrl_lock);
if (status < 0)
dev_err(dev, "%s: Unable to configure ANC! (status = %d)\n",
__func__, status);
dev_dbg(dev, "%s: Exit.\n", __func__);
return (status < 0) ? status : 1;
}
static int filter_control_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
struct filter_control *fc =
(struct filter_control *)kcontrol->private_value;
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = fc->count;
uinfo->value.integer.min = fc->min;
uinfo->value.integer.max = fc->max;
return 0;
}
static int filter_control_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct ab8500_codec_drvdata *drvdata = snd_soc_component_get_drvdata(component);
struct filter_control *fc =
(struct filter_control *)kcontrol->private_value;
unsigned int i;
mutex_lock(&drvdata->ctrl_lock);
for (i = 0; i < fc->count; i++)
ucontrol->value.integer.value[i] = fc->value[i];
mutex_unlock(&drvdata->ctrl_lock);
return 0;
}
static int filter_control_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct ab8500_codec_drvdata *drvdata = snd_soc_component_get_drvdata(component);
struct filter_control *fc =
(struct filter_control *)kcontrol->private_value;
unsigned int i;
mutex_lock(&drvdata->ctrl_lock);
for (i = 0; i < fc->count; i++)
fc->value[i] = ucontrol->value.integer.value[i];
mutex_unlock(&drvdata->ctrl_lock);
return 0;
}
/*
* Controls - Non-DAPM ASoC
*/
static DECLARE_TLV_DB_SCALE(adx_dig_gain_tlv, -3200, 100, 1);
/* -32dB = Mute */
static DECLARE_TLV_DB_SCALE(dax_dig_gain_tlv, -6300, 100, 1);
/* -63dB = Mute */
static DECLARE_TLV_DB_SCALE(hs_ear_dig_gain_tlv, -100, 100, 1);
/* -1dB = Mute */
static const DECLARE_TLV_DB_RANGE(hs_gain_tlv,
0, 3, TLV_DB_SCALE_ITEM(-3200, 400, 0),
4, 15, TLV_DB_SCALE_ITEM(-1800, 200, 0)
);
static DECLARE_TLV_DB_SCALE(mic_gain_tlv, 0, 100, 0);
static DECLARE_TLV_DB_SCALE(lin_gain_tlv, -1000, 200, 0);
static DECLARE_TLV_DB_SCALE(lin2hs_gain_tlv, -3800, 200, 1);
/* -38dB = Mute */
static const char * const enum_hsfadspeed[] = {"2ms", "0.5ms", "10.6ms",
"5ms"};
static SOC_ENUM_SINGLE_DECL(soc_enum_hsfadspeed,
AB8500_DIGMICCONF, AB8500_DIGMICCONF_HSFADSPEED, enum_hsfadspeed);
static const char * const enum_envdetthre[] = {
"250mV", "300mV", "350mV", "400mV",
"450mV", "500mV", "550mV", "600mV",
"650mV", "700mV", "750mV", "800mV",
"850mV", "900mV", "950mV", "1.00V" };
static SOC_ENUM_SINGLE_DECL(soc_enum_envdeththre,
AB8500_ENVCPCONF, AB8500_ENVCPCONF_ENVDETHTHRE, enum_envdetthre);
static SOC_ENUM_SINGLE_DECL(soc_enum_envdetlthre,
AB8500_ENVCPCONF, AB8500_ENVCPCONF_ENVDETLTHRE, enum_envdetthre);
static const char * const enum_envdettime[] = {
"26.6us", "53.2us", "106us", "213us",
"426us", "851us", "1.70ms", "3.40ms",
"6.81ms", "13.6ms", "27.2ms", "54.5ms",
"109ms", "218ms", "436ms", "872ms" };
static SOC_ENUM_SINGLE_DECL(soc_enum_envdettime,
AB8500_SIGENVCONF, AB8500_SIGENVCONF_ENVDETTIME, enum_envdettime);
static const char * const enum_sinc31[] = {"Sinc 3", "Sinc 1"};
static SOC_ENUM_SINGLE_DECL(soc_enum_hsesinc, AB8500_HSLEARDIGGAIN,
AB8500_HSLEARDIGGAIN_HSSINC1, enum_sinc31);
static const char * const enum_fadespeed[] = {"1ms", "4ms", "8ms", "16ms"};
static SOC_ENUM_SINGLE_DECL(soc_enum_fadespeed, AB8500_HSRDIGGAIN,
AB8500_HSRDIGGAIN_FADESPEED, enum_fadespeed);
/* Earpiece */
static const char * const enum_lowpow[] = {"Normal", "Low Power"};
static SOC_ENUM_SINGLE_DECL(soc_enum_eardaclowpow, AB8500_ANACONF1,
AB8500_ANACONF1_EARDACLOWPOW, enum_lowpow);
static SOC_ENUM_SINGLE_DECL(soc_enum_eardrvlowpow, AB8500_ANACONF1,
AB8500_ANACONF1_EARDRVLOWPOW, enum_lowpow);
static const char * const enum_av_mode[] = {"Audio", "Voice"};
static SOC_ENUM_DOUBLE_DECL(soc_enum_ad12voice, AB8500_ADFILTCONF,
AB8500_ADFILTCONF_AD1VOICE, AB8500_ADFILTCONF_AD2VOICE, enum_av_mode);
static SOC_ENUM_DOUBLE_DECL(soc_enum_ad34voice, AB8500_ADFILTCONF,
AB8500_ADFILTCONF_AD3VOICE, AB8500_ADFILTCONF_AD4VOICE, enum_av_mode);
/* DA */
static SOC_ENUM_SINGLE_DECL(soc_enum_da12voice,
AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_DA12VOICE,
enum_av_mode);
static SOC_ENUM_SINGLE_DECL(soc_enum_da34voice,
AB8500_DASLOTCONF3, AB8500_DASLOTCONF3_DA34VOICE,
enum_av_mode);
static SOC_ENUM_SINGLE_DECL(soc_enum_da56voice,
AB8500_DASLOTCONF5, AB8500_DASLOTCONF5_DA56VOICE,
enum_av_mode);
static const char * const enum_da2hslr[] = {"Sidetone", "Audio Path"};
static SOC_ENUM_DOUBLE_DECL(soc_enum_da2hslr, AB8500_DIGMULTCONF1,
AB8500_DIGMULTCONF1_DATOHSLEN,
AB8500_DIGMULTCONF1_DATOHSREN, enum_da2hslr);
static const char * const enum_sinc53[] = {"Sinc 5", "Sinc 3"};
static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic12sinc, AB8500_DMICFILTCONF,
AB8500_DMICFILTCONF_DMIC1SINC3,
AB8500_DMICFILTCONF_DMIC2SINC3, enum_sinc53);
static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic34sinc, AB8500_DMICFILTCONF,
AB8500_DMICFILTCONF_DMIC3SINC3,
AB8500_DMICFILTCONF_DMIC4SINC3, enum_sinc53);
static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic56sinc, AB8500_DMICFILTCONF,
AB8500_DMICFILTCONF_DMIC5SINC3,
AB8500_DMICFILTCONF_DMIC6SINC3, enum_sinc53);
/* Digital interface - DA from slot mapping */
static const char * const enum_da_from_slot_map[] = {"SLOT0",
"SLOT1",
"SLOT2",
"SLOT3",
"SLOT4",
"SLOT5",
"SLOT6",
"SLOT7",
"SLOT8",
"SLOT9",
"SLOT10",
"SLOT11",
"SLOT12",
"SLOT13",
"SLOT14",
"SLOT15",
"SLOT16",
"SLOT17",
"SLOT18",
"SLOT19",
"SLOT20",
"SLOT21",
"SLOT22",
"SLOT23",
"SLOT24",
"SLOT25",
"SLOT26",
"SLOT27",
"SLOT28",
"SLOT29",
"SLOT30",
"SLOT31"};
static SOC_ENUM_SINGLE_DECL(soc_enum_da1slotmap,
AB8500_DASLOTCONF1, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
enum_da_from_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_da2slotmap,
AB8500_DASLOTCONF2, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
enum_da_from_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_da3slotmap,
AB8500_DASLOTCONF3, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
enum_da_from_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_da4slotmap,
AB8500_DASLOTCONF4, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
enum_da_from_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_da5slotmap,
AB8500_DASLOTCONF5, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
enum_da_from_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_da6slotmap,
AB8500_DASLOTCONF6, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
enum_da_from_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_da7slotmap,
AB8500_DASLOTCONF7, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
enum_da_from_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_da8slotmap,
AB8500_DASLOTCONF8, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
enum_da_from_slot_map);
/* Digital interface - AD to slot mapping */
static const char * const enum_ad_to_slot_map[] = {"AD_OUT1",
"AD_OUT2",
"AD_OUT3",
"AD_OUT4",
"AD_OUT5",
"AD_OUT6",
"AD_OUT7",
"AD_OUT8",
"zeroes",
"zeroes",
"zeroes",
"zeroes",
"tristate",
"tristate",
"tristate",
"tristate"};
static SOC_ENUM_SINGLE_DECL(soc_enum_adslot0map,
AB8500_ADSLOTSEL1, AB8500_ADSLOTSELX_EVEN_SHIFT,
enum_ad_to_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_adslot1map,
AB8500_ADSLOTSEL1, AB8500_ADSLOTSELX_ODD_SHIFT,
enum_ad_to_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_adslot2map,
AB8500_ADSLOTSEL2, AB8500_ADSLOTSELX_EVEN_SHIFT,
enum_ad_to_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_adslot3map,
AB8500_ADSLOTSEL2, AB8500_ADSLOTSELX_ODD_SHIFT,
enum_ad_to_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_adslot4map,
AB8500_ADSLOTSEL3, AB8500_ADSLOTSELX_EVEN_SHIFT,
enum_ad_to_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_adslot5map,
AB8500_ADSLOTSEL3, AB8500_ADSLOTSELX_ODD_SHIFT,
enum_ad_to_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_adslot6map,
AB8500_ADSLOTSEL4, AB8500_ADSLOTSELX_EVEN_SHIFT,
enum_ad_to_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_adslot7map,
AB8500_ADSLOTSEL4, AB8500_ADSLOTSELX_ODD_SHIFT,
enum_ad_to_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_adslot8map,
AB8500_ADSLOTSEL5, AB8500_ADSLOTSELX_EVEN_SHIFT,
enum_ad_to_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_adslot9map,
AB8500_ADSLOTSEL5, AB8500_ADSLOTSELX_ODD_SHIFT,
enum_ad_to_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_adslot10map,
AB8500_ADSLOTSEL6, AB8500_ADSLOTSELX_EVEN_SHIFT,
enum_ad_to_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_adslot11map,
AB8500_ADSLOTSEL6, AB8500_ADSLOTSELX_ODD_SHIFT,
enum_ad_to_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_adslot12map,
AB8500_ADSLOTSEL7, AB8500_ADSLOTSELX_EVEN_SHIFT,
enum_ad_to_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_adslot13map,
AB8500_ADSLOTSEL7, AB8500_ADSLOTSELX_ODD_SHIFT,
enum_ad_to_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_adslot14map,
AB8500_ADSLOTSEL8, AB8500_ADSLOTSELX_EVEN_SHIFT,
enum_ad_to_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_adslot15map,
AB8500_ADSLOTSEL8, AB8500_ADSLOTSELX_ODD_SHIFT,
enum_ad_to_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_adslot16map,
AB8500_ADSLOTSEL9, AB8500_ADSLOTSELX_EVEN_SHIFT,
enum_ad_to_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_adslot17map,
AB8500_ADSLOTSEL9, AB8500_ADSLOTSELX_ODD_SHIFT,
enum_ad_to_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_adslot18map,
AB8500_ADSLOTSEL10, AB8500_ADSLOTSELX_EVEN_SHIFT,
enum_ad_to_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_adslot19map,
AB8500_ADSLOTSEL10, AB8500_ADSLOTSELX_ODD_SHIFT,
enum_ad_to_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_adslot20map,
AB8500_ADSLOTSEL11, AB8500_ADSLOTSELX_EVEN_SHIFT,
enum_ad_to_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_adslot21map,
AB8500_ADSLOTSEL11, AB8500_ADSLOTSELX_ODD_SHIFT,
enum_ad_to_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_adslot22map,
AB8500_ADSLOTSEL12, AB8500_ADSLOTSELX_EVEN_SHIFT,
enum_ad_to_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_adslot23map,
AB8500_ADSLOTSEL12, AB8500_ADSLOTSELX_ODD_SHIFT,
enum_ad_to_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_adslot24map,
AB8500_ADSLOTSEL13, AB8500_ADSLOTSELX_EVEN_SHIFT,
enum_ad_to_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_adslot25map,
AB8500_ADSLOTSEL13, AB8500_ADSLOTSELX_ODD_SHIFT,
enum_ad_to_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_adslot26map,
AB8500_ADSLOTSEL14, AB8500_ADSLOTSELX_EVEN_SHIFT,
enum_ad_to_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_adslot27map,
AB8500_ADSLOTSEL14, AB8500_ADSLOTSELX_ODD_SHIFT,
enum_ad_to_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_adslot28map,
AB8500_ADSLOTSEL15, AB8500_ADSLOTSELX_EVEN_SHIFT,
enum_ad_to_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_adslot29map,
AB8500_ADSLOTSEL15, AB8500_ADSLOTSELX_ODD_SHIFT,
enum_ad_to_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_adslot30map,
AB8500_ADSLOTSEL16, AB8500_ADSLOTSELX_EVEN_SHIFT,
enum_ad_to_slot_map);
static SOC_ENUM_SINGLE_DECL(soc_enum_adslot31map,
AB8500_ADSLOTSEL16, AB8500_ADSLOTSELX_ODD_SHIFT,
enum_ad_to_slot_map);
/* Digital interface - Burst mode */
static const char * const enum_mask[] = {"Unmasked", "Masked"};
static SOC_ENUM_SINGLE_DECL(soc_enum_bfifomask,
AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFOMASK,
enum_mask);
static const char * const enum_bitclk0[] = {"19_2_MHz", "38_4_MHz"};
static SOC_ENUM_SINGLE_DECL(soc_enum_bfifo19m2,
AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFO19M2,
enum_bitclk0);
static const char * const enum_slavemaster[] = {"Slave", "Master"};
static SOC_ENUM_SINGLE_DECL(soc_enum_bfifomast,
AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFOMAST_SHIFT,
enum_slavemaster);
/* Sidetone */
static SOC_ENUM_SINGLE_EXT_DECL(soc_enum_sidstate, enum_sid_state);
/* ANC */
static SOC_ENUM_SINGLE_EXT_DECL(soc_enum_ancstate, enum_anc_state);
static struct snd_kcontrol_new ab8500_ctrls[] = {
/* Charge pump */
SOC_ENUM("Charge Pump High Threshold For Low Voltage",
soc_enum_envdeththre),
SOC_ENUM("Charge Pump Low Threshold For Low Voltage",
soc_enum_envdetlthre),
SOC_SINGLE("Charge Pump Envelope Detection Switch",
AB8500_SIGENVCONF, AB8500_SIGENVCONF_ENVDETCPEN,
1, 0),
SOC_ENUM("Charge Pump Envelope Detection Decay Time",
soc_enum_envdettime),
/* Headset */
SOC_ENUM("Headset Mode", soc_enum_da12voice),
SOC_SINGLE("Headset High Pass Switch",
AB8500_ANACONF1, AB8500_ANACONF1_HSHPEN,
1, 0),
SOC_SINGLE("Headset Low Power Switch",
AB8500_ANACONF1, AB8500_ANACONF1_HSLOWPOW,
1, 0),
SOC_SINGLE("Headset DAC Low Power Switch",
AB8500_ANACONF1, AB8500_ANACONF1_DACLOWPOW1,
1, 0),
SOC_SINGLE("Headset DAC Drv Low Power Switch",
AB8500_ANACONF1, AB8500_ANACONF1_DACLOWPOW0,
1, 0),
SOC_ENUM("Headset Fade Speed", soc_enum_hsfadspeed),
SOC_ENUM("Headset Source", soc_enum_da2hslr),
SOC_ENUM("Headset Filter", soc_enum_hsesinc),
SOC_DOUBLE_R_TLV("Headset Master Volume",
AB8500_DADIGGAIN1, AB8500_DADIGGAIN2,
0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv),
SOC_DOUBLE_R_TLV("Headset Digital Volume",
AB8500_HSLEARDIGGAIN, AB8500_HSRDIGGAIN,
0, AB8500_HSLEARDIGGAIN_HSLDGAIN_MAX, 1, hs_ear_dig_gain_tlv),
SOC_DOUBLE_TLV("Headset Volume",
AB8500_ANAGAIN3,
AB8500_ANAGAIN3_HSLGAIN, AB8500_ANAGAIN3_HSRGAIN,
AB8500_ANAGAIN3_HSXGAIN_MAX, 1, hs_gain_tlv),
/* Earpiece */
SOC_ENUM("Earpiece DAC Mode",
soc_enum_eardaclowpow),
SOC_ENUM("Earpiece DAC Drv Mode",
soc_enum_eardrvlowpow),
/* HandsFree */
SOC_ENUM("HF Mode", soc_enum_da34voice),
SOC_SINGLE("HF and Headset Swap Switch",
AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_SWAPDA12_34,
1, 0),
SOC_DOUBLE("HF Low EMI Mode Switch",
AB8500_CLASSDCONF1,
AB8500_CLASSDCONF1_HFLSWAPEN, AB8500_CLASSDCONF1_HFRSWAPEN,
1, 0),
SOC_DOUBLE("HF FIR Bypass Switch",
AB8500_CLASSDCONF2,
AB8500_CLASSDCONF2_FIRBYP0, AB8500_CLASSDCONF2_FIRBYP1,
1, 0),
SOC_DOUBLE("HF High Volume Switch",
AB8500_CLASSDCONF2,
AB8500_CLASSDCONF2_HIGHVOLEN0, AB8500_CLASSDCONF2_HIGHVOLEN1,
1, 0),
SOC_SINGLE("HF L and R Bridge Switch",
AB8500_CLASSDCONF1, AB8500_CLASSDCONF1_PARLHF,
1, 0),
SOC_DOUBLE_R_TLV("HF Master Volume",
AB8500_DADIGGAIN3, AB8500_DADIGGAIN4,
0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv),
/* Vibra */
SOC_DOUBLE("Vibra High Volume Switch",
AB8500_CLASSDCONF2,
AB8500_CLASSDCONF2_HIGHVOLEN2, AB8500_CLASSDCONF2_HIGHVOLEN3,
1, 0),
SOC_DOUBLE("Vibra Low EMI Mode Switch",
AB8500_CLASSDCONF1,
AB8500_CLASSDCONF1_VIB1SWAPEN, AB8500_CLASSDCONF1_VIB2SWAPEN,
1, 0),
SOC_DOUBLE("Vibra FIR Bypass Switch",
AB8500_CLASSDCONF2,
AB8500_CLASSDCONF2_FIRBYP2, AB8500_CLASSDCONF2_FIRBYP3,
1, 0),
SOC_ENUM("Vibra Mode", soc_enum_da56voice),
SOC_DOUBLE_R("Vibra PWM Duty Cycle N",
AB8500_PWMGENCONF3, AB8500_PWMGENCONF5,
AB8500_PWMGENCONFX_PWMVIBXDUTCYC,
AB8500_PWMGENCONFX_PWMVIBXDUTCYC_MAX, 0),
SOC_DOUBLE_R("Vibra PWM Duty Cycle P",
AB8500_PWMGENCONF2, AB8500_PWMGENCONF4,
AB8500_PWMGENCONFX_PWMVIBXDUTCYC,
AB8500_PWMGENCONFX_PWMVIBXDUTCYC_MAX, 0),
SOC_SINGLE("Vibra 1 and 2 Bridge Switch",
AB8500_CLASSDCONF1, AB8500_CLASSDCONF1_PARLVIB,
1, 0),
SOC_DOUBLE_R_TLV("Vibra Master Volume",
AB8500_DADIGGAIN5, AB8500_DADIGGAIN6,
0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv),
/* HandsFree, Vibra */
SOC_SINGLE("ClassD High Pass Volume",
AB8500_CLASSDCONF3, AB8500_CLASSDCONF3_DITHHPGAIN,
AB8500_CLASSDCONF3_DITHHPGAIN_MAX, 0),
SOC_SINGLE("ClassD White Volume",
AB8500_CLASSDCONF3, AB8500_CLASSDCONF3_DITHWGAIN,
AB8500_CLASSDCONF3_DITHWGAIN_MAX, 0),
/* Mic 1, Mic 2, LineIn */
SOC_DOUBLE_R_TLV("Mic Master Volume",
AB8500_ADDIGGAIN3, AB8500_ADDIGGAIN4,
0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv),
/* Mic 1 */
SOC_SINGLE_TLV("Mic 1",
AB8500_ANAGAIN1,
AB8500_ANAGAINX_MICXGAIN,
AB8500_ANAGAINX_MICXGAIN_MAX, 0, mic_gain_tlv),
SOC_SINGLE("Mic 1 Low Power Switch",
AB8500_ANAGAIN1, AB8500_ANAGAINX_LOWPOWMICX,
1, 0),
/* Mic 2 */
SOC_DOUBLE("Mic High Pass Switch",
AB8500_ADFILTCONF,
AB8500_ADFILTCONF_AD3NH, AB8500_ADFILTCONF_AD4NH,
1, 1),
SOC_ENUM("Mic Mode", soc_enum_ad34voice),
SOC_ENUM("Mic Filter", soc_enum_dmic34sinc),
SOC_SINGLE_TLV("Mic 2",
AB8500_ANAGAIN2,
AB8500_ANAGAINX_MICXGAIN,
AB8500_ANAGAINX_MICXGAIN_MAX, 0, mic_gain_tlv),
SOC_SINGLE("Mic 2 Low Power Switch",
AB8500_ANAGAIN2, AB8500_ANAGAINX_LOWPOWMICX,
1, 0),
/* LineIn */
SOC_DOUBLE("LineIn High Pass Switch",
AB8500_ADFILTCONF,
AB8500_ADFILTCONF_AD1NH, AB8500_ADFILTCONF_AD2NH,
1, 1),
SOC_ENUM("LineIn Filter", soc_enum_dmic12sinc),
SOC_ENUM("LineIn Mode", soc_enum_ad12voice),
SOC_DOUBLE_R_TLV("LineIn Master Volume",
AB8500_ADDIGGAIN1, AB8500_ADDIGGAIN2,
0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv),
SOC_DOUBLE_TLV("LineIn",
AB8500_ANAGAIN4,
AB8500_ANAGAIN4_LINLGAIN, AB8500_ANAGAIN4_LINRGAIN,
AB8500_ANAGAIN4_LINXGAIN_MAX, 0, lin_gain_tlv),
SOC_DOUBLE_R_TLV("LineIn to Headset Volume",
AB8500_DIGLINHSLGAIN, AB8500_DIGLINHSRGAIN,
AB8500_DIGLINHSXGAIN_LINTOHSXGAIN,
AB8500_DIGLINHSXGAIN_LINTOHSXGAIN_MAX,
1, lin2hs_gain_tlv),
/* DMic */
SOC_ENUM("DMic Filter", soc_enum_dmic56sinc),
SOC_DOUBLE_R_TLV("DMic Master Volume",
AB8500_ADDIGGAIN5, AB8500_ADDIGGAIN6,
0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv),
/* Digital gains */
SOC_ENUM("Digital Gain Fade Speed", soc_enum_fadespeed),
/* Analog loopback */
SOC_DOUBLE_R_TLV("Analog Loopback Volume",
AB8500_ADDIGLOOPGAIN1, AB8500_ADDIGLOOPGAIN2,
0, AB8500_ADDIGLOOPGAINX_ADXLBGAIN_MAX, 1, dax_dig_gain_tlv),
/* Digital interface - DA from slot mapping */
SOC_ENUM("Digital Interface DA 1 From Slot Map", soc_enum_da1slotmap),
SOC_ENUM("Digital Interface DA 2 From Slot Map", soc_enum_da2slotmap),
SOC_ENUM("Digital Interface DA 3 From Slot Map", soc_enum_da3slotmap),
SOC_ENUM("Digital Interface DA 4 From Slot Map", soc_enum_da4slotmap),
SOC_ENUM("Digital Interface DA 5 From Slot Map", soc_enum_da5slotmap),
SOC_ENUM("Digital Interface DA 6 From Slot Map", soc_enum_da6slotmap),
SOC_ENUM("Digital Interface DA 7 From Slot Map", soc_enum_da7slotmap),
SOC_ENUM("Digital Interface DA 8 From Slot Map", soc_enum_da8slotmap),
/* Digital interface - AD to slot mapping */
SOC_ENUM("Digital Interface AD To Slot 0 Map", soc_enum_adslot0map),
SOC_ENUM("Digital Interface AD To Slot 1 Map", soc_enum_adslot1map),
SOC_ENUM("Digital Interface AD To Slot 2 Map", soc_enum_adslot2map),
SOC_ENUM("Digital Interface AD To Slot 3 Map", soc_enum_adslot3map),
SOC_ENUM("Digital Interface AD To Slot 4 Map", soc_enum_adslot4map),
SOC_ENUM("Digital Interface AD To Slot 5 Map", soc_enum_adslot5map),
SOC_ENUM("Digital Interface AD To Slot 6 Map", soc_enum_adslot6map),
SOC_ENUM("Digital Interface AD To Slot 7 Map", soc_enum_adslot7map),
SOC_ENUM("Digital Interface AD To Slot 8 Map", soc_enum_adslot8map),
SOC_ENUM("Digital Interface AD To Slot 9 Map", soc_enum_adslot9map),
SOC_ENUM("Digital Interface AD To Slot 10 Map", soc_enum_adslot10map),
SOC_ENUM("Digital Interface AD To Slot 11 Map", soc_enum_adslot11map),
SOC_ENUM("Digital Interface AD To Slot 12 Map", soc_enum_adslot12map),
SOC_ENUM("Digital Interface AD To Slot 13 Map", soc_enum_adslot13map),
SOC_ENUM("Digital Interface AD To Slot 14 Map", soc_enum_adslot14map),
SOC_ENUM("Digital Interface AD To Slot 15 Map", soc_enum_adslot15map),
SOC_ENUM("Digital Interface AD To Slot 16 Map", soc_enum_adslot16map),
SOC_ENUM("Digital Interface AD To Slot 17 Map", soc_enum_adslot17map),
SOC_ENUM("Digital Interface AD To Slot 18 Map", soc_enum_adslot18map),
SOC_ENUM("Digital Interface AD To Slot 19 Map", soc_enum_adslot19map),
SOC_ENUM("Digital Interface AD To Slot 20 Map", soc_enum_adslot20map),
SOC_ENUM("Digital Interface AD To Slot 21 Map", soc_enum_adslot21map),
SOC_ENUM("Digital Interface AD To Slot 22 Map", soc_enum_adslot22map),
SOC_ENUM("Digital Interface AD To Slot 23 Map", soc_enum_adslot23map),
SOC_ENUM("Digital Interface AD To Slot 24 Map", soc_enum_adslot24map),
SOC_ENUM("Digital Interface AD To Slot 25 Map", soc_enum_adslot25map),
SOC_ENUM("Digital Interface AD To Slot 26 Map", soc_enum_adslot26map),
SOC_ENUM("Digital Interface AD To Slot 27 Map", soc_enum_adslot27map),
SOC_ENUM("Digital Interface AD To Slot 28 Map", soc_enum_adslot28map),
SOC_ENUM("Digital Interface AD To Slot 29 Map", soc_enum_adslot29map),
SOC_ENUM("Digital Interface AD To Slot 30 Map", soc_enum_adslot30map),
SOC_ENUM("Digital Interface AD To Slot 31 Map", soc_enum_adslot31map),
/* Digital interface - Loopback */
SOC_SINGLE("Digital Interface AD 1 Loopback Switch",
AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_DAI7TOADO1,
1, 0),
SOC_SINGLE("Digital Interface AD 2 Loopback Switch",
AB8500_DASLOTCONF2, AB8500_DASLOTCONF2_DAI8TOADO2,
1, 0),
SOC_SINGLE("Digital Interface AD 3 Loopback Switch",
AB8500_DASLOTCONF3, AB8500_DASLOTCONF3_DAI7TOADO3,
1, 0),
SOC_SINGLE("Digital Interface AD 4 Loopback Switch",
AB8500_DASLOTCONF4, AB8500_DASLOTCONF4_DAI8TOADO4,
1, 0),
SOC_SINGLE("Digital Interface AD 5 Loopback Switch",
AB8500_DASLOTCONF5, AB8500_DASLOTCONF5_DAI7TOADO5,
1, 0),
SOC_SINGLE("Digital Interface AD 6 Loopback Switch",
AB8500_DASLOTCONF6, AB8500_DASLOTCONF6_DAI8TOADO6,
1, 0),
SOC_SINGLE("Digital Interface AD 7 Loopback Switch",
AB8500_DASLOTCONF7, AB8500_DASLOTCONF7_DAI8TOADO7,
1, 0),
SOC_SINGLE("Digital Interface AD 8 Loopback Switch",
AB8500_DASLOTCONF8, AB8500_DASLOTCONF8_DAI7TOADO8,
1, 0),
/* Digital interface - Burst FIFO */
SOC_SINGLE("Digital Interface 0 FIFO Enable Switch",
AB8500_DIGIFCONF3, AB8500_DIGIFCONF3_IF0BFIFOEN,
1, 0),
SOC_ENUM("Burst FIFO Mask", soc_enum_bfifomask),
SOC_ENUM("Burst FIFO Bit-clock Frequency", soc_enum_bfifo19m2),
SOC_SINGLE("Burst FIFO Threshold",
AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFOINT_SHIFT,
AB8500_FIFOCONF1_BFIFOINT_MAX, 0),
SOC_SINGLE("Burst FIFO Length",
AB8500_FIFOCONF2, AB8500_FIFOCONF2_BFIFOTX_SHIFT,
AB8500_FIFOCONF2_BFIFOTX_MAX, 0),
SOC_SINGLE("Burst FIFO EOS Extra Slots",
AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFOEXSL_SHIFT,
AB8500_FIFOCONF3_BFIFOEXSL_MAX, 0),
SOC_SINGLE("Burst FIFO FS Extra Bit-clocks",
AB8500_FIFOCONF3, AB8500_FIFOCONF3_PREBITCLK0_SHIFT,
AB8500_FIFOCONF3_PREBITCLK0_MAX, 0),
SOC_ENUM("Burst FIFO Interface Mode", soc_enum_bfifomast),
SOC_SINGLE("Burst FIFO Interface Switch",
AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFORUN_SHIFT,
1, 0),
SOC_SINGLE("Burst FIFO Switch Frame Number",
AB8500_FIFOCONF4, AB8500_FIFOCONF4_BFIFOFRAMSW_SHIFT,
AB8500_FIFOCONF4_BFIFOFRAMSW_MAX, 0),
SOC_SINGLE("Burst FIFO Wake Up Delay",
AB8500_FIFOCONF5, AB8500_FIFOCONF5_BFIFOWAKEUP_SHIFT,
AB8500_FIFOCONF5_BFIFOWAKEUP_MAX, 0),
SOC_SINGLE("Burst FIFO Samples In FIFO",
AB8500_FIFOCONF6, AB8500_FIFOCONF6_BFIFOSAMPLE_SHIFT,
AB8500_FIFOCONF6_BFIFOSAMPLE_MAX, 0),
/* ANC */
SOC_ENUM_EXT("ANC Status", soc_enum_ancstate,
anc_status_control_get, anc_status_control_put),
SOC_SINGLE_XR_SX("ANC Warp Delay Shift",
AB8500_ANCCONF2, 1, AB8500_ANCCONF2_SHIFT,
AB8500_ANCCONF2_MIN, AB8500_ANCCONF2_MAX, 0),
SOC_SINGLE_XR_SX("ANC FIR Output Shift",
AB8500_ANCCONF3, 1, AB8500_ANCCONF3_SHIFT,
AB8500_ANCCONF3_MIN, AB8500_ANCCONF3_MAX, 0),
SOC_SINGLE_XR_SX("ANC IIR Output Shift",
AB8500_ANCCONF4, 1, AB8500_ANCCONF4_SHIFT,
AB8500_ANCCONF4_MIN, AB8500_ANCCONF4_MAX, 0),
SOC_SINGLE_XR_SX("ANC Warp Delay",
AB8500_ANCCONF9, 2, AB8500_ANC_WARP_DELAY_SHIFT,
AB8500_ANC_WARP_DELAY_MIN, AB8500_ANC_WARP_DELAY_MAX, 0),
/* Sidetone */
SOC_ENUM_EXT("Sidetone Status", soc_enum_sidstate,
sid_status_control_get, sid_status_control_put),
SOC_SINGLE_STROBE("Sidetone Reset",
AB8500_SIDFIRADR, AB8500_SIDFIRADR_FIRSIDSET, 0),
};
static struct snd_kcontrol_new ab8500_filter_controls[] = {
AB8500_FILTER_CONTROL("ANC FIR Coefficients", AB8500_ANC_FIR_COEFFS,
AB8500_ANC_FIR_COEFF_MIN, AB8500_ANC_FIR_COEFF_MAX),
AB8500_FILTER_CONTROL("ANC IIR Coefficients", AB8500_ANC_IIR_COEFFS,
AB8500_ANC_IIR_COEFF_MIN, AB8500_ANC_IIR_COEFF_MAX),
AB8500_FILTER_CONTROL("Sidetone FIR Coefficients",
AB8500_SID_FIR_COEFFS, AB8500_SID_FIR_COEFF_MIN,
AB8500_SID_FIR_COEFF_MAX)
};
enum ab8500_filter {
AB8500_FILTER_ANC_FIR = 0,
AB8500_FILTER_ANC_IIR = 1,
AB8500_FILTER_SID_FIR = 2,
};
/*
* Extended interface for codec-driver
*/
static int ab8500_audio_init_audioblock(struct snd_soc_component *component)
{
int status;
dev_dbg(component->dev, "%s: Enter.\n", __func__);
/* Reset audio-registers and disable 32kHz-clock output 2 */
status = ab8500_sysctrl_write(AB8500_STW4500CTRL3,
AB8500_STW4500CTRL3_CLK32KOUT2DIS |
AB8500_STW4500CTRL3_RESETAUDN,
AB8500_STW4500CTRL3_RESETAUDN);
if (status < 0)
return status;
return 0;
}
static int ab8500_audio_setup_mics(struct snd_soc_component *component,
struct amic_settings *amics)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
u8 value8;
unsigned int value;
int status;
const struct snd_soc_dapm_route *route;
dev_dbg(component->dev, "%s: Enter.\n", __func__);
/* Set DMic-clocks to outputs */
status = abx500_get_register_interruptible(component->dev, AB8500_MISC,
AB8500_GPIO_DIR4_REG,
&value8);
if (status < 0)
return status;
value = value8 | GPIO27_DIR_OUTPUT | GPIO29_DIR_OUTPUT |
GPIO31_DIR_OUTPUT;
status = abx500_set_register_interruptible(component->dev,
AB8500_MISC,
AB8500_GPIO_DIR4_REG,
value);
if (status < 0)
return status;
/* Attach regulators to AMic DAPM-paths */
dev_dbg(component->dev, "%s: Mic 1a regulator: %s\n", __func__,
amic_micbias_str(amics->mic1a_micbias));
route = &ab8500_dapm_routes_mic1a_vamicx[amics->mic1a_micbias];
status = snd_soc_dapm_add_routes(dapm, route, 1);
dev_dbg(component->dev, "%s: Mic 1b regulator: %s\n", __func__,
amic_micbias_str(amics->mic1b_micbias));
route = &ab8500_dapm_routes_mic1b_vamicx[amics->mic1b_micbias];
status |= snd_soc_dapm_add_routes(dapm, route, 1);
dev_dbg(component->dev, "%s: Mic 2 regulator: %s\n", __func__,
amic_micbias_str(amics->mic2_micbias));
route = &ab8500_dapm_routes_mic2_vamicx[amics->mic2_micbias];
status |= snd_soc_dapm_add_routes(dapm, route, 1);
if (status < 0) {
dev_err(component->dev,
"%s: Failed to add AMic-regulator DAPM-routes (%d).\n",
__func__, status);
return status;
}
/* Set AMic-configuration */
dev_dbg(component->dev, "%s: Mic 1 mic-type: %s\n", __func__,
amic_type_str(amics->mic1_type));
snd_soc_component_update_bits(component, AB8500_ANAGAIN1, AB8500_ANAGAINX_ENSEMICX,
amics->mic1_type == AMIC_TYPE_DIFFERENTIAL ?
0 : AB8500_ANAGAINX_ENSEMICX);
dev_dbg(component->dev, "%s: Mic 2 mic-type: %s\n", __func__,
amic_type_str(amics->mic2_type));
snd_soc_component_update_bits(component, AB8500_ANAGAIN2, AB8500_ANAGAINX_ENSEMICX,
amics->mic2_type == AMIC_TYPE_DIFFERENTIAL ?
0 : AB8500_ANAGAINX_ENSEMICX);
return 0;
}
static int ab8500_audio_set_ear_cmv(struct snd_soc_component *component,
enum ear_cm_voltage ear_cmv)
{
char *cmv_str;
switch (ear_cmv) {
case EAR_CMV_0_95V:
cmv_str = "0.95V";
break;
case EAR_CMV_1_10V:
cmv_str = "1.10V";
break;
case EAR_CMV_1_27V:
cmv_str = "1.27V";
break;
case EAR_CMV_1_58V:
cmv_str = "1.58V";
break;
default:
dev_err(component->dev,
"%s: Unknown earpiece CM-voltage (%d)!\n",
__func__, (int)ear_cmv);
return -EINVAL;
}
dev_dbg(component->dev, "%s: Earpiece CM-voltage: %s\n", __func__,
cmv_str);
snd_soc_component_update_bits(component, AB8500_ANACONF1, AB8500_ANACONF1_EARSELCM,
ear_cmv);
return 0;
}
static int ab8500_audio_set_bit_delay(struct snd_soc_dai *dai,
unsigned int delay)
{
unsigned int mask, val;
struct snd_soc_component *component = dai->component;
mask = BIT(AB8500_DIGIFCONF2_IF0DEL);
val = 0;
switch (delay) {
case 0:
break;
case 1:
val |= BIT(AB8500_DIGIFCONF2_IF0DEL);
break;
default:
dev_err(dai->component->dev,
"%s: ERROR: Unsupported bit-delay (0x%x)!\n",
__func__, delay);
return -EINVAL;
}
dev_dbg(dai->component->dev, "%s: IF0 Bit-delay: %d bits.\n",
__func__, delay);
snd_soc_component_update_bits(component, AB8500_DIGIFCONF2, mask, val);
return 0;
}
/* Gates clocking according format mask */
static int ab8500_codec_set_dai_clock_gate(struct snd_soc_component *component,
unsigned int fmt)
{
unsigned int mask;
unsigned int val;
mask = BIT(AB8500_DIGIFCONF1_ENMASTGEN) |
BIT(AB8500_DIGIFCONF1_ENFSBITCLK0);
val = BIT(AB8500_DIGIFCONF1_ENMASTGEN);
switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) {
case SND_SOC_DAIFMT_CONT: /* continuous clock */
dev_dbg(component->dev, "%s: IF0 Clock is continuous.\n",
__func__);
val |= BIT(AB8500_DIGIFCONF1_ENFSBITCLK0);
break;
case SND_SOC_DAIFMT_GATED: /* clock is gated */
dev_dbg(component->dev, "%s: IF0 Clock is gated.\n",
__func__);
break;
default:
dev_err(component->dev,
"%s: ERROR: Unsupported clock mask (0x%x)!\n",
__func__, fmt & SND_SOC_DAIFMT_CLOCK_MASK);
return -EINVAL;
}
snd_soc_component_update_bits(component, AB8500_DIGIFCONF1, mask, val);
return 0;
}
static int ab8500_codec_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
unsigned int mask;
unsigned int val;
struct snd_soc_component *component = dai->component;
int status;
dev_dbg(component->dev, "%s: Enter (fmt = 0x%x)\n", __func__, fmt);
mask = BIT(AB8500_DIGIFCONF3_IF1DATOIF0AD) |
BIT(AB8500_DIGIFCONF3_IF1CLKTOIF0CLK) |
BIT(AB8500_DIGIFCONF3_IF0BFIFOEN) |
BIT(AB8500_DIGIFCONF3_IF0MASTER);
val = 0;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
dev_dbg(dai->component->dev,
"%s: IF0 Master-mode: AB8500 provider.\n", __func__);
val |= BIT(AB8500_DIGIFCONF3_IF0MASTER);
break;
case SND_SOC_DAIFMT_CBC_CFC:
dev_dbg(dai->component->dev,
"%s: IF0 Master-mode: AB8500 consumer.\n", __func__);
break;
case SND_SOC_DAIFMT_CBC_CFP:
case SND_SOC_DAIFMT_CBP_CFC:
dev_err(dai->component->dev,
"%s: ERROR: The device is either a provider or a consumer.\n",
__func__);
fallthrough;
default:
dev_err(dai->component->dev,
"%s: ERROR: Unsupporter clocking mask 0x%x\n",
__func__, fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK);
return -EINVAL;
}
snd_soc_component_update_bits(component, AB8500_DIGIFCONF3, mask, val);
/* Set clock gating */
status = ab8500_codec_set_dai_clock_gate(component, fmt);
if (status) {
dev_err(dai->component->dev,
"%s: ERROR: Failed to set clock gate (%d).\n",
__func__, status);
return status;
}
/* Setting data transfer format */
mask = BIT(AB8500_DIGIFCONF2_IF0FORMAT0) |
BIT(AB8500_DIGIFCONF2_IF0FORMAT1) |
BIT(AB8500_DIGIFCONF2_FSYNC0P) |
BIT(AB8500_DIGIFCONF2_BITCLK0P);
val = 0;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S: /* I2S mode */
dev_dbg(dai->component->dev, "%s: IF0 Protocol: I2S\n", __func__);
val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT1);
ab8500_audio_set_bit_delay(dai, 0);
break;
case SND_SOC_DAIFMT_DSP_A: /* L data MSB after FRM LRC */
dev_dbg(dai->component->dev,
"%s: IF0 Protocol: DSP A (TDM)\n", __func__);
val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT0);
ab8500_audio_set_bit_delay(dai, 1);
break;
case SND_SOC_DAIFMT_DSP_B: /* L data MSB during FRM LRC */
dev_dbg(dai->component->dev,
"%s: IF0 Protocol: DSP B (TDM)\n", __func__);
val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT0);
ab8500_audio_set_bit_delay(dai, 0);
break;
default:
dev_err(dai->component->dev,
"%s: ERROR: Unsupported format (0x%x)!\n",
__func__, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF: /* normal bit clock + frame */
dev_dbg(dai->component->dev,
"%s: IF0: Normal bit clock, normal frame\n",
__func__);
break;
case SND_SOC_DAIFMT_NB_IF: /* normal BCLK + inv FRM */
dev_dbg(dai->component->dev,
"%s: IF0: Normal bit clock, inverted frame\n",
__func__);
val |= BIT(AB8500_DIGIFCONF2_FSYNC0P);
break;
case SND_SOC_DAIFMT_IB_NF: /* invert BCLK + nor FRM */
dev_dbg(dai->component->dev,
"%s: IF0: Inverted bit clock, normal frame\n",
__func__);
val |= BIT(AB8500_DIGIFCONF2_BITCLK0P);
break;
case SND_SOC_DAIFMT_IB_IF: /* invert BCLK + FRM */
dev_dbg(dai->component->dev,
"%s: IF0: Inverted bit clock, inverted frame\n",
__func__);
val |= BIT(AB8500_DIGIFCONF2_FSYNC0P);
val |= BIT(AB8500_DIGIFCONF2_BITCLK0P);
break;
default:
dev_err(dai->component->dev,
"%s: ERROR: Unsupported INV mask 0x%x\n",
__func__, fmt & SND_SOC_DAIFMT_INV_MASK);
return -EINVAL;
}
snd_soc_component_update_bits(component, AB8500_DIGIFCONF2, mask, val);
return 0;
}
static int ab8500_codec_set_dai_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask,
int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
unsigned int val, mask, slot, slots_active;
mask = BIT(AB8500_DIGIFCONF2_IF0WL0) |
BIT(AB8500_DIGIFCONF2_IF0WL1);
val = 0;
switch (slot_width) {
case 16:
break;
case 20:
val |= BIT(AB8500_DIGIFCONF2_IF0WL0);
break;
case 24:
val |= BIT(AB8500_DIGIFCONF2_IF0WL1);
break;
case 32:
val |= BIT(AB8500_DIGIFCONF2_IF0WL1) |
BIT(AB8500_DIGIFCONF2_IF0WL0);
break;
default:
dev_err(dai->component->dev, "%s: Unsupported slot-width 0x%x\n",
__func__, slot_width);
return -EINVAL;
}
dev_dbg(dai->component->dev, "%s: IF0 slot-width: %d bits.\n",
__func__, slot_width);
snd_soc_component_update_bits(component, AB8500_DIGIFCONF2, mask, val);
/* Setup TDM clocking according to slot count */
dev_dbg(dai->component->dev, "%s: Slots, total: %d\n", __func__, slots);
mask = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0) |
BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1);
switch (slots) {
case 2:
val = AB8500_MASK_NONE;
break;
case 4:
val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0);
break;
case 8:
val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1);
break;
case 16:
val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0) |
BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1);
break;
default:
dev_err(dai->component->dev,
"%s: ERROR: Unsupported number of slots (%d)!\n",
__func__, slots);
return -EINVAL;
}
snd_soc_component_update_bits(component, AB8500_DIGIFCONF1, mask, val);
/* Setup TDM DA according to active tx slots */
if (tx_mask & ~0xff)
return -EINVAL;
mask = AB8500_DASLOTCONFX_SLTODAX_MASK;
tx_mask = tx_mask << AB8500_DA_DATA0_OFFSET;
slots_active = hweight32(tx_mask);
dev_dbg(dai->component->dev, "%s: Slots, active, TX: %d\n", __func__,
slots_active);
switch (slots_active) {
case 0:
break;
case 1:
slot = ffs(tx_mask);
snd_soc_component_update_bits(component, AB8500_DASLOTCONF1, mask, slot);
snd_soc_component_update_bits(component, AB8500_DASLOTCONF3, mask, slot);
snd_soc_component_update_bits(component, AB8500_DASLOTCONF2, mask, slot);
snd_soc_component_update_bits(component, AB8500_DASLOTCONF4, mask, slot);
break;
case 2:
slot = ffs(tx_mask);
snd_soc_component_update_bits(component, AB8500_DASLOTCONF1, mask, slot);
snd_soc_component_update_bits(component, AB8500_DASLOTCONF3, mask, slot);
slot = fls(tx_mask);
snd_soc_component_update_bits(component, AB8500_DASLOTCONF2, mask, slot);
snd_soc_component_update_bits(component, AB8500_DASLOTCONF4, mask, slot);
break;
case 8:
dev_dbg(dai->component->dev,
"%s: In 8-channel mode DA-from-slot mapping is set manually.",
__func__);
break;
default:
dev_err(dai->component->dev,
"%s: Unsupported number of active TX-slots (%d)!\n",
__func__, slots_active);
return -EINVAL;
}
/* Setup TDM AD according to active RX-slots */
if (rx_mask & ~0xff)
return -EINVAL;
rx_mask = rx_mask << AB8500_AD_DATA0_OFFSET;
slots_active = hweight32(rx_mask);
dev_dbg(dai->component->dev, "%s: Slots, active, RX: %d\n", __func__,
slots_active);
switch (slots_active) {
case 0:
break;
case 1:
slot = ffs(rx_mask);
snd_soc_component_update_bits(component, AB8500_ADSLOTSEL(slot),
AB8500_MASK_SLOT(slot),
AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT3, slot));
break;
case 2:
slot = ffs(rx_mask);
snd_soc_component_update_bits(component,
AB8500_ADSLOTSEL(slot),
AB8500_MASK_SLOT(slot),
AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT3, slot));
slot = fls(rx_mask);
snd_soc_component_update_bits(component,
AB8500_ADSLOTSEL(slot),
AB8500_MASK_SLOT(slot),
AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT2, slot));
break;
case 8:
dev_dbg(dai->component->dev,
"%s: In 8-channel mode AD-to-slot mapping is set manually.",
__func__);
break;
default:
dev_err(dai->component->dev,
"%s: Unsupported number of active RX-slots (%d)!\n",
__func__, slots_active);
return -EINVAL;
}
return 0;
}
static const struct snd_soc_dai_ops ab8500_codec_ops = {
.set_fmt = ab8500_codec_set_dai_fmt,
.set_tdm_slot = ab8500_codec_set_dai_tdm_slot,
};
static struct snd_soc_dai_driver ab8500_codec_dai[] = {
{
.name = "ab8500-codec-dai.0",
.id = 0,
.playback = {
.stream_name = "ab8500_0p",
.channels_min = 1,
.channels_max = 8,
.rates = AB8500_SUPPORTED_RATE,
.formats = AB8500_SUPPORTED_FMT,
},
.ops = &ab8500_codec_ops,
.symmetric_rate = 1
},
{
.name = "ab8500-codec-dai.1",
.id = 1,
.capture = {
.stream_name = "ab8500_0c",
.channels_min = 1,
.channels_max = 8,
.rates = AB8500_SUPPORTED_RATE,
.formats = AB8500_SUPPORTED_FMT,
},
.ops = &ab8500_codec_ops,
.symmetric_rate = 1
}
};
static void ab8500_codec_of_probe(struct device *dev, struct device_node *np,
struct ab8500_codec_platform_data *codec)
{
u32 value;
if (of_property_read_bool(np, "stericsson,amic1-type-single-ended"))
codec->amics.mic1_type = AMIC_TYPE_SINGLE_ENDED;
else
codec->amics.mic1_type = AMIC_TYPE_DIFFERENTIAL;
if (of_property_read_bool(np, "stericsson,amic2-type-single-ended"))
codec->amics.mic2_type = AMIC_TYPE_SINGLE_ENDED;
else
codec->amics.mic2_type = AMIC_TYPE_DIFFERENTIAL;
/* Has a non-standard Vamic been requested? */
if (of_property_read_bool(np, "stericsson,amic1a-bias-vamic2"))
codec->amics.mic1a_micbias = AMIC_MICBIAS_VAMIC2;
else
codec->amics.mic1a_micbias = AMIC_MICBIAS_VAMIC1;
if (of_property_read_bool(np, "stericsson,amic1b-bias-vamic2"))
codec->amics.mic1b_micbias = AMIC_MICBIAS_VAMIC2;
else
codec->amics.mic1b_micbias = AMIC_MICBIAS_VAMIC1;
if (of_property_read_bool(np, "stericsson,amic2-bias-vamic1"))
codec->amics.mic2_micbias = AMIC_MICBIAS_VAMIC1;
else
codec->amics.mic2_micbias = AMIC_MICBIAS_VAMIC2;
if (!of_property_read_u32(np, "stericsson,earpeice-cmv", &value)) {
switch (value) {
case 950 :
codec->ear_cmv = EAR_CMV_0_95V;
break;
case 1100 :
codec->ear_cmv = EAR_CMV_1_10V;
break;
case 1270 :
codec->ear_cmv = EAR_CMV_1_27V;
break;
case 1580 :
codec->ear_cmv = EAR_CMV_1_58V;
break;
default :
codec->ear_cmv = EAR_CMV_UNKNOWN;
dev_err(dev, "Unsuitable earpiece voltage found in DT\n");
}
} else {
dev_warn(dev, "No earpiece voltage found in DT - using default\n");
codec->ear_cmv = EAR_CMV_0_95V;
}
}
static int ab8500_codec_probe(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct device *dev = component->dev;
struct device_node *np = dev->of_node;
struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(dev);
struct ab8500_codec_platform_data codec_pdata;
struct filter_control *fc;
int status;
dev_dbg(dev, "%s: Enter.\n", __func__);
ab8500_codec_of_probe(dev, np, &codec_pdata);
status = ab8500_audio_setup_mics(component, &codec_pdata.amics);
if (status < 0) {
pr_err("%s: Failed to setup mics (%d)!\n", __func__, status);
return status;
}
status = ab8500_audio_set_ear_cmv(component, codec_pdata.ear_cmv);
if (status < 0) {
pr_err("%s: Failed to set earpiece CM-voltage (%d)!\n",
__func__, status);
return status;
}
status = ab8500_audio_init_audioblock(component);
if (status < 0) {
dev_err(dev, "%s: failed to init audio-block (%d)!\n",
__func__, status);
return status;
}
/* Override HW-defaults */
snd_soc_component_write(component, AB8500_ANACONF5,
BIT(AB8500_ANACONF5_HSAUTOEN));
snd_soc_component_write(component, AB8500_SHORTCIRCONF,
BIT(AB8500_SHORTCIRCONF_HSZCDDIS));
/* Add filter controls */
status = snd_soc_add_component_controls(component, ab8500_filter_controls,
ARRAY_SIZE(ab8500_filter_controls));
if (status < 0) {
dev_err(dev,
"%s: failed to add ab8500 filter controls (%d).\n",
__func__, status);
return status;
}
fc = (struct filter_control *)
&ab8500_filter_controls[AB8500_FILTER_ANC_FIR].private_value;
drvdata->anc_fir_values = (long *)fc->value;
fc = (struct filter_control *)
&ab8500_filter_controls[AB8500_FILTER_ANC_IIR].private_value;
drvdata->anc_iir_values = (long *)fc->value;
fc = (struct filter_control *)
&ab8500_filter_controls[AB8500_FILTER_SID_FIR].private_value;
drvdata->sid_fir_values = (long *)fc->value;
snd_soc_dapm_disable_pin(dapm, "ANC Configure Input");
mutex_init(&drvdata->ctrl_lock);
return status;
}
static const struct snd_soc_component_driver ab8500_component_driver = {
.probe = ab8500_codec_probe,
.controls = ab8500_ctrls,
.num_controls = ARRAY_SIZE(ab8500_ctrls),
.dapm_widgets = ab8500_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(ab8500_dapm_widgets),
.dapm_routes = ab8500_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(ab8500_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int ab8500_codec_driver_probe(struct platform_device *pdev)
{
int status;
struct ab8500_codec_drvdata *drvdata;
dev_dbg(&pdev->dev, "%s: Enter.\n", __func__);
/* Create driver private-data struct */
drvdata = devm_kzalloc(&pdev->dev, sizeof(struct ab8500_codec_drvdata),
GFP_KERNEL);
if (!drvdata)
return -ENOMEM;
drvdata->sid_status = SID_UNCONFIGURED;
drvdata->anc_status = ANC_UNCONFIGURED;
dev_set_drvdata(&pdev->dev, drvdata);
drvdata->regmap = devm_regmap_init(&pdev->dev, NULL, &pdev->dev,
&ab8500_codec_regmap);
if (IS_ERR(drvdata->regmap)) {
status = PTR_ERR(drvdata->regmap);
dev_err(&pdev->dev, "%s: Failed to allocate regmap: %d\n",
__func__, status);
return status;
}
dev_dbg(&pdev->dev, "%s: Register codec.\n", __func__);
status = devm_snd_soc_register_component(&pdev->dev,
&ab8500_component_driver,
ab8500_codec_dai,
ARRAY_SIZE(ab8500_codec_dai));
if (status < 0)
dev_err(&pdev->dev,
"%s: Error: Failed to register codec (%d).\n",
__func__, status);
return status;
}
static struct platform_driver ab8500_codec_platform_driver = {
.driver = {
.name = "ab8500-codec",
},
.probe = ab8500_codec_driver_probe,
};
module_platform_driver(ab8500_codec_platform_driver);
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/ab8500-codec.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
// Copyright (c) 2017-2018, Linaro Limited
#include <linux/slab.h>
#include <sound/soc.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include "wcd9335.h"
#include "wcd-clsh-v2.h"
struct wcd_clsh_ctrl {
int state;
int mode;
int flyback_users;
int buck_users;
int clsh_users;
int codec_version;
struct snd_soc_component *comp;
};
/* Class-H registers for codecs from and above WCD9335 */
#define WCD9XXX_A_CDC_RX0_RX_PATH_CFG0 WCD9335_REG(0xB, 0x42)
#define WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK BIT(6)
#define WCD9XXX_A_CDC_RX_PATH_CLSH_ENABLE BIT(6)
#define WCD9XXX_A_CDC_RX_PATH_CLSH_DISABLE 0
#define WCD9XXX_A_CDC_RX1_RX_PATH_CFG0 WCD9335_REG(0xB, 0x56)
#define WCD9XXX_A_CDC_RX2_RX_PATH_CFG0 WCD9335_REG(0xB, 0x6A)
#define WCD9XXX_A_CDC_CLSH_K1_MSB WCD9335_REG(0xC, 0x08)
#define WCD9XXX_A_CDC_CLSH_K1_MSB_COEF_MASK GENMASK(3, 0)
#define WCD9XXX_A_CDC_CLSH_K1_LSB WCD9335_REG(0xC, 0x09)
#define WCD9XXX_A_CDC_CLSH_K1_LSB_COEF_MASK GENMASK(7, 0)
#define WCD9XXX_A_ANA_RX_SUPPLIES WCD9335_REG(0x6, 0x08)
#define WCD9XXX_A_ANA_RX_REGULATOR_MODE_MASK BIT(1)
#define WCD9XXX_A_ANA_RX_REGULATOR_MODE_CLS_H 0
#define WCD9XXX_A_ANA_RX_REGULATOR_MODE_CLS_AB BIT(1)
#define WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_MASK BIT(2)
#define WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_UHQA BIT(2)
#define WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_DEFAULT 0
#define WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_MASK BIT(3)
#define WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_UHQA BIT(3)
#define WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_DEFAULT 0
#define WCD9XXX_A_ANA_RX_VNEG_EN_MASK BIT(6)
#define WCD9XXX_A_ANA_RX_VNEG_EN_SHIFT 6
#define WCD9XXX_A_ANA_RX_VNEG_ENABLE BIT(6)
#define WCD9XXX_A_ANA_RX_VNEG_DISABLE 0
#define WCD9XXX_A_ANA_RX_VPOS_EN_MASK BIT(7)
#define WCD9XXX_A_ANA_RX_VPOS_EN_SHIFT 7
#define WCD9XXX_A_ANA_RX_VPOS_ENABLE BIT(7)
#define WCD9XXX_A_ANA_RX_VPOS_DISABLE 0
#define WCD9XXX_A_ANA_HPH WCD9335_REG(0x6, 0x09)
#define WCD9XXX_A_ANA_HPH_PWR_LEVEL_MASK GENMASK(3, 2)
#define WCD9XXX_A_ANA_HPH_PWR_LEVEL_UHQA 0x08
#define WCD9XXX_A_ANA_HPH_PWR_LEVEL_LP 0x04
#define WCD9XXX_A_ANA_HPH_PWR_LEVEL_NORMAL 0x0
#define WCD9XXX_A_CDC_CLSH_CRC WCD9335_REG(0xC, 0x01)
#define WCD9XXX_A_CDC_CLSH_CRC_CLK_EN_MASK BIT(0)
#define WCD9XXX_A_CDC_CLSH_CRC_CLK_ENABLE BIT(0)
#define WCD9XXX_A_CDC_CLSH_CRC_CLK_DISABLE 0
#define WCD9XXX_FLYBACK_EN WCD9335_REG(0x6, 0xA4)
#define WCD9XXX_FLYBACK_EN_DELAY_SEL_MASK GENMASK(6, 5)
#define WCD9XXX_FLYBACK_EN_DELAY_26P25_US 0x40
#define WCD9XXX_FLYBACK_EN_RESET_BY_EXT_MASK BIT(4)
#define WCD9XXX_FLYBACK_EN_PWDN_WITHOUT_DELAY BIT(4)
#define WCD9XXX_FLYBACK_EN_PWDN_WITH_DELAY 0
#define WCD9XXX_RX_BIAS_FLYB_BUFF WCD9335_REG(0x6, 0xC7)
#define WCD9XXX_RX_BIAS_FLYB_VNEG_5_UA_MASK GENMASK(7, 4)
#define WCD9XXX_RX_BIAS_FLYB_VPOS_5_UA_MASK GENMASK(3, 0)
#define WCD9XXX_HPH_L_EN WCD9335_REG(0x6, 0xD3)
#define WCD9XXX_HPH_CONST_SEL_L_MASK GENMASK(7, 3)
#define WCD9XXX_HPH_CONST_SEL_BYPASS 0
#define WCD9XXX_HPH_CONST_SEL_LP_PATH 0x40
#define WCD9XXX_HPH_CONST_SEL_HQ_PATH 0x80
#define WCD9XXX_HPH_R_EN WCD9335_REG(0x6, 0xD6)
#define WCD9XXX_HPH_REFBUFF_UHQA_CTL WCD9335_REG(0x6, 0xDD)
#define WCD9XXX_HPH_REFBUFF_UHQA_GAIN_MASK GENMASK(2, 0)
#define WCD9XXX_CLASSH_CTRL_VCL_2 WCD9335_REG(0x6, 0x9B)
#define WCD9XXX_CLASSH_CTRL_VCL_2_VREF_FILT_1_MASK GENMASK(5, 4)
#define WCD9XXX_CLASSH_CTRL_VCL_VREF_FILT_R_50KOHM 0x20
#define WCD9XXX_CLASSH_CTRL_VCL_VREF_FILT_R_0KOHM 0x0
#define WCD9XXX_CDC_RX1_RX_PATH_CTL WCD9335_REG(0xB, 0x55)
#define WCD9XXX_CDC_RX2_RX_PATH_CTL WCD9335_REG(0xB, 0x69)
#define WCD9XXX_CDC_CLK_RST_CTRL_MCLK_CONTROL WCD9335_REG(0xD, 0x41)
#define WCD9XXX_CDC_CLK_RST_CTRL_MCLK_EN_MASK BIT(0)
#define WCD9XXX_CDC_CLK_RST_CTRL_MCLK_11P3_EN_MASK BIT(1)
#define WCD9XXX_CLASSH_CTRL_CCL_1 WCD9335_REG(0x6, 0x9C)
#define WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_MASK GENMASK(7, 4)
#define WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_50MA 0x50
#define WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_30MA 0x30
#define WCD9XXX_BASE_ADDRESS 0x3000
#define WCD9XXX_ANA_RX_SUPPLIES (WCD9XXX_BASE_ADDRESS+0x008)
#define WCD9XXX_ANA_HPH (WCD9XXX_BASE_ADDRESS+0x009)
#define WCD9XXX_CLASSH_MODE_2 (WCD9XXX_BASE_ADDRESS+0x098)
#define WCD9XXX_CLASSH_MODE_3 (WCD9XXX_BASE_ADDRESS+0x099)
#define WCD9XXX_FLYBACK_VNEG_CTRL_1 (WCD9XXX_BASE_ADDRESS+0x0A5)
#define WCD9XXX_FLYBACK_VNEG_CTRL_4 (WCD9XXX_BASE_ADDRESS+0x0A8)
#define WCD9XXX_FLYBACK_VNEGDAC_CTRL_2 (WCD9XXX_BASE_ADDRESS+0x0AF)
#define WCD9XXX_RX_BIAS_HPH_LOWPOWER (WCD9XXX_BASE_ADDRESS+0x0BF)
#define WCD9XXX_V3_RX_BIAS_FLYB_BUFF (WCD9XXX_BASE_ADDRESS+0x0C7)
#define WCD9XXX_HPH_PA_CTL1 (WCD9XXX_BASE_ADDRESS+0x0D1)
#define WCD9XXX_HPH_NEW_INT_PA_MISC2 (WCD9XXX_BASE_ADDRESS+0x138)
#define CLSH_REQ_ENABLE true
#define CLSH_REQ_DISABLE false
#define WCD_USLEEP_RANGE 50
enum {
DAC_GAIN_0DB = 0,
DAC_GAIN_0P2DB,
DAC_GAIN_0P4DB,
DAC_GAIN_0P6DB,
DAC_GAIN_0P8DB,
DAC_GAIN_M0P2DB,
DAC_GAIN_M0P4DB,
DAC_GAIN_M0P6DB,
};
static inline void wcd_enable_clsh_block(struct wcd_clsh_ctrl *ctrl,
bool enable)
{
struct snd_soc_component *comp = ctrl->comp;
if ((enable && ++ctrl->clsh_users == 1) ||
(!enable && --ctrl->clsh_users == 0))
snd_soc_component_update_bits(comp, WCD9XXX_A_CDC_CLSH_CRC,
WCD9XXX_A_CDC_CLSH_CRC_CLK_EN_MASK,
enable);
if (ctrl->clsh_users < 0)
ctrl->clsh_users = 0;
}
static inline void wcd_clsh_set_buck_mode(struct snd_soc_component *comp,
int mode)
{
/* set to HIFI */
if (mode == CLS_H_HIFI)
snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES,
WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_MASK,
WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_UHQA);
else
snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES,
WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_MASK,
WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_DEFAULT);
}
static void wcd_clsh_v3_set_buck_mode(struct snd_soc_component *component,
int mode)
{
if (mode == CLS_H_HIFI || mode == CLS_H_LOHIFI ||
mode == CLS_AB_HIFI || mode == CLS_AB_LOHIFI)
snd_soc_component_update_bits(component,
WCD9XXX_ANA_RX_SUPPLIES,
0x08, 0x08); /* set to HIFI */
else
snd_soc_component_update_bits(component,
WCD9XXX_ANA_RX_SUPPLIES,
0x08, 0x00); /* set to default */
}
static inline void wcd_clsh_set_flyback_mode(struct snd_soc_component *comp,
int mode)
{
/* set to HIFI */
if (mode == CLS_H_HIFI)
snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES,
WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_MASK,
WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_UHQA);
else
snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES,
WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_MASK,
WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_DEFAULT);
}
static void wcd_clsh_buck_ctrl(struct wcd_clsh_ctrl *ctrl,
int mode,
bool enable)
{
struct snd_soc_component *comp = ctrl->comp;
/* enable/disable buck */
if ((enable && (++ctrl->buck_users == 1)) ||
(!enable && (--ctrl->buck_users == 0)))
snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES,
WCD9XXX_A_ANA_RX_VPOS_EN_MASK,
enable << WCD9XXX_A_ANA_RX_VPOS_EN_SHIFT);
/*
* 500us sleep is required after buck enable/disable
* as per HW requirement
*/
usleep_range(500, 500 + WCD_USLEEP_RANGE);
}
static void wcd_clsh_v3_buck_ctrl(struct snd_soc_component *component,
struct wcd_clsh_ctrl *ctrl,
int mode,
bool enable)
{
/* enable/disable buck */
if ((enable && (++ctrl->buck_users == 1)) ||
(!enable && (--ctrl->buck_users == 0))) {
snd_soc_component_update_bits(component,
WCD9XXX_ANA_RX_SUPPLIES,
(1 << 7), (enable << 7));
/*
* 500us sleep is required after buck enable/disable
* as per HW requirement
*/
usleep_range(500, 510);
if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
mode == CLS_H_HIFI || mode == CLS_H_LP)
snd_soc_component_update_bits(component,
WCD9XXX_CLASSH_MODE_3,
0x02, 0x00);
snd_soc_component_update_bits(component,
WCD9XXX_CLASSH_MODE_2,
0xFF, 0x3A);
/* 500usec delay is needed as per HW requirement */
usleep_range(500, 500 + WCD_USLEEP_RANGE);
}
}
static void wcd_clsh_flyback_ctrl(struct wcd_clsh_ctrl *ctrl,
int mode,
bool enable)
{
struct snd_soc_component *comp = ctrl->comp;
/* enable/disable flyback */
if ((enable && (++ctrl->flyback_users == 1)) ||
(!enable && (--ctrl->flyback_users == 0))) {
snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES,
WCD9XXX_A_ANA_RX_VNEG_EN_MASK,
enable << WCD9XXX_A_ANA_RX_VNEG_EN_SHIFT);
/* 100usec delay is needed as per HW requirement */
usleep_range(100, 110);
}
/*
* 500us sleep is required after flyback enable/disable
* as per HW requirement
*/
usleep_range(500, 500 + WCD_USLEEP_RANGE);
}
static void wcd_clsh_set_gain_path(struct wcd_clsh_ctrl *ctrl, int mode)
{
struct snd_soc_component *comp = ctrl->comp;
int val = 0;
switch (mode) {
case CLS_H_NORMAL:
case CLS_AB:
val = WCD9XXX_HPH_CONST_SEL_BYPASS;
break;
case CLS_H_HIFI:
val = WCD9XXX_HPH_CONST_SEL_HQ_PATH;
break;
case CLS_H_LP:
val = WCD9XXX_HPH_CONST_SEL_LP_PATH;
break;
}
snd_soc_component_update_bits(comp, WCD9XXX_HPH_L_EN,
WCD9XXX_HPH_CONST_SEL_L_MASK,
val);
snd_soc_component_update_bits(comp, WCD9XXX_HPH_R_EN,
WCD9XXX_HPH_CONST_SEL_L_MASK,
val);
}
static void wcd_clsh_v2_set_hph_mode(struct snd_soc_component *comp, int mode)
{
int val = 0, gain = 0, res_val;
int ipeak = WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_50MA;
res_val = WCD9XXX_CLASSH_CTRL_VCL_VREF_FILT_R_0KOHM;
switch (mode) {
case CLS_H_NORMAL:
res_val = WCD9XXX_CLASSH_CTRL_VCL_VREF_FILT_R_50KOHM;
val = WCD9XXX_A_ANA_HPH_PWR_LEVEL_NORMAL;
gain = DAC_GAIN_0DB;
ipeak = WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_50MA;
break;
case CLS_AB:
val = WCD9XXX_A_ANA_HPH_PWR_LEVEL_NORMAL;
gain = DAC_GAIN_0DB;
ipeak = WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_50MA;
break;
case CLS_H_HIFI:
val = WCD9XXX_A_ANA_HPH_PWR_LEVEL_UHQA;
gain = DAC_GAIN_M0P2DB;
ipeak = WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_50MA;
break;
case CLS_H_LP:
val = WCD9XXX_A_ANA_HPH_PWR_LEVEL_LP;
ipeak = WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_30MA;
break;
}
snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_HPH,
WCD9XXX_A_ANA_HPH_PWR_LEVEL_MASK, val);
snd_soc_component_update_bits(comp, WCD9XXX_CLASSH_CTRL_VCL_2,
WCD9XXX_CLASSH_CTRL_VCL_2_VREF_FILT_1_MASK,
res_val);
if (mode != CLS_H_LP)
snd_soc_component_update_bits(comp,
WCD9XXX_HPH_REFBUFF_UHQA_CTL,
WCD9XXX_HPH_REFBUFF_UHQA_GAIN_MASK,
gain);
snd_soc_component_update_bits(comp, WCD9XXX_CLASSH_CTRL_CCL_1,
WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_MASK,
ipeak);
}
static void wcd_clsh_v3_set_hph_mode(struct snd_soc_component *component,
int mode)
{
u8 val;
switch (mode) {
case CLS_H_NORMAL:
val = 0x00;
break;
case CLS_AB:
case CLS_H_ULP:
val = 0x0C;
break;
case CLS_AB_HIFI:
case CLS_H_HIFI:
val = 0x08;
break;
case CLS_H_LP:
case CLS_H_LOHIFI:
case CLS_AB_LP:
case CLS_AB_LOHIFI:
val = 0x04;
break;
default:
dev_err(component->dev, "%s:Invalid mode %d\n", __func__, mode);
return;
}
snd_soc_component_update_bits(component, WCD9XXX_ANA_HPH, 0x0C, val);
}
void wcd_clsh_set_hph_mode(struct wcd_clsh_ctrl *ctrl, int mode)
{
struct snd_soc_component *comp = ctrl->comp;
if (ctrl->codec_version >= WCD937X)
wcd_clsh_v3_set_hph_mode(comp, mode);
else
wcd_clsh_v2_set_hph_mode(comp, mode);
}
EXPORT_SYMBOL_GPL(wcd_clsh_set_hph_mode);
static void wcd_clsh_set_flyback_current(struct snd_soc_component *comp,
int mode)
{
snd_soc_component_update_bits(comp, WCD9XXX_RX_BIAS_FLYB_BUFF,
WCD9XXX_RX_BIAS_FLYB_VPOS_5_UA_MASK, 0x0A);
snd_soc_component_update_bits(comp, WCD9XXX_RX_BIAS_FLYB_BUFF,
WCD9XXX_RX_BIAS_FLYB_VNEG_5_UA_MASK, 0x0A);
/* Sleep needed to avoid click and pop as per HW requirement */
usleep_range(100, 110);
}
static void wcd_clsh_set_buck_regulator_mode(struct snd_soc_component *comp,
int mode)
{
if (mode == CLS_AB)
snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES,
WCD9XXX_A_ANA_RX_REGULATOR_MODE_MASK,
WCD9XXX_A_ANA_RX_REGULATOR_MODE_CLS_AB);
else
snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES,
WCD9XXX_A_ANA_RX_REGULATOR_MODE_MASK,
WCD9XXX_A_ANA_RX_REGULATOR_MODE_CLS_H);
}
static void wcd_clsh_v3_set_buck_regulator_mode(struct snd_soc_component *component,
int mode)
{
snd_soc_component_update_bits(component, WCD9XXX_ANA_RX_SUPPLIES,
0x02, 0x00);
}
static void wcd_clsh_v3_set_flyback_mode(struct snd_soc_component *component,
int mode)
{
if (mode == CLS_H_HIFI || mode == CLS_H_LOHIFI ||
mode == CLS_AB_HIFI || mode == CLS_AB_LOHIFI) {
snd_soc_component_update_bits(component,
WCD9XXX_ANA_RX_SUPPLIES,
0x04, 0x04);
snd_soc_component_update_bits(component,
WCD9XXX_FLYBACK_VNEG_CTRL_4,
0xF0, 0x80);
} else {
snd_soc_component_update_bits(component,
WCD9XXX_ANA_RX_SUPPLIES,
0x04, 0x00); /* set to Default */
snd_soc_component_update_bits(component,
WCD9XXX_FLYBACK_VNEG_CTRL_4,
0xF0, 0x70);
}
}
static void wcd_clsh_v3_force_iq_ctl(struct snd_soc_component *component,
int mode, bool enable)
{
if (enable) {
snd_soc_component_update_bits(component,
WCD9XXX_FLYBACK_VNEGDAC_CTRL_2,
0xE0, 0xA0);
/* 100usec delay is needed as per HW requirement */
usleep_range(100, 110);
snd_soc_component_update_bits(component,
WCD9XXX_CLASSH_MODE_3,
0x02, 0x02);
snd_soc_component_update_bits(component,
WCD9XXX_CLASSH_MODE_2,
0xFF, 0x1C);
if (mode == CLS_H_LOHIFI || mode == CLS_AB_LOHIFI) {
snd_soc_component_update_bits(component,
WCD9XXX_HPH_NEW_INT_PA_MISC2,
0x20, 0x20);
snd_soc_component_update_bits(component,
WCD9XXX_RX_BIAS_HPH_LOWPOWER,
0xF0, 0xC0);
snd_soc_component_update_bits(component,
WCD9XXX_HPH_PA_CTL1,
0x0E, 0x02);
}
} else {
snd_soc_component_update_bits(component,
WCD9XXX_HPH_NEW_INT_PA_MISC2,
0x20, 0x00);
snd_soc_component_update_bits(component,
WCD9XXX_RX_BIAS_HPH_LOWPOWER,
0xF0, 0x80);
snd_soc_component_update_bits(component,
WCD9XXX_HPH_PA_CTL1,
0x0E, 0x06);
}
}
static void wcd_clsh_v3_flyback_ctrl(struct snd_soc_component *component,
struct wcd_clsh_ctrl *ctrl,
int mode,
bool enable)
{
/* enable/disable flyback */
if ((enable && (++ctrl->flyback_users == 1)) ||
(!enable && (--ctrl->flyback_users == 0))) {
snd_soc_component_update_bits(component,
WCD9XXX_FLYBACK_VNEG_CTRL_1,
0xE0, 0xE0);
snd_soc_component_update_bits(component,
WCD9XXX_ANA_RX_SUPPLIES,
(1 << 6), (enable << 6));
/*
* 100us sleep is required after flyback enable/disable
* as per HW requirement
*/
usleep_range(100, 110);
snd_soc_component_update_bits(component,
WCD9XXX_FLYBACK_VNEGDAC_CTRL_2,
0xE0, 0xE0);
/* 500usec delay is needed as per HW requirement */
usleep_range(500, 500 + WCD_USLEEP_RANGE);
}
}
static void wcd_clsh_v3_set_flyback_current(struct snd_soc_component *component,
int mode)
{
snd_soc_component_update_bits(component, WCD9XXX_V3_RX_BIAS_FLYB_BUFF,
0x0F, 0x0A);
snd_soc_component_update_bits(component, WCD9XXX_V3_RX_BIAS_FLYB_BUFF,
0xF0, 0xA0);
/* Sleep needed to avoid click and pop as per HW requirement */
usleep_range(100, 110);
}
static void wcd_clsh_v3_state_aux(struct wcd_clsh_ctrl *ctrl, int req_state,
bool is_enable, int mode)
{
struct snd_soc_component *component = ctrl->comp;
if (is_enable) {
wcd_clsh_v3_set_buck_mode(component, mode);
wcd_clsh_v3_set_flyback_mode(component, mode);
wcd_clsh_v3_flyback_ctrl(component, ctrl, mode, true);
wcd_clsh_v3_set_flyback_current(component, mode);
wcd_clsh_v3_buck_ctrl(component, ctrl, mode, true);
} else {
wcd_clsh_v3_buck_ctrl(component, ctrl, mode, false);
wcd_clsh_v3_flyback_ctrl(component, ctrl, mode, false);
wcd_clsh_v3_set_flyback_mode(component, CLS_H_NORMAL);
wcd_clsh_v3_set_buck_mode(component, CLS_H_NORMAL);
}
}
static void wcd_clsh_state_lo(struct wcd_clsh_ctrl *ctrl, int req_state,
bool is_enable, int mode)
{
struct snd_soc_component *comp = ctrl->comp;
if (mode != CLS_AB) {
dev_err(comp->dev, "%s: LO cannot be in this mode: %d\n",
__func__, mode);
return;
}
if (is_enable) {
wcd_clsh_set_buck_regulator_mode(comp, mode);
wcd_clsh_set_buck_mode(comp, mode);
wcd_clsh_set_flyback_mode(comp, mode);
wcd_clsh_flyback_ctrl(ctrl, mode, true);
wcd_clsh_set_flyback_current(comp, mode);
wcd_clsh_buck_ctrl(ctrl, mode, true);
} else {
wcd_clsh_buck_ctrl(ctrl, mode, false);
wcd_clsh_flyback_ctrl(ctrl, mode, false);
wcd_clsh_set_flyback_mode(comp, CLS_H_NORMAL);
wcd_clsh_set_buck_mode(comp, CLS_H_NORMAL);
wcd_clsh_set_buck_regulator_mode(comp, CLS_H_NORMAL);
}
}
static void wcd_clsh_v3_state_hph_r(struct wcd_clsh_ctrl *ctrl, int req_state,
bool is_enable, int mode)
{
struct snd_soc_component *component = ctrl->comp;
if (mode == CLS_H_NORMAL) {
dev_dbg(component->dev, "%s: Normal mode not applicable for hph_r\n",
__func__);
return;
}
if (is_enable) {
wcd_clsh_v3_set_buck_regulator_mode(component, mode);
wcd_clsh_v3_set_flyback_mode(component, mode);
wcd_clsh_v3_force_iq_ctl(component, mode, true);
wcd_clsh_v3_flyback_ctrl(component, ctrl, mode, true);
wcd_clsh_v3_set_flyback_current(component, mode);
wcd_clsh_v3_set_buck_mode(component, mode);
wcd_clsh_v3_buck_ctrl(component, ctrl, mode, true);
wcd_clsh_v3_set_hph_mode(component, mode);
} else {
wcd_clsh_v3_set_hph_mode(component, CLS_H_NORMAL);
/* buck and flyback set to default mode and disable */
wcd_clsh_v3_flyback_ctrl(component, ctrl, CLS_H_NORMAL, false);
wcd_clsh_v3_buck_ctrl(component, ctrl, CLS_H_NORMAL, false);
wcd_clsh_v3_force_iq_ctl(component, CLS_H_NORMAL, false);
wcd_clsh_v3_set_flyback_mode(component, CLS_H_NORMAL);
wcd_clsh_v3_set_buck_mode(component, CLS_H_NORMAL);
}
}
static void wcd_clsh_state_hph_r(struct wcd_clsh_ctrl *ctrl, int req_state,
bool is_enable, int mode)
{
struct snd_soc_component *comp = ctrl->comp;
if (mode == CLS_H_NORMAL) {
dev_err(comp->dev, "%s: Normal mode not applicable for hph_r\n",
__func__);
return;
}
if (is_enable) {
if (mode != CLS_AB) {
wcd_enable_clsh_block(ctrl, true);
/*
* These K1 values depend on the Headphone Impedance
* For now it is assumed to be 16 ohm
*/
snd_soc_component_update_bits(comp,
WCD9XXX_A_CDC_CLSH_K1_MSB,
WCD9XXX_A_CDC_CLSH_K1_MSB_COEF_MASK,
0x00);
snd_soc_component_update_bits(comp,
WCD9XXX_A_CDC_CLSH_K1_LSB,
WCD9XXX_A_CDC_CLSH_K1_LSB_COEF_MASK,
0xC0);
snd_soc_component_update_bits(comp,
WCD9XXX_A_CDC_RX2_RX_PATH_CFG0,
WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK,
WCD9XXX_A_CDC_RX_PATH_CLSH_ENABLE);
}
wcd_clsh_set_buck_regulator_mode(comp, mode);
wcd_clsh_set_flyback_mode(comp, mode);
wcd_clsh_flyback_ctrl(ctrl, mode, true);
wcd_clsh_set_flyback_current(comp, mode);
wcd_clsh_set_buck_mode(comp, mode);
wcd_clsh_buck_ctrl(ctrl, mode, true);
wcd_clsh_v2_set_hph_mode(comp, mode);
wcd_clsh_set_gain_path(ctrl, mode);
} else {
wcd_clsh_v2_set_hph_mode(comp, CLS_H_NORMAL);
if (mode != CLS_AB) {
snd_soc_component_update_bits(comp,
WCD9XXX_A_CDC_RX2_RX_PATH_CFG0,
WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK,
WCD9XXX_A_CDC_RX_PATH_CLSH_DISABLE);
wcd_enable_clsh_block(ctrl, false);
}
/* buck and flyback set to default mode and disable */
wcd_clsh_buck_ctrl(ctrl, CLS_H_NORMAL, false);
wcd_clsh_flyback_ctrl(ctrl, CLS_H_NORMAL, false);
wcd_clsh_set_flyback_mode(comp, CLS_H_NORMAL);
wcd_clsh_set_buck_mode(comp, CLS_H_NORMAL);
wcd_clsh_set_buck_regulator_mode(comp, CLS_H_NORMAL);
}
}
static void wcd_clsh_v3_state_hph_l(struct wcd_clsh_ctrl *ctrl, int req_state,
bool is_enable, int mode)
{
struct snd_soc_component *component = ctrl->comp;
if (mode == CLS_H_NORMAL) {
dev_dbg(component->dev, "%s: Normal mode not applicable for hph_l\n",
__func__);
return;
}
if (is_enable) {
wcd_clsh_v3_set_buck_regulator_mode(component, mode);
wcd_clsh_v3_set_flyback_mode(component, mode);
wcd_clsh_v3_force_iq_ctl(component, mode, true);
wcd_clsh_v3_flyback_ctrl(component, ctrl, mode, true);
wcd_clsh_v3_set_flyback_current(component, mode);
wcd_clsh_v3_set_buck_mode(component, mode);
wcd_clsh_v3_buck_ctrl(component, ctrl, mode, true);
wcd_clsh_v3_set_hph_mode(component, mode);
} else {
wcd_clsh_v3_set_hph_mode(component, CLS_H_NORMAL);
/* set buck and flyback to Default Mode */
wcd_clsh_v3_flyback_ctrl(component, ctrl, CLS_H_NORMAL, false);
wcd_clsh_v3_buck_ctrl(component, ctrl, CLS_H_NORMAL, false);
wcd_clsh_v3_force_iq_ctl(component, CLS_H_NORMAL, false);
wcd_clsh_v3_set_flyback_mode(component, CLS_H_NORMAL);
wcd_clsh_v3_set_buck_mode(component, CLS_H_NORMAL);
}
}
static void wcd_clsh_state_hph_l(struct wcd_clsh_ctrl *ctrl, int req_state,
bool is_enable, int mode)
{
struct snd_soc_component *comp = ctrl->comp;
if (mode == CLS_H_NORMAL) {
dev_err(comp->dev, "%s: Normal mode not applicable for hph_l\n",
__func__);
return;
}
if (is_enable) {
if (mode != CLS_AB) {
wcd_enable_clsh_block(ctrl, true);
/*
* These K1 values depend on the Headphone Impedance
* For now it is assumed to be 16 ohm
*/
snd_soc_component_update_bits(comp,
WCD9XXX_A_CDC_CLSH_K1_MSB,
WCD9XXX_A_CDC_CLSH_K1_MSB_COEF_MASK,
0x00);
snd_soc_component_update_bits(comp,
WCD9XXX_A_CDC_CLSH_K1_LSB,
WCD9XXX_A_CDC_CLSH_K1_LSB_COEF_MASK,
0xC0);
snd_soc_component_update_bits(comp,
WCD9XXX_A_CDC_RX1_RX_PATH_CFG0,
WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK,
WCD9XXX_A_CDC_RX_PATH_CLSH_ENABLE);
}
wcd_clsh_set_buck_regulator_mode(comp, mode);
wcd_clsh_set_flyback_mode(comp, mode);
wcd_clsh_flyback_ctrl(ctrl, mode, true);
wcd_clsh_set_flyback_current(comp, mode);
wcd_clsh_set_buck_mode(comp, mode);
wcd_clsh_buck_ctrl(ctrl, mode, true);
wcd_clsh_v2_set_hph_mode(comp, mode);
wcd_clsh_set_gain_path(ctrl, mode);
} else {
wcd_clsh_v2_set_hph_mode(comp, CLS_H_NORMAL);
if (mode != CLS_AB) {
snd_soc_component_update_bits(comp,
WCD9XXX_A_CDC_RX1_RX_PATH_CFG0,
WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK,
WCD9XXX_A_CDC_RX_PATH_CLSH_DISABLE);
wcd_enable_clsh_block(ctrl, false);
}
/* set buck and flyback to Default Mode */
wcd_clsh_buck_ctrl(ctrl, CLS_H_NORMAL, false);
wcd_clsh_flyback_ctrl(ctrl, CLS_H_NORMAL, false);
wcd_clsh_set_flyback_mode(comp, CLS_H_NORMAL);
wcd_clsh_set_buck_mode(comp, CLS_H_NORMAL);
wcd_clsh_set_buck_regulator_mode(comp, CLS_H_NORMAL);
}
}
static void wcd_clsh_v3_state_ear(struct wcd_clsh_ctrl *ctrl, int req_state,
bool is_enable, int mode)
{
struct snd_soc_component *component = ctrl->comp;
if (is_enable) {
wcd_clsh_v3_set_buck_regulator_mode(component, mode);
wcd_clsh_v3_set_flyback_mode(component, mode);
wcd_clsh_v3_force_iq_ctl(component, mode, true);
wcd_clsh_v3_flyback_ctrl(component, ctrl, mode, true);
wcd_clsh_v3_set_flyback_current(component, mode);
wcd_clsh_v3_set_buck_mode(component, mode);
wcd_clsh_v3_buck_ctrl(component, ctrl, mode, true);
wcd_clsh_v3_set_hph_mode(component, mode);
} else {
wcd_clsh_v3_set_hph_mode(component, CLS_H_NORMAL);
/* set buck and flyback to Default Mode */
wcd_clsh_v3_flyback_ctrl(component, ctrl, CLS_H_NORMAL, false);
wcd_clsh_v3_buck_ctrl(component, ctrl, CLS_H_NORMAL, false);
wcd_clsh_v3_force_iq_ctl(component, CLS_H_NORMAL, false);
wcd_clsh_v3_set_flyback_mode(component, CLS_H_NORMAL);
wcd_clsh_v3_set_buck_mode(component, CLS_H_NORMAL);
}
}
static void wcd_clsh_state_ear(struct wcd_clsh_ctrl *ctrl, int req_state,
bool is_enable, int mode)
{
struct snd_soc_component *comp = ctrl->comp;
if (mode != CLS_H_NORMAL) {
dev_err(comp->dev, "%s: mode: %d cannot be used for EAR\n",
__func__, mode);
return;
}
if (is_enable) {
wcd_enable_clsh_block(ctrl, true);
snd_soc_component_update_bits(comp,
WCD9XXX_A_CDC_RX0_RX_PATH_CFG0,
WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK,
WCD9XXX_A_CDC_RX_PATH_CLSH_ENABLE);
wcd_clsh_set_buck_mode(comp, mode);
wcd_clsh_set_flyback_mode(comp, mode);
wcd_clsh_flyback_ctrl(ctrl, mode, true);
wcd_clsh_set_flyback_current(comp, mode);
wcd_clsh_buck_ctrl(ctrl, mode, true);
} else {
snd_soc_component_update_bits(comp,
WCD9XXX_A_CDC_RX0_RX_PATH_CFG0,
WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK,
WCD9XXX_A_CDC_RX_PATH_CLSH_DISABLE);
wcd_enable_clsh_block(ctrl, false);
wcd_clsh_buck_ctrl(ctrl, mode, false);
wcd_clsh_flyback_ctrl(ctrl, mode, false);
wcd_clsh_set_flyback_mode(comp, CLS_H_NORMAL);
wcd_clsh_set_buck_mode(comp, CLS_H_NORMAL);
}
}
static int _wcd_clsh_ctrl_set_state(struct wcd_clsh_ctrl *ctrl, int req_state,
bool is_enable, int mode)
{
switch (req_state) {
case WCD_CLSH_STATE_EAR:
if (ctrl->codec_version >= WCD937X)
wcd_clsh_v3_state_ear(ctrl, req_state, is_enable, mode);
else
wcd_clsh_state_ear(ctrl, req_state, is_enable, mode);
break;
case WCD_CLSH_STATE_HPHL:
if (ctrl->codec_version >= WCD937X)
wcd_clsh_v3_state_hph_l(ctrl, req_state, is_enable, mode);
else
wcd_clsh_state_hph_l(ctrl, req_state, is_enable, mode);
break;
case WCD_CLSH_STATE_HPHR:
if (ctrl->codec_version >= WCD937X)
wcd_clsh_v3_state_hph_r(ctrl, req_state, is_enable, mode);
else
wcd_clsh_state_hph_r(ctrl, req_state, is_enable, mode);
break;
case WCD_CLSH_STATE_LO:
if (ctrl->codec_version < WCD937X)
wcd_clsh_state_lo(ctrl, req_state, is_enable, mode);
break;
case WCD_CLSH_STATE_AUX:
if (ctrl->codec_version >= WCD937X)
wcd_clsh_v3_state_aux(ctrl, req_state, is_enable, mode);
break;
default:
break;
}
return 0;
}
/*
* Function: wcd_clsh_is_state_valid
* Params: state
* Description:
* Provides information on valid states of Class H configuration
*/
static bool wcd_clsh_is_state_valid(int state)
{
switch (state) {
case WCD_CLSH_STATE_IDLE:
case WCD_CLSH_STATE_EAR:
case WCD_CLSH_STATE_HPHL:
case WCD_CLSH_STATE_HPHR:
case WCD_CLSH_STATE_LO:
case WCD_CLSH_STATE_AUX:
return true;
default:
return false;
};
}
/*
* Function: wcd_clsh_fsm
* Params: ctrl, req_state, req_type, clsh_event
* Description:
* This function handles PRE DAC and POST DAC conditions of different devices
* and updates class H configuration of different combination of devices
* based on validity of their states. ctrl will contain current
* class h state information
*/
int wcd_clsh_ctrl_set_state(struct wcd_clsh_ctrl *ctrl,
enum wcd_clsh_event clsh_event,
int nstate,
enum wcd_clsh_mode mode)
{
struct snd_soc_component *comp = ctrl->comp;
if (nstate == ctrl->state)
return 0;
if (!wcd_clsh_is_state_valid(nstate)) {
dev_err(comp->dev, "Class-H not a valid new state:\n");
return -EINVAL;
}
switch (clsh_event) {
case WCD_CLSH_EVENT_PRE_DAC:
_wcd_clsh_ctrl_set_state(ctrl, nstate, CLSH_REQ_ENABLE, mode);
break;
case WCD_CLSH_EVENT_POST_PA:
_wcd_clsh_ctrl_set_state(ctrl, nstate, CLSH_REQ_DISABLE, mode);
break;
}
ctrl->state = nstate;
ctrl->mode = mode;
return 0;
}
EXPORT_SYMBOL_GPL(wcd_clsh_ctrl_set_state);
int wcd_clsh_ctrl_get_state(struct wcd_clsh_ctrl *ctrl)
{
return ctrl->state;
}
EXPORT_SYMBOL_GPL(wcd_clsh_ctrl_get_state);
struct wcd_clsh_ctrl *wcd_clsh_ctrl_alloc(struct snd_soc_component *comp,
int version)
{
struct wcd_clsh_ctrl *ctrl;
ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
if (!ctrl)
return ERR_PTR(-ENOMEM);
ctrl->state = WCD_CLSH_STATE_IDLE;
ctrl->comp = comp;
ctrl->codec_version = version;
return ctrl;
}
EXPORT_SYMBOL_GPL(wcd_clsh_ctrl_alloc);
void wcd_clsh_ctrl_free(struct wcd_clsh_ctrl *ctrl)
{
kfree(ctrl);
}
EXPORT_SYMBOL_GPL(wcd_clsh_ctrl_free);
MODULE_DESCRIPTION("WCD93XX Class-H driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wcd-clsh-v2.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* es8328.c -- ES8328 ALSA SoC Audio driver
*
* Copyright 2014 Sutajio Ko-Usagi PTE LTD
*
* Author: Sean Cross <[email protected]>
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/of_device.h>
#include <linux/module.h>
#include <linux/pm.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/regulator/consumer.h>
#include <sound/core.h>
#include <sound/initval.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include "es8328.h"
static const unsigned int rates_12288[] = {
8000, 12000, 16000, 24000, 32000, 48000, 96000,
};
static const int ratios_12288[] = {
10, 7, 6, 4, 3, 2, 0,
};
static const struct snd_pcm_hw_constraint_list constraints_12288 = {
.count = ARRAY_SIZE(rates_12288),
.list = rates_12288,
};
static const unsigned int rates_11289[] = {
8018, 11025, 22050, 44100, 88200,
};
static const int ratios_11289[] = {
9, 7, 4, 2, 0,
};
static const struct snd_pcm_hw_constraint_list constraints_11289 = {
.count = ARRAY_SIZE(rates_11289),
.list = rates_11289,
};
/* regulator supplies for sgtl5000, VDDD is an optional external supply */
enum sgtl5000_regulator_supplies {
DVDD,
AVDD,
PVDD,
HPVDD,
ES8328_SUPPLY_NUM
};
/* vddd is optional supply */
static const char * const supply_names[ES8328_SUPPLY_NUM] = {
"DVDD",
"AVDD",
"PVDD",
"HPVDD",
};
#define ES8328_RATES (SNDRV_PCM_RATE_192000 | \
SNDRV_PCM_RATE_96000 | \
SNDRV_PCM_RATE_88200 | \
SNDRV_PCM_RATE_8000_48000)
#define ES8328_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S18_3LE | \
SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE)
struct es8328_priv {
struct regmap *regmap;
struct clk *clk;
int playback_fs;
bool deemph;
int mclkdiv2;
const struct snd_pcm_hw_constraint_list *sysclk_constraints;
const int *mclk_ratios;
bool provider;
struct regulator_bulk_data supplies[ES8328_SUPPLY_NUM];
};
/*
* ES8328 Controls
*/
static const char * const adcpol_txt[] = {"Normal", "L Invert", "R Invert",
"L + R Invert"};
static SOC_ENUM_SINGLE_DECL(adcpol,
ES8328_ADCCONTROL6, 6, adcpol_txt);
static const DECLARE_TLV_DB_SCALE(play_tlv, -3000, 100, 0);
static const DECLARE_TLV_DB_SCALE(dac_adc_tlv, -9600, 50, 0);
static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 300, 0);
static const struct {
int rate;
unsigned int val;
} deemph_settings[] = {
{ 0, ES8328_DACCONTROL6_DEEMPH_OFF },
{ 32000, ES8328_DACCONTROL6_DEEMPH_32k },
{ 44100, ES8328_DACCONTROL6_DEEMPH_44_1k },
{ 48000, ES8328_DACCONTROL6_DEEMPH_48k },
};
static int es8328_set_deemph(struct snd_soc_component *component)
{
struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
int val, i, best;
/*
* If we're using deemphasis select the nearest available sample
* rate.
*/
if (es8328->deemph) {
best = 0;
for (i = 1; i < ARRAY_SIZE(deemph_settings); i++) {
if (abs(deemph_settings[i].rate - es8328->playback_fs) <
abs(deemph_settings[best].rate - es8328->playback_fs))
best = i;
}
val = deemph_settings[best].val;
} else {
val = ES8328_DACCONTROL6_DEEMPH_OFF;
}
dev_dbg(component->dev, "Set deemphasis %d\n", val);
return snd_soc_component_update_bits(component, ES8328_DACCONTROL6,
ES8328_DACCONTROL6_DEEMPH_MASK, val);
}
static int es8328_get_deemph(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = es8328->deemph;
return 0;
}
static int es8328_put_deemph(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
unsigned int deemph = ucontrol->value.integer.value[0];
int ret;
if (deemph > 1)
return -EINVAL;
if (es8328->deemph == deemph)
return 0;
ret = es8328_set_deemph(component);
if (ret < 0)
return ret;
es8328->deemph = deemph;
return 1;
}
static const struct snd_kcontrol_new es8328_snd_controls[] = {
SOC_DOUBLE_R_TLV("Capture Digital Volume",
ES8328_ADCCONTROL8, ES8328_ADCCONTROL9,
0, 0xc0, 1, dac_adc_tlv),
SOC_SINGLE("Capture ZC Switch", ES8328_ADCCONTROL7, 6, 1, 0),
SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
es8328_get_deemph, es8328_put_deemph),
SOC_ENUM("Capture Polarity", adcpol),
SOC_SINGLE_TLV("Left Mixer Left Bypass Volume",
ES8328_DACCONTROL17, 3, 7, 1, bypass_tlv),
SOC_SINGLE_TLV("Left Mixer Right Bypass Volume",
ES8328_DACCONTROL19, 3, 7, 1, bypass_tlv),
SOC_SINGLE_TLV("Right Mixer Left Bypass Volume",
ES8328_DACCONTROL18, 3, 7, 1, bypass_tlv),
SOC_SINGLE_TLV("Right Mixer Right Bypass Volume",
ES8328_DACCONTROL20, 3, 7, 1, bypass_tlv),
SOC_DOUBLE_R_TLV("PCM Volume",
ES8328_LDACVOL, ES8328_RDACVOL,
0, ES8328_DACVOL_MAX, 1, dac_adc_tlv),
SOC_DOUBLE_R_TLV("Output 1 Playback Volume",
ES8328_LOUT1VOL, ES8328_ROUT1VOL,
0, ES8328_OUT1VOL_MAX, 0, play_tlv),
SOC_DOUBLE_R_TLV("Output 2 Playback Volume",
ES8328_LOUT2VOL, ES8328_ROUT2VOL,
0, ES8328_OUT2VOL_MAX, 0, play_tlv),
SOC_DOUBLE_TLV("Mic PGA Volume", ES8328_ADCCONTROL1,
4, 0, 8, 0, mic_tlv),
};
/*
* DAPM Controls
*/
static const char * const es8328_line_texts[] = {
"Line 1", "Line 2", "PGA", "Differential"};
static const struct soc_enum es8328_lline_enum =
SOC_ENUM_SINGLE(ES8328_DACCONTROL16, 3,
ARRAY_SIZE(es8328_line_texts),
es8328_line_texts);
static const struct snd_kcontrol_new es8328_left_line_controls =
SOC_DAPM_ENUM("Route", es8328_lline_enum);
static const struct soc_enum es8328_rline_enum =
SOC_ENUM_SINGLE(ES8328_DACCONTROL16, 0,
ARRAY_SIZE(es8328_line_texts),
es8328_line_texts);
static const struct snd_kcontrol_new es8328_right_line_controls =
SOC_DAPM_ENUM("Route", es8328_rline_enum);
/* Left Mixer */
static const struct snd_kcontrol_new es8328_left_mixer_controls[] = {
SOC_DAPM_SINGLE("Playback Switch", ES8328_DACCONTROL17, 7, 1, 0),
SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL17, 6, 1, 0),
SOC_DAPM_SINGLE("Right Playback Switch", ES8328_DACCONTROL18, 7, 1, 0),
SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL18, 6, 1, 0),
};
/* Right Mixer */
static const struct snd_kcontrol_new es8328_right_mixer_controls[] = {
SOC_DAPM_SINGLE("Left Playback Switch", ES8328_DACCONTROL19, 7, 1, 0),
SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL19, 6, 1, 0),
SOC_DAPM_SINGLE("Playback Switch", ES8328_DACCONTROL20, 7, 1, 0),
SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL20, 6, 1, 0),
};
static const char * const es8328_pga_sel[] = {
"Line 1", "Line 2", "Line 3", "Differential"};
/* Left PGA Mux */
static const struct soc_enum es8328_lpga_enum =
SOC_ENUM_SINGLE(ES8328_ADCCONTROL2, 6,
ARRAY_SIZE(es8328_pga_sel),
es8328_pga_sel);
static const struct snd_kcontrol_new es8328_left_pga_controls =
SOC_DAPM_ENUM("Route", es8328_lpga_enum);
/* Right PGA Mux */
static const struct soc_enum es8328_rpga_enum =
SOC_ENUM_SINGLE(ES8328_ADCCONTROL2, 4,
ARRAY_SIZE(es8328_pga_sel),
es8328_pga_sel);
static const struct snd_kcontrol_new es8328_right_pga_controls =
SOC_DAPM_ENUM("Route", es8328_rpga_enum);
/* Differential Mux */
static const char * const es8328_diff_sel[] = {"Line 1", "Line 2"};
static SOC_ENUM_SINGLE_DECL(diffmux,
ES8328_ADCCONTROL3, 7, es8328_diff_sel);
static const struct snd_kcontrol_new es8328_diffmux_controls =
SOC_DAPM_ENUM("Route", diffmux);
/* Mono ADC Mux */
static const char * const es8328_mono_mux[] = {"Stereo", "Mono (Left)",
"Mono (Right)", "Digital Mono"};
static SOC_ENUM_SINGLE_DECL(monomux,
ES8328_ADCCONTROL3, 3, es8328_mono_mux);
static const struct snd_kcontrol_new es8328_monomux_controls =
SOC_DAPM_ENUM("Route", monomux);
static const struct snd_soc_dapm_widget es8328_dapm_widgets[] = {
SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
&es8328_diffmux_controls),
SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
&es8328_monomux_controls),
SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
&es8328_monomux_controls),
SND_SOC_DAPM_MUX("Left PGA Mux", ES8328_ADCPOWER,
ES8328_ADCPOWER_AINL_OFF, 1,
&es8328_left_pga_controls),
SND_SOC_DAPM_MUX("Right PGA Mux", ES8328_ADCPOWER,
ES8328_ADCPOWER_AINR_OFF, 1,
&es8328_right_pga_controls),
SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
&es8328_left_line_controls),
SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
&es8328_right_line_controls),
SND_SOC_DAPM_ADC("Right ADC", "Right Capture", ES8328_ADCPOWER,
ES8328_ADCPOWER_ADCR_OFF, 1),
SND_SOC_DAPM_ADC("Left ADC", "Left Capture", ES8328_ADCPOWER,
ES8328_ADCPOWER_ADCL_OFF, 1),
SND_SOC_DAPM_SUPPLY("Mic Bias", ES8328_ADCPOWER,
ES8328_ADCPOWER_MIC_BIAS_OFF, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("Mic Bias Gen", ES8328_ADCPOWER,
ES8328_ADCPOWER_ADC_BIAS_GEN_OFF, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC STM", ES8328_CHIPPOWER,
ES8328_CHIPPOWER_DACSTM_RESET, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC STM", ES8328_CHIPPOWER,
ES8328_CHIPPOWER_ADCSTM_RESET, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC DIG", ES8328_CHIPPOWER,
ES8328_CHIPPOWER_DACDIG_OFF, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC DIG", ES8328_CHIPPOWER,
ES8328_CHIPPOWER_ADCDIG_OFF, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC DLL", ES8328_CHIPPOWER,
ES8328_CHIPPOWER_DACDLL_OFF, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC DLL", ES8328_CHIPPOWER,
ES8328_CHIPPOWER_ADCDLL_OFF, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC Vref", ES8328_CHIPPOWER,
ES8328_CHIPPOWER_ADCVREF_OFF, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC Vref", ES8328_CHIPPOWER,
ES8328_CHIPPOWER_DACVREF_OFF, 1, NULL, 0),
SND_SOC_DAPM_DAC("Right DAC", "Right Playback", ES8328_DACPOWER,
ES8328_DACPOWER_RDAC_OFF, 1),
SND_SOC_DAPM_DAC("Left DAC", "Left Playback", ES8328_DACPOWER,
ES8328_DACPOWER_LDAC_OFF, 1),
SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
&es8328_left_mixer_controls[0],
ARRAY_SIZE(es8328_left_mixer_controls)),
SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
&es8328_right_mixer_controls[0],
ARRAY_SIZE(es8328_right_mixer_controls)),
SND_SOC_DAPM_PGA("Right Out 2", ES8328_DACPOWER,
ES8328_DACPOWER_ROUT2_ON, 0, NULL, 0),
SND_SOC_DAPM_PGA("Left Out 2", ES8328_DACPOWER,
ES8328_DACPOWER_LOUT2_ON, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Out 1", ES8328_DACPOWER,
ES8328_DACPOWER_ROUT1_ON, 0, NULL, 0),
SND_SOC_DAPM_PGA("Left Out 1", ES8328_DACPOWER,
ES8328_DACPOWER_LOUT1_ON, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("LOUT1"),
SND_SOC_DAPM_OUTPUT("ROUT1"),
SND_SOC_DAPM_OUTPUT("LOUT2"),
SND_SOC_DAPM_OUTPUT("ROUT2"),
SND_SOC_DAPM_INPUT("LINPUT1"),
SND_SOC_DAPM_INPUT("LINPUT2"),
SND_SOC_DAPM_INPUT("RINPUT1"),
SND_SOC_DAPM_INPUT("RINPUT2"),
};
static const struct snd_soc_dapm_route es8328_dapm_routes[] = {
{ "Left Line Mux", "Line 1", "LINPUT1" },
{ "Left Line Mux", "Line 2", "LINPUT2" },
{ "Left Line Mux", "PGA", "Left PGA Mux" },
{ "Left Line Mux", "Differential", "Differential Mux" },
{ "Right Line Mux", "Line 1", "RINPUT1" },
{ "Right Line Mux", "Line 2", "RINPUT2" },
{ "Right Line Mux", "PGA", "Right PGA Mux" },
{ "Right Line Mux", "Differential", "Differential Mux" },
{ "Left PGA Mux", "Line 1", "LINPUT1" },
{ "Left PGA Mux", "Line 2", "LINPUT2" },
{ "Left PGA Mux", "Differential", "Differential Mux" },
{ "Right PGA Mux", "Line 1", "RINPUT1" },
{ "Right PGA Mux", "Line 2", "RINPUT2" },
{ "Right PGA Mux", "Differential", "Differential Mux" },
{ "Differential Mux", "Line 1", "LINPUT1" },
{ "Differential Mux", "Line 1", "RINPUT1" },
{ "Differential Mux", "Line 2", "LINPUT2" },
{ "Differential Mux", "Line 2", "RINPUT2" },
{ "Left ADC Mux", "Stereo", "Left PGA Mux" },
{ "Left ADC Mux", "Mono (Left)", "Left PGA Mux" },
{ "Left ADC Mux", "Digital Mono", "Left PGA Mux" },
{ "Right ADC Mux", "Stereo", "Right PGA Mux" },
{ "Right ADC Mux", "Mono (Right)", "Right PGA Mux" },
{ "Right ADC Mux", "Digital Mono", "Right PGA Mux" },
{ "Left ADC", NULL, "Left ADC Mux" },
{ "Right ADC", NULL, "Right ADC Mux" },
{ "ADC DIG", NULL, "ADC STM" },
{ "ADC DIG", NULL, "ADC Vref" },
{ "ADC DIG", NULL, "ADC DLL" },
{ "Left ADC", NULL, "ADC DIG" },
{ "Right ADC", NULL, "ADC DIG" },
{ "Mic Bias", NULL, "Mic Bias Gen" },
{ "Left Line Mux", "Line 1", "LINPUT1" },
{ "Left Line Mux", "Line 2", "LINPUT2" },
{ "Left Line Mux", "PGA", "Left PGA Mux" },
{ "Left Line Mux", "Differential", "Differential Mux" },
{ "Right Line Mux", "Line 1", "RINPUT1" },
{ "Right Line Mux", "Line 2", "RINPUT2" },
{ "Right Line Mux", "PGA", "Right PGA Mux" },
{ "Right Line Mux", "Differential", "Differential Mux" },
{ "Left Out 1", NULL, "Left DAC" },
{ "Right Out 1", NULL, "Right DAC" },
{ "Left Out 2", NULL, "Left DAC" },
{ "Right Out 2", NULL, "Right DAC" },
{ "Left Mixer", "Playback Switch", "Left DAC" },
{ "Left Mixer", "Left Bypass Switch", "Left Line Mux" },
{ "Left Mixer", "Right Playback Switch", "Right DAC" },
{ "Left Mixer", "Right Bypass Switch", "Right Line Mux" },
{ "Right Mixer", "Left Playback Switch", "Left DAC" },
{ "Right Mixer", "Left Bypass Switch", "Left Line Mux" },
{ "Right Mixer", "Playback Switch", "Right DAC" },
{ "Right Mixer", "Right Bypass Switch", "Right Line Mux" },
{ "DAC DIG", NULL, "DAC STM" },
{ "DAC DIG", NULL, "DAC Vref" },
{ "DAC DIG", NULL, "DAC DLL" },
{ "Left DAC", NULL, "DAC DIG" },
{ "Right DAC", NULL, "DAC DIG" },
{ "Left Out 1", NULL, "Left Mixer" },
{ "LOUT1", NULL, "Left Out 1" },
{ "Right Out 1", NULL, "Right Mixer" },
{ "ROUT1", NULL, "Right Out 1" },
{ "Left Out 2", NULL, "Left Mixer" },
{ "LOUT2", NULL, "Left Out 2" },
{ "Right Out 2", NULL, "Right Mixer" },
{ "ROUT2", NULL, "Right Out 2" },
};
static int es8328_mute(struct snd_soc_dai *dai, int mute, int direction)
{
return snd_soc_component_update_bits(dai->component, ES8328_DACCONTROL3,
ES8328_DACCONTROL3_DACMUTE,
mute ? ES8328_DACCONTROL3_DACMUTE : 0);
}
static int es8328_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
if (es8328->provider && es8328->sysclk_constraints)
snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
es8328->sysclk_constraints);
return 0;
}
static int es8328_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
int i;
int reg;
int wl;
int ratio;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
reg = ES8328_DACCONTROL2;
else
reg = ES8328_ADCCONTROL5;
if (es8328->provider) {
if (!es8328->sysclk_constraints) {
dev_err(component->dev, "No MCLK configured\n");
return -EINVAL;
}
for (i = 0; i < es8328->sysclk_constraints->count; i++)
if (es8328->sysclk_constraints->list[i] ==
params_rate(params))
break;
if (i == es8328->sysclk_constraints->count) {
dev_err(component->dev,
"LRCLK %d unsupported with current clock\n",
params_rate(params));
return -EINVAL;
}
ratio = es8328->mclk_ratios[i];
} else {
ratio = 0;
es8328->mclkdiv2 = 0;
}
snd_soc_component_update_bits(component, ES8328_MASTERMODE,
ES8328_MASTERMODE_MCLKDIV2,
es8328->mclkdiv2 ? ES8328_MASTERMODE_MCLKDIV2 : 0);
switch (params_width(params)) {
case 16:
wl = 3;
break;
case 18:
wl = 2;
break;
case 20:
wl = 1;
break;
case 24:
wl = 0;
break;
case 32:
wl = 4;
break;
default:
return -EINVAL;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
snd_soc_component_update_bits(component, ES8328_DACCONTROL1,
ES8328_DACCONTROL1_DACWL_MASK,
wl << ES8328_DACCONTROL1_DACWL_SHIFT);
es8328->playback_fs = params_rate(params);
es8328_set_deemph(component);
} else
snd_soc_component_update_bits(component, ES8328_ADCCONTROL4,
ES8328_ADCCONTROL4_ADCWL_MASK,
wl << ES8328_ADCCONTROL4_ADCWL_SHIFT);
return snd_soc_component_update_bits(component, reg, ES8328_RATEMASK, ratio);
}
static int es8328_set_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
int mclkdiv2 = 0;
switch (freq) {
case 0:
es8328->sysclk_constraints = NULL;
es8328->mclk_ratios = NULL;
break;
case 22579200:
mclkdiv2 = 1;
fallthrough;
case 11289600:
es8328->sysclk_constraints = &constraints_11289;
es8328->mclk_ratios = ratios_11289;
break;
case 24576000:
mclkdiv2 = 1;
fallthrough;
case 12288000:
es8328->sysclk_constraints = &constraints_12288;
es8328->mclk_ratios = ratios_12288;
break;
default:
return -EINVAL;
}
es8328->mclkdiv2 = mclkdiv2;
return 0;
}
static int es8328_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
u8 dac_mode = 0;
u8 adc_mode = 0;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
/* Master serial port mode, with BCLK generated automatically */
snd_soc_component_update_bits(component, ES8328_MASTERMODE,
ES8328_MASTERMODE_MSC,
ES8328_MASTERMODE_MSC);
es8328->provider = true;
break;
case SND_SOC_DAIFMT_CBC_CFC:
/* Slave serial port mode */
snd_soc_component_update_bits(component, ES8328_MASTERMODE,
ES8328_MASTERMODE_MSC, 0);
es8328->provider = false;
break;
default:
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
dac_mode |= ES8328_DACCONTROL1_DACFORMAT_I2S;
adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_I2S;
break;
case SND_SOC_DAIFMT_RIGHT_J:
dac_mode |= ES8328_DACCONTROL1_DACFORMAT_RJUST;
adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_RJUST;
break;
case SND_SOC_DAIFMT_LEFT_J:
dac_mode |= ES8328_DACCONTROL1_DACFORMAT_LJUST;
adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_LJUST;
break;
default:
return -EINVAL;
}
/* clock inversion */
if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF)
return -EINVAL;
snd_soc_component_update_bits(component, ES8328_DACCONTROL1,
ES8328_DACCONTROL1_DACFORMAT_MASK, dac_mode);
snd_soc_component_update_bits(component, ES8328_ADCCONTROL4,
ES8328_ADCCONTROL4_ADCFORMAT_MASK, adc_mode);
return 0;
}
static int es8328_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
/* VREF, VMID=2x50k, digital enabled */
snd_soc_component_write(component, ES8328_CHIPPOWER, 0);
snd_soc_component_update_bits(component, ES8328_CONTROL1,
ES8328_CONTROL1_VMIDSEL_MASK |
ES8328_CONTROL1_ENREF,
ES8328_CONTROL1_VMIDSEL_50k |
ES8328_CONTROL1_ENREF);
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
snd_soc_component_update_bits(component, ES8328_CONTROL1,
ES8328_CONTROL1_VMIDSEL_MASK |
ES8328_CONTROL1_ENREF,
ES8328_CONTROL1_VMIDSEL_5k |
ES8328_CONTROL1_ENREF);
/* Charge caps */
msleep(100);
}
snd_soc_component_write(component, ES8328_CONTROL2,
ES8328_CONTROL2_OVERCURRENT_ON |
ES8328_CONTROL2_THERMAL_SHUTDOWN_ON);
/* VREF, VMID=2*500k, digital stopped */
snd_soc_component_update_bits(component, ES8328_CONTROL1,
ES8328_CONTROL1_VMIDSEL_MASK |
ES8328_CONTROL1_ENREF,
ES8328_CONTROL1_VMIDSEL_500k |
ES8328_CONTROL1_ENREF);
break;
case SND_SOC_BIAS_OFF:
snd_soc_component_update_bits(component, ES8328_CONTROL1,
ES8328_CONTROL1_VMIDSEL_MASK |
ES8328_CONTROL1_ENREF,
0);
break;
}
return 0;
}
static const struct snd_soc_dai_ops es8328_dai_ops = {
.startup = es8328_startup,
.hw_params = es8328_hw_params,
.mute_stream = es8328_mute,
.set_sysclk = es8328_set_sysclk,
.set_fmt = es8328_set_dai_fmt,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver es8328_dai = {
.name = "es8328-hifi-analog",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = ES8328_RATES,
.formats = ES8328_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = ES8328_RATES,
.formats = ES8328_FORMATS,
},
.ops = &es8328_dai_ops,
.symmetric_rate = 1,
};
static int es8328_suspend(struct snd_soc_component *component)
{
struct es8328_priv *es8328;
int ret;
es8328 = snd_soc_component_get_drvdata(component);
clk_disable_unprepare(es8328->clk);
ret = regulator_bulk_disable(ARRAY_SIZE(es8328->supplies),
es8328->supplies);
if (ret) {
dev_err(component->dev, "unable to disable regulators\n");
return ret;
}
return 0;
}
static int es8328_resume(struct snd_soc_component *component)
{
struct regmap *regmap = dev_get_regmap(component->dev, NULL);
struct es8328_priv *es8328;
int ret;
es8328 = snd_soc_component_get_drvdata(component);
ret = clk_prepare_enable(es8328->clk);
if (ret) {
dev_err(component->dev, "unable to enable clock\n");
return ret;
}
ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies),
es8328->supplies);
if (ret) {
dev_err(component->dev, "unable to enable regulators\n");
return ret;
}
regcache_mark_dirty(regmap);
ret = regcache_sync(regmap);
if (ret) {
dev_err(component->dev, "unable to sync regcache\n");
return ret;
}
return 0;
}
static int es8328_component_probe(struct snd_soc_component *component)
{
struct es8328_priv *es8328;
int ret;
es8328 = snd_soc_component_get_drvdata(component);
ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies),
es8328->supplies);
if (ret) {
dev_err(component->dev, "unable to enable regulators\n");
return ret;
}
/* Setup clocks */
es8328->clk = devm_clk_get(component->dev, NULL);
if (IS_ERR(es8328->clk)) {
dev_err(component->dev, "codec clock missing or invalid\n");
ret = PTR_ERR(es8328->clk);
goto clk_fail;
}
ret = clk_prepare_enable(es8328->clk);
if (ret) {
dev_err(component->dev, "unable to prepare codec clk\n");
goto clk_fail;
}
return 0;
clk_fail:
regulator_bulk_disable(ARRAY_SIZE(es8328->supplies),
es8328->supplies);
return ret;
}
static void es8328_remove(struct snd_soc_component *component)
{
struct es8328_priv *es8328;
es8328 = snd_soc_component_get_drvdata(component);
clk_disable_unprepare(es8328->clk);
regulator_bulk_disable(ARRAY_SIZE(es8328->supplies),
es8328->supplies);
}
const struct regmap_config es8328_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = ES8328_REG_MAX,
.cache_type = REGCACHE_MAPLE,
.use_single_read = true,
.use_single_write = true,
};
EXPORT_SYMBOL_GPL(es8328_regmap_config);
static const struct snd_soc_component_driver es8328_component_driver = {
.probe = es8328_component_probe,
.remove = es8328_remove,
.suspend = es8328_suspend,
.resume = es8328_resume,
.set_bias_level = es8328_set_bias_level,
.controls = es8328_snd_controls,
.num_controls = ARRAY_SIZE(es8328_snd_controls),
.dapm_widgets = es8328_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(es8328_dapm_widgets),
.dapm_routes = es8328_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(es8328_dapm_routes),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
int es8328_probe(struct device *dev, struct regmap *regmap)
{
struct es8328_priv *es8328;
int ret;
int i;
if (IS_ERR(regmap))
return PTR_ERR(regmap);
es8328 = devm_kzalloc(dev, sizeof(*es8328), GFP_KERNEL);
if (es8328 == NULL)
return -ENOMEM;
es8328->regmap = regmap;
for (i = 0; i < ARRAY_SIZE(es8328->supplies); i++)
es8328->supplies[i].supply = supply_names[i];
ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(es8328->supplies),
es8328->supplies);
if (ret) {
dev_err(dev, "unable to get regulators\n");
return ret;
}
dev_set_drvdata(dev, es8328);
return devm_snd_soc_register_component(dev,
&es8328_component_driver, &es8328_dai, 1);
}
EXPORT_SYMBOL_GPL(es8328_probe);
MODULE_DESCRIPTION("ASoC ES8328 driver");
MODULE_AUTHOR("Sean Cross <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/es8328.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* TDA7419 audio processor driver
*
* Copyright 2018 Konsulko Group
*
* Author: Matt Porter <[email protected]>
*/
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/control.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#define TDA7419_MAIN_SRC_REG 0x00
#define TDA7419_LOUDNESS_REG 0x01
#define TDA7419_MUTE_CLK_REG 0x02
#define TDA7419_VOLUME_REG 0x03
#define TDA7419_TREBLE_REG 0x04
#define TDA7419_MIDDLE_REG 0x05
#define TDA7419_BASS_REG 0x06
#define TDA7419_SECOND_SRC_REG 0x07
#define TDA7419_SUB_MID_BASS_REG 0x08
#define TDA7419_MIXING_GAIN_REG 0x09
#define TDA7419_ATTENUATOR_LF_REG 0x0a
#define TDA7419_ATTENUATOR_RF_REG 0x0b
#define TDA7419_ATTENUATOR_LR_REG 0x0c
#define TDA7419_ATTENUATOR_RR_REG 0x0d
#define TDA7419_MIXING_LEVEL_REG 0x0e
#define TDA7419_ATTENUATOR_SUB_REG 0x0f
#define TDA7419_SA_CLK_AC_REG 0x10
#define TDA7419_TESTING_REG 0x11
#define TDA7419_MAIN_SRC_SEL 0
#define TDA7419_MAIN_SRC_GAIN 3
#define TDA7419_MAIN_SRC_AUTOZERO 7
#define TDA7419_LOUDNESS_ATTEN 0
#define TDA7419_LOUDNESS_CENTER_FREQ 4
#define TDA7419_LOUDNESS_BOOST 6
#define TDA7419_LOUDNESS_SOFT_STEP 7
#define TDA7419_VOLUME_SOFT_STEP 7
#define TDA7419_SOFT_MUTE 0
#define TDA7419_MUTE_INFLUENCE 1
#define TDA7419_SOFT_MUTE_TIME 2
#define TDA7419_SOFT_STEP_TIME 4
#define TDA7419_CLK_FAST_MODE 7
#define TDA7419_TREBLE_CENTER_FREQ 5
#define TDA7419_REF_OUT_SELECT 7
#define TDA7419_MIDDLE_Q_FACTOR 5
#define TDA7419_MIDDLE_SOFT_STEP 7
#define TDA7419_BASS_Q_FACTOR 5
#define TDA7419_BASS_SOFT_STEP 7
#define TDA7419_SECOND_SRC_SEL 0
#define TDA7419_SECOND_SRC_GAIN 3
#define TDA7419_REAR_SPKR_SRC 7
#define TDA7419_SUB_CUT_OFF_FREQ 0
#define TDA7419_MIDDLE_CENTER_FREQ 2
#define TDA7419_BASS_CENTER_FREQ 4
#define TDA7419_BASS_DC_MODE 6
#define TDA7419_SMOOTHING_FILTER 7
#define TDA7419_MIX_LF 0
#define TDA7419_MIX_RF 1
#define TDA7419_MIX_ENABLE 2
#define TDA7419_SUB_ENABLE 3
#define TDA7419_HPF_GAIN 4
#define TDA7419_SA_Q_FACTOR 0
#define TDA7419_RESET_MODE 1
#define TDA7419_SA_SOURCE 2
#define TDA7419_SA_RUN 3
#define TDA7419_RESET 4
#define TDA7419_CLK_SOURCE 5
#define TDA7419_COUPLING_MODE 6
struct tda7419_data {
struct regmap *regmap;
};
static bool tda7419_readable_reg(struct device *dev, unsigned int reg)
{
return false;
}
static const struct reg_default tda7419_regmap_defaults[] = {
{ TDA7419_MAIN_SRC_REG, 0xfe },
{ TDA7419_LOUDNESS_REG, 0xfe },
{ TDA7419_MUTE_CLK_REG, 0xfe },
{ TDA7419_VOLUME_REG, 0xfe },
{ TDA7419_TREBLE_REG, 0xfe },
{ TDA7419_MIDDLE_REG, 0xfe },
{ TDA7419_BASS_REG, 0xfe },
{ TDA7419_SECOND_SRC_REG, 0xfe },
{ TDA7419_SUB_MID_BASS_REG, 0xfe },
{ TDA7419_MIXING_GAIN_REG, 0xfe },
{ TDA7419_ATTENUATOR_LF_REG, 0xfe },
{ TDA7419_ATTENUATOR_RF_REG, 0xfe },
{ TDA7419_ATTENUATOR_LR_REG, 0xfe },
{ TDA7419_ATTENUATOR_RR_REG, 0xfe },
{ TDA7419_MIXING_LEVEL_REG, 0xfe },
{ TDA7419_ATTENUATOR_SUB_REG, 0xfe },
{ TDA7419_SA_CLK_AC_REG, 0xfe },
{ TDA7419_TESTING_REG, 0xfe },
};
static const struct regmap_config tda7419_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = TDA7419_TESTING_REG,
.cache_type = REGCACHE_RBTREE,
.readable_reg = tda7419_readable_reg,
.reg_defaults = tda7419_regmap_defaults,
.num_reg_defaults = ARRAY_SIZE(tda7419_regmap_defaults),
};
struct tda7419_vol_control {
int min, max;
unsigned int reg, rreg, mask, thresh;
unsigned int invert:1;
};
static inline bool tda7419_vol_is_stereo(struct tda7419_vol_control *tvc)
{
if (tvc->reg == tvc->rreg)
return false;
return true;
}
static int tda7419_vol_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
struct tda7419_vol_control *tvc =
(struct tda7419_vol_control *)kcontrol->private_value;
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = tda7419_vol_is_stereo(tvc) ? 2 : 1;
uinfo->value.integer.min = tvc->min;
uinfo->value.integer.max = tvc->max;
return 0;
}
static inline int tda7419_vol_get_value(int val, unsigned int mask,
int min, int thresh,
unsigned int invert)
{
val &= mask;
if (val < thresh) {
if (invert)
val = 0 - val;
} else if (val > thresh) {
if (invert)
val = val - thresh;
else
val = thresh - val;
}
if (val < min)
val = min;
return val;
}
static int tda7419_vol_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct tda7419_vol_control *tvc =
(struct tda7419_vol_control *)kcontrol->private_value;
unsigned int reg = tvc->reg;
unsigned int rreg = tvc->rreg;
unsigned int mask = tvc->mask;
int min = tvc->min;
int thresh = tvc->thresh;
unsigned int invert = tvc->invert;
int val;
val = snd_soc_component_read(component, reg);
ucontrol->value.integer.value[0] =
tda7419_vol_get_value(val, mask, min, thresh, invert);
if (tda7419_vol_is_stereo(tvc)) {
val = snd_soc_component_read(component, rreg);
ucontrol->value.integer.value[1] =
tda7419_vol_get_value(val, mask, min, thresh, invert);
}
return 0;
}
static inline int tda7419_vol_put_value(int val, int thresh,
unsigned int invert)
{
if (val < 0) {
if (invert)
val = abs(val);
else
val = thresh - val;
} else if ((val > 0) && invert) {
val += thresh;
}
return val;
}
static int tda7419_vol_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_kcontrol_chip(kcontrol);
struct tda7419_vol_control *tvc =
(struct tda7419_vol_control *)kcontrol->private_value;
unsigned int reg = tvc->reg;
unsigned int rreg = tvc->rreg;
unsigned int mask = tvc->mask;
int thresh = tvc->thresh;
unsigned int invert = tvc->invert;
int val;
int ret;
val = tda7419_vol_put_value(ucontrol->value.integer.value[0],
thresh, invert);
ret = snd_soc_component_update_bits(component, reg,
mask, val);
if (ret < 0)
return ret;
if (tda7419_vol_is_stereo(tvc)) {
val = tda7419_vol_put_value(ucontrol->value.integer.value[1],
thresh, invert);
ret = snd_soc_component_update_bits(component, rreg,
mask, val);
}
return ret;
}
#define TDA7419_SINGLE_VALUE(xreg, xmask, xmin, xmax, xthresh, xinvert) \
((unsigned long)&(struct tda7419_vol_control) \
{.reg = xreg, .rreg = xreg, .mask = xmask, .min = xmin, \
.max = xmax, .thresh = xthresh, .invert = xinvert})
#define TDA7419_DOUBLE_R_VALUE(xregl, xregr, xmask, xmin, xmax, xthresh, \
xinvert) \
((unsigned long)&(struct tda7419_vol_control) \
{.reg = xregl, .rreg = xregr, .mask = xmask, .min = xmin, \
.max = xmax, .thresh = xthresh, .invert = xinvert})
#define TDA7419_SINGLE_TLV(xname, xreg, xmask, xmin, xmax, xthresh, \
xinvert, xtlv_array) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
.name = xname, \
.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
SNDRV_CTL_ELEM_ACCESS_READWRITE, \
.tlv.p = (xtlv_array), \
.info = tda7419_vol_info, \
.get = tda7419_vol_get, \
.put = tda7419_vol_put, \
.private_value = TDA7419_SINGLE_VALUE(xreg, xmask, xmin, \
xmax, xthresh, xinvert), \
}
#define TDA7419_DOUBLE_R_TLV(xname, xregl, xregr, xmask, xmin, xmax, \
xthresh, xinvert, xtlv_array) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
.name = xname, \
.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
SNDRV_CTL_ELEM_ACCESS_READWRITE, \
.tlv.p = (xtlv_array), \
.info = tda7419_vol_info, \
.get = tda7419_vol_get, \
.put = tda7419_vol_put, \
.private_value = TDA7419_DOUBLE_R_VALUE(xregl, xregr, xmask, \
xmin, xmax, xthresh, \
xinvert), \
}
static const char * const enum_src_sel[] = {
"QD", "SE1", "SE2", "SE3", "SE", "Mute", "Mute", "Mute"};
static SOC_ENUM_SINGLE_DECL(soc_enum_main_src_sel,
TDA7419_MAIN_SRC_REG, TDA7419_MAIN_SRC_SEL, enum_src_sel);
static const struct snd_kcontrol_new soc_mux_main_src_sel =
SOC_DAPM_ENUM("Main Source Select", soc_enum_main_src_sel);
static DECLARE_TLV_DB_SCALE(tlv_src_gain, 0, 100, 0);
static DECLARE_TLV_DB_SCALE(tlv_loudness_atten, -1500, 100, 0);
static const char * const enum_loudness_center_freq[] = {
"Flat", "400 Hz", "800 Hz", "2400 Hz"};
static SOC_ENUM_SINGLE_DECL(soc_enum_loudness_center_freq,
TDA7419_LOUDNESS_REG, TDA7419_LOUDNESS_CENTER_FREQ,
enum_loudness_center_freq);
static const char * const enum_mute_influence[] = {
"Pin and IIC", "IIC"};
static SOC_ENUM_SINGLE_DECL(soc_enum_mute_influence,
TDA7419_MUTE_CLK_REG, TDA7419_MUTE_INFLUENCE, enum_mute_influence);
static const char * const enum_soft_mute_time[] = {
"0.48 ms", "0.96 ms", "123 ms", "123 ms"};
static SOC_ENUM_SINGLE_DECL(soc_enum_soft_mute_time,
TDA7419_MUTE_CLK_REG, TDA7419_SOFT_MUTE_TIME, enum_soft_mute_time);
static const char * const enum_soft_step_time[] = {
"0.160 ms", "0.321 ms", "0.642 ms", "1.28 ms",
"2.56 ms", "5.12 ms", "10.24 ms", "20.48 ms"};
static SOC_ENUM_SINGLE_DECL(soc_enum_soft_step_time,
TDA7419_MUTE_CLK_REG, TDA7419_SOFT_STEP_TIME, enum_soft_step_time);
static DECLARE_TLV_DB_SCALE(tlv_volume, -8000, 100, 1);
static const char * const enum_treble_center_freq[] = {
"10.0 kHz", "12.5 kHz", "15.0 kHz", "17.5 kHz"};
static DECLARE_TLV_DB_SCALE(tlv_filter, -1500, 100, 0);
static SOC_ENUM_SINGLE_DECL(soc_enum_treble_center_freq,
TDA7419_TREBLE_REG, TDA7419_TREBLE_CENTER_FREQ,
enum_treble_center_freq);
static const char * const enum_ref_out_select[] = {
"External Vref (4 V)", "Internal Vref (3.3 V)"};
static SOC_ENUM_SINGLE_DECL(soc_enum_ref_out_select,
TDA7419_TREBLE_REG, TDA7419_REF_OUT_SELECT, enum_ref_out_select);
static const char * const enum_middle_q_factor[] = {
"0.5", "0.75", "1.0", "1.25"};
static SOC_ENUM_SINGLE_DECL(soc_enum_middle_q_factor,
TDA7419_MIDDLE_REG, TDA7419_MIDDLE_Q_FACTOR, enum_middle_q_factor);
static const char * const enum_bass_q_factor[] = {
"1.0", "1.25", "1.5", "2.0"};
static SOC_ENUM_SINGLE_DECL(soc_enum_bass_q_factor,
TDA7419_BASS_REG, TDA7419_BASS_Q_FACTOR, enum_bass_q_factor);
static SOC_ENUM_SINGLE_DECL(soc_enum_second_src_sel,
TDA7419_SECOND_SRC_REG, TDA7419_SECOND_SRC_SEL, enum_src_sel);
static const struct snd_kcontrol_new soc_mux_second_src_sel =
SOC_DAPM_ENUM("Second Source Select", soc_enum_second_src_sel);
static const char * const enum_rear_spkr_src[] = {
"Main", "Second"};
static SOC_ENUM_SINGLE_DECL(soc_enum_rear_spkr_src,
TDA7419_SECOND_SRC_REG, TDA7419_REAR_SPKR_SRC, enum_rear_spkr_src);
static const struct snd_kcontrol_new soc_mux_rear_spkr_src =
SOC_DAPM_ENUM("Rear Speaker Source", soc_enum_rear_spkr_src);
static const char * const enum_sub_cut_off_freq[] = {
"Flat", "80 Hz", "120 Hz", "160 Hz"};
static SOC_ENUM_SINGLE_DECL(soc_enum_sub_cut_off_freq,
TDA7419_SUB_MID_BASS_REG, TDA7419_SUB_CUT_OFF_FREQ,
enum_sub_cut_off_freq);
static const char * const enum_middle_center_freq[] = {
"500 Hz", "1000 Hz", "1500 Hz", "2500 Hz"};
static SOC_ENUM_SINGLE_DECL(soc_enum_middle_center_freq,
TDA7419_SUB_MID_BASS_REG, TDA7419_MIDDLE_CENTER_FREQ,
enum_middle_center_freq);
static const char * const enum_bass_center_freq[] = {
"60 Hz", "80 Hz", "100 Hz", "200 Hz"};
static SOC_ENUM_SINGLE_DECL(soc_enum_bass_center_freq,
TDA7419_SUB_MID_BASS_REG, TDA7419_BASS_CENTER_FREQ,
enum_bass_center_freq);
static const char * const enum_sa_q_factor[] = {
"3.5", "1.75" };
static SOC_ENUM_SINGLE_DECL(soc_enum_sa_q_factor,
TDA7419_SA_CLK_AC_REG, TDA7419_SA_Q_FACTOR, enum_sa_q_factor);
static const char * const enum_reset_mode[] = {
"IIC", "Auto" };
static SOC_ENUM_SINGLE_DECL(soc_enum_reset_mode,
TDA7419_SA_CLK_AC_REG, TDA7419_RESET_MODE, enum_reset_mode);
static const char * const enum_sa_src[] = {
"Bass", "In Gain" };
static SOC_ENUM_SINGLE_DECL(soc_enum_sa_src,
TDA7419_SA_CLK_AC_REG, TDA7419_SA_SOURCE, enum_sa_src);
static const char * const enum_clk_src[] = {
"Internal", "External" };
static SOC_ENUM_SINGLE_DECL(soc_enum_clk_src,
TDA7419_SA_CLK_AC_REG, TDA7419_CLK_SOURCE, enum_clk_src);
static const char * const enum_coupling_mode[] = {
"DC Coupling (without HPF)", "AC Coupling after In Gain",
"DC Coupling (with HPF)", "AC Coupling after Bass" };
static SOC_ENUM_SINGLE_DECL(soc_enum_coupling_mode,
TDA7419_SA_CLK_AC_REG, TDA7419_COUPLING_MODE, enum_coupling_mode);
/* ASoC Controls */
static struct snd_kcontrol_new tda7419_controls[] = {
SOC_SINGLE_TLV("Main Source Capture Volume", TDA7419_MAIN_SRC_REG,
TDA7419_MAIN_SRC_GAIN, 15, 0, tlv_src_gain),
SOC_SINGLE("Main Source AutoZero Switch", TDA7419_MAIN_SRC_REG,
TDA7419_MAIN_SRC_AUTOZERO, 1, 1),
SOC_SINGLE_TLV("Loudness Playback Volume", TDA7419_LOUDNESS_REG,
TDA7419_LOUDNESS_ATTEN, 15, 1, tlv_loudness_atten),
SOC_ENUM("Loudness Center Frequency", soc_enum_loudness_center_freq),
SOC_SINGLE("Loudness High Boost Switch", TDA7419_LOUDNESS_REG,
TDA7419_LOUDNESS_BOOST, 1, 1),
SOC_SINGLE("Loudness Soft Step Switch", TDA7419_LOUDNESS_REG,
TDA7419_LOUDNESS_SOFT_STEP, 1, 1),
SOC_SINGLE("Soft Mute Switch", TDA7419_MUTE_CLK_REG, TDA7419_SOFT_MUTE, 1, 1),
SOC_ENUM("Mute Influence", soc_enum_mute_influence),
SOC_ENUM("Soft Mute Time", soc_enum_soft_mute_time),
SOC_ENUM("Soft Step Time", soc_enum_soft_step_time),
SOC_SINGLE("Clock Fast Mode Switch", TDA7419_MUTE_CLK_REG,
TDA7419_CLK_FAST_MODE, 1, 1),
TDA7419_SINGLE_TLV("Master Playback Volume", TDA7419_VOLUME_REG,
0x7f, -80, 15, 0x10, 0, tlv_volume),
SOC_SINGLE("Volume Soft Step Switch", TDA7419_VOLUME_REG,
TDA7419_VOLUME_SOFT_STEP, 1, 1),
TDA7419_SINGLE_TLV("Treble Playback Volume", TDA7419_TREBLE_REG,
0x1f, -15, 15, 0x10, 1, tlv_filter),
SOC_ENUM("Treble Center Frequency", soc_enum_treble_center_freq),
SOC_ENUM("Reference Output Select", soc_enum_ref_out_select),
TDA7419_SINGLE_TLV("Middle Playback Volume", TDA7419_MIDDLE_REG,
0x1f, -15, 15, 0x10, 1, tlv_filter),
SOC_ENUM("Middle Q Factor", soc_enum_middle_q_factor),
SOC_SINGLE("Middle Soft Step Switch", TDA7419_MIDDLE_REG,
TDA7419_MIDDLE_SOFT_STEP, 1, 1),
TDA7419_SINGLE_TLV("Bass Playback Volume", TDA7419_BASS_REG,
0x1f, -15, 15, 0x10, 1, tlv_filter),
SOC_ENUM("Bass Q Factor", soc_enum_bass_q_factor),
SOC_SINGLE("Bass Soft Step Switch", TDA7419_BASS_REG,
TDA7419_BASS_SOFT_STEP, 1, 1),
SOC_SINGLE_TLV("Second Source Capture Volume", TDA7419_SECOND_SRC_REG,
TDA7419_SECOND_SRC_GAIN, 15, 0, tlv_src_gain),
SOC_ENUM("Subwoofer Cut-off Frequency", soc_enum_sub_cut_off_freq),
SOC_ENUM("Middle Center Frequency", soc_enum_middle_center_freq),
SOC_ENUM("Bass Center Frequency", soc_enum_bass_center_freq),
SOC_SINGLE("Bass DC Mode Switch", TDA7419_SUB_MID_BASS_REG,
TDA7419_BASS_DC_MODE, 1, 1),
SOC_SINGLE("Smoothing Filter Switch", TDA7419_SUB_MID_BASS_REG,
TDA7419_SMOOTHING_FILTER, 1, 1),
TDA7419_DOUBLE_R_TLV("Front Speaker Playback Volume", TDA7419_ATTENUATOR_LF_REG,
TDA7419_ATTENUATOR_RF_REG, 0x7f, -80, 15, 0x10, 0,
tlv_volume),
SOC_SINGLE("Left Front Soft Step Switch", TDA7419_ATTENUATOR_LF_REG,
TDA7419_VOLUME_SOFT_STEP, 1, 1),
SOC_SINGLE("Right Front Soft Step Switch", TDA7419_ATTENUATOR_RF_REG,
TDA7419_VOLUME_SOFT_STEP, 1, 1),
TDA7419_DOUBLE_R_TLV("Rear Speaker Playback Volume", TDA7419_ATTENUATOR_LR_REG,
TDA7419_ATTENUATOR_RR_REG, 0x7f, -80, 15, 0x10, 0,
tlv_volume),
SOC_SINGLE("Left Rear Soft Step Switch", TDA7419_ATTENUATOR_LR_REG,
TDA7419_VOLUME_SOFT_STEP, 1, 1),
SOC_SINGLE("Right Rear Soft Step Switch", TDA7419_ATTENUATOR_RR_REG,
TDA7419_VOLUME_SOFT_STEP, 1, 1),
TDA7419_SINGLE_TLV("Mixing Capture Volume", TDA7419_MIXING_LEVEL_REG,
0x7f, -80, 15, 0x10, 0, tlv_volume),
SOC_SINGLE("Mixing Level Soft Step Switch", TDA7419_MIXING_LEVEL_REG,
TDA7419_VOLUME_SOFT_STEP, 1, 1),
TDA7419_SINGLE_TLV("Subwoofer Playback Volume", TDA7419_ATTENUATOR_SUB_REG,
0x7f, -80, 15, 0x10, 0, tlv_volume),
SOC_SINGLE("Subwoofer Soft Step Switch", TDA7419_ATTENUATOR_SUB_REG,
TDA7419_VOLUME_SOFT_STEP, 1, 1),
SOC_ENUM("Spectrum Analyzer Q Factor", soc_enum_sa_q_factor),
SOC_ENUM("Spectrum Analyzer Reset Mode", soc_enum_reset_mode),
SOC_ENUM("Spectrum Analyzer Source", soc_enum_sa_src),
SOC_SINGLE("Spectrum Analyzer Run Switch", TDA7419_SA_CLK_AC_REG,
TDA7419_SA_RUN, 1, 1),
SOC_SINGLE("Spectrum Analyzer Reset Switch", TDA7419_SA_CLK_AC_REG,
TDA7419_RESET, 1, 1),
SOC_ENUM("Clock Source", soc_enum_clk_src),
SOC_ENUM("Coupling Mode", soc_enum_coupling_mode),
};
static const struct snd_kcontrol_new soc_mixer_lf_output_controls[] = {
SOC_DAPM_SINGLE("Mix to LF Speaker Switch",
TDA7419_MIXING_GAIN_REG,
TDA7419_MIX_LF, 1, 1),
};
static const struct snd_kcontrol_new soc_mixer_rf_output_controls[] = {
SOC_DAPM_SINGLE("Mix to RF Speaker Switch",
TDA7419_MIXING_GAIN_REG,
TDA7419_MIX_RF, 1, 1),
};
static const struct snd_kcontrol_new soc_mix_enable_switch_controls[] = {
SOC_DAPM_SINGLE("Switch", TDA7419_MIXING_GAIN_REG,
TDA7419_MIX_ENABLE, 1, 1),
};
static const struct snd_kcontrol_new soc_sub_enable_switch_controls[] = {
SOC_DAPM_SINGLE("Switch", TDA7419_MIXING_GAIN_REG,
TDA7419_MIX_ENABLE, 1, 1),
};
static const struct snd_soc_dapm_widget tda7419_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("SE3L"),
SND_SOC_DAPM_INPUT("SE3R"),
SND_SOC_DAPM_INPUT("SE2L"),
SND_SOC_DAPM_INPUT("SE2R"),
SND_SOC_DAPM_INPUT("SE1L"),
SND_SOC_DAPM_INPUT("SE1R"),
SND_SOC_DAPM_INPUT("DIFFL"),
SND_SOC_DAPM_INPUT("DIFFR"),
SND_SOC_DAPM_INPUT("MIX"),
SND_SOC_DAPM_MUX("Main Source Select", SND_SOC_NOPM,
0, 0, &soc_mux_main_src_sel),
SND_SOC_DAPM_MUX("Second Source Select", SND_SOC_NOPM,
0, 0, &soc_mux_second_src_sel),
SND_SOC_DAPM_MUX("Rear Speaker Source", SND_SOC_NOPM,
0, 0, &soc_mux_rear_spkr_src),
SND_SOC_DAPM_SWITCH("Mix Enable", SND_SOC_NOPM,
0, 0, &soc_mix_enable_switch_controls[0]),
SND_SOC_DAPM_MIXER_NAMED_CTL("LF Output Mixer", SND_SOC_NOPM,
0, 0, &soc_mixer_lf_output_controls[0],
ARRAY_SIZE(soc_mixer_lf_output_controls)),
SND_SOC_DAPM_MIXER_NAMED_CTL("RF Output Mixer", SND_SOC_NOPM,
0, 0, &soc_mixer_rf_output_controls[0],
ARRAY_SIZE(soc_mixer_rf_output_controls)),
SND_SOC_DAPM_SWITCH("Subwoofer Enable",
SND_SOC_NOPM, 0, 0,
&soc_sub_enable_switch_controls[0]),
SND_SOC_DAPM_OUTPUT("OUTLF"),
SND_SOC_DAPM_OUTPUT("OUTRF"),
SND_SOC_DAPM_OUTPUT("OUTLR"),
SND_SOC_DAPM_OUTPUT("OUTRR"),
SND_SOC_DAPM_OUTPUT("OUTSW"),
};
static const struct snd_soc_dapm_route tda7419_dapm_routes[] = {
{"Main Source Select", "SE3", "SE3L"},
{"Main Source Select", "SE3", "SE3R"},
{"Main Source Select", "SE2", "SE2L"},
{"Main Source Select", "SE2", "SE2R"},
{"Main Source Select", "SE1", "SE1L"},
{"Main Source Select", "SE1", "SE1R"},
{"Main Source Select", "SE", "DIFFL"},
{"Main Source Select", "SE", "DIFFR"},
{"Main Source Select", "QD", "DIFFL"},
{"Main Source Select", "QD", "DIFFR"},
{"Second Source Select", "SE3", "SE3L"},
{"Second Source Select", "SE3", "SE3R"},
{"Second Source Select", "SE2", "SE2L"},
{"Second Source Select", "SE2", "SE2R"},
{"Second Source Select", "SE1", "SE1L"},
{"Second Source Select", "SE1", "SE1R"},
{"Second Source Select", "SE", "DIFFL"},
{"Second Source Select", "SE", "DIFFR"},
{"Second Source Select", "QD", "DIFFL"},
{"Second Source Select", "QD", "DIFFR"},
{"Rear Speaker Source", "Main", "Main Source Select"},
{"Rear Speaker Source", "Second", "Second Source Select"},
{"Subwoofer Enable", "Switch", "Main Source Select"},
{"Mix Enable", "Switch", "MIX"},
{"LF Output Mixer", NULL, "Main Source Select"},
{"LF Output Mixer", "Mix to LF Speaker Switch", "Mix Enable"},
{"RF Output Mixer", NULL, "Main Source Select"},
{"RF Output Mixer", "Mix to RF Speaker Switch", "Mix Enable"},
{"OUTLF", NULL, "LF Output Mixer"},
{"OUTRF", NULL, "RF Output Mixer"},
{"OUTLR", NULL, "Rear Speaker Source"},
{"OUTRR", NULL, "Rear Speaker Source"},
{"OUTSW", NULL, "Subwoofer Enable"},
};
static const struct snd_soc_component_driver tda7419_component_driver = {
.name = "tda7419",
.controls = tda7419_controls,
.num_controls = ARRAY_SIZE(tda7419_controls),
.dapm_widgets = tda7419_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(tda7419_dapm_widgets),
.dapm_routes = tda7419_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(tda7419_dapm_routes),
};
static int tda7419_probe(struct i2c_client *i2c)
{
struct tda7419_data *tda7419;
int i, ret;
tda7419 = devm_kzalloc(&i2c->dev,
sizeof(struct tda7419_data),
GFP_KERNEL);
if (tda7419 == NULL)
return -ENOMEM;
i2c_set_clientdata(i2c, tda7419);
tda7419->regmap = devm_regmap_init_i2c(i2c, &tda7419_regmap_config);
if (IS_ERR(tda7419->regmap)) {
ret = PTR_ERR(tda7419->regmap);
dev_err(&i2c->dev, "error initializing regmap: %d\n",
ret);
return ret;
}
/*
* Reset registers to power-on defaults. The part does not provide a
* soft-reset function and the registers are not readable. This ensures
* that the cache matches register contents even if the registers have
* been previously initialized and not power cycled before probe.
*/
for (i = 0; i < ARRAY_SIZE(tda7419_regmap_defaults); i++)
regmap_write(tda7419->regmap,
tda7419_regmap_defaults[i].reg,
tda7419_regmap_defaults[i].def);
ret = devm_snd_soc_register_component(&i2c->dev,
&tda7419_component_driver, NULL, 0);
if (ret < 0) {
dev_err(&i2c->dev, "error registering component: %d\n",
ret);
}
return ret;
}
static const struct i2c_device_id tda7419_i2c_id[] = {
{ "tda7419", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, tda7419_i2c_id);
static const struct of_device_id tda7419_of_match[] = {
{ .compatible = "st,tda7419" },
{ },
};
static struct i2c_driver tda7419_driver = {
.driver = {
.name = "tda7419",
.of_match_table = tda7419_of_match,
},
.probe = tda7419_probe,
.id_table = tda7419_i2c_id,
};
module_i2c_driver(tda7419_driver);
MODULE_AUTHOR("Matt Porter <[email protected]>");
MODULE_DESCRIPTION("TDA7419 audio processor driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/tda7419.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8728.c -- WM8728 ALSA SoC Audio driver
*
* Copyright 2008 Wolfson Microelectronics plc
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <linux/of_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "wm8728.h"
/*
* We can't read the WM8728 register space so we cache them instead.
* Note that the defaults here aren't the physical defaults, we latch
* the volume update bits, mute the output and enable infinite zero
* detect.
*/
static const struct reg_default wm8728_reg_defaults[] = {
{ 0, 0x1ff },
{ 1, 0x1ff },
{ 2, 0x001 },
{ 3, 0x100 },
};
/* codec private data */
struct wm8728_priv {
struct regmap *regmap;
};
static const DECLARE_TLV_DB_SCALE(wm8728_tlv, -12750, 50, 1);
static const struct snd_kcontrol_new wm8728_snd_controls[] = {
SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8728_DACLVOL, WM8728_DACRVOL,
0, 255, 0, wm8728_tlv),
SOC_SINGLE("Deemphasis", WM8728_DACCTL, 1, 1, 0),
};
/*
* DAPM controls.
*/
static const struct snd_soc_dapm_widget wm8728_dapm_widgets[] = {
SND_SOC_DAPM_DAC("DAC", "HiFi Playback", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_OUTPUT("VOUTL"),
SND_SOC_DAPM_OUTPUT("VOUTR"),
};
static const struct snd_soc_dapm_route wm8728_intercon[] = {
{"VOUTL", NULL, "DAC"},
{"VOUTR", NULL, "DAC"},
};
static int wm8728_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
u16 mute_reg = snd_soc_component_read(component, WM8728_DACCTL);
if (mute)
snd_soc_component_write(component, WM8728_DACCTL, mute_reg | 1);
else
snd_soc_component_write(component, WM8728_DACCTL, mute_reg & ~1);
return 0;
}
static int wm8728_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
u16 dac = snd_soc_component_read(component, WM8728_DACCTL);
dac &= ~0x18;
switch (params_width(params)) {
case 16:
break;
case 20:
dac |= 0x10;
break;
case 24:
dac |= 0x08;
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, WM8728_DACCTL, dac);
return 0;
}
static int wm8728_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
u16 iface = snd_soc_component_read(component, WM8728_IFCTL);
/* Currently only I2S is supported by the driver, though the
* hardware is more flexible.
*/
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface |= 1;
break;
default:
return -EINVAL;
}
/* The hardware only support full slave mode */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
iface &= ~0x22;
break;
case SND_SOC_DAIFMT_IB_NF:
iface |= 0x20;
iface &= ~0x02;
break;
case SND_SOC_DAIFMT_NB_IF:
iface |= 0x02;
iface &= ~0x20;
break;
case SND_SOC_DAIFMT_IB_IF:
iface |= 0x22;
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, WM8728_IFCTL, iface);
return 0;
}
static int wm8728_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct wm8728_priv *wm8728 = snd_soc_component_get_drvdata(component);
u16 reg;
switch (level) {
case SND_SOC_BIAS_ON:
case SND_SOC_BIAS_PREPARE:
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
/* Power everything up... */
reg = snd_soc_component_read(component, WM8728_DACCTL);
snd_soc_component_write(component, WM8728_DACCTL, reg & ~0x4);
/* ..then sync in the register cache. */
regcache_sync(wm8728->regmap);
}
break;
case SND_SOC_BIAS_OFF:
reg = snd_soc_component_read(component, WM8728_DACCTL);
snd_soc_component_write(component, WM8728_DACCTL, reg | 0x4);
break;
}
return 0;
}
#define WM8728_RATES (SNDRV_PCM_RATE_8000_192000)
#define WM8728_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE)
static const struct snd_soc_dai_ops wm8728_dai_ops = {
.hw_params = wm8728_hw_params,
.mute_stream = wm8728_mute,
.set_fmt = wm8728_set_dai_fmt,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver wm8728_dai = {
.name = "wm8728-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = WM8728_RATES,
.formats = WM8728_FORMATS,
},
.ops = &wm8728_dai_ops,
};
static const struct snd_soc_component_driver soc_component_dev_wm8728 = {
.set_bias_level = wm8728_set_bias_level,
.controls = wm8728_snd_controls,
.num_controls = ARRAY_SIZE(wm8728_snd_controls),
.dapm_widgets = wm8728_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8728_dapm_widgets),
.dapm_routes = wm8728_intercon,
.num_dapm_routes = ARRAY_SIZE(wm8728_intercon),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct of_device_id wm8728_of_match[] = {
{ .compatible = "wlf,wm8728", },
{ }
};
MODULE_DEVICE_TABLE(of, wm8728_of_match);
static const struct regmap_config wm8728_regmap = {
.reg_bits = 7,
.val_bits = 9,
.max_register = WM8728_IFCTL,
.reg_defaults = wm8728_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8728_reg_defaults),
.cache_type = REGCACHE_MAPLE,
};
#if defined(CONFIG_SPI_MASTER)
static int wm8728_spi_probe(struct spi_device *spi)
{
struct wm8728_priv *wm8728;
int ret;
wm8728 = devm_kzalloc(&spi->dev, sizeof(struct wm8728_priv),
GFP_KERNEL);
if (wm8728 == NULL)
return -ENOMEM;
wm8728->regmap = devm_regmap_init_spi(spi, &wm8728_regmap);
if (IS_ERR(wm8728->regmap))
return PTR_ERR(wm8728->regmap);
spi_set_drvdata(spi, wm8728);
ret = devm_snd_soc_register_component(&spi->dev,
&soc_component_dev_wm8728, &wm8728_dai, 1);
return ret;
}
static struct spi_driver wm8728_spi_driver = {
.driver = {
.name = "wm8728",
.of_match_table = wm8728_of_match,
},
.probe = wm8728_spi_probe,
};
#endif /* CONFIG_SPI_MASTER */
#if IS_ENABLED(CONFIG_I2C)
static int wm8728_i2c_probe(struct i2c_client *i2c)
{
struct wm8728_priv *wm8728;
int ret;
wm8728 = devm_kzalloc(&i2c->dev, sizeof(struct wm8728_priv),
GFP_KERNEL);
if (wm8728 == NULL)
return -ENOMEM;
wm8728->regmap = devm_regmap_init_i2c(i2c, &wm8728_regmap);
if (IS_ERR(wm8728->regmap))
return PTR_ERR(wm8728->regmap);
i2c_set_clientdata(i2c, wm8728);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_wm8728, &wm8728_dai, 1);
return ret;
}
static const struct i2c_device_id wm8728_i2c_id[] = {
{ "wm8728", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8728_i2c_id);
static struct i2c_driver wm8728_i2c_driver = {
.driver = {
.name = "wm8728",
.of_match_table = wm8728_of_match,
},
.probe = wm8728_i2c_probe,
.id_table = wm8728_i2c_id,
};
#endif
static int __init wm8728_modinit(void)
{
int ret = 0;
#if IS_ENABLED(CONFIG_I2C)
ret = i2c_add_driver(&wm8728_i2c_driver);
if (ret != 0) {
printk(KERN_ERR "Failed to register wm8728 I2C driver: %d\n",
ret);
}
#endif
#if defined(CONFIG_SPI_MASTER)
ret = spi_register_driver(&wm8728_spi_driver);
if (ret != 0) {
printk(KERN_ERR "Failed to register wm8728 SPI driver: %d\n",
ret);
}
#endif
return ret;
}
module_init(wm8728_modinit);
static void __exit wm8728_exit(void)
{
#if IS_ENABLED(CONFIG_I2C)
i2c_del_driver(&wm8728_i2c_driver);
#endif
#if defined(CONFIG_SPI_MASTER)
spi_unregister_driver(&wm8728_spi_driver);
#endif
}
module_exit(wm8728_exit);
MODULE_DESCRIPTION("ASoC WM8728 driver");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8728.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* cs4265.c -- CS4265 ALSA SoC audio driver
*
* Copyright 2014 Cirrus Logic, Inc.
*
* Author: Paul Handrigan <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/gpio/consumer.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/input.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "cs4265.h"
struct cs4265_private {
struct regmap *regmap;
struct gpio_desc *reset_gpio;
u8 format;
u32 sysclk;
};
static const struct reg_default cs4265_reg_defaults[] = {
{ CS4265_PWRCTL, 0x0F },
{ CS4265_DAC_CTL, 0x08 },
{ CS4265_ADC_CTL, 0x00 },
{ CS4265_MCLK_FREQ, 0x00 },
{ CS4265_SIG_SEL, 0x40 },
{ CS4265_CHB_PGA_CTL, 0x00 },
{ CS4265_CHA_PGA_CTL, 0x00 },
{ CS4265_ADC_CTL2, 0x19 },
{ CS4265_DAC_CHA_VOL, 0x00 },
{ CS4265_DAC_CHB_VOL, 0x00 },
{ CS4265_DAC_CTL2, 0xC0 },
{ CS4265_SPDIF_CTL1, 0x00 },
{ CS4265_SPDIF_CTL2, 0x00 },
{ CS4265_INT_MASK, 0x00 },
{ CS4265_STATUS_MODE_MSB, 0x00 },
{ CS4265_STATUS_MODE_LSB, 0x00 },
};
static bool cs4265_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS4265_CHIP_ID ... CS4265_MAX_REGISTER:
return true;
default:
return false;
}
}
static bool cs4265_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS4265_INT_STATUS:
return true;
default:
return false;
}
}
static DECLARE_TLV_DB_SCALE(pga_tlv, -1200, 50, 0);
static DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 0);
static const char * const digital_input_mux_text[] = {
"SDIN1", "SDIN2"
};
static SOC_ENUM_SINGLE_DECL(digital_input_mux_enum, CS4265_SIG_SEL, 7,
digital_input_mux_text);
static const struct snd_kcontrol_new digital_input_mux =
SOC_DAPM_ENUM("Digital Input Mux", digital_input_mux_enum);
static const char * const mic_linein_text[] = {
"MIC", "LINEIN"
};
static SOC_ENUM_SINGLE_DECL(mic_linein_enum, CS4265_ADC_CTL2, 0,
mic_linein_text);
static const char * const cam_mode_text[] = {
"One Byte", "Two Byte"
};
static SOC_ENUM_SINGLE_DECL(cam_mode_enum, CS4265_SPDIF_CTL1, 5,
cam_mode_text);
static const char * const cam_mono_stereo_text[] = {
"Stereo", "Mono"
};
static SOC_ENUM_SINGLE_DECL(spdif_mono_stereo_enum, CS4265_SPDIF_CTL2, 2,
cam_mono_stereo_text);
static const char * const mono_select_text[] = {
"Channel A", "Channel B"
};
static SOC_ENUM_SINGLE_DECL(spdif_mono_select_enum, CS4265_SPDIF_CTL2, 0,
mono_select_text);
static const struct snd_kcontrol_new mic_linein_mux =
SOC_DAPM_ENUM("ADC Input Capture Mux", mic_linein_enum);
static const struct snd_kcontrol_new loopback_ctl =
SOC_DAPM_SINGLE("Switch", CS4265_SIG_SEL, 1, 1, 0);
static const struct snd_kcontrol_new spdif_switch =
SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 0, 0);
static const struct snd_kcontrol_new dac_switch =
SOC_DAPM_SINGLE("Switch", CS4265_PWRCTL, 1, 1, 0);
static const struct snd_kcontrol_new cs4265_snd_controls[] = {
SOC_DOUBLE_R_SX_TLV("PGA Volume", CS4265_CHA_PGA_CTL,
CS4265_CHB_PGA_CTL, 0, 0x28, 0x30, pga_tlv),
SOC_DOUBLE_R_TLV("DAC Volume", CS4265_DAC_CHA_VOL,
CS4265_DAC_CHB_VOL, 0, 0xFF, 1, dac_tlv),
SOC_SINGLE("De-emp 44.1kHz Switch", CS4265_DAC_CTL, 1,
1, 0),
SOC_SINGLE("DAC INV Switch", CS4265_DAC_CTL2, 5,
1, 0),
SOC_SINGLE("DAC Zero Cross Switch", CS4265_DAC_CTL2, 6,
1, 0),
SOC_SINGLE("DAC Soft Ramp Switch", CS4265_DAC_CTL2, 7,
1, 0),
SOC_SINGLE("ADC HPF Switch", CS4265_ADC_CTL, 1,
1, 0),
SOC_SINGLE("ADC Zero Cross Switch", CS4265_ADC_CTL2, 3,
1, 1),
SOC_SINGLE("ADC Soft Ramp Switch", CS4265_ADC_CTL2, 7,
1, 0),
SOC_SINGLE("E to F Buffer Disable Switch", CS4265_SPDIF_CTL1,
6, 1, 0),
SOC_ENUM("C Data Access", cam_mode_enum),
SOC_SINGLE("Validity Bit Control Switch", CS4265_SPDIF_CTL2,
3, 1, 0),
SOC_ENUM("SPDIF Mono/Stereo", spdif_mono_stereo_enum),
SOC_SINGLE("MMTLR Data Switch", CS4265_SPDIF_CTL2, 0, 1, 0),
SOC_ENUM("Mono Channel Select", spdif_mono_select_enum),
SND_SOC_BYTES("C Data Buffer", CS4265_C_DATA_BUFF, 24),
};
static const struct snd_soc_dapm_widget cs4265_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("LINEINL"),
SND_SOC_DAPM_INPUT("LINEINR"),
SND_SOC_DAPM_INPUT("MICL"),
SND_SOC_DAPM_INPUT("MICR"),
SND_SOC_DAPM_AIF_OUT("DOUT", NULL, 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("SPDIFOUT", NULL, 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_MUX("ADC Mux", SND_SOC_NOPM, 0, 0, &mic_linein_mux),
SND_SOC_DAPM_ADC("ADC", NULL, CS4265_PWRCTL, 2, 1),
SND_SOC_DAPM_PGA("Pre-amp MIC", CS4265_PWRCTL, 3,
1, NULL, 0),
SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM,
0, 0, &digital_input_mux),
SND_SOC_DAPM_MIXER("SDIN1 Input Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SDIN2 Input Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SPDIF Transmitter", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SWITCH("Loopback", SND_SOC_NOPM, 0, 0,
&loopback_ctl),
SND_SOC_DAPM_SWITCH("SPDIF", CS4265_SPDIF_CTL2, 5, 1,
&spdif_switch),
SND_SOC_DAPM_SWITCH("DAC", CS4265_PWRCTL, 1, 1,
&dac_switch),
SND_SOC_DAPM_AIF_IN("DIN1", NULL, 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("DIN2", NULL, 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("TXIN", NULL, 0,
CS4265_SPDIF_CTL2, 5, 1),
SND_SOC_DAPM_OUTPUT("LINEOUTL"),
SND_SOC_DAPM_OUTPUT("LINEOUTR"),
};
static const struct snd_soc_dapm_route cs4265_audio_map[] = {
{"DIN1", NULL, "DAI1 Playback"},
{"DIN2", NULL, "DAI2 Playback"},
{"SDIN1 Input Mixer", NULL, "DIN1"},
{"SDIN2 Input Mixer", NULL, "DIN2"},
{"Input Mux", "SDIN1", "SDIN1 Input Mixer"},
{"Input Mux", "SDIN2", "SDIN2 Input Mixer"},
{"DAC", "Switch", "Input Mux"},
{"SPDIF", "Switch", "Input Mux"},
{"LINEOUTL", NULL, "DAC"},
{"LINEOUTR", NULL, "DAC"},
{"SPDIFOUT", NULL, "SPDIF"},
{"Pre-amp MIC", NULL, "MICL"},
{"Pre-amp MIC", NULL, "MICR"},
{"ADC Mux", "MIC", "Pre-amp MIC"},
{"ADC Mux", "LINEIN", "LINEINL"},
{"ADC Mux", "LINEIN", "LINEINR"},
{"ADC", NULL, "ADC Mux"},
{"DOUT", NULL, "ADC"},
{"DAI1 Capture", NULL, "DOUT"},
{"DAI2 Capture", NULL, "DOUT"},
/* Loopback */
{"Loopback", "Switch", "ADC"},
{"DAC", NULL, "Loopback"},
};
struct cs4265_clk_para {
u32 mclk;
u32 rate;
u8 fm_mode; /* values 1, 2, or 4 */
u8 mclkdiv;
};
static const struct cs4265_clk_para clk_map_table[] = {
/*32k*/
{8192000, 32000, 0, 0},
{12288000, 32000, 0, 1},
{16384000, 32000, 0, 2},
{24576000, 32000, 0, 3},
{32768000, 32000, 0, 4},
/*44.1k*/
{11289600, 44100, 0, 0},
{16934400, 44100, 0, 1},
{22579200, 44100, 0, 2},
{33868000, 44100, 0, 3},
{45158400, 44100, 0, 4},
/*48k*/
{12288000, 48000, 0, 0},
{18432000, 48000, 0, 1},
{24576000, 48000, 0, 2},
{36864000, 48000, 0, 3},
{49152000, 48000, 0, 4},
/*64k*/
{8192000, 64000, 1, 0},
{12288000, 64000, 1, 1},
{16934400, 64000, 1, 2},
{24576000, 64000, 1, 3},
{32768000, 64000, 1, 4},
/* 88.2k */
{11289600, 88200, 1, 0},
{16934400, 88200, 1, 1},
{22579200, 88200, 1, 2},
{33868000, 88200, 1, 3},
{45158400, 88200, 1, 4},
/* 96k */
{12288000, 96000, 1, 0},
{18432000, 96000, 1, 1},
{24576000, 96000, 1, 2},
{36864000, 96000, 1, 3},
{49152000, 96000, 1, 4},
/* 128k */
{8192000, 128000, 2, 0},
{12288000, 128000, 2, 1},
{16934400, 128000, 2, 2},
{24576000, 128000, 2, 3},
{32768000, 128000, 2, 4},
/* 176.4k */
{11289600, 176400, 2, 0},
{16934400, 176400, 2, 1},
{22579200, 176400, 2, 2},
{33868000, 176400, 2, 3},
{49152000, 176400, 2, 4},
/* 192k */
{12288000, 192000, 2, 0},
{18432000, 192000, 2, 1},
{24576000, 192000, 2, 2},
{36864000, 192000, 2, 3},
{49152000, 192000, 2, 4},
};
static int cs4265_get_clk_index(int mclk, int rate)
{
int i;
for (i = 0; i < ARRAY_SIZE(clk_map_table); i++) {
if (clk_map_table[i].rate == rate &&
clk_map_table[i].mclk == mclk)
return i;
}
return -EINVAL;
}
static int cs4265_set_sysclk(struct snd_soc_dai *codec_dai, int clk_id,
unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct cs4265_private *cs4265 = snd_soc_component_get_drvdata(component);
int i;
if (clk_id != 0) {
dev_err(component->dev, "Invalid clk_id %d\n", clk_id);
return -EINVAL;
}
for (i = 0; i < ARRAY_SIZE(clk_map_table); i++) {
if (clk_map_table[i].mclk == freq) {
cs4265->sysclk = freq;
return 0;
}
}
cs4265->sysclk = 0;
dev_err(component->dev, "Invalid freq parameter %d\n", freq);
return -EINVAL;
}
static int cs4265_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct cs4265_private *cs4265 = snd_soc_component_get_drvdata(component);
u8 iface = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
snd_soc_component_update_bits(component, CS4265_ADC_CTL,
CS4265_ADC_MASTER,
CS4265_ADC_MASTER);
break;
case SND_SOC_DAIFMT_CBS_CFS:
snd_soc_component_update_bits(component, CS4265_ADC_CTL,
CS4265_ADC_MASTER,
0);
break;
default:
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface |= SND_SOC_DAIFMT_I2S;
break;
case SND_SOC_DAIFMT_RIGHT_J:
iface |= SND_SOC_DAIFMT_RIGHT_J;
break;
case SND_SOC_DAIFMT_LEFT_J:
iface |= SND_SOC_DAIFMT_LEFT_J;
break;
default:
return -EINVAL;
}
cs4265->format = iface;
return 0;
}
static int cs4265_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
if (mute) {
snd_soc_component_update_bits(component, CS4265_DAC_CTL,
CS4265_DAC_CTL_MUTE,
CS4265_DAC_CTL_MUTE);
snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
CS4265_SPDIF_CTL2_MUTE,
CS4265_SPDIF_CTL2_MUTE);
} else {
snd_soc_component_update_bits(component, CS4265_DAC_CTL,
CS4265_DAC_CTL_MUTE,
0);
snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
CS4265_SPDIF_CTL2_MUTE,
0);
}
return 0;
}
static int cs4265_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct cs4265_private *cs4265 = snd_soc_component_get_drvdata(component);
int index;
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE &&
((cs4265->format & SND_SOC_DAIFMT_FORMAT_MASK)
== SND_SOC_DAIFMT_RIGHT_J))
return -EINVAL;
index = cs4265_get_clk_index(cs4265->sysclk, params_rate(params));
if (index >= 0) {
snd_soc_component_update_bits(component, CS4265_ADC_CTL,
CS4265_ADC_FM, clk_map_table[index].fm_mode << 6);
snd_soc_component_update_bits(component, CS4265_MCLK_FREQ,
CS4265_MCLK_FREQ_MASK,
clk_map_table[index].mclkdiv << 4);
} else {
dev_err(component->dev, "can't get correct mclk\n");
return -EINVAL;
}
switch (cs4265->format & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
snd_soc_component_update_bits(component, CS4265_DAC_CTL,
CS4265_DAC_CTL_DIF, (1 << 4));
snd_soc_component_update_bits(component, CS4265_ADC_CTL,
CS4265_ADC_DIF, (1 << 4));
snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
CS4265_SPDIF_CTL2_DIF, (1 << 6));
break;
case SND_SOC_DAIFMT_RIGHT_J:
if (params_width(params) == 16) {
snd_soc_component_update_bits(component, CS4265_DAC_CTL,
CS4265_DAC_CTL_DIF, (2 << 4));
snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
CS4265_SPDIF_CTL2_DIF, (2 << 6));
} else {
snd_soc_component_update_bits(component, CS4265_DAC_CTL,
CS4265_DAC_CTL_DIF, (3 << 4));
snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
CS4265_SPDIF_CTL2_DIF, (3 << 6));
}
break;
case SND_SOC_DAIFMT_LEFT_J:
snd_soc_component_update_bits(component, CS4265_DAC_CTL,
CS4265_DAC_CTL_DIF, 0);
snd_soc_component_update_bits(component, CS4265_ADC_CTL,
CS4265_ADC_DIF, 0);
snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
CS4265_SPDIF_CTL2_DIF, 0);
break;
default:
return -EINVAL;
}
return 0;
}
static int cs4265_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
snd_soc_component_update_bits(component, CS4265_PWRCTL,
CS4265_PWRCTL_PDN, 0);
break;
case SND_SOC_BIAS_STANDBY:
snd_soc_component_update_bits(component, CS4265_PWRCTL,
CS4265_PWRCTL_PDN,
CS4265_PWRCTL_PDN);
break;
case SND_SOC_BIAS_OFF:
snd_soc_component_update_bits(component, CS4265_PWRCTL,
CS4265_PWRCTL_PDN,
CS4265_PWRCTL_PDN);
break;
}
return 0;
}
#define CS4265_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | \
SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000)
#define CS4265_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_U24_LE | \
SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_U32_LE)
static const struct snd_soc_dai_ops cs4265_ops = {
.hw_params = cs4265_pcm_hw_params,
.mute_stream = cs4265_mute,
.set_fmt = cs4265_set_fmt,
.set_sysclk = cs4265_set_sysclk,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver cs4265_dai[] = {
{
.name = "cs4265-dai1",
.playback = {
.stream_name = "DAI1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = CS4265_RATES,
.formats = CS4265_FORMATS,
},
.capture = {
.stream_name = "DAI1 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = CS4265_RATES,
.formats = CS4265_FORMATS,
},
.ops = &cs4265_ops,
},
{
.name = "cs4265-dai2",
.playback = {
.stream_name = "DAI2 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = CS4265_RATES,
.formats = CS4265_FORMATS,
},
.capture = {
.stream_name = "DAI2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = CS4265_RATES,
.formats = CS4265_FORMATS,
},
.ops = &cs4265_ops,
},
};
static const struct snd_soc_component_driver soc_component_cs4265 = {
.set_bias_level = cs4265_set_bias_level,
.controls = cs4265_snd_controls,
.num_controls = ARRAY_SIZE(cs4265_snd_controls),
.dapm_widgets = cs4265_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(cs4265_dapm_widgets),
.dapm_routes = cs4265_audio_map,
.num_dapm_routes = ARRAY_SIZE(cs4265_audio_map),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config cs4265_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = CS4265_MAX_REGISTER,
.reg_defaults = cs4265_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(cs4265_reg_defaults),
.readable_reg = cs4265_readable_register,
.volatile_reg = cs4265_volatile_register,
.cache_type = REGCACHE_MAPLE,
};
static int cs4265_i2c_probe(struct i2c_client *i2c_client)
{
struct cs4265_private *cs4265;
int ret;
unsigned int devid = 0;
unsigned int reg;
cs4265 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs4265_private),
GFP_KERNEL);
if (cs4265 == NULL)
return -ENOMEM;
cs4265->regmap = devm_regmap_init_i2c(i2c_client, &cs4265_regmap);
if (IS_ERR(cs4265->regmap)) {
ret = PTR_ERR(cs4265->regmap);
dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
return ret;
}
cs4265->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
"reset", GPIOD_OUT_LOW);
if (IS_ERR(cs4265->reset_gpio))
return PTR_ERR(cs4265->reset_gpio);
if (cs4265->reset_gpio) {
mdelay(1);
gpiod_set_value_cansleep(cs4265->reset_gpio, 1);
}
i2c_set_clientdata(i2c_client, cs4265);
ret = regmap_read(cs4265->regmap, CS4265_CHIP_ID, ®);
if (ret) {
dev_err(&i2c_client->dev, "Failed to read chip ID: %d\n", ret);
return ret;
}
devid = reg & CS4265_CHIP_ID_MASK;
if (devid != CS4265_CHIP_ID_VAL) {
ret = -ENODEV;
dev_err(&i2c_client->dev,
"CS4265 Part Number ID: 0x%x Expected: 0x%x\n",
devid >> 4, CS4265_CHIP_ID_VAL >> 4);
return ret;
}
dev_info(&i2c_client->dev,
"CS4265 Version %x\n",
reg & CS4265_REV_ID_MASK);
regmap_write(cs4265->regmap, CS4265_PWRCTL, 0x0F);
return devm_snd_soc_register_component(&i2c_client->dev,
&soc_component_cs4265, cs4265_dai,
ARRAY_SIZE(cs4265_dai));
}
static void cs4265_i2c_remove(struct i2c_client *i2c)
{
struct cs4265_private *cs4265 = i2c_get_clientdata(i2c);
if (cs4265->reset_gpio)
gpiod_set_value_cansleep(cs4265->reset_gpio, 0);
}
static const struct of_device_id cs4265_of_match[] = {
{ .compatible = "cirrus,cs4265", },
{ }
};
MODULE_DEVICE_TABLE(of, cs4265_of_match);
static const struct i2c_device_id cs4265_id[] = {
{ "cs4265", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, cs4265_id);
static struct i2c_driver cs4265_i2c_driver = {
.driver = {
.name = "cs4265",
.of_match_table = cs4265_of_match,
},
.id_table = cs4265_id,
.probe = cs4265_i2c_probe,
.remove = cs4265_i2c_remove,
};
module_i2c_driver(cs4265_i2c_driver);
MODULE_DESCRIPTION("ASoC CS4265 driver");
MODULE_AUTHOR("Paul Handrigan, Cirrus Logic Inc, <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cs4265.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* da7218.c - DA7218 ALSA SoC Codec Driver
*
* Copyright (c) 2015 Dialog Semiconductor
*
* Author: Adam Thomson <[email protected]>
*/
#include <linux/clk.h>
#include <linux/i2c.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/pm.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/regulator/consumer.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/jack.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <asm/div64.h>
#include <sound/da7218.h>
#include "da7218.h"
/*
* TLVs and Enums
*/
/* Input TLVs */
static const DECLARE_TLV_DB_SCALE(da7218_mic_gain_tlv, -600, 600, 0);
static const DECLARE_TLV_DB_SCALE(da7218_mixin_gain_tlv, -450, 150, 0);
static const DECLARE_TLV_DB_SCALE(da7218_in_dig_gain_tlv, -8325, 75, 0);
static const DECLARE_TLV_DB_SCALE(da7218_ags_trigger_tlv, -9000, 600, 0);
static const DECLARE_TLV_DB_SCALE(da7218_ags_att_max_tlv, 0, 600, 0);
static const DECLARE_TLV_DB_SCALE(da7218_alc_threshold_tlv, -9450, 150, 0);
static const DECLARE_TLV_DB_SCALE(da7218_alc_gain_tlv, 0, 600, 0);
static const DECLARE_TLV_DB_SCALE(da7218_alc_ana_gain_tlv, 0, 600, 0);
/* Input/Output TLVs */
static const DECLARE_TLV_DB_SCALE(da7218_dmix_gain_tlv, -4200, 150, 0);
/* Output TLVs */
static const DECLARE_TLV_DB_SCALE(da7218_dgs_trigger_tlv, -9450, 150, 0);
static const DECLARE_TLV_DB_SCALE(da7218_dgs_anticlip_tlv, -4200, 600, 0);
static const DECLARE_TLV_DB_SCALE(da7218_dgs_signal_tlv, -9000, 600, 0);
static const DECLARE_TLV_DB_SCALE(da7218_out_eq_band_tlv, -1050, 150, 0);
static const DECLARE_TLV_DB_SCALE(da7218_out_dig_gain_tlv, -8325, 75, 0);
static const DECLARE_TLV_DB_SCALE(da7218_dac_ng_threshold_tlv, -10200, 600, 0);
static const DECLARE_TLV_DB_SCALE(da7218_mixout_gain_tlv, -100, 50, 0);
static const DECLARE_TLV_DB_SCALE(da7218_hp_gain_tlv, -5700, 150, 0);
/* Input Enums */
static const char * const da7218_alc_attack_rate_txt[] = {
"7.33/fs", "14.66/fs", "29.32/fs", "58.64/fs", "117.3/fs", "234.6/fs",
"469.1/fs", "938.2/fs", "1876/fs", "3753/fs", "7506/fs", "15012/fs",
"30024/fs",
};
static const struct soc_enum da7218_alc_attack_rate =
SOC_ENUM_SINGLE(DA7218_ALC_CTRL2, DA7218_ALC_ATTACK_SHIFT,
DA7218_ALC_ATTACK_MAX, da7218_alc_attack_rate_txt);
static const char * const da7218_alc_release_rate_txt[] = {
"28.66/fs", "57.33/fs", "114.6/fs", "229.3/fs", "458.6/fs", "917.1/fs",
"1834/fs", "3668/fs", "7337/fs", "14674/fs", "29348/fs",
};
static const struct soc_enum da7218_alc_release_rate =
SOC_ENUM_SINGLE(DA7218_ALC_CTRL2, DA7218_ALC_RELEASE_SHIFT,
DA7218_ALC_RELEASE_MAX, da7218_alc_release_rate_txt);
static const char * const da7218_alc_hold_time_txt[] = {
"62/fs", "124/fs", "248/fs", "496/fs", "992/fs", "1984/fs", "3968/fs",
"7936/fs", "15872/fs", "31744/fs", "63488/fs", "126976/fs",
"253952/fs", "507904/fs", "1015808/fs", "2031616/fs"
};
static const struct soc_enum da7218_alc_hold_time =
SOC_ENUM_SINGLE(DA7218_ALC_CTRL3, DA7218_ALC_HOLD_SHIFT,
DA7218_ALC_HOLD_MAX, da7218_alc_hold_time_txt);
static const char * const da7218_alc_anticlip_step_txt[] = {
"0.034dB/fs", "0.068dB/fs", "0.136dB/fs", "0.272dB/fs",
};
static const struct soc_enum da7218_alc_anticlip_step =
SOC_ENUM_SINGLE(DA7218_ALC_ANTICLIP_CTRL,
DA7218_ALC_ANTICLIP_STEP_SHIFT,
DA7218_ALC_ANTICLIP_STEP_MAX,
da7218_alc_anticlip_step_txt);
static const char * const da7218_integ_rate_txt[] = {
"1/4", "1/16", "1/256", "1/65536"
};
static const struct soc_enum da7218_integ_attack_rate =
SOC_ENUM_SINGLE(DA7218_ENV_TRACK_CTRL, DA7218_INTEG_ATTACK_SHIFT,
DA7218_INTEG_MAX, da7218_integ_rate_txt);
static const struct soc_enum da7218_integ_release_rate =
SOC_ENUM_SINGLE(DA7218_ENV_TRACK_CTRL, DA7218_INTEG_RELEASE_SHIFT,
DA7218_INTEG_MAX, da7218_integ_rate_txt);
/* Input/Output Enums */
static const char * const da7218_gain_ramp_rate_txt[] = {
"Nominal Rate * 8", "Nominal Rate", "Nominal Rate / 8",
"Nominal Rate / 16",
};
static const struct soc_enum da7218_gain_ramp_rate =
SOC_ENUM_SINGLE(DA7218_GAIN_RAMP_CTRL, DA7218_GAIN_RAMP_RATE_SHIFT,
DA7218_GAIN_RAMP_RATE_MAX, da7218_gain_ramp_rate_txt);
static const char * const da7218_hpf_mode_txt[] = {
"Disabled", "Audio", "Voice",
};
static const unsigned int da7218_hpf_mode_val[] = {
DA7218_HPF_DISABLED, DA7218_HPF_AUDIO_EN, DA7218_HPF_VOICE_EN,
};
static const struct soc_enum da7218_in1_hpf_mode =
SOC_VALUE_ENUM_SINGLE(DA7218_IN_1_HPF_FILTER_CTRL,
DA7218_HPF_MODE_SHIFT, DA7218_HPF_MODE_MASK,
DA7218_HPF_MODE_MAX, da7218_hpf_mode_txt,
da7218_hpf_mode_val);
static const struct soc_enum da7218_in2_hpf_mode =
SOC_VALUE_ENUM_SINGLE(DA7218_IN_2_HPF_FILTER_CTRL,
DA7218_HPF_MODE_SHIFT, DA7218_HPF_MODE_MASK,
DA7218_HPF_MODE_MAX, da7218_hpf_mode_txt,
da7218_hpf_mode_val);
static const struct soc_enum da7218_out1_hpf_mode =
SOC_VALUE_ENUM_SINGLE(DA7218_OUT_1_HPF_FILTER_CTRL,
DA7218_HPF_MODE_SHIFT, DA7218_HPF_MODE_MASK,
DA7218_HPF_MODE_MAX, da7218_hpf_mode_txt,
da7218_hpf_mode_val);
static const char * const da7218_audio_hpf_corner_txt[] = {
"2Hz", "4Hz", "8Hz", "16Hz",
};
static const struct soc_enum da7218_in1_audio_hpf_corner =
SOC_ENUM_SINGLE(DA7218_IN_1_HPF_FILTER_CTRL,
DA7218_IN_1_AUDIO_HPF_CORNER_SHIFT,
DA7218_AUDIO_HPF_CORNER_MAX,
da7218_audio_hpf_corner_txt);
static const struct soc_enum da7218_in2_audio_hpf_corner =
SOC_ENUM_SINGLE(DA7218_IN_2_HPF_FILTER_CTRL,
DA7218_IN_2_AUDIO_HPF_CORNER_SHIFT,
DA7218_AUDIO_HPF_CORNER_MAX,
da7218_audio_hpf_corner_txt);
static const struct soc_enum da7218_out1_audio_hpf_corner =
SOC_ENUM_SINGLE(DA7218_OUT_1_HPF_FILTER_CTRL,
DA7218_OUT_1_AUDIO_HPF_CORNER_SHIFT,
DA7218_AUDIO_HPF_CORNER_MAX,
da7218_audio_hpf_corner_txt);
static const char * const da7218_voice_hpf_corner_txt[] = {
"2.5Hz", "25Hz", "50Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz",
};
static const struct soc_enum da7218_in1_voice_hpf_corner =
SOC_ENUM_SINGLE(DA7218_IN_1_HPF_FILTER_CTRL,
DA7218_IN_1_VOICE_HPF_CORNER_SHIFT,
DA7218_VOICE_HPF_CORNER_MAX,
da7218_voice_hpf_corner_txt);
static const struct soc_enum da7218_in2_voice_hpf_corner =
SOC_ENUM_SINGLE(DA7218_IN_2_HPF_FILTER_CTRL,
DA7218_IN_2_VOICE_HPF_CORNER_SHIFT,
DA7218_VOICE_HPF_CORNER_MAX,
da7218_voice_hpf_corner_txt);
static const struct soc_enum da7218_out1_voice_hpf_corner =
SOC_ENUM_SINGLE(DA7218_OUT_1_HPF_FILTER_CTRL,
DA7218_OUT_1_VOICE_HPF_CORNER_SHIFT,
DA7218_VOICE_HPF_CORNER_MAX,
da7218_voice_hpf_corner_txt);
static const char * const da7218_tonegen_dtmf_key_txt[] = {
"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "A", "B", "C", "D",
"*", "#"
};
static const struct soc_enum da7218_tonegen_dtmf_key =
SOC_ENUM_SINGLE(DA7218_TONE_GEN_CFG1, DA7218_DTMF_REG_SHIFT,
DA7218_DTMF_REG_MAX, da7218_tonegen_dtmf_key_txt);
static const char * const da7218_tonegen_swg_sel_txt[] = {
"Sum", "SWG1", "SWG2", "SWG1_1-Cos"
};
static const struct soc_enum da7218_tonegen_swg_sel =
SOC_ENUM_SINGLE(DA7218_TONE_GEN_CFG2, DA7218_SWG_SEL_SHIFT,
DA7218_SWG_SEL_MAX, da7218_tonegen_swg_sel_txt);
/* Output Enums */
static const char * const da7218_dgs_rise_coeff_txt[] = {
"1/1", "1/16", "1/64", "1/256", "1/1024", "1/4096", "1/16384",
};
static const struct soc_enum da7218_dgs_rise_coeff =
SOC_ENUM_SINGLE(DA7218_DGS_RISE_FALL, DA7218_DGS_RISE_COEFF_SHIFT,
DA7218_DGS_RISE_COEFF_MAX, da7218_dgs_rise_coeff_txt);
static const char * const da7218_dgs_fall_coeff_txt[] = {
"1/4", "1/16", "1/64", "1/256", "1/1024", "1/4096", "1/16384", "1/65536",
};
static const struct soc_enum da7218_dgs_fall_coeff =
SOC_ENUM_SINGLE(DA7218_DGS_RISE_FALL, DA7218_DGS_FALL_COEFF_SHIFT,
DA7218_DGS_FALL_COEFF_MAX, da7218_dgs_fall_coeff_txt);
static const char * const da7218_dac_ng_setup_time_txt[] = {
"256 Samples", "512 Samples", "1024 Samples", "2048 Samples"
};
static const struct soc_enum da7218_dac_ng_setup_time =
SOC_ENUM_SINGLE(DA7218_DAC_NG_SETUP_TIME,
DA7218_DAC_NG_SETUP_TIME_SHIFT,
DA7218_DAC_NG_SETUP_TIME_MAX,
da7218_dac_ng_setup_time_txt);
static const char * const da7218_dac_ng_rampup_txt[] = {
"0.22ms/dB", "0.0138ms/dB"
};
static const struct soc_enum da7218_dac_ng_rampup_rate =
SOC_ENUM_SINGLE(DA7218_DAC_NG_SETUP_TIME,
DA7218_DAC_NG_RAMPUP_RATE_SHIFT,
DA7218_DAC_NG_RAMPUP_RATE_MAX,
da7218_dac_ng_rampup_txt);
static const char * const da7218_dac_ng_rampdown_txt[] = {
"0.88ms/dB", "14.08ms/dB"
};
static const struct soc_enum da7218_dac_ng_rampdown_rate =
SOC_ENUM_SINGLE(DA7218_DAC_NG_SETUP_TIME,
DA7218_DAC_NG_RAMPDN_RATE_SHIFT,
DA7218_DAC_NG_RAMPDN_RATE_MAX,
da7218_dac_ng_rampdown_txt);
static const char * const da7218_cp_mchange_txt[] = {
"Largest Volume", "DAC Volume", "Signal Magnitude"
};
static const unsigned int da7218_cp_mchange_val[] = {
DA7218_CP_MCHANGE_LARGEST_VOL, DA7218_CP_MCHANGE_DAC_VOL,
DA7218_CP_MCHANGE_SIG_MAG
};
static const struct soc_enum da7218_cp_mchange =
SOC_VALUE_ENUM_SINGLE(DA7218_CP_CTRL, DA7218_CP_MCHANGE_SHIFT,
DA7218_CP_MCHANGE_REL_MASK, DA7218_CP_MCHANGE_MAX,
da7218_cp_mchange_txt, da7218_cp_mchange_val);
static const char * const da7218_cp_fcontrol_txt[] = {
"1MHz", "500KHz", "250KHz", "125KHz", "63KHz", "0KHz"
};
static const struct soc_enum da7218_cp_fcontrol =
SOC_ENUM_SINGLE(DA7218_CP_DELAY, DA7218_CP_FCONTROL_SHIFT,
DA7218_CP_FCONTROL_MAX, da7218_cp_fcontrol_txt);
static const char * const da7218_cp_tau_delay_txt[] = {
"0ms", "2ms", "4ms", "16ms", "64ms", "128ms", "256ms", "512ms"
};
static const struct soc_enum da7218_cp_tau_delay =
SOC_ENUM_SINGLE(DA7218_CP_DELAY, DA7218_CP_TAU_DELAY_SHIFT,
DA7218_CP_TAU_DELAY_MAX, da7218_cp_tau_delay_txt);
/*
* Control Functions
*/
/* ALC */
static void da7218_alc_calib(struct snd_soc_component *component)
{
u8 mic_1_ctrl, mic_2_ctrl;
u8 mixin_1_ctrl, mixin_2_ctrl;
u8 in_1l_filt_ctrl, in_1r_filt_ctrl, in_2l_filt_ctrl, in_2r_filt_ctrl;
u8 in_1_hpf_ctrl, in_2_hpf_ctrl;
u8 calib_ctrl;
int i = 0;
bool calibrated = false;
/* Save current state of MIC control registers */
mic_1_ctrl = snd_soc_component_read(component, DA7218_MIC_1_CTRL);
mic_2_ctrl = snd_soc_component_read(component, DA7218_MIC_2_CTRL);
/* Save current state of input mixer control registers */
mixin_1_ctrl = snd_soc_component_read(component, DA7218_MIXIN_1_CTRL);
mixin_2_ctrl = snd_soc_component_read(component, DA7218_MIXIN_2_CTRL);
/* Save current state of input filter control registers */
in_1l_filt_ctrl = snd_soc_component_read(component, DA7218_IN_1L_FILTER_CTRL);
in_1r_filt_ctrl = snd_soc_component_read(component, DA7218_IN_1R_FILTER_CTRL);
in_2l_filt_ctrl = snd_soc_component_read(component, DA7218_IN_2L_FILTER_CTRL);
in_2r_filt_ctrl = snd_soc_component_read(component, DA7218_IN_2R_FILTER_CTRL);
/* Save current state of input HPF control registers */
in_1_hpf_ctrl = snd_soc_component_read(component, DA7218_IN_1_HPF_FILTER_CTRL);
in_2_hpf_ctrl = snd_soc_component_read(component, DA7218_IN_2_HPF_FILTER_CTRL);
/* Enable then Mute MIC PGAs */
snd_soc_component_update_bits(component, DA7218_MIC_1_CTRL, DA7218_MIC_1_AMP_EN_MASK,
DA7218_MIC_1_AMP_EN_MASK);
snd_soc_component_update_bits(component, DA7218_MIC_2_CTRL, DA7218_MIC_2_AMP_EN_MASK,
DA7218_MIC_2_AMP_EN_MASK);
snd_soc_component_update_bits(component, DA7218_MIC_1_CTRL,
DA7218_MIC_1_AMP_MUTE_EN_MASK,
DA7218_MIC_1_AMP_MUTE_EN_MASK);
snd_soc_component_update_bits(component, DA7218_MIC_2_CTRL,
DA7218_MIC_2_AMP_MUTE_EN_MASK,
DA7218_MIC_2_AMP_MUTE_EN_MASK);
/* Enable input mixers unmuted */
snd_soc_component_update_bits(component, DA7218_MIXIN_1_CTRL,
DA7218_MIXIN_1_AMP_EN_MASK |
DA7218_MIXIN_1_AMP_MUTE_EN_MASK,
DA7218_MIXIN_1_AMP_EN_MASK);
snd_soc_component_update_bits(component, DA7218_MIXIN_2_CTRL,
DA7218_MIXIN_2_AMP_EN_MASK |
DA7218_MIXIN_2_AMP_MUTE_EN_MASK,
DA7218_MIXIN_2_AMP_EN_MASK);
/* Enable input filters unmuted */
snd_soc_component_update_bits(component, DA7218_IN_1L_FILTER_CTRL,
DA7218_IN_1L_FILTER_EN_MASK |
DA7218_IN_1L_MUTE_EN_MASK,
DA7218_IN_1L_FILTER_EN_MASK);
snd_soc_component_update_bits(component, DA7218_IN_1R_FILTER_CTRL,
DA7218_IN_1R_FILTER_EN_MASK |
DA7218_IN_1R_MUTE_EN_MASK,
DA7218_IN_1R_FILTER_EN_MASK);
snd_soc_component_update_bits(component, DA7218_IN_2L_FILTER_CTRL,
DA7218_IN_2L_FILTER_EN_MASK |
DA7218_IN_2L_MUTE_EN_MASK,
DA7218_IN_2L_FILTER_EN_MASK);
snd_soc_component_update_bits(component, DA7218_IN_2R_FILTER_CTRL,
DA7218_IN_2R_FILTER_EN_MASK |
DA7218_IN_2R_MUTE_EN_MASK,
DA7218_IN_2R_FILTER_EN_MASK);
/*
* Make sure input HPFs voice mode is disabled, otherwise for sampling
* rates above 32KHz the ADC signals will be stopped and will cause
* calibration to lock up.
*/
snd_soc_component_update_bits(component, DA7218_IN_1_HPF_FILTER_CTRL,
DA7218_IN_1_VOICE_EN_MASK, 0);
snd_soc_component_update_bits(component, DA7218_IN_2_HPF_FILTER_CTRL,
DA7218_IN_2_VOICE_EN_MASK, 0);
/* Perform auto calibration */
snd_soc_component_update_bits(component, DA7218_CALIB_CTRL, DA7218_CALIB_AUTO_EN_MASK,
DA7218_CALIB_AUTO_EN_MASK);
do {
calib_ctrl = snd_soc_component_read(component, DA7218_CALIB_CTRL);
if (calib_ctrl & DA7218_CALIB_AUTO_EN_MASK) {
++i;
usleep_range(DA7218_ALC_CALIB_DELAY_MIN,
DA7218_ALC_CALIB_DELAY_MAX);
} else {
calibrated = true;
}
} while ((i < DA7218_ALC_CALIB_MAX_TRIES) && (!calibrated));
/* If auto calibration fails, disable DC offset, hybrid ALC */
if ((!calibrated) || (calib_ctrl & DA7218_CALIB_OVERFLOW_MASK)) {
dev_warn(component->dev,
"ALC auto calibration failed - %s\n",
(calibrated) ? "overflow" : "timeout");
snd_soc_component_update_bits(component, DA7218_CALIB_CTRL,
DA7218_CALIB_OFFSET_EN_MASK, 0);
snd_soc_component_update_bits(component, DA7218_ALC_CTRL1,
DA7218_ALC_SYNC_MODE_MASK, 0);
} else {
/* Enable DC offset cancellation */
snd_soc_component_update_bits(component, DA7218_CALIB_CTRL,
DA7218_CALIB_OFFSET_EN_MASK,
DA7218_CALIB_OFFSET_EN_MASK);
/* Enable ALC hybrid mode */
snd_soc_component_update_bits(component, DA7218_ALC_CTRL1,
DA7218_ALC_SYNC_MODE_MASK,
DA7218_ALC_SYNC_MODE_CH1 |
DA7218_ALC_SYNC_MODE_CH2);
}
/* Restore input HPF control registers to original states */
snd_soc_component_write(component, DA7218_IN_1_HPF_FILTER_CTRL, in_1_hpf_ctrl);
snd_soc_component_write(component, DA7218_IN_2_HPF_FILTER_CTRL, in_2_hpf_ctrl);
/* Restore input filter control registers to original states */
snd_soc_component_write(component, DA7218_IN_1L_FILTER_CTRL, in_1l_filt_ctrl);
snd_soc_component_write(component, DA7218_IN_1R_FILTER_CTRL, in_1r_filt_ctrl);
snd_soc_component_write(component, DA7218_IN_2L_FILTER_CTRL, in_2l_filt_ctrl);
snd_soc_component_write(component, DA7218_IN_2R_FILTER_CTRL, in_2r_filt_ctrl);
/* Restore input mixer control registers to original state */
snd_soc_component_write(component, DA7218_MIXIN_1_CTRL, mixin_1_ctrl);
snd_soc_component_write(component, DA7218_MIXIN_2_CTRL, mixin_2_ctrl);
/* Restore MIC control registers to original states */
snd_soc_component_write(component, DA7218_MIC_1_CTRL, mic_1_ctrl);
snd_soc_component_write(component, DA7218_MIC_2_CTRL, mic_2_ctrl);
}
static int da7218_mixin_gain_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
int ret;
ret = snd_soc_put_volsw(kcontrol, ucontrol);
/*
* If ALC in operation and value of control has been updated,
* make sure calibrated offsets are updated.
*/
if ((ret == 1) && (da7218->alc_en))
da7218_alc_calib(component);
return ret;
}
static int da7218_alc_sw_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *mc =
(struct soc_mixer_control *) kcontrol->private_value;
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
unsigned int lvalue = ucontrol->value.integer.value[0];
unsigned int rvalue = ucontrol->value.integer.value[1];
unsigned int lshift = mc->shift;
unsigned int rshift = mc->rshift;
unsigned int mask = (mc->max << lshift) | (mc->max << rshift);
/* Force ALC offset calibration if enabling ALC */
if ((lvalue || rvalue) && (!da7218->alc_en))
da7218_alc_calib(component);
/* Update bits to detail which channels are enabled/disabled */
da7218->alc_en &= ~mask;
da7218->alc_en |= (lvalue << lshift) | (rvalue << rshift);
return snd_soc_put_volsw(kcontrol, ucontrol);
}
/* ToneGen */
static int da7218_tonegen_freq_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
struct soc_mixer_control *mixer_ctrl =
(struct soc_mixer_control *) kcontrol->private_value;
unsigned int reg = mixer_ctrl->reg;
u16 val;
int ret;
/*
* Frequency value spans two 8-bit registers, lower then upper byte.
* Therefore we need to convert to host endianness here.
*/
ret = regmap_raw_read(da7218->regmap, reg, &val, 2);
if (ret)
return ret;
ucontrol->value.integer.value[0] = le16_to_cpu(val);
return 0;
}
static int da7218_tonegen_freq_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
struct soc_mixer_control *mixer_ctrl =
(struct soc_mixer_control *) kcontrol->private_value;
unsigned int reg = mixer_ctrl->reg;
u16 val;
/*
* Frequency value spans two 8-bit registers, lower then upper byte.
* Therefore we need to convert to little endian here to align with
* HW registers.
*/
val = cpu_to_le16(ucontrol->value.integer.value[0]);
return regmap_raw_write(da7218->regmap, reg, &val, 2);
}
static int da7218_mic_lvl_det_sw_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
struct soc_mixer_control *mixer_ctrl =
(struct soc_mixer_control *) kcontrol->private_value;
unsigned int lvalue = ucontrol->value.integer.value[0];
unsigned int rvalue = ucontrol->value.integer.value[1];
unsigned int lshift = mixer_ctrl->shift;
unsigned int rshift = mixer_ctrl->rshift;
unsigned int mask = (mixer_ctrl->max << lshift) |
(mixer_ctrl->max << rshift);
da7218->mic_lvl_det_en &= ~mask;
da7218->mic_lvl_det_en |= (lvalue << lshift) | (rvalue << rshift);
/*
* Here we only enable the feature on paths which are already
* powered. If a channel is enabled here for level detect, but that path
* isn't powered, then the channel will actually be enabled when we do
* power the path (IN_FILTER widget events). This handling avoids
* unwanted level detect events.
*/
return snd_soc_component_write(component, mixer_ctrl->reg,
(da7218->in_filt_en & da7218->mic_lvl_det_en));
}
static int da7218_mic_lvl_det_sw_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
struct soc_mixer_control *mixer_ctrl =
(struct soc_mixer_control *) kcontrol->private_value;
unsigned int lshift = mixer_ctrl->shift;
unsigned int rshift = mixer_ctrl->rshift;
unsigned int lmask = (mixer_ctrl->max << lshift);
unsigned int rmask = (mixer_ctrl->max << rshift);
ucontrol->value.integer.value[0] =
(da7218->mic_lvl_det_en & lmask) >> lshift;
ucontrol->value.integer.value[1] =
(da7218->mic_lvl_det_en & rmask) >> rshift;
return 0;
}
static int da7218_biquad_coeff_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
struct soc_bytes_ext *bytes_ext =
(struct soc_bytes_ext *) kcontrol->private_value;
/* Determine which BiQuads we're setting based on size of config data */
switch (bytes_ext->max) {
case DA7218_OUT_1_BIQ_5STAGE_CFG_SIZE:
memcpy(ucontrol->value.bytes.data, da7218->biq_5stage_coeff,
bytes_ext->max);
break;
case DA7218_SIDETONE_BIQ_3STAGE_CFG_SIZE:
memcpy(ucontrol->value.bytes.data, da7218->stbiq_3stage_coeff,
bytes_ext->max);
break;
default:
return -EINVAL;
}
return 0;
}
static int da7218_biquad_coeff_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
struct soc_bytes_ext *bytes_ext =
(struct soc_bytes_ext *) kcontrol->private_value;
u8 reg, out_filt1l;
u8 cfg[DA7218_BIQ_CFG_SIZE];
int i;
/*
* Determine which BiQuads we're setting based on size of config data,
* and stored the data for use by get function.
*/
switch (bytes_ext->max) {
case DA7218_OUT_1_BIQ_5STAGE_CFG_SIZE:
reg = DA7218_OUT_1_BIQ_5STAGE_DATA;
memcpy(da7218->biq_5stage_coeff, ucontrol->value.bytes.data,
bytes_ext->max);
break;
case DA7218_SIDETONE_BIQ_3STAGE_CFG_SIZE:
reg = DA7218_SIDETONE_BIQ_3STAGE_DATA;
memcpy(da7218->stbiq_3stage_coeff, ucontrol->value.bytes.data,
bytes_ext->max);
break;
default:
return -EINVAL;
}
/* Make sure at least out filter1 enabled to allow programming */
out_filt1l = snd_soc_component_read(component, DA7218_OUT_1L_FILTER_CTRL);
snd_soc_component_write(component, DA7218_OUT_1L_FILTER_CTRL,
out_filt1l | DA7218_OUT_1L_FILTER_EN_MASK);
for (i = 0; i < bytes_ext->max; ++i) {
cfg[DA7218_BIQ_CFG_DATA] = ucontrol->value.bytes.data[i];
cfg[DA7218_BIQ_CFG_ADDR] = i;
regmap_raw_write(da7218->regmap, reg, cfg, DA7218_BIQ_CFG_SIZE);
}
/* Restore filter to previous setting */
snd_soc_component_write(component, DA7218_OUT_1L_FILTER_CTRL, out_filt1l);
return 0;
}
/*
* KControls
*/
static const struct snd_kcontrol_new da7218_snd_controls[] = {
/* Mics */
SOC_SINGLE_TLV("Mic1 Volume", DA7218_MIC_1_GAIN,
DA7218_MIC_1_AMP_GAIN_SHIFT, DA7218_MIC_AMP_GAIN_MAX,
DA7218_NO_INVERT, da7218_mic_gain_tlv),
SOC_SINGLE("Mic1 Switch", DA7218_MIC_1_CTRL,
DA7218_MIC_1_AMP_MUTE_EN_SHIFT, DA7218_SWITCH_EN_MAX,
DA7218_INVERT),
SOC_SINGLE_TLV("Mic2 Volume", DA7218_MIC_2_GAIN,
DA7218_MIC_2_AMP_GAIN_SHIFT, DA7218_MIC_AMP_GAIN_MAX,
DA7218_NO_INVERT, da7218_mic_gain_tlv),
SOC_SINGLE("Mic2 Switch", DA7218_MIC_2_CTRL,
DA7218_MIC_2_AMP_MUTE_EN_SHIFT, DA7218_SWITCH_EN_MAX,
DA7218_INVERT),
/* Mixer Input */
SOC_SINGLE_EXT_TLV("Mixin1 Volume", DA7218_MIXIN_1_GAIN,
DA7218_MIXIN_1_AMP_GAIN_SHIFT,
DA7218_MIXIN_AMP_GAIN_MAX, DA7218_NO_INVERT,
snd_soc_get_volsw, da7218_mixin_gain_put,
da7218_mixin_gain_tlv),
SOC_SINGLE("Mixin1 Switch", DA7218_MIXIN_1_CTRL,
DA7218_MIXIN_1_AMP_MUTE_EN_SHIFT, DA7218_SWITCH_EN_MAX,
DA7218_INVERT),
SOC_SINGLE("Mixin1 Gain Ramp Switch", DA7218_MIXIN_1_CTRL,
DA7218_MIXIN_1_AMP_RAMP_EN_SHIFT, DA7218_SWITCH_EN_MAX,
DA7218_NO_INVERT),
SOC_SINGLE("Mixin1 ZC Gain Switch", DA7218_MIXIN_1_CTRL,
DA7218_MIXIN_1_AMP_ZC_EN_SHIFT, DA7218_SWITCH_EN_MAX,
DA7218_NO_INVERT),
SOC_SINGLE_EXT_TLV("Mixin2 Volume", DA7218_MIXIN_2_GAIN,
DA7218_MIXIN_2_AMP_GAIN_SHIFT,
DA7218_MIXIN_AMP_GAIN_MAX, DA7218_NO_INVERT,
snd_soc_get_volsw, da7218_mixin_gain_put,
da7218_mixin_gain_tlv),
SOC_SINGLE("Mixin2 Switch", DA7218_MIXIN_2_CTRL,
DA7218_MIXIN_2_AMP_MUTE_EN_SHIFT, DA7218_SWITCH_EN_MAX,
DA7218_INVERT),
SOC_SINGLE("Mixin2 Gain Ramp Switch", DA7218_MIXIN_2_CTRL,
DA7218_MIXIN_2_AMP_RAMP_EN_SHIFT, DA7218_SWITCH_EN_MAX,
DA7218_NO_INVERT),
SOC_SINGLE("Mixin2 ZC Gain Switch", DA7218_MIXIN_2_CTRL,
DA7218_MIXIN_2_AMP_ZC_EN_SHIFT, DA7218_SWITCH_EN_MAX,
DA7218_NO_INVERT),
/* ADCs */
SOC_SINGLE("ADC1 AAF Switch", DA7218_ADC_1_CTRL,
DA7218_ADC_1_AAF_EN_SHIFT, DA7218_SWITCH_EN_MAX,
DA7218_NO_INVERT),
SOC_SINGLE("ADC2 AAF Switch", DA7218_ADC_2_CTRL,
DA7218_ADC_2_AAF_EN_SHIFT, DA7218_SWITCH_EN_MAX,
DA7218_NO_INVERT),
SOC_SINGLE("ADC LP Mode Switch", DA7218_ADC_MODE,
DA7218_ADC_LP_MODE_SHIFT, DA7218_SWITCH_EN_MAX,
DA7218_NO_INVERT),
/* Input Filters */
SOC_SINGLE_TLV("In Filter1L Volume", DA7218_IN_1L_GAIN,
DA7218_IN_1L_DIGITAL_GAIN_SHIFT,
DA7218_IN_DIGITAL_GAIN_MAX, DA7218_NO_INVERT,
da7218_in_dig_gain_tlv),
SOC_SINGLE("In Filter1L Switch", DA7218_IN_1L_FILTER_CTRL,
DA7218_IN_1L_MUTE_EN_SHIFT, DA7218_SWITCH_EN_MAX,
DA7218_INVERT),
SOC_SINGLE("In Filter1L Gain Ramp Switch", DA7218_IN_1L_FILTER_CTRL,
DA7218_IN_1L_RAMP_EN_SHIFT, DA7218_SWITCH_EN_MAX,
DA7218_NO_INVERT),
SOC_SINGLE_TLV("In Filter1R Volume", DA7218_IN_1R_GAIN,
DA7218_IN_1R_DIGITAL_GAIN_SHIFT,
DA7218_IN_DIGITAL_GAIN_MAX, DA7218_NO_INVERT,
da7218_in_dig_gain_tlv),
SOC_SINGLE("In Filter1R Switch", DA7218_IN_1R_FILTER_CTRL,
DA7218_IN_1R_MUTE_EN_SHIFT, DA7218_SWITCH_EN_MAX,
DA7218_INVERT),
SOC_SINGLE("In Filter1R Gain Ramp Switch",
DA7218_IN_1R_FILTER_CTRL, DA7218_IN_1R_RAMP_EN_SHIFT,
DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT),
SOC_SINGLE_TLV("In Filter2L Volume", DA7218_IN_2L_GAIN,
DA7218_IN_2L_DIGITAL_GAIN_SHIFT,
DA7218_IN_DIGITAL_GAIN_MAX, DA7218_NO_INVERT,
da7218_in_dig_gain_tlv),
SOC_SINGLE("In Filter2L Switch", DA7218_IN_2L_FILTER_CTRL,
DA7218_IN_2L_MUTE_EN_SHIFT, DA7218_SWITCH_EN_MAX,
DA7218_INVERT),
SOC_SINGLE("In Filter2L Gain Ramp Switch", DA7218_IN_2L_FILTER_CTRL,
DA7218_IN_2L_RAMP_EN_SHIFT, DA7218_SWITCH_EN_MAX,
DA7218_NO_INVERT),
SOC_SINGLE_TLV("In Filter2R Volume", DA7218_IN_2R_GAIN,
DA7218_IN_2R_DIGITAL_GAIN_SHIFT,
DA7218_IN_DIGITAL_GAIN_MAX, DA7218_NO_INVERT,
da7218_in_dig_gain_tlv),
SOC_SINGLE("In Filter2R Switch", DA7218_IN_2R_FILTER_CTRL,
DA7218_IN_2R_MUTE_EN_SHIFT, DA7218_SWITCH_EN_MAX,
DA7218_INVERT),
SOC_SINGLE("In Filter2R Gain Ramp Switch",
DA7218_IN_2R_FILTER_CTRL, DA7218_IN_2R_RAMP_EN_SHIFT,
DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT),
/* AGS */
SOC_SINGLE_TLV("AGS Trigger", DA7218_AGS_TRIGGER,
DA7218_AGS_TRIGGER_SHIFT, DA7218_AGS_TRIGGER_MAX,
DA7218_INVERT, da7218_ags_trigger_tlv),
SOC_SINGLE_TLV("AGS Max Attenuation", DA7218_AGS_ATT_MAX,
DA7218_AGS_ATT_MAX_SHIFT, DA7218_AGS_ATT_MAX_MAX,
DA7218_NO_INVERT, da7218_ags_att_max_tlv),
SOC_SINGLE("AGS Anticlip Switch", DA7218_AGS_ANTICLIP_CTRL,
DA7218_AGS_ANTICLIP_EN_SHIFT, DA7218_SWITCH_EN_MAX,
DA7218_NO_INVERT),
SOC_SINGLE("AGS Channel1 Switch", DA7218_AGS_ENABLE,
DA7218_AGS_ENABLE_CHAN1_SHIFT, DA7218_SWITCH_EN_MAX,
DA7218_NO_INVERT),
SOC_SINGLE("AGS Channel2 Switch", DA7218_AGS_ENABLE,
DA7218_AGS_ENABLE_CHAN2_SHIFT, DA7218_SWITCH_EN_MAX,
DA7218_NO_INVERT),
/* ALC */
SOC_ENUM("ALC Attack Rate", da7218_alc_attack_rate),
SOC_ENUM("ALC Release Rate", da7218_alc_release_rate),
SOC_ENUM("ALC Hold Time", da7218_alc_hold_time),
SOC_SINGLE_TLV("ALC Noise Threshold", DA7218_ALC_NOISE,
DA7218_ALC_NOISE_SHIFT, DA7218_ALC_THRESHOLD_MAX,
DA7218_INVERT, da7218_alc_threshold_tlv),
SOC_SINGLE_TLV("ALC Min Threshold", DA7218_ALC_TARGET_MIN,
DA7218_ALC_THRESHOLD_MIN_SHIFT, DA7218_ALC_THRESHOLD_MAX,
DA7218_INVERT, da7218_alc_threshold_tlv),
SOC_SINGLE_TLV("ALC Max Threshold", DA7218_ALC_TARGET_MAX,
DA7218_ALC_THRESHOLD_MAX_SHIFT, DA7218_ALC_THRESHOLD_MAX,
DA7218_INVERT, da7218_alc_threshold_tlv),
SOC_SINGLE_TLV("ALC Max Attenuation", DA7218_ALC_GAIN_LIMITS,
DA7218_ALC_ATTEN_MAX_SHIFT, DA7218_ALC_ATTEN_GAIN_MAX,
DA7218_NO_INVERT, da7218_alc_gain_tlv),
SOC_SINGLE_TLV("ALC Max Gain", DA7218_ALC_GAIN_LIMITS,
DA7218_ALC_GAIN_MAX_SHIFT, DA7218_ALC_ATTEN_GAIN_MAX,
DA7218_NO_INVERT, da7218_alc_gain_tlv),
SOC_SINGLE_RANGE_TLV("ALC Min Analog Gain", DA7218_ALC_ANA_GAIN_LIMITS,
DA7218_ALC_ANA_GAIN_MIN_SHIFT,
DA7218_ALC_ANA_GAIN_MIN, DA7218_ALC_ANA_GAIN_MAX,
DA7218_NO_INVERT, da7218_alc_ana_gain_tlv),
SOC_SINGLE_RANGE_TLV("ALC Max Analog Gain", DA7218_ALC_ANA_GAIN_LIMITS,
DA7218_ALC_ANA_GAIN_MAX_SHIFT,
DA7218_ALC_ANA_GAIN_MIN, DA7218_ALC_ANA_GAIN_MAX,
DA7218_NO_INVERT, da7218_alc_ana_gain_tlv),
SOC_ENUM("ALC Anticlip Step", da7218_alc_anticlip_step),
SOC_SINGLE("ALC Anticlip Switch", DA7218_ALC_ANTICLIP_CTRL,
DA7218_ALC_ANTICLIP_EN_SHIFT, DA7218_SWITCH_EN_MAX,
DA7218_NO_INVERT),
SOC_DOUBLE_EXT("ALC Channel1 Switch", DA7218_ALC_CTRL1,
DA7218_ALC_CHAN1_L_EN_SHIFT, DA7218_ALC_CHAN1_R_EN_SHIFT,
DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT,
snd_soc_get_volsw, da7218_alc_sw_put),
SOC_DOUBLE_EXT("ALC Channel2 Switch", DA7218_ALC_CTRL1,
DA7218_ALC_CHAN2_L_EN_SHIFT, DA7218_ALC_CHAN2_R_EN_SHIFT,
DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT,
snd_soc_get_volsw, da7218_alc_sw_put),
/* Envelope Tracking */
SOC_ENUM("Envelope Tracking Attack Rate", da7218_integ_attack_rate),
SOC_ENUM("Envelope Tracking Release Rate", da7218_integ_release_rate),
/* Input High-Pass Filters */
SOC_ENUM("In Filter1 HPF Mode", da7218_in1_hpf_mode),
SOC_ENUM("In Filter1 HPF Corner Audio", da7218_in1_audio_hpf_corner),
SOC_ENUM("In Filter1 HPF Corner Voice", da7218_in1_voice_hpf_corner),
SOC_ENUM("In Filter2 HPF Mode", da7218_in2_hpf_mode),
SOC_ENUM("In Filter2 HPF Corner Audio", da7218_in2_audio_hpf_corner),
SOC_ENUM("In Filter2 HPF Corner Voice", da7218_in2_voice_hpf_corner),
/* Mic Level Detect */
SOC_DOUBLE_EXT("Mic Level Detect Channel1 Switch", DA7218_LVL_DET_CTRL,
DA7218_LVL_DET_EN_CHAN1L_SHIFT,
DA7218_LVL_DET_EN_CHAN1R_SHIFT, DA7218_SWITCH_EN_MAX,
DA7218_NO_INVERT, da7218_mic_lvl_det_sw_get,
da7218_mic_lvl_det_sw_put),
SOC_DOUBLE_EXT("Mic Level Detect Channel2 Switch", DA7218_LVL_DET_CTRL,
DA7218_LVL_DET_EN_CHAN2L_SHIFT,
DA7218_LVL_DET_EN_CHAN2R_SHIFT, DA7218_SWITCH_EN_MAX,
DA7218_NO_INVERT, da7218_mic_lvl_det_sw_get,
da7218_mic_lvl_det_sw_put),
SOC_SINGLE("Mic Level Detect Level", DA7218_LVL_DET_LEVEL,
DA7218_LVL_DET_LEVEL_SHIFT, DA7218_LVL_DET_LEVEL_MAX,
DA7218_NO_INVERT),
/* Digital Mixer (Input) */
SOC_SINGLE_TLV("DMix In Filter1L Out1 DAIL Volume",
DA7218_DMIX_OUTDAI_1L_INFILT_1L_GAIN,
DA7218_OUTDAI_1L_INFILT_1L_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix In Filter1L Out1 DAIR Volume",
DA7218_DMIX_OUTDAI_1R_INFILT_1L_GAIN,
DA7218_OUTDAI_1R_INFILT_1L_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix In Filter1L Out2 DAIL Volume",
DA7218_DMIX_OUTDAI_2L_INFILT_1L_GAIN,
DA7218_OUTDAI_2L_INFILT_1L_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix In Filter1L Out2 DAIR Volume",
DA7218_DMIX_OUTDAI_2R_INFILT_1L_GAIN,
DA7218_OUTDAI_2R_INFILT_1L_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix In Filter1R Out1 DAIL Volume",
DA7218_DMIX_OUTDAI_1L_INFILT_1R_GAIN,
DA7218_OUTDAI_1L_INFILT_1R_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix In Filter1R Out1 DAIR Volume",
DA7218_DMIX_OUTDAI_1R_INFILT_1R_GAIN,
DA7218_OUTDAI_1R_INFILT_1R_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix In Filter1R Out2 DAIL Volume",
DA7218_DMIX_OUTDAI_2L_INFILT_1R_GAIN,
DA7218_OUTDAI_2L_INFILT_1R_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix In Filter1R Out2 DAIR Volume",
DA7218_DMIX_OUTDAI_2R_INFILT_1R_GAIN,
DA7218_OUTDAI_2R_INFILT_1R_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix In Filter2L Out1 DAIL Volume",
DA7218_DMIX_OUTDAI_1L_INFILT_2L_GAIN,
DA7218_OUTDAI_1L_INFILT_2L_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix In Filter2L Out1 DAIR Volume",
DA7218_DMIX_OUTDAI_1R_INFILT_2L_GAIN,
DA7218_OUTDAI_1R_INFILT_2L_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix In Filter2L Out2 DAIL Volume",
DA7218_DMIX_OUTDAI_2L_INFILT_2L_GAIN,
DA7218_OUTDAI_2L_INFILT_2L_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix In Filter2L Out2 DAIR Volume",
DA7218_DMIX_OUTDAI_2R_INFILT_2L_GAIN,
DA7218_OUTDAI_2R_INFILT_2L_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix In Filter2R Out1 DAIL Volume",
DA7218_DMIX_OUTDAI_1L_INFILT_2R_GAIN,
DA7218_OUTDAI_1L_INFILT_2R_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix In Filter2R Out1 DAIR Volume",
DA7218_DMIX_OUTDAI_1R_INFILT_2R_GAIN,
DA7218_OUTDAI_1R_INFILT_2R_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix In Filter2R Out2 DAIL Volume",
DA7218_DMIX_OUTDAI_2L_INFILT_2R_GAIN,
DA7218_OUTDAI_2L_INFILT_2R_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix In Filter2R Out2 DAIR Volume",
DA7218_DMIX_OUTDAI_2R_INFILT_2R_GAIN,
DA7218_OUTDAI_2R_INFILT_2R_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix ToneGen Out1 DAIL Volume",
DA7218_DMIX_OUTDAI_1L_TONEGEN_GAIN,
DA7218_OUTDAI_1L_TONEGEN_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix ToneGen Out1 DAIR Volume",
DA7218_DMIX_OUTDAI_1R_TONEGEN_GAIN,
DA7218_OUTDAI_1R_TONEGEN_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix ToneGen Out2 DAIL Volume",
DA7218_DMIX_OUTDAI_2L_TONEGEN_GAIN,
DA7218_OUTDAI_2L_TONEGEN_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix ToneGen Out2 DAIR Volume",
DA7218_DMIX_OUTDAI_2R_TONEGEN_GAIN,
DA7218_OUTDAI_2R_TONEGEN_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix In DAIL Out1 DAIL Volume",
DA7218_DMIX_OUTDAI_1L_INDAI_1L_GAIN,
DA7218_OUTDAI_1L_INDAI_1L_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix In DAIL Out1 DAIR Volume",
DA7218_DMIX_OUTDAI_1R_INDAI_1L_GAIN,
DA7218_OUTDAI_1R_INDAI_1L_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix In DAIL Out2 DAIL Volume",
DA7218_DMIX_OUTDAI_2L_INDAI_1L_GAIN,
DA7218_OUTDAI_2L_INDAI_1L_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix In DAIL Out2 DAIR Volume",
DA7218_DMIX_OUTDAI_2R_INDAI_1L_GAIN,
DA7218_OUTDAI_2R_INDAI_1L_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix In DAIR Out1 DAIL Volume",
DA7218_DMIX_OUTDAI_1L_INDAI_1R_GAIN,
DA7218_OUTDAI_1L_INDAI_1R_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix In DAIR Out1 DAIR Volume",
DA7218_DMIX_OUTDAI_1R_INDAI_1R_GAIN,
DA7218_OUTDAI_1R_INDAI_1R_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix In DAIR Out2 DAIL Volume",
DA7218_DMIX_OUTDAI_2L_INDAI_1R_GAIN,
DA7218_OUTDAI_2L_INDAI_1R_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix In DAIR Out2 DAIR Volume",
DA7218_DMIX_OUTDAI_2R_INDAI_1R_GAIN,
DA7218_OUTDAI_2R_INDAI_1R_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
/* Digital Mixer (Output) */
SOC_SINGLE_TLV("DMix In Filter1L Out FilterL Volume",
DA7218_DMIX_OUTFILT_1L_INFILT_1L_GAIN,
DA7218_OUTFILT_1L_INFILT_1L_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix In Filter1L Out FilterR Volume",
DA7218_DMIX_OUTFILT_1R_INFILT_1L_GAIN,
DA7218_OUTFILT_1R_INFILT_1L_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix In Filter1R Out FilterL Volume",
DA7218_DMIX_OUTFILT_1L_INFILT_1R_GAIN,
DA7218_OUTFILT_1L_INFILT_1R_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix In Filter1R Out FilterR Volume",
DA7218_DMIX_OUTFILT_1R_INFILT_1R_GAIN,
DA7218_OUTFILT_1R_INFILT_1R_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix In Filter2L Out FilterL Volume",
DA7218_DMIX_OUTFILT_1L_INFILT_2L_GAIN,
DA7218_OUTFILT_1L_INFILT_2L_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix In Filter2L Out FilterR Volume",
DA7218_DMIX_OUTFILT_1R_INFILT_2L_GAIN,
DA7218_OUTFILT_1R_INFILT_2L_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix In Filter2R Out FilterL Volume",
DA7218_DMIX_OUTFILT_1L_INFILT_2R_GAIN,
DA7218_OUTFILT_1L_INFILT_2R_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix In Filter2R Out FilterR Volume",
DA7218_DMIX_OUTFILT_1R_INFILT_2R_GAIN,
DA7218_OUTFILT_1R_INFILT_2R_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix ToneGen Out FilterL Volume",
DA7218_DMIX_OUTFILT_1L_TONEGEN_GAIN,
DA7218_OUTFILT_1L_TONEGEN_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix ToneGen Out FilterR Volume",
DA7218_DMIX_OUTFILT_1R_TONEGEN_GAIN,
DA7218_OUTFILT_1R_TONEGEN_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix In DAIL Out FilterL Volume",
DA7218_DMIX_OUTFILT_1L_INDAI_1L_GAIN,
DA7218_OUTFILT_1L_INDAI_1L_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix In DAIL Out FilterR Volume",
DA7218_DMIX_OUTFILT_1R_INDAI_1L_GAIN,
DA7218_OUTFILT_1R_INDAI_1L_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix In DAIR Out FilterL Volume",
DA7218_DMIX_OUTFILT_1L_INDAI_1R_GAIN,
DA7218_OUTFILT_1L_INDAI_1R_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
SOC_SINGLE_TLV("DMix In DAIR Out FilterR Volume",
DA7218_DMIX_OUTFILT_1R_INDAI_1R_GAIN,
DA7218_OUTFILT_1R_INDAI_1R_GAIN_SHIFT,
DA7218_DMIX_GAIN_MAX, DA7218_NO_INVERT,
da7218_dmix_gain_tlv),
/* Sidetone Filter */
SND_SOC_BYTES_EXT("Sidetone BiQuad Coefficients",
DA7218_SIDETONE_BIQ_3STAGE_CFG_SIZE,
da7218_biquad_coeff_get, da7218_biquad_coeff_put),
SOC_SINGLE_TLV("Sidetone Volume", DA7218_SIDETONE_GAIN,
DA7218_SIDETONE_GAIN_SHIFT, DA7218_DMIX_GAIN_MAX,
DA7218_NO_INVERT, da7218_dmix_gain_tlv),
SOC_SINGLE("Sidetone Switch", DA7218_SIDETONE_CTRL,
DA7218_SIDETONE_MUTE_EN_SHIFT, DA7218_SWITCH_EN_MAX,
DA7218_INVERT),
/* Tone Generator */
SOC_ENUM("ToneGen DTMF Key", da7218_tonegen_dtmf_key),
SOC_SINGLE("ToneGen DTMF Switch", DA7218_TONE_GEN_CFG1,
DA7218_DTMF_EN_SHIFT, DA7218_SWITCH_EN_MAX,
DA7218_NO_INVERT),
SOC_ENUM("ToneGen Sinewave Gen Type", da7218_tonegen_swg_sel),
SOC_SINGLE_EXT("ToneGen Sinewave1 Freq", DA7218_TONE_GEN_FREQ1_L,
DA7218_FREQ1_L_SHIFT, DA7218_FREQ_MAX, DA7218_NO_INVERT,
da7218_tonegen_freq_get, da7218_tonegen_freq_put),
SOC_SINGLE_EXT("ToneGen Sinewave2 Freq", DA7218_TONE_GEN_FREQ2_L,
DA7218_FREQ2_L_SHIFT, DA7218_FREQ_MAX, DA7218_NO_INVERT,
da7218_tonegen_freq_get, da7218_tonegen_freq_put),
SOC_SINGLE("ToneGen On Time", DA7218_TONE_GEN_ON_PER,
DA7218_BEEP_ON_PER_SHIFT, DA7218_BEEP_ON_OFF_MAX,
DA7218_NO_INVERT),
SOC_SINGLE("ToneGen Off Time", DA7218_TONE_GEN_OFF_PER,
DA7218_BEEP_OFF_PER_SHIFT, DA7218_BEEP_ON_OFF_MAX,
DA7218_NO_INVERT),
/* Gain ramping */
SOC_ENUM("Gain Ramp Rate", da7218_gain_ramp_rate),
/* DGS */
SOC_SINGLE_TLV("DGS Trigger", DA7218_DGS_TRIGGER,
DA7218_DGS_TRIGGER_LVL_SHIFT, DA7218_DGS_TRIGGER_MAX,
DA7218_INVERT, da7218_dgs_trigger_tlv),
SOC_ENUM("DGS Rise Coefficient", da7218_dgs_rise_coeff),
SOC_ENUM("DGS Fall Coefficient", da7218_dgs_fall_coeff),
SOC_SINGLE("DGS Sync Delay", DA7218_DGS_SYNC_DELAY,
DA7218_DGS_SYNC_DELAY_SHIFT, DA7218_DGS_SYNC_DELAY_MAX,
DA7218_NO_INVERT),
SOC_SINGLE("DGS Fast SR Sync Delay", DA7218_DGS_SYNC_DELAY2,
DA7218_DGS_SYNC_DELAY2_SHIFT, DA7218_DGS_SYNC_DELAY_MAX,
DA7218_NO_INVERT),
SOC_SINGLE("DGS Voice Filter Sync Delay", DA7218_DGS_SYNC_DELAY3,
DA7218_DGS_SYNC_DELAY3_SHIFT, DA7218_DGS_SYNC_DELAY3_MAX,
DA7218_NO_INVERT),
SOC_SINGLE_TLV("DGS Anticlip Level", DA7218_DGS_LEVELS,
DA7218_DGS_ANTICLIP_LVL_SHIFT,
DA7218_DGS_ANTICLIP_LVL_MAX, DA7218_INVERT,
da7218_dgs_anticlip_tlv),
SOC_SINGLE_TLV("DGS Signal Level", DA7218_DGS_LEVELS,
DA7218_DGS_SIGNAL_LVL_SHIFT, DA7218_DGS_SIGNAL_LVL_MAX,
DA7218_INVERT, da7218_dgs_signal_tlv),
SOC_SINGLE("DGS Gain Subrange Switch", DA7218_DGS_GAIN_CTRL,
DA7218_DGS_SUBR_EN_SHIFT, DA7218_SWITCH_EN_MAX,
DA7218_NO_INVERT),
SOC_SINGLE("DGS Gain Ramp Switch", DA7218_DGS_GAIN_CTRL,
DA7218_DGS_RAMP_EN_SHIFT, DA7218_SWITCH_EN_MAX,
DA7218_NO_INVERT),
SOC_SINGLE("DGS Gain Steps", DA7218_DGS_GAIN_CTRL,
DA7218_DGS_STEPS_SHIFT, DA7218_DGS_STEPS_MAX,
DA7218_NO_INVERT),
SOC_DOUBLE("DGS Switch", DA7218_DGS_ENABLE, DA7218_DGS_ENABLE_L_SHIFT,
DA7218_DGS_ENABLE_R_SHIFT, DA7218_SWITCH_EN_MAX,
DA7218_NO_INVERT),
/* Output High-Pass Filter */
SOC_ENUM("Out Filter HPF Mode", da7218_out1_hpf_mode),
SOC_ENUM("Out Filter HPF Corner Audio", da7218_out1_audio_hpf_corner),
SOC_ENUM("Out Filter HPF Corner Voice", da7218_out1_voice_hpf_corner),
/* 5-Band Equaliser */
SOC_SINGLE_TLV("Out EQ Band1 Volume", DA7218_OUT_1_EQ_12_FILTER_CTRL,
DA7218_OUT_1_EQ_BAND1_SHIFT, DA7218_OUT_EQ_BAND_MAX,
DA7218_NO_INVERT, da7218_out_eq_band_tlv),
SOC_SINGLE_TLV("Out EQ Band2 Volume", DA7218_OUT_1_EQ_12_FILTER_CTRL,
DA7218_OUT_1_EQ_BAND2_SHIFT, DA7218_OUT_EQ_BAND_MAX,
DA7218_NO_INVERT, da7218_out_eq_band_tlv),
SOC_SINGLE_TLV("Out EQ Band3 Volume", DA7218_OUT_1_EQ_34_FILTER_CTRL,
DA7218_OUT_1_EQ_BAND3_SHIFT, DA7218_OUT_EQ_BAND_MAX,
DA7218_NO_INVERT, da7218_out_eq_band_tlv),
SOC_SINGLE_TLV("Out EQ Band4 Volume", DA7218_OUT_1_EQ_34_FILTER_CTRL,
DA7218_OUT_1_EQ_BAND4_SHIFT, DA7218_OUT_EQ_BAND_MAX,
DA7218_NO_INVERT, da7218_out_eq_band_tlv),
SOC_SINGLE_TLV("Out EQ Band5 Volume", DA7218_OUT_1_EQ_5_FILTER_CTRL,
DA7218_OUT_1_EQ_BAND5_SHIFT, DA7218_OUT_EQ_BAND_MAX,
DA7218_NO_INVERT, da7218_out_eq_band_tlv),
SOC_SINGLE("Out EQ Switch", DA7218_OUT_1_EQ_5_FILTER_CTRL,
DA7218_OUT_1_EQ_EN_SHIFT, DA7218_SWITCH_EN_MAX,
DA7218_NO_INVERT),
/* BiQuad Filters */
SND_SOC_BYTES_EXT("BiQuad Coefficients",
DA7218_OUT_1_BIQ_5STAGE_CFG_SIZE,
da7218_biquad_coeff_get, da7218_biquad_coeff_put),
SOC_SINGLE("BiQuad Filter Switch", DA7218_OUT_1_BIQ_5STAGE_CTRL,
DA7218_OUT_1_BIQ_5STAGE_MUTE_EN_SHIFT, DA7218_SWITCH_EN_MAX,
DA7218_INVERT),
/* Output Filters */
SOC_DOUBLE_R_RANGE_TLV("Out Filter Volume", DA7218_OUT_1L_GAIN,
DA7218_OUT_1R_GAIN,
DA7218_OUT_1L_DIGITAL_GAIN_SHIFT,
DA7218_OUT_DIGITAL_GAIN_MIN,
DA7218_OUT_DIGITAL_GAIN_MAX, DA7218_NO_INVERT,
da7218_out_dig_gain_tlv),
SOC_DOUBLE_R("Out Filter Switch", DA7218_OUT_1L_FILTER_CTRL,
DA7218_OUT_1R_FILTER_CTRL, DA7218_OUT_1L_MUTE_EN_SHIFT,
DA7218_SWITCH_EN_MAX, DA7218_INVERT),
SOC_DOUBLE_R("Out Filter Gain Subrange Switch",
DA7218_OUT_1L_FILTER_CTRL, DA7218_OUT_1R_FILTER_CTRL,
DA7218_OUT_1L_SUBRANGE_EN_SHIFT, DA7218_SWITCH_EN_MAX,
DA7218_NO_INVERT),
SOC_DOUBLE_R("Out Filter Gain Ramp Switch", DA7218_OUT_1L_FILTER_CTRL,
DA7218_OUT_1R_FILTER_CTRL, DA7218_OUT_1L_RAMP_EN_SHIFT,
DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT),
/* Mixer Output */
SOC_DOUBLE_R_RANGE_TLV("Mixout Volume", DA7218_MIXOUT_L_GAIN,
DA7218_MIXOUT_R_GAIN,
DA7218_MIXOUT_L_AMP_GAIN_SHIFT,
DA7218_MIXOUT_AMP_GAIN_MIN,
DA7218_MIXOUT_AMP_GAIN_MAX, DA7218_NO_INVERT,
da7218_mixout_gain_tlv),
/* DAC Noise Gate */
SOC_ENUM("DAC NG Setup Time", da7218_dac_ng_setup_time),
SOC_ENUM("DAC NG Rampup Rate", da7218_dac_ng_rampup_rate),
SOC_ENUM("DAC NG Rampdown Rate", da7218_dac_ng_rampdown_rate),
SOC_SINGLE_TLV("DAC NG Off Threshold", DA7218_DAC_NG_OFF_THRESH,
DA7218_DAC_NG_OFF_THRESHOLD_SHIFT,
DA7218_DAC_NG_THRESHOLD_MAX, DA7218_NO_INVERT,
da7218_dac_ng_threshold_tlv),
SOC_SINGLE_TLV("DAC NG On Threshold", DA7218_DAC_NG_ON_THRESH,
DA7218_DAC_NG_ON_THRESHOLD_SHIFT,
DA7218_DAC_NG_THRESHOLD_MAX, DA7218_NO_INVERT,
da7218_dac_ng_threshold_tlv),
SOC_SINGLE("DAC NG Switch", DA7218_DAC_NG_CTRL, DA7218_DAC_NG_EN_SHIFT,
DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT),
/* CP */
SOC_ENUM("Charge Pump Track Mode", da7218_cp_mchange),
SOC_ENUM("Charge Pump Frequency", da7218_cp_fcontrol),
SOC_ENUM("Charge Pump Decay Rate", da7218_cp_tau_delay),
SOC_SINGLE("Charge Pump Threshold", DA7218_CP_VOL_THRESHOLD1,
DA7218_CP_THRESH_VDD2_SHIFT, DA7218_CP_THRESH_VDD2_MAX,
DA7218_NO_INVERT),
/* Headphones */
SOC_DOUBLE_R_RANGE_TLV("Headphone Volume", DA7218_HP_L_GAIN,
DA7218_HP_R_GAIN, DA7218_HP_L_AMP_GAIN_SHIFT,
DA7218_HP_AMP_GAIN_MIN, DA7218_HP_AMP_GAIN_MAX,
DA7218_NO_INVERT, da7218_hp_gain_tlv),
SOC_DOUBLE_R("Headphone Switch", DA7218_HP_L_CTRL, DA7218_HP_R_CTRL,
DA7218_HP_L_AMP_MUTE_EN_SHIFT, DA7218_SWITCH_EN_MAX,
DA7218_INVERT),
SOC_DOUBLE_R("Headphone Gain Ramp Switch", DA7218_HP_L_CTRL,
DA7218_HP_R_CTRL, DA7218_HP_L_AMP_RAMP_EN_SHIFT,
DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT),
SOC_DOUBLE_R("Headphone ZC Gain Switch", DA7218_HP_L_CTRL,
DA7218_HP_R_CTRL, DA7218_HP_L_AMP_ZC_EN_SHIFT,
DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT),
};
/*
* DAPM Mux Controls
*/
static const char * const da7218_mic_sel_text[] = { "Analog", "Digital" };
static const struct soc_enum da7218_mic1_sel =
SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(da7218_mic_sel_text),
da7218_mic_sel_text);
static const struct snd_kcontrol_new da7218_mic1_sel_mux =
SOC_DAPM_ENUM("Mic1 Mux", da7218_mic1_sel);
static const struct soc_enum da7218_mic2_sel =
SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(da7218_mic_sel_text),
da7218_mic_sel_text);
static const struct snd_kcontrol_new da7218_mic2_sel_mux =
SOC_DAPM_ENUM("Mic2 Mux", da7218_mic2_sel);
static const char * const da7218_sidetone_in_sel_txt[] = {
"In Filter1L", "In Filter1R", "In Filter2L", "In Filter2R"
};
static const struct soc_enum da7218_sidetone_in_sel =
SOC_ENUM_SINGLE(DA7218_SIDETONE_IN_SELECT,
DA7218_SIDETONE_IN_SELECT_SHIFT,
DA7218_SIDETONE_IN_SELECT_MAX,
da7218_sidetone_in_sel_txt);
static const struct snd_kcontrol_new da7218_sidetone_in_sel_mux =
SOC_DAPM_ENUM("Sidetone Mux", da7218_sidetone_in_sel);
static const char * const da7218_out_filt_biq_sel_txt[] = {
"Bypass", "Enabled"
};
static const struct soc_enum da7218_out_filtl_biq_sel =
SOC_ENUM_SINGLE(DA7218_OUT_1L_FILTER_CTRL,
DA7218_OUT_1L_BIQ_5STAGE_SEL_SHIFT,
DA7218_OUT_BIQ_5STAGE_SEL_MAX,
da7218_out_filt_biq_sel_txt);
static const struct snd_kcontrol_new da7218_out_filtl_biq_sel_mux =
SOC_DAPM_ENUM("Out FilterL BiQuad Mux", da7218_out_filtl_biq_sel);
static const struct soc_enum da7218_out_filtr_biq_sel =
SOC_ENUM_SINGLE(DA7218_OUT_1R_FILTER_CTRL,
DA7218_OUT_1R_BIQ_5STAGE_SEL_SHIFT,
DA7218_OUT_BIQ_5STAGE_SEL_MAX,
da7218_out_filt_biq_sel_txt);
static const struct snd_kcontrol_new da7218_out_filtr_biq_sel_mux =
SOC_DAPM_ENUM("Out FilterR BiQuad Mux", da7218_out_filtr_biq_sel);
/*
* DAPM Mixer Controls
*/
#define DA7218_DMIX_CTRLS(reg) \
SOC_DAPM_SINGLE("In Filter1L Switch", reg, \
DA7218_DMIX_SRC_INFILT1L, \
DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT), \
SOC_DAPM_SINGLE("In Filter1R Switch", reg, \
DA7218_DMIX_SRC_INFILT1R, \
DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT), \
SOC_DAPM_SINGLE("In Filter2L Switch", reg, \
DA7218_DMIX_SRC_INFILT2L, \
DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT), \
SOC_DAPM_SINGLE("In Filter2R Switch", reg, \
DA7218_DMIX_SRC_INFILT2R, \
DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT), \
SOC_DAPM_SINGLE("ToneGen Switch", reg, \
DA7218_DMIX_SRC_TONEGEN, \
DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT), \
SOC_DAPM_SINGLE("DAIL Switch", reg, DA7218_DMIX_SRC_DAIL, \
DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT), \
SOC_DAPM_SINGLE("DAIR Switch", reg, DA7218_DMIX_SRC_DAIR, \
DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT)
static const struct snd_kcontrol_new da7218_out_dai1l_mix_controls[] = {
DA7218_DMIX_CTRLS(DA7218_DROUTING_OUTDAI_1L),
};
static const struct snd_kcontrol_new da7218_out_dai1r_mix_controls[] = {
DA7218_DMIX_CTRLS(DA7218_DROUTING_OUTDAI_1R),
};
static const struct snd_kcontrol_new da7218_out_dai2l_mix_controls[] = {
DA7218_DMIX_CTRLS(DA7218_DROUTING_OUTDAI_2L),
};
static const struct snd_kcontrol_new da7218_out_dai2r_mix_controls[] = {
DA7218_DMIX_CTRLS(DA7218_DROUTING_OUTDAI_2R),
};
static const struct snd_kcontrol_new da7218_out_filtl_mix_controls[] = {
DA7218_DMIX_CTRLS(DA7218_DROUTING_OUTFILT_1L),
};
static const struct snd_kcontrol_new da7218_out_filtr_mix_controls[] = {
DA7218_DMIX_CTRLS(DA7218_DROUTING_OUTFILT_1R),
};
#define DA7218_DMIX_ST_CTRLS(reg) \
SOC_DAPM_SINGLE("Out FilterL Switch", reg, \
DA7218_DMIX_ST_SRC_OUTFILT1L, \
DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT), \
SOC_DAPM_SINGLE("Out FilterR Switch", reg, \
DA7218_DMIX_ST_SRC_OUTFILT1R, \
DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT), \
SOC_DAPM_SINGLE("Sidetone Switch", reg, \
DA7218_DMIX_ST_SRC_SIDETONE, \
DA7218_SWITCH_EN_MAX, DA7218_NO_INVERT) \
static const struct snd_kcontrol_new da7218_st_out_filtl_mix_controls[] = {
DA7218_DMIX_ST_CTRLS(DA7218_DROUTING_ST_OUTFILT_1L),
};
static const struct snd_kcontrol_new da7218_st_out_filtr_mix_controls[] = {
DA7218_DMIX_ST_CTRLS(DA7218_DROUTING_ST_OUTFILT_1R),
};
/*
* DAPM Events
*/
/*
* We keep track of which input filters are enabled. This is used in the logic
* for controlling the mic level detect feature.
*/
static int da7218_in_filter_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
u8 mask;
switch (w->reg) {
case DA7218_IN_1L_FILTER_CTRL:
mask = (1 << DA7218_LVL_DET_EN_CHAN1L_SHIFT);
break;
case DA7218_IN_1R_FILTER_CTRL:
mask = (1 << DA7218_LVL_DET_EN_CHAN1R_SHIFT);
break;
case DA7218_IN_2L_FILTER_CTRL:
mask = (1 << DA7218_LVL_DET_EN_CHAN2L_SHIFT);
break;
case DA7218_IN_2R_FILTER_CTRL:
mask = (1 << DA7218_LVL_DET_EN_CHAN2R_SHIFT);
break;
default:
return -EINVAL;
}
switch (event) {
case SND_SOC_DAPM_POST_PMU:
da7218->in_filt_en |= mask;
/*
* If we're enabling path for mic level detect, wait for path
* to settle before enabling feature to avoid incorrect and
* unwanted detect events.
*/
if (mask & da7218->mic_lvl_det_en)
msleep(DA7218_MIC_LVL_DET_DELAY);
break;
case SND_SOC_DAPM_PRE_PMD:
da7218->in_filt_en &= ~mask;
break;
default:
return -EINVAL;
}
/* Enable configured level detection paths */
snd_soc_component_write(component, DA7218_LVL_DET_CTRL,
(da7218->in_filt_en & da7218->mic_lvl_det_en));
return 0;
}
static int da7218_dai_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
u8 pll_ctrl, pll_status, refosc_cal;
int i;
bool success;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
if (da7218->master)
/* Enable DAI clks for master mode */
snd_soc_component_update_bits(component, DA7218_DAI_CLK_MODE,
DA7218_DAI_CLK_EN_MASK,
DA7218_DAI_CLK_EN_MASK);
/* Tune reference oscillator */
snd_soc_component_write(component, DA7218_PLL_REFOSC_CAL,
DA7218_PLL_REFOSC_CAL_START_MASK);
snd_soc_component_write(component, DA7218_PLL_REFOSC_CAL,
DA7218_PLL_REFOSC_CAL_START_MASK |
DA7218_PLL_REFOSC_CAL_EN_MASK);
/* Check tuning complete */
i = 0;
success = false;
do {
refosc_cal = snd_soc_component_read(component, DA7218_PLL_REFOSC_CAL);
if (!(refosc_cal & DA7218_PLL_REFOSC_CAL_START_MASK)) {
success = true;
} else {
++i;
usleep_range(DA7218_REF_OSC_CHECK_DELAY_MIN,
DA7218_REF_OSC_CHECK_DELAY_MAX);
}
} while ((i < DA7218_REF_OSC_CHECK_TRIES) && (!success));
if (!success)
dev_warn(component->dev,
"Reference oscillator failed calibration\n");
/* PC synchronised to DAI */
snd_soc_component_write(component, DA7218_PC_COUNT,
DA7218_PC_RESYNC_AUTO_MASK);
/* If SRM not enabled, we don't need to check status */
pll_ctrl = snd_soc_component_read(component, DA7218_PLL_CTRL);
if ((pll_ctrl & DA7218_PLL_MODE_MASK) != DA7218_PLL_MODE_SRM)
return 0;
/* Check SRM has locked */
i = 0;
success = false;
do {
pll_status = snd_soc_component_read(component, DA7218_PLL_STATUS);
if (pll_status & DA7218_PLL_SRM_STATUS_SRM_LOCK) {
success = true;
} else {
++i;
msleep(DA7218_SRM_CHECK_DELAY);
}
} while ((i < DA7218_SRM_CHECK_TRIES) && (!success));
if (!success)
dev_warn(component->dev, "SRM failed to lock\n");
return 0;
case SND_SOC_DAPM_POST_PMD:
/* PC free-running */
snd_soc_component_write(component, DA7218_PC_COUNT, DA7218_PC_FREERUN_MASK);
if (da7218->master)
/* Disable DAI clks for master mode */
snd_soc_component_update_bits(component, DA7218_DAI_CLK_MODE,
DA7218_DAI_CLK_EN_MASK, 0);
return 0;
default:
return -EINVAL;
}
}
static int da7218_cp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
/*
* If this is DA7217 and we're using single supply for differential
* output, we really don't want to touch the charge pump.
*/
if (da7218->hp_single_supply)
return 0;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_component_update_bits(component, DA7218_CP_CTRL, DA7218_CP_EN_MASK,
DA7218_CP_EN_MASK);
return 0;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, DA7218_CP_CTRL, DA7218_CP_EN_MASK,
0);
return 0;
default:
return -EINVAL;
}
}
static int da7218_hp_pga_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
/* Enable headphone output */
snd_soc_component_update_bits(component, w->reg, DA7218_HP_AMP_OE_MASK,
DA7218_HP_AMP_OE_MASK);
return 0;
case SND_SOC_DAPM_PRE_PMD:
/* Headphone output high impedance */
snd_soc_component_update_bits(component, w->reg, DA7218_HP_AMP_OE_MASK, 0);
return 0;
default:
return -EINVAL;
}
}
/*
* DAPM Widgets
*/
static const struct snd_soc_dapm_widget da7218_dapm_widgets[] = {
/* Input Supplies */
SND_SOC_DAPM_SUPPLY("Mic Bias1", DA7218_MICBIAS_EN,
DA7218_MICBIAS_1_EN_SHIFT, DA7218_NO_INVERT,
NULL, 0),
SND_SOC_DAPM_SUPPLY("Mic Bias2", DA7218_MICBIAS_EN,
DA7218_MICBIAS_2_EN_SHIFT, DA7218_NO_INVERT,
NULL, 0),
SND_SOC_DAPM_SUPPLY("DMic1 Left", DA7218_DMIC_1_CTRL,
DA7218_DMIC_1L_EN_SHIFT, DA7218_NO_INVERT,
NULL, 0),
SND_SOC_DAPM_SUPPLY("DMic1 Right", DA7218_DMIC_1_CTRL,
DA7218_DMIC_1R_EN_SHIFT, DA7218_NO_INVERT,
NULL, 0),
SND_SOC_DAPM_SUPPLY("DMic2 Left", DA7218_DMIC_2_CTRL,
DA7218_DMIC_2L_EN_SHIFT, DA7218_NO_INVERT,
NULL, 0),
SND_SOC_DAPM_SUPPLY("DMic2 Right", DA7218_DMIC_2_CTRL,
DA7218_DMIC_2R_EN_SHIFT, DA7218_NO_INVERT,
NULL, 0),
/* Inputs */
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_INPUT("MIC2"),
SND_SOC_DAPM_INPUT("DMIC1L"),
SND_SOC_DAPM_INPUT("DMIC1R"),
SND_SOC_DAPM_INPUT("DMIC2L"),
SND_SOC_DAPM_INPUT("DMIC2R"),
/* Input Mixer Supplies */
SND_SOC_DAPM_SUPPLY("Mixin1 Supply", DA7218_MIXIN_1_CTRL,
DA7218_MIXIN_1_MIX_SEL_SHIFT, DA7218_NO_INVERT,
NULL, 0),
SND_SOC_DAPM_SUPPLY("Mixin2 Supply", DA7218_MIXIN_2_CTRL,
DA7218_MIXIN_2_MIX_SEL_SHIFT, DA7218_NO_INVERT,
NULL, 0),
/* Input PGAs */
SND_SOC_DAPM_PGA("Mic1 PGA", DA7218_MIC_1_CTRL,
DA7218_MIC_1_AMP_EN_SHIFT, DA7218_NO_INVERT,
NULL, 0),
SND_SOC_DAPM_PGA("Mic2 PGA", DA7218_MIC_2_CTRL,
DA7218_MIC_2_AMP_EN_SHIFT, DA7218_NO_INVERT,
NULL, 0),
SND_SOC_DAPM_PGA("Mixin1 PGA", DA7218_MIXIN_1_CTRL,
DA7218_MIXIN_1_AMP_EN_SHIFT, DA7218_NO_INVERT,
NULL, 0),
SND_SOC_DAPM_PGA("Mixin2 PGA", DA7218_MIXIN_2_CTRL,
DA7218_MIXIN_2_AMP_EN_SHIFT, DA7218_NO_INVERT,
NULL, 0),
/* Mic/DMic Muxes */
SND_SOC_DAPM_MUX("Mic1 Mux", SND_SOC_NOPM, 0, 0, &da7218_mic1_sel_mux),
SND_SOC_DAPM_MUX("Mic2 Mux", SND_SOC_NOPM, 0, 0, &da7218_mic2_sel_mux),
/* Input Filters */
SND_SOC_DAPM_ADC_E("In Filter1L", NULL, DA7218_IN_1L_FILTER_CTRL,
DA7218_IN_1L_FILTER_EN_SHIFT, DA7218_NO_INVERT,
da7218_in_filter_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_ADC_E("In Filter1R", NULL, DA7218_IN_1R_FILTER_CTRL,
DA7218_IN_1R_FILTER_EN_SHIFT, DA7218_NO_INVERT,
da7218_in_filter_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_ADC_E("In Filter2L", NULL, DA7218_IN_2L_FILTER_CTRL,
DA7218_IN_2L_FILTER_EN_SHIFT, DA7218_NO_INVERT,
da7218_in_filter_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_ADC_E("In Filter2R", NULL, DA7218_IN_2R_FILTER_CTRL,
DA7218_IN_2R_FILTER_EN_SHIFT, DA7218_NO_INVERT,
da7218_in_filter_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
/* Tone Generator */
SND_SOC_DAPM_SIGGEN("TONE"),
SND_SOC_DAPM_PGA("Tone Generator", DA7218_TONE_GEN_CFG1,
DA7218_START_STOPN_SHIFT, DA7218_NO_INVERT, NULL, 0),
/* Sidetone Input */
SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
&da7218_sidetone_in_sel_mux),
SND_SOC_DAPM_ADC("Sidetone Filter", NULL, DA7218_SIDETONE_CTRL,
DA7218_SIDETONE_FILTER_EN_SHIFT, DA7218_NO_INVERT),
/* Input Mixers */
SND_SOC_DAPM_MIXER("Mixer DAI1L", SND_SOC_NOPM, 0, 0,
da7218_out_dai1l_mix_controls,
ARRAY_SIZE(da7218_out_dai1l_mix_controls)),
SND_SOC_DAPM_MIXER("Mixer DAI1R", SND_SOC_NOPM, 0, 0,
da7218_out_dai1r_mix_controls,
ARRAY_SIZE(da7218_out_dai1r_mix_controls)),
SND_SOC_DAPM_MIXER("Mixer DAI2L", SND_SOC_NOPM, 0, 0,
da7218_out_dai2l_mix_controls,
ARRAY_SIZE(da7218_out_dai2l_mix_controls)),
SND_SOC_DAPM_MIXER("Mixer DAI2R", SND_SOC_NOPM, 0, 0,
da7218_out_dai2r_mix_controls,
ARRAY_SIZE(da7218_out_dai2r_mix_controls)),
/* DAI Supply */
SND_SOC_DAPM_SUPPLY("DAI", DA7218_DAI_CTRL, DA7218_DAI_EN_SHIFT,
DA7218_NO_INVERT, da7218_dai_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
/* DAI */
SND_SOC_DAPM_AIF_OUT("DAIOUT", "Capture", 0, DA7218_DAI_TDM_CTRL,
DA7218_DAI_OE_SHIFT, DA7218_NO_INVERT),
SND_SOC_DAPM_AIF_IN("DAIIN", "Playback", 0, SND_SOC_NOPM, 0, 0),
/* Output Mixers */
SND_SOC_DAPM_MIXER("Mixer Out FilterL", SND_SOC_NOPM, 0, 0,
da7218_out_filtl_mix_controls,
ARRAY_SIZE(da7218_out_filtl_mix_controls)),
SND_SOC_DAPM_MIXER("Mixer Out FilterR", SND_SOC_NOPM, 0, 0,
da7218_out_filtr_mix_controls,
ARRAY_SIZE(da7218_out_filtr_mix_controls)),
/* BiQuad Filters */
SND_SOC_DAPM_MUX("Out FilterL BiQuad Mux", SND_SOC_NOPM, 0, 0,
&da7218_out_filtl_biq_sel_mux),
SND_SOC_DAPM_MUX("Out FilterR BiQuad Mux", SND_SOC_NOPM, 0, 0,
&da7218_out_filtr_biq_sel_mux),
SND_SOC_DAPM_DAC("BiQuad Filter", NULL, DA7218_OUT_1_BIQ_5STAGE_CTRL,
DA7218_OUT_1_BIQ_5STAGE_FILTER_EN_SHIFT,
DA7218_NO_INVERT),
/* Sidetone Mixers */
SND_SOC_DAPM_MIXER("ST Mixer Out FilterL", SND_SOC_NOPM, 0, 0,
da7218_st_out_filtl_mix_controls,
ARRAY_SIZE(da7218_st_out_filtl_mix_controls)),
SND_SOC_DAPM_MIXER("ST Mixer Out FilterR", SND_SOC_NOPM, 0, 0,
da7218_st_out_filtr_mix_controls,
ARRAY_SIZE(da7218_st_out_filtr_mix_controls)),
/* Output Filters */
SND_SOC_DAPM_DAC("Out FilterL", NULL, DA7218_OUT_1L_FILTER_CTRL,
DA7218_OUT_1L_FILTER_EN_SHIFT, DA7218_NO_INVERT),
SND_SOC_DAPM_DAC("Out FilterR", NULL, DA7218_OUT_1R_FILTER_CTRL,
DA7218_IN_1R_FILTER_EN_SHIFT, DA7218_NO_INVERT),
/* Output PGAs */
SND_SOC_DAPM_PGA("Mixout Left PGA", DA7218_MIXOUT_L_CTRL,
DA7218_MIXOUT_L_AMP_EN_SHIFT, DA7218_NO_INVERT,
NULL, 0),
SND_SOC_DAPM_PGA("Mixout Right PGA", DA7218_MIXOUT_R_CTRL,
DA7218_MIXOUT_R_AMP_EN_SHIFT, DA7218_NO_INVERT,
NULL, 0),
SND_SOC_DAPM_PGA_E("Headphone Left PGA", DA7218_HP_L_CTRL,
DA7218_HP_L_AMP_EN_SHIFT, DA7218_NO_INVERT, NULL, 0,
da7218_hp_pga_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA_E("Headphone Right PGA", DA7218_HP_R_CTRL,
DA7218_HP_R_AMP_EN_SHIFT, DA7218_NO_INVERT, NULL, 0,
da7218_hp_pga_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
/* Output Supplies */
SND_SOC_DAPM_SUPPLY("Charge Pump", SND_SOC_NOPM, 0, 0, da7218_cp_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
/* Outputs */
SND_SOC_DAPM_OUTPUT("HPL"),
SND_SOC_DAPM_OUTPUT("HPR"),
};
/*
* DAPM Mixer Routes
*/
#define DA7218_DMIX_ROUTES(name) \
{name, "In Filter1L Switch", "In Filter1L"}, \
{name, "In Filter1R Switch", "In Filter1R"}, \
{name, "In Filter2L Switch", "In Filter2L"}, \
{name, "In Filter2R Switch", "In Filter2R"}, \
{name, "ToneGen Switch", "Tone Generator"}, \
{name, "DAIL Switch", "DAIIN"}, \
{name, "DAIR Switch", "DAIIN"}
#define DA7218_DMIX_ST_ROUTES(name) \
{name, "Out FilterL Switch", "Out FilterL BiQuad Mux"}, \
{name, "Out FilterR Switch", "Out FilterR BiQuad Mux"}, \
{name, "Sidetone Switch", "Sidetone Filter"}
/*
* DAPM audio route definition
*/
static const struct snd_soc_dapm_route da7218_audio_map[] = {
/* Input paths */
{"MIC1", NULL, "Mic Bias1"},
{"MIC2", NULL, "Mic Bias2"},
{"DMIC1L", NULL, "Mic Bias1"},
{"DMIC1L", NULL, "DMic1 Left"},
{"DMIC1R", NULL, "Mic Bias1"},
{"DMIC1R", NULL, "DMic1 Right"},
{"DMIC2L", NULL, "Mic Bias2"},
{"DMIC2L", NULL, "DMic2 Left"},
{"DMIC2R", NULL, "Mic Bias2"},
{"DMIC2R", NULL, "DMic2 Right"},
{"Mic1 PGA", NULL, "MIC1"},
{"Mic2 PGA", NULL, "MIC2"},
{"Mixin1 PGA", NULL, "Mixin1 Supply"},
{"Mixin2 PGA", NULL, "Mixin2 Supply"},
{"Mixin1 PGA", NULL, "Mic1 PGA"},
{"Mixin2 PGA", NULL, "Mic2 PGA"},
{"Mic1 Mux", "Analog", "Mixin1 PGA"},
{"Mic1 Mux", "Digital", "DMIC1L"},
{"Mic1 Mux", "Digital", "DMIC1R"},
{"Mic2 Mux", "Analog", "Mixin2 PGA"},
{"Mic2 Mux", "Digital", "DMIC2L"},
{"Mic2 Mux", "Digital", "DMIC2R"},
{"In Filter1L", NULL, "Mic1 Mux"},
{"In Filter1R", NULL, "Mic1 Mux"},
{"In Filter2L", NULL, "Mic2 Mux"},
{"In Filter2R", NULL, "Mic2 Mux"},
{"Tone Generator", NULL, "TONE"},
{"Sidetone Mux", "In Filter1L", "In Filter1L"},
{"Sidetone Mux", "In Filter1R", "In Filter1R"},
{"Sidetone Mux", "In Filter2L", "In Filter2L"},
{"Sidetone Mux", "In Filter2R", "In Filter2R"},
{"Sidetone Filter", NULL, "Sidetone Mux"},
DA7218_DMIX_ROUTES("Mixer DAI1L"),
DA7218_DMIX_ROUTES("Mixer DAI1R"),
DA7218_DMIX_ROUTES("Mixer DAI2L"),
DA7218_DMIX_ROUTES("Mixer DAI2R"),
{"DAIOUT", NULL, "Mixer DAI1L"},
{"DAIOUT", NULL, "Mixer DAI1R"},
{"DAIOUT", NULL, "Mixer DAI2L"},
{"DAIOUT", NULL, "Mixer DAI2R"},
{"DAIOUT", NULL, "DAI"},
/* Output paths */
{"DAIIN", NULL, "DAI"},
DA7218_DMIX_ROUTES("Mixer Out FilterL"),
DA7218_DMIX_ROUTES("Mixer Out FilterR"),
{"BiQuad Filter", NULL, "Mixer Out FilterL"},
{"BiQuad Filter", NULL, "Mixer Out FilterR"},
{"Out FilterL BiQuad Mux", "Bypass", "Mixer Out FilterL"},
{"Out FilterL BiQuad Mux", "Enabled", "BiQuad Filter"},
{"Out FilterR BiQuad Mux", "Bypass", "Mixer Out FilterR"},
{"Out FilterR BiQuad Mux", "Enabled", "BiQuad Filter"},
DA7218_DMIX_ST_ROUTES("ST Mixer Out FilterL"),
DA7218_DMIX_ST_ROUTES("ST Mixer Out FilterR"),
{"Out FilterL", NULL, "ST Mixer Out FilterL"},
{"Out FilterR", NULL, "ST Mixer Out FilterR"},
{"Mixout Left PGA", NULL, "Out FilterL"},
{"Mixout Right PGA", NULL, "Out FilterR"},
{"Headphone Left PGA", NULL, "Mixout Left PGA"},
{"Headphone Right PGA", NULL, "Mixout Right PGA"},
{"HPL", NULL, "Headphone Left PGA"},
{"HPR", NULL, "Headphone Right PGA"},
{"HPL", NULL, "Charge Pump"},
{"HPR", NULL, "Charge Pump"},
};
/*
* DAI operations
*/
static int da7218_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
int ret;
if (da7218->mclk_rate == freq)
return 0;
if ((freq < 2000000) || (freq > 54000000)) {
dev_err(codec_dai->dev, "Unsupported MCLK value %d\n",
freq);
return -EINVAL;
}
switch (clk_id) {
case DA7218_CLKSRC_MCLK_SQR:
snd_soc_component_update_bits(component, DA7218_PLL_CTRL,
DA7218_PLL_MCLK_SQR_EN_MASK,
DA7218_PLL_MCLK_SQR_EN_MASK);
break;
case DA7218_CLKSRC_MCLK:
snd_soc_component_update_bits(component, DA7218_PLL_CTRL,
DA7218_PLL_MCLK_SQR_EN_MASK, 0);
break;
default:
dev_err(codec_dai->dev, "Unknown clock source %d\n", clk_id);
return -EINVAL;
}
if (da7218->mclk) {
freq = clk_round_rate(da7218->mclk, freq);
ret = clk_set_rate(da7218->mclk, freq);
if (ret) {
dev_err(codec_dai->dev, "Failed to set clock rate %d\n",
freq);
return ret;
}
}
da7218->mclk_rate = freq;
return 0;
}
static int da7218_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
int source, unsigned int fref, unsigned int fout)
{
struct snd_soc_component *component = codec_dai->component;
struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
u8 pll_ctrl, indiv_bits, indiv;
u8 pll_frac_top, pll_frac_bot, pll_integer;
u32 freq_ref;
u64 frac_div;
/* Verify 2MHz - 54MHz MCLK provided, and set input divider */
if (da7218->mclk_rate < 2000000) {
dev_err(component->dev, "PLL input clock %d below valid range\n",
da7218->mclk_rate);
return -EINVAL;
} else if (da7218->mclk_rate <= 4500000) {
indiv_bits = DA7218_PLL_INDIV_2_TO_4_5_MHZ;
indiv = DA7218_PLL_INDIV_2_TO_4_5_MHZ_VAL;
} else if (da7218->mclk_rate <= 9000000) {
indiv_bits = DA7218_PLL_INDIV_4_5_TO_9_MHZ;
indiv = DA7218_PLL_INDIV_4_5_TO_9_MHZ_VAL;
} else if (da7218->mclk_rate <= 18000000) {
indiv_bits = DA7218_PLL_INDIV_9_TO_18_MHZ;
indiv = DA7218_PLL_INDIV_9_TO_18_MHZ_VAL;
} else if (da7218->mclk_rate <= 36000000) {
indiv_bits = DA7218_PLL_INDIV_18_TO_36_MHZ;
indiv = DA7218_PLL_INDIV_18_TO_36_MHZ_VAL;
} else if (da7218->mclk_rate <= 54000000) {
indiv_bits = DA7218_PLL_INDIV_36_TO_54_MHZ;
indiv = DA7218_PLL_INDIV_36_TO_54_MHZ_VAL;
} else {
dev_err(component->dev, "PLL input clock %d above valid range\n",
da7218->mclk_rate);
return -EINVAL;
}
freq_ref = (da7218->mclk_rate / indiv);
pll_ctrl = indiv_bits;
/* Configure PLL */
switch (source) {
case DA7218_SYSCLK_MCLK:
pll_ctrl |= DA7218_PLL_MODE_BYPASS;
snd_soc_component_update_bits(component, DA7218_PLL_CTRL,
DA7218_PLL_INDIV_MASK |
DA7218_PLL_MODE_MASK, pll_ctrl);
return 0;
case DA7218_SYSCLK_PLL:
pll_ctrl |= DA7218_PLL_MODE_NORMAL;
break;
case DA7218_SYSCLK_PLL_SRM:
pll_ctrl |= DA7218_PLL_MODE_SRM;
break;
default:
dev_err(component->dev, "Invalid PLL config\n");
return -EINVAL;
}
/* Calculate dividers for PLL */
pll_integer = fout / freq_ref;
frac_div = (u64)(fout % freq_ref) * 8192ULL;
do_div(frac_div, freq_ref);
pll_frac_top = (frac_div >> DA7218_BYTE_SHIFT) & DA7218_BYTE_MASK;
pll_frac_bot = (frac_div) & DA7218_BYTE_MASK;
/* Write PLL config & dividers */
snd_soc_component_write(component, DA7218_PLL_FRAC_TOP, pll_frac_top);
snd_soc_component_write(component, DA7218_PLL_FRAC_BOT, pll_frac_bot);
snd_soc_component_write(component, DA7218_PLL_INTEGER, pll_integer);
snd_soc_component_update_bits(component, DA7218_PLL_CTRL,
DA7218_PLL_MODE_MASK | DA7218_PLL_INDIV_MASK,
pll_ctrl);
return 0;
}
static int da7218_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
u8 dai_clk_mode = 0, dai_ctrl = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
da7218->master = true;
break;
case SND_SOC_DAIFMT_CBS_CFS:
da7218->master = false;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_LEFT_J:
case SND_SOC_DAIFMT_RIGHT_J:
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_NB_IF:
dai_clk_mode |= DA7218_DAI_WCLK_POL_INV;
break;
case SND_SOC_DAIFMT_IB_NF:
dai_clk_mode |= DA7218_DAI_CLK_POL_INV;
break;
case SND_SOC_DAIFMT_IB_IF:
dai_clk_mode |= DA7218_DAI_WCLK_POL_INV |
DA7218_DAI_CLK_POL_INV;
break;
default:
return -EINVAL;
}
break;
case SND_SOC_DAIFMT_DSP_B:
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
dai_clk_mode |= DA7218_DAI_CLK_POL_INV;
break;
case SND_SOC_DAIFMT_NB_IF:
dai_clk_mode |= DA7218_DAI_WCLK_POL_INV |
DA7218_DAI_CLK_POL_INV;
break;
case SND_SOC_DAIFMT_IB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
dai_clk_mode |= DA7218_DAI_WCLK_POL_INV;
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
dai_ctrl |= DA7218_DAI_FORMAT_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
dai_ctrl |= DA7218_DAI_FORMAT_LEFT_J;
break;
case SND_SOC_DAIFMT_RIGHT_J:
dai_ctrl |= DA7218_DAI_FORMAT_RIGHT_J;
break;
case SND_SOC_DAIFMT_DSP_B:
dai_ctrl |= DA7218_DAI_FORMAT_DSP;
break;
default:
return -EINVAL;
}
/* By default 64 BCLKs per WCLK is supported */
dai_clk_mode |= DA7218_DAI_BCLKS_PER_WCLK_64;
snd_soc_component_write(component, DA7218_DAI_CLK_MODE, dai_clk_mode);
snd_soc_component_update_bits(component, DA7218_DAI_CTRL, DA7218_DAI_FORMAT_MASK,
dai_ctrl);
return 0;
}
static int da7218_set_dai_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask,
int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
u8 dai_bclks_per_wclk;
u32 frame_size;
/* No channels enabled so disable TDM, revert to 64-bit frames */
if (!tx_mask) {
snd_soc_component_update_bits(component, DA7218_DAI_TDM_CTRL,
DA7218_DAI_TDM_CH_EN_MASK |
DA7218_DAI_TDM_MODE_EN_MASK, 0);
snd_soc_component_update_bits(component, DA7218_DAI_CLK_MODE,
DA7218_DAI_BCLKS_PER_WCLK_MASK,
DA7218_DAI_BCLKS_PER_WCLK_64);
return 0;
}
/* Check we have valid slots */
if (fls(tx_mask) > DA7218_DAI_TDM_MAX_SLOTS) {
dev_err(component->dev, "Invalid number of slots, max = %d\n",
DA7218_DAI_TDM_MAX_SLOTS);
return -EINVAL;
}
/* Check we have a valid offset given (first 2 bytes of rx_mask) */
if (rx_mask >> DA7218_2BYTE_SHIFT) {
dev_err(component->dev, "Invalid slot offset, max = %d\n",
DA7218_2BYTE_MASK);
return -EINVAL;
}
/* Calculate & validate frame size based on slot info provided. */
frame_size = slots * slot_width;
switch (frame_size) {
case 32:
dai_bclks_per_wclk = DA7218_DAI_BCLKS_PER_WCLK_32;
break;
case 64:
dai_bclks_per_wclk = DA7218_DAI_BCLKS_PER_WCLK_64;
break;
case 128:
dai_bclks_per_wclk = DA7218_DAI_BCLKS_PER_WCLK_128;
break;
case 256:
dai_bclks_per_wclk = DA7218_DAI_BCLKS_PER_WCLK_256;
break;
default:
dev_err(component->dev, "Invalid frame size\n");
return -EINVAL;
}
snd_soc_component_update_bits(component, DA7218_DAI_CLK_MODE,
DA7218_DAI_BCLKS_PER_WCLK_MASK,
dai_bclks_per_wclk);
snd_soc_component_write(component, DA7218_DAI_OFFSET_LOWER,
(rx_mask & DA7218_BYTE_MASK));
snd_soc_component_write(component, DA7218_DAI_OFFSET_UPPER,
((rx_mask >> DA7218_BYTE_SHIFT) & DA7218_BYTE_MASK));
snd_soc_component_update_bits(component, DA7218_DAI_TDM_CTRL,
DA7218_DAI_TDM_CH_EN_MASK |
DA7218_DAI_TDM_MODE_EN_MASK,
(tx_mask << DA7218_DAI_TDM_CH_EN_SHIFT) |
DA7218_DAI_TDM_MODE_EN_MASK);
return 0;
}
static int da7218_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
u8 dai_ctrl = 0, fs;
unsigned int channels;
switch (params_width(params)) {
case 16:
dai_ctrl |= DA7218_DAI_WORD_LENGTH_S16_LE;
break;
case 20:
dai_ctrl |= DA7218_DAI_WORD_LENGTH_S20_LE;
break;
case 24:
dai_ctrl |= DA7218_DAI_WORD_LENGTH_S24_LE;
break;
case 32:
dai_ctrl |= DA7218_DAI_WORD_LENGTH_S32_LE;
break;
default:
return -EINVAL;
}
channels = params_channels(params);
if ((channels < 1) || (channels > DA7218_DAI_CH_NUM_MAX)) {
dev_err(component->dev,
"Invalid number of channels, only 1 to %d supported\n",
DA7218_DAI_CH_NUM_MAX);
return -EINVAL;
}
dai_ctrl |= channels << DA7218_DAI_CH_NUM_SHIFT;
switch (params_rate(params)) {
case 8000:
fs = DA7218_SR_8000;
break;
case 11025:
fs = DA7218_SR_11025;
break;
case 12000:
fs = DA7218_SR_12000;
break;
case 16000:
fs = DA7218_SR_16000;
break;
case 22050:
fs = DA7218_SR_22050;
break;
case 24000:
fs = DA7218_SR_24000;
break;
case 32000:
fs = DA7218_SR_32000;
break;
case 44100:
fs = DA7218_SR_44100;
break;
case 48000:
fs = DA7218_SR_48000;
break;
case 88200:
fs = DA7218_SR_88200;
break;
case 96000:
fs = DA7218_SR_96000;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, DA7218_DAI_CTRL,
DA7218_DAI_WORD_LENGTH_MASK | DA7218_DAI_CH_NUM_MASK,
dai_ctrl);
/* SRs tied for ADCs and DACs. */
snd_soc_component_write(component, DA7218_SR,
(fs << DA7218_SR_DAC_SHIFT) | (fs << DA7218_SR_ADC_SHIFT));
return 0;
}
static const struct snd_soc_dai_ops da7218_dai_ops = {
.hw_params = da7218_hw_params,
.set_sysclk = da7218_set_dai_sysclk,
.set_pll = da7218_set_dai_pll,
.set_fmt = da7218_set_dai_fmt,
.set_tdm_slot = da7218_set_dai_tdm_slot,
};
#define DA7218_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver da7218_dai = {
.name = "da7218-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 4, /* Only 2 channels of data */
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = DA7218_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 4,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = DA7218_FORMATS,
},
.ops = &da7218_dai_ops,
.symmetric_rate = 1,
.symmetric_channels = 1,
.symmetric_sample_bits = 1,
};
/*
* HP Detect
*/
int da7218_hpldet(struct snd_soc_component *component, struct snd_soc_jack *jack)
{
struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
if (da7218->dev_id == DA7217_DEV_ID)
return -EINVAL;
da7218->jack = jack;
snd_soc_component_update_bits(component, DA7218_HPLDET_JACK,
DA7218_HPLDET_JACK_EN_MASK,
jack ? DA7218_HPLDET_JACK_EN_MASK : 0);
return 0;
}
EXPORT_SYMBOL_GPL(da7218_hpldet);
static void da7218_micldet_irq(struct snd_soc_component *component)
{
char *envp[] = {
"EVENT=MIC_LEVEL_DETECT",
NULL,
};
kobject_uevent_env(&component->dev->kobj, KOBJ_CHANGE, envp);
}
static void da7218_hpldet_irq(struct snd_soc_component *component)
{
struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
u8 jack_status;
int report;
jack_status = snd_soc_component_read(component, DA7218_EVENT_STATUS);
if (jack_status & DA7218_HPLDET_JACK_STS_MASK)
report = SND_JACK_HEADPHONE;
else
report = 0;
snd_soc_jack_report(da7218->jack, report, SND_JACK_HEADPHONE);
}
/*
* IRQ
*/
static irqreturn_t da7218_irq_thread(int irq, void *data)
{
struct snd_soc_component *component = data;
u8 status;
/* Read IRQ status reg */
status = snd_soc_component_read(component, DA7218_EVENT);
if (!status)
return IRQ_NONE;
/* Mic level detect */
if (status & DA7218_LVL_DET_EVENT_MASK)
da7218_micldet_irq(component);
/* HP detect */
if (status & DA7218_HPLDET_JACK_EVENT_MASK)
da7218_hpldet_irq(component);
/* Clear interrupts */
snd_soc_component_write(component, DA7218_EVENT, status);
return IRQ_HANDLED;
}
/*
* DT
*/
static const struct of_device_id da7218_of_match[] = {
{ .compatible = "dlg,da7217", .data = (void *) DA7217_DEV_ID },
{ .compatible = "dlg,da7218", .data = (void *) DA7218_DEV_ID },
{ }
};
MODULE_DEVICE_TABLE(of, da7218_of_match);
static inline int da7218_of_get_id(struct device *dev)
{
const struct of_device_id *id = of_match_device(da7218_of_match, dev);
if (id)
return (uintptr_t)id->data;
else
return -EINVAL;
}
static enum da7218_micbias_voltage
da7218_of_micbias_lvl(struct snd_soc_component *component, u32 val)
{
switch (val) {
case 1200:
return DA7218_MICBIAS_1_2V;
case 1600:
return DA7218_MICBIAS_1_6V;
case 1800:
return DA7218_MICBIAS_1_8V;
case 2000:
return DA7218_MICBIAS_2_0V;
case 2200:
return DA7218_MICBIAS_2_2V;
case 2400:
return DA7218_MICBIAS_2_4V;
case 2600:
return DA7218_MICBIAS_2_6V;
case 2800:
return DA7218_MICBIAS_2_8V;
case 3000:
return DA7218_MICBIAS_3_0V;
default:
dev_warn(component->dev, "Invalid micbias level");
return DA7218_MICBIAS_1_6V;
}
}
static enum da7218_mic_amp_in_sel
da7218_of_mic_amp_in_sel(struct snd_soc_component *component, const char *str)
{
if (!strcmp(str, "diff")) {
return DA7218_MIC_AMP_IN_SEL_DIFF;
} else if (!strcmp(str, "se_p")) {
return DA7218_MIC_AMP_IN_SEL_SE_P;
} else if (!strcmp(str, "se_n")) {
return DA7218_MIC_AMP_IN_SEL_SE_N;
} else {
dev_warn(component->dev, "Invalid mic input type selection");
return DA7218_MIC_AMP_IN_SEL_DIFF;
}
}
static enum da7218_dmic_data_sel
da7218_of_dmic_data_sel(struct snd_soc_component *component, const char *str)
{
if (!strcmp(str, "lrise_rfall")) {
return DA7218_DMIC_DATA_LRISE_RFALL;
} else if (!strcmp(str, "lfall_rrise")) {
return DA7218_DMIC_DATA_LFALL_RRISE;
} else {
dev_warn(component->dev, "Invalid DMIC data type selection");
return DA7218_DMIC_DATA_LRISE_RFALL;
}
}
static enum da7218_dmic_samplephase
da7218_of_dmic_samplephase(struct snd_soc_component *component, const char *str)
{
if (!strcmp(str, "on_clkedge")) {
return DA7218_DMIC_SAMPLE_ON_CLKEDGE;
} else if (!strcmp(str, "between_clkedge")) {
return DA7218_DMIC_SAMPLE_BETWEEN_CLKEDGE;
} else {
dev_warn(component->dev, "Invalid DMIC sample phase");
return DA7218_DMIC_SAMPLE_ON_CLKEDGE;
}
}
static enum da7218_dmic_clk_rate
da7218_of_dmic_clkrate(struct snd_soc_component *component, u32 val)
{
switch (val) {
case 1500000:
return DA7218_DMIC_CLK_1_5MHZ;
case 3000000:
return DA7218_DMIC_CLK_3_0MHZ;
default:
dev_warn(component->dev, "Invalid DMIC clock rate");
return DA7218_DMIC_CLK_3_0MHZ;
}
}
static enum da7218_hpldet_jack_rate
da7218_of_jack_rate(struct snd_soc_component *component, u32 val)
{
switch (val) {
case 5:
return DA7218_HPLDET_JACK_RATE_5US;
case 10:
return DA7218_HPLDET_JACK_RATE_10US;
case 20:
return DA7218_HPLDET_JACK_RATE_20US;
case 40:
return DA7218_HPLDET_JACK_RATE_40US;
case 80:
return DA7218_HPLDET_JACK_RATE_80US;
case 160:
return DA7218_HPLDET_JACK_RATE_160US;
case 320:
return DA7218_HPLDET_JACK_RATE_320US;
case 640:
return DA7218_HPLDET_JACK_RATE_640US;
default:
dev_warn(component->dev, "Invalid jack detect rate");
return DA7218_HPLDET_JACK_RATE_40US;
}
}
static enum da7218_hpldet_jack_debounce
da7218_of_jack_debounce(struct snd_soc_component *component, u32 val)
{
switch (val) {
case 0:
return DA7218_HPLDET_JACK_DEBOUNCE_OFF;
case 2:
return DA7218_HPLDET_JACK_DEBOUNCE_2;
case 3:
return DA7218_HPLDET_JACK_DEBOUNCE_3;
case 4:
return DA7218_HPLDET_JACK_DEBOUNCE_4;
default:
dev_warn(component->dev, "Invalid jack debounce");
return DA7218_HPLDET_JACK_DEBOUNCE_2;
}
}
static enum da7218_hpldet_jack_thr
da7218_of_jack_thr(struct snd_soc_component *component, u32 val)
{
switch (val) {
case 84:
return DA7218_HPLDET_JACK_THR_84PCT;
case 88:
return DA7218_HPLDET_JACK_THR_88PCT;
case 92:
return DA7218_HPLDET_JACK_THR_92PCT;
case 96:
return DA7218_HPLDET_JACK_THR_96PCT;
default:
dev_warn(component->dev, "Invalid jack threshold level");
return DA7218_HPLDET_JACK_THR_84PCT;
}
}
static struct da7218_pdata *da7218_of_to_pdata(struct snd_soc_component *component)
{
struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
struct device_node *np = component->dev->of_node;
struct device_node *hpldet_np;
struct da7218_pdata *pdata;
struct da7218_hpldet_pdata *hpldet_pdata;
const char *of_str;
u32 of_val32;
pdata = devm_kzalloc(component->dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return NULL;
if (of_property_read_u32(np, "dlg,micbias1-lvl-millivolt", &of_val32) >= 0)
pdata->micbias1_lvl = da7218_of_micbias_lvl(component, of_val32);
else
pdata->micbias1_lvl = DA7218_MICBIAS_1_6V;
if (of_property_read_u32(np, "dlg,micbias2-lvl-millivolt", &of_val32) >= 0)
pdata->micbias2_lvl = da7218_of_micbias_lvl(component, of_val32);
else
pdata->micbias2_lvl = DA7218_MICBIAS_1_6V;
if (!of_property_read_string(np, "dlg,mic1-amp-in-sel", &of_str))
pdata->mic1_amp_in_sel =
da7218_of_mic_amp_in_sel(component, of_str);
else
pdata->mic1_amp_in_sel = DA7218_MIC_AMP_IN_SEL_DIFF;
if (!of_property_read_string(np, "dlg,mic2-amp-in-sel", &of_str))
pdata->mic2_amp_in_sel =
da7218_of_mic_amp_in_sel(component, of_str);
else
pdata->mic2_amp_in_sel = DA7218_MIC_AMP_IN_SEL_DIFF;
if (!of_property_read_string(np, "dlg,dmic1-data-sel", &of_str))
pdata->dmic1_data_sel = da7218_of_dmic_data_sel(component, of_str);
else
pdata->dmic1_data_sel = DA7218_DMIC_DATA_LRISE_RFALL;
if (!of_property_read_string(np, "dlg,dmic1-samplephase", &of_str))
pdata->dmic1_samplephase =
da7218_of_dmic_samplephase(component, of_str);
else
pdata->dmic1_samplephase = DA7218_DMIC_SAMPLE_ON_CLKEDGE;
if (of_property_read_u32(np, "dlg,dmic1-clkrate-hz", &of_val32) >= 0)
pdata->dmic1_clk_rate = da7218_of_dmic_clkrate(component, of_val32);
else
pdata->dmic1_clk_rate = DA7218_DMIC_CLK_3_0MHZ;
if (!of_property_read_string(np, "dlg,dmic2-data-sel", &of_str))
pdata->dmic2_data_sel = da7218_of_dmic_data_sel(component, of_str);
else
pdata->dmic2_data_sel = DA7218_DMIC_DATA_LRISE_RFALL;
if (!of_property_read_string(np, "dlg,dmic2-samplephase", &of_str))
pdata->dmic2_samplephase =
da7218_of_dmic_samplephase(component, of_str);
else
pdata->dmic2_samplephase = DA7218_DMIC_SAMPLE_ON_CLKEDGE;
if (of_property_read_u32(np, "dlg,dmic2-clkrate-hz", &of_val32) >= 0)
pdata->dmic2_clk_rate = da7218_of_dmic_clkrate(component, of_val32);
else
pdata->dmic2_clk_rate = DA7218_DMIC_CLK_3_0MHZ;
if (da7218->dev_id == DA7217_DEV_ID) {
if (of_property_read_bool(np, "dlg,hp-diff-single-supply"))
pdata->hp_diff_single_supply = true;
}
if (da7218->dev_id == DA7218_DEV_ID) {
hpldet_np = of_get_child_by_name(np, "da7218_hpldet");
if (!hpldet_np)
return pdata;
hpldet_pdata = devm_kzalloc(component->dev, sizeof(*hpldet_pdata),
GFP_KERNEL);
if (!hpldet_pdata) {
of_node_put(hpldet_np);
return pdata;
}
pdata->hpldet_pdata = hpldet_pdata;
if (of_property_read_u32(hpldet_np, "dlg,jack-rate-us",
&of_val32) >= 0)
hpldet_pdata->jack_rate =
da7218_of_jack_rate(component, of_val32);
else
hpldet_pdata->jack_rate = DA7218_HPLDET_JACK_RATE_40US;
if (of_property_read_u32(hpldet_np, "dlg,jack-debounce",
&of_val32) >= 0)
hpldet_pdata->jack_debounce =
da7218_of_jack_debounce(component, of_val32);
else
hpldet_pdata->jack_debounce =
DA7218_HPLDET_JACK_DEBOUNCE_2;
if (of_property_read_u32(hpldet_np, "dlg,jack-threshold-pct",
&of_val32) >= 0)
hpldet_pdata->jack_thr =
da7218_of_jack_thr(component, of_val32);
else
hpldet_pdata->jack_thr = DA7218_HPLDET_JACK_THR_84PCT;
if (of_property_read_bool(hpldet_np, "dlg,comp-inv"))
hpldet_pdata->comp_inv = true;
if (of_property_read_bool(hpldet_np, "dlg,hyst"))
hpldet_pdata->hyst = true;
if (of_property_read_bool(hpldet_np, "dlg,discharge"))
hpldet_pdata->discharge = true;
of_node_put(hpldet_np);
}
return pdata;
}
/*
* Codec driver functions
*/
static int da7218_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
int ret;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
/* Enable MCLK for transition to ON state */
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY) {
if (da7218->mclk) {
ret = clk_prepare_enable(da7218->mclk);
if (ret) {
dev_err(component->dev, "Failed to enable mclk\n");
return ret;
}
}
}
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
/* Master bias */
snd_soc_component_update_bits(component, DA7218_REFERENCES,
DA7218_BIAS_EN_MASK,
DA7218_BIAS_EN_MASK);
/* Internal LDO */
snd_soc_component_update_bits(component, DA7218_LDO_CTRL,
DA7218_LDO_EN_MASK,
DA7218_LDO_EN_MASK);
} else {
/* Remove MCLK */
if (da7218->mclk)
clk_disable_unprepare(da7218->mclk);
}
break;
case SND_SOC_BIAS_OFF:
/* Only disable if jack detection disabled */
if (!da7218->jack) {
/* Internal LDO */
snd_soc_component_update_bits(component, DA7218_LDO_CTRL,
DA7218_LDO_EN_MASK, 0);
/* Master bias */
snd_soc_component_update_bits(component, DA7218_REFERENCES,
DA7218_BIAS_EN_MASK, 0);
}
break;
}
return 0;
}
static const char *da7218_supply_names[DA7218_NUM_SUPPLIES] = {
[DA7218_SUPPLY_VDD] = "VDD",
[DA7218_SUPPLY_VDDMIC] = "VDDMIC",
[DA7218_SUPPLY_VDDIO] = "VDDIO",
};
static int da7218_handle_supplies(struct snd_soc_component *component)
{
struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
struct regulator *vddio;
u8 io_voltage_lvl = DA7218_IO_VOLTAGE_LEVEL_2_5V_3_6V;
int i, ret;
/* Get required supplies */
for (i = 0; i < DA7218_NUM_SUPPLIES; ++i)
da7218->supplies[i].supply = da7218_supply_names[i];
ret = devm_regulator_bulk_get(component->dev, DA7218_NUM_SUPPLIES,
da7218->supplies);
if (ret) {
dev_err(component->dev, "Failed to get supplies\n");
return ret;
}
/* Determine VDDIO voltage provided */
vddio = da7218->supplies[DA7218_SUPPLY_VDDIO].consumer;
ret = regulator_get_voltage(vddio);
if (ret < 1500000)
dev_warn(component->dev, "Invalid VDDIO voltage\n");
else if (ret < 2500000)
io_voltage_lvl = DA7218_IO_VOLTAGE_LEVEL_1_5V_2_5V;
/* Enable main supplies */
ret = regulator_bulk_enable(DA7218_NUM_SUPPLIES, da7218->supplies);
if (ret) {
dev_err(component->dev, "Failed to enable supplies\n");
return ret;
}
/* Ensure device in active mode */
snd_soc_component_write(component, DA7218_SYSTEM_ACTIVE, DA7218_SYSTEM_ACTIVE_MASK);
/* Update IO voltage level range */
snd_soc_component_write(component, DA7218_IO_CTRL, io_voltage_lvl);
return 0;
}
static void da7218_handle_pdata(struct snd_soc_component *component)
{
struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
struct da7218_pdata *pdata = da7218->pdata;
if (pdata) {
u8 micbias_lvl = 0, dmic_cfg = 0;
/* Mic Bias voltages */
switch (pdata->micbias1_lvl) {
case DA7218_MICBIAS_1_2V:
micbias_lvl |= DA7218_MICBIAS_1_LP_MODE_MASK;
break;
case DA7218_MICBIAS_1_6V:
case DA7218_MICBIAS_1_8V:
case DA7218_MICBIAS_2_0V:
case DA7218_MICBIAS_2_2V:
case DA7218_MICBIAS_2_4V:
case DA7218_MICBIAS_2_6V:
case DA7218_MICBIAS_2_8V:
case DA7218_MICBIAS_3_0V:
micbias_lvl |= (pdata->micbias1_lvl <<
DA7218_MICBIAS_1_LEVEL_SHIFT);
break;
}
switch (pdata->micbias2_lvl) {
case DA7218_MICBIAS_1_2V:
micbias_lvl |= DA7218_MICBIAS_2_LP_MODE_MASK;
break;
case DA7218_MICBIAS_1_6V:
case DA7218_MICBIAS_1_8V:
case DA7218_MICBIAS_2_0V:
case DA7218_MICBIAS_2_2V:
case DA7218_MICBIAS_2_4V:
case DA7218_MICBIAS_2_6V:
case DA7218_MICBIAS_2_8V:
case DA7218_MICBIAS_3_0V:
micbias_lvl |= (pdata->micbias2_lvl <<
DA7218_MICBIAS_2_LEVEL_SHIFT);
break;
}
snd_soc_component_write(component, DA7218_MICBIAS_CTRL, micbias_lvl);
/* Mic */
switch (pdata->mic1_amp_in_sel) {
case DA7218_MIC_AMP_IN_SEL_DIFF:
case DA7218_MIC_AMP_IN_SEL_SE_P:
case DA7218_MIC_AMP_IN_SEL_SE_N:
snd_soc_component_write(component, DA7218_MIC_1_SELECT,
pdata->mic1_amp_in_sel);
break;
}
switch (pdata->mic2_amp_in_sel) {
case DA7218_MIC_AMP_IN_SEL_DIFF:
case DA7218_MIC_AMP_IN_SEL_SE_P:
case DA7218_MIC_AMP_IN_SEL_SE_N:
snd_soc_component_write(component, DA7218_MIC_2_SELECT,
pdata->mic2_amp_in_sel);
break;
}
/* DMic */
switch (pdata->dmic1_data_sel) {
case DA7218_DMIC_DATA_LFALL_RRISE:
case DA7218_DMIC_DATA_LRISE_RFALL:
dmic_cfg |= (pdata->dmic1_data_sel <<
DA7218_DMIC_1_DATA_SEL_SHIFT);
break;
}
switch (pdata->dmic1_samplephase) {
case DA7218_DMIC_SAMPLE_ON_CLKEDGE:
case DA7218_DMIC_SAMPLE_BETWEEN_CLKEDGE:
dmic_cfg |= (pdata->dmic1_samplephase <<
DA7218_DMIC_1_SAMPLEPHASE_SHIFT);
break;
}
switch (pdata->dmic1_clk_rate) {
case DA7218_DMIC_CLK_3_0MHZ:
case DA7218_DMIC_CLK_1_5MHZ:
dmic_cfg |= (pdata->dmic1_clk_rate <<
DA7218_DMIC_1_CLK_RATE_SHIFT);
break;
}
snd_soc_component_update_bits(component, DA7218_DMIC_1_CTRL,
DA7218_DMIC_1_DATA_SEL_MASK |
DA7218_DMIC_1_SAMPLEPHASE_MASK |
DA7218_DMIC_1_CLK_RATE_MASK, dmic_cfg);
dmic_cfg = 0;
switch (pdata->dmic2_data_sel) {
case DA7218_DMIC_DATA_LFALL_RRISE:
case DA7218_DMIC_DATA_LRISE_RFALL:
dmic_cfg |= (pdata->dmic2_data_sel <<
DA7218_DMIC_2_DATA_SEL_SHIFT);
break;
}
switch (pdata->dmic2_samplephase) {
case DA7218_DMIC_SAMPLE_ON_CLKEDGE:
case DA7218_DMIC_SAMPLE_BETWEEN_CLKEDGE:
dmic_cfg |= (pdata->dmic2_samplephase <<
DA7218_DMIC_2_SAMPLEPHASE_SHIFT);
break;
}
switch (pdata->dmic2_clk_rate) {
case DA7218_DMIC_CLK_3_0MHZ:
case DA7218_DMIC_CLK_1_5MHZ:
dmic_cfg |= (pdata->dmic2_clk_rate <<
DA7218_DMIC_2_CLK_RATE_SHIFT);
break;
}
snd_soc_component_update_bits(component, DA7218_DMIC_2_CTRL,
DA7218_DMIC_2_DATA_SEL_MASK |
DA7218_DMIC_2_SAMPLEPHASE_MASK |
DA7218_DMIC_2_CLK_RATE_MASK, dmic_cfg);
/* DA7217 Specific */
if (da7218->dev_id == DA7217_DEV_ID) {
da7218->hp_single_supply =
pdata->hp_diff_single_supply;
if (da7218->hp_single_supply) {
snd_soc_component_write(component, DA7218_HP_DIFF_UNLOCK,
DA7218_HP_DIFF_UNLOCK_VAL);
snd_soc_component_update_bits(component, DA7218_HP_DIFF_CTRL,
DA7218_HP_AMP_SINGLE_SUPPLY_EN_MASK,
DA7218_HP_AMP_SINGLE_SUPPLY_EN_MASK);
}
}
/* DA7218 Specific */
if ((da7218->dev_id == DA7218_DEV_ID) &&
(pdata->hpldet_pdata)) {
struct da7218_hpldet_pdata *hpldet_pdata =
pdata->hpldet_pdata;
u8 hpldet_cfg = 0;
switch (hpldet_pdata->jack_rate) {
case DA7218_HPLDET_JACK_RATE_5US:
case DA7218_HPLDET_JACK_RATE_10US:
case DA7218_HPLDET_JACK_RATE_20US:
case DA7218_HPLDET_JACK_RATE_40US:
case DA7218_HPLDET_JACK_RATE_80US:
case DA7218_HPLDET_JACK_RATE_160US:
case DA7218_HPLDET_JACK_RATE_320US:
case DA7218_HPLDET_JACK_RATE_640US:
hpldet_cfg |=
(hpldet_pdata->jack_rate <<
DA7218_HPLDET_JACK_RATE_SHIFT);
break;
}
switch (hpldet_pdata->jack_debounce) {
case DA7218_HPLDET_JACK_DEBOUNCE_OFF:
case DA7218_HPLDET_JACK_DEBOUNCE_2:
case DA7218_HPLDET_JACK_DEBOUNCE_3:
case DA7218_HPLDET_JACK_DEBOUNCE_4:
hpldet_cfg |=
(hpldet_pdata->jack_debounce <<
DA7218_HPLDET_JACK_DEBOUNCE_SHIFT);
break;
}
switch (hpldet_pdata->jack_thr) {
case DA7218_HPLDET_JACK_THR_84PCT:
case DA7218_HPLDET_JACK_THR_88PCT:
case DA7218_HPLDET_JACK_THR_92PCT:
case DA7218_HPLDET_JACK_THR_96PCT:
hpldet_cfg |=
(hpldet_pdata->jack_thr <<
DA7218_HPLDET_JACK_THR_SHIFT);
break;
}
snd_soc_component_update_bits(component, DA7218_HPLDET_JACK,
DA7218_HPLDET_JACK_RATE_MASK |
DA7218_HPLDET_JACK_DEBOUNCE_MASK |
DA7218_HPLDET_JACK_THR_MASK,
hpldet_cfg);
hpldet_cfg = 0;
if (hpldet_pdata->comp_inv)
hpldet_cfg |= DA7218_HPLDET_COMP_INV_MASK;
if (hpldet_pdata->hyst)
hpldet_cfg |= DA7218_HPLDET_HYST_EN_MASK;
if (hpldet_pdata->discharge)
hpldet_cfg |= DA7218_HPLDET_DISCHARGE_EN_MASK;
snd_soc_component_write(component, DA7218_HPLDET_CTRL, hpldet_cfg);
}
}
}
static int da7218_probe(struct snd_soc_component *component)
{
struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
int ret;
/* Regulator configuration */
ret = da7218_handle_supplies(component);
if (ret)
return ret;
/* Handle DT/Platform data */
if (component->dev->of_node)
da7218->pdata = da7218_of_to_pdata(component);
else
da7218->pdata = dev_get_platdata(component->dev);
da7218_handle_pdata(component);
/* Check if MCLK provided, if not the clock is NULL */
da7218->mclk = devm_clk_get_optional(component->dev, "mclk");
if (IS_ERR(da7218->mclk)) {
ret = PTR_ERR(da7218->mclk);
goto err_disable_reg;
}
/* Default PC to free-running */
snd_soc_component_write(component, DA7218_PC_COUNT, DA7218_PC_FREERUN_MASK);
/*
* Default Output Filter mixers to off otherwise DAPM will power
* Mic to HP passthrough paths by default at startup.
*/
snd_soc_component_write(component, DA7218_DROUTING_OUTFILT_1L, 0);
snd_soc_component_write(component, DA7218_DROUTING_OUTFILT_1R, 0);
/* Default CP to normal load, power mode */
snd_soc_component_update_bits(component, DA7218_CP_CTRL,
DA7218_CP_SMALL_SWITCH_FREQ_EN_MASK, 0);
/* Default gain ramping */
snd_soc_component_update_bits(component, DA7218_MIXIN_1_CTRL,
DA7218_MIXIN_1_AMP_RAMP_EN_MASK,
DA7218_MIXIN_1_AMP_RAMP_EN_MASK);
snd_soc_component_update_bits(component, DA7218_MIXIN_2_CTRL,
DA7218_MIXIN_2_AMP_RAMP_EN_MASK,
DA7218_MIXIN_2_AMP_RAMP_EN_MASK);
snd_soc_component_update_bits(component, DA7218_IN_1L_FILTER_CTRL,
DA7218_IN_1L_RAMP_EN_MASK,
DA7218_IN_1L_RAMP_EN_MASK);
snd_soc_component_update_bits(component, DA7218_IN_1R_FILTER_CTRL,
DA7218_IN_1R_RAMP_EN_MASK,
DA7218_IN_1R_RAMP_EN_MASK);
snd_soc_component_update_bits(component, DA7218_IN_2L_FILTER_CTRL,
DA7218_IN_2L_RAMP_EN_MASK,
DA7218_IN_2L_RAMP_EN_MASK);
snd_soc_component_update_bits(component, DA7218_IN_2R_FILTER_CTRL,
DA7218_IN_2R_RAMP_EN_MASK,
DA7218_IN_2R_RAMP_EN_MASK);
snd_soc_component_update_bits(component, DA7218_DGS_GAIN_CTRL,
DA7218_DGS_RAMP_EN_MASK, DA7218_DGS_RAMP_EN_MASK);
snd_soc_component_update_bits(component, DA7218_OUT_1L_FILTER_CTRL,
DA7218_OUT_1L_RAMP_EN_MASK,
DA7218_OUT_1L_RAMP_EN_MASK);
snd_soc_component_update_bits(component, DA7218_OUT_1R_FILTER_CTRL,
DA7218_OUT_1R_RAMP_EN_MASK,
DA7218_OUT_1R_RAMP_EN_MASK);
snd_soc_component_update_bits(component, DA7218_HP_L_CTRL,
DA7218_HP_L_AMP_RAMP_EN_MASK,
DA7218_HP_L_AMP_RAMP_EN_MASK);
snd_soc_component_update_bits(component, DA7218_HP_R_CTRL,
DA7218_HP_R_AMP_RAMP_EN_MASK,
DA7218_HP_R_AMP_RAMP_EN_MASK);
/* Default infinite tone gen, start/stop by Kcontrol */
snd_soc_component_write(component, DA7218_TONE_GEN_CYCLES, DA7218_BEEP_CYCLES_MASK);
/* DA7217 specific config */
if (da7218->dev_id == DA7217_DEV_ID) {
snd_soc_component_update_bits(component, DA7218_HP_DIFF_CTRL,
DA7218_HP_AMP_DIFF_MODE_EN_MASK,
DA7218_HP_AMP_DIFF_MODE_EN_MASK);
/* Only DA7218 supports HP detect, mask off for DA7217 */
snd_soc_component_write(component, DA7218_EVENT_MASK,
DA7218_HPLDET_JACK_EVENT_IRQ_MSK_MASK);
}
if (da7218->irq) {
ret = devm_request_threaded_irq(component->dev, da7218->irq, NULL,
da7218_irq_thread,
IRQF_TRIGGER_LOW | IRQF_ONESHOT,
"da7218", component);
if (ret != 0) {
dev_err(component->dev, "Failed to request IRQ %d: %d\n",
da7218->irq, ret);
goto err_disable_reg;
}
}
return 0;
err_disable_reg:
regulator_bulk_disable(DA7218_NUM_SUPPLIES, da7218->supplies);
return ret;
}
static void da7218_remove(struct snd_soc_component *component)
{
struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
regulator_bulk_disable(DA7218_NUM_SUPPLIES, da7218->supplies);
}
#ifdef CONFIG_PM
static int da7218_suspend(struct snd_soc_component *component)
{
struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
da7218_set_bias_level(component, SND_SOC_BIAS_OFF);
/* Put device into standby mode if jack detection disabled */
if (!da7218->jack)
snd_soc_component_write(component, DA7218_SYSTEM_ACTIVE, 0);
return 0;
}
static int da7218_resume(struct snd_soc_component *component)
{
struct da7218_priv *da7218 = snd_soc_component_get_drvdata(component);
/* Put device into active mode if previously moved to standby */
if (!da7218->jack)
snd_soc_component_write(component, DA7218_SYSTEM_ACTIVE,
DA7218_SYSTEM_ACTIVE_MASK);
da7218_set_bias_level(component, SND_SOC_BIAS_STANDBY);
return 0;
}
#else
#define da7218_suspend NULL
#define da7218_resume NULL
#endif
static const struct snd_soc_component_driver soc_component_dev_da7218 = {
.probe = da7218_probe,
.remove = da7218_remove,
.suspend = da7218_suspend,
.resume = da7218_resume,
.set_bias_level = da7218_set_bias_level,
.controls = da7218_snd_controls,
.num_controls = ARRAY_SIZE(da7218_snd_controls),
.dapm_widgets = da7218_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(da7218_dapm_widgets),
.dapm_routes = da7218_audio_map,
.num_dapm_routes = ARRAY_SIZE(da7218_audio_map),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
/*
* Regmap configs
*/
static struct reg_default da7218_reg_defaults[] = {
{ DA7218_SYSTEM_ACTIVE, 0x00 },
{ DA7218_CIF_CTRL, 0x00 },
{ DA7218_SPARE1, 0x00 },
{ DA7218_SR, 0xAA },
{ DA7218_PC_COUNT, 0x02 },
{ DA7218_GAIN_RAMP_CTRL, 0x00 },
{ DA7218_CIF_TIMEOUT_CTRL, 0x01 },
{ DA7218_SYSTEM_MODES_INPUT, 0x00 },
{ DA7218_SYSTEM_MODES_OUTPUT, 0x00 },
{ DA7218_IN_1L_FILTER_CTRL, 0x00 },
{ DA7218_IN_1R_FILTER_CTRL, 0x00 },
{ DA7218_IN_2L_FILTER_CTRL, 0x00 },
{ DA7218_IN_2R_FILTER_CTRL, 0x00 },
{ DA7218_OUT_1L_FILTER_CTRL, 0x40 },
{ DA7218_OUT_1R_FILTER_CTRL, 0x40 },
{ DA7218_OUT_1_HPF_FILTER_CTRL, 0x80 },
{ DA7218_OUT_1_EQ_12_FILTER_CTRL, 0x77 },
{ DA7218_OUT_1_EQ_34_FILTER_CTRL, 0x77 },
{ DA7218_OUT_1_EQ_5_FILTER_CTRL, 0x07 },
{ DA7218_OUT_1_BIQ_5STAGE_CTRL, 0x40 },
{ DA7218_OUT_1_BIQ_5STAGE_DATA, 0x00 },
{ DA7218_OUT_1_BIQ_5STAGE_ADDR, 0x00 },
{ DA7218_MIXIN_1_CTRL, 0x48 },
{ DA7218_MIXIN_1_GAIN, 0x03 },
{ DA7218_MIXIN_2_CTRL, 0x48 },
{ DA7218_MIXIN_2_GAIN, 0x03 },
{ DA7218_ALC_CTRL1, 0x00 },
{ DA7218_ALC_CTRL2, 0x00 },
{ DA7218_ALC_CTRL3, 0x00 },
{ DA7218_ALC_NOISE, 0x3F },
{ DA7218_ALC_TARGET_MIN, 0x3F },
{ DA7218_ALC_TARGET_MAX, 0x00 },
{ DA7218_ALC_GAIN_LIMITS, 0xFF },
{ DA7218_ALC_ANA_GAIN_LIMITS, 0x71 },
{ DA7218_ALC_ANTICLIP_CTRL, 0x00 },
{ DA7218_AGS_ENABLE, 0x00 },
{ DA7218_AGS_TRIGGER, 0x09 },
{ DA7218_AGS_ATT_MAX, 0x00 },
{ DA7218_AGS_TIMEOUT, 0x00 },
{ DA7218_AGS_ANTICLIP_CTRL, 0x00 },
{ DA7218_ENV_TRACK_CTRL, 0x00 },
{ DA7218_LVL_DET_CTRL, 0x00 },
{ DA7218_LVL_DET_LEVEL, 0x7F },
{ DA7218_DGS_TRIGGER, 0x24 },
{ DA7218_DGS_ENABLE, 0x00 },
{ DA7218_DGS_RISE_FALL, 0x50 },
{ DA7218_DGS_SYNC_DELAY, 0xA3 },
{ DA7218_DGS_SYNC_DELAY2, 0x31 },
{ DA7218_DGS_SYNC_DELAY3, 0x11 },
{ DA7218_DGS_LEVELS, 0x01 },
{ DA7218_DGS_GAIN_CTRL, 0x74 },
{ DA7218_DROUTING_OUTDAI_1L, 0x01 },
{ DA7218_DMIX_OUTDAI_1L_INFILT_1L_GAIN, 0x1C },
{ DA7218_DMIX_OUTDAI_1L_INFILT_1R_GAIN, 0x1C },
{ DA7218_DMIX_OUTDAI_1L_INFILT_2L_GAIN, 0x1C },
{ DA7218_DMIX_OUTDAI_1L_INFILT_2R_GAIN, 0x1C },
{ DA7218_DMIX_OUTDAI_1L_TONEGEN_GAIN, 0x1C },
{ DA7218_DMIX_OUTDAI_1L_INDAI_1L_GAIN, 0x1C },
{ DA7218_DMIX_OUTDAI_1L_INDAI_1R_GAIN, 0x1C },
{ DA7218_DROUTING_OUTDAI_1R, 0x04 },
{ DA7218_DMIX_OUTDAI_1R_INFILT_1L_GAIN, 0x1C },
{ DA7218_DMIX_OUTDAI_1R_INFILT_1R_GAIN, 0x1C },
{ DA7218_DMIX_OUTDAI_1R_INFILT_2L_GAIN, 0x1C },
{ DA7218_DMIX_OUTDAI_1R_INFILT_2R_GAIN, 0x1C },
{ DA7218_DMIX_OUTDAI_1R_TONEGEN_GAIN, 0x1C },
{ DA7218_DMIX_OUTDAI_1R_INDAI_1L_GAIN, 0x1C },
{ DA7218_DMIX_OUTDAI_1R_INDAI_1R_GAIN, 0x1C },
{ DA7218_DROUTING_OUTFILT_1L, 0x01 },
{ DA7218_DMIX_OUTFILT_1L_INFILT_1L_GAIN, 0x1C },
{ DA7218_DMIX_OUTFILT_1L_INFILT_1R_GAIN, 0x1C },
{ DA7218_DMIX_OUTFILT_1L_INFILT_2L_GAIN, 0x1C },
{ DA7218_DMIX_OUTFILT_1L_INFILT_2R_GAIN, 0x1C },
{ DA7218_DMIX_OUTFILT_1L_TONEGEN_GAIN, 0x1C },
{ DA7218_DMIX_OUTFILT_1L_INDAI_1L_GAIN, 0x1C },
{ DA7218_DMIX_OUTFILT_1L_INDAI_1R_GAIN, 0x1C },
{ DA7218_DROUTING_OUTFILT_1R, 0x04 },
{ DA7218_DMIX_OUTFILT_1R_INFILT_1L_GAIN, 0x1C },
{ DA7218_DMIX_OUTFILT_1R_INFILT_1R_GAIN, 0x1C },
{ DA7218_DMIX_OUTFILT_1R_INFILT_2L_GAIN, 0x1C },
{ DA7218_DMIX_OUTFILT_1R_INFILT_2R_GAIN, 0x1C },
{ DA7218_DMIX_OUTFILT_1R_TONEGEN_GAIN, 0x1C },
{ DA7218_DMIX_OUTFILT_1R_INDAI_1L_GAIN, 0x1C },
{ DA7218_DMIX_OUTFILT_1R_INDAI_1R_GAIN, 0x1C },
{ DA7218_DROUTING_OUTDAI_2L, 0x04 },
{ DA7218_DMIX_OUTDAI_2L_INFILT_1L_GAIN, 0x1C },
{ DA7218_DMIX_OUTDAI_2L_INFILT_1R_GAIN, 0x1C },
{ DA7218_DMIX_OUTDAI_2L_INFILT_2L_GAIN, 0x1C },
{ DA7218_DMIX_OUTDAI_2L_INFILT_2R_GAIN, 0x1C },
{ DA7218_DMIX_OUTDAI_2L_TONEGEN_GAIN, 0x1C },
{ DA7218_DMIX_OUTDAI_2L_INDAI_1L_GAIN, 0x1C },
{ DA7218_DMIX_OUTDAI_2L_INDAI_1R_GAIN, 0x1C },
{ DA7218_DROUTING_OUTDAI_2R, 0x08 },
{ DA7218_DMIX_OUTDAI_2R_INFILT_1L_GAIN, 0x1C },
{ DA7218_DMIX_OUTDAI_2R_INFILT_1R_GAIN, 0x1C },
{ DA7218_DMIX_OUTDAI_2R_INFILT_2L_GAIN, 0x1C },
{ DA7218_DMIX_OUTDAI_2R_INFILT_2R_GAIN, 0x1C },
{ DA7218_DMIX_OUTDAI_2R_TONEGEN_GAIN, 0x1C },
{ DA7218_DMIX_OUTDAI_2R_INDAI_1L_GAIN, 0x1C },
{ DA7218_DMIX_OUTDAI_2R_INDAI_1R_GAIN, 0x1C },
{ DA7218_DAI_CTRL, 0x28 },
{ DA7218_DAI_TDM_CTRL, 0x40 },
{ DA7218_DAI_OFFSET_LOWER, 0x00 },
{ DA7218_DAI_OFFSET_UPPER, 0x00 },
{ DA7218_DAI_CLK_MODE, 0x01 },
{ DA7218_PLL_CTRL, 0x04 },
{ DA7218_PLL_FRAC_TOP, 0x00 },
{ DA7218_PLL_FRAC_BOT, 0x00 },
{ DA7218_PLL_INTEGER, 0x20 },
{ DA7218_DAC_NG_CTRL, 0x00 },
{ DA7218_DAC_NG_SETUP_TIME, 0x00 },
{ DA7218_DAC_NG_OFF_THRESH, 0x00 },
{ DA7218_DAC_NG_ON_THRESH, 0x00 },
{ DA7218_TONE_GEN_CFG2, 0x00 },
{ DA7218_TONE_GEN_FREQ1_L, 0x55 },
{ DA7218_TONE_GEN_FREQ1_U, 0x15 },
{ DA7218_TONE_GEN_FREQ2_L, 0x00 },
{ DA7218_TONE_GEN_FREQ2_U, 0x40 },
{ DA7218_TONE_GEN_CYCLES, 0x00 },
{ DA7218_TONE_GEN_ON_PER, 0x02 },
{ DA7218_TONE_GEN_OFF_PER, 0x01 },
{ DA7218_CP_CTRL, 0x60 },
{ DA7218_CP_DELAY, 0x11 },
{ DA7218_CP_VOL_THRESHOLD1, 0x0E },
{ DA7218_MIC_1_CTRL, 0x40 },
{ DA7218_MIC_1_GAIN, 0x01 },
{ DA7218_MIC_1_SELECT, 0x00 },
{ DA7218_MIC_2_CTRL, 0x40 },
{ DA7218_MIC_2_GAIN, 0x01 },
{ DA7218_MIC_2_SELECT, 0x00 },
{ DA7218_IN_1_HPF_FILTER_CTRL, 0x80 },
{ DA7218_IN_2_HPF_FILTER_CTRL, 0x80 },
{ DA7218_ADC_1_CTRL, 0x07 },
{ DA7218_ADC_2_CTRL, 0x07 },
{ DA7218_MIXOUT_L_CTRL, 0x00 },
{ DA7218_MIXOUT_L_GAIN, 0x03 },
{ DA7218_MIXOUT_R_CTRL, 0x00 },
{ DA7218_MIXOUT_R_GAIN, 0x03 },
{ DA7218_HP_L_CTRL, 0x40 },
{ DA7218_HP_L_GAIN, 0x3B },
{ DA7218_HP_R_CTRL, 0x40 },
{ DA7218_HP_R_GAIN, 0x3B },
{ DA7218_HP_DIFF_CTRL, 0x00 },
{ DA7218_HP_DIFF_UNLOCK, 0xC3 },
{ DA7218_HPLDET_JACK, 0x0B },
{ DA7218_HPLDET_CTRL, 0x00 },
{ DA7218_REFERENCES, 0x08 },
{ DA7218_IO_CTRL, 0x00 },
{ DA7218_LDO_CTRL, 0x00 },
{ DA7218_SIDETONE_CTRL, 0x40 },
{ DA7218_SIDETONE_IN_SELECT, 0x00 },
{ DA7218_SIDETONE_GAIN, 0x1C },
{ DA7218_DROUTING_ST_OUTFILT_1L, 0x01 },
{ DA7218_DROUTING_ST_OUTFILT_1R, 0x02 },
{ DA7218_SIDETONE_BIQ_3STAGE_DATA, 0x00 },
{ DA7218_SIDETONE_BIQ_3STAGE_ADDR, 0x00 },
{ DA7218_EVENT_MASK, 0x00 },
{ DA7218_DMIC_1_CTRL, 0x00 },
{ DA7218_DMIC_2_CTRL, 0x00 },
{ DA7218_IN_1L_GAIN, 0x6F },
{ DA7218_IN_1R_GAIN, 0x6F },
{ DA7218_IN_2L_GAIN, 0x6F },
{ DA7218_IN_2R_GAIN, 0x6F },
{ DA7218_OUT_1L_GAIN, 0x6F },
{ DA7218_OUT_1R_GAIN, 0x6F },
{ DA7218_MICBIAS_CTRL, 0x00 },
{ DA7218_MICBIAS_EN, 0x00 },
};
static bool da7218_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case DA7218_STATUS1:
case DA7218_SOFT_RESET:
case DA7218_SYSTEM_STATUS:
case DA7218_CALIB_CTRL:
case DA7218_CALIB_OFFSET_AUTO_M_1:
case DA7218_CALIB_OFFSET_AUTO_U_1:
case DA7218_CALIB_OFFSET_AUTO_M_2:
case DA7218_CALIB_OFFSET_AUTO_U_2:
case DA7218_PLL_STATUS:
case DA7218_PLL_REFOSC_CAL:
case DA7218_TONE_GEN_CFG1:
case DA7218_ADC_MODE:
case DA7218_HP_SNGL_CTRL:
case DA7218_HPLDET_TEST:
case DA7218_EVENT_STATUS:
case DA7218_EVENT:
return true;
default:
return false;
}
}
static const struct regmap_config da7218_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = DA7218_MICBIAS_EN,
.reg_defaults = da7218_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(da7218_reg_defaults),
.volatile_reg = da7218_volatile_register,
.cache_type = REGCACHE_RBTREE,
};
/*
* I2C layer
*/
static const struct i2c_device_id da7218_i2c_id[];
static inline int da7218_i2c_get_id(struct i2c_client *i2c)
{
const struct i2c_device_id *id = i2c_match_id(da7218_i2c_id, i2c);
if (id)
return (uintptr_t)id->driver_data;
else
return -EINVAL;
}
static int da7218_i2c_probe(struct i2c_client *i2c)
{
struct da7218_priv *da7218;
int ret;
da7218 = devm_kzalloc(&i2c->dev, sizeof(*da7218), GFP_KERNEL);
if (!da7218)
return -ENOMEM;
i2c_set_clientdata(i2c, da7218);
if (i2c->dev.of_node)
da7218->dev_id = da7218_of_get_id(&i2c->dev);
else
da7218->dev_id = da7218_i2c_get_id(i2c);
if ((da7218->dev_id != DA7217_DEV_ID) &&
(da7218->dev_id != DA7218_DEV_ID)) {
dev_err(&i2c->dev, "Invalid device Id\n");
return -EINVAL;
}
da7218->irq = i2c->irq;
da7218->regmap = devm_regmap_init_i2c(i2c, &da7218_regmap_config);
if (IS_ERR(da7218->regmap)) {
ret = PTR_ERR(da7218->regmap);
dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);
return ret;
}
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_da7218, &da7218_dai, 1);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to register da7218 component: %d\n",
ret);
}
return ret;
}
static const struct i2c_device_id da7218_i2c_id[] = {
{ "da7217", DA7217_DEV_ID },
{ "da7218", DA7218_DEV_ID },
{ }
};
MODULE_DEVICE_TABLE(i2c, da7218_i2c_id);
static struct i2c_driver da7218_i2c_driver = {
.driver = {
.name = "da7218",
.of_match_table = da7218_of_match,
},
.probe = da7218_i2c_probe,
.id_table = da7218_i2c_id,
};
module_i2c_driver(da7218_i2c_driver);
MODULE_DESCRIPTION("ASoC DA7218 Codec driver");
MODULE_AUTHOR("Adam Thomson <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/da7218.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* es8328.c -- ES8328 ALSA SoC SPI Audio driver
*
* Copyright 2014 Sutajio Ko-Usagi PTE LTD
*
* Author: Sean Cross <[email protected]>
*/
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include <sound/soc.h>
#include "es8328.h"
static const struct of_device_id es8328_of_match[] = {
{ .compatible = "everest,es8328", },
{ }
};
MODULE_DEVICE_TABLE(of, es8328_of_match);
static int es8328_spi_probe(struct spi_device *spi)
{
return es8328_probe(&spi->dev,
devm_regmap_init_spi(spi, &es8328_regmap_config));
}
static struct spi_driver es8328_spi_driver = {
.driver = {
.name = "es8328",
.of_match_table = es8328_of_match,
},
.probe = es8328_spi_probe,
};
module_spi_driver(es8328_spi_driver);
MODULE_DESCRIPTION("ASoC ES8328 audio CODEC SPI driver");
MODULE_AUTHOR("Sean Cross <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/es8328-spi.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* max98927.c -- MAX98927 ALSA Soc Audio driver
*
* Copyright (C) 2016-2017 Maxim Integrated Products
* Author: Ryan Lee <[email protected]>
*/
#include <linux/acpi.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/cdev.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/of_gpio.h>
#include <sound/tlv.h>
#include "max98927.h"
static struct reg_default max98927_reg[] = {
{MAX98927_R0001_INT_RAW1, 0x00},
{MAX98927_R0002_INT_RAW2, 0x00},
{MAX98927_R0003_INT_RAW3, 0x00},
{MAX98927_R0004_INT_STATE1, 0x00},
{MAX98927_R0005_INT_STATE2, 0x00},
{MAX98927_R0006_INT_STATE3, 0x00},
{MAX98927_R0007_INT_FLAG1, 0x00},
{MAX98927_R0008_INT_FLAG2, 0x00},
{MAX98927_R0009_INT_FLAG3, 0x00},
{MAX98927_R000A_INT_EN1, 0x00},
{MAX98927_R000B_INT_EN2, 0x00},
{MAX98927_R000C_INT_EN3, 0x00},
{MAX98927_R000D_INT_FLAG_CLR1, 0x00},
{MAX98927_R000E_INT_FLAG_CLR2, 0x00},
{MAX98927_R000F_INT_FLAG_CLR3, 0x00},
{MAX98927_R0010_IRQ_CTRL, 0x00},
{MAX98927_R0011_CLK_MON, 0x00},
{MAX98927_R0012_WDOG_CTRL, 0x00},
{MAX98927_R0013_WDOG_RST, 0x00},
{MAX98927_R0014_MEAS_ADC_THERM_WARN_THRESH, 0x75},
{MAX98927_R0015_MEAS_ADC_THERM_SHDN_THRESH, 0x8c},
{MAX98927_R0016_MEAS_ADC_THERM_HYSTERESIS, 0x08},
{MAX98927_R0017_PIN_CFG, 0x55},
{MAX98927_R0018_PCM_RX_EN_A, 0x00},
{MAX98927_R0019_PCM_RX_EN_B, 0x00},
{MAX98927_R001A_PCM_TX_EN_A, 0x00},
{MAX98927_R001B_PCM_TX_EN_B, 0x00},
{MAX98927_R001C_PCM_TX_HIZ_CTRL_A, 0x00},
{MAX98927_R001D_PCM_TX_HIZ_CTRL_B, 0x00},
{MAX98927_R001E_PCM_TX_CH_SRC_A, 0x00},
{MAX98927_R001F_PCM_TX_CH_SRC_B, 0x00},
{MAX98927_R0020_PCM_MODE_CFG, 0x40},
{MAX98927_R0021_PCM_MASTER_MODE, 0x00},
{MAX98927_R0022_PCM_CLK_SETUP, 0x22},
{MAX98927_R0023_PCM_SR_SETUP1, 0x00},
{MAX98927_R0024_PCM_SR_SETUP2, 0x00},
{MAX98927_R0025_PCM_TO_SPK_MONOMIX_A, 0x00},
{MAX98927_R0026_PCM_TO_SPK_MONOMIX_B, 0x00},
{MAX98927_R0027_ICC_RX_EN_A, 0x00},
{MAX98927_R0028_ICC_RX_EN_B, 0x00},
{MAX98927_R002B_ICC_TX_EN_A, 0x00},
{MAX98927_R002C_ICC_TX_EN_B, 0x00},
{MAX98927_R002E_ICC_HIZ_MANUAL_MODE, 0x00},
{MAX98927_R002F_ICC_TX_HIZ_EN_A, 0x00},
{MAX98927_R0030_ICC_TX_HIZ_EN_B, 0x00},
{MAX98927_R0031_ICC_LNK_EN, 0x00},
{MAX98927_R0032_PDM_TX_EN, 0x00},
{MAX98927_R0033_PDM_TX_HIZ_CTRL, 0x00},
{MAX98927_R0034_PDM_TX_CTRL, 0x00},
{MAX98927_R0035_PDM_RX_CTRL, 0x00},
{MAX98927_R0036_AMP_VOL_CTRL, 0x00},
{MAX98927_R0037_AMP_DSP_CFG, 0x02},
{MAX98927_R0038_TONE_GEN_DC_CFG, 0x00},
{MAX98927_R0039_DRE_CTRL, 0x01},
{MAX98927_R003A_AMP_EN, 0x00},
{MAX98927_R003B_SPK_SRC_SEL, 0x00},
{MAX98927_R003C_SPK_GAIN, 0x00},
{MAX98927_R003D_SSM_CFG, 0x04},
{MAX98927_R003E_MEAS_EN, 0x00},
{MAX98927_R003F_MEAS_DSP_CFG, 0x04},
{MAX98927_R0040_BOOST_CTRL0, 0x00},
{MAX98927_R0041_BOOST_CTRL3, 0x00},
{MAX98927_R0042_BOOST_CTRL1, 0x00},
{MAX98927_R0043_MEAS_ADC_CFG, 0x00},
{MAX98927_R0044_MEAS_ADC_BASE_MSB, 0x01},
{MAX98927_R0045_MEAS_ADC_BASE_LSB, 0x00},
{MAX98927_R0046_ADC_CH0_DIVIDE, 0x00},
{MAX98927_R0047_ADC_CH1_DIVIDE, 0x00},
{MAX98927_R0048_ADC_CH2_DIVIDE, 0x00},
{MAX98927_R0049_ADC_CH0_FILT_CFG, 0x00},
{MAX98927_R004A_ADC_CH1_FILT_CFG, 0x00},
{MAX98927_R004B_ADC_CH2_FILT_CFG, 0x00},
{MAX98927_R004C_MEAS_ADC_CH0_READ, 0x00},
{MAX98927_R004D_MEAS_ADC_CH1_READ, 0x00},
{MAX98927_R004E_MEAS_ADC_CH2_READ, 0x00},
{MAX98927_R0051_BROWNOUT_STATUS, 0x00},
{MAX98927_R0052_BROWNOUT_EN, 0x00},
{MAX98927_R0053_BROWNOUT_INFINITE_HOLD, 0x00},
{MAX98927_R0054_BROWNOUT_INFINITE_HOLD_CLR, 0x00},
{MAX98927_R0055_BROWNOUT_LVL_HOLD, 0x00},
{MAX98927_R005A_BROWNOUT_LVL1_THRESH, 0x00},
{MAX98927_R005B_BROWNOUT_LVL2_THRESH, 0x00},
{MAX98927_R005C_BROWNOUT_LVL3_THRESH, 0x00},
{MAX98927_R005D_BROWNOUT_LVL4_THRESH, 0x00},
{MAX98927_R005E_BROWNOUT_THRESH_HYSTERYSIS, 0x00},
{MAX98927_R005F_BROWNOUT_AMP_LIMITER_ATK_REL, 0x00},
{MAX98927_R0060_BROWNOUT_AMP_GAIN_ATK_REL, 0x00},
{MAX98927_R0061_BROWNOUT_AMP1_CLIP_MODE, 0x00},
{MAX98927_R0072_BROWNOUT_LVL1_CUR_LIMIT, 0x00},
{MAX98927_R0073_BROWNOUT_LVL1_AMP1_CTRL1, 0x00},
{MAX98927_R0074_BROWNOUT_LVL1_AMP1_CTRL2, 0x00},
{MAX98927_R0075_BROWNOUT_LVL1_AMP1_CTRL3, 0x00},
{MAX98927_R0076_BROWNOUT_LVL2_CUR_LIMIT, 0x00},
{MAX98927_R0077_BROWNOUT_LVL2_AMP1_CTRL1, 0x00},
{MAX98927_R0078_BROWNOUT_LVL2_AMP1_CTRL2, 0x00},
{MAX98927_R0079_BROWNOUT_LVL2_AMP1_CTRL3, 0x00},
{MAX98927_R007A_BROWNOUT_LVL3_CUR_LIMIT, 0x00},
{MAX98927_R007B_BROWNOUT_LVL3_AMP1_CTRL1, 0x00},
{MAX98927_R007C_BROWNOUT_LVL3_AMP1_CTRL2, 0x00},
{MAX98927_R007D_BROWNOUT_LVL3_AMP1_CTRL3, 0x00},
{MAX98927_R007E_BROWNOUT_LVL4_CUR_LIMIT, 0x00},
{MAX98927_R007F_BROWNOUT_LVL4_AMP1_CTRL1, 0x00},
{MAX98927_R0080_BROWNOUT_LVL4_AMP1_CTRL2, 0x00},
{MAX98927_R0081_BROWNOUT_LVL4_AMP1_CTRL3, 0x00},
{MAX98927_R0082_ENV_TRACK_VOUT_HEADROOM, 0x00},
{MAX98927_R0083_ENV_TRACK_BOOST_VOUT_DELAY, 0x00},
{MAX98927_R0084_ENV_TRACK_REL_RATE, 0x00},
{MAX98927_R0085_ENV_TRACK_HOLD_RATE, 0x00},
{MAX98927_R0086_ENV_TRACK_CTRL, 0x00},
{MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ, 0x00},
{MAX98927_R00FF_GLOBAL_SHDN, 0x00},
{MAX98927_R0100_SOFT_RESET, 0x00},
{MAX98927_R01FF_REV_ID, 0x40},
};
static int max98927_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
unsigned int mode = 0;
unsigned int format = 0;
bool use_pdm = false;
unsigned int invert = 0;
dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt);
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC:
max98927->provider = false;
mode = MAX98927_PCM_MASTER_MODE_SLAVE;
break;
case SND_SOC_DAIFMT_CBP_CFP:
max98927->provider = true;
mode = MAX98927_PCM_MASTER_MODE_MASTER;
break;
default:
dev_err(component->dev, "DAI clock mode unsupported\n");
return -EINVAL;
}
regmap_update_bits(max98927->regmap, MAX98927_R0021_PCM_MASTER_MODE,
MAX98927_PCM_MASTER_MODE_MASK, mode);
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
invert = MAX98927_PCM_MODE_CFG_PCM_BCLKEDGE;
break;
default:
dev_err(component->dev, "DAI invert mode unsupported\n");
return -EINVAL;
}
regmap_update_bits(max98927->regmap, MAX98927_R0020_PCM_MODE_CFG,
MAX98927_PCM_MODE_CFG_PCM_BCLKEDGE, invert);
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
format = MAX98927_PCM_FORMAT_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
format = MAX98927_PCM_FORMAT_LJ;
break;
case SND_SOC_DAIFMT_DSP_A:
format = MAX98927_PCM_FORMAT_TDM_MODE1;
break;
case SND_SOC_DAIFMT_DSP_B:
format = MAX98927_PCM_FORMAT_TDM_MODE0;
break;
case SND_SOC_DAIFMT_PDM:
use_pdm = true;
break;
default:
return -EINVAL;
}
max98927->iface = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
if (!use_pdm) {
/* pcm channel configuration */
regmap_update_bits(max98927->regmap, MAX98927_R0018_PCM_RX_EN_A,
MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN,
MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN);
regmap_update_bits(max98927->regmap,
MAX98927_R0020_PCM_MODE_CFG,
MAX98927_PCM_MODE_CFG_FORMAT_MASK,
format << MAX98927_PCM_MODE_CFG_FORMAT_SHIFT);
regmap_update_bits(max98927->regmap, MAX98927_R003B_SPK_SRC_SEL,
MAX98927_SPK_SRC_MASK, 0);
regmap_update_bits(max98927->regmap, MAX98927_R0035_PDM_RX_CTRL,
MAX98927_PDM_RX_EN_MASK, 0);
} else {
/* pdm channel configuration */
regmap_update_bits(max98927->regmap, MAX98927_R0035_PDM_RX_CTRL,
MAX98927_PDM_RX_EN_MASK, 1);
regmap_update_bits(max98927->regmap, MAX98927_R003B_SPK_SRC_SEL,
MAX98927_SPK_SRC_MASK, 3);
regmap_update_bits(max98927->regmap, MAX98927_R0018_PCM_RX_EN_A,
MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN,
0);
}
return 0;
}
/* codec MCLK rate in master mode */
static const int rate_table[] = {
5644800, 6000000, 6144000, 6500000,
9600000, 11289600, 12000000, 12288000,
13000000, 19200000,
};
/* BCLKs per LRCLK */
static const int bclk_sel_table[] = {
32, 48, 64, 96, 128, 192, 256, 384, 512,
};
static int max98927_get_bclk_sel(int bclk)
{
int i;
/* match BCLKs per LRCLK */
for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) {
if (bclk_sel_table[i] == bclk)
return i + 2;
}
return 0;
}
static int max98927_set_clock(struct max98927_priv *max98927,
struct snd_pcm_hw_params *params)
{
struct snd_soc_component *component = max98927->component;
/* BCLK/LRCLK ratio calculation */
int blr_clk_ratio = params_channels(params) * max98927->ch_size;
int value;
if (max98927->provider) {
int i;
/* match rate to closest value */
for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
if (rate_table[i] >= max98927->sysclk)
break;
}
if (i == ARRAY_SIZE(rate_table)) {
dev_err(component->dev, "failed to find proper clock rate.\n");
return -EINVAL;
}
regmap_update_bits(max98927->regmap,
MAX98927_R0021_PCM_MASTER_MODE,
MAX98927_PCM_MASTER_MODE_MCLK_MASK,
i << MAX98927_PCM_MASTER_MODE_MCLK_RATE_SHIFT);
}
if (!max98927->tdm_mode) {
/* BCLK configuration */
value = max98927_get_bclk_sel(blr_clk_ratio);
if (!value) {
dev_err(component->dev, "format unsupported %d\n",
params_format(params));
return -EINVAL;
}
regmap_update_bits(max98927->regmap,
MAX98927_R0022_PCM_CLK_SETUP,
MAX98927_PCM_CLK_SETUP_BSEL_MASK, value);
}
return 0;
}
static int max98927_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
unsigned int sampling_rate = 0;
unsigned int chan_sz = 0;
/* pcm mode configuration */
switch (snd_pcm_format_width(params_format(params))) {
case 16:
chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_16;
break;
case 24:
chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_24;
break;
case 32:
chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_32;
break;
default:
dev_err(component->dev, "format unsupported %d\n",
params_format(params));
goto err;
}
max98927->ch_size = snd_pcm_format_width(params_format(params));
regmap_update_bits(max98927->regmap, MAX98927_R0020_PCM_MODE_CFG,
MAX98927_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
dev_dbg(component->dev, "format supported %d",
params_format(params));
/* sampling rate configuration */
switch (params_rate(params)) {
case 8000:
sampling_rate = MAX98927_PCM_SR_SET1_SR_8000;
break;
case 11025:
sampling_rate = MAX98927_PCM_SR_SET1_SR_11025;
break;
case 12000:
sampling_rate = MAX98927_PCM_SR_SET1_SR_12000;
break;
case 16000:
sampling_rate = MAX98927_PCM_SR_SET1_SR_16000;
break;
case 22050:
sampling_rate = MAX98927_PCM_SR_SET1_SR_22050;
break;
case 24000:
sampling_rate = MAX98927_PCM_SR_SET1_SR_24000;
break;
case 32000:
sampling_rate = MAX98927_PCM_SR_SET1_SR_32000;
break;
case 44100:
sampling_rate = MAX98927_PCM_SR_SET1_SR_44100;
break;
case 48000:
sampling_rate = MAX98927_PCM_SR_SET1_SR_48000;
break;
default:
dev_err(component->dev, "rate %d not supported\n",
params_rate(params));
goto err;
}
/* set DAI_SR to correct LRCLK frequency */
regmap_update_bits(max98927->regmap, MAX98927_R0023_PCM_SR_SETUP1,
MAX98927_PCM_SR_SET1_SR_MASK, sampling_rate);
regmap_update_bits(max98927->regmap, MAX98927_R0024_PCM_SR_SETUP2,
MAX98927_PCM_SR_SET2_SR_MASK,
sampling_rate << MAX98927_PCM_SR_SET2_SR_SHIFT);
/* set sampling rate of IV */
if (max98927->interleave_mode &&
sampling_rate > MAX98927_PCM_SR_SET1_SR_16000)
regmap_update_bits(max98927->regmap,
MAX98927_R0024_PCM_SR_SETUP2,
MAX98927_PCM_SR_SET2_IVADC_SR_MASK,
sampling_rate - 3);
else
regmap_update_bits(max98927->regmap,
MAX98927_R0024_PCM_SR_SETUP2,
MAX98927_PCM_SR_SET2_IVADC_SR_MASK,
sampling_rate);
return max98927_set_clock(max98927, params);
err:
return -EINVAL;
}
static int max98927_dai_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask,
int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
int bsel = 0;
unsigned int chan_sz = 0;
max98927->tdm_mode = true;
/* BCLK configuration */
bsel = max98927_get_bclk_sel(slots * slot_width);
if (bsel == 0) {
dev_err(component->dev, "BCLK %d not supported\n",
slots * slot_width);
return -EINVAL;
}
regmap_update_bits(max98927->regmap, MAX98927_R0022_PCM_CLK_SETUP,
MAX98927_PCM_CLK_SETUP_BSEL_MASK, bsel);
/* Channel size configuration */
switch (slot_width) {
case 16:
chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_16;
break;
case 24:
chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_24;
break;
case 32:
chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_32;
break;
default:
dev_err(component->dev, "format unsupported %d\n",
slot_width);
return -EINVAL;
}
regmap_update_bits(max98927->regmap, MAX98927_R0020_PCM_MODE_CFG,
MAX98927_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
/* Rx slot configuration */
regmap_write(max98927->regmap, MAX98927_R0018_PCM_RX_EN_A,
rx_mask & 0xFF);
regmap_write(max98927->regmap, MAX98927_R0019_PCM_RX_EN_B,
(rx_mask & 0xFF00) >> 8);
/* Tx slot configuration */
regmap_write(max98927->regmap, MAX98927_R001A_PCM_TX_EN_A,
tx_mask & 0xFF);
regmap_write(max98927->regmap, MAX98927_R001B_PCM_TX_EN_B,
(tx_mask & 0xFF00) >> 8);
/* Tx slot Hi-Z configuration */
regmap_write(max98927->regmap, MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
~tx_mask & 0xFF);
regmap_write(max98927->regmap, MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
(~tx_mask & 0xFF00) >> 8);
return 0;
}
#define MAX98927_RATES SNDRV_PCM_RATE_8000_48000
#define MAX98927_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static int max98927_dai_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
max98927->sysclk = freq;
return 0;
}
static const struct snd_soc_dai_ops max98927_dai_ops = {
.set_sysclk = max98927_dai_set_sysclk,
.set_fmt = max98927_dai_set_fmt,
.hw_params = max98927_dai_hw_params,
.set_tdm_slot = max98927_dai_tdm_slot,
};
static int max98927_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
max98927->tdm_mode = false;
break;
case SND_SOC_DAPM_POST_PMU:
regmap_update_bits(max98927->regmap, MAX98927_R003A_AMP_EN,
MAX98927_AMP_EN_MASK, 1);
regmap_update_bits(max98927->regmap, MAX98927_R00FF_GLOBAL_SHDN,
MAX98927_GLOBAL_EN_MASK, 1);
break;
case SND_SOC_DAPM_POST_PMD:
regmap_update_bits(max98927->regmap, MAX98927_R00FF_GLOBAL_SHDN,
MAX98927_GLOBAL_EN_MASK, 0);
regmap_update_bits(max98927->regmap, MAX98927_R003A_AMP_EN,
MAX98927_AMP_EN_MASK, 0);
break;
default:
return 0;
}
return 0;
}
static const char * const max98927_switch_text[] = {
"Left", "Right", "LeftRight"};
static const struct soc_enum dai_sel_enum =
SOC_ENUM_SINGLE(MAX98927_R0025_PCM_TO_SPK_MONOMIX_A,
MAX98927_PCM_TO_SPK_MONOMIX_CFG_SHIFT, 3,
max98927_switch_text);
static const struct snd_kcontrol_new max98927_dai_controls =
SOC_DAPM_ENUM("DAI Sel", dai_sel_enum);
static const struct snd_kcontrol_new max98927_vi_control =
SOC_DAPM_SINGLE("Switch", MAX98927_R003F_MEAS_DSP_CFG, 2, 1, 0);
static const struct snd_soc_dapm_widget max98927_dapm_widgets[] = {
SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback", MAX98927_R003A_AMP_EN,
0, 0, max98927_dac_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0,
&max98927_dai_controls),
SND_SOC_DAPM_OUTPUT("BE_OUT"),
SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0,
MAX98927_R003E_MEAS_EN, 0, 0),
SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0,
MAX98927_R003E_MEAS_EN, 1, 0),
SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0,
&max98927_vi_control),
SND_SOC_DAPM_SIGGEN("VMON"),
SND_SOC_DAPM_SIGGEN("IMON"),
};
static DECLARE_TLV_DB_SCALE(max98927_spk_tlv, 300, 300, 0);
static DECLARE_TLV_DB_SCALE(max98927_digital_tlv, -1600, 25, 0);
static bool max98927_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX98927_R0001_INT_RAW1 ... MAX98927_R0028_ICC_RX_EN_B:
case MAX98927_R002B_ICC_TX_EN_A ... MAX98927_R002C_ICC_TX_EN_B:
case MAX98927_R002E_ICC_HIZ_MANUAL_MODE
... MAX98927_R004E_MEAS_ADC_CH2_READ:
case MAX98927_R0051_BROWNOUT_STATUS
... MAX98927_R0055_BROWNOUT_LVL_HOLD:
case MAX98927_R005A_BROWNOUT_LVL1_THRESH
... MAX98927_R0061_BROWNOUT_AMP1_CLIP_MODE:
case MAX98927_R0072_BROWNOUT_LVL1_CUR_LIMIT
... MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ:
case MAX98927_R00FF_GLOBAL_SHDN:
case MAX98927_R0100_SOFT_RESET:
case MAX98927_R01FF_REV_ID:
return true;
default:
return false;
}
};
static bool max98927_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX98927_R0001_INT_RAW1 ... MAX98927_R0009_INT_FLAG3:
case MAX98927_R004C_MEAS_ADC_CH0_READ:
case MAX98927_R004D_MEAS_ADC_CH1_READ:
case MAX98927_R004E_MEAS_ADC_CH2_READ:
case MAX98927_R0051_BROWNOUT_STATUS:
case MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ:
case MAX98927_R01FF_REV_ID:
case MAX98927_R0100_SOFT_RESET:
return true;
default:
return false;
}
}
static const char * const max98927_boost_voltage_text[] = {
"6.5V", "6.625V", "6.75V", "6.875V", "7V", "7.125V", "7.25V", "7.375V",
"7.5V", "7.625V", "7.75V", "7.875V", "8V", "8.125V", "8.25V", "8.375V",
"8.5V", "8.625V", "8.75V", "8.875V", "9V", "9.125V", "9.25V", "9.375V",
"9.5V", "9.625V", "9.75V", "9.875V", "10V"
};
static SOC_ENUM_SINGLE_DECL(max98927_boost_voltage,
MAX98927_R0040_BOOST_CTRL0, 0,
max98927_boost_voltage_text);
static const char * const max98927_current_limit_text[] = {
"1.00A", "1.10A", "1.20A", "1.30A", "1.40A", "1.50A", "1.60A", "1.70A",
"1.80A", "1.90A", "2.00A", "2.10A", "2.20A", "2.30A", "2.40A", "2.50A",
"2.60A", "2.70A", "2.80A", "2.90A", "3.00A", "3.10A", "3.20A", "3.30A",
"3.40A", "3.50A", "3.60A", "3.70A", "3.80A", "3.90A", "4.00A", "4.10A"
};
static SOC_ENUM_SINGLE_DECL(max98927_current_limit,
MAX98927_R0042_BOOST_CTRL1, 1,
max98927_current_limit_text);
static const struct snd_kcontrol_new max98927_snd_controls[] = {
SOC_SINGLE_TLV("Speaker Volume", MAX98927_R003C_SPK_GAIN, 0, 6, 0,
max98927_spk_tlv),
SOC_SINGLE_TLV("Digital Volume", MAX98927_R0036_AMP_VOL_CTRL,
0, (1 << MAX98927_AMP_VOL_WIDTH) - 1, 0,
max98927_digital_tlv),
SOC_SINGLE("Amp DSP Switch", MAX98927_R0052_BROWNOUT_EN,
MAX98927_BROWNOUT_DSP_SHIFT, 1, 0),
SOC_SINGLE("Ramp Switch", MAX98927_R0037_AMP_DSP_CFG,
MAX98927_AMP_DSP_CFG_RMP_SHIFT, 1, 0),
SOC_SINGLE("DRE Switch", MAX98927_R0039_DRE_CTRL, MAX98927_DRE_EN_SHIFT,
1, 0),
SOC_SINGLE("Volume Location Switch", MAX98927_R0036_AMP_VOL_CTRL,
MAX98927_AMP_VOL_SEL_SHIFT, 1, 0),
SOC_ENUM("Boost Output Voltage", max98927_boost_voltage),
SOC_ENUM("Current Limit", max98927_current_limit),
};
static const struct snd_soc_dapm_route max98927_audio_map[] = {
/* Plabyack */
{"DAI Sel Mux", "Left", "Amp Enable"},
{"DAI Sel Mux", "Right", "Amp Enable"},
{"DAI Sel Mux", "LeftRight", "Amp Enable"},
{"BE_OUT", NULL, "DAI Sel Mux"},
/* Capture */
{ "VI Sense", "Switch", "VMON" },
{ "VI Sense", "Switch", "IMON" },
{ "Voltage Sense", NULL, "VI Sense" },
{ "Current Sense", NULL, "VI Sense" },
};
static struct snd_soc_dai_driver max98927_dai[] = {
{
.name = "max98927-aif1",
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MAX98927_RATES,
.formats = MAX98927_FORMATS,
},
.capture = {
.stream_name = "HiFi Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MAX98927_RATES,
.formats = MAX98927_FORMATS,
},
.ops = &max98927_dai_ops,
}
};
static int max98927_probe(struct snd_soc_component *component)
{
struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
max98927->component = component;
/* Software Reset */
regmap_write(max98927->regmap, MAX98927_R0100_SOFT_RESET,
MAX98927_SOFT_RESET);
/* IV default slot configuration */
regmap_write(max98927->regmap, MAX98927_R001C_PCM_TX_HIZ_CTRL_A, 0xFF);
regmap_write(max98927->regmap, MAX98927_R001D_PCM_TX_HIZ_CTRL_B, 0xFF);
regmap_write(max98927->regmap, MAX98927_R0025_PCM_TO_SPK_MONOMIX_A,
0x80);
regmap_write(max98927->regmap, MAX98927_R0026_PCM_TO_SPK_MONOMIX_B,
0x1);
/* Set inital volume (+13dB) */
regmap_write(max98927->regmap, MAX98927_R0036_AMP_VOL_CTRL, 0x38);
regmap_write(max98927->regmap, MAX98927_R003C_SPK_GAIN, 0x05);
/* Enable DC blocker */
regmap_write(max98927->regmap, MAX98927_R0037_AMP_DSP_CFG, 0x03);
/* Enable IMON VMON DC blocker */
regmap_write(max98927->regmap, MAX98927_R003F_MEAS_DSP_CFG, 0xF7);
/* Boost Output Voltage & Current limit */
regmap_write(max98927->regmap, MAX98927_R0040_BOOST_CTRL0, 0x1C);
regmap_write(max98927->regmap, MAX98927_R0042_BOOST_CTRL1, 0x3E);
/* Measurement ADC config */
regmap_write(max98927->regmap, MAX98927_R0043_MEAS_ADC_CFG, 0x04);
regmap_write(max98927->regmap, MAX98927_R0044_MEAS_ADC_BASE_MSB, 0x00);
regmap_write(max98927->regmap, MAX98927_R0045_MEAS_ADC_BASE_LSB, 0x24);
/* Brownout Level */
regmap_write(max98927->regmap, MAX98927_R007F_BROWNOUT_LVL4_AMP1_CTRL1,
0x06);
/* Envelope Tracking configuration */
regmap_write(max98927->regmap, MAX98927_R0082_ENV_TRACK_VOUT_HEADROOM,
0x08);
regmap_write(max98927->regmap, MAX98927_R0086_ENV_TRACK_CTRL, 0x01);
regmap_write(max98927->regmap, MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ,
0x10);
/* voltage, current slot configuration */
regmap_write(max98927->regmap, MAX98927_R001E_PCM_TX_CH_SRC_A,
(max98927->i_l_slot << MAX98927_PCM_TX_CH_SRC_A_I_SHIFT | max98927->v_l_slot) & 0xFF);
if (max98927->v_l_slot < 8) {
regmap_update_bits(max98927->regmap,
MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
1 << max98927->v_l_slot, 0);
regmap_update_bits(max98927->regmap, MAX98927_R001A_PCM_TX_EN_A,
1 << max98927->v_l_slot,
1 << max98927->v_l_slot);
} else {
regmap_update_bits(max98927->regmap,
MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
1 << (max98927->v_l_slot - 8), 0);
regmap_update_bits(max98927->regmap, MAX98927_R001B_PCM_TX_EN_B,
1 << (max98927->v_l_slot - 8),
1 << (max98927->v_l_slot - 8));
}
if (max98927->i_l_slot < 8) {
regmap_update_bits(max98927->regmap,
MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
1 << max98927->i_l_slot, 0);
regmap_update_bits(max98927->regmap, MAX98927_R001A_PCM_TX_EN_A,
1 << max98927->i_l_slot,
1 << max98927->i_l_slot);
} else {
regmap_update_bits(max98927->regmap,
MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
1 << (max98927->i_l_slot - 8), 0);
regmap_update_bits(max98927->regmap, MAX98927_R001B_PCM_TX_EN_B,
1 << (max98927->i_l_slot - 8),
1 << (max98927->i_l_slot - 8));
}
/* Set interleave mode */
if (max98927->interleave_mode)
regmap_update_bits(max98927->regmap,
MAX98927_R001F_PCM_TX_CH_SRC_B,
MAX98927_PCM_TX_CH_INTERLEAVE_MASK,
MAX98927_PCM_TX_CH_INTERLEAVE_MASK);
return 0;
}
#ifdef CONFIG_PM_SLEEP
static int max98927_suspend(struct device *dev)
{
struct max98927_priv *max98927 = dev_get_drvdata(dev);
regcache_cache_only(max98927->regmap, true);
regcache_mark_dirty(max98927->regmap);
return 0;
}
static int max98927_resume(struct device *dev)
{
struct max98927_priv *max98927 = dev_get_drvdata(dev);
regmap_write(max98927->regmap, MAX98927_R0100_SOFT_RESET,
MAX98927_SOFT_RESET);
regcache_cache_only(max98927->regmap, false);
regcache_sync(max98927->regmap);
return 0;
}
#endif
static const struct dev_pm_ops max98927_pm = {
SET_SYSTEM_SLEEP_PM_OPS(max98927_suspend, max98927_resume)
};
static const struct snd_soc_component_driver soc_component_dev_max98927 = {
.probe = max98927_probe,
.controls = max98927_snd_controls,
.num_controls = ARRAY_SIZE(max98927_snd_controls),
.dapm_widgets = max98927_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(max98927_dapm_widgets),
.dapm_routes = max98927_audio_map,
.num_dapm_routes = ARRAY_SIZE(max98927_audio_map),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config max98927_regmap = {
.reg_bits = 16,
.val_bits = 8,
.max_register = MAX98927_R01FF_REV_ID,
.reg_defaults = max98927_reg,
.num_reg_defaults = ARRAY_SIZE(max98927_reg),
.readable_reg = max98927_readable_register,
.volatile_reg = max98927_volatile_reg,
.cache_type = REGCACHE_RBTREE,
};
static void max98927_slot_config(struct i2c_client *i2c,
struct max98927_priv *max98927)
{
int value;
struct device *dev = &i2c->dev;
if (!device_property_read_u32(dev, "vmon-slot-no", &value))
max98927->v_l_slot = value & 0xF;
else
max98927->v_l_slot = 0;
if (!device_property_read_u32(dev, "imon-slot-no", &value))
max98927->i_l_slot = value & 0xF;
else
max98927->i_l_slot = 1;
}
static int max98927_i2c_probe(struct i2c_client *i2c)
{
int ret = 0, value;
int reg = 0;
struct max98927_priv *max98927 = NULL;
max98927 = devm_kzalloc(&i2c->dev, sizeof(*max98927), GFP_KERNEL);
if (!max98927) {
ret = -ENOMEM;
return ret;
}
i2c_set_clientdata(i2c, max98927);
/* update interleave mode info */
if (of_property_read_bool(i2c->dev.of_node, "maxim,interleave-mode")) {
max98927->interleave_mode = true;
} else {
if (!of_property_read_u32(i2c->dev.of_node, "interleave_mode",
&value))
if (value > 0)
max98927->interleave_mode = true;
}
/* regmap initialization */
max98927->regmap
= devm_regmap_init_i2c(i2c, &max98927_regmap);
if (IS_ERR(max98927->regmap)) {
ret = PTR_ERR(max98927->regmap);
dev_err(&i2c->dev,
"Failed to allocate regmap: %d\n", ret);
return ret;
}
max98927->reset_gpio = devm_gpiod_get_optional(&i2c->dev, "reset",
GPIOD_OUT_HIGH);
if (IS_ERR(max98927->reset_gpio)) {
ret = PTR_ERR(max98927->reset_gpio);
return dev_err_probe(&i2c->dev, ret, "failed to request GPIO reset pin");
}
if (max98927->reset_gpio) {
gpiod_set_value_cansleep(max98927->reset_gpio, 0);
/* Wait for i2c port to be ready */
usleep_range(5000, 6000);
}
/* Check Revision ID */
ret = regmap_read(max98927->regmap, MAX98927_R01FF_REV_ID, ®);
if (ret < 0) {
dev_err(&i2c->dev,
"Failed to read: 0x%02X\n", MAX98927_R01FF_REV_ID);
return ret;
}
dev_info(&i2c->dev, "MAX98927 revisionID: 0x%02X\n", reg);
/* voltage/current slot configuration */
max98927_slot_config(i2c, max98927);
/* codec registeration */
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_max98927,
max98927_dai, ARRAY_SIZE(max98927_dai));
if (ret < 0)
dev_err(&i2c->dev, "Failed to register component: %d\n", ret);
return ret;
}
static void max98927_i2c_remove(struct i2c_client *i2c)
{
struct max98927_priv *max98927 = i2c_get_clientdata(i2c);
if (max98927->reset_gpio)
gpiod_set_value_cansleep(max98927->reset_gpio, 1);
}
static const struct i2c_device_id max98927_i2c_id[] = {
{ "max98927", 0},
{ },
};
MODULE_DEVICE_TABLE(i2c, max98927_i2c_id);
#if defined(CONFIG_OF)
static const struct of_device_id max98927_of_match[] = {
{ .compatible = "maxim,max98927", },
{ }
};
MODULE_DEVICE_TABLE(of, max98927_of_match);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id max98927_acpi_match[] = {
{ "MX98927", 0 },
{},
};
MODULE_DEVICE_TABLE(acpi, max98927_acpi_match);
#endif
static struct i2c_driver max98927_i2c_driver = {
.driver = {
.name = "max98927",
.of_match_table = of_match_ptr(max98927_of_match),
.acpi_match_table = ACPI_PTR(max98927_acpi_match),
.pm = &max98927_pm,
},
.probe = max98927_i2c_probe,
.remove = max98927_i2c_remove,
.id_table = max98927_i2c_id,
};
module_i2c_driver(max98927_i2c_driver)
MODULE_DESCRIPTION("ALSA SoC MAX98927 driver");
MODULE_AUTHOR("Ryan Lee <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/max98927.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* cs35l35.c -- CS35L35 ALSA SoC audio driver
*
* Copyright 2017 Cirrus Logic, Inc.
*
* Author: Brian Austin <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/gpio/consumer.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <linux/gpio.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/cs35l35.h>
#include <linux/of_irq.h>
#include <linux/completion.h>
#include "cs35l35.h"
#include "cirrus_legacy.h"
/*
* Some fields take zero as a valid value so use a high bit flag that won't
* get written to the device to mark those.
*/
#define CS35L35_VALID_PDATA 0x80000000
static const struct reg_default cs35l35_reg[] = {
{CS35L35_PWRCTL1, 0x01},
{CS35L35_PWRCTL2, 0x11},
{CS35L35_PWRCTL3, 0x00},
{CS35L35_CLK_CTL1, 0x04},
{CS35L35_CLK_CTL2, 0x12},
{CS35L35_CLK_CTL3, 0xCF},
{CS35L35_SP_FMT_CTL1, 0x20},
{CS35L35_SP_FMT_CTL2, 0x00},
{CS35L35_SP_FMT_CTL3, 0x02},
{CS35L35_MAG_COMP_CTL, 0x00},
{CS35L35_AMP_INP_DRV_CTL, 0x01},
{CS35L35_AMP_DIG_VOL_CTL, 0x12},
{CS35L35_AMP_DIG_VOL, 0x00},
{CS35L35_ADV_DIG_VOL, 0x00},
{CS35L35_PROTECT_CTL, 0x06},
{CS35L35_AMP_GAIN_AUD_CTL, 0x13},
{CS35L35_AMP_GAIN_PDM_CTL, 0x00},
{CS35L35_AMP_GAIN_ADV_CTL, 0x00},
{CS35L35_GPI_CTL, 0x00},
{CS35L35_BST_CVTR_V_CTL, 0x00},
{CS35L35_BST_PEAK_I, 0x07},
{CS35L35_BST_RAMP_CTL, 0x85},
{CS35L35_BST_CONV_COEF_1, 0x24},
{CS35L35_BST_CONV_COEF_2, 0x24},
{CS35L35_BST_CONV_SLOPE_COMP, 0x4E},
{CS35L35_BST_CONV_SW_FREQ, 0x04},
{CS35L35_CLASS_H_CTL, 0x0B},
{CS35L35_CLASS_H_HEADRM_CTL, 0x0B},
{CS35L35_CLASS_H_RELEASE_RATE, 0x08},
{CS35L35_CLASS_H_FET_DRIVE_CTL, 0x41},
{CS35L35_CLASS_H_VP_CTL, 0xC5},
{CS35L35_VPBR_CTL, 0x0A},
{CS35L35_VPBR_VOL_CTL, 0x90},
{CS35L35_VPBR_TIMING_CTL, 0x6A},
{CS35L35_VPBR_MODE_VOL_CTL, 0x00},
{CS35L35_SPKR_MON_CTL, 0xC0},
{CS35L35_IMON_SCALE_CTL, 0x30},
{CS35L35_AUDIN_RXLOC_CTL, 0x00},
{CS35L35_ADVIN_RXLOC_CTL, 0x80},
{CS35L35_VMON_TXLOC_CTL, 0x00},
{CS35L35_IMON_TXLOC_CTL, 0x80},
{CS35L35_VPMON_TXLOC_CTL, 0x04},
{CS35L35_VBSTMON_TXLOC_CTL, 0x84},
{CS35L35_VPBR_STATUS_TXLOC_CTL, 0x04},
{CS35L35_ZERO_FILL_LOC_CTL, 0x00},
{CS35L35_AUDIN_DEPTH_CTL, 0x0F},
{CS35L35_SPKMON_DEPTH_CTL, 0x0F},
{CS35L35_SUPMON_DEPTH_CTL, 0x0F},
{CS35L35_ZEROFILL_DEPTH_CTL, 0x00},
{CS35L35_MULT_DEV_SYNCH1, 0x02},
{CS35L35_MULT_DEV_SYNCH2, 0x80},
{CS35L35_PROT_RELEASE_CTL, 0x00},
{CS35L35_DIAG_MODE_REG_LOCK, 0x00},
{CS35L35_DIAG_MODE_CTL_1, 0x40},
{CS35L35_DIAG_MODE_CTL_2, 0x00},
{CS35L35_INT_MASK_1, 0xFF},
{CS35L35_INT_MASK_2, 0xFF},
{CS35L35_INT_MASK_3, 0xFF},
{CS35L35_INT_MASK_4, 0xFF},
};
static bool cs35l35_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS35L35_INT_STATUS_1:
case CS35L35_INT_STATUS_2:
case CS35L35_INT_STATUS_3:
case CS35L35_INT_STATUS_4:
case CS35L35_PLL_STATUS:
case CS35L35_OTP_TRIM_STATUS:
return true;
default:
return false;
}
}
static bool cs35l35_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS35L35_DEVID_AB ... CS35L35_PWRCTL3:
case CS35L35_CLK_CTL1 ... CS35L35_SP_FMT_CTL3:
case CS35L35_MAG_COMP_CTL ... CS35L35_AMP_GAIN_AUD_CTL:
case CS35L35_AMP_GAIN_PDM_CTL ... CS35L35_BST_PEAK_I:
case CS35L35_BST_RAMP_CTL ... CS35L35_BST_CONV_SW_FREQ:
case CS35L35_CLASS_H_CTL ... CS35L35_CLASS_H_VP_CTL:
case CS35L35_CLASS_H_STATUS:
case CS35L35_VPBR_CTL ... CS35L35_VPBR_MODE_VOL_CTL:
case CS35L35_VPBR_ATTEN_STATUS:
case CS35L35_SPKR_MON_CTL:
case CS35L35_IMON_SCALE_CTL ... CS35L35_ZEROFILL_DEPTH_CTL:
case CS35L35_MULT_DEV_SYNCH1 ... CS35L35_PROT_RELEASE_CTL:
case CS35L35_DIAG_MODE_REG_LOCK ... CS35L35_DIAG_MODE_CTL_2:
case CS35L35_INT_MASK_1 ... CS35L35_PLL_STATUS:
case CS35L35_OTP_TRIM_STATUS:
return true;
default:
return false;
}
}
static bool cs35l35_precious_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS35L35_INT_STATUS_1:
case CS35L35_INT_STATUS_2:
case CS35L35_INT_STATUS_3:
case CS35L35_INT_STATUS_4:
case CS35L35_PLL_STATUS:
case CS35L35_OTP_TRIM_STATUS:
return true;
default:
return false;
}
}
static void cs35l35_reset(struct cs35l35_private *cs35l35)
{
gpiod_set_value_cansleep(cs35l35->reset_gpio, 0);
usleep_range(2000, 2100);
gpiod_set_value_cansleep(cs35l35->reset_gpio, 1);
usleep_range(1000, 1100);
}
static int cs35l35_wait_for_pdn(struct cs35l35_private *cs35l35)
{
int ret;
if (cs35l35->pdata.ext_bst) {
usleep_range(5000, 5500);
return 0;
}
reinit_completion(&cs35l35->pdn_done);
ret = wait_for_completion_timeout(&cs35l35->pdn_done,
msecs_to_jiffies(100));
if (ret == 0) {
dev_err(cs35l35->dev, "PDN_DONE did not complete\n");
return -ETIMEDOUT;
}
return 0;
}
static int cs35l35_sdin_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct cs35l35_private *cs35l35 = snd_soc_component_get_drvdata(component);
int ret = 0;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
CS35L35_MCLK_DIS_MASK,
0 << CS35L35_MCLK_DIS_SHIFT);
regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
CS35L35_DISCHG_FILT_MASK,
0 << CS35L35_DISCHG_FILT_SHIFT);
regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
CS35L35_PDN_ALL_MASK, 0);
break;
case SND_SOC_DAPM_POST_PMD:
regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
CS35L35_DISCHG_FILT_MASK,
1 << CS35L35_DISCHG_FILT_SHIFT);
regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
CS35L35_PDN_ALL_MASK, 1);
/* Already muted, so disable volume ramp for faster shutdown */
regmap_update_bits(cs35l35->regmap, CS35L35_AMP_DIG_VOL_CTL,
CS35L35_AMP_DIGSFT_MASK, 0);
ret = cs35l35_wait_for_pdn(cs35l35);
regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
CS35L35_MCLK_DIS_MASK,
1 << CS35L35_MCLK_DIS_SHIFT);
regmap_update_bits(cs35l35->regmap, CS35L35_AMP_DIG_VOL_CTL,
CS35L35_AMP_DIGSFT_MASK,
1 << CS35L35_AMP_DIGSFT_SHIFT);
break;
default:
dev_err(component->dev, "Invalid event = 0x%x\n", event);
ret = -EINVAL;
}
return ret;
}
static int cs35l35_main_amp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct cs35l35_private *cs35l35 = snd_soc_component_get_drvdata(component);
unsigned int reg[4];
int i;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
if (cs35l35->pdata.bst_pdn_fet_on)
regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
CS35L35_PDN_BST_MASK,
0 << CS35L35_PDN_BST_FETON_SHIFT);
else
regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
CS35L35_PDN_BST_MASK,
0 << CS35L35_PDN_BST_FETOFF_SHIFT);
break;
case SND_SOC_DAPM_POST_PMU:
usleep_range(5000, 5100);
/* If in PDM mode we must use VP for Voltage control */
if (cs35l35->pdm_mode)
regmap_update_bits(cs35l35->regmap,
CS35L35_BST_CVTR_V_CTL,
CS35L35_BST_CTL_MASK,
0 << CS35L35_BST_CTL_SHIFT);
regmap_update_bits(cs35l35->regmap, CS35L35_PROTECT_CTL,
CS35L35_AMP_MUTE_MASK, 0);
for (i = 0; i < 2; i++)
regmap_bulk_read(cs35l35->regmap, CS35L35_INT_STATUS_1,
®, ARRAY_SIZE(reg));
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_update_bits(cs35l35->regmap, CS35L35_PROTECT_CTL,
CS35L35_AMP_MUTE_MASK,
1 << CS35L35_AMP_MUTE_SHIFT);
if (cs35l35->pdata.bst_pdn_fet_on)
regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
CS35L35_PDN_BST_MASK,
1 << CS35L35_PDN_BST_FETON_SHIFT);
else
regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
CS35L35_PDN_BST_MASK,
1 << CS35L35_PDN_BST_FETOFF_SHIFT);
break;
case SND_SOC_DAPM_POST_PMD:
usleep_range(5000, 5100);
/*
* If PDM mode we should switch back to pdata value
* for Voltage control when we go down
*/
if (cs35l35->pdm_mode)
regmap_update_bits(cs35l35->regmap,
CS35L35_BST_CVTR_V_CTL,
CS35L35_BST_CTL_MASK,
cs35l35->pdata.bst_vctl
<< CS35L35_BST_CTL_SHIFT);
break;
default:
dev_err(component->dev, "Invalid event = 0x%x\n", event);
}
return 0;
}
static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 0, 1, 1);
static DECLARE_TLV_DB_SCALE(dig_vol_tlv, -10200, 50, 0);
static const struct snd_kcontrol_new cs35l35_aud_controls[] = {
SOC_SINGLE_SX_TLV("Digital Audio Volume", CS35L35_AMP_DIG_VOL,
0, 0x34, 0xE4, dig_vol_tlv),
SOC_SINGLE_TLV("Analog Audio Volume", CS35L35_AMP_GAIN_AUD_CTL, 0, 19, 0,
amp_gain_tlv),
SOC_SINGLE_TLV("PDM Volume", CS35L35_AMP_GAIN_PDM_CTL, 0, 19, 0,
amp_gain_tlv),
};
static const struct snd_kcontrol_new cs35l35_adv_controls[] = {
SOC_SINGLE_SX_TLV("Digital Advisory Volume", CS35L35_ADV_DIG_VOL,
0, 0x34, 0xE4, dig_vol_tlv),
SOC_SINGLE_TLV("Analog Advisory Volume", CS35L35_AMP_GAIN_ADV_CTL, 0, 19, 0,
amp_gain_tlv),
};
static const struct snd_soc_dapm_widget cs35l35_dapm_widgets[] = {
SND_SOC_DAPM_AIF_IN_E("SDIN", NULL, 0, CS35L35_PWRCTL3, 1, 1,
cs35l35_sdin_event, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_AIF_OUT("SDOUT", NULL, 0, CS35L35_PWRCTL3, 2, 1),
SND_SOC_DAPM_OUTPUT("SPK"),
SND_SOC_DAPM_INPUT("VP"),
SND_SOC_DAPM_INPUT("VBST"),
SND_SOC_DAPM_INPUT("ISENSE"),
SND_SOC_DAPM_INPUT("VSENSE"),
SND_SOC_DAPM_ADC("VMON ADC", NULL, CS35L35_PWRCTL2, 7, 1),
SND_SOC_DAPM_ADC("IMON ADC", NULL, CS35L35_PWRCTL2, 6, 1),
SND_SOC_DAPM_ADC("VPMON ADC", NULL, CS35L35_PWRCTL3, 3, 1),
SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, CS35L35_PWRCTL3, 4, 1),
SND_SOC_DAPM_ADC("CLASS H", NULL, CS35L35_PWRCTL2, 5, 1),
SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L35_PWRCTL2, 0, 1, NULL, 0,
cs35l35_main_amp_event, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD),
};
static const struct snd_soc_dapm_route cs35l35_audio_map[] = {
{"VPMON ADC", NULL, "VP"},
{"VBSTMON ADC", NULL, "VBST"},
{"IMON ADC", NULL, "ISENSE"},
{"VMON ADC", NULL, "VSENSE"},
{"SDOUT", NULL, "IMON ADC"},
{"SDOUT", NULL, "VMON ADC"},
{"SDOUT", NULL, "VBSTMON ADC"},
{"SDOUT", NULL, "VPMON ADC"},
{"AMP Capture", NULL, "SDOUT"},
{"SDIN", NULL, "AMP Playback"},
{"CLASS H", NULL, "SDIN"},
{"Main AMP", NULL, "CLASS H"},
{"SPK", NULL, "Main AMP"},
};
static int cs35l35_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct cs35l35_private *cs35l35 = snd_soc_component_get_drvdata(component);
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
CS35L35_MS_MASK, 1 << CS35L35_MS_SHIFT);
cs35l35->clock_consumer = false;
break;
case SND_SOC_DAIFMT_CBC_CFC:
regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
CS35L35_MS_MASK, 0 << CS35L35_MS_SHIFT);
cs35l35->clock_consumer = true;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
cs35l35->i2s_mode = true;
cs35l35->pdm_mode = false;
break;
case SND_SOC_DAIFMT_PDM:
cs35l35->pdm_mode = true;
cs35l35->i2s_mode = false;
break;
default:
return -EINVAL;
}
return 0;
}
struct cs35l35_sysclk_config {
int sysclk;
int srate;
u8 clk_cfg;
};
static struct cs35l35_sysclk_config cs35l35_clk_ctl[] = {
/* SYSCLK, Sample Rate, Serial Port Cfg */
{5644800, 44100, 0x00},
{5644800, 88200, 0x40},
{6144000, 48000, 0x10},
{6144000, 96000, 0x50},
{11289600, 44100, 0x01},
{11289600, 88200, 0x41},
{11289600, 176400, 0x81},
{12000000, 44100, 0x03},
{12000000, 48000, 0x13},
{12000000, 88200, 0x43},
{12000000, 96000, 0x53},
{12000000, 176400, 0x83},
{12000000, 192000, 0x93},
{12288000, 48000, 0x11},
{12288000, 96000, 0x51},
{12288000, 192000, 0x91},
{13000000, 44100, 0x07},
{13000000, 48000, 0x17},
{13000000, 88200, 0x47},
{13000000, 96000, 0x57},
{13000000, 176400, 0x87},
{13000000, 192000, 0x97},
{22579200, 44100, 0x02},
{22579200, 88200, 0x42},
{22579200, 176400, 0x82},
{24000000, 44100, 0x0B},
{24000000, 48000, 0x1B},
{24000000, 88200, 0x4B},
{24000000, 96000, 0x5B},
{24000000, 176400, 0x8B},
{24000000, 192000, 0x9B},
{24576000, 48000, 0x12},
{24576000, 96000, 0x52},
{24576000, 192000, 0x92},
{26000000, 44100, 0x0F},
{26000000, 48000, 0x1F},
{26000000, 88200, 0x4F},
{26000000, 96000, 0x5F},
{26000000, 176400, 0x8F},
{26000000, 192000, 0x9F},
};
static int cs35l35_get_clk_config(int sysclk, int srate)
{
int i;
for (i = 0; i < ARRAY_SIZE(cs35l35_clk_ctl); i++) {
if (cs35l35_clk_ctl[i].sysclk == sysclk &&
cs35l35_clk_ctl[i].srate == srate)
return cs35l35_clk_ctl[i].clk_cfg;
}
return -EINVAL;
}
static int cs35l35_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct cs35l35_private *cs35l35 = snd_soc_component_get_drvdata(component);
struct classh_cfg *classh = &cs35l35->pdata.classh_algo;
int srate = params_rate(params);
int ret = 0;
u8 sp_sclks;
int audin_format;
int errata_chk;
int clk_ctl = cs35l35_get_clk_config(cs35l35->sysclk, srate);
if (clk_ctl < 0) {
dev_err(component->dev, "Invalid CLK:Rate %d:%d\n",
cs35l35->sysclk, srate);
return -EINVAL;
}
ret = regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL2,
CS35L35_CLK_CTL2_MASK, clk_ctl);
if (ret != 0) {
dev_err(component->dev, "Failed to set port config %d\n", ret);
return ret;
}
/*
* Rev A0 Errata
* When configured for the weak-drive detection path (CH_WKFET_DIS = 0)
* the Class H algorithm does not enable weak-drive operation for
* nonzero values of CH_WKFET_DELAY if SP_RATE = 01 or 10
*/
errata_chk = (clk_ctl & CS35L35_SP_RATE_MASK) >> CS35L35_SP_RATE_SHIFT;
if (classh->classh_wk_fet_disable == 0x00 &&
(errata_chk == 0x01 || errata_chk == 0x02)) {
ret = regmap_update_bits(cs35l35->regmap,
CS35L35_CLASS_H_FET_DRIVE_CTL,
CS35L35_CH_WKFET_DEL_MASK,
0 << CS35L35_CH_WKFET_DEL_SHIFT);
if (ret != 0) {
dev_err(component->dev, "Failed to set fet config %d\n",
ret);
return ret;
}
}
/*
* You can pull more Monitor data from the SDOUT pin than going to SDIN
* Just make sure your SCLK is fast enough to fill the frame
*/
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
switch (params_width(params)) {
case 8:
audin_format = CS35L35_SDIN_DEPTH_8;
break;
case 16:
audin_format = CS35L35_SDIN_DEPTH_16;
break;
case 24:
audin_format = CS35L35_SDIN_DEPTH_24;
break;
default:
dev_err(component->dev, "Unsupported Width %d\n",
params_width(params));
return -EINVAL;
}
regmap_update_bits(cs35l35->regmap,
CS35L35_AUDIN_DEPTH_CTL,
CS35L35_AUDIN_DEPTH_MASK,
audin_format <<
CS35L35_AUDIN_DEPTH_SHIFT);
if (cs35l35->pdata.stereo) {
regmap_update_bits(cs35l35->regmap,
CS35L35_AUDIN_DEPTH_CTL,
CS35L35_ADVIN_DEPTH_MASK,
audin_format <<
CS35L35_ADVIN_DEPTH_SHIFT);
}
}
if (cs35l35->i2s_mode) {
/* We have to take the SCLK to derive num sclks
* to configure the CLOCK_CTL3 register correctly
*/
if ((cs35l35->sclk / srate) % 4) {
dev_err(component->dev, "Unsupported sclk/fs ratio %d:%d\n",
cs35l35->sclk, srate);
return -EINVAL;
}
sp_sclks = ((cs35l35->sclk / srate) / 4) - 1;
/* Only certain ratios supported when device is a clock consumer */
if (cs35l35->clock_consumer) {
switch (sp_sclks) {
case CS35L35_SP_SCLKS_32FS:
case CS35L35_SP_SCLKS_48FS:
case CS35L35_SP_SCLKS_64FS:
break;
default:
dev_err(component->dev, "ratio not supported\n");
return -EINVAL;
}
} else {
/* Only certain ratios supported when device is a clock provider */
switch (sp_sclks) {
case CS35L35_SP_SCLKS_32FS:
case CS35L35_SP_SCLKS_64FS:
break;
default:
dev_err(component->dev, "ratio not supported\n");
return -EINVAL;
}
}
ret = regmap_update_bits(cs35l35->regmap,
CS35L35_CLK_CTL3,
CS35L35_SP_SCLKS_MASK, sp_sclks <<
CS35L35_SP_SCLKS_SHIFT);
if (ret != 0) {
dev_err(component->dev, "Failed to set fsclk %d\n", ret);
return ret;
}
}
return ret;
}
static const unsigned int cs35l35_src_rates[] = {
44100, 48000, 88200, 96000, 176400, 192000
};
static const struct snd_pcm_hw_constraint_list cs35l35_constraints = {
.count = ARRAY_SIZE(cs35l35_src_rates),
.list = cs35l35_src_rates,
};
static int cs35l35_pcm_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct cs35l35_private *cs35l35 = snd_soc_component_get_drvdata(component);
if (!substream->runtime)
return 0;
snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE, &cs35l35_constraints);
regmap_update_bits(cs35l35->regmap, CS35L35_AMP_INP_DRV_CTL,
CS35L35_PDM_MODE_MASK,
0 << CS35L35_PDM_MODE_SHIFT);
return 0;
}
static const unsigned int cs35l35_pdm_rates[] = {
44100, 48000, 88200, 96000
};
static const struct snd_pcm_hw_constraint_list cs35l35_pdm_constraints = {
.count = ARRAY_SIZE(cs35l35_pdm_rates),
.list = cs35l35_pdm_rates,
};
static int cs35l35_pdm_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct cs35l35_private *cs35l35 = snd_soc_component_get_drvdata(component);
if (!substream->runtime)
return 0;
snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&cs35l35_pdm_constraints);
regmap_update_bits(cs35l35->regmap, CS35L35_AMP_INP_DRV_CTL,
CS35L35_PDM_MODE_MASK,
1 << CS35L35_PDM_MODE_SHIFT);
return 0;
}
static int cs35l35_dai_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct cs35l35_private *cs35l35 = snd_soc_component_get_drvdata(component);
/* Need the SCLK Frequency regardless of sysclk source for I2S */
cs35l35->sclk = freq;
return 0;
}
static const struct snd_soc_dai_ops cs35l35_ops = {
.startup = cs35l35_pcm_startup,
.set_fmt = cs35l35_set_dai_fmt,
.hw_params = cs35l35_hw_params,
.set_sysclk = cs35l35_dai_set_sysclk,
};
static const struct snd_soc_dai_ops cs35l35_pdm_ops = {
.startup = cs35l35_pdm_startup,
.set_fmt = cs35l35_set_dai_fmt,
.hw_params = cs35l35_hw_params,
};
static struct snd_soc_dai_driver cs35l35_dai[] = {
{
.name = "cs35l35-pcm",
.id = 0,
.playback = {
.stream_name = "AMP Playback",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = CS35L35_FORMATS,
},
.capture = {
.stream_name = "AMP Capture",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = CS35L35_FORMATS,
},
.ops = &cs35l35_ops,
.symmetric_rate = 1,
},
{
.name = "cs35l35-pdm",
.id = 1,
.playback = {
.stream_name = "PDM Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = CS35L35_FORMATS,
},
.ops = &cs35l35_pdm_ops,
},
};
static int cs35l35_component_set_sysclk(struct snd_soc_component *component,
int clk_id, int source, unsigned int freq,
int dir)
{
struct cs35l35_private *cs35l35 = snd_soc_component_get_drvdata(component);
int clksrc;
int ret = 0;
switch (clk_id) {
case 0:
clksrc = CS35L35_CLK_SOURCE_MCLK;
break;
case 1:
clksrc = CS35L35_CLK_SOURCE_SCLK;
break;
case 2:
clksrc = CS35L35_CLK_SOURCE_PDM;
break;
default:
dev_err(component->dev, "Invalid CLK Source\n");
return -EINVAL;
}
switch (freq) {
case 5644800:
case 6144000:
case 11289600:
case 12000000:
case 12288000:
case 13000000:
case 22579200:
case 24000000:
case 24576000:
case 26000000:
cs35l35->sysclk = freq;
break;
default:
dev_err(component->dev, "Invalid CLK Frequency Input : %d\n", freq);
return -EINVAL;
}
ret = regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
CS35L35_CLK_SOURCE_MASK,
clksrc << CS35L35_CLK_SOURCE_SHIFT);
if (ret != 0) {
dev_err(component->dev, "Failed to set sysclk %d\n", ret);
return ret;
}
return ret;
}
static int cs35l35_boost_inductor(struct cs35l35_private *cs35l35,
int inductor)
{
struct regmap *regmap = cs35l35->regmap;
unsigned int bst_ipk = 0;
/*
* Digital Boost Converter Configuration for feedback,
* ramping, switching frequency, and estimation block seeding.
*/
regmap_update_bits(regmap, CS35L35_BST_CONV_SW_FREQ,
CS35L35_BST_CONV_SWFREQ_MASK, 0x00);
regmap_read(regmap, CS35L35_BST_PEAK_I, &bst_ipk);
bst_ipk &= CS35L35_BST_IPK_MASK;
switch (inductor) {
case 1000: /* 1 uH */
regmap_write(regmap, CS35L35_BST_CONV_COEF_1, 0x24);
regmap_write(regmap, CS35L35_BST_CONV_COEF_2, 0x24);
regmap_update_bits(regmap, CS35L35_BST_CONV_SW_FREQ,
CS35L35_BST_CONV_LBST_MASK, 0x00);
if (bst_ipk < 0x04)
regmap_write(regmap, CS35L35_BST_CONV_SLOPE_COMP, 0x1B);
else
regmap_write(regmap, CS35L35_BST_CONV_SLOPE_COMP, 0x4E);
break;
case 1200: /* 1.2 uH */
regmap_write(regmap, CS35L35_BST_CONV_COEF_1, 0x20);
regmap_write(regmap, CS35L35_BST_CONV_COEF_2, 0x20);
regmap_update_bits(regmap, CS35L35_BST_CONV_SW_FREQ,
CS35L35_BST_CONV_LBST_MASK, 0x01);
if (bst_ipk < 0x04)
regmap_write(regmap, CS35L35_BST_CONV_SLOPE_COMP, 0x1B);
else
regmap_write(regmap, CS35L35_BST_CONV_SLOPE_COMP, 0x47);
break;
case 1500: /* 1.5uH */
regmap_write(regmap, CS35L35_BST_CONV_COEF_1, 0x20);
regmap_write(regmap, CS35L35_BST_CONV_COEF_2, 0x20);
regmap_update_bits(regmap, CS35L35_BST_CONV_SW_FREQ,
CS35L35_BST_CONV_LBST_MASK, 0x02);
if (bst_ipk < 0x04)
regmap_write(regmap, CS35L35_BST_CONV_SLOPE_COMP, 0x1B);
else
regmap_write(regmap, CS35L35_BST_CONV_SLOPE_COMP, 0x3C);
break;
case 2200: /* 2.2uH */
regmap_write(regmap, CS35L35_BST_CONV_COEF_1, 0x19);
regmap_write(regmap, CS35L35_BST_CONV_COEF_2, 0x25);
regmap_update_bits(regmap, CS35L35_BST_CONV_SW_FREQ,
CS35L35_BST_CONV_LBST_MASK, 0x03);
if (bst_ipk < 0x04)
regmap_write(regmap, CS35L35_BST_CONV_SLOPE_COMP, 0x1B);
else
regmap_write(regmap, CS35L35_BST_CONV_SLOPE_COMP, 0x23);
break;
default:
dev_err(cs35l35->dev, "Invalid Inductor Value %d uH\n",
inductor);
return -EINVAL;
}
return 0;
}
static int cs35l35_component_probe(struct snd_soc_component *component)
{
struct cs35l35_private *cs35l35 = snd_soc_component_get_drvdata(component);
struct classh_cfg *classh = &cs35l35->pdata.classh_algo;
struct monitor_cfg *monitor_config = &cs35l35->pdata.mon_cfg;
int ret;
/* Set Platform Data */
if (cs35l35->pdata.bst_vctl)
regmap_update_bits(cs35l35->regmap, CS35L35_BST_CVTR_V_CTL,
CS35L35_BST_CTL_MASK,
cs35l35->pdata.bst_vctl);
if (cs35l35->pdata.bst_ipk)
regmap_update_bits(cs35l35->regmap, CS35L35_BST_PEAK_I,
CS35L35_BST_IPK_MASK,
cs35l35->pdata.bst_ipk <<
CS35L35_BST_IPK_SHIFT);
ret = cs35l35_boost_inductor(cs35l35, cs35l35->pdata.boost_ind);
if (ret)
return ret;
if (cs35l35->pdata.gain_zc)
regmap_update_bits(cs35l35->regmap, CS35L35_PROTECT_CTL,
CS35L35_AMP_GAIN_ZC_MASK,
cs35l35->pdata.gain_zc <<
CS35L35_AMP_GAIN_ZC_SHIFT);
if (cs35l35->pdata.aud_channel)
regmap_update_bits(cs35l35->regmap,
CS35L35_AUDIN_RXLOC_CTL,
CS35L35_AUD_IN_LR_MASK,
cs35l35->pdata.aud_channel <<
CS35L35_AUD_IN_LR_SHIFT);
if (cs35l35->pdata.stereo) {
regmap_update_bits(cs35l35->regmap,
CS35L35_ADVIN_RXLOC_CTL,
CS35L35_ADV_IN_LR_MASK,
cs35l35->pdata.adv_channel <<
CS35L35_ADV_IN_LR_SHIFT);
if (cs35l35->pdata.shared_bst)
regmap_update_bits(cs35l35->regmap, CS35L35_CLASS_H_CTL,
CS35L35_CH_STEREO_MASK,
1 << CS35L35_CH_STEREO_SHIFT);
ret = snd_soc_add_component_controls(component, cs35l35_adv_controls,
ARRAY_SIZE(cs35l35_adv_controls));
if (ret)
return ret;
}
if (cs35l35->pdata.sp_drv_str)
regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
CS35L35_SP_DRV_MASK,
cs35l35->pdata.sp_drv_str <<
CS35L35_SP_DRV_SHIFT);
if (cs35l35->pdata.sp_drv_unused)
regmap_update_bits(cs35l35->regmap, CS35L35_SP_FMT_CTL3,
CS35L35_SP_I2S_DRV_MASK,
cs35l35->pdata.sp_drv_unused <<
CS35L35_SP_I2S_DRV_SHIFT);
if (classh->classh_algo_enable) {
if (classh->classh_bst_override)
regmap_update_bits(cs35l35->regmap,
CS35L35_CLASS_H_CTL,
CS35L35_CH_BST_OVR_MASK,
classh->classh_bst_override <<
CS35L35_CH_BST_OVR_SHIFT);
if (classh->classh_bst_max_limit)
regmap_update_bits(cs35l35->regmap,
CS35L35_CLASS_H_CTL,
CS35L35_CH_BST_LIM_MASK,
classh->classh_bst_max_limit <<
CS35L35_CH_BST_LIM_SHIFT);
if (classh->classh_mem_depth)
regmap_update_bits(cs35l35->regmap,
CS35L35_CLASS_H_CTL,
CS35L35_CH_MEM_DEPTH_MASK,
classh->classh_mem_depth <<
CS35L35_CH_MEM_DEPTH_SHIFT);
if (classh->classh_headroom)
regmap_update_bits(cs35l35->regmap,
CS35L35_CLASS_H_HEADRM_CTL,
CS35L35_CH_HDRM_CTL_MASK,
classh->classh_headroom <<
CS35L35_CH_HDRM_CTL_SHIFT);
if (classh->classh_release_rate)
regmap_update_bits(cs35l35->regmap,
CS35L35_CLASS_H_RELEASE_RATE,
CS35L35_CH_REL_RATE_MASK,
classh->classh_release_rate <<
CS35L35_CH_REL_RATE_SHIFT);
if (classh->classh_wk_fet_disable)
regmap_update_bits(cs35l35->regmap,
CS35L35_CLASS_H_FET_DRIVE_CTL,
CS35L35_CH_WKFET_DIS_MASK,
classh->classh_wk_fet_disable <<
CS35L35_CH_WKFET_DIS_SHIFT);
if (classh->classh_wk_fet_delay)
regmap_update_bits(cs35l35->regmap,
CS35L35_CLASS_H_FET_DRIVE_CTL,
CS35L35_CH_WKFET_DEL_MASK,
classh->classh_wk_fet_delay <<
CS35L35_CH_WKFET_DEL_SHIFT);
if (classh->classh_wk_fet_thld)
regmap_update_bits(cs35l35->regmap,
CS35L35_CLASS_H_FET_DRIVE_CTL,
CS35L35_CH_WKFET_THLD_MASK,
classh->classh_wk_fet_thld <<
CS35L35_CH_WKFET_THLD_SHIFT);
if (classh->classh_vpch_auto)
regmap_update_bits(cs35l35->regmap,
CS35L35_CLASS_H_VP_CTL,
CS35L35_CH_VP_AUTO_MASK,
classh->classh_vpch_auto <<
CS35L35_CH_VP_AUTO_SHIFT);
if (classh->classh_vpch_rate)
regmap_update_bits(cs35l35->regmap,
CS35L35_CLASS_H_VP_CTL,
CS35L35_CH_VP_RATE_MASK,
classh->classh_vpch_rate <<
CS35L35_CH_VP_RATE_SHIFT);
if (classh->classh_vpch_man)
regmap_update_bits(cs35l35->regmap,
CS35L35_CLASS_H_VP_CTL,
CS35L35_CH_VP_MAN_MASK,
classh->classh_vpch_man <<
CS35L35_CH_VP_MAN_SHIFT);
}
if (monitor_config->is_present) {
if (monitor_config->vmon_specs) {
regmap_update_bits(cs35l35->regmap,
CS35L35_SPKMON_DEPTH_CTL,
CS35L35_VMON_DEPTH_MASK,
monitor_config->vmon_dpth <<
CS35L35_VMON_DEPTH_SHIFT);
regmap_update_bits(cs35l35->regmap,
CS35L35_VMON_TXLOC_CTL,
CS35L35_MON_TXLOC_MASK,
monitor_config->vmon_loc <<
CS35L35_MON_TXLOC_SHIFT);
regmap_update_bits(cs35l35->regmap,
CS35L35_VMON_TXLOC_CTL,
CS35L35_MON_FRM_MASK,
monitor_config->vmon_frm <<
CS35L35_MON_FRM_SHIFT);
}
if (monitor_config->imon_specs) {
regmap_update_bits(cs35l35->regmap,
CS35L35_SPKMON_DEPTH_CTL,
CS35L35_IMON_DEPTH_MASK,
monitor_config->imon_dpth <<
CS35L35_IMON_DEPTH_SHIFT);
regmap_update_bits(cs35l35->regmap,
CS35L35_IMON_TXLOC_CTL,
CS35L35_MON_TXLOC_MASK,
monitor_config->imon_loc <<
CS35L35_MON_TXLOC_SHIFT);
regmap_update_bits(cs35l35->regmap,
CS35L35_IMON_TXLOC_CTL,
CS35L35_MON_FRM_MASK,
monitor_config->imon_frm <<
CS35L35_MON_FRM_SHIFT);
regmap_update_bits(cs35l35->regmap,
CS35L35_IMON_SCALE_CTL,
CS35L35_IMON_SCALE_MASK,
monitor_config->imon_scale <<
CS35L35_IMON_SCALE_SHIFT);
}
if (monitor_config->vpmon_specs) {
regmap_update_bits(cs35l35->regmap,
CS35L35_SUPMON_DEPTH_CTL,
CS35L35_VPMON_DEPTH_MASK,
monitor_config->vpmon_dpth <<
CS35L35_VPMON_DEPTH_SHIFT);
regmap_update_bits(cs35l35->regmap,
CS35L35_VPMON_TXLOC_CTL,
CS35L35_MON_TXLOC_MASK,
monitor_config->vpmon_loc <<
CS35L35_MON_TXLOC_SHIFT);
regmap_update_bits(cs35l35->regmap,
CS35L35_VPMON_TXLOC_CTL,
CS35L35_MON_FRM_MASK,
monitor_config->vpmon_frm <<
CS35L35_MON_FRM_SHIFT);
}
if (monitor_config->vbstmon_specs) {
regmap_update_bits(cs35l35->regmap,
CS35L35_SUPMON_DEPTH_CTL,
CS35L35_VBSTMON_DEPTH_MASK,
monitor_config->vpmon_dpth <<
CS35L35_VBSTMON_DEPTH_SHIFT);
regmap_update_bits(cs35l35->regmap,
CS35L35_VBSTMON_TXLOC_CTL,
CS35L35_MON_TXLOC_MASK,
monitor_config->vbstmon_loc <<
CS35L35_MON_TXLOC_SHIFT);
regmap_update_bits(cs35l35->regmap,
CS35L35_VBSTMON_TXLOC_CTL,
CS35L35_MON_FRM_MASK,
monitor_config->vbstmon_frm <<
CS35L35_MON_FRM_SHIFT);
}
if (monitor_config->vpbrstat_specs) {
regmap_update_bits(cs35l35->regmap,
CS35L35_SUPMON_DEPTH_CTL,
CS35L35_VPBRSTAT_DEPTH_MASK,
monitor_config->vpbrstat_dpth <<
CS35L35_VPBRSTAT_DEPTH_SHIFT);
regmap_update_bits(cs35l35->regmap,
CS35L35_VPBR_STATUS_TXLOC_CTL,
CS35L35_MON_TXLOC_MASK,
monitor_config->vpbrstat_loc <<
CS35L35_MON_TXLOC_SHIFT);
regmap_update_bits(cs35l35->regmap,
CS35L35_VPBR_STATUS_TXLOC_CTL,
CS35L35_MON_FRM_MASK,
monitor_config->vpbrstat_frm <<
CS35L35_MON_FRM_SHIFT);
}
if (monitor_config->zerofill_specs) {
regmap_update_bits(cs35l35->regmap,
CS35L35_SUPMON_DEPTH_CTL,
CS35L35_ZEROFILL_DEPTH_MASK,
monitor_config->zerofill_dpth <<
CS35L35_ZEROFILL_DEPTH_SHIFT);
regmap_update_bits(cs35l35->regmap,
CS35L35_ZERO_FILL_LOC_CTL,
CS35L35_MON_TXLOC_MASK,
monitor_config->zerofill_loc <<
CS35L35_MON_TXLOC_SHIFT);
regmap_update_bits(cs35l35->regmap,
CS35L35_ZERO_FILL_LOC_CTL,
CS35L35_MON_FRM_MASK,
monitor_config->zerofill_frm <<
CS35L35_MON_FRM_SHIFT);
}
}
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_cs35l35 = {
.probe = cs35l35_component_probe,
.set_sysclk = cs35l35_component_set_sysclk,
.dapm_widgets = cs35l35_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(cs35l35_dapm_widgets),
.dapm_routes = cs35l35_audio_map,
.num_dapm_routes = ARRAY_SIZE(cs35l35_audio_map),
.controls = cs35l35_aud_controls,
.num_controls = ARRAY_SIZE(cs35l35_aud_controls),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static struct regmap_config cs35l35_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = CS35L35_MAX_REGISTER,
.reg_defaults = cs35l35_reg,
.num_reg_defaults = ARRAY_SIZE(cs35l35_reg),
.volatile_reg = cs35l35_volatile_register,
.readable_reg = cs35l35_readable_register,
.precious_reg = cs35l35_precious_register,
.cache_type = REGCACHE_MAPLE,
.use_single_read = true,
.use_single_write = true,
};
static irqreturn_t cs35l35_irq(int irq, void *data)
{
struct cs35l35_private *cs35l35 = data;
unsigned int sticky1, sticky2, sticky3, sticky4;
unsigned int mask1, mask2, mask3, mask4, current1;
/* ack the irq by reading all status registers */
regmap_read(cs35l35->regmap, CS35L35_INT_STATUS_4, &sticky4);
regmap_read(cs35l35->regmap, CS35L35_INT_STATUS_3, &sticky3);
regmap_read(cs35l35->regmap, CS35L35_INT_STATUS_2, &sticky2);
regmap_read(cs35l35->regmap, CS35L35_INT_STATUS_1, &sticky1);
regmap_read(cs35l35->regmap, CS35L35_INT_MASK_4, &mask4);
regmap_read(cs35l35->regmap, CS35L35_INT_MASK_3, &mask3);
regmap_read(cs35l35->regmap, CS35L35_INT_MASK_2, &mask2);
regmap_read(cs35l35->regmap, CS35L35_INT_MASK_1, &mask1);
/* Check to see if unmasked bits are active */
if (!(sticky1 & ~mask1) && !(sticky2 & ~mask2) && !(sticky3 & ~mask3)
&& !(sticky4 & ~mask4))
return IRQ_NONE;
if (sticky2 & CS35L35_PDN_DONE)
complete(&cs35l35->pdn_done);
/* read the current values */
regmap_read(cs35l35->regmap, CS35L35_INT_STATUS_1, ¤t1);
/* handle the interrupts */
if (sticky1 & CS35L35_CAL_ERR) {
dev_crit(cs35l35->dev, "Calibration Error\n");
/* error is no longer asserted; safe to reset */
if (!(current1 & CS35L35_CAL_ERR)) {
pr_debug("%s : Cal error release\n", __func__);
regmap_update_bits(cs35l35->regmap,
CS35L35_PROT_RELEASE_CTL,
CS35L35_CAL_ERR_RLS, 0);
regmap_update_bits(cs35l35->regmap,
CS35L35_PROT_RELEASE_CTL,
CS35L35_CAL_ERR_RLS,
CS35L35_CAL_ERR_RLS);
regmap_update_bits(cs35l35->regmap,
CS35L35_PROT_RELEASE_CTL,
CS35L35_CAL_ERR_RLS, 0);
}
}
if (sticky1 & CS35L35_AMP_SHORT) {
dev_crit(cs35l35->dev, "AMP Short Error\n");
/* error is no longer asserted; safe to reset */
if (!(current1 & CS35L35_AMP_SHORT)) {
dev_dbg(cs35l35->dev, "Amp short error release\n");
regmap_update_bits(cs35l35->regmap,
CS35L35_PROT_RELEASE_CTL,
CS35L35_SHORT_RLS, 0);
regmap_update_bits(cs35l35->regmap,
CS35L35_PROT_RELEASE_CTL,
CS35L35_SHORT_RLS,
CS35L35_SHORT_RLS);
regmap_update_bits(cs35l35->regmap,
CS35L35_PROT_RELEASE_CTL,
CS35L35_SHORT_RLS, 0);
}
}
if (sticky1 & CS35L35_OTW) {
dev_warn(cs35l35->dev, "Over temperature warning\n");
/* error is no longer asserted; safe to reset */
if (!(current1 & CS35L35_OTW)) {
dev_dbg(cs35l35->dev, "Over temperature warn release\n");
regmap_update_bits(cs35l35->regmap,
CS35L35_PROT_RELEASE_CTL,
CS35L35_OTW_RLS, 0);
regmap_update_bits(cs35l35->regmap,
CS35L35_PROT_RELEASE_CTL,
CS35L35_OTW_RLS,
CS35L35_OTW_RLS);
regmap_update_bits(cs35l35->regmap,
CS35L35_PROT_RELEASE_CTL,
CS35L35_OTW_RLS, 0);
}
}
if (sticky1 & CS35L35_OTE) {
dev_crit(cs35l35->dev, "Over temperature error\n");
/* error is no longer asserted; safe to reset */
if (!(current1 & CS35L35_OTE)) {
dev_dbg(cs35l35->dev, "Over temperature error release\n");
regmap_update_bits(cs35l35->regmap,
CS35L35_PROT_RELEASE_CTL,
CS35L35_OTE_RLS, 0);
regmap_update_bits(cs35l35->regmap,
CS35L35_PROT_RELEASE_CTL,
CS35L35_OTE_RLS,
CS35L35_OTE_RLS);
regmap_update_bits(cs35l35->regmap,
CS35L35_PROT_RELEASE_CTL,
CS35L35_OTE_RLS, 0);
}
}
if (sticky3 & CS35L35_BST_HIGH) {
dev_crit(cs35l35->dev, "VBST error: powering off!\n");
regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
CS35L35_PDN_AMP, CS35L35_PDN_AMP);
regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
CS35L35_PDN_ALL, CS35L35_PDN_ALL);
}
if (sticky3 & CS35L35_LBST_SHORT) {
dev_crit(cs35l35->dev, "LBST error: powering off!\n");
regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
CS35L35_PDN_AMP, CS35L35_PDN_AMP);
regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
CS35L35_PDN_ALL, CS35L35_PDN_ALL);
}
if (sticky2 & CS35L35_VPBR_ERR)
dev_dbg(cs35l35->dev, "Error: Reactive Brownout\n");
if (sticky4 & CS35L35_VMON_OVFL)
dev_dbg(cs35l35->dev, "Error: VMON overflow\n");
if (sticky4 & CS35L35_IMON_OVFL)
dev_dbg(cs35l35->dev, "Error: IMON overflow\n");
return IRQ_HANDLED;
}
static int cs35l35_handle_of_data(struct i2c_client *i2c_client,
struct cs35l35_platform_data *pdata)
{
struct device_node *np = i2c_client->dev.of_node;
struct device_node *classh, *signal_format;
struct classh_cfg *classh_config = &pdata->classh_algo;
struct monitor_cfg *monitor_config = &pdata->mon_cfg;
unsigned int val32 = 0;
u8 monitor_array[4];
const int imon_array_size = ARRAY_SIZE(monitor_array);
const int mon_array_size = imon_array_size - 1;
int ret = 0;
if (!np)
return 0;
pdata->bst_pdn_fet_on = of_property_read_bool(np,
"cirrus,boost-pdn-fet-on");
ret = of_property_read_u32(np, "cirrus,boost-ctl-millivolt", &val32);
if (ret >= 0) {
if (val32 < 2600 || val32 > 9000) {
dev_err(&i2c_client->dev,
"Invalid Boost Voltage %d mV\n", val32);
return -EINVAL;
}
pdata->bst_vctl = ((val32 - 2600) / 100) + 1;
}
ret = of_property_read_u32(np, "cirrus,boost-peak-milliamp", &val32);
if (ret >= 0) {
if (val32 < 1680 || val32 > 4480) {
dev_err(&i2c_client->dev,
"Invalid Boost Peak Current %u mA\n", val32);
return -EINVAL;
}
pdata->bst_ipk = ((val32 - 1680) / 110) | CS35L35_VALID_PDATA;
}
ret = of_property_read_u32(np, "cirrus,boost-ind-nanohenry", &val32);
if (ret >= 0) {
pdata->boost_ind = val32;
} else {
dev_err(&i2c_client->dev, "Inductor not specified.\n");
return -EINVAL;
}
if (of_property_read_u32(np, "cirrus,sp-drv-strength", &val32) >= 0)
pdata->sp_drv_str = val32;
if (of_property_read_u32(np, "cirrus,sp-drv-unused", &val32) >= 0)
pdata->sp_drv_unused = val32 | CS35L35_VALID_PDATA;
pdata->stereo = of_property_read_bool(np, "cirrus,stereo-config");
if (pdata->stereo) {
ret = of_property_read_u32(np, "cirrus,audio-channel", &val32);
if (ret >= 0)
pdata->aud_channel = val32;
ret = of_property_read_u32(np, "cirrus,advisory-channel",
&val32);
if (ret >= 0)
pdata->adv_channel = val32;
pdata->shared_bst = of_property_read_bool(np,
"cirrus,shared-boost");
}
pdata->ext_bst = of_property_read_bool(np, "cirrus,external-boost");
pdata->gain_zc = of_property_read_bool(np, "cirrus,amp-gain-zc");
classh = of_get_child_by_name(np, "cirrus,classh-internal-algo");
classh_config->classh_algo_enable = (classh != NULL);
if (classh_config->classh_algo_enable) {
classh_config->classh_bst_override =
of_property_read_bool(np, "cirrus,classh-bst-overide");
ret = of_property_read_u32(classh,
"cirrus,classh-bst-max-limit",
&val32);
if (ret >= 0) {
val32 |= CS35L35_VALID_PDATA;
classh_config->classh_bst_max_limit = val32;
}
ret = of_property_read_u32(classh,
"cirrus,classh-bst-max-limit",
&val32);
if (ret >= 0) {
val32 |= CS35L35_VALID_PDATA;
classh_config->classh_bst_max_limit = val32;
}
ret = of_property_read_u32(classh, "cirrus,classh-mem-depth",
&val32);
if (ret >= 0) {
val32 |= CS35L35_VALID_PDATA;
classh_config->classh_mem_depth = val32;
}
ret = of_property_read_u32(classh, "cirrus,classh-release-rate",
&val32);
if (ret >= 0)
classh_config->classh_release_rate = val32;
ret = of_property_read_u32(classh, "cirrus,classh-headroom",
&val32);
if (ret >= 0) {
val32 |= CS35L35_VALID_PDATA;
classh_config->classh_headroom = val32;
}
ret = of_property_read_u32(classh,
"cirrus,classh-wk-fet-disable",
&val32);
if (ret >= 0)
classh_config->classh_wk_fet_disable = val32;
ret = of_property_read_u32(classh, "cirrus,classh-wk-fet-delay",
&val32);
if (ret >= 0) {
val32 |= CS35L35_VALID_PDATA;
classh_config->classh_wk_fet_delay = val32;
}
ret = of_property_read_u32(classh, "cirrus,classh-wk-fet-thld",
&val32);
if (ret >= 0)
classh_config->classh_wk_fet_thld = val32;
ret = of_property_read_u32(classh, "cirrus,classh-vpch-auto",
&val32);
if (ret >= 0) {
val32 |= CS35L35_VALID_PDATA;
classh_config->classh_vpch_auto = val32;
}
ret = of_property_read_u32(classh, "cirrus,classh-vpch-rate",
&val32);
if (ret >= 0) {
val32 |= CS35L35_VALID_PDATA;
classh_config->classh_vpch_rate = val32;
}
ret = of_property_read_u32(classh, "cirrus,classh-vpch-man",
&val32);
if (ret >= 0)
classh_config->classh_vpch_man = val32;
}
of_node_put(classh);
/* frame depth location */
signal_format = of_get_child_by_name(np, "cirrus,monitor-signal-format");
monitor_config->is_present = signal_format ? true : false;
if (monitor_config->is_present) {
ret = of_property_read_u8_array(signal_format, "cirrus,imon",
monitor_array, imon_array_size);
if (!ret) {
monitor_config->imon_specs = true;
monitor_config->imon_dpth = monitor_array[0];
monitor_config->imon_loc = monitor_array[1];
monitor_config->imon_frm = monitor_array[2];
monitor_config->imon_scale = monitor_array[3];
}
ret = of_property_read_u8_array(signal_format, "cirrus,vmon",
monitor_array, mon_array_size);
if (!ret) {
monitor_config->vmon_specs = true;
monitor_config->vmon_dpth = monitor_array[0];
monitor_config->vmon_loc = monitor_array[1];
monitor_config->vmon_frm = monitor_array[2];
}
ret = of_property_read_u8_array(signal_format, "cirrus,vpmon",
monitor_array, mon_array_size);
if (!ret) {
monitor_config->vpmon_specs = true;
monitor_config->vpmon_dpth = monitor_array[0];
monitor_config->vpmon_loc = monitor_array[1];
monitor_config->vpmon_frm = monitor_array[2];
}
ret = of_property_read_u8_array(signal_format, "cirrus,vbstmon",
monitor_array, mon_array_size);
if (!ret) {
monitor_config->vbstmon_specs = true;
monitor_config->vbstmon_dpth = monitor_array[0];
monitor_config->vbstmon_loc = monitor_array[1];
monitor_config->vbstmon_frm = monitor_array[2];
}
ret = of_property_read_u8_array(signal_format, "cirrus,vpbrstat",
monitor_array, mon_array_size);
if (!ret) {
monitor_config->vpbrstat_specs = true;
monitor_config->vpbrstat_dpth = monitor_array[0];
monitor_config->vpbrstat_loc = monitor_array[1];
monitor_config->vpbrstat_frm = monitor_array[2];
}
ret = of_property_read_u8_array(signal_format, "cirrus,zerofill",
monitor_array, mon_array_size);
if (!ret) {
monitor_config->zerofill_specs = true;
monitor_config->zerofill_dpth = monitor_array[0];
monitor_config->zerofill_loc = monitor_array[1];
monitor_config->zerofill_frm = monitor_array[2];
}
}
of_node_put(signal_format);
return 0;
}
/* Errata Rev A0 */
static const struct reg_sequence cs35l35_errata_patch[] = {
{ 0x7F, 0x99 },
{ 0x00, 0x99 },
{ 0x52, 0x22 },
{ 0x04, 0x14 },
{ 0x6D, 0x44 },
{ 0x24, 0x10 },
{ 0x58, 0xC4 },
{ 0x00, 0x98 },
{ 0x18, 0x08 },
{ 0x00, 0x00 },
{ 0x7F, 0x00 },
};
static int cs35l35_i2c_probe(struct i2c_client *i2c_client)
{
struct cs35l35_private *cs35l35;
struct device *dev = &i2c_client->dev;
struct cs35l35_platform_data *pdata = dev_get_platdata(dev);
int i, devid;
int ret;
unsigned int reg;
cs35l35 = devm_kzalloc(dev, sizeof(struct cs35l35_private), GFP_KERNEL);
if (!cs35l35)
return -ENOMEM;
cs35l35->dev = dev;
i2c_set_clientdata(i2c_client, cs35l35);
cs35l35->regmap = devm_regmap_init_i2c(i2c_client, &cs35l35_regmap);
if (IS_ERR(cs35l35->regmap)) {
ret = PTR_ERR(cs35l35->regmap);
dev_err(dev, "regmap_init() failed: %d\n", ret);
return ret;
}
for (i = 0; i < ARRAY_SIZE(cs35l35_supplies); i++)
cs35l35->supplies[i].supply = cs35l35_supplies[i];
cs35l35->num_supplies = ARRAY_SIZE(cs35l35_supplies);
ret = devm_regulator_bulk_get(dev, cs35l35->num_supplies,
cs35l35->supplies);
if (ret != 0) {
dev_err(dev, "Failed to request core supplies: %d\n", ret);
return ret;
}
if (pdata) {
cs35l35->pdata = *pdata;
} else {
pdata = devm_kzalloc(dev, sizeof(struct cs35l35_platform_data),
GFP_KERNEL);
if (!pdata)
return -ENOMEM;
if (i2c_client->dev.of_node) {
ret = cs35l35_handle_of_data(i2c_client, pdata);
if (ret != 0)
return ret;
}
cs35l35->pdata = *pdata;
}
ret = regulator_bulk_enable(cs35l35->num_supplies,
cs35l35->supplies);
if (ret != 0) {
dev_err(dev, "Failed to enable core supplies: %d\n", ret);
return ret;
}
/* returning NULL can be valid if in stereo mode */
cs35l35->reset_gpio = devm_gpiod_get_optional(dev, "reset",
GPIOD_OUT_LOW);
if (IS_ERR(cs35l35->reset_gpio)) {
ret = PTR_ERR(cs35l35->reset_gpio);
cs35l35->reset_gpio = NULL;
if (ret == -EBUSY) {
dev_info(dev,
"Reset line busy, assuming shared reset\n");
} else {
dev_err(dev, "Failed to get reset GPIO: %d\n", ret);
goto err;
}
}
cs35l35_reset(cs35l35);
init_completion(&cs35l35->pdn_done);
ret = devm_request_threaded_irq(dev, i2c_client->irq, NULL, cs35l35_irq,
IRQF_ONESHOT | IRQF_TRIGGER_LOW |
IRQF_SHARED, "cs35l35", cs35l35);
if (ret != 0) {
dev_err(dev, "Failed to request IRQ: %d\n", ret);
goto err;
}
/* initialize codec */
devid = cirrus_read_device_id(cs35l35->regmap, CS35L35_DEVID_AB);
if (devid < 0) {
ret = devid;
dev_err(dev, "Failed to read device ID: %d\n", ret);
goto err;
}
if (devid != CS35L35_CHIP_ID) {
dev_err(dev, "CS35L35 Device ID (%X). Expected ID %X\n",
devid, CS35L35_CHIP_ID);
ret = -ENODEV;
goto err;
}
ret = regmap_read(cs35l35->regmap, CS35L35_REV_ID, ®);
if (ret < 0) {
dev_err(dev, "Get Revision ID failed: %d\n", ret);
goto err;
}
ret = regmap_register_patch(cs35l35->regmap, cs35l35_errata_patch,
ARRAY_SIZE(cs35l35_errata_patch));
if (ret < 0) {
dev_err(dev, "Failed to apply errata patch: %d\n", ret);
goto err;
}
dev_info(dev, "Cirrus Logic CS35L35 (%x), Revision: %02X\n",
devid, reg & 0xFF);
/* Set the INT Masks for critical errors */
regmap_write(cs35l35->regmap, CS35L35_INT_MASK_1,
CS35L35_INT1_CRIT_MASK);
regmap_write(cs35l35->regmap, CS35L35_INT_MASK_2,
CS35L35_INT2_CRIT_MASK);
regmap_write(cs35l35->regmap, CS35L35_INT_MASK_3,
CS35L35_INT3_CRIT_MASK);
regmap_write(cs35l35->regmap, CS35L35_INT_MASK_4,
CS35L35_INT4_CRIT_MASK);
regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
CS35L35_PWR2_PDN_MASK,
CS35L35_PWR2_PDN_MASK);
if (cs35l35->pdata.bst_pdn_fet_on)
regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
CS35L35_PDN_BST_MASK,
1 << CS35L35_PDN_BST_FETON_SHIFT);
else
regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
CS35L35_PDN_BST_MASK,
1 << CS35L35_PDN_BST_FETOFF_SHIFT);
regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL3,
CS35L35_PWR3_PDN_MASK,
CS35L35_PWR3_PDN_MASK);
regmap_update_bits(cs35l35->regmap, CS35L35_PROTECT_CTL,
CS35L35_AMP_MUTE_MASK, 1 << CS35L35_AMP_MUTE_SHIFT);
ret = devm_snd_soc_register_component(dev, &soc_component_dev_cs35l35,
cs35l35_dai, ARRAY_SIZE(cs35l35_dai));
if (ret < 0) {
dev_err(dev, "Failed to register component: %d\n", ret);
goto err;
}
return 0;
err:
regulator_bulk_disable(cs35l35->num_supplies,
cs35l35->supplies);
gpiod_set_value_cansleep(cs35l35->reset_gpio, 0);
return ret;
}
static void cs35l35_i2c_remove(struct i2c_client *i2c_client)
{
struct cs35l35_private *cs35l35 = i2c_get_clientdata(i2c_client);
regulator_bulk_disable(cs35l35->num_supplies, cs35l35->supplies);
gpiod_set_value_cansleep(cs35l35->reset_gpio, 0);
}
static const struct of_device_id cs35l35_of_match[] = {
{.compatible = "cirrus,cs35l35"},
{},
};
MODULE_DEVICE_TABLE(of, cs35l35_of_match);
static const struct i2c_device_id cs35l35_id[] = {
{"cs35l35", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, cs35l35_id);
static struct i2c_driver cs35l35_i2c_driver = {
.driver = {
.name = "cs35l35",
.of_match_table = cs35l35_of_match,
},
.id_table = cs35l35_id,
.probe = cs35l35_i2c_probe,
.remove = cs35l35_i2c_remove,
};
module_i2c_driver(cs35l35_i2c_driver);
MODULE_DESCRIPTION("ASoC CS35L35 driver");
MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cs35l35.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for ADAU1361/ADAU1461/ADAU1761/ADAU1961 codec
*
* Copyright 2011-2013 Analog Devices Inc.
* Author: Lars-Peter Clausen <[email protected]>
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <linux/platform_data/adau17x1.h>
#include "adau17x1.h"
#include "adau1761.h"
#define ADAU1761_DIGMIC_JACKDETECT 0x4008
#define ADAU1761_REC_MIXER_LEFT0 0x400a
#define ADAU1761_REC_MIXER_LEFT1 0x400b
#define ADAU1761_REC_MIXER_RIGHT0 0x400c
#define ADAU1761_REC_MIXER_RIGHT1 0x400d
#define ADAU1761_LEFT_DIFF_INPUT_VOL 0x400e
#define ADAU1761_RIGHT_DIFF_INPUT_VOL 0x400f
#define ADAU1761_ALC_CTRL0 0x4011
#define ADAU1761_ALC_CTRL1 0x4012
#define ADAU1761_ALC_CTRL2 0x4013
#define ADAU1761_ALC_CTRL3 0x4014
#define ADAU1761_PLAY_LR_MIXER_LEFT 0x4020
#define ADAU1761_PLAY_MIXER_LEFT0 0x401c
#define ADAU1761_PLAY_MIXER_LEFT1 0x401d
#define ADAU1761_PLAY_MIXER_RIGHT0 0x401e
#define ADAU1761_PLAY_MIXER_RIGHT1 0x401f
#define ADAU1761_PLAY_LR_MIXER_RIGHT 0x4021
#define ADAU1761_PLAY_MIXER_MONO 0x4022
#define ADAU1761_PLAY_HP_LEFT_VOL 0x4023
#define ADAU1761_PLAY_HP_RIGHT_VOL 0x4024
#define ADAU1761_PLAY_LINE_LEFT_VOL 0x4025
#define ADAU1761_PLAY_LINE_RIGHT_VOL 0x4026
#define ADAU1761_PLAY_MONO_OUTPUT_VOL 0x4027
#define ADAU1761_POP_CLICK_SUPPRESS 0x4028
#define ADAU1761_JACK_DETECT_PIN 0x4031
#define ADAU1761_DEJITTER 0x4036
#define ADAU1761_CLK_ENABLE0 0x40f9
#define ADAU1761_CLK_ENABLE1 0x40fa
#define ADAU1761_DIGMIC_JACKDETECT_ACTIVE_LOW BIT(0)
#define ADAU1761_DIGMIC_JACKDETECT_DIGMIC BIT(5)
#define ADAU1761_DIFF_INPUT_VOL_LDEN BIT(0)
#define ADAU1761_PLAY_MONO_OUTPUT_VOL_MODE_HP BIT(0)
#define ADAU1761_PLAY_MONO_OUTPUT_VOL_UNMUTE BIT(1)
#define ADAU1761_PLAY_HP_RIGHT_VOL_MODE_HP BIT(0)
#define ADAU1761_PLAY_LINE_LEFT_VOL_MODE_HP BIT(0)
#define ADAU1761_PLAY_LINE_RIGHT_VOL_MODE_HP BIT(0)
#define ADAU1761_FIRMWARE "adau1761.bin"
static const struct reg_default adau1761_reg_defaults[] = {
{ ADAU1761_DEJITTER, 0x03 },
{ ADAU1761_DIGMIC_JACKDETECT, 0x00 },
{ ADAU1761_REC_MIXER_LEFT0, 0x00 },
{ ADAU1761_REC_MIXER_LEFT1, 0x00 },
{ ADAU1761_REC_MIXER_RIGHT0, 0x00 },
{ ADAU1761_REC_MIXER_RIGHT1, 0x00 },
{ ADAU1761_LEFT_DIFF_INPUT_VOL, 0x00 },
{ ADAU1761_ALC_CTRL0, 0x00 },
{ ADAU1761_ALC_CTRL1, 0x00 },
{ ADAU1761_ALC_CTRL2, 0x00 },
{ ADAU1761_ALC_CTRL3, 0x00 },
{ ADAU1761_RIGHT_DIFF_INPUT_VOL, 0x00 },
{ ADAU1761_PLAY_LR_MIXER_LEFT, 0x00 },
{ ADAU1761_PLAY_MIXER_LEFT0, 0x00 },
{ ADAU1761_PLAY_MIXER_LEFT1, 0x00 },
{ ADAU1761_PLAY_MIXER_RIGHT0, 0x00 },
{ ADAU1761_PLAY_MIXER_RIGHT1, 0x00 },
{ ADAU1761_PLAY_LR_MIXER_RIGHT, 0x00 },
{ ADAU1761_PLAY_MIXER_MONO, 0x00 },
{ ADAU1761_PLAY_HP_LEFT_VOL, 0x00 },
{ ADAU1761_PLAY_HP_RIGHT_VOL, 0x00 },
{ ADAU1761_PLAY_LINE_LEFT_VOL, 0x00 },
{ ADAU1761_PLAY_LINE_RIGHT_VOL, 0x00 },
{ ADAU1761_PLAY_MONO_OUTPUT_VOL, 0x00 },
{ ADAU1761_POP_CLICK_SUPPRESS, 0x00 },
{ ADAU1761_JACK_DETECT_PIN, 0x00 },
{ ADAU1761_CLK_ENABLE0, 0x00 },
{ ADAU1761_CLK_ENABLE1, 0x00 },
{ ADAU17X1_CLOCK_CONTROL, 0x00 },
{ ADAU17X1_PLL_CONTROL, 0x00 },
{ ADAU17X1_REC_POWER_MGMT, 0x00 },
{ ADAU17X1_MICBIAS, 0x00 },
{ ADAU17X1_SERIAL_PORT0, 0x00 },
{ ADAU17X1_SERIAL_PORT1, 0x00 },
{ ADAU17X1_CONVERTER0, 0x00 },
{ ADAU17X1_CONVERTER1, 0x00 },
{ ADAU17X1_LEFT_INPUT_DIGITAL_VOL, 0x00 },
{ ADAU17X1_RIGHT_INPUT_DIGITAL_VOL, 0x00 },
{ ADAU17X1_ADC_CONTROL, 0x00 },
{ ADAU17X1_PLAY_POWER_MGMT, 0x00 },
{ ADAU17X1_DAC_CONTROL0, 0x00 },
{ ADAU17X1_DAC_CONTROL1, 0x00 },
{ ADAU17X1_DAC_CONTROL2, 0x00 },
{ ADAU17X1_SERIAL_PORT_PAD, 0xaa },
{ ADAU17X1_CONTROL_PORT_PAD0, 0xaa },
{ ADAU17X1_CONTROL_PORT_PAD1, 0x00 },
{ ADAU17X1_DSP_SAMPLING_RATE, 0x01 },
{ ADAU17X1_SERIAL_INPUT_ROUTE, 0x00 },
{ ADAU17X1_SERIAL_OUTPUT_ROUTE, 0x00 },
{ ADAU17X1_DSP_ENABLE, 0x00 },
{ ADAU17X1_DSP_RUN, 0x00 },
{ ADAU17X1_SERIAL_SAMPLING_RATE, 0x00 },
};
static const DECLARE_TLV_DB_SCALE(adau1761_sing_in_tlv, -1500, 300, 1);
static const DECLARE_TLV_DB_SCALE(adau1761_diff_in_tlv, -1200, 75, 0);
static const DECLARE_TLV_DB_SCALE(adau1761_out_tlv, -5700, 100, 0);
static const DECLARE_TLV_DB_SCALE(adau1761_sidetone_tlv, -1800, 300, 1);
static const DECLARE_TLV_DB_SCALE(adau1761_boost_tlv, -600, 600, 1);
static const DECLARE_TLV_DB_SCALE(adau1761_pga_boost_tlv, -2000, 2000, 1);
static const DECLARE_TLV_DB_SCALE(adau1761_alc_max_gain_tlv, -1200, 600, 0);
static const DECLARE_TLV_DB_SCALE(adau1761_alc_target_tlv, -2850, 150, 0);
static const DECLARE_TLV_DB_SCALE(adau1761_alc_ng_threshold_tlv, -7650, 150, 0);
static const unsigned int adau1761_bias_select_values[] = {
0, 2, 3,
};
static const char * const adau1761_bias_select_text[] = {
"Normal operation", "Enhanced performance", "Power saving",
};
static const char * const adau1761_bias_select_extreme_text[] = {
"Normal operation", "Extreme power saving", "Enhanced performance",
"Power saving",
};
static SOC_ENUM_SINGLE_DECL(adau1761_adc_bias_enum,
ADAU17X1_REC_POWER_MGMT, 3, adau1761_bias_select_extreme_text);
static SOC_ENUM_SINGLE_DECL(adau1761_hp_bias_enum,
ADAU17X1_PLAY_POWER_MGMT, 6, adau1761_bias_select_extreme_text);
static SOC_ENUM_SINGLE_DECL(adau1761_dac_bias_enum,
ADAU17X1_PLAY_POWER_MGMT, 4, adau1761_bias_select_extreme_text);
static SOC_VALUE_ENUM_SINGLE_DECL(adau1761_playback_bias_enum,
ADAU17X1_PLAY_POWER_MGMT, 2, 0x3, adau1761_bias_select_text,
adau1761_bias_select_values);
static SOC_VALUE_ENUM_SINGLE_DECL(adau1761_capture_bias_enum,
ADAU17X1_REC_POWER_MGMT, 1, 0x3, adau1761_bias_select_text,
adau1761_bias_select_values);
static const unsigned int adau1761_pga_slew_time_values[] = {
3, 0, 1, 2,
};
static const char * const adau1761_pga_slew_time_text[] = {
"Off",
"24 ms",
"48 ms",
"96 ms",
};
static const char * const adau1761_alc_function_text[] = {
"Off",
"Right",
"Left",
"Stereo",
"DSP control",
};
static const char * const adau1761_alc_hold_time_text[] = {
"2.67 ms",
"5.34 ms",
"10.68 ms",
"21.36 ms",
"42.72 ms",
"85.44 ms",
"170.88 ms",
"341.76 ms",
"683.52 ms",
"1367 ms",
"2734.1 ms",
"5468.2 ms",
"10936 ms",
"21873 ms",
"43745 ms",
"87491 ms",
};
static const char * const adau1761_alc_attack_time_text[] = {
"6 ms",
"12 ms",
"24 ms",
"48 ms",
"96 ms",
"192 ms",
"384 ms",
"768 ms",
"1540 ms",
"3070 ms",
"6140 ms",
"12290 ms",
"24580 ms",
"49150 ms",
"98300 ms",
"196610 ms",
};
static const char * const adau1761_alc_decay_time_text[] = {
"24 ms",
"48 ms",
"96 ms",
"192 ms",
"384 ms",
"768 ms",
"15400 ms",
"30700 ms",
"61400 ms",
"12290 ms",
"24580 ms",
"49150 ms",
"98300 ms",
"196610 ms",
"393220 ms",
"786430 ms",
};
static const char * const adau1761_alc_ng_type_text[] = {
"Hold",
"Mute",
"Fade",
"Fade + Mute",
};
static SOC_VALUE_ENUM_SINGLE_DECL(adau1761_pga_slew_time_enum,
ADAU1761_ALC_CTRL0, 6, 0x3, adau1761_pga_slew_time_text,
adau1761_pga_slew_time_values);
static SOC_ENUM_SINGLE_DECL(adau1761_alc_function_enum,
ADAU1761_ALC_CTRL0, 0, adau1761_alc_function_text);
static SOC_ENUM_SINGLE_DECL(adau1761_alc_hold_time_enum,
ADAU1761_ALC_CTRL1, 4, adau1761_alc_hold_time_text);
static SOC_ENUM_SINGLE_DECL(adau1761_alc_attack_time_enum,
ADAU1761_ALC_CTRL2, 4, adau1761_alc_attack_time_text);
static SOC_ENUM_SINGLE_DECL(adau1761_alc_decay_time_enum,
ADAU1761_ALC_CTRL2, 0, adau1761_alc_decay_time_text);
static SOC_ENUM_SINGLE_DECL(adau1761_alc_ng_type_enum,
ADAU1761_ALC_CTRL3, 6, adau1761_alc_ng_type_text);
static const struct snd_kcontrol_new adau1761_jack_detect_controls[] = {
SOC_SINGLE("Speaker Auto-mute Switch", ADAU1761_DIGMIC_JACKDETECT,
4, 1, 0),
};
static const struct snd_kcontrol_new adau1761_differential_mode_controls[] = {
SOC_DOUBLE_R_TLV("Capture Volume", ADAU1761_LEFT_DIFF_INPUT_VOL,
ADAU1761_RIGHT_DIFF_INPUT_VOL, 2, 0x3f, 0,
adau1761_diff_in_tlv),
SOC_DOUBLE_R("Capture Switch", ADAU1761_LEFT_DIFF_INPUT_VOL,
ADAU1761_RIGHT_DIFF_INPUT_VOL, 1, 1, 0),
SOC_DOUBLE_R_TLV("PGA Boost Capture Volume", ADAU1761_REC_MIXER_LEFT1,
ADAU1761_REC_MIXER_RIGHT1, 3, 2, 0, adau1761_pga_boost_tlv),
SOC_ENUM("PGA Capture Slew Time", adau1761_pga_slew_time_enum),
SOC_SINGLE_TLV("ALC Capture Max Gain Volume", ADAU1761_ALC_CTRL0,
3, 7, 0, adau1761_alc_max_gain_tlv),
SOC_ENUM("ALC Capture Function", adau1761_alc_function_enum),
SOC_ENUM("ALC Capture Hold Time", adau1761_alc_hold_time_enum),
SOC_SINGLE_TLV("ALC Capture Target Volume", ADAU1761_ALC_CTRL1,
0, 15, 0, adau1761_alc_target_tlv),
SOC_ENUM("ALC Capture Attack Time", adau1761_alc_decay_time_enum),
SOC_ENUM("ALC Capture Decay Time", adau1761_alc_attack_time_enum),
SOC_ENUM("ALC Capture Noise Gate Type", adau1761_alc_ng_type_enum),
SOC_SINGLE("ALC Capture Noise Gate Switch",
ADAU1761_ALC_CTRL3, 5, 1, 0),
SOC_SINGLE_TLV("ALC Capture Noise Gate Threshold Volume",
ADAU1761_ALC_CTRL3, 0, 31, 0, adau1761_alc_ng_threshold_tlv),
};
static const struct snd_kcontrol_new adau1761_single_mode_controls[] = {
SOC_SINGLE_TLV("Input 1 Capture Volume", ADAU1761_REC_MIXER_LEFT0,
4, 7, 0, adau1761_sing_in_tlv),
SOC_SINGLE_TLV("Input 2 Capture Volume", ADAU1761_REC_MIXER_LEFT0,
1, 7, 0, adau1761_sing_in_tlv),
SOC_SINGLE_TLV("Input 3 Capture Volume", ADAU1761_REC_MIXER_RIGHT0,
4, 7, 0, adau1761_sing_in_tlv),
SOC_SINGLE_TLV("Input 4 Capture Volume", ADAU1761_REC_MIXER_RIGHT0,
1, 7, 0, adau1761_sing_in_tlv),
};
static const struct snd_kcontrol_new adau1761_controls[] = {
SOC_DOUBLE_R_TLV("Aux Capture Volume", ADAU1761_REC_MIXER_LEFT1,
ADAU1761_REC_MIXER_RIGHT1, 0, 7, 0, adau1761_sing_in_tlv),
SOC_DOUBLE_R_TLV("Headphone Playback Volume", ADAU1761_PLAY_HP_LEFT_VOL,
ADAU1761_PLAY_HP_RIGHT_VOL, 2, 0x3f, 0, adau1761_out_tlv),
SOC_DOUBLE_R("Headphone Playback Switch", ADAU1761_PLAY_HP_LEFT_VOL,
ADAU1761_PLAY_HP_RIGHT_VOL, 1, 1, 0),
SOC_DOUBLE_R_TLV("Lineout Playback Volume", ADAU1761_PLAY_LINE_LEFT_VOL,
ADAU1761_PLAY_LINE_RIGHT_VOL, 2, 0x3f, 0, adau1761_out_tlv),
SOC_DOUBLE_R("Lineout Playback Switch", ADAU1761_PLAY_LINE_LEFT_VOL,
ADAU1761_PLAY_LINE_RIGHT_VOL, 1, 1, 0),
SOC_ENUM("ADC Bias", adau1761_adc_bias_enum),
SOC_ENUM("DAC Bias", adau1761_dac_bias_enum),
SOC_ENUM("Capture Bias", adau1761_capture_bias_enum),
SOC_ENUM("Playback Bias", adau1761_playback_bias_enum),
SOC_ENUM("Headphone Bias", adau1761_hp_bias_enum),
};
static const struct snd_kcontrol_new adau1761_mono_controls[] = {
SOC_SINGLE_TLV("Mono Playback Volume", ADAU1761_PLAY_MONO_OUTPUT_VOL,
2, 0x3f, 0, adau1761_out_tlv),
SOC_SINGLE("Mono Playback Switch", ADAU1761_PLAY_MONO_OUTPUT_VOL,
1, 1, 0),
};
static const struct snd_kcontrol_new adau1761_left_mixer_controls[] = {
SOC_DAPM_SINGLE_AUTODISABLE("Left DAC Switch",
ADAU1761_PLAY_MIXER_LEFT0, 5, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("Right DAC Switch",
ADAU1761_PLAY_MIXER_LEFT0, 6, 1, 0),
SOC_DAPM_SINGLE_TLV("Aux Bypass Volume",
ADAU1761_PLAY_MIXER_LEFT0, 1, 8, 0, adau1761_sidetone_tlv),
SOC_DAPM_SINGLE_TLV("Right Bypass Volume",
ADAU1761_PLAY_MIXER_LEFT1, 4, 8, 0, adau1761_sidetone_tlv),
SOC_DAPM_SINGLE_TLV("Left Bypass Volume",
ADAU1761_PLAY_MIXER_LEFT1, 0, 8, 0, adau1761_sidetone_tlv),
};
static const struct snd_kcontrol_new adau1761_right_mixer_controls[] = {
SOC_DAPM_SINGLE_AUTODISABLE("Left DAC Switch",
ADAU1761_PLAY_MIXER_RIGHT0, 5, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("Right DAC Switch",
ADAU1761_PLAY_MIXER_RIGHT0, 6, 1, 0),
SOC_DAPM_SINGLE_TLV("Aux Bypass Volume",
ADAU1761_PLAY_MIXER_RIGHT0, 1, 8, 0, adau1761_sidetone_tlv),
SOC_DAPM_SINGLE_TLV("Right Bypass Volume",
ADAU1761_PLAY_MIXER_RIGHT1, 4, 8, 0, adau1761_sidetone_tlv),
SOC_DAPM_SINGLE_TLV("Left Bypass Volume",
ADAU1761_PLAY_MIXER_RIGHT1, 0, 8, 0, adau1761_sidetone_tlv),
};
static const struct snd_kcontrol_new adau1761_left_lr_mixer_controls[] = {
SOC_DAPM_SINGLE_TLV("Left Volume",
ADAU1761_PLAY_LR_MIXER_LEFT, 1, 2, 0, adau1761_boost_tlv),
SOC_DAPM_SINGLE_TLV("Right Volume",
ADAU1761_PLAY_LR_MIXER_LEFT, 3, 2, 0, adau1761_boost_tlv),
};
static const struct snd_kcontrol_new adau1761_right_lr_mixer_controls[] = {
SOC_DAPM_SINGLE_TLV("Left Volume",
ADAU1761_PLAY_LR_MIXER_RIGHT, 1, 2, 0, adau1761_boost_tlv),
SOC_DAPM_SINGLE_TLV("Right Volume",
ADAU1761_PLAY_LR_MIXER_RIGHT, 3, 2, 0, adau1761_boost_tlv),
};
static const char * const adau1761_input_mux_text[] = {
"ADC", "DMIC",
};
static SOC_ENUM_SINGLE_DECL(adau1761_input_mux_enum,
ADAU17X1_ADC_CONTROL, 2, adau1761_input_mux_text);
static const struct snd_kcontrol_new adau1761_input_mux_control =
SOC_DAPM_ENUM("Input Select", adau1761_input_mux_enum);
static int adau1761_dejitter_fixup(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct adau *adau = snd_soc_component_get_drvdata(component);
/* After any power changes have been made the dejitter circuit
* has to be reinitialized. */
regmap_write(adau->regmap, ADAU1761_DEJITTER, 0);
if (!adau->master)
regmap_write(adau->regmap, ADAU1761_DEJITTER, 3);
return 0;
}
static const struct snd_soc_dapm_widget adau1x61_dapm_widgets[] = {
SND_SOC_DAPM_MIXER("Left Input Mixer", ADAU1761_REC_MIXER_LEFT0, 0, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("Right Input Mixer", ADAU1761_REC_MIXER_RIGHT0, 0, 0,
NULL, 0),
SOC_MIXER_ARRAY("Left Playback Mixer", ADAU1761_PLAY_MIXER_LEFT0,
0, 0, adau1761_left_mixer_controls),
SOC_MIXER_ARRAY("Right Playback Mixer", ADAU1761_PLAY_MIXER_RIGHT0,
0, 0, adau1761_right_mixer_controls),
SOC_MIXER_ARRAY("Left LR Playback Mixer", ADAU1761_PLAY_LR_MIXER_LEFT,
0, 0, adau1761_left_lr_mixer_controls),
SOC_MIXER_ARRAY("Right LR Playback Mixer", ADAU1761_PLAY_LR_MIXER_RIGHT,
0, 0, adau1761_right_lr_mixer_controls),
SND_SOC_DAPM_SUPPLY("Headphone", ADAU1761_PLAY_HP_LEFT_VOL,
0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("SYSCLK", 2, SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_POST("Dejitter fixup", adau1761_dejitter_fixup),
SND_SOC_DAPM_INPUT("LAUX"),
SND_SOC_DAPM_INPUT("RAUX"),
SND_SOC_DAPM_INPUT("LINP"),
SND_SOC_DAPM_INPUT("LINN"),
SND_SOC_DAPM_INPUT("RINP"),
SND_SOC_DAPM_INPUT("RINN"),
SND_SOC_DAPM_OUTPUT("LOUT"),
SND_SOC_DAPM_OUTPUT("ROUT"),
SND_SOC_DAPM_OUTPUT("LHP"),
SND_SOC_DAPM_OUTPUT("RHP"),
};
static const struct snd_soc_dapm_widget adau1761_mono_dapm_widgets[] = {
SND_SOC_DAPM_MIXER("Mono Playback Mixer", ADAU1761_PLAY_MIXER_MONO,
0, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("MONOOUT"),
};
static const struct snd_soc_dapm_widget adau1761_capless_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY_S("Headphone VGND", 1, ADAU1761_PLAY_MIXER_MONO,
0, 0, NULL, 0),
};
static const struct snd_soc_dapm_route adau1x61_dapm_routes[] = {
{ "Left Input Mixer", NULL, "LINP" },
{ "Left Input Mixer", NULL, "LINN" },
{ "Left Input Mixer", NULL, "LAUX" },
{ "Right Input Mixer", NULL, "RINP" },
{ "Right Input Mixer", NULL, "RINN" },
{ "Right Input Mixer", NULL, "RAUX" },
{ "Left Playback Mixer", NULL, "Left Playback Enable"},
{ "Right Playback Mixer", NULL, "Right Playback Enable"},
{ "Left LR Playback Mixer", NULL, "Left Playback Enable"},
{ "Right LR Playback Mixer", NULL, "Right Playback Enable"},
{ "Left Playback Mixer", "Left DAC Switch", "Left DAC" },
{ "Left Playback Mixer", "Right DAC Switch", "Right DAC" },
{ "Right Playback Mixer", "Left DAC Switch", "Left DAC" },
{ "Right Playback Mixer", "Right DAC Switch", "Right DAC" },
{ "Left LR Playback Mixer", "Left Volume", "Left Playback Mixer" },
{ "Left LR Playback Mixer", "Right Volume", "Right Playback Mixer" },
{ "Right LR Playback Mixer", "Left Volume", "Left Playback Mixer" },
{ "Right LR Playback Mixer", "Right Volume", "Right Playback Mixer" },
{ "LHP", NULL, "Left Playback Mixer" },
{ "RHP", NULL, "Right Playback Mixer" },
{ "LHP", NULL, "Headphone" },
{ "RHP", NULL, "Headphone" },
{ "LOUT", NULL, "Left LR Playback Mixer" },
{ "ROUT", NULL, "Right LR Playback Mixer" },
{ "Left Playback Mixer", "Aux Bypass Volume", "LAUX" },
{ "Left Playback Mixer", "Left Bypass Volume", "Left Input Mixer" },
{ "Left Playback Mixer", "Right Bypass Volume", "Right Input Mixer" },
{ "Right Playback Mixer", "Aux Bypass Volume", "RAUX" },
{ "Right Playback Mixer", "Left Bypass Volume", "Left Input Mixer" },
{ "Right Playback Mixer", "Right Bypass Volume", "Right Input Mixer" },
};
static const struct snd_soc_dapm_route adau1761_mono_dapm_routes[] = {
{ "Mono Playback Mixer", NULL, "Left Playback Mixer" },
{ "Mono Playback Mixer", NULL, "Right Playback Mixer" },
{ "MONOOUT", NULL, "Mono Playback Mixer" },
};
static const struct snd_soc_dapm_route adau1761_capless_dapm_routes[] = {
{ "Headphone", NULL, "Headphone VGND" },
};
static const struct snd_soc_dapm_widget adau1761_dmic_widgets[] = {
SND_SOC_DAPM_MUX("Left Decimator Mux", SND_SOC_NOPM, 0, 0,
&adau1761_input_mux_control),
SND_SOC_DAPM_MUX("Right Decimator Mux", SND_SOC_NOPM, 0, 0,
&adau1761_input_mux_control),
SND_SOC_DAPM_INPUT("DMIC"),
};
static const struct snd_soc_dapm_route adau1761_dmic_routes[] = {
{ "Left Decimator Mux", "ADC", "Left Input Mixer" },
{ "Left Decimator Mux", "DMIC", "DMIC" },
{ "Right Decimator Mux", "ADC", "Right Input Mixer" },
{ "Right Decimator Mux", "DMIC", "DMIC" },
{ "Left Decimator", NULL, "Left Decimator Mux" },
{ "Right Decimator", NULL, "Right Decimator Mux" },
};
static const struct snd_soc_dapm_route adau1761_no_dmic_routes[] = {
{ "Left Decimator", NULL, "Left Input Mixer" },
{ "Right Decimator", NULL, "Right Input Mixer" },
};
static const struct snd_soc_dapm_widget adau1761_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("Serial Port Clock", ADAU1761_CLK_ENABLE0,
0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Serial Input Routing Clock", ADAU1761_CLK_ENABLE0,
1, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Serial Output Routing Clock", ADAU1761_CLK_ENABLE0,
3, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Decimator Resync Clock", ADAU1761_CLK_ENABLE0,
4, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Interpolator Resync Clock", ADAU1761_CLK_ENABLE0,
2, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Slew Clock", ADAU1761_CLK_ENABLE0, 6, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ALC Clock", ADAU1761_CLK_ENABLE0, 5, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("Digital Clock 0", 1, ADAU1761_CLK_ENABLE1,
0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("Digital Clock 1", 1, ADAU1761_CLK_ENABLE1,
1, 0, NULL, 0),
};
static const struct snd_soc_dapm_route adau1761_dapm_routes[] = {
{ "Left Decimator", NULL, "Digital Clock 0", },
{ "Right Decimator", NULL, "Digital Clock 0", },
{ "Left DAC", NULL, "Digital Clock 0", },
{ "Right DAC", NULL, "Digital Clock 0", },
{ "AIFCLK", NULL, "Digital Clock 1" },
{ "Playback", NULL, "Serial Port Clock" },
{ "Capture", NULL, "Serial Port Clock" },
{ "Playback", NULL, "Serial Input Routing Clock" },
{ "Capture", NULL, "Serial Output Routing Clock" },
{ "Left Decimator", NULL, "Decimator Resync Clock" },
{ "Right Decimator", NULL, "Decimator Resync Clock" },
{ "Left DAC", NULL, "Interpolator Resync Clock" },
{ "Right DAC", NULL, "Interpolator Resync Clock" },
{ "Slew Clock", NULL, "Digital Clock 0" },
{ "Right Playback Mixer", NULL, "Slew Clock" },
{ "Left Playback Mixer", NULL, "Slew Clock" },
{ "Left Input Mixer", NULL, "ALC Clock" },
{ "Right Input Mixer", NULL, "ALC Clock" },
{ "Digital Clock 0", NULL, "SYSCLK" },
{ "Digital Clock 1", NULL, "SYSCLK" },
};
static const struct snd_soc_dapm_route adau1761_dapm_dsp_routes[] = {
{ "DSP", NULL, "Digital Clock 0" },
};
static int adau1761_compatibility_probe(struct device *dev)
{
struct adau *adau = dev_get_drvdata(dev);
struct regmap *regmap = adau->regmap;
int val, ret = 0;
/* Only consider compatibility mode when ADAU1361 was specified. */
if (adau->type != ADAU1361)
return 0;
regcache_cache_bypass(regmap, true);
/*
* This will enable the core clock and bypass the PLL,
* so that we can access the registers for probing purposes
* (without having to set up the PLL).
*/
regmap_write(regmap, ADAU17X1_CLOCK_CONTROL,
ADAU17X1_CLOCK_CONTROL_SYSCLK_EN);
/*
* ADAU17X1_SERIAL_SAMPLING_RATE doesn't exist in non-DSP chips;
* reading it results in zero at all times, and write is a no-op.
* Use this register to probe for ADAU1761.
*/
regmap_write(regmap, ADAU17X1_SERIAL_SAMPLING_RATE, 1);
ret = regmap_read(regmap, ADAU17X1_SERIAL_SAMPLING_RATE, &val);
if (ret)
goto exit;
if (val != 1)
goto exit;
regmap_write(regmap, ADAU17X1_SERIAL_SAMPLING_RATE, 0);
ret = regmap_read(regmap, ADAU17X1_SERIAL_SAMPLING_RATE, &val);
if (ret)
goto exit;
if (val != 0)
goto exit;
adau->type = ADAU1761_AS_1361;
exit:
/* Disable core clock after probing. */
regmap_write(regmap, ADAU17X1_CLOCK_CONTROL, 0);
regcache_cache_bypass(regmap, false);
return ret;
}
static int adau1761_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct adau *adau = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
regcache_cache_only(adau->regmap, false);
regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL,
ADAU17X1_CLOCK_CONTROL_SYSCLK_EN,
ADAU17X1_CLOCK_CONTROL_SYSCLK_EN);
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
regcache_sync(adau->regmap);
break;
case SND_SOC_BIAS_OFF:
regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL,
ADAU17X1_CLOCK_CONTROL_SYSCLK_EN, 0);
regcache_cache_only(adau->regmap, true);
break;
}
return 0;
}
static enum adau1761_output_mode adau1761_get_lineout_mode(
struct snd_soc_component *component)
{
struct adau1761_platform_data *pdata = component->dev->platform_data;
if (pdata)
return pdata->lineout_mode;
return ADAU1761_OUTPUT_MODE_LINE;
}
static int adau1761_setup_digmic_jackdetect(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct adau1761_platform_data *pdata = component->dev->platform_data;
struct adau *adau = snd_soc_component_get_drvdata(component);
enum adau1761_digmic_jackdet_pin_mode mode;
unsigned int val = 0;
int ret;
if (pdata)
mode = pdata->digmic_jackdetect_pin_mode;
else
mode = ADAU1761_DIGMIC_JACKDET_PIN_MODE_NONE;
switch (mode) {
case ADAU1761_DIGMIC_JACKDET_PIN_MODE_JACKDETECT:
switch (pdata->jackdetect_debounce_time) {
case ADAU1761_JACKDETECT_DEBOUNCE_5MS:
case ADAU1761_JACKDETECT_DEBOUNCE_10MS:
case ADAU1761_JACKDETECT_DEBOUNCE_20MS:
case ADAU1761_JACKDETECT_DEBOUNCE_40MS:
val |= pdata->jackdetect_debounce_time << 6;
break;
default:
return -EINVAL;
}
if (pdata->jackdetect_active_low)
val |= ADAU1761_DIGMIC_JACKDETECT_ACTIVE_LOW;
ret = snd_soc_add_component_controls(component,
adau1761_jack_detect_controls,
ARRAY_SIZE(adau1761_jack_detect_controls));
if (ret)
return ret;
fallthrough;
case ADAU1761_DIGMIC_JACKDET_PIN_MODE_NONE:
ret = snd_soc_dapm_add_routes(dapm, adau1761_no_dmic_routes,
ARRAY_SIZE(adau1761_no_dmic_routes));
if (ret)
return ret;
break;
case ADAU1761_DIGMIC_JACKDET_PIN_MODE_DIGMIC:
ret = snd_soc_dapm_new_controls(dapm, adau1761_dmic_widgets,
ARRAY_SIZE(adau1761_dmic_widgets));
if (ret)
return ret;
ret = snd_soc_dapm_add_routes(dapm, adau1761_dmic_routes,
ARRAY_SIZE(adau1761_dmic_routes));
if (ret)
return ret;
val |= ADAU1761_DIGMIC_JACKDETECT_DIGMIC;
break;
default:
return -EINVAL;
}
regmap_write(adau->regmap, ADAU1761_DIGMIC_JACKDETECT, val);
return 0;
}
static int adau1761_setup_headphone_mode(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct adau *adau = snd_soc_component_get_drvdata(component);
struct adau1761_platform_data *pdata = component->dev->platform_data;
enum adau1761_output_mode mode;
int ret;
if (pdata)
mode = pdata->headphone_mode;
else
mode = ADAU1761_OUTPUT_MODE_HEADPHONE;
switch (mode) {
case ADAU1761_OUTPUT_MODE_LINE:
break;
case ADAU1761_OUTPUT_MODE_HEADPHONE_CAPLESS:
regmap_update_bits(adau->regmap, ADAU1761_PLAY_MONO_OUTPUT_VOL,
ADAU1761_PLAY_MONO_OUTPUT_VOL_MODE_HP |
ADAU1761_PLAY_MONO_OUTPUT_VOL_UNMUTE,
ADAU1761_PLAY_MONO_OUTPUT_VOL_MODE_HP |
ADAU1761_PLAY_MONO_OUTPUT_VOL_UNMUTE);
fallthrough;
case ADAU1761_OUTPUT_MODE_HEADPHONE:
regmap_update_bits(adau->regmap, ADAU1761_PLAY_HP_RIGHT_VOL,
ADAU1761_PLAY_HP_RIGHT_VOL_MODE_HP,
ADAU1761_PLAY_HP_RIGHT_VOL_MODE_HP);
break;
default:
return -EINVAL;
}
if (mode == ADAU1761_OUTPUT_MODE_HEADPHONE_CAPLESS) {
ret = snd_soc_dapm_new_controls(dapm,
adau1761_capless_dapm_widgets,
ARRAY_SIZE(adau1761_capless_dapm_widgets));
if (ret)
return ret;
ret = snd_soc_dapm_add_routes(dapm,
adau1761_capless_dapm_routes,
ARRAY_SIZE(adau1761_capless_dapm_routes));
} else {
ret = snd_soc_add_component_controls(component, adau1761_mono_controls,
ARRAY_SIZE(adau1761_mono_controls));
if (ret)
return ret;
ret = snd_soc_dapm_new_controls(dapm,
adau1761_mono_dapm_widgets,
ARRAY_SIZE(adau1761_mono_dapm_widgets));
if (ret)
return ret;
ret = snd_soc_dapm_add_routes(dapm,
adau1761_mono_dapm_routes,
ARRAY_SIZE(adau1761_mono_dapm_routes));
}
return ret;
}
static bool adau1761_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case ADAU1761_DIGMIC_JACKDETECT:
case ADAU1761_REC_MIXER_LEFT0:
case ADAU1761_REC_MIXER_LEFT1:
case ADAU1761_REC_MIXER_RIGHT0:
case ADAU1761_REC_MIXER_RIGHT1:
case ADAU1761_LEFT_DIFF_INPUT_VOL:
case ADAU1761_RIGHT_DIFF_INPUT_VOL:
case ADAU1761_PLAY_LR_MIXER_LEFT:
case ADAU1761_PLAY_MIXER_LEFT0:
case ADAU1761_PLAY_MIXER_LEFT1:
case ADAU1761_PLAY_MIXER_RIGHT0:
case ADAU1761_PLAY_MIXER_RIGHT1:
case ADAU1761_PLAY_LR_MIXER_RIGHT:
case ADAU1761_PLAY_MIXER_MONO:
case ADAU1761_PLAY_HP_LEFT_VOL:
case ADAU1761_PLAY_HP_RIGHT_VOL:
case ADAU1761_PLAY_LINE_LEFT_VOL:
case ADAU1761_PLAY_LINE_RIGHT_VOL:
case ADAU1761_PLAY_MONO_OUTPUT_VOL:
case ADAU1761_POP_CLICK_SUPPRESS:
case ADAU1761_JACK_DETECT_PIN:
case ADAU1761_DEJITTER:
case ADAU1761_CLK_ENABLE0:
case ADAU1761_CLK_ENABLE1:
case ADAU1761_ALC_CTRL0:
case ADAU1761_ALC_CTRL1:
case ADAU1761_ALC_CTRL2:
case ADAU1761_ALC_CTRL3:
return true;
default:
break;
}
return adau17x1_readable_register(dev, reg);
}
static int adau1761_component_probe(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct adau1761_platform_data *pdata = component->dev->platform_data;
struct adau *adau = snd_soc_component_get_drvdata(component);
int ret;
ret = adau17x1_add_widgets(component);
if (ret < 0)
return ret;
if (pdata && pdata->input_differential) {
regmap_update_bits(adau->regmap, ADAU1761_LEFT_DIFF_INPUT_VOL,
ADAU1761_DIFF_INPUT_VOL_LDEN,
ADAU1761_DIFF_INPUT_VOL_LDEN);
regmap_update_bits(adau->regmap, ADAU1761_RIGHT_DIFF_INPUT_VOL,
ADAU1761_DIFF_INPUT_VOL_LDEN,
ADAU1761_DIFF_INPUT_VOL_LDEN);
ret = snd_soc_add_component_controls(component,
adau1761_differential_mode_controls,
ARRAY_SIZE(adau1761_differential_mode_controls));
if (ret)
return ret;
} else {
ret = snd_soc_add_component_controls(component,
adau1761_single_mode_controls,
ARRAY_SIZE(adau1761_single_mode_controls));
if (ret)
return ret;
}
switch (adau1761_get_lineout_mode(component)) {
case ADAU1761_OUTPUT_MODE_LINE:
break;
case ADAU1761_OUTPUT_MODE_HEADPHONE:
regmap_update_bits(adau->regmap, ADAU1761_PLAY_LINE_LEFT_VOL,
ADAU1761_PLAY_LINE_LEFT_VOL_MODE_HP,
ADAU1761_PLAY_LINE_LEFT_VOL_MODE_HP);
regmap_update_bits(adau->regmap, ADAU1761_PLAY_LINE_RIGHT_VOL,
ADAU1761_PLAY_LINE_RIGHT_VOL_MODE_HP,
ADAU1761_PLAY_LINE_RIGHT_VOL_MODE_HP);
break;
default:
return -EINVAL;
}
ret = adau1761_setup_headphone_mode(component);
if (ret)
return ret;
ret = adau1761_setup_digmic_jackdetect(component);
if (ret)
return ret;
/*
* If we've got an ADAU1761, or an ADAU1761 operating as an
* ADAU1361, we need these non-DSP related DAPM widgets and routes.
*/
if (adau->type == ADAU1761 || adau->type == ADAU1761_AS_1361) {
ret = snd_soc_dapm_new_controls(dapm, adau1761_dapm_widgets,
ARRAY_SIZE(adau1761_dapm_widgets));
if (ret)
return ret;
ret = snd_soc_dapm_add_routes(dapm, adau1761_dapm_routes,
ARRAY_SIZE(adau1761_dapm_routes));
if (ret)
return ret;
}
/*
* These routes are DSP related and only used when we have a
* bona fide ADAU1761.
*/
if (adau->type == ADAU1761) {
ret = snd_soc_dapm_add_routes(dapm, adau1761_dapm_dsp_routes,
ARRAY_SIZE(adau1761_dapm_dsp_routes));
if (ret)
return ret;
}
/*
* In the ADAU1761, by default, the AIF is routed to the DSP, whereas
* for the ADAU1361, the AIF is permanently routed to the ADC and DAC.
* Thus, if we have an ADAU1761 masquerading as an ADAU1361,
* we need to explicitly route the AIF to the ADC and DAC.
* For the ADAU1761, this is normally done by set_tdm_slot, but this
* function is not necessarily called during stream setup, so set up
* the compatible AIF routings here from the start.
*/
if (adau->type == ADAU1761_AS_1361) {
regmap_write(adau->regmap, ADAU17X1_SERIAL_INPUT_ROUTE, 0x01);
regmap_write(adau->regmap, ADAU17X1_SERIAL_OUTPUT_ROUTE, 0x01);
}
ret = adau17x1_add_routes(component);
if (ret < 0)
return ret;
return 0;
}
static const struct snd_soc_component_driver adau1761_component_driver = {
.probe = adau1761_component_probe,
.resume = adau17x1_resume,
.set_bias_level = adau1761_set_bias_level,
.controls = adau1761_controls,
.num_controls = ARRAY_SIZE(adau1761_controls),
.dapm_widgets = adau1x61_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(adau1x61_dapm_widgets),
.dapm_routes = adau1x61_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(adau1x61_dapm_routes),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
#define ADAU1761_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver adau1361_dai_driver = {
.name = "adau-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 4,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = ADAU1761_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 4,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = ADAU1761_FORMATS,
},
.ops = &adau17x1_dai_ops,
};
static struct snd_soc_dai_driver adau1761_dai_driver = {
.name = "adau-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = ADAU1761_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = ADAU1761_FORMATS,
},
.ops = &adau17x1_dai_ops,
};
int adau1761_probe(struct device *dev, struct regmap *regmap,
enum adau17x1_type type, void (*switch_mode)(struct device *dev))
{
struct snd_soc_dai_driver *dai_drv;
const char *firmware_name;
int ret;
if (type == ADAU1361) {
dai_drv = &adau1361_dai_driver;
firmware_name = NULL;
} else {
dai_drv = &adau1761_dai_driver;
firmware_name = ADAU1761_FIRMWARE;
}
ret = adau17x1_probe(dev, regmap, type, switch_mode, firmware_name);
if (ret)
return ret;
ret = adau1761_compatibility_probe(dev);
if (ret)
return ret;
/* Enable cache only mode as we could miss writes before bias level
* reaches standby and the core clock is enabled */
regcache_cache_only(regmap, true);
return devm_snd_soc_register_component(dev, &adau1761_component_driver,
dai_drv, 1);
}
EXPORT_SYMBOL_GPL(adau1761_probe);
const struct regmap_config adau1761_regmap_config = {
.val_bits = 8,
.reg_bits = 16,
.max_register = 0x40fa,
.reg_defaults = adau1761_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(adau1761_reg_defaults),
.readable_reg = adau1761_readable_register,
.volatile_reg = adau17x1_volatile_register,
.precious_reg = adau17x1_precious_register,
.cache_type = REGCACHE_MAPLE,
};
EXPORT_SYMBOL_GPL(adau1761_regmap_config);
MODULE_DESCRIPTION("ASoC ADAU1361/ADAU1461/ADAU1761/ADAU1961 CODEC driver");
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/adau1761.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8994.c -- WM8994 ALSA SoC Audio driver
*
* Copyright 2009-12 Wolfson Microelectronics plc
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/gcd.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/jack.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <trace/events/asoc.h>
#include <linux/mfd/wm8994/core.h>
#include <linux/mfd/wm8994/registers.h>
#include <linux/mfd/wm8994/pdata.h>
#include <linux/mfd/wm8994/gpio.h>
#include "wm8994.h"
#include "wm_hubs.h"
#define WM1811_JACKDET_MODE_NONE 0x0000
#define WM1811_JACKDET_MODE_JACK 0x0100
#define WM1811_JACKDET_MODE_MIC 0x0080
#define WM1811_JACKDET_MODE_AUDIO 0x0180
#define WM8994_NUM_DRC 3
#define WM8994_NUM_EQ 3
struct wm8994_reg_mask {
unsigned int reg;
unsigned int mask;
};
static struct wm8994_reg_mask wm8994_vu_bits[] = {
{ WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
{ WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
{ WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
{ WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
{ WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
{ WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
{ WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
{ WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
{ WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
{ WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
{ WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
{ WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
{ WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
{ WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
{ WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
{ WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
{ WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
{ WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
{ WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
{ WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
{ WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
{ WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
};
/* VU bitfields for ADC2, DAC2 not available on WM1811 */
static struct wm8994_reg_mask wm8994_adc2_dac2_vu_bits[] = {
{ WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
{ WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
{ WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
{ WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
};
static int wm8994_drc_base[] = {
WM8994_AIF1_DRC1_1,
WM8994_AIF1_DRC2_1,
WM8994_AIF2_DRC_1,
};
static int wm8994_retune_mobile_base[] = {
WM8994_AIF1_DAC1_EQ_GAINS_1,
WM8994_AIF1_DAC2_EQ_GAINS_1,
WM8994_AIF2_EQ_GAINS_1,
};
static const struct wm8958_micd_rate micdet_rates[] = {
{ 32768, true, 1, 4 },
{ 32768, false, 1, 1 },
{ 44100 * 256, true, 7, 10 },
{ 44100 * 256, false, 7, 10 },
};
static const struct wm8958_micd_rate jackdet_rates[] = {
{ 32768, true, 0, 1 },
{ 32768, false, 0, 1 },
{ 44100 * 256, true, 10, 10 },
{ 44100 * 256, false, 7, 8 },
};
static void wm8958_micd_set_rate(struct snd_soc_component *component)
{
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
struct wm8994 *control = wm8994->wm8994;
int best, i, sysclk, val;
bool idle;
const struct wm8958_micd_rate *rates;
int num_rates;
idle = !wm8994->jack_mic;
sysclk = snd_soc_component_read(component, WM8994_CLOCKING_1);
if (sysclk & WM8994_SYSCLK_SRC)
sysclk = wm8994->aifclk[1];
else
sysclk = wm8994->aifclk[0];
if (control->pdata.micd_rates) {
rates = control->pdata.micd_rates;
num_rates = control->pdata.num_micd_rates;
} else if (wm8994->jackdet) {
rates = jackdet_rates;
num_rates = ARRAY_SIZE(jackdet_rates);
} else {
rates = micdet_rates;
num_rates = ARRAY_SIZE(micdet_rates);
}
best = 0;
for (i = 0; i < num_rates; i++) {
if (rates[i].idle != idle)
continue;
if (abs(rates[i].sysclk - sysclk) <
abs(rates[best].sysclk - sysclk))
best = i;
else if (rates[best].idle != idle)
best = i;
}
val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
| rates[best].rate << WM8958_MICD_RATE_SHIFT;
dev_dbg(component->dev, "MICD rate %d,%d for %dHz %s\n",
rates[best].start, rates[best].rate, sysclk,
idle ? "idle" : "active");
snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1,
WM8958_MICD_BIAS_STARTTIME_MASK |
WM8958_MICD_RATE_MASK, val);
}
static int configure_aif_clock(struct snd_soc_component *component, int aif)
{
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
int rate;
int reg1 = 0;
int offset;
if (aif)
offset = 4;
else
offset = 0;
switch (wm8994->sysclk[aif]) {
case WM8994_SYSCLK_MCLK1:
rate = wm8994->mclk_rate[0];
break;
case WM8994_SYSCLK_MCLK2:
reg1 |= 0x8;
rate = wm8994->mclk_rate[1];
break;
case WM8994_SYSCLK_FLL1:
reg1 |= 0x10;
rate = wm8994->fll[0].out;
break;
case WM8994_SYSCLK_FLL2:
reg1 |= 0x18;
rate = wm8994->fll[1].out;
break;
default:
return -EINVAL;
}
if (rate >= 13500000) {
rate /= 2;
reg1 |= WM8994_AIF1CLK_DIV;
dev_dbg(component->dev, "Dividing AIF%d clock to %dHz\n",
aif + 1, rate);
}
wm8994->aifclk[aif] = rate;
snd_soc_component_update_bits(component, WM8994_AIF1_CLOCKING_1 + offset,
WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
reg1);
return 0;
}
static int configure_clock(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
int change, new;
/* Bring up the AIF clocks first */
configure_aif_clock(component, 0);
configure_aif_clock(component, 1);
/* Then switch CLK_SYS over to the higher of them; a change
* can only happen as a result of a clocking change which can
* only be made outside of DAPM so we can safely redo the
* clocking.
*/
/* If they're equal it doesn't matter which is used */
if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
wm8958_micd_set_rate(component);
return 0;
}
if (wm8994->aifclk[0] < wm8994->aifclk[1])
new = WM8994_SYSCLK_SRC;
else
new = 0;
change = snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
WM8994_SYSCLK_SRC, new);
if (change)
snd_soc_dapm_sync(dapm);
wm8958_micd_set_rate(component);
return 0;
}
static int check_clk_sys(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
int reg = snd_soc_component_read(component, WM8994_CLOCKING_1);
const char *clk;
/* Check what we're currently using for CLK_SYS */
if (reg & WM8994_SYSCLK_SRC)
clk = "AIF2CLK";
else
clk = "AIF1CLK";
return strcmp(source->name, clk) == 0;
}
static const char *sidetone_hpf_text[] = {
"2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
};
static SOC_ENUM_SINGLE_DECL(sidetone_hpf,
WM8994_SIDETONE, 7, sidetone_hpf_text);
static const char *adc_hpf_text[] = {
"HiFi", "Voice 1", "Voice 2", "Voice 3"
};
static SOC_ENUM_SINGLE_DECL(aif1adc1_hpf,
WM8994_AIF1_ADC1_FILTERS, 13, adc_hpf_text);
static SOC_ENUM_SINGLE_DECL(aif1adc2_hpf,
WM8994_AIF1_ADC2_FILTERS, 13, adc_hpf_text);
static SOC_ENUM_SINGLE_DECL(aif2adc_hpf,
WM8994_AIF2_ADC_FILTERS, 13, adc_hpf_text);
static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
#define WM8994_DRC_SWITCH(xname, reg, shift) \
SOC_SINGLE_EXT(xname, reg, shift, 1, 0, \
snd_soc_get_volsw, wm8994_put_drc_sw)
static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
int mask, ret;
/* Can't enable both ADC and DAC paths simultaneously */
if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
WM8994_AIF1ADC1R_DRC_ENA_MASK;
else
mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
ret = snd_soc_component_read(component, mc->reg);
if (ret < 0)
return ret;
if (ret & mask)
return -EINVAL;
return snd_soc_put_volsw(kcontrol, ucontrol);
}
static void wm8994_set_drc(struct snd_soc_component *component, int drc)
{
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
struct wm8994 *control = wm8994->wm8994;
struct wm8994_pdata *pdata = &control->pdata;
int base = wm8994_drc_base[drc];
int cfg = wm8994->drc_cfg[drc];
int save, i;
/* Save any enables; the configuration should clear them. */
save = snd_soc_component_read(component, base);
save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
WM8994_AIF1ADC1R_DRC_ENA;
for (i = 0; i < WM8994_DRC_REGS; i++)
snd_soc_component_update_bits(component, base + i, 0xffff,
pdata->drc_cfgs[cfg].regs[i]);
snd_soc_component_update_bits(component, base, WM8994_AIF1DAC1_DRC_ENA |
WM8994_AIF1ADC1L_DRC_ENA |
WM8994_AIF1ADC1R_DRC_ENA, save);
}
/* Icky as hell but saves code duplication */
static int wm8994_get_drc(const char *name)
{
if (strcmp(name, "AIF1DRC1 Mode") == 0)
return 0;
if (strcmp(name, "AIF1DRC2 Mode") == 0)
return 1;
if (strcmp(name, "AIF2DRC Mode") == 0)
return 2;
return -EINVAL;
}
static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
struct wm8994 *control = wm8994->wm8994;
struct wm8994_pdata *pdata = &control->pdata;
int drc = wm8994_get_drc(kcontrol->id.name);
int value = ucontrol->value.enumerated.item[0];
if (drc < 0)
return drc;
if (value >= pdata->num_drc_cfgs)
return -EINVAL;
wm8994->drc_cfg[drc] = value;
wm8994_set_drc(component, drc);
return 0;
}
static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
int drc = wm8994_get_drc(kcontrol->id.name);
if (drc < 0)
return drc;
ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
return 0;
}
static void wm8994_set_retune_mobile(struct snd_soc_component *component, int block)
{
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
struct wm8994 *control = wm8994->wm8994;
struct wm8994_pdata *pdata = &control->pdata;
int base = wm8994_retune_mobile_base[block];
int iface, best, best_val, save, i, cfg;
if (!pdata || !wm8994->num_retune_mobile_texts)
return;
switch (block) {
case 0:
case 1:
iface = 0;
break;
case 2:
iface = 1;
break;
default:
return;
}
/* Find the version of the currently selected configuration
* with the nearest sample rate. */
cfg = wm8994->retune_mobile_cfg[block];
best = 0;
best_val = INT_MAX;
for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
if (strcmp(pdata->retune_mobile_cfgs[i].name,
wm8994->retune_mobile_texts[cfg]) == 0 &&
abs(pdata->retune_mobile_cfgs[i].rate
- wm8994->dac_rates[iface]) < best_val) {
best = i;
best_val = abs(pdata->retune_mobile_cfgs[i].rate
- wm8994->dac_rates[iface]);
}
}
dev_dbg(component->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
block,
pdata->retune_mobile_cfgs[best].name,
pdata->retune_mobile_cfgs[best].rate,
wm8994->dac_rates[iface]);
/* The EQ will be disabled while reconfiguring it, remember the
* current configuration.
*/
save = snd_soc_component_read(component, base);
save &= WM8994_AIF1DAC1_EQ_ENA;
for (i = 0; i < WM8994_EQ_REGS; i++)
snd_soc_component_update_bits(component, base + i, 0xffff,
pdata->retune_mobile_cfgs[best].regs[i]);
snd_soc_component_update_bits(component, base, WM8994_AIF1DAC1_EQ_ENA, save);
}
/* Icky as hell but saves code duplication */
static int wm8994_get_retune_mobile_block(const char *name)
{
if (strcmp(name, "AIF1.1 EQ Mode") == 0)
return 0;
if (strcmp(name, "AIF1.2 EQ Mode") == 0)
return 1;
if (strcmp(name, "AIF2 EQ Mode") == 0)
return 2;
return -EINVAL;
}
static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
struct wm8994 *control = wm8994->wm8994;
struct wm8994_pdata *pdata = &control->pdata;
int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
int value = ucontrol->value.enumerated.item[0];
if (block < 0)
return block;
if (value >= pdata->num_retune_mobile_cfgs)
return -EINVAL;
wm8994->retune_mobile_cfg[block] = value;
wm8994_set_retune_mobile(component, block);
return 0;
}
static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
if (block < 0)
return block;
ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
return 0;
}
static const char *aif_chan_src_text[] = {
"Left", "Right"
};
static SOC_ENUM_SINGLE_DECL(aif1adcl_src,
WM8994_AIF1_CONTROL_1, 15, aif_chan_src_text);
static SOC_ENUM_SINGLE_DECL(aif1adcr_src,
WM8994_AIF1_CONTROL_1, 14, aif_chan_src_text);
static SOC_ENUM_SINGLE_DECL(aif2adcl_src,
WM8994_AIF2_CONTROL_1, 15, aif_chan_src_text);
static SOC_ENUM_SINGLE_DECL(aif2adcr_src,
WM8994_AIF2_CONTROL_1, 14, aif_chan_src_text);
static SOC_ENUM_SINGLE_DECL(aif1dacl_src,
WM8994_AIF1_CONTROL_2, 15, aif_chan_src_text);
static SOC_ENUM_SINGLE_DECL(aif1dacr_src,
WM8994_AIF1_CONTROL_2, 14, aif_chan_src_text);
static SOC_ENUM_SINGLE_DECL(aif2dacl_src,
WM8994_AIF2_CONTROL_2, 15, aif_chan_src_text);
static SOC_ENUM_SINGLE_DECL(aif2dacr_src,
WM8994_AIF2_CONTROL_2, 14, aif_chan_src_text);
static const char *osr_text[] = {
"Low Power", "High Performance",
};
static SOC_ENUM_SINGLE_DECL(dac_osr,
WM8994_OVERSAMPLING, 0, osr_text);
static SOC_ENUM_SINGLE_DECL(adc_osr,
WM8994_OVERSAMPLING, 1, osr_text);
static const struct snd_kcontrol_new wm8994_common_snd_controls[] = {
SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
WM8994_AIF1_ADC1_RIGHT_VOLUME,
1, 119, 0, digital_tlv),
SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
WM8994_AIF2_ADC_RIGHT_VOLUME,
1, 119, 0, digital_tlv),
SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
SOC_ENUM("AIF1DACL Source", aif1dacl_src),
SOC_ENUM("AIF1DACR Source", aif1dacr_src),
SOC_ENUM("AIF2DACL Source", aif2dacl_src),
SOC_ENUM("AIF2DACR Source", aif2dacr_src),
SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
5, 12, 0, st_tlv),
SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
0, 12, 0, st_tlv),
SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
5, 12, 0, st_tlv),
SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
0, 12, 0, st_tlv),
SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
SOC_ENUM("ADC OSR", adc_osr),
SOC_ENUM("DAC OSR", dac_osr),
SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
6, 1, 1, wm_hubs_spkmix_tlv),
SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
2, 1, 1, wm_hubs_spkmix_tlv),
SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
6, 1, 1, wm_hubs_spkmix_tlv),
SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
2, 1, 1, wm_hubs_spkmix_tlv),
SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
10, 15, 0, wm8994_3d_tlv),
SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
8, 1, 0),
SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
10, 15, 0, wm8994_3d_tlv),
SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
8, 1, 0),
SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
10, 15, 0, wm8994_3d_tlv),
SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
8, 1, 0),
};
/* Controls not available on WM1811 */
static const struct snd_kcontrol_new wm8994_snd_controls[] = {
SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
WM8994_AIF1_ADC2_RIGHT_VOLUME,
1, 119, 0, digital_tlv),
SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
};
static const struct snd_kcontrol_new wm8994_eq_controls[] = {
SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
eq_tlv),
SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
eq_tlv),
SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
eq_tlv),
SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
eq_tlv),
SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
eq_tlv),
SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
eq_tlv),
SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
eq_tlv),
SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
eq_tlv),
SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
eq_tlv),
SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
eq_tlv),
SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
eq_tlv),
SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
eq_tlv),
SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
eq_tlv),
SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
eq_tlv),
SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
eq_tlv),
};
static const struct snd_kcontrol_new wm8994_drc_controls[] = {
SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5,
WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
WM8994_AIF1ADC1R_DRC_ENA),
SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5,
WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA |
WM8994_AIF1ADC2R_DRC_ENA),
SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5,
WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA |
WM8994_AIF2ADCR_DRC_ENA),
};
static const char *wm8958_ng_text[] = {
"30ms", "125ms", "250ms", "500ms",
};
static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac1_ng_hold,
WM8958_AIF1_DAC1_NOISE_GATE,
WM8958_AIF1DAC1_NG_THR_SHIFT,
wm8958_ng_text);
static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac2_ng_hold,
WM8958_AIF1_DAC2_NOISE_GATE,
WM8958_AIF1DAC2_NG_THR_SHIFT,
wm8958_ng_text);
static SOC_ENUM_SINGLE_DECL(wm8958_aif2dac_ng_hold,
WM8958_AIF2_DAC_NOISE_GATE,
WM8958_AIF2DAC_NG_THR_SHIFT,
wm8958_ng_text);
static const struct snd_kcontrol_new wm8958_snd_controls[] = {
SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
7, 1, ng_tlv),
SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
7, 1, ng_tlv),
SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
7, 1, ng_tlv),
};
/* We run all mode setting through a function to enforce audio mode */
static void wm1811_jackdet_set_mode(struct snd_soc_component *component, u16 mode)
{
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
if (!wm8994->jackdet || !wm8994->micdet[0].jack)
return;
if (wm8994->active_refcount)
mode = WM1811_JACKDET_MODE_AUDIO;
if (mode == wm8994->jackdet_mode)
return;
wm8994->jackdet_mode = mode;
/* Always use audio mode to detect while the system is active */
if (mode != WM1811_JACKDET_MODE_NONE)
mode = WM1811_JACKDET_MODE_AUDIO;
snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
WM1811_JACKDET_MODE_MASK, mode);
}
static void active_reference(struct snd_soc_component *component)
{
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
mutex_lock(&wm8994->accdet_lock);
wm8994->active_refcount++;
dev_dbg(component->dev, "Active refcount incremented, now %d\n",
wm8994->active_refcount);
/* If we're using jack detection go into audio mode */
wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_AUDIO);
mutex_unlock(&wm8994->accdet_lock);
}
static void active_dereference(struct snd_soc_component *component)
{
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
u16 mode;
mutex_lock(&wm8994->accdet_lock);
wm8994->active_refcount--;
dev_dbg(component->dev, "Active refcount decremented, now %d\n",
wm8994->active_refcount);
if (wm8994->active_refcount == 0) {
/* Go into appropriate detection only mode */
if (wm8994->jack_mic || wm8994->mic_detecting)
mode = WM1811_JACKDET_MODE_MIC;
else
mode = WM1811_JACKDET_MODE_JACK;
wm1811_jackdet_set_mode(component, mode);
}
mutex_unlock(&wm8994->accdet_lock);
}
static int clk_sys_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
return configure_clock(component);
case SND_SOC_DAPM_POST_PMU:
/*
* JACKDET won't run until we start the clock and it
* only reports deltas, make sure we notify the state
* up the stack on startup. Use a *very* generous
* timeout for paranoia, there's no urgency and we
* don't want false reports.
*/
if (wm8994->jackdet && !wm8994->clk_has_run) {
queue_delayed_work(system_power_efficient_wq,
&wm8994->jackdet_bootstrap,
msecs_to_jiffies(1000));
wm8994->clk_has_run = true;
}
break;
case SND_SOC_DAPM_POST_PMD:
configure_clock(component);
break;
}
return 0;
}
static void vmid_reference(struct snd_soc_component *component)
{
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
pm_runtime_get_sync(component->dev);
wm8994->vmid_refcount++;
dev_dbg(component->dev, "Referencing VMID, refcount is now %d\n",
wm8994->vmid_refcount);
if (wm8994->vmid_refcount == 1) {
snd_soc_component_update_bits(component, WM8994_ANTIPOP_1,
WM8994_LINEOUT1_DISCH |
WM8994_LINEOUT2_DISCH, 0);
wm_hubs_vmid_ena(component);
switch (wm8994->vmid_mode) {
default:
WARN_ON(NULL == "Invalid VMID mode");
fallthrough;
case WM8994_VMID_NORMAL:
/* Startup bias, VMID ramp & buffer */
snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
WM8994_BIAS_SRC |
WM8994_VMID_DISCH |
WM8994_STARTUP_BIAS_ENA |
WM8994_VMID_BUF_ENA |
WM8994_VMID_RAMP_MASK,
WM8994_BIAS_SRC |
WM8994_STARTUP_BIAS_ENA |
WM8994_VMID_BUF_ENA |
(0x2 << WM8994_VMID_RAMP_SHIFT));
/* Main bias enable, VMID=2x40k */
snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1,
WM8994_BIAS_ENA |
WM8994_VMID_SEL_MASK,
WM8994_BIAS_ENA | 0x2);
msleep(300);
snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
WM8994_VMID_RAMP_MASK |
WM8994_BIAS_SRC,
0);
break;
case WM8994_VMID_FORCE:
/* Startup bias, slow VMID ramp & buffer */
snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
WM8994_BIAS_SRC |
WM8994_VMID_DISCH |
WM8994_STARTUP_BIAS_ENA |
WM8994_VMID_BUF_ENA |
WM8994_VMID_RAMP_MASK,
WM8994_BIAS_SRC |
WM8994_STARTUP_BIAS_ENA |
WM8994_VMID_BUF_ENA |
(0x2 << WM8994_VMID_RAMP_SHIFT));
/* Main bias enable, VMID=2x40k */
snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1,
WM8994_BIAS_ENA |
WM8994_VMID_SEL_MASK,
WM8994_BIAS_ENA | 0x2);
msleep(400);
snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
WM8994_VMID_RAMP_MASK |
WM8994_BIAS_SRC,
0);
break;
}
}
}
static void vmid_dereference(struct snd_soc_component *component)
{
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
wm8994->vmid_refcount--;
dev_dbg(component->dev, "Dereferencing VMID, refcount is now %d\n",
wm8994->vmid_refcount);
if (wm8994->vmid_refcount == 0) {
if (wm8994->hubs.lineout1_se)
snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_3,
WM8994_LINEOUT1N_ENA |
WM8994_LINEOUT1P_ENA,
WM8994_LINEOUT1N_ENA |
WM8994_LINEOUT1P_ENA);
if (wm8994->hubs.lineout2_se)
snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_3,
WM8994_LINEOUT2N_ENA |
WM8994_LINEOUT2P_ENA,
WM8994_LINEOUT2N_ENA |
WM8994_LINEOUT2P_ENA);
/* Start discharging VMID */
snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
WM8994_BIAS_SRC |
WM8994_VMID_DISCH,
WM8994_BIAS_SRC |
WM8994_VMID_DISCH);
snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1,
WM8994_VMID_SEL_MASK, 0);
msleep(400);
/* Active discharge */
snd_soc_component_update_bits(component, WM8994_ANTIPOP_1,
WM8994_LINEOUT1_DISCH |
WM8994_LINEOUT2_DISCH,
WM8994_LINEOUT1_DISCH |
WM8994_LINEOUT2_DISCH);
snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_3,
WM8994_LINEOUT1N_ENA |
WM8994_LINEOUT1P_ENA |
WM8994_LINEOUT2N_ENA |
WM8994_LINEOUT2P_ENA, 0);
/* Switch off startup biases */
snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
WM8994_BIAS_SRC |
WM8994_STARTUP_BIAS_ENA |
WM8994_VMID_BUF_ENA |
WM8994_VMID_RAMP_MASK, 0);
snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1,
WM8994_VMID_SEL_MASK, 0);
}
pm_runtime_put(component->dev);
}
static int vmid_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
vmid_reference(component);
break;
case SND_SOC_DAPM_POST_PMD:
vmid_dereference(component);
break;
}
return 0;
}
static bool wm8994_check_class_w_digital(struct snd_soc_component *component)
{
int source = 0; /* GCC flow analysis can't track enable */
int reg, reg_r;
/* We also need the same AIF source for L/R and only one path */
reg = snd_soc_component_read(component, WM8994_DAC1_LEFT_MIXER_ROUTING);
switch (reg) {
case WM8994_AIF2DACL_TO_DAC1L:
dev_vdbg(component->dev, "Class W source AIF2DAC\n");
source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
break;
case WM8994_AIF1DAC2L_TO_DAC1L:
dev_vdbg(component->dev, "Class W source AIF1DAC2\n");
source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
break;
case WM8994_AIF1DAC1L_TO_DAC1L:
dev_vdbg(component->dev, "Class W source AIF1DAC1\n");
source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
break;
default:
dev_vdbg(component->dev, "DAC mixer setting: %x\n", reg);
return false;
}
reg_r = snd_soc_component_read(component, WM8994_DAC1_RIGHT_MIXER_ROUTING);
if (reg_r != reg) {
dev_vdbg(component->dev, "Left and right DAC mixers different\n");
return false;
}
/* Set the source up */
snd_soc_component_update_bits(component, WM8994_CLASS_W_1,
WM8994_CP_DYN_SRC_SEL_MASK, source);
return true;
}
static void wm8994_update_vu_bits(struct snd_soc_component *component)
{
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
struct wm8994 *control = wm8994->wm8994;
int i;
for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
snd_soc_component_write(component, wm8994_vu_bits[i].reg,
snd_soc_component_read(component,
wm8994_vu_bits[i].reg));
if (control->type == WM1811)
return;
for (i = 0; i < ARRAY_SIZE(wm8994_adc2_dac2_vu_bits); i++)
snd_soc_component_write(component,
wm8994_adc2_dac2_vu_bits[i].reg,
snd_soc_component_read(component,
wm8994_adc2_dac2_vu_bits[i].reg));
}
static int aif_mclk_set(struct snd_soc_component *component, int aif, bool enable)
{
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
unsigned int offset, val, clk_idx;
int ret;
if (aif)
offset = 4;
else
offset = 0;
val = snd_soc_component_read(component, WM8994_AIF1_CLOCKING_1 + offset);
val &= WM8994_AIF1CLK_SRC_MASK;
switch (val) {
case 0:
clk_idx = WM8994_MCLK1;
break;
case 1:
clk_idx = WM8994_MCLK2;
break;
default:
return 0;
}
if (enable) {
ret = clk_prepare_enable(wm8994->mclk[clk_idx].clk);
if (ret < 0) {
dev_err(component->dev, "Failed to enable MCLK%d\n",
clk_idx);
return ret;
}
} else {
clk_disable_unprepare(wm8994->mclk[clk_idx].clk);
}
return 0;
}
static int aif1clk_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
struct wm8994 *control = wm8994->wm8994;
int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
int ret;
int dac;
int adc;
int val;
switch (control->type) {
case WM8994:
case WM8958:
mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
break;
default:
break;
}
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
ret = aif_mclk_set(component, 0, true);
if (ret < 0)
return ret;
/* Don't enable timeslot 2 if not in use */
if (wm8994->channels[0] <= 2)
mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
val = snd_soc_component_read(component, WM8994_AIF1_CONTROL_1);
if ((val & WM8994_AIF1ADCL_SRC) &&
(val & WM8994_AIF1ADCR_SRC))
adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
else if (!(val & WM8994_AIF1ADCL_SRC) &&
!(val & WM8994_AIF1ADCR_SRC))
adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
else
adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
val = snd_soc_component_read(component, WM8994_AIF1_CONTROL_2);
if ((val & WM8994_AIF1DACL_SRC) &&
(val & WM8994_AIF1DACR_SRC))
dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
else if (!(val & WM8994_AIF1DACL_SRC) &&
!(val & WM8994_AIF1DACR_SRC))
dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
else
dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4,
mask, adc);
snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
mask, dac);
snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
WM8994_AIF1DSPCLK_ENA |
WM8994_SYSDSPCLK_ENA,
WM8994_AIF1DSPCLK_ENA |
WM8994_SYSDSPCLK_ENA);
snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4, mask,
WM8994_AIF1ADC1R_ENA |
WM8994_AIF1ADC1L_ENA |
WM8994_AIF1ADC2R_ENA |
WM8994_AIF1ADC2L_ENA);
snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5, mask,
WM8994_AIF1DAC1R_ENA |
WM8994_AIF1DAC1L_ENA |
WM8994_AIF1DAC2R_ENA |
WM8994_AIF1DAC2L_ENA);
break;
case SND_SOC_DAPM_POST_PMU:
wm8994_update_vu_bits(component);
break;
case SND_SOC_DAPM_PRE_PMD:
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
mask, 0);
snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4,
mask, 0);
val = snd_soc_component_read(component, WM8994_CLOCKING_1);
if (val & WM8994_AIF2DSPCLK_ENA)
val = WM8994_SYSDSPCLK_ENA;
else
val = 0;
snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
WM8994_SYSDSPCLK_ENA |
WM8994_AIF1DSPCLK_ENA, val);
break;
}
switch (event) {
case SND_SOC_DAPM_POST_PMD:
aif_mclk_set(component, 0, false);
break;
}
return 0;
}
static int aif2clk_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
int ret;
int dac;
int adc;
int val;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
ret = aif_mclk_set(component, 1, true);
if (ret < 0)
return ret;
val = snd_soc_component_read(component, WM8994_AIF2_CONTROL_1);
if ((val & WM8994_AIF2ADCL_SRC) &&
(val & WM8994_AIF2ADCR_SRC))
adc = WM8994_AIF2ADCR_ENA;
else if (!(val & WM8994_AIF2ADCL_SRC) &&
!(val & WM8994_AIF2ADCR_SRC))
adc = WM8994_AIF2ADCL_ENA;
else
adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
val = snd_soc_component_read(component, WM8994_AIF2_CONTROL_2);
if ((val & WM8994_AIF2DACL_SRC) &&
(val & WM8994_AIF2DACR_SRC))
dac = WM8994_AIF2DACR_ENA;
else if (!(val & WM8994_AIF2DACL_SRC) &&
!(val & WM8994_AIF2DACR_SRC))
dac = WM8994_AIF2DACL_ENA;
else
dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4,
WM8994_AIF2ADCL_ENA |
WM8994_AIF2ADCR_ENA, adc);
snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
WM8994_AIF2DACL_ENA |
WM8994_AIF2DACR_ENA, dac);
snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
WM8994_AIF2DSPCLK_ENA |
WM8994_SYSDSPCLK_ENA,
WM8994_AIF2DSPCLK_ENA |
WM8994_SYSDSPCLK_ENA);
snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4,
WM8994_AIF2ADCL_ENA |
WM8994_AIF2ADCR_ENA,
WM8994_AIF2ADCL_ENA |
WM8994_AIF2ADCR_ENA);
snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
WM8994_AIF2DACL_ENA |
WM8994_AIF2DACR_ENA,
WM8994_AIF2DACL_ENA |
WM8994_AIF2DACR_ENA);
break;
case SND_SOC_DAPM_POST_PMU:
wm8994_update_vu_bits(component);
break;
case SND_SOC_DAPM_PRE_PMD:
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
WM8994_AIF2DACL_ENA |
WM8994_AIF2DACR_ENA, 0);
snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4,
WM8994_AIF2ADCL_ENA |
WM8994_AIF2ADCR_ENA, 0);
val = snd_soc_component_read(component, WM8994_CLOCKING_1);
if (val & WM8994_AIF1DSPCLK_ENA)
val = WM8994_SYSDSPCLK_ENA;
else
val = 0;
snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
WM8994_SYSDSPCLK_ENA |
WM8994_AIF2DSPCLK_ENA, val);
break;
}
switch (event) {
case SND_SOC_DAPM_POST_PMD:
aif_mclk_set(component, 1, false);
break;
}
return 0;
}
static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
wm8994->aif1clk_enable = 1;
break;
case SND_SOC_DAPM_POST_PMD:
wm8994->aif1clk_disable = 1;
break;
}
return 0;
}
static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
wm8994->aif2clk_enable = 1;
break;
case SND_SOC_DAPM_POST_PMD:
wm8994->aif2clk_disable = 1;
break;
}
return 0;
}
static int late_enable_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
if (wm8994->aif1clk_enable) {
aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
snd_soc_component_update_bits(component, WM8994_AIF1_CLOCKING_1,
WM8994_AIF1CLK_ENA_MASK,
WM8994_AIF1CLK_ENA);
aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
wm8994->aif1clk_enable = 0;
}
if (wm8994->aif2clk_enable) {
aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
snd_soc_component_update_bits(component, WM8994_AIF2_CLOCKING_1,
WM8994_AIF2CLK_ENA_MASK,
WM8994_AIF2CLK_ENA);
aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
wm8994->aif2clk_enable = 0;
}
break;
}
/* We may also have postponed startup of DSP, handle that. */
wm8958_aif_ev(w, kcontrol, event);
return 0;
}
static int late_disable_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMD:
if (wm8994->aif1clk_disable) {
aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
snd_soc_component_update_bits(component, WM8994_AIF1_CLOCKING_1,
WM8994_AIF1CLK_ENA_MASK, 0);
aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
wm8994->aif1clk_disable = 0;
}
if (wm8994->aif2clk_disable) {
aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
snd_soc_component_update_bits(component, WM8994_AIF2_CLOCKING_1,
WM8994_AIF2CLK_ENA_MASK, 0);
aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
wm8994->aif2clk_disable = 0;
}
break;
}
return 0;
}
static int adc_mux_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
late_enable_ev(w, kcontrol, event);
return 0;
}
static int micbias_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
late_enable_ev(w, kcontrol, event);
return 0;
}
static int dac_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
unsigned int mask = 1 << w->shift;
snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
mask, mask);
return 0;
}
static const char *adc_mux_text[] = {
"ADC",
"DMIC",
};
static SOC_ENUM_SINGLE_VIRT_DECL(adc_enum, adc_mux_text);
static const struct snd_kcontrol_new adcl_mux =
SOC_DAPM_ENUM("ADCL Mux", adc_enum);
static const struct snd_kcontrol_new adcr_mux =
SOC_DAPM_ENUM("ADCR Mux", adc_enum);
static const struct snd_kcontrol_new left_speaker_mixer[] = {
SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
};
static const struct snd_kcontrol_new right_speaker_mixer[] = {
SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
};
/* Debugging; dump chip status after DAPM transitions */
static int post_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
dev_dbg(component->dev, "SRC status: %x\n",
snd_soc_component_read(component,
WM8994_RATE_STATUS));
return 0;
}
static const struct snd_kcontrol_new aif1adc1l_mix[] = {
SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1, 1, 0),
SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
0, 1, 0),
};
static const struct snd_kcontrol_new aif1adc1r_mix[] = {
SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1, 1, 0),
SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
0, 1, 0),
};
static const struct snd_kcontrol_new aif1adc2l_mix[] = {
SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1, 1, 0),
SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
0, 1, 0),
};
static const struct snd_kcontrol_new aif1adc2r_mix[] = {
SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1, 1, 0),
SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
0, 1, 0),
};
static const struct snd_kcontrol_new aif2dac2l_mix[] = {
SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
5, 1, 0),
SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
4, 1, 0),
SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
2, 1, 0),
SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1, 1, 0),
SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
0, 1, 0),
};
static const struct snd_kcontrol_new aif2dac2r_mix[] = {
SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
5, 1, 0),
SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
4, 1, 0),
SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
2, 1, 0),
SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1, 1, 0),
SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
0, 1, 0),
};
#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
SOC_SINGLE_EXT(xname, reg, shift, max, invert, \
snd_soc_dapm_get_volsw, wm8994_put_class_w)
static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
int ret;
ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
wm_hubs_update_class_w(component);
return ret;
}
static const struct snd_kcontrol_new dac1l_mix[] = {
WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
5, 1, 0),
WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
4, 1, 0),
WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
2, 1, 0),
WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1, 1, 0),
WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
0, 1, 0),
};
static const struct snd_kcontrol_new dac1r_mix[] = {
WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
5, 1, 0),
WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
4, 1, 0),
WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
2, 1, 0),
WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1, 1, 0),
WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
0, 1, 0),
};
static const char *sidetone_text[] = {
"ADC/DMIC1", "DMIC2",
};
static SOC_ENUM_SINGLE_DECL(sidetone1_enum,
WM8994_SIDETONE, 0, sidetone_text);
static const struct snd_kcontrol_new sidetone1_mux =
SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
static SOC_ENUM_SINGLE_DECL(sidetone2_enum,
WM8994_SIDETONE, 1, sidetone_text);
static const struct snd_kcontrol_new sidetone2_mux =
SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
static const char *aif1dac_text[] = {
"AIF1DACDAT", "AIF3DACDAT",
};
static const char *loopback_text[] = {
"None", "ADCDAT",
};
static SOC_ENUM_SINGLE_DECL(aif1_loopback_enum,
WM8994_AIF1_CONTROL_2,
WM8994_AIF1_LOOPBACK_SHIFT,
loopback_text);
static const struct snd_kcontrol_new aif1_loopback =
SOC_DAPM_ENUM("AIF1 Loopback", aif1_loopback_enum);
static SOC_ENUM_SINGLE_DECL(aif2_loopback_enum,
WM8994_AIF2_CONTROL_2,
WM8994_AIF2_LOOPBACK_SHIFT,
loopback_text);
static const struct snd_kcontrol_new aif2_loopback =
SOC_DAPM_ENUM("AIF2 Loopback", aif2_loopback_enum);
static SOC_ENUM_SINGLE_DECL(aif1dac_enum,
WM8994_POWER_MANAGEMENT_6, 0, aif1dac_text);
static const struct snd_kcontrol_new aif1dac_mux =
SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
static const char *aif2dac_text[] = {
"AIF2DACDAT", "AIF3DACDAT",
};
static SOC_ENUM_SINGLE_DECL(aif2dac_enum,
WM8994_POWER_MANAGEMENT_6, 1, aif2dac_text);
static const struct snd_kcontrol_new aif2dac_mux =
SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
static const char *aif2adc_text[] = {
"AIF2ADCDAT", "AIF3DACDAT",
};
static SOC_ENUM_SINGLE_DECL(aif2adc_enum,
WM8994_POWER_MANAGEMENT_6, 2, aif2adc_text);
static const struct snd_kcontrol_new aif2adc_mux =
SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
static const char *aif3adc_text[] = {
"AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
};
static SOC_ENUM_SINGLE_DECL(wm8994_aif3adc_enum,
WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text);
static const struct snd_kcontrol_new wm8994_aif3adc_mux =
SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
static SOC_ENUM_SINGLE_DECL(wm8958_aif3adc_enum,
WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text);
static const struct snd_kcontrol_new wm8958_aif3adc_mux =
SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
static const char *mono_pcm_out_text[] = {
"None", "AIF2ADCL", "AIF2ADCR",
};
static SOC_ENUM_SINGLE_DECL(mono_pcm_out_enum,
WM8994_POWER_MANAGEMENT_6, 9, mono_pcm_out_text);
static const struct snd_kcontrol_new mono_pcm_out_mux =
SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
static const char *aif2dac_src_text[] = {
"AIF2", "AIF3",
};
/* Note that these two control shouldn't be simultaneously switched to AIF3 */
static SOC_ENUM_SINGLE_DECL(aif2dacl_src_enum,
WM8994_POWER_MANAGEMENT_6, 7, aif2dac_src_text);
static const struct snd_kcontrol_new aif2dacl_src_mux =
SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
static SOC_ENUM_SINGLE_DECL(aif2dacr_src_enum,
WM8994_POWER_MANAGEMENT_6, 8, aif2dac_src_text);
static const struct snd_kcontrol_new aif2dacr_src_mux =
SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
late_enable_ev, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
late_enable_ev, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
late_enable_ev, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
late_enable_ev, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
late_enable_ev, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
late_enable_ev, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
late_enable_ev, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
late_enable_ev, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
late_enable_ev, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
};
static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
};
static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
dac_ev, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
dac_ev, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
dac_ev, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
dac_ev, SND_SOC_DAPM_PRE_PMU),
};
static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
};
static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
};
static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
};
static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("DMIC1DAT"),
SND_SOC_DAPM_INPUT("DMIC2DAT"),
SND_SOC_DAPM_INPUT("Clock"),
SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
0, SND_SOC_NOPM, 9, 0),
SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
0, SND_SOC_NOPM, 8, 0),
SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
0, SND_SOC_NOPM, 11, 0),
SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
0, SND_SOC_NOPM, 10, 0),
SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
dac1l_mix, ARRAY_SIZE(dac1l_mix)),
SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
dac1r_mix, ARRAY_SIZE(dac1r_mix)),
SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
SND_SOC_NOPM, 13, 0),
SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
SND_SOC_NOPM, 12, 0),
SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
/* Power is done with the muxes since the ADC power also controls the
* downsampling chain, the chip will automatically manage the analogue
* specific portions.
*/
SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_MUX("AIF1 Loopback", SND_SOC_NOPM, 0, 0, &aif1_loopback),
SND_SOC_DAPM_MUX("AIF2 Loopback", SND_SOC_NOPM, 0, 0, &aif2_loopback),
SND_SOC_DAPM_POST("Debug log", post_ev),
};
static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
};
static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
};
static const struct snd_soc_dapm_route intercon[] = {
{ "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
{ "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
{ "DSP1CLK", NULL, "CLK_SYS" },
{ "DSP2CLK", NULL, "CLK_SYS" },
{ "DSPINTCLK", NULL, "CLK_SYS" },
{ "AIF1ADC1L", NULL, "AIF1CLK" },
{ "AIF1ADC1L", NULL, "DSP1CLK" },
{ "AIF1ADC1R", NULL, "AIF1CLK" },
{ "AIF1ADC1R", NULL, "DSP1CLK" },
{ "AIF1ADC1R", NULL, "DSPINTCLK" },
{ "AIF1DAC1L", NULL, "AIF1CLK" },
{ "AIF1DAC1L", NULL, "DSP1CLK" },
{ "AIF1DAC1R", NULL, "AIF1CLK" },
{ "AIF1DAC1R", NULL, "DSP1CLK" },
{ "AIF1DAC1R", NULL, "DSPINTCLK" },
{ "AIF1ADC2L", NULL, "AIF1CLK" },
{ "AIF1ADC2L", NULL, "DSP1CLK" },
{ "AIF1ADC2R", NULL, "AIF1CLK" },
{ "AIF1ADC2R", NULL, "DSP1CLK" },
{ "AIF1ADC2R", NULL, "DSPINTCLK" },
{ "AIF1DAC2L", NULL, "AIF1CLK" },
{ "AIF1DAC2L", NULL, "DSP1CLK" },
{ "AIF1DAC2R", NULL, "AIF1CLK" },
{ "AIF1DAC2R", NULL, "DSP1CLK" },
{ "AIF1DAC2R", NULL, "DSPINTCLK" },
{ "AIF2ADCL", NULL, "AIF2CLK" },
{ "AIF2ADCL", NULL, "DSP2CLK" },
{ "AIF2ADCR", NULL, "AIF2CLK" },
{ "AIF2ADCR", NULL, "DSP2CLK" },
{ "AIF2ADCR", NULL, "DSPINTCLK" },
{ "AIF2DACL", NULL, "AIF2CLK" },
{ "AIF2DACL", NULL, "DSP2CLK" },
{ "AIF2DACR", NULL, "AIF2CLK" },
{ "AIF2DACR", NULL, "DSP2CLK" },
{ "AIF2DACR", NULL, "DSPINTCLK" },
{ "DMIC1L", NULL, "DMIC1DAT" },
{ "DMIC1L", NULL, "CLK_SYS" },
{ "DMIC1R", NULL, "DMIC1DAT" },
{ "DMIC1R", NULL, "CLK_SYS" },
{ "DMIC2L", NULL, "DMIC2DAT" },
{ "DMIC2L", NULL, "CLK_SYS" },
{ "DMIC2R", NULL, "DMIC2DAT" },
{ "DMIC2R", NULL, "CLK_SYS" },
{ "ADCL", NULL, "AIF1CLK" },
{ "ADCL", NULL, "DSP1CLK" },
{ "ADCL", NULL, "DSPINTCLK" },
{ "ADCR", NULL, "AIF1CLK" },
{ "ADCR", NULL, "DSP1CLK" },
{ "ADCR", NULL, "DSPINTCLK" },
{ "ADCL Mux", "ADC", "ADCL" },
{ "ADCL Mux", "DMIC", "DMIC1L" },
{ "ADCR Mux", "ADC", "ADCR" },
{ "ADCR Mux", "DMIC", "DMIC1R" },
{ "DAC1L", NULL, "AIF1CLK" },
{ "DAC1L", NULL, "DSP1CLK" },
{ "DAC1L", NULL, "DSPINTCLK" },
{ "DAC1R", NULL, "AIF1CLK" },
{ "DAC1R", NULL, "DSP1CLK" },
{ "DAC1R", NULL, "DSPINTCLK" },
{ "DAC2L", NULL, "AIF2CLK" },
{ "DAC2L", NULL, "DSP2CLK" },
{ "DAC2L", NULL, "DSPINTCLK" },
{ "DAC2R", NULL, "AIF2DACR" },
{ "DAC2R", NULL, "AIF2CLK" },
{ "DAC2R", NULL, "DSP2CLK" },
{ "DAC2R", NULL, "DSPINTCLK" },
{ "TOCLK", NULL, "CLK_SYS" },
{ "AIF1DACDAT", NULL, "AIF1 Playback" },
{ "AIF2DACDAT", NULL, "AIF2 Playback" },
{ "AIF3DACDAT", NULL, "AIF3 Playback" },
{ "AIF1 Capture", NULL, "AIF1ADCDAT" },
{ "AIF2 Capture", NULL, "AIF2ADCDAT" },
{ "AIF3 Capture", NULL, "AIF3ADCDAT" },
/* AIF1 outputs */
{ "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
{ "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
{ "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
{ "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
{ "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
{ "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
{ "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
{ "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
{ "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
{ "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
{ "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
{ "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
/* Pin level routing for AIF3 */
{ "AIF1DAC1L", NULL, "AIF1DAC Mux" },
{ "AIF1DAC1R", NULL, "AIF1DAC Mux" },
{ "AIF1DAC2L", NULL, "AIF1DAC Mux" },
{ "AIF1DAC2R", NULL, "AIF1DAC Mux" },
{ "AIF1DAC Mux", "AIF1DACDAT", "AIF1 Loopback" },
{ "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
{ "AIF2DAC Mux", "AIF2DACDAT", "AIF2 Loopback" },
{ "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
{ "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
{ "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
{ "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
/* DAC1 inputs */
{ "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
{ "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
{ "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
{ "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
{ "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
{ "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
{ "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
{ "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
{ "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
{ "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
/* DAC2/AIF2 outputs */
{ "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
{ "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
{ "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
{ "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
{ "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
{ "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
{ "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
{ "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
{ "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
{ "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
{ "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
{ "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
{ "AIF1ADCDAT", NULL, "AIF1ADC1L" },
{ "AIF1ADCDAT", NULL, "AIF1ADC1R" },
{ "AIF1ADCDAT", NULL, "AIF1ADC2L" },
{ "AIF1ADCDAT", NULL, "AIF1ADC2R" },
{ "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
/* AIF3 output */
{ "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC1L" },
{ "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC1R" },
{ "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC2L" },
{ "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC2R" },
{ "AIF3ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
{ "AIF3ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
{ "AIF3ADC Mux", "AIF2DACDAT", "AIF2DACL" },
{ "AIF3ADC Mux", "AIF2DACDAT", "AIF2DACR" },
{ "AIF3ADCDAT", NULL, "AIF3ADC Mux" },
/* Loopback */
{ "AIF1 Loopback", "ADCDAT", "AIF1ADCDAT" },
{ "AIF1 Loopback", "None", "AIF1DACDAT" },
{ "AIF2 Loopback", "ADCDAT", "AIF2ADCDAT" },
{ "AIF2 Loopback", "None", "AIF2DACDAT" },
/* Sidetone */
{ "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
{ "Left Sidetone", "DMIC2", "DMIC2L" },
{ "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
{ "Right Sidetone", "DMIC2", "DMIC2R" },
/* Output stages */
{ "Left Output Mixer", "DAC Switch", "DAC1L" },
{ "Right Output Mixer", "DAC Switch", "DAC1R" },
{ "SPKL", "DAC1 Switch", "DAC1L" },
{ "SPKL", "DAC2 Switch", "DAC2L" },
{ "SPKR", "DAC1 Switch", "DAC1R" },
{ "SPKR", "DAC2 Switch", "DAC2R" },
{ "Left Headphone Mux", "DAC", "DAC1L" },
{ "Right Headphone Mux", "DAC", "DAC1R" },
};
static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
{ "DAC1L", NULL, "Late DAC1L Enable PGA" },
{ "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
{ "DAC1R", NULL, "Late DAC1R Enable PGA" },
{ "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
{ "DAC2L", NULL, "Late DAC2L Enable PGA" },
{ "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
{ "DAC2R", NULL, "Late DAC2R Enable PGA" },
{ "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
};
static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
{ "DAC1L", NULL, "DAC1L Mixer" },
{ "DAC1R", NULL, "DAC1R Mixer" },
{ "DAC2L", NULL, "AIF2DAC2L Mixer" },
{ "DAC2R", NULL, "AIF2DAC2R Mixer" },
};
static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
{ "AIF1DACDAT", NULL, "AIF2DACDAT" },
{ "AIF2DACDAT", NULL, "AIF1DACDAT" },
{ "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
{ "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
{ "MICBIAS1", NULL, "CLK_SYS" },
{ "MICBIAS1", NULL, "MICBIAS Supply" },
{ "MICBIAS2", NULL, "CLK_SYS" },
{ "MICBIAS2", NULL, "MICBIAS Supply" },
};
static const struct snd_soc_dapm_route wm8994_intercon[] = {
{ "AIF2DACL", NULL, "AIF2DAC Mux" },
{ "AIF2DACR", NULL, "AIF2DAC Mux" },
{ "MICBIAS1", NULL, "VMID" },
{ "MICBIAS2", NULL, "VMID" },
};
static const struct snd_soc_dapm_route wm8958_intercon[] = {
{ "AIF2DACL", NULL, "AIF2DACL Mux" },
{ "AIF2DACR", NULL, "AIF2DACR Mux" },
{ "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
{ "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
{ "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
{ "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
{ "AIF3DACDAT", NULL, "AIF3" },
{ "AIF3ADCDAT", NULL, "AIF3" },
{ "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
{ "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
{ "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
};
/* The size in bits of the FLL divide multiplied by 10
* to allow rounding later */
#define FIXED_FLL_SIZE ((1 << 16) * 10)
struct fll_div {
u16 outdiv;
u16 n;
u16 k;
u16 lambda;
u16 clk_ref_div;
u16 fll_fratio;
};
static int wm8994_get_fll_config(struct wm8994 *control, struct fll_div *fll,
int freq_in, int freq_out)
{
u64 Kpart;
unsigned int K, Ndiv, Nmod, gcd_fll;
pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
/* Scale the input frequency down to <= 13.5MHz */
fll->clk_ref_div = 0;
while (freq_in > 13500000) {
fll->clk_ref_div++;
freq_in /= 2;
if (fll->clk_ref_div > 3)
return -EINVAL;
}
pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
/* Scale the output to give 90MHz<=Fvco<=100MHz */
fll->outdiv = 3;
while (freq_out * (fll->outdiv + 1) < 90000000) {
fll->outdiv++;
if (fll->outdiv > 63)
return -EINVAL;
}
freq_out *= fll->outdiv + 1;
pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
if (freq_in > 1000000) {
fll->fll_fratio = 0;
} else if (freq_in > 256000) {
fll->fll_fratio = 1;
freq_in *= 2;
} else if (freq_in > 128000) {
fll->fll_fratio = 2;
freq_in *= 4;
} else if (freq_in > 64000) {
fll->fll_fratio = 3;
freq_in *= 8;
} else {
fll->fll_fratio = 4;
freq_in *= 16;
}
pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
/* Now, calculate N.K */
Ndiv = freq_out / freq_in;
fll->n = Ndiv;
Nmod = freq_out % freq_in;
pr_debug("Nmod=%d\n", Nmod);
switch (control->type) {
case WM8994:
/* Calculate fractional part - scale up so we can round. */
Kpart = FIXED_FLL_SIZE * (long long)Nmod;
do_div(Kpart, freq_in);
K = Kpart & 0xFFFFFFFF;
if ((K % 10) >= 5)
K += 5;
/* Move down to proper range now rounding is done */
fll->k = K / 10;
fll->lambda = 0;
pr_debug("N=%x K=%x\n", fll->n, fll->k);
break;
default:
gcd_fll = gcd(freq_out, freq_in);
fll->k = (freq_out - (freq_in * fll->n)) / gcd_fll;
fll->lambda = freq_in / gcd_fll;
}
return 0;
}
static int _wm8994_set_fll(struct snd_soc_component *component, int id, int src,
unsigned int freq_in, unsigned int freq_out)
{
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
struct wm8994 *control = wm8994->wm8994;
int reg_offset, ret;
struct fll_div fll;
u16 reg, clk1, aif_reg, aif_src;
unsigned long timeout;
bool was_enabled;
struct clk *mclk;
switch (id) {
case WM8994_FLL1:
reg_offset = 0;
id = 0;
aif_src = 0x10;
break;
case WM8994_FLL2:
reg_offset = 0x20;
id = 1;
aif_src = 0x18;
break;
default:
return -EINVAL;
}
reg = snd_soc_component_read(component, WM8994_FLL1_CONTROL_1 + reg_offset);
was_enabled = reg & WM8994_FLL1_ENA;
switch (src) {
case 0:
/* Allow no source specification when stopping */
if (freq_out)
return -EINVAL;
src = wm8994->fll[id].src;
break;
case WM8994_FLL_SRC_MCLK1:
case WM8994_FLL_SRC_MCLK2:
case WM8994_FLL_SRC_LRCLK:
case WM8994_FLL_SRC_BCLK:
break;
case WM8994_FLL_SRC_INTERNAL:
freq_in = 12000000;
freq_out = 12000000;
break;
default:
return -EINVAL;
}
/* Are we changing anything? */
if (wm8994->fll[id].src == src &&
wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
return 0;
/* If we're stopping the FLL redo the old config - no
* registers will actually be written but we avoid GCC flow
* analysis bugs spewing warnings.
*/
if (freq_out)
ret = wm8994_get_fll_config(control, &fll, freq_in, freq_out);
else
ret = wm8994_get_fll_config(control, &fll, wm8994->fll[id].in,
wm8994->fll[id].out);
if (ret < 0)
return ret;
/* Make sure that we're not providing SYSCLK right now */
clk1 = snd_soc_component_read(component, WM8994_CLOCKING_1);
if (clk1 & WM8994_SYSCLK_SRC)
aif_reg = WM8994_AIF2_CLOCKING_1;
else
aif_reg = WM8994_AIF1_CLOCKING_1;
reg = snd_soc_component_read(component, aif_reg);
if ((reg & WM8994_AIF1CLK_ENA) &&
(reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
dev_err(component->dev, "FLL%d is currently providing SYSCLK\n",
id + 1);
return -EBUSY;
}
/* We always need to disable the FLL while reconfiguring */
snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_1 + reg_offset,
WM8994_FLL1_ENA, 0);
/* Disable MCLK if needed before we possibly change to new clock parent */
if (was_enabled) {
reg = snd_soc_component_read(component, WM8994_FLL1_CONTROL_5
+ reg_offset);
reg = ((reg & WM8994_FLL1_REFCLK_SRC_MASK)
>> WM8994_FLL1_REFCLK_SRC_SHIFT) + 1;
switch (reg) {
case WM8994_FLL_SRC_MCLK1:
mclk = wm8994->mclk[WM8994_MCLK1].clk;
break;
case WM8994_FLL_SRC_MCLK2:
mclk = wm8994->mclk[WM8994_MCLK2].clk;
break;
default:
mclk = NULL;
}
clk_disable_unprepare(mclk);
}
if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
freq_in == freq_out && freq_out) {
dev_dbg(component->dev, "Bypassing FLL%d\n", id + 1);
snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_5 + reg_offset,
WM8958_FLL1_BYP, WM8958_FLL1_BYP);
goto out;
}
reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
(fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_2 + reg_offset,
WM8994_FLL1_OUTDIV_MASK |
WM8994_FLL1_FRATIO_MASK, reg);
snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_3 + reg_offset,
WM8994_FLL1_K_MASK, fll.k);
snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_4 + reg_offset,
WM8994_FLL1_N_MASK,
fll.n << WM8994_FLL1_N_SHIFT);
if (fll.lambda) {
snd_soc_component_update_bits(component, WM8958_FLL1_EFS_1 + reg_offset,
WM8958_FLL1_LAMBDA_MASK,
fll.lambda);
snd_soc_component_update_bits(component, WM8958_FLL1_EFS_2 + reg_offset,
WM8958_FLL1_EFS_ENA, WM8958_FLL1_EFS_ENA);
} else {
snd_soc_component_update_bits(component, WM8958_FLL1_EFS_2 + reg_offset,
WM8958_FLL1_EFS_ENA, 0);
}
snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_5 + reg_offset,
WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP |
WM8994_FLL1_REFCLK_DIV_MASK |
WM8994_FLL1_REFCLK_SRC_MASK,
((src == WM8994_FLL_SRC_INTERNAL)
<< WM8994_FLL1_FRC_NCO_SHIFT) |
(fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
(src - 1));
/* Clear any pending completion from a previous failure */
try_wait_for_completion(&wm8994->fll_locked[id]);
switch (src) {
case WM8994_FLL_SRC_MCLK1:
mclk = wm8994->mclk[WM8994_MCLK1].clk;
break;
case WM8994_FLL_SRC_MCLK2:
mclk = wm8994->mclk[WM8994_MCLK2].clk;
break;
default:
mclk = NULL;
}
/* Enable (with fractional mode if required) */
if (freq_out) {
ret = clk_prepare_enable(mclk);
if (ret < 0) {
dev_err(component->dev, "Failed to enable MCLK for FLL%d\n",
id + 1);
return ret;
}
/* Enable VMID if we need it */
if (!was_enabled) {
active_reference(component);
switch (control->type) {
case WM8994:
vmid_reference(component);
break;
case WM8958:
if (control->revision < 1)
vmid_reference(component);
break;
default:
break;
}
}
reg = WM8994_FLL1_ENA;
if (fll.k)
reg |= WM8994_FLL1_FRAC;
if (src == WM8994_FLL_SRC_INTERNAL)
reg |= WM8994_FLL1_OSC_ENA;
snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_1 + reg_offset,
WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA |
WM8994_FLL1_FRAC, reg);
if (wm8994->fll_locked_irq) {
timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
msecs_to_jiffies(10));
if (timeout == 0)
dev_warn(component->dev,
"Timed out waiting for FLL lock\n");
} else {
msleep(5);
}
} else {
if (was_enabled) {
switch (control->type) {
case WM8994:
vmid_dereference(component);
break;
case WM8958:
if (control->revision < 1)
vmid_dereference(component);
break;
default:
break;
}
active_dereference(component);
}
}
out:
wm8994->fll[id].in = freq_in;
wm8994->fll[id].out = freq_out;
wm8994->fll[id].src = src;
configure_clock(component);
/*
* If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
* for detection.
*/
if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
dev_dbg(component->dev, "Configuring AIFs for 128fs\n");
wm8994->aifdiv[0] = snd_soc_component_read(component, WM8994_AIF1_RATE)
& WM8994_AIF1CLK_RATE_MASK;
wm8994->aifdiv[1] = snd_soc_component_read(component, WM8994_AIF2_RATE)
& WM8994_AIF1CLK_RATE_MASK;
snd_soc_component_update_bits(component, WM8994_AIF1_RATE,
WM8994_AIF1CLK_RATE_MASK, 0x1);
snd_soc_component_update_bits(component, WM8994_AIF2_RATE,
WM8994_AIF2CLK_RATE_MASK, 0x1);
} else if (wm8994->aifdiv[0]) {
snd_soc_component_update_bits(component, WM8994_AIF1_RATE,
WM8994_AIF1CLK_RATE_MASK,
wm8994->aifdiv[0]);
snd_soc_component_update_bits(component, WM8994_AIF2_RATE,
WM8994_AIF2CLK_RATE_MASK,
wm8994->aifdiv[1]);
wm8994->aifdiv[0] = 0;
wm8994->aifdiv[1] = 0;
}
return 0;
}
static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
{
struct completion *completion = data;
complete(completion);
return IRQ_HANDLED;
}
static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
unsigned int freq_in, unsigned int freq_out)
{
return _wm8994_set_fll(dai->component, id, src, freq_in, freq_out);
}
static int wm8994_set_mclk_rate(struct wm8994_priv *wm8994, unsigned int id,
unsigned int *freq)
{
int ret;
if (!wm8994->mclk[id].clk || *freq == wm8994->mclk_rate[id])
return 0;
ret = clk_set_rate(wm8994->mclk[id].clk, *freq);
if (ret < 0)
return ret;
*freq = clk_get_rate(wm8994->mclk[id].clk);
return 0;
}
static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
int ret, i;
switch (dai->id) {
case 1:
case 2:
break;
default:
/* AIF3 shares clocking with AIF1/2 */
return -EINVAL;
}
switch (clk_id) {
case WM8994_SYSCLK_MCLK1:
wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
ret = wm8994_set_mclk_rate(wm8994, dai->id - 1, &freq);
if (ret < 0)
return ret;
wm8994->mclk_rate[0] = freq;
dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
dai->id, freq);
break;
case WM8994_SYSCLK_MCLK2:
/* TODO: Set GPIO AF */
wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
ret = wm8994_set_mclk_rate(wm8994, dai->id - 1, &freq);
if (ret < 0)
return ret;
wm8994->mclk_rate[1] = freq;
dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
dai->id, freq);
break;
case WM8994_SYSCLK_FLL1:
wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
break;
case WM8994_SYSCLK_FLL2:
wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
break;
case WM8994_SYSCLK_OPCLK:
/* Special case - a division (times 10) is given and
* no effect on main clocking.
*/
if (freq) {
for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
if (opclk_divs[i] == freq)
break;
if (i == ARRAY_SIZE(opclk_divs))
return -EINVAL;
snd_soc_component_update_bits(component, WM8994_CLOCKING_2,
WM8994_OPCLK_DIV_MASK, i);
snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_2,
WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
} else {
snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_2,
WM8994_OPCLK_ENA, 0);
}
break;
default:
return -EINVAL;
}
configure_clock(component);
/*
* If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
* for detection.
*/
if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
dev_dbg(component->dev, "Configuring AIFs for 128fs\n");
wm8994->aifdiv[0] = snd_soc_component_read(component, WM8994_AIF1_RATE)
& WM8994_AIF1CLK_RATE_MASK;
wm8994->aifdiv[1] = snd_soc_component_read(component, WM8994_AIF2_RATE)
& WM8994_AIF1CLK_RATE_MASK;
snd_soc_component_update_bits(component, WM8994_AIF1_RATE,
WM8994_AIF1CLK_RATE_MASK, 0x1);
snd_soc_component_update_bits(component, WM8994_AIF2_RATE,
WM8994_AIF2CLK_RATE_MASK, 0x1);
} else if (wm8994->aifdiv[0]) {
snd_soc_component_update_bits(component, WM8994_AIF1_RATE,
WM8994_AIF1CLK_RATE_MASK,
wm8994->aifdiv[0]);
snd_soc_component_update_bits(component, WM8994_AIF2_RATE,
WM8994_AIF2CLK_RATE_MASK,
wm8994->aifdiv[1]);
wm8994->aifdiv[0] = 0;
wm8994->aifdiv[1] = 0;
}
return 0;
}
static int wm8994_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
struct wm8994 *control = wm8994->wm8994;
wm_hubs_set_bias_level(component, level);
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
/* MICBIAS into regulating mode */
switch (control->type) {
case WM8958:
case WM1811:
snd_soc_component_update_bits(component, WM8958_MICBIAS1,
WM8958_MICB1_MODE, 0);
snd_soc_component_update_bits(component, WM8958_MICBIAS2,
WM8958_MICB2_MODE, 0);
break;
default:
break;
}
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY)
active_reference(component);
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
switch (control->type) {
case WM8958:
if (control->revision == 0) {
/* Optimise performance for rev A */
snd_soc_component_update_bits(component,
WM8958_CHARGE_PUMP_2,
WM8958_CP_DISCH,
WM8958_CP_DISCH);
}
break;
default:
break;
}
/* Discharge LINEOUT1 & 2 */
snd_soc_component_update_bits(component, WM8994_ANTIPOP_1,
WM8994_LINEOUT1_DISCH |
WM8994_LINEOUT2_DISCH,
WM8994_LINEOUT1_DISCH |
WM8994_LINEOUT2_DISCH);
}
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE)
active_dereference(component);
/* MICBIAS into bypass mode on newer devices */
switch (control->type) {
case WM8958:
case WM1811:
snd_soc_component_update_bits(component, WM8958_MICBIAS1,
WM8958_MICB1_MODE,
WM8958_MICB1_MODE);
snd_soc_component_update_bits(component, WM8958_MICBIAS2,
WM8958_MICB2_MODE,
WM8958_MICB2_MODE);
break;
default:
break;
}
break;
case SND_SOC_BIAS_OFF:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY)
wm8994->cur_fw = NULL;
break;
}
return 0;
}
int wm8994_vmid_mode(struct snd_soc_component *component, enum wm8994_vmid_mode mode)
{
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
switch (mode) {
case WM8994_VMID_NORMAL:
snd_soc_dapm_mutex_lock(dapm);
if (wm8994->hubs.lineout1_se) {
snd_soc_dapm_disable_pin_unlocked(dapm,
"LINEOUT1N Driver");
snd_soc_dapm_disable_pin_unlocked(dapm,
"LINEOUT1P Driver");
}
if (wm8994->hubs.lineout2_se) {
snd_soc_dapm_disable_pin_unlocked(dapm,
"LINEOUT2N Driver");
snd_soc_dapm_disable_pin_unlocked(dapm,
"LINEOUT2P Driver");
}
/* Do the sync with the old mode to allow it to clean up */
snd_soc_dapm_sync_unlocked(dapm);
wm8994->vmid_mode = mode;
snd_soc_dapm_mutex_unlock(dapm);
break;
case WM8994_VMID_FORCE:
snd_soc_dapm_mutex_lock(dapm);
if (wm8994->hubs.lineout1_se) {
snd_soc_dapm_force_enable_pin_unlocked(dapm,
"LINEOUT1N Driver");
snd_soc_dapm_force_enable_pin_unlocked(dapm,
"LINEOUT1P Driver");
}
if (wm8994->hubs.lineout2_se) {
snd_soc_dapm_force_enable_pin_unlocked(dapm,
"LINEOUT2N Driver");
snd_soc_dapm_force_enable_pin_unlocked(dapm,
"LINEOUT2P Driver");
}
wm8994->vmid_mode = mode;
snd_soc_dapm_sync_unlocked(dapm);
snd_soc_dapm_mutex_unlock(dapm);
break;
default:
return -EINVAL;
}
return 0;
}
static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
struct wm8994 *control = wm8994->wm8994;
int ms_reg;
int aif1_reg;
int dac_reg;
int adc_reg;
int ms = 0;
int aif1 = 0;
int lrclk = 0;
switch (dai->id) {
case 1:
ms_reg = WM8994_AIF1_MASTER_SLAVE;
aif1_reg = WM8994_AIF1_CONTROL_1;
dac_reg = WM8994_AIF1DAC_LRCLK;
adc_reg = WM8994_AIF1ADC_LRCLK;
break;
case 2:
ms_reg = WM8994_AIF2_MASTER_SLAVE;
aif1_reg = WM8994_AIF2_CONTROL_1;
dac_reg = WM8994_AIF1DAC_LRCLK;
adc_reg = WM8994_AIF1ADC_LRCLK;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
break;
case SND_SOC_DAIFMT_CBM_CFM:
ms = WM8994_AIF1_MSTR;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_B:
aif1 |= WM8994_AIF1_LRCLK_INV;
lrclk |= WM8958_AIF1_LRCLK_INV;
fallthrough;
case SND_SOC_DAIFMT_DSP_A:
aif1 |= 0x18;
break;
case SND_SOC_DAIFMT_I2S:
aif1 |= 0x10;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
aif1 |= 0x8;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B:
/* frame inversion not valid for DSP modes */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
aif1 |= WM8994_AIF1_BCLK_INV;
break;
default:
return -EINVAL;
}
break;
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_RIGHT_J:
case SND_SOC_DAIFMT_LEFT_J:
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
lrclk |= WM8958_AIF1_LRCLK_INV;
break;
case SND_SOC_DAIFMT_IB_NF:
aif1 |= WM8994_AIF1_BCLK_INV;
break;
case SND_SOC_DAIFMT_NB_IF:
aif1 |= WM8994_AIF1_LRCLK_INV;
lrclk |= WM8958_AIF1_LRCLK_INV;
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
/* The AIF2 format configuration needs to be mirrored to AIF3
* on WM8958 if it's in use so just do it all the time. */
switch (control->type) {
case WM1811:
case WM8958:
if (dai->id == 2)
snd_soc_component_update_bits(component, WM8958_AIF3_CONTROL_1,
WM8994_AIF1_LRCLK_INV |
WM8958_AIF3_FMT_MASK, aif1);
break;
default:
break;
}
snd_soc_component_update_bits(component, aif1_reg,
WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
WM8994_AIF1_FMT_MASK,
aif1);
snd_soc_component_update_bits(component, ms_reg, WM8994_AIF1_MSTR,
ms);
snd_soc_component_update_bits(component, dac_reg,
WM8958_AIF1_LRCLK_INV, lrclk);
snd_soc_component_update_bits(component, adc_reg,
WM8958_AIF1_LRCLK_INV, lrclk);
return 0;
}
static struct {
int val, rate;
} srs[] = {
{ 0, 8000 },
{ 1, 11025 },
{ 2, 12000 },
{ 3, 16000 },
{ 4, 22050 },
{ 5, 24000 },
{ 6, 32000 },
{ 7, 44100 },
{ 8, 48000 },
{ 9, 88200 },
{ 10, 96000 },
};
static int fs_ratios[] = {
64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536
};
static int bclk_divs[] = {
10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
640, 880, 960, 1280, 1760, 1920
};
static int wm8994_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
struct wm8994 *control = wm8994->wm8994;
struct wm8994_pdata *pdata = &control->pdata;
int aif1_reg;
int aif2_reg;
int bclk_reg;
int lrclk_reg;
int rate_reg;
int aif1 = 0;
int aif2 = 0;
int bclk = 0;
int lrclk = 0;
int rate_val = 0;
int id = dai->id - 1;
int i, cur_val, best_val, bclk_rate, best;
switch (dai->id) {
case 1:
aif1_reg = WM8994_AIF1_CONTROL_1;
aif2_reg = WM8994_AIF1_CONTROL_2;
bclk_reg = WM8994_AIF1_BCLK;
rate_reg = WM8994_AIF1_RATE;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
wm8994->lrclk_shared[0]) {
lrclk_reg = WM8994_AIF1DAC_LRCLK;
} else {
lrclk_reg = WM8994_AIF1ADC_LRCLK;
dev_dbg(component->dev, "AIF1 using split LRCLK\n");
}
break;
case 2:
aif1_reg = WM8994_AIF2_CONTROL_1;
aif2_reg = WM8994_AIF2_CONTROL_2;
bclk_reg = WM8994_AIF2_BCLK;
rate_reg = WM8994_AIF2_RATE;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
wm8994->lrclk_shared[1]) {
lrclk_reg = WM8994_AIF2DAC_LRCLK;
} else {
lrclk_reg = WM8994_AIF2ADC_LRCLK;
dev_dbg(component->dev, "AIF2 using split LRCLK\n");
}
break;
default:
return -EINVAL;
}
bclk_rate = params_rate(params);
switch (params_width(params)) {
case 16:
bclk_rate *= 16;
break;
case 20:
bclk_rate *= 20;
aif1 |= 0x20;
break;
case 24:
bclk_rate *= 24;
aif1 |= 0x40;
break;
case 32:
bclk_rate *= 32;
aif1 |= 0x60;
break;
default:
return -EINVAL;
}
wm8994->channels[id] = params_channels(params);
if (pdata->max_channels_clocked[id] &&
wm8994->channels[id] > pdata->max_channels_clocked[id]) {
dev_dbg(dai->dev, "Constraining channels to %d from %d\n",
pdata->max_channels_clocked[id], wm8994->channels[id]);
wm8994->channels[id] = pdata->max_channels_clocked[id];
}
switch (wm8994->channels[id]) {
case 1:
case 2:
bclk_rate *= 2;
break;
default:
bclk_rate *= 4;
break;
}
/* Try to find an appropriate sample rate; look for an exact match. */
for (i = 0; i < ARRAY_SIZE(srs); i++)
if (srs[i].rate == params_rate(params))
break;
if (i == ARRAY_SIZE(srs))
return -EINVAL;
rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
dai->id, wm8994->aifclk[id], bclk_rate);
if (wm8994->channels[id] == 1 &&
(snd_soc_component_read(component, aif1_reg) & 0x18) == 0x18)
aif2 |= WM8994_AIF1_MONO;
if (wm8994->aifclk[id] == 0) {
dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
return -EINVAL;
}
/* AIFCLK/fs ratio; look for a close match in either direction */
best = 0;
best_val = abs((fs_ratios[0] * params_rate(params))
- wm8994->aifclk[id]);
for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
cur_val = abs((fs_ratios[i] * params_rate(params))
- wm8994->aifclk[id]);
if (cur_val >= best_val)
continue;
best = i;
best_val = cur_val;
}
dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
dai->id, fs_ratios[best]);
rate_val |= best;
/* We may not get quite the right frequency if using
* approximate clocks so look for the closest match that is
* higher than the target (we need to ensure that there enough
* BCLKs to clock out the samples).
*/
best = 0;
for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
if (cur_val < 0) /* BCLK table is sorted */
break;
best = i;
}
bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
bclk_divs[best], bclk_rate);
bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
lrclk = bclk_rate / params_rate(params);
if (!lrclk) {
dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
bclk_rate);
return -EINVAL;
}
dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
lrclk, bclk_rate / lrclk);
snd_soc_component_update_bits(component, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
snd_soc_component_update_bits(component, aif2_reg, WM8994_AIF1_MONO, aif2);
snd_soc_component_update_bits(component, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
snd_soc_component_update_bits(component, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
lrclk);
snd_soc_component_update_bits(component, rate_reg, WM8994_AIF1_SR_MASK |
WM8994_AIF1CLK_RATE_MASK, rate_val);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
switch (dai->id) {
case 1:
wm8994->dac_rates[0] = params_rate(params);
wm8994_set_retune_mobile(component, 0);
wm8994_set_retune_mobile(component, 1);
break;
case 2:
wm8994->dac_rates[1] = params_rate(params);
wm8994_set_retune_mobile(component, 2);
break;
}
}
return 0;
}
static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
struct wm8994 *control = wm8994->wm8994;
int aif1_reg;
int aif1 = 0;
switch (dai->id) {
case 3:
switch (control->type) {
case WM1811:
case WM8958:
aif1_reg = WM8958_AIF3_CONTROL_1;
break;
default:
return 0;
}
break;
default:
return 0;
}
switch (params_width(params)) {
case 16:
break;
case 20:
aif1 |= 0x20;
break;
case 24:
aif1 |= 0x40;
break;
case 32:
aif1 |= 0x60;
break;
default:
return -EINVAL;
}
return snd_soc_component_update_bits(component, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
}
static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute,
int direction)
{
struct snd_soc_component *component = codec_dai->component;
int mute_reg;
int reg;
switch (codec_dai->id) {
case 1:
mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
break;
case 2:
mute_reg = WM8994_AIF2_DAC_FILTERS_1;
break;
default:
return -EINVAL;
}
if (mute)
reg = WM8994_AIF1DAC1_MUTE;
else
reg = 0;
snd_soc_component_update_bits(component, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
return 0;
}
static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
{
struct snd_soc_component *component = codec_dai->component;
int reg, val, mask;
switch (codec_dai->id) {
case 1:
reg = WM8994_AIF1_MASTER_SLAVE;
mask = WM8994_AIF1_TRI;
break;
case 2:
reg = WM8994_AIF2_MASTER_SLAVE;
mask = WM8994_AIF2_TRI;
break;
default:
return -EINVAL;
}
if (tristate)
val = mask;
else
val = 0;
return snd_soc_component_update_bits(component, reg, mask, val);
}
static int wm8994_aif2_probe(struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
/* Disable the pulls on the AIF if we're using it to save power. */
snd_soc_component_update_bits(component, WM8994_GPIO_3,
WM8994_GPN_PU | WM8994_GPN_PD, 0);
snd_soc_component_update_bits(component, WM8994_GPIO_4,
WM8994_GPN_PU | WM8994_GPN_PD, 0);
snd_soc_component_update_bits(component, WM8994_GPIO_5,
WM8994_GPN_PU | WM8994_GPN_PD, 0);
return 0;
}
#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
.set_sysclk = wm8994_set_dai_sysclk,
.set_fmt = wm8994_set_dai_fmt,
.hw_params = wm8994_hw_params,
.mute_stream = wm8994_aif_mute,
.set_pll = wm8994_set_fll,
.set_tristate = wm8994_set_tristate,
.no_capture_mute = 1,
};
static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
.probe = wm8994_aif2_probe,
.set_sysclk = wm8994_set_dai_sysclk,
.set_fmt = wm8994_set_dai_fmt,
.hw_params = wm8994_hw_params,
.mute_stream = wm8994_aif_mute,
.set_pll = wm8994_set_fll,
.set_tristate = wm8994_set_tristate,
.no_capture_mute = 1,
};
static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
.hw_params = wm8994_aif3_hw_params,
};
static struct snd_soc_dai_driver wm8994_dai[] = {
{
.name = "wm8994-aif1",
.id = 1,
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM8994_RATES,
.formats = WM8994_FORMATS,
.sig_bits = 24,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM8994_RATES,
.formats = WM8994_FORMATS,
.sig_bits = 24,
},
.ops = &wm8994_aif1_dai_ops,
},
{
.name = "wm8994-aif2",
.id = 2,
.playback = {
.stream_name = "AIF2 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM8994_RATES,
.formats = WM8994_FORMATS,
.sig_bits = 24,
},
.capture = {
.stream_name = "AIF2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM8994_RATES,
.formats = WM8994_FORMATS,
.sig_bits = 24,
},
.ops = &wm8994_aif2_dai_ops,
},
{
.name = "wm8994-aif3",
.id = 3,
.playback = {
.stream_name = "AIF3 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM8994_RATES,
.formats = WM8994_FORMATS,
.sig_bits = 24,
},
.capture = {
.stream_name = "AIF3 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM8994_RATES,
.formats = WM8994_FORMATS,
.sig_bits = 24,
},
.ops = &wm8994_aif3_dai_ops,
}
};
#ifdef CONFIG_PM
static int wm8994_component_suspend(struct snd_soc_component *component)
{
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
int i, ret;
for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
sizeof(struct wm8994_fll_config));
ret = _wm8994_set_fll(component, i + 1, 0, 0, 0);
if (ret < 0)
dev_warn(component->dev, "Failed to stop FLL%d: %d\n",
i + 1, ret);
}
snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
return 0;
}
static int wm8994_component_resume(struct snd_soc_component *component)
{
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
int i, ret;
for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
if (!wm8994->fll_suspend[i].out)
continue;
ret = _wm8994_set_fll(component, i + 1,
wm8994->fll_suspend[i].src,
wm8994->fll_suspend[i].in,
wm8994->fll_suspend[i].out);
if (ret < 0)
dev_warn(component->dev, "Failed to restore FLL%d: %d\n",
i + 1, ret);
}
return 0;
}
#else
#define wm8994_component_suspend NULL
#define wm8994_component_resume NULL
#endif
static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
{
struct snd_soc_component *component = wm8994->hubs.component;
struct wm8994 *control = wm8994->wm8994;
struct wm8994_pdata *pdata = &control->pdata;
struct snd_kcontrol_new controls[] = {
SOC_ENUM_EXT("AIF1.1 EQ Mode",
wm8994->retune_mobile_enum,
wm8994_get_retune_mobile_enum,
wm8994_put_retune_mobile_enum),
SOC_ENUM_EXT("AIF1.2 EQ Mode",
wm8994->retune_mobile_enum,
wm8994_get_retune_mobile_enum,
wm8994_put_retune_mobile_enum),
SOC_ENUM_EXT("AIF2 EQ Mode",
wm8994->retune_mobile_enum,
wm8994_get_retune_mobile_enum,
wm8994_put_retune_mobile_enum),
};
int ret, i, j;
const char **t;
/* We need an array of texts for the enum API but the number
* of texts is likely to be less than the number of
* configurations due to the sample rate dependency of the
* configurations. */
wm8994->num_retune_mobile_texts = 0;
wm8994->retune_mobile_texts = NULL;
for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
if (strcmp(pdata->retune_mobile_cfgs[i].name,
wm8994->retune_mobile_texts[j]) == 0)
break;
}
if (j != wm8994->num_retune_mobile_texts)
continue;
/* Expand the array... */
t = krealloc(wm8994->retune_mobile_texts,
sizeof(char *) *
(wm8994->num_retune_mobile_texts + 1),
GFP_KERNEL);
if (t == NULL)
continue;
/* ...store the new entry... */
t[wm8994->num_retune_mobile_texts] =
pdata->retune_mobile_cfgs[i].name;
/* ...and remember the new version. */
wm8994->num_retune_mobile_texts++;
wm8994->retune_mobile_texts = t;
}
dev_dbg(component->dev, "Allocated %d unique ReTune Mobile names\n",
wm8994->num_retune_mobile_texts);
wm8994->retune_mobile_enum.items = wm8994->num_retune_mobile_texts;
wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
ret = snd_soc_add_component_controls(wm8994->hubs.component, controls,
ARRAY_SIZE(controls));
if (ret != 0)
dev_err(wm8994->hubs.component->dev,
"Failed to add ReTune Mobile controls: %d\n", ret);
}
static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
{
struct snd_soc_component *component = wm8994->hubs.component;
struct wm8994 *control = wm8994->wm8994;
struct wm8994_pdata *pdata = &control->pdata;
int ret, i;
if (!pdata)
return;
wm_hubs_handle_analogue_pdata(component, pdata->lineout1_diff,
pdata->lineout2_diff,
pdata->lineout1fb,
pdata->lineout2fb,
pdata->jd_scthr,
pdata->jd_thr,
pdata->micb1_delay,
pdata->micb2_delay,
pdata->micbias1_lvl,
pdata->micbias2_lvl);
dev_dbg(component->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
if (pdata->num_drc_cfgs) {
struct snd_kcontrol_new controls[] = {
SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
wm8994_get_drc_enum, wm8994_put_drc_enum),
SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
wm8994_get_drc_enum, wm8994_put_drc_enum),
SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
wm8994_get_drc_enum, wm8994_put_drc_enum),
};
/* We need an array of texts for the enum API */
wm8994->drc_texts = devm_kcalloc(wm8994->hubs.component->dev,
pdata->num_drc_cfgs, sizeof(char *), GFP_KERNEL);
if (!wm8994->drc_texts)
return;
for (i = 0; i < pdata->num_drc_cfgs; i++)
wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
wm8994->drc_enum.items = pdata->num_drc_cfgs;
wm8994->drc_enum.texts = wm8994->drc_texts;
ret = snd_soc_add_component_controls(wm8994->hubs.component, controls,
ARRAY_SIZE(controls));
for (i = 0; i < WM8994_NUM_DRC; i++)
wm8994_set_drc(component, i);
} else {
ret = snd_soc_add_component_controls(wm8994->hubs.component,
wm8994_drc_controls,
ARRAY_SIZE(wm8994_drc_controls));
}
if (ret != 0)
dev_err(wm8994->hubs.component->dev,
"Failed to add DRC mode controls: %d\n", ret);
dev_dbg(component->dev, "%d ReTune Mobile configurations\n",
pdata->num_retune_mobile_cfgs);
if (pdata->num_retune_mobile_cfgs)
wm8994_handle_retune_mobile_pdata(wm8994);
else
snd_soc_add_component_controls(wm8994->hubs.component, wm8994_eq_controls,
ARRAY_SIZE(wm8994_eq_controls));
for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
if (pdata->micbias[i]) {
snd_soc_component_write(component, WM8958_MICBIAS1 + i,
pdata->micbias[i] & 0xffff);
}
}
}
/**
* wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
*
* @component: WM8994 component
* @jack: jack to report detection events on
* @micbias: microphone bias to detect on
*
* Enable microphone detection via IRQ on the WM8994. If GPIOs are
* being used to bring out signals to the processor then only platform
* data configuration is needed for WM8994 and processor GPIOs should
* be configured using snd_soc_jack_add_gpios() instead.
*
* Configuration of detection levels is available via the micbias1_lvl
* and micbias2_lvl platform data members.
*/
int wm8994_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack,
int micbias)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
struct wm8994_micdet *micdet;
struct wm8994 *control = wm8994->wm8994;
int reg, ret;
if (control->type != WM8994) {
dev_warn(component->dev, "Not a WM8994\n");
return -EINVAL;
}
pm_runtime_get_sync(component->dev);
switch (micbias) {
case 1:
micdet = &wm8994->micdet[0];
if (jack)
ret = snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
else
ret = snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
break;
case 2:
micdet = &wm8994->micdet[1];
if (jack)
ret = snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
else
ret = snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
break;
default:
dev_warn(component->dev, "Invalid MICBIAS %d\n", micbias);
return -EINVAL;
}
if (ret != 0)
dev_warn(component->dev, "Failed to configure MICBIAS%d: %d\n",
micbias, ret);
dev_dbg(component->dev, "Configuring microphone detection on %d %p\n",
micbias, jack);
/* Store the configuration */
micdet->jack = jack;
micdet->detecting = true;
/* If either of the jacks is set up then enable detection */
if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
reg = WM8994_MICD_ENA;
else
reg = 0;
snd_soc_component_update_bits(component, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
/* enable MICDET and MICSHRT deboune */
snd_soc_component_update_bits(component, WM8994_IRQ_DEBOUNCE,
WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK |
WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK,
WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB);
snd_soc_dapm_sync(dapm);
pm_runtime_put(component->dev);
return 0;
}
EXPORT_SYMBOL_GPL(wm8994_mic_detect);
static void wm8994_mic_work(struct work_struct *work)
{
struct wm8994_priv *priv = container_of(work,
struct wm8994_priv,
mic_work.work);
struct regmap *regmap = priv->wm8994->regmap;
struct device *dev = priv->wm8994->dev;
unsigned int reg;
int ret;
int report;
pm_runtime_get_sync(dev);
ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, ®);
if (ret < 0) {
dev_err(dev, "Failed to read microphone status: %d\n",
ret);
pm_runtime_put(dev);
return;
}
dev_dbg(dev, "Microphone status: %x\n", reg);
report = 0;
if (reg & WM8994_MIC1_DET_STS) {
if (priv->micdet[0].detecting)
report = SND_JACK_HEADSET;
}
if (reg & WM8994_MIC1_SHRT_STS) {
if (priv->micdet[0].detecting)
report = SND_JACK_HEADPHONE;
else
report |= SND_JACK_BTN_0;
}
if (report)
priv->micdet[0].detecting = false;
else
priv->micdet[0].detecting = true;
snd_soc_jack_report(priv->micdet[0].jack, report,
SND_JACK_HEADSET | SND_JACK_BTN_0);
report = 0;
if (reg & WM8994_MIC2_DET_STS) {
if (priv->micdet[1].detecting)
report = SND_JACK_HEADSET;
}
if (reg & WM8994_MIC2_SHRT_STS) {
if (priv->micdet[1].detecting)
report = SND_JACK_HEADPHONE;
else
report |= SND_JACK_BTN_0;
}
if (report)
priv->micdet[1].detecting = false;
else
priv->micdet[1].detecting = true;
snd_soc_jack_report(priv->micdet[1].jack, report,
SND_JACK_HEADSET | SND_JACK_BTN_0);
pm_runtime_put(dev);
}
static irqreturn_t wm8994_mic_irq(int irq, void *data)
{
struct wm8994_priv *priv = data;
struct snd_soc_component *component = priv->hubs.component;
#ifndef CONFIG_SND_SOC_WM8994_MODULE
trace_snd_soc_jack_irq(dev_name(component->dev));
#endif
pm_wakeup_event(component->dev, 300);
queue_delayed_work(system_power_efficient_wq,
&priv->mic_work, msecs_to_jiffies(250));
return IRQ_HANDLED;
}
/* Should be called with accdet_lock held */
static void wm1811_micd_stop(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
if (!wm8994->jackdet)
return;
snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1, WM8958_MICD_ENA, 0);
wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_JACK);
if (wm8994->wm8994->pdata.jd_ext_cap)
snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
}
static void wm8958_button_det(struct snd_soc_component *component, u16 status)
{
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
int report;
report = 0;
if (status & 0x4)
report |= SND_JACK_BTN_0;
if (status & 0x8)
report |= SND_JACK_BTN_1;
if (status & 0x10)
report |= SND_JACK_BTN_2;
if (status & 0x20)
report |= SND_JACK_BTN_3;
if (status & 0x40)
report |= SND_JACK_BTN_4;
if (status & 0x80)
report |= SND_JACK_BTN_5;
snd_soc_jack_report(wm8994->micdet[0].jack, report,
wm8994->btn_mask);
}
static void wm8958_open_circuit_work(struct work_struct *work)
{
struct wm8994_priv *wm8994 = container_of(work,
struct wm8994_priv,
open_circuit_work.work);
struct device *dev = wm8994->wm8994->dev;
mutex_lock(&wm8994->accdet_lock);
wm1811_micd_stop(wm8994->hubs.component);
dev_dbg(dev, "Reporting open circuit\n");
wm8994->jack_mic = false;
wm8994->mic_detecting = true;
wm8958_micd_set_rate(wm8994->hubs.component);
snd_soc_jack_report(wm8994->micdet[0].jack, 0,
wm8994->btn_mask |
SND_JACK_HEADSET);
mutex_unlock(&wm8994->accdet_lock);
}
static void wm8958_mic_id(void *data, u16 status)
{
struct snd_soc_component *component = data;
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
/* Either nothing present or just starting detection */
if (!(status & WM8958_MICD_STS)) {
/* If nothing present then clear our statuses */
dev_dbg(component->dev, "Detected open circuit\n");
queue_delayed_work(system_power_efficient_wq,
&wm8994->open_circuit_work,
msecs_to_jiffies(2500));
return;
}
/* If the measurement is showing a high impedence we've got a
* microphone.
*/
if (status & 0x600) {
dev_dbg(component->dev, "Detected microphone\n");
wm8994->mic_detecting = false;
wm8994->jack_mic = true;
wm8958_micd_set_rate(component);
snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
SND_JACK_HEADSET);
}
if (status & 0xfc) {
dev_dbg(component->dev, "Detected headphone\n");
wm8994->mic_detecting = false;
wm8958_micd_set_rate(component);
/* If we have jackdet that will detect removal */
wm1811_micd_stop(component);
snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
SND_JACK_HEADSET);
}
}
/* Deferred mic detection to allow for extra settling time */
static void wm1811_mic_work(struct work_struct *work)
{
struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv,
mic_work.work);
struct wm8994 *control = wm8994->wm8994;
struct snd_soc_component *component = wm8994->hubs.component;
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
pm_runtime_get_sync(component->dev);
/* If required for an external cap force MICBIAS on */
if (control->pdata.jd_ext_cap) {
snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2");
snd_soc_dapm_sync(dapm);
}
mutex_lock(&wm8994->accdet_lock);
dev_dbg(component->dev, "Starting mic detection\n");
/* Use a user-supplied callback if we have one */
if (wm8994->micd_cb) {
wm8994->micd_cb(wm8994->micd_cb_data);
} else {
/*
* Start off measument of microphone impedence to find out
* what's actually there.
*/
wm8994->mic_detecting = true;
wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_MIC);
snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1,
WM8958_MICD_ENA, WM8958_MICD_ENA);
}
mutex_unlock(&wm8994->accdet_lock);
pm_runtime_put(component->dev);
}
static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
{
struct wm8994_priv *wm8994 = data;
struct wm8994 *control = wm8994->wm8994;
struct snd_soc_component *component = wm8994->hubs.component;
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
int reg, delay;
bool present;
pm_runtime_get_sync(component->dev);
cancel_delayed_work_sync(&wm8994->mic_complete_work);
mutex_lock(&wm8994->accdet_lock);
reg = snd_soc_component_read(component, WM1811_JACKDET_CTRL);
if (reg < 0) {
dev_err(component->dev, "Failed to read jack status: %d\n", reg);
mutex_unlock(&wm8994->accdet_lock);
pm_runtime_put(component->dev);
return IRQ_NONE;
}
dev_dbg(component->dev, "JACKDET %x\n", reg);
present = reg & WM1811_JACKDET_LVL;
if (present) {
dev_dbg(component->dev, "Jack detected\n");
wm8958_micd_set_rate(component);
snd_soc_component_update_bits(component, WM8958_MICBIAS2,
WM8958_MICB2_DISCH, 0);
/* Disable debounce while inserted */
snd_soc_component_update_bits(component, WM1811_JACKDET_CTRL,
WM1811_JACKDET_DB, 0);
delay = control->pdata.micdet_delay;
queue_delayed_work(system_power_efficient_wq,
&wm8994->mic_work,
msecs_to_jiffies(delay));
} else {
dev_dbg(component->dev, "Jack not detected\n");
/* Release wm8994->accdet_lock to avoid deadlock:
* cancel_delayed_work_sync() takes wm8994->mic_work internal
* lock and wm1811_mic_work takes wm8994->accdet_lock */
mutex_unlock(&wm8994->accdet_lock);
cancel_delayed_work_sync(&wm8994->mic_work);
mutex_lock(&wm8994->accdet_lock);
snd_soc_component_update_bits(component, WM8958_MICBIAS2,
WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
/* Enable debounce while removed */
snd_soc_component_update_bits(component, WM1811_JACKDET_CTRL,
WM1811_JACKDET_DB, WM1811_JACKDET_DB);
wm8994->mic_detecting = false;
wm8994->jack_mic = false;
snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1,
WM8958_MICD_ENA, 0);
wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_JACK);
}
mutex_unlock(&wm8994->accdet_lock);
/* Turn off MICBIAS if it was on for an external cap */
if (control->pdata.jd_ext_cap && !present)
snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
if (present)
snd_soc_jack_report(wm8994->micdet[0].jack,
SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
else
snd_soc_jack_report(wm8994->micdet[0].jack, 0,
SND_JACK_MECHANICAL | SND_JACK_HEADSET |
wm8994->btn_mask);
/* Since we only report deltas force an update, ensures we
* avoid bootstrapping issues with the core. */
snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0);
pm_runtime_put(component->dev);
return IRQ_HANDLED;
}
static void wm1811_jackdet_bootstrap(struct work_struct *work)
{
struct wm8994_priv *wm8994 = container_of(work,
struct wm8994_priv,
jackdet_bootstrap.work);
wm1811_jackdet_irq(0, wm8994);
}
/**
* wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
*
* @component: WM8958 component
* @jack: jack to report detection events on
* @det_cb: detection callback
* @det_cb_data: data for detection callback
* @id_cb: mic id callback
* @id_cb_data: data for mic id callback
*
* Enable microphone detection functionality for the WM8958. By
* default simple detection which supports the detection of up to 6
* buttons plus video and microphone functionality is supported.
*
* The WM8958 has an advanced jack detection facility which is able to
* support complex accessory detection, especially when used in
* conjunction with external circuitry. In order to provide maximum
* flexiblity a callback is provided which allows a completely custom
* detection algorithm.
*/
int wm8958_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack,
wm1811_micdet_cb det_cb, void *det_cb_data,
wm1811_mic_id_cb id_cb, void *id_cb_data)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
struct wm8994 *control = wm8994->wm8994;
u16 micd_lvl_sel;
switch (control->type) {
case WM1811:
case WM8958:
break;
default:
return -EINVAL;
}
pm_runtime_get_sync(component->dev);
if (jack) {
snd_soc_dapm_force_enable_pin(dapm, "CLK_SYS");
snd_soc_dapm_sync(dapm);
wm8994->micdet[0].jack = jack;
if (det_cb) {
wm8994->micd_cb = det_cb;
wm8994->micd_cb_data = det_cb_data;
} else {
wm8994->mic_detecting = true;
wm8994->jack_mic = false;
}
if (id_cb) {
wm8994->mic_id_cb = id_cb;
wm8994->mic_id_cb_data = id_cb_data;
} else {
wm8994->mic_id_cb = wm8958_mic_id;
wm8994->mic_id_cb_data = component;
}
wm8958_micd_set_rate(component);
/* Detect microphones and short circuits by default */
if (control->pdata.micd_lvl_sel)
micd_lvl_sel = control->pdata.micd_lvl_sel;
else
micd_lvl_sel = 0x41;
wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3 |
SND_JACK_BTN_4 | SND_JACK_BTN_5;
snd_soc_component_update_bits(component, WM8958_MIC_DETECT_2,
WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
WARN_ON(snd_soc_component_get_bias_level(component) > SND_SOC_BIAS_STANDBY);
/*
* If we can use jack detection start off with that,
* otherwise jump straight to microphone detection.
*/
if (wm8994->jackdet) {
/* Disable debounce for the initial detect */
snd_soc_component_update_bits(component, WM1811_JACKDET_CTRL,
WM1811_JACKDET_DB, 0);
snd_soc_component_update_bits(component, WM8958_MICBIAS2,
WM8958_MICB2_DISCH,
WM8958_MICB2_DISCH);
snd_soc_component_update_bits(component, WM8994_LDO_1,
WM8994_LDO1_DISCH, 0);
wm1811_jackdet_set_mode(component,
WM1811_JACKDET_MODE_JACK);
} else {
snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1,
WM8958_MICD_ENA, WM8958_MICD_ENA);
}
} else {
snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1,
WM8958_MICD_ENA, 0);
wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_NONE);
snd_soc_dapm_disable_pin(dapm, "CLK_SYS");
snd_soc_dapm_sync(dapm);
}
pm_runtime_put(component->dev);
return 0;
}
EXPORT_SYMBOL_GPL(wm8958_mic_detect);
static void wm8958_mic_work(struct work_struct *work)
{
struct wm8994_priv *wm8994 = container_of(work,
struct wm8994_priv,
mic_complete_work.work);
struct snd_soc_component *component = wm8994->hubs.component;
pm_runtime_get_sync(component->dev);
mutex_lock(&wm8994->accdet_lock);
wm8994->mic_id_cb(wm8994->mic_id_cb_data, wm8994->mic_status);
mutex_unlock(&wm8994->accdet_lock);
pm_runtime_put(component->dev);
}
static irqreturn_t wm8958_mic_irq(int irq, void *data)
{
struct wm8994_priv *wm8994 = data;
struct snd_soc_component *component = wm8994->hubs.component;
int reg, count, ret, id_delay;
/*
* Jack detection may have detected a removal simulataneously
* with an update of the MICDET status; if so it will have
* stopped detection and we can ignore this interrupt.
*/
if (!(snd_soc_component_read(component, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
return IRQ_HANDLED;
cancel_delayed_work_sync(&wm8994->mic_complete_work);
cancel_delayed_work_sync(&wm8994->open_circuit_work);
pm_runtime_get_sync(component->dev);
/* We may occasionally read a detection without an impedence
* range being provided - if that happens loop again.
*/
count = 10;
do {
reg = snd_soc_component_read(component, WM8958_MIC_DETECT_3);
if (reg < 0) {
dev_err(component->dev,
"Failed to read mic detect status: %d\n",
reg);
pm_runtime_put(component->dev);
return IRQ_NONE;
}
if (!(reg & WM8958_MICD_VALID)) {
dev_dbg(component->dev, "Mic detect data not valid\n");
goto out;
}
if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
break;
msleep(1);
} while (count--);
if (count == 0)
dev_warn(component->dev, "No impedance range reported for jack\n");
#ifndef CONFIG_SND_SOC_WM8994_MODULE
trace_snd_soc_jack_irq(dev_name(component->dev));
#endif
/* Avoid a transient report when the accessory is being removed */
if (wm8994->jackdet) {
ret = snd_soc_component_read(component, WM1811_JACKDET_CTRL);
if (ret < 0) {
dev_err(component->dev, "Failed to read jack status: %d\n",
ret);
} else if (!(ret & WM1811_JACKDET_LVL)) {
dev_dbg(component->dev, "Ignoring removed jack\n");
goto out;
}
} else if (!(reg & WM8958_MICD_STS)) {
snd_soc_jack_report(wm8994->micdet[0].jack, 0,
SND_JACK_MECHANICAL | SND_JACK_HEADSET |
wm8994->btn_mask);
wm8994->mic_detecting = true;
goto out;
}
wm8994->mic_status = reg;
id_delay = wm8994->wm8994->pdata.mic_id_delay;
if (wm8994->mic_detecting)
queue_delayed_work(system_power_efficient_wq,
&wm8994->mic_complete_work,
msecs_to_jiffies(id_delay));
else
wm8958_button_det(component, reg);
out:
pm_runtime_put(component->dev);
return IRQ_HANDLED;
}
static irqreturn_t wm8994_fifo_error(int irq, void *data)
{
struct snd_soc_component *component = data;
dev_err(component->dev, "FIFO error\n");
return IRQ_HANDLED;
}
static irqreturn_t wm8994_temp_warn(int irq, void *data)
{
struct snd_soc_component *component = data;
dev_err(component->dev, "Thermal warning\n");
return IRQ_HANDLED;
}
static irqreturn_t wm8994_temp_shut(int irq, void *data)
{
struct snd_soc_component *component = data;
dev_crit(component->dev, "Thermal shutdown\n");
return IRQ_HANDLED;
}
static int wm8994_component_probe(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct wm8994 *control = dev_get_drvdata(component->dev->parent);
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
unsigned int reg;
int ret, i;
snd_soc_component_init_regmap(component, control->regmap);
wm8994->hubs.component = component;
mutex_init(&wm8994->accdet_lock);
INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap,
wm1811_jackdet_bootstrap);
INIT_DELAYED_WORK(&wm8994->open_circuit_work,
wm8958_open_circuit_work);
switch (control->type) {
case WM8994:
INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
break;
case WM1811:
INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work);
break;
default:
break;
}
INIT_DELAYED_WORK(&wm8994->mic_complete_work, wm8958_mic_work);
for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
init_completion(&wm8994->fll_locked[i]);
wm8994->micdet_irq = control->pdata.micdet_irq;
/* By default use idle_bias_off, will override for WM8994 */
dapm->idle_bias_off = 1;
/* Set revision-specific configuration */
switch (control->type) {
case WM8994:
/* Single ended line outputs should have VMID on. */
if (!control->pdata.lineout1_diff ||
!control->pdata.lineout2_diff)
dapm->idle_bias_off = 0;
switch (control->revision) {
case 2:
case 3:
wm8994->hubs.dcs_codes_l = -5;
wm8994->hubs.dcs_codes_r = -5;
wm8994->hubs.hp_startup_mode = 1;
wm8994->hubs.dcs_readback_mode = 1;
wm8994->hubs.series_startup = 1;
break;
default:
wm8994->hubs.dcs_readback_mode = 2;
break;
}
wm8994->hubs.micd_scthr = true;
break;
case WM8958:
wm8994->hubs.dcs_readback_mode = 1;
wm8994->hubs.hp_startup_mode = 1;
wm8994->hubs.micd_scthr = true;
switch (control->revision) {
case 0:
break;
default:
wm8994->fll_byp = true;
break;
}
break;
case WM1811:
wm8994->hubs.dcs_readback_mode = 2;
wm8994->hubs.no_series_update = 1;
wm8994->hubs.hp_startup_mode = 1;
wm8994->hubs.no_cache_dac_hp_direct = true;
wm8994->fll_byp = true;
wm8994->hubs.dcs_codes_l = -9;
wm8994->hubs.dcs_codes_r = -7;
snd_soc_component_update_bits(component, WM8994_ANALOGUE_HP_1,
WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
break;
default:
break;
}
wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
wm8994_fifo_error, "FIFO error", component);
wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
wm8994_temp_warn, "Thermal warning", component);
wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
wm8994_temp_shut, "Thermal shutdown", component);
switch (control->type) {
case WM8994:
if (wm8994->micdet_irq)
ret = request_threaded_irq(wm8994->micdet_irq, NULL,
wm8994_mic_irq,
IRQF_TRIGGER_RISING |
IRQF_ONESHOT,
"Mic1 detect",
wm8994);
else
ret = wm8994_request_irq(wm8994->wm8994,
WM8994_IRQ_MIC1_DET,
wm8994_mic_irq, "Mic 1 detect",
wm8994);
if (ret != 0)
dev_warn(component->dev,
"Failed to request Mic1 detect IRQ: %d\n",
ret);
ret = wm8994_request_irq(wm8994->wm8994,
WM8994_IRQ_MIC1_SHRT,
wm8994_mic_irq, "Mic 1 short",
wm8994);
if (ret != 0)
dev_warn(component->dev,
"Failed to request Mic1 short IRQ: %d\n",
ret);
ret = wm8994_request_irq(wm8994->wm8994,
WM8994_IRQ_MIC2_DET,
wm8994_mic_irq, "Mic 2 detect",
wm8994);
if (ret != 0)
dev_warn(component->dev,
"Failed to request Mic2 detect IRQ: %d\n",
ret);
ret = wm8994_request_irq(wm8994->wm8994,
WM8994_IRQ_MIC2_SHRT,
wm8994_mic_irq, "Mic 2 short",
wm8994);
if (ret != 0)
dev_warn(component->dev,
"Failed to request Mic2 short IRQ: %d\n",
ret);
break;
case WM8958:
case WM1811:
if (wm8994->micdet_irq) {
ret = request_threaded_irq(wm8994->micdet_irq, NULL,
wm8958_mic_irq,
IRQF_TRIGGER_RISING |
IRQF_ONESHOT,
"Mic detect",
wm8994);
if (ret != 0)
dev_warn(component->dev,
"Failed to request Mic detect IRQ: %d\n",
ret);
} else {
wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
wm8958_mic_irq, "Mic detect",
wm8994);
}
}
switch (control->type) {
case WM1811:
if (control->cust_id > 1 || control->revision > 1) {
ret = wm8994_request_irq(wm8994->wm8994,
WM8994_IRQ_GPIO(6),
wm1811_jackdet_irq, "JACKDET",
wm8994);
if (ret == 0)
wm8994->jackdet = true;
}
break;
default:
break;
}
wm8994->fll_locked_irq = true;
for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
ret = wm8994_request_irq(wm8994->wm8994,
WM8994_IRQ_FLL1_LOCK + i,
wm8994_fll_locked_irq, "FLL lock",
&wm8994->fll_locked[i]);
if (ret != 0)
wm8994->fll_locked_irq = false;
}
/* Make sure we can read from the GPIOs if they're inputs */
pm_runtime_get_sync(component->dev);
/* Remember if AIFnLRCLK is configured as a GPIO. This should be
* configured on init - if a system wants to do this dynamically
* at runtime we can deal with that then.
*/
ret = regmap_read(control->regmap, WM8994_GPIO_1, ®);
if (ret < 0) {
dev_err(component->dev, "Failed to read GPIO1 state: %d\n", ret);
goto err_irq;
}
if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
wm8994->lrclk_shared[0] = 1;
wm8994_dai[0].symmetric_rate = 1;
} else {
wm8994->lrclk_shared[0] = 0;
}
ret = regmap_read(control->regmap, WM8994_GPIO_6, ®);
if (ret < 0) {
dev_err(component->dev, "Failed to read GPIO6 state: %d\n", ret);
goto err_irq;
}
if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
wm8994->lrclk_shared[1] = 1;
wm8994_dai[1].symmetric_rate = 1;
} else {
wm8994->lrclk_shared[1] = 0;
}
pm_runtime_put(component->dev);
/* Latch volume update bits */
for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
snd_soc_component_update_bits(component, wm8994_vu_bits[i].reg,
wm8994_vu_bits[i].mask,
wm8994_vu_bits[i].mask);
if (control->type != WM1811) {
for (i = 0; i < ARRAY_SIZE(wm8994_adc2_dac2_vu_bits); i++)
snd_soc_component_update_bits(component,
wm8994_adc2_dac2_vu_bits[i].reg,
wm8994_adc2_dac2_vu_bits[i].mask,
wm8994_adc2_dac2_vu_bits[i].mask);
}
/* Set the low bit of the 3D stereo depth so TLV matches */
snd_soc_component_update_bits(component, WM8994_AIF1_DAC1_FILTERS_2,
1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
snd_soc_component_update_bits(component, WM8994_AIF1_DAC2_FILTERS_2,
1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
snd_soc_component_update_bits(component, WM8994_AIF2_DAC_FILTERS_2,
1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
/* Unconditionally enable AIF1 ADC TDM mode on chips which can
* use this; it only affects behaviour on idle TDM clock
* cycles. */
switch (control->type) {
case WM8994:
case WM8958:
snd_soc_component_update_bits(component, WM8994_AIF1_CONTROL_1,
WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
break;
default:
break;
}
/* Put MICBIAS into bypass mode by default on newer devices */
switch (control->type) {
case WM8958:
case WM1811:
snd_soc_component_update_bits(component, WM8958_MICBIAS1,
WM8958_MICB1_MODE, WM8958_MICB1_MODE);
snd_soc_component_update_bits(component, WM8958_MICBIAS2,
WM8958_MICB2_MODE, WM8958_MICB2_MODE);
break;
default:
break;
}
wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
wm_hubs_update_class_w(component);
wm8994_handle_pdata(wm8994);
wm_hubs_add_analogue_controls(component);
snd_soc_add_component_controls(component, wm8994_common_snd_controls,
ARRAY_SIZE(wm8994_common_snd_controls));
snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
ARRAY_SIZE(wm8994_dapm_widgets));
switch (control->type) {
case WM8994:
snd_soc_add_component_controls(component, wm8994_snd_controls,
ARRAY_SIZE(wm8994_snd_controls));
snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
ARRAY_SIZE(wm8994_specific_dapm_widgets));
if (control->revision < 4) {
snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
ARRAY_SIZE(wm8994_lateclk_revd_widgets));
snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
ARRAY_SIZE(wm8994_adc_revd_widgets));
snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
ARRAY_SIZE(wm8994_dac_revd_widgets));
} else {
snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
ARRAY_SIZE(wm8994_lateclk_widgets));
snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
ARRAY_SIZE(wm8994_adc_widgets));
snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
ARRAY_SIZE(wm8994_dac_widgets));
}
break;
case WM8958:
snd_soc_add_component_controls(component, wm8994_snd_controls,
ARRAY_SIZE(wm8994_snd_controls));
snd_soc_add_component_controls(component, wm8958_snd_controls,
ARRAY_SIZE(wm8958_snd_controls));
snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
ARRAY_SIZE(wm8958_dapm_widgets));
if (control->revision < 1) {
snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
ARRAY_SIZE(wm8994_lateclk_revd_widgets));
snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
ARRAY_SIZE(wm8994_adc_revd_widgets));
snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
ARRAY_SIZE(wm8994_dac_revd_widgets));
} else {
snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
ARRAY_SIZE(wm8994_lateclk_widgets));
snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
ARRAY_SIZE(wm8994_adc_widgets));
snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
ARRAY_SIZE(wm8994_dac_widgets));
}
break;
case WM1811:
snd_soc_add_component_controls(component, wm8958_snd_controls,
ARRAY_SIZE(wm8958_snd_controls));
snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
ARRAY_SIZE(wm8958_dapm_widgets));
snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
ARRAY_SIZE(wm8994_lateclk_widgets));
snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
ARRAY_SIZE(wm8994_adc_widgets));
snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
ARRAY_SIZE(wm8994_dac_widgets));
break;
}
wm_hubs_add_analogue_routes(component, 0, 0);
ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
wm_hubs_dcs_done, "DC servo done",
&wm8994->hubs);
if (ret == 0)
wm8994->hubs.dcs_done_irq = true;
snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
switch (control->type) {
case WM8994:
snd_soc_dapm_add_routes(dapm, wm8994_intercon,
ARRAY_SIZE(wm8994_intercon));
if (control->revision < 4) {
snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
ARRAY_SIZE(wm8994_revd_intercon));
snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
ARRAY_SIZE(wm8994_lateclk_revd_intercon));
} else {
snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
ARRAY_SIZE(wm8994_lateclk_intercon));
}
break;
case WM8958:
if (control->revision < 1) {
snd_soc_dapm_add_routes(dapm, wm8994_intercon,
ARRAY_SIZE(wm8994_intercon));
snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
ARRAY_SIZE(wm8994_revd_intercon));
snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
ARRAY_SIZE(wm8994_lateclk_revd_intercon));
} else {
snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
ARRAY_SIZE(wm8994_lateclk_intercon));
snd_soc_dapm_add_routes(dapm, wm8958_intercon,
ARRAY_SIZE(wm8958_intercon));
}
wm8958_dsp2_init(component);
break;
case WM1811:
snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
ARRAY_SIZE(wm8994_lateclk_intercon));
snd_soc_dapm_add_routes(dapm, wm8958_intercon,
ARRAY_SIZE(wm8958_intercon));
break;
}
return 0;
err_irq:
if (wm8994->jackdet)
wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
if (wm8994->micdet_irq)
free_irq(wm8994->micdet_irq, wm8994);
for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
&wm8994->fll_locked[i]);
wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
&wm8994->hubs);
wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, component);
wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, component);
wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, component);
return ret;
}
static void wm8994_component_remove(struct snd_soc_component *component)
{
struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
struct wm8994 *control = wm8994->wm8994;
int i;
for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
&wm8994->fll_locked[i]);
wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
&wm8994->hubs);
wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, component);
wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, component);
wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, component);
if (wm8994->jackdet)
wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
switch (control->type) {
case WM8994:
if (wm8994->micdet_irq)
free_irq(wm8994->micdet_irq, wm8994);
wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
wm8994);
wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
wm8994);
wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
wm8994);
break;
case WM1811:
case WM8958:
if (wm8994->micdet_irq)
free_irq(wm8994->micdet_irq, wm8994);
break;
}
release_firmware(wm8994->mbc);
release_firmware(wm8994->mbc_vss);
release_firmware(wm8994->enh_eq);
kfree(wm8994->retune_mobile_texts);
}
static const struct snd_soc_component_driver soc_component_dev_wm8994 = {
.probe = wm8994_component_probe,
.remove = wm8994_component_remove,
.suspend = wm8994_component_suspend,
.resume = wm8994_component_resume,
.set_bias_level = wm8994_set_bias_level,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int wm8994_probe(struct platform_device *pdev)
{
struct wm8994_priv *wm8994;
int ret;
wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
GFP_KERNEL);
if (wm8994 == NULL)
return -ENOMEM;
platform_set_drvdata(pdev, wm8994);
mutex_init(&wm8994->fw_lock);
wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
wm8994->mclk[WM8994_MCLK1].id = "MCLK1";
wm8994->mclk[WM8994_MCLK2].id = "MCLK2";
ret = devm_clk_bulk_get_optional(pdev->dev.parent, ARRAY_SIZE(wm8994->mclk),
wm8994->mclk);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to get clocks: %d\n", ret);
return ret;
}
pm_runtime_enable(&pdev->dev);
pm_runtime_idle(&pdev->dev);
ret = devm_snd_soc_register_component(&pdev->dev, &soc_component_dev_wm8994,
wm8994_dai, ARRAY_SIZE(wm8994_dai));
if (ret < 0)
pm_runtime_disable(&pdev->dev);
return ret;
}
static void wm8994_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
}
#ifdef CONFIG_PM_SLEEP
static int wm8994_suspend(struct device *dev)
{
struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
/* Drop down to power saving mode when system is suspended */
if (wm8994->jackdet && !wm8994->active_refcount)
regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
WM1811_JACKDET_MODE_MASK,
wm8994->jackdet_mode);
return 0;
}
static int wm8994_resume(struct device *dev)
{
struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
if (wm8994->jackdet && wm8994->jackdet_mode)
regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
WM1811_JACKDET_MODE_MASK,
WM1811_JACKDET_MODE_AUDIO);
return 0;
}
#endif
static const struct dev_pm_ops wm8994_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
};
static struct platform_driver wm8994_codec_driver = {
.driver = {
.name = "wm8994-codec",
.pm = &wm8994_pm_ops,
},
.probe = wm8994_probe,
.remove_new = wm8994_remove,
};
module_platform_driver(wm8994_codec_driver);
MODULE_DESCRIPTION("ASoC WM8994 driver");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:wm8994-codec");
| linux-master | sound/soc/codecs/wm8994.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* da7219-aad.c - Dialog DA7219 ALSA SoC AAD Driver
*
* Copyright (c) 2015 Dialog Semiconductor Ltd.
*
* Author: Adam Thomson <[email protected]>
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/i2c.h>
#include <linux/property.h>
#include <linux/pm_wakeirq.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/workqueue.h>
#include <sound/soc.h>
#include <sound/jack.h>
#include <sound/da7219.h>
#include "da7219.h"
#include "da7219-aad.h"
/*
* Detection control
*/
void da7219_aad_jack_det(struct snd_soc_component *component, struct snd_soc_jack *jack)
{
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
da7219->aad->jack = jack;
da7219->aad->jack_inserted = false;
/* Send an initial empty report */
snd_soc_jack_report(jack, 0, DA7219_AAD_REPORT_ALL_MASK);
/* Enable/Disable jack detection */
snd_soc_component_update_bits(component, DA7219_ACCDET_CONFIG_1,
DA7219_ACCDET_EN_MASK,
(jack ? DA7219_ACCDET_EN_MASK : 0));
}
/*
* Button/HPTest work
*/
static void da7219_aad_btn_det_work(struct work_struct *work)
{
struct da7219_aad_priv *da7219_aad =
container_of(work, struct da7219_aad_priv, btn_det_work);
struct snd_soc_component *component = da7219_aad->component;
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
u8 statusa, micbias_ctrl;
bool micbias_up = false;
int retries = 0;
/* Disable ground switch */
snd_soc_component_update_bits(component, 0xFB, 0x01, 0x00);
/* Drive headphones/lineout */
snd_soc_component_update_bits(component, DA7219_HP_L_CTRL,
DA7219_HP_L_AMP_OE_MASK,
DA7219_HP_L_AMP_OE_MASK);
snd_soc_component_update_bits(component, DA7219_HP_R_CTRL,
DA7219_HP_R_AMP_OE_MASK,
DA7219_HP_R_AMP_OE_MASK);
/* Make sure mic bias is up */
snd_soc_dapm_force_enable_pin(dapm, "Mic Bias");
snd_soc_dapm_sync(dapm);
do {
statusa = snd_soc_component_read(component, DA7219_ACCDET_STATUS_A);
if (statusa & DA7219_MICBIAS_UP_STS_MASK)
micbias_up = true;
else if (retries++ < DA7219_AAD_MICBIAS_CHK_RETRIES)
msleep(DA7219_AAD_MICBIAS_CHK_DELAY);
} while ((!micbias_up) && (retries < DA7219_AAD_MICBIAS_CHK_RETRIES));
if (retries >= DA7219_AAD_MICBIAS_CHK_RETRIES)
dev_warn(component->dev, "Mic bias status check timed out");
da7219->micbias_on_event = true;
/*
* Mic bias pulse required to enable mic, must be done before enabling
* button detection to prevent erroneous button readings.
*/
if (da7219_aad->micbias_pulse_lvl && da7219_aad->micbias_pulse_time) {
/* Pulse higher level voltage */
micbias_ctrl = snd_soc_component_read(component, DA7219_MICBIAS_CTRL);
snd_soc_component_update_bits(component, DA7219_MICBIAS_CTRL,
DA7219_MICBIAS1_LEVEL_MASK,
da7219_aad->micbias_pulse_lvl);
msleep(da7219_aad->micbias_pulse_time);
snd_soc_component_write(component, DA7219_MICBIAS_CTRL, micbias_ctrl);
}
snd_soc_component_update_bits(component, DA7219_ACCDET_CONFIG_1,
DA7219_BUTTON_CONFIG_MASK,
da7219_aad->btn_cfg);
}
static void da7219_aad_hptest_work(struct work_struct *work)
{
struct da7219_aad_priv *da7219_aad =
container_of(work, struct da7219_aad_priv, hptest_work);
struct snd_soc_component *component = da7219_aad->component;
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
__le16 tonegen_freq_hptest;
u8 pll_srm_sts, pll_ctrl, gain_ramp_ctrl, accdet_cfg8;
int report = 0, ret;
/* Lock DAPM, Kcontrols affected by this test and the PLL */
snd_soc_dapm_mutex_lock(dapm);
mutex_lock(&da7219->ctrl_lock);
mutex_lock(&da7219->pll_lock);
/* Ensure MCLK is available for HP test procedure */
if (da7219->mclk) {
ret = clk_prepare_enable(da7219->mclk);
if (ret) {
dev_err(component->dev, "Failed to enable mclk - %d\n", ret);
mutex_unlock(&da7219->pll_lock);
mutex_unlock(&da7219->ctrl_lock);
snd_soc_dapm_mutex_unlock(dapm);
return;
}
}
/*
* If MCLK not present, then we're using the internal oscillator and
* require different frequency settings to achieve the same result.
*
* If MCLK is present, but PLL is not enabled then we enable it here to
* ensure a consistent detection procedure.
*/
pll_srm_sts = snd_soc_component_read(component, DA7219_PLL_SRM_STS);
if (pll_srm_sts & DA7219_PLL_SRM_STS_MCLK) {
tonegen_freq_hptest = cpu_to_le16(DA7219_AAD_HPTEST_RAMP_FREQ);
pll_ctrl = snd_soc_component_read(component, DA7219_PLL_CTRL);
if ((pll_ctrl & DA7219_PLL_MODE_MASK) == DA7219_PLL_MODE_BYPASS)
da7219_set_pll(component, DA7219_SYSCLK_PLL,
DA7219_PLL_FREQ_OUT_98304);
} else {
tonegen_freq_hptest = cpu_to_le16(DA7219_AAD_HPTEST_RAMP_FREQ_INT_OSC);
}
/* Disable ground switch */
snd_soc_component_update_bits(component, 0xFB, 0x01, 0x00);
/* Ensure gain ramping at fastest rate */
gain_ramp_ctrl = snd_soc_component_read(component, DA7219_GAIN_RAMP_CTRL);
snd_soc_component_write(component, DA7219_GAIN_RAMP_CTRL, DA7219_GAIN_RAMP_RATE_X8);
/* Bypass cache so it saves current settings */
regcache_cache_bypass(da7219->regmap, true);
/* Make sure Tone Generator is disabled */
snd_soc_component_write(component, DA7219_TONE_GEN_CFG1, 0);
/* Enable HPTest block, 1KOhms check */
snd_soc_component_update_bits(component, DA7219_ACCDET_CONFIG_8,
DA7219_HPTEST_EN_MASK | DA7219_HPTEST_RES_SEL_MASK,
DA7219_HPTEST_EN_MASK |
DA7219_HPTEST_RES_SEL_1KOHMS);
/* Set gains to 0db */
snd_soc_component_write(component, DA7219_DAC_L_GAIN, DA7219_DAC_DIGITAL_GAIN_0DB);
snd_soc_component_write(component, DA7219_DAC_R_GAIN, DA7219_DAC_DIGITAL_GAIN_0DB);
snd_soc_component_write(component, DA7219_HP_L_GAIN, DA7219_HP_AMP_GAIN_0DB);
snd_soc_component_write(component, DA7219_HP_R_GAIN, DA7219_HP_AMP_GAIN_0DB);
/* Disable DAC filters, EQs and soft mute */
snd_soc_component_update_bits(component, DA7219_DAC_FILTERS1, DA7219_HPF_MODE_MASK,
0);
snd_soc_component_update_bits(component, DA7219_DAC_FILTERS4, DA7219_DAC_EQ_EN_MASK,
0);
snd_soc_component_update_bits(component, DA7219_DAC_FILTERS5,
DA7219_DAC_SOFTMUTE_EN_MASK, 0);
/* Enable HP left & right paths */
snd_soc_component_update_bits(component, DA7219_CP_CTRL, DA7219_CP_EN_MASK,
DA7219_CP_EN_MASK);
snd_soc_component_update_bits(component, DA7219_DIG_ROUTING_DAC,
DA7219_DAC_L_SRC_MASK | DA7219_DAC_R_SRC_MASK,
DA7219_DAC_L_SRC_TONEGEN |
DA7219_DAC_R_SRC_TONEGEN);
snd_soc_component_update_bits(component, DA7219_DAC_L_CTRL,
DA7219_DAC_L_EN_MASK | DA7219_DAC_L_MUTE_EN_MASK,
DA7219_DAC_L_EN_MASK);
snd_soc_component_update_bits(component, DA7219_DAC_R_CTRL,
DA7219_DAC_R_EN_MASK | DA7219_DAC_R_MUTE_EN_MASK,
DA7219_DAC_R_EN_MASK);
snd_soc_component_update_bits(component, DA7219_MIXOUT_L_SELECT,
DA7219_MIXOUT_L_MIX_SELECT_MASK,
DA7219_MIXOUT_L_MIX_SELECT_MASK);
snd_soc_component_update_bits(component, DA7219_MIXOUT_R_SELECT,
DA7219_MIXOUT_R_MIX_SELECT_MASK,
DA7219_MIXOUT_R_MIX_SELECT_MASK);
snd_soc_component_update_bits(component, DA7219_DROUTING_ST_OUTFILT_1L,
DA7219_OUTFILT_ST_1L_SRC_MASK,
DA7219_DMIX_ST_SRC_OUTFILT1L);
snd_soc_component_update_bits(component, DA7219_DROUTING_ST_OUTFILT_1R,
DA7219_OUTFILT_ST_1R_SRC_MASK,
DA7219_DMIX_ST_SRC_OUTFILT1R);
snd_soc_component_update_bits(component, DA7219_MIXOUT_L_CTRL,
DA7219_MIXOUT_L_AMP_EN_MASK,
DA7219_MIXOUT_L_AMP_EN_MASK);
snd_soc_component_update_bits(component, DA7219_MIXOUT_R_CTRL,
DA7219_MIXOUT_R_AMP_EN_MASK,
DA7219_MIXOUT_R_AMP_EN_MASK);
snd_soc_component_update_bits(component, DA7219_HP_L_CTRL,
DA7219_HP_L_AMP_OE_MASK | DA7219_HP_L_AMP_EN_MASK,
DA7219_HP_L_AMP_OE_MASK | DA7219_HP_L_AMP_EN_MASK);
snd_soc_component_update_bits(component, DA7219_HP_R_CTRL,
DA7219_HP_R_AMP_OE_MASK | DA7219_HP_R_AMP_EN_MASK,
DA7219_HP_R_AMP_OE_MASK | DA7219_HP_R_AMP_EN_MASK);
msleep(DA7219_SETTLING_DELAY);
snd_soc_component_update_bits(component, DA7219_HP_L_CTRL,
DA7219_HP_L_AMP_MUTE_EN_MASK |
DA7219_HP_L_AMP_MIN_GAIN_EN_MASK, 0);
snd_soc_component_update_bits(component, DA7219_HP_R_CTRL,
DA7219_HP_R_AMP_MUTE_EN_MASK |
DA7219_HP_R_AMP_MIN_GAIN_EN_MASK, 0);
/*
* If we're running from the internal oscillator then give audio paths
* time to settle before running test.
*/
if (!(pll_srm_sts & DA7219_PLL_SRM_STS_MCLK))
msleep(DA7219_AAD_HPTEST_INT_OSC_PATH_DELAY);
/* Configure & start Tone Generator */
snd_soc_component_write(component, DA7219_TONE_GEN_ON_PER, DA7219_BEEP_ON_PER_MASK);
regmap_raw_write(da7219->regmap, DA7219_TONE_GEN_FREQ1_L,
&tonegen_freq_hptest, sizeof(tonegen_freq_hptest));
snd_soc_component_update_bits(component, DA7219_TONE_GEN_CFG2,
DA7219_SWG_SEL_MASK | DA7219_TONE_GEN_GAIN_MASK,
DA7219_SWG_SEL_SRAMP |
DA7219_TONE_GEN_GAIN_MINUS_15DB);
snd_soc_component_write(component, DA7219_TONE_GEN_CFG1, DA7219_START_STOPN_MASK);
msleep(DA7219_AAD_HPTEST_PERIOD);
/* Grab comparator reading */
accdet_cfg8 = snd_soc_component_read(component, DA7219_ACCDET_CONFIG_8);
if (accdet_cfg8 & DA7219_HPTEST_COMP_MASK)
report |= SND_JACK_HEADPHONE;
else
report |= SND_JACK_LINEOUT;
/* Stop tone generator */
snd_soc_component_write(component, DA7219_TONE_GEN_CFG1, 0);
msleep(DA7219_AAD_HPTEST_PERIOD);
/* Restore original settings from cache */
regcache_mark_dirty(da7219->regmap);
regcache_sync_region(da7219->regmap, DA7219_HP_L_CTRL,
DA7219_HP_R_CTRL);
msleep(DA7219_SETTLING_DELAY);
regcache_sync_region(da7219->regmap, DA7219_MIXOUT_L_CTRL,
DA7219_MIXOUT_R_CTRL);
regcache_sync_region(da7219->regmap, DA7219_DROUTING_ST_OUTFILT_1L,
DA7219_DROUTING_ST_OUTFILT_1R);
regcache_sync_region(da7219->regmap, DA7219_MIXOUT_L_SELECT,
DA7219_MIXOUT_R_SELECT);
regcache_sync_region(da7219->regmap, DA7219_DAC_L_CTRL,
DA7219_DAC_R_CTRL);
regcache_sync_region(da7219->regmap, DA7219_DIG_ROUTING_DAC,
DA7219_DIG_ROUTING_DAC);
regcache_sync_region(da7219->regmap, DA7219_CP_CTRL, DA7219_CP_CTRL);
regcache_sync_region(da7219->regmap, DA7219_DAC_FILTERS5,
DA7219_DAC_FILTERS5);
regcache_sync_region(da7219->regmap, DA7219_DAC_FILTERS4,
DA7219_DAC_FILTERS1);
regcache_sync_region(da7219->regmap, DA7219_HP_L_GAIN,
DA7219_HP_R_GAIN);
regcache_sync_region(da7219->regmap, DA7219_DAC_L_GAIN,
DA7219_DAC_R_GAIN);
regcache_sync_region(da7219->regmap, DA7219_TONE_GEN_ON_PER,
DA7219_TONE_GEN_ON_PER);
regcache_sync_region(da7219->regmap, DA7219_TONE_GEN_FREQ1_L,
DA7219_TONE_GEN_FREQ1_U);
regcache_sync_region(da7219->regmap, DA7219_TONE_GEN_CFG1,
DA7219_TONE_GEN_CFG2);
regcache_cache_bypass(da7219->regmap, false);
/* Disable HPTest block */
snd_soc_component_update_bits(component, DA7219_ACCDET_CONFIG_8,
DA7219_HPTEST_EN_MASK, 0);
/*
* If we're running from the internal oscillator then give audio paths
* time to settle before allowing headphones to be driven as required.
*/
if (!(pll_srm_sts & DA7219_PLL_SRM_STS_MCLK))
msleep(DA7219_AAD_HPTEST_INT_OSC_PATH_DELAY);
/* Restore gain ramping rate */
snd_soc_component_write(component, DA7219_GAIN_RAMP_CTRL, gain_ramp_ctrl);
/* Drive Headphones/lineout */
snd_soc_component_update_bits(component, DA7219_HP_L_CTRL, DA7219_HP_L_AMP_OE_MASK,
DA7219_HP_L_AMP_OE_MASK);
snd_soc_component_update_bits(component, DA7219_HP_R_CTRL, DA7219_HP_R_AMP_OE_MASK,
DA7219_HP_R_AMP_OE_MASK);
/* Restore PLL to previous configuration, if re-configured */
if ((pll_srm_sts & DA7219_PLL_SRM_STS_MCLK) &&
((pll_ctrl & DA7219_PLL_MODE_MASK) == DA7219_PLL_MODE_BYPASS))
da7219_set_pll(component, DA7219_SYSCLK_MCLK, 0);
/* Remove MCLK, if previously enabled */
if (da7219->mclk)
clk_disable_unprepare(da7219->mclk);
mutex_unlock(&da7219->pll_lock);
mutex_unlock(&da7219->ctrl_lock);
snd_soc_dapm_mutex_unlock(dapm);
/*
* Only send report if jack hasn't been removed during process,
* otherwise it's invalid and we drop it.
*/
if (da7219_aad->jack_inserted)
snd_soc_jack_report(da7219_aad->jack, report,
SND_JACK_HEADSET | SND_JACK_LINEOUT);
}
static void da7219_aad_jack_det_work(struct work_struct *work)
{
struct da7219_aad_priv *da7219_aad =
container_of(work, struct da7219_aad_priv, jack_det_work.work);
struct snd_soc_component *component = da7219_aad->component;
/* Enable ground switch */
snd_soc_component_update_bits(component, 0xFB, 0x01, 0x01);
}
/*
* IRQ
*/
static irqreturn_t da7219_aad_irq_thread(int irq, void *data)
{
struct da7219_aad_priv *da7219_aad = data;
struct snd_soc_component *component = da7219_aad->component;
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
u8 events[DA7219_AAD_IRQ_REG_MAX];
u8 statusa;
int i, ret, report = 0, mask = 0;
/* Read current IRQ events */
ret = regmap_bulk_read(da7219->regmap, DA7219_ACCDET_IRQ_EVENT_A,
events, DA7219_AAD_IRQ_REG_MAX);
if (ret) {
dev_warn_ratelimited(component->dev, "Failed to read IRQ events: %d\n", ret);
return IRQ_NONE;
}
if (!events[DA7219_AAD_IRQ_REG_A] && !events[DA7219_AAD_IRQ_REG_B])
return IRQ_NONE;
/* Read status register for jack insertion & type status */
statusa = snd_soc_component_read(component, DA7219_ACCDET_STATUS_A);
if (events[DA7219_AAD_IRQ_REG_A] & DA7219_E_JACK_INSERTED_MASK) {
u8 srm_st;
int delay = 0;
srm_st = snd_soc_component_read(component,
DA7219_PLL_SRM_STS) & DA7219_PLL_SRM_STS_MCLK;
delay = (da7219_aad->gnd_switch_delay * ((srm_st == 0x0) ? 2 : 1) - 2);
queue_delayed_work(da7219_aad->aad_wq,
&da7219_aad->jack_det_work,
msecs_to_jiffies(delay));
}
/* Clear events */
regmap_bulk_write(da7219->regmap, DA7219_ACCDET_IRQ_EVENT_A,
events, DA7219_AAD_IRQ_REG_MAX);
dev_dbg(component->dev, "IRQ events = 0x%x|0x%x, status = 0x%x\n",
events[DA7219_AAD_IRQ_REG_A], events[DA7219_AAD_IRQ_REG_B],
statusa);
if (statusa & DA7219_JACK_INSERTION_STS_MASK) {
/* Jack Insertion */
if (events[DA7219_AAD_IRQ_REG_A] &
DA7219_E_JACK_INSERTED_MASK) {
report |= SND_JACK_MECHANICAL;
mask |= SND_JACK_MECHANICAL;
da7219_aad->jack_inserted = true;
}
/* Jack type detection */
if (events[DA7219_AAD_IRQ_REG_A] &
DA7219_E_JACK_DETECT_COMPLETE_MASK) {
/*
* If 4-pole, then enable button detection, else perform
* HP impedance test to determine output type to report.
*
* We schedule work here as the tasks themselves can
* take time to complete, and in particular for hptest
* we want to be able to check if the jack was removed
* during the procedure as this will invalidate the
* result. By doing this as work, the IRQ thread can
* handle a removal, and we can check at the end of
* hptest if we have a valid result or not.
*/
if (statusa & DA7219_JACK_TYPE_STS_MASK) {
report |= SND_JACK_HEADSET;
mask |= SND_JACK_HEADSET | SND_JACK_LINEOUT;
queue_work(da7219_aad->aad_wq, &da7219_aad->btn_det_work);
} else {
queue_work(da7219_aad->aad_wq, &da7219_aad->hptest_work);
}
}
/* Button support for 4-pole jack */
if (statusa & DA7219_JACK_TYPE_STS_MASK) {
for (i = 0; i < DA7219_AAD_MAX_BUTTONS; ++i) {
/* Button Press */
if (events[DA7219_AAD_IRQ_REG_B] &
(DA7219_E_BUTTON_A_PRESSED_MASK << i)) {
report |= SND_JACK_BTN_0 >> i;
mask |= SND_JACK_BTN_0 >> i;
}
}
snd_soc_jack_report(da7219_aad->jack, report, mask);
for (i = 0; i < DA7219_AAD_MAX_BUTTONS; ++i) {
/* Button Release */
if (events[DA7219_AAD_IRQ_REG_B] &
(DA7219_E_BUTTON_A_RELEASED_MASK >> i)) {
report &= ~(SND_JACK_BTN_0 >> i);
mask |= SND_JACK_BTN_0 >> i;
}
}
}
} else {
/* Jack removal */
if (events[DA7219_AAD_IRQ_REG_A] & DA7219_E_JACK_REMOVED_MASK) {
report = 0;
mask |= DA7219_AAD_REPORT_ALL_MASK;
da7219_aad->jack_inserted = false;
/* Cancel any pending work */
cancel_delayed_work_sync(&da7219_aad->jack_det_work);
cancel_work_sync(&da7219_aad->btn_det_work);
cancel_work_sync(&da7219_aad->hptest_work);
/* Un-drive headphones/lineout */
snd_soc_component_update_bits(component, DA7219_HP_R_CTRL,
DA7219_HP_R_AMP_OE_MASK, 0);
snd_soc_component_update_bits(component, DA7219_HP_L_CTRL,
DA7219_HP_L_AMP_OE_MASK, 0);
/* Ensure button detection disabled */
snd_soc_component_update_bits(component, DA7219_ACCDET_CONFIG_1,
DA7219_BUTTON_CONFIG_MASK, 0);
da7219->micbias_on_event = false;
/* Disable mic bias */
snd_soc_dapm_disable_pin(dapm, "Mic Bias");
snd_soc_dapm_sync(dapm);
/* Disable ground switch */
snd_soc_component_update_bits(component, 0xFB, 0x01, 0x00);
}
}
snd_soc_jack_report(da7219_aad->jack, report, mask);
return IRQ_HANDLED;
}
/*
* DT/ACPI to pdata conversion
*/
static enum da7219_aad_micbias_pulse_lvl
da7219_aad_fw_micbias_pulse_lvl(struct device *dev, u32 val)
{
switch (val) {
case 2800:
return DA7219_AAD_MICBIAS_PULSE_LVL_2_8V;
case 2900:
return DA7219_AAD_MICBIAS_PULSE_LVL_2_9V;
default:
dev_warn(dev, "Invalid micbias pulse level");
return DA7219_AAD_MICBIAS_PULSE_LVL_OFF;
}
}
static enum da7219_aad_btn_cfg
da7219_aad_fw_btn_cfg(struct device *dev, u32 val)
{
switch (val) {
case 2:
return DA7219_AAD_BTN_CFG_2MS;
case 5:
return DA7219_AAD_BTN_CFG_5MS;
case 10:
return DA7219_AAD_BTN_CFG_10MS;
case 50:
return DA7219_AAD_BTN_CFG_50MS;
case 100:
return DA7219_AAD_BTN_CFG_100MS;
case 200:
return DA7219_AAD_BTN_CFG_200MS;
case 500:
return DA7219_AAD_BTN_CFG_500MS;
default:
dev_warn(dev, "Invalid button config");
return DA7219_AAD_BTN_CFG_10MS;
}
}
static enum da7219_aad_mic_det_thr
da7219_aad_fw_mic_det_thr(struct device *dev, u32 val)
{
switch (val) {
case 200:
return DA7219_AAD_MIC_DET_THR_200_OHMS;
case 500:
return DA7219_AAD_MIC_DET_THR_500_OHMS;
case 750:
return DA7219_AAD_MIC_DET_THR_750_OHMS;
case 1000:
return DA7219_AAD_MIC_DET_THR_1000_OHMS;
default:
dev_warn(dev, "Invalid mic detect threshold");
return DA7219_AAD_MIC_DET_THR_500_OHMS;
}
}
static enum da7219_aad_jack_ins_deb
da7219_aad_fw_jack_ins_deb(struct device *dev, u32 val)
{
switch (val) {
case 5:
return DA7219_AAD_JACK_INS_DEB_5MS;
case 10:
return DA7219_AAD_JACK_INS_DEB_10MS;
case 20:
return DA7219_AAD_JACK_INS_DEB_20MS;
case 50:
return DA7219_AAD_JACK_INS_DEB_50MS;
case 100:
return DA7219_AAD_JACK_INS_DEB_100MS;
case 200:
return DA7219_AAD_JACK_INS_DEB_200MS;
case 500:
return DA7219_AAD_JACK_INS_DEB_500MS;
case 1000:
return DA7219_AAD_JACK_INS_DEB_1S;
default:
dev_warn(dev, "Invalid jack insert debounce");
return DA7219_AAD_JACK_INS_DEB_20MS;
}
}
static enum da7219_aad_jack_ins_det_pty
da7219_aad_fw_jack_ins_det_pty(struct device *dev, const char *str)
{
if (!strcmp(str, "low")) {
return DA7219_AAD_JACK_INS_DET_PTY_LOW;
} else if (!strcmp(str, "high")) {
return DA7219_AAD_JACK_INS_DET_PTY_HIGH;
} else {
dev_warn(dev, "Invalid jack insertion detection polarity");
return DA7219_AAD_JACK_INS_DET_PTY_LOW;
}
}
static enum da7219_aad_jack_det_rate
da7219_aad_fw_jack_det_rate(struct device *dev, const char *str)
{
if (!strcmp(str, "32_64")) {
return DA7219_AAD_JACK_DET_RATE_32_64MS;
} else if (!strcmp(str, "64_128")) {
return DA7219_AAD_JACK_DET_RATE_64_128MS;
} else if (!strcmp(str, "128_256")) {
return DA7219_AAD_JACK_DET_RATE_128_256MS;
} else if (!strcmp(str, "256_512")) {
return DA7219_AAD_JACK_DET_RATE_256_512MS;
} else {
dev_warn(dev, "Invalid jack detect rate");
return DA7219_AAD_JACK_DET_RATE_256_512MS;
}
}
static enum da7219_aad_jack_rem_deb
da7219_aad_fw_jack_rem_deb(struct device *dev, u32 val)
{
switch (val) {
case 1:
return DA7219_AAD_JACK_REM_DEB_1MS;
case 5:
return DA7219_AAD_JACK_REM_DEB_5MS;
case 10:
return DA7219_AAD_JACK_REM_DEB_10MS;
case 20:
return DA7219_AAD_JACK_REM_DEB_20MS;
default:
dev_warn(dev, "Invalid jack removal debounce");
return DA7219_AAD_JACK_REM_DEB_1MS;
}
}
static enum da7219_aad_btn_avg
da7219_aad_fw_btn_avg(struct device *dev, u32 val)
{
switch (val) {
case 1:
return DA7219_AAD_BTN_AVG_1;
case 2:
return DA7219_AAD_BTN_AVG_2;
case 4:
return DA7219_AAD_BTN_AVG_4;
case 8:
return DA7219_AAD_BTN_AVG_8;
default:
dev_warn(dev, "Invalid button average value");
return DA7219_AAD_BTN_AVG_2;
}
}
static enum da7219_aad_adc_1bit_rpt
da7219_aad_fw_adc_1bit_rpt(struct device *dev, u32 val)
{
switch (val) {
case 1:
return DA7219_AAD_ADC_1BIT_RPT_1;
case 2:
return DA7219_AAD_ADC_1BIT_RPT_2;
case 4:
return DA7219_AAD_ADC_1BIT_RPT_4;
case 8:
return DA7219_AAD_ADC_1BIT_RPT_8;
default:
dev_warn(dev, "Invalid ADC 1-bit repeat value");
return DA7219_AAD_ADC_1BIT_RPT_1;
}
}
static struct da7219_aad_pdata *da7219_aad_fw_to_pdata(struct device *dev)
{
struct i2c_client *i2c = to_i2c_client(dev);
struct fwnode_handle *aad_np;
struct da7219_aad_pdata *aad_pdata;
const char *fw_str;
u32 fw_val32;
aad_np = device_get_named_child_node(dev, "da7219_aad");
if (!aad_np)
return NULL;
aad_pdata = devm_kzalloc(dev, sizeof(*aad_pdata), GFP_KERNEL);
if (!aad_pdata)
return NULL;
aad_pdata->irq = i2c->irq;
if (fwnode_property_read_u32(aad_np, "dlg,micbias-pulse-lvl",
&fw_val32) >= 0)
aad_pdata->micbias_pulse_lvl =
da7219_aad_fw_micbias_pulse_lvl(dev, fw_val32);
else
aad_pdata->micbias_pulse_lvl = DA7219_AAD_MICBIAS_PULSE_LVL_OFF;
if (fwnode_property_read_u32(aad_np, "dlg,micbias-pulse-time",
&fw_val32) >= 0)
aad_pdata->micbias_pulse_time = fw_val32;
if (fwnode_property_read_u32(aad_np, "dlg,btn-cfg", &fw_val32) >= 0)
aad_pdata->btn_cfg = da7219_aad_fw_btn_cfg(dev, fw_val32);
else
aad_pdata->btn_cfg = DA7219_AAD_BTN_CFG_10MS;
if (fwnode_property_read_u32(aad_np, "dlg,mic-det-thr", &fw_val32) >= 0)
aad_pdata->mic_det_thr =
da7219_aad_fw_mic_det_thr(dev, fw_val32);
else
aad_pdata->mic_det_thr = DA7219_AAD_MIC_DET_THR_500_OHMS;
if (fwnode_property_read_u32(aad_np, "dlg,jack-ins-deb", &fw_val32) >= 0)
aad_pdata->jack_ins_deb =
da7219_aad_fw_jack_ins_deb(dev, fw_val32);
else
aad_pdata->jack_ins_deb = DA7219_AAD_JACK_INS_DEB_20MS;
if (!fwnode_property_read_string(aad_np, "dlg,jack-ins-det-pty", &fw_str))
aad_pdata->jack_ins_det_pty =
da7219_aad_fw_jack_ins_det_pty(dev, fw_str);
else
aad_pdata->jack_ins_det_pty = DA7219_AAD_JACK_INS_DET_PTY_LOW;
if (!fwnode_property_read_string(aad_np, "dlg,jack-det-rate", &fw_str))
aad_pdata->jack_det_rate =
da7219_aad_fw_jack_det_rate(dev, fw_str);
else
aad_pdata->jack_det_rate = DA7219_AAD_JACK_DET_RATE_256_512MS;
if (fwnode_property_read_u32(aad_np, "dlg,jack-rem-deb", &fw_val32) >= 0)
aad_pdata->jack_rem_deb =
da7219_aad_fw_jack_rem_deb(dev, fw_val32);
else
aad_pdata->jack_rem_deb = DA7219_AAD_JACK_REM_DEB_1MS;
if (fwnode_property_read_u32(aad_np, "dlg,a-d-btn-thr", &fw_val32) >= 0)
aad_pdata->a_d_btn_thr = (u8) fw_val32;
else
aad_pdata->a_d_btn_thr = 0xA;
if (fwnode_property_read_u32(aad_np, "dlg,d-b-btn-thr", &fw_val32) >= 0)
aad_pdata->d_b_btn_thr = (u8) fw_val32;
else
aad_pdata->d_b_btn_thr = 0x16;
if (fwnode_property_read_u32(aad_np, "dlg,b-c-btn-thr", &fw_val32) >= 0)
aad_pdata->b_c_btn_thr = (u8) fw_val32;
else
aad_pdata->b_c_btn_thr = 0x21;
if (fwnode_property_read_u32(aad_np, "dlg,c-mic-btn-thr", &fw_val32) >= 0)
aad_pdata->c_mic_btn_thr = (u8) fw_val32;
else
aad_pdata->c_mic_btn_thr = 0x3E;
if (fwnode_property_read_u32(aad_np, "dlg,btn-avg", &fw_val32) >= 0)
aad_pdata->btn_avg = da7219_aad_fw_btn_avg(dev, fw_val32);
else
aad_pdata->btn_avg = DA7219_AAD_BTN_AVG_2;
if (fwnode_property_read_u32(aad_np, "dlg,adc-1bit-rpt", &fw_val32) >= 0)
aad_pdata->adc_1bit_rpt =
da7219_aad_fw_adc_1bit_rpt(dev, fw_val32);
else
aad_pdata->adc_1bit_rpt = DA7219_AAD_ADC_1BIT_RPT_1;
return aad_pdata;
}
static void da7219_aad_handle_pdata(struct snd_soc_component *component)
{
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
struct da7219_aad_priv *da7219_aad = da7219->aad;
struct da7219_pdata *pdata = da7219->pdata;
if ((pdata) && (pdata->aad_pdata)) {
struct da7219_aad_pdata *aad_pdata = pdata->aad_pdata;
u8 cfg, mask;
da7219_aad->irq = aad_pdata->irq;
switch (aad_pdata->micbias_pulse_lvl) {
case DA7219_AAD_MICBIAS_PULSE_LVL_2_8V:
case DA7219_AAD_MICBIAS_PULSE_LVL_2_9V:
da7219_aad->micbias_pulse_lvl =
(aad_pdata->micbias_pulse_lvl <<
DA7219_MICBIAS1_LEVEL_SHIFT);
break;
default:
break;
}
da7219_aad->micbias_pulse_time = aad_pdata->micbias_pulse_time;
switch (aad_pdata->btn_cfg) {
case DA7219_AAD_BTN_CFG_2MS:
case DA7219_AAD_BTN_CFG_5MS:
case DA7219_AAD_BTN_CFG_10MS:
case DA7219_AAD_BTN_CFG_50MS:
case DA7219_AAD_BTN_CFG_100MS:
case DA7219_AAD_BTN_CFG_200MS:
case DA7219_AAD_BTN_CFG_500MS:
da7219_aad->btn_cfg = (aad_pdata->btn_cfg <<
DA7219_BUTTON_CONFIG_SHIFT);
}
cfg = 0;
mask = 0;
switch (aad_pdata->mic_det_thr) {
case DA7219_AAD_MIC_DET_THR_200_OHMS:
case DA7219_AAD_MIC_DET_THR_500_OHMS:
case DA7219_AAD_MIC_DET_THR_750_OHMS:
case DA7219_AAD_MIC_DET_THR_1000_OHMS:
cfg |= (aad_pdata->mic_det_thr <<
DA7219_MIC_DET_THRESH_SHIFT);
mask |= DA7219_MIC_DET_THRESH_MASK;
}
snd_soc_component_update_bits(component, DA7219_ACCDET_CONFIG_1, mask, cfg);
cfg = 0;
mask = 0;
switch (aad_pdata->jack_ins_deb) {
case DA7219_AAD_JACK_INS_DEB_5MS:
case DA7219_AAD_JACK_INS_DEB_10MS:
case DA7219_AAD_JACK_INS_DEB_20MS:
case DA7219_AAD_JACK_INS_DEB_50MS:
case DA7219_AAD_JACK_INS_DEB_100MS:
case DA7219_AAD_JACK_INS_DEB_200MS:
case DA7219_AAD_JACK_INS_DEB_500MS:
case DA7219_AAD_JACK_INS_DEB_1S:
cfg |= (aad_pdata->jack_ins_deb <<
DA7219_JACKDET_DEBOUNCE_SHIFT);
mask |= DA7219_JACKDET_DEBOUNCE_MASK;
}
switch (aad_pdata->jack_det_rate) {
case DA7219_AAD_JACK_DET_RATE_32_64MS:
case DA7219_AAD_JACK_DET_RATE_64_128MS:
case DA7219_AAD_JACK_DET_RATE_128_256MS:
case DA7219_AAD_JACK_DET_RATE_256_512MS:
cfg |= (aad_pdata->jack_det_rate <<
DA7219_JACK_DETECT_RATE_SHIFT);
mask |= DA7219_JACK_DETECT_RATE_MASK;
}
switch (aad_pdata->jack_rem_deb) {
case DA7219_AAD_JACK_REM_DEB_1MS:
case DA7219_AAD_JACK_REM_DEB_5MS:
case DA7219_AAD_JACK_REM_DEB_10MS:
case DA7219_AAD_JACK_REM_DEB_20MS:
cfg |= (aad_pdata->jack_rem_deb <<
DA7219_JACKDET_REM_DEB_SHIFT);
mask |= DA7219_JACKDET_REM_DEB_MASK;
}
snd_soc_component_update_bits(component, DA7219_ACCDET_CONFIG_2, mask, cfg);
snd_soc_component_write(component, DA7219_ACCDET_CONFIG_3,
aad_pdata->a_d_btn_thr);
snd_soc_component_write(component, DA7219_ACCDET_CONFIG_4,
aad_pdata->d_b_btn_thr);
snd_soc_component_write(component, DA7219_ACCDET_CONFIG_5,
aad_pdata->b_c_btn_thr);
snd_soc_component_write(component, DA7219_ACCDET_CONFIG_6,
aad_pdata->c_mic_btn_thr);
cfg = 0;
mask = 0;
switch (aad_pdata->btn_avg) {
case DA7219_AAD_BTN_AVG_1:
case DA7219_AAD_BTN_AVG_2:
case DA7219_AAD_BTN_AVG_4:
case DA7219_AAD_BTN_AVG_8:
cfg |= (aad_pdata->btn_avg <<
DA7219_BUTTON_AVERAGE_SHIFT);
mask |= DA7219_BUTTON_AVERAGE_MASK;
}
switch (aad_pdata->adc_1bit_rpt) {
case DA7219_AAD_ADC_1BIT_RPT_1:
case DA7219_AAD_ADC_1BIT_RPT_2:
case DA7219_AAD_ADC_1BIT_RPT_4:
case DA7219_AAD_ADC_1BIT_RPT_8:
cfg |= (aad_pdata->adc_1bit_rpt <<
DA7219_ADC_1_BIT_REPEAT_SHIFT);
mask |= DA7219_ADC_1_BIT_REPEAT_MASK;
}
snd_soc_component_update_bits(component, DA7219_ACCDET_CONFIG_7, mask, cfg);
switch (aad_pdata->jack_ins_det_pty) {
case DA7219_AAD_JACK_INS_DET_PTY_LOW:
snd_soc_component_write(component, 0xF0, 0x8B);
snd_soc_component_write(component, 0x75, 0x80);
snd_soc_component_write(component, 0xF0, 0x00);
break;
case DA7219_AAD_JACK_INS_DET_PTY_HIGH:
snd_soc_component_write(component, 0xF0, 0x8B);
snd_soc_component_write(component, 0x75, 0x00);
snd_soc_component_write(component, 0xF0, 0x00);
break;
default:
break;
}
}
}
static void da7219_aad_handle_gnd_switch_time(struct snd_soc_component *component)
{
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
struct da7219_aad_priv *da7219_aad = da7219->aad;
u8 jack_det;
jack_det = snd_soc_component_read(component, DA7219_ACCDET_CONFIG_2)
& DA7219_JACK_DETECT_RATE_MASK;
switch (jack_det) {
case 0x00:
da7219_aad->gnd_switch_delay = 32;
break;
case 0x10:
da7219_aad->gnd_switch_delay = 64;
break;
case 0x20:
da7219_aad->gnd_switch_delay = 128;
break;
case 0x30:
da7219_aad->gnd_switch_delay = 256;
break;
default:
da7219_aad->gnd_switch_delay = 32;
break;
}
}
/*
* Suspend/Resume
*/
void da7219_aad_suspend(struct snd_soc_component *component)
{
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
struct da7219_aad_priv *da7219_aad = da7219->aad;
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
u8 micbias_ctrl;
if (da7219_aad->jack) {
/* Disable jack detection during suspend */
snd_soc_component_update_bits(component, DA7219_ACCDET_CONFIG_1,
DA7219_ACCDET_EN_MASK, 0);
/*
* If we have a 4-pole jack inserted, then micbias will be
* enabled. We can disable micbias here, and keep a note to
* re-enable it on resume. If jack removal occurred during
* suspend then this will be dealt with through the IRQ handler.
*/
if (da7219_aad->jack_inserted) {
micbias_ctrl = snd_soc_component_read(component, DA7219_MICBIAS_CTRL);
if (micbias_ctrl & DA7219_MICBIAS1_EN_MASK) {
snd_soc_dapm_disable_pin(dapm, "Mic Bias");
snd_soc_dapm_sync(dapm);
da7219_aad->micbias_resume_enable = true;
}
}
}
synchronize_irq(da7219_aad->irq);
}
void da7219_aad_resume(struct snd_soc_component *component)
{
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
struct da7219_aad_priv *da7219_aad = da7219->aad;
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
if (da7219_aad->jack) {
/* Re-enable micbias if previously enabled for 4-pole jack */
if (da7219_aad->jack_inserted &&
da7219_aad->micbias_resume_enable) {
snd_soc_dapm_force_enable_pin(dapm, "Mic Bias");
snd_soc_dapm_sync(dapm);
da7219_aad->micbias_resume_enable = false;
}
/* Re-enable jack detection */
snd_soc_component_update_bits(component, DA7219_ACCDET_CONFIG_1,
DA7219_ACCDET_EN_MASK,
DA7219_ACCDET_EN_MASK);
}
}
/*
* Init/Exit
*/
int da7219_aad_init(struct snd_soc_component *component)
{
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
struct da7219_aad_priv *da7219_aad = da7219->aad;
u8 mask[DA7219_AAD_IRQ_REG_MAX];
int ret;
da7219_aad->component = component;
/* Handle any DT/ACPI/platform data */
da7219_aad_handle_pdata(component);
/* Disable button detection */
snd_soc_component_update_bits(component, DA7219_ACCDET_CONFIG_1,
DA7219_BUTTON_CONFIG_MASK, 0);
da7219_aad_handle_gnd_switch_time(component);
da7219_aad->aad_wq = create_singlethread_workqueue("da7219-aad");
if (!da7219_aad->aad_wq) {
dev_err(component->dev, "Failed to create aad workqueue\n");
return -ENOMEM;
}
INIT_DELAYED_WORK(&da7219_aad->jack_det_work, da7219_aad_jack_det_work);
INIT_WORK(&da7219_aad->btn_det_work, da7219_aad_btn_det_work);
INIT_WORK(&da7219_aad->hptest_work, da7219_aad_hptest_work);
ret = request_threaded_irq(da7219_aad->irq, NULL,
da7219_aad_irq_thread,
IRQF_TRIGGER_LOW | IRQF_ONESHOT,
"da7219-aad", da7219_aad);
if (ret) {
dev_err(component->dev, "Failed to request IRQ: %d\n", ret);
return ret;
}
/* Unmask AAD IRQs */
memset(mask, 0, DA7219_AAD_IRQ_REG_MAX);
regmap_bulk_write(da7219->regmap, DA7219_ACCDET_IRQ_MASK_A,
&mask, DA7219_AAD_IRQ_REG_MAX);
return 0;
}
void da7219_aad_exit(struct snd_soc_component *component)
{
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
struct da7219_aad_priv *da7219_aad = da7219->aad;
u8 mask[DA7219_AAD_IRQ_REG_MAX];
/* Mask off AAD IRQs */
memset(mask, DA7219_BYTE_MASK, DA7219_AAD_IRQ_REG_MAX);
regmap_bulk_write(da7219->regmap, DA7219_ACCDET_IRQ_MASK_A,
mask, DA7219_AAD_IRQ_REG_MAX);
free_irq(da7219_aad->irq, da7219_aad);
cancel_delayed_work_sync(&da7219_aad->jack_det_work);
cancel_work_sync(&da7219_aad->btn_det_work);
cancel_work_sync(&da7219_aad->hptest_work);
destroy_workqueue(da7219_aad->aad_wq);
}
/*
* AAD related I2C probe handling
*/
int da7219_aad_probe(struct i2c_client *i2c)
{
struct da7219_priv *da7219 = i2c_get_clientdata(i2c);
struct device *dev = &i2c->dev;
struct da7219_aad_priv *da7219_aad;
da7219_aad = devm_kzalloc(dev, sizeof(*da7219_aad), GFP_KERNEL);
if (!da7219_aad)
return -ENOMEM;
da7219->aad = da7219_aad;
/* Retrieve any DT/ACPI/platform data */
if (da7219->pdata && !da7219->pdata->aad_pdata)
da7219->pdata->aad_pdata = da7219_aad_fw_to_pdata(dev);
return 0;
}
MODULE_DESCRIPTION("ASoC DA7219 AAD Driver");
MODULE_AUTHOR("Adam Thomson <[email protected]>");
MODULE_AUTHOR("David Rau <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/da7219-aad.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ALSA SoC TWL6040 codec driver
*
* Author: Misael Lopez Cruz <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/mfd/twl6040.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "twl6040.h"
enum twl6040_dai_id {
TWL6040_DAI_LEGACY = 0,
TWL6040_DAI_UL,
TWL6040_DAI_DL1,
TWL6040_DAI_DL2,
TWL6040_DAI_VIB,
};
#define TWL6040_RATES SNDRV_PCM_RATE_8000_96000
#define TWL6040_FORMATS (SNDRV_PCM_FMTBIT_S32_LE)
#define TWL6040_OUTHS_0dB 0x00
#define TWL6040_OUTHS_M30dB 0x0F
#define TWL6040_OUTHF_0dB 0x03
#define TWL6040_OUTHF_M52dB 0x1D
#define TWL6040_CACHEREGNUM (TWL6040_REG_STATUS + 1)
struct twl6040_jack_data {
struct snd_soc_jack *jack;
struct delayed_work work;
int report;
};
/* codec private data */
struct twl6040_data {
int plug_irq;
int codec_powered;
int pll;
int pll_power_mode;
int hs_power_mode;
int hs_power_mode_locked;
bool dl1_unmuted;
bool dl2_unmuted;
u8 dl12_cache[TWL6040_REG_HFRCTL - TWL6040_REG_HSLCTL + 1];
unsigned int clk_in;
unsigned int sysclk;
struct twl6040_jack_data hs_jack;
struct snd_soc_component *component;
struct mutex mutex;
};
/* set of rates for each pll: low-power and high-performance */
static const unsigned int lp_rates[] = {
8000,
11250,
16000,
22500,
32000,
44100,
48000,
88200,
96000,
};
static const unsigned int hp_rates[] = {
8000,
16000,
32000,
48000,
96000,
};
static const struct snd_pcm_hw_constraint_list sysclk_constraints[] = {
{ .count = ARRAY_SIZE(lp_rates), .list = lp_rates, },
{ .count = ARRAY_SIZE(hp_rates), .list = hp_rates, },
};
#define to_twl6040(component) dev_get_drvdata((component)->dev->parent)
static unsigned int twl6040_read(struct snd_soc_component *component, unsigned int reg)
{
struct twl6040_data *priv = snd_soc_component_get_drvdata(component);
struct twl6040 *twl6040 = to_twl6040(component);
u8 value;
if (reg >= TWL6040_CACHEREGNUM)
return -EIO;
switch (reg) {
case TWL6040_REG_HSLCTL:
case TWL6040_REG_HSRCTL:
case TWL6040_REG_EARCTL:
case TWL6040_REG_HFLCTL:
case TWL6040_REG_HFRCTL:
value = priv->dl12_cache[reg - TWL6040_REG_HSLCTL];
break;
default:
value = twl6040_reg_read(twl6040, reg);
break;
}
return value;
}
static bool twl6040_can_write_to_chip(struct snd_soc_component *component,
unsigned int reg)
{
struct twl6040_data *priv = snd_soc_component_get_drvdata(component);
switch (reg) {
case TWL6040_REG_HSLCTL:
case TWL6040_REG_HSRCTL:
case TWL6040_REG_EARCTL:
/* DL1 path */
return priv->dl1_unmuted;
case TWL6040_REG_HFLCTL:
case TWL6040_REG_HFRCTL:
return priv->dl2_unmuted;
default:
return true;
}
}
static inline void twl6040_update_dl12_cache(struct snd_soc_component *component,
u8 reg, u8 value)
{
struct twl6040_data *priv = snd_soc_component_get_drvdata(component);
switch (reg) {
case TWL6040_REG_HSLCTL:
case TWL6040_REG_HSRCTL:
case TWL6040_REG_EARCTL:
case TWL6040_REG_HFLCTL:
case TWL6040_REG_HFRCTL:
priv->dl12_cache[reg - TWL6040_REG_HSLCTL] = value;
break;
default:
break;
}
}
static int twl6040_write(struct snd_soc_component *component,
unsigned int reg, unsigned int value)
{
struct twl6040 *twl6040 = to_twl6040(component);
if (reg >= TWL6040_CACHEREGNUM)
return -EIO;
twl6040_update_dl12_cache(component, reg, value);
if (twl6040_can_write_to_chip(component, reg))
return twl6040_reg_write(twl6040, reg, value);
else
return 0;
}
static void twl6040_init_chip(struct snd_soc_component *component)
{
twl6040_read(component, TWL6040_REG_TRIM1);
twl6040_read(component, TWL6040_REG_TRIM2);
twl6040_read(component, TWL6040_REG_TRIM3);
twl6040_read(component, TWL6040_REG_HSOTRIM);
twl6040_read(component, TWL6040_REG_HFOTRIM);
/* Change chip defaults */
/* No imput selected for microphone amplifiers */
twl6040_write(component, TWL6040_REG_MICLCTL, 0x18);
twl6040_write(component, TWL6040_REG_MICRCTL, 0x18);
/*
* We need to lower the default gain values, so the ramp code
* can work correctly for the first playback.
* This reduces the pop noise heard at the first playback.
*/
twl6040_write(component, TWL6040_REG_HSGAIN, 0xff);
twl6040_write(component, TWL6040_REG_EARCTL, 0x1e);
twl6040_write(component, TWL6040_REG_HFLGAIN, 0x1d);
twl6040_write(component, TWL6040_REG_HFRGAIN, 0x1d);
twl6040_write(component, TWL6040_REG_LINEGAIN, 0);
}
/* set headset dac and driver power mode */
static int headset_power_mode(struct snd_soc_component *component, int high_perf)
{
int hslctl, hsrctl;
int mask = TWL6040_HSDRVMODE | TWL6040_HSDACMODE;
hslctl = twl6040_read(component, TWL6040_REG_HSLCTL);
hsrctl = twl6040_read(component, TWL6040_REG_HSRCTL);
if (high_perf) {
hslctl &= ~mask;
hsrctl &= ~mask;
} else {
hslctl |= mask;
hsrctl |= mask;
}
twl6040_write(component, TWL6040_REG_HSLCTL, hslctl);
twl6040_write(component, TWL6040_REG_HSRCTL, hsrctl);
return 0;
}
static int twl6040_hs_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
u8 hslctl, hsrctl;
/*
* Workaround for Headset DC offset caused pop noise:
* Both HS DAC need to be turned on (before the HS driver) and off at
* the same time.
*/
hslctl = twl6040_read(component, TWL6040_REG_HSLCTL);
hsrctl = twl6040_read(component, TWL6040_REG_HSRCTL);
if (SND_SOC_DAPM_EVENT_ON(event)) {
hslctl |= TWL6040_HSDACENA;
hsrctl |= TWL6040_HSDACENA;
} else {
hslctl &= ~TWL6040_HSDACENA;
hsrctl &= ~TWL6040_HSDACENA;
}
twl6040_write(component, TWL6040_REG_HSLCTL, hslctl);
twl6040_write(component, TWL6040_REG_HSRCTL, hsrctl);
msleep(1);
return 0;
}
static int twl6040_ep_drv_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct twl6040_data *priv = snd_soc_component_get_drvdata(component);
int ret = 0;
if (SND_SOC_DAPM_EVENT_ON(event)) {
/* Earphone doesn't support low power mode */
priv->hs_power_mode_locked = 1;
ret = headset_power_mode(component, 1);
} else {
priv->hs_power_mode_locked = 0;
ret = headset_power_mode(component, priv->hs_power_mode);
}
msleep(1);
return ret;
}
static void twl6040_hs_jack_report(struct snd_soc_component *component,
struct snd_soc_jack *jack, int report)
{
struct twl6040_data *priv = snd_soc_component_get_drvdata(component);
int status;
mutex_lock(&priv->mutex);
/* Sync status */
status = twl6040_read(component, TWL6040_REG_STATUS);
if (status & TWL6040_PLUGCOMP)
snd_soc_jack_report(jack, report, report);
else
snd_soc_jack_report(jack, 0, report);
mutex_unlock(&priv->mutex);
}
void twl6040_hs_jack_detect(struct snd_soc_component *component,
struct snd_soc_jack *jack, int report)
{
struct twl6040_data *priv = snd_soc_component_get_drvdata(component);
struct twl6040_jack_data *hs_jack = &priv->hs_jack;
hs_jack->jack = jack;
hs_jack->report = report;
twl6040_hs_jack_report(component, hs_jack->jack, hs_jack->report);
}
EXPORT_SYMBOL_GPL(twl6040_hs_jack_detect);
static void twl6040_accessory_work(struct work_struct *work)
{
struct twl6040_data *priv = container_of(work,
struct twl6040_data, hs_jack.work.work);
struct snd_soc_component *component = priv->component;
struct twl6040_jack_data *hs_jack = &priv->hs_jack;
twl6040_hs_jack_report(component, hs_jack->jack, hs_jack->report);
}
/* audio interrupt handler */
static irqreturn_t twl6040_audio_handler(int irq, void *data)
{
struct snd_soc_component *component = data;
struct twl6040_data *priv = snd_soc_component_get_drvdata(component);
queue_delayed_work(system_power_efficient_wq,
&priv->hs_jack.work, msecs_to_jiffies(200));
return IRQ_HANDLED;
}
static int twl6040_soc_dapm_put_vibra_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int val;
/* Do not allow changes while Input/FF efect is running */
val = twl6040_read(component, e->reg);
if (val & TWL6040_VIBENA && !(val & TWL6040_VIBSEL))
return -EBUSY;
return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
}
/*
* MICATT volume control:
* from -6 to 0 dB in 6 dB steps
*/
static DECLARE_TLV_DB_SCALE(mic_preamp_tlv, -600, 600, 0);
/*
* MICGAIN volume control:
* from 6 to 30 dB in 6 dB steps
*/
static DECLARE_TLV_DB_SCALE(mic_amp_tlv, 600, 600, 0);
/*
* AFMGAIN volume control:
* from -18 to 24 dB in 6 dB steps
*/
static DECLARE_TLV_DB_SCALE(afm_amp_tlv, -1800, 600, 0);
/*
* HSGAIN volume control:
* from -30 to 0 dB in 2 dB steps
*/
static DECLARE_TLV_DB_SCALE(hs_tlv, -3000, 200, 0);
/*
* HFGAIN volume control:
* from -52 to 6 dB in 2 dB steps
*/
static DECLARE_TLV_DB_SCALE(hf_tlv, -5200, 200, 0);
/*
* EPGAIN volume control:
* from -24 to 6 dB in 2 dB steps
*/
static DECLARE_TLV_DB_SCALE(ep_tlv, -2400, 200, 0);
/* Left analog microphone selection */
static const char *twl6040_amicl_texts[] =
{"Headset Mic", "Main Mic", "Aux/FM Left", "Off"};
/* Right analog microphone selection */
static const char *twl6040_amicr_texts[] =
{"Headset Mic", "Sub Mic", "Aux/FM Right", "Off"};
static const struct soc_enum twl6040_enum[] = {
SOC_ENUM_SINGLE(TWL6040_REG_MICLCTL, 3,
ARRAY_SIZE(twl6040_amicl_texts), twl6040_amicl_texts),
SOC_ENUM_SINGLE(TWL6040_REG_MICRCTL, 3,
ARRAY_SIZE(twl6040_amicr_texts), twl6040_amicr_texts),
};
static const char *twl6040_hs_texts[] = {
"Off", "HS DAC", "Line-In amp"
};
static const struct soc_enum twl6040_hs_enum[] = {
SOC_ENUM_SINGLE(TWL6040_REG_HSLCTL, 5, ARRAY_SIZE(twl6040_hs_texts),
twl6040_hs_texts),
SOC_ENUM_SINGLE(TWL6040_REG_HSRCTL, 5, ARRAY_SIZE(twl6040_hs_texts),
twl6040_hs_texts),
};
static const char *twl6040_hf_texts[] = {
"Off", "HF DAC", "Line-In amp"
};
static const struct soc_enum twl6040_hf_enum[] = {
SOC_ENUM_SINGLE(TWL6040_REG_HFLCTL, 2, ARRAY_SIZE(twl6040_hf_texts),
twl6040_hf_texts),
SOC_ENUM_SINGLE(TWL6040_REG_HFRCTL, 2, ARRAY_SIZE(twl6040_hf_texts),
twl6040_hf_texts),
};
static const char *twl6040_vibrapath_texts[] = {
"Input FF", "Audio PDM"
};
static const struct soc_enum twl6040_vibra_enum[] = {
SOC_ENUM_SINGLE(TWL6040_REG_VIBCTLL, 1,
ARRAY_SIZE(twl6040_vibrapath_texts),
twl6040_vibrapath_texts),
SOC_ENUM_SINGLE(TWL6040_REG_VIBCTLR, 1,
ARRAY_SIZE(twl6040_vibrapath_texts),
twl6040_vibrapath_texts),
};
static const struct snd_kcontrol_new amicl_control =
SOC_DAPM_ENUM("Route", twl6040_enum[0]);
static const struct snd_kcontrol_new amicr_control =
SOC_DAPM_ENUM("Route", twl6040_enum[1]);
/* Headset DAC playback switches */
static const struct snd_kcontrol_new hsl_mux_controls =
SOC_DAPM_ENUM("Route", twl6040_hs_enum[0]);
static const struct snd_kcontrol_new hsr_mux_controls =
SOC_DAPM_ENUM("Route", twl6040_hs_enum[1]);
/* Handsfree DAC playback switches */
static const struct snd_kcontrol_new hfl_mux_controls =
SOC_DAPM_ENUM("Route", twl6040_hf_enum[0]);
static const struct snd_kcontrol_new hfr_mux_controls =
SOC_DAPM_ENUM("Route", twl6040_hf_enum[1]);
static const struct snd_kcontrol_new ep_path_enable_control =
SOC_DAPM_SINGLE_VIRT("Switch", 1);
static const struct snd_kcontrol_new auxl_switch_control =
SOC_DAPM_SINGLE("Switch", TWL6040_REG_HFLCTL, 6, 1, 0);
static const struct snd_kcontrol_new auxr_switch_control =
SOC_DAPM_SINGLE("Switch", TWL6040_REG_HFRCTL, 6, 1, 0);
/* Vibra playback switches */
static const struct snd_kcontrol_new vibral_mux_controls =
SOC_DAPM_ENUM_EXT("Route", twl6040_vibra_enum[0],
snd_soc_dapm_get_enum_double,
twl6040_soc_dapm_put_vibra_enum);
static const struct snd_kcontrol_new vibrar_mux_controls =
SOC_DAPM_ENUM_EXT("Route", twl6040_vibra_enum[1],
snd_soc_dapm_get_enum_double,
twl6040_soc_dapm_put_vibra_enum);
/* Headset power mode */
static const char *twl6040_power_mode_texts[] = {
"Low-Power", "High-Performance",
};
static SOC_ENUM_SINGLE_EXT_DECL(twl6040_power_mode_enum,
twl6040_power_mode_texts);
static int twl6040_headset_power_get_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct twl6040_data *priv = snd_soc_component_get_drvdata(component);
ucontrol->value.enumerated.item[0] = priv->hs_power_mode;
return 0;
}
static int twl6040_headset_power_put_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct twl6040_data *priv = snd_soc_component_get_drvdata(component);
int high_perf = ucontrol->value.enumerated.item[0];
int ret = 0;
if (!priv->hs_power_mode_locked)
ret = headset_power_mode(component, high_perf);
if (!ret)
priv->hs_power_mode = high_perf;
return ret;
}
static int twl6040_pll_get_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct twl6040_data *priv = snd_soc_component_get_drvdata(component);
ucontrol->value.enumerated.item[0] = priv->pll_power_mode;
return 0;
}
static int twl6040_pll_put_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct twl6040_data *priv = snd_soc_component_get_drvdata(component);
priv->pll_power_mode = ucontrol->value.enumerated.item[0];
return 0;
}
int twl6040_get_dl1_gain(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
if (snd_soc_dapm_get_pin_status(dapm, "EP"))
return -1; /* -1dB */
if (snd_soc_dapm_get_pin_status(dapm, "HSOR") ||
snd_soc_dapm_get_pin_status(dapm, "HSOL")) {
u8 val = twl6040_read(component, TWL6040_REG_HSLCTL);
if (val & TWL6040_HSDACMODE)
/* HSDACL in LP mode */
return -8; /* -8dB */
else
/* HSDACL in HP mode */
return -1; /* -1dB */
}
return 0; /* 0dB */
}
EXPORT_SYMBOL_GPL(twl6040_get_dl1_gain);
int twl6040_get_clk_id(struct snd_soc_component *component)
{
struct twl6040_data *priv = snd_soc_component_get_drvdata(component);
return priv->pll_power_mode;
}
EXPORT_SYMBOL_GPL(twl6040_get_clk_id);
int twl6040_get_trim_value(struct snd_soc_component *component, enum twl6040_trim trim)
{
if (unlikely(trim >= TWL6040_TRIM_INVAL))
return -EINVAL;
return twl6040_read(component, TWL6040_REG_TRIM1 + trim);
}
EXPORT_SYMBOL_GPL(twl6040_get_trim_value);
int twl6040_get_hs_step_size(struct snd_soc_component *component)
{
struct twl6040 *twl6040 = to_twl6040(component);
if (twl6040_get_revid(twl6040) < TWL6040_REV_ES1_3)
/* For ES under ES_1.3 HS step is 2 mV */
return 2;
else
/* For ES_1.3 HS step is 1 mV */
return 1;
}
EXPORT_SYMBOL_GPL(twl6040_get_hs_step_size);
static const struct snd_kcontrol_new twl6040_snd_controls[] = {
/* Capture gains */
SOC_DOUBLE_TLV("Capture Preamplifier Volume",
TWL6040_REG_MICGAIN, 6, 7, 1, 1, mic_preamp_tlv),
SOC_DOUBLE_TLV("Capture Volume",
TWL6040_REG_MICGAIN, 0, 3, 4, 0, mic_amp_tlv),
/* AFM gains */
SOC_DOUBLE_TLV("Aux FM Volume",
TWL6040_REG_LINEGAIN, 0, 3, 7, 0, afm_amp_tlv),
/* Playback gains */
SOC_DOUBLE_TLV("Headset Playback Volume",
TWL6040_REG_HSGAIN, 0, 4, 0xF, 1, hs_tlv),
SOC_DOUBLE_R_TLV("Handsfree Playback Volume",
TWL6040_REG_HFLGAIN, TWL6040_REG_HFRGAIN, 0, 0x1D, 1, hf_tlv),
SOC_SINGLE_TLV("Earphone Playback Volume",
TWL6040_REG_EARCTL, 1, 0xF, 1, ep_tlv),
SOC_ENUM_EXT("Headset Power Mode", twl6040_power_mode_enum,
twl6040_headset_power_get_enum,
twl6040_headset_power_put_enum),
/* Left HS PDM data routed to Right HSDAC */
SOC_SINGLE("Headset Mono to Stereo Playback Switch",
TWL6040_REG_HSRCTL, 7, 1, 0),
/* Left HF PDM data routed to Right HFDAC */
SOC_SINGLE("Handsfree Mono to Stereo Playback Switch",
TWL6040_REG_HFRCTL, 5, 1, 0),
SOC_ENUM_EXT("PLL Selection", twl6040_power_mode_enum,
twl6040_pll_get_enum, twl6040_pll_put_enum),
};
static const struct snd_soc_dapm_widget twl6040_dapm_widgets[] = {
/* Inputs */
SND_SOC_DAPM_INPUT("MAINMIC"),
SND_SOC_DAPM_INPUT("HSMIC"),
SND_SOC_DAPM_INPUT("SUBMIC"),
SND_SOC_DAPM_INPUT("AFML"),
SND_SOC_DAPM_INPUT("AFMR"),
/* Outputs */
SND_SOC_DAPM_OUTPUT("HSOL"),
SND_SOC_DAPM_OUTPUT("HSOR"),
SND_SOC_DAPM_OUTPUT("HFL"),
SND_SOC_DAPM_OUTPUT("HFR"),
SND_SOC_DAPM_OUTPUT("EP"),
SND_SOC_DAPM_OUTPUT("AUXL"),
SND_SOC_DAPM_OUTPUT("AUXR"),
SND_SOC_DAPM_OUTPUT("VIBRAL"),
SND_SOC_DAPM_OUTPUT("VIBRAR"),
/* Analog input muxes for the capture amplifiers */
SND_SOC_DAPM_MUX("Analog Left Capture Route",
SND_SOC_NOPM, 0, 0, &amicl_control),
SND_SOC_DAPM_MUX("Analog Right Capture Route",
SND_SOC_NOPM, 0, 0, &amicr_control),
/* Analog capture PGAs */
SND_SOC_DAPM_PGA("MicAmpL",
TWL6040_REG_MICLCTL, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("MicAmpR",
TWL6040_REG_MICRCTL, 0, 0, NULL, 0),
/* Auxiliary FM PGAs */
SND_SOC_DAPM_PGA("AFMAmpL",
TWL6040_REG_MICLCTL, 1, 0, NULL, 0),
SND_SOC_DAPM_PGA("AFMAmpR",
TWL6040_REG_MICRCTL, 1, 0, NULL, 0),
/* ADCs */
SND_SOC_DAPM_ADC("ADC Left", NULL, TWL6040_REG_MICLCTL, 2, 0),
SND_SOC_DAPM_ADC("ADC Right", NULL, TWL6040_REG_MICRCTL, 2, 0),
/* Microphone bias */
SND_SOC_DAPM_SUPPLY("Headset Mic Bias",
TWL6040_REG_AMICBCTL, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Main Mic Bias",
TWL6040_REG_AMICBCTL, 4, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Digital Mic1 Bias",
TWL6040_REG_DMICBCTL, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Digital Mic2 Bias",
TWL6040_REG_DMICBCTL, 4, 0, NULL, 0),
/* DACs */
SND_SOC_DAPM_DAC("HSDAC Left", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("HSDAC Right", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("HFDAC Left", NULL, TWL6040_REG_HFLCTL, 0, 0),
SND_SOC_DAPM_DAC("HFDAC Right", NULL, TWL6040_REG_HFRCTL, 0, 0),
/* Virtual DAC for vibra path (DL4 channel) */
SND_SOC_DAPM_DAC("VIBRA DAC", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_MUX("Handsfree Left Playback",
SND_SOC_NOPM, 0, 0, &hfl_mux_controls),
SND_SOC_DAPM_MUX("Handsfree Right Playback",
SND_SOC_NOPM, 0, 0, &hfr_mux_controls),
/* Analog playback Muxes */
SND_SOC_DAPM_MUX("Headset Left Playback",
SND_SOC_NOPM, 0, 0, &hsl_mux_controls),
SND_SOC_DAPM_MUX("Headset Right Playback",
SND_SOC_NOPM, 0, 0, &hsr_mux_controls),
SND_SOC_DAPM_MUX("Vibra Left Playback", SND_SOC_NOPM, 0, 0,
&vibral_mux_controls),
SND_SOC_DAPM_MUX("Vibra Right Playback", SND_SOC_NOPM, 0, 0,
&vibrar_mux_controls),
SND_SOC_DAPM_SWITCH("Earphone Playback", SND_SOC_NOPM, 0, 0,
&ep_path_enable_control),
SND_SOC_DAPM_SWITCH("AUXL Playback", SND_SOC_NOPM, 0, 0,
&auxl_switch_control),
SND_SOC_DAPM_SWITCH("AUXR Playback", SND_SOC_NOPM, 0, 0,
&auxr_switch_control),
/* Analog playback drivers */
SND_SOC_DAPM_OUT_DRV("HF Left Driver",
TWL6040_REG_HFLCTL, 4, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("HF Right Driver",
TWL6040_REG_HFRCTL, 4, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("HS Left Driver",
TWL6040_REG_HSLCTL, 2, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("HS Right Driver",
TWL6040_REG_HSRCTL, 2, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV_E("Earphone Driver",
TWL6040_REG_EARCTL, 0, 0, NULL, 0,
twl6040_ep_drv_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_OUT_DRV("Vibra Left Driver",
TWL6040_REG_VIBCTLL, 0, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("Vibra Right Driver",
TWL6040_REG_VIBCTLR, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Vibra Left Control", TWL6040_REG_VIBCTLL, 2, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("Vibra Right Control", TWL6040_REG_VIBCTLR, 2, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY_S("HSDAC Power", 1, SND_SOC_NOPM, 0, 0,
twl6040_hs_dac_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
/* Analog playback PGAs */
SND_SOC_DAPM_PGA("HF Left PGA",
TWL6040_REG_HFLCTL, 1, 0, NULL, 0),
SND_SOC_DAPM_PGA("HF Right PGA",
TWL6040_REG_HFRCTL, 1, 0, NULL, 0),
};
static const struct snd_soc_dapm_route intercon[] = {
/* Stream -> DAC mapping */
{"HSDAC Left", NULL, "Legacy Playback"},
{"HSDAC Left", NULL, "Headset Playback"},
{"HSDAC Right", NULL, "Legacy Playback"},
{"HSDAC Right", NULL, "Headset Playback"},
{"HFDAC Left", NULL, "Legacy Playback"},
{"HFDAC Left", NULL, "Handsfree Playback"},
{"HFDAC Right", NULL, "Legacy Playback"},
{"HFDAC Right", NULL, "Handsfree Playback"},
{"VIBRA DAC", NULL, "Legacy Playback"},
{"VIBRA DAC", NULL, "Vibra Playback"},
/* ADC -> Stream mapping */
{"Legacy Capture" , NULL, "ADC Left"},
{"Capture", NULL, "ADC Left"},
{"Legacy Capture", NULL, "ADC Right"},
{"Capture" , NULL, "ADC Right"},
/* Capture path */
{"Analog Left Capture Route", "Headset Mic", "HSMIC"},
{"Analog Left Capture Route", "Main Mic", "MAINMIC"},
{"Analog Left Capture Route", "Aux/FM Left", "AFML"},
{"Analog Right Capture Route", "Headset Mic", "HSMIC"},
{"Analog Right Capture Route", "Sub Mic", "SUBMIC"},
{"Analog Right Capture Route", "Aux/FM Right", "AFMR"},
{"MicAmpL", NULL, "Analog Left Capture Route"},
{"MicAmpR", NULL, "Analog Right Capture Route"},
{"ADC Left", NULL, "MicAmpL"},
{"ADC Right", NULL, "MicAmpR"},
/* AFM path */
{"AFMAmpL", NULL, "AFML"},
{"AFMAmpR", NULL, "AFMR"},
{"HSDAC Left", NULL, "HSDAC Power"},
{"HSDAC Right", NULL, "HSDAC Power"},
{"Headset Left Playback", "HS DAC", "HSDAC Left"},
{"Headset Left Playback", "Line-In amp", "AFMAmpL"},
{"Headset Right Playback", "HS DAC", "HSDAC Right"},
{"Headset Right Playback", "Line-In amp", "AFMAmpR"},
{"HS Left Driver", NULL, "Headset Left Playback"},
{"HS Right Driver", NULL, "Headset Right Playback"},
{"HSOL", NULL, "HS Left Driver"},
{"HSOR", NULL, "HS Right Driver"},
/* Earphone playback path */
{"Earphone Playback", "Switch", "HSDAC Left"},
{"Earphone Driver", NULL, "Earphone Playback"},
{"EP", NULL, "Earphone Driver"},
{"Handsfree Left Playback", "HF DAC", "HFDAC Left"},
{"Handsfree Left Playback", "Line-In amp", "AFMAmpL"},
{"Handsfree Right Playback", "HF DAC", "HFDAC Right"},
{"Handsfree Right Playback", "Line-In amp", "AFMAmpR"},
{"HF Left PGA", NULL, "Handsfree Left Playback"},
{"HF Right PGA", NULL, "Handsfree Right Playback"},
{"HF Left Driver", NULL, "HF Left PGA"},
{"HF Right Driver", NULL, "HF Right PGA"},
{"HFL", NULL, "HF Left Driver"},
{"HFR", NULL, "HF Right Driver"},
{"AUXL Playback", "Switch", "HF Left PGA"},
{"AUXR Playback", "Switch", "HF Right PGA"},
{"AUXL", NULL, "AUXL Playback"},
{"AUXR", NULL, "AUXR Playback"},
/* Vibrator paths */
{"Vibra Left Playback", "Audio PDM", "VIBRA DAC"},
{"Vibra Right Playback", "Audio PDM", "VIBRA DAC"},
{"Vibra Left Driver", NULL, "Vibra Left Playback"},
{"Vibra Right Driver", NULL, "Vibra Right Playback"},
{"Vibra Left Driver", NULL, "Vibra Left Control"},
{"Vibra Right Driver", NULL, "Vibra Right Control"},
{"VIBRAL", NULL, "Vibra Left Driver"},
{"VIBRAR", NULL, "Vibra Right Driver"},
};
static int twl6040_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct twl6040 *twl6040 = to_twl6040(component);
struct twl6040_data *priv = snd_soc_component_get_drvdata(component);
int ret = 0;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
if (priv->codec_powered) {
/* Select low power PLL in standby */
ret = twl6040_set_pll(twl6040, TWL6040_SYSCLK_SEL_LPPLL,
32768, 19200000);
break;
}
ret = twl6040_power(twl6040, 1);
if (ret)
break;
priv->codec_powered = 1;
/* Set external boost GPO */
twl6040_write(component, TWL6040_REG_GPOCTL, 0x02);
break;
case SND_SOC_BIAS_OFF:
if (!priv->codec_powered)
break;
twl6040_power(twl6040, 0);
priv->codec_powered = 0;
break;
}
return ret;
}
static int twl6040_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct twl6040_data *priv = snd_soc_component_get_drvdata(component);
snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&sysclk_constraints[priv->pll_power_mode]);
return 0;
}
static int twl6040_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct twl6040_data *priv = snd_soc_component_get_drvdata(component);
int rate;
rate = params_rate(params);
switch (rate) {
case 11250:
case 22500:
case 44100:
case 88200:
/* These rates are not supported when HPPLL is in use */
if (unlikely(priv->pll == TWL6040_SYSCLK_SEL_HPPLL)) {
dev_err(component->dev, "HPPLL does not support rate %d\n",
rate);
return -EINVAL;
}
priv->sysclk = 17640000;
break;
case 8000:
case 16000:
case 32000:
case 48000:
case 96000:
priv->sysclk = 19200000;
break;
default:
dev_err(component->dev, "unsupported rate %d\n", rate);
return -EINVAL;
}
return 0;
}
static int twl6040_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct twl6040 *twl6040 = to_twl6040(component);
struct twl6040_data *priv = snd_soc_component_get_drvdata(component);
int ret;
if (!priv->sysclk) {
dev_err(component->dev,
"no mclk configured, call set_sysclk() on init\n");
return -EINVAL;
}
ret = twl6040_set_pll(twl6040, priv->pll, priv->clk_in, priv->sysclk);
if (ret) {
dev_err(component->dev, "Can not set PLL (%d)\n", ret);
return -EPERM;
}
return 0;
}
static int twl6040_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct twl6040_data *priv = snd_soc_component_get_drvdata(component);
switch (clk_id) {
case TWL6040_SYSCLK_SEL_LPPLL:
case TWL6040_SYSCLK_SEL_HPPLL:
priv->pll = clk_id;
priv->clk_in = freq;
break;
default:
dev_err(component->dev, "unknown clk_id %d\n", clk_id);
return -EINVAL;
}
return 0;
}
static void twl6040_mute_path(struct snd_soc_component *component, enum twl6040_dai_id id,
int mute)
{
struct twl6040 *twl6040 = to_twl6040(component);
struct twl6040_data *priv = snd_soc_component_get_drvdata(component);
int hslctl, hsrctl, earctl;
int hflctl, hfrctl;
switch (id) {
case TWL6040_DAI_DL1:
hslctl = twl6040_read(component, TWL6040_REG_HSLCTL);
hsrctl = twl6040_read(component, TWL6040_REG_HSRCTL);
earctl = twl6040_read(component, TWL6040_REG_EARCTL);
if (mute) {
/* Power down drivers and DACs */
earctl &= ~0x01;
hslctl &= ~(TWL6040_HSDRVENA | TWL6040_HSDACENA);
hsrctl &= ~(TWL6040_HSDRVENA | TWL6040_HSDACENA);
}
twl6040_reg_write(twl6040, TWL6040_REG_EARCTL, earctl);
twl6040_reg_write(twl6040, TWL6040_REG_HSLCTL, hslctl);
twl6040_reg_write(twl6040, TWL6040_REG_HSRCTL, hsrctl);
priv->dl1_unmuted = !mute;
break;
case TWL6040_DAI_DL2:
hflctl = twl6040_read(component, TWL6040_REG_HFLCTL);
hfrctl = twl6040_read(component, TWL6040_REG_HFRCTL);
if (mute) {
/* Power down drivers and DACs */
hflctl &= ~(TWL6040_HFDACENA | TWL6040_HFPGAENA |
TWL6040_HFDRVENA | TWL6040_HFSWENA);
hfrctl &= ~(TWL6040_HFDACENA | TWL6040_HFPGAENA |
TWL6040_HFDRVENA | TWL6040_HFSWENA);
}
twl6040_reg_write(twl6040, TWL6040_REG_HFLCTL, hflctl);
twl6040_reg_write(twl6040, TWL6040_REG_HFRCTL, hfrctl);
priv->dl2_unmuted = !mute;
break;
default:
break;
}
}
static int twl6040_mute_stream(struct snd_soc_dai *dai, int mute, int direction)
{
switch (dai->id) {
case TWL6040_DAI_LEGACY:
twl6040_mute_path(dai->component, TWL6040_DAI_DL1, mute);
twl6040_mute_path(dai->component, TWL6040_DAI_DL2, mute);
break;
case TWL6040_DAI_DL1:
case TWL6040_DAI_DL2:
twl6040_mute_path(dai->component, dai->id, mute);
break;
default:
break;
}
return 0;
}
static const struct snd_soc_dai_ops twl6040_dai_ops = {
.startup = twl6040_startup,
.hw_params = twl6040_hw_params,
.prepare = twl6040_prepare,
.set_sysclk = twl6040_set_dai_sysclk,
.mute_stream = twl6040_mute_stream,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver twl6040_dai[] = {
{
.name = "twl6040-legacy",
.id = TWL6040_DAI_LEGACY,
.playback = {
.stream_name = "Legacy Playback",
.channels_min = 1,
.channels_max = 5,
.rates = TWL6040_RATES,
.formats = TWL6040_FORMATS,
},
.capture = {
.stream_name = "Legacy Capture",
.channels_min = 1,
.channels_max = 2,
.rates = TWL6040_RATES,
.formats = TWL6040_FORMATS,
},
.ops = &twl6040_dai_ops,
},
{
.name = "twl6040-ul",
.id = TWL6040_DAI_UL,
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = TWL6040_RATES,
.formats = TWL6040_FORMATS,
},
.ops = &twl6040_dai_ops,
},
{
.name = "twl6040-dl1",
.id = TWL6040_DAI_DL1,
.playback = {
.stream_name = "Headset Playback",
.channels_min = 1,
.channels_max = 2,
.rates = TWL6040_RATES,
.formats = TWL6040_FORMATS,
},
.ops = &twl6040_dai_ops,
},
{
.name = "twl6040-dl2",
.id = TWL6040_DAI_DL2,
.playback = {
.stream_name = "Handsfree Playback",
.channels_min = 1,
.channels_max = 2,
.rates = TWL6040_RATES,
.formats = TWL6040_FORMATS,
},
.ops = &twl6040_dai_ops,
},
{
.name = "twl6040-vib",
.id = TWL6040_DAI_VIB,
.playback = {
.stream_name = "Vibra Playback",
.channels_min = 1,
.channels_max = 1,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.formats = TWL6040_FORMATS,
},
.ops = &twl6040_dai_ops,
},
};
static int twl6040_probe(struct snd_soc_component *component)
{
struct twl6040_data *priv;
struct platform_device *pdev = to_platform_device(component->dev);
int ret = 0;
priv = devm_kzalloc(component->dev, sizeof(*priv), GFP_KERNEL);
if (priv == NULL)
return -ENOMEM;
snd_soc_component_set_drvdata(component, priv);
priv->component = component;
priv->plug_irq = platform_get_irq(pdev, 0);
if (priv->plug_irq < 0)
return priv->plug_irq;
INIT_DELAYED_WORK(&priv->hs_jack.work, twl6040_accessory_work);
mutex_init(&priv->mutex);
ret = request_threaded_irq(priv->plug_irq, NULL,
twl6040_audio_handler,
IRQF_NO_SUSPEND | IRQF_ONESHOT,
"twl6040_irq_plug", component);
if (ret) {
dev_err(component->dev, "PLUG IRQ request failed: %d\n", ret);
return ret;
}
snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
twl6040_init_chip(component);
return 0;
}
static void twl6040_remove(struct snd_soc_component *component)
{
struct twl6040_data *priv = snd_soc_component_get_drvdata(component);
free_irq(priv->plug_irq, component);
}
static const struct snd_soc_component_driver soc_component_dev_twl6040 = {
.probe = twl6040_probe,
.remove = twl6040_remove,
.read = twl6040_read,
.write = twl6040_write,
.set_bias_level = twl6040_set_bias_level,
.controls = twl6040_snd_controls,
.num_controls = ARRAY_SIZE(twl6040_snd_controls),
.dapm_widgets = twl6040_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(twl6040_dapm_widgets),
.dapm_routes = intercon,
.num_dapm_routes = ARRAY_SIZE(intercon),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.endianness = 1,
};
static int twl6040_codec_probe(struct platform_device *pdev)
{
return devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_twl6040,
twl6040_dai, ARRAY_SIZE(twl6040_dai));
}
static struct platform_driver twl6040_codec_driver = {
.driver = {
.name = "twl6040-codec",
},
.probe = twl6040_codec_probe,
};
module_platform_driver(twl6040_codec_driver);
MODULE_DESCRIPTION("ASoC TWL6040 codec driver");
MODULE_AUTHOR("Misael Lopez Cruz");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/twl6040.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8731-i2c.c -- WM8731 ALSA SoC Audio driver I2C code
*
* Copyright 2005 Openedhand Ltd.
* Copyright 2006-12 Wolfson Microelectronics, plc
*
* Author: Richard Purdie <[email protected]>
*
* Based on wm8753.c by Liam Girdwood
*/
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include "wm8731.h"
static const struct of_device_id wm8731_of_match[] = {
{ .compatible = "wlf,wm8731", },
{ }
};
MODULE_DEVICE_TABLE(of, wm8731_of_match);
static int wm8731_i2c_probe(struct i2c_client *i2c)
{
struct wm8731_priv *wm8731;
int ret;
wm8731 = devm_kzalloc(&i2c->dev, sizeof(struct wm8731_priv),
GFP_KERNEL);
if (wm8731 == NULL)
return -ENOMEM;
i2c_set_clientdata(i2c, wm8731);
wm8731->regmap = devm_regmap_init_i2c(i2c, &wm8731_regmap);
if (IS_ERR(wm8731->regmap)) {
ret = PTR_ERR(wm8731->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
return wm8731_init(&i2c->dev, wm8731);
}
static const struct i2c_device_id wm8731_i2c_id[] = {
{ "wm8731", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8731_i2c_id);
static struct i2c_driver wm8731_i2c_driver = {
.driver = {
.name = "wm8731",
.of_match_table = wm8731_of_match,
},
.probe = wm8731_i2c_probe,
.id_table = wm8731_i2c_id,
};
module_i2c_driver(wm8731_i2c_driver);
MODULE_DESCRIPTION("ASoC WM8731 driver - I2C");
MODULE_AUTHOR("Richard Purdie");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8731-i2c.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright(c) 2021-2022 Intel Corporation. All rights reserved.
//
// Author: Cezary Rojewski <[email protected]>
//
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <sound/soc.h>
#include <sound/hdaudio_ext.h>
#include <sound/hda_i915.h>
#include <sound/hda_codec.h>
#include "hda.h"
static int hda_codec_create_dais(struct hda_codec *codec, int pcm_count,
struct snd_soc_dai_driver **drivers)
{
struct device *dev = &codec->core.dev;
struct snd_soc_dai_driver *drvs;
struct hda_pcm *pcm;
int i;
drvs = devm_kcalloc(dev, pcm_count, sizeof(*drvs), GFP_KERNEL);
if (!drvs)
return -ENOMEM;
pcm = list_first_entry(&codec->pcm_list_head, struct hda_pcm, list);
for (i = 0; i < pcm_count; i++, pcm = list_next_entry(pcm, list)) {
struct snd_soc_pcm_stream *stream;
int dir;
dev_info(dev, "creating for %s %d\n", pcm->name, i);
drvs[i].id = i;
drvs[i].name = pcm->name;
drvs[i].ops = &snd_soc_hda_codec_dai_ops;
dir = SNDRV_PCM_STREAM_PLAYBACK;
stream = &drvs[i].playback;
if (!pcm->stream[dir].substreams) {
dev_info(dev, "skipping playback dai for %s\n", pcm->name);
goto capture_dais;
}
stream->stream_name =
devm_kasprintf(dev, GFP_KERNEL, "%s %s", pcm->name,
snd_pcm_direction_name(dir));
if (!stream->stream_name)
return -ENOMEM;
stream->channels_min = pcm->stream[dir].channels_min;
stream->channels_max = pcm->stream[dir].channels_max;
stream->rates = pcm->stream[dir].rates;
stream->formats = pcm->stream[dir].formats;
stream->sig_bits = pcm->stream[dir].maxbps;
capture_dais:
dir = SNDRV_PCM_STREAM_CAPTURE;
stream = &drvs[i].capture;
if (!pcm->stream[dir].substreams) {
dev_info(dev, "skipping capture dai for %s\n", pcm->name);
continue;
}
stream->stream_name =
devm_kasprintf(dev, GFP_KERNEL, "%s %s", pcm->name,
snd_pcm_direction_name(dir));
if (!stream->stream_name)
return -ENOMEM;
stream->channels_min = pcm->stream[dir].channels_min;
stream->channels_max = pcm->stream[dir].channels_max;
stream->rates = pcm->stream[dir].rates;
stream->formats = pcm->stream[dir].formats;
stream->sig_bits = pcm->stream[dir].maxbps;
}
*drivers = drvs;
return 0;
}
static int hda_codec_register_dais(struct hda_codec *codec, struct snd_soc_component *component)
{
struct snd_soc_dai_driver *drvs = NULL;
struct snd_soc_dapm_context *dapm;
struct hda_pcm *pcm;
int ret, pcm_count = 0;
if (list_empty(&codec->pcm_list_head))
return -EINVAL;
list_for_each_entry(pcm, &codec->pcm_list_head, list)
pcm_count++;
ret = hda_codec_create_dais(codec, pcm_count, &drvs);
if (ret < 0)
return ret;
dapm = snd_soc_component_get_dapm(component);
list_for_each_entry(pcm, &codec->pcm_list_head, list) {
struct snd_soc_dai *dai;
dai = snd_soc_register_dai(component, drvs, false);
if (!dai) {
dev_err(component->dev, "register dai for %s failed\n", pcm->name);
return -EINVAL;
}
ret = snd_soc_dapm_new_dai_widgets(dapm, dai);
if (ret < 0) {
dev_err(component->dev, "create widgets failed: %d\n", ret);
snd_soc_unregister_dai(dai);
return ret;
}
snd_soc_dai_init_dma_data(dai, &pcm->stream[0], &pcm->stream[1]);
drvs++;
}
return 0;
}
static void hda_codec_unregister_dais(struct hda_codec *codec,
struct snd_soc_component *component)
{
struct snd_soc_dai *dai, *save;
struct hda_pcm *pcm;
for_each_component_dais_safe(component, dai, save) {
int stream;
list_for_each_entry(pcm, &codec->pcm_list_head, list) {
if (strcmp(dai->driver->name, pcm->name))
continue;
for_each_pcm_streams(stream)
snd_soc_dapm_free_widget(snd_soc_dai_get_widget(dai, stream));
snd_soc_unregister_dai(dai);
break;
}
}
}
int hda_codec_probe_complete(struct hda_codec *codec)
{
struct hdac_device *hdev = &codec->core;
struct hdac_bus *bus = hdev->bus;
int ret;
ret = snd_hda_codec_build_controls(codec);
if (ret < 0) {
dev_err(&hdev->dev, "unable to create controls %d\n", ret);
goto out;
}
/* Bus suspended codecs as it does not manage their pm */
pm_runtime_set_active(&hdev->dev);
/* rpm was forbidden in snd_hda_codec_device_new() */
snd_hda_codec_set_power_save(codec, 2000);
snd_hda_codec_register(codec);
out:
/* Complement pm_runtime_get_sync(bus) in probe */
pm_runtime_mark_last_busy(bus->dev);
pm_runtime_put_autosuspend(bus->dev);
return ret;
}
EXPORT_SYMBOL_GPL(hda_codec_probe_complete);
/* Expects codec with usage_count=1 and status=suspended */
static int hda_codec_probe(struct snd_soc_component *component)
{
struct hda_codec *codec = dev_to_hda_codec(component->dev);
struct hdac_device *hdev = &codec->core;
struct hdac_bus *bus = hdev->bus;
struct hdac_ext_link *hlink;
hda_codec_patch_t patch;
int ret;
#ifdef CONFIG_PM
WARN_ON(atomic_read(&hdev->dev.power.usage_count) != 1 ||
!pm_runtime_status_suspended(&hdev->dev));
#endif
hlink = snd_hdac_ext_bus_get_hlink_by_addr(bus, hdev->addr);
if (!hlink) {
dev_err(&hdev->dev, "hdac link not found\n");
return -EIO;
}
pm_runtime_get_sync(bus->dev);
if (hda_codec_is_display(codec))
snd_hdac_display_power(bus, hdev->addr, true);
snd_hdac_ext_bus_link_get(bus, hlink);
ret = snd_hda_codec_device_new(codec->bus, component->card->snd_card, hdev->addr, codec,
false);
if (ret < 0) {
dev_err(&hdev->dev, "create hda codec failed: %d\n", ret);
goto device_new_err;
}
ret = snd_hda_codec_set_name(codec, codec->preset->name);
if (ret < 0) {
dev_err(&hdev->dev, "name failed %s\n", codec->preset->name);
goto err;
}
ret = snd_hdac_regmap_init(&codec->core);
if (ret < 0) {
dev_err(&hdev->dev, "regmap init failed\n");
goto err;
}
patch = (hda_codec_patch_t)codec->preset->driver_data;
if (!patch) {
dev_err(&hdev->dev, "no patch specified\n");
ret = -EINVAL;
goto err;
}
ret = patch(codec);
if (ret < 0) {
dev_err(&hdev->dev, "patch failed %d\n", ret);
goto err;
}
ret = snd_hda_codec_parse_pcms(codec);
if (ret < 0) {
dev_err(&hdev->dev, "unable to map pcms to dai %d\n", ret);
goto parse_pcms_err;
}
ret = hda_codec_register_dais(codec, component);
if (ret < 0) {
dev_err(&hdev->dev, "update dais failed: %d\n", ret);
goto parse_pcms_err;
}
if (!hda_codec_is_display(codec)) {
ret = hda_codec_probe_complete(codec);
if (ret < 0)
goto complete_err;
}
codec->core.lazy_cache = true;
return 0;
complete_err:
hda_codec_unregister_dais(codec, component);
parse_pcms_err:
if (codec->patch_ops.free)
codec->patch_ops.free(codec);
err:
snd_hda_codec_cleanup_for_unbind(codec);
device_new_err:
if (hda_codec_is_display(codec))
snd_hdac_display_power(bus, hdev->addr, false);
snd_hdac_ext_bus_link_put(bus, hlink);
pm_runtime_mark_last_busy(bus->dev);
pm_runtime_put_autosuspend(bus->dev);
return ret;
}
/* Leaves codec with usage_count=1 and status=suspended */
static void hda_codec_remove(struct snd_soc_component *component)
{
struct hda_codec *codec = dev_to_hda_codec(component->dev);
struct hdac_device *hdev = &codec->core;
struct hdac_bus *bus = hdev->bus;
struct hdac_ext_link *hlink;
bool was_registered = codec->core.registered;
/* Don't allow any more runtime suspends */
pm_runtime_forbid(&hdev->dev);
hda_codec_unregister_dais(codec, component);
if (codec->patch_ops.free)
codec->patch_ops.free(codec);
snd_hda_codec_cleanup_for_unbind(codec);
pm_runtime_put_noidle(&hdev->dev);
/* snd_hdac_device_exit() is only called on bus remove */
pm_runtime_set_suspended(&hdev->dev);
if (hda_codec_is_display(codec))
snd_hdac_display_power(bus, hdev->addr, false);
hlink = snd_hdac_ext_bus_get_hlink_by_addr(bus, hdev->addr);
if (hlink)
snd_hdac_ext_bus_link_put(bus, hlink);
/*
* HDMI card's hda_codec_probe_complete() (see late_probe()) may
* not be called due to early error, leaving bus uc unbalanced
*/
if (!was_registered) {
pm_runtime_mark_last_busy(bus->dev);
pm_runtime_put_autosuspend(bus->dev);
}
#ifdef CONFIG_PM
WARN_ON(atomic_read(&hdev->dev.power.usage_count) != 1 ||
!pm_runtime_status_suspended(&hdev->dev));
#endif
}
static const struct snd_soc_dapm_route hda_dapm_routes[] = {
{"AIF1TX", NULL, "Codec Input Pin1"},
{"AIF2TX", NULL, "Codec Input Pin2"},
{"AIF3TX", NULL, "Codec Input Pin3"},
{"Codec Output Pin1", NULL, "AIF1RX"},
{"Codec Output Pin2", NULL, "AIF2RX"},
{"Codec Output Pin3", NULL, "AIF3RX"},
};
static const struct snd_soc_dapm_widget hda_dapm_widgets[] = {
/* Audio Interface */
SND_SOC_DAPM_AIF_IN("AIF1RX", "Analog Codec Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX", "Digital Codec Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIF3RX", "Alt Analog Codec Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX", "Analog Codec Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX", "Digital Codec Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF3TX", "Alt Analog Codec Capture", 0, SND_SOC_NOPM, 0, 0),
/* Input Pins */
SND_SOC_DAPM_INPUT("Codec Input Pin1"),
SND_SOC_DAPM_INPUT("Codec Input Pin2"),
SND_SOC_DAPM_INPUT("Codec Input Pin3"),
/* Output Pins */
SND_SOC_DAPM_OUTPUT("Codec Output Pin1"),
SND_SOC_DAPM_OUTPUT("Codec Output Pin2"),
SND_SOC_DAPM_OUTPUT("Codec Output Pin3"),
};
static struct snd_soc_dai_driver card_binder_dai = {
.id = -1,
.name = "codec-probing-DAI",
};
static int hda_hdev_attach(struct hdac_device *hdev)
{
struct hda_codec *codec = dev_to_hda_codec(&hdev->dev);
struct snd_soc_component_driver *comp_drv;
comp_drv = devm_kzalloc(&hdev->dev, sizeof(*comp_drv), GFP_KERNEL);
if (!comp_drv)
return -ENOMEM;
/*
* It's save to rely on dev_name() rather than a copy as component
* driver's lifetime is directly tied to hda codec one
*/
comp_drv->name = dev_name(&hdev->dev);
comp_drv->probe = hda_codec_probe;
comp_drv->remove = hda_codec_remove;
comp_drv->idle_bias_on = false;
if (!hda_codec_is_display(codec)) {
comp_drv->dapm_widgets = hda_dapm_widgets;
comp_drv->num_dapm_widgets = ARRAY_SIZE(hda_dapm_widgets);
comp_drv->dapm_routes = hda_dapm_routes;
comp_drv->num_dapm_routes = ARRAY_SIZE(hda_dapm_routes);
}
return snd_soc_register_component(&hdev->dev, comp_drv, &card_binder_dai, 1);
}
static int hda_hdev_detach(struct hdac_device *hdev)
{
struct hda_codec *codec = dev_to_hda_codec(&hdev->dev);
if (codec->core.registered)
cancel_delayed_work_sync(&codec->jackpoll_work);
snd_soc_unregister_component(&hdev->dev);
return 0;
}
const struct hdac_ext_bus_ops soc_hda_ext_bus_ops = {
.hdev_attach = hda_hdev_attach,
.hdev_detach = hda_hdev_detach,
};
EXPORT_SYMBOL_GPL(soc_hda_ext_bus_ops);
MODULE_DESCRIPTION("HD-Audio codec driver");
MODULE_AUTHOR("Cezary Rojewski <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/hda.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* wm8753.c -- WM8753 ALSA Soc Audio driver
*
* Copyright 2003-11 Wolfson Microelectronics PLC.
* Author: Liam Girdwood <[email protected]>
*
* Notes:
* The WM8753 is a low power, high quality stereo codec with integrated PCM
* codec designed for portable digital telephony applications.
*
* Dual DAI:-
*
* This driver support 2 DAI PCM's. This makes the default PCM available for
* HiFi audio (e.g. MP3, ogg) playback/capture and the other PCM available for
* voice.
*
* Please note that the voice PCM can be connected directly to a Bluetooth
* codec or GSM modem and thus cannot be read or written to, although it is
* available to be configured with snd_hw_params(), etc and kcontrols in the
* normal alsa manner.
*
* Fast DAI switching:-
*
* The driver can now fast switch between the DAI configurations via a
* an alsa kcontrol. This allows the PCM to remain open.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <asm/div64.h>
#include "wm8753.h"
static int caps_charge = 2000;
module_param(caps_charge, int, 0);
MODULE_PARM_DESC(caps_charge, "WM8753 cap charge time (msecs)");
static int wm8753_hifi_write_dai_fmt(struct snd_soc_component *component,
unsigned int fmt);
static int wm8753_voice_write_dai_fmt(struct snd_soc_component *component,
unsigned int fmt);
/*
* wm8753 register cache
* We can't read the WM8753 register space when we
* are using 2 wire for device control, so we cache them instead.
*/
static const struct reg_default wm8753_reg_defaults[] = {
{ 0x00, 0x0000 },
{ 0x01, 0x0008 },
{ 0x02, 0x0000 },
{ 0x03, 0x000a },
{ 0x04, 0x000a },
{ 0x05, 0x0033 },
{ 0x06, 0x0000 },
{ 0x07, 0x0007 },
{ 0x08, 0x00ff },
{ 0x09, 0x00ff },
{ 0x0a, 0x000f },
{ 0x0b, 0x000f },
{ 0x0c, 0x007b },
{ 0x0d, 0x0000 },
{ 0x0e, 0x0032 },
{ 0x0f, 0x0000 },
{ 0x10, 0x00c3 },
{ 0x11, 0x00c3 },
{ 0x12, 0x00c0 },
{ 0x13, 0x0000 },
{ 0x14, 0x0000 },
{ 0x15, 0x0000 },
{ 0x16, 0x0000 },
{ 0x17, 0x0000 },
{ 0x18, 0x0000 },
{ 0x19, 0x0000 },
{ 0x1a, 0x0000 },
{ 0x1b, 0x0000 },
{ 0x1c, 0x0000 },
{ 0x1d, 0x0000 },
{ 0x1e, 0x0000 },
{ 0x1f, 0x0000 },
{ 0x20, 0x0055 },
{ 0x21, 0x0005 },
{ 0x22, 0x0050 },
{ 0x23, 0x0055 },
{ 0x24, 0x0050 },
{ 0x25, 0x0055 },
{ 0x26, 0x0050 },
{ 0x27, 0x0055 },
{ 0x28, 0x0079 },
{ 0x29, 0x0079 },
{ 0x2a, 0x0079 },
{ 0x2b, 0x0079 },
{ 0x2c, 0x0079 },
{ 0x2d, 0x0000 },
{ 0x2e, 0x0000 },
{ 0x2f, 0x0000 },
{ 0x30, 0x0000 },
{ 0x31, 0x0097 },
{ 0x32, 0x0097 },
{ 0x33, 0x0000 },
{ 0x34, 0x0004 },
{ 0x35, 0x0000 },
{ 0x36, 0x0083 },
{ 0x37, 0x0024 },
{ 0x38, 0x01ba },
{ 0x39, 0x0000 },
{ 0x3a, 0x0083 },
{ 0x3b, 0x0024 },
{ 0x3c, 0x01ba },
{ 0x3d, 0x0000 },
{ 0x3e, 0x0000 },
{ 0x3f, 0x0000 },
};
static bool wm8753_volatile(struct device *dev, unsigned int reg)
{
return reg == WM8753_RESET;
}
/* codec private data */
struct wm8753_priv {
struct regmap *regmap;
unsigned int sysclk;
unsigned int pcmclk;
unsigned int voice_fmt;
unsigned int hifi_fmt;
int dai_func;
struct delayed_work charge_work;
};
#define wm8753_reset(c) snd_soc_component_write(c, WM8753_RESET, 0)
/*
* WM8753 Controls
*/
static const char *wm8753_base[] = {"Linear Control", "Adaptive Boost"};
static const char *wm8753_base_filter[] =
{"130Hz @ 48kHz", "200Hz @ 48kHz", "100Hz @ 16kHz", "400Hz @ 48kHz",
"100Hz @ 8kHz", "200Hz @ 8kHz"};
static const char *wm8753_treble[] = {"8kHz", "4kHz"};
static const char *wm8753_alc_func[] = {"Off", "Right", "Left", "Stereo"};
static const char *wm8753_ng_type[] = {"Constant PGA Gain", "Mute ADC Output"};
static const char *wm8753_3d_func[] = {"Capture", "Playback"};
static const char *wm8753_3d_uc[] = {"2.2kHz", "1.5kHz"};
static const char *wm8753_3d_lc[] = {"200Hz", "500Hz"};
static const char *wm8753_deemp[] = {"None", "32kHz", "44.1kHz", "48kHz"};
static const char *wm8753_mono_mix[] = {"Stereo", "Left", "Right", "Mono"};
static const char *wm8753_dac_phase[] = {"Non Inverted", "Inverted"};
static const char *wm8753_line_mix[] = {"Line 1 + 2", "Line 1 - 2",
"Line 1", "Line 2"};
static const char *wm8753_mono_mux[] = {"Line Mix", "Rx Mix"};
static const char *wm8753_right_mux[] = {"Line 2", "Rx Mix"};
static const char *wm8753_left_mux[] = {"Line 1", "Rx Mix"};
static const char *wm8753_rxmsel[] = {"RXP - RXN", "RXP + RXN", "RXP", "RXN"};
static const char *wm8753_sidetone_mux[] = {"Left PGA", "Mic 1", "Mic 2",
"Right PGA"};
static const char *wm8753_mono2_src[] = {"Inverted Mono 1", "Left", "Right",
"Left + Right"};
static const char *wm8753_out3[] = {"VREF", "ROUT2", "Left + Right"};
static const char *wm8753_out4[] = {"VREF", "Capture ST", "LOUT2"};
static const char *wm8753_radcsel[] = {"PGA", "Line or RXP-RXN", "Sidetone"};
static const char *wm8753_ladcsel[] = {"PGA", "Line or RXP-RXN", "Line"};
static const char *wm8753_mono_adc[] = {"Stereo", "Analogue Mix Left",
"Analogue Mix Right", "Digital Mono Mix"};
static const char *wm8753_adc_hp[] = {"3.4Hz @ 48kHz", "82Hz @ 16k",
"82Hz @ 8kHz", "170Hz @ 8kHz"};
static const char *wm8753_adc_filter[] = {"HiFi", "Voice"};
static const char *wm8753_mic_sel[] = {"Mic 1", "Mic 2", "Mic 3"};
static const char *wm8753_dai_mode[] = {"DAI 0", "DAI 1", "DAI 2", "DAI 3"};
static const char *wm8753_dat_sel[] = {"Stereo", "Left ADC", "Right ADC",
"Channel Swap"};
static const char *wm8753_rout2_phase[] = {"Non Inverted", "Inverted"};
static const struct soc_enum wm8753_enum[] = {
SOC_ENUM_SINGLE(WM8753_BASS, 7, 2, wm8753_base),
SOC_ENUM_SINGLE(WM8753_BASS, 4, 6, wm8753_base_filter),
SOC_ENUM_SINGLE(WM8753_TREBLE, 6, 2, wm8753_treble),
SOC_ENUM_SINGLE(WM8753_ALC1, 7, 4, wm8753_alc_func),
SOC_ENUM_SINGLE(WM8753_NGATE, 1, 2, wm8753_ng_type),
SOC_ENUM_SINGLE(WM8753_3D, 7, 2, wm8753_3d_func),
SOC_ENUM_SINGLE(WM8753_3D, 6, 2, wm8753_3d_uc),
SOC_ENUM_SINGLE(WM8753_3D, 5, 2, wm8753_3d_lc),
SOC_ENUM_SINGLE(WM8753_DAC, 1, 4, wm8753_deemp),
SOC_ENUM_SINGLE(WM8753_DAC, 4, 4, wm8753_mono_mix),
SOC_ENUM_SINGLE(WM8753_DAC, 6, 2, wm8753_dac_phase),
SOC_ENUM_SINGLE(WM8753_INCTL1, 3, 4, wm8753_line_mix),
SOC_ENUM_SINGLE(WM8753_INCTL1, 2, 2, wm8753_mono_mux),
SOC_ENUM_SINGLE(WM8753_INCTL1, 1, 2, wm8753_right_mux),
SOC_ENUM_SINGLE(WM8753_INCTL1, 0, 2, wm8753_left_mux),
SOC_ENUM_SINGLE(WM8753_INCTL2, 6, 4, wm8753_rxmsel),
SOC_ENUM_SINGLE(WM8753_INCTL2, 4, 4, wm8753_sidetone_mux),
SOC_ENUM_SINGLE(WM8753_OUTCTL, 7, 4, wm8753_mono2_src),
SOC_ENUM_SINGLE(WM8753_OUTCTL, 0, 3, wm8753_out3),
SOC_ENUM_SINGLE(WM8753_ADCTL2, 7, 3, wm8753_out4),
SOC_ENUM_SINGLE(WM8753_ADCIN, 2, 3, wm8753_radcsel),
SOC_ENUM_SINGLE(WM8753_ADCIN, 0, 3, wm8753_ladcsel),
SOC_ENUM_SINGLE(WM8753_ADCIN, 4, 4, wm8753_mono_adc),
SOC_ENUM_SINGLE(WM8753_ADC, 2, 4, wm8753_adc_hp),
SOC_ENUM_SINGLE(WM8753_ADC, 4, 2, wm8753_adc_filter),
SOC_ENUM_SINGLE(WM8753_MICBIAS, 6, 3, wm8753_mic_sel),
SOC_ENUM_SINGLE(WM8753_IOCTL, 2, 4, wm8753_dai_mode),
SOC_ENUM_SINGLE(WM8753_ADC, 7, 4, wm8753_dat_sel),
SOC_ENUM_SINGLE(WM8753_OUTCTL, 2, 2, wm8753_rout2_phase),
};
static int wm8753_get_dai(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8753_priv *wm8753 = snd_soc_component_get_drvdata(component);
ucontrol->value.enumerated.item[0] = wm8753->dai_func;
return 0;
}
static int wm8753_set_dai(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8753_priv *wm8753 = snd_soc_component_get_drvdata(component);
u16 ioctl;
if (wm8753->dai_func == ucontrol->value.enumerated.item[0])
return 0;
if (snd_soc_component_active(component))
return -EBUSY;
ioctl = snd_soc_component_read(component, WM8753_IOCTL);
wm8753->dai_func = ucontrol->value.enumerated.item[0];
if (((ioctl >> 2) & 0x3) == wm8753->dai_func)
return 1;
ioctl = (ioctl & 0x1f3) | (wm8753->dai_func << 2);
snd_soc_component_write(component, WM8753_IOCTL, ioctl);
wm8753_hifi_write_dai_fmt(component, wm8753->hifi_fmt);
wm8753_voice_write_dai_fmt(component, wm8753->voice_fmt);
return 1;
}
static const DECLARE_TLV_DB_SCALE(rec_mix_tlv, -1500, 300, 0);
static const DECLARE_TLV_DB_SCALE(mic_preamp_tlv, 1200, 600, 0);
static const DECLARE_TLV_DB_SCALE(adc_tlv, -9750, 50, 1);
static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
static const DECLARE_TLV_DB_RANGE(out_tlv,
/* 0000000 - 0101111 = "Analogue mute" */
0, 48, TLV_DB_SCALE_ITEM(-25500, 0, 0),
48, 127, TLV_DB_SCALE_ITEM(-7300, 100, 0)
);
static const DECLARE_TLV_DB_SCALE(mix_tlv, -1500, 300, 0);
static const DECLARE_TLV_DB_SCALE(voice_mix_tlv, -1200, 300, 0);
static const DECLARE_TLV_DB_SCALE(pga_tlv, -1725, 75, 0);
static const struct snd_kcontrol_new wm8753_snd_controls[] = {
SOC_SINGLE("Hi-Fi DAC Left/Right channel Swap", WM8753_HIFI, 5, 1, 0),
SOC_DOUBLE_R_TLV("PCM Volume", WM8753_LDAC, WM8753_RDAC, 0, 255, 0, dac_tlv),
SOC_DOUBLE_R_TLV("ADC Capture Volume", WM8753_LADC, WM8753_RADC, 0, 255, 0,
adc_tlv),
SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8753_LOUT1V, WM8753_ROUT1V,
0, 127, 0, out_tlv),
SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8753_LOUT2V, WM8753_ROUT2V, 0,
127, 0, out_tlv),
SOC_SINGLE_TLV("Mono Playback Volume", WM8753_MOUTV, 0, 127, 0, out_tlv),
SOC_DOUBLE_R_TLV("Bypass Playback Volume", WM8753_LOUTM1, WM8753_ROUTM1, 4, 7,
1, mix_tlv),
SOC_DOUBLE_R_TLV("Sidetone Playback Volume", WM8753_LOUTM2, WM8753_ROUTM2, 4,
7, 1, mix_tlv),
SOC_DOUBLE_R_TLV("Voice Playback Volume", WM8753_LOUTM2, WM8753_ROUTM2, 0, 7,
1, voice_mix_tlv),
SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8753_LOUT1V, WM8753_ROUT1V, 7,
1, 0),
SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8753_LOUT2V, WM8753_ROUT2V, 7,
1, 0),
SOC_SINGLE_TLV("Mono Bypass Playback Volume", WM8753_MOUTM1, 4, 7, 1, mix_tlv),
SOC_SINGLE_TLV("Mono Sidetone Playback Volume", WM8753_MOUTM2, 4, 7, 1,
mix_tlv),
SOC_SINGLE_TLV("Mono Voice Playback Volume", WM8753_MOUTM2, 0, 7, 1,
voice_mix_tlv),
SOC_SINGLE("Mono Playback ZC Switch", WM8753_MOUTV, 7, 1, 0),
SOC_ENUM("Bass Boost", wm8753_enum[0]),
SOC_ENUM("Bass Filter", wm8753_enum[1]),
SOC_SINGLE("Bass Volume", WM8753_BASS, 0, 15, 1),
SOC_SINGLE("Treble Volume", WM8753_TREBLE, 0, 15, 1),
SOC_ENUM("Treble Cut-off", wm8753_enum[2]),
SOC_DOUBLE_TLV("Sidetone Capture Volume", WM8753_RECMIX1, 0, 4, 7, 1,
rec_mix_tlv),
SOC_SINGLE_TLV("Voice Sidetone Capture Volume", WM8753_RECMIX2, 0, 7, 1,
rec_mix_tlv),
SOC_DOUBLE_R_TLV("Capture Volume", WM8753_LINVOL, WM8753_RINVOL, 0, 63, 0,
pga_tlv),
SOC_DOUBLE_R("Capture ZC Switch", WM8753_LINVOL, WM8753_RINVOL, 6, 1, 0),
SOC_DOUBLE_R("Capture Switch", WM8753_LINVOL, WM8753_RINVOL, 7, 1, 1),
SOC_ENUM("Capture Filter Select", wm8753_enum[23]),
SOC_ENUM("Capture Filter Cut-off", wm8753_enum[24]),
SOC_SINGLE("Capture Filter Switch", WM8753_ADC, 0, 1, 1),
SOC_SINGLE("ALC Capture Target Volume", WM8753_ALC1, 0, 7, 0),
SOC_SINGLE("ALC Capture Max Volume", WM8753_ALC1, 4, 7, 0),
SOC_ENUM("ALC Capture Function", wm8753_enum[3]),
SOC_SINGLE("ALC Capture ZC Switch", WM8753_ALC2, 8, 1, 0),
SOC_SINGLE("ALC Capture Hold Time", WM8753_ALC2, 0, 15, 1),
SOC_SINGLE("ALC Capture Decay Time", WM8753_ALC3, 4, 15, 1),
SOC_SINGLE("ALC Capture Attack Time", WM8753_ALC3, 0, 15, 0),
SOC_SINGLE("ALC Capture NG Threshold", WM8753_NGATE, 3, 31, 0),
SOC_ENUM("ALC Capture NG Type", wm8753_enum[4]),
SOC_SINGLE("ALC Capture NG Switch", WM8753_NGATE, 0, 1, 0),
SOC_ENUM("3D Function", wm8753_enum[5]),
SOC_ENUM("3D Upper Cut-off", wm8753_enum[6]),
SOC_ENUM("3D Lower Cut-off", wm8753_enum[7]),
SOC_SINGLE("3D Volume", WM8753_3D, 1, 15, 0),
SOC_SINGLE("3D Switch", WM8753_3D, 0, 1, 0),
SOC_SINGLE("Capture 6dB Attenuate", WM8753_ADCTL1, 2, 1, 0),
SOC_SINGLE("Playback 6dB Attenuate", WM8753_ADCTL1, 1, 1, 0),
SOC_ENUM("De-emphasis", wm8753_enum[8]),
SOC_ENUM("Playback Mono Mix", wm8753_enum[9]),
SOC_ENUM("Playback Phase", wm8753_enum[10]),
SOC_SINGLE_TLV("Mic2 Capture Volume", WM8753_INCTL1, 7, 3, 0, mic_preamp_tlv),
SOC_SINGLE_TLV("Mic1 Capture Volume", WM8753_INCTL1, 5, 3, 0, mic_preamp_tlv),
SOC_ENUM_EXT("DAI Mode", wm8753_enum[26], wm8753_get_dai, wm8753_set_dai),
SOC_ENUM("ADC Data Select", wm8753_enum[27]),
SOC_ENUM("ROUT2 Phase", wm8753_enum[28]),
};
/*
* _DAPM_ Controls
*/
/* Left Mixer */
static const struct snd_kcontrol_new wm8753_left_mixer_controls[] = {
SOC_DAPM_SINGLE("Voice Playback Switch", WM8753_LOUTM2, 8, 1, 0),
SOC_DAPM_SINGLE("Sidetone Playback Switch", WM8753_LOUTM2, 7, 1, 0),
SOC_DAPM_SINGLE("Left Playback Switch", WM8753_LOUTM1, 8, 1, 0),
SOC_DAPM_SINGLE("Bypass Playback Switch", WM8753_LOUTM1, 7, 1, 0),
};
/* Right mixer */
static const struct snd_kcontrol_new wm8753_right_mixer_controls[] = {
SOC_DAPM_SINGLE("Voice Playback Switch", WM8753_ROUTM2, 8, 1, 0),
SOC_DAPM_SINGLE("Sidetone Playback Switch", WM8753_ROUTM2, 7, 1, 0),
SOC_DAPM_SINGLE("Right Playback Switch", WM8753_ROUTM1, 8, 1, 0),
SOC_DAPM_SINGLE("Bypass Playback Switch", WM8753_ROUTM1, 7, 1, 0),
};
/* Mono mixer */
static const struct snd_kcontrol_new wm8753_mono_mixer_controls[] = {
SOC_DAPM_SINGLE("Left Playback Switch", WM8753_MOUTM1, 8, 1, 0),
SOC_DAPM_SINGLE("Right Playback Switch", WM8753_MOUTM2, 8, 1, 0),
SOC_DAPM_SINGLE("Voice Playback Switch", WM8753_MOUTM2, 3, 1, 0),
SOC_DAPM_SINGLE("Sidetone Playback Switch", WM8753_MOUTM2, 7, 1, 0),
SOC_DAPM_SINGLE("Bypass Playback Switch", WM8753_MOUTM1, 7, 1, 0),
};
/* Mono 2 Mux */
static const struct snd_kcontrol_new wm8753_mono2_controls =
SOC_DAPM_ENUM("Route", wm8753_enum[17]);
/* Out 3 Mux */
static const struct snd_kcontrol_new wm8753_out3_controls =
SOC_DAPM_ENUM("Route", wm8753_enum[18]);
/* Out 4 Mux */
static const struct snd_kcontrol_new wm8753_out4_controls =
SOC_DAPM_ENUM("Route", wm8753_enum[19]);
/* ADC Mono Mix */
static const struct snd_kcontrol_new wm8753_adc_mono_controls =
SOC_DAPM_ENUM("Route", wm8753_enum[22]);
/* Record mixer */
static const struct snd_kcontrol_new wm8753_record_mixer_controls[] = {
SOC_DAPM_SINGLE("Voice Capture Switch", WM8753_RECMIX2, 3, 1, 0),
SOC_DAPM_SINGLE("Left Capture Switch", WM8753_RECMIX1, 3, 1, 0),
SOC_DAPM_SINGLE("Right Capture Switch", WM8753_RECMIX1, 7, 1, 0),
};
/* Left ADC mux */
static const struct snd_kcontrol_new wm8753_adc_left_controls =
SOC_DAPM_ENUM("Route", wm8753_enum[21]);
/* Right ADC mux */
static const struct snd_kcontrol_new wm8753_adc_right_controls =
SOC_DAPM_ENUM("Route", wm8753_enum[20]);
/* MIC mux */
static const struct snd_kcontrol_new wm8753_mic_mux_controls =
SOC_DAPM_ENUM("Route", wm8753_enum[16]);
/* ALC mixer */
static const struct snd_kcontrol_new wm8753_alc_mixer_controls[] = {
SOC_DAPM_SINGLE("Line Capture Switch", WM8753_INCTL2, 3, 1, 0),
SOC_DAPM_SINGLE("Mic2 Capture Switch", WM8753_INCTL2, 2, 1, 0),
SOC_DAPM_SINGLE("Mic1 Capture Switch", WM8753_INCTL2, 1, 1, 0),
SOC_DAPM_SINGLE("Rx Capture Switch", WM8753_INCTL2, 0, 1, 0),
};
/* Left Line mux */
static const struct snd_kcontrol_new wm8753_line_left_controls =
SOC_DAPM_ENUM("Route", wm8753_enum[14]);
/* Right Line mux */
static const struct snd_kcontrol_new wm8753_line_right_controls =
SOC_DAPM_ENUM("Route", wm8753_enum[13]);
/* Mono Line mux */
static const struct snd_kcontrol_new wm8753_line_mono_controls =
SOC_DAPM_ENUM("Route", wm8753_enum[12]);
/* Line mux and mixer */
static const struct snd_kcontrol_new wm8753_line_mux_mix_controls =
SOC_DAPM_ENUM("Route", wm8753_enum[11]);
/* Rx mux and mixer */
static const struct snd_kcontrol_new wm8753_rx_mux_mix_controls =
SOC_DAPM_ENUM("Route", wm8753_enum[15]);
/* Mic Selector Mux */
static const struct snd_kcontrol_new wm8753_mic_sel_mux_controls =
SOC_DAPM_ENUM("Route", wm8753_enum[25]);
static const struct snd_soc_dapm_widget wm8753_dapm_widgets[] = {
SND_SOC_DAPM_MICBIAS("Mic Bias", WM8753_PWR1, 5, 0),
SND_SOC_DAPM_MIXER("Left Mixer", WM8753_PWR4, 0, 0,
&wm8753_left_mixer_controls[0], ARRAY_SIZE(wm8753_left_mixer_controls)),
SND_SOC_DAPM_PGA("Left Out 1", WM8753_PWR3, 8, 0, NULL, 0),
SND_SOC_DAPM_PGA("Left Out 2", WM8753_PWR3, 6, 0, NULL, 0),
SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback", WM8753_PWR1, 3, 0),
SND_SOC_DAPM_OUTPUT("LOUT1"),
SND_SOC_DAPM_OUTPUT("LOUT2"),
SND_SOC_DAPM_MIXER("Right Mixer", WM8753_PWR4, 1, 0,
&wm8753_right_mixer_controls[0], ARRAY_SIZE(wm8753_right_mixer_controls)),
SND_SOC_DAPM_PGA("Right Out 1", WM8753_PWR3, 7, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Out 2", WM8753_PWR3, 5, 0, NULL, 0),
SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback", WM8753_PWR1, 2, 0),
SND_SOC_DAPM_OUTPUT("ROUT1"),
SND_SOC_DAPM_OUTPUT("ROUT2"),
SND_SOC_DAPM_MIXER("Mono Mixer", WM8753_PWR4, 2, 0,
&wm8753_mono_mixer_controls[0], ARRAY_SIZE(wm8753_mono_mixer_controls)),
SND_SOC_DAPM_PGA("Mono Out 1", WM8753_PWR3, 2, 0, NULL, 0),
SND_SOC_DAPM_PGA("Mono Out 2", WM8753_PWR3, 1, 0, NULL, 0),
SND_SOC_DAPM_DAC("Voice DAC", "Voice Playback", WM8753_PWR1, 4, 0),
SND_SOC_DAPM_OUTPUT("MONO1"),
SND_SOC_DAPM_MUX("Mono 2 Mux", SND_SOC_NOPM, 0, 0, &wm8753_mono2_controls),
SND_SOC_DAPM_OUTPUT("MONO2"),
SND_SOC_DAPM_MIXER("Out3 Left + Right", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX("Out3 Mux", SND_SOC_NOPM, 0, 0, &wm8753_out3_controls),
SND_SOC_DAPM_PGA("Out 3", WM8753_PWR3, 4, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("OUT3"),
SND_SOC_DAPM_MUX("Out4 Mux", SND_SOC_NOPM, 0, 0, &wm8753_out4_controls),
SND_SOC_DAPM_PGA("Out 4", WM8753_PWR3, 3, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("OUT4"),
SND_SOC_DAPM_MIXER("Playback Mixer", WM8753_PWR4, 3, 0,
&wm8753_record_mixer_controls[0],
ARRAY_SIZE(wm8753_record_mixer_controls)),
SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8753_PWR2, 3, 0),
SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8753_PWR2, 2, 0),
SND_SOC_DAPM_MUX("Capture Left Mixer", SND_SOC_NOPM, 0, 0,
&wm8753_adc_mono_controls),
SND_SOC_DAPM_MUX("Capture Right Mixer", SND_SOC_NOPM, 0, 0,
&wm8753_adc_mono_controls),
SND_SOC_DAPM_MUX("Capture Left Mux", SND_SOC_NOPM, 0, 0,
&wm8753_adc_left_controls),
SND_SOC_DAPM_MUX("Capture Right Mux", SND_SOC_NOPM, 0, 0,
&wm8753_adc_right_controls),
SND_SOC_DAPM_MUX("Mic Sidetone Mux", SND_SOC_NOPM, 0, 0,
&wm8753_mic_mux_controls),
SND_SOC_DAPM_PGA("Left Capture Volume", WM8753_PWR2, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Capture Volume", WM8753_PWR2, 4, 0, NULL, 0),
SND_SOC_DAPM_MIXER("ALC Mixer", WM8753_PWR2, 6, 0,
&wm8753_alc_mixer_controls[0], ARRAY_SIZE(wm8753_alc_mixer_controls)),
SND_SOC_DAPM_MUX("Line Left Mux", SND_SOC_NOPM, 0, 0,
&wm8753_line_left_controls),
SND_SOC_DAPM_MUX("Line Right Mux", SND_SOC_NOPM, 0, 0,
&wm8753_line_right_controls),
SND_SOC_DAPM_MUX("Line Mono Mux", SND_SOC_NOPM, 0, 0,
&wm8753_line_mono_controls),
SND_SOC_DAPM_MUX("Line Mixer", WM8753_PWR2, 0, 0,
&wm8753_line_mux_mix_controls),
SND_SOC_DAPM_MUX("Rx Mixer", WM8753_PWR2, 1, 0,
&wm8753_rx_mux_mix_controls),
SND_SOC_DAPM_PGA("Mic 1 Volume", WM8753_PWR2, 8, 0, NULL, 0),
SND_SOC_DAPM_PGA("Mic 2 Volume", WM8753_PWR2, 7, 0, NULL, 0),
SND_SOC_DAPM_MUX("Mic Selection Mux", SND_SOC_NOPM, 0, 0,
&wm8753_mic_sel_mux_controls),
SND_SOC_DAPM_INPUT("LINE1"),
SND_SOC_DAPM_INPUT("LINE2"),
SND_SOC_DAPM_INPUT("RXP"),
SND_SOC_DAPM_INPUT("RXN"),
SND_SOC_DAPM_INPUT("ACIN"),
SND_SOC_DAPM_OUTPUT("ACOP"),
SND_SOC_DAPM_INPUT("MIC1N"),
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_INPUT("MIC2N"),
SND_SOC_DAPM_INPUT("MIC2"),
SND_SOC_DAPM_VMID("VREF"),
};
static const struct snd_soc_dapm_route wm8753_dapm_routes[] = {
/* left mixer */
{"Left Mixer", "Left Playback Switch", "Left DAC"},
{"Left Mixer", "Voice Playback Switch", "Voice DAC"},
{"Left Mixer", "Sidetone Playback Switch", "Mic Sidetone Mux"},
{"Left Mixer", "Bypass Playback Switch", "Line Left Mux"},
/* right mixer */
{"Right Mixer", "Right Playback Switch", "Right DAC"},
{"Right Mixer", "Voice Playback Switch", "Voice DAC"},
{"Right Mixer", "Sidetone Playback Switch", "Mic Sidetone Mux"},
{"Right Mixer", "Bypass Playback Switch", "Line Right Mux"},
/* mono mixer */
{"Mono Mixer", "Voice Playback Switch", "Voice DAC"},
{"Mono Mixer", "Left Playback Switch", "Left DAC"},
{"Mono Mixer", "Right Playback Switch", "Right DAC"},
{"Mono Mixer", "Sidetone Playback Switch", "Mic Sidetone Mux"},
{"Mono Mixer", "Bypass Playback Switch", "Line Mono Mux"},
/* left out */
{"Left Out 1", NULL, "Left Mixer"},
{"Left Out 2", NULL, "Left Mixer"},
{"LOUT1", NULL, "Left Out 1"},
{"LOUT2", NULL, "Left Out 2"},
/* right out */
{"Right Out 1", NULL, "Right Mixer"},
{"Right Out 2", NULL, "Right Mixer"},
{"ROUT1", NULL, "Right Out 1"},
{"ROUT2", NULL, "Right Out 2"},
/* mono 1 out */
{"Mono Out 1", NULL, "Mono Mixer"},
{"MONO1", NULL, "Mono Out 1"},
/* mono 2 out */
{"Mono 2 Mux", "Left + Right", "Out3 Left + Right"},
{"Mono 2 Mux", "Inverted Mono 1", "MONO1"},
{"Mono 2 Mux", "Left", "Left Mixer"},
{"Mono 2 Mux", "Right", "Right Mixer"},
{"Mono Out 2", NULL, "Mono 2 Mux"},
{"MONO2", NULL, "Mono Out 2"},
/* out 3 */
{"Out3 Left + Right", NULL, "Left Mixer"},
{"Out3 Left + Right", NULL, "Right Mixer"},
{"Out3 Mux", "VREF", "VREF"},
{"Out3 Mux", "Left + Right", "Out3 Left + Right"},
{"Out3 Mux", "ROUT2", "ROUT2"},
{"Out 3", NULL, "Out3 Mux"},
{"OUT3", NULL, "Out 3"},
/* out 4 */
{"Out4 Mux", "VREF", "VREF"},
{"Out4 Mux", "Capture ST", "Playback Mixer"},
{"Out4 Mux", "LOUT2", "LOUT2"},
{"Out 4", NULL, "Out4 Mux"},
{"OUT4", NULL, "Out 4"},
/* record mixer */
{"Playback Mixer", "Left Capture Switch", "Left Mixer"},
{"Playback Mixer", "Voice Capture Switch", "Mono Mixer"},
{"Playback Mixer", "Right Capture Switch", "Right Mixer"},
/* Mic/SideTone Mux */
{"Mic Sidetone Mux", "Left PGA", "Left Capture Volume"},
{"Mic Sidetone Mux", "Right PGA", "Right Capture Volume"},
{"Mic Sidetone Mux", "Mic 1", "Mic 1 Volume"},
{"Mic Sidetone Mux", "Mic 2", "Mic 2 Volume"},
/* Capture Left Mux */
{"Capture Left Mux", "PGA", "Left Capture Volume"},
{"Capture Left Mux", "Line or RXP-RXN", "Line Left Mux"},
{"Capture Left Mux", "Line", "LINE1"},
/* Capture Right Mux */
{"Capture Right Mux", "PGA", "Right Capture Volume"},
{"Capture Right Mux", "Line or RXP-RXN", "Line Right Mux"},
{"Capture Right Mux", "Sidetone", "Playback Mixer"},
/* Mono Capture mixer-mux */
{"Capture Right Mixer", "Stereo", "Capture Right Mux"},
{"Capture Left Mixer", "Stereo", "Capture Left Mux"},
{"Capture Left Mixer", "Analogue Mix Left", "Capture Left Mux"},
{"Capture Left Mixer", "Analogue Mix Left", "Capture Right Mux"},
{"Capture Right Mixer", "Analogue Mix Right", "Capture Left Mux"},
{"Capture Right Mixer", "Analogue Mix Right", "Capture Right Mux"},
{"Capture Left Mixer", "Digital Mono Mix", "Capture Left Mux"},
{"Capture Left Mixer", "Digital Mono Mix", "Capture Right Mux"},
{"Capture Right Mixer", "Digital Mono Mix", "Capture Left Mux"},
{"Capture Right Mixer", "Digital Mono Mix", "Capture Right Mux"},
/* ADC */
{"Left ADC", NULL, "Capture Left Mixer"},
{"Right ADC", NULL, "Capture Right Mixer"},
/* Left Capture Volume */
{"Left Capture Volume", NULL, "ACIN"},
/* Right Capture Volume */
{"Right Capture Volume", NULL, "Mic 2 Volume"},
/* ALC Mixer */
{"ALC Mixer", "Line Capture Switch", "Line Mixer"},
{"ALC Mixer", "Mic2 Capture Switch", "Mic 2 Volume"},
{"ALC Mixer", "Mic1 Capture Switch", "Mic 1 Volume"},
{"ALC Mixer", "Rx Capture Switch", "Rx Mixer"},
/* Line Left Mux */
{"Line Left Mux", "Line 1", "LINE1"},
{"Line Left Mux", "Rx Mix", "Rx Mixer"},
/* Line Right Mux */
{"Line Right Mux", "Line 2", "LINE2"},
{"Line Right Mux", "Rx Mix", "Rx Mixer"},
/* Line Mono Mux */
{"Line Mono Mux", "Line Mix", "Line Mixer"},
{"Line Mono Mux", "Rx Mix", "Rx Mixer"},
/* Line Mixer/Mux */
{"Line Mixer", "Line 1 + 2", "LINE1"},
{"Line Mixer", "Line 1 - 2", "LINE1"},
{"Line Mixer", "Line 1 + 2", "LINE2"},
{"Line Mixer", "Line 1 - 2", "LINE2"},
{"Line Mixer", "Line 1", "LINE1"},
{"Line Mixer", "Line 2", "LINE2"},
/* Rx Mixer/Mux */
{"Rx Mixer", "RXP - RXN", "RXP"},
{"Rx Mixer", "RXP + RXN", "RXP"},
{"Rx Mixer", "RXP - RXN", "RXN"},
{"Rx Mixer", "RXP + RXN", "RXN"},
{"Rx Mixer", "RXP", "RXP"},
{"Rx Mixer", "RXN", "RXN"},
/* Mic 1 Volume */
{"Mic 1 Volume", NULL, "MIC1N"},
{"Mic 1 Volume", NULL, "Mic Selection Mux"},
/* Mic 2 Volume */
{"Mic 2 Volume", NULL, "MIC2N"},
{"Mic 2 Volume", NULL, "MIC2"},
/* Mic Selector Mux */
{"Mic Selection Mux", "Mic 1", "MIC1"},
{"Mic Selection Mux", "Mic 2", "MIC2N"},
{"Mic Selection Mux", "Mic 3", "MIC2"},
/* ACOP */
{"ACOP", NULL, "ALC Mixer"},
};
/* PLL divisors */
struct _pll_div {
u32 div2:1;
u32 n:4;
u32 k:24;
};
/* The size in bits of the pll divide multiplied by 10
* to allow rounding later */
#define FIXED_PLL_SIZE ((1 << 22) * 10)
static void pll_factors(struct _pll_div *pll_div, unsigned int target,
unsigned int source)
{
u64 Kpart;
unsigned int K, Ndiv, Nmod;
Ndiv = target / source;
if (Ndiv < 6) {
source >>= 1;
pll_div->div2 = 1;
Ndiv = target / source;
} else
pll_div->div2 = 0;
if ((Ndiv < 6) || (Ndiv > 12))
printk(KERN_WARNING
"wm8753: unsupported N = %u\n", Ndiv);
pll_div->n = Ndiv;
Nmod = target % source;
Kpart = FIXED_PLL_SIZE * (long long)Nmod;
do_div(Kpart, source);
K = Kpart & 0xFFFFFFFF;
/* Check if we need to round */
if ((K % 10) >= 5)
K += 5;
/* Move down to proper range now rounding is done */
K /= 10;
pll_div->k = K;
}
static int wm8753_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
int source, unsigned int freq_in, unsigned int freq_out)
{
u16 reg, enable;
int offset;
struct snd_soc_component *component = codec_dai->component;
if (pll_id < WM8753_PLL1 || pll_id > WM8753_PLL2)
return -ENODEV;
if (pll_id == WM8753_PLL1) {
offset = 0;
enable = 0x10;
reg = snd_soc_component_read(component, WM8753_CLOCK) & 0xffef;
} else {
offset = 4;
enable = 0x8;
reg = snd_soc_component_read(component, WM8753_CLOCK) & 0xfff7;
}
if (!freq_in || !freq_out) {
/* disable PLL */
snd_soc_component_write(component, WM8753_PLL1CTL1 + offset, 0x0026);
snd_soc_component_write(component, WM8753_CLOCK, reg);
return 0;
} else {
u16 value = 0;
struct _pll_div pll_div;
pll_factors(&pll_div, freq_out * 8, freq_in);
/* set up N and K PLL divisor ratios */
/* bits 8:5 = PLL_N, bits 3:0 = PLL_K[21:18] */
value = (pll_div.n << 5) + ((pll_div.k & 0x3c0000) >> 18);
snd_soc_component_write(component, WM8753_PLL1CTL2 + offset, value);
/* bits 8:0 = PLL_K[17:9] */
value = (pll_div.k & 0x03fe00) >> 9;
snd_soc_component_write(component, WM8753_PLL1CTL3 + offset, value);
/* bits 8:0 = PLL_K[8:0] */
value = pll_div.k & 0x0001ff;
snd_soc_component_write(component, WM8753_PLL1CTL4 + offset, value);
/* set PLL as input and enable */
snd_soc_component_write(component, WM8753_PLL1CTL1 + offset, 0x0027 |
(pll_div.div2 << 3));
snd_soc_component_write(component, WM8753_CLOCK, reg | enable);
}
return 0;
}
struct _coeff_div {
u32 mclk;
u32 rate;
u8 sr:5;
u8 usb:1;
};
/* codec hifi mclk (after PLL) clock divider coefficients */
static const struct _coeff_div coeff_div[] = {
/* 8k */
{12288000, 8000, 0x6, 0x0},
{11289600, 8000, 0x16, 0x0},
{18432000, 8000, 0x7, 0x0},
{16934400, 8000, 0x17, 0x0},
{12000000, 8000, 0x6, 0x1},
/* 11.025k */
{11289600, 11025, 0x18, 0x0},
{16934400, 11025, 0x19, 0x0},
{12000000, 11025, 0x19, 0x1},
/* 16k */
{12288000, 16000, 0xa, 0x0},
{18432000, 16000, 0xb, 0x0},
{12000000, 16000, 0xa, 0x1},
/* 22.05k */
{11289600, 22050, 0x1a, 0x0},
{16934400, 22050, 0x1b, 0x0},
{12000000, 22050, 0x1b, 0x1},
/* 32k */
{12288000, 32000, 0xc, 0x0},
{18432000, 32000, 0xd, 0x0},
{12000000, 32000, 0xa, 0x1},
/* 44.1k */
{11289600, 44100, 0x10, 0x0},
{16934400, 44100, 0x11, 0x0},
{12000000, 44100, 0x11, 0x1},
/* 48k */
{12288000, 48000, 0x0, 0x0},
{18432000, 48000, 0x1, 0x0},
{12000000, 48000, 0x0, 0x1},
/* 88.2k */
{11289600, 88200, 0x1e, 0x0},
{16934400, 88200, 0x1f, 0x0},
{12000000, 88200, 0x1f, 0x1},
/* 96k */
{12288000, 96000, 0xe, 0x0},
{18432000, 96000, 0xf, 0x0},
{12000000, 96000, 0xe, 0x1},
};
static int get_coeff(int mclk, int rate)
{
int i;
for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
return i;
}
return -EINVAL;
}
/*
* Clock after PLL and dividers
*/
static int wm8753_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct wm8753_priv *wm8753 = snd_soc_component_get_drvdata(component);
switch (freq) {
case 11289600:
case 12000000:
case 12288000:
case 16934400:
case 18432000:
if (clk_id == WM8753_MCLK) {
wm8753->sysclk = freq;
return 0;
} else if (clk_id == WM8753_PCMCLK) {
wm8753->pcmclk = freq;
return 0;
}
break;
}
return -EINVAL;
}
/*
* Set's ADC and Voice DAC format.
*/
static int wm8753_vdac_adc_set_dai_fmt(struct snd_soc_component *component,
unsigned int fmt)
{
u16 voice = snd_soc_component_read(component, WM8753_PCM) & 0x01ec;
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
voice |= 0x0002;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
voice |= 0x0001;
break;
case SND_SOC_DAIFMT_DSP_A:
voice |= 0x0003;
break;
case SND_SOC_DAIFMT_DSP_B:
voice |= 0x0013;
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, WM8753_PCM, voice);
return 0;
}
/*
* Set PCM DAI bit size and sample rate.
*/
static int wm8753_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm8753_priv *wm8753 = snd_soc_component_get_drvdata(component);
u16 voice = snd_soc_component_read(component, WM8753_PCM) & 0x01f3;
u16 srate = snd_soc_component_read(component, WM8753_SRATE1) & 0x017f;
/* bit size */
switch (params_width(params)) {
case 16:
break;
case 20:
voice |= 0x0004;
break;
case 24:
voice |= 0x0008;
break;
case 32:
voice |= 0x000c;
break;
}
/* sample rate */
if (params_rate(params) * 384 == wm8753->pcmclk)
srate |= 0x80;
snd_soc_component_write(component, WM8753_SRATE1, srate);
snd_soc_component_write(component, WM8753_PCM, voice);
return 0;
}
/*
* Set's PCM dai fmt and BCLK.
*/
static int wm8753_pcm_set_dai_fmt(struct snd_soc_component *component,
unsigned int fmt)
{
u16 voice, ioctl;
voice = snd_soc_component_read(component, WM8753_PCM) & 0x011f;
ioctl = snd_soc_component_read(component, WM8753_IOCTL) & 0x015d;
/* set master/slave audio interface */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
break;
case SND_SOC_DAIFMT_CBM_CFM:
ioctl |= 0x2;
fallthrough;
case SND_SOC_DAIFMT_CBM_CFS:
voice |= 0x0040;
break;
default:
return -EINVAL;
}
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B:
/* frame inversion not valid for DSP modes */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
voice |= 0x0080;
break;
default:
return -EINVAL;
}
break;
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_RIGHT_J:
case SND_SOC_DAIFMT_LEFT_J:
voice &= ~0x0010;
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
voice |= 0x0090;
break;
case SND_SOC_DAIFMT_IB_NF:
voice |= 0x0080;
break;
case SND_SOC_DAIFMT_NB_IF:
voice |= 0x0010;
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, WM8753_PCM, voice);
snd_soc_component_write(component, WM8753_IOCTL, ioctl);
return 0;
}
static int wm8753_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
int div_id, int div)
{
struct snd_soc_component *component = codec_dai->component;
u16 reg;
switch (div_id) {
case WM8753_PCMDIV:
reg = snd_soc_component_read(component, WM8753_CLOCK) & 0x003f;
snd_soc_component_write(component, WM8753_CLOCK, reg | div);
break;
case WM8753_BCLKDIV:
reg = snd_soc_component_read(component, WM8753_SRATE2) & 0x01c7;
snd_soc_component_write(component, WM8753_SRATE2, reg | div);
break;
case WM8753_VXCLKDIV:
reg = snd_soc_component_read(component, WM8753_SRATE2) & 0x003f;
snd_soc_component_write(component, WM8753_SRATE2, reg | div);
break;
default:
return -EINVAL;
}
return 0;
}
/*
* Set's HiFi DAC format.
*/
static int wm8753_hdac_set_dai_fmt(struct snd_soc_component *component,
unsigned int fmt)
{
u16 hifi = snd_soc_component_read(component, WM8753_HIFI) & 0x01e0;
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
hifi |= 0x0002;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
hifi |= 0x0001;
break;
case SND_SOC_DAIFMT_DSP_A:
hifi |= 0x0003;
break;
case SND_SOC_DAIFMT_DSP_B:
hifi |= 0x0013;
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, WM8753_HIFI, hifi);
return 0;
}
/*
* Set's I2S DAI format.
*/
static int wm8753_i2s_set_dai_fmt(struct snd_soc_component *component,
unsigned int fmt)
{
u16 ioctl, hifi;
hifi = snd_soc_component_read(component, WM8753_HIFI) & 0x013f;
ioctl = snd_soc_component_read(component, WM8753_IOCTL) & 0x00ae;
/* set master/slave audio interface */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
break;
case SND_SOC_DAIFMT_CBM_CFM:
ioctl |= 0x1;
fallthrough;
case SND_SOC_DAIFMT_CBM_CFS:
hifi |= 0x0040;
break;
default:
return -EINVAL;
}
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B:
/* frame inversion not valid for DSP modes */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
hifi |= 0x0080;
break;
default:
return -EINVAL;
}
break;
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_RIGHT_J:
case SND_SOC_DAIFMT_LEFT_J:
hifi &= ~0x0010;
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
hifi |= 0x0090;
break;
case SND_SOC_DAIFMT_IB_NF:
hifi |= 0x0080;
break;
case SND_SOC_DAIFMT_NB_IF:
hifi |= 0x0010;
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, WM8753_HIFI, hifi);
snd_soc_component_write(component, WM8753_IOCTL, ioctl);
return 0;
}
/*
* Set PCM DAI bit size and sample rate.
*/
static int wm8753_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm8753_priv *wm8753 = snd_soc_component_get_drvdata(component);
u16 srate = snd_soc_component_read(component, WM8753_SRATE1) & 0x01c0;
u16 hifi = snd_soc_component_read(component, WM8753_HIFI) & 0x01f3;
int coeff;
/* is digital filter coefficient valid ? */
coeff = get_coeff(wm8753->sysclk, params_rate(params));
if (coeff < 0) {
printk(KERN_ERR "wm8753 invalid MCLK or rate\n");
return coeff;
}
snd_soc_component_write(component, WM8753_SRATE1, srate | (coeff_div[coeff].sr << 1) |
coeff_div[coeff].usb);
/* bit size */
switch (params_width(params)) {
case 16:
break;
case 20:
hifi |= 0x0004;
break;
case 24:
hifi |= 0x0008;
break;
case 32:
hifi |= 0x000c;
break;
}
snd_soc_component_write(component, WM8753_HIFI, hifi);
return 0;
}
static int wm8753_mode1v_set_dai_fmt(struct snd_soc_component *component,
unsigned int fmt)
{
u16 clock;
/* set clk source as pcmclk */
clock = snd_soc_component_read(component, WM8753_CLOCK) & 0xfffb;
snd_soc_component_write(component, WM8753_CLOCK, clock);
return wm8753_vdac_adc_set_dai_fmt(component, fmt);
}
static int wm8753_mode1h_set_dai_fmt(struct snd_soc_component *component,
unsigned int fmt)
{
return wm8753_hdac_set_dai_fmt(component, fmt);
}
static int wm8753_mode2_set_dai_fmt(struct snd_soc_component *component,
unsigned int fmt)
{
u16 clock;
/* set clk source as pcmclk */
clock = snd_soc_component_read(component, WM8753_CLOCK) & 0xfffb;
snd_soc_component_write(component, WM8753_CLOCK, clock);
return wm8753_vdac_adc_set_dai_fmt(component, fmt);
}
static int wm8753_mode3_4_set_dai_fmt(struct snd_soc_component *component,
unsigned int fmt)
{
u16 clock;
/* set clk source as mclk */
clock = snd_soc_component_read(component, WM8753_CLOCK) & 0xfffb;
snd_soc_component_write(component, WM8753_CLOCK, clock | 0x4);
if (wm8753_hdac_set_dai_fmt(component, fmt) < 0)
return -EINVAL;
return wm8753_vdac_adc_set_dai_fmt(component, fmt);
}
static int wm8753_hifi_write_dai_fmt(struct snd_soc_component *component,
unsigned int fmt)
{
struct wm8753_priv *wm8753 = snd_soc_component_get_drvdata(component);
int ret = 0;
switch (wm8753->dai_func) {
case 0:
ret = wm8753_mode1h_set_dai_fmt(component, fmt);
break;
case 1:
ret = wm8753_mode2_set_dai_fmt(component, fmt);
break;
case 2:
case 3:
ret = wm8753_mode3_4_set_dai_fmt(component, fmt);
break;
default:
break;
}
if (ret)
return ret;
return wm8753_i2s_set_dai_fmt(component, fmt);
}
static int wm8753_hifi_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct wm8753_priv *wm8753 = snd_soc_component_get_drvdata(component);
wm8753->hifi_fmt = fmt;
return wm8753_hifi_write_dai_fmt(component, fmt);
};
static int wm8753_voice_write_dai_fmt(struct snd_soc_component *component,
unsigned int fmt)
{
struct wm8753_priv *wm8753 = snd_soc_component_get_drvdata(component);
int ret = 0;
if (wm8753->dai_func != 0)
return 0;
ret = wm8753_mode1v_set_dai_fmt(component, fmt);
if (ret)
return ret;
ret = wm8753_pcm_set_dai_fmt(component, fmt);
if (ret)
return ret;
return 0;
};
static int wm8753_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct wm8753_priv *wm8753 = snd_soc_component_get_drvdata(component);
wm8753->voice_fmt = fmt;
return wm8753_voice_write_dai_fmt(component, fmt);
};
static int wm8753_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
u16 mute_reg = snd_soc_component_read(component, WM8753_DAC) & 0xfff7;
struct wm8753_priv *wm8753 = snd_soc_component_get_drvdata(component);
/* the digital mute covers the HiFi and Voice DAC's on the WM8753.
* make sure we check if they are not both active when we mute */
if (mute && wm8753->dai_func == 1) {
if (!snd_soc_component_active(component))
snd_soc_component_write(component, WM8753_DAC, mute_reg | 0x8);
} else {
if (mute)
snd_soc_component_write(component, WM8753_DAC, mute_reg | 0x8);
else
snd_soc_component_write(component, WM8753_DAC, mute_reg);
}
return 0;
}
static void wm8753_charge_work(struct work_struct *work)
{
struct wm8753_priv *wm8753 =
container_of(work, struct wm8753_priv, charge_work.work);
/* Set to 500k */
regmap_update_bits(wm8753->regmap, WM8753_PWR1, 0x0180, 0x0100);
}
static int wm8753_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct wm8753_priv *wm8753 = snd_soc_component_get_drvdata(component);
u16 pwr_reg = snd_soc_component_read(component, WM8753_PWR1) & 0xfe3e;
switch (level) {
case SND_SOC_BIAS_ON:
/* set vmid to 50k and unmute dac */
snd_soc_component_write(component, WM8753_PWR1, pwr_reg | 0x00c0);
break;
case SND_SOC_BIAS_PREPARE:
/* Wait until fully charged */
flush_delayed_work(&wm8753->charge_work);
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
/* set vmid to 5k for quick power up */
snd_soc_component_write(component, WM8753_PWR1, pwr_reg | 0x01c1);
schedule_delayed_work(&wm8753->charge_work,
msecs_to_jiffies(caps_charge));
} else {
/* mute dac and set vmid to 500k, enable VREF */
snd_soc_component_write(component, WM8753_PWR1, pwr_reg | 0x0141);
}
break;
case SND_SOC_BIAS_OFF:
cancel_delayed_work_sync(&wm8753->charge_work);
snd_soc_component_write(component, WM8753_PWR1, 0x0001);
break;
}
return 0;
}
#define WM8753_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
#define WM8753_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE)
/*
* The WM8753 supports up to 4 different and mutually exclusive DAI
* configurations. This gives 2 PCM's available for use, hifi and voice.
* NOTE: The Voice PCM cannot play or capture audio to the CPU as it's DAI
* is connected between the wm8753 and a BT codec or GSM modem.
*
* 1. Voice over PCM DAI - HIFI DAC over HIFI DAI
* 2. Voice over HIFI DAI - HIFI disabled
* 3. Voice disabled - HIFI over HIFI
* 4. Voice disabled - HIFI over HIFI, uses voice DAI LRC for capture
*/
static const struct snd_soc_dai_ops wm8753_dai_ops_hifi_mode = {
.hw_params = wm8753_i2s_hw_params,
.mute_stream = wm8753_mute,
.set_fmt = wm8753_hifi_set_dai_fmt,
.set_clkdiv = wm8753_set_dai_clkdiv,
.set_pll = wm8753_set_dai_pll,
.set_sysclk = wm8753_set_dai_sysclk,
.no_capture_mute = 1,
};
static const struct snd_soc_dai_ops wm8753_dai_ops_voice_mode = {
.hw_params = wm8753_pcm_hw_params,
.mute_stream = wm8753_mute,
.set_fmt = wm8753_voice_set_dai_fmt,
.set_clkdiv = wm8753_set_dai_clkdiv,
.set_pll = wm8753_set_dai_pll,
.set_sysclk = wm8753_set_dai_sysclk,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver wm8753_dai[] = {
/* DAI HiFi mode 1 */
{ .name = "wm8753-hifi",
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM8753_RATES,
.formats = WM8753_FORMATS
},
.capture = { /* dummy for fast DAI switching */
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM8753_RATES,
.formats = WM8753_FORMATS
},
.ops = &wm8753_dai_ops_hifi_mode,
},
/* DAI Voice mode 1 */
{ .name = "wm8753-voice",
.playback = {
.stream_name = "Voice Playback",
.channels_min = 1,
.channels_max = 1,
.rates = WM8753_RATES,
.formats = WM8753_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM8753_RATES,
.formats = WM8753_FORMATS,
},
.ops = &wm8753_dai_ops_voice_mode,
},
};
static int wm8753_resume(struct snd_soc_component *component)
{
struct wm8753_priv *wm8753 = snd_soc_component_get_drvdata(component);
regcache_sync(wm8753->regmap);
return 0;
}
static int wm8753_probe(struct snd_soc_component *component)
{
struct wm8753_priv *wm8753 = snd_soc_component_get_drvdata(component);
int ret;
INIT_DELAYED_WORK(&wm8753->charge_work, wm8753_charge_work);
ret = wm8753_reset(component);
if (ret < 0) {
dev_err(component->dev, "Failed to issue reset: %d\n", ret);
return ret;
}
wm8753->dai_func = 0;
/* set the update bits */
snd_soc_component_update_bits(component, WM8753_LDAC, 0x0100, 0x0100);
snd_soc_component_update_bits(component, WM8753_RDAC, 0x0100, 0x0100);
snd_soc_component_update_bits(component, WM8753_LADC, 0x0100, 0x0100);
snd_soc_component_update_bits(component, WM8753_RADC, 0x0100, 0x0100);
snd_soc_component_update_bits(component, WM8753_LOUT1V, 0x0100, 0x0100);
snd_soc_component_update_bits(component, WM8753_ROUT1V, 0x0100, 0x0100);
snd_soc_component_update_bits(component, WM8753_LOUT2V, 0x0100, 0x0100);
snd_soc_component_update_bits(component, WM8753_ROUT2V, 0x0100, 0x0100);
snd_soc_component_update_bits(component, WM8753_LINVOL, 0x0100, 0x0100);
snd_soc_component_update_bits(component, WM8753_RINVOL, 0x0100, 0x0100);
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_wm8753 = {
.probe = wm8753_probe,
.resume = wm8753_resume,
.set_bias_level = wm8753_set_bias_level,
.controls = wm8753_snd_controls,
.num_controls = ARRAY_SIZE(wm8753_snd_controls),
.dapm_widgets = wm8753_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8753_dapm_widgets),
.dapm_routes = wm8753_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(wm8753_dapm_routes),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct of_device_id wm8753_of_match[] = {
{ .compatible = "wlf,wm8753", },
{ }
};
MODULE_DEVICE_TABLE(of, wm8753_of_match);
static const struct regmap_config wm8753_regmap = {
.reg_bits = 7,
.val_bits = 9,
.max_register = WM8753_ADCTL2,
.volatile_reg = wm8753_volatile,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = wm8753_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8753_reg_defaults),
};
#if defined(CONFIG_SPI_MASTER)
static int wm8753_spi_probe(struct spi_device *spi)
{
struct wm8753_priv *wm8753;
int ret;
wm8753 = devm_kzalloc(&spi->dev, sizeof(struct wm8753_priv),
GFP_KERNEL);
if (wm8753 == NULL)
return -ENOMEM;
spi_set_drvdata(spi, wm8753);
wm8753->regmap = devm_regmap_init_spi(spi, &wm8753_regmap);
if (IS_ERR(wm8753->regmap)) {
ret = PTR_ERR(wm8753->regmap);
dev_err(&spi->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
ret = devm_snd_soc_register_component(&spi->dev, &soc_component_dev_wm8753,
wm8753_dai, ARRAY_SIZE(wm8753_dai));
if (ret != 0)
dev_err(&spi->dev, "Failed to register CODEC: %d\n", ret);
return ret;
}
static struct spi_driver wm8753_spi_driver = {
.driver = {
.name = "wm8753",
.of_match_table = wm8753_of_match,
},
.probe = wm8753_spi_probe,
};
#endif /* CONFIG_SPI_MASTER */
#if IS_ENABLED(CONFIG_I2C)
static int wm8753_i2c_probe(struct i2c_client *i2c)
{
struct wm8753_priv *wm8753;
int ret;
wm8753 = devm_kzalloc(&i2c->dev, sizeof(struct wm8753_priv),
GFP_KERNEL);
if (wm8753 == NULL)
return -ENOMEM;
i2c_set_clientdata(i2c, wm8753);
wm8753->regmap = devm_regmap_init_i2c(i2c, &wm8753_regmap);
if (IS_ERR(wm8753->regmap)) {
ret = PTR_ERR(wm8753->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
ret = devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_wm8753,
wm8753_dai, ARRAY_SIZE(wm8753_dai));
if (ret != 0)
dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
return ret;
}
static const struct i2c_device_id wm8753_i2c_id[] = {
{ "wm8753", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8753_i2c_id);
static struct i2c_driver wm8753_i2c_driver = {
.driver = {
.name = "wm8753",
.of_match_table = wm8753_of_match,
},
.probe = wm8753_i2c_probe,
.id_table = wm8753_i2c_id,
};
#endif
static int __init wm8753_modinit(void)
{
int ret = 0;
#if IS_ENABLED(CONFIG_I2C)
ret = i2c_add_driver(&wm8753_i2c_driver);
if (ret != 0) {
printk(KERN_ERR "Failed to register wm8753 I2C driver: %d\n",
ret);
}
#endif
#if defined(CONFIG_SPI_MASTER)
ret = spi_register_driver(&wm8753_spi_driver);
if (ret != 0) {
printk(KERN_ERR "Failed to register wm8753 SPI driver: %d\n",
ret);
}
#endif
return ret;
}
module_init(wm8753_modinit);
static void __exit wm8753_exit(void)
{
#if IS_ENABLED(CONFIG_I2C)
i2c_del_driver(&wm8753_i2c_driver);
#endif
#if defined(CONFIG_SPI_MASTER)
spi_unregister_driver(&wm8753_spi_driver);
#endif
}
module_exit(wm8753_exit);
MODULE_DESCRIPTION("ASoC WM8753 driver");
MODULE_AUTHOR("Liam Girdwood");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8753.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* max98095.c -- MAX98095 ALSA SoC Audio driver
*
* Copyright 2011 Maxim Integrated Products
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/clk.h>
#include <linux/mutex.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <linux/slab.h>
#include <asm/div64.h>
#include <sound/max98095.h>
#include <sound/jack.h>
#include "max98095.h"
enum max98095_type {
MAX98095,
};
struct max98095_cdata {
unsigned int rate;
unsigned int fmt;
int eq_sel;
int bq_sel;
};
struct max98095_priv {
struct regmap *regmap;
enum max98095_type devtype;
struct max98095_pdata *pdata;
struct clk *mclk;
unsigned int sysclk;
struct max98095_cdata dai[3];
const char **eq_texts;
const char **bq_texts;
struct soc_enum eq_enum;
struct soc_enum bq_enum;
int eq_textcnt;
int bq_textcnt;
u8 lin_state;
unsigned int mic1pre;
unsigned int mic2pre;
struct snd_soc_jack *headphone_jack;
struct snd_soc_jack *mic_jack;
struct mutex lock;
};
static const struct reg_default max98095_reg_def[] = {
{ 0xf, 0x00 }, /* 0F */
{ 0x10, 0x00 }, /* 10 */
{ 0x11, 0x00 }, /* 11 */
{ 0x12, 0x00 }, /* 12 */
{ 0x13, 0x00 }, /* 13 */
{ 0x14, 0x00 }, /* 14 */
{ 0x15, 0x00 }, /* 15 */
{ 0x16, 0x00 }, /* 16 */
{ 0x17, 0x00 }, /* 17 */
{ 0x18, 0x00 }, /* 18 */
{ 0x19, 0x00 }, /* 19 */
{ 0x1a, 0x00 }, /* 1A */
{ 0x1b, 0x00 }, /* 1B */
{ 0x1c, 0x00 }, /* 1C */
{ 0x1d, 0x00 }, /* 1D */
{ 0x1e, 0x00 }, /* 1E */
{ 0x1f, 0x00 }, /* 1F */
{ 0x20, 0x00 }, /* 20 */
{ 0x21, 0x00 }, /* 21 */
{ 0x22, 0x00 }, /* 22 */
{ 0x23, 0x00 }, /* 23 */
{ 0x24, 0x00 }, /* 24 */
{ 0x25, 0x00 }, /* 25 */
{ 0x26, 0x00 }, /* 26 */
{ 0x27, 0x00 }, /* 27 */
{ 0x28, 0x00 }, /* 28 */
{ 0x29, 0x00 }, /* 29 */
{ 0x2a, 0x00 }, /* 2A */
{ 0x2b, 0x00 }, /* 2B */
{ 0x2c, 0x00 }, /* 2C */
{ 0x2d, 0x00 }, /* 2D */
{ 0x2e, 0x00 }, /* 2E */
{ 0x2f, 0x00 }, /* 2F */
{ 0x30, 0x00 }, /* 30 */
{ 0x31, 0x00 }, /* 31 */
{ 0x32, 0x00 }, /* 32 */
{ 0x33, 0x00 }, /* 33 */
{ 0x34, 0x00 }, /* 34 */
{ 0x35, 0x00 }, /* 35 */
{ 0x36, 0x00 }, /* 36 */
{ 0x37, 0x00 }, /* 37 */
{ 0x38, 0x00 }, /* 38 */
{ 0x39, 0x00 }, /* 39 */
{ 0x3a, 0x00 }, /* 3A */
{ 0x3b, 0x00 }, /* 3B */
{ 0x3c, 0x00 }, /* 3C */
{ 0x3d, 0x00 }, /* 3D */
{ 0x3e, 0x00 }, /* 3E */
{ 0x3f, 0x00 }, /* 3F */
{ 0x40, 0x00 }, /* 40 */
{ 0x41, 0x00 }, /* 41 */
{ 0x42, 0x00 }, /* 42 */
{ 0x43, 0x00 }, /* 43 */
{ 0x44, 0x00 }, /* 44 */
{ 0x45, 0x00 }, /* 45 */
{ 0x46, 0x00 }, /* 46 */
{ 0x47, 0x00 }, /* 47 */
{ 0x48, 0x00 }, /* 48 */
{ 0x49, 0x00 }, /* 49 */
{ 0x4a, 0x00 }, /* 4A */
{ 0x4b, 0x00 }, /* 4B */
{ 0x4c, 0x00 }, /* 4C */
{ 0x4d, 0x00 }, /* 4D */
{ 0x4e, 0x00 }, /* 4E */
{ 0x4f, 0x00 }, /* 4F */
{ 0x50, 0x00 }, /* 50 */
{ 0x51, 0x00 }, /* 51 */
{ 0x52, 0x00 }, /* 52 */
{ 0x53, 0x00 }, /* 53 */
{ 0x54, 0x00 }, /* 54 */
{ 0x55, 0x00 }, /* 55 */
{ 0x56, 0x00 }, /* 56 */
{ 0x57, 0x00 }, /* 57 */
{ 0x58, 0x00 }, /* 58 */
{ 0x59, 0x00 }, /* 59 */
{ 0x5a, 0x00 }, /* 5A */
{ 0x5b, 0x00 }, /* 5B */
{ 0x5c, 0x00 }, /* 5C */
{ 0x5d, 0x00 }, /* 5D */
{ 0x5e, 0x00 }, /* 5E */
{ 0x5f, 0x00 }, /* 5F */
{ 0x60, 0x00 }, /* 60 */
{ 0x61, 0x00 }, /* 61 */
{ 0x62, 0x00 }, /* 62 */
{ 0x63, 0x00 }, /* 63 */
{ 0x64, 0x00 }, /* 64 */
{ 0x65, 0x00 }, /* 65 */
{ 0x66, 0x00 }, /* 66 */
{ 0x67, 0x00 }, /* 67 */
{ 0x68, 0x00 }, /* 68 */
{ 0x69, 0x00 }, /* 69 */
{ 0x6a, 0x00 }, /* 6A */
{ 0x6b, 0x00 }, /* 6B */
{ 0x6c, 0x00 }, /* 6C */
{ 0x6d, 0x00 }, /* 6D */
{ 0x6e, 0x00 }, /* 6E */
{ 0x6f, 0x00 }, /* 6F */
{ 0x70, 0x00 }, /* 70 */
{ 0x71, 0x00 }, /* 71 */
{ 0x72, 0x00 }, /* 72 */
{ 0x73, 0x00 }, /* 73 */
{ 0x74, 0x00 }, /* 74 */
{ 0x75, 0x00 }, /* 75 */
{ 0x76, 0x00 }, /* 76 */
{ 0x77, 0x00 }, /* 77 */
{ 0x78, 0x00 }, /* 78 */
{ 0x79, 0x00 }, /* 79 */
{ 0x7a, 0x00 }, /* 7A */
{ 0x7b, 0x00 }, /* 7B */
{ 0x7c, 0x00 }, /* 7C */
{ 0x7d, 0x00 }, /* 7D */
{ 0x7e, 0x00 }, /* 7E */
{ 0x7f, 0x00 }, /* 7F */
{ 0x80, 0x00 }, /* 80 */
{ 0x81, 0x00 }, /* 81 */
{ 0x82, 0x00 }, /* 82 */
{ 0x83, 0x00 }, /* 83 */
{ 0x84, 0x00 }, /* 84 */
{ 0x85, 0x00 }, /* 85 */
{ 0x86, 0x00 }, /* 86 */
{ 0x87, 0x00 }, /* 87 */
{ 0x88, 0x00 }, /* 88 */
{ 0x89, 0x00 }, /* 89 */
{ 0x8a, 0x00 }, /* 8A */
{ 0x8b, 0x00 }, /* 8B */
{ 0x8c, 0x00 }, /* 8C */
{ 0x8d, 0x00 }, /* 8D */
{ 0x8e, 0x00 }, /* 8E */
{ 0x8f, 0x00 }, /* 8F */
{ 0x90, 0x00 }, /* 90 */
{ 0x91, 0x00 }, /* 91 */
{ 0x92, 0x30 }, /* 92 */
{ 0x93, 0xF0 }, /* 93 */
{ 0x94, 0x00 }, /* 94 */
{ 0x95, 0x00 }, /* 95 */
{ 0x96, 0x3F }, /* 96 */
{ 0x97, 0x00 }, /* 97 */
{ 0xff, 0x00 }, /* FF */
};
static bool max98095_readable(struct device *dev, unsigned int reg)
{
switch (reg) {
case M98095_001_HOST_INT_STS ... M98095_097_PWR_SYS:
case M98095_0FF_REV_ID:
return true;
default:
return false;
}
}
static bool max98095_writeable(struct device *dev, unsigned int reg)
{
switch (reg) {
case M98095_00F_HOST_CFG ... M98095_097_PWR_SYS:
return true;
default:
return false;
}
}
static bool max98095_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case M98095_000_HOST_DATA ... M98095_00E_TEMP_SENSOR_STS:
case M98095_REG_MAX_CACHED + 1 ... M98095_0FF_REV_ID:
return true;
default:
return false;
}
}
static const struct regmap_config max98095_regmap = {
.reg_bits = 8,
.val_bits = 8,
.reg_defaults = max98095_reg_def,
.num_reg_defaults = ARRAY_SIZE(max98095_reg_def),
.max_register = M98095_0FF_REV_ID,
.cache_type = REGCACHE_RBTREE,
.readable_reg = max98095_readable,
.writeable_reg = max98095_writeable,
.volatile_reg = max98095_volatile,
};
/*
* Load equalizer DSP coefficient configurations registers
*/
static void m98095_eq_band(struct snd_soc_component *component, unsigned int dai,
unsigned int band, u16 *coefs)
{
unsigned int eq_reg;
unsigned int i;
if (WARN_ON(band > 4) ||
WARN_ON(dai > 1))
return;
/* Load the base register address */
eq_reg = dai ? M98095_142_DAI2_EQ_BASE : M98095_110_DAI1_EQ_BASE;
/* Add the band address offset, note adjustment for word address */
eq_reg += band * (M98095_COEFS_PER_BAND << 1);
/* Step through the registers and coefs */
for (i = 0; i < M98095_COEFS_PER_BAND; i++) {
snd_soc_component_write(component, eq_reg++, M98095_BYTE1(coefs[i]));
snd_soc_component_write(component, eq_reg++, M98095_BYTE0(coefs[i]));
}
}
/*
* Load biquad filter coefficient configurations registers
*/
static void m98095_biquad_band(struct snd_soc_component *component, unsigned int dai,
unsigned int band, u16 *coefs)
{
unsigned int bq_reg;
unsigned int i;
if (WARN_ON(band > 1) ||
WARN_ON(dai > 1))
return;
/* Load the base register address */
bq_reg = dai ? M98095_17E_DAI2_BQ_BASE : M98095_174_DAI1_BQ_BASE;
/* Add the band address offset, note adjustment for word address */
bq_reg += band * (M98095_COEFS_PER_BAND << 1);
/* Step through the registers and coefs */
for (i = 0; i < M98095_COEFS_PER_BAND; i++) {
snd_soc_component_write(component, bq_reg++, M98095_BYTE1(coefs[i]));
snd_soc_component_write(component, bq_reg++, M98095_BYTE0(coefs[i]));
}
}
static const char * const max98095_fltr_mode[] = { "Voice", "Music" };
static SOC_ENUM_SINGLE_DECL(max98095_dai1_filter_mode_enum,
M98095_02E_DAI1_FILTERS, 7,
max98095_fltr_mode);
static SOC_ENUM_SINGLE_DECL(max98095_dai2_filter_mode_enum,
M98095_038_DAI2_FILTERS, 7,
max98095_fltr_mode);
static const char * const max98095_extmic_text[] = { "None", "MIC1", "MIC2" };
static SOC_ENUM_SINGLE_DECL(max98095_extmic_enum,
M98095_087_CFG_MIC, 0,
max98095_extmic_text);
static const struct snd_kcontrol_new max98095_extmic_mux =
SOC_DAPM_ENUM("External MIC Mux", max98095_extmic_enum);
static const char * const max98095_linein_text[] = { "INA", "INB" };
static SOC_ENUM_SINGLE_DECL(max98095_linein_enum,
M98095_086_CFG_LINE, 6,
max98095_linein_text);
static const struct snd_kcontrol_new max98095_linein_mux =
SOC_DAPM_ENUM("Linein Input Mux", max98095_linein_enum);
static const char * const max98095_line_mode_text[] = {
"Stereo", "Differential"};
static SOC_ENUM_SINGLE_DECL(max98095_linein_mode_enum,
M98095_086_CFG_LINE, 7,
max98095_line_mode_text);
static SOC_ENUM_SINGLE_DECL(max98095_lineout_mode_enum,
M98095_086_CFG_LINE, 4,
max98095_line_mode_text);
static const char * const max98095_dai_fltr[] = {
"Off", "Elliptical-HPF-16k", "Butterworth-HPF-16k",
"Elliptical-HPF-8k", "Butterworth-HPF-8k", "Butterworth-HPF-Fs/240"};
static SOC_ENUM_SINGLE_DECL(max98095_dai1_dac_filter_enum,
M98095_02E_DAI1_FILTERS, 0,
max98095_dai_fltr);
static SOC_ENUM_SINGLE_DECL(max98095_dai2_dac_filter_enum,
M98095_038_DAI2_FILTERS, 0,
max98095_dai_fltr);
static SOC_ENUM_SINGLE_DECL(max98095_dai3_dac_filter_enum,
M98095_042_DAI3_FILTERS, 0,
max98095_dai_fltr);
static int max98095_mic1pre_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
unsigned int sel = ucontrol->value.integer.value[0];
max98095->mic1pre = sel;
snd_soc_component_update_bits(component, M98095_05F_LVL_MIC1, M98095_MICPRE_MASK,
(1+sel)<<M98095_MICPRE_SHIFT);
return 0;
}
static int max98095_mic1pre_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = max98095->mic1pre;
return 0;
}
static int max98095_mic2pre_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
unsigned int sel = ucontrol->value.integer.value[0];
max98095->mic2pre = sel;
snd_soc_component_update_bits(component, M98095_060_LVL_MIC2, M98095_MICPRE_MASK,
(1+sel)<<M98095_MICPRE_SHIFT);
return 0;
}
static int max98095_mic2pre_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = max98095->mic2pre;
return 0;
}
static const DECLARE_TLV_DB_RANGE(max98095_micboost_tlv,
0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0)
);
static const DECLARE_TLV_DB_SCALE(max98095_mic_tlv, 0, 100, 0);
static const DECLARE_TLV_DB_SCALE(max98095_adc_tlv, -1200, 100, 0);
static const DECLARE_TLV_DB_SCALE(max98095_adcboost_tlv, 0, 600, 0);
static const DECLARE_TLV_DB_RANGE(max98095_hp_tlv,
0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
28, 31, TLV_DB_SCALE_ITEM(150, 50, 0)
);
static const DECLARE_TLV_DB_RANGE(max98095_spk_tlv,
0, 10, TLV_DB_SCALE_ITEM(-5900, 400, 0),
11, 18, TLV_DB_SCALE_ITEM(-1700, 200, 0),
19, 27, TLV_DB_SCALE_ITEM(-200, 100, 0),
28, 39, TLV_DB_SCALE_ITEM(650, 50, 0)
);
static const DECLARE_TLV_DB_RANGE(max98095_rcv_lout_tlv,
0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
28, 31, TLV_DB_SCALE_ITEM(650, 50, 0)
);
static const DECLARE_TLV_DB_RANGE(max98095_lin_tlv,
0, 2, TLV_DB_SCALE_ITEM(-600, 300, 0),
3, 3, TLV_DB_SCALE_ITEM(300, 1100, 0),
4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0)
);
static const struct snd_kcontrol_new max98095_snd_controls[] = {
SOC_DOUBLE_R_TLV("Headphone Volume", M98095_064_LVL_HP_L,
M98095_065_LVL_HP_R, 0, 31, 0, max98095_hp_tlv),
SOC_DOUBLE_R_TLV("Speaker Volume", M98095_067_LVL_SPK_L,
M98095_068_LVL_SPK_R, 0, 39, 0, max98095_spk_tlv),
SOC_SINGLE_TLV("Receiver Volume", M98095_066_LVL_RCV,
0, 31, 0, max98095_rcv_lout_tlv),
SOC_DOUBLE_R_TLV("Lineout Volume", M98095_062_LVL_LINEOUT1,
M98095_063_LVL_LINEOUT2, 0, 31, 0, max98095_rcv_lout_tlv),
SOC_DOUBLE_R("Headphone Switch", M98095_064_LVL_HP_L,
M98095_065_LVL_HP_R, 7, 1, 1),
SOC_DOUBLE_R("Speaker Switch", M98095_067_LVL_SPK_L,
M98095_068_LVL_SPK_R, 7, 1, 1),
SOC_SINGLE("Receiver Switch", M98095_066_LVL_RCV, 7, 1, 1),
SOC_DOUBLE_R("Lineout Switch", M98095_062_LVL_LINEOUT1,
M98095_063_LVL_LINEOUT2, 7, 1, 1),
SOC_SINGLE_TLV("MIC1 Volume", M98095_05F_LVL_MIC1, 0, 20, 1,
max98095_mic_tlv),
SOC_SINGLE_TLV("MIC2 Volume", M98095_060_LVL_MIC2, 0, 20, 1,
max98095_mic_tlv),
SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
M98095_05F_LVL_MIC1, 5, 2, 0,
max98095_mic1pre_get, max98095_mic1pre_set,
max98095_micboost_tlv),
SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
M98095_060_LVL_MIC2, 5, 2, 0,
max98095_mic2pre_get, max98095_mic2pre_set,
max98095_micboost_tlv),
SOC_SINGLE_TLV("Linein Volume", M98095_061_LVL_LINEIN, 0, 5, 1,
max98095_lin_tlv),
SOC_SINGLE_TLV("ADCL Volume", M98095_05D_LVL_ADC_L, 0, 15, 1,
max98095_adc_tlv),
SOC_SINGLE_TLV("ADCR Volume", M98095_05E_LVL_ADC_R, 0, 15, 1,
max98095_adc_tlv),
SOC_SINGLE_TLV("ADCL Boost Volume", M98095_05D_LVL_ADC_L, 4, 3, 0,
max98095_adcboost_tlv),
SOC_SINGLE_TLV("ADCR Boost Volume", M98095_05E_LVL_ADC_R, 4, 3, 0,
max98095_adcboost_tlv),
SOC_SINGLE("EQ1 Switch", M98095_088_CFG_LEVEL, 0, 1, 0),
SOC_SINGLE("EQ2 Switch", M98095_088_CFG_LEVEL, 1, 1, 0),
SOC_SINGLE("Biquad1 Switch", M98095_088_CFG_LEVEL, 2, 1, 0),
SOC_SINGLE("Biquad2 Switch", M98095_088_CFG_LEVEL, 3, 1, 0),
SOC_ENUM("DAI1 Filter Mode", max98095_dai1_filter_mode_enum),
SOC_ENUM("DAI2 Filter Mode", max98095_dai2_filter_mode_enum),
SOC_ENUM("DAI1 DAC Filter", max98095_dai1_dac_filter_enum),
SOC_ENUM("DAI2 DAC Filter", max98095_dai2_dac_filter_enum),
SOC_ENUM("DAI3 DAC Filter", max98095_dai3_dac_filter_enum),
SOC_ENUM("Linein Mode", max98095_linein_mode_enum),
SOC_ENUM("Lineout Mode", max98095_lineout_mode_enum),
};
/* Left speaker mixer switch */
static const struct snd_kcontrol_new max98095_left_speaker_mixer_controls[] = {
SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_050_MIX_SPK_LEFT, 0, 1, 0),
SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_050_MIX_SPK_LEFT, 6, 1, 0),
SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0),
SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0),
SOC_DAPM_SINGLE("MIC1 Switch", M98095_050_MIX_SPK_LEFT, 4, 1, 0),
SOC_DAPM_SINGLE("MIC2 Switch", M98095_050_MIX_SPK_LEFT, 5, 1, 0),
SOC_DAPM_SINGLE("IN1 Switch", M98095_050_MIX_SPK_LEFT, 1, 1, 0),
SOC_DAPM_SINGLE("IN2 Switch", M98095_050_MIX_SPK_LEFT, 2, 1, 0),
};
/* Right speaker mixer switch */
static const struct snd_kcontrol_new max98095_right_speaker_mixer_controls[] = {
SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 6, 1, 0),
SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 0, 1, 0),
SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0),
SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0),
SOC_DAPM_SINGLE("MIC1 Switch", M98095_051_MIX_SPK_RIGHT, 5, 1, 0),
SOC_DAPM_SINGLE("MIC2 Switch", M98095_051_MIX_SPK_RIGHT, 4, 1, 0),
SOC_DAPM_SINGLE("IN1 Switch", M98095_051_MIX_SPK_RIGHT, 1, 1, 0),
SOC_DAPM_SINGLE("IN2 Switch", M98095_051_MIX_SPK_RIGHT, 2, 1, 0),
};
/* Left headphone mixer switch */
static const struct snd_kcontrol_new max98095_left_hp_mixer_controls[] = {
SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04C_MIX_HP_LEFT, 0, 1, 0),
SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04C_MIX_HP_LEFT, 5, 1, 0),
SOC_DAPM_SINGLE("MIC1 Switch", M98095_04C_MIX_HP_LEFT, 3, 1, 0),
SOC_DAPM_SINGLE("MIC2 Switch", M98095_04C_MIX_HP_LEFT, 4, 1, 0),
SOC_DAPM_SINGLE("IN1 Switch", M98095_04C_MIX_HP_LEFT, 1, 1, 0),
SOC_DAPM_SINGLE("IN2 Switch", M98095_04C_MIX_HP_LEFT, 2, 1, 0),
};
/* Right headphone mixer switch */
static const struct snd_kcontrol_new max98095_right_hp_mixer_controls[] = {
SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 5, 1, 0),
SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 0, 1, 0),
SOC_DAPM_SINGLE("MIC1 Switch", M98095_04D_MIX_HP_RIGHT, 3, 1, 0),
SOC_DAPM_SINGLE("MIC2 Switch", M98095_04D_MIX_HP_RIGHT, 4, 1, 0),
SOC_DAPM_SINGLE("IN1 Switch", M98095_04D_MIX_HP_RIGHT, 1, 1, 0),
SOC_DAPM_SINGLE("IN2 Switch", M98095_04D_MIX_HP_RIGHT, 2, 1, 0),
};
/* Receiver earpiece mixer switch */
static const struct snd_kcontrol_new max98095_mono_rcv_mixer_controls[] = {
SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04F_MIX_RCV, 0, 1, 0),
SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04F_MIX_RCV, 5, 1, 0),
SOC_DAPM_SINGLE("MIC1 Switch", M98095_04F_MIX_RCV, 3, 1, 0),
SOC_DAPM_SINGLE("MIC2 Switch", M98095_04F_MIX_RCV, 4, 1, 0),
SOC_DAPM_SINGLE("IN1 Switch", M98095_04F_MIX_RCV, 1, 1, 0),
SOC_DAPM_SINGLE("IN2 Switch", M98095_04F_MIX_RCV, 2, 1, 0),
};
/* Left lineout mixer switch */
static const struct snd_kcontrol_new max98095_left_lineout_mixer_controls[] = {
SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_053_MIX_LINEOUT1, 5, 1, 0),
SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_053_MIX_LINEOUT1, 0, 1, 0),
SOC_DAPM_SINGLE("MIC1 Switch", M98095_053_MIX_LINEOUT1, 3, 1, 0),
SOC_DAPM_SINGLE("MIC2 Switch", M98095_053_MIX_LINEOUT1, 4, 1, 0),
SOC_DAPM_SINGLE("IN1 Switch", M98095_053_MIX_LINEOUT1, 1, 1, 0),
SOC_DAPM_SINGLE("IN2 Switch", M98095_053_MIX_LINEOUT1, 2, 1, 0),
};
/* Right lineout mixer switch */
static const struct snd_kcontrol_new max98095_right_lineout_mixer_controls[] = {
SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_054_MIX_LINEOUT2, 0, 1, 0),
SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_054_MIX_LINEOUT2, 5, 1, 0),
SOC_DAPM_SINGLE("MIC1 Switch", M98095_054_MIX_LINEOUT2, 3, 1, 0),
SOC_DAPM_SINGLE("MIC2 Switch", M98095_054_MIX_LINEOUT2, 4, 1, 0),
SOC_DAPM_SINGLE("IN1 Switch", M98095_054_MIX_LINEOUT2, 1, 1, 0),
SOC_DAPM_SINGLE("IN2 Switch", M98095_054_MIX_LINEOUT2, 2, 1, 0),
};
/* Left ADC mixer switch */
static const struct snd_kcontrol_new max98095_left_ADC_mixer_controls[] = {
SOC_DAPM_SINGLE("MIC1 Switch", M98095_04A_MIX_ADC_LEFT, 7, 1, 0),
SOC_DAPM_SINGLE("MIC2 Switch", M98095_04A_MIX_ADC_LEFT, 6, 1, 0),
SOC_DAPM_SINGLE("IN1 Switch", M98095_04A_MIX_ADC_LEFT, 3, 1, 0),
SOC_DAPM_SINGLE("IN2 Switch", M98095_04A_MIX_ADC_LEFT, 2, 1, 0),
};
/* Right ADC mixer switch */
static const struct snd_kcontrol_new max98095_right_ADC_mixer_controls[] = {
SOC_DAPM_SINGLE("MIC1 Switch", M98095_04B_MIX_ADC_RIGHT, 7, 1, 0),
SOC_DAPM_SINGLE("MIC2 Switch", M98095_04B_MIX_ADC_RIGHT, 6, 1, 0),
SOC_DAPM_SINGLE("IN1 Switch", M98095_04B_MIX_ADC_RIGHT, 3, 1, 0),
SOC_DAPM_SINGLE("IN2 Switch", M98095_04B_MIX_ADC_RIGHT, 2, 1, 0),
};
static int max98095_mic_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
if (w->reg == M98095_05F_LVL_MIC1) {
snd_soc_component_update_bits(component, w->reg, M98095_MICPRE_MASK,
(1+max98095->mic1pre)<<M98095_MICPRE_SHIFT);
} else {
snd_soc_component_update_bits(component, w->reg, M98095_MICPRE_MASK,
(1+max98095->mic2pre)<<M98095_MICPRE_SHIFT);
}
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component, w->reg, M98095_MICPRE_MASK, 0);
break;
default:
return -EINVAL;
}
return 0;
}
/*
* The line inputs are stereo inputs with the left and right
* channels sharing a common PGA power control signal.
*/
static int max98095_line_pga(struct snd_soc_dapm_widget *w,
int event, u8 channel)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
u8 *state;
if (WARN_ON(!(channel == 1 || channel == 2)))
return -EINVAL;
state = &max98095->lin_state;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
*state |= channel;
snd_soc_component_update_bits(component, w->reg,
(1 << w->shift), (1 << w->shift));
break;
case SND_SOC_DAPM_POST_PMD:
*state &= ~channel;
if (*state == 0) {
snd_soc_component_update_bits(component, w->reg,
(1 << w->shift), 0);
}
break;
default:
return -EINVAL;
}
return 0;
}
static int max98095_pga_in1_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *k, int event)
{
return max98095_line_pga(w, event, 1);
}
static int max98095_pga_in2_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *k, int event)
{
return max98095_line_pga(w, event, 2);
}
/*
* The stereo line out mixer outputs to two stereo line outs.
* The 2nd pair has a separate set of enables.
*/
static int max98095_lineout_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(component, w->reg,
(1 << (w->shift+2)), (1 << (w->shift+2)));
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component, w->reg,
(1 << (w->shift+2)), 0);
break;
default:
return -EINVAL;
}
return 0;
}
static const struct snd_soc_dapm_widget max98095_dapm_widgets[] = {
SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98095_090_PWR_EN_IN, 0, 0),
SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98095_090_PWR_EN_IN, 1, 0),
SND_SOC_DAPM_DAC("DACL1", "HiFi Playback",
M98095_091_PWR_EN_OUT, 0, 0),
SND_SOC_DAPM_DAC("DACR1", "HiFi Playback",
M98095_091_PWR_EN_OUT, 1, 0),
SND_SOC_DAPM_DAC("DACM2", "Aux Playback",
M98095_091_PWR_EN_OUT, 2, 0),
SND_SOC_DAPM_DAC("DACM3", "Voice Playback",
M98095_091_PWR_EN_OUT, 2, 0),
SND_SOC_DAPM_PGA("HP Left Out", M98095_091_PWR_EN_OUT,
6, 0, NULL, 0),
SND_SOC_DAPM_PGA("HP Right Out", M98095_091_PWR_EN_OUT,
7, 0, NULL, 0),
SND_SOC_DAPM_PGA("SPK Left Out", M98095_091_PWR_EN_OUT,
4, 0, NULL, 0),
SND_SOC_DAPM_PGA("SPK Right Out", M98095_091_PWR_EN_OUT,
5, 0, NULL, 0),
SND_SOC_DAPM_PGA("RCV Mono Out", M98095_091_PWR_EN_OUT,
3, 0, NULL, 0),
SND_SOC_DAPM_PGA_E("LINE Left Out", M98095_092_PWR_EN_OUT,
0, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA_E("LINE Right Out", M98095_092_PWR_EN_OUT,
1, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0,
&max98095_extmic_mux),
SND_SOC_DAPM_MUX("Linein Mux", SND_SOC_NOPM, 0, 0,
&max98095_linein_mux),
SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
&max98095_left_hp_mixer_controls[0],
ARRAY_SIZE(max98095_left_hp_mixer_controls)),
SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
&max98095_right_hp_mixer_controls[0],
ARRAY_SIZE(max98095_right_hp_mixer_controls)),
SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0,
&max98095_left_speaker_mixer_controls[0],
ARRAY_SIZE(max98095_left_speaker_mixer_controls)),
SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0,
&max98095_right_speaker_mixer_controls[0],
ARRAY_SIZE(max98095_right_speaker_mixer_controls)),
SND_SOC_DAPM_MIXER("Receiver Mixer", SND_SOC_NOPM, 0, 0,
&max98095_mono_rcv_mixer_controls[0],
ARRAY_SIZE(max98095_mono_rcv_mixer_controls)),
SND_SOC_DAPM_MIXER("Left Lineout Mixer", SND_SOC_NOPM, 0, 0,
&max98095_left_lineout_mixer_controls[0],
ARRAY_SIZE(max98095_left_lineout_mixer_controls)),
SND_SOC_DAPM_MIXER("Right Lineout Mixer", SND_SOC_NOPM, 0, 0,
&max98095_right_lineout_mixer_controls[0],
ARRAY_SIZE(max98095_right_lineout_mixer_controls)),
SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
&max98095_left_ADC_mixer_controls[0],
ARRAY_SIZE(max98095_left_ADC_mixer_controls)),
SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
&max98095_right_ADC_mixer_controls[0],
ARRAY_SIZE(max98095_right_ADC_mixer_controls)),
SND_SOC_DAPM_PGA_E("MIC1 Input", M98095_05F_LVL_MIC1,
5, 0, NULL, 0, max98095_mic_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("MIC2 Input", M98095_060_LVL_MIC2,
5, 0, NULL, 0, max98095_mic_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("IN1 Input", M98095_090_PWR_EN_IN,
7, 0, NULL, 0, max98095_pga_in1_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("IN2 Input", M98095_090_PWR_EN_IN,
7, 0, NULL, 0, max98095_pga_in2_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MICBIAS("MICBIAS1", M98095_090_PWR_EN_IN, 2, 0),
SND_SOC_DAPM_MICBIAS("MICBIAS2", M98095_090_PWR_EN_IN, 3, 0),
SND_SOC_DAPM_OUTPUT("HPL"),
SND_SOC_DAPM_OUTPUT("HPR"),
SND_SOC_DAPM_OUTPUT("SPKL"),
SND_SOC_DAPM_OUTPUT("SPKR"),
SND_SOC_DAPM_OUTPUT("RCV"),
SND_SOC_DAPM_OUTPUT("OUT1"),
SND_SOC_DAPM_OUTPUT("OUT2"),
SND_SOC_DAPM_OUTPUT("OUT3"),
SND_SOC_DAPM_OUTPUT("OUT4"),
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_INPUT("MIC2"),
SND_SOC_DAPM_INPUT("INA1"),
SND_SOC_DAPM_INPUT("INA2"),
SND_SOC_DAPM_INPUT("INB1"),
SND_SOC_DAPM_INPUT("INB2"),
};
static const struct snd_soc_dapm_route max98095_audio_map[] = {
/* Left headphone output mixer */
{"Left Headphone Mixer", "Left DAC1 Switch", "DACL1"},
{"Left Headphone Mixer", "Right DAC1 Switch", "DACR1"},
{"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
{"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
{"Left Headphone Mixer", "IN1 Switch", "IN1 Input"},
{"Left Headphone Mixer", "IN2 Switch", "IN2 Input"},
/* Right headphone output mixer */
{"Right Headphone Mixer", "Left DAC1 Switch", "DACL1"},
{"Right Headphone Mixer", "Right DAC1 Switch", "DACR1"},
{"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
{"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
{"Right Headphone Mixer", "IN1 Switch", "IN1 Input"},
{"Right Headphone Mixer", "IN2 Switch", "IN2 Input"},
/* Left speaker output mixer */
{"Left Speaker Mixer", "Left DAC1 Switch", "DACL1"},
{"Left Speaker Mixer", "Right DAC1 Switch", "DACR1"},
{"Left Speaker Mixer", "Mono DAC2 Switch", "DACM2"},
{"Left Speaker Mixer", "Mono DAC3 Switch", "DACM3"},
{"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
{"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
{"Left Speaker Mixer", "IN1 Switch", "IN1 Input"},
{"Left Speaker Mixer", "IN2 Switch", "IN2 Input"},
/* Right speaker output mixer */
{"Right Speaker Mixer", "Left DAC1 Switch", "DACL1"},
{"Right Speaker Mixer", "Right DAC1 Switch", "DACR1"},
{"Right Speaker Mixer", "Mono DAC2 Switch", "DACM2"},
{"Right Speaker Mixer", "Mono DAC3 Switch", "DACM3"},
{"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
{"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
{"Right Speaker Mixer", "IN1 Switch", "IN1 Input"},
{"Right Speaker Mixer", "IN2 Switch", "IN2 Input"},
/* Earpiece/Receiver output mixer */
{"Receiver Mixer", "Left DAC1 Switch", "DACL1"},
{"Receiver Mixer", "Right DAC1 Switch", "DACR1"},
{"Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
{"Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
{"Receiver Mixer", "IN1 Switch", "IN1 Input"},
{"Receiver Mixer", "IN2 Switch", "IN2 Input"},
/* Left Lineout output mixer */
{"Left Lineout Mixer", "Left DAC1 Switch", "DACL1"},
{"Left Lineout Mixer", "Right DAC1 Switch", "DACR1"},
{"Left Lineout Mixer", "MIC1 Switch", "MIC1 Input"},
{"Left Lineout Mixer", "MIC2 Switch", "MIC2 Input"},
{"Left Lineout Mixer", "IN1 Switch", "IN1 Input"},
{"Left Lineout Mixer", "IN2 Switch", "IN2 Input"},
/* Right lineout output mixer */
{"Right Lineout Mixer", "Left DAC1 Switch", "DACL1"},
{"Right Lineout Mixer", "Right DAC1 Switch", "DACR1"},
{"Right Lineout Mixer", "MIC1 Switch", "MIC1 Input"},
{"Right Lineout Mixer", "MIC2 Switch", "MIC2 Input"},
{"Right Lineout Mixer", "IN1 Switch", "IN1 Input"},
{"Right Lineout Mixer", "IN2 Switch", "IN2 Input"},
{"HP Left Out", NULL, "Left Headphone Mixer"},
{"HP Right Out", NULL, "Right Headphone Mixer"},
{"SPK Left Out", NULL, "Left Speaker Mixer"},
{"SPK Right Out", NULL, "Right Speaker Mixer"},
{"RCV Mono Out", NULL, "Receiver Mixer"},
{"LINE Left Out", NULL, "Left Lineout Mixer"},
{"LINE Right Out", NULL, "Right Lineout Mixer"},
{"HPL", NULL, "HP Left Out"},
{"HPR", NULL, "HP Right Out"},
{"SPKL", NULL, "SPK Left Out"},
{"SPKR", NULL, "SPK Right Out"},
{"RCV", NULL, "RCV Mono Out"},
{"OUT1", NULL, "LINE Left Out"},
{"OUT2", NULL, "LINE Right Out"},
{"OUT3", NULL, "LINE Left Out"},
{"OUT4", NULL, "LINE Right Out"},
/* Left ADC input mixer */
{"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
{"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
{"Left ADC Mixer", "IN1 Switch", "IN1 Input"},
{"Left ADC Mixer", "IN2 Switch", "IN2 Input"},
/* Right ADC input mixer */
{"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
{"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
{"Right ADC Mixer", "IN1 Switch", "IN1 Input"},
{"Right ADC Mixer", "IN2 Switch", "IN2 Input"},
/* Inputs */
{"ADCL", NULL, "Left ADC Mixer"},
{"ADCR", NULL, "Right ADC Mixer"},
{"IN1 Input", NULL, "INA1"},
{"IN2 Input", NULL, "INA2"},
{"MIC1 Input", NULL, "MIC1"},
{"MIC2 Input", NULL, "MIC2"},
};
/* codec mclk clock divider coefficients */
static const struct {
u32 rate;
u8 sr;
} rate_table[] = {
{8000, 0x01},
{11025, 0x02},
{16000, 0x03},
{22050, 0x04},
{24000, 0x05},
{32000, 0x06},
{44100, 0x07},
{48000, 0x08},
{88200, 0x09},
{96000, 0x0A},
};
static int rate_value(int rate, u8 *value)
{
int i;
for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
if (rate_table[i].rate >= rate) {
*value = rate_table[i].sr;
return 0;
}
}
*value = rate_table[0].sr;
return -EINVAL;
}
static int max98095_dai1_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
struct max98095_cdata *cdata;
unsigned long long ni;
unsigned int rate;
u8 regval;
cdata = &max98095->dai[0];
rate = params_rate(params);
switch (params_width(params)) {
case 16:
snd_soc_component_update_bits(component, M98095_02A_DAI1_FORMAT,
M98095_DAI_WS, 0);
break;
case 24:
snd_soc_component_update_bits(component, M98095_02A_DAI1_FORMAT,
M98095_DAI_WS, M98095_DAI_WS);
break;
default:
return -EINVAL;
}
if (rate_value(rate, ®val))
return -EINVAL;
snd_soc_component_update_bits(component, M98095_027_DAI1_CLKMODE,
M98095_CLKMODE_MASK, regval);
cdata->rate = rate;
/* Configure NI when operating as master */
if (snd_soc_component_read(component, M98095_02A_DAI1_FORMAT) & M98095_DAI_MAS) {
if (max98095->sysclk == 0) {
dev_err(component->dev, "Invalid system clock frequency\n");
return -EINVAL;
}
ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
* (unsigned long long int)rate;
do_div(ni, (unsigned long long int)max98095->sysclk);
snd_soc_component_write(component, M98095_028_DAI1_CLKCFG_HI,
(ni >> 8) & 0x7F);
snd_soc_component_write(component, M98095_029_DAI1_CLKCFG_LO,
ni & 0xFF);
}
/* Update sample rate mode */
if (rate < 50000)
snd_soc_component_update_bits(component, M98095_02E_DAI1_FILTERS,
M98095_DAI_DHF, 0);
else
snd_soc_component_update_bits(component, M98095_02E_DAI1_FILTERS,
M98095_DAI_DHF, M98095_DAI_DHF);
return 0;
}
static int max98095_dai2_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
struct max98095_cdata *cdata;
unsigned long long ni;
unsigned int rate;
u8 regval;
cdata = &max98095->dai[1];
rate = params_rate(params);
switch (params_width(params)) {
case 16:
snd_soc_component_update_bits(component, M98095_034_DAI2_FORMAT,
M98095_DAI_WS, 0);
break;
case 24:
snd_soc_component_update_bits(component, M98095_034_DAI2_FORMAT,
M98095_DAI_WS, M98095_DAI_WS);
break;
default:
return -EINVAL;
}
if (rate_value(rate, ®val))
return -EINVAL;
snd_soc_component_update_bits(component, M98095_031_DAI2_CLKMODE,
M98095_CLKMODE_MASK, regval);
cdata->rate = rate;
/* Configure NI when operating as master */
if (snd_soc_component_read(component, M98095_034_DAI2_FORMAT) & M98095_DAI_MAS) {
if (max98095->sysclk == 0) {
dev_err(component->dev, "Invalid system clock frequency\n");
return -EINVAL;
}
ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
* (unsigned long long int)rate;
do_div(ni, (unsigned long long int)max98095->sysclk);
snd_soc_component_write(component, M98095_032_DAI2_CLKCFG_HI,
(ni >> 8) & 0x7F);
snd_soc_component_write(component, M98095_033_DAI2_CLKCFG_LO,
ni & 0xFF);
}
/* Update sample rate mode */
if (rate < 50000)
snd_soc_component_update_bits(component, M98095_038_DAI2_FILTERS,
M98095_DAI_DHF, 0);
else
snd_soc_component_update_bits(component, M98095_038_DAI2_FILTERS,
M98095_DAI_DHF, M98095_DAI_DHF);
return 0;
}
static int max98095_dai3_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
struct max98095_cdata *cdata;
unsigned long long ni;
unsigned int rate;
u8 regval;
cdata = &max98095->dai[2];
rate = params_rate(params);
switch (params_width(params)) {
case 16:
snd_soc_component_update_bits(component, M98095_03E_DAI3_FORMAT,
M98095_DAI_WS, 0);
break;
case 24:
snd_soc_component_update_bits(component, M98095_03E_DAI3_FORMAT,
M98095_DAI_WS, M98095_DAI_WS);
break;
default:
return -EINVAL;
}
if (rate_value(rate, ®val))
return -EINVAL;
snd_soc_component_update_bits(component, M98095_03B_DAI3_CLKMODE,
M98095_CLKMODE_MASK, regval);
cdata->rate = rate;
/* Configure NI when operating as master */
if (snd_soc_component_read(component, M98095_03E_DAI3_FORMAT) & M98095_DAI_MAS) {
if (max98095->sysclk == 0) {
dev_err(component->dev, "Invalid system clock frequency\n");
return -EINVAL;
}
ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
* (unsigned long long int)rate;
do_div(ni, (unsigned long long int)max98095->sysclk);
snd_soc_component_write(component, M98095_03C_DAI3_CLKCFG_HI,
(ni >> 8) & 0x7F);
snd_soc_component_write(component, M98095_03D_DAI3_CLKCFG_LO,
ni & 0xFF);
}
/* Update sample rate mode */
if (rate < 50000)
snd_soc_component_update_bits(component, M98095_042_DAI3_FILTERS,
M98095_DAI_DHF, 0);
else
snd_soc_component_update_bits(component, M98095_042_DAI3_FILTERS,
M98095_DAI_DHF, M98095_DAI_DHF);
return 0;
}
static int max98095_dai_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
/* Requested clock frequency is already setup */
if (freq == max98095->sysclk)
return 0;
if (!IS_ERR(max98095->mclk)) {
freq = clk_round_rate(max98095->mclk, freq);
clk_set_rate(max98095->mclk, freq);
}
/* Setup clocks for slave mode, and using the PLL
* PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
* 0x02 (when master clk is 20MHz to 40MHz)..
* 0x03 (when master clk is 40MHz to 60MHz)..
*/
if ((freq >= 10000000) && (freq < 20000000)) {
snd_soc_component_write(component, M98095_026_SYS_CLK, 0x10);
} else if ((freq >= 20000000) && (freq < 40000000)) {
snd_soc_component_write(component, M98095_026_SYS_CLK, 0x20);
} else if ((freq >= 40000000) && (freq < 60000000)) {
snd_soc_component_write(component, M98095_026_SYS_CLK, 0x30);
} else {
dev_err(component->dev, "Invalid master clock frequency\n");
return -EINVAL;
}
dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
max98095->sysclk = freq;
return 0;
}
static int max98095_dai1_set_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
struct max98095_cdata *cdata;
u8 regval = 0;
cdata = &max98095->dai[0];
if (fmt != cdata->fmt) {
cdata->fmt = fmt;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC:
/* Consumer mode PLL */
snd_soc_component_write(component, M98095_028_DAI1_CLKCFG_HI,
0x80);
snd_soc_component_write(component, M98095_029_DAI1_CLKCFG_LO,
0x00);
break;
case SND_SOC_DAIFMT_CBP_CFP:
/* Set to provider mode */
regval |= M98095_DAI_MAS;
break;
default:
dev_err(component->dev, "Clock mode unsupported");
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
regval |= M98095_DAI_DLY;
break;
case SND_SOC_DAIFMT_LEFT_J:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_NB_IF:
regval |= M98095_DAI_WCI;
break;
case SND_SOC_DAIFMT_IB_NF:
regval |= M98095_DAI_BCI;
break;
case SND_SOC_DAIFMT_IB_IF:
regval |= M98095_DAI_BCI|M98095_DAI_WCI;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, M98095_02A_DAI1_FORMAT,
M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
M98095_DAI_WCI, regval);
snd_soc_component_write(component, M98095_02B_DAI1_CLOCK, M98095_DAI_BSEL64);
}
return 0;
}
static int max98095_dai2_set_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
struct max98095_cdata *cdata;
u8 regval = 0;
cdata = &max98095->dai[1];
if (fmt != cdata->fmt) {
cdata->fmt = fmt;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC:
/* Consumer mode PLL */
snd_soc_component_write(component, M98095_032_DAI2_CLKCFG_HI,
0x80);
snd_soc_component_write(component, M98095_033_DAI2_CLKCFG_LO,
0x00);
break;
case SND_SOC_DAIFMT_CBP_CFP:
/* Set to provider mode */
regval |= M98095_DAI_MAS;
break;
default:
dev_err(component->dev, "Clock mode unsupported");
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
regval |= M98095_DAI_DLY;
break;
case SND_SOC_DAIFMT_LEFT_J:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_NB_IF:
regval |= M98095_DAI_WCI;
break;
case SND_SOC_DAIFMT_IB_NF:
regval |= M98095_DAI_BCI;
break;
case SND_SOC_DAIFMT_IB_IF:
regval |= M98095_DAI_BCI|M98095_DAI_WCI;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, M98095_034_DAI2_FORMAT,
M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
M98095_DAI_WCI, regval);
snd_soc_component_write(component, M98095_035_DAI2_CLOCK,
M98095_DAI_BSEL64);
}
return 0;
}
static int max98095_dai3_set_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
struct max98095_cdata *cdata;
u8 regval = 0;
cdata = &max98095->dai[2];
if (fmt != cdata->fmt) {
cdata->fmt = fmt;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC:
/* Consumer mode PLL */
snd_soc_component_write(component, M98095_03C_DAI3_CLKCFG_HI,
0x80);
snd_soc_component_write(component, M98095_03D_DAI3_CLKCFG_LO,
0x00);
break;
case SND_SOC_DAIFMT_CBP_CFP:
/* Set to provider mode */
regval |= M98095_DAI_MAS;
break;
default:
dev_err(component->dev, "Clock mode unsupported");
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
regval |= M98095_DAI_DLY;
break;
case SND_SOC_DAIFMT_LEFT_J:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_NB_IF:
regval |= M98095_DAI_WCI;
break;
case SND_SOC_DAIFMT_IB_NF:
regval |= M98095_DAI_BCI;
break;
case SND_SOC_DAIFMT_IB_IF:
regval |= M98095_DAI_BCI|M98095_DAI_WCI;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, M98095_03E_DAI3_FORMAT,
M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
M98095_DAI_WCI, regval);
snd_soc_component_write(component, M98095_03F_DAI3_CLOCK,
M98095_DAI_BSEL64);
}
return 0;
}
static int max98095_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
int ret;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
/*
* SND_SOC_BIAS_PREPARE is called while preparing for a
* transition to ON or away from ON. If current bias_level
* is SND_SOC_BIAS_ON, then it is preparing for a transition
* away from ON. Disable the clock in that case, otherwise
* enable it.
*/
if (IS_ERR(max98095->mclk))
break;
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) {
clk_disable_unprepare(max98095->mclk);
} else {
ret = clk_prepare_enable(max98095->mclk);
if (ret)
return ret;
}
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
ret = regcache_sync(max98095->regmap);
if (ret != 0) {
dev_err(component->dev, "Failed to sync cache: %d\n", ret);
return ret;
}
}
snd_soc_component_update_bits(component, M98095_090_PWR_EN_IN,
M98095_MBEN, M98095_MBEN);
break;
case SND_SOC_BIAS_OFF:
snd_soc_component_update_bits(component, M98095_090_PWR_EN_IN,
M98095_MBEN, 0);
regcache_mark_dirty(max98095->regmap);
break;
}
return 0;
}
#define MAX98095_RATES SNDRV_PCM_RATE_8000_96000
#define MAX98095_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
static const struct snd_soc_dai_ops max98095_dai1_ops = {
.set_sysclk = max98095_dai_set_sysclk,
.set_fmt = max98095_dai1_set_fmt,
.hw_params = max98095_dai1_hw_params,
};
static const struct snd_soc_dai_ops max98095_dai2_ops = {
.set_sysclk = max98095_dai_set_sysclk,
.set_fmt = max98095_dai2_set_fmt,
.hw_params = max98095_dai2_hw_params,
};
static const struct snd_soc_dai_ops max98095_dai3_ops = {
.set_sysclk = max98095_dai_set_sysclk,
.set_fmt = max98095_dai3_set_fmt,
.hw_params = max98095_dai3_hw_params,
};
static struct snd_soc_dai_driver max98095_dai[] = {
{
.name = "HiFi",
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MAX98095_RATES,
.formats = MAX98095_FORMATS,
},
.capture = {
.stream_name = "HiFi Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MAX98095_RATES,
.formats = MAX98095_FORMATS,
},
.ops = &max98095_dai1_ops,
},
{
.name = "Aux",
.playback = {
.stream_name = "Aux Playback",
.channels_min = 1,
.channels_max = 1,
.rates = MAX98095_RATES,
.formats = MAX98095_FORMATS,
},
.ops = &max98095_dai2_ops,
},
{
.name = "Voice",
.playback = {
.stream_name = "Voice Playback",
.channels_min = 1,
.channels_max = 1,
.rates = MAX98095_RATES,
.formats = MAX98095_FORMATS,
},
.ops = &max98095_dai3_ops,
}
};
static int max98095_get_eq_channel(const char *name)
{
if (strcmp(name, "EQ1 Mode") == 0)
return 0;
if (strcmp(name, "EQ2 Mode") == 0)
return 1;
return -EINVAL;
}
static int max98095_put_eq_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
struct max98095_pdata *pdata = max98095->pdata;
int channel = max98095_get_eq_channel(kcontrol->id.name);
struct max98095_cdata *cdata;
unsigned int sel = ucontrol->value.enumerated.item[0];
struct max98095_eq_cfg *coef_set;
int fs, best, best_val, i;
int regmask, regsave;
if (WARN_ON(channel > 1))
return -EINVAL;
if (!pdata || !max98095->eq_textcnt)
return 0;
if (sel >= pdata->eq_cfgcnt)
return -EINVAL;
cdata = &max98095->dai[channel];
cdata->eq_sel = sel;
fs = cdata->rate;
/* Find the selected configuration with nearest sample rate */
best = 0;
best_val = INT_MAX;
for (i = 0; i < pdata->eq_cfgcnt; i++) {
if (strcmp(pdata->eq_cfg[i].name, max98095->eq_texts[sel]) == 0 &&
abs(pdata->eq_cfg[i].rate - fs) < best_val) {
best = i;
best_val = abs(pdata->eq_cfg[i].rate - fs);
}
}
dev_dbg(component->dev, "Selected %s/%dHz for %dHz sample rate\n",
pdata->eq_cfg[best].name,
pdata->eq_cfg[best].rate, fs);
coef_set = &pdata->eq_cfg[best];
regmask = (channel == 0) ? M98095_EQ1EN : M98095_EQ2EN;
/* Disable filter while configuring, and save current on/off state */
regsave = snd_soc_component_read(component, M98095_088_CFG_LEVEL);
snd_soc_component_update_bits(component, M98095_088_CFG_LEVEL, regmask, 0);
mutex_lock(&max98095->lock);
snd_soc_component_update_bits(component, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG);
m98095_eq_band(component, channel, 0, coef_set->band1);
m98095_eq_band(component, channel, 1, coef_set->band2);
m98095_eq_band(component, channel, 2, coef_set->band3);
m98095_eq_band(component, channel, 3, coef_set->band4);
m98095_eq_band(component, channel, 4, coef_set->band5);
snd_soc_component_update_bits(component, M98095_00F_HOST_CFG, M98095_SEG, 0);
mutex_unlock(&max98095->lock);
/* Restore the original on/off state */
snd_soc_component_update_bits(component, M98095_088_CFG_LEVEL, regmask, regsave);
return 0;
}
static int max98095_get_eq_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
int channel = max98095_get_eq_channel(kcontrol->id.name);
struct max98095_cdata *cdata;
cdata = &max98095->dai[channel];
ucontrol->value.enumerated.item[0] = cdata->eq_sel;
return 0;
}
static void max98095_handle_eq_pdata(struct snd_soc_component *component)
{
struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
struct max98095_pdata *pdata = max98095->pdata;
struct max98095_eq_cfg *cfg;
unsigned int cfgcnt;
int i, j;
const char **t;
int ret;
struct snd_kcontrol_new controls[] = {
SOC_ENUM_EXT("EQ1 Mode",
max98095->eq_enum,
max98095_get_eq_enum,
max98095_put_eq_enum),
SOC_ENUM_EXT("EQ2 Mode",
max98095->eq_enum,
max98095_get_eq_enum,
max98095_put_eq_enum),
};
cfg = pdata->eq_cfg;
cfgcnt = pdata->eq_cfgcnt;
/* Setup an array of texts for the equalizer enum.
* This is based on Mark Brown's equalizer driver code.
*/
max98095->eq_textcnt = 0;
max98095->eq_texts = NULL;
for (i = 0; i < cfgcnt; i++) {
for (j = 0; j < max98095->eq_textcnt; j++) {
if (strcmp(cfg[i].name, max98095->eq_texts[j]) == 0)
break;
}
if (j != max98095->eq_textcnt)
continue;
/* Expand the array */
t = krealloc(max98095->eq_texts,
sizeof(char *) * (max98095->eq_textcnt + 1),
GFP_KERNEL);
if (t == NULL)
continue;
/* Store the new entry */
t[max98095->eq_textcnt] = cfg[i].name;
max98095->eq_textcnt++;
max98095->eq_texts = t;
}
/* Now point the soc_enum to .texts array items */
max98095->eq_enum.texts = max98095->eq_texts;
max98095->eq_enum.items = max98095->eq_textcnt;
ret = snd_soc_add_component_controls(component, controls, ARRAY_SIZE(controls));
if (ret != 0)
dev_err(component->dev, "Failed to add EQ control: %d\n", ret);
}
static const char *bq_mode_name[] = {"Biquad1 Mode", "Biquad2 Mode"};
static int max98095_get_bq_channel(struct snd_soc_component *component,
const char *name)
{
int ret;
ret = match_string(bq_mode_name, ARRAY_SIZE(bq_mode_name), name);
if (ret < 0)
dev_err(component->dev, "Bad biquad channel name '%s'\n", name);
return ret;
}
static int max98095_put_bq_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
struct max98095_pdata *pdata = max98095->pdata;
int channel = max98095_get_bq_channel(component, kcontrol->id.name);
struct max98095_cdata *cdata;
unsigned int sel = ucontrol->value.enumerated.item[0];
struct max98095_biquad_cfg *coef_set;
int fs, best, best_val, i;
int regmask, regsave;
if (channel < 0)
return channel;
if (!pdata || !max98095->bq_textcnt)
return 0;
if (sel >= pdata->bq_cfgcnt)
return -EINVAL;
cdata = &max98095->dai[channel];
cdata->bq_sel = sel;
fs = cdata->rate;
/* Find the selected configuration with nearest sample rate */
best = 0;
best_val = INT_MAX;
for (i = 0; i < pdata->bq_cfgcnt; i++) {
if (strcmp(pdata->bq_cfg[i].name, max98095->bq_texts[sel]) == 0 &&
abs(pdata->bq_cfg[i].rate - fs) < best_val) {
best = i;
best_val = abs(pdata->bq_cfg[i].rate - fs);
}
}
dev_dbg(component->dev, "Selected %s/%dHz for %dHz sample rate\n",
pdata->bq_cfg[best].name,
pdata->bq_cfg[best].rate, fs);
coef_set = &pdata->bq_cfg[best];
regmask = (channel == 0) ? M98095_BQ1EN : M98095_BQ2EN;
/* Disable filter while configuring, and save current on/off state */
regsave = snd_soc_component_read(component, M98095_088_CFG_LEVEL);
snd_soc_component_update_bits(component, M98095_088_CFG_LEVEL, regmask, 0);
mutex_lock(&max98095->lock);
snd_soc_component_update_bits(component, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG);
m98095_biquad_band(component, channel, 0, coef_set->band1);
m98095_biquad_band(component, channel, 1, coef_set->band2);
snd_soc_component_update_bits(component, M98095_00F_HOST_CFG, M98095_SEG, 0);
mutex_unlock(&max98095->lock);
/* Restore the original on/off state */
snd_soc_component_update_bits(component, M98095_088_CFG_LEVEL, regmask, regsave);
return 0;
}
static int max98095_get_bq_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
int channel = max98095_get_bq_channel(component, kcontrol->id.name);
struct max98095_cdata *cdata;
if (channel < 0)
return channel;
cdata = &max98095->dai[channel];
ucontrol->value.enumerated.item[0] = cdata->bq_sel;
return 0;
}
static void max98095_handle_bq_pdata(struct snd_soc_component *component)
{
struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
struct max98095_pdata *pdata = max98095->pdata;
struct max98095_biquad_cfg *cfg;
unsigned int cfgcnt;
int i, j;
const char **t;
int ret;
struct snd_kcontrol_new controls[] = {
SOC_ENUM_EXT((char *)bq_mode_name[0],
max98095->bq_enum,
max98095_get_bq_enum,
max98095_put_bq_enum),
SOC_ENUM_EXT((char *)bq_mode_name[1],
max98095->bq_enum,
max98095_get_bq_enum,
max98095_put_bq_enum),
};
BUILD_BUG_ON(ARRAY_SIZE(controls) != ARRAY_SIZE(bq_mode_name));
cfg = pdata->bq_cfg;
cfgcnt = pdata->bq_cfgcnt;
/* Setup an array of texts for the biquad enum.
* This is based on Mark Brown's equalizer driver code.
*/
max98095->bq_textcnt = 0;
max98095->bq_texts = NULL;
for (i = 0; i < cfgcnt; i++) {
for (j = 0; j < max98095->bq_textcnt; j++) {
if (strcmp(cfg[i].name, max98095->bq_texts[j]) == 0)
break;
}
if (j != max98095->bq_textcnt)
continue;
/* Expand the array */
t = krealloc(max98095->bq_texts,
sizeof(char *) * (max98095->bq_textcnt + 1),
GFP_KERNEL);
if (t == NULL)
continue;
/* Store the new entry */
t[max98095->bq_textcnt] = cfg[i].name;
max98095->bq_textcnt++;
max98095->bq_texts = t;
}
/* Now point the soc_enum to .texts array items */
max98095->bq_enum.texts = max98095->bq_texts;
max98095->bq_enum.items = max98095->bq_textcnt;
ret = snd_soc_add_component_controls(component, controls, ARRAY_SIZE(controls));
if (ret != 0)
dev_err(component->dev, "Failed to add Biquad control: %d\n", ret);
}
static void max98095_handle_pdata(struct snd_soc_component *component)
{
struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
struct max98095_pdata *pdata = max98095->pdata;
u8 regval = 0;
if (!pdata) {
dev_dbg(component->dev, "No platform data\n");
return;
}
/* Configure mic for analog/digital mic mode */
if (pdata->digmic_left_mode)
regval |= M98095_DIGMIC_L;
if (pdata->digmic_right_mode)
regval |= M98095_DIGMIC_R;
snd_soc_component_write(component, M98095_087_CFG_MIC, regval);
/* Configure equalizers */
if (pdata->eq_cfgcnt)
max98095_handle_eq_pdata(component);
/* Configure bi-quad filters */
if (pdata->bq_cfgcnt)
max98095_handle_bq_pdata(component);
}
static irqreturn_t max98095_report_jack(int irq, void *data)
{
struct snd_soc_component *component = data;
struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
unsigned int value;
int hp_report = 0;
int mic_report = 0;
/* Read the Jack Status Register */
value = snd_soc_component_read(component, M98095_007_JACK_AUTO_STS);
/* If ddone is not set, then detection isn't finished yet */
if ((value & M98095_DDONE) == 0)
return IRQ_NONE;
/* if hp, check its bit, and if set, clear it */
if ((value & M98095_HP_IN || value & M98095_LO_IN) &&
max98095->headphone_jack)
hp_report |= SND_JACK_HEADPHONE;
/* if mic, check its bit, and if set, clear it */
if ((value & M98095_MIC_IN) && max98095->mic_jack)
mic_report |= SND_JACK_MICROPHONE;
if (max98095->headphone_jack == max98095->mic_jack) {
snd_soc_jack_report(max98095->headphone_jack,
hp_report | mic_report,
SND_JACK_HEADSET);
} else {
if (max98095->headphone_jack)
snd_soc_jack_report(max98095->headphone_jack,
hp_report, SND_JACK_HEADPHONE);
if (max98095->mic_jack)
snd_soc_jack_report(max98095->mic_jack,
mic_report, SND_JACK_MICROPHONE);
}
return IRQ_HANDLED;
}
static int max98095_jack_detect_enable(struct snd_soc_component *component)
{
struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
int ret = 0;
int detect_enable = M98095_JDEN;
unsigned int slew = M98095_DEFAULT_SLEW_DELAY;
if (max98095->pdata->jack_detect_pin5en)
detect_enable |= M98095_PIN5EN;
if (max98095->pdata->jack_detect_delay)
slew = max98095->pdata->jack_detect_delay;
ret = snd_soc_component_write(component, M98095_08E_JACK_DC_SLEW, slew);
if (ret < 0) {
dev_err(component->dev, "Failed to cfg auto detect %d\n", ret);
return ret;
}
/* configure auto detection to be enabled */
ret = snd_soc_component_write(component, M98095_089_JACK_DET_AUTO, detect_enable);
if (ret < 0) {
dev_err(component->dev, "Failed to cfg auto detect %d\n", ret);
return ret;
}
return ret;
}
static int max98095_jack_detect_disable(struct snd_soc_component *component)
{
int ret = 0;
/* configure auto detection to be disabled */
ret = snd_soc_component_write(component, M98095_089_JACK_DET_AUTO, 0x0);
if (ret < 0) {
dev_err(component->dev, "Failed to cfg auto detect %d\n", ret);
return ret;
}
return ret;
}
int max98095_jack_detect(struct snd_soc_component *component,
struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack)
{
struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
struct i2c_client *client = to_i2c_client(component->dev);
int ret = 0;
max98095->headphone_jack = hp_jack;
max98095->mic_jack = mic_jack;
/* only progress if we have at least 1 jack pointer */
if (!hp_jack && !mic_jack)
return -EINVAL;
max98095_jack_detect_enable(component);
/* enable interrupts for headphone jack detection */
ret = snd_soc_component_update_bits(component, M98095_013_JACK_INT_EN,
M98095_IDDONE, M98095_IDDONE);
if (ret < 0) {
dev_err(component->dev, "Failed to cfg jack irqs %d\n", ret);
return ret;
}
max98095_report_jack(client->irq, component);
return 0;
}
EXPORT_SYMBOL_GPL(max98095_jack_detect);
#ifdef CONFIG_PM
static int max98095_suspend(struct snd_soc_component *component)
{
struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
if (max98095->headphone_jack || max98095->mic_jack)
max98095_jack_detect_disable(component);
snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
return 0;
}
static int max98095_resume(struct snd_soc_component *component)
{
struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
struct i2c_client *client = to_i2c_client(component->dev);
snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
if (max98095->headphone_jack || max98095->mic_jack) {
max98095_jack_detect_enable(component);
max98095_report_jack(client->irq, component);
}
return 0;
}
#else
#define max98095_suspend NULL
#define max98095_resume NULL
#endif
static int max98095_reset(struct snd_soc_component *component)
{
int i, ret;
/* Gracefully reset the DSP core and the codec hardware
* in a proper sequence */
ret = snd_soc_component_write(component, M98095_00F_HOST_CFG, 0);
if (ret < 0) {
dev_err(component->dev, "Failed to reset DSP: %d\n", ret);
return ret;
}
ret = snd_soc_component_write(component, M98095_097_PWR_SYS, 0);
if (ret < 0) {
dev_err(component->dev, "Failed to reset component: %d\n", ret);
return ret;
}
/* Reset to hardware default for registers, as there is not
* a soft reset hardware control register */
for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) {
ret = snd_soc_component_write(component, i, snd_soc_component_read(component, i));
if (ret < 0) {
dev_err(component->dev, "Failed to reset: %d\n", ret);
return ret;
}
}
return ret;
}
static int max98095_probe(struct snd_soc_component *component)
{
struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
struct max98095_cdata *cdata;
struct i2c_client *client;
int ret = 0;
max98095->mclk = devm_clk_get(component->dev, "mclk");
if (PTR_ERR(max98095->mclk) == -EPROBE_DEFER)
return -EPROBE_DEFER;
/* reset the codec, the DSP core, and disable all interrupts */
max98095_reset(component);
client = to_i2c_client(component->dev);
/* initialize private data */
max98095->sysclk = (unsigned)-1;
max98095->eq_textcnt = 0;
max98095->bq_textcnt = 0;
cdata = &max98095->dai[0];
cdata->rate = (unsigned)-1;
cdata->fmt = (unsigned)-1;
cdata->eq_sel = 0;
cdata->bq_sel = 0;
cdata = &max98095->dai[1];
cdata->rate = (unsigned)-1;
cdata->fmt = (unsigned)-1;
cdata->eq_sel = 0;
cdata->bq_sel = 0;
cdata = &max98095->dai[2];
cdata->rate = (unsigned)-1;
cdata->fmt = (unsigned)-1;
cdata->eq_sel = 0;
cdata->bq_sel = 0;
max98095->lin_state = 0;
max98095->mic1pre = 0;
max98095->mic2pre = 0;
if (client->irq) {
/* register an audio interrupt */
ret = request_threaded_irq(client->irq, NULL,
max98095_report_jack,
IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING |
IRQF_ONESHOT, "max98095", component);
if (ret) {
dev_err(component->dev, "Failed to request IRQ: %d\n", ret);
goto err_access;
}
}
ret = snd_soc_component_read(component, M98095_0FF_REV_ID);
if (ret < 0) {
dev_err(component->dev, "Failure reading hardware revision: %d\n",
ret);
goto err_irq;
}
dev_info(component->dev, "Hardware revision: %c\n", ret - 0x40 + 'A');
snd_soc_component_write(component, M98095_097_PWR_SYS, M98095_PWRSV);
snd_soc_component_write(component, M98095_048_MIX_DAC_LR,
M98095_DAI1L_TO_DACL|M98095_DAI1R_TO_DACR);
snd_soc_component_write(component, M98095_049_MIX_DAC_M,
M98095_DAI2M_TO_DACM|M98095_DAI3M_TO_DACM);
snd_soc_component_write(component, M98095_092_PWR_EN_OUT, M98095_SPK_SPREADSPECTRUM);
snd_soc_component_write(component, M98095_045_CFG_DSP, M98095_DSPNORMAL);
snd_soc_component_write(component, M98095_04E_CFG_HP, M98095_HPNORMAL);
snd_soc_component_write(component, M98095_02C_DAI1_IOCFG,
M98095_S1NORMAL|M98095_SDATA);
snd_soc_component_write(component, M98095_036_DAI2_IOCFG,
M98095_S2NORMAL|M98095_SDATA);
snd_soc_component_write(component, M98095_040_DAI3_IOCFG,
M98095_S3NORMAL|M98095_SDATA);
max98095_handle_pdata(component);
/* take the codec out of the shut down */
snd_soc_component_update_bits(component, M98095_097_PWR_SYS, M98095_SHDNRUN,
M98095_SHDNRUN);
return 0;
err_irq:
if (client->irq)
free_irq(client->irq, component);
err_access:
return ret;
}
static void max98095_remove(struct snd_soc_component *component)
{
struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
struct i2c_client *client = to_i2c_client(component->dev);
if (max98095->headphone_jack || max98095->mic_jack)
max98095_jack_detect_disable(component);
if (client->irq)
free_irq(client->irq, component);
}
static const struct snd_soc_component_driver soc_component_dev_max98095 = {
.probe = max98095_probe,
.remove = max98095_remove,
.suspend = max98095_suspend,
.resume = max98095_resume,
.set_bias_level = max98095_set_bias_level,
.controls = max98095_snd_controls,
.num_controls = ARRAY_SIZE(max98095_snd_controls),
.dapm_widgets = max98095_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(max98095_dapm_widgets),
.dapm_routes = max98095_audio_map,
.num_dapm_routes = ARRAY_SIZE(max98095_audio_map),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct i2c_device_id max98095_i2c_id[] = {
{ "max98095", MAX98095 },
{ }
};
MODULE_DEVICE_TABLE(i2c, max98095_i2c_id);
static int max98095_i2c_probe(struct i2c_client *i2c)
{
struct max98095_priv *max98095;
int ret;
const struct i2c_device_id *id;
max98095 = devm_kzalloc(&i2c->dev, sizeof(struct max98095_priv),
GFP_KERNEL);
if (max98095 == NULL)
return -ENOMEM;
mutex_init(&max98095->lock);
max98095->regmap = devm_regmap_init_i2c(i2c, &max98095_regmap);
if (IS_ERR(max98095->regmap)) {
ret = PTR_ERR(max98095->regmap);
dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
return ret;
}
id = i2c_match_id(max98095_i2c_id, i2c);
max98095->devtype = id->driver_data;
i2c_set_clientdata(i2c, max98095);
max98095->pdata = i2c->dev.platform_data;
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_max98095,
max98095_dai, ARRAY_SIZE(max98095_dai));
return ret;
}
#ifdef CONFIG_OF
static const struct of_device_id max98095_of_match[] = {
{ .compatible = "maxim,max98095", },
{ }
};
MODULE_DEVICE_TABLE(of, max98095_of_match);
#endif
static struct i2c_driver max98095_i2c_driver = {
.driver = {
.name = "max98095",
.of_match_table = of_match_ptr(max98095_of_match),
},
.probe = max98095_i2c_probe,
.id_table = max98095_i2c_id,
};
module_i2c_driver(max98095_i2c_driver);
MODULE_DESCRIPTION("ALSA SoC MAX98095 driver");
MODULE_AUTHOR("Peter Hsiang");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/max98095.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* rt5616.c -- RT5616 ALSA SoC audio codec driver
*
* Copyright 2015 Realtek Semiconductor Corp.
* Author: Bard Liao <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "rl6231.h"
#include "rt5616.h"
#define RT5616_PR_RANGE_BASE (0xff + 1)
#define RT5616_PR_SPACING 0x100
#define RT5616_PR_BASE (RT5616_PR_RANGE_BASE + (0 * RT5616_PR_SPACING))
static const struct regmap_range_cfg rt5616_ranges[] = {
{
.name = "PR",
.range_min = RT5616_PR_BASE,
.range_max = RT5616_PR_BASE + 0xf8,
.selector_reg = RT5616_PRIV_INDEX,
.selector_mask = 0xff,
.selector_shift = 0x0,
.window_start = RT5616_PRIV_DATA,
.window_len = 0x1,
},
};
static const struct reg_sequence init_list[] = {
{RT5616_PR_BASE + 0x3d, 0x3e00},
{RT5616_PR_BASE + 0x25, 0x6110},
{RT5616_PR_BASE + 0x20, 0x611f},
{RT5616_PR_BASE + 0x21, 0x4040},
{RT5616_PR_BASE + 0x23, 0x0004},
};
#define RT5616_INIT_REG_LEN ARRAY_SIZE(init_list)
static const struct reg_default rt5616_reg[] = {
{ 0x00, 0x0021 },
{ 0x02, 0xc8c8 },
{ 0x03, 0xc8c8 },
{ 0x05, 0x0000 },
{ 0x0d, 0x0000 },
{ 0x0f, 0x0808 },
{ 0x19, 0xafaf },
{ 0x1c, 0x2f2f },
{ 0x1e, 0x0000 },
{ 0x27, 0x7860 },
{ 0x29, 0x8080 },
{ 0x2a, 0x5252 },
{ 0x3b, 0x0000 },
{ 0x3c, 0x006f },
{ 0x3d, 0x0000 },
{ 0x3e, 0x006f },
{ 0x45, 0x6000 },
{ 0x4d, 0x0000 },
{ 0x4e, 0x0000 },
{ 0x4f, 0x0279 },
{ 0x50, 0x0000 },
{ 0x51, 0x0000 },
{ 0x52, 0x0279 },
{ 0x53, 0xf000 },
{ 0x61, 0x0000 },
{ 0x62, 0x0000 },
{ 0x63, 0x00c0 },
{ 0x64, 0x0000 },
{ 0x65, 0x0000 },
{ 0x66, 0x0000 },
{ 0x70, 0x8000 },
{ 0x73, 0x1104 },
{ 0x74, 0x0c00 },
{ 0x80, 0x0000 },
{ 0x81, 0x0000 },
{ 0x82, 0x0000 },
{ 0x8b, 0x0600 },
{ 0x8e, 0x0004 },
{ 0x8f, 0x1100 },
{ 0x90, 0x0000 },
{ 0x91, 0x0c00 },
{ 0x92, 0x0000 },
{ 0x93, 0x2000 },
{ 0x94, 0x0200 },
{ 0x95, 0x0000 },
{ 0xb0, 0x2080 },
{ 0xb1, 0x0000 },
{ 0xb2, 0x0000 },
{ 0xb4, 0x2206 },
{ 0xb5, 0x1f00 },
{ 0xb6, 0x0000 },
{ 0xb7, 0x0000 },
{ 0xbb, 0x0000 },
{ 0xbc, 0x0000 },
{ 0xbd, 0x0000 },
{ 0xbe, 0x0000 },
{ 0xbf, 0x0000 },
{ 0xc0, 0x0100 },
{ 0xc1, 0x0000 },
{ 0xc2, 0x0000 },
{ 0xc8, 0x0000 },
{ 0xc9, 0x0000 },
{ 0xca, 0x0000 },
{ 0xcb, 0x0000 },
{ 0xcc, 0x0000 },
{ 0xcd, 0x0000 },
{ 0xce, 0x0000 },
{ 0xcf, 0x0013 },
{ 0xd0, 0x0680 },
{ 0xd1, 0x1c17 },
{ 0xd3, 0xb320 },
{ 0xd4, 0x0000 },
{ 0xd6, 0x0000 },
{ 0xd7, 0x0000 },
{ 0xd9, 0x0809 },
{ 0xda, 0x0000 },
{ 0xfa, 0x0010 },
{ 0xfb, 0x0000 },
{ 0xfc, 0x0000 },
{ 0xfe, 0x10ec },
{ 0xff, 0x6281 },
};
struct rt5616_priv {
struct snd_soc_component *component;
struct delayed_work patch_work;
struct regmap *regmap;
struct clk *mclk;
int sysclk;
int sysclk_src;
int lrck[RT5616_AIFS];
int bclk[RT5616_AIFS];
int master[RT5616_AIFS];
int pll_src;
int pll_in;
int pll_out;
};
static bool rt5616_volatile_register(struct device *dev, unsigned int reg)
{
int i;
for (i = 0; i < ARRAY_SIZE(rt5616_ranges); i++) {
if (reg >= rt5616_ranges[i].range_min &&
reg <= rt5616_ranges[i].range_max)
return true;
}
switch (reg) {
case RT5616_RESET:
case RT5616_PRIV_DATA:
case RT5616_EQ_CTRL1:
case RT5616_DRC_AGC_1:
case RT5616_IRQ_CTRL2:
case RT5616_INT_IRQ_ST:
case RT5616_PGM_REG_ARR1:
case RT5616_PGM_REG_ARR3:
case RT5616_VENDOR_ID:
case RT5616_DEVICE_ID:
return true;
default:
return false;
}
}
static bool rt5616_readable_register(struct device *dev, unsigned int reg)
{
int i;
for (i = 0; i < ARRAY_SIZE(rt5616_ranges); i++) {
if (reg >= rt5616_ranges[i].range_min &&
reg <= rt5616_ranges[i].range_max)
return true;
}
switch (reg) {
case RT5616_RESET:
case RT5616_VERSION_ID:
case RT5616_VENDOR_ID:
case RT5616_DEVICE_ID:
case RT5616_HP_VOL:
case RT5616_LOUT_CTRL1:
case RT5616_LOUT_CTRL2:
case RT5616_IN1_IN2:
case RT5616_INL1_INR1_VOL:
case RT5616_DAC1_DIG_VOL:
case RT5616_ADC_DIG_VOL:
case RT5616_ADC_BST_VOL:
case RT5616_STO1_ADC_MIXER:
case RT5616_AD_DA_MIXER:
case RT5616_STO_DAC_MIXER:
case RT5616_REC_L1_MIXER:
case RT5616_REC_L2_MIXER:
case RT5616_REC_R1_MIXER:
case RT5616_REC_R2_MIXER:
case RT5616_HPO_MIXER:
case RT5616_OUT_L1_MIXER:
case RT5616_OUT_L2_MIXER:
case RT5616_OUT_L3_MIXER:
case RT5616_OUT_R1_MIXER:
case RT5616_OUT_R2_MIXER:
case RT5616_OUT_R3_MIXER:
case RT5616_LOUT_MIXER:
case RT5616_PWR_DIG1:
case RT5616_PWR_DIG2:
case RT5616_PWR_ANLG1:
case RT5616_PWR_ANLG2:
case RT5616_PWR_MIXER:
case RT5616_PWR_VOL:
case RT5616_PRIV_INDEX:
case RT5616_PRIV_DATA:
case RT5616_I2S1_SDP:
case RT5616_ADDA_CLK1:
case RT5616_ADDA_CLK2:
case RT5616_GLB_CLK:
case RT5616_PLL_CTRL1:
case RT5616_PLL_CTRL2:
case RT5616_HP_OVCD:
case RT5616_DEPOP_M1:
case RT5616_DEPOP_M2:
case RT5616_DEPOP_M3:
case RT5616_CHARGE_PUMP:
case RT5616_PV_DET_SPK_G:
case RT5616_MICBIAS:
case RT5616_A_JD_CTL1:
case RT5616_A_JD_CTL2:
case RT5616_EQ_CTRL1:
case RT5616_EQ_CTRL2:
case RT5616_WIND_FILTER:
case RT5616_DRC_AGC_1:
case RT5616_DRC_AGC_2:
case RT5616_DRC_AGC_3:
case RT5616_SVOL_ZC:
case RT5616_JD_CTRL1:
case RT5616_JD_CTRL2:
case RT5616_IRQ_CTRL1:
case RT5616_IRQ_CTRL2:
case RT5616_INT_IRQ_ST:
case RT5616_GPIO_CTRL1:
case RT5616_GPIO_CTRL2:
case RT5616_GPIO_CTRL3:
case RT5616_PGM_REG_ARR1:
case RT5616_PGM_REG_ARR2:
case RT5616_PGM_REG_ARR3:
case RT5616_PGM_REG_ARR4:
case RT5616_PGM_REG_ARR5:
case RT5616_SCB_FUNC:
case RT5616_SCB_CTRL:
case RT5616_BASE_BACK:
case RT5616_MP3_PLUS1:
case RT5616_MP3_PLUS2:
case RT5616_ADJ_HPF_CTRL1:
case RT5616_ADJ_HPF_CTRL2:
case RT5616_HP_CALIB_AMP_DET:
case RT5616_HP_CALIB2:
case RT5616_SV_ZCD1:
case RT5616_SV_ZCD2:
case RT5616_D_MISC:
case RT5616_DUMMY2:
case RT5616_DUMMY3:
return true;
default:
return false;
}
}
static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(bst_tlv,
0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
);
static const struct snd_kcontrol_new rt5616_snd_controls[] = {
/* Headphone Output Volume */
SOC_DOUBLE("HP Playback Switch", RT5616_HP_VOL,
RT5616_L_MUTE_SFT, RT5616_R_MUTE_SFT, 1, 1),
SOC_DOUBLE("HPVOL Playback Switch", RT5616_HP_VOL,
RT5616_VOL_L_SFT, RT5616_VOL_R_SFT, 1, 1),
SOC_DOUBLE_TLV("HP Playback Volume", RT5616_HP_VOL,
RT5616_L_VOL_SFT, RT5616_R_VOL_SFT, 39, 1, out_vol_tlv),
/* OUTPUT Control */
SOC_DOUBLE("OUT Playback Switch", RT5616_LOUT_CTRL1,
RT5616_L_MUTE_SFT, RT5616_R_MUTE_SFT, 1, 1),
SOC_DOUBLE("OUT Channel Switch", RT5616_LOUT_CTRL1,
RT5616_VOL_L_SFT, RT5616_VOL_R_SFT, 1, 1),
SOC_DOUBLE_TLV("OUT Playback Volume", RT5616_LOUT_CTRL1,
RT5616_L_VOL_SFT, RT5616_R_VOL_SFT, 39, 1, out_vol_tlv),
/* DAC Digital Volume */
SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5616_DAC1_DIG_VOL,
RT5616_L_VOL_SFT, RT5616_R_VOL_SFT,
175, 0, dac_vol_tlv),
/* IN1/IN2 Control */
SOC_SINGLE_TLV("IN1 Boost Volume", RT5616_IN1_IN2,
RT5616_BST_SFT1, 8, 0, bst_tlv),
SOC_SINGLE_TLV("IN2 Boost Volume", RT5616_IN1_IN2,
RT5616_BST_SFT2, 8, 0, bst_tlv),
/* INL/INR Volume Control */
SOC_DOUBLE_TLV("IN Capture Volume", RT5616_INL1_INR1_VOL,
RT5616_INL_VOL_SFT, RT5616_INR_VOL_SFT,
31, 1, in_vol_tlv),
/* ADC Digital Volume Control */
SOC_DOUBLE("ADC Capture Switch", RT5616_ADC_DIG_VOL,
RT5616_L_MUTE_SFT, RT5616_R_MUTE_SFT, 1, 1),
SOC_DOUBLE_TLV("ADC Capture Volume", RT5616_ADC_DIG_VOL,
RT5616_L_VOL_SFT, RT5616_R_VOL_SFT,
127, 0, adc_vol_tlv),
/* ADC Boost Volume Control */
SOC_DOUBLE_TLV("ADC Boost Volume", RT5616_ADC_BST_VOL,
RT5616_ADC_L_BST_SFT, RT5616_ADC_R_BST_SFT,
3, 0, adc_bst_tlv),
};
static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
unsigned int val;
val = snd_soc_component_read(snd_soc_dapm_to_component(source->dapm), RT5616_GLB_CLK);
val &= RT5616_SCLK_SRC_MASK;
if (val == RT5616_SCLK_SRC_PLL1)
return 1;
else
return 0;
}
/* Digital Mixer */
static const struct snd_kcontrol_new rt5616_sto1_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5616_STO1_ADC_MIXER,
RT5616_M_STO1_ADC_L1_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5616_sto1_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5616_STO1_ADC_MIXER,
RT5616_M_STO1_ADC_R1_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5616_dac_l_mix[] = {
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5616_AD_DA_MIXER,
RT5616_M_ADCMIX_L_SFT, 1, 1),
SOC_DAPM_SINGLE("INF1 Switch", RT5616_AD_DA_MIXER,
RT5616_M_IF1_DAC_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5616_dac_r_mix[] = {
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5616_AD_DA_MIXER,
RT5616_M_ADCMIX_R_SFT, 1, 1),
SOC_DAPM_SINGLE("INF1 Switch", RT5616_AD_DA_MIXER,
RT5616_M_IF1_DAC_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5616_sto_dac_l_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5616_STO_DAC_MIXER,
RT5616_M_DAC_L1_MIXL_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5616_STO_DAC_MIXER,
RT5616_M_DAC_R1_MIXL_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5616_sto_dac_r_mix[] = {
SOC_DAPM_SINGLE("DAC R1 Switch", RT5616_STO_DAC_MIXER,
RT5616_M_DAC_R1_MIXR_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L1 Switch", RT5616_STO_DAC_MIXER,
RT5616_M_DAC_L1_MIXR_SFT, 1, 1),
};
/* Analog Input Mixer */
static const struct snd_kcontrol_new rt5616_rec_l_mix[] = {
SOC_DAPM_SINGLE("INL1 Switch", RT5616_REC_L2_MIXER,
RT5616_M_IN1_L_RM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5616_REC_L2_MIXER,
RT5616_M_BST2_RM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5616_REC_L2_MIXER,
RT5616_M_BST1_RM_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5616_rec_r_mix[] = {
SOC_DAPM_SINGLE("INR1 Switch", RT5616_REC_R2_MIXER,
RT5616_M_IN1_R_RM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5616_REC_R2_MIXER,
RT5616_M_BST2_RM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5616_REC_R2_MIXER,
RT5616_M_BST1_RM_R_SFT, 1, 1),
};
/* Analog Output Mixer */
static const struct snd_kcontrol_new rt5616_out_l_mix[] = {
SOC_DAPM_SINGLE("BST1 Switch", RT5616_OUT_L3_MIXER,
RT5616_M_BST1_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5616_OUT_L3_MIXER,
RT5616_M_BST2_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("INL1 Switch", RT5616_OUT_L3_MIXER,
RT5616_M_IN1_L_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("REC MIXL Switch", RT5616_OUT_L3_MIXER,
RT5616_M_RM_L_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L1 Switch", RT5616_OUT_L3_MIXER,
RT5616_M_DAC_L1_OM_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5616_out_r_mix[] = {
SOC_DAPM_SINGLE("BST2 Switch", RT5616_OUT_R3_MIXER,
RT5616_M_BST2_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5616_OUT_R3_MIXER,
RT5616_M_BST1_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("INR1 Switch", RT5616_OUT_R3_MIXER,
RT5616_M_IN1_R_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("REC MIXR Switch", RT5616_OUT_R3_MIXER,
RT5616_M_RM_R_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5616_OUT_R3_MIXER,
RT5616_M_DAC_R1_OM_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5616_hpo_mix[] = {
SOC_DAPM_SINGLE("DAC1 Switch", RT5616_HPO_MIXER,
RT5616_M_DAC1_HM_SFT, 1, 1),
SOC_DAPM_SINGLE("HPVOL Switch", RT5616_HPO_MIXER,
RT5616_M_HPVOL_HM_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5616_lout_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5616_LOUT_MIXER,
RT5616_M_DAC_L1_LM_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5616_LOUT_MIXER,
RT5616_M_DAC_R1_LM_SFT, 1, 1),
SOC_DAPM_SINGLE("OUTVOL L Switch", RT5616_LOUT_MIXER,
RT5616_M_OV_L_LM_SFT, 1, 1),
SOC_DAPM_SINGLE("OUTVOL R Switch", RT5616_LOUT_MIXER,
RT5616_M_OV_R_LM_SFT, 1, 1),
};
static int rt5616_adc_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(component, RT5616_ADC_DIG_VOL,
RT5616_L_MUTE | RT5616_R_MUTE, 0);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component, RT5616_ADC_DIG_VOL,
RT5616_L_MUTE | RT5616_R_MUTE,
RT5616_L_MUTE | RT5616_R_MUTE);
break;
default:
return 0;
}
return 0;
}
static int rt5616_charge_pump_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
/* depop parameters */
snd_soc_component_update_bits(component, RT5616_DEPOP_M2,
RT5616_DEPOP_MASK, RT5616_DEPOP_MAN);
snd_soc_component_update_bits(component, RT5616_DEPOP_M1,
RT5616_HP_CP_MASK | RT5616_HP_SG_MASK |
RT5616_HP_CB_MASK, RT5616_HP_CP_PU |
RT5616_HP_SG_DIS | RT5616_HP_CB_PU);
snd_soc_component_write(component, RT5616_PR_BASE +
RT5616_HP_DCC_INT1, 0x9f00);
/* headphone amp power on */
snd_soc_component_update_bits(component, RT5616_PWR_ANLG1,
RT5616_PWR_FV1 | RT5616_PWR_FV2, 0);
snd_soc_component_update_bits(component, RT5616_PWR_VOL,
RT5616_PWR_HV_L | RT5616_PWR_HV_R,
RT5616_PWR_HV_L | RT5616_PWR_HV_R);
snd_soc_component_update_bits(component, RT5616_PWR_ANLG1,
RT5616_PWR_HP_L | RT5616_PWR_HP_R |
RT5616_PWR_HA, RT5616_PWR_HP_L |
RT5616_PWR_HP_R | RT5616_PWR_HA);
msleep(50);
snd_soc_component_update_bits(component, RT5616_PWR_ANLG1,
RT5616_PWR_FV1 | RT5616_PWR_FV2,
RT5616_PWR_FV1 | RT5616_PWR_FV2);
snd_soc_component_update_bits(component, RT5616_CHARGE_PUMP,
RT5616_PM_HP_MASK, RT5616_PM_HP_HV);
snd_soc_component_update_bits(component, RT5616_PR_BASE +
RT5616_CHOP_DAC_ADC, 0x0200, 0x0200);
snd_soc_component_update_bits(component, RT5616_DEPOP_M1,
RT5616_HP_CO_MASK | RT5616_HP_SG_MASK,
RT5616_HP_CO_EN | RT5616_HP_SG_EN);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, RT5616_PR_BASE +
RT5616_CHOP_DAC_ADC, 0x0200, 0x0);
snd_soc_component_update_bits(component, RT5616_DEPOP_M1,
RT5616_HP_SG_MASK | RT5616_HP_L_SMT_MASK |
RT5616_HP_R_SMT_MASK, RT5616_HP_SG_DIS |
RT5616_HP_L_SMT_DIS | RT5616_HP_R_SMT_DIS);
/* headphone amp power down */
snd_soc_component_update_bits(component, RT5616_DEPOP_M1,
RT5616_SMT_TRIG_MASK |
RT5616_HP_CD_PD_MASK | RT5616_HP_CO_MASK |
RT5616_HP_CP_MASK | RT5616_HP_SG_MASK |
RT5616_HP_CB_MASK,
RT5616_SMT_TRIG_DIS | RT5616_HP_CD_PD_EN |
RT5616_HP_CO_DIS | RT5616_HP_CP_PD |
RT5616_HP_SG_EN | RT5616_HP_CB_PD);
snd_soc_component_update_bits(component, RT5616_PWR_ANLG1,
RT5616_PWR_HP_L | RT5616_PWR_HP_R |
RT5616_PWR_HA, 0);
break;
default:
return 0;
}
return 0;
}
static int rt5616_hp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
/* headphone unmute sequence */
snd_soc_component_update_bits(component, RT5616_DEPOP_M3,
RT5616_CP_FQ1_MASK | RT5616_CP_FQ2_MASK |
RT5616_CP_FQ3_MASK,
RT5616_CP_FQ_192_KHZ << RT5616_CP_FQ1_SFT |
RT5616_CP_FQ_12_KHZ << RT5616_CP_FQ2_SFT |
RT5616_CP_FQ_192_KHZ << RT5616_CP_FQ3_SFT);
snd_soc_component_write(component, RT5616_PR_BASE +
RT5616_MAMP_INT_REG2, 0xfc00);
snd_soc_component_update_bits(component, RT5616_DEPOP_M1,
RT5616_SMT_TRIG_MASK, RT5616_SMT_TRIG_EN);
snd_soc_component_update_bits(component, RT5616_DEPOP_M1,
RT5616_RSTN_MASK, RT5616_RSTN_EN);
snd_soc_component_update_bits(component, RT5616_DEPOP_M1,
RT5616_RSTN_MASK | RT5616_HP_L_SMT_MASK |
RT5616_HP_R_SMT_MASK, RT5616_RSTN_DIS |
RT5616_HP_L_SMT_EN | RT5616_HP_R_SMT_EN);
snd_soc_component_update_bits(component, RT5616_HP_VOL,
RT5616_L_MUTE | RT5616_R_MUTE, 0);
msleep(100);
snd_soc_component_update_bits(component, RT5616_DEPOP_M1,
RT5616_HP_SG_MASK | RT5616_HP_L_SMT_MASK |
RT5616_HP_R_SMT_MASK, RT5616_HP_SG_DIS |
RT5616_HP_L_SMT_DIS | RT5616_HP_R_SMT_DIS);
msleep(20);
snd_soc_component_update_bits(component, RT5616_HP_CALIB_AMP_DET,
RT5616_HPD_PS_MASK, RT5616_HPD_PS_EN);
break;
case SND_SOC_DAPM_PRE_PMD:
/* headphone mute sequence */
snd_soc_component_update_bits(component, RT5616_DEPOP_M3,
RT5616_CP_FQ1_MASK | RT5616_CP_FQ2_MASK |
RT5616_CP_FQ3_MASK,
RT5616_CP_FQ_96_KHZ << RT5616_CP_FQ1_SFT |
RT5616_CP_FQ_12_KHZ << RT5616_CP_FQ2_SFT |
RT5616_CP_FQ_96_KHZ << RT5616_CP_FQ3_SFT);
snd_soc_component_write(component, RT5616_PR_BASE +
RT5616_MAMP_INT_REG2, 0xfc00);
snd_soc_component_update_bits(component, RT5616_DEPOP_M1,
RT5616_HP_SG_MASK, RT5616_HP_SG_EN);
snd_soc_component_update_bits(component, RT5616_DEPOP_M1,
RT5616_RSTP_MASK, RT5616_RSTP_EN);
snd_soc_component_update_bits(component, RT5616_DEPOP_M1,
RT5616_RSTP_MASK | RT5616_HP_L_SMT_MASK |
RT5616_HP_R_SMT_MASK, RT5616_RSTP_DIS |
RT5616_HP_L_SMT_EN | RT5616_HP_R_SMT_EN);
snd_soc_component_update_bits(component, RT5616_HP_CALIB_AMP_DET,
RT5616_HPD_PS_MASK, RT5616_HPD_PS_DIS);
msleep(90);
snd_soc_component_update_bits(component, RT5616_HP_VOL,
RT5616_L_MUTE | RT5616_R_MUTE,
RT5616_L_MUTE | RT5616_R_MUTE);
msleep(30);
break;
default:
return 0;
}
return 0;
}
static int rt5616_lout_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(component, RT5616_PWR_ANLG1,
RT5616_PWR_LM, RT5616_PWR_LM);
snd_soc_component_update_bits(component, RT5616_LOUT_CTRL1,
RT5616_L_MUTE | RT5616_R_MUTE, 0);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, RT5616_LOUT_CTRL1,
RT5616_L_MUTE | RT5616_R_MUTE,
RT5616_L_MUTE | RT5616_R_MUTE);
snd_soc_component_update_bits(component, RT5616_PWR_ANLG1,
RT5616_PWR_LM, 0);
break;
default:
return 0;
}
return 0;
}
static int rt5616_bst1_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(component, RT5616_PWR_ANLG2,
RT5616_PWR_BST1_OP2, RT5616_PWR_BST1_OP2);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, RT5616_PWR_ANLG2,
RT5616_PWR_BST1_OP2, 0);
break;
default:
return 0;
}
return 0;
}
static int rt5616_bst2_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(component, RT5616_PWR_ANLG2,
RT5616_PWR_BST2_OP2, RT5616_PWR_BST2_OP2);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, RT5616_PWR_ANLG2,
RT5616_PWR_BST2_OP2, 0);
break;
default:
return 0;
}
return 0;
}
static const struct snd_soc_dapm_widget rt5616_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("PLL1", RT5616_PWR_ANLG2,
RT5616_PWR_PLL_BIT, 0, NULL, 0),
/* Input Side */
/* micbias */
SND_SOC_DAPM_SUPPLY("LDO", RT5616_PWR_ANLG1,
RT5616_PWR_LDO_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("micbias1", RT5616_PWR_ANLG2,
RT5616_PWR_MB1_BIT, 0, NULL, 0),
/* Input Lines */
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_INPUT("MIC2"),
SND_SOC_DAPM_INPUT("IN1P"),
SND_SOC_DAPM_INPUT("IN2P"),
SND_SOC_DAPM_INPUT("IN2N"),
/* Boost */
SND_SOC_DAPM_PGA_E("BST1", RT5616_PWR_ANLG2,
RT5616_PWR_BST1_BIT, 0, NULL, 0, rt5616_bst1_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("BST2", RT5616_PWR_ANLG2,
RT5616_PWR_BST2_BIT, 0, NULL, 0, rt5616_bst2_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
/* Input Volume */
SND_SOC_DAPM_PGA("INL1 VOL", RT5616_PWR_VOL,
RT5616_PWR_IN1_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("INR1 VOL", RT5616_PWR_VOL,
RT5616_PWR_IN1_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("INL2 VOL", RT5616_PWR_VOL,
RT5616_PWR_IN2_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("INR2 VOL", RT5616_PWR_VOL,
RT5616_PWR_IN2_R_BIT, 0, NULL, 0),
/* REC Mixer */
SND_SOC_DAPM_MIXER("RECMIXL", RT5616_PWR_MIXER, RT5616_PWR_RM_L_BIT, 0,
rt5616_rec_l_mix, ARRAY_SIZE(rt5616_rec_l_mix)),
SND_SOC_DAPM_MIXER("RECMIXR", RT5616_PWR_MIXER, RT5616_PWR_RM_R_BIT, 0,
rt5616_rec_r_mix, ARRAY_SIZE(rt5616_rec_r_mix)),
/* ADCs */
SND_SOC_DAPM_ADC_E("ADC L", NULL, RT5616_PWR_DIG1,
RT5616_PWR_ADC_L_BIT, 0, rt5616_adc_event,
SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_ADC_E("ADC R", NULL, RT5616_PWR_DIG1,
RT5616_PWR_ADC_R_BIT, 0, rt5616_adc_event,
SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
/* ADC Mixer */
SND_SOC_DAPM_SUPPLY("stereo1 filter", RT5616_PWR_DIG2,
RT5616_PWR_ADC_STO1_F_BIT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0,
rt5616_sto1_adc_l_mix,
ARRAY_SIZE(rt5616_sto1_adc_l_mix)),
SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0,
rt5616_sto1_adc_r_mix,
ARRAY_SIZE(rt5616_sto1_adc_r_mix)),
/* Digital Interface */
SND_SOC_DAPM_SUPPLY("I2S1", RT5616_PWR_DIG1,
RT5616_PWR_I2S1_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
/* Digital Interface Select */
/* Audio Interface */
SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
/* Audio DSP */
SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
/* Output Side */
/* DAC mixer before sound effect */
SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
rt5616_dac_l_mix, ARRAY_SIZE(rt5616_dac_l_mix)),
SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
rt5616_dac_r_mix, ARRAY_SIZE(rt5616_dac_r_mix)),
SND_SOC_DAPM_SUPPLY("Stero1 DAC Power", RT5616_PWR_DIG2,
RT5616_PWR_DAC_STO1_F_BIT, 0, NULL, 0),
/* DAC Mixer */
SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
rt5616_sto_dac_l_mix,
ARRAY_SIZE(rt5616_sto_dac_l_mix)),
SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
rt5616_sto_dac_r_mix,
ARRAY_SIZE(rt5616_sto_dac_r_mix)),
/* DACs */
SND_SOC_DAPM_DAC("DAC L1", NULL, RT5616_PWR_DIG1,
RT5616_PWR_DAC_L1_BIT, 0),
SND_SOC_DAPM_DAC("DAC R1", NULL, RT5616_PWR_DIG1,
RT5616_PWR_DAC_R1_BIT, 0),
/* OUT Mixer */
SND_SOC_DAPM_MIXER("OUT MIXL", RT5616_PWR_MIXER, RT5616_PWR_OM_L_BIT,
0, rt5616_out_l_mix, ARRAY_SIZE(rt5616_out_l_mix)),
SND_SOC_DAPM_MIXER("OUT MIXR", RT5616_PWR_MIXER, RT5616_PWR_OM_R_BIT,
0, rt5616_out_r_mix, ARRAY_SIZE(rt5616_out_r_mix)),
/* Output Volume */
SND_SOC_DAPM_PGA("OUTVOL L", RT5616_PWR_VOL,
RT5616_PWR_OV_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("OUTVOL R", RT5616_PWR_VOL,
RT5616_PWR_OV_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("HPOVOL L", RT5616_PWR_VOL,
RT5616_PWR_HV_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("HPOVOL R", RT5616_PWR_VOL,
RT5616_PWR_HV_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM,
0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM,
0, 0, NULL, 0),
SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM,
0, 0, NULL, 0),
SND_SOC_DAPM_PGA("INL1", RT5616_PWR_VOL,
RT5616_PWR_IN1_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("INR1", RT5616_PWR_VOL,
RT5616_PWR_IN1_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("INL2", RT5616_PWR_VOL,
RT5616_PWR_IN2_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("INR2", RT5616_PWR_VOL,
RT5616_PWR_IN2_R_BIT, 0, NULL, 0),
/* HPO/LOUT/Mono Mixer */
SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0,
rt5616_hpo_mix, ARRAY_SIZE(rt5616_hpo_mix)),
SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0,
rt5616_lout_mix, ARRAY_SIZE(rt5616_lout_mix)),
SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0,
rt5616_hp_event, SND_SOC_DAPM_PRE_PMD |
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0,
rt5616_lout_event, SND_SOC_DAPM_PRE_PMD |
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, SND_SOC_NOPM, 0, 0,
rt5616_charge_pump_event, SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD),
/* Output Lines */
SND_SOC_DAPM_OUTPUT("HPOL"),
SND_SOC_DAPM_OUTPUT("HPOR"),
SND_SOC_DAPM_OUTPUT("LOUTL"),
SND_SOC_DAPM_OUTPUT("LOUTR"),
};
static const struct snd_soc_dapm_route rt5616_dapm_routes[] = {
{"IN1P", NULL, "LDO"},
{"IN2P", NULL, "LDO"},
{"IN1P", NULL, "MIC1"},
{"IN2P", NULL, "MIC2"},
{"IN2N", NULL, "MIC2"},
{"BST1", NULL, "IN1P"},
{"BST2", NULL, "IN2P"},
{"BST2", NULL, "IN2N"},
{"BST1", NULL, "micbias1"},
{"BST2", NULL, "micbias1"},
{"INL1 VOL", NULL, "IN2P"},
{"INR1 VOL", NULL, "IN2N"},
{"RECMIXL", "INL1 Switch", "INL1 VOL"},
{"RECMIXL", "BST2 Switch", "BST2"},
{"RECMIXL", "BST1 Switch", "BST1"},
{"RECMIXR", "INR1 Switch", "INR1 VOL"},
{"RECMIXR", "BST2 Switch", "BST2"},
{"RECMIXR", "BST1 Switch", "BST1"},
{"ADC L", NULL, "RECMIXL"},
{"ADC R", NULL, "RECMIXR"},
{"Stereo1 ADC MIXL", "ADC1 Switch", "ADC L"},
{"Stereo1 ADC MIXL", NULL, "stereo1 filter"},
{"stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll},
{"Stereo1 ADC MIXR", "ADC1 Switch", "ADC R"},
{"Stereo1 ADC MIXR", NULL, "stereo1 filter"},
{"stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll},
{"IF1 ADC1", NULL, "Stereo1 ADC MIXL"},
{"IF1 ADC1", NULL, "Stereo1 ADC MIXR"},
{"IF1 ADC1", NULL, "I2S1"},
{"AIF1TX", NULL, "IF1 ADC1"},
{"IF1 DAC", NULL, "AIF1RX"},
{"IF1 DAC", NULL, "I2S1"},
{"IF1 DAC1 L", NULL, "IF1 DAC"},
{"IF1 DAC1 R", NULL, "IF1 DAC"},
{"DAC MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
{"DAC MIXL", "INF1 Switch", "IF1 DAC1 L"},
{"DAC MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
{"DAC MIXR", "INF1 Switch", "IF1 DAC1 R"},
{"Audio DSP", NULL, "DAC MIXL"},
{"Audio DSP", NULL, "DAC MIXR"},
{"Stereo DAC MIXL", "DAC L1 Switch", "Audio DSP"},
{"Stereo DAC MIXL", "DAC R1 Switch", "DAC MIXR"},
{"Stereo DAC MIXL", NULL, "Stero1 DAC Power"},
{"Stereo DAC MIXR", "DAC R1 Switch", "Audio DSP"},
{"Stereo DAC MIXR", "DAC L1 Switch", "DAC MIXL"},
{"Stereo DAC MIXR", NULL, "Stero1 DAC Power"},
{"DAC L1", NULL, "Stereo DAC MIXL"},
{"DAC L1", NULL, "PLL1", is_sys_clk_from_pll},
{"DAC R1", NULL, "Stereo DAC MIXR"},
{"DAC R1", NULL, "PLL1", is_sys_clk_from_pll},
{"OUT MIXL", "BST1 Switch", "BST1"},
{"OUT MIXL", "BST2 Switch", "BST2"},
{"OUT MIXL", "INL1 Switch", "INL1 VOL"},
{"OUT MIXL", "REC MIXL Switch", "RECMIXL"},
{"OUT MIXL", "DAC L1 Switch", "DAC L1"},
{"OUT MIXR", "BST2 Switch", "BST2"},
{"OUT MIXR", "BST1 Switch", "BST1"},
{"OUT MIXR", "INR1 Switch", "INR1 VOL"},
{"OUT MIXR", "REC MIXR Switch", "RECMIXR"},
{"OUT MIXR", "DAC R1 Switch", "DAC R1"},
{"HPOVOL L", NULL, "OUT MIXL"},
{"HPOVOL R", NULL, "OUT MIXR"},
{"OUTVOL L", NULL, "OUT MIXL"},
{"OUTVOL R", NULL, "OUT MIXR"},
{"DAC 1", NULL, "DAC L1"},
{"DAC 1", NULL, "DAC R1"},
{"HPOVOL", NULL, "HPOVOL L"},
{"HPOVOL", NULL, "HPOVOL R"},
{"HPO MIX", "DAC1 Switch", "DAC 1"},
{"HPO MIX", "HPVOL Switch", "HPOVOL"},
{"LOUT MIX", "DAC L1 Switch", "DAC L1"},
{"LOUT MIX", "DAC R1 Switch", "DAC R1"},
{"LOUT MIX", "OUTVOL L Switch", "OUTVOL L"},
{"LOUT MIX", "OUTVOL R Switch", "OUTVOL R"},
{"HP amp", NULL, "HPO MIX"},
{"HP amp", NULL, "Charge Pump"},
{"HPOL", NULL, "HP amp"},
{"HPOR", NULL, "HP amp"},
{"LOUT amp", NULL, "LOUT MIX"},
{"LOUT amp", NULL, "Charge Pump"},
{"LOUTL", NULL, "LOUT amp"},
{"LOUTR", NULL, "LOUT amp"},
};
static int rt5616_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt5616_priv *rt5616 = snd_soc_component_get_drvdata(component);
unsigned int val_len = 0, val_clk, mask_clk;
int pre_div, bclk_ms, frame_size;
rt5616->lrck[dai->id] = params_rate(params);
pre_div = rl6231_get_clk_info(rt5616->sysclk, rt5616->lrck[dai->id]);
if (pre_div < 0) {
dev_err(component->dev, "Unsupported clock setting\n");
return -EINVAL;
}
frame_size = snd_soc_params_to_frame_size(params);
if (frame_size < 0) {
dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
return -EINVAL;
}
bclk_ms = frame_size > 32 ? 1 : 0;
rt5616->bclk[dai->id] = rt5616->lrck[dai->id] * (32 << bclk_ms);
dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
rt5616->bclk[dai->id], rt5616->lrck[dai->id]);
dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
bclk_ms, pre_div, dai->id);
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
break;
case SNDRV_PCM_FORMAT_S20_3LE:
val_len |= RT5616_I2S_DL_20;
break;
case SNDRV_PCM_FORMAT_S24_LE:
val_len |= RT5616_I2S_DL_24;
break;
case SNDRV_PCM_FORMAT_S8:
val_len |= RT5616_I2S_DL_8;
break;
default:
return -EINVAL;
}
mask_clk = RT5616_I2S_PD1_MASK;
val_clk = pre_div << RT5616_I2S_PD1_SFT;
snd_soc_component_update_bits(component, RT5616_I2S1_SDP,
RT5616_I2S_DL_MASK, val_len);
snd_soc_component_update_bits(component, RT5616_ADDA_CLK1, mask_clk, val_clk);
return 0;
}
static int rt5616_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct rt5616_priv *rt5616 = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
rt5616->master[dai->id] = 1;
break;
case SND_SOC_DAIFMT_CBS_CFS:
reg_val |= RT5616_I2S_MS_S;
rt5616->master[dai->id] = 0;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
reg_val |= RT5616_I2S_BP_INV;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_LEFT_J:
reg_val |= RT5616_I2S_DF_LEFT;
break;
case SND_SOC_DAIFMT_DSP_A:
reg_val |= RT5616_I2S_DF_PCM_A;
break;
case SND_SOC_DAIFMT_DSP_B:
reg_val |= RT5616_I2S_DF_PCM_B;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, RT5616_I2S1_SDP,
RT5616_I2S_MS_MASK | RT5616_I2S_BP_MASK |
RT5616_I2S_DF_MASK, reg_val);
return 0;
}
static int rt5616_set_dai_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct rt5616_priv *rt5616 = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0;
if (freq == rt5616->sysclk && clk_id == rt5616->sysclk_src)
return 0;
switch (clk_id) {
case RT5616_SCLK_S_MCLK:
reg_val |= RT5616_SCLK_SRC_MCLK;
break;
case RT5616_SCLK_S_PLL1:
reg_val |= RT5616_SCLK_SRC_PLL1;
break;
default:
dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
return -EINVAL;
}
snd_soc_component_update_bits(component, RT5616_GLB_CLK,
RT5616_SCLK_SRC_MASK, reg_val);
rt5616->sysclk = freq;
rt5616->sysclk_src = clk_id;
dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
return 0;
}
static int rt5616_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
unsigned int freq_in, unsigned int freq_out)
{
struct snd_soc_component *component = dai->component;
struct rt5616_priv *rt5616 = snd_soc_component_get_drvdata(component);
struct rl6231_pll_code pll_code;
int ret;
if (source == rt5616->pll_src && freq_in == rt5616->pll_in &&
freq_out == rt5616->pll_out)
return 0;
if (!freq_in || !freq_out) {
dev_dbg(component->dev, "PLL disabled\n");
rt5616->pll_in = 0;
rt5616->pll_out = 0;
snd_soc_component_update_bits(component, RT5616_GLB_CLK,
RT5616_SCLK_SRC_MASK,
RT5616_SCLK_SRC_MCLK);
return 0;
}
switch (source) {
case RT5616_PLL1_S_MCLK:
snd_soc_component_update_bits(component, RT5616_GLB_CLK,
RT5616_PLL1_SRC_MASK,
RT5616_PLL1_SRC_MCLK);
break;
case RT5616_PLL1_S_BCLK1:
case RT5616_PLL1_S_BCLK2:
snd_soc_component_update_bits(component, RT5616_GLB_CLK,
RT5616_PLL1_SRC_MASK,
RT5616_PLL1_SRC_BCLK1);
break;
default:
dev_err(component->dev, "Unknown PLL source %d\n", source);
return -EINVAL;
}
ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
if (ret < 0) {
dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
return ret;
}
dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
pll_code.n_code, pll_code.k_code);
snd_soc_component_write(component, RT5616_PLL_CTRL1,
pll_code.n_code << RT5616_PLL_N_SFT | pll_code.k_code);
snd_soc_component_write(component, RT5616_PLL_CTRL2,
(pll_code.m_bp ? 0 : pll_code.m_code) <<
RT5616_PLL_M_SFT |
pll_code.m_bp << RT5616_PLL_M_BP_SFT);
rt5616->pll_in = freq_in;
rt5616->pll_out = freq_out;
rt5616->pll_src = source;
return 0;
}
static int rt5616_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct rt5616_priv *rt5616 = snd_soc_component_get_drvdata(component);
int ret;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
/*
* SND_SOC_BIAS_PREPARE is called while preparing for a
* transition to ON or away from ON. If current bias_level
* is SND_SOC_BIAS_ON, then it is preparing for a transition
* away from ON. Disable the clock in that case, otherwise
* enable it.
*/
if (IS_ERR(rt5616->mclk))
break;
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) {
clk_disable_unprepare(rt5616->mclk);
} else {
ret = clk_prepare_enable(rt5616->mclk);
if (ret)
return ret;
}
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
snd_soc_component_update_bits(component, RT5616_PWR_ANLG1,
RT5616_PWR_VREF1 | RT5616_PWR_MB |
RT5616_PWR_BG | RT5616_PWR_VREF2,
RT5616_PWR_VREF1 | RT5616_PWR_MB |
RT5616_PWR_BG | RT5616_PWR_VREF2);
mdelay(10);
snd_soc_component_update_bits(component, RT5616_PWR_ANLG1,
RT5616_PWR_FV1 | RT5616_PWR_FV2,
RT5616_PWR_FV1 | RT5616_PWR_FV2);
snd_soc_component_update_bits(component, RT5616_D_MISC,
RT5616_D_GATE_EN,
RT5616_D_GATE_EN);
}
break;
case SND_SOC_BIAS_OFF:
snd_soc_component_update_bits(component, RT5616_D_MISC, RT5616_D_GATE_EN, 0);
snd_soc_component_write(component, RT5616_PWR_DIG1, 0x0000);
snd_soc_component_write(component, RT5616_PWR_DIG2, 0x0000);
snd_soc_component_write(component, RT5616_PWR_VOL, 0x0000);
snd_soc_component_write(component, RT5616_PWR_MIXER, 0x0000);
snd_soc_component_write(component, RT5616_PWR_ANLG1, 0x0000);
snd_soc_component_write(component, RT5616_PWR_ANLG2, 0x0000);
break;
default:
break;
}
return 0;
}
static int rt5616_probe(struct snd_soc_component *component)
{
struct rt5616_priv *rt5616 = snd_soc_component_get_drvdata(component);
/* Check if MCLK provided */
rt5616->mclk = devm_clk_get(component->dev, "mclk");
if (PTR_ERR(rt5616->mclk) == -EPROBE_DEFER)
return -EPROBE_DEFER;
rt5616->component = component;
return 0;
}
#ifdef CONFIG_PM
static int rt5616_suspend(struct snd_soc_component *component)
{
struct rt5616_priv *rt5616 = snd_soc_component_get_drvdata(component);
regcache_cache_only(rt5616->regmap, true);
regcache_mark_dirty(rt5616->regmap);
return 0;
}
static int rt5616_resume(struct snd_soc_component *component)
{
struct rt5616_priv *rt5616 = snd_soc_component_get_drvdata(component);
regcache_cache_only(rt5616->regmap, false);
regcache_sync(rt5616->regmap);
return 0;
}
#else
#define rt5616_suspend NULL
#define rt5616_resume NULL
#endif
#define RT5616_STEREO_RATES SNDRV_PCM_RATE_8000_192000
#define RT5616_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
static const struct snd_soc_dai_ops rt5616_aif_dai_ops = {
.hw_params = rt5616_hw_params,
.set_fmt = rt5616_set_dai_fmt,
.set_sysclk = rt5616_set_dai_sysclk,
.set_pll = rt5616_set_dai_pll,
};
static struct snd_soc_dai_driver rt5616_dai[] = {
{
.name = "rt5616-aif1",
.id = RT5616_AIF1,
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT5616_STEREO_RATES,
.formats = RT5616_FORMATS,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT5616_STEREO_RATES,
.formats = RT5616_FORMATS,
},
.ops = &rt5616_aif_dai_ops,
},
};
static const struct snd_soc_component_driver soc_component_dev_rt5616 = {
.probe = rt5616_probe,
.suspend = rt5616_suspend,
.resume = rt5616_resume,
.set_bias_level = rt5616_set_bias_level,
.controls = rt5616_snd_controls,
.num_controls = ARRAY_SIZE(rt5616_snd_controls),
.dapm_widgets = rt5616_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt5616_dapm_widgets),
.dapm_routes = rt5616_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(rt5616_dapm_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config rt5616_regmap = {
.reg_bits = 8,
.val_bits = 16,
.use_single_read = true,
.use_single_write = true,
.max_register = RT5616_DEVICE_ID + 1 + (ARRAY_SIZE(rt5616_ranges) *
RT5616_PR_SPACING),
.volatile_reg = rt5616_volatile_register,
.readable_reg = rt5616_readable_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = rt5616_reg,
.num_reg_defaults = ARRAY_SIZE(rt5616_reg),
.ranges = rt5616_ranges,
.num_ranges = ARRAY_SIZE(rt5616_ranges),
};
static const struct i2c_device_id rt5616_i2c_id[] = {
{ "rt5616", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, rt5616_i2c_id);
#if defined(CONFIG_OF)
static const struct of_device_id rt5616_of_match[] = {
{ .compatible = "realtek,rt5616", },
{},
};
MODULE_DEVICE_TABLE(of, rt5616_of_match);
#endif
static int rt5616_i2c_probe(struct i2c_client *i2c)
{
struct rt5616_priv *rt5616;
unsigned int val;
int ret;
rt5616 = devm_kzalloc(&i2c->dev, sizeof(struct rt5616_priv),
GFP_KERNEL);
if (!rt5616)
return -ENOMEM;
i2c_set_clientdata(i2c, rt5616);
rt5616->regmap = devm_regmap_init_i2c(i2c, &rt5616_regmap);
if (IS_ERR(rt5616->regmap)) {
ret = PTR_ERR(rt5616->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
regmap_read(rt5616->regmap, RT5616_DEVICE_ID, &val);
if (val != 0x6281) {
dev_err(&i2c->dev,
"Device with ID register %#x is not rt5616\n",
val);
return -ENODEV;
}
regmap_write(rt5616->regmap, RT5616_RESET, 0);
regmap_update_bits(rt5616->regmap, RT5616_PWR_ANLG1,
RT5616_PWR_VREF1 | RT5616_PWR_MB |
RT5616_PWR_BG | RT5616_PWR_VREF2,
RT5616_PWR_VREF1 | RT5616_PWR_MB |
RT5616_PWR_BG | RT5616_PWR_VREF2);
mdelay(10);
regmap_update_bits(rt5616->regmap, RT5616_PWR_ANLG1,
RT5616_PWR_FV1 | RT5616_PWR_FV2,
RT5616_PWR_FV1 | RT5616_PWR_FV2);
ret = regmap_register_patch(rt5616->regmap, init_list,
ARRAY_SIZE(init_list));
if (ret != 0)
dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
regmap_update_bits(rt5616->regmap, RT5616_PWR_ANLG1,
RT5616_PWR_LDO_DVO_MASK, RT5616_PWR_LDO_DVO_1_2V);
return devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_rt5616,
rt5616_dai, ARRAY_SIZE(rt5616_dai));
}
static void rt5616_i2c_remove(struct i2c_client *i2c)
{}
static void rt5616_i2c_shutdown(struct i2c_client *client)
{
struct rt5616_priv *rt5616 = i2c_get_clientdata(client);
regmap_write(rt5616->regmap, RT5616_HP_VOL, 0xc8c8);
regmap_write(rt5616->regmap, RT5616_LOUT_CTRL1, 0xc8c8);
}
static struct i2c_driver rt5616_i2c_driver = {
.driver = {
.name = "rt5616",
.of_match_table = of_match_ptr(rt5616_of_match),
},
.probe = rt5616_i2c_probe,
.remove = rt5616_i2c_remove,
.shutdown = rt5616_i2c_shutdown,
.id_table = rt5616_i2c_id,
};
module_i2c_driver(rt5616_i2c_driver);
MODULE_DESCRIPTION("ASoC RT5616 driver");
MODULE_AUTHOR("Bard Liao <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/rt5616.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ALSA SoC TWL4030 codec driver
*
* Author: Steve Sakoman, <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/mfd/twl.h>
#include <linux/slab.h>
#include <linux/gpio.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
/* Register descriptions are here */
#include <linux/mfd/twl4030-audio.h>
/* TWL4030 PMBR1 Register */
#define TWL4030_PMBR1_REG 0x0D
/* TWL4030 PMBR1 Register GPIO6 mux bits */
#define TWL4030_GPIO6_PWM0_MUTE(value) ((value & 0x03) << 2)
#define TWL4030_CACHEREGNUM (TWL4030_REG_MISC_SET_2 + 1)
struct twl4030_board_params {
unsigned int digimic_delay; /* in ms */
unsigned int ramp_delay_value;
unsigned int offset_cncl_path;
unsigned int hs_extmute:1;
int hs_extmute_gpio;
};
/* codec private data */
struct twl4030_priv {
unsigned int codec_powered;
/* reference counts of AIF/APLL users */
unsigned int apll_enabled;
struct snd_pcm_substream *master_substream;
struct snd_pcm_substream *slave_substream;
unsigned int configured;
unsigned int rate;
unsigned int sample_bits;
unsigned int channels;
unsigned int sysclk;
/* Output (with associated amp) states */
u8 hsl_enabled, hsr_enabled;
u8 earpiece_enabled;
u8 predrivel_enabled, predriver_enabled;
u8 carkitl_enabled, carkitr_enabled;
u8 ctl_cache[TWL4030_REG_PRECKR_CTL - TWL4030_REG_EAR_CTL + 1];
struct twl4030_board_params *board_params;
};
static void tw4030_init_ctl_cache(struct twl4030_priv *twl4030)
{
int i;
u8 byte;
for (i = TWL4030_REG_EAR_CTL; i <= TWL4030_REG_PRECKR_CTL; i++) {
twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, i);
twl4030->ctl_cache[i - TWL4030_REG_EAR_CTL] = byte;
}
}
static unsigned int twl4030_read(struct snd_soc_component *component, unsigned int reg)
{
struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
u8 value = 0;
if (reg >= TWL4030_CACHEREGNUM)
return -EIO;
switch (reg) {
case TWL4030_REG_EAR_CTL:
case TWL4030_REG_PREDL_CTL:
case TWL4030_REG_PREDR_CTL:
case TWL4030_REG_PRECKL_CTL:
case TWL4030_REG_PRECKR_CTL:
case TWL4030_REG_HS_GAIN_SET:
value = twl4030->ctl_cache[reg - TWL4030_REG_EAR_CTL];
break;
default:
twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &value, reg);
break;
}
return value;
}
static bool twl4030_can_write_to_chip(struct twl4030_priv *twl4030,
unsigned int reg)
{
bool write_to_reg = false;
/* Decide if the given register can be written */
switch (reg) {
case TWL4030_REG_EAR_CTL:
if (twl4030->earpiece_enabled)
write_to_reg = true;
break;
case TWL4030_REG_PREDL_CTL:
if (twl4030->predrivel_enabled)
write_to_reg = true;
break;
case TWL4030_REG_PREDR_CTL:
if (twl4030->predriver_enabled)
write_to_reg = true;
break;
case TWL4030_REG_PRECKL_CTL:
if (twl4030->carkitl_enabled)
write_to_reg = true;
break;
case TWL4030_REG_PRECKR_CTL:
if (twl4030->carkitr_enabled)
write_to_reg = true;
break;
case TWL4030_REG_HS_GAIN_SET:
if (twl4030->hsl_enabled || twl4030->hsr_enabled)
write_to_reg = true;
break;
default:
/* All other register can be written */
write_to_reg = true;
break;
}
return write_to_reg;
}
static int twl4030_write(struct snd_soc_component *component, unsigned int reg,
unsigned int value)
{
struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
/* Update the ctl cache */
switch (reg) {
case TWL4030_REG_EAR_CTL:
case TWL4030_REG_PREDL_CTL:
case TWL4030_REG_PREDR_CTL:
case TWL4030_REG_PRECKL_CTL:
case TWL4030_REG_PRECKR_CTL:
case TWL4030_REG_HS_GAIN_SET:
twl4030->ctl_cache[reg - TWL4030_REG_EAR_CTL] = value;
break;
default:
break;
}
if (twl4030_can_write_to_chip(twl4030, reg))
return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
return 0;
}
static inline void twl4030_wait_ms(int time)
{
if (time < 60) {
time *= 1000;
usleep_range(time, time + 500);
} else {
msleep(time);
}
}
static void twl4030_codec_enable(struct snd_soc_component *component, int enable)
{
struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
int mode;
if (enable == twl4030->codec_powered)
return;
if (enable)
mode = twl4030_audio_enable_resource(TWL4030_AUDIO_RES_POWER);
else
mode = twl4030_audio_disable_resource(TWL4030_AUDIO_RES_POWER);
if (mode >= 0)
twl4030->codec_powered = enable;
/* REVISIT: this delay is present in TI sample drivers */
/* but there seems to be no TRM requirement for it */
udelay(10);
}
static void
twl4030_get_board_param_values(struct twl4030_board_params *board_params,
struct device_node *node)
{
int value;
of_property_read_u32(node, "ti,digimic_delay", &board_params->digimic_delay);
of_property_read_u32(node, "ti,ramp_delay_value", &board_params->ramp_delay_value);
of_property_read_u32(node, "ti,offset_cncl_path", &board_params->offset_cncl_path);
if (!of_property_read_u32(node, "ti,hs_extmute", &value))
board_params->hs_extmute = value;
board_params->hs_extmute_gpio = of_get_named_gpio(node, "ti,hs_extmute_gpio", 0);
if (gpio_is_valid(board_params->hs_extmute_gpio))
board_params->hs_extmute = 1;
}
static struct twl4030_board_params*
twl4030_get_board_params(struct snd_soc_component *component)
{
struct twl4030_board_params *board_params = NULL;
struct device_node *twl4030_codec_node = NULL;
twl4030_codec_node = of_get_child_by_name(component->dev->parent->of_node,
"codec");
if (twl4030_codec_node) {
board_params = devm_kzalloc(component->dev,
sizeof(struct twl4030_board_params),
GFP_KERNEL);
if (!board_params) {
of_node_put(twl4030_codec_node);
return NULL;
}
twl4030_get_board_param_values(board_params, twl4030_codec_node);
of_node_put(twl4030_codec_node);
}
return board_params;
}
static void twl4030_init_chip(struct snd_soc_component *component)
{
struct twl4030_board_params *board_params;
struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
u8 reg, byte;
int i = 0;
board_params = twl4030_get_board_params(component);
if (board_params && board_params->hs_extmute) {
if (gpio_is_valid(board_params->hs_extmute_gpio)) {
int ret;
if (!board_params->hs_extmute_gpio)
dev_warn(component->dev,
"Extmute GPIO is 0 is this correct?\n");
ret = gpio_request_one(board_params->hs_extmute_gpio,
GPIOF_OUT_INIT_LOW,
"hs_extmute");
if (ret) {
dev_err(component->dev,
"Failed to get hs_extmute GPIO\n");
board_params->hs_extmute_gpio = -1;
}
} else {
u8 pin_mux;
/* Set TWL4030 GPIO6 as EXTMUTE signal */
twl_i2c_read_u8(TWL4030_MODULE_INTBR, &pin_mux,
TWL4030_PMBR1_REG);
pin_mux &= ~TWL4030_GPIO6_PWM0_MUTE(0x03);
pin_mux |= TWL4030_GPIO6_PWM0_MUTE(0x02);
twl_i2c_write_u8(TWL4030_MODULE_INTBR, pin_mux,
TWL4030_PMBR1_REG);
}
}
/* Initialize the local ctl register cache */
tw4030_init_ctl_cache(twl4030);
/* anti-pop when changing analog gain */
reg = twl4030_read(component, TWL4030_REG_MISC_SET_1);
twl4030_write(component, TWL4030_REG_MISC_SET_1,
reg | TWL4030_SMOOTH_ANAVOL_EN);
twl4030_write(component, TWL4030_REG_OPTION,
TWL4030_ATXL1_EN | TWL4030_ATXR1_EN |
TWL4030_ARXL2_EN | TWL4030_ARXR2_EN);
/* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */
twl4030_write(component, TWL4030_REG_ARXR2_APGA_CTL, 0x32);
/* Machine dependent setup */
if (!board_params)
return;
twl4030->board_params = board_params;
reg = twl4030_read(component, TWL4030_REG_HS_POPN_SET);
reg &= ~TWL4030_RAMP_DELAY;
reg |= (board_params->ramp_delay_value << 2);
twl4030_write(component, TWL4030_REG_HS_POPN_SET, reg);
/* initiate offset cancellation */
twl4030_codec_enable(component, 1);
reg = twl4030_read(component, TWL4030_REG_ANAMICL);
reg &= ~TWL4030_OFFSET_CNCL_SEL;
reg |= board_params->offset_cncl_path;
twl4030_write(component, TWL4030_REG_ANAMICL,
reg | TWL4030_CNCL_OFFSET_START);
/*
* Wait for offset cancellation to complete.
* Since this takes a while, do not slam the i2c.
* Start polling the status after ~20ms.
*/
msleep(20);
do {
usleep_range(1000, 2000);
twl_set_regcache_bypass(TWL4030_MODULE_AUDIO_VOICE, true);
twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
TWL4030_REG_ANAMICL);
twl_set_regcache_bypass(TWL4030_MODULE_AUDIO_VOICE, false);
} while ((i++ < 100) &&
((byte & TWL4030_CNCL_OFFSET_START) ==
TWL4030_CNCL_OFFSET_START));
twl4030_codec_enable(component, 0);
}
static void twl4030_apll_enable(struct snd_soc_component *component, int enable)
{
struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
if (enable) {
twl4030->apll_enabled++;
if (twl4030->apll_enabled == 1)
twl4030_audio_enable_resource(
TWL4030_AUDIO_RES_APLL);
} else {
twl4030->apll_enabled--;
if (!twl4030->apll_enabled)
twl4030_audio_disable_resource(
TWL4030_AUDIO_RES_APLL);
}
}
/* Earpiece */
static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
};
/* PreDrive Left */
static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
};
/* PreDrive Right */
static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
};
/* Headset Left */
static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
};
/* Headset Right */
static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
};
/* Carkit Left */
static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
};
/* Carkit Right */
static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
};
/* Handsfree Left */
static const char *twl4030_handsfreel_texts[] =
{"Voice", "AudioL1", "AudioL2", "AudioR2"};
static SOC_ENUM_SINGLE_DECL(twl4030_handsfreel_enum,
TWL4030_REG_HFL_CTL, 0,
twl4030_handsfreel_texts);
static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
/* Handsfree Left virtual mute */
static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
SOC_DAPM_SINGLE_VIRT("Switch", 1);
/* Handsfree Right */
static const char *twl4030_handsfreer_texts[] =
{"Voice", "AudioR1", "AudioR2", "AudioL2"};
static SOC_ENUM_SINGLE_DECL(twl4030_handsfreer_enum,
TWL4030_REG_HFR_CTL, 0,
twl4030_handsfreer_texts);
static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
/* Handsfree Right virtual mute */
static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
SOC_DAPM_SINGLE_VIRT("Switch", 1);
/* Vibra */
/* Vibra audio path selection */
static const char *twl4030_vibra_texts[] =
{"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
static SOC_ENUM_SINGLE_DECL(twl4030_vibra_enum,
TWL4030_REG_VIBRA_CTL, 2,
twl4030_vibra_texts);
static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
/* Vibra path selection: local vibrator (PWM) or audio driven */
static const char *twl4030_vibrapath_texts[] =
{"Local vibrator", "Audio"};
static SOC_ENUM_SINGLE_DECL(twl4030_vibrapath_enum,
TWL4030_REG_VIBRA_CTL, 4,
twl4030_vibrapath_texts);
static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
/* Left analog microphone selection */
static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
SOC_DAPM_SINGLE("Main Mic Capture Switch",
TWL4030_REG_ANAMICL, 0, 1, 0),
SOC_DAPM_SINGLE("Headset Mic Capture Switch",
TWL4030_REG_ANAMICL, 1, 1, 0),
SOC_DAPM_SINGLE("AUXL Capture Switch",
TWL4030_REG_ANAMICL, 2, 1, 0),
SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
TWL4030_REG_ANAMICL, 3, 1, 0),
};
/* Right analog microphone selection */
static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
};
/* TX1 L/R Analog/Digital microphone selection */
static const char *twl4030_micpathtx1_texts[] =
{"Analog", "Digimic0"};
static SOC_ENUM_SINGLE_DECL(twl4030_micpathtx1_enum,
TWL4030_REG_ADCMICSEL, 0,
twl4030_micpathtx1_texts);
static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
/* TX2 L/R Analog/Digital microphone selection */
static const char *twl4030_micpathtx2_texts[] =
{"Analog", "Digimic1"};
static SOC_ENUM_SINGLE_DECL(twl4030_micpathtx2_enum,
TWL4030_REG_ADCMICSEL, 2,
twl4030_micpathtx2_texts);
static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
/* Analog bypass for AudioR1 */
static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
/* Analog bypass for AudioL1 */
static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
/* Analog bypass for AudioR2 */
static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
/* Analog bypass for AudioL2 */
static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
/* Analog bypass for Voice */
static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
/* Digital bypass gain, mute instead of -30dB */
static const DECLARE_TLV_DB_RANGE(twl4030_dapm_dbypass_tlv,
0, 1, TLV_DB_SCALE_ITEM(-3000, 600, 1),
2, 3, TLV_DB_SCALE_ITEM(-2400, 0, 0),
4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0)
);
/* Digital bypass left (TX1L -> RX2L) */
static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
SOC_DAPM_SINGLE_TLV("Volume",
TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
twl4030_dapm_dbypass_tlv);
/* Digital bypass right (TX1R -> RX2R) */
static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
SOC_DAPM_SINGLE_TLV("Volume",
TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
twl4030_dapm_dbypass_tlv);
/*
* Voice Sidetone GAIN volume control:
* from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
*/
static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
/* Digital bypass voice: sidetone (VUL -> VDL)*/
static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
SOC_DAPM_SINGLE_TLV("Volume",
TWL4030_REG_VSTPGA, 0, 0x29, 0,
twl4030_dapm_dbypassv_tlv);
/*
* Output PGA builder:
* Handle the muting and unmuting of the given output (turning off the
* amplifier associated with the output pin)
* On mute bypass the reg_cache and write 0 to the register
* On unmute: restore the register content from the reg_cache
* Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
*/
#define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
struct snd_kcontrol *kcontrol, int event) \
{ \
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); \
struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component); \
\
switch (event) { \
case SND_SOC_DAPM_POST_PMU: \
twl4030->pin_name##_enabled = 1; \
twl4030_write(component, reg, twl4030_read(component, reg)); \
break; \
case SND_SOC_DAPM_POST_PMD: \
twl4030->pin_name##_enabled = 0; \
twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, 0, reg); \
break; \
} \
return 0; \
}
TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
static void handsfree_ramp(struct snd_soc_component *component, int reg, int ramp)
{
unsigned char hs_ctl;
hs_ctl = twl4030_read(component, reg);
if (ramp) {
/* HF ramp-up */
hs_ctl |= TWL4030_HF_CTL_REF_EN;
twl4030_write(component, reg, hs_ctl);
udelay(10);
hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
twl4030_write(component, reg, hs_ctl);
udelay(40);
hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
hs_ctl |= TWL4030_HF_CTL_HB_EN;
twl4030_write(component, reg, hs_ctl);
} else {
/* HF ramp-down */
hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
twl4030_write(component, reg, hs_ctl);
hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
twl4030_write(component, reg, hs_ctl);
udelay(40);
hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
twl4030_write(component, reg, hs_ctl);
}
}
static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
handsfree_ramp(component, TWL4030_REG_HFL_CTL, 1);
break;
case SND_SOC_DAPM_POST_PMD:
handsfree_ramp(component, TWL4030_REG_HFL_CTL, 0);
break;
}
return 0;
}
static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
handsfree_ramp(component, TWL4030_REG_HFR_CTL, 1);
break;
case SND_SOC_DAPM_POST_PMD:
handsfree_ramp(component, TWL4030_REG_HFR_CTL, 0);
break;
}
return 0;
}
static int vibramux_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
twl4030_write(component, TWL4030_REG_VIBRA_SET, 0xff);
return 0;
}
static int apll_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
twl4030_apll_enable(component, 1);
break;
case SND_SOC_DAPM_POST_PMD:
twl4030_apll_enable(component, 0);
break;
}
return 0;
}
static int aif_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
u8 audio_if;
audio_if = twl4030_read(component, TWL4030_REG_AUDIO_IF);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* Enable AIF */
/* enable the PLL before we use it to clock the DAI */
twl4030_apll_enable(component, 1);
twl4030_write(component, TWL4030_REG_AUDIO_IF,
audio_if | TWL4030_AIF_EN);
break;
case SND_SOC_DAPM_POST_PMD:
/* disable the DAI before we stop it's source PLL */
twl4030_write(component, TWL4030_REG_AUDIO_IF,
audio_if & ~TWL4030_AIF_EN);
twl4030_apll_enable(component, 0);
break;
}
return 0;
}
static void headset_ramp(struct snd_soc_component *component, int ramp)
{
unsigned char hs_gain, hs_pop;
struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
struct twl4030_board_params *board_params = twl4030->board_params;
/* Base values for ramp delay calculation: 2^19 - 2^26 */
static const unsigned int ramp_base[] = {
524288, 1048576, 2097152, 4194304,
8388608, 16777216, 33554432, 67108864
};
unsigned int delay;
hs_gain = twl4030_read(component, TWL4030_REG_HS_GAIN_SET);
hs_pop = twl4030_read(component, TWL4030_REG_HS_POPN_SET);
delay = (ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
twl4030->sysclk) + 1;
/* Enable external mute control, this dramatically reduces
* the pop-noise */
if (board_params && board_params->hs_extmute) {
if (gpio_is_valid(board_params->hs_extmute_gpio)) {
gpio_set_value(board_params->hs_extmute_gpio, 1);
} else {
hs_pop |= TWL4030_EXTMUTE;
twl4030_write(component, TWL4030_REG_HS_POPN_SET, hs_pop);
}
}
if (ramp) {
/* Headset ramp-up according to the TRM */
hs_pop |= TWL4030_VMID_EN;
twl4030_write(component, TWL4030_REG_HS_POPN_SET, hs_pop);
/* Actually write to the register */
twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, hs_gain,
TWL4030_REG_HS_GAIN_SET);
hs_pop |= TWL4030_RAMP_EN;
twl4030_write(component, TWL4030_REG_HS_POPN_SET, hs_pop);
/* Wait ramp delay time + 1, so the VMID can settle */
twl4030_wait_ms(delay);
} else {
/* Headset ramp-down _not_ according to
* the TRM, but in a way that it is working */
hs_pop &= ~TWL4030_RAMP_EN;
twl4030_write(component, TWL4030_REG_HS_POPN_SET, hs_pop);
/* Wait ramp delay time + 1, so the VMID can settle */
twl4030_wait_ms(delay);
/* Bypass the reg_cache to mute the headset */
twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, hs_gain & (~0x0f),
TWL4030_REG_HS_GAIN_SET);
hs_pop &= ~TWL4030_VMID_EN;
twl4030_write(component, TWL4030_REG_HS_POPN_SET, hs_pop);
}
/* Disable external mute */
if (board_params && board_params->hs_extmute) {
if (gpio_is_valid(board_params->hs_extmute_gpio)) {
gpio_set_value(board_params->hs_extmute_gpio, 0);
} else {
hs_pop &= ~TWL4030_EXTMUTE;
twl4030_write(component, TWL4030_REG_HS_POPN_SET, hs_pop);
}
}
}
static int headsetlpga_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
/* Do the ramp-up only once */
if (!twl4030->hsr_enabled)
headset_ramp(component, 1);
twl4030->hsl_enabled = 1;
break;
case SND_SOC_DAPM_POST_PMD:
/* Do the ramp-down only if both headsetL/R is disabled */
if (!twl4030->hsr_enabled)
headset_ramp(component, 0);
twl4030->hsl_enabled = 0;
break;
}
return 0;
}
static int headsetrpga_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
/* Do the ramp-up only once */
if (!twl4030->hsl_enabled)
headset_ramp(component, 1);
twl4030->hsr_enabled = 1;
break;
case SND_SOC_DAPM_POST_PMD:
/* Do the ramp-down only if both headsetL/R is disabled */
if (!twl4030->hsl_enabled)
headset_ramp(component, 0);
twl4030->hsr_enabled = 0;
break;
}
return 0;
}
static int digimic_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
struct twl4030_board_params *board_params = twl4030->board_params;
if (board_params && board_params->digimic_delay)
twl4030_wait_ms(board_params->digimic_delay);
return 0;
}
/*
* Some of the gain controls in TWL (mostly those which are associated with
* the outputs) are implemented in an interesting way:
* 0x0 : Power down (mute)
* 0x1 : 6dB
* 0x2 : 0 dB
* 0x3 : -6 dB
* Inverting not going to help with these.
* Custom volsw and volsw_2r get/put functions to handle these gain bits.
*/
static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
unsigned int reg = mc->reg;
unsigned int shift = mc->shift;
unsigned int rshift = mc->rshift;
int max = mc->max;
int mask = (1 << fls(max)) - 1;
ucontrol->value.integer.value[0] =
(twl4030_read(component, reg) >> shift) & mask;
if (ucontrol->value.integer.value[0])
ucontrol->value.integer.value[0] =
max + 1 - ucontrol->value.integer.value[0];
if (shift != rshift) {
ucontrol->value.integer.value[1] =
(twl4030_read(component, reg) >> rshift) & mask;
if (ucontrol->value.integer.value[1])
ucontrol->value.integer.value[1] =
max + 1 - ucontrol->value.integer.value[1];
}
return 0;
}
static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
unsigned int reg = mc->reg;
unsigned int shift = mc->shift;
unsigned int rshift = mc->rshift;
int max = mc->max;
int mask = (1 << fls(max)) - 1;
unsigned short val, val2, val_mask;
val = (ucontrol->value.integer.value[0] & mask);
val_mask = mask << shift;
if (val)
val = max + 1 - val;
val = val << shift;
if (shift != rshift) {
val2 = (ucontrol->value.integer.value[1] & mask);
val_mask |= mask << rshift;
if (val2)
val2 = max + 1 - val2;
val |= val2 << rshift;
}
return snd_soc_component_update_bits(component, reg, val_mask, val);
}
static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
unsigned int reg = mc->reg;
unsigned int reg2 = mc->rreg;
unsigned int shift = mc->shift;
int max = mc->max;
int mask = (1<<fls(max))-1;
ucontrol->value.integer.value[0] =
(twl4030_read(component, reg) >> shift) & mask;
ucontrol->value.integer.value[1] =
(twl4030_read(component, reg2) >> shift) & mask;
if (ucontrol->value.integer.value[0])
ucontrol->value.integer.value[0] =
max + 1 - ucontrol->value.integer.value[0];
if (ucontrol->value.integer.value[1])
ucontrol->value.integer.value[1] =
max + 1 - ucontrol->value.integer.value[1];
return 0;
}
static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
unsigned int reg = mc->reg;
unsigned int reg2 = mc->rreg;
unsigned int shift = mc->shift;
int max = mc->max;
int mask = (1 << fls(max)) - 1;
int err;
unsigned short val, val2, val_mask;
val_mask = mask << shift;
val = (ucontrol->value.integer.value[0] & mask);
val2 = (ucontrol->value.integer.value[1] & mask);
if (val)
val = max + 1 - val;
if (val2)
val2 = max + 1 - val2;
val = val << shift;
val2 = val2 << shift;
err = snd_soc_component_update_bits(component, reg, val_mask, val);
if (err < 0)
return err;
err = snd_soc_component_update_bits(component, reg2, val_mask, val2);
return err;
}
/* Codec operation modes */
static const char *twl4030_op_modes_texts[] = {
"Option 2 (voice/audio)", "Option 1 (audio)"
};
static SOC_ENUM_SINGLE_DECL(twl4030_op_modes_enum,
TWL4030_REG_CODEC_MODE, 0,
twl4030_op_modes_texts);
static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
if (twl4030->configured) {
dev_err(component->dev,
"operation mode cannot be changed on-the-fly\n");
return -EBUSY;
}
return snd_soc_put_enum_double(kcontrol, ucontrol);
}
/*
* FGAIN volume control:
* from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
*/
static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
/*
* CGAIN volume control:
* 0 dB to 12 dB in 6 dB steps
* value 2 and 3 means 12 dB
*/
static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
/*
* Voice Downlink GAIN volume control:
* from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
*/
static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
/*
* Analog playback gain
* -24 dB to 12 dB in 2 dB steps
*/
static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
/*
* Gain controls tied to outputs
* -6 dB to 6 dB in 6 dB steps (mute instead of -12)
*/
static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
/*
* Gain control for earpiece amplifier
* 0 dB to 12 dB in 6 dB steps (mute instead of -6)
*/
static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
/*
* Capture gain after the ADCs
* from 0 dB to 31 dB in 1 dB steps
*/
static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
/*
* Gain control for input amplifiers
* 0 dB to 30 dB in 6 dB steps
*/
static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
/* AVADC clock priority */
static const char *twl4030_avadc_clk_priority_texts[] = {
"Voice high priority", "HiFi high priority"
};
static SOC_ENUM_SINGLE_DECL(twl4030_avadc_clk_priority_enum,
TWL4030_REG_AVADC_CTL, 2,
twl4030_avadc_clk_priority_texts);
static const char *twl4030_rampdelay_texts[] = {
"27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
"437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
"3495/2581/1748 ms"
};
static SOC_ENUM_SINGLE_DECL(twl4030_rampdelay_enum,
TWL4030_REG_HS_POPN_SET, 2,
twl4030_rampdelay_texts);
/* Vibra H-bridge direction mode */
static const char *twl4030_vibradirmode_texts[] = {
"Vibra H-bridge direction", "Audio data MSB",
};
static SOC_ENUM_SINGLE_DECL(twl4030_vibradirmode_enum,
TWL4030_REG_VIBRA_CTL, 5,
twl4030_vibradirmode_texts);
/* Vibra H-bridge direction */
static const char *twl4030_vibradir_texts[] = {
"Positive polarity", "Negative polarity",
};
static SOC_ENUM_SINGLE_DECL(twl4030_vibradir_enum,
TWL4030_REG_VIBRA_CTL, 1,
twl4030_vibradir_texts);
/* Digimic Left and right swapping */
static const char *twl4030_digimicswap_texts[] = {
"Not swapped", "Swapped",
};
static SOC_ENUM_SINGLE_DECL(twl4030_digimicswap_enum,
TWL4030_REG_MISC_SET_1, 0,
twl4030_digimicswap_texts);
static const struct snd_kcontrol_new twl4030_snd_controls[] = {
/* Codec operation mode control */
SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
snd_soc_get_enum_double,
snd_soc_put_twl4030_opmode_enum_double),
/* Common playback gain controls */
SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
0, 0x3f, 0, digital_fine_tlv),
SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
0, 0x3f, 0, digital_fine_tlv),
SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
6, 0x2, 0, digital_coarse_tlv),
SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
6, 0x2, 0, digital_coarse_tlv),
SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
3, 0x12, 1, analog_tlv),
SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
3, 0x12, 1, analog_tlv),
SOC_DOUBLE_R("DAC1 Analog Playback Switch",
TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1, 1, 0),
SOC_DOUBLE_R("DAC2 Analog Playback Switch",
TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1, 1, 0),
/* Common voice downlink gain controls */
SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
SOC_SINGLE("DAC Voice Analog Downlink Switch",
TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
/* Separate output gain controls */
SOC_DOUBLE_R_EXT_TLV("PreDriv Playback Volume",
TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
4, 3, 0, snd_soc_get_volsw_r2_twl4030,
snd_soc_put_volsw_r2_twl4030, output_tvl),
SOC_DOUBLE_EXT_TLV("Headset Playback Volume",
TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, snd_soc_get_volsw_twl4030,
snd_soc_put_volsw_twl4030, output_tvl),
SOC_DOUBLE_R_EXT_TLV("Carkit Playback Volume",
TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
4, 3, 0, snd_soc_get_volsw_r2_twl4030,
snd_soc_put_volsw_r2_twl4030, output_tvl),
SOC_SINGLE_EXT_TLV("Earpiece Playback Volume",
TWL4030_REG_EAR_CTL, 4, 3, 0, snd_soc_get_volsw_twl4030,
snd_soc_put_volsw_twl4030, output_ear_tvl),
/* Common capture gain controls */
SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
0, 0x1f, 0, digital_capture_tlv),
SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
0, 0x1f, 0, digital_capture_tlv),
SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
0, 3, 5, 0, input_gain_tlv),
SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
SOC_ENUM("Digimic LR Swap", twl4030_digimicswap_enum),
};
static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
/* Left channel inputs */
SND_SOC_DAPM_INPUT("MAINMIC"),
SND_SOC_DAPM_INPUT("HSMIC"),
SND_SOC_DAPM_INPUT("AUXL"),
SND_SOC_DAPM_INPUT("CARKITMIC"),
/* Right channel inputs */
SND_SOC_DAPM_INPUT("SUBMIC"),
SND_SOC_DAPM_INPUT("AUXR"),
/* Digital microphones (Stereo) */
SND_SOC_DAPM_INPUT("DIGIMIC0"),
SND_SOC_DAPM_INPUT("DIGIMIC1"),
/* Outputs */
SND_SOC_DAPM_OUTPUT("EARPIECE"),
SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
SND_SOC_DAPM_OUTPUT("PREDRIVER"),
SND_SOC_DAPM_OUTPUT("HSOL"),
SND_SOC_DAPM_OUTPUT("HSOR"),
SND_SOC_DAPM_OUTPUT("CARKITL"),
SND_SOC_DAPM_OUTPUT("CARKITR"),
SND_SOC_DAPM_OUTPUT("HFL"),
SND_SOC_DAPM_OUTPUT("HFR"),
SND_SOC_DAPM_OUTPUT("VIBRA"),
/* AIF and APLL clocks for running DAIs (including loopback) */
SND_SOC_DAPM_OUTPUT("Virtual HiFi OUT"),
SND_SOC_DAPM_INPUT("Virtual HiFi IN"),
SND_SOC_DAPM_OUTPUT("Virtual Voice OUT"),
/* DACs */
SND_SOC_DAPM_DAC("DAC Right1", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DAC Left1", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DAC Right2", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DAC Left2", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DAC Voice", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("VAIFIN", "Voice Playback", 0,
TWL4030_REG_VOICE_IF, 6, 0),
/* Analog bypasses */
SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
&twl4030_dapm_abypassr1_control),
SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
&twl4030_dapm_abypassl1_control),
SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
&twl4030_dapm_abypassr2_control),
SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
&twl4030_dapm_abypassl2_control),
SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
&twl4030_dapm_abypassv_control),
/* Master analog loopback switch */
SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
NULL, 0),
/* Digital bypasses */
SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
&twl4030_dapm_dbypassl_control),
SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
&twl4030_dapm_dbypassr_control),
SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
&twl4030_dapm_dbypassv_control),
/* Digital mixers, power control for the physical DACs */
SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
/* Analog mixers, power control for the physical PGAs */
SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("AIF Enable", SND_SOC_NOPM, 0, 0, aif_event,
SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
/* Output MIXER controls */
/* Earpiece */
SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
&twl4030_dapm_earpiece_controls[0],
ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
0, 0, NULL, 0, earpiecepga_event,
SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
/* PreDrivL/R */
SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
&twl4030_dapm_predrivel_controls[0],
ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
0, 0, NULL, 0, predrivelpga_event,
SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
&twl4030_dapm_predriver_controls[0],
ARRAY_SIZE(twl4030_dapm_predriver_controls)),
SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
0, 0, NULL, 0, predriverpga_event,
SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
/* HeadsetL/R */
SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
&twl4030_dapm_hsol_controls[0],
ARRAY_SIZE(twl4030_dapm_hsol_controls)),
SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
0, 0, NULL, 0, headsetlpga_event,
SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
&twl4030_dapm_hsor_controls[0],
ARRAY_SIZE(twl4030_dapm_hsor_controls)),
SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
0, 0, NULL, 0, headsetrpga_event,
SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
/* CarkitL/R */
SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
&twl4030_dapm_carkitl_controls[0],
ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
0, 0, NULL, 0, carkitlpga_event,
SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
&twl4030_dapm_carkitr_controls[0],
ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
0, 0, NULL, 0, carkitrpga_event,
SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
/* Output MUX controls */
/* HandsfreeL/R */
SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
&twl4030_dapm_handsfreel_control),
SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
&twl4030_dapm_handsfreelmute_control),
SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
0, 0, NULL, 0, handsfreelpga_event,
SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
&twl4030_dapm_handsfreer_control),
SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
&twl4030_dapm_handsfreermute_control),
SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
0, 0, NULL, 0, handsfreerpga_event,
SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
/* Vibra */
SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
&twl4030_dapm_vibra_control, vibramux_event,
SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
&twl4030_dapm_vibrapath_control),
/* Introducing four virtual ADC, since TWL4030 have four channel for
capture */
SND_SOC_DAPM_ADC("ADC Virtual Left1", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("ADC Virtual Right1", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("ADC Virtual Left2", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("ADC Virtual Right2", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("VAIFOUT", "Voice Capture", 0,
TWL4030_REG_VOICE_IF, 5, 0),
/* Analog/Digital mic path selection.
TX1 Left/Right: either analog Left/Right or Digimic0
TX2 Left/Right: either analog Left/Right or Digimic1 */
SND_SOC_DAPM_MUX("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
&twl4030_dapm_micpathtx1_control),
SND_SOC_DAPM_MUX("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
&twl4030_dapm_micpathtx2_control),
/* Analog input mixers for the capture amplifiers */
SND_SOC_DAPM_MIXER("Analog Left",
TWL4030_REG_ANAMICL, 4, 0,
&twl4030_dapm_analoglmic_controls[0],
ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
SND_SOC_DAPM_MIXER("Analog Right",
TWL4030_REG_ANAMICR, 4, 0,
&twl4030_dapm_analogrmic_controls[0],
ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
SND_SOC_DAPM_PGA("ADC Physical Left",
TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
SND_SOC_DAPM_PGA("ADC Physical Right",
TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
SND_SOC_DAPM_PGA_E("Digimic0 Enable",
TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0,
digimic_event, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("Digimic1 Enable",
TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0,
digimic_event, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY("micbias1 select", TWL4030_REG_MICBIAS_CTL, 5, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("micbias2 select", TWL4030_REG_MICBIAS_CTL, 6, 0,
NULL, 0),
/* Microphone bias */
SND_SOC_DAPM_SUPPLY("Mic Bias 1",
TWL4030_REG_MICBIAS_CTL, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Mic Bias 2",
TWL4030_REG_MICBIAS_CTL, 1, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Headset Mic Bias",
TWL4030_REG_MICBIAS_CTL, 2, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("VIF Enable", TWL4030_REG_VOICE_IF, 0, 0, NULL, 0),
};
static const struct snd_soc_dapm_route intercon[] = {
/* Stream -> DAC mapping */
{"DAC Right1", NULL, "HiFi Playback"},
{"DAC Left1", NULL, "HiFi Playback"},
{"DAC Right2", NULL, "HiFi Playback"},
{"DAC Left2", NULL, "HiFi Playback"},
{"DAC Voice", NULL, "VAIFIN"},
/* ADC -> Stream mapping */
{"HiFi Capture", NULL, "ADC Virtual Left1"},
{"HiFi Capture", NULL, "ADC Virtual Right1"},
{"HiFi Capture", NULL, "ADC Virtual Left2"},
{"HiFi Capture", NULL, "ADC Virtual Right2"},
{"VAIFOUT", NULL, "ADC Virtual Left2"},
{"VAIFOUT", NULL, "ADC Virtual Right2"},
{"VAIFOUT", NULL, "VIF Enable"},
{"Digital L1 Playback Mixer", NULL, "DAC Left1"},
{"Digital R1 Playback Mixer", NULL, "DAC Right1"},
{"Digital L2 Playback Mixer", NULL, "DAC Left2"},
{"Digital R2 Playback Mixer", NULL, "DAC Right2"},
{"Digital Voice Playback Mixer", NULL, "DAC Voice"},
/* Supply for the digital part (APLL) */
{"Digital Voice Playback Mixer", NULL, "APLL Enable"},
{"DAC Left1", NULL, "AIF Enable"},
{"DAC Right1", NULL, "AIF Enable"},
{"DAC Left2", NULL, "AIF Enable"},
{"DAC Right1", NULL, "AIF Enable"},
{"DAC Voice", NULL, "VIF Enable"},
{"Digital R2 Playback Mixer", NULL, "AIF Enable"},
{"Digital L2 Playback Mixer", NULL, "AIF Enable"},
{"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
{"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
{"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
{"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
{"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
/* Internal playback routings */
/* Earpiece */
{"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
{"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
{"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
{"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
{"Earpiece PGA", NULL, "Earpiece Mixer"},
/* PreDrivL */
{"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
{"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
{"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
{"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
{"PredriveL PGA", NULL, "PredriveL Mixer"},
/* PreDrivR */
{"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
{"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
{"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
{"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
{"PredriveR PGA", NULL, "PredriveR Mixer"},
/* HeadsetL */
{"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
{"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
{"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
{"HeadsetL PGA", NULL, "HeadsetL Mixer"},
/* HeadsetR */
{"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
{"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
{"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
{"HeadsetR PGA", NULL, "HeadsetR Mixer"},
/* CarkitL */
{"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
{"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
{"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
{"CarkitL PGA", NULL, "CarkitL Mixer"},
/* CarkitR */
{"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
{"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
{"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
{"CarkitR PGA", NULL, "CarkitR Mixer"},
/* HandsfreeL */
{"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
{"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
{"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
{"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
{"HandsfreeL", "Switch", "HandsfreeL Mux"},
{"HandsfreeL PGA", NULL, "HandsfreeL"},
/* HandsfreeR */
{"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
{"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
{"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
{"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
{"HandsfreeR", "Switch", "HandsfreeR Mux"},
{"HandsfreeR PGA", NULL, "HandsfreeR"},
/* Vibra */
{"Vibra Mux", "AudioL1", "DAC Left1"},
{"Vibra Mux", "AudioR1", "DAC Right1"},
{"Vibra Mux", "AudioL2", "DAC Left2"},
{"Vibra Mux", "AudioR2", "DAC Right2"},
/* outputs */
/* Must be always connected (for AIF and APLL) */
{"Virtual HiFi OUT", NULL, "DAC Left1"},
{"Virtual HiFi OUT", NULL, "DAC Right1"},
{"Virtual HiFi OUT", NULL, "DAC Left2"},
{"Virtual HiFi OUT", NULL, "DAC Right2"},
/* Must be always connected (for APLL) */
{"Virtual Voice OUT", NULL, "Digital Voice Playback Mixer"},
/* Physical outputs */
{"EARPIECE", NULL, "Earpiece PGA"},
{"PREDRIVEL", NULL, "PredriveL PGA"},
{"PREDRIVER", NULL, "PredriveR PGA"},
{"HSOL", NULL, "HeadsetL PGA"},
{"HSOR", NULL, "HeadsetR PGA"},
{"CARKITL", NULL, "CarkitL PGA"},
{"CARKITR", NULL, "CarkitR PGA"},
{"HFL", NULL, "HandsfreeL PGA"},
{"HFR", NULL, "HandsfreeR PGA"},
{"Vibra Route", "Audio", "Vibra Mux"},
{"VIBRA", NULL, "Vibra Route"},
/* Capture path */
/* Must be always connected (for AIF and APLL) */
{"ADC Virtual Left1", NULL, "Virtual HiFi IN"},
{"ADC Virtual Right1", NULL, "Virtual HiFi IN"},
{"ADC Virtual Left2", NULL, "Virtual HiFi IN"},
{"ADC Virtual Right2", NULL, "Virtual HiFi IN"},
/* Physical inputs */
{"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
{"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
{"Analog Left", "AUXL Capture Switch", "AUXL"},
{"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
{"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
{"Analog Right", "AUXR Capture Switch", "AUXR"},
{"ADC Physical Left", NULL, "Analog Left"},
{"ADC Physical Right", NULL, "Analog Right"},
{"Digimic0 Enable", NULL, "DIGIMIC0"},
{"Digimic1 Enable", NULL, "DIGIMIC1"},
{"DIGIMIC0", NULL, "micbias1 select"},
{"DIGIMIC1", NULL, "micbias2 select"},
/* TX1 Left capture path */
{"TX1 Capture Route", "Analog", "ADC Physical Left"},
{"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
/* TX1 Right capture path */
{"TX1 Capture Route", "Analog", "ADC Physical Right"},
{"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
/* TX2 Left capture path */
{"TX2 Capture Route", "Analog", "ADC Physical Left"},
{"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
/* TX2 Right capture path */
{"TX2 Capture Route", "Analog", "ADC Physical Right"},
{"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
{"ADC Virtual Left1", NULL, "TX1 Capture Route"},
{"ADC Virtual Right1", NULL, "TX1 Capture Route"},
{"ADC Virtual Left2", NULL, "TX2 Capture Route"},
{"ADC Virtual Right2", NULL, "TX2 Capture Route"},
{"ADC Virtual Left1", NULL, "AIF Enable"},
{"ADC Virtual Right1", NULL, "AIF Enable"},
{"ADC Virtual Left2", NULL, "AIF Enable"},
{"ADC Virtual Right2", NULL, "AIF Enable"},
/* Analog bypass routes */
{"Right1 Analog Loopback", "Switch", "Analog Right"},
{"Left1 Analog Loopback", "Switch", "Analog Left"},
{"Right2 Analog Loopback", "Switch", "Analog Right"},
{"Left2 Analog Loopback", "Switch", "Analog Left"},
{"Voice Analog Loopback", "Switch", "Analog Left"},
/* Supply for the Analog loopbacks */
{"Right1 Analog Loopback", NULL, "FM Loop Enable"},
{"Left1 Analog Loopback", NULL, "FM Loop Enable"},
{"Right2 Analog Loopback", NULL, "FM Loop Enable"},
{"Left2 Analog Loopback", NULL, "FM Loop Enable"},
{"Voice Analog Loopback", NULL, "FM Loop Enable"},
{"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
{"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
{"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
{"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
{"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
/* Digital bypass routes */
{"Right Digital Loopback", "Volume", "TX1 Capture Route"},
{"Left Digital Loopback", "Volume", "TX1 Capture Route"},
{"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
{"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
{"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
{"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
};
static int twl4030_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
twl4030_codec_enable(component, 1);
break;
case SND_SOC_BIAS_OFF:
twl4030_codec_enable(component, 0);
break;
}
return 0;
}
static void twl4030_constraints(struct twl4030_priv *twl4030,
struct snd_pcm_substream *mst_substream)
{
struct snd_pcm_substream *slv_substream;
/* Pick the stream, which need to be constrained */
if (mst_substream == twl4030->master_substream)
slv_substream = twl4030->slave_substream;
else if (mst_substream == twl4030->slave_substream)
slv_substream = twl4030->master_substream;
else /* This should not happen.. */
return;
/* Set the constraints according to the already configured stream */
snd_pcm_hw_constraint_single(slv_substream->runtime,
SNDRV_PCM_HW_PARAM_RATE,
twl4030->rate);
snd_pcm_hw_constraint_single(slv_substream->runtime,
SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
twl4030->sample_bits);
snd_pcm_hw_constraint_single(slv_substream->runtime,
SNDRV_PCM_HW_PARAM_CHANNELS,
twl4030->channels);
}
/* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
* capture has to be enabled/disabled. */
static void twl4030_tdm_enable(struct snd_soc_component *component, int direction,
int enable)
{
u8 reg, mask;
reg = twl4030_read(component, TWL4030_REG_OPTION);
if (direction == SNDRV_PCM_STREAM_PLAYBACK)
mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
else
mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
if (enable)
reg |= mask;
else
reg &= ~mask;
twl4030_write(component, TWL4030_REG_OPTION, reg);
}
static int twl4030_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
if (twl4030->master_substream) {
twl4030->slave_substream = substream;
/* The DAI has one configuration for playback and capture, so
* if the DAI has been already configured then constrain this
* substream to match it. */
if (twl4030->configured)
twl4030_constraints(twl4030, twl4030->master_substream);
} else {
if (!(twl4030_read(component, TWL4030_REG_CODEC_MODE) &
TWL4030_OPTION_1)) {
/* In option2 4 channel is not supported, set the
* constraint for the first stream for channels, the
* second stream will 'inherit' this cosntraint */
snd_pcm_hw_constraint_single(substream->runtime,
SNDRV_PCM_HW_PARAM_CHANNELS,
2);
}
twl4030->master_substream = substream;
}
return 0;
}
static void twl4030_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
if (twl4030->master_substream == substream)
twl4030->master_substream = twl4030->slave_substream;
twl4030->slave_substream = NULL;
/* If all streams are closed, or the remaining stream has not yet
* been configured than set the DAI as not configured. */
if (!twl4030->master_substream)
twl4030->configured = 0;
else if (!twl4030->master_substream->runtime->channels)
twl4030->configured = 0;
/* If the closing substream had 4 channel, do the necessary cleanup */
if (substream->runtime->channels == 4)
twl4030_tdm_enable(component, substream->stream, 0);
}
static int twl4030_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
u8 mode, old_mode, format, old_format;
/* If the substream has 4 channel, do the necessary setup */
if (params_channels(params) == 4) {
format = twl4030_read(component, TWL4030_REG_AUDIO_IF);
mode = twl4030_read(component, TWL4030_REG_CODEC_MODE);
/* Safety check: are we in the correct operating mode and
* the interface is in TDM mode? */
if ((mode & TWL4030_OPTION_1) &&
((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
twl4030_tdm_enable(component, substream->stream, 1);
else
return -EINVAL;
}
if (twl4030->configured)
/* Ignoring hw_params for already configured DAI */
return 0;
/* bit rate */
old_mode = twl4030_read(component,
TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
mode = old_mode & ~TWL4030_APLL_RATE;
switch (params_rate(params)) {
case 8000:
mode |= TWL4030_APLL_RATE_8000;
break;
case 11025:
mode |= TWL4030_APLL_RATE_11025;
break;
case 12000:
mode |= TWL4030_APLL_RATE_12000;
break;
case 16000:
mode |= TWL4030_APLL_RATE_16000;
break;
case 22050:
mode |= TWL4030_APLL_RATE_22050;
break;
case 24000:
mode |= TWL4030_APLL_RATE_24000;
break;
case 32000:
mode |= TWL4030_APLL_RATE_32000;
break;
case 44100:
mode |= TWL4030_APLL_RATE_44100;
break;
case 48000:
mode |= TWL4030_APLL_RATE_48000;
break;
case 96000:
mode |= TWL4030_APLL_RATE_96000;
break;
default:
dev_err(component->dev, "%s: unknown rate %d\n", __func__,
params_rate(params));
return -EINVAL;
}
/* sample size */
old_format = twl4030_read(component, TWL4030_REG_AUDIO_IF);
format = old_format;
format &= ~TWL4030_DATA_WIDTH;
switch (params_width(params)) {
case 16:
format |= TWL4030_DATA_WIDTH_16S_16W;
break;
case 32:
format |= TWL4030_DATA_WIDTH_32S_24W;
break;
default:
dev_err(component->dev, "%s: unsupported bits/sample %d\n",
__func__, params_width(params));
return -EINVAL;
}
if (format != old_format || mode != old_mode) {
if (twl4030->codec_powered) {
/*
* If the codec is powered, than we need to toggle the
* codec power.
*/
twl4030_codec_enable(component, 0);
twl4030_write(component, TWL4030_REG_CODEC_MODE, mode);
twl4030_write(component, TWL4030_REG_AUDIO_IF, format);
twl4030_codec_enable(component, 1);
} else {
twl4030_write(component, TWL4030_REG_CODEC_MODE, mode);
twl4030_write(component, TWL4030_REG_AUDIO_IF, format);
}
}
/* Store the important parameters for the DAI configuration and set
* the DAI as configured */
twl4030->configured = 1;
twl4030->rate = params_rate(params);
twl4030->sample_bits = hw_param_interval(params,
SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
twl4030->channels = params_channels(params);
/* If both playback and capture streams are open, and one of them
* is setting the hw parameters right now (since we are here), set
* constraints to the other stream to match the current one. */
if (twl4030->slave_substream)
twl4030_constraints(twl4030, substream);
return 0;
}
static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id,
unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
switch (freq) {
case 19200000:
case 26000000:
case 38400000:
break;
default:
dev_err(component->dev, "Unsupported HFCLKIN: %u\n", freq);
return -EINVAL;
}
if ((freq / 1000) != twl4030->sysclk) {
dev_err(component->dev,
"Mismatch in HFCLKIN: %u (configured: %u)\n",
freq, twl4030->sysclk * 1000);
return -EINVAL;
}
return 0;
}
static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
u8 old_format, format;
/* get format */
old_format = twl4030_read(component, TWL4030_REG_AUDIO_IF);
format = old_format;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
format &= ~(TWL4030_AIF_SLAVE_EN);
format &= ~(TWL4030_CLK256FS_EN);
break;
case SND_SOC_DAIFMT_CBC_CFC:
format |= TWL4030_AIF_SLAVE_EN;
format |= TWL4030_CLK256FS_EN;
break;
default:
return -EINVAL;
}
/* interface format */
format &= ~TWL4030_AIF_FORMAT;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
format |= TWL4030_AIF_FORMAT_CODEC;
break;
case SND_SOC_DAIFMT_DSP_A:
format |= TWL4030_AIF_FORMAT_TDM;
break;
default:
return -EINVAL;
}
if (format != old_format) {
if (twl4030->codec_powered) {
/*
* If the codec is powered, than we need to toggle the
* codec power.
*/
twl4030_codec_enable(component, 0);
twl4030_write(component, TWL4030_REG_AUDIO_IF, format);
twl4030_codec_enable(component, 1);
} else {
twl4030_write(component, TWL4030_REG_AUDIO_IF, format);
}
}
return 0;
}
static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
{
struct snd_soc_component *component = dai->component;
u8 reg = twl4030_read(component, TWL4030_REG_AUDIO_IF);
if (tristate)
reg |= TWL4030_AIF_TRI_EN;
else
reg &= ~TWL4030_AIF_TRI_EN;
return twl4030_write(component, TWL4030_REG_AUDIO_IF, reg);
}
/* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
* (VTXL, VTXR) for uplink has to be enabled/disabled. */
static void twl4030_voice_enable(struct snd_soc_component *component, int direction,
int enable)
{
u8 reg, mask;
reg = twl4030_read(component, TWL4030_REG_OPTION);
if (direction == SNDRV_PCM_STREAM_PLAYBACK)
mask = TWL4030_ARXL1_VRX_EN;
else
mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
if (enable)
reg |= mask;
else
reg &= ~mask;
twl4030_write(component, TWL4030_REG_OPTION, reg);
}
static int twl4030_voice_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
u8 mode;
/* If the system master clock is not 26MHz, the voice PCM interface is
* not available.
*/
if (twl4030->sysclk != 26000) {
dev_err(component->dev,
"%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n",
__func__, twl4030->sysclk);
return -EINVAL;
}
/* If the codec mode is not option2, the voice PCM interface is not
* available.
*/
mode = twl4030_read(component, TWL4030_REG_CODEC_MODE)
& TWL4030_OPT_MODE;
if (mode != TWL4030_OPTION_2) {
dev_err(component->dev, "%s: the codec mode is not option2\n",
__func__);
return -EINVAL;
}
return 0;
}
static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
/* Enable voice digital filters */
twl4030_voice_enable(component, substream->stream, 0);
}
static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
u8 old_mode, mode;
/* Enable voice digital filters */
twl4030_voice_enable(component, substream->stream, 1);
/* bit rate */
old_mode = twl4030_read(component,
TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
mode = old_mode;
switch (params_rate(params)) {
case 8000:
mode &= ~(TWL4030_SEL_16K);
break;
case 16000:
mode |= TWL4030_SEL_16K;
break;
default:
dev_err(component->dev, "%s: unknown rate %d\n", __func__,
params_rate(params));
return -EINVAL;
}
if (mode != old_mode) {
if (twl4030->codec_powered) {
/*
* If the codec is powered, than we need to toggle the
* codec power.
*/
twl4030_codec_enable(component, 0);
twl4030_write(component, TWL4030_REG_CODEC_MODE, mode);
twl4030_codec_enable(component, 1);
} else {
twl4030_write(component, TWL4030_REG_CODEC_MODE, mode);
}
}
return 0;
}
static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
if (freq != 26000000) {
dev_err(component->dev,
"%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n",
__func__, freq / 1000);
return -EINVAL;
}
if ((freq / 1000) != twl4030->sysclk) {
dev_err(component->dev,
"Mismatch in HFCLKIN: %u (configured: %u)\n",
freq, twl4030->sysclk * 1000);
return -EINVAL;
}
return 0;
}
static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
u8 old_format, format;
/* get format */
old_format = twl4030_read(component, TWL4030_REG_VOICE_IF);
format = old_format;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
format &= ~(TWL4030_VIF_SLAVE_EN);
break;
case SND_SOC_DAIFMT_CBS_CFS:
format |= TWL4030_VIF_SLAVE_EN;
break;
default:
return -EINVAL;
}
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_IB_NF:
format &= ~(TWL4030_VIF_FORMAT);
break;
case SND_SOC_DAIFMT_NB_IF:
format |= TWL4030_VIF_FORMAT;
break;
default:
return -EINVAL;
}
if (format != old_format) {
if (twl4030->codec_powered) {
/*
* If the codec is powered, than we need to toggle the
* codec power.
*/
twl4030_codec_enable(component, 0);
twl4030_write(component, TWL4030_REG_VOICE_IF, format);
twl4030_codec_enable(component, 1);
} else {
twl4030_write(component, TWL4030_REG_VOICE_IF, format);
}
}
return 0;
}
static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
{
struct snd_soc_component *component = dai->component;
u8 reg = twl4030_read(component, TWL4030_REG_VOICE_IF);
if (tristate)
reg |= TWL4030_VIF_TRI_EN;
else
reg &= ~TWL4030_VIF_TRI_EN;
return twl4030_write(component, TWL4030_REG_VOICE_IF, reg);
}
#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops twl4030_dai_hifi_ops = {
.startup = twl4030_startup,
.shutdown = twl4030_shutdown,
.hw_params = twl4030_hw_params,
.set_sysclk = twl4030_set_dai_sysclk,
.set_fmt = twl4030_set_dai_fmt,
.set_tristate = twl4030_set_tristate,
};
static const struct snd_soc_dai_ops twl4030_dai_voice_ops = {
.startup = twl4030_voice_startup,
.shutdown = twl4030_voice_shutdown,
.hw_params = twl4030_voice_hw_params,
.set_sysclk = twl4030_voice_set_dai_sysclk,
.set_fmt = twl4030_voice_set_dai_fmt,
.set_tristate = twl4030_voice_set_tristate,
};
static struct snd_soc_dai_driver twl4030_dai[] = {
{
.name = "twl4030-hifi",
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 2,
.channels_max = 4,
.rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
.formats = TWL4030_FORMATS,
.sig_bits = 24,},
.capture = {
.stream_name = "HiFi Capture",
.channels_min = 2,
.channels_max = 4,
.rates = TWL4030_RATES,
.formats = TWL4030_FORMATS,
.sig_bits = 24,},
.ops = &twl4030_dai_hifi_ops,
},
{
.name = "twl4030-voice",
.playback = {
.stream_name = "Voice Playback",
.channels_min = 1,
.channels_max = 1,
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,},
.capture = {
.stream_name = "Voice Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,},
.ops = &twl4030_dai_voice_ops,
},
};
static int twl4030_soc_probe(struct snd_soc_component *component)
{
struct twl4030_priv *twl4030;
twl4030 = devm_kzalloc(component->dev, sizeof(struct twl4030_priv),
GFP_KERNEL);
if (!twl4030)
return -ENOMEM;
snd_soc_component_set_drvdata(component, twl4030);
/* Set the defaults, and power up the codec */
twl4030->sysclk = twl4030_audio_get_mclk() / 1000;
twl4030_init_chip(component);
return 0;
}
static void twl4030_soc_remove(struct snd_soc_component *component)
{
struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
struct twl4030_board_params *board_params = twl4030->board_params;
if (board_params && board_params->hs_extmute &&
gpio_is_valid(board_params->hs_extmute_gpio))
gpio_free(board_params->hs_extmute_gpio);
}
static const struct snd_soc_component_driver soc_component_dev_twl4030 = {
.probe = twl4030_soc_probe,
.remove = twl4030_soc_remove,
.read = twl4030_read,
.write = twl4030_write,
.set_bias_level = twl4030_set_bias_level,
.controls = twl4030_snd_controls,
.num_controls = ARRAY_SIZE(twl4030_snd_controls),
.dapm_widgets = twl4030_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(twl4030_dapm_widgets),
.dapm_routes = intercon,
.num_dapm_routes = ARRAY_SIZE(intercon),
.use_pmdown_time = 1,
.endianness = 1,
};
static int twl4030_codec_probe(struct platform_device *pdev)
{
return devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_twl4030,
twl4030_dai, ARRAY_SIZE(twl4030_dai));
}
MODULE_ALIAS("platform:twl4030-codec");
static struct platform_driver twl4030_codec_driver = {
.probe = twl4030_codec_probe,
.driver = {
.name = "twl4030-codec",
},
};
module_platform_driver(twl4030_codec_driver);
MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
MODULE_AUTHOR("Steve Sakoman");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/twl4030.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// rt1316-sdw.c -- rt1316 SDCA ALSA SoC amplifier audio driver
//
// Copyright(c) 2021 Realtek Semiconductor Corp.
//
//
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/pm_runtime.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/sdw.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include "rt1316-sdw.h"
static const struct reg_default rt1316_reg_defaults[] = {
{ 0x3004, 0x00 },
{ 0x3005, 0x00 },
{ 0x3206, 0x00 },
{ 0xc001, 0x00 },
{ 0xc002, 0x00 },
{ 0xc003, 0x00 },
{ 0xc004, 0x00 },
{ 0xc005, 0x00 },
{ 0xc006, 0x00 },
{ 0xc007, 0x00 },
{ 0xc008, 0x00 },
{ 0xc009, 0x00 },
{ 0xc00a, 0x00 },
{ 0xc00b, 0x00 },
{ 0xc00c, 0x00 },
{ 0xc00d, 0x00 },
{ 0xc00e, 0x00 },
{ 0xc00f, 0x00 },
{ 0xc010, 0xa5 },
{ 0xc011, 0x00 },
{ 0xc012, 0xff },
{ 0xc013, 0xff },
{ 0xc014, 0x40 },
{ 0xc015, 0x00 },
{ 0xc016, 0x00 },
{ 0xc017, 0x00 },
{ 0xc605, 0x30 },
{ 0xc700, 0x0a },
{ 0xc701, 0xaa },
{ 0xc702, 0x1a },
{ 0xc703, 0x0a },
{ 0xc710, 0x80 },
{ 0xc711, 0x00 },
{ 0xc712, 0x3e },
{ 0xc713, 0x80 },
{ 0xc714, 0x80 },
{ 0xc715, 0x06 },
{ 0xd101, 0x00 },
{ 0xd102, 0x30 },
{ 0xd103, 0x00 },
{ SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_UDMPU21, RT1316_SDCA_CTL_UDMPU_CLUSTER, 0), 0x00 },
{ SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_L), 0x01 },
{ SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_R), 0x01 },
{ SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_XU24, RT1316_SDCA_CTL_BYPASS, 0), 0x01 },
{ SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23, RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
{ SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22, RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
{ SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24, RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
};
static const struct reg_sequence rt1316_blind_write[] = {
{ 0xc710, 0x17 },
{ 0xc711, 0x80 },
{ 0xc712, 0x26 },
{ 0xc713, 0x06 },
{ 0xc714, 0x80 },
{ 0xc715, 0x06 },
{ 0xc702, 0x0a },
{ 0xc703, 0x0a },
{ 0xc001, 0x45 },
{ 0xc003, 0x00 },
{ 0xc004, 0x11 },
{ 0xc005, 0x00 },
{ 0xc006, 0x00 },
{ 0xc106, 0x00 },
{ 0xc007, 0x11 },
{ 0xc008, 0x11 },
{ 0xc009, 0x00 },
{ 0x2f0a, 0x00 },
{ 0xd101, 0xf0 },
{ 0xd103, 0x9b },
{ 0x2f36, 0x8e },
{ 0x3206, 0x80 },
{ 0x3211, 0x0b },
{ 0x3216, 0x06 },
{ 0xc614, 0x20 },
{ 0xc615, 0x0a },
{ 0xc616, 0x02 },
{ 0xc617, 0x00 },
{ 0xc60b, 0x10 },
{ 0xc60e, 0x05 },
{ 0xc102, 0x00 },
{ 0xc090, 0xb0 },
{ 0xc00f, 0x01 },
{ 0xc09c, 0x7b },
{ 0xc602, 0x07 },
{ 0xc603, 0x07 },
{ 0xc0a3, 0x71 },
{ 0xc00b, 0x30 },
{ 0xc093, 0x80 },
{ 0xc09d, 0x80 },
{ 0xc0b0, 0x77 },
{ 0xc010, 0xa5 },
{ 0xc050, 0x83 },
{ 0x2f55, 0x03 },
{ 0x3217, 0xb5 },
{ 0x3202, 0x02 },
{ SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_XU24, RT1316_SDCA_CTL_BYPASS, 0), 0x00 },
/* for IV sense */
{ 0x2232, 0x80 },
{ 0xc0b0, 0x77 },
{ 0xc011, 0x00 },
{ 0xc020, 0x00 },
{ 0xc023, 0x00 },
{ 0x3101, 0x00 },
{ 0x3004, 0xa0 },
{ 0x3005, 0xb1 },
{ 0xc007, 0x11 },
{ 0xc008, 0x11 },
{ 0xc009, 0x00 },
{ 0xc022, 0xd6 },
{ 0xc025, 0xd6 },
{ 0xd001, 0x03 },
{ 0xd002, 0xbf },
{ 0xd003, 0x03 },
{ 0xd004, 0xbf },
};
static bool rt1316_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x2f0a:
case 0x2f36:
case 0x3203 ... 0x320e:
case 0xc000 ... 0xc7b4:
case 0xcf00 ... 0xcf03:
case 0xd101 ... 0xd103:
case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_UDMPU21, RT1316_SDCA_CTL_UDMPU_CLUSTER, 0):
case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_L):
case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_R):
case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23, RT1316_SDCA_CTL_REQ_POWER_STATE, 0):
case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE27, RT1316_SDCA_CTL_REQ_POWER_STATE, 0):
case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22, RT1316_SDCA_CTL_REQ_POWER_STATE, 0):
case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24, RT1316_SDCA_CTL_REQ_POWER_STATE, 0):
return true;
default:
return false;
}
}
static bool rt1316_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0xc000:
case 0xc093:
case 0xc09d:
case 0xc0a3:
case 0xc201:
case 0xc427 ... 0xc428:
case 0xd102:
return true;
default:
return false;
}
}
static const struct regmap_config rt1316_sdw_regmap = {
.reg_bits = 32,
.val_bits = 8,
.readable_reg = rt1316_readable_register,
.volatile_reg = rt1316_volatile_register,
.max_register = 0x4108ffff,
.reg_defaults = rt1316_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(rt1316_reg_defaults),
.cache_type = REGCACHE_MAPLE,
.use_single_read = true,
.use_single_write = true,
};
static int rt1316_read_prop(struct sdw_slave *slave)
{
struct sdw_slave_prop *prop = &slave->prop;
int nval;
int i, j;
u32 bit;
unsigned long addr;
struct sdw_dpn_prop *dpn;
prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
prop->paging_support = true;
/* first we need to allocate memory for set bits in port lists */
prop->source_ports = 0x04; /* BITMAP: 00000100 */
prop->sink_ports = 0x2; /* BITMAP: 00000010 */
nval = hweight32(prop->source_ports);
prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
sizeof(*prop->src_dpn_prop), GFP_KERNEL);
if (!prop->src_dpn_prop)
return -ENOMEM;
i = 0;
dpn = prop->src_dpn_prop;
addr = prop->source_ports;
for_each_set_bit(bit, &addr, 32) {
dpn[i].num = bit;
dpn[i].type = SDW_DPN_FULL;
dpn[i].simple_ch_prep_sm = true;
dpn[i].ch_prep_timeout = 10;
i++;
}
/* do this again for sink now */
nval = hweight32(prop->sink_ports);
prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
sizeof(*prop->sink_dpn_prop), GFP_KERNEL);
if (!prop->sink_dpn_prop)
return -ENOMEM;
j = 0;
dpn = prop->sink_dpn_prop;
addr = prop->sink_ports;
for_each_set_bit(bit, &addr, 32) {
dpn[j].num = bit;
dpn[j].type = SDW_DPN_FULL;
dpn[j].simple_ch_prep_sm = true;
dpn[j].ch_prep_timeout = 10;
j++;
}
/* set the timeout values */
prop->clk_stop_timeout = 20;
dev_dbg(&slave->dev, "%s\n", __func__);
return 0;
}
static void rt1316_apply_bq_params(struct rt1316_sdw_priv *rt1316)
{
unsigned int i, reg, data;
for (i = 0; i < rt1316->bq_params_cnt; i += 3) {
reg = rt1316->bq_params[i] | (rt1316->bq_params[i + 1] << 8);
data = rt1316->bq_params[i + 2];
regmap_write(rt1316->regmap, reg, data);
}
}
static int rt1316_io_init(struct device *dev, struct sdw_slave *slave)
{
struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(dev);
if (rt1316->hw_init)
return 0;
regcache_cache_only(rt1316->regmap, false);
if (rt1316->first_hw_init) {
regcache_cache_bypass(rt1316->regmap, true);
} else {
/*
* PM runtime status is marked as 'active' only when a Slave reports as Attached
*/
/* update count of parent 'active' children */
pm_runtime_set_active(&slave->dev);
}
pm_runtime_get_noresume(&slave->dev);
/* sw reset */
regmap_write(rt1316->regmap, 0xc000, 0x02);
/* initial settings - blind write */
regmap_multi_reg_write(rt1316->regmap, rt1316_blind_write,
ARRAY_SIZE(rt1316_blind_write));
if (rt1316->first_hw_init) {
regcache_cache_bypass(rt1316->regmap, false);
regcache_mark_dirty(rt1316->regmap);
} else
rt1316->first_hw_init = true;
/* Mark Slave initialization complete */
rt1316->hw_init = true;
pm_runtime_mark_last_busy(&slave->dev);
pm_runtime_put_autosuspend(&slave->dev);
dev_dbg(&slave->dev, "%s hw_init complete\n", __func__);
return 0;
}
static int rt1316_update_status(struct sdw_slave *slave,
enum sdw_slave_status status)
{
struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(&slave->dev);
if (status == SDW_SLAVE_UNATTACHED)
rt1316->hw_init = false;
/*
* Perform initialization only if slave status is present and
* hw_init flag is false
*/
if (rt1316->hw_init || status != SDW_SLAVE_ATTACHED)
return 0;
/* perform I/O transfers required for Slave initialization */
return rt1316_io_init(&slave->dev, slave);
}
static int rt1316_classd_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt1316_sdw_priv *rt1316 = snd_soc_component_get_drvdata(component);
unsigned char ps0 = 0x0, ps3 = 0x3;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_write(rt1316->regmap,
SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23,
RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
ps0);
regmap_write(rt1316->regmap,
SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE27,
RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
ps0);
regmap_write(rt1316->regmap,
SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22,
RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
ps0);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_write(rt1316->regmap,
SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23,
RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
ps3);
regmap_write(rt1316->regmap,
SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE27,
RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
ps3);
regmap_write(rt1316->regmap,
SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22,
RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
ps3);
break;
default:
break;
}
return 0;
}
static int rt1316_pde24_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt1316_sdw_priv *rt1316 = snd_soc_component_get_drvdata(component);
unsigned char ps0 = 0x0, ps3 = 0x3;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_write(rt1316->regmap,
SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24,
RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
ps0);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_write(rt1316->regmap,
SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24,
RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
ps3);
break;
}
return 0;
}
static const char * const rt1316_rx_data_ch_select[] = {
"L,R",
"L,L",
"L,R",
"L,L+R",
"R,L",
"R,R",
"R,L+R",
"L+R,L",
"L+R,R",
"L+R,L+R",
};
static SOC_ENUM_SINGLE_DECL(rt1316_rx_data_ch_enum,
SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_UDMPU21, RT1316_SDCA_CTL_UDMPU_CLUSTER, 0), 0,
rt1316_rx_data_ch_select);
static const char * const rt1316_dac_output_vol_select[] = {
"immediately",
"zero crossing",
"zero crossing with soft ramp",
};
static SOC_ENUM_SINGLE_DECL(rt1316_dac_vol_ctl_enum,
0xc010, 6, rt1316_dac_output_vol_select);
static const struct snd_kcontrol_new rt1316_snd_controls[] = {
/* I2S Data Channel Selection */
SOC_ENUM("RX Channel Select", rt1316_rx_data_ch_enum),
/* XU24 Bypass Control */
SOC_SINGLE("XU24 Bypass Switch",
SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_XU24, RT1316_SDCA_CTL_BYPASS, 0), 0, 1, 0),
/* Left/Right IV tag */
SOC_SINGLE("Left V Tag Select", 0x3004, 0, 7, 0),
SOC_SINGLE("Left I Tag Select", 0x3004, 4, 7, 0),
SOC_SINGLE("Right V Tag Select", 0x3005, 0, 7, 0),
SOC_SINGLE("Right I Tag Select", 0x3005, 4, 7, 0),
/* IV mixer Control */
SOC_DOUBLE("Isense Mixer Switch", 0xc605, 2, 0, 1, 1),
SOC_DOUBLE("Vsense Mixer Switch", 0xc605, 3, 1, 1, 1),
/* DAC Output Volume Control */
SOC_ENUM("DAC Output Vol Control", rt1316_dac_vol_ctl_enum),
};
static const struct snd_kcontrol_new rt1316_sto_dac =
SOC_DAPM_DOUBLE_R("Switch",
SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_L),
SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_R),
0, 1, 1);
static const struct snd_soc_dapm_widget rt1316_dapm_widgets[] = {
/* Audio Interface */
SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("DP2TX", "DP2 Capture", 0, SND_SOC_NOPM, 0, 0),
/* Digital Interface */
SND_SOC_DAPM_SWITCH("DAC", SND_SOC_NOPM, 0, 0, &rt1316_sto_dac),
/* Output Lines */
SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
rt1316_classd_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_OUTPUT("SPOL"),
SND_SOC_DAPM_OUTPUT("SPOR"),
SND_SOC_DAPM_SUPPLY("PDE 24", SND_SOC_NOPM, 0, 0,
rt1316_pde24_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA("I Sense", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("V Sense", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SIGGEN("I Gen"),
SND_SOC_DAPM_SIGGEN("V Gen"),
};
static const struct snd_soc_dapm_route rt1316_dapm_routes[] = {
{ "DAC", "Switch", "DP1RX" },
{ "CLASS D", NULL, "DAC" },
{ "SPOL", NULL, "CLASS D" },
{ "SPOR", NULL, "CLASS D" },
{ "I Sense", NULL, "I Gen" },
{ "V Sense", NULL, "V Gen" },
{ "I Sense", NULL, "PDE 24" },
{ "V Sense", NULL, "PDE 24" },
{ "DP2TX", NULL, "I Sense" },
{ "DP2TX", NULL, "V Sense" },
};
static int rt1316_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
int direction)
{
snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
return 0;
}
static void rt1316_sdw_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
snd_soc_dai_set_dma_data(dai, substream, NULL);
}
static int rt1316_sdw_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt1316_sdw_priv *rt1316 =
snd_soc_component_get_drvdata(component);
struct sdw_stream_config stream_config = {0};
struct sdw_port_config port_config = {0};
struct sdw_stream_runtime *sdw_stream;
int retval;
dev_dbg(dai->dev, "%s %s", __func__, dai->name);
sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
if (!sdw_stream)
return -EINVAL;
if (!rt1316->sdw_slave)
return -EINVAL;
/* SoundWire specific configuration */
snd_sdw_params_to_config(substream, params, &stream_config, &port_config);
/* port 1 for playback */
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
port_config.num = 1;
else
port_config.num = 2;
retval = sdw_stream_add_slave(rt1316->sdw_slave, &stream_config,
&port_config, 1, sdw_stream);
if (retval) {
dev_err(dai->dev, "Unable to configure port\n");
return retval;
}
return 0;
}
static int rt1316_sdw_pcm_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt1316_sdw_priv *rt1316 =
snd_soc_component_get_drvdata(component);
struct sdw_stream_runtime *sdw_stream =
snd_soc_dai_get_dma_data(dai, substream);
if (!rt1316->sdw_slave)
return -EINVAL;
sdw_stream_remove_slave(rt1316->sdw_slave, sdw_stream);
return 0;
}
/*
* slave_ops: callbacks for get_clock_stop_mode, clock_stop and
* port_prep are not defined for now
*/
static const struct sdw_slave_ops rt1316_slave_ops = {
.read_prop = rt1316_read_prop,
.update_status = rt1316_update_status,
};
static int rt1316_sdw_parse_dt(struct rt1316_sdw_priv *rt1316, struct device *dev)
{
int ret = 0;
device_property_read_u32(dev, "realtek,bq-params-cnt", &rt1316->bq_params_cnt);
if (rt1316->bq_params_cnt) {
rt1316->bq_params = devm_kzalloc(dev, rt1316->bq_params_cnt, GFP_KERNEL);
if (!rt1316->bq_params) {
dev_err(dev, "Could not allocate bq_params memory\n");
ret = -ENOMEM;
} else {
ret = device_property_read_u8_array(dev, "realtek,bq-params", rt1316->bq_params, rt1316->bq_params_cnt);
if (ret < 0)
dev_err(dev, "Could not read list of realtek,bq-params\n");
}
}
dev_dbg(dev, "bq_params_cnt=%d\n", rt1316->bq_params_cnt);
return ret;
}
static int rt1316_sdw_component_probe(struct snd_soc_component *component)
{
struct rt1316_sdw_priv *rt1316 = snd_soc_component_get_drvdata(component);
int ret;
rt1316->component = component;
rt1316_sdw_parse_dt(rt1316, &rt1316->sdw_slave->dev);
if (!rt1316->first_hw_init)
return 0;
ret = pm_runtime_resume(component->dev);
if (ret < 0 && ret != -EACCES)
return ret;
/* apply BQ params */
rt1316_apply_bq_params(rt1316);
return 0;
}
static const struct snd_soc_component_driver soc_component_sdw_rt1316 = {
.probe = rt1316_sdw_component_probe,
.controls = rt1316_snd_controls,
.num_controls = ARRAY_SIZE(rt1316_snd_controls),
.dapm_widgets = rt1316_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt1316_dapm_widgets),
.dapm_routes = rt1316_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(rt1316_dapm_routes),
.endianness = 1,
};
static const struct snd_soc_dai_ops rt1316_aif_dai_ops = {
.hw_params = rt1316_sdw_hw_params,
.hw_free = rt1316_sdw_pcm_hw_free,
.set_stream = rt1316_set_sdw_stream,
.shutdown = rt1316_sdw_shutdown,
};
#define RT1316_STEREO_RATES SNDRV_PCM_RATE_48000
#define RT1316_FORMATS (SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE)
static struct snd_soc_dai_driver rt1316_sdw_dai[] = {
{
.name = "rt1316-aif",
.playback = {
.stream_name = "DP1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT1316_STEREO_RATES,
.formats = RT1316_FORMATS,
},
.capture = {
.stream_name = "DP2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT1316_STEREO_RATES,
.formats = RT1316_FORMATS,
},
.ops = &rt1316_aif_dai_ops,
},
};
static int rt1316_sdw_init(struct device *dev, struct regmap *regmap,
struct sdw_slave *slave)
{
struct rt1316_sdw_priv *rt1316;
int ret;
rt1316 = devm_kzalloc(dev, sizeof(*rt1316), GFP_KERNEL);
if (!rt1316)
return -ENOMEM;
dev_set_drvdata(dev, rt1316);
rt1316->sdw_slave = slave;
rt1316->regmap = regmap;
regcache_cache_only(rt1316->regmap, true);
/*
* Mark hw_init to false
* HW init will be performed when device reports present
*/
rt1316->hw_init = false;
rt1316->first_hw_init = false;
ret = devm_snd_soc_register_component(dev,
&soc_component_sdw_rt1316,
rt1316_sdw_dai,
ARRAY_SIZE(rt1316_sdw_dai));
if (ret < 0)
return ret;
/* set autosuspend parameters */
pm_runtime_set_autosuspend_delay(dev, 3000);
pm_runtime_use_autosuspend(dev);
/* make sure the device does not suspend immediately */
pm_runtime_mark_last_busy(dev);
pm_runtime_enable(dev);
/* important note: the device is NOT tagged as 'active' and will remain
* 'suspended' until the hardware is enumerated/initialized. This is required
* to make sure the ASoC framework use of pm_runtime_get_sync() does not silently
* fail with -EACCESS because of race conditions between card creation and enumeration
*/
dev_dbg(dev, "%s\n", __func__);
return 0;
}
static int rt1316_sdw_probe(struct sdw_slave *slave,
const struct sdw_device_id *id)
{
struct regmap *regmap;
/* Regmap Initialization */
regmap = devm_regmap_init_sdw(slave, &rt1316_sdw_regmap);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return rt1316_sdw_init(&slave->dev, regmap, slave);
}
static int rt1316_sdw_remove(struct sdw_slave *slave)
{
pm_runtime_disable(&slave->dev);
return 0;
}
static const struct sdw_device_id rt1316_id[] = {
SDW_SLAVE_ENTRY_EXT(0x025d, 0x1316, 0x3, 0x1, 0),
{},
};
MODULE_DEVICE_TABLE(sdw, rt1316_id);
static int __maybe_unused rt1316_dev_suspend(struct device *dev)
{
struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(dev);
if (!rt1316->hw_init)
return 0;
regcache_cache_only(rt1316->regmap, true);
return 0;
}
#define RT1316_PROBE_TIMEOUT 5000
static int __maybe_unused rt1316_dev_resume(struct device *dev)
{
struct sdw_slave *slave = dev_to_sdw_dev(dev);
struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(dev);
unsigned long time;
if (!rt1316->first_hw_init)
return 0;
if (!slave->unattach_request)
goto regmap_sync;
time = wait_for_completion_timeout(&slave->initialization_complete,
msecs_to_jiffies(RT1316_PROBE_TIMEOUT));
if (!time) {
dev_err(&slave->dev, "Initialization not complete, timed out\n");
sdw_show_ping_status(slave->bus, true);
return -ETIMEDOUT;
}
regmap_sync:
slave->unattach_request = 0;
regcache_cache_only(rt1316->regmap, false);
regcache_sync(rt1316->regmap);
return 0;
}
static const struct dev_pm_ops rt1316_pm = {
SET_SYSTEM_SLEEP_PM_OPS(rt1316_dev_suspend, rt1316_dev_resume)
SET_RUNTIME_PM_OPS(rt1316_dev_suspend, rt1316_dev_resume, NULL)
};
static struct sdw_driver rt1316_sdw_driver = {
.driver = {
.name = "rt1316-sdca",
.owner = THIS_MODULE,
.pm = &rt1316_pm,
},
.probe = rt1316_sdw_probe,
.remove = rt1316_sdw_remove,
.ops = &rt1316_slave_ops,
.id_table = rt1316_id,
};
module_sdw_driver(rt1316_sdw_driver);
MODULE_DESCRIPTION("ASoC RT1316 driver SDCA SDW");
MODULE_AUTHOR("Shuming Fan <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/rt1316-sdw.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* rl6231.c - RL6231 class device shared support
*
* Copyright 2014 Realtek Semiconductor Corp.
*
* Author: Oder Chiou <[email protected]>
*/
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/gcd.h>
#include "rl6231.h"
/**
* rl6231_get_pre_div - Return the value of pre divider.
*
* @map: map for setting.
* @reg: register.
* @sft: shift.
*
* Return the value of pre divider from given register value.
* Return negative error code for unexpected register value.
*/
int rl6231_get_pre_div(struct regmap *map, unsigned int reg, int sft)
{
int pd, val;
regmap_read(map, reg, &val);
val = (val >> sft) & 0x7;
switch (val) {
case 0:
case 1:
case 2:
case 3:
pd = val + 1;
break;
case 4:
pd = 6;
break;
case 5:
pd = 8;
break;
case 6:
pd = 12;
break;
case 7:
pd = 16;
break;
default:
pd = -EINVAL;
break;
}
return pd;
}
EXPORT_SYMBOL_GPL(rl6231_get_pre_div);
/**
* rl6231_calc_dmic_clk - Calculate the frequency divider parameter of dmic.
*
* @rate: base clock rate.
*
* Choose divider parameter that gives the highest possible DMIC frequency in
* 1MHz - 3MHz range.
*/
int rl6231_calc_dmic_clk(int rate)
{
static const int div[] = {2, 3, 4, 6, 8, 12};
int i;
if (rate < 1000000 * div[0]) {
pr_warn("Base clock rate %d is too low\n", rate);
return -EINVAL;
}
for (i = 0; i < ARRAY_SIZE(div); i++) {
if ((div[i] % 3) == 0)
continue;
/* find divider that gives DMIC frequency below 1.536MHz */
if (1536000 * div[i] >= rate)
return i;
}
pr_warn("Base clock rate %d is too high\n", rate);
return -EINVAL;
}
EXPORT_SYMBOL_GPL(rl6231_calc_dmic_clk);
struct pll_calc_map {
unsigned int pll_in;
unsigned int pll_out;
int k;
int n;
int m;
bool m_bp;
bool k_bp;
};
static const struct pll_calc_map pll_preset_table[] = {
{19200000, 4096000, 23, 14, 1, false, false},
{19200000, 24576000, 3, 30, 3, false, false},
{48000000, 3840000, 23, 2, 0, false, false},
{3840000, 24576000, 3, 30, 0, true, false},
{3840000, 22579200, 3, 5, 0, true, false},
};
static unsigned int find_best_div(unsigned int in,
unsigned int max, unsigned int div)
{
unsigned int d;
if (in <= max)
return 1;
d = in / max;
if (in % max)
d++;
while (div % d != 0)
d++;
return d;
}
/**
* rl6231_pll_calc - Calcualte PLL M/N/K code.
* @freq_in: external clock provided to codec.
* @freq_out: target clock which codec works on.
* @pll_code: Pointer to structure with M, N, K, m_bypass and k_bypass flag.
*
* Calcualte M/N/K code to configure PLL for codec.
*
* Returns 0 for success or negative error code.
*/
int rl6231_pll_calc(const unsigned int freq_in,
const unsigned int freq_out, struct rl6231_pll_code *pll_code)
{
int max_n = RL6231_PLL_N_MAX, max_m = RL6231_PLL_M_MAX;
int i, k, n_t;
int k_t, min_k, max_k, n = 0, m = 0, m_t = 0;
unsigned int red, pll_out, in_t, out_t, div, div_t;
unsigned int red_t = abs(freq_out - freq_in);
unsigned int f_in, f_out, f_max;
bool m_bypass = false, k_bypass = false;
if (RL6231_PLL_INP_MAX < freq_in || RL6231_PLL_INP_MIN > freq_in)
return -EINVAL;
for (i = 0; i < ARRAY_SIZE(pll_preset_table); i++) {
if (freq_in == pll_preset_table[i].pll_in &&
freq_out == pll_preset_table[i].pll_out) {
k = pll_preset_table[i].k;
m = pll_preset_table[i].m;
n = pll_preset_table[i].n;
m_bypass = pll_preset_table[i].m_bp;
k_bypass = pll_preset_table[i].k_bp;
pr_debug("Use preset PLL parameter table\n");
goto code_find;
}
}
min_k = 80000000 / freq_out - 2;
max_k = 150000000 / freq_out - 2;
if (max_k > RL6231_PLL_K_MAX)
max_k = RL6231_PLL_K_MAX;
if (min_k > RL6231_PLL_K_MAX)
min_k = max_k = RL6231_PLL_K_MAX;
div_t = gcd(freq_in, freq_out);
f_max = 0xffffffff / RL6231_PLL_N_MAX;
div = find_best_div(freq_in, f_max, div_t);
f_in = freq_in / div;
f_out = freq_out / div;
k = min_k;
if (min_k < -1)
min_k = -1;
for (k_t = min_k; k_t <= max_k; k_t++) {
for (n_t = 0; n_t <= max_n; n_t++) {
in_t = f_in * (n_t + 2);
pll_out = f_out * (k_t + 2);
if (in_t == pll_out) {
m_bypass = true;
n = n_t;
k = k_t;
goto code_find;
}
out_t = in_t / (k_t + 2);
red = abs(f_out - out_t);
if (red < red_t) {
m_bypass = true;
n = n_t;
m = 0;
k = k_t;
if (red == 0)
goto code_find;
red_t = red;
}
for (m_t = 0; m_t <= max_m; m_t++) {
out_t = in_t / ((m_t + 2) * (k_t + 2));
red = abs(f_out - out_t);
if (red < red_t) {
m_bypass = false;
n = n_t;
m = m_t;
k = k_t;
if (red == 0)
goto code_find;
red_t = red;
}
}
}
}
pr_debug("Only get approximation about PLL\n");
code_find:
if (k == -1) {
k_bypass = true;
k = 0;
}
pll_code->m_bp = m_bypass;
pll_code->k_bp = k_bypass;
pll_code->m_code = m;
pll_code->n_code = n;
pll_code->k_code = k;
return 0;
}
EXPORT_SYMBOL_GPL(rl6231_pll_calc);
int rl6231_get_clk_info(int sclk, int rate)
{
int i;
static const int pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
if (sclk <= 0 || rate <= 0)
return -EINVAL;
rate = rate << 8;
for (i = 0; i < ARRAY_SIZE(pd); i++)
if (sclk == rate * pd[i])
return i;
return -EINVAL;
}
EXPORT_SYMBOL_GPL(rl6231_get_clk_info);
MODULE_DESCRIPTION("RL6231 class device shared support");
MODULE_AUTHOR("Oder Chiou <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/rl6231.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* This is a simple driver for the GTM601 Voice PCM interface
*
* Copyright (C) 2015 Goldelico GmbH
*
* Author: Marek Belisko <[email protected]>
*
* Based on wm8727.c driver
*/
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/of_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/initval.h>
#include <sound/soc.h>
static const struct snd_soc_dapm_widget gtm601_dapm_widgets[] = {
SND_SOC_DAPM_OUTPUT("AOUT"),
SND_SOC_DAPM_INPUT("AIN"),
};
static const struct snd_soc_dapm_route gtm601_dapm_routes[] = {
{ "AOUT", NULL, "Playback" },
{ "Capture", NULL, "AIN" },
};
static struct snd_soc_dai_driver gtm601_dai = {
.name = "gtm601",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 1,
.rates = SNDRV_PCM_RATE_8000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 1,
.rates = SNDRV_PCM_RATE_8000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
};
static struct snd_soc_dai_driver bm818_dai = {
.name = "bm818",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
};
static const struct snd_soc_component_driver soc_component_dev_gtm601 = {
.dapm_widgets = gtm601_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(gtm601_dapm_widgets),
.dapm_routes = gtm601_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(gtm601_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int gtm601_platform_probe(struct platform_device *pdev)
{
const struct snd_soc_dai_driver *dai_driver;
dai_driver = of_device_get_match_data(&pdev->dev);
return devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_gtm601,
(struct snd_soc_dai_driver *)dai_driver, 1);
}
static const struct of_device_id gtm601_codec_of_match[] __maybe_unused = {
{ .compatible = "option,gtm601", .data = (void *)>m601_dai },
{ .compatible = "broadmobi,bm818", .data = (void *)&bm818_dai },
{},
};
MODULE_DEVICE_TABLE(of, gtm601_codec_of_match);
static struct platform_driver gtm601_codec_driver = {
.driver = {
.name = "gtm601",
.of_match_table = of_match_ptr(gtm601_codec_of_match),
},
.probe = gtm601_platform_probe,
};
module_platform_driver(gtm601_codec_driver);
MODULE_DESCRIPTION("ASoC gtm601 driver");
MODULE_AUTHOR("Marek Belisko <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:gtm601");
| linux-master | sound/soc/codecs/gtm601.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* rt5677.c -- RT5677 ALSA SoC audio codec driver
*
* Copyright 2013 Realtek Semiconductor Corp.
* Author: Oder Chiou <[email protected]>
*/
#include <linux/delay.h>
#include <linux/firmware.h>
#include <linux/fs.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include <linux/workqueue.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "rl6231.h"
#include "rt5677.h"
#include "rt5677-spi.h"
#define RT5677_DEVICE_ID 0x6327
/* Register controlling boot vector */
#define RT5677_DSP_BOOT_VECTOR 0x1801f090
#define RT5677_MODEL_ADDR 0x5FFC9800
#define RT5677_PR_RANGE_BASE (0xff + 1)
#define RT5677_PR_SPACING 0x100
#define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
static const struct regmap_range_cfg rt5677_ranges[] = {
{
.name = "PR",
.range_min = RT5677_PR_BASE,
.range_max = RT5677_PR_BASE + 0xfd,
.selector_reg = RT5677_PRIV_INDEX,
.selector_mask = 0xff,
.selector_shift = 0x0,
.window_start = RT5677_PRIV_DATA,
.window_len = 0x1,
},
};
static const struct reg_sequence init_list[] = {
{RT5677_ASRC_12, 0x0018},
{RT5677_PR_BASE + 0x3d, 0x364d},
{RT5677_PR_BASE + 0x17, 0x4fc0},
{RT5677_PR_BASE + 0x13, 0x0312},
{RT5677_PR_BASE + 0x1e, 0x0000},
{RT5677_PR_BASE + 0x12, 0x0eaa},
{RT5677_PR_BASE + 0x14, 0x018a},
{RT5677_PR_BASE + 0x15, 0x0490},
{RT5677_PR_BASE + 0x38, 0x0f71},
{RT5677_PR_BASE + 0x39, 0x0f71},
};
#define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
static const struct reg_default rt5677_reg[] = {
{RT5677_RESET , 0x0000},
{RT5677_LOUT1 , 0xa800},
{RT5677_IN1 , 0x0000},
{RT5677_MICBIAS , 0x0000},
{RT5677_SLIMBUS_PARAM , 0x0000},
{RT5677_SLIMBUS_RX , 0x0000},
{RT5677_SLIMBUS_CTRL , 0x0000},
{RT5677_SIDETONE_CTRL , 0x000b},
{RT5677_ANA_DAC1_2_3_SRC , 0x0000},
{RT5677_IF_DSP_DAC3_4_MIXER , 0x1111},
{RT5677_DAC4_DIG_VOL , 0xafaf},
{RT5677_DAC3_DIG_VOL , 0xafaf},
{RT5677_DAC1_DIG_VOL , 0xafaf},
{RT5677_DAC2_DIG_VOL , 0xafaf},
{RT5677_IF_DSP_DAC2_MIXER , 0x0011},
{RT5677_STO1_ADC_DIG_VOL , 0x2f2f},
{RT5677_MONO_ADC_DIG_VOL , 0x2f2f},
{RT5677_STO1_2_ADC_BST , 0x0000},
{RT5677_STO2_ADC_DIG_VOL , 0x2f2f},
{RT5677_ADC_BST_CTRL2 , 0x0000},
{RT5677_STO3_4_ADC_BST , 0x0000},
{RT5677_STO3_ADC_DIG_VOL , 0x2f2f},
{RT5677_STO4_ADC_DIG_VOL , 0x2f2f},
{RT5677_STO4_ADC_MIXER , 0xd4c0},
{RT5677_STO3_ADC_MIXER , 0xd4c0},
{RT5677_STO2_ADC_MIXER , 0xd4c0},
{RT5677_STO1_ADC_MIXER , 0xd4c0},
{RT5677_MONO_ADC_MIXER , 0xd4d1},
{RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080},
{RT5677_STO1_DAC_MIXER , 0xaaaa},
{RT5677_MONO_DAC_MIXER , 0xaaaa},
{RT5677_DD1_MIXER , 0xaaaa},
{RT5677_DD2_MIXER , 0xaaaa},
{RT5677_IF3_DATA , 0x0000},
{RT5677_IF4_DATA , 0x0000},
{RT5677_PDM_OUT_CTRL , 0x8888},
{RT5677_PDM_DATA_CTRL1 , 0x0000},
{RT5677_PDM_DATA_CTRL2 , 0x0000},
{RT5677_PDM1_DATA_CTRL2 , 0x0000},
{RT5677_PDM1_DATA_CTRL3 , 0x0000},
{RT5677_PDM1_DATA_CTRL4 , 0x0000},
{RT5677_PDM2_DATA_CTRL2 , 0x0000},
{RT5677_PDM2_DATA_CTRL3 , 0x0000},
{RT5677_PDM2_DATA_CTRL4 , 0x0000},
{RT5677_TDM1_CTRL1 , 0x0300},
{RT5677_TDM1_CTRL2 , 0x0000},
{RT5677_TDM1_CTRL3 , 0x4000},
{RT5677_TDM1_CTRL4 , 0x0123},
{RT5677_TDM1_CTRL5 , 0x4567},
{RT5677_TDM2_CTRL1 , 0x0300},
{RT5677_TDM2_CTRL2 , 0x0000},
{RT5677_TDM2_CTRL3 , 0x4000},
{RT5677_TDM2_CTRL4 , 0x0123},
{RT5677_TDM2_CTRL5 , 0x4567},
{RT5677_I2C_MASTER_CTRL1 , 0x0001},
{RT5677_I2C_MASTER_CTRL2 , 0x0000},
{RT5677_I2C_MASTER_CTRL3 , 0x0000},
{RT5677_I2C_MASTER_CTRL4 , 0x0000},
{RT5677_I2C_MASTER_CTRL5 , 0x0000},
{RT5677_I2C_MASTER_CTRL6 , 0x0000},
{RT5677_I2C_MASTER_CTRL7 , 0x0000},
{RT5677_I2C_MASTER_CTRL8 , 0x0000},
{RT5677_DMIC_CTRL1 , 0x1505},
{RT5677_DMIC_CTRL2 , 0x0055},
{RT5677_HAP_GENE_CTRL1 , 0x0111},
{RT5677_HAP_GENE_CTRL2 , 0x0064},
{RT5677_HAP_GENE_CTRL3 , 0xef0e},
{RT5677_HAP_GENE_CTRL4 , 0xf0f0},
{RT5677_HAP_GENE_CTRL5 , 0xef0e},
{RT5677_HAP_GENE_CTRL6 , 0xf0f0},
{RT5677_HAP_GENE_CTRL7 , 0xef0e},
{RT5677_HAP_GENE_CTRL8 , 0xf0f0},
{RT5677_HAP_GENE_CTRL9 , 0xf000},
{RT5677_HAP_GENE_CTRL10 , 0x0000},
{RT5677_PWR_DIG1 , 0x0000},
{RT5677_PWR_DIG2 , 0x0000},
{RT5677_PWR_ANLG1 , 0x0055},
{RT5677_PWR_ANLG2 , 0x0000},
{RT5677_PWR_DSP1 , 0x0001},
{RT5677_PWR_DSP_ST , 0x0000},
{RT5677_PWR_DSP2 , 0x0000},
{RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00},
{RT5677_PRIV_INDEX , 0x0000},
{RT5677_PRIV_DATA , 0x0000},
{RT5677_I2S4_SDP , 0x8000},
{RT5677_I2S1_SDP , 0x8000},
{RT5677_I2S2_SDP , 0x8000},
{RT5677_I2S3_SDP , 0x8000},
{RT5677_CLK_TREE_CTRL1 , 0x1111},
{RT5677_CLK_TREE_CTRL2 , 0x1111},
{RT5677_CLK_TREE_CTRL3 , 0x0000},
{RT5677_PLL1_CTRL1 , 0x0000},
{RT5677_PLL1_CTRL2 , 0x0000},
{RT5677_PLL2_CTRL1 , 0x0c60},
{RT5677_PLL2_CTRL2 , 0x2000},
{RT5677_GLB_CLK1 , 0x0000},
{RT5677_GLB_CLK2 , 0x0000},
{RT5677_ASRC_1 , 0x0000},
{RT5677_ASRC_2 , 0x0000},
{RT5677_ASRC_3 , 0x0000},
{RT5677_ASRC_4 , 0x0000},
{RT5677_ASRC_5 , 0x0000},
{RT5677_ASRC_6 , 0x0000},
{RT5677_ASRC_7 , 0x0000},
{RT5677_ASRC_8 , 0x0000},
{RT5677_ASRC_9 , 0x0000},
{RT5677_ASRC_10 , 0x0000},
{RT5677_ASRC_11 , 0x0000},
{RT5677_ASRC_12 , 0x0018},
{RT5677_ASRC_13 , 0x0000},
{RT5677_ASRC_14 , 0x0000},
{RT5677_ASRC_15 , 0x0000},
{RT5677_ASRC_16 , 0x0000},
{RT5677_ASRC_17 , 0x0000},
{RT5677_ASRC_18 , 0x0000},
{RT5677_ASRC_19 , 0x0000},
{RT5677_ASRC_20 , 0x0000},
{RT5677_ASRC_21 , 0x000c},
{RT5677_ASRC_22 , 0x0000},
{RT5677_ASRC_23 , 0x0000},
{RT5677_VAD_CTRL1 , 0x2184},
{RT5677_VAD_CTRL2 , 0x010a},
{RT5677_VAD_CTRL3 , 0x0aea},
{RT5677_VAD_CTRL4 , 0x000c},
{RT5677_VAD_CTRL5 , 0x0000},
{RT5677_DSP_INB_CTRL1 , 0x0000},
{RT5677_DSP_INB_CTRL2 , 0x0000},
{RT5677_DSP_IN_OUTB_CTRL , 0x0000},
{RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f},
{RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f},
{RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f},
{RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f},
{RT5677_ADC_EQ_CTRL1 , 0x6000},
{RT5677_ADC_EQ_CTRL2 , 0x0000},
{RT5677_EQ_CTRL1 , 0xc000},
{RT5677_EQ_CTRL2 , 0x0000},
{RT5677_EQ_CTRL3 , 0x0000},
{RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009},
{RT5677_JD_CTRL1 , 0x0000},
{RT5677_JD_CTRL2 , 0x0000},
{RT5677_JD_CTRL3 , 0x0000},
{RT5677_IRQ_CTRL1 , 0x0000},
{RT5677_IRQ_CTRL2 , 0x0000},
{RT5677_GPIO_ST , 0x0000},
{RT5677_GPIO_CTRL1 , 0x0000},
{RT5677_GPIO_CTRL2 , 0x0000},
{RT5677_GPIO_CTRL3 , 0x0000},
{RT5677_STO1_ADC_HI_FILTER1 , 0xb320},
{RT5677_STO1_ADC_HI_FILTER2 , 0x0000},
{RT5677_MONO_ADC_HI_FILTER1 , 0xb300},
{RT5677_MONO_ADC_HI_FILTER2 , 0x0000},
{RT5677_STO2_ADC_HI_FILTER1 , 0xb300},
{RT5677_STO2_ADC_HI_FILTER2 , 0x0000},
{RT5677_STO3_ADC_HI_FILTER1 , 0xb300},
{RT5677_STO3_ADC_HI_FILTER2 , 0x0000},
{RT5677_STO4_ADC_HI_FILTER1 , 0xb300},
{RT5677_STO4_ADC_HI_FILTER2 , 0x0000},
{RT5677_MB_DRC_CTRL1 , 0x0f20},
{RT5677_DRC1_CTRL1 , 0x001f},
{RT5677_DRC1_CTRL2 , 0x020c},
{RT5677_DRC1_CTRL3 , 0x1f00},
{RT5677_DRC1_CTRL4 , 0x0000},
{RT5677_DRC1_CTRL5 , 0x0000},
{RT5677_DRC1_CTRL6 , 0x0029},
{RT5677_DRC2_CTRL1 , 0x001f},
{RT5677_DRC2_CTRL2 , 0x020c},
{RT5677_DRC2_CTRL3 , 0x1f00},
{RT5677_DRC2_CTRL4 , 0x0000},
{RT5677_DRC2_CTRL5 , 0x0000},
{RT5677_DRC2_CTRL6 , 0x0029},
{RT5677_DRC1_HL_CTRL1 , 0x8000},
{RT5677_DRC1_HL_CTRL2 , 0x0200},
{RT5677_DRC2_HL_CTRL1 , 0x8000},
{RT5677_DRC2_HL_CTRL2 , 0x0200},
{RT5677_DSP_INB1_SRC_CTRL1 , 0x5800},
{RT5677_DSP_INB1_SRC_CTRL2 , 0x0000},
{RT5677_DSP_INB1_SRC_CTRL3 , 0x0000},
{RT5677_DSP_INB1_SRC_CTRL4 , 0x0800},
{RT5677_DSP_INB2_SRC_CTRL1 , 0x5800},
{RT5677_DSP_INB2_SRC_CTRL2 , 0x0000},
{RT5677_DSP_INB2_SRC_CTRL3 , 0x0000},
{RT5677_DSP_INB2_SRC_CTRL4 , 0x0800},
{RT5677_DSP_INB3_SRC_CTRL1 , 0x5800},
{RT5677_DSP_INB3_SRC_CTRL2 , 0x0000},
{RT5677_DSP_INB3_SRC_CTRL3 , 0x0000},
{RT5677_DSP_INB3_SRC_CTRL4 , 0x0800},
{RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800},
{RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000},
{RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000},
{RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800},
{RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800},
{RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000},
{RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000},
{RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800},
{RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
{RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe},
{RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe},
{RT5677_DIG_MISC , 0x0000},
{RT5677_GEN_CTRL1 , 0x0000},
{RT5677_GEN_CTRL2 , 0x0000},
{RT5677_VENDOR_ID , 0x0000},
{RT5677_VENDOR_ID1 , 0x10ec},
{RT5677_VENDOR_ID2 , 0x6327},
};
static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
{
int i;
for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
if (reg >= rt5677_ranges[i].range_min &&
reg <= rt5677_ranges[i].range_max) {
return true;
}
}
switch (reg) {
case RT5677_RESET:
case RT5677_SLIMBUS_PARAM:
case RT5677_PDM_DATA_CTRL1:
case RT5677_PDM_DATA_CTRL2:
case RT5677_PDM1_DATA_CTRL4:
case RT5677_PDM2_DATA_CTRL4:
case RT5677_I2C_MASTER_CTRL1:
case RT5677_I2C_MASTER_CTRL7:
case RT5677_I2C_MASTER_CTRL8:
case RT5677_HAP_GENE_CTRL2:
case RT5677_PWR_ANLG2: /* Modified by DSP firmware */
case RT5677_PWR_DSP_ST:
case RT5677_PRIV_DATA:
case RT5677_ASRC_22:
case RT5677_ASRC_23:
case RT5677_VAD_CTRL5:
case RT5677_ADC_EQ_CTRL1:
case RT5677_EQ_CTRL1:
case RT5677_IRQ_CTRL1:
case RT5677_IRQ_CTRL2:
case RT5677_GPIO_ST:
case RT5677_GPIO_CTRL1: /* Modified by DSP firmware */
case RT5677_GPIO_CTRL2: /* Modified by DSP firmware */
case RT5677_DSP_INB1_SRC_CTRL4:
case RT5677_DSP_INB2_SRC_CTRL4:
case RT5677_DSP_INB3_SRC_CTRL4:
case RT5677_DSP_OUTB1_SRC_CTRL4:
case RT5677_DSP_OUTB2_SRC_CTRL4:
case RT5677_VENDOR_ID:
case RT5677_VENDOR_ID1:
case RT5677_VENDOR_ID2:
return true;
default:
return false;
}
}
static bool rt5677_readable_register(struct device *dev, unsigned int reg)
{
int i;
for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
if (reg >= rt5677_ranges[i].range_min &&
reg <= rt5677_ranges[i].range_max) {
return true;
}
}
switch (reg) {
case RT5677_RESET:
case RT5677_LOUT1:
case RT5677_IN1:
case RT5677_MICBIAS:
case RT5677_SLIMBUS_PARAM:
case RT5677_SLIMBUS_RX:
case RT5677_SLIMBUS_CTRL:
case RT5677_SIDETONE_CTRL:
case RT5677_ANA_DAC1_2_3_SRC:
case RT5677_IF_DSP_DAC3_4_MIXER:
case RT5677_DAC4_DIG_VOL:
case RT5677_DAC3_DIG_VOL:
case RT5677_DAC1_DIG_VOL:
case RT5677_DAC2_DIG_VOL:
case RT5677_IF_DSP_DAC2_MIXER:
case RT5677_STO1_ADC_DIG_VOL:
case RT5677_MONO_ADC_DIG_VOL:
case RT5677_STO1_2_ADC_BST:
case RT5677_STO2_ADC_DIG_VOL:
case RT5677_ADC_BST_CTRL2:
case RT5677_STO3_4_ADC_BST:
case RT5677_STO3_ADC_DIG_VOL:
case RT5677_STO4_ADC_DIG_VOL:
case RT5677_STO4_ADC_MIXER:
case RT5677_STO3_ADC_MIXER:
case RT5677_STO2_ADC_MIXER:
case RT5677_STO1_ADC_MIXER:
case RT5677_MONO_ADC_MIXER:
case RT5677_ADC_IF_DSP_DAC1_MIXER:
case RT5677_STO1_DAC_MIXER:
case RT5677_MONO_DAC_MIXER:
case RT5677_DD1_MIXER:
case RT5677_DD2_MIXER:
case RT5677_IF3_DATA:
case RT5677_IF4_DATA:
case RT5677_PDM_OUT_CTRL:
case RT5677_PDM_DATA_CTRL1:
case RT5677_PDM_DATA_CTRL2:
case RT5677_PDM1_DATA_CTRL2:
case RT5677_PDM1_DATA_CTRL3:
case RT5677_PDM1_DATA_CTRL4:
case RT5677_PDM2_DATA_CTRL2:
case RT5677_PDM2_DATA_CTRL3:
case RT5677_PDM2_DATA_CTRL4:
case RT5677_TDM1_CTRL1:
case RT5677_TDM1_CTRL2:
case RT5677_TDM1_CTRL3:
case RT5677_TDM1_CTRL4:
case RT5677_TDM1_CTRL5:
case RT5677_TDM2_CTRL1:
case RT5677_TDM2_CTRL2:
case RT5677_TDM2_CTRL3:
case RT5677_TDM2_CTRL4:
case RT5677_TDM2_CTRL5:
case RT5677_I2C_MASTER_CTRL1:
case RT5677_I2C_MASTER_CTRL2:
case RT5677_I2C_MASTER_CTRL3:
case RT5677_I2C_MASTER_CTRL4:
case RT5677_I2C_MASTER_CTRL5:
case RT5677_I2C_MASTER_CTRL6:
case RT5677_I2C_MASTER_CTRL7:
case RT5677_I2C_MASTER_CTRL8:
case RT5677_DMIC_CTRL1:
case RT5677_DMIC_CTRL2:
case RT5677_HAP_GENE_CTRL1:
case RT5677_HAP_GENE_CTRL2:
case RT5677_HAP_GENE_CTRL3:
case RT5677_HAP_GENE_CTRL4:
case RT5677_HAP_GENE_CTRL5:
case RT5677_HAP_GENE_CTRL6:
case RT5677_HAP_GENE_CTRL7:
case RT5677_HAP_GENE_CTRL8:
case RT5677_HAP_GENE_CTRL9:
case RT5677_HAP_GENE_CTRL10:
case RT5677_PWR_DIG1:
case RT5677_PWR_DIG2:
case RT5677_PWR_ANLG1:
case RT5677_PWR_ANLG2:
case RT5677_PWR_DSP1:
case RT5677_PWR_DSP_ST:
case RT5677_PWR_DSP2:
case RT5677_ADC_DAC_HPF_CTRL1:
case RT5677_PRIV_INDEX:
case RT5677_PRIV_DATA:
case RT5677_I2S4_SDP:
case RT5677_I2S1_SDP:
case RT5677_I2S2_SDP:
case RT5677_I2S3_SDP:
case RT5677_CLK_TREE_CTRL1:
case RT5677_CLK_TREE_CTRL2:
case RT5677_CLK_TREE_CTRL3:
case RT5677_PLL1_CTRL1:
case RT5677_PLL1_CTRL2:
case RT5677_PLL2_CTRL1:
case RT5677_PLL2_CTRL2:
case RT5677_GLB_CLK1:
case RT5677_GLB_CLK2:
case RT5677_ASRC_1:
case RT5677_ASRC_2:
case RT5677_ASRC_3:
case RT5677_ASRC_4:
case RT5677_ASRC_5:
case RT5677_ASRC_6:
case RT5677_ASRC_7:
case RT5677_ASRC_8:
case RT5677_ASRC_9:
case RT5677_ASRC_10:
case RT5677_ASRC_11:
case RT5677_ASRC_12:
case RT5677_ASRC_13:
case RT5677_ASRC_14:
case RT5677_ASRC_15:
case RT5677_ASRC_16:
case RT5677_ASRC_17:
case RT5677_ASRC_18:
case RT5677_ASRC_19:
case RT5677_ASRC_20:
case RT5677_ASRC_21:
case RT5677_ASRC_22:
case RT5677_ASRC_23:
case RT5677_VAD_CTRL1:
case RT5677_VAD_CTRL2:
case RT5677_VAD_CTRL3:
case RT5677_VAD_CTRL4:
case RT5677_VAD_CTRL5:
case RT5677_DSP_INB_CTRL1:
case RT5677_DSP_INB_CTRL2:
case RT5677_DSP_IN_OUTB_CTRL:
case RT5677_DSP_OUTB0_1_DIG_VOL:
case RT5677_DSP_OUTB2_3_DIG_VOL:
case RT5677_DSP_OUTB4_5_DIG_VOL:
case RT5677_DSP_OUTB6_7_DIG_VOL:
case RT5677_ADC_EQ_CTRL1:
case RT5677_ADC_EQ_CTRL2:
case RT5677_EQ_CTRL1:
case RT5677_EQ_CTRL2:
case RT5677_EQ_CTRL3:
case RT5677_SOFT_VOL_ZERO_CROSS1:
case RT5677_JD_CTRL1:
case RT5677_JD_CTRL2:
case RT5677_JD_CTRL3:
case RT5677_IRQ_CTRL1:
case RT5677_IRQ_CTRL2:
case RT5677_GPIO_ST:
case RT5677_GPIO_CTRL1:
case RT5677_GPIO_CTRL2:
case RT5677_GPIO_CTRL3:
case RT5677_STO1_ADC_HI_FILTER1:
case RT5677_STO1_ADC_HI_FILTER2:
case RT5677_MONO_ADC_HI_FILTER1:
case RT5677_MONO_ADC_HI_FILTER2:
case RT5677_STO2_ADC_HI_FILTER1:
case RT5677_STO2_ADC_HI_FILTER2:
case RT5677_STO3_ADC_HI_FILTER1:
case RT5677_STO3_ADC_HI_FILTER2:
case RT5677_STO4_ADC_HI_FILTER1:
case RT5677_STO4_ADC_HI_FILTER2:
case RT5677_MB_DRC_CTRL1:
case RT5677_DRC1_CTRL1:
case RT5677_DRC1_CTRL2:
case RT5677_DRC1_CTRL3:
case RT5677_DRC1_CTRL4:
case RT5677_DRC1_CTRL5:
case RT5677_DRC1_CTRL6:
case RT5677_DRC2_CTRL1:
case RT5677_DRC2_CTRL2:
case RT5677_DRC2_CTRL3:
case RT5677_DRC2_CTRL4:
case RT5677_DRC2_CTRL5:
case RT5677_DRC2_CTRL6:
case RT5677_DRC1_HL_CTRL1:
case RT5677_DRC1_HL_CTRL2:
case RT5677_DRC2_HL_CTRL1:
case RT5677_DRC2_HL_CTRL2:
case RT5677_DSP_INB1_SRC_CTRL1:
case RT5677_DSP_INB1_SRC_CTRL2:
case RT5677_DSP_INB1_SRC_CTRL3:
case RT5677_DSP_INB1_SRC_CTRL4:
case RT5677_DSP_INB2_SRC_CTRL1:
case RT5677_DSP_INB2_SRC_CTRL2:
case RT5677_DSP_INB2_SRC_CTRL3:
case RT5677_DSP_INB2_SRC_CTRL4:
case RT5677_DSP_INB3_SRC_CTRL1:
case RT5677_DSP_INB3_SRC_CTRL2:
case RT5677_DSP_INB3_SRC_CTRL3:
case RT5677_DSP_INB3_SRC_CTRL4:
case RT5677_DSP_OUTB1_SRC_CTRL1:
case RT5677_DSP_OUTB1_SRC_CTRL2:
case RT5677_DSP_OUTB1_SRC_CTRL3:
case RT5677_DSP_OUTB1_SRC_CTRL4:
case RT5677_DSP_OUTB2_SRC_CTRL1:
case RT5677_DSP_OUTB2_SRC_CTRL2:
case RT5677_DSP_OUTB2_SRC_CTRL3:
case RT5677_DSP_OUTB2_SRC_CTRL4:
case RT5677_DSP_OUTB_0123_MIXER_CTRL:
case RT5677_DSP_OUTB_45_MIXER_CTRL:
case RT5677_DSP_OUTB_67_MIXER_CTRL:
case RT5677_DIG_MISC:
case RT5677_GEN_CTRL1:
case RT5677_GEN_CTRL2:
case RT5677_VENDOR_ID:
case RT5677_VENDOR_ID1:
case RT5677_VENDOR_ID2:
return true;
default:
return false;
}
}
/**
* rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
* @rt5677: Private Data.
* @addr: Address index.
* @value: Address data.
* @opcode: opcode value
*
* Returns 0 for success or negative error code.
*/
static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677,
unsigned int addr, unsigned int value, unsigned int opcode)
{
struct snd_soc_component *component = rt5677->component;
int ret;
mutex_lock(&rt5677->dsp_cmd_lock);
ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
addr >> 16);
if (ret < 0) {
dev_err(component->dev, "Failed to set addr msb value: %d\n", ret);
goto err;
}
ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
addr & 0xffff);
if (ret < 0) {
dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret);
goto err;
}
ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB,
value >> 16);
if (ret < 0) {
dev_err(component->dev, "Failed to set data msb value: %d\n", ret);
goto err;
}
ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB,
value & 0xffff);
if (ret < 0) {
dev_err(component->dev, "Failed to set data lsb value: %d\n", ret);
goto err;
}
ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
opcode);
if (ret < 0) {
dev_err(component->dev, "Failed to set op code value: %d\n", ret);
goto err;
}
err:
mutex_unlock(&rt5677->dsp_cmd_lock);
return ret;
}
/**
* rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
* @rt5677: Private Data.
* @addr: Address index.
* @value: Address data.
*
*
* Returns 0 for success or negative error code.
*/
static int rt5677_dsp_mode_i2c_read_addr(
struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value)
{
struct snd_soc_component *component = rt5677->component;
int ret;
unsigned int msb, lsb;
mutex_lock(&rt5677->dsp_cmd_lock);
ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
addr >> 16);
if (ret < 0) {
dev_err(component->dev, "Failed to set addr msb value: %d\n", ret);
goto err;
}
ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
addr & 0xffff);
if (ret < 0) {
dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret);
goto err;
}
ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
0x0002);
if (ret < 0) {
dev_err(component->dev, "Failed to set op code value: %d\n", ret);
goto err;
}
regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb);
regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb);
*value = (msb << 16) | lsb;
err:
mutex_unlock(&rt5677->dsp_cmd_lock);
return ret;
}
/**
* rt5677_dsp_mode_i2c_write - Write register on DSP mode.
* @rt5677: Private Data.
* @reg: Register index.
* @value: Register data.
*
*
* Returns 0 for success or negative error code.
*/
static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677,
unsigned int reg, unsigned int value)
{
return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2,
value, 0x0001);
}
/**
* rt5677_dsp_mode_i2c_read - Read register on DSP mode.
* @rt5677: Private Data
* @reg: Register index.
* @value: Register data.
*
*
* Returns 0 for success or negative error code.
*/
static int rt5677_dsp_mode_i2c_read(
struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value)
{
int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2,
value);
*value &= 0xffff;
return ret;
}
static void rt5677_set_dsp_mode(struct rt5677_priv *rt5677, bool on)
{
if (on) {
regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
RT5677_PWR_DSP, RT5677_PWR_DSP);
rt5677->is_dsp_mode = true;
} else {
regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
RT5677_PWR_DSP, 0x0);
rt5677->is_dsp_mode = false;
}
}
static unsigned int rt5677_set_vad_source(struct rt5677_priv *rt5677)
{
struct snd_soc_dapm_context *dapm =
snd_soc_component_get_dapm(rt5677->component);
/* Force dapm to sync before we enable the
* DSP to prevent write corruption
*/
snd_soc_dapm_sync(dapm);
/* DMIC1 power = enabled
* DMIC CLK = 256 * fs / 12
*/
regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
RT5677_DMIC_CLK_MASK, 5 << RT5677_DMIC_CLK_SFT);
/* I2S pre divide 2 = /6 (clk_sys2) */
regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
RT5677_I2S_PD2_MASK, RT5677_I2S_PD2_6);
/* DSP Clock = MCLK1 (bypassed PLL2) */
regmap_write(rt5677->regmap, RT5677_GLB_CLK2,
RT5677_DSP_CLK_SRC_BYPASS);
/* SAD Threshold1 */
regmap_write(rt5677->regmap, RT5677_VAD_CTRL2, 0x013f);
/* SAD Threshold2 */
regmap_write(rt5677->regmap, RT5677_VAD_CTRL3, 0x0ae5);
/* SAD Sample Rate Converter = Up 6 (8K to 48K)
* SAD Output Sample Rate = Same as I2S
* SAD Threshold3
*/
regmap_update_bits(rt5677->regmap, RT5677_VAD_CTRL4,
RT5677_VAD_OUT_SRC_RATE_MASK | RT5677_VAD_OUT_SRC_MASK |
RT5677_VAD_LV_DIFF_MASK, 0x7f << RT5677_VAD_LV_DIFF_SFT);
/* Minimum frame level within a pre-determined duration = 32 frames
* Bypass ADPCM Encoder/Decoder = Bypass ADPCM
* Automatic Push Data to SAD Buffer Once SAD Flag is triggered = enable
* SAD Buffer Over-Writing = enable
* SAD Buffer Pop Mode Control = disable
* SAD Buffer Push Mode Control = enable
* SAD Detector Control = enable
* SAD Function Control = enable
* SAD Function Reset = normal
*/
regmap_write(rt5677->regmap, RT5677_VAD_CTRL1,
RT5677_VAD_FUNC_RESET | RT5677_VAD_FUNC_ENABLE |
RT5677_VAD_DET_ENABLE | RT5677_VAD_BUF_PUSH |
RT5677_VAD_BUF_OW | RT5677_VAD_FG2ENC |
RT5677_VAD_ADPCM_BYPASS | 1 << RT5677_VAD_MIN_DUR_SFT);
/* VAD/SAD is not routed to the IRQ output (i.e. MX-BE[14] = 0), but it
* is routed to DSP_IRQ_0, so DSP firmware may use it to sleep and save
* power. See ALC5677 datasheet section 9.17 "GPIO, Interrupt and Jack
* Detection" for more info.
*/
/* Private register, no doc */
regmap_update_bits(rt5677->regmap, RT5677_PR_BASE + RT5677_BIAS_CUR4,
0x0f00, 0x0100);
/* LDO2 output = 1.2V
* LDO1 output = 1.2V (LDO_IN = 1.8V)
*/
regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
5 << RT5677_LDO1_SEL_SFT | 5 << RT5677_LDO2_SEL_SFT);
/* Codec core power = power on
* LDO1 power = power on
*/
regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
RT5677_PWR_CORE | RT5677_PWR_LDO1,
RT5677_PWR_CORE | RT5677_PWR_LDO1);
/* Isolation for DCVDD4 = normal (set during probe)
* Isolation for DCVDD2 = normal (set during probe)
* Isolation for DSP = normal
* Isolation for Band 0~7 = disable
* Isolation for InBound 4~10 and OutBound 4~10 = disable
*/
regmap_write(rt5677->regmap, RT5677_PWR_DSP2,
RT5677_PWR_CORE_ISO | RT5677_PWR_DSP_ISO |
RT5677_PWR_SR7_ISO | RT5677_PWR_SR6_ISO |
RT5677_PWR_SR5_ISO | RT5677_PWR_SR4_ISO |
RT5677_PWR_SR3_ISO | RT5677_PWR_SR2_ISO |
RT5677_PWR_SR1_ISO | RT5677_PWR_SR0_ISO |
RT5677_PWR_MLT_ISO);
/* System Band 0~7 = power on
* InBound 4~10 and OutBound 4~10 = power on
* DSP = power on
* DSP CPU = stop (will be set to "run" after firmware loaded)
*/
regmap_write(rt5677->regmap, RT5677_PWR_DSP1,
RT5677_PWR_SR7 | RT5677_PWR_SR6 |
RT5677_PWR_SR5 | RT5677_PWR_SR4 |
RT5677_PWR_SR3 | RT5677_PWR_SR2 |
RT5677_PWR_SR1 | RT5677_PWR_SR0 |
RT5677_PWR_MLT | RT5677_PWR_DSP |
RT5677_PWR_DSP_CPU);
return 0;
}
static int rt5677_parse_and_load_dsp(struct rt5677_priv *rt5677, const u8 *buf,
unsigned int len)
{
struct snd_soc_component *component = rt5677->component;
Elf32_Ehdr *elf_hdr;
Elf32_Phdr *pr_hdr;
Elf32_Half i;
int ret = 0;
if (!buf || (len < sizeof(Elf32_Ehdr)))
return -ENOMEM;
elf_hdr = (Elf32_Ehdr *)buf;
#ifndef EM_XTENSA
#define EM_XTENSA 94
#endif
if (strncmp(elf_hdr->e_ident, ELFMAG, sizeof(ELFMAG) - 1))
dev_err(component->dev, "Wrong ELF header prefix\n");
if (elf_hdr->e_ehsize != sizeof(Elf32_Ehdr))
dev_err(component->dev, "Wrong ELF header size\n");
if (elf_hdr->e_machine != EM_XTENSA)
dev_err(component->dev, "Wrong DSP code file\n");
if (len < elf_hdr->e_phoff)
return -ENOMEM;
pr_hdr = (Elf32_Phdr *)(buf + elf_hdr->e_phoff);
for (i = 0; i < elf_hdr->e_phnum; i++) {
/* TODO: handle p_memsz != p_filesz */
if (pr_hdr->p_paddr && pr_hdr->p_filesz) {
dev_info(component->dev, "Load 0x%x bytes to 0x%x\n",
pr_hdr->p_filesz, pr_hdr->p_paddr);
ret = rt5677_spi_write(pr_hdr->p_paddr,
buf + pr_hdr->p_offset,
pr_hdr->p_filesz);
if (ret)
dev_err(component->dev, "Load firmware failed %d\n",
ret);
}
pr_hdr++;
}
return ret;
}
static int rt5677_load_dsp_from_file(struct rt5677_priv *rt5677)
{
const struct firmware *fwp;
struct device *dev = rt5677->component->dev;
int ret = 0;
/* Load dsp firmware from rt5677_elf_vad file */
ret = request_firmware(&fwp, "rt5677_elf_vad", dev);
if (ret) {
dev_err(dev, "Request rt5677_elf_vad failed %d\n", ret);
return ret;
}
dev_info(dev, "Requested rt5677_elf_vad (%zu)\n", fwp->size);
ret = rt5677_parse_and_load_dsp(rt5677, fwp->data, fwp->size);
release_firmware(fwp);
return ret;
}
static int rt5677_set_dsp_vad(struct snd_soc_component *component, bool on)
{
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
rt5677->dsp_vad_en_request = on;
rt5677->dsp_vad_en = on;
if (!IS_ENABLED(CONFIG_SND_SOC_RT5677_SPI))
return -ENXIO;
schedule_delayed_work(&rt5677->dsp_work, 0);
return 0;
}
static void rt5677_dsp_work(struct work_struct *work)
{
struct rt5677_priv *rt5677 =
container_of(work, struct rt5677_priv, dsp_work.work);
static bool activity;
bool enable = rt5677->dsp_vad_en;
int i, val;
dev_info(rt5677->component->dev, "DSP VAD: enable=%d, activity=%d\n",
enable, activity);
if (enable && !activity) {
activity = true;
/* Before a hotword is detected, GPIO1 pin is configured as IRQ
* output so that jack detect works. When a hotword is detected,
* the DSP firmware configures the GPIO1 pin as GPIO1 and
* drives a 1. rt5677_irq() is called after a rising edge on
* the GPIO1 pin, due to either jack detect event or hotword
* event, or both. All possible events are checked and handled
* in rt5677_irq() where GPIO1 pin is configured back to IRQ
* output if a hotword is detected.
*/
rt5677_set_vad_source(rt5677);
rt5677_set_dsp_mode(rt5677, true);
#define RT5677_BOOT_RETRY 20
for (i = 0; i < RT5677_BOOT_RETRY; i++) {
regmap_read(rt5677->regmap, RT5677_PWR_DSP_ST, &val);
if (val == 0x3ff)
break;
udelay(500);
}
if (i == RT5677_BOOT_RETRY && val != 0x3ff) {
dev_err(rt5677->component->dev, "DSP Boot Timed Out!");
return;
}
/* Boot the firmware from IRAM instead of SRAM0. */
rt5677_dsp_mode_i2c_write_addr(rt5677, RT5677_DSP_BOOT_VECTOR,
0x0009, 0x0003);
rt5677_dsp_mode_i2c_write_addr(rt5677, RT5677_DSP_BOOT_VECTOR,
0x0019, 0x0003);
rt5677_dsp_mode_i2c_write_addr(rt5677, RT5677_DSP_BOOT_VECTOR,
0x0009, 0x0003);
rt5677_load_dsp_from_file(rt5677);
/* Set DSP CPU to Run */
regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
RT5677_PWR_DSP_CPU, 0x0);
} else if (!enable && activity) {
activity = false;
/* Don't turn off the DSP while handling irqs */
mutex_lock(&rt5677->irq_lock);
/* Set DSP CPU to Stop */
regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
RT5677_PWR_DSP_CPU, RT5677_PWR_DSP_CPU);
rt5677_set_dsp_mode(rt5677, false);
/* Disable and clear VAD interrupt */
regmap_write(rt5677->regmap, RT5677_VAD_CTRL1, 0x2184);
/* Set GPIO1 pin back to be IRQ output for jack detect */
regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1,
RT5677_GPIO1_PIN_MASK, RT5677_GPIO1_PIN_IRQ);
mutex_unlock(&rt5677->irq_lock);
}
}
static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
static const DECLARE_TLV_DB_RANGE(bst_tlv,
0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
);
static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = rt5677->dsp_vad_en_request;
return 0;
}
static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
rt5677_set_dsp_vad(component, !!ucontrol->value.integer.value[0]);
return 0;
}
static const struct snd_kcontrol_new rt5677_snd_controls[] = {
/* OUTPUT Control */
SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
RT5677_LOUT1_L_MUTE_SFT, 1, 1),
SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
RT5677_LOUT2_L_MUTE_SFT, 1, 1),
SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
RT5677_LOUT3_L_MUTE_SFT, 1, 1),
/* DAC Digital Volume */
SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv),
SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv),
SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv),
SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv),
/* IN1/IN2 Control */
SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
/* ADC Digital Volume Control */
SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
adc_vol_tlv),
SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
adc_vol_tlv),
SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
adc_vol_tlv),
SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
adc_vol_tlv),
SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0,
adc_vol_tlv),
/* Sidetone Control */
SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL,
RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv),
/* ADC Boost Volume Control */
SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
adc_bst_tlv),
SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
adc_bst_tlv),
SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
adc_bst_tlv),
SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
adc_bst_tlv),
SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
adc_bst_tlv),
SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0,
rt5677_dsp_vad_get, rt5677_dsp_vad_put),
};
/**
* set_dmic_clk - Set parameter of dmic.
*
* @w: DAPM widget.
* @kcontrol: The kcontrol of this widget.
* @event: Event id.
*
* Choose dmic clock between 1MHz and 3MHz.
* It is better for clock to approximate 3MHz.
*/
static int set_dmic_clk(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
int idx, rate;
rate = rt5677->sysclk / rl6231_get_pre_div(rt5677->regmap,
RT5677_CLK_TREE_CTRL1, RT5677_I2S_PD1_SFT);
idx = rl6231_calc_dmic_clk(rate);
if (idx < 0)
dev_err(component->dev, "Failed to set DMIC clock\n");
else
regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
return idx;
}
static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
unsigned int val;
regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
val &= RT5677_SCLK_SRC_MASK;
if (val == RT5677_SCLK_SRC_PLL1)
return 1;
else
return 0;
}
static int is_using_asrc(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
unsigned int reg, shift, val;
if (source->reg == RT5677_ASRC_1) {
switch (source->shift) {
case 12:
reg = RT5677_ASRC_4;
shift = 0;
break;
case 13:
reg = RT5677_ASRC_4;
shift = 4;
break;
case 14:
reg = RT5677_ASRC_4;
shift = 8;
break;
case 15:
reg = RT5677_ASRC_4;
shift = 12;
break;
default:
return 0;
}
} else {
switch (source->shift) {
case 0:
reg = RT5677_ASRC_6;
shift = 8;
break;
case 1:
reg = RT5677_ASRC_6;
shift = 12;
break;
case 2:
reg = RT5677_ASRC_5;
shift = 0;
break;
case 3:
reg = RT5677_ASRC_5;
shift = 4;
break;
case 4:
reg = RT5677_ASRC_5;
shift = 8;
break;
case 5:
reg = RT5677_ASRC_5;
shift = 12;
break;
case 12:
reg = RT5677_ASRC_3;
shift = 0;
break;
case 13:
reg = RT5677_ASRC_3;
shift = 4;
break;
case 14:
reg = RT5677_ASRC_3;
shift = 12;
break;
default:
return 0;
}
}
regmap_read(rt5677->regmap, reg, &val);
val = (val >> shift) & 0xf;
switch (val) {
case 1 ... 6:
return 1;
default:
return 0;
}
}
static int can_use_asrc(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384)
return 1;
return 0;
}
/**
* rt5677_sel_asrc_clk_src - select ASRC clock source for a set of filters
* @component: SoC audio component device.
* @filter_mask: mask of filters.
* @clk_src: clock source
*
* The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5677 can
* only support standard 32fs or 64fs i2s format, ASRC should be enabled to
* support special i2s clock format such as Intel's 100fs(100 * sampling rate).
* ASRC function will track i2s clock and generate a corresponding system clock
* for codec. This function provides an API to select the clock source for a
* set of filters specified by the mask. And the codec driver will turn on ASRC
* for these filters if ASRC is selected as their clock source.
*/
int rt5677_sel_asrc_clk_src(struct snd_soc_component *component,
unsigned int filter_mask, unsigned int clk_src)
{
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
unsigned int asrc3_mask = 0, asrc3_value = 0;
unsigned int asrc4_mask = 0, asrc4_value = 0;
unsigned int asrc5_mask = 0, asrc5_value = 0;
unsigned int asrc6_mask = 0, asrc6_value = 0;
unsigned int asrc7_mask = 0, asrc7_value = 0;
unsigned int asrc8_mask = 0, asrc8_value = 0;
switch (clk_src) {
case RT5677_CLK_SEL_SYS:
case RT5677_CLK_SEL_I2S1_ASRC:
case RT5677_CLK_SEL_I2S2_ASRC:
case RT5677_CLK_SEL_I2S3_ASRC:
case RT5677_CLK_SEL_I2S4_ASRC:
case RT5677_CLK_SEL_I2S5_ASRC:
case RT5677_CLK_SEL_I2S6_ASRC:
case RT5677_CLK_SEL_SYS2:
case RT5677_CLK_SEL_SYS3:
case RT5677_CLK_SEL_SYS4:
case RT5677_CLK_SEL_SYS5:
case RT5677_CLK_SEL_SYS6:
case RT5677_CLK_SEL_SYS7:
break;
default:
return -EINVAL;
}
/* ASRC 3 */
if (filter_mask & RT5677_DA_STEREO_FILTER) {
asrc3_mask |= RT5677_DA_STO_CLK_SEL_MASK;
asrc3_value = (asrc3_value & ~RT5677_DA_STO_CLK_SEL_MASK)
| (clk_src << RT5677_DA_STO_CLK_SEL_SFT);
}
if (filter_mask & RT5677_DA_MONO2_L_FILTER) {
asrc3_mask |= RT5677_DA_MONO2L_CLK_SEL_MASK;
asrc3_value = (asrc3_value & ~RT5677_DA_MONO2L_CLK_SEL_MASK)
| (clk_src << RT5677_DA_MONO2L_CLK_SEL_SFT);
}
if (filter_mask & RT5677_DA_MONO2_R_FILTER) {
asrc3_mask |= RT5677_DA_MONO2R_CLK_SEL_MASK;
asrc3_value = (asrc3_value & ~RT5677_DA_MONO2R_CLK_SEL_MASK)
| (clk_src << RT5677_DA_MONO2R_CLK_SEL_SFT);
}
if (asrc3_mask)
regmap_update_bits(rt5677->regmap, RT5677_ASRC_3, asrc3_mask,
asrc3_value);
/* ASRC 4 */
if (filter_mask & RT5677_DA_MONO3_L_FILTER) {
asrc4_mask |= RT5677_DA_MONO3L_CLK_SEL_MASK;
asrc4_value = (asrc4_value & ~RT5677_DA_MONO3L_CLK_SEL_MASK)
| (clk_src << RT5677_DA_MONO3L_CLK_SEL_SFT);
}
if (filter_mask & RT5677_DA_MONO3_R_FILTER) {
asrc4_mask |= RT5677_DA_MONO3R_CLK_SEL_MASK;
asrc4_value = (asrc4_value & ~RT5677_DA_MONO3R_CLK_SEL_MASK)
| (clk_src << RT5677_DA_MONO3R_CLK_SEL_SFT);
}
if (filter_mask & RT5677_DA_MONO4_L_FILTER) {
asrc4_mask |= RT5677_DA_MONO4L_CLK_SEL_MASK;
asrc4_value = (asrc4_value & ~RT5677_DA_MONO4L_CLK_SEL_MASK)
| (clk_src << RT5677_DA_MONO4L_CLK_SEL_SFT);
}
if (filter_mask & RT5677_DA_MONO4_R_FILTER) {
asrc4_mask |= RT5677_DA_MONO4R_CLK_SEL_MASK;
asrc4_value = (asrc4_value & ~RT5677_DA_MONO4R_CLK_SEL_MASK)
| (clk_src << RT5677_DA_MONO4R_CLK_SEL_SFT);
}
if (asrc4_mask)
regmap_update_bits(rt5677->regmap, RT5677_ASRC_4, asrc4_mask,
asrc4_value);
/* ASRC 5 */
if (filter_mask & RT5677_AD_STEREO1_FILTER) {
asrc5_mask |= RT5677_AD_STO1_CLK_SEL_MASK;
asrc5_value = (asrc5_value & ~RT5677_AD_STO1_CLK_SEL_MASK)
| (clk_src << RT5677_AD_STO1_CLK_SEL_SFT);
}
if (filter_mask & RT5677_AD_STEREO2_FILTER) {
asrc5_mask |= RT5677_AD_STO2_CLK_SEL_MASK;
asrc5_value = (asrc5_value & ~RT5677_AD_STO2_CLK_SEL_MASK)
| (clk_src << RT5677_AD_STO2_CLK_SEL_SFT);
}
if (filter_mask & RT5677_AD_STEREO3_FILTER) {
asrc5_mask |= RT5677_AD_STO3_CLK_SEL_MASK;
asrc5_value = (asrc5_value & ~RT5677_AD_STO3_CLK_SEL_MASK)
| (clk_src << RT5677_AD_STO3_CLK_SEL_SFT);
}
if (filter_mask & RT5677_AD_STEREO4_FILTER) {
asrc5_mask |= RT5677_AD_STO4_CLK_SEL_MASK;
asrc5_value = (asrc5_value & ~RT5677_AD_STO4_CLK_SEL_MASK)
| (clk_src << RT5677_AD_STO4_CLK_SEL_SFT);
}
if (asrc5_mask)
regmap_update_bits(rt5677->regmap, RT5677_ASRC_5, asrc5_mask,
asrc5_value);
/* ASRC 6 */
if (filter_mask & RT5677_AD_MONO_L_FILTER) {
asrc6_mask |= RT5677_AD_MONOL_CLK_SEL_MASK;
asrc6_value = (asrc6_value & ~RT5677_AD_MONOL_CLK_SEL_MASK)
| (clk_src << RT5677_AD_MONOL_CLK_SEL_SFT);
}
if (filter_mask & RT5677_AD_MONO_R_FILTER) {
asrc6_mask |= RT5677_AD_MONOR_CLK_SEL_MASK;
asrc6_value = (asrc6_value & ~RT5677_AD_MONOR_CLK_SEL_MASK)
| (clk_src << RT5677_AD_MONOR_CLK_SEL_SFT);
}
if (asrc6_mask)
regmap_update_bits(rt5677->regmap, RT5677_ASRC_6, asrc6_mask,
asrc6_value);
/* ASRC 7 */
if (filter_mask & RT5677_DSP_OB_0_3_FILTER) {
asrc7_mask |= RT5677_DSP_OB_0_3_CLK_SEL_MASK;
asrc7_value = (asrc7_value & ~RT5677_DSP_OB_0_3_CLK_SEL_MASK)
| (clk_src << RT5677_DSP_OB_0_3_CLK_SEL_SFT);
}
if (filter_mask & RT5677_DSP_OB_4_7_FILTER) {
asrc7_mask |= RT5677_DSP_OB_4_7_CLK_SEL_MASK;
asrc7_value = (asrc7_value & ~RT5677_DSP_OB_4_7_CLK_SEL_MASK)
| (clk_src << RT5677_DSP_OB_4_7_CLK_SEL_SFT);
}
if (asrc7_mask)
regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask,
asrc7_value);
/* ASRC 8 */
if (filter_mask & RT5677_I2S1_SOURCE) {
asrc8_mask |= RT5677_I2S1_CLK_SEL_MASK;
asrc8_value = (asrc8_value & ~RT5677_I2S1_CLK_SEL_MASK)
| ((clk_src - 1) << RT5677_I2S1_CLK_SEL_SFT);
}
if (filter_mask & RT5677_I2S2_SOURCE) {
asrc8_mask |= RT5677_I2S2_CLK_SEL_MASK;
asrc8_value = (asrc8_value & ~RT5677_I2S2_CLK_SEL_MASK)
| ((clk_src - 1) << RT5677_I2S2_CLK_SEL_SFT);
}
if (filter_mask & RT5677_I2S3_SOURCE) {
asrc8_mask |= RT5677_I2S3_CLK_SEL_MASK;
asrc8_value = (asrc8_value & ~RT5677_I2S3_CLK_SEL_MASK)
| ((clk_src - 1) << RT5677_I2S3_CLK_SEL_SFT);
}
if (filter_mask & RT5677_I2S4_SOURCE) {
asrc8_mask |= RT5677_I2S4_CLK_SEL_MASK;
asrc8_value = (asrc8_value & ~RT5677_I2S4_CLK_SEL_MASK)
| ((clk_src - 1) << RT5677_I2S4_CLK_SEL_SFT);
}
if (asrc8_mask)
regmap_update_bits(rt5677->regmap, RT5677_ASRC_8, asrc8_mask,
asrc8_value);
return 0;
}
EXPORT_SYMBOL_GPL(rt5677_sel_asrc_clk_src);
static int rt5677_dmic_use_asrc(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
unsigned int asrc_setting;
switch (source->shift) {
case 11:
regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
asrc_setting = (asrc_setting & RT5677_AD_STO1_CLK_SEL_MASK) >>
RT5677_AD_STO1_CLK_SEL_SFT;
break;
case 10:
regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
asrc_setting = (asrc_setting & RT5677_AD_STO2_CLK_SEL_MASK) >>
RT5677_AD_STO2_CLK_SEL_SFT;
break;
case 9:
regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
asrc_setting = (asrc_setting & RT5677_AD_STO3_CLK_SEL_MASK) >>
RT5677_AD_STO3_CLK_SEL_SFT;
break;
case 8:
regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
asrc_setting = (asrc_setting & RT5677_AD_STO4_CLK_SEL_MASK) >>
RT5677_AD_STO4_CLK_SEL_SFT;
break;
case 7:
regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
asrc_setting = (asrc_setting & RT5677_AD_MONOL_CLK_SEL_MASK) >>
RT5677_AD_MONOL_CLK_SEL_SFT;
break;
case 6:
regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
asrc_setting = (asrc_setting & RT5677_AD_MONOR_CLK_SEL_MASK) >>
RT5677_AD_MONOR_CLK_SEL_SFT;
break;
default:
return 0;
}
if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
return 1;
return 0;
}
/* Digital Mixer */
static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
RT5677_M_STO1_ADC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
RT5677_M_STO1_ADC_L2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
RT5677_M_STO1_ADC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
RT5677_M_STO1_ADC_R2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
RT5677_M_STO2_ADC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
RT5677_M_STO2_ADC_L2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
RT5677_M_STO2_ADC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
RT5677_M_STO2_ADC_R2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
RT5677_M_STO3_ADC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
RT5677_M_STO3_ADC_L2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
RT5677_M_STO3_ADC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
RT5677_M_STO3_ADC_R2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
RT5677_M_STO4_ADC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
RT5677_M_STO4_ADC_L2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
RT5677_M_STO4_ADC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
RT5677_M_STO4_ADC_R2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
RT5677_M_MONO_ADC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
RT5677_M_MONO_ADC_L2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
RT5677_M_MONO_ADC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
RT5677_M_MONO_ADC_R2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
RT5677_M_DAC1_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
RT5677_M_DAC1_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_STO1_DAC_MIXER,
RT5677_M_ST_DAC1_L_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_STO1_DAC_MIXER,
RT5677_M_ST_DAC1_R_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_MONO_DAC_MIXER,
RT5677_M_ST_DAC2_L_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_MONO_DAC_MIXER,
RT5677_M_ST_DAC2_R_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
RT5677_M_STO_L_DD1_L_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER,
RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER,
RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
RT5677_M_STO_R_DD1_R_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER,
RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER,
RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
RT5677_M_STO_L_DD2_L_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER,
RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER,
RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
RT5677_M_STO_R_DD2_R_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER,
RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER,
RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
RT5677_DSP_IB_01_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
RT5677_DSP_IB_23_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
RT5677_DSP_IB_45_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
RT5677_DSP_IB_6_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
RT5677_DSP_IB_7_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
RT5677_DSP_IB_8_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
RT5677_DSP_IB_9_H_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
RT5677_DSP_IB_01_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
RT5677_DSP_IB_23_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
RT5677_DSP_IB_45_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
RT5677_DSP_IB_6_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
RT5677_DSP_IB_7_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
RT5677_DSP_IB_8_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
RT5677_DSP_IB_9_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
RT5677_DSP_IB_01_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
RT5677_DSP_IB_23_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
RT5677_DSP_IB_45_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
RT5677_DSP_IB_6_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
RT5677_DSP_IB_7_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
RT5677_DSP_IB_8_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
RT5677_DSP_IB_9_H_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
RT5677_DSP_IB_01_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
RT5677_DSP_IB_23_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
RT5677_DSP_IB_45_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
RT5677_DSP_IB_6_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
RT5677_DSP_IB_7_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
RT5677_DSP_IB_8_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
RT5677_DSP_IB_9_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
RT5677_DSP_IB_01_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
RT5677_DSP_IB_23_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
RT5677_DSP_IB_45_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
RT5677_DSP_IB_6_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
RT5677_DSP_IB_7_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
RT5677_DSP_IB_8_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
RT5677_DSP_IB_9_H_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
RT5677_DSP_IB_01_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
RT5677_DSP_IB_23_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
RT5677_DSP_IB_45_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
RT5677_DSP_IB_6_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
RT5677_DSP_IB_7_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
RT5677_DSP_IB_8_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
RT5677_DSP_IB_9_L_SFT, 1, 1),
};
/* Mux */
/* DAC1 L/R Source */ /* MX-29 [10:8] */
static const char * const rt5677_dac1_src[] = {
"IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
"OB 01"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
static const struct snd_kcontrol_new rt5677_dac1_mux =
SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
/* ADDA1 L/R Source */ /* MX-29 [1:0] */
static const char * const rt5677_adda1_src[] = {
"STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
};
static SOC_ENUM_SINGLE_DECL(
rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
static const struct snd_kcontrol_new rt5677_adda1_mux =
SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
/*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
static const char * const rt5677_dac2l_src[] = {
"IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
"OB 2",
};
static SOC_ENUM_SINGLE_DECL(
rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
static const struct snd_kcontrol_new rt5677_dac2_l_mux =
SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
static const char * const rt5677_dac2r_src[] = {
"IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
"OB 3", "Haptic Generator", "VAD ADC"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
static const struct snd_kcontrol_new rt5677_dac2_r_mux =
SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
/*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
static const char * const rt5677_dac3l_src[] = {
"IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
"SLB DAC 4", "OB 4"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
static const struct snd_kcontrol_new rt5677_dac3_l_mux =
SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
static const char * const rt5677_dac3r_src[] = {
"IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
"SLB DAC 5", "OB 5"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
static const struct snd_kcontrol_new rt5677_dac3_r_mux =
SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
/*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
static const char * const rt5677_dac4l_src[] = {
"IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
"SLB DAC 6", "OB 6"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
static const struct snd_kcontrol_new rt5677_dac4_l_mux =
SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
static const char * const rt5677_dac4r_src[] = {
"IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
"SLB DAC 7", "OB 7"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
static const struct snd_kcontrol_new rt5677_dac4_r_mux =
SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
/* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
static const char * const rt5677_iob_bypass_src[] = {
"Bypass", "Pass SRC"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
/* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
static const char * const rt5677_stereo_adc2_src[] = {
"DD MIX1", "DMIC", "Stereo DAC MIX"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
/* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
static const char * const rt5677_dmic_src[] = {
"DMIC1", "DMIC2", "DMIC3", "DMIC4"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
/* Stereo2 ADC Source */ /* MX-26 [0] */
static const char * const rt5677_stereo2_adc_lr_src[] = {
"L", "LR"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
/* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
static const char * const rt5677_stereo_adc1_src[] = {
"DD MIX1", "ADC1/2", "Stereo DAC MIX"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
/* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
static const char * const rt5677_mono_adc2_l_src[] = {
"DD MIX1L", "DMIC", "MONO DAC MIXL"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
/* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
static const char * const rt5677_mono_adc1_l_src[] = {
"DD MIX1L", "ADC1", "MONO DAC MIXL"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
/* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
static const char * const rt5677_mono_adc2_r_src[] = {
"DD MIX1R", "DMIC", "MONO DAC MIXR"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
/* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
static const char * const rt5677_mono_adc1_r_src[] = {
"DD MIX1R", "ADC2", "MONO DAC MIXR"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
/* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
static const char * const rt5677_stereo4_adc2_src[] = {
"DD MIX1", "DMIC", "DD MIX2"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
/* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
static const char * const rt5677_stereo4_adc1_src[] = {
"DD MIX1", "ADC1/2", "DD MIX2"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
/* InBound0/1 Source */ /* MX-A3 [14:12] */
static const char * const rt5677_inbound01_src[] = {
"IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
"VAD ADC/DAC1 FS"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
static const struct snd_kcontrol_new rt5677_ib01_src_mux =
SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
/* InBound2/3 Source */ /* MX-A3 [10:8] */
static const char * const rt5677_inbound23_src[] = {
"IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
"DAC1 FS", "IF4 DAC"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
static const struct snd_kcontrol_new rt5677_ib23_src_mux =
SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
/* InBound4/5 Source */ /* MX-A3 [6:4] */
static const char * const rt5677_inbound45_src[] = {
"IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
"IF3 DAC"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
static const struct snd_kcontrol_new rt5677_ib45_src_mux =
SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
/* InBound6 Source */ /* MX-A3 [2:0] */
static const char * const rt5677_inbound6_src[] = {
"IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
"IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
static const struct snd_kcontrol_new rt5677_ib6_src_mux =
SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
/* InBound7 Source */ /* MX-A4 [14:12] */
static const char * const rt5677_inbound7_src[] = {
"IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
"IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
static const struct snd_kcontrol_new rt5677_ib7_src_mux =
SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
/* InBound8 Source */ /* MX-A4 [10:8] */
static const char * const rt5677_inbound8_src[] = {
"STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
"MONO ADC MIX L", "DACL1 FS"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
static const struct snd_kcontrol_new rt5677_ib8_src_mux =
SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
/* InBound9 Source */ /* MX-A4 [6:4] */
static const char * const rt5677_inbound9_src[] = {
"STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
"MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
static const struct snd_kcontrol_new rt5677_ib9_src_mux =
SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
/* VAD Source */ /* MX-9F [6:4] */
static const char * const rt5677_vad_src[] = {
"STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
"STO3 ADC MIX L"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_vad_enum, RT5677_VAD_CTRL4,
RT5677_VAD_SRC_SFT, rt5677_vad_src);
static const struct snd_kcontrol_new rt5677_vad_src_mux =
SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
/* Sidetone Source */ /* MX-13 [11:9] */
static const char * const rt5677_sidetone_src[] = {
"DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
RT5677_ST_SEL_SFT, rt5677_sidetone_src);
static const struct snd_kcontrol_new rt5677_sidetone_mux =
SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
/* DAC1/2 Source */ /* MX-15 [1:0] */
static const char * const rt5677_dac12_src[] = {
"STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
static const struct snd_kcontrol_new rt5677_dac12_mux =
SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
/* DAC3 Source */ /* MX-15 [5:4] */
static const char * const rt5677_dac3_src[] = {
"MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
static const struct snd_kcontrol_new rt5677_dac3_mux =
SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
/* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
static const char * const rt5677_pdm_src[] = {
"STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
/* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */
static const char * const rt5677_if12_adc1_src[] = {
"STO1 ADC MIX", "OB01", "VAD ADC"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
/* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
static const char * const rt5677_if12_adc2_src[] = {
"STO2 ADC MIX", "OB23"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
/* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
static const char * const rt5677_if12_adc3_src[] = {
"STO3 ADC MIX", "MONO ADC MIX", "OB45"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
/* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
static const char * const rt5677_if12_adc4_src[] = {
"STO4 ADC MIX", "OB67", "OB01"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
/* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */
static const char * const rt5677_if34_adc_src[] = {
"STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
"MONO ADC MIX", "OB01", "OB23", "VAD ADC"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_if3_adc_enum, RT5677_IF3_DATA,
RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
static const struct snd_kcontrol_new rt5677_if3_adc_mux =
SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if4_adc_enum, RT5677_IF4_DATA,
RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
static const struct snd_kcontrol_new rt5677_if4_adc_mux =
SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
/* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */
static const char * const rt5677_if12_adc_swap_src[] = {
"L/R", "R/L", "L/L", "R/R"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1,
RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src);
static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux =
SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1,
RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux =
SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1,
RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux =
SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1,
RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux =
SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1,
RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux =
SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1,
RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux =
SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1,
RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux =
SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1,
RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux =
SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum);
/* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */
static const char * const rt5677_if1_adc_tdm_swap_src[] = {
"1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
"3/1/2/4", "3/4/1/2"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2,
RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src);
static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux =
SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum);
/* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */
static const char * const rt5677_if2_adc_tdm_swap_src[] = {
"1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
"2/3/1/4", "3/4/1/2"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2,
RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src);
static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux =
SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum);
/* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0]
MX-3F[14:12][10:8][6:4][2:0]
MX-43[14:12][10:8][6:4][2:0]
MX-44[14:12][10:8][6:4][2:0] */
static const char * const rt5677_if12_dac_tdm_sel_src[] = {
"Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4,
RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux =
SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4,
RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux =
SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4,
RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux =
SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4,
RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux =
SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5,
RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux =
SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5,
RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux =
SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5,
RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux =
SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5,
RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux =
SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4,
RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux =
SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4,
RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux =
SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4,
RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux =
SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4,
RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux =
SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5,
RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux =
SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5,
RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux =
SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5,
RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux =
SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5,
RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux =
SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum);
static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
RT5677_PWR_BST1_P, 0);
break;
default:
return 0;
}
return 0;
}
static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
RT5677_PWR_BST2_P, 0);
break;
default:
return 0;
}
return 0;
}
static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
break;
case SND_SOC_DAPM_POST_PMU:
regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
break;
default:
return 0;
}
return 0;
}
static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
break;
case SND_SOC_DAPM_POST_PMU:
regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
break;
default:
return 0;
}
return 0;
}
static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
RT5677_PWR_CLK_MB, 0);
break;
default:
return 0;
}
return 0;
}
static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
unsigned int value;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value);
if (value & RT5677_IF1_ADC_CTRL_MASK)
regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1,
RT5677_IF1_ADC_MODE_MASK,
RT5677_IF1_ADC_MODE_TDM);
break;
default:
return 0;
}
return 0;
}
static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
unsigned int value;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value);
if (value & RT5677_IF2_ADC_CTRL_MASK)
regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1,
RT5677_IF2_ADC_MODE_MASK,
RT5677_IF2_ADC_MODE_TDM);
break;
default:
return 0;
}
return 0;
}
static int rt5677_vref_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
if (snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_ON &&
!rt5677->is_vref_slow) {
mdelay(20);
regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
RT5677_PWR_FV1 | RT5677_PWR_FV2,
RT5677_PWR_FV1 | RT5677_PWR_FV2);
rt5677->is_vref_slow = true;
}
break;
default:
return 0;
}
return 0;
}
static int rt5677_filter_power_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
switch (event) {
case SND_SOC_DAPM_POST_PMU:
msleep(50);
break;
default:
return 0;
}
return 0;
}
static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
0, rt5677_set_pll1_event, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
0, rt5677_set_pll2_event, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMU),
/* ASRC */
SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5677_ASRC_1, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5677_ASRC_1, 1, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5677_ASRC_1, 2, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("I2S4 ASRC", 1, RT5677_ASRC_1, 3, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5677_ASRC_2, 14, 0,
rt5677_filter_power_event, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY_S("DAC MONO2 L ASRC", 1, RT5677_ASRC_2, 13, 0, NULL,
0),
SND_SOC_DAPM_SUPPLY_S("DAC MONO2 R ASRC", 1, RT5677_ASRC_2, 12, 0, NULL,
0),
SND_SOC_DAPM_SUPPLY_S("DAC MONO3 L ASRC", 1, RT5677_ASRC_1, 15, 0, NULL,
0),
SND_SOC_DAPM_SUPPLY_S("DAC MONO3 R ASRC", 1, RT5677_ASRC_1, 14, 0, NULL,
0),
SND_SOC_DAPM_SUPPLY_S("DAC MONO4 L ASRC", 1, RT5677_ASRC_1, 13, 0, NULL,
0),
SND_SOC_DAPM_SUPPLY_S("DAC MONO4 R ASRC", 1, RT5677_ASRC_1, 12, 0, NULL,
0),
SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5677_ASRC_2, 11, 0, NULL,
0),
SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5677_ASRC_2, 10, 0, NULL,
0),
SND_SOC_DAPM_SUPPLY_S("DMIC STO3 ASRC", 1, RT5677_ASRC_2, 9, 0, NULL,
0),
SND_SOC_DAPM_SUPPLY_S("DMIC STO4 ASRC", 1, RT5677_ASRC_2, 8, 0, NULL,
0),
SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5677_ASRC_2, 7, 0, NULL,
0),
SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5677_ASRC_2, 6, 0, NULL,
0),
SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5677_ASRC_2, 5, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5677_ASRC_2, 4, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADC STO3 ASRC", 1, RT5677_ASRC_2, 3, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADC STO4 ASRC", 1, RT5677_ASRC_2, 2, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5677_ASRC_2, 1, 0, NULL,
0),
SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5677_ASRC_2, 0, 0, NULL,
0),
/* Input Side */
/* micbias */
SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD |
SND_SOC_DAPM_POST_PMU),
/* Input Lines */
SND_SOC_DAPM_INPUT("DMIC L1"),
SND_SOC_DAPM_INPUT("DMIC R1"),
SND_SOC_DAPM_INPUT("DMIC L2"),
SND_SOC_DAPM_INPUT("DMIC R2"),
SND_SOC_DAPM_INPUT("DMIC L3"),
SND_SOC_DAPM_INPUT("DMIC R3"),
SND_SOC_DAPM_INPUT("DMIC L4"),
SND_SOC_DAPM_INPUT("DMIC R4"),
SND_SOC_DAPM_INPUT("IN1P"),
SND_SOC_DAPM_INPUT("IN1N"),
SND_SOC_DAPM_INPUT("IN2P"),
SND_SOC_DAPM_INPUT("IN2N"),
SND_SOC_DAPM_INPUT("Haptic Generator"),
SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1,
RT5677_DMIC_1_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1,
RT5677_DMIC_2_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1,
RT5677_DMIC_3_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2,
RT5677_DMIC_4_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
/* Boost */
SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
/* ADCs */
SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
0, 0),
SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
0, 0),
SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
/* ADC Mux */
SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
&rt5677_sto1_dmic_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_sto1_adc1_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_sto1_adc2_mux),
SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
&rt5677_sto2_dmic_mux),
SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_sto2_adc1_mux),
SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_sto2_adc2_mux),
SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
&rt5677_sto2_adc_lr_mux),
SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
&rt5677_sto3_dmic_mux),
SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_sto3_adc1_mux),
SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_sto3_adc2_mux),
SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
&rt5677_sto4_dmic_mux),
SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_sto4_adc1_mux),
SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_sto4_adc2_mux),
SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
&rt5677_mono_dmic_l_mux),
SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
&rt5677_mono_dmic_r_mux),
SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
&rt5677_mono_adc2_l_mux),
SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
&rt5677_mono_adc1_l_mux),
SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
&rt5677_mono_adc1_r_mux),
SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
&rt5677_mono_adc2_r_mux),
/* ADC Mixer */
SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
/* ADC PGA */
SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
/* DSP */
SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_ib9_src_mux),
SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_ib8_src_mux),
SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_ib7_src_mux),
SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_ib6_src_mux),
SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_ib45_src_mux),
SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_ib23_src_mux),
SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_ib01_src_mux),
SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
&rt5677_ib45_bypass_src_mux),
SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
&rt5677_ib23_bypass_src_mux),
SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
&rt5677_ib01_bypass_src_mux),
SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
&rt5677_ob23_bypass_src_mux),
SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
&rt5677_ob01_bypass_src_mux),
SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
/* Digital Interface */
SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
RT5677_PWR_I2S1_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
RT5677_PWR_I2S2_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
RT5677_PWR_I2S3_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
RT5677_PWR_I2S4_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
RT5677_PWR_SLB_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
/* Digital Interface Select */
SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if1_adc1_mux),
SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if1_adc2_mux),
SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if1_adc3_mux),
SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if1_adc4_mux),
SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if1_adc1_swap_mux),
SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if1_adc2_swap_mux),
SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if1_adc3_swap_mux),
SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if1_adc4_swap_mux),
SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event,
SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if2_adc1_mux),
SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if2_adc2_mux),
SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if2_adc3_mux),
SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if2_adc4_mux),
SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if2_adc1_swap_mux),
SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if2_adc2_swap_mux),
SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if2_adc3_swap_mux),
SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if2_adc4_swap_mux),
SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event,
SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if3_adc_mux),
SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if4_adc_mux),
SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_slb_adc1_mux),
SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_slb_adc2_mux),
SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_slb_adc3_mux),
SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_slb_adc4_mux),
SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if1_dac0_tdm_sel_mux),
SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if1_dac1_tdm_sel_mux),
SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if1_dac2_tdm_sel_mux),
SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if1_dac3_tdm_sel_mux),
SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if1_dac4_tdm_sel_mux),
SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if1_dac5_tdm_sel_mux),
SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if1_dac6_tdm_sel_mux),
SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if1_dac7_tdm_sel_mux),
SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if2_dac0_tdm_sel_mux),
SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if2_dac1_tdm_sel_mux),
SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if2_dac2_tdm_sel_mux),
SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if2_dac3_tdm_sel_mux),
SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if2_dac4_tdm_sel_mux),
SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if2_dac5_tdm_sel_mux),
SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if2_dac6_tdm_sel_mux),
SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_if2_dac7_tdm_sel_mux),
/* Audio Interface */
SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("DSPTX", "DSP Buffer", 0, SND_SOC_NOPM, 0, 0),
/* Sidetone Mux */
SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
&rt5677_sidetone_mux),
SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL,
RT5677_ST_EN_SFT, 0, NULL, 0),
/* VAD Mux*/
SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
&rt5677_vad_src_mux),
/* Tensilica DSP */
SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
/* Output Side */
/* DAC mixer before sound effect */
SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
/* DAC Mux */
SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_dac1_mux),
SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
&rt5677_adda1_mux),
SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
&rt5677_dac12_mux),
SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
&rt5677_dac3_mux),
/* DAC2 channel Mux */
SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
&rt5677_dac2_l_mux),
SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
&rt5677_dac2_r_mux),
/* DAC3 channel Mux */
SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
&rt5677_dac3_l_mux),
SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
&rt5677_dac3_r_mux),
/* DAC4 channel Mux */
SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
&rt5677_dac4_l_mux),
SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
&rt5677_dac4_r_mux),
/* DAC Mixer */
SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
RT5677_PWR_DAC_S1F_BIT, 0, rt5677_filter_power_event,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY("dac mono2 left filter", RT5677_PWR_DIG2,
RT5677_PWR_DAC_M2F_L_BIT, 0, rt5677_filter_power_event,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY("dac mono2 right filter", RT5677_PWR_DIG2,
RT5677_PWR_DAC_M2F_R_BIT, 0, rt5677_filter_power_event,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY("dac mono3 left filter", RT5677_PWR_DIG2,
RT5677_PWR_DAC_M3F_L_BIT, 0, rt5677_filter_power_event,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY("dac mono3 right filter", RT5677_PWR_DIG2,
RT5677_PWR_DAC_M3F_R_BIT, 0, rt5677_filter_power_event,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY("dac mono4 left filter", RT5677_PWR_DIG2,
RT5677_PWR_DAC_M4F_L_BIT, 0, rt5677_filter_power_event,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY("dac mono4 right filter", RT5677_PWR_DIG2,
RT5677_PWR_DAC_M4F_R_BIT, 0, rt5677_filter_power_event,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
/* DACs */
SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
RT5677_PWR_DAC1_BIT, 0),
SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
RT5677_PWR_DAC2_BIT, 0),
SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
RT5677_PWR_DAC3_BIT, 0),
/* PDM */
SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
RT5677_PWR_PDM1_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
RT5677_PWR_PDM2_BIT, 0, NULL, 0),
SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
1, &rt5677_pdm1_l_mux),
SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
1, &rt5677_pdm1_r_mux),
SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
1, &rt5677_pdm2_l_mux),
SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
1, &rt5677_pdm2_r_mux),
SND_SOC_DAPM_PGA_S("LOUT1 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
0, NULL, 0),
SND_SOC_DAPM_PGA_S("LOUT2 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
0, NULL, 0),
SND_SOC_DAPM_PGA_S("LOUT3 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
0, NULL, 0),
SND_SOC_DAPM_PGA_S("LOUT1 vref", 1, SND_SOC_NOPM, 0, 0,
rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_S("LOUT2 vref", 1, SND_SOC_NOPM, 0, 0,
rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_S("LOUT3 vref", 1, SND_SOC_NOPM, 0, 0,
rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
/* Output Lines */
SND_SOC_DAPM_OUTPUT("LOUT1"),
SND_SOC_DAPM_OUTPUT("LOUT2"),
SND_SOC_DAPM_OUTPUT("LOUT3"),
SND_SOC_DAPM_OUTPUT("PDM1L"),
SND_SOC_DAPM_OUTPUT("PDM1R"),
SND_SOC_DAPM_OUTPUT("PDM2L"),
SND_SOC_DAPM_OUTPUT("PDM2R"),
SND_SOC_DAPM_POST("vref", rt5677_vref_event),
};
static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
{ "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", rt5677_dmic_use_asrc },
{ "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", rt5677_dmic_use_asrc },
{ "Stereo3 DMIC Mux", NULL, "DMIC STO3 ASRC", rt5677_dmic_use_asrc },
{ "Stereo4 DMIC Mux", NULL, "DMIC STO4 ASRC", rt5677_dmic_use_asrc },
{ "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", rt5677_dmic_use_asrc },
{ "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", rt5677_dmic_use_asrc },
{ "I2S1", NULL, "I2S1 ASRC", can_use_asrc},
{ "I2S2", NULL, "I2S2 ASRC", can_use_asrc},
{ "I2S3", NULL, "I2S3 ASRC", can_use_asrc},
{ "I2S4", NULL, "I2S4 ASRC", can_use_asrc},
{ "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
{ "dac mono2 left filter", NULL, "DAC MONO2 L ASRC", is_using_asrc },
{ "dac mono2 right filter", NULL, "DAC MONO2 R ASRC", is_using_asrc },
{ "dac mono3 left filter", NULL, "DAC MONO3 L ASRC", is_using_asrc },
{ "dac mono3 right filter", NULL, "DAC MONO3 R ASRC", is_using_asrc },
{ "dac mono4 left filter", NULL, "DAC MONO4 L ASRC", is_using_asrc },
{ "dac mono4 right filter", NULL, "DAC MONO4 R ASRC", is_using_asrc },
{ "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
{ "adc stereo2 filter", NULL, "ADC STO2 ASRC", is_using_asrc },
{ "adc stereo3 filter", NULL, "ADC STO3 ASRC", is_using_asrc },
{ "adc stereo4 filter", NULL, "ADC STO4 ASRC", is_using_asrc },
{ "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
{ "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
{ "DMIC1", NULL, "DMIC L1" },
{ "DMIC1", NULL, "DMIC R1" },
{ "DMIC2", NULL, "DMIC L2" },
{ "DMIC2", NULL, "DMIC R2" },
{ "DMIC3", NULL, "DMIC L3" },
{ "DMIC3", NULL, "DMIC R3" },
{ "DMIC4", NULL, "DMIC L4" },
{ "DMIC4", NULL, "DMIC R4" },
{ "DMIC L1", NULL, "DMIC CLK" },
{ "DMIC R1", NULL, "DMIC CLK" },
{ "DMIC L2", NULL, "DMIC CLK" },
{ "DMIC R2", NULL, "DMIC CLK" },
{ "DMIC L3", NULL, "DMIC CLK" },
{ "DMIC R3", NULL, "DMIC CLK" },
{ "DMIC L4", NULL, "DMIC CLK" },
{ "DMIC R4", NULL, "DMIC CLK" },
{ "DMIC L1", NULL, "DMIC1 power" },
{ "DMIC R1", NULL, "DMIC1 power" },
{ "DMIC L3", NULL, "DMIC3 power" },
{ "DMIC R3", NULL, "DMIC3 power" },
{ "DMIC L4", NULL, "DMIC4 power" },
{ "DMIC R4", NULL, "DMIC4 power" },
{ "BST1", NULL, "IN1P" },
{ "BST1", NULL, "IN1N" },
{ "BST2", NULL, "IN2P" },
{ "BST2", NULL, "IN2N" },
{ "IN1P", NULL, "MICBIAS1" },
{ "IN1N", NULL, "MICBIAS1" },
{ "IN2P", NULL, "MICBIAS1" },
{ "IN2N", NULL, "MICBIAS1" },
{ "ADC 1", NULL, "BST1" },
{ "ADC 1", NULL, "ADC 1 power" },
{ "ADC 1", NULL, "ADC1 clock" },
{ "ADC 2", NULL, "BST2" },
{ "ADC 2", NULL, "ADC 2 power" },
{ "ADC 2", NULL, "ADC2 clock" },
{ "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
{ "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
{ "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
{ "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
{ "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
{ "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
{ "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
{ "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
{ "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
{ "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
{ "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
{ "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
{ "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
{ "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
{ "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
{ "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
{ "Mono DMIC L Mux", "DMIC1", "DMIC1" },
{ "Mono DMIC L Mux", "DMIC2", "DMIC2" },
{ "Mono DMIC L Mux", "DMIC3", "DMIC3" },
{ "Mono DMIC L Mux", "DMIC4", "DMIC4" },
{ "Mono DMIC R Mux", "DMIC1", "DMIC1" },
{ "Mono DMIC R Mux", "DMIC2", "DMIC2" },
{ "Mono DMIC R Mux", "DMIC3", "DMIC3" },
{ "Mono DMIC R Mux", "DMIC4", "DMIC4" },
{ "ADC 1_2", NULL, "ADC 1" },
{ "ADC 1_2", NULL, "ADC 2" },
{ "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
{ "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
{ "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
{ "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
{ "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
{ "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
{ "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
{ "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
{ "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
{ "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
{ "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
{ "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
{ "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
{ "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
{ "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
{ "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
{ "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
{ "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
{ "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
{ "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
{ "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
{ "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
{ "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
{ "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
{ "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
{ "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
{ "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
{ "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
{ "Mono ADC1 L Mux", "ADC1", "ADC 1" },
{ "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
{ "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
{ "Mono ADC1 R Mux", "ADC2", "ADC 2" },
{ "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
{ "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
{ "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
{ "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
{ "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
{ "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
{ "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
{ "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
{ "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
{ "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
{ "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
{ "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
{ "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
{ "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
{ "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
{ "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
{ "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
{ "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
{ "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
{ "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
{ "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
{ "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
{ "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
{ "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
{ "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
{ "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
{ "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
{ "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
{ "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
{ "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
{ "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
{ "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
{ "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
{ "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
{ "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
{ "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
{ "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
{ "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
{ "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
{ "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
{ "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
{ "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
{ "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
{ "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
{ "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
{ "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
{ "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
{ "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
{ "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
{ "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
{ "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
{ "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
{ "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
{ "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
{ "Mono ADC MIXL", NULL, "adc mono left filter" },
{ "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
{ "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
{ "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
{ "Mono ADC MIXR", NULL, "adc mono right filter" },
{ "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
{ "Mono ADC MIX", NULL, "Mono ADC MIXL" },
{ "Mono ADC MIX", NULL, "Mono ADC MIXR" },
{ "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
{ "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
{ "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
{ "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
{ "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
{ "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
{ "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
{ "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
{ "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
{ "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
{ "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
{ "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
{ "IF1 ADC3 Mux", "OB45", "OB45" },
{ "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
{ "IF1 ADC4 Mux", "OB67", "OB67" },
{ "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
{ "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" },
{ "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" },
{ "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" },
{ "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" },
{ "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" },
{ "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" },
{ "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" },
{ "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" },
{ "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" },
{ "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" },
{ "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" },
{ "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" },
{ "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" },
{ "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" },
{ "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" },
{ "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" },
{ "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" },
{ "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" },
{ "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" },
{ "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" },
{ "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" },
{ "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" },
{ "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" },
{ "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" },
{ "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" },
{ "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" },
{ "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" },
{ "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" },
{ "AIF1TX", NULL, "I2S1" },
{ "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" },
{ "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
{ "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
{ "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
{ "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
{ "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
{ "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
{ "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
{ "IF2 ADC3 Mux", "OB45", "OB45" },
{ "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
{ "IF2 ADC4 Mux", "OB67", "OB67" },
{ "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
{ "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" },
{ "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" },
{ "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" },
{ "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" },
{ "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" },
{ "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" },
{ "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" },
{ "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" },
{ "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" },
{ "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" },
{ "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" },
{ "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" },
{ "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" },
{ "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" },
{ "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" },
{ "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" },
{ "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" },
{ "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" },
{ "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" },
{ "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" },
{ "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" },
{ "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" },
{ "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" },
{ "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" },
{ "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" },
{ "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" },
{ "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" },
{ "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" },
{ "AIF2TX", NULL, "I2S2" },
{ "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" },
{ "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
{ "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
{ "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
{ "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
{ "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
{ "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
{ "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
{ "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
{ "AIF3TX", NULL, "I2S3" },
{ "AIF3TX", NULL, "IF3 ADC Mux" },
{ "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
{ "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
{ "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
{ "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
{ "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
{ "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
{ "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
{ "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
{ "AIF4TX", NULL, "I2S4" },
{ "AIF4TX", NULL, "IF4 ADC Mux" },
{ "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
{ "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
{ "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
{ "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
{ "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
{ "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
{ "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
{ "SLB ADC3 Mux", "OB45", "OB45" },
{ "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
{ "SLB ADC4 Mux", "OB67", "OB67" },
{ "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
{ "SLBTX", NULL, "SLB" },
{ "SLBTX", NULL, "SLB ADC1 Mux" },
{ "SLBTX", NULL, "SLB ADC2 Mux" },
{ "SLBTX", NULL, "SLB ADC3 Mux" },
{ "SLBTX", NULL, "SLB ADC4 Mux" },
{ "DSPTX", NULL, "IB01 Bypass Mux" },
{ "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
{ "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
{ "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
{ "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
/* The IB01 Mux controls the source for InBound0 and InBound1.
* When the mux option "VAD ADC/DAC1 FS" is selected, "VAD ADC" goes to
* InBound0 and "DAC1 FS" goes to InBound1. "VAD ADC" is used for
* hotwording. "DAC1 FS" is not used currently.
*
* Creating a common widget node for "VAD ADC" + "DAC1 FS" and
* connecting the common widget to IB01 Mux causes the issue where
* there is an active path going from system playback -> "DAC1 FS" ->
* IB01 Mux -> DSP Buffer -> hotword stream. This wrong path confuses
* DAPM. Therefore "DAC1 FS" is ignored for now.
*/
{ "IB01 Mux", "VAD ADC/DAC1 FS", "VAD ADC Mux" },
{ "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
{ "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
{ "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
{ "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
{ "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
{ "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
{ "IB23 Mux", "DAC1 FS", "DAC1 FS" },
{ "IB23 Mux", "IF4 DAC", "IF4 DAC" },
{ "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
{ "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
{ "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
{ "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
{ "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
{ "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
{ "IB45 Mux", "IF3 DAC", "IF3 DAC" },
{ "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
{ "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
{ "IB6 Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
{ "IB6 Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
{ "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
{ "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
{ "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
{ "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
{ "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
{ "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
{ "IB7 Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
{ "IB7 Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
{ "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
{ "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
{ "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
{ "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
{ "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
{ "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
{ "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
{ "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
{ "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
{ "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
{ "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
{ "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
{ "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
{ "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
{ "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
{ "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
{ "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
{ "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
{ "IB9 Mux", "DAC1 FS", "DAC1 FS" },
{ "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
{ "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
{ "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
{ "OB01 MIX", "IB6 Switch", "IB6 Mux" },
{ "OB01 MIX", "IB7 Switch", "IB7 Mux" },
{ "OB01 MIX", "IB8 Switch", "IB8 Mux" },
{ "OB01 MIX", "IB9 Switch", "IB9 Mux" },
{ "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
{ "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
{ "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
{ "OB23 MIX", "IB6 Switch", "IB6 Mux" },
{ "OB23 MIX", "IB7 Switch", "IB7 Mux" },
{ "OB23 MIX", "IB8 Switch", "IB8 Mux" },
{ "OB23 MIX", "IB9 Switch", "IB9 Mux" },
{ "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
{ "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
{ "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
{ "OB4 MIX", "IB6 Switch", "IB6 Mux" },
{ "OB4 MIX", "IB7 Switch", "IB7 Mux" },
{ "OB4 MIX", "IB8 Switch", "IB8 Mux" },
{ "OB4 MIX", "IB9 Switch", "IB9 Mux" },
{ "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
{ "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
{ "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
{ "OB5 MIX", "IB6 Switch", "IB6 Mux" },
{ "OB5 MIX", "IB7 Switch", "IB7 Mux" },
{ "OB5 MIX", "IB8 Switch", "IB8 Mux" },
{ "OB5 MIX", "IB9 Switch", "IB9 Mux" },
{ "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
{ "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
{ "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
{ "OB6 MIX", "IB6 Switch", "IB6 Mux" },
{ "OB6 MIX", "IB7 Switch", "IB7 Mux" },
{ "OB6 MIX", "IB8 Switch", "IB8 Mux" },
{ "OB6 MIX", "IB9 Switch", "IB9 Mux" },
{ "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
{ "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
{ "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
{ "OB7 MIX", "IB6 Switch", "IB6 Mux" },
{ "OB7 MIX", "IB7 Switch", "IB7 Mux" },
{ "OB7 MIX", "IB8 Switch", "IB8 Mux" },
{ "OB7 MIX", "IB9 Switch", "IB9 Mux" },
{ "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
{ "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
{ "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
{ "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
{ "OutBound2", NULL, "OB23 Bypass Mux" },
{ "OutBound3", NULL, "OB23 Bypass Mux" },
{ "OutBound4", NULL, "OB4 MIX" },
{ "OutBound5", NULL, "OB5 MIX" },
{ "OutBound6", NULL, "OB6 MIX" },
{ "OutBound7", NULL, "OB7 MIX" },
{ "OB45", NULL, "OutBound4" },
{ "OB45", NULL, "OutBound5" },
{ "OB67", NULL, "OutBound6" },
{ "OB67", NULL, "OutBound7" },
{ "IF1 DAC0", NULL, "AIF1RX" },
{ "IF1 DAC1", NULL, "AIF1RX" },
{ "IF1 DAC2", NULL, "AIF1RX" },
{ "IF1 DAC3", NULL, "AIF1RX" },
{ "IF1 DAC4", NULL, "AIF1RX" },
{ "IF1 DAC5", NULL, "AIF1RX" },
{ "IF1 DAC6", NULL, "AIF1RX" },
{ "IF1 DAC7", NULL, "AIF1RX" },
{ "IF1 DAC0", NULL, "I2S1" },
{ "IF1 DAC1", NULL, "I2S1" },
{ "IF1 DAC2", NULL, "I2S1" },
{ "IF1 DAC3", NULL, "I2S1" },
{ "IF1 DAC4", NULL, "I2S1" },
{ "IF1 DAC5", NULL, "I2S1" },
{ "IF1 DAC6", NULL, "I2S1" },
{ "IF1 DAC7", NULL, "I2S1" },
{ "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" },
{ "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" },
{ "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" },
{ "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" },
{ "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" },
{ "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" },
{ "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" },
{ "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" },
{ "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" },
{ "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" },
{ "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" },
{ "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" },
{ "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" },
{ "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" },
{ "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" },
{ "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" },
{ "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" },
{ "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" },
{ "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" },
{ "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" },
{ "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" },
{ "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" },
{ "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" },
{ "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" },
{ "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" },
{ "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" },
{ "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" },
{ "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" },
{ "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" },
{ "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" },
{ "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" },
{ "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" },
{ "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" },
{ "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" },
{ "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" },
{ "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" },
{ "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" },
{ "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" },
{ "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" },
{ "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" },
{ "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" },
{ "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" },
{ "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" },
{ "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" },
{ "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" },
{ "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" },
{ "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" },
{ "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" },
{ "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" },
{ "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" },
{ "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" },
{ "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" },
{ "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" },
{ "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" },
{ "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" },
{ "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" },
{ "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" },
{ "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" },
{ "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" },
{ "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" },
{ "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" },
{ "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" },
{ "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" },
{ "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" },
{ "IF1 DAC01", NULL, "IF1 DAC0 Mux" },
{ "IF1 DAC01", NULL, "IF1 DAC1 Mux" },
{ "IF1 DAC23", NULL, "IF1 DAC2 Mux" },
{ "IF1 DAC23", NULL, "IF1 DAC3 Mux" },
{ "IF1 DAC45", NULL, "IF1 DAC4 Mux" },
{ "IF1 DAC45", NULL, "IF1 DAC5 Mux" },
{ "IF1 DAC67", NULL, "IF1 DAC6 Mux" },
{ "IF1 DAC67", NULL, "IF1 DAC7 Mux" },
{ "IF2 DAC0", NULL, "AIF2RX" },
{ "IF2 DAC1", NULL, "AIF2RX" },
{ "IF2 DAC2", NULL, "AIF2RX" },
{ "IF2 DAC3", NULL, "AIF2RX" },
{ "IF2 DAC4", NULL, "AIF2RX" },
{ "IF2 DAC5", NULL, "AIF2RX" },
{ "IF2 DAC6", NULL, "AIF2RX" },
{ "IF2 DAC7", NULL, "AIF2RX" },
{ "IF2 DAC0", NULL, "I2S2" },
{ "IF2 DAC1", NULL, "I2S2" },
{ "IF2 DAC2", NULL, "I2S2" },
{ "IF2 DAC3", NULL, "I2S2" },
{ "IF2 DAC4", NULL, "I2S2" },
{ "IF2 DAC5", NULL, "I2S2" },
{ "IF2 DAC6", NULL, "I2S2" },
{ "IF2 DAC7", NULL, "I2S2" },
{ "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" },
{ "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" },
{ "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" },
{ "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" },
{ "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" },
{ "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" },
{ "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" },
{ "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" },
{ "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" },
{ "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" },
{ "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" },
{ "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" },
{ "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" },
{ "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" },
{ "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" },
{ "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" },
{ "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" },
{ "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" },
{ "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" },
{ "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" },
{ "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" },
{ "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" },
{ "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" },
{ "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" },
{ "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" },
{ "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" },
{ "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" },
{ "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" },
{ "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" },
{ "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" },
{ "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" },
{ "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" },
{ "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" },
{ "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" },
{ "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" },
{ "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" },
{ "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" },
{ "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" },
{ "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" },
{ "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" },
{ "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" },
{ "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" },
{ "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" },
{ "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" },
{ "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" },
{ "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" },
{ "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" },
{ "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" },
{ "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" },
{ "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" },
{ "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" },
{ "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" },
{ "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" },
{ "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" },
{ "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" },
{ "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" },
{ "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" },
{ "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" },
{ "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" },
{ "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" },
{ "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" },
{ "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" },
{ "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" },
{ "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" },
{ "IF2 DAC01", NULL, "IF2 DAC0 Mux" },
{ "IF2 DAC01", NULL, "IF2 DAC1 Mux" },
{ "IF2 DAC23", NULL, "IF2 DAC2 Mux" },
{ "IF2 DAC23", NULL, "IF2 DAC3 Mux" },
{ "IF2 DAC45", NULL, "IF2 DAC4 Mux" },
{ "IF2 DAC45", NULL, "IF2 DAC5 Mux" },
{ "IF2 DAC67", NULL, "IF2 DAC6 Mux" },
{ "IF2 DAC67", NULL, "IF2 DAC7 Mux" },
{ "IF3 DAC", NULL, "AIF3RX" },
{ "IF3 DAC", NULL, "I2S3" },
{ "IF4 DAC", NULL, "AIF4RX" },
{ "IF4 DAC", NULL, "I2S4" },
{ "IF3 DAC L", NULL, "IF3 DAC" },
{ "IF3 DAC R", NULL, "IF3 DAC" },
{ "IF4 DAC L", NULL, "IF4 DAC" },
{ "IF4 DAC R", NULL, "IF4 DAC" },
{ "SLB DAC0", NULL, "SLBRX" },
{ "SLB DAC1", NULL, "SLBRX" },
{ "SLB DAC2", NULL, "SLBRX" },
{ "SLB DAC3", NULL, "SLBRX" },
{ "SLB DAC4", NULL, "SLBRX" },
{ "SLB DAC5", NULL, "SLBRX" },
{ "SLB DAC6", NULL, "SLBRX" },
{ "SLB DAC7", NULL, "SLBRX" },
{ "SLB DAC0", NULL, "SLB" },
{ "SLB DAC1", NULL, "SLB" },
{ "SLB DAC2", NULL, "SLB" },
{ "SLB DAC3", NULL, "SLB" },
{ "SLB DAC4", NULL, "SLB" },
{ "SLB DAC5", NULL, "SLB" },
{ "SLB DAC6", NULL, "SLB" },
{ "SLB DAC7", NULL, "SLB" },
{ "SLB DAC01", NULL, "SLB DAC0" },
{ "SLB DAC01", NULL, "SLB DAC1" },
{ "SLB DAC23", NULL, "SLB DAC2" },
{ "SLB DAC23", NULL, "SLB DAC3" },
{ "SLB DAC45", NULL, "SLB DAC4" },
{ "SLB DAC45", NULL, "SLB DAC5" },
{ "SLB DAC67", NULL, "SLB DAC6" },
{ "SLB DAC67", NULL, "SLB DAC7" },
{ "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
{ "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
{ "ADDA1 Mux", "OB 67", "OB67" },
{ "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
{ "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
{ "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
{ "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
{ "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
{ "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
{ "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
{ "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
{ "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
{ "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
{ "DAC1 FS", NULL, "DAC1 MIXL" },
{ "DAC1 FS", NULL, "DAC1 MIXR" },
{ "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2 Mux" },
{ "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2 Mux" },
{ "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
{ "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
{ "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
{ "DAC2 L Mux", "OB 2", "OutBound2" },
{ "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3 Mux" },
{ "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3 Mux" },
{ "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
{ "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
{ "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
{ "DAC2 R Mux", "OB 3", "OutBound3" },
{ "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
{ "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
{ "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4 Mux" },
{ "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4 Mux" },
{ "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
{ "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
{ "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
{ "DAC3 L Mux", "OB 4", "OutBound4" },
{ "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC5 Mux" },
{ "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC5 Mux" },
{ "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
{ "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
{ "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
{ "DAC3 R Mux", "OB 5", "OutBound5" },
{ "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
{ "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
{ "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
{ "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
{ "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
{ "DAC4 L Mux", "OB 6", "OutBound6" },
{ "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
{ "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
{ "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
{ "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
{ "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
{ "DAC4 R Mux", "OB 7", "OutBound7" },
{ "Sidetone Mux", "DMIC1 L", "DMIC L1" },
{ "Sidetone Mux", "DMIC2 L", "DMIC L2" },
{ "Sidetone Mux", "DMIC3 L", "DMIC L3" },
{ "Sidetone Mux", "DMIC4 L", "DMIC L4" },
{ "Sidetone Mux", "ADC1", "ADC 1" },
{ "Sidetone Mux", "ADC2", "ADC 2" },
{ "Sidetone Mux", NULL, "Sidetone Power" },
{ "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
{ "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
{ "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
{ "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
{ "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
{ "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
{ "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
{ "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
{ "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
{ "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
{ "dac stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
{ "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
{ "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
{ "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
{ "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
{ "Mono DAC MIXL", NULL, "dac mono2 left filter" },
{ "dac mono2 left filter", NULL, "PLL1", is_sys_clk_from_pll },
{ "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
{ "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
{ "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
{ "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
{ "Mono DAC MIXR", NULL, "dac mono2 right filter" },
{ "dac mono2 right filter", NULL, "PLL1", is_sys_clk_from_pll },
{ "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
{ "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
{ "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
{ "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
{ "DD1 MIXL", NULL, "dac mono3 left filter" },
{ "dac mono3 left filter", NULL, "PLL1", is_sys_clk_from_pll },
{ "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
{ "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
{ "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
{ "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
{ "DD1 MIXR", NULL, "dac mono3 right filter" },
{ "dac mono3 right filter", NULL, "PLL1", is_sys_clk_from_pll },
{ "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
{ "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
{ "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
{ "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
{ "DD2 MIXL", NULL, "dac mono4 left filter" },
{ "dac mono4 left filter", NULL, "PLL1", is_sys_clk_from_pll },
{ "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
{ "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
{ "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
{ "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
{ "DD2 MIXR", NULL, "dac mono4 right filter" },
{ "dac mono4 right filter", NULL, "PLL1", is_sys_clk_from_pll },
{ "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
{ "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
{ "Mono DAC MIX", NULL, "Mono DAC MIXL" },
{ "Mono DAC MIX", NULL, "Mono DAC MIXR" },
{ "DD1 MIX", NULL, "DD1 MIXL" },
{ "DD1 MIX", NULL, "DD1 MIXR" },
{ "DD2 MIX", NULL, "DD2 MIXL" },
{ "DD2 MIX", NULL, "DD2 MIXR" },
{ "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
{ "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
{ "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
{ "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
{ "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
{ "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
{ "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
{ "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
{ "DAC 1", NULL, "DAC12 SRC Mux" },
{ "DAC 2", NULL, "DAC12 SRC Mux" },
{ "DAC 3", NULL, "DAC3 SRC Mux" },
{ "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
{ "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
{ "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
{ "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
{ "PDM1 L Mux", NULL, "PDM1 Power" },
{ "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
{ "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
{ "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
{ "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
{ "PDM1 R Mux", NULL, "PDM1 Power" },
{ "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
{ "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
{ "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
{ "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
{ "PDM2 L Mux", NULL, "PDM2 Power" },
{ "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
{ "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
{ "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
{ "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
{ "PDM2 R Mux", NULL, "PDM2 Power" },
{ "LOUT1 amp", NULL, "DAC 1" },
{ "LOUT2 amp", NULL, "DAC 2" },
{ "LOUT3 amp", NULL, "DAC 3" },
{ "LOUT1 vref", NULL, "LOUT1 amp" },
{ "LOUT2 vref", NULL, "LOUT2 amp" },
{ "LOUT3 vref", NULL, "LOUT3 amp" },
{ "LOUT1", NULL, "LOUT1 vref" },
{ "LOUT2", NULL, "LOUT2 vref" },
{ "LOUT3", NULL, "LOUT3 vref" },
{ "PDM1L", NULL, "PDM1 L Mux" },
{ "PDM1R", NULL, "PDM1 R Mux" },
{ "PDM2L", NULL, "PDM2 L Mux" },
{ "PDM2R", NULL, "PDM2 R Mux" },
};
static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = {
{ "DMIC L2", NULL, "DMIC1 power" },
{ "DMIC R2", NULL, "DMIC1 power" },
};
static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = {
{ "DMIC L2", NULL, "DMIC2 power" },
{ "DMIC R2", NULL, "DMIC2 power" },
};
static int rt5677_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
unsigned int val_len = 0, val_clk, mask_clk;
int pre_div, bclk_ms, frame_size;
rt5677->lrck[dai->id] = params_rate(params);
pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
if (pre_div < 0) {
dev_err(component->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n",
rt5677->sysclk, rt5677->lrck[dai->id]);
return -EINVAL;
}
frame_size = snd_soc_params_to_frame_size(params);
if (frame_size < 0) {
dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
return -EINVAL;
}
bclk_ms = frame_size > 32;
rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
bclk_ms, pre_div, dai->id);
switch (params_width(params)) {
case 16:
break;
case 20:
val_len |= RT5677_I2S_DL_20;
break;
case 24:
val_len |= RT5677_I2S_DL_24;
break;
case 8:
val_len |= RT5677_I2S_DL_8;
break;
default:
return -EINVAL;
}
switch (dai->id) {
case RT5677_AIF1:
mask_clk = RT5677_I2S_PD1_MASK;
val_clk = pre_div << RT5677_I2S_PD1_SFT;
regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
RT5677_I2S_DL_MASK, val_len);
regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
mask_clk, val_clk);
break;
case RT5677_AIF2:
mask_clk = RT5677_I2S_PD2_MASK;
val_clk = pre_div << RT5677_I2S_PD2_SFT;
regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
RT5677_I2S_DL_MASK, val_len);
regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
mask_clk, val_clk);
break;
case RT5677_AIF3:
mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK;
val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT |
pre_div << RT5677_I2S_PD3_SFT;
regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
RT5677_I2S_DL_MASK, val_len);
regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
mask_clk, val_clk);
break;
case RT5677_AIF4:
mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK;
val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT |
pre_div << RT5677_I2S_PD4_SFT;
regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
RT5677_I2S_DL_MASK, val_len);
regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
mask_clk, val_clk);
break;
default:
break;
}
return 0;
}
static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
rt5677->master[dai->id] = 1;
break;
case SND_SOC_DAIFMT_CBS_CFS:
reg_val |= RT5677_I2S_MS_S;
rt5677->master[dai->id] = 0;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
reg_val |= RT5677_I2S_BP_INV;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_LEFT_J:
reg_val |= RT5677_I2S_DF_LEFT;
break;
case SND_SOC_DAIFMT_DSP_A:
reg_val |= RT5677_I2S_DF_PCM_A;
break;
case SND_SOC_DAIFMT_DSP_B:
reg_val |= RT5677_I2S_DF_PCM_B;
break;
default:
return -EINVAL;
}
switch (dai->id) {
case RT5677_AIF1:
regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
RT5677_I2S_DF_MASK, reg_val);
break;
case RT5677_AIF2:
regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
RT5677_I2S_DF_MASK, reg_val);
break;
case RT5677_AIF3:
regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
RT5677_I2S_DF_MASK, reg_val);
break;
case RT5677_AIF4:
regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
RT5677_I2S_DF_MASK, reg_val);
break;
default:
break;
}
return 0;
}
static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0;
if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
return 0;
switch (clk_id) {
case RT5677_SCLK_S_MCLK:
reg_val |= RT5677_SCLK_SRC_MCLK;
break;
case RT5677_SCLK_S_PLL1:
reg_val |= RT5677_SCLK_SRC_PLL1;
break;
case RT5677_SCLK_S_RCCLK:
reg_val |= RT5677_SCLK_SRC_RCCLK;
break;
default:
dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
return -EINVAL;
}
regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
RT5677_SCLK_SRC_MASK, reg_val);
rt5677->sysclk = freq;
rt5677->sysclk_src = clk_id;
dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
return 0;
}
/**
* rt5677_pll_calc - Calcualte PLL M/N/K code.
* @freq_in: external clock provided to codec.
* @freq_out: target clock which codec works on.
* @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag.
*
* Calcualte M/N/K code and bypass K/M flag to configure PLL for codec.
*
* Returns 0 for success or negative error code.
*/
static int rt5677_pll_calc(const unsigned int freq_in,
const unsigned int freq_out, struct rl6231_pll_code *pll_code)
{
if (RT5677_PLL_INP_MIN > freq_in)
return -EINVAL;
return rl6231_pll_calc(freq_in, freq_out, pll_code);
}
static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
unsigned int freq_in, unsigned int freq_out)
{
struct snd_soc_component *component = dai->component;
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
struct rl6231_pll_code pll_code;
int ret;
if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
freq_out == rt5677->pll_out)
return 0;
if (!freq_in || !freq_out) {
dev_dbg(component->dev, "PLL disabled\n");
rt5677->pll_in = 0;
rt5677->pll_out = 0;
regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
return 0;
}
switch (source) {
case RT5677_PLL1_S_MCLK:
regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
break;
case RT5677_PLL1_S_BCLK1:
case RT5677_PLL1_S_BCLK2:
case RT5677_PLL1_S_BCLK3:
case RT5677_PLL1_S_BCLK4:
switch (dai->id) {
case RT5677_AIF1:
regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
break;
case RT5677_AIF2:
regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
break;
case RT5677_AIF3:
regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
break;
case RT5677_AIF4:
regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
break;
default:
break;
}
break;
default:
dev_err(component->dev, "Unknown PLL source %d\n", source);
return -EINVAL;
}
ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
if (ret < 0) {
dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
return ret;
}
dev_dbg(component->dev, "m_bypass=%d m=%d n=%d k=%d\n",
pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
pll_code.n_code, pll_code.k_code);
regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code);
regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
((pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT) |
(pll_code.m_bp << RT5677_PLL_M_BP_SFT));
rt5677->pll_in = freq_in;
rt5677->pll_out = freq_out;
rt5677->pll_src = source;
return 0;
}
static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
unsigned int val = 0, slot_width_25 = 0;
if (rx_mask || tx_mask)
val |= (1 << 12);
switch (slots) {
case 4:
val |= (1 << 10);
break;
case 6:
val |= (2 << 10);
break;
case 8:
val |= (3 << 10);
break;
case 2:
default:
break;
}
switch (slot_width) {
case 20:
val |= (1 << 8);
break;
case 25:
slot_width_25 = 0x8080;
fallthrough;
case 24:
val |= (2 << 8);
break;
case 32:
val |= (3 << 8);
break;
case 16:
default:
break;
}
switch (dai->id) {
case RT5677_AIF1:
regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 0x1f00,
val);
regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x8000,
slot_width_25);
break;
case RT5677_AIF2:
regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 0x1f00,
val);
regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x80,
slot_width_25);
break;
default:
break;
}
return 0;
}
static int rt5677_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
enum snd_soc_bias_level prev_bias =
snd_soc_component_get_bias_level(component);
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
if (prev_bias == SND_SOC_BIAS_STANDBY) {
regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
5 << RT5677_LDO1_SEL_SFT |
5 << RT5677_LDO2_SEL_SFT);
regmap_update_bits(rt5677->regmap,
RT5677_PR_BASE + RT5677_BIAS_CUR4,
0x0f00, 0x0f00);
regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
RT5677_PWR_FV1 | RT5677_PWR_FV2 |
RT5677_PWR_VREF1 | RT5677_PWR_MB |
RT5677_PWR_BG | RT5677_PWR_VREF2,
RT5677_PWR_VREF1 | RT5677_PWR_MB |
RT5677_PWR_BG | RT5677_PWR_VREF2);
rt5677->is_vref_slow = false;
regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
RT5677_PWR_CORE, RT5677_PWR_CORE);
regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
0x1, 0x1);
}
break;
case SND_SOC_BIAS_STANDBY:
if (prev_bias == SND_SOC_BIAS_OFF &&
rt5677->dsp_vad_en_request) {
/* Re-enable the DSP if it was turned off at suspend */
rt5677->dsp_vad_en = true;
/* The delay is to wait for MCLK */
schedule_delayed_work(&rt5677->dsp_work,
msecs_to_jiffies(1000));
}
break;
case SND_SOC_BIAS_OFF:
flush_delayed_work(&rt5677->dsp_work);
if (rt5677->is_dsp_mode) {
/* Turn off the DSP before suspend */
rt5677->dsp_vad_en = false;
schedule_delayed_work(&rt5677->dsp_work, 0);
flush_delayed_work(&rt5677->dsp_work);
}
regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
regmap_write(rt5677->regmap, RT5677_PWR_ANLG1,
2 << RT5677_LDO1_SEL_SFT |
2 << RT5677_LDO2_SEL_SFT);
regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
RT5677_PWR_CORE, 0);
regmap_update_bits(rt5677->regmap,
RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
if (rt5677->dsp_vad_en)
rt5677_set_dsp_vad(component, true);
break;
default:
break;
}
return 0;
}
static int rt5677_update_gpio_bits(struct rt5677_priv *rt5677, unsigned offset, int m, int v)
{
unsigned int bank = offset / 5;
unsigned int shift = (offset % 5) * 3;
unsigned int reg = bank ? RT5677_GPIO_CTRL3 : RT5677_GPIO_CTRL2;
return regmap_update_bits(rt5677->regmap, reg, m << shift, v << shift);
}
#ifdef CONFIG_GPIOLIB
static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
int level = value ? RT5677_GPIOx_OUT_HI : RT5677_GPIOx_OUT_LO;
int m = RT5677_GPIOx_OUT_MASK;
rt5677_update_gpio_bits(rt5677, offset, m, level);
}
static int rt5677_gpio_direction_out(struct gpio_chip *chip,
unsigned offset, int value)
{
struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
int level = value ? RT5677_GPIOx_OUT_HI : RT5677_GPIOx_OUT_LO;
int m = RT5677_GPIOx_DIR_MASK | RT5677_GPIOx_OUT_MASK;
int v = RT5677_GPIOx_DIR_OUT | level;
return rt5677_update_gpio_bits(rt5677, offset, m, v);
}
static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
int value, ret;
ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value);
if (ret < 0)
return ret;
return (value & (0x1 << offset)) >> offset;
}
static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
{
struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
int m = RT5677_GPIOx_DIR_MASK;
int v = RT5677_GPIOx_DIR_IN;
return rt5677_update_gpio_bits(rt5677, offset, m, v);
}
/*
* Configures the GPIO as
* 0 - floating
* 1 - pull down
* 2 - pull up
*/
static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
int value)
{
int shift;
switch (offset) {
case RT5677_GPIO1 ... RT5677_GPIO2:
shift = 2 * (1 - offset);
regmap_update_bits(rt5677->regmap,
RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2,
0x3 << shift,
(value & 0x3) << shift);
break;
case RT5677_GPIO3 ... RT5677_GPIO6:
shift = 2 * (9 - offset);
regmap_update_bits(rt5677->regmap,
RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3,
0x3 << shift,
(value & 0x3) << shift);
break;
default:
break;
}
}
static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset)
{
struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
int irq;
if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) ||
(rt5677->pdata.jd1_gpio == 2 &&
offset == RT5677_GPIO2) ||
(rt5677->pdata.jd1_gpio == 3 &&
offset == RT5677_GPIO3)) {
irq = RT5677_IRQ_JD1;
} else if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) ||
(rt5677->pdata.jd2_gpio == 2 &&
offset == RT5677_GPIO5) ||
(rt5677->pdata.jd2_gpio == 3 &&
offset == RT5677_GPIO6)) {
irq = RT5677_IRQ_JD2;
} else if ((rt5677->pdata.jd3_gpio == 1 &&
offset == RT5677_GPIO4) ||
(rt5677->pdata.jd3_gpio == 2 &&
offset == RT5677_GPIO5) ||
(rt5677->pdata.jd3_gpio == 3 &&
offset == RT5677_GPIO6)) {
irq = RT5677_IRQ_JD3;
} else {
return -ENXIO;
}
return irq_create_mapping(rt5677->domain, irq);
}
static const struct gpio_chip rt5677_template_chip = {
.label = RT5677_DRV_NAME,
.owner = THIS_MODULE,
.direction_output = rt5677_gpio_direction_out,
.set = rt5677_gpio_set,
.direction_input = rt5677_gpio_direction_in,
.get = rt5677_gpio_get,
.to_irq = rt5677_to_irq,
.can_sleep = 1,
};
static void rt5677_init_gpio(struct i2c_client *i2c)
{
struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
int ret;
rt5677->gpio_chip = rt5677_template_chip;
rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM;
rt5677->gpio_chip.parent = &i2c->dev;
rt5677->gpio_chip.base = -1;
ret = gpiochip_add_data(&rt5677->gpio_chip, rt5677);
if (ret != 0)
dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
}
static void rt5677_free_gpio(struct i2c_client *i2c)
{
struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
gpiochip_remove(&rt5677->gpio_chip);
}
#else
static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
int value)
{
}
static void rt5677_init_gpio(struct i2c_client *i2c)
{
}
static void rt5677_free_gpio(struct i2c_client *i2c)
{
}
#endif
static int rt5677_probe(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
int i;
rt5677->component = component;
if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
snd_soc_dapm_add_routes(dapm,
rt5677_dmic2_clk_2,
ARRAY_SIZE(rt5677_dmic2_clk_2));
} else { /*use dmic1 clock by default*/
snd_soc_dapm_add_routes(dapm,
rt5677_dmic2_clk_1,
ARRAY_SIZE(rt5677_dmic2_clk_1));
}
snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
~RT5677_IRQ_DEBOUNCE_SEL_MASK, 0x0020);
regmap_write(rt5677->regmap, RT5677_PWR_DSP2,
RT5677_PWR_SLIM_ISO | RT5677_PWR_CORE_ISO);
for (i = 0; i < RT5677_GPIO_NUM; i++)
rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]);
mutex_init(&rt5677->dsp_cmd_lock);
mutex_init(&rt5677->dsp_pri_lock);
return 0;
}
static void rt5677_remove(struct snd_soc_component *component)
{
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
cancel_delayed_work_sync(&rt5677->dsp_work);
regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
gpiod_set_value_cansleep(rt5677->reset_pin, 1);
}
#ifdef CONFIG_PM
static int rt5677_suspend(struct snd_soc_component *component)
{
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
if (rt5677->irq) {
cancel_delayed_work_sync(&rt5677->resume_irq_check);
disable_irq(rt5677->irq);
}
if (!rt5677->dsp_vad_en) {
regcache_cache_only(rt5677->regmap, true);
regcache_mark_dirty(rt5677->regmap);
gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
gpiod_set_value_cansleep(rt5677->reset_pin, 1);
}
return 0;
}
static int rt5677_resume(struct snd_soc_component *component)
{
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
if (!rt5677->dsp_vad_en) {
rt5677->pll_src = 0;
rt5677->pll_in = 0;
rt5677->pll_out = 0;
gpiod_set_value_cansleep(rt5677->pow_ldo2, 1);
gpiod_set_value_cansleep(rt5677->reset_pin, 0);
if (rt5677->pow_ldo2 || rt5677->reset_pin)
msleep(10);
regcache_cache_only(rt5677->regmap, false);
regcache_sync(rt5677->regmap);
}
if (rt5677->irq) {
enable_irq(rt5677->irq);
schedule_delayed_work(&rt5677->resume_irq_check, 0);
}
return 0;
}
#else
#define rt5677_suspend NULL
#define rt5677_resume NULL
#endif
static int rt5677_read(void *context, unsigned int reg, unsigned int *val)
{
struct i2c_client *client = context;
struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
if (rt5677->is_dsp_mode) {
if (reg > 0xff) {
mutex_lock(&rt5677->dsp_pri_lock);
rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
reg & 0xff);
rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val);
mutex_unlock(&rt5677->dsp_pri_lock);
} else {
rt5677_dsp_mode_i2c_read(rt5677, reg, val);
}
} else {
regmap_read(rt5677->regmap_physical, reg, val);
}
return 0;
}
static int rt5677_write(void *context, unsigned int reg, unsigned int val)
{
struct i2c_client *client = context;
struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
if (rt5677->is_dsp_mode) {
if (reg > 0xff) {
mutex_lock(&rt5677->dsp_pri_lock);
rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
reg & 0xff);
rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA,
val);
mutex_unlock(&rt5677->dsp_pri_lock);
} else {
rt5677_dsp_mode_i2c_write(rt5677, reg, val);
}
} else {
regmap_write(rt5677->regmap_physical, reg, val);
}
return 0;
}
#define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
#define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
static const struct snd_soc_dai_ops rt5677_aif_dai_ops = {
.hw_params = rt5677_hw_params,
.set_fmt = rt5677_set_dai_fmt,
.set_sysclk = rt5677_set_dai_sysclk,
.set_pll = rt5677_set_dai_pll,
.set_tdm_slot = rt5677_set_tdm_slot,
};
static const struct snd_soc_dai_ops rt5677_dsp_dai_ops = {
.set_sysclk = rt5677_set_dai_sysclk,
.set_pll = rt5677_set_dai_pll,
};
static struct snd_soc_dai_driver rt5677_dai[] = {
{
.name = "rt5677-aif1",
.id = RT5677_AIF1,
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT5677_STEREO_RATES,
.formats = RT5677_FORMATS,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT5677_STEREO_RATES,
.formats = RT5677_FORMATS,
},
.ops = &rt5677_aif_dai_ops,
},
{
.name = "rt5677-aif2",
.id = RT5677_AIF2,
.playback = {
.stream_name = "AIF2 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT5677_STEREO_RATES,
.formats = RT5677_FORMATS,
},
.capture = {
.stream_name = "AIF2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT5677_STEREO_RATES,
.formats = RT5677_FORMATS,
},
.ops = &rt5677_aif_dai_ops,
},
{
.name = "rt5677-aif3",
.id = RT5677_AIF3,
.playback = {
.stream_name = "AIF3 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT5677_STEREO_RATES,
.formats = RT5677_FORMATS,
},
.capture = {
.stream_name = "AIF3 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT5677_STEREO_RATES,
.formats = RT5677_FORMATS,
},
.ops = &rt5677_aif_dai_ops,
},
{
.name = "rt5677-aif4",
.id = RT5677_AIF4,
.playback = {
.stream_name = "AIF4 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT5677_STEREO_RATES,
.formats = RT5677_FORMATS,
},
.capture = {
.stream_name = "AIF4 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT5677_STEREO_RATES,
.formats = RT5677_FORMATS,
},
.ops = &rt5677_aif_dai_ops,
},
{
.name = "rt5677-slimbus",
.id = RT5677_AIF5,
.playback = {
.stream_name = "SLIMBus Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT5677_STEREO_RATES,
.formats = RT5677_FORMATS,
},
.capture = {
.stream_name = "SLIMBus Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT5677_STEREO_RATES,
.formats = RT5677_FORMATS,
},
.ops = &rt5677_aif_dai_ops,
},
{
.name = "rt5677-dspbuffer",
.id = RT5677_DSPBUFF,
.capture = {
.stream_name = "DSP Buffer",
.channels_min = 1,
.channels_max = 1,
.rates = SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.ops = &rt5677_dsp_dai_ops,
},
};
static const struct snd_soc_component_driver soc_component_dev_rt5677 = {
.name = RT5677_DRV_NAME,
.probe = rt5677_probe,
.remove = rt5677_remove,
.suspend = rt5677_suspend,
.resume = rt5677_resume,
.set_bias_level = rt5677_set_bias_level,
.controls = rt5677_snd_controls,
.num_controls = ARRAY_SIZE(rt5677_snd_controls),
.dapm_widgets = rt5677_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets),
.dapm_routes = rt5677_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config rt5677_regmap_physical = {
.name = "physical",
.reg_bits = 8,
.val_bits = 16,
.max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
RT5677_PR_SPACING),
.readable_reg = rt5677_readable_register,
.cache_type = REGCACHE_NONE,
.ranges = rt5677_ranges,
.num_ranges = ARRAY_SIZE(rt5677_ranges),
};
static const struct regmap_config rt5677_regmap = {
.reg_bits = 8,
.val_bits = 16,
.max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
RT5677_PR_SPACING),
.volatile_reg = rt5677_volatile_register,
.readable_reg = rt5677_readable_register,
.reg_read = rt5677_read,
.reg_write = rt5677_write,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = rt5677_reg,
.num_reg_defaults = ARRAY_SIZE(rt5677_reg),
.ranges = rt5677_ranges,
.num_ranges = ARRAY_SIZE(rt5677_ranges),
};
static const struct of_device_id rt5677_of_match[] = {
{ .compatible = "realtek,rt5677", .data = (const void *)RT5677 },
{ }
};
MODULE_DEVICE_TABLE(of, rt5677_of_match);
static const struct acpi_device_id rt5677_acpi_match[] = {
{ "RT5677CE", RT5677 },
{ }
};
MODULE_DEVICE_TABLE(acpi, rt5677_acpi_match);
static void rt5677_read_device_properties(struct rt5677_priv *rt5677,
struct device *dev)
{
u32 val;
rt5677->pdata.in1_diff =
device_property_read_bool(dev, "IN1") ||
device_property_read_bool(dev, "realtek,in1-differential");
rt5677->pdata.in2_diff =
device_property_read_bool(dev, "IN2") ||
device_property_read_bool(dev, "realtek,in2-differential");
rt5677->pdata.lout1_diff =
device_property_read_bool(dev, "OUT1") ||
device_property_read_bool(dev, "realtek,lout1-differential");
rt5677->pdata.lout2_diff =
device_property_read_bool(dev, "OUT2") ||
device_property_read_bool(dev, "realtek,lout2-differential");
rt5677->pdata.lout3_diff =
device_property_read_bool(dev, "OUT3") ||
device_property_read_bool(dev, "realtek,lout3-differential");
device_property_read_u8_array(dev, "realtek,gpio-config",
rt5677->pdata.gpio_config,
RT5677_GPIO_NUM);
if (!device_property_read_u32(dev, "DCLK", &val) ||
!device_property_read_u32(dev, "realtek,dmic2_clk_pin", &val))
rt5677->pdata.dmic2_clk_pin = val;
if (!device_property_read_u32(dev, "JD1", &val) ||
!device_property_read_u32(dev, "realtek,jd1-gpio", &val))
rt5677->pdata.jd1_gpio = val;
if (!device_property_read_u32(dev, "JD2", &val) ||
!device_property_read_u32(dev, "realtek,jd2-gpio", &val))
rt5677->pdata.jd2_gpio = val;
if (!device_property_read_u32(dev, "JD3", &val) ||
!device_property_read_u32(dev, "realtek,jd3-gpio", &val))
rt5677->pdata.jd3_gpio = val;
}
struct rt5677_irq_desc {
unsigned int enable_mask;
unsigned int status_mask;
unsigned int polarity_mask;
};
static const struct rt5677_irq_desc rt5677_irq_descs[] = {
[RT5677_IRQ_JD1] = {
.enable_mask = RT5677_EN_IRQ_GPIO_JD1,
.status_mask = RT5677_STA_GPIO_JD1,
.polarity_mask = RT5677_INV_GPIO_JD1,
},
[RT5677_IRQ_JD2] = {
.enable_mask = RT5677_EN_IRQ_GPIO_JD2,
.status_mask = RT5677_STA_GPIO_JD2,
.polarity_mask = RT5677_INV_GPIO_JD2,
},
[RT5677_IRQ_JD3] = {
.enable_mask = RT5677_EN_IRQ_GPIO_JD3,
.status_mask = RT5677_STA_GPIO_JD3,
.polarity_mask = RT5677_INV_GPIO_JD3,
},
};
static bool rt5677_check_hotword(struct rt5677_priv *rt5677)
{
int reg_gpio;
if (!rt5677->is_dsp_mode)
return false;
if (regmap_read(rt5677->regmap, RT5677_GPIO_CTRL1, ®_gpio))
return false;
/* Firmware sets GPIO1 pin to be GPIO1 after hotword is detected */
if ((reg_gpio & RT5677_GPIO1_PIN_MASK) == RT5677_GPIO1_PIN_IRQ)
return false;
/* Set GPIO1 pin back to be IRQ output for jack detect */
regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1,
RT5677_GPIO1_PIN_MASK, RT5677_GPIO1_PIN_IRQ);
rt5677_spi_hotword_detected();
return true;
}
static irqreturn_t rt5677_irq(int unused, void *data)
{
struct rt5677_priv *rt5677 = data;
int ret, loop, i, reg_irq, virq;
bool irq_fired = false;
mutex_lock(&rt5677->irq_lock);
/*
* Loop to handle interrupts until the last i2c read shows no pending
* irqs. The interrupt line is shared by multiple interrupt sources.
* After the regmap_read() below, a new interrupt source line may
* become high before the regmap_write() finishes, so there isn't a
* rising edge on the shared interrupt line for the new interrupt. Thus,
* the loop is needed to avoid missing irqs.
*
* A safeguard of 20 loops is used to avoid hanging in the irq handler
* if there is something wrong with the interrupt status update. The
* interrupt sources here are audio jack plug/unplug events which
* shouldn't happen at a high frequency for a long period of time.
* Empirically, more than 3 loops have never been seen.
*/
for (loop = 0; loop < 20; loop++) {
/* Read interrupt status */
ret = regmap_read(rt5677->regmap, RT5677_IRQ_CTRL1, ®_irq);
if (ret) {
dev_err(rt5677->dev, "failed reading IRQ status: %d\n",
ret);
goto exit;
}
irq_fired = false;
for (i = 0; i < RT5677_IRQ_NUM; i++) {
if (reg_irq & rt5677_irq_descs[i].status_mask) {
irq_fired = true;
virq = irq_find_mapping(rt5677->domain, i);
if (virq)
handle_nested_irq(virq);
/* Clear the interrupt by flipping the polarity
* of the interrupt source line that fired
*/
reg_irq ^= rt5677_irq_descs[i].polarity_mask;
}
}
/* Exit the loop only when we know for sure that GPIO1 pin
* was low at some point since irq_lock was acquired. Any event
* after that point creates a rising edge that triggers another
* call to rt5677_irq().
*/
if (!irq_fired && !rt5677_check_hotword(rt5677))
goto exit;
ret = regmap_write(rt5677->regmap, RT5677_IRQ_CTRL1, reg_irq);
if (ret) {
dev_err(rt5677->dev, "failed updating IRQ status: %d\n",
ret);
goto exit;
}
}
exit:
WARN_ON_ONCE(loop == 20);
mutex_unlock(&rt5677->irq_lock);
if (irq_fired)
return IRQ_HANDLED;
else
return IRQ_NONE;
}
static void rt5677_resume_irq_check(struct work_struct *work)
{
int i, virq;
struct rt5677_priv *rt5677 =
container_of(work, struct rt5677_priv, resume_irq_check.work);
/* This is needed to check and clear the interrupt status register
* at resume. If the headset is plugged/unplugged when the device is
* fully suspended, there won't be a rising edge at resume to trigger
* the interrupt. Without this, we miss the next unplug/plug event.
*/
rt5677_irq(0, rt5677);
/* Call all enabled jack detect irq handlers again. This is needed in
* addition to the above check for a corner case caused by jack gpio
* debounce. After codec irq is disabled at suspend, the delayed work
* scheduled by soc-jack may run and read wrong jack gpio values, since
* the regmap is in cache only mode. At resume, there is no irq because
* rt5677_irq has already ran and cleared the irq status at suspend.
* Without this explicit check, unplug the headset right after suspend
* starts, then after resume the headset is still shown as plugged in.
*/
mutex_lock(&rt5677->irq_lock);
for (i = 0; i < RT5677_IRQ_NUM; i++) {
if (rt5677->irq_en & rt5677_irq_descs[i].enable_mask) {
virq = irq_find_mapping(rt5677->domain, i);
if (virq)
handle_nested_irq(virq);
}
}
mutex_unlock(&rt5677->irq_lock);
}
static void rt5677_irq_bus_lock(struct irq_data *data)
{
struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data);
mutex_lock(&rt5677->irq_lock);
}
static void rt5677_irq_bus_sync_unlock(struct irq_data *data)
{
struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data);
// Set the enable/disable bits for the jack detect IRQs.
regmap_update_bits(rt5677->regmap, RT5677_IRQ_CTRL1,
RT5677_EN_IRQ_GPIO_JD1 | RT5677_EN_IRQ_GPIO_JD2 |
RT5677_EN_IRQ_GPIO_JD3, rt5677->irq_en);
mutex_unlock(&rt5677->irq_lock);
}
static void rt5677_irq_enable(struct irq_data *data)
{
struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data);
rt5677->irq_en |= rt5677_irq_descs[data->hwirq].enable_mask;
}
static void rt5677_irq_disable(struct irq_data *data)
{
struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data);
rt5677->irq_en &= ~rt5677_irq_descs[data->hwirq].enable_mask;
}
static struct irq_chip rt5677_irq_chip = {
.name = "rt5677_irq_chip",
.irq_bus_lock = rt5677_irq_bus_lock,
.irq_bus_sync_unlock = rt5677_irq_bus_sync_unlock,
.irq_disable = rt5677_irq_disable,
.irq_enable = rt5677_irq_enable,
};
static int rt5677_irq_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
struct rt5677_priv *rt5677 = h->host_data;
irq_set_chip_data(virq, rt5677);
irq_set_chip(virq, &rt5677_irq_chip);
irq_set_nested_thread(virq, 1);
irq_set_noprobe(virq);
return 0;
}
static const struct irq_domain_ops rt5677_domain_ops = {
.map = rt5677_irq_map,
.xlate = irq_domain_xlate_twocell,
};
static int rt5677_init_irq(struct i2c_client *i2c)
{
int ret;
struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
unsigned int jd_mask = 0, jd_val = 0;
if (!rt5677->pdata.jd1_gpio &&
!rt5677->pdata.jd2_gpio &&
!rt5677->pdata.jd3_gpio)
return 0;
if (!i2c->irq) {
dev_err(&i2c->dev, "No interrupt specified\n");
return -EINVAL;
}
mutex_init(&rt5677->irq_lock);
INIT_DELAYED_WORK(&rt5677->resume_irq_check, rt5677_resume_irq_check);
/*
* Select RC as the debounce clock so that GPIO works even when
* MCLK is gated which happens when there is no audio stream
* (SND_SOC_BIAS_OFF).
*/
regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
RT5677_IRQ_DEBOUNCE_SEL_MASK,
RT5677_IRQ_DEBOUNCE_SEL_RC);
/* Enable auto power on RC when GPIO states are changed */
regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL1, 0xff, 0xff);
/* Select and enable jack detection sources per platform data */
if (rt5677->pdata.jd1_gpio) {
jd_mask |= RT5677_SEL_GPIO_JD1_MASK;
jd_val |= rt5677->pdata.jd1_gpio << RT5677_SEL_GPIO_JD1_SFT;
}
if (rt5677->pdata.jd2_gpio) {
jd_mask |= RT5677_SEL_GPIO_JD2_MASK;
jd_val |= rt5677->pdata.jd2_gpio << RT5677_SEL_GPIO_JD2_SFT;
}
if (rt5677->pdata.jd3_gpio) {
jd_mask |= RT5677_SEL_GPIO_JD3_MASK;
jd_val |= rt5677->pdata.jd3_gpio << RT5677_SEL_GPIO_JD3_SFT;
}
regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1, jd_mask, jd_val);
/* Set GPIO1 pin to be IRQ output */
regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1,
RT5677_GPIO1_PIN_MASK, RT5677_GPIO1_PIN_IRQ);
/* Ready to listen for interrupts */
rt5677->domain = irq_domain_create_linear(dev_fwnode(&i2c->dev),
RT5677_IRQ_NUM, &rt5677_domain_ops, rt5677);
if (!rt5677->domain) {
dev_err(&i2c->dev, "Failed to create IRQ domain\n");
return -ENOMEM;
}
ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, rt5677_irq,
IRQF_TRIGGER_RISING | IRQF_ONESHOT,
"rt5677", rt5677);
if (ret)
dev_err(&i2c->dev, "Failed to request IRQ: %d\n", ret);
rt5677->irq = i2c->irq;
return ret;
}
static int rt5677_i2c_probe(struct i2c_client *i2c)
{
struct device *dev = &i2c->dev;
struct rt5677_priv *rt5677;
int ret;
unsigned int val;
rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
GFP_KERNEL);
if (rt5677 == NULL)
return -ENOMEM;
rt5677->dev = &i2c->dev;
rt5677->set_dsp_vad = rt5677_set_dsp_vad;
INIT_DELAYED_WORK(&rt5677->dsp_work, rt5677_dsp_work);
i2c_set_clientdata(i2c, rt5677);
rt5677->type = (enum rt5677_type)(uintptr_t)device_get_match_data(dev);
if (rt5677->type == 0)
return -EINVAL;
rt5677_read_device_properties(rt5677, &i2c->dev);
/* pow-ldo2 and reset are optional. The codec pins may be statically
* connected on the board without gpios. If the gpio device property
* isn't specified, devm_gpiod_get_optional returns NULL.
*/
rt5677->pow_ldo2 = devm_gpiod_get_optional(&i2c->dev,
"realtek,pow-ldo2", GPIOD_OUT_HIGH);
if (IS_ERR(rt5677->pow_ldo2)) {
ret = PTR_ERR(rt5677->pow_ldo2);
dev_err(&i2c->dev, "Failed to request POW_LDO2: %d\n", ret);
return ret;
}
rt5677->reset_pin = devm_gpiod_get_optional(&i2c->dev,
"realtek,reset", GPIOD_OUT_LOW);
if (IS_ERR(rt5677->reset_pin)) {
ret = PTR_ERR(rt5677->reset_pin);
dev_err(&i2c->dev, "Failed to request RESET: %d\n", ret);
return ret;
}
if (rt5677->pow_ldo2 || rt5677->reset_pin) {
/* Wait a while until I2C bus becomes available. The datasheet
* does not specify the exact we should wait but startup
* sequence mentiones at least a few milliseconds.
*/
msleep(10);
}
rt5677->regmap_physical = devm_regmap_init_i2c(i2c,
&rt5677_regmap_physical);
if (IS_ERR(rt5677->regmap_physical)) {
ret = PTR_ERR(rt5677->regmap_physical);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap);
if (IS_ERR(rt5677->regmap)) {
ret = PTR_ERR(rt5677->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
if (val != RT5677_DEVICE_ID) {
dev_err(&i2c->dev,
"Device with ID register %#x is not rt5677\n", val);
return -ENODEV;
}
regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
ret = regmap_register_patch(rt5677->regmap, init_list,
ARRAY_SIZE(init_list));
if (ret != 0)
dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
if (rt5677->pdata.in1_diff)
regmap_update_bits(rt5677->regmap, RT5677_IN1,
RT5677_IN_DF1, RT5677_IN_DF1);
if (rt5677->pdata.in2_diff)
regmap_update_bits(rt5677->regmap, RT5677_IN1,
RT5677_IN_DF2, RT5677_IN_DF2);
if (rt5677->pdata.lout1_diff)
regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF);
if (rt5677->pdata.lout2_diff)
regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF);
if (rt5677->pdata.lout3_diff)
regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF);
if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
RT5677_GPIO5_FUNC_MASK,
RT5677_GPIO5_FUNC_DMIC);
rt5677_update_gpio_bits(rt5677, RT5677_GPIO5,
RT5677_GPIOx_DIR_MASK,
RT5677_GPIOx_DIR_OUT);
}
if (rt5677->pdata.micbias1_vdd_3v3)
regmap_update_bits(rt5677->regmap, RT5677_MICBIAS,
RT5677_MICBIAS1_CTRL_VDD_MASK,
RT5677_MICBIAS1_CTRL_VDD_3_3V);
rt5677_init_gpio(i2c);
ret = rt5677_init_irq(i2c);
if (ret)
dev_err(&i2c->dev, "Failed to initialize irq: %d\n", ret);
return devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_rt5677,
rt5677_dai, ARRAY_SIZE(rt5677_dai));
}
static void rt5677_i2c_remove(struct i2c_client *i2c)
{
rt5677_free_gpio(i2c);
}
static struct i2c_driver rt5677_i2c_driver = {
.driver = {
.name = RT5677_DRV_NAME,
.of_match_table = rt5677_of_match,
.acpi_match_table = rt5677_acpi_match,
},
.probe = rt5677_i2c_probe,
.remove = rt5677_i2c_remove,
};
module_i2c_driver(rt5677_i2c_driver);
MODULE_DESCRIPTION("ASoC RT5677 driver");
MODULE_AUTHOR("Oder Chiou <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_FIRMWARE("rt5677_elf_vad");
| linux-master | sound/soc/codecs/rt5677.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm2000.c -- WM2000 ALSA Soc Audio driver
*
* Copyright 2008-2011 Wolfson Microelectronics PLC.
*
* Author: Mark Brown <[email protected]>
*
* The download image for the WM2000 will be requested as
* 'wm2000_anc.bin' by default (overridable via platform data) at
* runtime and is expected to be in flat binary format. This is
* generated by Wolfson configuration tools and includes
* system-specific calibration information. If supplied as a
* sequence of ASCII-encoded hexidecimal bytes this can be converted
* into a flat binary with a command such as this on the command line:
*
* perl -e 'while (<>) { s/[\r\n]+// ; printf("%c", hex($_)); }'
* < file > wm2000_anc.bin
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/firmware.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/debugfs.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/wm2000.h>
#include "wm2000.h"
#define WM2000_NUM_SUPPLIES 3
static const char *wm2000_supplies[WM2000_NUM_SUPPLIES] = {
"SPKVDD",
"DBVDD",
"DCVDD",
};
enum wm2000_anc_mode {
ANC_ACTIVE = 0,
ANC_BYPASS = 1,
ANC_STANDBY = 2,
ANC_OFF = 3,
};
struct wm2000_priv {
struct i2c_client *i2c;
struct regmap *regmap;
struct clk *mclk;
struct regulator_bulk_data supplies[WM2000_NUM_SUPPLIES];
enum wm2000_anc_mode anc_mode;
unsigned int anc_active:1;
unsigned int anc_eng_ena:1;
unsigned int spk_ena:1;
unsigned int speech_clarity:1;
int anc_download_size;
char *anc_download;
struct mutex lock;
};
static int wm2000_write(struct i2c_client *i2c, unsigned int reg,
unsigned int value)
{
struct wm2000_priv *wm2000 = i2c_get_clientdata(i2c);
return regmap_write(wm2000->regmap, reg, value);
}
static void wm2000_reset(struct wm2000_priv *wm2000)
{
struct i2c_client *i2c = wm2000->i2c;
wm2000_write(i2c, WM2000_REG_SYS_CTL2, WM2000_ANC_ENG_CLR);
wm2000_write(i2c, WM2000_REG_SYS_CTL2, WM2000_RAM_CLR);
wm2000_write(i2c, WM2000_REG_ID1, 0);
wm2000->anc_mode = ANC_OFF;
}
static int wm2000_poll_bit(struct i2c_client *i2c,
unsigned int reg, u8 mask)
{
struct wm2000_priv *wm2000 = i2c_get_clientdata(i2c);
int timeout = 4000;
unsigned int val;
regmap_read(wm2000->regmap, reg, &val);
while (!(val & mask) && --timeout) {
msleep(1);
regmap_read(wm2000->regmap, reg, &val);
}
if (timeout == 0)
return 0;
else
return 1;
}
static int wm2000_power_up(struct i2c_client *i2c, int analogue)
{
struct wm2000_priv *wm2000 = dev_get_drvdata(&i2c->dev);
unsigned long rate;
unsigned int val;
int ret;
if (WARN_ON(wm2000->anc_mode != ANC_OFF))
return -EINVAL;
dev_dbg(&i2c->dev, "Beginning power up\n");
ret = regulator_bulk_enable(WM2000_NUM_SUPPLIES, wm2000->supplies);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
return ret;
}
rate = clk_get_rate(wm2000->mclk);
if (rate <= 13500000) {
dev_dbg(&i2c->dev, "Disabling MCLK divider\n");
wm2000_write(i2c, WM2000_REG_SYS_CTL2,
WM2000_MCLK_DIV2_ENA_CLR);
} else {
dev_dbg(&i2c->dev, "Enabling MCLK divider\n");
wm2000_write(i2c, WM2000_REG_SYS_CTL2,
WM2000_MCLK_DIV2_ENA_SET);
}
wm2000_write(i2c, WM2000_REG_SYS_CTL2, WM2000_ANC_ENG_CLR);
wm2000_write(i2c, WM2000_REG_SYS_CTL2, WM2000_ANC_ENG_SET);
/* Wait for ANC engine to become ready */
if (!wm2000_poll_bit(i2c, WM2000_REG_ANC_STAT,
WM2000_ANC_ENG_IDLE)) {
dev_err(&i2c->dev, "ANC engine failed to reset\n");
regulator_bulk_disable(WM2000_NUM_SUPPLIES, wm2000->supplies);
return -ETIMEDOUT;
}
if (!wm2000_poll_bit(i2c, WM2000_REG_SYS_STATUS,
WM2000_STATUS_BOOT_COMPLETE)) {
dev_err(&i2c->dev, "ANC engine failed to initialise\n");
regulator_bulk_disable(WM2000_NUM_SUPPLIES, wm2000->supplies);
return -ETIMEDOUT;
}
wm2000_write(i2c, WM2000_REG_SYS_CTL2, WM2000_RAM_SET);
/* Open code download of the data since it is the only bulk
* write we do. */
dev_dbg(&i2c->dev, "Downloading %d bytes\n",
wm2000->anc_download_size - 2);
ret = i2c_master_send(i2c, wm2000->anc_download,
wm2000->anc_download_size);
if (ret < 0) {
dev_err(&i2c->dev, "i2c_transfer() failed: %d\n", ret);
regulator_bulk_disable(WM2000_NUM_SUPPLIES, wm2000->supplies);
return ret;
}
if (ret != wm2000->anc_download_size) {
dev_err(&i2c->dev, "i2c_transfer() failed, %d != %d\n",
ret, wm2000->anc_download_size);
regulator_bulk_disable(WM2000_NUM_SUPPLIES, wm2000->supplies);
return -EIO;
}
dev_dbg(&i2c->dev, "Download complete\n");
if (analogue) {
wm2000_write(i2c, WM2000_REG_ANA_VMID_PU_TIME, 248 / 4);
wm2000_write(i2c, WM2000_REG_SYS_MODE_CNTRL,
WM2000_MODE_ANA_SEQ_INCLUDE |
WM2000_MODE_MOUSE_ENABLE |
WM2000_MODE_THERMAL_ENABLE);
} else {
wm2000_write(i2c, WM2000_REG_SYS_MODE_CNTRL,
WM2000_MODE_MOUSE_ENABLE |
WM2000_MODE_THERMAL_ENABLE);
}
ret = regmap_read(wm2000->regmap, WM2000_REG_SPEECH_CLARITY, &val);
if (ret != 0) {
dev_err(&i2c->dev, "Unable to read Speech Clarity: %d\n", ret);
regulator_bulk_disable(WM2000_NUM_SUPPLIES, wm2000->supplies);
return ret;
}
if (wm2000->speech_clarity)
val |= WM2000_SPEECH_CLARITY;
else
val &= ~WM2000_SPEECH_CLARITY;
wm2000_write(i2c, WM2000_REG_SPEECH_CLARITY, val);
wm2000_write(i2c, WM2000_REG_SYS_START0, 0x33);
wm2000_write(i2c, WM2000_REG_SYS_START1, 0x02);
wm2000_write(i2c, WM2000_REG_SYS_CTL2, WM2000_ANC_INT_N_CLR);
if (!wm2000_poll_bit(i2c, WM2000_REG_SYS_STATUS,
WM2000_STATUS_MOUSE_ACTIVE)) {
dev_err(&i2c->dev, "Timed out waiting for device\n");
regulator_bulk_disable(WM2000_NUM_SUPPLIES, wm2000->supplies);
return -ETIMEDOUT;
}
dev_dbg(&i2c->dev, "ANC active\n");
if (analogue)
dev_dbg(&i2c->dev, "Analogue active\n");
wm2000->anc_mode = ANC_ACTIVE;
return 0;
}
static int wm2000_power_down(struct i2c_client *i2c, int analogue)
{
struct wm2000_priv *wm2000 = dev_get_drvdata(&i2c->dev);
if (analogue) {
wm2000_write(i2c, WM2000_REG_ANA_VMID_PD_TIME, 248 / 4);
wm2000_write(i2c, WM2000_REG_SYS_MODE_CNTRL,
WM2000_MODE_ANA_SEQ_INCLUDE |
WM2000_MODE_POWER_DOWN);
} else {
wm2000_write(i2c, WM2000_REG_SYS_MODE_CNTRL,
WM2000_MODE_POWER_DOWN);
}
if (!wm2000_poll_bit(i2c, WM2000_REG_SYS_STATUS,
WM2000_STATUS_POWER_DOWN_COMPLETE)) {
dev_err(&i2c->dev, "Timeout waiting for ANC power down\n");
return -ETIMEDOUT;
}
if (!wm2000_poll_bit(i2c, WM2000_REG_ANC_STAT,
WM2000_ANC_ENG_IDLE)) {
dev_err(&i2c->dev, "Timeout waiting for ANC engine idle\n");
return -ETIMEDOUT;
}
regulator_bulk_disable(WM2000_NUM_SUPPLIES, wm2000->supplies);
dev_dbg(&i2c->dev, "powered off\n");
wm2000->anc_mode = ANC_OFF;
return 0;
}
static int wm2000_enter_bypass(struct i2c_client *i2c, int analogue)
{
struct wm2000_priv *wm2000 = dev_get_drvdata(&i2c->dev);
if (WARN_ON(wm2000->anc_mode != ANC_ACTIVE))
return -EINVAL;
if (analogue) {
wm2000_write(i2c, WM2000_REG_SYS_MODE_CNTRL,
WM2000_MODE_ANA_SEQ_INCLUDE |
WM2000_MODE_THERMAL_ENABLE |
WM2000_MODE_BYPASS_ENTRY);
} else {
wm2000_write(i2c, WM2000_REG_SYS_MODE_CNTRL,
WM2000_MODE_THERMAL_ENABLE |
WM2000_MODE_BYPASS_ENTRY);
}
if (!wm2000_poll_bit(i2c, WM2000_REG_SYS_STATUS,
WM2000_STATUS_ANC_DISABLED)) {
dev_err(&i2c->dev, "Timeout waiting for ANC disable\n");
return -ETIMEDOUT;
}
if (!wm2000_poll_bit(i2c, WM2000_REG_ANC_STAT,
WM2000_ANC_ENG_IDLE)) {
dev_err(&i2c->dev, "Timeout waiting for ANC engine idle\n");
return -ETIMEDOUT;
}
wm2000_write(i2c, WM2000_REG_SYS_CTL1, WM2000_SYS_STBY);
wm2000_write(i2c, WM2000_REG_SYS_CTL2, WM2000_RAM_CLR);
wm2000->anc_mode = ANC_BYPASS;
dev_dbg(&i2c->dev, "bypass enabled\n");
return 0;
}
static int wm2000_exit_bypass(struct i2c_client *i2c, int analogue)
{
struct wm2000_priv *wm2000 = dev_get_drvdata(&i2c->dev);
if (WARN_ON(wm2000->anc_mode != ANC_BYPASS))
return -EINVAL;
wm2000_write(i2c, WM2000_REG_SYS_CTL1, 0);
if (analogue) {
wm2000_write(i2c, WM2000_REG_SYS_MODE_CNTRL,
WM2000_MODE_ANA_SEQ_INCLUDE |
WM2000_MODE_MOUSE_ENABLE |
WM2000_MODE_THERMAL_ENABLE);
} else {
wm2000_write(i2c, WM2000_REG_SYS_MODE_CNTRL,
WM2000_MODE_MOUSE_ENABLE |
WM2000_MODE_THERMAL_ENABLE);
}
wm2000_write(i2c, WM2000_REG_SYS_CTL2, WM2000_RAM_SET);
wm2000_write(i2c, WM2000_REG_SYS_CTL2, WM2000_ANC_INT_N_CLR);
if (!wm2000_poll_bit(i2c, WM2000_REG_SYS_STATUS,
WM2000_STATUS_MOUSE_ACTIVE)) {
dev_err(&i2c->dev, "Timed out waiting for MOUSE\n");
return -ETIMEDOUT;
}
wm2000->anc_mode = ANC_ACTIVE;
dev_dbg(&i2c->dev, "MOUSE active\n");
return 0;
}
static int wm2000_enter_standby(struct i2c_client *i2c, int analogue)
{
struct wm2000_priv *wm2000 = dev_get_drvdata(&i2c->dev);
if (WARN_ON(wm2000->anc_mode != ANC_ACTIVE))
return -EINVAL;
if (analogue) {
wm2000_write(i2c, WM2000_REG_ANA_VMID_PD_TIME, 248 / 4);
wm2000_write(i2c, WM2000_REG_SYS_MODE_CNTRL,
WM2000_MODE_ANA_SEQ_INCLUDE |
WM2000_MODE_THERMAL_ENABLE |
WM2000_MODE_STANDBY_ENTRY);
} else {
wm2000_write(i2c, WM2000_REG_SYS_MODE_CNTRL,
WM2000_MODE_THERMAL_ENABLE |
WM2000_MODE_STANDBY_ENTRY);
}
if (!wm2000_poll_bit(i2c, WM2000_REG_SYS_STATUS,
WM2000_STATUS_ANC_DISABLED)) {
dev_err(&i2c->dev,
"Timed out waiting for ANC disable after 1ms\n");
return -ETIMEDOUT;
}
if (!wm2000_poll_bit(i2c, WM2000_REG_ANC_STAT, WM2000_ANC_ENG_IDLE)) {
dev_err(&i2c->dev,
"Timed out waiting for standby\n");
return -ETIMEDOUT;
}
wm2000_write(i2c, WM2000_REG_SYS_CTL1, WM2000_SYS_STBY);
wm2000_write(i2c, WM2000_REG_SYS_CTL2, WM2000_RAM_CLR);
wm2000->anc_mode = ANC_STANDBY;
dev_dbg(&i2c->dev, "standby\n");
if (analogue)
dev_dbg(&i2c->dev, "Analogue disabled\n");
return 0;
}
static int wm2000_exit_standby(struct i2c_client *i2c, int analogue)
{
struct wm2000_priv *wm2000 = dev_get_drvdata(&i2c->dev);
if (WARN_ON(wm2000->anc_mode != ANC_STANDBY))
return -EINVAL;
wm2000_write(i2c, WM2000_REG_SYS_CTL1, 0);
if (analogue) {
wm2000_write(i2c, WM2000_REG_ANA_VMID_PU_TIME, 248 / 4);
wm2000_write(i2c, WM2000_REG_SYS_MODE_CNTRL,
WM2000_MODE_ANA_SEQ_INCLUDE |
WM2000_MODE_THERMAL_ENABLE |
WM2000_MODE_MOUSE_ENABLE);
} else {
wm2000_write(i2c, WM2000_REG_SYS_MODE_CNTRL,
WM2000_MODE_THERMAL_ENABLE |
WM2000_MODE_MOUSE_ENABLE);
}
wm2000_write(i2c, WM2000_REG_SYS_CTL2, WM2000_RAM_SET);
wm2000_write(i2c, WM2000_REG_SYS_CTL2, WM2000_ANC_INT_N_CLR);
if (!wm2000_poll_bit(i2c, WM2000_REG_SYS_STATUS,
WM2000_STATUS_MOUSE_ACTIVE)) {
dev_err(&i2c->dev, "Timed out waiting for MOUSE\n");
return -ETIMEDOUT;
}
wm2000->anc_mode = ANC_ACTIVE;
dev_dbg(&i2c->dev, "MOUSE active\n");
if (analogue)
dev_dbg(&i2c->dev, "Analogue enabled\n");
return 0;
}
typedef int (*wm2000_mode_fn)(struct i2c_client *i2c, int analogue);
static struct {
enum wm2000_anc_mode source;
enum wm2000_anc_mode dest;
int analogue;
wm2000_mode_fn step[2];
} anc_transitions[] = {
{
.source = ANC_OFF,
.dest = ANC_ACTIVE,
.analogue = 1,
.step = {
wm2000_power_up,
},
},
{
.source = ANC_OFF,
.dest = ANC_STANDBY,
.step = {
wm2000_power_up,
wm2000_enter_standby,
},
},
{
.source = ANC_OFF,
.dest = ANC_BYPASS,
.analogue = 1,
.step = {
wm2000_power_up,
wm2000_enter_bypass,
},
},
{
.source = ANC_ACTIVE,
.dest = ANC_BYPASS,
.analogue = 1,
.step = {
wm2000_enter_bypass,
},
},
{
.source = ANC_ACTIVE,
.dest = ANC_STANDBY,
.analogue = 1,
.step = {
wm2000_enter_standby,
},
},
{
.source = ANC_ACTIVE,
.dest = ANC_OFF,
.analogue = 1,
.step = {
wm2000_power_down,
},
},
{
.source = ANC_BYPASS,
.dest = ANC_ACTIVE,
.analogue = 1,
.step = {
wm2000_exit_bypass,
},
},
{
.source = ANC_BYPASS,
.dest = ANC_STANDBY,
.analogue = 1,
.step = {
wm2000_exit_bypass,
wm2000_enter_standby,
},
},
{
.source = ANC_BYPASS,
.dest = ANC_OFF,
.step = {
wm2000_exit_bypass,
wm2000_power_down,
},
},
{
.source = ANC_STANDBY,
.dest = ANC_ACTIVE,
.analogue = 1,
.step = {
wm2000_exit_standby,
},
},
{
.source = ANC_STANDBY,
.dest = ANC_BYPASS,
.analogue = 1,
.step = {
wm2000_exit_standby,
wm2000_enter_bypass,
},
},
{
.source = ANC_STANDBY,
.dest = ANC_OFF,
.step = {
wm2000_exit_standby,
wm2000_power_down,
},
},
};
static int wm2000_anc_transition(struct wm2000_priv *wm2000,
enum wm2000_anc_mode mode)
{
struct i2c_client *i2c = wm2000->i2c;
int i, j;
int ret = 0;
if (wm2000->anc_mode == mode)
return 0;
for (i = 0; i < ARRAY_SIZE(anc_transitions); i++)
if (anc_transitions[i].source == wm2000->anc_mode &&
anc_transitions[i].dest == mode)
break;
if (i == ARRAY_SIZE(anc_transitions)) {
dev_err(&i2c->dev, "No transition for %d->%d\n",
wm2000->anc_mode, mode);
return -EINVAL;
}
/* Maintain clock while active */
if (anc_transitions[i].source == ANC_OFF) {
ret = clk_prepare_enable(wm2000->mclk);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to enable MCLK: %d\n", ret);
return ret;
}
}
for (j = 0; j < ARRAY_SIZE(anc_transitions[j].step); j++) {
if (!anc_transitions[i].step[j])
break;
ret = anc_transitions[i].step[j](i2c,
anc_transitions[i].analogue);
if (ret != 0)
break;
}
if (anc_transitions[i].dest == ANC_OFF)
clk_disable_unprepare(wm2000->mclk);
return ret;
}
static int wm2000_anc_set_mode(struct wm2000_priv *wm2000)
{
struct i2c_client *i2c = wm2000->i2c;
enum wm2000_anc_mode mode;
if (wm2000->anc_eng_ena && wm2000->spk_ena)
if (wm2000->anc_active)
mode = ANC_ACTIVE;
else
mode = ANC_BYPASS;
else
mode = ANC_STANDBY;
dev_dbg(&i2c->dev, "Set mode %d (enabled %d, mute %d, active %d)\n",
mode, wm2000->anc_eng_ena, !wm2000->spk_ena,
wm2000->anc_active);
return wm2000_anc_transition(wm2000, mode);
}
static int wm2000_anc_mode_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm2000_priv *wm2000 = dev_get_drvdata(component->dev);
ucontrol->value.integer.value[0] = wm2000->anc_active;
return 0;
}
static int wm2000_anc_mode_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm2000_priv *wm2000 = dev_get_drvdata(component->dev);
unsigned int anc_active = ucontrol->value.integer.value[0];
int ret;
if (anc_active > 1)
return -EINVAL;
mutex_lock(&wm2000->lock);
wm2000->anc_active = anc_active;
ret = wm2000_anc_set_mode(wm2000);
mutex_unlock(&wm2000->lock);
return ret;
}
static int wm2000_speaker_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm2000_priv *wm2000 = dev_get_drvdata(component->dev);
ucontrol->value.integer.value[0] = wm2000->spk_ena;
return 0;
}
static int wm2000_speaker_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm2000_priv *wm2000 = dev_get_drvdata(component->dev);
unsigned int val = ucontrol->value.integer.value[0];
int ret;
if (val > 1)
return -EINVAL;
mutex_lock(&wm2000->lock);
wm2000->spk_ena = val;
ret = wm2000_anc_set_mode(wm2000);
mutex_unlock(&wm2000->lock);
return ret;
}
static const struct snd_kcontrol_new wm2000_controls[] = {
SOC_SINGLE("ANC Volume", WM2000_REG_ANC_GAIN_CTRL, 0, 255, 0),
SOC_SINGLE_BOOL_EXT("WM2000 ANC Switch", 0,
wm2000_anc_mode_get,
wm2000_anc_mode_put),
SOC_SINGLE_BOOL_EXT("WM2000 Switch", 0,
wm2000_speaker_get,
wm2000_speaker_put),
};
static int wm2000_anc_power_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wm2000_priv *wm2000 = dev_get_drvdata(component->dev);
int ret;
mutex_lock(&wm2000->lock);
if (SND_SOC_DAPM_EVENT_ON(event))
wm2000->anc_eng_ena = 1;
if (SND_SOC_DAPM_EVENT_OFF(event))
wm2000->anc_eng_ena = 0;
ret = wm2000_anc_set_mode(wm2000);
mutex_unlock(&wm2000->lock);
return ret;
}
static const struct snd_soc_dapm_widget wm2000_dapm_widgets[] = {
/* Externally visible pins */
SND_SOC_DAPM_OUTPUT("SPKN"),
SND_SOC_DAPM_OUTPUT("SPKP"),
SND_SOC_DAPM_INPUT("LINN"),
SND_SOC_DAPM_INPUT("LINP"),
SND_SOC_DAPM_PGA_E("ANC Engine", SND_SOC_NOPM, 0, 0, NULL, 0,
wm2000_anc_power_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
};
/* Target, Path, Source */
static const struct snd_soc_dapm_route wm2000_audio_map[] = {
{ "SPKN", NULL, "ANC Engine" },
{ "SPKP", NULL, "ANC Engine" },
{ "ANC Engine", NULL, "LINN" },
{ "ANC Engine", NULL, "LINP" },
};
#ifdef CONFIG_PM
static int wm2000_suspend(struct snd_soc_component *component)
{
struct wm2000_priv *wm2000 = dev_get_drvdata(component->dev);
return wm2000_anc_transition(wm2000, ANC_OFF);
}
static int wm2000_resume(struct snd_soc_component *component)
{
struct wm2000_priv *wm2000 = dev_get_drvdata(component->dev);
return wm2000_anc_set_mode(wm2000);
}
#else
#define wm2000_suspend NULL
#define wm2000_resume NULL
#endif
static bool wm2000_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM2000_REG_SYS_START:
case WM2000_REG_ANC_GAIN_CTRL:
case WM2000_REG_MSE_TH1:
case WM2000_REG_MSE_TH2:
case WM2000_REG_SPEECH_CLARITY:
case WM2000_REG_SYS_WATCHDOG:
case WM2000_REG_ANA_VMID_PD_TIME:
case WM2000_REG_ANA_VMID_PU_TIME:
case WM2000_REG_CAT_FLTR_INDX:
case WM2000_REG_CAT_GAIN_0:
case WM2000_REG_SYS_STATUS:
case WM2000_REG_SYS_MODE_CNTRL:
case WM2000_REG_SYS_START0:
case WM2000_REG_SYS_START1:
case WM2000_REG_ID1:
case WM2000_REG_ID2:
case WM2000_REG_REVISON:
case WM2000_REG_SYS_CTL1:
case WM2000_REG_SYS_CTL2:
case WM2000_REG_ANC_STAT:
case WM2000_REG_IF_CTL:
case WM2000_REG_ANA_MIC_CTL:
case WM2000_REG_SPK_CTL:
return true;
default:
return false;
}
}
static const struct regmap_config wm2000_regmap = {
.reg_bits = 16,
.val_bits = 8,
.max_register = WM2000_REG_SPK_CTL,
.readable_reg = wm2000_readable_reg,
};
static int wm2000_probe(struct snd_soc_component *component)
{
struct wm2000_priv *wm2000 = dev_get_drvdata(component->dev);
/* This will trigger a transition to standby mode by default */
wm2000_anc_set_mode(wm2000);
return 0;
}
static void wm2000_remove(struct snd_soc_component *component)
{
struct wm2000_priv *wm2000 = dev_get_drvdata(component->dev);
wm2000_anc_transition(wm2000, ANC_OFF);
}
static const struct snd_soc_component_driver soc_component_dev_wm2000 = {
.probe = wm2000_probe,
.remove = wm2000_remove,
.suspend = wm2000_suspend,
.resume = wm2000_resume,
.controls = wm2000_controls,
.num_controls = ARRAY_SIZE(wm2000_controls),
.dapm_widgets = wm2000_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm2000_dapm_widgets),
.dapm_routes = wm2000_audio_map,
.num_dapm_routes = ARRAY_SIZE(wm2000_audio_map),
.idle_bias_on = 1,
.use_pmdown_time = 1,
};
static int wm2000_i2c_probe(struct i2c_client *i2c)
{
struct wm2000_priv *wm2000;
struct wm2000_platform_data *pdata;
const char *filename;
const struct firmware *fw = NULL;
int ret, i;
unsigned int reg;
u16 id;
wm2000 = devm_kzalloc(&i2c->dev, sizeof(*wm2000), GFP_KERNEL);
if (!wm2000)
return -ENOMEM;
mutex_init(&wm2000->lock);
dev_set_drvdata(&i2c->dev, wm2000);
wm2000->regmap = devm_regmap_init_i2c(i2c, &wm2000_regmap);
if (IS_ERR(wm2000->regmap)) {
ret = PTR_ERR(wm2000->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
goto out;
}
for (i = 0; i < WM2000_NUM_SUPPLIES; i++)
wm2000->supplies[i].supply = wm2000_supplies[i];
ret = devm_regulator_bulk_get(&i2c->dev, WM2000_NUM_SUPPLIES,
wm2000->supplies);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to get supplies: %d\n", ret);
return ret;
}
ret = regulator_bulk_enable(WM2000_NUM_SUPPLIES, wm2000->supplies);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
return ret;
}
/* Verify that this is a WM2000 */
ret = regmap_read(wm2000->regmap, WM2000_REG_ID1, ®);
if (ret != 0) {
dev_err(&i2c->dev, "Unable to read ID1: %d\n", ret);
return ret;
}
id = reg << 8;
ret = regmap_read(wm2000->regmap, WM2000_REG_ID2, ®);
if (ret != 0) {
dev_err(&i2c->dev, "Unable to read ID2: %d\n", ret);
return ret;
}
id |= reg & 0xff;
if (id != 0x2000) {
dev_err(&i2c->dev, "Device is not a WM2000 - ID %x\n", id);
ret = -ENODEV;
goto err_supplies;
}
ret = regmap_read(wm2000->regmap, WM2000_REG_REVISON, ®);
if (ret != 0) {
dev_err(&i2c->dev, "Unable to read Revision: %d\n", ret);
return ret;
}
dev_info(&i2c->dev, "revision %c\n", reg + 'A');
wm2000->mclk = devm_clk_get(&i2c->dev, "MCLK");
if (IS_ERR(wm2000->mclk)) {
ret = PTR_ERR(wm2000->mclk);
dev_err(&i2c->dev, "Failed to get MCLK: %d\n", ret);
goto err_supplies;
}
filename = "wm2000_anc.bin";
pdata = dev_get_platdata(&i2c->dev);
if (pdata) {
wm2000->speech_clarity = !pdata->speech_enh_disable;
if (pdata->download_file)
filename = pdata->download_file;
}
ret = request_firmware(&fw, filename, &i2c->dev);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to acquire ANC data: %d\n", ret);
goto err_supplies;
}
/* Pre-cook the concatenation of the register address onto the image */
wm2000->anc_download_size = fw->size + 2;
wm2000->anc_download = devm_kzalloc(&i2c->dev,
wm2000->anc_download_size,
GFP_KERNEL);
if (wm2000->anc_download == NULL) {
ret = -ENOMEM;
goto err_supplies;
}
wm2000->anc_download[0] = 0x80;
wm2000->anc_download[1] = 0x00;
memcpy(wm2000->anc_download + 2, fw->data, fw->size);
wm2000->anc_eng_ena = 1;
wm2000->anc_active = 1;
wm2000->spk_ena = 1;
wm2000->i2c = i2c;
wm2000_reset(wm2000);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_wm2000, NULL, 0);
err_supplies:
regulator_bulk_disable(WM2000_NUM_SUPPLIES, wm2000->supplies);
out:
release_firmware(fw);
return ret;
}
static const struct i2c_device_id wm2000_i2c_id[] = {
{ "wm2000", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm2000_i2c_id);
static struct i2c_driver wm2000_i2c_driver = {
.driver = {
.name = "wm2000",
},
.probe = wm2000_i2c_probe,
.id_table = wm2000_i2c_id,
};
module_i2c_driver(wm2000_i2c_driver);
MODULE_DESCRIPTION("ASoC WM2000 driver");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm2000.c |
// SPDX-License-Identifier: GPL-2.0
//
// JZ4725B CODEC driver
//
// Copyright (C) 2019, Paul Cercueil <[email protected]>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/regmap.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#define ICDC_RGADW_OFFSET 0x00
#define ICDC_RGDATA_OFFSET 0x04
/* ICDC internal register access control register(RGADW) */
#define ICDC_RGADW_RGWR BIT(16)
#define ICDC_RGADW_RGADDR_OFFSET 8
#define ICDC_RGADW_RGADDR_MASK GENMASK(14, ICDC_RGADW_RGADDR_OFFSET)
#define ICDC_RGADW_RGDIN_OFFSET 0
#define ICDC_RGADW_RGDIN_MASK GENMASK(7, ICDC_RGADW_RGDIN_OFFSET)
/* ICDC internal register data output register (RGDATA)*/
#define ICDC_RGDATA_IRQ BIT(8)
#define ICDC_RGDATA_RGDOUT_OFFSET 0
#define ICDC_RGDATA_RGDOUT_MASK GENMASK(7, ICDC_RGDATA_RGDOUT_OFFSET)
/* JZ internal register space */
enum {
JZ4725B_CODEC_REG_AICR,
JZ4725B_CODEC_REG_CR1,
JZ4725B_CODEC_REG_CR2,
JZ4725B_CODEC_REG_CCR1,
JZ4725B_CODEC_REG_CCR2,
JZ4725B_CODEC_REG_PMR1,
JZ4725B_CODEC_REG_PMR2,
JZ4725B_CODEC_REG_CRR,
JZ4725B_CODEC_REG_ICR,
JZ4725B_CODEC_REG_IFR,
JZ4725B_CODEC_REG_CGR1,
JZ4725B_CODEC_REG_CGR2,
JZ4725B_CODEC_REG_CGR3,
JZ4725B_CODEC_REG_CGR4,
JZ4725B_CODEC_REG_CGR5,
JZ4725B_CODEC_REG_CGR6,
JZ4725B_CODEC_REG_CGR7,
JZ4725B_CODEC_REG_CGR8,
JZ4725B_CODEC_REG_CGR9,
JZ4725B_CODEC_REG_CGR10,
JZ4725B_CODEC_REG_TR1,
JZ4725B_CODEC_REG_TR2,
JZ4725B_CODEC_REG_CR3,
JZ4725B_CODEC_REG_AGC1,
JZ4725B_CODEC_REG_AGC2,
JZ4725B_CODEC_REG_AGC3,
JZ4725B_CODEC_REG_AGC4,
JZ4725B_CODEC_REG_AGC5,
};
#define REG_AICR_CONFIG1_OFFSET 0
#define REG_AICR_CONFIG1_MASK (0xf << REG_AICR_CONFIG1_OFFSET)
#define REG_CR1_SB_MICBIAS_OFFSET 7
#define REG_CR1_MONO_OFFSET 6
#define REG_CR1_DAC_MUTE_OFFSET 5
#define REG_CR1_HP_DIS_OFFSET 4
#define REG_CR1_DACSEL_OFFSET 3
#define REG_CR1_BYPASS_OFFSET 2
#define REG_CR2_DAC_DEEMP_OFFSET 7
#define REG_CR2_DAC_ADWL_OFFSET 5
#define REG_CR2_DAC_ADWL_MASK (0x3 << REG_CR2_DAC_ADWL_OFFSET)
#define REG_CR2_ADC_ADWL_OFFSET 3
#define REG_CR2_ADC_ADWL_MASK (0x3 << REG_CR2_ADC_ADWL_OFFSET)
#define REG_CR2_ADC_HPF_OFFSET 2
#define REG_CR3_SB_MIC1_OFFSET 7
#define REG_CR3_SB_MIC2_OFFSET 6
#define REG_CR3_SIDETONE1_OFFSET 5
#define REG_CR3_SIDETONE2_OFFSET 4
#define REG_CR3_MICDIFF_OFFSET 3
#define REG_CR3_MICSTEREO_OFFSET 2
#define REG_CR3_INSEL_OFFSET 0
#define REG_CR3_INSEL_MASK (0x3 << REG_CR3_INSEL_OFFSET)
#define REG_CCR1_CONFIG4_OFFSET 0
#define REG_CCR1_CONFIG4_MASK (0xf << REG_CCR1_CONFIG4_OFFSET)
#define REG_CCR2_DFREQ_OFFSET 4
#define REG_CCR2_DFREQ_MASK (0xf << REG_CCR2_DFREQ_OFFSET)
#define REG_CCR2_AFREQ_OFFSET 0
#define REG_CCR2_AFREQ_MASK (0xf << REG_CCR2_AFREQ_OFFSET)
#define REG_PMR1_SB_DAC_OFFSET 7
#define REG_PMR1_SB_OUT_OFFSET 6
#define REG_PMR1_SB_MIX_OFFSET 5
#define REG_PMR1_SB_ADC_OFFSET 4
#define REG_PMR1_SB_LIN_OFFSET 3
#define REG_PMR1_SB_IND_OFFSET 0
#define REG_PMR2_LRGI_OFFSET 7
#define REG_PMR2_RLGI_OFFSET 6
#define REG_PMR2_LRGOD_OFFSET 5
#define REG_PMR2_RLGOD_OFFSET 4
#define REG_PMR2_GIM_OFFSET 3
#define REG_PMR2_SB_MC_OFFSET 2
#define REG_PMR2_SB_OFFSET 1
#define REG_PMR2_SB_SLEEP_OFFSET 0
#define REG_IFR_RAMP_UP_DONE_OFFSET 3
#define REG_IFR_RAMP_DOWN_DONE_OFFSET 2
#define REG_CGR1_GODL_OFFSET 4
#define REG_CGR1_GODL_MASK (0xf << REG_CGR1_GODL_OFFSET)
#define REG_CGR1_GODR_OFFSET 0
#define REG_CGR1_GODR_MASK (0xf << REG_CGR1_GODR_OFFSET)
#define REG_CGR2_GO1R_OFFSET 0
#define REG_CGR2_GO1R_MASK (0x1f << REG_CGR2_GO1R_OFFSET)
#define REG_CGR3_GO1L_OFFSET 0
#define REG_CGR3_GO1L_MASK (0x1f << REG_CGR3_GO1L_OFFSET)
#define REG_CGR4_GO2R_OFFSET 0
#define REG_CGR4_GO2R_MASK (0x1f << REG_CGR4_GO2R_OFFSET)
#define REG_CGR5_GO2L_OFFSET 0
#define REG_CGR5_GO2L_MASK (0x1f << REG_CGR5_GO2L_OFFSET)
#define REG_CGR6_GO3R_OFFSET 0
#define REG_CGR6_GO3R_MASK (0x1f << REG_CGR6_GO3R_OFFSET)
#define REG_CGR7_GO3L_OFFSET 0
#define REG_CGR7_GO3L_MASK (0x1f << REG_CGR7_GO3L_OFFSET)
#define REG_CGR8_GOR_OFFSET 0
#define REG_CGR8_GOR_MASK (0x1f << REG_CGR8_GOR_OFFSET)
#define REG_CGR9_GOL_OFFSET 0
#define REG_CGR9_GOL_MASK (0x1f << REG_CGR9_GOL_OFFSET)
#define REG_CGR10_GIL_OFFSET 0
#define REG_CGR10_GIR_OFFSET 4
struct jz_icdc {
struct regmap *regmap;
void __iomem *base;
struct clk *clk;
};
static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(jz4725b_adc_tlv, 0, 150, 0);
static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(jz4725b_dac_tlv, -2250, 150, 0);
static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(jz4725b_mix_tlv,
0, 11, TLV_DB_SCALE_ITEM(-2250, 0, 0),
12, 31, TLV_DB_SCALE_ITEM(-2250, 150, 0),
);
static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(jz4725b_out_tlv,
0, 11, TLV_DB_SCALE_ITEM(-3350, 200, 0),
12, 23, TLV_DB_SCALE_ITEM(-1050, 100, 0),
24, 31, TLV_DB_SCALE_ITEM( 100, 50, 0),
);
static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(jz4725b_mic_boost_tlv, 0, 2000, 0);
static const char * const jz4725b_mic_mode_texts[] = {
"Single Ended", "Differential",
};
static const struct soc_enum jz4725b_mic_mode_enum =
SOC_ENUM_SINGLE(JZ4725B_CODEC_REG_CR3, REG_CR3_MICDIFF_OFFSET,
2, jz4725b_mic_mode_texts);
static const struct snd_kcontrol_new jz4725b_codec_controls[] = {
SOC_DOUBLE_TLV("DAC Playback Volume",
JZ4725B_CODEC_REG_CGR1,
REG_CGR1_GODL_OFFSET,
REG_CGR1_GODR_OFFSET,
0xf, 1, jz4725b_dac_tlv),
SOC_DOUBLE_TLV("Master Capture Volume",
JZ4725B_CODEC_REG_CGR10,
REG_CGR10_GIL_OFFSET,
REG_CGR10_GIR_OFFSET,
0xf, 0, jz4725b_adc_tlv),
SOC_DOUBLE_R_TLV("Mixer Line In Bypass Playback Volume",
JZ4725B_CODEC_REG_CGR3,
JZ4725B_CODEC_REG_CGR2,
REG_CGR2_GO1R_OFFSET,
0x1f, 1, jz4725b_mix_tlv),
SOC_DOUBLE_R_TLV("Mixer Mic 1 Bypass Playback Volume",
JZ4725B_CODEC_REG_CGR5,
JZ4725B_CODEC_REG_CGR4,
REG_CGR4_GO2R_OFFSET,
0x1f, 1, jz4725b_mix_tlv),
SOC_DOUBLE_R_TLV("Mixer Mic 2 Bypass Playback Volume",
JZ4725B_CODEC_REG_CGR7,
JZ4725B_CODEC_REG_CGR6,
REG_CGR6_GO3R_OFFSET,
0x1f, 1, jz4725b_mix_tlv),
SOC_DOUBLE_R_TLV("Master Playback Volume",
JZ4725B_CODEC_REG_CGR9,
JZ4725B_CODEC_REG_CGR8,
REG_CGR8_GOR_OFFSET,
0x1f, 1, jz4725b_out_tlv),
SOC_SINGLE("DAC Playback Switch", JZ4725B_CODEC_REG_CR1,
REG_CR1_DAC_MUTE_OFFSET, 1, 1),
SOC_SINGLE("Deemphasize Filter Playback Switch",
JZ4725B_CODEC_REG_CR2,
REG_CR2_DAC_DEEMP_OFFSET, 1, 0),
SOC_SINGLE("High-Pass Filter Capture Switch",
JZ4725B_CODEC_REG_CR2,
REG_CR2_ADC_HPF_OFFSET, 1, 0),
SOC_ENUM("Mic Mode Capture Switch", jz4725b_mic_mode_enum),
SOC_SINGLE_TLV("Mic1 Boost Capture Volume",
JZ4725B_CODEC_REG_PMR2,
REG_PMR2_GIM_OFFSET,
1, 0, jz4725b_mic_boost_tlv),
};
static const char * const jz4725b_codec_adc_src_texts[] = {
"Mic 1", "Mic 2", "Line In", "Mixer",
};
static const unsigned int jz4725b_codec_adc_src_values[] = { 0, 1, 2, 3, };
static SOC_VALUE_ENUM_SINGLE_DECL(jz4725b_codec_adc_src_enum,
JZ4725B_CODEC_REG_CR3,
REG_CR3_INSEL_OFFSET,
REG_CR3_INSEL_MASK,
jz4725b_codec_adc_src_texts,
jz4725b_codec_adc_src_values);
static const struct snd_kcontrol_new jz4725b_codec_adc_src_ctrl =
SOC_DAPM_ENUM("ADC Source Capture Route", jz4725b_codec_adc_src_enum);
static const struct snd_kcontrol_new jz4725b_codec_mixer_controls[] = {
SOC_DAPM_SINGLE("Line In Bypass Playback Switch", JZ4725B_CODEC_REG_CR1,
REG_CR1_BYPASS_OFFSET, 1, 0),
SOC_DAPM_SINGLE("Mic 1 Bypass Playback Switch", JZ4725B_CODEC_REG_CR3,
REG_CR3_SIDETONE1_OFFSET, 1, 0),
SOC_DAPM_SINGLE("Mic 2 Bypass Playback Switch", JZ4725B_CODEC_REG_CR3,
REG_CR3_SIDETONE2_OFFSET, 1, 0),
};
static int jz4725b_out_stage_enable(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *codec = snd_soc_dapm_to_component(w->dapm);
struct jz_icdc *icdc = snd_soc_component_get_drvdata(codec);
struct regmap *map = icdc->regmap;
unsigned int val;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
return regmap_clear_bits(map, JZ4725B_CODEC_REG_IFR,
BIT(REG_IFR_RAMP_UP_DONE_OFFSET));
case SND_SOC_DAPM_POST_PMU:
return regmap_read_poll_timeout(map, JZ4725B_CODEC_REG_IFR,
val, val & BIT(REG_IFR_RAMP_UP_DONE_OFFSET),
100000, 500000);
case SND_SOC_DAPM_PRE_PMD:
return regmap_clear_bits(map, JZ4725B_CODEC_REG_IFR,
BIT(REG_IFR_RAMP_DOWN_DONE_OFFSET));
case SND_SOC_DAPM_POST_PMD:
return regmap_read_poll_timeout(map, JZ4725B_CODEC_REG_IFR,
val, val & BIT(REG_IFR_RAMP_DOWN_DONE_OFFSET),
100000, 500000);
default:
return -EINVAL;
}
}
static const struct snd_soc_dapm_widget jz4725b_codec_dapm_widgets[] = {
/* DAC */
SND_SOC_DAPM_DAC("DAC", "Playback",
JZ4725B_CODEC_REG_PMR1, REG_PMR1_SB_DAC_OFFSET, 1),
/* ADC */
SND_SOC_DAPM_ADC("ADC", "Capture",
JZ4725B_CODEC_REG_PMR1, REG_PMR1_SB_ADC_OFFSET, 1),
SND_SOC_DAPM_MUX("ADC Source Capture Route", SND_SOC_NOPM, 0, 0,
&jz4725b_codec_adc_src_ctrl),
/* Mixer */
SND_SOC_DAPM_MIXER("Mixer", JZ4725B_CODEC_REG_PMR1,
REG_PMR1_SB_MIX_OFFSET, 1,
jz4725b_codec_mixer_controls,
ARRAY_SIZE(jz4725b_codec_mixer_controls)),
SND_SOC_DAPM_MIXER("DAC to Mixer", JZ4725B_CODEC_REG_CR1,
REG_CR1_DACSEL_OFFSET, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Line In", JZ4725B_CODEC_REG_PMR1,
REG_PMR1_SB_LIN_OFFSET, 1, NULL, 0),
SND_SOC_DAPM_MIXER("HP Out", JZ4725B_CODEC_REG_CR1,
REG_CR1_HP_DIS_OFFSET, 1, NULL, 0),
SND_SOC_DAPM_MIXER("Mic 1", JZ4725B_CODEC_REG_CR3,
REG_CR3_SB_MIC1_OFFSET, 1, NULL, 0),
SND_SOC_DAPM_MIXER("Mic 2", JZ4725B_CODEC_REG_CR3,
REG_CR3_SB_MIC2_OFFSET, 1, NULL, 0),
SND_SOC_DAPM_MIXER_E("Out Stage", JZ4725B_CODEC_REG_PMR1,
REG_PMR1_SB_OUT_OFFSET, 1, NULL, 0,
jz4725b_out_stage_enable,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER("Mixer to ADC", JZ4725B_CODEC_REG_PMR1,
REG_PMR1_SB_IND_OFFSET, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("Mic Bias", JZ4725B_CODEC_REG_CR1,
REG_CR1_SB_MICBIAS_OFFSET, 1, NULL, 0),
/* Pins */
SND_SOC_DAPM_INPUT("MIC1P"),
SND_SOC_DAPM_INPUT("MIC1N"),
SND_SOC_DAPM_INPUT("MIC2P"),
SND_SOC_DAPM_INPUT("MIC2N"),
SND_SOC_DAPM_INPUT("LLINEIN"),
SND_SOC_DAPM_INPUT("RLINEIN"),
SND_SOC_DAPM_OUTPUT("LHPOUT"),
SND_SOC_DAPM_OUTPUT("RHPOUT"),
};
static const struct snd_soc_dapm_route jz4725b_codec_dapm_routes[] = {
{"Mic 1", NULL, "MIC1P"},
{"Mic 1", NULL, "MIC1N"},
{"Mic 2", NULL, "MIC2P"},
{"Mic 2", NULL, "MIC2N"},
{"Line In", NULL, "LLINEIN"},
{"Line In", NULL, "RLINEIN"},
{"Mixer", "Mic 1 Bypass Playback Switch", "Mic 1"},
{"Mixer", "Mic 2 Bypass Playback Switch", "Mic 2"},
{"Mixer", "Line In Bypass Playback Switch", "Line In"},
{"DAC to Mixer", NULL, "DAC"},
{"Mixer", NULL, "DAC to Mixer"},
{"Mixer to ADC", NULL, "Mixer"},
{"ADC Source Capture Route", "Mixer", "Mixer to ADC"},
{"ADC Source Capture Route", "Line In", "Line In"},
{"ADC Source Capture Route", "Mic 1", "Mic 1"},
{"ADC Source Capture Route", "Mic 2", "Mic 2"},
{"ADC", NULL, "ADC Source Capture Route"},
{"Out Stage", NULL, "Mixer"},
{"HP Out", NULL, "Out Stage"},
{"LHPOUT", NULL, "HP Out"},
{"RHPOUT", NULL, "HP Out"},
};
static int jz4725b_codec_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct jz_icdc *icdc = snd_soc_component_get_drvdata(component);
struct regmap *map = icdc->regmap;
switch (level) {
case SND_SOC_BIAS_ON:
regmap_clear_bits(map, JZ4725B_CODEC_REG_PMR2,
BIT(REG_PMR2_SB_SLEEP_OFFSET));
break;
case SND_SOC_BIAS_PREPARE:
/* Enable sound hardware */
regmap_clear_bits(map, JZ4725B_CODEC_REG_PMR2,
BIT(REG_PMR2_SB_OFFSET));
msleep(224);
break;
case SND_SOC_BIAS_STANDBY:
regmap_set_bits(map, JZ4725B_CODEC_REG_PMR2,
BIT(REG_PMR2_SB_SLEEP_OFFSET));
break;
case SND_SOC_BIAS_OFF:
regmap_set_bits(map, JZ4725B_CODEC_REG_PMR2,
BIT(REG_PMR2_SB_OFFSET));
break;
}
return 0;
}
static int jz4725b_codec_dev_probe(struct snd_soc_component *component)
{
struct jz_icdc *icdc = snd_soc_component_get_drvdata(component);
struct regmap *map = icdc->regmap;
clk_prepare_enable(icdc->clk);
/* Write CONFIGn (n=1 to 8) bits.
* The value 0x0f is specified in the datasheet as a requirement.
*/
regmap_write(map, JZ4725B_CODEC_REG_AICR,
0xf << REG_AICR_CONFIG1_OFFSET);
regmap_write(map, JZ4725B_CODEC_REG_CCR1,
0x0 << REG_CCR1_CONFIG4_OFFSET);
return 0;
}
static void jz4725b_codec_dev_remove(struct snd_soc_component *component)
{
struct jz_icdc *icdc = snd_soc_component_get_drvdata(component);
clk_disable_unprepare(icdc->clk);
}
static const struct snd_soc_component_driver jz4725b_codec = {
.probe = jz4725b_codec_dev_probe,
.remove = jz4725b_codec_dev_remove,
.set_bias_level = jz4725b_codec_set_bias_level,
.controls = jz4725b_codec_controls,
.num_controls = ARRAY_SIZE(jz4725b_codec_controls),
.dapm_widgets = jz4725b_codec_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(jz4725b_codec_dapm_widgets),
.dapm_routes = jz4725b_codec_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(jz4725b_codec_dapm_routes),
.suspend_bias_off = 1,
.use_pmdown_time = 1,
};
static const unsigned int jz4725b_codec_sample_rates[] = {
96000, 48000, 44100, 32000,
24000, 22050, 16000, 12000,
11025, 9600, 8000,
};
static int jz4725b_codec_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct jz_icdc *icdc = snd_soc_component_get_drvdata(dai->component);
unsigned int rate, bit_width;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
bit_width = 0;
break;
case SNDRV_PCM_FORMAT_S18_3LE:
bit_width = 1;
break;
case SNDRV_PCM_FORMAT_S20_3LE:
bit_width = 2;
break;
case SNDRV_PCM_FORMAT_S24_3LE:
bit_width = 3;
break;
default:
return -EINVAL;
}
for (rate = 0; rate < ARRAY_SIZE(jz4725b_codec_sample_rates); rate++) {
if (jz4725b_codec_sample_rates[rate] == params_rate(params))
break;
}
if (rate == ARRAY_SIZE(jz4725b_codec_sample_rates))
return -EINVAL;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
regmap_update_bits(icdc->regmap,
JZ4725B_CODEC_REG_CR2,
REG_CR2_DAC_ADWL_MASK,
bit_width << REG_CR2_DAC_ADWL_OFFSET);
regmap_update_bits(icdc->regmap,
JZ4725B_CODEC_REG_CCR2,
REG_CCR2_DFREQ_MASK,
rate << REG_CCR2_DFREQ_OFFSET);
} else {
regmap_update_bits(icdc->regmap,
JZ4725B_CODEC_REG_CR2,
REG_CR2_ADC_ADWL_MASK,
bit_width << REG_CR2_ADC_ADWL_OFFSET);
regmap_update_bits(icdc->regmap,
JZ4725B_CODEC_REG_CCR2,
REG_CCR2_AFREQ_MASK,
rate << REG_CCR2_AFREQ_OFFSET);
}
return 0;
}
static const struct snd_soc_dai_ops jz4725b_codec_dai_ops = {
.hw_params = jz4725b_codec_hw_params,
};
#define JZ_ICDC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \
SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_3LE)
static struct snd_soc_dai_driver jz4725b_codec_dai = {
.name = "jz4725b-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = JZ_ICDC_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = JZ_ICDC_FORMATS,
},
.ops = &jz4725b_codec_dai_ops,
};
static bool jz4725b_codec_volatile(struct device *dev, unsigned int reg)
{
return reg == JZ4725B_CODEC_REG_IFR;
}
static bool jz4725b_codec_can_access_reg(struct device *dev, unsigned int reg)
{
return (reg != JZ4725B_CODEC_REG_TR1) && (reg != JZ4725B_CODEC_REG_TR2);
}
static int jz4725b_codec_io_wait(struct jz_icdc *icdc)
{
u32 reg;
return readl_poll_timeout(icdc->base + ICDC_RGADW_OFFSET, reg,
!(reg & ICDC_RGADW_RGWR), 1000, 10000);
}
static int jz4725b_codec_reg_read(void *context, unsigned int reg,
unsigned int *val)
{
struct jz_icdc *icdc = context;
unsigned int i;
u32 tmp;
int ret;
ret = jz4725b_codec_io_wait(icdc);
if (ret)
return ret;
tmp = readl(icdc->base + ICDC_RGADW_OFFSET);
tmp = (tmp & ~ICDC_RGADW_RGADDR_MASK)
| (reg << ICDC_RGADW_RGADDR_OFFSET);
writel(tmp, icdc->base + ICDC_RGADW_OFFSET);
/* wait 6+ cycles */
for (i = 0; i < 6; i++)
*val = readl(icdc->base + ICDC_RGDATA_OFFSET) &
ICDC_RGDATA_RGDOUT_MASK;
return 0;
}
static int jz4725b_codec_reg_write(void *context, unsigned int reg,
unsigned int val)
{
struct jz_icdc *icdc = context;
int ret;
ret = jz4725b_codec_io_wait(icdc);
if (ret)
return ret;
writel(ICDC_RGADW_RGWR | (reg << ICDC_RGADW_RGADDR_OFFSET) | val,
icdc->base + ICDC_RGADW_OFFSET);
ret = jz4725b_codec_io_wait(icdc);
if (ret)
return ret;
return 0;
}
static const u8 jz4725b_codec_reg_defaults[] = {
0x0c, 0xaa, 0x78, 0x00, 0x00, 0xff, 0x03, 0x51,
0x3f, 0x00, 0x00, 0x04, 0x04, 0x04, 0x04, 0x04,
0x04, 0x0a, 0x0a, 0x00, 0x00, 0x00, 0xc0, 0x34,
0x07, 0x44, 0x1f, 0x00,
};
static const struct regmap_config jz4725b_codec_regmap_config = {
.reg_bits = 7,
.val_bits = 8,
.max_register = JZ4725B_CODEC_REG_AGC5,
.volatile_reg = jz4725b_codec_volatile,
.readable_reg = jz4725b_codec_can_access_reg,
.writeable_reg = jz4725b_codec_can_access_reg,
.reg_read = jz4725b_codec_reg_read,
.reg_write = jz4725b_codec_reg_write,
.reg_defaults_raw = jz4725b_codec_reg_defaults,
.num_reg_defaults_raw = ARRAY_SIZE(jz4725b_codec_reg_defaults),
.cache_type = REGCACHE_FLAT,
};
static int jz4725b_codec_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct jz_icdc *icdc;
int ret;
icdc = devm_kzalloc(dev, sizeof(*icdc), GFP_KERNEL);
if (!icdc)
return -ENOMEM;
icdc->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(icdc->base))
return PTR_ERR(icdc->base);
icdc->regmap = devm_regmap_init(dev, NULL, icdc,
&jz4725b_codec_regmap_config);
if (IS_ERR(icdc->regmap))
return PTR_ERR(icdc->regmap);
icdc->clk = devm_clk_get(&pdev->dev, "aic");
if (IS_ERR(icdc->clk))
return PTR_ERR(icdc->clk);
platform_set_drvdata(pdev, icdc);
ret = devm_snd_soc_register_component(dev, &jz4725b_codec,
&jz4725b_codec_dai, 1);
if (ret)
dev_err(dev, "Failed to register codec\n");
return ret;
}
static const struct of_device_id jz4725b_codec_of_matches[] = {
{ .compatible = "ingenic,jz4725b-codec", },
{ }
};
MODULE_DEVICE_TABLE(of, jz4725b_codec_of_matches);
static struct platform_driver jz4725b_codec_driver = {
.probe = jz4725b_codec_probe,
.driver = {
.name = "jz4725b-codec",
.of_match_table = jz4725b_codec_of_matches,
},
};
module_platform_driver(jz4725b_codec_driver);
MODULE_DESCRIPTION("JZ4725B SoC internal codec driver");
MODULE_AUTHOR("Paul Cercueil <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/jz4725b.c |
// SPDX-License-Identifier: GPL-2.0
//
// mt6358.c -- mt6358 ALSA SoC audio codec driver
//
// Copyright (c) 2018 MediaTek Inc.
// Author: KaiChieh Chuang <[email protected]>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/delay.h>
#include <linux/kthread.h>
#include <linux/sched.h>
#include <linux/mfd/mt6397/core.h>
#include <linux/regulator/consumer.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include "mt6358.h"
enum {
AUDIO_ANALOG_VOLUME_HSOUTL,
AUDIO_ANALOG_VOLUME_HSOUTR,
AUDIO_ANALOG_VOLUME_HPOUTL,
AUDIO_ANALOG_VOLUME_HPOUTR,
AUDIO_ANALOG_VOLUME_LINEOUTL,
AUDIO_ANALOG_VOLUME_LINEOUTR,
AUDIO_ANALOG_VOLUME_MICAMP1,
AUDIO_ANALOG_VOLUME_MICAMP2,
AUDIO_ANALOG_VOLUME_TYPE_MAX
};
enum {
MUX_ADC_L,
MUX_ADC_R,
MUX_PGA_L,
MUX_PGA_R,
MUX_MIC_TYPE,
MUX_HP_L,
MUX_HP_R,
MUX_NUM,
};
enum {
DEVICE_HP,
DEVICE_LO,
DEVICE_RCV,
DEVICE_MIC1,
DEVICE_MIC2,
DEVICE_NUM
};
/* Supply widget subseq */
enum {
/* common */
SUPPLY_SEQ_CLK_BUF,
SUPPLY_SEQ_AUD_GLB,
SUPPLY_SEQ_CLKSQ,
SUPPLY_SEQ_VOW_AUD_LPW,
SUPPLY_SEQ_AUD_VOW,
SUPPLY_SEQ_VOW_CLK,
SUPPLY_SEQ_VOW_LDO,
SUPPLY_SEQ_TOP_CK,
SUPPLY_SEQ_TOP_CK_LAST,
SUPPLY_SEQ_AUD_TOP,
SUPPLY_SEQ_AUD_TOP_LAST,
SUPPLY_SEQ_AFE,
/* capture */
SUPPLY_SEQ_ADC_SUPPLY,
};
enum {
CH_L = 0,
CH_R,
NUM_CH,
};
#define REG_STRIDE 2
struct mt6358_priv {
struct device *dev;
struct regmap *regmap;
unsigned int dl_rate;
unsigned int ul_rate;
int ana_gain[AUDIO_ANALOG_VOLUME_TYPE_MAX];
unsigned int mux_select[MUX_NUM];
int dev_counter[DEVICE_NUM];
int mtkaif_protocol;
struct regulator *avdd_reg;
int wov_enabled;
unsigned int dmic_one_wire_mode;
};
int mt6358_set_mtkaif_protocol(struct snd_soc_component *cmpnt,
int mtkaif_protocol)
{
struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
priv->mtkaif_protocol = mtkaif_protocol;
return 0;
}
EXPORT_SYMBOL_GPL(mt6358_set_mtkaif_protocol);
static void playback_gpio_set(struct mt6358_priv *priv)
{
/* set gpio mosi mode */
regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR,
0x01f8, 0x01f8);
regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_SET,
0xffff, 0x0249);
regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2,
0xffff, 0x0249);
}
static void playback_gpio_reset(struct mt6358_priv *priv)
{
/* set pad_aud_*_mosi to GPIO mode and dir input
* reason:
* pad_aud_dat_mosi*, because the pin is used as boot strap
* don't clean clk/sync, for mtkaif protocol 2
*/
regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR,
0x01f8, 0x01f8);
regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2,
0x01f8, 0x0000);
regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0,
0xf << 8, 0x0);
}
static void capture_gpio_set(struct mt6358_priv *priv)
{
/* set gpio miso mode */
regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR,
0xffff, 0xffff);
regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_SET,
0xffff, 0x0249);
regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3,
0xffff, 0x0249);
}
static void capture_gpio_reset(struct mt6358_priv *priv)
{
/* set pad_aud_*_miso to GPIO mode and dir input
* reason:
* pad_aud_clk_miso, because when playback only the miso_clk
* will also have 26m, so will have power leak
* pad_aud_dat_miso*, because the pin is used as boot strap
*/
regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR,
0xffff, 0xffff);
regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3,
0xffff, 0x0000);
regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0,
0xf << 12, 0x0);
}
/* use only when not govern by DAPM */
static int mt6358_set_dcxo(struct mt6358_priv *priv, bool enable)
{
regmap_update_bits(priv->regmap, MT6358_DCXO_CW14,
0x1 << RG_XO_AUDIO_EN_M_SFT,
(enable ? 1 : 0) << RG_XO_AUDIO_EN_M_SFT);
return 0;
}
/* use only when not govern by DAPM */
static int mt6358_set_clksq(struct mt6358_priv *priv, bool enable)
{
/* audio clk source from internal dcxo */
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6,
RG_CLKSQ_IN_SEL_TEST_MASK_SFT,
0x0);
/* Enable/disable CLKSQ 26MHz */
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6,
RG_CLKSQ_EN_MASK_SFT,
(enable ? 1 : 0) << RG_CLKSQ_EN_SFT);
return 0;
}
/* use only when not govern by DAPM */
static int mt6358_set_aud_global_bias(struct mt6358_priv *priv, bool enable)
{
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
RG_AUDGLB_PWRDN_VA28_MASK_SFT,
(enable ? 0 : 1) << RG_AUDGLB_PWRDN_VA28_SFT);
return 0;
}
/* use only when not govern by DAPM */
static int mt6358_set_topck(struct mt6358_priv *priv, bool enable)
{
regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0,
0x0066, enable ? 0x0 : 0x66);
return 0;
}
static int mt6358_mtkaif_tx_enable(struct mt6358_priv *priv)
{
switch (priv->mtkaif_protocol) {
case MT6358_MTKAIF_PROTOCOL_2_CLK_P2:
/* MTKAIF TX format setting */
regmap_update_bits(priv->regmap,
MT6358_AFE_ADDA_MTKAIF_CFG0,
0xffff, 0x0010);
/* enable aud_pad TX fifos */
regmap_update_bits(priv->regmap,
MT6358_AFE_AUD_PAD_TOP,
0xff00, 0x3800);
regmap_update_bits(priv->regmap,
MT6358_AFE_AUD_PAD_TOP,
0xff00, 0x3900);
break;
case MT6358_MTKAIF_PROTOCOL_2:
/* MTKAIF TX format setting */
regmap_update_bits(priv->regmap,
MT6358_AFE_ADDA_MTKAIF_CFG0,
0xffff, 0x0010);
/* enable aud_pad TX fifos */
regmap_update_bits(priv->regmap,
MT6358_AFE_AUD_PAD_TOP,
0xff00, 0x3100);
break;
case MT6358_MTKAIF_PROTOCOL_1:
default:
/* MTKAIF TX format setting */
regmap_update_bits(priv->regmap,
MT6358_AFE_ADDA_MTKAIF_CFG0,
0xffff, 0x0000);
/* enable aud_pad TX fifos */
regmap_update_bits(priv->regmap,
MT6358_AFE_AUD_PAD_TOP,
0xff00, 0x3100);
break;
}
return 0;
}
static int mt6358_mtkaif_tx_disable(struct mt6358_priv *priv)
{
/* disable aud_pad TX fifos */
regmap_update_bits(priv->regmap, MT6358_AFE_AUD_PAD_TOP,
0xff00, 0x3000);
return 0;
}
int mt6358_mtkaif_calibration_enable(struct snd_soc_component *cmpnt)
{
struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
playback_gpio_set(priv);
capture_gpio_set(priv);
mt6358_mtkaif_tx_enable(priv);
mt6358_set_dcxo(priv, true);
mt6358_set_aud_global_bias(priv, true);
mt6358_set_clksq(priv, true);
mt6358_set_topck(priv, true);
/* set dat_miso_loopback on */
regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT,
1 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT);
regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT,
1 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT);
return 0;
}
EXPORT_SYMBOL_GPL(mt6358_mtkaif_calibration_enable);
int mt6358_mtkaif_calibration_disable(struct snd_soc_component *cmpnt)
{
struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
/* set dat_miso_loopback off */
regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT,
0 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT);
regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT,
0 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT);
mt6358_set_topck(priv, false);
mt6358_set_clksq(priv, false);
mt6358_set_aud_global_bias(priv, false);
mt6358_set_dcxo(priv, false);
mt6358_mtkaif_tx_disable(priv);
playback_gpio_reset(priv);
capture_gpio_reset(priv);
return 0;
}
EXPORT_SYMBOL_GPL(mt6358_mtkaif_calibration_disable);
int mt6358_set_mtkaif_calibration_phase(struct snd_soc_component *cmpnt,
int phase_1, int phase_2)
{
struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
RG_AUD_PAD_TOP_PHASE_MODE_MASK_SFT,
phase_1 << RG_AUD_PAD_TOP_PHASE_MODE_SFT);
regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
RG_AUD_PAD_TOP_PHASE_MODE2_MASK_SFT,
phase_2 << RG_AUD_PAD_TOP_PHASE_MODE2_SFT);
return 0;
}
EXPORT_SYMBOL_GPL(mt6358_set_mtkaif_calibration_phase);
/* dl pga gain */
enum {
DL_GAIN_8DB = 0,
DL_GAIN_0DB = 8,
DL_GAIN_N_1DB = 9,
DL_GAIN_N_10DB = 18,
DL_GAIN_N_40DB = 0x1f,
};
#define DL_GAIN_N_10DB_REG (DL_GAIN_N_10DB << 7 | DL_GAIN_N_10DB)
#define DL_GAIN_N_40DB_REG (DL_GAIN_N_40DB << 7 | DL_GAIN_N_40DB)
#define DL_GAIN_REG_MASK 0x0f9f
static void hp_zcd_disable(struct mt6358_priv *priv)
{
regmap_write(priv->regmap, MT6358_ZCD_CON0, 0x0000);
}
static void hp_main_output_ramp(struct mt6358_priv *priv, bool up)
{
int i, stage;
int target = 7;
/* Enable/Reduce HPL/R main output stage step by step */
for (i = 0; i <= target; i++) {
stage = up ? i : target - i;
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
0x7 << 8, stage << 8);
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
0x7 << 11, stage << 11);
usleep_range(100, 150);
}
}
static void hp_aux_feedback_loop_gain_ramp(struct mt6358_priv *priv, bool up)
{
int i, stage;
/* Reduce HP aux feedback loop gain step by step */
for (i = 0; i <= 0xf; i++) {
stage = up ? i : 0xf - i;
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
0xf << 12, stage << 12);
usleep_range(100, 150);
}
}
static void hp_pull_down(struct mt6358_priv *priv, bool enable)
{
int i;
if (enable) {
for (i = 0x0; i <= 0x6; i++) {
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
0x7, i);
usleep_range(600, 700);
}
} else {
for (i = 0x6; i >= 0x1; i--) {
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
0x7, i);
usleep_range(600, 700);
}
}
}
static bool is_valid_hp_pga_idx(int reg_idx)
{
return (reg_idx >= DL_GAIN_8DB && reg_idx <= DL_GAIN_N_10DB) ||
reg_idx == DL_GAIN_N_40DB;
}
static void headset_volume_ramp(struct mt6358_priv *priv, int from, int to)
{
int offset = 0, count = 0, reg_idx;
if (!is_valid_hp_pga_idx(from) || !is_valid_hp_pga_idx(to))
dev_warn(priv->dev, "%s(), volume index is not valid, from %d, to %d\n",
__func__, from, to);
dev_info(priv->dev, "%s(), from %d, to %d\n",
__func__, from, to);
if (to > from)
offset = to - from;
else
offset = from - to;
while (offset >= 0) {
if (to > from)
reg_idx = from + count;
else
reg_idx = from - count;
if (is_valid_hp_pga_idx(reg_idx)) {
regmap_update_bits(priv->regmap,
MT6358_ZCD_CON2,
DL_GAIN_REG_MASK,
(reg_idx << 7) | reg_idx);
usleep_range(200, 300);
}
offset--;
count++;
}
}
static int mt6358_put_volsw(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct mt6358_priv *priv = snd_soc_component_get_drvdata(component);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
unsigned int reg = 0;
int ret;
ret = snd_soc_put_volsw(kcontrol, ucontrol);
if (ret < 0)
return ret;
switch (mc->reg) {
case MT6358_ZCD_CON2:
regmap_read(priv->regmap, MT6358_ZCD_CON2, ®);
priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] =
(reg >> RG_AUDHPLGAIN_SFT) & RG_AUDHPLGAIN_MASK;
priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] =
(reg >> RG_AUDHPRGAIN_SFT) & RG_AUDHPRGAIN_MASK;
break;
case MT6358_ZCD_CON1:
regmap_read(priv->regmap, MT6358_ZCD_CON1, ®);
priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] =
(reg >> RG_AUDLOLGAIN_SFT) & RG_AUDLOLGAIN_MASK;
priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] =
(reg >> RG_AUDLORGAIN_SFT) & RG_AUDLORGAIN_MASK;
break;
case MT6358_ZCD_CON3:
regmap_read(priv->regmap, MT6358_ZCD_CON3, ®);
priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL] =
(reg >> RG_AUDHSGAIN_SFT) & RG_AUDHSGAIN_MASK;
priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTR] =
(reg >> RG_AUDHSGAIN_SFT) & RG_AUDHSGAIN_MASK;
break;
case MT6358_AUDENC_ANA_CON0:
case MT6358_AUDENC_ANA_CON1:
regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON0, ®);
priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1] =
(reg >> RG_AUDPREAMPLGAIN_SFT) & RG_AUDPREAMPLGAIN_MASK;
regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON1, ®);
priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2] =
(reg >> RG_AUDPREAMPRGAIN_SFT) & RG_AUDPREAMPRGAIN_MASK;
break;
}
return ret;
}
static void mt6358_restore_pga(struct mt6358_priv *priv);
static int mt6358_enable_wov_phase2(struct mt6358_priv *priv)
{
/* analog */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
0xffff, 0x0000);
regmap_update_bits(priv->regmap, MT6358_DCXO_CW14, 0xffff, 0xa2b5);
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
0xffff, 0x0800);
mt6358_restore_pga(priv);
regmap_update_bits(priv->regmap, MT6358_DCXO_CW13, 0xffff, 0x9929);
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
0xffff, 0x0025);
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON8,
0xffff, 0x0005);
/* digital */
regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0,
0xffff, 0x0000);
regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 0xffff, 0x0120);
regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG0, 0xffff, 0xffff);
regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG1, 0xffff, 0x0200);
regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG2, 0xffff, 0x2424);
regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG3, 0xffff, 0xdbac);
regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG4, 0xffff, 0x029e);
regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG5, 0xffff, 0x0000);
regmap_update_bits(priv->regmap, MT6358_AFE_VOW_POSDIV_CFG0,
0xffff, 0x0000);
regmap_update_bits(priv->regmap, MT6358_AFE_VOW_HPF_CFG0,
0xffff, 0x0451);
regmap_update_bits(priv->regmap, MT6358_AFE_VOW_TOP, 0xffff, 0x68d1);
return 0;
}
static int mt6358_disable_wov_phase2(struct mt6358_priv *priv)
{
/* digital */
regmap_update_bits(priv->regmap, MT6358_AFE_VOW_TOP, 0xffff, 0xc000);
regmap_update_bits(priv->regmap, MT6358_AFE_VOW_HPF_CFG0,
0xffff, 0x0450);
regmap_update_bits(priv->regmap, MT6358_AFE_VOW_POSDIV_CFG0,
0xffff, 0x0c00);
regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG5, 0xffff, 0x0100);
regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG4, 0xffff, 0x006c);
regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG3, 0xffff, 0xa879);
regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG2, 0xffff, 0x2323);
regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG1, 0xffff, 0x0400);
regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG0, 0xffff, 0x0000);
regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 0xffff, 0x02d8);
regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0,
0xffff, 0x0000);
/* analog */
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON8,
0xffff, 0x0004);
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
0xffff, 0x0000);
regmap_update_bits(priv->regmap, MT6358_DCXO_CW13, 0xffff, 0x9829);
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
0xffff, 0x0000);
mt6358_restore_pga(priv);
regmap_update_bits(priv->regmap, MT6358_DCXO_CW14, 0xffff, 0xa2b5);
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
0xffff, 0x0010);
return 0;
}
static int mt6358_get_wov(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *c = snd_soc_kcontrol_component(kcontrol);
struct mt6358_priv *priv = snd_soc_component_get_drvdata(c);
ucontrol->value.integer.value[0] = priv->wov_enabled;
return 0;
}
static int mt6358_put_wov(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *c = snd_soc_kcontrol_component(kcontrol);
struct mt6358_priv *priv = snd_soc_component_get_drvdata(c);
int enabled = ucontrol->value.integer.value[0];
if (enabled < 0 || enabled > 1)
return -EINVAL;
if (priv->wov_enabled != enabled) {
if (enabled)
mt6358_enable_wov_phase2(priv);
else
mt6358_disable_wov_phase2(priv);
priv->wov_enabled = enabled;
return 1;
}
return 0;
}
static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0);
static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 600, 0);
static const struct snd_kcontrol_new mt6358_snd_controls[] = {
/* dl pga gain */
SOC_DOUBLE_EXT_TLV("Headphone Volume",
MT6358_ZCD_CON2, 0, 7, 0x12, 1,
snd_soc_get_volsw, mt6358_put_volsw, playback_tlv),
SOC_DOUBLE_EXT_TLV("Lineout Volume",
MT6358_ZCD_CON1, 0, 7, 0x12, 1,
snd_soc_get_volsw, mt6358_put_volsw, playback_tlv),
SOC_SINGLE_EXT_TLV("Handset Volume",
MT6358_ZCD_CON3, 0, 0x12, 1,
snd_soc_get_volsw, mt6358_put_volsw, playback_tlv),
/* ul pga gain */
SOC_DOUBLE_R_EXT_TLV("PGA Volume",
MT6358_AUDENC_ANA_CON0, MT6358_AUDENC_ANA_CON1,
8, 4, 0,
snd_soc_get_volsw, mt6358_put_volsw, pga_tlv),
SOC_SINGLE_BOOL_EXT("Wake-on-Voice Phase2 Switch", 0,
mt6358_get_wov, mt6358_put_wov),
};
/* MUX */
/* LOL MUX */
static const char * const lo_in_mux_map[] = {
"Open", "Mute", "Playback", "Test Mode"
};
static int lo_in_mux_map_value[] = {
0x0, 0x1, 0x2, 0x3,
};
static SOC_VALUE_ENUM_SINGLE_DECL(lo_in_mux_map_enum,
MT6358_AUDDEC_ANA_CON7,
RG_AUDLOLMUXINPUTSEL_VAUDP15_SFT,
RG_AUDLOLMUXINPUTSEL_VAUDP15_MASK,
lo_in_mux_map,
lo_in_mux_map_value);
static const struct snd_kcontrol_new lo_in_mux_control =
SOC_DAPM_ENUM("In Select", lo_in_mux_map_enum);
/*HP MUX */
enum {
HP_MUX_OPEN = 0,
HP_MUX_HPSPK,
HP_MUX_HP,
HP_MUX_TEST_MODE,
HP_MUX_HP_IMPEDANCE,
HP_MUX_MASK = 0x7,
};
static const char * const hp_in_mux_map[] = {
"Open",
"LoudSPK Playback",
"Audio Playback",
"Test Mode",
"HP Impedance",
};
static int hp_in_mux_map_value[] = {
HP_MUX_OPEN,
HP_MUX_HPSPK,
HP_MUX_HP,
HP_MUX_TEST_MODE,
HP_MUX_HP_IMPEDANCE,
};
static SOC_VALUE_ENUM_SINGLE_DECL(hpl_in_mux_map_enum,
SND_SOC_NOPM,
0,
HP_MUX_MASK,
hp_in_mux_map,
hp_in_mux_map_value);
static const struct snd_kcontrol_new hpl_in_mux_control =
SOC_DAPM_ENUM("HPL Select", hpl_in_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(hpr_in_mux_map_enum,
SND_SOC_NOPM,
0,
HP_MUX_MASK,
hp_in_mux_map,
hp_in_mux_map_value);
static const struct snd_kcontrol_new hpr_in_mux_control =
SOC_DAPM_ENUM("HPR Select", hpr_in_mux_map_enum);
/* RCV MUX */
enum {
RCV_MUX_OPEN = 0,
RCV_MUX_MUTE,
RCV_MUX_VOICE_PLAYBACK,
RCV_MUX_TEST_MODE,
RCV_MUX_MASK = 0x3,
};
static const char * const rcv_in_mux_map[] = {
"Open", "Mute", "Voice Playback", "Test Mode"
};
static int rcv_in_mux_map_value[] = {
RCV_MUX_OPEN,
RCV_MUX_MUTE,
RCV_MUX_VOICE_PLAYBACK,
RCV_MUX_TEST_MODE,
};
static SOC_VALUE_ENUM_SINGLE_DECL(rcv_in_mux_map_enum,
SND_SOC_NOPM,
0,
RCV_MUX_MASK,
rcv_in_mux_map,
rcv_in_mux_map_value);
static const struct snd_kcontrol_new rcv_in_mux_control =
SOC_DAPM_ENUM("RCV Select", rcv_in_mux_map_enum);
/* DAC In MUX */
static const char * const dac_in_mux_map[] = {
"Normal Path", "Sgen"
};
static int dac_in_mux_map_value[] = {
0x0, 0x1,
};
static SOC_VALUE_ENUM_SINGLE_DECL(dac_in_mux_map_enum,
MT6358_AFE_TOP_CON0,
DL_SINE_ON_SFT,
DL_SINE_ON_MASK,
dac_in_mux_map,
dac_in_mux_map_value);
static const struct snd_kcontrol_new dac_in_mux_control =
SOC_DAPM_ENUM("DAC Select", dac_in_mux_map_enum);
/* AIF Out MUX */
static SOC_VALUE_ENUM_SINGLE_DECL(aif_out_mux_map_enum,
MT6358_AFE_TOP_CON0,
UL_SINE_ON_SFT,
UL_SINE_ON_MASK,
dac_in_mux_map,
dac_in_mux_map_value);
static const struct snd_kcontrol_new aif_out_mux_control =
SOC_DAPM_ENUM("AIF Out Select", aif_out_mux_map_enum);
/* Mic Type MUX */
enum {
MIC_TYPE_MUX_IDLE = 0,
MIC_TYPE_MUX_ACC,
MIC_TYPE_MUX_DMIC,
MIC_TYPE_MUX_DCC,
MIC_TYPE_MUX_DCC_ECM_DIFF,
MIC_TYPE_MUX_DCC_ECM_SINGLE,
MIC_TYPE_MUX_MASK = 0x7,
};
#define IS_DCC_BASE(type) ((type) == MIC_TYPE_MUX_DCC || \
(type) == MIC_TYPE_MUX_DCC_ECM_DIFF || \
(type) == MIC_TYPE_MUX_DCC_ECM_SINGLE)
static const char * const mic_type_mux_map[] = {
"Idle",
"ACC",
"DMIC",
"DCC",
"DCC_ECM_DIFF",
"DCC_ECM_SINGLE",
};
static int mic_type_mux_map_value[] = {
MIC_TYPE_MUX_IDLE,
MIC_TYPE_MUX_ACC,
MIC_TYPE_MUX_DMIC,
MIC_TYPE_MUX_DCC,
MIC_TYPE_MUX_DCC_ECM_DIFF,
MIC_TYPE_MUX_DCC_ECM_SINGLE,
};
static SOC_VALUE_ENUM_SINGLE_DECL(mic_type_mux_map_enum,
SND_SOC_NOPM,
0,
MIC_TYPE_MUX_MASK,
mic_type_mux_map,
mic_type_mux_map_value);
static const struct snd_kcontrol_new mic_type_mux_control =
SOC_DAPM_ENUM("Mic Type Select", mic_type_mux_map_enum);
/* ADC L MUX */
enum {
ADC_MUX_IDLE = 0,
ADC_MUX_AIN0,
ADC_MUX_PREAMPLIFIER,
ADC_MUX_IDLE1,
ADC_MUX_MASK = 0x3,
};
static const char * const adc_left_mux_map[] = {
"Idle", "AIN0", "Left Preamplifier", "Idle_1"
};
static int adc_mux_map_value[] = {
ADC_MUX_IDLE,
ADC_MUX_AIN0,
ADC_MUX_PREAMPLIFIER,
ADC_MUX_IDLE1,
};
static SOC_VALUE_ENUM_SINGLE_DECL(adc_left_mux_map_enum,
SND_SOC_NOPM,
0,
ADC_MUX_MASK,
adc_left_mux_map,
adc_mux_map_value);
static const struct snd_kcontrol_new adc_left_mux_control =
SOC_DAPM_ENUM("ADC L Select", adc_left_mux_map_enum);
/* ADC R MUX */
static const char * const adc_right_mux_map[] = {
"Idle", "AIN0", "Right Preamplifier", "Idle_1"
};
static SOC_VALUE_ENUM_SINGLE_DECL(adc_right_mux_map_enum,
SND_SOC_NOPM,
0,
ADC_MUX_MASK,
adc_right_mux_map,
adc_mux_map_value);
static const struct snd_kcontrol_new adc_right_mux_control =
SOC_DAPM_ENUM("ADC R Select", adc_right_mux_map_enum);
/* PGA L MUX */
enum {
PGA_MUX_NONE = 0,
PGA_MUX_AIN0,
PGA_MUX_AIN1,
PGA_MUX_AIN2,
PGA_MUX_MASK = 0x3,
};
static const char * const pga_mux_map[] = {
"None", "AIN0", "AIN1", "AIN2"
};
static int pga_mux_map_value[] = {
PGA_MUX_NONE,
PGA_MUX_AIN0,
PGA_MUX_AIN1,
PGA_MUX_AIN2,
};
static SOC_VALUE_ENUM_SINGLE_DECL(pga_left_mux_map_enum,
SND_SOC_NOPM,
0,
PGA_MUX_MASK,
pga_mux_map,
pga_mux_map_value);
static const struct snd_kcontrol_new pga_left_mux_control =
SOC_DAPM_ENUM("PGA L Select", pga_left_mux_map_enum);
/* PGA R MUX */
static SOC_VALUE_ENUM_SINGLE_DECL(pga_right_mux_map_enum,
SND_SOC_NOPM,
0,
PGA_MUX_MASK,
pga_mux_map,
pga_mux_map_value);
static const struct snd_kcontrol_new pga_right_mux_control =
SOC_DAPM_ENUM("PGA R Select", pga_right_mux_map_enum);
static int mt_clksq_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* audio clk source from internal dcxo */
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6,
RG_CLKSQ_IN_SEL_TEST_MASK_SFT,
0x0);
break;
default:
break;
}
return 0;
}
static int mt_sgen_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* sdm audio fifo clock power on */
regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006);
/* scrambler clock on enable */
regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1);
/* sdm power on */
regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003);
/* sdm fifo enable */
regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B);
regmap_update_bits(priv->regmap, MT6358_AFE_SGEN_CFG0,
0xff3f,
0x0000);
regmap_update_bits(priv->regmap, MT6358_AFE_SGEN_CFG1,
0xffff,
0x0001);
break;
case SND_SOC_DAPM_POST_PMD:
/* DL scrambler disabling sequence */
regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000);
regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0);
break;
default:
break;
}
return 0;
}
static int mt_aif_in_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
dev_info(priv->dev, "%s(), event 0x%x, rate %d\n",
__func__, event, priv->dl_rate);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
playback_gpio_set(priv);
/* sdm audio fifo clock power on */
regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006);
/* scrambler clock on enable */
regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1);
/* sdm power on */
regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003);
/* sdm fifo enable */
regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B);
break;
case SND_SOC_DAPM_POST_PMD:
/* DL scrambler disabling sequence */
regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000);
regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0);
playback_gpio_reset(priv);
break;
default:
break;
}
return 0;
}
static int mtk_hp_enable(struct mt6358_priv *priv)
{
/* Pull-down HPL/R to AVSS28_AUD */
hp_pull_down(priv, true);
/* release HP CMFB gate rstb */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
0x1 << 6, 0x1 << 6);
/* Reduce ESD resistance of AU_REFN */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000);
/* Set HPR/HPL gain as minimum (~ -40dB) */
regmap_write(priv->regmap, MT6358_ZCD_CON2, DL_GAIN_N_40DB_REG);
/* Turn on DA_600K_NCP_VA18 */
regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001);
/* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c);
/* Toggle RG_DIVCKS_CHG */
regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001);
/* Set NCP soft start mode as default mode: 100us */
regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003);
/* Enable NCP */
regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000);
usleep_range(250, 270);
/* Enable cap-less LDOs (1.5V) */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
0x1055, 0x1055);
/* Enable NV regulator (-1.2V) */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001);
usleep_range(100, 120);
/* Disable AUD_ZCD */
hp_zcd_disable(priv);
/* Disable headphone short-circuit protection */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000);
/* Enable IBIST */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
/* Set HP DR bias current optimization, 010: 6uA */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900);
/* Set HP & ZCD bias current optimization */
/* 01: ZCD: 4uA, HP/HS/LO: 5uA */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
/* Set HPP/N STB enhance circuits */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033);
/* Enable HP aux output stage */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x000c);
/* Enable HP aux feedback loop */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x003c);
/* Enable HP aux CMFB loop */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00);
/* Enable HP driver bias circuits */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0);
/* Enable HP driver core circuits */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0);
/* Short HP main output to HP aux output stage */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00fc);
/* Enable HP main CMFB loop */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00);
/* Disable HP aux CMFB loop */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200);
/* Select CMFB resistor bulk to AC mode */
/* Selec HS/LO cap size (6.5pF default) */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000);
/* Enable HP main output stage */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00ff);
/* Enable HPR/L main output stage step by step */
hp_main_output_ramp(priv, true);
/* Reduce HP aux feedback loop gain */
hp_aux_feedback_loop_gain_ramp(priv, true);
/* Disable HP aux feedback loop */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf);
/* apply volume setting */
headset_volume_ramp(priv,
DL_GAIN_N_10DB,
priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]);
/* Disable HP aux output stage */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3);
/* Unshort HP main output to HP aux output stage */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3f03);
usleep_range(100, 120);
/* Enable AUD_CLK */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1);
/* Enable Audio DAC */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30ff);
/* Enable low-noise mode of DAC */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0xf201);
usleep_range(100, 120);
/* Switch HPL MUX to audio DAC */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x32ff);
/* Switch HPR MUX to audio DAC */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3aff);
/* Disable Pull-down HPL/R to AVSS28_AUD */
hp_pull_down(priv, false);
return 0;
}
static int mtk_hp_disable(struct mt6358_priv *priv)
{
/* Pull-down HPL/R to AVSS28_AUD */
hp_pull_down(priv, true);
/* HPR/HPL mux to open */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
0x0f00, 0x0000);
/* Disable low-noise mode of DAC */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
0x0001, 0x0000);
/* Disable Audio DAC */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
0x000f, 0x0000);
/* Disable AUD_CLK */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0);
/* Short HP main output to HP aux output stage */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3);
/* Enable HP aux output stage */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf);
/* decrease HPL/R gain to normal gain step by step */
headset_volume_ramp(priv,
priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL],
DL_GAIN_N_40DB);
/* Enable HP aux feedback loop */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff);
/* Reduce HP aux feedback loop gain */
hp_aux_feedback_loop_gain_ramp(priv, false);
/* decrease HPR/L main output stage step by step */
hp_main_output_ramp(priv, false);
/* Disable HP main output stage */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0);
/* Enable HP aux CMFB loop */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00);
/* Disable HP main CMFB loop */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00);
/* Unshort HP main output to HP aux output stage */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
0x3 << 6, 0x0);
/* Disable HP driver core circuits */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
0x3 << 4, 0x0);
/* Disable HP driver bias circuits */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
0x3 << 6, 0x0);
/* Disable HP aux CMFB loop */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000);
/* Disable HP aux feedback loop */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
0x3 << 4, 0x0);
/* Disable HP aux output stage */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
0x3 << 2, 0x0);
/* Disable IBIST */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12,
0x1 << 8, 0x1 << 8);
/* Disable NV regulator (-1.2V) */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0);
/* Disable cap-less LDOs (1.5V) */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
0x1055, 0x0);
/* Disable NCP */
regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3,
0x1, 0x1);
/* Increase ESD resistance of AU_REFN */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON2,
0x1 << 14, 0x0);
/* Set HP CMFB gate rstb */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
0x1 << 6, 0x0);
/* disable Pull-down HPL/R to AVSS28_AUD */
hp_pull_down(priv, false);
return 0;
}
static int mtk_hp_spk_enable(struct mt6358_priv *priv)
{
/* Pull-down HPL/R to AVSS28_AUD */
hp_pull_down(priv, true);
/* release HP CMFB gate rstb */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
0x1 << 6, 0x1 << 6);
/* Reduce ESD resistance of AU_REFN */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000);
/* Set HPR/HPL gain to -10dB */
regmap_write(priv->regmap, MT6358_ZCD_CON2, DL_GAIN_N_10DB_REG);
/* Turn on DA_600K_NCP_VA18 */
regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001);
/* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c);
/* Toggle RG_DIVCKS_CHG */
regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001);
/* Set NCP soft start mode as default mode: 100us */
regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003);
/* Enable NCP */
regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000);
usleep_range(250, 270);
/* Enable cap-less LDOs (1.5V) */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
0x1055, 0x1055);
/* Enable NV regulator (-1.2V) */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001);
usleep_range(100, 120);
/* Disable AUD_ZCD */
hp_zcd_disable(priv);
/* Disable headphone short-circuit protection */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000);
/* Enable IBIST */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
/* Set HP DR bias current optimization, 010: 6uA */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900);
/* Set HP & ZCD bias current optimization */
/* 01: ZCD: 4uA, HP/HS/LO: 5uA */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
/* Set HPP/N STB enhance circuits */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033);
/* Disable Pull-down HPL/R to AVSS28_AUD */
hp_pull_down(priv, false);
/* Enable HP driver bias circuits */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0);
/* Enable HP driver core circuits */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0);
/* Enable HP main CMFB loop */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200);
/* Select CMFB resistor bulk to AC mode */
/* Selec HS/LO cap size (6.5pF default) */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000);
/* Enable HP main output stage */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x0003);
/* Enable HPR/L main output stage step by step */
hp_main_output_ramp(priv, true);
/* Set LO gain as minimum (~ -40dB) */
regmap_write(priv->regmap, MT6358_ZCD_CON1, DL_GAIN_N_40DB_REG);
/* apply volume setting */
headset_volume_ramp(priv,
DL_GAIN_N_10DB,
priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]);
/* Set LO STB enhance circuits */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0110);
/* Enable LO driver bias circuits */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0112);
/* Enable LO driver core circuits */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0113);
/* Set LOL gain to normal gain step by step */
regmap_update_bits(priv->regmap, MT6358_ZCD_CON1,
RG_AUDLOLGAIN_MASK_SFT,
priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] <<
RG_AUDLOLGAIN_SFT);
regmap_update_bits(priv->regmap, MT6358_ZCD_CON1,
RG_AUDLORGAIN_MASK_SFT,
priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] <<
RG_AUDLORGAIN_SFT);
/* Enable AUD_CLK */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1);
/* Enable Audio DAC */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f9);
/* Enable low-noise mode of DAC */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0201);
/* Switch LOL MUX to audio DAC */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x011b);
/* Switch HPL/R MUX to Line-out */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x35f9);
return 0;
}
static int mtk_hp_spk_disable(struct mt6358_priv *priv)
{
/* HPR/HPL mux to open */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
0x0f00, 0x0000);
/* LOL mux to open */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
0x3 << 2, 0x0000);
/* Disable Audio DAC */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
0x000f, 0x0000);
/* Disable AUD_CLK */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0);
/* decrease HPL/R gain to normal gain step by step */
headset_volume_ramp(priv,
priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL],
DL_GAIN_N_40DB);
/* decrease LOL gain to minimum gain step by step */
regmap_update_bits(priv->regmap, MT6358_ZCD_CON1,
DL_GAIN_REG_MASK, DL_GAIN_N_40DB_REG);
/* decrease HPR/L main output stage step by step */
hp_main_output_ramp(priv, false);
/* Disable HP main output stage */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0);
/* Short HP main output to HP aux output stage */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3);
/* Enable HP aux output stage */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf);
/* Enable HP aux feedback loop */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff);
/* Reduce HP aux feedback loop gain */
hp_aux_feedback_loop_gain_ramp(priv, false);
/* Disable HP driver core circuits */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
0x3 << 4, 0x0);
/* Disable LO driver core circuits */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
0x1, 0x0);
/* Disable HP driver bias circuits */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
0x3 << 6, 0x0);
/* Disable LO driver bias circuits */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
0x1 << 1, 0x0);
/* Disable HP aux CMFB loop */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
0xff << 8, 0x0000);
/* Disable IBIST */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12,
0x1 << 8, 0x1 << 8);
/* Disable NV regulator (-1.2V) */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0);
/* Disable cap-less LDOs (1.5V) */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 0x1055, 0x0);
/* Disable NCP */
regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x1, 0x1);
/* Set HP CMFB gate rstb */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
0x1 << 6, 0x0);
/* disable Pull-down HPL/R to AVSS28_AUD */
hp_pull_down(priv, false);
return 0;
}
static int mt_hp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
int device = DEVICE_HP;
dev_info(priv->dev, "%s(), event 0x%x, dev_counter[DEV_HP] %d, mux %u\n",
__func__,
event,
priv->dev_counter[device],
mux);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
priv->dev_counter[device]++;
if (priv->dev_counter[device] > 1)
break; /* already enabled, do nothing */
else if (priv->dev_counter[device] <= 0)
dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d <= 0\n",
__func__,
priv->dev_counter[device]);
priv->mux_select[MUX_HP_L] = mux;
if (mux == HP_MUX_HP)
mtk_hp_enable(priv);
else if (mux == HP_MUX_HPSPK)
mtk_hp_spk_enable(priv);
break;
case SND_SOC_DAPM_PRE_PMD:
priv->dev_counter[device]--;
if (priv->dev_counter[device] > 0) {
break; /* still being used, don't close */
} else if (priv->dev_counter[device] < 0) {
dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d < 0\n",
__func__,
priv->dev_counter[device]);
priv->dev_counter[device] = 0;
break;
}
if (priv->mux_select[MUX_HP_L] == HP_MUX_HP)
mtk_hp_disable(priv);
else if (priv->mux_select[MUX_HP_L] == HP_MUX_HPSPK)
mtk_hp_spk_disable(priv);
priv->mux_select[MUX_HP_L] = mux;
break;
default:
break;
}
return 0;
}
static int mt_rcv_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
dev_info(priv->dev, "%s(), event 0x%x, mux %u\n",
__func__,
event,
dapm_kcontrol_get_value(w->kcontrols[0]));
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* Reduce ESD resistance of AU_REFN */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000);
/* Turn on DA_600K_NCP_VA18 */
regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001);
/* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c);
/* Toggle RG_DIVCKS_CHG */
regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001);
/* Set NCP soft start mode as default mode: 100us */
regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003);
/* Enable NCP */
regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000);
usleep_range(250, 270);
/* Enable cap-less LDOs (1.5V) */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
0x1055, 0x1055);
/* Enable NV regulator (-1.2V) */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001);
usleep_range(100, 120);
/* Disable AUD_ZCD */
hp_zcd_disable(priv);
/* Disable handset short-circuit protection */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0010);
/* Enable IBIST */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
/* Set HP DR bias current optimization, 010: 6uA */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900);
/* Set HP & ZCD bias current optimization */
/* 01: ZCD: 4uA, HP/HS/LO: 5uA */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
/* Set HS STB enhance circuits */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0090);
/* Disable HP main CMFB loop */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000);
/* Select CMFB resistor bulk to AC mode */
/* Selec HS/LO cap size (6.5pF default) */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000);
/* Enable HS driver bias circuits */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0092);
/* Enable HS driver core circuits */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0093);
/* Enable AUD_CLK */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
0x1, 0x1);
/* Enable Audio DAC */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x0009);
/* Enable low-noise mode of DAC */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0001);
/* Switch HS MUX to audio DAC */
regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x009b);
break;
case SND_SOC_DAPM_PRE_PMD:
/* HS mux to open */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
RG_AUDHSMUXINPUTSEL_VAUDP15_MASK_SFT,
RCV_MUX_OPEN);
/* Disable Audio DAC */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
0x000f, 0x0000);
/* Disable AUD_CLK */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
0x1, 0x0);
/* decrease HS gain to minimum gain step by step */
regmap_write(priv->regmap, MT6358_ZCD_CON3, DL_GAIN_N_40DB);
/* Disable HS driver core circuits */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
0x1, 0x0);
/* Disable HS driver bias circuits */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
0x1 << 1, 0x0000);
/* Disable HP aux CMFB loop */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
0xff << 8, 0x0);
/* Enable HP main CMFB Switch */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
0xff << 8, 0x2 << 8);
/* Disable IBIST */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12,
0x1 << 8, 0x1 << 8);
/* Disable NV regulator (-1.2V) */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15,
0x1, 0x0);
/* Disable cap-less LDOs (1.5V) */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
0x1055, 0x0);
/* Disable NCP */
regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3,
0x1, 0x1);
break;
default:
break;
}
return 0;
}
static int mt_aif_out_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n",
__func__, event, priv->ul_rate);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
capture_gpio_set(priv);
break;
case SND_SOC_DAPM_POST_PMD:
capture_gpio_reset(priv);
break;
default:
break;
}
return 0;
}
static int mt_adc_supply_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
dev_dbg(priv->dev, "%s(), event 0x%x\n",
__func__, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* Enable audio ADC CLKGEN */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
0x1 << 5, 0x1 << 5);
/* ADC CLK from CLKGEN (13MHz) */
regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3,
0x0000);
/* Enable LCLDO_ENC 1P8V */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
0x2500, 0x0100);
/* LCLDO_ENC remote sense */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
0x2500, 0x2500);
break;
case SND_SOC_DAPM_POST_PMD:
/* LCLDO_ENC remote sense off */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
0x2500, 0x0100);
/* disable LCLDO_ENC 1P8V */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
0x2500, 0x0000);
/* ADC CLK from CLKGEN (13MHz) */
regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3, 0x0000);
/* disable audio ADC CLKGEN */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
0x1 << 5, 0x0 << 5);
break;
default:
break;
}
return 0;
}
static int mt6358_amic_enable(struct mt6358_priv *priv)
{
unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE];
unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L];
unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R];
dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u\n",
__func__, mic_type, mux_pga_l, mux_pga_r);
if (IS_DCC_BASE(mic_type)) {
/* DCC 50k CLK (from 26M) */
regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060);
regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2061);
regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG1, 0x0100);
}
/* mic bias 0 */
if (mux_pga_l == PGA_MUX_AIN0 || mux_pga_l == PGA_MUX_AIN2 ||
mux_pga_r == PGA_MUX_AIN0 || mux_pga_r == PGA_MUX_AIN2) {
switch (mic_type) {
case MIC_TYPE_MUX_DCC_ECM_DIFF:
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
0xff00, 0x7700);
break;
case MIC_TYPE_MUX_DCC_ECM_SINGLE:
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
0xff00, 0x1100);
break;
default:
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
0xff00, 0x0000);
break;
}
/* Enable MICBIAS0, MISBIAS0 = 1P9V */
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
0xff, 0x21);
}
/* mic bias 1 */
if (mux_pga_l == PGA_MUX_AIN1 || mux_pga_r == PGA_MUX_AIN1) {
/* Enable MICBIAS1, MISBIAS1 = 2P6V */
if (mic_type == MIC_TYPE_MUX_DCC_ECM_SINGLE)
regmap_write(priv->regmap,
MT6358_AUDENC_ANA_CON10, 0x0161);
else
regmap_write(priv->regmap,
MT6358_AUDENC_ANA_CON10, 0x0061);
}
if (IS_DCC_BASE(mic_type)) {
/* Audio L/R preamplifier DCC precharge */
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
0xf8ff, 0x0004);
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
0xf8ff, 0x0004);
} else {
/* reset reg */
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
0xf8ff, 0x0000);
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
0xf8ff, 0x0000);
}
if (mux_pga_l != PGA_MUX_NONE) {
/* L preamplifier input sel */
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
RG_AUDPREAMPLINPUTSEL_MASK_SFT,
mux_pga_l << RG_AUDPREAMPLINPUTSEL_SFT);
/* L preamplifier enable */
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
RG_AUDPREAMPLON_MASK_SFT,
0x1 << RG_AUDPREAMPLON_SFT);
if (IS_DCC_BASE(mic_type)) {
/* L preamplifier DCCEN */
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
RG_AUDPREAMPLDCCEN_MASK_SFT,
0x1 << RG_AUDPREAMPLDCCEN_SFT);
}
/* L ADC input sel : L PGA. Enable audio L ADC */
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
RG_AUDADCLINPUTSEL_MASK_SFT,
ADC_MUX_PREAMPLIFIER <<
RG_AUDADCLINPUTSEL_SFT);
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
RG_AUDADCLPWRUP_MASK_SFT,
0x1 << RG_AUDADCLPWRUP_SFT);
}
if (mux_pga_r != PGA_MUX_NONE) {
/* R preamplifier input sel */
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
RG_AUDPREAMPRINPUTSEL_MASK_SFT,
mux_pga_r << RG_AUDPREAMPRINPUTSEL_SFT);
/* R preamplifier enable */
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
RG_AUDPREAMPRON_MASK_SFT,
0x1 << RG_AUDPREAMPRON_SFT);
if (IS_DCC_BASE(mic_type)) {
/* R preamplifier DCCEN */
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
RG_AUDPREAMPRDCCEN_MASK_SFT,
0x1 << RG_AUDPREAMPRDCCEN_SFT);
}
/* R ADC input sel : R PGA. Enable audio R ADC */
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
RG_AUDADCRINPUTSEL_MASK_SFT,
ADC_MUX_PREAMPLIFIER <<
RG_AUDADCRINPUTSEL_SFT);
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
RG_AUDADCRPWRUP_MASK_SFT,
0x1 << RG_AUDADCRPWRUP_SFT);
}
if (IS_DCC_BASE(mic_type)) {
usleep_range(100, 150);
/* Audio L preamplifier DCC precharge off */
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
RG_AUDPREAMPLDCPRECHARGE_MASK_SFT, 0x0);
/* Audio R preamplifier DCC precharge off */
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
RG_AUDPREAMPRDCPRECHARGE_MASK_SFT, 0x0);
/* Short body to ground in PGA */
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON3,
0x1 << 12, 0x0);
}
/* here to set digital part */
mt6358_mtkaif_tx_enable(priv);
/* UL dmic setting off */
regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0000);
/* UL turn on */
regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0001);
return 0;
}
static void mt6358_amic_disable(struct mt6358_priv *priv)
{
unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE];
unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L];
unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R];
dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u\n",
__func__, mic_type, mux_pga_l, mux_pga_r);
/* UL turn off */
regmap_update_bits(priv->regmap, MT6358_AFE_UL_SRC_CON0_L,
0x0001, 0x0000);
/* disable aud_pad TX fifos */
mt6358_mtkaif_tx_disable(priv);
/* L ADC input sel : off, disable L ADC */
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
0xf000, 0x0000);
/* L preamplifier DCCEN */
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
0x1 << 1, 0x0);
/* L preamplifier input sel : off, L PGA 0 dB gain */
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
0xfffb, 0x0000);
/* disable L preamplifier DCC precharge */
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
0x1 << 2, 0x0);
/* R ADC input sel : off, disable R ADC */
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
0xf000, 0x0000);
/* R preamplifier DCCEN */
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
0x1 << 1, 0x0);
/* R preamplifier input sel : off, R PGA 0 dB gain */
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
0x0ffb, 0x0000);
/* disable R preamplifier DCC precharge */
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
0x1 << 2, 0x0);
/* mic bias */
/* Disable MICBIAS0, MISBIAS0 = 1P7V */
regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000);
/* Disable MICBIAS1 */
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10,
0x0001, 0x0000);
if (IS_DCC_BASE(mic_type)) {
/* dcclk_gen_on=1'b0 */
regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060);
/* dcclk_pdn=1'b1 */
regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
/* dcclk_ref_ck_sel=2'b00 */
regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
/* dcclk_div=11'b00100000011 */
regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
}
}
static int mt6358_dmic_enable(struct mt6358_priv *priv)
{
dev_info(priv->dev, "%s()\n", __func__);
/* mic bias */
/* Enable MICBIAS0, MISBIAS0 = 1P9V */
regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0021);
/* RG_BANDGAPGEN=1'b0 */
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10,
0x1 << 12, 0x0);
/* DMIC enable */
regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0005);
/* here to set digital part */
mt6358_mtkaif_tx_enable(priv);
/* UL dmic setting */
if (priv->dmic_one_wire_mode)
regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0400);
else
regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0080);
/* UL turn on */
regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0003);
/* Prevent pop noise form dmic hw */
msleep(100);
return 0;
}
static void mt6358_dmic_disable(struct mt6358_priv *priv)
{
dev_info(priv->dev, "%s()\n", __func__);
/* UL turn off */
regmap_update_bits(priv->regmap, MT6358_AFE_UL_SRC_CON0_L,
0x0003, 0x0000);
/* disable aud_pad TX fifos */
mt6358_mtkaif_tx_disable(priv);
/* DMIC disable */
regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0000);
/* mic bias */
/* MISBIAS0 = 1P7V */
regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0001);
/* RG_BANDGAPGEN=1'b0 */
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10,
0x1 << 12, 0x0);
/* MICBIA0 disable */
regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000);
}
static void mt6358_restore_pga(struct mt6358_priv *priv)
{
unsigned int gain_l, gain_r;
gain_l = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1];
gain_r = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2];
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
RG_AUDPREAMPLGAIN_MASK_SFT,
gain_l << RG_AUDPREAMPLGAIN_SFT);
regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
RG_AUDPREAMPRGAIN_MASK_SFT,
gain_r << RG_AUDPREAMPRGAIN_SFT);
}
static int mt_mic_type_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n",
__func__, event, mux);
switch (event) {
case SND_SOC_DAPM_WILL_PMU:
priv->mux_select[MUX_MIC_TYPE] = mux;
break;
case SND_SOC_DAPM_PRE_PMU:
switch (mux) {
case MIC_TYPE_MUX_DMIC:
mt6358_dmic_enable(priv);
break;
default:
mt6358_amic_enable(priv);
break;
}
mt6358_restore_pga(priv);
break;
case SND_SOC_DAPM_POST_PMD:
switch (priv->mux_select[MUX_MIC_TYPE]) {
case MIC_TYPE_MUX_DMIC:
mt6358_dmic_disable(priv);
break;
default:
mt6358_amic_disable(priv);
break;
}
priv->mux_select[MUX_MIC_TYPE] = mux;
break;
default:
break;
}
return 0;
}
static int mt_adc_l_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
__func__, event, mux);
priv->mux_select[MUX_ADC_L] = mux;
return 0;
}
static int mt_adc_r_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
__func__, event, mux);
priv->mux_select[MUX_ADC_R] = mux;
return 0;
}
static int mt_pga_left_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
__func__, event, mux);
priv->mux_select[MUX_PGA_L] = mux;
return 0;
}
static int mt_pga_right_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
__func__, event, mux);
priv->mux_select[MUX_PGA_R] = mux;
return 0;
}
static int mt_delay_250_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
switch (event) {
case SND_SOC_DAPM_POST_PMU:
usleep_range(250, 270);
break;
case SND_SOC_DAPM_PRE_PMD:
usleep_range(250, 270);
break;
default:
break;
}
return 0;
}
/* DAPM Widgets */
static const struct snd_soc_dapm_widget mt6358_dapm_widgets[] = {
/* Global Supply*/
SND_SOC_DAPM_SUPPLY_S("CLK_BUF", SUPPLY_SEQ_CLK_BUF,
MT6358_DCXO_CW14,
RG_XO_AUDIO_EN_M_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("AUDGLB", SUPPLY_SEQ_AUD_GLB,
MT6358_AUDDEC_ANA_CON13,
RG_AUDGLB_PWRDN_VA28_SFT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("CLKSQ Audio", SUPPLY_SEQ_CLKSQ,
MT6358_AUDENC_ANA_CON6,
RG_CLKSQ_EN_SFT, 0,
mt_clksq_event,
SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_SUPPLY_S("AUDNCP_CK", SUPPLY_SEQ_TOP_CK,
MT6358_AUD_TOP_CKPDN_CON0,
RG_AUDNCP_CK_PDN_SFT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ZCD13M_CK", SUPPLY_SEQ_TOP_CK,
MT6358_AUD_TOP_CKPDN_CON0,
RG_ZCD13M_CK_PDN_SFT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("AUD_CK", SUPPLY_SEQ_TOP_CK_LAST,
MT6358_AUD_TOP_CKPDN_CON0,
RG_AUD_CK_PDN_SFT, 1,
mt_delay_250_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SUPPLY_S("AUDIF_CK", SUPPLY_SEQ_TOP_CK,
MT6358_AUD_TOP_CKPDN_CON0,
RG_AUDIF_CK_PDN_SFT, 1, NULL, 0),
/* Digital Clock */
SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_AFE_CTL", SUPPLY_SEQ_AUD_TOP_LAST,
MT6358_AUDIO_TOP_CON0,
PDN_AFE_CTL_SFT, 1,
mt_delay_250_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_DAC_CTL", SUPPLY_SEQ_AUD_TOP,
MT6358_AUDIO_TOP_CON0,
PDN_DAC_CTL_SFT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_ADC_CTL", SUPPLY_SEQ_AUD_TOP,
MT6358_AUDIO_TOP_CON0,
PDN_ADC_CTL_SFT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_I2S_DL", SUPPLY_SEQ_AUD_TOP,
MT6358_AUDIO_TOP_CON0,
PDN_I2S_DL_CTL_SFT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PWR_CLK", SUPPLY_SEQ_AUD_TOP,
MT6358_AUDIO_TOP_CON0,
PWR_CLK_DIS_CTL_SFT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_AFE_TESTMODEL", SUPPLY_SEQ_AUD_TOP,
MT6358_AUDIO_TOP_CON0,
PDN_AFE_TESTMODEL_CTL_SFT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_RESERVED", SUPPLY_SEQ_AUD_TOP,
MT6358_AUDIO_TOP_CON0,
PDN_RESERVED_SFT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("DL Digital Clock", SND_SOC_NOPM,
0, 0, NULL, 0),
/* AFE ON */
SND_SOC_DAPM_SUPPLY_S("AFE_ON", SUPPLY_SEQ_AFE,
MT6358_AFE_UL_DL_CON0, AFE_ON_SFT, 0,
NULL, 0),
/* AIF Rx*/
SND_SOC_DAPM_AIF_IN_E("AIF_RX", "AIF1 Playback", 0,
MT6358_AFE_DL_SRC2_CON0_L,
DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
mt_aif_in_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
/* DL Supply */
SND_SOC_DAPM_SUPPLY("DL Power Supply", SND_SOC_NOPM,
0, 0, NULL, 0),
/* DAC */
SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control),
SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),
/* LOL */
SND_SOC_DAPM_MUX("LOL Mux", SND_SOC_NOPM, 0, 0, &lo_in_mux_control),
SND_SOC_DAPM_SUPPLY("LO Stability Enh", MT6358_AUDDEC_ANA_CON7,
RG_LOOUTPUTSTBENH_VAUDP15_SFT, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("LOL Buffer", MT6358_AUDDEC_ANA_CON7,
RG_AUDLOLPWRUP_VAUDP15_SFT, 0, NULL, 0),
/* Headphone */
SND_SOC_DAPM_MUX_E("HPL Mux", SND_SOC_NOPM, 0, 0,
&hpl_in_mux_control,
mt_hp_event,
SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_MUX_E("HPR Mux", SND_SOC_NOPM, 0, 0,
&hpr_in_mux_control,
mt_hp_event,
SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_PRE_PMD),
/* Receiver */
SND_SOC_DAPM_MUX_E("RCV Mux", SND_SOC_NOPM, 0, 0,
&rcv_in_mux_control,
mt_rcv_event,
SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_PRE_PMD),
/* Outputs */
SND_SOC_DAPM_OUTPUT("Receiver"),
SND_SOC_DAPM_OUTPUT("Headphone L"),
SND_SOC_DAPM_OUTPUT("Headphone R"),
SND_SOC_DAPM_OUTPUT("Headphone L Ext Spk Amp"),
SND_SOC_DAPM_OUTPUT("Headphone R Ext Spk Amp"),
SND_SOC_DAPM_OUTPUT("LINEOUT L"),
SND_SOC_DAPM_OUTPUT("LINEOUT L HSSPK"),
/* SGEN */
SND_SOC_DAPM_SUPPLY("SGEN DL Enable", MT6358_AFE_SGEN_CFG0,
SGEN_DAC_EN_CTL_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("SGEN MUTE", MT6358_AFE_SGEN_CFG0,
SGEN_MUTE_SW_CTL_SFT, 1,
mt_sgen_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("SGEN DL SRC", MT6358_AFE_DL_SRC2_CON0_L,
DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, NULL, 0),
SND_SOC_DAPM_INPUT("SGEN DL"),
/* Uplinks */
SND_SOC_DAPM_AIF_OUT_E("AIF1TX", "AIF1 Capture", 0,
SND_SOC_NOPM, 0, 0,
mt_aif_out_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("ADC Supply", SUPPLY_SEQ_ADC_SUPPLY,
SND_SOC_NOPM, 0, 0,
mt_adc_supply_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
/* Uplinks MUX */
SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0,
&aif_out_mux_control),
SND_SOC_DAPM_MUX_E("Mic Type Mux", SND_SOC_NOPM, 0, 0,
&mic_type_mux_control,
mt_mic_type_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_WILL_PMU),
SND_SOC_DAPM_MUX_E("ADC L Mux", SND_SOC_NOPM, 0, 0,
&adc_left_mux_control,
mt_adc_l_event,
SND_SOC_DAPM_WILL_PMU),
SND_SOC_DAPM_MUX_E("ADC R Mux", SND_SOC_NOPM, 0, 0,
&adc_right_mux_control,
mt_adc_r_event,
SND_SOC_DAPM_WILL_PMU),
SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_MUX_E("PGA L Mux", SND_SOC_NOPM, 0, 0,
&pga_left_mux_control,
mt_pga_left_event,
SND_SOC_DAPM_WILL_PMU),
SND_SOC_DAPM_MUX_E("PGA R Mux", SND_SOC_NOPM, 0, 0,
&pga_right_mux_control,
mt_pga_right_event,
SND_SOC_DAPM_WILL_PMU),
SND_SOC_DAPM_PGA("PGA L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("PGA R", SND_SOC_NOPM, 0, 0, NULL, 0),
/* UL input */
SND_SOC_DAPM_INPUT("AIN0"),
SND_SOC_DAPM_INPUT("AIN1"),
SND_SOC_DAPM_INPUT("AIN2"),
};
static const struct snd_soc_dapm_route mt6358_dapm_routes[] = {
/* Capture */
{"AIF1TX", NULL, "AIF Out Mux"},
{"AIF1TX", NULL, "CLK_BUF"},
{"AIF1TX", NULL, "AUDGLB"},
{"AIF1TX", NULL, "CLKSQ Audio"},
{"AIF1TX", NULL, "AUD_CK"},
{"AIF1TX", NULL, "AUDIF_CK"},
{"AIF1TX", NULL, "AUDIO_TOP_AFE_CTL"},
{"AIF1TX", NULL, "AUDIO_TOP_ADC_CTL"},
{"AIF1TX", NULL, "AUDIO_TOP_PWR_CLK"},
{"AIF1TX", NULL, "AUDIO_TOP_PDN_RESERVED"},
{"AIF1TX", NULL, "AUDIO_TOP_I2S_DL"},
{"AIF1TX", NULL, "AFE_ON"},
{"AIF Out Mux", NULL, "Mic Type Mux"},
{"Mic Type Mux", "ACC", "ADC L"},
{"Mic Type Mux", "ACC", "ADC R"},
{"Mic Type Mux", "DCC", "ADC L"},
{"Mic Type Mux", "DCC", "ADC R"},
{"Mic Type Mux", "DCC_ECM_DIFF", "ADC L"},
{"Mic Type Mux", "DCC_ECM_DIFF", "ADC R"},
{"Mic Type Mux", "DCC_ECM_SINGLE", "ADC L"},
{"Mic Type Mux", "DCC_ECM_SINGLE", "ADC R"},
{"Mic Type Mux", "DMIC", "AIN0"},
{"Mic Type Mux", "DMIC", "AIN2"},
{"ADC L", NULL, "ADC L Mux"},
{"ADC L", NULL, "ADC Supply"},
{"ADC R", NULL, "ADC R Mux"},
{"ADC R", NULL, "ADC Supply"},
{"ADC L Mux", "Left Preamplifier", "PGA L"},
{"ADC R Mux", "Right Preamplifier", "PGA R"},
{"PGA L", NULL, "PGA L Mux"},
{"PGA R", NULL, "PGA R Mux"},
{"PGA L Mux", "AIN0", "AIN0"},
{"PGA L Mux", "AIN1", "AIN1"},
{"PGA L Mux", "AIN2", "AIN2"},
{"PGA R Mux", "AIN0", "AIN0"},
{"PGA R Mux", "AIN1", "AIN1"},
{"PGA R Mux", "AIN2", "AIN2"},
/* DL Supply */
{"DL Power Supply", NULL, "CLK_BUF"},
{"DL Power Supply", NULL, "AUDGLB"},
{"DL Power Supply", NULL, "CLKSQ Audio"},
{"DL Power Supply", NULL, "AUDNCP_CK"},
{"DL Power Supply", NULL, "ZCD13M_CK"},
{"DL Power Supply", NULL, "AUD_CK"},
{"DL Power Supply", NULL, "AUDIF_CK"},
/* DL Digital Supply */
{"DL Digital Clock", NULL, "AUDIO_TOP_AFE_CTL"},
{"DL Digital Clock", NULL, "AUDIO_TOP_DAC_CTL"},
{"DL Digital Clock", NULL, "AUDIO_TOP_PWR_CLK"},
{"DL Digital Clock", NULL, "AFE_ON"},
{"AIF_RX", NULL, "DL Digital Clock"},
/* DL Path */
{"DAC In Mux", "Normal Path", "AIF_RX"},
{"DAC In Mux", "Sgen", "SGEN DL"},
{"SGEN DL", NULL, "SGEN DL SRC"},
{"SGEN DL", NULL, "SGEN MUTE"},
{"SGEN DL", NULL, "SGEN DL Enable"},
{"SGEN DL", NULL, "DL Digital Clock"},
{"SGEN DL", NULL, "AUDIO_TOP_PDN_AFE_TESTMODEL"},
{"DACL", NULL, "DAC In Mux"},
{"DACL", NULL, "DL Power Supply"},
{"DACR", NULL, "DAC In Mux"},
{"DACR", NULL, "DL Power Supply"},
/* Lineout Path */
{"LOL Mux", "Playback", "DACL"},
{"LOL Buffer", NULL, "LOL Mux"},
{"LOL Buffer", NULL, "LO Stability Enh"},
{"LINEOUT L", NULL, "LOL Buffer"},
/* Headphone Path */
{"HPL Mux", "Audio Playback", "DACL"},
{"HPR Mux", "Audio Playback", "DACR"},
{"HPL Mux", "HP Impedance", "DACL"},
{"HPR Mux", "HP Impedance", "DACR"},
{"HPL Mux", "LoudSPK Playback", "DACL"},
{"HPR Mux", "LoudSPK Playback", "DACR"},
{"Headphone L", NULL, "HPL Mux"},
{"Headphone R", NULL, "HPR Mux"},
{"Headphone L Ext Spk Amp", NULL, "HPL Mux"},
{"Headphone R Ext Spk Amp", NULL, "HPR Mux"},
{"LINEOUT L HSSPK", NULL, "HPL Mux"},
/* Receiver Path */
{"RCV Mux", "Voice Playback", "DACL"},
{"Receiver", NULL, "RCV Mux"},
};
static int mt6358_codec_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *cmpnt = dai->component;
struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
unsigned int rate = params_rate(params);
dev_info(priv->dev, "%s(), substream->stream %d, rate %d, number %d\n",
__func__,
substream->stream,
rate,
substream->number);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
priv->dl_rate = rate;
else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
priv->ul_rate = rate;
return 0;
}
static const struct snd_soc_dai_ops mt6358_codec_dai_ops = {
.hw_params = mt6358_codec_dai_hw_params,
};
#define MT6358_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_U24_LE |\
SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_U32_LE)
static struct snd_soc_dai_driver mt6358_dai_driver[] = {
{
.name = "mt6358-snd-codec-aif1",
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000 |
SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = MT6358_FORMATS,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_32000 |
SNDRV_PCM_RATE_48000,
.formats = MT6358_FORMATS,
},
.ops = &mt6358_codec_dai_ops,
},
};
static void mt6358_codec_init_reg(struct mt6358_priv *priv)
{
/* Disable HeadphoneL/HeadphoneR short circuit protection */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
RG_AUDHPLSCDISABLE_VAUDP15_MASK_SFT,
0x1 << RG_AUDHPLSCDISABLE_VAUDP15_SFT);
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
RG_AUDHPRSCDISABLE_VAUDP15_MASK_SFT,
0x1 << RG_AUDHPRSCDISABLE_VAUDP15_SFT);
/* Disable voice short circuit protection */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
RG_AUDHSSCDISABLE_VAUDP15_MASK_SFT,
0x1 << RG_AUDHSSCDISABLE_VAUDP15_SFT);
/* disable LO buffer left short circuit protection */
regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
RG_AUDLOLSCDISABLE_VAUDP15_MASK_SFT,
0x1 << RG_AUDLOLSCDISABLE_VAUDP15_SFT);
/* accdet s/w enable */
regmap_update_bits(priv->regmap, MT6358_ACCDET_CON13,
0xFFFF, 0x700E);
/* gpio miso driving set to 4mA */
regmap_write(priv->regmap, MT6358_DRV_CON3, 0x8888);
/* set gpio */
playback_gpio_reset(priv);
capture_gpio_reset(priv);
}
static int mt6358_codec_probe(struct snd_soc_component *cmpnt)
{
struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
int ret;
snd_soc_component_init_regmap(cmpnt, priv->regmap);
mt6358_codec_init_reg(priv);
priv->avdd_reg = devm_regulator_get(priv->dev, "Avdd");
if (IS_ERR(priv->avdd_reg)) {
dev_err(priv->dev, "%s() have no Avdd supply", __func__);
return PTR_ERR(priv->avdd_reg);
}
ret = regulator_enable(priv->avdd_reg);
if (ret)
return ret;
return 0;
}
static const struct snd_soc_component_driver mt6358_soc_component_driver = {
.probe = mt6358_codec_probe,
.controls = mt6358_snd_controls,
.num_controls = ARRAY_SIZE(mt6358_snd_controls),
.dapm_widgets = mt6358_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(mt6358_dapm_widgets),
.dapm_routes = mt6358_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(mt6358_dapm_routes),
.endianness = 1,
};
static void mt6358_parse_dt(struct mt6358_priv *priv)
{
int ret;
struct device *dev = priv->dev;
ret = of_property_read_u32(dev->of_node, "mediatek,dmic-mode",
&priv->dmic_one_wire_mode);
if (ret) {
dev_warn(priv->dev, "%s() failed to read dmic-mode\n",
__func__);
priv->dmic_one_wire_mode = 0;
}
}
static int mt6358_platform_driver_probe(struct platform_device *pdev)
{
struct mt6358_priv *priv;
struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
priv = devm_kzalloc(&pdev->dev,
sizeof(struct mt6358_priv),
GFP_KERNEL);
if (!priv)
return -ENOMEM;
dev_set_drvdata(&pdev->dev, priv);
priv->dev = &pdev->dev;
priv->regmap = mt6397->regmap;
if (IS_ERR(priv->regmap))
return PTR_ERR(priv->regmap);
mt6358_parse_dt(priv);
dev_info(priv->dev, "%s(), dev name %s\n",
__func__, dev_name(&pdev->dev));
return devm_snd_soc_register_component(&pdev->dev,
&mt6358_soc_component_driver,
mt6358_dai_driver,
ARRAY_SIZE(mt6358_dai_driver));
}
static const struct of_device_id mt6358_of_match[] = {
{.compatible = "mediatek,mt6358-sound",},
{.compatible = "mediatek,mt6366-sound",},
{}
};
MODULE_DEVICE_TABLE(of, mt6358_of_match);
static struct platform_driver mt6358_platform_driver = {
.driver = {
.name = "mt6358-sound",
.of_match_table = mt6358_of_match,
},
.probe = mt6358_platform_driver_probe,
};
module_platform_driver(mt6358_platform_driver)
/* Module information */
MODULE_DESCRIPTION("MT6358 ALSA SoC codec driver");
MODULE_AUTHOR("KaiChieh Chuang <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/mt6358.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright(c) 2015-18 Intel Corporation.
/*
* hdac_hda.c - ASoC extensions to reuse the legacy HDA codec drivers
* with ASoC platform drivers. These APIs are called by the legacy HDA
* codec drivers using hdac_ext_bus_ops ops.
*/
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/hdaudio_ext.h>
#include <sound/hda_i915.h>
#include <sound/hda_codec.h>
#include <sound/hda_register.h>
#include "hdac_hda.h"
#define STUB_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_U8 | \
SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_U16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_U24_LE | \
SNDRV_PCM_FMTBIT_S32_LE | \
SNDRV_PCM_FMTBIT_U32_LE | \
SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE)
#define STUB_HDMI_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |\
SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
SNDRV_PCM_RATE_192000)
static int hdac_hda_dai_open(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai);
static void hdac_hda_dai_close(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai);
static int hdac_hda_dai_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai);
static int hdac_hda_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai);
static int hdac_hda_dai_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai);
static int hdac_hda_dai_set_stream(struct snd_soc_dai *dai, void *stream,
int direction);
static struct hda_pcm *snd_soc_find_pcm_from_dai(struct hdac_hda_priv *hda_pvt,
struct snd_soc_dai *dai);
static const struct snd_soc_dai_ops hdac_hda_dai_ops = {
.startup = hdac_hda_dai_open,
.shutdown = hdac_hda_dai_close,
.prepare = hdac_hda_dai_prepare,
.hw_params = hdac_hda_dai_hw_params,
.hw_free = hdac_hda_dai_hw_free,
.set_stream = hdac_hda_dai_set_stream,
};
static struct snd_soc_dai_driver hdac_hda_dais[] = {
{
.id = HDAC_ANALOG_DAI_ID,
.name = "Analog Codec DAI",
.ops = &hdac_hda_dai_ops,
.playback = {
.stream_name = "Analog Codec Playback",
.channels_min = 1,
.channels_max = 16,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = STUB_FORMATS,
.sig_bits = 24,
},
.capture = {
.stream_name = "Analog Codec Capture",
.channels_min = 1,
.channels_max = 16,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = STUB_FORMATS,
.sig_bits = 24,
},
},
{
.id = HDAC_DIGITAL_DAI_ID,
.name = "Digital Codec DAI",
.ops = &hdac_hda_dai_ops,
.playback = {
.stream_name = "Digital Codec Playback",
.channels_min = 1,
.channels_max = 16,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = STUB_FORMATS,
.sig_bits = 24,
},
.capture = {
.stream_name = "Digital Codec Capture",
.channels_min = 1,
.channels_max = 16,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = STUB_FORMATS,
.sig_bits = 24,
},
},
{
.id = HDAC_ALT_ANALOG_DAI_ID,
.name = "Alt Analog Codec DAI",
.ops = &hdac_hda_dai_ops,
.playback = {
.stream_name = "Alt Analog Codec Playback",
.channels_min = 1,
.channels_max = 16,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = STUB_FORMATS,
.sig_bits = 24,
},
.capture = {
.stream_name = "Alt Analog Codec Capture",
.channels_min = 1,
.channels_max = 16,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = STUB_FORMATS,
.sig_bits = 24,
},
},
{
.id = HDAC_HDMI_0_DAI_ID,
.name = "intel-hdmi-hifi1",
.ops = &hdac_hda_dai_ops,
.playback = {
.stream_name = "hifi1",
.channels_min = 1,
.channels_max = 32,
.rates = STUB_HDMI_RATES,
.formats = STUB_FORMATS,
.sig_bits = 24,
},
},
{
.id = HDAC_HDMI_1_DAI_ID,
.name = "intel-hdmi-hifi2",
.ops = &hdac_hda_dai_ops,
.playback = {
.stream_name = "hifi2",
.channels_min = 1,
.channels_max = 32,
.rates = STUB_HDMI_RATES,
.formats = STUB_FORMATS,
.sig_bits = 24,
},
},
{
.id = HDAC_HDMI_2_DAI_ID,
.name = "intel-hdmi-hifi3",
.ops = &hdac_hda_dai_ops,
.playback = {
.stream_name = "hifi3",
.channels_min = 1,
.channels_max = 32,
.rates = STUB_HDMI_RATES,
.formats = STUB_FORMATS,
.sig_bits = 24,
},
},
{
.id = HDAC_HDMI_3_DAI_ID,
.name = "intel-hdmi-hifi4",
.ops = &hdac_hda_dai_ops,
.playback = {
.stream_name = "hifi4",
.channels_min = 1,
.channels_max = 32,
.rates = STUB_HDMI_RATES,
.formats = STUB_FORMATS,
.sig_bits = 24,
},
},
};
static int hdac_hda_dai_set_stream(struct snd_soc_dai *dai,
void *stream, int direction)
{
struct snd_soc_component *component = dai->component;
struct hdac_hda_priv *hda_pvt;
struct hdac_hda_pcm *pcm;
struct hdac_stream *hstream;
if (!stream)
return -EINVAL;
hda_pvt = snd_soc_component_get_drvdata(component);
pcm = &hda_pvt->pcm[dai->id];
hstream = (struct hdac_stream *)stream;
pcm->stream_tag[direction] = hstream->stream_tag;
return 0;
}
static int hdac_hda_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct hdac_hda_priv *hda_pvt;
unsigned int format_val;
unsigned int maxbps;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
maxbps = dai->driver->playback.sig_bits;
else
maxbps = dai->driver->capture.sig_bits;
hda_pvt = snd_soc_component_get_drvdata(component);
format_val = snd_hdac_calc_stream_format(params_rate(params),
params_channels(params),
params_format(params),
maxbps,
0);
if (!format_val) {
dev_err(dai->dev,
"invalid format_val, rate=%d, ch=%d, format=%d, maxbps=%d\n",
params_rate(params), params_channels(params),
params_format(params), maxbps);
return -EINVAL;
}
hda_pvt->pcm[dai->id].format_val[substream->stream] = format_val;
return 0;
}
static int hdac_hda_dai_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct hdac_hda_priv *hda_pvt;
struct hda_pcm_stream *hda_stream;
struct hda_pcm *pcm;
hda_pvt = snd_soc_component_get_drvdata(component);
pcm = snd_soc_find_pcm_from_dai(hda_pvt, dai);
if (!pcm)
return -EINVAL;
hda_stream = &pcm->stream[substream->stream];
snd_hda_codec_cleanup(hda_pvt->codec, hda_stream, substream);
return 0;
}
static int hdac_hda_dai_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct hda_pcm_stream *hda_stream;
struct hdac_hda_priv *hda_pvt;
struct hdac_device *hdev;
unsigned int format_val;
struct hda_pcm *pcm;
unsigned int stream;
int ret = 0;
hda_pvt = snd_soc_component_get_drvdata(component);
hdev = &hda_pvt->codec->core;
pcm = snd_soc_find_pcm_from_dai(hda_pvt, dai);
if (!pcm)
return -EINVAL;
hda_stream = &pcm->stream[substream->stream];
stream = hda_pvt->pcm[dai->id].stream_tag[substream->stream];
format_val = hda_pvt->pcm[dai->id].format_val[substream->stream];
ret = snd_hda_codec_prepare(hda_pvt->codec, hda_stream,
stream, format_val, substream);
if (ret < 0)
dev_err(&hdev->dev, "codec prepare failed %d\n", ret);
return ret;
}
static int hdac_hda_dai_open(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct hdac_hda_priv *hda_pvt;
struct hda_pcm_stream *hda_stream;
struct hda_pcm *pcm;
hda_pvt = snd_soc_component_get_drvdata(component);
pcm = snd_soc_find_pcm_from_dai(hda_pvt, dai);
if (!pcm)
return -EINVAL;
snd_hda_codec_pcm_get(pcm);
hda_stream = &pcm->stream[substream->stream];
return hda_stream->ops.open(hda_stream, hda_pvt->codec, substream);
}
static void hdac_hda_dai_close(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct hdac_hda_priv *hda_pvt;
struct hda_pcm_stream *hda_stream;
struct hda_pcm *pcm;
hda_pvt = snd_soc_component_get_drvdata(component);
pcm = snd_soc_find_pcm_from_dai(hda_pvt, dai);
if (!pcm)
return;
hda_stream = &pcm->stream[substream->stream];
hda_stream->ops.close(hda_stream, hda_pvt->codec, substream);
snd_hda_codec_pcm_put(pcm);
}
static struct hda_pcm *snd_soc_find_pcm_from_dai(struct hdac_hda_priv *hda_pvt,
struct snd_soc_dai *dai)
{
struct hda_codec *hcodec = hda_pvt->codec;
struct hda_pcm *cpcm;
const char *pcm_name;
/*
* map DAI ID to the closest matching PCM name, using the naming
* scheme used by hda-codec snd_hda_gen_build_pcms() and for
* HDMI in hda_codec patch_hdmi.c)
*/
switch (dai->id) {
case HDAC_ANALOG_DAI_ID:
pcm_name = "Analog";
break;
case HDAC_DIGITAL_DAI_ID:
pcm_name = "Digital";
break;
case HDAC_ALT_ANALOG_DAI_ID:
pcm_name = "Alt Analog";
break;
case HDAC_HDMI_0_DAI_ID:
pcm_name = "HDMI 0";
break;
case HDAC_HDMI_1_DAI_ID:
pcm_name = "HDMI 1";
break;
case HDAC_HDMI_2_DAI_ID:
pcm_name = "HDMI 2";
break;
case HDAC_HDMI_3_DAI_ID:
pcm_name = "HDMI 3";
break;
default:
dev_err(&hcodec->core.dev, "invalid dai id %d\n", dai->id);
return NULL;
}
list_for_each_entry(cpcm, &hcodec->pcm_list_head, list) {
if (strstr(cpcm->name, pcm_name)) {
if (strcmp(pcm_name, "Analog") == 0) {
if (strstr(cpcm->name, "Alt Analog"))
continue;
}
return cpcm;
}
}
dev_err(&hcodec->core.dev, "didn't find PCM for DAI %s\n", dai->name);
return NULL;
}
static bool is_hdmi_codec(struct hda_codec *hcodec)
{
struct hda_pcm *cpcm;
list_for_each_entry(cpcm, &hcodec->pcm_list_head, list) {
if (cpcm->pcm_type == HDA_PCM_TYPE_HDMI)
return true;
}
return false;
}
static int hdac_hda_codec_probe(struct snd_soc_component *component)
{
struct hdac_hda_priv *hda_pvt =
snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm =
snd_soc_component_get_dapm(component);
struct hdac_device *hdev = &hda_pvt->codec->core;
struct hda_codec *hcodec = hda_pvt->codec;
struct hdac_ext_link *hlink;
hda_codec_patch_t patch;
int ret;
hlink = snd_hdac_ext_bus_get_hlink_by_name(hdev->bus, dev_name(&hdev->dev));
if (!hlink) {
dev_err(&hdev->dev, "hdac link not found\n");
return -EIO;
}
snd_hdac_ext_bus_link_get(hdev->bus, hlink);
/*
* Ensure any HDA display is powered at codec probe.
* After snd_hda_codec_device_new(), display power is
* managed by runtime PM.
*/
if (hda_pvt->need_display_power)
snd_hdac_display_power(hdev->bus,
HDA_CODEC_IDX_CONTROLLER, true);
ret = snd_hda_codec_device_new(hcodec->bus, component->card->snd_card,
hdev->addr, hcodec, true);
if (ret < 0) {
dev_err(&hdev->dev, "failed to create hda codec %d\n", ret);
goto error_no_pm;
}
/*
* Overwrite type to HDA_DEV_ASOC since it is a ASoC driver
* hda_codec.c will check this flag to determine if unregister
* device is needed.
*/
hdev->type = HDA_DEV_ASOC;
/*
* snd_hda_codec_device_new decrements the usage count so call get pm
* else the device will be powered off
*/
pm_runtime_get_noresume(&hdev->dev);
hcodec->bus->card = dapm->card->snd_card;
ret = snd_hda_codec_set_name(hcodec, hcodec->preset->name);
if (ret < 0) {
dev_err(&hdev->dev, "name failed %s\n", hcodec->preset->name);
goto error_pm;
}
ret = snd_hdac_regmap_init(&hcodec->core);
if (ret < 0) {
dev_err(&hdev->dev, "regmap init failed\n");
goto error_pm;
}
patch = (hda_codec_patch_t)hcodec->preset->driver_data;
if (patch) {
ret = patch(hcodec);
if (ret < 0) {
dev_err(&hdev->dev, "patch failed %d\n", ret);
goto error_regmap;
}
} else {
dev_dbg(&hdev->dev, "no patch file found\n");
}
ret = snd_hda_codec_parse_pcms(hcodec);
if (ret < 0) {
dev_err(&hdev->dev, "unable to map pcms to dai %d\n", ret);
goto error_patch;
}
/* HDMI controls need to be created in machine drivers */
if (!is_hdmi_codec(hcodec)) {
ret = snd_hda_codec_build_controls(hcodec);
if (ret < 0) {
dev_err(&hdev->dev, "unable to create controls %d\n",
ret);
goto error_patch;
}
}
hcodec->core.lazy_cache = true;
if (hda_pvt->need_display_power)
snd_hdac_display_power(hdev->bus,
HDA_CODEC_IDX_CONTROLLER, false);
/* match for forbid call in snd_hda_codec_device_new() */
pm_runtime_allow(&hdev->dev);
/*
* hdac_device core already sets the state to active and calls
* get_noresume. So enable runtime and set the device to suspend.
* pm_runtime_enable is also called during codec registeration
*/
pm_runtime_put(&hdev->dev);
pm_runtime_suspend(&hdev->dev);
return 0;
error_patch:
if (hcodec->patch_ops.free)
hcodec->patch_ops.free(hcodec);
error_regmap:
snd_hdac_regmap_exit(hdev);
error_pm:
pm_runtime_put(&hdev->dev);
error_no_pm:
snd_hdac_ext_bus_link_put(hdev->bus, hlink);
return ret;
}
static void hdac_hda_codec_remove(struct snd_soc_component *component)
{
struct hdac_hda_priv *hda_pvt =
snd_soc_component_get_drvdata(component);
struct hdac_device *hdev = &hda_pvt->codec->core;
struct hda_codec *codec = hda_pvt->codec;
struct hdac_ext_link *hlink = NULL;
hlink = snd_hdac_ext_bus_get_hlink_by_name(hdev->bus, dev_name(&hdev->dev));
if (!hlink) {
dev_err(&hdev->dev, "hdac link not found\n");
return;
}
pm_runtime_disable(&hdev->dev);
snd_hdac_ext_bus_link_put(hdev->bus, hlink);
if (codec->patch_ops.free)
codec->patch_ops.free(codec);
snd_hda_codec_cleanup_for_unbind(codec);
}
static const struct snd_soc_dapm_route hdac_hda_dapm_routes[] = {
{"AIF1TX", NULL, "Codec Input Pin1"},
{"AIF2TX", NULL, "Codec Input Pin2"},
{"AIF3TX", NULL, "Codec Input Pin3"},
{"Codec Output Pin1", NULL, "AIF1RX"},
{"Codec Output Pin2", NULL, "AIF2RX"},
{"Codec Output Pin3", NULL, "AIF3RX"},
};
static const struct snd_soc_dapm_widget hdac_hda_dapm_widgets[] = {
/* Audio Interface */
SND_SOC_DAPM_AIF_IN("AIF1RX", "Analog Codec Playback", 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX", "Digital Codec Playback", 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIF3RX", "Alt Analog Codec Playback", 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX", "Analog Codec Capture", 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX", "Digital Codec Capture", 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF3TX", "Alt Analog Codec Capture", 0,
SND_SOC_NOPM, 0, 0),
/* Input Pins */
SND_SOC_DAPM_INPUT("Codec Input Pin1"),
SND_SOC_DAPM_INPUT("Codec Input Pin2"),
SND_SOC_DAPM_INPUT("Codec Input Pin3"),
/* Output Pins */
SND_SOC_DAPM_OUTPUT("Codec Output Pin1"),
SND_SOC_DAPM_OUTPUT("Codec Output Pin2"),
SND_SOC_DAPM_OUTPUT("Codec Output Pin3"),
};
static const struct snd_soc_component_driver hdac_hda_codec = {
.probe = hdac_hda_codec_probe,
.remove = hdac_hda_codec_remove,
.dapm_widgets = hdac_hda_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(hdac_hda_dapm_widgets),
.dapm_routes = hdac_hda_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(hdac_hda_dapm_routes),
.idle_bias_on = false,
.endianness = 1,
};
static int hdac_hda_dev_probe(struct hdac_device *hdev)
{
struct hdac_ext_link *hlink;
int ret;
/* hold the ref while we probe */
hlink = snd_hdac_ext_bus_get_hlink_by_name(hdev->bus, dev_name(&hdev->dev));
if (!hlink) {
dev_err(&hdev->dev, "hdac link not found\n");
return -EIO;
}
snd_hdac_ext_bus_link_get(hdev->bus, hlink);
/* ASoC specific initialization */
ret = devm_snd_soc_register_component(&hdev->dev,
&hdac_hda_codec, hdac_hda_dais,
ARRAY_SIZE(hdac_hda_dais));
if (ret < 0) {
dev_err(&hdev->dev, "failed to register HDA codec %d\n", ret);
return ret;
}
snd_hdac_ext_bus_link_put(hdev->bus, hlink);
return ret;
}
static int hdac_hda_dev_remove(struct hdac_device *hdev)
{
/*
* Resources are freed in hdac_hda_codec_remove(). This
* function is kept to keep hda_codec_driver_remove() happy.
*/
return 0;
}
static struct hdac_ext_bus_ops hdac_ops = {
.hdev_attach = hdac_hda_dev_probe,
.hdev_detach = hdac_hda_dev_remove,
};
struct hdac_ext_bus_ops *snd_soc_hdac_hda_get_ops(void)
{
return &hdac_ops;
}
EXPORT_SYMBOL_GPL(snd_soc_hdac_hda_get_ops);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("ASoC Extensions for legacy HDA Drivers");
MODULE_AUTHOR("Rakesh Ughreja<[email protected]>");
| linux-master | sound/soc/codecs/hdac_hda.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Driver of Inno codec for rk3036 by Rockchip Inc.
*
* Author: Rockchip Inc.
* Author: Zheng ShunQian<[email protected]>
*/
#include <sound/soc.h>
#include <sound/tlv.h>
#include <sound/soc-dapm.h>
#include <sound/soc-dai.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/clk.h>
#include <linux/regmap.h>
#include <linux/device.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/io.h>
#include "inno_rk3036.h"
struct rk3036_codec_priv {
void __iomem *base;
struct clk *pclk;
struct regmap *regmap;
struct device *dev;
};
static const DECLARE_TLV_DB_MINMAX(rk3036_codec_hp_tlv, -39, 0);
static int rk3036_codec_antipop_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
uinfo->count = 2;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = 1;
return 0;
}
static int rk3036_codec_antipop_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
int val, regval;
regval = snd_soc_component_read(component, INNO_R09);
val = ((regval >> INNO_R09_HPL_ANITPOP_SHIFT) &
INNO_R09_HP_ANTIPOP_MSK) == INNO_R09_HP_ANTIPOP_ON;
ucontrol->value.integer.value[0] = val;
val = ((regval >> INNO_R09_HPR_ANITPOP_SHIFT) &
INNO_R09_HP_ANTIPOP_MSK) == INNO_R09_HP_ANTIPOP_ON;
ucontrol->value.integer.value[1] = val;
return 0;
}
static int rk3036_codec_antipop_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
int val, ret, regmsk;
val = (ucontrol->value.integer.value[0] ?
INNO_R09_HP_ANTIPOP_ON : INNO_R09_HP_ANTIPOP_OFF) <<
INNO_R09_HPL_ANITPOP_SHIFT;
val |= (ucontrol->value.integer.value[1] ?
INNO_R09_HP_ANTIPOP_ON : INNO_R09_HP_ANTIPOP_OFF) <<
INNO_R09_HPR_ANITPOP_SHIFT;
regmsk = INNO_R09_HP_ANTIPOP_MSK << INNO_R09_HPL_ANITPOP_SHIFT |
INNO_R09_HP_ANTIPOP_MSK << INNO_R09_HPR_ANITPOP_SHIFT;
ret = snd_soc_component_update_bits(component, INNO_R09,
regmsk, val);
if (ret < 0)
return ret;
return 0;
}
#define SOC_RK3036_CODEC_ANTIPOP_DECL(xname) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
.info = rk3036_codec_antipop_info, .get = rk3036_codec_antipop_get, \
.put = rk3036_codec_antipop_put, }
static const struct snd_kcontrol_new rk3036_codec_dapm_controls[] = {
SOC_DOUBLE_R_RANGE_TLV("Headphone Volume", INNO_R07, INNO_R08,
INNO_HP_GAIN_SHIFT, INNO_HP_GAIN_N39DB,
INNO_HP_GAIN_0DB, 0, rk3036_codec_hp_tlv),
SOC_DOUBLE("Zero Cross Switch", INNO_R06, INNO_R06_VOUTL_CZ_SHIFT,
INNO_R06_VOUTR_CZ_SHIFT, 1, 0),
SOC_DOUBLE("Headphone Switch", INNO_R09, INNO_R09_HPL_MUTE_SHIFT,
INNO_R09_HPR_MUTE_SHIFT, 1, 0),
SOC_RK3036_CODEC_ANTIPOP_DECL("Anti-pop Switch"),
};
static const struct snd_kcontrol_new rk3036_codec_hpl_mixer_controls[] = {
SOC_DAPM_SINGLE("DAC Left Out Switch", INNO_R09,
INNO_R09_DACL_SWITCH_SHIFT, 1, 0),
};
static const struct snd_kcontrol_new rk3036_codec_hpr_mixer_controls[] = {
SOC_DAPM_SINGLE("DAC Right Out Switch", INNO_R09,
INNO_R09_DACR_SWITCH_SHIFT, 1, 0),
};
static const struct snd_kcontrol_new rk3036_codec_hpl_switch_controls[] = {
SOC_DAPM_SINGLE("HP Left Out Switch", INNO_R05,
INNO_R05_HPL_WORK_SHIFT, 1, 0),
};
static const struct snd_kcontrol_new rk3036_codec_hpr_switch_controls[] = {
SOC_DAPM_SINGLE("HP Right Out Switch", INNO_R05,
INNO_R05_HPR_WORK_SHIFT, 1, 0),
};
static const struct snd_soc_dapm_widget rk3036_codec_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY_S("DAC PWR", 1, INNO_R06,
INNO_R06_DAC_EN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DACL VREF", 2, INNO_R04,
INNO_R04_DACL_VREF_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DACR VREF", 2, INNO_R04,
INNO_R04_DACR_VREF_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DACL HiLo VREF", 3, INNO_R06,
INNO_R06_DACL_HILO_VREF_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DACR HiLo VREF", 3, INNO_R06,
INNO_R06_DACR_HILO_VREF_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DACR CLK", 3, INNO_R04,
INNO_R04_DACR_CLK_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DACL CLK", 3, INNO_R04,
INNO_R04_DACL_CLK_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_DAC("DACL", "Left Playback", INNO_R04,
INNO_R04_DACL_SW_SHIFT, 0),
SND_SOC_DAPM_DAC("DACR", "Right Playback", INNO_R04,
INNO_R04_DACR_SW_SHIFT, 0),
SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
rk3036_codec_hpl_mixer_controls,
ARRAY_SIZE(rk3036_codec_hpl_mixer_controls)),
SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
rk3036_codec_hpr_mixer_controls,
ARRAY_SIZE(rk3036_codec_hpr_mixer_controls)),
SND_SOC_DAPM_PGA("HP Left Out", INNO_R05,
INNO_R05_HPL_EN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("HP Right Out", INNO_R05,
INNO_R05_HPR_EN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("HP Left Switch", SND_SOC_NOPM, 0, 0,
rk3036_codec_hpl_switch_controls,
ARRAY_SIZE(rk3036_codec_hpl_switch_controls)),
SND_SOC_DAPM_MIXER("HP Right Switch", SND_SOC_NOPM, 0, 0,
rk3036_codec_hpr_switch_controls,
ARRAY_SIZE(rk3036_codec_hpr_switch_controls)),
SND_SOC_DAPM_OUTPUT("HPL"),
SND_SOC_DAPM_OUTPUT("HPR"),
};
static const struct snd_soc_dapm_route rk3036_codec_dapm_routes[] = {
{"DACL VREF", NULL, "DAC PWR"},
{"DACR VREF", NULL, "DAC PWR"},
{"DACL HiLo VREF", NULL, "DAC PWR"},
{"DACR HiLo VREF", NULL, "DAC PWR"},
{"DACL CLK", NULL, "DAC PWR"},
{"DACR CLK", NULL, "DAC PWR"},
{"DACL", NULL, "DACL VREF"},
{"DACL", NULL, "DACL HiLo VREF"},
{"DACL", NULL, "DACL CLK"},
{"DACR", NULL, "DACR VREF"},
{"DACR", NULL, "DACR HiLo VREF"},
{"DACR", NULL, "DACR CLK"},
{"Left Headphone Mixer", "DAC Left Out Switch", "DACL"},
{"Right Headphone Mixer", "DAC Right Out Switch", "DACR"},
{"HP Left Out", NULL, "Left Headphone Mixer"},
{"HP Right Out", NULL, "Right Headphone Mixer"},
{"HP Left Switch", "HP Left Out Switch", "HP Left Out"},
{"HP Right Switch", "HP Right Out Switch", "HP Right Out"},
{"HPL", NULL, "HP Left Switch"},
{"HPR", NULL, "HP Right Switch"},
};
static int rk3036_codec_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
unsigned int reg01_val = 0, reg02_val = 0, reg03_val = 0;
dev_dbg(component->dev, "rk3036_codec dai set fmt : %08x\n", fmt);
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC:
reg01_val |= INNO_R01_PINDIR_IN_SLAVE |
INNO_R01_I2SMODE_SLAVE;
break;
case SND_SOC_DAIFMT_CBP_CFP:
reg01_val |= INNO_R01_PINDIR_OUT_MASTER |
INNO_R01_I2SMODE_MASTER;
break;
default:
dev_err(component->dev, "invalid fmt\n");
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
reg02_val |= INNO_R02_DACM_PCM;
break;
case SND_SOC_DAIFMT_I2S:
reg02_val |= INNO_R02_DACM_I2S;
break;
case SND_SOC_DAIFMT_RIGHT_J:
reg02_val |= INNO_R02_DACM_RJM;
break;
case SND_SOC_DAIFMT_LEFT_J:
reg02_val |= INNO_R02_DACM_LJM;
break;
default:
dev_err(component->dev, "set dai format failed\n");
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
reg02_val |= INNO_R02_LRCP_NORMAL;
reg03_val |= INNO_R03_BCP_NORMAL;
break;
case SND_SOC_DAIFMT_IB_IF:
reg02_val |= INNO_R02_LRCP_REVERSAL;
reg03_val |= INNO_R03_BCP_REVERSAL;
break;
case SND_SOC_DAIFMT_IB_NF:
reg02_val |= INNO_R02_LRCP_REVERSAL;
reg03_val |= INNO_R03_BCP_NORMAL;
break;
case SND_SOC_DAIFMT_NB_IF:
reg02_val |= INNO_R02_LRCP_NORMAL;
reg03_val |= INNO_R03_BCP_REVERSAL;
break;
default:
dev_err(component->dev, "set dai format failed\n");
return -EINVAL;
}
snd_soc_component_update_bits(component, INNO_R01, INNO_R01_I2SMODE_MSK |
INNO_R01_PINDIR_MSK, reg01_val);
snd_soc_component_update_bits(component, INNO_R02, INNO_R02_LRCP_MSK |
INNO_R02_DACM_MSK, reg02_val);
snd_soc_component_update_bits(component, INNO_R03, INNO_R03_BCP_MSK, reg03_val);
return 0;
}
static int rk3036_codec_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *hw_params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
unsigned int reg02_val = 0, reg03_val = 0;
switch (params_format(hw_params)) {
case SNDRV_PCM_FORMAT_S16_LE:
reg02_val |= INNO_R02_VWL_16BIT;
break;
case SNDRV_PCM_FORMAT_S20_3LE:
reg02_val |= INNO_R02_VWL_20BIT;
break;
case SNDRV_PCM_FORMAT_S24_LE:
reg02_val |= INNO_R02_VWL_24BIT;
break;
case SNDRV_PCM_FORMAT_S32_LE:
reg02_val |= INNO_R02_VWL_32BIT;
break;
default:
return -EINVAL;
}
reg02_val |= INNO_R02_LRCP_NORMAL;
reg03_val |= INNO_R03_FWL_32BIT | INNO_R03_DACR_WORK;
snd_soc_component_update_bits(component, INNO_R02, INNO_R02_LRCP_MSK |
INNO_R02_VWL_MSK, reg02_val);
snd_soc_component_update_bits(component, INNO_R03, INNO_R03_DACR_MSK |
INNO_R03_FWL_MSK, reg03_val);
return 0;
}
#define RK3036_CODEC_RATES (SNDRV_PCM_RATE_8000 | \
SNDRV_PCM_RATE_16000 | \
SNDRV_PCM_RATE_32000 | \
SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000 | \
SNDRV_PCM_RATE_96000)
#define RK3036_CODEC_FMTS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops rk3036_codec_dai_ops = {
.set_fmt = rk3036_codec_dai_set_fmt,
.hw_params = rk3036_codec_dai_hw_params,
};
static struct snd_soc_dai_driver rk3036_codec_dai_driver[] = {
{
.name = "rk3036-codec-dai",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RK3036_CODEC_RATES,
.formats = RK3036_CODEC_FMTS,
},
.ops = &rk3036_codec_dai_ops,
.symmetric_rate = 1,
},
};
static void rk3036_codec_reset(struct snd_soc_component *component)
{
snd_soc_component_write(component, INNO_R00,
INNO_R00_CSR_RESET | INNO_R00_CDCR_RESET);
snd_soc_component_write(component, INNO_R00,
INNO_R00_CSR_WORK | INNO_R00_CDCR_WORK);
}
static int rk3036_codec_probe(struct snd_soc_component *component)
{
rk3036_codec_reset(component);
return 0;
}
static void rk3036_codec_remove(struct snd_soc_component *component)
{
rk3036_codec_reset(component);
}
static int rk3036_codec_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
switch (level) {
case SND_SOC_BIAS_STANDBY:
/* set a big current for capacitor charging. */
snd_soc_component_write(component, INNO_R10, INNO_R10_MAX_CUR);
/* start precharge */
snd_soc_component_write(component, INNO_R06, INNO_R06_DAC_PRECHARGE);
break;
case SND_SOC_BIAS_OFF:
/* set a big current for capacitor discharging. */
snd_soc_component_write(component, INNO_R10, INNO_R10_MAX_CUR);
/* start discharge. */
snd_soc_component_write(component, INNO_R06, INNO_R06_DAC_DISCHARGE);
break;
default:
break;
}
return 0;
}
static const struct snd_soc_component_driver rk3036_codec_driver = {
.probe = rk3036_codec_probe,
.remove = rk3036_codec_remove,
.set_bias_level = rk3036_codec_set_bias_level,
.controls = rk3036_codec_dapm_controls,
.num_controls = ARRAY_SIZE(rk3036_codec_dapm_controls),
.dapm_routes = rk3036_codec_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(rk3036_codec_dapm_routes),
.dapm_widgets = rk3036_codec_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rk3036_codec_dapm_widgets),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config rk3036_codec_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
};
#define GRF_SOC_CON0 0x00140
#define GRF_ACODEC_SEL (BIT(10) | BIT(16 + 10))
static int rk3036_codec_platform_probe(struct platform_device *pdev)
{
struct rk3036_codec_priv *priv;
struct device_node *of_node = pdev->dev.of_node;
void __iomem *base;
struct regmap *grf;
int ret;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
priv->base = base;
priv->regmap = devm_regmap_init_mmio(&pdev->dev, priv->base,
&rk3036_codec_regmap_config);
if (IS_ERR(priv->regmap)) {
dev_err(&pdev->dev, "init regmap failed\n");
return PTR_ERR(priv->regmap);
}
grf = syscon_regmap_lookup_by_phandle(of_node, "rockchip,grf");
if (IS_ERR(grf)) {
dev_err(&pdev->dev, "needs 'rockchip,grf' property\n");
return PTR_ERR(grf);
}
ret = regmap_write(grf, GRF_SOC_CON0, GRF_ACODEC_SEL);
if (ret) {
dev_err(&pdev->dev, "Could not write to GRF: %d\n", ret);
return ret;
}
priv->pclk = devm_clk_get(&pdev->dev, "acodec_pclk");
if (IS_ERR(priv->pclk))
return PTR_ERR(priv->pclk);
ret = clk_prepare_enable(priv->pclk);
if (ret < 0) {
dev_err(&pdev->dev, "failed to enable clk\n");
return ret;
}
priv->dev = &pdev->dev;
dev_set_drvdata(&pdev->dev, priv);
ret = devm_snd_soc_register_component(&pdev->dev, &rk3036_codec_driver,
rk3036_codec_dai_driver,
ARRAY_SIZE(rk3036_codec_dai_driver));
if (ret) {
clk_disable_unprepare(priv->pclk);
dev_set_drvdata(&pdev->dev, NULL);
}
return ret;
}
static void rk3036_codec_platform_remove(struct platform_device *pdev)
{
struct rk3036_codec_priv *priv = dev_get_drvdata(&pdev->dev);
clk_disable_unprepare(priv->pclk);
}
static const struct of_device_id rk3036_codec_of_match[] __maybe_unused = {
{ .compatible = "rockchip,rk3036-codec", },
{}
};
MODULE_DEVICE_TABLE(of, rk3036_codec_of_match);
static struct platform_driver rk3036_codec_platform_driver = {
.driver = {
.name = "rk3036-codec-platform",
.of_match_table = of_match_ptr(rk3036_codec_of_match),
},
.probe = rk3036_codec_platform_probe,
.remove_new = rk3036_codec_platform_remove,
};
module_platform_driver(rk3036_codec_platform_driver);
MODULE_AUTHOR("Rockchip Inc.");
MODULE_DESCRIPTION("Rockchip rk3036 codec driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/inno_rk3036.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ALSA SoC WL1273 codec driver
*
* Author: Matti Aaltonen, <[email protected]>
*
* Copyright: (C) 2010, 2011 Nokia Corporation
*/
#include <linux/mfd/wl1273-core.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include "wl1273.h"
enum wl1273_mode { WL1273_MODE_BT, WL1273_MODE_FM_RX, WL1273_MODE_FM_TX };
/* codec private data */
struct wl1273_priv {
enum wl1273_mode mode;
struct wl1273_core *core;
unsigned int channels;
};
static int snd_wl1273_fm_set_i2s_mode(struct wl1273_core *core,
int rate, int width)
{
struct device *dev = &core->client->dev;
int r = 0;
u16 mode;
dev_dbg(dev, "rate: %d\n", rate);
dev_dbg(dev, "width: %d\n", width);
mutex_lock(&core->lock);
mode = core->i2s_mode & ~WL1273_IS2_WIDTH & ~WL1273_IS2_RATE;
switch (rate) {
case 48000:
mode |= WL1273_IS2_RATE_48K;
break;
case 44100:
mode |= WL1273_IS2_RATE_44_1K;
break;
case 32000:
mode |= WL1273_IS2_RATE_32K;
break;
case 22050:
mode |= WL1273_IS2_RATE_22_05K;
break;
case 16000:
mode |= WL1273_IS2_RATE_16K;
break;
case 12000:
mode |= WL1273_IS2_RATE_12K;
break;
case 11025:
mode |= WL1273_IS2_RATE_11_025;
break;
case 8000:
mode |= WL1273_IS2_RATE_8K;
break;
default:
dev_err(dev, "Sampling rate: %d not supported\n", rate);
r = -EINVAL;
goto out;
}
switch (width) {
case 16:
mode |= WL1273_IS2_WIDTH_32;
break;
case 20:
mode |= WL1273_IS2_WIDTH_40;
break;
case 24:
mode |= WL1273_IS2_WIDTH_48;
break;
case 25:
mode |= WL1273_IS2_WIDTH_50;
break;
case 30:
mode |= WL1273_IS2_WIDTH_60;
break;
case 32:
mode |= WL1273_IS2_WIDTH_64;
break;
case 40:
mode |= WL1273_IS2_WIDTH_80;
break;
case 48:
mode |= WL1273_IS2_WIDTH_96;
break;
case 64:
mode |= WL1273_IS2_WIDTH_128;
break;
default:
dev_err(dev, "Data width: %d not supported\n", width);
r = -EINVAL;
goto out;
}
dev_dbg(dev, "WL1273_I2S_DEF_MODE: 0x%04x\n", WL1273_I2S_DEF_MODE);
dev_dbg(dev, "core->i2s_mode: 0x%04x\n", core->i2s_mode);
dev_dbg(dev, "mode: 0x%04x\n", mode);
if (core->i2s_mode != mode) {
r = core->write(core, WL1273_I2S_MODE_CONFIG_SET, mode);
if (r)
goto out;
core->i2s_mode = mode;
r = core->write(core, WL1273_AUDIO_ENABLE,
WL1273_AUDIO_ENABLE_I2S);
if (r)
goto out;
}
out:
mutex_unlock(&core->lock);
return r;
}
static int snd_wl1273_fm_set_channel_number(struct wl1273_core *core,
int channel_number)
{
struct device *dev = &core->client->dev;
int r = 0;
dev_dbg(dev, "%s\n", __func__);
mutex_lock(&core->lock);
if (core->channel_number == channel_number)
goto out;
if (channel_number == 1 && core->mode == WL1273_MODE_RX)
r = core->write(core, WL1273_MOST_MODE_SET, WL1273_RX_MONO);
else if (channel_number == 1 && core->mode == WL1273_MODE_TX)
r = core->write(core, WL1273_MONO_SET, WL1273_TX_MONO);
else if (channel_number == 2 && core->mode == WL1273_MODE_RX)
r = core->write(core, WL1273_MOST_MODE_SET, WL1273_RX_STEREO);
else if (channel_number == 2 && core->mode == WL1273_MODE_TX)
r = core->write(core, WL1273_MONO_SET, WL1273_TX_STEREO);
else
r = -EINVAL;
out:
mutex_unlock(&core->lock);
return r;
}
static int snd_wl1273_get_audio_route(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wl1273_priv *wl1273 = snd_soc_component_get_drvdata(component);
ucontrol->value.enumerated.item[0] = wl1273->mode;
return 0;
}
/*
* TODO: Implement the audio routing in the driver. Now this control
* only indicates the setting that has been done elsewhere (in the user
* space).
*/
static const char * const wl1273_audio_route[] = { "Bt", "FmRx", "FmTx" };
static int snd_wl1273_set_audio_route(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wl1273_priv *wl1273 = snd_soc_component_get_drvdata(component);
if (wl1273->mode == ucontrol->value.enumerated.item[0])
return 0;
/* Do not allow changes while stream is running */
if (snd_soc_component_active(component))
return -EPERM;
if (ucontrol->value.enumerated.item[0] >= ARRAY_SIZE(wl1273_audio_route))
return -EINVAL;
wl1273->mode = ucontrol->value.enumerated.item[0];
return 1;
}
static SOC_ENUM_SINGLE_EXT_DECL(wl1273_enum, wl1273_audio_route);
static int snd_wl1273_fm_audio_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wl1273_priv *wl1273 = snd_soc_component_get_drvdata(component);
dev_dbg(component->dev, "%s: enter.\n", __func__);
ucontrol->value.enumerated.item[0] = wl1273->core->audio_mode;
return 0;
}
static int snd_wl1273_fm_audio_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wl1273_priv *wl1273 = snd_soc_component_get_drvdata(component);
int val, r = 0;
dev_dbg(component->dev, "%s: enter.\n", __func__);
val = ucontrol->value.enumerated.item[0];
if (wl1273->core->audio_mode == val)
return 0;
r = wl1273->core->set_audio(wl1273->core, val);
if (r < 0)
return r;
return 1;
}
static const char * const wl1273_audio_strings[] = { "Digital", "Analog" };
static SOC_ENUM_SINGLE_EXT_DECL(wl1273_audio_enum, wl1273_audio_strings);
static int snd_wl1273_fm_volume_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wl1273_priv *wl1273 = snd_soc_component_get_drvdata(component);
dev_dbg(component->dev, "%s: enter.\n", __func__);
ucontrol->value.integer.value[0] = wl1273->core->volume;
return 0;
}
static int snd_wl1273_fm_volume_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wl1273_priv *wl1273 = snd_soc_component_get_drvdata(component);
int r;
dev_dbg(component->dev, "%s: enter.\n", __func__);
r = wl1273->core->set_volume(wl1273->core,
ucontrol->value.integer.value[0]);
if (r)
return r;
return 1;
}
static const struct snd_kcontrol_new wl1273_controls[] = {
SOC_ENUM_EXT("Codec Mode", wl1273_enum,
snd_wl1273_get_audio_route, snd_wl1273_set_audio_route),
SOC_ENUM_EXT("Audio Switch", wl1273_audio_enum,
snd_wl1273_fm_audio_get, snd_wl1273_fm_audio_put),
SOC_SINGLE_EXT("Volume", 0, 0, WL1273_MAX_VOLUME, 0,
snd_wl1273_fm_volume_get, snd_wl1273_fm_volume_put),
};
static const struct snd_soc_dapm_widget wl1273_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("RX"),
SND_SOC_DAPM_OUTPUT("TX"),
};
static const struct snd_soc_dapm_route wl1273_dapm_routes[] = {
{ "Capture", NULL, "RX" },
{ "TX", NULL, "Playback" },
};
static int wl1273_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wl1273_priv *wl1273 = snd_soc_component_get_drvdata(component);
switch (wl1273->mode) {
case WL1273_MODE_BT:
snd_pcm_hw_constraint_single(substream->runtime,
SNDRV_PCM_HW_PARAM_RATE, 8000);
snd_pcm_hw_constraint_single(substream->runtime,
SNDRV_PCM_HW_PARAM_CHANNELS, 1);
break;
case WL1273_MODE_FM_RX:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
pr_err("Cannot play in RX mode.\n");
return -EINVAL;
}
break;
case WL1273_MODE_FM_TX:
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
pr_err("Cannot capture in TX mode.\n");
return -EINVAL;
}
break;
default:
return -EINVAL;
}
return 0;
}
static int wl1273_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct wl1273_priv *wl1273 = snd_soc_component_get_drvdata(dai->component);
struct wl1273_core *core = wl1273->core;
unsigned int rate, width, r;
if (params_width(params) != 16) {
dev_err(dai->dev, "%d bits/sample not supported\n",
params_width(params));
return -EINVAL;
}
rate = params_rate(params);
width = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
if (wl1273->mode == WL1273_MODE_BT) {
if (rate != 8000) {
pr_err("Rate %d not supported.\n", params_rate(params));
return -EINVAL;
}
if (params_channels(params) != 1) {
pr_err("Only mono supported.\n");
return -EINVAL;
}
return 0;
}
if (wl1273->mode == WL1273_MODE_FM_TX &&
substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
pr_err("Only playback supported with TX.\n");
return -EINVAL;
}
if (wl1273->mode == WL1273_MODE_FM_RX &&
substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
pr_err("Only capture supported with RX.\n");
return -EINVAL;
}
if (wl1273->mode != WL1273_MODE_FM_RX &&
wl1273->mode != WL1273_MODE_FM_TX) {
pr_err("Unexpected mode: %d.\n", wl1273->mode);
return -EINVAL;
}
r = snd_wl1273_fm_set_i2s_mode(core, rate, width);
if (r)
return r;
wl1273->channels = params_channels(params);
r = snd_wl1273_fm_set_channel_number(core, wl1273->channels);
if (r)
return r;
return 0;
}
static const struct snd_soc_dai_ops wl1273_dai_ops = {
.startup = wl1273_startup,
.hw_params = wl1273_hw_params,
};
static struct snd_soc_dai_driver wl1273_dai = {
.name = "wl1273-fm",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE},
.ops = &wl1273_dai_ops,
};
/* Audio interface format for the soc_card driver */
int wl1273_get_format(struct snd_soc_component *component, unsigned int *fmt)
{
struct wl1273_priv *wl1273;
if (component == NULL || fmt == NULL)
return -EINVAL;
wl1273 = snd_soc_component_get_drvdata(component);
switch (wl1273->mode) {
case WL1273_MODE_FM_RX:
case WL1273_MODE_FM_TX:
*fmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBP_CFP;
break;
case WL1273_MODE_BT:
*fmt = SND_SOC_DAIFMT_DSP_A |
SND_SOC_DAIFMT_IB_NF |
SND_SOC_DAIFMT_CBP_CFP;
break;
default:
return -EINVAL;
}
return 0;
}
EXPORT_SYMBOL_GPL(wl1273_get_format);
static int wl1273_probe(struct snd_soc_component *component)
{
struct wl1273_core **core = component->dev->platform_data;
struct wl1273_priv *wl1273;
dev_dbg(component->dev, "%s.\n", __func__);
if (!core) {
dev_err(component->dev, "Platform data is missing.\n");
return -EINVAL;
}
wl1273 = kzalloc(sizeof(struct wl1273_priv), GFP_KERNEL);
if (!wl1273)
return -ENOMEM;
wl1273->mode = WL1273_MODE_BT;
wl1273->core = *core;
snd_soc_component_set_drvdata(component, wl1273);
return 0;
}
static void wl1273_remove(struct snd_soc_component *component)
{
struct wl1273_priv *wl1273 = snd_soc_component_get_drvdata(component);
dev_dbg(component->dev, "%s\n", __func__);
kfree(wl1273);
}
static const struct snd_soc_component_driver soc_component_dev_wl1273 = {
.probe = wl1273_probe,
.remove = wl1273_remove,
.controls = wl1273_controls,
.num_controls = ARRAY_SIZE(wl1273_controls),
.dapm_widgets = wl1273_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wl1273_dapm_widgets),
.dapm_routes = wl1273_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(wl1273_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int wl1273_platform_probe(struct platform_device *pdev)
{
return devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_wl1273,
&wl1273_dai, 1);
}
MODULE_ALIAS("platform:wl1273-codec");
static struct platform_driver wl1273_platform_driver = {
.driver = {
.name = "wl1273-codec",
},
.probe = wl1273_platform_probe,
};
module_platform_driver(wl1273_platform_driver);
MODULE_AUTHOR("Matti Aaltonen <[email protected]>");
MODULE_DESCRIPTION("ASoC WL1273 codec driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wl1273.c |
// SPDX-License-Identifier: GPL-2.0
//
// CS42L43 CODEC driver SoundWire handling
//
// Copyright (C) 2022-2023 Cirrus Logic, Inc. and
// Cirrus Logic International Semiconductor Ltd.
#include <linux/errno.h>
#include <linux/mfd/cs42l43.h>
#include <linux/mfd/cs42l43-regs.h>
#include <linux/module.h>
#include <sound/pcm.h>
#include <sound/sdw.h>
#include <sound/soc-component.h>
#include <sound/soc-dai.h>
#include <sound/soc.h>
#include "cs42l43.h"
int cs42l43_sdw_add_peripheral(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct cs42l43_codec *priv = snd_soc_component_get_drvdata(dai->component);
struct sdw_stream_runtime *sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
struct sdw_slave *sdw = dev_to_sdw_dev(priv->dev->parent);
struct sdw_stream_config sconfig = {0};
struct sdw_port_config pconfig = {0};
int ret;
if (!sdw_stream)
return -EINVAL;
snd_sdw_params_to_config(substream, params, &sconfig, &pconfig);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
pconfig.num = dai->id;
else
pconfig.num = dai->id;
ret = sdw_stream_add_slave(sdw, &sconfig, &pconfig, 1, sdw_stream);
if (ret) {
dev_err(priv->dev, "Failed to add sdw stream: %d\n", ret);
return ret;
}
return 0;
}
EXPORT_SYMBOL_NS_GPL(cs42l43_sdw_add_peripheral, SND_SOC_CS42L43);
int cs42l43_sdw_remove_peripheral(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct cs42l43_codec *priv = snd_soc_component_get_drvdata(dai->component);
struct sdw_stream_runtime *sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
struct sdw_slave *sdw = dev_to_sdw_dev(priv->dev->parent);
if (!sdw_stream)
return -EINVAL;
return sdw_stream_remove_slave(sdw, sdw_stream);
}
EXPORT_SYMBOL_NS_GPL(cs42l43_sdw_remove_peripheral, SND_SOC_CS42L43);
int cs42l43_sdw_set_stream(struct snd_soc_dai *dai, void *sdw_stream, int direction)
{
snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
return 0;
}
EXPORT_SYMBOL_NS_GPL(cs42l43_sdw_set_stream, SND_SOC_CS42L43);
MODULE_DESCRIPTION("CS42L43 CODEC SoundWire Driver");
MODULE_AUTHOR("Charles Keepax <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cs42l43-sdw.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Common code for ADAU1X61 and ADAU1X81 codecs
*
* Copyright 2011-2014 Analog Devices Inc.
* Author: Lars-Peter Clausen <[email protected]>
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <linux/i2c.h>
#include <linux/spi/spi.h>
#include <linux/regmap.h>
#include <asm/unaligned.h>
#include "sigmadsp.h"
#include "adau17x1.h"
#include "adau-utils.h"
#define ADAU17X1_SAFELOAD_TARGET_ADDRESS 0x0006
#define ADAU17X1_SAFELOAD_TRIGGER 0x0007
#define ADAU17X1_SAFELOAD_DATA 0x0001
#define ADAU17X1_SAFELOAD_DATA_SIZE 20
#define ADAU17X1_WORD_SIZE 4
static const char * const adau17x1_capture_mixer_boost_text[] = {
"Normal operation", "Boost Level 1", "Boost Level 2", "Boost Level 3",
};
static SOC_ENUM_SINGLE_DECL(adau17x1_capture_boost_enum,
ADAU17X1_REC_POWER_MGMT, 5, adau17x1_capture_mixer_boost_text);
static const char * const adau17x1_mic_bias_mode_text[] = {
"Normal operation", "High performance",
};
static SOC_ENUM_SINGLE_DECL(adau17x1_mic_bias_mode_enum,
ADAU17X1_MICBIAS, 3, adau17x1_mic_bias_mode_text);
static const DECLARE_TLV_DB_MINMAX(adau17x1_digital_tlv, -9563, 0);
static const struct snd_kcontrol_new adau17x1_controls[] = {
SOC_DOUBLE_R_TLV("Digital Capture Volume",
ADAU17X1_LEFT_INPUT_DIGITAL_VOL,
ADAU17X1_RIGHT_INPUT_DIGITAL_VOL,
0, 0xff, 1, adau17x1_digital_tlv),
SOC_DOUBLE_R_TLV("Digital Playback Volume", ADAU17X1_DAC_CONTROL1,
ADAU17X1_DAC_CONTROL2, 0, 0xff, 1, adau17x1_digital_tlv),
SOC_SINGLE("ADC High Pass Filter Switch", ADAU17X1_ADC_CONTROL,
5, 1, 0),
SOC_SINGLE("Playback De-emphasis Switch", ADAU17X1_DAC_CONTROL0,
2, 1, 0),
SOC_ENUM("Capture Boost", adau17x1_capture_boost_enum),
SOC_ENUM("Mic Bias Mode", adau17x1_mic_bias_mode_enum),
};
static int adau17x1_setup_firmware(struct snd_soc_component *component,
unsigned int rate);
static int adau17x1_pll_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct adau *adau = snd_soc_component_get_drvdata(component);
if (SND_SOC_DAPM_EVENT_ON(event)) {
adau->pll_regs[5] = 1;
} else {
adau->pll_regs[5] = 0;
/* Bypass the PLL when disabled, otherwise registers will become
* inaccessible. */
regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL,
ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL, 0);
}
/* The PLL register is 6 bytes long and can only be written at once. */
regmap_raw_write(adau->regmap, ADAU17X1_PLL_CONTROL,
adau->pll_regs, ARRAY_SIZE(adau->pll_regs));
if (SND_SOC_DAPM_EVENT_ON(event)) {
mdelay(5);
regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL,
ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL,
ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL);
}
return 0;
}
static int adau17x1_adc_fixup(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct adau *adau = snd_soc_component_get_drvdata(component);
/*
* If we are capturing, toggle the ADOSR bit in Converter Control 0 to
* avoid losing SNR (workaround from ADI). This must be done after
* the ADC(s) have been enabled. According to the data sheet, it is
* normally illegal to set this bit when the sampling rate is 96 kHz,
* but according to ADI it is acceptable for this workaround.
*/
regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0,
ADAU17X1_CONVERTER0_ADOSR, ADAU17X1_CONVERTER0_ADOSR);
regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0,
ADAU17X1_CONVERTER0_ADOSR, 0);
return 0;
}
static const char * const adau17x1_mono_stereo_text[] = {
"Stereo",
"Mono Left Channel (L+R)",
"Mono Right Channel (L+R)",
"Mono (L+R)",
};
static SOC_ENUM_SINGLE_DECL(adau17x1_dac_mode_enum,
ADAU17X1_DAC_CONTROL0, 6, adau17x1_mono_stereo_text);
static const struct snd_kcontrol_new adau17x1_dac_mode_mux =
SOC_DAPM_ENUM("DAC Mono-Stereo-Mode", adau17x1_dac_mode_enum);
static const struct snd_soc_dapm_widget adau17x1_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY_S("PLL", 3, SND_SOC_NOPM, 0, 0, adau17x1_pll_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("AIFCLK", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS", ADAU17X1_MICBIAS, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Left Playback Enable", ADAU17X1_PLAY_POWER_MGMT,
0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Right Playback Enable", ADAU17X1_PLAY_POWER_MGMT,
1, 0, NULL, 0),
SND_SOC_DAPM_MUX("Left DAC Mode Mux", SND_SOC_NOPM, 0, 0,
&adau17x1_dac_mode_mux),
SND_SOC_DAPM_MUX("Right DAC Mode Mux", SND_SOC_NOPM, 0, 0,
&adau17x1_dac_mode_mux),
SND_SOC_DAPM_ADC_E("Left Decimator", NULL, ADAU17X1_ADC_CONTROL, 0, 0,
adau17x1_adc_fixup, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_ADC("Right Decimator", NULL, ADAU17X1_ADC_CONTROL, 1, 0),
SND_SOC_DAPM_DAC("Left DAC", NULL, ADAU17X1_DAC_CONTROL0, 0, 0),
SND_SOC_DAPM_DAC("Right DAC", NULL, ADAU17X1_DAC_CONTROL0, 1, 0),
};
static const struct snd_soc_dapm_route adau17x1_dapm_routes[] = {
{ "Left Decimator", NULL, "SYSCLK" },
{ "Right Decimator", NULL, "SYSCLK" },
{ "Left DAC", NULL, "SYSCLK" },
{ "Right DAC", NULL, "SYSCLK" },
{ "Capture", NULL, "SYSCLK" },
{ "Playback", NULL, "SYSCLK" },
{ "Left DAC", NULL, "Left DAC Mode Mux" },
{ "Right DAC", NULL, "Right DAC Mode Mux" },
{ "Capture", NULL, "AIFCLK" },
{ "Playback", NULL, "AIFCLK" },
};
static const struct snd_soc_dapm_route adau17x1_dapm_pll_route = {
"SYSCLK", NULL, "PLL",
};
/*
* The MUX register for the Capture and Playback MUXs selects either DSP as
* source/destination or one of the TDM slots. The TDM slot is selected via
* snd_soc_dai_set_tdm_slot(), so we only expose whether to go to the DSP or
* directly to the DAI interface with this control.
*/
static int adau17x1_dsp_mux_enum_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct adau *adau = snd_soc_component_get_drvdata(component);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
struct snd_soc_dapm_update update = {};
unsigned int stream = e->shift_l;
unsigned int val, change;
int reg;
if (ucontrol->value.enumerated.item[0] >= e->items)
return -EINVAL;
switch (ucontrol->value.enumerated.item[0]) {
case 0:
val = 0;
adau->dsp_bypass[stream] = false;
break;
default:
val = (adau->tdm_slot[stream] * 2) + 1;
adau->dsp_bypass[stream] = true;
break;
}
if (stream == SNDRV_PCM_STREAM_PLAYBACK)
reg = ADAU17X1_SERIAL_INPUT_ROUTE;
else
reg = ADAU17X1_SERIAL_OUTPUT_ROUTE;
change = snd_soc_component_test_bits(component, reg, 0xff, val);
if (change) {
update.kcontrol = kcontrol;
update.mask = 0xff;
update.reg = reg;
update.val = val;
snd_soc_dapm_mux_update_power(dapm, kcontrol,
ucontrol->value.enumerated.item[0], e, &update);
}
return change;
}
static int adau17x1_dsp_mux_enum_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
struct adau *adau = snd_soc_component_get_drvdata(component);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int stream = e->shift_l;
unsigned int reg, val;
int ret;
if (stream == SNDRV_PCM_STREAM_PLAYBACK)
reg = ADAU17X1_SERIAL_INPUT_ROUTE;
else
reg = ADAU17X1_SERIAL_OUTPUT_ROUTE;
ret = regmap_read(adau->regmap, reg, &val);
if (ret)
return ret;
if (val != 0)
val = 1;
ucontrol->value.enumerated.item[0] = val;
return 0;
}
#define DECLARE_ADAU17X1_DSP_MUX_CTRL(_name, _label, _stream, _text) \
const struct snd_kcontrol_new _name = \
SOC_DAPM_ENUM_EXT(_label, (const struct soc_enum)\
SOC_ENUM_SINGLE(SND_SOC_NOPM, _stream, \
ARRAY_SIZE(_text), _text), \
adau17x1_dsp_mux_enum_get, adau17x1_dsp_mux_enum_put)
static const char * const adau17x1_dac_mux_text[] = {
"DSP",
"AIFIN",
};
static const char * const adau17x1_capture_mux_text[] = {
"DSP",
"Decimator",
};
static DECLARE_ADAU17X1_DSP_MUX_CTRL(adau17x1_dac_mux, "DAC Playback Mux",
SNDRV_PCM_STREAM_PLAYBACK, adau17x1_dac_mux_text);
static DECLARE_ADAU17X1_DSP_MUX_CTRL(adau17x1_capture_mux, "Capture Mux",
SNDRV_PCM_STREAM_CAPTURE, adau17x1_capture_mux_text);
static const struct snd_soc_dapm_widget adau17x1_dsp_dapm_widgets[] = {
SND_SOC_DAPM_PGA("DSP", ADAU17X1_DSP_RUN, 0, 0, NULL, 0),
SND_SOC_DAPM_SIGGEN("DSP Siggen"),
SND_SOC_DAPM_MUX("DAC Playback Mux", SND_SOC_NOPM, 0, 0,
&adau17x1_dac_mux),
SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0,
&adau17x1_capture_mux),
};
static const struct snd_soc_dapm_route adau17x1_dsp_dapm_routes[] = {
{ "DAC Playback Mux", "DSP", "DSP" },
{ "DAC Playback Mux", "AIFIN", "Playback" },
{ "Left DAC Mode Mux", "Stereo", "DAC Playback Mux" },
{ "Left DAC Mode Mux", "Mono (L+R)", "DAC Playback Mux" },
{ "Left DAC Mode Mux", "Mono Left Channel (L+R)", "DAC Playback Mux" },
{ "Right DAC Mode Mux", "Stereo", "DAC Playback Mux" },
{ "Right DAC Mode Mux", "Mono (L+R)", "DAC Playback Mux" },
{ "Right DAC Mode Mux", "Mono Right Channel (L+R)", "DAC Playback Mux" },
{ "Capture Mux", "DSP", "DSP" },
{ "Capture Mux", "Decimator", "Left Decimator" },
{ "Capture Mux", "Decimator", "Right Decimator" },
{ "Capture", NULL, "Capture Mux" },
{ "DSP", NULL, "DSP Siggen" },
{ "DSP", NULL, "Left Decimator" },
{ "DSP", NULL, "Right Decimator" },
{ "DSP", NULL, "Playback" },
};
static const struct snd_soc_dapm_route adau17x1_no_dsp_dapm_routes[] = {
{ "Left DAC Mode Mux", "Stereo", "Playback" },
{ "Left DAC Mode Mux", "Mono (L+R)", "Playback" },
{ "Left DAC Mode Mux", "Mono Left Channel (L+R)", "Playback" },
{ "Right DAC Mode Mux", "Stereo", "Playback" },
{ "Right DAC Mode Mux", "Mono (L+R)", "Playback" },
{ "Right DAC Mode Mux", "Mono Right Channel (L+R)", "Playback" },
{ "Capture", NULL, "Left Decimator" },
{ "Capture", NULL, "Right Decimator" },
};
static bool adau17x1_has_dsp(struct adau *adau)
{
switch (adau->type) {
case ADAU1761:
case ADAU1381:
case ADAU1781:
return true;
default:
return false;
}
}
/* Chip has a DSP but we're pretending it doesn't. */
static bool adau17x1_has_disused_dsp(struct adau *adau)
{
switch (adau->type) {
case ADAU1761_AS_1361:
return true;
default:
return false;
}
}
static bool adau17x1_has_safeload(struct adau *adau)
{
switch (adau->type) {
case ADAU1761:
case ADAU1781:
return true;
default:
return false;
}
}
static int adau17x1_set_dai_pll(struct snd_soc_dai *dai, int pll_id,
int source, unsigned int freq_in, unsigned int freq_out)
{
struct snd_soc_component *component = dai->component;
struct adau *adau = snd_soc_component_get_drvdata(component);
int ret;
if (freq_in < 8000000 || freq_in > 27000000)
return -EINVAL;
ret = adau_calc_pll_cfg(freq_in, freq_out, adau->pll_regs);
if (ret < 0)
return ret;
/* The PLL register is 6 bytes long and can only be written at once. */
ret = regmap_raw_write(adau->regmap, ADAU17X1_PLL_CONTROL,
adau->pll_regs, ARRAY_SIZE(adau->pll_regs));
if (ret)
return ret;
adau->pll_freq = freq_out;
return 0;
}
static int adau17x1_set_dai_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(dai->component);
struct adau *adau = snd_soc_component_get_drvdata(dai->component);
bool is_pll;
bool was_pll;
switch (clk_id) {
case ADAU17X1_CLK_SRC_MCLK:
is_pll = false;
break;
case ADAU17X1_CLK_SRC_PLL_AUTO:
if (!adau->mclk)
return -EINVAL;
fallthrough;
case ADAU17X1_CLK_SRC_PLL:
is_pll = true;
break;
default:
return -EINVAL;
}
switch (adau->clk_src) {
case ADAU17X1_CLK_SRC_MCLK:
was_pll = false;
break;
case ADAU17X1_CLK_SRC_PLL:
case ADAU17X1_CLK_SRC_PLL_AUTO:
was_pll = true;
break;
default:
return -EINVAL;
}
adau->sysclk = freq;
if (is_pll != was_pll) {
if (is_pll) {
snd_soc_dapm_add_routes(dapm,
&adau17x1_dapm_pll_route, 1);
} else {
snd_soc_dapm_del_routes(dapm,
&adau17x1_dapm_pll_route, 1);
}
}
adau->clk_src = clk_id;
return 0;
}
static int adau17x1_auto_pll(struct snd_soc_dai *dai,
struct snd_pcm_hw_params *params)
{
struct adau *adau = snd_soc_dai_get_drvdata(dai);
unsigned int pll_rate;
switch (params_rate(params)) {
case 48000:
case 8000:
case 12000:
case 16000:
case 24000:
case 32000:
case 96000:
pll_rate = 48000 * 1024;
break;
case 44100:
case 7350:
case 11025:
case 14700:
case 22050:
case 29400:
case 88200:
pll_rate = 44100 * 1024;
break;
default:
return -EINVAL;
}
return adau17x1_set_dai_pll(dai, ADAU17X1_PLL, ADAU17X1_PLL_SRC_MCLK,
clk_get_rate(adau->mclk), pll_rate);
}
static int adau17x1_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct adau *adau = snd_soc_component_get_drvdata(component);
unsigned int val, div, dsp_div;
unsigned int freq;
int ret;
switch (adau->clk_src) {
case ADAU17X1_CLK_SRC_PLL_AUTO:
ret = adau17x1_auto_pll(dai, params);
if (ret)
return ret;
fallthrough;
case ADAU17X1_CLK_SRC_PLL:
freq = adau->pll_freq;
break;
default:
freq = adau->sysclk;
break;
}
if (freq % params_rate(params) != 0)
return -EINVAL;
switch (freq / params_rate(params)) {
case 1024: /* fs */
div = 0;
dsp_div = 1;
break;
case 6144: /* fs / 6 */
div = 1;
dsp_div = 6;
break;
case 4096: /* fs / 4 */
div = 2;
dsp_div = 5;
break;
case 3072: /* fs / 3 */
div = 3;
dsp_div = 4;
break;
case 2048: /* fs / 2 */
div = 4;
dsp_div = 3;
break;
case 1536: /* fs / 1.5 */
div = 5;
dsp_div = 2;
break;
case 512: /* fs / 0.5 */
div = 6;
dsp_div = 0;
break;
default:
return -EINVAL;
}
regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0,
ADAU17X1_CONVERTER0_CONVSR_MASK, div);
if (adau17x1_has_dsp(adau) || adau17x1_has_disused_dsp(adau))
regmap_write(adau->regmap, ADAU17X1_SERIAL_SAMPLING_RATE, div);
if (adau17x1_has_dsp(adau))
regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, dsp_div);
if (adau->sigmadsp) {
ret = adau17x1_setup_firmware(component, params_rate(params));
if (ret < 0)
return ret;
}
if (adau->dai_fmt != SND_SOC_DAIFMT_RIGHT_J)
return 0;
switch (params_width(params)) {
case 16:
val = ADAU17X1_SERIAL_PORT1_DELAY16;
break;
case 24:
val = ADAU17X1_SERIAL_PORT1_DELAY8;
break;
case 32:
val = ADAU17X1_SERIAL_PORT1_DELAY0;
break;
default:
return -EINVAL;
}
return regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT1,
ADAU17X1_SERIAL_PORT1_DELAY_MASK, val);
}
static int adau17x1_set_dai_fmt(struct snd_soc_dai *dai,
unsigned int fmt)
{
struct adau *adau = snd_soc_component_get_drvdata(dai->component);
unsigned int ctrl0, ctrl1;
unsigned int ctrl0_mask;
int lrclk_pol;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
ctrl0 = ADAU17X1_SERIAL_PORT0_MASTER;
adau->master = true;
break;
case SND_SOC_DAIFMT_CBC_CFC:
ctrl0 = 0;
adau->master = false;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
lrclk_pol = 0;
ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY1;
break;
case SND_SOC_DAIFMT_LEFT_J:
case SND_SOC_DAIFMT_RIGHT_J:
lrclk_pol = 1;
ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY0;
break;
case SND_SOC_DAIFMT_DSP_A:
lrclk_pol = 1;
ctrl0 |= ADAU17X1_SERIAL_PORT0_PULSE_MODE;
ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY1;
break;
case SND_SOC_DAIFMT_DSP_B:
lrclk_pol = 1;
ctrl0 |= ADAU17X1_SERIAL_PORT0_PULSE_MODE;
ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY0;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
ctrl0 |= ADAU17X1_SERIAL_PORT0_BCLK_POL;
break;
case SND_SOC_DAIFMT_NB_IF:
lrclk_pol = !lrclk_pol;
break;
case SND_SOC_DAIFMT_IB_IF:
ctrl0 |= ADAU17X1_SERIAL_PORT0_BCLK_POL;
lrclk_pol = !lrclk_pol;
break;
default:
return -EINVAL;
}
if (lrclk_pol)
ctrl0 |= ADAU17X1_SERIAL_PORT0_LRCLK_POL;
/* Set the mask to update all relevant bits in ADAU17X1_SERIAL_PORT0 */
ctrl0_mask = ADAU17X1_SERIAL_PORT0_MASTER |
ADAU17X1_SERIAL_PORT0_LRCLK_POL |
ADAU17X1_SERIAL_PORT0_BCLK_POL |
ADAU17X1_SERIAL_PORT0_PULSE_MODE;
regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT0, ctrl0_mask,
ctrl0);
regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT1,
ADAU17X1_SERIAL_PORT1_DELAY_MASK, ctrl1);
adau->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
return 0;
}
static int adau17x1_set_dai_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
{
struct adau *adau = snd_soc_component_get_drvdata(dai->component);
unsigned int ser_ctrl0, ser_ctrl1;
unsigned int conv_ctrl0, conv_ctrl1;
/* I2S mode */
if (slots == 0) {
slots = 2;
rx_mask = 3;
tx_mask = 3;
slot_width = 32;
}
switch (slots) {
case 2:
ser_ctrl0 = ADAU17X1_SERIAL_PORT0_STEREO;
break;
case 4:
ser_ctrl0 = ADAU17X1_SERIAL_PORT0_TDM4;
break;
case 8:
if (adau->type == ADAU1361)
return -EINVAL;
ser_ctrl0 = ADAU17X1_SERIAL_PORT0_TDM8;
break;
default:
return -EINVAL;
}
switch (slot_width * slots) {
case 32:
if (adau->type == ADAU1761 || adau->type == ADAU1761_AS_1361)
return -EINVAL;
ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK32;
break;
case 64:
ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK64;
break;
case 48:
ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK48;
break;
case 128:
ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK128;
break;
case 256:
if (adau->type == ADAU1361)
return -EINVAL;
ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK256;
break;
default:
return -EINVAL;
}
switch (rx_mask) {
case 0x03:
conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(1);
adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 0;
break;
case 0x0c:
conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(2);
adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 1;
break;
case 0x30:
conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(3);
adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 2;
break;
case 0xc0:
conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(4);
adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 3;
break;
default:
return -EINVAL;
}
switch (tx_mask) {
case 0x03:
conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(1);
adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 0;
break;
case 0x0c:
conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(2);
adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 1;
break;
case 0x30:
conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(3);
adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 2;
break;
case 0xc0:
conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(4);
adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 3;
break;
default:
return -EINVAL;
}
regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0,
ADAU17X1_CONVERTER0_DAC_PAIR_MASK, conv_ctrl0);
regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER1,
ADAU17X1_CONVERTER1_ADC_PAIR_MASK, conv_ctrl1);
regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT0,
ADAU17X1_SERIAL_PORT0_TDM_MASK, ser_ctrl0);
regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT1,
ADAU17X1_SERIAL_PORT1_BCLK_MASK, ser_ctrl1);
if (!adau17x1_has_dsp(adau) && !adau17x1_has_disused_dsp(adau))
return 0;
if (adau->dsp_bypass[SNDRV_PCM_STREAM_PLAYBACK]) {
regmap_write(adau->regmap, ADAU17X1_SERIAL_INPUT_ROUTE,
(adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] * 2) + 1);
}
if (adau->dsp_bypass[SNDRV_PCM_STREAM_CAPTURE]) {
regmap_write(adau->regmap, ADAU17X1_SERIAL_OUTPUT_ROUTE,
(adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] * 2) + 1);
}
return 0;
}
static int adau17x1_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct adau *adau = snd_soc_component_get_drvdata(dai->component);
if (adau->sigmadsp)
return sigmadsp_restrict_params(adau->sigmadsp, substream);
return 0;
}
const struct snd_soc_dai_ops adau17x1_dai_ops = {
.hw_params = adau17x1_hw_params,
.set_sysclk = adau17x1_set_dai_sysclk,
.set_fmt = adau17x1_set_dai_fmt,
.set_pll = adau17x1_set_dai_pll,
.set_tdm_slot = adau17x1_set_dai_tdm_slot,
.startup = adau17x1_startup,
};
EXPORT_SYMBOL_GPL(adau17x1_dai_ops);
int adau17x1_set_micbias_voltage(struct snd_soc_component *component,
enum adau17x1_micbias_voltage micbias)
{
struct adau *adau = snd_soc_component_get_drvdata(component);
switch (micbias) {
case ADAU17X1_MICBIAS_0_90_AVDD:
case ADAU17X1_MICBIAS_0_65_AVDD:
break;
default:
return -EINVAL;
}
return regmap_write(adau->regmap, ADAU17X1_MICBIAS, micbias << 2);
}
EXPORT_SYMBOL_GPL(adau17x1_set_micbias_voltage);
bool adau17x1_precious_register(struct device *dev, unsigned int reg)
{
/* SigmaDSP parameter memory */
if (reg < 0x400)
return true;
return false;
}
EXPORT_SYMBOL_GPL(adau17x1_precious_register);
bool adau17x1_readable_register(struct device *dev, unsigned int reg)
{
/* SigmaDSP parameter memory */
if (reg < 0x400)
return true;
switch (reg) {
case ADAU17X1_CLOCK_CONTROL:
case ADAU17X1_PLL_CONTROL:
case ADAU17X1_REC_POWER_MGMT:
case ADAU17X1_MICBIAS:
case ADAU17X1_SERIAL_PORT0:
case ADAU17X1_SERIAL_PORT1:
case ADAU17X1_CONVERTER0:
case ADAU17X1_CONVERTER1:
case ADAU17X1_LEFT_INPUT_DIGITAL_VOL:
case ADAU17X1_RIGHT_INPUT_DIGITAL_VOL:
case ADAU17X1_ADC_CONTROL:
case ADAU17X1_PLAY_POWER_MGMT:
case ADAU17X1_DAC_CONTROL0:
case ADAU17X1_DAC_CONTROL1:
case ADAU17X1_DAC_CONTROL2:
case ADAU17X1_SERIAL_PORT_PAD:
case ADAU17X1_CONTROL_PORT_PAD0:
case ADAU17X1_CONTROL_PORT_PAD1:
case ADAU17X1_DSP_SAMPLING_RATE:
case ADAU17X1_SERIAL_INPUT_ROUTE:
case ADAU17X1_SERIAL_OUTPUT_ROUTE:
case ADAU17X1_DSP_ENABLE:
case ADAU17X1_DSP_RUN:
case ADAU17X1_SERIAL_SAMPLING_RATE:
return true;
default:
break;
}
return false;
}
EXPORT_SYMBOL_GPL(adau17x1_readable_register);
bool adau17x1_volatile_register(struct device *dev, unsigned int reg)
{
/* SigmaDSP parameter and program memory */
if (reg < 0x4000)
return true;
switch (reg) {
/* The PLL register is 6 bytes long */
case ADAU17X1_PLL_CONTROL:
case ADAU17X1_PLL_CONTROL + 1:
case ADAU17X1_PLL_CONTROL + 2:
case ADAU17X1_PLL_CONTROL + 3:
case ADAU17X1_PLL_CONTROL + 4:
case ADAU17X1_PLL_CONTROL + 5:
return true;
default:
break;
}
return false;
}
EXPORT_SYMBOL_GPL(adau17x1_volatile_register);
static int adau17x1_setup_firmware(struct snd_soc_component *component,
unsigned int rate)
{
int ret;
int dspsr, dsp_run;
struct adau *adau = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
/* Check if sample rate is the same as before. If it is there is no
* point in performing the below steps as the call to
* sigmadsp_setup(...) will return directly when it finds the sample
* rate to be the same as before. By checking this we can prevent an
* audiable popping noise which occours when toggling DSP_RUN.
*/
if (adau->sigmadsp->current_samplerate == rate)
return 0;
snd_soc_dapm_mutex_lock(dapm);
ret = regmap_read(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, &dspsr);
if (ret)
goto err;
ret = regmap_read(adau->regmap, ADAU17X1_DSP_RUN, &dsp_run);
if (ret)
goto err;
regmap_write(adau->regmap, ADAU17X1_DSP_ENABLE, 1);
regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, 0xf);
regmap_write(adau->regmap, ADAU17X1_DSP_RUN, 0);
ret = sigmadsp_setup(adau->sigmadsp, rate);
if (ret) {
regmap_write(adau->regmap, ADAU17X1_DSP_ENABLE, 0);
goto err;
}
regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, dspsr);
regmap_write(adau->regmap, ADAU17X1_DSP_RUN, dsp_run);
err:
snd_soc_dapm_mutex_unlock(dapm);
return ret;
}
int adau17x1_add_widgets(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct adau *adau = snd_soc_component_get_drvdata(component);
int ret;
ret = snd_soc_add_component_controls(component, adau17x1_controls,
ARRAY_SIZE(adau17x1_controls));
if (ret)
return ret;
ret = snd_soc_dapm_new_controls(dapm, adau17x1_dapm_widgets,
ARRAY_SIZE(adau17x1_dapm_widgets));
if (ret)
return ret;
if (adau17x1_has_dsp(adau)) {
ret = snd_soc_dapm_new_controls(dapm, adau17x1_dsp_dapm_widgets,
ARRAY_SIZE(adau17x1_dsp_dapm_widgets));
if (ret)
return ret;
if (!adau->sigmadsp)
return 0;
ret = sigmadsp_attach(adau->sigmadsp, component);
if (ret) {
dev_err(component->dev, "Failed to attach firmware: %d\n",
ret);
return ret;
}
}
return 0;
}
EXPORT_SYMBOL_GPL(adau17x1_add_widgets);
int adau17x1_add_routes(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct adau *adau = snd_soc_component_get_drvdata(component);
int ret;
ret = snd_soc_dapm_add_routes(dapm, adau17x1_dapm_routes,
ARRAY_SIZE(adau17x1_dapm_routes));
if (ret)
return ret;
if (adau17x1_has_dsp(adau)) {
ret = snd_soc_dapm_add_routes(dapm, adau17x1_dsp_dapm_routes,
ARRAY_SIZE(adau17x1_dsp_dapm_routes));
} else {
ret = snd_soc_dapm_add_routes(dapm, adau17x1_no_dsp_dapm_routes,
ARRAY_SIZE(adau17x1_no_dsp_dapm_routes));
}
if (adau->clk_src != ADAU17X1_CLK_SRC_MCLK)
snd_soc_dapm_add_routes(dapm, &adau17x1_dapm_pll_route, 1);
return ret;
}
EXPORT_SYMBOL_GPL(adau17x1_add_routes);
int adau17x1_resume(struct snd_soc_component *component)
{
struct adau *adau = snd_soc_component_get_drvdata(component);
if (adau->switch_mode)
adau->switch_mode(component->dev);
regcache_sync(adau->regmap);
return 0;
}
EXPORT_SYMBOL_GPL(adau17x1_resume);
static int adau17x1_safeload(struct sigmadsp *sigmadsp, unsigned int addr,
const uint8_t bytes[], size_t len)
{
uint8_t buf[ADAU17X1_WORD_SIZE];
uint8_t data[ADAU17X1_SAFELOAD_DATA_SIZE];
unsigned int addr_offset;
unsigned int nbr_words;
int ret;
/* write data to safeload addresses. Check if len is not a multiple of
* 4 bytes, if so we need to zero pad.
*/
nbr_words = len / ADAU17X1_WORD_SIZE;
if ((len - nbr_words * ADAU17X1_WORD_SIZE) == 0) {
ret = regmap_raw_write(sigmadsp->control_data,
ADAU17X1_SAFELOAD_DATA, bytes, len);
} else {
nbr_words++;
memset(data, 0, ADAU17X1_SAFELOAD_DATA_SIZE);
memcpy(data, bytes, len);
ret = regmap_raw_write(sigmadsp->control_data,
ADAU17X1_SAFELOAD_DATA, data,
nbr_words * ADAU17X1_WORD_SIZE);
}
if (ret < 0)
return ret;
/* Write target address, target address is offset by 1 */
addr_offset = addr - 1;
put_unaligned_be32(addr_offset, buf);
ret = regmap_raw_write(sigmadsp->control_data,
ADAU17X1_SAFELOAD_TARGET_ADDRESS, buf, ADAU17X1_WORD_SIZE);
if (ret < 0)
return ret;
/* write nbr of words to trigger address */
put_unaligned_be32(nbr_words, buf);
ret = regmap_raw_write(sigmadsp->control_data,
ADAU17X1_SAFELOAD_TRIGGER, buf, ADAU17X1_WORD_SIZE);
if (ret < 0)
return ret;
return 0;
}
static const struct sigmadsp_ops adau17x1_sigmadsp_ops = {
.safeload = adau17x1_safeload,
};
int adau17x1_probe(struct device *dev, struct regmap *regmap,
enum adau17x1_type type, void (*switch_mode)(struct device *dev),
const char *firmware_name)
{
struct adau *adau;
int ret;
if (IS_ERR(regmap))
return PTR_ERR(regmap);
adau = devm_kzalloc(dev, sizeof(*adau), GFP_KERNEL);
if (!adau)
return -ENOMEM;
/* Clock is optional (for the driver) */
adau->mclk = devm_clk_get_optional(dev, "mclk");
if (IS_ERR(adau->mclk))
return PTR_ERR(adau->mclk);
if (adau->mclk) {
adau->clk_src = ADAU17X1_CLK_SRC_PLL_AUTO;
/*
* Any valid PLL output rate will work at this point, use one
* that is likely to be chosen later as well. The register will
* be written when the PLL is powered up for the first time.
*/
ret = adau_calc_pll_cfg(clk_get_rate(adau->mclk), 48000 * 1024,
adau->pll_regs);
if (ret < 0)
return ret;
ret = clk_prepare_enable(adau->mclk);
if (ret)
return ret;
}
adau->regmap = regmap;
adau->switch_mode = switch_mode;
adau->type = type;
dev_set_drvdata(dev, adau);
if (firmware_name) {
if (adau17x1_has_safeload(adau)) {
adau->sigmadsp = devm_sigmadsp_init_regmap(dev, regmap,
&adau17x1_sigmadsp_ops, firmware_name);
} else {
adau->sigmadsp = devm_sigmadsp_init_regmap(dev, regmap,
NULL, firmware_name);
}
if (IS_ERR(adau->sigmadsp)) {
dev_warn(dev, "Could not find firmware file: %ld\n",
PTR_ERR(adau->sigmadsp));
adau->sigmadsp = NULL;
}
}
if (switch_mode)
switch_mode(dev);
return 0;
}
EXPORT_SYMBOL_GPL(adau17x1_probe);
void adau17x1_remove(struct device *dev)
{
struct adau *adau = dev_get_drvdata(dev);
clk_disable_unprepare(adau->mclk);
}
EXPORT_SYMBOL_GPL(adau17x1_remove);
MODULE_DESCRIPTION("ASoC ADAU1X61/ADAU1X81 common code");
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/adau17x1.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* TS3A227E Autonomous Audio Accessory Detection and Configuration Switch
*
* Copyright (C) 2014 Google, Inc.
*/
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/input.h>
#include <linux/module.h>
#include <linux/of_gpio.h>
#include <linux/regmap.h>
#include <linux/acpi.h>
#include <sound/core.h>
#include <sound/jack.h>
#include <sound/soc.h>
#include "ts3a227e.h"
struct ts3a227e {
struct device *dev;
struct regmap *regmap;
struct snd_soc_jack *jack;
bool plugged;
bool mic_present;
unsigned int buttons_held;
int irq;
};
/* Button values to be reported on the jack */
static const int ts3a227e_buttons[] = {
SND_JACK_BTN_0,
SND_JACK_BTN_1,
SND_JACK_BTN_2,
SND_JACK_BTN_3,
};
#define TS3A227E_NUM_BUTTONS 4
#define TS3A227E_JACK_MASK (SND_JACK_HEADPHONE | \
SND_JACK_MICROPHONE | \
SND_JACK_BTN_0 | \
SND_JACK_BTN_1 | \
SND_JACK_BTN_2 | \
SND_JACK_BTN_3)
/* TS3A227E registers */
#define TS3A227E_REG_DEVICE_ID 0x00
#define TS3A227E_REG_INTERRUPT 0x01
#define TS3A227E_REG_KP_INTERRUPT 0x02
#define TS3A227E_REG_INTERRUPT_DISABLE 0x03
#define TS3A227E_REG_SETTING_1 0x04
#define TS3A227E_REG_SETTING_2 0x05
#define TS3A227E_REG_SETTING_3 0x06
#define TS3A227E_REG_SWITCH_CONTROL_1 0x07
#define TS3A227E_REG_SWITCH_CONTROL_2 0x08
#define TS3A227E_REG_SWITCH_STATUS_1 0x09
#define TS3A227E_REG_SWITCH_STATUS_2 0x0a
#define TS3A227E_REG_ACCESSORY_STATUS 0x0b
#define TS3A227E_REG_ADC_OUTPUT 0x0c
#define TS3A227E_REG_KP_THRESHOLD_1 0x0d
#define TS3A227E_REG_KP_THRESHOLD_2 0x0e
#define TS3A227E_REG_KP_THRESHOLD_3 0x0f
/* TS3A227E_REG_INTERRUPT 0x01 */
#define INS_REM_EVENT 0x01
#define DETECTION_COMPLETE_EVENT 0x02
/* TS3A227E_REG_KP_INTERRUPT 0x02 */
#define PRESS_MASK(idx) (0x01 << (2 * (idx)))
#define RELEASE_MASK(idx) (0x02 << (2 * (idx)))
/* TS3A227E_REG_INTERRUPT_DISABLE 0x03 */
#define INS_REM_INT_DISABLE 0x01
#define DETECTION_COMPLETE_INT_DISABLE 0x02
#define ADC_COMPLETE_INT_DISABLE 0x04
#define INTB_DISABLE 0x08
/* TS3A227E_REG_SETTING_1 0x4 */
#define DEBOUNCE_INSERTION_SETTING_SFT (0)
#define DEBOUNCE_INSERTION_SETTING_MASK (0x7 << DEBOUNCE_PRESS_SETTING_SFT)
/* TS3A227E_REG_SETTING_2 0x05 */
#define KP_ENABLE 0x04
/* TS3A227E_REG_SETTING_3 0x06 */
#define MICBIAS_SETTING_SFT 3
#define MICBIAS_SETTING_MASK (0x7 << MICBIAS_SETTING_SFT)
#define DEBOUNCE_RELEASE_SETTING_SFT 2
#define DEBOUNCE_RELEASE_SETTING_MASK (0x1 << DEBOUNCE_RELEASE_SETTING_SFT)
#define DEBOUNCE_PRESS_SETTING_SFT 0
#define DEBOUNCE_PRESS_SETTING_MASK (0x3 << DEBOUNCE_PRESS_SETTING_SFT)
/* TS3A227E_REG_ACCESSORY_STATUS 0x0b */
#define TYPE_3_POLE 0x01
#define TYPE_4_POLE_OMTP 0x02
#define TYPE_4_POLE_STANDARD 0x04
#define JACK_INSERTED 0x08
#define EITHER_MIC_MASK (TYPE_4_POLE_OMTP | TYPE_4_POLE_STANDARD)
static const struct reg_default ts3a227e_reg_defaults[] = {
{ TS3A227E_REG_DEVICE_ID, 0x10 },
{ TS3A227E_REG_INTERRUPT, 0x00 },
{ TS3A227E_REG_KP_INTERRUPT, 0x00 },
{ TS3A227E_REG_INTERRUPT_DISABLE, 0x08 },
{ TS3A227E_REG_SETTING_1, 0x23 },
{ TS3A227E_REG_SETTING_2, 0x00 },
{ TS3A227E_REG_SETTING_3, 0x0e },
{ TS3A227E_REG_SWITCH_CONTROL_1, 0x00 },
{ TS3A227E_REG_SWITCH_CONTROL_2, 0x00 },
{ TS3A227E_REG_SWITCH_STATUS_1, 0x0c },
{ TS3A227E_REG_SWITCH_STATUS_2, 0x00 },
{ TS3A227E_REG_ACCESSORY_STATUS, 0x00 },
{ TS3A227E_REG_ADC_OUTPUT, 0x00 },
{ TS3A227E_REG_KP_THRESHOLD_1, 0x20 },
{ TS3A227E_REG_KP_THRESHOLD_2, 0x40 },
{ TS3A227E_REG_KP_THRESHOLD_3, 0x68 },
};
static bool ts3a227e_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TS3A227E_REG_DEVICE_ID ... TS3A227E_REG_KP_THRESHOLD_3:
return true;
default:
return false;
}
}
static bool ts3a227e_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TS3A227E_REG_INTERRUPT_DISABLE ... TS3A227E_REG_SWITCH_CONTROL_2:
case TS3A227E_REG_KP_THRESHOLD_1 ... TS3A227E_REG_KP_THRESHOLD_3:
return true;
default:
return false;
}
}
static bool ts3a227e_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TS3A227E_REG_INTERRUPT ... TS3A227E_REG_INTERRUPT_DISABLE:
case TS3A227E_REG_SETTING_1 ... TS3A227E_REG_SETTING_2:
case TS3A227E_REG_SWITCH_STATUS_1 ... TS3A227E_REG_ADC_OUTPUT:
return true;
default:
return false;
}
}
static void ts3a227e_jack_report(struct ts3a227e *ts3a227e)
{
unsigned int i;
int report = 0;
if (!ts3a227e->jack)
return;
if (ts3a227e->plugged)
report = SND_JACK_HEADPHONE;
if (ts3a227e->mic_present)
report |= SND_JACK_MICROPHONE;
for (i = 0; i < TS3A227E_NUM_BUTTONS; i++) {
if (ts3a227e->buttons_held & (1 << i))
report |= ts3a227e_buttons[i];
}
snd_soc_jack_report(ts3a227e->jack, report, TS3A227E_JACK_MASK);
}
static void ts3a227e_new_jack_state(struct ts3a227e *ts3a227e, unsigned acc_reg)
{
bool plugged, mic_present;
plugged = !!(acc_reg & JACK_INSERTED);
mic_present = plugged && !!(acc_reg & EITHER_MIC_MASK);
ts3a227e->plugged = plugged;
if (mic_present != ts3a227e->mic_present) {
ts3a227e->mic_present = mic_present;
ts3a227e->buttons_held = 0;
if (mic_present) {
/* Enable key press detection. */
regmap_update_bits(ts3a227e->regmap,
TS3A227E_REG_SETTING_2,
KP_ENABLE, KP_ENABLE);
}
}
}
static irqreturn_t ts3a227e_interrupt(int irq, void *data)
{
struct ts3a227e *ts3a227e = (struct ts3a227e *)data;
struct regmap *regmap = ts3a227e->regmap;
unsigned int int_reg, kp_int_reg, acc_reg, i;
struct device *dev = ts3a227e->dev;
int ret;
/* Check for plug/unplug. */
ret = regmap_read(regmap, TS3A227E_REG_INTERRUPT, &int_reg);
if (ret) {
dev_err(dev, "failed to clear interrupt ret=%d\n", ret);
return IRQ_NONE;
}
if (int_reg & (DETECTION_COMPLETE_EVENT | INS_REM_EVENT)) {
regmap_read(regmap, TS3A227E_REG_ACCESSORY_STATUS, &acc_reg);
ts3a227e_new_jack_state(ts3a227e, acc_reg);
}
/* Report any key events. */
ret = regmap_read(regmap, TS3A227E_REG_KP_INTERRUPT, &kp_int_reg);
if (ret) {
dev_err(dev, "failed to clear key interrupt ret=%d\n", ret);
return IRQ_NONE;
}
for (i = 0; i < TS3A227E_NUM_BUTTONS; i++) {
if (kp_int_reg & PRESS_MASK(i))
ts3a227e->buttons_held |= (1 << i);
if (kp_int_reg & RELEASE_MASK(i))
ts3a227e->buttons_held &= ~(1 << i);
}
ts3a227e_jack_report(ts3a227e);
return IRQ_HANDLED;
}
/**
* ts3a227e_enable_jack_detect - Specify a jack for event reporting
*
* @component: component to register the jack with
* @jack: jack to use to report headset and button events on
*
* After this function has been called the headset insert/remove and button
* events 0-3 will be routed to the given jack. Jack can be null to stop
* reporting.
*/
int ts3a227e_enable_jack_detect(struct snd_soc_component *component,
struct snd_soc_jack *jack)
{
struct ts3a227e *ts3a227e = snd_soc_component_get_drvdata(component);
snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOICECOMMAND);
snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEUP);
snd_jack_set_key(jack->jack, SND_JACK_BTN_3, KEY_VOLUMEDOWN);
ts3a227e->jack = jack;
ts3a227e_jack_report(ts3a227e);
return 0;
}
EXPORT_SYMBOL_GPL(ts3a227e_enable_jack_detect);
static int ts3a227e_set_jack(struct snd_soc_component *component,
struct snd_soc_jack *jack, void *data)
{
if (jack == NULL)
return -EINVAL;
return ts3a227e_enable_jack_detect(component, jack);
}
static int ts3a227e_get_jack_type(struct snd_soc_component *component)
{
return SND_JACK_HEADSET;
}
static const struct snd_soc_component_driver ts3a227e_soc_driver = {
.name = "ti,ts3a227e",
.set_jack = ts3a227e_set_jack,
.get_jack_type = ts3a227e_get_jack_type,
};
static const struct regmap_config ts3a227e_regmap_config = {
.val_bits = 8,
.reg_bits = 8,
.max_register = TS3A227E_REG_KP_THRESHOLD_3,
.readable_reg = ts3a227e_readable_reg,
.writeable_reg = ts3a227e_writeable_reg,
.volatile_reg = ts3a227e_volatile_reg,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = ts3a227e_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(ts3a227e_reg_defaults),
};
static int ts3a227e_parse_device_property(struct ts3a227e *ts3a227e,
struct device *dev)
{
u32 value;
u32 value_ms;
u32 setting3_value = 0;
u32 setting3_mask = 0;
int err;
err = device_property_read_u32(dev, "ti,micbias", &value);
if (!err) {
setting3_mask = MICBIAS_SETTING_MASK;
setting3_value = (value << MICBIAS_SETTING_SFT) &
MICBIAS_SETTING_MASK;
}
err = device_property_read_u32(dev, "ti,debounce-release-ms",
&value_ms);
if (!err) {
value = (value_ms > 10);
setting3_mask |= DEBOUNCE_RELEASE_SETTING_MASK;
setting3_value |= (value << DEBOUNCE_RELEASE_SETTING_SFT) &
DEBOUNCE_RELEASE_SETTING_MASK;
}
err = device_property_read_u32(dev, "ti,debounce-press-ms", &value_ms);
if (!err) {
value = (value_ms + 20) / 40;
if (value > 3)
value = 3;
setting3_mask |= DEBOUNCE_PRESS_SETTING_MASK;
setting3_value |= (value << DEBOUNCE_PRESS_SETTING_SFT) &
DEBOUNCE_PRESS_SETTING_MASK;
}
if (setting3_mask)
regmap_update_bits(ts3a227e->regmap, TS3A227E_REG_SETTING_3,
setting3_mask, setting3_value);
err = device_property_read_u32(dev, "ti,debounce-insertion-ms",
&value_ms);
if (!err) {
if (value_ms < 165)
value = (value_ms + 15) / 30;
else if (value_ms < 1500)
value = 6;
else
value = 7;
regmap_update_bits(ts3a227e->regmap, TS3A227E_REG_SETTING_1,
DEBOUNCE_INSERTION_SETTING_MASK,
(value << DEBOUNCE_INSERTION_SETTING_SFT) &
DEBOUNCE_INSERTION_SETTING_MASK);
}
return 0;
}
static int ts3a227e_i2c_probe(struct i2c_client *i2c)
{
struct ts3a227e *ts3a227e;
struct device *dev = &i2c->dev;
int ret;
unsigned int acc_reg;
ts3a227e = devm_kzalloc(&i2c->dev, sizeof(*ts3a227e), GFP_KERNEL);
if (ts3a227e == NULL)
return -ENOMEM;
i2c_set_clientdata(i2c, ts3a227e);
ts3a227e->dev = dev;
ts3a227e->irq = i2c->irq;
ts3a227e->regmap = devm_regmap_init_i2c(i2c, &ts3a227e_regmap_config);
if (IS_ERR(ts3a227e->regmap))
return PTR_ERR(ts3a227e->regmap);
ret = ts3a227e_parse_device_property(ts3a227e, dev);
if (ret) {
dev_err(dev, "Failed to parse device property: %d\n", ret);
return ret;
}
ret = devm_request_threaded_irq(dev, i2c->irq, NULL, ts3a227e_interrupt,
IRQF_TRIGGER_LOW | IRQF_ONESHOT,
"TS3A227E", ts3a227e);
if (ret) {
dev_err(dev, "Cannot request irq %d (%d)\n", i2c->irq, ret);
return ret;
}
ret = devm_snd_soc_register_component(&i2c->dev, &ts3a227e_soc_driver,
NULL, 0);
if (ret)
return ret;
/* Enable interrupts except for ADC complete. */
regmap_update_bits(ts3a227e->regmap, TS3A227E_REG_INTERRUPT_DISABLE,
INTB_DISABLE | ADC_COMPLETE_INT_DISABLE,
ADC_COMPLETE_INT_DISABLE);
/* Read jack status because chip might not trigger interrupt at boot. */
regmap_read(ts3a227e->regmap, TS3A227E_REG_ACCESSORY_STATUS, &acc_reg);
ts3a227e_new_jack_state(ts3a227e, acc_reg);
ts3a227e_jack_report(ts3a227e);
return 0;
}
#ifdef CONFIG_PM_SLEEP
static int ts3a227e_suspend(struct device *dev)
{
struct ts3a227e *ts3a227e = dev_get_drvdata(dev);
dev_dbg(ts3a227e->dev, "suspend disable irq\n");
disable_irq(ts3a227e->irq);
return 0;
}
static int ts3a227e_resume(struct device *dev)
{
struct ts3a227e *ts3a227e = dev_get_drvdata(dev);
dev_dbg(ts3a227e->dev, "resume enable irq\n");
enable_irq(ts3a227e->irq);
return 0;
}
#endif
static const struct dev_pm_ops ts3a227e_pm = {
SET_SYSTEM_SLEEP_PM_OPS(ts3a227e_suspend, ts3a227e_resume)
};
static const struct i2c_device_id ts3a227e_i2c_ids[] = {
{ "ts3a227e", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, ts3a227e_i2c_ids);
#ifdef CONFIG_OF
static const struct of_device_id ts3a227e_of_match[] = {
{ .compatible = "ti,ts3a227e", },
{ }
};
MODULE_DEVICE_TABLE(of, ts3a227e_of_match);
#endif
#ifdef CONFIG_ACPI
static struct acpi_device_id ts3a227e_acpi_match[] = {
{ "104C227E", 0 },
{},
};
MODULE_DEVICE_TABLE(acpi, ts3a227e_acpi_match);
#endif
static struct i2c_driver ts3a227e_driver = {
.driver = {
.name = "ts3a227e",
.pm = &ts3a227e_pm,
.of_match_table = of_match_ptr(ts3a227e_of_match),
.acpi_match_table = ACPI_PTR(ts3a227e_acpi_match),
},
.probe = ts3a227e_i2c_probe,
.id_table = ts3a227e_i2c_ids,
};
module_i2c_driver(ts3a227e_driver);
MODULE_DESCRIPTION("ASoC ts3a227e driver");
MODULE_AUTHOR("Dylan Reid <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/ts3a227e.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8776.c -- WM8776 ALSA SoC Audio driver
*
* Copyright 2009-12 Wolfson Microelectronics plc
*
* Author: Mark Brown <[email protected]>
*
* TODO: Input ALC/limiter support
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "wm8776.h"
enum wm8776_chip_type {
WM8775 = 1,
WM8776,
};
/* codec private data */
struct wm8776_priv {
struct regmap *regmap;
int sysclk[2];
};
static const struct reg_default wm8776_reg_defaults[] = {
{ 0, 0x79 },
{ 1, 0x79 },
{ 2, 0x79 },
{ 3, 0xff },
{ 4, 0xff },
{ 5, 0xff },
{ 6, 0x00 },
{ 7, 0x90 },
{ 8, 0x00 },
{ 9, 0x00 },
{ 10, 0x22 },
{ 11, 0x22 },
{ 12, 0x22 },
{ 13, 0x08 },
{ 14, 0xcf },
{ 15, 0xcf },
{ 16, 0x7b },
{ 17, 0x00 },
{ 18, 0x32 },
{ 19, 0x00 },
{ 20, 0xa6 },
{ 21, 0x01 },
{ 22, 0x01 },
};
static bool wm8776_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8776_RESET:
return true;
default:
return false;
}
}
static int wm8776_reset(struct snd_soc_component *component)
{
return snd_soc_component_write(component, WM8776_RESET, 0);
}
static const DECLARE_TLV_DB_SCALE(hp_tlv, -12100, 100, 1);
static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
static const DECLARE_TLV_DB_SCALE(adc_tlv, -10350, 50, 1);
static const struct snd_kcontrol_new wm8776_snd_controls[] = {
SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8776_HPLVOL, WM8776_HPRVOL,
0, 127, 0, hp_tlv),
SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8776_DACLVOL, WM8776_DACRVOL,
0, 255, 0, dac_tlv),
SOC_SINGLE("Digital Playback ZC Switch", WM8776_DACCTRL1, 0, 1, 0),
SOC_SINGLE("Deemphasis Switch", WM8776_DACCTRL2, 0, 1, 0),
SOC_DOUBLE_R_TLV("Capture Volume", WM8776_ADCLVOL, WM8776_ADCRVOL,
0, 255, 0, adc_tlv),
SOC_DOUBLE("Capture Switch", WM8776_ADCMUX, 7, 6, 1, 1),
SOC_DOUBLE_R("Capture ZC Switch", WM8776_ADCLVOL, WM8776_ADCRVOL, 8, 1, 0),
SOC_SINGLE("Capture HPF Switch", WM8776_ADCIFCTRL, 8, 1, 1),
};
static const struct snd_kcontrol_new inmix_controls[] = {
SOC_DAPM_SINGLE("AIN1 Switch", WM8776_ADCMUX, 0, 1, 0),
SOC_DAPM_SINGLE("AIN2 Switch", WM8776_ADCMUX, 1, 1, 0),
SOC_DAPM_SINGLE("AIN3 Switch", WM8776_ADCMUX, 2, 1, 0),
SOC_DAPM_SINGLE("AIN4 Switch", WM8776_ADCMUX, 3, 1, 0),
SOC_DAPM_SINGLE("AIN5 Switch", WM8776_ADCMUX, 4, 1, 0),
};
static const struct snd_kcontrol_new outmix_controls[] = {
SOC_DAPM_SINGLE("DAC Switch", WM8776_OUTMUX, 0, 1, 0),
SOC_DAPM_SINGLE("AUX Switch", WM8776_OUTMUX, 1, 1, 0),
SOC_DAPM_SINGLE("Bypass Switch", WM8776_OUTMUX, 2, 1, 0),
};
static const struct snd_soc_dapm_widget wm8776_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("AUX"),
SND_SOC_DAPM_INPUT("AIN1"),
SND_SOC_DAPM_INPUT("AIN2"),
SND_SOC_DAPM_INPUT("AIN3"),
SND_SOC_DAPM_INPUT("AIN4"),
SND_SOC_DAPM_INPUT("AIN5"),
SND_SOC_DAPM_MIXER("Input Mixer", WM8776_PWRDOWN, 6, 1,
inmix_controls, ARRAY_SIZE(inmix_controls)),
SND_SOC_DAPM_ADC("ADC", "Capture", WM8776_PWRDOWN, 1, 1),
SND_SOC_DAPM_DAC("DAC", "Playback", WM8776_PWRDOWN, 2, 1),
SND_SOC_DAPM_MIXER("Output Mixer", SND_SOC_NOPM, 0, 0,
outmix_controls, ARRAY_SIZE(outmix_controls)),
SND_SOC_DAPM_PGA("Headphone PGA", WM8776_PWRDOWN, 3, 1, NULL, 0),
SND_SOC_DAPM_OUTPUT("VOUT"),
SND_SOC_DAPM_OUTPUT("HPOUTL"),
SND_SOC_DAPM_OUTPUT("HPOUTR"),
};
static const struct snd_soc_dapm_route routes[] = {
{ "Input Mixer", "AIN1 Switch", "AIN1" },
{ "Input Mixer", "AIN2 Switch", "AIN2" },
{ "Input Mixer", "AIN3 Switch", "AIN3" },
{ "Input Mixer", "AIN4 Switch", "AIN4" },
{ "Input Mixer", "AIN5 Switch", "AIN5" },
{ "ADC", NULL, "Input Mixer" },
{ "Output Mixer", "DAC Switch", "DAC" },
{ "Output Mixer", "AUX Switch", "AUX" },
{ "Output Mixer", "Bypass Switch", "Input Mixer" },
{ "VOUT", NULL, "Output Mixer" },
{ "Headphone PGA", NULL, "Output Mixer" },
{ "HPOUTL", NULL, "Headphone PGA" },
{ "HPOUTR", NULL, "Headphone PGA" },
};
static int wm8776_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
int reg, iface, master;
switch (dai->driver->id) {
case WM8776_DAI_DAC:
reg = WM8776_DACIFCTRL;
master = 0x80;
break;
case WM8776_DAI_ADC:
reg = WM8776_ADCIFCTRL;
master = 0x100;
break;
default:
return -EINVAL;
}
iface = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
break;
case SND_SOC_DAIFMT_CBS_CFS:
master = 0;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface |= 0x0002;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
iface |= 0x0001;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
iface |= 0x00c;
break;
case SND_SOC_DAIFMT_IB_NF:
iface |= 0x008;
break;
case SND_SOC_DAIFMT_NB_IF:
iface |= 0x004;
break;
default:
return -EINVAL;
}
/* Finally, write out the values */
snd_soc_component_update_bits(component, reg, 0xf, iface);
snd_soc_component_update_bits(component, WM8776_MSTRCTRL, 0x180, master);
return 0;
}
static int mclk_ratios[] = {
128,
192,
256,
384,
512,
768,
};
static int wm8776_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm8776_priv *wm8776 = snd_soc_component_get_drvdata(component);
int iface_reg, iface;
int ratio_shift, master;
int i;
switch (dai->driver->id) {
case WM8776_DAI_DAC:
iface_reg = WM8776_DACIFCTRL;
master = 0x80;
ratio_shift = 4;
break;
case WM8776_DAI_ADC:
iface_reg = WM8776_ADCIFCTRL;
master = 0x100;
ratio_shift = 0;
break;
default:
return -EINVAL;
}
/* Set word length */
switch (params_width(params)) {
case 16:
iface = 0;
break;
case 20:
iface = 0x10;
break;
case 24:
iface = 0x20;
break;
case 32:
iface = 0x30;
break;
default:
dev_err(component->dev, "Unsupported sample size: %i\n",
params_width(params));
return -EINVAL;
}
/* Only need to set MCLK/LRCLK ratio if we're master */
if (snd_soc_component_read(component, WM8776_MSTRCTRL) & master) {
for (i = 0; i < ARRAY_SIZE(mclk_ratios); i++) {
if (wm8776->sysclk[dai->driver->id] / params_rate(params)
== mclk_ratios[i])
break;
}
if (i == ARRAY_SIZE(mclk_ratios)) {
dev_err(component->dev,
"Unable to configure MCLK ratio %d/%d\n",
wm8776->sysclk[dai->driver->id], params_rate(params));
return -EINVAL;
}
dev_dbg(component->dev, "MCLK is %dfs\n", mclk_ratios[i]);
snd_soc_component_update_bits(component, WM8776_MSTRCTRL,
0x7 << ratio_shift, i << ratio_shift);
} else {
dev_dbg(component->dev, "DAI in slave mode\n");
}
snd_soc_component_update_bits(component, iface_reg, 0x30, iface);
return 0;
}
static int wm8776_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
return snd_soc_component_write(component, WM8776_DACMUTE, !!mute);
}
static int wm8776_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct wm8776_priv *wm8776 = snd_soc_component_get_drvdata(component);
if (WARN_ON(dai->driver->id >= ARRAY_SIZE(wm8776->sysclk)))
return -EINVAL;
wm8776->sysclk[dai->driver->id] = freq;
return 0;
}
static int wm8776_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct wm8776_priv *wm8776 = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
regcache_sync(wm8776->regmap);
/* Disable the global powerdown; DAPM does the rest */
snd_soc_component_update_bits(component, WM8776_PWRDOWN, 1, 0);
}
break;
case SND_SOC_BIAS_OFF:
snd_soc_component_update_bits(component, WM8776_PWRDOWN, 1, 1);
break;
}
return 0;
}
#define WM8776_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops wm8776_dac_ops = {
.mute_stream = wm8776_mute,
.hw_params = wm8776_hw_params,
.set_fmt = wm8776_set_fmt,
.set_sysclk = wm8776_set_sysclk,
.no_capture_mute = 1,
};
static const struct snd_soc_dai_ops wm8776_adc_ops = {
.hw_params = wm8776_hw_params,
.set_fmt = wm8776_set_fmt,
.set_sysclk = wm8776_set_sysclk,
};
static struct snd_soc_dai_driver wm8776_dai[] = {
{
.name = "wm8776-hifi-playback",
.id = WM8776_DAI_DAC,
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.rate_min = 32000,
.rate_max = 192000,
.formats = WM8776_FORMATS,
},
.ops = &wm8776_dac_ops,
},
{
.name = "wm8776-hifi-capture",
.id = WM8776_DAI_ADC,
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.rate_min = 32000,
.rate_max = 96000,
.formats = WM8776_FORMATS,
},
.ops = &wm8776_adc_ops,
},
};
static int wm8776_probe(struct snd_soc_component *component)
{
int ret = 0;
ret = wm8776_reset(component);
if (ret < 0) {
dev_err(component->dev, "Failed to issue reset: %d\n", ret);
return ret;
}
/* Latch the update bits; right channel only since we always
* update both. */
snd_soc_component_update_bits(component, WM8776_HPRVOL, 0x100, 0x100);
snd_soc_component_update_bits(component, WM8776_DACRVOL, 0x100, 0x100);
return ret;
}
static const struct snd_soc_component_driver soc_component_dev_wm8776 = {
.probe = wm8776_probe,
.set_bias_level = wm8776_set_bias_level,
.controls = wm8776_snd_controls,
.num_controls = ARRAY_SIZE(wm8776_snd_controls),
.dapm_widgets = wm8776_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8776_dapm_widgets),
.dapm_routes = routes,
.num_dapm_routes = ARRAY_SIZE(routes),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct of_device_id wm8776_of_match[] = {
{ .compatible = "wlf,wm8776", },
{ }
};
MODULE_DEVICE_TABLE(of, wm8776_of_match);
static const struct regmap_config wm8776_regmap = {
.reg_bits = 7,
.val_bits = 9,
.max_register = WM8776_RESET,
.reg_defaults = wm8776_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8776_reg_defaults),
.cache_type = REGCACHE_MAPLE,
.volatile_reg = wm8776_volatile,
};
#if defined(CONFIG_SPI_MASTER)
static int wm8776_spi_probe(struct spi_device *spi)
{
struct wm8776_priv *wm8776;
int ret;
wm8776 = devm_kzalloc(&spi->dev, sizeof(struct wm8776_priv),
GFP_KERNEL);
if (wm8776 == NULL)
return -ENOMEM;
wm8776->regmap = devm_regmap_init_spi(spi, &wm8776_regmap);
if (IS_ERR(wm8776->regmap))
return PTR_ERR(wm8776->regmap);
spi_set_drvdata(spi, wm8776);
ret = devm_snd_soc_register_component(&spi->dev,
&soc_component_dev_wm8776, wm8776_dai, ARRAY_SIZE(wm8776_dai));
return ret;
}
static struct spi_driver wm8776_spi_driver = {
.driver = {
.name = "wm8776",
.of_match_table = wm8776_of_match,
},
.probe = wm8776_spi_probe,
};
#endif /* CONFIG_SPI_MASTER */
#if IS_ENABLED(CONFIG_I2C)
static int wm8776_i2c_probe(struct i2c_client *i2c)
{
struct wm8776_priv *wm8776;
int ret;
wm8776 = devm_kzalloc(&i2c->dev, sizeof(struct wm8776_priv),
GFP_KERNEL);
if (wm8776 == NULL)
return -ENOMEM;
wm8776->regmap = devm_regmap_init_i2c(i2c, &wm8776_regmap);
if (IS_ERR(wm8776->regmap))
return PTR_ERR(wm8776->regmap);
i2c_set_clientdata(i2c, wm8776);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_wm8776, wm8776_dai, ARRAY_SIZE(wm8776_dai));
return ret;
}
static const struct i2c_device_id wm8776_i2c_id[] = {
{ "wm8775", WM8775 },
{ "wm8776", WM8776 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8776_i2c_id);
static struct i2c_driver wm8776_i2c_driver = {
.driver = {
.name = "wm8776",
.of_match_table = wm8776_of_match,
},
.probe = wm8776_i2c_probe,
.id_table = wm8776_i2c_id,
};
#endif
static int __init wm8776_modinit(void)
{
int ret = 0;
#if IS_ENABLED(CONFIG_I2C)
ret = i2c_add_driver(&wm8776_i2c_driver);
if (ret != 0) {
printk(KERN_ERR "Failed to register wm8776 I2C driver: %d\n",
ret);
}
#endif
#if defined(CONFIG_SPI_MASTER)
ret = spi_register_driver(&wm8776_spi_driver);
if (ret != 0) {
printk(KERN_ERR "Failed to register wm8776 SPI driver: %d\n",
ret);
}
#endif
return ret;
}
module_init(wm8776_modinit);
static void __exit wm8776_exit(void)
{
#if IS_ENABLED(CONFIG_I2C)
i2c_del_driver(&wm8776_i2c_driver);
#endif
#if defined(CONFIG_SPI_MASTER)
spi_unregister_driver(&wm8776_spi_driver);
#endif
}
module_exit(wm8776_exit);
MODULE_DESCRIPTION("ASoC WM8776 driver");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8776.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// rt715-sdca.c -- rt715 ALSA SoC audio driver
//
// Copyright(c) 2020 Realtek Semiconductor Corp.
//
//
//
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pm_runtime.h>
#include <linux/pm.h>
#include <linux/soundwire/sdw.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/sdw.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <linux/soundwire/sdw_registers.h>
#include "rt715-sdca.h"
static int rt715_sdca_index_write(struct rt715_sdca_priv *rt715,
unsigned int nid, unsigned int reg, unsigned int value)
{
struct regmap *regmap = rt715->mbq_regmap;
unsigned int addr;
int ret;
addr = (nid << 20) | reg;
ret = regmap_write(regmap, addr, value);
if (ret < 0)
dev_err(&rt715->slave->dev,
"Failed to set private value: %08x <= %04x %d\n", ret, addr,
value);
return ret;
}
static int rt715_sdca_index_read(struct rt715_sdca_priv *rt715,
unsigned int nid, unsigned int reg, unsigned int *value)
{
struct regmap *regmap = rt715->mbq_regmap;
unsigned int addr;
int ret;
addr = (nid << 20) | reg;
ret = regmap_read(regmap, addr, value);
if (ret < 0)
dev_err(&rt715->slave->dev,
"Failed to get private value: %06x => %04x ret=%d\n",
addr, *value, ret);
return ret;
}
static int rt715_sdca_index_update_bits(struct rt715_sdca_priv *rt715,
unsigned int nid, unsigned int reg, unsigned int mask, unsigned int val)
{
unsigned int tmp;
int ret;
ret = rt715_sdca_index_read(rt715, nid, reg, &tmp);
if (ret < 0)
return ret;
set_mask_bits(&tmp, mask, val);
return rt715_sdca_index_write(rt715, nid, reg, tmp);
}
static inline unsigned int rt715_sdca_vol_gain(unsigned int u_ctrl_val,
unsigned int vol_max, unsigned int vol_gain_sft)
{
unsigned int val;
if (u_ctrl_val > vol_max)
u_ctrl_val = vol_max;
val = u_ctrl_val;
u_ctrl_val =
((abs(u_ctrl_val - vol_gain_sft) * RT715_SDCA_DB_STEP) << 8) / 1000;
if (val <= vol_gain_sft) {
u_ctrl_val = ~u_ctrl_val;
u_ctrl_val += 1;
}
u_ctrl_val &= 0xffff;
return u_ctrl_val;
}
static inline unsigned int rt715_sdca_boost_gain(unsigned int u_ctrl_val,
unsigned int b_max, unsigned int b_gain_sft)
{
if (u_ctrl_val > b_max)
u_ctrl_val = b_max;
return (u_ctrl_val * 10) << b_gain_sft;
}
static inline unsigned int rt715_sdca_get_gain(unsigned int reg_val,
unsigned int gain_sft)
{
unsigned int neg_flag = 0;
if (reg_val & BIT(15)) {
reg_val = ~(reg_val - 1) & 0xffff;
neg_flag = 1;
}
reg_val *= 1000;
reg_val >>= 8;
if (neg_flag)
reg_val = gain_sft - reg_val / RT715_SDCA_DB_STEP;
else
reg_val = gain_sft + reg_val / RT715_SDCA_DB_STEP;
return reg_val;
}
/* SDCA Volume/Boost control */
static int rt715_sdca_set_amp_gain_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct rt715_sdca_priv *rt715 = snd_soc_component_get_drvdata(component);
unsigned int gain_val, i, k_changed = 0;
int ret;
for (i = 0; i < 2; i++) {
if (ucontrol->value.integer.value[i] != rt715->kctl_2ch_orig[i]) {
k_changed = 1;
break;
}
}
for (i = 0; i < 2; i++) {
rt715->kctl_2ch_orig[i] = ucontrol->value.integer.value[i];
gain_val =
rt715_sdca_vol_gain(ucontrol->value.integer.value[i], mc->max,
mc->shift);
ret = regmap_write(rt715->mbq_regmap, mc->reg + i, gain_val);
if (ret != 0) {
dev_err(component->dev, "Failed to write 0x%x=0x%x\n",
mc->reg + i, gain_val);
return ret;
}
}
return k_changed;
}
static int rt715_sdca_set_amp_gain_4ch_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt715_sdca_priv *rt715 = snd_soc_component_get_drvdata(component);
struct rt715_sdca_kcontrol_private *p =
(struct rt715_sdca_kcontrol_private *)kcontrol->private_value;
unsigned int reg_base = p->reg_base, k_changed = 0;
const unsigned int gain_sft = 0x2f;
unsigned int gain_val, i;
int ret;
for (i = 0; i < 4; i++) {
if (ucontrol->value.integer.value[i] != rt715->kctl_4ch_orig[i]) {
k_changed = 1;
break;
}
}
for (i = 0; i < 4; i++) {
rt715->kctl_4ch_orig[i] = ucontrol->value.integer.value[i];
gain_val =
rt715_sdca_vol_gain(ucontrol->value.integer.value[i], p->max,
gain_sft);
ret = regmap_write(rt715->mbq_regmap, reg_base + i,
gain_val);
if (ret != 0) {
dev_err(component->dev, "Failed to write 0x%x=0x%x\n",
reg_base + i, gain_val);
return ret;
}
}
return k_changed;
}
static int rt715_sdca_set_amp_gain_8ch_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt715_sdca_priv *rt715 = snd_soc_component_get_drvdata(component);
struct rt715_sdca_kcontrol_private *p =
(struct rt715_sdca_kcontrol_private *)kcontrol->private_value;
unsigned int reg_base = p->reg_base, i, k_changed = 0;
const unsigned int gain_sft = 8;
unsigned int gain_val, reg;
int ret;
for (i = 0; i < 8; i++) {
if (ucontrol->value.integer.value[i] != rt715->kctl_8ch_orig[i]) {
k_changed = 1;
break;
}
}
for (i = 0; i < 8; i++) {
rt715->kctl_8ch_orig[i] = ucontrol->value.integer.value[i];
gain_val =
rt715_sdca_boost_gain(ucontrol->value.integer.value[i], p->max,
gain_sft);
reg = i < 7 ? reg_base + i : (reg_base - 1) | BIT(15);
ret = regmap_write(rt715->mbq_regmap, reg, gain_val);
if (ret != 0) {
dev_err(component->dev, "Failed to write 0x%x=0x%x\n",
reg, gain_val);
return ret;
}
}
return k_changed;
}
static int rt715_sdca_set_amp_gain_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct rt715_sdca_priv *rt715 = snd_soc_component_get_drvdata(component);
unsigned int val, i;
int ret;
for (i = 0; i < 2; i++) {
ret = regmap_read(rt715->mbq_regmap, mc->reg + i, &val);
if (ret < 0) {
dev_err(component->dev, "Failed to read 0x%x, ret=%d\n",
mc->reg + i, ret);
return ret;
}
ucontrol->value.integer.value[i] = rt715_sdca_get_gain(val, mc->shift);
}
return 0;
}
static int rt715_sdca_set_amp_gain_4ch_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt715_sdca_priv *rt715 = snd_soc_component_get_drvdata(component);
struct rt715_sdca_kcontrol_private *p =
(struct rt715_sdca_kcontrol_private *)kcontrol->private_value;
unsigned int reg_base = p->reg_base, i;
const unsigned int gain_sft = 0x2f;
unsigned int val;
int ret;
for (i = 0; i < 4; i++) {
ret = regmap_read(rt715->mbq_regmap, reg_base + i, &val);
if (ret < 0) {
dev_err(component->dev, "Failed to read 0x%x, ret=%d\n",
reg_base + i, ret);
return ret;
}
ucontrol->value.integer.value[i] = rt715_sdca_get_gain(val, gain_sft);
}
return 0;
}
static int rt715_sdca_set_amp_gain_8ch_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt715_sdca_priv *rt715 = snd_soc_component_get_drvdata(component);
struct rt715_sdca_kcontrol_private *p =
(struct rt715_sdca_kcontrol_private *)kcontrol->private_value;
unsigned int reg_base = p->reg_base;
const unsigned int gain_sft = 8;
unsigned int val_l, val_r;
unsigned int i, reg;
int ret;
for (i = 0; i < 8; i += 2) {
ret = regmap_read(rt715->mbq_regmap, reg_base + i, &val_l);
if (ret < 0) {
dev_err(component->dev, "Failed to read 0x%x, ret=%d\n",
reg_base + i, ret);
return ret;
}
ucontrol->value.integer.value[i] = (val_l >> gain_sft) / 10;
reg = (i == 6) ? (reg_base - 1) | BIT(15) : reg_base + 1 + i;
ret = regmap_read(rt715->mbq_regmap, reg, &val_r);
if (ret < 0) {
dev_err(component->dev, "Failed to read 0x%x, ret=%d\n",
reg, ret);
return ret;
}
ucontrol->value.integer.value[i + 1] = (val_r >> gain_sft) / 10;
}
return 0;
}
static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -17625, 375, 0);
static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
static int rt715_sdca_get_volsw(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt715_sdca_kcontrol_private *p =
(struct rt715_sdca_kcontrol_private *)kcontrol->private_value;
unsigned int reg_base = p->reg_base;
unsigned int invert = p->invert, i;
int val;
for (i = 0; i < p->count; i += 2) {
val = snd_soc_component_read(component, reg_base + i);
if (val < 0)
return -EINVAL;
ucontrol->value.integer.value[i] = invert ? p->max - val : val;
val = snd_soc_component_read(component, reg_base + 1 + i);
if (val < 0)
return -EINVAL;
ucontrol->value.integer.value[i + 1] =
invert ? p->max - val : val;
}
return 0;
}
static int rt715_sdca_put_volsw(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt715_sdca_priv *rt715 = snd_soc_component_get_drvdata(component);
struct rt715_sdca_kcontrol_private *p =
(struct rt715_sdca_kcontrol_private *)kcontrol->private_value;
unsigned int val[4] = {0}, val_mask, i, k_changed = 0;
unsigned int reg = p->reg_base;
unsigned int shift = p->shift;
unsigned int max = p->max;
unsigned int mask = (1 << fls(max)) - 1;
unsigned int invert = p->invert;
int err;
for (i = 0; i < 4; i++) {
if (ucontrol->value.integer.value[i] != rt715->kctl_switch_orig[i]) {
k_changed = 1;
break;
}
}
for (i = 0; i < 2; i++) {
rt715->kctl_switch_orig[i * 2] = ucontrol->value.integer.value[i * 2];
val[i * 2] = ucontrol->value.integer.value[i * 2] & mask;
if (invert)
val[i * 2] = max - val[i * 2];
val_mask = mask << shift;
val[i * 2] <<= shift;
rt715->kctl_switch_orig[i * 2 + 1] =
ucontrol->value.integer.value[i * 2 + 1];
val[i * 2 + 1] =
ucontrol->value.integer.value[i * 2 + 1] & mask;
if (invert)
val[i * 2 + 1] = max - val[i * 2 + 1];
val[i * 2 + 1] <<= shift;
err = snd_soc_component_update_bits(component, reg + i * 2, val_mask,
val[i * 2]);
if (err < 0)
return err;
err = snd_soc_component_update_bits(component, reg + 1 + i * 2,
val_mask, val[i * 2 + 1]);
if (err < 0)
return err;
}
return k_changed;
}
static int rt715_sdca_fu_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
struct rt715_sdca_kcontrol_private *p =
(struct rt715_sdca_kcontrol_private *)kcontrol->private_value;
if (p->max == 1)
uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
else
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = p->count;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = p->max;
return 0;
}
#define RT715_SDCA_PR_VALUE(xreg_base, xcount, xmax, xshift, xinvert) \
((unsigned long)&(struct rt715_sdca_kcontrol_private) \
{.reg_base = xreg_base, .count = xcount, .max = xmax, \
.shift = xshift, .invert = xinvert})
#define RT715_SDCA_FU_CTRL(xname, reg_base, xshift, xmax, xinvert, xcount) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
.info = rt715_sdca_fu_info, \
.get = rt715_sdca_get_volsw, \
.put = rt715_sdca_put_volsw, \
.private_value = RT715_SDCA_PR_VALUE(reg_base, xcount, xmax, \
xshift, xinvert)}
#define SOC_DOUBLE_R_EXT(xname, reg_left, reg_right, xshift, xmax, xinvert,\
xhandler_get, xhandler_put) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
.info = snd_soc_info_volsw, \
.get = xhandler_get, .put = xhandler_put, \
.private_value = SOC_DOUBLE_R_VALUE(reg_left, reg_right, xshift, \
xmax, xinvert) }
#define RT715_SDCA_EXT_TLV(xname, reg_base, xhandler_get,\
xhandler_put, tlv_array, xcount, xmax) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
SNDRV_CTL_ELEM_ACCESS_READWRITE, \
.tlv.p = (tlv_array), \
.info = rt715_sdca_fu_info, \
.get = xhandler_get, .put = xhandler_put, \
.private_value = RT715_SDCA_PR_VALUE(reg_base, xcount, xmax, 0, 0) }
#define RT715_SDCA_BOOST_EXT_TLV(xname, reg_base, xhandler_get,\
xhandler_put, tlv_array, xcount, xmax) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
SNDRV_CTL_ELEM_ACCESS_READWRITE, \
.tlv.p = (tlv_array), \
.info = rt715_sdca_fu_info, \
.get = xhandler_get, .put = xhandler_put, \
.private_value = RT715_SDCA_PR_VALUE(reg_base, xcount, xmax, 0, 0) }
static const struct snd_kcontrol_new rt715_sdca_snd_controls[] = {
/* Capture switch */
SOC_DOUBLE_R("FU0A Capture Switch",
SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_FU_ADC7_27_VOL,
RT715_SDCA_FU_MUTE_CTRL, CH_01),
SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_FU_ADC7_27_VOL,
RT715_SDCA_FU_MUTE_CTRL, CH_02),
0, 1, 1),
RT715_SDCA_FU_CTRL("FU02 Capture Switch",
SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_FU_ADC8_9_VOL,
RT715_SDCA_FU_MUTE_CTRL, CH_01),
0, 1, 1, 4),
RT715_SDCA_FU_CTRL("FU06 Capture Switch",
SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_FU_ADC10_11_VOL,
RT715_SDCA_FU_MUTE_CTRL, CH_01),
0, 1, 1, 4),
/* Volume Control */
SOC_DOUBLE_R_EXT_TLV("FU0A Capture Volume",
SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_FU_ADC7_27_VOL,
RT715_SDCA_FU_VOL_CTRL, CH_01),
SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_FU_ADC7_27_VOL,
RT715_SDCA_FU_VOL_CTRL, CH_02),
0x2f, 0x7f, 0,
rt715_sdca_set_amp_gain_get, rt715_sdca_set_amp_gain_put,
in_vol_tlv),
RT715_SDCA_EXT_TLV("FU02 Capture Volume",
SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_FU_ADC8_9_VOL,
RT715_SDCA_FU_VOL_CTRL, CH_01),
rt715_sdca_set_amp_gain_4ch_get,
rt715_sdca_set_amp_gain_4ch_put,
in_vol_tlv, 4, 0x7f),
RT715_SDCA_EXT_TLV("FU06 Capture Volume",
SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_FU_ADC10_11_VOL,
RT715_SDCA_FU_VOL_CTRL, CH_01),
rt715_sdca_set_amp_gain_4ch_get,
rt715_sdca_set_amp_gain_4ch_put,
in_vol_tlv, 4, 0x7f),
/* MIC Boost Control */
RT715_SDCA_BOOST_EXT_TLV("FU0E Boost",
SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_FU_DMIC_GAIN_EN,
RT715_SDCA_FU_DMIC_GAIN_CTRL, CH_01),
rt715_sdca_set_amp_gain_8ch_get,
rt715_sdca_set_amp_gain_8ch_put,
mic_vol_tlv, 8, 3),
RT715_SDCA_BOOST_EXT_TLV("FU0C Boost",
SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_FU_AMIC_GAIN_EN,
RT715_SDCA_FU_DMIC_GAIN_CTRL, CH_01),
rt715_sdca_set_amp_gain_8ch_get,
rt715_sdca_set_amp_gain_8ch_put,
mic_vol_tlv, 8, 3),
};
static int rt715_sdca_mux_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_dapm_kcontrol_component(kcontrol);
struct rt715_sdca_priv *rt715 = snd_soc_component_get_drvdata(component);
unsigned int val, mask_sft;
if (strstr(ucontrol->id.name, "ADC 22 Mux"))
mask_sft = 12;
else if (strstr(ucontrol->id.name, "ADC 23 Mux"))
mask_sft = 8;
else if (strstr(ucontrol->id.name, "ADC 24 Mux"))
mask_sft = 4;
else if (strstr(ucontrol->id.name, "ADC 25 Mux"))
mask_sft = 0;
else
return -EINVAL;
rt715_sdca_index_read(rt715, RT715_VENDOR_HDA_CTL,
RT715_HDA_LEGACY_MUX_CTL1, &val);
val = (val >> mask_sft) & 0xf;
/*
* The first two indices of ADC Mux 24/25 are routed to the same
* hardware source. ie, ADC Mux 24 0/1 will both connect to MIC2.
* To have a unique set of inputs, we skip the index1 of the muxes.
*/
if ((strstr(ucontrol->id.name, "ADC 24 Mux") ||
strstr(ucontrol->id.name, "ADC 25 Mux")) && val > 0)
val -= 1;
ucontrol->value.enumerated.item[0] = val;
return 0;
}
static int rt715_sdca_mux_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_dapm_kcontrol_component(kcontrol);
struct snd_soc_dapm_context *dapm =
snd_soc_dapm_kcontrol_dapm(kcontrol);
struct rt715_sdca_priv *rt715 = snd_soc_component_get_drvdata(component);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int *item = ucontrol->value.enumerated.item;
unsigned int val, val2 = 0, change, mask_sft;
if (item[0] >= e->items)
return -EINVAL;
if (strstr(ucontrol->id.name, "ADC 22 Mux"))
mask_sft = 12;
else if (strstr(ucontrol->id.name, "ADC 23 Mux"))
mask_sft = 8;
else if (strstr(ucontrol->id.name, "ADC 24 Mux"))
mask_sft = 4;
else if (strstr(ucontrol->id.name, "ADC 25 Mux"))
mask_sft = 0;
else
return -EINVAL;
/* Verb ID = 0x701h, nid = e->reg */
val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
rt715_sdca_index_read(rt715, RT715_VENDOR_HDA_CTL,
RT715_HDA_LEGACY_MUX_CTL1, &val2);
val2 = (val2 >> mask_sft) & 0xf;
change = val != val2;
if (change)
rt715_sdca_index_update_bits(rt715, RT715_VENDOR_HDA_CTL,
RT715_HDA_LEGACY_MUX_CTL1, 0xf << mask_sft, val << mask_sft);
snd_soc_dapm_mux_update_power(dapm, kcontrol, item[0], e, NULL);
return change;
}
static const char * const adc_22_23_mux_text[] = {
"MIC1",
"MIC2",
"LINE1",
"LINE2",
"DMIC1",
"DMIC2",
"DMIC3",
"DMIC4",
};
/*
* Due to mux design for nid 24 (MUX_IN3)/25 (MUX_IN4), connection index 0 and
* 1 will be connected to the same dmic source, therefore we skip index 1 to
* avoid misunderstanding on usage of dapm routing.
*/
static int rt715_adc_24_25_values[] = {
0,
2,
3,
4,
5,
};
static const char * const adc_24_mux_text[] = {
"MIC2",
"DMIC1",
"DMIC2",
"DMIC3",
"DMIC4",
};
static const char * const adc_25_mux_text[] = {
"MIC1",
"DMIC1",
"DMIC2",
"DMIC3",
"DMIC4",
};
static SOC_ENUM_SINGLE_DECL(rt715_adc22_enum, SND_SOC_NOPM, 0,
adc_22_23_mux_text);
static SOC_ENUM_SINGLE_DECL(rt715_adc23_enum, SND_SOC_NOPM, 0,
adc_22_23_mux_text);
static SOC_VALUE_ENUM_SINGLE_DECL(rt715_adc24_enum,
SND_SOC_NOPM, 0, 0xf,
adc_24_mux_text, rt715_adc_24_25_values);
static SOC_VALUE_ENUM_SINGLE_DECL(rt715_adc25_enum,
SND_SOC_NOPM, 0, 0xf,
adc_25_mux_text, rt715_adc_24_25_values);
static const struct snd_kcontrol_new rt715_adc22_mux =
SOC_DAPM_ENUM_EXT("ADC 22 Mux", rt715_adc22_enum,
rt715_sdca_mux_get, rt715_sdca_mux_put);
static const struct snd_kcontrol_new rt715_adc23_mux =
SOC_DAPM_ENUM_EXT("ADC 23 Mux", rt715_adc23_enum,
rt715_sdca_mux_get, rt715_sdca_mux_put);
static const struct snd_kcontrol_new rt715_adc24_mux =
SOC_DAPM_ENUM_EXT("ADC 24 Mux", rt715_adc24_enum,
rt715_sdca_mux_get, rt715_sdca_mux_put);
static const struct snd_kcontrol_new rt715_adc25_mux =
SOC_DAPM_ENUM_EXT("ADC 25 Mux", rt715_adc25_enum,
rt715_sdca_mux_get, rt715_sdca_mux_put);
static int rt715_sdca_pde23_24_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt715_sdca_priv *rt715 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_write(rt715->regmap,
SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_CREQ_POW_EN,
RT715_SDCA_REQ_POW_CTRL,
CH_00), 0x00);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_write(rt715->regmap,
SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_CREQ_POW_EN,
RT715_SDCA_REQ_POW_CTRL,
CH_00), 0x03);
break;
}
return 0;
}
static const struct snd_soc_dapm_widget rt715_sdca_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("DMIC1"),
SND_SOC_DAPM_INPUT("DMIC2"),
SND_SOC_DAPM_INPUT("DMIC3"),
SND_SOC_DAPM_INPUT("DMIC4"),
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_INPUT("MIC2"),
SND_SOC_DAPM_INPUT("LINE1"),
SND_SOC_DAPM_INPUT("LINE2"),
SND_SOC_DAPM_SUPPLY("PDE23_24", SND_SOC_NOPM, 0, 0,
rt715_sdca_pde23_24_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_ADC("ADC 07", NULL, SND_SOC_NOPM, 4, 0),
SND_SOC_DAPM_ADC("ADC 08", NULL, SND_SOC_NOPM, 4, 0),
SND_SOC_DAPM_ADC("ADC 09", NULL, SND_SOC_NOPM, 4, 0),
SND_SOC_DAPM_ADC("ADC 27", NULL, SND_SOC_NOPM, 4, 0),
SND_SOC_DAPM_MUX("ADC 22 Mux", SND_SOC_NOPM, 0, 0,
&rt715_adc22_mux),
SND_SOC_DAPM_MUX("ADC 23 Mux", SND_SOC_NOPM, 0, 0,
&rt715_adc23_mux),
SND_SOC_DAPM_MUX("ADC 24 Mux", SND_SOC_NOPM, 0, 0,
&rt715_adc24_mux),
SND_SOC_DAPM_MUX("ADC 25 Mux", SND_SOC_NOPM, 0, 0,
&rt715_adc25_mux),
SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("DP6TX", "DP6 Capture", 0, SND_SOC_NOPM, 0, 0),
};
static const struct snd_soc_dapm_route rt715_sdca_audio_map[] = {
{"DP6TX", NULL, "ADC 09"},
{"DP6TX", NULL, "ADC 08"},
{"DP4TX", NULL, "ADC 07"},
{"DP4TX", NULL, "ADC 27"},
{"DP4TX", NULL, "ADC 09"},
{"DP4TX", NULL, "ADC 08"},
{"LINE1", NULL, "PDE23_24"},
{"LINE2", NULL, "PDE23_24"},
{"MIC1", NULL, "PDE23_24"},
{"MIC2", NULL, "PDE23_24"},
{"DMIC1", NULL, "PDE23_24"},
{"DMIC2", NULL, "PDE23_24"},
{"DMIC3", NULL, "PDE23_24"},
{"DMIC4", NULL, "PDE23_24"},
{"ADC 09", NULL, "ADC 22 Mux"},
{"ADC 08", NULL, "ADC 23 Mux"},
{"ADC 07", NULL, "ADC 24 Mux"},
{"ADC 27", NULL, "ADC 25 Mux"},
{"ADC 22 Mux", "MIC1", "MIC1"},
{"ADC 22 Mux", "MIC2", "MIC2"},
{"ADC 22 Mux", "LINE1", "LINE1"},
{"ADC 22 Mux", "LINE2", "LINE2"},
{"ADC 22 Mux", "DMIC1", "DMIC1"},
{"ADC 22 Mux", "DMIC2", "DMIC2"},
{"ADC 22 Mux", "DMIC3", "DMIC3"},
{"ADC 22 Mux", "DMIC4", "DMIC4"},
{"ADC 23 Mux", "MIC1", "MIC1"},
{"ADC 23 Mux", "MIC2", "MIC2"},
{"ADC 23 Mux", "LINE1", "LINE1"},
{"ADC 23 Mux", "LINE2", "LINE2"},
{"ADC 23 Mux", "DMIC1", "DMIC1"},
{"ADC 23 Mux", "DMIC2", "DMIC2"},
{"ADC 23 Mux", "DMIC3", "DMIC3"},
{"ADC 23 Mux", "DMIC4", "DMIC4"},
{"ADC 24 Mux", "MIC2", "MIC2"},
{"ADC 24 Mux", "DMIC1", "DMIC1"},
{"ADC 24 Mux", "DMIC2", "DMIC2"},
{"ADC 24 Mux", "DMIC3", "DMIC3"},
{"ADC 24 Mux", "DMIC4", "DMIC4"},
{"ADC 25 Mux", "MIC1", "MIC1"},
{"ADC 25 Mux", "DMIC1", "DMIC1"},
{"ADC 25 Mux", "DMIC2", "DMIC2"},
{"ADC 25 Mux", "DMIC3", "DMIC3"},
{"ADC 25 Mux", "DMIC4", "DMIC4"},
};
static int rt715_sdca_probe(struct snd_soc_component *component)
{
struct rt715_sdca_priv *rt715 = snd_soc_component_get_drvdata(component);
int ret;
if (!rt715->first_hw_init)
return 0;
ret = pm_runtime_resume(component->dev);
if (ret < 0 && ret != -EACCES)
return ret;
return 0;
}
static const struct snd_soc_component_driver soc_codec_dev_rt715_sdca = {
.probe = rt715_sdca_probe,
.controls = rt715_sdca_snd_controls,
.num_controls = ARRAY_SIZE(rt715_sdca_snd_controls),
.dapm_widgets = rt715_sdca_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt715_sdca_dapm_widgets),
.dapm_routes = rt715_sdca_audio_map,
.num_dapm_routes = ARRAY_SIZE(rt715_sdca_audio_map),
.endianness = 1,
};
static int rt715_sdca_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
int direction)
{
snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
return 0;
}
static void rt715_sdca_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
snd_soc_dai_set_dma_data(dai, substream, NULL);
}
static int rt715_sdca_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt715_sdca_priv *rt715 = snd_soc_component_get_drvdata(component);
struct sdw_stream_config stream_config = {0};
struct sdw_port_config port_config = {0};
struct sdw_stream_runtime *sdw_stream;
int retval;
unsigned int val;
sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
if (!sdw_stream)
return -EINVAL;
if (!rt715->slave)
return -EINVAL;
snd_sdw_params_to_config(substream, params, &stream_config, &port_config);
switch (dai->id) {
case RT715_AIF1:
port_config.num = 6;
rt715_sdca_index_write(rt715, RT715_VENDOR_REG, RT715_SDW_INPUT_SEL,
0xa500);
break;
case RT715_AIF2:
port_config.num = 4;
rt715_sdca_index_write(rt715, RT715_VENDOR_REG, RT715_SDW_INPUT_SEL,
0xaf00);
break;
default:
dev_err(component->dev, "Invalid DAI id %d\n", dai->id);
return -EINVAL;
}
retval = sdw_stream_add_slave(rt715->slave, &stream_config,
&port_config, 1, sdw_stream);
if (retval) {
dev_err(component->dev, "Unable to configure port, retval:%d\n",
retval);
return retval;
}
switch (params_rate(params)) {
case 8000:
val = 0x1;
break;
case 11025:
val = 0x2;
break;
case 12000:
val = 0x3;
break;
case 16000:
val = 0x4;
break;
case 22050:
val = 0x5;
break;
case 24000:
val = 0x6;
break;
case 32000:
val = 0x7;
break;
case 44100:
val = 0x8;
break;
case 48000:
val = 0x9;
break;
case 88200:
val = 0xa;
break;
case 96000:
val = 0xb;
break;
case 176400:
val = 0xc;
break;
case 192000:
val = 0xd;
break;
case 384000:
val = 0xe;
break;
case 768000:
val = 0xf;
break;
default:
dev_err(component->dev, "Unsupported sample rate %d\n",
params_rate(params));
return -EINVAL;
}
regmap_write(rt715->regmap,
SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_CS_FREQ_IND_EN,
RT715_SDCA_FREQ_IND_CTRL, CH_00), val);
return 0;
}
static int rt715_sdca_pcm_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt715_sdca_priv *rt715 = snd_soc_component_get_drvdata(component);
struct sdw_stream_runtime *sdw_stream =
snd_soc_dai_get_dma_data(dai, substream);
if (!rt715->slave)
return -EINVAL;
sdw_stream_remove_slave(rt715->slave, sdw_stream);
return 0;
}
#define RT715_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
#define RT715_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
static const struct snd_soc_dai_ops rt715_sdca_ops = {
.hw_params = rt715_sdca_pcm_hw_params,
.hw_free = rt715_sdca_pcm_hw_free,
.set_stream = rt715_sdca_set_sdw_stream,
.shutdown = rt715_sdca_shutdown,
};
static struct snd_soc_dai_driver rt715_sdca_dai[] = {
{
.name = "rt715-aif1",
.id = RT715_AIF1,
.capture = {
.stream_name = "DP6 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT715_STEREO_RATES,
.formats = RT715_FORMATS,
},
.ops = &rt715_sdca_ops,
},
{
.name = "rt715-aif2",
.id = RT715_AIF2,
.capture = {
.stream_name = "DP4 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT715_STEREO_RATES,
.formats = RT715_FORMATS,
},
.ops = &rt715_sdca_ops,
},
};
/* Bus clock frequency */
#define RT715_CLK_FREQ_9600000HZ 9600000
#define RT715_CLK_FREQ_12000000HZ 12000000
#define RT715_CLK_FREQ_6000000HZ 6000000
#define RT715_CLK_FREQ_4800000HZ 4800000
#define RT715_CLK_FREQ_2400000HZ 2400000
#define RT715_CLK_FREQ_12288000HZ 12288000
int rt715_sdca_init(struct device *dev, struct regmap *mbq_regmap,
struct regmap *regmap, struct sdw_slave *slave)
{
struct rt715_sdca_priv *rt715;
int ret;
rt715 = devm_kzalloc(dev, sizeof(*rt715), GFP_KERNEL);
if (!rt715)
return -ENOMEM;
dev_set_drvdata(dev, rt715);
rt715->slave = slave;
rt715->regmap = regmap;
rt715->mbq_regmap = mbq_regmap;
rt715->hw_sdw_ver = slave->id.sdw_version;
regcache_cache_only(rt715->regmap, true);
regcache_cache_only(rt715->mbq_regmap, true);
/*
* Mark hw_init to false
* HW init will be performed when device reports present
*/
rt715->hw_init = false;
rt715->first_hw_init = false;
ret = devm_snd_soc_register_component(dev,
&soc_codec_dev_rt715_sdca,
rt715_sdca_dai,
ARRAY_SIZE(rt715_sdca_dai));
if (ret < 0)
return ret;
/* set autosuspend parameters */
pm_runtime_set_autosuspend_delay(dev, 3000);
pm_runtime_use_autosuspend(dev);
/* make sure the device does not suspend immediately */
pm_runtime_mark_last_busy(dev);
pm_runtime_enable(dev);
/* important note: the device is NOT tagged as 'active' and will remain
* 'suspended' until the hardware is enumerated/initialized. This is required
* to make sure the ASoC framework use of pm_runtime_get_sync() does not silently
* fail with -EACCESS because of race conditions between card creation and enumeration
*/
dev_dbg(dev, "%s\n", __func__);
return ret;
}
int rt715_sdca_io_init(struct device *dev, struct sdw_slave *slave)
{
struct rt715_sdca_priv *rt715 = dev_get_drvdata(dev);
unsigned int hw_ver;
if (rt715->hw_init)
return 0;
regcache_cache_only(rt715->regmap, false);
regcache_cache_only(rt715->mbq_regmap, false);
/*
* PM runtime status is marked as 'active' only when a Slave reports as Attached
*/
if (!rt715->first_hw_init) {
/* update count of parent 'active' children */
pm_runtime_set_active(&slave->dev);
rt715->first_hw_init = true;
}
pm_runtime_get_noresume(&slave->dev);
rt715_sdca_index_read(rt715, RT715_VENDOR_REG,
RT715_PRODUCT_NUM, &hw_ver);
hw_ver = hw_ver & 0x000f;
/* set clock selector = external */
regmap_write(rt715->regmap,
SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_CX_CLK_SEL_EN,
RT715_SDCA_CX_CLK_SEL_CTRL, CH_00), 0x1);
/* set GPIO_4/5/6 to be 3rd/4th DMIC usage */
if (hw_ver == 0x0)
rt715_sdca_index_update_bits(rt715, RT715_VENDOR_REG,
RT715_AD_FUNC_EN, 0x54, 0x54);
else if (hw_ver == 0x1) {
rt715_sdca_index_update_bits(rt715, RT715_VENDOR_REG,
RT715_AD_FUNC_EN, 0x55, 0x55);
rt715_sdca_index_update_bits(rt715, RT715_VENDOR_REG,
RT715_REV_1, 0x40, 0x40);
}
/* DFLL Calibration trigger */
rt715_sdca_index_update_bits(rt715, RT715_VENDOR_REG,
RT715_DFLL_VAD, 0x1, 0x1);
/* trigger mode = VAD enable */
regmap_write(rt715->regmap,
SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_SMPU_TRIG_ST_EN,
RT715_SDCA_SMPU_TRIG_EN_CTRL, CH_00), 0x2);
/* SMPU-1 interrupt enable mask */
regmap_update_bits(rt715->regmap, RT715_INT_MASK, 0x1, 0x1);
/* Mark Slave initialization complete */
rt715->hw_init = true;
pm_runtime_mark_last_busy(&slave->dev);
pm_runtime_put_autosuspend(&slave->dev);
return 0;
}
MODULE_DESCRIPTION("ASoC rt715 driver SDW SDCA");
MODULE_AUTHOR("Jack Yu <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/rt715-sdca.c |
// SPDX-License-Identifier: GPL-2.0
// Driver for the Texas Instruments TAS2780 Mono
// Audio amplifier
// Copyright (C) 2022 Texas Instruments Inc.
#include <linux/module.h>
#include <linux/err.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/regmap.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <sound/soc.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/tlv.h>
#include "tas2780.h"
struct tas2780_priv {
struct snd_soc_component *component;
struct gpio_desc *reset_gpio;
struct regmap *regmap;
struct device *dev;
int v_sense_slot;
int i_sense_slot;
};
static void tas2780_reset(struct tas2780_priv *tas2780)
{
int ret = 0;
if (tas2780->reset_gpio) {
gpiod_set_value_cansleep(tas2780->reset_gpio, 0);
usleep_range(2000, 2050);
gpiod_set_value_cansleep(tas2780->reset_gpio, 1);
usleep_range(2000, 2050);
}
snd_soc_component_write(tas2780->component, TAS2780_SW_RST,
TAS2780_RST);
if (ret)
dev_err(tas2780->dev, "%s:errCode:0x%x Reset error!\n",
__func__, ret);
}
#ifdef CONFIG_PM
static int tas2780_codec_suspend(struct snd_soc_component *component)
{
struct tas2780_priv *tas2780 =
snd_soc_component_get_drvdata(component);
int ret = 0;
ret = snd_soc_component_update_bits(component, TAS2780_PWR_CTRL,
TAS2780_PWR_CTRL_MASK, TAS2780_PWR_CTRL_SHUTDOWN);
if (ret < 0) {
dev_err(tas2780->dev, "%s:errCode:0x%0x:power down error\n",
__func__, ret);
goto err;
}
ret = 0;
regcache_cache_only(tas2780->regmap, true);
regcache_mark_dirty(tas2780->regmap);
err:
return ret;
}
static int tas2780_codec_resume(struct snd_soc_component *component)
{
struct tas2780_priv *tas2780 =
snd_soc_component_get_drvdata(component);
int ret = 0;
ret = snd_soc_component_update_bits(component, TAS2780_PWR_CTRL,
TAS2780_PWR_CTRL_MASK, TAS2780_PWR_CTRL_ACTIVE);
if (ret < 0) {
dev_err(tas2780->dev, "%s:errCode:0x%0x:power down error\n",
__func__, ret);
goto err;
}
ret = 0;
regcache_cache_only(tas2780->regmap, false);
ret = regcache_sync(tas2780->regmap);
err:
return ret;
}
#endif
static const char * const tas2780_ASI1_src[] = {
"I2C offset", "Left", "Right", "LeftRightDiv2",
};
static SOC_ENUM_SINGLE_DECL(
tas2780_ASI1_src_enum, TAS2780_TDM_CFG2, 4, tas2780_ASI1_src);
static const struct snd_kcontrol_new tas2780_asi1_mux =
SOC_DAPM_ENUM("ASI1 Source", tas2780_ASI1_src_enum);
static const struct snd_kcontrol_new isense_switch =
SOC_DAPM_SINGLE("Switch", TAS2780_PWR_CTRL,
TAS2780_ISENSE_POWER_EN, 1, 1);
static const struct snd_kcontrol_new vsense_switch =
SOC_DAPM_SINGLE("Switch", TAS2780_PWR_CTRL,
TAS2780_VSENSE_POWER_EN, 1, 1);
static const struct snd_soc_dapm_widget tas2780_dapm_widgets[] = {
SND_SOC_DAPM_AIF_IN("ASI1", "ASI1 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_MUX("ASI1 Sel", SND_SOC_NOPM, 0, 0, &tas2780_asi1_mux),
SND_SOC_DAPM_SWITCH("ISENSE", TAS2780_PWR_CTRL,
TAS2780_ISENSE_POWER_EN, 1, &isense_switch),
SND_SOC_DAPM_SWITCH("VSENSE", TAS2780_PWR_CTRL,
TAS2780_VSENSE_POWER_EN, 1, &vsense_switch),
SND_SOC_DAPM_OUTPUT("OUT"),
SND_SOC_DAPM_SIGGEN("VMON"),
SND_SOC_DAPM_SIGGEN("IMON")
};
static const struct snd_soc_dapm_route tas2780_audio_map[] = {
{"ASI1 Sel", "I2C offset", "ASI1"},
{"ASI1 Sel", "Left", "ASI1"},
{"ASI1 Sel", "Right", "ASI1"},
{"ASI1 Sel", "LeftRightDiv2", "ASI1"},
{"OUT", NULL, "ASI1 Sel"},
{"ISENSE", "Switch", "IMON"},
{"VSENSE", "Switch", "VMON"},
};
static int tas2780_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
struct tas2780_priv *tas2780 =
snd_soc_component_get_drvdata(component);
int ret = 0;
ret = snd_soc_component_update_bits(component, TAS2780_PWR_CTRL,
TAS2780_PWR_CTRL_MASK,
mute ? TAS2780_PWR_CTRL_MUTE : 0);
if (ret < 0) {
dev_err(tas2780->dev, "%s: Failed to set powercontrol\n",
__func__);
goto err;
}
ret = 0;
err:
return ret;
}
static int tas2780_set_bitwidth(struct tas2780_priv *tas2780, int bitwidth)
{
struct snd_soc_component *component = tas2780->component;
int sense_en;
int val;
int ret;
int slot_size;
switch (bitwidth) {
case SNDRV_PCM_FORMAT_S16_LE:
ret = snd_soc_component_update_bits(component,
TAS2780_TDM_CFG2,
TAS2780_TDM_CFG2_RXW_MASK,
TAS2780_TDM_CFG2_RXW_16BITS);
slot_size = TAS2780_TDM_CFG2_RXS_16BITS;
break;
case SNDRV_PCM_FORMAT_S24_LE:
ret = snd_soc_component_update_bits(component,
TAS2780_TDM_CFG2,
TAS2780_TDM_CFG2_RXW_MASK,
TAS2780_TDM_CFG2_RXW_24BITS);
slot_size = TAS2780_TDM_CFG2_RXS_24BITS;
break;
case SNDRV_PCM_FORMAT_S32_LE:
ret = snd_soc_component_update_bits(component,
TAS2780_TDM_CFG2,
TAS2780_TDM_CFG2_RXW_MASK,
TAS2780_TDM_CFG2_RXW_32BITS);
slot_size = TAS2780_TDM_CFG2_RXS_32BITS;
break;
default:
ret = -EINVAL;
}
if (ret < 0) {
dev_err(tas2780->dev, "%s:errCode:0x%x set bitwidth error\n",
__func__, ret);
goto err;
}
ret = snd_soc_component_update_bits(component, TAS2780_TDM_CFG2,
TAS2780_TDM_CFG2_RXS_MASK, slot_size);
if (ret < 0) {
dev_err(tas2780->dev,
"%s:errCode:0x%x set RX slot size error\n",
__func__, ret);
goto err;
}
val = snd_soc_component_read(tas2780->component, TAS2780_PWR_CTRL);
if (val < 0) {
dev_err(tas2780->dev, "%s:errCode:0x%x read PWR_CTRL error\n",
__func__, val);
ret = val;
goto err;
}
if (val & (1 << TAS2780_VSENSE_POWER_EN))
sense_en = 0;
else
sense_en = TAS2780_TDM_CFG5_VSNS_ENABLE;
ret = snd_soc_component_update_bits(tas2780->component,
TAS2780_TDM_CFG5, TAS2780_TDM_CFG5_VSNS_ENABLE, sense_en);
if (ret < 0) {
dev_err(tas2780->dev, "%s:errCode:0x%x enable vSNS error\n",
__func__, ret);
goto err;
}
if (val & (1 << TAS2780_ISENSE_POWER_EN))
sense_en = 0;
else
sense_en = TAS2780_TDM_CFG6_ISNS_ENABLE;
ret = snd_soc_component_update_bits(tas2780->component,
TAS2780_TDM_CFG6, TAS2780_TDM_CFG6_ISNS_ENABLE, sense_en);
if (ret < 0) {
dev_err(tas2780->dev, "%s:errCode:0x%x enable iSNS error\n",
__func__, ret);
goto err;
}
ret = 0;
err:
return ret;
}
static int tas2780_set_samplerate(
struct tas2780_priv *tas2780, int samplerate)
{
struct snd_soc_component *component = tas2780->component;
int ramp_rate_val;
int ret;
switch (samplerate) {
case 48000:
ramp_rate_val = TAS2780_TDM_CFG0_SMP_48KHZ |
TAS2780_TDM_CFG0_44_1_48KHZ;
break;
case 44100:
ramp_rate_val = TAS2780_TDM_CFG0_SMP_44_1KHZ |
TAS2780_TDM_CFG0_44_1_48KHZ;
break;
case 96000:
ramp_rate_val = TAS2780_TDM_CFG0_SMP_48KHZ |
TAS2780_TDM_CFG0_88_2_96KHZ;
break;
case 88200:
ramp_rate_val = TAS2780_TDM_CFG0_SMP_44_1KHZ |
TAS2780_TDM_CFG0_88_2_96KHZ;
break;
default:
return -EINVAL;
}
ret = snd_soc_component_update_bits(component, TAS2780_TDM_CFG0,
TAS2780_TDM_CFG0_SMP_MASK | TAS2780_TDM_CFG0_MASK,
ramp_rate_val);
if (ret < 0) {
dev_err(tas2780->dev,
"%s:errCode:0x%x Failed to set ramp_rate_val\n",
__func__, ret);
goto err;
}
ret = 0;
err:
return ret;
}
static int tas2780_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct tas2780_priv *tas2780 =
snd_soc_component_get_drvdata(component);
int ret;
ret = tas2780_set_bitwidth(tas2780, params_format(params));
if (ret < 0)
return ret;
return tas2780_set_samplerate(tas2780, params_rate(params));
}
static int tas2780_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct tas2780_priv *tas2780 =
snd_soc_component_get_drvdata(component);
u8 tdm_rx_start_slot = 0, asi_cfg_1 = 0;
int iface;
int ret = 0;
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
asi_cfg_1 = TAS2780_TDM_CFG1_RX_RISING;
break;
case SND_SOC_DAIFMT_IB_NF:
asi_cfg_1 = TAS2780_TDM_CFG1_RX_FALLING;
break;
default:
dev_err(tas2780->dev, "ASI format Inverse is not found\n");
return -EINVAL;
}
ret = snd_soc_component_update_bits(component, TAS2780_TDM_CFG1,
TAS2780_TDM_CFG1_RX_MASK, asi_cfg_1);
if (ret < 0) {
dev_err(tas2780->dev,
"%s:errCode:0x%x Failed to set asi_cfg_1\n",
__func__, ret);
goto err;
}
if (((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_I2S)
|| ((fmt & SND_SOC_DAIFMT_FORMAT_MASK)
== SND_SOC_DAIFMT_DSP_A)){
iface = TAS2780_TDM_CFG2_SCFG_I2S;
tdm_rx_start_slot = 1;
} else {
if (((fmt & SND_SOC_DAIFMT_FORMAT_MASK)
== SND_SOC_DAIFMT_DSP_B)
|| ((fmt & SND_SOC_DAIFMT_FORMAT_MASK)
== SND_SOC_DAIFMT_LEFT_J)) {
iface = TAS2780_TDM_CFG2_SCFG_LEFT_J;
tdm_rx_start_slot = 0;
} else {
dev_err(tas2780->dev,
"%s:DAI Format is not found, fmt=0x%x\n",
__func__, fmt);
ret = -EINVAL;
goto err;
}
}
ret = snd_soc_component_update_bits(component, TAS2780_TDM_CFG1,
TAS2780_TDM_CFG1_MASK,
(tdm_rx_start_slot << TAS2780_TDM_CFG1_51_SHIFT));
if (ret < 0) {
dev_err(tas2780->dev,
"%s:errCode:0x%x Failed to set tdm_rx_start_slot\n",
__func__, ret);
goto err;
}
ret = snd_soc_component_update_bits(component, TAS2780_TDM_CFG2,
TAS2780_TDM_CFG2_SCFG_MASK, iface);
if (ret < 0) {
dev_err(tas2780->dev, "%s:errCode:0x%x Failed to set iface\n",
__func__, ret);
goto err;
}
ret = 0;
err:
return ret;
}
static int tas2780_set_dai_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask,
unsigned int rx_mask,
int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
struct tas2780_priv *tas2780 =
snd_soc_component_get_drvdata(component);
int left_slot, right_slot;
int slots_cfg;
int slot_size;
int ret = 0;
if (tx_mask == 0 || rx_mask != 0)
return -EINVAL;
left_slot = __ffs(tx_mask);
tx_mask &= ~(1 << left_slot);
if (tx_mask == 0) {
right_slot = left_slot;
} else {
right_slot = __ffs(tx_mask);
tx_mask &= ~(1 << right_slot);
}
if (tx_mask != 0 || left_slot >= slots || right_slot >= slots)
return -EINVAL;
slots_cfg = (right_slot << TAS2780_TDM_CFG3_RXS_SHIFT) | left_slot;
ret = snd_soc_component_write(component, TAS2780_TDM_CFG3, slots_cfg);
if (ret) {
dev_err(tas2780->dev,
"%s:errCode:0x%x Failed to set slots_cfg\n",
__func__, ret);
goto err;
}
switch (slot_width) {
case 16:
slot_size = TAS2780_TDM_CFG2_RXS_16BITS;
break;
case 24:
slot_size = TAS2780_TDM_CFG2_RXS_24BITS;
break;
case 32:
slot_size = TAS2780_TDM_CFG2_RXS_32BITS;
break;
default:
ret = -EINVAL;
goto err;
}
ret = snd_soc_component_update_bits(component, TAS2780_TDM_CFG2,
TAS2780_TDM_CFG2_RXS_MASK, slot_size);
if (ret < 0) {
dev_err(tas2780->dev,
"%s:errCode:0x%x Failed to set slot_size\n",
__func__, ret);
goto err;
}
ret = snd_soc_component_update_bits(component, TAS2780_TDM_CFG5,
TAS2780_TDM_CFG5_50_MASK, tas2780->v_sense_slot);
if (ret < 0) {
dev_err(tas2780->dev,
"%s:errCode:0x%x Failed to set v_sense_slot\n",
__func__, ret);
goto err;
}
ret = snd_soc_component_update_bits(component, TAS2780_TDM_CFG6,
TAS2780_TDM_CFG6_50_MASK, tas2780->i_sense_slot);
if (ret < 0) {
dev_err(tas2780->dev,
"%s:errCode:0x%x Failed to set i_sense_slot\n",
__func__, ret);
goto err;
}
ret = 0;
err:
return ret;
}
static const struct snd_soc_dai_ops tas2780_dai_ops = {
.mute_stream = tas2780_mute,
.hw_params = tas2780_hw_params,
.set_fmt = tas2780_set_fmt,
.set_tdm_slot = tas2780_set_dai_tdm_slot,
.no_capture_mute = 1,
};
#define TAS2780_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
#define TAS2780_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_88200)
static struct snd_soc_dai_driver tas2780_dai_driver[] = {
{
.name = "tas2780 ASI1",
.id = 0,
.playback = {
.stream_name = "ASI1 Playback",
.channels_min = 2,
.channels_max = 2,
.rates = TAS2780_RATES,
.formats = TAS2780_FORMATS,
},
.capture = {
.stream_name = "ASI1 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = TAS2780_RATES,
.formats = TAS2780_FORMATS,
},
.ops = &tas2780_dai_ops,
.symmetric_rate = 1,
},
};
static int tas2780_codec_probe(struct snd_soc_component *component)
{
struct tas2780_priv *tas2780 =
snd_soc_component_get_drvdata(component);
int ret = 0;
tas2780->component = component;
tas2780_reset(tas2780);
ret = snd_soc_component_update_bits(component,
TAS2780_IC_CFG, TAS2780_IC_CFG_MASK,
TAS2780_IC_CFG_ENABLE);
if (ret < 0)
dev_err(tas2780->dev, "%s:errCode:0x%0x\n",
__func__, ret);
return ret;
}
static DECLARE_TLV_DB_SCALE(tas2780_digital_tlv, 1100, 50, 0);
static DECLARE_TLV_DB_SCALE(tas2780_playback_volume, -10000, 50, 0);
static const struct snd_kcontrol_new tas2780_snd_controls[] = {
SOC_SINGLE_TLV("Speaker Volume", TAS2780_DVC, 0,
TAS2780_DVC_MAX, 1, tas2780_playback_volume),
SOC_SINGLE_TLV("Amp Gain Volume", TAS2780_CHNL_0, 0, 0x14, 0,
tas2780_digital_tlv),
};
static const struct snd_soc_component_driver soc_component_driver_tas2780 = {
.probe = tas2780_codec_probe,
#ifdef CONFIG_PM
.suspend = tas2780_codec_suspend,
.resume = tas2780_codec_resume,
#endif
.controls = tas2780_snd_controls,
.num_controls = ARRAY_SIZE(tas2780_snd_controls),
.dapm_widgets = tas2780_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(tas2780_dapm_widgets),
.dapm_routes = tas2780_audio_map,
.num_dapm_routes = ARRAY_SIZE(tas2780_audio_map),
.idle_bias_on = 1,
.endianness = 1,
};
static const struct reg_default tas2780_reg_defaults[] = {
{ TAS2780_PAGE, 0x00 },
{ TAS2780_SW_RST, 0x00 },
{ TAS2780_PWR_CTRL, 0x1a },
{ TAS2780_DVC, 0x00 },
{ TAS2780_CHNL_0, 0x00 },
{ TAS2780_TDM_CFG0, 0x09 },
{ TAS2780_TDM_CFG1, 0x02 },
{ TAS2780_TDM_CFG2, 0x0a },
{ TAS2780_TDM_CFG3, 0x10 },
{ TAS2780_TDM_CFG5, 0x42 },
};
static const struct regmap_range_cfg tas2780_regmap_ranges[] = {
{
.range_min = 0,
.range_max = 1 * 128,
.selector_reg = TAS2780_PAGE,
.selector_mask = 0xff,
.selector_shift = 0,
.window_start = 0,
.window_len = 128,
},
};
static const struct regmap_config tas2780_i2c_regmap = {
.reg_bits = 8,
.val_bits = 8,
.reg_defaults = tas2780_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tas2780_reg_defaults),
.cache_type = REGCACHE_RBTREE,
.ranges = tas2780_regmap_ranges,
.num_ranges = ARRAY_SIZE(tas2780_regmap_ranges),
.max_register = 1 * 128,
};
static int tas2780_parse_dt(struct device *dev, struct tas2780_priv *tas2780)
{
int ret = 0;
tas2780->reset_gpio = devm_gpiod_get_optional(tas2780->dev, "reset",
GPIOD_OUT_HIGH);
if (IS_ERR(tas2780->reset_gpio)) {
if (PTR_ERR(tas2780->reset_gpio) == -EPROBE_DEFER) {
tas2780->reset_gpio = NULL;
return -EPROBE_DEFER;
}
}
ret = fwnode_property_read_u32(dev->fwnode, "ti,imon-slot-no",
&tas2780->i_sense_slot);
if (ret)
tas2780->i_sense_slot = 0;
ret = fwnode_property_read_u32(dev->fwnode, "ti,vmon-slot-no",
&tas2780->v_sense_slot);
if (ret)
tas2780->v_sense_slot = 2;
return 0;
}
static int tas2780_i2c_probe(struct i2c_client *client)
{
struct tas2780_priv *tas2780;
int result;
tas2780 = devm_kzalloc(&client->dev, sizeof(struct tas2780_priv),
GFP_KERNEL);
if (!tas2780)
return -ENOMEM;
tas2780->dev = &client->dev;
i2c_set_clientdata(client, tas2780);
dev_set_drvdata(&client->dev, tas2780);
tas2780->regmap = devm_regmap_init_i2c(client, &tas2780_i2c_regmap);
if (IS_ERR(tas2780->regmap)) {
result = PTR_ERR(tas2780->regmap);
dev_err(&client->dev, "Failed to allocate register map: %d\n",
result);
return result;
}
if (client->dev.of_node) {
result = tas2780_parse_dt(&client->dev, tas2780);
if (result) {
dev_err(tas2780->dev,
"%s: Failed to parse devicetree\n", __func__);
return result;
}
}
return devm_snd_soc_register_component(tas2780->dev,
&soc_component_driver_tas2780, tas2780_dai_driver,
ARRAY_SIZE(tas2780_dai_driver));
}
static const struct i2c_device_id tas2780_i2c_id[] = {
{ "tas2780", 0},
{ }
};
MODULE_DEVICE_TABLE(i2c, tas2780_i2c_id);
#if defined(CONFIG_OF)
static const struct of_device_id tas2780_of_match[] = {
{ .compatible = "ti,tas2780" },
{},
};
MODULE_DEVICE_TABLE(of, tas2780_of_match);
#endif
static struct i2c_driver tas2780_i2c_driver = {
.driver = {
.name = "tas2780",
.of_match_table = of_match_ptr(tas2780_of_match),
},
.probe = tas2780_i2c_probe,
.id_table = tas2780_i2c_id,
};
module_i2c_driver(tas2780_i2c_driver);
MODULE_AUTHOR("Raphael Xu <[email protected]>");
MODULE_DESCRIPTION("TAS2780 I2C Smart Amplifier driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/tas2780.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* ad1980.c -- ALSA Soc AD1980 codec support
*
* Copyright: Analog Devices Inc.
* Author: Roy Huang <[email protected]>
* Cliff Cai <[email protected]>
*/
/*
* WARNING:
*
* Because Analog Devices Inc. discontinued the ad1980 sound chip since
* Sep. 2009, this ad1980 driver is not maintained, tested and supported
* by ADI now.
*/
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/ac97_codec.h>
#include <sound/initval.h>
#include <sound/soc.h>
static const struct reg_default ad1980_reg_defaults[] = {
{ 0x02, 0x8000 },
{ 0x04, 0x8000 },
{ 0x06, 0x8000 },
{ 0x0c, 0x8008 },
{ 0x0e, 0x8008 },
{ 0x10, 0x8808 },
{ 0x12, 0x8808 },
{ 0x16, 0x8808 },
{ 0x18, 0x8808 },
{ 0x1a, 0x0000 },
{ 0x1c, 0x8000 },
{ 0x20, 0x0000 },
{ 0x28, 0x03c7 },
{ 0x2c, 0xbb80 },
{ 0x2e, 0xbb80 },
{ 0x30, 0xbb80 },
{ 0x32, 0xbb80 },
{ 0x36, 0x8080 },
{ 0x38, 0x8080 },
{ 0x3a, 0x2000 },
{ 0x60, 0x0000 },
{ 0x62, 0x0000 },
{ 0x72, 0x0000 },
{ 0x74, 0x1001 },
{ 0x76, 0x0000 },
};
static bool ad1980_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case AC97_RESET ... AC97_MASTER_MONO:
case AC97_PHONE ... AC97_CD:
case AC97_AUX ... AC97_GENERAL_PURPOSE:
case AC97_POWERDOWN ... AC97_PCM_LR_ADC_RATE:
case AC97_SPDIF:
case AC97_CODEC_CLASS_REV:
case AC97_PCI_SVID:
case AC97_AD_CODEC_CFG:
case AC97_AD_JACK_SPDIF:
case AC97_AD_SERIAL_CFG:
case AC97_VENDOR_ID1:
case AC97_VENDOR_ID2:
return true;
default:
return false;
}
}
static bool ad1980_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case AC97_VENDOR_ID1:
case AC97_VENDOR_ID2:
return false;
default:
return ad1980_readable_reg(dev, reg);
}
}
static const struct regmap_config ad1980_regmap_config = {
.reg_bits = 16,
.reg_stride = 2,
.val_bits = 16,
.max_register = 0x7e,
.cache_type = REGCACHE_MAPLE,
.volatile_reg = regmap_ac97_default_volatile,
.readable_reg = ad1980_readable_reg,
.writeable_reg = ad1980_writeable_reg,
.reg_defaults = ad1980_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(ad1980_reg_defaults),
};
static const char *ad1980_rec_sel[] = {"Mic", "CD", "NC", "AUX", "Line",
"Stereo Mix", "Mono Mix", "Phone"};
static SOC_ENUM_DOUBLE_DECL(ad1980_cap_src,
AC97_REC_SEL, 8, 0, ad1980_rec_sel);
static const struct snd_kcontrol_new ad1980_snd_ac97_controls[] = {
SOC_DOUBLE("Master Playback Volume", AC97_MASTER, 8, 0, 31, 1),
SOC_SINGLE("Master Playback Switch", AC97_MASTER, 15, 1, 1),
SOC_DOUBLE("Headphone Playback Volume", AC97_HEADPHONE, 8, 0, 31, 1),
SOC_SINGLE("Headphone Playback Switch", AC97_HEADPHONE, 15, 1, 1),
SOC_DOUBLE("PCM Playback Volume", AC97_PCM, 8, 0, 31, 1),
SOC_SINGLE("PCM Playback Switch", AC97_PCM, 15, 1, 1),
SOC_DOUBLE("PCM Capture Volume", AC97_REC_GAIN, 8, 0, 31, 0),
SOC_SINGLE("PCM Capture Switch", AC97_REC_GAIN, 15, 1, 1),
SOC_SINGLE("Mono Playback Volume", AC97_MASTER_MONO, 0, 31, 1),
SOC_SINGLE("Mono Playback Switch", AC97_MASTER_MONO, 15, 1, 1),
SOC_SINGLE("Phone Capture Volume", AC97_PHONE, 0, 31, 1),
SOC_SINGLE("Phone Capture Switch", AC97_PHONE, 15, 1, 1),
SOC_SINGLE("Mic Volume", AC97_MIC, 0, 31, 1),
SOC_SINGLE("Mic Switch", AC97_MIC, 15, 1, 1),
SOC_SINGLE("Stereo Mic Switch", AC97_AD_MISC, 6, 1, 0),
SOC_DOUBLE("Line HP Swap Switch", AC97_AD_MISC, 10, 5, 1, 0),
SOC_DOUBLE("Surround Playback Volume", AC97_SURROUND_MASTER, 8, 0, 31, 1),
SOC_DOUBLE("Surround Playback Switch", AC97_SURROUND_MASTER, 15, 7, 1, 1),
SOC_DOUBLE("Center/LFE Playback Volume", AC97_CENTER_LFE_MASTER, 8, 0, 31, 1),
SOC_DOUBLE("Center/LFE Playback Switch", AC97_CENTER_LFE_MASTER, 15, 7, 1, 1),
SOC_ENUM("Capture Source", ad1980_cap_src),
SOC_SINGLE("Mic Boost Switch", AC97_MIC, 6, 1, 0),
};
static const struct snd_soc_dapm_widget ad1980_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_INPUT("MIC2"),
SND_SOC_DAPM_INPUT("CD_L"),
SND_SOC_DAPM_INPUT("CD_R"),
SND_SOC_DAPM_INPUT("AUX_L"),
SND_SOC_DAPM_INPUT("AUX_R"),
SND_SOC_DAPM_INPUT("LINE_IN_L"),
SND_SOC_DAPM_INPUT("LINE_IN_R"),
SND_SOC_DAPM_OUTPUT("LFE_OUT"),
SND_SOC_DAPM_OUTPUT("CENTER_OUT"),
SND_SOC_DAPM_OUTPUT("LINE_OUT_L"),
SND_SOC_DAPM_OUTPUT("LINE_OUT_R"),
SND_SOC_DAPM_OUTPUT("MONO_OUT"),
SND_SOC_DAPM_OUTPUT("HP_OUT_L"),
SND_SOC_DAPM_OUTPUT("HP_OUT_R"),
};
static const struct snd_soc_dapm_route ad1980_dapm_routes[] = {
{ "Capture", NULL, "MIC1" },
{ "Capture", NULL, "MIC2" },
{ "Capture", NULL, "CD_L" },
{ "Capture", NULL, "CD_R" },
{ "Capture", NULL, "AUX_L" },
{ "Capture", NULL, "AUX_R" },
{ "Capture", NULL, "LINE_IN_L" },
{ "Capture", NULL, "LINE_IN_R" },
{ "LFE_OUT", NULL, "Playback" },
{ "CENTER_OUT", NULL, "Playback" },
{ "LINE_OUT_L", NULL, "Playback" },
{ "LINE_OUT_R", NULL, "Playback" },
{ "MONO_OUT", NULL, "Playback" },
{ "HP_OUT_L", NULL, "Playback" },
{ "HP_OUT_R", NULL, "Playback" },
};
static struct snd_soc_dai_driver ad1980_dai = {
.name = "ad1980-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 6,
.rates = SNDRV_PCM_RATE_48000,
.formats = SND_SOC_STD_AC97_FMTS, },
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_48000,
.formats = SND_SOC_STD_AC97_FMTS, },
};
#define AD1980_VENDOR_ID 0x41445300
#define AD1980_VENDOR_MASK 0xffffff00
static int ad1980_reset(struct snd_soc_component *component, int try_warm)
{
struct snd_ac97 *ac97 = snd_soc_component_get_drvdata(component);
unsigned int retry_cnt = 0;
int ret;
do {
ret = snd_ac97_reset(ac97, true, AD1980_VENDOR_ID,
AD1980_VENDOR_MASK);
if (ret >= 0)
return 0;
/*
* Set bit 16slot in register 74h, then every slot will has only
* 16 bits. This command is sent out in 20bit mode, in which
* case the first nibble of data is eaten by the addr. (Tag is
* always 16 bit)
*/
snd_soc_component_write(component, AC97_AD_SERIAL_CFG, 0x9900);
} while (retry_cnt++ < 10);
dev_err(component->dev, "Failed to reset: AC97 link error\n");
return -EIO;
}
static int ad1980_soc_probe(struct snd_soc_component *component)
{
struct snd_ac97 *ac97;
struct regmap *regmap;
int ret;
u16 vendor_id2;
u16 ext_status;
ac97 = snd_soc_new_ac97_component(component, 0, 0);
if (IS_ERR(ac97)) {
ret = PTR_ERR(ac97);
dev_err(component->dev, "Failed to register AC97 component: %d\n", ret);
return ret;
}
regmap = regmap_init_ac97(ac97, &ad1980_regmap_config);
if (IS_ERR(regmap)) {
ret = PTR_ERR(regmap);
goto err_free_ac97;
}
snd_soc_component_init_regmap(component, regmap);
snd_soc_component_set_drvdata(component, ac97);
ret = ad1980_reset(component, 0);
if (ret < 0)
goto reset_err;
vendor_id2 = snd_soc_component_read(component, AC97_VENDOR_ID2);
if (vendor_id2 == 0x5374) {
dev_warn(component->dev,
"Found AD1981 - only 2/2 IN/OUT Channels supported\n");
}
/* unmute captures and playbacks volume */
snd_soc_component_write(component, AC97_MASTER, 0x0000);
snd_soc_component_write(component, AC97_PCM, 0x0000);
snd_soc_component_write(component, AC97_REC_GAIN, 0x0000);
snd_soc_component_write(component, AC97_CENTER_LFE_MASTER, 0x0000);
snd_soc_component_write(component, AC97_SURROUND_MASTER, 0x0000);
/*power on LFE/CENTER/Surround DACs*/
ext_status = snd_soc_component_read(component, AC97_EXTENDED_STATUS);
snd_soc_component_write(component, AC97_EXTENDED_STATUS, ext_status&~0x3800);
return 0;
reset_err:
snd_soc_component_exit_regmap(component);
err_free_ac97:
snd_soc_free_ac97_component(ac97);
return ret;
}
static void ad1980_soc_remove(struct snd_soc_component *component)
{
struct snd_ac97 *ac97 = snd_soc_component_get_drvdata(component);
snd_soc_component_exit_regmap(component);
snd_soc_free_ac97_component(ac97);
}
static const struct snd_soc_component_driver soc_component_dev_ad1980 = {
.probe = ad1980_soc_probe,
.remove = ad1980_soc_remove,
.controls = ad1980_snd_ac97_controls,
.num_controls = ARRAY_SIZE(ad1980_snd_ac97_controls),
.dapm_widgets = ad1980_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(ad1980_dapm_widgets),
.dapm_routes = ad1980_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(ad1980_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int ad1980_probe(struct platform_device *pdev)
{
return devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_ad1980, &ad1980_dai, 1);
}
static struct platform_driver ad1980_codec_driver = {
.driver = {
.name = "ad1980",
},
.probe = ad1980_probe,
};
module_platform_driver(ad1980_codec_driver);
MODULE_DESCRIPTION("ASoC ad1980 driver (Obsolete)");
MODULE_AUTHOR("Roy Huang, Cliff Cai");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/ad1980.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8804-spi.c -- WM8804 S/PDIF transceiver driver - SPI
*
* Copyright 2015 Cirrus Logic Inc
*
* Author: Charles Keepax <[email protected]>
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/spi/spi.h>
#include "wm8804.h"
static int wm8804_spi_probe(struct spi_device *spi)
{
struct regmap *regmap;
regmap = devm_regmap_init_spi(spi, &wm8804_regmap_config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return wm8804_probe(&spi->dev, regmap);
}
static void wm8804_spi_remove(struct spi_device *spi)
{
wm8804_remove(&spi->dev);
}
static const struct of_device_id wm8804_of_match[] = {
{ .compatible = "wlf,wm8804", },
{ }
};
MODULE_DEVICE_TABLE(of, wm8804_of_match);
static struct spi_driver wm8804_spi_driver = {
.driver = {
.name = "wm8804",
.pm = &wm8804_pm,
.of_match_table = wm8804_of_match,
},
.probe = wm8804_spi_probe,
.remove = wm8804_spi_remove
};
module_spi_driver(wm8804_spi_driver);
MODULE_DESCRIPTION("ASoC WM8804 driver - SPI");
MODULE_AUTHOR("Charles Keepax <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8804-spi.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* lm49453.c - LM49453 ALSA Soc Audio driver
*
* Copyright (c) 2012 Texas Instruments, Inc
*
* Initially based on sound/soc/codecs/wm8350.c
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/tlv.h>
#include <sound/jack.h>
#include <sound/initval.h>
#include <asm/div64.h>
#include "lm49453.h"
static const struct reg_default lm49453_reg_defs[] = {
{ 0, 0x00 },
{ 1, 0x00 },
{ 2, 0x00 },
{ 3, 0x00 },
{ 4, 0x00 },
{ 5, 0x00 },
{ 6, 0x00 },
{ 7, 0x00 },
{ 8, 0x00 },
{ 9, 0x00 },
{ 10, 0x00 },
{ 11, 0x00 },
{ 12, 0x00 },
{ 13, 0x00 },
{ 14, 0x00 },
{ 15, 0x00 },
{ 16, 0x00 },
{ 17, 0x00 },
{ 18, 0x00 },
{ 19, 0x00 },
{ 20, 0x00 },
{ 21, 0x00 },
{ 22, 0x00 },
{ 23, 0x00 },
{ 32, 0x00 },
{ 33, 0x00 },
{ 35, 0x00 },
{ 36, 0x00 },
{ 37, 0x00 },
{ 46, 0x00 },
{ 48, 0x00 },
{ 49, 0x00 },
{ 51, 0x00 },
{ 56, 0x00 },
{ 58, 0x00 },
{ 59, 0x00 },
{ 60, 0x00 },
{ 61, 0x00 },
{ 62, 0x00 },
{ 63, 0x00 },
{ 64, 0x00 },
{ 65, 0x00 },
{ 66, 0x00 },
{ 67, 0x00 },
{ 68, 0x00 },
{ 69, 0x00 },
{ 70, 0x00 },
{ 71, 0x00 },
{ 72, 0x00 },
{ 73, 0x00 },
{ 74, 0x00 },
{ 75, 0x00 },
{ 76, 0x00 },
{ 77, 0x00 },
{ 78, 0x00 },
{ 79, 0x00 },
{ 80, 0x00 },
{ 81, 0x00 },
{ 82, 0x00 },
{ 83, 0x00 },
{ 85, 0x00 },
{ 85, 0x00 },
{ 86, 0x00 },
{ 87, 0x00 },
{ 88, 0x00 },
{ 89, 0x00 },
{ 90, 0x00 },
{ 91, 0x00 },
{ 92, 0x00 },
{ 93, 0x00 },
{ 94, 0x00 },
{ 95, 0x00 },
{ 96, 0x01 },
{ 97, 0x00 },
{ 98, 0x00 },
{ 99, 0x00 },
{ 100, 0x00 },
{ 101, 0x00 },
{ 102, 0x00 },
{ 103, 0x01 },
{ 104, 0x01 },
{ 105, 0x00 },
{ 106, 0x01 },
{ 107, 0x00 },
{ 108, 0x00 },
{ 109, 0x00 },
{ 110, 0x00 },
{ 111, 0x02 },
{ 112, 0x02 },
{ 113, 0x00 },
{ 121, 0x80 },
{ 122, 0xBB },
{ 123, 0x80 },
{ 124, 0xBB },
{ 128, 0x00 },
{ 130, 0x00 },
{ 131, 0x00 },
{ 132, 0x00 },
{ 133, 0x0A },
{ 134, 0x0A },
{ 135, 0x0A },
{ 136, 0x0F },
{ 137, 0x00 },
{ 138, 0x73 },
{ 139, 0x33 },
{ 140, 0x73 },
{ 141, 0x33 },
{ 142, 0x73 },
{ 143, 0x33 },
{ 144, 0x73 },
{ 145, 0x33 },
{ 146, 0x73 },
{ 147, 0x33 },
{ 148, 0x73 },
{ 149, 0x33 },
{ 150, 0x73 },
{ 151, 0x33 },
{ 152, 0x00 },
{ 153, 0x00 },
{ 154, 0x00 },
{ 155, 0x00 },
{ 176, 0x00 },
{ 177, 0x00 },
{ 178, 0x00 },
{ 179, 0x00 },
{ 180, 0x00 },
{ 181, 0x00 },
{ 182, 0x00 },
{ 183, 0x00 },
{ 184, 0x00 },
{ 185, 0x00 },
{ 186, 0x00 },
{ 187, 0x00 },
{ 188, 0x00 },
{ 189, 0x00 },
{ 208, 0x06 },
{ 209, 0x00 },
{ 210, 0x08 },
{ 211, 0x54 },
{ 212, 0x14 },
{ 213, 0x0d },
{ 214, 0x0d },
{ 215, 0x14 },
{ 216, 0x60 },
{ 221, 0x00 },
{ 222, 0x00 },
{ 223, 0x00 },
{ 224, 0x00 },
{ 248, 0x00 },
{ 249, 0x00 },
{ 250, 0x00 },
{ 255, 0x00 },
};
/* codec private data */
struct lm49453_priv {
struct regmap *regmap;
};
/* capture path controls */
static const char *lm49453_mic2mode_text[] = {"Single Ended", "Differential"};
static SOC_ENUM_SINGLE_DECL(lm49453_mic2mode_enum, LM49453_P0_MICR_REG, 5,
lm49453_mic2mode_text);
static const char *lm49453_dmic_cfg_text[] = {"DMICDAT1", "DMICDAT2"};
static SOC_ENUM_SINGLE_DECL(lm49453_dmic12_cfg_enum,
LM49453_P0_DIGITAL_MIC1_CONFIG_REG, 7,
lm49453_dmic_cfg_text);
static SOC_ENUM_SINGLE_DECL(lm49453_dmic34_cfg_enum,
LM49453_P0_DIGITAL_MIC2_CONFIG_REG, 7,
lm49453_dmic_cfg_text);
/* MUX Controls */
static const char *lm49453_adcl_mux_text[] = { "MIC1", "Aux_L" };
static const char *lm49453_adcr_mux_text[] = { "MIC2", "Aux_R" };
static SOC_ENUM_SINGLE_DECL(lm49453_adcl_enum,
LM49453_P0_ANALOG_MIXER_ADC_REG, 0,
lm49453_adcl_mux_text);
static SOC_ENUM_SINGLE_DECL(lm49453_adcr_enum,
LM49453_P0_ANALOG_MIXER_ADC_REG, 1,
lm49453_adcr_mux_text);
static const struct snd_kcontrol_new lm49453_adcl_mux_control =
SOC_DAPM_ENUM("ADC Left Mux", lm49453_adcl_enum);
static const struct snd_kcontrol_new lm49453_adcr_mux_control =
SOC_DAPM_ENUM("ADC Right Mux", lm49453_adcr_enum);
static const struct snd_kcontrol_new lm49453_headset_left_mixer[] = {
SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHPL1_REG, 0, 1, 0),
SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHPL1_REG, 1, 1, 0),
SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHPL1_REG, 2, 1, 0),
SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHPL1_REG, 3, 1, 0),
SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHPL1_REG, 4, 1, 0),
SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHPL1_REG, 5, 1, 0),
SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHPL1_REG, 6, 1, 0),
SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHPL1_REG, 7, 1, 0),
SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHPL2_REG, 0, 1, 0),
SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHPL2_REG, 1, 1, 0),
SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHPL2_REG, 2, 1, 0),
SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHPL2_REG, 3, 1, 0),
SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHPL2_REG, 4, 1, 0),
SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHPL2_REG, 5, 1, 0),
SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHPL2_REG, 6, 1, 0),
SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHPL2_REG, 7, 1, 0),
SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 0, 0, 0),
};
static const struct snd_kcontrol_new lm49453_headset_right_mixer[] = {
SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHPR1_REG, 0, 1, 0),
SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHPR1_REG, 1, 1, 0),
SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHPR1_REG, 2, 1, 0),
SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHPR1_REG, 3, 1, 0),
SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHPR1_REG, 4, 1, 0),
SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHPR1_REG, 5, 1, 0),
SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHPR1_REG, 6, 1, 0),
SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHPR1_REG, 7, 1, 0),
SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHPR2_REG, 0, 1, 0),
SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHPR2_REG, 1, 1, 0),
SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHPR2_REG, 2, 1, 0),
SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHPR2_REG, 3, 1, 0),
SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHPR2_REG, 4, 1, 0),
SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHPR2_REG, 5, 1, 0),
SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHPR2_REG, 6, 1, 0),
SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHPR2_REG, 7, 1, 0),
SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 1, 0, 0),
};
static const struct snd_kcontrol_new lm49453_speaker_left_mixer[] = {
SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLSL1_REG, 0, 1, 0),
SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLSL1_REG, 1, 1, 0),
SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLSL1_REG, 2, 1, 0),
SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLSL1_REG, 3, 1, 0),
SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLSL1_REG, 4, 1, 0),
SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLSL1_REG, 5, 1, 0),
SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLSL1_REG, 6, 1, 0),
SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLSL1_REG, 7, 1, 0),
SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLSL2_REG, 0, 1, 0),
SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLSL2_REG, 1, 1, 0),
SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLSL2_REG, 2, 1, 0),
SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLSL2_REG, 3, 1, 0),
SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLSL2_REG, 4, 1, 0),
SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLSL2_REG, 5, 1, 0),
SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLSL2_REG, 6, 1, 0),
SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLSL2_REG, 7, 1, 0),
SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 2, 0, 0),
};
static const struct snd_kcontrol_new lm49453_speaker_right_mixer[] = {
SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLSR1_REG, 0, 1, 0),
SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLSR1_REG, 1, 1, 0),
SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLSR1_REG, 2, 1, 0),
SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLSR1_REG, 3, 1, 0),
SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLSR1_REG, 4, 1, 0),
SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLSR1_REG, 5, 1, 0),
SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLSR1_REG, 6, 1, 0),
SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLSR1_REG, 7, 1, 0),
SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLSR2_REG, 0, 1, 0),
SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLSR2_REG, 1, 1, 0),
SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLSR2_REG, 2, 1, 0),
SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLSR2_REG, 3, 1, 0),
SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLSR2_REG, 4, 1, 0),
SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLSR2_REG, 5, 1, 0),
SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLSR2_REG, 6, 1, 0),
SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLSR2_REG, 7, 1, 0),
SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 3, 0, 0),
};
static const struct snd_kcontrol_new lm49453_haptic_left_mixer[] = {
SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHAL1_REG, 0, 1, 0),
SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHAL1_REG, 1, 1, 0),
SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHAL1_REG, 2, 1, 0),
SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHAL1_REG, 3, 1, 0),
SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHAL1_REG, 4, 1, 0),
SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHAL1_REG, 5, 1, 0),
SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHAL1_REG, 6, 1, 0),
SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHAL1_REG, 7, 1, 0),
SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHAL2_REG, 0, 1, 0),
SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHAL2_REG, 1, 1, 0),
SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHAL2_REG, 2, 1, 0),
SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHAL2_REG, 3, 1, 0),
SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHAL2_REG, 4, 1, 0),
SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHAL2_REG, 5, 1, 0),
SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHAL2_REG, 6, 1, 0),
SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHAL2_REG, 7, 1, 0),
SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 4, 0, 0),
};
static const struct snd_kcontrol_new lm49453_haptic_right_mixer[] = {
SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHAR1_REG, 0, 1, 0),
SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHAR1_REG, 1, 1, 0),
SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHAR1_REG, 2, 1, 0),
SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHAR1_REG, 3, 1, 0),
SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHAR1_REG, 4, 1, 0),
SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHAR1_REG, 5, 1, 0),
SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHAR1_REG, 6, 1, 0),
SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHAR1_REG, 7, 1, 0),
SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHAR2_REG, 0, 1, 0),
SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHAR2_REG, 1, 1, 0),
SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHAR2_REG, 2, 1, 0),
SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHAR2_REG, 3, 1, 0),
SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHAR2_REG, 4, 1, 0),
SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHAR2_REG, 5, 1, 0),
SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHAR2_REG, 6, 1, 0),
SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHAR2_REG, 7, 1, 0),
SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 5, 0, 0),
};
static const struct snd_kcontrol_new lm49453_lineout_left_mixer[] = {
SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLOL1_REG, 0, 1, 0),
SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLOL1_REG, 1, 1, 0),
SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLOL1_REG, 2, 1, 0),
SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLOL1_REG, 3, 1, 0),
SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLOL1_REG, 4, 1, 0),
SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLOL1_REG, 5, 1, 0),
SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLOL1_REG, 6, 1, 0),
SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLOL1_REG, 7, 1, 0),
SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLOL2_REG, 0, 1, 0),
SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLOL2_REG, 1, 1, 0),
SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLOL2_REG, 2, 1, 0),
SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLOL2_REG, 3, 1, 0),
SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLOL2_REG, 4, 1, 0),
SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLOL2_REG, 5, 1, 0),
SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLOL2_REG, 6, 1, 0),
SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLOL2_REG, 7, 1, 0),
SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 6, 0, 0),
};
static const struct snd_kcontrol_new lm49453_lineout_right_mixer[] = {
SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLOR1_REG, 0, 1, 0),
SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLOR1_REG, 1, 1, 0),
SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLOR1_REG, 2, 1, 0),
SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLOR1_REG, 3, 1, 0),
SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLOR1_REG, 4, 1, 0),
SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLOR1_REG, 5, 1, 0),
SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLOR1_REG, 6, 1, 0),
SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLOR1_REG, 7, 1, 0),
SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLOR2_REG, 0, 1, 0),
SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLOR2_REG, 1, 1, 0),
SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLOR2_REG, 2, 1, 0),
SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLOR2_REG, 3, 1, 0),
SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLOR2_REG, 4, 1, 0),
SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLOR2_REG, 5, 1, 0),
SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLOR2_REG, 6, 1, 0),
SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLOR2_REG, 7, 1, 0),
SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 7, 0, 0),
};
static const struct snd_kcontrol_new lm49453_port1_tx1_mixer[] = {
SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX1_REG, 0, 1, 0),
SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX1_REG, 1, 1, 0),
SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX1_REG, 2, 1, 0),
SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX1_REG, 3, 1, 0),
SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX1_REG, 4, 1, 0),
SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX1_REG, 5, 1, 0),
SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_PORT1_TX1_REG, 6, 1, 0),
SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_PORT1_TX1_REG, 7, 1, 0),
};
static const struct snd_kcontrol_new lm49453_port1_tx2_mixer[] = {
SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX2_REG, 0, 1, 0),
SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX2_REG, 1, 1, 0),
SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX2_REG, 2, 1, 0),
SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX2_REG, 3, 1, 0),
SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX2_REG, 4, 1, 0),
SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX2_REG, 5, 1, 0),
SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_PORT1_TX2_REG, 6, 1, 0),
SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_PORT1_TX2_REG, 7, 1, 0),
};
static const struct snd_kcontrol_new lm49453_port1_tx3_mixer[] = {
SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX3_REG, 0, 1, 0),
SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX3_REG, 1, 1, 0),
SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX3_REG, 2, 1, 0),
SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX3_REG, 3, 1, 0),
SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX3_REG, 4, 1, 0),
SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX3_REG, 5, 1, 0),
SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_PORT1_TX3_REG, 6, 1, 0),
};
static const struct snd_kcontrol_new lm49453_port1_tx4_mixer[] = {
SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX4_REG, 0, 1, 0),
SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX4_REG, 1, 1, 0),
SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX4_REG, 2, 1, 0),
SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX4_REG, 3, 1, 0),
SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX4_REG, 4, 1, 0),
SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX4_REG, 5, 1, 0),
SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_PORT1_TX4_REG, 6, 1, 0),
};
static const struct snd_kcontrol_new lm49453_port1_tx5_mixer[] = {
SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX5_REG, 0, 1, 0),
SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX5_REG, 1, 1, 0),
SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX5_REG, 2, 1, 0),
SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX5_REG, 3, 1, 0),
SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX5_REG, 4, 1, 0),
SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX5_REG, 5, 1, 0),
SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_PORT1_TX5_REG, 6, 1, 0),
};
static const struct snd_kcontrol_new lm49453_port1_tx6_mixer[] = {
SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX6_REG, 0, 1, 0),
SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX6_REG, 1, 1, 0),
SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX6_REG, 2, 1, 0),
SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX6_REG, 3, 1, 0),
SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX6_REG, 4, 1, 0),
SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX6_REG, 5, 1, 0),
SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_PORT1_TX6_REG, 6, 1, 0),
};
static const struct snd_kcontrol_new lm49453_port1_tx7_mixer[] = {
SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX7_REG, 0, 1, 0),
SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX7_REG, 1, 1, 0),
SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX7_REG, 2, 1, 0),
SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX7_REG, 3, 1, 0),
SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX7_REG, 4, 1, 0),
SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX7_REG, 5, 1, 0),
SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_PORT1_TX7_REG, 6, 1, 0),
};
static const struct snd_kcontrol_new lm49453_port1_tx8_mixer[] = {
SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX8_REG, 0, 1, 0),
SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX8_REG, 1, 1, 0),
SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX8_REG, 2, 1, 0),
SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX8_REG, 3, 1, 0),
SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX8_REG, 4, 1, 0),
SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX8_REG, 5, 1, 0),
SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_PORT1_TX8_REG, 6, 1, 0),
};
static const struct snd_kcontrol_new lm49453_port2_tx1_mixer[] = {
SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT2_TX1_REG, 0, 1, 0),
SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT2_TX1_REG, 1, 1, 0),
SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT2_TX1_REG, 2, 1, 0),
SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT2_TX1_REG, 3, 1, 0),
SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT2_TX1_REG, 4, 1, 0),
SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT2_TX1_REG, 5, 1, 0),
SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_PORT2_TX1_REG, 6, 1, 0),
SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_PORT2_TX1_REG, 7, 1, 0),
};
static const struct snd_kcontrol_new lm49453_port2_tx2_mixer[] = {
SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT2_TX2_REG, 0, 1, 0),
SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT2_TX2_REG, 1, 1, 0),
SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT2_TX2_REG, 2, 1, 0),
SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT2_TX2_REG, 3, 1, 0),
SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT2_TX2_REG, 4, 1, 0),
SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT2_TX2_REG, 5, 1, 0),
SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_PORT2_TX2_REG, 6, 1, 0),
SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_PORT2_TX2_REG, 7, 1, 0),
};
/* TLV Declarations */
static const DECLARE_TLV_DB_SCALE(adc_dac_tlv, -7650, 150, 1);
static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 200, 1);
static const DECLARE_TLV_DB_SCALE(port_tlv, -1800, 600, 0);
static const DECLARE_TLV_DB_SCALE(stn_tlv, -7200, 150, 0);
static const struct snd_kcontrol_new lm49453_sidetone_mixer_controls[] = {
/* Sidetone supports mono only */
SOC_DAPM_SINGLE_TLV("Sidetone ADCL Volume", LM49453_P0_STN_VOL_ADCL_REG,
0, 0x3F, 0, stn_tlv),
SOC_DAPM_SINGLE_TLV("Sidetone ADCR Volume", LM49453_P0_STN_VOL_ADCR_REG,
0, 0x3F, 0, stn_tlv),
SOC_DAPM_SINGLE_TLV("Sidetone DMIC1L Volume", LM49453_P0_STN_VOL_DMIC1L_REG,
0, 0x3F, 0, stn_tlv),
SOC_DAPM_SINGLE_TLV("Sidetone DMIC1R Volume", LM49453_P0_STN_VOL_DMIC1R_REG,
0, 0x3F, 0, stn_tlv),
SOC_DAPM_SINGLE_TLV("Sidetone DMIC2L Volume", LM49453_P0_STN_VOL_DMIC2L_REG,
0, 0x3F, 0, stn_tlv),
SOC_DAPM_SINGLE_TLV("Sidetone DMIC2R Volume", LM49453_P0_STN_VOL_DMIC2R_REG,
0, 0x3F, 0, stn_tlv),
};
static const struct snd_kcontrol_new lm49453_snd_controls[] = {
/* mic1 and mic2 supports mono only */
SOC_SINGLE_TLV("Mic1 Volume", LM49453_P0_MICL_REG, 0, 15, 0, mic_tlv),
SOC_SINGLE_TLV("Mic2 Volume", LM49453_P0_MICR_REG, 0, 15, 0, mic_tlv),
SOC_SINGLE_TLV("ADCL Volume", LM49453_P0_ADC_LEVELL_REG, 0, 63,
0, adc_dac_tlv),
SOC_SINGLE_TLV("ADCR Volume", LM49453_P0_ADC_LEVELR_REG, 0, 63,
0, adc_dac_tlv),
SOC_DOUBLE_R_TLV("DMIC1 Volume", LM49453_P0_DMIC1_LEVELL_REG,
LM49453_P0_DMIC1_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
SOC_DOUBLE_R_TLV("DMIC2 Volume", LM49453_P0_DMIC2_LEVELL_REG,
LM49453_P0_DMIC2_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
SOC_DAPM_ENUM("Mic2Mode", lm49453_mic2mode_enum),
SOC_DAPM_ENUM("DMIC12 SRC", lm49453_dmic12_cfg_enum),
SOC_DAPM_ENUM("DMIC34 SRC", lm49453_dmic34_cfg_enum),
/* Capture path filter enable */
SOC_SINGLE("DMIC1 HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG,
0, 1, 0),
SOC_SINGLE("DMIC2 HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG,
1, 1, 0),
SOC_SINGLE("ADC HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG,
2, 1, 0),
SOC_DOUBLE_R_TLV("DAC HP Volume", LM49453_P0_DAC_HP_LEVELL_REG,
LM49453_P0_DAC_HP_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
SOC_DOUBLE_R_TLV("DAC LO Volume", LM49453_P0_DAC_LO_LEVELL_REG,
LM49453_P0_DAC_LO_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
SOC_DOUBLE_R_TLV("DAC LS Volume", LM49453_P0_DAC_LS_LEVELL_REG,
LM49453_P0_DAC_LS_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
SOC_DOUBLE_R_TLV("DAC HA Volume", LM49453_P0_DAC_HA_LEVELL_REG,
LM49453_P0_DAC_HA_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
SOC_SINGLE_TLV("EP Volume", LM49453_P0_DAC_LS_LEVELL_REG,
0, 63, 0, adc_dac_tlv),
SOC_SINGLE_TLV("PORT1_1_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
0, 3, 0, port_tlv),
SOC_SINGLE_TLV("PORT1_2_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
2, 3, 0, port_tlv),
SOC_SINGLE_TLV("PORT1_3_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
4, 3, 0, port_tlv),
SOC_SINGLE_TLV("PORT1_4_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
6, 3, 0, port_tlv),
SOC_SINGLE_TLV("PORT1_5_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
0, 3, 0, port_tlv),
SOC_SINGLE_TLV("PORT1_6_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
2, 3, 0, port_tlv),
SOC_SINGLE_TLV("PORT1_7_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
4, 3, 0, port_tlv),
SOC_SINGLE_TLV("PORT1_8_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
6, 3, 0, port_tlv),
SOC_SINGLE_TLV("PORT2_1_RX_LVL Volume", LM49453_P0_PORT2_RX_LVL_REG,
0, 3, 0, port_tlv),
SOC_SINGLE_TLV("PORT2_2_RX_LVL Volume", LM49453_P0_PORT2_RX_LVL_REG,
2, 3, 0, port_tlv),
SOC_SINGLE("Port1 Playback Switch", LM49453_P0_AUDIO_PORT1_BASIC_REG,
1, 1, 0),
SOC_SINGLE("Port2 Playback Switch", LM49453_P0_AUDIO_PORT2_BASIC_REG,
1, 1, 0),
SOC_SINGLE("Port1 Capture Switch", LM49453_P0_AUDIO_PORT1_BASIC_REG,
2, 1, 0),
SOC_SINGLE("Port2 Capture Switch", LM49453_P0_AUDIO_PORT2_BASIC_REG,
2, 1, 0)
};
/* DAPM widgets */
static const struct snd_soc_dapm_widget lm49453_dapm_widgets[] = {
/* All end points HP,EP, LS, Lineout and Haptic */
SND_SOC_DAPM_OUTPUT("HPOUTL"),
SND_SOC_DAPM_OUTPUT("HPOUTR"),
SND_SOC_DAPM_OUTPUT("EPOUT"),
SND_SOC_DAPM_OUTPUT("LSOUTL"),
SND_SOC_DAPM_OUTPUT("LSOUTR"),
SND_SOC_DAPM_OUTPUT("LOOUTR"),
SND_SOC_DAPM_OUTPUT("LOOUTL"),
SND_SOC_DAPM_OUTPUT("HAOUTL"),
SND_SOC_DAPM_OUTPUT("HAOUTR"),
SND_SOC_DAPM_INPUT("AMIC1"),
SND_SOC_DAPM_INPUT("AMIC2"),
SND_SOC_DAPM_INPUT("DMIC1DAT"),
SND_SOC_DAPM_INPUT("DMIC2DAT"),
SND_SOC_DAPM_INPUT("AUXL"),
SND_SOC_DAPM_INPUT("AUXR"),
SND_SOC_DAPM_PGA("PORT1_1_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("PORT1_2_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("PORT1_3_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("PORT1_4_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("PORT1_5_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("PORT1_6_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("PORT1_7_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("PORT1_8_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("PORT2_1_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("PORT2_2_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("AMIC1Bias", LM49453_P0_MICL_REG, 6, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("AMIC2Bias", LM49453_P0_MICR_REG, 6, 0, NULL, 0),
/* playback path driver enables */
SND_SOC_DAPM_OUT_DRV("Headset Switch",
LM49453_P0_PMC_SETUP_REG, 0, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("Earpiece Switch",
LM49453_P0_EP_REG, 0, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("Speaker Left Switch",
LM49453_P0_DIS_PKVL_FB_REG, 0, 1, NULL, 0),
SND_SOC_DAPM_OUT_DRV("Speaker Right Switch",
LM49453_P0_DIS_PKVL_FB_REG, 1, 1, NULL, 0),
SND_SOC_DAPM_OUT_DRV("Haptic Left Switch",
LM49453_P0_DIS_PKVL_FB_REG, 2, 1, NULL, 0),
SND_SOC_DAPM_OUT_DRV("Haptic Right Switch",
LM49453_P0_DIS_PKVL_FB_REG, 3, 1, NULL, 0),
/* DAC */
SND_SOC_DAPM_DAC("HPL DAC", "Headset", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("HPR DAC", "Headset", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("LSL DAC", "Speaker", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("LSR DAC", "Speaker", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("HAL DAC", "Haptic", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("HAR DAC", "Haptic", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("LOL DAC", "Lineout", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("LOR DAC", "Lineout", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_PGA("AUXL Input",
LM49453_P0_ANALOG_MIXER_ADC_REG, 2, 0, NULL, 0),
SND_SOC_DAPM_PGA("AUXR Input",
LM49453_P0_ANALOG_MIXER_ADC_REG, 3, 0, NULL, 0),
SND_SOC_DAPM_PGA("Sidetone", SND_SOC_NOPM, 0, 0, NULL, 0),
/* ADC */
SND_SOC_DAPM_ADC("DMIC1 Left", "Capture", SND_SOC_NOPM, 1, 0),
SND_SOC_DAPM_ADC("DMIC1 Right", "Capture", SND_SOC_NOPM, 1, 0),
SND_SOC_DAPM_ADC("DMIC2 Left", "Capture", SND_SOC_NOPM, 1, 0),
SND_SOC_DAPM_ADC("DMIC2 Right", "Capture", SND_SOC_NOPM, 1, 0),
SND_SOC_DAPM_ADC("ADC Left", "Capture", SND_SOC_NOPM, 1, 0),
SND_SOC_DAPM_ADC("ADC Right", "Capture", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_MUX("ADCL Mux", SND_SOC_NOPM, 0, 0,
&lm49453_adcl_mux_control),
SND_SOC_DAPM_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0,
&lm49453_adcr_mux_control),
SND_SOC_DAPM_MUX("Mic1 Input",
SND_SOC_NOPM, 0, 0, &lm49453_adcl_mux_control),
SND_SOC_DAPM_MUX("Mic2 Input",
SND_SOC_NOPM, 0, 0, &lm49453_adcr_mux_control),
/* AIF */
SND_SOC_DAPM_AIF_IN("PORT1_SDI", NULL, 0,
LM49453_P0_PULL_CONFIG1_REG, 2, 0),
SND_SOC_DAPM_AIF_IN("PORT2_SDI", NULL, 0,
LM49453_P0_PULL_CONFIG1_REG, 6, 0),
SND_SOC_DAPM_AIF_OUT("PORT1_SDO", NULL, 0,
LM49453_P0_PULL_CONFIG1_REG, 3, 0),
SND_SOC_DAPM_AIF_OUT("PORT2_SDO", NULL, 0,
LM49453_P0_PULL_CONFIG1_REG, 7, 0),
/* Port1 TX controls */
SND_SOC_DAPM_OUT_DRV("P1_1_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("P1_2_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("P1_3_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("P1_4_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("P1_5_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("P1_6_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("P1_7_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("P1_8_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
/* Port2 TX controls */
SND_SOC_DAPM_OUT_DRV("P2_1_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("P2_2_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
/* Sidetone Mixer */
SND_SOC_DAPM_MIXER("Sidetone Mixer", SND_SOC_NOPM, 0, 0,
lm49453_sidetone_mixer_controls,
ARRAY_SIZE(lm49453_sidetone_mixer_controls)),
/* DAC MIXERS */
SND_SOC_DAPM_MIXER("HPL Mixer", SND_SOC_NOPM, 0, 0,
lm49453_headset_left_mixer,
ARRAY_SIZE(lm49453_headset_left_mixer)),
SND_SOC_DAPM_MIXER("HPR Mixer", SND_SOC_NOPM, 0, 0,
lm49453_headset_right_mixer,
ARRAY_SIZE(lm49453_headset_right_mixer)),
SND_SOC_DAPM_MIXER("LOL Mixer", SND_SOC_NOPM, 0, 0,
lm49453_lineout_left_mixer,
ARRAY_SIZE(lm49453_lineout_left_mixer)),
SND_SOC_DAPM_MIXER("LOR Mixer", SND_SOC_NOPM, 0, 0,
lm49453_lineout_right_mixer,
ARRAY_SIZE(lm49453_lineout_right_mixer)),
SND_SOC_DAPM_MIXER("LSL Mixer", SND_SOC_NOPM, 0, 0,
lm49453_speaker_left_mixer,
ARRAY_SIZE(lm49453_speaker_left_mixer)),
SND_SOC_DAPM_MIXER("LSR Mixer", SND_SOC_NOPM, 0, 0,
lm49453_speaker_right_mixer,
ARRAY_SIZE(lm49453_speaker_right_mixer)),
SND_SOC_DAPM_MIXER("HAL Mixer", SND_SOC_NOPM, 0, 0,
lm49453_haptic_left_mixer,
ARRAY_SIZE(lm49453_haptic_left_mixer)),
SND_SOC_DAPM_MIXER("HAR Mixer", SND_SOC_NOPM, 0, 0,
lm49453_haptic_right_mixer,
ARRAY_SIZE(lm49453_haptic_right_mixer)),
/* Capture Mixer */
SND_SOC_DAPM_MIXER("Port1_1 Mixer", SND_SOC_NOPM, 0, 0,
lm49453_port1_tx1_mixer,
ARRAY_SIZE(lm49453_port1_tx1_mixer)),
SND_SOC_DAPM_MIXER("Port1_2 Mixer", SND_SOC_NOPM, 0, 0,
lm49453_port1_tx2_mixer,
ARRAY_SIZE(lm49453_port1_tx2_mixer)),
SND_SOC_DAPM_MIXER("Port1_3 Mixer", SND_SOC_NOPM, 0, 0,
lm49453_port1_tx3_mixer,
ARRAY_SIZE(lm49453_port1_tx3_mixer)),
SND_SOC_DAPM_MIXER("Port1_4 Mixer", SND_SOC_NOPM, 0, 0,
lm49453_port1_tx4_mixer,
ARRAY_SIZE(lm49453_port1_tx4_mixer)),
SND_SOC_DAPM_MIXER("Port1_5 Mixer", SND_SOC_NOPM, 0, 0,
lm49453_port1_tx5_mixer,
ARRAY_SIZE(lm49453_port1_tx5_mixer)),
SND_SOC_DAPM_MIXER("Port1_6 Mixer", SND_SOC_NOPM, 0, 0,
lm49453_port1_tx6_mixer,
ARRAY_SIZE(lm49453_port1_tx6_mixer)),
SND_SOC_DAPM_MIXER("Port1_7 Mixer", SND_SOC_NOPM, 0, 0,
lm49453_port1_tx7_mixer,
ARRAY_SIZE(lm49453_port1_tx7_mixer)),
SND_SOC_DAPM_MIXER("Port1_8 Mixer", SND_SOC_NOPM, 0, 0,
lm49453_port1_tx8_mixer,
ARRAY_SIZE(lm49453_port1_tx8_mixer)),
SND_SOC_DAPM_MIXER("Port2_1 Mixer", SND_SOC_NOPM, 0, 0,
lm49453_port2_tx1_mixer,
ARRAY_SIZE(lm49453_port2_tx1_mixer)),
SND_SOC_DAPM_MIXER("Port2_2 Mixer", SND_SOC_NOPM, 0, 0,
lm49453_port2_tx2_mixer,
ARRAY_SIZE(lm49453_port2_tx2_mixer)),
};
static const struct snd_soc_dapm_route lm49453_audio_map[] = {
/* Port SDI mapping */
{ "PORT1_1_RX", "Port1 Playback Switch", "PORT1_SDI" },
{ "PORT1_2_RX", "Port1 Playback Switch", "PORT1_SDI" },
{ "PORT1_3_RX", "Port1 Playback Switch", "PORT1_SDI" },
{ "PORT1_4_RX", "Port1 Playback Switch", "PORT1_SDI" },
{ "PORT1_5_RX", "Port1 Playback Switch", "PORT1_SDI" },
{ "PORT1_6_RX", "Port1 Playback Switch", "PORT1_SDI" },
{ "PORT1_7_RX", "Port1 Playback Switch", "PORT1_SDI" },
{ "PORT1_8_RX", "Port1 Playback Switch", "PORT1_SDI" },
{ "PORT2_1_RX", "Port2 Playback Switch", "PORT2_SDI" },
{ "PORT2_2_RX", "Port2 Playback Switch", "PORT2_SDI" },
/* HP mapping */
{ "HPL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
{ "HPL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
{ "HPL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
{ "HPL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
{ "HPL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
{ "HPL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
{ "HPL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
{ "HPL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
{ "HPL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
{ "HPL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
{ "HPL Mixer", "ADCL Switch", "ADC Left" },
{ "HPL Mixer", "ADCR Switch", "ADC Right" },
{ "HPL Mixer", "DMIC1L Switch", "DMIC1 Left" },
{ "HPL Mixer", "DMIC1R Switch", "DMIC1 Right" },
{ "HPL Mixer", "DMIC2L Switch", "DMIC2 Left" },
{ "HPL Mixer", "DMIC2R Switch", "DMIC2 Right" },
{ "HPL Mixer", "Sidetone Switch", "Sidetone" },
{ "HPL DAC", NULL, "HPL Mixer" },
{ "HPR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
{ "HPR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
{ "HPR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
{ "HPR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
{ "HPR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
{ "HPR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
{ "HPR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
{ "HPR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
/* Port 2 */
{ "HPR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
{ "HPR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
{ "HPR Mixer", "ADCL Switch", "ADC Left" },
{ "HPR Mixer", "ADCR Switch", "ADC Right" },
{ "HPR Mixer", "DMIC1L Switch", "DMIC1 Left" },
{ "HPR Mixer", "DMIC1R Switch", "DMIC1 Right" },
{ "HPR Mixer", "DMIC2L Switch", "DMIC2 Left" },
{ "HPR Mixer", "DMIC2L Switch", "DMIC2 Right" },
{ "HPR Mixer", "Sidetone Switch", "Sidetone" },
{ "HPR DAC", NULL, "HPR Mixer" },
{ "HPOUTL", "Headset Switch", "HPL DAC"},
{ "HPOUTR", "Headset Switch", "HPR DAC"},
/* EP map */
{ "EPOUT", "Earpiece Switch", "HPL DAC" },
/* Speaker map */
{ "LSL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
{ "LSL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
{ "LSL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
{ "LSL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
{ "LSL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
{ "LSL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
{ "LSL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
{ "LSL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
/* Port 2 */
{ "LSL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
{ "LSL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
{ "LSL Mixer", "ADCL Switch", "ADC Left" },
{ "LSL Mixer", "ADCR Switch", "ADC Right" },
{ "LSL Mixer", "DMIC1L Switch", "DMIC1 Left" },
{ "LSL Mixer", "DMIC1R Switch", "DMIC1 Right" },
{ "LSL Mixer", "DMIC2L Switch", "DMIC2 Left" },
{ "LSL Mixer", "DMIC2R Switch", "DMIC2 Right" },
{ "LSL Mixer", "Sidetone Switch", "Sidetone" },
{ "LSL DAC", NULL, "LSL Mixer" },
{ "LSR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
{ "LSR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
{ "LSR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
{ "LSR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
{ "LSR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
{ "LSR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
{ "LSR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
{ "LSR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
/* Port 2 */
{ "LSR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
{ "LSR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
{ "LSR Mixer", "ADCL Switch", "ADC Left" },
{ "LSR Mixer", "ADCR Switch", "ADC Right" },
{ "LSR Mixer", "DMIC1L Switch", "DMIC1 Left" },
{ "LSR Mixer", "DMIC1R Switch", "DMIC1 Right" },
{ "LSR Mixer", "DMIC2L Switch", "DMIC2 Left" },
{ "LSR Mixer", "DMIC2R Switch", "DMIC2 Right" },
{ "LSR Mixer", "Sidetone Switch", "Sidetone" },
{ "LSR DAC", NULL, "LSR Mixer" },
{ "LSOUTL", "Speaker Left Switch", "LSL DAC"},
{ "LSOUTR", "Speaker Left Switch", "LSR DAC"},
/* Haptic map */
{ "HAL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
{ "HAL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
{ "HAL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
{ "HAL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
{ "HAL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
{ "HAL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
{ "HAL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
{ "HAL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
/* Port 2 */
{ "HAL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
{ "HAL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
{ "HAL Mixer", "ADCL Switch", "ADC Left" },
{ "HAL Mixer", "ADCR Switch", "ADC Right" },
{ "HAL Mixer", "DMIC1L Switch", "DMIC1 Left" },
{ "HAL Mixer", "DMIC1R Switch", "DMIC1 Right" },
{ "HAL Mixer", "DMIC2L Switch", "DMIC2 Left" },
{ "HAL Mixer", "DMIC2R Switch", "DMIC2 Right" },
{ "HAL Mixer", "Sidetone Switch", "Sidetone" },
{ "HAL DAC", NULL, "HAL Mixer" },
{ "HAR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
{ "HAR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
{ "HAR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
{ "HAR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
{ "HAR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
{ "HAR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
{ "HAR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
{ "HAR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
/* Port 2 */
{ "HAR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
{ "HAR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
{ "HAR Mixer", "ADCL Switch", "ADC Left" },
{ "HAR Mixer", "ADCR Switch", "ADC Right" },
{ "HAR Mixer", "DMIC1L Switch", "DMIC1 Left" },
{ "HAR Mixer", "DMIC1R Switch", "DMIC1 Right" },
{ "HAR Mixer", "DMIC2L Switch", "DMIC2 Left" },
{ "HAR Mixer", "DMIC2R Switch", "DMIC2 Right" },
{ "HAR Mixer", "Sideton Switch", "Sidetone" },
{ "HAR DAC", NULL, "HAR Mixer" },
{ "HAOUTL", "Haptic Left Switch", "HAL DAC" },
{ "HAOUTR", "Haptic Right Switch", "HAR DAC" },
/* Lineout map */
{ "LOL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
{ "LOL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
{ "LOL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
{ "LOL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
{ "LOL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
{ "LOL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
{ "LOL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
{ "LOL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
/* Port 2 */
{ "LOL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
{ "LOL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
{ "LOL Mixer", "ADCL Switch", "ADC Left" },
{ "LOL Mixer", "ADCR Switch", "ADC Right" },
{ "LOL Mixer", "DMIC1L Switch", "DMIC1 Left" },
{ "LOL Mixer", "DMIC1R Switch", "DMIC1 Right" },
{ "LOL Mixer", "DMIC2L Switch", "DMIC2 Left" },
{ "LOL Mixer", "DMIC2R Switch", "DMIC2 Right" },
{ "LOL Mixer", "Sidetone Switch", "Sidetone" },
{ "LOL DAC", NULL, "LOL Mixer" },
{ "LOR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
{ "LOR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
{ "LOR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
{ "LOR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
{ "LOR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
{ "LOR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
{ "LOR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
{ "LOR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
/* Port 2 */
{ "LOR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
{ "LOR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
{ "LOR Mixer", "ADCL Switch", "ADC Left" },
{ "LOR Mixer", "ADCR Switch", "ADC Right" },
{ "LOR Mixer", "DMIC1L Switch", "DMIC1 Left" },
{ "LOR Mixer", "DMIC1R Switch", "DMIC1 Right" },
{ "LOR Mixer", "DMIC2L Switch", "DMIC2 Left" },
{ "LOR Mixer", "DMIC2R Switch", "DMIC2 Right" },
{ "LOR Mixer", "Sidetone Switch", "Sidetone" },
{ "LOR DAC", NULL, "LOR Mixer" },
{ "LOOUTL", NULL, "LOL DAC" },
{ "LOOUTR", NULL, "LOR DAC" },
/* TX map */
/* Port1 mappings */
{ "Port1_1 Mixer", "ADCL Switch", "ADC Left" },
{ "Port1_1 Mixer", "ADCR Switch", "ADC Right" },
{ "Port1_1 Mixer", "DMIC1L Switch", "DMIC1 Left" },
{ "Port1_1 Mixer", "DMIC1R Switch", "DMIC1 Right" },
{ "Port1_1 Mixer", "DMIC2L Switch", "DMIC2 Left" },
{ "Port1_1 Mixer", "DMIC2R Switch", "DMIC2 Right" },
{ "Port1_2 Mixer", "ADCL Switch", "ADC Left" },
{ "Port1_2 Mixer", "ADCR Switch", "ADC Right" },
{ "Port1_2 Mixer", "DMIC1L Switch", "DMIC1 Left" },
{ "Port1_2 Mixer", "DMIC1R Switch", "DMIC1 Right" },
{ "Port1_2 Mixer", "DMIC2L Switch", "DMIC2 Left" },
{ "Port1_2 Mixer", "DMIC2R Switch", "DMIC2 Right" },
{ "Port1_3 Mixer", "ADCL Switch", "ADC Left" },
{ "Port1_3 Mixer", "ADCR Switch", "ADC Right" },
{ "Port1_3 Mixer", "DMIC1L Switch", "DMIC1 Left" },
{ "Port1_3 Mixer", "DMIC1R Switch", "DMIC1 Right" },
{ "Port1_3 Mixer", "DMIC2L Switch", "DMIC2 Left" },
{ "Port1_3 Mixer", "DMIC2R Switch", "DMIC2 Right" },
{ "Port1_4 Mixer", "ADCL Switch", "ADC Left" },
{ "Port1_4 Mixer", "ADCR Switch", "ADC Right" },
{ "Port1_4 Mixer", "DMIC1L Switch", "DMIC1 Left" },
{ "Port1_4 Mixer", "DMIC1R Switch", "DMIC1 Right" },
{ "Port1_4 Mixer", "DMIC2L Switch", "DMIC2 Left" },
{ "Port1_4 Mixer", "DMIC2R Switch", "DMIC2 Right" },
{ "Port1_5 Mixer", "ADCL Switch", "ADC Left" },
{ "Port1_5 Mixer", "ADCR Switch", "ADC Right" },
{ "Port1_5 Mixer", "DMIC1L Switch", "DMIC1 Left" },
{ "Port1_5 Mixer", "DMIC1R Switch", "DMIC1 Right" },
{ "Port1_5 Mixer", "DMIC2L Switch", "DMIC2 Left" },
{ "Port1_5 Mixer", "DMIC2R Switch", "DMIC2 Right" },
{ "Port1_6 Mixer", "ADCL Switch", "ADC Left" },
{ "Port1_6 Mixer", "ADCR Switch", "ADC Right" },
{ "Port1_6 Mixer", "DMIC1L Switch", "DMIC1 Left" },
{ "Port1_6 Mixer", "DMIC1R Switch", "DMIC1 Right" },
{ "Port1_6 Mixer", "DMIC2L Switch", "DMIC2 Left" },
{ "Port1_6 Mixer", "DMIC2R Switch", "DMIC2 Right" },
{ "Port1_7 Mixer", "ADCL Switch", "ADC Left" },
{ "Port1_7 Mixer", "ADCR Switch", "ADC Right" },
{ "Port1_7 Mixer", "DMIC1L Switch", "DMIC1 Left" },
{ "Port1_7 Mixer", "DMIC1R Switch", "DMIC1 Right" },
{ "Port1_7 Mixer", "DMIC2L Switch", "DMIC2 Left" },
{ "Port1_7 Mixer", "DMIC2R Switch", "DMIC2 Right" },
{ "Port1_8 Mixer", "ADCL Switch", "ADC Left" },
{ "Port1_8 Mixer", "ADCR Switch", "ADC Right" },
{ "Port1_8 Mixer", "DMIC1L Switch", "DMIC1 Left" },
{ "Port1_8 Mixer", "DMIC1R Switch", "DMIC1 Right" },
{ "Port1_8 Mixer", "DMIC2L Switch", "DMIC2 Left" },
{ "Port1_8 Mixer", "DMIC2R Switch", "DMIC2 Right" },
{ "Port2_1 Mixer", "ADCL Switch", "ADC Left" },
{ "Port2_1 Mixer", "ADCR Switch", "ADC Right" },
{ "Port2_1 Mixer", "DMIC1L Switch", "DMIC1 Left" },
{ "Port2_1 Mixer", "DMIC1R Switch", "DMIC1 Right" },
{ "Port2_1 Mixer", "DMIC2L Switch", "DMIC2 Left" },
{ "Port2_1 Mixer", "DMIC2R Switch", "DMIC2 Right" },
{ "Port2_2 Mixer", "ADCL Switch", "ADC Left" },
{ "Port2_2 Mixer", "ADCR Switch", "ADC Right" },
{ "Port2_2 Mixer", "DMIC1L Switch", "DMIC1 Left" },
{ "Port2_2 Mixer", "DMIC1R Switch", "DMIC1 Right" },
{ "Port2_2 Mixer", "DMIC2L Switch", "DMIC2 Left" },
{ "Port2_2 Mixer", "DMIC2R Switch", "DMIC2 Right" },
{ "P1_1_TX", NULL, "Port1_1 Mixer" },
{ "P1_2_TX", NULL, "Port1_2 Mixer" },
{ "P1_3_TX", NULL, "Port1_3 Mixer" },
{ "P1_4_TX", NULL, "Port1_4 Mixer" },
{ "P1_5_TX", NULL, "Port1_5 Mixer" },
{ "P1_6_TX", NULL, "Port1_6 Mixer" },
{ "P1_7_TX", NULL, "Port1_7 Mixer" },
{ "P1_8_TX", NULL, "Port1_8 Mixer" },
{ "P2_1_TX", NULL, "Port2_1 Mixer" },
{ "P2_2_TX", NULL, "Port2_2 Mixer" },
{ "PORT1_SDO", "Port1 Capture Switch", "P1_1_TX"},
{ "PORT1_SDO", "Port1 Capture Switch", "P1_2_TX"},
{ "PORT1_SDO", "Port1 Capture Switch", "P1_3_TX"},
{ "PORT1_SDO", "Port1 Capture Switch", "P1_4_TX"},
{ "PORT1_SDO", "Port1 Capture Switch", "P1_5_TX"},
{ "PORT1_SDO", "Port1 Capture Switch", "P1_6_TX"},
{ "PORT1_SDO", "Port1 Capture Switch", "P1_7_TX"},
{ "PORT1_SDO", "Port1 Capture Switch", "P1_8_TX"},
{ "PORT2_SDO", "Port2 Capture Switch", "P2_1_TX"},
{ "PORT2_SDO", "Port2 Capture Switch", "P2_2_TX"},
{ "Mic1 Input", NULL, "AMIC1" },
{ "Mic2 Input", NULL, "AMIC2" },
{ "AUXL Input", NULL, "AUXL" },
{ "AUXR Input", NULL, "AUXR" },
/* AUX connections */
{ "ADCL Mux", "Aux_L", "AUXL Input" },
{ "ADCL Mux", "MIC1", "Mic1 Input" },
{ "ADCR Mux", "Aux_R", "AUXR Input" },
{ "ADCR Mux", "MIC2", "Mic2 Input" },
/* ADC connection */
{ "ADC Left", NULL, "ADCL Mux"},
{ "ADC Right", NULL, "ADCR Mux"},
{ "DMIC1 Left", NULL, "DMIC1DAT"},
{ "DMIC1 Right", NULL, "DMIC1DAT"},
{ "DMIC2 Left", NULL, "DMIC2DAT"},
{ "DMIC2 Right", NULL, "DMIC2DAT"},
/* Sidetone map */
{ "Sidetone Mixer", NULL, "ADC Left" },
{ "Sidetone Mixer", NULL, "ADC Right" },
{ "Sidetone Mixer", NULL, "DMIC1 Left" },
{ "Sidetone Mixer", NULL, "DMIC1 Right" },
{ "Sidetone Mixer", NULL, "DMIC2 Left" },
{ "Sidetone Mixer", NULL, "DMIC2 Right" },
{ "Sidetone", "Sidetone Switch", "Sidetone Mixer" },
};
static int lm49453_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
u16 clk_div = 0;
/* Setting DAC clock dividers based on substream sample rate. */
switch (params_rate(params)) {
case 8000:
case 16000:
case 32000:
case 24000:
case 48000:
clk_div = 256;
break;
case 11025:
case 22050:
case 44100:
clk_div = 216;
break;
case 96000:
clk_div = 127;
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, LM49453_P0_ADC_CLK_DIV_REG, clk_div);
snd_soc_component_write(component, LM49453_P0_DAC_HP_CLK_DIV_REG, clk_div);
return 0;
}
static int lm49453_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
u16 aif_val;
int mode = 0;
int clk_phase = 0;
int clk_shift = 0;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC:
aif_val = 0;
break;
case SND_SOC_DAIFMT_CBC_CFP:
aif_val = LM49453_AUDIO_PORT1_BASIC_SYNC_MS;
break;
case SND_SOC_DAIFMT_CBP_CFC:
aif_val = LM49453_AUDIO_PORT1_BASIC_CLK_MS;
break;
case SND_SOC_DAIFMT_CBP_CFP:
aif_val = LM49453_AUDIO_PORT1_BASIC_CLK_MS |
LM49453_AUDIO_PORT1_BASIC_SYNC_MS;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_DSP_A:
mode = 1;
clk_phase = (1 << 5);
clk_shift = 1;
break;
case SND_SOC_DAIFMT_DSP_B:
mode = 1;
clk_phase = (1 << 5);
clk_shift = 0;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, LM49453_P0_AUDIO_PORT1_BASIC_REG,
LM49453_AUDIO_PORT1_BASIC_FMT_MASK|BIT(0)|BIT(5),
(aif_val | mode | clk_phase));
snd_soc_component_write(component, LM49453_P0_AUDIO_PORT1_RX_MSB_REG, clk_shift);
return 0;
}
static int lm49453_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
u16 pll_clk = 0;
switch (freq) {
case 12288000:
case 26000000:
case 19200000:
/* pll clk slection */
pll_clk = 0;
break;
case 48000:
case 32576:
return 0;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, LM49453_P0_PMC_SETUP_REG, BIT(4), pll_clk);
return 0;
}
static int lm49453_hp_mute(struct snd_soc_dai *dai, int mute, int direction)
{
snd_soc_component_update_bits(dai->component, LM49453_P0_DAC_DSP_REG, BIT(1)|BIT(0),
(mute ? (BIT(1)|BIT(0)) : 0));
return 0;
}
static int lm49453_lo_mute(struct snd_soc_dai *dai, int mute, int direction)
{
snd_soc_component_update_bits(dai->component, LM49453_P0_DAC_DSP_REG, BIT(3)|BIT(2),
(mute ? (BIT(3)|BIT(2)) : 0));
return 0;
}
static int lm49453_ls_mute(struct snd_soc_dai *dai, int mute, int direction)
{
snd_soc_component_update_bits(dai->component, LM49453_P0_DAC_DSP_REG, BIT(5)|BIT(4),
(mute ? (BIT(5)|BIT(4)) : 0));
return 0;
}
static int lm49453_ep_mute(struct snd_soc_dai *dai, int mute, int direction)
{
snd_soc_component_update_bits(dai->component, LM49453_P0_DAC_DSP_REG, BIT(4),
(mute ? BIT(4) : 0));
return 0;
}
static int lm49453_ha_mute(struct snd_soc_dai *dai, int mute, int direction)
{
snd_soc_component_update_bits(dai->component, LM49453_P0_DAC_DSP_REG, BIT(7)|BIT(6),
(mute ? (BIT(7)|BIT(6)) : 0));
return 0;
}
static int lm49453_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct lm49453_priv *lm49453 = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_ON:
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
regcache_sync(lm49453->regmap);
snd_soc_component_update_bits(component, LM49453_P0_PMC_SETUP_REG,
LM49453_PMC_SETUP_CHIP_EN, LM49453_CHIP_EN);
break;
case SND_SOC_BIAS_OFF:
snd_soc_component_update_bits(component, LM49453_P0_PMC_SETUP_REG,
LM49453_PMC_SETUP_CHIP_EN, 0);
break;
}
return 0;
}
/* Formates supported by LM49453 driver. */
#define LM49453_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops lm49453_headset_dai_ops = {
.hw_params = lm49453_hw_params,
.set_sysclk = lm49453_set_dai_sysclk,
.set_fmt = lm49453_set_dai_fmt,
.mute_stream = lm49453_hp_mute,
.no_capture_mute = 1,
};
static const struct snd_soc_dai_ops lm49453_speaker_dai_ops = {
.hw_params = lm49453_hw_params,
.set_sysclk = lm49453_set_dai_sysclk,
.set_fmt = lm49453_set_dai_fmt,
.mute_stream = lm49453_ls_mute,
.no_capture_mute = 1,
};
static const struct snd_soc_dai_ops lm49453_haptic_dai_ops = {
.hw_params = lm49453_hw_params,
.set_sysclk = lm49453_set_dai_sysclk,
.set_fmt = lm49453_set_dai_fmt,
.mute_stream = lm49453_ha_mute,
.no_capture_mute = 1,
};
static const struct snd_soc_dai_ops lm49453_ep_dai_ops = {
.hw_params = lm49453_hw_params,
.set_sysclk = lm49453_set_dai_sysclk,
.set_fmt = lm49453_set_dai_fmt,
.mute_stream = lm49453_ep_mute,
.no_capture_mute = 1,
};
static const struct snd_soc_dai_ops lm49453_lineout_dai_ops = {
.hw_params = lm49453_hw_params,
.set_sysclk = lm49453_set_dai_sysclk,
.set_fmt = lm49453_set_dai_fmt,
.mute_stream = lm49453_lo_mute,
.no_capture_mute = 1,
};
/* LM49453 dai structure. */
static struct snd_soc_dai_driver lm49453_dai[] = {
{
.name = "LM49453 Headset",
.playback = {
.stream_name = "Headset",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = LM49453_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 5,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = LM49453_FORMATS,
},
.ops = &lm49453_headset_dai_ops,
.symmetric_rate = 1,
},
{
.name = "LM49453 Speaker",
.playback = {
.stream_name = "Speaker",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = LM49453_FORMATS,
},
.ops = &lm49453_speaker_dai_ops,
},
{
.name = "LM49453 Haptic",
.playback = {
.stream_name = "Haptic",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = LM49453_FORMATS,
},
.ops = &lm49453_haptic_dai_ops,
},
{
.name = "LM49453 Earpiece",
.playback = {
.stream_name = "Earpiece",
.channels_min = 1,
.channels_max = 1,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = LM49453_FORMATS,
},
.ops = &lm49453_ep_dai_ops,
},
{
.name = "LM49453 line out",
.playback = {
.stream_name = "Lineout",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = LM49453_FORMATS,
},
.ops = &lm49453_lineout_dai_ops,
},
};
static const struct snd_soc_component_driver soc_component_dev_lm49453 = {
.set_bias_level = lm49453_set_bias_level,
.controls = lm49453_snd_controls,
.num_controls = ARRAY_SIZE(lm49453_snd_controls),
.dapm_widgets = lm49453_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(lm49453_dapm_widgets),
.dapm_routes = lm49453_audio_map,
.num_dapm_routes = ARRAY_SIZE(lm49453_audio_map),
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config lm49453_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = LM49453_MAX_REGISTER,
.reg_defaults = lm49453_reg_defs,
.num_reg_defaults = ARRAY_SIZE(lm49453_reg_defs),
.cache_type = REGCACHE_RBTREE,
};
static int lm49453_i2c_probe(struct i2c_client *i2c)
{
struct lm49453_priv *lm49453;
int ret = 0;
lm49453 = devm_kzalloc(&i2c->dev, sizeof(struct lm49453_priv),
GFP_KERNEL);
if (lm49453 == NULL)
return -ENOMEM;
i2c_set_clientdata(i2c, lm49453);
lm49453->regmap = devm_regmap_init_i2c(i2c, &lm49453_regmap_config);
if (IS_ERR(lm49453->regmap)) {
ret = PTR_ERR(lm49453->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_lm49453,
lm49453_dai, ARRAY_SIZE(lm49453_dai));
if (ret < 0)
dev_err(&i2c->dev, "Failed to register component: %d\n", ret);
return ret;
}
static const struct i2c_device_id lm49453_i2c_id[] = {
{ "lm49453", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, lm49453_i2c_id);
static struct i2c_driver lm49453_i2c_driver = {
.driver = {
.name = "lm49453",
},
.probe = lm49453_i2c_probe,
.id_table = lm49453_i2c_id,
};
module_i2c_driver(lm49453_i2c_driver);
MODULE_DESCRIPTION("ASoC LM49453 driver");
MODULE_AUTHOR("M R Swami Reddy <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/lm49453.c |
// SPDX-License-Identifier: GPL-2.0
//
// ALSA SoC CX20721/CX20723 codec driver
//
// Copyright: (C) 2017 Conexant Systems, Inc.
// Author: Simon Ho, <[email protected]>
//
// TODO: add support for TDM mode.
//
#include <linux/acpi.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/initval.h>
#include <sound/jack.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/tlv.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include "cx2072x.h"
#define PLL_OUT_HZ_48 (1024 * 3 * 48000)
#define BITS_PER_SLOT 8
/* codec private data */
struct cx2072x_priv {
struct regmap *regmap;
struct clk *mclk;
unsigned int mclk_rate;
struct device *dev;
struct snd_soc_component *codec;
struct snd_soc_jack_gpio jack_gpio;
struct mutex lock;
unsigned int bclk_ratio;
bool pll_changed;
bool i2spcm_changed;
int sample_size;
int frame_size;
int sample_rate;
unsigned int dai_fmt;
bool en_aec_ref;
};
/*
* DAC/ADC Volume
*
* max : 74 : 0 dB
* ( in 1 dB step )
* min : 0 : -74 dB
*/
static const DECLARE_TLV_DB_SCALE(adc_tlv, -7400, 100, 0);
static const DECLARE_TLV_DB_SCALE(dac_tlv, -7400, 100, 0);
static const DECLARE_TLV_DB_SCALE(boost_tlv, 0, 1200, 0);
struct cx2072x_eq_ctrl {
u8 ch;
u8 band;
};
static const DECLARE_TLV_DB_RANGE(hpf_tlv,
0, 0, TLV_DB_SCALE_ITEM(120, 0, 0),
1, 63, TLV_DB_SCALE_ITEM(30, 30, 0)
);
/* Lookup table for PRE_DIV */
static const struct {
unsigned int mclk;
unsigned int div;
} mclk_pre_div[] = {
{ 6144000, 1 },
{ 12288000, 2 },
{ 19200000, 3 },
{ 26000000, 4 },
{ 28224000, 5 },
{ 36864000, 6 },
{ 36864000, 7 },
{ 48000000, 8 },
{ 49152000, 8 },
};
/*
* cx2072x register cache.
*/
static const struct reg_default cx2072x_reg_defaults[] = {
{ CX2072X_AFG_POWER_STATE, 0x00000003 },
{ CX2072X_UM_RESPONSE, 0x00000000 },
{ CX2072X_GPIO_DATA, 0x00000000 },
{ CX2072X_GPIO_ENABLE, 0x00000000 },
{ CX2072X_GPIO_DIRECTION, 0x00000000 },
{ CX2072X_GPIO_WAKE, 0x00000000 },
{ CX2072X_GPIO_UM_ENABLE, 0x00000000 },
{ CX2072X_GPIO_STICKY_MASK, 0x00000000 },
{ CX2072X_DAC1_CONVERTER_FORMAT, 0x00000031 },
{ CX2072X_DAC1_AMP_GAIN_RIGHT, 0x0000004a },
{ CX2072X_DAC1_AMP_GAIN_LEFT, 0x0000004a },
{ CX2072X_DAC1_POWER_STATE, 0x00000433 },
{ CX2072X_DAC1_CONVERTER_STREAM_CHANNEL, 0x00000000 },
{ CX2072X_DAC1_EAPD_ENABLE, 0x00000000 },
{ CX2072X_DAC2_CONVERTER_FORMAT, 0x00000031 },
{ CX2072X_DAC2_AMP_GAIN_RIGHT, 0x0000004a },
{ CX2072X_DAC2_AMP_GAIN_LEFT, 0x0000004a },
{ CX2072X_DAC2_POWER_STATE, 0x00000433 },
{ CX2072X_DAC2_CONVERTER_STREAM_CHANNEL, 0x00000000 },
{ CX2072X_ADC1_CONVERTER_FORMAT, 0x00000031 },
{ CX2072X_ADC1_AMP_GAIN_RIGHT_0, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_LEFT_0, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_RIGHT_1, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_LEFT_1, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_RIGHT_2, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_LEFT_2, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_RIGHT_3, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_LEFT_3, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_RIGHT_4, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_LEFT_4, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_RIGHT_5, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_LEFT_5, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_RIGHT_6, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_LEFT_6, 0x0000004a },
{ CX2072X_ADC1_CONNECTION_SELECT_CONTROL, 0x00000000 },
{ CX2072X_ADC1_POWER_STATE, 0x00000433 },
{ CX2072X_ADC1_CONVERTER_STREAM_CHANNEL, 0x00000000 },
{ CX2072X_ADC2_CONVERTER_FORMAT, 0x00000031 },
{ CX2072X_ADC2_AMP_GAIN_RIGHT_0, 0x0000004a },
{ CX2072X_ADC2_AMP_GAIN_LEFT_0, 0x0000004a },
{ CX2072X_ADC2_AMP_GAIN_RIGHT_1, 0x0000004a },
{ CX2072X_ADC2_AMP_GAIN_LEFT_1, 0x0000004a },
{ CX2072X_ADC2_AMP_GAIN_RIGHT_2, 0x0000004a },
{ CX2072X_ADC2_AMP_GAIN_LEFT_2, 0x0000004a },
{ CX2072X_ADC2_CONNECTION_SELECT_CONTROL, 0x00000000 },
{ CX2072X_ADC2_POWER_STATE, 0x00000433 },
{ CX2072X_ADC2_CONVERTER_STREAM_CHANNEL, 0x00000000 },
{ CX2072X_PORTA_CONNECTION_SELECT_CTRL, 0x00000000 },
{ CX2072X_PORTA_POWER_STATE, 0x00000433 },
{ CX2072X_PORTA_PIN_CTRL, 0x000000c0 },
{ CX2072X_PORTA_UNSOLICITED_RESPONSE, 0x00000000 },
{ CX2072X_PORTA_PIN_SENSE, 0x00000000 },
{ CX2072X_PORTA_EAPD_BTL, 0x00000002 },
{ CX2072X_PORTB_POWER_STATE, 0x00000433 },
{ CX2072X_PORTB_PIN_CTRL, 0x00000000 },
{ CX2072X_PORTB_UNSOLICITED_RESPONSE, 0x00000000 },
{ CX2072X_PORTB_PIN_SENSE, 0x00000000 },
{ CX2072X_PORTB_EAPD_BTL, 0x00000002 },
{ CX2072X_PORTB_GAIN_RIGHT, 0x00000000 },
{ CX2072X_PORTB_GAIN_LEFT, 0x00000000 },
{ CX2072X_PORTC_POWER_STATE, 0x00000433 },
{ CX2072X_PORTC_PIN_CTRL, 0x00000000 },
{ CX2072X_PORTC_GAIN_RIGHT, 0x00000000 },
{ CX2072X_PORTC_GAIN_LEFT, 0x00000000 },
{ CX2072X_PORTD_POWER_STATE, 0x00000433 },
{ CX2072X_PORTD_PIN_CTRL, 0x00000020 },
{ CX2072X_PORTD_UNSOLICITED_RESPONSE, 0x00000000 },
{ CX2072X_PORTD_PIN_SENSE, 0x00000000 },
{ CX2072X_PORTD_GAIN_RIGHT, 0x00000000 },
{ CX2072X_PORTD_GAIN_LEFT, 0x00000000 },
{ CX2072X_PORTE_CONNECTION_SELECT_CTRL, 0x00000000 },
{ CX2072X_PORTE_POWER_STATE, 0x00000433 },
{ CX2072X_PORTE_PIN_CTRL, 0x00000040 },
{ CX2072X_PORTE_UNSOLICITED_RESPONSE, 0x00000000 },
{ CX2072X_PORTE_PIN_SENSE, 0x00000000 },
{ CX2072X_PORTE_EAPD_BTL, 0x00000002 },
{ CX2072X_PORTE_GAIN_RIGHT, 0x00000000 },
{ CX2072X_PORTE_GAIN_LEFT, 0x00000000 },
{ CX2072X_PORTF_POWER_STATE, 0x00000433 },
{ CX2072X_PORTF_PIN_CTRL, 0x00000000 },
{ CX2072X_PORTF_UNSOLICITED_RESPONSE, 0x00000000 },
{ CX2072X_PORTF_PIN_SENSE, 0x00000000 },
{ CX2072X_PORTF_GAIN_RIGHT, 0x00000000 },
{ CX2072X_PORTF_GAIN_LEFT, 0x00000000 },
{ CX2072X_PORTG_POWER_STATE, 0x00000433 },
{ CX2072X_PORTG_PIN_CTRL, 0x00000040 },
{ CX2072X_PORTG_CONNECTION_SELECT_CTRL, 0x00000000 },
{ CX2072X_PORTG_EAPD_BTL, 0x00000002 },
{ CX2072X_PORTM_POWER_STATE, 0x00000433 },
{ CX2072X_PORTM_PIN_CTRL, 0x00000000 },
{ CX2072X_PORTM_CONNECTION_SELECT_CTRL, 0x00000000 },
{ CX2072X_PORTM_EAPD_BTL, 0x00000002 },
{ CX2072X_MIXER_POWER_STATE, 0x00000433 },
{ CX2072X_MIXER_GAIN_RIGHT_0, 0x0000004a },
{ CX2072X_MIXER_GAIN_LEFT_0, 0x0000004a },
{ CX2072X_MIXER_GAIN_RIGHT_1, 0x0000004a },
{ CX2072X_MIXER_GAIN_LEFT_1, 0x0000004a },
{ CX2072X_SPKR_DRC_ENABLE_STEP, 0x040065a4 },
{ CX2072X_SPKR_DRC_CONTROL, 0x007b0024 },
{ CX2072X_SPKR_DRC_TEST, 0x00000000 },
{ CX2072X_DIGITAL_BIOS_TEST0, 0x001f008a },
{ CX2072X_DIGITAL_BIOS_TEST2, 0x00990026 },
{ CX2072X_I2SPCM_CONTROL1, 0x00010001 },
{ CX2072X_I2SPCM_CONTROL2, 0x00000000 },
{ CX2072X_I2SPCM_CONTROL3, 0x00000000 },
{ CX2072X_I2SPCM_CONTROL4, 0x00000000 },
{ CX2072X_I2SPCM_CONTROL5, 0x00000000 },
{ CX2072X_I2SPCM_CONTROL6, 0x00000000 },
{ CX2072X_UM_INTERRUPT_CRTL_E, 0x00000000 },
{ CX2072X_CODEC_TEST2, 0x00000000 },
{ CX2072X_CODEC_TEST9, 0x00000004 },
{ CX2072X_CODEC_TEST20, 0x00000600 },
{ CX2072X_CODEC_TEST26, 0x00000208 },
{ CX2072X_ANALOG_TEST4, 0x00000000 },
{ CX2072X_ANALOG_TEST5, 0x00000000 },
{ CX2072X_ANALOG_TEST6, 0x0000059a },
{ CX2072X_ANALOG_TEST7, 0x000000a7 },
{ CX2072X_ANALOG_TEST8, 0x00000017 },
{ CX2072X_ANALOG_TEST9, 0x00000000 },
{ CX2072X_ANALOG_TEST10, 0x00000285 },
{ CX2072X_ANALOG_TEST11, 0x00000000 },
{ CX2072X_ANALOG_TEST12, 0x00000000 },
{ CX2072X_ANALOG_TEST13, 0x00000000 },
{ CX2072X_DIGITAL_TEST1, 0x00000242 },
{ CX2072X_DIGITAL_TEST11, 0x00000000 },
{ CX2072X_DIGITAL_TEST12, 0x00000084 },
{ CX2072X_DIGITAL_TEST15, 0x00000077 },
{ CX2072X_DIGITAL_TEST16, 0x00000021 },
{ CX2072X_DIGITAL_TEST17, 0x00000018 },
{ CX2072X_DIGITAL_TEST18, 0x00000024 },
{ CX2072X_DIGITAL_TEST19, 0x00000001 },
{ CX2072X_DIGITAL_TEST20, 0x00000002 },
};
/*
* register initialization
*/
static const struct reg_sequence cx2072x_reg_init[] = {
{ CX2072X_ANALOG_TEST9, 0x080 }, /* DC offset Calibration */
{ CX2072X_CODEC_TEST26, 0x65f }, /* Disable the PA */
{ CX2072X_ANALOG_TEST10, 0x289 }, /* Set the speaker output gain */
{ CX2072X_CODEC_TEST20, 0xf05 },
{ CX2072X_CODEC_TESTXX, 0x380 },
{ CX2072X_CODEC_TEST26, 0xb90 },
{ CX2072X_CODEC_TEST9, 0x001 }, /* Enable 30 Hz High pass filter */
{ CX2072X_ANALOG_TEST3, 0x300 }, /* Disable PCBEEP pad */
{ CX2072X_CODEC_TEST24, 0x100 }, /* Disable SnM mode */
{ CX2072X_PORTD_PIN_CTRL, 0x020 }, /* Enable PortD input */
{ CX2072X_GPIO_ENABLE, 0x040 }, /* Enable GPIO7 pin for button */
{ CX2072X_GPIO_UM_ENABLE, 0x040 }, /* Enable UM for GPIO7 */
{ CX2072X_UM_RESPONSE, 0x080 }, /* Enable button response */
{ CX2072X_DIGITAL_TEST12, 0x0c4 }, /* Enable headset button */
{ CX2072X_DIGITAL_TEST0, 0x415 }, /* Power down class-D during idle */
{ CX2072X_I2SPCM_CONTROL2, 0x00f }, /* Enable I2S TX */
{ CX2072X_I2SPCM_CONTROL3, 0x00f }, /* Enable I2S RX */
};
static unsigned int cx2072x_register_size(unsigned int reg)
{
switch (reg) {
case CX2072X_VENDOR_ID:
case CX2072X_REVISION_ID:
case CX2072X_PORTA_PIN_SENSE:
case CX2072X_PORTB_PIN_SENSE:
case CX2072X_PORTD_PIN_SENSE:
case CX2072X_PORTE_PIN_SENSE:
case CX2072X_PORTF_PIN_SENSE:
case CX2072X_I2SPCM_CONTROL1:
case CX2072X_I2SPCM_CONTROL2:
case CX2072X_I2SPCM_CONTROL3:
case CX2072X_I2SPCM_CONTROL4:
case CX2072X_I2SPCM_CONTROL5:
case CX2072X_I2SPCM_CONTROL6:
case CX2072X_UM_INTERRUPT_CRTL_E:
case CX2072X_EQ_G_COEFF:
case CX2072X_SPKR_DRC_CONTROL:
case CX2072X_SPKR_DRC_TEST:
case CX2072X_DIGITAL_BIOS_TEST0:
case CX2072X_DIGITAL_BIOS_TEST2:
return 4;
case CX2072X_EQ_ENABLE_BYPASS:
case CX2072X_EQ_B0_COEFF:
case CX2072X_EQ_B1_COEFF:
case CX2072X_EQ_B2_COEFF:
case CX2072X_EQ_A1_COEFF:
case CX2072X_EQ_A2_COEFF:
case CX2072X_DAC1_CONVERTER_FORMAT:
case CX2072X_DAC2_CONVERTER_FORMAT:
case CX2072X_ADC1_CONVERTER_FORMAT:
case CX2072X_ADC2_CONVERTER_FORMAT:
case CX2072X_CODEC_TEST2:
case CX2072X_CODEC_TEST9:
case CX2072X_CODEC_TEST20:
case CX2072X_CODEC_TEST26:
case CX2072X_ANALOG_TEST3:
case CX2072X_ANALOG_TEST4:
case CX2072X_ANALOG_TEST5:
case CX2072X_ANALOG_TEST6:
case CX2072X_ANALOG_TEST7:
case CX2072X_ANALOG_TEST8:
case CX2072X_ANALOG_TEST9:
case CX2072X_ANALOG_TEST10:
case CX2072X_ANALOG_TEST11:
case CX2072X_ANALOG_TEST12:
case CX2072X_ANALOG_TEST13:
case CX2072X_DIGITAL_TEST0:
case CX2072X_DIGITAL_TEST1:
case CX2072X_DIGITAL_TEST11:
case CX2072X_DIGITAL_TEST12:
case CX2072X_DIGITAL_TEST15:
case CX2072X_DIGITAL_TEST16:
case CX2072X_DIGITAL_TEST17:
case CX2072X_DIGITAL_TEST18:
case CX2072X_DIGITAL_TEST19:
case CX2072X_DIGITAL_TEST20:
return 2;
default:
return 1;
}
}
static bool cx2072x_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CX2072X_VENDOR_ID:
case CX2072X_REVISION_ID:
case CX2072X_CURRENT_BCLK_FREQUENCY:
case CX2072X_AFG_POWER_STATE:
case CX2072X_UM_RESPONSE:
case CX2072X_GPIO_DATA:
case CX2072X_GPIO_ENABLE:
case CX2072X_GPIO_DIRECTION:
case CX2072X_GPIO_WAKE:
case CX2072X_GPIO_UM_ENABLE:
case CX2072X_GPIO_STICKY_MASK:
case CX2072X_DAC1_CONVERTER_FORMAT:
case CX2072X_DAC1_AMP_GAIN_RIGHT:
case CX2072X_DAC1_AMP_GAIN_LEFT:
case CX2072X_DAC1_POWER_STATE:
case CX2072X_DAC1_CONVERTER_STREAM_CHANNEL:
case CX2072X_DAC1_EAPD_ENABLE:
case CX2072X_DAC2_CONVERTER_FORMAT:
case CX2072X_DAC2_AMP_GAIN_RIGHT:
case CX2072X_DAC2_AMP_GAIN_LEFT:
case CX2072X_DAC2_POWER_STATE:
case CX2072X_DAC2_CONVERTER_STREAM_CHANNEL:
case CX2072X_ADC1_CONVERTER_FORMAT:
case CX2072X_ADC1_AMP_GAIN_RIGHT_0:
case CX2072X_ADC1_AMP_GAIN_LEFT_0:
case CX2072X_ADC1_AMP_GAIN_RIGHT_1:
case CX2072X_ADC1_AMP_GAIN_LEFT_1:
case CX2072X_ADC1_AMP_GAIN_RIGHT_2:
case CX2072X_ADC1_AMP_GAIN_LEFT_2:
case CX2072X_ADC1_AMP_GAIN_RIGHT_3:
case CX2072X_ADC1_AMP_GAIN_LEFT_3:
case CX2072X_ADC1_AMP_GAIN_RIGHT_4:
case CX2072X_ADC1_AMP_GAIN_LEFT_4:
case CX2072X_ADC1_AMP_GAIN_RIGHT_5:
case CX2072X_ADC1_AMP_GAIN_LEFT_5:
case CX2072X_ADC1_AMP_GAIN_RIGHT_6:
case CX2072X_ADC1_AMP_GAIN_LEFT_6:
case CX2072X_ADC1_CONNECTION_SELECT_CONTROL:
case CX2072X_ADC1_POWER_STATE:
case CX2072X_ADC1_CONVERTER_STREAM_CHANNEL:
case CX2072X_ADC2_CONVERTER_FORMAT:
case CX2072X_ADC2_AMP_GAIN_RIGHT_0:
case CX2072X_ADC2_AMP_GAIN_LEFT_0:
case CX2072X_ADC2_AMP_GAIN_RIGHT_1:
case CX2072X_ADC2_AMP_GAIN_LEFT_1:
case CX2072X_ADC2_AMP_GAIN_RIGHT_2:
case CX2072X_ADC2_AMP_GAIN_LEFT_2:
case CX2072X_ADC2_CONNECTION_SELECT_CONTROL:
case CX2072X_ADC2_POWER_STATE:
case CX2072X_ADC2_CONVERTER_STREAM_CHANNEL:
case CX2072X_PORTA_CONNECTION_SELECT_CTRL:
case CX2072X_PORTA_POWER_STATE:
case CX2072X_PORTA_PIN_CTRL:
case CX2072X_PORTA_UNSOLICITED_RESPONSE:
case CX2072X_PORTA_PIN_SENSE:
case CX2072X_PORTA_EAPD_BTL:
case CX2072X_PORTB_POWER_STATE:
case CX2072X_PORTB_PIN_CTRL:
case CX2072X_PORTB_UNSOLICITED_RESPONSE:
case CX2072X_PORTB_PIN_SENSE:
case CX2072X_PORTB_EAPD_BTL:
case CX2072X_PORTB_GAIN_RIGHT:
case CX2072X_PORTB_GAIN_LEFT:
case CX2072X_PORTC_POWER_STATE:
case CX2072X_PORTC_PIN_CTRL:
case CX2072X_PORTC_GAIN_RIGHT:
case CX2072X_PORTC_GAIN_LEFT:
case CX2072X_PORTD_POWER_STATE:
case CX2072X_PORTD_PIN_CTRL:
case CX2072X_PORTD_UNSOLICITED_RESPONSE:
case CX2072X_PORTD_PIN_SENSE:
case CX2072X_PORTD_GAIN_RIGHT:
case CX2072X_PORTD_GAIN_LEFT:
case CX2072X_PORTE_CONNECTION_SELECT_CTRL:
case CX2072X_PORTE_POWER_STATE:
case CX2072X_PORTE_PIN_CTRL:
case CX2072X_PORTE_UNSOLICITED_RESPONSE:
case CX2072X_PORTE_PIN_SENSE:
case CX2072X_PORTE_EAPD_BTL:
case CX2072X_PORTE_GAIN_RIGHT:
case CX2072X_PORTE_GAIN_LEFT:
case CX2072X_PORTF_POWER_STATE:
case CX2072X_PORTF_PIN_CTRL:
case CX2072X_PORTF_UNSOLICITED_RESPONSE:
case CX2072X_PORTF_PIN_SENSE:
case CX2072X_PORTF_GAIN_RIGHT:
case CX2072X_PORTF_GAIN_LEFT:
case CX2072X_PORTG_POWER_STATE:
case CX2072X_PORTG_PIN_CTRL:
case CX2072X_PORTG_CONNECTION_SELECT_CTRL:
case CX2072X_PORTG_EAPD_BTL:
case CX2072X_PORTM_POWER_STATE:
case CX2072X_PORTM_PIN_CTRL:
case CX2072X_PORTM_CONNECTION_SELECT_CTRL:
case CX2072X_PORTM_EAPD_BTL:
case CX2072X_MIXER_POWER_STATE:
case CX2072X_MIXER_GAIN_RIGHT_0:
case CX2072X_MIXER_GAIN_LEFT_0:
case CX2072X_MIXER_GAIN_RIGHT_1:
case CX2072X_MIXER_GAIN_LEFT_1:
case CX2072X_EQ_ENABLE_BYPASS:
case CX2072X_EQ_B0_COEFF:
case CX2072X_EQ_B1_COEFF:
case CX2072X_EQ_B2_COEFF:
case CX2072X_EQ_A1_COEFF:
case CX2072X_EQ_A2_COEFF:
case CX2072X_EQ_G_COEFF:
case CX2072X_SPKR_DRC_ENABLE_STEP:
case CX2072X_SPKR_DRC_CONTROL:
case CX2072X_SPKR_DRC_TEST:
case CX2072X_DIGITAL_BIOS_TEST0:
case CX2072X_DIGITAL_BIOS_TEST2:
case CX2072X_I2SPCM_CONTROL1:
case CX2072X_I2SPCM_CONTROL2:
case CX2072X_I2SPCM_CONTROL3:
case CX2072X_I2SPCM_CONTROL4:
case CX2072X_I2SPCM_CONTROL5:
case CX2072X_I2SPCM_CONTROL6:
case CX2072X_UM_INTERRUPT_CRTL_E:
case CX2072X_CODEC_TEST2:
case CX2072X_CODEC_TEST9:
case CX2072X_CODEC_TEST20:
case CX2072X_CODEC_TEST26:
case CX2072X_ANALOG_TEST4:
case CX2072X_ANALOG_TEST5:
case CX2072X_ANALOG_TEST6:
case CX2072X_ANALOG_TEST7:
case CX2072X_ANALOG_TEST8:
case CX2072X_ANALOG_TEST9:
case CX2072X_ANALOG_TEST10:
case CX2072X_ANALOG_TEST11:
case CX2072X_ANALOG_TEST12:
case CX2072X_ANALOG_TEST13:
case CX2072X_DIGITAL_TEST0:
case CX2072X_DIGITAL_TEST1:
case CX2072X_DIGITAL_TEST11:
case CX2072X_DIGITAL_TEST12:
case CX2072X_DIGITAL_TEST15:
case CX2072X_DIGITAL_TEST16:
case CX2072X_DIGITAL_TEST17:
case CX2072X_DIGITAL_TEST18:
case CX2072X_DIGITAL_TEST19:
case CX2072X_DIGITAL_TEST20:
return true;
default:
return false;
}
}
static bool cx2072x_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CX2072X_VENDOR_ID:
case CX2072X_REVISION_ID:
case CX2072X_UM_INTERRUPT_CRTL_E:
case CX2072X_DIGITAL_TEST11:
case CX2072X_PORTA_PIN_SENSE:
case CX2072X_PORTB_PIN_SENSE:
case CX2072X_PORTD_PIN_SENSE:
case CX2072X_PORTE_PIN_SENSE:
case CX2072X_PORTF_PIN_SENSE:
case CX2072X_EQ_G_COEFF:
case CX2072X_EQ_BAND:
return true;
default:
return false;
}
}
static int cx2072x_reg_raw_write(struct i2c_client *client,
unsigned int reg,
const void *val, size_t val_count)
{
struct device *dev = &client->dev;
u8 buf[2 + CX2072X_MAX_EQ_COEFF];
int ret;
if (WARN_ON(val_count + 2 > sizeof(buf)))
return -EINVAL;
buf[0] = reg >> 8;
buf[1] = reg & 0xff;
memcpy(buf + 2, val, val_count);
ret = i2c_master_send(client, buf, val_count + 2);
if (ret != val_count + 2) {
dev_err(dev, "I2C write failed, ret = %d\n", ret);
return ret < 0 ? ret : -EIO;
}
return 0;
}
static int cx2072x_reg_write(void *context, unsigned int reg,
unsigned int value)
{
__le32 raw_value;
unsigned int size;
size = cx2072x_register_size(reg);
if (reg == CX2072X_UM_INTERRUPT_CRTL_E) {
/* Update the MSB byte only */
reg += 3;
size = 1;
value >>= 24;
}
raw_value = cpu_to_le32(value);
return cx2072x_reg_raw_write(context, reg, &raw_value, size);
}
static int cx2072x_reg_read(void *context, unsigned int reg,
unsigned int *value)
{
struct i2c_client *client = context;
struct device *dev = &client->dev;
__le32 recv_buf = 0;
struct i2c_msg msgs[2];
unsigned int size;
u8 send_buf[2];
int ret;
size = cx2072x_register_size(reg);
send_buf[0] = reg >> 8;
send_buf[1] = reg & 0xff;
msgs[0].addr = client->addr;
msgs[0].len = sizeof(send_buf);
msgs[0].buf = send_buf;
msgs[0].flags = 0;
msgs[1].addr = client->addr;
msgs[1].len = size;
msgs[1].buf = (u8 *)&recv_buf;
msgs[1].flags = I2C_M_RD;
ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
if (ret != ARRAY_SIZE(msgs)) {
dev_err(dev, "Failed to read register, ret = %d\n", ret);
return ret < 0 ? ret : -EIO;
}
*value = le32_to_cpu(recv_buf);
return 0;
}
/* get suggested pre_div valuce from mclk frequency */
static unsigned int get_div_from_mclk(unsigned int mclk)
{
unsigned int div = 8;
int i;
for (i = 0; i < ARRAY_SIZE(mclk_pre_div); i++) {
if (mclk <= mclk_pre_div[i].mclk) {
div = mclk_pre_div[i].div;
break;
}
}
return div;
}
static int cx2072x_config_pll(struct cx2072x_priv *cx2072x)
{
struct device *dev = cx2072x->dev;
unsigned int pre_div;
unsigned int pre_div_val;
unsigned int pll_input;
unsigned int pll_output;
unsigned int int_div;
unsigned int frac_div;
u64 frac_num;
unsigned int frac;
unsigned int sample_rate = cx2072x->sample_rate;
int pt_sample_per_sync = 2;
int pt_clock_per_sample = 96;
switch (sample_rate) {
case 48000:
case 32000:
case 24000:
case 16000:
break;
case 96000:
pt_sample_per_sync = 1;
pt_clock_per_sample = 48;
break;
case 192000:
pt_sample_per_sync = 0;
pt_clock_per_sample = 24;
break;
default:
dev_err(dev, "Unsupported sample rate %d\n", sample_rate);
return -EINVAL;
}
/* Configure PLL settings */
pre_div = get_div_from_mclk(cx2072x->mclk_rate);
pll_input = cx2072x->mclk_rate / pre_div;
pll_output = sample_rate * 3072;
int_div = pll_output / pll_input;
frac_div = pll_output - (int_div * pll_input);
if (frac_div) {
frac_div *= 1000;
frac_div /= pll_input;
frac_num = (u64)(4000 + frac_div) * ((1 << 20) - 4);
do_div(frac_num, 7);
frac = ((u32)frac_num + 499) / 1000;
}
pre_div_val = (pre_div - 1) * 2;
regmap_write(cx2072x->regmap, CX2072X_ANALOG_TEST4,
0x40 | (pre_div_val << 8));
if (frac_div == 0) {
/* Int mode */
regmap_write(cx2072x->regmap, CX2072X_ANALOG_TEST7, 0x100);
} else {
/* frac mode */
regmap_write(cx2072x->regmap, CX2072X_ANALOG_TEST6,
frac & 0xfff);
regmap_write(cx2072x->regmap, CX2072X_ANALOG_TEST7,
(u8)(frac >> 12));
}
int_div--;
regmap_write(cx2072x->regmap, CX2072X_ANALOG_TEST8, int_div);
/* configure PLL tracking */
if (frac_div == 0) {
/* disable PLL tracking */
regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST16, 0x00);
} else {
/* configure and enable PLL tracking */
regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST16,
(pt_sample_per_sync << 4) & 0xf0);
regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST17,
pt_clock_per_sample);
regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST18,
pt_clock_per_sample * 3 / 2);
regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST19, 0x01);
regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST20, 0x02);
regmap_update_bits(cx2072x->regmap, CX2072X_DIGITAL_TEST16,
0x01, 0x01);
}
return 0;
}
static int cx2072x_config_i2spcm(struct cx2072x_priv *cx2072x)
{
struct device *dev = cx2072x->dev;
unsigned int bclk_rate = 0;
int is_i2s = 0;
int has_one_bit_delay = 0;
int is_frame_inv = 0;
int is_bclk_inv = 0;
int pulse_len;
int frame_len = cx2072x->frame_size;
int sample_size = cx2072x->sample_size;
int i2s_right_slot;
int i2s_right_pause_interval = 0;
int i2s_right_pause_pos;
int is_big_endian = 1;
u64 div;
unsigned int mod;
union cx2072x_reg_i2spcm_ctrl_reg1 reg1;
union cx2072x_reg_i2spcm_ctrl_reg2 reg2;
union cx2072x_reg_i2spcm_ctrl_reg3 reg3;
union cx2072x_reg_i2spcm_ctrl_reg4 reg4;
union cx2072x_reg_i2spcm_ctrl_reg5 reg5;
union cx2072x_reg_i2spcm_ctrl_reg6 reg6;
union cx2072x_reg_digital_bios_test2 regdbt2;
const unsigned int fmt = cx2072x->dai_fmt;
if (frame_len <= 0) {
dev_err(dev, "Incorrect frame len %d\n", frame_len);
return -EINVAL;
}
if (sample_size <= 0) {
dev_err(dev, "Incorrect sample size %d\n", sample_size);
return -EINVAL;
}
dev_dbg(dev, "config_i2spcm set_dai_fmt- %08x\n", fmt);
regdbt2.ulval = 0xac;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
reg2.r.tx_master = 1;
reg3.r.rx_master = 1;
break;
case SND_SOC_DAIFMT_CBC_CFC:
reg2.r.tx_master = 0;
reg3.r.rx_master = 0;
break;
default:
dev_err(dev, "Unsupported DAI clocking mode\n");
return -EINVAL;
}
/* set format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
is_i2s = 1;
has_one_bit_delay = 1;
pulse_len = frame_len / 2;
break;
case SND_SOC_DAIFMT_RIGHT_J:
is_i2s = 1;
pulse_len = frame_len / 2;
break;
case SND_SOC_DAIFMT_LEFT_J:
is_i2s = 1;
pulse_len = frame_len / 2;
break;
default:
dev_err(dev, "Unsupported DAI format\n");
return -EINVAL;
}
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
is_frame_inv = is_i2s;
is_bclk_inv = is_i2s;
break;
case SND_SOC_DAIFMT_IB_IF:
is_frame_inv = !is_i2s;
is_bclk_inv = !is_i2s;
break;
case SND_SOC_DAIFMT_IB_NF:
is_frame_inv = is_i2s;
is_bclk_inv = !is_i2s;
break;
case SND_SOC_DAIFMT_NB_IF:
is_frame_inv = !is_i2s;
is_bclk_inv = is_i2s;
break;
default:
dev_err(dev, "Unsupported DAI clock inversion\n");
return -EINVAL;
}
reg1.r.rx_data_one_line = 1;
reg1.r.tx_data_one_line = 1;
if (is_i2s) {
i2s_right_slot = (frame_len / 2) / BITS_PER_SLOT;
i2s_right_pause_interval = (frame_len / 2) % BITS_PER_SLOT;
i2s_right_pause_pos = i2s_right_slot * BITS_PER_SLOT;
}
reg1.r.rx_ws_pol = is_frame_inv;
reg1.r.rx_ws_wid = pulse_len - 1;
reg1.r.rx_frm_len = frame_len / BITS_PER_SLOT - 1;
reg1.r.rx_sa_size = (sample_size / BITS_PER_SLOT) - 1;
reg1.r.tx_ws_pol = reg1.r.rx_ws_pol;
reg1.r.tx_ws_wid = pulse_len - 1;
reg1.r.tx_frm_len = reg1.r.rx_frm_len;
reg1.r.tx_sa_size = reg1.r.rx_sa_size;
reg2.r.tx_endian_sel = !is_big_endian;
reg2.r.tx_dstart_dly = has_one_bit_delay;
if (cx2072x->en_aec_ref)
reg2.r.tx_dstart_dly = 0;
reg3.r.rx_endian_sel = !is_big_endian;
reg3.r.rx_dstart_dly = has_one_bit_delay;
reg4.ulval = 0;
if (is_i2s) {
reg2.r.tx_slot_1 = 0;
reg2.r.tx_slot_2 = i2s_right_slot;
reg3.r.rx_slot_1 = 0;
if (cx2072x->en_aec_ref)
reg3.r.rx_slot_2 = 0;
else
reg3.r.rx_slot_2 = i2s_right_slot;
reg6.r.rx_pause_start_pos = i2s_right_pause_pos;
reg6.r.rx_pause_cycles = i2s_right_pause_interval;
reg6.r.tx_pause_start_pos = i2s_right_pause_pos;
reg6.r.tx_pause_cycles = i2s_right_pause_interval;
} else {
dev_err(dev, "TDM mode is not implemented yet\n");
return -EINVAL;
}
regdbt2.r.i2s_bclk_invert = is_bclk_inv;
/* Configures the BCLK output */
bclk_rate = cx2072x->sample_rate * frame_len;
reg5.r.i2s_pcm_clk_div_chan_en = 0;
/* Disables bclk output before setting new value */
regmap_write(cx2072x->regmap, CX2072X_I2SPCM_CONTROL5, 0);
if (reg2.r.tx_master) {
/* Configures BCLK rate */
div = PLL_OUT_HZ_48;
mod = do_div(div, bclk_rate);
if (mod) {
dev_err(dev, "Unsupported BCLK %dHz\n", bclk_rate);
return -EINVAL;
}
dev_dbg(dev, "enables BCLK %dHz output\n", bclk_rate);
reg5.r.i2s_pcm_clk_div = (u32)div - 1;
reg5.r.i2s_pcm_clk_div_chan_en = 1;
}
regmap_write(cx2072x->regmap, CX2072X_I2SPCM_CONTROL1, reg1.ulval);
regmap_update_bits(cx2072x->regmap, CX2072X_I2SPCM_CONTROL2, 0xffffffc0,
reg2.ulval);
regmap_update_bits(cx2072x->regmap, CX2072X_I2SPCM_CONTROL3, 0xffffffc0,
reg3.ulval);
regmap_write(cx2072x->regmap, CX2072X_I2SPCM_CONTROL4, reg4.ulval);
regmap_write(cx2072x->regmap, CX2072X_I2SPCM_CONTROL6, reg6.ulval);
regmap_write(cx2072x->regmap, CX2072X_I2SPCM_CONTROL5, reg5.ulval);
regmap_write(cx2072x->regmap, CX2072X_DIGITAL_BIOS_TEST2,
regdbt2.ulval);
return 0;
}
static int afg_power_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *codec = snd_soc_dapm_to_component(w->dapm);
struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_update_bits(cx2072x->regmap, CX2072X_DIGITAL_BIOS_TEST0,
0x00, 0x10);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_update_bits(cx2072x->regmap, CX2072X_DIGITAL_BIOS_TEST0,
0x10, 0x10);
break;
}
return 0;
}
static const struct snd_kcontrol_new cx2072x_snd_controls[] = {
SOC_DOUBLE_R_TLV("PortD Boost Volume", CX2072X_PORTD_GAIN_LEFT,
CX2072X_PORTD_GAIN_RIGHT, 0, 3, 0, boost_tlv),
SOC_DOUBLE_R_TLV("PortC Boost Volume", CX2072X_PORTC_GAIN_LEFT,
CX2072X_PORTC_GAIN_RIGHT, 0, 3, 0, boost_tlv),
SOC_DOUBLE_R_TLV("PortB Boost Volume", CX2072X_PORTB_GAIN_LEFT,
CX2072X_PORTB_GAIN_RIGHT, 0, 3, 0, boost_tlv),
SOC_DOUBLE_R_TLV("PortD ADC1 Volume", CX2072X_ADC1_AMP_GAIN_LEFT_1,
CX2072X_ADC1_AMP_GAIN_RIGHT_1, 0, 0x4a, 0, adc_tlv),
SOC_DOUBLE_R_TLV("PortC ADC1 Volume", CX2072X_ADC1_AMP_GAIN_LEFT_2,
CX2072X_ADC1_AMP_GAIN_RIGHT_2, 0, 0x4a, 0, adc_tlv),
SOC_DOUBLE_R_TLV("PortB ADC1 Volume", CX2072X_ADC1_AMP_GAIN_LEFT_0,
CX2072X_ADC1_AMP_GAIN_RIGHT_0, 0, 0x4a, 0, adc_tlv),
SOC_DOUBLE_R_TLV("DAC1 Volume", CX2072X_DAC1_AMP_GAIN_LEFT,
CX2072X_DAC1_AMP_GAIN_RIGHT, 0, 0x4a, 0, dac_tlv),
SOC_DOUBLE_R("DAC1 Switch", CX2072X_DAC1_AMP_GAIN_LEFT,
CX2072X_DAC1_AMP_GAIN_RIGHT, 7, 1, 0),
SOC_DOUBLE_R_TLV("DAC2 Volume", CX2072X_DAC2_AMP_GAIN_LEFT,
CX2072X_DAC2_AMP_GAIN_RIGHT, 0, 0x4a, 0, dac_tlv),
SOC_SINGLE_TLV("HPF Freq", CX2072X_CODEC_TEST9, 0, 0x3f, 0, hpf_tlv),
SOC_DOUBLE("HPF Switch", CX2072X_CODEC_TEST9, 8, 9, 1, 1),
SOC_SINGLE("PortA HP Amp Switch", CX2072X_PORTA_PIN_CTRL, 7, 1, 0),
};
static int cx2072x_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *codec = dai->component;
struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
struct device *dev = codec->dev;
const unsigned int sample_rate = params_rate(params);
int sample_size, frame_size;
/* Data sizes if not using TDM */
sample_size = params_width(params);
if (sample_size < 0)
return sample_size;
frame_size = snd_soc_params_to_frame_size(params);
if (frame_size < 0)
return frame_size;
if (cx2072x->mclk_rate == 0) {
dev_err(dev, "Master clock rate is not configured\n");
return -EINVAL;
}
if (cx2072x->bclk_ratio)
frame_size = cx2072x->bclk_ratio;
switch (sample_rate) {
case 48000:
case 32000:
case 24000:
case 16000:
case 96000:
case 192000:
break;
default:
dev_err(dev, "Unsupported sample rate %d\n", sample_rate);
return -EINVAL;
}
dev_dbg(dev, "Sample size %d bits, frame = %d bits, rate = %d Hz\n",
sample_size, frame_size, sample_rate);
cx2072x->frame_size = frame_size;
cx2072x->sample_size = sample_size;
cx2072x->sample_rate = sample_rate;
if (dai->id == CX2072X_DAI_DSP) {
cx2072x->en_aec_ref = true;
dev_dbg(cx2072x->dev, "enables aec reference\n");
regmap_write(cx2072x->regmap,
CX2072X_ADC1_CONNECTION_SELECT_CONTROL, 3);
}
if (cx2072x->pll_changed) {
cx2072x_config_pll(cx2072x);
cx2072x->pll_changed = false;
}
if (cx2072x->i2spcm_changed) {
cx2072x_config_i2spcm(cx2072x);
cx2072x->i2spcm_changed = false;
}
return 0;
}
static int cx2072x_set_dai_bclk_ratio(struct snd_soc_dai *dai,
unsigned int ratio)
{
struct snd_soc_component *codec = dai->component;
struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
cx2072x->bclk_ratio = ratio;
return 0;
}
static int cx2072x_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct snd_soc_component *codec = dai->component;
struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
if (clk_set_rate(cx2072x->mclk, freq)) {
dev_err(codec->dev, "set clk rate failed\n");
return -EINVAL;
}
cx2072x->mclk_rate = freq;
return 0;
}
static int cx2072x_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *codec = dai->component;
struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
struct device *dev = codec->dev;
dev_dbg(dev, "set_dai_fmt- %08x\n", fmt);
/* set master/slave */
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
case SND_SOC_DAIFMT_CBC_CFC:
break;
default:
dev_err(dev, "Unsupported DAI master mode\n");
return -EINVAL;
}
/* set format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_RIGHT_J:
case SND_SOC_DAIFMT_LEFT_J:
break;
default:
dev_err(dev, "Unsupported DAI format\n");
return -EINVAL;
}
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
case SND_SOC_DAIFMT_IB_IF:
case SND_SOC_DAIFMT_IB_NF:
case SND_SOC_DAIFMT_NB_IF:
break;
default:
dev_err(dev, "Unsupported DAI clock inversion\n");
return -EINVAL;
}
cx2072x->dai_fmt = fmt;
return 0;
}
static const struct snd_kcontrol_new portaouten_ctl =
SOC_DAPM_SINGLE("Switch", CX2072X_PORTA_PIN_CTRL, 6, 1, 0);
static const struct snd_kcontrol_new porteouten_ctl =
SOC_DAPM_SINGLE("Switch", CX2072X_PORTE_PIN_CTRL, 6, 1, 0);
static const struct snd_kcontrol_new portgouten_ctl =
SOC_DAPM_SINGLE("Switch", CX2072X_PORTG_PIN_CTRL, 6, 1, 0);
static const struct snd_kcontrol_new portmouten_ctl =
SOC_DAPM_SINGLE("Switch", CX2072X_PORTM_PIN_CTRL, 6, 1, 0);
static const struct snd_kcontrol_new portbinen_ctl =
SOC_DAPM_SINGLE("Switch", CX2072X_PORTB_PIN_CTRL, 5, 1, 0);
static const struct snd_kcontrol_new portcinen_ctl =
SOC_DAPM_SINGLE("Switch", CX2072X_PORTC_PIN_CTRL, 5, 1, 0);
static const struct snd_kcontrol_new portdinen_ctl =
SOC_DAPM_SINGLE("Switch", CX2072X_PORTD_PIN_CTRL, 5, 1, 0);
static const struct snd_kcontrol_new porteinen_ctl =
SOC_DAPM_SINGLE("Switch", CX2072X_PORTE_PIN_CTRL, 5, 1, 0);
static const struct snd_kcontrol_new i2sadc1l_ctl =
SOC_DAPM_SINGLE("Switch", CX2072X_I2SPCM_CONTROL2, 0, 1, 0);
static const struct snd_kcontrol_new i2sadc1r_ctl =
SOC_DAPM_SINGLE("Switch", CX2072X_I2SPCM_CONTROL2, 1, 1, 0);
static const struct snd_kcontrol_new i2sadc2l_ctl =
SOC_DAPM_SINGLE("Switch", CX2072X_I2SPCM_CONTROL2, 2, 1, 0);
static const struct snd_kcontrol_new i2sadc2r_ctl =
SOC_DAPM_SINGLE("Switch", CX2072X_I2SPCM_CONTROL2, 3, 1, 0);
static const struct snd_kcontrol_new i2sdac1l_ctl =
SOC_DAPM_SINGLE("Switch", CX2072X_I2SPCM_CONTROL3, 0, 1, 0);
static const struct snd_kcontrol_new i2sdac1r_ctl =
SOC_DAPM_SINGLE("Switch", CX2072X_I2SPCM_CONTROL3, 1, 1, 0);
static const struct snd_kcontrol_new i2sdac2l_ctl =
SOC_DAPM_SINGLE("Switch", CX2072X_I2SPCM_CONTROL3, 2, 1, 0);
static const struct snd_kcontrol_new i2sdac2r_ctl =
SOC_DAPM_SINGLE("Switch", CX2072X_I2SPCM_CONTROL3, 3, 1, 0);
static const char * const dac_enum_text[] = {
"DAC1 Switch", "DAC2 Switch",
};
static const struct soc_enum porta_dac_enum =
SOC_ENUM_SINGLE(CX2072X_PORTA_CONNECTION_SELECT_CTRL, 0, 2, dac_enum_text);
static const struct snd_kcontrol_new porta_mux =
SOC_DAPM_ENUM("PortA Mux", porta_dac_enum);
static const struct soc_enum portg_dac_enum =
SOC_ENUM_SINGLE(CX2072X_PORTG_CONNECTION_SELECT_CTRL, 0, 2, dac_enum_text);
static const struct snd_kcontrol_new portg_mux =
SOC_DAPM_ENUM("PortG Mux", portg_dac_enum);
static const struct soc_enum porte_dac_enum =
SOC_ENUM_SINGLE(CX2072X_PORTE_CONNECTION_SELECT_CTRL, 0, 2, dac_enum_text);
static const struct snd_kcontrol_new porte_mux =
SOC_DAPM_ENUM("PortE Mux", porte_dac_enum);
static const struct soc_enum portm_dac_enum =
SOC_ENUM_SINGLE(CX2072X_PORTM_CONNECTION_SELECT_CTRL, 0, 2, dac_enum_text);
static const struct snd_kcontrol_new portm_mux =
SOC_DAPM_ENUM("PortM Mux", portm_dac_enum);
static const char * const adc1in_sel_text[] = {
"PortB Switch", "PortD Switch", "PortC Switch", "Widget15 Switch",
"PortE Switch", "PortF Switch", "PortH Switch"
};
static const struct soc_enum adc1in_sel_enum =
SOC_ENUM_SINGLE(CX2072X_ADC1_CONNECTION_SELECT_CONTROL, 0, 7, adc1in_sel_text);
static const struct snd_kcontrol_new adc1_mux =
SOC_DAPM_ENUM("ADC1 Mux", adc1in_sel_enum);
static const char * const adc2in_sel_text[] = {
"PortC Switch", "Widget15 Switch", "PortH Switch"
};
static const struct soc_enum adc2in_sel_enum =
SOC_ENUM_SINGLE(CX2072X_ADC2_CONNECTION_SELECT_CONTROL, 0, 3, adc2in_sel_text);
static const struct snd_kcontrol_new adc2_mux =
SOC_DAPM_ENUM("ADC2 Mux", adc2in_sel_enum);
static const struct snd_kcontrol_new wid15_mix[] = {
SOC_DAPM_SINGLE("DAC1L Switch", CX2072X_MIXER_GAIN_LEFT_0, 7, 1, 1),
SOC_DAPM_SINGLE("DAC1R Switch", CX2072X_MIXER_GAIN_RIGHT_0, 7, 1, 1),
SOC_DAPM_SINGLE("DAC2L Switch", CX2072X_MIXER_GAIN_LEFT_1, 7, 1, 1),
SOC_DAPM_SINGLE("DAC2R Switch", CX2072X_MIXER_GAIN_RIGHT_1, 7, 1, 1),
};
#define CX2072X_DAPM_SUPPLY_S(wname, wsubseq, wreg, wshift, wmask, won_val, \
woff_val, wevent, wflags) \
{.id = snd_soc_dapm_supply, .name = wname, .kcontrol_news = NULL, \
.num_kcontrols = 0, .reg = wreg, .shift = wshift, .mask = wmask, \
.on_val = won_val, .off_val = woff_val, \
.subseq = wsubseq, .event = wevent, .event_flags = wflags}
#define CX2072X_DAPM_SWITCH(wname, wreg, wshift, wmask, won_val, woff_val, \
wevent, wflags) \
{.id = snd_soc_dapm_switch, .name = wname, .kcontrol_news = NULL, \
.num_kcontrols = 0, .reg = wreg, .shift = wshift, .mask = wmask, \
.on_val = won_val, .off_val = woff_val, \
.event = wevent, .event_flags = wflags}
#define CX2072X_DAPM_SWITCH(wname, wreg, wshift, wmask, won_val, woff_val, \
wevent, wflags) \
{.id = snd_soc_dapm_switch, .name = wname, .kcontrol_news = NULL, \
.num_kcontrols = 0, .reg = wreg, .shift = wshift, .mask = wmask, \
.on_val = won_val, .off_val = woff_val, \
.event = wevent, .event_flags = wflags}
#define CX2072X_DAPM_REG_E(wid, wname, wreg, wshift, wmask, won_val, woff_val, \
wevent, wflags) \
{.id = wid, .name = wname, .kcontrol_news = NULL, .num_kcontrols = 0, \
.reg = wreg, .shift = wshift, .mask = wmask, \
.on_val = won_val, .off_val = woff_val, \
.event = wevent, .event_flags = wflags}
static const struct snd_soc_dapm_widget cx2072x_dapm_widgets[] = {
/*Playback*/
SND_SOC_DAPM_AIF_IN("In AIF", "Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SWITCH("I2S DAC1L", SND_SOC_NOPM, 0, 0, &i2sdac1l_ctl),
SND_SOC_DAPM_SWITCH("I2S DAC1R", SND_SOC_NOPM, 0, 0, &i2sdac1r_ctl),
SND_SOC_DAPM_SWITCH("I2S DAC2L", SND_SOC_NOPM, 0, 0, &i2sdac2l_ctl),
SND_SOC_DAPM_SWITCH("I2S DAC2R", SND_SOC_NOPM, 0, 0, &i2sdac2r_ctl),
SND_SOC_DAPM_REG(snd_soc_dapm_dac, "DAC1", CX2072X_DAC1_POWER_STATE,
0, 0xfff, 0x00, 0x03),
SND_SOC_DAPM_REG(snd_soc_dapm_dac, "DAC2", CX2072X_DAC2_POWER_STATE,
0, 0xfff, 0x00, 0x03),
SND_SOC_DAPM_MUX("PortA Mux", SND_SOC_NOPM, 0, 0, &porta_mux),
SND_SOC_DAPM_MUX("PortG Mux", SND_SOC_NOPM, 0, 0, &portg_mux),
SND_SOC_DAPM_MUX("PortE Mux", SND_SOC_NOPM, 0, 0, &porte_mux),
SND_SOC_DAPM_MUX("PortM Mux", SND_SOC_NOPM, 0, 0, &portm_mux),
SND_SOC_DAPM_REG(snd_soc_dapm_supply, "PortA Power",
CX2072X_PORTA_POWER_STATE, 0, 0xfff, 0x00, 0x03),
SND_SOC_DAPM_REG(snd_soc_dapm_supply, "PortM Power",
CX2072X_PORTM_POWER_STATE, 0, 0xfff, 0x00, 0x03),
SND_SOC_DAPM_REG(snd_soc_dapm_supply, "PortG Power",
CX2072X_PORTG_POWER_STATE, 0, 0xfff, 0x00, 0x03),
CX2072X_DAPM_SUPPLY_S("AFG Power", 0, CX2072X_AFG_POWER_STATE,
0, 0xfff, 0x00, 0x03, afg_power_ev,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SWITCH("PortA Out En", SND_SOC_NOPM, 0, 0,
&portaouten_ctl),
SND_SOC_DAPM_SWITCH("PortE Out En", SND_SOC_NOPM, 0, 0,
&porteouten_ctl),
SND_SOC_DAPM_SWITCH("PortG Out En", SND_SOC_NOPM, 0, 0,
&portgouten_ctl),
SND_SOC_DAPM_SWITCH("PortM Out En", SND_SOC_NOPM, 0, 0,
&portmouten_ctl),
SND_SOC_DAPM_OUTPUT("PORTA"),
SND_SOC_DAPM_OUTPUT("PORTG"),
SND_SOC_DAPM_OUTPUT("PORTE"),
SND_SOC_DAPM_OUTPUT("PORTM"),
SND_SOC_DAPM_OUTPUT("AEC REF"),
/*Capture*/
SND_SOC_DAPM_AIF_OUT("Out AIF", "Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SWITCH("I2S ADC1L", SND_SOC_NOPM, 0, 0, &i2sadc1l_ctl),
SND_SOC_DAPM_SWITCH("I2S ADC1R", SND_SOC_NOPM, 0, 0, &i2sadc1r_ctl),
SND_SOC_DAPM_SWITCH("I2S ADC2L", SND_SOC_NOPM, 0, 0, &i2sadc2l_ctl),
SND_SOC_DAPM_SWITCH("I2S ADC2R", SND_SOC_NOPM, 0, 0, &i2sadc2r_ctl),
SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ADC1", CX2072X_ADC1_POWER_STATE,
0, 0xff, 0x00, 0x03),
SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ADC2", CX2072X_ADC2_POWER_STATE,
0, 0xff, 0x00, 0x03),
SND_SOC_DAPM_MUX("ADC1 Mux", SND_SOC_NOPM, 0, 0, &adc1_mux),
SND_SOC_DAPM_MUX("ADC2 Mux", SND_SOC_NOPM, 0, 0, &adc2_mux),
SND_SOC_DAPM_REG(snd_soc_dapm_supply, "PortB Power",
CX2072X_PORTB_POWER_STATE, 0, 0xfff, 0x00, 0x03),
SND_SOC_DAPM_REG(snd_soc_dapm_supply, "PortC Power",
CX2072X_PORTC_POWER_STATE, 0, 0xfff, 0x00, 0x03),
SND_SOC_DAPM_REG(snd_soc_dapm_supply, "PortD Power",
CX2072X_PORTD_POWER_STATE, 0, 0xfff, 0x00, 0x03),
SND_SOC_DAPM_REG(snd_soc_dapm_supply, "PortE Power",
CX2072X_PORTE_POWER_STATE, 0, 0xfff, 0x00, 0x03),
SND_SOC_DAPM_REG(snd_soc_dapm_supply, "Widget15 Power",
CX2072X_MIXER_POWER_STATE, 0, 0xfff, 0x00, 0x03),
SND_SOC_DAPM_MIXER("Widget15 Mixer", SND_SOC_NOPM, 0, 0,
wid15_mix, ARRAY_SIZE(wid15_mix)),
SND_SOC_DAPM_SWITCH("PortB In En", SND_SOC_NOPM, 0, 0, &portbinen_ctl),
SND_SOC_DAPM_SWITCH("PortC In En", SND_SOC_NOPM, 0, 0, &portcinen_ctl),
SND_SOC_DAPM_SWITCH("PortD In En", SND_SOC_NOPM, 0, 0, &portdinen_ctl),
SND_SOC_DAPM_SWITCH("PortE In En", SND_SOC_NOPM, 0, 0, &porteinen_ctl),
SND_SOC_DAPM_MICBIAS("Headset Bias", CX2072X_ANALOG_TEST11, 1, 0),
SND_SOC_DAPM_MICBIAS("PortB Mic Bias", CX2072X_PORTB_PIN_CTRL, 2, 0),
SND_SOC_DAPM_MICBIAS("PortD Mic Bias", CX2072X_PORTD_PIN_CTRL, 2, 0),
SND_SOC_DAPM_MICBIAS("PortE Mic Bias", CX2072X_PORTE_PIN_CTRL, 2, 0),
SND_SOC_DAPM_INPUT("PORTB"),
SND_SOC_DAPM_INPUT("PORTC"),
SND_SOC_DAPM_INPUT("PORTD"),
SND_SOC_DAPM_INPUT("PORTEIN"),
};
static const struct snd_soc_dapm_route cx2072x_intercon[] = {
/* Playback */
{"In AIF", NULL, "AFG Power"},
{"I2S DAC1L", "Switch", "In AIF"},
{"I2S DAC1R", "Switch", "In AIF"},
{"I2S DAC2L", "Switch", "In AIF"},
{"I2S DAC2R", "Switch", "In AIF"},
{"DAC1", NULL, "I2S DAC1L"},
{"DAC1", NULL, "I2S DAC1R"},
{"DAC2", NULL, "I2S DAC2L"},
{"DAC2", NULL, "I2S DAC2R"},
{"PortA Mux", "DAC1 Switch", "DAC1"},
{"PortA Mux", "DAC2 Switch", "DAC2"},
{"PortG Mux", "DAC1 Switch", "DAC1"},
{"PortG Mux", "DAC2 Switch", "DAC2"},
{"PortE Mux", "DAC1 Switch", "DAC1"},
{"PortE Mux", "DAC2 Switch", "DAC2"},
{"PortM Mux", "DAC1 Switch", "DAC1"},
{"PortM Mux", "DAC2 Switch", "DAC2"},
{"Widget15 Mixer", "DAC1L Switch", "DAC1"},
{"Widget15 Mixer", "DAC1R Switch", "DAC2"},
{"Widget15 Mixer", "DAC2L Switch", "DAC1"},
{"Widget15 Mixer", "DAC2R Switch", "DAC2"},
{"Widget15 Mixer", NULL, "Widget15 Power"},
{"PortA Out En", "Switch", "PortA Mux"},
{"PortG Out En", "Switch", "PortG Mux"},
{"PortE Out En", "Switch", "PortE Mux"},
{"PortM Out En", "Switch", "PortM Mux"},
{"PortA Mux", NULL, "PortA Power"},
{"PortG Mux", NULL, "PortG Power"},
{"PortE Mux", NULL, "PortE Power"},
{"PortM Mux", NULL, "PortM Power"},
{"PortA Out En", NULL, "PortA Power"},
{"PortG Out En", NULL, "PortG Power"},
{"PortE Out En", NULL, "PortE Power"},
{"PortM Out En", NULL, "PortM Power"},
{"PORTA", NULL, "PortA Out En"},
{"PORTG", NULL, "PortG Out En"},
{"PORTE", NULL, "PortE Out En"},
{"PORTM", NULL, "PortM Out En"},
/* Capture */
{"PORTD", NULL, "Headset Bias"},
{"PortB In En", "Switch", "PORTB"},
{"PortC In En", "Switch", "PORTC"},
{"PortD In En", "Switch", "PORTD"},
{"PortE In En", "Switch", "PORTEIN"},
{"ADC1 Mux", "PortB Switch", "PortB In En"},
{"ADC1 Mux", "PortC Switch", "PortC In En"},
{"ADC1 Mux", "PortD Switch", "PortD In En"},
{"ADC1 Mux", "PortE Switch", "PortE In En"},
{"ADC1 Mux", "Widget15 Switch", "Widget15 Mixer"},
{"ADC2 Mux", "PortC Switch", "PortC In En"},
{"ADC2 Mux", "Widget15 Switch", "Widget15 Mixer"},
{"ADC1", NULL, "ADC1 Mux"},
{"ADC2", NULL, "ADC2 Mux"},
{"I2S ADC1L", "Switch", "ADC1"},
{"I2S ADC1R", "Switch", "ADC1"},
{"I2S ADC2L", "Switch", "ADC2"},
{"I2S ADC2R", "Switch", "ADC2"},
{"Out AIF", NULL, "I2S ADC1L"},
{"Out AIF", NULL, "I2S ADC1R"},
{"Out AIF", NULL, "I2S ADC2L"},
{"Out AIF", NULL, "I2S ADC2R"},
{"Out AIF", NULL, "AFG Power"},
{"AEC REF", NULL, "Out AIF"},
{"PortB In En", NULL, "PortB Power"},
{"PortC In En", NULL, "PortC Power"},
{"PortD In En", NULL, "PortD Power"},
{"PortE In En", NULL, "PortE Power"},
};
static int cx2072x_set_bias_level(struct snd_soc_component *codec,
enum snd_soc_bias_level level)
{
struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
const enum snd_soc_bias_level old_level =
snd_soc_component_get_bias_level(codec);
if (level == SND_SOC_BIAS_STANDBY && old_level == SND_SOC_BIAS_OFF)
regmap_write(cx2072x->regmap, CX2072X_AFG_POWER_STATE, 0);
else if (level == SND_SOC_BIAS_OFF && old_level != SND_SOC_BIAS_OFF)
regmap_write(cx2072x->regmap, CX2072X_AFG_POWER_STATE, 3);
return 0;
}
/*
* FIXME: the whole jack detection code below is pretty platform-specific;
* it has lots of implicit assumptions about the pins, etc.
* However, since we have no other code and reference, take this hard-coded
* setup for now. Once when we have different platform implementations,
* this needs to be rewritten in a more generic form, or moving into the
* platform data.
*/
static void cx2072x_enable_jack_detect(struct snd_soc_component *codec)
{
struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(codec);
/* No-sticky input type */
regmap_write(cx2072x->regmap, CX2072X_GPIO_STICKY_MASK, 0x1f);
/* Use GPOI0 as interrupt pin */
regmap_write(cx2072x->regmap, CX2072X_UM_INTERRUPT_CRTL_E, 0x12 << 24);
/* Enables unsolitited message on PortA */
regmap_write(cx2072x->regmap, CX2072X_PORTA_UNSOLICITED_RESPONSE, 0x80);
/* support both nokia and apple headset set. Monitor time = 275 ms */
regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST15, 0x73);
/* Disable TIP detection */
regmap_write(cx2072x->regmap, CX2072X_ANALOG_TEST12, 0x300);
/* Switch MusicD3Live pin to GPIO */
regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST1, 0);
snd_soc_dapm_mutex_lock(dapm);
snd_soc_dapm_force_enable_pin_unlocked(dapm, "PORTD");
snd_soc_dapm_force_enable_pin_unlocked(dapm, "Headset Bias");
snd_soc_dapm_force_enable_pin_unlocked(dapm, "PortD Mic Bias");
snd_soc_dapm_mutex_unlock(dapm);
}
static void cx2072x_disable_jack_detect(struct snd_soc_component *codec)
{
struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
regmap_write(cx2072x->regmap, CX2072X_UM_INTERRUPT_CRTL_E, 0);
regmap_write(cx2072x->regmap, CX2072X_PORTA_UNSOLICITED_RESPONSE, 0);
}
static int cx2072x_jack_status_check(void *data)
{
struct snd_soc_component *codec = data;
struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
unsigned int jack;
unsigned int type = 0;
int state = 0;
mutex_lock(&cx2072x->lock);
regmap_read(cx2072x->regmap, CX2072X_PORTA_PIN_SENSE, &jack);
jack = jack >> 24;
regmap_read(cx2072x->regmap, CX2072X_DIGITAL_TEST11, &type);
if (jack == 0x80) {
type = type >> 8;
if (type & 0x8) {
/* Apple headset */
state |= SND_JACK_HEADSET;
if (type & 0x2)
state |= SND_JACK_BTN_0;
} else {
/*
* Nokia headset (type & 0x4) and
* regular Headphone
*/
state |= SND_JACK_HEADPHONE;
}
}
/* clear interrupt */
regmap_write(cx2072x->regmap, CX2072X_UM_INTERRUPT_CRTL_E, 0x12 << 24);
mutex_unlock(&cx2072x->lock);
dev_dbg(codec->dev, "CX2072X_HSDETECT type=0x%X,Jack state = %x\n",
type, state);
return state;
}
static const struct snd_soc_jack_gpio cx2072x_jack_gpio = {
.name = "headset",
.report = SND_JACK_HEADSET | SND_JACK_BTN_0,
.debounce_time = 150,
.wake = true,
.jack_status_check = cx2072x_jack_status_check,
};
static int cx2072x_set_jack(struct snd_soc_component *codec,
struct snd_soc_jack *jack, void *data)
{
struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
int err;
if (!jack) {
cx2072x_disable_jack_detect(codec);
return 0;
}
if (!cx2072x->jack_gpio.gpiod_dev) {
cx2072x->jack_gpio = cx2072x_jack_gpio;
cx2072x->jack_gpio.gpiod_dev = codec->dev;
cx2072x->jack_gpio.data = codec;
err = snd_soc_jack_add_gpios(jack, 1, &cx2072x->jack_gpio);
if (err) {
cx2072x->jack_gpio.gpiod_dev = NULL;
return err;
}
}
cx2072x_enable_jack_detect(codec);
return 0;
}
static int cx2072x_probe(struct snd_soc_component *codec)
{
struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
cx2072x->codec = codec;
/*
* FIXME: below is, again, a very platform-specific init sequence,
* but we keep the code here just for simplicity. It seems that all
* existing hardware implementations require this, so there is no very
* much reason to move this out of the codec driver to the platform
* data.
* But of course it's no "right" thing; if you are a good boy, don't
* read and follow the code like this!
*/
pm_runtime_get_sync(codec->dev);
regmap_write(cx2072x->regmap, CX2072X_AFG_POWER_STATE, 0);
regmap_multi_reg_write(cx2072x->regmap, cx2072x_reg_init,
ARRAY_SIZE(cx2072x_reg_init));
/* configure PortC as input device */
regmap_update_bits(cx2072x->regmap, CX2072X_PORTC_PIN_CTRL,
0x20, 0x20);
regmap_update_bits(cx2072x->regmap, CX2072X_DIGITAL_BIOS_TEST2,
0x84, 0xff);
regmap_write(cx2072x->regmap, CX2072X_AFG_POWER_STATE, 3);
pm_runtime_put(codec->dev);
return 0;
}
static const struct snd_soc_component_driver soc_codec_driver_cx2072x = {
.probe = cx2072x_probe,
.set_bias_level = cx2072x_set_bias_level,
.set_jack = cx2072x_set_jack,
.controls = cx2072x_snd_controls,
.num_controls = ARRAY_SIZE(cx2072x_snd_controls),
.dapm_widgets = cx2072x_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(cx2072x_dapm_widgets),
.dapm_routes = cx2072x_intercon,
.num_dapm_routes = ARRAY_SIZE(cx2072x_intercon),
.endianness = 1,
};
/*
* DAI ops
*/
static const struct snd_soc_dai_ops cx2072x_dai_ops = {
.set_sysclk = cx2072x_set_dai_sysclk,
.set_fmt = cx2072x_set_dai_fmt,
.hw_params = cx2072x_hw_params,
.set_bclk_ratio = cx2072x_set_dai_bclk_ratio,
};
static int cx2072x_dsp_dai_probe(struct snd_soc_dai *dai)
{
struct cx2072x_priv *cx2072x =
snd_soc_component_get_drvdata(dai->component);
cx2072x->en_aec_ref = true;
return 0;
}
static const struct snd_soc_dai_ops cx2072x_dai_ops2 = {
.probe = cx2072x_dsp_dai_probe,
.set_sysclk = cx2072x_set_dai_sysclk,
.set_fmt = cx2072x_set_dai_fmt,
.hw_params = cx2072x_hw_params,
.set_bclk_ratio = cx2072x_set_dai_bclk_ratio,
};
#define CX2072X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
static struct snd_soc_dai_driver soc_codec_cx2072x_dai[] = {
{ /* playback and capture */
.name = "cx2072x-hifi",
.id = CX2072X_DAI_HIFI,
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = CX2072X_RATES_DSP,
.formats = CX2072X_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = CX2072X_RATES_DSP,
.formats = CX2072X_FORMATS,
},
.ops = &cx2072x_dai_ops,
.symmetric_rate = 1,
},
{ /* plabayck only, return echo reference to Conexant DSP chip */
.name = "cx2072x-dsp",
.id = CX2072X_DAI_DSP,
.playback = {
.stream_name = "DSP Playback",
.channels_min = 2,
.channels_max = 2,
.rates = CX2072X_RATES_DSP,
.formats = CX2072X_FORMATS,
},
.ops = &cx2072x_dai_ops2,
},
{ /* plabayck only, return echo reference through I2S TX */
.name = "cx2072x-aec",
.id = 3,
.capture = {
.stream_name = "AEC Capture",
.channels_min = 2,
.channels_max = 2,
.rates = CX2072X_RATES_DSP,
.formats = CX2072X_FORMATS,
},
},
};
static const struct regmap_config cx2072x_regmap = {
.reg_bits = 16,
.val_bits = 32,
.max_register = CX2072X_REG_MAX,
.reg_defaults = cx2072x_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(cx2072x_reg_defaults),
.cache_type = REGCACHE_RBTREE,
.readable_reg = cx2072x_readable_register,
.volatile_reg = cx2072x_volatile_register,
/* Needs custom read/write functions for various register lengths */
.reg_read = cx2072x_reg_read,
.reg_write = cx2072x_reg_write,
};
static int __maybe_unused cx2072x_runtime_suspend(struct device *dev)
{
struct cx2072x_priv *cx2072x = dev_get_drvdata(dev);
clk_disable_unprepare(cx2072x->mclk);
return 0;
}
static int __maybe_unused cx2072x_runtime_resume(struct device *dev)
{
struct cx2072x_priv *cx2072x = dev_get_drvdata(dev);
return clk_prepare_enable(cx2072x->mclk);
}
static int cx2072x_i2c_probe(struct i2c_client *i2c)
{
struct cx2072x_priv *cx2072x;
unsigned int ven_id, rev_id;
int ret;
cx2072x = devm_kzalloc(&i2c->dev, sizeof(struct cx2072x_priv),
GFP_KERNEL);
if (!cx2072x)
return -ENOMEM;
cx2072x->regmap = devm_regmap_init(&i2c->dev, NULL, i2c,
&cx2072x_regmap);
if (IS_ERR(cx2072x->regmap))
return PTR_ERR(cx2072x->regmap);
mutex_init(&cx2072x->lock);
i2c_set_clientdata(i2c, cx2072x);
cx2072x->dev = &i2c->dev;
cx2072x->pll_changed = true;
cx2072x->i2spcm_changed = true;
cx2072x->bclk_ratio = 0;
cx2072x->mclk = devm_clk_get(cx2072x->dev, "mclk");
if (IS_ERR(cx2072x->mclk)) {
dev_err(cx2072x->dev, "Failed to get MCLK\n");
return PTR_ERR(cx2072x->mclk);
}
regmap_read(cx2072x->regmap, CX2072X_VENDOR_ID, &ven_id);
regmap_read(cx2072x->regmap, CX2072X_REVISION_ID, &rev_id);
dev_info(cx2072x->dev, "codec version: %08x,%08x\n", ven_id, rev_id);
ret = devm_snd_soc_register_component(cx2072x->dev,
&soc_codec_driver_cx2072x,
soc_codec_cx2072x_dai,
ARRAY_SIZE(soc_codec_cx2072x_dai));
if (ret < 0)
return ret;
pm_runtime_use_autosuspend(cx2072x->dev);
pm_runtime_enable(cx2072x->dev);
return 0;
}
static void cx2072x_i2c_remove(struct i2c_client *i2c)
{
pm_runtime_disable(&i2c->dev);
}
static const struct i2c_device_id cx2072x_i2c_id[] = {
{ "cx20721", 0 },
{ "cx20723", 0 },
{}
};
MODULE_DEVICE_TABLE(i2c, cx2072x_i2c_id);
#ifdef CONFIG_ACPI
static struct acpi_device_id cx2072x_acpi_match[] = {
{ "14F10720", 0 },
{},
};
MODULE_DEVICE_TABLE(acpi, cx2072x_acpi_match);
#endif
static const struct dev_pm_ops cx2072x_runtime_pm = {
SET_RUNTIME_PM_OPS(cx2072x_runtime_suspend, cx2072x_runtime_resume,
NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static struct i2c_driver cx2072x_i2c_driver = {
.driver = {
.name = "cx2072x",
.acpi_match_table = ACPI_PTR(cx2072x_acpi_match),
.pm = &cx2072x_runtime_pm,
},
.probe = cx2072x_i2c_probe,
.remove = cx2072x_i2c_remove,
.id_table = cx2072x_i2c_id,
};
module_i2c_driver(cx2072x_i2c_driver);
MODULE_DESCRIPTION("ASoC cx2072x Codec Driver");
MODULE_AUTHOR("Simon Ho <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cx2072x.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* rt5677-spi.c -- RT5677 ALSA SoC audio codec driver
*
* Copyright 2013 Realtek Semiconductor Corp.
* Author: Oder Chiou <[email protected]>
*/
#include <linux/module.h>
#include <linux/input.h>
#include <linux/spi/spi.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <linux/sched.h>
#include <linux/uaccess.h>
#include <linux/regulator/consumer.h>
#include <linux/pm_qos.h>
#include <linux/sysfs.h>
#include <linux/clk.h>
#include <linux/firmware.h>
#include <linux/acpi.h>
#include <sound/soc.h>
#include "rt5677.h"
#include "rt5677-spi.h"
#define DRV_NAME "rt5677spi"
#define RT5677_SPI_BURST_LEN 240
#define RT5677_SPI_HEADER 5
#define RT5677_SPI_FREQ 6000000
/* The AddressPhase and DataPhase of SPI commands are MSB first on the wire.
* DataPhase word size of 16-bit commands is 2 bytes.
* DataPhase word size of 32-bit commands is 4 bytes.
* DataPhase word size of burst commands is 8 bytes.
* The DSP CPU is little-endian.
*/
#define RT5677_SPI_WRITE_BURST 0x5
#define RT5677_SPI_READ_BURST 0x4
#define RT5677_SPI_WRITE_32 0x3
#define RT5677_SPI_READ_32 0x2
#define RT5677_SPI_WRITE_16 0x1
#define RT5677_SPI_READ_16 0x0
#define RT5677_BUF_BYTES_TOTAL 0x20000
#define RT5677_MIC_BUF_ADDR 0x60030000
#define RT5677_MODEL_ADDR 0x5FFC9800
#define RT5677_MIC_BUF_BYTES ((u32)(RT5677_BUF_BYTES_TOTAL - \
sizeof(u32)))
#define RT5677_MIC_BUF_FIRST_READ_SIZE 0x10000
static struct spi_device *g_spi;
static DEFINE_MUTEX(spi_mutex);
struct rt5677_dsp {
struct device *dev;
struct delayed_work copy_work;
struct mutex dma_lock;
struct snd_pcm_substream *substream;
size_t dma_offset; /* zero-based offset into runtime->dma_area */
size_t avail_bytes; /* number of new bytes since last period */
u32 mic_read_offset; /* zero-based offset into DSP's mic buffer */
bool new_hotword; /* a new hotword is fired */
};
static const struct snd_pcm_hardware rt5677_spi_pcm_hardware = {
.info = SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_INTERLEAVED,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.period_bytes_min = PAGE_SIZE,
.period_bytes_max = RT5677_BUF_BYTES_TOTAL / 8,
.periods_min = 8,
.periods_max = 8,
.channels_min = 1,
.channels_max = 1,
.buffer_bytes_max = RT5677_BUF_BYTES_TOTAL,
};
static struct snd_soc_dai_driver rt5677_spi_dai = {
/* The DAI name "rt5677-dsp-cpu-dai" is not used. The actual DAI name
* registered with ASoC is the name of the device "spi-RT5677AA:00",
* because we only have one DAI. See snd_soc_register_dais().
*/
.name = "rt5677-dsp-cpu-dai",
.id = 0,
.capture = {
.stream_name = "DSP Capture",
.channels_min = 1,
.channels_max = 1,
.rates = SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
};
/* PCM for streaming audio from the DSP buffer */
static int rt5677_spi_pcm_open(
struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
snd_soc_set_runtime_hwparams(substream, &rt5677_spi_pcm_hardware);
return 0;
}
static int rt5677_spi_pcm_close(
struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_component *codec_component =
snd_soc_rtdcom_lookup(rtd, "rt5677");
struct rt5677_priv *rt5677 =
snd_soc_component_get_drvdata(codec_component);
struct rt5677_dsp *rt5677_dsp =
snd_soc_component_get_drvdata(component);
cancel_delayed_work_sync(&rt5677_dsp->copy_work);
rt5677->set_dsp_vad(codec_component, false);
return 0;
}
static int rt5677_spi_hw_params(
struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *hw_params)
{
struct rt5677_dsp *rt5677_dsp =
snd_soc_component_get_drvdata(component);
mutex_lock(&rt5677_dsp->dma_lock);
rt5677_dsp->substream = substream;
mutex_unlock(&rt5677_dsp->dma_lock);
return 0;
}
static int rt5677_spi_hw_free(
struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct rt5677_dsp *rt5677_dsp =
snd_soc_component_get_drvdata(component);
mutex_lock(&rt5677_dsp->dma_lock);
rt5677_dsp->substream = NULL;
mutex_unlock(&rt5677_dsp->dma_lock);
return 0;
}
static int rt5677_spi_prepare(
struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_component *rt5677_component =
snd_soc_rtdcom_lookup(rtd, "rt5677");
struct rt5677_priv *rt5677 =
snd_soc_component_get_drvdata(rt5677_component);
struct rt5677_dsp *rt5677_dsp =
snd_soc_component_get_drvdata(component);
rt5677->set_dsp_vad(rt5677_component, true);
rt5677_dsp->dma_offset = 0;
rt5677_dsp->avail_bytes = 0;
return 0;
}
static snd_pcm_uframes_t rt5677_spi_pcm_pointer(
struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct rt5677_dsp *rt5677_dsp =
snd_soc_component_get_drvdata(component);
return bytes_to_frames(runtime, rt5677_dsp->dma_offset);
}
static int rt5677_spi_mic_write_offset(u32 *mic_write_offset)
{
int ret;
/* Grab the first 4 bytes that hold the write pointer on the
* dsp, and check to make sure that it points somewhere inside the
* buffer.
*/
ret = rt5677_spi_read(RT5677_MIC_BUF_ADDR, mic_write_offset,
sizeof(u32));
if (ret)
return ret;
/* Adjust the offset so that it's zero-based */
*mic_write_offset = *mic_write_offset - sizeof(u32);
return *mic_write_offset < RT5677_MIC_BUF_BYTES ? 0 : -EFAULT;
}
/*
* Copy one contiguous block of audio samples from the DSP mic buffer to the
* dma_area of the pcm runtime. The receiving buffer may wrap around.
* @begin: start offset of the block to copy, in bytes.
* @end: offset of the first byte after the block to copy, must be greater
* than or equal to begin.
*
* Return: Zero if successful, or a negative error code on failure.
*/
static int rt5677_spi_copy_block(struct rt5677_dsp *rt5677_dsp,
u32 begin, u32 end)
{
struct snd_pcm_runtime *runtime = rt5677_dsp->substream->runtime;
size_t bytes_per_frame = frames_to_bytes(runtime, 1);
size_t first_chunk_len, second_chunk_len;
int ret;
if (begin > end || runtime->dma_bytes < 2 * bytes_per_frame) {
dev_err(rt5677_dsp->dev,
"Invalid copy from (%u, %u), dma_area size %zu\n",
begin, end, runtime->dma_bytes);
return -EINVAL;
}
/* The block to copy is empty */
if (begin == end)
return 0;
/* If the incoming chunk is too big for the receiving buffer, only the
* last "receiving buffer size - one frame" bytes are copied.
*/
if (end - begin > runtime->dma_bytes - bytes_per_frame)
begin = end - (runtime->dma_bytes - bytes_per_frame);
/* May need to split to two chunks, calculate the size of each */
first_chunk_len = end - begin;
second_chunk_len = 0;
if (rt5677_dsp->dma_offset + first_chunk_len > runtime->dma_bytes) {
/* Receiving buffer wrapped around */
second_chunk_len = first_chunk_len;
first_chunk_len = runtime->dma_bytes - rt5677_dsp->dma_offset;
second_chunk_len -= first_chunk_len;
}
/* Copy first chunk */
ret = rt5677_spi_read(RT5677_MIC_BUF_ADDR + sizeof(u32) + begin,
runtime->dma_area + rt5677_dsp->dma_offset,
first_chunk_len);
if (ret)
return ret;
rt5677_dsp->dma_offset += first_chunk_len;
if (rt5677_dsp->dma_offset == runtime->dma_bytes)
rt5677_dsp->dma_offset = 0;
/* Copy second chunk */
if (second_chunk_len) {
ret = rt5677_spi_read(RT5677_MIC_BUF_ADDR + sizeof(u32) +
begin + first_chunk_len, runtime->dma_area,
second_chunk_len);
if (!ret)
rt5677_dsp->dma_offset = second_chunk_len;
}
return ret;
}
/*
* Copy a given amount of audio samples from the DSP mic buffer starting at
* mic_read_offset, to the dma_area of the pcm runtime. The source buffer may
* wrap around. mic_read_offset is updated after successful copy.
* @amount: amount of samples to copy, in bytes.
*
* Return: Zero if successful, or a negative error code on failure.
*/
static int rt5677_spi_copy(struct rt5677_dsp *rt5677_dsp, u32 amount)
{
int ret = 0;
u32 target;
if (amount == 0)
return ret;
target = rt5677_dsp->mic_read_offset + amount;
/* Copy the first chunk in DSP's mic buffer */
ret |= rt5677_spi_copy_block(rt5677_dsp, rt5677_dsp->mic_read_offset,
min(target, RT5677_MIC_BUF_BYTES));
if (target >= RT5677_MIC_BUF_BYTES) {
/* Wrap around, copy the second chunk */
target -= RT5677_MIC_BUF_BYTES;
ret |= rt5677_spi_copy_block(rt5677_dsp, 0, target);
}
if (!ret)
rt5677_dsp->mic_read_offset = target;
return ret;
}
/*
* A delayed work that streams audio samples from the DSP mic buffer to the
* dma_area of the pcm runtime via SPI.
*/
static void rt5677_spi_copy_work(struct work_struct *work)
{
struct rt5677_dsp *rt5677_dsp =
container_of(work, struct rt5677_dsp, copy_work.work);
struct snd_pcm_runtime *runtime;
u32 mic_write_offset;
size_t new_bytes, copy_bytes, period_bytes;
unsigned int delay;
int ret = 0;
/* Ensure runtime->dma_area buffer does not go away while copying. */
mutex_lock(&rt5677_dsp->dma_lock);
if (!rt5677_dsp->substream) {
dev_err(rt5677_dsp->dev, "No pcm substream\n");
goto done;
}
runtime = rt5677_dsp->substream->runtime;
if (rt5677_spi_mic_write_offset(&mic_write_offset)) {
dev_err(rt5677_dsp->dev, "No mic_write_offset\n");
goto done;
}
/* If this is the first time that we've asked for streaming data after
* a hotword is fired, we should start reading from the previous 2
* seconds of audio from wherever the mic_write_offset is currently.
*/
if (rt5677_dsp->new_hotword) {
rt5677_dsp->new_hotword = false;
/* See if buffer wraparound happens */
if (mic_write_offset < RT5677_MIC_BUF_FIRST_READ_SIZE)
rt5677_dsp->mic_read_offset = RT5677_MIC_BUF_BYTES -
(RT5677_MIC_BUF_FIRST_READ_SIZE -
mic_write_offset);
else
rt5677_dsp->mic_read_offset = mic_write_offset -
RT5677_MIC_BUF_FIRST_READ_SIZE;
}
/* Calculate the amount of new samples in bytes */
if (rt5677_dsp->mic_read_offset <= mic_write_offset)
new_bytes = mic_write_offset - rt5677_dsp->mic_read_offset;
else
new_bytes = RT5677_MIC_BUF_BYTES + mic_write_offset
- rt5677_dsp->mic_read_offset;
/* Copy all new samples from DSP mic buffer, one period at a time */
period_bytes = snd_pcm_lib_period_bytes(rt5677_dsp->substream);
while (new_bytes) {
copy_bytes = min(new_bytes, period_bytes
- rt5677_dsp->avail_bytes);
ret = rt5677_spi_copy(rt5677_dsp, copy_bytes);
if (ret) {
dev_err(rt5677_dsp->dev, "Copy failed %d\n", ret);
goto done;
}
rt5677_dsp->avail_bytes += copy_bytes;
if (rt5677_dsp->avail_bytes >= period_bytes) {
snd_pcm_period_elapsed(rt5677_dsp->substream);
rt5677_dsp->avail_bytes = 0;
}
new_bytes -= copy_bytes;
}
delay = bytes_to_frames(runtime, period_bytes) / (runtime->rate / 1000);
schedule_delayed_work(&rt5677_dsp->copy_work, msecs_to_jiffies(delay));
done:
mutex_unlock(&rt5677_dsp->dma_lock);
}
static int rt5677_spi_pcm_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_VMALLOC,
NULL, 0, 0);
return 0;
}
static int rt5677_spi_pcm_probe(struct snd_soc_component *component)
{
struct rt5677_dsp *rt5677_dsp;
rt5677_dsp = devm_kzalloc(component->dev, sizeof(*rt5677_dsp),
GFP_KERNEL);
if (!rt5677_dsp)
return -ENOMEM;
rt5677_dsp->dev = &g_spi->dev;
mutex_init(&rt5677_dsp->dma_lock);
INIT_DELAYED_WORK(&rt5677_dsp->copy_work, rt5677_spi_copy_work);
snd_soc_component_set_drvdata(component, rt5677_dsp);
return 0;
}
static const struct snd_soc_component_driver rt5677_spi_dai_component = {
.name = DRV_NAME,
.probe = rt5677_spi_pcm_probe,
.open = rt5677_spi_pcm_open,
.close = rt5677_spi_pcm_close,
.hw_params = rt5677_spi_hw_params,
.hw_free = rt5677_spi_hw_free,
.prepare = rt5677_spi_prepare,
.pointer = rt5677_spi_pcm_pointer,
.pcm_construct = rt5677_spi_pcm_new,
.legacy_dai_naming = 1,
};
/* Select a suitable transfer command for the next transfer to ensure
* the transfer address is always naturally aligned while minimizing
* the total number of transfers required.
*
* 3 transfer commands are available:
* RT5677_SPI_READ/WRITE_16: Transfer 2 bytes
* RT5677_SPI_READ/WRITE_32: Transfer 4 bytes
* RT5677_SPI_READ/WRITE_BURST: Transfer any multiples of 8 bytes
*
* Note:
* 16 Bit writes and reads are restricted to the address range
* 0x18020000 ~ 0x18021000
*
* For example, reading 256 bytes at 0x60030004 uses the following commands:
* 0x60030004 RT5677_SPI_READ_32 4 bytes
* 0x60030008 RT5677_SPI_READ_BURST 240 bytes
* 0x600300F8 RT5677_SPI_READ_BURST 8 bytes
* 0x60030100 RT5677_SPI_READ_32 4 bytes
*
* Input:
* @read: true for read commands; false for write commands
* @align: alignment of the next transfer address
* @remain: number of bytes remaining to transfer
*
* Output:
* @len: number of bytes to transfer with the selected command
* Returns the selected command
*/
static u8 rt5677_spi_select_cmd(bool read, u32 align, u32 remain, u32 *len)
{
u8 cmd;
if (align == 4 || remain <= 4) {
cmd = RT5677_SPI_READ_32;
*len = 4;
} else {
cmd = RT5677_SPI_READ_BURST;
*len = (((remain - 1) >> 3) + 1) << 3;
*len = min_t(u32, *len, RT5677_SPI_BURST_LEN);
}
return read ? cmd : cmd + 1;
}
/* Copy dstlen bytes from src to dst, while reversing byte order for each word.
* If srclen < dstlen, zeros are padded.
*/
static void rt5677_spi_reverse(u8 *dst, u32 dstlen, const u8 *src, u32 srclen)
{
u32 w, i, si;
u32 word_size = min_t(u32, dstlen, 8);
for (w = 0; w < dstlen; w += word_size) {
for (i = 0; i < word_size && i + w < dstlen; i++) {
si = w + word_size - i - 1;
dst[w + i] = si < srclen ? src[si] : 0;
}
}
}
/* Read DSP address space using SPI. addr and len have to be 4-byte aligned. */
int rt5677_spi_read(u32 addr, void *rxbuf, size_t len)
{
u32 offset;
int status = 0;
struct spi_transfer t[2];
struct spi_message m;
/* +4 bytes is for the DummyPhase following the AddressPhase */
u8 header[RT5677_SPI_HEADER + 4];
u8 body[RT5677_SPI_BURST_LEN];
u8 spi_cmd;
u8 *cb = rxbuf;
if (!g_spi)
return -ENODEV;
if ((addr & 3) || (len & 3)) {
dev_err(&g_spi->dev, "Bad read align 0x%x(%zu)\n", addr, len);
return -EACCES;
}
memset(t, 0, sizeof(t));
t[0].tx_buf = header;
t[0].len = sizeof(header);
t[0].speed_hz = RT5677_SPI_FREQ;
t[1].rx_buf = body;
t[1].speed_hz = RT5677_SPI_FREQ;
spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t));
for (offset = 0; offset < len; offset += t[1].len) {
spi_cmd = rt5677_spi_select_cmd(true, (addr + offset) & 7,
len - offset, &t[1].len);
/* Construct SPI message header */
header[0] = spi_cmd;
header[1] = ((addr + offset) & 0xff000000) >> 24;
header[2] = ((addr + offset) & 0x00ff0000) >> 16;
header[3] = ((addr + offset) & 0x0000ff00) >> 8;
header[4] = ((addr + offset) & 0x000000ff) >> 0;
mutex_lock(&spi_mutex);
status |= spi_sync(g_spi, &m);
mutex_unlock(&spi_mutex);
/* Copy data back to caller buffer */
rt5677_spi_reverse(cb + offset, len - offset, body, t[1].len);
}
return status;
}
EXPORT_SYMBOL_GPL(rt5677_spi_read);
/* Write DSP address space using SPI. addr has to be 4-byte aligned.
* If len is not 4-byte aligned, then extra zeros are written at the end
* as padding.
*/
int rt5677_spi_write(u32 addr, const void *txbuf, size_t len)
{
u32 offset;
int status = 0;
struct spi_transfer t;
struct spi_message m;
/* +1 byte is for the DummyPhase following the DataPhase */
u8 buf[RT5677_SPI_HEADER + RT5677_SPI_BURST_LEN + 1];
u8 *body = buf + RT5677_SPI_HEADER;
u8 spi_cmd;
const u8 *cb = txbuf;
if (!g_spi)
return -ENODEV;
if (addr & 3) {
dev_err(&g_spi->dev, "Bad write align 0x%x(%zu)\n", addr, len);
return -EACCES;
}
memset(&t, 0, sizeof(t));
t.tx_buf = buf;
t.speed_hz = RT5677_SPI_FREQ;
spi_message_init_with_transfers(&m, &t, 1);
for (offset = 0; offset < len;) {
spi_cmd = rt5677_spi_select_cmd(false, (addr + offset) & 7,
len - offset, &t.len);
/* Construct SPI message header */
buf[0] = spi_cmd;
buf[1] = ((addr + offset) & 0xff000000) >> 24;
buf[2] = ((addr + offset) & 0x00ff0000) >> 16;
buf[3] = ((addr + offset) & 0x0000ff00) >> 8;
buf[4] = ((addr + offset) & 0x000000ff) >> 0;
/* Fetch data from caller buffer */
rt5677_spi_reverse(body, t.len, cb + offset, len - offset);
offset += t.len;
t.len += RT5677_SPI_HEADER + 1;
mutex_lock(&spi_mutex);
status |= spi_sync(g_spi, &m);
mutex_unlock(&spi_mutex);
}
return status;
}
EXPORT_SYMBOL_GPL(rt5677_spi_write);
int rt5677_spi_write_firmware(u32 addr, const struct firmware *fw)
{
return rt5677_spi_write(addr, fw->data, fw->size);
}
EXPORT_SYMBOL_GPL(rt5677_spi_write_firmware);
void rt5677_spi_hotword_detected(void)
{
struct rt5677_dsp *rt5677_dsp;
if (!g_spi)
return;
rt5677_dsp = dev_get_drvdata(&g_spi->dev);
if (!rt5677_dsp) {
dev_err(&g_spi->dev, "Can't get rt5677_dsp\n");
return;
}
mutex_lock(&rt5677_dsp->dma_lock);
dev_info(rt5677_dsp->dev, "Hotword detected\n");
rt5677_dsp->new_hotword = true;
mutex_unlock(&rt5677_dsp->dma_lock);
schedule_delayed_work(&rt5677_dsp->copy_work, 0);
}
EXPORT_SYMBOL_GPL(rt5677_spi_hotword_detected);
static int rt5677_spi_probe(struct spi_device *spi)
{
int ret;
g_spi = spi;
ret = devm_snd_soc_register_component(&spi->dev,
&rt5677_spi_dai_component,
&rt5677_spi_dai, 1);
if (ret < 0)
dev_err(&spi->dev, "Failed to register component.\n");
return ret;
}
#ifdef CONFIG_ACPI
static const struct acpi_device_id rt5677_spi_acpi_id[] = {
{ "RT5677AA", 0 },
{ }
};
MODULE_DEVICE_TABLE(acpi, rt5677_spi_acpi_id);
#endif
static struct spi_driver rt5677_spi_driver = {
.driver = {
.name = DRV_NAME,
.acpi_match_table = ACPI_PTR(rt5677_spi_acpi_id),
},
.probe = rt5677_spi_probe,
};
module_spi_driver(rt5677_spi_driver);
MODULE_DESCRIPTION("ASoC RT5677 SPI driver");
MODULE_AUTHOR("Oder Chiou <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/rt5677-spi.c |
// SPDX-License-Identifier: GPL-2.0
//
// rt711-sdw.c -- rt711 ALSA SoC audio driver
//
// Copyright(c) 2019 Realtek Semiconductor Corp.
//
//
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/mod_devicetable.h>
#include <linux/soundwire/sdw.h>
#include <linux/soundwire/sdw_type.h>
#include <linux/soundwire/sdw_registers.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include "rt711.h"
#include "rt711-sdw.h"
static bool rt711_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x00e0:
case 0x00f0:
case 0x2012 ... 0x2016:
case 0x201a ... 0x2027:
case 0x2029 ... 0x202a:
case 0x202d ... 0x2034:
case 0x2201 ... 0x2204:
case 0x2206 ... 0x2212:
case 0x2220 ... 0x2223:
case 0x2230 ... 0x2239:
case 0x2f01 ... 0x2f0f:
case 0x3000 ... 0x3fff:
case 0x7000 ... 0x7fff:
case 0x8300 ... 0x83ff:
case 0x9c00 ... 0x9cff:
case 0xb900 ... 0xb9ff:
case 0x752009:
case 0x752011:
case 0x75201a:
case 0x752045:
case 0x752046:
case 0x752048:
case 0x75204a:
case 0x75206b:
case 0x75206f:
case 0x752080:
case 0x752081:
case 0x752091:
case 0x755800:
return true;
default:
return false;
}
}
static bool rt711_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x2016:
case 0x201b:
case 0x201c:
case 0x201d:
case 0x201f:
case 0x2021:
case 0x2023:
case 0x2230:
case 0x2012 ... 0x2015: /* HD-A read */
case 0x202d ... 0x202f: /* BRA */
case 0x2201 ... 0x2212: /* i2c debug */
case 0x2220 ... 0x2223: /* decoded HD-A */
case 0x9c00 ... 0x9cff:
case 0xb900 ... 0xb9ff:
case 0xff01:
case 0x75201a:
case 0x752046:
case 0x752080:
case 0x752081:
case 0x755800:
return true;
default:
return false;
}
}
static int rt711_sdw_read(void *context, unsigned int reg, unsigned int *val)
{
struct device *dev = context;
struct rt711_priv *rt711 = dev_get_drvdata(dev);
unsigned int sdw_data_3, sdw_data_2, sdw_data_1, sdw_data_0;
unsigned int reg2 = 0, reg3 = 0, reg4 = 0, mask, nid, val2;
unsigned int is_hda_reg = 1, is_index_reg = 0;
int ret;
if (reg > 0xffff)
is_index_reg = 1;
mask = reg & 0xf000;
if (is_index_reg) { /* index registers */
val2 = reg & 0xff;
reg = reg >> 8;
nid = reg & 0xff;
ret = regmap_write(rt711->sdw_regmap, reg, 0);
if (ret < 0)
return ret;
reg2 = reg + 0x1000;
reg2 |= 0x80;
ret = regmap_write(rt711->sdw_regmap, reg2, val2);
if (ret < 0)
return ret;
reg3 = RT711_PRIV_DATA_R_H | nid;
ret = regmap_write(rt711->sdw_regmap,
reg3, ((*val >> 8) & 0xff));
if (ret < 0)
return ret;
reg4 = reg3 + 0x1000;
reg4 |= 0x80;
ret = regmap_write(rt711->sdw_regmap, reg4, (*val & 0xff));
if (ret < 0)
return ret;
} else if (mask == 0x3000) {
reg += 0x8000;
ret = regmap_write(rt711->sdw_regmap, reg, *val);
if (ret < 0)
return ret;
} else if (mask == 0x7000) {
reg += 0x2000;
reg |= 0x800;
ret = regmap_write(rt711->sdw_regmap,
reg, ((*val >> 8) & 0xff));
if (ret < 0)
return ret;
reg2 = reg + 0x1000;
reg2 |= 0x80;
ret = regmap_write(rt711->sdw_regmap, reg2, (*val & 0xff));
if (ret < 0)
return ret;
} else if ((reg & 0xff00) == 0x8300) { /* for R channel */
reg2 = reg - 0x1000;
reg2 &= ~0x80;
ret = regmap_write(rt711->sdw_regmap,
reg2, ((*val >> 8) & 0xff));
if (ret < 0)
return ret;
ret = regmap_write(rt711->sdw_regmap, reg, (*val & 0xff));
if (ret < 0)
return ret;
} else if (mask == 0x9000) {
ret = regmap_write(rt711->sdw_regmap,
reg, ((*val >> 8) & 0xff));
if (ret < 0)
return ret;
reg2 = reg + 0x1000;
reg2 |= 0x80;
ret = regmap_write(rt711->sdw_regmap, reg2, (*val & 0xff));
if (ret < 0)
return ret;
} else if (mask == 0xb000) {
ret = regmap_write(rt711->sdw_regmap, reg, *val);
if (ret < 0)
return ret;
} else {
ret = regmap_read(rt711->sdw_regmap, reg, val);
if (ret < 0)
return ret;
is_hda_reg = 0;
}
if (is_hda_reg || is_index_reg) {
sdw_data_3 = 0;
sdw_data_2 = 0;
sdw_data_1 = 0;
sdw_data_0 = 0;
ret = regmap_read(rt711->sdw_regmap,
RT711_READ_HDA_3, &sdw_data_3);
if (ret < 0)
return ret;
ret = regmap_read(rt711->sdw_regmap,
RT711_READ_HDA_2, &sdw_data_2);
if (ret < 0)
return ret;
ret = regmap_read(rt711->sdw_regmap,
RT711_READ_HDA_1, &sdw_data_1);
if (ret < 0)
return ret;
ret = regmap_read(rt711->sdw_regmap,
RT711_READ_HDA_0, &sdw_data_0);
if (ret < 0)
return ret;
*val = ((sdw_data_3 & 0xff) << 24) |
((sdw_data_2 & 0xff) << 16) |
((sdw_data_1 & 0xff) << 8) | (sdw_data_0 & 0xff);
}
if (is_hda_reg == 0)
dev_dbg(dev, "[%s] %04x => %08x\n", __func__, reg, *val);
else if (is_index_reg)
dev_dbg(dev, "[%s] %04x %04x %04x %04x => %08x\n",
__func__, reg, reg2, reg3, reg4, *val);
else
dev_dbg(dev, "[%s] %04x %04x => %08x\n",
__func__, reg, reg2, *val);
return 0;
}
static int rt711_sdw_write(void *context, unsigned int reg, unsigned int val)
{
struct device *dev = context;
struct rt711_priv *rt711 = dev_get_drvdata(dev);
unsigned int reg2 = 0, reg3, reg4, nid, mask, val2;
unsigned int is_index_reg = 0;
int ret;
if (reg > 0xffff)
is_index_reg = 1;
mask = reg & 0xf000;
if (is_index_reg) { /* index registers */
val2 = reg & 0xff;
reg = reg >> 8;
nid = reg & 0xff;
ret = regmap_write(rt711->sdw_regmap, reg, 0);
if (ret < 0)
return ret;
reg2 = reg + 0x1000;
reg2 |= 0x80;
ret = regmap_write(rt711->sdw_regmap, reg2, val2);
if (ret < 0)
return ret;
reg3 = RT711_PRIV_DATA_W_H | nid;
ret = regmap_write(rt711->sdw_regmap,
reg3, ((val >> 8) & 0xff));
if (ret < 0)
return ret;
reg4 = reg3 + 0x1000;
reg4 |= 0x80;
ret = regmap_write(rt711->sdw_regmap, reg4, (val & 0xff));
if (ret < 0)
return ret;
is_index_reg = 1;
} else if (reg < 0x4fff) {
ret = regmap_write(rt711->sdw_regmap, reg, val);
if (ret < 0)
return ret;
} else if (reg == RT711_FUNC_RESET) {
ret = regmap_write(rt711->sdw_regmap, reg, val);
if (ret < 0)
return ret;
} else if (mask == 0x7000) {
ret = regmap_write(rt711->sdw_regmap,
reg, ((val >> 8) & 0xff));
if (ret < 0)
return ret;
reg2 = reg + 0x1000;
reg2 |= 0x80;
ret = regmap_write(rt711->sdw_regmap, reg2, (val & 0xff));
if (ret < 0)
return ret;
} else if ((reg & 0xff00) == 0x8300) { /* for R channel */
reg2 = reg - 0x1000;
reg2 &= ~0x80;
ret = regmap_write(rt711->sdw_regmap,
reg2, ((val >> 8) & 0xff));
if (ret < 0)
return ret;
ret = regmap_write(rt711->sdw_regmap, reg, (val & 0xff));
if (ret < 0)
return ret;
}
if (reg2 == 0)
dev_dbg(dev, "[%s] %04x <= %04x\n", __func__, reg, val);
else if (is_index_reg)
dev_dbg(dev, "[%s] %04x %04x %04x %04x <= %04x %04x\n",
__func__, reg, reg2, reg3, reg4, val2, val);
else
dev_dbg(dev, "[%s] %04x %04x <= %04x\n",
__func__, reg, reg2, val);
return 0;
}
static const struct regmap_config rt711_regmap = {
.reg_bits = 24,
.val_bits = 32,
.readable_reg = rt711_readable_register,
.volatile_reg = rt711_volatile_register,
.max_register = 0x755800,
.reg_defaults = rt711_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(rt711_reg_defaults),
.cache_type = REGCACHE_MAPLE,
.use_single_read = true,
.use_single_write = true,
.reg_read = rt711_sdw_read,
.reg_write = rt711_sdw_write,
};
static const struct regmap_config rt711_sdw_regmap = {
.name = "sdw",
.reg_bits = 32,
.val_bits = 8,
.readable_reg = rt711_readable_register,
.max_register = 0xff01,
.cache_type = REGCACHE_NONE,
.use_single_read = true,
.use_single_write = true,
};
static int rt711_update_status(struct sdw_slave *slave,
enum sdw_slave_status status)
{
struct rt711_priv *rt711 = dev_get_drvdata(&slave->dev);
if (status == SDW_SLAVE_UNATTACHED)
rt711->hw_init = false;
/*
* Perform initialization only if slave status is present and
* hw_init flag is false
*/
if (rt711->hw_init || status != SDW_SLAVE_ATTACHED)
return 0;
/* perform I/O transfers required for Slave initialization */
return rt711_io_init(&slave->dev, slave);
}
static int rt711_read_prop(struct sdw_slave *slave)
{
struct sdw_slave_prop *prop = &slave->prop;
int nval;
int i, j;
u32 bit;
unsigned long addr;
struct sdw_dpn_prop *dpn;
prop->scp_int1_mask = SDW_SCP_INT1_IMPL_DEF | SDW_SCP_INT1_BUS_CLASH |
SDW_SCP_INT1_PARITY;
prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
prop->paging_support = false;
/* first we need to allocate memory for set bits in port lists */
prop->source_ports = 0x14; /* BITMAP: 00010100 */
prop->sink_ports = 0x8; /* BITMAP: 00001000 */
nval = hweight32(prop->source_ports);
prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
sizeof(*prop->src_dpn_prop),
GFP_KERNEL);
if (!prop->src_dpn_prop)
return -ENOMEM;
i = 0;
dpn = prop->src_dpn_prop;
addr = prop->source_ports;
for_each_set_bit(bit, &addr, 32) {
dpn[i].num = bit;
dpn[i].type = SDW_DPN_FULL;
dpn[i].simple_ch_prep_sm = true;
dpn[i].ch_prep_timeout = 10;
i++;
}
/* do this again for sink now */
nval = hweight32(prop->sink_ports);
prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
sizeof(*prop->sink_dpn_prop),
GFP_KERNEL);
if (!prop->sink_dpn_prop)
return -ENOMEM;
j = 0;
dpn = prop->sink_dpn_prop;
addr = prop->sink_ports;
for_each_set_bit(bit, &addr, 32) {
dpn[j].num = bit;
dpn[j].type = SDW_DPN_FULL;
dpn[j].simple_ch_prep_sm = true;
dpn[j].ch_prep_timeout = 10;
j++;
}
/* set the timeout values */
prop->clk_stop_timeout = 20;
/* wake-up event */
prop->wake_capable = 1;
return 0;
}
static int rt711_bus_config(struct sdw_slave *slave,
struct sdw_bus_params *params)
{
struct rt711_priv *rt711 = dev_get_drvdata(&slave->dev);
int ret;
memcpy(&rt711->params, params, sizeof(*params));
ret = rt711_clock_config(&slave->dev);
if (ret < 0)
dev_err(&slave->dev, "Invalid clk config");
return ret;
}
static int rt711_interrupt_callback(struct sdw_slave *slave,
struct sdw_slave_intr_status *status)
{
struct rt711_priv *rt711 = dev_get_drvdata(&slave->dev);
dev_dbg(&slave->dev,
"%s control_port_stat=%x", __func__, status->control_port);
mutex_lock(&rt711->disable_irq_lock);
if (status->control_port & 0x4 && !rt711->disable_irq) {
mod_delayed_work(system_power_efficient_wq,
&rt711->jack_detect_work, msecs_to_jiffies(250));
}
mutex_unlock(&rt711->disable_irq_lock);
return 0;
}
static const struct sdw_slave_ops rt711_slave_ops = {
.read_prop = rt711_read_prop,
.interrupt_callback = rt711_interrupt_callback,
.update_status = rt711_update_status,
.bus_config = rt711_bus_config,
};
static int rt711_sdw_probe(struct sdw_slave *slave,
const struct sdw_device_id *id)
{
struct regmap *sdw_regmap, *regmap;
/* Regmap Initialization */
sdw_regmap = devm_regmap_init_sdw(slave, &rt711_sdw_regmap);
if (IS_ERR(sdw_regmap))
return PTR_ERR(sdw_regmap);
regmap = devm_regmap_init(&slave->dev, NULL,
&slave->dev, &rt711_regmap);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return rt711_init(&slave->dev, sdw_regmap, regmap, slave);
}
static int rt711_sdw_remove(struct sdw_slave *slave)
{
struct rt711_priv *rt711 = dev_get_drvdata(&slave->dev);
if (rt711->hw_init) {
cancel_delayed_work_sync(&rt711->jack_detect_work);
cancel_delayed_work_sync(&rt711->jack_btn_check_work);
cancel_work_sync(&rt711->calibration_work);
}
pm_runtime_disable(&slave->dev);
mutex_destroy(&rt711->calibrate_mutex);
mutex_destroy(&rt711->disable_irq_lock);
return 0;
}
static const struct sdw_device_id rt711_id[] = {
SDW_SLAVE_ENTRY_EXT(0x025d, 0x711, 0x2, 0, 0),
{},
};
MODULE_DEVICE_TABLE(sdw, rt711_id);
static int __maybe_unused rt711_dev_suspend(struct device *dev)
{
struct rt711_priv *rt711 = dev_get_drvdata(dev);
if (!rt711->hw_init)
return 0;
cancel_delayed_work_sync(&rt711->jack_detect_work);
cancel_delayed_work_sync(&rt711->jack_btn_check_work);
cancel_work_sync(&rt711->calibration_work);
regcache_cache_only(rt711->regmap, true);
return 0;
}
static int __maybe_unused rt711_dev_system_suspend(struct device *dev)
{
struct rt711_priv *rt711 = dev_get_drvdata(dev);
struct sdw_slave *slave = dev_to_sdw_dev(dev);
int ret;
if (!rt711->hw_init)
return 0;
/*
* prevent new interrupts from being handled after the
* deferred work completes and before the parent disables
* interrupts on the link
*/
mutex_lock(&rt711->disable_irq_lock);
rt711->disable_irq = true;
ret = sdw_update_no_pm(slave, SDW_SCP_INTMASK1,
SDW_SCP_INT1_IMPL_DEF, 0);
mutex_unlock(&rt711->disable_irq_lock);
if (ret < 0) {
/* log but don't prevent suspend from happening */
dev_dbg(&slave->dev, "%s: could not disable imp-def interrupts\n:", __func__);
}
return rt711_dev_suspend(dev);
}
#define RT711_PROBE_TIMEOUT 5000
static int __maybe_unused rt711_dev_resume(struct device *dev)
{
struct sdw_slave *slave = dev_to_sdw_dev(dev);
struct rt711_priv *rt711 = dev_get_drvdata(dev);
unsigned long time;
if (!rt711->first_hw_init)
return 0;
if (!slave->unattach_request) {
if (rt711->disable_irq == true) {
mutex_lock(&rt711->disable_irq_lock);
sdw_write_no_pm(slave, SDW_SCP_INTMASK1, SDW_SCP_INT1_IMPL_DEF);
rt711->disable_irq = false;
mutex_unlock(&rt711->disable_irq_lock);
}
goto regmap_sync;
}
time = wait_for_completion_timeout(&slave->initialization_complete,
msecs_to_jiffies(RT711_PROBE_TIMEOUT));
if (!time) {
dev_err(&slave->dev, "Initialization not complete, timed out\n");
return -ETIMEDOUT;
}
regmap_sync:
slave->unattach_request = 0;
regcache_cache_only(rt711->regmap, false);
regcache_sync_region(rt711->regmap, 0x3000, 0x8fff);
regcache_sync_region(rt711->regmap, 0x752009, 0x752091);
return 0;
}
static const struct dev_pm_ops rt711_pm = {
SET_SYSTEM_SLEEP_PM_OPS(rt711_dev_system_suspend, rt711_dev_resume)
SET_RUNTIME_PM_OPS(rt711_dev_suspend, rt711_dev_resume, NULL)
};
static struct sdw_driver rt711_sdw_driver = {
.driver = {
.name = "rt711",
.owner = THIS_MODULE,
.pm = &rt711_pm,
},
.probe = rt711_sdw_probe,
.remove = rt711_sdw_remove,
.ops = &rt711_slave_ops,
.id_table = rt711_id,
};
module_sdw_driver(rt711_sdw_driver);
MODULE_DESCRIPTION("ASoC RT711 SDW driver");
MODULE_AUTHOR("Shuming Fan <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/rt711-sdw.c |
// SPDX-License-Identifier: GPL-2.0
// tscs42xx.c -- TSCS42xx ALSA SoC Audio driver
// Copyright 2017 Tempo Semiconductor, Inc.
// Author: Steven Eckhoff <[email protected]>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/regmap.h>
#include <linux/i2c.h>
#include <linux/err.h>
#include <linux/string.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/mutex.h>
#include <linux/clk.h>
#include <sound/tlv.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include "tscs42xx.h"
#define COEFF_SIZE 3
#define BIQUAD_COEFF_COUNT 5
#define BIQUAD_SIZE (COEFF_SIZE * BIQUAD_COEFF_COUNT)
#define COEFF_RAM_MAX_ADDR 0xcd
#define COEFF_RAM_COEFF_COUNT (COEFF_RAM_MAX_ADDR + 1)
#define COEFF_RAM_SIZE (COEFF_SIZE * COEFF_RAM_COEFF_COUNT)
struct tscs42xx {
int bclk_ratio;
int samplerate;
struct mutex audio_params_lock;
u8 coeff_ram[COEFF_RAM_SIZE];
bool coeff_ram_synced;
struct mutex coeff_ram_lock;
struct mutex pll_lock;
struct regmap *regmap;
struct clk *sysclk;
int sysclk_src_id;
};
struct coeff_ram_ctl {
unsigned int addr;
struct soc_bytes_ext bytes_ext;
};
static bool tscs42xx_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case R_DACCRWRL:
case R_DACCRWRM:
case R_DACCRWRH:
case R_DACCRRDL:
case R_DACCRRDM:
case R_DACCRRDH:
case R_DACCRSTAT:
case R_DACCRADDR:
case R_PLLCTL0:
return true;
default:
return false;
}
}
static bool tscs42xx_precious(struct device *dev, unsigned int reg)
{
switch (reg) {
case R_DACCRWRL:
case R_DACCRWRM:
case R_DACCRWRH:
case R_DACCRRDL:
case R_DACCRRDM:
case R_DACCRRDH:
return true;
default:
return false;
}
}
static const struct regmap_config tscs42xx_regmap = {
.reg_bits = 8,
.val_bits = 8,
.volatile_reg = tscs42xx_volatile,
.precious_reg = tscs42xx_precious,
.max_register = R_DACMBCREL3H,
.cache_type = REGCACHE_RBTREE,
.can_multi_write = true,
};
#define MAX_PLL_LOCK_20MS_WAITS 1
static bool plls_locked(struct snd_soc_component *component)
{
int ret;
int count = MAX_PLL_LOCK_20MS_WAITS;
do {
ret = snd_soc_component_read(component, R_PLLCTL0);
if (ret < 0) {
dev_err(component->dev,
"Failed to read PLL lock status (%d)\n", ret);
return false;
} else if (ret > 0) {
return true;
}
msleep(20);
} while (count--);
return false;
}
static int sample_rate_to_pll_freq_out(int sample_rate)
{
switch (sample_rate) {
case 11025:
case 22050:
case 44100:
case 88200:
return 112896000;
case 8000:
case 16000:
case 32000:
case 48000:
case 96000:
return 122880000;
default:
return -EINVAL;
}
}
#define DACCRSTAT_MAX_TRYS 10
static int write_coeff_ram(struct snd_soc_component *component, u8 *coeff_ram,
unsigned int addr, unsigned int coeff_cnt)
{
struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component);
int cnt;
int trys;
int ret;
for (cnt = 0; cnt < coeff_cnt; cnt++, addr++) {
for (trys = 0; trys < DACCRSTAT_MAX_TRYS; trys++) {
ret = snd_soc_component_read(component, R_DACCRSTAT);
if (ret < 0) {
dev_err(component->dev,
"Failed to read stat (%d)\n", ret);
return ret;
}
if (!ret)
break;
}
if (trys == DACCRSTAT_MAX_TRYS) {
ret = -EIO;
dev_err(component->dev,
"dac coefficient write error (%d)\n", ret);
return ret;
}
ret = regmap_write(tscs42xx->regmap, R_DACCRADDR, addr);
if (ret < 0) {
dev_err(component->dev,
"Failed to write dac ram address (%d)\n", ret);
return ret;
}
ret = regmap_bulk_write(tscs42xx->regmap, R_DACCRWRL,
&coeff_ram[addr * COEFF_SIZE],
COEFF_SIZE);
if (ret < 0) {
dev_err(component->dev,
"Failed to write dac ram (%d)\n", ret);
return ret;
}
}
return 0;
}
static int power_up_audio_plls(struct snd_soc_component *component)
{
struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component);
int freq_out;
int ret;
unsigned int mask;
unsigned int val;
freq_out = sample_rate_to_pll_freq_out(tscs42xx->samplerate);
switch (freq_out) {
case 122880000: /* 48k */
mask = RM_PLLCTL1C_PDB_PLL1;
val = RV_PLLCTL1C_PDB_PLL1_ENABLE;
break;
case 112896000: /* 44.1k */
mask = RM_PLLCTL1C_PDB_PLL2;
val = RV_PLLCTL1C_PDB_PLL2_ENABLE;
break;
default:
ret = -EINVAL;
dev_err(component->dev,
"Unrecognized PLL output freq (%d)\n", ret);
return ret;
}
mutex_lock(&tscs42xx->pll_lock);
ret = snd_soc_component_update_bits(component, R_PLLCTL1C, mask, val);
if (ret < 0) {
dev_err(component->dev, "Failed to turn PLL on (%d)\n", ret);
goto exit;
}
if (!plls_locked(component)) {
dev_err(component->dev, "Failed to lock plls\n");
ret = -ENOMSG;
goto exit;
}
ret = 0;
exit:
mutex_unlock(&tscs42xx->pll_lock);
return ret;
}
static int power_down_audio_plls(struct snd_soc_component *component)
{
struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component);
int ret;
mutex_lock(&tscs42xx->pll_lock);
ret = snd_soc_component_update_bits(component, R_PLLCTL1C,
RM_PLLCTL1C_PDB_PLL1,
RV_PLLCTL1C_PDB_PLL1_DISABLE);
if (ret < 0) {
dev_err(component->dev, "Failed to turn PLL off (%d)\n", ret);
goto exit;
}
ret = snd_soc_component_update_bits(component, R_PLLCTL1C,
RM_PLLCTL1C_PDB_PLL2,
RV_PLLCTL1C_PDB_PLL2_DISABLE);
if (ret < 0) {
dev_err(component->dev, "Failed to turn PLL off (%d)\n", ret);
goto exit;
}
ret = 0;
exit:
mutex_unlock(&tscs42xx->pll_lock);
return ret;
}
static int coeff_ram_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component);
struct coeff_ram_ctl *ctl =
(struct coeff_ram_ctl *)kcontrol->private_value;
struct soc_bytes_ext *params = &ctl->bytes_ext;
mutex_lock(&tscs42xx->coeff_ram_lock);
memcpy(ucontrol->value.bytes.data,
&tscs42xx->coeff_ram[ctl->addr * COEFF_SIZE], params->max);
mutex_unlock(&tscs42xx->coeff_ram_lock);
return 0;
}
static int coeff_ram_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component);
struct coeff_ram_ctl *ctl =
(struct coeff_ram_ctl *)kcontrol->private_value;
struct soc_bytes_ext *params = &ctl->bytes_ext;
unsigned int coeff_cnt = params->max / COEFF_SIZE;
int ret;
mutex_lock(&tscs42xx->coeff_ram_lock);
tscs42xx->coeff_ram_synced = false;
memcpy(&tscs42xx->coeff_ram[ctl->addr * COEFF_SIZE],
ucontrol->value.bytes.data, params->max);
mutex_lock(&tscs42xx->pll_lock);
if (plls_locked(component)) {
ret = write_coeff_ram(component, tscs42xx->coeff_ram,
ctl->addr, coeff_cnt);
if (ret < 0) {
dev_err(component->dev,
"Failed to flush coeff ram cache (%d)\n", ret);
goto exit;
}
tscs42xx->coeff_ram_synced = true;
}
ret = 0;
exit:
mutex_unlock(&tscs42xx->pll_lock);
mutex_unlock(&tscs42xx->coeff_ram_lock);
return ret;
}
/* Input L Capture Route */
static char const * const input_select_text[] = {
"Line 1", "Line 2", "Line 3", "D2S"
};
static const struct soc_enum left_input_select_enum =
SOC_ENUM_SINGLE(R_INSELL, FB_INSELL, ARRAY_SIZE(input_select_text),
input_select_text);
static const struct snd_kcontrol_new left_input_select =
SOC_DAPM_ENUM("LEFT_INPUT_SELECT_ENUM", left_input_select_enum);
/* Input R Capture Route */
static const struct soc_enum right_input_select_enum =
SOC_ENUM_SINGLE(R_INSELR, FB_INSELR, ARRAY_SIZE(input_select_text),
input_select_text);
static const struct snd_kcontrol_new right_input_select =
SOC_DAPM_ENUM("RIGHT_INPUT_SELECT_ENUM", right_input_select_enum);
/* Input Channel Mapping */
static char const * const ch_map_select_text[] = {
"Normal", "Left to Right", "Right to Left", "Swap"
};
static const struct soc_enum ch_map_select_enum =
SOC_ENUM_SINGLE(R_AIC2, FB_AIC2_ADCDSEL, ARRAY_SIZE(ch_map_select_text),
ch_map_select_text);
static int dapm_vref_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
msleep(20);
return 0;
}
static int dapm_micb_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
msleep(20);
return 0;
}
static int pll_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
int ret;
if (SND_SOC_DAPM_EVENT_ON(event))
ret = power_up_audio_plls(component);
else
ret = power_down_audio_plls(component);
return ret;
}
static int dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component);
int ret;
mutex_lock(&tscs42xx->coeff_ram_lock);
if (!tscs42xx->coeff_ram_synced) {
ret = write_coeff_ram(component, tscs42xx->coeff_ram, 0x00,
COEFF_RAM_COEFF_COUNT);
if (ret < 0)
goto exit;
tscs42xx->coeff_ram_synced = true;
}
ret = 0;
exit:
mutex_unlock(&tscs42xx->coeff_ram_lock);
return ret;
}
static const struct snd_soc_dapm_widget tscs42xx_dapm_widgets[] = {
/* Vref */
SND_SOC_DAPM_SUPPLY_S("Vref", 1, R_PWRM2, FB_PWRM2_VREF, 0,
dapm_vref_event, SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD),
/* PLL */
SND_SOC_DAPM_SUPPLY("PLL", SND_SOC_NOPM, 0, 0, pll_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
/* Headphone */
SND_SOC_DAPM_DAC_E("DAC L", "HiFi Playback", R_PWRM2, FB_PWRM2_HPL, 0,
dac_event, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_DAC_E("DAC R", "HiFi Playback", R_PWRM2, FB_PWRM2_HPR, 0,
dac_event, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_OUTPUT("Headphone L"),
SND_SOC_DAPM_OUTPUT("Headphone R"),
/* Speaker */
SND_SOC_DAPM_DAC_E("ClassD L", "HiFi Playback",
R_PWRM2, FB_PWRM2_SPKL, 0,
dac_event, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_DAC_E("ClassD R", "HiFi Playback",
R_PWRM2, FB_PWRM2_SPKR, 0,
dac_event, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_OUTPUT("Speaker L"),
SND_SOC_DAPM_OUTPUT("Speaker R"),
/* Capture */
SND_SOC_DAPM_PGA("Analog In PGA L", R_PWRM1, FB_PWRM1_PGAL, 0, NULL, 0),
SND_SOC_DAPM_PGA("Analog In PGA R", R_PWRM1, FB_PWRM1_PGAR, 0, NULL, 0),
SND_SOC_DAPM_PGA("Analog Boost L", R_PWRM1, FB_PWRM1_BSTL, 0, NULL, 0),
SND_SOC_DAPM_PGA("Analog Boost R", R_PWRM1, FB_PWRM1_BSTR, 0, NULL, 0),
SND_SOC_DAPM_PGA("ADC Mute", R_CNVRTR0, FB_CNVRTR0_HPOR, true, NULL, 0),
SND_SOC_DAPM_ADC("ADC L", "HiFi Capture", R_PWRM1, FB_PWRM1_ADCL, 0),
SND_SOC_DAPM_ADC("ADC R", "HiFi Capture", R_PWRM1, FB_PWRM1_ADCR, 0),
/* Capture Input */
SND_SOC_DAPM_MUX("Input L Capture Route", R_PWRM2,
FB_PWRM2_INSELL, 0, &left_input_select),
SND_SOC_DAPM_MUX("Input R Capture Route", R_PWRM2,
FB_PWRM2_INSELR, 0, &right_input_select),
/* Digital Mic */
SND_SOC_DAPM_SUPPLY_S("Digital Mic Enable", 2, R_DMICCTL,
FB_DMICCTL_DMICEN, 0, NULL,
SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD),
/* Analog Mic */
SND_SOC_DAPM_SUPPLY_S("Mic Bias", 2, R_PWRM1, FB_PWRM1_MICB,
0, dapm_micb_event, SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD),
/* Line In */
SND_SOC_DAPM_INPUT("Line In 1 L"),
SND_SOC_DAPM_INPUT("Line In 1 R"),
SND_SOC_DAPM_INPUT("Line In 2 L"),
SND_SOC_DAPM_INPUT("Line In 2 R"),
SND_SOC_DAPM_INPUT("Line In 3 L"),
SND_SOC_DAPM_INPUT("Line In 3 R"),
};
static const struct snd_soc_dapm_route tscs42xx_intercon[] = {
{"DAC L", NULL, "PLL"},
{"DAC R", NULL, "PLL"},
{"DAC L", NULL, "Vref"},
{"DAC R", NULL, "Vref"},
{"Headphone L", NULL, "DAC L"},
{"Headphone R", NULL, "DAC R"},
{"ClassD L", NULL, "PLL"},
{"ClassD R", NULL, "PLL"},
{"ClassD L", NULL, "Vref"},
{"ClassD R", NULL, "Vref"},
{"Speaker L", NULL, "ClassD L"},
{"Speaker R", NULL, "ClassD R"},
{"Input L Capture Route", NULL, "Vref"},
{"Input R Capture Route", NULL, "Vref"},
{"Mic Bias", NULL, "Vref"},
{"Input L Capture Route", "Line 1", "Line In 1 L"},
{"Input R Capture Route", "Line 1", "Line In 1 R"},
{"Input L Capture Route", "Line 2", "Line In 2 L"},
{"Input R Capture Route", "Line 2", "Line In 2 R"},
{"Input L Capture Route", "Line 3", "Line In 3 L"},
{"Input R Capture Route", "Line 3", "Line In 3 R"},
{"Analog In PGA L", NULL, "Input L Capture Route"},
{"Analog In PGA R", NULL, "Input R Capture Route"},
{"Analog Boost L", NULL, "Analog In PGA L"},
{"Analog Boost R", NULL, "Analog In PGA R"},
{"ADC Mute", NULL, "Analog Boost L"},
{"ADC Mute", NULL, "Analog Boost R"},
{"ADC L", NULL, "PLL"},
{"ADC R", NULL, "PLL"},
{"ADC L", NULL, "ADC Mute"},
{"ADC R", NULL, "ADC Mute"},
};
/************
* CONTROLS *
************/
static char const * const eq_band_enable_text[] = {
"Prescale only",
"Band1",
"Band1:2",
"Band1:3",
"Band1:4",
"Band1:5",
"Band1:6",
};
static char const * const level_detection_text[] = {
"Average",
"Peak",
};
static char const * const level_detection_window_text[] = {
"512 Samples",
"64 Samples",
};
static char const * const compressor_ratio_text[] = {
"Reserved", "1.5:1", "2:1", "3:1", "4:1", "5:1", "6:1",
"7:1", "8:1", "9:1", "10:1", "11:1", "12:1", "13:1", "14:1",
"15:1", "16:1", "17:1", "18:1", "19:1", "20:1",
};
static DECLARE_TLV_DB_SCALE(hpvol_scale, -8850, 75, 0);
static DECLARE_TLV_DB_SCALE(spkvol_scale, -7725, 75, 0);
static DECLARE_TLV_DB_SCALE(dacvol_scale, -9563, 38, 0);
static DECLARE_TLV_DB_SCALE(adcvol_scale, -7125, 38, 0);
static DECLARE_TLV_DB_SCALE(invol_scale, -1725, 75, 0);
static DECLARE_TLV_DB_SCALE(mic_boost_scale, 0, 1000, 0);
static DECLARE_TLV_DB_MINMAX(mugain_scale, 0, 4650);
static DECLARE_TLV_DB_MINMAX(compth_scale, -9562, 0);
static const struct soc_enum eq1_band_enable_enum =
SOC_ENUM_SINGLE(R_CONFIG1, FB_CONFIG1_EQ1_BE,
ARRAY_SIZE(eq_band_enable_text), eq_band_enable_text);
static const struct soc_enum eq2_band_enable_enum =
SOC_ENUM_SINGLE(R_CONFIG1, FB_CONFIG1_EQ2_BE,
ARRAY_SIZE(eq_band_enable_text), eq_band_enable_text);
static const struct soc_enum cle_level_detection_enum =
SOC_ENUM_SINGLE(R_CLECTL, FB_CLECTL_LVL_MODE,
ARRAY_SIZE(level_detection_text),
level_detection_text);
static const struct soc_enum cle_level_detection_window_enum =
SOC_ENUM_SINGLE(R_CLECTL, FB_CLECTL_WINDOWSEL,
ARRAY_SIZE(level_detection_window_text),
level_detection_window_text);
static const struct soc_enum mbc_level_detection_enums[] = {
SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE1,
ARRAY_SIZE(level_detection_text),
level_detection_text),
SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE2,
ARRAY_SIZE(level_detection_text),
level_detection_text),
SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE3,
ARRAY_SIZE(level_detection_text),
level_detection_text),
};
static const struct soc_enum mbc_level_detection_window_enums[] = {
SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL1,
ARRAY_SIZE(level_detection_window_text),
level_detection_window_text),
SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL2,
ARRAY_SIZE(level_detection_window_text),
level_detection_window_text),
SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL3,
ARRAY_SIZE(level_detection_window_text),
level_detection_window_text),
};
static const struct soc_enum compressor_ratio_enum =
SOC_ENUM_SINGLE(R_CMPRAT, FB_CMPRAT,
ARRAY_SIZE(compressor_ratio_text), compressor_ratio_text);
static const struct soc_enum dac_mbc1_compressor_ratio_enum =
SOC_ENUM_SINGLE(R_DACMBCRAT1, FB_DACMBCRAT1_RATIO,
ARRAY_SIZE(compressor_ratio_text), compressor_ratio_text);
static const struct soc_enum dac_mbc2_compressor_ratio_enum =
SOC_ENUM_SINGLE(R_DACMBCRAT2, FB_DACMBCRAT2_RATIO,
ARRAY_SIZE(compressor_ratio_text), compressor_ratio_text);
static const struct soc_enum dac_mbc3_compressor_ratio_enum =
SOC_ENUM_SINGLE(R_DACMBCRAT3, FB_DACMBCRAT3_RATIO,
ARRAY_SIZE(compressor_ratio_text), compressor_ratio_text);
static int bytes_info_ext(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *ucontrol)
{
struct coeff_ram_ctl *ctl =
(struct coeff_ram_ctl *)kcontrol->private_value;
struct soc_bytes_ext *params = &ctl->bytes_ext;
ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
ucontrol->count = params->max;
return 0;
}
#define COEFF_RAM_CTL(xname, xcount, xaddr) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
.info = bytes_info_ext, \
.get = coeff_ram_get, .put = coeff_ram_put, \
.private_value = (unsigned long)&(struct coeff_ram_ctl) { \
.addr = xaddr, \
.bytes_ext = {.max = xcount, }, \
} \
}
static const struct snd_kcontrol_new tscs42xx_snd_controls[] = {
/* Volumes */
SOC_DOUBLE_R_TLV("Headphone Volume", R_HPVOLL, R_HPVOLR,
FB_HPVOLL, 0x7F, 0, hpvol_scale),
SOC_DOUBLE_R_TLV("Speaker Volume", R_SPKVOLL, R_SPKVOLR,
FB_SPKVOLL, 0x7F, 0, spkvol_scale),
SOC_DOUBLE_R_TLV("Master Volume", R_DACVOLL, R_DACVOLR,
FB_DACVOLL, 0xFF, 0, dacvol_scale),
SOC_DOUBLE_R_TLV("PCM Volume", R_ADCVOLL, R_ADCVOLR,
FB_ADCVOLL, 0xFF, 0, adcvol_scale),
SOC_DOUBLE_R_TLV("Input Volume", R_INVOLL, R_INVOLR,
FB_INVOLL, 0x3F, 0, invol_scale),
/* INSEL */
SOC_DOUBLE_R_TLV("Mic Boost Volume", R_INSELL, R_INSELR,
FB_INSELL_MICBSTL, FV_INSELL_MICBSTL_30DB,
0, mic_boost_scale),
/* Input Channel Map */
SOC_ENUM("Input Channel Map", ch_map_select_enum),
/* Mic Bias */
SOC_SINGLE("Mic Bias Boost Switch", 0x71, 0x07, 1, 0),
/* Headphone Auto Switching */
SOC_SINGLE("Headphone Auto Switching Switch",
R_CTL, FB_CTL_HPSWEN, 1, 0),
SOC_SINGLE("Headphone Detect Polarity Toggle Switch",
R_CTL, FB_CTL_HPSWPOL, 1, 0),
/* Coefficient Ram */
COEFF_RAM_CTL("Cascade1L BiQuad1", BIQUAD_SIZE, 0x00),
COEFF_RAM_CTL("Cascade1L BiQuad2", BIQUAD_SIZE, 0x05),
COEFF_RAM_CTL("Cascade1L BiQuad3", BIQUAD_SIZE, 0x0a),
COEFF_RAM_CTL("Cascade1L BiQuad4", BIQUAD_SIZE, 0x0f),
COEFF_RAM_CTL("Cascade1L BiQuad5", BIQUAD_SIZE, 0x14),
COEFF_RAM_CTL("Cascade1L BiQuad6", BIQUAD_SIZE, 0x19),
COEFF_RAM_CTL("Cascade1R BiQuad1", BIQUAD_SIZE, 0x20),
COEFF_RAM_CTL("Cascade1R BiQuad2", BIQUAD_SIZE, 0x25),
COEFF_RAM_CTL("Cascade1R BiQuad3", BIQUAD_SIZE, 0x2a),
COEFF_RAM_CTL("Cascade1R BiQuad4", BIQUAD_SIZE, 0x2f),
COEFF_RAM_CTL("Cascade1R BiQuad5", BIQUAD_SIZE, 0x34),
COEFF_RAM_CTL("Cascade1R BiQuad6", BIQUAD_SIZE, 0x39),
COEFF_RAM_CTL("Cascade1L Prescale", COEFF_SIZE, 0x1f),
COEFF_RAM_CTL("Cascade1R Prescale", COEFF_SIZE, 0x3f),
COEFF_RAM_CTL("Cascade2L BiQuad1", BIQUAD_SIZE, 0x40),
COEFF_RAM_CTL("Cascade2L BiQuad2", BIQUAD_SIZE, 0x45),
COEFF_RAM_CTL("Cascade2L BiQuad3", BIQUAD_SIZE, 0x4a),
COEFF_RAM_CTL("Cascade2L BiQuad4", BIQUAD_SIZE, 0x4f),
COEFF_RAM_CTL("Cascade2L BiQuad5", BIQUAD_SIZE, 0x54),
COEFF_RAM_CTL("Cascade2L BiQuad6", BIQUAD_SIZE, 0x59),
COEFF_RAM_CTL("Cascade2R BiQuad1", BIQUAD_SIZE, 0x60),
COEFF_RAM_CTL("Cascade2R BiQuad2", BIQUAD_SIZE, 0x65),
COEFF_RAM_CTL("Cascade2R BiQuad3", BIQUAD_SIZE, 0x6a),
COEFF_RAM_CTL("Cascade2R BiQuad4", BIQUAD_SIZE, 0x6f),
COEFF_RAM_CTL("Cascade2R BiQuad5", BIQUAD_SIZE, 0x74),
COEFF_RAM_CTL("Cascade2R BiQuad6", BIQUAD_SIZE, 0x79),
COEFF_RAM_CTL("Cascade2L Prescale", COEFF_SIZE, 0x5f),
COEFF_RAM_CTL("Cascade2R Prescale", COEFF_SIZE, 0x7f),
COEFF_RAM_CTL("Bass Extraction BiQuad1", BIQUAD_SIZE, 0x80),
COEFF_RAM_CTL("Bass Extraction BiQuad2", BIQUAD_SIZE, 0x85),
COEFF_RAM_CTL("Bass Non Linear Function 1", COEFF_SIZE, 0x8a),
COEFF_RAM_CTL("Bass Non Linear Function 2", COEFF_SIZE, 0x8b),
COEFF_RAM_CTL("Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c),
COEFF_RAM_CTL("Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91),
COEFF_RAM_CTL("Bass Mix", COEFF_SIZE, 0x96),
COEFF_RAM_CTL("Treb Extraction BiQuad1", BIQUAD_SIZE, 0x97),
COEFF_RAM_CTL("Treb Extraction BiQuad2", BIQUAD_SIZE, 0x9c),
COEFF_RAM_CTL("Treb Non Linear Function 1", COEFF_SIZE, 0xa1),
COEFF_RAM_CTL("Treb Non Linear Function 2", COEFF_SIZE, 0xa2),
COEFF_RAM_CTL("Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3),
COEFF_RAM_CTL("Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8),
COEFF_RAM_CTL("Treb Mix", COEFF_SIZE, 0xad),
COEFF_RAM_CTL("3D", COEFF_SIZE, 0xae),
COEFF_RAM_CTL("3D Mix", COEFF_SIZE, 0xaf),
COEFF_RAM_CTL("MBC1 BiQuad1", BIQUAD_SIZE, 0xb0),
COEFF_RAM_CTL("MBC1 BiQuad2", BIQUAD_SIZE, 0xb5),
COEFF_RAM_CTL("MBC2 BiQuad1", BIQUAD_SIZE, 0xba),
COEFF_RAM_CTL("MBC2 BiQuad2", BIQUAD_SIZE, 0xbf),
COEFF_RAM_CTL("MBC3 BiQuad1", BIQUAD_SIZE, 0xc4),
COEFF_RAM_CTL("MBC3 BiQuad2", BIQUAD_SIZE, 0xc9),
/* EQ */
SOC_SINGLE("EQ1 Switch", R_CONFIG1, FB_CONFIG1_EQ1_EN, 1, 0),
SOC_SINGLE("EQ2 Switch", R_CONFIG1, FB_CONFIG1_EQ2_EN, 1, 0),
SOC_ENUM("EQ1 Band Enable", eq1_band_enable_enum),
SOC_ENUM("EQ2 Band Enable", eq2_band_enable_enum),
/* CLE */
SOC_ENUM("CLE Level Detect",
cle_level_detection_enum),
SOC_ENUM("CLE Level Detect Win",
cle_level_detection_window_enum),
SOC_SINGLE("Expander Switch",
R_CLECTL, FB_CLECTL_EXP_EN, 1, 0),
SOC_SINGLE("Limiter Switch",
R_CLECTL, FB_CLECTL_LIMIT_EN, 1, 0),
SOC_SINGLE("Comp Switch",
R_CLECTL, FB_CLECTL_COMP_EN, 1, 0),
SOC_SINGLE_TLV("CLE Make-Up Gain Volume",
R_MUGAIN, FB_MUGAIN_CLEMUG, 0x1f, 0, mugain_scale),
SOC_SINGLE_TLV("Comp Thresh Volume",
R_COMPTH, FB_COMPTH, 0xff, 0, compth_scale),
SOC_ENUM("Comp Ratio", compressor_ratio_enum),
SND_SOC_BYTES("Comp Atk Time", R_CATKTCL, 2),
/* Effects */
SOC_SINGLE("3D Switch", R_FXCTL, FB_FXCTL_3DEN, 1, 0),
SOC_SINGLE("Treble Switch", R_FXCTL, FB_FXCTL_TEEN, 1, 0),
SOC_SINGLE("Treble Bypass Switch", R_FXCTL, FB_FXCTL_TNLFBYPASS, 1, 0),
SOC_SINGLE("Bass Switch", R_FXCTL, FB_FXCTL_BEEN, 1, 0),
SOC_SINGLE("Bass Bypass Switch", R_FXCTL, FB_FXCTL_BNLFBYPASS, 1, 0),
/* MBC */
SOC_SINGLE("MBC Band1 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN1, 1, 0),
SOC_SINGLE("MBC Band2 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN2, 1, 0),
SOC_SINGLE("MBC Band3 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN3, 1, 0),
SOC_ENUM("MBC Band1 Level Detect",
mbc_level_detection_enums[0]),
SOC_ENUM("MBC Band2 Level Detect",
mbc_level_detection_enums[1]),
SOC_ENUM("MBC Band3 Level Detect",
mbc_level_detection_enums[2]),
SOC_ENUM("MBC Band1 Level Detect Win",
mbc_level_detection_window_enums[0]),
SOC_ENUM("MBC Band2 Level Detect Win",
mbc_level_detection_window_enums[1]),
SOC_ENUM("MBC Band3 Level Detect Win",
mbc_level_detection_window_enums[2]),
SOC_SINGLE("MBC1 Phase Invert Switch",
R_DACMBCMUG1, FB_DACMBCMUG1_PHASE, 1, 0),
SOC_SINGLE_TLV("DAC MBC1 Make-Up Gain Volume",
R_DACMBCMUG1, FB_DACMBCMUG1_MUGAIN, 0x1f, 0, mugain_scale),
SOC_SINGLE_TLV("DAC MBC1 Comp Thresh Volume",
R_DACMBCTHR1, FB_DACMBCTHR1_THRESH, 0xff, 0, compth_scale),
SOC_ENUM("DAC MBC1 Comp Ratio",
dac_mbc1_compressor_ratio_enum),
SND_SOC_BYTES("DAC MBC1 Comp Atk Time", R_DACMBCATK1L, 2),
SND_SOC_BYTES("DAC MBC1 Comp Rel Time Const",
R_DACMBCREL1L, 2),
SOC_SINGLE("MBC2 Phase Invert Switch",
R_DACMBCMUG2, FB_DACMBCMUG2_PHASE, 1, 0),
SOC_SINGLE_TLV("DAC MBC2 Make-Up Gain Volume",
R_DACMBCMUG2, FB_DACMBCMUG2_MUGAIN, 0x1f, 0, mugain_scale),
SOC_SINGLE_TLV("DAC MBC2 Comp Thresh Volume",
R_DACMBCTHR2, FB_DACMBCTHR2_THRESH, 0xff, 0, compth_scale),
SOC_ENUM("DAC MBC2 Comp Ratio",
dac_mbc2_compressor_ratio_enum),
SND_SOC_BYTES("DAC MBC2 Comp Atk Time", R_DACMBCATK2L, 2),
SND_SOC_BYTES("DAC MBC2 Comp Rel Time Const",
R_DACMBCREL2L, 2),
SOC_SINGLE("MBC3 Phase Invert Switch",
R_DACMBCMUG3, FB_DACMBCMUG3_PHASE, 1, 0),
SOC_SINGLE_TLV("DAC MBC3 Make-Up Gain Volume",
R_DACMBCMUG3, FB_DACMBCMUG3_MUGAIN, 0x1f, 0, mugain_scale),
SOC_SINGLE_TLV("DAC MBC3 Comp Thresh Volume",
R_DACMBCTHR3, FB_DACMBCTHR3_THRESH, 0xff, 0, compth_scale),
SOC_ENUM("DAC MBC3 Comp Ratio",
dac_mbc3_compressor_ratio_enum),
SND_SOC_BYTES("DAC MBC3 Comp Atk Time", R_DACMBCATK3L, 2),
SND_SOC_BYTES("DAC MBC3 Comp Rel Time Const",
R_DACMBCREL3L, 2),
};
static int setup_sample_format(struct snd_soc_component *component,
snd_pcm_format_t format)
{
unsigned int width;
int ret;
switch (format) {
case SNDRV_PCM_FORMAT_S16_LE:
width = RV_AIC1_WL_16;
break;
case SNDRV_PCM_FORMAT_S20_3LE:
width = RV_AIC1_WL_20;
break;
case SNDRV_PCM_FORMAT_S24_LE:
width = RV_AIC1_WL_24;
break;
case SNDRV_PCM_FORMAT_S32_LE:
width = RV_AIC1_WL_32;
break;
default:
ret = -EINVAL;
dev_err(component->dev, "Unsupported format width (%d)\n", ret);
return ret;
}
ret = snd_soc_component_update_bits(component,
R_AIC1, RM_AIC1_WL, width);
if (ret < 0) {
dev_err(component->dev,
"Failed to set sample width (%d)\n", ret);
return ret;
}
return 0;
}
static int setup_sample_rate(struct snd_soc_component *component,
unsigned int rate)
{
struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component);
unsigned int br, bm;
int ret;
switch (rate) {
case 8000:
br = RV_DACSR_DBR_32;
bm = RV_DACSR_DBM_PT25;
break;
case 16000:
br = RV_DACSR_DBR_32;
bm = RV_DACSR_DBM_PT5;
break;
case 24000:
br = RV_DACSR_DBR_48;
bm = RV_DACSR_DBM_PT5;
break;
case 32000:
br = RV_DACSR_DBR_32;
bm = RV_DACSR_DBM_1;
break;
case 48000:
br = RV_DACSR_DBR_48;
bm = RV_DACSR_DBM_1;
break;
case 96000:
br = RV_DACSR_DBR_48;
bm = RV_DACSR_DBM_2;
break;
case 11025:
br = RV_DACSR_DBR_44_1;
bm = RV_DACSR_DBM_PT25;
break;
case 22050:
br = RV_DACSR_DBR_44_1;
bm = RV_DACSR_DBM_PT5;
break;
case 44100:
br = RV_DACSR_DBR_44_1;
bm = RV_DACSR_DBM_1;
break;
case 88200:
br = RV_DACSR_DBR_44_1;
bm = RV_DACSR_DBM_2;
break;
default:
dev_err(component->dev, "Unsupported sample rate %d\n", rate);
return -EINVAL;
}
/* DAC and ADC share bit and frame clock */
ret = snd_soc_component_update_bits(component,
R_DACSR, RM_DACSR_DBR, br);
if (ret < 0) {
dev_err(component->dev,
"Failed to update register (%d)\n", ret);
return ret;
}
ret = snd_soc_component_update_bits(component,
R_DACSR, RM_DACSR_DBM, bm);
if (ret < 0) {
dev_err(component->dev,
"Failed to update register (%d)\n", ret);
return ret;
}
ret = snd_soc_component_update_bits(component,
R_ADCSR, RM_DACSR_DBR, br);
if (ret < 0) {
dev_err(component->dev,
"Failed to update register (%d)\n", ret);
return ret;
}
ret = snd_soc_component_update_bits(component,
R_ADCSR, RM_DACSR_DBM, bm);
if (ret < 0) {
dev_err(component->dev,
"Failed to update register (%d)\n", ret);
return ret;
}
mutex_lock(&tscs42xx->audio_params_lock);
tscs42xx->samplerate = rate;
mutex_unlock(&tscs42xx->audio_params_lock);
return 0;
}
struct reg_setting {
unsigned int addr;
unsigned int val;
unsigned int mask;
};
#define PLL_REG_SETTINGS_COUNT 13
struct pll_ctl {
int input_freq;
struct reg_setting settings[PLL_REG_SETTINGS_COUNT];
};
#define PLL_CTL(f, rt, rd, r1b_l, r9, ra, rb, \
rc, r12, r1b_h, re, rf, r10, r11) \
{ \
.input_freq = f, \
.settings = { \
{R_TIMEBASE, rt, 0xFF}, \
{R_PLLCTLD, rd, 0xFF}, \
{R_PLLCTL1B, r1b_l, 0x0F}, \
{R_PLLCTL9, r9, 0xFF}, \
{R_PLLCTLA, ra, 0xFF}, \
{R_PLLCTLB, rb, 0xFF}, \
{R_PLLCTLC, rc, 0xFF}, \
{R_PLLCTL12, r12, 0xFF}, \
{R_PLLCTL1B, r1b_h, 0xF0}, \
{R_PLLCTLE, re, 0xFF}, \
{R_PLLCTLF, rf, 0xFF}, \
{R_PLLCTL10, r10, 0xFF}, \
{R_PLLCTL11, r11, 0xFF}, \
}, \
}
static const struct pll_ctl pll_ctls[] = {
PLL_CTL(1411200, 0x05,
0x39, 0x04, 0x07, 0x02, 0xC3, 0x04,
0x1B, 0x10, 0x03, 0x03, 0xD0, 0x02),
PLL_CTL(1536000, 0x05,
0x1A, 0x04, 0x02, 0x03, 0xE0, 0x01,
0x1A, 0x10, 0x02, 0x03, 0xB9, 0x01),
PLL_CTL(2822400, 0x0A,
0x23, 0x04, 0x07, 0x04, 0xC3, 0x04,
0x22, 0x10, 0x05, 0x03, 0x58, 0x02),
PLL_CTL(3072000, 0x0B,
0x22, 0x04, 0x07, 0x03, 0x48, 0x03,
0x1A, 0x10, 0x04, 0x03, 0xB9, 0x01),
PLL_CTL(5644800, 0x15,
0x23, 0x04, 0x0E, 0x04, 0xC3, 0x04,
0x1A, 0x10, 0x08, 0x03, 0xE0, 0x01),
PLL_CTL(6144000, 0x17,
0x1A, 0x04, 0x08, 0x03, 0xE0, 0x01,
0x1A, 0x10, 0x08, 0x03, 0xB9, 0x01),
PLL_CTL(12000000, 0x2E,
0x1B, 0x04, 0x19, 0x03, 0x00, 0x03,
0x2A, 0x10, 0x19, 0x05, 0x98, 0x04),
PLL_CTL(19200000, 0x4A,
0x13, 0x04, 0x14, 0x03, 0x80, 0x01,
0x1A, 0x10, 0x19, 0x03, 0xB9, 0x01),
PLL_CTL(22000000, 0x55,
0x2A, 0x04, 0x37, 0x05, 0x00, 0x06,
0x22, 0x10, 0x26, 0x03, 0x49, 0x02),
PLL_CTL(22579200, 0x57,
0x22, 0x04, 0x31, 0x03, 0x20, 0x03,
0x1A, 0x10, 0x1D, 0x03, 0xB3, 0x01),
PLL_CTL(24000000, 0x5D,
0x13, 0x04, 0x19, 0x03, 0x80, 0x01,
0x1B, 0x10, 0x19, 0x05, 0x4C, 0x02),
PLL_CTL(24576000, 0x5F,
0x13, 0x04, 0x1D, 0x03, 0xB3, 0x01,
0x22, 0x10, 0x40, 0x03, 0x72, 0x03),
PLL_CTL(27000000, 0x68,
0x22, 0x04, 0x4B, 0x03, 0x00, 0x04,
0x2A, 0x10, 0x7D, 0x03, 0x20, 0x06),
PLL_CTL(36000000, 0x8C,
0x1B, 0x04, 0x4B, 0x03, 0x00, 0x03,
0x2A, 0x10, 0x7D, 0x03, 0x98, 0x04),
PLL_CTL(25000000, 0x61,
0x1B, 0x04, 0x37, 0x03, 0x2B, 0x03,
0x1A, 0x10, 0x2A, 0x03, 0x39, 0x02),
PLL_CTL(26000000, 0x65,
0x23, 0x04, 0x41, 0x05, 0x00, 0x06,
0x1A, 0x10, 0x26, 0x03, 0xEF, 0x01),
PLL_CTL(12288000, 0x2F,
0x1A, 0x04, 0x12, 0x03, 0x1C, 0x02,
0x22, 0x10, 0x20, 0x03, 0x72, 0x03),
PLL_CTL(40000000, 0x9B,
0x22, 0x08, 0x7D, 0x03, 0x80, 0x04,
0x23, 0x10, 0x7D, 0x05, 0xE4, 0x06),
PLL_CTL(512000, 0x01,
0x22, 0x04, 0x01, 0x03, 0xD0, 0x02,
0x1B, 0x10, 0x01, 0x04, 0x72, 0x03),
PLL_CTL(705600, 0x02,
0x22, 0x04, 0x02, 0x03, 0x15, 0x04,
0x22, 0x10, 0x01, 0x04, 0x80, 0x02),
PLL_CTL(1024000, 0x03,
0x22, 0x04, 0x02, 0x03, 0xD0, 0x02,
0x1B, 0x10, 0x02, 0x04, 0x72, 0x03),
PLL_CTL(2048000, 0x07,
0x22, 0x04, 0x04, 0x03, 0xD0, 0x02,
0x1B, 0x10, 0x04, 0x04, 0x72, 0x03),
PLL_CTL(2400000, 0x08,
0x22, 0x04, 0x05, 0x03, 0x00, 0x03,
0x23, 0x10, 0x05, 0x05, 0x98, 0x04),
};
static const struct pll_ctl *get_pll_ctl(int input_freq)
{
int i;
const struct pll_ctl *pll_ctl = NULL;
for (i = 0; i < ARRAY_SIZE(pll_ctls); ++i)
if (input_freq == pll_ctls[i].input_freq) {
pll_ctl = &pll_ctls[i];
break;
}
return pll_ctl;
}
static int set_pll_ctl_from_input_freq(struct snd_soc_component *component,
const int input_freq)
{
int ret;
int i;
const struct pll_ctl *pll_ctl;
pll_ctl = get_pll_ctl(input_freq);
if (!pll_ctl) {
ret = -EINVAL;
dev_err(component->dev, "No PLL input entry for %d (%d)\n",
input_freq, ret);
return ret;
}
for (i = 0; i < PLL_REG_SETTINGS_COUNT; ++i) {
ret = snd_soc_component_update_bits(component,
pll_ctl->settings[i].addr,
pll_ctl->settings[i].mask,
pll_ctl->settings[i].val);
if (ret < 0) {
dev_err(component->dev, "Failed to set pll ctl (%d)\n",
ret);
return ret;
}
}
return 0;
}
static int tscs42xx_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *codec_dai)
{
struct snd_soc_component *component = codec_dai->component;
int ret;
ret = setup_sample_format(component, params_format(params));
if (ret < 0) {
dev_err(component->dev, "Failed to setup sample format (%d)\n",
ret);
return ret;
}
ret = setup_sample_rate(component, params_rate(params));
if (ret < 0) {
dev_err(component->dev,
"Failed to setup sample rate (%d)\n", ret);
return ret;
}
return 0;
}
static inline int dac_mute(struct snd_soc_component *component)
{
int ret;
ret = snd_soc_component_update_bits(component,
R_CNVRTR1, RM_CNVRTR1_DACMU,
RV_CNVRTR1_DACMU_ENABLE);
if (ret < 0) {
dev_err(component->dev, "Failed to mute DAC (%d)\n",
ret);
return ret;
}
return 0;
}
static inline int dac_unmute(struct snd_soc_component *component)
{
int ret;
ret = snd_soc_component_update_bits(component,
R_CNVRTR1, RM_CNVRTR1_DACMU,
RV_CNVRTR1_DACMU_DISABLE);
if (ret < 0) {
dev_err(component->dev, "Failed to unmute DAC (%d)\n",
ret);
return ret;
}
return 0;
}
static inline int adc_mute(struct snd_soc_component *component)
{
int ret;
ret = snd_soc_component_update_bits(component,
R_CNVRTR0, RM_CNVRTR0_ADCMU, RV_CNVRTR0_ADCMU_ENABLE);
if (ret < 0) {
dev_err(component->dev, "Failed to mute ADC (%d)\n",
ret);
return ret;
}
return 0;
}
static inline int adc_unmute(struct snd_soc_component *component)
{
int ret;
ret = snd_soc_component_update_bits(component,
R_CNVRTR0, RM_CNVRTR0_ADCMU, RV_CNVRTR0_ADCMU_DISABLE);
if (ret < 0) {
dev_err(component->dev, "Failed to unmute ADC (%d)\n",
ret);
return ret;
}
return 0;
}
static int tscs42xx_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
{
struct snd_soc_component *component = dai->component;
int ret;
if (mute)
if (stream == SNDRV_PCM_STREAM_PLAYBACK)
ret = dac_mute(component);
else
ret = adc_mute(component);
else
if (stream == SNDRV_PCM_STREAM_PLAYBACK)
ret = dac_unmute(component);
else
ret = adc_unmute(component);
return ret;
}
static int tscs42xx_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
int ret;
/* Consumer mode not supported since it needs always-on frame clock */
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
ret = snd_soc_component_update_bits(component,
R_AIC1, RM_AIC1_MS, RV_AIC1_MS_MASTER);
if (ret < 0) {
dev_err(component->dev,
"Failed to set codec DAI master (%d)\n", ret);
return ret;
}
break;
default:
ret = -EINVAL;
dev_err(component->dev, "Unsupported format (%d)\n", ret);
return ret;
}
return 0;
}
static int tscs42xx_set_dai_bclk_ratio(struct snd_soc_dai *codec_dai,
unsigned int ratio)
{
struct snd_soc_component *component = codec_dai->component;
struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component);
unsigned int value;
int ret = 0;
switch (ratio) {
case 32:
value = RV_DACSR_DBCM_32;
break;
case 40:
value = RV_DACSR_DBCM_40;
break;
case 64:
value = RV_DACSR_DBCM_64;
break;
default:
dev_err(component->dev, "Unsupported bclk ratio (%d)\n", ret);
return -EINVAL;
}
ret = snd_soc_component_update_bits(component,
R_DACSR, RM_DACSR_DBCM, value);
if (ret < 0) {
dev_err(component->dev,
"Failed to set DAC BCLK ratio (%d)\n", ret);
return ret;
}
ret = snd_soc_component_update_bits(component,
R_ADCSR, RM_ADCSR_ABCM, value);
if (ret < 0) {
dev_err(component->dev,
"Failed to set ADC BCLK ratio (%d)\n", ret);
return ret;
}
mutex_lock(&tscs42xx->audio_params_lock);
tscs42xx->bclk_ratio = ratio;
mutex_unlock(&tscs42xx->audio_params_lock);
return 0;
}
static const struct snd_soc_dai_ops tscs42xx_dai_ops = {
.hw_params = tscs42xx_hw_params,
.mute_stream = tscs42xx_mute_stream,
.set_fmt = tscs42xx_set_dai_fmt,
.set_bclk_ratio = tscs42xx_set_dai_bclk_ratio,
};
static int part_is_valid(struct tscs42xx *tscs42xx)
{
int val;
int ret;
unsigned int reg;
ret = regmap_read(tscs42xx->regmap, R_DEVIDH, ®);
if (ret < 0)
return ret;
val = reg << 8;
ret = regmap_read(tscs42xx->regmap, R_DEVIDL, ®);
if (ret < 0)
return ret;
val |= reg;
switch (val) {
case 0x4A74:
case 0x4A73:
return true;
default:
return false;
}
}
static int set_sysclk(struct snd_soc_component *component)
{
struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component);
unsigned long freq;
int ret;
switch (tscs42xx->sysclk_src_id) {
case TSCS42XX_PLL_SRC_XTAL:
case TSCS42XX_PLL_SRC_MCLK1:
ret = snd_soc_component_write(component, R_PLLREFSEL,
RV_PLLREFSEL_PLL1_REF_SEL_XTAL_MCLK1 |
RV_PLLREFSEL_PLL2_REF_SEL_XTAL_MCLK1);
if (ret < 0) {
dev_err(component->dev,
"Failed to set pll reference input (%d)\n",
ret);
return ret;
}
break;
case TSCS42XX_PLL_SRC_MCLK2:
ret = snd_soc_component_write(component, R_PLLREFSEL,
RV_PLLREFSEL_PLL1_REF_SEL_MCLK2 |
RV_PLLREFSEL_PLL2_REF_SEL_MCLK2);
if (ret < 0) {
dev_err(component->dev,
"Failed to set PLL reference (%d)\n", ret);
return ret;
}
break;
default:
dev_err(component->dev, "pll src is unsupported\n");
return -EINVAL;
}
freq = clk_get_rate(tscs42xx->sysclk);
ret = set_pll_ctl_from_input_freq(component, freq);
if (ret < 0) {
dev_err(component->dev,
"Failed to setup PLL input freq (%d)\n", ret);
return ret;
}
return 0;
}
static int tscs42xx_probe(struct snd_soc_component *component)
{
return set_sysclk(component);
}
static const struct snd_soc_component_driver soc_codec_dev_tscs42xx = {
.probe = tscs42xx_probe,
.dapm_widgets = tscs42xx_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(tscs42xx_dapm_widgets),
.dapm_routes = tscs42xx_intercon,
.num_dapm_routes = ARRAY_SIZE(tscs42xx_intercon),
.controls = tscs42xx_snd_controls,
.num_controls = ARRAY_SIZE(tscs42xx_snd_controls),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static inline void init_coeff_ram_cache(struct tscs42xx *tscs42xx)
{
static const u8 norm_addrs[] = {
0x00, 0x05, 0x0a, 0x0f, 0x14, 0x19, 0x1f, 0x20, 0x25, 0x2a,
0x2f, 0x34, 0x39, 0x3f, 0x40, 0x45, 0x4a, 0x4f, 0x54, 0x59,
0x5f, 0x60, 0x65, 0x6a, 0x6f, 0x74, 0x79, 0x7f, 0x80, 0x85,
0x8c, 0x91, 0x96, 0x97, 0x9c, 0xa3, 0xa8, 0xad, 0xaf, 0xb0,
0xb5, 0xba, 0xbf, 0xc4, 0xc9,
};
u8 *coeff_ram = tscs42xx->coeff_ram;
int i;
for (i = 0; i < ARRAY_SIZE(norm_addrs); i++)
coeff_ram[((norm_addrs[i] + 1) * COEFF_SIZE) - 1] = 0x40;
}
#define TSCS42XX_RATES SNDRV_PCM_RATE_8000_96000
#define TSCS42XX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
| SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver tscs42xx_dai = {
.name = "tscs42xx-HiFi",
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 2,
.channels_max = 2,
.rates = TSCS42XX_RATES,
.formats = TSCS42XX_FORMATS,},
.capture = {
.stream_name = "HiFi Capture",
.channels_min = 2,
.channels_max = 2,
.rates = TSCS42XX_RATES,
.formats = TSCS42XX_FORMATS,},
.ops = &tscs42xx_dai_ops,
.symmetric_rate = 1,
.symmetric_channels = 1,
.symmetric_sample_bits = 1,
};
static const struct reg_sequence tscs42xx_patch[] = {
{ R_AIC2, RV_AIC2_BLRCM_DAC_BCLK_LRCLK_SHARED },
};
static char const * const src_names[TSCS42XX_PLL_SRC_CNT] = {
"xtal", "mclk1", "mclk2"};
static int tscs42xx_i2c_probe(struct i2c_client *i2c)
{
struct tscs42xx *tscs42xx;
int src;
int ret;
tscs42xx = devm_kzalloc(&i2c->dev, sizeof(*tscs42xx), GFP_KERNEL);
if (!tscs42xx) {
ret = -ENOMEM;
dev_err(&i2c->dev,
"Failed to allocate memory for data (%d)\n", ret);
return ret;
}
i2c_set_clientdata(i2c, tscs42xx);
for (src = TSCS42XX_PLL_SRC_XTAL; src < TSCS42XX_PLL_SRC_CNT; src++) {
tscs42xx->sysclk = devm_clk_get(&i2c->dev, src_names[src]);
if (!IS_ERR(tscs42xx->sysclk)) {
break;
} else if (PTR_ERR(tscs42xx->sysclk) != -ENOENT) {
ret = PTR_ERR(tscs42xx->sysclk);
dev_err(&i2c->dev, "Failed to get sysclk (%d)\n", ret);
return ret;
}
}
if (src == TSCS42XX_PLL_SRC_CNT) {
ret = -EINVAL;
dev_err(&i2c->dev, "Failed to get a valid clock name (%d)\n",
ret);
return ret;
}
tscs42xx->sysclk_src_id = src;
tscs42xx->regmap = devm_regmap_init_i2c(i2c, &tscs42xx_regmap);
if (IS_ERR(tscs42xx->regmap)) {
ret = PTR_ERR(tscs42xx->regmap);
dev_err(&i2c->dev, "Failed to allocate regmap (%d)\n", ret);
return ret;
}
init_coeff_ram_cache(tscs42xx);
ret = part_is_valid(tscs42xx);
if (ret <= 0) {
dev_err(&i2c->dev, "No valid part (%d)\n", ret);
ret = -ENODEV;
return ret;
}
ret = regmap_write(tscs42xx->regmap, R_RESET, RV_RESET_ENABLE);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to reset device (%d)\n", ret);
return ret;
}
ret = regmap_register_patch(tscs42xx->regmap, tscs42xx_patch,
ARRAY_SIZE(tscs42xx_patch));
if (ret < 0) {
dev_err(&i2c->dev, "Failed to apply patch (%d)\n", ret);
return ret;
}
mutex_init(&tscs42xx->audio_params_lock);
mutex_init(&tscs42xx->coeff_ram_lock);
mutex_init(&tscs42xx->pll_lock);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_codec_dev_tscs42xx, &tscs42xx_dai, 1);
if (ret) {
dev_err(&i2c->dev, "Failed to register codec (%d)\n", ret);
return ret;
}
return 0;
}
static const struct i2c_device_id tscs42xx_i2c_id[] = {
{ "tscs42A1", 0 },
{ "tscs42A2", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, tscs42xx_i2c_id);
static const struct of_device_id tscs42xx_of_match[] = {
{ .compatible = "tempo,tscs42A1", },
{ .compatible = "tempo,tscs42A2", },
{ }
};
MODULE_DEVICE_TABLE(of, tscs42xx_of_match);
static struct i2c_driver tscs42xx_i2c_driver = {
.driver = {
.name = "tscs42xx",
.of_match_table = tscs42xx_of_match,
},
.probe = tscs42xx_i2c_probe,
.id_table = tscs42xx_i2c_id,
};
module_i2c_driver(tscs42xx_i2c_driver);
MODULE_AUTHOR("Tempo Semiconductor <[email protected]");
MODULE_DESCRIPTION("ASoC TSCS42xx driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/tscs42xx.c |
// SPDX-License-Identifier: GPL-2.0
//
// cs35l45-spi.c -- CS35L45 SPI driver
//
// Copyright 2019-2022 Cirrus Logic, Inc.
//
// Author: James Schulman <[email protected]>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include "cs35l45.h"
static int cs35l45_spi_probe(struct spi_device *spi)
{
struct cs35l45_private *cs35l45;
struct device *dev = &spi->dev;
int ret;
cs35l45 = devm_kzalloc(dev, sizeof(struct cs35l45_private), GFP_KERNEL);
if (cs35l45 == NULL)
return -ENOMEM;
spi->max_speed_hz = CS35L45_SPI_MAX_FREQ;
spi_setup(spi);
spi_set_drvdata(spi, cs35l45);
cs35l45->regmap = devm_regmap_init_spi(spi, &cs35l45_spi_regmap);
if (IS_ERR(cs35l45->regmap)) {
ret = PTR_ERR(cs35l45->regmap);
dev_err(dev, "Failed to allocate register map: %d\n", ret);
return ret;
}
cs35l45->dev = dev;
cs35l45->irq = spi->irq;
cs35l45->bus_type = CONTROL_BUS_SPI;
return cs35l45_probe(cs35l45);
}
static void cs35l45_spi_remove(struct spi_device *spi)
{
struct cs35l45_private *cs35l45 = spi_get_drvdata(spi);
cs35l45_remove(cs35l45);
}
static const struct of_device_id cs35l45_of_match[] = {
{ .compatible = "cirrus,cs35l45" },
{},
};
MODULE_DEVICE_TABLE(of, cs35l45_of_match);
static const struct spi_device_id cs35l45_id_spi[] = {
{ "cs35l45", 0 },
{}
};
MODULE_DEVICE_TABLE(spi, cs35l45_id_spi);
static struct spi_driver cs35l45_spi_driver = {
.driver = {
.name = "cs35l45",
.of_match_table = cs35l45_of_match,
.pm = &cs35l45_pm_ops,
},
.id_table = cs35l45_id_spi,
.probe = cs35l45_spi_probe,
.remove = cs35l45_spi_remove,
};
module_spi_driver(cs35l45_spi_driver);
MODULE_DESCRIPTION("SPI CS35L45 driver");
MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_IMPORT_NS(SND_SOC_CS35L45);
| linux-master | sound/soc/codecs/cs35l45-spi.c |
// SPDX-License-Identifier: GPL-2.0-or-later
//
// sma1303.c -- sma1303 ALSA SoC Audio driver
//
// Copyright 2023 Iron Device Corporation
//
// Auther: Gyuhwa Park <[email protected]>
// Kiseok Jo <[email protected]>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <linux/of_device.h>
#include <linux/slab.h>
#include <asm/div64.h>
#include "sma1303.h"
#define CHECK_PERIOD_TIME 1 /* sec per HZ */
#define MAX_CONTROL_NAME 48
#define PLL_MATCH(_input_clk_name, _output_clk_name, _input_clk,\
_post_n, _n, _vco, _p_cp)\
{\
.input_clk_name = _input_clk_name,\
.output_clk_name = _output_clk_name,\
.input_clk = _input_clk,\
.post_n = _post_n,\
.n = _n,\
.vco = _vco,\
.p_cp = _p_cp,\
}
enum sma1303_type {
SMA1303,
};
struct sma1303_pll_match {
char *input_clk_name;
char *output_clk_name;
unsigned int input_clk;
unsigned int post_n;
unsigned int n;
unsigned int vco;
unsigned int p_cp;
};
struct sma1303_priv {
enum sma1303_type devtype;
struct attribute_group *attr_grp;
struct delayed_work check_fault_work;
struct device *dev;
struct kobject *kobj;
struct regmap *regmap;
struct sma1303_pll_match *pll_matches;
bool amp_power_status;
bool force_mute_status;
int num_of_pll_matches;
int retry_cnt;
unsigned int amp_mode;
unsigned int cur_vol;
unsigned int format;
unsigned int frame_size;
unsigned int init_vol;
unsigned int last_bclk;
unsigned int last_ocp_val;
unsigned int last_over_temp;
unsigned int rev_num;
unsigned int sys_clk_id;
unsigned int tdm_slot_rx;
unsigned int tdm_slot_tx;
unsigned int tsdw_cnt;
long check_fault_period;
long check_fault_status;
};
static struct sma1303_pll_match sma1303_pll_matches[] = {
PLL_MATCH("1.411MHz", "24.595MHz", 1411200, 0x07, 0xF4, 0x8B, 0x03),
PLL_MATCH("1.536MHz", "24.576MHz", 1536000, 0x07, 0xE0, 0x8B, 0x03),
PLL_MATCH("3.072MHz", "24.576MHz", 3072000, 0x07, 0x70, 0x8B, 0x03),
PLL_MATCH("6.144MHz", "24.576MHz", 6144000, 0x07, 0x70, 0x8B, 0x07),
PLL_MATCH("12.288MHz", "24.576MHz", 12288000, 0x07, 0x70, 0x8B, 0x0B),
PLL_MATCH("19.2MHz", "24.343MHz", 19200000, 0x07, 0x47, 0x8B, 0x0A),
PLL_MATCH("24.576MHz", "24.576MHz", 24576000, 0x07, 0x70, 0x8B, 0x0F),
};
static int sma1303_startup(struct snd_soc_component *);
static int sma1303_shutdown(struct snd_soc_component *);
static const struct reg_default sma1303_reg_def[] = {
{ 0x00, 0x80 },
{ 0x01, 0x00 },
{ 0x02, 0x00 },
{ 0x03, 0x11 },
{ 0x04, 0x17 },
{ 0x09, 0x00 },
{ 0x0A, 0x31 },
{ 0x0B, 0x98 },
{ 0x0C, 0x84 },
{ 0x0D, 0x07 },
{ 0x0E, 0x3F },
{ 0x10, 0x00 },
{ 0x11, 0x00 },
{ 0x12, 0x00 },
{ 0x14, 0x5C },
{ 0x15, 0x01 },
{ 0x16, 0x0F },
{ 0x17, 0x0F },
{ 0x18, 0x0F },
{ 0x19, 0x00 },
{ 0x1A, 0x00 },
{ 0x1B, 0x00 },
{ 0x23, 0x19 },
{ 0x24, 0x00 },
{ 0x25, 0x00 },
{ 0x26, 0x04 },
{ 0x33, 0x00 },
{ 0x36, 0x92 },
{ 0x37, 0x27 },
{ 0x3B, 0x5A },
{ 0x3C, 0x20 },
{ 0x3D, 0x00 },
{ 0x3E, 0x03 },
{ 0x3F, 0x0C },
{ 0x8B, 0x07 },
{ 0x8C, 0x70 },
{ 0x8D, 0x8B },
{ 0x8E, 0x6F },
{ 0x8F, 0x03 },
{ 0x90, 0x26 },
{ 0x91, 0x42 },
{ 0x92, 0xE0 },
{ 0x94, 0x35 },
{ 0x95, 0x0C },
{ 0x96, 0x42 },
{ 0x97, 0x95 },
{ 0xA0, 0x00 },
{ 0xA1, 0x3B },
{ 0xA2, 0xC8 },
{ 0xA3, 0x28 },
{ 0xA4, 0x40 },
{ 0xA5, 0x01 },
{ 0xA6, 0x41 },
{ 0xA7, 0x00 },
};
static bool sma1303_readable_register(struct device *dev, unsigned int reg)
{
bool result;
if (reg > SMA1303_FF_DEVICE_INDEX)
return false;
switch (reg) {
case SMA1303_00_SYSTEM_CTRL ... SMA1303_04_INPUT1_CTRL4:
case SMA1303_09_OUTPUT_CTRL ... SMA1303_0E_MUTE_VOL_CTRL:
case SMA1303_10_SYSTEM_CTRL1 ... SMA1303_12_SYSTEM_CTRL3:
case SMA1303_14_MODULATOR ... SMA1303_1B_BASS_SPK7:
case SMA1303_23_COMP_LIM1 ... SMA1303_26_COMP_LIM4:
case SMA1303_33_SDM_CTRL ... SMA1303_34_OTP_DATA1:
case SMA1303_36_PROTECTION ... SMA1303_38_OTP_TRM0:
case SMA1303_3B_TEST1 ... SMA1303_3F_ATEST2:
case SMA1303_8B_PLL_POST_N ... SMA1303_92_FDPEC_CTRL:
case SMA1303_94_BOOST_CTRL1 ... SMA1303_97_BOOST_CTRL4:
case SMA1303_A0_PAD_CTRL0 ... SMA1303_A7_CLK_MON:
case SMA1303_FA_STATUS1 ... SMA1303_FB_STATUS2:
result = true;
break;
case SMA1303_FF_DEVICE_INDEX:
result = true;
break;
default:
result = false;
break;
}
return result;
}
static bool sma1303_writeable_register(struct device *dev, unsigned int reg)
{
bool result;
if (reg > SMA1303_FF_DEVICE_INDEX)
return false;
switch (reg) {
case SMA1303_00_SYSTEM_CTRL ... SMA1303_04_INPUT1_CTRL4:
case SMA1303_09_OUTPUT_CTRL ... SMA1303_0E_MUTE_VOL_CTRL:
case SMA1303_10_SYSTEM_CTRL1 ... SMA1303_12_SYSTEM_CTRL3:
case SMA1303_14_MODULATOR ... SMA1303_1B_BASS_SPK7:
case SMA1303_23_COMP_LIM1 ... SMA1303_26_COMP_LIM4:
case SMA1303_33_SDM_CTRL:
case SMA1303_36_PROTECTION ... SMA1303_37_SLOPE_CTRL:
case SMA1303_3B_TEST1 ... SMA1303_3F_ATEST2:
case SMA1303_8B_PLL_POST_N ... SMA1303_92_FDPEC_CTRL:
case SMA1303_94_BOOST_CTRL1 ... SMA1303_97_BOOST_CTRL4:
case SMA1303_A0_PAD_CTRL0 ... SMA1303_A7_CLK_MON:
result = true;
break;
default:
result = false;
break;
}
return result;
}
static bool sma1303_volatile_register(struct device *dev, unsigned int reg)
{
bool result;
switch (reg) {
case SMA1303_FA_STATUS1 ... SMA1303_FB_STATUS2:
result = true;
break;
case SMA1303_FF_DEVICE_INDEX:
result = true;
break;
default:
result = false;
break;
}
return result;
}
static const DECLARE_TLV_DB_SCALE(sma1303_spk_tlv, -6000, 50, 0);
static int sma1303_regmap_write(struct sma1303_priv *sma1303,
unsigned int reg, unsigned int val)
{
int ret = 0;
int cnt = sma1303->retry_cnt;
while (cnt--) {
ret = regmap_write(sma1303->regmap, reg, val);
if (ret < 0) {
dev_err(sma1303->dev,
"Failed to write [0x%02X]\n", reg);
} else
break;
}
return ret;
}
static int sma1303_regmap_update_bits(struct sma1303_priv *sma1303,
unsigned int reg, unsigned int mask, unsigned int val, bool *change)
{
int ret = 0;
int cnt = sma1303->retry_cnt;
while (cnt--) {
ret = regmap_update_bits_check(sma1303->regmap, reg,
mask, val, change);
if (ret < 0) {
dev_err(sma1303->dev,
"Failed to update [0x%02X]\n", reg);
} else
break;
}
return ret;
}
static int sma1303_regmap_read(struct sma1303_priv *sma1303,
unsigned int reg, unsigned int *val)
{
int ret = 0;
int cnt = sma1303->retry_cnt;
while (cnt--) {
ret = regmap_read(sma1303->regmap, reg, val);
if (ret < 0) {
dev_err(sma1303->dev,
"Failed to read [0x%02X]\n", reg);
} else
break;
}
return ret;
}
static const char * const sma1303_aif_in_source_text[] = {
"Mono", "Left", "Right"};
static const char * const sma1303_aif_out_source_text[] = {
"Disable", "After_FmtC", "After_Mixer", "After_DSP", "After_Post",
"Clk_PLL", "Clk_OSC"};
static const char * const sma1303_tdm_slot_text[] = {
"Slot0", "Slot1", "Slot2", "Slot3",
"Slot4", "Slot5", "Slot6", "Slot7"};
static const struct soc_enum sma1303_aif_in_source_enum =
SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(sma1303_aif_in_source_text),
sma1303_aif_in_source_text);
static const struct soc_enum sma1303_aif_out_source_enum =
SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(sma1303_aif_out_source_text),
sma1303_aif_out_source_text);
static const struct soc_enum sma1303_tdm_slot_enum =
SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(sma1303_tdm_slot_text),
sma1303_tdm_slot_text);
static int sma1303_force_mute_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = (int)sma1303->force_mute_status;
dev_dbg(sma1303->dev, "%s : Force Mute %s\n", __func__,
sma1303->force_mute_status ? "ON" : "OFF");
return 0;
}
static int sma1303_force_mute_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
bool change = false, val = (bool)ucontrol->value.integer.value[0];
if (sma1303->force_mute_status == val)
change = false;
else {
change = true;
sma1303->force_mute_status = val;
}
dev_dbg(sma1303->dev, "%s : Force Mute %s\n", __func__,
sma1303->force_mute_status ? "ON" : "OFF");
return change;
}
static int sma1303_postscaler_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
int val, ret;
ret = sma1303_regmap_read(sma1303, SMA1303_90_POSTSCALER, &val);
if (ret < 0)
return -EINVAL;
ucontrol->value.integer.value[0] = (val & 0x7E) >> 1;
return 0;
}
static int sma1303_postscaler_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
int ret, val = (int)ucontrol->value.integer.value[0];
bool change;
ret = sma1303_regmap_update_bits(sma1303,
SMA1303_90_POSTSCALER, 0x7E, (val << 1), &change);
if (ret < 0)
return -EINVAL;
return change;
}
static int sma1303_tdm_slot_rx_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
int val, ret;
ret = sma1303_regmap_read(sma1303, SMA1303_A5_TDM1, &val);
if (ret < 0)
return -EINVAL;
ucontrol->value.integer.value[0] = (val & 0x38) >> 3;
sma1303->tdm_slot_rx = ucontrol->value.integer.value[0];
return 0;
}
static int sma1303_tdm_slot_rx_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
int ret, val = (int)ucontrol->value.integer.value[0];
bool change;
ret = sma1303_regmap_update_bits(sma1303,
SMA1303_A5_TDM1, 0x38, (val << 3), &change);
if (ret < 0)
return -EINVAL;
return change;
}
static int sma1303_tdm_slot_tx_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
int val, ret;
ret = sma1303_regmap_read(sma1303, SMA1303_A6_TDM2, &val);
if (ret < 0)
return -EINVAL;
ucontrol->value.integer.value[0] = (val & 0x38) >> 3;
sma1303->tdm_slot_tx = ucontrol->value.integer.value[0];
return 0;
}
static int sma1303_tdm_slot_tx_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
int ret, val = (int)ucontrol->value.integer.value[0];
bool change;
ret = sma1303_regmap_update_bits(sma1303,
SMA1303_A6_TDM2, 0x38, (val << 3), &change);
if (ret < 0)
return -EINVAL;
return change;
}
static int sma1303_startup(struct snd_soc_component *component)
{
struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
bool change = false, temp = false;
sma1303_regmap_update_bits(sma1303, SMA1303_8E_PLL_CTRL,
SMA1303_PLL_PD2_MASK, SMA1303_PLL_OPERATION2, &temp);
if (temp == true)
change = true;
sma1303_regmap_update_bits(sma1303, SMA1303_00_SYSTEM_CTRL,
SMA1303_POWER_MASK, SMA1303_POWER_ON, &temp);
if (temp == true)
change = true;
if (sma1303->amp_mode == SMA1303_MONO) {
sma1303_regmap_update_bits(sma1303,
SMA1303_10_SYSTEM_CTRL1,
SMA1303_SPK_MODE_MASK,
SMA1303_SPK_MONO,
&temp);
if (temp == true)
change = true;
} else {
sma1303_regmap_update_bits(sma1303,
SMA1303_10_SYSTEM_CTRL1,
SMA1303_SPK_MODE_MASK,
SMA1303_SPK_STEREO,
&temp);
if (temp == true)
change = true;
}
if (sma1303->check_fault_status) {
if (sma1303->check_fault_period > 0)
queue_delayed_work(system_freezable_wq,
&sma1303->check_fault_work,
sma1303->check_fault_period * HZ);
else
queue_delayed_work(system_freezable_wq,
&sma1303->check_fault_work,
CHECK_PERIOD_TIME * HZ);
}
sma1303->amp_power_status = true;
return change;
}
static int sma1303_shutdown(struct snd_soc_component *component)
{
struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
bool change = false, temp = false;
cancel_delayed_work_sync(&sma1303->check_fault_work);
sma1303_regmap_update_bits(sma1303, SMA1303_10_SYSTEM_CTRL1,
SMA1303_SPK_MODE_MASK, SMA1303_SPK_OFF, &temp);
if (temp == true)
change = true;
sma1303_regmap_update_bits(sma1303, SMA1303_00_SYSTEM_CTRL,
SMA1303_POWER_MASK, SMA1303_POWER_OFF, &temp);
if (temp == true)
change = true;
sma1303_regmap_update_bits(sma1303, SMA1303_8E_PLL_CTRL,
SMA1303_PLL_PD2_MASK, SMA1303_PLL_PD2, &temp);
if (temp == true)
change = true;
sma1303->amp_power_status = false;
return change;
}
static int sma1303_aif_in_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
int ret = 0;
bool change = false, temp = false;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
switch (mux) {
case 0:
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_11_SYSTEM_CTRL2,
SMA1303_MONOMIX_MASK,
SMA1303_MONOMIX_ON,
&change);
sma1303->amp_mode = SMA1303_MONO;
break;
case 1:
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_11_SYSTEM_CTRL2,
SMA1303_MONOMIX_MASK,
SMA1303_MONOMIX_OFF,
&temp);
if (temp == true)
change = true;
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_11_SYSTEM_CTRL2,
SMA1303_LR_DATA_SW_MASK,
SMA1303_LR_DATA_SW_NORMAL,
&temp);
if (temp == true)
change = true;
sma1303->amp_mode = SMA1303_STEREO;
break;
case 2:
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_11_SYSTEM_CTRL2,
SMA1303_MONOMIX_MASK,
SMA1303_MONOMIX_OFF,
&temp);
if (temp == true)
change = true;
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_11_SYSTEM_CTRL2,
SMA1303_LR_DATA_SW_MASK,
SMA1303_LR_DATA_SW_SWAP,
&temp);
if (temp == true)
change = true;
sma1303->amp_mode = SMA1303_STEREO;
break;
default:
dev_err(sma1303->dev, "%s : Invalid value (%d)\n",
__func__, mux);
return -EINVAL;
}
dev_dbg(sma1303->dev, "%s : Source : %s\n", __func__,
sma1303_aif_in_source_text[mux]);
break;
}
if (ret < 0)
return -EINVAL;
return change;
}
static int sma1303_aif_out_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
int ret = 0;
bool change = false, temp = false;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
switch (mux) {
case 0:
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_A3_TOP_MAN2,
SMA1303_TEST_CLKO_EN_MASK,
SMA1303_NORMAL_SDO,
&temp);
if (temp == true)
change = true;
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_09_OUTPUT_CTRL,
SMA1303_PORT_OUT_SEL_MASK,
SMA1303_OUT_SEL_DISABLE,
&temp);
if (temp == true)
change = true;
break;
case 1:
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_A3_TOP_MAN2,
SMA1303_TEST_CLKO_EN_MASK,
SMA1303_NORMAL_SDO,
&temp);
if (temp == true)
change = true;
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_09_OUTPUT_CTRL,
SMA1303_PORT_OUT_SEL_MASK,
SMA1303_FORMAT_CONVERTER,
&temp);
if (temp == true)
change = true;
break;
case 2:
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_A3_TOP_MAN2,
SMA1303_TEST_CLKO_EN_MASK,
SMA1303_NORMAL_SDO,
&temp);
if (temp == true)
change = true;
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_09_OUTPUT_CTRL,
SMA1303_PORT_OUT_SEL_MASK,
SMA1303_MIXER_OUTPUT,
&temp);
if (temp == true)
change = true;
break;
case 3:
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_A3_TOP_MAN2,
SMA1303_TEST_CLKO_EN_MASK,
SMA1303_NORMAL_SDO,
&temp);
if (temp == true)
change = true;
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_09_OUTPUT_CTRL,
SMA1303_PORT_OUT_SEL_MASK,
SMA1303_SPEAKER_PATH,
&temp);
if (temp == true)
change = true;
break;
case 4:
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_A3_TOP_MAN2,
SMA1303_TEST_CLKO_EN_MASK,
SMA1303_NORMAL_SDO,
&temp);
if (temp == true)
change = true;
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_09_OUTPUT_CTRL,
SMA1303_PORT_OUT_SEL_MASK,
SMA1303_POSTSCALER_OUTPUT,
&temp);
if (temp == true)
change = true;
break;
case 5:
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_A3_TOP_MAN2,
SMA1303_TEST_CLKO_EN_MASK,
SMA1303_CLK_OUT_SDO,
&temp);
if (temp == true)
change = true;
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_A3_TOP_MAN2,
SMA1303_MON_OSC_PLL_MASK,
SMA1303_PLL_SDO,
&temp);
if (temp == true)
change = true;
break;
case 6:
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_A3_TOP_MAN2,
SMA1303_TEST_CLKO_EN_MASK,
SMA1303_CLK_OUT_SDO,
&temp);
if (temp == true)
change = true;
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_A3_TOP_MAN2,
SMA1303_MON_OSC_PLL_MASK,
SMA1303_OSC_SDO,
&temp);
if (temp == true)
change = true;
break;
default:
dev_err(sma1303->dev, "%s : Invalid value (%d)\n",
__func__, mux);
return -EINVAL;
}
dev_dbg(sma1303->dev, "%s : Source : %s\n", __func__,
sma1303_aif_out_source_text[mux]);
break;
}
if (ret < 0)
return -EINVAL;
return change;
}
static int sma1303_sdo_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
int ret = 0;
bool change = false, temp = false;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
dev_dbg(sma1303->dev,
"%s : SND_SOC_DAPM_PRE_PMU\n", __func__);
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_09_OUTPUT_CTRL,
SMA1303_PORT_CONFIG_MASK,
SMA1303_OUTPUT_PORT_ENABLE,
&temp);
if (temp == true)
change = true;
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_A3_TOP_MAN2,
SMA1303_SDO_OUTPUT_MASK,
SMA1303_NORMAL_OUT,
&temp);
if (temp == true)
change = true;
break;
case SND_SOC_DAPM_POST_PMD:
dev_dbg(sma1303->dev,
"%s : SND_SOC_DAPM_POST_PMD\n", __func__);
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_09_OUTPUT_CTRL,
SMA1303_PORT_CONFIG_MASK,
SMA1303_INPUT_PORT_ONLY,
&temp);
if (temp == true)
change = true;
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_A3_TOP_MAN2,
SMA1303_SDO_OUTPUT_MASK,
SMA1303_HIGH_Z_OUT,
&temp);
if (temp == true)
change = true;
break;
}
if (ret < 0)
return -EINVAL;
return change;
}
static int sma1303_post_scaler_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
int ret = 0;
bool change = false;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
dev_dbg(sma1303->dev,
"%s : SND_SOC_DAPM_PRE_PMU\n", __func__);
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_90_POSTSCALER,
SMA1303_BYP_POST_MASK,
SMA1303_EN_POST_SCALER,
&change);
break;
case SND_SOC_DAPM_POST_PMD:
dev_dbg(sma1303->dev,
"%s : SND_SOC_DAPM_POST_PMD\n", __func__);
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_90_POSTSCALER,
SMA1303_BYP_POST_MASK,
SMA1303_BYP_POST_SCALER,
&change);
break;
}
if (ret < 0)
return -EINVAL;
return change;
}
static int sma1303_power_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
int ret = 0;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
dev_dbg(sma1303->dev,
"%s : SND_SOC_DAPM_POST_PMU\n", __func__);
ret = sma1303_startup(component);
break;
case SND_SOC_DAPM_PRE_PMD:
dev_dbg(sma1303->dev,
"%s : SND_SOC_DAPM_PRE_PMD\n", __func__);
ret = sma1303_shutdown(component);
break;
}
return ret;
}
static const struct snd_kcontrol_new sma1303_aif_in_source_control =
SOC_DAPM_ENUM("AIF IN Source", sma1303_aif_in_source_enum);
static const struct snd_kcontrol_new sma1303_aif_out_source_control =
SOC_DAPM_ENUM("AIF OUT Source", sma1303_aif_out_source_enum);
static const struct snd_kcontrol_new sma1303_sdo_control =
SOC_DAPM_SINGLE_VIRT("Switch", 1);
static const struct snd_kcontrol_new sma1303_post_scaler_control =
SOC_DAPM_SINGLE_VIRT("Switch", 1);
static const struct snd_kcontrol_new sma1303_enable_control =
SOC_DAPM_SINGLE_VIRT("Switch", 1);
static const struct snd_kcontrol_new sma1303_snd_controls[] = {
SOC_SINGLE_TLV("Speaker Volume", SMA1303_0A_SPK_VOL,
0, 167, 1, sma1303_spk_tlv),
SOC_SINGLE_BOOL_EXT("Force Mute Switch", 0,
sma1303_force_mute_get, sma1303_force_mute_put),
SOC_SINGLE_EXT("Postscaler Gain", SMA1303_90_POSTSCALER, 1, 0x30, 0,
sma1303_postscaler_get, sma1303_postscaler_put),
SOC_ENUM_EXT("TDM RX Slot Position", sma1303_tdm_slot_enum,
sma1303_tdm_slot_rx_get, sma1303_tdm_slot_rx_put),
SOC_ENUM_EXT("TDM TX Slot Position", sma1303_tdm_slot_enum,
sma1303_tdm_slot_tx_get, sma1303_tdm_slot_tx_put),
};
static const struct snd_soc_dapm_widget sma1303_dapm_widgets[] = {
/* platform domain */
SND_SOC_DAPM_OUTPUT("SPK"),
SND_SOC_DAPM_INPUT("SDO"),
/* path domain */
SND_SOC_DAPM_MUX_E("AIF IN Source", SND_SOC_NOPM, 0, 0,
&sma1303_aif_in_source_control,
sma1303_aif_in_event,
SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_MUX_E("AIF OUT Source", SND_SOC_NOPM, 0, 0,
&sma1303_aif_out_source_control,
sma1303_aif_out_event,
SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_SWITCH_E("SDO Enable", SND_SOC_NOPM, 0, 0,
&sma1303_sdo_control,
sma1303_sdo_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER("Entry", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SWITCH_E("Post Scaler", SND_SOC_NOPM, 0, 1,
&sma1303_post_scaler_control,
sma1303_post_scaler_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_OUT_DRV_E("AMP Power", SND_SOC_NOPM, 0, 0, NULL, 0,
sma1303_power_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SWITCH("AMP Enable", SND_SOC_NOPM, 0, 1,
&sma1303_enable_control),
/* stream domain */
SND_SOC_DAPM_AIF_IN("AIF IN", "Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF OUT", "Capture", 0, SND_SOC_NOPM, 0, 0),
};
static const struct snd_soc_dapm_route sma1303_audio_map[] = {
/* Playback */
{"AIF IN Source", "Mono", "AIF IN"},
{"AIF IN Source", "Left", "AIF IN"},
{"AIF IN Source", "Right", "AIF IN"},
{"SDO Enable", "Switch", "AIF IN"},
{"AIF OUT Source", "Disable", "SDO Enable"},
{"AIF OUT Source", "After_FmtC", "SDO Enable"},
{"AIF OUT Source", "After_Mixer", "SDO Enable"},
{"AIF OUT Source", "After_DSP", "SDO Enable"},
{"AIF OUT Source", "After_Post", "SDO Enable"},
{"AIF OUT Source", "Clk_PLL", "SDO Enable"},
{"AIF OUT Source", "Clk_OSC", "SDO Enable"},
{"Entry", NULL, "AIF OUT Source"},
{"Entry", NULL, "AIF IN Source"},
{"Post Scaler", "Switch", "Entry"},
{"AMP Power", NULL, "Entry"},
{"AMP Power", NULL, "Entry"},
{"AMP Enable", "Switch", "AMP Power"},
{"SPK", NULL, "AMP Enable"},
/* Capture */
{"AIF OUT", NULL, "AMP Enable"},
};
static int sma1303_setup_pll(struct snd_soc_component *component,
unsigned int bclk)
{
struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
int i = 0, ret = 0;
dev_dbg(component->dev, "%s : BCLK = %dHz\n",
__func__, bclk);
if (sma1303->sys_clk_id == SMA1303_PLL_CLKIN_MCLK) {
dev_dbg(component->dev, "%s : MCLK is not supported\n",
__func__);
} else if (sma1303->sys_clk_id == SMA1303_PLL_CLKIN_BCLK) {
for (i = 0; i < sma1303->num_of_pll_matches; i++) {
if (sma1303->pll_matches[i].input_clk == bclk)
break;
}
if (i == sma1303->num_of_pll_matches) {
dev_dbg(component->dev, "%s : No matching value between pll table and SCK\n",
__func__);
return -EINVAL;
}
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_A2_TOP_MAN1,
SMA1303_PLL_PD_MASK|SMA1303_PLL_REF_CLK_MASK,
SMA1303_PLL_OPERATION|SMA1303_PLL_SCK,
NULL);
}
ret += sma1303_regmap_write(sma1303,
SMA1303_8B_PLL_POST_N,
sma1303->pll_matches[i].post_n);
ret += sma1303_regmap_write(sma1303,
SMA1303_8C_PLL_N,
sma1303->pll_matches[i].n);
ret += sma1303_regmap_write(sma1303,
SMA1303_8D_PLL_A_SETTING,
sma1303->pll_matches[i].vco);
ret += sma1303_regmap_write(sma1303,
SMA1303_8F_PLL_P_CP,
sma1303->pll_matches[i].p_cp);
if (ret < 0)
return -EINVAL;
return 0;
}
static int sma1303_dai_hw_params_amp(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
unsigned int bclk = 0;
int ret = 0;
if (sma1303->format == SND_SOC_DAIFMT_DSP_A)
bclk = params_rate(params) * sma1303->frame_size;
else
bclk = params_rate(params) * params_physical_width(params)
* params_channels(params);
dev_dbg(component->dev,
"%s : rate = %d : bit size = %d : channel = %d\n",
__func__, params_rate(params), params_width(params),
params_channels(params));
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
if (sma1303->sys_clk_id == SMA1303_PLL_CLKIN_BCLK) {
if (sma1303->last_bclk != bclk) {
sma1303_setup_pll(component, bclk);
sma1303->last_bclk = bclk;
}
}
switch (params_rate(params)) {
case 8000:
case 12000:
case 16000:
case 24000:
case 32000:
case 44100:
case 48000:
case 96000:
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_A2_TOP_MAN1,
SMA1303_DAC_DN_CONV_MASK,
SMA1303_DAC_DN_CONV_DISABLE,
NULL);
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_01_INPUT1_CTRL1,
SMA1303_LEFTPOL_MASK,
SMA1303_LOW_FIRST_CH,
NULL);
break;
case 192000:
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_A2_TOP_MAN1,
SMA1303_DAC_DN_CONV_MASK,
SMA1303_DAC_DN_CONV_ENABLE,
NULL);
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_01_INPUT1_CTRL1,
SMA1303_LEFTPOL_MASK,
SMA1303_HIGH_FIRST_CH,
NULL);
break;
default:
dev_err(component->dev, "%s not support rate : %d\n",
__func__, params_rate(params));
return -EINVAL;
}
} else {
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
dev_dbg(component->dev,
"%s set format SNDRV_PCM_FORMAT_S16_LE\n",
__func__);
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_A4_TOP_MAN3,
SMA1303_SCK_RATE_MASK,
SMA1303_SCK_32FS,
NULL);
break;
case SNDRV_PCM_FORMAT_S24_LE:
dev_dbg(component->dev,
"%s set format SNDRV_PCM_FORMAT_S24_LE\n",
__func__);
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_A4_TOP_MAN3,
SMA1303_SCK_RATE_MASK,
SMA1303_SCK_64FS,
NULL);
break;
case SNDRV_PCM_FORMAT_S32_LE:
dev_dbg(component->dev,
"%s set format SNDRV_PCM_FORMAT_S32_LE\n",
__func__);
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_A4_TOP_MAN3,
SMA1303_SCK_RATE_MASK,
SMA1303_SCK_64FS,
NULL);
break;
default:
dev_err(component->dev,
"%s not support data bit : %d\n", __func__,
params_format(params));
return -EINVAL;
}
}
switch (sma1303->format) {
case SND_SOC_DAIFMT_I2S:
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_01_INPUT1_CTRL1,
SMA1303_I2S_MODE_MASK,
SMA1303_STANDARD_I2S,
NULL);
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_A4_TOP_MAN3,
SMA1303_O_FORMAT_MASK,
SMA1303_O_FMT_I2S,
NULL);
break;
case SND_SOC_DAIFMT_LEFT_J:
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_01_INPUT1_CTRL1,
SMA1303_I2S_MODE_MASK,
SMA1303_LJ,
NULL);
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_A4_TOP_MAN3,
SMA1303_O_FORMAT_MASK,
SMA1303_O_FMT_LJ,
NULL);
break;
case SND_SOC_DAIFMT_RIGHT_J:
switch (params_width(params)) {
case 16:
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_01_INPUT1_CTRL1,
SMA1303_I2S_MODE_MASK,
SMA1303_RJ_16BIT,
NULL);
break;
case 24:
case 32:
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_01_INPUT1_CTRL1,
SMA1303_I2S_MODE_MASK,
SMA1303_RJ_24BIT,
NULL);
break;
}
break;
case SND_SOC_DAIFMT_DSP_A:
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_01_INPUT1_CTRL1,
SMA1303_I2S_MODE_MASK,
SMA1303_STANDARD_I2S,
NULL);
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_A4_TOP_MAN3,
SMA1303_O_FORMAT_MASK,
SMA1303_O_FMT_TDM,
NULL);
break;
}
switch (params_width(params)) {
case 16:
case 24:
case 32:
break;
default:
dev_err(component->dev,
"%s not support data bit : %d\n", __func__,
params_format(params));
return -EINVAL;
}
if (ret < 0)
return -EINVAL;
return 0;
}
static int sma1303_dai_set_sysclk_amp(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
switch (clk_id) {
case SMA1303_EXTERNAL_CLOCK_19_2:
break;
case SMA1303_EXTERNAL_CLOCK_24_576:
break;
case SMA1303_PLL_CLKIN_MCLK:
break;
case SMA1303_PLL_CLKIN_BCLK:
break;
default:
dev_err(component->dev, "Invalid clk id: %d\n", clk_id);
return -EINVAL;
}
sma1303->sys_clk_id = clk_id;
return 0;
}
static int sma1303_dai_mute(struct snd_soc_dai *dai, int mute, int stream)
{
struct snd_soc_component *component = dai->component;
struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
int ret = 0;
if (stream == SNDRV_PCM_STREAM_CAPTURE)
return ret;
if (mute) {
dev_dbg(component->dev, "%s : %s\n", __func__, "MUTE");
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_0E_MUTE_VOL_CTRL,
SMA1303_SPK_MUTE_MASK,
SMA1303_SPK_MUTE,
NULL);
/* Need to wait time for mute slope */
msleep(55);
} else {
if (!sma1303->force_mute_status) {
dev_dbg(component->dev, "%s : %s\n",
__func__, "UNMUTE");
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_0E_MUTE_VOL_CTRL,
SMA1303_SPK_MUTE_MASK,
SMA1303_SPK_UNMUTE,
NULL);
} else {
dev_dbg(sma1303->dev,
"%s : FORCE MUTE!!!\n", __func__);
}
}
if (ret < 0)
return -EINVAL;
return 0;
}
static int sma1303_dai_set_fmt_amp(struct snd_soc_dai *dai,
unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
int ret = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC:
dev_dbg(component->dev,
"%s : %s\n", __func__, "I2S/TDM Device mode");
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_01_INPUT1_CTRL1,
SMA1303_CONTROLLER_DEVICE_MASK,
SMA1303_DEVICE_MODE,
NULL);
break;
case SND_SOC_DAIFMT_CBP_CFP:
dev_dbg(component->dev,
"%s : %s\n", __func__, "I2S/TDM Controller mode");
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_01_INPUT1_CTRL1,
SMA1303_CONTROLLER_DEVICE_MASK,
SMA1303_CONTROLLER_MODE,
NULL);
break;
default:
dev_err(component->dev,
"Unsupported Controller/Device : 0x%x\n", fmt);
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_RIGHT_J:
case SND_SOC_DAIFMT_LEFT_J:
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B:
sma1303->format = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
break;
default:
dev_err(component->dev,
"Unsupported Audio Interface Format : 0x%x\n", fmt);
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_IB_NF:
dev_dbg(component->dev, "%s : %s\n",
__func__, "Invert BCLK + Normal Frame");
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_01_INPUT1_CTRL1,
SMA1303_SCK_RISING_MASK,
SMA1303_SCK_RISING_EDGE,
NULL);
break;
case SND_SOC_DAIFMT_IB_IF:
dev_dbg(component->dev, "%s : %s\n",
__func__, "Invert BCLK + Invert Frame");
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_01_INPUT1_CTRL1,
SMA1303_LEFTPOL_MASK|SMA1303_SCK_RISING_MASK,
SMA1303_HIGH_FIRST_CH|SMA1303_SCK_RISING_EDGE,
NULL);
break;
case SND_SOC_DAIFMT_NB_IF:
dev_dbg(component->dev, "%s : %s\n",
__func__, "Normal BCLK + Invert Frame");
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_01_INPUT1_CTRL1,
SMA1303_LEFTPOL_MASK,
SMA1303_HIGH_FIRST_CH,
NULL);
break;
case SND_SOC_DAIFMT_NB_NF:
dev_dbg(component->dev, "%s : %s\n",
__func__, "Normal BCLK + Normal Frame");
break;
default:
dev_err(component->dev,
"Unsupported Bit & Frameclock : 0x%x\n", fmt);
return -EINVAL;
}
if (ret < 0)
return -EINVAL;
return 0;
}
static int sma1303_dai_set_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask,
int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
int ret = 0;
dev_dbg(component->dev, "%s : slots = %d, slot_width - %d\n",
__func__, slots, slot_width);
sma1303->frame_size = slot_width * slots;
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_A4_TOP_MAN3,
SMA1303_O_FORMAT_MASK,
SMA1303_O_FMT_TDM,
NULL);
switch (slot_width) {
case 16:
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_A6_TDM2,
SMA1303_TDM_DL_MASK,
SMA1303_TDM_DL_16,
NULL);
break;
case 32:
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_A6_TDM2,
SMA1303_TDM_DL_MASK,
SMA1303_TDM_DL_32,
NULL);
break;
default:
dev_err(component->dev, "%s not support TDM %d slot_width\n",
__func__, slot_width);
break;
}
switch (slots) {
case 4:
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_A6_TDM2,
SMA1303_TDM_N_SLOT_MASK,
SMA1303_TDM_N_SLOT_4,
NULL);
break;
case 8:
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_A6_TDM2,
SMA1303_TDM_N_SLOT_MASK,
SMA1303_TDM_N_SLOT_8,
NULL);
break;
default:
dev_err(component->dev, "%s not support TDM %d slots\n",
__func__, slots);
break;
}
if (sma1303->tdm_slot_rx < slots)
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_A5_TDM1,
SMA1303_TDM_SLOT1_RX_POS_MASK,
(sma1303->tdm_slot_rx) << 3,
NULL);
else
dev_err(component->dev, "%s Incorrect tdm-slot-rx %d set\n",
__func__, sma1303->tdm_slot_rx);
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_A5_TDM1,
SMA1303_TDM_CLK_POL_MASK,
SMA1303_TDM_CLK_POL_RISE,
NULL);
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_A5_TDM1,
SMA1303_TDM_TX_MODE_MASK,
SMA1303_TDM_TX_MONO,
NULL);
if (sma1303->tdm_slot_tx < slots)
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_A6_TDM2,
SMA1303_TDM_SLOT1_TX_POS_MASK,
(sma1303->tdm_slot_tx) << 3,
NULL);
else
dev_err(component->dev, "%s Incorrect tdm-slot-tx %d set\n",
__func__, sma1303->tdm_slot_tx);
if (ret < 0)
return -EINVAL;
return 0;
}
static const struct snd_soc_dai_ops sma1303_dai_ops_amp = {
.set_sysclk = sma1303_dai_set_sysclk_amp,
.set_fmt = sma1303_dai_set_fmt_amp,
.hw_params = sma1303_dai_hw_params_amp,
.mute_stream = sma1303_dai_mute,
.set_tdm_slot = sma1303_dai_set_tdm_slot,
};
#define SMA1303_RATES SNDRV_PCM_RATE_8000_192000
#define SMA1303_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver sma1303_dai[] = {
{
.name = "sma1303-amplifier",
.id = 0,
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SMA1303_RATES,
.formats = SMA1303_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SMA1303_RATES,
.formats = SMA1303_FORMATS,
},
.ops = &sma1303_dai_ops_amp,
},
};
static void sma1303_check_fault_worker(struct work_struct *work)
{
struct sma1303_priv *sma1303 =
container_of(work, struct sma1303_priv, check_fault_work.work);
int ret = 0;
unsigned int over_temp, ocp_val, uvlo_val;
if (sma1303->tsdw_cnt)
ret = sma1303_regmap_read(sma1303,
SMA1303_0A_SPK_VOL, &sma1303->cur_vol);
else
ret = sma1303_regmap_read(sma1303,
SMA1303_0A_SPK_VOL, &sma1303->init_vol);
if (ret != 0) {
dev_err(sma1303->dev,
"failed to read SMA1303_0A_SPK_VOL : %d\n", ret);
return;
}
ret = sma1303_regmap_read(sma1303, SMA1303_FA_STATUS1, &over_temp);
if (ret != 0) {
dev_err(sma1303->dev,
"failed to read SMA1303_FA_STATUS1 : %d\n", ret);
return;
}
ret = sma1303_regmap_read(sma1303, SMA1303_FB_STATUS2, &ocp_val);
if (ret != 0) {
dev_err(sma1303->dev,
"failed to read SMA1303_FB_STATUS2 : %d\n", ret);
return;
}
ret = sma1303_regmap_read(sma1303, SMA1303_FF_DEVICE_INDEX, &uvlo_val);
if (ret != 0) {
dev_err(sma1303->dev,
"failed to read SMA1303_FF_DEVICE_INDEX : %d\n", ret);
return;
}
if (~over_temp & SMA1303_OT1_OK_STATUS) {
dev_crit(sma1303->dev,
"%s : OT1(Over Temperature Level 1)\n", __func__);
if ((sma1303->cur_vol + 6) <= 0xFF)
sma1303_regmap_write(sma1303,
SMA1303_0A_SPK_VOL, sma1303->cur_vol + 6);
sma1303->tsdw_cnt++;
} else if (sma1303->tsdw_cnt) {
sma1303_regmap_write(sma1303,
SMA1303_0A_SPK_VOL, sma1303->init_vol);
sma1303->tsdw_cnt = 0;
sma1303->cur_vol = sma1303->init_vol;
}
if (~over_temp & SMA1303_OT2_OK_STATUS) {
dev_crit(sma1303->dev,
"%s : OT2(Over Temperature Level 2)\n", __func__);
}
if (ocp_val & SMA1303_OCP_SPK_STATUS) {
dev_crit(sma1303->dev,
"%s : OCP_SPK(Over Current Protect SPK)\n", __func__);
}
if (ocp_val & SMA1303_OCP_BST_STATUS) {
dev_crit(sma1303->dev,
"%s : OCP_BST(Over Current Protect Boost)\n", __func__);
}
if ((ocp_val & SMA1303_CLK_MON_STATUS) && (sma1303->amp_power_status)) {
dev_crit(sma1303->dev,
"%s : CLK_FAULT(No clock input)\n", __func__);
}
if (uvlo_val & SMA1303_UVLO_BST_STATUS) {
dev_crit(sma1303->dev,
"%s : UVLO(Under Voltage Lock Out)\n", __func__);
}
if ((over_temp != sma1303->last_over_temp) ||
(ocp_val != sma1303->last_ocp_val)) {
dev_crit(sma1303->dev, "Please check AMP status");
dev_dbg(sma1303->dev, "STATUS1=0x%02X : STATUS2=0x%02X\n",
over_temp, ocp_val);
sma1303->last_over_temp = over_temp;
sma1303->last_ocp_val = ocp_val;
}
if (sma1303->check_fault_status) {
if (sma1303->check_fault_period > 0)
queue_delayed_work(system_freezable_wq,
&sma1303->check_fault_work,
sma1303->check_fault_period * HZ);
else
queue_delayed_work(system_freezable_wq,
&sma1303->check_fault_work,
CHECK_PERIOD_TIME * HZ);
}
if (!(~over_temp & SMA1303_OT1_OK_STATUS)
&& !(~over_temp & SMA1303_OT2_OK_STATUS)
&& !(ocp_val & SMA1303_OCP_SPK_STATUS)
&& !(ocp_val & SMA1303_OCP_BST_STATUS)
&& !(ocp_val & SMA1303_CLK_MON_STATUS)
&& !(uvlo_val & SMA1303_UVLO_BST_STATUS)) {
}
}
static int sma1303_probe(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm =
snd_soc_component_get_dapm(component);
snd_soc_dapm_sync(dapm);
return 0;
}
static void sma1303_remove(struct snd_soc_component *component)
{
struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
cancel_delayed_work_sync(&sma1303->check_fault_work);
}
static const struct snd_soc_component_driver sma1303_component = {
.probe = sma1303_probe,
.remove = sma1303_remove,
.controls = sma1303_snd_controls,
.num_controls = ARRAY_SIZE(sma1303_snd_controls),
.dapm_widgets = sma1303_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(sma1303_dapm_widgets),
.dapm_routes = sma1303_audio_map,
.num_dapm_routes = ARRAY_SIZE(sma1303_audio_map),
};
static const struct regmap_config sma_i2c_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = SMA1303_FF_DEVICE_INDEX,
.readable_reg = sma1303_readable_register,
.writeable_reg = sma1303_writeable_register,
.volatile_reg = sma1303_volatile_register,
.cache_type = REGCACHE_NONE,
.reg_defaults = sma1303_reg_def,
.num_reg_defaults = ARRAY_SIZE(sma1303_reg_def),
};
static ssize_t check_fault_period_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sma1303_priv *sma1303 = dev_get_drvdata(dev);
return sysfs_emit(buf, "%ld\n", sma1303->check_fault_period);
}
static ssize_t check_fault_period_store(struct device *dev,
struct device_attribute *devattr, const char *buf, size_t count)
{
struct sma1303_priv *sma1303 = dev_get_drvdata(dev);
int ret;
ret = kstrtol(buf, 10, &sma1303->check_fault_period);
if (ret)
return -EINVAL;
return (ssize_t)count;
}
static DEVICE_ATTR_RW(check_fault_period);
static ssize_t check_fault_status_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sma1303_priv *sma1303 = dev_get_drvdata(dev);
return sysfs_emit(buf, "%ld\n", sma1303->check_fault_status);
}
static ssize_t check_fault_status_store(struct device *dev,
struct device_attribute *devattr, const char *buf, size_t count)
{
struct sma1303_priv *sma1303 = dev_get_drvdata(dev);
int ret;
ret = kstrtol(buf, 10, &sma1303->check_fault_status);
if (ret)
return -EINVAL;
if (sma1303->check_fault_status) {
if (sma1303->check_fault_period > 0)
queue_delayed_work(system_freezable_wq,
&sma1303->check_fault_work,
sma1303->check_fault_period * HZ);
else
queue_delayed_work(system_freezable_wq,
&sma1303->check_fault_work,
CHECK_PERIOD_TIME * HZ);
}
return (ssize_t)count;
}
static DEVICE_ATTR_RW(check_fault_status);
static struct attribute *sma1303_attr[] = {
&dev_attr_check_fault_period.attr,
&dev_attr_check_fault_status.attr,
NULL,
};
static struct attribute_group sma1303_attr_group = {
.attrs = sma1303_attr,
};
static int sma1303_i2c_probe(struct i2c_client *client)
{
struct sma1303_priv *sma1303;
int ret, i = 0;
unsigned int device_info, status, otp_stat;
sma1303 = devm_kzalloc(&client->dev,
sizeof(struct sma1303_priv), GFP_KERNEL);
if (!sma1303)
return -ENOMEM;
sma1303->dev = &client->dev;
sma1303->regmap = devm_regmap_init_i2c(client, &sma_i2c_regmap);
if (IS_ERR(sma1303->regmap)) {
ret = PTR_ERR(sma1303->regmap);
dev_err(&client->dev,
"Failed to allocate register map: %d\n", ret);
return ret;
}
ret = sma1303_regmap_read(sma1303,
SMA1303_FF_DEVICE_INDEX, &device_info);
if ((ret != 0) || ((device_info & 0xF8) != SMA1303_DEVICE_ID)) {
dev_err(&client->dev, "device initialization error (%d 0x%02X)",
ret, device_info);
}
dev_dbg(&client->dev, "chip version 0x%02X\n", device_info);
ret += sma1303_regmap_update_bits(sma1303,
SMA1303_00_SYSTEM_CTRL,
SMA1303_RESETBYI2C_MASK, SMA1303_RESETBYI2C_RESET,
NULL);
ret += sma1303_regmap_read(sma1303, SMA1303_FF_DEVICE_INDEX, &status);
sma1303->rev_num = status & SMA1303_REV_NUM_STATUS;
if (sma1303->rev_num == SMA1303_REV_NUM_TV0)
dev_dbg(&client->dev, "SMA1303 Trimming Version 0\n");
else if (sma1303->rev_num == SMA1303_REV_NUM_TV1)
dev_dbg(&client->dev, "SMA1303 Trimming Version 1\n");
ret += sma1303_regmap_read(sma1303, SMA1303_FB_STATUS2, &otp_stat);
if (ret < 0)
dev_err(&client->dev,
"failed to read, register: %02X, ret: %d\n",
SMA1303_FF_DEVICE_INDEX, ret);
if (((sma1303->rev_num == SMA1303_REV_NUM_TV0) &&
((otp_stat & 0x0E) == SMA1303_OTP_STAT_OK_0)) ||
((sma1303->rev_num != SMA1303_REV_NUM_TV0) &&
((otp_stat & 0x0C) == SMA1303_OTP_STAT_OK_1)))
dev_dbg(&client->dev, "SMA1303 OTP Status Successful\n");
else
dev_dbg(&client->dev, "SMA1303 OTP Status Fail\n");
for (i = 0; i < (unsigned int)ARRAY_SIZE(sma1303_reg_def); i++)
ret += sma1303_regmap_write(sma1303,
sma1303_reg_def[i].reg,
sma1303_reg_def[i].def);
sma1303->amp_mode = SMA1303_MONO;
sma1303->amp_power_status = false;
sma1303->check_fault_period = CHECK_PERIOD_TIME;
sma1303->check_fault_status = true;
sma1303->force_mute_status = false;
sma1303->init_vol = 0x31;
sma1303->cur_vol = sma1303->init_vol;
sma1303->last_bclk = 0;
sma1303->last_ocp_val = 0x08;
sma1303->last_over_temp = 0xC0;
sma1303->tsdw_cnt = 0;
sma1303->retry_cnt = SMA1303_I2C_RETRY_COUNT;
sma1303->tdm_slot_rx = 0;
sma1303->tdm_slot_tx = 0;
sma1303->sys_clk_id = SMA1303_PLL_CLKIN_BCLK;
sma1303->dev = &client->dev;
sma1303->kobj = &client->dev.kobj;
INIT_DELAYED_WORK(&sma1303->check_fault_work,
sma1303_check_fault_worker);
i2c_set_clientdata(client, sma1303);
sma1303->pll_matches = sma1303_pll_matches;
sma1303->num_of_pll_matches =
ARRAY_SIZE(sma1303_pll_matches);
ret = devm_snd_soc_register_component(&client->dev,
&sma1303_component, sma1303_dai, 1);
if (ret) {
dev_err(&client->dev, "Failed to register component");
return ret;
}
sma1303->attr_grp = &sma1303_attr_group;
ret = sysfs_create_group(sma1303->kobj, sma1303->attr_grp);
if (ret) {
dev_err(&client->dev,
"failed to create attribute group [%d]\n", ret);
sma1303->attr_grp = NULL;
}
return ret;
}
static void sma1303_i2c_remove(struct i2c_client *client)
{
struct sma1303_priv *sma1303 =
(struct sma1303_priv *) i2c_get_clientdata(client);
cancel_delayed_work_sync(&sma1303->check_fault_work);
}
static const struct i2c_device_id sma1303_i2c_id[] = {
{"sma1303", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, sma1303_i2c_id);
static const struct of_device_id sma1303_of_match[] = {
{ .compatible = "irondevice,sma1303", },
{ }
};
MODULE_DEVICE_TABLE(of, sma1303_of_match);
static struct i2c_driver sma1303_i2c_driver = {
.driver = {
.name = "sma1303",
.of_match_table = sma1303_of_match,
},
.probe = sma1303_i2c_probe,
.remove = sma1303_i2c_remove,
.id_table = sma1303_i2c_id,
};
module_i2c_driver(sma1303_i2c_driver);
MODULE_DESCRIPTION("ALSA SoC SMA1303 driver");
MODULE_AUTHOR("Gyuhwa Park, <[email protected]>");
MODULE_AUTHOR("Kiseok Jo, <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/sma1303.c |
// SPDX-License-Identifier: GPL-2.0
//
// ak4613.c -- Asahi Kasei ALSA Soc Audio driver
//
// Copyright (C) 2015 Renesas Electronics Corporation
// Kuninori Morimoto <[email protected]>
//
// Based on ak4642.c by Kuninori Morimoto
// Based on wm8731.c by Richard Purdie
// Based on ak4535.c by Richard Purdie
// Based on wm8753.c by Liam Girdwood
/*
* +-------+
* |AK4613 |
* SDTO1 <-| |
* | |
* SDTI1 ->| |
* SDTI2 ->| |
* SDTI3 ->| |
* +-------+
*
* +---+
* clk | |___________________________________________...
*
* [TDM512]
* SDTO1 [L1][R1][L2][R2]
* SDTI1 [L1][R1][L2][R2][L3][R3][L4][R4][L5][R5][L6][R6]
*
* [TDM256]
* SDTO1 [L1][R1][L2][R2]
* SDTI1 [L1][R1][L2][R2][L3][R3][L4][R4]
* SDTI2 [L5][R5][L6][R6]
*
* [TDM128]
* SDTO1 [L1][R1][L2][R2]
* SDTI1 [L1][R1][L2][R2]
* SDTI2 [L3][R3][L4][R4]
* SDTI3 [L5][R5][L6][R6]
*
* [STEREO]
* Playback 2ch : SDTI1
* Capture 2ch : SDTO1
*
* [TDM512]
* Playback 12ch : SDTI1
* Capture 4ch : SDTO1
*
* [TDM256]
* Playback 12ch : SDTI1 + SDTI2
* Playback 8ch : SDTI1
* Capture 4ch : SDTO1
*
* [TDM128]
* Playback 12ch : SDTI1 + SDTI2 + SDTI3
* Playback 8ch : SDTI1 + SDTI2
* Playback 4ch : SDTI1
* Capture 4ch : SDTO1
*
*
* !!! NOTE !!!
*
* Renesas is the only user of ak4613 on upstream so far,
* but the chip connection is like below.
* Thus, Renesas can't test all connection case.
* Tested TDM is very limited.
*
* +-----+ +-----------+
* | SoC | | AK4613 |
* | |<-----|SDTO1 IN1|<-- Mic
* | | | IN2|
* | | | |
* | |----->|SDTI1 OUT1|--> Headphone
* +-----+ |SDTI2 OUT2|
* |SDTI3 OUT3|
* | OUT4|
* | OUT5|
* | OUT6|
* +-----------+
*
* Renesas SoC can handle [2, 6,8] channels.
* Ak4613 can handle [2,4, 8,12] channels.
*
* Because of above HW connection and available channels number,
* Renesas could test are ...
*
* [STEREO] Playback 2ch : SDTI1
* Capture 2ch : SDTO1
* [TDM256] Playback 8ch : SDTI1 (*)
*
* (*) it used 8ch data between SoC <-> AK4613 on TDM256 mode,
* but could confirm is only first 2ch because only 1
* Headphone is connected.
*
* see
* AK4613_ENABLE_TDM_TEST
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/of_device.h>
#include <linux/of_graph.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include <sound/pcm_params.h>
#include <sound/tlv.h>
#define PW_MGMT1 0x00 /* Power Management 1 */
#define PW_MGMT2 0x01 /* Power Management 2 */
#define PW_MGMT3 0x02 /* Power Management 3 */
#define CTRL1 0x03 /* Control 1 */
#define CTRL2 0x04 /* Control 2 */
#define DEMP1 0x05 /* De-emphasis1 */
#define DEMP2 0x06 /* De-emphasis2 */
#define OFD 0x07 /* Overflow Detect */
#define ZRD 0x08 /* Zero Detect */
#define ICTRL 0x09 /* Input Control */
#define OCTRL 0x0a /* Output Control */
#define LOUT1 0x0b /* LOUT1 Volume Control */
#define ROUT1 0x0c /* ROUT1 Volume Control */
#define LOUT2 0x0d /* LOUT2 Volume Control */
#define ROUT2 0x0e /* ROUT2 Volume Control */
#define LOUT3 0x0f /* LOUT3 Volume Control */
#define ROUT3 0x10 /* ROUT3 Volume Control */
#define LOUT4 0x11 /* LOUT4 Volume Control */
#define ROUT4 0x12 /* ROUT4 Volume Control */
#define LOUT5 0x13 /* LOUT5 Volume Control */
#define ROUT5 0x14 /* ROUT5 Volume Control */
#define LOUT6 0x15 /* LOUT6 Volume Control */
#define ROUT6 0x16 /* ROUT6 Volume Control */
/* PW_MGMT1 */
#define RSTN BIT(0)
#define PMDAC BIT(1)
#define PMADC BIT(2)
#define PMVR BIT(3)
/* PW_MGMT2 */
#define PMAD_ALL 0x7
/* PW_MGMT3 */
#define PMDA_ALL 0x3f
/* CTRL1 */
#define DIF0 BIT(3)
#define DIF1 BIT(4)
#define DIF2 BIT(5)
#define TDM0 BIT(6)
#define TDM1 BIT(7)
#define NO_FMT (0xff)
#define FMT_MASK (0xf8)
/* CTRL2 */
#define DFS_MASK (3 << 2)
#define DFS_NORMAL_SPEED (0 << 2)
#define DFS_DOUBLE_SPEED (1 << 2)
#define DFS_QUAD_SPEED (2 << 2)
/* ICTRL */
#define ICTRL_MASK (0x3)
/* OCTRL */
#define OCTRL_MASK (0x3F)
/*
* configs
*
* 0x000000BA
*
* B : AK4613_CONFIG_SDTI_x
* A : AK4613_CONFIG_MODE_x
*/
#define AK4613_CONFIG_SET(priv, x) priv->configs |= AK4613_CONFIG_##x
#define AK4613_CONFIG_GET(priv, x) (priv->configs & AK4613_CONFIG_##x##_MASK)
/*
* AK4613_CONFIG_SDTI_x
*
* It indicates how many SDTIx is connected.
*/
#define AK4613_CONFIG_SDTI_MASK (0xF << 4)
#define AK4613_CONFIG_SDTI(x) (((x) & 0xF) << 4)
#define AK4613_CONFIG_SDTI_set(priv, x) AK4613_CONFIG_SET(priv, SDTI(x))
#define AK4613_CONFIG_SDTI_get(priv) ((AK4613_CONFIG_GET(priv, SDTI) >> 4) & 0xF)
/*
* AK4613_CONFIG_MODE_x
*
* Same as Ctrl1 :: TDM1/TDM0
* No shift is requested
* see
* AK4613_CTRL1_TO_MODE()
* Table 11/12/13/14
*/
#define AK4613_CONFIG_MODE_MASK (0xF)
#define AK4613_CONFIG_MODE_STEREO (0x0)
#define AK4613_CONFIG_MODE_TDM512 (0x1)
#define AK4613_CONFIG_MODE_TDM256 (0x2)
#define AK4613_CONFIG_MODE_TDM128 (0x3)
/*
* !!!! FIXME !!!!
*
* Because of testable HW limitation, TDM256 8ch TDM was only tested.
* This driver uses AK4613_ENABLE_TDM_TEST instead of new DT property so far.
* Don't hesitate to update driver, you don't need to care compatible
* with Renesas.
*
* #define AK4613_ENABLE_TDM_TEST
*/
struct ak4613_interface {
unsigned int width;
unsigned int fmt;
u8 dif;
};
struct ak4613_priv {
struct mutex lock;
struct snd_pcm_hw_constraint_list constraint_rates;
struct snd_pcm_hw_constraint_list constraint_channels;
struct work_struct dummy_write_work;
struct snd_soc_component *component;
unsigned int rate;
unsigned int sysclk;
unsigned int fmt;
unsigned int configs;
int cnt;
u8 ctrl1;
u8 oc;
u8 ic;
};
/*
* Playback Volume
*
* max : 0x00 : 0 dB
* ( 0.5 dB step )
* min : 0xFE : -127.0 dB
* mute: 0xFF
*/
static const DECLARE_TLV_DB_SCALE(out_tlv, -12750, 50, 1);
static const struct snd_kcontrol_new ak4613_snd_controls[] = {
SOC_DOUBLE_R_TLV("Digital Playback Volume1", LOUT1, ROUT1,
0, 0xFF, 1, out_tlv),
SOC_DOUBLE_R_TLV("Digital Playback Volume2", LOUT2, ROUT2,
0, 0xFF, 1, out_tlv),
SOC_DOUBLE_R_TLV("Digital Playback Volume3", LOUT3, ROUT3,
0, 0xFF, 1, out_tlv),
SOC_DOUBLE_R_TLV("Digital Playback Volume4", LOUT4, ROUT4,
0, 0xFF, 1, out_tlv),
SOC_DOUBLE_R_TLV("Digital Playback Volume5", LOUT5, ROUT5,
0, 0xFF, 1, out_tlv),
SOC_DOUBLE_R_TLV("Digital Playback Volume6", LOUT6, ROUT6,
0, 0xFF, 1, out_tlv),
};
static const struct reg_default ak4613_reg[] = {
{ 0x0, 0x0f }, { 0x1, 0x07 }, { 0x2, 0x3f }, { 0x3, 0x20 },
{ 0x4, 0x20 }, { 0x5, 0x55 }, { 0x6, 0x05 }, { 0x7, 0x07 },
{ 0x8, 0x0f }, { 0x9, 0x07 }, { 0xa, 0x3f }, { 0xb, 0x00 },
{ 0xc, 0x00 }, { 0xd, 0x00 }, { 0xe, 0x00 }, { 0xf, 0x00 },
{ 0x10, 0x00 }, { 0x11, 0x00 }, { 0x12, 0x00 }, { 0x13, 0x00 },
{ 0x14, 0x00 }, { 0x15, 0x00 }, { 0x16, 0x00 },
};
/*
* CTRL1 register
* see
* Table 11/12/13/14
*/
#define AUDIO_IFACE(_dif, _width, _fmt) \
{ \
.dif = _dif, \
.width = _width, \
.fmt = SND_SOC_DAIFMT_##_fmt,\
}
static const struct ak4613_interface ak4613_iface[] = {
/* It doesn't support asymmetric format */
AUDIO_IFACE(0x03, 24, LEFT_J),
AUDIO_IFACE(0x04, 24, I2S),
};
#define AK4613_CTRL1_TO_MODE(priv) ((priv)->ctrl1 >> 6) /* AK4613_CONFIG_MODE_x */
static const struct regmap_config ak4613_regmap_cfg = {
.reg_bits = 8,
.val_bits = 8,
.max_register = 0x16,
.reg_defaults = ak4613_reg,
.num_reg_defaults = ARRAY_SIZE(ak4613_reg),
.cache_type = REGCACHE_RBTREE,
};
static const struct of_device_id ak4613_of_match[] = {
{ .compatible = "asahi-kasei,ak4613", .data = &ak4613_regmap_cfg },
{},
};
MODULE_DEVICE_TABLE(of, ak4613_of_match);
static const struct i2c_device_id ak4613_i2c_id[] = {
{ "ak4613", (kernel_ulong_t)&ak4613_regmap_cfg },
{ }
};
MODULE_DEVICE_TABLE(i2c, ak4613_i2c_id);
static const struct snd_soc_dapm_widget ak4613_dapm_widgets[] = {
/* Outputs */
SND_SOC_DAPM_OUTPUT("LOUT1"),
SND_SOC_DAPM_OUTPUT("LOUT2"),
SND_SOC_DAPM_OUTPUT("LOUT3"),
SND_SOC_DAPM_OUTPUT("LOUT4"),
SND_SOC_DAPM_OUTPUT("LOUT5"),
SND_SOC_DAPM_OUTPUT("LOUT6"),
SND_SOC_DAPM_OUTPUT("ROUT1"),
SND_SOC_DAPM_OUTPUT("ROUT2"),
SND_SOC_DAPM_OUTPUT("ROUT3"),
SND_SOC_DAPM_OUTPUT("ROUT4"),
SND_SOC_DAPM_OUTPUT("ROUT5"),
SND_SOC_DAPM_OUTPUT("ROUT6"),
/* Inputs */
SND_SOC_DAPM_INPUT("LIN1"),
SND_SOC_DAPM_INPUT("LIN2"),
SND_SOC_DAPM_INPUT("RIN1"),
SND_SOC_DAPM_INPUT("RIN2"),
/* DAC */
SND_SOC_DAPM_DAC("DAC1", NULL, PW_MGMT3, 0, 0),
SND_SOC_DAPM_DAC("DAC2", NULL, PW_MGMT3, 1, 0),
SND_SOC_DAPM_DAC("DAC3", NULL, PW_MGMT3, 2, 0),
SND_SOC_DAPM_DAC("DAC4", NULL, PW_MGMT3, 3, 0),
SND_SOC_DAPM_DAC("DAC5", NULL, PW_MGMT3, 4, 0),
SND_SOC_DAPM_DAC("DAC6", NULL, PW_MGMT3, 5, 0),
/* ADC */
SND_SOC_DAPM_ADC("ADC1", NULL, PW_MGMT2, 0, 0),
SND_SOC_DAPM_ADC("ADC2", NULL, PW_MGMT2, 1, 0),
};
static const struct snd_soc_dapm_route ak4613_intercon[] = {
{"LOUT1", NULL, "DAC1"},
{"LOUT2", NULL, "DAC2"},
{"LOUT3", NULL, "DAC3"},
{"LOUT4", NULL, "DAC4"},
{"LOUT5", NULL, "DAC5"},
{"LOUT6", NULL, "DAC6"},
{"ROUT1", NULL, "DAC1"},
{"ROUT2", NULL, "DAC2"},
{"ROUT3", NULL, "DAC3"},
{"ROUT4", NULL, "DAC4"},
{"ROUT5", NULL, "DAC5"},
{"ROUT6", NULL, "DAC6"},
{"DAC1", NULL, "Playback"},
{"DAC2", NULL, "Playback"},
{"DAC3", NULL, "Playback"},
{"DAC4", NULL, "Playback"},
{"DAC5", NULL, "Playback"},
{"DAC6", NULL, "Playback"},
{"Capture", NULL, "ADC1"},
{"Capture", NULL, "ADC2"},
{"ADC1", NULL, "LIN1"},
{"ADC2", NULL, "LIN2"},
{"ADC1", NULL, "RIN1"},
{"ADC2", NULL, "RIN2"},
};
static void ak4613_dai_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct ak4613_priv *priv = snd_soc_component_get_drvdata(component);
struct device *dev = component->dev;
mutex_lock(&priv->lock);
priv->cnt--;
if (priv->cnt < 0) {
dev_err(dev, "unexpected counter error\n");
priv->cnt = 0;
}
if (!priv->cnt)
priv->ctrl1 = 0;
mutex_unlock(&priv->lock);
}
static void ak4613_hw_constraints(struct ak4613_priv *priv,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
static const unsigned int ak4613_rates[] = {
32000,
44100,
48000,
64000,
88200,
96000,
176400,
192000,
};
#define AK4613_CHANNEL_2 0
#define AK4613_CHANNEL_4 1
#define AK4613_CHANNEL_8 2
#define AK4613_CHANNEL_12 3
#define AK4613_CHANNEL_NONE -1
static const unsigned int ak4613_channels[] = {
[AK4613_CHANNEL_2] = 2,
[AK4613_CHANNEL_4] = 4,
[AK4613_CHANNEL_8] = 8,
[AK4613_CHANNEL_12] = 12,
};
#define MODE_MAX 4
#define SDTx_MAX 4
#define MASK(x) (1 << AK4613_CHANNEL_##x)
static const int mask_list[MODE_MAX][SDTx_MAX] = {
/* SDTO SDTIx1 SDTIx2 SDTIx3 */
[AK4613_CONFIG_MODE_STEREO] = { MASK(2), MASK(2), MASK(2), MASK(2)},
[AK4613_CONFIG_MODE_TDM512] = { MASK(4), MASK(12), MASK(12), MASK(12)},
[AK4613_CONFIG_MODE_TDM256] = { MASK(4), MASK(8), MASK(8)|MASK(12), MASK(8)|MASK(12)},
[AK4613_CONFIG_MODE_TDM128] = { MASK(4), MASK(4), MASK(4)|MASK(8), MASK(4)|MASK(8)|MASK(12)},
};
struct snd_pcm_hw_constraint_list *constraint;
unsigned int mask;
unsigned int mode;
unsigned int fs;
int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
int sdti_num;
int i;
constraint = &priv->constraint_rates;
constraint->list = ak4613_rates;
constraint->mask = 0;
constraint->count = 0;
/*
* Slave Mode
* Normal: [32kHz, 48kHz] : 256fs,384fs or 512fs
* Double: [64kHz, 96kHz] : 256fs
* Quad : [128kHz,192kHz]: 128fs
*
* Master mode
* Normal: [32kHz, 48kHz] : 256fs or 512fs
* Double: [64kHz, 96kHz] : 256fs
* Quad : [128kHz,192kHz]: 128fs
*/
for (i = 0; i < ARRAY_SIZE(ak4613_rates); i++) {
/* minimum fs on each range */
fs = (ak4613_rates[i] <= 96000) ? 256 : 128;
if (priv->sysclk >= ak4613_rates[i] * fs)
constraint->count = i + 1;
}
snd_pcm_hw_constraint_list(runtime, 0,
SNDRV_PCM_HW_PARAM_RATE, constraint);
sdti_num = AK4613_CONFIG_SDTI_get(priv);
if (WARN_ON(sdti_num >= SDTx_MAX))
return;
if (priv->cnt) {
/*
* If it was already working,
* the constraint is same as working mode.
*/
mode = AK4613_CTRL1_TO_MODE(priv);
mask = 0; /* no default */
} else {
/*
* It is not yet working,
* the constraint is based on board configs.
* STEREO mask is default
*/
mode = AK4613_CONFIG_GET(priv, MODE);
mask = mask_list[AK4613_CONFIG_MODE_STEREO][is_play * sdti_num];
}
if (WARN_ON(mode >= MODE_MAX))
return;
/* add each mode mask */
mask |= mask_list[mode][is_play * sdti_num];
constraint = &priv->constraint_channels;
constraint->list = ak4613_channels;
constraint->mask = mask;
constraint->count = sizeof(ak4613_channels);
snd_pcm_hw_constraint_list(runtime, 0,
SNDRV_PCM_HW_PARAM_CHANNELS, constraint);
}
static int ak4613_dai_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct ak4613_priv *priv = snd_soc_component_get_drvdata(component);
mutex_lock(&priv->lock);
ak4613_hw_constraints(priv, substream);
priv->cnt++;
mutex_unlock(&priv->lock);
return 0;
}
static int ak4613_dai_set_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct ak4613_priv *priv = snd_soc_component_get_drvdata(component);
priv->sysclk = freq;
return 0;
}
static int ak4613_dai_set_fmt(struct snd_soc_dai *dai, unsigned int format)
{
struct snd_soc_component *component = dai->component;
struct ak4613_priv *priv = snd_soc_component_get_drvdata(component);
unsigned int fmt;
fmt = format & SND_SOC_DAIFMT_FORMAT_MASK;
switch (fmt) {
case SND_SOC_DAIFMT_LEFT_J:
case SND_SOC_DAIFMT_I2S:
priv->fmt = fmt;
break;
default:
return -EINVAL;
}
fmt = format & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK;
switch (fmt) {
case SND_SOC_DAIFMT_CBC_CFC:
break;
default:
/*
* SUPPORTME
*
* "clock provider" is not yet supperted
*/
return -EINVAL;
}
return 0;
}
static int ak4613_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct ak4613_priv *priv = snd_soc_component_get_drvdata(component);
struct device *dev = component->dev;
unsigned int width = params_width(params);
unsigned int fmt = priv->fmt;
unsigned int rate;
int i, ret;
u8 ctrl2;
rate = params_rate(params);
switch (rate) {
case 32000:
case 44100:
case 48000:
ctrl2 = DFS_NORMAL_SPEED;
break;
case 64000:
case 88200:
case 96000:
ctrl2 = DFS_DOUBLE_SPEED;
break;
case 176400:
case 192000:
ctrl2 = DFS_QUAD_SPEED;
break;
default:
return -EINVAL;
}
priv->rate = rate;
/*
* FIXME
*
* It doesn't have full TDM suppert yet
*/
ret = -EINVAL;
mutex_lock(&priv->lock);
if (priv->cnt > 1) {
/*
* If it was already working, use current priv->ctrl1
*/
ret = 0;
} else {
/*
* It is not yet working,
*/
unsigned int channel = params_channels(params);
u8 tdm;
/* STEREO or TDM */
if (channel == 2)
tdm = AK4613_CONFIG_MODE_STEREO;
else
tdm = AK4613_CONFIG_GET(priv, MODE);
for (i = ARRAY_SIZE(ak4613_iface) - 1; i >= 0; i--) {
const struct ak4613_interface *iface = ak4613_iface + i;
if ((iface->fmt == fmt) && (iface->width == width)) {
/*
* Ctrl1
* | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
* |TDM1|TDM0|DIF2|DIF1|DIF0|ATS1|ATS0|SMUTE|
* < tdm > < iface->dif >
*/
priv->ctrl1 = (tdm << 6) | (iface->dif << 3);
ret = 0;
break;
}
}
}
mutex_unlock(&priv->lock);
if (ret < 0)
goto hw_params_end;
snd_soc_component_update_bits(component, CTRL1, FMT_MASK, priv->ctrl1);
snd_soc_component_update_bits(component, CTRL2, DFS_MASK, ctrl2);
snd_soc_component_update_bits(component, ICTRL, ICTRL_MASK, priv->ic);
snd_soc_component_update_bits(component, OCTRL, OCTRL_MASK, priv->oc);
hw_params_end:
if (ret < 0)
dev_warn(dev, "unsupported data width/format combination\n");
return ret;
}
static int ak4613_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
u8 mgmt1 = 0;
switch (level) {
case SND_SOC_BIAS_ON:
mgmt1 |= RSTN;
fallthrough;
case SND_SOC_BIAS_PREPARE:
mgmt1 |= PMADC | PMDAC;
fallthrough;
case SND_SOC_BIAS_STANDBY:
mgmt1 |= PMVR;
fallthrough;
case SND_SOC_BIAS_OFF:
default:
break;
}
snd_soc_component_write(component, PW_MGMT1, mgmt1);
return 0;
}
static void ak4613_dummy_write(struct work_struct *work)
{
struct ak4613_priv *priv = container_of(work,
struct ak4613_priv,
dummy_write_work);
struct snd_soc_component *component = priv->component;
unsigned int mgmt1;
unsigned int mgmt3;
/*
* PW_MGMT1 / PW_MGMT3 needs dummy write at least after 5 LR clocks
*
* Note
*
* To avoid extra delay, we want to avoid preemption here,
* but we can't. Because it uses I2C access which is using IRQ
* and sleep. Thus, delay might be more than 5 LR clocks
* see also
* ak4613_dai_trigger()
*/
udelay(5000000 / priv->rate);
mgmt1 = snd_soc_component_read(component, PW_MGMT1);
mgmt3 = snd_soc_component_read(component, PW_MGMT3);
snd_soc_component_write(component, PW_MGMT1, mgmt1);
snd_soc_component_write(component, PW_MGMT3, mgmt3);
}
static int ak4613_dai_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct ak4613_priv *priv = snd_soc_component_get_drvdata(component);
/*
* FIXME
*
* PW_MGMT1 / PW_MGMT3 needs dummy write at least after 5 LR clocks
* from Power Down Release. Otherwise, Playback volume will be 0dB.
* To avoid complex multiple delay/dummy_write method from
* ak4613_set_bias_level() / SND_SOC_DAPM_DAC_E("DACx", ...),
* call it once here.
*
* But, unfortunately, we can't "write" here because here is atomic
* context (It uses I2C access for writing).
* Thus, use schedule_work() to switching to normal context
* immediately.
*
* Note
*
* Calling ak4613_dummy_write() function might be delayed.
* In such case, ak4613 volume might be temporarily 0dB when
* beggining of playback.
* see also
* ak4613_dummy_write()
*/
if ((cmd != SNDRV_PCM_TRIGGER_START) &&
(cmd != SNDRV_PCM_TRIGGER_RESUME))
return 0;
if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
return 0;
priv->component = component;
schedule_work(&priv->dummy_write_work);
return 0;
}
/*
* Select below from Sound Card, not Auto
* SND_SOC_DAIFMT_CBC_CFC
* SND_SOC_DAIFMT_CBP_CFP
*/
static u64 ak4613_dai_formats =
SND_SOC_POSSIBLE_DAIFMT_I2S |
SND_SOC_POSSIBLE_DAIFMT_LEFT_J;
static const struct snd_soc_dai_ops ak4613_dai_ops = {
.startup = ak4613_dai_startup,
.shutdown = ak4613_dai_shutdown,
.set_sysclk = ak4613_dai_set_sysclk,
.set_fmt = ak4613_dai_set_fmt,
.trigger = ak4613_dai_trigger,
.hw_params = ak4613_dai_hw_params,
.auto_selectable_formats = &ak4613_dai_formats,
.num_auto_selectable_formats = 1,
};
#define AK4613_PCM_RATE (SNDRV_PCM_RATE_32000 |\
SNDRV_PCM_RATE_44100 |\
SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_64000 |\
SNDRV_PCM_RATE_88200 |\
SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_176400 |\
SNDRV_PCM_RATE_192000)
#define AK4613_PCM_FMTBIT (SNDRV_PCM_FMTBIT_S24_LE)
static struct snd_soc_dai_driver ak4613_dai = {
.name = "ak4613-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 12,
.rates = AK4613_PCM_RATE,
.formats = AK4613_PCM_FMTBIT,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 4,
.rates = AK4613_PCM_RATE,
.formats = AK4613_PCM_FMTBIT,
},
.ops = &ak4613_dai_ops,
.symmetric_rate = 1,
};
static int ak4613_suspend(struct snd_soc_component *component)
{
struct regmap *regmap = dev_get_regmap(component->dev, NULL);
regcache_cache_only(regmap, true);
regcache_mark_dirty(regmap);
return 0;
}
static int ak4613_resume(struct snd_soc_component *component)
{
struct regmap *regmap = dev_get_regmap(component->dev, NULL);
regcache_cache_only(regmap, false);
return regcache_sync(regmap);
}
static const struct snd_soc_component_driver soc_component_dev_ak4613 = {
.suspend = ak4613_suspend,
.resume = ak4613_resume,
.set_bias_level = ak4613_set_bias_level,
.controls = ak4613_snd_controls,
.num_controls = ARRAY_SIZE(ak4613_snd_controls),
.dapm_widgets = ak4613_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(ak4613_dapm_widgets),
.dapm_routes = ak4613_intercon,
.num_dapm_routes = ARRAY_SIZE(ak4613_intercon),
.idle_bias_on = 1,
.endianness = 1,
};
static void ak4613_parse_of(struct ak4613_priv *priv,
struct device *dev)
{
struct device_node *np = dev->of_node;
char prop[32];
int sdti_num;
int i;
/* Input 1 - 2 */
for (i = 0; i < 2; i++) {
snprintf(prop, sizeof(prop), "asahi-kasei,in%d-single-end", i + 1);
if (!of_get_property(np, prop, NULL))
priv->ic |= 1 << i;
}
/* Output 1 - 6 */
for (i = 0; i < 6; i++) {
snprintf(prop, sizeof(prop), "asahi-kasei,out%d-single-end", i + 1);
if (!of_get_property(np, prop, NULL))
priv->oc |= 1 << i;
}
/*
* enable TDM256 test
*
* !!! FIXME !!!
*
* It should be configured by DT or other way
* if it was full supported.
* But it is using ifdef style for now for test
* purpose.
*/
#if defined(AK4613_ENABLE_TDM_TEST)
AK4613_CONFIG_SET(priv, MODE_TDM256);
#endif
/*
* connected STDI
* TDM support is assuming it is probed via Audio-Graph-Card style here.
* Default is SDTIx1 if it was probed via Simple-Audio-Card for now.
*/
sdti_num = of_graph_get_endpoint_count(np);
if ((sdti_num >= SDTx_MAX) || (sdti_num < 1))
sdti_num = 1;
AK4613_CONFIG_SDTI_set(priv, sdti_num);
}
static int ak4613_i2c_probe(struct i2c_client *i2c)
{
struct device *dev = &i2c->dev;
const struct regmap_config *regmap_cfg;
struct regmap *regmap;
struct ak4613_priv *priv;
regmap_cfg = i2c_get_match_data(i2c);
if (!regmap_cfg)
return -EINVAL;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
ak4613_parse_of(priv, dev);
priv->ctrl1 = 0;
priv->cnt = 0;
priv->sysclk = 0;
INIT_WORK(&priv->dummy_write_work, ak4613_dummy_write);
mutex_init(&priv->lock);
i2c_set_clientdata(i2c, priv);
regmap = devm_regmap_init_i2c(i2c, regmap_cfg);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return devm_snd_soc_register_component(dev, &soc_component_dev_ak4613,
&ak4613_dai, 1);
}
static struct i2c_driver ak4613_i2c_driver = {
.driver = {
.name = "ak4613-codec",
.of_match_table = ak4613_of_match,
},
.probe = ak4613_i2c_probe,
.id_table = ak4613_i2c_id,
};
module_i2c_driver(ak4613_i2c_driver);
MODULE_DESCRIPTION("Soc AK4613 driver");
MODULE_AUTHOR("Kuninori Morimoto <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/ak4613.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* cs43130.c -- CS43130 ALSA Soc Audio driver
*
* Copyright 2017 Cirrus Logic, Inc.
*
* Authors: Li Xu <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <linux/of_gpio.h>
#include <linux/regulator/consumer.h>
#include <linux/pm_runtime.h>
#include <linux/of_irq.h>
#include <linux/completion.h>
#include <linux/mutex.h>
#include <linux/workqueue.h>
#include <sound/jack.h>
#include "cs43130.h"
#include "cirrus_legacy.h"
static const struct reg_default cs43130_reg_defaults[] = {
{CS43130_SYS_CLK_CTL_1, 0x06},
{CS43130_SP_SRATE, 0x01},
{CS43130_SP_BITSIZE, 0x05},
{CS43130_PAD_INT_CFG, 0x03},
{CS43130_PWDN_CTL, 0xFE},
{CS43130_CRYSTAL_SET, 0x04},
{CS43130_PLL_SET_1, 0x00},
{CS43130_PLL_SET_2, 0x00},
{CS43130_PLL_SET_3, 0x00},
{CS43130_PLL_SET_4, 0x00},
{CS43130_PLL_SET_5, 0x40},
{CS43130_PLL_SET_6, 0x10},
{CS43130_PLL_SET_7, 0x80},
{CS43130_PLL_SET_8, 0x03},
{CS43130_PLL_SET_9, 0x02},
{CS43130_PLL_SET_10, 0x02},
{CS43130_CLKOUT_CTL, 0x00},
{CS43130_ASP_NUM_1, 0x01},
{CS43130_ASP_NUM_2, 0x00},
{CS43130_ASP_DEN_1, 0x08},
{CS43130_ASP_DEN_2, 0x00},
{CS43130_ASP_LRCK_HI_TIME_1, 0x1F},
{CS43130_ASP_LRCK_HI_TIME_2, 0x00},
{CS43130_ASP_LRCK_PERIOD_1, 0x3F},
{CS43130_ASP_LRCK_PERIOD_2, 0x00},
{CS43130_ASP_CLOCK_CONF, 0x0C},
{CS43130_ASP_FRAME_CONF, 0x0A},
{CS43130_XSP_NUM_1, 0x01},
{CS43130_XSP_NUM_2, 0x00},
{CS43130_XSP_DEN_1, 0x02},
{CS43130_XSP_DEN_2, 0x00},
{CS43130_XSP_LRCK_HI_TIME_1, 0x1F},
{CS43130_XSP_LRCK_HI_TIME_2, 0x00},
{CS43130_XSP_LRCK_PERIOD_1, 0x3F},
{CS43130_XSP_LRCK_PERIOD_2, 0x00},
{CS43130_XSP_CLOCK_CONF, 0x0C},
{CS43130_XSP_FRAME_CONF, 0x0A},
{CS43130_ASP_CH_1_LOC, 0x00},
{CS43130_ASP_CH_2_LOC, 0x00},
{CS43130_ASP_CH_1_SZ_EN, 0x06},
{CS43130_ASP_CH_2_SZ_EN, 0x0E},
{CS43130_XSP_CH_1_LOC, 0x00},
{CS43130_XSP_CH_2_LOC, 0x00},
{CS43130_XSP_CH_1_SZ_EN, 0x06},
{CS43130_XSP_CH_2_SZ_EN, 0x0E},
{CS43130_DSD_VOL_B, 0x78},
{CS43130_DSD_VOL_A, 0x78},
{CS43130_DSD_PATH_CTL_1, 0xA8},
{CS43130_DSD_INT_CFG, 0x00},
{CS43130_DSD_PATH_CTL_2, 0x02},
{CS43130_DSD_PCM_MIX_CTL, 0x00},
{CS43130_DSD_PATH_CTL_3, 0x40},
{CS43130_HP_OUT_CTL_1, 0x30},
{CS43130_PCM_FILT_OPT, 0x02},
{CS43130_PCM_VOL_B, 0x78},
{CS43130_PCM_VOL_A, 0x78},
{CS43130_PCM_PATH_CTL_1, 0xA8},
{CS43130_PCM_PATH_CTL_2, 0x00},
{CS43130_CLASS_H_CTL, 0x1E},
{CS43130_HP_DETECT, 0x04},
{CS43130_HP_LOAD_1, 0x00},
{CS43130_HP_MEAS_LOAD_1, 0x00},
{CS43130_HP_MEAS_LOAD_2, 0x00},
{CS43130_INT_MASK_1, 0xFF},
{CS43130_INT_MASK_2, 0xFF},
{CS43130_INT_MASK_3, 0xFF},
{CS43130_INT_MASK_4, 0xFF},
{CS43130_INT_MASK_5, 0xFF},
};
static bool cs43130_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS43130_INT_STATUS_1 ... CS43130_INT_STATUS_5:
case CS43130_HP_DC_STAT_1 ... CS43130_HP_DC_STAT_2:
case CS43130_HP_AC_STAT_1 ... CS43130_HP_AC_STAT_2:
return true;
default:
return false;
}
}
static bool cs43130_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS43130_DEVID_AB ... CS43130_SYS_CLK_CTL_1:
case CS43130_SP_SRATE ... CS43130_PAD_INT_CFG:
case CS43130_PWDN_CTL:
case CS43130_CRYSTAL_SET:
case CS43130_PLL_SET_1 ... CS43130_PLL_SET_5:
case CS43130_PLL_SET_6:
case CS43130_PLL_SET_7:
case CS43130_PLL_SET_8:
case CS43130_PLL_SET_9:
case CS43130_PLL_SET_10:
case CS43130_CLKOUT_CTL:
case CS43130_ASP_NUM_1 ... CS43130_ASP_FRAME_CONF:
case CS43130_XSP_NUM_1 ... CS43130_XSP_FRAME_CONF:
case CS43130_ASP_CH_1_LOC:
case CS43130_ASP_CH_2_LOC:
case CS43130_ASP_CH_1_SZ_EN:
case CS43130_ASP_CH_2_SZ_EN:
case CS43130_XSP_CH_1_LOC:
case CS43130_XSP_CH_2_LOC:
case CS43130_XSP_CH_1_SZ_EN:
case CS43130_XSP_CH_2_SZ_EN:
case CS43130_DSD_VOL_B ... CS43130_DSD_PATH_CTL_3:
case CS43130_HP_OUT_CTL_1:
case CS43130_PCM_FILT_OPT ... CS43130_PCM_PATH_CTL_2:
case CS43130_CLASS_H_CTL:
case CS43130_HP_DETECT:
case CS43130_HP_STATUS:
case CS43130_HP_LOAD_1:
case CS43130_HP_MEAS_LOAD_1:
case CS43130_HP_MEAS_LOAD_2:
case CS43130_HP_DC_STAT_1:
case CS43130_HP_DC_STAT_2:
case CS43130_HP_AC_STAT_1:
case CS43130_HP_AC_STAT_2:
case CS43130_HP_LOAD_STAT:
case CS43130_INT_STATUS_1 ... CS43130_INT_STATUS_5:
case CS43130_INT_MASK_1 ... CS43130_INT_MASK_5:
return true;
default:
return false;
}
}
static bool cs43130_precious_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS43130_INT_STATUS_1 ... CS43130_INT_STATUS_5:
return true;
default:
return false;
}
}
struct cs43130_pll_params {
unsigned int pll_in;
u8 sclk_prediv;
u8 pll_div_int;
u32 pll_div_frac;
u8 pll_mode;
u8 pll_divout;
unsigned int pll_out;
u8 pll_cal_ratio;
};
static const struct cs43130_pll_params pll_ratio_table[] = {
{9600000, 0x02, 0x49, 0x800000, 0x00, 0x08, 22579200, 151},
{9600000, 0x02, 0x50, 0x000000, 0x00, 0x08, 24576000, 164},
{11289600, 0x02, 0X40, 0, 0x01, 0x08, 22579200, 128},
{11289600, 0x02, 0x44, 0x06F700, 0x0, 0x08, 24576000, 139},
{12000000, 0x02, 0x49, 0x800000, 0x00, 0x0A, 22579200, 120},
{12000000, 0x02, 0x40, 0x000000, 0x00, 0x08, 24576000, 131},
{12288000, 0x02, 0x49, 0x800000, 0x01, 0x0A, 22579200, 118},
{12288000, 0x02, 0x40, 0x000000, 0x01, 0x08, 24576000, 128},
{13000000, 0x02, 0x45, 0x797680, 0x01, 0x0A, 22579200, 111},
{13000000, 0x02, 0x3C, 0x7EA940, 0x01, 0x08, 24576000, 121},
{19200000, 0x03, 0x49, 0x800000, 0x00, 0x08, 22579200, 151},
{19200000, 0x03, 0x50, 0x000000, 0x00, 0x08, 24576000, 164},
{22579200, 0, 0, 0, 0, 0, 22579200, 0},
{22579200, 0x03, 0x44, 0x06F700, 0x00, 0x08, 24576000, 139},
{24000000, 0x03, 0x49, 0x800000, 0x00, 0x0A, 22579200, 120},
{24000000, 0x03, 0x40, 0x000000, 0x00, 0x08, 24576000, 131},
{24576000, 0x03, 0x49, 0x800000, 0x01, 0x0A, 22579200, 118},
{24576000, 0, 0, 0, 0, 0, 24576000, 0},
{26000000, 0x03, 0x45, 0x797680, 0x01, 0x0A, 22579200, 111},
{26000000, 0x03, 0x3C, 0x7EA940, 0x01, 0x08, 24576000, 121},
};
static const struct cs43130_pll_params *cs43130_get_pll_table(
unsigned int freq_in, unsigned int freq_out)
{
int i;
for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
if (pll_ratio_table[i].pll_in == freq_in &&
pll_ratio_table[i].pll_out == freq_out)
return &pll_ratio_table[i];
}
return NULL;
}
static int cs43130_pll_config(struct snd_soc_component *component)
{
struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
const struct cs43130_pll_params *pll_entry;
dev_dbg(component->dev, "cs43130->mclk = %u, cs43130->mclk_int = %u\n",
cs43130->mclk, cs43130->mclk_int);
pll_entry = cs43130_get_pll_table(cs43130->mclk, cs43130->mclk_int);
if (!pll_entry)
return -EINVAL;
if (pll_entry->pll_cal_ratio == 0) {
regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_1,
CS43130_PLL_START_MASK, 0);
cs43130->pll_bypass = true;
return 0;
}
cs43130->pll_bypass = false;
regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_2,
CS43130_PLL_DIV_DATA_MASK,
pll_entry->pll_div_frac >>
CS43130_PLL_DIV_FRAC_0_DATA_SHIFT);
regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_3,
CS43130_PLL_DIV_DATA_MASK,
pll_entry->pll_div_frac >>
CS43130_PLL_DIV_FRAC_1_DATA_SHIFT);
regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_4,
CS43130_PLL_DIV_DATA_MASK,
pll_entry->pll_div_frac >>
CS43130_PLL_DIV_FRAC_2_DATA_SHIFT);
regmap_write(cs43130->regmap, CS43130_PLL_SET_5,
pll_entry->pll_div_int);
regmap_write(cs43130->regmap, CS43130_PLL_SET_6, pll_entry->pll_divout);
regmap_write(cs43130->regmap, CS43130_PLL_SET_7,
pll_entry->pll_cal_ratio);
regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_8,
CS43130_PLL_MODE_MASK,
pll_entry->pll_mode << CS43130_PLL_MODE_SHIFT);
regmap_write(cs43130->regmap, CS43130_PLL_SET_9,
pll_entry->sclk_prediv);
regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_1,
CS43130_PLL_START_MASK, 1);
return 0;
}
static int cs43130_set_pll(struct snd_soc_component *component, int pll_id, int source,
unsigned int freq_in, unsigned int freq_out)
{
int ret = 0;
struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
switch (freq_in) {
case 9600000:
case 11289600:
case 12000000:
case 12288000:
case 13000000:
case 19200000:
case 22579200:
case 24000000:
case 24576000:
case 26000000:
cs43130->mclk = freq_in;
break;
default:
dev_err(component->dev,
"unsupported pll input reference clock:%d\n", freq_in);
return -EINVAL;
}
switch (freq_out) {
case 22579200:
cs43130->mclk_int = freq_out;
break;
case 24576000:
cs43130->mclk_int = freq_out;
break;
default:
dev_err(component->dev,
"unsupported pll output ref clock: %u\n", freq_out);
return -EINVAL;
}
ret = cs43130_pll_config(component);
dev_dbg(component->dev, "cs43130->pll_bypass = %d", cs43130->pll_bypass);
return ret;
}
static int cs43130_change_clksrc(struct snd_soc_component *component,
enum cs43130_mclk_src_sel src)
{
int ret;
struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
int mclk_int_decoded;
if (src == cs43130->mclk_int_src) {
/* clk source has not changed */
return 0;
}
switch (cs43130->mclk_int) {
case CS43130_MCLK_22M:
mclk_int_decoded = CS43130_MCLK_22P5;
break;
case CS43130_MCLK_24M:
mclk_int_decoded = CS43130_MCLK_24P5;
break;
default:
dev_err(component->dev, "Invalid MCLK INT freq: %u\n", cs43130->mclk_int);
return -EINVAL;
}
switch (src) {
case CS43130_MCLK_SRC_EXT:
cs43130->pll_bypass = true;
cs43130->mclk_int_src = CS43130_MCLK_SRC_EXT;
if (cs43130->xtal_ibias == CS43130_XTAL_UNUSED) {
regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
CS43130_PDN_XTAL_MASK,
1 << CS43130_PDN_XTAL_SHIFT);
} else {
reinit_completion(&cs43130->xtal_rdy);
regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
CS43130_XTAL_RDY_INT_MASK, 0);
regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
CS43130_PDN_XTAL_MASK, 0);
ret = wait_for_completion_timeout(&cs43130->xtal_rdy,
msecs_to_jiffies(100));
regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
CS43130_XTAL_RDY_INT_MASK,
1 << CS43130_XTAL_RDY_INT_SHIFT);
if (ret == 0) {
dev_err(component->dev, "Timeout waiting for XTAL_READY interrupt\n");
return -ETIMEDOUT;
}
}
regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
CS43130_MCLK_SRC_SEL_MASK,
src << CS43130_MCLK_SRC_SEL_SHIFT);
regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
CS43130_MCLK_INT_MASK,
mclk_int_decoded << CS43130_MCLK_INT_SHIFT);
usleep_range(150, 200);
regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
CS43130_PDN_PLL_MASK,
1 << CS43130_PDN_PLL_SHIFT);
break;
case CS43130_MCLK_SRC_PLL:
cs43130->pll_bypass = false;
cs43130->mclk_int_src = CS43130_MCLK_SRC_PLL;
if (cs43130->xtal_ibias == CS43130_XTAL_UNUSED) {
regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
CS43130_PDN_XTAL_MASK,
1 << CS43130_PDN_XTAL_SHIFT);
} else {
reinit_completion(&cs43130->xtal_rdy);
regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
CS43130_XTAL_RDY_INT_MASK, 0);
regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
CS43130_PDN_XTAL_MASK, 0);
ret = wait_for_completion_timeout(&cs43130->xtal_rdy,
msecs_to_jiffies(100));
regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
CS43130_XTAL_RDY_INT_MASK,
1 << CS43130_XTAL_RDY_INT_SHIFT);
if (ret == 0) {
dev_err(component->dev, "Timeout waiting for XTAL_READY interrupt\n");
return -ETIMEDOUT;
}
}
reinit_completion(&cs43130->pll_rdy);
regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
CS43130_PLL_RDY_INT_MASK, 0);
regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
CS43130_PDN_PLL_MASK, 0);
ret = wait_for_completion_timeout(&cs43130->pll_rdy,
msecs_to_jiffies(100));
regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
CS43130_PLL_RDY_INT_MASK,
1 << CS43130_PLL_RDY_INT_SHIFT);
if (ret == 0) {
dev_err(component->dev, "Timeout waiting for PLL_READY interrupt\n");
return -ETIMEDOUT;
}
regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
CS43130_MCLK_SRC_SEL_MASK,
src << CS43130_MCLK_SRC_SEL_SHIFT);
regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
CS43130_MCLK_INT_MASK,
mclk_int_decoded << CS43130_MCLK_INT_SHIFT);
usleep_range(150, 200);
break;
case CS43130_MCLK_SRC_RCO:
cs43130->mclk_int_src = CS43130_MCLK_SRC_RCO;
regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
CS43130_MCLK_SRC_SEL_MASK,
src << CS43130_MCLK_SRC_SEL_SHIFT);
regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
CS43130_MCLK_INT_MASK,
CS43130_MCLK_22P5 << CS43130_MCLK_INT_SHIFT);
usleep_range(150, 200);
regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
CS43130_PDN_XTAL_MASK,
1 << CS43130_PDN_XTAL_SHIFT);
regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
CS43130_PDN_PLL_MASK,
1 << CS43130_PDN_PLL_SHIFT);
break;
default:
dev_err(component->dev, "Invalid MCLK source value\n");
return -EINVAL;
}
return 0;
}
static const struct cs43130_bitwidth_map cs43130_bitwidth_table[] = {
{8, CS43130_SP_BIT_SIZE_8, CS43130_CH_BIT_SIZE_8},
{16, CS43130_SP_BIT_SIZE_16, CS43130_CH_BIT_SIZE_16},
{24, CS43130_SP_BIT_SIZE_24, CS43130_CH_BIT_SIZE_24},
{32, CS43130_SP_BIT_SIZE_32, CS43130_CH_BIT_SIZE_32},
};
static const struct cs43130_bitwidth_map *cs43130_get_bitwidth_table(
unsigned int bitwidth)
{
int i;
for (i = 0; i < ARRAY_SIZE(cs43130_bitwidth_table); i++) {
if (cs43130_bitwidth_table[i].bitwidth == bitwidth)
return &cs43130_bitwidth_table[i];
}
return NULL;
}
static int cs43130_set_bitwidth(int dai_id, unsigned int bitwidth_dai,
struct regmap *regmap)
{
const struct cs43130_bitwidth_map *bw_map;
bw_map = cs43130_get_bitwidth_table(bitwidth_dai);
if (!bw_map)
return -EINVAL;
switch (dai_id) {
case CS43130_ASP_PCM_DAI:
case CS43130_ASP_DOP_DAI:
regmap_update_bits(regmap, CS43130_ASP_CH_1_SZ_EN,
CS43130_CH_BITSIZE_MASK, bw_map->ch_bit);
regmap_update_bits(regmap, CS43130_ASP_CH_2_SZ_EN,
CS43130_CH_BITSIZE_MASK, bw_map->ch_bit);
regmap_update_bits(regmap, CS43130_SP_BITSIZE,
CS43130_ASP_BITSIZE_MASK, bw_map->sp_bit);
break;
case CS43130_XSP_DOP_DAI:
regmap_update_bits(regmap, CS43130_XSP_CH_1_SZ_EN,
CS43130_CH_BITSIZE_MASK, bw_map->ch_bit);
regmap_update_bits(regmap, CS43130_XSP_CH_2_SZ_EN,
CS43130_CH_BITSIZE_MASK, bw_map->ch_bit);
regmap_update_bits(regmap, CS43130_SP_BITSIZE,
CS43130_XSP_BITSIZE_MASK, bw_map->sp_bit <<
CS43130_XSP_BITSIZE_SHIFT);
break;
default:
return -EINVAL;
}
return 0;
}
static const struct cs43130_rate_map cs43130_rate_table[] = {
{32000, CS43130_ASP_SPRATE_32K},
{44100, CS43130_ASP_SPRATE_44_1K},
{48000, CS43130_ASP_SPRATE_48K},
{88200, CS43130_ASP_SPRATE_88_2K},
{96000, CS43130_ASP_SPRATE_96K},
{176400, CS43130_ASP_SPRATE_176_4K},
{192000, CS43130_ASP_SPRATE_192K},
{352800, CS43130_ASP_SPRATE_352_8K},
{384000, CS43130_ASP_SPRATE_384K},
};
static const struct cs43130_rate_map *cs43130_get_rate_table(int fs)
{
int i;
for (i = 0; i < ARRAY_SIZE(cs43130_rate_table); i++) {
if (cs43130_rate_table[i].fs == fs)
return &cs43130_rate_table[i];
}
return NULL;
}
static const struct cs43130_clk_gen *cs43130_get_clk_gen(int mclk_int, int fs,
const struct cs43130_clk_gen *clk_gen_table, int len_clk_gen_table)
{
int i;
for (i = 0; i < len_clk_gen_table; i++) {
if (clk_gen_table[i].mclk_int == mclk_int &&
clk_gen_table[i].fs == fs)
return &clk_gen_table[i];
}
return NULL;
}
static int cs43130_set_sp_fmt(int dai_id, unsigned int bitwidth_sclk,
struct snd_pcm_hw_params *params,
struct cs43130_private *cs43130)
{
u16 frm_size;
u16 hi_size;
u8 frm_delay;
u8 frm_phase;
u8 frm_data;
u8 sclk_edge;
u8 lrck_edge;
u8 clk_data;
u8 loc_ch1;
u8 loc_ch2;
u8 dai_mode_val;
const struct cs43130_clk_gen *clk_gen;
switch (cs43130->dais[dai_id].dai_format) {
case SND_SOC_DAIFMT_I2S:
hi_size = bitwidth_sclk;
frm_delay = 2;
frm_phase = 0;
break;
case SND_SOC_DAIFMT_LEFT_J:
hi_size = bitwidth_sclk;
frm_delay = 2;
frm_phase = 1;
break;
case SND_SOC_DAIFMT_DSP_A:
hi_size = 1;
frm_delay = 2;
frm_phase = 1;
break;
case SND_SOC_DAIFMT_DSP_B:
hi_size = 1;
frm_delay = 0;
frm_phase = 1;
break;
default:
return -EINVAL;
}
switch (cs43130->dais[dai_id].dai_mode) {
case SND_SOC_DAIFMT_CBS_CFS:
dai_mode_val = 0;
break;
case SND_SOC_DAIFMT_CBM_CFM:
dai_mode_val = 1;
break;
default:
return -EINVAL;
}
frm_size = bitwidth_sclk * params_channels(params);
sclk_edge = 1;
lrck_edge = 0;
loc_ch1 = 0;
loc_ch2 = bitwidth_sclk * (params_channels(params) - 1);
frm_data = frm_delay & CS43130_SP_FSD_MASK;
frm_data |= (frm_phase << CS43130_SP_STP_SHIFT) & CS43130_SP_STP_MASK;
clk_data = lrck_edge & CS43130_SP_LCPOL_IN_MASK;
clk_data |= (lrck_edge << CS43130_SP_LCPOL_OUT_SHIFT) &
CS43130_SP_LCPOL_OUT_MASK;
clk_data |= (sclk_edge << CS43130_SP_SCPOL_IN_SHIFT) &
CS43130_SP_SCPOL_IN_MASK;
clk_data |= (sclk_edge << CS43130_SP_SCPOL_OUT_SHIFT) &
CS43130_SP_SCPOL_OUT_MASK;
clk_data |= (dai_mode_val << CS43130_SP_MODE_SHIFT) &
CS43130_SP_MODE_MASK;
switch (dai_id) {
case CS43130_ASP_PCM_DAI:
case CS43130_ASP_DOP_DAI:
regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_PERIOD_1,
CS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >>
CS43130_SP_LCPR_LSB_DATA_SHIFT);
regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_PERIOD_2,
CS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >>
CS43130_SP_LCPR_MSB_DATA_SHIFT);
regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_HI_TIME_1,
CS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >>
CS43130_SP_LCHI_LSB_DATA_SHIFT);
regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_HI_TIME_2,
CS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >>
CS43130_SP_LCHI_MSB_DATA_SHIFT);
regmap_write(cs43130->regmap, CS43130_ASP_FRAME_CONF, frm_data);
regmap_write(cs43130->regmap, CS43130_ASP_CH_1_LOC, loc_ch1);
regmap_write(cs43130->regmap, CS43130_ASP_CH_2_LOC, loc_ch2);
regmap_update_bits(cs43130->regmap, CS43130_ASP_CH_1_SZ_EN,
CS43130_CH_EN_MASK, 1 << CS43130_CH_EN_SHIFT);
regmap_update_bits(cs43130->regmap, CS43130_ASP_CH_2_SZ_EN,
CS43130_CH_EN_MASK, 1 << CS43130_CH_EN_SHIFT);
regmap_write(cs43130->regmap, CS43130_ASP_CLOCK_CONF, clk_data);
break;
case CS43130_XSP_DOP_DAI:
regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_PERIOD_1,
CS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >>
CS43130_SP_LCPR_LSB_DATA_SHIFT);
regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_PERIOD_2,
CS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >>
CS43130_SP_LCPR_MSB_DATA_SHIFT);
regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_HI_TIME_1,
CS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >>
CS43130_SP_LCHI_LSB_DATA_SHIFT);
regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_HI_TIME_2,
CS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >>
CS43130_SP_LCHI_MSB_DATA_SHIFT);
regmap_write(cs43130->regmap, CS43130_XSP_FRAME_CONF, frm_data);
regmap_write(cs43130->regmap, CS43130_XSP_CH_1_LOC, loc_ch1);
regmap_write(cs43130->regmap, CS43130_XSP_CH_2_LOC, loc_ch2);
regmap_update_bits(cs43130->regmap, CS43130_XSP_CH_1_SZ_EN,
CS43130_CH_EN_MASK, 1 << CS43130_CH_EN_SHIFT);
regmap_update_bits(cs43130->regmap, CS43130_XSP_CH_2_SZ_EN,
CS43130_CH_EN_MASK, 1 << CS43130_CH_EN_SHIFT);
regmap_write(cs43130->regmap, CS43130_XSP_CLOCK_CONF, clk_data);
break;
default:
return -EINVAL;
}
switch (frm_size) {
case 16:
clk_gen = cs43130_get_clk_gen(cs43130->mclk_int,
params_rate(params),
cs43130_16_clk_gen,
ARRAY_SIZE(cs43130_16_clk_gen));
break;
case 32:
clk_gen = cs43130_get_clk_gen(cs43130->mclk_int,
params_rate(params),
cs43130_32_clk_gen,
ARRAY_SIZE(cs43130_32_clk_gen));
break;
case 48:
clk_gen = cs43130_get_clk_gen(cs43130->mclk_int,
params_rate(params),
cs43130_48_clk_gen,
ARRAY_SIZE(cs43130_48_clk_gen));
break;
case 64:
clk_gen = cs43130_get_clk_gen(cs43130->mclk_int,
params_rate(params),
cs43130_64_clk_gen,
ARRAY_SIZE(cs43130_64_clk_gen));
break;
default:
return -EINVAL;
}
if (!clk_gen)
return -EINVAL;
switch (dai_id) {
case CS43130_ASP_PCM_DAI:
case CS43130_ASP_DOP_DAI:
regmap_write(cs43130->regmap, CS43130_ASP_DEN_1,
(clk_gen->v.denominator & CS43130_SP_M_LSB_DATA_MASK) >>
CS43130_SP_M_LSB_DATA_SHIFT);
regmap_write(cs43130->regmap, CS43130_ASP_DEN_2,
(clk_gen->v.denominator & CS43130_SP_M_MSB_DATA_MASK) >>
CS43130_SP_M_MSB_DATA_SHIFT);
regmap_write(cs43130->regmap, CS43130_ASP_NUM_1,
(clk_gen->v.numerator & CS43130_SP_N_LSB_DATA_MASK) >>
CS43130_SP_N_LSB_DATA_SHIFT);
regmap_write(cs43130->regmap, CS43130_ASP_NUM_2,
(clk_gen->v.numerator & CS43130_SP_N_MSB_DATA_MASK) >>
CS43130_SP_N_MSB_DATA_SHIFT);
break;
case CS43130_XSP_DOP_DAI:
regmap_write(cs43130->regmap, CS43130_XSP_DEN_1,
(clk_gen->v.denominator & CS43130_SP_M_LSB_DATA_MASK) >>
CS43130_SP_M_LSB_DATA_SHIFT);
regmap_write(cs43130->regmap, CS43130_XSP_DEN_2,
(clk_gen->v.denominator & CS43130_SP_M_MSB_DATA_MASK) >>
CS43130_SP_M_MSB_DATA_SHIFT);
regmap_write(cs43130->regmap, CS43130_XSP_NUM_1,
(clk_gen->v.numerator & CS43130_SP_N_LSB_DATA_MASK) >>
CS43130_SP_N_LSB_DATA_SHIFT);
regmap_write(cs43130->regmap, CS43130_XSP_NUM_2,
(clk_gen->v.numerator & CS43130_SP_N_MSB_DATA_MASK) >>
CS43130_SP_N_MSB_DATA_SHIFT);
break;
default:
return -EINVAL;
}
return 0;
}
static int cs43130_pcm_dsd_mix(bool en, struct regmap *regmap)
{
if (en) {
regmap_update_bits(regmap, CS43130_DSD_PCM_MIX_CTL,
CS43130_MIX_PCM_PREP_MASK,
1 << CS43130_MIX_PCM_PREP_SHIFT);
usleep_range(6000, 6050);
regmap_update_bits(regmap, CS43130_DSD_PCM_MIX_CTL,
CS43130_MIX_PCM_DSD_MASK,
1 << CS43130_MIX_PCM_DSD_SHIFT);
} else {
regmap_update_bits(regmap, CS43130_DSD_PCM_MIX_CTL,
CS43130_MIX_PCM_DSD_MASK,
0 << CS43130_MIX_PCM_DSD_SHIFT);
usleep_range(1600, 1650);
regmap_update_bits(regmap, CS43130_DSD_PCM_MIX_CTL,
CS43130_MIX_PCM_PREP_MASK,
0 << CS43130_MIX_PCM_PREP_SHIFT);
}
return 0;
}
static int cs43130_dsd_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
unsigned int required_clk;
u8 dsd_speed;
mutex_lock(&cs43130->clk_mutex);
if (!cs43130->clk_req) {
/* no DAI is currently using clk */
if (!(CS43130_MCLK_22M % params_rate(params)))
required_clk = CS43130_MCLK_22M;
else
required_clk = CS43130_MCLK_24M;
cs43130_set_pll(component, 0, 0, cs43130->mclk, required_clk);
if (cs43130->pll_bypass)
cs43130_change_clksrc(component, CS43130_MCLK_SRC_EXT);
else
cs43130_change_clksrc(component, CS43130_MCLK_SRC_PLL);
}
cs43130->clk_req++;
if (cs43130->clk_req == 2)
cs43130_pcm_dsd_mix(true, cs43130->regmap);
mutex_unlock(&cs43130->clk_mutex);
switch (params_rate(params)) {
case 176400:
dsd_speed = 0;
break;
case 352800:
dsd_speed = 1;
break;
default:
dev_err(component->dev, "Rate(%u) not supported\n",
params_rate(params));
return -EINVAL;
}
if (cs43130->dais[dai->id].dai_mode == SND_SOC_DAIFMT_CBM_CFM)
regmap_update_bits(cs43130->regmap, CS43130_DSD_INT_CFG,
CS43130_DSD_MASTER, CS43130_DSD_MASTER);
else
regmap_update_bits(cs43130->regmap, CS43130_DSD_INT_CFG,
CS43130_DSD_MASTER, 0);
regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2,
CS43130_DSD_SPEED_MASK,
dsd_speed << CS43130_DSD_SPEED_SHIFT);
regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2,
CS43130_DSD_SRC_MASK, CS43130_DSD_SRC_DSD <<
CS43130_DSD_SRC_SHIFT);
return 0;
}
static int cs43130_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
const struct cs43130_rate_map *rate_map;
unsigned int sclk = cs43130->dais[dai->id].sclk;
unsigned int bitwidth_sclk;
unsigned int bitwidth_dai = (unsigned int)(params_width(params));
unsigned int required_clk;
u8 dsd_speed;
mutex_lock(&cs43130->clk_mutex);
if (!cs43130->clk_req) {
/* no DAI is currently using clk */
if (!(CS43130_MCLK_22M % params_rate(params)))
required_clk = CS43130_MCLK_22M;
else
required_clk = CS43130_MCLK_24M;
cs43130_set_pll(component, 0, 0, cs43130->mclk, required_clk);
if (cs43130->pll_bypass)
cs43130_change_clksrc(component, CS43130_MCLK_SRC_EXT);
else
cs43130_change_clksrc(component, CS43130_MCLK_SRC_PLL);
}
cs43130->clk_req++;
if (cs43130->clk_req == 2)
cs43130_pcm_dsd_mix(true, cs43130->regmap);
mutex_unlock(&cs43130->clk_mutex);
switch (dai->id) {
case CS43130_ASP_DOP_DAI:
case CS43130_XSP_DOP_DAI:
/* DoP bitwidth is always 24-bit */
bitwidth_dai = 24;
sclk = params_rate(params) * bitwidth_dai *
params_channels(params);
switch (params_rate(params)) {
case 176400:
dsd_speed = 0;
break;
case 352800:
dsd_speed = 1;
break;
default:
dev_err(component->dev, "Rate(%u) not supported\n",
params_rate(params));
return -EINVAL;
}
regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2,
CS43130_DSD_SPEED_MASK,
dsd_speed << CS43130_DSD_SPEED_SHIFT);
break;
case CS43130_ASP_PCM_DAI:
rate_map = cs43130_get_rate_table(params_rate(params));
if (!rate_map)
return -EINVAL;
regmap_write(cs43130->regmap, CS43130_SP_SRATE, rate_map->val);
break;
default:
dev_err(component->dev, "Invalid DAI (%d)\n", dai->id);
return -EINVAL;
}
switch (dai->id) {
case CS43130_ASP_DOP_DAI:
regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2,
CS43130_DSD_SRC_MASK, CS43130_DSD_SRC_ASP <<
CS43130_DSD_SRC_SHIFT);
break;
case CS43130_XSP_DOP_DAI:
regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2,
CS43130_DSD_SRC_MASK, CS43130_DSD_SRC_XSP <<
CS43130_DSD_SRC_SHIFT);
break;
}
if (!sclk && cs43130->dais[dai->id].dai_mode == SND_SOC_DAIFMT_CBM_CFM)
/* Calculate SCLK in master mode if unassigned */
sclk = params_rate(params) * bitwidth_dai *
params_channels(params);
if (!sclk) {
/* at this point, SCLK must be set */
dev_err(component->dev, "SCLK freq is not set\n");
return -EINVAL;
}
bitwidth_sclk = (sclk / params_rate(params)) / params_channels(params);
if (bitwidth_sclk < bitwidth_dai) {
dev_err(component->dev, "Format not supported: SCLK freq is too low\n");
return -EINVAL;
}
dev_dbg(component->dev,
"sclk = %u, fs = %d, bitwidth_dai = %u\n",
sclk, params_rate(params), bitwidth_dai);
dev_dbg(component->dev,
"bitwidth_sclk = %u, num_ch = %u\n",
bitwidth_sclk, params_channels(params));
cs43130_set_bitwidth(dai->id, bitwidth_dai, cs43130->regmap);
cs43130_set_sp_fmt(dai->id, bitwidth_sclk, params, cs43130);
return 0;
}
static int cs43130_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
mutex_lock(&cs43130->clk_mutex);
cs43130->clk_req--;
if (!cs43130->clk_req) {
/* no DAI is currently using clk */
cs43130_change_clksrc(component, CS43130_MCLK_SRC_RCO);
cs43130_pcm_dsd_mix(false, cs43130->regmap);
}
mutex_unlock(&cs43130->clk_mutex);
return 0;
}
static const DECLARE_TLV_DB_SCALE(pcm_vol_tlv, -12750, 50, 1);
static const char * const pcm_ch_text[] = {
"Left-Right Ch",
"Left-Left Ch",
"Right-Left Ch",
"Right-Right Ch",
};
static const struct reg_sequence pcm_ch_en_seq[] = {
{CS43130_DXD1, 0x99},
{0x180005, 0x8C},
{0x180007, 0xAB},
{0x180015, 0x31},
{0x180017, 0xB2},
{0x180025, 0x30},
{0x180027, 0x84},
{0x180035, 0x9C},
{0x180037, 0xAE},
{0x18000D, 0x24},
{0x18000F, 0xA3},
{0x18001D, 0x05},
{0x18001F, 0xD4},
{0x18002D, 0x0B},
{0x18002F, 0xC7},
{0x18003D, 0x71},
{0x18003F, 0xE7},
{CS43130_DXD1, 0},
};
static const struct reg_sequence pcm_ch_dis_seq[] = {
{CS43130_DXD1, 0x99},
{0x180005, 0x24},
{0x180007, 0xA3},
{0x180015, 0x05},
{0x180017, 0xD4},
{0x180025, 0x0B},
{0x180027, 0xC7},
{0x180035, 0x71},
{0x180037, 0xE7},
{0x18000D, 0x8C},
{0x18000F, 0xAB},
{0x18001D, 0x31},
{0x18001F, 0xB2},
{0x18002D, 0x30},
{0x18002F, 0x84},
{0x18003D, 0x9C},
{0x18003F, 0xAE},
{CS43130_DXD1, 0},
};
static int cs43130_pcm_ch_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
return snd_soc_get_enum_double(kcontrol, ucontrol);
}
static int cs43130_pcm_ch_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int *item = ucontrol->value.enumerated.item;
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
unsigned int val;
if (item[0] >= e->items)
return -EINVAL;
val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
switch (cs43130->dev_id) {
case CS43131_CHIP_ID:
case CS43198_CHIP_ID:
if (val >= 2)
regmap_multi_reg_write(cs43130->regmap, pcm_ch_en_seq,
ARRAY_SIZE(pcm_ch_en_seq));
else
regmap_multi_reg_write(cs43130->regmap, pcm_ch_dis_seq,
ARRAY_SIZE(pcm_ch_dis_seq));
break;
}
return snd_soc_put_enum_double(kcontrol, ucontrol);
}
static SOC_ENUM_SINGLE_DECL(pcm_ch_enum, CS43130_PCM_PATH_CTL_2, 0,
pcm_ch_text);
static const char * const pcm_spd_texts[] = {
"Fast",
"Slow",
};
static SOC_ENUM_SINGLE_DECL(pcm_spd_enum, CS43130_PCM_FILT_OPT, 7,
pcm_spd_texts);
static const char * const dsd_texts[] = {
"Off",
"BCKA Mode",
"BCKD Mode",
};
static const unsigned int dsd_values[] = {
CS43130_DSD_SRC_DSD,
CS43130_DSD_SRC_ASP,
CS43130_DSD_SRC_XSP,
};
static SOC_VALUE_ENUM_SINGLE_DECL(dsd_enum, CS43130_DSD_INT_CFG, 0, 0x03,
dsd_texts, dsd_values);
static const struct snd_kcontrol_new cs43130_snd_controls[] = {
SOC_DOUBLE_R_TLV("Master Playback Volume",
CS43130_PCM_VOL_A, CS43130_PCM_VOL_B, 0, 0xFF, 1,
pcm_vol_tlv),
SOC_DOUBLE_R_TLV("Master DSD Playback Volume",
CS43130_DSD_VOL_A, CS43130_DSD_VOL_B, 0, 0xFF, 1,
pcm_vol_tlv),
SOC_ENUM_EXT("PCM Ch Select", pcm_ch_enum, cs43130_pcm_ch_get,
cs43130_pcm_ch_put),
SOC_ENUM("PCM Filter Speed", pcm_spd_enum),
SOC_SINGLE("PCM Phase Compensation", CS43130_PCM_FILT_OPT, 6, 1, 0),
SOC_SINGLE("PCM Nonoversample Emulate", CS43130_PCM_FILT_OPT, 5, 1, 0),
SOC_SINGLE("PCM High-pass Filter", CS43130_PCM_FILT_OPT, 1, 1, 0),
SOC_SINGLE("PCM De-emphasis Filter", CS43130_PCM_FILT_OPT, 0, 1, 0),
SOC_ENUM("DSD Phase Modulation", dsd_enum),
};
static const struct reg_sequence pcm_seq[] = {
{CS43130_DXD1, 0x99},
{CS43130_DXD7, 0x01},
{CS43130_DXD8, 0},
{CS43130_DXD9, 0x01},
{CS43130_DXD3, 0x12},
{CS43130_DXD4, 0},
{CS43130_DXD10, 0x28},
{CS43130_DXD11, 0x28},
{CS43130_DXD1, 0},
};
static const struct reg_sequence dsd_seq[] = {
{CS43130_DXD1, 0x99},
{CS43130_DXD7, 0x01},
{CS43130_DXD8, 0},
{CS43130_DXD9, 0x01},
{CS43130_DXD3, 0x12},
{CS43130_DXD4, 0},
{CS43130_DXD10, 0x1E},
{CS43130_DXD11, 0x20},
{CS43130_DXD1, 0},
};
static const struct reg_sequence pop_free_seq[] = {
{CS43130_DXD1, 0x99},
{CS43130_DXD12, 0x0A},
{CS43130_DXD1, 0},
};
static const struct reg_sequence pop_free_seq2[] = {
{CS43130_DXD1, 0x99},
{CS43130_DXD13, 0x20},
{CS43130_DXD1, 0},
};
static const struct reg_sequence mute_seq[] = {
{CS43130_DXD1, 0x99},
{CS43130_DXD3, 0x12},
{CS43130_DXD5, 0x02},
{CS43130_DXD4, 0x12},
{CS43130_DXD1, 0},
};
static const struct reg_sequence unmute_seq[] = {
{CS43130_DXD1, 0x99},
{CS43130_DXD3, 0x10},
{CS43130_DXD5, 0},
{CS43130_DXD4, 0x16},
{CS43130_DXD1, 0},
};
static int cs43130_dsd_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
switch (cs43130->dev_id) {
case CS43130_CHIP_ID:
case CS4399_CHIP_ID:
regmap_multi_reg_write(cs43130->regmap, dsd_seq,
ARRAY_SIZE(dsd_seq));
break;
}
break;
case SND_SOC_DAPM_POST_PMU:
regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_1,
CS43130_MUTE_MASK, 0);
switch (cs43130->dev_id) {
case CS43130_CHIP_ID:
case CS4399_CHIP_ID:
regmap_multi_reg_write(cs43130->regmap, unmute_seq,
ARRAY_SIZE(unmute_seq));
break;
}
break;
case SND_SOC_DAPM_PRE_PMD:
switch (cs43130->dev_id) {
case CS43130_CHIP_ID:
case CS4399_CHIP_ID:
regmap_multi_reg_write(cs43130->regmap, mute_seq,
ARRAY_SIZE(mute_seq));
regmap_update_bits(cs43130->regmap,
CS43130_DSD_PATH_CTL_1,
CS43130_MUTE_MASK, CS43130_MUTE_EN);
/*
* DSD Power Down Sequence
* According to Design, 130ms is preferred.
*/
msleep(130);
break;
case CS43131_CHIP_ID:
case CS43198_CHIP_ID:
regmap_update_bits(cs43130->regmap,
CS43130_DSD_PATH_CTL_1,
CS43130_MUTE_MASK, CS43130_MUTE_EN);
break;
}
break;
default:
dev_err(component->dev, "Invalid event = 0x%x\n", event);
return -EINVAL;
}
return 0;
}
static int cs43130_pcm_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
switch (cs43130->dev_id) {
case CS43130_CHIP_ID:
case CS4399_CHIP_ID:
regmap_multi_reg_write(cs43130->regmap, pcm_seq,
ARRAY_SIZE(pcm_seq));
break;
}
break;
case SND_SOC_DAPM_POST_PMU:
regmap_update_bits(cs43130->regmap, CS43130_PCM_PATH_CTL_1,
CS43130_MUTE_MASK, 0);
switch (cs43130->dev_id) {
case CS43130_CHIP_ID:
case CS4399_CHIP_ID:
regmap_multi_reg_write(cs43130->regmap, unmute_seq,
ARRAY_SIZE(unmute_seq));
break;
}
break;
case SND_SOC_DAPM_PRE_PMD:
switch (cs43130->dev_id) {
case CS43130_CHIP_ID:
case CS4399_CHIP_ID:
regmap_multi_reg_write(cs43130->regmap, mute_seq,
ARRAY_SIZE(mute_seq));
regmap_update_bits(cs43130->regmap,
CS43130_PCM_PATH_CTL_1,
CS43130_MUTE_MASK, CS43130_MUTE_EN);
/*
* PCM Power Down Sequence
* According to Design, 130ms is preferred.
*/
msleep(130);
break;
case CS43131_CHIP_ID:
case CS43198_CHIP_ID:
regmap_update_bits(cs43130->regmap,
CS43130_PCM_PATH_CTL_1,
CS43130_MUTE_MASK, CS43130_MUTE_EN);
break;
}
break;
default:
dev_err(component->dev, "Invalid event = 0x%x\n", event);
return -EINVAL;
}
return 0;
}
static const struct reg_sequence dac_postpmu_seq[] = {
{CS43130_DXD9, 0x0C},
{CS43130_DXD3, 0x10},
{CS43130_DXD4, 0x20},
};
static const struct reg_sequence dac_postpmd_seq[] = {
{CS43130_DXD1, 0x99},
{CS43130_DXD6, 0x01},
{CS43130_DXD1, 0},
};
static int cs43130_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
switch (cs43130->dev_id) {
case CS43130_CHIP_ID:
case CS4399_CHIP_ID:
regmap_multi_reg_write(cs43130->regmap, pop_free_seq,
ARRAY_SIZE(pop_free_seq));
break;
case CS43131_CHIP_ID:
case CS43198_CHIP_ID:
regmap_multi_reg_write(cs43130->regmap, pop_free_seq2,
ARRAY_SIZE(pop_free_seq2));
break;
}
break;
case SND_SOC_DAPM_POST_PMU:
usleep_range(10000, 10050);
regmap_write(cs43130->regmap, CS43130_DXD1, 0x99);
switch (cs43130->dev_id) {
case CS43130_CHIP_ID:
case CS4399_CHIP_ID:
regmap_multi_reg_write(cs43130->regmap, dac_postpmu_seq,
ARRAY_SIZE(dac_postpmu_seq));
/*
* Per datasheet, Sec. PCM Power-Up Sequence.
* According to Design, CS43130_DXD12 must be 0 to meet
* THDN and Dynamic Range spec.
*/
msleep(1000);
regmap_write(cs43130->regmap, CS43130_DXD12, 0);
break;
case CS43131_CHIP_ID:
case CS43198_CHIP_ID:
usleep_range(12000, 12010);
regmap_write(cs43130->regmap, CS43130_DXD13, 0);
break;
}
regmap_write(cs43130->regmap, CS43130_DXD1, 0);
break;
case SND_SOC_DAPM_POST_PMD:
switch (cs43130->dev_id) {
case CS43130_CHIP_ID:
case CS4399_CHIP_ID:
regmap_multi_reg_write(cs43130->regmap, dac_postpmd_seq,
ARRAY_SIZE(dac_postpmd_seq));
break;
}
break;
default:
dev_err(component->dev, "Invalid DAC event = 0x%x\n", event);
return -EINVAL;
}
return 0;
}
static const struct reg_sequence hpin_prepmd_seq[] = {
{CS43130_DXD1, 0x99},
{CS43130_DXD15, 0x64},
{CS43130_DXD14, 0},
{CS43130_DXD2, 0},
{CS43130_DXD1, 0},
};
static const struct reg_sequence hpin_postpmu_seq[] = {
{CS43130_DXD1, 0x99},
{CS43130_DXD2, 1},
{CS43130_DXD14, 0xDC},
{CS43130_DXD15, 0xE4},
{CS43130_DXD1, 0},
};
static int cs43130_hpin_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMD:
regmap_multi_reg_write(cs43130->regmap, hpin_prepmd_seq,
ARRAY_SIZE(hpin_prepmd_seq));
break;
case SND_SOC_DAPM_PRE_PMU:
regmap_multi_reg_write(cs43130->regmap, hpin_postpmu_seq,
ARRAY_SIZE(hpin_postpmu_seq));
break;
default:
dev_err(component->dev, "Invalid HPIN event = 0x%x\n", event);
return -EINVAL;
}
return 0;
}
static const struct snd_soc_dapm_widget digital_hp_widgets[] = {
SND_SOC_DAPM_OUTPUT("HPOUTA"),
SND_SOC_DAPM_OUTPUT("HPOUTB"),
SND_SOC_DAPM_AIF_IN_E("ASPIN PCM", NULL, 0, CS43130_PWDN_CTL,
CS43130_PDN_ASP_SHIFT, 1, cs43130_pcm_event,
(SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD)),
SND_SOC_DAPM_AIF_IN_E("ASPIN DoP", NULL, 0, CS43130_PWDN_CTL,
CS43130_PDN_ASP_SHIFT, 1, cs43130_dsd_event,
(SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD)),
SND_SOC_DAPM_AIF_IN_E("XSPIN DoP", NULL, 0, CS43130_PWDN_CTL,
CS43130_PDN_XSP_SHIFT, 1, cs43130_dsd_event,
(SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD)),
SND_SOC_DAPM_AIF_IN_E("XSPIN DSD", NULL, 0, CS43130_PWDN_CTL,
CS43130_PDN_DSDIF_SHIFT, 1, cs43130_dsd_event,
(SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD)),
SND_SOC_DAPM_DAC("DSD", NULL, CS43130_DSD_PATH_CTL_2,
CS43130_DSD_EN_SHIFT, 0),
SND_SOC_DAPM_DAC_E("HiFi DAC", NULL, CS43130_PWDN_CTL,
CS43130_PDN_HP_SHIFT, 1, cs43130_dac_event,
(SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD)),
};
static const struct snd_soc_dapm_widget analog_hp_widgets[] = {
SND_SOC_DAPM_DAC_E("Analog Playback", NULL, CS43130_HP_OUT_CTL_1,
CS43130_HP_IN_EN_SHIFT, 0, cs43130_hpin_event,
(SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD)),
};
static struct snd_soc_dapm_widget all_hp_widgets[
ARRAY_SIZE(digital_hp_widgets) +
ARRAY_SIZE(analog_hp_widgets)];
static const struct snd_soc_dapm_route digital_hp_routes[] = {
{"ASPIN PCM", NULL, "ASP PCM Playback"},
{"ASPIN DoP", NULL, "ASP DoP Playback"},
{"XSPIN DoP", NULL, "XSP DoP Playback"},
{"XSPIN DSD", NULL, "XSP DSD Playback"},
{"DSD", NULL, "ASPIN DoP"},
{"DSD", NULL, "XSPIN DoP"},
{"DSD", NULL, "XSPIN DSD"},
{"HiFi DAC", NULL, "ASPIN PCM"},
{"HiFi DAC", NULL, "DSD"},
{"HPOUTA", NULL, "HiFi DAC"},
{"HPOUTB", NULL, "HiFi DAC"},
};
static const struct snd_soc_dapm_route analog_hp_routes[] = {
{"HPOUTA", NULL, "Analog Playback"},
{"HPOUTB", NULL, "Analog Playback"},
};
static struct snd_soc_dapm_route all_hp_routes[
ARRAY_SIZE(digital_hp_routes) +
ARRAY_SIZE(analog_hp_routes)];
static const unsigned int cs43130_asp_src_rates[] = {
32000, 44100, 48000, 88200, 96000, 176400, 192000, 352800, 384000
};
static const struct snd_pcm_hw_constraint_list cs43130_asp_constraints = {
.count = ARRAY_SIZE(cs43130_asp_src_rates),
.list = cs43130_asp_src_rates,
};
static int cs43130_pcm_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
return snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&cs43130_asp_constraints);
}
static const unsigned int cs43130_dop_src_rates[] = {
176400, 352800,
};
static const struct snd_pcm_hw_constraint_list cs43130_dop_constraints = {
.count = ARRAY_SIZE(cs43130_dop_src_rates),
.list = cs43130_dop_src_rates,
};
static int cs43130_dop_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
return snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&cs43130_dop_constraints);
}
static int cs43130_pcm_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBS_CFS;
break;
case SND_SOC_DAIFMT_CBM_CFM:
cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBM_CFM;
break;
default:
dev_err(component->dev, "unsupported mode\n");
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_LEFT_J;
break;
case SND_SOC_DAIFMT_DSP_A:
cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_DSP_A;
break;
case SND_SOC_DAIFMT_DSP_B:
cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_DSP_B;
break;
default:
dev_err(component->dev,
"unsupported audio format\n");
return -EINVAL;
}
dev_dbg(component->dev, "dai_id = %d, dai_mode = %u, dai_format = %u\n",
codec_dai->id,
cs43130->dais[codec_dai->id].dai_mode,
cs43130->dais[codec_dai->id].dai_format);
return 0;
}
static int cs43130_dsd_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBS_CFS;
break;
case SND_SOC_DAIFMT_CBM_CFM:
cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBM_CFM;
break;
default:
dev_err(component->dev, "Unsupported DAI format.\n");
return -EINVAL;
}
dev_dbg(component->dev, "dai_mode = 0x%x\n",
cs43130->dais[codec_dai->id].dai_mode);
return 0;
}
static int cs43130_set_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
cs43130->dais[codec_dai->id].sclk = freq;
dev_dbg(component->dev, "dai_id = %d, sclk = %u\n", codec_dai->id,
cs43130->dais[codec_dai->id].sclk);
return 0;
}
static const struct snd_soc_dai_ops cs43130_pcm_ops = {
.startup = cs43130_pcm_startup,
.hw_params = cs43130_hw_params,
.hw_free = cs43130_hw_free,
.set_sysclk = cs43130_set_sysclk,
.set_fmt = cs43130_pcm_set_fmt,
};
static const struct snd_soc_dai_ops cs43130_dop_ops = {
.startup = cs43130_dop_startup,
.hw_params = cs43130_hw_params,
.hw_free = cs43130_hw_free,
.set_sysclk = cs43130_set_sysclk,
.set_fmt = cs43130_pcm_set_fmt,
};
static const struct snd_soc_dai_ops cs43130_dsd_ops = {
.startup = cs43130_dop_startup,
.hw_params = cs43130_dsd_hw_params,
.hw_free = cs43130_hw_free,
.set_fmt = cs43130_dsd_set_fmt,
};
static struct snd_soc_dai_driver cs43130_dai[] = {
{
.name = "cs43130-asp-pcm",
.id = CS43130_ASP_PCM_DAI,
.playback = {
.stream_name = "ASP PCM Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = CS43130_PCM_FORMATS,
},
.ops = &cs43130_pcm_ops,
.symmetric_rate = 1,
},
{
.name = "cs43130-asp-dop",
.id = CS43130_ASP_DOP_DAI,
.playback = {
.stream_name = "ASP DoP Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = CS43130_DOP_FORMATS,
},
.ops = &cs43130_dop_ops,
.symmetric_rate = 1,
},
{
.name = "cs43130-xsp-dop",
.id = CS43130_XSP_DOP_DAI,
.playback = {
.stream_name = "XSP DoP Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = CS43130_DOP_FORMATS,
},
.ops = &cs43130_dop_ops,
.symmetric_rate = 1,
},
{
.name = "cs43130-xsp-dsd",
.id = CS43130_XSP_DSD_DAI,
.playback = {
.stream_name = "XSP DSD Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = CS43130_DOP_FORMATS,
},
.ops = &cs43130_dsd_ops,
},
};
static int cs43130_component_set_sysclk(struct snd_soc_component *component,
int clk_id, int source, unsigned int freq,
int dir)
{
struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
dev_dbg(component->dev, "clk_id = %d, source = %d, freq = %d, dir = %d\n",
clk_id, source, freq, dir);
switch (freq) {
case CS43130_MCLK_22M:
case CS43130_MCLK_24M:
cs43130->mclk = freq;
break;
default:
dev_err(component->dev, "Invalid MCLK INT freq: %u\n", freq);
return -EINVAL;
}
if (source == CS43130_MCLK_SRC_EXT) {
cs43130->pll_bypass = true;
} else {
dev_err(component->dev, "Invalid MCLK source\n");
return -EINVAL;
}
return 0;
}
static inline u16 cs43130_get_ac_reg_val(u16 ac_freq)
{
/* AC freq is counted in 5.94Hz step. */
return ac_freq / 6;
}
static int cs43130_show_dc(struct device *dev, char *buf, u8 ch)
{
struct i2c_client *client = to_i2c_client(dev);
struct cs43130_private *cs43130 = i2c_get_clientdata(client);
if (!cs43130->hpload_done)
return sysfs_emit(buf, "NO_HPLOAD\n");
else
return sysfs_emit(buf, "%u\n", cs43130->hpload_dc[ch]);
}
static ssize_t hpload_dc_l_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
return cs43130_show_dc(dev, buf, HP_LEFT);
}
static ssize_t hpload_dc_r_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
return cs43130_show_dc(dev, buf, HP_RIGHT);
}
static u16 const cs43130_ac_freq[CS43130_AC_FREQ] = {
24,
43,
93,
200,
431,
928,
2000,
4309,
9283,
20000,
};
static int cs43130_show_ac(struct device *dev, char *buf, u8 ch)
{
int i, j = 0, tmp;
struct i2c_client *client = to_i2c_client(dev);
struct cs43130_private *cs43130 = i2c_get_clientdata(client);
if (cs43130->hpload_done && cs43130->ac_meas) {
for (i = 0; i < ARRAY_SIZE(cs43130_ac_freq); i++) {
tmp = sysfs_emit_at(buf, j, "%u\n",
cs43130->hpload_ac[i][ch]);
if (!tmp)
break;
j += tmp;
}
return j;
} else {
return sysfs_emit(buf, "NO_HPLOAD\n");
}
}
static ssize_t hpload_ac_l_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
return cs43130_show_ac(dev, buf, HP_LEFT);
}
static ssize_t hpload_ac_r_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
return cs43130_show_ac(dev, buf, HP_RIGHT);
}
static DEVICE_ATTR_RO(hpload_dc_l);
static DEVICE_ATTR_RO(hpload_dc_r);
static DEVICE_ATTR_RO(hpload_ac_l);
static DEVICE_ATTR_RO(hpload_ac_r);
static struct attribute *hpload_attrs[] = {
&dev_attr_hpload_dc_l.attr,
&dev_attr_hpload_dc_r.attr,
&dev_attr_hpload_ac_l.attr,
&dev_attr_hpload_ac_r.attr,
};
ATTRIBUTE_GROUPS(hpload);
static struct reg_sequence hp_en_cal_seq[] = {
{CS43130_INT_MASK_4, CS43130_INT_MASK_ALL},
{CS43130_HP_MEAS_LOAD_1, 0},
{CS43130_HP_MEAS_LOAD_2, 0},
{CS43130_INT_MASK_4, 0},
{CS43130_DXD1, 0x99},
{CS43130_DXD16, 0xBB},
{CS43130_DXD12, 0x01},
{CS43130_DXD19, 0xCB},
{CS43130_DXD17, 0x95},
{CS43130_DXD18, 0x0B},
{CS43130_DXD1, 0},
{CS43130_HP_LOAD_1, 0x80},
};
static struct reg_sequence hp_en_cal_seq2[] = {
{CS43130_INT_MASK_4, CS43130_INT_MASK_ALL},
{CS43130_HP_MEAS_LOAD_1, 0},
{CS43130_HP_MEAS_LOAD_2, 0},
{CS43130_INT_MASK_4, 0},
{CS43130_HP_LOAD_1, 0x80},
};
static struct reg_sequence hp_dis_cal_seq[] = {
{CS43130_HP_LOAD_1, 0x80},
{CS43130_DXD1, 0x99},
{CS43130_DXD12, 0},
{CS43130_DXD1, 0},
{CS43130_HP_LOAD_1, 0},
};
static struct reg_sequence hp_dis_cal_seq2[] = {
{CS43130_HP_LOAD_1, 0x80},
{CS43130_HP_LOAD_1, 0},
};
static struct reg_sequence hp_dc_ch_l_seq[] = {
{CS43130_DXD1, 0x99},
{CS43130_DXD19, 0x0A},
{CS43130_DXD17, 0x93},
{CS43130_DXD18, 0x0A},
{CS43130_DXD1, 0},
{CS43130_HP_LOAD_1, 0x80},
{CS43130_HP_LOAD_1, 0x81},
};
static struct reg_sequence hp_dc_ch_l_seq2[] = {
{CS43130_HP_LOAD_1, 0x80},
{CS43130_HP_LOAD_1, 0x81},
};
static struct reg_sequence hp_dc_ch_r_seq[] = {
{CS43130_DXD1, 0x99},
{CS43130_DXD19, 0x8A},
{CS43130_DXD17, 0x15},
{CS43130_DXD18, 0x06},
{CS43130_DXD1, 0},
{CS43130_HP_LOAD_1, 0x90},
{CS43130_HP_LOAD_1, 0x91},
};
static struct reg_sequence hp_dc_ch_r_seq2[] = {
{CS43130_HP_LOAD_1, 0x90},
{CS43130_HP_LOAD_1, 0x91},
};
static struct reg_sequence hp_ac_ch_l_seq[] = {
{CS43130_DXD1, 0x99},
{CS43130_DXD19, 0x0A},
{CS43130_DXD17, 0x93},
{CS43130_DXD18, 0x0A},
{CS43130_DXD1, 0},
{CS43130_HP_LOAD_1, 0x80},
{CS43130_HP_LOAD_1, 0x82},
};
static struct reg_sequence hp_ac_ch_l_seq2[] = {
{CS43130_HP_LOAD_1, 0x80},
{CS43130_HP_LOAD_1, 0x82},
};
static struct reg_sequence hp_ac_ch_r_seq[] = {
{CS43130_DXD1, 0x99},
{CS43130_DXD19, 0x8A},
{CS43130_DXD17, 0x15},
{CS43130_DXD18, 0x06},
{CS43130_DXD1, 0},
{CS43130_HP_LOAD_1, 0x90},
{CS43130_HP_LOAD_1, 0x92},
};
static struct reg_sequence hp_ac_ch_r_seq2[] = {
{CS43130_HP_LOAD_1, 0x90},
{CS43130_HP_LOAD_1, 0x92},
};
static struct reg_sequence hp_cln_seq[] = {
{CS43130_INT_MASK_4, CS43130_INT_MASK_ALL},
{CS43130_HP_MEAS_LOAD_1, 0},
{CS43130_HP_MEAS_LOAD_2, 0},
};
struct reg_sequences {
struct reg_sequence *seq;
int size;
unsigned int msk;
};
static struct reg_sequences hpload_seq1[] = {
{
.seq = hp_en_cal_seq,
.size = ARRAY_SIZE(hp_en_cal_seq),
.msk = CS43130_HPLOAD_ON_INT,
},
{
.seq = hp_dc_ch_l_seq,
.size = ARRAY_SIZE(hp_dc_ch_l_seq),
.msk = CS43130_HPLOAD_DC_INT,
},
{
.seq = hp_ac_ch_l_seq,
.size = ARRAY_SIZE(hp_ac_ch_l_seq),
.msk = CS43130_HPLOAD_AC_INT,
},
{
.seq = hp_dis_cal_seq,
.size = ARRAY_SIZE(hp_dis_cal_seq),
.msk = CS43130_HPLOAD_OFF_INT,
},
{
.seq = hp_en_cal_seq,
.size = ARRAY_SIZE(hp_en_cal_seq),
.msk = CS43130_HPLOAD_ON_INT,
},
{
.seq = hp_dc_ch_r_seq,
.size = ARRAY_SIZE(hp_dc_ch_r_seq),
.msk = CS43130_HPLOAD_DC_INT,
},
{
.seq = hp_ac_ch_r_seq,
.size = ARRAY_SIZE(hp_ac_ch_r_seq),
.msk = CS43130_HPLOAD_AC_INT,
},
};
static struct reg_sequences hpload_seq2[] = {
{
.seq = hp_en_cal_seq2,
.size = ARRAY_SIZE(hp_en_cal_seq2),
.msk = CS43130_HPLOAD_ON_INT,
},
{
.seq = hp_dc_ch_l_seq2,
.size = ARRAY_SIZE(hp_dc_ch_l_seq2),
.msk = CS43130_HPLOAD_DC_INT,
},
{
.seq = hp_ac_ch_l_seq2,
.size = ARRAY_SIZE(hp_ac_ch_l_seq2),
.msk = CS43130_HPLOAD_AC_INT,
},
{
.seq = hp_dis_cal_seq2,
.size = ARRAY_SIZE(hp_dis_cal_seq2),
.msk = CS43130_HPLOAD_OFF_INT,
},
{
.seq = hp_en_cal_seq2,
.size = ARRAY_SIZE(hp_en_cal_seq2),
.msk = CS43130_HPLOAD_ON_INT,
},
{
.seq = hp_dc_ch_r_seq2,
.size = ARRAY_SIZE(hp_dc_ch_r_seq2),
.msk = CS43130_HPLOAD_DC_INT,
},
{
.seq = hp_ac_ch_r_seq2,
.size = ARRAY_SIZE(hp_ac_ch_r_seq2),
.msk = CS43130_HPLOAD_AC_INT,
},
};
static int cs43130_update_hpload(unsigned int msk, int ac_idx,
struct cs43130_private *cs43130)
{
bool left_ch = true;
unsigned int reg;
u32 addr;
u16 impedance;
struct snd_soc_component *component = cs43130->component;
switch (msk) {
case CS43130_HPLOAD_DC_INT:
case CS43130_HPLOAD_AC_INT:
break;
default:
return 0;
}
regmap_read(cs43130->regmap, CS43130_HP_LOAD_1, ®);
if (reg & CS43130_HPLOAD_CHN_SEL)
left_ch = false;
if (msk == CS43130_HPLOAD_DC_INT)
addr = CS43130_HP_DC_STAT_1;
else
addr = CS43130_HP_AC_STAT_1;
regmap_read(cs43130->regmap, addr, ®);
impedance = reg >> 3;
regmap_read(cs43130->regmap, addr + 1, ®);
impedance |= reg << 5;
if (msk == CS43130_HPLOAD_DC_INT) {
if (left_ch)
cs43130->hpload_dc[HP_LEFT] = impedance;
else
cs43130->hpload_dc[HP_RIGHT] = impedance;
dev_dbg(component->dev, "HP DC impedance (Ch %u): %u\n", !left_ch,
impedance);
} else {
if (left_ch)
cs43130->hpload_ac[ac_idx][HP_LEFT] = impedance;
else
cs43130->hpload_ac[ac_idx][HP_RIGHT] = impedance;
dev_dbg(component->dev, "HP AC (%u Hz) impedance (Ch %u): %u\n",
cs43130->ac_freq[ac_idx], !left_ch, impedance);
}
return 0;
}
static int cs43130_hpload_proc(struct cs43130_private *cs43130,
struct reg_sequence *seq, int seq_size,
unsigned int rslt_msk, int ac_idx)
{
int ret;
unsigned int msk;
u16 ac_reg_val;
struct snd_soc_component *component = cs43130->component;
reinit_completion(&cs43130->hpload_evt);
if (rslt_msk == CS43130_HPLOAD_AC_INT) {
ac_reg_val = cs43130_get_ac_reg_val(cs43130->ac_freq[ac_idx]);
regmap_update_bits(cs43130->regmap, CS43130_HP_LOAD_1,
CS43130_HPLOAD_AC_START, 0);
regmap_update_bits(cs43130->regmap, CS43130_HP_MEAS_LOAD_1,
CS43130_HP_MEAS_LOAD_MASK,
ac_reg_val >> CS43130_HP_MEAS_LOAD_1_SHIFT);
regmap_update_bits(cs43130->regmap, CS43130_HP_MEAS_LOAD_2,
CS43130_HP_MEAS_LOAD_MASK,
ac_reg_val >> CS43130_HP_MEAS_LOAD_2_SHIFT);
}
regmap_multi_reg_write(cs43130->regmap, seq,
seq_size);
ret = wait_for_completion_timeout(&cs43130->hpload_evt,
msecs_to_jiffies(1000));
regmap_read(cs43130->regmap, CS43130_INT_MASK_4, &msk);
if (!ret) {
dev_err(component->dev, "Timeout waiting for HPLOAD interrupt\n");
return -1;
}
dev_dbg(component->dev, "HP load stat: %x, INT_MASK_4: %x\n",
cs43130->hpload_stat, msk);
if ((cs43130->hpload_stat & (CS43130_HPLOAD_NO_DC_INT |
CS43130_HPLOAD_UNPLUG_INT |
CS43130_HPLOAD_OOR_INT)) ||
!(cs43130->hpload_stat & rslt_msk)) {
dev_dbg(component->dev, "HP load measure failed\n");
return -1;
}
return 0;
}
static const struct reg_sequence hv_seq[][2] = {
{
{CS43130_CLASS_H_CTL, 0x1C},
{CS43130_HP_OUT_CTL_1, 0x10},
},
{
{CS43130_CLASS_H_CTL, 0x1E},
{CS43130_HP_OUT_CTL_1, 0x20},
},
{
{CS43130_CLASS_H_CTL, 0x1E},
{CS43130_HP_OUT_CTL_1, 0x30},
},
};
static int cs43130_set_hv(struct regmap *regmap, u16 hpload_dc,
const u16 *dc_threshold)
{
int i;
for (i = 0; i < CS43130_DC_THRESHOLD; i++) {
if (hpload_dc <= dc_threshold[i])
break;
}
regmap_multi_reg_write(regmap, hv_seq[i], ARRAY_SIZE(hv_seq[i]));
return 0;
}
static void cs43130_imp_meas(struct work_struct *wk)
{
unsigned int reg, seq_size;
int i, ret, ac_idx;
struct cs43130_private *cs43130;
struct snd_soc_component *component;
struct reg_sequences *hpload_seq;
cs43130 = container_of(wk, struct cs43130_private, work);
component = cs43130->component;
if (!cs43130->mclk)
return;
cs43130->hpload_done = false;
mutex_lock(&cs43130->clk_mutex);
if (!cs43130->clk_req) {
/* clk not in use */
cs43130_set_pll(component, 0, 0, cs43130->mclk, CS43130_MCLK_22M);
if (cs43130->pll_bypass)
cs43130_change_clksrc(component, CS43130_MCLK_SRC_EXT);
else
cs43130_change_clksrc(component, CS43130_MCLK_SRC_PLL);
}
cs43130->clk_req++;
mutex_unlock(&cs43130->clk_mutex);
regmap_read(cs43130->regmap, CS43130_INT_STATUS_4, ®);
switch (cs43130->dev_id) {
case CS43130_CHIP_ID:
hpload_seq = hpload_seq1;
seq_size = ARRAY_SIZE(hpload_seq1);
break;
case CS43131_CHIP_ID:
hpload_seq = hpload_seq2;
seq_size = ARRAY_SIZE(hpload_seq2);
break;
default:
WARN(1, "Invalid dev_id for meas: %d", cs43130->dev_id);
return;
}
i = 0;
ac_idx = 0;
while (i < seq_size) {
ret = cs43130_hpload_proc(cs43130, hpload_seq[i].seq,
hpload_seq[i].size,
hpload_seq[i].msk, ac_idx);
if (ret < 0)
goto exit;
cs43130_update_hpload(hpload_seq[i].msk, ac_idx, cs43130);
if (cs43130->ac_meas &&
hpload_seq[i].msk == CS43130_HPLOAD_AC_INT &&
ac_idx < CS43130_AC_FREQ - 1) {
ac_idx++;
} else {
ac_idx = 0;
i++;
}
}
cs43130->hpload_done = true;
if (cs43130->hpload_dc[HP_LEFT] >= CS43130_LINEOUT_LOAD)
snd_soc_jack_report(&cs43130->jack, CS43130_JACK_LINEOUT,
CS43130_JACK_MASK);
else
snd_soc_jack_report(&cs43130->jack, CS43130_JACK_HEADPHONE,
CS43130_JACK_MASK);
dev_dbg(component->dev, "Set HP output control. DC threshold\n");
for (i = 0; i < CS43130_DC_THRESHOLD; i++)
dev_dbg(component->dev, "DC threshold[%d]: %u.\n", i,
cs43130->dc_threshold[i]);
cs43130_set_hv(cs43130->regmap, cs43130->hpload_dc[HP_LEFT],
cs43130->dc_threshold);
exit:
switch (cs43130->dev_id) {
case CS43130_CHIP_ID:
cs43130_hpload_proc(cs43130, hp_dis_cal_seq,
ARRAY_SIZE(hp_dis_cal_seq),
CS43130_HPLOAD_OFF_INT, ac_idx);
break;
case CS43131_CHIP_ID:
cs43130_hpload_proc(cs43130, hp_dis_cal_seq2,
ARRAY_SIZE(hp_dis_cal_seq2),
CS43130_HPLOAD_OFF_INT, ac_idx);
break;
}
regmap_multi_reg_write(cs43130->regmap, hp_cln_seq,
ARRAY_SIZE(hp_cln_seq));
mutex_lock(&cs43130->clk_mutex);
cs43130->clk_req--;
/* clk not in use */
if (!cs43130->clk_req)
cs43130_change_clksrc(component, CS43130_MCLK_SRC_RCO);
mutex_unlock(&cs43130->clk_mutex);
}
static irqreturn_t cs43130_irq_thread(int irq, void *data)
{
struct cs43130_private *cs43130 = (struct cs43130_private *)data;
struct snd_soc_component *component = cs43130->component;
unsigned int stickies[CS43130_NUM_INT];
unsigned int irq_occurrence = 0;
unsigned int masks[CS43130_NUM_INT];
int i, j;
for (i = 0; i < ARRAY_SIZE(stickies); i++) {
regmap_read(cs43130->regmap, CS43130_INT_STATUS_1 + i,
&stickies[i]);
regmap_read(cs43130->regmap, CS43130_INT_MASK_1 + i,
&masks[i]);
}
for (i = 0; i < ARRAY_SIZE(stickies); i++) {
stickies[i] = stickies[i] & (~masks[i]);
for (j = 0; j < 8; j++)
irq_occurrence += (stickies[i] >> j) & 1;
}
dev_dbg(component->dev, "number of interrupts occurred (%u)\n",
irq_occurrence);
if (!irq_occurrence)
return IRQ_NONE;
if (stickies[0] & CS43130_XTAL_RDY_INT) {
complete(&cs43130->xtal_rdy);
return IRQ_HANDLED;
}
if (stickies[0] & CS43130_PLL_RDY_INT) {
complete(&cs43130->pll_rdy);
return IRQ_HANDLED;
}
if (stickies[3] & CS43130_HPLOAD_NO_DC_INT) {
cs43130->hpload_stat = stickies[3];
dev_err(component->dev,
"DC load has not completed before AC load (%x)\n",
cs43130->hpload_stat);
complete(&cs43130->hpload_evt);
return IRQ_HANDLED;
}
if (stickies[3] & CS43130_HPLOAD_UNPLUG_INT) {
cs43130->hpload_stat = stickies[3];
dev_err(component->dev, "HP unplugged during measurement (%x)\n",
cs43130->hpload_stat);
complete(&cs43130->hpload_evt);
return IRQ_HANDLED;
}
if (stickies[3] & CS43130_HPLOAD_OOR_INT) {
cs43130->hpload_stat = stickies[3];
dev_err(component->dev, "HP load out of range (%x)\n",
cs43130->hpload_stat);
complete(&cs43130->hpload_evt);
return IRQ_HANDLED;
}
if (stickies[3] & CS43130_HPLOAD_AC_INT) {
cs43130->hpload_stat = stickies[3];
dev_dbg(component->dev, "HP AC load measurement done (%x)\n",
cs43130->hpload_stat);
complete(&cs43130->hpload_evt);
return IRQ_HANDLED;
}
if (stickies[3] & CS43130_HPLOAD_DC_INT) {
cs43130->hpload_stat = stickies[3];
dev_dbg(component->dev, "HP DC load measurement done (%x)\n",
cs43130->hpload_stat);
complete(&cs43130->hpload_evt);
return IRQ_HANDLED;
}
if (stickies[3] & CS43130_HPLOAD_ON_INT) {
cs43130->hpload_stat = stickies[3];
dev_dbg(component->dev, "HP load state machine on done (%x)\n",
cs43130->hpload_stat);
complete(&cs43130->hpload_evt);
return IRQ_HANDLED;
}
if (stickies[3] & CS43130_HPLOAD_OFF_INT) {
cs43130->hpload_stat = stickies[3];
dev_dbg(component->dev, "HP load state machine off done (%x)\n",
cs43130->hpload_stat);
complete(&cs43130->hpload_evt);
return IRQ_HANDLED;
}
if (stickies[0] & CS43130_XTAL_ERR_INT) {
dev_err(component->dev, "Crystal err: clock is not running\n");
return IRQ_HANDLED;
}
if (stickies[0] & CS43130_HP_UNPLUG_INT) {
dev_dbg(component->dev, "HP unplugged\n");
cs43130->hpload_done = false;
snd_soc_jack_report(&cs43130->jack, 0, CS43130_JACK_MASK);
return IRQ_HANDLED;
}
if (stickies[0] & CS43130_HP_PLUG_INT) {
if (cs43130->dc_meas && !cs43130->hpload_done &&
!work_busy(&cs43130->work)) {
dev_dbg(component->dev, "HP load queue work\n");
queue_work(cs43130->wq, &cs43130->work);
}
snd_soc_jack_report(&cs43130->jack, SND_JACK_MECHANICAL,
CS43130_JACK_MASK);
return IRQ_HANDLED;
}
return IRQ_NONE;
}
static int cs43130_probe(struct snd_soc_component *component)
{
int ret;
struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
struct snd_soc_card *card = component->card;
unsigned int reg;
cs43130->component = component;
if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED) {
regmap_update_bits(cs43130->regmap, CS43130_CRYSTAL_SET,
CS43130_XTAL_IBIAS_MASK,
cs43130->xtal_ibias);
regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
CS43130_XTAL_ERR_INT, 0);
}
ret = snd_soc_card_jack_new(card, "Headphone", CS43130_JACK_MASK,
&cs43130->jack);
if (ret < 0) {
dev_err(component->dev, "Cannot create jack\n");
return ret;
}
cs43130->hpload_done = false;
if (cs43130->dc_meas) {
ret = sysfs_create_groups(&component->dev->kobj, hpload_groups);
if (ret)
return ret;
cs43130->wq = create_singlethread_workqueue("cs43130_hp");
if (!cs43130->wq) {
sysfs_remove_groups(&component->dev->kobj, hpload_groups);
return -ENOMEM;
}
INIT_WORK(&cs43130->work, cs43130_imp_meas);
}
regmap_read(cs43130->regmap, CS43130_INT_STATUS_1, ®);
regmap_read(cs43130->regmap, CS43130_HP_STATUS, ®);
regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
CS43130_HP_PLUG_INT | CS43130_HP_UNPLUG_INT, 0);
regmap_update_bits(cs43130->regmap, CS43130_HP_DETECT,
CS43130_HP_DETECT_CTRL_MASK, 0);
regmap_update_bits(cs43130->regmap, CS43130_HP_DETECT,
CS43130_HP_DETECT_CTRL_MASK,
CS43130_HP_DETECT_CTRL_MASK);
return 0;
}
static struct snd_soc_component_driver soc_component_dev_cs43130 = {
.probe = cs43130_probe,
.controls = cs43130_snd_controls,
.num_controls = ARRAY_SIZE(cs43130_snd_controls),
.set_sysclk = cs43130_component_set_sysclk,
.set_pll = cs43130_set_pll,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config cs43130_regmap = {
.reg_bits = 24,
.pad_bits = 8,
.val_bits = 8,
.max_register = CS43130_LASTREG,
.reg_defaults = cs43130_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(cs43130_reg_defaults),
.readable_reg = cs43130_readable_register,
.precious_reg = cs43130_precious_register,
.volatile_reg = cs43130_volatile_register,
.cache_type = REGCACHE_MAPLE,
/* needed for regcache_sync */
.use_single_read = true,
.use_single_write = true,
};
static u16 const cs43130_dc_threshold[CS43130_DC_THRESHOLD] = {
50,
120,
};
static int cs43130_handle_device_data(struct i2c_client *i2c_client,
struct cs43130_private *cs43130)
{
struct device_node *np = i2c_client->dev.of_node;
unsigned int val;
int i;
if (of_property_read_u32(np, "cirrus,xtal-ibias", &val) < 0) {
/* Crystal is unused. System clock is used for external MCLK */
cs43130->xtal_ibias = CS43130_XTAL_UNUSED;
return 0;
}
switch (val) {
case 1:
cs43130->xtal_ibias = CS43130_XTAL_IBIAS_7_5UA;
break;
case 2:
cs43130->xtal_ibias = CS43130_XTAL_IBIAS_12_5UA;
break;
case 3:
cs43130->xtal_ibias = CS43130_XTAL_IBIAS_15UA;
break;
default:
dev_err(&i2c_client->dev,
"Invalid cirrus,xtal-ibias value: %d\n", val);
return -EINVAL;
}
cs43130->dc_meas = of_property_read_bool(np, "cirrus,dc-measure");
cs43130->ac_meas = of_property_read_bool(np, "cirrus,ac-measure");
if (of_property_read_u16_array(np, "cirrus,ac-freq", cs43130->ac_freq,
CS43130_AC_FREQ) < 0) {
for (i = 0; i < CS43130_AC_FREQ; i++)
cs43130->ac_freq[i] = cs43130_ac_freq[i];
}
if (of_property_read_u16_array(np, "cirrus,dc-threshold",
cs43130->dc_threshold,
CS43130_DC_THRESHOLD) < 0) {
for (i = 0; i < CS43130_DC_THRESHOLD; i++)
cs43130->dc_threshold[i] = cs43130_dc_threshold[i];
}
return 0;
}
static int cs43130_i2c_probe(struct i2c_client *client)
{
struct cs43130_private *cs43130;
int ret;
unsigned int reg;
int i, devid;
cs43130 = devm_kzalloc(&client->dev, sizeof(*cs43130), GFP_KERNEL);
if (!cs43130)
return -ENOMEM;
i2c_set_clientdata(client, cs43130);
cs43130->regmap = devm_regmap_init_i2c(client, &cs43130_regmap);
if (IS_ERR(cs43130->regmap)) {
ret = PTR_ERR(cs43130->regmap);
return ret;
}
if (client->dev.of_node) {
ret = cs43130_handle_device_data(client, cs43130);
if (ret != 0)
return ret;
}
for (i = 0; i < ARRAY_SIZE(cs43130->supplies); i++)
cs43130->supplies[i].supply = cs43130_supply_names[i];
ret = devm_regulator_bulk_get(&client->dev,
ARRAY_SIZE(cs43130->supplies),
cs43130->supplies);
if (ret != 0) {
dev_err(&client->dev, "Failed to request supplies: %d\n", ret);
return ret;
}
ret = regulator_bulk_enable(ARRAY_SIZE(cs43130->supplies),
cs43130->supplies);
if (ret != 0) {
dev_err(&client->dev, "Failed to enable supplies: %d\n", ret);
return ret;
}
cs43130->reset_gpio = devm_gpiod_get_optional(&client->dev,
"reset", GPIOD_OUT_LOW);
if (IS_ERR(cs43130->reset_gpio)) {
ret = PTR_ERR(cs43130->reset_gpio);
goto err_supplies;
}
gpiod_set_value_cansleep(cs43130->reset_gpio, 1);
usleep_range(2000, 2050);
devid = cirrus_read_device_id(cs43130->regmap, CS43130_DEVID_AB);
if (devid < 0) {
ret = devid;
dev_err(&client->dev, "Failed to read device ID: %d\n", ret);
goto err;
}
switch (devid) {
case CS43130_CHIP_ID:
case CS4399_CHIP_ID:
case CS43131_CHIP_ID:
case CS43198_CHIP_ID:
break;
default:
dev_err(&client->dev,
"CS43130 Device ID %X. Expected ID %X, %X, %X or %X\n",
devid, CS43130_CHIP_ID, CS4399_CHIP_ID,
CS43131_CHIP_ID, CS43198_CHIP_ID);
ret = -ENODEV;
goto err;
}
cs43130->dev_id = devid;
ret = regmap_read(cs43130->regmap, CS43130_REV_ID, ®);
if (ret < 0) {
dev_err(&client->dev, "Get Revision ID failed\n");
goto err;
}
dev_info(&client->dev,
"Cirrus Logic CS43130 (%x), Revision: %02X\n", devid,
reg & 0xFF);
mutex_init(&cs43130->clk_mutex);
init_completion(&cs43130->xtal_rdy);
init_completion(&cs43130->pll_rdy);
init_completion(&cs43130->hpload_evt);
ret = devm_request_threaded_irq(&client->dev, client->irq,
NULL, cs43130_irq_thread,
IRQF_ONESHOT | IRQF_TRIGGER_LOW,
"cs43130", cs43130);
if (ret != 0) {
dev_err(&client->dev, "Failed to request IRQ: %d\n", ret);
goto err;
}
cs43130->mclk_int_src = CS43130_MCLK_SRC_RCO;
pm_runtime_set_autosuspend_delay(&client->dev, 100);
pm_runtime_use_autosuspend(&client->dev);
pm_runtime_set_active(&client->dev);
pm_runtime_enable(&client->dev);
switch (cs43130->dev_id) {
case CS43130_CHIP_ID:
case CS43131_CHIP_ID:
memcpy(all_hp_widgets, digital_hp_widgets,
sizeof(digital_hp_widgets));
memcpy(all_hp_widgets + ARRAY_SIZE(digital_hp_widgets),
analog_hp_widgets, sizeof(analog_hp_widgets));
memcpy(all_hp_routes, digital_hp_routes,
sizeof(digital_hp_routes));
memcpy(all_hp_routes + ARRAY_SIZE(digital_hp_routes),
analog_hp_routes, sizeof(analog_hp_routes));
soc_component_dev_cs43130.dapm_widgets =
all_hp_widgets;
soc_component_dev_cs43130.num_dapm_widgets =
ARRAY_SIZE(all_hp_widgets);
soc_component_dev_cs43130.dapm_routes =
all_hp_routes;
soc_component_dev_cs43130.num_dapm_routes =
ARRAY_SIZE(all_hp_routes);
break;
case CS43198_CHIP_ID:
case CS4399_CHIP_ID:
soc_component_dev_cs43130.dapm_widgets =
digital_hp_widgets;
soc_component_dev_cs43130.num_dapm_widgets =
ARRAY_SIZE(digital_hp_widgets);
soc_component_dev_cs43130.dapm_routes =
digital_hp_routes;
soc_component_dev_cs43130.num_dapm_routes =
ARRAY_SIZE(digital_hp_routes);
break;
}
ret = devm_snd_soc_register_component(&client->dev,
&soc_component_dev_cs43130,
cs43130_dai, ARRAY_SIZE(cs43130_dai));
if (ret < 0) {
dev_err(&client->dev,
"snd_soc_register_component failed with ret = %d\n", ret);
goto err;
}
regmap_update_bits(cs43130->regmap, CS43130_PAD_INT_CFG,
CS43130_ASP_3ST_MASK, 0);
regmap_update_bits(cs43130->regmap, CS43130_PAD_INT_CFG,
CS43130_XSP_3ST_MASK, 0);
return 0;
err:
gpiod_set_value_cansleep(cs43130->reset_gpio, 0);
err_supplies:
regulator_bulk_disable(ARRAY_SIZE(cs43130->supplies),
cs43130->supplies);
return ret;
}
static void cs43130_i2c_remove(struct i2c_client *client)
{
struct cs43130_private *cs43130 = i2c_get_clientdata(client);
if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED)
regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
CS43130_XTAL_ERR_INT,
1 << CS43130_XTAL_ERR_INT_SHIFT);
regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
CS43130_HP_PLUG_INT | CS43130_HP_UNPLUG_INT,
CS43130_HP_PLUG_INT | CS43130_HP_UNPLUG_INT);
if (cs43130->dc_meas) {
cancel_work_sync(&cs43130->work);
flush_workqueue(cs43130->wq);
device_remove_file(&client->dev, &dev_attr_hpload_dc_l);
device_remove_file(&client->dev, &dev_attr_hpload_dc_r);
device_remove_file(&client->dev, &dev_attr_hpload_ac_l);
device_remove_file(&client->dev, &dev_attr_hpload_ac_r);
}
gpiod_set_value_cansleep(cs43130->reset_gpio, 0);
pm_runtime_disable(&client->dev);
regulator_bulk_disable(CS43130_NUM_SUPPLIES, cs43130->supplies);
}
static int __maybe_unused cs43130_runtime_suspend(struct device *dev)
{
struct cs43130_private *cs43130 = dev_get_drvdata(dev);
if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED)
regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
CS43130_XTAL_ERR_INT,
1 << CS43130_XTAL_ERR_INT_SHIFT);
regcache_cache_only(cs43130->regmap, true);
regcache_mark_dirty(cs43130->regmap);
gpiod_set_value_cansleep(cs43130->reset_gpio, 0);
regulator_bulk_disable(CS43130_NUM_SUPPLIES, cs43130->supplies);
return 0;
}
static int __maybe_unused cs43130_runtime_resume(struct device *dev)
{
struct cs43130_private *cs43130 = dev_get_drvdata(dev);
int ret;
ret = regulator_bulk_enable(CS43130_NUM_SUPPLIES, cs43130->supplies);
if (ret != 0) {
dev_err(dev, "Failed to enable supplies: %d\n", ret);
return ret;
}
regcache_cache_only(cs43130->regmap, false);
gpiod_set_value_cansleep(cs43130->reset_gpio, 1);
usleep_range(2000, 2050);
ret = regcache_sync(cs43130->regmap);
if (ret != 0) {
dev_err(dev, "Failed to restore register cache\n");
goto err;
}
if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED)
regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
CS43130_XTAL_ERR_INT, 0);
return 0;
err:
regcache_cache_only(cs43130->regmap, true);
regulator_bulk_disable(CS43130_NUM_SUPPLIES, cs43130->supplies);
return ret;
}
static const struct dev_pm_ops cs43130_runtime_pm = {
SET_RUNTIME_PM_OPS(cs43130_runtime_suspend, cs43130_runtime_resume,
NULL)
};
static const struct of_device_id cs43130_of_match[] = {
{.compatible = "cirrus,cs43130",},
{.compatible = "cirrus,cs4399",},
{.compatible = "cirrus,cs43131",},
{.compatible = "cirrus,cs43198",},
{},
};
MODULE_DEVICE_TABLE(of, cs43130_of_match);
static const struct i2c_device_id cs43130_i2c_id[] = {
{"cs43130", 0},
{"cs4399", 0},
{"cs43131", 0},
{"cs43198", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, cs43130_i2c_id);
static struct i2c_driver cs43130_i2c_driver = {
.driver = {
.name = "cs43130",
.of_match_table = cs43130_of_match,
.pm = &cs43130_runtime_pm,
},
.id_table = cs43130_i2c_id,
.probe = cs43130_i2c_probe,
.remove = cs43130_i2c_remove,
};
module_i2c_driver(cs43130_i2c_driver);
MODULE_AUTHOR("Li Xu <[email protected]>");
MODULE_DESCRIPTION("Cirrus Logic CS43130 ALSA SoC Codec Driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cs43130.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2016, The Linux Foundation. All rights reserved.
#include <linux/module.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/regulator/consumer.h>
#include <linux/types.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/tlv.h>
#include <sound/jack.h>
#define CDC_D_REVISION1 (0xf000)
#define CDC_D_PERPH_SUBTYPE (0xf005)
#define CDC_D_INT_EN_SET (0xf015)
#define CDC_D_INT_EN_CLR (0xf016)
#define MBHC_SWITCH_INT BIT(7)
#define MBHC_MIC_ELECTRICAL_INS_REM_DET BIT(6)
#define MBHC_BUTTON_PRESS_DET BIT(5)
#define MBHC_BUTTON_RELEASE_DET BIT(4)
#define CDC_D_CDC_RST_CTL (0xf046)
#define RST_CTL_DIG_SW_RST_N_MASK BIT(7)
#define RST_CTL_DIG_SW_RST_N_RESET 0
#define RST_CTL_DIG_SW_RST_N_REMOVE_RESET BIT(7)
#define CDC_D_CDC_TOP_CLK_CTL (0xf048)
#define TOP_CLK_CTL_A_MCLK_MCLK2_EN_MASK (BIT(2) | BIT(3))
#define TOP_CLK_CTL_A_MCLK_EN_ENABLE BIT(2)
#define TOP_CLK_CTL_A_MCLK2_EN_ENABLE BIT(3)
#define CDC_D_CDC_ANA_CLK_CTL (0xf049)
#define ANA_CLK_CTL_EAR_HPHR_CLK_EN_MASK BIT(0)
#define ANA_CLK_CTL_EAR_HPHR_CLK_EN BIT(0)
#define ANA_CLK_CTL_EAR_HPHL_CLK_EN BIT(1)
#define ANA_CLK_CTL_SPKR_CLK_EN_MASK BIT(4)
#define ANA_CLK_CTL_SPKR_CLK_EN BIT(4)
#define ANA_CLK_CTL_TXA_CLK25_EN BIT(5)
#define CDC_D_CDC_DIG_CLK_CTL (0xf04A)
#define DIG_CLK_CTL_RXD1_CLK_EN BIT(0)
#define DIG_CLK_CTL_RXD2_CLK_EN BIT(1)
#define DIG_CLK_CTL_RXD3_CLK_EN BIT(2)
#define DIG_CLK_CTL_D_MBHC_CLK_EN_MASK BIT(3)
#define DIG_CLK_CTL_D_MBHC_CLK_EN BIT(3)
#define DIG_CLK_CTL_TXD_CLK_EN BIT(4)
#define DIG_CLK_CTL_NCP_CLK_EN_MASK BIT(6)
#define DIG_CLK_CTL_NCP_CLK_EN BIT(6)
#define DIG_CLK_CTL_RXD_PDM_CLK_EN_MASK BIT(7)
#define DIG_CLK_CTL_RXD_PDM_CLK_EN BIT(7)
#define CDC_D_CDC_CONN_TX1_CTL (0xf050)
#define CONN_TX1_SERIAL_TX1_MUX GENMASK(1, 0)
#define CONN_TX1_SERIAL_TX1_ADC_1 0x0
#define CONN_TX1_SERIAL_TX1_RX_PDM_LB 0x1
#define CONN_TX1_SERIAL_TX1_ZERO 0x2
#define CDC_D_CDC_CONN_TX2_CTL (0xf051)
#define CONN_TX2_SERIAL_TX2_MUX GENMASK(1, 0)
#define CONN_TX2_SERIAL_TX2_ADC_2 0x0
#define CONN_TX2_SERIAL_TX2_RX_PDM_LB 0x1
#define CONN_TX2_SERIAL_TX2_ZERO 0x2
#define CDC_D_CDC_CONN_HPHR_DAC_CTL (0xf052)
#define CDC_D_CDC_CONN_RX1_CTL (0xf053)
#define CDC_D_CDC_CONN_RX2_CTL (0xf054)
#define CDC_D_CDC_CONN_RX3_CTL (0xf055)
#define CDC_D_CDC_CONN_RX_LB_CTL (0xf056)
#define CDC_D_SEC_ACCESS (0xf0D0)
#define CDC_D_PERPH_RESET_CTL3 (0xf0DA)
#define CDC_D_PERPH_RESET_CTL4 (0xf0DB)
#define CDC_A_REVISION1 (0xf100)
#define CDC_A_REVISION2 (0xf101)
#define CDC_A_REVISION3 (0xf102)
#define CDC_A_REVISION4 (0xf103)
#define CDC_A_PERPH_TYPE (0xf104)
#define CDC_A_PERPH_SUBTYPE (0xf105)
#define CDC_A_INT_RT_STS (0xf110)
#define CDC_A_INT_SET_TYPE (0xf111)
#define CDC_A_INT_POLARITY_HIGH (0xf112)
#define CDC_A_INT_POLARITY_LOW (0xf113)
#define CDC_A_INT_LATCHED_CLR (0xf114)
#define CDC_A_INT_EN_SET (0xf115)
#define CDC_A_INT_EN_CLR (0xf116)
#define CDC_A_INT_LATCHED_STS (0xf118)
#define CDC_A_INT_PENDING_STS (0xf119)
#define CDC_A_INT_MID_SEL (0xf11A)
#define CDC_A_INT_PRIORITY (0xf11B)
#define CDC_A_MICB_1_EN (0xf140)
#define MICB_1_EN_MICB_ENABLE BIT(7)
#define MICB_1_EN_BYP_CAP_MASK BIT(6)
#define MICB_1_EN_NO_EXT_BYP_CAP BIT(6)
#define MICB_1_EN_EXT_BYP_CAP 0
#define MICB_1_EN_PULL_DOWN_EN_MASK BIT(5)
#define MICB_1_EN_PULL_DOWN_EN_ENABLE BIT(5)
#define MICB_1_EN_OPA_STG2_TAIL_CURR_MASK GENMASK(3, 1)
#define MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA (0x4)
#define MICB_1_EN_PULL_UP_EN_MASK BIT(4)
#define MICB_1_EN_TX3_GND_SEL_MASK BIT(0)
#define MICB_1_EN_TX3_GND_SEL_TX_GND 0
#define CDC_A_MICB_1_VAL (0xf141)
#define MICB_MIN_VAL 1600
#define MICB_STEP_SIZE 50
#define MICB_VOLTAGE_REGVAL(v) (((v - MICB_MIN_VAL)/MICB_STEP_SIZE) << 3)
#define MICB_1_VAL_MICB_OUT_VAL_MASK GENMASK(7, 3)
#define MICB_1_VAL_MICB_OUT_VAL_V2P70V ((0x16) << 3)
#define MICB_1_VAL_MICB_OUT_VAL_V1P80V ((0x4) << 3)
#define CDC_A_MICB_1_CTL (0xf142)
#define MICB_1_CTL_CFILT_REF_SEL_MASK BIT(1)
#define MICB_1_CTL_CFILT_REF_SEL_HPF_REF BIT(1)
#define MICB_1_CTL_EXT_PRECHARG_EN_MASK BIT(5)
#define MICB_1_CTL_EXT_PRECHARG_EN_ENABLE BIT(5)
#define MICB_1_CTL_INT_PRECHARG_BYP_MASK BIT(6)
#define MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL BIT(6)
#define CDC_A_MICB_1_INT_RBIAS (0xf143)
#define MICB_1_INT_TX1_INT_RBIAS_EN_MASK BIT(7)
#define MICB_1_INT_TX1_INT_RBIAS_EN_ENABLE BIT(7)
#define MICB_1_INT_TX1_INT_RBIAS_EN_DISABLE 0
#define MICB_1_INT_TX1_INT_PULLUP_EN_MASK BIT(6)
#define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(6)
#define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_GND 0
#define MICB_1_INT_TX2_INT_RBIAS_EN_MASK BIT(4)
#define MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE BIT(4)
#define MICB_1_INT_TX2_INT_RBIAS_EN_DISABLE 0
#define MICB_1_INT_TX2_INT_PULLUP_EN_MASK BIT(3)
#define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(3)
#define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_GND 0
#define MICB_1_INT_TX3_INT_RBIAS_EN_MASK BIT(1)
#define MICB_1_INT_TX3_INT_RBIAS_EN_ENABLE BIT(1)
#define MICB_1_INT_TX3_INT_RBIAS_EN_DISABLE 0
#define MICB_1_INT_TX3_INT_PULLUP_EN_MASK BIT(0)
#define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(0)
#define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_GND 0
#define CDC_A_MICB_2_EN (0xf144)
#define CDC_A_MICB_2_EN_ENABLE BIT(7)
#define CDC_A_MICB_2_PULL_DOWN_EN_MASK BIT(5)
#define CDC_A_MICB_2_PULL_DOWN_EN BIT(5)
#define CDC_A_TX_1_2_ATEST_CTL_2 (0xf145)
#define CDC_A_MASTER_BIAS_CTL (0xf146)
#define CDC_A_MBHC_DET_CTL_1 (0xf147)
#define CDC_A_MBHC_DET_CTL_L_DET_EN BIT(7)
#define CDC_A_MBHC_DET_CTL_GND_DET_EN BIT(6)
#define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_INSERTION BIT(5)
#define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_REMOVAL (0)
#define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK BIT(5)
#define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_SHIFT (5)
#define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_AUTO BIT(4)
#define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MANUAL BIT(3)
#define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MASK GENMASK(4, 3)
#define CDC_A_MBHC_DET_CTL_MBHC_BIAS_EN BIT(2)
#define CDC_A_MBHC_DET_CTL_2 (0xf150)
#define CDC_A_MBHC_DET_CTL_HS_L_DET_PULL_UP_CTRL_I_3P0 (BIT(7) | BIT(6))
#define CDC_A_MBHC_DET_CTL_HS_L_DET_COMPA_CTRL_V0P9_VDD BIT(5)
#define CDC_A_PLUG_TYPE_MASK GENMASK(4, 3)
#define CDC_A_HPHL_PLUG_TYPE_NO BIT(4)
#define CDC_A_GND_PLUG_TYPE_NO BIT(3)
#define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN_MASK BIT(0)
#define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN BIT(0)
#define CDC_A_MBHC_FSM_CTL (0xf151)
#define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN BIT(7)
#define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN_MASK BIT(7)
#define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_I_100UA (0x3 << 4)
#define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_MASK GENMASK(6, 4)
#define CDC_A_MBHC_DBNC_TIMER (0xf152)
#define CDC_A_MBHC_DBNC_TIMER_BTN_DBNC_T_16MS BIT(3)
#define CDC_A_MBHC_DBNC_TIMER_INSREM_DBNC_T_256_MS (0x9 << 4)
#define CDC_A_MBHC_BTN0_ZDET_CTL_0 (0xf153)
#define CDC_A_MBHC_BTN1_ZDET_CTL_1 (0xf154)
#define CDC_A_MBHC_BTN2_ZDET_CTL_2 (0xf155)
#define CDC_A_MBHC_BTN3_CTL (0xf156)
#define CDC_A_MBHC_BTN4_CTL (0xf157)
#define CDC_A_MBHC_BTN_VREF_FINE_SHIFT (2)
#define CDC_A_MBHC_BTN_VREF_FINE_MASK GENMASK(4, 2)
#define CDC_A_MBHC_BTN_VREF_COARSE_MASK GENMASK(7, 5)
#define CDC_A_MBHC_BTN_VREF_COARSE_SHIFT (5)
#define CDC_A_MBHC_BTN_VREF_MASK (CDC_A_MBHC_BTN_VREF_COARSE_MASK | \
CDC_A_MBHC_BTN_VREF_FINE_MASK)
#define CDC_A_MBHC_RESULT_1 (0xf158)
#define CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK GENMASK(4, 0)
#define CDC_A_TX_1_EN (0xf160)
#define CDC_A_TX_2_EN (0xf161)
#define CDC_A_TX_1_2_TEST_CTL_1 (0xf162)
#define CDC_A_TX_1_2_TEST_CTL_2 (0xf163)
#define CDC_A_TX_1_2_ATEST_CTL (0xf164)
#define CDC_A_TX_1_2_OPAMP_BIAS (0xf165)
#define CDC_A_TX_3_EN (0xf167)
#define CDC_A_NCP_EN (0xf180)
#define CDC_A_NCP_CLK (0xf181)
#define CDC_A_NCP_FBCTRL (0xf183)
#define CDC_A_NCP_FBCTRL_FB_CLK_INV_MASK BIT(5)
#define CDC_A_NCP_FBCTRL_FB_CLK_INV BIT(5)
#define CDC_A_NCP_BIAS (0xf184)
#define CDC_A_NCP_VCTRL (0xf185)
#define CDC_A_NCP_TEST (0xf186)
#define CDC_A_NCP_CLIM_ADDR (0xf187)
#define CDC_A_RX_CLOCK_DIVIDER (0xf190)
#define CDC_A_RX_COM_OCP_CTL (0xf191)
#define CDC_A_RX_COM_OCP_COUNT (0xf192)
#define CDC_A_RX_COM_BIAS_DAC (0xf193)
#define RX_COM_BIAS_DAC_RX_BIAS_EN_MASK BIT(7)
#define RX_COM_BIAS_DAC_RX_BIAS_EN_ENABLE BIT(7)
#define RX_COM_BIAS_DAC_DAC_REF_EN_MASK BIT(0)
#define RX_COM_BIAS_DAC_DAC_REF_EN_ENABLE BIT(0)
#define CDC_A_RX_HPH_BIAS_PA (0xf194)
#define CDC_A_RX_HPH_BIAS_LDO_OCP (0xf195)
#define CDC_A_RX_HPH_BIAS_CNP (0xf196)
#define CDC_A_RX_HPH_CNP_EN (0xf197)
#define CDC_A_RX_HPH_L_PA_DAC_CTL (0xf19B)
#define RX_HPA_L_PA_DAC_CTL_DATA_RESET_MASK BIT(1)
#define RX_HPA_L_PA_DAC_CTL_DATA_RESET_RESET BIT(1)
#define CDC_A_RX_HPH_R_PA_DAC_CTL (0xf19D)
#define RX_HPH_R_PA_DAC_CTL_DATA_RESET BIT(1)
#define RX_HPH_R_PA_DAC_CTL_DATA_RESET_MASK BIT(1)
#define CDC_A_RX_EAR_CTL (0xf19E)
#define RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK BIT(0)
#define RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE BIT(0)
#define RX_EAR_CTL_PA_EAR_PA_EN_MASK BIT(6)
#define RX_EAR_CTL_PA_EAR_PA_EN_ENABLE BIT(6)
#define RX_EAR_CTL_PA_SEL_MASK BIT(7)
#define RX_EAR_CTL_PA_SEL BIT(7)
#define CDC_A_SPKR_DAC_CTL (0xf1B0)
#define SPKR_DAC_CTL_DAC_RESET_MASK BIT(4)
#define SPKR_DAC_CTL_DAC_RESET_NORMAL 0
#define CDC_A_SPKR_DRV_CTL (0xf1B2)
#define SPKR_DRV_CTL_DEF_MASK 0xEF
#define SPKR_DRV_CLASSD_PA_EN_MASK BIT(7)
#define SPKR_DRV_CLASSD_PA_EN_ENABLE BIT(7)
#define SPKR_DRV_CAL_EN BIT(6)
#define SPKR_DRV_SETTLE_EN BIT(5)
#define SPKR_DRV_FW_EN BIT(3)
#define SPKR_DRV_BOOST_SET BIT(2)
#define SPKR_DRV_CMFB_SET BIT(1)
#define SPKR_DRV_GAIN_SET BIT(0)
#define SPKR_DRV_CTL_DEF_VAL (SPKR_DRV_CLASSD_PA_EN_ENABLE | \
SPKR_DRV_CAL_EN | SPKR_DRV_SETTLE_EN | \
SPKR_DRV_FW_EN | SPKR_DRV_BOOST_SET | \
SPKR_DRV_CMFB_SET | SPKR_DRV_GAIN_SET)
#define CDC_A_SPKR_OCP_CTL (0xf1B4)
#define CDC_A_SPKR_PWRSTG_CTL (0xf1B5)
#define SPKR_PWRSTG_CTL_DAC_EN_MASK BIT(0)
#define SPKR_PWRSTG_CTL_DAC_EN BIT(0)
#define SPKR_PWRSTG_CTL_MASK 0xE0
#define SPKR_PWRSTG_CTL_BBM_MASK BIT(7)
#define SPKR_PWRSTG_CTL_BBM_EN BIT(7)
#define SPKR_PWRSTG_CTL_HBRDGE_EN_MASK BIT(6)
#define SPKR_PWRSTG_CTL_HBRDGE_EN BIT(6)
#define SPKR_PWRSTG_CTL_CLAMP_EN_MASK BIT(5)
#define SPKR_PWRSTG_CTL_CLAMP_EN BIT(5)
#define CDC_A_SPKR_DRV_DBG (0xf1B7)
#define CDC_A_CURRENT_LIMIT (0xf1C0)
#define CDC_A_BOOST_EN_CTL (0xf1C3)
#define CDC_A_SLOPE_COMP_IP_ZERO (0xf1C4)
#define CDC_A_SEC_ACCESS (0xf1D0)
#define CDC_A_PERPH_RESET_CTL3 (0xf1DA)
#define CDC_A_PERPH_RESET_CTL4 (0xf1DB)
#define MSM8916_WCD_ANALOG_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)
#define MSM8916_WCD_ANALOG_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static int btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3 | SND_JACK_BTN_4;
static int hs_jack_mask = SND_JACK_HEADPHONE | SND_JACK_HEADSET;
static const char * const supply_names[] = {
"vdd-cdc-io",
"vdd-cdc-tx-rx-cx",
};
#define MBHC_MAX_BUTTONS (5)
struct pm8916_wcd_analog_priv {
u16 pmic_rev;
u16 codec_version;
bool mbhc_btn_enabled;
/* special event to detect accessory type */
int mbhc_btn0_released;
bool detect_accessory_type;
struct clk *mclk;
struct snd_soc_component *component;
struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
struct snd_soc_jack *jack;
bool hphl_jack_type_normally_open;
bool gnd_jack_type_normally_open;
/* Voltage threshold when internal current source of 100uA is used */
u32 vref_btn_cs[MBHC_MAX_BUTTONS];
/* Voltage threshold when microphone bias is ON */
u32 vref_btn_micb[MBHC_MAX_BUTTONS];
unsigned int micbias1_cap_mode;
unsigned int micbias2_cap_mode;
unsigned int micbias_mv;
};
static const char *const adc2_mux_text[] = { "ZERO", "INP2", "INP3" };
static const char *const rdac2_mux_text[] = { "RX1", "RX2" };
static const char *const hph_text[] = { "ZERO", "Switch", };
static const struct soc_enum hph_enum = SOC_ENUM_SINGLE_VIRT(
ARRAY_SIZE(hph_text), hph_text);
static const struct snd_kcontrol_new ear_mux = SOC_DAPM_ENUM("EAR_S", hph_enum);
static const struct snd_kcontrol_new hphl_mux = SOC_DAPM_ENUM("HPHL", hph_enum);
static const struct snd_kcontrol_new hphr_mux = SOC_DAPM_ENUM("HPHR", hph_enum);
/* ADC2 MUX */
static const struct soc_enum adc2_enum = SOC_ENUM_SINGLE_VIRT(
ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
/* RDAC2 MUX */
static const struct soc_enum rdac2_mux_enum = SOC_ENUM_SINGLE(
CDC_D_CDC_CONN_HPHR_DAC_CTL, 0, 2, rdac2_mux_text);
static const struct snd_kcontrol_new spkr_switch[] = {
SOC_DAPM_SINGLE("Switch", CDC_A_SPKR_DAC_CTL, 7, 1, 0)
};
static const struct snd_kcontrol_new rdac2_mux = SOC_DAPM_ENUM(
"RDAC2 MUX Mux", rdac2_mux_enum);
static const struct snd_kcontrol_new tx_adc2_mux = SOC_DAPM_ENUM(
"ADC2 MUX Mux", adc2_enum);
/* Analog Gain control 0 dB to +24 dB in 6 dB steps */
static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 600, 0);
static const struct snd_kcontrol_new pm8916_wcd_analog_snd_controls[] = {
SOC_SINGLE_TLV("ADC1 Volume", CDC_A_TX_1_EN, 3, 8, 0, analog_gain),
SOC_SINGLE_TLV("ADC2 Volume", CDC_A_TX_2_EN, 3, 8, 0, analog_gain),
SOC_SINGLE_TLV("ADC3 Volume", CDC_A_TX_3_EN, 3, 8, 0, analog_gain),
};
static void pm8916_wcd_analog_micbias_enable(struct snd_soc_component *component)
{
struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL,
MICB_1_CTL_EXT_PRECHARG_EN_MASK |
MICB_1_CTL_INT_PRECHARG_BYP_MASK,
MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL
| MICB_1_CTL_EXT_PRECHARG_EN_ENABLE);
if (wcd->micbias_mv) {
snd_soc_component_update_bits(component, CDC_A_MICB_1_VAL,
MICB_1_VAL_MICB_OUT_VAL_MASK,
MICB_VOLTAGE_REGVAL(wcd->micbias_mv));
/*
* Special headset needs MICBIAS as 2.7V so wait for
* 50 msec for the MICBIAS to reach 2.7 volts.
*/
if (wcd->micbias_mv >= 2700)
msleep(50);
}
snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL,
MICB_1_CTL_EXT_PRECHARG_EN_MASK |
MICB_1_CTL_INT_PRECHARG_BYP_MASK, 0);
}
static int pm8916_wcd_analog_enable_micbias(struct snd_soc_component *component,
int event, unsigned int cap_mode)
{
switch (event) {
case SND_SOC_DAPM_POST_PMU:
pm8916_wcd_analog_micbias_enable(component);
snd_soc_component_update_bits(component, CDC_A_MICB_1_EN,
MICB_1_EN_BYP_CAP_MASK, cap_mode);
break;
}
return 0;
}
static int pm8916_wcd_analog_enable_micbias_int(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_component_update_bits(component, CDC_A_MICB_1_EN,
MICB_1_EN_OPA_STG2_TAIL_CURR_MASK,
MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA);
break;
}
return 0;
}
static int pm8916_wcd_analog_enable_micbias1(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
return pm8916_wcd_analog_enable_micbias(component, event,
wcd->micbias1_cap_mode);
}
static int pm8916_wcd_analog_enable_micbias2(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
return pm8916_wcd_analog_enable_micbias(component, event,
wcd->micbias2_cap_mode);
}
static int pm8916_mbhc_configure_bias(struct pm8916_wcd_analog_priv *priv,
bool micbias2_enabled)
{
struct snd_soc_component *component = priv->component;
u32 coarse, fine, reg_val, reg_addr;
int *vrefs, i;
if (!micbias2_enabled) { /* use internal 100uA Current source */
/* Enable internal 2.2k Internal Rbias Resistor */
snd_soc_component_update_bits(component, CDC_A_MICB_1_INT_RBIAS,
MICB_1_INT_TX2_INT_RBIAS_EN_MASK,
MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE);
/* Remove pull down on MIC BIAS2 */
snd_soc_component_update_bits(component, CDC_A_MICB_2_EN,
CDC_A_MICB_2_PULL_DOWN_EN_MASK,
0);
/* enable 100uA internal current source */
snd_soc_component_update_bits(component, CDC_A_MBHC_FSM_CTL,
CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_MASK,
CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_I_100UA);
}
snd_soc_component_update_bits(component, CDC_A_MBHC_FSM_CTL,
CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN_MASK,
CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN);
if (micbias2_enabled)
vrefs = &priv->vref_btn_micb[0];
else
vrefs = &priv->vref_btn_cs[0];
/* program vref ranges for all the buttons */
reg_addr = CDC_A_MBHC_BTN0_ZDET_CTL_0;
for (i = 0; i < MBHC_MAX_BUTTONS; i++) {
/* split mv in to coarse parts of 100mv & fine parts of 12mv */
coarse = (vrefs[i] / 100);
fine = ((vrefs[i] % 100) / 12);
reg_val = (coarse << CDC_A_MBHC_BTN_VREF_COARSE_SHIFT) |
(fine << CDC_A_MBHC_BTN_VREF_FINE_SHIFT);
snd_soc_component_update_bits(component, reg_addr,
CDC_A_MBHC_BTN_VREF_MASK,
reg_val);
reg_addr++;
}
return 0;
}
static void pm8916_wcd_setup_mbhc(struct pm8916_wcd_analog_priv *wcd)
{
struct snd_soc_component *component = wcd->component;
bool micbias_enabled = false;
u32 plug_type = 0;
u32 int_en_mask;
snd_soc_component_write(component, CDC_A_MBHC_DET_CTL_1,
CDC_A_MBHC_DET_CTL_L_DET_EN |
CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_INSERTION |
CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_AUTO |
CDC_A_MBHC_DET_CTL_MBHC_BIAS_EN);
if (wcd->hphl_jack_type_normally_open)
plug_type |= CDC_A_HPHL_PLUG_TYPE_NO;
if (wcd->gnd_jack_type_normally_open)
plug_type |= CDC_A_GND_PLUG_TYPE_NO;
snd_soc_component_write(component, CDC_A_MBHC_DET_CTL_2,
CDC_A_MBHC_DET_CTL_HS_L_DET_PULL_UP_CTRL_I_3P0 |
CDC_A_MBHC_DET_CTL_HS_L_DET_COMPA_CTRL_V0P9_VDD |
plug_type |
CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN);
snd_soc_component_write(component, CDC_A_MBHC_DBNC_TIMER,
CDC_A_MBHC_DBNC_TIMER_INSREM_DBNC_T_256_MS |
CDC_A_MBHC_DBNC_TIMER_BTN_DBNC_T_16MS);
/* enable MBHC clock */
snd_soc_component_update_bits(component, CDC_D_CDC_DIG_CLK_CTL,
DIG_CLK_CTL_D_MBHC_CLK_EN_MASK,
DIG_CLK_CTL_D_MBHC_CLK_EN);
if (snd_soc_component_read(component, CDC_A_MICB_2_EN) & CDC_A_MICB_2_EN_ENABLE)
micbias_enabled = true;
pm8916_mbhc_configure_bias(wcd, micbias_enabled);
int_en_mask = MBHC_SWITCH_INT;
if (wcd->mbhc_btn_enabled)
int_en_mask |= MBHC_BUTTON_PRESS_DET | MBHC_BUTTON_RELEASE_DET;
snd_soc_component_update_bits(component, CDC_D_INT_EN_CLR, int_en_mask, 0);
snd_soc_component_update_bits(component, CDC_D_INT_EN_SET, int_en_mask, int_en_mask);
wcd->mbhc_btn0_released = false;
wcd->detect_accessory_type = true;
}
static int pm8916_wcd_analog_enable_micbias_int2(struct
snd_soc_dapm_widget
*w, struct snd_kcontrol
*kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_component_update_bits(component, CDC_A_MICB_2_EN,
CDC_A_MICB_2_PULL_DOWN_EN_MASK, 0);
break;
case SND_SOC_DAPM_POST_PMU:
pm8916_mbhc_configure_bias(wcd, true);
break;
case SND_SOC_DAPM_POST_PMD:
pm8916_mbhc_configure_bias(wcd, false);
break;
}
return pm8916_wcd_analog_enable_micbias_int(w, kcontrol, event);
}
static int pm8916_wcd_analog_enable_adc(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
u16 adc_reg = CDC_A_TX_1_2_TEST_CTL_2;
u8 init_bit_shift;
if (w->reg == CDC_A_TX_1_EN)
init_bit_shift = 5;
else
init_bit_shift = 4;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
if (w->reg == CDC_A_TX_2_EN)
snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL,
MICB_1_CTL_CFILT_REF_SEL_MASK,
MICB_1_CTL_CFILT_REF_SEL_HPF_REF);
/*
* Add delay of 10 ms to give sufficient time for the voltage
* to shoot up and settle so that the txfe init does not
* happen when the input voltage is changing too much.
*/
usleep_range(10000, 10010);
snd_soc_component_update_bits(component, adc_reg, 1 << init_bit_shift,
1 << init_bit_shift);
switch (w->reg) {
case CDC_A_TX_1_EN:
snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX1_CTL,
CONN_TX1_SERIAL_TX1_MUX,
CONN_TX1_SERIAL_TX1_ADC_1);
break;
case CDC_A_TX_2_EN:
case CDC_A_TX_3_EN:
snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX2_CTL,
CONN_TX2_SERIAL_TX2_MUX,
CONN_TX2_SERIAL_TX2_ADC_2);
break;
}
break;
case SND_SOC_DAPM_POST_PMU:
/*
* Add delay of 12 ms before deasserting the init
* to reduce the tx pop
*/
usleep_range(12000, 12010);
snd_soc_component_update_bits(component, adc_reg, 1 << init_bit_shift, 0x00);
break;
case SND_SOC_DAPM_POST_PMD:
switch (w->reg) {
case CDC_A_TX_1_EN:
snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX1_CTL,
CONN_TX1_SERIAL_TX1_MUX,
CONN_TX1_SERIAL_TX1_ZERO);
break;
case CDC_A_TX_2_EN:
snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL,
MICB_1_CTL_CFILT_REF_SEL_MASK, 0);
fallthrough;
case CDC_A_TX_3_EN:
snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX2_CTL,
CONN_TX2_SERIAL_TX2_MUX,
CONN_TX2_SERIAL_TX2_ZERO);
break;
}
break;
}
return 0;
}
static int pm8916_wcd_analog_enable_spk_pa(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_component_update_bits(component, CDC_A_SPKR_PWRSTG_CTL,
SPKR_PWRSTG_CTL_DAC_EN_MASK |
SPKR_PWRSTG_CTL_BBM_MASK |
SPKR_PWRSTG_CTL_HBRDGE_EN_MASK |
SPKR_PWRSTG_CTL_CLAMP_EN_MASK,
SPKR_PWRSTG_CTL_DAC_EN|
SPKR_PWRSTG_CTL_BBM_EN |
SPKR_PWRSTG_CTL_HBRDGE_EN |
SPKR_PWRSTG_CTL_CLAMP_EN);
snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK,
RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE);
break;
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(component, CDC_A_SPKR_DRV_CTL,
SPKR_DRV_CTL_DEF_MASK,
SPKR_DRV_CTL_DEF_VAL);
snd_soc_component_update_bits(component, w->reg,
SPKR_DRV_CLASSD_PA_EN_MASK,
SPKR_DRV_CLASSD_PA_EN_ENABLE);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component, CDC_A_SPKR_PWRSTG_CTL,
SPKR_PWRSTG_CTL_DAC_EN_MASK|
SPKR_PWRSTG_CTL_BBM_MASK |
SPKR_PWRSTG_CTL_HBRDGE_EN_MASK |
SPKR_PWRSTG_CTL_CLAMP_EN_MASK, 0);
snd_soc_component_update_bits(component, CDC_A_SPKR_DAC_CTL,
SPKR_DAC_CTL_DAC_RESET_MASK,
SPKR_DAC_CTL_DAC_RESET_NORMAL);
snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK, 0);
break;
}
return 0;
}
static int pm8916_wcd_analog_enable_ear_pa(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
RX_EAR_CTL_PA_SEL_MASK, RX_EAR_CTL_PA_SEL);
break;
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
RX_EAR_CTL_PA_EAR_PA_EN_MASK,
RX_EAR_CTL_PA_EAR_PA_EN_ENABLE);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
RX_EAR_CTL_PA_EAR_PA_EN_MASK, 0);
/* Delay to reduce ear turn off pop */
usleep_range(7000, 7100);
snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
RX_EAR_CTL_PA_SEL_MASK, 0);
break;
}
return 0;
}
static const struct reg_default wcd_reg_defaults_2_0[] = {
{CDC_A_RX_COM_OCP_CTL, 0xD1},
{CDC_A_RX_COM_OCP_COUNT, 0xFF},
{CDC_D_SEC_ACCESS, 0xA5},
{CDC_D_PERPH_RESET_CTL3, 0x0F},
{CDC_A_TX_1_2_OPAMP_BIAS, 0x4F},
{CDC_A_NCP_FBCTRL, 0x28},
{CDC_A_SPKR_DRV_CTL, 0x69},
{CDC_A_SPKR_DRV_DBG, 0x01},
{CDC_A_BOOST_EN_CTL, 0x5F},
{CDC_A_SLOPE_COMP_IP_ZERO, 0x88},
{CDC_A_SEC_ACCESS, 0xA5},
{CDC_A_PERPH_RESET_CTL3, 0x0F},
{CDC_A_CURRENT_LIMIT, 0x82},
{CDC_A_SPKR_DAC_CTL, 0x03},
{CDC_A_SPKR_OCP_CTL, 0xE1},
{CDC_A_MASTER_BIAS_CTL, 0x30},
};
static int pm8916_wcd_analog_probe(struct snd_soc_component *component)
{
struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(component->dev);
int err, reg;
err = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
if (err != 0) {
dev_err(component->dev, "failed to enable regulators (%d)\n", err);
return err;
}
snd_soc_component_init_regmap(component,
dev_get_regmap(component->dev->parent, NULL));
snd_soc_component_set_drvdata(component, priv);
priv->pmic_rev = snd_soc_component_read(component, CDC_D_REVISION1);
priv->codec_version = snd_soc_component_read(component, CDC_D_PERPH_SUBTYPE);
dev_info(component->dev, "PMIC REV: %d\t CODEC Version: %d\n",
priv->pmic_rev, priv->codec_version);
snd_soc_component_write(component, CDC_D_PERPH_RESET_CTL4, 0x01);
snd_soc_component_write(component, CDC_A_PERPH_RESET_CTL4, 0x01);
for (reg = 0; reg < ARRAY_SIZE(wcd_reg_defaults_2_0); reg++)
snd_soc_component_write(component, wcd_reg_defaults_2_0[reg].reg,
wcd_reg_defaults_2_0[reg].def);
priv->component = component;
snd_soc_component_update_bits(component, CDC_D_CDC_RST_CTL,
RST_CTL_DIG_SW_RST_N_MASK,
RST_CTL_DIG_SW_RST_N_REMOVE_RESET);
pm8916_wcd_setup_mbhc(priv);
return 0;
}
static void pm8916_wcd_analog_remove(struct snd_soc_component *component)
{
struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(component->dev);
snd_soc_component_update_bits(component, CDC_D_CDC_RST_CTL,
RST_CTL_DIG_SW_RST_N_MASK, 0);
regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
priv->supplies);
}
static const struct snd_soc_dapm_route pm8916_wcd_analog_audio_map[] = {
{"PDM_RX1", NULL, "PDM Playback"},
{"PDM_RX2", NULL, "PDM Playback"},
{"PDM_RX3", NULL, "PDM Playback"},
{"PDM Capture", NULL, "PDM_TX"},
/* ADC Connections */
{"PDM_TX", NULL, "ADC2"},
{"PDM_TX", NULL, "ADC3"},
{"ADC2", NULL, "ADC2 MUX"},
{"ADC3", NULL, "ADC2 MUX"},
{"ADC2 MUX", "INP2", "ADC2_INP2"},
{"ADC2 MUX", "INP3", "ADC2_INP3"},
{"PDM_TX", NULL, "ADC1"},
{"ADC1", NULL, "AMIC1"},
{"ADC2_INP2", NULL, "AMIC2"},
{"ADC2_INP3", NULL, "AMIC3"},
/* RDAC Connections */
{"HPHR DAC", NULL, "RDAC2 MUX"},
{"RDAC2 MUX", "RX1", "PDM_RX1"},
{"RDAC2 MUX", "RX2", "PDM_RX2"},
{"HPHL DAC", NULL, "PDM_RX1"},
{"PDM_RX1", NULL, "RXD1_CLK"},
{"PDM_RX2", NULL, "RXD2_CLK"},
{"PDM_RX3", NULL, "RXD3_CLK"},
{"PDM_RX1", NULL, "RXD_PDM_CLK"},
{"PDM_RX2", NULL, "RXD_PDM_CLK"},
{"PDM_RX3", NULL, "RXD_PDM_CLK"},
{"ADC1", NULL, "TXD_CLK"},
{"ADC2", NULL, "TXD_CLK"},
{"ADC3", NULL, "TXD_CLK"},
{"ADC1", NULL, "TXA_CLK25"},
{"ADC2", NULL, "TXA_CLK25"},
{"ADC3", NULL, "TXA_CLK25"},
{"PDM_RX1", NULL, "A_MCLK2"},
{"PDM_RX2", NULL, "A_MCLK2"},
{"PDM_RX3", NULL, "A_MCLK2"},
{"PDM_TX", NULL, "A_MCLK2"},
{"A_MCLK2", NULL, "A_MCLK"},
/* Earpiece (RX MIX1) */
{"EAR", NULL, "EAR_S"},
{"EAR_S", "Switch", "EAR PA"},
{"EAR PA", NULL, "RX_BIAS"},
{"EAR PA", NULL, "HPHL DAC"},
{"EAR PA", NULL, "HPHR DAC"},
{"EAR PA", NULL, "EAR CP"},
/* Headset (RX MIX1 and RX MIX2) */
{"HPH_L", NULL, "HPHL PA"},
{"HPH_R", NULL, "HPHR PA"},
{"HPHL DAC", NULL, "EAR_HPHL_CLK"},
{"HPHR DAC", NULL, "EAR_HPHR_CLK"},
{"CP", NULL, "NCP_CLK"},
{"HPHL PA", NULL, "HPHL"},
{"HPHR PA", NULL, "HPHR"},
{"HPHL PA", NULL, "CP"},
{"HPHL PA", NULL, "RX_BIAS"},
{"HPHR PA", NULL, "CP"},
{"HPHR PA", NULL, "RX_BIAS"},
{"HPHL", "Switch", "HPHL DAC"},
{"HPHR", "Switch", "HPHR DAC"},
{"RX_BIAS", NULL, "DAC_REF"},
{"SPK_OUT", NULL, "SPK PA"},
{"SPK PA", NULL, "RX_BIAS"},
{"SPK PA", NULL, "SPKR_CLK"},
{"SPK PA", NULL, "SPK DAC"},
{"SPK DAC", "Switch", "PDM_RX3"},
{"MIC_BIAS1", NULL, "INT_LDO_H"},
{"MIC_BIAS2", NULL, "INT_LDO_H"},
{"MIC_BIAS1", NULL, "vdd-micbias"},
{"MIC_BIAS2", NULL, "vdd-micbias"},
{"MIC BIAS External1", NULL, "MIC_BIAS1"},
{"MIC BIAS Internal1", NULL, "MIC_BIAS1"},
{"MIC BIAS External2", NULL, "MIC_BIAS2"},
{"MIC BIAS Internal2", NULL, "MIC_BIAS2"},
{"MIC BIAS Internal3", NULL, "MIC_BIAS1"},
};
static const struct snd_soc_dapm_widget pm8916_wcd_analog_dapm_widgets[] = {
SND_SOC_DAPM_AIF_IN("PDM_RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("PDM_RX2", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("PDM_RX3", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("PDM_TX", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_INPUT("AMIC1"),
SND_SOC_DAPM_INPUT("AMIC3"),
SND_SOC_DAPM_INPUT("AMIC2"),
SND_SOC_DAPM_OUTPUT("EAR"),
SND_SOC_DAPM_OUTPUT("HPH_L"),
SND_SOC_DAPM_OUTPUT("HPH_R"),
/* RX stuff */
SND_SOC_DAPM_SUPPLY("INT_LDO_H", SND_SOC_NOPM, 1, 0, NULL, 0),
SND_SOC_DAPM_PGA_E("EAR PA", SND_SOC_NOPM,
0, 0, NULL, 0,
pm8916_wcd_analog_enable_ear_pa,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("EAR_S", SND_SOC_NOPM, 0, 0, &ear_mux),
SND_SOC_DAPM_SUPPLY("EAR CP", CDC_A_NCP_EN, 4, 0, NULL, 0),
SND_SOC_DAPM_PGA("HPHL PA", CDC_A_RX_HPH_CNP_EN, 5, 0, NULL, 0),
SND_SOC_DAPM_MUX("HPHL", SND_SOC_NOPM, 0, 0, &hphl_mux),
SND_SOC_DAPM_MIXER("HPHL DAC", CDC_A_RX_HPH_L_PA_DAC_CTL, 3, 0, NULL,
0),
SND_SOC_DAPM_PGA("HPHR PA", CDC_A_RX_HPH_CNP_EN, 4, 0, NULL, 0),
SND_SOC_DAPM_MUX("HPHR", SND_SOC_NOPM, 0, 0, &hphr_mux),
SND_SOC_DAPM_MIXER("HPHR DAC", CDC_A_RX_HPH_R_PA_DAC_CTL, 3, 0, NULL,
0),
SND_SOC_DAPM_MIXER("SPK DAC", SND_SOC_NOPM, 0, 0,
spkr_switch, ARRAY_SIZE(spkr_switch)),
/* Speaker */
SND_SOC_DAPM_OUTPUT("SPK_OUT"),
SND_SOC_DAPM_PGA_E("SPK PA", CDC_A_SPKR_DRV_CTL,
6, 0, NULL, 0,
pm8916_wcd_analog_enable_spk_pa,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-micbias", 0, 0),
SND_SOC_DAPM_SUPPLY("CP", CDC_A_NCP_EN, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC_REF", CDC_A_RX_COM_BIAS_DAC, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("RX_BIAS", CDC_A_RX_COM_BIAS_DAC, 7, 0, NULL, 0),
/* TX */
SND_SOC_DAPM_SUPPLY("MIC_BIAS1", CDC_A_MICB_1_EN, 7, 0,
pm8916_wcd_analog_enable_micbias1,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY("MIC_BIAS2", CDC_A_MICB_2_EN, 7, 0,
pm8916_wcd_analog_enable_micbias2,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY("MIC BIAS External1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MIC BIAS External2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MIC BIAS Internal1", CDC_A_MICB_1_INT_RBIAS, 7, 0,
pm8916_wcd_analog_enable_micbias_int,
SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_SUPPLY("MIC BIAS Internal2", CDC_A_MICB_1_INT_RBIAS, 4, 0,
pm8916_wcd_analog_enable_micbias_int2,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("MIC BIAS Internal3", CDC_A_MICB_1_INT_RBIAS, 1, 0,
pm8916_wcd_analog_enable_micbias_int,
SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_ADC_E("ADC1", NULL, CDC_A_TX_1_EN, 7, 0,
pm8916_wcd_analog_enable_adc,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_ADC_E("ADC2_INP2", NULL, CDC_A_TX_2_EN, 7, 0,
pm8916_wcd_analog_enable_adc,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_ADC_E("ADC2_INP3", NULL, CDC_A_TX_3_EN, 7, 0,
pm8916_wcd_analog_enable_adc,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER("ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux),
SND_SOC_DAPM_MUX("RDAC2 MUX", SND_SOC_NOPM, 0, 0, &rdac2_mux),
/* Analog path clocks */
SND_SOC_DAPM_SUPPLY("EAR_HPHR_CLK", CDC_D_CDC_ANA_CLK_CTL, 0, 0, NULL,
0),
SND_SOC_DAPM_SUPPLY("EAR_HPHL_CLK", CDC_D_CDC_ANA_CLK_CTL, 1, 0, NULL,
0),
SND_SOC_DAPM_SUPPLY("SPKR_CLK", CDC_D_CDC_ANA_CLK_CTL, 4, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("TXA_CLK25", CDC_D_CDC_ANA_CLK_CTL, 5, 0, NULL, 0),
/* Digital path clocks */
SND_SOC_DAPM_SUPPLY("RXD1_CLK", CDC_D_CDC_DIG_CLK_CTL, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("RXD2_CLK", CDC_D_CDC_DIG_CLK_CTL, 1, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("RXD3_CLK", CDC_D_CDC_DIG_CLK_CTL, 2, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("TXD_CLK", CDC_D_CDC_DIG_CLK_CTL, 4, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("NCP_CLK", CDC_D_CDC_DIG_CLK_CTL, 6, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("RXD_PDM_CLK", CDC_D_CDC_DIG_CLK_CTL, 7, 0, NULL,
0),
/* System Clock source */
SND_SOC_DAPM_SUPPLY("A_MCLK", CDC_D_CDC_TOP_CLK_CTL, 2, 0, NULL, 0),
/* TX ADC and RX DAC Clock source. */
SND_SOC_DAPM_SUPPLY("A_MCLK2", CDC_D_CDC_TOP_CLK_CTL, 3, 0, NULL, 0),
};
static int pm8916_wcd_analog_set_jack(struct snd_soc_component *component,
struct snd_soc_jack *jack,
void *data)
{
struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
wcd->jack = jack;
return 0;
}
static irqreturn_t mbhc_btn_release_irq_handler(int irq, void *arg)
{
struct pm8916_wcd_analog_priv *priv = arg;
if (priv->detect_accessory_type) {
struct snd_soc_component *component = priv->component;
u32 val = snd_soc_component_read(component, CDC_A_MBHC_RESULT_1);
/* check if its BTN0 thats released */
if ((val != -1) && !(val & CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK))
priv->mbhc_btn0_released = true;
} else {
snd_soc_jack_report(priv->jack, 0, btn_mask);
}
return IRQ_HANDLED;
}
static irqreturn_t mbhc_btn_press_irq_handler(int irq, void *arg)
{
struct pm8916_wcd_analog_priv *priv = arg;
struct snd_soc_component *component = priv->component;
u32 btn_result;
btn_result = snd_soc_component_read(component, CDC_A_MBHC_RESULT_1) &
CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK;
switch (btn_result) {
case 0xf:
snd_soc_jack_report(priv->jack, SND_JACK_BTN_4, btn_mask);
break;
case 0x7:
snd_soc_jack_report(priv->jack, SND_JACK_BTN_3, btn_mask);
break;
case 0x3:
snd_soc_jack_report(priv->jack, SND_JACK_BTN_2, btn_mask);
break;
case 0x1:
snd_soc_jack_report(priv->jack, SND_JACK_BTN_1, btn_mask);
break;
case 0x0:
/* handle BTN_0 specially for type detection */
if (!priv->detect_accessory_type)
snd_soc_jack_report(priv->jack,
SND_JACK_BTN_0, btn_mask);
break;
default:
dev_err(component->dev,
"Unexpected button press result (%x)", btn_result);
break;
}
return IRQ_HANDLED;
}
static irqreturn_t pm8916_mbhc_switch_irq_handler(int irq, void *arg)
{
struct pm8916_wcd_analog_priv *priv = arg;
struct snd_soc_component *component = priv->component;
bool ins = false;
if (snd_soc_component_read(component, CDC_A_MBHC_DET_CTL_1) &
CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK)
ins = true;
/* Set the detection type appropriately */
snd_soc_component_update_bits(component, CDC_A_MBHC_DET_CTL_1,
CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK,
(!ins << CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_SHIFT));
if (ins) { /* hs insertion */
bool micbias_enabled = false;
if (snd_soc_component_read(component, CDC_A_MICB_2_EN) &
CDC_A_MICB_2_EN_ENABLE)
micbias_enabled = true;
pm8916_mbhc_configure_bias(priv, micbias_enabled);
/*
* if only a btn0 press event is receive just before
* insert event then its a 3 pole headphone else if
* both press and release event received then its
* a headset.
*/
if (priv->mbhc_btn0_released)
snd_soc_jack_report(priv->jack,
SND_JACK_HEADSET, hs_jack_mask);
else
snd_soc_jack_report(priv->jack,
SND_JACK_HEADPHONE, hs_jack_mask);
priv->detect_accessory_type = false;
} else { /* removal */
snd_soc_jack_report(priv->jack, 0, hs_jack_mask);
priv->detect_accessory_type = true;
priv->mbhc_btn0_released = false;
}
return IRQ_HANDLED;
}
static struct snd_soc_dai_driver pm8916_wcd_analog_dai[] = {
[0] = {
.name = "pm8916_wcd_analog_pdm_rx",
.id = 0,
.playback = {
.stream_name = "PDM Playback",
.rates = MSM8916_WCD_ANALOG_RATES,
.formats = MSM8916_WCD_ANALOG_FORMATS,
.channels_min = 1,
.channels_max = 3,
},
},
[1] = {
.name = "pm8916_wcd_analog_pdm_tx",
.id = 1,
.capture = {
.stream_name = "PDM Capture",
.rates = MSM8916_WCD_ANALOG_RATES,
.formats = MSM8916_WCD_ANALOG_FORMATS,
.channels_min = 1,
.channels_max = 4,
},
},
};
static const struct snd_soc_component_driver pm8916_wcd_analog = {
.probe = pm8916_wcd_analog_probe,
.remove = pm8916_wcd_analog_remove,
.set_jack = pm8916_wcd_analog_set_jack,
.controls = pm8916_wcd_analog_snd_controls,
.num_controls = ARRAY_SIZE(pm8916_wcd_analog_snd_controls),
.dapm_widgets = pm8916_wcd_analog_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(pm8916_wcd_analog_dapm_widgets),
.dapm_routes = pm8916_wcd_analog_audio_map,
.num_dapm_routes = ARRAY_SIZE(pm8916_wcd_analog_audio_map),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int pm8916_wcd_analog_parse_dt(struct device *dev,
struct pm8916_wcd_analog_priv *priv)
{
int rval;
if (of_property_read_bool(dev->of_node, "qcom,micbias1-ext-cap"))
priv->micbias1_cap_mode = MICB_1_EN_EXT_BYP_CAP;
else
priv->micbias1_cap_mode = MICB_1_EN_NO_EXT_BYP_CAP;
if (of_property_read_bool(dev->of_node, "qcom,micbias2-ext-cap"))
priv->micbias2_cap_mode = MICB_1_EN_EXT_BYP_CAP;
else
priv->micbias2_cap_mode = MICB_1_EN_NO_EXT_BYP_CAP;
of_property_read_u32(dev->of_node, "qcom,micbias-lvl",
&priv->micbias_mv);
if (of_property_read_bool(dev->of_node,
"qcom,hphl-jack-type-normally-open"))
priv->hphl_jack_type_normally_open = true;
else
priv->hphl_jack_type_normally_open = false;
if (of_property_read_bool(dev->of_node,
"qcom,gnd-jack-type-normally-open"))
priv->gnd_jack_type_normally_open = true;
else
priv->gnd_jack_type_normally_open = false;
priv->mbhc_btn_enabled = true;
rval = of_property_read_u32_array(dev->of_node,
"qcom,mbhc-vthreshold-low",
&priv->vref_btn_cs[0],
MBHC_MAX_BUTTONS);
if (rval < 0) {
priv->mbhc_btn_enabled = false;
} else {
rval = of_property_read_u32_array(dev->of_node,
"qcom,mbhc-vthreshold-high",
&priv->vref_btn_micb[0],
MBHC_MAX_BUTTONS);
if (rval < 0)
priv->mbhc_btn_enabled = false;
}
if (!priv->mbhc_btn_enabled)
dev_err(dev,
"DT property missing, MBHC btn detection disabled\n");
return 0;
}
static int pm8916_wcd_analog_spmi_probe(struct platform_device *pdev)
{
struct pm8916_wcd_analog_priv *priv;
struct device *dev = &pdev->dev;
int ret, i, irq;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
ret = pm8916_wcd_analog_parse_dt(dev, priv);
if (ret < 0)
return ret;
for (i = 0; i < ARRAY_SIZE(supply_names); i++)
priv->supplies[i].supply = supply_names[i];
ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(priv->supplies),
priv->supplies);
if (ret) {
dev_err(dev, "Failed to get regulator supplies %d\n", ret);
return ret;
}
irq = platform_get_irq_byname(pdev, "mbhc_switch_int");
if (irq < 0)
return irq;
ret = devm_request_threaded_irq(dev, irq, NULL,
pm8916_mbhc_switch_irq_handler,
IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
IRQF_ONESHOT,
"mbhc switch irq", priv);
if (ret) {
dev_err(dev, "cannot request mbhc switch irq\n");
return ret;
}
if (priv->mbhc_btn_enabled) {
irq = platform_get_irq_byname(pdev, "mbhc_but_press_det");
if (irq < 0)
return irq;
ret = devm_request_threaded_irq(dev, irq, NULL,
mbhc_btn_press_irq_handler,
IRQF_TRIGGER_RISING |
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
"mbhc btn press irq", priv);
if (ret) {
dev_err(dev, "cannot request mbhc button press irq\n");
return ret;
}
irq = platform_get_irq_byname(pdev, "mbhc_but_rel_det");
if (irq < 0)
return irq;
ret = devm_request_threaded_irq(dev, irq, NULL,
mbhc_btn_release_irq_handler,
IRQF_TRIGGER_RISING |
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
"mbhc btn release irq", priv);
if (ret) {
dev_err(dev, "cannot request mbhc button release irq\n");
return ret;
}
}
dev_set_drvdata(dev, priv);
return devm_snd_soc_register_component(dev, &pm8916_wcd_analog,
pm8916_wcd_analog_dai,
ARRAY_SIZE(pm8916_wcd_analog_dai));
}
static const struct of_device_id pm8916_wcd_analog_spmi_match_table[] = {
{ .compatible = "qcom,pm8916-wcd-analog-codec", },
{ }
};
MODULE_DEVICE_TABLE(of, pm8916_wcd_analog_spmi_match_table);
static struct platform_driver pm8916_wcd_analog_spmi_driver = {
.driver = {
.name = "qcom,pm8916-wcd-spmi-codec",
.of_match_table = pm8916_wcd_analog_spmi_match_table,
},
.probe = pm8916_wcd_analog_spmi_probe,
};
module_platform_driver(pm8916_wcd_analog_spmi_driver);
MODULE_AUTHOR("Srinivas Kandagatla <[email protected]>");
MODULE_DESCRIPTION("PMIC PM8916 WCD Analog Codec driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/msm8916-wcd-analog.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm2200.c -- WM2200 ALSA SoC Audio driver
*
* Copyright 2012 Wolfson Microelectronics plc
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/firmware.h>
#include <linux/gcd.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <linux/regulator/fixed.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/jack.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/wm2200.h>
#include "wm2200.h"
#include "wm_adsp.h"
#define WM2200_DSP_CONTROL_1 0x00
#define WM2200_DSP_CONTROL_2 0x02
#define WM2200_DSP_CONTROL_3 0x03
#define WM2200_DSP_CONTROL_4 0x04
#define WM2200_DSP_CONTROL_5 0x06
#define WM2200_DSP_CONTROL_6 0x07
#define WM2200_DSP_CONTROL_7 0x08
#define WM2200_DSP_CONTROL_8 0x09
#define WM2200_DSP_CONTROL_9 0x0A
#define WM2200_DSP_CONTROL_10 0x0B
#define WM2200_DSP_CONTROL_11 0x0C
#define WM2200_DSP_CONTROL_12 0x0D
#define WM2200_DSP_CONTROL_13 0x0F
#define WM2200_DSP_CONTROL_14 0x10
#define WM2200_DSP_CONTROL_15 0x11
#define WM2200_DSP_CONTROL_16 0x12
#define WM2200_DSP_CONTROL_17 0x13
#define WM2200_DSP_CONTROL_18 0x14
#define WM2200_DSP_CONTROL_19 0x16
#define WM2200_DSP_CONTROL_20 0x17
#define WM2200_DSP_CONTROL_21 0x18
#define WM2200_DSP_CONTROL_22 0x1A
#define WM2200_DSP_CONTROL_23 0x1B
#define WM2200_DSP_CONTROL_24 0x1C
#define WM2200_DSP_CONTROL_25 0x1E
#define WM2200_DSP_CONTROL_26 0x20
#define WM2200_DSP_CONTROL_27 0x21
#define WM2200_DSP_CONTROL_28 0x22
#define WM2200_DSP_CONTROL_29 0x23
#define WM2200_DSP_CONTROL_30 0x24
#define WM2200_DSP_CONTROL_31 0x26
/* The code assumes DCVDD is generated internally */
#define WM2200_NUM_CORE_SUPPLIES 2
static const char *wm2200_core_supply_names[WM2200_NUM_CORE_SUPPLIES] = {
"DBVDD",
"LDOVDD",
};
/* codec private data */
struct wm2200_priv {
struct wm_adsp dsp[2];
struct regmap *regmap;
struct device *dev;
struct snd_soc_component *component;
struct wm2200_pdata pdata;
struct regulator_bulk_data core_supplies[WM2200_NUM_CORE_SUPPLIES];
struct completion fll_lock;
int fll_fout;
int fll_fref;
int fll_src;
int rev;
int sysclk;
unsigned int symmetric_rates:1;
};
#define WM2200_DSP_RANGE_BASE (WM2200_MAX_REGISTER + 1)
#define WM2200_DSP_SPACING 12288
#define WM2200_DSP1_DM_BASE (WM2200_DSP_RANGE_BASE + (0 * WM2200_DSP_SPACING))
#define WM2200_DSP1_PM_BASE (WM2200_DSP_RANGE_BASE + (1 * WM2200_DSP_SPACING))
#define WM2200_DSP1_ZM_BASE (WM2200_DSP_RANGE_BASE + (2 * WM2200_DSP_SPACING))
#define WM2200_DSP2_DM_BASE (WM2200_DSP_RANGE_BASE + (3 * WM2200_DSP_SPACING))
#define WM2200_DSP2_PM_BASE (WM2200_DSP_RANGE_BASE + (4 * WM2200_DSP_SPACING))
#define WM2200_DSP2_ZM_BASE (WM2200_DSP_RANGE_BASE + (5 * WM2200_DSP_SPACING))
static const struct regmap_range_cfg wm2200_ranges[] = {
{ .name = "DSP1DM", .range_min = WM2200_DSP1_DM_BASE,
.range_max = WM2200_DSP1_DM_BASE + 12287,
.selector_reg = WM2200_DSP1_CONTROL_3,
.selector_mask = WM2200_DSP1_PAGE_BASE_DM_0_MASK,
.selector_shift = WM2200_DSP1_PAGE_BASE_DM_0_SHIFT,
.window_start = WM2200_DSP1_DM_0, .window_len = 2048, },
{ .name = "DSP1PM", .range_min = WM2200_DSP1_PM_BASE,
.range_max = WM2200_DSP1_PM_BASE + 12287,
.selector_reg = WM2200_DSP1_CONTROL_2,
.selector_mask = WM2200_DSP1_PAGE_BASE_PM_0_MASK,
.selector_shift = WM2200_DSP1_PAGE_BASE_PM_0_SHIFT,
.window_start = WM2200_DSP1_PM_0, .window_len = 768, },
{ .name = "DSP1ZM", .range_min = WM2200_DSP1_ZM_BASE,
.range_max = WM2200_DSP1_ZM_BASE + 2047,
.selector_reg = WM2200_DSP1_CONTROL_4,
.selector_mask = WM2200_DSP1_PAGE_BASE_ZM_0_MASK,
.selector_shift = WM2200_DSP1_PAGE_BASE_ZM_0_SHIFT,
.window_start = WM2200_DSP1_ZM_0, .window_len = 1024, },
{ .name = "DSP2DM", .range_min = WM2200_DSP2_DM_BASE,
.range_max = WM2200_DSP2_DM_BASE + 4095,
.selector_reg = WM2200_DSP2_CONTROL_3,
.selector_mask = WM2200_DSP2_PAGE_BASE_DM_0_MASK,
.selector_shift = WM2200_DSP2_PAGE_BASE_DM_0_SHIFT,
.window_start = WM2200_DSP2_DM_0, .window_len = 2048, },
{ .name = "DSP2PM", .range_min = WM2200_DSP2_PM_BASE,
.range_max = WM2200_DSP2_PM_BASE + 11287,
.selector_reg = WM2200_DSP2_CONTROL_2,
.selector_mask = WM2200_DSP2_PAGE_BASE_PM_0_MASK,
.selector_shift = WM2200_DSP2_PAGE_BASE_PM_0_SHIFT,
.window_start = WM2200_DSP2_PM_0, .window_len = 768, },
{ .name = "DSP2ZM", .range_min = WM2200_DSP2_ZM_BASE,
.range_max = WM2200_DSP2_ZM_BASE + 2047,
.selector_reg = WM2200_DSP2_CONTROL_4,
.selector_mask = WM2200_DSP2_PAGE_BASE_ZM_0_MASK,
.selector_shift = WM2200_DSP2_PAGE_BASE_ZM_0_SHIFT,
.window_start = WM2200_DSP2_ZM_0, .window_len = 1024, },
};
static const struct cs_dsp_region wm2200_dsp1_regions[] = {
{ .type = WMFW_ADSP1_PM, .base = WM2200_DSP1_PM_BASE },
{ .type = WMFW_ADSP1_DM, .base = WM2200_DSP1_DM_BASE },
{ .type = WMFW_ADSP1_ZM, .base = WM2200_DSP1_ZM_BASE },
};
static const struct cs_dsp_region wm2200_dsp2_regions[] = {
{ .type = WMFW_ADSP1_PM, .base = WM2200_DSP2_PM_BASE },
{ .type = WMFW_ADSP1_DM, .base = WM2200_DSP2_DM_BASE },
{ .type = WMFW_ADSP1_ZM, .base = WM2200_DSP2_ZM_BASE },
};
static const struct reg_default wm2200_reg_defaults[] = {
{ 0x000B, 0x0000 }, /* R11 - Tone Generator 1 */
{ 0x0102, 0x0000 }, /* R258 - Clocking 3 */
{ 0x0103, 0x0011 }, /* R259 - Clocking 4 */
{ 0x0111, 0x0000 }, /* R273 - FLL Control 1 */
{ 0x0112, 0x0000 }, /* R274 - FLL Control 2 */
{ 0x0113, 0x0000 }, /* R275 - FLL Control 3 */
{ 0x0114, 0x0000 }, /* R276 - FLL Control 4 */
{ 0x0116, 0x0177 }, /* R278 - FLL Control 6 */
{ 0x0117, 0x0004 }, /* R279 - FLL Control 7 */
{ 0x0119, 0x0000 }, /* R281 - FLL EFS 1 */
{ 0x011A, 0x0002 }, /* R282 - FLL EFS 2 */
{ 0x0200, 0x0000 }, /* R512 - Mic Charge Pump 1 */
{ 0x0201, 0x03FF }, /* R513 - Mic Charge Pump 2 */
{ 0x0202, 0x9BDE }, /* R514 - DM Charge Pump 1 */
{ 0x020C, 0x0000 }, /* R524 - Mic Bias Ctrl 1 */
{ 0x020D, 0x0000 }, /* R525 - Mic Bias Ctrl 2 */
{ 0x020F, 0x0000 }, /* R527 - Ear Piece Ctrl 1 */
{ 0x0210, 0x0000 }, /* R528 - Ear Piece Ctrl 2 */
{ 0x0301, 0x0000 }, /* R769 - Input Enables */
{ 0x0302, 0x2240 }, /* R770 - IN1L Control */
{ 0x0303, 0x0040 }, /* R771 - IN1R Control */
{ 0x0304, 0x2240 }, /* R772 - IN2L Control */
{ 0x0305, 0x0040 }, /* R773 - IN2R Control */
{ 0x0306, 0x2240 }, /* R774 - IN3L Control */
{ 0x0307, 0x0040 }, /* R775 - IN3R Control */
{ 0x030A, 0x0000 }, /* R778 - RXANC_SRC */
{ 0x030B, 0x0022 }, /* R779 - Input Volume Ramp */
{ 0x030C, 0x0180 }, /* R780 - ADC Digital Volume 1L */
{ 0x030D, 0x0180 }, /* R781 - ADC Digital Volume 1R */
{ 0x030E, 0x0180 }, /* R782 - ADC Digital Volume 2L */
{ 0x030F, 0x0180 }, /* R783 - ADC Digital Volume 2R */
{ 0x0310, 0x0180 }, /* R784 - ADC Digital Volume 3L */
{ 0x0311, 0x0180 }, /* R785 - ADC Digital Volume 3R */
{ 0x0400, 0x0000 }, /* R1024 - Output Enables */
{ 0x0401, 0x0000 }, /* R1025 - DAC Volume Limit 1L */
{ 0x0402, 0x0000 }, /* R1026 - DAC Volume Limit 1R */
{ 0x0403, 0x0000 }, /* R1027 - DAC Volume Limit 2L */
{ 0x0404, 0x0000 }, /* R1028 - DAC Volume Limit 2R */
{ 0x0409, 0x0000 }, /* R1033 - DAC AEC Control 1 */
{ 0x040A, 0x0022 }, /* R1034 - Output Volume Ramp */
{ 0x040B, 0x0180 }, /* R1035 - DAC Digital Volume 1L */
{ 0x040C, 0x0180 }, /* R1036 - DAC Digital Volume 1R */
{ 0x040D, 0x0180 }, /* R1037 - DAC Digital Volume 2L */
{ 0x040E, 0x0180 }, /* R1038 - DAC Digital Volume 2R */
{ 0x0417, 0x0069 }, /* R1047 - PDM 1 */
{ 0x0418, 0x0000 }, /* R1048 - PDM 2 */
{ 0x0500, 0x0000 }, /* R1280 - Audio IF 1_1 */
{ 0x0501, 0x0008 }, /* R1281 - Audio IF 1_2 */
{ 0x0502, 0x0000 }, /* R1282 - Audio IF 1_3 */
{ 0x0503, 0x0000 }, /* R1283 - Audio IF 1_4 */
{ 0x0504, 0x0000 }, /* R1284 - Audio IF 1_5 */
{ 0x0505, 0x0001 }, /* R1285 - Audio IF 1_6 */
{ 0x0506, 0x0001 }, /* R1286 - Audio IF 1_7 */
{ 0x0507, 0x0000 }, /* R1287 - Audio IF 1_8 */
{ 0x0508, 0x0000 }, /* R1288 - Audio IF 1_9 */
{ 0x0509, 0x0000 }, /* R1289 - Audio IF 1_10 */
{ 0x050A, 0x0000 }, /* R1290 - Audio IF 1_11 */
{ 0x050B, 0x0000 }, /* R1291 - Audio IF 1_12 */
{ 0x050C, 0x0000 }, /* R1292 - Audio IF 1_13 */
{ 0x050D, 0x0000 }, /* R1293 - Audio IF 1_14 */
{ 0x050E, 0x0000 }, /* R1294 - Audio IF 1_15 */
{ 0x050F, 0x0000 }, /* R1295 - Audio IF 1_16 */
{ 0x0510, 0x0000 }, /* R1296 - Audio IF 1_17 */
{ 0x0511, 0x0000 }, /* R1297 - Audio IF 1_18 */
{ 0x0512, 0x0000 }, /* R1298 - Audio IF 1_19 */
{ 0x0513, 0x0000 }, /* R1299 - Audio IF 1_20 */
{ 0x0514, 0x0000 }, /* R1300 - Audio IF 1_21 */
{ 0x0515, 0x0001 }, /* R1301 - Audio IF 1_22 */
{ 0x0600, 0x0000 }, /* R1536 - OUT1LMIX Input 1 Source */
{ 0x0601, 0x0080 }, /* R1537 - OUT1LMIX Input 1 Volume */
{ 0x0602, 0x0000 }, /* R1538 - OUT1LMIX Input 2 Source */
{ 0x0603, 0x0080 }, /* R1539 - OUT1LMIX Input 2 Volume */
{ 0x0604, 0x0000 }, /* R1540 - OUT1LMIX Input 3 Source */
{ 0x0605, 0x0080 }, /* R1541 - OUT1LMIX Input 3 Volume */
{ 0x0606, 0x0000 }, /* R1542 - OUT1LMIX Input 4 Source */
{ 0x0607, 0x0080 }, /* R1543 - OUT1LMIX Input 4 Volume */
{ 0x0608, 0x0000 }, /* R1544 - OUT1RMIX Input 1 Source */
{ 0x0609, 0x0080 }, /* R1545 - OUT1RMIX Input 1 Volume */
{ 0x060A, 0x0000 }, /* R1546 - OUT1RMIX Input 2 Source */
{ 0x060B, 0x0080 }, /* R1547 - OUT1RMIX Input 2 Volume */
{ 0x060C, 0x0000 }, /* R1548 - OUT1RMIX Input 3 Source */
{ 0x060D, 0x0080 }, /* R1549 - OUT1RMIX Input 3 Volume */
{ 0x060E, 0x0000 }, /* R1550 - OUT1RMIX Input 4 Source */
{ 0x060F, 0x0080 }, /* R1551 - OUT1RMIX Input 4 Volume */
{ 0x0610, 0x0000 }, /* R1552 - OUT2LMIX Input 1 Source */
{ 0x0611, 0x0080 }, /* R1553 - OUT2LMIX Input 1 Volume */
{ 0x0612, 0x0000 }, /* R1554 - OUT2LMIX Input 2 Source */
{ 0x0613, 0x0080 }, /* R1555 - OUT2LMIX Input 2 Volume */
{ 0x0614, 0x0000 }, /* R1556 - OUT2LMIX Input 3 Source */
{ 0x0615, 0x0080 }, /* R1557 - OUT2LMIX Input 3 Volume */
{ 0x0616, 0x0000 }, /* R1558 - OUT2LMIX Input 4 Source */
{ 0x0617, 0x0080 }, /* R1559 - OUT2LMIX Input 4 Volume */
{ 0x0618, 0x0000 }, /* R1560 - OUT2RMIX Input 1 Source */
{ 0x0619, 0x0080 }, /* R1561 - OUT2RMIX Input 1 Volume */
{ 0x061A, 0x0000 }, /* R1562 - OUT2RMIX Input 2 Source */
{ 0x061B, 0x0080 }, /* R1563 - OUT2RMIX Input 2 Volume */
{ 0x061C, 0x0000 }, /* R1564 - OUT2RMIX Input 3 Source */
{ 0x061D, 0x0080 }, /* R1565 - OUT2RMIX Input 3 Volume */
{ 0x061E, 0x0000 }, /* R1566 - OUT2RMIX Input 4 Source */
{ 0x061F, 0x0080 }, /* R1567 - OUT2RMIX Input 4 Volume */
{ 0x0620, 0x0000 }, /* R1568 - AIF1TX1MIX Input 1 Source */
{ 0x0621, 0x0080 }, /* R1569 - AIF1TX1MIX Input 1 Volume */
{ 0x0622, 0x0000 }, /* R1570 - AIF1TX1MIX Input 2 Source */
{ 0x0623, 0x0080 }, /* R1571 - AIF1TX1MIX Input 2 Volume */
{ 0x0624, 0x0000 }, /* R1572 - AIF1TX1MIX Input 3 Source */
{ 0x0625, 0x0080 }, /* R1573 - AIF1TX1MIX Input 3 Volume */
{ 0x0626, 0x0000 }, /* R1574 - AIF1TX1MIX Input 4 Source */
{ 0x0627, 0x0080 }, /* R1575 - AIF1TX1MIX Input 4 Volume */
{ 0x0628, 0x0000 }, /* R1576 - AIF1TX2MIX Input 1 Source */
{ 0x0629, 0x0080 }, /* R1577 - AIF1TX2MIX Input 1 Volume */
{ 0x062A, 0x0000 }, /* R1578 - AIF1TX2MIX Input 2 Source */
{ 0x062B, 0x0080 }, /* R1579 - AIF1TX2MIX Input 2 Volume */
{ 0x062C, 0x0000 }, /* R1580 - AIF1TX2MIX Input 3 Source */
{ 0x062D, 0x0080 }, /* R1581 - AIF1TX2MIX Input 3 Volume */
{ 0x062E, 0x0000 }, /* R1582 - AIF1TX2MIX Input 4 Source */
{ 0x062F, 0x0080 }, /* R1583 - AIF1TX2MIX Input 4 Volume */
{ 0x0630, 0x0000 }, /* R1584 - AIF1TX3MIX Input 1 Source */
{ 0x0631, 0x0080 }, /* R1585 - AIF1TX3MIX Input 1 Volume */
{ 0x0632, 0x0000 }, /* R1586 - AIF1TX3MIX Input 2 Source */
{ 0x0633, 0x0080 }, /* R1587 - AIF1TX3MIX Input 2 Volume */
{ 0x0634, 0x0000 }, /* R1588 - AIF1TX3MIX Input 3 Source */
{ 0x0635, 0x0080 }, /* R1589 - AIF1TX3MIX Input 3 Volume */
{ 0x0636, 0x0000 }, /* R1590 - AIF1TX3MIX Input 4 Source */
{ 0x0637, 0x0080 }, /* R1591 - AIF1TX3MIX Input 4 Volume */
{ 0x0638, 0x0000 }, /* R1592 - AIF1TX4MIX Input 1 Source */
{ 0x0639, 0x0080 }, /* R1593 - AIF1TX4MIX Input 1 Volume */
{ 0x063A, 0x0000 }, /* R1594 - AIF1TX4MIX Input 2 Source */
{ 0x063B, 0x0080 }, /* R1595 - AIF1TX4MIX Input 2 Volume */
{ 0x063C, 0x0000 }, /* R1596 - AIF1TX4MIX Input 3 Source */
{ 0x063D, 0x0080 }, /* R1597 - AIF1TX4MIX Input 3 Volume */
{ 0x063E, 0x0000 }, /* R1598 - AIF1TX4MIX Input 4 Source */
{ 0x063F, 0x0080 }, /* R1599 - AIF1TX4MIX Input 4 Volume */
{ 0x0640, 0x0000 }, /* R1600 - AIF1TX5MIX Input 1 Source */
{ 0x0641, 0x0080 }, /* R1601 - AIF1TX5MIX Input 1 Volume */
{ 0x0642, 0x0000 }, /* R1602 - AIF1TX5MIX Input 2 Source */
{ 0x0643, 0x0080 }, /* R1603 - AIF1TX5MIX Input 2 Volume */
{ 0x0644, 0x0000 }, /* R1604 - AIF1TX5MIX Input 3 Source */
{ 0x0645, 0x0080 }, /* R1605 - AIF1TX5MIX Input 3 Volume */
{ 0x0646, 0x0000 }, /* R1606 - AIF1TX5MIX Input 4 Source */
{ 0x0647, 0x0080 }, /* R1607 - AIF1TX5MIX Input 4 Volume */
{ 0x0648, 0x0000 }, /* R1608 - AIF1TX6MIX Input 1 Source */
{ 0x0649, 0x0080 }, /* R1609 - AIF1TX6MIX Input 1 Volume */
{ 0x064A, 0x0000 }, /* R1610 - AIF1TX6MIX Input 2 Source */
{ 0x064B, 0x0080 }, /* R1611 - AIF1TX6MIX Input 2 Volume */
{ 0x064C, 0x0000 }, /* R1612 - AIF1TX6MIX Input 3 Source */
{ 0x064D, 0x0080 }, /* R1613 - AIF1TX6MIX Input 3 Volume */
{ 0x064E, 0x0000 }, /* R1614 - AIF1TX6MIX Input 4 Source */
{ 0x064F, 0x0080 }, /* R1615 - AIF1TX6MIX Input 4 Volume */
{ 0x0650, 0x0000 }, /* R1616 - EQLMIX Input 1 Source */
{ 0x0651, 0x0080 }, /* R1617 - EQLMIX Input 1 Volume */
{ 0x0652, 0x0000 }, /* R1618 - EQLMIX Input 2 Source */
{ 0x0653, 0x0080 }, /* R1619 - EQLMIX Input 2 Volume */
{ 0x0654, 0x0000 }, /* R1620 - EQLMIX Input 3 Source */
{ 0x0655, 0x0080 }, /* R1621 - EQLMIX Input 3 Volume */
{ 0x0656, 0x0000 }, /* R1622 - EQLMIX Input 4 Source */
{ 0x0657, 0x0080 }, /* R1623 - EQLMIX Input 4 Volume */
{ 0x0658, 0x0000 }, /* R1624 - EQRMIX Input 1 Source */
{ 0x0659, 0x0080 }, /* R1625 - EQRMIX Input 1 Volume */
{ 0x065A, 0x0000 }, /* R1626 - EQRMIX Input 2 Source */
{ 0x065B, 0x0080 }, /* R1627 - EQRMIX Input 2 Volume */
{ 0x065C, 0x0000 }, /* R1628 - EQRMIX Input 3 Source */
{ 0x065D, 0x0080 }, /* R1629 - EQRMIX Input 3 Volume */
{ 0x065E, 0x0000 }, /* R1630 - EQRMIX Input 4 Source */
{ 0x065F, 0x0080 }, /* R1631 - EQRMIX Input 4 Volume */
{ 0x0660, 0x0000 }, /* R1632 - LHPF1MIX Input 1 Source */
{ 0x0661, 0x0080 }, /* R1633 - LHPF1MIX Input 1 Volume */
{ 0x0662, 0x0000 }, /* R1634 - LHPF1MIX Input 2 Source */
{ 0x0663, 0x0080 }, /* R1635 - LHPF1MIX Input 2 Volume */
{ 0x0664, 0x0000 }, /* R1636 - LHPF1MIX Input 3 Source */
{ 0x0665, 0x0080 }, /* R1637 - LHPF1MIX Input 3 Volume */
{ 0x0666, 0x0000 }, /* R1638 - LHPF1MIX Input 4 Source */
{ 0x0667, 0x0080 }, /* R1639 - LHPF1MIX Input 4 Volume */
{ 0x0668, 0x0000 }, /* R1640 - LHPF2MIX Input 1 Source */
{ 0x0669, 0x0080 }, /* R1641 - LHPF2MIX Input 1 Volume */
{ 0x066A, 0x0000 }, /* R1642 - LHPF2MIX Input 2 Source */
{ 0x066B, 0x0080 }, /* R1643 - LHPF2MIX Input 2 Volume */
{ 0x066C, 0x0000 }, /* R1644 - LHPF2MIX Input 3 Source */
{ 0x066D, 0x0080 }, /* R1645 - LHPF2MIX Input 3 Volume */
{ 0x066E, 0x0000 }, /* R1646 - LHPF2MIX Input 4 Source */
{ 0x066F, 0x0080 }, /* R1647 - LHPF2MIX Input 4 Volume */
{ 0x0670, 0x0000 }, /* R1648 - DSP1LMIX Input 1 Source */
{ 0x0671, 0x0080 }, /* R1649 - DSP1LMIX Input 1 Volume */
{ 0x0672, 0x0000 }, /* R1650 - DSP1LMIX Input 2 Source */
{ 0x0673, 0x0080 }, /* R1651 - DSP1LMIX Input 2 Volume */
{ 0x0674, 0x0000 }, /* R1652 - DSP1LMIX Input 3 Source */
{ 0x0675, 0x0080 }, /* R1653 - DSP1LMIX Input 3 Volume */
{ 0x0676, 0x0000 }, /* R1654 - DSP1LMIX Input 4 Source */
{ 0x0677, 0x0080 }, /* R1655 - DSP1LMIX Input 4 Volume */
{ 0x0678, 0x0000 }, /* R1656 - DSP1RMIX Input 1 Source */
{ 0x0679, 0x0080 }, /* R1657 - DSP1RMIX Input 1 Volume */
{ 0x067A, 0x0000 }, /* R1658 - DSP1RMIX Input 2 Source */
{ 0x067B, 0x0080 }, /* R1659 - DSP1RMIX Input 2 Volume */
{ 0x067C, 0x0000 }, /* R1660 - DSP1RMIX Input 3 Source */
{ 0x067D, 0x0080 }, /* R1661 - DSP1RMIX Input 3 Volume */
{ 0x067E, 0x0000 }, /* R1662 - DSP1RMIX Input 4 Source */
{ 0x067F, 0x0080 }, /* R1663 - DSP1RMIX Input 4 Volume */
{ 0x0680, 0x0000 }, /* R1664 - DSP1AUX1MIX Input 1 Source */
{ 0x0681, 0x0000 }, /* R1665 - DSP1AUX2MIX Input 1 Source */
{ 0x0682, 0x0000 }, /* R1666 - DSP1AUX3MIX Input 1 Source */
{ 0x0683, 0x0000 }, /* R1667 - DSP1AUX4MIX Input 1 Source */
{ 0x0684, 0x0000 }, /* R1668 - DSP1AUX5MIX Input 1 Source */
{ 0x0685, 0x0000 }, /* R1669 - DSP1AUX6MIX Input 1 Source */
{ 0x0686, 0x0000 }, /* R1670 - DSP2LMIX Input 1 Source */
{ 0x0687, 0x0080 }, /* R1671 - DSP2LMIX Input 1 Volume */
{ 0x0688, 0x0000 }, /* R1672 - DSP2LMIX Input 2 Source */
{ 0x0689, 0x0080 }, /* R1673 - DSP2LMIX Input 2 Volume */
{ 0x068A, 0x0000 }, /* R1674 - DSP2LMIX Input 3 Source */
{ 0x068B, 0x0080 }, /* R1675 - DSP2LMIX Input 3 Volume */
{ 0x068C, 0x0000 }, /* R1676 - DSP2LMIX Input 4 Source */
{ 0x068D, 0x0080 }, /* R1677 - DSP2LMIX Input 4 Volume */
{ 0x068E, 0x0000 }, /* R1678 - DSP2RMIX Input 1 Source */
{ 0x068F, 0x0080 }, /* R1679 - DSP2RMIX Input 1 Volume */
{ 0x0690, 0x0000 }, /* R1680 - DSP2RMIX Input 2 Source */
{ 0x0691, 0x0080 }, /* R1681 - DSP2RMIX Input 2 Volume */
{ 0x0692, 0x0000 }, /* R1682 - DSP2RMIX Input 3 Source */
{ 0x0693, 0x0080 }, /* R1683 - DSP2RMIX Input 3 Volume */
{ 0x0694, 0x0000 }, /* R1684 - DSP2RMIX Input 4 Source */
{ 0x0695, 0x0080 }, /* R1685 - DSP2RMIX Input 4 Volume */
{ 0x0696, 0x0000 }, /* R1686 - DSP2AUX1MIX Input 1 Source */
{ 0x0697, 0x0000 }, /* R1687 - DSP2AUX2MIX Input 1 Source */
{ 0x0698, 0x0000 }, /* R1688 - DSP2AUX3MIX Input 1 Source */
{ 0x0699, 0x0000 }, /* R1689 - DSP2AUX4MIX Input 1 Source */
{ 0x069A, 0x0000 }, /* R1690 - DSP2AUX5MIX Input 1 Source */
{ 0x069B, 0x0000 }, /* R1691 - DSP2AUX6MIX Input 1 Source */
{ 0x0700, 0xA101 }, /* R1792 - GPIO CTRL 1 */
{ 0x0701, 0xA101 }, /* R1793 - GPIO CTRL 2 */
{ 0x0702, 0xA101 }, /* R1794 - GPIO CTRL 3 */
{ 0x0703, 0xA101 }, /* R1795 - GPIO CTRL 4 */
{ 0x0709, 0x0000 }, /* R1801 - Misc Pad Ctrl 1 */
{ 0x0801, 0x00FF }, /* R2049 - Interrupt Status 1 Mask */
{ 0x0804, 0xFFFF }, /* R2052 - Interrupt Status 2 Mask */
{ 0x0808, 0x0000 }, /* R2056 - Interrupt Control */
{ 0x0900, 0x0000 }, /* R2304 - EQL_1 */
{ 0x0901, 0x0000 }, /* R2305 - EQL_2 */
{ 0x0902, 0x0000 }, /* R2306 - EQL_3 */
{ 0x0903, 0x0000 }, /* R2307 - EQL_4 */
{ 0x0904, 0x0000 }, /* R2308 - EQL_5 */
{ 0x0905, 0x0000 }, /* R2309 - EQL_6 */
{ 0x0906, 0x0000 }, /* R2310 - EQL_7 */
{ 0x0907, 0x0000 }, /* R2311 - EQL_8 */
{ 0x0908, 0x0000 }, /* R2312 - EQL_9 */
{ 0x0909, 0x0000 }, /* R2313 - EQL_10 */
{ 0x090A, 0x0000 }, /* R2314 - EQL_11 */
{ 0x090B, 0x0000 }, /* R2315 - EQL_12 */
{ 0x090C, 0x0000 }, /* R2316 - EQL_13 */
{ 0x090D, 0x0000 }, /* R2317 - EQL_14 */
{ 0x090E, 0x0000 }, /* R2318 - EQL_15 */
{ 0x090F, 0x0000 }, /* R2319 - EQL_16 */
{ 0x0910, 0x0000 }, /* R2320 - EQL_17 */
{ 0x0911, 0x0000 }, /* R2321 - EQL_18 */
{ 0x0912, 0x0000 }, /* R2322 - EQL_19 */
{ 0x0913, 0x0000 }, /* R2323 - EQL_20 */
{ 0x0916, 0x0000 }, /* R2326 - EQR_1 */
{ 0x0917, 0x0000 }, /* R2327 - EQR_2 */
{ 0x0918, 0x0000 }, /* R2328 - EQR_3 */
{ 0x0919, 0x0000 }, /* R2329 - EQR_4 */
{ 0x091A, 0x0000 }, /* R2330 - EQR_5 */
{ 0x091B, 0x0000 }, /* R2331 - EQR_6 */
{ 0x091C, 0x0000 }, /* R2332 - EQR_7 */
{ 0x091D, 0x0000 }, /* R2333 - EQR_8 */
{ 0x091E, 0x0000 }, /* R2334 - EQR_9 */
{ 0x091F, 0x0000 }, /* R2335 - EQR_10 */
{ 0x0920, 0x0000 }, /* R2336 - EQR_11 */
{ 0x0921, 0x0000 }, /* R2337 - EQR_12 */
{ 0x0922, 0x0000 }, /* R2338 - EQR_13 */
{ 0x0923, 0x0000 }, /* R2339 - EQR_14 */
{ 0x0924, 0x0000 }, /* R2340 - EQR_15 */
{ 0x0925, 0x0000 }, /* R2341 - EQR_16 */
{ 0x0926, 0x0000 }, /* R2342 - EQR_17 */
{ 0x0927, 0x0000 }, /* R2343 - EQR_18 */
{ 0x0928, 0x0000 }, /* R2344 - EQR_19 */
{ 0x0929, 0x0000 }, /* R2345 - EQR_20 */
{ 0x093E, 0x0000 }, /* R2366 - HPLPF1_1 */
{ 0x093F, 0x0000 }, /* R2367 - HPLPF1_2 */
{ 0x0942, 0x0000 }, /* R2370 - HPLPF2_1 */
{ 0x0943, 0x0000 }, /* R2371 - HPLPF2_2 */
{ 0x0A00, 0x0000 }, /* R2560 - DSP1 Control 1 */
{ 0x0A02, 0x0000 }, /* R2562 - DSP1 Control 2 */
{ 0x0A03, 0x0000 }, /* R2563 - DSP1 Control 3 */
{ 0x0A04, 0x0000 }, /* R2564 - DSP1 Control 4 */
{ 0x0A06, 0x0000 }, /* R2566 - DSP1 Control 5 */
{ 0x0A07, 0x0000 }, /* R2567 - DSP1 Control 6 */
{ 0x0A08, 0x0000 }, /* R2568 - DSP1 Control 7 */
{ 0x0A09, 0x0000 }, /* R2569 - DSP1 Control 8 */
{ 0x0A0A, 0x0000 }, /* R2570 - DSP1 Control 9 */
{ 0x0A0B, 0x0000 }, /* R2571 - DSP1 Control 10 */
{ 0x0A0C, 0x0000 }, /* R2572 - DSP1 Control 11 */
{ 0x0A0D, 0x0000 }, /* R2573 - DSP1 Control 12 */
{ 0x0A0F, 0x0000 }, /* R2575 - DSP1 Control 13 */
{ 0x0A10, 0x0000 }, /* R2576 - DSP1 Control 14 */
{ 0x0A11, 0x0000 }, /* R2577 - DSP1 Control 15 */
{ 0x0A12, 0x0000 }, /* R2578 - DSP1 Control 16 */
{ 0x0A13, 0x0000 }, /* R2579 - DSP1 Control 17 */
{ 0x0A14, 0x0000 }, /* R2580 - DSP1 Control 18 */
{ 0x0A16, 0x0000 }, /* R2582 - DSP1 Control 19 */
{ 0x0A17, 0x0000 }, /* R2583 - DSP1 Control 20 */
{ 0x0A18, 0x0000 }, /* R2584 - DSP1 Control 21 */
{ 0x0A1A, 0x1800 }, /* R2586 - DSP1 Control 22 */
{ 0x0A1B, 0x1000 }, /* R2587 - DSP1 Control 23 */
{ 0x0A1C, 0x0400 }, /* R2588 - DSP1 Control 24 */
{ 0x0A1E, 0x0000 }, /* R2590 - DSP1 Control 25 */
{ 0x0A20, 0x0000 }, /* R2592 - DSP1 Control 26 */
{ 0x0A21, 0x0000 }, /* R2593 - DSP1 Control 27 */
{ 0x0A22, 0x0000 }, /* R2594 - DSP1 Control 28 */
{ 0x0A23, 0x0000 }, /* R2595 - DSP1 Control 29 */
{ 0x0A24, 0x0000 }, /* R2596 - DSP1 Control 30 */
{ 0x0A26, 0x0000 }, /* R2598 - DSP1 Control 31 */
{ 0x0B00, 0x0000 }, /* R2816 - DSP2 Control 1 */
{ 0x0B02, 0x0000 }, /* R2818 - DSP2 Control 2 */
{ 0x0B03, 0x0000 }, /* R2819 - DSP2 Control 3 */
{ 0x0B04, 0x0000 }, /* R2820 - DSP2 Control 4 */
{ 0x0B06, 0x0000 }, /* R2822 - DSP2 Control 5 */
{ 0x0B07, 0x0000 }, /* R2823 - DSP2 Control 6 */
{ 0x0B08, 0x0000 }, /* R2824 - DSP2 Control 7 */
{ 0x0B09, 0x0000 }, /* R2825 - DSP2 Control 8 */
{ 0x0B0A, 0x0000 }, /* R2826 - DSP2 Control 9 */
{ 0x0B0B, 0x0000 }, /* R2827 - DSP2 Control 10 */
{ 0x0B0C, 0x0000 }, /* R2828 - DSP2 Control 11 */
{ 0x0B0D, 0x0000 }, /* R2829 - DSP2 Control 12 */
{ 0x0B0F, 0x0000 }, /* R2831 - DSP2 Control 13 */
{ 0x0B10, 0x0000 }, /* R2832 - DSP2 Control 14 */
{ 0x0B11, 0x0000 }, /* R2833 - DSP2 Control 15 */
{ 0x0B12, 0x0000 }, /* R2834 - DSP2 Control 16 */
{ 0x0B13, 0x0000 }, /* R2835 - DSP2 Control 17 */
{ 0x0B14, 0x0000 }, /* R2836 - DSP2 Control 18 */
{ 0x0B16, 0x0000 }, /* R2838 - DSP2 Control 19 */
{ 0x0B17, 0x0000 }, /* R2839 - DSP2 Control 20 */
{ 0x0B18, 0x0000 }, /* R2840 - DSP2 Control 21 */
{ 0x0B1A, 0x0800 }, /* R2842 - DSP2 Control 22 */
{ 0x0B1B, 0x1000 }, /* R2843 - DSP2 Control 23 */
{ 0x0B1C, 0x0400 }, /* R2844 - DSP2 Control 24 */
{ 0x0B1E, 0x0000 }, /* R2846 - DSP2 Control 25 */
{ 0x0B20, 0x0000 }, /* R2848 - DSP2 Control 26 */
{ 0x0B21, 0x0000 }, /* R2849 - DSP2 Control 27 */
{ 0x0B22, 0x0000 }, /* R2850 - DSP2 Control 28 */
{ 0x0B23, 0x0000 }, /* R2851 - DSP2 Control 29 */
{ 0x0B24, 0x0000 }, /* R2852 - DSP2 Control 30 */
{ 0x0B26, 0x0000 }, /* R2854 - DSP2 Control 31 */
};
static bool wm2200_volatile_register(struct device *dev, unsigned int reg)
{
int i;
for (i = 0; i < ARRAY_SIZE(wm2200_ranges); i++)
if ((reg >= wm2200_ranges[i].window_start &&
reg <= wm2200_ranges[i].window_start +
wm2200_ranges[i].window_len) ||
(reg >= wm2200_ranges[i].range_min &&
reg <= wm2200_ranges[i].range_max))
return true;
switch (reg) {
case WM2200_SOFTWARE_RESET:
case WM2200_DEVICE_REVISION:
case WM2200_ADPS1_IRQ0:
case WM2200_ADPS1_IRQ1:
case WM2200_INTERRUPT_STATUS_1:
case WM2200_INTERRUPT_STATUS_2:
case WM2200_INTERRUPT_RAW_STATUS_2:
return true;
default:
return false;
}
}
static bool wm2200_readable_register(struct device *dev, unsigned int reg)
{
int i;
for (i = 0; i < ARRAY_SIZE(wm2200_ranges); i++)
if ((reg >= wm2200_ranges[i].window_start &&
reg <= wm2200_ranges[i].window_start +
wm2200_ranges[i].window_len) ||
(reg >= wm2200_ranges[i].range_min &&
reg <= wm2200_ranges[i].range_max))
return true;
switch (reg) {
case WM2200_SOFTWARE_RESET:
case WM2200_DEVICE_REVISION:
case WM2200_TONE_GENERATOR_1:
case WM2200_CLOCKING_3:
case WM2200_CLOCKING_4:
case WM2200_FLL_CONTROL_1:
case WM2200_FLL_CONTROL_2:
case WM2200_FLL_CONTROL_3:
case WM2200_FLL_CONTROL_4:
case WM2200_FLL_CONTROL_6:
case WM2200_FLL_CONTROL_7:
case WM2200_FLL_EFS_1:
case WM2200_FLL_EFS_2:
case WM2200_MIC_CHARGE_PUMP_1:
case WM2200_MIC_CHARGE_PUMP_2:
case WM2200_DM_CHARGE_PUMP_1:
case WM2200_MIC_BIAS_CTRL_1:
case WM2200_MIC_BIAS_CTRL_2:
case WM2200_EAR_PIECE_CTRL_1:
case WM2200_EAR_PIECE_CTRL_2:
case WM2200_INPUT_ENABLES:
case WM2200_IN1L_CONTROL:
case WM2200_IN1R_CONTROL:
case WM2200_IN2L_CONTROL:
case WM2200_IN2R_CONTROL:
case WM2200_IN3L_CONTROL:
case WM2200_IN3R_CONTROL:
case WM2200_RXANC_SRC:
case WM2200_INPUT_VOLUME_RAMP:
case WM2200_ADC_DIGITAL_VOLUME_1L:
case WM2200_ADC_DIGITAL_VOLUME_1R:
case WM2200_ADC_DIGITAL_VOLUME_2L:
case WM2200_ADC_DIGITAL_VOLUME_2R:
case WM2200_ADC_DIGITAL_VOLUME_3L:
case WM2200_ADC_DIGITAL_VOLUME_3R:
case WM2200_OUTPUT_ENABLES:
case WM2200_DAC_VOLUME_LIMIT_1L:
case WM2200_DAC_VOLUME_LIMIT_1R:
case WM2200_DAC_VOLUME_LIMIT_2L:
case WM2200_DAC_VOLUME_LIMIT_2R:
case WM2200_DAC_AEC_CONTROL_1:
case WM2200_OUTPUT_VOLUME_RAMP:
case WM2200_DAC_DIGITAL_VOLUME_1L:
case WM2200_DAC_DIGITAL_VOLUME_1R:
case WM2200_DAC_DIGITAL_VOLUME_2L:
case WM2200_DAC_DIGITAL_VOLUME_2R:
case WM2200_PDM_1:
case WM2200_PDM_2:
case WM2200_AUDIO_IF_1_1:
case WM2200_AUDIO_IF_1_2:
case WM2200_AUDIO_IF_1_3:
case WM2200_AUDIO_IF_1_4:
case WM2200_AUDIO_IF_1_5:
case WM2200_AUDIO_IF_1_6:
case WM2200_AUDIO_IF_1_7:
case WM2200_AUDIO_IF_1_8:
case WM2200_AUDIO_IF_1_9:
case WM2200_AUDIO_IF_1_10:
case WM2200_AUDIO_IF_1_11:
case WM2200_AUDIO_IF_1_12:
case WM2200_AUDIO_IF_1_13:
case WM2200_AUDIO_IF_1_14:
case WM2200_AUDIO_IF_1_15:
case WM2200_AUDIO_IF_1_16:
case WM2200_AUDIO_IF_1_17:
case WM2200_AUDIO_IF_1_18:
case WM2200_AUDIO_IF_1_19:
case WM2200_AUDIO_IF_1_20:
case WM2200_AUDIO_IF_1_21:
case WM2200_AUDIO_IF_1_22:
case WM2200_OUT1LMIX_INPUT_1_SOURCE:
case WM2200_OUT1LMIX_INPUT_1_VOLUME:
case WM2200_OUT1LMIX_INPUT_2_SOURCE:
case WM2200_OUT1LMIX_INPUT_2_VOLUME:
case WM2200_OUT1LMIX_INPUT_3_SOURCE:
case WM2200_OUT1LMIX_INPUT_3_VOLUME:
case WM2200_OUT1LMIX_INPUT_4_SOURCE:
case WM2200_OUT1LMIX_INPUT_4_VOLUME:
case WM2200_OUT1RMIX_INPUT_1_SOURCE:
case WM2200_OUT1RMIX_INPUT_1_VOLUME:
case WM2200_OUT1RMIX_INPUT_2_SOURCE:
case WM2200_OUT1RMIX_INPUT_2_VOLUME:
case WM2200_OUT1RMIX_INPUT_3_SOURCE:
case WM2200_OUT1RMIX_INPUT_3_VOLUME:
case WM2200_OUT1RMIX_INPUT_4_SOURCE:
case WM2200_OUT1RMIX_INPUT_4_VOLUME:
case WM2200_OUT2LMIX_INPUT_1_SOURCE:
case WM2200_OUT2LMIX_INPUT_1_VOLUME:
case WM2200_OUT2LMIX_INPUT_2_SOURCE:
case WM2200_OUT2LMIX_INPUT_2_VOLUME:
case WM2200_OUT2LMIX_INPUT_3_SOURCE:
case WM2200_OUT2LMIX_INPUT_3_VOLUME:
case WM2200_OUT2LMIX_INPUT_4_SOURCE:
case WM2200_OUT2LMIX_INPUT_4_VOLUME:
case WM2200_OUT2RMIX_INPUT_1_SOURCE:
case WM2200_OUT2RMIX_INPUT_1_VOLUME:
case WM2200_OUT2RMIX_INPUT_2_SOURCE:
case WM2200_OUT2RMIX_INPUT_2_VOLUME:
case WM2200_OUT2RMIX_INPUT_3_SOURCE:
case WM2200_OUT2RMIX_INPUT_3_VOLUME:
case WM2200_OUT2RMIX_INPUT_4_SOURCE:
case WM2200_OUT2RMIX_INPUT_4_VOLUME:
case WM2200_AIF1TX1MIX_INPUT_1_SOURCE:
case WM2200_AIF1TX1MIX_INPUT_1_VOLUME:
case WM2200_AIF1TX1MIX_INPUT_2_SOURCE:
case WM2200_AIF1TX1MIX_INPUT_2_VOLUME:
case WM2200_AIF1TX1MIX_INPUT_3_SOURCE:
case WM2200_AIF1TX1MIX_INPUT_3_VOLUME:
case WM2200_AIF1TX1MIX_INPUT_4_SOURCE:
case WM2200_AIF1TX1MIX_INPUT_4_VOLUME:
case WM2200_AIF1TX2MIX_INPUT_1_SOURCE:
case WM2200_AIF1TX2MIX_INPUT_1_VOLUME:
case WM2200_AIF1TX2MIX_INPUT_2_SOURCE:
case WM2200_AIF1TX2MIX_INPUT_2_VOLUME:
case WM2200_AIF1TX2MIX_INPUT_3_SOURCE:
case WM2200_AIF1TX2MIX_INPUT_3_VOLUME:
case WM2200_AIF1TX2MIX_INPUT_4_SOURCE:
case WM2200_AIF1TX2MIX_INPUT_4_VOLUME:
case WM2200_AIF1TX3MIX_INPUT_1_SOURCE:
case WM2200_AIF1TX3MIX_INPUT_1_VOLUME:
case WM2200_AIF1TX3MIX_INPUT_2_SOURCE:
case WM2200_AIF1TX3MIX_INPUT_2_VOLUME:
case WM2200_AIF1TX3MIX_INPUT_3_SOURCE:
case WM2200_AIF1TX3MIX_INPUT_3_VOLUME:
case WM2200_AIF1TX3MIX_INPUT_4_SOURCE:
case WM2200_AIF1TX3MIX_INPUT_4_VOLUME:
case WM2200_AIF1TX4MIX_INPUT_1_SOURCE:
case WM2200_AIF1TX4MIX_INPUT_1_VOLUME:
case WM2200_AIF1TX4MIX_INPUT_2_SOURCE:
case WM2200_AIF1TX4MIX_INPUT_2_VOLUME:
case WM2200_AIF1TX4MIX_INPUT_3_SOURCE:
case WM2200_AIF1TX4MIX_INPUT_3_VOLUME:
case WM2200_AIF1TX4MIX_INPUT_4_SOURCE:
case WM2200_AIF1TX4MIX_INPUT_4_VOLUME:
case WM2200_AIF1TX5MIX_INPUT_1_SOURCE:
case WM2200_AIF1TX5MIX_INPUT_1_VOLUME:
case WM2200_AIF1TX5MIX_INPUT_2_SOURCE:
case WM2200_AIF1TX5MIX_INPUT_2_VOLUME:
case WM2200_AIF1TX5MIX_INPUT_3_SOURCE:
case WM2200_AIF1TX5MIX_INPUT_3_VOLUME:
case WM2200_AIF1TX5MIX_INPUT_4_SOURCE:
case WM2200_AIF1TX5MIX_INPUT_4_VOLUME:
case WM2200_AIF1TX6MIX_INPUT_1_SOURCE:
case WM2200_AIF1TX6MIX_INPUT_1_VOLUME:
case WM2200_AIF1TX6MIX_INPUT_2_SOURCE:
case WM2200_AIF1TX6MIX_INPUT_2_VOLUME:
case WM2200_AIF1TX6MIX_INPUT_3_SOURCE:
case WM2200_AIF1TX6MIX_INPUT_3_VOLUME:
case WM2200_AIF1TX6MIX_INPUT_4_SOURCE:
case WM2200_AIF1TX6MIX_INPUT_4_VOLUME:
case WM2200_EQLMIX_INPUT_1_SOURCE:
case WM2200_EQLMIX_INPUT_1_VOLUME:
case WM2200_EQLMIX_INPUT_2_SOURCE:
case WM2200_EQLMIX_INPUT_2_VOLUME:
case WM2200_EQLMIX_INPUT_3_SOURCE:
case WM2200_EQLMIX_INPUT_3_VOLUME:
case WM2200_EQLMIX_INPUT_4_SOURCE:
case WM2200_EQLMIX_INPUT_4_VOLUME:
case WM2200_EQRMIX_INPUT_1_SOURCE:
case WM2200_EQRMIX_INPUT_1_VOLUME:
case WM2200_EQRMIX_INPUT_2_SOURCE:
case WM2200_EQRMIX_INPUT_2_VOLUME:
case WM2200_EQRMIX_INPUT_3_SOURCE:
case WM2200_EQRMIX_INPUT_3_VOLUME:
case WM2200_EQRMIX_INPUT_4_SOURCE:
case WM2200_EQRMIX_INPUT_4_VOLUME:
case WM2200_LHPF1MIX_INPUT_1_SOURCE:
case WM2200_LHPF1MIX_INPUT_1_VOLUME:
case WM2200_LHPF1MIX_INPUT_2_SOURCE:
case WM2200_LHPF1MIX_INPUT_2_VOLUME:
case WM2200_LHPF1MIX_INPUT_3_SOURCE:
case WM2200_LHPF1MIX_INPUT_3_VOLUME:
case WM2200_LHPF1MIX_INPUT_4_SOURCE:
case WM2200_LHPF1MIX_INPUT_4_VOLUME:
case WM2200_LHPF2MIX_INPUT_1_SOURCE:
case WM2200_LHPF2MIX_INPUT_1_VOLUME:
case WM2200_LHPF2MIX_INPUT_2_SOURCE:
case WM2200_LHPF2MIX_INPUT_2_VOLUME:
case WM2200_LHPF2MIX_INPUT_3_SOURCE:
case WM2200_LHPF2MIX_INPUT_3_VOLUME:
case WM2200_LHPF2MIX_INPUT_4_SOURCE:
case WM2200_LHPF2MIX_INPUT_4_VOLUME:
case WM2200_DSP1LMIX_INPUT_1_SOURCE:
case WM2200_DSP1LMIX_INPUT_1_VOLUME:
case WM2200_DSP1LMIX_INPUT_2_SOURCE:
case WM2200_DSP1LMIX_INPUT_2_VOLUME:
case WM2200_DSP1LMIX_INPUT_3_SOURCE:
case WM2200_DSP1LMIX_INPUT_3_VOLUME:
case WM2200_DSP1LMIX_INPUT_4_SOURCE:
case WM2200_DSP1LMIX_INPUT_4_VOLUME:
case WM2200_DSP1RMIX_INPUT_1_SOURCE:
case WM2200_DSP1RMIX_INPUT_1_VOLUME:
case WM2200_DSP1RMIX_INPUT_2_SOURCE:
case WM2200_DSP1RMIX_INPUT_2_VOLUME:
case WM2200_DSP1RMIX_INPUT_3_SOURCE:
case WM2200_DSP1RMIX_INPUT_3_VOLUME:
case WM2200_DSP1RMIX_INPUT_4_SOURCE:
case WM2200_DSP1RMIX_INPUT_4_VOLUME:
case WM2200_DSP1AUX1MIX_INPUT_1_SOURCE:
case WM2200_DSP1AUX2MIX_INPUT_1_SOURCE:
case WM2200_DSP1AUX3MIX_INPUT_1_SOURCE:
case WM2200_DSP1AUX4MIX_INPUT_1_SOURCE:
case WM2200_DSP1AUX5MIX_INPUT_1_SOURCE:
case WM2200_DSP1AUX6MIX_INPUT_1_SOURCE:
case WM2200_DSP2LMIX_INPUT_1_SOURCE:
case WM2200_DSP2LMIX_INPUT_1_VOLUME:
case WM2200_DSP2LMIX_INPUT_2_SOURCE:
case WM2200_DSP2LMIX_INPUT_2_VOLUME:
case WM2200_DSP2LMIX_INPUT_3_SOURCE:
case WM2200_DSP2LMIX_INPUT_3_VOLUME:
case WM2200_DSP2LMIX_INPUT_4_SOURCE:
case WM2200_DSP2LMIX_INPUT_4_VOLUME:
case WM2200_DSP2RMIX_INPUT_1_SOURCE:
case WM2200_DSP2RMIX_INPUT_1_VOLUME:
case WM2200_DSP2RMIX_INPUT_2_SOURCE:
case WM2200_DSP2RMIX_INPUT_2_VOLUME:
case WM2200_DSP2RMIX_INPUT_3_SOURCE:
case WM2200_DSP2RMIX_INPUT_3_VOLUME:
case WM2200_DSP2RMIX_INPUT_4_SOURCE:
case WM2200_DSP2RMIX_INPUT_4_VOLUME:
case WM2200_DSP2AUX1MIX_INPUT_1_SOURCE:
case WM2200_DSP2AUX2MIX_INPUT_1_SOURCE:
case WM2200_DSP2AUX3MIX_INPUT_1_SOURCE:
case WM2200_DSP2AUX4MIX_INPUT_1_SOURCE:
case WM2200_DSP2AUX5MIX_INPUT_1_SOURCE:
case WM2200_DSP2AUX6MIX_INPUT_1_SOURCE:
case WM2200_GPIO_CTRL_1:
case WM2200_GPIO_CTRL_2:
case WM2200_GPIO_CTRL_3:
case WM2200_GPIO_CTRL_4:
case WM2200_ADPS1_IRQ0:
case WM2200_ADPS1_IRQ1:
case WM2200_MISC_PAD_CTRL_1:
case WM2200_INTERRUPT_STATUS_1:
case WM2200_INTERRUPT_STATUS_1_MASK:
case WM2200_INTERRUPT_STATUS_2:
case WM2200_INTERRUPT_RAW_STATUS_2:
case WM2200_INTERRUPT_STATUS_2_MASK:
case WM2200_INTERRUPT_CONTROL:
case WM2200_EQL_1:
case WM2200_EQL_2:
case WM2200_EQL_3:
case WM2200_EQL_4:
case WM2200_EQL_5:
case WM2200_EQL_6:
case WM2200_EQL_7:
case WM2200_EQL_8:
case WM2200_EQL_9:
case WM2200_EQL_10:
case WM2200_EQL_11:
case WM2200_EQL_12:
case WM2200_EQL_13:
case WM2200_EQL_14:
case WM2200_EQL_15:
case WM2200_EQL_16:
case WM2200_EQL_17:
case WM2200_EQL_18:
case WM2200_EQL_19:
case WM2200_EQL_20:
case WM2200_EQR_1:
case WM2200_EQR_2:
case WM2200_EQR_3:
case WM2200_EQR_4:
case WM2200_EQR_5:
case WM2200_EQR_6:
case WM2200_EQR_7:
case WM2200_EQR_8:
case WM2200_EQR_9:
case WM2200_EQR_10:
case WM2200_EQR_11:
case WM2200_EQR_12:
case WM2200_EQR_13:
case WM2200_EQR_14:
case WM2200_EQR_15:
case WM2200_EQR_16:
case WM2200_EQR_17:
case WM2200_EQR_18:
case WM2200_EQR_19:
case WM2200_EQR_20:
case WM2200_HPLPF1_1:
case WM2200_HPLPF1_2:
case WM2200_HPLPF2_1:
case WM2200_HPLPF2_2:
case WM2200_DSP1_CONTROL_1:
case WM2200_DSP1_CONTROL_2:
case WM2200_DSP1_CONTROL_3:
case WM2200_DSP1_CONTROL_4:
case WM2200_DSP1_CONTROL_5:
case WM2200_DSP1_CONTROL_6:
case WM2200_DSP1_CONTROL_7:
case WM2200_DSP1_CONTROL_8:
case WM2200_DSP1_CONTROL_9:
case WM2200_DSP1_CONTROL_10:
case WM2200_DSP1_CONTROL_11:
case WM2200_DSP1_CONTROL_12:
case WM2200_DSP1_CONTROL_13:
case WM2200_DSP1_CONTROL_14:
case WM2200_DSP1_CONTROL_15:
case WM2200_DSP1_CONTROL_16:
case WM2200_DSP1_CONTROL_17:
case WM2200_DSP1_CONTROL_18:
case WM2200_DSP1_CONTROL_19:
case WM2200_DSP1_CONTROL_20:
case WM2200_DSP1_CONTROL_21:
case WM2200_DSP1_CONTROL_22:
case WM2200_DSP1_CONTROL_23:
case WM2200_DSP1_CONTROL_24:
case WM2200_DSP1_CONTROL_25:
case WM2200_DSP1_CONTROL_26:
case WM2200_DSP1_CONTROL_27:
case WM2200_DSP1_CONTROL_28:
case WM2200_DSP1_CONTROL_29:
case WM2200_DSP1_CONTROL_30:
case WM2200_DSP1_CONTROL_31:
case WM2200_DSP2_CONTROL_1:
case WM2200_DSP2_CONTROL_2:
case WM2200_DSP2_CONTROL_3:
case WM2200_DSP2_CONTROL_4:
case WM2200_DSP2_CONTROL_5:
case WM2200_DSP2_CONTROL_6:
case WM2200_DSP2_CONTROL_7:
case WM2200_DSP2_CONTROL_8:
case WM2200_DSP2_CONTROL_9:
case WM2200_DSP2_CONTROL_10:
case WM2200_DSP2_CONTROL_11:
case WM2200_DSP2_CONTROL_12:
case WM2200_DSP2_CONTROL_13:
case WM2200_DSP2_CONTROL_14:
case WM2200_DSP2_CONTROL_15:
case WM2200_DSP2_CONTROL_16:
case WM2200_DSP2_CONTROL_17:
case WM2200_DSP2_CONTROL_18:
case WM2200_DSP2_CONTROL_19:
case WM2200_DSP2_CONTROL_20:
case WM2200_DSP2_CONTROL_21:
case WM2200_DSP2_CONTROL_22:
case WM2200_DSP2_CONTROL_23:
case WM2200_DSP2_CONTROL_24:
case WM2200_DSP2_CONTROL_25:
case WM2200_DSP2_CONTROL_26:
case WM2200_DSP2_CONTROL_27:
case WM2200_DSP2_CONTROL_28:
case WM2200_DSP2_CONTROL_29:
case WM2200_DSP2_CONTROL_30:
case WM2200_DSP2_CONTROL_31:
return true;
default:
return false;
}
}
static const struct reg_sequence wm2200_reva_patch[] = {
{ 0x07, 0x0003 },
{ 0x102, 0x0200 },
{ 0x203, 0x0084 },
{ 0x201, 0x83FF },
{ 0x20C, 0x0062 },
{ 0x20D, 0x0062 },
{ 0x207, 0x2002 },
{ 0x208, 0x20C0 },
{ 0x21D, 0x01C0 },
{ 0x50A, 0x0001 },
{ 0x50B, 0x0002 },
{ 0x50C, 0x0003 },
{ 0x50D, 0x0004 },
{ 0x50E, 0x0005 },
{ 0x510, 0x0001 },
{ 0x511, 0x0002 },
{ 0x512, 0x0003 },
{ 0x513, 0x0004 },
{ 0x514, 0x0005 },
{ 0x515, 0x0000 },
{ 0x201, 0x8084 },
{ 0x202, 0xBBDE },
{ 0x203, 0x00EC },
{ 0x500, 0x8000 },
{ 0x507, 0x1820 },
{ 0x508, 0x1820 },
{ 0x505, 0x0300 },
{ 0x506, 0x0300 },
{ 0x302, 0x2280 },
{ 0x303, 0x0080 },
{ 0x304, 0x2280 },
{ 0x305, 0x0080 },
{ 0x306, 0x2280 },
{ 0x307, 0x0080 },
{ 0x401, 0x0080 },
{ 0x402, 0x0080 },
{ 0x417, 0x3069 },
{ 0x900, 0x6318 },
{ 0x901, 0x6300 },
{ 0x902, 0x0FC8 },
{ 0x903, 0x03FE },
{ 0x904, 0x00E0 },
{ 0x905, 0x1EC4 },
{ 0x906, 0xF136 },
{ 0x907, 0x0409 },
{ 0x908, 0x04CC },
{ 0x909, 0x1C9B },
{ 0x90A, 0xF337 },
{ 0x90B, 0x040B },
{ 0x90C, 0x0CBB },
{ 0x90D, 0x16F8 },
{ 0x90E, 0xF7D9 },
{ 0x90F, 0x040A },
{ 0x910, 0x1F14 },
{ 0x911, 0x058C },
{ 0x912, 0x0563 },
{ 0x913, 0x4000 },
{ 0x916, 0x6318 },
{ 0x917, 0x6300 },
{ 0x918, 0x0FC8 },
{ 0x919, 0x03FE },
{ 0x91A, 0x00E0 },
{ 0x91B, 0x1EC4 },
{ 0x91C, 0xF136 },
{ 0x91D, 0x0409 },
{ 0x91E, 0x04CC },
{ 0x91F, 0x1C9B },
{ 0x920, 0xF337 },
{ 0x921, 0x040B },
{ 0x922, 0x0CBB },
{ 0x923, 0x16F8 },
{ 0x924, 0xF7D9 },
{ 0x925, 0x040A },
{ 0x926, 0x1F14 },
{ 0x927, 0x058C },
{ 0x928, 0x0563 },
{ 0x929, 0x4000 },
{ 0x709, 0x2000 },
{ 0x207, 0x200E },
{ 0x208, 0x20D4 },
{ 0x20A, 0x0080 },
{ 0x07, 0x0000 },
};
static int wm2200_reset(struct wm2200_priv *wm2200)
{
if (wm2200->pdata.reset) {
gpio_set_value_cansleep(wm2200->pdata.reset, 0);
gpio_set_value_cansleep(wm2200->pdata.reset, 1);
return 0;
} else {
return regmap_write(wm2200->regmap, WM2200_SOFTWARE_RESET,
0x2200);
}
}
static DECLARE_TLV_DB_SCALE(in_tlv, -6300, 100, 0);
static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0);
static DECLARE_TLV_DB_SCALE(out_tlv, -6400, 100, 0);
static const char * const wm2200_mixer_texts[] = {
"None",
"Tone Generator",
"AEC Loopback",
"IN1L",
"IN1R",
"IN2L",
"IN2R",
"IN3L",
"IN3R",
"AIF1RX1",
"AIF1RX2",
"AIF1RX3",
"AIF1RX4",
"AIF1RX5",
"AIF1RX6",
"EQL",
"EQR",
"LHPF1",
"LHPF2",
"DSP1.1",
"DSP1.2",
"DSP1.3",
"DSP1.4",
"DSP1.5",
"DSP1.6",
"DSP2.1",
"DSP2.2",
"DSP2.3",
"DSP2.4",
"DSP2.5",
"DSP2.6",
};
static unsigned int wm2200_mixer_values[] = {
0x00,
0x04, /* Tone */
0x08, /* AEC */
0x10, /* Input */
0x11,
0x12,
0x13,
0x14,
0x15,
0x20, /* AIF */
0x21,
0x22,
0x23,
0x24,
0x25,
0x50, /* EQ */
0x51,
0x60, /* LHPF1 */
0x61, /* LHPF2 */
0x68, /* DSP1 */
0x69,
0x6a,
0x6b,
0x6c,
0x6d,
0x70, /* DSP2 */
0x71,
0x72,
0x73,
0x74,
0x75,
};
#define WM2200_MIXER_CONTROLS(name, base) \
SOC_SINGLE_TLV(name " Input 1 Volume", base + 1 , \
WM2200_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
SOC_SINGLE_TLV(name " Input 2 Volume", base + 3 , \
WM2200_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
SOC_SINGLE_TLV(name " Input 3 Volume", base + 5 , \
WM2200_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
SOC_SINGLE_TLV(name " Input 4 Volume", base + 7 , \
WM2200_MIXER_VOL_SHIFT, 80, 0, mixer_tlv)
#define WM2200_MUX_ENUM_DECL(name, reg) \
SOC_VALUE_ENUM_SINGLE_DECL(name, reg, 0, 0xff, \
wm2200_mixer_texts, wm2200_mixer_values)
#define WM2200_MUX_CTL_DECL(name) \
const struct snd_kcontrol_new name##_mux = \
SOC_DAPM_ENUM("Route", name##_enum)
#define WM2200_MIXER_ENUMS(name, base_reg) \
static WM2200_MUX_ENUM_DECL(name##_in1_enum, base_reg); \
static WM2200_MUX_ENUM_DECL(name##_in2_enum, base_reg + 2); \
static WM2200_MUX_ENUM_DECL(name##_in3_enum, base_reg + 4); \
static WM2200_MUX_ENUM_DECL(name##_in4_enum, base_reg + 6); \
static WM2200_MUX_CTL_DECL(name##_in1); \
static WM2200_MUX_CTL_DECL(name##_in2); \
static WM2200_MUX_CTL_DECL(name##_in3); \
static WM2200_MUX_CTL_DECL(name##_in4)
#define WM2200_DSP_ENUMS(name, base_reg) \
static WM2200_MUX_ENUM_DECL(name##_aux1_enum, base_reg); \
static WM2200_MUX_ENUM_DECL(name##_aux2_enum, base_reg + 1); \
static WM2200_MUX_ENUM_DECL(name##_aux3_enum, base_reg + 2); \
static WM2200_MUX_ENUM_DECL(name##_aux4_enum, base_reg + 3); \
static WM2200_MUX_ENUM_DECL(name##_aux5_enum, base_reg + 4); \
static WM2200_MUX_ENUM_DECL(name##_aux6_enum, base_reg + 5); \
static WM2200_MUX_CTL_DECL(name##_aux1); \
static WM2200_MUX_CTL_DECL(name##_aux2); \
static WM2200_MUX_CTL_DECL(name##_aux3); \
static WM2200_MUX_CTL_DECL(name##_aux4); \
static WM2200_MUX_CTL_DECL(name##_aux5); \
static WM2200_MUX_CTL_DECL(name##_aux6);
static const char *wm2200_rxanc_input_sel_texts[] = {
"None", "IN1", "IN2", "IN3",
};
static SOC_ENUM_SINGLE_DECL(wm2200_rxanc_input_sel,
WM2200_RXANC_SRC,
WM2200_IN_RXANC_SEL_SHIFT,
wm2200_rxanc_input_sel_texts);
static const struct snd_kcontrol_new wm2200_snd_controls[] = {
SOC_SINGLE("IN1 High Performance Switch", WM2200_IN1L_CONTROL,
WM2200_IN1_OSR_SHIFT, 1, 0),
SOC_SINGLE("IN2 High Performance Switch", WM2200_IN2L_CONTROL,
WM2200_IN2_OSR_SHIFT, 1, 0),
SOC_SINGLE("IN3 High Performance Switch", WM2200_IN3L_CONTROL,
WM2200_IN3_OSR_SHIFT, 1, 0),
SOC_DOUBLE_R_TLV("IN1 Volume", WM2200_IN1L_CONTROL, WM2200_IN1R_CONTROL,
WM2200_IN1L_PGA_VOL_SHIFT, 0x5f, 0, in_tlv),
SOC_DOUBLE_R_TLV("IN2 Volume", WM2200_IN2L_CONTROL, WM2200_IN2R_CONTROL,
WM2200_IN2L_PGA_VOL_SHIFT, 0x5f, 0, in_tlv),
SOC_DOUBLE_R_TLV("IN3 Volume", WM2200_IN3L_CONTROL, WM2200_IN3R_CONTROL,
WM2200_IN3L_PGA_VOL_SHIFT, 0x5f, 0, in_tlv),
SOC_DOUBLE_R("IN1 Digital Switch", WM2200_ADC_DIGITAL_VOLUME_1L,
WM2200_ADC_DIGITAL_VOLUME_1R, WM2200_IN1L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R("IN2 Digital Switch", WM2200_ADC_DIGITAL_VOLUME_2L,
WM2200_ADC_DIGITAL_VOLUME_2R, WM2200_IN2L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R("IN3 Digital Switch", WM2200_ADC_DIGITAL_VOLUME_3L,
WM2200_ADC_DIGITAL_VOLUME_3R, WM2200_IN3L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R_TLV("IN1 Digital Volume", WM2200_ADC_DIGITAL_VOLUME_1L,
WM2200_ADC_DIGITAL_VOLUME_1R, WM2200_IN1L_DIG_VOL_SHIFT,
0xbf, 0, digital_tlv),
SOC_DOUBLE_R_TLV("IN2 Digital Volume", WM2200_ADC_DIGITAL_VOLUME_2L,
WM2200_ADC_DIGITAL_VOLUME_2R, WM2200_IN2L_DIG_VOL_SHIFT,
0xbf, 0, digital_tlv),
SOC_DOUBLE_R_TLV("IN3 Digital Volume", WM2200_ADC_DIGITAL_VOLUME_3L,
WM2200_ADC_DIGITAL_VOLUME_3R, WM2200_IN3L_DIG_VOL_SHIFT,
0xbf, 0, digital_tlv),
SND_SOC_BYTES_MASK("EQL Coefficients", WM2200_EQL_1, 20, WM2200_EQL_ENA),
SND_SOC_BYTES_MASK("EQR Coefficients", WM2200_EQR_1, 20, WM2200_EQR_ENA),
SND_SOC_BYTES("LHPF1 Coefficients", WM2200_HPLPF1_2, 1),
SND_SOC_BYTES("LHPF2 Coefficients", WM2200_HPLPF2_2, 1),
SOC_SINGLE("OUT1 High Performance Switch", WM2200_DAC_DIGITAL_VOLUME_1L,
WM2200_OUT1_OSR_SHIFT, 1, 0),
SOC_SINGLE("OUT2 High Performance Switch", WM2200_DAC_DIGITAL_VOLUME_2L,
WM2200_OUT2_OSR_SHIFT, 1, 0),
SOC_DOUBLE_R("OUT1 Digital Switch", WM2200_DAC_DIGITAL_VOLUME_1L,
WM2200_DAC_DIGITAL_VOLUME_1R, WM2200_OUT1L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R_TLV("OUT1 Digital Volume", WM2200_DAC_DIGITAL_VOLUME_1L,
WM2200_DAC_DIGITAL_VOLUME_1R, WM2200_OUT1L_VOL_SHIFT, 0x9f, 0,
digital_tlv),
SOC_DOUBLE_R_TLV("OUT1 Volume", WM2200_DAC_VOLUME_LIMIT_1L,
WM2200_DAC_VOLUME_LIMIT_1R, WM2200_OUT1L_PGA_VOL_SHIFT,
0x46, 0, out_tlv),
SOC_DOUBLE_R("OUT2 Digital Switch", WM2200_DAC_DIGITAL_VOLUME_2L,
WM2200_DAC_DIGITAL_VOLUME_2R, WM2200_OUT2L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R_TLV("OUT2 Digital Volume", WM2200_DAC_DIGITAL_VOLUME_2L,
WM2200_DAC_DIGITAL_VOLUME_2R, WM2200_OUT2L_VOL_SHIFT, 0x9f, 0,
digital_tlv),
SOC_DOUBLE("OUT2 Switch", WM2200_PDM_1, WM2200_SPK1L_MUTE_SHIFT,
WM2200_SPK1R_MUTE_SHIFT, 1, 1),
SOC_ENUM("RxANC Src", wm2200_rxanc_input_sel),
WM_ADSP_FW_CONTROL("DSP1", 0),
WM_ADSP_FW_CONTROL("DSP2", 1),
};
WM2200_MIXER_ENUMS(OUT1L, WM2200_OUT1LMIX_INPUT_1_SOURCE);
WM2200_MIXER_ENUMS(OUT1R, WM2200_OUT1RMIX_INPUT_1_SOURCE);
WM2200_MIXER_ENUMS(OUT2L, WM2200_OUT2LMIX_INPUT_1_SOURCE);
WM2200_MIXER_ENUMS(OUT2R, WM2200_OUT2RMIX_INPUT_1_SOURCE);
WM2200_MIXER_ENUMS(AIF1TX1, WM2200_AIF1TX1MIX_INPUT_1_SOURCE);
WM2200_MIXER_ENUMS(AIF1TX2, WM2200_AIF1TX2MIX_INPUT_1_SOURCE);
WM2200_MIXER_ENUMS(AIF1TX3, WM2200_AIF1TX3MIX_INPUT_1_SOURCE);
WM2200_MIXER_ENUMS(AIF1TX4, WM2200_AIF1TX4MIX_INPUT_1_SOURCE);
WM2200_MIXER_ENUMS(AIF1TX5, WM2200_AIF1TX5MIX_INPUT_1_SOURCE);
WM2200_MIXER_ENUMS(AIF1TX6, WM2200_AIF1TX6MIX_INPUT_1_SOURCE);
WM2200_MIXER_ENUMS(EQL, WM2200_EQLMIX_INPUT_1_SOURCE);
WM2200_MIXER_ENUMS(EQR, WM2200_EQRMIX_INPUT_1_SOURCE);
WM2200_MIXER_ENUMS(DSP1L, WM2200_DSP1LMIX_INPUT_1_SOURCE);
WM2200_MIXER_ENUMS(DSP1R, WM2200_DSP1RMIX_INPUT_1_SOURCE);
WM2200_MIXER_ENUMS(DSP2L, WM2200_DSP2LMIX_INPUT_1_SOURCE);
WM2200_MIXER_ENUMS(DSP2R, WM2200_DSP2RMIX_INPUT_1_SOURCE);
WM2200_DSP_ENUMS(DSP1, WM2200_DSP1AUX1MIX_INPUT_1_SOURCE);
WM2200_DSP_ENUMS(DSP2, WM2200_DSP2AUX1MIX_INPUT_1_SOURCE);
WM2200_MIXER_ENUMS(LHPF1, WM2200_LHPF1MIX_INPUT_1_SOURCE);
WM2200_MIXER_ENUMS(LHPF2, WM2200_LHPF2MIX_INPUT_1_SOURCE);
#define WM2200_MUX(name, ctrl) \
SND_SOC_DAPM_MUX(name, SND_SOC_NOPM, 0, 0, ctrl)
#define WM2200_MIXER_WIDGETS(name, name_str) \
WM2200_MUX(name_str " Input 1", &name##_in1_mux), \
WM2200_MUX(name_str " Input 2", &name##_in2_mux), \
WM2200_MUX(name_str " Input 3", &name##_in3_mux), \
WM2200_MUX(name_str " Input 4", &name##_in4_mux), \
SND_SOC_DAPM_MIXER(name_str " Mixer", SND_SOC_NOPM, 0, 0, NULL, 0)
#define WM2200_DSP_WIDGETS(name, name_str) \
WM2200_MIXER_WIDGETS(name##L, name_str "L"), \
WM2200_MIXER_WIDGETS(name##R, name_str "R"), \
WM2200_MUX(name_str " Aux 1", &name##_aux1_mux), \
WM2200_MUX(name_str " Aux 2", &name##_aux2_mux), \
WM2200_MUX(name_str " Aux 3", &name##_aux3_mux), \
WM2200_MUX(name_str " Aux 4", &name##_aux4_mux), \
WM2200_MUX(name_str " Aux 5", &name##_aux5_mux), \
WM2200_MUX(name_str " Aux 6", &name##_aux6_mux)
#define WM2200_MIXER_INPUT_ROUTES(name) \
{ name, "Tone Generator", "Tone Generator" }, \
{ name, "AEC Loopback", "AEC Loopback" }, \
{ name, "IN1L", "IN1L PGA" }, \
{ name, "IN1R", "IN1R PGA" }, \
{ name, "IN2L", "IN2L PGA" }, \
{ name, "IN2R", "IN2R PGA" }, \
{ name, "IN3L", "IN3L PGA" }, \
{ name, "IN3R", "IN3R PGA" }, \
{ name, "DSP1.1", "DSP1" }, \
{ name, "DSP1.2", "DSP1" }, \
{ name, "DSP1.3", "DSP1" }, \
{ name, "DSP1.4", "DSP1" }, \
{ name, "DSP1.5", "DSP1" }, \
{ name, "DSP1.6", "DSP1" }, \
{ name, "DSP2.1", "DSP2" }, \
{ name, "DSP2.2", "DSP2" }, \
{ name, "DSP2.3", "DSP2" }, \
{ name, "DSP2.4", "DSP2" }, \
{ name, "DSP2.5", "DSP2" }, \
{ name, "DSP2.6", "DSP2" }, \
{ name, "AIF1RX1", "AIF1RX1" }, \
{ name, "AIF1RX2", "AIF1RX2" }, \
{ name, "AIF1RX3", "AIF1RX3" }, \
{ name, "AIF1RX4", "AIF1RX4" }, \
{ name, "AIF1RX5", "AIF1RX5" }, \
{ name, "AIF1RX6", "AIF1RX6" }, \
{ name, "EQL", "EQL" }, \
{ name, "EQR", "EQR" }, \
{ name, "LHPF1", "LHPF1" }, \
{ name, "LHPF2", "LHPF2" }
#define WM2200_MIXER_ROUTES(widget, name) \
{ widget, NULL, name " Mixer" }, \
{ name " Mixer", NULL, name " Input 1" }, \
{ name " Mixer", NULL, name " Input 2" }, \
{ name " Mixer", NULL, name " Input 3" }, \
{ name " Mixer", NULL, name " Input 4" }, \
WM2200_MIXER_INPUT_ROUTES(name " Input 1"), \
WM2200_MIXER_INPUT_ROUTES(name " Input 2"), \
WM2200_MIXER_INPUT_ROUTES(name " Input 3"), \
WM2200_MIXER_INPUT_ROUTES(name " Input 4")
#define WM2200_DSP_AUX_ROUTES(name) \
{ name, NULL, name " Aux 1" }, \
{ name, NULL, name " Aux 2" }, \
{ name, NULL, name " Aux 3" }, \
{ name, NULL, name " Aux 4" }, \
{ name, NULL, name " Aux 5" }, \
{ name, NULL, name " Aux 6" }, \
WM2200_MIXER_INPUT_ROUTES(name " Aux 1"), \
WM2200_MIXER_INPUT_ROUTES(name " Aux 2"), \
WM2200_MIXER_INPUT_ROUTES(name " Aux 3"), \
WM2200_MIXER_INPUT_ROUTES(name " Aux 4"), \
WM2200_MIXER_INPUT_ROUTES(name " Aux 5"), \
WM2200_MIXER_INPUT_ROUTES(name " Aux 6")
static const char *wm2200_aec_loopback_texts[] = {
"OUT1L", "OUT1R", "OUT2L", "OUT2R",
};
static SOC_ENUM_SINGLE_DECL(wm2200_aec_loopback,
WM2200_DAC_AEC_CONTROL_1,
WM2200_AEC_LOOPBACK_SRC_SHIFT,
wm2200_aec_loopback_texts);
static const struct snd_kcontrol_new wm2200_aec_loopback_mux =
SOC_DAPM_ENUM("AEC Loopback", wm2200_aec_loopback);
static const struct snd_soc_dapm_widget wm2200_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("SYSCLK", WM2200_CLOCKING_3, WM2200_SYSCLK_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("CP1", WM2200_DM_CHARGE_PUMP_1, WM2200_CPDM_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("CP2", WM2200_MIC_CHARGE_PUMP_1, WM2200_CPMIC_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS1", WM2200_MIC_BIAS_CTRL_1, WM2200_MICB1_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS2", WM2200_MIC_BIAS_CTRL_2, WM2200_MICB2_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("AVDD", 20, 0),
SND_SOC_DAPM_INPUT("IN1L"),
SND_SOC_DAPM_INPUT("IN1R"),
SND_SOC_DAPM_INPUT("IN2L"),
SND_SOC_DAPM_INPUT("IN2R"),
SND_SOC_DAPM_INPUT("IN3L"),
SND_SOC_DAPM_INPUT("IN3R"),
SND_SOC_DAPM_SIGGEN("TONE"),
SND_SOC_DAPM_PGA("Tone Generator", WM2200_TONE_GENERATOR_1,
WM2200_TONE_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("IN1L PGA", WM2200_INPUT_ENABLES, WM2200_IN1L_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("IN1R PGA", WM2200_INPUT_ENABLES, WM2200_IN1R_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("IN2L PGA", WM2200_INPUT_ENABLES, WM2200_IN2L_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("IN2R PGA", WM2200_INPUT_ENABLES, WM2200_IN2R_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("IN3L PGA", WM2200_INPUT_ENABLES, WM2200_IN3L_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("IN3R PGA", WM2200_INPUT_ENABLES, WM2200_IN3R_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX1", "Playback", 0,
WM2200_AUDIO_IF_1_22, WM2200_AIF1RX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX2", "Playback", 1,
WM2200_AUDIO_IF_1_22, WM2200_AIF1RX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX3", "Playback", 2,
WM2200_AUDIO_IF_1_22, WM2200_AIF1RX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX4", "Playback", 3,
WM2200_AUDIO_IF_1_22, WM2200_AIF1RX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX5", "Playback", 4,
WM2200_AUDIO_IF_1_22, WM2200_AIF1RX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX6", "Playback", 5,
WM2200_AUDIO_IF_1_22, WM2200_AIF1RX6_ENA_SHIFT, 0),
SND_SOC_DAPM_PGA("EQL", WM2200_EQL_1, WM2200_EQL_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQR", WM2200_EQR_1, WM2200_EQR_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("LHPF1", WM2200_HPLPF1_1, WM2200_LHPF1_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF2", WM2200_HPLPF2_1, WM2200_LHPF2_ENA_SHIFT, 0,
NULL, 0),
WM_ADSP1("DSP1", 0),
WM_ADSP1("DSP2", 1),
SND_SOC_DAPM_AIF_OUT("AIF1TX1", "Capture", 0,
WM2200_AUDIO_IF_1_22, WM2200_AIF1TX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX2", "Capture", 1,
WM2200_AUDIO_IF_1_22, WM2200_AIF1TX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX3", "Capture", 2,
WM2200_AUDIO_IF_1_22, WM2200_AIF1TX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX4", "Capture", 3,
WM2200_AUDIO_IF_1_22, WM2200_AIF1TX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX5", "Capture", 4,
WM2200_AUDIO_IF_1_22, WM2200_AIF1TX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX6", "Capture", 5,
WM2200_AUDIO_IF_1_22, WM2200_AIF1TX6_ENA_SHIFT, 0),
SND_SOC_DAPM_MUX("AEC Loopback", WM2200_DAC_AEC_CONTROL_1,
WM2200_AEC_LOOPBACK_ENA_SHIFT, 0, &wm2200_aec_loopback_mux),
SND_SOC_DAPM_PGA_S("OUT1L", 0, WM2200_OUTPUT_ENABLES,
WM2200_OUT1L_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("OUT1R", 0, WM2200_OUTPUT_ENABLES,
WM2200_OUT1R_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("EPD_LP", 1, WM2200_EAR_PIECE_CTRL_1,
WM2200_EPD_LP_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("EPD_OUTP_LP", 1, WM2200_EAR_PIECE_CTRL_1,
WM2200_EPD_OUTP_LP_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("EPD_RMV_SHRT_LP", 1, WM2200_EAR_PIECE_CTRL_1,
WM2200_EPD_RMV_SHRT_LP_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("EPD_LN", 1, WM2200_EAR_PIECE_CTRL_1,
WM2200_EPD_LN_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("EPD_OUTP_LN", 1, WM2200_EAR_PIECE_CTRL_1,
WM2200_EPD_OUTP_LN_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("EPD_RMV_SHRT_LN", 1, WM2200_EAR_PIECE_CTRL_1,
WM2200_EPD_RMV_SHRT_LN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("EPD_RP", 1, WM2200_EAR_PIECE_CTRL_2,
WM2200_EPD_RP_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("EPD_OUTP_RP", 1, WM2200_EAR_PIECE_CTRL_2,
WM2200_EPD_OUTP_RP_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("EPD_RMV_SHRT_RP", 1, WM2200_EAR_PIECE_CTRL_2,
WM2200_EPD_RMV_SHRT_RP_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("EPD_RN", 1, WM2200_EAR_PIECE_CTRL_2,
WM2200_EPD_RN_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("EPD_OUTP_RN", 1, WM2200_EAR_PIECE_CTRL_2,
WM2200_EPD_OUTP_RN_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("EPD_RMV_SHRT_RN", 1, WM2200_EAR_PIECE_CTRL_2,
WM2200_EPD_RMV_SHRT_RN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("OUT2L", WM2200_OUTPUT_ENABLES, WM2200_OUT2L_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA("OUT2R", WM2200_OUTPUT_ENABLES, WM2200_OUT2R_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_OUTPUT("EPOUTLN"),
SND_SOC_DAPM_OUTPUT("EPOUTLP"),
SND_SOC_DAPM_OUTPUT("EPOUTRN"),
SND_SOC_DAPM_OUTPUT("EPOUTRP"),
SND_SOC_DAPM_OUTPUT("SPK"),
WM2200_MIXER_WIDGETS(EQL, "EQL"),
WM2200_MIXER_WIDGETS(EQR, "EQR"),
WM2200_MIXER_WIDGETS(LHPF1, "LHPF1"),
WM2200_MIXER_WIDGETS(LHPF2, "LHPF2"),
WM2200_DSP_WIDGETS(DSP1, "DSP1"),
WM2200_DSP_WIDGETS(DSP2, "DSP2"),
WM2200_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"),
WM2200_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"),
WM2200_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"),
WM2200_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"),
WM2200_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"),
WM2200_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"),
WM2200_MIXER_WIDGETS(OUT1L, "OUT1L"),
WM2200_MIXER_WIDGETS(OUT1R, "OUT1R"),
WM2200_MIXER_WIDGETS(OUT2L, "OUT2L"),
WM2200_MIXER_WIDGETS(OUT2R, "OUT2R"),
};
static const struct snd_soc_dapm_route wm2200_dapm_routes[] = {
/* Everything needs SYSCLK but only hook up things on the edge
* of the chip */
{ "IN1L", NULL, "SYSCLK" },
{ "IN1R", NULL, "SYSCLK" },
{ "IN2L", NULL, "SYSCLK" },
{ "IN2R", NULL, "SYSCLK" },
{ "IN3L", NULL, "SYSCLK" },
{ "IN3R", NULL, "SYSCLK" },
{ "OUT1L", NULL, "SYSCLK" },
{ "OUT1R", NULL, "SYSCLK" },
{ "OUT2L", NULL, "SYSCLK" },
{ "OUT2R", NULL, "SYSCLK" },
{ "AIF1RX1", NULL, "SYSCLK" },
{ "AIF1RX2", NULL, "SYSCLK" },
{ "AIF1RX3", NULL, "SYSCLK" },
{ "AIF1RX4", NULL, "SYSCLK" },
{ "AIF1RX5", NULL, "SYSCLK" },
{ "AIF1RX6", NULL, "SYSCLK" },
{ "AIF1TX1", NULL, "SYSCLK" },
{ "AIF1TX2", NULL, "SYSCLK" },
{ "AIF1TX3", NULL, "SYSCLK" },
{ "AIF1TX4", NULL, "SYSCLK" },
{ "AIF1TX5", NULL, "SYSCLK" },
{ "AIF1TX6", NULL, "SYSCLK" },
{ "IN1L", NULL, "AVDD" },
{ "IN1R", NULL, "AVDD" },
{ "IN2L", NULL, "AVDD" },
{ "IN2R", NULL, "AVDD" },
{ "IN3L", NULL, "AVDD" },
{ "IN3R", NULL, "AVDD" },
{ "OUT1L", NULL, "AVDD" },
{ "OUT1R", NULL, "AVDD" },
{ "IN1L PGA", NULL, "IN1L" },
{ "IN1R PGA", NULL, "IN1R" },
{ "IN2L PGA", NULL, "IN2L" },
{ "IN2R PGA", NULL, "IN2R" },
{ "IN3L PGA", NULL, "IN3L" },
{ "IN3R PGA", NULL, "IN3R" },
{ "Tone Generator", NULL, "TONE" },
{ "CP2", NULL, "CPVDD" },
{ "MICBIAS1", NULL, "CP2" },
{ "MICBIAS2", NULL, "CP2" },
{ "CP1", NULL, "CPVDD" },
{ "EPD_LN", NULL, "CP1" },
{ "EPD_LP", NULL, "CP1" },
{ "EPD_RN", NULL, "CP1" },
{ "EPD_RP", NULL, "CP1" },
{ "EPD_LP", NULL, "OUT1L" },
{ "EPD_OUTP_LP", NULL, "EPD_LP" },
{ "EPD_RMV_SHRT_LP", NULL, "EPD_OUTP_LP" },
{ "EPOUTLP", NULL, "EPD_RMV_SHRT_LP" },
{ "EPD_LN", NULL, "OUT1L" },
{ "EPD_OUTP_LN", NULL, "EPD_LN" },
{ "EPD_RMV_SHRT_LN", NULL, "EPD_OUTP_LN" },
{ "EPOUTLN", NULL, "EPD_RMV_SHRT_LN" },
{ "EPD_RP", NULL, "OUT1R" },
{ "EPD_OUTP_RP", NULL, "EPD_RP" },
{ "EPD_RMV_SHRT_RP", NULL, "EPD_OUTP_RP" },
{ "EPOUTRP", NULL, "EPD_RMV_SHRT_RP" },
{ "EPD_RN", NULL, "OUT1R" },
{ "EPD_OUTP_RN", NULL, "EPD_RN" },
{ "EPD_RMV_SHRT_RN", NULL, "EPD_OUTP_RN" },
{ "EPOUTRN", NULL, "EPD_RMV_SHRT_RN" },
{ "SPK", NULL, "OUT2L" },
{ "SPK", NULL, "OUT2R" },
{ "AEC Loopback", "OUT1L", "OUT1L" },
{ "AEC Loopback", "OUT1R", "OUT1R" },
{ "AEC Loopback", "OUT2L", "OUT2L" },
{ "AEC Loopback", "OUT2R", "OUT2R" },
WM2200_MIXER_ROUTES("DSP1", "DSP1L"),
WM2200_MIXER_ROUTES("DSP1", "DSP1R"),
WM2200_MIXER_ROUTES("DSP2", "DSP2L"),
WM2200_MIXER_ROUTES("DSP2", "DSP2R"),
WM2200_DSP_AUX_ROUTES("DSP1"),
WM2200_DSP_AUX_ROUTES("DSP2"),
WM2200_MIXER_ROUTES("OUT1L", "OUT1L"),
WM2200_MIXER_ROUTES("OUT1R", "OUT1R"),
WM2200_MIXER_ROUTES("OUT2L", "OUT2L"),
WM2200_MIXER_ROUTES("OUT2R", "OUT2R"),
WM2200_MIXER_ROUTES("AIF1TX1", "AIF1TX1"),
WM2200_MIXER_ROUTES("AIF1TX2", "AIF1TX2"),
WM2200_MIXER_ROUTES("AIF1TX3", "AIF1TX3"),
WM2200_MIXER_ROUTES("AIF1TX4", "AIF1TX4"),
WM2200_MIXER_ROUTES("AIF1TX5", "AIF1TX5"),
WM2200_MIXER_ROUTES("AIF1TX6", "AIF1TX6"),
WM2200_MIXER_ROUTES("EQL", "EQL"),
WM2200_MIXER_ROUTES("EQR", "EQR"),
WM2200_MIXER_ROUTES("LHPF1", "LHPF1"),
WM2200_MIXER_ROUTES("LHPF2", "LHPF2"),
};
static int wm2200_probe(struct snd_soc_component *component)
{
struct wm2200_priv *wm2200 = snd_soc_component_get_drvdata(component);
wm2200->component = component;
return 0;
}
static int wm2200_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
int lrclk, bclk, fmt_val;
lrclk = 0;
bclk = 0;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
fmt_val = 0;
break;
case SND_SOC_DAIFMT_I2S:
fmt_val = 2;
break;
default:
dev_err(component->dev, "Unsupported DAI format %d\n",
fmt & SND_SOC_DAIFMT_FORMAT_MASK);
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
break;
case SND_SOC_DAIFMT_CBS_CFM:
lrclk |= WM2200_AIF1TX_LRCLK_MSTR;
break;
case SND_SOC_DAIFMT_CBM_CFS:
bclk |= WM2200_AIF1_BCLK_MSTR;
break;
case SND_SOC_DAIFMT_CBM_CFM:
lrclk |= WM2200_AIF1TX_LRCLK_MSTR;
bclk |= WM2200_AIF1_BCLK_MSTR;
break;
default:
dev_err(component->dev, "Unsupported master mode %d\n",
fmt & SND_SOC_DAIFMT_MASTER_MASK);
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
bclk |= WM2200_AIF1_BCLK_INV;
lrclk |= WM2200_AIF1TX_LRCLK_INV;
break;
case SND_SOC_DAIFMT_IB_NF:
bclk |= WM2200_AIF1_BCLK_INV;
break;
case SND_SOC_DAIFMT_NB_IF:
lrclk |= WM2200_AIF1TX_LRCLK_INV;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, WM2200_AUDIO_IF_1_1, WM2200_AIF1_BCLK_MSTR |
WM2200_AIF1_BCLK_INV, bclk);
snd_soc_component_update_bits(component, WM2200_AUDIO_IF_1_2,
WM2200_AIF1TX_LRCLK_MSTR | WM2200_AIF1TX_LRCLK_INV,
lrclk);
snd_soc_component_update_bits(component, WM2200_AUDIO_IF_1_3,
WM2200_AIF1TX_LRCLK_MSTR | WM2200_AIF1TX_LRCLK_INV,
lrclk);
snd_soc_component_update_bits(component, WM2200_AUDIO_IF_1_5,
WM2200_AIF1_FMT_MASK, fmt_val);
return 0;
}
static int wm2200_sr_code[] = {
0,
12000,
24000,
48000,
96000,
192000,
384000,
768000,
0,
11025,
22050,
44100,
88200,
176400,
352800,
705600,
4000,
8000,
16000,
32000,
64000,
128000,
256000,
512000,
};
#define WM2200_NUM_BCLK_RATES 12
static int wm2200_bclk_rates_dat[WM2200_NUM_BCLK_RATES] = {
6144000,
3072000,
2048000,
1536000,
768000,
512000,
384000,
256000,
192000,
128000,
96000,
64000,
};
static int wm2200_bclk_rates_cd[WM2200_NUM_BCLK_RATES] = {
5644800,
3763200,
2882400,
1881600,
1411200,
705600,
470400,
352800,
176400,
117600,
88200,
58800,
};
static int wm2200_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm2200_priv *wm2200 = snd_soc_component_get_drvdata(component);
int i, bclk, lrclk, wl, fl, sr_code;
int *bclk_rates;
/* Data sizes if not using TDM */
wl = params_width(params);
if (wl < 0)
return wl;
fl = snd_soc_params_to_frame_size(params);
if (fl < 0)
return fl;
dev_dbg(component->dev, "Word length %d bits, frame length %d bits\n",
wl, fl);
/* Target BCLK rate */
bclk = snd_soc_params_to_bclk(params);
if (bclk < 0)
return bclk;
if (!wm2200->sysclk) {
dev_err(component->dev, "SYSCLK has no rate set\n");
return -EINVAL;
}
for (i = 0; i < ARRAY_SIZE(wm2200_sr_code); i++)
if (wm2200_sr_code[i] == params_rate(params))
break;
if (i == ARRAY_SIZE(wm2200_sr_code)) {
dev_err(component->dev, "Unsupported sample rate: %dHz\n",
params_rate(params));
return -EINVAL;
}
sr_code = i;
dev_dbg(component->dev, "Target BCLK is %dHz, using %dHz SYSCLK\n",
bclk, wm2200->sysclk);
if (wm2200->sysclk % 4000)
bclk_rates = wm2200_bclk_rates_cd;
else
bclk_rates = wm2200_bclk_rates_dat;
for (i = 0; i < WM2200_NUM_BCLK_RATES; i++)
if (bclk_rates[i] >= bclk && (bclk_rates[i] % bclk == 0))
break;
if (i == WM2200_NUM_BCLK_RATES) {
dev_err(component->dev,
"No valid BCLK for %dHz found from %dHz SYSCLK\n",
bclk, wm2200->sysclk);
return -EINVAL;
}
bclk = i;
dev_dbg(component->dev, "Setting %dHz BCLK\n", bclk_rates[bclk]);
snd_soc_component_update_bits(component, WM2200_AUDIO_IF_1_1,
WM2200_AIF1_BCLK_DIV_MASK, bclk);
lrclk = bclk_rates[bclk] / params_rate(params);
dev_dbg(component->dev, "Setting %dHz LRCLK\n", bclk_rates[bclk] / lrclk);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
wm2200->symmetric_rates)
snd_soc_component_update_bits(component, WM2200_AUDIO_IF_1_7,
WM2200_AIF1RX_BCPF_MASK, lrclk);
else
snd_soc_component_update_bits(component, WM2200_AUDIO_IF_1_6,
WM2200_AIF1TX_BCPF_MASK, lrclk);
i = (wl << WM2200_AIF1TX_WL_SHIFT) | wl;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
snd_soc_component_update_bits(component, WM2200_AUDIO_IF_1_9,
WM2200_AIF1RX_WL_MASK |
WM2200_AIF1RX_SLOT_LEN_MASK, i);
else
snd_soc_component_update_bits(component, WM2200_AUDIO_IF_1_8,
WM2200_AIF1TX_WL_MASK |
WM2200_AIF1TX_SLOT_LEN_MASK, i);
snd_soc_component_update_bits(component, WM2200_CLOCKING_4,
WM2200_SAMPLE_RATE_1_MASK, sr_code);
return 0;
}
static int wm2200_set_sysclk(struct snd_soc_component *component, int clk_id,
int source, unsigned int freq, int dir)
{
struct wm2200_priv *wm2200 = snd_soc_component_get_drvdata(component);
int fval;
switch (clk_id) {
case WM2200_CLK_SYSCLK:
break;
default:
dev_err(component->dev, "Unknown clock %d\n", clk_id);
return -EINVAL;
}
switch (source) {
case WM2200_CLKSRC_MCLK1:
case WM2200_CLKSRC_MCLK2:
case WM2200_CLKSRC_FLL:
case WM2200_CLKSRC_BCLK1:
break;
default:
dev_err(component->dev, "Invalid source %d\n", source);
return -EINVAL;
}
switch (freq) {
case 22579200:
case 24576000:
fval = 2;
break;
default:
dev_err(component->dev, "Invalid clock rate: %d\n", freq);
return -EINVAL;
}
/* TODO: Check if MCLKs are in use and enable/disable pulls to
* match.
*/
snd_soc_component_update_bits(component, WM2200_CLOCKING_3, WM2200_SYSCLK_FREQ_MASK |
WM2200_SYSCLK_SRC_MASK,
fval << WM2200_SYSCLK_FREQ_SHIFT | source);
wm2200->sysclk = freq;
return 0;
}
struct _fll_div {
u16 fll_fratio;
u16 fll_outdiv;
u16 fll_refclk_div;
u16 n;
u16 theta;
u16 lambda;
};
static struct {
unsigned int min;
unsigned int max;
u16 fll_fratio;
int ratio;
} fll_fratios[] = {
{ 0, 64000, 4, 16 },
{ 64000, 128000, 3, 8 },
{ 128000, 256000, 2, 4 },
{ 256000, 1000000, 1, 2 },
{ 1000000, 13500000, 0, 1 },
};
static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
unsigned int Fout)
{
unsigned int target;
unsigned int div;
unsigned int fratio, gcd_fll;
int i;
/* Fref must be <=13.5MHz */
div = 1;
fll_div->fll_refclk_div = 0;
while ((Fref / div) > 13500000) {
div *= 2;
fll_div->fll_refclk_div++;
if (div > 8) {
pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
Fref);
return -EINVAL;
}
}
pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
/* Apply the division for our remaining calculations */
Fref /= div;
/* Fvco should be 90-100MHz; don't check the upper bound */
div = 2;
while (Fout * div < 90000000) {
div++;
if (div > 64) {
pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
Fout);
return -EINVAL;
}
}
target = Fout * div;
fll_div->fll_outdiv = div - 1;
pr_debug("FLL Fvco=%dHz\n", target);
/* Find an appropraite FLL_FRATIO and factor it out of the target */
for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
fll_div->fll_fratio = fll_fratios[i].fll_fratio;
fratio = fll_fratios[i].ratio;
break;
}
}
if (i == ARRAY_SIZE(fll_fratios)) {
pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
return -EINVAL;
}
fll_div->n = target / (fratio * Fref);
if (target % Fref == 0) {
fll_div->theta = 0;
fll_div->lambda = 0;
} else {
gcd_fll = gcd(target, fratio * Fref);
fll_div->theta = (target - (fll_div->n * fratio * Fref))
/ gcd_fll;
fll_div->lambda = (fratio * Fref) / gcd_fll;
}
pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
fll_div->n, fll_div->theta, fll_div->lambda);
pr_debug("FLL_FRATIO=%x(%d) FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
fll_div->fll_fratio, fratio, fll_div->fll_outdiv,
fll_div->fll_refclk_div);
return 0;
}
static int wm2200_set_fll(struct snd_soc_component *component, int fll_id, int source,
unsigned int Fref, unsigned int Fout)
{
struct i2c_client *i2c = to_i2c_client(component->dev);
struct wm2200_priv *wm2200 = snd_soc_component_get_drvdata(component);
struct _fll_div factors;
int ret, i, timeout;
unsigned long time_left;
if (!Fout) {
dev_dbg(component->dev, "FLL disabled");
if (wm2200->fll_fout)
pm_runtime_put(component->dev);
wm2200->fll_fout = 0;
snd_soc_component_update_bits(component, WM2200_FLL_CONTROL_1,
WM2200_FLL_ENA, 0);
return 0;
}
switch (source) {
case WM2200_FLL_SRC_MCLK1:
case WM2200_FLL_SRC_MCLK2:
case WM2200_FLL_SRC_BCLK:
break;
default:
dev_err(component->dev, "Invalid FLL source %d\n", source);
return -EINVAL;
}
ret = fll_factors(&factors, Fref, Fout);
if (ret < 0)
return ret;
/* Disable the FLL while we reconfigure */
snd_soc_component_update_bits(component, WM2200_FLL_CONTROL_1, WM2200_FLL_ENA, 0);
snd_soc_component_update_bits(component, WM2200_FLL_CONTROL_2,
WM2200_FLL_OUTDIV_MASK | WM2200_FLL_FRATIO_MASK,
(factors.fll_outdiv << WM2200_FLL_OUTDIV_SHIFT) |
factors.fll_fratio);
if (factors.theta) {
snd_soc_component_update_bits(component, WM2200_FLL_CONTROL_3,
WM2200_FLL_FRACN_ENA,
WM2200_FLL_FRACN_ENA);
snd_soc_component_update_bits(component, WM2200_FLL_EFS_2,
WM2200_FLL_EFS_ENA,
WM2200_FLL_EFS_ENA);
} else {
snd_soc_component_update_bits(component, WM2200_FLL_CONTROL_3,
WM2200_FLL_FRACN_ENA, 0);
snd_soc_component_update_bits(component, WM2200_FLL_EFS_2,
WM2200_FLL_EFS_ENA, 0);
}
snd_soc_component_update_bits(component, WM2200_FLL_CONTROL_4, WM2200_FLL_THETA_MASK,
factors.theta);
snd_soc_component_update_bits(component, WM2200_FLL_CONTROL_6, WM2200_FLL_N_MASK,
factors.n);
snd_soc_component_update_bits(component, WM2200_FLL_CONTROL_7,
WM2200_FLL_CLK_REF_DIV_MASK |
WM2200_FLL_CLK_REF_SRC_MASK,
(factors.fll_refclk_div
<< WM2200_FLL_CLK_REF_DIV_SHIFT) | source);
snd_soc_component_update_bits(component, WM2200_FLL_EFS_1,
WM2200_FLL_LAMBDA_MASK, factors.lambda);
/* Clear any pending completions */
try_wait_for_completion(&wm2200->fll_lock);
pm_runtime_get_sync(component->dev);
snd_soc_component_update_bits(component, WM2200_FLL_CONTROL_1,
WM2200_FLL_ENA, WM2200_FLL_ENA);
if (i2c->irq)
timeout = 2;
else
timeout = 50;
snd_soc_component_update_bits(component, WM2200_CLOCKING_3, WM2200_SYSCLK_ENA,
WM2200_SYSCLK_ENA);
/* Poll for the lock; will use the interrupt to exit quickly */
for (i = 0; i < timeout; i++) {
if (i2c->irq) {
time_left = wait_for_completion_timeout(
&wm2200->fll_lock,
msecs_to_jiffies(25));
if (time_left > 0)
break;
} else {
msleep(1);
}
ret = snd_soc_component_read(component,
WM2200_INTERRUPT_RAW_STATUS_2);
if (ret < 0) {
dev_err(component->dev,
"Failed to read FLL status: %d\n",
ret);
continue;
}
if (ret & WM2200_FLL_LOCK_STS)
break;
}
if (i == timeout) {
dev_err(component->dev, "FLL lock timed out\n");
pm_runtime_put(component->dev);
return -ETIMEDOUT;
}
wm2200->fll_src = source;
wm2200->fll_fref = Fref;
wm2200->fll_fout = Fout;
dev_dbg(component->dev, "FLL running %dHz->%dHz\n", Fref, Fout);
return 0;
}
static int wm2200_dai_probe(struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm2200_priv *wm2200 = snd_soc_component_get_drvdata(component);
unsigned int val = 0;
int ret;
ret = snd_soc_component_read(component, WM2200_GPIO_CTRL_1);
if (ret >= 0) {
if ((ret & WM2200_GP1_FN_MASK) != 0) {
wm2200->symmetric_rates = true;
val = WM2200_AIF1TX_LRCLK_SRC;
}
} else {
dev_err(component->dev, "Failed to read GPIO 1 config: %d\n", ret);
}
snd_soc_component_update_bits(component, WM2200_AUDIO_IF_1_2,
WM2200_AIF1TX_LRCLK_SRC, val);
return 0;
}
static const struct snd_soc_dai_ops wm2200_dai_ops = {
.probe = wm2200_dai_probe,
.set_fmt = wm2200_set_fmt,
.hw_params = wm2200_hw_params,
};
#define WM2200_RATES SNDRV_PCM_RATE_8000_48000
#define WM2200_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver wm2200_dai = {
.name = "wm2200",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = WM2200_RATES,
.formats = WM2200_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = WM2200_RATES,
.formats = WM2200_FORMATS,
},
.ops = &wm2200_dai_ops,
};
static const struct snd_soc_component_driver soc_component_wm2200 = {
.probe = wm2200_probe,
.set_sysclk = wm2200_set_sysclk,
.set_pll = wm2200_set_fll,
.controls = wm2200_snd_controls,
.num_controls = ARRAY_SIZE(wm2200_snd_controls),
.dapm_widgets = wm2200_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm2200_dapm_widgets),
.dapm_routes = wm2200_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(wm2200_dapm_routes),
.endianness = 1,
};
static irqreturn_t wm2200_irq(int irq, void *data)
{
struct wm2200_priv *wm2200 = data;
unsigned int val, mask;
int ret;
ret = regmap_read(wm2200->regmap, WM2200_INTERRUPT_STATUS_2, &val);
if (ret != 0) {
dev_err(wm2200->dev, "Failed to read IRQ status: %d\n", ret);
return IRQ_NONE;
}
ret = regmap_read(wm2200->regmap, WM2200_INTERRUPT_STATUS_2_MASK,
&mask);
if (ret != 0) {
dev_warn(wm2200->dev, "Failed to read IRQ mask: %d\n", ret);
mask = 0;
}
val &= ~mask;
if (val & WM2200_FLL_LOCK_EINT) {
dev_dbg(wm2200->dev, "FLL locked\n");
complete(&wm2200->fll_lock);
}
if (val) {
regmap_write(wm2200->regmap, WM2200_INTERRUPT_STATUS_2, val);
return IRQ_HANDLED;
} else {
return IRQ_NONE;
}
}
static const struct regmap_config wm2200_regmap = {
.reg_bits = 16,
.val_bits = 16,
.max_register = WM2200_MAX_REGISTER + (ARRAY_SIZE(wm2200_ranges) *
WM2200_DSP_SPACING),
.reg_defaults = wm2200_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm2200_reg_defaults),
.volatile_reg = wm2200_volatile_register,
.readable_reg = wm2200_readable_register,
.cache_type = REGCACHE_MAPLE,
.ranges = wm2200_ranges,
.num_ranges = ARRAY_SIZE(wm2200_ranges),
};
static const unsigned int wm2200_dig_vu[] = {
WM2200_DAC_DIGITAL_VOLUME_1L,
WM2200_DAC_DIGITAL_VOLUME_1R,
WM2200_DAC_DIGITAL_VOLUME_2L,
WM2200_DAC_DIGITAL_VOLUME_2R,
WM2200_ADC_DIGITAL_VOLUME_1L,
WM2200_ADC_DIGITAL_VOLUME_1R,
WM2200_ADC_DIGITAL_VOLUME_2L,
WM2200_ADC_DIGITAL_VOLUME_2R,
WM2200_ADC_DIGITAL_VOLUME_3L,
WM2200_ADC_DIGITAL_VOLUME_3R,
};
static const unsigned int wm2200_mic_ctrl_reg[] = {
WM2200_IN1L_CONTROL,
WM2200_IN2L_CONTROL,
WM2200_IN3L_CONTROL,
};
static int wm2200_i2c_probe(struct i2c_client *i2c)
{
struct wm2200_pdata *pdata = dev_get_platdata(&i2c->dev);
struct wm2200_priv *wm2200;
unsigned int reg;
int ret, i;
int val;
wm2200 = devm_kzalloc(&i2c->dev, sizeof(struct wm2200_priv),
GFP_KERNEL);
if (wm2200 == NULL)
return -ENOMEM;
wm2200->dev = &i2c->dev;
init_completion(&wm2200->fll_lock);
wm2200->regmap = devm_regmap_init_i2c(i2c, &wm2200_regmap);
if (IS_ERR(wm2200->regmap)) {
ret = PTR_ERR(wm2200->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
for (i = 0; i < 2; i++) {
wm2200->dsp[i].cs_dsp.type = WMFW_ADSP1;
wm2200->dsp[i].part = "wm2200";
wm2200->dsp[i].cs_dsp.num = i + 1;
wm2200->dsp[i].cs_dsp.dev = &i2c->dev;
wm2200->dsp[i].cs_dsp.regmap = wm2200->regmap;
wm2200->dsp[i].cs_dsp.sysclk_reg = WM2200_CLOCKING_3;
wm2200->dsp[i].cs_dsp.sysclk_mask = WM2200_SYSCLK_FREQ_MASK;
wm2200->dsp[i].cs_dsp.sysclk_shift = WM2200_SYSCLK_FREQ_SHIFT;
}
wm2200->dsp[0].cs_dsp.base = WM2200_DSP1_CONTROL_1;
wm2200->dsp[0].cs_dsp.mem = wm2200_dsp1_regions;
wm2200->dsp[0].cs_dsp.num_mems = ARRAY_SIZE(wm2200_dsp1_regions);
wm2200->dsp[1].cs_dsp.base = WM2200_DSP2_CONTROL_1;
wm2200->dsp[1].cs_dsp.mem = wm2200_dsp2_regions;
wm2200->dsp[1].cs_dsp.num_mems = ARRAY_SIZE(wm2200_dsp2_regions);
for (i = 0; i < ARRAY_SIZE(wm2200->dsp); i++)
wm_adsp1_init(&wm2200->dsp[i]);
if (pdata)
wm2200->pdata = *pdata;
i2c_set_clientdata(i2c, wm2200);
for (i = 0; i < ARRAY_SIZE(wm2200->core_supplies); i++)
wm2200->core_supplies[i].supply = wm2200_core_supply_names[i];
ret = devm_regulator_bulk_get(&i2c->dev,
ARRAY_SIZE(wm2200->core_supplies),
wm2200->core_supplies);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to request core supplies: %d\n",
ret);
return ret;
}
ret = regulator_bulk_enable(ARRAY_SIZE(wm2200->core_supplies),
wm2200->core_supplies);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to enable core supplies: %d\n",
ret);
return ret;
}
if (wm2200->pdata.ldo_ena) {
ret = devm_gpio_request_one(&i2c->dev, wm2200->pdata.ldo_ena,
GPIOF_OUT_INIT_HIGH,
"WM2200 LDOENA");
if (ret < 0) {
dev_err(&i2c->dev, "Failed to request LDOENA %d: %d\n",
wm2200->pdata.ldo_ena, ret);
goto err_enable;
}
msleep(2);
}
if (wm2200->pdata.reset) {
ret = devm_gpio_request_one(&i2c->dev, wm2200->pdata.reset,
GPIOF_OUT_INIT_HIGH,
"WM2200 /RESET");
if (ret < 0) {
dev_err(&i2c->dev, "Failed to request /RESET %d: %d\n",
wm2200->pdata.reset, ret);
goto err_ldo;
}
}
ret = regmap_read(wm2200->regmap, WM2200_SOFTWARE_RESET, ®);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
goto err_reset;
}
switch (reg) {
case 0x2200:
break;
default:
dev_err(&i2c->dev, "Device is not a WM2200, ID is %x\n", reg);
ret = -EINVAL;
goto err_reset;
}
ret = regmap_read(wm2200->regmap, WM2200_DEVICE_REVISION, ®);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to read revision register\n");
goto err_reset;
}
wm2200->rev = reg & WM2200_DEVICE_REVISION_MASK;
dev_info(&i2c->dev, "revision %c\n", wm2200->rev + 'A');
switch (wm2200->rev) {
case 0:
case 1:
ret = regmap_register_patch(wm2200->regmap, wm2200_reva_patch,
ARRAY_SIZE(wm2200_reva_patch));
if (ret != 0) {
dev_err(&i2c->dev, "Failed to register patch: %d\n",
ret);
}
break;
default:
break;
}
ret = wm2200_reset(wm2200);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to issue reset\n");
goto err_reset;
}
for (i = 0; i < ARRAY_SIZE(wm2200->pdata.gpio_defaults); i++) {
if (!wm2200->pdata.gpio_defaults[i])
continue;
regmap_write(wm2200->regmap, WM2200_GPIO_CTRL_1 + i,
wm2200->pdata.gpio_defaults[i]);
}
for (i = 0; i < ARRAY_SIZE(wm2200_dig_vu); i++)
regmap_update_bits(wm2200->regmap, wm2200_dig_vu[i],
WM2200_OUT_VU, WM2200_OUT_VU);
/* Assign slots 1-6 to channels 1-6 for both TX and RX */
for (i = 0; i < 6; i++) {
regmap_write(wm2200->regmap, WM2200_AUDIO_IF_1_10 + i, i);
regmap_write(wm2200->regmap, WM2200_AUDIO_IF_1_16 + i, i);
}
for (i = 0; i < WM2200_MAX_MICBIAS; i++) {
if (!wm2200->pdata.micbias[i].mb_lvl &&
!wm2200->pdata.micbias[i].bypass)
continue;
/* Apply default for bypass mode */
if (!wm2200->pdata.micbias[i].mb_lvl)
wm2200->pdata.micbias[i].mb_lvl
= WM2200_MBIAS_LVL_1V5;
val = (wm2200->pdata.micbias[i].mb_lvl -1)
<< WM2200_MICB1_LVL_SHIFT;
if (wm2200->pdata.micbias[i].discharge)
val |= WM2200_MICB1_DISCH;
if (wm2200->pdata.micbias[i].fast_start)
val |= WM2200_MICB1_RATE;
if (wm2200->pdata.micbias[i].bypass)
val |= WM2200_MICB1_MODE;
regmap_update_bits(wm2200->regmap,
WM2200_MIC_BIAS_CTRL_1 + i,
WM2200_MICB1_LVL_MASK |
WM2200_MICB1_DISCH |
WM2200_MICB1_MODE |
WM2200_MICB1_RATE, val);
}
for (i = 0; i < ARRAY_SIZE(wm2200->pdata.in_mode); i++) {
regmap_update_bits(wm2200->regmap, wm2200_mic_ctrl_reg[i],
WM2200_IN1_MODE_MASK |
WM2200_IN1_DMIC_SUP_MASK,
(wm2200->pdata.in_mode[i] <<
WM2200_IN1_MODE_SHIFT) |
(wm2200->pdata.dmic_sup[i] <<
WM2200_IN1_DMIC_SUP_SHIFT));
}
if (i2c->irq) {
ret = request_threaded_irq(i2c->irq, NULL, wm2200_irq,
IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
"wm2200", wm2200);
if (ret == 0)
regmap_update_bits(wm2200->regmap,
WM2200_INTERRUPT_STATUS_2_MASK,
WM2200_FLL_LOCK_EINT, 0);
else
dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n",
i2c->irq, ret);
}
pm_runtime_set_active(&i2c->dev);
pm_runtime_enable(&i2c->dev);
pm_request_idle(&i2c->dev);
ret = devm_snd_soc_register_component(&i2c->dev, &soc_component_wm2200,
&wm2200_dai, 1);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
goto err_pm_runtime;
}
return 0;
err_pm_runtime:
pm_runtime_disable(&i2c->dev);
if (i2c->irq)
free_irq(i2c->irq, wm2200);
err_reset:
if (wm2200->pdata.reset)
gpio_set_value_cansleep(wm2200->pdata.reset, 0);
err_ldo:
if (wm2200->pdata.ldo_ena)
gpio_set_value_cansleep(wm2200->pdata.ldo_ena, 0);
err_enable:
regulator_bulk_disable(ARRAY_SIZE(wm2200->core_supplies),
wm2200->core_supplies);
return ret;
}
static void wm2200_i2c_remove(struct i2c_client *i2c)
{
struct wm2200_priv *wm2200 = i2c_get_clientdata(i2c);
pm_runtime_disable(&i2c->dev);
if (i2c->irq)
free_irq(i2c->irq, wm2200);
if (wm2200->pdata.reset)
gpio_set_value_cansleep(wm2200->pdata.reset, 0);
if (wm2200->pdata.ldo_ena)
gpio_set_value_cansleep(wm2200->pdata.ldo_ena, 0);
regulator_bulk_disable(ARRAY_SIZE(wm2200->core_supplies),
wm2200->core_supplies);
}
#ifdef CONFIG_PM
static int wm2200_runtime_suspend(struct device *dev)
{
struct wm2200_priv *wm2200 = dev_get_drvdata(dev);
regcache_cache_only(wm2200->regmap, true);
regcache_mark_dirty(wm2200->regmap);
if (wm2200->pdata.ldo_ena)
gpio_set_value_cansleep(wm2200->pdata.ldo_ena, 0);
regulator_bulk_disable(ARRAY_SIZE(wm2200->core_supplies),
wm2200->core_supplies);
return 0;
}
static int wm2200_runtime_resume(struct device *dev)
{
struct wm2200_priv *wm2200 = dev_get_drvdata(dev);
int ret;
ret = regulator_bulk_enable(ARRAY_SIZE(wm2200->core_supplies),
wm2200->core_supplies);
if (ret != 0) {
dev_err(dev, "Failed to enable supplies: %d\n",
ret);
return ret;
}
if (wm2200->pdata.ldo_ena) {
gpio_set_value_cansleep(wm2200->pdata.ldo_ena, 1);
msleep(2);
}
regcache_cache_only(wm2200->regmap, false);
regcache_sync(wm2200->regmap);
return 0;
}
#endif
static const struct dev_pm_ops wm2200_pm = {
SET_RUNTIME_PM_OPS(wm2200_runtime_suspend, wm2200_runtime_resume,
NULL)
};
static const struct i2c_device_id wm2200_i2c_id[] = {
{ "wm2200", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm2200_i2c_id);
static struct i2c_driver wm2200_i2c_driver = {
.driver = {
.name = "wm2200",
.pm = &wm2200_pm,
},
.probe = wm2200_i2c_probe,
.remove = wm2200_i2c_remove,
.id_table = wm2200_i2c_id,
};
module_i2c_driver(wm2200_i2c_driver);
MODULE_DESCRIPTION("ASoC WM2200 driver");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm2200.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* CS4271 ASoC codec driver
*
* Copyright (c) 2010 Alexander Sverdlin <[email protected]>
*
* This driver support CS4271 codec being master or slave, working
* in control port mode, connected either via SPI or I2C.
* The data format accepted is I2S or left-justified.
* DAPM support not implemented.
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/regulator/consumer.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <sound/cs4271.h>
#include "cs4271.h"
#define CS4271_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE)
#define CS4271_PCM_RATES SNDRV_PCM_RATE_8000_192000
/*
* CS4271 registers
*/
#define CS4271_MODE1 0x01 /* Mode Control 1 */
#define CS4271_DACCTL 0x02 /* DAC Control */
#define CS4271_DACVOL 0x03 /* DAC Volume & Mixing Control */
#define CS4271_VOLA 0x04 /* DAC Channel A Volume Control */
#define CS4271_VOLB 0x05 /* DAC Channel B Volume Control */
#define CS4271_ADCCTL 0x06 /* ADC Control */
#define CS4271_MODE2 0x07 /* Mode Control 2 */
#define CS4271_CHIPID 0x08 /* Chip ID */
#define CS4271_FIRSTREG CS4271_MODE1
#define CS4271_LASTREG CS4271_MODE2
#define CS4271_NR_REGS ((CS4271_LASTREG & 0xFF) + 1)
/* Bit masks for the CS4271 registers */
#define CS4271_MODE1_MODE_MASK 0xC0
#define CS4271_MODE1_MODE_1X 0x00
#define CS4271_MODE1_MODE_2X 0x80
#define CS4271_MODE1_MODE_4X 0xC0
#define CS4271_MODE1_DIV_MASK 0x30
#define CS4271_MODE1_DIV_1 0x00
#define CS4271_MODE1_DIV_15 0x10
#define CS4271_MODE1_DIV_2 0x20
#define CS4271_MODE1_DIV_3 0x30
#define CS4271_MODE1_MASTER 0x08
#define CS4271_MODE1_DAC_DIF_MASK 0x07
#define CS4271_MODE1_DAC_DIF_LJ 0x00
#define CS4271_MODE1_DAC_DIF_I2S 0x01
#define CS4271_MODE1_DAC_DIF_RJ16 0x02
#define CS4271_MODE1_DAC_DIF_RJ24 0x03
#define CS4271_MODE1_DAC_DIF_RJ20 0x04
#define CS4271_MODE1_DAC_DIF_RJ18 0x05
#define CS4271_DACCTL_AMUTE 0x80
#define CS4271_DACCTL_IF_SLOW 0x40
#define CS4271_DACCTL_DEM_MASK 0x30
#define CS4271_DACCTL_DEM_DIS 0x00
#define CS4271_DACCTL_DEM_441 0x10
#define CS4271_DACCTL_DEM_48 0x20
#define CS4271_DACCTL_DEM_32 0x30
#define CS4271_DACCTL_SVRU 0x08
#define CS4271_DACCTL_SRD 0x04
#define CS4271_DACCTL_INVA 0x02
#define CS4271_DACCTL_INVB 0x01
#define CS4271_DACVOL_BEQUA 0x40
#define CS4271_DACVOL_SOFT 0x20
#define CS4271_DACVOL_ZEROC 0x10
#define CS4271_DACVOL_ATAPI_MASK 0x0F
#define CS4271_DACVOL_ATAPI_M_M 0x00
#define CS4271_DACVOL_ATAPI_M_BR 0x01
#define CS4271_DACVOL_ATAPI_M_BL 0x02
#define CS4271_DACVOL_ATAPI_M_BLR2 0x03
#define CS4271_DACVOL_ATAPI_AR_M 0x04
#define CS4271_DACVOL_ATAPI_AR_BR 0x05
#define CS4271_DACVOL_ATAPI_AR_BL 0x06
#define CS4271_DACVOL_ATAPI_AR_BLR2 0x07
#define CS4271_DACVOL_ATAPI_AL_M 0x08
#define CS4271_DACVOL_ATAPI_AL_BR 0x09
#define CS4271_DACVOL_ATAPI_AL_BL 0x0A
#define CS4271_DACVOL_ATAPI_AL_BLR2 0x0B
#define CS4271_DACVOL_ATAPI_ALR2_M 0x0C
#define CS4271_DACVOL_ATAPI_ALR2_BR 0x0D
#define CS4271_DACVOL_ATAPI_ALR2_BL 0x0E
#define CS4271_DACVOL_ATAPI_ALR2_BLR2 0x0F
#define CS4271_VOLA_MUTE 0x80
#define CS4271_VOLA_VOL_MASK 0x7F
#define CS4271_VOLB_MUTE 0x80
#define CS4271_VOLB_VOL_MASK 0x7F
#define CS4271_ADCCTL_DITHER16 0x20
#define CS4271_ADCCTL_ADC_DIF_MASK 0x10
#define CS4271_ADCCTL_ADC_DIF_LJ 0x00
#define CS4271_ADCCTL_ADC_DIF_I2S 0x10
#define CS4271_ADCCTL_MUTEA 0x08
#define CS4271_ADCCTL_MUTEB 0x04
#define CS4271_ADCCTL_HPFDA 0x02
#define CS4271_ADCCTL_HPFDB 0x01
#define CS4271_MODE2_LOOP 0x10
#define CS4271_MODE2_MUTECAEQUB 0x08
#define CS4271_MODE2_FREEZE 0x04
#define CS4271_MODE2_CPEN 0x02
#define CS4271_MODE2_PDN 0x01
#define CS4271_CHIPID_PART_MASK 0xF0
#define CS4271_CHIPID_REV_MASK 0x0F
/*
* Default CS4271 power-up configuration
* Array contains non-existing in hw register at address 0
* Array do not include Chip ID, as codec driver does not use
* registers read operations at all
*/
static const struct reg_default cs4271_reg_defaults[] = {
{ CS4271_MODE1, 0, },
{ CS4271_DACCTL, CS4271_DACCTL_AMUTE, },
{ CS4271_DACVOL, CS4271_DACVOL_SOFT | CS4271_DACVOL_ATAPI_AL_BR, },
{ CS4271_VOLA, 0, },
{ CS4271_VOLB, 0, },
{ CS4271_ADCCTL, 0, },
{ CS4271_MODE2, 0, },
};
static bool cs4271_volatile_reg(struct device *dev, unsigned int reg)
{
return reg == CS4271_CHIPID;
}
static const char * const supply_names[] = {
"vd", "vl", "va"
};
struct cs4271_private {
unsigned int mclk;
bool master;
bool deemph;
struct regmap *regmap;
/* Current sample rate for de-emphasis control */
int rate;
/* GPIO driving Reset pin, if any */
int gpio_nreset;
/* GPIO that disable serial bus, if any */
int gpio_disable;
/* enable soft reset workaround */
bool enable_soft_reset;
struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
};
static const struct snd_soc_dapm_widget cs4271_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("AINA"),
SND_SOC_DAPM_INPUT("AINB"),
SND_SOC_DAPM_OUTPUT("AOUTA+"),
SND_SOC_DAPM_OUTPUT("AOUTA-"),
SND_SOC_DAPM_OUTPUT("AOUTB+"),
SND_SOC_DAPM_OUTPUT("AOUTB-"),
};
static const struct snd_soc_dapm_route cs4271_dapm_routes[] = {
{ "Capture", NULL, "AINA" },
{ "Capture", NULL, "AINB" },
{ "AOUTA+", NULL, "Playback" },
{ "AOUTA-", NULL, "Playback" },
{ "AOUTB+", NULL, "Playback" },
{ "AOUTB-", NULL, "Playback" },
};
/*
* @freq is the desired MCLK rate
* MCLK rate should (c) be the sample rate, multiplied by one of the
* ratios listed in cs4271_mclk_fs_ratios table
*/
static int cs4271_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
cs4271->mclk = freq;
return 0;
}
static int cs4271_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int format)
{
struct snd_soc_component *component = codec_dai->component;
struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
unsigned int val = 0;
int ret;
switch (format & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
cs4271->master = false;
break;
case SND_SOC_DAIFMT_CBM_CFM:
cs4271->master = true;
val |= CS4271_MODE1_MASTER;
break;
default:
dev_err(component->dev, "Invalid DAI format\n");
return -EINVAL;
}
switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_LEFT_J:
val |= CS4271_MODE1_DAC_DIF_LJ;
ret = regmap_update_bits(cs4271->regmap, CS4271_ADCCTL,
CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_LJ);
if (ret < 0)
return ret;
break;
case SND_SOC_DAIFMT_I2S:
val |= CS4271_MODE1_DAC_DIF_I2S;
ret = regmap_update_bits(cs4271->regmap, CS4271_ADCCTL,
CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_I2S);
if (ret < 0)
return ret;
break;
default:
dev_err(component->dev, "Invalid DAI format\n");
return -EINVAL;
}
ret = regmap_update_bits(cs4271->regmap, CS4271_MODE1,
CS4271_MODE1_DAC_DIF_MASK | CS4271_MODE1_MASTER, val);
if (ret < 0)
return ret;
return 0;
}
static int cs4271_deemph[] = {0, 44100, 48000, 32000};
static int cs4271_set_deemph(struct snd_soc_component *component)
{
struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
int i, ret;
int val = CS4271_DACCTL_DEM_DIS;
if (cs4271->deemph) {
/* Find closest de-emphasis freq */
val = 1;
for (i = 2; i < ARRAY_SIZE(cs4271_deemph); i++)
if (abs(cs4271_deemph[i] - cs4271->rate) <
abs(cs4271_deemph[val] - cs4271->rate))
val = i;
val <<= 4;
}
ret = regmap_update_bits(cs4271->regmap, CS4271_DACCTL,
CS4271_DACCTL_DEM_MASK, val);
if (ret < 0)
return ret;
return 0;
}
static int cs4271_get_deemph(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = cs4271->deemph;
return 0;
}
static int cs4271_put_deemph(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
cs4271->deemph = ucontrol->value.integer.value[0];
return cs4271_set_deemph(component);
}
struct cs4271_clk_cfg {
bool master; /* codec mode */
u8 speed_mode; /* codec speed mode: 1x, 2x, 4x */
unsigned short ratio; /* MCLK / sample rate */
u8 ratio_mask; /* ratio bit mask for Master mode */
};
static struct cs4271_clk_cfg cs4271_clk_tab[] = {
{1, CS4271_MODE1_MODE_1X, 256, CS4271_MODE1_DIV_1},
{1, CS4271_MODE1_MODE_1X, 384, CS4271_MODE1_DIV_15},
{1, CS4271_MODE1_MODE_1X, 512, CS4271_MODE1_DIV_2},
{1, CS4271_MODE1_MODE_1X, 768, CS4271_MODE1_DIV_3},
{1, CS4271_MODE1_MODE_2X, 128, CS4271_MODE1_DIV_1},
{1, CS4271_MODE1_MODE_2X, 192, CS4271_MODE1_DIV_15},
{1, CS4271_MODE1_MODE_2X, 256, CS4271_MODE1_DIV_2},
{1, CS4271_MODE1_MODE_2X, 384, CS4271_MODE1_DIV_3},
{1, CS4271_MODE1_MODE_4X, 64, CS4271_MODE1_DIV_1},
{1, CS4271_MODE1_MODE_4X, 96, CS4271_MODE1_DIV_15},
{1, CS4271_MODE1_MODE_4X, 128, CS4271_MODE1_DIV_2},
{1, CS4271_MODE1_MODE_4X, 192, CS4271_MODE1_DIV_3},
{0, CS4271_MODE1_MODE_1X, 256, CS4271_MODE1_DIV_1},
{0, CS4271_MODE1_MODE_1X, 384, CS4271_MODE1_DIV_1},
{0, CS4271_MODE1_MODE_1X, 512, CS4271_MODE1_DIV_1},
{0, CS4271_MODE1_MODE_1X, 768, CS4271_MODE1_DIV_2},
{0, CS4271_MODE1_MODE_1X, 1024, CS4271_MODE1_DIV_2},
{0, CS4271_MODE1_MODE_2X, 128, CS4271_MODE1_DIV_1},
{0, CS4271_MODE1_MODE_2X, 192, CS4271_MODE1_DIV_1},
{0, CS4271_MODE1_MODE_2X, 256, CS4271_MODE1_DIV_1},
{0, CS4271_MODE1_MODE_2X, 384, CS4271_MODE1_DIV_2},
{0, CS4271_MODE1_MODE_2X, 512, CS4271_MODE1_DIV_2},
{0, CS4271_MODE1_MODE_4X, 64, CS4271_MODE1_DIV_1},
{0, CS4271_MODE1_MODE_4X, 96, CS4271_MODE1_DIV_1},
{0, CS4271_MODE1_MODE_4X, 128, CS4271_MODE1_DIV_1},
{0, CS4271_MODE1_MODE_4X, 192, CS4271_MODE1_DIV_2},
{0, CS4271_MODE1_MODE_4X, 256, CS4271_MODE1_DIV_2},
};
#define CS4271_NR_RATIOS ARRAY_SIZE(cs4271_clk_tab)
static int cs4271_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
int i, ret;
unsigned int ratio, val;
if (cs4271->enable_soft_reset) {
/*
* Put the codec in soft reset and back again in case it's not
* currently streaming data. This way of bringing the codec in
* sync to the current clocks is not explicitly documented in
* the data sheet, but it seems to work fine, and in contrast
* to a read hardware reset, we don't have to sync back all
* registers every time.
*/
if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK &&
!snd_soc_dai_stream_active(dai, SNDRV_PCM_STREAM_CAPTURE)) ||
(substream->stream == SNDRV_PCM_STREAM_CAPTURE &&
!snd_soc_dai_stream_active(dai, SNDRV_PCM_STREAM_PLAYBACK))) {
ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
CS4271_MODE2_PDN,
CS4271_MODE2_PDN);
if (ret < 0)
return ret;
ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
CS4271_MODE2_PDN, 0);
if (ret < 0)
return ret;
}
}
cs4271->rate = params_rate(params);
/* Configure DAC */
if (cs4271->rate < 50000)
val = CS4271_MODE1_MODE_1X;
else if (cs4271->rate < 100000)
val = CS4271_MODE1_MODE_2X;
else
val = CS4271_MODE1_MODE_4X;
ratio = cs4271->mclk / cs4271->rate;
for (i = 0; i < CS4271_NR_RATIOS; i++)
if ((cs4271_clk_tab[i].master == cs4271->master) &&
(cs4271_clk_tab[i].speed_mode == val) &&
(cs4271_clk_tab[i].ratio == ratio))
break;
if (i == CS4271_NR_RATIOS) {
dev_err(component->dev, "Invalid sample rate\n");
return -EINVAL;
}
val |= cs4271_clk_tab[i].ratio_mask;
ret = regmap_update_bits(cs4271->regmap, CS4271_MODE1,
CS4271_MODE1_MODE_MASK | CS4271_MODE1_DIV_MASK, val);
if (ret < 0)
return ret;
return cs4271_set_deemph(component);
}
static int cs4271_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
{
struct snd_soc_component *component = dai->component;
struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
int ret;
int val_a = 0;
int val_b = 0;
if (stream != SNDRV_PCM_STREAM_PLAYBACK)
return 0;
if (mute) {
val_a = CS4271_VOLA_MUTE;
val_b = CS4271_VOLB_MUTE;
}
ret = regmap_update_bits(cs4271->regmap, CS4271_VOLA,
CS4271_VOLA_MUTE, val_a);
if (ret < 0)
return ret;
ret = regmap_update_bits(cs4271->regmap, CS4271_VOLB,
CS4271_VOLB_MUTE, val_b);
if (ret < 0)
return ret;
return 0;
}
/* CS4271 controls */
static DECLARE_TLV_DB_SCALE(cs4271_dac_tlv, -12700, 100, 0);
static const struct snd_kcontrol_new cs4271_snd_controls[] = {
SOC_DOUBLE_R_TLV("Master Playback Volume", CS4271_VOLA, CS4271_VOLB,
0, 0x7F, 1, cs4271_dac_tlv),
SOC_SINGLE("Digital Loopback Switch", CS4271_MODE2, 4, 1, 0),
SOC_SINGLE("Soft Ramp Switch", CS4271_DACVOL, 5, 1, 0),
SOC_SINGLE("Zero Cross Switch", CS4271_DACVOL, 4, 1, 0),
SOC_SINGLE_BOOL_EXT("De-emphasis Switch", 0,
cs4271_get_deemph, cs4271_put_deemph),
SOC_SINGLE("Auto-Mute Switch", CS4271_DACCTL, 7, 1, 0),
SOC_SINGLE("Slow Roll Off Filter Switch", CS4271_DACCTL, 6, 1, 0),
SOC_SINGLE("Soft Volume Ramp-Up Switch", CS4271_DACCTL, 3, 1, 0),
SOC_SINGLE("Soft Ramp-Down Switch", CS4271_DACCTL, 2, 1, 0),
SOC_SINGLE("Left Channel Inversion Switch", CS4271_DACCTL, 1, 1, 0),
SOC_SINGLE("Right Channel Inversion Switch", CS4271_DACCTL, 0, 1, 0),
SOC_DOUBLE("Master Capture Switch", CS4271_ADCCTL, 3, 2, 1, 1),
SOC_SINGLE("Dither 16-Bit Data Switch", CS4271_ADCCTL, 5, 1, 0),
SOC_DOUBLE("High Pass Filter Switch", CS4271_ADCCTL, 1, 0, 1, 1),
SOC_DOUBLE_R("Master Playback Switch", CS4271_VOLA, CS4271_VOLB,
7, 1, 1),
};
static const struct snd_soc_dai_ops cs4271_dai_ops = {
.hw_params = cs4271_hw_params,
.set_sysclk = cs4271_set_dai_sysclk,
.set_fmt = cs4271_set_dai_fmt,
.mute_stream = cs4271_mute_stream,
};
static struct snd_soc_dai_driver cs4271_dai = {
.name = "cs4271-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = CS4271_PCM_RATES,
.formats = CS4271_PCM_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = CS4271_PCM_RATES,
.formats = CS4271_PCM_FORMATS,
},
.ops = &cs4271_dai_ops,
.symmetric_rate = 1,
};
static int cs4271_reset(struct snd_soc_component *component)
{
struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
if (gpio_is_valid(cs4271->gpio_nreset)) {
gpio_direction_output(cs4271->gpio_nreset, 0);
mdelay(1);
gpio_set_value(cs4271->gpio_nreset, 1);
mdelay(1);
}
return 0;
}
#ifdef CONFIG_PM
static int cs4271_soc_suspend(struct snd_soc_component *component)
{
int ret;
struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
/* Set power-down bit */
ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
CS4271_MODE2_PDN, CS4271_MODE2_PDN);
if (ret < 0)
return ret;
regcache_mark_dirty(cs4271->regmap);
regulator_bulk_disable(ARRAY_SIZE(cs4271->supplies), cs4271->supplies);
return 0;
}
static int cs4271_soc_resume(struct snd_soc_component *component)
{
int ret;
struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
ret = regulator_bulk_enable(ARRAY_SIZE(cs4271->supplies),
cs4271->supplies);
if (ret < 0) {
dev_err(component->dev, "Failed to enable regulators: %d\n", ret);
return ret;
}
/* Do a proper reset after power up */
cs4271_reset(component);
/* Restore codec state */
ret = regcache_sync(cs4271->regmap);
if (ret < 0)
return ret;
/* then disable the power-down bit */
ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
CS4271_MODE2_PDN, 0);
if (ret < 0)
return ret;
return 0;
}
#else
#define cs4271_soc_suspend NULL
#define cs4271_soc_resume NULL
#endif /* CONFIG_PM */
#ifdef CONFIG_OF
const struct of_device_id cs4271_dt_ids[] = {
{ .compatible = "cirrus,cs4271", },
{ }
};
MODULE_DEVICE_TABLE(of, cs4271_dt_ids);
EXPORT_SYMBOL_GPL(cs4271_dt_ids);
#endif
static int cs4271_component_probe(struct snd_soc_component *component)
{
struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
struct cs4271_platform_data *cs4271plat = component->dev->platform_data;
int ret;
bool amutec_eq_bmutec = false;
#ifdef CONFIG_OF
if (of_match_device(cs4271_dt_ids, component->dev)) {
if (of_get_property(component->dev->of_node,
"cirrus,amutec-eq-bmutec", NULL))
amutec_eq_bmutec = true;
if (of_get_property(component->dev->of_node,
"cirrus,enable-soft-reset", NULL))
cs4271->enable_soft_reset = true;
}
#endif
ret = regulator_bulk_enable(ARRAY_SIZE(cs4271->supplies),
cs4271->supplies);
if (ret < 0) {
dev_err(component->dev, "Failed to enable regulators: %d\n", ret);
return ret;
}
if (cs4271plat) {
amutec_eq_bmutec = cs4271plat->amutec_eq_bmutec;
cs4271->enable_soft_reset = cs4271plat->enable_soft_reset;
}
/* Reset codec */
cs4271_reset(component);
ret = regcache_sync(cs4271->regmap);
if (ret < 0)
return ret;
ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
CS4271_MODE2_PDN | CS4271_MODE2_CPEN,
CS4271_MODE2_PDN | CS4271_MODE2_CPEN);
if (ret < 0)
return ret;
ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
CS4271_MODE2_PDN, 0);
if (ret < 0)
return ret;
/* Power-up sequence requires 85 uS */
udelay(85);
if (amutec_eq_bmutec)
regmap_update_bits(cs4271->regmap, CS4271_MODE2,
CS4271_MODE2_MUTECAEQUB,
CS4271_MODE2_MUTECAEQUB);
return 0;
}
static void cs4271_component_remove(struct snd_soc_component *component)
{
struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
if (gpio_is_valid(cs4271->gpio_nreset))
/* Set codec to the reset state */
gpio_set_value(cs4271->gpio_nreset, 0);
regcache_mark_dirty(cs4271->regmap);
regulator_bulk_disable(ARRAY_SIZE(cs4271->supplies), cs4271->supplies);
};
static const struct snd_soc_component_driver soc_component_dev_cs4271 = {
.probe = cs4271_component_probe,
.remove = cs4271_component_remove,
.suspend = cs4271_soc_suspend,
.resume = cs4271_soc_resume,
.controls = cs4271_snd_controls,
.num_controls = ARRAY_SIZE(cs4271_snd_controls),
.dapm_widgets = cs4271_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(cs4271_dapm_widgets),
.dapm_routes = cs4271_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(cs4271_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int cs4271_common_probe(struct device *dev,
struct cs4271_private **c)
{
struct cs4271_platform_data *cs4271plat = dev->platform_data;
struct cs4271_private *cs4271;
int i, ret;
cs4271 = devm_kzalloc(dev, sizeof(*cs4271), GFP_KERNEL);
if (!cs4271)
return -ENOMEM;
if (of_match_device(cs4271_dt_ids, dev))
cs4271->gpio_nreset =
of_get_named_gpio(dev->of_node, "reset-gpio", 0);
if (cs4271plat)
cs4271->gpio_nreset = cs4271plat->gpio_nreset;
if (gpio_is_valid(cs4271->gpio_nreset)) {
ret = devm_gpio_request(dev, cs4271->gpio_nreset,
"CS4271 Reset");
if (ret < 0)
return ret;
}
for (i = 0; i < ARRAY_SIZE(supply_names); i++)
cs4271->supplies[i].supply = supply_names[i];
ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(cs4271->supplies),
cs4271->supplies);
if (ret < 0) {
dev_err(dev, "Failed to get regulators: %d\n", ret);
return ret;
}
*c = cs4271;
return 0;
}
const struct regmap_config cs4271_regmap_config = {
.max_register = CS4271_LASTREG,
.reg_defaults = cs4271_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(cs4271_reg_defaults),
.cache_type = REGCACHE_FLAT,
.val_bits = 8,
.volatile_reg = cs4271_volatile_reg,
};
EXPORT_SYMBOL_GPL(cs4271_regmap_config);
int cs4271_probe(struct device *dev, struct regmap *regmap)
{
struct cs4271_private *cs4271;
int ret;
if (IS_ERR(regmap))
return PTR_ERR(regmap);
ret = cs4271_common_probe(dev, &cs4271);
if (ret < 0)
return ret;
dev_set_drvdata(dev, cs4271);
cs4271->regmap = regmap;
return devm_snd_soc_register_component(dev, &soc_component_dev_cs4271,
&cs4271_dai, 1);
}
EXPORT_SYMBOL_GPL(cs4271_probe);
MODULE_AUTHOR("Alexander Sverdlin <[email protected]>");
MODULE_DESCRIPTION("Cirrus Logic CS4271 ALSA SoC Codec Driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cs4271.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Driver for the PCM512x CODECs
*
* Author: Mark Brown <[email protected]>
* Copyright 2014 Linaro Ltd
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/acpi.h>
#include "pcm512x.h"
static int pcm512x_i2c_probe(struct i2c_client *i2c)
{
struct regmap *regmap;
struct regmap_config config = pcm512x_regmap;
/* msb needs to be set to enable auto-increment of addresses */
config.read_flag_mask = 0x80;
config.write_flag_mask = 0x80;
regmap = devm_regmap_init_i2c(i2c, &config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return pcm512x_probe(&i2c->dev, regmap);
}
static void pcm512x_i2c_remove(struct i2c_client *i2c)
{
pcm512x_remove(&i2c->dev);
}
static const struct i2c_device_id pcm512x_i2c_id[] = {
{ "pcm5121", },
{ "pcm5122", },
{ "pcm5141", },
{ "pcm5142", },
{ }
};
MODULE_DEVICE_TABLE(i2c, pcm512x_i2c_id);
#if defined(CONFIG_OF)
static const struct of_device_id pcm512x_of_match[] = {
{ .compatible = "ti,pcm5121", },
{ .compatible = "ti,pcm5122", },
{ .compatible = "ti,pcm5141", },
{ .compatible = "ti,pcm5142", },
{ }
};
MODULE_DEVICE_TABLE(of, pcm512x_of_match);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id pcm512x_acpi_match[] = {
{ "104C5121", 0 },
{ "104C5122", 0 },
{ "104C5141", 0 },
{ "104C5142", 0 },
{ },
};
MODULE_DEVICE_TABLE(acpi, pcm512x_acpi_match);
#endif
static struct i2c_driver pcm512x_i2c_driver = {
.probe = pcm512x_i2c_probe,
.remove = pcm512x_i2c_remove,
.id_table = pcm512x_i2c_id,
.driver = {
.name = "pcm512x",
.of_match_table = of_match_ptr(pcm512x_of_match),
.acpi_match_table = ACPI_PTR(pcm512x_acpi_match),
.pm = &pcm512x_pm_ops,
},
};
module_i2c_driver(pcm512x_i2c_driver);
MODULE_DESCRIPTION("ASoC PCM512x codec driver - I2C");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/pcm512x-i2c.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// ALSA SoC Audio driver for CS47L90 codec
//
// Copyright (C) 2015-2019 Cirrus Logic, Inc. and
// Cirrus Logic International Semiconductor Ltd.
//
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <linux/irqchip/irq-madera.h>
#include <linux/mfd/madera/core.h>
#include <linux/mfd/madera/registers.h>
#include "madera.h"
#include "wm_adsp.h"
#define DRV_NAME "cs47l90-codec"
#define CS47L90_NUM_ADSP 7
#define CS47L90_MONO_OUTPUTS 3
struct cs47l90 {
struct madera_priv core;
struct madera_fll fll[3];
};
static const struct cs_dsp_region cs47l90_dsp1_regions[] = {
{ .type = WMFW_ADSP2_PM, .base = 0x080000 },
{ .type = WMFW_ADSP2_ZM, .base = 0x0e0000 },
{ .type = WMFW_ADSP2_XM, .base = 0x0a0000 },
{ .type = WMFW_ADSP2_YM, .base = 0x0c0000 },
};
static const struct cs_dsp_region cs47l90_dsp2_regions[] = {
{ .type = WMFW_ADSP2_PM, .base = 0x100000 },
{ .type = WMFW_ADSP2_ZM, .base = 0x160000 },
{ .type = WMFW_ADSP2_XM, .base = 0x120000 },
{ .type = WMFW_ADSP2_YM, .base = 0x140000 },
};
static const struct cs_dsp_region cs47l90_dsp3_regions[] = {
{ .type = WMFW_ADSP2_PM, .base = 0x180000 },
{ .type = WMFW_ADSP2_ZM, .base = 0x1e0000 },
{ .type = WMFW_ADSP2_XM, .base = 0x1a0000 },
{ .type = WMFW_ADSP2_YM, .base = 0x1c0000 },
};
static const struct cs_dsp_region cs47l90_dsp4_regions[] = {
{ .type = WMFW_ADSP2_PM, .base = 0x200000 },
{ .type = WMFW_ADSP2_ZM, .base = 0x260000 },
{ .type = WMFW_ADSP2_XM, .base = 0x220000 },
{ .type = WMFW_ADSP2_YM, .base = 0x240000 },
};
static const struct cs_dsp_region cs47l90_dsp5_regions[] = {
{ .type = WMFW_ADSP2_PM, .base = 0x280000 },
{ .type = WMFW_ADSP2_ZM, .base = 0x2e0000 },
{ .type = WMFW_ADSP2_XM, .base = 0x2a0000 },
{ .type = WMFW_ADSP2_YM, .base = 0x2c0000 },
};
static const struct cs_dsp_region cs47l90_dsp6_regions[] = {
{ .type = WMFW_ADSP2_PM, .base = 0x300000 },
{ .type = WMFW_ADSP2_ZM, .base = 0x360000 },
{ .type = WMFW_ADSP2_XM, .base = 0x320000 },
{ .type = WMFW_ADSP2_YM, .base = 0x340000 },
};
static const struct cs_dsp_region cs47l90_dsp7_regions[] = {
{ .type = WMFW_ADSP2_PM, .base = 0x380000 },
{ .type = WMFW_ADSP2_ZM, .base = 0x3e0000 },
{ .type = WMFW_ADSP2_XM, .base = 0x3a0000 },
{ .type = WMFW_ADSP2_YM, .base = 0x3c0000 },
};
static const struct cs_dsp_region *cs47l90_dsp_regions[] = {
cs47l90_dsp1_regions,
cs47l90_dsp2_regions,
cs47l90_dsp3_regions,
cs47l90_dsp4_regions,
cs47l90_dsp5_regions,
cs47l90_dsp6_regions,
cs47l90_dsp7_regions,
};
static const int cs47l90_dsp_control_bases[] = {
MADERA_DSP1_CONFIG_1,
MADERA_DSP2_CONFIG_1,
MADERA_DSP3_CONFIG_1,
MADERA_DSP4_CONFIG_1,
MADERA_DSP5_CONFIG_1,
MADERA_DSP6_CONFIG_1,
MADERA_DSP7_CONFIG_1,
};
static int cs47l90_adsp_power_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct cs47l90 *cs47l90 = snd_soc_component_get_drvdata(component);
struct madera_priv *priv = &cs47l90->core;
struct madera *madera = priv->madera;
unsigned int freq;
int ret;
ret = regmap_read(madera->regmap, MADERA_DSP_CLOCK_2, &freq);
if (ret != 0) {
dev_err(madera->dev,
"Failed to read MADERA_DSP_CLOCK_2: %d\n", ret);
return ret;
}
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
ret = madera_set_adsp_clk(&cs47l90->core, w->shift, freq);
if (ret)
return ret;
break;
default:
break;
}
return wm_adsp_early_event(w, kcontrol, event);
}
#define CS47L90_NG_SRC(name, base) \
SOC_SINGLE(name " NG HPOUT1L Switch", base, 0, 1, 0), \
SOC_SINGLE(name " NG HPOUT1R Switch", base, 1, 1, 0), \
SOC_SINGLE(name " NG HPOUT2L Switch", base, 2, 1, 0), \
SOC_SINGLE(name " NG HPOUT2R Switch", base, 3, 1, 0), \
SOC_SINGLE(name " NG HPOUT3L Switch", base, 4, 1, 0), \
SOC_SINGLE(name " NG HPOUT3R Switch", base, 5, 1, 0), \
SOC_SINGLE(name " NG SPKDAT1L Switch", base, 8, 1, 0), \
SOC_SINGLE(name " NG SPKDAT1R Switch", base, 9, 1, 0)
#define CS47L90_RXANC_INPUT_ROUTES(widget, name) \
{ widget, NULL, name " NG Mux" }, \
{ name " NG Internal", NULL, "RXANC NG Clock" }, \
{ name " NG Internal", NULL, name " Channel" }, \
{ name " NG External", NULL, "RXANC NG External Clock" }, \
{ name " NG External", NULL, name " Channel" }, \
{ name " NG Mux", "None", name " Channel" }, \
{ name " NG Mux", "Internal", name " NG Internal" }, \
{ name " NG Mux", "External", name " NG External" }, \
{ name " Channel", "Left", name " Left Input" }, \
{ name " Channel", "Combine", name " Left Input" }, \
{ name " Channel", "Right", name " Right Input" }, \
{ name " Channel", "Combine", name " Right Input" }, \
{ name " Left Input", "IN1", "IN1L" }, \
{ name " Right Input", "IN1", "IN1R" }, \
{ name " Left Input", "IN2", "IN2L" }, \
{ name " Right Input", "IN2", "IN2R" }, \
{ name " Left Input", "IN3", "IN3L" }, \
{ name " Right Input", "IN3", "IN3R" }, \
{ name " Left Input", "IN4", "IN4L" }, \
{ name " Right Input", "IN4", "IN4R" }, \
{ name " Left Input", "IN5", "IN5L" }, \
{ name " Right Input", "IN5", "IN5R" }
#define CS47L90_RXANC_OUTPUT_ROUTES(widget, name) \
{ widget, NULL, name " ANC Source" }, \
{ name " ANC Source", "RXANCL", "RXANCL" }, \
{ name " ANC Source", "RXANCR", "RXANCR" }
static const struct snd_kcontrol_new cs47l90_snd_controls[] = {
SOC_ENUM("IN1 OSR", madera_in_dmic_osr[0]),
SOC_ENUM("IN2 OSR", madera_in_dmic_osr[1]),
SOC_ENUM("IN3 OSR", madera_in_dmic_osr[2]),
SOC_ENUM("IN4 OSR", madera_in_dmic_osr[3]),
SOC_ENUM("IN5 OSR", madera_in_dmic_osr[4]),
SOC_SINGLE_RANGE_TLV("IN1L Volume", MADERA_IN1L_CONTROL,
MADERA_IN1L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
SOC_SINGLE_RANGE_TLV("IN1R Volume", MADERA_IN1R_CONTROL,
MADERA_IN1R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
SOC_SINGLE_RANGE_TLV("IN2L Volume", MADERA_IN2L_CONTROL,
MADERA_IN2L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
SOC_SINGLE_RANGE_TLV("IN2R Volume", MADERA_IN2R_CONTROL,
MADERA_IN2R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
SOC_ENUM("IN HPF Cutoff Frequency", madera_in_hpf_cut_enum),
SOC_SINGLE_EXT("IN1L LP Switch", MADERA_ADC_DIGITAL_VOLUME_1L,
MADERA_IN1L_LP_MODE_SHIFT, 1, 0,
snd_soc_get_volsw, madera_lp_mode_put),
SOC_SINGLE_EXT("IN1R LP Switch", MADERA_ADC_DIGITAL_VOLUME_1R,
MADERA_IN1R_LP_MODE_SHIFT, 1, 0,
snd_soc_get_volsw, madera_lp_mode_put),
SOC_SINGLE_EXT("IN2L LP Switch", MADERA_ADC_DIGITAL_VOLUME_2L,
MADERA_IN2L_LP_MODE_SHIFT, 1, 0,
snd_soc_get_volsw, madera_lp_mode_put),
SOC_SINGLE_EXT("IN2R LP Switch", MADERA_ADC_DIGITAL_VOLUME_2R,
MADERA_IN2R_LP_MODE_SHIFT, 1, 0,
snd_soc_get_volsw, madera_lp_mode_put),
SOC_SINGLE("IN1L HPF Switch", MADERA_IN1L_CONTROL,
MADERA_IN1L_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN1R HPF Switch", MADERA_IN1R_CONTROL,
MADERA_IN1R_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN2L HPF Switch", MADERA_IN2L_CONTROL,
MADERA_IN2L_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN2R HPF Switch", MADERA_IN2R_CONTROL,
MADERA_IN2R_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN3L HPF Switch", MADERA_IN3L_CONTROL,
MADERA_IN3L_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN3R HPF Switch", MADERA_IN3R_CONTROL,
MADERA_IN3R_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN4L HPF Switch", MADERA_IN4L_CONTROL,
MADERA_IN4L_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN4R HPF Switch", MADERA_IN4R_CONTROL,
MADERA_IN4R_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN5L HPF Switch", MADERA_IN5L_CONTROL,
MADERA_IN5L_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN5R HPF Switch", MADERA_IN5R_CONTROL,
MADERA_IN5R_HPF_SHIFT, 1, 0),
SOC_SINGLE_TLV("IN1L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_1L,
MADERA_IN1L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_SINGLE_TLV("IN1R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_1R,
MADERA_IN1R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_SINGLE_TLV("IN2L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_2L,
MADERA_IN2L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_SINGLE_TLV("IN2R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_2R,
MADERA_IN2R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_SINGLE_TLV("IN3L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_3L,
MADERA_IN3L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_SINGLE_TLV("IN3R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_3R,
MADERA_IN3R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_SINGLE_TLV("IN4L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_4L,
MADERA_IN4L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_SINGLE_TLV("IN4R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_4R,
MADERA_IN4R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_SINGLE_TLV("IN5L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_5L,
MADERA_IN5L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_SINGLE_TLV("IN5R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_5R,
MADERA_IN5R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_ENUM("Input Ramp Up", madera_in_vi_ramp),
SOC_ENUM("Input Ramp Down", madera_in_vd_ramp),
SND_SOC_BYTES("RXANC Coefficients", MADERA_ANC_COEFF_START,
MADERA_ANC_COEFF_END - MADERA_ANC_COEFF_START + 1),
SND_SOC_BYTES("RXANCL Config", MADERA_FCL_FILTER_CONTROL, 1),
SND_SOC_BYTES("RXANCL Coefficients", MADERA_FCL_COEFF_START,
MADERA_FCL_COEFF_END - MADERA_FCL_COEFF_START + 1),
SND_SOC_BYTES("RXANCR Config", MADERA_FCR_FILTER_CONTROL, 1),
SND_SOC_BYTES("RXANCR Coefficients", MADERA_FCR_COEFF_START,
MADERA_FCR_COEFF_END - MADERA_FCR_COEFF_START + 1),
MADERA_MIXER_CONTROLS("EQ1", MADERA_EQ1MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("EQ2", MADERA_EQ2MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("EQ3", MADERA_EQ3MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("EQ4", MADERA_EQ4MIX_INPUT_1_SOURCE),
MADERA_EQ_CONTROL("EQ1 Coefficients", MADERA_EQ1_2),
SOC_SINGLE_TLV("EQ1 B1 Volume", MADERA_EQ1_1, MADERA_EQ1_B1_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ1 B2 Volume", MADERA_EQ1_1, MADERA_EQ1_B2_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ1 B3 Volume", MADERA_EQ1_1, MADERA_EQ1_B3_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ1 B4 Volume", MADERA_EQ1_2, MADERA_EQ1_B4_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ1 B5 Volume", MADERA_EQ1_2, MADERA_EQ1_B5_GAIN_SHIFT,
24, 0, madera_eq_tlv),
MADERA_EQ_CONTROL("EQ2 Coefficients", MADERA_EQ2_2),
SOC_SINGLE_TLV("EQ2 B1 Volume", MADERA_EQ2_1, MADERA_EQ2_B1_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ2 B2 Volume", MADERA_EQ2_1, MADERA_EQ2_B2_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ2 B3 Volume", MADERA_EQ2_1, MADERA_EQ2_B3_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ2 B4 Volume", MADERA_EQ2_2, MADERA_EQ2_B4_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ2 B5 Volume", MADERA_EQ2_2, MADERA_EQ2_B5_GAIN_SHIFT,
24, 0, madera_eq_tlv),
MADERA_EQ_CONTROL("EQ3 Coefficients", MADERA_EQ3_2),
SOC_SINGLE_TLV("EQ3 B1 Volume", MADERA_EQ3_1, MADERA_EQ3_B1_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ3 B2 Volume", MADERA_EQ3_1, MADERA_EQ3_B2_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ3 B3 Volume", MADERA_EQ3_1, MADERA_EQ3_B3_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ3 B4 Volume", MADERA_EQ3_2, MADERA_EQ3_B4_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ3 B5 Volume", MADERA_EQ3_2, MADERA_EQ3_B5_GAIN_SHIFT,
24, 0, madera_eq_tlv),
MADERA_EQ_CONTROL("EQ4 Coefficients", MADERA_EQ4_2),
SOC_SINGLE_TLV("EQ4 B1 Volume", MADERA_EQ4_1, MADERA_EQ4_B1_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ4 B2 Volume", MADERA_EQ4_1, MADERA_EQ4_B2_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ4 B3 Volume", MADERA_EQ4_1, MADERA_EQ4_B3_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ4 B4 Volume", MADERA_EQ4_2, MADERA_EQ4_B4_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ4 B5 Volume", MADERA_EQ4_2, MADERA_EQ4_B5_GAIN_SHIFT,
24, 0, madera_eq_tlv),
MADERA_MIXER_CONTROLS("DRC1L", MADERA_DRC1LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DRC1R", MADERA_DRC1RMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DRC2L", MADERA_DRC2LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DRC2R", MADERA_DRC2RMIX_INPUT_1_SOURCE),
SND_SOC_BYTES_MASK("DRC1", MADERA_DRC1_CTRL1, 5,
MADERA_DRC1R_ENA | MADERA_DRC1L_ENA),
SND_SOC_BYTES_MASK("DRC2", MADERA_DRC2_CTRL1, 5,
MADERA_DRC2R_ENA | MADERA_DRC2L_ENA),
MADERA_MIXER_CONTROLS("LHPF1", MADERA_HPLP1MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("LHPF2", MADERA_HPLP2MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("LHPF3", MADERA_HPLP3MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("LHPF4", MADERA_HPLP4MIX_INPUT_1_SOURCE),
MADERA_LHPF_CONTROL("LHPF1 Coefficients", MADERA_HPLPF1_2),
MADERA_LHPF_CONTROL("LHPF2 Coefficients", MADERA_HPLPF2_2),
MADERA_LHPF_CONTROL("LHPF3 Coefficients", MADERA_HPLPF3_2),
MADERA_LHPF_CONTROL("LHPF4 Coefficients", MADERA_HPLPF4_2),
SOC_ENUM("LHPF1 Mode", madera_lhpf1_mode),
SOC_ENUM("LHPF2 Mode", madera_lhpf2_mode),
SOC_ENUM("LHPF3 Mode", madera_lhpf3_mode),
SOC_ENUM("LHPF4 Mode", madera_lhpf4_mode),
MADERA_RATE_ENUM("ISRC1 FSL", madera_isrc_fsl[0]),
MADERA_RATE_ENUM("ISRC2 FSL", madera_isrc_fsl[1]),
MADERA_RATE_ENUM("ISRC3 FSL", madera_isrc_fsl[2]),
MADERA_RATE_ENUM("ISRC4 FSL", madera_isrc_fsl[3]),
MADERA_RATE_ENUM("ISRC1 FSH", madera_isrc_fsh[0]),
MADERA_RATE_ENUM("ISRC2 FSH", madera_isrc_fsh[1]),
MADERA_RATE_ENUM("ISRC3 FSH", madera_isrc_fsh[2]),
MADERA_RATE_ENUM("ISRC4 FSH", madera_isrc_fsh[3]),
MADERA_RATE_ENUM("ASRC1 Rate 1", madera_asrc1_rate[0]),
MADERA_RATE_ENUM("ASRC1 Rate 2", madera_asrc1_rate[1]),
MADERA_RATE_ENUM("ASRC2 Rate 1", madera_asrc2_rate[0]),
MADERA_RATE_ENUM("ASRC2 Rate 2", madera_asrc2_rate[1]),
WM_ADSP2_PRELOAD_SWITCH("DSP1", 1),
WM_ADSP2_PRELOAD_SWITCH("DSP2", 2),
WM_ADSP2_PRELOAD_SWITCH("DSP3", 3),
WM_ADSP2_PRELOAD_SWITCH("DSP4", 4),
WM_ADSP2_PRELOAD_SWITCH("DSP5", 5),
WM_ADSP2_PRELOAD_SWITCH("DSP6", 6),
WM_ADSP2_PRELOAD_SWITCH("DSP7", 7),
MADERA_MIXER_CONTROLS("DSP1L", MADERA_DSP1LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DSP1R", MADERA_DSP1RMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DSP2L", MADERA_DSP2LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DSP2R", MADERA_DSP2RMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DSP3L", MADERA_DSP3LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DSP3R", MADERA_DSP3RMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DSP4L", MADERA_DSP4LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DSP4R", MADERA_DSP4RMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DSP5L", MADERA_DSP5LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DSP5R", MADERA_DSP5RMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DSP6L", MADERA_DSP6LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DSP6R", MADERA_DSP6RMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DSP7L", MADERA_DSP7LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DSP7R", MADERA_DSP7RMIX_INPUT_1_SOURCE),
SOC_SINGLE_TLV("Noise Generator Volume", MADERA_COMFORT_NOISE_GENERATOR,
MADERA_NOISE_GEN_GAIN_SHIFT, 0x16, 0, madera_noise_tlv),
MADERA_MIXER_CONTROLS("HPOUT1L", MADERA_OUT1LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("HPOUT1R", MADERA_OUT1RMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("HPOUT2L", MADERA_OUT2LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("HPOUT2R", MADERA_OUT2RMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("HPOUT3L", MADERA_OUT3LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("HPOUT3R", MADERA_OUT3RMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SPKDAT1L", MADERA_OUT5LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SPKDAT1R", MADERA_OUT5RMIX_INPUT_1_SOURCE),
SOC_SINGLE("HPOUT1 SC Protect Switch", MADERA_HP1_SHORT_CIRCUIT_CTRL,
MADERA_HP1_SC_ENA_SHIFT, 1, 0),
SOC_SINGLE("HPOUT2 SC Protect Switch", MADERA_HP2_SHORT_CIRCUIT_CTRL,
MADERA_HP2_SC_ENA_SHIFT, 1, 0),
SOC_SINGLE("HPOUT3 SC Protect Switch", MADERA_HP3_SHORT_CIRCUIT_CTRL,
MADERA_HP3_SC_ENA_SHIFT, 1, 0),
SOC_SINGLE("SPKDAT1 High Performance Switch", MADERA_OUTPUT_PATH_CONFIG_5L,
MADERA_OUT5_OSR_SHIFT, 1, 0),
SOC_DOUBLE_R("HPOUT1 Digital Switch", MADERA_DAC_DIGITAL_VOLUME_1L,
MADERA_DAC_DIGITAL_VOLUME_1R, MADERA_OUT1L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R("HPOUT2 Digital Switch", MADERA_DAC_DIGITAL_VOLUME_2L,
MADERA_DAC_DIGITAL_VOLUME_2R, MADERA_OUT2L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R("HPOUT3 Digital Switch", MADERA_DAC_DIGITAL_VOLUME_3L,
MADERA_DAC_DIGITAL_VOLUME_3R, MADERA_OUT3L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R("SPKDAT1 Digital Switch", MADERA_DAC_DIGITAL_VOLUME_5L,
MADERA_DAC_DIGITAL_VOLUME_5R, MADERA_OUT5L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", MADERA_DAC_DIGITAL_VOLUME_1L,
MADERA_DAC_DIGITAL_VOLUME_1R, MADERA_OUT1L_VOL_SHIFT,
0xbf, 0, madera_digital_tlv),
SOC_DOUBLE_R_TLV("HPOUT2 Digital Volume", MADERA_DAC_DIGITAL_VOLUME_2L,
MADERA_DAC_DIGITAL_VOLUME_2R, MADERA_OUT2L_VOL_SHIFT,
0xbf, 0, madera_digital_tlv),
SOC_DOUBLE_R_TLV("HPOUT3 Digital Volume", MADERA_DAC_DIGITAL_VOLUME_3L,
MADERA_DAC_DIGITAL_VOLUME_3R, MADERA_OUT3L_VOL_SHIFT,
0xbf, 0, madera_digital_tlv),
SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", MADERA_DAC_DIGITAL_VOLUME_5L,
MADERA_DAC_DIGITAL_VOLUME_5R, MADERA_OUT5L_VOL_SHIFT,
0xbf, 0, madera_digital_tlv),
SOC_DOUBLE("SPKDAT1 Switch", MADERA_PDM_SPK1_CTRL_1, MADERA_SPK1L_MUTE_SHIFT,
MADERA_SPK1R_MUTE_SHIFT, 1, 1),
SOC_ENUM("Output Ramp Up", madera_out_vi_ramp),
SOC_ENUM("Output Ramp Down", madera_out_vd_ramp),
SOC_SINGLE("Noise Gate Switch", MADERA_NOISE_GATE_CONTROL,
MADERA_NGATE_ENA_SHIFT, 1, 0),
SOC_SINGLE_TLV("Noise Gate Threshold Volume", MADERA_NOISE_GATE_CONTROL,
MADERA_NGATE_THR_SHIFT, 7, 1, madera_ng_tlv),
SOC_ENUM("Noise Gate Hold", madera_ng_hold),
SOC_ENUM_EXT("DFC1RX Width", madera_dfc_width[0],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC1RX Type", madera_dfc_type[0],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC1TX Width", madera_dfc_width[1],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC1TX Type", madera_dfc_type[1],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC2RX Width", madera_dfc_width[2],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC2RX Type", madera_dfc_type[2],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC2TX Width", madera_dfc_width[3],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC2TX Type", madera_dfc_type[3],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC3RX Width", madera_dfc_width[4],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC3RX Type", madera_dfc_type[4],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC3TX Width", madera_dfc_width[5],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC3TX Type", madera_dfc_type[5],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC4RX Width", madera_dfc_width[6],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC4RX Type", madera_dfc_type[6],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC4TX Width", madera_dfc_width[7],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC4TX Type", madera_dfc_type[7],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC5RX Width", madera_dfc_width[8],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC5RX Type", madera_dfc_type[8],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC5TX Width", madera_dfc_width[9],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC5TX Type", madera_dfc_type[9],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC6RX Width", madera_dfc_width[10],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC6RX Type", madera_dfc_type[10],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC6TX Width", madera_dfc_width[11],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC6TX Type", madera_dfc_type[11],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC7RX Width", madera_dfc_width[12],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC7RX Type", madera_dfc_type[12],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC7TX Width", madera_dfc_width[13],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC7TX Type", madera_dfc_type[13],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC8RX Width", madera_dfc_width[14],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC8RX Type", madera_dfc_type[14],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC8TX Width", madera_dfc_width[15],
snd_soc_get_enum_double, madera_dfc_put),
SOC_ENUM_EXT("DFC8TX Type", madera_dfc_type[15],
snd_soc_get_enum_double, madera_dfc_put),
CS47L90_NG_SRC("HPOUT1L", MADERA_NOISE_GATE_SELECT_1L),
CS47L90_NG_SRC("HPOUT1R", MADERA_NOISE_GATE_SELECT_1R),
CS47L90_NG_SRC("HPOUT2L", MADERA_NOISE_GATE_SELECT_2L),
CS47L90_NG_SRC("HPOUT2R", MADERA_NOISE_GATE_SELECT_2R),
CS47L90_NG_SRC("HPOUT3L", MADERA_NOISE_GATE_SELECT_3L),
CS47L90_NG_SRC("HPOUT3R", MADERA_NOISE_GATE_SELECT_3R),
CS47L90_NG_SRC("SPKDAT1L", MADERA_NOISE_GATE_SELECT_5L),
CS47L90_NG_SRC("SPKDAT1R", MADERA_NOISE_GATE_SELECT_5R),
MADERA_MIXER_CONTROLS("AIF1TX1", MADERA_AIF1TX1MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF1TX2", MADERA_AIF1TX2MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF1TX3", MADERA_AIF1TX3MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF1TX4", MADERA_AIF1TX4MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF1TX5", MADERA_AIF1TX5MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF1TX6", MADERA_AIF1TX6MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF1TX7", MADERA_AIF1TX7MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF1TX8", MADERA_AIF1TX8MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF2TX1", MADERA_AIF2TX1MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF2TX2", MADERA_AIF2TX2MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF2TX3", MADERA_AIF2TX3MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF2TX4", MADERA_AIF2TX4MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF2TX5", MADERA_AIF2TX5MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF2TX6", MADERA_AIF2TX6MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF2TX7", MADERA_AIF2TX7MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF2TX8", MADERA_AIF2TX8MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF3TX1", MADERA_AIF3TX1MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF3TX2", MADERA_AIF3TX2MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF4TX1", MADERA_AIF4TX1MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF4TX2", MADERA_AIF4TX2MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SLIMTX1", MADERA_SLIMTX1MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SLIMTX2", MADERA_SLIMTX2MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SLIMTX3", MADERA_SLIMTX3MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SLIMTX4", MADERA_SLIMTX4MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SLIMTX5", MADERA_SLIMTX5MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SLIMTX6", MADERA_SLIMTX6MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SLIMTX7", MADERA_SLIMTX7MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SLIMTX8", MADERA_SLIMTX8MIX_INPUT_1_SOURCE),
MADERA_GAINMUX_CONTROLS("SPDIF1TX1", MADERA_SPDIF1TX1MIX_INPUT_1_SOURCE),
MADERA_GAINMUX_CONTROLS("SPDIF1TX2", MADERA_SPDIF1TX2MIX_INPUT_1_SOURCE),
WM_ADSP_FW_CONTROL("DSP1", 0),
WM_ADSP_FW_CONTROL("DSP2", 1),
WM_ADSP_FW_CONTROL("DSP3", 2),
WM_ADSP_FW_CONTROL("DSP4", 3),
WM_ADSP_FW_CONTROL("DSP5", 4),
WM_ADSP_FW_CONTROL("DSP6", 5),
WM_ADSP_FW_CONTROL("DSP7", 6),
};
MADERA_MIXER_ENUMS(EQ1, MADERA_EQ1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(EQ2, MADERA_EQ2MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(EQ3, MADERA_EQ3MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(EQ4, MADERA_EQ4MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DRC1L, MADERA_DRC1LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DRC1R, MADERA_DRC1RMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DRC2L, MADERA_DRC2LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DRC2R, MADERA_DRC2RMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(LHPF1, MADERA_HPLP1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(LHPF2, MADERA_HPLP2MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(LHPF3, MADERA_HPLP3MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(LHPF4, MADERA_HPLP4MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP1L, MADERA_DSP1LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP1R, MADERA_DSP1RMIX_INPUT_1_SOURCE);
MADERA_DSP_AUX_ENUMS(DSP1, MADERA_DSP1AUX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP2L, MADERA_DSP2LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP2R, MADERA_DSP2RMIX_INPUT_1_SOURCE);
MADERA_DSP_AUX_ENUMS(DSP2, MADERA_DSP2AUX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP3L, MADERA_DSP3LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP3R, MADERA_DSP3RMIX_INPUT_1_SOURCE);
MADERA_DSP_AUX_ENUMS(DSP3, MADERA_DSP3AUX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP4L, MADERA_DSP4LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP4R, MADERA_DSP4RMIX_INPUT_1_SOURCE);
MADERA_DSP_AUX_ENUMS(DSP4, MADERA_DSP4AUX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP5L, MADERA_DSP5LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP5R, MADERA_DSP5RMIX_INPUT_1_SOURCE);
MADERA_DSP_AUX_ENUMS(DSP5, MADERA_DSP5AUX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP6L, MADERA_DSP6LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP6R, MADERA_DSP6RMIX_INPUT_1_SOURCE);
MADERA_DSP_AUX_ENUMS(DSP6, MADERA_DSP6AUX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP7L, MADERA_DSP7LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP7R, MADERA_DSP7RMIX_INPUT_1_SOURCE);
MADERA_DSP_AUX_ENUMS(DSP7, MADERA_DSP7AUX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(PWM1, MADERA_PWM1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(PWM2, MADERA_PWM2MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(OUT1L, MADERA_OUT1LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(OUT1R, MADERA_OUT1RMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(OUT2L, MADERA_OUT2LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(OUT2R, MADERA_OUT2RMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(OUT3L, MADERA_OUT3LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(OUT3R, MADERA_OUT3RMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SPKDAT1L, MADERA_OUT5LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SPKDAT1R, MADERA_OUT5RMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX1, MADERA_AIF1TX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX2, MADERA_AIF1TX2MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX3, MADERA_AIF1TX3MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX4, MADERA_AIF1TX4MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX5, MADERA_AIF1TX5MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX6, MADERA_AIF1TX6MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX7, MADERA_AIF1TX7MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX8, MADERA_AIF1TX8MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF2TX1, MADERA_AIF2TX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF2TX2, MADERA_AIF2TX2MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF2TX3, MADERA_AIF2TX3MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF2TX4, MADERA_AIF2TX4MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF2TX5, MADERA_AIF2TX5MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF2TX6, MADERA_AIF2TX6MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF2TX7, MADERA_AIF2TX7MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF2TX8, MADERA_AIF2TX8MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF3TX1, MADERA_AIF3TX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF3TX2, MADERA_AIF3TX2MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF4TX1, MADERA_AIF4TX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF4TX2, MADERA_AIF4TX2MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SLIMTX1, MADERA_SLIMTX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SLIMTX2, MADERA_SLIMTX2MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SLIMTX3, MADERA_SLIMTX3MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SLIMTX4, MADERA_SLIMTX4MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SLIMTX5, MADERA_SLIMTX5MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SLIMTX6, MADERA_SLIMTX6MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SLIMTX7, MADERA_SLIMTX7MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SLIMTX8, MADERA_SLIMTX8MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(SPD1TX1, MADERA_SPDIF1TX1MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(SPD1TX2, MADERA_SPDIF1TX2MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ASRC1IN1L, MADERA_ASRC1_1LMIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ASRC1IN1R, MADERA_ASRC1_1RMIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ASRC1IN2L, MADERA_ASRC1_2LMIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ASRC1IN2R, MADERA_ASRC1_2RMIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ASRC2IN1L, MADERA_ASRC2_1LMIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ASRC2IN1R, MADERA_ASRC2_1RMIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ASRC2IN2L, MADERA_ASRC2_2LMIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ASRC2IN2R, MADERA_ASRC2_2RMIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1INT1, MADERA_ISRC1INT1MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1INT2, MADERA_ISRC1INT2MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1INT3, MADERA_ISRC1INT3MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1INT4, MADERA_ISRC1INT4MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1DEC1, MADERA_ISRC1DEC1MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1DEC2, MADERA_ISRC1DEC2MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1DEC3, MADERA_ISRC1DEC3MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1DEC4, MADERA_ISRC1DEC4MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2INT1, MADERA_ISRC2INT1MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2INT2, MADERA_ISRC2INT2MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2INT3, MADERA_ISRC2INT3MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2INT4, MADERA_ISRC2INT4MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2DEC1, MADERA_ISRC2DEC1MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2DEC2, MADERA_ISRC2DEC2MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2DEC3, MADERA_ISRC2DEC3MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2DEC4, MADERA_ISRC2DEC4MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC3INT1, MADERA_ISRC3INT1MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC3INT2, MADERA_ISRC3INT2MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC3DEC1, MADERA_ISRC3DEC1MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC3DEC2, MADERA_ISRC3DEC2MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC4INT1, MADERA_ISRC4INT1MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC4INT2, MADERA_ISRC4INT2MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC4DEC1, MADERA_ISRC4DEC1MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC4DEC2, MADERA_ISRC4DEC2MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(DFC1, MADERA_DFC1MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(DFC2, MADERA_DFC2MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(DFC3, MADERA_DFC3MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(DFC4, MADERA_DFC4MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(DFC5, MADERA_DFC5MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(DFC6, MADERA_DFC6MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(DFC7, MADERA_DFC7MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(DFC8, MADERA_DFC8MIX_INPUT_1_SOURCE);
static const char * const cs47l90_aec_loopback_texts[] = {
"HPOUT1L", "HPOUT1R", "HPOUT2L", "HPOUT2R", "HPOUT3L", "HPOUT3R",
"SPKDAT1L", "SPKDAT1R",
};
static const unsigned int cs47l90_aec_loopback_values[] = {
0, 1, 2, 3, 4, 5, 8, 9,
};
static const struct soc_enum cs47l90_aec1_loopback =
SOC_VALUE_ENUM_SINGLE(MADERA_DAC_AEC_CONTROL_1,
MADERA_AEC1_LOOPBACK_SRC_SHIFT, 0xf,
ARRAY_SIZE(cs47l90_aec_loopback_texts),
cs47l90_aec_loopback_texts,
cs47l90_aec_loopback_values);
static const struct soc_enum cs47l90_aec2_loopback =
SOC_VALUE_ENUM_SINGLE(MADERA_DAC_AEC_CONTROL_2,
MADERA_AEC2_LOOPBACK_SRC_SHIFT, 0xf,
ARRAY_SIZE(cs47l90_aec_loopback_texts),
cs47l90_aec_loopback_texts,
cs47l90_aec_loopback_values);
static const struct snd_kcontrol_new cs47l90_aec_loopback_mux[] = {
SOC_DAPM_ENUM("AEC1 Loopback", cs47l90_aec1_loopback),
SOC_DAPM_ENUM("AEC2 Loopback", cs47l90_aec2_loopback),
};
static const struct snd_kcontrol_new cs47l90_anc_input_mux[] = {
SOC_DAPM_ENUM("RXANCL Input", madera_anc_input_src[0]),
SOC_DAPM_ENUM("RXANCL Channel", madera_anc_input_src[1]),
SOC_DAPM_ENUM("RXANCR Input", madera_anc_input_src[2]),
SOC_DAPM_ENUM("RXANCR Channel", madera_anc_input_src[3]),
};
static const struct snd_kcontrol_new cs47l90_anc_ng_mux =
SOC_DAPM_ENUM("RXANC NG Source", madera_anc_ng_enum);
static const struct snd_kcontrol_new cs47l90_output_anc_src[] = {
SOC_DAPM_ENUM("HPOUT1L ANC Source", madera_output_anc_src[0]),
SOC_DAPM_ENUM("HPOUT1R ANC Source", madera_output_anc_src[1]),
SOC_DAPM_ENUM("HPOUT2L ANC Source", madera_output_anc_src[2]),
SOC_DAPM_ENUM("HPOUT2R ANC Source", madera_output_anc_src[3]),
SOC_DAPM_ENUM("HPOUT3L ANC Source", madera_output_anc_src[4]),
SOC_DAPM_ENUM("HPOUT3R ANC Source", madera_output_anc_src[0]),
SOC_DAPM_ENUM("SPKDAT1L ANC Source", madera_output_anc_src[8]),
SOC_DAPM_ENUM("SPKDAT1R ANC Source", madera_output_anc_src[9]),
};
static const struct snd_soc_dapm_widget cs47l90_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("SYSCLK", MADERA_SYSTEM_CLOCK_1, MADERA_SYSCLK_ENA_SHIFT,
0, madera_sysclk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("ASYNCCLK", MADERA_ASYNC_CLOCK_1,
MADERA_ASYNC_CLK_ENA_SHIFT, 0, madera_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("OPCLK", MADERA_OUTPUT_SYSTEM_CLOCK,
MADERA_OPCLK_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ASYNCOPCLK", MADERA_OUTPUT_ASYNC_CLOCK,
MADERA_OPCLK_ASYNC_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DSPCLK", MADERA_DSP_CLOCK_1, MADERA_DSP_CLK_ENA_SHIFT,
0, madera_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD2", 0, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD3", 0, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD4", 0, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD1", 20, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD2", 20, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("MICVDD", 0, SND_SOC_DAPM_REGULATOR_BYPASS),
SND_SOC_DAPM_SUPPLY("MICBIAS1", MADERA_MIC_BIAS_CTRL_1,
MADERA_MICB1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS2", MADERA_MIC_BIAS_CTRL_2,
MADERA_MICB1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS1A", MADERA_MIC_BIAS_CTRL_5,
MADERA_MICB1A_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS1B", MADERA_MIC_BIAS_CTRL_5,
MADERA_MICB1B_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS1C", MADERA_MIC_BIAS_CTRL_5,
MADERA_MICB1C_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS1D", MADERA_MIC_BIAS_CTRL_5,
MADERA_MICB1D_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS2A", MADERA_MIC_BIAS_CTRL_6,
MADERA_MICB2A_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS2B", MADERA_MIC_BIAS_CTRL_6,
MADERA_MICB2B_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS2C", MADERA_MIC_BIAS_CTRL_6,
MADERA_MICB2C_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS2D", MADERA_MIC_BIAS_CTRL_6,
MADERA_MICB2D_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("FXCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_FX, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("ASRC1CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_ASRC1, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("ASRC2CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_ASRC2, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("ISRC1CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_ISRC1, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("ISRC2CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_ISRC2, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("ISRC3CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_ISRC3, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("ISRC4CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_ISRC4, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("OUTCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_OUT, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("SPDCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_SPD, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_DSP1, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_DSP2, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("DSP3CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_DSP3, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("DSP4CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_DSP4, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("DSP5CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_DSP5, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("DSP6CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_DSP6, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("DSP7CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_DSP7, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("AIF1TXCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_AIF1, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("AIF2TXCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_AIF2, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("AIF3TXCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_AIF3, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("AIF4TXCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_AIF4, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("SLIMBUSCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_SLIMBUS, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("PWMCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_PWM, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("DFCCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_DFC, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SIGGEN("TONE"),
SND_SOC_DAPM_SIGGEN("NOISE"),
SND_SOC_DAPM_INPUT("IN1ALN"),
SND_SOC_DAPM_INPUT("IN1ALP"),
SND_SOC_DAPM_INPUT("IN1BLN"),
SND_SOC_DAPM_INPUT("IN1BLP"),
SND_SOC_DAPM_INPUT("IN1ARN"),
SND_SOC_DAPM_INPUT("IN1ARP"),
SND_SOC_DAPM_INPUT("IN1BRN"),
SND_SOC_DAPM_INPUT("IN1BRP"),
SND_SOC_DAPM_INPUT("IN2ALN"),
SND_SOC_DAPM_INPUT("IN2ALP"),
SND_SOC_DAPM_INPUT("IN2BLN"),
SND_SOC_DAPM_INPUT("IN2BLP"),
SND_SOC_DAPM_INPUT("IN2RN"),
SND_SOC_DAPM_INPUT("IN2RP"),
SND_SOC_DAPM_INPUT("DMICCLK3"),
SND_SOC_DAPM_INPUT("DMICDAT3"),
SND_SOC_DAPM_INPUT("DMICCLK4"),
SND_SOC_DAPM_INPUT("DMICDAT4"),
SND_SOC_DAPM_INPUT("DMICCLK5"),
SND_SOC_DAPM_INPUT("DMICDAT5"),
SND_SOC_DAPM_MUX("IN1L Analog Mux", SND_SOC_NOPM, 0, 0, &madera_inmux[0]),
SND_SOC_DAPM_MUX("IN1R Analog Mux", SND_SOC_NOPM, 0, 0, &madera_inmux[1]),
SND_SOC_DAPM_MUX("IN2L Analog Mux", SND_SOC_NOPM, 0, 0, &madera_inmux[2]),
SND_SOC_DAPM_MUX("IN1L Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[0]),
SND_SOC_DAPM_MUX("IN1R Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[0]),
SND_SOC_DAPM_MUX("IN2L Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[1]),
SND_SOC_DAPM_MUX("IN2R Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[1]),
SND_SOC_DAPM_OUTPUT("DRC1 Signal Activity"),
SND_SOC_DAPM_OUTPUT("DRC2 Signal Activity"),
SND_SOC_DAPM_OUTPUT("DSP Trigger Out"),
SND_SOC_DAPM_PGA("PWM1 Driver", MADERA_PWM_DRIVE_1, MADERA_PWM1_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA("PWM2 Driver", MADERA_PWM_DRIVE_1, MADERA_PWM2_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY("RXANC NG External Clock", SND_SOC_NOPM,
MADERA_EXT_NG_SEL_SET_SHIFT, 0, madera_anc_ev,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA("RXANCL NG External", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("RXANCR NG External", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("RXANC NG Clock", SND_SOC_NOPM,
MADERA_CLK_NG_ENA_SET_SHIFT, 0, madera_anc_ev,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA("RXANCL NG Internal", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("RXANCR NG Internal", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX("RXANCL Left Input", SND_SOC_NOPM, 0, 0,
&cs47l90_anc_input_mux[0]),
SND_SOC_DAPM_MUX("RXANCL Right Input", SND_SOC_NOPM, 0, 0,
&cs47l90_anc_input_mux[0]),
SND_SOC_DAPM_MUX("RXANCL Channel", SND_SOC_NOPM, 0, 0,
&cs47l90_anc_input_mux[1]),
SND_SOC_DAPM_MUX("RXANCL NG Mux", SND_SOC_NOPM, 0, 0, &cs47l90_anc_ng_mux),
SND_SOC_DAPM_MUX("RXANCR Left Input", SND_SOC_NOPM, 0, 0,
&cs47l90_anc_input_mux[2]),
SND_SOC_DAPM_MUX("RXANCR Right Input", SND_SOC_NOPM, 0, 0,
&cs47l90_anc_input_mux[2]),
SND_SOC_DAPM_MUX("RXANCR Channel", SND_SOC_NOPM, 0, 0,
&cs47l90_anc_input_mux[3]),
SND_SOC_DAPM_MUX("RXANCR NG Mux", SND_SOC_NOPM, 0, 0, &cs47l90_anc_ng_mux),
SND_SOC_DAPM_PGA_E("RXANCL", SND_SOC_NOPM, MADERA_CLK_L_ENA_SET_SHIFT,
0, NULL, 0, madera_anc_ev,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA_E("RXANCR", SND_SOC_NOPM, MADERA_CLK_R_ENA_SET_SHIFT,
0, NULL, 0, madera_anc_ev,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_MUX("HPOUT1L ANC Source", SND_SOC_NOPM, 0, 0,
&cs47l90_output_anc_src[0]),
SND_SOC_DAPM_MUX("HPOUT1R ANC Source", SND_SOC_NOPM, 0, 0,
&cs47l90_output_anc_src[1]),
SND_SOC_DAPM_MUX("HPOUT2L ANC Source", SND_SOC_NOPM, 0, 0,
&cs47l90_output_anc_src[2]),
SND_SOC_DAPM_MUX("HPOUT2R ANC Source", SND_SOC_NOPM, 0, 0,
&cs47l90_output_anc_src[3]),
SND_SOC_DAPM_MUX("HPOUT3L ANC Source", SND_SOC_NOPM, 0, 0,
&cs47l90_output_anc_src[4]),
SND_SOC_DAPM_MUX("HPOUT3R ANC Source", SND_SOC_NOPM, 0, 0,
&cs47l90_output_anc_src[5]),
SND_SOC_DAPM_MUX("SPKDAT1L ANC Source", SND_SOC_NOPM, 0, 0,
&cs47l90_output_anc_src[6]),
SND_SOC_DAPM_MUX("SPKDAT1R ANC Source", SND_SOC_NOPM, 0, 0,
&cs47l90_output_anc_src[7]),
SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 0,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 1,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 2,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 3,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 4,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX6", NULL, 5,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX7", NULL, 6,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX7_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX8", NULL, 7,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX8_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0,
MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX2", NULL, 1,
MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX3", NULL, 2,
MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX4", NULL, 3,
MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX5", NULL, 4,
MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX6", NULL, 5,
MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX7", NULL, 6,
MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX7_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX8", NULL, 7,
MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX8_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX1", NULL, 0,
MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
MADERA_SLIMTX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX2", NULL, 1,
MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
MADERA_SLIMTX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX3", NULL, 2,
MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
MADERA_SLIMTX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX4", NULL, 3,
MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
MADERA_SLIMTX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX5", NULL, 4,
MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
MADERA_SLIMTX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX6", NULL, 5,
MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
MADERA_SLIMTX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX7", NULL, 6,
MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
MADERA_SLIMTX7_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX8", NULL, 7,
MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
MADERA_SLIMTX8_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF3TX1", NULL, 0,
MADERA_AIF3_TX_ENABLES, MADERA_AIF3TX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF3TX2", NULL, 1,
MADERA_AIF3_TX_ENABLES, MADERA_AIF3TX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF4TX1", NULL, 0,
MADERA_AIF4_TX_ENABLES, MADERA_AIF4TX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF4TX2", NULL, 1,
MADERA_AIF4_TX_ENABLES, MADERA_AIF4TX2_ENA_SHIFT, 0),
SND_SOC_DAPM_PGA_E("OUT1L", SND_SOC_NOPM,
MADERA_OUT1L_ENA_SHIFT, 0, NULL, 0, madera_hp_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT1R", SND_SOC_NOPM,
MADERA_OUT1R_ENA_SHIFT, 0, NULL, 0, madera_hp_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT2L", SND_SOC_NOPM,
MADERA_OUT2L_ENA_SHIFT, 0, NULL, 0, madera_hp_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT2R", SND_SOC_NOPM,
MADERA_OUT2R_ENA_SHIFT, 0, NULL, 0, madera_hp_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT3L", SND_SOC_NOPM,
MADERA_OUT3L_ENA_SHIFT, 0, NULL, 0, madera_hp_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT3R", SND_SOC_NOPM,
MADERA_OUT3R_ENA_SHIFT, 0, NULL, 0, madera_hp_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT5L", MADERA_OUTPUT_ENABLES_1,
MADERA_OUT5L_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT5R", MADERA_OUTPUT_ENABLES_1,
MADERA_OUT5R_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA("SPD1TX1", MADERA_SPD1_TX_CONTROL,
MADERA_SPD1_VAL1_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("SPD1TX2", MADERA_SPD1_TX_CONTROL,
MADERA_SPD1_VAL2_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("SPD1", MADERA_SPD1_TX_CONTROL,
MADERA_SPD1_ENA_SHIFT, 0, NULL, 0),
/*
* mux_in widgets : arranged in the order of sources
* specified in MADERA_MIXER_INPUT_ROUTES
*/
SND_SOC_DAPM_PGA("Noise Generator", MADERA_COMFORT_NOISE_GENERATOR,
MADERA_NOISE_GEN_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("Tone Generator 1", MADERA_TONE_GENERATOR_1,
MADERA_TONE1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("Tone Generator 2", MADERA_TONE_GENERATOR_1,
MADERA_TONE2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SIGGEN("HAPTICS"),
SND_SOC_DAPM_MUX("AEC1 Loopback", MADERA_DAC_AEC_CONTROL_1,
MADERA_AEC1_LOOPBACK_ENA_SHIFT, 0,
&cs47l90_aec_loopback_mux[0]),
SND_SOC_DAPM_MUX("AEC2 Loopback", MADERA_DAC_AEC_CONTROL_2,
MADERA_AEC2_LOOPBACK_ENA_SHIFT, 0,
&cs47l90_aec_loopback_mux[1]),
SND_SOC_DAPM_PGA_E("IN1L", MADERA_INPUT_ENABLES, MADERA_IN1L_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN1R", MADERA_INPUT_ENABLES, MADERA_IN1R_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN2L", MADERA_INPUT_ENABLES, MADERA_IN2L_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN2R", MADERA_INPUT_ENABLES, MADERA_IN2R_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN3L", MADERA_INPUT_ENABLES, MADERA_IN3L_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN3R", MADERA_INPUT_ENABLES, MADERA_IN3R_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN4L", MADERA_INPUT_ENABLES, MADERA_IN4L_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN4R", MADERA_INPUT_ENABLES, MADERA_IN4R_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN5L", MADERA_INPUT_ENABLES, MADERA_IN5L_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN5R", MADERA_INPUT_ENABLES, MADERA_IN5R_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 0,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 1,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 2,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 3,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 4,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX6", NULL, 5,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX7", NULL, 6,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX7_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX8", NULL, 7,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX8_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0,
MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX2", NULL, 1,
MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX3", NULL, 2,
MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX4", NULL, 3,
MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX5", NULL, 4,
MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX6", NULL, 5,
MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX7", NULL, 6,
MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX7_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX8", NULL, 7,
MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX8_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF3RX1", NULL, 0,
MADERA_AIF3_RX_ENABLES, MADERA_AIF3RX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF3RX2", NULL, 1,
MADERA_AIF3_RX_ENABLES, MADERA_AIF3RX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF4RX1", NULL, 0,
MADERA_AIF4_RX_ENABLES, MADERA_AIF4RX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF4RX2", NULL, 1,
MADERA_AIF4_RX_ENABLES, MADERA_AIF4RX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX1", NULL, 0, MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
MADERA_SLIMRX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX2", NULL, 1, MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
MADERA_SLIMRX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX3", NULL, 2, MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
MADERA_SLIMRX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX4", NULL, 3, MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
MADERA_SLIMRX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX5", NULL, 4, MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
MADERA_SLIMRX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX6", NULL, 5, MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
MADERA_SLIMRX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX7", NULL, 6, MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
MADERA_SLIMRX7_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX8", NULL, 7, MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
MADERA_SLIMRX8_ENA_SHIFT, 0),
SND_SOC_DAPM_PGA("EQ1", MADERA_EQ1_1, MADERA_EQ1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ2", MADERA_EQ2_1, MADERA_EQ2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ3", MADERA_EQ3_1, MADERA_EQ3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ4", MADERA_EQ4_1, MADERA_EQ4_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("DRC1L", MADERA_DRC1_CTRL1, MADERA_DRC1L_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("DRC1R", MADERA_DRC1_CTRL1, MADERA_DRC1R_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("DRC2L", MADERA_DRC2_CTRL1, MADERA_DRC2L_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("DRC2R", MADERA_DRC2_CTRL1, MADERA_DRC2R_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF1", MADERA_HPLPF1_1, MADERA_LHPF1_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF2", MADERA_HPLPF2_1, MADERA_LHPF2_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF3", MADERA_HPLPF3_1, MADERA_LHPF3_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF4", MADERA_HPLPF4_1, MADERA_LHPF4_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("ASRC1IN1L", MADERA_ASRC1_ENABLE,
MADERA_ASRC1_IN1L_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ASRC1IN1R", MADERA_ASRC1_ENABLE,
MADERA_ASRC1_IN1R_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ASRC1IN2L", MADERA_ASRC1_ENABLE,
MADERA_ASRC1_IN2L_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ASRC1IN2R", MADERA_ASRC1_ENABLE,
MADERA_ASRC1_IN2R_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ASRC2IN1L", MADERA_ASRC2_ENABLE,
MADERA_ASRC2_IN1L_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ASRC2IN1R", MADERA_ASRC2_ENABLE,
MADERA_ASRC2_IN1R_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ASRC2IN2L", MADERA_ASRC2_ENABLE,
MADERA_ASRC2_IN2L_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ASRC2IN2R", MADERA_ASRC2_ENABLE,
MADERA_ASRC2_IN2R_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC1", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_DEC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC2", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_DEC2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC3", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_DEC3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC4", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_DEC4_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1INT1", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_INT1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1INT2", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_INT2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1INT3", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_INT3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1INT4", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_INT4_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2DEC1", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_DEC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2DEC2", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_DEC2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2DEC3", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_DEC3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2DEC4", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_DEC4_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2INT1", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_INT1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2INT2", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_INT2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2INT3", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_INT3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2INT4", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_INT4_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC3DEC1", MADERA_ISRC_3_CTRL_3,
MADERA_ISRC3_DEC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC3DEC2", MADERA_ISRC_3_CTRL_3,
MADERA_ISRC3_DEC2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC3INT1", MADERA_ISRC_3_CTRL_3,
MADERA_ISRC3_INT1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC3INT2", MADERA_ISRC_3_CTRL_3,
MADERA_ISRC3_INT2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC4DEC1", MADERA_ISRC_4_CTRL_3,
MADERA_ISRC4_DEC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC4DEC2", MADERA_ISRC_4_CTRL_3,
MADERA_ISRC4_DEC2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC4INT1", MADERA_ISRC_4_CTRL_3,
MADERA_ISRC4_INT1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC4INT2", MADERA_ISRC_4_CTRL_3,
MADERA_ISRC4_INT2_ENA_SHIFT, 0, NULL, 0),
WM_ADSP2("DSP1", 0, cs47l90_adsp_power_ev),
WM_ADSP2("DSP2", 1, cs47l90_adsp_power_ev),
WM_ADSP2("DSP3", 2, cs47l90_adsp_power_ev),
WM_ADSP2("DSP4", 3, cs47l90_adsp_power_ev),
WM_ADSP2("DSP5", 4, cs47l90_adsp_power_ev),
WM_ADSP2("DSP6", 5, cs47l90_adsp_power_ev),
WM_ADSP2("DSP7", 6, cs47l90_adsp_power_ev),
/* end of ordered widget list */
SND_SOC_DAPM_PGA("DFC1", MADERA_DFC1_CTRL, MADERA_DFC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("DFC2", MADERA_DFC2_CTRL, MADERA_DFC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("DFC3", MADERA_DFC3_CTRL, MADERA_DFC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("DFC4", MADERA_DFC4_CTRL, MADERA_DFC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("DFC5", MADERA_DFC5_CTRL, MADERA_DFC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("DFC6", MADERA_DFC6_CTRL, MADERA_DFC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("DFC7", MADERA_DFC7_CTRL, MADERA_DFC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("DFC8", MADERA_DFC8_CTRL, MADERA_DFC1_ENA_SHIFT, 0, NULL, 0),
MADERA_MIXER_WIDGETS(EQ1, "EQ1"),
MADERA_MIXER_WIDGETS(EQ2, "EQ2"),
MADERA_MIXER_WIDGETS(EQ3, "EQ3"),
MADERA_MIXER_WIDGETS(EQ4, "EQ4"),
MADERA_MIXER_WIDGETS(DRC1L, "DRC1L"),
MADERA_MIXER_WIDGETS(DRC1R, "DRC1R"),
MADERA_MIXER_WIDGETS(DRC2L, "DRC2L"),
MADERA_MIXER_WIDGETS(DRC2R, "DRC2R"),
SND_SOC_DAPM_SWITCH("DRC1 Activity Output", SND_SOC_NOPM, 0, 0,
&madera_drc_activity_output_mux[0]),
SND_SOC_DAPM_SWITCH("DRC2 Activity Output", SND_SOC_NOPM, 0, 0,
&madera_drc_activity_output_mux[1]),
MADERA_MIXER_WIDGETS(LHPF1, "LHPF1"),
MADERA_MIXER_WIDGETS(LHPF2, "LHPF2"),
MADERA_MIXER_WIDGETS(LHPF3, "LHPF3"),
MADERA_MIXER_WIDGETS(LHPF4, "LHPF4"),
MADERA_MIXER_WIDGETS(PWM1, "PWM1"),
MADERA_MIXER_WIDGETS(PWM2, "PWM2"),
MADERA_MIXER_WIDGETS(OUT1L, "HPOUT1L"),
MADERA_MIXER_WIDGETS(OUT1R, "HPOUT1R"),
MADERA_MIXER_WIDGETS(OUT2L, "HPOUT2L"),
MADERA_MIXER_WIDGETS(OUT2R, "HPOUT2R"),
MADERA_MIXER_WIDGETS(OUT3L, "HPOUT3L"),
MADERA_MIXER_WIDGETS(OUT3R, "HPOUT3R"),
MADERA_MIXER_WIDGETS(SPKDAT1L, "SPKDAT1L"),
MADERA_MIXER_WIDGETS(SPKDAT1R, "SPKDAT1R"),
MADERA_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"),
MADERA_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"),
MADERA_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"),
MADERA_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"),
MADERA_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"),
MADERA_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"),
MADERA_MIXER_WIDGETS(AIF1TX7, "AIF1TX7"),
MADERA_MIXER_WIDGETS(AIF1TX8, "AIF1TX8"),
MADERA_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"),
MADERA_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"),
MADERA_MIXER_WIDGETS(AIF2TX3, "AIF2TX3"),
MADERA_MIXER_WIDGETS(AIF2TX4, "AIF2TX4"),
MADERA_MIXER_WIDGETS(AIF2TX5, "AIF2TX5"),
MADERA_MIXER_WIDGETS(AIF2TX6, "AIF2TX6"),
MADERA_MIXER_WIDGETS(AIF2TX7, "AIF2TX7"),
MADERA_MIXER_WIDGETS(AIF2TX8, "AIF2TX8"),
MADERA_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"),
MADERA_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"),
MADERA_MIXER_WIDGETS(AIF4TX1, "AIF4TX1"),
MADERA_MIXER_WIDGETS(AIF4TX2, "AIF4TX2"),
MADERA_MIXER_WIDGETS(SLIMTX1, "SLIMTX1"),
MADERA_MIXER_WIDGETS(SLIMTX2, "SLIMTX2"),
MADERA_MIXER_WIDGETS(SLIMTX3, "SLIMTX3"),
MADERA_MIXER_WIDGETS(SLIMTX4, "SLIMTX4"),
MADERA_MIXER_WIDGETS(SLIMTX5, "SLIMTX5"),
MADERA_MIXER_WIDGETS(SLIMTX6, "SLIMTX6"),
MADERA_MIXER_WIDGETS(SLIMTX7, "SLIMTX7"),
MADERA_MIXER_WIDGETS(SLIMTX8, "SLIMTX8"),
MADERA_MUX_WIDGETS(SPD1TX1, "SPDIF1TX1"),
MADERA_MUX_WIDGETS(SPD1TX2, "SPDIF1TX2"),
MADERA_MUX_WIDGETS(ASRC1IN1L, "ASRC1IN1L"),
MADERA_MUX_WIDGETS(ASRC1IN1R, "ASRC1IN1R"),
MADERA_MUX_WIDGETS(ASRC1IN2L, "ASRC1IN2L"),
MADERA_MUX_WIDGETS(ASRC1IN2R, "ASRC1IN2R"),
MADERA_MUX_WIDGETS(ASRC2IN1L, "ASRC2IN1L"),
MADERA_MUX_WIDGETS(ASRC2IN1R, "ASRC2IN1R"),
MADERA_MUX_WIDGETS(ASRC2IN2L, "ASRC2IN2L"),
MADERA_MUX_WIDGETS(ASRC2IN2R, "ASRC2IN2R"),
MADERA_DSP_WIDGETS(DSP1, "DSP1"),
MADERA_DSP_WIDGETS(DSP2, "DSP2"),
MADERA_DSP_WIDGETS(DSP3, "DSP3"),
MADERA_DSP_WIDGETS(DSP4, "DSP4"),
MADERA_DSP_WIDGETS(DSP5, "DSP5"),
MADERA_DSP_WIDGETS(DSP6, "DSP6"),
MADERA_DSP_WIDGETS(DSP7, "DSP7"),
SND_SOC_DAPM_SWITCH("DSP1 Trigger Output", SND_SOC_NOPM, 0, 0,
&madera_dsp_trigger_output_mux[0]),
SND_SOC_DAPM_SWITCH("DSP2 Trigger Output", SND_SOC_NOPM, 0, 0,
&madera_dsp_trigger_output_mux[1]),
SND_SOC_DAPM_SWITCH("DSP3 Trigger Output", SND_SOC_NOPM, 0, 0,
&madera_dsp_trigger_output_mux[2]),
SND_SOC_DAPM_SWITCH("DSP4 Trigger Output", SND_SOC_NOPM, 0, 0,
&madera_dsp_trigger_output_mux[3]),
SND_SOC_DAPM_SWITCH("DSP5 Trigger Output", SND_SOC_NOPM, 0, 0,
&madera_dsp_trigger_output_mux[4]),
SND_SOC_DAPM_SWITCH("DSP6 Trigger Output", SND_SOC_NOPM, 0, 0,
&madera_dsp_trigger_output_mux[5]),
SND_SOC_DAPM_SWITCH("DSP7 Trigger Output", SND_SOC_NOPM, 0, 0,
&madera_dsp_trigger_output_mux[6]),
MADERA_MUX_WIDGETS(ISRC1DEC1, "ISRC1DEC1"),
MADERA_MUX_WIDGETS(ISRC1DEC2, "ISRC1DEC2"),
MADERA_MUX_WIDGETS(ISRC1DEC3, "ISRC1DEC3"),
MADERA_MUX_WIDGETS(ISRC1DEC4, "ISRC1DEC4"),
MADERA_MUX_WIDGETS(ISRC1INT1, "ISRC1INT1"),
MADERA_MUX_WIDGETS(ISRC1INT2, "ISRC1INT2"),
MADERA_MUX_WIDGETS(ISRC1INT3, "ISRC1INT3"),
MADERA_MUX_WIDGETS(ISRC1INT4, "ISRC1INT4"),
MADERA_MUX_WIDGETS(ISRC2DEC1, "ISRC2DEC1"),
MADERA_MUX_WIDGETS(ISRC2DEC2, "ISRC2DEC2"),
MADERA_MUX_WIDGETS(ISRC2DEC3, "ISRC2DEC3"),
MADERA_MUX_WIDGETS(ISRC2DEC4, "ISRC2DEC4"),
MADERA_MUX_WIDGETS(ISRC2INT1, "ISRC2INT1"),
MADERA_MUX_WIDGETS(ISRC2INT2, "ISRC2INT2"),
MADERA_MUX_WIDGETS(ISRC2INT3, "ISRC2INT3"),
MADERA_MUX_WIDGETS(ISRC2INT4, "ISRC2INT4"),
MADERA_MUX_WIDGETS(ISRC3DEC1, "ISRC3DEC1"),
MADERA_MUX_WIDGETS(ISRC3DEC2, "ISRC3DEC2"),
MADERA_MUX_WIDGETS(ISRC3INT1, "ISRC3INT1"),
MADERA_MUX_WIDGETS(ISRC3INT2, "ISRC3INT2"),
MADERA_MUX_WIDGETS(ISRC4DEC1, "ISRC4DEC1"),
MADERA_MUX_WIDGETS(ISRC4DEC2, "ISRC4DEC2"),
MADERA_MUX_WIDGETS(ISRC4INT1, "ISRC4INT1"),
MADERA_MUX_WIDGETS(ISRC4INT2, "ISRC4INT2"),
MADERA_MUX_WIDGETS(DFC1, "DFC1"),
MADERA_MUX_WIDGETS(DFC2, "DFC2"),
MADERA_MUX_WIDGETS(DFC3, "DFC3"),
MADERA_MUX_WIDGETS(DFC4, "DFC4"),
MADERA_MUX_WIDGETS(DFC5, "DFC5"),
MADERA_MUX_WIDGETS(DFC6, "DFC6"),
MADERA_MUX_WIDGETS(DFC7, "DFC7"),
MADERA_MUX_WIDGETS(DFC8, "DFC8"),
SND_SOC_DAPM_OUTPUT("HPOUT1L"),
SND_SOC_DAPM_OUTPUT("HPOUT1R"),
SND_SOC_DAPM_OUTPUT("HPOUT2L"),
SND_SOC_DAPM_OUTPUT("HPOUT2R"),
SND_SOC_DAPM_OUTPUT("HPOUT3L"),
SND_SOC_DAPM_OUTPUT("HPOUT3R"),
SND_SOC_DAPM_OUTPUT("SPKDAT1L"),
SND_SOC_DAPM_OUTPUT("SPKDAT1R"),
SND_SOC_DAPM_OUTPUT("SPDIF1"),
SND_SOC_DAPM_OUTPUT("MICSUPP"),
};
#define MADERA_MIXER_INPUT_ROUTES(name) \
{ name, "Noise Generator", "Noise Generator" }, \
{ name, "Tone Generator 1", "Tone Generator 1" }, \
{ name, "Tone Generator 2", "Tone Generator 2" }, \
{ name, "Haptics", "HAPTICS" }, \
{ name, "AEC1", "AEC1 Loopback" }, \
{ name, "AEC2", "AEC2 Loopback" }, \
{ name, "IN1L", "IN1L" }, \
{ name, "IN1R", "IN1R" }, \
{ name, "IN2L", "IN2L" }, \
{ name, "IN2R", "IN2R" }, \
{ name, "IN3L", "IN3L" }, \
{ name, "IN3R", "IN3R" }, \
{ name, "IN4L", "IN4L" }, \
{ name, "IN4R", "IN4R" }, \
{ name, "IN5L", "IN5L" }, \
{ name, "IN5R", "IN5R" }, \
{ name, "AIF1RX1", "AIF1RX1" }, \
{ name, "AIF1RX2", "AIF1RX2" }, \
{ name, "AIF1RX3", "AIF1RX3" }, \
{ name, "AIF1RX4", "AIF1RX4" }, \
{ name, "AIF1RX5", "AIF1RX5" }, \
{ name, "AIF1RX6", "AIF1RX6" }, \
{ name, "AIF1RX7", "AIF1RX7" }, \
{ name, "AIF1RX8", "AIF1RX8" }, \
{ name, "AIF2RX1", "AIF2RX1" }, \
{ name, "AIF2RX2", "AIF2RX2" }, \
{ name, "AIF2RX3", "AIF2RX3" }, \
{ name, "AIF2RX4", "AIF2RX4" }, \
{ name, "AIF2RX5", "AIF2RX5" }, \
{ name, "AIF2RX6", "AIF2RX6" }, \
{ name, "AIF2RX7", "AIF2RX7" }, \
{ name, "AIF2RX8", "AIF2RX8" }, \
{ name, "AIF3RX1", "AIF3RX1" }, \
{ name, "AIF3RX2", "AIF3RX2" }, \
{ name, "AIF4RX1", "AIF4RX1" }, \
{ name, "AIF4RX2", "AIF4RX2" }, \
{ name, "SLIMRX1", "SLIMRX1" }, \
{ name, "SLIMRX2", "SLIMRX2" }, \
{ name, "SLIMRX3", "SLIMRX3" }, \
{ name, "SLIMRX4", "SLIMRX4" }, \
{ name, "SLIMRX5", "SLIMRX5" }, \
{ name, "SLIMRX6", "SLIMRX6" }, \
{ name, "SLIMRX7", "SLIMRX7" }, \
{ name, "SLIMRX8", "SLIMRX8" }, \
{ name, "EQ1", "EQ1" }, \
{ name, "EQ2", "EQ2" }, \
{ name, "EQ3", "EQ3" }, \
{ name, "EQ4", "EQ4" }, \
{ name, "DRC1L", "DRC1L" }, \
{ name, "DRC1R", "DRC1R" }, \
{ name, "DRC2L", "DRC2L" }, \
{ name, "DRC2R", "DRC2R" }, \
{ name, "LHPF1", "LHPF1" }, \
{ name, "LHPF2", "LHPF2" }, \
{ name, "LHPF3", "LHPF3" }, \
{ name, "LHPF4", "LHPF4" }, \
{ name, "ASRC1IN1L", "ASRC1IN1L" }, \
{ name, "ASRC1IN1R", "ASRC1IN1R" }, \
{ name, "ASRC1IN2L", "ASRC1IN2L" }, \
{ name, "ASRC1IN2R", "ASRC1IN2R" }, \
{ name, "ASRC2IN1L", "ASRC2IN1L" }, \
{ name, "ASRC2IN1R", "ASRC2IN1R" }, \
{ name, "ASRC2IN2L", "ASRC2IN2L" }, \
{ name, "ASRC2IN2R", "ASRC2IN2R" }, \
{ name, "ISRC1DEC1", "ISRC1DEC1" }, \
{ name, "ISRC1DEC2", "ISRC1DEC2" }, \
{ name, "ISRC1DEC3", "ISRC1DEC3" }, \
{ name, "ISRC1DEC4", "ISRC1DEC4" }, \
{ name, "ISRC1INT1", "ISRC1INT1" }, \
{ name, "ISRC1INT2", "ISRC1INT2" }, \
{ name, "ISRC1INT3", "ISRC1INT3" }, \
{ name, "ISRC1INT4", "ISRC1INT4" }, \
{ name, "ISRC2DEC1", "ISRC2DEC1" }, \
{ name, "ISRC2DEC2", "ISRC2DEC2" }, \
{ name, "ISRC2DEC3", "ISRC2DEC3" }, \
{ name, "ISRC2DEC4", "ISRC2DEC4" }, \
{ name, "ISRC2INT1", "ISRC2INT1" }, \
{ name, "ISRC2INT2", "ISRC2INT2" }, \
{ name, "ISRC2INT3", "ISRC2INT3" }, \
{ name, "ISRC2INT4", "ISRC2INT4" }, \
{ name, "ISRC3DEC1", "ISRC3DEC1" }, \
{ name, "ISRC3DEC2", "ISRC3DEC2" }, \
{ name, "ISRC3INT1", "ISRC3INT1" }, \
{ name, "ISRC3INT2", "ISRC3INT2" }, \
{ name, "ISRC4DEC1", "ISRC4DEC1" }, \
{ name, "ISRC4DEC2", "ISRC4DEC2" }, \
{ name, "ISRC4INT1", "ISRC4INT1" }, \
{ name, "ISRC4INT2", "ISRC4INT2" }, \
{ name, "DSP1.1", "DSP1" }, \
{ name, "DSP1.2", "DSP1" }, \
{ name, "DSP1.3", "DSP1" }, \
{ name, "DSP1.4", "DSP1" }, \
{ name, "DSP1.5", "DSP1" }, \
{ name, "DSP1.6", "DSP1" }, \
{ name, "DSP2.1", "DSP2" }, \
{ name, "DSP2.2", "DSP2" }, \
{ name, "DSP2.3", "DSP2" }, \
{ name, "DSP2.4", "DSP2" }, \
{ name, "DSP2.5", "DSP2" }, \
{ name, "DSP2.6", "DSP2" }, \
{ name, "DSP3.1", "DSP3" }, \
{ name, "DSP3.2", "DSP3" }, \
{ name, "DSP3.3", "DSP3" }, \
{ name, "DSP3.4", "DSP3" }, \
{ name, "DSP3.5", "DSP3" }, \
{ name, "DSP3.6", "DSP3" }, \
{ name, "DSP4.1", "DSP4" }, \
{ name, "DSP4.2", "DSP4" }, \
{ name, "DSP4.3", "DSP4" }, \
{ name, "DSP4.4", "DSP4" }, \
{ name, "DSP4.5", "DSP4" }, \
{ name, "DSP4.6", "DSP4" }, \
{ name, "DSP5.1", "DSP5" }, \
{ name, "DSP5.2", "DSP5" }, \
{ name, "DSP5.3", "DSP5" }, \
{ name, "DSP5.4", "DSP5" }, \
{ name, "DSP5.5", "DSP5" }, \
{ name, "DSP5.6", "DSP5" }, \
{ name, "DSP6.1", "DSP6" }, \
{ name, "DSP6.2", "DSP6" }, \
{ name, "DSP6.3", "DSP6" }, \
{ name, "DSP6.4", "DSP6" }, \
{ name, "DSP6.5", "DSP6" }, \
{ name, "DSP6.6", "DSP6" }, \
{ name, "DSP7.1", "DSP7" }, \
{ name, "DSP7.2", "DSP7" }, \
{ name, "DSP7.3", "DSP7" }, \
{ name, "DSP7.4", "DSP7" }, \
{ name, "DSP7.5", "DSP7" }, \
{ name, "DSP7.6", "DSP7" }, \
{ name, "DFC1", "DFC1" }, \
{ name, "DFC2", "DFC2" }, \
{ name, "DFC3", "DFC3" }, \
{ name, "DFC4", "DFC4" }, \
{ name, "DFC5", "DFC5" }, \
{ name, "DFC6", "DFC6" }, \
{ name, "DFC7", "DFC7" }, \
{ name, "DFC8", "DFC8" }
static const struct snd_soc_dapm_route cs47l90_dapm_routes[] = {
/* Internal clock domains */
{ "EQ1", NULL, "FXCLK" },
{ "EQ2", NULL, "FXCLK" },
{ "EQ3", NULL, "FXCLK" },
{ "EQ4", NULL, "FXCLK" },
{ "DRC1L", NULL, "FXCLK" },
{ "DRC1R", NULL, "FXCLK" },
{ "DRC2L", NULL, "FXCLK" },
{ "DRC2R", NULL, "FXCLK" },
{ "LHPF1", NULL, "FXCLK" },
{ "LHPF2", NULL, "FXCLK" },
{ "LHPF3", NULL, "FXCLK" },
{ "LHPF4", NULL, "FXCLK" },
{ "PWM1 Mixer", NULL, "PWMCLK" },
{ "PWM2 Mixer", NULL, "PWMCLK" },
{ "OUT1L", NULL, "OUTCLK" },
{ "OUT1R", NULL, "OUTCLK" },
{ "OUT2L", NULL, "OUTCLK" },
{ "OUT2R", NULL, "OUTCLK" },
{ "OUT3L", NULL, "OUTCLK" },
{ "OUT3R", NULL, "OUTCLK" },
{ "OUT5L", NULL, "OUTCLK" },
{ "OUT5R", NULL, "OUTCLK" },
{ "AIF1TX1", NULL, "AIF1TXCLK" },
{ "AIF1TX2", NULL, "AIF1TXCLK" },
{ "AIF1TX3", NULL, "AIF1TXCLK" },
{ "AIF1TX4", NULL, "AIF1TXCLK" },
{ "AIF1TX5", NULL, "AIF1TXCLK" },
{ "AIF1TX6", NULL, "AIF1TXCLK" },
{ "AIF1TX7", NULL, "AIF1TXCLK" },
{ "AIF1TX8", NULL, "AIF1TXCLK" },
{ "AIF2TX1", NULL, "AIF2TXCLK" },
{ "AIF2TX2", NULL, "AIF2TXCLK" },
{ "AIF2TX3", NULL, "AIF2TXCLK" },
{ "AIF2TX4", NULL, "AIF2TXCLK" },
{ "AIF2TX5", NULL, "AIF2TXCLK" },
{ "AIF2TX6", NULL, "AIF2TXCLK" },
{ "AIF2TX7", NULL, "AIF2TXCLK" },
{ "AIF2TX8", NULL, "AIF2TXCLK" },
{ "AIF3TX1", NULL, "AIF3TXCLK" },
{ "AIF3TX2", NULL, "AIF3TXCLK" },
{ "AIF4TX1", NULL, "AIF4TXCLK" },
{ "AIF4TX2", NULL, "AIF4TXCLK" },
{ "SLIMTX1", NULL, "SLIMBUSCLK" },
{ "SLIMTX2", NULL, "SLIMBUSCLK" },
{ "SLIMTX3", NULL, "SLIMBUSCLK" },
{ "SLIMTX4", NULL, "SLIMBUSCLK" },
{ "SLIMTX5", NULL, "SLIMBUSCLK" },
{ "SLIMTX6", NULL, "SLIMBUSCLK" },
{ "SLIMTX7", NULL, "SLIMBUSCLK" },
{ "SLIMTX8", NULL, "SLIMBUSCLK" },
{ "SPD1TX1", NULL, "SPDCLK" },
{ "SPD1TX2", NULL, "SPDCLK" },
{ "DSP1", NULL, "DSP1CLK" },
{ "DSP2", NULL, "DSP2CLK" },
{ "DSP3", NULL, "DSP3CLK" },
{ "DSP4", NULL, "DSP4CLK" },
{ "DSP5", NULL, "DSP5CLK" },
{ "DSP6", NULL, "DSP6CLK" },
{ "DSP7", NULL, "DSP7CLK" },
{ "ISRC1DEC1", NULL, "ISRC1CLK" },
{ "ISRC1DEC2", NULL, "ISRC1CLK" },
{ "ISRC1DEC3", NULL, "ISRC1CLK" },
{ "ISRC1DEC4", NULL, "ISRC1CLK" },
{ "ISRC1INT1", NULL, "ISRC1CLK" },
{ "ISRC1INT2", NULL, "ISRC1CLK" },
{ "ISRC1INT3", NULL, "ISRC1CLK" },
{ "ISRC1INT4", NULL, "ISRC1CLK" },
{ "ISRC2DEC1", NULL, "ISRC2CLK" },
{ "ISRC2DEC2", NULL, "ISRC2CLK" },
{ "ISRC2DEC3", NULL, "ISRC2CLK" },
{ "ISRC2DEC4", NULL, "ISRC2CLK" },
{ "ISRC2INT1", NULL, "ISRC2CLK" },
{ "ISRC2INT2", NULL, "ISRC2CLK" },
{ "ISRC2INT3", NULL, "ISRC2CLK" },
{ "ISRC2INT4", NULL, "ISRC2CLK" },
{ "ISRC3DEC1", NULL, "ISRC3CLK" },
{ "ISRC3DEC2", NULL, "ISRC3CLK" },
{ "ISRC3INT1", NULL, "ISRC3CLK" },
{ "ISRC3INT2", NULL, "ISRC3CLK" },
{ "ISRC4DEC1", NULL, "ISRC4CLK" },
{ "ISRC4DEC2", NULL, "ISRC4CLK" },
{ "ISRC4INT1", NULL, "ISRC4CLK" },
{ "ISRC4INT2", NULL, "ISRC4CLK" },
{ "ASRC1IN1L", NULL, "ASRC1CLK" },
{ "ASRC1IN1R", NULL, "ASRC1CLK" },
{ "ASRC1IN2L", NULL, "ASRC1CLK" },
{ "ASRC1IN2R", NULL, "ASRC1CLK" },
{ "ASRC2IN1L", NULL, "ASRC2CLK" },
{ "ASRC2IN1R", NULL, "ASRC2CLK" },
{ "ASRC2IN2L", NULL, "ASRC2CLK" },
{ "ASRC2IN2R", NULL, "ASRC2CLK" },
{ "DFC1", NULL, "DFCCLK" },
{ "DFC2", NULL, "DFCCLK" },
{ "DFC3", NULL, "DFCCLK" },
{ "DFC4", NULL, "DFCCLK" },
{ "DFC5", NULL, "DFCCLK" },
{ "DFC6", NULL, "DFCCLK" },
{ "DFC7", NULL, "DFCCLK" },
{ "DFC8", NULL, "DFCCLK" },
{ "AIF2 Capture", NULL, "DBVDD2" },
{ "AIF2 Playback", NULL, "DBVDD2" },
{ "AIF3 Capture", NULL, "DBVDD3" },
{ "AIF3 Playback", NULL, "DBVDD3" },
{ "AIF4 Capture", NULL, "DBVDD3" },
{ "AIF4 Playback", NULL, "DBVDD3" },
{ "OUT1L", NULL, "CPVDD1" },
{ "OUT1L", NULL, "CPVDD2" },
{ "OUT1R", NULL, "CPVDD1" },
{ "OUT1R", NULL, "CPVDD2" },
{ "OUT2L", NULL, "CPVDD1" },
{ "OUT2L", NULL, "CPVDD2" },
{ "OUT2R", NULL, "CPVDD1" },
{ "OUT2R", NULL, "CPVDD2" },
{ "OUT3L", NULL, "CPVDD1" },
{ "OUT3L", NULL, "CPVDD2" },
{ "OUT3R", NULL, "CPVDD1" },
{ "OUT3R", NULL, "CPVDD2" },
{ "OUT1L", NULL, "SYSCLK" },
{ "OUT1R", NULL, "SYSCLK" },
{ "OUT2L", NULL, "SYSCLK" },
{ "OUT2R", NULL, "SYSCLK" },
{ "OUT3L", NULL, "SYSCLK" },
{ "OUT3R", NULL, "SYSCLK" },
{ "OUT5L", NULL, "SYSCLK" },
{ "OUT5R", NULL, "SYSCLK" },
{ "SPD1", NULL, "SYSCLK" },
{ "SPD1", NULL, "SPD1TX1" },
{ "SPD1", NULL, "SPD1TX2" },
{ "IN1L", NULL, "SYSCLK" },
{ "IN1R", NULL, "SYSCLK" },
{ "IN2L", NULL, "SYSCLK" },
{ "IN2R", NULL, "SYSCLK" },
{ "IN3L", NULL, "SYSCLK" },
{ "IN3R", NULL, "SYSCLK" },
{ "IN4L", NULL, "SYSCLK" },
{ "IN4R", NULL, "SYSCLK" },
{ "IN5L", NULL, "SYSCLK" },
{ "IN5R", NULL, "SYSCLK" },
{ "IN3L", NULL, "DBVDD4" },
{ "IN3R", NULL, "DBVDD4" },
{ "IN4L", NULL, "DBVDD4" },
{ "IN4R", NULL, "DBVDD4" },
{ "IN5L", NULL, "DBVDD4" },
{ "IN5R", NULL, "DBVDD4" },
{ "ASRC1IN1L", NULL, "SYSCLK" },
{ "ASRC1IN1R", NULL, "SYSCLK" },
{ "ASRC1IN2L", NULL, "SYSCLK" },
{ "ASRC1IN2R", NULL, "SYSCLK" },
{ "ASRC2IN1L", NULL, "SYSCLK" },
{ "ASRC2IN1R", NULL, "SYSCLK" },
{ "ASRC2IN2L", NULL, "SYSCLK" },
{ "ASRC2IN2R", NULL, "SYSCLK" },
{ "ASRC1IN1L", NULL, "ASYNCCLK" },
{ "ASRC1IN1R", NULL, "ASYNCCLK" },
{ "ASRC1IN2L", NULL, "ASYNCCLK" },
{ "ASRC1IN2R", NULL, "ASYNCCLK" },
{ "ASRC2IN1L", NULL, "ASYNCCLK" },
{ "ASRC2IN1R", NULL, "ASYNCCLK" },
{ "ASRC2IN2L", NULL, "ASYNCCLK" },
{ "ASRC2IN2R", NULL, "ASYNCCLK" },
{ "MICBIAS1", NULL, "MICVDD" },
{ "MICBIAS2", NULL, "MICVDD" },
{ "MICBIAS1A", NULL, "MICBIAS1" },
{ "MICBIAS1B", NULL, "MICBIAS1" },
{ "MICBIAS1C", NULL, "MICBIAS1" },
{ "MICBIAS1D", NULL, "MICBIAS1" },
{ "MICBIAS2A", NULL, "MICBIAS2" },
{ "MICBIAS2B", NULL, "MICBIAS2" },
{ "MICBIAS2C", NULL, "MICBIAS2" },
{ "MICBIAS2D", NULL, "MICBIAS2" },
{ "Noise Generator", NULL, "SYSCLK" },
{ "Tone Generator 1", NULL, "SYSCLK" },
{ "Tone Generator 2", NULL, "SYSCLK" },
{ "Noise Generator", NULL, "NOISE" },
{ "Tone Generator 1", NULL, "TONE" },
{ "Tone Generator 2", NULL, "TONE" },
{ "AIF1 Capture", NULL, "AIF1TX1" },
{ "AIF1 Capture", NULL, "AIF1TX2" },
{ "AIF1 Capture", NULL, "AIF1TX3" },
{ "AIF1 Capture", NULL, "AIF1TX4" },
{ "AIF1 Capture", NULL, "AIF1TX5" },
{ "AIF1 Capture", NULL, "AIF1TX6" },
{ "AIF1 Capture", NULL, "AIF1TX7" },
{ "AIF1 Capture", NULL, "AIF1TX8" },
{ "AIF1RX1", NULL, "AIF1 Playback" },
{ "AIF1RX2", NULL, "AIF1 Playback" },
{ "AIF1RX3", NULL, "AIF1 Playback" },
{ "AIF1RX4", NULL, "AIF1 Playback" },
{ "AIF1RX5", NULL, "AIF1 Playback" },
{ "AIF1RX6", NULL, "AIF1 Playback" },
{ "AIF1RX7", NULL, "AIF1 Playback" },
{ "AIF1RX8", NULL, "AIF1 Playback" },
{ "AIF2 Capture", NULL, "AIF2TX1" },
{ "AIF2 Capture", NULL, "AIF2TX2" },
{ "AIF2 Capture", NULL, "AIF2TX3" },
{ "AIF2 Capture", NULL, "AIF2TX4" },
{ "AIF2 Capture", NULL, "AIF2TX5" },
{ "AIF2 Capture", NULL, "AIF2TX6" },
{ "AIF2 Capture", NULL, "AIF2TX7" },
{ "AIF2 Capture", NULL, "AIF2TX8" },
{ "AIF2RX1", NULL, "AIF2 Playback" },
{ "AIF2RX2", NULL, "AIF2 Playback" },
{ "AIF2RX3", NULL, "AIF2 Playback" },
{ "AIF2RX4", NULL, "AIF2 Playback" },
{ "AIF2RX5", NULL, "AIF2 Playback" },
{ "AIF2RX6", NULL, "AIF2 Playback" },
{ "AIF2RX7", NULL, "AIF2 Playback" },
{ "AIF2RX8", NULL, "AIF2 Playback" },
{ "AIF3 Capture", NULL, "AIF3TX1" },
{ "AIF3 Capture", NULL, "AIF3TX2" },
{ "AIF3RX1", NULL, "AIF3 Playback" },
{ "AIF3RX2", NULL, "AIF3 Playback" },
{ "AIF4 Capture", NULL, "AIF4TX1" },
{ "AIF4 Capture", NULL, "AIF4TX2" },
{ "AIF4RX1", NULL, "AIF4 Playback" },
{ "AIF4RX2", NULL, "AIF4 Playback" },
{ "Slim1 Capture", NULL, "SLIMTX1" },
{ "Slim1 Capture", NULL, "SLIMTX2" },
{ "Slim1 Capture", NULL, "SLIMTX3" },
{ "Slim1 Capture", NULL, "SLIMTX4" },
{ "SLIMRX1", NULL, "Slim1 Playback" },
{ "SLIMRX2", NULL, "Slim1 Playback" },
{ "SLIMRX3", NULL, "Slim1 Playback" },
{ "SLIMRX4", NULL, "Slim1 Playback" },
{ "Slim2 Capture", NULL, "SLIMTX5" },
{ "Slim2 Capture", NULL, "SLIMTX6" },
{ "SLIMRX5", NULL, "Slim2 Playback" },
{ "SLIMRX6", NULL, "Slim2 Playback" },
{ "Slim3 Capture", NULL, "SLIMTX7" },
{ "Slim3 Capture", NULL, "SLIMTX8" },
{ "SLIMRX7", NULL, "Slim3 Playback" },
{ "SLIMRX8", NULL, "Slim3 Playback" },
{ "AIF1 Playback", NULL, "SYSCLK" },
{ "AIF2 Playback", NULL, "SYSCLK" },
{ "AIF3 Playback", NULL, "SYSCLK" },
{ "AIF4 Playback", NULL, "SYSCLK" },
{ "Slim1 Playback", NULL, "SYSCLK" },
{ "Slim2 Playback", NULL, "SYSCLK" },
{ "Slim3 Playback", NULL, "SYSCLK" },
{ "AIF1 Capture", NULL, "SYSCLK" },
{ "AIF2 Capture", NULL, "SYSCLK" },
{ "AIF3 Capture", NULL, "SYSCLK" },
{ "AIF4 Capture", NULL, "SYSCLK" },
{ "Slim1 Capture", NULL, "SYSCLK" },
{ "Slim2 Capture", NULL, "SYSCLK" },
{ "Slim3 Capture", NULL, "SYSCLK" },
{ "Voice Control DSP", NULL, "DSP6" },
{ "Audio Trace DSP", NULL, "DSP1" },
{ "IN1L Analog Mux", "A", "IN1ALN" },
{ "IN1L Analog Mux", "A", "IN1ALP" },
{ "IN1L Analog Mux", "B", "IN1BLN" },
{ "IN1L Analog Mux", "B", "IN1BLP" },
{ "IN1R Analog Mux", "A", "IN1ARN" },
{ "IN1R Analog Mux", "A", "IN1ARP" },
{ "IN1R Analog Mux", "B", "IN1BRN" },
{ "IN1R Analog Mux", "B", "IN1BRP" },
{ "IN1L Mode", "Analog", "IN1L Analog Mux" },
{ "IN1R Mode", "Analog", "IN1R Analog Mux" },
{ "IN1L Mode", "Digital", "IN1ARN" },
{ "IN1L Mode", "Digital", "IN1ARP" },
{ "IN1R Mode", "Digital", "IN1ARN" },
{ "IN1R Mode", "Digital", "IN1ARP" },
{ "IN1L", NULL, "IN1L Mode" },
{ "IN1R", NULL, "IN1R Mode" },
{ "IN2L Analog Mux", "A", "IN2ALN" },
{ "IN2L Analog Mux", "A", "IN2ALP" },
{ "IN2L Analog Mux", "B", "IN2BLN" },
{ "IN2L Analog Mux", "B", "IN2BLP" },
{ "IN2L Mode", "Analog", "IN2L Analog Mux" },
{ "IN2R Mode", "Analog", "IN2RN" },
{ "IN2R Mode", "Analog", "IN2RP" },
{ "IN2L Mode", "Digital", "IN2ALN" },
{ "IN2L Mode", "Digital", "IN2ALP" },
{ "IN2R Mode", "Digital", "IN2ALN" },
{ "IN2R Mode", "Digital", "IN2ALP" },
{ "IN2L", NULL, "IN2L Mode" },
{ "IN2R", NULL, "IN2R Mode" },
{ "IN3L", NULL, "DMICCLK3" },
{ "IN3L", NULL, "DMICDAT3" },
{ "IN3R", NULL, "DMICCLK3" },
{ "IN3R", NULL, "DMICDAT3" },
{ "IN4L", NULL, "DMICCLK4" },
{ "IN4L", NULL, "DMICDAT4" },
{ "IN4R", NULL, "DMICCLK4" },
{ "IN4R", NULL, "DMICDAT4" },
{ "IN5L", NULL, "DMICCLK5" },
{ "IN5L", NULL, "DMICDAT5" },
{ "IN5R", NULL, "DMICCLK5" },
{ "IN5R", NULL, "DMICDAT5" },
MADERA_MIXER_ROUTES("OUT1L", "HPOUT1L"),
MADERA_MIXER_ROUTES("OUT1R", "HPOUT1R"),
MADERA_MIXER_ROUTES("OUT2L", "HPOUT2L"),
MADERA_MIXER_ROUTES("OUT2R", "HPOUT2R"),
MADERA_MIXER_ROUTES("OUT3L", "HPOUT3L"),
MADERA_MIXER_ROUTES("OUT3R", "HPOUT3R"),
MADERA_MIXER_ROUTES("OUT5L", "SPKDAT1L"),
MADERA_MIXER_ROUTES("OUT5R", "SPKDAT1R"),
MADERA_MIXER_ROUTES("PWM1 Driver", "PWM1"),
MADERA_MIXER_ROUTES("PWM2 Driver", "PWM2"),
MADERA_MIXER_ROUTES("AIF1TX1", "AIF1TX1"),
MADERA_MIXER_ROUTES("AIF1TX2", "AIF1TX2"),
MADERA_MIXER_ROUTES("AIF1TX3", "AIF1TX3"),
MADERA_MIXER_ROUTES("AIF1TX4", "AIF1TX4"),
MADERA_MIXER_ROUTES("AIF1TX5", "AIF1TX5"),
MADERA_MIXER_ROUTES("AIF1TX6", "AIF1TX6"),
MADERA_MIXER_ROUTES("AIF1TX7", "AIF1TX7"),
MADERA_MIXER_ROUTES("AIF1TX8", "AIF1TX8"),
MADERA_MIXER_ROUTES("AIF2TX1", "AIF2TX1"),
MADERA_MIXER_ROUTES("AIF2TX2", "AIF2TX2"),
MADERA_MIXER_ROUTES("AIF2TX3", "AIF2TX3"),
MADERA_MIXER_ROUTES("AIF2TX4", "AIF2TX4"),
MADERA_MIXER_ROUTES("AIF2TX5", "AIF2TX5"),
MADERA_MIXER_ROUTES("AIF2TX6", "AIF2TX6"),
MADERA_MIXER_ROUTES("AIF2TX7", "AIF2TX7"),
MADERA_MIXER_ROUTES("AIF2TX8", "AIF2TX8"),
MADERA_MIXER_ROUTES("AIF3TX1", "AIF3TX1"),
MADERA_MIXER_ROUTES("AIF3TX2", "AIF3TX2"),
MADERA_MIXER_ROUTES("AIF4TX1", "AIF4TX1"),
MADERA_MIXER_ROUTES("AIF4TX2", "AIF4TX2"),
MADERA_MIXER_ROUTES("SLIMTX1", "SLIMTX1"),
MADERA_MIXER_ROUTES("SLIMTX2", "SLIMTX2"),
MADERA_MIXER_ROUTES("SLIMTX3", "SLIMTX3"),
MADERA_MIXER_ROUTES("SLIMTX4", "SLIMTX4"),
MADERA_MIXER_ROUTES("SLIMTX5", "SLIMTX5"),
MADERA_MIXER_ROUTES("SLIMTX6", "SLIMTX6"),
MADERA_MIXER_ROUTES("SLIMTX7", "SLIMTX7"),
MADERA_MIXER_ROUTES("SLIMTX8", "SLIMTX8"),
MADERA_MUX_ROUTES("SPD1TX1", "SPDIF1TX1"),
MADERA_MUX_ROUTES("SPD1TX2", "SPDIF1TX2"),
MADERA_MIXER_ROUTES("EQ1", "EQ1"),
MADERA_MIXER_ROUTES("EQ2", "EQ2"),
MADERA_MIXER_ROUTES("EQ3", "EQ3"),
MADERA_MIXER_ROUTES("EQ4", "EQ4"),
MADERA_MIXER_ROUTES("DRC1L", "DRC1L"),
MADERA_MIXER_ROUTES("DRC1R", "DRC1R"),
MADERA_MIXER_ROUTES("DRC2L", "DRC2L"),
MADERA_MIXER_ROUTES("DRC2R", "DRC2R"),
MADERA_MIXER_ROUTES("LHPF1", "LHPF1"),
MADERA_MIXER_ROUTES("LHPF2", "LHPF2"),
MADERA_MIXER_ROUTES("LHPF3", "LHPF3"),
MADERA_MIXER_ROUTES("LHPF4", "LHPF4"),
MADERA_MUX_ROUTES("ASRC1IN1L", "ASRC1IN1L"),
MADERA_MUX_ROUTES("ASRC1IN1R", "ASRC1IN1R"),
MADERA_MUX_ROUTES("ASRC1IN2L", "ASRC1IN2L"),
MADERA_MUX_ROUTES("ASRC1IN2R", "ASRC1IN2R"),
MADERA_MUX_ROUTES("ASRC2IN1L", "ASRC2IN1L"),
MADERA_MUX_ROUTES("ASRC2IN1R", "ASRC2IN1R"),
MADERA_MUX_ROUTES("ASRC2IN2L", "ASRC2IN2L"),
MADERA_MUX_ROUTES("ASRC2IN2R", "ASRC2IN2R"),
MADERA_DSP_ROUTES("DSP1"),
MADERA_DSP_ROUTES("DSP2"),
MADERA_DSP_ROUTES("DSP3"),
MADERA_DSP_ROUTES("DSP4"),
MADERA_DSP_ROUTES("DSP5"),
MADERA_DSP_ROUTES("DSP6"),
MADERA_DSP_ROUTES("DSP7"),
{ "DSP Trigger Out", NULL, "DSP1 Trigger Output" },
{ "DSP Trigger Out", NULL, "DSP2 Trigger Output" },
{ "DSP Trigger Out", NULL, "DSP3 Trigger Output" },
{ "DSP Trigger Out", NULL, "DSP4 Trigger Output" },
{ "DSP Trigger Out", NULL, "DSP5 Trigger Output" },
{ "DSP Trigger Out", NULL, "DSP6 Trigger Output" },
{ "DSP Trigger Out", NULL, "DSP7 Trigger Output" },
{ "DSP1 Trigger Output", "Switch", "DSP1" },
{ "DSP2 Trigger Output", "Switch", "DSP2" },
{ "DSP3 Trigger Output", "Switch", "DSP3" },
{ "DSP4 Trigger Output", "Switch", "DSP4" },
{ "DSP5 Trigger Output", "Switch", "DSP5" },
{ "DSP6 Trigger Output", "Switch", "DSP6" },
{ "DSP7 Trigger Output", "Switch", "DSP7" },
MADERA_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"),
MADERA_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"),
MADERA_MUX_ROUTES("ISRC1INT3", "ISRC1INT3"),
MADERA_MUX_ROUTES("ISRC1INT4", "ISRC1INT4"),
MADERA_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"),
MADERA_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"),
MADERA_MUX_ROUTES("ISRC1DEC3", "ISRC1DEC3"),
MADERA_MUX_ROUTES("ISRC1DEC4", "ISRC1DEC4"),
MADERA_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"),
MADERA_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"),
MADERA_MUX_ROUTES("ISRC2INT3", "ISRC2INT3"),
MADERA_MUX_ROUTES("ISRC2INT4", "ISRC2INT4"),
MADERA_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"),
MADERA_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"),
MADERA_MUX_ROUTES("ISRC2DEC3", "ISRC2DEC3"),
MADERA_MUX_ROUTES("ISRC2DEC4", "ISRC2DEC4"),
MADERA_MUX_ROUTES("ISRC3INT1", "ISRC3INT1"),
MADERA_MUX_ROUTES("ISRC3INT2", "ISRC3INT2"),
MADERA_MUX_ROUTES("ISRC3DEC1", "ISRC3DEC1"),
MADERA_MUX_ROUTES("ISRC3DEC2", "ISRC3DEC2"),
MADERA_MUX_ROUTES("ISRC4INT1", "ISRC4INT1"),
MADERA_MUX_ROUTES("ISRC4INT2", "ISRC4INT2"),
MADERA_MUX_ROUTES("ISRC4DEC1", "ISRC4DEC1"),
MADERA_MUX_ROUTES("ISRC4DEC2", "ISRC4DEC2"),
{ "AEC1 Loopback", "HPOUT1L", "OUT1L" },
{ "AEC1 Loopback", "HPOUT1R", "OUT1R" },
{ "AEC2 Loopback", "HPOUT1L", "OUT1L" },
{ "AEC2 Loopback", "HPOUT1R", "OUT1R" },
{ "HPOUT1L", NULL, "OUT1L" },
{ "HPOUT1R", NULL, "OUT1R" },
{ "AEC1 Loopback", "HPOUT2L", "OUT2L" },
{ "AEC1 Loopback", "HPOUT2R", "OUT2R" },
{ "AEC2 Loopback", "HPOUT2L", "OUT2L" },
{ "AEC2 Loopback", "HPOUT2R", "OUT2R" },
{ "HPOUT2L", NULL, "OUT2L" },
{ "HPOUT2R", NULL, "OUT2R" },
{ "AEC1 Loopback", "HPOUT3L", "OUT3L" },
{ "AEC1 Loopback", "HPOUT3R", "OUT3R" },
{ "AEC2 Loopback", "HPOUT3L", "OUT3L" },
{ "AEC2 Loopback", "HPOUT3R", "OUT3R" },
{ "HPOUT3L", NULL, "OUT3L" },
{ "HPOUT3R", NULL, "OUT3R" },
{ "AEC1 Loopback", "SPKDAT1L", "OUT5L" },
{ "AEC1 Loopback", "SPKDAT1R", "OUT5R" },
{ "AEC2 Loopback", "SPKDAT1L", "OUT5L" },
{ "AEC2 Loopback", "SPKDAT1R", "OUT5R" },
{ "SPKDAT1L", NULL, "OUT5L" },
{ "SPKDAT1R", NULL, "OUT5R" },
CS47L90_RXANC_INPUT_ROUTES("RXANCL", "RXANCL"),
CS47L90_RXANC_INPUT_ROUTES("RXANCR", "RXANCR"),
CS47L90_RXANC_OUTPUT_ROUTES("OUT1L", "HPOUT1L"),
CS47L90_RXANC_OUTPUT_ROUTES("OUT1R", "HPOUT1R"),
CS47L90_RXANC_OUTPUT_ROUTES("OUT2L", "HPOUT2L"),
CS47L90_RXANC_OUTPUT_ROUTES("OUT2R", "HPOUT2R"),
CS47L90_RXANC_OUTPUT_ROUTES("OUT3L", "HPOUT3L"),
CS47L90_RXANC_OUTPUT_ROUTES("OUT3R", "HPOUT3R"),
CS47L90_RXANC_OUTPUT_ROUTES("OUT5L", "SPKDAT1L"),
CS47L90_RXANC_OUTPUT_ROUTES("OUT5R", "SPKDAT1R"),
{ "SPDIF1", NULL, "SPD1" },
{ "MICSUPP", NULL, "SYSCLK" },
{ "DRC1 Signal Activity", NULL, "DRC1 Activity Output" },
{ "DRC2 Signal Activity", NULL, "DRC2 Activity Output" },
{ "DRC1 Activity Output", "Switch", "DRC1L" },
{ "DRC1 Activity Output", "Switch", "DRC1R" },
{ "DRC2 Activity Output", "Switch", "DRC2L" },
{ "DRC2 Activity Output", "Switch", "DRC2R" },
MADERA_MUX_ROUTES("DFC1", "DFC1"),
MADERA_MUX_ROUTES("DFC2", "DFC2"),
MADERA_MUX_ROUTES("DFC3", "DFC3"),
MADERA_MUX_ROUTES("DFC4", "DFC4"),
MADERA_MUX_ROUTES("DFC5", "DFC5"),
MADERA_MUX_ROUTES("DFC6", "DFC6"),
MADERA_MUX_ROUTES("DFC7", "DFC7"),
MADERA_MUX_ROUTES("DFC8", "DFC8"),
};
static int cs47l90_set_fll(struct snd_soc_component *component, int fll_id,
int source, unsigned int fref, unsigned int fout)
{
struct cs47l90 *cs47l90 = snd_soc_component_get_drvdata(component);
switch (fll_id) {
case MADERA_FLL1_REFCLK:
return madera_set_fll_refclk(&cs47l90->fll[0], source, fref,
fout);
case MADERA_FLL2_REFCLK:
return madera_set_fll_refclk(&cs47l90->fll[1], source, fref,
fout);
case MADERA_FLLAO_REFCLK:
return madera_set_fll_ao_refclk(&cs47l90->fll[2], source, fref,
fout);
case MADERA_FLL1_SYNCCLK:
return madera_set_fll_syncclk(&cs47l90->fll[0], source, fref,
fout);
case MADERA_FLL2_SYNCCLK:
return madera_set_fll_syncclk(&cs47l90->fll[1], source, fref,
fout);
default:
return -EINVAL;
}
}
static const struct snd_soc_dai_ops cs47l90_dai_ops = {
.compress_new = snd_soc_new_compress,
};
static struct snd_soc_dai_driver cs47l90_dai[] = {
{
.name = "cs47l90-aif1",
.id = 1,
.base = MADERA_AIF1_BCLK_CTRL,
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 8,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 1,
.channels_max = 8,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &madera_dai_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
{
.name = "cs47l90-aif2",
.id = 2,
.base = MADERA_AIF2_BCLK_CTRL,
.playback = {
.stream_name = "AIF2 Playback",
.channels_min = 1,
.channels_max = 8,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.capture = {
.stream_name = "AIF2 Capture",
.channels_min = 1,
.channels_max = 8,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &madera_dai_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
{
.name = "cs47l90-aif3",
.id = 3,
.base = MADERA_AIF3_BCLK_CTRL,
.playback = {
.stream_name = "AIF3 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.capture = {
.stream_name = "AIF3 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &madera_dai_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
{
.name = "cs47l90-aif4",
.id = 4,
.base = MADERA_AIF4_BCLK_CTRL,
.playback = {
.stream_name = "AIF4 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.capture = {
.stream_name = "AIF4 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &madera_dai_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
{
.name = "cs47l90-slim1",
.id = 5,
.playback = {
.stream_name = "Slim1 Playback",
.channels_min = 1,
.channels_max = 4,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.capture = {
.stream_name = "Slim1 Capture",
.channels_min = 1,
.channels_max = 4,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &madera_simple_dai_ops,
},
{
.name = "cs47l90-slim2",
.id = 6,
.playback = {
.stream_name = "Slim2 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.capture = {
.stream_name = "Slim2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &madera_simple_dai_ops,
},
{
.name = "cs47l90-slim3",
.id = 7,
.playback = {
.stream_name = "Slim3 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.capture = {
.stream_name = "Slim3 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &madera_simple_dai_ops,
},
{
.name = "cs47l90-cpu-voicectrl",
.capture = {
.stream_name = "Voice Control CPU",
.channels_min = 1,
.channels_max = 1,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &cs47l90_dai_ops,
},
{
.name = "cs47l90-dsp-voicectrl",
.capture = {
.stream_name = "Voice Control DSP",
.channels_min = 1,
.channels_max = 1,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
},
{
.name = "cs47l90-cpu-trace",
.capture = {
.stream_name = "Audio Trace CPU",
.channels_min = 1,
.channels_max = 6,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &cs47l90_dai_ops,
},
{
.name = "cs47l90-dsp-trace",
.capture = {
.stream_name = "Audio Trace DSP",
.channels_min = 1,
.channels_max = 6,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
},
};
static int cs47l90_open(struct snd_soc_component *component,
struct snd_compr_stream *stream)
{
struct snd_soc_pcm_runtime *rtd = stream->private_data;
struct cs47l90 *cs47l90 = snd_soc_component_get_drvdata(component);
struct madera_priv *priv = &cs47l90->core;
struct madera *madera = priv->madera;
int n_adsp;
if (strcmp(asoc_rtd_to_codec(rtd, 0)->name, "cs47l90-dsp-voicectrl") == 0) {
n_adsp = 5;
} else if (strcmp(asoc_rtd_to_codec(rtd, 0)->name, "cs47l90-dsp-trace") == 0) {
n_adsp = 0;
} else {
dev_err(madera->dev,
"No suitable compressed stream for DAI '%s'\n",
asoc_rtd_to_codec(rtd, 0)->name);
return -EINVAL;
}
return wm_adsp_compr_open(&priv->adsp[n_adsp], stream);
}
static irqreturn_t cs47l90_adsp2_irq(int irq, void *data)
{
struct cs47l90 *cs47l90 = data;
struct madera_priv *priv = &cs47l90->core;
struct madera *madera = priv->madera;
struct madera_voice_trigger_info trig_info;
int serviced = 0;
int i, ret;
for (i = 0; i < CS47L90_NUM_ADSP; ++i) {
ret = wm_adsp_compr_handle_irq(&priv->adsp[i]);
if (ret != -ENODEV)
serviced++;
if (ret == WM_ADSP_COMPR_VOICE_TRIGGER) {
trig_info.core_num = i + 1;
blocking_notifier_call_chain(&madera->notifier,
MADERA_NOTIFY_VOICE_TRIGGER,
&trig_info);
}
}
if (!serviced) {
dev_err(madera->dev, "Spurious compressed data IRQ\n");
return IRQ_NONE;
}
return IRQ_HANDLED;
}
static int cs47l90_component_probe(struct snd_soc_component *component)
{
struct cs47l90 *cs47l90 = snd_soc_component_get_drvdata(component);
struct madera *madera = cs47l90->core.madera;
int ret, i;
snd_soc_component_init_regmap(component, madera->regmap);
mutex_lock(&madera->dapm_ptr_lock);
madera->dapm = snd_soc_component_get_dapm(component);
mutex_unlock(&madera->dapm_ptr_lock);
ret = madera_init_inputs(component);
if (ret)
return ret;
ret = madera_init_outputs(component, NULL, CS47L90_MONO_OUTPUTS,
CS47L90_MONO_OUTPUTS);
if (ret)
return ret;
snd_soc_component_disable_pin(component, "HAPTICS");
ret = snd_soc_add_component_controls(component,
madera_adsp_rate_controls,
CS47L90_NUM_ADSP);
if (ret)
return ret;
for (i = 0; i < CS47L90_NUM_ADSP; i++)
wm_adsp2_component_probe(&cs47l90->core.adsp[i], component);
return 0;
}
static void cs47l90_component_remove(struct snd_soc_component *component)
{
struct cs47l90 *cs47l90 = snd_soc_component_get_drvdata(component);
struct madera *madera = cs47l90->core.madera;
int i;
mutex_lock(&madera->dapm_ptr_lock);
madera->dapm = NULL;
mutex_unlock(&madera->dapm_ptr_lock);
for (i = 0; i < CS47L90_NUM_ADSP; i++)
wm_adsp2_component_remove(&cs47l90->core.adsp[i], component);
}
#define CS47L90_DIG_VU 0x0200
static unsigned int cs47l90_digital_vu[] = {
MADERA_DAC_DIGITAL_VOLUME_1L,
MADERA_DAC_DIGITAL_VOLUME_1R,
MADERA_DAC_DIGITAL_VOLUME_2L,
MADERA_DAC_DIGITAL_VOLUME_2R,
MADERA_DAC_DIGITAL_VOLUME_3L,
MADERA_DAC_DIGITAL_VOLUME_3R,
MADERA_DAC_DIGITAL_VOLUME_5L,
MADERA_DAC_DIGITAL_VOLUME_5R,
};
static const struct snd_compress_ops cs47l90_compress_ops = {
.open = &cs47l90_open,
.free = &wm_adsp_compr_free,
.set_params = &wm_adsp_compr_set_params,
.get_caps = &wm_adsp_compr_get_caps,
.trigger = &wm_adsp_compr_trigger,
.pointer = &wm_adsp_compr_pointer,
.copy = &wm_adsp_compr_copy,
};
static const struct snd_soc_component_driver soc_component_dev_cs47l90 = {
.probe = &cs47l90_component_probe,
.remove = &cs47l90_component_remove,
.set_sysclk = &madera_set_sysclk,
.set_pll = &cs47l90_set_fll,
.name = DRV_NAME,
.compress_ops = &cs47l90_compress_ops,
.controls = cs47l90_snd_controls,
.num_controls = ARRAY_SIZE(cs47l90_snd_controls),
.dapm_widgets = cs47l90_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(cs47l90_dapm_widgets),
.dapm_routes = cs47l90_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(cs47l90_dapm_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
static int cs47l90_probe(struct platform_device *pdev)
{
struct madera *madera = dev_get_drvdata(pdev->dev.parent);
struct cs47l90 *cs47l90;
int i, ret;
BUILD_BUG_ON(ARRAY_SIZE(cs47l90_dai) > MADERA_MAX_DAI);
/* quick exit if Madera irqchip driver hasn't completed probe */
if (!madera->irq_dev) {
dev_dbg(&pdev->dev, "irqchip driver not ready\n");
return -EPROBE_DEFER;
}
cs47l90 = devm_kzalloc(&pdev->dev, sizeof(struct cs47l90),
GFP_KERNEL);
if (!cs47l90)
return -ENOMEM;
platform_set_drvdata(pdev, cs47l90);
cs47l90->core.madera = madera;
cs47l90->core.dev = &pdev->dev;
cs47l90->core.num_inputs = 10;
ret = madera_core_init(&cs47l90->core);
if (ret)
return ret;
ret = madera_request_irq(madera, MADERA_IRQ_DSP_IRQ1,
"ADSP2 Compressed IRQ", cs47l90_adsp2_irq,
cs47l90);
if (ret != 0) {
dev_err(&pdev->dev, "Failed to request DSP IRQ: %d\n", ret);
goto error_core;
}
ret = madera_set_irq_wake(madera, MADERA_IRQ_DSP_IRQ1, 1);
if (ret)
dev_warn(&pdev->dev, "Failed to set DSP IRQ wake: %d\n", ret);
for (i = 0; i < CS47L90_NUM_ADSP; i++) {
cs47l90->core.adsp[i].part = "cs47l90";
cs47l90->core.adsp[i].cs_dsp.num = i + 1;
cs47l90->core.adsp[i].cs_dsp.type = WMFW_ADSP2;
cs47l90->core.adsp[i].cs_dsp.rev = 2;
cs47l90->core.adsp[i].cs_dsp.dev = madera->dev;
cs47l90->core.adsp[i].cs_dsp.regmap = madera->regmap_32bit;
cs47l90->core.adsp[i].cs_dsp.base = cs47l90_dsp_control_bases[i];
cs47l90->core.adsp[i].cs_dsp.mem = cs47l90_dsp_regions[i];
cs47l90->core.adsp[i].cs_dsp.num_mems =
ARRAY_SIZE(cs47l90_dsp1_regions);
cs47l90->core.adsp[i].cs_dsp.lock_regions = CS_ADSP2_REGION_1_9;
ret = wm_adsp2_init(&cs47l90->core.adsp[i]);
if (ret == 0) {
ret = madera_init_bus_error_irq(&cs47l90->core, i,
wm_adsp2_bus_error);
if (ret != 0)
wm_adsp2_remove(&cs47l90->core.adsp[i]);
}
if (ret) {
for (--i; i >= 0; --i) {
madera_free_bus_error_irq(&cs47l90->core, i);
wm_adsp2_remove(&cs47l90->core.adsp[i]);
}
goto error_dsp_irq;
}
}
madera_init_fll(madera, 1, MADERA_FLL1_CONTROL_1 - 1,
&cs47l90->fll[0]);
madera_init_fll(madera, 2, MADERA_FLL2_CONTROL_1 - 1,
&cs47l90->fll[1]);
madera_init_fll(madera, 4, MADERA_FLLAO_CONTROL_1 - 1,
&cs47l90->fll[2]);
for (i = 0; i < ARRAY_SIZE(cs47l90_dai); i++)
madera_init_dai(&cs47l90->core, i);
/* Latch volume update bits */
for (i = 0; i < ARRAY_SIZE(cs47l90_digital_vu); i++)
regmap_update_bits(madera->regmap, cs47l90_digital_vu[i],
CS47L90_DIG_VU, CS47L90_DIG_VU);
pm_runtime_enable(&pdev->dev);
pm_runtime_idle(&pdev->dev);
ret = devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_cs47l90,
cs47l90_dai,
ARRAY_SIZE(cs47l90_dai));
if (ret < 0) {
dev_err(&pdev->dev, "Failed to register component: %d\n", ret);
goto error_pm_runtime;
}
return ret;
error_pm_runtime:
pm_runtime_disable(&pdev->dev);
for (i = 0; i < CS47L90_NUM_ADSP; i++) {
madera_free_bus_error_irq(&cs47l90->core, i);
wm_adsp2_remove(&cs47l90->core.adsp[i]);
}
error_dsp_irq:
madera_set_irq_wake(madera, MADERA_IRQ_DSP_IRQ1, 0);
madera_free_irq(madera, MADERA_IRQ_DSP_IRQ1, cs47l90);
error_core:
madera_core_free(&cs47l90->core);
return ret;
}
static void cs47l90_remove(struct platform_device *pdev)
{
struct cs47l90 *cs47l90 = platform_get_drvdata(pdev);
int i;
pm_runtime_disable(&pdev->dev);
for (i = 0; i < CS47L90_NUM_ADSP; i++) {
madera_free_bus_error_irq(&cs47l90->core, i);
wm_adsp2_remove(&cs47l90->core.adsp[i]);
}
madera_set_irq_wake(cs47l90->core.madera, MADERA_IRQ_DSP_IRQ1, 0);
madera_free_irq(cs47l90->core.madera, MADERA_IRQ_DSP_IRQ1, cs47l90);
madera_core_free(&cs47l90->core);
}
static struct platform_driver cs47l90_codec_driver = {
.driver = {
.name = "cs47l90-codec",
},
.probe = &cs47l90_probe,
.remove_new = cs47l90_remove,
};
module_platform_driver(cs47l90_codec_driver);
MODULE_SOFTDEP("pre: madera irq-madera arizona-micsupp");
MODULE_DESCRIPTION("ASoC CS47L90 driver");
MODULE_AUTHOR("Nikesh Oswal <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:cs47l90-codec");
| linux-master | sound/soc/codecs/cs47l90.c |
// SPDX-License-Identifier: GPL-2.0
//
// cs35l41-lib.c -- CS35L41 Common functions for HDA and ASoC Audio drivers
//
// Copyright 2017-2021 Cirrus Logic, Inc.
//
// Author: David Rhodes <[email protected]>
// Author: Lucas Tanure <[email protected]>
#include <linux/dev_printk.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <linux/firmware/cirrus/wmfw.h>
#include <sound/cs35l41.h>
static const struct reg_default cs35l41_reg[] = {
{ CS35L41_PWR_CTRL1, 0x00000000 },
{ CS35L41_PWR_CTRL2, 0x00000000 },
{ CS35L41_PWR_CTRL3, 0x01000010 },
{ CS35L41_GPIO_PAD_CONTROL, 0x00000000 },
{ CS35L41_GLOBAL_CLK_CTRL, 0x00000003 },
{ CS35L41_TST_FS_MON0, 0x00020016 },
{ CS35L41_BSTCVRT_COEFF, 0x00002424 },
{ CS35L41_BSTCVRT_SLOPE_LBST, 0x00007500 },
{ CS35L41_BSTCVRT_PEAK_CUR, 0x0000004A },
{ CS35L41_SP_ENABLES, 0x00000000 },
{ CS35L41_SP_RATE_CTRL, 0x00000028 },
{ CS35L41_SP_FORMAT, 0x18180200 },
{ CS35L41_SP_HIZ_CTRL, 0x00000002 },
{ CS35L41_SP_FRAME_TX_SLOT, 0x03020100 },
{ CS35L41_SP_FRAME_RX_SLOT, 0x00000100 },
{ CS35L41_SP_TX_WL, 0x00000018 },
{ CS35L41_SP_RX_WL, 0x00000018 },
{ CS35L41_DAC_PCM1_SRC, 0x00000008 },
{ CS35L41_ASP_TX1_SRC, 0x00000018 },
{ CS35L41_ASP_TX2_SRC, 0x00000019 },
{ CS35L41_ASP_TX3_SRC, 0x00000000 },
{ CS35L41_ASP_TX4_SRC, 0x00000000 },
{ CS35L41_DSP1_RX1_SRC, 0x00000008 },
{ CS35L41_DSP1_RX2_SRC, 0x00000009 },
{ CS35L41_DSP1_RX3_SRC, 0x00000018 },
{ CS35L41_DSP1_RX4_SRC, 0x00000019 },
{ CS35L41_DSP1_RX5_SRC, 0x00000020 },
{ CS35L41_DSP1_RX6_SRC, 0x00000021 },
{ CS35L41_DSP1_RX7_SRC, 0x0000003A },
{ CS35L41_DSP1_RX8_SRC, 0x0000003B },
{ CS35L41_NGATE1_SRC, 0x00000008 },
{ CS35L41_NGATE2_SRC, 0x00000009 },
{ CS35L41_AMP_DIG_VOL_CTRL, 0x00008000 },
{ CS35L41_CLASSH_CFG, 0x000B0405 },
{ CS35L41_WKFET_CFG, 0x00000111 },
{ CS35L41_NG_CFG, 0x00000033 },
{ CS35L41_AMP_GAIN_CTRL, 0x00000000 },
{ CS35L41_IRQ1_MASK1, 0xFFFFFFFF },
{ CS35L41_IRQ1_MASK2, 0xFFFFFFFF },
{ CS35L41_IRQ1_MASK3, 0xFFFF87FF },
{ CS35L41_IRQ1_MASK4, 0xFEFFFFFF },
{ CS35L41_GPIO1_CTRL1, 0x81000001 },
{ CS35L41_GPIO2_CTRL1, 0x81000001 },
{ CS35L41_MIXER_NGATE_CFG, 0x00000000 },
{ CS35L41_MIXER_NGATE_CH1_CFG, 0x00000303 },
{ CS35L41_MIXER_NGATE_CH2_CFG, 0x00000303 },
{ CS35L41_DSP1_CCM_CORE_CTRL, 0x00000101 },
};
static bool cs35l41_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS35L41_DEVID:
case CS35L41_REVID:
case CS35L41_FABID:
case CS35L41_RELID:
case CS35L41_OTPID:
case CS35L41_TEST_KEY_CTL:
case CS35L41_USER_KEY_CTL:
case CS35L41_OTP_CTRL0:
case CS35L41_OTP_CTRL3:
case CS35L41_OTP_CTRL4:
case CS35L41_OTP_CTRL5:
case CS35L41_OTP_CTRL6:
case CS35L41_OTP_CTRL7:
case CS35L41_OTP_CTRL8:
case CS35L41_PWR_CTRL1:
case CS35L41_PWR_CTRL2:
case CS35L41_PWR_CTRL3:
case CS35L41_CTRL_OVRRIDE:
case CS35L41_AMP_OUT_MUTE:
case CS35L41_PROTECT_REL_ERR_IGN:
case CS35L41_GPIO_PAD_CONTROL:
case CS35L41_JTAG_CONTROL:
case CS35L41_PWRMGT_CTL:
case CS35L41_WAKESRC_CTL:
case CS35L41_PWRMGT_STS:
case CS35L41_PLL_CLK_CTRL:
case CS35L41_DSP_CLK_CTRL:
case CS35L41_GLOBAL_CLK_CTRL:
case CS35L41_DATA_FS_SEL:
case CS35L41_TST_FS_MON0:
case CS35L41_MDSYNC_EN:
case CS35L41_MDSYNC_TX_ID:
case CS35L41_MDSYNC_PWR_CTRL:
case CS35L41_MDSYNC_DATA_TX:
case CS35L41_MDSYNC_TX_STATUS:
case CS35L41_MDSYNC_DATA_RX:
case CS35L41_MDSYNC_RX_STATUS:
case CS35L41_MDSYNC_ERR_STATUS:
case CS35L41_MDSYNC_SYNC_PTE2:
case CS35L41_MDSYNC_SYNC_PTE3:
case CS35L41_MDSYNC_SYNC_MSM_STATUS:
case CS35L41_BSTCVRT_VCTRL1:
case CS35L41_BSTCVRT_VCTRL2:
case CS35L41_BSTCVRT_PEAK_CUR:
case CS35L41_BSTCVRT_SFT_RAMP:
case CS35L41_BSTCVRT_COEFF:
case CS35L41_BSTCVRT_SLOPE_LBST:
case CS35L41_BSTCVRT_SW_FREQ:
case CS35L41_BSTCVRT_DCM_CTRL:
case CS35L41_BSTCVRT_DCM_MODE_FORCE:
case CS35L41_BSTCVRT_OVERVOLT_CTRL:
case CS35L41_VI_VOL_POL:
case CS35L41_DTEMP_WARN_THLD:
case CS35L41_DTEMP_CFG:
case CS35L41_DTEMP_EN:
case CS35L41_VPVBST_FS_SEL:
case CS35L41_SP_ENABLES:
case CS35L41_SP_RATE_CTRL:
case CS35L41_SP_FORMAT:
case CS35L41_SP_HIZ_CTRL:
case CS35L41_SP_FRAME_TX_SLOT:
case CS35L41_SP_FRAME_RX_SLOT:
case CS35L41_SP_TX_WL:
case CS35L41_SP_RX_WL:
case CS35L41_DAC_PCM1_SRC:
case CS35L41_ASP_TX1_SRC:
case CS35L41_ASP_TX2_SRC:
case CS35L41_ASP_TX3_SRC:
case CS35L41_ASP_TX4_SRC:
case CS35L41_DSP1_RX1_SRC:
case CS35L41_DSP1_RX2_SRC:
case CS35L41_DSP1_RX3_SRC:
case CS35L41_DSP1_RX4_SRC:
case CS35L41_DSP1_RX5_SRC:
case CS35L41_DSP1_RX6_SRC:
case CS35L41_DSP1_RX7_SRC:
case CS35L41_DSP1_RX8_SRC:
case CS35L41_NGATE1_SRC:
case CS35L41_NGATE2_SRC:
case CS35L41_AMP_DIG_VOL_CTRL:
case CS35L41_VPBR_CFG:
case CS35L41_VBBR_CFG:
case CS35L41_VPBR_STATUS:
case CS35L41_VBBR_STATUS:
case CS35L41_OVERTEMP_CFG:
case CS35L41_AMP_ERR_VOL:
case CS35L41_VOL_STATUS_TO_DSP:
case CS35L41_CLASSH_CFG:
case CS35L41_WKFET_CFG:
case CS35L41_NG_CFG:
case CS35L41_AMP_GAIN_CTRL:
case CS35L41_DAC_MSM_CFG:
case CS35L41_IRQ1_CFG:
case CS35L41_IRQ1_STATUS:
case CS35L41_IRQ1_STATUS1:
case CS35L41_IRQ1_STATUS2:
case CS35L41_IRQ1_STATUS3:
case CS35L41_IRQ1_STATUS4:
case CS35L41_IRQ1_RAW_STATUS1:
case CS35L41_IRQ1_RAW_STATUS2:
case CS35L41_IRQ1_RAW_STATUS3:
case CS35L41_IRQ1_RAW_STATUS4:
case CS35L41_IRQ1_MASK1:
case CS35L41_IRQ1_MASK2:
case CS35L41_IRQ1_MASK3:
case CS35L41_IRQ1_MASK4:
case CS35L41_IRQ1_FRC1:
case CS35L41_IRQ1_FRC2:
case CS35L41_IRQ1_FRC3:
case CS35L41_IRQ1_FRC4:
case CS35L41_IRQ1_EDGE1:
case CS35L41_IRQ1_EDGE4:
case CS35L41_IRQ1_POL1:
case CS35L41_IRQ1_POL2:
case CS35L41_IRQ1_POL3:
case CS35L41_IRQ1_POL4:
case CS35L41_IRQ1_DB3:
case CS35L41_IRQ2_CFG:
case CS35L41_IRQ2_STATUS:
case CS35L41_IRQ2_STATUS1:
case CS35L41_IRQ2_STATUS2:
case CS35L41_IRQ2_STATUS3:
case CS35L41_IRQ2_STATUS4:
case CS35L41_IRQ2_RAW_STATUS1:
case CS35L41_IRQ2_RAW_STATUS2:
case CS35L41_IRQ2_RAW_STATUS3:
case CS35L41_IRQ2_RAW_STATUS4:
case CS35L41_IRQ2_MASK1:
case CS35L41_IRQ2_MASK2:
case CS35L41_IRQ2_MASK3:
case CS35L41_IRQ2_MASK4:
case CS35L41_IRQ2_FRC1:
case CS35L41_IRQ2_FRC2:
case CS35L41_IRQ2_FRC3:
case CS35L41_IRQ2_FRC4:
case CS35L41_IRQ2_EDGE1:
case CS35L41_IRQ2_EDGE4:
case CS35L41_IRQ2_POL1:
case CS35L41_IRQ2_POL2:
case CS35L41_IRQ2_POL3:
case CS35L41_IRQ2_POL4:
case CS35L41_IRQ2_DB3:
case CS35L41_GPIO_STATUS1:
case CS35L41_GPIO1_CTRL1:
case CS35L41_GPIO2_CTRL1:
case CS35L41_MIXER_NGATE_CFG:
case CS35L41_MIXER_NGATE_CH1_CFG:
case CS35L41_MIXER_NGATE_CH2_CFG:
case CS35L41_DSP_MBOX_1 ... CS35L41_DSP_VIRT2_MBOX_8:
case CS35L41_CLOCK_DETECT_1:
case CS35L41_DIE_STS1:
case CS35L41_DIE_STS2:
case CS35L41_TEMP_CAL1:
case CS35L41_TEMP_CAL2:
case CS35L41_DSP1_TIMESTAMP_COUNT:
case CS35L41_DSP1_SYS_ID:
case CS35L41_DSP1_SYS_VERSION:
case CS35L41_DSP1_SYS_CORE_ID:
case CS35L41_DSP1_SYS_AHB_ADDR:
case CS35L41_DSP1_SYS_XSRAM_SIZE:
case CS35L41_DSP1_SYS_YSRAM_SIZE:
case CS35L41_DSP1_SYS_PSRAM_SIZE:
case CS35L41_DSP1_SYS_PM_BOOT_SIZE:
case CS35L41_DSP1_SYS_FEATURES:
case CS35L41_DSP1_SYS_FIR_FILTERS:
case CS35L41_DSP1_SYS_LMS_FILTERS:
case CS35L41_DSP1_SYS_XM_BANK_SIZE:
case CS35L41_DSP1_SYS_YM_BANK_SIZE:
case CS35L41_DSP1_SYS_PM_BANK_SIZE:
case CS35L41_DSP1_RX1_RATE:
case CS35L41_DSP1_RX2_RATE:
case CS35L41_DSP1_RX3_RATE:
case CS35L41_DSP1_RX4_RATE:
case CS35L41_DSP1_RX5_RATE:
case CS35L41_DSP1_RX6_RATE:
case CS35L41_DSP1_RX7_RATE:
case CS35L41_DSP1_RX8_RATE:
case CS35L41_DSP1_TX1_RATE:
case CS35L41_DSP1_TX2_RATE:
case CS35L41_DSP1_TX3_RATE:
case CS35L41_DSP1_TX4_RATE:
case CS35L41_DSP1_TX5_RATE:
case CS35L41_DSP1_TX6_RATE:
case CS35L41_DSP1_TX7_RATE:
case CS35L41_DSP1_TX8_RATE:
case CS35L41_DSP1_SCRATCH1:
case CS35L41_DSP1_SCRATCH2:
case CS35L41_DSP1_SCRATCH3:
case CS35L41_DSP1_SCRATCH4:
case CS35L41_DSP1_CCM_CORE_CTRL:
case CS35L41_DSP1_CCM_CLK_OVERRIDE:
case CS35L41_DSP1_XM_MSTR_EN:
case CS35L41_DSP1_XM_CORE_PRI:
case CS35L41_DSP1_XM_AHB_PACK_PL_PRI:
case CS35L41_DSP1_XM_AHB_UP_PL_PRI:
case CS35L41_DSP1_XM_ACCEL_PL0_PRI:
case CS35L41_DSP1_XM_NPL0_PRI:
case CS35L41_DSP1_YM_MSTR_EN:
case CS35L41_DSP1_YM_CORE_PRI:
case CS35L41_DSP1_YM_AHB_PACK_PL_PRI:
case CS35L41_DSP1_YM_AHB_UP_PL_PRI:
case CS35L41_DSP1_YM_ACCEL_PL0_PRI:
case CS35L41_DSP1_YM_NPL0_PRI:
case CS35L41_DSP1_MPU_XM_ACCESS0:
case CS35L41_DSP1_MPU_YM_ACCESS0:
case CS35L41_DSP1_MPU_WNDW_ACCESS0:
case CS35L41_DSP1_MPU_XREG_ACCESS0:
case CS35L41_DSP1_MPU_YREG_ACCESS0:
case CS35L41_DSP1_MPU_XM_ACCESS1:
case CS35L41_DSP1_MPU_YM_ACCESS1:
case CS35L41_DSP1_MPU_WNDW_ACCESS1:
case CS35L41_DSP1_MPU_XREG_ACCESS1:
case CS35L41_DSP1_MPU_YREG_ACCESS1:
case CS35L41_DSP1_MPU_XM_ACCESS2:
case CS35L41_DSP1_MPU_YM_ACCESS2:
case CS35L41_DSP1_MPU_WNDW_ACCESS2:
case CS35L41_DSP1_MPU_XREG_ACCESS2:
case CS35L41_DSP1_MPU_YREG_ACCESS2:
case CS35L41_DSP1_MPU_XM_ACCESS3:
case CS35L41_DSP1_MPU_YM_ACCESS3:
case CS35L41_DSP1_MPU_WNDW_ACCESS3:
case CS35L41_DSP1_MPU_XREG_ACCESS3:
case CS35L41_DSP1_MPU_YREG_ACCESS3:
case CS35L41_DSP1_MPU_XM_VIO_ADDR:
case CS35L41_DSP1_MPU_XM_VIO_STATUS:
case CS35L41_DSP1_MPU_YM_VIO_ADDR:
case CS35L41_DSP1_MPU_YM_VIO_STATUS:
case CS35L41_DSP1_MPU_PM_VIO_ADDR:
case CS35L41_DSP1_MPU_PM_VIO_STATUS:
case CS35L41_DSP1_MPU_LOCK_CONFIG:
case CS35L41_DSP1_MPU_WDT_RST_CTRL:
case CS35L41_OTP_TRIM_1:
case CS35L41_OTP_TRIM_2:
case CS35L41_OTP_TRIM_3:
case CS35L41_OTP_TRIM_4:
case CS35L41_OTP_TRIM_5:
case CS35L41_OTP_TRIM_6:
case CS35L41_OTP_TRIM_7:
case CS35L41_OTP_TRIM_8:
case CS35L41_OTP_TRIM_9:
case CS35L41_OTP_TRIM_10:
case CS35L41_OTP_TRIM_11:
case CS35L41_OTP_TRIM_12:
case CS35L41_OTP_TRIM_13:
case CS35L41_OTP_TRIM_14:
case CS35L41_OTP_TRIM_15:
case CS35L41_OTP_TRIM_16:
case CS35L41_OTP_TRIM_17:
case CS35L41_OTP_TRIM_18:
case CS35L41_OTP_TRIM_19:
case CS35L41_OTP_TRIM_20:
case CS35L41_OTP_TRIM_21:
case CS35L41_OTP_TRIM_22:
case CS35L41_OTP_TRIM_23:
case CS35L41_OTP_TRIM_24:
case CS35L41_OTP_TRIM_25:
case CS35L41_OTP_TRIM_26:
case CS35L41_OTP_TRIM_27:
case CS35L41_OTP_TRIM_28:
case CS35L41_OTP_TRIM_29:
case CS35L41_OTP_TRIM_30:
case CS35L41_OTP_TRIM_31:
case CS35L41_OTP_TRIM_32:
case CS35L41_OTP_TRIM_33:
case CS35L41_OTP_TRIM_34:
case CS35L41_OTP_TRIM_35:
case CS35L41_OTP_TRIM_36:
case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31:
case CS35L41_DSP1_XMEM_PACK_0 ... CS35L41_DSP1_XMEM_PACK_3068:
case CS35L41_DSP1_XMEM_UNPACK32_0 ... CS35L41_DSP1_XMEM_UNPACK32_2046:
case CS35L41_DSP1_XMEM_UNPACK24_0 ... CS35L41_DSP1_XMEM_UNPACK24_4093:
case CS35L41_DSP1_YMEM_PACK_0 ... CS35L41_DSP1_YMEM_PACK_1532:
case CS35L41_DSP1_YMEM_UNPACK32_0 ... CS35L41_DSP1_YMEM_UNPACK32_1022:
case CS35L41_DSP1_YMEM_UNPACK24_0 ... CS35L41_DSP1_YMEM_UNPACK24_2045:
case CS35L41_DSP1_PMEM_0 ... CS35L41_DSP1_PMEM_5114:
/*test regs*/
case CS35L41_PLL_OVR:
case CS35L41_BST_TEST_DUTY:
case CS35L41_DIGPWM_IOCTRL:
return true;
default:
return false;
}
}
static bool cs35l41_precious_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS35L41_TEST_KEY_CTL:
case CS35L41_USER_KEY_CTL:
case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31:
case CS35L41_TST_FS_MON0:
case CS35L41_DSP1_XMEM_PACK_0 ... CS35L41_DSP1_XMEM_PACK_3068:
case CS35L41_DSP1_YMEM_PACK_0 ... CS35L41_DSP1_YMEM_PACK_1532:
case CS35L41_DSP1_PMEM_0 ... CS35L41_DSP1_PMEM_5114:
return true;
default:
return false;
}
}
static bool cs35l41_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS35L41_DEVID:
case CS35L41_SFT_RESET:
case CS35L41_FABID:
case CS35L41_REVID:
case CS35L41_OTPID:
case CS35L41_TEST_KEY_CTL:
case CS35L41_USER_KEY_CTL:
case CS35L41_PWRMGT_CTL:
case CS35L41_WAKESRC_CTL:
case CS35L41_PWRMGT_STS:
case CS35L41_DTEMP_EN:
case CS35L41_IRQ1_STATUS:
case CS35L41_IRQ1_STATUS1:
case CS35L41_IRQ1_STATUS2:
case CS35L41_IRQ1_STATUS3:
case CS35L41_IRQ1_STATUS4:
case CS35L41_IRQ1_RAW_STATUS1:
case CS35L41_IRQ1_RAW_STATUS2:
case CS35L41_IRQ1_RAW_STATUS3:
case CS35L41_IRQ1_RAW_STATUS4:
case CS35L41_IRQ2_STATUS:
case CS35L41_IRQ2_STATUS1:
case CS35L41_IRQ2_STATUS2:
case CS35L41_IRQ2_STATUS3:
case CS35L41_IRQ2_STATUS4:
case CS35L41_IRQ2_RAW_STATUS1:
case CS35L41_IRQ2_RAW_STATUS2:
case CS35L41_IRQ2_RAW_STATUS3:
case CS35L41_IRQ2_RAW_STATUS4:
case CS35L41_GPIO_STATUS1:
case CS35L41_DSP_MBOX_1 ... CS35L41_DSP_VIRT2_MBOX_8:
case CS35L41_DSP1_XMEM_PACK_0 ... CS35L41_DSP1_XMEM_PACK_3068:
case CS35L41_DSP1_XMEM_UNPACK32_0 ... CS35L41_DSP1_XMEM_UNPACK32_2046:
case CS35L41_DSP1_XMEM_UNPACK24_0 ... CS35L41_DSP1_XMEM_UNPACK24_4093:
case CS35L41_DSP1_YMEM_PACK_0 ... CS35L41_DSP1_YMEM_PACK_1532:
case CS35L41_DSP1_YMEM_UNPACK32_0 ... CS35L41_DSP1_YMEM_UNPACK32_1022:
case CS35L41_DSP1_YMEM_UNPACK24_0 ... CS35L41_DSP1_YMEM_UNPACK24_2045:
case CS35L41_DSP1_PMEM_0 ... CS35L41_DSP1_PMEM_5114:
case CS35L41_DSP1_SCRATCH1:
case CS35L41_DSP1_SCRATCH2:
case CS35L41_DSP1_SCRATCH3:
case CS35L41_DSP1_SCRATCH4:
case CS35L41_DSP1_CCM_CLK_OVERRIDE ... CS35L41_DSP1_WDT_STATUS:
case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31:
return true;
default:
return false;
}
}
static const struct cs35l41_otp_packed_element_t otp_map_1[] = {
/* addr shift size */
{ 0x00002030, 0, 4 }, /*TRIM_OSC_FREQ_TRIM*/
{ 0x00002030, 7, 1 }, /*TRIM_OSC_TRIM_DONE*/
{ 0x0000208c, 24, 6 }, /*TST_DIGREG_VREF_TRIM*/
{ 0x00002090, 14, 4 }, /*TST_REF_TRIM*/
{ 0x00002090, 10, 4 }, /*TST_REF_TEMPCO_TRIM*/
{ 0x0000300C, 11, 4 }, /*PLL_LDOA_TST_VREF_TRIM*/
{ 0x0000394C, 23, 2 }, /*BST_ATEST_CM_VOFF*/
{ 0x00003950, 0, 7 }, /*BST_ATRIM_IADC_OFFSET*/
{ 0x00003950, 8, 7 }, /*BST_ATRIM_IADC_GAIN1*/
{ 0x00003950, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET1*/
{ 0x00003950, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN1*/
{ 0x00003954, 0, 7 }, /*BST_ATRIM_IADC_OFFSET2*/
{ 0x00003954, 8, 7 }, /*BST_ATRIM_IADC_GAIN2*/
{ 0x00003954, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET2*/
{ 0x00003954, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN2*/
{ 0x00003958, 0, 7 }, /*BST_ATRIM_IADC_OFFSET3*/
{ 0x00003958, 8, 7 }, /*BST_ATRIM_IADC_GAIN3*/
{ 0x00003958, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET3*/
{ 0x00003958, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN3*/
{ 0x0000395C, 0, 7 }, /*BST_ATRIM_IADC_OFFSET4*/
{ 0x0000395C, 8, 7 }, /*BST_ATRIM_IADC_GAIN4*/
{ 0x0000395C, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET4*/
{ 0x0000395C, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN4*/
{ 0x0000416C, 0, 8 }, /*VMON_GAIN_OTP_VAL*/
{ 0x00004160, 0, 7 }, /*VMON_OFFSET_OTP_VAL*/
{ 0x0000416C, 8, 8 }, /*IMON_GAIN_OTP_VAL*/
{ 0x00004160, 16, 10 }, /*IMON_OFFSET_OTP_VAL*/
{ 0x0000416C, 16, 12 }, /*VMON_CM_GAIN_OTP_VAL*/
{ 0x0000416C, 28, 1 }, /*VMON_CM_GAIN_SIGN_OTP_VAL*/
{ 0x00004170, 0, 6 }, /*IMON_CAL_TEMPCO_OTP_VAL*/
{ 0x00004170, 6, 1 }, /*IMON_CAL_TEMPCO_SIGN_OTP*/
{ 0x00004170, 8, 6 }, /*IMON_CAL_TEMPCO2_OTP_VAL*/
{ 0x00004170, 14, 1 }, /*IMON_CAL_TEMPCO2_DN_UPB_OTP_VAL*/
{ 0x00004170, 16, 9 }, /*IMON_CAL_TEMPCO_TBASE_OTP_VAL*/
{ 0x00004360, 0, 5 }, /*TEMP_GAIN_OTP_VAL*/
{ 0x00004360, 6, 9 }, /*TEMP_OFFSET_OTP_VAL*/
{ 0x00004448, 0, 8 }, /*VP_SARADC_OFFSET*/
{ 0x00004448, 8, 8 }, /*VP_GAIN_INDEX*/
{ 0x00004448, 16, 8 }, /*VBST_SARADC_OFFSET*/
{ 0x00004448, 24, 8 }, /*VBST_GAIN_INDEX*/
{ 0x0000444C, 0, 3 }, /*ANA_SELINVREF*/
{ 0x00006E30, 0, 5 }, /*GAIN_ERR_COEFF_0*/
{ 0x00006E30, 8, 5 }, /*GAIN_ERR_COEFF_1*/
{ 0x00006E30, 16, 5 }, /*GAIN_ERR_COEFF_2*/
{ 0x00006E30, 24, 5 }, /*GAIN_ERR_COEFF_3*/
{ 0x00006E34, 0, 5 }, /*GAIN_ERR_COEFF_4*/
{ 0x00006E34, 8, 5 }, /*GAIN_ERR_COEFF_5*/
{ 0x00006E34, 16, 5 }, /*GAIN_ERR_COEFF_6*/
{ 0x00006E34, 24, 5 }, /*GAIN_ERR_COEFF_7*/
{ 0x00006E38, 0, 5 }, /*GAIN_ERR_COEFF_8*/
{ 0x00006E38, 8, 5 }, /*GAIN_ERR_COEFF_9*/
{ 0x00006E38, 16, 5 }, /*GAIN_ERR_COEFF_10*/
{ 0x00006E38, 24, 5 }, /*GAIN_ERR_COEFF_11*/
{ 0x00006E3C, 0, 5 }, /*GAIN_ERR_COEFF_12*/
{ 0x00006E3C, 8, 5 }, /*GAIN_ERR_COEFF_13*/
{ 0x00006E3C, 16, 5 }, /*GAIN_ERR_COEFF_14*/
{ 0x00006E3C, 24, 5 }, /*GAIN_ERR_COEFF_15*/
{ 0x00006E40, 0, 5 }, /*GAIN_ERR_COEFF_16*/
{ 0x00006E40, 8, 5 }, /*GAIN_ERR_COEFF_17*/
{ 0x00006E40, 16, 5 }, /*GAIN_ERR_COEFF_18*/
{ 0x00006E40, 24, 5 }, /*GAIN_ERR_COEFF_19*/
{ 0x00006E44, 0, 5 }, /*GAIN_ERR_COEFF_20*/
{ 0x00006E48, 0, 10 }, /*VOFF_GAIN_0*/
{ 0x00006E48, 10, 10 }, /*VOFF_GAIN_1*/
{ 0x00006E48, 20, 10 }, /*VOFF_GAIN_2*/
{ 0x00006E4C, 0, 10 }, /*VOFF_GAIN_3*/
{ 0x00006E4C, 10, 10 }, /*VOFF_GAIN_4*/
{ 0x00006E4C, 20, 10 }, /*VOFF_GAIN_5*/
{ 0x00006E50, 0, 10 }, /*VOFF_GAIN_6*/
{ 0x00006E50, 10, 10 }, /*VOFF_GAIN_7*/
{ 0x00006E50, 20, 10 }, /*VOFF_GAIN_8*/
{ 0x00006E54, 0, 10 }, /*VOFF_GAIN_9*/
{ 0x00006E54, 10, 10 }, /*VOFF_GAIN_10*/
{ 0x00006E54, 20, 10 }, /*VOFF_GAIN_11*/
{ 0x00006E58, 0, 10 }, /*VOFF_GAIN_12*/
{ 0x00006E58, 10, 10 }, /*VOFF_GAIN_13*/
{ 0x00006E58, 20, 10 }, /*VOFF_GAIN_14*/
{ 0x00006E5C, 0, 10 }, /*VOFF_GAIN_15*/
{ 0x00006E5C, 10, 10 }, /*VOFF_GAIN_16*/
{ 0x00006E5C, 20, 10 }, /*VOFF_GAIN_17*/
{ 0x00006E60, 0, 10 }, /*VOFF_GAIN_18*/
{ 0x00006E60, 10, 10 }, /*VOFF_GAIN_19*/
{ 0x00006E60, 20, 10 }, /*VOFF_GAIN_20*/
{ 0x00006E64, 0, 10 }, /*VOFF_INT1*/
{ 0x00007418, 7, 5 }, /*DS_SPK_INT1_CAP_TRIM*/
{ 0x0000741C, 0, 5 }, /*DS_SPK_INT2_CAP_TRIM*/
{ 0x0000741C, 11, 4 }, /*DS_SPK_LPF_CAP_TRIM*/
{ 0x0000741C, 19, 4 }, /*DS_SPK_QUAN_CAP_TRIM*/
{ 0x00007434, 17, 1 }, /*FORCE_CAL*/
{ 0x00007434, 18, 7 }, /*CAL_OVERRIDE*/
{ 0x00007068, 0, 9 }, /*MODIX*/
{ 0x0000410C, 7, 1 }, /*VIMON_DLY_NOT_COMB*/
{ 0x0000400C, 0, 7 }, /*VIMON_DLY*/
{ 0x00000000, 0, 1 }, /*extra bit*/
{ 0x00017040, 0, 8 }, /*X_COORDINATE*/
{ 0x00017040, 8, 8 }, /*Y_COORDINATE*/
{ 0x00017040, 16, 8 }, /*WAFER_ID*/
{ 0x00017040, 24, 8 }, /*DVS*/
{ 0x00017044, 0, 24 }, /*LOT_NUMBER*/
};
static const struct cs35l41_otp_packed_element_t otp_map_2[] = {
/* addr shift size */
{ 0x00002030, 0, 4 }, /*TRIM_OSC_FREQ_TRIM*/
{ 0x00002030, 7, 1 }, /*TRIM_OSC_TRIM_DONE*/
{ 0x0000208c, 24, 6 }, /*TST_DIGREG_VREF_TRIM*/
{ 0x00002090, 14, 4 }, /*TST_REF_TRIM*/
{ 0x00002090, 10, 4 }, /*TST_REF_TEMPCO_TRIM*/
{ 0x0000300C, 11, 4 }, /*PLL_LDOA_TST_VREF_TRIM*/
{ 0x0000394C, 23, 2 }, /*BST_ATEST_CM_VOFF*/
{ 0x00003950, 0, 7 }, /*BST_ATRIM_IADC_OFFSET*/
{ 0x00003950, 8, 7 }, /*BST_ATRIM_IADC_GAIN1*/
{ 0x00003950, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET1*/
{ 0x00003950, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN1*/
{ 0x00003954, 0, 7 }, /*BST_ATRIM_IADC_OFFSET2*/
{ 0x00003954, 8, 7 }, /*BST_ATRIM_IADC_GAIN2*/
{ 0x00003954, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET2*/
{ 0x00003954, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN2*/
{ 0x00003958, 0, 7 }, /*BST_ATRIM_IADC_OFFSET3*/
{ 0x00003958, 8, 7 }, /*BST_ATRIM_IADC_GAIN3*/
{ 0x00003958, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET3*/
{ 0x00003958, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN3*/
{ 0x0000395C, 0, 7 }, /*BST_ATRIM_IADC_OFFSET4*/
{ 0x0000395C, 8, 7 }, /*BST_ATRIM_IADC_GAIN4*/
{ 0x0000395C, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET4*/
{ 0x0000395C, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN4*/
{ 0x0000416C, 0, 8 }, /*VMON_GAIN_OTP_VAL*/
{ 0x00004160, 0, 7 }, /*VMON_OFFSET_OTP_VAL*/
{ 0x0000416C, 8, 8 }, /*IMON_GAIN_OTP_VAL*/
{ 0x00004160, 16, 10 }, /*IMON_OFFSET_OTP_VAL*/
{ 0x0000416C, 16, 12 }, /*VMON_CM_GAIN_OTP_VAL*/
{ 0x0000416C, 28, 1 }, /*VMON_CM_GAIN_SIGN_OTP_VAL*/
{ 0x00004170, 0, 6 }, /*IMON_CAL_TEMPCO_OTP_VAL*/
{ 0x00004170, 6, 1 }, /*IMON_CAL_TEMPCO_SIGN_OTP*/
{ 0x00004170, 8, 6 }, /*IMON_CAL_TEMPCO2_OTP_VAL*/
{ 0x00004170, 14, 1 }, /*IMON_CAL_TEMPCO2_DN_UPB_OTP_VAL*/
{ 0x00004170, 16, 9 }, /*IMON_CAL_TEMPCO_TBASE_OTP_VAL*/
{ 0x00004360, 0, 5 }, /*TEMP_GAIN_OTP_VAL*/
{ 0x00004360, 6, 9 }, /*TEMP_OFFSET_OTP_VAL*/
{ 0x00004448, 0, 8 }, /*VP_SARADC_OFFSET*/
{ 0x00004448, 8, 8 }, /*VP_GAIN_INDEX*/
{ 0x00004448, 16, 8 }, /*VBST_SARADC_OFFSET*/
{ 0x00004448, 24, 8 }, /*VBST_GAIN_INDEX*/
{ 0x0000444C, 0, 3 }, /*ANA_SELINVREF*/
{ 0x00006E30, 0, 5 }, /*GAIN_ERR_COEFF_0*/
{ 0x00006E30, 8, 5 }, /*GAIN_ERR_COEFF_1*/
{ 0x00006E30, 16, 5 }, /*GAIN_ERR_COEFF_2*/
{ 0x00006E30, 24, 5 }, /*GAIN_ERR_COEFF_3*/
{ 0x00006E34, 0, 5 }, /*GAIN_ERR_COEFF_4*/
{ 0x00006E34, 8, 5 }, /*GAIN_ERR_COEFF_5*/
{ 0x00006E34, 16, 5 }, /*GAIN_ERR_COEFF_6*/
{ 0x00006E34, 24, 5 }, /*GAIN_ERR_COEFF_7*/
{ 0x00006E38, 0, 5 }, /*GAIN_ERR_COEFF_8*/
{ 0x00006E38, 8, 5 }, /*GAIN_ERR_COEFF_9*/
{ 0x00006E38, 16, 5 }, /*GAIN_ERR_COEFF_10*/
{ 0x00006E38, 24, 5 }, /*GAIN_ERR_COEFF_11*/
{ 0x00006E3C, 0, 5 }, /*GAIN_ERR_COEFF_12*/
{ 0x00006E3C, 8, 5 }, /*GAIN_ERR_COEFF_13*/
{ 0x00006E3C, 16, 5 }, /*GAIN_ERR_COEFF_14*/
{ 0x00006E3C, 24, 5 }, /*GAIN_ERR_COEFF_15*/
{ 0x00006E40, 0, 5 }, /*GAIN_ERR_COEFF_16*/
{ 0x00006E40, 8, 5 }, /*GAIN_ERR_COEFF_17*/
{ 0x00006E40, 16, 5 }, /*GAIN_ERR_COEFF_18*/
{ 0x00006E40, 24, 5 }, /*GAIN_ERR_COEFF_19*/
{ 0x00006E44, 0, 5 }, /*GAIN_ERR_COEFF_20*/
{ 0x00006E48, 0, 10 }, /*VOFF_GAIN_0*/
{ 0x00006E48, 10, 10 }, /*VOFF_GAIN_1*/
{ 0x00006E48, 20, 10 }, /*VOFF_GAIN_2*/
{ 0x00006E4C, 0, 10 }, /*VOFF_GAIN_3*/
{ 0x00006E4C, 10, 10 }, /*VOFF_GAIN_4*/
{ 0x00006E4C, 20, 10 }, /*VOFF_GAIN_5*/
{ 0x00006E50, 0, 10 }, /*VOFF_GAIN_6*/
{ 0x00006E50, 10, 10 }, /*VOFF_GAIN_7*/
{ 0x00006E50, 20, 10 }, /*VOFF_GAIN_8*/
{ 0x00006E54, 0, 10 }, /*VOFF_GAIN_9*/
{ 0x00006E54, 10, 10 }, /*VOFF_GAIN_10*/
{ 0x00006E54, 20, 10 }, /*VOFF_GAIN_11*/
{ 0x00006E58, 0, 10 }, /*VOFF_GAIN_12*/
{ 0x00006E58, 10, 10 }, /*VOFF_GAIN_13*/
{ 0x00006E58, 20, 10 }, /*VOFF_GAIN_14*/
{ 0x00006E5C, 0, 10 }, /*VOFF_GAIN_15*/
{ 0x00006E5C, 10, 10 }, /*VOFF_GAIN_16*/
{ 0x00006E5C, 20, 10 }, /*VOFF_GAIN_17*/
{ 0x00006E60, 0, 10 }, /*VOFF_GAIN_18*/
{ 0x00006E60, 10, 10 }, /*VOFF_GAIN_19*/
{ 0x00006E60, 20, 10 }, /*VOFF_GAIN_20*/
{ 0x00006E64, 0, 10 }, /*VOFF_INT1*/
{ 0x00007418, 7, 5 }, /*DS_SPK_INT1_CAP_TRIM*/
{ 0x0000741C, 0, 5 }, /*DS_SPK_INT2_CAP_TRIM*/
{ 0x0000741C, 11, 4 }, /*DS_SPK_LPF_CAP_TRIM*/
{ 0x0000741C, 19, 4 }, /*DS_SPK_QUAN_CAP_TRIM*/
{ 0x00007434, 17, 1 }, /*FORCE_CAL*/
{ 0x00007434, 18, 7 }, /*CAL_OVERRIDE*/
{ 0x00007068, 0, 9 }, /*MODIX*/
{ 0x0000410C, 7, 1 }, /*VIMON_DLY_NOT_COMB*/
{ 0x0000400C, 0, 7 }, /*VIMON_DLY*/
{ 0x00004000, 11, 1 }, /*VMON_POL*/
{ 0x00017040, 0, 8 }, /*X_COORDINATE*/
{ 0x00017040, 8, 8 }, /*Y_COORDINATE*/
{ 0x00017040, 16, 8 }, /*WAFER_ID*/
{ 0x00017040, 24, 8 }, /*DVS*/
{ 0x00017044, 0, 24 }, /*LOT_NUMBER*/
};
static const struct reg_sequence cs35l41_reva0_errata_patch[] = {
{ 0x00003854, 0x05180240 },
{ CS35L41_VIMON_SPKMON_RESYNC, 0x00000000 },
{ 0x00004310, 0x00000000 },
{ CS35L41_VPVBST_FS_SEL, 0x00000000 },
{ CS35L41_OTP_TRIM_30, 0x9091A1C8 },
{ 0x00003014, 0x0200EE0E },
{ CS35L41_BSTCVRT_DCM_CTRL, 0x00000051 },
{ 0x00000054, 0x00000004 },
{ CS35L41_IRQ1_DB3, 0x00000000 },
{ CS35L41_IRQ2_DB3, 0x00000000 },
{ CS35L41_DSP1_YM_ACCEL_PL0_PRI, 0x00000000 },
{ CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 },
{ CS35L41_PWR_CTRL2, 0x00000000 },
{ CS35L41_AMP_GAIN_CTRL, 0x00000000 },
{ CS35L41_ASP_TX3_SRC, 0x00000000 },
{ CS35L41_ASP_TX4_SRC, 0x00000000 },
};
static const struct reg_sequence cs35l41_revb0_errata_patch[] = {
{ CS35L41_VIMON_SPKMON_RESYNC, 0x00000000 },
{ 0x00004310, 0x00000000 },
{ CS35L41_VPVBST_FS_SEL, 0x00000000 },
{ CS35L41_BSTCVRT_DCM_CTRL, 0x00000051 },
{ CS35L41_DSP1_YM_ACCEL_PL0_PRI, 0x00000000 },
{ CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 },
{ CS35L41_PWR_CTRL2, 0x00000000 },
{ CS35L41_AMP_GAIN_CTRL, 0x00000000 },
{ CS35L41_ASP_TX3_SRC, 0x00000000 },
{ CS35L41_ASP_TX4_SRC, 0x00000000 },
};
static const struct reg_sequence cs35l41_revb2_errata_patch[] = {
{ CS35L41_VIMON_SPKMON_RESYNC, 0x00000000 },
{ 0x00004310, 0x00000000 },
{ CS35L41_VPVBST_FS_SEL, 0x00000000 },
{ CS35L41_BSTCVRT_DCM_CTRL, 0x00000051 },
{ CS35L41_DSP1_YM_ACCEL_PL0_PRI, 0x00000000 },
{ CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 },
{ CS35L41_PWR_CTRL2, 0x00000000 },
{ CS35L41_AMP_GAIN_CTRL, 0x00000000 },
{ CS35L41_ASP_TX3_SRC, 0x00000000 },
{ CS35L41_ASP_TX4_SRC, 0x00000000 },
};
static const struct reg_sequence cs35l41_fs_errata_patch[] = {
{ CS35L41_DSP1_RX1_RATE, 0x00000001 },
{ CS35L41_DSP1_RX2_RATE, 0x00000001 },
{ CS35L41_DSP1_RX3_RATE, 0x00000001 },
{ CS35L41_DSP1_RX4_RATE, 0x00000001 },
{ CS35L41_DSP1_RX5_RATE, 0x00000001 },
{ CS35L41_DSP1_RX6_RATE, 0x00000001 },
{ CS35L41_DSP1_RX7_RATE, 0x00000001 },
{ CS35L41_DSP1_RX8_RATE, 0x00000001 },
{ CS35L41_DSP1_TX1_RATE, 0x00000001 },
{ CS35L41_DSP1_TX2_RATE, 0x00000001 },
{ CS35L41_DSP1_TX3_RATE, 0x00000001 },
{ CS35L41_DSP1_TX4_RATE, 0x00000001 },
{ CS35L41_DSP1_TX5_RATE, 0x00000001 },
{ CS35L41_DSP1_TX6_RATE, 0x00000001 },
{ CS35L41_DSP1_TX7_RATE, 0x00000001 },
{ CS35L41_DSP1_TX8_RATE, 0x00000001 },
};
static const struct cs35l41_otp_map_element_t cs35l41_otp_map_map[] = {
{
.id = 0x01,
.map = otp_map_1,
.num_elements = ARRAY_SIZE(otp_map_1),
.bit_offset = 16,
.word_offset = 2,
},
{
.id = 0x02,
.map = otp_map_2,
.num_elements = ARRAY_SIZE(otp_map_2),
.bit_offset = 16,
.word_offset = 2,
},
{
.id = 0x03,
.map = otp_map_2,
.num_elements = ARRAY_SIZE(otp_map_2),
.bit_offset = 16,
.word_offset = 2,
},
{
.id = 0x06,
.map = otp_map_2,
.num_elements = ARRAY_SIZE(otp_map_2),
.bit_offset = 16,
.word_offset = 2,
},
{
.id = 0x08,
.map = otp_map_1,
.num_elements = ARRAY_SIZE(otp_map_1),
.bit_offset = 16,
.word_offset = 2,
},
};
struct regmap_config cs35l41_regmap_i2c = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = CS35L41_REGSTRIDE,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = CS35L41_LASTREG,
.reg_defaults = cs35l41_reg,
.num_reg_defaults = ARRAY_SIZE(cs35l41_reg),
.volatile_reg = cs35l41_volatile_reg,
.readable_reg = cs35l41_readable_reg,
.precious_reg = cs35l41_precious_reg,
.cache_type = REGCACHE_MAPLE,
};
EXPORT_SYMBOL_GPL(cs35l41_regmap_i2c);
struct regmap_config cs35l41_regmap_spi = {
.reg_bits = 32,
.val_bits = 32,
.pad_bits = 16,
.reg_stride = CS35L41_REGSTRIDE,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = CS35L41_LASTREG,
.reg_defaults = cs35l41_reg,
.num_reg_defaults = ARRAY_SIZE(cs35l41_reg),
.volatile_reg = cs35l41_volatile_reg,
.readable_reg = cs35l41_readable_reg,
.precious_reg = cs35l41_precious_reg,
.cache_type = REGCACHE_MAPLE,
};
EXPORT_SYMBOL_GPL(cs35l41_regmap_spi);
static const struct cs35l41_otp_map_element_t *cs35l41_find_otp_map(u32 otp_id)
{
int i;
for (i = 0; i < ARRAY_SIZE(cs35l41_otp_map_map); i++) {
if (cs35l41_otp_map_map[i].id == otp_id)
return &cs35l41_otp_map_map[i];
}
return NULL;
}
int cs35l41_test_key_unlock(struct device *dev, struct regmap *regmap)
{
static const struct reg_sequence unlock[] = {
{ CS35L41_TEST_KEY_CTL, 0x00000055 },
{ CS35L41_TEST_KEY_CTL, 0x000000AA },
};
int ret;
ret = regmap_multi_reg_write(regmap, unlock, ARRAY_SIZE(unlock));
if (ret)
dev_err(dev, "Failed to unlock test key: %d\n", ret);
return ret;
}
EXPORT_SYMBOL_GPL(cs35l41_test_key_unlock);
int cs35l41_test_key_lock(struct device *dev, struct regmap *regmap)
{
static const struct reg_sequence unlock[] = {
{ CS35L41_TEST_KEY_CTL, 0x000000CC },
{ CS35L41_TEST_KEY_CTL, 0x00000033 },
};
int ret;
ret = regmap_multi_reg_write(regmap, unlock, ARRAY_SIZE(unlock));
if (ret)
dev_err(dev, "Failed to lock test key: %d\n", ret);
return ret;
}
EXPORT_SYMBOL_GPL(cs35l41_test_key_lock);
/* Must be called with the TEST_KEY unlocked */
int cs35l41_otp_unpack(struct device *dev, struct regmap *regmap)
{
const struct cs35l41_otp_map_element_t *otp_map_match;
const struct cs35l41_otp_packed_element_t *otp_map;
int bit_offset, word_offset, ret, i;
unsigned int bit_sum = 8;
u32 otp_val, otp_id_reg;
u32 *otp_mem;
otp_mem = kmalloc_array(CS35L41_OTP_SIZE_WORDS, sizeof(*otp_mem), GFP_KERNEL);
if (!otp_mem)
return -ENOMEM;
ret = regmap_read(regmap, CS35L41_OTPID, &otp_id_reg);
if (ret) {
dev_err(dev, "Read OTP ID failed: %d\n", ret);
goto err_otp_unpack;
}
otp_map_match = cs35l41_find_otp_map(otp_id_reg);
if (!otp_map_match) {
dev_err(dev, "OTP Map matching ID %d not found\n", otp_id_reg);
ret = -EINVAL;
goto err_otp_unpack;
}
ret = regmap_bulk_read(regmap, CS35L41_OTP_MEM0, otp_mem, CS35L41_OTP_SIZE_WORDS);
if (ret) {
dev_err(dev, "Read OTP Mem failed: %d\n", ret);
goto err_otp_unpack;
}
otp_map = otp_map_match->map;
bit_offset = otp_map_match->bit_offset;
word_offset = otp_map_match->word_offset;
for (i = 0; i < otp_map_match->num_elements; i++) {
dev_dbg(dev, "bitoffset= %d, word_offset=%d, bit_sum mod 32=%d, otp_map[i].size = %u\n",
bit_offset, word_offset, bit_sum % 32, otp_map[i].size);
if (bit_offset + otp_map[i].size - 1 >= 32) {
otp_val = (otp_mem[word_offset] &
GENMASK(31, bit_offset)) >> bit_offset;
otp_val |= (otp_mem[++word_offset] &
GENMASK(bit_offset + otp_map[i].size - 33, 0)) <<
(32 - bit_offset);
bit_offset += otp_map[i].size - 32;
} else if (bit_offset + otp_map[i].size - 1 >= 0) {
otp_val = (otp_mem[word_offset] &
GENMASK(bit_offset + otp_map[i].size - 1, bit_offset)
) >> bit_offset;
bit_offset += otp_map[i].size;
} else /* both bit_offset and otp_map[i].size are 0 */
otp_val = 0;
bit_sum += otp_map[i].size;
if (bit_offset == 32) {
bit_offset = 0;
word_offset++;
}
if (otp_map[i].reg != 0) {
ret = regmap_update_bits(regmap, otp_map[i].reg,
GENMASK(otp_map[i].shift + otp_map[i].size - 1,
otp_map[i].shift),
otp_val << otp_map[i].shift);
if (ret < 0) {
dev_err(dev, "Write OTP val failed: %d\n", ret);
goto err_otp_unpack;
}
}
}
ret = 0;
err_otp_unpack:
kfree(otp_mem);
return ret;
}
EXPORT_SYMBOL_GPL(cs35l41_otp_unpack);
/* Must be called with the TEST_KEY unlocked */
int cs35l41_register_errata_patch(struct device *dev, struct regmap *reg, unsigned int reg_revid)
{
char *rev;
int ret;
switch (reg_revid) {
case CS35L41_REVID_A0:
ret = regmap_register_patch(reg, cs35l41_reva0_errata_patch,
ARRAY_SIZE(cs35l41_reva0_errata_patch));
rev = "A0";
break;
case CS35L41_REVID_B0:
ret = regmap_register_patch(reg, cs35l41_revb0_errata_patch,
ARRAY_SIZE(cs35l41_revb0_errata_patch));
rev = "B0";
break;
case CS35L41_REVID_B2:
ret = regmap_register_patch(reg, cs35l41_revb2_errata_patch,
ARRAY_SIZE(cs35l41_revb2_errata_patch));
rev = "B2";
break;
default:
ret = -EINVAL;
rev = "XX";
break;
}
if (ret)
dev_err(dev, "Failed to apply %s errata patch: %d\n", rev, ret);
ret = regmap_write(reg, CS35L41_DSP1_CCM_CORE_CTRL, 0);
if (ret < 0)
dev_err(dev, "Write CCM_CORE_CTRL failed: %d\n", ret);
return ret;
}
EXPORT_SYMBOL_GPL(cs35l41_register_errata_patch);
int cs35l41_set_channels(struct device *dev, struct regmap *reg,
unsigned int tx_num, unsigned int *tx_slot,
unsigned int rx_num, unsigned int *rx_slot)
{
unsigned int val, mask;
int i;
if (tx_num > 4 || rx_num > 2)
return -EINVAL;
val = 0;
mask = 0;
for (i = 0; i < rx_num; i++) {
dev_dbg(dev, "rx slot %d position = %d\n", i, rx_slot[i]);
val |= rx_slot[i] << (i * 8);
mask |= 0x3F << (i * 8);
}
regmap_update_bits(reg, CS35L41_SP_FRAME_RX_SLOT, mask, val);
val = 0;
mask = 0;
for (i = 0; i < tx_num; i++) {
dev_dbg(dev, "tx slot %d position = %d\n", i, tx_slot[i]);
val |= tx_slot[i] << (i * 8);
mask |= 0x3F << (i * 8);
}
regmap_update_bits(reg, CS35L41_SP_FRAME_TX_SLOT, mask, val);
return 0;
}
EXPORT_SYMBOL_GPL(cs35l41_set_channels);
static const unsigned char cs35l41_bst_k1_table[4][5] = {
{ 0x24, 0x32, 0x32, 0x4F, 0x57 },
{ 0x24, 0x32, 0x32, 0x4F, 0x57 },
{ 0x40, 0x32, 0x32, 0x4F, 0x57 },
{ 0x40, 0x32, 0x32, 0x4F, 0x57 }
};
static const unsigned char cs35l41_bst_k2_table[4][5] = {
{ 0x24, 0x49, 0x66, 0xA3, 0xEA },
{ 0x24, 0x49, 0x66, 0xA3, 0xEA },
{ 0x48, 0x49, 0x66, 0xA3, 0xEA },
{ 0x48, 0x49, 0x66, 0xA3, 0xEA }
};
static const unsigned char cs35l41_bst_slope_table[4] = {
0x75, 0x6B, 0x3B, 0x28
};
static int cs35l41_boost_config(struct device *dev, struct regmap *regmap, int boost_ind,
int boost_cap, int boost_ipk)
{
unsigned char bst_lbst_val, bst_cbst_range, bst_ipk_scaled;
int ret;
switch (boost_ind) {
case 1000: /* 1.0 uH */
bst_lbst_val = 0;
break;
case 1200: /* 1.2 uH */
bst_lbst_val = 1;
break;
case 1500: /* 1.5 uH */
bst_lbst_val = 2;
break;
case 2200: /* 2.2 uH */
bst_lbst_val = 3;
break;
default:
dev_err(dev, "Invalid boost inductor value: %d nH\n", boost_ind);
return -EINVAL;
}
switch (boost_cap) {
case 0 ... 19:
bst_cbst_range = 0;
break;
case 20 ... 50:
bst_cbst_range = 1;
break;
case 51 ... 100:
bst_cbst_range = 2;
break;
case 101 ... 200:
bst_cbst_range = 3;
break;
default:
if (boost_cap < 0) {
dev_err(dev, "Invalid boost capacitor value: %d nH\n", boost_cap);
return -EINVAL;
}
/* 201 uF and greater */
bst_cbst_range = 4;
}
if (boost_ipk < 1600 || boost_ipk > 4500) {
dev_err(dev, "Invalid boost inductor peak current: %d mA\n", boost_ipk);
return -EINVAL;
}
ret = regmap_update_bits(regmap, CS35L41_BSTCVRT_COEFF,
CS35L41_BST_K1_MASK | CS35L41_BST_K2_MASK,
cs35l41_bst_k1_table[bst_lbst_val][bst_cbst_range]
<< CS35L41_BST_K1_SHIFT |
cs35l41_bst_k2_table[bst_lbst_val][bst_cbst_range]
<< CS35L41_BST_K2_SHIFT);
if (ret) {
dev_err(dev, "Failed to write boost coefficients: %d\n", ret);
return ret;
}
ret = regmap_update_bits(regmap, CS35L41_BSTCVRT_SLOPE_LBST,
CS35L41_BST_SLOPE_MASK | CS35L41_BST_LBST_VAL_MASK,
cs35l41_bst_slope_table[bst_lbst_val]
<< CS35L41_BST_SLOPE_SHIFT |
bst_lbst_val << CS35L41_BST_LBST_VAL_SHIFT);
if (ret) {
dev_err(dev, "Failed to write boost slope/inductor value: %d\n", ret);
return ret;
}
bst_ipk_scaled = ((boost_ipk - 1600) / 50) + 0x10;
ret = regmap_update_bits(regmap, CS35L41_BSTCVRT_PEAK_CUR, CS35L41_BST_IPK_MASK,
bst_ipk_scaled << CS35L41_BST_IPK_SHIFT);
if (ret) {
dev_err(dev, "Failed to write boost inductor peak current: %d\n", ret);
return ret;
}
regmap_update_bits(regmap, CS35L41_PWR_CTRL2, CS35L41_BST_EN_MASK,
CS35L41_BST_EN_DEFAULT << CS35L41_BST_EN_SHIFT);
return 0;
}
static const struct reg_sequence cs35l41_safe_to_reset[] = {
{ 0x00000040, 0x00000055 },
{ 0x00000040, 0x000000AA },
{ 0x0000393C, 0x000000C0, 6000},
{ 0x0000393C, 0x00000000 },
{ 0x00007414, 0x00C82222 },
{ 0x0000742C, 0x00000000 },
{ 0x00000040, 0x000000CC },
{ 0x00000040, 0x00000033 },
};
static const struct reg_sequence cs35l41_active_to_safe_start[] = {
{ 0x00000040, 0x00000055 },
{ 0x00000040, 0x000000AA },
{ 0x00007438, 0x00585941 },
{ CS35L41_PWR_CTRL1, 0x00000000 },
{ 0x0000742C, 0x00000009 },
};
static const struct reg_sequence cs35l41_active_to_safe_end[] = {
{ 0x00007438, 0x00580941 },
{ 0x00000040, 0x000000CC },
{ 0x00000040, 0x00000033 },
};
static const struct reg_sequence cs35l41_safe_to_active_start[] = {
{ 0x00000040, 0x00000055 },
{ 0x00000040, 0x000000AA },
{ 0x0000742C, 0x0000000F },
{ 0x0000742C, 0x00000079 },
{ 0x00007438, 0x00585941 },
{ CS35L41_PWR_CTRL1, 0x00000001 }, // GLOBAL_EN = 1
};
static const struct reg_sequence cs35l41_safe_to_active_en_spk[] = {
{ 0x0000742C, 0x000000F9 },
{ 0x00007438, 0x00580941 },
};
static const struct reg_sequence cs35l41_reset_to_safe[] = {
{ 0x00000040, 0x00000055 },
{ 0x00000040, 0x000000AA },
{ 0x00007438, 0x00585941 },
{ 0x00007414, 0x08C82222 },
{ 0x0000742C, 0x00000009 },
{ 0x00000040, 0x000000CC },
{ 0x00000040, 0x00000033 },
};
static const struct reg_sequence cs35l41_actv_seq[] = {
/* SYNC_BST_CTL_RX_EN = 1; SYNC_BST_CTL_TX_EN = 1 */
{CS35L41_MDSYNC_EN, 0x00003000},
/* BST_CTL_SEL = MDSYNC */
{CS35L41_BSTCVRT_VCTRL2, 0x00000002},
};
static const struct reg_sequence cs35l41_pass_seq[] = {
/* SYNC_BST_CTL_RX_EN = 0; SYNC_BST_CTL_TX_EN = 1 */
{CS35L41_MDSYNC_EN, 0x00001000},
/* BST_EN = 0 */
{CS35L41_PWR_CTRL2, 0x00003300},
/* BST_CTL_SEL = MDSYNC */
{CS35L41_BSTCVRT_VCTRL2, 0x00000002},
};
int cs35l41_init_boost(struct device *dev, struct regmap *regmap,
struct cs35l41_hw_cfg *hw_cfg)
{
int ret;
switch (hw_cfg->bst_type) {
case CS35L41_SHD_BOOST_ACTV:
regmap_multi_reg_write(regmap, cs35l41_actv_seq, ARRAY_SIZE(cs35l41_actv_seq));
fallthrough;
case CS35L41_INT_BOOST:
ret = cs35l41_boost_config(dev, regmap, hw_cfg->bst_ind,
hw_cfg->bst_cap, hw_cfg->bst_ipk);
if (ret)
dev_err(dev, "Error in Boost DT config: %d\n", ret);
break;
case CS35L41_EXT_BOOST:
case CS35L41_EXT_BOOST_NO_VSPK_SWITCH:
/* Only CLSA0100 doesn't use GPIO as VSPK switch, but even on that laptop we can
* toggle GPIO1 as is not connected to anything.
* There will be no other device without VSPK switch.
*/
regmap_write(regmap, CS35L41_GPIO1_CTRL1, 0x00000001);
regmap_multi_reg_write(regmap, cs35l41_reset_to_safe,
ARRAY_SIZE(cs35l41_reset_to_safe));
ret = regmap_update_bits(regmap, CS35L41_PWR_CTRL2, CS35L41_BST_EN_MASK,
CS35L41_BST_DIS_FET_OFF << CS35L41_BST_EN_SHIFT);
break;
case CS35L41_SHD_BOOST_PASS:
ret = regmap_multi_reg_write(regmap, cs35l41_pass_seq,
ARRAY_SIZE(cs35l41_pass_seq));
break;
default:
dev_err(dev, "Boost type %d not supported\n", hw_cfg->bst_type);
ret = -EINVAL;
break;
}
return ret;
}
EXPORT_SYMBOL_GPL(cs35l41_init_boost);
bool cs35l41_safe_reset(struct regmap *regmap, enum cs35l41_boost_type b_type)
{
switch (b_type) {
/* There is only one laptop that doesn't have VSPK switch. */
case CS35L41_EXT_BOOST_NO_VSPK_SWITCH:
return false;
case CS35L41_EXT_BOOST:
regmap_write(regmap, CS35L41_GPIO1_CTRL1, 0x00000001);
regmap_multi_reg_write(regmap, cs35l41_safe_to_reset,
ARRAY_SIZE(cs35l41_safe_to_reset));
return true;
default:
return true;
}
}
EXPORT_SYMBOL_GPL(cs35l41_safe_reset);
int cs35l41_global_enable(struct device *dev, struct regmap *regmap, enum cs35l41_boost_type b_type,
int enable, struct completion *pll_lock, bool firmware_running)
{
int ret;
unsigned int gpio1_func, pad_control, pwr_ctrl1, pwr_ctrl3, int_status, pup_pdn_mask;
unsigned int pwr_ctl1_val;
struct reg_sequence cs35l41_mdsync_down_seq[] = {
{CS35L41_PWR_CTRL3, 0},
{CS35L41_GPIO_PAD_CONTROL, 0},
{CS35L41_PWR_CTRL1, 0, 3000},
};
struct reg_sequence cs35l41_mdsync_up_seq[] = {
{CS35L41_PWR_CTRL3, 0},
{CS35L41_PWR_CTRL1, 0x00000000, 3000},
{CS35L41_PWR_CTRL1, 0x00000001, 3000},
};
pup_pdn_mask = enable ? CS35L41_PUP_DONE_MASK : CS35L41_PDN_DONE_MASK;
ret = regmap_read(regmap, CS35L41_PWR_CTRL1, &pwr_ctl1_val);
if (ret)
return ret;
if ((pwr_ctl1_val & CS35L41_GLOBAL_EN_MASK) && enable) {
dev_dbg(dev, "Cannot set Global Enable - already set.\n");
return 0;
} else if (!(pwr_ctl1_val & CS35L41_GLOBAL_EN_MASK) && !enable) {
dev_dbg(dev, "Cannot unset Global Enable - not set.\n");
return 0;
}
switch (b_type) {
case CS35L41_SHD_BOOST_ACTV:
case CS35L41_SHD_BOOST_PASS:
regmap_read(regmap, CS35L41_PWR_CTRL3, &pwr_ctrl3);
regmap_read(regmap, CS35L41_GPIO_PAD_CONTROL, &pad_control);
pwr_ctrl3 &= ~CS35L41_SYNC_EN_MASK;
pwr_ctrl1 = enable << CS35L41_GLOBAL_EN_SHIFT;
gpio1_func = enable ? CS35L41_GPIO1_MDSYNC : CS35L41_GPIO1_HIZ;
gpio1_func <<= CS35L41_GPIO1_CTRL_SHIFT;
pad_control &= ~CS35L41_GPIO1_CTRL_MASK;
pad_control |= gpio1_func & CS35L41_GPIO1_CTRL_MASK;
cs35l41_mdsync_down_seq[0].def = pwr_ctrl3;
cs35l41_mdsync_down_seq[1].def = pad_control;
cs35l41_mdsync_down_seq[2].def = pwr_ctrl1;
ret = regmap_multi_reg_write(regmap, cs35l41_mdsync_down_seq,
ARRAY_SIZE(cs35l41_mdsync_down_seq));
if (!enable)
break;
if (!pll_lock)
return -EINVAL;
ret = wait_for_completion_timeout(pll_lock, msecs_to_jiffies(1000));
if (ret == 0) {
ret = -ETIMEDOUT;
} else {
regmap_read(regmap, CS35L41_PWR_CTRL3, &pwr_ctrl3);
pwr_ctrl3 |= CS35L41_SYNC_EN_MASK;
cs35l41_mdsync_up_seq[0].def = pwr_ctrl3;
ret = regmap_multi_reg_write(regmap, cs35l41_mdsync_up_seq,
ARRAY_SIZE(cs35l41_mdsync_up_seq));
}
ret = regmap_read_poll_timeout(regmap, CS35L41_IRQ1_STATUS1,
int_status, int_status & pup_pdn_mask,
1000, 100000);
if (ret)
dev_err(dev, "Enable(%d) failed: %d\n", enable, ret);
// Clear PUP/PDN status
regmap_write(regmap, CS35L41_IRQ1_STATUS1, pup_pdn_mask);
break;
case CS35L41_INT_BOOST:
ret = regmap_update_bits(regmap, CS35L41_PWR_CTRL1, CS35L41_GLOBAL_EN_MASK,
enable << CS35L41_GLOBAL_EN_SHIFT);
if (ret) {
dev_err(dev, "CS35L41_PWR_CTRL1 set failed: %d\n", ret);
return ret;
}
ret = regmap_read_poll_timeout(regmap, CS35L41_IRQ1_STATUS1,
int_status, int_status & pup_pdn_mask,
1000, 100000);
if (ret)
dev_err(dev, "Enable(%d) failed: %d\n", enable, ret);
/* Clear PUP/PDN status */
regmap_write(regmap, CS35L41_IRQ1_STATUS1, pup_pdn_mask);
break;
case CS35L41_EXT_BOOST:
case CS35L41_EXT_BOOST_NO_VSPK_SWITCH:
if (enable) {
/* Test Key is unlocked here */
ret = regmap_multi_reg_write(regmap, cs35l41_safe_to_active_start,
ARRAY_SIZE(cs35l41_safe_to_active_start));
if (ret)
return ret;
ret = regmap_read_poll_timeout(regmap, CS35L41_IRQ1_STATUS1, int_status,
int_status & CS35L41_PUP_DONE_MASK, 1000, 100000);
if (ret) {
dev_err(dev, "Failed waiting for CS35L41_PUP_DONE_MASK: %d\n", ret);
/* Lock the test key, it was unlocked during the multi_reg_write */
cs35l41_test_key_lock(dev, regmap);
return ret;
}
regmap_write(regmap, CS35L41_IRQ1_STATUS1, CS35L41_PUP_DONE_MASK);
if (firmware_running)
ret = cs35l41_set_cspl_mbox_cmd(dev, regmap,
CSPL_MBOX_CMD_SPK_OUT_ENABLE);
else
ret = regmap_multi_reg_write(regmap, cs35l41_safe_to_active_en_spk,
ARRAY_SIZE(cs35l41_safe_to_active_en_spk));
/* Lock the test key, it was unlocked during the multi_reg_write */
cs35l41_test_key_lock(dev, regmap);
} else {
/* Test Key is unlocked here */
ret = regmap_multi_reg_write(regmap, cs35l41_active_to_safe_start,
ARRAY_SIZE(cs35l41_active_to_safe_start));
if (ret) {
/* Lock the test key, it was unlocked during the multi_reg_write */
cs35l41_test_key_lock(dev, regmap);
return ret;
}
ret = regmap_read_poll_timeout(regmap, CS35L41_IRQ1_STATUS1, int_status,
int_status & CS35L41_PDN_DONE_MASK, 1000, 100000);
if (ret) {
dev_err(dev, "Failed waiting for CS35L41_PDN_DONE_MASK: %d\n", ret);
/* Lock the test key, it was unlocked during the multi_reg_write */
cs35l41_test_key_lock(dev, regmap);
return ret;
}
regmap_write(regmap, CS35L41_IRQ1_STATUS1, CS35L41_PDN_DONE_MASK);
/* Test Key is locked here */
ret = regmap_multi_reg_write(regmap, cs35l41_active_to_safe_end,
ARRAY_SIZE(cs35l41_active_to_safe_end));
}
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
EXPORT_SYMBOL_GPL(cs35l41_global_enable);
int cs35l41_gpio_config(struct regmap *regmap, struct cs35l41_hw_cfg *hw_cfg)
{
struct cs35l41_gpio_cfg *gpio1 = &hw_cfg->gpio1;
struct cs35l41_gpio_cfg *gpio2 = &hw_cfg->gpio2;
int irq_pol = IRQF_TRIGGER_NONE;
regmap_update_bits(regmap, CS35L41_GPIO1_CTRL1,
CS35L41_GPIO_POL_MASK | CS35L41_GPIO_DIR_MASK,
gpio1->pol_inv << CS35L41_GPIO_POL_SHIFT |
!gpio1->out_en << CS35L41_GPIO_DIR_SHIFT);
regmap_update_bits(regmap, CS35L41_GPIO2_CTRL1,
CS35L41_GPIO_POL_MASK | CS35L41_GPIO_DIR_MASK,
gpio2->pol_inv << CS35L41_GPIO_POL_SHIFT |
!gpio2->out_en << CS35L41_GPIO_DIR_SHIFT);
if (gpio1->valid)
regmap_update_bits(regmap, CS35L41_GPIO_PAD_CONTROL, CS35L41_GPIO1_CTRL_MASK,
gpio1->func << CS35L41_GPIO1_CTRL_SHIFT);
if (gpio2->valid) {
regmap_update_bits(regmap, CS35L41_GPIO_PAD_CONTROL, CS35L41_GPIO2_CTRL_MASK,
gpio2->func << CS35L41_GPIO2_CTRL_SHIFT);
switch (gpio2->func) {
case CS35L41_GPIO2_INT_PUSH_PULL_LOW:
case CS35L41_GPIO2_INT_OPEN_DRAIN:
irq_pol = IRQF_TRIGGER_LOW;
break;
case CS35L41_GPIO2_INT_PUSH_PULL_HIGH:
irq_pol = IRQF_TRIGGER_HIGH;
break;
default:
break;
}
}
return irq_pol;
}
EXPORT_SYMBOL_GPL(cs35l41_gpio_config);
static const struct cs_dsp_region cs35l41_dsp1_regions[] = {
{ .type = WMFW_HALO_PM_PACKED, .base = CS35L41_DSP1_PMEM_0 },
{ .type = WMFW_HALO_XM_PACKED, .base = CS35L41_DSP1_XMEM_PACK_0 },
{ .type = WMFW_HALO_YM_PACKED, .base = CS35L41_DSP1_YMEM_PACK_0 },
{. type = WMFW_ADSP2_XM, .base = CS35L41_DSP1_XMEM_UNPACK24_0},
{. type = WMFW_ADSP2_YM, .base = CS35L41_DSP1_YMEM_UNPACK24_0},
};
void cs35l41_configure_cs_dsp(struct device *dev, struct regmap *reg, struct cs_dsp *dsp)
{
dsp->num = 1;
dsp->type = WMFW_HALO;
dsp->rev = 0;
dsp->dev = dev;
dsp->regmap = reg;
dsp->base = CS35L41_DSP1_CTRL_BASE;
dsp->base_sysinfo = CS35L41_DSP1_SYS_ID;
dsp->mem = cs35l41_dsp1_regions;
dsp->num_mems = ARRAY_SIZE(cs35l41_dsp1_regions);
dsp->lock_regions = 0xFFFFFFFF;
}
EXPORT_SYMBOL_GPL(cs35l41_configure_cs_dsp);
static bool cs35l41_check_cspl_mbox_sts(enum cs35l41_cspl_mbox_cmd cmd,
enum cs35l41_cspl_mbox_status sts)
{
switch (cmd) {
case CSPL_MBOX_CMD_NONE:
case CSPL_MBOX_CMD_UNKNOWN_CMD:
return true;
case CSPL_MBOX_CMD_PAUSE:
case CSPL_MBOX_CMD_OUT_OF_HIBERNATE:
return (sts == CSPL_MBOX_STS_PAUSED);
case CSPL_MBOX_CMD_RESUME:
return (sts == CSPL_MBOX_STS_RUNNING);
case CSPL_MBOX_CMD_REINIT:
return (sts == CSPL_MBOX_STS_RUNNING);
case CSPL_MBOX_CMD_STOP_PRE_REINIT:
return (sts == CSPL_MBOX_STS_RDY_FOR_REINIT);
case CSPL_MBOX_CMD_SPK_OUT_ENABLE:
return (sts == CSPL_MBOX_STS_RUNNING);
default:
return false;
}
}
int cs35l41_set_cspl_mbox_cmd(struct device *dev, struct regmap *regmap,
enum cs35l41_cspl_mbox_cmd cmd)
{
unsigned int sts = 0, i;
int ret;
// Set mailbox cmd
ret = regmap_write(regmap, CS35L41_DSP_VIRT1_MBOX_1, cmd);
if (ret < 0) {
if (cmd != CSPL_MBOX_CMD_OUT_OF_HIBERNATE)
dev_err(dev, "Failed to write MBOX: %d\n", ret);
return ret;
}
// Read mailbox status and verify it is appropriate for the given cmd
for (i = 0; i < 5; i++) {
usleep_range(1000, 1100);
ret = regmap_read(regmap, CS35L41_DSP_MBOX_2, &sts);
if (ret < 0) {
dev_err(dev, "Failed to read MBOX STS: %d\n", ret);
continue;
}
if (!cs35l41_check_cspl_mbox_sts(cmd, sts))
dev_dbg(dev, "[%u] cmd %u returned invalid sts %u", i, cmd, sts);
else
return 0;
}
if (cmd != CSPL_MBOX_CMD_OUT_OF_HIBERNATE)
dev_err(dev, "Failed to set mailbox cmd %u (status %u)\n", cmd, sts);
return -ENOMSG;
}
EXPORT_SYMBOL_GPL(cs35l41_set_cspl_mbox_cmd);
int cs35l41_write_fs_errata(struct device *dev, struct regmap *regmap)
{
int ret;
ret = regmap_multi_reg_write(regmap, cs35l41_fs_errata_patch,
ARRAY_SIZE(cs35l41_fs_errata_patch));
if (ret < 0)
dev_err(dev, "Failed to write fs errata: %d\n", ret);
return ret;
}
EXPORT_SYMBOL_GPL(cs35l41_write_fs_errata);
int cs35l41_enter_hibernate(struct device *dev, struct regmap *regmap,
enum cs35l41_boost_type b_type)
{
if (!cs35l41_safe_reset(regmap, b_type)) {
dev_dbg(dev, "System does not support Suspend\n");
return -EINVAL;
}
dev_dbg(dev, "Enter hibernate\n");
regmap_write(regmap, CS35L41_WAKESRC_CTL, 0x0088);
regmap_write(regmap, CS35L41_WAKESRC_CTL, 0x0188);
// Don't wait for ACK since bus activity would wake the device
regmap_write(regmap, CS35L41_DSP_VIRT1_MBOX_1, CSPL_MBOX_CMD_HIBERNATE);
return 0;
}
EXPORT_SYMBOL_GPL(cs35l41_enter_hibernate);
static void cs35l41_wait_for_pwrmgt_sts(struct device *dev, struct regmap *regmap)
{
const int pwrmgt_retries = 10;
unsigned int sts;
int i, ret;
for (i = 0; i < pwrmgt_retries; i++) {
ret = regmap_read(regmap, CS35L41_PWRMGT_STS, &sts);
if (ret)
dev_err(dev, "Failed to read PWRMGT_STS: %d\n", ret);
else if (!(sts & CS35L41_WR_PEND_STS_MASK))
return;
udelay(20);
}
dev_err(dev, "Timed out reading PWRMGT_STS\n");
}
int cs35l41_exit_hibernate(struct device *dev, struct regmap *regmap)
{
const int wake_retries = 20;
const int sleep_retries = 5;
int ret, i, j;
for (i = 0; i < sleep_retries; i++) {
dev_dbg(dev, "Exit hibernate\n");
for (j = 0; j < wake_retries; j++) {
ret = cs35l41_set_cspl_mbox_cmd(dev, regmap,
CSPL_MBOX_CMD_OUT_OF_HIBERNATE);
if (!ret)
break;
usleep_range(100, 200);
}
if (j < wake_retries) {
dev_dbg(dev, "Wake success at cycle: %d\n", j);
return 0;
}
dev_err(dev, "Wake failed, re-enter hibernate: %d\n", ret);
cs35l41_wait_for_pwrmgt_sts(dev, regmap);
regmap_write(regmap, CS35L41_WAKESRC_CTL, 0x0088);
cs35l41_wait_for_pwrmgt_sts(dev, regmap);
regmap_write(regmap, CS35L41_WAKESRC_CTL, 0x0188);
cs35l41_wait_for_pwrmgt_sts(dev, regmap);
regmap_write(regmap, CS35L41_PWRMGT_CTL, 0x3);
}
dev_err(dev, "Timed out waking device\n");
return -ETIMEDOUT;
}
EXPORT_SYMBOL_GPL(cs35l41_exit_hibernate);
MODULE_DESCRIPTION("CS35L41 library");
MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, <[email protected]>");
MODULE_AUTHOR("Lucas Tanure, Cirrus Logic Inc, <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cs35l41-lib.c |
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