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// SPDX-License-Identifier: GPL-2.0-only
//
// rt1015p.c -- RT1015P ALSA SoC audio amplifier driver
//
// Copyright 2020 The Linux Foundation. All rights reserved.
#include <linux/acpi.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/gpio/consumer.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include <sound/soc-dapm.h>
struct rt1015p_priv {
struct gpio_desc *sdb;
bool calib_done;
};
static int rt1015p_sdb_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt1015p_priv *rt1015p =
snd_soc_component_get_drvdata(component);
if (!rt1015p->sdb)
return 0;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
gpiod_set_value_cansleep(rt1015p->sdb, 1);
dev_dbg(component->dev, "set sdb to 1");
if (!rt1015p->calib_done) {
msleep(300);
rt1015p->calib_done = true;
}
break;
case SND_SOC_DAPM_POST_PMD:
gpiod_set_value_cansleep(rt1015p->sdb, 0);
dev_dbg(component->dev, "set sdb to 0");
break;
default:
break;
}
return 0;
}
static const struct snd_soc_dapm_widget rt1015p_dapm_widgets[] = {
SND_SOC_DAPM_OUTPUT("Speaker"),
SND_SOC_DAPM_OUT_DRV_E("SDB", SND_SOC_NOPM, 0, 0, NULL, 0,
rt1015p_sdb_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
};
static const struct snd_soc_dapm_route rt1015p_dapm_routes[] = {
{"SDB", NULL, "HiFi Playback"},
{"Speaker", NULL, "SDB"},
};
#ifdef CONFIG_PM
static int rt1015p_suspend(struct snd_soc_component *component)
{
struct rt1015p_priv *rt1015p = snd_soc_component_get_drvdata(component);
rt1015p->calib_done = false;
return 0;
}
#else
#define rt1015p_suspend NULL
#endif
static const struct snd_soc_component_driver rt1015p_component_driver = {
.suspend = rt1015p_suspend,
.dapm_widgets = rt1015p_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt1015p_dapm_widgets),
.dapm_routes = rt1015p_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(rt1015p_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static struct snd_soc_dai_driver rt1015p_dai_driver = {
.name = "HiFi",
.playback = {
.stream_name = "HiFi Playback",
.formats = SNDRV_PCM_FMTBIT_S24 |
SNDRV_PCM_FMTBIT_S32,
.rates = SNDRV_PCM_RATE_48000,
.channels_min = 1,
.channels_max = 2,
},
};
static int rt1015p_platform_probe(struct platform_device *pdev)
{
struct rt1015p_priv *rt1015p;
rt1015p = devm_kzalloc(&pdev->dev, sizeof(*rt1015p), GFP_KERNEL);
if (!rt1015p)
return -ENOMEM;
rt1015p->sdb = devm_gpiod_get_optional(&pdev->dev,
"sdb", GPIOD_OUT_LOW);
if (IS_ERR(rt1015p->sdb))
return PTR_ERR(rt1015p->sdb);
dev_set_drvdata(&pdev->dev, rt1015p);
return devm_snd_soc_register_component(&pdev->dev,
&rt1015p_component_driver,
&rt1015p_dai_driver, 1);
}
#ifdef CONFIG_OF
static const struct of_device_id rt1015p_device_id[] = {
{ .compatible = "realtek,rt1015p" },
{ .compatible = "realtek,rt1019p" },
{}
};
MODULE_DEVICE_TABLE(of, rt1015p_device_id);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id rt1015p_acpi_match[] = {
{ "RTL1015", 0},
{ "RTL1019", 0},
{ },
};
MODULE_DEVICE_TABLE(acpi, rt1015p_acpi_match);
#endif
static struct platform_driver rt1015p_platform_driver = {
.driver = {
.name = "rt1015p",
.of_match_table = of_match_ptr(rt1015p_device_id),
.acpi_match_table = ACPI_PTR(rt1015p_acpi_match),
},
.probe = rt1015p_platform_probe,
};
module_platform_driver(rt1015p_platform_driver);
MODULE_DESCRIPTION("ASoC RT1015P driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/rt1015p.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2017, Maxim Integrated
#include <linux/acpi.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/cdev.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <linux/gpio.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <sound/tlv.h>
#include "max98373.h"
static int max98373_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_update_bits(max98373->regmap,
MAX98373_R20FF_GLOBAL_SHDN,
MAX98373_GLOBAL_EN_MASK, 1);
usleep_range(30000, 31000);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_update_bits(max98373->regmap,
MAX98373_R20FF_GLOBAL_SHDN,
MAX98373_GLOBAL_EN_MASK, 0);
usleep_range(30000, 31000);
max98373->tdm_mode = false;
break;
default:
return 0;
}
return 0;
}
static const char * const max98373_switch_text[] = {
"Left", "Right", "LeftRight"};
static const struct soc_enum dai_sel_enum =
SOC_ENUM_SINGLE(MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
MAX98373_PCM_TO_SPK_MONOMIX_CFG_SHIFT,
3, max98373_switch_text);
static const struct snd_kcontrol_new max98373_dai_controls =
SOC_DAPM_ENUM("DAI Sel", dai_sel_enum);
static const struct snd_kcontrol_new max98373_vi_control =
SOC_DAPM_SINGLE("Switch", MAX98373_R202C_PCM_TX_EN, 0, 1, 0);
static const struct snd_kcontrol_new max98373_spkfb_control =
SOC_DAPM_SINGLE("Switch", MAX98373_R2043_AMP_EN, 1, 1, 0);
static const struct snd_soc_dapm_widget max98373_dapm_widgets[] = {
SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback",
MAX98373_R202B_PCM_RX_EN, 0, 0, max98373_dac_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0,
&max98373_dai_controls),
SND_SOC_DAPM_OUTPUT("BE_OUT"),
SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0,
MAX98373_R2047_IV_SENSE_ADC_EN, 0, 0),
SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0,
MAX98373_R2047_IV_SENSE_ADC_EN, 1, 0),
SND_SOC_DAPM_AIF_OUT("Speaker FB Sense", "HiFi Capture", 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0,
&max98373_vi_control),
SND_SOC_DAPM_SWITCH("SpkFB Sense", SND_SOC_NOPM, 0, 0,
&max98373_spkfb_control),
SND_SOC_DAPM_SIGGEN("VMON"),
SND_SOC_DAPM_SIGGEN("IMON"),
SND_SOC_DAPM_SIGGEN("FBMON"),
};
static DECLARE_TLV_DB_SCALE(max98373_digital_tlv, -6350, 50, 1);
static const DECLARE_TLV_DB_RANGE(max98373_spk_tlv,
0, 8, TLV_DB_SCALE_ITEM(0, 50, 0),
9, 10, TLV_DB_SCALE_ITEM(500, 100, 0),
);
static const DECLARE_TLV_DB_RANGE(max98373_spkgain_max_tlv,
0, 9, TLV_DB_SCALE_ITEM(800, 100, 0),
);
static const DECLARE_TLV_DB_RANGE(max98373_dht_step_size_tlv,
0, 1, TLV_DB_SCALE_ITEM(25, 25, 0),
2, 4, TLV_DB_SCALE_ITEM(100, 100, 0),
);
static const DECLARE_TLV_DB_RANGE(max98373_dht_spkgain_min_tlv,
0, 9, TLV_DB_SCALE_ITEM(800, 100, 0),
);
static const DECLARE_TLV_DB_RANGE(max98373_dht_rotation_point_tlv,
0, 1, TLV_DB_SCALE_ITEM(-3000, 500, 0),
2, 4, TLV_DB_SCALE_ITEM(-2200, 200, 0),
5, 6, TLV_DB_SCALE_ITEM(-1500, 300, 0),
7, 9, TLV_DB_SCALE_ITEM(-1000, 200, 0),
10, 13, TLV_DB_SCALE_ITEM(-500, 100, 0),
14, 15, TLV_DB_SCALE_ITEM(-100, 50, 0),
);
static const DECLARE_TLV_DB_RANGE(max98373_limiter_thresh_tlv,
0, 15, TLV_DB_SCALE_ITEM(-1500, 100, 0),
);
static const DECLARE_TLV_DB_RANGE(max98373_bde_gain_tlv,
0, 60, TLV_DB_SCALE_ITEM(-1500, 25, 0),
);
static const char * const max98373_output_voltage_lvl_text[] = {
"5.43V", "6.09V", "6.83V", "7.67V", "8.60V",
"9.65V", "10.83V", "12.15V", "13.63V", "15.29V"
};
static SOC_ENUM_SINGLE_DECL(max98373_out_volt_enum,
MAX98373_R203E_AMP_PATH_GAIN, 0,
max98373_output_voltage_lvl_text);
static const char * const max98373_dht_attack_rate_text[] = {
"17.5us", "35us", "70us", "140us",
"280us", "560us", "1120us", "2240us"
};
static SOC_ENUM_SINGLE_DECL(max98373_dht_attack_rate_enum,
MAX98373_R20D2_DHT_ATTACK_CFG, 0,
max98373_dht_attack_rate_text);
static const char * const max98373_dht_release_rate_text[] = {
"45ms", "225ms", "450ms", "1150ms",
"2250ms", "3100ms", "4500ms", "6750ms"
};
static SOC_ENUM_SINGLE_DECL(max98373_dht_release_rate_enum,
MAX98373_R20D3_DHT_RELEASE_CFG, 0,
max98373_dht_release_rate_text);
static const char * const max98373_limiter_attack_rate_text[] = {
"10us", "20us", "40us", "80us",
"160us", "320us", "640us", "1.28ms",
"2.56ms", "5.12ms", "10.24ms", "20.48ms",
"40.96ms", "81.92ms", "16.384ms", "32.768ms"
};
static SOC_ENUM_SINGLE_DECL(max98373_limiter_attack_rate_enum,
MAX98373_R20E1_LIMITER_ATK_REL_RATES, 4,
max98373_limiter_attack_rate_text);
static const char * const max98373_limiter_release_rate_text[] = {
"40us", "80us", "160us", "320us",
"640us", "1.28ms", "2.56ms", "5.120ms",
"10.24ms", "20.48ms", "40.96ms", "81.92ms",
"163.84ms", "327.68ms", "655.36ms", "1310.72ms"
};
static SOC_ENUM_SINGLE_DECL(max98373_limiter_release_rate_enum,
MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0,
max98373_limiter_release_rate_text);
static const char * const max98373_ADC_samplerate_text[] = {
"333kHz", "192kHz", "64kHz", "48kHz"
};
static SOC_ENUM_SINGLE_DECL(max98373_adc_samplerate_enum,
MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0,
max98373_ADC_samplerate_text);
static int max98373_feedback_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
int i;
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
/*
* Register values will be cached before suspend. The cached value
* will be a valid value and userspace will happy with that.
*/
for (i = 0; i < max98373->cache_num; i++) {
if (mc->reg == max98373->cache[i].reg) {
ucontrol->value.integer.value[0] = max98373->cache[i].val;
return 0;
}
}
}
return snd_soc_get_volsw(kcontrol, ucontrol);
}
static const struct snd_kcontrol_new max98373_snd_controls[] = {
SOC_SINGLE("Digital Vol Sel Switch", MAX98373_R203F_AMP_DSP_CFG,
MAX98373_AMP_VOL_SEL_SHIFT, 1, 0),
SOC_SINGLE("Volume Location Switch", MAX98373_R203F_AMP_DSP_CFG,
MAX98373_AMP_VOL_SEL_SHIFT, 1, 0),
SOC_SINGLE("Ramp Up Switch", MAX98373_R203F_AMP_DSP_CFG,
MAX98373_AMP_DSP_CFG_RMP_UP_SHIFT, 1, 0),
SOC_SINGLE("Ramp Down Switch", MAX98373_R203F_AMP_DSP_CFG,
MAX98373_AMP_DSP_CFG_RMP_DN_SHIFT, 1, 0),
/* Speaker Amplifier Overcurrent Automatic Restart Enable */
SOC_SINGLE("OVC Autorestart Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG,
MAX98373_OVC_AUTORESTART_SHIFT, 1, 0),
/* Thermal Shutdown Automatic Restart Enable */
SOC_SINGLE("THERM Autorestart Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG,
MAX98373_THERM_AUTORESTART_SHIFT, 1, 0),
/* Clock Monitor Automatic Restart Enable */
SOC_SINGLE("CMON Autorestart Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG,
MAX98373_CMON_AUTORESTART_SHIFT, 1, 0),
SOC_SINGLE("CLK Monitor Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG,
MAX98373_CLOCK_MON_SHIFT, 1, 0),
SOC_SINGLE("Dither Switch", MAX98373_R203F_AMP_DSP_CFG,
MAX98373_AMP_DSP_CFG_DITH_SHIFT, 1, 0),
SOC_SINGLE("DC Blocker Switch", MAX98373_R203F_AMP_DSP_CFG,
MAX98373_AMP_DSP_CFG_DCBLK_SHIFT, 1, 0),
SOC_SINGLE_TLV("Digital Volume", MAX98373_R203D_AMP_DIG_VOL_CTRL,
0, 0x7F, 1, max98373_digital_tlv),
SOC_SINGLE_TLV("Speaker Volume", MAX98373_R203E_AMP_PATH_GAIN,
MAX98373_SPK_DIGI_GAIN_SHIFT, 10, 0, max98373_spk_tlv),
SOC_SINGLE_TLV("FS Max Volume", MAX98373_R203E_AMP_PATH_GAIN,
MAX98373_FS_GAIN_MAX_SHIFT, 9, 0, max98373_spkgain_max_tlv),
SOC_ENUM("Output Voltage", max98373_out_volt_enum),
/* Dynamic Headroom Tracking */
SOC_SINGLE("DHT Switch", MAX98373_R20D4_DHT_EN,
MAX98373_DHT_EN_SHIFT, 1, 0),
SOC_SINGLE_TLV("DHT Min Volume", MAX98373_R20D1_DHT_CFG,
MAX98373_DHT_SPK_GAIN_MIN_SHIFT, 9, 0, max98373_dht_spkgain_min_tlv),
SOC_SINGLE_TLV("DHT Rot Pnt Volume", MAX98373_R20D1_DHT_CFG,
MAX98373_DHT_ROT_PNT_SHIFT, 15, 1, max98373_dht_rotation_point_tlv),
SOC_SINGLE_TLV("DHT Attack Step Volume", MAX98373_R20D2_DHT_ATTACK_CFG,
MAX98373_DHT_ATTACK_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv),
SOC_SINGLE_TLV("DHT Release Step Volume", MAX98373_R20D3_DHT_RELEASE_CFG,
MAX98373_DHT_RELEASE_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv),
SOC_ENUM("DHT Attack Rate", max98373_dht_attack_rate_enum),
SOC_ENUM("DHT Release Rate", max98373_dht_release_rate_enum),
/* ADC configuration */
SOC_SINGLE("ADC PVDD CH Switch", MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0, 1, 0),
SOC_SINGLE("ADC PVDD FLT Switch", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG,
MAX98373_FLT_EN_SHIFT, 1, 0),
SOC_SINGLE("ADC TEMP FLT Switch", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG,
MAX98373_FLT_EN_SHIFT, 1, 0),
SOC_SINGLE_EXT("ADC PVDD", MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0, 0xFF, 0,
max98373_feedback_get, NULL),
SOC_SINGLE_EXT("ADC TEMP", MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0, 0xFF, 0,
max98373_feedback_get, NULL),
SOC_SINGLE("ADC PVDD FLT Coeff", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG,
0, 0x3, 0),
SOC_SINGLE("ADC TEMP FLT Coeff", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG,
0, 0x3, 0),
SOC_ENUM("ADC SampleRate", max98373_adc_samplerate_enum),
/* Brownout Detection Engine */
SOC_SINGLE("BDE Switch", MAX98373_R20B5_BDE_EN, MAX98373_BDE_EN_SHIFT, 1, 0),
SOC_SINGLE("BDE LVL4 Mute Switch", MAX98373_R20B2_BDE_L4_CFG_2,
MAX98373_LVL4_MUTE_EN_SHIFT, 1, 0),
SOC_SINGLE("BDE LVL4 Hold Switch", MAX98373_R20B2_BDE_L4_CFG_2,
MAX98373_LVL4_HOLD_EN_SHIFT, 1, 0),
SOC_SINGLE("BDE LVL1 Thresh", MAX98373_R2097_BDE_L1_THRESH, 0, 0xFF, 0),
SOC_SINGLE("BDE LVL2 Thresh", MAX98373_R2098_BDE_L2_THRESH, 0, 0xFF, 0),
SOC_SINGLE("BDE LVL3 Thresh", MAX98373_R2099_BDE_L3_THRESH, 0, 0xFF, 0),
SOC_SINGLE("BDE LVL4 Thresh", MAX98373_R209A_BDE_L4_THRESH, 0, 0xFF, 0),
SOC_SINGLE_EXT("BDE Active Level", MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0, 8, 0,
max98373_feedback_get, NULL),
SOC_SINGLE("BDE Clip Mode Switch", MAX98373_R2092_BDE_CLIPPER_MODE, 0, 1, 0),
SOC_SINGLE("BDE Thresh Hysteresis", MAX98373_R209B_BDE_THRESH_HYST, 0, 0xFF, 0),
SOC_SINGLE("BDE Hold Time", MAX98373_R2090_BDE_LVL_HOLD, 0, 0xFF, 0),
SOC_SINGLE("BDE Attack Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 4, 0xF, 0),
SOC_SINGLE("BDE Release Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0, 0xF, 0),
SOC_SINGLE_TLV("BDE LVL1 Clip Thresh Volume", MAX98373_R20A9_BDE_L1_CFG_2,
0, 0x3C, 1, max98373_bde_gain_tlv),
SOC_SINGLE_TLV("BDE LVL2 Clip Thresh Volume", MAX98373_R20AC_BDE_L2_CFG_2,
0, 0x3C, 1, max98373_bde_gain_tlv),
SOC_SINGLE_TLV("BDE LVL3 Clip Thresh Volume", MAX98373_R20AF_BDE_L3_CFG_2,
0, 0x3C, 1, max98373_bde_gain_tlv),
SOC_SINGLE_TLV("BDE LVL4 Clip Thresh Volume", MAX98373_R20B2_BDE_L4_CFG_2,
0, 0x3C, 1, max98373_bde_gain_tlv),
SOC_SINGLE_TLV("BDE LVL1 Clip Reduction Volume", MAX98373_R20AA_BDE_L1_CFG_3,
0, 0x3C, 1, max98373_bde_gain_tlv),
SOC_SINGLE_TLV("BDE LVL2 Clip Reduction Volume", MAX98373_R20AD_BDE_L2_CFG_3,
0, 0x3C, 1, max98373_bde_gain_tlv),
SOC_SINGLE_TLV("BDE LVL3 Clip Reduction Volume", MAX98373_R20B0_BDE_L3_CFG_3,
0, 0x3C, 1, max98373_bde_gain_tlv),
SOC_SINGLE_TLV("BDE LVL4 Clip Reduction Volume", MAX98373_R20B3_BDE_L4_CFG_3,
0, 0x3C, 1, max98373_bde_gain_tlv),
SOC_SINGLE_TLV("BDE LVL1 Limiter Thresh Volume", MAX98373_R20A8_BDE_L1_CFG_1,
0, 0xF, 1, max98373_limiter_thresh_tlv),
SOC_SINGLE_TLV("BDE LVL2 Limiter Thresh Volume", MAX98373_R20AB_BDE_L2_CFG_1,
0, 0xF, 1, max98373_limiter_thresh_tlv),
SOC_SINGLE_TLV("BDE LVL3 Limiter Thresh Volume", MAX98373_R20AE_BDE_L3_CFG_1,
0, 0xF, 1, max98373_limiter_thresh_tlv),
SOC_SINGLE_TLV("BDE LVL4 Limiter Thresh Volume", MAX98373_R20B1_BDE_L4_CFG_1,
0, 0xF, 1, max98373_limiter_thresh_tlv),
/* Limiter */
SOC_SINGLE("Limiter Switch", MAX98373_R20E2_LIMITER_EN,
MAX98373_LIMITER_EN_SHIFT, 1, 0),
SOC_SINGLE("Limiter Src Switch", MAX98373_R20E0_LIMITER_THRESH_CFG,
MAX98373_LIMITER_THRESH_SRC_SHIFT, 1, 0),
SOC_SINGLE_TLV("Limiter Thresh Volume", MAX98373_R20E0_LIMITER_THRESH_CFG,
MAX98373_LIMITER_THRESH_SHIFT, 15, 0, max98373_limiter_thresh_tlv),
SOC_ENUM("Limiter Attack Rate", max98373_limiter_attack_rate_enum),
SOC_ENUM("Limiter Release Rate", max98373_limiter_release_rate_enum),
};
static const struct snd_soc_dapm_route max98373_audio_map[] = {
/* Plabyack */
{"DAI Sel Mux", "Left", "Amp Enable"},
{"DAI Sel Mux", "Right", "Amp Enable"},
{"DAI Sel Mux", "LeftRight", "Amp Enable"},
{"BE_OUT", NULL, "DAI Sel Mux"},
/* Capture */
{ "VI Sense", "Switch", "VMON" },
{ "VI Sense", "Switch", "IMON" },
{ "SpkFB Sense", "Switch", "FBMON" },
{ "Voltage Sense", NULL, "VI Sense" },
{ "Current Sense", NULL, "VI Sense" },
{ "Speaker FB Sense", NULL, "SpkFB Sense" },
};
void max98373_reset(struct max98373_priv *max98373, struct device *dev)
{
int ret, reg, count;
/* Software Reset */
ret = regmap_update_bits(max98373->regmap,
MAX98373_R2000_SW_RESET,
MAX98373_SOFT_RESET,
MAX98373_SOFT_RESET);
if (ret)
dev_err(dev, "Reset command failed. (ret:%d)\n", ret);
count = 0;
while (count < 3) {
usleep_range(10000, 11000);
/* Software Reset Verification */
ret = regmap_read(max98373->regmap,
MAX98373_R21FF_REV_ID, ®);
if (!ret) {
dev_info(dev, "Reset completed (retry:%d)\n", count);
return;
}
count++;
}
dev_err(dev, "Reset failed. (ret:%d)\n", ret);
}
EXPORT_SYMBOL_GPL(max98373_reset);
static int max98373_probe(struct snd_soc_component *component)
{
struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
/* Software Reset */
max98373_reset(max98373, component->dev);
/* IV default slot configuration */
regmap_write(max98373->regmap,
MAX98373_R2020_PCM_TX_HIZ_EN_1,
0xFF);
regmap_write(max98373->regmap,
MAX98373_R2021_PCM_TX_HIZ_EN_2,
0xFF);
/* L/R mix configuration */
regmap_write(max98373->regmap,
MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
0x80);
regmap_write(max98373->regmap,
MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2,
0x1);
/* Enable DC blocker */
regmap_write(max98373->regmap,
MAX98373_R203F_AMP_DSP_CFG,
0x3);
/* Enable IMON VMON DC blocker */
regmap_write(max98373->regmap,
MAX98373_R2046_IV_SENSE_ADC_DSP_CFG,
0x7);
/* voltage, current slot configuration */
regmap_write(max98373->regmap,
MAX98373_R2022_PCM_TX_SRC_1,
(max98373->i_slot << MAX98373_PCM_TX_CH_SRC_A_I_SHIFT |
max98373->v_slot) & 0xFF);
if (max98373->v_slot < 8)
regmap_update_bits(max98373->regmap,
MAX98373_R2020_PCM_TX_HIZ_EN_1,
1 << max98373->v_slot, 0);
else
regmap_update_bits(max98373->regmap,
MAX98373_R2021_PCM_TX_HIZ_EN_2,
1 << (max98373->v_slot - 8), 0);
if (max98373->i_slot < 8)
regmap_update_bits(max98373->regmap,
MAX98373_R2020_PCM_TX_HIZ_EN_1,
1 << max98373->i_slot, 0);
else
regmap_update_bits(max98373->regmap,
MAX98373_R2021_PCM_TX_HIZ_EN_2,
1 << (max98373->i_slot - 8), 0);
/* enable auto restart function by default */
regmap_write(max98373->regmap,
MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG,
0xF);
/* speaker feedback slot configuration */
regmap_write(max98373->regmap,
MAX98373_R2023_PCM_TX_SRC_2,
max98373->spkfb_slot & 0xFF);
/* Set interleave mode */
if (max98373->interleave_mode)
regmap_update_bits(max98373->regmap,
MAX98373_R2024_PCM_DATA_FMT_CFG,
MAX98373_PCM_TX_CH_INTERLEAVE_MASK,
MAX98373_PCM_TX_CH_INTERLEAVE_MASK);
/* Speaker enable */
regmap_update_bits(max98373->regmap,
MAX98373_R2043_AMP_EN,
MAX98373_SPK_EN_MASK, 1);
return 0;
}
const struct snd_soc_component_driver soc_codec_dev_max98373 = {
.probe = max98373_probe,
.controls = max98373_snd_controls,
.num_controls = ARRAY_SIZE(max98373_snd_controls),
.dapm_widgets = max98373_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(max98373_dapm_widgets),
.dapm_routes = max98373_audio_map,
.num_dapm_routes = ARRAY_SIZE(max98373_audio_map),
.use_pmdown_time = 1,
.endianness = 1,
};
EXPORT_SYMBOL_GPL(soc_codec_dev_max98373);
static int max98373_sdw_probe(struct snd_soc_component *component)
{
int ret;
ret = pm_runtime_resume(component->dev);
if (ret < 0 && ret != -EACCES)
return ret;
return 0;
}
const struct snd_soc_component_driver soc_codec_dev_max98373_sdw = {
.probe = max98373_sdw_probe,
.controls = max98373_snd_controls,
.num_controls = ARRAY_SIZE(max98373_snd_controls),
.dapm_widgets = max98373_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(max98373_dapm_widgets),
.dapm_routes = max98373_audio_map,
.num_dapm_routes = ARRAY_SIZE(max98373_audio_map),
.use_pmdown_time = 1,
.endianness = 1,
};
EXPORT_SYMBOL_GPL(soc_codec_dev_max98373_sdw);
void max98373_slot_config(struct device *dev,
struct max98373_priv *max98373)
{
int value;
if (!device_property_read_u32(dev, "maxim,vmon-slot-no", &value))
max98373->v_slot = value & 0xF;
else
max98373->v_slot = 0;
if (!device_property_read_u32(dev, "maxim,imon-slot-no", &value))
max98373->i_slot = value & 0xF;
else
max98373->i_slot = 1;
if (dev->of_node) {
max98373->reset_gpio = of_get_named_gpio(dev->of_node,
"maxim,reset-gpio", 0);
if (!gpio_is_valid(max98373->reset_gpio)) {
dev_err(dev, "Looking up %s property in node %s failed %d\n",
"maxim,reset-gpio", dev->of_node->full_name,
max98373->reset_gpio);
} else {
dev_dbg(dev, "maxim,reset-gpio=%d",
max98373->reset_gpio);
}
} else {
/* this makes reset_gpio as invalid */
max98373->reset_gpio = -1;
}
if (!device_property_read_u32(dev, "maxim,spkfb-slot-no", &value))
max98373->spkfb_slot = value & 0xF;
else
max98373->spkfb_slot = 2;
}
EXPORT_SYMBOL_GPL(max98373_slot_config);
MODULE_DESCRIPTION("ALSA SoC MAX98373 driver");
MODULE_AUTHOR("Ryan Lee <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/max98373.c |
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright 2011-2019 NW Digital Radio
*
* Author: Annaliese McDermond <[email protected]>
*
* Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27.
*
*/
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include "tlv320aic32x4.h"
static const struct of_device_id aic32x4_of_id[];
static const struct i2c_device_id aic32x4_i2c_id[];
static int aic32x4_i2c_probe(struct i2c_client *i2c)
{
struct regmap *regmap;
struct regmap_config config;
config = aic32x4_regmap_config;
config.reg_bits = 8;
config.val_bits = 8;
regmap = devm_regmap_init_i2c(i2c, &config);
if (i2c->dev.of_node) {
const struct of_device_id *oid;
oid = of_match_node(aic32x4_of_id, i2c->dev.of_node);
dev_set_drvdata(&i2c->dev, (void *)oid->data);
} else {
const struct i2c_device_id *id;
id = i2c_match_id(aic32x4_i2c_id, i2c);
dev_set_drvdata(&i2c->dev, (void *)id->driver_data);
}
return aic32x4_probe(&i2c->dev, regmap);
}
static void aic32x4_i2c_remove(struct i2c_client *i2c)
{
aic32x4_remove(&i2c->dev);
}
static const struct i2c_device_id aic32x4_i2c_id[] = {
{ "tlv320aic32x4", (kernel_ulong_t)AIC32X4_TYPE_AIC32X4 },
{ "tlv320aic32x6", (kernel_ulong_t)AIC32X4_TYPE_AIC32X6 },
{ "tas2505", (kernel_ulong_t)AIC32X4_TYPE_TAS2505 },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(i2c, aic32x4_i2c_id);
static const struct of_device_id aic32x4_of_id[] = {
{ .compatible = "ti,tlv320aic32x4", .data = (void *)AIC32X4_TYPE_AIC32X4 },
{ .compatible = "ti,tlv320aic32x6", .data = (void *)AIC32X4_TYPE_AIC32X6 },
{ .compatible = "ti,tas2505", .data = (void *)AIC32X4_TYPE_TAS2505 },
{ /* senitel */ }
};
MODULE_DEVICE_TABLE(of, aic32x4_of_id);
static struct i2c_driver aic32x4_i2c_driver = {
.driver = {
.name = "tlv320aic32x4",
.of_match_table = aic32x4_of_id,
},
.probe = aic32x4_i2c_probe,
.remove = aic32x4_i2c_remove,
.id_table = aic32x4_i2c_id,
};
module_i2c_driver(aic32x4_i2c_driver);
MODULE_DESCRIPTION("ASoC TLV320AIC32x4 codec driver I2C");
MODULE_AUTHOR("Annaliese McDermond <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/tlv320aic32x4-i2c.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* rt1305.c -- RT1305 ALSA SoC amplifier component driver
*
* Copyright 2018 Realtek Semiconductor Corp.
* Author: Shuming Fan <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/acpi.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/platform_device.h>
#include <linux/firmware.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "rl6231.h"
#include "rt1305.h"
#define RT1305_PR_RANGE_BASE (0xff + 1)
#define RT1305_PR_SPACING 0x100
#define RT1305_PR_BASE (RT1305_PR_RANGE_BASE + (0 * RT1305_PR_SPACING))
static const struct regmap_range_cfg rt1305_ranges[] = {
{
.name = "PR",
.range_min = RT1305_PR_BASE,
.range_max = RT1305_PR_BASE + 0xff,
.selector_reg = RT1305_PRIV_INDEX,
.selector_mask = 0xff,
.selector_shift = 0x0,
.window_start = RT1305_PRIV_DATA,
.window_len = 0x1,
},
};
static const struct reg_sequence init_list[] = {
{ RT1305_PR_BASE + 0xcf, 0x5548 },
{ RT1305_PR_BASE + 0x5d, 0x0442 },
{ RT1305_PR_BASE + 0xc1, 0x0320 },
{ RT1305_POWER_STATUS, 0x0000 },
{ RT1305_SPK_TEMP_PROTECTION_1, 0xd6de },
{ RT1305_SPK_TEMP_PROTECTION_2, 0x0707 },
{ RT1305_SPK_TEMP_PROTECTION_3, 0x4090 },
{ RT1305_DAC_SET_1, 0xdfdf }, /* 4 ohm 2W */
{ RT1305_ADC_SET_3, 0x0219 },
{ RT1305_ADC_SET_1, 0x170f }, /* 0.2 ohm RSense*/
};
#define RT1305_INIT_REG_LEN ARRAY_SIZE(init_list)
struct rt1305_priv {
struct snd_soc_component *component;
struct regmap *regmap;
int sysclk;
int sysclk_src;
int lrck;
int bclk;
int master;
int pll_src;
int pll_in;
int pll_out;
};
static const struct reg_default rt1305_reg[] = {
{ 0x04, 0x0400 },
{ 0x05, 0x0880 },
{ 0x06, 0x0000 },
{ 0x07, 0x3100 },
{ 0x08, 0x8000 },
{ 0x09, 0x0000 },
{ 0x0a, 0x087e },
{ 0x0b, 0x0020 },
{ 0x0c, 0x0802 },
{ 0x0d, 0x0020 },
{ 0x10, 0x1d1d },
{ 0x11, 0x1d1d },
{ 0x12, 0xffff },
{ 0x14, 0x000c },
{ 0x16, 0x1717 },
{ 0x17, 0x4000 },
{ 0x18, 0x0019 },
{ 0x20, 0x0000 },
{ 0x22, 0x0000 },
{ 0x24, 0x0000 },
{ 0x26, 0x0000 },
{ 0x28, 0x0000 },
{ 0x2a, 0x4000 },
{ 0x2b, 0x3000 },
{ 0x2d, 0x6000 },
{ 0x2e, 0x0000 },
{ 0x2f, 0x8000 },
{ 0x32, 0x0000 },
{ 0x39, 0x0001 },
{ 0x3a, 0x0000 },
{ 0x3b, 0x1020 },
{ 0x3c, 0x0000 },
{ 0x3d, 0x0000 },
{ 0x3e, 0x4c00 },
{ 0x3f, 0x3000 },
{ 0x40, 0x000c },
{ 0x42, 0x0400 },
{ 0x46, 0xc22c },
{ 0x47, 0x0000 },
{ 0x4b, 0x0000 },
{ 0x4c, 0x0300 },
{ 0x4f, 0xf000 },
{ 0x50, 0xc200 },
{ 0x51, 0x1f1f },
{ 0x52, 0x01f0 },
{ 0x53, 0x407f },
{ 0x54, 0xffff },
{ 0x58, 0x4005 },
{ 0x5e, 0x0000 },
{ 0x5f, 0x0000 },
{ 0x60, 0xee13 },
{ 0x62, 0x0000 },
{ 0x63, 0x5f5f },
{ 0x64, 0x0040 },
{ 0x65, 0x4000 },
{ 0x66, 0x4004 },
{ 0x67, 0x0306 },
{ 0x68, 0x8c04 },
{ 0x69, 0xe021 },
{ 0x6a, 0x0000 },
{ 0x6c, 0xaaaa },
{ 0x70, 0x0333 },
{ 0x71, 0x3330 },
{ 0x72, 0x3333 },
{ 0x73, 0x3300 },
{ 0x74, 0x0000 },
{ 0x75, 0x0000 },
{ 0x76, 0x0000 },
{ 0x7a, 0x0003 },
{ 0x7c, 0x10ec },
{ 0x7e, 0x6251 },
{ 0x80, 0x0800 },
{ 0x81, 0x4000 },
{ 0x82, 0x0000 },
{ 0x90, 0x7a01 },
{ 0x91, 0x8431 },
{ 0x92, 0x0180 },
{ 0x93, 0x0000 },
{ 0x94, 0x0000 },
{ 0x95, 0x0000 },
{ 0x96, 0x0000 },
{ 0x97, 0x0000 },
{ 0x98, 0x0000 },
{ 0x99, 0x0000 },
{ 0x9a, 0x0000 },
{ 0x9b, 0x0000 },
{ 0x9c, 0x0000 },
{ 0x9d, 0x0000 },
{ 0x9e, 0x0000 },
{ 0x9f, 0x0000 },
{ 0xa0, 0x0000 },
{ 0xb0, 0x8200 },
{ 0xb1, 0x00ff },
{ 0xb2, 0x0008 },
{ 0xc0, 0x0200 },
{ 0xc1, 0x0000 },
{ 0xc2, 0x0000 },
{ 0xc3, 0x0000 },
{ 0xc4, 0x0000 },
{ 0xc5, 0x0000 },
{ 0xc6, 0x0000 },
{ 0xc7, 0x0000 },
{ 0xc8, 0x0000 },
{ 0xc9, 0x0000 },
{ 0xca, 0x0200 },
{ 0xcb, 0x0000 },
{ 0xcc, 0x0000 },
{ 0xcd, 0x0000 },
{ 0xce, 0x0000 },
{ 0xcf, 0x0000 },
{ 0xd0, 0x0000 },
{ 0xd1, 0x0000 },
{ 0xd2, 0x0000 },
{ 0xd3, 0x0000 },
{ 0xd4, 0x0200 },
{ 0xd5, 0x0000 },
{ 0xd6, 0x0000 },
{ 0xd7, 0x0000 },
{ 0xd8, 0x0000 },
{ 0xd9, 0x0000 },
{ 0xda, 0x0000 },
{ 0xdb, 0x0000 },
{ 0xdc, 0x0000 },
{ 0xdd, 0x0000 },
{ 0xde, 0x0200 },
{ 0xdf, 0x0000 },
{ 0xe0, 0x0000 },
{ 0xe1, 0x0000 },
{ 0xe2, 0x0000 },
{ 0xe3, 0x0000 },
{ 0xe4, 0x0000 },
{ 0xe5, 0x0000 },
{ 0xe6, 0x0000 },
{ 0xe7, 0x0000 },
{ 0xe8, 0x0200 },
{ 0xe9, 0x0000 },
{ 0xea, 0x0000 },
{ 0xeb, 0x0000 },
{ 0xec, 0x0000 },
{ 0xed, 0x0000 },
{ 0xee, 0x0000 },
{ 0xef, 0x0000 },
{ 0xf0, 0x0000 },
{ 0xf1, 0x0000 },
{ 0xf2, 0x0200 },
{ 0xf3, 0x0000 },
{ 0xf4, 0x0000 },
{ 0xf5, 0x0000 },
{ 0xf6, 0x0000 },
{ 0xf7, 0x0000 },
{ 0xf8, 0x0000 },
{ 0xf9, 0x0000 },
{ 0xfa, 0x0000 },
{ 0xfb, 0x0000 },
};
static int rt1305_reg_init(struct snd_soc_component *component)
{
struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
regmap_multi_reg_write(rt1305->regmap, init_list, RT1305_INIT_REG_LEN);
return 0;
}
static bool rt1305_volatile_register(struct device *dev, unsigned int reg)
{
int i;
for (i = 0; i < ARRAY_SIZE(rt1305_ranges); i++) {
if (reg >= rt1305_ranges[i].range_min &&
reg <= rt1305_ranges[i].range_max) {
return true;
}
}
switch (reg) {
case RT1305_RESET:
case RT1305_SPDIF_IN_SET_1:
case RT1305_SPDIF_IN_SET_2:
case RT1305_SPDIF_IN_SET_3:
case RT1305_POWER_CTRL_2:
case RT1305_CLOCK_DETECT:
case RT1305_BIQUAD_SET_1:
case RT1305_BIQUAD_SET_2:
case RT1305_EQ_SET_2:
case RT1305_SPK_TEMP_PROTECTION_0:
case RT1305_SPK_TEMP_PROTECTION_2:
case RT1305_SPK_DC_DETECT_1:
case RT1305_SILENCE_DETECT:
case RT1305_VERSION_ID:
case RT1305_VENDOR_ID:
case RT1305_DEVICE_ID:
case RT1305_EFUSE_1:
case RT1305_EFUSE_3:
case RT1305_DC_CALIB_1:
case RT1305_DC_CALIB_3:
case RT1305_DAC_OFFSET_1:
case RT1305_DAC_OFFSET_2:
case RT1305_DAC_OFFSET_3:
case RT1305_DAC_OFFSET_4:
case RT1305_DAC_OFFSET_5:
case RT1305_DAC_OFFSET_6:
case RT1305_DAC_OFFSET_7:
case RT1305_DAC_OFFSET_8:
case RT1305_DAC_OFFSET_9:
case RT1305_DAC_OFFSET_10:
case RT1305_DAC_OFFSET_11:
case RT1305_TRIM_1:
case RT1305_TRIM_2:
return true;
default:
return false;
}
}
static bool rt1305_readable_register(struct device *dev, unsigned int reg)
{
int i;
for (i = 0; i < ARRAY_SIZE(rt1305_ranges); i++) {
if (reg >= rt1305_ranges[i].range_min &&
reg <= rt1305_ranges[i].range_max) {
return true;
}
}
switch (reg) {
case RT1305_RESET:
case RT1305_CLK_1 ... RT1305_CAL_EFUSE_CLOCK:
case RT1305_PLL0_1 ... RT1305_PLL1_2:
case RT1305_MIXER_CTRL_1:
case RT1305_MIXER_CTRL_2:
case RT1305_DAC_SET_1:
case RT1305_DAC_SET_2:
case RT1305_ADC_SET_1:
case RT1305_ADC_SET_2:
case RT1305_ADC_SET_3:
case RT1305_PATH_SET:
case RT1305_SPDIF_IN_SET_1:
case RT1305_SPDIF_IN_SET_2:
case RT1305_SPDIF_IN_SET_3:
case RT1305_SPDIF_OUT_SET_1:
case RT1305_SPDIF_OUT_SET_2:
case RT1305_SPDIF_OUT_SET_3:
case RT1305_I2S_SET_1:
case RT1305_I2S_SET_2:
case RT1305_PBTL_MONO_MODE_SRC:
case RT1305_MANUALLY_I2C_DEVICE:
case RT1305_POWER_STATUS:
case RT1305_POWER_CTRL_1:
case RT1305_POWER_CTRL_2:
case RT1305_POWER_CTRL_3:
case RT1305_POWER_CTRL_4:
case RT1305_POWER_CTRL_5:
case RT1305_CLOCK_DETECT:
case RT1305_BIQUAD_SET_1:
case RT1305_BIQUAD_SET_2:
case RT1305_ADJUSTED_HPF_1:
case RT1305_ADJUSTED_HPF_2:
case RT1305_EQ_SET_1:
case RT1305_EQ_SET_2:
case RT1305_SPK_TEMP_PROTECTION_0:
case RT1305_SPK_TEMP_PROTECTION_1:
case RT1305_SPK_TEMP_PROTECTION_2:
case RT1305_SPK_TEMP_PROTECTION_3:
case RT1305_SPK_DC_DETECT_1:
case RT1305_SPK_DC_DETECT_2:
case RT1305_LOUDNESS:
case RT1305_THERMAL_FOLD_BACK_1:
case RT1305_THERMAL_FOLD_BACK_2:
case RT1305_SILENCE_DETECT ... RT1305_SPK_EXCURSION_LIMITER_7:
case RT1305_VERSION_ID:
case RT1305_VENDOR_ID:
case RT1305_DEVICE_ID:
case RT1305_EFUSE_1:
case RT1305_EFUSE_2:
case RT1305_EFUSE_3:
case RT1305_DC_CALIB_1:
case RT1305_DC_CALIB_2:
case RT1305_DC_CALIB_3:
case RT1305_DAC_OFFSET_1 ... RT1305_DAC_OFFSET_14:
case RT1305_TRIM_1:
case RT1305_TRIM_2:
case RT1305_TUNE_INTERNAL_OSC:
case RT1305_BIQUAD1_H0_L_28_16 ... RT1305_BIQUAD3_A2_R_15_0:
return true;
default:
return false;
}
}
static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9435, 37, 0);
static const char * const rt1305_rx_data_ch_select[] = {
"LR",
"RL",
"Copy L",
"Copy R",
};
static SOC_ENUM_SINGLE_DECL(rt1305_rx_data_ch_enum, RT1305_I2S_SET_2, 2,
rt1305_rx_data_ch_select);
static void rt1305_reset(struct regmap *regmap)
{
regmap_write(regmap, RT1305_RESET, 0);
}
static const struct snd_kcontrol_new rt1305_snd_controls[] = {
SOC_DOUBLE_TLV("DAC Playback Volume", RT1305_DAC_SET_1,
8, 0, 0xff, 0, dac_vol_tlv),
/* I2S Data Channel Selection */
SOC_ENUM("RX Channel Select", rt1305_rx_data_ch_enum),
};
static int rt1305_is_rc_clk_from_pll(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(source->dapm);
struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
unsigned int val;
val = snd_soc_component_read(component, RT1305_CLK_1);
if (rt1305->sysclk_src == RT1305_FS_SYS_PRE_S_PLL1 &&
(val & RT1305_SEL_PLL_SRC_2_RCCLK))
return 1;
else
return 0;
}
static int rt1305_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(source->dapm);
struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
if (rt1305->sysclk_src == RT1305_FS_SYS_PRE_S_PLL1)
return 1;
else
return 0;
}
static int rt1305_classd_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(component, RT1305_POWER_CTRL_1,
RT1305_POW_PDB_JD_MASK, RT1305_POW_PDB_JD);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, RT1305_POWER_CTRL_1,
RT1305_POW_PDB_JD_MASK, 0);
usleep_range(150000, 200000);
break;
default:
return 0;
}
return 0;
}
static const struct snd_kcontrol_new rt1305_sto_dac_l =
SOC_DAPM_SINGLE("Switch", RT1305_DAC_SET_2,
RT1305_DVOL_MUTE_L_EN_SFT, 1, 1);
static const struct snd_kcontrol_new rt1305_sto_dac_r =
SOC_DAPM_SINGLE("Switch", RT1305_DAC_SET_2,
RT1305_DVOL_MUTE_R_EN_SFT, 1, 1);
static const struct snd_soc_dapm_widget rt1305_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("PLL0", RT1305_POWER_CTRL_1,
RT1305_POW_PLL0_EN_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PLL1", RT1305_POWER_CTRL_1,
RT1305_POW_PLL1_EN_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MBIAS", RT1305_POWER_CTRL_1,
RT1305_POW_MBIAS_LV_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("BG MBIAS", RT1305_POWER_CTRL_1,
RT1305_POW_BG_MBIAS_LV_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("LDO2", RT1305_POWER_CTRL_1,
RT1305_POW_LDO2_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("BG2", RT1305_POWER_CTRL_1,
RT1305_POW_BG2_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("LDO2 IB2", RT1305_POWER_CTRL_1,
RT1305_POW_LDO2_IB2_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("VREF", RT1305_POWER_CTRL_1,
RT1305_POW_VREF_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("VREF1", RT1305_POWER_CTRL_1,
RT1305_POW_VREF1_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("VREF2", RT1305_POWER_CTRL_1,
RT1305_POW_VREF2_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DISC VREF", RT1305_POWER_CTRL_2,
RT1305_POW_DISC_VREF_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("FASTB VREF", RT1305_POWER_CTRL_2,
RT1305_POW_FASTB_VREF_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ULTRA FAST VREF", RT1305_POWER_CTRL_2,
RT1305_POW_ULTRA_FAST_VREF_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CHOP DAC", RT1305_POWER_CTRL_2,
RT1305_POW_CKXEN_DAC_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CKGEN DAC", RT1305_POWER_CTRL_2,
RT1305_POW_EN_CKGEN_DAC_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CLAMP", RT1305_POWER_CTRL_2,
RT1305_POW_CLAMP_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("BUFL", RT1305_POWER_CTRL_2,
RT1305_POW_BUFL_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("BUFR", RT1305_POWER_CTRL_2,
RT1305_POW_BUFR_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CKGEN ADC", RT1305_POWER_CTRL_2,
RT1305_POW_EN_CKGEN_ADC_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC3 L", RT1305_POWER_CTRL_2,
RT1305_POW_ADC3_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC3 R", RT1305_POWER_CTRL_2,
RT1305_POW_ADC3_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("TRIOSC", RT1305_POWER_CTRL_2,
RT1305_POW_TRIOSC_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("AVDD1", RT1305_POWER_CTRL_2,
RT1305_POR_AVDD1_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("AVDD2", RT1305_POWER_CTRL_2,
RT1305_POR_AVDD2_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("VSENSE R", RT1305_POWER_CTRL_3,
RT1305_POW_VSENSE_RCH_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("VSENSE L", RT1305_POWER_CTRL_3,
RT1305_POW_VSENSE_LCH_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ISENSE R", RT1305_POWER_CTRL_3,
RT1305_POW_ISENSE_RCH_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ISENSE L", RT1305_POWER_CTRL_3,
RT1305_POW_ISENSE_LCH_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("POR AVDD1", RT1305_POWER_CTRL_3,
RT1305_POW_POR_AVDD1_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("POR AVDD2", RT1305_POWER_CTRL_3,
RT1305_POW_POR_AVDD2_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("VCM 6172", RT1305_POWER_CTRL_3,
RT1305_EN_VCM_6172_BIT, 0, NULL, 0),
/* Audio Interface */
SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
/* Digital Interface */
SND_SOC_DAPM_SUPPLY("DAC L Power", RT1305_POWER_CTRL_2,
RT1305_POW_DAC1_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC R Power", RT1305_POWER_CTRL_2,
RT1305_POW_DAC1_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SWITCH("DAC L", SND_SOC_NOPM, 0, 0, &rt1305_sto_dac_l),
SND_SOC_DAPM_SWITCH("DAC R", SND_SOC_NOPM, 0, 0, &rt1305_sto_dac_r),
/* Output Lines */
SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
rt1305_classd_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_OUTPUT("SPOL"),
SND_SOC_DAPM_OUTPUT("SPOR"),
};
static const struct snd_soc_dapm_route rt1305_dapm_routes[] = {
{ "DAC", NULL, "AIF1RX" },
{ "DAC", NULL, "PLL0", rt1305_is_rc_clk_from_pll },
{ "DAC", NULL, "PLL1", rt1305_is_sys_clk_from_pll },
{ "DAC", NULL, "MBIAS" },
{ "DAC", NULL, "BG MBIAS" },
{ "DAC", NULL, "LDO2" },
{ "DAC", NULL, "BG2" },
{ "DAC", NULL, "LDO2 IB2" },
{ "DAC", NULL, "VREF" },
{ "DAC", NULL, "VREF1" },
{ "DAC", NULL, "VREF2" },
{ "DAC", NULL, "DISC VREF" },
{ "DAC", NULL, "FASTB VREF" },
{ "DAC", NULL, "ULTRA FAST VREF" },
{ "DAC", NULL, "CHOP DAC" },
{ "DAC", NULL, "CKGEN DAC" },
{ "DAC", NULL, "CLAMP" },
{ "DAC", NULL, "CKGEN ADC" },
{ "DAC", NULL, "TRIOSC" },
{ "DAC", NULL, "AVDD1" },
{ "DAC", NULL, "AVDD2" },
{ "DAC", NULL, "POR AVDD1" },
{ "DAC", NULL, "POR AVDD2" },
{ "DAC", NULL, "VCM 6172" },
{ "DAC L", "Switch", "DAC" },
{ "DAC R", "Switch", "DAC" },
{ "DAC R", NULL, "VSENSE R" },
{ "DAC L", NULL, "VSENSE L" },
{ "DAC R", NULL, "ISENSE R" },
{ "DAC L", NULL, "ISENSE L" },
{ "DAC L", NULL, "ADC3 L" },
{ "DAC R", NULL, "ADC3 R" },
{ "DAC L", NULL, "BUFL" },
{ "DAC R", NULL, "BUFR" },
{ "DAC L", NULL, "DAC L Power" },
{ "DAC R", NULL, "DAC R Power" },
{ "CLASS D", NULL, "DAC L" },
{ "CLASS D", NULL, "DAC R" },
{ "SPOL", NULL, "CLASS D" },
{ "SPOR", NULL, "CLASS D" },
};
static int rt1305_get_clk_info(int sclk, int rate)
{
int i;
static const int pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
if (sclk <= 0 || rate <= 0)
return -EINVAL;
rate = rate << 8;
for (i = 0; i < ARRAY_SIZE(pd); i++)
if (sclk == rate * pd[i])
return i;
return -EINVAL;
}
static int rt1305_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
unsigned int val_len = 0, val_clk, mask_clk;
int pre_div, bclk_ms, frame_size;
rt1305->lrck = params_rate(params);
pre_div = rt1305_get_clk_info(rt1305->sysclk, rt1305->lrck);
if (pre_div < 0) {
dev_warn(component->dev, "Force using PLL ");
snd_soc_dai_set_pll(dai, 0, RT1305_PLL1_S_BCLK,
rt1305->lrck * 64, rt1305->lrck * 256);
snd_soc_dai_set_sysclk(dai, RT1305_FS_SYS_PRE_S_PLL1,
rt1305->lrck * 256, SND_SOC_CLOCK_IN);
pre_div = 0;
}
frame_size = snd_soc_params_to_frame_size(params);
if (frame_size < 0) {
dev_err(component->dev, "Unsupported frame size: %d\n",
frame_size);
return -EINVAL;
}
bclk_ms = frame_size > 32;
rt1305->bclk = rt1305->lrck * (32 << bclk_ms);
dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
bclk_ms, pre_div, dai->id);
dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
rt1305->lrck, pre_div, dai->id);
switch (params_width(params)) {
case 16:
val_len |= RT1305_I2S_DL_SEL_16B;
break;
case 20:
val_len |= RT1305_I2S_DL_SEL_20B;
break;
case 24:
val_len |= RT1305_I2S_DL_SEL_24B;
break;
case 8:
val_len |= RT1305_I2S_DL_SEL_8B;
break;
default:
return -EINVAL;
}
switch (dai->id) {
case RT1305_AIF1:
mask_clk = RT1305_DIV_FS_SYS_MASK;
val_clk = pre_div << RT1305_DIV_FS_SYS_SFT;
snd_soc_component_update_bits(component, RT1305_I2S_SET_2,
RT1305_I2S_DL_SEL_MASK,
val_len);
break;
default:
dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
return -EINVAL;
}
snd_soc_component_update_bits(component, RT1305_CLK_2,
mask_clk, val_clk);
return 0;
}
static int rt1305_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0, reg1_val = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
reg_val |= RT1305_SEL_I2S_OUT_MODE_M;
rt1305->master = 1;
break;
case SND_SOC_DAIFMT_CBS_CFS:
reg_val |= RT1305_SEL_I2S_OUT_MODE_S;
rt1305->master = 0;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
reg1_val |= RT1305_I2S_BCLK_INV;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_LEFT_J:
reg1_val |= RT1305_I2S_DF_SEL_LEFT;
break;
case SND_SOC_DAIFMT_DSP_A:
reg1_val |= RT1305_I2S_DF_SEL_PCM_A;
break;
case SND_SOC_DAIFMT_DSP_B:
reg1_val |= RT1305_I2S_DF_SEL_PCM_B;
break;
default:
return -EINVAL;
}
switch (dai->id) {
case RT1305_AIF1:
snd_soc_component_update_bits(component, RT1305_I2S_SET_1,
RT1305_SEL_I2S_OUT_MODE_MASK, reg_val);
snd_soc_component_update_bits(component, RT1305_I2S_SET_2,
RT1305_I2S_DF_SEL_MASK | RT1305_I2S_BCLK_MASK,
reg1_val);
break;
default:
dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
return -EINVAL;
}
return 0;
}
static int rt1305_set_component_sysclk(struct snd_soc_component *component,
int clk_id, int source, unsigned int freq, int dir)
{
struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0;
if (freq == rt1305->sysclk && clk_id == rt1305->sysclk_src)
return 0;
switch (clk_id) {
case RT1305_FS_SYS_PRE_S_MCLK:
reg_val |= RT1305_SEL_FS_SYS_PRE_MCLK;
snd_soc_component_update_bits(component,
RT1305_CLOCK_DETECT, RT1305_SEL_CLK_DET_SRC_MASK,
RT1305_SEL_CLK_DET_SRC_MCLK);
break;
case RT1305_FS_SYS_PRE_S_PLL1:
reg_val |= RT1305_SEL_FS_SYS_PRE_PLL;
break;
case RT1305_FS_SYS_PRE_S_RCCLK:
reg_val |= RT1305_SEL_FS_SYS_PRE_RCCLK;
break;
default:
dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
return -EINVAL;
}
snd_soc_component_update_bits(component, RT1305_CLK_1,
RT1305_SEL_FS_SYS_PRE_MASK, reg_val);
rt1305->sysclk = freq;
rt1305->sysclk_src = clk_id;
dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
freq, clk_id);
return 0;
}
static int rt1305_set_component_pll(struct snd_soc_component *component,
int pll_id, int source, unsigned int freq_in,
unsigned int freq_out)
{
struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
struct rl6231_pll_code pll_code;
int ret;
if (source == rt1305->pll_src && freq_in == rt1305->pll_in &&
freq_out == rt1305->pll_out)
return 0;
if (!freq_in || !freq_out) {
dev_dbg(component->dev, "PLL disabled\n");
rt1305->pll_in = 0;
rt1305->pll_out = 0;
snd_soc_component_update_bits(component, RT1305_CLK_1,
RT1305_SEL_FS_SYS_PRE_MASK | RT1305_SEL_PLL_SRC_1_MASK,
RT1305_SEL_FS_SYS_PRE_PLL | RT1305_SEL_PLL_SRC_1_BCLK);
return 0;
}
switch (source) {
case RT1305_PLL2_S_MCLK:
snd_soc_component_update_bits(component, RT1305_CLK_1,
RT1305_SEL_PLL_SRC_2_MASK | RT1305_SEL_PLL_SRC_1_MASK |
RT1305_DIV_PLL_SRC_2_MASK,
RT1305_SEL_PLL_SRC_2_MCLK | RT1305_SEL_PLL_SRC_1_PLL2);
snd_soc_component_update_bits(component,
RT1305_CLOCK_DETECT, RT1305_SEL_CLK_DET_SRC_MASK,
RT1305_SEL_CLK_DET_SRC_MCLK);
break;
case RT1305_PLL1_S_BCLK:
snd_soc_component_update_bits(component,
RT1305_CLK_1, RT1305_SEL_PLL_SRC_1_MASK,
RT1305_SEL_PLL_SRC_1_BCLK);
break;
case RT1305_PLL2_S_RCCLK:
snd_soc_component_update_bits(component, RT1305_CLK_1,
RT1305_SEL_PLL_SRC_2_MASK | RT1305_SEL_PLL_SRC_1_MASK |
RT1305_DIV_PLL_SRC_2_MASK,
RT1305_SEL_PLL_SRC_2_RCCLK | RT1305_SEL_PLL_SRC_1_PLL2);
freq_in = 98304000;
break;
default:
dev_err(component->dev, "Unknown PLL Source %d\n", source);
return -EINVAL;
}
ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
if (ret < 0) {
dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
return ret;
}
dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
pll_code.n_code, pll_code.k_code);
snd_soc_component_write(component, RT1305_PLL1_1,
((pll_code.m_bp ? 0 : pll_code.m_code) << RT1305_PLL_1_M_SFT) |
(pll_code.m_bp << RT1305_PLL_1_M_BYPASS_SFT) |
pll_code.n_code);
snd_soc_component_write(component, RT1305_PLL1_2,
pll_code.k_code);
rt1305->pll_in = freq_in;
rt1305->pll_out = freq_out;
rt1305->pll_src = source;
return 0;
}
static int rt1305_probe(struct snd_soc_component *component)
{
struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
rt1305->component = component;
/* initial settings */
rt1305_reg_init(component);
return 0;
}
static void rt1305_remove(struct snd_soc_component *component)
{
struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
rt1305_reset(rt1305->regmap);
}
#ifdef CONFIG_PM
static int rt1305_suspend(struct snd_soc_component *component)
{
struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
regcache_cache_only(rt1305->regmap, true);
regcache_mark_dirty(rt1305->regmap);
return 0;
}
static int rt1305_resume(struct snd_soc_component *component)
{
struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
regcache_cache_only(rt1305->regmap, false);
regcache_sync(rt1305->regmap);
return 0;
}
#else
#define rt1305_suspend NULL
#define rt1305_resume NULL
#endif
#define RT1305_STEREO_RATES SNDRV_PCM_RATE_8000_192000
#define RT1305_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE)
static const struct snd_soc_dai_ops rt1305_aif_dai_ops = {
.hw_params = rt1305_hw_params,
.set_fmt = rt1305_set_dai_fmt,
};
static struct snd_soc_dai_driver rt1305_dai[] = {
{
.name = "rt1305-aif",
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT1305_STEREO_RATES,
.formats = RT1305_FORMATS,
},
.ops = &rt1305_aif_dai_ops,
},
};
static const struct snd_soc_component_driver soc_component_dev_rt1305 = {
.probe = rt1305_probe,
.remove = rt1305_remove,
.suspend = rt1305_suspend,
.resume = rt1305_resume,
.controls = rt1305_snd_controls,
.num_controls = ARRAY_SIZE(rt1305_snd_controls),
.dapm_widgets = rt1305_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt1305_dapm_widgets),
.dapm_routes = rt1305_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(rt1305_dapm_routes),
.set_sysclk = rt1305_set_component_sysclk,
.set_pll = rt1305_set_component_pll,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config rt1305_regmap = {
.reg_bits = 8,
.val_bits = 16,
.max_register = RT1305_MAX_REG + 1 + (ARRAY_SIZE(rt1305_ranges) *
RT1305_PR_SPACING),
.volatile_reg = rt1305_volatile_register,
.readable_reg = rt1305_readable_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = rt1305_reg,
.num_reg_defaults = ARRAY_SIZE(rt1305_reg),
.ranges = rt1305_ranges,
.num_ranges = ARRAY_SIZE(rt1305_ranges),
.use_single_read = true,
.use_single_write = true,
};
#if defined(CONFIG_OF)
static const struct of_device_id rt1305_of_match[] = {
{ .compatible = "realtek,rt1305", },
{ .compatible = "realtek,rt1306", },
{},
};
MODULE_DEVICE_TABLE(of, rt1305_of_match);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id rt1305_acpi_match[] = {
{"10EC1305", 0,},
{"10EC1306", 0,},
{},
};
MODULE_DEVICE_TABLE(acpi, rt1305_acpi_match);
#endif
static const struct i2c_device_id rt1305_i2c_id[] = {
{ "rt1305", 0 },
{ "rt1306", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, rt1305_i2c_id);
static void rt1305_calibrate(struct rt1305_priv *rt1305)
{
unsigned int valmsb, vallsb, offsetl, offsetr;
unsigned int rh, rl, rhl, r0ohm;
u64 r0l, r0r;
regcache_cache_bypass(rt1305->regmap, true);
rt1305_reset(rt1305->regmap);
regmap_write(rt1305->regmap, RT1305_ADC_SET_3, 0x0219);
regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xcf, 0x5548);
regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc1, 0x0320);
regmap_write(rt1305->regmap, RT1305_CLOCK_DETECT, 0x1000);
regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0600);
regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xffd0);
regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0080);
regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880);
regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0dfe);
/* Sin Gen */
regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x0442);
regmap_write(rt1305->regmap, RT1305_CAL_EFUSE_CLOCK, 0xb000);
regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc3, 0xd4a0);
regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xcc, 0x00cc);
regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc1, 0x0320);
regmap_write(rt1305->regmap, RT1305_POWER_STATUS, 0x0000);
regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0xffff);
regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfc20);
regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x06, 0x00c0);
regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfca0);
regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfce0);
regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfcf0);
/* EFUSE read */
regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0080);
regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880);
regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880);
regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfce0);
regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfca0);
regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfc20);
regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x06, 0x0000);
regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0000);
regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_5, &valmsb);
regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_6, &vallsb);
offsetl = valmsb << 16 | vallsb;
regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_7, &valmsb);
regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_8, &vallsb);
offsetr = valmsb << 16 | vallsb;
pr_info("DC offsetl=0x%x, offsetr=0x%x\n", offsetl, offsetr);
/* R0 calibration */
regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x9542);
regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfcf0);
regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0xffff);
regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x1dfe);
regmap_write(rt1305->regmap, RT1305_SILENCE_DETECT, 0x0e13);
regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0650);
regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x50, 0x0064);
regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x51, 0x0770);
regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x52, 0xc30c);
regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0x8200);
regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xfb00);
regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xff80);
msleep(2000);
regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x55, &rh);
regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x56, &rl);
rhl = (rh << 16) | rl;
r0ohm = (rhl*10) / 33554432;
pr_debug("Left_rhl = 0x%x rh=0x%x rl=0x%x\n", rhl, rh, rl);
pr_info("Left channel %d.%dohm\n", (r0ohm/10), (r0ohm%10));
r0l = 562949953421312ULL;
if (rhl != 0)
do_div(r0l, rhl);
pr_debug("Left_r0 = 0x%llx\n", r0l);
regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0x9200);
regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xfb00);
regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xff80);
msleep(2000);
regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x55, &rh);
regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x56, &rl);
rhl = (rh << 16) | rl;
r0ohm = (rhl*10) / 33554432;
pr_debug("Right_rhl = 0x%x rh=0x%x rl=0x%x\n", rhl, rh, rl);
pr_info("Right channel %d.%dohm\n", (r0ohm/10), (r0ohm%10));
r0r = 562949953421312ULL;
if (rhl != 0)
do_div(r0r, rhl);
pr_debug("Right_r0 = 0x%llx\n", r0r);
regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0xc2ec);
if ((r0l > R0_UPPER) && (r0l < R0_LOWER) &&
(r0r > R0_UPPER) && (r0r < R0_LOWER)) {
regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x4e,
(r0l >> 16) & 0xffff);
regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x4f,
r0l & 0xffff);
regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xfe,
((r0r >> 16) & 0xffff) | 0xf800);
regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xfd,
r0r & 0xffff);
} else {
pr_err("R0 calibration failed\n");
}
/* restore some registers */
regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0dfe);
usleep_range(200000, 400000);
regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x0442);
regmap_write(rt1305->regmap, RT1305_CLOCK_DETECT, 0x3000);
regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0400);
regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0000);
regmap_write(rt1305->regmap, RT1305_CAL_EFUSE_CLOCK, 0x8000);
regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0x1020);
regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0x0000);
regcache_cache_bypass(rt1305->regmap, false);
}
static int rt1305_i2c_probe(struct i2c_client *i2c)
{
struct rt1305_priv *rt1305;
int ret;
unsigned int val;
rt1305 = devm_kzalloc(&i2c->dev, sizeof(struct rt1305_priv),
GFP_KERNEL);
if (rt1305 == NULL)
return -ENOMEM;
i2c_set_clientdata(i2c, rt1305);
rt1305->regmap = devm_regmap_init_i2c(i2c, &rt1305_regmap);
if (IS_ERR(rt1305->regmap)) {
ret = PTR_ERR(rt1305->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
regmap_read(rt1305->regmap, RT1305_DEVICE_ID, &val);
if (val != RT1305_DEVICE_ID_NUM) {
dev_err(&i2c->dev,
"Device with ID register %x is not rt1305\n", val);
return -ENODEV;
}
rt1305_reset(rt1305->regmap);
rt1305_calibrate(rt1305);
return devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_rt1305,
rt1305_dai, ARRAY_SIZE(rt1305_dai));
}
static void rt1305_i2c_shutdown(struct i2c_client *client)
{
struct rt1305_priv *rt1305 = i2c_get_clientdata(client);
rt1305_reset(rt1305->regmap);
}
static struct i2c_driver rt1305_i2c_driver = {
.driver = {
.name = "rt1305",
#if defined(CONFIG_OF)
.of_match_table = rt1305_of_match,
#endif
#if defined(CONFIG_ACPI)
.acpi_match_table = ACPI_PTR(rt1305_acpi_match)
#endif
},
.probe = rt1305_i2c_probe,
.shutdown = rt1305_i2c_shutdown,
.id_table = rt1305_i2c_id,
};
module_i2c_driver(rt1305_i2c_driver);
MODULE_DESCRIPTION("ASoC RT1305 amplifier driver");
MODULE_AUTHOR("Shuming Fan <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/rt1305.c |
// SPDX-License-Identifier: GPL-2.0
//
// ALSA SoC Texas Instruments TAS2781 Audio Smart Amplifier
//
// Copyright (C) 2022 - 2023 Texas Instruments Incorporated
// https://www.ti.com
//
// The TAS2781 driver implements a flexible and configurable
// algo coefficient setting for one, two, or even multiple
// TAS2781 chips.
//
// Author: Shenghao Ding <[email protected]>
// Author: Kevin Lu <[email protected]>
//
#include <linux/crc8.h>
#include <linux/firmware.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/of_irq.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tas2781.h>
#include <sound/tlv.h>
#include <sound/tas2781-tlv.h>
static const struct i2c_device_id tasdevice_id[] = {
{ "tas2781", TAS2781 },
{}
};
MODULE_DEVICE_TABLE(i2c, tasdevice_id);
#ifdef CONFIG_OF
static const struct of_device_id tasdevice_of_match[] = {
{ .compatible = "ti,tas2781" },
{},
};
MODULE_DEVICE_TABLE(of, tasdevice_of_match);
#endif
/**
* tas2781_digital_getvol - get the volum control
* @kcontrol: control pointer
* @ucontrol: User data
* Customer Kcontrol for tas2781 is primarily for regmap booking, paging
* depends on internal regmap mechanism.
* tas2781 contains book and page two-level register map, especially
* book switching will set the register BXXP00R7F, after switching to the
* correct book, then leverage the mechanism for paging to access the
* register.
*/
static int tas2781_digital_getvol(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct tasdevice_priv *tas_priv = snd_soc_component_get_drvdata(codec);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
return tasdevice_digital_getvol(tas_priv, ucontrol, mc);
}
static int tas2781_digital_putvol(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct tasdevice_priv *tas_priv = snd_soc_component_get_drvdata(codec);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
return tasdevice_digital_putvol(tas_priv, ucontrol, mc);
}
static int tas2781_amp_getvol(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct tasdevice_priv *tas_priv = snd_soc_component_get_drvdata(codec);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
return tasdevice_amp_getvol(tas_priv, ucontrol, mc);
}
static int tas2781_amp_putvol(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct tasdevice_priv *tas_priv =
snd_soc_component_get_drvdata(codec);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
return tasdevice_amp_putvol(tas_priv, ucontrol, mc);
}
static int tas2781_force_fwload_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct tasdevice_priv *tas_priv =
snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = (int)tas_priv->force_fwload_status;
dev_dbg(tas_priv->dev, "%s : Force FWload %s\n", __func__,
tas_priv->force_fwload_status ? "ON" : "OFF");
return 0;
}
static int tas2781_force_fwload_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct tasdevice_priv *tas_priv =
snd_soc_component_get_drvdata(component);
bool change, val = (bool)ucontrol->value.integer.value[0];
if (tas_priv->force_fwload_status == val)
change = false;
else {
change = true;
tas_priv->force_fwload_status = val;
}
dev_dbg(tas_priv->dev, "%s : Force FWload %s\n", __func__,
tas_priv->force_fwload_status ? "ON" : "OFF");
return change;
}
static const struct snd_kcontrol_new tas2781_snd_controls[] = {
SOC_SINGLE_RANGE_EXT_TLV("Speaker Analog Gain", TAS2781_AMP_LEVEL,
1, 0, 20, 0, tas2781_amp_getvol,
tas2781_amp_putvol, amp_vol_tlv),
SOC_SINGLE_RANGE_EXT_TLV("Speaker Digital Gain", TAS2781_DVC_LVL,
0, 0, 200, 1, tas2781_digital_getvol,
tas2781_digital_putvol, dvc_tlv),
SOC_SINGLE_BOOL_EXT("Speaker Force Firmware Load", 0,
tas2781_force_fwload_get, tas2781_force_fwload_put),
};
static int tasdevice_set_profile_id(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct tasdevice_priv *tas_priv = snd_soc_component_get_drvdata(codec);
int ret = 0;
if (tas_priv->rcabin.profile_cfg_id !=
ucontrol->value.integer.value[0]) {
tas_priv->rcabin.profile_cfg_id =
ucontrol->value.integer.value[0];
ret = 1;
}
return ret;
}
static int tasdevice_info_programs(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct tasdevice_priv *tas_priv = snd_soc_component_get_drvdata(codec);
struct tasdevice_fw *tas_fw = tas_priv->fmw;
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = 1;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = (int)tas_fw->nr_programs;
return 0;
}
static int tasdevice_info_configurations(
struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
{
struct snd_soc_component *codec =
snd_soc_kcontrol_component(kcontrol);
struct tasdevice_priv *tas_priv = snd_soc_component_get_drvdata(codec);
struct tasdevice_fw *tas_fw = tas_priv->fmw;
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = 1;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = (int)tas_fw->nr_configurations - 1;
return 0;
}
static int tasdevice_info_profile(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct tasdevice_priv *tas_priv = snd_soc_component_get_drvdata(codec);
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = 1;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = tas_priv->rcabin.ncfgs - 1;
return 0;
}
static int tasdevice_get_profile_id(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct tasdevice_priv *tas_priv = snd_soc_component_get_drvdata(codec);
ucontrol->value.integer.value[0] = tas_priv->rcabin.profile_cfg_id;
return 0;
}
static int tasdevice_create_control(struct tasdevice_priv *tas_priv)
{
struct snd_kcontrol_new *prof_ctrls;
int nr_controls = 1;
int mix_index = 0;
int ret;
char *name;
prof_ctrls = devm_kcalloc(tas_priv->dev, nr_controls,
sizeof(prof_ctrls[0]), GFP_KERNEL);
if (!prof_ctrls) {
ret = -ENOMEM;
goto out;
}
/* Create a mixer item for selecting the active profile */
name = devm_kzalloc(tas_priv->dev, SNDRV_CTL_ELEM_ID_NAME_MAXLEN,
GFP_KERNEL);
if (!name) {
ret = -ENOMEM;
goto out;
}
scnprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "Speaker Profile Id");
prof_ctrls[mix_index].name = name;
prof_ctrls[mix_index].iface = SNDRV_CTL_ELEM_IFACE_MIXER;
prof_ctrls[mix_index].info = tasdevice_info_profile;
prof_ctrls[mix_index].get = tasdevice_get_profile_id;
prof_ctrls[mix_index].put = tasdevice_set_profile_id;
mix_index++;
ret = snd_soc_add_component_controls(tas_priv->codec,
prof_ctrls, nr_controls < mix_index ? nr_controls : mix_index);
out:
return ret;
}
static int tasdevice_program_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct tasdevice_priv *tas_priv = snd_soc_component_get_drvdata(codec);
ucontrol->value.integer.value[0] = tas_priv->cur_prog;
return 0;
}
static int tasdevice_program_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct tasdevice_priv *tas_priv = snd_soc_component_get_drvdata(codec);
unsigned int nr_program = ucontrol->value.integer.value[0];
int ret = 0;
if (tas_priv->cur_prog != nr_program) {
tas_priv->cur_prog = nr_program;
ret = 1;
}
return ret;
}
static int tasdevice_configuration_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct tasdevice_priv *tas_priv = snd_soc_component_get_drvdata(codec);
ucontrol->value.integer.value[0] = tas_priv->cur_conf;
return 0;
}
static int tasdevice_configuration_put(
struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct tasdevice_priv *tas_priv = snd_soc_component_get_drvdata(codec);
unsigned int nr_configuration = ucontrol->value.integer.value[0];
int ret = 0;
if (tas_priv->cur_conf != nr_configuration) {
tas_priv->cur_conf = nr_configuration;
ret = 1;
}
return ret;
}
static int tasdevice_dsp_create_ctrls(
struct tasdevice_priv *tas_priv)
{
struct snd_kcontrol_new *dsp_ctrls;
char *prog_name, *conf_name;
int nr_controls = 2;
int mix_index = 0;
int ret;
/* Alloc kcontrol via devm_kzalloc, which don't manually
* free the kcontrol
*/
dsp_ctrls = devm_kcalloc(tas_priv->dev, nr_controls,
sizeof(dsp_ctrls[0]), GFP_KERNEL);
if (!dsp_ctrls) {
ret = -ENOMEM;
goto out;
}
/* Create a mixer item for selecting the active profile */
prog_name = devm_kzalloc(tas_priv->dev,
SNDRV_CTL_ELEM_ID_NAME_MAXLEN, GFP_KERNEL);
conf_name = devm_kzalloc(tas_priv->dev, SNDRV_CTL_ELEM_ID_NAME_MAXLEN,
GFP_KERNEL);
if (!prog_name || !conf_name) {
ret = -ENOMEM;
goto out;
}
scnprintf(prog_name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN,
"Speaker Program Id");
dsp_ctrls[mix_index].name = prog_name;
dsp_ctrls[mix_index].iface = SNDRV_CTL_ELEM_IFACE_MIXER;
dsp_ctrls[mix_index].info = tasdevice_info_programs;
dsp_ctrls[mix_index].get = tasdevice_program_get;
dsp_ctrls[mix_index].put = tasdevice_program_put;
mix_index++;
scnprintf(conf_name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN,
"Speaker Config Id");
dsp_ctrls[mix_index].name = conf_name;
dsp_ctrls[mix_index].iface = SNDRV_CTL_ELEM_IFACE_MIXER;
dsp_ctrls[mix_index].info = tasdevice_info_configurations;
dsp_ctrls[mix_index].get = tasdevice_configuration_get;
dsp_ctrls[mix_index].put = tasdevice_configuration_put;
mix_index++;
ret = snd_soc_add_component_controls(tas_priv->codec, dsp_ctrls,
nr_controls < mix_index ? nr_controls : mix_index);
out:
return ret;
}
static void tasdevice_fw_ready(const struct firmware *fmw,
void *context)
{
struct tasdevice_priv *tas_priv = context;
int ret = 0;
int i;
mutex_lock(&tas_priv->codec_lock);
ret = tasdevice_rca_parser(tas_priv, fmw);
if (ret)
goto out;
tasdevice_create_control(tas_priv);
tasdevice_dsp_remove(tas_priv);
tasdevice_calbin_remove(tas_priv);
tas_priv->fw_state = TASDEVICE_DSP_FW_PENDING;
scnprintf(tas_priv->coef_binaryname, 64, "%s_coef.bin",
tas_priv->dev_name);
ret = tasdevice_dsp_parser(tas_priv);
if (ret) {
dev_err(tas_priv->dev, "dspfw load %s error\n",
tas_priv->coef_binaryname);
tas_priv->fw_state = TASDEVICE_DSP_FW_FAIL;
goto out;
}
tasdevice_dsp_create_ctrls(tas_priv);
tas_priv->fw_state = TASDEVICE_DSP_FW_ALL_OK;
/* If calibrated data occurs error, dsp will still works with default
* calibrated data inside algo.
*/
for (i = 0; i < tas_priv->ndev; i++) {
scnprintf(tas_priv->cal_binaryname[i], 64, "%s_cal_0x%02x.bin",
tas_priv->dev_name, tas_priv->tasdevice[i].dev_addr);
ret = tas2781_load_calibration(tas_priv,
tas_priv->cal_binaryname[i], i);
if (ret != 0)
dev_err(tas_priv->dev,
"%s: load %s error, default will effect\n",
__func__, tas_priv->cal_binaryname[i]);
}
tasdevice_prmg_calibdata_load(tas_priv, 0);
tas_priv->cur_prog = 0;
out:
if (tas_priv->fw_state == TASDEVICE_DSP_FW_FAIL) {
/*If DSP FW fail, kcontrol won't be created */
tasdevice_config_info_remove(tas_priv);
tasdevice_dsp_remove(tas_priv);
}
mutex_unlock(&tas_priv->codec_lock);
if (fmw)
release_firmware(fmw);
}
static int tasdevice_dapm_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *codec = snd_soc_dapm_to_component(w->dapm);
struct tasdevice_priv *tas_priv = snd_soc_component_get_drvdata(codec);
int state = 0;
/* Codec Lock Hold */
mutex_lock(&tas_priv->codec_lock);
if (event == SND_SOC_DAPM_PRE_PMD)
state = 1;
tasdevice_tuning_switch(tas_priv, state);
/* Codec Lock Release*/
mutex_unlock(&tas_priv->codec_lock);
return 0;
}
static const struct snd_soc_dapm_widget tasdevice_dapm_widgets[] = {
SND_SOC_DAPM_AIF_IN("ASI", "ASI Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT_E("ASI OUT", "ASI Capture", 0, SND_SOC_NOPM,
0, 0, tasdevice_dapm_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SPK("SPK", tasdevice_dapm_event),
SND_SOC_DAPM_OUTPUT("OUT"),
SND_SOC_DAPM_INPUT("DMIC")
};
static const struct snd_soc_dapm_route tasdevice_audio_map[] = {
{"SPK", NULL, "ASI"},
{"OUT", NULL, "SPK"},
{"ASI OUT", NULL, "DMIC"}
};
static int tasdevice_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *codec = dai->component;
struct tasdevice_priv *tas_priv = snd_soc_component_get_drvdata(codec);
int ret = 0;
if (tas_priv->fw_state != TASDEVICE_DSP_FW_ALL_OK) {
dev_err(tas_priv->dev, "DSP bin file not loaded\n");
ret = -EINVAL;
}
return ret;
}
static int tasdevice_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct tasdevice_priv *tas_priv = snd_soc_dai_get_drvdata(dai);
unsigned int slot_width;
unsigned int fsrate;
int bclk_rate;
int rc = 0;
fsrate = params_rate(params);
switch (fsrate) {
case 48000:
case 44100:
break;
default:
dev_err(tas_priv->dev, "%s: incorrect sample rate = %u\n",
__func__, fsrate);
rc = -EINVAL;
goto out;
}
slot_width = params_width(params);
switch (slot_width) {
case 16:
case 20:
case 24:
case 32:
break;
default:
dev_err(tas_priv->dev, "%s: incorrect slot width = %u\n",
__func__, slot_width);
rc = -EINVAL;
goto out;
}
bclk_rate = snd_soc_params_to_bclk(params);
if (bclk_rate < 0) {
dev_err(tas_priv->dev, "%s: incorrect bclk rate = %d\n",
__func__, bclk_rate);
rc = bclk_rate;
goto out;
}
out:
return rc;
}
static int tasdevice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct tasdevice_priv *tas_priv = snd_soc_dai_get_drvdata(codec_dai);
tas_priv->sysclk = freq;
return 0;
}
static const struct snd_soc_dai_ops tasdevice_dai_ops = {
.startup = tasdevice_startup,
.hw_params = tasdevice_hw_params,
.set_sysclk = tasdevice_set_dai_sysclk,
};
static struct snd_soc_dai_driver tasdevice_dai_driver[] = {
{
.name = "tas2781_codec",
.id = 0,
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 4,
.rates = TASDEVICE_RATES,
.formats = TASDEVICE_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 4,
.rates = TASDEVICE_RATES,
.formats = TASDEVICE_FORMATS,
},
.ops = &tasdevice_dai_ops,
.symmetric_rate = 1,
},
};
static int tasdevice_codec_probe(struct snd_soc_component *codec)
{
struct tasdevice_priv *tas_priv = snd_soc_component_get_drvdata(codec);
return tascodec_init(tas_priv, codec, tasdevice_fw_ready);
}
static void tasdevice_deinit(void *context)
{
struct tasdevice_priv *tas_priv = (struct tasdevice_priv *) context;
tasdevice_config_info_remove(tas_priv);
tasdevice_dsp_remove(tas_priv);
tasdevice_calbin_remove(tas_priv);
tas_priv->fw_state = TASDEVICE_DSP_FW_PENDING;
}
static void tasdevice_codec_remove(
struct snd_soc_component *codec)
{
struct tasdevice_priv *tas_priv = snd_soc_component_get_drvdata(codec);
tasdevice_deinit(tas_priv);
}
static const struct snd_soc_component_driver
soc_codec_driver_tasdevice = {
.probe = tasdevice_codec_probe,
.remove = tasdevice_codec_remove,
.controls = tas2781_snd_controls,
.num_controls = ARRAY_SIZE(tas2781_snd_controls),
.dapm_widgets = tasdevice_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(tasdevice_dapm_widgets),
.dapm_routes = tasdevice_audio_map,
.num_dapm_routes = ARRAY_SIZE(tasdevice_audio_map),
.idle_bias_on = 1,
.endianness = 1,
};
static void tasdevice_parse_dt(struct tasdevice_priv *tas_priv)
{
struct i2c_client *client = (struct i2c_client *)tas_priv->client;
unsigned int dev_addrs[TASDEVICE_MAX_CHANNELS];
int rc, i, ndev = 0;
if (tas_priv->isacpi) {
ndev = device_property_read_u32_array(&client->dev,
"ti,audio-slots", NULL, 0);
if (ndev <= 0) {
ndev = 1;
dev_addrs[0] = client->addr;
} else {
ndev = (ndev < ARRAY_SIZE(dev_addrs))
? ndev : ARRAY_SIZE(dev_addrs);
ndev = device_property_read_u32_array(&client->dev,
"ti,audio-slots", dev_addrs, ndev);
}
tas_priv->irq_info.irq_gpio =
acpi_dev_gpio_irq_get(ACPI_COMPANION(&client->dev), 0);
} else {
struct device_node *np = tas_priv->dev->of_node;
#ifdef CONFIG_OF
const __be32 *reg, *reg_end;
int len, sw, aw;
aw = of_n_addr_cells(np);
sw = of_n_size_cells(np);
if (sw == 0) {
reg = (const __be32 *)of_get_property(np,
"reg", &len);
reg_end = reg + len/sizeof(*reg);
ndev = 0;
do {
dev_addrs[ndev] = of_read_number(reg, aw);
reg += aw;
ndev++;
} while (reg < reg_end);
} else {
ndev = 1;
dev_addrs[0] = client->addr;
}
#else
ndev = 1;
dev_addrs[0] = client->addr;
#endif
tas_priv->irq_info.irq_gpio = of_irq_get(np, 0);
}
tas_priv->ndev = ndev;
for (i = 0; i < ndev; i++)
tas_priv->tasdevice[i].dev_addr = dev_addrs[i];
tas_priv->reset = devm_gpiod_get_optional(&client->dev,
"reset-gpios", GPIOD_OUT_HIGH);
if (IS_ERR(tas_priv->reset))
dev_err(tas_priv->dev, "%s Can't get reset GPIO\n",
__func__);
strcpy(tas_priv->dev_name, tasdevice_id[tas_priv->chip_id].name);
if (gpio_is_valid(tas_priv->irq_info.irq_gpio)) {
rc = gpio_request(tas_priv->irq_info.irq_gpio,
"AUDEV-IRQ");
if (!rc) {
gpio_direction_input(
tas_priv->irq_info.irq_gpio);
tas_priv->irq_info.irq =
gpio_to_irq(tas_priv->irq_info.irq_gpio);
} else
dev_err(tas_priv->dev, "%s: GPIO %d request error\n",
__func__, tas_priv->irq_info.irq_gpio);
} else
dev_err(tas_priv->dev,
"Looking up irq-gpio property failed %d\n",
tas_priv->irq_info.irq_gpio);
}
static int tasdevice_i2c_probe(struct i2c_client *i2c)
{
const struct i2c_device_id *id = i2c_match_id(tasdevice_id, i2c);
const struct acpi_device_id *acpi_id;
struct tasdevice_priv *tas_priv;
int ret;
tas_priv = tasdevice_kzalloc(i2c);
if (!tas_priv)
return -ENOMEM;
if (ACPI_HANDLE(&i2c->dev)) {
acpi_id = acpi_match_device(i2c->dev.driver->acpi_match_table,
&i2c->dev);
if (!acpi_id) {
dev_err(&i2c->dev, "No driver data\n");
ret = -EINVAL;
goto err;
}
tas_priv->chip_id = acpi_id->driver_data;
tas_priv->isacpi = true;
} else {
tas_priv->chip_id = id ? id->driver_data : 0;
tas_priv->isacpi = false;
}
tasdevice_parse_dt(tas_priv);
ret = tasdevice_init(tas_priv);
if (ret)
goto err;
ret = devm_snd_soc_register_component(tas_priv->dev,
&soc_codec_driver_tasdevice,
tasdevice_dai_driver, ARRAY_SIZE(tasdevice_dai_driver));
if (ret) {
dev_err(tas_priv->dev, "%s: codec register error:0x%08x\n",
__func__, ret);
goto err;
}
err:
if (ret < 0)
tasdevice_remove(tas_priv);
return ret;
}
static void tasdevice_i2c_remove(struct i2c_client *client)
{
struct tasdevice_priv *tas_priv = i2c_get_clientdata(client);
tasdevice_remove(tas_priv);
}
#ifdef CONFIG_ACPI
static const struct acpi_device_id tasdevice_acpi_match[] = {
{ "TAS2781", TAS2781 },
{},
};
MODULE_DEVICE_TABLE(acpi, tasdevice_acpi_match);
#endif
static struct i2c_driver tasdevice_i2c_driver = {
.driver = {
.name = "tas2781-codec",
.of_match_table = of_match_ptr(tasdevice_of_match),
#ifdef CONFIG_ACPI
.acpi_match_table = ACPI_PTR(tasdevice_acpi_match),
#endif
},
.probe = tasdevice_i2c_probe,
.remove = tasdevice_i2c_remove,
.id_table = tasdevice_id,
};
module_i2c_driver(tasdevice_i2c_driver);
MODULE_AUTHOR("Shenghao Ding <[email protected]>");
MODULE_AUTHOR("Kevin Lu <[email protected]>");
MODULE_DESCRIPTION("ASoC TAS2781 Driver");
MODULE_LICENSE("GPL");
MODULE_IMPORT_NS(SND_SOC_TAS2781_FMWLIB);
| linux-master | sound/soc/codecs/tas2781-i2c.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* extcon-arizona.c - Extcon driver Wolfson Arizona devices
*
* Copyright (C) 2012-2014 Wolfson Microelectronics plc
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/err.h>
#include <linux/gpio/consumer.h>
#include <linux/gpio.h>
#include <linux/input.h>
#include <linux/pm_runtime.h>
#include <linux/property.h>
#include <linux/regulator/consumer.h>
#include <sound/jack.h>
#include <sound/soc.h>
#include <linux/mfd/arizona/core.h>
#include <linux/mfd/arizona/pdata.h>
#include <linux/mfd/arizona/registers.h>
#include <dt-bindings/mfd/arizona.h>
#include "arizona.h"
#define ARIZONA_MAX_MICD_RANGE 8
/*
* The hardware supports 8 ranges / buttons, but the snd-jack interface
* only supports 6 buttons (button 0-5).
*/
#define ARIZONA_MAX_MICD_BUTTONS 6
#define ARIZONA_MICD_CLAMP_MODE_JDL 0x4
#define ARIZONA_MICD_CLAMP_MODE_JDH 0x5
#define ARIZONA_MICD_CLAMP_MODE_JDL_GP5H 0x9
#define ARIZONA_MICD_CLAMP_MODE_JDH_GP5H 0xb
#define ARIZONA_TST_CAP_DEFAULT 0x3
#define ARIZONA_TST_CAP_CLAMP 0x1
#define ARIZONA_HPDET_MAX 10000
#define HPDET_DEBOUNCE 500
#define DEFAULT_MICD_TIMEOUT 2000
#define ARIZONA_HPDET_WAIT_COUNT 15
#define ARIZONA_HPDET_WAIT_DELAY_MS 20
#define QUICK_HEADPHONE_MAX_OHM 3
#define MICROPHONE_MIN_OHM 1257
#define MICROPHONE_MAX_OHM 30000
#define MICD_DBTIME_TWO_READINGS 2
#define MICD_DBTIME_FOUR_READINGS 4
#define MICD_LVL_1_TO_7 (ARIZONA_MICD_LVL_1 | ARIZONA_MICD_LVL_2 | \
ARIZONA_MICD_LVL_3 | ARIZONA_MICD_LVL_4 | \
ARIZONA_MICD_LVL_5 | ARIZONA_MICD_LVL_6 | \
ARIZONA_MICD_LVL_7)
#define MICD_LVL_0_TO_7 (ARIZONA_MICD_LVL_0 | MICD_LVL_1_TO_7)
#define MICD_LVL_0_TO_8 (MICD_LVL_0_TO_7 | ARIZONA_MICD_LVL_8)
static const struct arizona_micd_config micd_default_modes[] = {
{ ARIZONA_ACCDET_SRC, 1, 0 },
{ 0, 2, 1 },
};
static const struct arizona_micd_range micd_default_ranges[] = {
{ .max = 11, .key = BTN_0 },
{ .max = 28, .key = BTN_1 },
{ .max = 54, .key = BTN_2 },
{ .max = 100, .key = BTN_3 },
{ .max = 186, .key = BTN_4 },
{ .max = 430, .key = BTN_5 },
};
/* The number of levels in arizona_micd_levels valid for button thresholds */
#define ARIZONA_NUM_MICD_BUTTON_LEVELS 64
static const int arizona_micd_levels[] = {
3, 6, 8, 11, 13, 16, 18, 21, 23, 26, 28, 31, 34, 36, 39, 41, 44, 46,
49, 52, 54, 57, 60, 62, 65, 67, 70, 73, 75, 78, 81, 83, 89, 94, 100,
105, 111, 116, 122, 127, 139, 150, 161, 173, 186, 196, 209, 220, 245,
270, 295, 321, 348, 375, 402, 430, 489, 550, 614, 681, 752, 903, 1071,
1257, 30000,
};
static void arizona_start_hpdet_acc_id(struct arizona_priv *info);
static void arizona_extcon_hp_clamp(struct arizona_priv *info,
bool clamp)
{
struct arizona *arizona = info->arizona;
unsigned int mask = 0, val = 0;
unsigned int cap_sel = 0;
int ret;
switch (arizona->type) {
case WM8998:
case WM1814:
mask = 0;
break;
case WM5110:
case WM8280:
mask = ARIZONA_HP1L_SHRTO | ARIZONA_HP1L_FLWR |
ARIZONA_HP1L_SHRTI;
if (clamp) {
val = ARIZONA_HP1L_SHRTO;
cap_sel = ARIZONA_TST_CAP_CLAMP;
} else {
val = ARIZONA_HP1L_FLWR | ARIZONA_HP1L_SHRTI;
cap_sel = ARIZONA_TST_CAP_DEFAULT;
}
ret = regmap_update_bits(arizona->regmap,
ARIZONA_HP_TEST_CTRL_1,
ARIZONA_HP1_TST_CAP_SEL_MASK,
cap_sel);
if (ret)
dev_warn(arizona->dev, "Failed to set TST_CAP_SEL: %d\n", ret);
break;
default:
mask = ARIZONA_RMV_SHRT_HP1L;
if (clamp)
val = ARIZONA_RMV_SHRT_HP1L;
break;
}
snd_soc_dapm_mutex_lock(arizona->dapm);
arizona->hpdet_clamp = clamp;
/* Keep the HP output stages disabled while doing the clamp */
if (clamp) {
ret = regmap_update_bits(arizona->regmap,
ARIZONA_OUTPUT_ENABLES_1,
ARIZONA_OUT1L_ENA |
ARIZONA_OUT1R_ENA, 0);
if (ret)
dev_warn(arizona->dev, "Failed to disable headphone outputs: %d\n", ret);
}
if (mask) {
ret = regmap_update_bits(arizona->regmap, ARIZONA_HP_CTRL_1L,
mask, val);
if (ret)
dev_warn(arizona->dev, "Failed to do clamp: %d\n", ret);
ret = regmap_update_bits(arizona->regmap, ARIZONA_HP_CTRL_1R,
mask, val);
if (ret)
dev_warn(arizona->dev, "Failed to do clamp: %d\n", ret);
}
/* Restore the desired state while not doing the clamp */
if (!clamp) {
ret = regmap_update_bits(arizona->regmap,
ARIZONA_OUTPUT_ENABLES_1,
ARIZONA_OUT1L_ENA |
ARIZONA_OUT1R_ENA, arizona->hp_ena);
if (ret)
dev_warn(arizona->dev, "Failed to restore headphone outputs: %d\n", ret);
}
snd_soc_dapm_mutex_unlock(arizona->dapm);
}
static void arizona_extcon_set_mode(struct arizona_priv *info, int mode)
{
struct arizona *arizona = info->arizona;
mode %= info->micd_num_modes;
gpiod_set_value_cansleep(info->micd_pol_gpio,
info->micd_modes[mode].gpio);
regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1,
ARIZONA_MICD_BIAS_SRC_MASK,
info->micd_modes[mode].bias <<
ARIZONA_MICD_BIAS_SRC_SHIFT);
regmap_update_bits(arizona->regmap, ARIZONA_ACCESSORY_DETECT_MODE_1,
ARIZONA_ACCDET_SRC, info->micd_modes[mode].src);
info->micd_mode = mode;
dev_dbg(arizona->dev, "Set jack polarity to %d\n", mode);
}
static const char *arizona_extcon_get_micbias(struct arizona_priv *info)
{
switch (info->micd_modes[0].bias) {
case 1:
return "MICBIAS1";
case 2:
return "MICBIAS2";
case 3:
return "MICBIAS3";
default:
return "MICVDD";
}
}
static void arizona_extcon_pulse_micbias(struct arizona_priv *info)
{
struct arizona *arizona = info->arizona;
const char *widget = arizona_extcon_get_micbias(info);
struct snd_soc_dapm_context *dapm = arizona->dapm;
struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
int ret;
ret = snd_soc_component_force_enable_pin(component, widget);
if (ret)
dev_warn(arizona->dev, "Failed to enable %s: %d\n", widget, ret);
snd_soc_dapm_sync(dapm);
if (!arizona->pdata.micd_force_micbias) {
ret = snd_soc_component_disable_pin(component, widget);
if (ret)
dev_warn(arizona->dev, "Failed to disable %s: %d\n", widget, ret);
snd_soc_dapm_sync(dapm);
}
}
static void arizona_start_mic(struct arizona_priv *info)
{
struct arizona *arizona = info->arizona;
bool change;
int ret;
unsigned int mode;
/* Microphone detection can't use idle mode */
pm_runtime_get_sync(arizona->dev);
if (info->detecting) {
ret = regulator_allow_bypass(info->micvdd, false);
if (ret)
dev_err(arizona->dev, "Failed to regulate MICVDD: %d\n", ret);
}
ret = regulator_enable(info->micvdd);
if (ret)
dev_err(arizona->dev, "Failed to enable MICVDD: %d\n", ret);
if (info->micd_reva) {
const struct reg_sequence reva[] = {
{ 0x80, 0x3 },
{ 0x294, 0x0 },
{ 0x80, 0x0 },
};
regmap_multi_reg_write(arizona->regmap, reva, ARRAY_SIZE(reva));
}
if (info->detecting && arizona->pdata.micd_software_compare)
mode = ARIZONA_ACCDET_MODE_ADC;
else
mode = ARIZONA_ACCDET_MODE_MIC;
regmap_update_bits(arizona->regmap,
ARIZONA_ACCESSORY_DETECT_MODE_1,
ARIZONA_ACCDET_MODE_MASK, mode);
arizona_extcon_pulse_micbias(info);
ret = regmap_update_bits_check(arizona->regmap, ARIZONA_MIC_DETECT_1,
ARIZONA_MICD_ENA, ARIZONA_MICD_ENA,
&change);
if (ret < 0) {
dev_err(arizona->dev, "Failed to enable micd: %d\n", ret);
} else if (!change) {
regulator_disable(info->micvdd);
pm_runtime_put_autosuspend(arizona->dev);
}
}
static void arizona_stop_mic(struct arizona_priv *info)
{
struct arizona *arizona = info->arizona;
const char *widget = arizona_extcon_get_micbias(info);
struct snd_soc_dapm_context *dapm = arizona->dapm;
struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
bool change = false;
int ret;
ret = regmap_update_bits_check(arizona->regmap, ARIZONA_MIC_DETECT_1,
ARIZONA_MICD_ENA, 0,
&change);
if (ret < 0)
dev_err(arizona->dev, "Failed to disable micd: %d\n", ret);
ret = snd_soc_component_disable_pin(component, widget);
if (ret)
dev_warn(arizona->dev, "Failed to disable %s: %d\n", widget, ret);
snd_soc_dapm_sync(dapm);
if (info->micd_reva) {
const struct reg_sequence reva[] = {
{ 0x80, 0x3 },
{ 0x294, 0x2 },
{ 0x80, 0x0 },
};
regmap_multi_reg_write(arizona->regmap, reva, ARRAY_SIZE(reva));
}
ret = regulator_allow_bypass(info->micvdd, true);
if (ret)
dev_err(arizona->dev, "Failed to bypass MICVDD: %d\n", ret);
if (change) {
regulator_disable(info->micvdd);
pm_runtime_mark_last_busy(arizona->dev);
pm_runtime_put_autosuspend(arizona->dev);
}
}
static struct {
unsigned int threshold;
unsigned int factor_a;
unsigned int factor_b;
} arizona_hpdet_b_ranges[] = {
{ 100, 5528, 362464 },
{ 169, 11084, 6186851 },
{ 169, 11065, 65460395 },
};
#define ARIZONA_HPDET_B_RANGE_MAX 0x3fb
static struct {
int min;
int max;
} arizona_hpdet_c_ranges[] = {
{ 0, 30 },
{ 8, 100 },
{ 100, 1000 },
{ 1000, 10000 },
};
static int arizona_hpdet_read(struct arizona_priv *info)
{
struct arizona *arizona = info->arizona;
unsigned int val, range;
int ret;
ret = regmap_read(arizona->regmap, ARIZONA_HEADPHONE_DETECT_2, &val);
if (ret) {
dev_err(arizona->dev, "Failed to read HPDET status: %d\n", ret);
return ret;
}
switch (info->hpdet_ip_version) {
case 0:
if (!(val & ARIZONA_HP_DONE)) {
dev_err(arizona->dev, "HPDET did not complete: %x\n", val);
return -EAGAIN;
}
val &= ARIZONA_HP_LVL_MASK;
break;
case 1:
if (!(val & ARIZONA_HP_DONE_B)) {
dev_err(arizona->dev, "HPDET did not complete: %x\n", val);
return -EAGAIN;
}
ret = regmap_read(arizona->regmap, ARIZONA_HP_DACVAL, &val);
if (ret) {
dev_err(arizona->dev, "Failed to read HP value: %d\n", ret);
return -EAGAIN;
}
regmap_read(arizona->regmap, ARIZONA_HEADPHONE_DETECT_1,
&range);
range = (range & ARIZONA_HP_IMPEDANCE_RANGE_MASK)
>> ARIZONA_HP_IMPEDANCE_RANGE_SHIFT;
if (range < ARRAY_SIZE(arizona_hpdet_b_ranges) - 1 &&
(val < arizona_hpdet_b_ranges[range].threshold ||
val >= ARIZONA_HPDET_B_RANGE_MAX)) {
range++;
dev_dbg(arizona->dev, "Moving to HPDET range %d\n", range);
regmap_update_bits(arizona->regmap,
ARIZONA_HEADPHONE_DETECT_1,
ARIZONA_HP_IMPEDANCE_RANGE_MASK,
range <<
ARIZONA_HP_IMPEDANCE_RANGE_SHIFT);
return -EAGAIN;
}
/* If we go out of range report top of range */
if (val < arizona_hpdet_b_ranges[range].threshold ||
val >= ARIZONA_HPDET_B_RANGE_MAX) {
dev_dbg(arizona->dev, "Measurement out of range\n");
return ARIZONA_HPDET_MAX;
}
dev_dbg(arizona->dev, "HPDET read %d in range %d\n", val, range);
val = arizona_hpdet_b_ranges[range].factor_b
/ ((val * 100) -
arizona_hpdet_b_ranges[range].factor_a);
break;
case 2:
if (!(val & ARIZONA_HP_DONE_B)) {
dev_err(arizona->dev, "HPDET did not complete: %x\n", val);
return -EAGAIN;
}
val &= ARIZONA_HP_LVL_B_MASK;
/* Convert to ohms, the value is in 0.5 ohm increments */
val /= 2;
regmap_read(arizona->regmap, ARIZONA_HEADPHONE_DETECT_1,
&range);
range = (range & ARIZONA_HP_IMPEDANCE_RANGE_MASK)
>> ARIZONA_HP_IMPEDANCE_RANGE_SHIFT;
/* Skip up a range, or report? */
if (range < ARRAY_SIZE(arizona_hpdet_c_ranges) - 1 &&
(val >= arizona_hpdet_c_ranges[range].max)) {
range++;
dev_dbg(arizona->dev, "Moving to HPDET range %d-%d\n",
arizona_hpdet_c_ranges[range].min,
arizona_hpdet_c_ranges[range].max);
regmap_update_bits(arizona->regmap,
ARIZONA_HEADPHONE_DETECT_1,
ARIZONA_HP_IMPEDANCE_RANGE_MASK,
range <<
ARIZONA_HP_IMPEDANCE_RANGE_SHIFT);
return -EAGAIN;
}
if (range && (val < arizona_hpdet_c_ranges[range].min)) {
dev_dbg(arizona->dev, "Reporting range boundary %d\n",
arizona_hpdet_c_ranges[range].min);
val = arizona_hpdet_c_ranges[range].min;
}
break;
default:
dev_warn(arizona->dev, "Unknown HPDET IP revision %d\n", info->hpdet_ip_version);
return -EINVAL;
}
dev_dbg(arizona->dev, "HP impedance %d ohms\n", val);
return val;
}
static int arizona_hpdet_do_id(struct arizona_priv *info, int *reading,
bool *mic)
{
struct arizona *arizona = info->arizona;
int id_gpio = arizona->pdata.hpdet_id_gpio;
if (!arizona->pdata.hpdet_acc_id)
return 0;
/*
* If we're using HPDET for accessory identification we need
* to take multiple measurements, step through them in sequence.
*/
info->hpdet_res[info->num_hpdet_res++] = *reading;
/* Only check the mic directly if we didn't already ID it */
if (id_gpio && info->num_hpdet_res == 1) {
dev_dbg(arizona->dev, "Measuring mic\n");
regmap_update_bits(arizona->regmap,
ARIZONA_ACCESSORY_DETECT_MODE_1,
ARIZONA_ACCDET_MODE_MASK |
ARIZONA_ACCDET_SRC,
ARIZONA_ACCDET_MODE_HPR |
info->micd_modes[0].src);
gpio_set_value_cansleep(id_gpio, 1);
regmap_update_bits(arizona->regmap, ARIZONA_HEADPHONE_DETECT_1,
ARIZONA_HP_POLL, ARIZONA_HP_POLL);
return -EAGAIN;
}
/* OK, got both. Now, compare... */
dev_dbg(arizona->dev, "HPDET measured %d %d\n",
info->hpdet_res[0], info->hpdet_res[1]);
/* Take the headphone impedance for the main report */
*reading = info->hpdet_res[0];
/* Sometimes we get false readings due to slow insert */
if (*reading >= ARIZONA_HPDET_MAX && !info->hpdet_retried) {
dev_dbg(arizona->dev, "Retrying high impedance\n");
info->num_hpdet_res = 0;
info->hpdet_retried = true;
arizona_start_hpdet_acc_id(info);
pm_runtime_put(arizona->dev);
return -EAGAIN;
}
/*
* If we measure the mic as high impedance
*/
if (!id_gpio || info->hpdet_res[1] > 50) {
dev_dbg(arizona->dev, "Detected mic\n");
*mic = true;
info->detecting = true;
} else {
dev_dbg(arizona->dev, "Detected headphone\n");
}
/* Make sure everything is reset back to the real polarity */
regmap_update_bits(arizona->regmap, ARIZONA_ACCESSORY_DETECT_MODE_1,
ARIZONA_ACCDET_SRC, info->micd_modes[0].src);
return 0;
}
static irqreturn_t arizona_hpdet_irq(int irq, void *data)
{
struct arizona_priv *info = data;
struct arizona *arizona = info->arizona;
int id_gpio = arizona->pdata.hpdet_id_gpio;
int ret, reading, state, report;
bool mic = false;
mutex_lock(&info->lock);
/* If we got a spurious IRQ for some reason then ignore it */
if (!info->hpdet_active) {
dev_warn(arizona->dev, "Spurious HPDET IRQ\n");
mutex_unlock(&info->lock);
return IRQ_NONE;
}
/* If the cable was removed while measuring ignore the result */
state = info->jack->status & SND_JACK_MECHANICAL;
if (!state) {
dev_dbg(arizona->dev, "Ignoring HPDET for removed cable\n");
goto done;
}
ret = arizona_hpdet_read(info);
if (ret == -EAGAIN)
goto out;
else if (ret < 0)
goto done;
reading = ret;
/* Reset back to starting range */
regmap_update_bits(arizona->regmap,
ARIZONA_HEADPHONE_DETECT_1,
ARIZONA_HP_IMPEDANCE_RANGE_MASK | ARIZONA_HP_POLL,
0);
ret = arizona_hpdet_do_id(info, &reading, &mic);
if (ret == -EAGAIN)
goto out;
else if (ret < 0)
goto done;
/* Report high impedence cables as line outputs */
if (reading >= 5000)
report = SND_JACK_LINEOUT;
else
report = SND_JACK_HEADPHONE;
snd_soc_jack_report(info->jack, report, SND_JACK_LINEOUT | SND_JACK_HEADPHONE);
done:
/* Reset back to starting range */
regmap_update_bits(arizona->regmap,
ARIZONA_HEADPHONE_DETECT_1,
ARIZONA_HP_IMPEDANCE_RANGE_MASK | ARIZONA_HP_POLL,
0);
arizona_extcon_hp_clamp(info, false);
if (id_gpio)
gpio_set_value_cansleep(id_gpio, 0);
/* If we have a mic then reenable MICDET */
if (state && (mic || info->mic))
arizona_start_mic(info);
if (info->hpdet_active) {
pm_runtime_put_autosuspend(arizona->dev);
info->hpdet_active = false;
}
/* Do not set hp_det done when the cable has been unplugged */
if (state)
info->hpdet_done = true;
out:
mutex_unlock(&info->lock);
return IRQ_HANDLED;
}
static void arizona_identify_headphone(struct arizona_priv *info)
{
struct arizona *arizona = info->arizona;
int ret;
if (info->hpdet_done)
return;
dev_dbg(arizona->dev, "Starting HPDET\n");
/* Make sure we keep the device enabled during the measurement */
pm_runtime_get_sync(arizona->dev);
info->hpdet_active = true;
arizona_stop_mic(info);
arizona_extcon_hp_clamp(info, true);
ret = regmap_update_bits(arizona->regmap,
ARIZONA_ACCESSORY_DETECT_MODE_1,
ARIZONA_ACCDET_MODE_MASK,
arizona->pdata.hpdet_channel);
if (ret != 0) {
dev_err(arizona->dev, "Failed to set HPDET mode: %d\n", ret);
goto err;
}
ret = regmap_update_bits(arizona->regmap, ARIZONA_HEADPHONE_DETECT_1,
ARIZONA_HP_POLL, ARIZONA_HP_POLL);
if (ret) {
dev_err(arizona->dev, "Can't start HPDETL measurement: %d\n", ret);
goto err;
}
return;
err:
arizona_extcon_hp_clamp(info, false);
pm_runtime_put_autosuspend(arizona->dev);
/* Just report headphone */
snd_soc_jack_report(info->jack, SND_JACK_HEADPHONE,
SND_JACK_LINEOUT | SND_JACK_HEADPHONE);
if (info->mic)
arizona_start_mic(info);
info->hpdet_active = false;
}
static void arizona_start_hpdet_acc_id(struct arizona_priv *info)
{
struct arizona *arizona = info->arizona;
int hp_reading = 32;
bool mic;
int ret;
dev_dbg(arizona->dev, "Starting identification via HPDET\n");
/* Make sure we keep the device enabled during the measurement */
pm_runtime_get_sync(arizona->dev);
info->hpdet_active = true;
arizona_extcon_hp_clamp(info, true);
ret = regmap_update_bits(arizona->regmap,
ARIZONA_ACCESSORY_DETECT_MODE_1,
ARIZONA_ACCDET_SRC | ARIZONA_ACCDET_MODE_MASK,
info->micd_modes[0].src |
arizona->pdata.hpdet_channel);
if (ret != 0) {
dev_err(arizona->dev, "Failed to set HPDET mode: %d\n", ret);
goto err;
}
if (arizona->pdata.hpdet_acc_id_line) {
ret = regmap_update_bits(arizona->regmap,
ARIZONA_HEADPHONE_DETECT_1,
ARIZONA_HP_POLL, ARIZONA_HP_POLL);
if (ret) {
dev_err(arizona->dev, "Can't start HPDETL measurement: %d\n", ret);
goto err;
}
} else {
arizona_hpdet_do_id(info, &hp_reading, &mic);
}
return;
err:
/* Just report headphone */
snd_soc_jack_report(info->jack, SND_JACK_HEADPHONE,
SND_JACK_LINEOUT | SND_JACK_HEADPHONE);
info->hpdet_active = false;
}
static void arizona_micd_timeout_work(struct work_struct *work)
{
struct arizona_priv *info = container_of(work,
struct arizona_priv,
micd_timeout_work.work);
mutex_lock(&info->lock);
dev_dbg(info->arizona->dev, "MICD timed out, reporting HP\n");
info->detecting = false;
arizona_identify_headphone(info);
mutex_unlock(&info->lock);
}
static int arizona_micd_adc_read(struct arizona_priv *info)
{
struct arizona *arizona = info->arizona;
unsigned int val;
int ret;
/* Must disable MICD before we read the ADCVAL */
regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1,
ARIZONA_MICD_ENA, 0);
ret = regmap_read(arizona->regmap, ARIZONA_MIC_DETECT_4, &val);
if (ret) {
dev_err(arizona->dev, "Failed to read MICDET_ADCVAL: %d\n", ret);
return ret;
}
dev_dbg(arizona->dev, "MICDET_ADCVAL: %x\n", val);
val &= ARIZONA_MICDET_ADCVAL_MASK;
if (val < ARRAY_SIZE(arizona_micd_levels))
val = arizona_micd_levels[val];
else
val = INT_MAX;
if (val <= QUICK_HEADPHONE_MAX_OHM)
val = ARIZONA_MICD_STS | ARIZONA_MICD_LVL_0;
else if (val <= MICROPHONE_MIN_OHM)
val = ARIZONA_MICD_STS | ARIZONA_MICD_LVL_1;
else if (val <= MICROPHONE_MAX_OHM)
val = ARIZONA_MICD_STS | ARIZONA_MICD_LVL_8;
else
val = ARIZONA_MICD_LVL_8;
return val;
}
static int arizona_micd_read(struct arizona_priv *info)
{
struct arizona *arizona = info->arizona;
unsigned int val = 0;
int ret, i;
for (i = 0; i < 10 && !(val & MICD_LVL_0_TO_8); i++) {
ret = regmap_read(arizona->regmap, ARIZONA_MIC_DETECT_3, &val);
if (ret) {
dev_err(arizona->dev, "Failed to read MICDET: %d\n", ret);
return ret;
}
dev_dbg(arizona->dev, "MICDET: %x\n", val);
if (!(val & ARIZONA_MICD_VALID)) {
dev_warn(arizona->dev, "Microphone detection state invalid\n");
return -EINVAL;
}
}
if (i == 10 && !(val & MICD_LVL_0_TO_8)) {
dev_err(arizona->dev, "Failed to get valid MICDET value\n");
return -EINVAL;
}
return val;
}
static int arizona_micdet_reading(void *priv)
{
struct arizona_priv *info = priv;
struct arizona *arizona = info->arizona;
int ret, val;
if (info->detecting && arizona->pdata.micd_software_compare)
ret = arizona_micd_adc_read(info);
else
ret = arizona_micd_read(info);
if (ret < 0)
return ret;
val = ret;
/* Due to jack detect this should never happen */
if (!(val & ARIZONA_MICD_STS)) {
dev_warn(arizona->dev, "Detected open circuit\n");
info->mic = false;
info->detecting = false;
arizona_identify_headphone(info);
return 0;
}
/* If we got a high impedence we should have a headset, report it. */
if (val & ARIZONA_MICD_LVL_8) {
info->mic = true;
info->detecting = false;
arizona_identify_headphone(info);
snd_soc_jack_report(info->jack, SND_JACK_MICROPHONE, SND_JACK_MICROPHONE);
/* Don't need to regulate for button detection */
ret = regulator_allow_bypass(info->micvdd, true);
if (ret)
dev_err(arizona->dev, "Failed to bypass MICVDD: %d\n", ret);
return 0;
}
/* If we detected a lower impedence during initial startup
* then we probably have the wrong polarity, flip it. Don't
* do this for the lowest impedences to speed up detection of
* plain headphones. If both polarities report a low
* impedence then give up and report headphones.
*/
if (val & MICD_LVL_1_TO_7) {
if (info->jack_flips >= info->micd_num_modes * 10) {
dev_dbg(arizona->dev, "Detected HP/line\n");
info->detecting = false;
arizona_identify_headphone(info);
} else {
info->micd_mode++;
if (info->micd_mode == info->micd_num_modes)
info->micd_mode = 0;
arizona_extcon_set_mode(info, info->micd_mode);
info->jack_flips++;
if (arizona->pdata.micd_software_compare)
regmap_update_bits(arizona->regmap,
ARIZONA_MIC_DETECT_1,
ARIZONA_MICD_ENA,
ARIZONA_MICD_ENA);
queue_delayed_work(system_power_efficient_wq,
&info->micd_timeout_work,
msecs_to_jiffies(arizona->pdata.micd_timeout));
}
return 0;
}
/*
* If we're still detecting and we detect a short then we've
* got a headphone.
*/
dev_dbg(arizona->dev, "Headphone detected\n");
info->detecting = false;
arizona_identify_headphone(info);
return 0;
}
static int arizona_button_reading(void *priv)
{
struct arizona_priv *info = priv;
struct arizona *arizona = info->arizona;
int val, key, lvl;
val = arizona_micd_read(info);
if (val < 0)
return val;
/*
* If we're still detecting and we detect a short then we've
* got a headphone. Otherwise it's a button press.
*/
if (val & MICD_LVL_0_TO_7) {
if (info->mic) {
dev_dbg(arizona->dev, "Mic button detected\n");
lvl = val & ARIZONA_MICD_LVL_MASK;
lvl >>= ARIZONA_MICD_LVL_SHIFT;
if (lvl && ffs(lvl) - 1 < info->num_micd_ranges) {
key = ffs(lvl) - 1;
snd_soc_jack_report(info->jack,
SND_JACK_BTN_0 >> key,
info->micd_button_mask);
} else {
dev_err(arizona->dev, "Button out of range\n");
}
} else {
dev_warn(arizona->dev, "Button with no mic: %x\n", val);
}
} else {
dev_dbg(arizona->dev, "Mic button released\n");
snd_soc_jack_report(info->jack, 0, info->micd_button_mask);
arizona_extcon_pulse_micbias(info);
}
return 0;
}
static void arizona_micd_detect(struct work_struct *work)
{
struct arizona_priv *info = container_of(work,
struct arizona_priv,
micd_detect_work.work);
struct arizona *arizona = info->arizona;
cancel_delayed_work_sync(&info->micd_timeout_work);
mutex_lock(&info->lock);
/* If the cable was removed while measuring ignore the result */
if (!(info->jack->status & SND_JACK_MECHANICAL)) {
dev_dbg(arizona->dev, "Ignoring MICDET for removed cable\n");
mutex_unlock(&info->lock);
return;
}
if (info->detecting)
arizona_micdet_reading(info);
else
arizona_button_reading(info);
pm_runtime_mark_last_busy(arizona->dev);
mutex_unlock(&info->lock);
}
static irqreturn_t arizona_micdet(int irq, void *data)
{
struct arizona_priv *info = data;
struct arizona *arizona = info->arizona;
int debounce = arizona->pdata.micd_detect_debounce;
cancel_delayed_work_sync(&info->micd_detect_work);
cancel_delayed_work_sync(&info->micd_timeout_work);
mutex_lock(&info->lock);
if (!info->detecting)
debounce = 0;
mutex_unlock(&info->lock);
if (debounce)
queue_delayed_work(system_power_efficient_wq,
&info->micd_detect_work,
msecs_to_jiffies(debounce));
else
arizona_micd_detect(&info->micd_detect_work.work);
return IRQ_HANDLED;
}
static void arizona_hpdet_work(struct work_struct *work)
{
struct arizona_priv *info = container_of(work,
struct arizona_priv,
hpdet_work.work);
mutex_lock(&info->lock);
arizona_start_hpdet_acc_id(info);
mutex_unlock(&info->lock);
}
static int arizona_hpdet_wait(struct arizona_priv *info)
{
struct arizona *arizona = info->arizona;
unsigned int val;
int i, ret;
for (i = 0; i < ARIZONA_HPDET_WAIT_COUNT; i++) {
ret = regmap_read(arizona->regmap, ARIZONA_HEADPHONE_DETECT_2,
&val);
if (ret) {
dev_err(arizona->dev, "Failed to read HPDET state: %d\n", ret);
return ret;
}
switch (info->hpdet_ip_version) {
case 0:
if (val & ARIZONA_HP_DONE)
return 0;
break;
default:
if (val & ARIZONA_HP_DONE_B)
return 0;
break;
}
msleep(ARIZONA_HPDET_WAIT_DELAY_MS);
}
dev_warn(arizona->dev, "HPDET did not appear to complete\n");
return -ETIMEDOUT;
}
static irqreturn_t arizona_jackdet(int irq, void *data)
{
struct arizona_priv *info = data;
struct arizona *arizona = info->arizona;
unsigned int val, present, mask;
bool cancelled_hp, cancelled_mic;
int ret, i;
cancelled_hp = cancel_delayed_work_sync(&info->hpdet_work);
cancelled_mic = cancel_delayed_work_sync(&info->micd_timeout_work);
pm_runtime_get_sync(arizona->dev);
mutex_lock(&info->lock);
if (info->micd_clamp) {
mask = ARIZONA_MICD_CLAMP_STS;
present = 0;
} else {
mask = ARIZONA_JD1_STS;
if (arizona->pdata.jd_invert)
present = 0;
else
present = ARIZONA_JD1_STS;
}
ret = regmap_read(arizona->regmap, ARIZONA_AOD_IRQ_RAW_STATUS, &val);
if (ret) {
dev_err(arizona->dev, "Failed to read jackdet status: %d\n", ret);
mutex_unlock(&info->lock);
pm_runtime_put_autosuspend(arizona->dev);
return IRQ_NONE;
}
val &= mask;
if (val == info->last_jackdet) {
dev_dbg(arizona->dev, "Suppressing duplicate JACKDET\n");
if (cancelled_hp)
queue_delayed_work(system_power_efficient_wq,
&info->hpdet_work,
msecs_to_jiffies(HPDET_DEBOUNCE));
if (cancelled_mic) {
int micd_timeout = arizona->pdata.micd_timeout;
queue_delayed_work(system_power_efficient_wq,
&info->micd_timeout_work,
msecs_to_jiffies(micd_timeout));
}
goto out;
}
info->last_jackdet = val;
if (info->last_jackdet == present) {
dev_dbg(arizona->dev, "Detected jack\n");
snd_soc_jack_report(info->jack, SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
info->detecting = true;
info->mic = false;
info->jack_flips = 0;
if (!arizona->pdata.hpdet_acc_id) {
arizona_start_mic(info);
} else {
queue_delayed_work(system_power_efficient_wq,
&info->hpdet_work,
msecs_to_jiffies(HPDET_DEBOUNCE));
}
if (info->micd_clamp || !arizona->pdata.jd_invert)
regmap_update_bits(arizona->regmap,
ARIZONA_JACK_DETECT_DEBOUNCE,
ARIZONA_MICD_CLAMP_DB |
ARIZONA_JD1_DB, 0);
} else {
dev_dbg(arizona->dev, "Detected jack removal\n");
arizona_stop_mic(info);
info->num_hpdet_res = 0;
for (i = 0; i < ARRAY_SIZE(info->hpdet_res); i++)
info->hpdet_res[i] = 0;
info->mic = false;
info->hpdet_done = false;
info->hpdet_retried = false;
snd_soc_jack_report(info->jack, 0, ARIZONA_JACK_MASK | info->micd_button_mask);
/*
* If the jack was removed during a headphone detection we
* need to wait for the headphone detection to finish, as
* it can not be aborted. We don't want to be able to start
* a new headphone detection from a fresh insert until this
* one is finished.
*/
arizona_hpdet_wait(info);
regmap_update_bits(arizona->regmap,
ARIZONA_JACK_DETECT_DEBOUNCE,
ARIZONA_MICD_CLAMP_DB | ARIZONA_JD1_DB,
ARIZONA_MICD_CLAMP_DB | ARIZONA_JD1_DB);
}
out:
/* Clear trig_sts to make sure DCVDD is not forced up */
regmap_write(arizona->regmap, ARIZONA_AOD_WKUP_AND_TRIG,
ARIZONA_MICD_CLAMP_FALL_TRIG_STS |
ARIZONA_MICD_CLAMP_RISE_TRIG_STS |
ARIZONA_JD1_FALL_TRIG_STS |
ARIZONA_JD1_RISE_TRIG_STS);
mutex_unlock(&info->lock);
pm_runtime_mark_last_busy(arizona->dev);
pm_runtime_put_autosuspend(arizona->dev);
return IRQ_HANDLED;
}
/* Map a level onto a slot in the register bank */
static void arizona_micd_set_level(struct arizona *arizona, int index,
unsigned int level)
{
int reg;
unsigned int mask;
reg = ARIZONA_MIC_DETECT_LEVEL_4 - (index / 2);
if (!(index % 2)) {
mask = 0x3f00;
level <<= 8;
} else {
mask = 0x3f;
}
/* Program the level itself */
regmap_update_bits(arizona->regmap, reg, mask, level);
}
static int arizona_extcon_get_micd_configs(struct device *dev,
struct arizona *arizona)
{
const char * const prop = "wlf,micd-configs";
const int entries_per_config = 3;
struct arizona_micd_config *micd_configs;
int nconfs, ret;
int i, j;
u32 *vals;
nconfs = device_property_count_u32(arizona->dev, prop);
if (nconfs <= 0)
return 0;
vals = kcalloc(nconfs, sizeof(u32), GFP_KERNEL);
if (!vals)
return -ENOMEM;
ret = device_property_read_u32_array(arizona->dev, prop, vals, nconfs);
if (ret < 0)
goto out;
nconfs /= entries_per_config;
micd_configs = devm_kcalloc(dev, nconfs, sizeof(*micd_configs),
GFP_KERNEL);
if (!micd_configs) {
ret = -ENOMEM;
goto out;
}
for (i = 0, j = 0; i < nconfs; ++i) {
micd_configs[i].src = vals[j++] ? ARIZONA_ACCDET_SRC : 0;
micd_configs[i].bias = vals[j++];
micd_configs[i].gpio = vals[j++];
}
arizona->pdata.micd_configs = micd_configs;
arizona->pdata.num_micd_configs = nconfs;
out:
kfree(vals);
return ret;
}
static int arizona_extcon_device_get_pdata(struct device *dev,
struct arizona *arizona)
{
struct arizona_pdata *pdata = &arizona->pdata;
unsigned int val = ARIZONA_ACCDET_MODE_HPL;
int ret;
device_property_read_u32(arizona->dev, "wlf,hpdet-channel", &val);
switch (val) {
case ARIZONA_ACCDET_MODE_HPL:
case ARIZONA_ACCDET_MODE_HPR:
pdata->hpdet_channel = val;
break;
default:
dev_err(arizona->dev, "Wrong wlf,hpdet-channel DT value %d\n", val);
pdata->hpdet_channel = ARIZONA_ACCDET_MODE_HPL;
}
device_property_read_u32(arizona->dev, "wlf,micd-detect-debounce",
&pdata->micd_detect_debounce);
device_property_read_u32(arizona->dev, "wlf,micd-bias-start-time",
&pdata->micd_bias_start_time);
device_property_read_u32(arizona->dev, "wlf,micd-rate",
&pdata->micd_rate);
device_property_read_u32(arizona->dev, "wlf,micd-dbtime",
&pdata->micd_dbtime);
device_property_read_u32(arizona->dev, "wlf,micd-timeout-ms",
&pdata->micd_timeout);
pdata->micd_force_micbias = device_property_read_bool(arizona->dev,
"wlf,micd-force-micbias");
pdata->micd_software_compare = device_property_read_bool(arizona->dev,
"wlf,micd-software-compare");
pdata->jd_invert = device_property_read_bool(arizona->dev,
"wlf,jd-invert");
device_property_read_u32(arizona->dev, "wlf,gpsw", &pdata->gpsw);
pdata->jd_gpio5 = device_property_read_bool(arizona->dev,
"wlf,use-jd2");
pdata->jd_gpio5_nopull = device_property_read_bool(arizona->dev,
"wlf,use-jd2-nopull");
ret = arizona_extcon_get_micd_configs(dev, arizona);
if (ret < 0)
dev_err(arizona->dev, "Failed to read micd configs: %d\n", ret);
return 0;
}
int arizona_jack_codec_dev_probe(struct arizona_priv *info, struct device *dev)
{
struct arizona *arizona = info->arizona;
struct arizona_pdata *pdata = &arizona->pdata;
int ret, mode;
if (!dev_get_platdata(arizona->dev))
arizona_extcon_device_get_pdata(dev, arizona);
info->micvdd = devm_regulator_get(dev, "MICVDD");
if (IS_ERR(info->micvdd))
return dev_err_probe(arizona->dev, PTR_ERR(info->micvdd), "getting MICVDD\n");
mutex_init(&info->lock);
info->last_jackdet = ~(ARIZONA_MICD_CLAMP_STS | ARIZONA_JD1_STS);
INIT_DELAYED_WORK(&info->hpdet_work, arizona_hpdet_work);
INIT_DELAYED_WORK(&info->micd_detect_work, arizona_micd_detect);
INIT_DELAYED_WORK(&info->micd_timeout_work, arizona_micd_timeout_work);
switch (arizona->type) {
case WM5102:
switch (arizona->rev) {
case 0:
info->micd_reva = true;
break;
default:
info->micd_clamp = true;
info->hpdet_ip_version = 1;
break;
}
break;
case WM5110:
case WM8280:
switch (arizona->rev) {
case 0 ... 2:
break;
default:
info->micd_clamp = true;
info->hpdet_ip_version = 2;
break;
}
break;
case WM8998:
case WM1814:
info->micd_clamp = true;
info->hpdet_ip_version = 2;
break;
default:
break;
}
if (!pdata->micd_timeout)
pdata->micd_timeout = DEFAULT_MICD_TIMEOUT;
if (pdata->num_micd_configs) {
info->micd_modes = pdata->micd_configs;
info->micd_num_modes = pdata->num_micd_configs;
} else {
info->micd_modes = micd_default_modes;
info->micd_num_modes = ARRAY_SIZE(micd_default_modes);
}
if (arizona->pdata.gpsw > 0)
regmap_update_bits(arizona->regmap, ARIZONA_GP_SWITCH_1,
ARIZONA_SW1_MODE_MASK, arizona->pdata.gpsw);
if (pdata->micd_pol_gpio > 0) {
if (info->micd_modes[0].gpio)
mode = GPIOF_OUT_INIT_HIGH;
else
mode = GPIOF_OUT_INIT_LOW;
ret = devm_gpio_request_one(dev, pdata->micd_pol_gpio,
mode, "MICD polarity");
if (ret != 0) {
dev_err(arizona->dev, "Failed to request GPIO%d: %d\n",
pdata->micd_pol_gpio, ret);
return ret;
}
info->micd_pol_gpio = gpio_to_desc(pdata->micd_pol_gpio);
} else {
if (info->micd_modes[0].gpio)
mode = GPIOD_OUT_HIGH;
else
mode = GPIOD_OUT_LOW;
/* We can't use devm here because we need to do the get
* against the MFD device, as that is where the of_node
* will reside, but if we devm against that the GPIO
* will not be freed if the extcon driver is unloaded.
*/
info->micd_pol_gpio = gpiod_get_optional(arizona->dev,
"wlf,micd-pol",
mode);
if (IS_ERR(info->micd_pol_gpio)) {
ret = PTR_ERR(info->micd_pol_gpio);
dev_err_probe(arizona->dev, ret, "getting microphone polarity GPIO\n");
return ret;
}
}
if (arizona->pdata.hpdet_id_gpio > 0) {
ret = devm_gpio_request_one(dev, arizona->pdata.hpdet_id_gpio,
GPIOF_OUT_INIT_LOW,
"HPDET");
if (ret != 0) {
dev_err(arizona->dev, "Failed to request GPIO%d: %d\n",
arizona->pdata.hpdet_id_gpio, ret);
gpiod_put(info->micd_pol_gpio);
return ret;
}
}
return 0;
}
EXPORT_SYMBOL_GPL(arizona_jack_codec_dev_probe);
int arizona_jack_codec_dev_remove(struct arizona_priv *info)
{
gpiod_put(info->micd_pol_gpio);
return 0;
}
EXPORT_SYMBOL_GPL(arizona_jack_codec_dev_remove);
static int arizona_jack_enable_jack_detect(struct arizona_priv *info,
struct snd_soc_jack *jack)
{
struct arizona *arizona = info->arizona;
struct arizona_pdata *pdata = &arizona->pdata;
unsigned int val;
unsigned int clamp_mode;
int jack_irq_fall, jack_irq_rise;
int ret, i, j;
if (arizona->pdata.micd_bias_start_time)
regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1,
ARIZONA_MICD_BIAS_STARTTIME_MASK,
arizona->pdata.micd_bias_start_time
<< ARIZONA_MICD_BIAS_STARTTIME_SHIFT);
if (arizona->pdata.micd_rate)
regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1,
ARIZONA_MICD_RATE_MASK,
arizona->pdata.micd_rate
<< ARIZONA_MICD_RATE_SHIFT);
switch (arizona->pdata.micd_dbtime) {
case MICD_DBTIME_FOUR_READINGS:
regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1,
ARIZONA_MICD_DBTIME_MASK,
ARIZONA_MICD_DBTIME);
break;
case MICD_DBTIME_TWO_READINGS:
regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1,
ARIZONA_MICD_DBTIME_MASK, 0);
break;
default:
break;
}
BUILD_BUG_ON(ARRAY_SIZE(arizona_micd_levels) <
ARIZONA_NUM_MICD_BUTTON_LEVELS);
if (arizona->pdata.num_micd_ranges) {
info->micd_ranges = pdata->micd_ranges;
info->num_micd_ranges = pdata->num_micd_ranges;
} else {
info->micd_ranges = micd_default_ranges;
info->num_micd_ranges = ARRAY_SIZE(micd_default_ranges);
}
if (arizona->pdata.num_micd_ranges > ARIZONA_MAX_MICD_BUTTONS) {
dev_err(arizona->dev, "Too many MICD ranges: %d > %d\n",
arizona->pdata.num_micd_ranges, ARIZONA_MAX_MICD_BUTTONS);
return -EINVAL;
}
if (info->num_micd_ranges > 1) {
for (i = 1; i < info->num_micd_ranges; i++) {
if (info->micd_ranges[i - 1].max >
info->micd_ranges[i].max) {
dev_err(arizona->dev, "MICD ranges must be sorted\n");
return -EINVAL;
}
}
}
/* Disable all buttons by default */
regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_2,
ARIZONA_MICD_LVL_SEL_MASK, 0x81);
/* Set up all the buttons the user specified */
for (i = 0; i < info->num_micd_ranges; i++) {
for (j = 0; j < ARIZONA_NUM_MICD_BUTTON_LEVELS; j++)
if (arizona_micd_levels[j] >= info->micd_ranges[i].max)
break;
if (j == ARIZONA_NUM_MICD_BUTTON_LEVELS) {
dev_err(arizona->dev, "Unsupported MICD level %d\n",
info->micd_ranges[i].max);
return -EINVAL;
}
dev_dbg(arizona->dev, "%d ohms for MICD threshold %d\n",
arizona_micd_levels[j], i);
arizona_micd_set_level(arizona, i, j);
/* SND_JACK_BTN_# masks start with the most significant bit */
info->micd_button_mask |= SND_JACK_BTN_0 >> i;
snd_jack_set_key(jack->jack, SND_JACK_BTN_0 >> i,
info->micd_ranges[i].key);
/* Enable reporting of that range */
regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_2,
1 << i, 1 << i);
}
/* Set all the remaining keys to a maximum */
for (; i < ARIZONA_MAX_MICD_RANGE; i++)
arizona_micd_set_level(arizona, i, 0x3f);
/*
* If we have a clamp use it, activating in conjunction with
* GPIO5 if that is connected for jack detect operation.
*/
if (info->micd_clamp) {
if (arizona->pdata.jd_gpio5) {
/* Put the GPIO into input mode with optional pull */
val = 0xc101;
if (arizona->pdata.jd_gpio5_nopull)
val &= ~ARIZONA_GPN_PU;
regmap_write(arizona->regmap, ARIZONA_GPIO5_CTRL,
val);
if (arizona->pdata.jd_invert)
clamp_mode = ARIZONA_MICD_CLAMP_MODE_JDH_GP5H;
else
clamp_mode = ARIZONA_MICD_CLAMP_MODE_JDL_GP5H;
} else {
if (arizona->pdata.jd_invert)
clamp_mode = ARIZONA_MICD_CLAMP_MODE_JDH;
else
clamp_mode = ARIZONA_MICD_CLAMP_MODE_JDL;
}
regmap_update_bits(arizona->regmap,
ARIZONA_MICD_CLAMP_CONTROL,
ARIZONA_MICD_CLAMP_MODE_MASK, clamp_mode);
regmap_update_bits(arizona->regmap,
ARIZONA_JACK_DETECT_DEBOUNCE,
ARIZONA_MICD_CLAMP_DB,
ARIZONA_MICD_CLAMP_DB);
}
arizona_extcon_set_mode(info, 0);
info->jack = jack;
pm_runtime_get_sync(arizona->dev);
if (info->micd_clamp) {
jack_irq_rise = ARIZONA_IRQ_MICD_CLAMP_RISE;
jack_irq_fall = ARIZONA_IRQ_MICD_CLAMP_FALL;
} else {
jack_irq_rise = ARIZONA_IRQ_JD_RISE;
jack_irq_fall = ARIZONA_IRQ_JD_FALL;
}
ret = arizona_request_irq(arizona, jack_irq_rise,
"JACKDET rise", arizona_jackdet, info);
if (ret != 0) {
dev_err(arizona->dev, "Failed to get JACKDET rise IRQ: %d\n", ret);
goto err_pm;
}
ret = arizona_set_irq_wake(arizona, jack_irq_rise, 1);
if (ret != 0) {
dev_err(arizona->dev, "Failed to set JD rise IRQ wake: %d\n", ret);
goto err_rise;
}
ret = arizona_request_irq(arizona, jack_irq_fall,
"JACKDET fall", arizona_jackdet, info);
if (ret != 0) {
dev_err(arizona->dev, "Failed to get JD fall IRQ: %d\n", ret);
goto err_rise_wake;
}
ret = arizona_set_irq_wake(arizona, jack_irq_fall, 1);
if (ret != 0) {
dev_err(arizona->dev, "Failed to set JD fall IRQ wake: %d\n", ret);
goto err_fall;
}
ret = arizona_request_irq(arizona, ARIZONA_IRQ_MICDET,
"MICDET", arizona_micdet, info);
if (ret != 0) {
dev_err(arizona->dev, "Failed to get MICDET IRQ: %d\n", ret);
goto err_fall_wake;
}
ret = arizona_request_irq(arizona, ARIZONA_IRQ_HPDET,
"HPDET", arizona_hpdet_irq, info);
if (ret != 0) {
dev_err(arizona->dev, "Failed to get HPDET IRQ: %d\n", ret);
goto err_micdet;
}
arizona_clk32k_enable(arizona);
regmap_update_bits(arizona->regmap, ARIZONA_JACK_DETECT_DEBOUNCE,
ARIZONA_JD1_DB, ARIZONA_JD1_DB);
regmap_update_bits(arizona->regmap, ARIZONA_JACK_DETECT_ANALOGUE,
ARIZONA_JD1_ENA, ARIZONA_JD1_ENA);
ret = regulator_allow_bypass(info->micvdd, true);
if (ret != 0)
dev_warn(arizona->dev, "Failed to set MICVDD to bypass: %d\n", ret);
pm_runtime_put(arizona->dev);
return 0;
err_micdet:
arizona_free_irq(arizona, ARIZONA_IRQ_MICDET, info);
err_fall_wake:
arizona_set_irq_wake(arizona, jack_irq_fall, 0);
err_fall:
arizona_free_irq(arizona, jack_irq_fall, info);
err_rise_wake:
arizona_set_irq_wake(arizona, jack_irq_rise, 0);
err_rise:
arizona_free_irq(arizona, jack_irq_rise, info);
err_pm:
pm_runtime_put(arizona->dev);
info->jack = NULL;
return ret;
}
static int arizona_jack_disable_jack_detect(struct arizona_priv *info)
{
struct arizona *arizona = info->arizona;
int jack_irq_rise, jack_irq_fall;
bool change;
int ret;
if (!info->jack)
return 0;
if (info->micd_clamp) {
jack_irq_rise = ARIZONA_IRQ_MICD_CLAMP_RISE;
jack_irq_fall = ARIZONA_IRQ_MICD_CLAMP_FALL;
} else {
jack_irq_rise = ARIZONA_IRQ_JD_RISE;
jack_irq_fall = ARIZONA_IRQ_JD_FALL;
}
arizona_set_irq_wake(arizona, jack_irq_rise, 0);
arizona_set_irq_wake(arizona, jack_irq_fall, 0);
arizona_free_irq(arizona, ARIZONA_IRQ_HPDET, info);
arizona_free_irq(arizona, ARIZONA_IRQ_MICDET, info);
arizona_free_irq(arizona, jack_irq_rise, info);
arizona_free_irq(arizona, jack_irq_fall, info);
cancel_delayed_work_sync(&info->hpdet_work);
cancel_delayed_work_sync(&info->micd_detect_work);
cancel_delayed_work_sync(&info->micd_timeout_work);
ret = regmap_update_bits_check(arizona->regmap, ARIZONA_MIC_DETECT_1,
ARIZONA_MICD_ENA, 0,
&change);
if (ret < 0) {
dev_err(arizona->dev, "Failed to disable micd on remove: %d\n", ret);
} else if (change) {
regulator_disable(info->micvdd);
pm_runtime_put(arizona->dev);
}
regmap_update_bits(arizona->regmap,
ARIZONA_MICD_CLAMP_CONTROL,
ARIZONA_MICD_CLAMP_MODE_MASK, 0);
regmap_update_bits(arizona->regmap, ARIZONA_JACK_DETECT_ANALOGUE,
ARIZONA_JD1_ENA, 0);
arizona_clk32k_disable(arizona);
info->jack = NULL;
return 0;
}
int arizona_jack_set_jack(struct snd_soc_component *component,
struct snd_soc_jack *jack, void *data)
{
struct arizona_priv *info = snd_soc_component_get_drvdata(component);
if (jack)
return arizona_jack_enable_jack_detect(info, jack);
else
return arizona_jack_disable_jack_detect(info);
}
EXPORT_SYMBOL_GPL(arizona_jack_set_jack);
| linux-master | sound/soc/codecs/arizona-jack.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* rl6347a.c - RL6347A class device shared support
*
* Copyright 2015 Realtek Semiconductor Corp.
*
* Author: Oder Chiou <[email protected]>
*/
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include "rl6347a.h"
int rl6347a_hw_write(void *context, unsigned int reg, unsigned int value)
{
struct i2c_client *client = context;
struct rl6347a_priv *rl6347a = i2c_get_clientdata(client);
u8 data[4];
int ret, i;
/* handle index registers */
if (reg <= 0xff) {
rl6347a_hw_write(client, RL6347A_COEF_INDEX, reg);
for (i = 0; i < rl6347a->index_cache_size; i++) {
if (reg == rl6347a->index_cache[i].reg) {
rl6347a->index_cache[i].def = value;
break;
}
}
reg = RL6347A_PROC_COEF;
}
data[0] = (reg >> 24) & 0xff;
data[1] = (reg >> 16) & 0xff;
/*
* 4 bit VID: reg should be 0
* 12 bit VID: value should be 0
* So we use an OR operator to handle it rather than use if condition.
*/
data[2] = ((reg >> 8) & 0xff) | ((value >> 8) & 0xff);
data[3] = value & 0xff;
ret = i2c_master_send(client, data, 4);
if (ret == 4)
return 0;
else
dev_err(&client->dev, "I2C error %d\n", ret);
if (ret < 0)
return ret;
else
return -EIO;
}
EXPORT_SYMBOL_GPL(rl6347a_hw_write);
int rl6347a_hw_read(void *context, unsigned int reg, unsigned int *value)
{
struct i2c_client *client = context;
struct i2c_msg xfer[2];
int ret;
__be32 be_reg, buf = 0x0;
unsigned int index, vid;
/* handle index registers */
if (reg <= 0xff) {
rl6347a_hw_write(client, RL6347A_COEF_INDEX, reg);
reg = RL6347A_PROC_COEF;
}
reg = reg | 0x80000;
vid = (reg >> 8) & 0xfff;
if (AC_VERB_GET_AMP_GAIN_MUTE == (vid & 0xf00)) {
index = (reg >> 8) & 0xf;
reg = (reg & ~0xf0f) | index;
}
be_reg = cpu_to_be32(reg);
/* Write register */
xfer[0].addr = client->addr;
xfer[0].flags = 0;
xfer[0].len = 4;
xfer[0].buf = (u8 *)&be_reg;
/* Read data */
xfer[1].addr = client->addr;
xfer[1].flags = I2C_M_RD;
xfer[1].len = 4;
xfer[1].buf = (u8 *)&buf;
ret = i2c_transfer(client->adapter, xfer, 2);
if (ret < 0)
return ret;
else if (ret != 2)
return -EIO;
*value = be32_to_cpu(buf);
return 0;
}
EXPORT_SYMBOL_GPL(rl6347a_hw_read);
MODULE_DESCRIPTION("RL6347A class device shared support");
MODULE_AUTHOR("Oder Chiou <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/rl6347a.c |
// SPDX-License-Identifier: GPL-2.0
//
// PCM3060 I2C driver
//
// Copyright (C) 2018 Kirill Marinushkin <[email protected]>
#include <linux/i2c.h>
#include <linux/module.h>
#include <sound/soc.h>
#include "pcm3060.h"
static int pcm3060_i2c_probe(struct i2c_client *i2c)
{
struct pcm3060_priv *priv;
priv = devm_kzalloc(&i2c->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
i2c_set_clientdata(i2c, priv);
priv->regmap = devm_regmap_init_i2c(i2c, &pcm3060_regmap);
if (IS_ERR(priv->regmap))
return PTR_ERR(priv->regmap);
return pcm3060_probe(&i2c->dev);
}
static const struct i2c_device_id pcm3060_i2c_id[] = {
{ .name = "pcm3060" },
{ },
};
MODULE_DEVICE_TABLE(i2c, pcm3060_i2c_id);
#ifdef CONFIG_OF
static const struct of_device_id pcm3060_of_match[] = {
{ .compatible = "ti,pcm3060" },
{ },
};
MODULE_DEVICE_TABLE(of, pcm3060_of_match);
#endif /* CONFIG_OF */
static struct i2c_driver pcm3060_i2c_driver = {
.driver = {
.name = "pcm3060",
#ifdef CONFIG_OF
.of_match_table = pcm3060_of_match,
#endif /* CONFIG_OF */
},
.id_table = pcm3060_i2c_id,
.probe = pcm3060_i2c_probe,
};
module_i2c_driver(pcm3060_i2c_driver);
MODULE_DESCRIPTION("PCM3060 I2C driver");
MODULE_AUTHOR("Kirill Marinushkin <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/pcm3060-i2c.c |
// SPDX-License-Identifier: GPL-2.0
//
// Audio driver for AK4458 DAC
//
// Copyright (C) 2016 Asahi Kasei Microdevices Corporation
// Copyright 2018 NXP
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include <linux/slab.h>
#include <sound/initval.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/tlv.h>
#include "ak4458.h"
#define AK4458_NUM_SUPPLIES 2
static const char *ak4458_supply_names[AK4458_NUM_SUPPLIES] = {
"DVDD",
"AVDD",
};
enum ak4458_type {
AK4458 = 0,
AK4497 = 1,
};
struct ak4458_drvdata {
struct snd_soc_dai_driver *dai_drv;
const struct snd_soc_component_driver *comp_drv;
enum ak4458_type type;
};
/* AK4458 Codec Private Data */
struct ak4458_priv {
struct regulator_bulk_data supplies[AK4458_NUM_SUPPLIES];
const struct ak4458_drvdata *drvdata;
struct device *dev;
struct regmap *regmap;
struct gpio_desc *reset_gpiod;
struct reset_control *reset;
struct gpio_desc *mute_gpiod;
int digfil; /* SSLOW, SD, SLOW bits */
int fs; /* sampling rate */
int fmt;
int slots;
int slot_width;
u32 dsd_path; /* For ak4497 */
};
static const struct reg_default ak4458_reg_defaults[] = {
{ 0x00, 0x0C }, /* 0x00 AK4458_00_CONTROL1 */
{ 0x01, 0x22 }, /* 0x01 AK4458_01_CONTROL2 */
{ 0x02, 0x00 }, /* 0x02 AK4458_02_CONTROL3 */
{ 0x03, 0xFF }, /* 0x03 AK4458_03_LCHATT */
{ 0x04, 0xFF }, /* 0x04 AK4458_04_RCHATT */
{ 0x05, 0x00 }, /* 0x05 AK4458_05_CONTROL4 */
{ 0x06, 0x00 }, /* 0x06 AK4458_06_DSD1 */
{ 0x07, 0x03 }, /* 0x07 AK4458_07_CONTROL5 */
{ 0x08, 0x00 }, /* 0x08 AK4458_08_SOUND_CONTROL */
{ 0x09, 0x00 }, /* 0x09 AK4458_09_DSD2 */
{ 0x0A, 0x0D }, /* 0x0A AK4458_0A_CONTROL6 */
{ 0x0B, 0x0C }, /* 0x0B AK4458_0B_CONTROL7 */
{ 0x0C, 0x00 }, /* 0x0C AK4458_0C_CONTROL8 */
{ 0x0D, 0x00 }, /* 0x0D AK4458_0D_CONTROL9 */
{ 0x0E, 0x50 }, /* 0x0E AK4458_0E_CONTROL10 */
{ 0x0F, 0xFF }, /* 0x0F AK4458_0F_L2CHATT */
{ 0x10, 0xFF }, /* 0x10 AK4458_10_R2CHATT */
{ 0x11, 0xFF }, /* 0x11 AK4458_11_L3CHATT */
{ 0x12, 0xFF }, /* 0x12 AK4458_12_R3CHATT */
{ 0x13, 0xFF }, /* 0x13 AK4458_13_L4CHATT */
{ 0x14, 0xFF }, /* 0x14 AK4458_14_R4CHATT */
};
/*
* Volume control:
* from -127 to 0 dB in 0.5 dB steps (mute instead of -127.5 dB)
*/
static DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
/*
* DEM1 bit DEM0 bit Mode
* 0 0 44.1kHz
* 0 1 OFF (default)
* 1 0 48kHz
* 1 1 32kHz
*/
static const char * const ak4458_dem_select_texts[] = {
"44.1kHz", "OFF", "48kHz", "32kHz"
};
/*
* SSLOW, SD, SLOW bits Digital Filter Setting
* 0, 0, 0 : Sharp Roll-Off Filter
* 0, 0, 1 : Slow Roll-Off Filter
* 0, 1, 0 : Short delay Sharp Roll-Off Filter
* 0, 1, 1 : Short delay Slow Roll-Off Filter
* 1, *, * : Super Slow Roll-Off Filter
*/
static const char * const ak4458_digfil_select_texts[] = {
"Sharp Roll-Off Filter",
"Slow Roll-Off Filter",
"Short delay Sharp Roll-Off Filter",
"Short delay Slow Roll-Off Filter",
"Super Slow Roll-Off Filter"
};
/*
* DZFB: Inverting Enable of DZF
* 0: DZF goes H at Zero Detection
* 1: DZF goes L at Zero Detection
*/
static const char * const ak4458_dzfb_select_texts[] = {"H", "L"};
/*
* SC1-0 bits: Sound Mode Setting
* 0 0 : Sound Mode 0
* 0 1 : Sound Mode 1
* 1 0 : Sound Mode 2
* 1 1 : Reserved
*/
static const char * const ak4458_sc_select_texts[] = {
"Sound Mode 0", "Sound Mode 1", "Sound Mode 2"
};
/* FIR2-0 bits: FIR Filter Mode Setting */
static const char * const ak4458_fir_select_texts[] = {
"Mode 0", "Mode 1", "Mode 2", "Mode 3",
"Mode 4", "Mode 5", "Mode 6", "Mode 7",
};
/* ATS1-0 bits Attenuation Speed */
static const char * const ak4458_ats_select_texts[] = {
"4080/fs", "2040/fs", "510/fs", "255/fs",
};
/* DIF2 bit Audio Interface Format Setting(BICK fs) */
static const char * const ak4458_dif_select_texts[] = {"32fs,48fs", "64fs",};
static const struct soc_enum ak4458_dac1_dem_enum =
SOC_ENUM_SINGLE(AK4458_01_CONTROL2, 1,
ARRAY_SIZE(ak4458_dem_select_texts),
ak4458_dem_select_texts);
static const struct soc_enum ak4458_dac2_dem_enum =
SOC_ENUM_SINGLE(AK4458_0A_CONTROL6, 0,
ARRAY_SIZE(ak4458_dem_select_texts),
ak4458_dem_select_texts);
static const struct soc_enum ak4458_dac3_dem_enum =
SOC_ENUM_SINGLE(AK4458_0E_CONTROL10, 4,
ARRAY_SIZE(ak4458_dem_select_texts),
ak4458_dem_select_texts);
static const struct soc_enum ak4458_dac4_dem_enum =
SOC_ENUM_SINGLE(AK4458_0E_CONTROL10, 6,
ARRAY_SIZE(ak4458_dem_select_texts),
ak4458_dem_select_texts);
static const struct soc_enum ak4458_digfil_enum =
SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(ak4458_digfil_select_texts),
ak4458_digfil_select_texts);
static const struct soc_enum ak4458_dzfb_enum =
SOC_ENUM_SINGLE(AK4458_02_CONTROL3, 2,
ARRAY_SIZE(ak4458_dzfb_select_texts),
ak4458_dzfb_select_texts);
static const struct soc_enum ak4458_sm_enum =
SOC_ENUM_SINGLE(AK4458_08_SOUND_CONTROL, 0,
ARRAY_SIZE(ak4458_sc_select_texts),
ak4458_sc_select_texts);
static const struct soc_enum ak4458_fir_enum =
SOC_ENUM_SINGLE(AK4458_0C_CONTROL8, 0,
ARRAY_SIZE(ak4458_fir_select_texts),
ak4458_fir_select_texts);
static const struct soc_enum ak4458_ats_enum =
SOC_ENUM_SINGLE(AK4458_0B_CONTROL7, 6,
ARRAY_SIZE(ak4458_ats_select_texts),
ak4458_ats_select_texts);
static const struct soc_enum ak4458_dif_enum =
SOC_ENUM_SINGLE(AK4458_00_CONTROL1, 3,
ARRAY_SIZE(ak4458_dif_select_texts),
ak4458_dif_select_texts);
static int get_digfil(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct ak4458_priv *ak4458 = snd_soc_component_get_drvdata(component);
ucontrol->value.enumerated.item[0] = ak4458->digfil;
return 0;
}
static int set_digfil(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct ak4458_priv *ak4458 = snd_soc_component_get_drvdata(component);
int num;
num = ucontrol->value.enumerated.item[0];
if (num > 4)
return -EINVAL;
ak4458->digfil = num;
/* write SD bit */
snd_soc_component_update_bits(component, AK4458_01_CONTROL2,
AK4458_SD_MASK,
((ak4458->digfil & 0x02) << 4));
/* write SLOW bit */
snd_soc_component_update_bits(component, AK4458_02_CONTROL3,
AK4458_SLOW_MASK,
(ak4458->digfil & 0x01));
/* write SSLOW bit */
snd_soc_component_update_bits(component, AK4458_05_CONTROL4,
AK4458_SSLOW_MASK,
((ak4458->digfil & 0x04) >> 2));
return 0;
}
static const struct snd_kcontrol_new ak4458_snd_controls[] = {
SOC_DOUBLE_R_TLV("DAC1 Playback Volume", AK4458_03_LCHATT,
AK4458_04_RCHATT, 0, 0xFF, 0, dac_tlv),
SOC_DOUBLE_R_TLV("DAC2 Playback Volume", AK4458_0F_L2CHATT,
AK4458_10_R2CHATT, 0, 0xFF, 0, dac_tlv),
SOC_DOUBLE_R_TLV("DAC3 Playback Volume", AK4458_11_L3CHATT,
AK4458_12_R3CHATT, 0, 0xFF, 0, dac_tlv),
SOC_DOUBLE_R_TLV("DAC4 Playback Volume", AK4458_13_L4CHATT,
AK4458_14_R4CHATT, 0, 0xFF, 0, dac_tlv),
SOC_ENUM("AK4458 De-emphasis Response DAC1", ak4458_dac1_dem_enum),
SOC_ENUM("AK4458 De-emphasis Response DAC2", ak4458_dac2_dem_enum),
SOC_ENUM("AK4458 De-emphasis Response DAC3", ak4458_dac3_dem_enum),
SOC_ENUM("AK4458 De-emphasis Response DAC4", ak4458_dac4_dem_enum),
SOC_ENUM_EXT("AK4458 Digital Filter Setting", ak4458_digfil_enum,
get_digfil, set_digfil),
SOC_ENUM("AK4458 Inverting Enable of DZFB", ak4458_dzfb_enum),
SOC_ENUM("AK4458 Sound Mode", ak4458_sm_enum),
SOC_ENUM("AK4458 FIR Filter Mode Setting", ak4458_fir_enum),
SOC_ENUM("AK4458 Attenuation transition Time Setting",
ak4458_ats_enum),
SOC_ENUM("AK4458 BICK fs Setting", ak4458_dif_enum),
};
/* ak4458 dapm widgets */
static const struct snd_soc_dapm_widget ak4458_dapm_widgets[] = {
SND_SOC_DAPM_DAC("AK4458 DAC1", NULL, AK4458_0A_CONTROL6, 2, 0),/*pw*/
SND_SOC_DAPM_AIF_IN("AK4458 SDTI", "Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_OUTPUT("AK4458 AOUTA"),
SND_SOC_DAPM_DAC("AK4458 DAC2", NULL, AK4458_0A_CONTROL6, 3, 0),/*pw*/
SND_SOC_DAPM_OUTPUT("AK4458 AOUTB"),
SND_SOC_DAPM_DAC("AK4458 DAC3", NULL, AK4458_0B_CONTROL7, 2, 0),/*pw*/
SND_SOC_DAPM_OUTPUT("AK4458 AOUTC"),
SND_SOC_DAPM_DAC("AK4458 DAC4", NULL, AK4458_0B_CONTROL7, 3, 0),/*pw*/
SND_SOC_DAPM_OUTPUT("AK4458 AOUTD"),
};
static const struct snd_soc_dapm_route ak4458_intercon[] = {
{"AK4458 DAC1", NULL, "AK4458 SDTI"},
{"AK4458 AOUTA", NULL, "AK4458 DAC1"},
{"AK4458 DAC2", NULL, "AK4458 SDTI"},
{"AK4458 AOUTB", NULL, "AK4458 DAC2"},
{"AK4458 DAC3", NULL, "AK4458 SDTI"},
{"AK4458 AOUTC", NULL, "AK4458 DAC3"},
{"AK4458 DAC4", NULL, "AK4458 SDTI"},
{"AK4458 AOUTD", NULL, "AK4458 DAC4"},
};
/* ak4497 controls */
static const struct snd_kcontrol_new ak4497_snd_controls[] = {
SOC_DOUBLE_R_TLV("DAC Playback Volume", AK4458_03_LCHATT,
AK4458_04_RCHATT, 0, 0xFF, 0, dac_tlv),
SOC_ENUM("AK4497 De-emphasis Response DAC", ak4458_dac1_dem_enum),
SOC_ENUM_EXT("AK4497 Digital Filter Setting", ak4458_digfil_enum,
get_digfil, set_digfil),
SOC_ENUM("AK4497 Inverting Enable of DZFB", ak4458_dzfb_enum),
SOC_ENUM("AK4497 Sound Mode", ak4458_sm_enum),
SOC_ENUM("AK4497 Attenuation transition Time Setting",
ak4458_ats_enum),
};
/* ak4497 dapm widgets */
static const struct snd_soc_dapm_widget ak4497_dapm_widgets[] = {
SND_SOC_DAPM_DAC("AK4497 DAC", NULL, AK4458_0A_CONTROL6, 2, 0),
SND_SOC_DAPM_AIF_IN("AK4497 SDTI", "Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_OUTPUT("AK4497 AOUT"),
};
/* ak4497 dapm routes */
static const struct snd_soc_dapm_route ak4497_intercon[] = {
{"AK4497 DAC", NULL, "AK4497 SDTI"},
{"AK4497 AOUT", NULL, "AK4497 DAC"},
};
static int ak4458_get_tdm_mode(struct ak4458_priv *ak4458)
{
switch (ak4458->slots * ak4458->slot_width) {
case 128:
return 1;
case 256:
return 2;
case 512:
return 3;
default:
return 0;
}
}
static int ak4458_rstn_control(struct snd_soc_component *component, int bit)
{
int ret;
if (bit)
ret = snd_soc_component_update_bits(component,
AK4458_00_CONTROL1,
AK4458_RSTN_MASK,
0x1);
else
ret = snd_soc_component_update_bits(component,
AK4458_00_CONTROL1,
AK4458_RSTN_MASK,
0x0);
if (ret < 0)
return ret;
return 0;
}
static int ak4458_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct ak4458_priv *ak4458 = snd_soc_component_get_drvdata(component);
int pcm_width = max(params_physical_width(params), ak4458->slot_width);
u8 format, dsdsel0, dsdsel1, dchn;
int nfs1, dsd_bclk, ret, channels, channels_max;
nfs1 = params_rate(params);
ak4458->fs = nfs1;
/* calculate bit clock */
channels = params_channels(params);
channels_max = dai->driver->playback.channels_max;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_DSD_U8:
case SNDRV_PCM_FORMAT_DSD_U16_LE:
case SNDRV_PCM_FORMAT_DSD_U16_BE:
case SNDRV_PCM_FORMAT_DSD_U32_LE:
case SNDRV_PCM_FORMAT_DSD_U32_BE:
dsd_bclk = nfs1 * params_physical_width(params);
switch (dsd_bclk) {
case 2822400:
dsdsel0 = 0;
dsdsel1 = 0;
break;
case 5644800:
dsdsel0 = 1;
dsdsel1 = 0;
break;
case 11289600:
dsdsel0 = 0;
dsdsel1 = 1;
break;
case 22579200:
if (ak4458->drvdata->type == AK4497) {
dsdsel0 = 1;
dsdsel1 = 1;
} else {
dev_err(dai->dev, "DSD512 not supported.\n");
return -EINVAL;
}
break;
default:
dev_err(dai->dev, "Unsupported dsd bclk.\n");
return -EINVAL;
}
snd_soc_component_update_bits(component, AK4458_06_DSD1,
AK4458_DSDSEL_MASK, dsdsel0);
snd_soc_component_update_bits(component, AK4458_09_DSD2,
AK4458_DSDSEL_MASK, dsdsel1);
break;
}
/* Master Clock Frequency Auto Setting Mode Enable */
snd_soc_component_update_bits(component, AK4458_00_CONTROL1, 0x80, 0x80);
switch (pcm_width) {
case 16:
if (ak4458->fmt == SND_SOC_DAIFMT_I2S)
format = AK4458_DIF_24BIT_I2S;
else
format = AK4458_DIF_16BIT_LSB;
break;
case 32:
switch (ak4458->fmt) {
case SND_SOC_DAIFMT_I2S:
format = AK4458_DIF_32BIT_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
format = AK4458_DIF_32BIT_MSB;
break;
case SND_SOC_DAIFMT_RIGHT_J:
format = AK4458_DIF_32BIT_LSB;
break;
case SND_SOC_DAIFMT_DSP_B:
format = AK4458_DIF_32BIT_MSB;
break;
case SND_SOC_DAIFMT_PDM:
format = AK4458_DIF_32BIT_MSB;
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, AK4458_00_CONTROL1,
AK4458_DIF_MASK, format);
/*
* Enable/disable Daisy Chain if in TDM mode and the number of played
* channels is bigger than the maximum supported number of channels
*/
dchn = ak4458_get_tdm_mode(ak4458) &&
(ak4458->fmt == SND_SOC_DAIFMT_DSP_B) &&
(channels > channels_max) ? AK4458_DCHAIN_MASK : 0;
snd_soc_component_update_bits(component, AK4458_0B_CONTROL7,
AK4458_DCHAIN_MASK, dchn);
if (ak4458->drvdata->type == AK4497) {
ret = snd_soc_component_update_bits(component, AK4458_09_DSD2,
0x4, (ak4458->dsd_path << 2));
if (ret < 0)
return ret;
}
ret = ak4458_rstn_control(component, 0);
if (ret)
return ret;
ret = ak4458_rstn_control(component, 1);
if (ret)
return ret;
return 0;
}
static int ak4458_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct ak4458_priv *ak4458 = snd_soc_component_get_drvdata(component);
int ret;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC: /* Consumer Mode */
break;
case SND_SOC_DAIFMT_CBP_CFP: /* Provider Mode is not supported */
case SND_SOC_DAIFMT_CBC_CFP:
case SND_SOC_DAIFMT_CBP_CFC:
default:
dev_err(component->dev, "Clock provider mode unsupported\n");
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_LEFT_J:
case SND_SOC_DAIFMT_RIGHT_J:
case SND_SOC_DAIFMT_DSP_B:
case SND_SOC_DAIFMT_PDM:
ak4458->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
break;
default:
dev_err(component->dev, "Audio format 0x%02X unsupported\n",
fmt & SND_SOC_DAIFMT_FORMAT_MASK);
return -EINVAL;
}
/* DSD mode */
snd_soc_component_update_bits(component, AK4458_02_CONTROL3,
AK4458_DP_MASK,
ak4458->fmt == SND_SOC_DAIFMT_PDM ?
AK4458_DP_MASK : 0);
ret = ak4458_rstn_control(component, 0);
if (ret)
return ret;
ret = ak4458_rstn_control(component, 1);
if (ret)
return ret;
return 0;
}
static const int att_speed[] = { 4080, 2040, 510, 255 };
static int ak4458_set_dai_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
struct ak4458_priv *ak4458 = snd_soc_component_get_drvdata(component);
int nfs, ndt, reg;
int ats;
nfs = ak4458->fs;
reg = snd_soc_component_read(component, AK4458_0B_CONTROL7);
ats = (reg & AK4458_ATS_MASK) >> AK4458_ATS_SHIFT;
ndt = att_speed[ats] / (nfs / 1000);
if (mute) {
snd_soc_component_update_bits(component, AK4458_01_CONTROL2, 0x01, 1);
mdelay(ndt);
if (ak4458->mute_gpiod)
gpiod_set_value_cansleep(ak4458->mute_gpiod, 1);
} else {
if (ak4458->mute_gpiod)
gpiod_set_value_cansleep(ak4458->mute_gpiod, 0);
snd_soc_component_update_bits(component, AK4458_01_CONTROL2, 0x01, 0);
mdelay(ndt);
}
return 0;
}
static int ak4458_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
struct ak4458_priv *ak4458 = snd_soc_component_get_drvdata(component);
int mode;
ak4458->slots = slots;
ak4458->slot_width = slot_width;
mode = ak4458_get_tdm_mode(ak4458) << AK4458_MODE_SHIFT;
snd_soc_component_update_bits(component, AK4458_0A_CONTROL6,
AK4458_MODE_MASK,
mode);
return 0;
}
#define AK4458_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE |\
SNDRV_PCM_FMTBIT_DSD_U8 |\
SNDRV_PCM_FMTBIT_DSD_U16_LE |\
SNDRV_PCM_FMTBIT_DSD_U32_LE)
static const unsigned int ak4458_rates[] = {
8000, 11025, 16000, 22050,
32000, 44100, 48000, 88200,
96000, 176400, 192000, 352800,
384000, 705600, 768000, 1411200,
2822400,
};
static const struct snd_pcm_hw_constraint_list ak4458_rate_constraints = {
.count = ARRAY_SIZE(ak4458_rates),
.list = ak4458_rates,
};
static int ak4458_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
int ret;
ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&ak4458_rate_constraints);
return ret;
}
static const struct snd_soc_dai_ops ak4458_dai_ops = {
.startup = ak4458_startup,
.hw_params = ak4458_hw_params,
.set_fmt = ak4458_set_dai_fmt,
.mute_stream = ak4458_set_dai_mute,
.set_tdm_slot = ak4458_set_tdm_slot,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver ak4458_dai = {
.name = "ak4458-aif",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = AK4458_FORMATS,
},
.ops = &ak4458_dai_ops,
};
static struct snd_soc_dai_driver ak4497_dai = {
.name = "ak4497-aif",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = AK4458_FORMATS,
},
.ops = &ak4458_dai_ops,
};
static void ak4458_reset(struct ak4458_priv *ak4458, bool active)
{
if (ak4458->reset_gpiod) {
gpiod_set_value_cansleep(ak4458->reset_gpiod, active);
usleep_range(1000, 2000);
} else if (!IS_ERR_OR_NULL(ak4458->reset)) {
if (active)
reset_control_assert(ak4458->reset);
else
reset_control_deassert(ak4458->reset);
usleep_range(1000, 2000);
}
}
#ifdef CONFIG_PM
static int __maybe_unused ak4458_runtime_suspend(struct device *dev)
{
struct ak4458_priv *ak4458 = dev_get_drvdata(dev);
regcache_cache_only(ak4458->regmap, true);
ak4458_reset(ak4458, true);
if (ak4458->mute_gpiod)
gpiod_set_value_cansleep(ak4458->mute_gpiod, 0);
regulator_bulk_disable(ARRAY_SIZE(ak4458->supplies),
ak4458->supplies);
return 0;
}
static int __maybe_unused ak4458_runtime_resume(struct device *dev)
{
struct ak4458_priv *ak4458 = dev_get_drvdata(dev);
int ret;
ret = regulator_bulk_enable(ARRAY_SIZE(ak4458->supplies),
ak4458->supplies);
if (ret != 0) {
dev_err(ak4458->dev, "Failed to enable supplies: %d\n", ret);
return ret;
}
if (ak4458->mute_gpiod)
gpiod_set_value_cansleep(ak4458->mute_gpiod, 1);
ak4458_reset(ak4458, false);
regcache_cache_only(ak4458->regmap, false);
regcache_mark_dirty(ak4458->regmap);
return regcache_sync(ak4458->regmap);
}
#endif /* CONFIG_PM */
static const struct snd_soc_component_driver soc_codec_dev_ak4458 = {
.controls = ak4458_snd_controls,
.num_controls = ARRAY_SIZE(ak4458_snd_controls),
.dapm_widgets = ak4458_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(ak4458_dapm_widgets),
.dapm_routes = ak4458_intercon,
.num_dapm_routes = ARRAY_SIZE(ak4458_intercon),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct snd_soc_component_driver soc_codec_dev_ak4497 = {
.controls = ak4497_snd_controls,
.num_controls = ARRAY_SIZE(ak4497_snd_controls),
.dapm_widgets = ak4497_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(ak4497_dapm_widgets),
.dapm_routes = ak4497_intercon,
.num_dapm_routes = ARRAY_SIZE(ak4497_intercon),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config ak4458_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = AK4458_14_R4CHATT,
.reg_defaults = ak4458_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(ak4458_reg_defaults),
.cache_type = REGCACHE_RBTREE,
};
static const struct ak4458_drvdata ak4458_drvdata = {
.dai_drv = &ak4458_dai,
.comp_drv = &soc_codec_dev_ak4458,
.type = AK4458,
};
static const struct ak4458_drvdata ak4497_drvdata = {
.dai_drv = &ak4497_dai,
.comp_drv = &soc_codec_dev_ak4497,
.type = AK4497,
};
static const struct dev_pm_ops ak4458_pm = {
SET_RUNTIME_PM_OPS(ak4458_runtime_suspend, ak4458_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static int ak4458_i2c_probe(struct i2c_client *i2c)
{
struct ak4458_priv *ak4458;
int ret, i;
ak4458 = devm_kzalloc(&i2c->dev, sizeof(*ak4458), GFP_KERNEL);
if (!ak4458)
return -ENOMEM;
ak4458->regmap = devm_regmap_init_i2c(i2c, &ak4458_regmap);
if (IS_ERR(ak4458->regmap))
return PTR_ERR(ak4458->regmap);
i2c_set_clientdata(i2c, ak4458);
ak4458->dev = &i2c->dev;
ak4458->drvdata = of_device_get_match_data(&i2c->dev);
ak4458->reset = devm_reset_control_get_optional_shared(ak4458->dev, NULL);
if (IS_ERR(ak4458->reset))
return PTR_ERR(ak4458->reset);
ak4458->reset_gpiod = devm_gpiod_get_optional(ak4458->dev, "reset",
GPIOD_OUT_LOW);
if (IS_ERR(ak4458->reset_gpiod))
return PTR_ERR(ak4458->reset_gpiod);
ak4458->mute_gpiod = devm_gpiod_get_optional(ak4458->dev, "mute",
GPIOD_OUT_LOW);
if (IS_ERR(ak4458->mute_gpiod))
return PTR_ERR(ak4458->mute_gpiod);
/* Optional property for ak4497 */
of_property_read_u32(i2c->dev.of_node, "dsd-path", &ak4458->dsd_path);
for (i = 0; i < ARRAY_SIZE(ak4458->supplies); i++)
ak4458->supplies[i].supply = ak4458_supply_names[i];
ret = devm_regulator_bulk_get(ak4458->dev, ARRAY_SIZE(ak4458->supplies),
ak4458->supplies);
if (ret != 0) {
dev_err(ak4458->dev, "Failed to request supplies: %d\n", ret);
return ret;
}
ret = devm_snd_soc_register_component(ak4458->dev,
ak4458->drvdata->comp_drv,
ak4458->drvdata->dai_drv, 1);
if (ret < 0) {
dev_err(ak4458->dev, "Failed to register CODEC: %d\n", ret);
return ret;
}
pm_runtime_enable(&i2c->dev);
regcache_cache_only(ak4458->regmap, true);
ak4458_reset(ak4458, false);
return 0;
}
static void ak4458_i2c_remove(struct i2c_client *i2c)
{
struct ak4458_priv *ak4458 = i2c_get_clientdata(i2c);
ak4458_reset(ak4458, true);
pm_runtime_disable(&i2c->dev);
}
static const struct of_device_id ak4458_of_match[] = {
{ .compatible = "asahi-kasei,ak4458", .data = &ak4458_drvdata},
{ .compatible = "asahi-kasei,ak4497", .data = &ak4497_drvdata},
{ },
};
MODULE_DEVICE_TABLE(of, ak4458_of_match);
static struct i2c_driver ak4458_i2c_driver = {
.driver = {
.name = "ak4458",
.pm = &ak4458_pm,
.of_match_table = ak4458_of_match,
},
.probe = ak4458_i2c_probe,
.remove = ak4458_i2c_remove,
};
module_i2c_driver(ak4458_i2c_driver);
MODULE_AUTHOR("Junichi Wakasugi <[email protected]>");
MODULE_AUTHOR("Mihai Serban <[email protected]>");
MODULE_DESCRIPTION("ASoC AK4458 DAC driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/ak4458.c |
// SPDX-License-Identifier: GPL-2.0
//
// PCM3060 codec driver
//
// Copyright (C) 2018 Kirill Marinushkin <[email protected]>
#include <linux/module.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include "pcm3060.h"
/* dai */
static int pcm3060_set_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct snd_soc_component *comp = dai->component;
struct pcm3060_priv *priv = snd_soc_component_get_drvdata(comp);
unsigned int reg;
unsigned int val;
if (dir != SND_SOC_CLOCK_IN) {
dev_err(comp->dev, "unsupported sysclock dir: %d\n", dir);
return -EINVAL;
}
switch (clk_id) {
case PCM3060_CLK_DEF:
val = 0;
break;
case PCM3060_CLK1:
val = (dai->id == PCM3060_DAI_ID_DAC ? PCM3060_REG_CSEL : 0);
break;
case PCM3060_CLK2:
val = (dai->id == PCM3060_DAI_ID_DAC ? 0 : PCM3060_REG_CSEL);
break;
default:
dev_err(comp->dev, "unsupported sysclock id: %d\n", clk_id);
return -EINVAL;
}
if (dai->id == PCM3060_DAI_ID_DAC)
reg = PCM3060_REG67;
else
reg = PCM3060_REG72;
regmap_update_bits(priv->regmap, reg, PCM3060_REG_CSEL, val);
priv->dai[dai->id].sclk_freq = freq;
return 0;
}
static int pcm3060_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *comp = dai->component;
struct pcm3060_priv *priv = snd_soc_component_get_drvdata(comp);
unsigned int reg;
unsigned int val;
if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF) {
dev_err(comp->dev, "unsupported DAI polarity: 0x%x\n", fmt);
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
priv->dai[dai->id].is_provider = true;
break;
case SND_SOC_DAIFMT_CBC_CFC:
priv->dai[dai->id].is_provider = false;
break;
default:
dev_err(comp->dev, "unsupported DAI mode: 0x%x\n", fmt);
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
val = PCM3060_REG_FMT_I2S;
break;
case SND_SOC_DAIFMT_RIGHT_J:
val = PCM3060_REG_FMT_RJ;
break;
case SND_SOC_DAIFMT_LEFT_J:
val = PCM3060_REG_FMT_LJ;
break;
default:
dev_err(comp->dev, "unsupported DAI format: 0x%x\n", fmt);
return -EINVAL;
}
if (dai->id == PCM3060_DAI_ID_DAC)
reg = PCM3060_REG67;
else
reg = PCM3060_REG72;
regmap_update_bits(priv->regmap, reg, PCM3060_REG_MASK_FMT, val);
return 0;
}
static int pcm3060_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *comp = dai->component;
struct pcm3060_priv *priv = snd_soc_component_get_drvdata(comp);
unsigned int rate;
unsigned int ratio;
unsigned int reg;
unsigned int val;
if (!priv->dai[dai->id].is_provider) {
val = PCM3060_REG_MS_S;
goto val_ready;
}
rate = params_rate(params);
if (!rate) {
dev_err(comp->dev, "rate is not configured\n");
return -EINVAL;
}
ratio = priv->dai[dai->id].sclk_freq / rate;
switch (ratio) {
case 768:
val = PCM3060_REG_MS_M768;
break;
case 512:
val = PCM3060_REG_MS_M512;
break;
case 384:
val = PCM3060_REG_MS_M384;
break;
case 256:
val = PCM3060_REG_MS_M256;
break;
case 192:
val = PCM3060_REG_MS_M192;
break;
case 128:
val = PCM3060_REG_MS_M128;
break;
default:
dev_err(comp->dev, "unsupported ratio: %d\n", ratio);
return -EINVAL;
}
val_ready:
if (dai->id == PCM3060_DAI_ID_DAC)
reg = PCM3060_REG67;
else
reg = PCM3060_REG72;
regmap_update_bits(priv->regmap, reg, PCM3060_REG_MASK_MS, val);
return 0;
}
static const struct snd_soc_dai_ops pcm3060_dai_ops = {
.set_sysclk = pcm3060_set_sysclk,
.set_fmt = pcm3060_set_fmt,
.hw_params = pcm3060_hw_params,
};
#define PCM3060_DAI_RATES_ADC (SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 | \
SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
#define PCM3060_DAI_RATES_DAC (PCM3060_DAI_RATES_ADC | \
SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000)
static struct snd_soc_dai_driver pcm3060_dai[] = {
{
.name = "pcm3060-dac",
.id = PCM3060_DAI_ID_DAC,
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = PCM3060_DAI_RATES_DAC,
.formats = SNDRV_PCM_FMTBIT_S24_LE,
},
.ops = &pcm3060_dai_ops,
},
{
.name = "pcm3060-adc",
.id = PCM3060_DAI_ID_ADC,
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = PCM3060_DAI_RATES_ADC,
.formats = SNDRV_PCM_FMTBIT_S24_LE,
},
.ops = &pcm3060_dai_ops,
},
};
/* dapm */
static DECLARE_TLV_DB_SCALE(pcm3060_dapm_tlv, -10050, 50, 1);
static const struct snd_kcontrol_new pcm3060_dapm_controls[] = {
SOC_DOUBLE_R_RANGE_TLV("Master Playback Volume",
PCM3060_REG65, PCM3060_REG66, 0,
PCM3060_REG_AT2_MIN, PCM3060_REG_AT2_MAX,
0, pcm3060_dapm_tlv),
SOC_DOUBLE("Master Playback Switch", PCM3060_REG68,
PCM3060_REG_SHIFT_MUT21, PCM3060_REG_SHIFT_MUT22, 1, 1),
SOC_DOUBLE_R_RANGE_TLV("Master Capture Volume",
PCM3060_REG70, PCM3060_REG71, 0,
PCM3060_REG_AT1_MIN, PCM3060_REG_AT1_MAX,
0, pcm3060_dapm_tlv),
SOC_DOUBLE("Master Capture Switch", PCM3060_REG73,
PCM3060_REG_SHIFT_MUT11, PCM3060_REG_SHIFT_MUT12, 1, 1),
};
static const struct snd_soc_dapm_widget pcm3060_dapm_widgets[] = {
SND_SOC_DAPM_DAC("DAC", "Playback", PCM3060_REG64,
PCM3060_REG_SHIFT_DAPSV, 1),
SND_SOC_DAPM_OUTPUT("OUTL"),
SND_SOC_DAPM_OUTPUT("OUTR"),
SND_SOC_DAPM_INPUT("INL"),
SND_SOC_DAPM_INPUT("INR"),
SND_SOC_DAPM_ADC("ADC", "Capture", PCM3060_REG64,
PCM3060_REG_SHIFT_ADPSV, 1),
};
static const struct snd_soc_dapm_route pcm3060_dapm_map[] = {
{ "OUTL", NULL, "DAC" },
{ "OUTR", NULL, "DAC" },
{ "ADC", NULL, "INL" },
{ "ADC", NULL, "INR" },
};
/* soc component */
static const struct snd_soc_component_driver pcm3060_soc_comp_driver = {
.controls = pcm3060_dapm_controls,
.num_controls = ARRAY_SIZE(pcm3060_dapm_controls),
.dapm_widgets = pcm3060_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(pcm3060_dapm_widgets),
.dapm_routes = pcm3060_dapm_map,
.num_dapm_routes = ARRAY_SIZE(pcm3060_dapm_map),
.endianness = 1,
};
/* regmap */
static bool pcm3060_reg_writeable(struct device *dev, unsigned int reg)
{
return (reg >= PCM3060_REG64);
}
static bool pcm3060_reg_readable(struct device *dev, unsigned int reg)
{
return (reg >= PCM3060_REG64);
}
static bool pcm3060_reg_volatile(struct device *dev, unsigned int reg)
{
/* PCM3060_REG64 is volatile */
return (reg == PCM3060_REG64);
}
static const struct reg_default pcm3060_reg_defaults[] = {
{ PCM3060_REG64, 0xF0 },
{ PCM3060_REG65, 0xFF },
{ PCM3060_REG66, 0xFF },
{ PCM3060_REG67, 0x00 },
{ PCM3060_REG68, 0x00 },
{ PCM3060_REG69, 0x00 },
{ PCM3060_REG70, 0xD7 },
{ PCM3060_REG71, 0xD7 },
{ PCM3060_REG72, 0x00 },
{ PCM3060_REG73, 0x00 },
};
const struct regmap_config pcm3060_regmap = {
.reg_bits = 8,
.val_bits = 8,
.writeable_reg = pcm3060_reg_writeable,
.readable_reg = pcm3060_reg_readable,
.volatile_reg = pcm3060_reg_volatile,
.max_register = PCM3060_REG73,
.reg_defaults = pcm3060_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(pcm3060_reg_defaults),
.cache_type = REGCACHE_RBTREE,
};
EXPORT_SYMBOL(pcm3060_regmap);
/* device */
static void pcm3060_parse_dt(const struct device_node *np,
struct pcm3060_priv *priv)
{
priv->out_se = of_property_read_bool(np, "ti,out-single-ended");
}
int pcm3060_probe(struct device *dev)
{
int rc;
struct pcm3060_priv *priv = dev_get_drvdata(dev);
/* soft reset */
rc = regmap_update_bits(priv->regmap, PCM3060_REG64,
PCM3060_REG_MRST, 0);
if (rc) {
dev_err(dev, "failed to reset component, rc=%d\n", rc);
return rc;
}
if (dev->of_node)
pcm3060_parse_dt(dev->of_node, priv);
if (priv->out_se)
regmap_update_bits(priv->regmap, PCM3060_REG64,
PCM3060_REG_SE, PCM3060_REG_SE);
rc = devm_snd_soc_register_component(dev, &pcm3060_soc_comp_driver,
pcm3060_dai,
ARRAY_SIZE(pcm3060_dai));
if (rc) {
dev_err(dev, "failed to register component, rc=%d\n", rc);
return rc;
}
return 0;
}
EXPORT_SYMBOL(pcm3060_probe);
MODULE_DESCRIPTION("PCM3060 codec driver");
MODULE_AUTHOR("Kirill Marinushkin <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/pcm3060.c |
// SPDX-License-Identifier: GPL-2.0
/*
* ALSA SoC Texas Instruments TAS6424 Quad-Channel Audio Amplifier
*
* Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/
* Author: Andreas Dannenberg <[email protected]>
* Andrew F. Davis <[email protected]>
*/
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/device.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/regulator/consumer.h>
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/tlv.h>
#include "tas6424.h"
/* Define how often to check (and clear) the fault status register (in ms) */
#define TAS6424_FAULT_CHECK_INTERVAL 200
static const char * const tas6424_supply_names[] = {
"dvdd", /* Digital power supply. Connect to 3.3-V supply. */
"vbat", /* Supply used for higher voltage analog circuits. */
"pvdd", /* Class-D amp output FETs supply. */
};
#define TAS6424_NUM_SUPPLIES ARRAY_SIZE(tas6424_supply_names)
struct tas6424_data {
struct device *dev;
struct regmap *regmap;
struct regulator_bulk_data supplies[TAS6424_NUM_SUPPLIES];
struct delayed_work fault_check_work;
unsigned int last_cfault;
unsigned int last_fault1;
unsigned int last_fault2;
unsigned int last_warn;
struct gpio_desc *standby_gpio;
struct gpio_desc *mute_gpio;
};
/*
* DAC digital volumes. From -103.5 to 24 dB in 0.5 dB steps. Note that
* setting the gain below -100 dB (register value <0x7) is effectively a MUTE
* as per device datasheet.
*/
static DECLARE_TLV_DB_SCALE(dac_tlv, -10350, 50, 0);
static const struct snd_kcontrol_new tas6424_snd_controls[] = {
SOC_SINGLE_TLV("Speaker Driver CH1 Playback Volume",
TAS6424_CH1_VOL_CTRL, 0, 0xff, 0, dac_tlv),
SOC_SINGLE_TLV("Speaker Driver CH2 Playback Volume",
TAS6424_CH2_VOL_CTRL, 0, 0xff, 0, dac_tlv),
SOC_SINGLE_TLV("Speaker Driver CH3 Playback Volume",
TAS6424_CH3_VOL_CTRL, 0, 0xff, 0, dac_tlv),
SOC_SINGLE_TLV("Speaker Driver CH4 Playback Volume",
TAS6424_CH4_VOL_CTRL, 0, 0xff, 0, dac_tlv),
SOC_SINGLE_STROBE("Auto Diagnostics Switch", TAS6424_DC_DIAG_CTRL1,
TAS6424_LDGBYPASS_SHIFT, 1),
};
static int tas6424_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct tas6424_data *tas6424 = snd_soc_component_get_drvdata(component);
dev_dbg(component->dev, "%s() event=0x%0x\n", __func__, event);
if (event & SND_SOC_DAPM_POST_PMU) {
/* Observe codec shutdown-to-active time */
msleep(12);
/* Turn on TAS6424 periodic fault checking/handling */
tas6424->last_fault1 = 0;
tas6424->last_fault2 = 0;
tas6424->last_warn = 0;
schedule_delayed_work(&tas6424->fault_check_work,
msecs_to_jiffies(TAS6424_FAULT_CHECK_INTERVAL));
} else if (event & SND_SOC_DAPM_PRE_PMD) {
/* Disable TAS6424 periodic fault checking/handling */
cancel_delayed_work_sync(&tas6424->fault_check_work);
}
return 0;
}
static const struct snd_soc_dapm_widget tas6424_dapm_widgets[] = {
SND_SOC_DAPM_AIF_IN("DAC IN", "Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC_E("DAC", NULL, SND_SOC_NOPM, 0, 0, tas6424_dac_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_OUTPUT("OUT")
};
static const struct snd_soc_dapm_route tas6424_audio_map[] = {
{ "DAC", NULL, "DAC IN" },
{ "OUT", NULL, "DAC" },
};
static int tas6424_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
unsigned int rate = params_rate(params);
unsigned int width = params_width(params);
u8 sap_ctrl = 0;
dev_dbg(component->dev, "%s() rate=%u width=%u\n", __func__, rate, width);
switch (rate) {
case 44100:
sap_ctrl |= TAS6424_SAP_RATE_44100;
break;
case 48000:
sap_ctrl |= TAS6424_SAP_RATE_48000;
break;
case 96000:
sap_ctrl |= TAS6424_SAP_RATE_96000;
break;
default:
dev_err(component->dev, "unsupported sample rate: %u\n", rate);
return -EINVAL;
}
switch (width) {
case 16:
sap_ctrl |= TAS6424_SAP_TDM_SLOT_SZ_16;
break;
case 24:
break;
default:
dev_err(component->dev, "unsupported sample width: %u\n", width);
return -EINVAL;
}
snd_soc_component_update_bits(component, TAS6424_SAP_CTRL,
TAS6424_SAP_RATE_MASK |
TAS6424_SAP_TDM_SLOT_SZ_16,
sap_ctrl);
return 0;
}
static int tas6424_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
u8 serial_format = 0;
dev_dbg(component->dev, "%s() fmt=0x%0x\n", __func__, fmt);
/* clock masters */
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC:
break;
default:
dev_err(component->dev, "Invalid DAI clocking\n");
return -EINVAL;
}
/* signal polarity */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
default:
dev_err(component->dev, "Invalid DAI clock signal polarity\n");
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
serial_format |= TAS6424_SAP_I2S;
break;
case SND_SOC_DAIFMT_DSP_A:
serial_format |= TAS6424_SAP_DSP;
break;
case SND_SOC_DAIFMT_DSP_B:
/*
* We can use the fact that the TAS6424 does not care about the
* LRCLK duty cycle during TDM to receive DSP_B formatted data
* in LEFTJ mode (no delaying of the 1st data bit).
*/
serial_format |= TAS6424_SAP_LEFTJ;
break;
case SND_SOC_DAIFMT_LEFT_J:
serial_format |= TAS6424_SAP_LEFTJ;
break;
default:
dev_err(component->dev, "Invalid DAI interface format\n");
return -EINVAL;
}
snd_soc_component_update_bits(component, TAS6424_SAP_CTRL,
TAS6424_SAP_FMT_MASK, serial_format);
return 0;
}
static int tas6424_set_dai_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask,
int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
unsigned int first_slot, last_slot;
bool sap_tdm_slot_last;
dev_dbg(component->dev, "%s() tx_mask=%d rx_mask=%d\n", __func__,
tx_mask, rx_mask);
if (!tx_mask || !rx_mask)
return 0; /* nothing needed to disable TDM mode */
/*
* Determine the first slot and last slot that is being requested so
* we'll be able to more easily enforce certain constraints as the
* TAS6424's TDM interface is not fully configurable.
*/
first_slot = __ffs(tx_mask);
last_slot = __fls(rx_mask);
if (last_slot - first_slot != 4) {
dev_err(component->dev, "tdm mask must cover 4 contiguous slots\n");
return -EINVAL;
}
switch (first_slot) {
case 0:
sap_tdm_slot_last = false;
break;
case 4:
sap_tdm_slot_last = true;
break;
default:
dev_err(component->dev, "tdm mask must start at slot 0 or 4\n");
return -EINVAL;
}
snd_soc_component_update_bits(component, TAS6424_SAP_CTRL, TAS6424_SAP_TDM_SLOT_LAST,
sap_tdm_slot_last ? TAS6424_SAP_TDM_SLOT_LAST : 0);
return 0;
}
static int tas6424_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
struct tas6424_data *tas6424 = snd_soc_component_get_drvdata(component);
unsigned int val;
dev_dbg(component->dev, "%s() mute=%d\n", __func__, mute);
if (tas6424->mute_gpio) {
gpiod_set_value_cansleep(tas6424->mute_gpio, mute);
return 0;
}
if (mute)
val = TAS6424_ALL_STATE_MUTE;
else
val = TAS6424_ALL_STATE_PLAY;
snd_soc_component_write(component, TAS6424_CH_STATE_CTRL, val);
return 0;
}
static int tas6424_power_off(struct snd_soc_component *component)
{
struct tas6424_data *tas6424 = snd_soc_component_get_drvdata(component);
int ret;
snd_soc_component_write(component, TAS6424_CH_STATE_CTRL, TAS6424_ALL_STATE_HIZ);
regcache_cache_only(tas6424->regmap, true);
regcache_mark_dirty(tas6424->regmap);
ret = regulator_bulk_disable(ARRAY_SIZE(tas6424->supplies),
tas6424->supplies);
if (ret < 0) {
dev_err(component->dev, "failed to disable supplies: %d\n", ret);
return ret;
}
return 0;
}
static int tas6424_power_on(struct snd_soc_component *component)
{
struct tas6424_data *tas6424 = snd_soc_component_get_drvdata(component);
int ret;
u8 chan_states;
int no_auto_diags = 0;
unsigned int reg_val;
if (!regmap_read(tas6424->regmap, TAS6424_DC_DIAG_CTRL1, ®_val))
no_auto_diags = reg_val & TAS6424_LDGBYPASS_MASK;
ret = regulator_bulk_enable(ARRAY_SIZE(tas6424->supplies),
tas6424->supplies);
if (ret < 0) {
dev_err(component->dev, "failed to enable supplies: %d\n", ret);
return ret;
}
regcache_cache_only(tas6424->regmap, false);
ret = regcache_sync(tas6424->regmap);
if (ret < 0) {
dev_err(component->dev, "failed to sync regcache: %d\n", ret);
return ret;
}
if (tas6424->mute_gpio) {
gpiod_set_value_cansleep(tas6424->mute_gpio, 0);
/*
* channels are muted via the mute pin. Don't also mute
* them via the registers so that subsequent register
* access is not necessary to un-mute the channels
*/
chan_states = TAS6424_ALL_STATE_PLAY;
} else {
chan_states = TAS6424_ALL_STATE_MUTE;
}
snd_soc_component_write(component, TAS6424_CH_STATE_CTRL, chan_states);
/* any time we come out of HIZ, the output channels automatically run DC
* load diagnostics if autodiagnotics are enabled. wait here until this
* completes.
*/
if (!no_auto_diags)
msleep(230);
return 0;
}
static int tas6424_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
dev_dbg(component->dev, "%s() level=%d\n", __func__, level);
switch (level) {
case SND_SOC_BIAS_ON:
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
tas6424_power_on(component);
break;
case SND_SOC_BIAS_OFF:
tas6424_power_off(component);
break;
}
return 0;
}
static struct snd_soc_component_driver soc_codec_dev_tas6424 = {
.set_bias_level = tas6424_set_bias_level,
.controls = tas6424_snd_controls,
.num_controls = ARRAY_SIZE(tas6424_snd_controls),
.dapm_widgets = tas6424_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(tas6424_dapm_widgets),
.dapm_routes = tas6424_audio_map,
.num_dapm_routes = ARRAY_SIZE(tas6424_audio_map),
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct snd_soc_dai_ops tas6424_speaker_dai_ops = {
.hw_params = tas6424_hw_params,
.set_fmt = tas6424_set_dai_fmt,
.set_tdm_slot = tas6424_set_dai_tdm_slot,
.mute_stream = tas6424_mute,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver tas6424_dai[] = {
{
.name = "tas6424-amplifier",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 4,
.rates = TAS6424_RATES,
.formats = TAS6424_FORMATS,
},
.ops = &tas6424_speaker_dai_ops,
},
};
static void tas6424_fault_check_work(struct work_struct *work)
{
struct tas6424_data *tas6424 = container_of(work, struct tas6424_data,
fault_check_work.work);
struct device *dev = tas6424->dev;
unsigned int reg;
int ret;
ret = regmap_read(tas6424->regmap, TAS6424_CHANNEL_FAULT, ®);
if (ret < 0) {
dev_err(dev, "failed to read CHANNEL_FAULT register: %d\n", ret);
goto out;
}
if (!reg) {
tas6424->last_cfault = reg;
goto check_global_fault1_reg;
}
/*
* Only flag errors once for a given occurrence. This is needed as
* the TAS6424 will take time clearing the fault condition internally
* during which we don't want to bombard the system with the same
* error message over and over.
*/
if ((reg & TAS6424_FAULT_OC_CH1) && !(tas6424->last_cfault & TAS6424_FAULT_OC_CH1))
dev_crit(dev, "experienced a channel 1 overcurrent fault\n");
if ((reg & TAS6424_FAULT_OC_CH2) && !(tas6424->last_cfault & TAS6424_FAULT_OC_CH2))
dev_crit(dev, "experienced a channel 2 overcurrent fault\n");
if ((reg & TAS6424_FAULT_OC_CH3) && !(tas6424->last_cfault & TAS6424_FAULT_OC_CH3))
dev_crit(dev, "experienced a channel 3 overcurrent fault\n");
if ((reg & TAS6424_FAULT_OC_CH4) && !(tas6424->last_cfault & TAS6424_FAULT_OC_CH4))
dev_crit(dev, "experienced a channel 4 overcurrent fault\n");
if ((reg & TAS6424_FAULT_DC_CH1) && !(tas6424->last_cfault & TAS6424_FAULT_DC_CH1))
dev_crit(dev, "experienced a channel 1 DC fault\n");
if ((reg & TAS6424_FAULT_DC_CH2) && !(tas6424->last_cfault & TAS6424_FAULT_DC_CH2))
dev_crit(dev, "experienced a channel 2 DC fault\n");
if ((reg & TAS6424_FAULT_DC_CH3) && !(tas6424->last_cfault & TAS6424_FAULT_DC_CH3))
dev_crit(dev, "experienced a channel 3 DC fault\n");
if ((reg & TAS6424_FAULT_DC_CH4) && !(tas6424->last_cfault & TAS6424_FAULT_DC_CH4))
dev_crit(dev, "experienced a channel 4 DC fault\n");
/* Store current fault1 value so we can detect any changes next time */
tas6424->last_cfault = reg;
check_global_fault1_reg:
ret = regmap_read(tas6424->regmap, TAS6424_GLOB_FAULT1, ®);
if (ret < 0) {
dev_err(dev, "failed to read GLOB_FAULT1 register: %d\n", ret);
goto out;
}
/*
* Ignore any clock faults as there is no clean way to check for them.
* We would need to start checking for those faults *after* the SAIF
* stream has been setup, and stop checking *before* the stream is
* stopped to avoid any false-positives. However there are no
* appropriate hooks to monitor these events.
*/
reg &= TAS6424_FAULT_PVDD_OV |
TAS6424_FAULT_VBAT_OV |
TAS6424_FAULT_PVDD_UV |
TAS6424_FAULT_VBAT_UV;
if (!reg) {
tas6424->last_fault1 = reg;
goto check_global_fault2_reg;
}
if ((reg & TAS6424_FAULT_PVDD_OV) && !(tas6424->last_fault1 & TAS6424_FAULT_PVDD_OV))
dev_crit(dev, "experienced a PVDD overvoltage fault\n");
if ((reg & TAS6424_FAULT_VBAT_OV) && !(tas6424->last_fault1 & TAS6424_FAULT_VBAT_OV))
dev_crit(dev, "experienced a VBAT overvoltage fault\n");
if ((reg & TAS6424_FAULT_PVDD_UV) && !(tas6424->last_fault1 & TAS6424_FAULT_PVDD_UV))
dev_crit(dev, "experienced a PVDD undervoltage fault\n");
if ((reg & TAS6424_FAULT_VBAT_UV) && !(tas6424->last_fault1 & TAS6424_FAULT_VBAT_UV))
dev_crit(dev, "experienced a VBAT undervoltage fault\n");
/* Store current fault1 value so we can detect any changes next time */
tas6424->last_fault1 = reg;
check_global_fault2_reg:
ret = regmap_read(tas6424->regmap, TAS6424_GLOB_FAULT2, ®);
if (ret < 0) {
dev_err(dev, "failed to read GLOB_FAULT2 register: %d\n", ret);
goto out;
}
reg &= TAS6424_FAULT_OTSD |
TAS6424_FAULT_OTSD_CH1 |
TAS6424_FAULT_OTSD_CH2 |
TAS6424_FAULT_OTSD_CH3 |
TAS6424_FAULT_OTSD_CH4;
if (!reg) {
tas6424->last_fault2 = reg;
goto check_warn_reg;
}
if ((reg & TAS6424_FAULT_OTSD) && !(tas6424->last_fault2 & TAS6424_FAULT_OTSD))
dev_crit(dev, "experienced a global overtemp shutdown\n");
if ((reg & TAS6424_FAULT_OTSD_CH1) && !(tas6424->last_fault2 & TAS6424_FAULT_OTSD_CH1))
dev_crit(dev, "experienced an overtemp shutdown on CH1\n");
if ((reg & TAS6424_FAULT_OTSD_CH2) && !(tas6424->last_fault2 & TAS6424_FAULT_OTSD_CH2))
dev_crit(dev, "experienced an overtemp shutdown on CH2\n");
if ((reg & TAS6424_FAULT_OTSD_CH3) && !(tas6424->last_fault2 & TAS6424_FAULT_OTSD_CH3))
dev_crit(dev, "experienced an overtemp shutdown on CH3\n");
if ((reg & TAS6424_FAULT_OTSD_CH4) && !(tas6424->last_fault2 & TAS6424_FAULT_OTSD_CH4))
dev_crit(dev, "experienced an overtemp shutdown on CH4\n");
/* Store current fault2 value so we can detect any changes next time */
tas6424->last_fault2 = reg;
check_warn_reg:
ret = regmap_read(tas6424->regmap, TAS6424_WARN, ®);
if (ret < 0) {
dev_err(dev, "failed to read WARN register: %d\n", ret);
goto out;
}
reg &= TAS6424_WARN_VDD_UV |
TAS6424_WARN_VDD_POR |
TAS6424_WARN_VDD_OTW |
TAS6424_WARN_VDD_OTW_CH1 |
TAS6424_WARN_VDD_OTW_CH2 |
TAS6424_WARN_VDD_OTW_CH3 |
TAS6424_WARN_VDD_OTW_CH4;
if (!reg) {
tas6424->last_warn = reg;
goto out;
}
if ((reg & TAS6424_WARN_VDD_UV) && !(tas6424->last_warn & TAS6424_WARN_VDD_UV))
dev_warn(dev, "experienced a VDD under voltage condition\n");
if ((reg & TAS6424_WARN_VDD_POR) && !(tas6424->last_warn & TAS6424_WARN_VDD_POR))
dev_warn(dev, "experienced a VDD POR condition\n");
if ((reg & TAS6424_WARN_VDD_OTW) && !(tas6424->last_warn & TAS6424_WARN_VDD_OTW))
dev_warn(dev, "experienced a global overtemp warning\n");
if ((reg & TAS6424_WARN_VDD_OTW_CH1) && !(tas6424->last_warn & TAS6424_WARN_VDD_OTW_CH1))
dev_warn(dev, "experienced an overtemp warning on CH1\n");
if ((reg & TAS6424_WARN_VDD_OTW_CH2) && !(tas6424->last_warn & TAS6424_WARN_VDD_OTW_CH2))
dev_warn(dev, "experienced an overtemp warning on CH2\n");
if ((reg & TAS6424_WARN_VDD_OTW_CH3) && !(tas6424->last_warn & TAS6424_WARN_VDD_OTW_CH3))
dev_warn(dev, "experienced an overtemp warning on CH3\n");
if ((reg & TAS6424_WARN_VDD_OTW_CH4) && !(tas6424->last_warn & TAS6424_WARN_VDD_OTW_CH4))
dev_warn(dev, "experienced an overtemp warning on CH4\n");
/* Store current warn value so we can detect any changes next time */
tas6424->last_warn = reg;
/* Clear any warnings by toggling the CLEAR_FAULT control bit */
ret = regmap_write_bits(tas6424->regmap, TAS6424_MISC_CTRL3,
TAS6424_CLEAR_FAULT, TAS6424_CLEAR_FAULT);
if (ret < 0)
dev_err(dev, "failed to write MISC_CTRL3 register: %d\n", ret);
ret = regmap_write_bits(tas6424->regmap, TAS6424_MISC_CTRL3,
TAS6424_CLEAR_FAULT, 0);
if (ret < 0)
dev_err(dev, "failed to write MISC_CTRL3 register: %d\n", ret);
out:
/* Schedule the next fault check at the specified interval */
schedule_delayed_work(&tas6424->fault_check_work,
msecs_to_jiffies(TAS6424_FAULT_CHECK_INTERVAL));
}
static const struct reg_default tas6424_reg_defaults[] = {
{ TAS6424_MODE_CTRL, 0x00 },
{ TAS6424_MISC_CTRL1, 0x32 },
{ TAS6424_MISC_CTRL2, 0x62 },
{ TAS6424_SAP_CTRL, 0x04 },
{ TAS6424_CH_STATE_CTRL, 0x55 },
{ TAS6424_CH1_VOL_CTRL, 0xcf },
{ TAS6424_CH2_VOL_CTRL, 0xcf },
{ TAS6424_CH3_VOL_CTRL, 0xcf },
{ TAS6424_CH4_VOL_CTRL, 0xcf },
{ TAS6424_DC_DIAG_CTRL1, 0x00 },
{ TAS6424_DC_DIAG_CTRL2, 0x11 },
{ TAS6424_DC_DIAG_CTRL3, 0x11 },
{ TAS6424_PIN_CTRL, 0xff },
{ TAS6424_AC_DIAG_CTRL1, 0x00 },
{ TAS6424_MISC_CTRL3, 0x00 },
{ TAS6424_CLIP_CTRL, 0x01 },
{ TAS6424_CLIP_WINDOW, 0x14 },
{ TAS6424_CLIP_WARN, 0x00 },
{ TAS6424_CBC_STAT, 0x00 },
{ TAS6424_MISC_CTRL4, 0x40 },
};
static bool tas6424_is_writable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TAS6424_MODE_CTRL:
case TAS6424_MISC_CTRL1:
case TAS6424_MISC_CTRL2:
case TAS6424_SAP_CTRL:
case TAS6424_CH_STATE_CTRL:
case TAS6424_CH1_VOL_CTRL:
case TAS6424_CH2_VOL_CTRL:
case TAS6424_CH3_VOL_CTRL:
case TAS6424_CH4_VOL_CTRL:
case TAS6424_DC_DIAG_CTRL1:
case TAS6424_DC_DIAG_CTRL2:
case TAS6424_DC_DIAG_CTRL3:
case TAS6424_PIN_CTRL:
case TAS6424_AC_DIAG_CTRL1:
case TAS6424_MISC_CTRL3:
case TAS6424_CLIP_CTRL:
case TAS6424_CLIP_WINDOW:
case TAS6424_CLIP_WARN:
case TAS6424_CBC_STAT:
case TAS6424_MISC_CTRL4:
return true;
default:
return false;
}
}
static bool tas6424_is_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TAS6424_DC_LOAD_DIAG_REP12:
case TAS6424_DC_LOAD_DIAG_REP34:
case TAS6424_DC_LOAD_DIAG_REPLO:
case TAS6424_CHANNEL_STATE:
case TAS6424_CHANNEL_FAULT:
case TAS6424_GLOB_FAULT1:
case TAS6424_GLOB_FAULT2:
case TAS6424_WARN:
case TAS6424_AC_LOAD_DIAG_REP1:
case TAS6424_AC_LOAD_DIAG_REP2:
case TAS6424_AC_LOAD_DIAG_REP3:
case TAS6424_AC_LOAD_DIAG_REP4:
return true;
default:
return false;
}
}
static const struct regmap_config tas6424_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.writeable_reg = tas6424_is_writable_reg,
.volatile_reg = tas6424_is_volatile_reg,
.max_register = TAS6424_MAX,
.reg_defaults = tas6424_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tas6424_reg_defaults),
.cache_type = REGCACHE_RBTREE,
};
#if IS_ENABLED(CONFIG_OF)
static const struct of_device_id tas6424_of_ids[] = {
{ .compatible = "ti,tas6424", },
{ },
};
MODULE_DEVICE_TABLE(of, tas6424_of_ids);
#endif
static int tas6424_i2c_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct tas6424_data *tas6424;
int ret;
int i;
tas6424 = devm_kzalloc(dev, sizeof(*tas6424), GFP_KERNEL);
if (!tas6424)
return -ENOMEM;
dev_set_drvdata(dev, tas6424);
tas6424->dev = dev;
tas6424->regmap = devm_regmap_init_i2c(client, &tas6424_regmap_config);
if (IS_ERR(tas6424->regmap)) {
ret = PTR_ERR(tas6424->regmap);
dev_err(dev, "unable to allocate register map: %d\n", ret);
return ret;
}
/*
* Get control of the standby pin and set it LOW to take the codec
* out of the stand-by mode.
* Note: The actual pin polarity is taken care of in the GPIO lib
* according the polarity specified in the DTS.
*/
tas6424->standby_gpio = devm_gpiod_get_optional(dev, "standby",
GPIOD_OUT_LOW);
if (IS_ERR(tas6424->standby_gpio)) {
if (PTR_ERR(tas6424->standby_gpio) == -EPROBE_DEFER)
return -EPROBE_DEFER;
dev_info(dev, "failed to get standby GPIO: %ld\n",
PTR_ERR(tas6424->standby_gpio));
tas6424->standby_gpio = NULL;
}
/*
* Get control of the mute pin and set it HIGH in order to start with
* all the output muted.
* Note: The actual pin polarity is taken care of in the GPIO lib
* according the polarity specified in the DTS.
*/
tas6424->mute_gpio = devm_gpiod_get_optional(dev, "mute",
GPIOD_OUT_HIGH);
if (IS_ERR(tas6424->mute_gpio)) {
if (PTR_ERR(tas6424->mute_gpio) == -EPROBE_DEFER)
return -EPROBE_DEFER;
dev_info(dev, "failed to get nmute GPIO: %ld\n",
PTR_ERR(tas6424->mute_gpio));
tas6424->mute_gpio = NULL;
}
for (i = 0; i < ARRAY_SIZE(tas6424->supplies); i++)
tas6424->supplies[i].supply = tas6424_supply_names[i];
ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(tas6424->supplies),
tas6424->supplies);
if (ret) {
dev_err(dev, "unable to request supplies: %d\n", ret);
return ret;
}
ret = regulator_bulk_enable(ARRAY_SIZE(tas6424->supplies),
tas6424->supplies);
if (ret) {
dev_err(dev, "unable to enable supplies: %d\n", ret);
return ret;
}
/* Reset device to establish well-defined startup state */
ret = regmap_update_bits(tas6424->regmap, TAS6424_MODE_CTRL,
TAS6424_RESET, TAS6424_RESET);
if (ret) {
dev_err(dev, "unable to reset device: %d\n", ret);
goto disable_regs;
}
INIT_DELAYED_WORK(&tas6424->fault_check_work, tas6424_fault_check_work);
ret = devm_snd_soc_register_component(dev, &soc_codec_dev_tas6424,
tas6424_dai, ARRAY_SIZE(tas6424_dai));
if (ret < 0) {
dev_err(dev, "unable to register codec: %d\n", ret);
goto disable_regs;
}
return 0;
disable_regs:
regulator_bulk_disable(ARRAY_SIZE(tas6424->supplies), tas6424->supplies);
return ret;
}
static void tas6424_i2c_remove(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct tas6424_data *tas6424 = dev_get_drvdata(dev);
int ret;
cancel_delayed_work_sync(&tas6424->fault_check_work);
/* put the codec in stand-by */
if (tas6424->standby_gpio)
gpiod_set_value_cansleep(tas6424->standby_gpio, 1);
ret = regulator_bulk_disable(ARRAY_SIZE(tas6424->supplies),
tas6424->supplies);
if (ret < 0)
dev_err(dev, "unable to disable supplies: %d\n", ret);
}
static const struct i2c_device_id tas6424_i2c_ids[] = {
{ "tas6424", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, tas6424_i2c_ids);
static struct i2c_driver tas6424_i2c_driver = {
.driver = {
.name = "tas6424",
.of_match_table = of_match_ptr(tas6424_of_ids),
},
.probe = tas6424_i2c_probe,
.remove = tas6424_i2c_remove,
.id_table = tas6424_i2c_ids,
};
module_i2c_driver(tas6424_i2c_driver);
MODULE_AUTHOR("Andreas Dannenberg <[email protected]>");
MODULE_AUTHOR("Andrew F. Davis <[email protected]>");
MODULE_DESCRIPTION("TAS6424 Audio amplifier driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/tas6424.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* max98090.c -- MAX98090 ALSA SoC Audio driver
*
* Copyright 2011-2012 Maxim Integrated Products
*/
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pm.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/acpi.h>
#include <linux/clk.h>
#include <sound/jack.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <sound/max98090.h>
#include "max98090.h"
/* Allows for sparsely populated register maps */
static const struct reg_default max98090_reg[] = {
{ 0x00, 0x00 }, /* 00 Software Reset */
{ 0x03, 0x04 }, /* 03 Interrupt Masks */
{ 0x04, 0x00 }, /* 04 System Clock Quick */
{ 0x05, 0x00 }, /* 05 Sample Rate Quick */
{ 0x06, 0x00 }, /* 06 DAI Interface Quick */
{ 0x07, 0x00 }, /* 07 DAC Path Quick */
{ 0x08, 0x00 }, /* 08 Mic/Direct to ADC Quick */
{ 0x09, 0x00 }, /* 09 Line to ADC Quick */
{ 0x0A, 0x00 }, /* 0A Analog Mic Loop Quick */
{ 0x0B, 0x00 }, /* 0B Analog Line Loop Quick */
{ 0x0C, 0x00 }, /* 0C Reserved */
{ 0x0D, 0x00 }, /* 0D Input Config */
{ 0x0E, 0x1B }, /* 0E Line Input Level */
{ 0x0F, 0x00 }, /* 0F Line Config */
{ 0x10, 0x14 }, /* 10 Mic1 Input Level */
{ 0x11, 0x14 }, /* 11 Mic2 Input Level */
{ 0x12, 0x00 }, /* 12 Mic Bias Voltage */
{ 0x13, 0x00 }, /* 13 Digital Mic Config */
{ 0x14, 0x00 }, /* 14 Digital Mic Mode */
{ 0x15, 0x00 }, /* 15 Left ADC Mixer */
{ 0x16, 0x00 }, /* 16 Right ADC Mixer */
{ 0x17, 0x03 }, /* 17 Left ADC Level */
{ 0x18, 0x03 }, /* 18 Right ADC Level */
{ 0x19, 0x00 }, /* 19 ADC Biquad Level */
{ 0x1A, 0x00 }, /* 1A ADC Sidetone */
{ 0x1B, 0x00 }, /* 1B System Clock */
{ 0x1C, 0x00 }, /* 1C Clock Mode */
{ 0x1D, 0x00 }, /* 1D Any Clock 1 */
{ 0x1E, 0x00 }, /* 1E Any Clock 2 */
{ 0x1F, 0x00 }, /* 1F Any Clock 3 */
{ 0x20, 0x00 }, /* 20 Any Clock 4 */
{ 0x21, 0x00 }, /* 21 Master Mode */
{ 0x22, 0x00 }, /* 22 Interface Format */
{ 0x23, 0x00 }, /* 23 TDM Format 1*/
{ 0x24, 0x00 }, /* 24 TDM Format 2*/
{ 0x25, 0x00 }, /* 25 I/O Configuration */
{ 0x26, 0x80 }, /* 26 Filter Config */
{ 0x27, 0x00 }, /* 27 DAI Playback Level */
{ 0x28, 0x00 }, /* 28 EQ Playback Level */
{ 0x29, 0x00 }, /* 29 Left HP Mixer */
{ 0x2A, 0x00 }, /* 2A Right HP Mixer */
{ 0x2B, 0x00 }, /* 2B HP Control */
{ 0x2C, 0x1A }, /* 2C Left HP Volume */
{ 0x2D, 0x1A }, /* 2D Right HP Volume */
{ 0x2E, 0x00 }, /* 2E Left Spk Mixer */
{ 0x2F, 0x00 }, /* 2F Right Spk Mixer */
{ 0x30, 0x00 }, /* 30 Spk Control */
{ 0x31, 0x2C }, /* 31 Left Spk Volume */
{ 0x32, 0x2C }, /* 32 Right Spk Volume */
{ 0x33, 0x00 }, /* 33 ALC Timing */
{ 0x34, 0x00 }, /* 34 ALC Compressor */
{ 0x35, 0x00 }, /* 35 ALC Expander */
{ 0x36, 0x00 }, /* 36 ALC Gain */
{ 0x37, 0x00 }, /* 37 Rcv/Line OutL Mixer */
{ 0x38, 0x00 }, /* 38 Rcv/Line OutL Control */
{ 0x39, 0x15 }, /* 39 Rcv/Line OutL Volume */
{ 0x3A, 0x00 }, /* 3A Line OutR Mixer */
{ 0x3B, 0x00 }, /* 3B Line OutR Control */
{ 0x3C, 0x15 }, /* 3C Line OutR Volume */
{ 0x3D, 0x00 }, /* 3D Jack Detect */
{ 0x3E, 0x00 }, /* 3E Input Enable */
{ 0x3F, 0x00 }, /* 3F Output Enable */
{ 0x40, 0x00 }, /* 40 Level Control */
{ 0x41, 0x00 }, /* 41 DSP Filter Enable */
{ 0x42, 0x00 }, /* 42 Bias Control */
{ 0x43, 0x00 }, /* 43 DAC Control */
{ 0x44, 0x06 }, /* 44 ADC Control */
{ 0x45, 0x00 }, /* 45 Device Shutdown */
{ 0x46, 0x00 }, /* 46 Equalizer Band 1 Coefficient B0 */
{ 0x47, 0x00 }, /* 47 Equalizer Band 1 Coefficient B0 */
{ 0x48, 0x00 }, /* 48 Equalizer Band 1 Coefficient B0 */
{ 0x49, 0x00 }, /* 49 Equalizer Band 1 Coefficient B1 */
{ 0x4A, 0x00 }, /* 4A Equalizer Band 1 Coefficient B1 */
{ 0x4B, 0x00 }, /* 4B Equalizer Band 1 Coefficient B1 */
{ 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */
{ 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */
{ 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */
{ 0x4F, 0x00 }, /* 4F Equalizer Band 1 Coefficient A1 */
{ 0x50, 0x00 }, /* 50 Equalizer Band 1 Coefficient A1 */
{ 0x51, 0x00 }, /* 51 Equalizer Band 1 Coefficient A1 */
{ 0x52, 0x00 }, /* 52 Equalizer Band 1 Coefficient A2 */
{ 0x53, 0x00 }, /* 53 Equalizer Band 1 Coefficient A2 */
{ 0x54, 0x00 }, /* 54 Equalizer Band 1 Coefficient A2 */
{ 0x55, 0x00 }, /* 55 Equalizer Band 2 Coefficient B0 */
{ 0x56, 0x00 }, /* 56 Equalizer Band 2 Coefficient B0 */
{ 0x57, 0x00 }, /* 57 Equalizer Band 2 Coefficient B0 */
{ 0x58, 0x00 }, /* 58 Equalizer Band 2 Coefficient B1 */
{ 0x59, 0x00 }, /* 59 Equalizer Band 2 Coefficient B1 */
{ 0x5A, 0x00 }, /* 5A Equalizer Band 2 Coefficient B1 */
{ 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */
{ 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */
{ 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */
{ 0x5E, 0x00 }, /* 5E Equalizer Band 2 Coefficient A1 */
{ 0x5F, 0x00 }, /* 5F Equalizer Band 2 Coefficient A1 */
{ 0x60, 0x00 }, /* 60 Equalizer Band 2 Coefficient A1 */
{ 0x61, 0x00 }, /* 61 Equalizer Band 2 Coefficient A2 */
{ 0x62, 0x00 }, /* 62 Equalizer Band 2 Coefficient A2 */
{ 0x63, 0x00 }, /* 63 Equalizer Band 2 Coefficient A2 */
{ 0x64, 0x00 }, /* 64 Equalizer Band 3 Coefficient B0 */
{ 0x65, 0x00 }, /* 65 Equalizer Band 3 Coefficient B0 */
{ 0x66, 0x00 }, /* 66 Equalizer Band 3 Coefficient B0 */
{ 0x67, 0x00 }, /* 67 Equalizer Band 3 Coefficient B1 */
{ 0x68, 0x00 }, /* 68 Equalizer Band 3 Coefficient B1 */
{ 0x69, 0x00 }, /* 69 Equalizer Band 3 Coefficient B1 */
{ 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */
{ 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */
{ 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */
{ 0x6D, 0x00 }, /* 6D Equalizer Band 3 Coefficient A1 */
{ 0x6E, 0x00 }, /* 6E Equalizer Band 3 Coefficient A1 */
{ 0x6F, 0x00 }, /* 6F Equalizer Band 3 Coefficient A1 */
{ 0x70, 0x00 }, /* 70 Equalizer Band 3 Coefficient A2 */
{ 0x71, 0x00 }, /* 71 Equalizer Band 3 Coefficient A2 */
{ 0x72, 0x00 }, /* 72 Equalizer Band 3 Coefficient A2 */
{ 0x73, 0x00 }, /* 73 Equalizer Band 4 Coefficient B0 */
{ 0x74, 0x00 }, /* 74 Equalizer Band 4 Coefficient B0 */
{ 0x75, 0x00 }, /* 75 Equalizer Band 4 Coefficient B0 */
{ 0x76, 0x00 }, /* 76 Equalizer Band 4 Coefficient B1 */
{ 0x77, 0x00 }, /* 77 Equalizer Band 4 Coefficient B1 */
{ 0x78, 0x00 }, /* 78 Equalizer Band 4 Coefficient B1 */
{ 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */
{ 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */
{ 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */
{ 0x7C, 0x00 }, /* 7C Equalizer Band 4 Coefficient A1 */
{ 0x7D, 0x00 }, /* 7D Equalizer Band 4 Coefficient A1 */
{ 0x7E, 0x00 }, /* 7E Equalizer Band 4 Coefficient A1 */
{ 0x7F, 0x00 }, /* 7F Equalizer Band 4 Coefficient A2 */
{ 0x80, 0x00 }, /* 80 Equalizer Band 4 Coefficient A2 */
{ 0x81, 0x00 }, /* 81 Equalizer Band 4 Coefficient A2 */
{ 0x82, 0x00 }, /* 82 Equalizer Band 5 Coefficient B0 */
{ 0x83, 0x00 }, /* 83 Equalizer Band 5 Coefficient B0 */
{ 0x84, 0x00 }, /* 84 Equalizer Band 5 Coefficient B0 */
{ 0x85, 0x00 }, /* 85 Equalizer Band 5 Coefficient B1 */
{ 0x86, 0x00 }, /* 86 Equalizer Band 5 Coefficient B1 */
{ 0x87, 0x00 }, /* 87 Equalizer Band 5 Coefficient B1 */
{ 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */
{ 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */
{ 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */
{ 0x8B, 0x00 }, /* 8B Equalizer Band 5 Coefficient A1 */
{ 0x8C, 0x00 }, /* 8C Equalizer Band 5 Coefficient A1 */
{ 0x8D, 0x00 }, /* 8D Equalizer Band 5 Coefficient A1 */
{ 0x8E, 0x00 }, /* 8E Equalizer Band 5 Coefficient A2 */
{ 0x8F, 0x00 }, /* 8F Equalizer Band 5 Coefficient A2 */
{ 0x90, 0x00 }, /* 90 Equalizer Band 5 Coefficient A2 */
{ 0x91, 0x00 }, /* 91 Equalizer Band 6 Coefficient B0 */
{ 0x92, 0x00 }, /* 92 Equalizer Band 6 Coefficient B0 */
{ 0x93, 0x00 }, /* 93 Equalizer Band 6 Coefficient B0 */
{ 0x94, 0x00 }, /* 94 Equalizer Band 6 Coefficient B1 */
{ 0x95, 0x00 }, /* 95 Equalizer Band 6 Coefficient B1 */
{ 0x96, 0x00 }, /* 96 Equalizer Band 6 Coefficient B1 */
{ 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */
{ 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */
{ 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */
{ 0x9A, 0x00 }, /* 9A Equalizer Band 6 Coefficient A1 */
{ 0x9B, 0x00 }, /* 9B Equalizer Band 6 Coefficient A1 */
{ 0x9C, 0x00 }, /* 9C Equalizer Band 6 Coefficient A1 */
{ 0x9D, 0x00 }, /* 9D Equalizer Band 6 Coefficient A2 */
{ 0x9E, 0x00 }, /* 9E Equalizer Band 6 Coefficient A2 */
{ 0x9F, 0x00 }, /* 9F Equalizer Band 6 Coefficient A2 */
{ 0xA0, 0x00 }, /* A0 Equalizer Band 7 Coefficient B0 */
{ 0xA1, 0x00 }, /* A1 Equalizer Band 7 Coefficient B0 */
{ 0xA2, 0x00 }, /* A2 Equalizer Band 7 Coefficient B0 */
{ 0xA3, 0x00 }, /* A3 Equalizer Band 7 Coefficient B1 */
{ 0xA4, 0x00 }, /* A4 Equalizer Band 7 Coefficient B1 */
{ 0xA5, 0x00 }, /* A5 Equalizer Band 7 Coefficient B1 */
{ 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */
{ 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */
{ 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */
{ 0xA9, 0x00 }, /* A9 Equalizer Band 7 Coefficient A1 */
{ 0xAA, 0x00 }, /* AA Equalizer Band 7 Coefficient A1 */
{ 0xAB, 0x00 }, /* AB Equalizer Band 7 Coefficient A1 */
{ 0xAC, 0x00 }, /* AC Equalizer Band 7 Coefficient A2 */
{ 0xAD, 0x00 }, /* AD Equalizer Band 7 Coefficient A2 */
{ 0xAE, 0x00 }, /* AE Equalizer Band 7 Coefficient A2 */
{ 0xAF, 0x00 }, /* AF ADC Biquad Coefficient B0 */
{ 0xB0, 0x00 }, /* B0 ADC Biquad Coefficient B0 */
{ 0xB1, 0x00 }, /* B1 ADC Biquad Coefficient B0 */
{ 0xB2, 0x00 }, /* B2 ADC Biquad Coefficient B1 */
{ 0xB3, 0x00 }, /* B3 ADC Biquad Coefficient B1 */
{ 0xB4, 0x00 }, /* B4 ADC Biquad Coefficient B1 */
{ 0xB5, 0x00 }, /* B5 ADC Biquad Coefficient B2 */
{ 0xB6, 0x00 }, /* B6 ADC Biquad Coefficient B2 */
{ 0xB7, 0x00 }, /* B7 ADC Biquad Coefficient B2 */
{ 0xB8, 0x00 }, /* B8 ADC Biquad Coefficient A1 */
{ 0xB9, 0x00 }, /* B9 ADC Biquad Coefficient A1 */
{ 0xBA, 0x00 }, /* BA ADC Biquad Coefficient A1 */
{ 0xBB, 0x00 }, /* BB ADC Biquad Coefficient A2 */
{ 0xBC, 0x00 }, /* BC ADC Biquad Coefficient A2 */
{ 0xBD, 0x00 }, /* BD ADC Biquad Coefficient A2 */
{ 0xBE, 0x00 }, /* BE Digital Mic 3 Volume */
{ 0xBF, 0x00 }, /* BF Digital Mic 4 Volume */
{ 0xC0, 0x00 }, /* C0 Digital Mic 34 Biquad Pre Atten */
{ 0xC1, 0x00 }, /* C1 Record TDM Slot */
{ 0xC2, 0x00 }, /* C2 Sample Rate */
{ 0xC3, 0x00 }, /* C3 Digital Mic 34 Biquad Coefficient C3 */
{ 0xC4, 0x00 }, /* C4 Digital Mic 34 Biquad Coefficient C4 */
{ 0xC5, 0x00 }, /* C5 Digital Mic 34 Biquad Coefficient C5 */
{ 0xC6, 0x00 }, /* C6 Digital Mic 34 Biquad Coefficient C6 */
{ 0xC7, 0x00 }, /* C7 Digital Mic 34 Biquad Coefficient C7 */
{ 0xC8, 0x00 }, /* C8 Digital Mic 34 Biquad Coefficient C8 */
{ 0xC9, 0x00 }, /* C9 Digital Mic 34 Biquad Coefficient C9 */
{ 0xCA, 0x00 }, /* CA Digital Mic 34 Biquad Coefficient CA */
{ 0xCB, 0x00 }, /* CB Digital Mic 34 Biquad Coefficient CB */
{ 0xCC, 0x00 }, /* CC Digital Mic 34 Biquad Coefficient CC */
{ 0xCD, 0x00 }, /* CD Digital Mic 34 Biquad Coefficient CD */
{ 0xCE, 0x00 }, /* CE Digital Mic 34 Biquad Coefficient CE */
{ 0xCF, 0x00 }, /* CF Digital Mic 34 Biquad Coefficient CF */
{ 0xD0, 0x00 }, /* D0 Digital Mic 34 Biquad Coefficient D0 */
{ 0xD1, 0x00 }, /* D1 Digital Mic 34 Biquad Coefficient D1 */
};
static bool max98090_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case M98090_REG_SOFTWARE_RESET:
case M98090_REG_DEVICE_STATUS:
case M98090_REG_JACK_STATUS:
case M98090_REG_REVISION_ID:
return true;
default:
return false;
}
}
static bool max98090_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case M98090_REG_DEVICE_STATUS ... M98090_REG_INTERRUPT_S:
case M98090_REG_LINE_INPUT_CONFIG ... 0xD1:
case M98090_REG_REVISION_ID:
return true;
default:
return false;
}
}
static int max98090_reset(struct max98090_priv *max98090)
{
int ret;
/* Reset the codec by writing to this write-only reset register */
ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET,
M98090_SWRESET_MASK);
if (ret < 0) {
dev_err(max98090->component->dev,
"Failed to reset codec: %d\n", ret);
return ret;
}
msleep(20);
return ret;
}
static const DECLARE_TLV_DB_RANGE(max98090_micboost_tlv,
0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0)
);
static const DECLARE_TLV_DB_SCALE(max98090_mic_tlv, 0, 100, 0);
static const DECLARE_TLV_DB_SCALE(max98090_line_single_ended_tlv,
-600, 600, 0);
static const DECLARE_TLV_DB_RANGE(max98090_line_tlv,
0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0),
4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0)
);
static const DECLARE_TLV_DB_SCALE(max98090_avg_tlv, 0, 600, 0);
static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0);
static const DECLARE_TLV_DB_SCALE(max98090_dvg_tlv, 0, 600, 0);
static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0);
static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv, 0, 100, 0);
static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0);
static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0);
static const DECLARE_TLV_DB_SCALE(max98090_sdg_tlv, 50, 200, 0);
static const DECLARE_TLV_DB_RANGE(max98090_mixout_tlv,
0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0),
2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0)
);
static const DECLARE_TLV_DB_RANGE(max98090_hp_tlv,
0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
28, 31, TLV_DB_SCALE_ITEM(150, 50, 0)
);
static const DECLARE_TLV_DB_RANGE(max98090_spk_tlv,
0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0),
5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0),
11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0),
15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0),
30, 39, TLV_DB_SCALE_ITEM(950, 50, 0)
);
static const DECLARE_TLV_DB_RANGE(max98090_rcv_lout_tlv,
0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
28, 31, TLV_DB_SCALE_ITEM(650, 50, 0)
);
static int max98090_get_enab_tlv(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
unsigned int mask = (1 << fls(mc->max)) - 1;
unsigned int val = snd_soc_component_read(component, mc->reg);
unsigned int *select;
switch (mc->reg) {
case M98090_REG_MIC1_INPUT_LEVEL:
select = &(max98090->pa1en);
break;
case M98090_REG_MIC2_INPUT_LEVEL:
select = &(max98090->pa2en);
break;
case M98090_REG_ADC_SIDETONE:
select = &(max98090->sidetone);
break;
default:
return -EINVAL;
}
val = (val >> mc->shift) & mask;
if (val >= 1) {
/* If on, return the volume */
val = val - 1;
*select = val;
} else {
/* If off, return last stored value */
val = *select;
}
ucontrol->value.integer.value[0] = val;
return 0;
}
static int max98090_put_enab_tlv(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
unsigned int mask = (1 << fls(mc->max)) - 1;
int sel_unchecked = ucontrol->value.integer.value[0];
unsigned int sel;
unsigned int val = snd_soc_component_read(component, mc->reg);
unsigned int *select;
int change;
switch (mc->reg) {
case M98090_REG_MIC1_INPUT_LEVEL:
select = &(max98090->pa1en);
break;
case M98090_REG_MIC2_INPUT_LEVEL:
select = &(max98090->pa2en);
break;
case M98090_REG_ADC_SIDETONE:
select = &(max98090->sidetone);
break;
default:
return -EINVAL;
}
val = (val >> mc->shift) & mask;
if (sel_unchecked < 0 || sel_unchecked > mc->max)
return -EINVAL;
sel = sel_unchecked;
change = *select != sel;
*select = sel;
/* Setting a volume is only valid if it is already On */
if (val >= 1) {
sel = sel + 1;
} else {
/* Write what was already there */
sel = val;
}
snd_soc_component_update_bits(component, mc->reg,
mask << mc->shift,
sel << mc->shift);
return change;
}
static const char *max98090_perf_pwr_text[] =
{ "High Performance", "Low Power" };
static const char *max98090_pwr_perf_text[] =
{ "Low Power", "High Performance" };
static SOC_ENUM_SINGLE_DECL(max98090_vcmbandgap_enum,
M98090_REG_BIAS_CONTROL,
M98090_VCM_MODE_SHIFT,
max98090_pwr_perf_text);
static const char *max98090_osr128_text[] = { "64*fs", "128*fs" };
static SOC_ENUM_SINGLE_DECL(max98090_osr128_enum,
M98090_REG_ADC_CONTROL,
M98090_OSR128_SHIFT,
max98090_osr128_text);
static const char *max98090_mode_text[] = { "Voice", "Music" };
static SOC_ENUM_SINGLE_DECL(max98090_mode_enum,
M98090_REG_FILTER_CONFIG,
M98090_MODE_SHIFT,
max98090_mode_text);
static SOC_ENUM_SINGLE_DECL(max98090_filter_dmic34mode_enum,
M98090_REG_FILTER_CONFIG,
M98090_FLT_DMIC34MODE_SHIFT,
max98090_mode_text);
static const char *max98090_drcatk_text[] =
{ "0.5ms", "1ms", "5ms", "10ms", "25ms", "50ms", "100ms", "200ms" };
static SOC_ENUM_SINGLE_DECL(max98090_drcatk_enum,
M98090_REG_DRC_TIMING,
M98090_DRCATK_SHIFT,
max98090_drcatk_text);
static const char *max98090_drcrls_text[] =
{ "8s", "4s", "2s", "1s", "0.5s", "0.25s", "0.125s", "0.0625s" };
static SOC_ENUM_SINGLE_DECL(max98090_drcrls_enum,
M98090_REG_DRC_TIMING,
M98090_DRCRLS_SHIFT,
max98090_drcrls_text);
static const char *max98090_alccmp_text[] =
{ "1:1", "1:1.5", "1:2", "1:4", "1:INF" };
static SOC_ENUM_SINGLE_DECL(max98090_alccmp_enum,
M98090_REG_DRC_COMPRESSOR,
M98090_DRCCMP_SHIFT,
max98090_alccmp_text);
static const char *max98090_drcexp_text[] = { "1:1", "2:1", "3:1" };
static SOC_ENUM_SINGLE_DECL(max98090_drcexp_enum,
M98090_REG_DRC_EXPANDER,
M98090_DRCEXP_SHIFT,
max98090_drcexp_text);
static SOC_ENUM_SINGLE_DECL(max98090_dac_perfmode_enum,
M98090_REG_DAC_CONTROL,
M98090_PERFMODE_SHIFT,
max98090_perf_pwr_text);
static SOC_ENUM_SINGLE_DECL(max98090_dachp_enum,
M98090_REG_DAC_CONTROL,
M98090_DACHP_SHIFT,
max98090_pwr_perf_text);
static SOC_ENUM_SINGLE_DECL(max98090_adchp_enum,
M98090_REG_ADC_CONTROL,
M98090_ADCHP_SHIFT,
max98090_pwr_perf_text);
static const struct snd_kcontrol_new max98090_snd_controls[] = {
SOC_ENUM("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum),
SOC_SINGLE("DMIC MIC Comp Filter Config", M98090_REG_DIGITAL_MIC_CONFIG,
M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0),
SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT,
M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv,
max98090_put_enab_tlv, max98090_micboost_tlv),
SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT,
M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv,
max98090_put_enab_tlv, max98090_micboost_tlv),
SOC_SINGLE_TLV("MIC1 Volume", M98090_REG_MIC1_INPUT_LEVEL,
M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1,
max98090_mic_tlv),
SOC_SINGLE_TLV("MIC2 Volume", M98090_REG_MIC2_INPUT_LEVEL,
M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1,
max98090_mic_tlv),
SOC_SINGLE_RANGE_TLV("LINEA Single Ended Volume",
M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG135_SHIFT, 0,
M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv),
SOC_SINGLE_RANGE_TLV("LINEB Single Ended Volume",
M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG246_SHIFT, 0,
M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv),
SOC_SINGLE_RANGE_TLV("LINEA Volume", M98090_REG_LINE_INPUT_LEVEL,
M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1,
max98090_line_tlv),
SOC_SINGLE_RANGE_TLV("LINEB Volume", M98090_REG_LINE_INPUT_LEVEL,
M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1,
max98090_line_tlv),
SOC_SINGLE("LINEA Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0),
SOC_SINGLE("LINEB Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0),
SOC_SINGLE_TLV("ADCL Boost Volume", M98090_REG_LEFT_ADC_LEVEL,
M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0,
max98090_avg_tlv),
SOC_SINGLE_TLV("ADCR Boost Volume", M98090_REG_RIGHT_ADC_LEVEL,
M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0,
max98090_avg_tlv),
SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL,
M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1,
max98090_av_tlv),
SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL,
M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1,
max98090_av_tlv),
SOC_ENUM("ADC Oversampling Rate", max98090_osr128_enum),
SOC_SINGLE("ADC Quantizer Dither", M98090_REG_ADC_CONTROL,
M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0),
SOC_ENUM("ADC High Performance Mode", max98090_adchp_enum),
SOC_SINGLE("DAC Mono Mode", M98090_REG_IO_CONFIGURATION,
M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0),
SOC_SINGLE("SDIN Mode", M98090_REG_IO_CONFIGURATION,
M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0),
SOC_SINGLE("SDOUT Mode", M98090_REG_IO_CONFIGURATION,
M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0),
SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION,
M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1),
SOC_ENUM("Filter Mode", max98090_mode_enum),
SOC_SINGLE("Record Path DC Blocking", M98090_REG_FILTER_CONFIG,
M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0),
SOC_SINGLE("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG,
M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0),
SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL,
M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv),
SOC_SINGLE_EXT_TLV("Digital Sidetone Volume",
M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT,
M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv,
max98090_put_enab_tlv, max98090_sdg_tlv),
SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0,
max98090_dvg_tlv),
SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
M98090_DV_SHIFT, M98090_DV_NUM - 1, 1,
max98090_dv_tlv),
SND_SOC_BYTES("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105),
SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0),
SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0),
SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0),
SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1,
1),
SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1,
max98090_dv_tlv),
SOC_SINGLE("ALC Enable", M98090_REG_DRC_TIMING,
M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0),
SOC_ENUM("ALC Attack Time", max98090_drcatk_enum),
SOC_ENUM("ALC Release Time", max98090_drcrls_enum),
SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN,
M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0,
max98090_alcmakeup_tlv),
SOC_ENUM("ALC Compression Ratio", max98090_alccmp_enum),
SOC_ENUM("ALC Expansion Ratio", max98090_drcexp_enum),
SOC_SINGLE_TLV("ALC Compression Threshold Volume",
M98090_REG_DRC_COMPRESSOR, M98090_DRCTHC_SHIFT,
M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv),
SOC_SINGLE_TLV("ALC Expansion Threshold Volume",
M98090_REG_DRC_EXPANDER, M98090_DRCTHE_SHIFT,
M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv),
SOC_ENUM("DAC HP Playback Performance Mode",
max98090_dac_perfmode_enum),
SOC_ENUM("DAC High Performance Mode", max98090_dachp_enum),
SOC_SINGLE_TLV("Headphone Left Mixer Volume",
M98090_REG_HP_CONTROL, M98090_MIXHPLG_SHIFT,
M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv),
SOC_SINGLE_TLV("Headphone Right Mixer Volume",
M98090_REG_HP_CONTROL, M98090_MIXHPRG_SHIFT,
M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv),
SOC_SINGLE_TLV("Speaker Left Mixer Volume",
M98090_REG_SPK_CONTROL, M98090_MIXSPLG_SHIFT,
M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv),
SOC_SINGLE_TLV("Speaker Right Mixer Volume",
M98090_REG_SPK_CONTROL, M98090_MIXSPRG_SHIFT,
M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv),
SOC_SINGLE_TLV("Receiver Left Mixer Volume",
M98090_REG_RCV_LOUTL_CONTROL, M98090_MIXRCVLG_SHIFT,
M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv),
SOC_SINGLE_TLV("Receiver Right Mixer Volume",
M98090_REG_LOUTR_CONTROL, M98090_MIXRCVRG_SHIFT,
M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv),
SOC_DOUBLE_R_TLV("Headphone Volume", M98090_REG_LEFT_HP_VOLUME,
M98090_REG_RIGHT_HP_VOLUME, M98090_HPVOLL_SHIFT,
M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv),
SOC_DOUBLE_R_RANGE_TLV("Speaker Volume",
M98090_REG_LEFT_SPK_VOLUME, M98090_REG_RIGHT_SPK_VOLUME,
M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24,
0, max98090_spk_tlv),
SOC_DOUBLE_R_TLV("Receiver Volume", M98090_REG_RCV_LOUTL_VOLUME,
M98090_REG_LOUTR_VOLUME, M98090_RCVLVOL_SHIFT,
M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv),
SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME,
M98090_HPLM_SHIFT, 1, 1),
SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME,
M98090_HPRM_SHIFT, 1, 1),
SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME,
M98090_SPLM_SHIFT, 1, 1),
SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME,
M98090_SPRM_SHIFT, 1, 1),
SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME,
M98090_RCVLM_SHIFT, 1, 1),
SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME,
M98090_RCVRM_SHIFT, 1, 1),
SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL,
M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1),
SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL,
M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1),
SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL,
M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1),
SND_SOC_BYTES("Biquad Coefficients", M98090_REG_RECORD_BIQUAD_BASE, 15),
SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0),
};
static const struct snd_kcontrol_new max98091_snd_controls[] = {
SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE,
M98090_DMIC34_ZEROPAD_SHIFT,
M98090_DMIC34_ZEROPAD_NUM - 1, 0),
SOC_ENUM("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum),
SOC_SINGLE("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG,
M98090_FLT_DMIC34HPF_SHIFT,
M98090_FLT_DMIC34HPF_NUM - 1, 0),
SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME,
M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0,
max98090_avg_tlv),
SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME,
M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0,
max98090_avg_tlv),
SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME,
M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1,
max98090_av_tlv),
SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME,
M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1,
max98090_av_tlv),
SND_SOC_BYTES("DMIC34 Biquad Coefficients",
M98090_REG_DMIC34_BIQUAD_BASE, 15),
SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0),
SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume",
M98090_REG_DMIC34_BQ_PREATTEN, M98090_AV34BQ_SHIFT,
M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv),
};
static int max98090_micinput_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
unsigned int val = snd_soc_component_read(component, w->reg);
if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
val = (val & M98090_MIC_PA1EN_MASK) >> M98090_MIC_PA1EN_SHIFT;
else
val = (val & M98090_MIC_PA2EN_MASK) >> M98090_MIC_PA2EN_SHIFT;
if (val >= 1) {
if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) {
max98090->pa1en = val - 1; /* Update for volatile */
} else {
max98090->pa2en = val - 1; /* Update for volatile */
}
}
switch (event) {
case SND_SOC_DAPM_POST_PMU:
/* If turning on, set to most recently selected volume */
if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
val = max98090->pa1en + 1;
else
val = max98090->pa2en + 1;
break;
case SND_SOC_DAPM_POST_PMD:
/* If turning off, turn off */
val = 0;
break;
default:
return -EINVAL;
}
if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA1EN_MASK,
val << M98090_MIC_PA1EN_SHIFT);
else
snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA2EN_MASK,
val << M98090_MIC_PA2EN_SHIFT);
return 0;
}
static int max98090_shdn_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
if (event & SND_SOC_DAPM_POST_PMU)
max98090->shdn_pending = true;
return 0;
}
static const char *mic1_mux_text[] = { "IN12", "IN56" };
static SOC_ENUM_SINGLE_DECL(mic1_mux_enum,
M98090_REG_INPUT_MODE,
M98090_EXTMIC1_SHIFT,
mic1_mux_text);
static const struct snd_kcontrol_new max98090_mic1_mux =
SOC_DAPM_ENUM("MIC1 Mux", mic1_mux_enum);
static const char *mic2_mux_text[] = { "IN34", "IN56" };
static SOC_ENUM_SINGLE_DECL(mic2_mux_enum,
M98090_REG_INPUT_MODE,
M98090_EXTMIC2_SHIFT,
mic2_mux_text);
static const struct snd_kcontrol_new max98090_mic2_mux =
SOC_DAPM_ENUM("MIC2 Mux", mic2_mux_enum);
static const char *dmic_mux_text[] = { "ADC", "DMIC" };
static SOC_ENUM_SINGLE_VIRT_DECL(dmic_mux_enum, dmic_mux_text);
static const struct snd_kcontrol_new max98090_dmic_mux =
SOC_DAPM_ENUM("DMIC Mux", dmic_mux_enum);
/* LINEA mixer switch */
static const struct snd_kcontrol_new max98090_linea_mixer_controls[] = {
SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG,
M98090_IN1SEEN_SHIFT, 1, 0),
SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG,
M98090_IN3SEEN_SHIFT, 1, 0),
SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG,
M98090_IN5SEEN_SHIFT, 1, 0),
SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG,
M98090_IN34DIFF_SHIFT, 1, 0),
};
/* LINEB mixer switch */
static const struct snd_kcontrol_new max98090_lineb_mixer_controls[] = {
SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG,
M98090_IN2SEEN_SHIFT, 1, 0),
SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG,
M98090_IN4SEEN_SHIFT, 1, 0),
SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG,
M98090_IN6SEEN_SHIFT, 1, 0),
SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG,
M98090_IN56DIFF_SHIFT, 1, 0),
};
/* Left ADC mixer switch */
static const struct snd_kcontrol_new max98090_left_adc_mixer_controls[] = {
SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER,
M98090_MIXADL_IN12DIFF_SHIFT, 1, 0),
SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER,
M98090_MIXADL_IN34DIFF_SHIFT, 1, 0),
SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER,
M98090_MIXADL_IN65DIFF_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER,
M98090_MIXADL_LINEA_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER,
M98090_MIXADL_LINEB_SHIFT, 1, 0),
SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER,
M98090_MIXADL_MIC1_SHIFT, 1, 0),
SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER,
M98090_MIXADL_MIC2_SHIFT, 1, 0),
};
/* Right ADC mixer switch */
static const struct snd_kcontrol_new max98090_right_adc_mixer_controls[] = {
SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER,
M98090_MIXADR_IN12DIFF_SHIFT, 1, 0),
SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER,
M98090_MIXADR_IN34DIFF_SHIFT, 1, 0),
SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER,
M98090_MIXADR_IN65DIFF_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER,
M98090_MIXADR_LINEA_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER,
M98090_MIXADR_LINEB_SHIFT, 1, 0),
SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER,
M98090_MIXADR_MIC1_SHIFT, 1, 0),
SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER,
M98090_MIXADR_MIC2_SHIFT, 1, 0),
};
static const char *lten_mux_text[] = { "Normal", "Loopthrough" };
static SOC_ENUM_SINGLE_DECL(ltenl_mux_enum,
M98090_REG_IO_CONFIGURATION,
M98090_LTEN_SHIFT,
lten_mux_text);
static SOC_ENUM_SINGLE_DECL(ltenr_mux_enum,
M98090_REG_IO_CONFIGURATION,
M98090_LTEN_SHIFT,
lten_mux_text);
static const struct snd_kcontrol_new max98090_ltenl_mux =
SOC_DAPM_ENUM("LTENL Mux", ltenl_mux_enum);
static const struct snd_kcontrol_new max98090_ltenr_mux =
SOC_DAPM_ENUM("LTENR Mux", ltenr_mux_enum);
static const char *lben_mux_text[] = { "Normal", "Loopback" };
static SOC_ENUM_SINGLE_DECL(lbenl_mux_enum,
M98090_REG_IO_CONFIGURATION,
M98090_LBEN_SHIFT,
lben_mux_text);
static SOC_ENUM_SINGLE_DECL(lbenr_mux_enum,
M98090_REG_IO_CONFIGURATION,
M98090_LBEN_SHIFT,
lben_mux_text);
static const struct snd_kcontrol_new max98090_lbenl_mux =
SOC_DAPM_ENUM("LBENL Mux", lbenl_mux_enum);
static const struct snd_kcontrol_new max98090_lbenr_mux =
SOC_DAPM_ENUM("LBENR Mux", lbenr_mux_enum);
static const char *stenl_mux_text[] = { "Normal", "Sidetone Left" };
static const char *stenr_mux_text[] = { "Normal", "Sidetone Right" };
static SOC_ENUM_SINGLE_DECL(stenl_mux_enum,
M98090_REG_ADC_SIDETONE,
M98090_DSTSL_SHIFT,
stenl_mux_text);
static SOC_ENUM_SINGLE_DECL(stenr_mux_enum,
M98090_REG_ADC_SIDETONE,
M98090_DSTSR_SHIFT,
stenr_mux_text);
static const struct snd_kcontrol_new max98090_stenl_mux =
SOC_DAPM_ENUM("STENL Mux", stenl_mux_enum);
static const struct snd_kcontrol_new max98090_stenr_mux =
SOC_DAPM_ENUM("STENR Mux", stenr_mux_enum);
/* Left speaker mixer switch */
static const struct
snd_kcontrol_new max98090_left_speaker_mixer_controls[] = {
SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER,
M98090_MIXSPL_DACL_SHIFT, 1, 0),
SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER,
M98090_MIXSPL_DACR_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER,
M98090_MIXSPL_LINEA_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER,
M98090_MIXSPL_LINEB_SHIFT, 1, 0),
SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER,
M98090_MIXSPL_MIC1_SHIFT, 1, 0),
SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER,
M98090_MIXSPL_MIC2_SHIFT, 1, 0),
};
/* Right speaker mixer switch */
static const struct
snd_kcontrol_new max98090_right_speaker_mixer_controls[] = {
SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
M98090_MIXSPR_DACL_SHIFT, 1, 0),
SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
M98090_MIXSPR_DACR_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER,
M98090_MIXSPR_LINEA_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER,
M98090_MIXSPR_LINEB_SHIFT, 1, 0),
SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER,
M98090_MIXSPR_MIC1_SHIFT, 1, 0),
SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER,
M98090_MIXSPR_MIC2_SHIFT, 1, 0),
};
/* Left headphone mixer switch */
static const struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = {
SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER,
M98090_MIXHPL_DACL_SHIFT, 1, 0),
SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER,
M98090_MIXHPL_DACR_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER,
M98090_MIXHPL_LINEA_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER,
M98090_MIXHPL_LINEB_SHIFT, 1, 0),
SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER,
M98090_MIXHPL_MIC1_SHIFT, 1, 0),
SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER,
M98090_MIXHPL_MIC2_SHIFT, 1, 0),
};
/* Right headphone mixer switch */
static const struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = {
SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER,
M98090_MIXHPR_DACL_SHIFT, 1, 0),
SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER,
M98090_MIXHPR_DACR_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER,
M98090_MIXHPR_LINEA_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER,
M98090_MIXHPR_LINEB_SHIFT, 1, 0),
SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER,
M98090_MIXHPR_MIC1_SHIFT, 1, 0),
SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER,
M98090_MIXHPR_MIC2_SHIFT, 1, 0),
};
/* Left receiver mixer switch */
static const struct snd_kcontrol_new max98090_left_rcv_mixer_controls[] = {
SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
M98090_MIXRCVL_DACL_SHIFT, 1, 0),
SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
M98090_MIXRCVL_DACR_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER,
M98090_MIXRCVL_LINEA_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER,
M98090_MIXRCVL_LINEB_SHIFT, 1, 0),
SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER,
M98090_MIXRCVL_MIC1_SHIFT, 1, 0),
SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER,
M98090_MIXRCVL_MIC2_SHIFT, 1, 0),
};
/* Right receiver mixer switch */
static const struct snd_kcontrol_new max98090_right_rcv_mixer_controls[] = {
SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER,
M98090_MIXRCVR_DACL_SHIFT, 1, 0),
SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER,
M98090_MIXRCVR_DACR_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER,
M98090_MIXRCVR_LINEA_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER,
M98090_MIXRCVR_LINEB_SHIFT, 1, 0),
SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER,
M98090_MIXRCVR_MIC1_SHIFT, 1, 0),
SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER,
M98090_MIXRCVR_MIC2_SHIFT, 1, 0),
};
static const char *linmod_mux_text[] = { "Left Only", "Left and Right" };
static SOC_ENUM_SINGLE_DECL(linmod_mux_enum,
M98090_REG_LOUTR_MIXER,
M98090_LINMOD_SHIFT,
linmod_mux_text);
static const struct snd_kcontrol_new max98090_linmod_mux =
SOC_DAPM_ENUM("LINMOD Mux", linmod_mux_enum);
static const char *mixhpsel_mux_text[] = { "DAC Only", "HP Mixer" };
/*
* This is a mux as it selects the HP output, but to DAPM it is a Mixer enable
*/
static SOC_ENUM_SINGLE_DECL(mixhplsel_mux_enum,
M98090_REG_HP_CONTROL,
M98090_MIXHPLSEL_SHIFT,
mixhpsel_mux_text);
static const struct snd_kcontrol_new max98090_mixhplsel_mux =
SOC_DAPM_ENUM("MIXHPLSEL Mux", mixhplsel_mux_enum);
static SOC_ENUM_SINGLE_DECL(mixhprsel_mux_enum,
M98090_REG_HP_CONTROL,
M98090_MIXHPRSEL_SHIFT,
mixhpsel_mux_text);
static const struct snd_kcontrol_new max98090_mixhprsel_mux =
SOC_DAPM_ENUM("MIXHPRSEL Mux", mixhprsel_mux_enum);
static const struct snd_soc_dapm_widget max98090_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_INPUT("MIC2"),
SND_SOC_DAPM_INPUT("DMICL"),
SND_SOC_DAPM_INPUT("DMICR"),
SND_SOC_DAPM_INPUT("IN1"),
SND_SOC_DAPM_INPUT("IN2"),
SND_SOC_DAPM_INPUT("IN3"),
SND_SOC_DAPM_INPUT("IN4"),
SND_SOC_DAPM_INPUT("IN5"),
SND_SOC_DAPM_INPUT("IN6"),
SND_SOC_DAPM_INPUT("IN12"),
SND_SOC_DAPM_INPUT("IN34"),
SND_SOC_DAPM_INPUT("IN56"),
SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE,
M98090_MBEN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN,
M98090_SHDNN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION,
M98090_SDIEN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION,
M98090_SDOEN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
M98090_DIGMICL_SHIFT, 0, max98090_shdn_event,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
M98090_DIGMICR_SHIFT, 0, max98090_shdn_event,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG,
M98090_AHPF_SHIFT, 0, NULL, 0),
/*
* Note: Sysclk and misc power supplies are taken care of by SHDN
*/
SND_SOC_DAPM_MUX("MIC1 Mux", SND_SOC_NOPM,
0, 0, &max98090_mic1_mux),
SND_SOC_DAPM_MUX("MIC2 Mux", SND_SOC_NOPM,
0, 0, &max98090_mic2_mux),
SND_SOC_DAPM_MUX("DMIC Mux", SND_SOC_NOPM, 0, 0, &max98090_dmic_mux),
SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL,
M98090_MIC_PA1EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("MIC2 Input", M98090_REG_MIC2_INPUT_LEVEL,
M98090_MIC_PA2EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER("LINEA Mixer", SND_SOC_NOPM, 0, 0,
&max98090_linea_mixer_controls[0],
ARRAY_SIZE(max98090_linea_mixer_controls)),
SND_SOC_DAPM_MIXER("LINEB Mixer", SND_SOC_NOPM, 0, 0,
&max98090_lineb_mixer_controls[0],
ARRAY_SIZE(max98090_lineb_mixer_controls)),
SND_SOC_DAPM_PGA("LINEA Input", M98090_REG_INPUT_ENABLE,
M98090_LINEAEN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("LINEB Input", M98090_REG_INPUT_ENABLE,
M98090_LINEBEN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
&max98090_left_adc_mixer_controls[0],
ARRAY_SIZE(max98090_left_adc_mixer_controls)),
SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
&max98090_right_adc_mixer_controls[0],
ARRAY_SIZE(max98090_right_adc_mixer_controls)),
SND_SOC_DAPM_ADC_E("ADCL", NULL, M98090_REG_INPUT_ENABLE,
M98090_ADLEN_SHIFT, 0, max98090_shdn_event,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_ADC_E("ADCR", NULL, M98090_REG_INPUT_ENABLE,
M98090_ADREN_SHIFT, 0, max98090_shdn_event,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIFOUTR", "HiFi Capture", 1,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_MUX("LBENL Mux", SND_SOC_NOPM,
0, 0, &max98090_lbenl_mux),
SND_SOC_DAPM_MUX("LBENR Mux", SND_SOC_NOPM,
0, 0, &max98090_lbenr_mux),
SND_SOC_DAPM_MUX("LTENL Mux", SND_SOC_NOPM,
0, 0, &max98090_ltenl_mux),
SND_SOC_DAPM_MUX("LTENR Mux", SND_SOC_NOPM,
0, 0, &max98090_ltenr_mux),
SND_SOC_DAPM_MUX("STENL Mux", SND_SOC_NOPM,
0, 0, &max98090_stenl_mux),
SND_SOC_DAPM_MUX("STENR Mux", SND_SOC_NOPM,
0, 0, &max98090_stenr_mux),
SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DACL", NULL, M98090_REG_OUTPUT_ENABLE,
M98090_DALEN_SHIFT, 0),
SND_SOC_DAPM_DAC("DACR", NULL, M98090_REG_OUTPUT_ENABLE,
M98090_DAREN_SHIFT, 0),
SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
&max98090_left_hp_mixer_controls[0],
ARRAY_SIZE(max98090_left_hp_mixer_controls)),
SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
&max98090_right_hp_mixer_controls[0],
ARRAY_SIZE(max98090_right_hp_mixer_controls)),
SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0,
&max98090_left_speaker_mixer_controls[0],
ARRAY_SIZE(max98090_left_speaker_mixer_controls)),
SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0,
&max98090_right_speaker_mixer_controls[0],
ARRAY_SIZE(max98090_right_speaker_mixer_controls)),
SND_SOC_DAPM_MIXER("Left Receiver Mixer", SND_SOC_NOPM, 0, 0,
&max98090_left_rcv_mixer_controls[0],
ARRAY_SIZE(max98090_left_rcv_mixer_controls)),
SND_SOC_DAPM_MIXER("Right Receiver Mixer", SND_SOC_NOPM, 0, 0,
&max98090_right_rcv_mixer_controls[0],
ARRAY_SIZE(max98090_right_rcv_mixer_controls)),
SND_SOC_DAPM_MUX("LINMOD Mux", SND_SOC_NOPM, 0, 0,
&max98090_linmod_mux),
SND_SOC_DAPM_MUX("MIXHPLSEL Mux", SND_SOC_NOPM, 0, 0,
&max98090_mixhplsel_mux),
SND_SOC_DAPM_MUX("MIXHPRSEL Mux", SND_SOC_NOPM, 0, 0,
&max98090_mixhprsel_mux),
SND_SOC_DAPM_PGA("HP Left Out", M98090_REG_OUTPUT_ENABLE,
M98090_HPLEN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("HP Right Out", M98090_REG_OUTPUT_ENABLE,
M98090_HPREN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("SPK Left Out", M98090_REG_OUTPUT_ENABLE,
M98090_SPLEN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("SPK Right Out", M98090_REG_OUTPUT_ENABLE,
M98090_SPREN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("RCV Left Out", M98090_REG_OUTPUT_ENABLE,
M98090_RCVLEN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("RCV Right Out", M98090_REG_OUTPUT_ENABLE,
M98090_RCVREN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("HPL"),
SND_SOC_DAPM_OUTPUT("HPR"),
SND_SOC_DAPM_OUTPUT("SPKL"),
SND_SOC_DAPM_OUTPUT("SPKR"),
SND_SOC_DAPM_OUTPUT("RCVL"),
SND_SOC_DAPM_OUTPUT("RCVR"),
};
static const struct snd_soc_dapm_widget max98091_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("DMIC3"),
SND_SOC_DAPM_INPUT("DMIC4"),
SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
M98090_DIGMIC3_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
M98090_DIGMIC4_SHIFT, 0, NULL, 0),
};
static const struct snd_soc_dapm_route max98090_dapm_routes[] = {
{"MIC1 Input", NULL, "MIC1"},
{"MIC2 Input", NULL, "MIC2"},
{"DMICL", NULL, "DMICL_ENA"},
{"DMICL", NULL, "DMICR_ENA"},
{"DMICR", NULL, "DMICL_ENA"},
{"DMICR", NULL, "DMICR_ENA"},
{"DMICL", NULL, "AHPF"},
{"DMICR", NULL, "AHPF"},
/* MIC1 input mux */
{"MIC1 Mux", "IN12", "IN12"},
{"MIC1 Mux", "IN56", "IN56"},
/* MIC2 input mux */
{"MIC2 Mux", "IN34", "IN34"},
{"MIC2 Mux", "IN56", "IN56"},
{"MIC1 Input", NULL, "MIC1 Mux"},
{"MIC2 Input", NULL, "MIC2 Mux"},
/* Left ADC input mixer */
{"Left ADC Mixer", "IN12 Switch", "IN12"},
{"Left ADC Mixer", "IN34 Switch", "IN34"},
{"Left ADC Mixer", "IN56 Switch", "IN56"},
{"Left ADC Mixer", "LINEA Switch", "LINEA Input"},
{"Left ADC Mixer", "LINEB Switch", "LINEB Input"},
{"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
{"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
/* Right ADC input mixer */
{"Right ADC Mixer", "IN12 Switch", "IN12"},
{"Right ADC Mixer", "IN34 Switch", "IN34"},
{"Right ADC Mixer", "IN56 Switch", "IN56"},
{"Right ADC Mixer", "LINEA Switch", "LINEA Input"},
{"Right ADC Mixer", "LINEB Switch", "LINEB Input"},
{"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
{"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
/* Line A input mixer */
{"LINEA Mixer", "IN1 Switch", "IN1"},
{"LINEA Mixer", "IN3 Switch", "IN3"},
{"LINEA Mixer", "IN5 Switch", "IN5"},
{"LINEA Mixer", "IN34 Switch", "IN34"},
/* Line B input mixer */
{"LINEB Mixer", "IN2 Switch", "IN2"},
{"LINEB Mixer", "IN4 Switch", "IN4"},
{"LINEB Mixer", "IN6 Switch", "IN6"},
{"LINEB Mixer", "IN56 Switch", "IN56"},
{"LINEA Input", NULL, "LINEA Mixer"},
{"LINEB Input", NULL, "LINEB Mixer"},
/* Inputs */
{"ADCL", NULL, "Left ADC Mixer"},
{"ADCR", NULL, "Right ADC Mixer"},
{"ADCL", NULL, "SHDN"},
{"ADCR", NULL, "SHDN"},
{"DMIC Mux", "ADC", "ADCL"},
{"DMIC Mux", "ADC", "ADCR"},
{"DMIC Mux", "DMIC", "DMICL"},
{"DMIC Mux", "DMIC", "DMICR"},
{"LBENL Mux", "Normal", "DMIC Mux"},
{"LBENL Mux", "Loopback", "LTENL Mux"},
{"LBENR Mux", "Normal", "DMIC Mux"},
{"LBENR Mux", "Loopback", "LTENR Mux"},
{"AIFOUTL", NULL, "LBENL Mux"},
{"AIFOUTR", NULL, "LBENR Mux"},
{"AIFOUTL", NULL, "SHDN"},
{"AIFOUTR", NULL, "SHDN"},
{"AIFOUTL", NULL, "SDOEN"},
{"AIFOUTR", NULL, "SDOEN"},
{"LTENL Mux", "Normal", "AIFINL"},
{"LTENL Mux", "Loopthrough", "LBENL Mux"},
{"LTENR Mux", "Normal", "AIFINR"},
{"LTENR Mux", "Loopthrough", "LBENR Mux"},
{"DACL", NULL, "LTENL Mux"},
{"DACR", NULL, "LTENR Mux"},
{"STENL Mux", "Sidetone Left", "ADCL"},
{"STENL Mux", "Sidetone Left", "DMICL"},
{"STENR Mux", "Sidetone Right", "ADCR"},
{"STENR Mux", "Sidetone Right", "DMICR"},
{"DACL", NULL, "STENL Mux"},
{"DACR", NULL, "STENR Mux"},
{"AIFINL", NULL, "SHDN"},
{"AIFINR", NULL, "SHDN"},
{"AIFINL", NULL, "SDIEN"},
{"AIFINR", NULL, "SDIEN"},
{"DACL", NULL, "SHDN"},
{"DACR", NULL, "SHDN"},
/* Left headphone output mixer */
{"Left Headphone Mixer", "Left DAC Switch", "DACL"},
{"Left Headphone Mixer", "Right DAC Switch", "DACR"},
{"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
{"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
{"Left Headphone Mixer", "LINEA Switch", "LINEA Input"},
{"Left Headphone Mixer", "LINEB Switch", "LINEB Input"},
/* Right headphone output mixer */
{"Right Headphone Mixer", "Left DAC Switch", "DACL"},
{"Right Headphone Mixer", "Right DAC Switch", "DACR"},
{"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
{"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
{"Right Headphone Mixer", "LINEA Switch", "LINEA Input"},
{"Right Headphone Mixer", "LINEB Switch", "LINEB Input"},
/* Left speaker output mixer */
{"Left Speaker Mixer", "Left DAC Switch", "DACL"},
{"Left Speaker Mixer", "Right DAC Switch", "DACR"},
{"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
{"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
{"Left Speaker Mixer", "LINEA Switch", "LINEA Input"},
{"Left Speaker Mixer", "LINEB Switch", "LINEB Input"},
/* Right speaker output mixer */
{"Right Speaker Mixer", "Left DAC Switch", "DACL"},
{"Right Speaker Mixer", "Right DAC Switch", "DACR"},
{"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
{"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
{"Right Speaker Mixer", "LINEA Switch", "LINEA Input"},
{"Right Speaker Mixer", "LINEB Switch", "LINEB Input"},
/* Left Receiver output mixer */
{"Left Receiver Mixer", "Left DAC Switch", "DACL"},
{"Left Receiver Mixer", "Right DAC Switch", "DACR"},
{"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
{"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
{"Left Receiver Mixer", "LINEA Switch", "LINEA Input"},
{"Left Receiver Mixer", "LINEB Switch", "LINEB Input"},
/* Right Receiver output mixer */
{"Right Receiver Mixer", "Left DAC Switch", "DACL"},
{"Right Receiver Mixer", "Right DAC Switch", "DACR"},
{"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
{"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
{"Right Receiver Mixer", "LINEA Switch", "LINEA Input"},
{"Right Receiver Mixer", "LINEB Switch", "LINEB Input"},
{"MIXHPLSEL Mux", "HP Mixer", "Left Headphone Mixer"},
/*
* Disable this for lowest power if bypassing
* the DAC with an analog signal
*/
{"HP Left Out", NULL, "DACL"},
{"HP Left Out", NULL, "MIXHPLSEL Mux"},
{"MIXHPRSEL Mux", "HP Mixer", "Right Headphone Mixer"},
/*
* Disable this for lowest power if bypassing
* the DAC with an analog signal
*/
{"HP Right Out", NULL, "DACR"},
{"HP Right Out", NULL, "MIXHPRSEL Mux"},
{"SPK Left Out", NULL, "Left Speaker Mixer"},
{"SPK Right Out", NULL, "Right Speaker Mixer"},
{"RCV Left Out", NULL, "Left Receiver Mixer"},
{"LINMOD Mux", "Left and Right", "Right Receiver Mixer"},
{"LINMOD Mux", "Left Only", "Left Receiver Mixer"},
{"RCV Right Out", NULL, "LINMOD Mux"},
{"HPL", NULL, "HP Left Out"},
{"HPR", NULL, "HP Right Out"},
{"SPKL", NULL, "SPK Left Out"},
{"SPKR", NULL, "SPK Right Out"},
{"RCVL", NULL, "RCV Left Out"},
{"RCVR", NULL, "RCV Right Out"},
};
static const struct snd_soc_dapm_route max98091_dapm_routes[] = {
/* DMIC inputs */
{"DMIC3", NULL, "DMIC3_ENA"},
{"DMIC4", NULL, "DMIC4_ENA"},
{"DMIC3", NULL, "AHPF"},
{"DMIC4", NULL, "AHPF"},
};
static int max98090_add_widgets(struct snd_soc_component *component)
{
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
snd_soc_add_component_controls(component, max98090_snd_controls,
ARRAY_SIZE(max98090_snd_controls));
if (max98090->devtype == MAX98091) {
snd_soc_add_component_controls(component, max98091_snd_controls,
ARRAY_SIZE(max98091_snd_controls));
}
snd_soc_dapm_new_controls(dapm, max98090_dapm_widgets,
ARRAY_SIZE(max98090_dapm_widgets));
snd_soc_dapm_add_routes(dapm, max98090_dapm_routes,
ARRAY_SIZE(max98090_dapm_routes));
if (max98090->devtype == MAX98091) {
snd_soc_dapm_new_controls(dapm, max98091_dapm_widgets,
ARRAY_SIZE(max98091_dapm_widgets));
snd_soc_dapm_add_routes(dapm, max98091_dapm_routes,
ARRAY_SIZE(max98091_dapm_routes));
}
return 0;
}
static const int pclk_rates[] = {
12000000, 12000000, 13000000, 13000000,
16000000, 16000000, 19200000, 19200000
};
static const int lrclk_rates[] = {
8000, 16000, 8000, 16000,
8000, 16000, 8000, 16000
};
static const int user_pclk_rates[] = {
13000000, 13000000, 19200000, 19200000,
};
static const int user_lrclk_rates[] = {
44100, 48000, 44100, 48000,
};
static const unsigned long long ni_value[] = {
3528, 768, 441, 8
};
static const unsigned long long mi_value[] = {
8125, 1625, 1500, 25
};
static void max98090_configure_bclk(struct snd_soc_component *component)
{
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
unsigned long long ni;
int i;
if (!max98090->sysclk) {
dev_err(component->dev, "No SYSCLK configured\n");
return;
}
if (!max98090->bclk || !max98090->lrclk) {
dev_err(component->dev, "No audio clocks configured\n");
return;
}
/* Skip configuration when operating as slave */
if (!(snd_soc_component_read(component, M98090_REG_MASTER_MODE) &
M98090_MAS_MASK)) {
return;
}
/* Check for supported PCLK to LRCLK ratios */
for (i = 0; i < ARRAY_SIZE(pclk_rates); i++) {
if ((pclk_rates[i] == max98090->sysclk) &&
(lrclk_rates[i] == max98090->lrclk)) {
dev_dbg(component->dev,
"Found supported PCLK to LRCLK rates 0x%x\n",
i + 0x8);
snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
M98090_FREQ_MASK,
(i + 0x8) << M98090_FREQ_SHIFT);
snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
M98090_USE_M1_MASK, 0);
return;
}
}
/* Check for user calculated MI and NI ratios */
for (i = 0; i < ARRAY_SIZE(user_pclk_rates); i++) {
if ((user_pclk_rates[i] == max98090->sysclk) &&
(user_lrclk_rates[i] == max98090->lrclk)) {
dev_dbg(component->dev,
"Found user supported PCLK to LRCLK rates\n");
dev_dbg(component->dev, "i %d ni %lld mi %lld\n",
i, ni_value[i], mi_value[i]);
snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
M98090_FREQ_MASK, 0);
snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
M98090_USE_M1_MASK,
1 << M98090_USE_M1_SHIFT);
snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_MSB,
(ni_value[i] >> 8) & 0x7F);
snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_LSB,
ni_value[i] & 0xFF);
snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_MI_MSB,
(mi_value[i] >> 8) & 0x7F);
snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_MI_LSB,
mi_value[i] & 0xFF);
return;
}
}
/*
* Calculate based on MI = 65536 (not as good as either method above)
*/
snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
M98090_FREQ_MASK, 0);
snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
M98090_USE_M1_MASK, 0);
/*
* Configure NI when operating as master
* Note: There is a small, but significant audio quality improvement
* by calculating ni and mi.
*/
ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL)
* (unsigned long long int)max98090->lrclk;
do_div(ni, (unsigned long long int)max98090->sysclk);
dev_info(component->dev, "No better method found\n");
dev_info(component->dev, "Calculating ni %lld with mi 65536\n", ni);
snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_MSB,
(ni >> 8) & 0x7F);
snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_LSB, ni & 0xFF);
}
static int max98090_dai_set_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
struct max98090_cdata *cdata;
u8 regval, tdm_regval;
max98090->dai_fmt = fmt;
cdata = &max98090->dai[0];
if (fmt != cdata->fmt) {
cdata->fmt = fmt;
regval = 0;
tdm_regval = 0;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC:
/* Set to consumer mode PLL - MAS mode off */
snd_soc_component_write(component,
M98090_REG_CLOCK_RATIO_NI_MSB, 0x00);
snd_soc_component_write(component,
M98090_REG_CLOCK_RATIO_NI_LSB, 0x00);
snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
M98090_USE_M1_MASK, 0);
max98090->master = false;
break;
case SND_SOC_DAIFMT_CBP_CFP:
/* Set to provider mode */
if (max98090->tdm_slots == 4) {
/* TDM */
regval |= M98090_MAS_MASK |
M98090_BSEL_64;
} else if (max98090->tdm_slots == 3) {
/* TDM */
regval |= M98090_MAS_MASK |
M98090_BSEL_48;
} else {
/* Few TDM slots, or No TDM */
regval |= M98090_MAS_MASK |
M98090_BSEL_32;
}
max98090->master = true;
break;
default:
dev_err(component->dev, "DAI clock mode unsupported");
return -EINVAL;
}
snd_soc_component_write(component, M98090_REG_MASTER_MODE, regval);
regval = 0;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
regval |= M98090_DLY_MASK;
break;
case SND_SOC_DAIFMT_LEFT_J:
break;
case SND_SOC_DAIFMT_RIGHT_J:
regval |= M98090_RJ_MASK;
break;
case SND_SOC_DAIFMT_DSP_A:
tdm_regval |= M98090_TDM_MASK;
break;
default:
dev_err(component->dev, "DAI format unsupported");
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_NB_IF:
regval |= M98090_WCI_MASK;
break;
case SND_SOC_DAIFMT_IB_NF:
regval |= M98090_BCI_MASK;
break;
case SND_SOC_DAIFMT_IB_IF:
regval |= M98090_BCI_MASK|M98090_WCI_MASK;
break;
default:
dev_err(component->dev, "DAI invert mode unsupported");
return -EINVAL;
}
/*
* This accommodates an inverted logic in the MAX98090 chip
* for Bit Clock Invert (BCI). The inverted logic is only
* seen for the case of TDM mode. The remaining cases have
* normal logic.
*/
if (tdm_regval)
regval ^= M98090_BCI_MASK;
snd_soc_component_write(component,
M98090_REG_INTERFACE_FORMAT, regval);
regval = 0;
if (tdm_regval)
regval = max98090->tdm_lslot << M98090_TDM_SLOTL_SHIFT |
max98090->tdm_rslot << M98090_TDM_SLOTR_SHIFT |
0 << M98090_TDM_SLOTDLY_SHIFT;
snd_soc_component_write(component, M98090_REG_TDM_FORMAT, regval);
snd_soc_component_write(component, M98090_REG_TDM_CONTROL, tdm_regval);
}
return 0;
}
static int max98090_set_tdm_slot(struct snd_soc_dai *codec_dai,
unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
{
struct snd_soc_component *component = codec_dai->component;
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
if (slots < 0 || slots > 4)
return -EINVAL;
if (slot_width != 16)
return -EINVAL;
if (rx_mask != tx_mask)
return -EINVAL;
if (!rx_mask)
return -EINVAL;
max98090->tdm_slots = slots;
max98090->tdm_lslot = ffs(rx_mask) - 1;
max98090->tdm_rslot = fls(rx_mask) - 1;
return 0;
}
static int max98090_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
int ret;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
/*
* SND_SOC_BIAS_PREPARE is called while preparing for a
* transition to ON or away from ON. If current bias_level
* is SND_SOC_BIAS_ON, then it is preparing for a transition
* away from ON. Disable the clock in that case, otherwise
* enable it.
*/
if (IS_ERR(max98090->mclk))
break;
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) {
clk_disable_unprepare(max98090->mclk);
} else {
ret = clk_prepare_enable(max98090->mclk);
if (ret)
return ret;
}
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
ret = regcache_sync(max98090->regmap);
if (ret != 0) {
dev_err(component->dev,
"Failed to sync cache: %d\n", ret);
return ret;
}
}
break;
case SND_SOC_BIAS_OFF:
/* Set internal pull-up to lowest power mode */
snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT,
M98090_JDWK_MASK, M98090_JDWK_MASK);
regcache_mark_dirty(max98090->regmap);
break;
}
return 0;
}
static const int dmic_divisors[] = { 2, 3, 4, 5, 6, 8 };
static const int comp_lrclk_rates[] = {
8000, 16000, 32000, 44100, 48000, 96000
};
struct dmic_table {
int pclk;
struct {
int freq;
int comp[6]; /* One each for 8, 16, 32, 44.1, 48, and 96 kHz */
} settings[6]; /* One for each dmic divisor. */
};
static const struct dmic_table dmic_table[] = { /* One for each pclk freq. */
{
.pclk = 11289600,
.settings = {
{ .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
{ .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
{ .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } },
{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
},
},
{
.pclk = 12000000,
.settings = {
{ .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
{ .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
{ .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
}
},
{
.pclk = 12288000,
.settings = {
{ .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
{ .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
{ .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } },
{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
}
},
{
.pclk = 13000000,
.settings = {
{ .freq = 2, .comp = { 7, 8, 1, 1, 1, 1 } },
{ .freq = 1, .comp = { 7, 8, 0, 0, 0, 0 } },
{ .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
{ .freq = 0, .comp = { 7, 8, 4, 4, 5, 5 } },
{ .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
{ .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
}
},
{
.pclk = 19200000,
.settings = {
{ .freq = 2, .comp = { 0, 0, 0, 0, 0, 0 } },
{ .freq = 1, .comp = { 7, 8, 1, 1, 1, 1 } },
{ .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
{ .freq = 0, .comp = { 7, 8, 2, 2, 3, 3 } },
{ .freq = 0, .comp = { 7, 8, 1, 1, 2, 2 } },
{ .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
}
},
};
static int max98090_find_divisor(int target_freq, int pclk)
{
int current_diff = INT_MAX;
int test_diff;
int divisor_index = 0;
int i;
for (i = 0; i < ARRAY_SIZE(dmic_divisors); i++) {
test_diff = abs(target_freq - (pclk / dmic_divisors[i]));
if (test_diff < current_diff) {
current_diff = test_diff;
divisor_index = i;
}
}
return divisor_index;
}
static int max98090_find_closest_pclk(int pclk)
{
int m1;
int m2;
int i;
for (i = 0; i < ARRAY_SIZE(dmic_table); i++) {
if (pclk == dmic_table[i].pclk)
return i;
if (pclk < dmic_table[i].pclk) {
if (i == 0)
return i;
m1 = pclk - dmic_table[i-1].pclk;
m2 = dmic_table[i].pclk - pclk;
if (m1 < m2)
return i - 1;
else
return i;
}
}
return -EINVAL;
}
static int max98090_configure_dmic(struct max98090_priv *max98090,
int target_dmic_clk, int pclk, int fs)
{
int micclk_index;
int pclk_index;
int dmic_freq;
int dmic_comp;
int i;
pclk_index = max98090_find_closest_pclk(pclk);
if (pclk_index < 0)
return pclk_index;
micclk_index = max98090_find_divisor(target_dmic_clk, pclk);
for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) {
if (fs <= (comp_lrclk_rates[i] + comp_lrclk_rates[i+1]) / 2)
break;
}
dmic_freq = dmic_table[pclk_index].settings[micclk_index].freq;
dmic_comp = dmic_table[pclk_index].settings[micclk_index].comp[i];
regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_ENABLE,
M98090_MICCLK_MASK,
micclk_index << M98090_MICCLK_SHIFT);
regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_CONFIG,
M98090_DMIC_COMP_MASK | M98090_DMIC_FREQ_MASK,
dmic_comp << M98090_DMIC_COMP_SHIFT |
dmic_freq << M98090_DMIC_FREQ_SHIFT);
return 0;
}
static int max98090_dai_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
unsigned int fmt = max98090->dai_fmt;
/* Remove 24-bit format support if it is not in right justified mode. */
if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_RIGHT_J) {
substream->runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE;
snd_pcm_hw_constraint_msbits(substream->runtime, 0, 16, 16);
}
return 0;
}
static int max98090_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
struct max98090_cdata *cdata;
cdata = &max98090->dai[0];
max98090->bclk = snd_soc_params_to_bclk(params);
if (params_channels(params) == 1)
max98090->bclk *= 2;
max98090->lrclk = params_rate(params);
switch (params_width(params)) {
case 16:
snd_soc_component_update_bits(component, M98090_REG_INTERFACE_FORMAT,
M98090_WS_MASK, 0);
break;
default:
return -EINVAL;
}
if (max98090->master)
max98090_configure_bclk(component);
cdata->rate = max98090->lrclk;
/* Update filter mode */
if (max98090->lrclk < 24000)
snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
M98090_MODE_MASK, 0);
else
snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
M98090_MODE_MASK, M98090_MODE_MASK);
/* Update sample rate mode */
if (max98090->lrclk < 50000)
snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
M98090_DHF_MASK, 0);
else
snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
M98090_DHF_MASK, M98090_DHF_MASK);
max98090_configure_dmic(max98090, max98090->dmic_freq, max98090->pclk,
max98090->lrclk);
return 0;
}
/*
* PLL / Sysclk
*/
static int max98090_dai_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
/* Requested clock frequency is already setup */
if (freq == max98090->sysclk)
return 0;
if (!IS_ERR(max98090->mclk)) {
freq = clk_round_rate(max98090->mclk, freq);
clk_set_rate(max98090->mclk, freq);
}
/* Setup clocks for slave mode, and using the PLL
* PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
* 0x02 (when master clk is 20MHz to 40MHz)..
* 0x03 (when master clk is 40MHz to 60MHz)..
*/
if ((freq >= 10000000) && (freq <= 20000000)) {
snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK,
M98090_PSCLK_DIV1);
max98090->pclk = freq;
} else if ((freq > 20000000) && (freq <= 40000000)) {
snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK,
M98090_PSCLK_DIV2);
max98090->pclk = freq >> 1;
} else if ((freq > 40000000) && (freq <= 60000000)) {
snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK,
M98090_PSCLK_DIV4);
max98090->pclk = freq >> 2;
} else {
dev_err(component->dev, "Invalid master clock frequency\n");
return -EINVAL;
}
max98090->sysclk = freq;
return 0;
}
static int max98090_dai_mute(struct snd_soc_dai *codec_dai, int mute,
int direction)
{
struct snd_soc_component *component = codec_dai->component;
int regval;
regval = mute ? M98090_DVM_MASK : 0;
snd_soc_component_update_bits(component, M98090_REG_DAI_PLAYBACK_LEVEL,
M98090_DVM_MASK, regval);
return 0;
}
static int max98090_dai_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
if (!max98090->master && snd_soc_dai_active(dai) == 1)
queue_delayed_work(system_power_efficient_wq,
&max98090->pll_det_enable_work,
msecs_to_jiffies(10));
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
if (!max98090->master && snd_soc_dai_active(dai) == 1)
schedule_work(&max98090->pll_det_disable_work);
break;
default:
break;
}
return 0;
}
static void max98090_pll_det_enable_work(struct work_struct *work)
{
struct max98090_priv *max98090 =
container_of(work, struct max98090_priv,
pll_det_enable_work.work);
struct snd_soc_component *component = max98090->component;
unsigned int status, mask;
/*
* Clear status register in order to clear possibly already occurred
* PLL unlock. If PLL hasn't still locked, the status will be set
* again and PLL unlock interrupt will occur.
* Note this will clear all status bits
*/
regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status);
/*
* Queue jack work in case jack state has just changed but handler
* hasn't run yet
*/
regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask);
status &= mask;
if (status & M98090_JDET_MASK)
queue_delayed_work(system_power_efficient_wq,
&max98090->jack_work,
msecs_to_jiffies(100));
/* Enable PLL unlock interrupt */
snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S,
M98090_IULK_MASK,
1 << M98090_IULK_SHIFT);
}
static void max98090_pll_det_disable_work(struct work_struct *work)
{
struct max98090_priv *max98090 =
container_of(work, struct max98090_priv, pll_det_disable_work);
struct snd_soc_component *component = max98090->component;
cancel_delayed_work_sync(&max98090->pll_det_enable_work);
/* Disable PLL unlock interrupt */
snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S,
M98090_IULK_MASK, 0);
}
static void max98090_pll_work(struct max98090_priv *max98090)
{
struct snd_soc_component *component = max98090->component;
unsigned int pll;
int i;
if (!snd_soc_component_active(component))
return;
dev_info_ratelimited(component->dev, "PLL unlocked\n");
/*
* As the datasheet suggested, the maximum PLL lock time should be
* 7 msec. The workaround resets the codec softly by toggling SHDN
* off and on if PLL failed to lock for 10 msec. Notably, there is
* no suggested hold time for SHDN off.
*/
/* Toggle shutdown OFF then ON */
snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN,
M98090_SHDNN_MASK, 0);
snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN,
M98090_SHDNN_MASK, M98090_SHDNN_MASK);
for (i = 0; i < 10; ++i) {
/* Give PLL time to lock */
usleep_range(1000, 1200);
/* Check lock status */
pll = snd_soc_component_read(
component, M98090_REG_DEVICE_STATUS);
if (!(pll & M98090_ULK_MASK))
break;
}
}
static void max98090_jack_work(struct work_struct *work)
{
struct max98090_priv *max98090 = container_of(work,
struct max98090_priv,
jack_work.work);
struct snd_soc_component *component = max98090->component;
int status = 0;
int reg;
/* Read a second time */
if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) {
/* Strong pull up allows mic detection */
snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT,
M98090_JDWK_MASK, 0);
msleep(50);
snd_soc_component_read(component, M98090_REG_JACK_STATUS);
/* Weak pull up allows only insertion detection */
snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT,
M98090_JDWK_MASK, M98090_JDWK_MASK);
}
reg = snd_soc_component_read(component, M98090_REG_JACK_STATUS);
switch (reg & (M98090_LSNS_MASK | M98090_JKSNS_MASK)) {
case M98090_LSNS_MASK | M98090_JKSNS_MASK:
dev_dbg(component->dev, "No Headset Detected\n");
max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
status |= 0;
break;
case 0:
if (max98090->jack_state ==
M98090_JACK_STATE_HEADSET) {
dev_dbg(component->dev,
"Headset Button Down Detected\n");
/*
* max98090_headset_button_event(codec)
* could be defined, then called here.
*/
status |= SND_JACK_HEADSET;
status |= SND_JACK_BTN_0;
break;
}
/* Line is reported as Headphone */
/* Nokia Headset is reported as Headphone */
/* Mono Headphone is reported as Headphone */
dev_dbg(component->dev, "Headphone Detected\n");
max98090->jack_state = M98090_JACK_STATE_HEADPHONE;
status |= SND_JACK_HEADPHONE;
break;
case M98090_JKSNS_MASK:
dev_dbg(component->dev, "Headset Detected\n");
max98090->jack_state = M98090_JACK_STATE_HEADSET;
status |= SND_JACK_HEADSET;
break;
default:
dev_dbg(component->dev, "Unrecognized Jack Status\n");
break;
}
snd_soc_jack_report(max98090->jack, status,
SND_JACK_HEADSET | SND_JACK_BTN_0);
}
static irqreturn_t max98090_interrupt(int irq, void *data)
{
struct max98090_priv *max98090 = data;
struct snd_soc_component *component = max98090->component;
int ret;
unsigned int mask;
unsigned int active;
/* Treat interrupt before codec is initialized as spurious */
if (component == NULL)
return IRQ_NONE;
dev_dbg(component->dev, "***** max98090_interrupt *****\n");
ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask);
if (ret != 0) {
dev_err(component->dev,
"failed to read M98090_REG_INTERRUPT_S: %d\n",
ret);
return IRQ_NONE;
}
ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active);
if (ret != 0) {
dev_err(component->dev,
"failed to read M98090_REG_DEVICE_STATUS: %d\n",
ret);
return IRQ_NONE;
}
dev_dbg(component->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n",
active, mask, active & mask);
active &= mask;
if (!active)
return IRQ_NONE;
if (active & M98090_CLD_MASK)
dev_err(component->dev, "M98090_CLD_MASK\n");
if (active & M98090_SLD_MASK)
dev_dbg(component->dev, "M98090_SLD_MASK\n");
if (active & M98090_ULK_MASK) {
dev_dbg(component->dev, "M98090_ULK_MASK\n");
max98090_pll_work(max98090);
}
if (active & M98090_JDET_MASK) {
dev_dbg(component->dev, "M98090_JDET_MASK\n");
pm_wakeup_event(component->dev, 100);
queue_delayed_work(system_power_efficient_wq,
&max98090->jack_work,
msecs_to_jiffies(100));
}
if (active & M98090_DRCACT_MASK)
dev_dbg(component->dev, "M98090_DRCACT_MASK\n");
if (active & M98090_DRCCLP_MASK)
dev_err(component->dev, "M98090_DRCCLP_MASK\n");
return IRQ_HANDLED;
}
/**
* max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ
*
* @component: MAX98090 component
* @jack: jack to report detection events on
*
* Enable microphone detection via IRQ on the MAX98090. If GPIOs are
* being used to bring out signals to the processor then only platform
* data configuration is needed for MAX98090 and processor GPIOs should
* be configured using snd_soc_jack_add_gpios() instead.
*
* If no jack is supplied detection will be disabled.
*/
int max98090_mic_detect(struct snd_soc_component *component,
struct snd_soc_jack *jack)
{
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
dev_dbg(component->dev, "max98090_mic_detect\n");
max98090->jack = jack;
if (jack) {
snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S,
M98090_IJDET_MASK,
1 << M98090_IJDET_SHIFT);
} else {
snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S,
M98090_IJDET_MASK,
0);
}
/* Send an initial empty report */
snd_soc_jack_report(max98090->jack, 0,
SND_JACK_HEADSET | SND_JACK_BTN_0);
queue_delayed_work(system_power_efficient_wq,
&max98090->jack_work,
msecs_to_jiffies(100));
return 0;
}
EXPORT_SYMBOL_GPL(max98090_mic_detect);
#define MAX98090_RATES SNDRV_PCM_RATE_8000_96000
#define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
static const struct snd_soc_dai_ops max98090_dai_ops = {
.startup = max98090_dai_startup,
.set_sysclk = max98090_dai_set_sysclk,
.set_fmt = max98090_dai_set_fmt,
.set_tdm_slot = max98090_set_tdm_slot,
.hw_params = max98090_dai_hw_params,
.mute_stream = max98090_dai_mute,
.trigger = max98090_dai_trigger,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver max98090_dai = {
.name = "HiFi",
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 2,
.channels_max = 2,
.rates = MAX98090_RATES,
.formats = MAX98090_FORMATS,
},
.capture = {
.stream_name = "HiFi Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MAX98090_RATES,
.formats = MAX98090_FORMATS,
},
.ops = &max98090_dai_ops,
};
static int max98090_probe(struct snd_soc_component *component)
{
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
struct max98090_cdata *cdata;
enum max98090_type devtype;
int ret = 0;
int err;
unsigned int micbias;
dev_dbg(component->dev, "max98090_probe\n");
max98090->mclk = devm_clk_get(component->dev, "mclk");
if (PTR_ERR(max98090->mclk) == -EPROBE_DEFER)
return -EPROBE_DEFER;
max98090->component = component;
/* Reset the codec, the DSP core, and disable all interrupts */
max98090_reset(max98090);
/* Initialize private data */
max98090->sysclk = (unsigned)-1;
max98090->pclk = (unsigned)-1;
max98090->master = false;
cdata = &max98090->dai[0];
cdata->rate = (unsigned)-1;
cdata->fmt = (unsigned)-1;
max98090->lin_state = 0;
max98090->pa1en = 0;
max98090->pa2en = 0;
max98090->tdm_lslot = 0;
max98090->tdm_rslot = 1;
ret = snd_soc_component_read(component, M98090_REG_REVISION_ID);
if (ret < 0) {
dev_err(component->dev, "Failed to read device revision: %d\n",
ret);
goto err_access;
}
if ((ret >= M98090_REVA) && (ret <= M98090_REVA + 0x0f)) {
devtype = MAX98090;
dev_info(component->dev, "MAX98090 REVID=0x%02x\n", ret);
} else if ((ret >= M98091_REVA) && (ret <= M98091_REVA + 0x0f)) {
devtype = MAX98091;
dev_info(component->dev, "MAX98091 REVID=0x%02x\n", ret);
} else {
devtype = MAX98090;
dev_err(component->dev, "Unrecognized revision 0x%02x\n", ret);
}
if (max98090->devtype != devtype) {
dev_warn(component->dev, "Mismatch in DT specified CODEC type.\n");
max98090->devtype = devtype;
}
max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work);
INIT_DELAYED_WORK(&max98090->pll_det_enable_work,
max98090_pll_det_enable_work);
INIT_WORK(&max98090->pll_det_disable_work,
max98090_pll_det_disable_work);
/* Enable jack detection */
snd_soc_component_write(component, M98090_REG_JACK_DETECT,
M98090_JDETEN_MASK | M98090_JDEB_25MS);
/*
* Clear any old interrupts.
* An old interrupt ocurring prior to installing the ISR
* can keep a new interrupt from generating a trigger.
*/
snd_soc_component_read(component, M98090_REG_DEVICE_STATUS);
/* High Performance is default */
snd_soc_component_update_bits(component, M98090_REG_DAC_CONTROL,
M98090_DACHP_MASK,
1 << M98090_DACHP_SHIFT);
snd_soc_component_update_bits(component, M98090_REG_DAC_CONTROL,
M98090_PERFMODE_MASK,
0 << M98090_PERFMODE_SHIFT);
snd_soc_component_update_bits(component, M98090_REG_ADC_CONTROL,
M98090_ADCHP_MASK,
1 << M98090_ADCHP_SHIFT);
/* Turn on VCM bandgap reference */
snd_soc_component_write(component, M98090_REG_BIAS_CONTROL,
M98090_VCM_MODE_MASK);
err = device_property_read_u32(component->dev, "maxim,micbias", &micbias);
if (err) {
micbias = M98090_MBVSEL_2V8;
dev_info(component->dev, "use default 2.8v micbias\n");
} else if (micbias > M98090_MBVSEL_2V8) {
dev_err(component->dev, "micbias out of range 0x%x\n", micbias);
micbias = M98090_MBVSEL_2V8;
}
snd_soc_component_update_bits(component, M98090_REG_MIC_BIAS_VOLTAGE,
M98090_MBVSEL_MASK, micbias);
max98090_add_widgets(component);
err_access:
return ret;
}
static void max98090_remove(struct snd_soc_component *component)
{
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
cancel_delayed_work_sync(&max98090->jack_work);
cancel_delayed_work_sync(&max98090->pll_det_enable_work);
cancel_work_sync(&max98090->pll_det_disable_work);
max98090->component = NULL;
}
static void max98090_seq_notifier(struct snd_soc_component *component,
enum snd_soc_dapm_type event, int subseq)
{
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
if (max98090->shdn_pending) {
snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN,
M98090_SHDNN_MASK, 0);
msleep(40);
snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN,
M98090_SHDNN_MASK, M98090_SHDNN_MASK);
max98090->shdn_pending = false;
}
}
static const struct snd_soc_component_driver soc_component_dev_max98090 = {
.probe = max98090_probe,
.remove = max98090_remove,
.seq_notifier = max98090_seq_notifier,
.set_bias_level = max98090_set_bias_level,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config max98090_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = MAX98090_MAX_REGISTER,
.reg_defaults = max98090_reg,
.num_reg_defaults = ARRAY_SIZE(max98090_reg),
.volatile_reg = max98090_volatile_register,
.readable_reg = max98090_readable_register,
.cache_type = REGCACHE_RBTREE,
};
static const struct i2c_device_id max98090_i2c_id[] = {
{ "max98090", MAX98090 },
{ "max98091", MAX98091 },
{ }
};
MODULE_DEVICE_TABLE(i2c, max98090_i2c_id);
static int max98090_i2c_probe(struct i2c_client *i2c)
{
struct max98090_priv *max98090;
const struct acpi_device_id *acpi_id;
kernel_ulong_t driver_data = 0;
int ret;
pr_debug("max98090_i2c_probe\n");
max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv),
GFP_KERNEL);
if (max98090 == NULL)
return -ENOMEM;
if (ACPI_HANDLE(&i2c->dev)) {
acpi_id = acpi_match_device(i2c->dev.driver->acpi_match_table,
&i2c->dev);
if (!acpi_id) {
dev_err(&i2c->dev, "No driver data\n");
return -EINVAL;
}
driver_data = acpi_id->driver_data;
} else {
const struct i2c_device_id *i2c_id =
i2c_match_id(max98090_i2c_id, i2c);
driver_data = i2c_id->driver_data;
}
max98090->devtype = driver_data;
i2c_set_clientdata(i2c, max98090);
max98090->pdata = i2c->dev.platform_data;
ret = of_property_read_u32(i2c->dev.of_node, "maxim,dmic-freq",
&max98090->dmic_freq);
if (ret < 0)
max98090->dmic_freq = MAX98090_DEFAULT_DMIC_FREQ;
max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap);
if (IS_ERR(max98090->regmap)) {
ret = PTR_ERR(max98090->regmap);
dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
goto err_enable;
}
ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
max98090_interrupt, IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
"max98090_interrupt", max98090);
if (ret < 0) {
dev_err(&i2c->dev, "request_irq failed: %d\n",
ret);
return ret;
}
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_max98090,
&max98090_dai, 1);
err_enable:
return ret;
}
static void max98090_i2c_shutdown(struct i2c_client *i2c)
{
struct max98090_priv *max98090 = dev_get_drvdata(&i2c->dev);
/*
* Enable volume smoothing, disable zero cross. This will cause
* a quick 40ms ramp to mute on shutdown.
*/
regmap_write(max98090->regmap,
M98090_REG_LEVEL_CONTROL, M98090_VSENN_MASK);
regmap_write(max98090->regmap,
M98090_REG_DEVICE_SHUTDOWN, 0x00);
msleep(40);
}
static void max98090_i2c_remove(struct i2c_client *client)
{
max98090_i2c_shutdown(client);
}
#ifdef CONFIG_PM
static int max98090_runtime_resume(struct device *dev)
{
struct max98090_priv *max98090 = dev_get_drvdata(dev);
regcache_cache_only(max98090->regmap, false);
max98090_reset(max98090);
regcache_sync(max98090->regmap);
return 0;
}
static int max98090_runtime_suspend(struct device *dev)
{
struct max98090_priv *max98090 = dev_get_drvdata(dev);
regcache_cache_only(max98090->regmap, true);
return 0;
}
#endif
#ifdef CONFIG_PM_SLEEP
static int max98090_resume(struct device *dev)
{
struct max98090_priv *max98090 = dev_get_drvdata(dev);
unsigned int status;
regcache_mark_dirty(max98090->regmap);
max98090_reset(max98090);
/* clear IRQ status */
regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status);
regcache_sync(max98090->regmap);
return 0;
}
#endif
static const struct dev_pm_ops max98090_pm = {
SET_RUNTIME_PM_OPS(max98090_runtime_suspend,
max98090_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(NULL, max98090_resume)
};
#ifdef CONFIG_OF
static const struct of_device_id max98090_of_match[] = {
{ .compatible = "maxim,max98090", },
{ .compatible = "maxim,max98091", },
{ }
};
MODULE_DEVICE_TABLE(of, max98090_of_match);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id max98090_acpi_match[] = {
{ "193C9890", MAX98090 },
{ }
};
MODULE_DEVICE_TABLE(acpi, max98090_acpi_match);
#endif
static struct i2c_driver max98090_i2c_driver = {
.driver = {
.name = "max98090",
.pm = &max98090_pm,
.of_match_table = of_match_ptr(max98090_of_match),
.acpi_match_table = ACPI_PTR(max98090_acpi_match),
},
.probe = max98090_i2c_probe,
.shutdown = max98090_i2c_shutdown,
.remove = max98090_i2c_remove,
.id_table = max98090_i2c_id,
};
module_i2c_driver(max98090_i2c_driver);
MODULE_DESCRIPTION("ALSA SoC MAX98090 driver");
MODULE_AUTHOR("Peter Hsiang, Jesse Marroqin, Jerry Wong");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/max98090.c |
/*
* CS4270 ALSA SoC (ASoC) codec driver
*
* Author: Timur Tabi <[email protected]>
*
* Copyright 2007-2009 Freescale Semiconductor, Inc. This file is licensed
* under the terms of the GNU General Public License version 2. This
* program is licensed "as is" without any warranty of any kind, whether
* express or implied.
*
* This is an ASoC device driver for the Cirrus Logic CS4270 codec.
*
* Current features/limitations:
*
* - Software mode is supported. Stand-alone mode is not supported.
* - Only I2C is supported, not SPI
* - Support for master and slave mode
* - The machine driver's 'startup' function must call
* cs4270_set_dai_sysclk() with the value of MCLK.
* - Only I2S and left-justified modes are supported
* - Power management is supported
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <linux/i2c.h>
#include <linux/delay.h>
#include <linux/regulator/consumer.h>
#include <linux/gpio/consumer.h>
#include <linux/of_device.h>
#define CS4270_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
/* CS4270 registers addresses */
#define CS4270_CHIPID 0x01 /* Chip ID */
#define CS4270_PWRCTL 0x02 /* Power Control */
#define CS4270_MODE 0x03 /* Mode Control */
#define CS4270_FORMAT 0x04 /* Serial Format, ADC/DAC Control */
#define CS4270_TRANS 0x05 /* Transition Control */
#define CS4270_MUTE 0x06 /* Mute Control */
#define CS4270_VOLA 0x07 /* DAC Channel A Volume Control */
#define CS4270_VOLB 0x08 /* DAC Channel B Volume Control */
#define CS4270_FIRSTREG 0x01
#define CS4270_LASTREG 0x08
#define CS4270_NUMREGS (CS4270_LASTREG - CS4270_FIRSTREG + 1)
#define CS4270_I2C_INCR 0x80
/* Bit masks for the CS4270 registers */
#define CS4270_CHIPID_ID 0xF0
#define CS4270_CHIPID_REV 0x0F
#define CS4270_PWRCTL_FREEZE 0x80
#define CS4270_PWRCTL_PDN_ADC 0x20
#define CS4270_PWRCTL_PDN_DAC 0x02
#define CS4270_PWRCTL_PDN 0x01
#define CS4270_PWRCTL_PDN_ALL \
(CS4270_PWRCTL_PDN_ADC | CS4270_PWRCTL_PDN_DAC | CS4270_PWRCTL_PDN)
#define CS4270_MODE_SPEED_MASK 0x30
#define CS4270_MODE_1X 0x00
#define CS4270_MODE_2X 0x10
#define CS4270_MODE_4X 0x20
#define CS4270_MODE_SLAVE 0x30
#define CS4270_MODE_DIV_MASK 0x0E
#define CS4270_MODE_DIV1 0x00
#define CS4270_MODE_DIV15 0x02
#define CS4270_MODE_DIV2 0x04
#define CS4270_MODE_DIV3 0x06
#define CS4270_MODE_DIV4 0x08
#define CS4270_MODE_POPGUARD 0x01
#define CS4270_FORMAT_FREEZE_A 0x80
#define CS4270_FORMAT_FREEZE_B 0x40
#define CS4270_FORMAT_LOOPBACK 0x20
#define CS4270_FORMAT_DAC_MASK 0x18
#define CS4270_FORMAT_DAC_LJ 0x00
#define CS4270_FORMAT_DAC_I2S 0x08
#define CS4270_FORMAT_DAC_RJ16 0x18
#define CS4270_FORMAT_DAC_RJ24 0x10
#define CS4270_FORMAT_ADC_MASK 0x01
#define CS4270_FORMAT_ADC_LJ 0x00
#define CS4270_FORMAT_ADC_I2S 0x01
#define CS4270_TRANS_ONE_VOL 0x80
#define CS4270_TRANS_SOFT 0x40
#define CS4270_TRANS_ZERO 0x20
#define CS4270_TRANS_INV_ADC_A 0x08
#define CS4270_TRANS_INV_ADC_B 0x10
#define CS4270_TRANS_INV_DAC_A 0x02
#define CS4270_TRANS_INV_DAC_B 0x04
#define CS4270_TRANS_DEEMPH 0x01
#define CS4270_MUTE_AUTO 0x20
#define CS4270_MUTE_ADC_A 0x08
#define CS4270_MUTE_ADC_B 0x10
#define CS4270_MUTE_POLARITY 0x04
#define CS4270_MUTE_DAC_A 0x01
#define CS4270_MUTE_DAC_B 0x02
/* Power-on default values for the registers
*
* This array contains the power-on default values of the registers, with the
* exception of the "CHIPID" register (01h). The lower four bits of that
* register contain the hardware revision, so it is treated as volatile.
*/
static const struct reg_default cs4270_reg_defaults[] = {
{ 2, 0x00 },
{ 3, 0x30 },
{ 4, 0x00 },
{ 5, 0x60 },
{ 6, 0x20 },
{ 7, 0x00 },
{ 8, 0x00 },
};
static const char *supply_names[] = {
"va", "vd", "vlc"
};
/* Private data for the CS4270 */
struct cs4270_private {
struct regmap *regmap;
unsigned int mclk; /* Input frequency of the MCLK pin */
unsigned int mode; /* The mode (I2S or left-justified) */
unsigned int slave_mode;
unsigned int manual_mute;
/* power domain regulators */
struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
/* reset gpio */
struct gpio_desc *reset_gpio;
};
static const struct snd_soc_dapm_widget cs4270_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("AINL"),
SND_SOC_DAPM_INPUT("AINR"),
SND_SOC_DAPM_OUTPUT("AOUTL"),
SND_SOC_DAPM_OUTPUT("AOUTR"),
};
static const struct snd_soc_dapm_route cs4270_dapm_routes[] = {
{ "Capture", NULL, "AINL" },
{ "Capture", NULL, "AINR" },
{ "AOUTL", NULL, "Playback" },
{ "AOUTR", NULL, "Playback" },
};
/**
* struct cs4270_mode_ratios - clock ratio tables
* @ratio: the ratio of MCLK to the sample rate
* @speed_mode: the Speed Mode bits to set in the Mode Control register for
* this ratio
* @mclk: the Ratio Select bits to set in the Mode Control register for this
* ratio
*
* The data for this chart is taken from Table 5 of the CS4270 reference
* manual.
*
* This table is used to determine how to program the Mode Control register.
* It is also used by cs4270_set_dai_sysclk() to tell ALSA which sampling
* rates the CS4270 currently supports.
*
* @speed_mode is the corresponding bit pattern to be written to the
* MODE bits of the Mode Control Register
*
* @mclk is the corresponding bit pattern to be wirten to the MCLK bits of
* the Mode Control Register.
*
* In situations where a single ratio is represented by multiple speed
* modes, we favor the slowest speed. E.g, for a ratio of 128, we pick
* double-speed instead of quad-speed. However, the CS4270 errata states
* that divide-By-1.5 can cause failures, so we avoid that mode where
* possible.
*
* Errata: There is an errata for the CS4270 where divide-by-1.5 does not
* work if Vd is 3.3V. If this effects you, select the
* CONFIG_SND_SOC_CS4270_VD33_ERRATA Kconfig option, and the driver will
* never select any sample rates that require divide-by-1.5.
*/
struct cs4270_mode_ratios {
unsigned int ratio;
u8 speed_mode;
u8 mclk;
};
static struct cs4270_mode_ratios cs4270_mode_ratios[] = {
{64, CS4270_MODE_4X, CS4270_MODE_DIV1},
#ifndef CONFIG_SND_SOC_CS4270_VD33_ERRATA
{96, CS4270_MODE_4X, CS4270_MODE_DIV15},
#endif
{128, CS4270_MODE_2X, CS4270_MODE_DIV1},
{192, CS4270_MODE_4X, CS4270_MODE_DIV3},
{256, CS4270_MODE_1X, CS4270_MODE_DIV1},
{384, CS4270_MODE_2X, CS4270_MODE_DIV3},
{512, CS4270_MODE_1X, CS4270_MODE_DIV2},
{768, CS4270_MODE_1X, CS4270_MODE_DIV3},
{1024, CS4270_MODE_1X, CS4270_MODE_DIV4}
};
/* The number of MCLK/LRCK ratios supported by the CS4270 */
#define NUM_MCLK_RATIOS ARRAY_SIZE(cs4270_mode_ratios)
static bool cs4270_reg_is_readable(struct device *dev, unsigned int reg)
{
return (reg >= CS4270_FIRSTREG) && (reg <= CS4270_LASTREG);
}
static bool cs4270_reg_is_volatile(struct device *dev, unsigned int reg)
{
/* Unreadable registers are considered volatile */
if ((reg < CS4270_FIRSTREG) || (reg > CS4270_LASTREG))
return true;
return reg == CS4270_CHIPID;
}
/**
* cs4270_set_dai_sysclk - determine the CS4270 samples rates.
* @codec_dai: the codec DAI
* @clk_id: the clock ID (ignored)
* @freq: the MCLK input frequency
* @dir: the clock direction (ignored)
*
* This function is used to tell the codec driver what the input MCLK
* frequency is.
*
* The value of MCLK is used to determine which sample rates are supported
* by the CS4270. The ratio of MCLK / Fs must be equal to one of nine
* supported values - 64, 96, 128, 192, 256, 384, 512, 768, and 1024.
*
* This function calculates the nine ratios and determines which ones match
* a standard sample rate. If there's a match, then it is added to the list
* of supported sample rates.
*
* This function must be called by the machine driver's 'startup' function,
* otherwise the list of supported sample rates will not be available in
* time for ALSA.
*
* For setups with variable MCLKs, pass 0 as 'freq' argument. This will cause
* theoretically possible sample rates to be enabled. Call it again with a
* proper value set one the external clock is set (most probably you would do
* that from a machine's driver 'hw_param' hook.
*/
static int cs4270_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct cs4270_private *cs4270 = snd_soc_component_get_drvdata(component);
cs4270->mclk = freq;
return 0;
}
/**
* cs4270_set_dai_fmt - configure the codec for the selected audio format
* @codec_dai: the codec DAI
* @format: a SND_SOC_DAIFMT_x value indicating the data format
*
* This function takes a bitmask of SND_SOC_DAIFMT_x bits and programs the
* codec accordingly.
*
* Currently, this function only supports SND_SOC_DAIFMT_I2S and
* SND_SOC_DAIFMT_LEFT_J. The CS4270 codec also supports right-justified
* data for playback only, but ASoC currently does not support different
* formats for playback vs. record.
*/
static int cs4270_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int format)
{
struct snd_soc_component *component = codec_dai->component;
struct cs4270_private *cs4270 = snd_soc_component_get_drvdata(component);
/* set DAI format */
switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_LEFT_J:
cs4270->mode = format & SND_SOC_DAIFMT_FORMAT_MASK;
break;
default:
dev_err(component->dev, "invalid dai format\n");
return -EINVAL;
}
/* set master/slave audio interface */
switch (format & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
cs4270->slave_mode = 1;
break;
case SND_SOC_DAIFMT_CBM_CFM:
cs4270->slave_mode = 0;
break;
default:
/* all other modes are unsupported by the hardware */
dev_err(component->dev, "Unknown master/slave configuration\n");
return -EINVAL;
}
return 0;
}
/**
* cs4270_hw_params - program the CS4270 with the given hardware parameters.
* @substream: the audio stream
* @params: the hardware parameters to set
* @dai: the SOC DAI (ignored)
*
* This function programs the hardware with the values provided.
* Specifically, the sample rate and the data format.
*
* The .ops functions are used to provide board-specific data, like input
* frequencies, to this driver. This function takes that information,
* combines it with the hardware parameters provided, and programs the
* hardware accordingly.
*/
static int cs4270_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct cs4270_private *cs4270 = snd_soc_component_get_drvdata(component);
int ret;
unsigned int i;
unsigned int rate;
unsigned int ratio;
int reg;
/* Figure out which MCLK/LRCK ratio to use */
rate = params_rate(params); /* Sampling rate, in Hz */
ratio = cs4270->mclk / rate; /* MCLK/LRCK ratio */
for (i = 0; i < NUM_MCLK_RATIOS; i++) {
if (cs4270_mode_ratios[i].ratio == ratio)
break;
}
if (i == NUM_MCLK_RATIOS) {
/* We did not find a matching ratio */
dev_err(component->dev, "could not find matching ratio\n");
return -EINVAL;
}
/* Set the sample rate */
reg = snd_soc_component_read(component, CS4270_MODE);
reg &= ~(CS4270_MODE_SPEED_MASK | CS4270_MODE_DIV_MASK);
reg |= cs4270_mode_ratios[i].mclk;
if (cs4270->slave_mode)
reg |= CS4270_MODE_SLAVE;
else
reg |= cs4270_mode_ratios[i].speed_mode;
ret = snd_soc_component_write(component, CS4270_MODE, reg);
if (ret < 0) {
dev_err(component->dev, "i2c write failed\n");
return ret;
}
/* Set the DAI format */
reg = snd_soc_component_read(component, CS4270_FORMAT);
reg &= ~(CS4270_FORMAT_DAC_MASK | CS4270_FORMAT_ADC_MASK);
switch (cs4270->mode) {
case SND_SOC_DAIFMT_I2S:
reg |= CS4270_FORMAT_DAC_I2S | CS4270_FORMAT_ADC_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
reg |= CS4270_FORMAT_DAC_LJ | CS4270_FORMAT_ADC_LJ;
break;
default:
dev_err(component->dev, "unknown dai format\n");
return -EINVAL;
}
ret = snd_soc_component_write(component, CS4270_FORMAT, reg);
if (ret < 0) {
dev_err(component->dev, "i2c write failed\n");
return ret;
}
return ret;
}
/**
* cs4270_dai_mute - enable/disable the CS4270 external mute
* @dai: the SOC DAI
* @mute: 0 = disable mute, 1 = enable mute
* @direction: (ignored)
*
* This function toggles the mute bits in the MUTE register. The CS4270's
* mute capability is intended for external muting circuitry, so if the
* board does not have the MUTEA or MUTEB pins connected to such circuitry,
* then this function will do nothing.
*/
static int cs4270_dai_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
struct cs4270_private *cs4270 = snd_soc_component_get_drvdata(component);
int reg6;
reg6 = snd_soc_component_read(component, CS4270_MUTE);
if (mute)
reg6 |= CS4270_MUTE_DAC_A | CS4270_MUTE_DAC_B;
else {
reg6 &= ~(CS4270_MUTE_DAC_A | CS4270_MUTE_DAC_B);
reg6 |= cs4270->manual_mute;
}
return snd_soc_component_write(component, CS4270_MUTE, reg6);
}
/**
* cs4270_soc_put_mute - put callback for the 'Master Playback switch'
* alsa control.
* @kcontrol: mixer control
* @ucontrol: control element information
*
* This function basically passes the arguments on to the generic
* snd_soc_put_volsw() function and saves the mute information in
* our private data structure. This is because we want to prevent
* cs4270_dai_mute() neglecting the user's decision to manually
* mute the codec's output.
*
* Returns 0 for success.
*/
static int cs4270_soc_put_mute(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct cs4270_private *cs4270 = snd_soc_component_get_drvdata(component);
int left = !ucontrol->value.integer.value[0];
int right = !ucontrol->value.integer.value[1];
cs4270->manual_mute = (left ? CS4270_MUTE_DAC_A : 0) |
(right ? CS4270_MUTE_DAC_B : 0);
return snd_soc_put_volsw(kcontrol, ucontrol);
}
/* A list of non-DAPM controls that the CS4270 supports */
static const struct snd_kcontrol_new cs4270_snd_controls[] = {
SOC_DOUBLE_R("Master Playback Volume",
CS4270_VOLA, CS4270_VOLB, 0, 0xFF, 1),
SOC_SINGLE("Digital Sidetone Switch", CS4270_FORMAT, 5, 1, 0),
SOC_SINGLE("Soft Ramp Switch", CS4270_TRANS, 6, 1, 0),
SOC_SINGLE("Zero Cross Switch", CS4270_TRANS, 5, 1, 0),
SOC_SINGLE("De-emphasis filter", CS4270_TRANS, 0, 1, 0),
SOC_SINGLE("Popguard Switch", CS4270_MODE, 0, 1, 1),
SOC_SINGLE("Auto-Mute Switch", CS4270_MUTE, 5, 1, 0),
SOC_DOUBLE("Master Capture Switch", CS4270_MUTE, 3, 4, 1, 1),
SOC_DOUBLE_EXT("Master Playback Switch", CS4270_MUTE, 0, 1, 1, 1,
snd_soc_get_volsw, cs4270_soc_put_mute),
};
static const struct snd_soc_dai_ops cs4270_dai_ops = {
.hw_params = cs4270_hw_params,
.set_sysclk = cs4270_set_dai_sysclk,
.set_fmt = cs4270_set_dai_fmt,
.mute_stream = cs4270_dai_mute,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver cs4270_dai = {
.name = "cs4270-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.rate_min = 4000,
.rate_max = 216000,
.formats = CS4270_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.rate_min = 4000,
.rate_max = 216000,
.formats = CS4270_FORMATS,
},
.ops = &cs4270_dai_ops,
};
/**
* cs4270_probe - ASoC probe function
* @component: ASoC component
*
* This function is called when ASoC has all the pieces it needs to
* instantiate a sound driver.
*/
static int cs4270_probe(struct snd_soc_component *component)
{
struct cs4270_private *cs4270 = snd_soc_component_get_drvdata(component);
int ret;
/* Disable auto-mute. This feature appears to be buggy. In some
* situations, auto-mute will not deactivate when it should, so we want
* this feature disabled by default. An application (e.g. alsactl) can
* re-enabled it by using the controls.
*/
ret = snd_soc_component_update_bits(component, CS4270_MUTE, CS4270_MUTE_AUTO, 0);
if (ret < 0) {
dev_err(component->dev, "i2c write failed\n");
return ret;
}
/* Disable automatic volume control. The hardware enables, and it
* causes volume change commands to be delayed, sometimes until after
* playback has started. An application (e.g. alsactl) can
* re-enabled it by using the controls.
*/
ret = snd_soc_component_update_bits(component, CS4270_TRANS,
CS4270_TRANS_SOFT | CS4270_TRANS_ZERO, 0);
if (ret < 0) {
dev_err(component->dev, "i2c write failed\n");
return ret;
}
ret = regulator_bulk_enable(ARRAY_SIZE(cs4270->supplies),
cs4270->supplies);
return ret;
}
/**
* cs4270_remove - ASoC remove function
* @component: ASoC component
*
* This function is the counterpart to cs4270_probe().
*/
static void cs4270_remove(struct snd_soc_component *component)
{
struct cs4270_private *cs4270 = snd_soc_component_get_drvdata(component);
regulator_bulk_disable(ARRAY_SIZE(cs4270->supplies), cs4270->supplies);
};
#ifdef CONFIG_PM
/* This suspend/resume implementation can handle both - a simple standby
* where the codec remains powered, and a full suspend, where the voltage
* domain the codec is connected to is teared down and/or any other hardware
* reset condition is asserted.
*
* The codec's own power saving features are enabled in the suspend callback,
* and all registers are written back to the hardware when resuming.
*/
static int cs4270_soc_suspend(struct snd_soc_component *component)
{
struct cs4270_private *cs4270 = snd_soc_component_get_drvdata(component);
int reg, ret;
reg = snd_soc_component_read(component, CS4270_PWRCTL) | CS4270_PWRCTL_PDN_ALL;
if (reg < 0)
return reg;
ret = snd_soc_component_write(component, CS4270_PWRCTL, reg);
if (ret < 0)
return ret;
regulator_bulk_disable(ARRAY_SIZE(cs4270->supplies),
cs4270->supplies);
return 0;
}
static int cs4270_soc_resume(struct snd_soc_component *component)
{
struct cs4270_private *cs4270 = snd_soc_component_get_drvdata(component);
int reg, ret;
ret = regulator_bulk_enable(ARRAY_SIZE(cs4270->supplies),
cs4270->supplies);
if (ret != 0)
return ret;
/* In case the device was put to hard reset during sleep, we need to
* wait 500ns here before any I2C communication. */
ndelay(500);
/* first restore the entire register cache ... */
regcache_sync(cs4270->regmap);
/* ... then disable the power-down bits */
reg = snd_soc_component_read(component, CS4270_PWRCTL);
reg &= ~CS4270_PWRCTL_PDN_ALL;
return snd_soc_component_write(component, CS4270_PWRCTL, reg);
}
#else
#define cs4270_soc_suspend NULL
#define cs4270_soc_resume NULL
#endif /* CONFIG_PM */
/*
* ASoC codec driver structure
*/
static const struct snd_soc_component_driver soc_component_device_cs4270 = {
.probe = cs4270_probe,
.remove = cs4270_remove,
.suspend = cs4270_soc_suspend,
.resume = cs4270_soc_resume,
.controls = cs4270_snd_controls,
.num_controls = ARRAY_SIZE(cs4270_snd_controls),
.dapm_widgets = cs4270_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(cs4270_dapm_widgets),
.dapm_routes = cs4270_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(cs4270_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
/*
* cs4270_of_match - the device tree bindings
*/
static const struct of_device_id cs4270_of_match[] = {
{ .compatible = "cirrus,cs4270", },
{ }
};
MODULE_DEVICE_TABLE(of, cs4270_of_match);
static const struct regmap_config cs4270_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = CS4270_LASTREG,
.reg_defaults = cs4270_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(cs4270_reg_defaults),
.cache_type = REGCACHE_MAPLE,
.write_flag_mask = CS4270_I2C_INCR,
.readable_reg = cs4270_reg_is_readable,
.volatile_reg = cs4270_reg_is_volatile,
};
/**
* cs4270_i2c_remove - deinitialize the I2C interface of the CS4270
* @i2c_client: the I2C client object
*
* This function puts the chip into low power mode when the i2c device
* is removed.
*/
static void cs4270_i2c_remove(struct i2c_client *i2c_client)
{
struct cs4270_private *cs4270 = i2c_get_clientdata(i2c_client);
gpiod_set_value_cansleep(cs4270->reset_gpio, 0);
}
/**
* cs4270_i2c_probe - initialize the I2C interface of the CS4270
* @i2c_client: the I2C client object
*
* This function is called whenever the I2C subsystem finds a device that
* matches the device ID given via a prior call to i2c_add_driver().
*/
static int cs4270_i2c_probe(struct i2c_client *i2c_client)
{
struct cs4270_private *cs4270;
unsigned int val;
int ret, i;
cs4270 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs4270_private),
GFP_KERNEL);
if (!cs4270)
return -ENOMEM;
/* get the power supply regulators */
for (i = 0; i < ARRAY_SIZE(supply_names); i++)
cs4270->supplies[i].supply = supply_names[i];
ret = devm_regulator_bulk_get(&i2c_client->dev,
ARRAY_SIZE(cs4270->supplies),
cs4270->supplies);
if (ret < 0)
return ret;
/* reset the device */
cs4270->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev, "reset",
GPIOD_OUT_LOW);
if (IS_ERR(cs4270->reset_gpio)) {
dev_dbg(&i2c_client->dev, "Error getting CS4270 reset GPIO\n");
return PTR_ERR(cs4270->reset_gpio);
}
if (cs4270->reset_gpio) {
dev_dbg(&i2c_client->dev, "Found reset GPIO\n");
gpiod_set_value_cansleep(cs4270->reset_gpio, 1);
}
/* Sleep 500ns before i2c communications */
ndelay(500);
cs4270->regmap = devm_regmap_init_i2c(i2c_client, &cs4270_regmap);
if (IS_ERR(cs4270->regmap))
return PTR_ERR(cs4270->regmap);
/* Verify that we have a CS4270 */
ret = regmap_read(cs4270->regmap, CS4270_CHIPID, &val);
if (ret < 0) {
dev_err(&i2c_client->dev, "failed to read i2c at addr %X\n",
i2c_client->addr);
return ret;
}
/* The top four bits of the chip ID should be 1100. */
if ((val & 0xF0) != 0xC0) {
dev_err(&i2c_client->dev, "device at addr %X is not a CS4270\n",
i2c_client->addr);
return -ENODEV;
}
dev_info(&i2c_client->dev, "found device at i2c address %X\n",
i2c_client->addr);
dev_info(&i2c_client->dev, "hardware revision %X\n", val & 0xF);
i2c_set_clientdata(i2c_client, cs4270);
ret = devm_snd_soc_register_component(&i2c_client->dev,
&soc_component_device_cs4270, &cs4270_dai, 1);
return ret;
}
/*
* cs4270_id - I2C device IDs supported by this driver
*/
static const struct i2c_device_id cs4270_id[] = {
{"cs4270", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, cs4270_id);
/*
* cs4270_i2c_driver - I2C device identification
*
* This structure tells the I2C subsystem how to identify and support a
* given I2C device type.
*/
static struct i2c_driver cs4270_i2c_driver = {
.driver = {
.name = "cs4270",
.of_match_table = cs4270_of_match,
},
.id_table = cs4270_id,
.probe = cs4270_i2c_probe,
.remove = cs4270_i2c_remove,
};
module_i2c_driver(cs4270_i2c_driver);
MODULE_AUTHOR("Timur Tabi <[email protected]>");
MODULE_DESCRIPTION("Cirrus Logic CS4270 ALSA SoC Codec Driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cs4270.c |
// SPDX-License-Identifier: GPL-2.0
//
// rt700-sdw.c -- rt700 ALSA SoC audio driver
//
// Copyright(c) 2019 Realtek Semiconductor Corp.
//
//
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/mod_devicetable.h>
#include <linux/soundwire/sdw.h>
#include <linux/soundwire/sdw_type.h>
#include <linux/soundwire/sdw_registers.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include "rt700.h"
#include "rt700-sdw.h"
static bool rt700_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x00e0:
case 0x00f0:
case 0x2000 ... 0x200e:
case 0x2012 ... 0x2016:
case 0x201a ... 0x2027:
case 0x2029 ... 0x202a:
case 0x202d ... 0x2034:
case 0x2200 ... 0x2204:
case 0x2206 ... 0x2212:
case 0x2220 ... 0x2223:
case 0x2230 ... 0x2231:
case 0x3000 ... 0x3fff:
case 0x7000 ... 0x7fff:
case 0x8300 ... 0x83ff:
case 0x9c00 ... 0x9cff:
case 0xb900 ... 0xb9ff:
case 0x75201a:
case 0x752045:
case 0x752046:
case 0x752048:
case 0x75204a:
case 0x75206b:
case 0x752080:
case 0x752081:
return true;
default:
return false;
}
}
static bool rt700_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x2009:
case 0x2016:
case 0x201b:
case 0x201c:
case 0x201d:
case 0x201f:
case 0x2021:
case 0x2023:
case 0x2230:
case 0x200b ... 0x200e: /* i2c read */
case 0x2012 ... 0x2015: /* HD-A read */
case 0x202d ... 0x202f: /* BRA */
case 0x2201 ... 0x2212: /* i2c debug */
case 0x2220 ... 0x2223: /* decoded HD-A */
case 0x9c00 ... 0x9cff:
case 0xb900 ... 0xb9ff:
case 0xff01:
case 0x75201a:
case 0x752046:
case 0x752080:
case 0x752081:
return true;
default:
return false;
}
}
static int rt700_sdw_read(void *context, unsigned int reg, unsigned int *val)
{
struct device *dev = context;
struct rt700_priv *rt700 = dev_get_drvdata(dev);
unsigned int sdw_data_3, sdw_data_2, sdw_data_1, sdw_data_0;
unsigned int reg2 = 0, reg3 = 0, reg4 = 0, mask, nid, val2;
unsigned int is_hda_reg = 1, is_index_reg = 0;
int ret;
if (reg > 0xffff)
is_index_reg = 1;
mask = reg & 0xf000;
if (is_index_reg) { /* index registers */
val2 = reg & 0xff;
reg = reg >> 8;
nid = reg & 0xff;
ret = regmap_write(rt700->sdw_regmap, reg, 0);
if (ret < 0)
return ret;
reg2 = reg + 0x1000;
reg2 |= 0x80;
ret = regmap_write(rt700->sdw_regmap, reg2, val2);
if (ret < 0)
return ret;
reg3 = RT700_PRIV_DATA_R_H | nid;
ret = regmap_write(rt700->sdw_regmap,
reg3, ((*val >> 8) & 0xff));
if (ret < 0)
return ret;
reg4 = reg3 + 0x1000;
reg4 |= 0x80;
ret = regmap_write(rt700->sdw_regmap, reg4, (*val & 0xff));
if (ret < 0)
return ret;
} else if (mask == 0x3000) {
reg += 0x8000;
ret = regmap_write(rt700->sdw_regmap, reg, *val);
if (ret < 0)
return ret;
} else if (mask == 0x7000) {
reg += 0x2000;
reg |= 0x800;
ret = regmap_write(rt700->sdw_regmap,
reg, ((*val >> 8) & 0xff));
if (ret < 0)
return ret;
reg2 = reg + 0x1000;
reg2 |= 0x80;
ret = regmap_write(rt700->sdw_regmap, reg2, (*val & 0xff));
if (ret < 0)
return ret;
} else if ((reg & 0xff00) == 0x8300) { /* for R channel */
reg2 = reg - 0x1000;
reg2 &= ~0x80;
ret = regmap_write(rt700->sdw_regmap,
reg2, ((*val >> 8) & 0xff));
if (ret < 0)
return ret;
ret = regmap_write(rt700->sdw_regmap, reg, (*val & 0xff));
if (ret < 0)
return ret;
} else if (mask == 0x9000) {
ret = regmap_write(rt700->sdw_regmap,
reg, ((*val >> 8) & 0xff));
if (ret < 0)
return ret;
reg2 = reg + 0x1000;
reg2 |= 0x80;
ret = regmap_write(rt700->sdw_regmap, reg2, (*val & 0xff));
if (ret < 0)
return ret;
} else if (mask == 0xb000) {
ret = regmap_write(rt700->sdw_regmap, reg, *val);
if (ret < 0)
return ret;
} else {
ret = regmap_read(rt700->sdw_regmap, reg, val);
if (ret < 0)
return ret;
is_hda_reg = 0;
}
if (is_hda_reg || is_index_reg) {
sdw_data_3 = 0;
sdw_data_2 = 0;
sdw_data_1 = 0;
sdw_data_0 = 0;
ret = regmap_read(rt700->sdw_regmap,
RT700_READ_HDA_3, &sdw_data_3);
if (ret < 0)
return ret;
ret = regmap_read(rt700->sdw_regmap,
RT700_READ_HDA_2, &sdw_data_2);
if (ret < 0)
return ret;
ret = regmap_read(rt700->sdw_regmap,
RT700_READ_HDA_1, &sdw_data_1);
if (ret < 0)
return ret;
ret = regmap_read(rt700->sdw_regmap,
RT700_READ_HDA_0, &sdw_data_0);
if (ret < 0)
return ret;
*val = ((sdw_data_3 & 0xff) << 24) |
((sdw_data_2 & 0xff) << 16) |
((sdw_data_1 & 0xff) << 8) | (sdw_data_0 & 0xff);
}
if (is_hda_reg == 0)
dev_dbg(dev, "[%s] %04x => %08x\n", __func__, reg, *val);
else if (is_index_reg)
dev_dbg(dev, "[%s] %04x %04x %04x %04x => %08x\n",
__func__, reg, reg2, reg3, reg4, *val);
else
dev_dbg(dev, "[%s] %04x %04x => %08x\n",
__func__, reg, reg2, *val);
return 0;
}
static int rt700_sdw_write(void *context, unsigned int reg, unsigned int val)
{
struct device *dev = context;
struct rt700_priv *rt700 = dev_get_drvdata(dev);
unsigned int reg2 = 0, reg3, reg4, nid, mask, val2;
unsigned int is_index_reg = 0;
int ret;
if (reg > 0xffff)
is_index_reg = 1;
mask = reg & 0xf000;
if (is_index_reg) { /* index registers */
val2 = reg & 0xff;
reg = reg >> 8;
nid = reg & 0xff;
ret = regmap_write(rt700->sdw_regmap, reg, 0);
if (ret < 0)
return ret;
reg2 = reg + 0x1000;
reg2 |= 0x80;
ret = regmap_write(rt700->sdw_regmap, reg2, val2);
if (ret < 0)
return ret;
reg3 = RT700_PRIV_DATA_W_H | nid;
ret = regmap_write(rt700->sdw_regmap,
reg3, ((val >> 8) & 0xff));
if (ret < 0)
return ret;
reg4 = reg3 + 0x1000;
reg4 |= 0x80;
ret = regmap_write(rt700->sdw_regmap, reg4, (val & 0xff));
if (ret < 0)
return ret;
is_index_reg = 1;
} else if (reg < 0x4fff) {
ret = regmap_write(rt700->sdw_regmap, reg, val);
if (ret < 0)
return ret;
} else if (reg == 0xff01) {
ret = regmap_write(rt700->sdw_regmap, reg, val);
if (ret < 0)
return ret;
} else if (mask == 0x7000) {
ret = regmap_write(rt700->sdw_regmap,
reg, ((val >> 8) & 0xff));
if (ret < 0)
return ret;
reg2 = reg + 0x1000;
reg2 |= 0x80;
ret = regmap_write(rt700->sdw_regmap, reg2, (val & 0xff));
if (ret < 0)
return ret;
} else if ((reg & 0xff00) == 0x8300) { /* for R channel */
reg2 = reg - 0x1000;
reg2 &= ~0x80;
ret = regmap_write(rt700->sdw_regmap,
reg2, ((val >> 8) & 0xff));
if (ret < 0)
return ret;
ret = regmap_write(rt700->sdw_regmap, reg, (val & 0xff));
if (ret < 0)
return ret;
}
if (reg2 == 0)
dev_dbg(dev, "[%s] %04x <= %04x\n", __func__, reg, val);
else if (is_index_reg)
dev_dbg(dev, "[%s] %04x %04x %04x %04x <= %04x %04x\n",
__func__, reg, reg2, reg3, reg4, val2, val);
else
dev_dbg(dev, "[%s] %04x %04x <= %04x\n",
__func__, reg, reg2, val);
return 0;
}
static const struct regmap_config rt700_regmap = {
.reg_bits = 24,
.val_bits = 32,
.readable_reg = rt700_readable_register,
.volatile_reg = rt700_volatile_register,
.max_register = 0x755800,
.reg_defaults = rt700_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(rt700_reg_defaults),
.cache_type = REGCACHE_MAPLE,
.use_single_read = true,
.use_single_write = true,
.reg_read = rt700_sdw_read,
.reg_write = rt700_sdw_write,
};
static const struct regmap_config rt700_sdw_regmap = {
.name = "sdw",
.reg_bits = 32,
.val_bits = 8,
.readable_reg = rt700_readable_register,
.max_register = 0xff01,
.cache_type = REGCACHE_NONE,
.use_single_read = true,
.use_single_write = true,
};
static int rt700_update_status(struct sdw_slave *slave,
enum sdw_slave_status status)
{
struct rt700_priv *rt700 = dev_get_drvdata(&slave->dev);
if (status == SDW_SLAVE_UNATTACHED)
rt700->hw_init = false;
/*
* Perform initialization only if slave status is present and
* hw_init flag is false
*/
if (rt700->hw_init || status != SDW_SLAVE_ATTACHED)
return 0;
/* perform I/O transfers required for Slave initialization */
return rt700_io_init(&slave->dev, slave);
}
static int rt700_read_prop(struct sdw_slave *slave)
{
struct sdw_slave_prop *prop = &slave->prop;
int nval, i;
u32 bit;
unsigned long addr;
struct sdw_dpn_prop *dpn;
prop->scp_int1_mask = SDW_SCP_INT1_IMPL_DEF | SDW_SCP_INT1_BUS_CLASH |
SDW_SCP_INT1_PARITY;
prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
prop->paging_support = false;
/* first we need to allocate memory for set bits in port lists */
prop->source_ports = 0x14; /* BITMAP: 00010100 */
prop->sink_ports = 0xA; /* BITMAP: 00001010 */
nval = hweight32(prop->source_ports);
prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
sizeof(*prop->src_dpn_prop),
GFP_KERNEL);
if (!prop->src_dpn_prop)
return -ENOMEM;
i = 0;
dpn = prop->src_dpn_prop;
addr = prop->source_ports;
for_each_set_bit(bit, &addr, 32) {
dpn[i].num = bit;
dpn[i].type = SDW_DPN_FULL;
dpn[i].simple_ch_prep_sm = true;
dpn[i].ch_prep_timeout = 10;
i++;
}
/* do this again for sink now */
nval = hweight32(prop->sink_ports);
prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
sizeof(*prop->sink_dpn_prop),
GFP_KERNEL);
if (!prop->sink_dpn_prop)
return -ENOMEM;
i = 0;
dpn = prop->sink_dpn_prop;
addr = prop->sink_ports;
for_each_set_bit(bit, &addr, 32) {
dpn[i].num = bit;
dpn[i].type = SDW_DPN_FULL;
dpn[i].simple_ch_prep_sm = true;
dpn[i].ch_prep_timeout = 10;
i++;
}
/* set the timeout values */
prop->clk_stop_timeout = 20;
/* wake-up event */
prop->wake_capable = 1;
return 0;
}
static int rt700_bus_config(struct sdw_slave *slave,
struct sdw_bus_params *params)
{
struct rt700_priv *rt700 = dev_get_drvdata(&slave->dev);
int ret;
memcpy(&rt700->params, params, sizeof(*params));
ret = rt700_clock_config(&slave->dev);
if (ret < 0)
dev_err(&slave->dev, "Invalid clk config");
return ret;
}
static int rt700_interrupt_callback(struct sdw_slave *slave,
struct sdw_slave_intr_status *status)
{
struct rt700_priv *rt700 = dev_get_drvdata(&slave->dev);
dev_dbg(&slave->dev,
"%s control_port_stat=%x", __func__, status->control_port);
mutex_lock(&rt700->disable_irq_lock);
if (status->control_port & 0x4 && !rt700->disable_irq) {
mod_delayed_work(system_power_efficient_wq,
&rt700->jack_detect_work, msecs_to_jiffies(250));
}
mutex_unlock(&rt700->disable_irq_lock);
return 0;
}
/*
* slave_ops: callbacks for get_clock_stop_mode, clock_stop and
* port_prep are not defined for now
*/
static const struct sdw_slave_ops rt700_slave_ops = {
.read_prop = rt700_read_prop,
.interrupt_callback = rt700_interrupt_callback,
.update_status = rt700_update_status,
.bus_config = rt700_bus_config,
};
static int rt700_sdw_probe(struct sdw_slave *slave,
const struct sdw_device_id *id)
{
struct regmap *sdw_regmap, *regmap;
/* Regmap Initialization */
sdw_regmap = devm_regmap_init_sdw(slave, &rt700_sdw_regmap);
if (IS_ERR(sdw_regmap))
return PTR_ERR(sdw_regmap);
regmap = devm_regmap_init(&slave->dev, NULL,
&slave->dev, &rt700_regmap);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return rt700_init(&slave->dev, sdw_regmap, regmap, slave);
}
static int rt700_sdw_remove(struct sdw_slave *slave)
{
struct rt700_priv *rt700 = dev_get_drvdata(&slave->dev);
if (rt700->hw_init) {
cancel_delayed_work_sync(&rt700->jack_detect_work);
cancel_delayed_work_sync(&rt700->jack_btn_check_work);
}
pm_runtime_disable(&slave->dev);
return 0;
}
static const struct sdw_device_id rt700_id[] = {
SDW_SLAVE_ENTRY_EXT(0x025d, 0x700, 0x1, 0, 0),
{},
};
MODULE_DEVICE_TABLE(sdw, rt700_id);
static int __maybe_unused rt700_dev_suspend(struct device *dev)
{
struct rt700_priv *rt700 = dev_get_drvdata(dev);
if (!rt700->hw_init)
return 0;
cancel_delayed_work_sync(&rt700->jack_detect_work);
cancel_delayed_work_sync(&rt700->jack_btn_check_work);
regcache_cache_only(rt700->regmap, true);
return 0;
}
static int __maybe_unused rt700_dev_system_suspend(struct device *dev)
{
struct sdw_slave *slave = dev_to_sdw_dev(dev);
struct rt700_priv *rt700 = dev_get_drvdata(dev);
int ret;
if (!rt700->hw_init)
return 0;
/*
* prevent new interrupts from being handled after the
* deferred work completes and before the parent disables
* interrupts on the link
*/
mutex_lock(&rt700->disable_irq_lock);
rt700->disable_irq = true;
ret = sdw_update_no_pm(slave, SDW_SCP_INTMASK1,
SDW_SCP_INT1_IMPL_DEF, 0);
mutex_unlock(&rt700->disable_irq_lock);
if (ret < 0) {
/* log but don't prevent suspend from happening */
dev_dbg(&slave->dev, "%s: could not disable imp-def interrupts\n:", __func__);
}
return rt700_dev_suspend(dev);
}
#define RT700_PROBE_TIMEOUT 5000
static int __maybe_unused rt700_dev_resume(struct device *dev)
{
struct sdw_slave *slave = dev_to_sdw_dev(dev);
struct rt700_priv *rt700 = dev_get_drvdata(dev);
unsigned long time;
if (!rt700->first_hw_init)
return 0;
if (!slave->unattach_request)
goto regmap_sync;
time = wait_for_completion_timeout(&slave->initialization_complete,
msecs_to_jiffies(RT700_PROBE_TIMEOUT));
if (!time) {
dev_err(&slave->dev, "Initialization not complete, timed out\n");
sdw_show_ping_status(slave->bus, true);
return -ETIMEDOUT;
}
regmap_sync:
slave->unattach_request = 0;
regcache_cache_only(rt700->regmap, false);
regcache_sync_region(rt700->regmap, 0x3000, 0x8fff);
regcache_sync_region(rt700->regmap, 0x752010, 0x75206b);
return 0;
}
static const struct dev_pm_ops rt700_pm = {
SET_SYSTEM_SLEEP_PM_OPS(rt700_dev_system_suspend, rt700_dev_resume)
SET_RUNTIME_PM_OPS(rt700_dev_suspend, rt700_dev_resume, NULL)
};
static struct sdw_driver rt700_sdw_driver = {
.driver = {
.name = "rt700",
.owner = THIS_MODULE,
.pm = &rt700_pm,
},
.probe = rt700_sdw_probe,
.remove = rt700_sdw_remove,
.ops = &rt700_slave_ops,
.id_table = rt700_id,
};
module_sdw_driver(rt700_sdw_driver);
MODULE_DESCRIPTION("ASoC RT700 driver SDW");
MODULE_AUTHOR("Shuming Fan <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/rt700-sdw.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* TAS5086 ASoC codec driver
*
* Copyright (c) 2013 Daniel Mack <[email protected]>
*
* TODO:
* - implement DAPM and input muxing
* - implement modulation limit
* - implement non-default PWM start
*
* Note that this chip has a very unusual register layout, specifically
* because the registers are of unequal size, and multi-byte registers
* require bulk writes to take effect. Regmap does not support that kind
* of devices.
*
* Currently, the driver does not touch any of the registers >= 0x20, so
* it doesn't matter because the entire map can be accessed as 8-bit
* array. In case more features will be added in the future
* that require access to higher registers, the entire regmap H/W I/O
* routines have to be open-coded.
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/spi/spi.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <sound/tas5086.h>
#define TAS5086_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_3LE)
#define TAS5086_PCM_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | \
SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | \
SNDRV_PCM_RATE_192000)
/*
* TAS5086 registers
*/
#define TAS5086_CLOCK_CONTROL 0x00 /* Clock control register */
#define TAS5086_CLOCK_RATE(val) (val << 5)
#define TAS5086_CLOCK_RATE_MASK (0x7 << 5)
#define TAS5086_CLOCK_RATIO(val) (val << 2)
#define TAS5086_CLOCK_RATIO_MASK (0x7 << 2)
#define TAS5086_CLOCK_SCLK_RATIO_48 (1 << 1)
#define TAS5086_CLOCK_VALID (1 << 0)
#define TAS5086_DEEMPH_MASK 0x03
#define TAS5086_SOFT_MUTE_ALL 0x3f
#define TAS5086_DEV_ID 0x01 /* Device ID register */
#define TAS5086_ERROR_STATUS 0x02 /* Error status register */
#define TAS5086_SYS_CONTROL_1 0x03 /* System control register 1 */
#define TAS5086_SERIAL_DATA_IF 0x04 /* Serial data interface register */
#define TAS5086_SYS_CONTROL_2 0x05 /* System control register 2 */
#define TAS5086_SOFT_MUTE 0x06 /* Soft mute register */
#define TAS5086_MASTER_VOL 0x07 /* Master volume */
#define TAS5086_CHANNEL_VOL(X) (0x08 + (X)) /* Channel 1-6 volume */
#define TAS5086_VOLUME_CONTROL 0x09 /* Volume control register */
#define TAS5086_MOD_LIMIT 0x10 /* Modulation limit register */
#define TAS5086_PWM_START 0x18 /* PWM start register */
#define TAS5086_SURROUND 0x19 /* Surround register */
#define TAS5086_SPLIT_CAP_CHARGE 0x1a /* Split cap charge period register */
#define TAS5086_OSC_TRIM 0x1b /* Oscillator trim register */
#define TAS5086_BKNDERR 0x1c
#define TAS5086_INPUT_MUX 0x20
#define TAS5086_PWM_OUTPUT_MUX 0x25
#define TAS5086_MAX_REGISTER TAS5086_PWM_OUTPUT_MUX
#define TAS5086_PWM_START_MIDZ_FOR_START_1 (1 << 7)
#define TAS5086_PWM_START_MIDZ_FOR_START_2 (1 << 6)
#define TAS5086_PWM_START_CHANNEL_MASK (0x3f)
/*
* Default TAS5086 power-up configuration
*/
static const struct reg_default tas5086_reg_defaults[] = {
{ 0x00, 0x6c },
{ 0x01, 0x03 },
{ 0x02, 0x00 },
{ 0x03, 0xa0 },
{ 0x04, 0x05 },
{ 0x05, 0x60 },
{ 0x06, 0x00 },
{ 0x07, 0xff },
{ 0x08, 0x30 },
{ 0x09, 0x30 },
{ 0x0a, 0x30 },
{ 0x0b, 0x30 },
{ 0x0c, 0x30 },
{ 0x0d, 0x30 },
{ 0x0e, 0xb1 },
{ 0x0f, 0x00 },
{ 0x10, 0x02 },
{ 0x11, 0x00 },
{ 0x12, 0x00 },
{ 0x13, 0x00 },
{ 0x14, 0x00 },
{ 0x15, 0x00 },
{ 0x16, 0x00 },
{ 0x17, 0x00 },
{ 0x18, 0x3f },
{ 0x19, 0x00 },
{ 0x1a, 0x18 },
{ 0x1b, 0x82 },
{ 0x1c, 0x05 },
};
static int tas5086_register_size(struct device *dev, unsigned int reg)
{
switch (reg) {
case TAS5086_CLOCK_CONTROL ... TAS5086_BKNDERR:
return 1;
case TAS5086_INPUT_MUX:
case TAS5086_PWM_OUTPUT_MUX:
return 4;
}
dev_err(dev, "Unsupported register address: %d\n", reg);
return 0;
}
static bool tas5086_accessible_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x0f:
case 0x11 ... 0x17:
case 0x1d ... 0x1f:
return false;
default:
return true;
}
}
static bool tas5086_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TAS5086_DEV_ID:
case TAS5086_ERROR_STATUS:
return true;
}
return false;
}
static bool tas5086_writeable_reg(struct device *dev, unsigned int reg)
{
return tas5086_accessible_reg(dev, reg) && (reg != TAS5086_DEV_ID);
}
static int tas5086_reg_write(void *context, unsigned int reg,
unsigned int value)
{
struct i2c_client *client = context;
unsigned int i, size;
uint8_t buf[5];
int ret;
size = tas5086_register_size(&client->dev, reg);
if (size == 0)
return -EINVAL;
buf[0] = reg;
for (i = size; i >= 1; --i) {
buf[i] = value;
value >>= 8;
}
ret = i2c_master_send(client, buf, size + 1);
if (ret == size + 1)
return 0;
else if (ret < 0)
return ret;
else
return -EIO;
}
static int tas5086_reg_read(void *context, unsigned int reg,
unsigned int *value)
{
struct i2c_client *client = context;
uint8_t send_buf, recv_buf[4];
struct i2c_msg msgs[2];
unsigned int size;
unsigned int i;
int ret;
size = tas5086_register_size(&client->dev, reg);
if (size == 0)
return -EINVAL;
send_buf = reg;
msgs[0].addr = client->addr;
msgs[0].len = sizeof(send_buf);
msgs[0].buf = &send_buf;
msgs[0].flags = 0;
msgs[1].addr = client->addr;
msgs[1].len = size;
msgs[1].buf = recv_buf;
msgs[1].flags = I2C_M_RD;
ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
if (ret < 0)
return ret;
else if (ret != ARRAY_SIZE(msgs))
return -EIO;
*value = 0;
for (i = 0; i < size; i++) {
*value <<= 8;
*value |= recv_buf[i];
}
return 0;
}
static const char * const supply_names[] = {
"dvdd", "avdd"
};
struct tas5086_private {
struct regmap *regmap;
unsigned int mclk, sclk;
unsigned int format;
bool deemph;
unsigned int charge_period;
unsigned int pwm_start_mid_z;
/* Current sample rate for de-emphasis control */
int rate;
/* GPIO driving Reset pin, if any */
int gpio_nreset;
struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
};
static int tas5086_deemph[] = { 0, 32000, 44100, 48000 };
static int tas5086_set_deemph(struct snd_soc_component *component)
{
struct tas5086_private *priv = snd_soc_component_get_drvdata(component);
int i, val = 0;
if (priv->deemph) {
for (i = 0; i < ARRAY_SIZE(tas5086_deemph); i++) {
if (tas5086_deemph[i] == priv->rate) {
val = i;
break;
}
}
}
return regmap_update_bits(priv->regmap, TAS5086_SYS_CONTROL_1,
TAS5086_DEEMPH_MASK, val);
}
static int tas5086_get_deemph(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct tas5086_private *priv = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = priv->deemph;
return 0;
}
static int tas5086_put_deemph(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct tas5086_private *priv = snd_soc_component_get_drvdata(component);
priv->deemph = ucontrol->value.integer.value[0];
return tas5086_set_deemph(component);
}
static int tas5086_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct tas5086_private *priv = snd_soc_component_get_drvdata(component);
switch (clk_id) {
case TAS5086_CLK_IDX_MCLK:
priv->mclk = freq;
break;
case TAS5086_CLK_IDX_SCLK:
priv->sclk = freq;
break;
}
return 0;
}
static int tas5086_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int format)
{
struct snd_soc_component *component = codec_dai->component;
struct tas5086_private *priv = snd_soc_component_get_drvdata(component);
/* The TAS5086 can only be slave to all clocks */
if ((format & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) != SND_SOC_DAIFMT_CBC_CFC) {
dev_err(component->dev, "Invalid clocking mode\n");
return -EINVAL;
}
/* we need to refer to the data format from hw_params() */
priv->format = format;
return 0;
}
static const int tas5086_sample_rates[] = {
32000, 38000, 44100, 48000, 88200, 96000, 176400, 192000
};
static const int tas5086_ratios[] = {
64, 128, 192, 256, 384, 512
};
static int index_in_array(const int *array, int len, int needle)
{
int i;
for (i = 0; i < len; i++)
if (array[i] == needle)
return i;
return -ENOENT;
}
static int tas5086_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct tas5086_private *priv = snd_soc_component_get_drvdata(component);
int val;
int ret;
priv->rate = params_rate(params);
/* Look up the sample rate and refer to the offset in the list */
val = index_in_array(tas5086_sample_rates,
ARRAY_SIZE(tas5086_sample_rates), priv->rate);
if (val < 0) {
dev_err(component->dev, "Invalid sample rate\n");
return -EINVAL;
}
ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL,
TAS5086_CLOCK_RATE_MASK,
TAS5086_CLOCK_RATE(val));
if (ret < 0)
return ret;
/* MCLK / Fs ratio */
val = index_in_array(tas5086_ratios, ARRAY_SIZE(tas5086_ratios),
priv->mclk / priv->rate);
if (val < 0) {
dev_err(component->dev, "Invalid MCLK / Fs ratio\n");
return -EINVAL;
}
ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL,
TAS5086_CLOCK_RATIO_MASK,
TAS5086_CLOCK_RATIO(val));
if (ret < 0)
return ret;
ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL,
TAS5086_CLOCK_SCLK_RATIO_48,
(priv->sclk == 48 * priv->rate) ?
TAS5086_CLOCK_SCLK_RATIO_48 : 0);
if (ret < 0)
return ret;
/*
* The chip has a very unituitive register mapping and muxes information
* about data format and sample depth into the same register, but not on
* a logical bit-boundary. Hence, we have to refer to the format passed
* in the set_dai_fmt() callback and set up everything from here.
*
* First, determine the 'base' value, using the format ...
*/
switch (priv->format & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_RIGHT_J:
val = 0x00;
break;
case SND_SOC_DAIFMT_I2S:
val = 0x03;
break;
case SND_SOC_DAIFMT_LEFT_J:
val = 0x06;
break;
default:
dev_err(component->dev, "Invalid DAI format\n");
return -EINVAL;
}
/* ... then add the offset for the sample bit depth. */
switch (params_width(params)) {
case 16:
val += 0;
break;
case 20:
val += 1;
break;
case 24:
val += 2;
break;
default:
dev_err(component->dev, "Invalid bit width\n");
return -EINVAL;
}
ret = regmap_write(priv->regmap, TAS5086_SERIAL_DATA_IF, val);
if (ret < 0)
return ret;
/* clock is considered valid now */
ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL,
TAS5086_CLOCK_VALID, TAS5086_CLOCK_VALID);
if (ret < 0)
return ret;
return tas5086_set_deemph(component);
}
static int tas5086_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
{
struct snd_soc_component *component = dai->component;
struct tas5086_private *priv = snd_soc_component_get_drvdata(component);
unsigned int val = 0;
if (mute)
val = TAS5086_SOFT_MUTE_ALL;
return regmap_write(priv->regmap, TAS5086_SOFT_MUTE, val);
}
static void tas5086_reset(struct tas5086_private *priv)
{
if (gpio_is_valid(priv->gpio_nreset)) {
/* Reset codec - minimum assertion time is 400ns */
gpio_direction_output(priv->gpio_nreset, 0);
udelay(1);
gpio_set_value(priv->gpio_nreset, 1);
/* Codec needs ~15ms to wake up */
msleep(15);
}
}
/* charge period values in microseconds */
static const int tas5086_charge_period[] = {
13000, 16900, 23400, 31200, 41600, 54600, 72800, 96200,
130000, 156000, 234000, 312000, 416000, 546000, 728000, 962000,
1300000, 169000, 2340000, 3120000, 4160000, 5460000, 7280000, 9620000,
};
static int tas5086_init(struct device *dev, struct tas5086_private *priv)
{
int ret, i;
/*
* If any of the channels is configured to start in Mid-Z mode,
* configure 'part 1' of the PWM starts to use Mid-Z, and tell
* all configured mid-z channels to start under 'part 1'.
*/
if (priv->pwm_start_mid_z)
regmap_write(priv->regmap, TAS5086_PWM_START,
TAS5086_PWM_START_MIDZ_FOR_START_1 |
priv->pwm_start_mid_z);
/* lookup and set split-capacitor charge period */
if (priv->charge_period == 0) {
regmap_write(priv->regmap, TAS5086_SPLIT_CAP_CHARGE, 0);
} else {
i = index_in_array(tas5086_charge_period,
ARRAY_SIZE(tas5086_charge_period),
priv->charge_period);
if (i >= 0)
regmap_write(priv->regmap, TAS5086_SPLIT_CAP_CHARGE,
i + 0x08);
else
dev_warn(dev,
"Invalid split-cap charge period of %d ns.\n",
priv->charge_period);
}
/* enable factory trim */
ret = regmap_write(priv->regmap, TAS5086_OSC_TRIM, 0x00);
if (ret < 0)
return ret;
/* start all channels */
ret = regmap_write(priv->regmap, TAS5086_SYS_CONTROL_2, 0x20);
if (ret < 0)
return ret;
/* mute all channels for now */
ret = regmap_write(priv->regmap, TAS5086_SOFT_MUTE,
TAS5086_SOFT_MUTE_ALL);
if (ret < 0)
return ret;
return 0;
}
/* TAS5086 controls */
static const DECLARE_TLV_DB_SCALE(tas5086_dac_tlv, -10350, 50, 1);
static const struct snd_kcontrol_new tas5086_controls[] = {
SOC_SINGLE_TLV("Master Playback Volume", TAS5086_MASTER_VOL,
0, 0xff, 1, tas5086_dac_tlv),
SOC_DOUBLE_R_TLV("Channel 1/2 Playback Volume",
TAS5086_CHANNEL_VOL(0), TAS5086_CHANNEL_VOL(1),
0, 0xff, 1, tas5086_dac_tlv),
SOC_DOUBLE_R_TLV("Channel 3/4 Playback Volume",
TAS5086_CHANNEL_VOL(2), TAS5086_CHANNEL_VOL(3),
0, 0xff, 1, tas5086_dac_tlv),
SOC_DOUBLE_R_TLV("Channel 5/6 Playback Volume",
TAS5086_CHANNEL_VOL(4), TAS5086_CHANNEL_VOL(5),
0, 0xff, 1, tas5086_dac_tlv),
SOC_SINGLE_BOOL_EXT("De-emphasis Switch", 0,
tas5086_get_deemph, tas5086_put_deemph),
};
/* Input mux controls */
static const char *tas5086_dapm_sdin_texts[] =
{
"SDIN1-L", "SDIN1-R", "SDIN2-L", "SDIN2-R",
"SDIN3-L", "SDIN3-R", "Ground (0)", "nc"
};
static const struct soc_enum tas5086_dapm_input_mux_enum[] = {
SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 20, 8, tas5086_dapm_sdin_texts),
SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 16, 8, tas5086_dapm_sdin_texts),
SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 12, 8, tas5086_dapm_sdin_texts),
SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 8, 8, tas5086_dapm_sdin_texts),
SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 4, 8, tas5086_dapm_sdin_texts),
SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 0, 8, tas5086_dapm_sdin_texts),
};
static const struct snd_kcontrol_new tas5086_dapm_input_mux_controls[] = {
SOC_DAPM_ENUM("Channel 1 input", tas5086_dapm_input_mux_enum[0]),
SOC_DAPM_ENUM("Channel 2 input", tas5086_dapm_input_mux_enum[1]),
SOC_DAPM_ENUM("Channel 3 input", tas5086_dapm_input_mux_enum[2]),
SOC_DAPM_ENUM("Channel 4 input", tas5086_dapm_input_mux_enum[3]),
SOC_DAPM_ENUM("Channel 5 input", tas5086_dapm_input_mux_enum[4]),
SOC_DAPM_ENUM("Channel 6 input", tas5086_dapm_input_mux_enum[5]),
};
/* Output mux controls */
static const char *tas5086_dapm_channel_texts[] =
{ "Channel 1 Mux", "Channel 2 Mux", "Channel 3 Mux",
"Channel 4 Mux", "Channel 5 Mux", "Channel 6 Mux" };
static const struct soc_enum tas5086_dapm_output_mux_enum[] = {
SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 20, 6, tas5086_dapm_channel_texts),
SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 16, 6, tas5086_dapm_channel_texts),
SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 12, 6, tas5086_dapm_channel_texts),
SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 8, 6, tas5086_dapm_channel_texts),
SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 4, 6, tas5086_dapm_channel_texts),
SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 0, 6, tas5086_dapm_channel_texts),
};
static const struct snd_kcontrol_new tas5086_dapm_output_mux_controls[] = {
SOC_DAPM_ENUM("PWM1 Output", tas5086_dapm_output_mux_enum[0]),
SOC_DAPM_ENUM("PWM2 Output", tas5086_dapm_output_mux_enum[1]),
SOC_DAPM_ENUM("PWM3 Output", tas5086_dapm_output_mux_enum[2]),
SOC_DAPM_ENUM("PWM4 Output", tas5086_dapm_output_mux_enum[3]),
SOC_DAPM_ENUM("PWM5 Output", tas5086_dapm_output_mux_enum[4]),
SOC_DAPM_ENUM("PWM6 Output", tas5086_dapm_output_mux_enum[5]),
};
static const struct snd_soc_dapm_widget tas5086_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("SDIN1-L"),
SND_SOC_DAPM_INPUT("SDIN1-R"),
SND_SOC_DAPM_INPUT("SDIN2-L"),
SND_SOC_DAPM_INPUT("SDIN2-R"),
SND_SOC_DAPM_INPUT("SDIN3-L"),
SND_SOC_DAPM_INPUT("SDIN3-R"),
SND_SOC_DAPM_INPUT("SDIN4-L"),
SND_SOC_DAPM_INPUT("SDIN4-R"),
SND_SOC_DAPM_OUTPUT("PWM1"),
SND_SOC_DAPM_OUTPUT("PWM2"),
SND_SOC_DAPM_OUTPUT("PWM3"),
SND_SOC_DAPM_OUTPUT("PWM4"),
SND_SOC_DAPM_OUTPUT("PWM5"),
SND_SOC_DAPM_OUTPUT("PWM6"),
SND_SOC_DAPM_MUX("Channel 1 Mux", SND_SOC_NOPM, 0, 0,
&tas5086_dapm_input_mux_controls[0]),
SND_SOC_DAPM_MUX("Channel 2 Mux", SND_SOC_NOPM, 0, 0,
&tas5086_dapm_input_mux_controls[1]),
SND_SOC_DAPM_MUX("Channel 3 Mux", SND_SOC_NOPM, 0, 0,
&tas5086_dapm_input_mux_controls[2]),
SND_SOC_DAPM_MUX("Channel 4 Mux", SND_SOC_NOPM, 0, 0,
&tas5086_dapm_input_mux_controls[3]),
SND_SOC_DAPM_MUX("Channel 5 Mux", SND_SOC_NOPM, 0, 0,
&tas5086_dapm_input_mux_controls[4]),
SND_SOC_DAPM_MUX("Channel 6 Mux", SND_SOC_NOPM, 0, 0,
&tas5086_dapm_input_mux_controls[5]),
SND_SOC_DAPM_MUX("PWM1 Mux", SND_SOC_NOPM, 0, 0,
&tas5086_dapm_output_mux_controls[0]),
SND_SOC_DAPM_MUX("PWM2 Mux", SND_SOC_NOPM, 0, 0,
&tas5086_dapm_output_mux_controls[1]),
SND_SOC_DAPM_MUX("PWM3 Mux", SND_SOC_NOPM, 0, 0,
&tas5086_dapm_output_mux_controls[2]),
SND_SOC_DAPM_MUX("PWM4 Mux", SND_SOC_NOPM, 0, 0,
&tas5086_dapm_output_mux_controls[3]),
SND_SOC_DAPM_MUX("PWM5 Mux", SND_SOC_NOPM, 0, 0,
&tas5086_dapm_output_mux_controls[4]),
SND_SOC_DAPM_MUX("PWM6 Mux", SND_SOC_NOPM, 0, 0,
&tas5086_dapm_output_mux_controls[5]),
};
static const struct snd_soc_dapm_route tas5086_dapm_routes[] = {
/* SDIN inputs -> channel muxes */
{ "Channel 1 Mux", "SDIN1-L", "SDIN1-L" },
{ "Channel 1 Mux", "SDIN1-R", "SDIN1-R" },
{ "Channel 1 Mux", "SDIN2-L", "SDIN2-L" },
{ "Channel 1 Mux", "SDIN2-R", "SDIN2-R" },
{ "Channel 1 Mux", "SDIN3-L", "SDIN3-L" },
{ "Channel 1 Mux", "SDIN3-R", "SDIN3-R" },
{ "Channel 2 Mux", "SDIN1-L", "SDIN1-L" },
{ "Channel 2 Mux", "SDIN1-R", "SDIN1-R" },
{ "Channel 2 Mux", "SDIN2-L", "SDIN2-L" },
{ "Channel 2 Mux", "SDIN2-R", "SDIN2-R" },
{ "Channel 2 Mux", "SDIN3-L", "SDIN3-L" },
{ "Channel 2 Mux", "SDIN3-R", "SDIN3-R" },
{ "Channel 2 Mux", "SDIN1-L", "SDIN1-L" },
{ "Channel 2 Mux", "SDIN1-R", "SDIN1-R" },
{ "Channel 2 Mux", "SDIN2-L", "SDIN2-L" },
{ "Channel 2 Mux", "SDIN2-R", "SDIN2-R" },
{ "Channel 2 Mux", "SDIN3-L", "SDIN3-L" },
{ "Channel 2 Mux", "SDIN3-R", "SDIN3-R" },
{ "Channel 3 Mux", "SDIN1-L", "SDIN1-L" },
{ "Channel 3 Mux", "SDIN1-R", "SDIN1-R" },
{ "Channel 3 Mux", "SDIN2-L", "SDIN2-L" },
{ "Channel 3 Mux", "SDIN2-R", "SDIN2-R" },
{ "Channel 3 Mux", "SDIN3-L", "SDIN3-L" },
{ "Channel 3 Mux", "SDIN3-R", "SDIN3-R" },
{ "Channel 4 Mux", "SDIN1-L", "SDIN1-L" },
{ "Channel 4 Mux", "SDIN1-R", "SDIN1-R" },
{ "Channel 4 Mux", "SDIN2-L", "SDIN2-L" },
{ "Channel 4 Mux", "SDIN2-R", "SDIN2-R" },
{ "Channel 4 Mux", "SDIN3-L", "SDIN3-L" },
{ "Channel 4 Mux", "SDIN3-R", "SDIN3-R" },
{ "Channel 5 Mux", "SDIN1-L", "SDIN1-L" },
{ "Channel 5 Mux", "SDIN1-R", "SDIN1-R" },
{ "Channel 5 Mux", "SDIN2-L", "SDIN2-L" },
{ "Channel 5 Mux", "SDIN2-R", "SDIN2-R" },
{ "Channel 5 Mux", "SDIN3-L", "SDIN3-L" },
{ "Channel 5 Mux", "SDIN3-R", "SDIN3-R" },
{ "Channel 6 Mux", "SDIN1-L", "SDIN1-L" },
{ "Channel 6 Mux", "SDIN1-R", "SDIN1-R" },
{ "Channel 6 Mux", "SDIN2-L", "SDIN2-L" },
{ "Channel 6 Mux", "SDIN2-R", "SDIN2-R" },
{ "Channel 6 Mux", "SDIN3-L", "SDIN3-L" },
{ "Channel 6 Mux", "SDIN3-R", "SDIN3-R" },
/* Channel muxes -> PWM muxes */
{ "PWM1 Mux", "Channel 1 Mux", "Channel 1 Mux" },
{ "PWM2 Mux", "Channel 1 Mux", "Channel 1 Mux" },
{ "PWM3 Mux", "Channel 1 Mux", "Channel 1 Mux" },
{ "PWM4 Mux", "Channel 1 Mux", "Channel 1 Mux" },
{ "PWM5 Mux", "Channel 1 Mux", "Channel 1 Mux" },
{ "PWM6 Mux", "Channel 1 Mux", "Channel 1 Mux" },
{ "PWM1 Mux", "Channel 2 Mux", "Channel 2 Mux" },
{ "PWM2 Mux", "Channel 2 Mux", "Channel 2 Mux" },
{ "PWM3 Mux", "Channel 2 Mux", "Channel 2 Mux" },
{ "PWM4 Mux", "Channel 2 Mux", "Channel 2 Mux" },
{ "PWM5 Mux", "Channel 2 Mux", "Channel 2 Mux" },
{ "PWM6 Mux", "Channel 2 Mux", "Channel 2 Mux" },
{ "PWM1 Mux", "Channel 3 Mux", "Channel 3 Mux" },
{ "PWM2 Mux", "Channel 3 Mux", "Channel 3 Mux" },
{ "PWM3 Mux", "Channel 3 Mux", "Channel 3 Mux" },
{ "PWM4 Mux", "Channel 3 Mux", "Channel 3 Mux" },
{ "PWM5 Mux", "Channel 3 Mux", "Channel 3 Mux" },
{ "PWM6 Mux", "Channel 3 Mux", "Channel 3 Mux" },
{ "PWM1 Mux", "Channel 4 Mux", "Channel 4 Mux" },
{ "PWM2 Mux", "Channel 4 Mux", "Channel 4 Mux" },
{ "PWM3 Mux", "Channel 4 Mux", "Channel 4 Mux" },
{ "PWM4 Mux", "Channel 4 Mux", "Channel 4 Mux" },
{ "PWM5 Mux", "Channel 4 Mux", "Channel 4 Mux" },
{ "PWM6 Mux", "Channel 4 Mux", "Channel 4 Mux" },
{ "PWM1 Mux", "Channel 5 Mux", "Channel 5 Mux" },
{ "PWM2 Mux", "Channel 5 Mux", "Channel 5 Mux" },
{ "PWM3 Mux", "Channel 5 Mux", "Channel 5 Mux" },
{ "PWM4 Mux", "Channel 5 Mux", "Channel 5 Mux" },
{ "PWM5 Mux", "Channel 5 Mux", "Channel 5 Mux" },
{ "PWM6 Mux", "Channel 5 Mux", "Channel 5 Mux" },
{ "PWM1 Mux", "Channel 6 Mux", "Channel 6 Mux" },
{ "PWM2 Mux", "Channel 6 Mux", "Channel 6 Mux" },
{ "PWM3 Mux", "Channel 6 Mux", "Channel 6 Mux" },
{ "PWM4 Mux", "Channel 6 Mux", "Channel 6 Mux" },
{ "PWM5 Mux", "Channel 6 Mux", "Channel 6 Mux" },
{ "PWM6 Mux", "Channel 6 Mux", "Channel 6 Mux" },
/* The PWM muxes are directly connected to the PWM outputs */
{ "PWM1", NULL, "PWM1 Mux" },
{ "PWM2", NULL, "PWM2 Mux" },
{ "PWM3", NULL, "PWM3 Mux" },
{ "PWM4", NULL, "PWM4 Mux" },
{ "PWM5", NULL, "PWM5 Mux" },
{ "PWM6", NULL, "PWM6 Mux" },
};
static const struct snd_soc_dai_ops tas5086_dai_ops = {
.hw_params = tas5086_hw_params,
.set_sysclk = tas5086_set_dai_sysclk,
.set_fmt = tas5086_set_dai_fmt,
.mute_stream = tas5086_mute_stream,
};
static struct snd_soc_dai_driver tas5086_dai = {
.name = "tas5086-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 6,
.rates = TAS5086_PCM_RATES,
.formats = TAS5086_PCM_FORMATS,
},
.ops = &tas5086_dai_ops,
};
#ifdef CONFIG_PM
static int tas5086_soc_suspend(struct snd_soc_component *component)
{
struct tas5086_private *priv = snd_soc_component_get_drvdata(component);
int ret;
/* Shut down all channels */
ret = regmap_write(priv->regmap, TAS5086_SYS_CONTROL_2, 0x60);
if (ret < 0)
return ret;
regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies);
return 0;
}
static int tas5086_soc_resume(struct snd_soc_component *component)
{
struct tas5086_private *priv = snd_soc_component_get_drvdata(component);
int ret;
ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
if (ret < 0)
return ret;
tas5086_reset(priv);
regcache_mark_dirty(priv->regmap);
ret = tas5086_init(component->dev, priv);
if (ret < 0)
return ret;
ret = regcache_sync(priv->regmap);
if (ret < 0)
return ret;
return 0;
}
#else
#define tas5086_soc_suspend NULL
#define tas5086_soc_resume NULL
#endif /* CONFIG_PM */
#ifdef CONFIG_OF
static const struct of_device_id tas5086_dt_ids[] = {
{ .compatible = "ti,tas5086", },
{ }
};
MODULE_DEVICE_TABLE(of, tas5086_dt_ids);
#endif
static int tas5086_probe(struct snd_soc_component *component)
{
struct tas5086_private *priv = snd_soc_component_get_drvdata(component);
int i, ret;
ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
if (ret < 0) {
dev_err(component->dev, "Failed to enable regulators: %d\n", ret);
return ret;
}
priv->pwm_start_mid_z = 0;
priv->charge_period = 1300000; /* hardware default is 1300 ms */
if (of_match_device(of_match_ptr(tas5086_dt_ids), component->dev)) {
struct device_node *of_node = component->dev->of_node;
of_property_read_u32(of_node, "ti,charge-period",
&priv->charge_period);
for (i = 0; i < 6; i++) {
char name[25];
snprintf(name, sizeof(name),
"ti,mid-z-channel-%d", i + 1);
if (of_property_read_bool(of_node, name))
priv->pwm_start_mid_z |= 1 << i;
}
}
tas5086_reset(priv);
ret = tas5086_init(component->dev, priv);
if (ret < 0)
goto exit_disable_regulators;
/* set master volume to 0 dB */
ret = regmap_write(priv->regmap, TAS5086_MASTER_VOL, 0x30);
if (ret < 0)
goto exit_disable_regulators;
return 0;
exit_disable_regulators:
regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies);
return ret;
}
static void tas5086_remove(struct snd_soc_component *component)
{
struct tas5086_private *priv = snd_soc_component_get_drvdata(component);
if (gpio_is_valid(priv->gpio_nreset))
/* Set codec to the reset state */
gpio_set_value(priv->gpio_nreset, 0);
regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies);
};
static const struct snd_soc_component_driver soc_component_dev_tas5086 = {
.probe = tas5086_probe,
.remove = tas5086_remove,
.suspend = tas5086_soc_suspend,
.resume = tas5086_soc_resume,
.controls = tas5086_controls,
.num_controls = ARRAY_SIZE(tas5086_controls),
.dapm_widgets = tas5086_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(tas5086_dapm_widgets),
.dapm_routes = tas5086_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(tas5086_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct i2c_device_id tas5086_i2c_id[] = {
{ "tas5086", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, tas5086_i2c_id);
static const struct regmap_config tas5086_regmap = {
.reg_bits = 8,
.val_bits = 32,
.max_register = TAS5086_MAX_REGISTER,
.reg_defaults = tas5086_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tas5086_reg_defaults),
.cache_type = REGCACHE_RBTREE,
.volatile_reg = tas5086_volatile_reg,
.writeable_reg = tas5086_writeable_reg,
.readable_reg = tas5086_accessible_reg,
.reg_read = tas5086_reg_read,
.reg_write = tas5086_reg_write,
};
static int tas5086_i2c_probe(struct i2c_client *i2c)
{
struct tas5086_private *priv;
struct device *dev = &i2c->dev;
int gpio_nreset = -EINVAL;
int i, ret;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
for (i = 0; i < ARRAY_SIZE(supply_names); i++)
priv->supplies[i].supply = supply_names[i];
ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(priv->supplies),
priv->supplies);
if (ret < 0) {
dev_err(dev, "Failed to get regulators: %d\n", ret);
return ret;
}
priv->regmap = devm_regmap_init(dev, NULL, i2c, &tas5086_regmap);
if (IS_ERR(priv->regmap)) {
ret = PTR_ERR(priv->regmap);
dev_err(&i2c->dev, "Failed to create regmap: %d\n", ret);
return ret;
}
i2c_set_clientdata(i2c, priv);
if (of_match_device(of_match_ptr(tas5086_dt_ids), dev)) {
struct device_node *of_node = dev->of_node;
gpio_nreset = of_get_named_gpio(of_node, "reset-gpio", 0);
}
if (gpio_is_valid(gpio_nreset))
if (devm_gpio_request(dev, gpio_nreset, "TAS5086 Reset"))
gpio_nreset = -EINVAL;
priv->gpio_nreset = gpio_nreset;
ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
if (ret < 0) {
dev_err(dev, "Failed to enable regulators: %d\n", ret);
return ret;
}
tas5086_reset(priv);
/* The TAS5086 always returns 0x03 in its TAS5086_DEV_ID register */
ret = regmap_read(priv->regmap, TAS5086_DEV_ID, &i);
if (ret == 0 && i != 0x3) {
dev_err(dev,
"Failed to identify TAS5086 codec (got %02x)\n", i);
ret = -ENODEV;
}
/*
* The chip has been identified, so we can turn off the power
* again until the dai link is set up.
*/
regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies);
if (ret == 0)
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_tas5086,
&tas5086_dai, 1);
return ret;
}
static void tas5086_i2c_remove(struct i2c_client *i2c)
{}
static struct i2c_driver tas5086_i2c_driver = {
.driver = {
.name = "tas5086",
.of_match_table = of_match_ptr(tas5086_dt_ids),
},
.id_table = tas5086_i2c_id,
.probe = tas5086_i2c_probe,
.remove = tas5086_i2c_remove,
};
module_i2c_driver(tas5086_i2c_driver);
MODULE_AUTHOR("Daniel Mack <[email protected]>");
MODULE_DESCRIPTION("Texas Instruments TAS5086 ALSA SoC Codec Driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/tas5086.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8737.c -- WM8737 ALSA SoC Audio driver
*
* Copyright 2010 Wolfson Microelectronics plc
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <linux/of_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "wm8737.h"
#define WM8737_NUM_SUPPLIES 4
static const char *wm8737_supply_names[WM8737_NUM_SUPPLIES] = {
"DCVDD",
"DBVDD",
"AVDD",
"MVDD",
};
/* codec private data */
struct wm8737_priv {
struct regmap *regmap;
struct regulator_bulk_data supplies[WM8737_NUM_SUPPLIES];
unsigned int mclk;
};
static const struct reg_default wm8737_reg_defaults[] = {
{ 0, 0x00C3 }, /* R0 - Left PGA volume */
{ 1, 0x00C3 }, /* R1 - Right PGA volume */
{ 2, 0x0007 }, /* R2 - AUDIO path L */
{ 3, 0x0007 }, /* R3 - AUDIO path R */
{ 4, 0x0000 }, /* R4 - 3D Enhance */
{ 5, 0x0000 }, /* R5 - ADC Control */
{ 6, 0x0000 }, /* R6 - Power Management */
{ 7, 0x000A }, /* R7 - Audio Format */
{ 8, 0x0000 }, /* R8 - Clocking */
{ 9, 0x000F }, /* R9 - MIC Preamp Control */
{ 10, 0x0003 }, /* R10 - Misc Bias Control */
{ 11, 0x0000 }, /* R11 - Noise Gate */
{ 12, 0x007C }, /* R12 - ALC1 */
{ 13, 0x0000 }, /* R13 - ALC2 */
{ 14, 0x0032 }, /* R14 - ALC3 */
};
static bool wm8737_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8737_RESET:
return true;
default:
return false;
}
}
static int wm8737_reset(struct snd_soc_component *component)
{
return snd_soc_component_write(component, WM8737_RESET, 0);
}
static const DECLARE_TLV_DB_RANGE(micboost_tlv,
0, 0, TLV_DB_SCALE_ITEM(1300, 0, 0),
1, 1, TLV_DB_SCALE_ITEM(1800, 0, 0),
2, 2, TLV_DB_SCALE_ITEM(2800, 0, 0),
3, 3, TLV_DB_SCALE_ITEM(3300, 0, 0)
);
static const DECLARE_TLV_DB_SCALE(pga_tlv, -9750, 50, 1);
static const DECLARE_TLV_DB_SCALE(adc_tlv, -600, 600, 0);
static const DECLARE_TLV_DB_SCALE(ng_tlv, -7800, 600, 0);
static const DECLARE_TLV_DB_SCALE(alc_max_tlv, -1200, 600, 0);
static const DECLARE_TLV_DB_SCALE(alc_target_tlv, -1800, 100, 0);
static const char *micbias_enum_text[] = {
"25%",
"50%",
"75%",
"100%",
};
static SOC_ENUM_SINGLE_DECL(micbias_enum,
WM8737_MIC_PREAMP_CONTROL, 0, micbias_enum_text);
static const char *low_cutoff_text[] = {
"Low", "High"
};
static SOC_ENUM_SINGLE_DECL(low_3d,
WM8737_3D_ENHANCE, 6, low_cutoff_text);
static const char *high_cutoff_text[] = {
"High", "Low"
};
static SOC_ENUM_SINGLE_DECL(high_3d,
WM8737_3D_ENHANCE, 5, high_cutoff_text);
static const char *alc_fn_text[] = {
"Disabled", "Right", "Left", "Stereo"
};
static SOC_ENUM_SINGLE_DECL(alc_fn,
WM8737_ALC1, 7, alc_fn_text);
static const char *alc_hold_text[] = {
"0", "2.67ms", "5.33ms", "10.66ms", "21.32ms", "42.64ms", "85.28ms",
"170.56ms", "341.12ms", "682.24ms", "1.364s", "2.728s", "5.458s",
"10.916s", "21.832s", "43.691s"
};
static SOC_ENUM_SINGLE_DECL(alc_hold,
WM8737_ALC2, 0, alc_hold_text);
static const char *alc_atk_text[] = {
"8.4ms", "16.8ms", "33.6ms", "67.2ms", "134.4ms", "268.8ms", "537.6ms",
"1.075s", "2.15s", "4.3s", "8.6s"
};
static SOC_ENUM_SINGLE_DECL(alc_atk,
WM8737_ALC3, 0, alc_atk_text);
static const char *alc_dcy_text[] = {
"33.6ms", "67.2ms", "134.4ms", "268.8ms", "537.6ms", "1.075s", "2.15s",
"4.3s", "8.6s", "17.2s", "34.41s"
};
static SOC_ENUM_SINGLE_DECL(alc_dcy,
WM8737_ALC3, 4, alc_dcy_text);
static const struct snd_kcontrol_new wm8737_snd_controls[] = {
SOC_DOUBLE_R_TLV("Mic Boost Volume", WM8737_AUDIO_PATH_L, WM8737_AUDIO_PATH_R,
6, 3, 0, micboost_tlv),
SOC_DOUBLE_R("Mic Boost Switch", WM8737_AUDIO_PATH_L, WM8737_AUDIO_PATH_R,
4, 1, 0),
SOC_DOUBLE("Mic ZC Switch", WM8737_AUDIO_PATH_L, WM8737_AUDIO_PATH_R,
3, 1, 0),
SOC_DOUBLE_R_TLV("Capture Volume", WM8737_LEFT_PGA_VOLUME,
WM8737_RIGHT_PGA_VOLUME, 0, 255, 0, pga_tlv),
SOC_DOUBLE("Capture ZC Switch", WM8737_AUDIO_PATH_L, WM8737_AUDIO_PATH_R,
2, 1, 0),
SOC_DOUBLE("INPUT1 DC Bias Switch", WM8737_MISC_BIAS_CONTROL, 0, 1, 1, 0),
SOC_ENUM("Mic PGA Bias", micbias_enum),
SOC_SINGLE("ADC Low Power Switch", WM8737_ADC_CONTROL, 2, 1, 0),
SOC_SINGLE("High Pass Filter Switch", WM8737_ADC_CONTROL, 0, 1, 1),
SOC_DOUBLE("Polarity Invert Switch", WM8737_ADC_CONTROL, 5, 6, 1, 0),
SOC_SINGLE("3D Switch", WM8737_3D_ENHANCE, 0, 1, 0),
SOC_SINGLE("3D Depth", WM8737_3D_ENHANCE, 1, 15, 0),
SOC_ENUM("3D Low Cut-off", low_3d),
SOC_ENUM("3D High Cut-off", high_3d),
SOC_SINGLE_TLV("3D ADC Volume", WM8737_3D_ENHANCE, 7, 1, 1, adc_tlv),
SOC_SINGLE("Noise Gate Switch", WM8737_NOISE_GATE, 0, 1, 0),
SOC_SINGLE_TLV("Noise Gate Threshold Volume", WM8737_NOISE_GATE, 2, 7, 0,
ng_tlv),
SOC_ENUM("ALC", alc_fn),
SOC_SINGLE_TLV("ALC Max Gain Volume", WM8737_ALC1, 4, 7, 0, alc_max_tlv),
SOC_SINGLE_TLV("ALC Target Volume", WM8737_ALC1, 0, 15, 0, alc_target_tlv),
SOC_ENUM("ALC Hold Time", alc_hold),
SOC_SINGLE("ALC ZC Switch", WM8737_ALC2, 4, 1, 0),
SOC_ENUM("ALC Attack Time", alc_atk),
SOC_ENUM("ALC Decay Time", alc_dcy),
};
static const char *linsel_text[] = {
"LINPUT1", "LINPUT2", "LINPUT3", "LINPUT1 DC",
};
static SOC_ENUM_SINGLE_DECL(linsel_enum,
WM8737_AUDIO_PATH_L, 7, linsel_text);
static const struct snd_kcontrol_new linsel_mux =
SOC_DAPM_ENUM("LINSEL", linsel_enum);
static const char *rinsel_text[] = {
"RINPUT1", "RINPUT2", "RINPUT3", "RINPUT1 DC",
};
static SOC_ENUM_SINGLE_DECL(rinsel_enum,
WM8737_AUDIO_PATH_R, 7, rinsel_text);
static const struct snd_kcontrol_new rinsel_mux =
SOC_DAPM_ENUM("RINSEL", rinsel_enum);
static const char *bypass_text[] = {
"Direct", "Preamp"
};
static SOC_ENUM_SINGLE_DECL(lbypass_enum,
WM8737_MIC_PREAMP_CONTROL, 2, bypass_text);
static const struct snd_kcontrol_new lbypass_mux =
SOC_DAPM_ENUM("Left Bypass", lbypass_enum);
static SOC_ENUM_SINGLE_DECL(rbypass_enum,
WM8737_MIC_PREAMP_CONTROL, 3, bypass_text);
static const struct snd_kcontrol_new rbypass_mux =
SOC_DAPM_ENUM("Left Bypass", rbypass_enum);
static const struct snd_soc_dapm_widget wm8737_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("LINPUT1"),
SND_SOC_DAPM_INPUT("LINPUT2"),
SND_SOC_DAPM_INPUT("LINPUT3"),
SND_SOC_DAPM_INPUT("RINPUT1"),
SND_SOC_DAPM_INPUT("RINPUT2"),
SND_SOC_DAPM_INPUT("RINPUT3"),
SND_SOC_DAPM_INPUT("LACIN"),
SND_SOC_DAPM_INPUT("RACIN"),
SND_SOC_DAPM_MUX("LINSEL", SND_SOC_NOPM, 0, 0, &linsel_mux),
SND_SOC_DAPM_MUX("RINSEL", SND_SOC_NOPM, 0, 0, &rinsel_mux),
SND_SOC_DAPM_MUX("Left Preamp Mux", SND_SOC_NOPM, 0, 0, &lbypass_mux),
SND_SOC_DAPM_MUX("Right Preamp Mux", SND_SOC_NOPM, 0, 0, &rbypass_mux),
SND_SOC_DAPM_PGA("PGAL", WM8737_POWER_MANAGEMENT, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA("PGAR", WM8737_POWER_MANAGEMENT, 4, 0, NULL, 0),
SND_SOC_DAPM_DAC("ADCL", NULL, WM8737_POWER_MANAGEMENT, 3, 0),
SND_SOC_DAPM_DAC("ADCR", NULL, WM8737_POWER_MANAGEMENT, 2, 0),
SND_SOC_DAPM_AIF_OUT("AIF", "Capture", 0, WM8737_POWER_MANAGEMENT, 6, 0),
};
static const struct snd_soc_dapm_route intercon[] = {
{ "LINSEL", "LINPUT1", "LINPUT1" },
{ "LINSEL", "LINPUT2", "LINPUT2" },
{ "LINSEL", "LINPUT3", "LINPUT3" },
{ "LINSEL", "LINPUT1 DC", "LINPUT1" },
{ "RINSEL", "RINPUT1", "RINPUT1" },
{ "RINSEL", "RINPUT2", "RINPUT2" },
{ "RINSEL", "RINPUT3", "RINPUT3" },
{ "RINSEL", "RINPUT1 DC", "RINPUT1" },
{ "Left Preamp Mux", "Preamp", "LINSEL" },
{ "Left Preamp Mux", "Direct", "LACIN" },
{ "Right Preamp Mux", "Preamp", "RINSEL" },
{ "Right Preamp Mux", "Direct", "RACIN" },
{ "PGAL", NULL, "Left Preamp Mux" },
{ "PGAR", NULL, "Right Preamp Mux" },
{ "ADCL", NULL, "PGAL" },
{ "ADCR", NULL, "PGAR" },
{ "AIF", NULL, "ADCL" },
{ "AIF", NULL, "ADCR" },
};
/* codec mclk clock divider coefficients */
static const struct {
u32 mclk;
u32 rate;
u8 usb;
u8 sr;
} coeff_div[] = {
{ 12288000, 8000, 0, 0x4 },
{ 12288000, 12000, 0, 0x8 },
{ 12288000, 16000, 0, 0xa },
{ 12288000, 24000, 0, 0x1c },
{ 12288000, 32000, 0, 0xc },
{ 12288000, 48000, 0, 0 },
{ 12288000, 96000, 0, 0xe },
{ 11289600, 8000, 0, 0x14 },
{ 11289600, 11025, 0, 0x18 },
{ 11289600, 22050, 0, 0x1a },
{ 11289600, 44100, 0, 0x10 },
{ 11289600, 88200, 0, 0x1e },
{ 18432000, 8000, 0, 0x5 },
{ 18432000, 12000, 0, 0x9 },
{ 18432000, 16000, 0, 0xb },
{ 18432000, 24000, 0, 0x1b },
{ 18432000, 32000, 0, 0xd },
{ 18432000, 48000, 0, 0x1 },
{ 18432000, 96000, 0, 0x1f },
{ 16934400, 8000, 0, 0x15 },
{ 16934400, 11025, 0, 0x19 },
{ 16934400, 22050, 0, 0x1b },
{ 16934400, 44100, 0, 0x11 },
{ 16934400, 88200, 0, 0x1f },
{ 12000000, 8000, 1, 0x4 },
{ 12000000, 11025, 1, 0x19 },
{ 12000000, 12000, 1, 0x8 },
{ 12000000, 16000, 1, 0xa },
{ 12000000, 22050, 1, 0x1b },
{ 12000000, 24000, 1, 0x1c },
{ 12000000, 32000, 1, 0xc },
{ 12000000, 44100, 1, 0x11 },
{ 12000000, 48000, 1, 0x0 },
{ 12000000, 88200, 1, 0x1f },
{ 12000000, 96000, 1, 0xe },
};
static int wm8737_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm8737_priv *wm8737 = snd_soc_component_get_drvdata(component);
int i;
u16 clocking = 0;
u16 af = 0;
for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
if (coeff_div[i].rate != params_rate(params))
continue;
if (coeff_div[i].mclk == wm8737->mclk)
break;
if (coeff_div[i].mclk == wm8737->mclk * 2) {
clocking |= WM8737_CLKDIV2;
break;
}
}
if (i == ARRAY_SIZE(coeff_div)) {
dev_err(component->dev, "%dHz MCLK can't support %dHz\n",
wm8737->mclk, params_rate(params));
return -EINVAL;
}
clocking |= coeff_div[i].usb | (coeff_div[i].sr << WM8737_SR_SHIFT);
switch (params_width(params)) {
case 16:
break;
case 20:
af |= 0x8;
break;
case 24:
af |= 0x10;
break;
case 32:
af |= 0x18;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, WM8737_AUDIO_FORMAT, WM8737_WL_MASK, af);
snd_soc_component_update_bits(component, WM8737_CLOCKING,
WM8737_USB_MODE | WM8737_CLKDIV2 | WM8737_SR_MASK,
clocking);
return 0;
}
static int wm8737_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct wm8737_priv *wm8737 = snd_soc_component_get_drvdata(component);
int i;
for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
if (freq == coeff_div[i].mclk ||
freq == coeff_div[i].mclk * 2) {
wm8737->mclk = freq;
return 0;
}
}
dev_err(component->dev, "MCLK rate %dHz not supported\n", freq);
return -EINVAL;
}
static int wm8737_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
u16 af = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
af |= WM8737_MS;
break;
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
af |= 0x2;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
af |= 0x1;
break;
case SND_SOC_DAIFMT_DSP_A:
af |= 0x3;
break;
case SND_SOC_DAIFMT_DSP_B:
af |= 0x13;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_NB_IF:
af |= WM8737_LRP;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, WM8737_AUDIO_FORMAT,
WM8737_FORMAT_MASK | WM8737_LRP | WM8737_MS, af);
return 0;
}
static int wm8737_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct wm8737_priv *wm8737 = snd_soc_component_get_drvdata(component);
int ret;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
/* VMID at 2*75k */
snd_soc_component_update_bits(component, WM8737_MISC_BIAS_CONTROL,
WM8737_VMIDSEL_MASK, 0);
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
ret = regulator_bulk_enable(ARRAY_SIZE(wm8737->supplies),
wm8737->supplies);
if (ret != 0) {
dev_err(component->dev,
"Failed to enable supplies: %d\n",
ret);
return ret;
}
regcache_sync(wm8737->regmap);
/* Fast VMID ramp at 2*2.5k */
snd_soc_component_update_bits(component, WM8737_MISC_BIAS_CONTROL,
WM8737_VMIDSEL_MASK,
2 << WM8737_VMIDSEL_SHIFT);
/* Bring VMID up */
snd_soc_component_update_bits(component, WM8737_POWER_MANAGEMENT,
WM8737_VMID_MASK |
WM8737_VREF_MASK,
WM8737_VMID_MASK |
WM8737_VREF_MASK);
msleep(500);
}
/* VMID at 2*300k */
snd_soc_component_update_bits(component, WM8737_MISC_BIAS_CONTROL,
WM8737_VMIDSEL_MASK,
1 << WM8737_VMIDSEL_SHIFT);
break;
case SND_SOC_BIAS_OFF:
snd_soc_component_update_bits(component, WM8737_POWER_MANAGEMENT,
WM8737_VMID_MASK | WM8737_VREF_MASK, 0);
regulator_bulk_disable(ARRAY_SIZE(wm8737->supplies),
wm8737->supplies);
break;
}
return 0;
}
#define WM8737_RATES SNDRV_PCM_RATE_8000_96000
#define WM8737_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops wm8737_dai_ops = {
.hw_params = wm8737_hw_params,
.set_sysclk = wm8737_set_dai_sysclk,
.set_fmt = wm8737_set_dai_fmt,
};
static struct snd_soc_dai_driver wm8737_dai = {
.name = "wm8737",
.capture = {
.stream_name = "Capture",
.channels_min = 2, /* Mono modes not yet supported */
.channels_max = 2,
.rates = WM8737_RATES,
.formats = WM8737_FORMATS,
},
.ops = &wm8737_dai_ops,
};
static int wm8737_probe(struct snd_soc_component *component)
{
struct wm8737_priv *wm8737 = snd_soc_component_get_drvdata(component);
int ret;
ret = regulator_bulk_enable(ARRAY_SIZE(wm8737->supplies),
wm8737->supplies);
if (ret != 0) {
dev_err(component->dev, "Failed to enable supplies: %d\n", ret);
goto err_get;
}
ret = wm8737_reset(component);
if (ret < 0) {
dev_err(component->dev, "Failed to issue reset\n");
goto err_enable;
}
snd_soc_component_update_bits(component, WM8737_LEFT_PGA_VOLUME, WM8737_LVU,
WM8737_LVU);
snd_soc_component_update_bits(component, WM8737_RIGHT_PGA_VOLUME, WM8737_RVU,
WM8737_RVU);
snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
/* Bias level configuration will have done an extra enable */
regulator_bulk_disable(ARRAY_SIZE(wm8737->supplies), wm8737->supplies);
return 0;
err_enable:
regulator_bulk_disable(ARRAY_SIZE(wm8737->supplies), wm8737->supplies);
err_get:
return ret;
}
static const struct snd_soc_component_driver soc_component_dev_wm8737 = {
.probe = wm8737_probe,
.set_bias_level = wm8737_set_bias_level,
.controls = wm8737_snd_controls,
.num_controls = ARRAY_SIZE(wm8737_snd_controls),
.dapm_widgets = wm8737_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8737_dapm_widgets),
.dapm_routes = intercon,
.num_dapm_routes = ARRAY_SIZE(intercon),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct of_device_id wm8737_of_match[] = {
{ .compatible = "wlf,wm8737", },
{ }
};
MODULE_DEVICE_TABLE(of, wm8737_of_match);
static const struct regmap_config wm8737_regmap = {
.reg_bits = 7,
.val_bits = 9,
.max_register = WM8737_MAX_REGISTER,
.reg_defaults = wm8737_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8737_reg_defaults),
.cache_type = REGCACHE_MAPLE,
.volatile_reg = wm8737_volatile,
};
#if IS_ENABLED(CONFIG_I2C)
static int wm8737_i2c_probe(struct i2c_client *i2c)
{
struct wm8737_priv *wm8737;
int ret, i;
wm8737 = devm_kzalloc(&i2c->dev, sizeof(struct wm8737_priv),
GFP_KERNEL);
if (wm8737 == NULL)
return -ENOMEM;
for (i = 0; i < ARRAY_SIZE(wm8737->supplies); i++)
wm8737->supplies[i].supply = wm8737_supply_names[i];
ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8737->supplies),
wm8737->supplies);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
return ret;
}
wm8737->regmap = devm_regmap_init_i2c(i2c, &wm8737_regmap);
if (IS_ERR(wm8737->regmap))
return PTR_ERR(wm8737->regmap);
i2c_set_clientdata(i2c, wm8737);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_wm8737, &wm8737_dai, 1);
return ret;
}
static const struct i2c_device_id wm8737_i2c_id[] = {
{ "wm8737", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8737_i2c_id);
static struct i2c_driver wm8737_i2c_driver = {
.driver = {
.name = "wm8737",
.of_match_table = wm8737_of_match,
},
.probe = wm8737_i2c_probe,
.id_table = wm8737_i2c_id,
};
#endif
#if defined(CONFIG_SPI_MASTER)
static int wm8737_spi_probe(struct spi_device *spi)
{
struct wm8737_priv *wm8737;
int ret, i;
wm8737 = devm_kzalloc(&spi->dev, sizeof(struct wm8737_priv),
GFP_KERNEL);
if (wm8737 == NULL)
return -ENOMEM;
for (i = 0; i < ARRAY_SIZE(wm8737->supplies); i++)
wm8737->supplies[i].supply = wm8737_supply_names[i];
ret = devm_regulator_bulk_get(&spi->dev, ARRAY_SIZE(wm8737->supplies),
wm8737->supplies);
if (ret != 0) {
dev_err(&spi->dev, "Failed to request supplies: %d\n", ret);
return ret;
}
wm8737->regmap = devm_regmap_init_spi(spi, &wm8737_regmap);
if (IS_ERR(wm8737->regmap))
return PTR_ERR(wm8737->regmap);
spi_set_drvdata(spi, wm8737);
ret = devm_snd_soc_register_component(&spi->dev,
&soc_component_dev_wm8737, &wm8737_dai, 1);
return ret;
}
static struct spi_driver wm8737_spi_driver = {
.driver = {
.name = "wm8737",
.of_match_table = wm8737_of_match,
},
.probe = wm8737_spi_probe,
};
#endif /* CONFIG_SPI_MASTER */
static int __init wm8737_modinit(void)
{
int ret;
#if IS_ENABLED(CONFIG_I2C)
ret = i2c_add_driver(&wm8737_i2c_driver);
if (ret != 0) {
printk(KERN_ERR "Failed to register WM8737 I2C driver: %d\n",
ret);
}
#endif
#if defined(CONFIG_SPI_MASTER)
ret = spi_register_driver(&wm8737_spi_driver);
if (ret != 0) {
printk(KERN_ERR "Failed to register WM8737 SPI driver: %d\n",
ret);
}
#endif
return 0;
}
module_init(wm8737_modinit);
static void __exit wm8737_exit(void)
{
#if defined(CONFIG_SPI_MASTER)
spi_unregister_driver(&wm8737_spi_driver);
#endif
#if IS_ENABLED(CONFIG_I2C)
i2c_del_driver(&wm8737_i2c_driver);
#endif
}
module_exit(wm8737_exit);
MODULE_DESCRIPTION("ASoC WM8737 driver");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8737.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Shared helper functions for devices from the ADAU family
*
* Copyright 2011-2016 Analog Devices Inc.
* Author: Lars-Peter Clausen <[email protected]>
*/
#include <linux/gcd.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include "adau-utils.h"
int adau_calc_pll_cfg(unsigned int freq_in, unsigned int freq_out,
uint8_t regs[5])
{
unsigned int r, n, m, i, j;
unsigned int div;
if (!freq_out) {
r = 0;
n = 0;
m = 0;
div = 0;
} else {
if (freq_out % freq_in != 0) {
div = DIV_ROUND_UP(freq_in, 13500000);
freq_in /= div;
r = freq_out / freq_in;
i = freq_out % freq_in;
j = gcd(i, freq_in);
n = i / j;
m = freq_in / j;
div--;
} else {
r = freq_out / freq_in;
n = 0;
m = 0;
div = 0;
}
if (n > 0xffff || m > 0xffff || div > 3 || r > 8 || r < 2)
return -EINVAL;
}
regs[0] = m >> 8;
regs[1] = m & 0xff;
regs[2] = n >> 8;
regs[3] = n & 0xff;
regs[4] = (r << 3) | (div << 1);
if (m != 0)
regs[4] |= 1; /* Fractional mode */
return 0;
}
EXPORT_SYMBOL_GPL(adau_calc_pll_cfg);
MODULE_DESCRIPTION("ASoC ADAU audio CODECs shared helper functions");
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/adau-utils.c |
// SPDX-License-Identifier: GPL-2.0
//
// Analog Devices SSM2305 Amplifier Driver
//
// Copyright (C) 2018 Pengutronix, Marco Felsch <[email protected]>
//
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <sound/soc.h>
#define DRV_NAME "ssm2305"
struct ssm2305 {
/* shutdown gpio */
struct gpio_desc *gpiod_shutdown;
};
static int ssm2305_power_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kctrl, int event)
{
struct snd_soc_component *c = snd_soc_dapm_to_component(w->dapm);
struct ssm2305 *data = snd_soc_component_get_drvdata(c);
gpiod_set_value_cansleep(data->gpiod_shutdown,
SND_SOC_DAPM_EVENT_ON(event));
return 0;
}
static const struct snd_soc_dapm_widget ssm2305_dapm_widgets[] = {
/* Stereo input/output */
SND_SOC_DAPM_INPUT("L_IN"),
SND_SOC_DAPM_INPUT("R_IN"),
SND_SOC_DAPM_OUTPUT("L_OUT"),
SND_SOC_DAPM_OUTPUT("R_OUT"),
SND_SOC_DAPM_SUPPLY("Power", SND_SOC_NOPM, 0, 0, ssm2305_power_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
};
static const struct snd_soc_dapm_route ssm2305_dapm_routes[] = {
{ "L_OUT", NULL, "L_IN" },
{ "R_OUT", NULL, "R_IN" },
{ "L_IN", NULL, "Power" },
{ "R_IN", NULL, "Power" },
};
static const struct snd_soc_component_driver ssm2305_component_driver = {
.dapm_widgets = ssm2305_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(ssm2305_dapm_widgets),
.dapm_routes = ssm2305_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(ssm2305_dapm_routes),
};
static int ssm2305_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct ssm2305 *priv;
/* Allocate the private data */
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
platform_set_drvdata(pdev, priv);
/* Get shutdown gpio */
priv->gpiod_shutdown = devm_gpiod_get(dev, "shutdown",
GPIOD_OUT_LOW);
if (IS_ERR(priv->gpiod_shutdown))
return dev_err_probe(dev, PTR_ERR(priv->gpiod_shutdown),
"Failed to get 'shutdown' gpio\n");
return devm_snd_soc_register_component(dev, &ssm2305_component_driver,
NULL, 0);
}
#ifdef CONFIG_OF
static const struct of_device_id ssm2305_of_match[] = {
{ .compatible = "adi,ssm2305", },
{ }
};
MODULE_DEVICE_TABLE(of, ssm2305_of_match);
#endif
static struct platform_driver ssm2305_driver = {
.driver = {
.name = DRV_NAME,
.of_match_table = of_match_ptr(ssm2305_of_match),
},
.probe = ssm2305_probe,
};
module_platform_driver(ssm2305_driver);
MODULE_DESCRIPTION("ASoC SSM2305 amplifier driver");
MODULE_AUTHOR("Marco Felsch <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/ssm2305.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ALSA SoC WM9090 driver
*
* Copyright 2009-12 Wolfson Microelectronics
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/device.h>
#include <linux/i2c.h>
#include <linux/delay.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <sound/wm9090.h>
#include "wm9090.h"
static const struct reg_default wm9090_reg_defaults[] = {
{ 1, 0x0006 }, /* R1 - Power Management (1) */
{ 2, 0x6000 }, /* R2 - Power Management (2) */
{ 3, 0x0000 }, /* R3 - Power Management (3) */
{ 6, 0x01C0 }, /* R6 - Clocking 1 */
{ 22, 0x0003 }, /* R22 - IN1 Line Control */
{ 23, 0x0003 }, /* R23 - IN2 Line Control */
{ 24, 0x0083 }, /* R24 - IN1 Line Input A Volume */
{ 25, 0x0083 }, /* R25 - IN1 Line Input B Volume */
{ 26, 0x0083 }, /* R26 - IN2 Line Input A Volume */
{ 27, 0x0083 }, /* R27 - IN2 Line Input B Volume */
{ 28, 0x002D }, /* R28 - Left Output Volume */
{ 29, 0x002D }, /* R29 - Right Output Volume */
{ 34, 0x0100 }, /* R34 - SPKMIXL Attenuation */
{ 35, 0x0010 }, /* R36 - SPKOUT Mixers */
{ 37, 0x0140 }, /* R37 - ClassD3 */
{ 38, 0x0039 }, /* R38 - Speaker Volume Left */
{ 45, 0x0000 }, /* R45 - Output Mixer1 */
{ 46, 0x0000 }, /* R46 - Output Mixer2 */
{ 47, 0x0100 }, /* R47 - Output Mixer3 */
{ 48, 0x0100 }, /* R48 - Output Mixer4 */
{ 54, 0x0000 }, /* R54 - Speaker Mixer */
{ 57, 0x000D }, /* R57 - AntiPOP2 */
{ 70, 0x0000 }, /* R70 - Write Sequencer 0 */
{ 71, 0x0000 }, /* R71 - Write Sequencer 1 */
{ 72, 0x0000 }, /* R72 - Write Sequencer 2 */
{ 73, 0x0000 }, /* R73 - Write Sequencer 3 */
{ 74, 0x0000 }, /* R74 - Write Sequencer 4 */
{ 75, 0x0000 }, /* R75 - Write Sequencer 5 */
{ 76, 0x1F25 }, /* R76 - Charge Pump 1 */
{ 85, 0x054A }, /* R85 - DC Servo 1 */
{ 87, 0x0000 }, /* R87 - DC Servo 3 */
{ 96, 0x0100 }, /* R96 - Analogue HP 0 */
{ 98, 0x8640 }, /* R98 - AGC Control 0 */
{ 99, 0xC000 }, /* R99 - AGC Control 1 */
{ 100, 0x0200 }, /* R100 - AGC Control 2 */
};
/* This struct is used to save the context */
struct wm9090_priv {
struct wm9090_platform_data pdata;
struct regmap *regmap;
};
static bool wm9090_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM9090_SOFTWARE_RESET:
case WM9090_DC_SERVO_0:
case WM9090_DC_SERVO_READBACK_0:
case WM9090_DC_SERVO_READBACK_1:
case WM9090_DC_SERVO_READBACK_2:
return true;
default:
return false;
}
}
static bool wm9090_readable(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM9090_SOFTWARE_RESET:
case WM9090_POWER_MANAGEMENT_1:
case WM9090_POWER_MANAGEMENT_2:
case WM9090_POWER_MANAGEMENT_3:
case WM9090_CLOCKING_1:
case WM9090_IN1_LINE_CONTROL:
case WM9090_IN2_LINE_CONTROL:
case WM9090_IN1_LINE_INPUT_A_VOLUME:
case WM9090_IN1_LINE_INPUT_B_VOLUME:
case WM9090_IN2_LINE_INPUT_A_VOLUME:
case WM9090_IN2_LINE_INPUT_B_VOLUME:
case WM9090_LEFT_OUTPUT_VOLUME:
case WM9090_RIGHT_OUTPUT_VOLUME:
case WM9090_SPKMIXL_ATTENUATION:
case WM9090_SPKOUT_MIXERS:
case WM9090_CLASSD3:
case WM9090_SPEAKER_VOLUME_LEFT:
case WM9090_OUTPUT_MIXER1:
case WM9090_OUTPUT_MIXER2:
case WM9090_OUTPUT_MIXER3:
case WM9090_OUTPUT_MIXER4:
case WM9090_SPEAKER_MIXER:
case WM9090_ANTIPOP2:
case WM9090_WRITE_SEQUENCER_0:
case WM9090_WRITE_SEQUENCER_1:
case WM9090_WRITE_SEQUENCER_2:
case WM9090_WRITE_SEQUENCER_3:
case WM9090_WRITE_SEQUENCER_4:
case WM9090_WRITE_SEQUENCER_5:
case WM9090_CHARGE_PUMP_1:
case WM9090_DC_SERVO_0:
case WM9090_DC_SERVO_1:
case WM9090_DC_SERVO_3:
case WM9090_DC_SERVO_READBACK_0:
case WM9090_DC_SERVO_READBACK_1:
case WM9090_DC_SERVO_READBACK_2:
case WM9090_ANALOGUE_HP_0:
case WM9090_AGC_CONTROL_0:
case WM9090_AGC_CONTROL_1:
case WM9090_AGC_CONTROL_2:
return true;
default:
return false;
}
}
static void wait_for_dc_servo(struct snd_soc_component *component)
{
unsigned int reg;
int count = 0;
dev_dbg(component->dev, "Waiting for DC servo...\n");
do {
count++;
msleep(1);
reg = snd_soc_component_read(component, WM9090_DC_SERVO_READBACK_0);
dev_dbg(component->dev, "DC servo status: %x\n", reg);
} while ((reg & WM9090_DCS_CAL_COMPLETE_MASK)
!= WM9090_DCS_CAL_COMPLETE_MASK && count < 1000);
if ((reg & WM9090_DCS_CAL_COMPLETE_MASK)
!= WM9090_DCS_CAL_COMPLETE_MASK)
dev_err(component->dev, "Timed out waiting for DC Servo\n");
}
static const DECLARE_TLV_DB_RANGE(in_tlv,
0, 0, TLV_DB_SCALE_ITEM(-600, 0, 0),
1, 3, TLV_DB_SCALE_ITEM(-350, 350, 0),
4, 6, TLV_DB_SCALE_ITEM(600, 600, 0)
);
static const DECLARE_TLV_DB_RANGE(mix_tlv,
0, 2, TLV_DB_SCALE_ITEM(-1200, 300, 0),
3, 3, TLV_DB_SCALE_ITEM(0, 0, 0)
);
static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
static const DECLARE_TLV_DB_RANGE(spkboost_tlv,
0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0)
);
static const struct snd_kcontrol_new wm9090_controls[] = {
SOC_SINGLE_TLV("IN1A Volume", WM9090_IN1_LINE_INPUT_A_VOLUME, 0, 6, 0,
in_tlv),
SOC_SINGLE("IN1A Switch", WM9090_IN1_LINE_INPUT_A_VOLUME, 7, 1, 1),
SOC_SINGLE("IN1A ZC Switch", WM9090_IN1_LINE_INPUT_A_VOLUME, 6, 1, 0),
SOC_SINGLE_TLV("IN2A Volume", WM9090_IN2_LINE_INPUT_A_VOLUME, 0, 6, 0,
in_tlv),
SOC_SINGLE("IN2A Switch", WM9090_IN2_LINE_INPUT_A_VOLUME, 7, 1, 1),
SOC_SINGLE("IN2A ZC Switch", WM9090_IN2_LINE_INPUT_A_VOLUME, 6, 1, 0),
SOC_SINGLE("MIXOUTL Switch", WM9090_OUTPUT_MIXER3, 8, 1, 1),
SOC_SINGLE_TLV("MIXOUTL IN1A Volume", WM9090_OUTPUT_MIXER3, 6, 3, 1,
mix_tlv),
SOC_SINGLE_TLV("MIXOUTL IN2A Volume", WM9090_OUTPUT_MIXER3, 2, 3, 1,
mix_tlv),
SOC_SINGLE("MIXOUTR Switch", WM9090_OUTPUT_MIXER4, 8, 1, 1),
SOC_SINGLE_TLV("MIXOUTR IN1A Volume", WM9090_OUTPUT_MIXER4, 6, 3, 1,
mix_tlv),
SOC_SINGLE_TLV("MIXOUTR IN2A Volume", WM9090_OUTPUT_MIXER4, 2, 3, 1,
mix_tlv),
SOC_SINGLE("SPKMIX Switch", WM9090_SPKMIXL_ATTENUATION, 8, 1, 1),
SOC_SINGLE_TLV("SPKMIX IN1A Volume", WM9090_SPKMIXL_ATTENUATION, 6, 3, 1,
mix_tlv),
SOC_SINGLE_TLV("SPKMIX IN2A Volume", WM9090_SPKMIXL_ATTENUATION, 2, 3, 1,
mix_tlv),
SOC_DOUBLE_R_TLV("Headphone Volume", WM9090_LEFT_OUTPUT_VOLUME,
WM9090_RIGHT_OUTPUT_VOLUME, 0, 63, 0, out_tlv),
SOC_DOUBLE_R("Headphone Switch", WM9090_LEFT_OUTPUT_VOLUME,
WM9090_RIGHT_OUTPUT_VOLUME, 6, 1, 1),
SOC_DOUBLE_R("Headphone ZC Switch", WM9090_LEFT_OUTPUT_VOLUME,
WM9090_RIGHT_OUTPUT_VOLUME, 7, 1, 0),
SOC_SINGLE_TLV("Speaker Volume", WM9090_SPEAKER_VOLUME_LEFT, 0, 63, 0,
out_tlv),
SOC_SINGLE("Speaker Switch", WM9090_SPEAKER_VOLUME_LEFT, 6, 1, 1),
SOC_SINGLE("Speaker ZC Switch", WM9090_SPEAKER_VOLUME_LEFT, 7, 1, 0),
SOC_SINGLE_TLV("Speaker Boost Volume", WM9090_CLASSD3, 3, 7, 0, spkboost_tlv),
};
static const struct snd_kcontrol_new wm9090_in1_se_controls[] = {
SOC_SINGLE_TLV("IN1B Volume", WM9090_IN1_LINE_INPUT_B_VOLUME, 0, 6, 0,
in_tlv),
SOC_SINGLE("IN1B Switch", WM9090_IN1_LINE_INPUT_B_VOLUME, 7, 1, 1),
SOC_SINGLE("IN1B ZC Switch", WM9090_IN1_LINE_INPUT_B_VOLUME, 6, 1, 0),
SOC_SINGLE_TLV("SPKMIX IN1B Volume", WM9090_SPKMIXL_ATTENUATION, 4, 3, 1,
mix_tlv),
SOC_SINGLE_TLV("MIXOUTL IN1B Volume", WM9090_OUTPUT_MIXER3, 4, 3, 1,
mix_tlv),
SOC_SINGLE_TLV("MIXOUTR IN1B Volume", WM9090_OUTPUT_MIXER4, 4, 3, 1,
mix_tlv),
};
static const struct snd_kcontrol_new wm9090_in2_se_controls[] = {
SOC_SINGLE_TLV("IN2B Volume", WM9090_IN2_LINE_INPUT_B_VOLUME, 0, 6, 0,
in_tlv),
SOC_SINGLE("IN2B Switch", WM9090_IN2_LINE_INPUT_B_VOLUME, 7, 1, 1),
SOC_SINGLE("IN2B ZC Switch", WM9090_IN2_LINE_INPUT_B_VOLUME, 6, 1, 0),
SOC_SINGLE_TLV("SPKMIX IN2B Volume", WM9090_SPKMIXL_ATTENUATION, 0, 3, 1,
mix_tlv),
SOC_SINGLE_TLV("MIXOUTL IN2B Volume", WM9090_OUTPUT_MIXER3, 0, 3, 1,
mix_tlv),
SOC_SINGLE_TLV("MIXOUTR IN2B Volume", WM9090_OUTPUT_MIXER4, 0, 3, 1,
mix_tlv),
};
static int hp_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
unsigned int reg = snd_soc_component_read(component, WM9090_ANALOGUE_HP_0);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(component, WM9090_CHARGE_PUMP_1,
WM9090_CP_ENA, WM9090_CP_ENA);
msleep(5);
snd_soc_component_update_bits(component, WM9090_POWER_MANAGEMENT_1,
WM9090_HPOUT1L_ENA | WM9090_HPOUT1R_ENA,
WM9090_HPOUT1L_ENA | WM9090_HPOUT1R_ENA);
reg |= WM9090_HPOUT1L_DLY | WM9090_HPOUT1R_DLY;
snd_soc_component_write(component, WM9090_ANALOGUE_HP_0, reg);
/* Start the DC servo. We don't currently use the
* ability to save the state since we don't have full
* control of the analogue paths and they can change
* DC offsets; see the WM8904 driver for an example of
* doing so.
*/
snd_soc_component_write(component, WM9090_DC_SERVO_0,
WM9090_DCS_ENA_CHAN_0 |
WM9090_DCS_ENA_CHAN_1 |
WM9090_DCS_TRIG_STARTUP_1 |
WM9090_DCS_TRIG_STARTUP_0);
wait_for_dc_servo(component);
reg |= WM9090_HPOUT1R_OUTP | WM9090_HPOUT1R_RMV_SHORT |
WM9090_HPOUT1L_OUTP | WM9090_HPOUT1L_RMV_SHORT;
snd_soc_component_write(component, WM9090_ANALOGUE_HP_0, reg);
break;
case SND_SOC_DAPM_PRE_PMD:
reg &= ~(WM9090_HPOUT1L_RMV_SHORT |
WM9090_HPOUT1L_DLY |
WM9090_HPOUT1L_OUTP |
WM9090_HPOUT1R_RMV_SHORT |
WM9090_HPOUT1R_DLY |
WM9090_HPOUT1R_OUTP);
snd_soc_component_write(component, WM9090_ANALOGUE_HP_0, reg);
snd_soc_component_write(component, WM9090_DC_SERVO_0, 0);
snd_soc_component_update_bits(component, WM9090_POWER_MANAGEMENT_1,
WM9090_HPOUT1L_ENA | WM9090_HPOUT1R_ENA,
0);
snd_soc_component_update_bits(component, WM9090_CHARGE_PUMP_1,
WM9090_CP_ENA, 0);
break;
}
return 0;
}
static const struct snd_kcontrol_new spkmix[] = {
SOC_DAPM_SINGLE("IN1A Switch", WM9090_SPEAKER_MIXER, 6, 1, 0),
SOC_DAPM_SINGLE("IN1B Switch", WM9090_SPEAKER_MIXER, 4, 1, 0),
SOC_DAPM_SINGLE("IN2A Switch", WM9090_SPEAKER_MIXER, 2, 1, 0),
SOC_DAPM_SINGLE("IN2B Switch", WM9090_SPEAKER_MIXER, 0, 1, 0),
};
static const struct snd_kcontrol_new spkout[] = {
SOC_DAPM_SINGLE("Mixer Switch", WM9090_SPKOUT_MIXERS, 4, 1, 0),
};
static const struct snd_kcontrol_new mixoutl[] = {
SOC_DAPM_SINGLE("IN1A Switch", WM9090_OUTPUT_MIXER1, 6, 1, 0),
SOC_DAPM_SINGLE("IN1B Switch", WM9090_OUTPUT_MIXER1, 4, 1, 0),
SOC_DAPM_SINGLE("IN2A Switch", WM9090_OUTPUT_MIXER1, 2, 1, 0),
SOC_DAPM_SINGLE("IN2B Switch", WM9090_OUTPUT_MIXER1, 0, 1, 0),
};
static const struct snd_kcontrol_new mixoutr[] = {
SOC_DAPM_SINGLE("IN1A Switch", WM9090_OUTPUT_MIXER2, 6, 1, 0),
SOC_DAPM_SINGLE("IN1B Switch", WM9090_OUTPUT_MIXER2, 4, 1, 0),
SOC_DAPM_SINGLE("IN2A Switch", WM9090_OUTPUT_MIXER2, 2, 1, 0),
SOC_DAPM_SINGLE("IN2B Switch", WM9090_OUTPUT_MIXER2, 0, 1, 0),
};
static const struct snd_soc_dapm_widget wm9090_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("IN1+"),
SND_SOC_DAPM_INPUT("IN1-"),
SND_SOC_DAPM_INPUT("IN2+"),
SND_SOC_DAPM_INPUT("IN2-"),
SND_SOC_DAPM_SUPPLY("OSC", WM9090_POWER_MANAGEMENT_1, 3, 0, NULL, 0),
SND_SOC_DAPM_PGA("IN1A PGA", WM9090_POWER_MANAGEMENT_2, 7, 0, NULL, 0),
SND_SOC_DAPM_PGA("IN1B PGA", WM9090_POWER_MANAGEMENT_2, 6, 0, NULL, 0),
SND_SOC_DAPM_PGA("IN2A PGA", WM9090_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA("IN2B PGA", WM9090_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SPKMIX", WM9090_POWER_MANAGEMENT_3, 3, 0,
spkmix, ARRAY_SIZE(spkmix)),
SND_SOC_DAPM_MIXER("MIXOUTL", WM9090_POWER_MANAGEMENT_3, 5, 0,
mixoutl, ARRAY_SIZE(mixoutl)),
SND_SOC_DAPM_MIXER("MIXOUTR", WM9090_POWER_MANAGEMENT_3, 4, 0,
mixoutr, ARRAY_SIZE(mixoutr)),
SND_SOC_DAPM_PGA_E("HP PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
hp_ev, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA("SPKPGA", WM9090_POWER_MANAGEMENT_3, 8, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SPKOUT", WM9090_POWER_MANAGEMENT_1, 12, 0,
spkout, ARRAY_SIZE(spkout)),
SND_SOC_DAPM_OUTPUT("HPR"),
SND_SOC_DAPM_OUTPUT("HPL"),
SND_SOC_DAPM_OUTPUT("Speaker"),
};
static const struct snd_soc_dapm_route audio_map[] = {
{ "IN1A PGA", NULL, "IN1+" },
{ "IN2A PGA", NULL, "IN2+" },
{ "SPKMIX", "IN1A Switch", "IN1A PGA" },
{ "SPKMIX", "IN2A Switch", "IN2A PGA" },
{ "MIXOUTL", "IN1A Switch", "IN1A PGA" },
{ "MIXOUTL", "IN2A Switch", "IN2A PGA" },
{ "MIXOUTR", "IN1A Switch", "IN1A PGA" },
{ "MIXOUTR", "IN2A Switch", "IN2A PGA" },
{ "HP PGA", NULL, "OSC" },
{ "HP PGA", NULL, "MIXOUTL" },
{ "HP PGA", NULL, "MIXOUTR" },
{ "HPL", NULL, "HP PGA" },
{ "HPR", NULL, "HP PGA" },
{ "SPKPGA", NULL, "OSC" },
{ "SPKPGA", NULL, "SPKMIX" },
{ "SPKOUT", "Mixer Switch", "SPKPGA" },
{ "Speaker", NULL, "SPKOUT" },
};
static const struct snd_soc_dapm_route audio_map_in1_se[] = {
{ "IN1B PGA", NULL, "IN1-" },
{ "SPKMIX", "IN1B Switch", "IN1B PGA" },
{ "MIXOUTL", "IN1B Switch", "IN1B PGA" },
{ "MIXOUTR", "IN1B Switch", "IN1B PGA" },
};
static const struct snd_soc_dapm_route audio_map_in1_diff[] = {
{ "IN1A PGA", NULL, "IN1-" },
};
static const struct snd_soc_dapm_route audio_map_in2_se[] = {
{ "IN2B PGA", NULL, "IN2-" },
{ "SPKMIX", "IN2B Switch", "IN2B PGA" },
{ "MIXOUTL", "IN2B Switch", "IN2B PGA" },
{ "MIXOUTR", "IN2B Switch", "IN2B PGA" },
};
static const struct snd_soc_dapm_route audio_map_in2_diff[] = {
{ "IN2A PGA", NULL, "IN2-" },
};
static int wm9090_add_controls(struct snd_soc_component *component)
{
struct wm9090_priv *wm9090 = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
int i;
snd_soc_dapm_new_controls(dapm, wm9090_dapm_widgets,
ARRAY_SIZE(wm9090_dapm_widgets));
snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
snd_soc_add_component_controls(component, wm9090_controls,
ARRAY_SIZE(wm9090_controls));
if (wm9090->pdata.lin1_diff) {
snd_soc_dapm_add_routes(dapm, audio_map_in1_diff,
ARRAY_SIZE(audio_map_in1_diff));
} else {
snd_soc_dapm_add_routes(dapm, audio_map_in1_se,
ARRAY_SIZE(audio_map_in1_se));
snd_soc_add_component_controls(component, wm9090_in1_se_controls,
ARRAY_SIZE(wm9090_in1_se_controls));
}
if (wm9090->pdata.lin2_diff) {
snd_soc_dapm_add_routes(dapm, audio_map_in2_diff,
ARRAY_SIZE(audio_map_in2_diff));
} else {
snd_soc_dapm_add_routes(dapm, audio_map_in2_se,
ARRAY_SIZE(audio_map_in2_se));
snd_soc_add_component_controls(component, wm9090_in2_se_controls,
ARRAY_SIZE(wm9090_in2_se_controls));
}
if (wm9090->pdata.agc_ena) {
for (i = 0; i < ARRAY_SIZE(wm9090->pdata.agc); i++)
snd_soc_component_write(component, WM9090_AGC_CONTROL_0 + i,
wm9090->pdata.agc[i]);
snd_soc_component_update_bits(component, WM9090_POWER_MANAGEMENT_3,
WM9090_AGC_ENA, WM9090_AGC_ENA);
} else {
snd_soc_component_update_bits(component, WM9090_POWER_MANAGEMENT_3,
WM9090_AGC_ENA, 0);
}
return 0;
}
/*
* The machine driver should call this from their set_bias_level; if there
* isn't one then this can just be set as the set_bias_level function.
*/
static int wm9090_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct wm9090_priv *wm9090 = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
snd_soc_component_update_bits(component, WM9090_ANTIPOP2, WM9090_VMID_ENA,
WM9090_VMID_ENA);
snd_soc_component_update_bits(component, WM9090_POWER_MANAGEMENT_1,
WM9090_BIAS_ENA |
WM9090_VMID_RES_MASK,
WM9090_BIAS_ENA |
1 << WM9090_VMID_RES_SHIFT);
msleep(1); /* Probably an overestimate */
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
/* Restore the register cache */
regcache_sync(wm9090->regmap);
}
/* We keep VMID off during standby since the combination of
* ground referenced outputs and class D speaker mean that
* latency is not an issue.
*/
snd_soc_component_update_bits(component, WM9090_POWER_MANAGEMENT_1,
WM9090_BIAS_ENA | WM9090_VMID_RES_MASK, 0);
snd_soc_component_update_bits(component, WM9090_ANTIPOP2,
WM9090_VMID_ENA, 0);
break;
case SND_SOC_BIAS_OFF:
break;
}
return 0;
}
static int wm9090_probe(struct snd_soc_component *component)
{
/* Configure some defaults; they will be written out when we
* bring the bias up.
*/
snd_soc_component_update_bits(component, WM9090_IN1_LINE_INPUT_A_VOLUME,
WM9090_IN1_VU | WM9090_IN1A_ZC,
WM9090_IN1_VU | WM9090_IN1A_ZC);
snd_soc_component_update_bits(component, WM9090_IN1_LINE_INPUT_B_VOLUME,
WM9090_IN1_VU | WM9090_IN1B_ZC,
WM9090_IN1_VU | WM9090_IN1B_ZC);
snd_soc_component_update_bits(component, WM9090_IN2_LINE_INPUT_A_VOLUME,
WM9090_IN2_VU | WM9090_IN2A_ZC,
WM9090_IN2_VU | WM9090_IN2A_ZC);
snd_soc_component_update_bits(component, WM9090_IN2_LINE_INPUT_B_VOLUME,
WM9090_IN2_VU | WM9090_IN2B_ZC,
WM9090_IN2_VU | WM9090_IN2B_ZC);
snd_soc_component_update_bits(component, WM9090_SPEAKER_VOLUME_LEFT,
WM9090_SPKOUT_VU | WM9090_SPKOUTL_ZC,
WM9090_SPKOUT_VU | WM9090_SPKOUTL_ZC);
snd_soc_component_update_bits(component, WM9090_LEFT_OUTPUT_VOLUME,
WM9090_HPOUT1_VU | WM9090_HPOUT1L_ZC,
WM9090_HPOUT1_VU | WM9090_HPOUT1L_ZC);
snd_soc_component_update_bits(component, WM9090_RIGHT_OUTPUT_VOLUME,
WM9090_HPOUT1_VU | WM9090_HPOUT1R_ZC,
WM9090_HPOUT1_VU | WM9090_HPOUT1R_ZC);
snd_soc_component_update_bits(component, WM9090_CLOCKING_1,
WM9090_TOCLK_ENA, WM9090_TOCLK_ENA);
wm9090_add_controls(component);
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_wm9090 = {
.probe = wm9090_probe,
.set_bias_level = wm9090_set_bias_level,
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
};
static const struct regmap_config wm9090_regmap = {
.reg_bits = 8,
.val_bits = 16,
.max_register = WM9090_MAX_REGISTER,
.volatile_reg = wm9090_volatile,
.readable_reg = wm9090_readable,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = wm9090_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm9090_reg_defaults),
};
static int wm9090_i2c_probe(struct i2c_client *i2c)
{
struct wm9090_priv *wm9090;
unsigned int reg;
int ret;
wm9090 = devm_kzalloc(&i2c->dev, sizeof(*wm9090), GFP_KERNEL);
if (!wm9090)
return -ENOMEM;
wm9090->regmap = devm_regmap_init_i2c(i2c, &wm9090_regmap);
if (IS_ERR(wm9090->regmap)) {
ret = PTR_ERR(wm9090->regmap);
dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
return ret;
}
ret = regmap_read(wm9090->regmap, WM9090_SOFTWARE_RESET, ®);
if (ret < 0)
return ret;
if (reg != 0x9093) {
dev_err(&i2c->dev, "Device is not a WM9090, ID=%x\n", reg);
return -ENODEV;
}
ret = regmap_write(wm9090->regmap, WM9090_SOFTWARE_RESET, 0);
if (ret < 0)
return ret;
if (i2c->dev.platform_data)
memcpy(&wm9090->pdata, i2c->dev.platform_data,
sizeof(wm9090->pdata));
i2c_set_clientdata(i2c, wm9090);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_wm9090, NULL, 0);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
return ret;
}
return 0;
}
static const struct i2c_device_id wm9090_id[] = {
{ "wm9090", 0 },
{ "wm9093", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm9090_id);
static struct i2c_driver wm9090_i2c_driver = {
.driver = {
.name = "wm9090",
},
.probe = wm9090_i2c_probe,
.id_table = wm9090_id,
};
module_i2c_driver(wm9090_i2c_driver);
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_DESCRIPTION("WM9090 ASoC driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm9090.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ALSA SoC TLV320AIC23 codec driver I2C interface
*
* Author: Arun KS, <[email protected]>
* Copyright: (C) 2008 Mistral Solutions Pvt Ltd.,
*
* Based on sound/soc/codecs/wm8731.c by Richard Purdie
*/
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include "tlv320aic23.h"
static int tlv320aic23_i2c_probe(struct i2c_client *i2c)
{
struct regmap *regmap;
if (!i2c_check_functionality(i2c->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
return -EINVAL;
regmap = devm_regmap_init_i2c(i2c, &tlv320aic23_regmap);
return tlv320aic23_probe(&i2c->dev, regmap);
}
static const struct i2c_device_id tlv320aic23_id[] = {
{"tlv320aic23", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, tlv320aic23_id);
#ifdef CONFIG_OF
static const struct of_device_id tlv320aic23_of_match[] = {
{ .compatible = "ti,tlv320aic23", },
{ }
};
MODULE_DEVICE_TABLE(of, tlv320aic23_of_match);
#endif
static struct i2c_driver tlv320aic23_i2c_driver = {
.driver = {
.name = "tlv320aic23-codec",
.of_match_table = of_match_ptr(tlv320aic23_of_match),
},
.probe = tlv320aic23_i2c_probe,
.id_table = tlv320aic23_id,
};
module_i2c_driver(tlv320aic23_i2c_driver);
MODULE_DESCRIPTION("ASoC TLV320AIC23 codec driver I2C");
MODULE_AUTHOR("Arun KS <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/tlv320aic23-i2c.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// ALSA SoC glue to use IIO devices as audio components
//
// Copyright 2023 CS GROUP France
//
// Author: Herve Codina <[email protected]>
#include <linux/iio/consumer.h>
#include <linux/minmax.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/string_helpers.h>
#include <sound/soc.h>
#include <sound/tlv.h>
struct audio_iio_aux_chan {
struct iio_channel *iio_chan;
const char *name;
int max;
int min;
bool is_invert_range;
};
struct audio_iio_aux {
struct device *dev;
struct audio_iio_aux_chan *chans;
unsigned int num_chans;
};
static int audio_iio_aux_info_volsw(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
struct audio_iio_aux_chan *chan = (struct audio_iio_aux_chan *)kcontrol->private_value;
uinfo->count = 1;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = chan->max - chan->min;
uinfo->type = (uinfo->value.integer.max == 1) ?
SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
return 0;
}
static int audio_iio_aux_get_volsw(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct audio_iio_aux_chan *chan = (struct audio_iio_aux_chan *)kcontrol->private_value;
int max = chan->max;
int min = chan->min;
bool invert_range = chan->is_invert_range;
int ret;
int val;
ret = iio_read_channel_raw(chan->iio_chan, &val);
if (ret < 0)
return ret;
ucontrol->value.integer.value[0] = val - min;
if (invert_range)
ucontrol->value.integer.value[0] = max - ucontrol->value.integer.value[0];
return 0;
}
static int audio_iio_aux_put_volsw(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct audio_iio_aux_chan *chan = (struct audio_iio_aux_chan *)kcontrol->private_value;
int max = chan->max;
int min = chan->min;
bool invert_range = chan->is_invert_range;
int val;
int ret;
int tmp;
val = ucontrol->value.integer.value[0];
if (val < 0)
return -EINVAL;
if (val > max - min)
return -EINVAL;
val = val + min;
if (invert_range)
val = max - val;
ret = iio_read_channel_raw(chan->iio_chan, &tmp);
if (ret < 0)
return ret;
if (tmp == val)
return 0;
ret = iio_write_channel_raw(chan->iio_chan, val);
if (ret)
return ret;
return 1; /* The value changed */
}
static int audio_iio_aux_add_controls(struct snd_soc_component *component,
struct audio_iio_aux_chan *chan)
{
struct snd_kcontrol_new control = {
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = chan->name,
.info = audio_iio_aux_info_volsw,
.get = audio_iio_aux_get_volsw,
.put = audio_iio_aux_put_volsw,
.private_value = (unsigned long)chan,
};
return snd_soc_add_component_controls(component, &control, 1);
}
/*
* These data could be on stack but they are pretty big.
* As ASoC internally copy them and protect them against concurrent accesses
* (snd_soc_bind_card() protects using client_mutex), keep them in the global
* data area.
*/
static struct snd_soc_dapm_widget widgets[3];
static struct snd_soc_dapm_route routes[2];
/* Be sure sizes are correct (need 3 widgets and 2 routes) */
static_assert(ARRAY_SIZE(widgets) >= 3, "3 widgets are needed");
static_assert(ARRAY_SIZE(routes) >= 2, "2 routes are needed");
static int audio_iio_aux_add_dapms(struct snd_soc_component *component,
struct audio_iio_aux_chan *chan)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
char *output_name;
char *input_name;
char *pga_name;
int ret;
input_name = kasprintf(GFP_KERNEL, "%s IN", chan->name);
if (!input_name)
return -ENOMEM;
output_name = kasprintf(GFP_KERNEL, "%s OUT", chan->name);
if (!output_name) {
ret = -ENOMEM;
goto out_free_input_name;
}
pga_name = kasprintf(GFP_KERNEL, "%s PGA", chan->name);
if (!pga_name) {
ret = -ENOMEM;
goto out_free_output_name;
}
widgets[0] = SND_SOC_DAPM_INPUT(input_name);
widgets[1] = SND_SOC_DAPM_OUTPUT(output_name);
widgets[2] = SND_SOC_DAPM_PGA(pga_name, SND_SOC_NOPM, 0, 0, NULL, 0);
ret = snd_soc_dapm_new_controls(dapm, widgets, 3);
if (ret)
goto out_free_pga_name;
routes[0].sink = pga_name;
routes[0].control = NULL;
routes[0].source = input_name;
routes[1].sink = output_name;
routes[1].control = NULL;
routes[1].source = pga_name;
ret = snd_soc_dapm_add_routes(dapm, routes, 2);
/* Allocated names are no more needed (duplicated in ASoC internals) */
out_free_pga_name:
kfree(pga_name);
out_free_output_name:
kfree(output_name);
out_free_input_name:
kfree(input_name);
return ret;
}
static int audio_iio_aux_component_probe(struct snd_soc_component *component)
{
struct audio_iio_aux *iio_aux = snd_soc_component_get_drvdata(component);
struct audio_iio_aux_chan *chan;
int ret;
int i;
for (i = 0; i < iio_aux->num_chans; i++) {
chan = iio_aux->chans + i;
ret = iio_read_max_channel_raw(chan->iio_chan, &chan->max);
if (ret)
return dev_err_probe(component->dev, ret,
"chan[%d] %s: Cannot get max raw value\n",
i, chan->name);
ret = iio_read_min_channel_raw(chan->iio_chan, &chan->min);
if (ret)
return dev_err_probe(component->dev, ret,
"chan[%d] %s: Cannot get min raw value\n",
i, chan->name);
if (chan->min > chan->max) {
/*
* This should never happen but to avoid any check
* later, just swap values here to ensure that the
* minimum value is lower than the maximum value.
*/
dev_dbg(component->dev, "chan[%d] %s: Swap min and max\n",
i, chan->name);
swap(chan->min, chan->max);
}
/* Set initial value */
ret = iio_write_channel_raw(chan->iio_chan,
chan->is_invert_range ? chan->max : chan->min);
if (ret)
return dev_err_probe(component->dev, ret,
"chan[%d] %s: Cannot set initial value\n",
i, chan->name);
ret = audio_iio_aux_add_controls(component, chan);
if (ret)
return ret;
ret = audio_iio_aux_add_dapms(component, chan);
if (ret)
return ret;
dev_dbg(component->dev, "chan[%d]: Added %s (min=%d, max=%d, invert=%s)\n",
i, chan->name, chan->min, chan->max,
str_on_off(chan->is_invert_range));
}
return 0;
}
static const struct snd_soc_component_driver audio_iio_aux_component_driver = {
.probe = audio_iio_aux_component_probe,
};
static int audio_iio_aux_probe(struct platform_device *pdev)
{
struct audio_iio_aux_chan *iio_aux_chan;
struct device *dev = &pdev->dev;
struct audio_iio_aux *iio_aux;
const char **names;
u32 *invert_ranges;
int count;
int ret;
int i;
iio_aux = devm_kzalloc(dev, sizeof(*iio_aux), GFP_KERNEL);
if (!iio_aux)
return -ENOMEM;
iio_aux->dev = dev;
count = device_property_string_array_count(dev, "io-channel-names");
if (count < 0)
return dev_err_probe(dev, count, "failed to count io-channel-names\n");
iio_aux->num_chans = count;
iio_aux->chans = devm_kmalloc_array(dev, iio_aux->num_chans,
sizeof(*iio_aux->chans), GFP_KERNEL);
if (!iio_aux->chans)
return -ENOMEM;
names = kcalloc(iio_aux->num_chans, sizeof(*names), GFP_KERNEL);
if (!names)
return -ENOMEM;
invert_ranges = kcalloc(iio_aux->num_chans, sizeof(*invert_ranges), GFP_KERNEL);
if (!invert_ranges) {
ret = -ENOMEM;
goto out_free_names;
}
ret = device_property_read_string_array(dev, "io-channel-names",
names, iio_aux->num_chans);
if (ret < 0) {
dev_err_probe(dev, ret, "failed to read io-channel-names\n");
goto out_free_invert_ranges;
}
/*
* snd-control-invert-range is optional and can contain fewer items
* than the number of channels. Unset values default to 0.
*/
count = device_property_count_u32(dev, "snd-control-invert-range");
if (count > 0) {
count = min_t(unsigned int, count, iio_aux->num_chans);
ret = device_property_read_u32_array(dev, "snd-control-invert-range",
invert_ranges, count);
if (ret < 0) {
dev_err_probe(dev, ret, "failed to read snd-control-invert-range\n");
goto out_free_invert_ranges;
}
}
for (i = 0; i < iio_aux->num_chans; i++) {
iio_aux_chan = iio_aux->chans + i;
iio_aux_chan->name = names[i];
iio_aux_chan->is_invert_range = invert_ranges[i];
iio_aux_chan->iio_chan = devm_iio_channel_get(dev, iio_aux_chan->name);
if (IS_ERR(iio_aux_chan->iio_chan)) {
ret = PTR_ERR(iio_aux_chan->iio_chan);
dev_err_probe(dev, ret, "get IIO channel '%s' failed\n",
iio_aux_chan->name);
goto out_free_invert_ranges;
}
}
platform_set_drvdata(pdev, iio_aux);
ret = devm_snd_soc_register_component(dev, &audio_iio_aux_component_driver,
NULL, 0);
out_free_invert_ranges:
kfree(invert_ranges);
out_free_names:
kfree(names);
return ret;
}
static const struct of_device_id audio_iio_aux_ids[] = {
{ .compatible = "audio-iio-aux" },
{ }
};
MODULE_DEVICE_TABLE(of, audio_iio_aux_ids);
static struct platform_driver audio_iio_aux_driver = {
.driver = {
.name = "audio-iio-aux",
.of_match_table = audio_iio_aux_ids,
},
.probe = audio_iio_aux_probe,
};
module_platform_driver(audio_iio_aux_driver);
MODULE_AUTHOR("Herve Codina <[email protected]>");
MODULE_DESCRIPTION("IIO ALSA SoC aux driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/audio-iio-aux.c |
// SPDX-License-Identifier: GPL-2.0
//
// Driver for the MAX9860 Mono Audio Voice Codec
//
// https://datasheets.maximintegrated.com/en/ds/MAX9860.pdf
//
// The driver does not support sidetone since the DVST register field is
// backwards with the mute near the maximum level instead of the minimum.
//
// Author: Peter Rosin <[email protected]>
// Copyright 2016 Axentia Technologies
#include <linux/init.h>
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/kernel.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/i2c.h>
#include <linux/regulator/consumer.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/pcm_params.h>
#include <sound/tlv.h>
#include "max9860.h"
struct max9860_priv {
struct regmap *regmap;
struct regulator *dvddio;
struct notifier_block dvddio_nb;
u8 psclk;
unsigned long pclk_rate;
int fmt;
};
static int max9860_dvddio_event(struct notifier_block *nb,
unsigned long event, void *data)
{
struct max9860_priv *max9860 = container_of(nb, struct max9860_priv,
dvddio_nb);
if (event & REGULATOR_EVENT_DISABLE) {
regcache_mark_dirty(max9860->regmap);
regcache_cache_only(max9860->regmap, true);
}
return 0;
}
static const struct reg_default max9860_reg_defaults[] = {
{ MAX9860_PWRMAN, 0x00 },
{ MAX9860_INTEN, 0x00 },
{ MAX9860_SYSCLK, 0x00 },
{ MAX9860_AUDIOCLKHIGH, 0x00 },
{ MAX9860_AUDIOCLKLOW, 0x00 },
{ MAX9860_IFC1A, 0x00 },
{ MAX9860_IFC1B, 0x00 },
{ MAX9860_VOICEFLTR, 0x00 },
{ MAX9860_DACATTN, 0x00 },
{ MAX9860_ADCLEVEL, 0x00 },
{ MAX9860_DACGAIN, 0x00 },
{ MAX9860_MICGAIN, 0x00 },
{ MAX9860_MICADC, 0x00 },
{ MAX9860_NOISEGATE, 0x00 },
};
static bool max9860_readable(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX9860_INTRSTATUS ... MAX9860_MICGAIN:
case MAX9860_MICADC ... MAX9860_PWRMAN:
case MAX9860_REVISION:
return true;
}
return false;
}
static bool max9860_writeable(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX9860_INTEN ... MAX9860_MICGAIN:
case MAX9860_MICADC ... MAX9860_PWRMAN:
return true;
}
return false;
}
static bool max9860_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX9860_INTRSTATUS:
case MAX9860_MICREADBACK:
return true;
}
return false;
}
static bool max9860_precious(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX9860_INTRSTATUS:
return true;
}
return false;
}
static const struct regmap_config max9860_regmap = {
.reg_bits = 8,
.val_bits = 8,
.readable_reg = max9860_readable,
.writeable_reg = max9860_writeable,
.volatile_reg = max9860_volatile,
.precious_reg = max9860_precious,
.max_register = MAX9860_MAX_REGISTER,
.reg_defaults = max9860_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(max9860_reg_defaults),
.cache_type = REGCACHE_RBTREE,
};
static const DECLARE_TLV_DB_SCALE(dva_tlv, -9100, 100, 1);
static const DECLARE_TLV_DB_SCALE(dvg_tlv, 0, 600, 0);
static const DECLARE_TLV_DB_SCALE(adc_tlv, -1200, 100, 0);
static const DECLARE_TLV_DB_RANGE(pam_tlv,
0, MAX9860_PAM_MAX - 1, TLV_DB_SCALE_ITEM(-2000, 2000, 1),
MAX9860_PAM_MAX, MAX9860_PAM_MAX, TLV_DB_SCALE_ITEM(3000, 0, 0));
static const DECLARE_TLV_DB_SCALE(pgam_tlv, 0, 100, 0);
static const DECLARE_TLV_DB_SCALE(anth_tlv, -7600, 400, 1);
static const DECLARE_TLV_DB_SCALE(agcth_tlv, -1800, 100, 0);
static const char * const agchld_text[] = {
"AGC Disabled", "50ms", "100ms", "400ms"
};
static SOC_ENUM_SINGLE_DECL(agchld_enum, MAX9860_MICADC,
MAX9860_AGCHLD_SHIFT, agchld_text);
static const char * const agcsrc_text[] = {
"Left ADC", "Left/Right ADC"
};
static SOC_ENUM_SINGLE_DECL(agcsrc_enum, MAX9860_MICADC,
MAX9860_AGCSRC_SHIFT, agcsrc_text);
static const char * const agcatk_text[] = {
"3ms", "12ms", "50ms", "200ms"
};
static SOC_ENUM_SINGLE_DECL(agcatk_enum, MAX9860_MICADC,
MAX9860_AGCATK_SHIFT, agcatk_text);
static const char * const agcrls_text[] = {
"78ms", "156ms", "312ms", "625ms",
"1.25s", "2.5s", "5s", "10s"
};
static SOC_ENUM_SINGLE_DECL(agcrls_enum, MAX9860_MICADC,
MAX9860_AGCRLS_SHIFT, agcrls_text);
static const char * const filter_text[] = {
"Disabled",
"Elliptical HP 217Hz notch (16kHz)",
"Butterworth HP 500Hz (16kHz)",
"Elliptical HP 217Hz notch (8kHz)",
"Butterworth HP 500Hz (8kHz)",
"Butterworth HP 200Hz (48kHz)"
};
static SOC_ENUM_SINGLE_DECL(avflt_enum, MAX9860_VOICEFLTR,
MAX9860_AVFLT_SHIFT, filter_text);
static SOC_ENUM_SINGLE_DECL(dvflt_enum, MAX9860_VOICEFLTR,
MAX9860_DVFLT_SHIFT, filter_text);
static const struct snd_kcontrol_new max9860_controls[] = {
SOC_SINGLE_TLV("Master Playback Volume", MAX9860_DACATTN,
MAX9860_DVA_SHIFT, MAX9860_DVA_MUTE, 1, dva_tlv),
SOC_SINGLE_TLV("DAC Gain Volume", MAX9860_DACGAIN,
MAX9860_DVG_SHIFT, MAX9860_DVG_MAX, 0, dvg_tlv),
SOC_DOUBLE_TLV("Line Capture Volume", MAX9860_ADCLEVEL,
MAX9860_ADCLL_SHIFT, MAX9860_ADCRL_SHIFT, MAX9860_ADCxL_MIN, 1,
adc_tlv),
SOC_ENUM("AGC Hold Time", agchld_enum),
SOC_ENUM("AGC/Noise Gate Source", agcsrc_enum),
SOC_ENUM("AGC Attack Time", agcatk_enum),
SOC_ENUM("AGC Release Time", agcrls_enum),
SOC_SINGLE_TLV("Noise Gate Threshold Volume", MAX9860_NOISEGATE,
MAX9860_ANTH_SHIFT, MAX9860_ANTH_MAX, 0, anth_tlv),
SOC_SINGLE_TLV("AGC Signal Threshold Volume", MAX9860_NOISEGATE,
MAX9860_AGCTH_SHIFT, MAX9860_AGCTH_MIN, 1, agcth_tlv),
SOC_SINGLE_TLV("Mic PGA Volume", MAX9860_MICGAIN,
MAX9860_PGAM_SHIFT, MAX9860_PGAM_MIN, 1, pgam_tlv),
SOC_SINGLE_TLV("Mic Preamp Volume", MAX9860_MICGAIN,
MAX9860_PAM_SHIFT, MAX9860_PAM_MAX, 0, pam_tlv),
SOC_ENUM("ADC Filter", avflt_enum),
SOC_ENUM("DAC Filter", dvflt_enum),
};
static const struct snd_soc_dapm_widget max9860_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("MICL"),
SND_SOC_DAPM_INPUT("MICR"),
SND_SOC_DAPM_ADC("ADCL", NULL, MAX9860_PWRMAN, MAX9860_ADCLEN_SHIFT, 0),
SND_SOC_DAPM_ADC("ADCR", NULL, MAX9860_PWRMAN, MAX9860_ADCREN_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DAC", NULL, MAX9860_PWRMAN, MAX9860_DACEN_SHIFT, 0),
SND_SOC_DAPM_OUTPUT("OUT"),
SND_SOC_DAPM_SUPPLY("Supply", SND_SOC_NOPM, 0, 0,
NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_REGULATOR_SUPPLY("AVDD", 0, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("DVDD", 0, 0),
SND_SOC_DAPM_CLOCK_SUPPLY("mclk"),
};
static const struct snd_soc_dapm_route max9860_dapm_routes[] = {
{ "ADCL", NULL, "MICL" },
{ "ADCR", NULL, "MICR" },
{ "AIFOUTL", NULL, "ADCL" },
{ "AIFOUTR", NULL, "ADCR" },
{ "DAC", NULL, "AIFINL" },
{ "DAC", NULL, "AIFINR" },
{ "OUT", NULL, "DAC" },
{ "Supply", NULL, "AVDD" },
{ "Supply", NULL, "DVDD" },
{ "Supply", NULL, "mclk" },
{ "DAC", NULL, "Supply" },
{ "ADCL", NULL, "Supply" },
{ "ADCR", NULL, "Supply" },
};
static int max9860_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct max9860_priv *max9860 = snd_soc_component_get_drvdata(component);
u8 master;
u8 ifc1a = 0;
u8 ifc1b = 0;
u8 sysclk = 0;
unsigned long n;
int ret;
dev_dbg(component->dev, "hw_params %u Hz, %u channels\n",
params_rate(params),
params_channels(params));
if (params_channels(params) == 2)
ifc1b |= MAX9860_ST;
switch (max9860->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC:
master = 0;
break;
case SND_SOC_DAIFMT_CBP_CFP:
master = MAX9860_MASTER;
break;
default:
return -EINVAL;
}
ifc1a |= master;
if (master) {
if (params_width(params) * params_channels(params) > 48)
ifc1b |= MAX9860_BSEL_64X;
else
ifc1b |= MAX9860_BSEL_48X;
}
switch (max9860->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
ifc1a |= MAX9860_DDLY;
ifc1b |= MAX9860_ADLY;
break;
case SND_SOC_DAIFMT_LEFT_J:
ifc1a |= MAX9860_WCI;
break;
case SND_SOC_DAIFMT_DSP_A:
if (params_width(params) != 16) {
dev_err(component->dev,
"DSP_A works for 16 bits per sample only.\n");
return -EINVAL;
}
ifc1a |= MAX9860_DDLY | MAX9860_WCI | MAX9860_HIZ | MAX9860_TDM;
ifc1b |= MAX9860_ADLY;
break;
case SND_SOC_DAIFMT_DSP_B:
if (params_width(params) != 16) {
dev_err(component->dev,
"DSP_B works for 16 bits per sample only.\n");
return -EINVAL;
}
ifc1a |= MAX9860_WCI | MAX9860_HIZ | MAX9860_TDM;
break;
default:
return -EINVAL;
}
switch (max9860->fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_NB_IF:
switch (max9860->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B:
return -EINVAL;
}
ifc1a ^= MAX9860_WCI;
break;
case SND_SOC_DAIFMT_IB_IF:
switch (max9860->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B:
return -EINVAL;
}
ifc1a ^= MAX9860_WCI;
fallthrough;
case SND_SOC_DAIFMT_IB_NF:
ifc1a ^= MAX9860_DBCI;
ifc1b ^= MAX9860_ABCI;
break;
default:
return -EINVAL;
}
dev_dbg(component->dev, "IFC1A %02x\n", ifc1a);
ret = regmap_write(max9860->regmap, MAX9860_IFC1A, ifc1a);
if (ret) {
dev_err(component->dev, "Failed to set IFC1A: %d\n", ret);
return ret;
}
dev_dbg(component->dev, "IFC1B %02x\n", ifc1b);
ret = regmap_write(max9860->regmap, MAX9860_IFC1B, ifc1b);
if (ret) {
dev_err(component->dev, "Failed to set IFC1B: %d\n", ret);
return ret;
}
/*
* Check if Integer Clock Mode is possible, but avoid it in slave mode
* since we then do not know if lrclk is derived from pclk and the
* datasheet mentions that the frequencies have to match exactly in
* order for this to work.
*/
if (params_rate(params) == 8000 || params_rate(params) == 16000) {
if (master) {
switch (max9860->pclk_rate) {
case 12000000:
sysclk = MAX9860_FREQ_12MHZ;
break;
case 13000000:
sysclk = MAX9860_FREQ_13MHZ;
break;
case 19200000:
sysclk = MAX9860_FREQ_19_2MHZ;
break;
default:
/*
* Integer Clock Mode not possible. Leave
* sysclk at zero and fall through to the
* code below for PLL mode.
*/
break;
}
if (sysclk && params_rate(params) == 16000)
sysclk |= MAX9860_16KHZ;
}
}
/*
* Largest possible n:
* 65536 * 96 * 48kHz / 10MHz -> 30199
* Smallest possible n:
* 65536 * 96 * 8kHz / 20MHz -> 2517
* Both fit nicely in the available 15 bits, no need to apply any mask.
*/
n = DIV_ROUND_CLOSEST_ULL(65536ULL * 96 * params_rate(params),
max9860->pclk_rate);
if (!sysclk) {
/* PLL mode */
if (params_rate(params) > 24000)
sysclk |= MAX9860_16KHZ;
if (!master)
n |= 1; /* trigger rapid pll lock mode */
}
sysclk |= max9860->psclk;
dev_dbg(component->dev, "SYSCLK %02x\n", sysclk);
ret = regmap_write(max9860->regmap,
MAX9860_SYSCLK, sysclk);
if (ret) {
dev_err(component->dev, "Failed to set SYSCLK: %d\n", ret);
return ret;
}
dev_dbg(component->dev, "N %lu\n", n);
ret = regmap_write(max9860->regmap,
MAX9860_AUDIOCLKHIGH, n >> 8);
if (ret) {
dev_err(component->dev, "Failed to set NHI: %d\n", ret);
return ret;
}
ret = regmap_write(max9860->regmap,
MAX9860_AUDIOCLKLOW, n & 0xff);
if (ret) {
dev_err(component->dev, "Failed to set NLO: %d\n", ret);
return ret;
}
if (!master) {
dev_dbg(component->dev, "Enable PLL\n");
ret = regmap_update_bits(max9860->regmap, MAX9860_AUDIOCLKHIGH,
MAX9860_PLL, MAX9860_PLL);
if (ret) {
dev_err(component->dev, "Failed to enable PLL: %d\n",
ret);
return ret;
}
}
return 0;
}
static int max9860_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct max9860_priv *max9860 = snd_soc_component_get_drvdata(component);
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
case SND_SOC_DAIFMT_CBC_CFC:
max9860->fmt = fmt;
return 0;
default:
return -EINVAL;
}
}
static const struct snd_soc_dai_ops max9860_dai_ops = {
.hw_params = max9860_hw_params,
.set_fmt = max9860_set_fmt,
};
static struct snd_soc_dai_driver max9860_dai = {
.name = "max9860-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.rate_min = 8000,
.rate_max = 48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S32_LE,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.rate_min = 8000,
.rate_max = 48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S32_LE,
},
.ops = &max9860_dai_ops,
.symmetric_rate = 1,
};
static int max9860_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct max9860_priv *max9860 = dev_get_drvdata(component->dev);
int ret;
switch (level) {
case SND_SOC_BIAS_ON:
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
ret = regmap_update_bits(max9860->regmap, MAX9860_PWRMAN,
MAX9860_SHDN, MAX9860_SHDN);
if (ret) {
dev_err(component->dev, "Failed to remove SHDN: %d\n",
ret);
return ret;
}
break;
case SND_SOC_BIAS_OFF:
ret = regmap_update_bits(max9860->regmap, MAX9860_PWRMAN,
MAX9860_SHDN, 0);
if (ret) {
dev_err(component->dev, "Failed to request SHDN: %d\n",
ret);
return ret;
}
break;
}
return 0;
}
static const struct snd_soc_component_driver max9860_component_driver = {
.set_bias_level = max9860_set_bias_level,
.controls = max9860_controls,
.num_controls = ARRAY_SIZE(max9860_controls),
.dapm_widgets = max9860_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(max9860_dapm_widgets),
.dapm_routes = max9860_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(max9860_dapm_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
#ifdef CONFIG_PM
static int max9860_suspend(struct device *dev)
{
struct max9860_priv *max9860 = dev_get_drvdata(dev);
int ret;
ret = regmap_update_bits(max9860->regmap, MAX9860_SYSCLK,
MAX9860_PSCLK, MAX9860_PSCLK_OFF);
if (ret) {
dev_err(dev, "Failed to disable clock: %d\n", ret);
return ret;
}
regulator_disable(max9860->dvddio);
return 0;
}
static int max9860_resume(struct device *dev)
{
struct max9860_priv *max9860 = dev_get_drvdata(dev);
int ret;
ret = regulator_enable(max9860->dvddio);
if (ret) {
dev_err(dev, "Failed to enable DVDDIO: %d\n", ret);
return ret;
}
regcache_cache_only(max9860->regmap, false);
ret = regcache_sync(max9860->regmap);
if (ret) {
dev_err(dev, "Failed to sync cache: %d\n", ret);
return ret;
}
ret = regmap_update_bits(max9860->regmap, MAX9860_SYSCLK,
MAX9860_PSCLK, max9860->psclk);
if (ret) {
dev_err(dev, "Failed to enable clock: %d\n", ret);
return ret;
}
return 0;
}
#endif
static const struct dev_pm_ops max9860_pm_ops = {
SET_RUNTIME_PM_OPS(max9860_suspend, max9860_resume, NULL)
};
static int max9860_probe(struct i2c_client *i2c)
{
struct device *dev = &i2c->dev;
struct max9860_priv *max9860;
int ret;
struct clk *mclk;
unsigned long mclk_rate;
int i;
int intr;
max9860 = devm_kzalloc(dev, sizeof(struct max9860_priv), GFP_KERNEL);
if (!max9860)
return -ENOMEM;
max9860->dvddio = devm_regulator_get(dev, "DVDDIO");
if (IS_ERR(max9860->dvddio))
return dev_err_probe(dev, PTR_ERR(max9860->dvddio),
"Failed to get DVDDIO supply\n");
max9860->dvddio_nb.notifier_call = max9860_dvddio_event;
ret = devm_regulator_register_notifier(max9860->dvddio,
&max9860->dvddio_nb);
if (ret)
dev_err(dev, "Failed to register DVDDIO notifier: %d\n", ret);
ret = regulator_enable(max9860->dvddio);
if (ret != 0) {
dev_err(dev, "Failed to enable DVDDIO: %d\n", ret);
return ret;
}
max9860->regmap = devm_regmap_init_i2c(i2c, &max9860_regmap);
if (IS_ERR(max9860->regmap)) {
ret = PTR_ERR(max9860->regmap);
goto err_regulator;
}
dev_set_drvdata(dev, max9860);
/*
* mclk has to be in the 10MHz to 60MHz range.
* psclk is used to scale mclk into pclk so that
* pclk is in the 10MHz to 20MHz range.
*/
mclk = clk_get(dev, "mclk");
if (IS_ERR(mclk)) {
ret = PTR_ERR(mclk);
dev_err_probe(dev, ret, "Failed to get MCLK\n");
goto err_regulator;
}
mclk_rate = clk_get_rate(mclk);
clk_put(mclk);
if (mclk_rate > 60000000 || mclk_rate < 10000000) {
dev_err(dev, "Bad mclk %luHz (needs 10MHz - 60MHz)\n",
mclk_rate);
ret = -EINVAL;
goto err_regulator;
}
if (mclk_rate >= 40000000)
max9860->psclk = 3;
else if (mclk_rate >= 20000000)
max9860->psclk = 2;
else
max9860->psclk = 1;
max9860->pclk_rate = mclk_rate >> (max9860->psclk - 1);
max9860->psclk <<= MAX9860_PSCLK_SHIFT;
dev_dbg(dev, "mclk %lu pclk %lu\n", mclk_rate, max9860->pclk_rate);
regcache_cache_bypass(max9860->regmap, true);
for (i = 0; i < max9860_regmap.num_reg_defaults; ++i) {
ret = regmap_write(max9860->regmap,
max9860_regmap.reg_defaults[i].reg,
max9860_regmap.reg_defaults[i].def);
if (ret) {
dev_err(dev, "Failed to initialize register %u: %d\n",
max9860_regmap.reg_defaults[i].reg, ret);
goto err_regulator;
}
}
regcache_cache_bypass(max9860->regmap, false);
ret = regmap_read(max9860->regmap, MAX9860_INTRSTATUS, &intr);
if (ret) {
dev_err(dev, "Failed to clear INTRSTATUS: %d\n", ret);
goto err_regulator;
}
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
pm_runtime_idle(dev);
ret = devm_snd_soc_register_component(dev, &max9860_component_driver,
&max9860_dai, 1);
if (ret) {
dev_err(dev, "Failed to register CODEC: %d\n", ret);
goto err_pm;
}
return 0;
err_pm:
pm_runtime_disable(dev);
err_regulator:
regulator_disable(max9860->dvddio);
return ret;
}
static void max9860_remove(struct i2c_client *i2c)
{
struct device *dev = &i2c->dev;
struct max9860_priv *max9860 = dev_get_drvdata(dev);
pm_runtime_disable(dev);
regulator_disable(max9860->dvddio);
}
static const struct i2c_device_id max9860_i2c_id[] = {
{ "max9860", },
{ }
};
MODULE_DEVICE_TABLE(i2c, max9860_i2c_id);
static const struct of_device_id max9860_of_match[] = {
{ .compatible = "maxim,max9860", },
{ }
};
MODULE_DEVICE_TABLE(of, max9860_of_match);
static struct i2c_driver max9860_i2c_driver = {
.probe = max9860_probe,
.remove = max9860_remove,
.id_table = max9860_i2c_id,
.driver = {
.name = "max9860",
.of_match_table = max9860_of_match,
.pm = &max9860_pm_ops,
},
};
module_i2c_driver(max9860_i2c_driver);
MODULE_DESCRIPTION("ASoC MAX9860 Mono Audio Voice Codec driver");
MODULE_AUTHOR("Peter Rosin <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/max9860.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// rt712-sdca-dmic.c -- rt712 SDCA DMIC ALSA SoC audio driver
//
// Copyright(c) 2023 Realtek Semiconductor Corp.
//
//
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/pm_runtime.h>
#include <linux/soundwire/sdw_registers.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/tlv.h>
#include "rt712-sdca.h"
#include "rt712-sdca-dmic.h"
static bool rt712_sdca_dmic_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x201a ... 0x201f:
case 0x2029 ... 0x202a:
case 0x202d ... 0x2034:
case 0x2230 ... 0x2232:
case 0x2f01 ... 0x2f0a:
case 0x2f35 ... 0x2f36:
case 0x2f52:
case 0x2f58 ... 0x2f59:
case 0x3201:
case 0x320c:
return true;
default:
return false;
}
}
static bool rt712_sdca_dmic_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x201b:
case 0x201c:
case 0x201d:
case 0x201f:
case 0x202d ... 0x202f:
case 0x2230:
case 0x2f01:
case 0x2f35:
case 0x320c:
return true;
default:
return false;
}
}
static bool rt712_sdca_dmic_mbq_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x2000000 ... 0x200008e:
case 0x5300000 ... 0x530000e:
case 0x5400000 ... 0x540000e:
case 0x5600000 ... 0x5600008:
case 0x5700000 ... 0x570000d:
case 0x5800000 ... 0x5800021:
case 0x5900000 ... 0x5900028:
case 0x5a00000 ... 0x5a00009:
case 0x5b00000 ... 0x5b00051:
case 0x5c00000 ... 0x5c0009a:
case 0x5d00000 ... 0x5d00009:
case 0x5f00000 ... 0x5f00030:
case 0x6100000 ... 0x6100068:
case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT712_SDCA_ENT_USER_FU1E, RT712_SDCA_CTL_FU_VOLUME, CH_01):
case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT712_SDCA_ENT_USER_FU1E, RT712_SDCA_CTL_FU_VOLUME, CH_02):
case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT712_SDCA_ENT_USER_FU1E, RT712_SDCA_CTL_FU_VOLUME, CH_03):
case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT712_SDCA_ENT_USER_FU1E, RT712_SDCA_CTL_FU_VOLUME, CH_04):
case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT712_SDCA_ENT_PLATFORM_FU15, RT712_SDCA_CTL_FU_CH_GAIN, CH_01):
case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT712_SDCA_ENT_PLATFORM_FU15, RT712_SDCA_CTL_FU_CH_GAIN, CH_02):
case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT712_SDCA_ENT_PLATFORM_FU15, RT712_SDCA_CTL_FU_CH_GAIN, CH_03):
case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT712_SDCA_ENT_PLATFORM_FU15, RT712_SDCA_CTL_FU_CH_GAIN, CH_04):
return true;
default:
return false;
}
}
static bool rt712_sdca_dmic_mbq_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x2000000:
case 0x200001a:
case 0x2000024:
case 0x2000046:
case 0x200008a:
case 0x5800000:
case 0x5800001:
case 0x6100008:
return true;
default:
return false;
}
}
static const struct regmap_config rt712_sdca_dmic_regmap = {
.reg_bits = 32,
.val_bits = 8,
.readable_reg = rt712_sdca_dmic_readable_register,
.volatile_reg = rt712_sdca_dmic_volatile_register,
.max_register = 0x40981300,
.reg_defaults = rt712_sdca_dmic_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(rt712_sdca_dmic_reg_defaults),
.cache_type = REGCACHE_MAPLE,
.use_single_read = true,
.use_single_write = true,
};
static const struct regmap_config rt712_sdca_dmic_mbq_regmap = {
.name = "sdw-mbq",
.reg_bits = 32,
.val_bits = 16,
.readable_reg = rt712_sdca_dmic_mbq_readable_register,
.volatile_reg = rt712_sdca_dmic_mbq_volatile_register,
.max_register = 0x40800f14,
.reg_defaults = rt712_sdca_dmic_mbq_defaults,
.num_reg_defaults = ARRAY_SIZE(rt712_sdca_dmic_mbq_defaults),
.cache_type = REGCACHE_MAPLE,
.use_single_read = true,
.use_single_write = true,
};
static int rt712_sdca_dmic_index_write(struct rt712_sdca_dmic_priv *rt712,
unsigned int nid, unsigned int reg, unsigned int value)
{
int ret;
struct regmap *regmap = rt712->mbq_regmap;
unsigned int addr = (nid << 20) | reg;
ret = regmap_write(regmap, addr, value);
if (ret < 0)
dev_err(&rt712->slave->dev,
"Failed to set private value: %06x <= %04x ret=%d\n",
addr, value, ret);
return ret;
}
static int rt712_sdca_dmic_index_read(struct rt712_sdca_dmic_priv *rt712,
unsigned int nid, unsigned int reg, unsigned int *value)
{
int ret;
struct regmap *regmap = rt712->mbq_regmap;
unsigned int addr = (nid << 20) | reg;
ret = regmap_read(regmap, addr, value);
if (ret < 0)
dev_err(&rt712->slave->dev,
"Failed to get private value: %06x => %04x ret=%d\n",
addr, *value, ret);
return ret;
}
static int rt712_sdca_dmic_index_update_bits(struct rt712_sdca_dmic_priv *rt712,
unsigned int nid, unsigned int reg, unsigned int mask, unsigned int val)
{
unsigned int tmp;
int ret;
ret = rt712_sdca_dmic_index_read(rt712, nid, reg, &tmp);
if (ret < 0)
return ret;
set_mask_bits(&tmp, mask, val);
return rt712_sdca_dmic_index_write(rt712, nid, reg, tmp);
}
static int rt712_sdca_dmic_io_init(struct device *dev, struct sdw_slave *slave)
{
struct rt712_sdca_dmic_priv *rt712 = dev_get_drvdata(dev);
if (rt712->hw_init)
return 0;
regcache_cache_only(rt712->regmap, false);
regcache_cache_only(rt712->mbq_regmap, false);
if (rt712->first_hw_init) {
regcache_cache_bypass(rt712->regmap, true);
regcache_cache_bypass(rt712->mbq_regmap, true);
} else {
/*
* PM runtime status is marked as 'active' only when a Slave reports as Attached
*/
/* update count of parent 'active' children */
pm_runtime_set_active(&slave->dev);
}
pm_runtime_get_noresume(&slave->dev);
rt712_sdca_dmic_index_write(rt712, RT712_VENDOR_HDA_CTL,
RT712_ADC0A_08_PDE_FLOAT_CTL, 0x1112);
rt712_sdca_dmic_index_write(rt712, RT712_VENDOR_HDA_CTL,
RT712_ADC0B_11_PDE_FLOAT_CTL, 0x1111);
rt712_sdca_dmic_index_write(rt712, RT712_VENDOR_HDA_CTL,
RT712_DMIC1_2_PDE_FLOAT_CTL, 0x1111);
rt712_sdca_dmic_index_write(rt712, RT712_VENDOR_HDA_CTL,
RT712_I2S_IN_OUT_PDE_FLOAT_CTL, 0x1155);
rt712_sdca_dmic_index_write(rt712, RT712_VENDOR_HDA_CTL,
RT712_DMIC_ENT_FLOAT_CTL, 0x2626);
rt712_sdca_dmic_index_write(rt712, RT712_VENDOR_HDA_CTL,
RT712_ADC_ENT_FLOAT_CTL, 0x1e19);
rt712_sdca_dmic_index_write(rt712, RT712_VENDOR_HDA_CTL,
RT712_DMIC_GAIN_ENT_FLOAT_CTL0, 0x1515);
rt712_sdca_dmic_index_write(rt712, RT712_VENDOR_HDA_CTL,
RT712_ADC_VOL_CH_FLOAT_CTL2, 0x0304);
rt712_sdca_dmic_index_write(rt712, RT712_VENDOR_HDA_CTL,
RT712_DMIC_GAIN_ENT_FLOAT_CTL2, 0x0304);
rt712_sdca_dmic_index_write(rt712, RT712_VENDOR_HDA_CTL,
RT712_HDA_LEGACY_CONFIG_CTL0, 0x0050);
regmap_write(rt712->regmap,
SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT712_SDCA_ENT_IT26, RT712_SDCA_CTL_VENDOR_DEF, 0), 0x01);
rt712_sdca_dmic_index_write(rt712, RT712_ULTRA_SOUND_DET,
RT712_ULTRA_SOUND_DETECTOR6, 0x3200);
regmap_write(rt712->regmap, RT712_RC_CAL, 0x23);
regmap_write(rt712->regmap, 0x2f52, 0x00);
if (rt712->first_hw_init) {
regcache_cache_bypass(rt712->regmap, false);
regcache_mark_dirty(rt712->regmap);
regcache_cache_bypass(rt712->mbq_regmap, false);
regcache_mark_dirty(rt712->mbq_regmap);
} else
rt712->first_hw_init = true;
/* Mark Slave initialization complete */
rt712->hw_init = true;
pm_runtime_mark_last_busy(&slave->dev);
pm_runtime_put_autosuspend(&slave->dev);
dev_dbg(&slave->dev, "%s hw_init complete\n", __func__);
return 0;
}
static int rt712_sdca_dmic_set_gain_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt712_sdca_priv *rt712 = snd_soc_component_get_drvdata(component);
struct rt712_sdca_dmic_kctrl_priv *p =
(struct rt712_sdca_dmic_kctrl_priv *)kcontrol->private_value;
unsigned int regvalue, ctl, i;
unsigned int adc_vol_flag = 0;
const unsigned int interval_offset = 0xc0;
if (strstr(ucontrol->id.name, "FU1E Capture Volume"))
adc_vol_flag = 1;
/* check all channels */
for (i = 0; i < p->count; i++) {
regmap_read(rt712->mbq_regmap, p->reg_base + i, ®value);
if (!adc_vol_flag) /* boost gain */
ctl = regvalue / 0x0a00;
else { /* ADC gain */
if (adc_vol_flag)
ctl = p->max - (((0x1e00 - regvalue) & 0xffff) / interval_offset);
else
ctl = p->max - (((0 - regvalue) & 0xffff) / interval_offset);
}
ucontrol->value.integer.value[i] = ctl;
}
return 0;
}
static int rt712_sdca_dmic_set_gain_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt712_sdca_dmic_kctrl_priv *p =
(struct rt712_sdca_dmic_kctrl_priv *)kcontrol->private_value;
struct rt712_sdca_priv *rt712 = snd_soc_component_get_drvdata(component);
unsigned int gain_val[4];
unsigned int i, adc_vol_flag = 0, changed = 0;
unsigned int regvalue[4];
const unsigned int interval_offset = 0xc0;
int err;
if (strstr(ucontrol->id.name, "FU1E Capture Volume"))
adc_vol_flag = 1;
/* check all channels */
for (i = 0; i < p->count; i++) {
regmap_read(rt712->mbq_regmap, p->reg_base + i, ®value[i]);
gain_val[i] = ucontrol->value.integer.value[i];
if (gain_val[i] > p->max)
gain_val[i] = p->max;
if (!adc_vol_flag) /* boost gain */
gain_val[i] = gain_val[i] * 0x0a00;
else { /* ADC gain */
gain_val[i] = 0x1e00 - ((p->max - gain_val[i]) * interval_offset);
gain_val[i] &= 0xffff;
}
if (regvalue[i] != gain_val[i])
changed = 1;
}
if (!changed)
return 0;
for (i = 0; i < p->count; i++) {
err = regmap_write(rt712->mbq_regmap, p->reg_base + i, gain_val[i]);
if (err < 0)
dev_err(&rt712->slave->dev, "0x%08x can't be set\n", p->reg_base + i);
}
return changed;
}
static int rt712_sdca_set_fu1e_capture_ctl(struct rt712_sdca_dmic_priv *rt712)
{
int err, i;
unsigned int ch_mute;
for (i = 0; i < ARRAY_SIZE(rt712->fu1e_mixer_mute); i++) {
ch_mute = (rt712->fu1e_dapm_mute || rt712->fu1e_mixer_mute[i]) ? 0x01 : 0x00;
err = regmap_write(rt712->regmap,
SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT712_SDCA_ENT_USER_FU1E,
RT712_SDCA_CTL_FU_MUTE, CH_01) + i, ch_mute);
if (err < 0)
return err;
}
return 0;
}
static int rt712_sdca_dmic_fu1e_capture_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt712_sdca_dmic_priv *rt712 = snd_soc_component_get_drvdata(component);
struct rt712_sdca_dmic_kctrl_priv *p =
(struct rt712_sdca_dmic_kctrl_priv *)kcontrol->private_value;
unsigned int i;
for (i = 0; i < p->count; i++)
ucontrol->value.integer.value[i] = !rt712->fu1e_mixer_mute[i];
return 0;
}
static int rt712_sdca_dmic_fu1e_capture_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt712_sdca_dmic_priv *rt712 = snd_soc_component_get_drvdata(component);
struct rt712_sdca_dmic_kctrl_priv *p =
(struct rt712_sdca_dmic_kctrl_priv *)kcontrol->private_value;
int err, changed = 0, i;
for (i = 0; i < p->count; i++) {
if (rt712->fu1e_mixer_mute[i] != !ucontrol->value.integer.value[i])
changed = 1;
rt712->fu1e_mixer_mute[i] = !ucontrol->value.integer.value[i];
}
err = rt712_sdca_set_fu1e_capture_ctl(rt712);
if (err < 0)
return err;
return changed;
}
static int rt712_sdca_fu_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
struct rt712_sdca_dmic_kctrl_priv *p =
(struct rt712_sdca_dmic_kctrl_priv *)kcontrol->private_value;
if (p->max == 1)
uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
else
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = p->count;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = p->max;
return 0;
}
#define RT712_SDCA_PR_VALUE(xreg_base, xcount, xmax, xinvert) \
((unsigned long)&(struct rt712_sdca_dmic_kctrl_priv) \
{.reg_base = xreg_base, .count = xcount, .max = xmax, \
.invert = xinvert})
#define RT712_SDCA_FU_CTRL(xname, reg_base, xmax, xinvert, xcount) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
.info = rt712_sdca_fu_info, \
.get = rt712_sdca_dmic_fu1e_capture_get, \
.put = rt712_sdca_dmic_fu1e_capture_put, \
.private_value = RT712_SDCA_PR_VALUE(reg_base, xcount, xmax, xinvert)}
#define RT712_SDCA_EXT_TLV(xname, reg_base, xhandler_get,\
xhandler_put, xcount, xmax, tlv_array) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
SNDRV_CTL_ELEM_ACCESS_READWRITE, \
.tlv.p = (tlv_array), \
.info = rt712_sdca_fu_info, \
.get = xhandler_get, .put = xhandler_put, \
.private_value = RT712_SDCA_PR_VALUE(reg_base, xcount, xmax, 0) }
static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -1725, 75, 0);
static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
static const struct snd_kcontrol_new rt712_sdca_dmic_snd_controls[] = {
RT712_SDCA_FU_CTRL("FU1E Capture Switch",
SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT712_SDCA_ENT_USER_FU1E, RT712_SDCA_CTL_FU_MUTE, CH_01),
1, 1, 4),
RT712_SDCA_EXT_TLV("FU1E Capture Volume",
SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT712_SDCA_ENT_USER_FU1E, RT712_SDCA_CTL_FU_VOLUME, CH_01),
rt712_sdca_dmic_set_gain_get, rt712_sdca_dmic_set_gain_put, 4, 0x3f, in_vol_tlv),
RT712_SDCA_EXT_TLV("FU15 Boost Volume",
SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT712_SDCA_ENT_PLATFORM_FU15, RT712_SDCA_CTL_FU_CH_GAIN, CH_01),
rt712_sdca_dmic_set_gain_get, rt712_sdca_dmic_set_gain_put, 4, 3, mic_vol_tlv),
};
static int rt712_sdca_dmic_mux_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_dapm_kcontrol_component(kcontrol);
struct rt712_sdca_dmic_priv *rt712 = snd_soc_component_get_drvdata(component);
unsigned int val = 0, mask_sft;
if (strstr(ucontrol->id.name, "ADC 25 Mux"))
mask_sft = 8;
else if (strstr(ucontrol->id.name, "ADC 26 Mux"))
mask_sft = 4;
else
return -EINVAL;
rt712_sdca_dmic_index_read(rt712, RT712_VENDOR_HDA_CTL,
RT712_HDA_LEGACY_MUX_CTL0, &val);
ucontrol->value.enumerated.item[0] = (val >> mask_sft) & 0x7;
return 0;
}
static int rt712_sdca_dmic_mux_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_dapm_kcontrol_component(kcontrol);
struct snd_soc_dapm_context *dapm =
snd_soc_dapm_kcontrol_dapm(kcontrol);
struct rt712_sdca_dmic_priv *rt712 = snd_soc_component_get_drvdata(component);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int *item = ucontrol->value.enumerated.item;
unsigned int val, val2 = 0, change, mask_sft;
if (item[0] >= e->items)
return -EINVAL;
if (strstr(ucontrol->id.name, "ADC 25 Mux"))
mask_sft = 8;
else if (strstr(ucontrol->id.name, "ADC 26 Mux"))
mask_sft = 4;
else
return -EINVAL;
val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
rt712_sdca_dmic_index_read(rt712, RT712_VENDOR_HDA_CTL,
RT712_HDA_LEGACY_MUX_CTL0, &val2);
val2 = (0x7 << mask_sft) & val2;
if (val == val2)
change = 0;
else
change = 1;
if (change)
rt712_sdca_dmic_index_update_bits(rt712, RT712_VENDOR_HDA_CTL,
RT712_HDA_LEGACY_MUX_CTL0, 0x7 << mask_sft,
val << mask_sft);
snd_soc_dapm_mux_update_power(dapm, kcontrol,
item[0], e, NULL);
return change;
}
static const char * const adc_mux_text[] = {
"DMIC1",
"DMIC2",
};
static SOC_ENUM_SINGLE_DECL(
rt712_adc25_enum, SND_SOC_NOPM, 0, adc_mux_text);
static SOC_ENUM_SINGLE_DECL(
rt712_adc26_enum, SND_SOC_NOPM, 0, adc_mux_text);
static const struct snd_kcontrol_new rt712_sdca_dmic_adc25_mux =
SOC_DAPM_ENUM_EXT("ADC 25 Mux", rt712_adc25_enum,
rt712_sdca_dmic_mux_get, rt712_sdca_dmic_mux_put);
static const struct snd_kcontrol_new rt712_sdca_dmic_adc26_mux =
SOC_DAPM_ENUM_EXT("ADC 26 Mux", rt712_adc26_enum,
rt712_sdca_dmic_mux_get, rt712_sdca_dmic_mux_put);
static int rt712_sdca_dmic_fu1e_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt712_sdca_dmic_priv *rt712 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
rt712->fu1e_dapm_mute = false;
rt712_sdca_set_fu1e_capture_ctl(rt712);
break;
case SND_SOC_DAPM_PRE_PMD:
rt712->fu1e_dapm_mute = true;
rt712_sdca_set_fu1e_capture_ctl(rt712);
break;
}
return 0;
}
static int rt712_sdca_dmic_pde11_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt712_sdca_dmic_priv *rt712 = snd_soc_component_get_drvdata(component);
unsigned char ps0 = 0x0, ps3 = 0x3;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_write(rt712->regmap,
SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT712_SDCA_ENT_PDE11,
RT712_SDCA_CTL_REQ_POWER_STATE, 0),
ps0);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_write(rt712->regmap,
SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT712_SDCA_ENT_PDE11,
RT712_SDCA_CTL_REQ_POWER_STATE, 0),
ps3);
break;
}
return 0;
}
static const struct snd_soc_dapm_widget rt712_sdca_dmic_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("DMIC1"),
SND_SOC_DAPM_INPUT("DMIC2"),
SND_SOC_DAPM_SUPPLY("PDE 11", SND_SOC_NOPM, 0, 0,
rt712_sdca_dmic_pde11_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_ADC_E("FU 1E", NULL, SND_SOC_NOPM, 0, 0,
rt712_sdca_dmic_fu1e_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_MUX("ADC 25 Mux", SND_SOC_NOPM, 0, 0,
&rt712_sdca_dmic_adc25_mux),
SND_SOC_DAPM_MUX("ADC 26 Mux", SND_SOC_NOPM, 0, 0,
&rt712_sdca_dmic_adc26_mux),
SND_SOC_DAPM_AIF_OUT("DP2TX", "DP2 Capture", 0, SND_SOC_NOPM, 0, 0),
};
static const struct snd_soc_dapm_route rt712_sdca_dmic_audio_map[] = {
{"DP2TX", NULL, "FU 1E"},
{"FU 1E", NULL, "PDE 11"},
{"FU 1E", NULL, "ADC 25 Mux"},
{"FU 1E", NULL, "ADC 26 Mux"},
{"ADC 25 Mux", "DMIC1", "DMIC1"},
{"ADC 25 Mux", "DMIC2", "DMIC2"},
{"ADC 26 Mux", "DMIC1", "DMIC1"},
{"ADC 26 Mux", "DMIC2", "DMIC2"},
};
static int rt712_sdca_dmic_probe(struct snd_soc_component *component)
{
struct rt712_sdca_dmic_priv *rt712 = snd_soc_component_get_drvdata(component);
int ret;
rt712->component = component;
if (!rt712->first_hw_init)
return 0;
ret = pm_runtime_resume(component->dev);
if (ret < 0 && ret != -EACCES)
return ret;
return 0;
}
static const struct snd_soc_component_driver soc_sdca_dev_rt712_dmic = {
.probe = rt712_sdca_dmic_probe,
.controls = rt712_sdca_dmic_snd_controls,
.num_controls = ARRAY_SIZE(rt712_sdca_dmic_snd_controls),
.dapm_widgets = rt712_sdca_dmic_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt712_sdca_dmic_dapm_widgets),
.dapm_routes = rt712_sdca_dmic_audio_map,
.num_dapm_routes = ARRAY_SIZE(rt712_sdca_dmic_audio_map),
.endianness = 1,
};
static int rt712_sdca_dmic_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
int direction)
{
snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
return 0;
}
static void rt712_sdca_dmic_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
snd_soc_dai_set_dma_data(dai, substream, NULL);
}
static int rt712_sdca_dmic_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt712_sdca_dmic_priv *rt712 = snd_soc_component_get_drvdata(component);
struct sdw_stream_config stream_config;
struct sdw_port_config port_config;
struct sdw_stream_runtime *sdw_stream;
int retval, num_channels;
unsigned int sampling_rate;
dev_dbg(dai->dev, "%s %s", __func__, dai->name);
sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
if (!sdw_stream)
return -EINVAL;
if (!rt712->slave)
return -EINVAL;
stream_config.frame_rate = params_rate(params);
stream_config.ch_count = params_channels(params);
stream_config.bps = snd_pcm_format_width(params_format(params));
stream_config.direction = SDW_DATA_DIR_TX;
num_channels = params_channels(params);
port_config.ch_mask = GENMASK(num_channels - 1, 0);
port_config.num = 2;
retval = sdw_stream_add_slave(rt712->slave, &stream_config,
&port_config, 1, sdw_stream);
if (retval) {
dev_err(dai->dev, "Unable to configure port\n");
return retval;
}
if (params_channels(params) > 4) {
dev_err(component->dev, "Unsupported channels %d\n",
params_channels(params));
return -EINVAL;
}
/* sampling rate configuration */
switch (params_rate(params)) {
case 16000:
sampling_rate = RT712_SDCA_RATE_16000HZ;
break;
case 32000:
sampling_rate = RT712_SDCA_RATE_32000HZ;
break;
case 44100:
sampling_rate = RT712_SDCA_RATE_44100HZ;
break;
case 48000:
sampling_rate = RT712_SDCA_RATE_48000HZ;
break;
case 96000:
sampling_rate = RT712_SDCA_RATE_96000HZ;
break;
case 192000:
sampling_rate = RT712_SDCA_RATE_192000HZ;
break;
default:
dev_err(component->dev, "Rate %d is not supported\n",
params_rate(params));
return -EINVAL;
}
/* set sampling frequency */
regmap_write(rt712->regmap,
SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT712_SDCA_ENT_CS1F, RT712_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
sampling_rate);
regmap_write(rt712->regmap,
SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT712_SDCA_ENT_CS1C, RT712_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
sampling_rate);
return 0;
}
static int rt712_sdca_dmic_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt712_sdca_dmic_priv *rt712 = snd_soc_component_get_drvdata(component);
struct sdw_stream_runtime *sdw_stream =
snd_soc_dai_get_dma_data(dai, substream);
if (!rt712->slave)
return -EINVAL;
sdw_stream_remove_slave(rt712->slave, sdw_stream);
return 0;
}
#define RT712_STEREO_RATES (SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
#define RT712_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE)
static const struct snd_soc_dai_ops rt712_sdca_dmic_ops = {
.hw_params = rt712_sdca_dmic_hw_params,
.hw_free = rt712_sdca_dmic_hw_free,
.set_stream = rt712_sdca_dmic_set_sdw_stream,
.shutdown = rt712_sdca_dmic_shutdown,
};
static struct snd_soc_dai_driver rt712_sdca_dmic_dai[] = {
{
.name = "rt712-sdca-dmic-aif1",
.id = RT712_AIF1,
.capture = {
.stream_name = "DP2 Capture",
.channels_min = 1,
.channels_max = 4,
.rates = RT712_STEREO_RATES,
.formats = RT712_FORMATS,
},
.ops = &rt712_sdca_dmic_ops,
},
};
static int rt712_sdca_dmic_init(struct device *dev, struct regmap *regmap,
struct regmap *mbq_regmap, struct sdw_slave *slave)
{
struct rt712_sdca_dmic_priv *rt712;
int ret;
rt712 = devm_kzalloc(dev, sizeof(*rt712), GFP_KERNEL);
if (!rt712)
return -ENOMEM;
dev_set_drvdata(dev, rt712);
rt712->slave = slave;
rt712->regmap = regmap;
rt712->mbq_regmap = mbq_regmap;
regcache_cache_only(rt712->regmap, true);
regcache_cache_only(rt712->mbq_regmap, true);
/*
* Mark hw_init to false
* HW init will be performed when device reports present
*/
rt712->hw_init = false;
rt712->first_hw_init = false;
rt712->fu1e_dapm_mute = true;
rt712->fu1e_mixer_mute[0] = rt712->fu1e_mixer_mute[1] =
rt712->fu1e_mixer_mute[2] = rt712->fu1e_mixer_mute[3] = true;
ret = devm_snd_soc_register_component(dev,
&soc_sdca_dev_rt712_dmic,
rt712_sdca_dmic_dai,
ARRAY_SIZE(rt712_sdca_dmic_dai));
if (ret < 0)
return ret;
/* set autosuspend parameters */
pm_runtime_set_autosuspend_delay(dev, 3000);
pm_runtime_use_autosuspend(dev);
/* make sure the device does not suspend immediately */
pm_runtime_mark_last_busy(dev);
pm_runtime_enable(dev);
/* important note: the device is NOT tagged as 'active' and will remain
* 'suspended' until the hardware is enumerated/initialized. This is required
* to make sure the ASoC framework use of pm_runtime_get_sync() does not silently
* fail with -EACCESS because of race conditions between card creation and enumeration
*/
dev_dbg(dev, "%s\n", __func__);
return 0;
}
static int rt712_sdca_dmic_update_status(struct sdw_slave *slave,
enum sdw_slave_status status)
{
struct rt712_sdca_dmic_priv *rt712 = dev_get_drvdata(&slave->dev);
if (status == SDW_SLAVE_UNATTACHED)
rt712->hw_init = false;
/*
* Perform initialization only if slave status is present and
* hw_init flag is false
*/
if (rt712->hw_init || status != SDW_SLAVE_ATTACHED)
return 0;
/* perform I/O transfers required for Slave initialization */
return rt712_sdca_dmic_io_init(&slave->dev, slave);
}
static int rt712_sdca_dmic_read_prop(struct sdw_slave *slave)
{
struct sdw_slave_prop *prop = &slave->prop;
int nval, i;
u32 bit;
unsigned long addr;
struct sdw_dpn_prop *dpn;
prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
prop->paging_support = true;
/* first we need to allocate memory for set bits in port lists */
prop->source_ports = BIT(2); /* BITMAP: 00000100 */
prop->sink_ports = 0;
nval = hweight32(prop->source_ports);
prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
sizeof(*prop->src_dpn_prop), GFP_KERNEL);
if (!prop->src_dpn_prop)
return -ENOMEM;
i = 0;
dpn = prop->src_dpn_prop;
addr = prop->source_ports;
for_each_set_bit(bit, &addr, 32) {
dpn[i].num = bit;
dpn[i].type = SDW_DPN_FULL;
dpn[i].simple_ch_prep_sm = true;
dpn[i].ch_prep_timeout = 10;
i++;
}
/* set the timeout values */
prop->clk_stop_timeout = 200;
/* wake-up event */
prop->wake_capable = 1;
return 0;
}
static const struct sdw_device_id rt712_sdca_dmic_id[] = {
SDW_SLAVE_ENTRY_EXT(0x025d, 0x1712, 0x3, 0x1, 0),
SDW_SLAVE_ENTRY_EXT(0x025d, 0x1713, 0x3, 0x1, 0),
SDW_SLAVE_ENTRY_EXT(0x025d, 0x1716, 0x3, 0x1, 0),
SDW_SLAVE_ENTRY_EXT(0x025d, 0x1717, 0x3, 0x1, 0),
{},
};
MODULE_DEVICE_TABLE(sdw, rt712_sdca_dmic_id);
static int __maybe_unused rt712_sdca_dmic_dev_suspend(struct device *dev)
{
struct rt712_sdca_dmic_priv *rt712 = dev_get_drvdata(dev);
if (!rt712->hw_init)
return 0;
regcache_cache_only(rt712->regmap, true);
regcache_cache_only(rt712->mbq_regmap, true);
return 0;
}
static int __maybe_unused rt712_sdca_dmic_dev_system_suspend(struct device *dev)
{
struct rt712_sdca_dmic_priv *rt712_sdca = dev_get_drvdata(dev);
if (!rt712_sdca->hw_init)
return 0;
return rt712_sdca_dmic_dev_suspend(dev);
}
#define RT712_PROBE_TIMEOUT 5000
static int __maybe_unused rt712_sdca_dmic_dev_resume(struct device *dev)
{
struct sdw_slave *slave = dev_to_sdw_dev(dev);
struct rt712_sdca_dmic_priv *rt712 = dev_get_drvdata(dev);
unsigned long time;
if (!rt712->first_hw_init)
return 0;
if (!slave->unattach_request)
goto regmap_sync;
time = wait_for_completion_timeout(&slave->initialization_complete,
msecs_to_jiffies(RT712_PROBE_TIMEOUT));
if (!time) {
dev_err(&slave->dev, "Initialization not complete, timed out\n");
sdw_show_ping_status(slave->bus, true);
return -ETIMEDOUT;
}
regmap_sync:
slave->unattach_request = 0;
regcache_cache_only(rt712->regmap, false);
regcache_sync(rt712->regmap);
regcache_cache_only(rt712->mbq_regmap, false);
regcache_sync(rt712->mbq_regmap);
return 0;
}
static const struct dev_pm_ops rt712_sdca_dmic_pm = {
SET_SYSTEM_SLEEP_PM_OPS(rt712_sdca_dmic_dev_system_suspend, rt712_sdca_dmic_dev_resume)
SET_RUNTIME_PM_OPS(rt712_sdca_dmic_dev_suspend, rt712_sdca_dmic_dev_resume, NULL)
};
static struct sdw_slave_ops rt712_sdca_dmic_slave_ops = {
.read_prop = rt712_sdca_dmic_read_prop,
.update_status = rt712_sdca_dmic_update_status,
};
static int rt712_sdca_dmic_sdw_probe(struct sdw_slave *slave,
const struct sdw_device_id *id)
{
struct regmap *regmap, *mbq_regmap;
/* Regmap Initialization */
mbq_regmap = devm_regmap_init_sdw_mbq(slave, &rt712_sdca_dmic_mbq_regmap);
if (IS_ERR(mbq_regmap))
return PTR_ERR(mbq_regmap);
regmap = devm_regmap_init_sdw(slave, &rt712_sdca_dmic_regmap);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return rt712_sdca_dmic_init(&slave->dev, regmap, mbq_regmap, slave);
}
static int rt712_sdca_dmic_sdw_remove(struct sdw_slave *slave)
{
pm_runtime_disable(&slave->dev);
return 0;
}
static struct sdw_driver rt712_sdca_dmic_sdw_driver = {
.driver = {
.name = "rt712-sdca-dmic",
.owner = THIS_MODULE,
.pm = &rt712_sdca_dmic_pm,
},
.probe = rt712_sdca_dmic_sdw_probe,
.remove = rt712_sdca_dmic_sdw_remove,
.ops = &rt712_sdca_dmic_slave_ops,
.id_table = rt712_sdca_dmic_id,
};
module_sdw_driver(rt712_sdca_dmic_sdw_driver);
MODULE_DESCRIPTION("ASoC RT712 SDCA DMIC SDW driver");
MODULE_AUTHOR("Shuming Fan <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/rt712-sdca-dmic.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* cs42l73.c -- CS42L73 ALSA Soc Audio driver
*
* Copyright 2011 Cirrus Logic, Inc.
*
* Authors: Georgi Vlaev, Nucleus Systems Ltd, <[email protected]>
* Brian Austin, Cirrus Logic Inc, <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/of_gpio.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/cs42l73.h>
#include "cs42l73.h"
#include "cirrus_legacy.h"
struct sp_config {
u8 spc, mmcc, spfs;
u32 srate;
};
struct cs42l73_private {
struct cs42l73_platform_data pdata;
struct sp_config config[3];
struct regmap *regmap;
u32 sysclk;
u8 mclksel;
u32 mclk;
int shutdwn_delay;
};
static const struct reg_default cs42l73_reg_defaults[] = {
{ 6, 0xF1 }, /* r06 - Power Ctl 1 */
{ 7, 0xDF }, /* r07 - Power Ctl 2 */
{ 8, 0x3F }, /* r08 - Power Ctl 3 */
{ 9, 0x50 }, /* r09 - Charge Pump Freq */
{ 10, 0x53 }, /* r0A - Output Load MicBias Short Detect */
{ 11, 0x00 }, /* r0B - DMIC Master Clock Ctl */
{ 12, 0x00 }, /* r0C - Aux PCM Ctl */
{ 13, 0x15 }, /* r0D - Aux PCM Master Clock Ctl */
{ 14, 0x00 }, /* r0E - Audio PCM Ctl */
{ 15, 0x15 }, /* r0F - Audio PCM Master Clock Ctl */
{ 16, 0x00 }, /* r10 - Voice PCM Ctl */
{ 17, 0x15 }, /* r11 - Voice PCM Master Clock Ctl */
{ 18, 0x00 }, /* r12 - Voice/Aux Sample Rate */
{ 19, 0x06 }, /* r13 - Misc I/O Path Ctl */
{ 20, 0x00 }, /* r14 - ADC Input Path Ctl */
{ 21, 0x00 }, /* r15 - MICA Preamp, PGA Volume */
{ 22, 0x00 }, /* r16 - MICB Preamp, PGA Volume */
{ 23, 0x00 }, /* r17 - Input Path A Digital Volume */
{ 24, 0x00 }, /* r18 - Input Path B Digital Volume */
{ 25, 0x00 }, /* r19 - Playback Digital Ctl */
{ 26, 0x00 }, /* r1A - HP/LO Left Digital Volume */
{ 27, 0x00 }, /* r1B - HP/LO Right Digital Volume */
{ 28, 0x00 }, /* r1C - Speakerphone Digital Volume */
{ 29, 0x00 }, /* r1D - Ear/SPKLO Digital Volume */
{ 30, 0x00 }, /* r1E - HP Left Analog Volume */
{ 31, 0x00 }, /* r1F - HP Right Analog Volume */
{ 32, 0x00 }, /* r20 - LO Left Analog Volume */
{ 33, 0x00 }, /* r21 - LO Right Analog Volume */
{ 34, 0x00 }, /* r22 - Stereo Input Path Advisory Volume */
{ 35, 0x00 }, /* r23 - Aux PCM Input Advisory Volume */
{ 36, 0x00 }, /* r24 - Audio PCM Input Advisory Volume */
{ 37, 0x00 }, /* r25 - Voice PCM Input Advisory Volume */
{ 38, 0x00 }, /* r26 - Limiter Attack Rate HP/LO */
{ 39, 0x7F }, /* r27 - Limter Ctl, Release Rate HP/LO */
{ 40, 0x00 }, /* r28 - Limter Threshold HP/LO */
{ 41, 0x00 }, /* r29 - Limiter Attack Rate Speakerphone */
{ 42, 0x3F }, /* r2A - Limter Ctl, Release Rate Speakerphone */
{ 43, 0x00 }, /* r2B - Limter Threshold Speakerphone */
{ 44, 0x00 }, /* r2C - Limiter Attack Rate Ear/SPKLO */
{ 45, 0x3F }, /* r2D - Limter Ctl, Release Rate Ear/SPKLO */
{ 46, 0x00 }, /* r2E - Limter Threshold Ear/SPKLO */
{ 47, 0x00 }, /* r2F - ALC Enable, Attack Rate Left/Right */
{ 48, 0x3F }, /* r30 - ALC Release Rate Left/Right */
{ 49, 0x00 }, /* r31 - ALC Threshold Left/Right */
{ 50, 0x00 }, /* r32 - Noise Gate Ctl Left/Right */
{ 51, 0x00 }, /* r33 - ALC/NG Misc Ctl */
{ 52, 0x18 }, /* r34 - Mixer Ctl */
{ 53, 0x3F }, /* r35 - HP/LO Left Mixer Input Path Volume */
{ 54, 0x3F }, /* r36 - HP/LO Right Mixer Input Path Volume */
{ 55, 0x3F }, /* r37 - HP/LO Left Mixer Aux PCM Volume */
{ 56, 0x3F }, /* r38 - HP/LO Right Mixer Aux PCM Volume */
{ 57, 0x3F }, /* r39 - HP/LO Left Mixer Audio PCM Volume */
{ 58, 0x3F }, /* r3A - HP/LO Right Mixer Audio PCM Volume */
{ 59, 0x3F }, /* r3B - HP/LO Left Mixer Voice PCM Mono Volume */
{ 60, 0x3F }, /* r3C - HP/LO Right Mixer Voice PCM Mono Volume */
{ 61, 0x3F }, /* r3D - Aux PCM Left Mixer Input Path Volume */
{ 62, 0x3F }, /* r3E - Aux PCM Right Mixer Input Path Volume */
{ 63, 0x3F }, /* r3F - Aux PCM Left Mixer Volume */
{ 64, 0x3F }, /* r40 - Aux PCM Left Mixer Volume */
{ 65, 0x3F }, /* r41 - Aux PCM Left Mixer Audio PCM L Volume */
{ 66, 0x3F }, /* r42 - Aux PCM Right Mixer Audio PCM R Volume */
{ 67, 0x3F }, /* r43 - Aux PCM Left Mixer Voice PCM Volume */
{ 68, 0x3F }, /* r44 - Aux PCM Right Mixer Voice PCM Volume */
{ 69, 0x3F }, /* r45 - Audio PCM Left Input Path Volume */
{ 70, 0x3F }, /* r46 - Audio PCM Right Input Path Volume */
{ 71, 0x3F }, /* r47 - Audio PCM Left Mixer Aux PCM L Volume */
{ 72, 0x3F }, /* r48 - Audio PCM Right Mixer Aux PCM R Volume */
{ 73, 0x3F }, /* r49 - Audio PCM Left Mixer Volume */
{ 74, 0x3F }, /* r4A - Audio PCM Right Mixer Volume */
{ 75, 0x3F }, /* r4B - Audio PCM Left Mixer Voice PCM Volume */
{ 76, 0x3F }, /* r4C - Audio PCM Right Mixer Voice PCM Volume */
{ 77, 0x3F }, /* r4D - Voice PCM Left Input Path Volume */
{ 78, 0x3F }, /* r4E - Voice PCM Right Input Path Volume */
{ 79, 0x3F }, /* r4F - Voice PCM Left Mixer Aux PCM L Volume */
{ 80, 0x3F }, /* r50 - Voice PCM Right Mixer Aux PCM R Volume */
{ 81, 0x3F }, /* r51 - Voice PCM Left Mixer Audio PCM L Volume */
{ 82, 0x3F }, /* r52 - Voice PCM Right Mixer Audio PCM R Volume */
{ 83, 0x3F }, /* r53 - Voice PCM Left Mixer Voice PCM Volume */
{ 84, 0x3F }, /* r54 - Voice PCM Right Mixer Voice PCM Volume */
{ 85, 0xAA }, /* r55 - Mono Mixer Ctl */
{ 86, 0x3F }, /* r56 - SPK Mono Mixer Input Path Volume */
{ 87, 0x3F }, /* r57 - SPK Mono Mixer Aux PCM Mono/L/R Volume */
{ 88, 0x3F }, /* r58 - SPK Mono Mixer Audio PCM Mono/L/R Volume */
{ 89, 0x3F }, /* r59 - SPK Mono Mixer Voice PCM Mono Volume */
{ 90, 0x3F }, /* r5A - SPKLO Mono Mixer Input Path Mono Volume */
{ 91, 0x3F }, /* r5B - SPKLO Mono Mixer Aux Mono/L/R Volume */
{ 92, 0x3F }, /* r5C - SPKLO Mono Mixer Audio Mono/L/R Volume */
{ 93, 0x3F }, /* r5D - SPKLO Mono Mixer Voice Mono Volume */
{ 94, 0x00 }, /* r5E - Interrupt Mask 1 */
{ 95, 0x00 }, /* r5F - Interrupt Mask 2 */
};
static bool cs42l73_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS42L73_IS1:
case CS42L73_IS2:
return true;
default:
return false;
}
}
static bool cs42l73_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS42L73_DEVID_AB ... CS42L73_DEVID_E:
case CS42L73_REVID ... CS42L73_IM2:
return true;
default:
return false;
}
}
static const DECLARE_TLV_DB_RANGE(hpaloa_tlv,
0, 13, TLV_DB_SCALE_ITEM(-7600, 200, 0),
14, 75, TLV_DB_SCALE_ITEM(-4900, 100, 0)
);
static DECLARE_TLV_DB_SCALE(adc_boost_tlv, 0, 2500, 0);
static DECLARE_TLV_DB_SCALE(hl_tlv, -10200, 50, 0);
static DECLARE_TLV_DB_SCALE(ipd_tlv, -9600, 100, 0);
static DECLARE_TLV_DB_SCALE(micpga_tlv, -600, 50, 0);
static const DECLARE_TLV_DB_RANGE(limiter_tlv,
0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0),
3, 7, TLV_DB_SCALE_ITEM(-1200, 300, 0)
);
static const DECLARE_TLV_DB_SCALE(attn_tlv, -6300, 100, 1);
static const char * const cs42l73_pgaa_text[] = { "Line A", "Mic 1" };
static const char * const cs42l73_pgab_text[] = { "Line B", "Mic 2" };
static SOC_ENUM_SINGLE_DECL(pgaa_enum,
CS42L73_ADCIPC, 3,
cs42l73_pgaa_text);
static SOC_ENUM_SINGLE_DECL(pgab_enum,
CS42L73_ADCIPC, 7,
cs42l73_pgab_text);
static const struct snd_kcontrol_new pgaa_mux =
SOC_DAPM_ENUM("Left Analog Input Capture Mux", pgaa_enum);
static const struct snd_kcontrol_new pgab_mux =
SOC_DAPM_ENUM("Right Analog Input Capture Mux", pgab_enum);
static const struct snd_kcontrol_new input_left_mixer[] = {
SOC_DAPM_SINGLE("ADC Left Input", CS42L73_PWRCTL1,
5, 1, 1),
SOC_DAPM_SINGLE("DMIC Left Input", CS42L73_PWRCTL1,
4, 1, 1),
};
static const struct snd_kcontrol_new input_right_mixer[] = {
SOC_DAPM_SINGLE("ADC Right Input", CS42L73_PWRCTL1,
7, 1, 1),
SOC_DAPM_SINGLE("DMIC Right Input", CS42L73_PWRCTL1,
6, 1, 1),
};
static const char * const cs42l73_ng_delay_text[] = {
"50ms", "100ms", "150ms", "200ms" };
static SOC_ENUM_SINGLE_DECL(ng_delay_enum,
CS42L73_NGCAB, 0,
cs42l73_ng_delay_text);
static const char * const cs42l73_mono_mix_texts[] = {
"Left", "Right", "Mono Mix"};
static const unsigned int cs42l73_mono_mix_values[] = { 0, 1, 2 };
static const struct soc_enum spk_asp_enum =
SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 6, 3,
ARRAY_SIZE(cs42l73_mono_mix_texts),
cs42l73_mono_mix_texts,
cs42l73_mono_mix_values);
static const struct snd_kcontrol_new spk_asp_mixer =
SOC_DAPM_ENUM("Route", spk_asp_enum);
static const struct soc_enum spk_xsp_enum =
SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 4, 3,
ARRAY_SIZE(cs42l73_mono_mix_texts),
cs42l73_mono_mix_texts,
cs42l73_mono_mix_values);
static const struct snd_kcontrol_new spk_xsp_mixer =
SOC_DAPM_ENUM("Route", spk_xsp_enum);
static const struct soc_enum esl_asp_enum =
SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 2, 3,
ARRAY_SIZE(cs42l73_mono_mix_texts),
cs42l73_mono_mix_texts,
cs42l73_mono_mix_values);
static const struct snd_kcontrol_new esl_asp_mixer =
SOC_DAPM_ENUM("Route", esl_asp_enum);
static const struct soc_enum esl_xsp_enum =
SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 0, 3,
ARRAY_SIZE(cs42l73_mono_mix_texts),
cs42l73_mono_mix_texts,
cs42l73_mono_mix_values);
static const struct snd_kcontrol_new esl_xsp_mixer =
SOC_DAPM_ENUM("Route", esl_xsp_enum);
static const char * const cs42l73_ip_swap_text[] = {
"Stereo", "Mono A", "Mono B", "Swap A-B"};
static SOC_ENUM_SINGLE_DECL(ip_swap_enum,
CS42L73_MIOPC, 6,
cs42l73_ip_swap_text);
static const char * const cs42l73_spo_mixer_text[] = {"Mono", "Stereo"};
static SOC_ENUM_SINGLE_DECL(vsp_output_mux_enum,
CS42L73_MIXERCTL, 5,
cs42l73_spo_mixer_text);
static SOC_ENUM_SINGLE_DECL(xsp_output_mux_enum,
CS42L73_MIXERCTL, 4,
cs42l73_spo_mixer_text);
static const struct snd_kcontrol_new hp_amp_ctl =
SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 0, 1, 1);
static const struct snd_kcontrol_new lo_amp_ctl =
SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 1, 1, 1);
static const struct snd_kcontrol_new spk_amp_ctl =
SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 2, 1, 1);
static const struct snd_kcontrol_new spklo_amp_ctl =
SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 4, 1, 1);
static const struct snd_kcontrol_new ear_amp_ctl =
SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 3, 1, 1);
static const struct snd_kcontrol_new cs42l73_snd_controls[] = {
SOC_DOUBLE_R_SX_TLV("Headphone Analog Playback Volume",
CS42L73_HPAAVOL, CS42L73_HPBAVOL, 0,
0x41, 0x4B, hpaloa_tlv),
SOC_DOUBLE_R_SX_TLV("LineOut Analog Playback Volume", CS42L73_LOAAVOL,
CS42L73_LOBAVOL, 0, 0x41, 0x4B, hpaloa_tlv),
SOC_DOUBLE_R_SX_TLV("Input PGA Analog Volume", CS42L73_MICAPREPGAAVOL,
CS42L73_MICBPREPGABVOL, 0, 0x34,
0x24, micpga_tlv),
SOC_DOUBLE_R("MIC Preamp Switch", CS42L73_MICAPREPGAAVOL,
CS42L73_MICBPREPGABVOL, 6, 1, 1),
SOC_DOUBLE_R_SX_TLV("Input Path Digital Volume", CS42L73_IPADVOL,
CS42L73_IPBDVOL, 0, 0xA0, 0x6C, ipd_tlv),
SOC_DOUBLE_R_SX_TLV("HL Digital Playback Volume",
CS42L73_HLADVOL, CS42L73_HLBDVOL,
0, 0x34, 0xE4, hl_tlv),
SOC_SINGLE_TLV("ADC A Boost Volume",
CS42L73_ADCIPC, 2, 0x01, 1, adc_boost_tlv),
SOC_SINGLE_TLV("ADC B Boost Volume",
CS42L73_ADCIPC, 6, 0x01, 1, adc_boost_tlv),
SOC_SINGLE_SX_TLV("Speakerphone Digital Volume",
CS42L73_SPKDVOL, 0, 0x34, 0xE4, hl_tlv),
SOC_SINGLE_SX_TLV("Ear Speaker Digital Volume",
CS42L73_ESLDVOL, 0, 0x34, 0xE4, hl_tlv),
SOC_DOUBLE_R("Headphone Analog Playback Switch", CS42L73_HPAAVOL,
CS42L73_HPBAVOL, 7, 1, 1),
SOC_DOUBLE_R("LineOut Analog Playback Switch", CS42L73_LOAAVOL,
CS42L73_LOBAVOL, 7, 1, 1),
SOC_DOUBLE("Input Path Digital Switch", CS42L73_ADCIPC, 0, 4, 1, 1),
SOC_DOUBLE("HL Digital Playback Switch", CS42L73_PBDC, 0,
1, 1, 1),
SOC_SINGLE("Speakerphone Digital Playback Switch", CS42L73_PBDC, 2, 1,
1),
SOC_SINGLE("Ear Speaker Digital Playback Switch", CS42L73_PBDC, 3, 1,
1),
SOC_SINGLE("PGA Soft-Ramp Switch", CS42L73_MIOPC, 3, 1, 0),
SOC_SINGLE("Analog Zero Cross Switch", CS42L73_MIOPC, 2, 1, 0),
SOC_SINGLE("Digital Soft-Ramp Switch", CS42L73_MIOPC, 1, 1, 0),
SOC_SINGLE("Analog Output Soft-Ramp Switch", CS42L73_MIOPC, 0, 1, 0),
SOC_DOUBLE("ADC Signal Polarity Switch", CS42L73_ADCIPC, 1, 5, 1,
0),
SOC_SINGLE("HL Limiter Attack Rate", CS42L73_LIMARATEHL, 0, 0x3F,
0),
SOC_SINGLE("HL Limiter Release Rate", CS42L73_LIMRRATEHL, 0,
0x3F, 0),
SOC_SINGLE("HL Limiter Switch", CS42L73_LIMRRATEHL, 7, 1, 0),
SOC_SINGLE("HL Limiter All Channels Switch", CS42L73_LIMRRATEHL, 6, 1,
0),
SOC_SINGLE_TLV("HL Limiter Max Threshold Volume", CS42L73_LMAXHL, 5, 7,
1, limiter_tlv),
SOC_SINGLE_TLV("HL Limiter Cushion Volume", CS42L73_LMAXHL, 2, 7, 1,
limiter_tlv),
SOC_SINGLE("SPK Limiter Attack Rate Volume", CS42L73_LIMARATESPK, 0,
0x3F, 0),
SOC_SINGLE("SPK Limiter Release Rate Volume", CS42L73_LIMRRATESPK, 0,
0x3F, 0),
SOC_SINGLE("SPK Limiter Switch", CS42L73_LIMRRATESPK, 7, 1, 0),
SOC_SINGLE("SPK Limiter All Channels Switch", CS42L73_LIMRRATESPK,
6, 1, 0),
SOC_SINGLE_TLV("SPK Limiter Max Threshold Volume", CS42L73_LMAXSPK, 5,
7, 1, limiter_tlv),
SOC_SINGLE_TLV("SPK Limiter Cushion Volume", CS42L73_LMAXSPK, 2, 7, 1,
limiter_tlv),
SOC_SINGLE("ESL Limiter Attack Rate Volume", CS42L73_LIMARATEESL, 0,
0x3F, 0),
SOC_SINGLE("ESL Limiter Release Rate Volume", CS42L73_LIMRRATEESL, 0,
0x3F, 0),
SOC_SINGLE("ESL Limiter Switch", CS42L73_LIMRRATEESL, 7, 1, 0),
SOC_SINGLE_TLV("ESL Limiter Max Threshold Volume", CS42L73_LMAXESL, 5,
7, 1, limiter_tlv),
SOC_SINGLE_TLV("ESL Limiter Cushion Volume", CS42L73_LMAXESL, 2, 7, 1,
limiter_tlv),
SOC_SINGLE("ALC Attack Rate Volume", CS42L73_ALCARATE, 0, 0x3F, 0),
SOC_SINGLE("ALC Release Rate Volume", CS42L73_ALCRRATE, 0, 0x3F, 0),
SOC_DOUBLE("ALC Switch", CS42L73_ALCARATE, 6, 7, 1, 0),
SOC_SINGLE_TLV("ALC Max Threshold Volume", CS42L73_ALCMINMAX, 5, 7, 0,
limiter_tlv),
SOC_SINGLE_TLV("ALC Min Threshold Volume", CS42L73_ALCMINMAX, 2, 7, 0,
limiter_tlv),
SOC_DOUBLE("NG Enable Switch", CS42L73_NGCAB, 6, 7, 1, 0),
SOC_SINGLE("NG Boost Switch", CS42L73_NGCAB, 5, 1, 0),
/*
NG Threshold depends on NG_BOOTSAB, which selects
between two threshold scales in decibels.
Set linear values for now ..
*/
SOC_SINGLE("NG Threshold", CS42L73_NGCAB, 2, 7, 0),
SOC_ENUM("NG Delay", ng_delay_enum),
SOC_DOUBLE_R_TLV("XSP-IP Volume",
CS42L73_XSPAIPAA, CS42L73_XSPBIPBA, 0, 0x3F, 1,
attn_tlv),
SOC_DOUBLE_R_TLV("XSP-XSP Volume",
CS42L73_XSPAXSPAA, CS42L73_XSPBXSPBA, 0, 0x3F, 1,
attn_tlv),
SOC_DOUBLE_R_TLV("XSP-ASP Volume",
CS42L73_XSPAASPAA, CS42L73_XSPAASPBA, 0, 0x3F, 1,
attn_tlv),
SOC_DOUBLE_R_TLV("XSP-VSP Volume",
CS42L73_XSPAVSPMA, CS42L73_XSPBVSPMA, 0, 0x3F, 1,
attn_tlv),
SOC_DOUBLE_R_TLV("ASP-IP Volume",
CS42L73_ASPAIPAA, CS42L73_ASPBIPBA, 0, 0x3F, 1,
attn_tlv),
SOC_DOUBLE_R_TLV("ASP-XSP Volume",
CS42L73_ASPAXSPAA, CS42L73_ASPBXSPBA, 0, 0x3F, 1,
attn_tlv),
SOC_DOUBLE_R_TLV("ASP-ASP Volume",
CS42L73_ASPAASPAA, CS42L73_ASPBASPBA, 0, 0x3F, 1,
attn_tlv),
SOC_DOUBLE_R_TLV("ASP-VSP Volume",
CS42L73_ASPAVSPMA, CS42L73_ASPBVSPMA, 0, 0x3F, 1,
attn_tlv),
SOC_DOUBLE_R_TLV("VSP-IP Volume",
CS42L73_VSPAIPAA, CS42L73_VSPBIPBA, 0, 0x3F, 1,
attn_tlv),
SOC_DOUBLE_R_TLV("VSP-XSP Volume",
CS42L73_VSPAXSPAA, CS42L73_VSPBXSPBA, 0, 0x3F, 1,
attn_tlv),
SOC_DOUBLE_R_TLV("VSP-ASP Volume",
CS42L73_VSPAASPAA, CS42L73_VSPBASPBA, 0, 0x3F, 1,
attn_tlv),
SOC_DOUBLE_R_TLV("VSP-VSP Volume",
CS42L73_VSPAVSPMA, CS42L73_VSPBVSPMA, 0, 0x3F, 1,
attn_tlv),
SOC_DOUBLE_R_TLV("HL-IP Volume",
CS42L73_HLAIPAA, CS42L73_HLBIPBA, 0, 0x3F, 1,
attn_tlv),
SOC_DOUBLE_R_TLV("HL-XSP Volume",
CS42L73_HLAXSPAA, CS42L73_HLBXSPBA, 0, 0x3F, 1,
attn_tlv),
SOC_DOUBLE_R_TLV("HL-ASP Volume",
CS42L73_HLAASPAA, CS42L73_HLBASPBA, 0, 0x3F, 1,
attn_tlv),
SOC_DOUBLE_R_TLV("HL-VSP Volume",
CS42L73_HLAVSPMA, CS42L73_HLBVSPMA, 0, 0x3F, 1,
attn_tlv),
SOC_SINGLE_TLV("SPK-IP Mono Volume",
CS42L73_SPKMIPMA, 0, 0x3F, 1, attn_tlv),
SOC_SINGLE_TLV("SPK-XSP Mono Volume",
CS42L73_SPKMXSPA, 0, 0x3F, 1, attn_tlv),
SOC_SINGLE_TLV("SPK-ASP Mono Volume",
CS42L73_SPKMASPA, 0, 0x3F, 1, attn_tlv),
SOC_SINGLE_TLV("SPK-VSP Mono Volume",
CS42L73_SPKMVSPMA, 0, 0x3F, 1, attn_tlv),
SOC_SINGLE_TLV("ESL-IP Mono Volume",
CS42L73_ESLMIPMA, 0, 0x3F, 1, attn_tlv),
SOC_SINGLE_TLV("ESL-XSP Mono Volume",
CS42L73_ESLMXSPA, 0, 0x3F, 1, attn_tlv),
SOC_SINGLE_TLV("ESL-ASP Mono Volume",
CS42L73_ESLMASPA, 0, 0x3F, 1, attn_tlv),
SOC_SINGLE_TLV("ESL-VSP Mono Volume",
CS42L73_ESLMVSPMA, 0, 0x3F, 1, attn_tlv),
SOC_ENUM("IP Digital Swap/Mono Select", ip_swap_enum),
SOC_ENUM("VSPOUT Mono/Stereo Select", vsp_output_mux_enum),
SOC_ENUM("XSPOUT Mono/Stereo Select", xsp_output_mux_enum),
};
static int cs42l73_spklo_spk_amp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct cs42l73_private *priv = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMD:
/* 150 ms delay between setting PDN and MCLKDIS */
priv->shutdwn_delay = 150;
break;
default:
pr_err("Invalid event = 0x%x\n", event);
}
return 0;
}
static int cs42l73_ear_amp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct cs42l73_private *priv = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMD:
/* 50 ms delay between setting PDN and MCLKDIS */
if (priv->shutdwn_delay < 50)
priv->shutdwn_delay = 50;
break;
default:
pr_err("Invalid event = 0x%x\n", event);
}
return 0;
}
static int cs42l73_hp_amp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct cs42l73_private *priv = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMD:
/* 30 ms delay between setting PDN and MCLKDIS */
if (priv->shutdwn_delay < 30)
priv->shutdwn_delay = 30;
break;
default:
pr_err("Invalid event = 0x%x\n", event);
}
return 0;
}
static const struct snd_soc_dapm_widget cs42l73_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("DMICA"),
SND_SOC_DAPM_INPUT("DMICB"),
SND_SOC_DAPM_INPUT("LINEINA"),
SND_SOC_DAPM_INPUT("LINEINB"),
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_SUPPLY("MIC1 Bias", CS42L73_PWRCTL2, 6, 1, NULL, 0),
SND_SOC_DAPM_INPUT("MIC2"),
SND_SOC_DAPM_SUPPLY("MIC2 Bias", CS42L73_PWRCTL2, 7, 1, NULL, 0),
SND_SOC_DAPM_AIF_OUT("XSPOUTL", NULL, 0,
CS42L73_PWRCTL2, 1, 1),
SND_SOC_DAPM_AIF_OUT("XSPOUTR", NULL, 0,
CS42L73_PWRCTL2, 1, 1),
SND_SOC_DAPM_AIF_OUT("ASPOUTL", NULL, 0,
CS42L73_PWRCTL2, 3, 1),
SND_SOC_DAPM_AIF_OUT("ASPOUTR", NULL, 0,
CS42L73_PWRCTL2, 3, 1),
SND_SOC_DAPM_AIF_OUT("VSPINOUT", NULL, 0,
CS42L73_PWRCTL2, 4, 1),
SND_SOC_DAPM_PGA("PGA Left", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("PGA Right", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX("PGA Left Mux", SND_SOC_NOPM, 0, 0, &pgaa_mux),
SND_SOC_DAPM_MUX("PGA Right Mux", SND_SOC_NOPM, 0, 0, &pgab_mux),
SND_SOC_DAPM_ADC("ADC Left", NULL, CS42L73_PWRCTL1, 7, 1),
SND_SOC_DAPM_ADC("ADC Right", NULL, CS42L73_PWRCTL1, 5, 1),
SND_SOC_DAPM_ADC("DMIC Left", NULL, CS42L73_PWRCTL1, 6, 1),
SND_SOC_DAPM_ADC("DMIC Right", NULL, CS42L73_PWRCTL1, 4, 1),
SND_SOC_DAPM_MIXER_NAMED_CTL("Input Left Capture", SND_SOC_NOPM,
0, 0, input_left_mixer,
ARRAY_SIZE(input_left_mixer)),
SND_SOC_DAPM_MIXER_NAMED_CTL("Input Right Capture", SND_SOC_NOPM,
0, 0, input_right_mixer,
ARRAY_SIZE(input_right_mixer)),
SND_SOC_DAPM_MIXER("ASPL Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("ASPR Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("XSPL Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("XSPR Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("VSP Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_AIF_IN("XSPINL", NULL, 0,
CS42L73_PWRCTL2, 0, 1),
SND_SOC_DAPM_AIF_IN("XSPINR", NULL, 0,
CS42L73_PWRCTL2, 0, 1),
SND_SOC_DAPM_AIF_IN("XSPINM", NULL, 0,
CS42L73_PWRCTL2, 0, 1),
SND_SOC_DAPM_AIF_IN("ASPINL", NULL, 0,
CS42L73_PWRCTL2, 2, 1),
SND_SOC_DAPM_AIF_IN("ASPINR", NULL, 0,
CS42L73_PWRCTL2, 2, 1),
SND_SOC_DAPM_AIF_IN("ASPINM", NULL, 0,
CS42L73_PWRCTL2, 2, 1),
SND_SOC_DAPM_AIF_IN("VSPINOUT", NULL, 0,
CS42L73_PWRCTL2, 4, 1),
SND_SOC_DAPM_MIXER("HL Left Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("HL Right Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SPK Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("ESL Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX("ESL-XSP Mux", SND_SOC_NOPM,
0, 0, &esl_xsp_mixer),
SND_SOC_DAPM_MUX("ESL-ASP Mux", SND_SOC_NOPM,
0, 0, &esl_asp_mixer),
SND_SOC_DAPM_MUX("SPK-ASP Mux", SND_SOC_NOPM,
0, 0, &spk_asp_mixer),
SND_SOC_DAPM_MUX("SPK-XSP Mux", SND_SOC_NOPM,
0, 0, &spk_xsp_mixer),
SND_SOC_DAPM_PGA("HL Left DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("HL Right DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("SPK DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("ESL DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SWITCH_E("HP Amp", CS42L73_PWRCTL3, 0, 1,
&hp_amp_ctl, cs42l73_hp_amp_event,
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SWITCH("LO Amp", CS42L73_PWRCTL3, 1, 1,
&lo_amp_ctl),
SND_SOC_DAPM_SWITCH_E("SPK Amp", CS42L73_PWRCTL3, 2, 1,
&spk_amp_ctl, cs42l73_spklo_spk_amp_event,
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SWITCH_E("EAR Amp", CS42L73_PWRCTL3, 3, 1,
&ear_amp_ctl, cs42l73_ear_amp_event,
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SWITCH_E("SPKLO Amp", CS42L73_PWRCTL3, 4, 1,
&spklo_amp_ctl, cs42l73_spklo_spk_amp_event,
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_OUTPUT("HPOUTA"),
SND_SOC_DAPM_OUTPUT("HPOUTB"),
SND_SOC_DAPM_OUTPUT("LINEOUTA"),
SND_SOC_DAPM_OUTPUT("LINEOUTB"),
SND_SOC_DAPM_OUTPUT("EAROUT"),
SND_SOC_DAPM_OUTPUT("SPKOUT"),
SND_SOC_DAPM_OUTPUT("SPKLINEOUT"),
};
static const struct snd_soc_dapm_route cs42l73_audio_map[] = {
/* SPKLO EARSPK Paths */
{"EAROUT", NULL, "EAR Amp"},
{"SPKLINEOUT", NULL, "SPKLO Amp"},
{"EAR Amp", "Switch", "ESL DAC"},
{"SPKLO Amp", "Switch", "ESL DAC"},
{"ESL DAC", "ESL-ASP Mono Volume", "ESL Mixer"},
{"ESL DAC", "ESL-XSP Mono Volume", "ESL Mixer"},
{"ESL DAC", "ESL-VSP Mono Volume", "VSPINOUT"},
/* Loopback */
{"ESL DAC", "ESL-IP Mono Volume", "Input Left Capture"},
{"ESL DAC", "ESL-IP Mono Volume", "Input Right Capture"},
{"ESL Mixer", NULL, "ESL-ASP Mux"},
{"ESL Mixer", NULL, "ESL-XSP Mux"},
{"ESL-ASP Mux", "Left", "ASPINL"},
{"ESL-ASP Mux", "Right", "ASPINR"},
{"ESL-ASP Mux", "Mono Mix", "ASPINM"},
{"ESL-XSP Mux", "Left", "XSPINL"},
{"ESL-XSP Mux", "Right", "XSPINR"},
{"ESL-XSP Mux", "Mono Mix", "XSPINM"},
/* Speakerphone Paths */
{"SPKOUT", NULL, "SPK Amp"},
{"SPK Amp", "Switch", "SPK DAC"},
{"SPK DAC", "SPK-ASP Mono Volume", "SPK Mixer"},
{"SPK DAC", "SPK-XSP Mono Volume", "SPK Mixer"},
{"SPK DAC", "SPK-VSP Mono Volume", "VSPINOUT"},
/* Loopback */
{"SPK DAC", "SPK-IP Mono Volume", "Input Left Capture"},
{"SPK DAC", "SPK-IP Mono Volume", "Input Right Capture"},
{"SPK Mixer", NULL, "SPK-ASP Mux"},
{"SPK Mixer", NULL, "SPK-XSP Mux"},
{"SPK-ASP Mux", "Left", "ASPINL"},
{"SPK-ASP Mux", "Mono Mix", "ASPINM"},
{"SPK-ASP Mux", "Right", "ASPINR"},
{"SPK-XSP Mux", "Left", "XSPINL"},
{"SPK-XSP Mux", "Mono Mix", "XSPINM"},
{"SPK-XSP Mux", "Right", "XSPINR"},
/* HP LineOUT Paths */
{"HPOUTA", NULL, "HP Amp"},
{"HPOUTB", NULL, "HP Amp"},
{"LINEOUTA", NULL, "LO Amp"},
{"LINEOUTB", NULL, "LO Amp"},
{"HP Amp", "Switch", "HL Left DAC"},
{"HP Amp", "Switch", "HL Right DAC"},
{"LO Amp", "Switch", "HL Left DAC"},
{"LO Amp", "Switch", "HL Right DAC"},
{"HL Left DAC", "HL-XSP Volume", "HL Left Mixer"},
{"HL Right DAC", "HL-XSP Volume", "HL Right Mixer"},
{"HL Left DAC", "HL-ASP Volume", "HL Left Mixer"},
{"HL Right DAC", "HL-ASP Volume", "HL Right Mixer"},
{"HL Left DAC", "HL-VSP Volume", "HL Left Mixer"},
{"HL Right DAC", "HL-VSP Volume", "HL Right Mixer"},
/* Loopback */
{"HL Left DAC", "HL-IP Volume", "HL Left Mixer"},
{"HL Right DAC", "HL-IP Volume", "HL Right Mixer"},
{"HL Left Mixer", NULL, "Input Left Capture"},
{"HL Right Mixer", NULL, "Input Right Capture"},
{"HL Left Mixer", NULL, "ASPINL"},
{"HL Right Mixer", NULL, "ASPINR"},
{"HL Left Mixer", NULL, "XSPINL"},
{"HL Right Mixer", NULL, "XSPINR"},
{"HL Left Mixer", NULL, "VSPINOUT"},
{"HL Right Mixer", NULL, "VSPINOUT"},
{"ASPINL", NULL, "ASP Playback"},
{"ASPINM", NULL, "ASP Playback"},
{"ASPINR", NULL, "ASP Playback"},
{"XSPINL", NULL, "XSP Playback"},
{"XSPINM", NULL, "XSP Playback"},
{"XSPINR", NULL, "XSP Playback"},
{"VSPINOUT", NULL, "VSP Playback"},
/* Capture Paths */
{"MIC1", NULL, "MIC1 Bias"},
{"PGA Left Mux", "Mic 1", "MIC1"},
{"MIC2", NULL, "MIC2 Bias"},
{"PGA Right Mux", "Mic 2", "MIC2"},
{"PGA Left Mux", "Line A", "LINEINA"},
{"PGA Right Mux", "Line B", "LINEINB"},
{"PGA Left", NULL, "PGA Left Mux"},
{"PGA Right", NULL, "PGA Right Mux"},
{"ADC Left", NULL, "PGA Left"},
{"ADC Right", NULL, "PGA Right"},
{"DMIC Left", NULL, "DMICA"},
{"DMIC Right", NULL, "DMICB"},
{"Input Left Capture", "ADC Left Input", "ADC Left"},
{"Input Right Capture", "ADC Right Input", "ADC Right"},
{"Input Left Capture", "DMIC Left Input", "DMIC Left"},
{"Input Right Capture", "DMIC Right Input", "DMIC Right"},
/* Audio Capture */
{"ASPL Output Mixer", NULL, "Input Left Capture"},
{"ASPR Output Mixer", NULL, "Input Right Capture"},
{"ASPOUTL", "ASP-IP Volume", "ASPL Output Mixer"},
{"ASPOUTR", "ASP-IP Volume", "ASPR Output Mixer"},
/* Auxillary Capture */
{"XSPL Output Mixer", NULL, "Input Left Capture"},
{"XSPR Output Mixer", NULL, "Input Right Capture"},
{"XSPOUTL", "XSP-IP Volume", "XSPL Output Mixer"},
{"XSPOUTR", "XSP-IP Volume", "XSPR Output Mixer"},
{"XSPOUTL", NULL, "XSPL Output Mixer"},
{"XSPOUTR", NULL, "XSPR Output Mixer"},
/* Voice Capture */
{"VSP Output Mixer", NULL, "Input Left Capture"},
{"VSP Output Mixer", NULL, "Input Right Capture"},
{"VSPINOUT", "VSP-IP Volume", "VSP Output Mixer"},
{"VSPINOUT", NULL, "VSP Output Mixer"},
{"ASP Capture", NULL, "ASPOUTL"},
{"ASP Capture", NULL, "ASPOUTR"},
{"XSP Capture", NULL, "XSPOUTL"},
{"XSP Capture", NULL, "XSPOUTR"},
{"VSP Capture", NULL, "VSPINOUT"},
};
struct cs42l73_mclk_div {
u32 mclk;
u32 srate;
u8 mmcc;
};
static const struct cs42l73_mclk_div cs42l73_mclk_coeffs[] = {
/* MCLK, Sample Rate, xMMCC[5:0] */
{5644800, 11025, 0x30},
{5644800, 22050, 0x20},
{5644800, 44100, 0x10},
{6000000, 8000, 0x39},
{6000000, 11025, 0x33},
{6000000, 12000, 0x31},
{6000000, 16000, 0x29},
{6000000, 22050, 0x23},
{6000000, 24000, 0x21},
{6000000, 32000, 0x19},
{6000000, 44100, 0x13},
{6000000, 48000, 0x11},
{6144000, 8000, 0x38},
{6144000, 12000, 0x30},
{6144000, 16000, 0x28},
{6144000, 24000, 0x20},
{6144000, 32000, 0x18},
{6144000, 48000, 0x10},
{6500000, 8000, 0x3C},
{6500000, 11025, 0x35},
{6500000, 12000, 0x34},
{6500000, 16000, 0x2C},
{6500000, 22050, 0x25},
{6500000, 24000, 0x24},
{6500000, 32000, 0x1C},
{6500000, 44100, 0x15},
{6500000, 48000, 0x14},
{6400000, 8000, 0x3E},
{6400000, 11025, 0x37},
{6400000, 12000, 0x36},
{6400000, 16000, 0x2E},
{6400000, 22050, 0x27},
{6400000, 24000, 0x26},
{6400000, 32000, 0x1E},
{6400000, 44100, 0x17},
{6400000, 48000, 0x16},
};
struct cs42l73_mclkx_div {
u32 mclkx;
u8 ratio;
u8 mclkdiv;
};
static const struct cs42l73_mclkx_div cs42l73_mclkx_coeffs[] = {
{5644800, 1, 0}, /* 5644800 */
{6000000, 1, 0}, /* 6000000 */
{6144000, 1, 0}, /* 6144000 */
{11289600, 2, 2}, /* 5644800 */
{12288000, 2, 2}, /* 6144000 */
{12000000, 2, 2}, /* 6000000 */
{13000000, 2, 2}, /* 6500000 */
{19200000, 3, 3}, /* 6400000 */
{24000000, 4, 4}, /* 6000000 */
{26000000, 4, 4}, /* 6500000 */
{38400000, 6, 5} /* 6400000 */
};
static int cs42l73_get_mclkx_coeff(int mclkx)
{
int i;
for (i = 0; i < ARRAY_SIZE(cs42l73_mclkx_coeffs); i++) {
if (cs42l73_mclkx_coeffs[i].mclkx == mclkx)
return i;
}
return -EINVAL;
}
static int cs42l73_get_mclk_coeff(int mclk, int srate)
{
int i;
for (i = 0; i < ARRAY_SIZE(cs42l73_mclk_coeffs); i++) {
if (cs42l73_mclk_coeffs[i].mclk == mclk &&
cs42l73_mclk_coeffs[i].srate == srate)
return i;
}
return -EINVAL;
}
static int cs42l73_set_mclk(struct snd_soc_dai *dai, unsigned int freq)
{
struct snd_soc_component *component = dai->component;
struct cs42l73_private *priv = snd_soc_component_get_drvdata(component);
int mclkx_coeff;
u32 mclk = 0;
u8 dmmcc = 0;
/* MCLKX -> MCLK */
mclkx_coeff = cs42l73_get_mclkx_coeff(freq);
if (mclkx_coeff < 0)
return mclkx_coeff;
mclk = cs42l73_mclkx_coeffs[mclkx_coeff].mclkx /
cs42l73_mclkx_coeffs[mclkx_coeff].ratio;
dev_dbg(component->dev, "MCLK%u %u <-> internal MCLK %u\n",
priv->mclksel + 1, cs42l73_mclkx_coeffs[mclkx_coeff].mclkx,
mclk);
dmmcc = (priv->mclksel << 4) |
(cs42l73_mclkx_coeffs[mclkx_coeff].mclkdiv << 1);
snd_soc_component_write(component, CS42L73_DMMCC, dmmcc);
priv->sysclk = mclkx_coeff;
priv->mclk = mclk;
return 0;
}
static int cs42l73_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct cs42l73_private *priv = snd_soc_component_get_drvdata(component);
switch (clk_id) {
case CS42L73_CLKID_MCLK1:
break;
case CS42L73_CLKID_MCLK2:
break;
default:
return -EINVAL;
}
if ((cs42l73_set_mclk(dai, freq)) < 0) {
dev_err(component->dev, "Unable to set MCLK for dai %s\n",
dai->name);
return -EINVAL;
}
priv->mclksel = clk_id;
return 0;
}
static int cs42l73_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct cs42l73_private *priv = snd_soc_component_get_drvdata(component);
u8 id = codec_dai->id;
unsigned int inv, format;
u8 spc, mmcc;
spc = snd_soc_component_read(component, CS42L73_SPC(id));
mmcc = snd_soc_component_read(component, CS42L73_MMCC(id));
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
mmcc |= CS42L73_MS_MASTER;
break;
case SND_SOC_DAIFMT_CBS_CFS:
mmcc &= ~CS42L73_MS_MASTER;
break;
default:
return -EINVAL;
}
format = (fmt & SND_SOC_DAIFMT_FORMAT_MASK);
inv = (fmt & SND_SOC_DAIFMT_INV_MASK);
switch (format) {
case SND_SOC_DAIFMT_I2S:
spc &= ~CS42L73_SPDIF_PCM;
break;
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B:
if (mmcc & CS42L73_MS_MASTER) {
dev_err(component->dev,
"PCM format in slave mode only\n");
return -EINVAL;
}
if (id == CS42L73_ASP) {
dev_err(component->dev,
"PCM format is not supported on ASP port\n");
return -EINVAL;
}
spc |= CS42L73_SPDIF_PCM;
break;
default:
return -EINVAL;
}
if (spc & CS42L73_SPDIF_PCM) {
/* Clear PCM mode, clear PCM_BIT_ORDER bit for MSB->LSB */
spc &= ~(CS42L73_PCM_MODE_MASK | CS42L73_PCM_BIT_ORDER);
switch (format) {
case SND_SOC_DAIFMT_DSP_B:
if (inv == SND_SOC_DAIFMT_IB_IF)
spc |= CS42L73_PCM_MODE0;
if (inv == SND_SOC_DAIFMT_IB_NF)
spc |= CS42L73_PCM_MODE1;
break;
case SND_SOC_DAIFMT_DSP_A:
if (inv == SND_SOC_DAIFMT_IB_IF)
spc |= CS42L73_PCM_MODE1;
break;
default:
return -EINVAL;
}
}
priv->config[id].spc = spc;
priv->config[id].mmcc = mmcc;
return 0;
}
static const unsigned int cs42l73_asrc_rates[] = {
8000, 11025, 12000, 16000, 22050,
24000, 32000, 44100, 48000
};
static unsigned int cs42l73_get_xspfs_coeff(u32 rate)
{
int i;
for (i = 0; i < ARRAY_SIZE(cs42l73_asrc_rates); i++) {
if (cs42l73_asrc_rates[i] == rate)
return i + 1;
}
return 0; /* 0 = Don't know */
}
static void cs42l73_update_asrc(struct snd_soc_component *component, int id, int srate)
{
u8 spfs = 0;
if (srate > 0)
spfs = cs42l73_get_xspfs_coeff(srate);
switch (id) {
case CS42L73_XSP:
snd_soc_component_update_bits(component, CS42L73_VXSPFS, 0x0f, spfs);
break;
case CS42L73_ASP:
snd_soc_component_update_bits(component, CS42L73_ASPC, 0x3c, spfs << 2);
break;
case CS42L73_VSP:
snd_soc_component_update_bits(component, CS42L73_VXSPFS, 0xf0, spfs << 4);
break;
default:
break;
}
}
static int cs42l73_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct cs42l73_private *priv = snd_soc_component_get_drvdata(component);
int id = dai->id;
int mclk_coeff;
int srate = params_rate(params);
if (priv->config[id].mmcc & CS42L73_MS_MASTER) {
/* CS42L73 Master */
/* MCLK -> srate */
mclk_coeff =
cs42l73_get_mclk_coeff(priv->mclk, srate);
if (mclk_coeff < 0)
return -EINVAL;
dev_dbg(component->dev,
"DAI[%d]: MCLK %u, srate %u, MMCC[5:0] = %x\n",
id, priv->mclk, srate,
cs42l73_mclk_coeffs[mclk_coeff].mmcc);
priv->config[id].mmcc &= 0xC0;
priv->config[id].mmcc |= cs42l73_mclk_coeffs[mclk_coeff].mmcc;
priv->config[id].spc &= 0xFC;
/* Use SCLK=64*Fs if internal MCLK >= 6.4MHz */
if (priv->mclk >= 6400000)
priv->config[id].spc |= CS42L73_MCK_SCLK_64FS;
else
priv->config[id].spc |= CS42L73_MCK_SCLK_MCLK;
} else {
/* CS42L73 Slave */
priv->config[id].spc &= 0xFC;
priv->config[id].spc |= CS42L73_MCK_SCLK_64FS;
}
/* Update ASRCs */
priv->config[id].srate = srate;
snd_soc_component_write(component, CS42L73_SPC(id), priv->config[id].spc);
snd_soc_component_write(component, CS42L73_MMCC(id), priv->config[id].mmcc);
cs42l73_update_asrc(component, id, srate);
return 0;
}
static int cs42l73_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct cs42l73_private *cs42l73 = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_ON:
snd_soc_component_update_bits(component, CS42L73_DMMCC, CS42L73_MCLKDIS, 0);
snd_soc_component_update_bits(component, CS42L73_PWRCTL1, CS42L73_PDN, 0);
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
regcache_cache_only(cs42l73->regmap, false);
regcache_sync(cs42l73->regmap);
}
snd_soc_component_update_bits(component, CS42L73_PWRCTL1, CS42L73_PDN, 1);
break;
case SND_SOC_BIAS_OFF:
snd_soc_component_update_bits(component, CS42L73_PWRCTL1, CS42L73_PDN, 1);
if (cs42l73->shutdwn_delay > 0) {
mdelay(cs42l73->shutdwn_delay);
cs42l73->shutdwn_delay = 0;
} else {
mdelay(15); /* Min amount of time requred to power
* down.
*/
}
snd_soc_component_update_bits(component, CS42L73_DMMCC, CS42L73_MCLKDIS, 1);
break;
}
return 0;
}
static int cs42l73_set_tristate(struct snd_soc_dai *dai, int tristate)
{
struct snd_soc_component *component = dai->component;
int id = dai->id;
return snd_soc_component_update_bits(component, CS42L73_SPC(id), CS42L73_SP_3ST,
tristate << 7);
}
static const struct snd_pcm_hw_constraint_list constraints_12_24 = {
.count = ARRAY_SIZE(cs42l73_asrc_rates),
.list = cs42l73_asrc_rates,
};
static int cs42l73_pcm_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&constraints_12_24);
return 0;
}
#define CS42L73_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE)
static const struct snd_soc_dai_ops cs42l73_ops = {
.startup = cs42l73_pcm_startup,
.hw_params = cs42l73_pcm_hw_params,
.set_fmt = cs42l73_set_dai_fmt,
.set_sysclk = cs42l73_set_sysclk,
.set_tristate = cs42l73_set_tristate,
};
static struct snd_soc_dai_driver cs42l73_dai[] = {
{
.name = "cs42l73-xsp",
.id = CS42L73_XSP,
.playback = {
.stream_name = "XSP Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = CS42L73_FORMATS,
},
.capture = {
.stream_name = "XSP Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = CS42L73_FORMATS,
},
.ops = &cs42l73_ops,
.symmetric_rate = 1,
},
{
.name = "cs42l73-asp",
.id = CS42L73_ASP,
.playback = {
.stream_name = "ASP Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = CS42L73_FORMATS,
},
.capture = {
.stream_name = "ASP Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = CS42L73_FORMATS,
},
.ops = &cs42l73_ops,
.symmetric_rate = 1,
},
{
.name = "cs42l73-vsp",
.id = CS42L73_VSP,
.playback = {
.stream_name = "VSP Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = CS42L73_FORMATS,
},
.capture = {
.stream_name = "VSP Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = CS42L73_FORMATS,
},
.ops = &cs42l73_ops,
.symmetric_rate = 1,
}
};
static int cs42l73_probe(struct snd_soc_component *component)
{
struct cs42l73_private *cs42l73 = snd_soc_component_get_drvdata(component);
/* Set Charge Pump Frequency */
if (cs42l73->pdata.chgfreq)
snd_soc_component_update_bits(component, CS42L73_CPFCHC,
CS42L73_CHARGEPUMP_MASK,
cs42l73->pdata.chgfreq << 4);
/* MCLK1 as master clk */
cs42l73->mclksel = CS42L73_CLKID_MCLK1;
cs42l73->mclk = 0;
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_cs42l73 = {
.probe = cs42l73_probe,
.set_bias_level = cs42l73_set_bias_level,
.controls = cs42l73_snd_controls,
.num_controls = ARRAY_SIZE(cs42l73_snd_controls),
.dapm_widgets = cs42l73_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(cs42l73_dapm_widgets),
.dapm_routes = cs42l73_audio_map,
.num_dapm_routes = ARRAY_SIZE(cs42l73_audio_map),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config cs42l73_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = CS42L73_MAX_REGISTER,
.reg_defaults = cs42l73_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(cs42l73_reg_defaults),
.volatile_reg = cs42l73_volatile_register,
.readable_reg = cs42l73_readable_register,
.cache_type = REGCACHE_MAPLE,
.use_single_read = true,
.use_single_write = true,
};
static int cs42l73_i2c_probe(struct i2c_client *i2c_client)
{
struct cs42l73_private *cs42l73;
struct cs42l73_platform_data *pdata = dev_get_platdata(&i2c_client->dev);
int ret, devid;
unsigned int reg;
u32 val32;
cs42l73 = devm_kzalloc(&i2c_client->dev, sizeof(*cs42l73), GFP_KERNEL);
if (!cs42l73)
return -ENOMEM;
cs42l73->regmap = devm_regmap_init_i2c(i2c_client, &cs42l73_regmap);
if (IS_ERR(cs42l73->regmap)) {
ret = PTR_ERR(cs42l73->regmap);
dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
return ret;
}
if (pdata) {
cs42l73->pdata = *pdata;
} else {
pdata = devm_kzalloc(&i2c_client->dev, sizeof(*pdata),
GFP_KERNEL);
if (!pdata)
return -ENOMEM;
if (i2c_client->dev.of_node) {
if (of_property_read_u32(i2c_client->dev.of_node,
"chgfreq", &val32) >= 0)
pdata->chgfreq = val32;
}
pdata->reset_gpio = of_get_named_gpio(i2c_client->dev.of_node,
"reset-gpio", 0);
cs42l73->pdata = *pdata;
}
i2c_set_clientdata(i2c_client, cs42l73);
if (cs42l73->pdata.reset_gpio) {
ret = devm_gpio_request_one(&i2c_client->dev,
cs42l73->pdata.reset_gpio,
GPIOF_OUT_INIT_HIGH,
"CS42L73 /RST");
if (ret < 0) {
dev_err(&i2c_client->dev, "Failed to request /RST %d: %d\n",
cs42l73->pdata.reset_gpio, ret);
return ret;
}
gpio_set_value_cansleep(cs42l73->pdata.reset_gpio, 0);
gpio_set_value_cansleep(cs42l73->pdata.reset_gpio, 1);
}
/* initialize codec */
devid = cirrus_read_device_id(cs42l73->regmap, CS42L73_DEVID_AB);
if (devid < 0) {
ret = devid;
dev_err(&i2c_client->dev, "Failed to read device ID: %d\n", ret);
goto err_reset;
}
if (devid != CS42L73_DEVID) {
ret = -ENODEV;
dev_err(&i2c_client->dev,
"CS42L73 Device ID (%X). Expected %X\n",
devid, CS42L73_DEVID);
goto err_reset;
}
ret = regmap_read(cs42l73->regmap, CS42L73_REVID, ®);
if (ret < 0) {
dev_err(&i2c_client->dev, "Get Revision ID failed\n");
goto err_reset;
}
dev_info(&i2c_client->dev,
"Cirrus Logic CS42L73, Revision: %02X\n", reg & 0xFF);
ret = devm_snd_soc_register_component(&i2c_client->dev,
&soc_component_dev_cs42l73, cs42l73_dai,
ARRAY_SIZE(cs42l73_dai));
if (ret < 0)
goto err_reset;
return 0;
err_reset:
gpio_set_value_cansleep(cs42l73->pdata.reset_gpio, 0);
return ret;
}
static const struct of_device_id cs42l73_of_match[] = {
{ .compatible = "cirrus,cs42l73", },
{},
};
MODULE_DEVICE_TABLE(of, cs42l73_of_match);
static const struct i2c_device_id cs42l73_id[] = {
{"cs42l73", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, cs42l73_id);
static struct i2c_driver cs42l73_i2c_driver = {
.driver = {
.name = "cs42l73",
.of_match_table = cs42l73_of_match,
},
.id_table = cs42l73_id,
.probe = cs42l73_i2c_probe,
};
module_i2c_driver(cs42l73_i2c_driver);
MODULE_DESCRIPTION("ASoC CS42L73 driver");
MODULE_AUTHOR("Georgi Vlaev, Nucleus Systems Ltd, <[email protected]>");
MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cs42l73.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ALSA SoC TLV320AIC23 codec driver
*
* Author: Arun KS, <[email protected]>
* Copyright: (C) 2008 Mistral Solutions Pvt Ltd.,
*
* Based on sound/soc/codecs/wm8731.c by Richard Purdie
*
* Notes:
* The AIC23 is a driver for a low power stereo audio
* codec tlv320aic23
*
* The machine layer should disable unsupported inputs/outputs by
* snd_soc_dapm_disable_pin(codec, "LHPOUT"), etc.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <sound/initval.h>
#include "tlv320aic23.h"
/*
* AIC23 register cache
*/
static const struct reg_default tlv320aic23_reg[] = {
{ 0, 0x0097 },
{ 1, 0x0097 },
{ 2, 0x00F9 },
{ 3, 0x00F9 },
{ 4, 0x001A },
{ 5, 0x0004 },
{ 6, 0x0007 },
{ 7, 0x0001 },
{ 8, 0x0020 },
{ 9, 0x0000 },
};
const struct regmap_config tlv320aic23_regmap = {
.reg_bits = 7,
.val_bits = 9,
.max_register = TLV320AIC23_RESET,
.reg_defaults = tlv320aic23_reg,
.num_reg_defaults = ARRAY_SIZE(tlv320aic23_reg),
.cache_type = REGCACHE_RBTREE,
};
EXPORT_SYMBOL(tlv320aic23_regmap);
static const char *rec_src_text[] = { "Line", "Mic" };
static const char *deemph_text[] = {"None", "32Khz", "44.1Khz", "48Khz"};
static SOC_ENUM_SINGLE_DECL(rec_src_enum,
TLV320AIC23_ANLG, 2, rec_src_text);
static const struct snd_kcontrol_new tlv320aic23_rec_src_mux_controls =
SOC_DAPM_ENUM("Input Select", rec_src_enum);
static SOC_ENUM_SINGLE_DECL(tlv320aic23_deemph,
TLV320AIC23_DIGT, 1, deemph_text);
static const DECLARE_TLV_DB_SCALE(out_gain_tlv, -12100, 100, 0);
static const DECLARE_TLV_DB_SCALE(input_gain_tlv, -1725, 75, 0);
static const DECLARE_TLV_DB_SCALE(sidetone_vol_tlv, -1800, 300, 0);
static int snd_soc_tlv320aic23_put_volsw(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
u16 val, reg;
val = (ucontrol->value.integer.value[0] & 0x07);
/* linear conversion to userspace
* 000 = -6db
* 001 = -9db
* 010 = -12db
* 011 = -18db (Min)
* 100 = 0db (Max)
*/
val = (val >= 4) ? 4 : (3 - val);
reg = snd_soc_component_read(component, TLV320AIC23_ANLG) & (~0x1C0);
snd_soc_component_write(component, TLV320AIC23_ANLG, reg | (val << 6));
return 0;
}
static int snd_soc_tlv320aic23_get_volsw(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
u16 val;
val = snd_soc_component_read(component, TLV320AIC23_ANLG) & (0x1C0);
val = val >> 6;
val = (val >= 4) ? 4 : (3 - val);
ucontrol->value.integer.value[0] = val;
return 0;
}
static const struct snd_kcontrol_new tlv320aic23_snd_controls[] = {
SOC_DOUBLE_R_TLV("Digital Playback Volume", TLV320AIC23_LCHNVOL,
TLV320AIC23_RCHNVOL, 0, 127, 0, out_gain_tlv),
SOC_SINGLE("Digital Playback Switch", TLV320AIC23_DIGT, 3, 1, 1),
SOC_DOUBLE_R("Line Input Switch", TLV320AIC23_LINVOL,
TLV320AIC23_RINVOL, 7, 1, 0),
SOC_DOUBLE_R_TLV("Line Input Volume", TLV320AIC23_LINVOL,
TLV320AIC23_RINVOL, 0, 31, 0, input_gain_tlv),
SOC_SINGLE("Mic Input Switch", TLV320AIC23_ANLG, 1, 1, 1),
SOC_SINGLE("Mic Booster Switch", TLV320AIC23_ANLG, 0, 1, 0),
SOC_SINGLE_EXT_TLV("Sidetone Volume", TLV320AIC23_ANLG, 6, 4, 0,
snd_soc_tlv320aic23_get_volsw,
snd_soc_tlv320aic23_put_volsw, sidetone_vol_tlv),
SOC_ENUM("Playback De-emphasis", tlv320aic23_deemph),
};
/* PGA Mixer controls for Line and Mic switch */
static const struct snd_kcontrol_new tlv320aic23_output_mixer_controls[] = {
SOC_DAPM_SINGLE("Line Bypass Switch", TLV320AIC23_ANLG, 3, 1, 0),
SOC_DAPM_SINGLE("Mic Sidetone Switch", TLV320AIC23_ANLG, 5, 1, 0),
SOC_DAPM_SINGLE("Playback Switch", TLV320AIC23_ANLG, 4, 1, 0),
};
static const struct snd_soc_dapm_widget tlv320aic23_dapm_widgets[] = {
SND_SOC_DAPM_DAC("DAC", "Playback", TLV320AIC23_PWR, 3, 1),
SND_SOC_DAPM_ADC("ADC", "Capture", TLV320AIC23_PWR, 2, 1),
SND_SOC_DAPM_MUX("Capture Source", SND_SOC_NOPM, 0, 0,
&tlv320aic23_rec_src_mux_controls),
SND_SOC_DAPM_MIXER("Output Mixer", TLV320AIC23_PWR, 4, 1,
&tlv320aic23_output_mixer_controls[0],
ARRAY_SIZE(tlv320aic23_output_mixer_controls)),
SND_SOC_DAPM_PGA("Line Input", TLV320AIC23_PWR, 0, 1, NULL, 0),
SND_SOC_DAPM_PGA("Mic Input", TLV320AIC23_PWR, 1, 1, NULL, 0),
SND_SOC_DAPM_OUTPUT("LHPOUT"),
SND_SOC_DAPM_OUTPUT("RHPOUT"),
SND_SOC_DAPM_OUTPUT("LOUT"),
SND_SOC_DAPM_OUTPUT("ROUT"),
SND_SOC_DAPM_INPUT("LLINEIN"),
SND_SOC_DAPM_INPUT("RLINEIN"),
SND_SOC_DAPM_INPUT("MICIN"),
};
static const struct snd_soc_dapm_route tlv320aic23_intercon[] = {
/* Output Mixer */
{"Output Mixer", "Line Bypass Switch", "Line Input"},
{"Output Mixer", "Playback Switch", "DAC"},
{"Output Mixer", "Mic Sidetone Switch", "Mic Input"},
/* Outputs */
{"RHPOUT", NULL, "Output Mixer"},
{"LHPOUT", NULL, "Output Mixer"},
{"LOUT", NULL, "Output Mixer"},
{"ROUT", NULL, "Output Mixer"},
/* Inputs */
{"Line Input", NULL, "LLINEIN"},
{"Line Input", NULL, "RLINEIN"},
{"Mic Input", NULL, "MICIN"},
/* input mux */
{"Capture Source", "Line", "Line Input"},
{"Capture Source", "Mic", "Mic Input"},
{"ADC", NULL, "Capture Source"},
};
/* AIC23 driver data */
struct aic23 {
struct regmap *regmap;
int mclk;
int requested_adc;
int requested_dac;
};
/*
* Common Crystals used
* 11.2896 Mhz /128 = *88.2k /192 = 58.8k
* 12.0000 Mhz /125 = *96k /136 = 88.235K
* 12.2880 Mhz /128 = *96k /192 = 64k
* 16.9344 Mhz /128 = 132.3k /192 = *88.2k
* 18.4320 Mhz /128 = 144k /192 = *96k
*/
/*
* Normal BOSR 0-256/2 = 128, 1-384/2 = 192
* USB BOSR 0-250/2 = 125, 1-272/2 = 136
*/
static const int bosr_usb_divisor_table[] = {
128, 125, 192, 136
};
#define LOWER_GROUP ((1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<6) | (1<<7))
#define UPPER_GROUP ((1<<8) | (1<<9) | (1<<10) | (1<<11) | (1<<15))
static const unsigned short sr_valid_mask[] = {
LOWER_GROUP|UPPER_GROUP, /* Normal, bosr - 0*/
LOWER_GROUP, /* Usb, bosr - 0*/
LOWER_GROUP|UPPER_GROUP, /* Normal, bosr - 1*/
UPPER_GROUP, /* Usb, bosr - 1*/
};
/*
* Every divisor is a factor of 11*12
*/
#define SR_MULT (11*12)
#define A(x) (SR_MULT/x)
static const unsigned char sr_adc_mult_table[] = {
A(2), A(2), A(12), A(12), 0, 0, A(3), A(1),
A(2), A(2), A(11), A(11), 0, 0, 0, A(1)
};
static const unsigned char sr_dac_mult_table[] = {
A(2), A(12), A(2), A(12), 0, 0, A(3), A(1),
A(2), A(11), A(2), A(11), 0, 0, 0, A(1)
};
static unsigned get_score(int adc, int adc_l, int adc_h, int need_adc,
int dac, int dac_l, int dac_h, int need_dac)
{
if ((adc >= adc_l) && (adc <= adc_h) &&
(dac >= dac_l) && (dac <= dac_h)) {
int diff_adc = need_adc - adc;
int diff_dac = need_dac - dac;
return abs(diff_adc) + abs(diff_dac);
}
return UINT_MAX;
}
static int find_rate(int mclk, u32 need_adc, u32 need_dac)
{
int i, j;
int best_i = -1;
int best_j = -1;
int best_div = 0;
unsigned best_score = UINT_MAX;
int adc_l, adc_h, dac_l, dac_h;
need_adc *= SR_MULT;
need_dac *= SR_MULT;
/*
* rates given are +/- 1/32
*/
adc_l = need_adc - (need_adc >> 5);
adc_h = need_adc + (need_adc >> 5);
dac_l = need_dac - (need_dac >> 5);
dac_h = need_dac + (need_dac >> 5);
for (i = 0; i < ARRAY_SIZE(bosr_usb_divisor_table); i++) {
int base = mclk / bosr_usb_divisor_table[i];
int mask = sr_valid_mask[i];
for (j = 0; j < ARRAY_SIZE(sr_adc_mult_table);
j++, mask >>= 1) {
int adc;
int dac;
int score;
if ((mask & 1) == 0)
continue;
adc = base * sr_adc_mult_table[j];
dac = base * sr_dac_mult_table[j];
score = get_score(adc, adc_l, adc_h, need_adc,
dac, dac_l, dac_h, need_dac);
if (best_score > score) {
best_score = score;
best_i = i;
best_j = j;
best_div = 0;
}
score = get_score((adc >> 1), adc_l, adc_h, need_adc,
(dac >> 1), dac_l, dac_h, need_dac);
/* prefer to have a /2 */
if ((score != UINT_MAX) && (best_score >= score)) {
best_score = score;
best_i = i;
best_j = j;
best_div = 1;
}
}
}
return (best_j << 2) | best_i | (best_div << TLV320AIC23_CLKIN_SHIFT);
}
#ifdef DEBUG
static void get_current_sample_rates(struct snd_soc_component *component, int mclk,
u32 *sample_rate_adc, u32 *sample_rate_dac)
{
int src = snd_soc_component_read(component, TLV320AIC23_SRATE);
int sr = (src >> 2) & 0x0f;
int val = (mclk / bosr_usb_divisor_table[src & 3]);
int adc = (val * sr_adc_mult_table[sr]) / SR_MULT;
int dac = (val * sr_dac_mult_table[sr]) / SR_MULT;
if (src & TLV320AIC23_CLKIN_HALF) {
adc >>= 1;
dac >>= 1;
}
*sample_rate_adc = adc;
*sample_rate_dac = dac;
}
#endif
static int set_sample_rate_control(struct snd_soc_component *component, int mclk,
u32 sample_rate_adc, u32 sample_rate_dac)
{
/* Search for the right sample rate */
int data = find_rate(mclk, sample_rate_adc, sample_rate_dac);
if (data < 0) {
printk(KERN_ERR "%s:Invalid rate %u,%u requested\n",
__func__, sample_rate_adc, sample_rate_dac);
return -EINVAL;
}
snd_soc_component_write(component, TLV320AIC23_SRATE, data);
#ifdef DEBUG
{
u32 adc, dac;
get_current_sample_rates(component, mclk, &adc, &dac);
printk(KERN_DEBUG "actual samplerate = %u,%u reg=%x\n",
adc, dac, data);
}
#endif
return 0;
}
static int tlv320aic23_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
u16 iface_reg;
int ret;
struct aic23 *aic23 = snd_soc_component_get_drvdata(component);
u32 sample_rate_adc = aic23->requested_adc;
u32 sample_rate_dac = aic23->requested_dac;
u32 sample_rate = params_rate(params);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
aic23->requested_dac = sample_rate_dac = sample_rate;
if (!sample_rate_adc)
sample_rate_adc = sample_rate;
} else {
aic23->requested_adc = sample_rate_adc = sample_rate;
if (!sample_rate_dac)
sample_rate_dac = sample_rate;
}
ret = set_sample_rate_control(component, aic23->mclk, sample_rate_adc,
sample_rate_dac);
if (ret < 0)
return ret;
iface_reg = snd_soc_component_read(component, TLV320AIC23_DIGT_FMT) & ~(0x03 << 2);
switch (params_width(params)) {
case 16:
break;
case 20:
iface_reg |= (0x01 << 2);
break;
case 24:
iface_reg |= (0x02 << 2);
break;
case 32:
iface_reg |= (0x03 << 2);
break;
}
snd_soc_component_write(component, TLV320AIC23_DIGT_FMT, iface_reg);
return 0;
}
static int tlv320aic23_pcm_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
/* set active */
snd_soc_component_write(component, TLV320AIC23_ACTIVE, 0x0001);
return 0;
}
static void tlv320aic23_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct aic23 *aic23 = snd_soc_component_get_drvdata(component);
/* deactivate */
if (!snd_soc_component_active(component)) {
udelay(50);
snd_soc_component_write(component, TLV320AIC23_ACTIVE, 0x0);
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
aic23->requested_dac = 0;
else
aic23->requested_adc = 0;
}
static int tlv320aic23_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
u16 reg;
reg = snd_soc_component_read(component, TLV320AIC23_DIGT);
if (mute)
reg |= TLV320AIC23_DACM_MUTE;
else
reg &= ~TLV320AIC23_DACM_MUTE;
snd_soc_component_write(component, TLV320AIC23_DIGT, reg);
return 0;
}
static int tlv320aic23_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
u16 iface_reg;
iface_reg = snd_soc_component_read(component, TLV320AIC23_DIGT_FMT) & (~0x03);
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
iface_reg |= TLV320AIC23_MS_MASTER;
break;
case SND_SOC_DAIFMT_CBC_CFC:
iface_reg &= ~TLV320AIC23_MS_MASTER;
break;
default:
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface_reg |= TLV320AIC23_FOR_I2S;
break;
case SND_SOC_DAIFMT_DSP_A:
iface_reg |= TLV320AIC23_LRP_ON;
fallthrough;
case SND_SOC_DAIFMT_DSP_B:
iface_reg |= TLV320AIC23_FOR_DSP;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
iface_reg |= TLV320AIC23_FOR_LJUST;
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, TLV320AIC23_DIGT_FMT, iface_reg);
return 0;
}
static int tlv320aic23_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct aic23 *aic23 = snd_soc_dai_get_drvdata(codec_dai);
aic23->mclk = freq;
return 0;
}
static int tlv320aic23_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
u16 reg = snd_soc_component_read(component, TLV320AIC23_PWR) & 0x17f;
switch (level) {
case SND_SOC_BIAS_ON:
/* vref/mid, osc on, dac unmute */
reg &= ~(TLV320AIC23_DEVICE_PWR_OFF | TLV320AIC23_OSC_OFF | \
TLV320AIC23_DAC_OFF);
snd_soc_component_write(component, TLV320AIC23_PWR, reg);
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
/* everything off except vref/vmid, */
snd_soc_component_write(component, TLV320AIC23_PWR,
reg | TLV320AIC23_CLK_OFF);
break;
case SND_SOC_BIAS_OFF:
/* everything off, dac mute, inactive */
snd_soc_component_write(component, TLV320AIC23_ACTIVE, 0x0);
snd_soc_component_write(component, TLV320AIC23_PWR, 0x1ff);
break;
}
return 0;
}
#define AIC23_RATES SNDRV_PCM_RATE_8000_96000
#define AIC23_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops tlv320aic23_dai_ops = {
.prepare = tlv320aic23_pcm_prepare,
.hw_params = tlv320aic23_hw_params,
.shutdown = tlv320aic23_shutdown,
.mute_stream = tlv320aic23_mute,
.set_fmt = tlv320aic23_set_dai_fmt,
.set_sysclk = tlv320aic23_set_dai_sysclk,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver tlv320aic23_dai = {
.name = "tlv320aic23-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = AIC23_RATES,
.formats = AIC23_FORMATS,},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = AIC23_RATES,
.formats = AIC23_FORMATS,},
.ops = &tlv320aic23_dai_ops,
};
static int tlv320aic23_resume(struct snd_soc_component *component)
{
struct aic23 *aic23 = snd_soc_component_get_drvdata(component);
regcache_mark_dirty(aic23->regmap);
regcache_sync(aic23->regmap);
return 0;
}
static int tlv320aic23_component_probe(struct snd_soc_component *component)
{
/* Reset codec */
snd_soc_component_write(component, TLV320AIC23_RESET, 0);
snd_soc_component_write(component, TLV320AIC23_DIGT, TLV320AIC23_DEEMP_44K);
/* Unmute input */
snd_soc_component_update_bits(component, TLV320AIC23_LINVOL,
TLV320AIC23_LIM_MUTED, TLV320AIC23_LRS_ENABLED);
snd_soc_component_update_bits(component, TLV320AIC23_RINVOL,
TLV320AIC23_LIM_MUTED, TLV320AIC23_LRS_ENABLED);
snd_soc_component_update_bits(component, TLV320AIC23_ANLG,
TLV320AIC23_BYPASS_ON | TLV320AIC23_MICM_MUTED,
0);
/* Default output volume */
snd_soc_component_write(component, TLV320AIC23_LCHNVOL,
TLV320AIC23_DEFAULT_OUT_VOL & TLV320AIC23_OUT_VOL_MASK);
snd_soc_component_write(component, TLV320AIC23_RCHNVOL,
TLV320AIC23_DEFAULT_OUT_VOL & TLV320AIC23_OUT_VOL_MASK);
snd_soc_component_write(component, TLV320AIC23_ACTIVE, 0x1);
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_tlv320aic23 = {
.probe = tlv320aic23_component_probe,
.resume = tlv320aic23_resume,
.set_bias_level = tlv320aic23_set_bias_level,
.controls = tlv320aic23_snd_controls,
.num_controls = ARRAY_SIZE(tlv320aic23_snd_controls),
.dapm_widgets = tlv320aic23_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(tlv320aic23_dapm_widgets),
.dapm_routes = tlv320aic23_intercon,
.num_dapm_routes = ARRAY_SIZE(tlv320aic23_intercon),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
int tlv320aic23_probe(struct device *dev, struct regmap *regmap)
{
struct aic23 *aic23;
if (IS_ERR(regmap))
return PTR_ERR(regmap);
aic23 = devm_kzalloc(dev, sizeof(struct aic23), GFP_KERNEL);
if (aic23 == NULL)
return -ENOMEM;
aic23->regmap = regmap;
dev_set_drvdata(dev, aic23);
return devm_snd_soc_register_component(dev,
&soc_component_dev_tlv320aic23,
&tlv320aic23_dai, 1);
}
EXPORT_SYMBOL(tlv320aic23_probe);
MODULE_DESCRIPTION("ASoC TLV320AIC23 codec driver");
MODULE_AUTHOR("Arun KS <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/tlv320aic23.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) STMicroelectronics SA 2015
* Authors: Arnaud Pouliquen <[email protected]>
* for STMicroelectronics.
*/
#include <linux/io.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/mfd/syscon.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
/* DAC definitions */
/* stih407 DAC registers */
/* sysconf 5041: Audio-Gue-Control */
#define STIH407_AUDIO_GLUE_CTRL 0x000000A4
/* sysconf 5042: Audio-DAC-Control */
#define STIH407_AUDIO_DAC_CTRL 0x000000A8
/* DAC definitions */
#define STIH407_DAC_SOFTMUTE 0x0
#define STIH407_DAC_STANDBY_ANA 0x1
#define STIH407_DAC_STANDBY 0x2
#define STIH407_DAC_SOFTMUTE_MASK BIT(STIH407_DAC_SOFTMUTE)
#define STIH407_DAC_STANDBY_ANA_MASK BIT(STIH407_DAC_STANDBY_ANA)
#define STIH407_DAC_STANDBY_MASK BIT(STIH407_DAC_STANDBY)
/* SPDIF definitions */
#define SPDIF_BIPHASE_ENABLE 0x6
#define SPDIF_BIPHASE_IDLE 0x7
#define SPDIF_BIPHASE_ENABLE_MASK BIT(SPDIF_BIPHASE_ENABLE)
#define SPDIF_BIPHASE_IDLE_MASK BIT(SPDIF_BIPHASE_IDLE)
enum {
STI_SAS_DAI_SPDIF_OUT,
STI_SAS_DAI_ANALOG_OUT,
};
static const struct reg_default stih407_sas_reg_defaults[] = {
{ STIH407_AUDIO_DAC_CTRL, 0x000000000 },
{ STIH407_AUDIO_GLUE_CTRL, 0x00000040 },
};
struct sti_dac_audio {
struct regmap *regmap;
struct regmap *virt_regmap;
int mclk;
};
struct sti_spdif_audio {
struct regmap *regmap;
int mclk;
};
/* device data structure */
struct sti_sas_dev_data {
const struct regmap_config *regmap;
const struct snd_soc_dai_ops *dac_ops; /* DAC function callbacks */
const struct snd_soc_dapm_widget *dapm_widgets; /* dapms declaration */
const int num_dapm_widgets; /* dapms declaration */
const struct snd_soc_dapm_route *dapm_routes; /* route declaration */
const int num_dapm_routes; /* route declaration */
};
/* driver data structure */
struct sti_sas_data {
struct device *dev;
const struct sti_sas_dev_data *dev_data;
struct sti_dac_audio dac;
struct sti_spdif_audio spdif;
};
/* Read a register from the sysconf reg bank */
static int sti_sas_read_reg(void *context, unsigned int reg,
unsigned int *value)
{
struct sti_sas_data *drvdata = context;
int status;
u32 val;
status = regmap_read(drvdata->dac.regmap, reg, &val);
*value = (unsigned int)val;
return status;
}
/* Read a register from the sysconf reg bank */
static int sti_sas_write_reg(void *context, unsigned int reg,
unsigned int value)
{
struct sti_sas_data *drvdata = context;
return regmap_write(drvdata->dac.regmap, reg, value);
}
static int sti_sas_init_sas_registers(struct snd_soc_component *component,
struct sti_sas_data *data)
{
int ret;
/*
* DAC and SPDIF are activated by default
* put them in IDLE to save power
*/
/* Initialise bi-phase formatter to disabled */
ret = snd_soc_component_update_bits(component, STIH407_AUDIO_GLUE_CTRL,
SPDIF_BIPHASE_ENABLE_MASK, 0);
if (!ret)
/* Initialise bi-phase formatter idle value to 0 */
ret = snd_soc_component_update_bits(component, STIH407_AUDIO_GLUE_CTRL,
SPDIF_BIPHASE_IDLE_MASK, 0);
if (ret < 0) {
dev_err(component->dev, "Failed to update SPDIF registers\n");
return ret;
}
/* Init DAC configuration */
/* init configuration */
ret = snd_soc_component_update_bits(component, STIH407_AUDIO_DAC_CTRL,
STIH407_DAC_STANDBY_MASK,
STIH407_DAC_STANDBY_MASK);
if (!ret)
ret = snd_soc_component_update_bits(component, STIH407_AUDIO_DAC_CTRL,
STIH407_DAC_STANDBY_ANA_MASK,
STIH407_DAC_STANDBY_ANA_MASK);
if (!ret)
ret = snd_soc_component_update_bits(component, STIH407_AUDIO_DAC_CTRL,
STIH407_DAC_SOFTMUTE_MASK,
STIH407_DAC_SOFTMUTE_MASK);
if (ret < 0) {
dev_err(component->dev, "Failed to update DAC registers\n");
return ret;
}
return ret;
}
/*
* DAC
*/
static int sti_sas_dac_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
/* Sanity check only */
if ((fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) != SND_SOC_DAIFMT_CBC_CFC) {
dev_err(dai->component->dev,
"%s: ERROR: Unsupported clocking 0x%x\n",
__func__, fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK);
return -EINVAL;
}
return 0;
}
static const struct snd_soc_dapm_widget stih407_sas_dapm_widgets[] = {
SND_SOC_DAPM_OUT_DRV("DAC standby ana", STIH407_AUDIO_DAC_CTRL,
STIH407_DAC_STANDBY_ANA, 1, NULL, 0),
SND_SOC_DAPM_DAC("DAC standby", "dac_p", STIH407_AUDIO_DAC_CTRL,
STIH407_DAC_STANDBY, 1),
SND_SOC_DAPM_OUTPUT("DAC Output"),
};
static const struct snd_soc_dapm_route stih407_sas_route[] = {
{"DAC Output", NULL, "DAC standby ana"},
{"DAC standby ana", NULL, "DAC standby"},
};
static int stih407_sas_dac_mute(struct snd_soc_dai *dai, int mute, int stream)
{
struct snd_soc_component *component = dai->component;
if (mute) {
return snd_soc_component_update_bits(component, STIH407_AUDIO_DAC_CTRL,
STIH407_DAC_SOFTMUTE_MASK,
STIH407_DAC_SOFTMUTE_MASK);
} else {
return snd_soc_component_update_bits(component, STIH407_AUDIO_DAC_CTRL,
STIH407_DAC_SOFTMUTE_MASK,
0);
}
}
/*
* SPDIF
*/
static int sti_sas_spdif_set_fmt(struct snd_soc_dai *dai,
unsigned int fmt)
{
if ((fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) != SND_SOC_DAIFMT_CBC_CFC) {
dev_err(dai->component->dev,
"%s: ERROR: Unsupported clocking mask 0x%x\n",
__func__, fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK);
return -EINVAL;
}
return 0;
}
/*
* sti_sas_spdif_trigger:
* Trigger function is used to ensure that BiPhase Formater is disabled
* before CPU dai is stopped.
* This is mandatory to avoid that BPF is stalled
*/
static int sti_sas_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
return snd_soc_component_update_bits(component, STIH407_AUDIO_GLUE_CTRL,
SPDIF_BIPHASE_ENABLE_MASK,
SPDIF_BIPHASE_ENABLE_MASK);
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
return snd_soc_component_update_bits(component, STIH407_AUDIO_GLUE_CTRL,
SPDIF_BIPHASE_ENABLE_MASK,
0);
default:
return -EINVAL;
}
}
static bool sti_sas_volatile_register(struct device *dev, unsigned int reg)
{
if (reg == STIH407_AUDIO_GLUE_CTRL)
return true;
return false;
}
/*
* CODEC DAIS
*/
/*
* sti_sas_set_sysclk:
* get MCLK input frequency to check that MCLK-FS ratio is coherent
*/
static int sti_sas_set_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct sti_sas_data *drvdata = dev_get_drvdata(component->dev);
if (dir == SND_SOC_CLOCK_OUT)
return 0;
if (clk_id != 0)
return -EINVAL;
switch (dai->id) {
case STI_SAS_DAI_SPDIF_OUT:
drvdata->spdif.mclk = freq;
break;
case STI_SAS_DAI_ANALOG_OUT:
drvdata->dac.mclk = freq;
break;
}
return 0;
}
static int sti_sas_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct sti_sas_data *drvdata = dev_get_drvdata(component->dev);
struct snd_pcm_runtime *runtime = substream->runtime;
switch (dai->id) {
case STI_SAS_DAI_SPDIF_OUT:
if ((drvdata->spdif.mclk / runtime->rate) != 128) {
dev_err(component->dev, "unexpected mclk-fs ratio\n");
return -EINVAL;
}
break;
case STI_SAS_DAI_ANALOG_OUT:
if ((drvdata->dac.mclk / runtime->rate) != 256) {
dev_err(component->dev, "unexpected mclk-fs ratio\n");
return -EINVAL;
}
break;
}
return 0;
}
static const struct snd_soc_dai_ops stih407_dac_ops = {
.set_fmt = sti_sas_dac_set_fmt,
.mute_stream = stih407_sas_dac_mute,
.prepare = sti_sas_prepare,
.set_sysclk = sti_sas_set_sysclk,
};
static const struct regmap_config stih407_sas_regmap = {
.reg_bits = 32,
.val_bits = 32,
.fast_io = true,
.max_register = STIH407_AUDIO_DAC_CTRL,
.reg_defaults = stih407_sas_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(stih407_sas_reg_defaults),
.volatile_reg = sti_sas_volatile_register,
.cache_type = REGCACHE_MAPLE,
.reg_read = sti_sas_read_reg,
.reg_write = sti_sas_write_reg,
};
static const struct sti_sas_dev_data stih407_data = {
.regmap = &stih407_sas_regmap,
.dac_ops = &stih407_dac_ops,
.dapm_widgets = stih407_sas_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(stih407_sas_dapm_widgets),
.dapm_routes = stih407_sas_route,
.num_dapm_routes = ARRAY_SIZE(stih407_sas_route),
};
static struct snd_soc_dai_driver sti_sas_dai[] = {
{
.name = "sas-dai-spdif-out",
.id = STI_SAS_DAI_SPDIF_OUT,
.playback = {
.stream_name = "spdif_p",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 |
SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
},
.ops = (struct snd_soc_dai_ops[]) {
{
.set_fmt = sti_sas_spdif_set_fmt,
.trigger = sti_sas_spdif_trigger,
.set_sysclk = sti_sas_set_sysclk,
.prepare = sti_sas_prepare,
}
},
},
{
.name = "sas-dai-dac",
.id = STI_SAS_DAI_ANALOG_OUT,
.playback = {
.stream_name = "dac_p",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
},
},
};
#ifdef CONFIG_PM_SLEEP
static int sti_sas_resume(struct snd_soc_component *component)
{
struct sti_sas_data *drvdata = dev_get_drvdata(component->dev);
return sti_sas_init_sas_registers(component, drvdata);
}
#else
#define sti_sas_resume NULL
#endif
static int sti_sas_component_probe(struct snd_soc_component *component)
{
struct sti_sas_data *drvdata = dev_get_drvdata(component->dev);
return sti_sas_init_sas_registers(component, drvdata);
}
static struct snd_soc_component_driver sti_sas_driver = {
.probe = sti_sas_component_probe,
.resume = sti_sas_resume,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct of_device_id sti_sas_dev_match[] = {
{
.compatible = "st,stih407-sas-codec",
.data = &stih407_data,
},
{},
};
MODULE_DEVICE_TABLE(of, sti_sas_dev_match);
static int sti_sas_driver_probe(struct platform_device *pdev)
{
struct device_node *pnode = pdev->dev.of_node;
struct sti_sas_data *drvdata;
const struct of_device_id *of_id;
/* Allocate device structure */
drvdata = devm_kzalloc(&pdev->dev, sizeof(struct sti_sas_data),
GFP_KERNEL);
if (!drvdata)
return -ENOMEM;
/* Populate data structure depending on compatibility */
of_id = of_match_node(sti_sas_dev_match, pnode);
if (!of_id->data) {
dev_err(&pdev->dev, "data associated to device is missing\n");
return -EINVAL;
}
drvdata->dev_data = (struct sti_sas_dev_data *)of_id->data;
/* Initialise device structure */
drvdata->dev = &pdev->dev;
/* Request the DAC & SPDIF registers memory region */
drvdata->dac.virt_regmap = devm_regmap_init(&pdev->dev, NULL, drvdata,
drvdata->dev_data->regmap);
if (IS_ERR(drvdata->dac.virt_regmap)) {
dev_err(&pdev->dev, "audio registers not enabled\n");
return PTR_ERR(drvdata->dac.virt_regmap);
}
/* Request the syscon region */
drvdata->dac.regmap =
syscon_regmap_lookup_by_phandle(pnode, "st,syscfg");
if (IS_ERR(drvdata->dac.regmap)) {
dev_err(&pdev->dev, "syscon registers not available\n");
return PTR_ERR(drvdata->dac.regmap);
}
drvdata->spdif.regmap = drvdata->dac.regmap;
sti_sas_dai[STI_SAS_DAI_ANALOG_OUT].ops = drvdata->dev_data->dac_ops;
/* Set dapms*/
sti_sas_driver.dapm_widgets = drvdata->dev_data->dapm_widgets;
sti_sas_driver.num_dapm_widgets = drvdata->dev_data->num_dapm_widgets;
sti_sas_driver.dapm_routes = drvdata->dev_data->dapm_routes;
sti_sas_driver.num_dapm_routes = drvdata->dev_data->num_dapm_routes;
/* Store context */
dev_set_drvdata(&pdev->dev, drvdata);
return devm_snd_soc_register_component(&pdev->dev, &sti_sas_driver,
sti_sas_dai,
ARRAY_SIZE(sti_sas_dai));
}
static struct platform_driver sti_sas_platform_driver = {
.driver = {
.name = "sti-sas-codec",
.of_match_table = sti_sas_dev_match,
},
.probe = sti_sas_driver_probe,
};
module_platform_driver(sti_sas_platform_driver);
MODULE_DESCRIPTION("audio codec for STMicroelectronics sti platforms");
MODULE_AUTHOR("[email protected]");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/sti-sas.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* PCM1681 ASoC codec driver
*
* Copyright (c) StreamUnlimited GmbH 2013
* Marek Belisko <[email protected]>
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#define PCM1681_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE)
#define PCM1681_PCM_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | \
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | \
SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
#define PCM1681_SOFT_MUTE_ALL 0xff
#define PCM1681_DEEMPH_RATE_MASK 0x18
#define PCM1681_DEEMPH_MASK 0x01
#define PCM1681_ATT_CONTROL(X) (X <= 6 ? X : X + 9) /* Attenuation level */
#define PCM1681_SOFT_MUTE 0x07 /* Soft mute control register */
#define PCM1681_DAC_CONTROL 0x08 /* DAC operation control */
#define PCM1681_FMT_CONTROL 0x09 /* Audio interface data format */
#define PCM1681_DEEMPH_CONTROL 0x0a /* De-emphasis control */
#define PCM1681_ZERO_DETECT_STATUS 0x0e /* Zero detect status reg */
static const struct reg_default pcm1681_reg_defaults[] = {
{ 0x01, 0xff },
{ 0x02, 0xff },
{ 0x03, 0xff },
{ 0x04, 0xff },
{ 0x05, 0xff },
{ 0x06, 0xff },
{ 0x07, 0x00 },
{ 0x08, 0x00 },
{ 0x09, 0x06 },
{ 0x0A, 0x00 },
{ 0x0B, 0xff },
{ 0x0C, 0x0f },
{ 0x0D, 0x00 },
{ 0x10, 0xff },
{ 0x11, 0xff },
{ 0x12, 0x00 },
{ 0x13, 0x00 },
};
static bool pcm1681_accessible_reg(struct device *dev, unsigned int reg)
{
return !((reg == 0x00) || (reg == 0x0f));
}
static bool pcm1681_writeable_reg(struct device *dev, unsigned int reg)
{
return pcm1681_accessible_reg(dev, reg) &&
(reg != PCM1681_ZERO_DETECT_STATUS);
}
struct pcm1681_private {
struct regmap *regmap;
unsigned int format;
/* Current deemphasis status */
unsigned int deemph;
/* Current rate for deemphasis control */
unsigned int rate;
};
static const int pcm1681_deemph[] = { 44100, 48000, 32000 };
static int pcm1681_set_deemph(struct snd_soc_component *component)
{
struct pcm1681_private *priv = snd_soc_component_get_drvdata(component);
int i, val = -1, enable = 0;
if (priv->deemph) {
for (i = 0; i < ARRAY_SIZE(pcm1681_deemph); i++) {
if (pcm1681_deemph[i] == priv->rate) {
val = i;
break;
}
}
}
if (val != -1) {
regmap_update_bits(priv->regmap, PCM1681_DEEMPH_CONTROL,
PCM1681_DEEMPH_RATE_MASK, val << 3);
enable = 1;
} else {
enable = 0;
}
/* enable/disable deemphasis functionality */
return regmap_update_bits(priv->regmap, PCM1681_DEEMPH_CONTROL,
PCM1681_DEEMPH_MASK, enable);
}
static int pcm1681_get_deemph(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct pcm1681_private *priv = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = priv->deemph;
return 0;
}
static int pcm1681_put_deemph(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct pcm1681_private *priv = snd_soc_component_get_drvdata(component);
priv->deemph = ucontrol->value.integer.value[0];
return pcm1681_set_deemph(component);
}
static int pcm1681_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int format)
{
struct snd_soc_component *component = codec_dai->component;
struct pcm1681_private *priv = snd_soc_component_get_drvdata(component);
/* The PCM1681 can only be consumer to all clocks */
if ((format & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) != SND_SOC_DAIFMT_CBC_CFC) {
dev_err(component->dev, "Invalid clocking mode\n");
return -EINVAL;
}
priv->format = format;
return 0;
}
static int pcm1681_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
struct pcm1681_private *priv = snd_soc_component_get_drvdata(component);
int val;
if (mute)
val = PCM1681_SOFT_MUTE_ALL;
else
val = 0;
return regmap_write(priv->regmap, PCM1681_SOFT_MUTE, val);
}
static int pcm1681_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct pcm1681_private *priv = snd_soc_component_get_drvdata(component);
int val = 0, ret;
priv->rate = params_rate(params);
switch (priv->format & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_RIGHT_J:
switch (params_width(params)) {
case 24:
val = 0;
break;
case 16:
val = 3;
break;
default:
return -EINVAL;
}
break;
case SND_SOC_DAIFMT_I2S:
val = 0x04;
break;
case SND_SOC_DAIFMT_LEFT_J:
val = 0x05;
break;
default:
dev_err(component->dev, "Invalid DAI format\n");
return -EINVAL;
}
ret = regmap_update_bits(priv->regmap, PCM1681_FMT_CONTROL, 0x0f, val);
if (ret < 0)
return ret;
return pcm1681_set_deemph(component);
}
static const struct snd_soc_dai_ops pcm1681_dai_ops = {
.set_fmt = pcm1681_set_dai_fmt,
.hw_params = pcm1681_hw_params,
.mute_stream = pcm1681_mute,
.no_capture_mute = 1,
};
static const struct snd_soc_dapm_widget pcm1681_dapm_widgets[] = {
SND_SOC_DAPM_OUTPUT("VOUT1"),
SND_SOC_DAPM_OUTPUT("VOUT2"),
SND_SOC_DAPM_OUTPUT("VOUT3"),
SND_SOC_DAPM_OUTPUT("VOUT4"),
SND_SOC_DAPM_OUTPUT("VOUT5"),
SND_SOC_DAPM_OUTPUT("VOUT6"),
SND_SOC_DAPM_OUTPUT("VOUT7"),
SND_SOC_DAPM_OUTPUT("VOUT8"),
};
static const struct snd_soc_dapm_route pcm1681_dapm_routes[] = {
{ "VOUT1", NULL, "Playback" },
{ "VOUT2", NULL, "Playback" },
{ "VOUT3", NULL, "Playback" },
{ "VOUT4", NULL, "Playback" },
{ "VOUT5", NULL, "Playback" },
{ "VOUT6", NULL, "Playback" },
{ "VOUT7", NULL, "Playback" },
{ "VOUT8", NULL, "Playback" },
};
static const DECLARE_TLV_DB_SCALE(pcm1681_dac_tlv, -6350, 50, 1);
static const struct snd_kcontrol_new pcm1681_controls[] = {
SOC_DOUBLE_R_TLV("Channel 1/2 Playback Volume",
PCM1681_ATT_CONTROL(1), PCM1681_ATT_CONTROL(2), 0,
0x7f, 0, pcm1681_dac_tlv),
SOC_DOUBLE_R_TLV("Channel 3/4 Playback Volume",
PCM1681_ATT_CONTROL(3), PCM1681_ATT_CONTROL(4), 0,
0x7f, 0, pcm1681_dac_tlv),
SOC_DOUBLE_R_TLV("Channel 5/6 Playback Volume",
PCM1681_ATT_CONTROL(5), PCM1681_ATT_CONTROL(6), 0,
0x7f, 0, pcm1681_dac_tlv),
SOC_DOUBLE_R_TLV("Channel 7/8 Playback Volume",
PCM1681_ATT_CONTROL(7), PCM1681_ATT_CONTROL(8), 0,
0x7f, 0, pcm1681_dac_tlv),
SOC_SINGLE_BOOL_EXT("De-emphasis Switch", 0,
pcm1681_get_deemph, pcm1681_put_deemph),
};
static struct snd_soc_dai_driver pcm1681_dai = {
.name = "pcm1681-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 8,
.rates = PCM1681_PCM_RATES,
.formats = PCM1681_PCM_FORMATS,
},
.ops = &pcm1681_dai_ops,
};
#ifdef CONFIG_OF
static const struct of_device_id pcm1681_dt_ids[] = {
{ .compatible = "ti,pcm1681", },
{ }
};
MODULE_DEVICE_TABLE(of, pcm1681_dt_ids);
#endif
static const struct regmap_config pcm1681_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = 0x13,
.reg_defaults = pcm1681_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(pcm1681_reg_defaults),
.writeable_reg = pcm1681_writeable_reg,
.readable_reg = pcm1681_accessible_reg,
};
static const struct snd_soc_component_driver soc_component_dev_pcm1681 = {
.controls = pcm1681_controls,
.num_controls = ARRAY_SIZE(pcm1681_controls),
.dapm_widgets = pcm1681_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(pcm1681_dapm_widgets),
.dapm_routes = pcm1681_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(pcm1681_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct i2c_device_id pcm1681_i2c_id[] = {
{"pcm1681", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, pcm1681_i2c_id);
static int pcm1681_i2c_probe(struct i2c_client *client)
{
int ret;
struct pcm1681_private *priv;
priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->regmap = devm_regmap_init_i2c(client, &pcm1681_regmap);
if (IS_ERR(priv->regmap)) {
ret = PTR_ERR(priv->regmap);
dev_err(&client->dev, "Failed to create regmap: %d\n", ret);
return ret;
}
i2c_set_clientdata(client, priv);
return devm_snd_soc_register_component(&client->dev,
&soc_component_dev_pcm1681,
&pcm1681_dai, 1);
}
static struct i2c_driver pcm1681_i2c_driver = {
.driver = {
.name = "pcm1681",
.of_match_table = of_match_ptr(pcm1681_dt_ids),
},
.id_table = pcm1681_i2c_id,
.probe = pcm1681_i2c_probe,
};
module_i2c_driver(pcm1681_i2c_driver);
MODULE_DESCRIPTION("Texas Instruments PCM1681 ALSA SoC Codec Driver");
MODULE_AUTHOR("Marek Belisko <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/pcm1681.c |
// SPDX-License-Identifier: GPL-2.0
//
// peb2466.c -- Infineon PEB2466 ALSA SoC driver
//
// Copyright 2023 CS GROUP France
//
// Author: Herve Codina <[email protected]>
#include <asm/unaligned.h>
#include <linux/clk.h>
#include <linux/firmware.h>
#include <linux/gpio/consumer.h>
#include <linux/gpio/driver.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/slab.h>
#include <linux/spi/spi.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#define PEB2466_NB_CHANNEL 4
struct peb2466_lookup {
u8 (*table)[4];
unsigned int count;
};
#define PEB2466_TLV_SIZE (sizeof((unsigned int []){TLV_DB_SCALE_ITEM(0, 0, 0)}) / \
sizeof(unsigned int))
struct peb2466_lkup_ctrl {
int reg;
unsigned int index;
const struct peb2466_lookup *lookup;
unsigned int tlv_array[PEB2466_TLV_SIZE];
};
struct peb2466 {
struct spi_device *spi;
struct clk *mclk;
struct gpio_desc *reset_gpio;
u8 spi_tx_buf[2 + 8]; /* Cannot use stack area for SPI (dma-safe memory) */
u8 spi_rx_buf[2 + 8]; /* Cannot use stack area for SPI (dma-safe memory) */
struct regmap *regmap;
struct {
struct peb2466_lookup ax_lookup;
struct peb2466_lookup ar_lookup;
struct peb2466_lkup_ctrl ax_lkup_ctrl;
struct peb2466_lkup_ctrl ar_lkup_ctrl;
unsigned int tg1_freq_item;
unsigned int tg2_freq_item;
} ch[PEB2466_NB_CHANNEL];
int max_chan_playback;
int max_chan_capture;
struct {
struct gpio_chip gpio_chip;
struct mutex lock;
struct {
unsigned int xr0;
unsigned int xr1;
unsigned int xr2;
unsigned int xr3;
} cache;
} gpio;
};
#define PEB2466_CMD_R (1 << 5)
#define PEB2466_CMD_W (0 << 5)
#define PEB2466_CMD_MASK 0x18
#define PEB2466_CMD_XOP 0x18 /* XOP is 0bxxx11xxx */
#define PEB2466_CMD_SOP 0x10 /* SOP is 0bxxx10xxx */
#define PEB2466_CMD_COP 0x00 /* COP is 0bxxx0xxxx, handle 0bxxx00xxx */
#define PEB2466_CMD_COP1 0x08 /* COP is 0bxxx0xxxx, handle 0bxxx01xxx */
#define PEB2466_MAKE_XOP(_lsel) (PEB2466_CMD_XOP | (_lsel))
#define PEB2466_MAKE_SOP(_ad, _lsel) (PEB2466_CMD_SOP | ((_ad) << 6) | (_lsel))
#define PEB2466_MAKE_COP(_ad, _code) (PEB2466_CMD_COP | ((_ad) << 6) | (_code))
#define PEB2466_CR0(_ch) PEB2466_MAKE_SOP(_ch, 0x0)
#define PEB2466_CR0_TH (1 << 7)
#define PEB2466_CR0_IMR1 (1 << 6)
#define PEB2466_CR0_FRX (1 << 5)
#define PEB2466_CR0_FRR (1 << 4)
#define PEB2466_CR0_AX (1 << 3)
#define PEB2466_CR0_AR (1 << 2)
#define PEB2466_CR0_THSEL_MASK (0x3 << 0)
#define PEB2466_CR0_THSEL(_set) ((_set) << 0)
#define PEB2466_CR1(_ch) PEB2466_MAKE_SOP(_ch, 0x1)
#define PEB2466_CR1_ETG2 (1 << 7)
#define PEB2466_CR1_ETG1 (1 << 6)
#define PEB2466_CR1_PTG2 (1 << 5)
#define PEB2466_CR1_PTG1 (1 << 4)
#define PEB2466_CR1_LAW_MASK (1 << 3)
#define PEB2466_CR1_LAW_ALAW (0 << 3)
#define PEB2466_CR1_LAW_MULAW (1 << 3)
#define PEB2466_CR1_PU (1 << 0)
#define PEB2466_CR2(_ch) PEB2466_MAKE_SOP(_ch, 0x2)
#define PEB2466_CR3(_ch) PEB2466_MAKE_SOP(_ch, 0x3)
#define PEB2466_CR4(_ch) PEB2466_MAKE_SOP(_ch, 0x4)
#define PEB2466_CR5(_ch) PEB2466_MAKE_SOP(_ch, 0x5)
#define PEB2466_XR0 PEB2466_MAKE_XOP(0x0)
#define PEB2466_XR1 PEB2466_MAKE_XOP(0x1)
#define PEB2466_XR2 PEB2466_MAKE_XOP(0x2)
#define PEB2466_XR3 PEB2466_MAKE_XOP(0x3)
#define PEB2466_XR4 PEB2466_MAKE_XOP(0x4)
#define PEB2466_XR5 PEB2466_MAKE_XOP(0x5)
#define PEB2466_XR5_MCLK_1536 (0x0 << 6)
#define PEB2466_XR5_MCLK_2048 (0x1 << 6)
#define PEB2466_XR5_MCLK_4096 (0x2 << 6)
#define PEB2466_XR5_MCLK_8192 (0x3 << 6)
#define PEB2466_XR6 PEB2466_MAKE_XOP(0x6)
#define PEB2466_XR6_PCM_OFFSET(_off) ((_off) << 0)
#define PEB2466_XR7 PEB2466_MAKE_XOP(0x7)
#define PEB2466_TH_FILTER_P1(_ch) PEB2466_MAKE_COP(_ch, 0x0)
#define PEB2466_TH_FILTER_P2(_ch) PEB2466_MAKE_COP(_ch, 0x1)
#define PEB2466_TH_FILTER_P3(_ch) PEB2466_MAKE_COP(_ch, 0x2)
#define PEB2466_IMR1_FILTER_P1(_ch) PEB2466_MAKE_COP(_ch, 0x4)
#define PEB2466_IMR1_FILTER_P2(_ch) PEB2466_MAKE_COP(_ch, 0x5)
#define PEB2466_FRX_FILTER(_ch) PEB2466_MAKE_COP(_ch, 0x6)
#define PEB2466_FRR_FILTER(_ch) PEB2466_MAKE_COP(_ch, 0x7)
#define PEB2466_AX_FILTER(_ch) PEB2466_MAKE_COP(_ch, 0x8)
#define PEB2466_AR_FILTER(_ch) PEB2466_MAKE_COP(_ch, 0x9)
#define PEB2466_TG1(_ch) PEB2466_MAKE_COP(_ch, 0xc)
#define PEB2466_TG2(_ch) PEB2466_MAKE_COP(_ch, 0xd)
static int peb2466_write_byte(struct peb2466 *peb2466, u8 cmd, u8 val)
{
struct spi_transfer xfer = {
.tx_buf = &peb2466->spi_tx_buf,
.len = 2,
};
peb2466->spi_tx_buf[0] = cmd | PEB2466_CMD_W;
peb2466->spi_tx_buf[1] = val;
dev_dbg(&peb2466->spi->dev, "write byte (cmd %02x) %02x\n",
peb2466->spi_tx_buf[0], peb2466->spi_tx_buf[1]);
return spi_sync_transfer(peb2466->spi, &xfer, 1);
}
static int peb2466_read_byte(struct peb2466 *peb2466, u8 cmd, u8 *val)
{
struct spi_transfer xfer = {
.tx_buf = &peb2466->spi_tx_buf,
.rx_buf = &peb2466->spi_rx_buf,
.len = 3,
};
int ret;
peb2466->spi_tx_buf[0] = cmd | PEB2466_CMD_R;
ret = spi_sync_transfer(peb2466->spi, &xfer, 1);
if (ret)
return ret;
if (peb2466->spi_rx_buf[1] != 0x81) {
dev_err(&peb2466->spi->dev,
"spi xfer rd (cmd %02x) invalid ident byte (0x%02x)\n",
peb2466->spi_tx_buf[0], peb2466->spi_rx_buf[1]);
return -EILSEQ;
}
*val = peb2466->spi_rx_buf[2];
dev_dbg(&peb2466->spi->dev, "read byte (cmd %02x) %02x\n",
peb2466->spi_tx_buf[0], *val);
return 0;
}
static int peb2466_write_buf(struct peb2466 *peb2466, u8 cmd, const u8 *buf, unsigned int len)
{
struct spi_transfer xfer = {
.tx_buf = &peb2466->spi_tx_buf,
.len = len + 1,
};
if (len > 8)
return -EINVAL;
peb2466->spi_tx_buf[0] = cmd | PEB2466_CMD_W;
memcpy(&peb2466->spi_tx_buf[1], buf, len);
dev_dbg(&peb2466->spi->dev, "write buf (cmd %02x, %u) %*ph\n",
peb2466->spi_tx_buf[0], len, len, &peb2466->spi_tx_buf[1]);
return spi_sync_transfer(peb2466->spi, &xfer, 1);
}
static int peb2466_reg_write(void *context, unsigned int reg, unsigned int val)
{
struct peb2466 *peb2466 = context;
int ret;
/*
* Only XOP and SOP commands can be handled as registers.
* COP commands are handled using direct peb2466_write_buf() calls.
*/
switch (reg & PEB2466_CMD_MASK) {
case PEB2466_CMD_XOP:
case PEB2466_CMD_SOP:
ret = peb2466_write_byte(peb2466, reg, val);
break;
default:
dev_err(&peb2466->spi->dev, "Not a XOP or SOP command\n");
ret = -EINVAL;
break;
}
return ret;
}
static int peb2466_reg_read(void *context, unsigned int reg, unsigned int *val)
{
struct peb2466 *peb2466 = context;
int ret;
u8 tmp;
/* Only XOP and SOP commands can be handled as registers */
switch (reg & PEB2466_CMD_MASK) {
case PEB2466_CMD_XOP:
case PEB2466_CMD_SOP:
ret = peb2466_read_byte(peb2466, reg, &tmp);
*val = tmp;
break;
default:
dev_err(&peb2466->spi->dev, "Not a XOP or SOP command\n");
ret = -EINVAL;
break;
}
return ret;
}
static const struct regmap_config peb2466_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = 0xFF,
.reg_write = peb2466_reg_write,
.reg_read = peb2466_reg_read,
.cache_type = REGCACHE_NONE,
};
static int peb2466_lkup_ctrl_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
struct peb2466_lkup_ctrl *lkup_ctrl =
(struct peb2466_lkup_ctrl *)kcontrol->private_value;
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = 1;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = lkup_ctrl->lookup->count - 1;
return 0;
}
static int peb2466_lkup_ctrl_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct peb2466_lkup_ctrl *lkup_ctrl =
(struct peb2466_lkup_ctrl *)kcontrol->private_value;
ucontrol->value.integer.value[0] = lkup_ctrl->index;
return 0;
}
static int peb2466_lkup_ctrl_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct peb2466_lkup_ctrl *lkup_ctrl =
(struct peb2466_lkup_ctrl *)kcontrol->private_value;
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component);
unsigned int index;
int ret;
index = ucontrol->value.integer.value[0];
if (index >= lkup_ctrl->lookup->count)
return -EINVAL;
if (index == lkup_ctrl->index)
return 0;
ret = peb2466_write_buf(peb2466, lkup_ctrl->reg,
lkup_ctrl->lookup->table[index], 4);
if (ret)
return ret;
lkup_ctrl->index = index;
return 1; /* The value changed */
}
static int peb2466_add_lkup_ctrl(struct snd_soc_component *component,
struct peb2466_lkup_ctrl *lkup_ctrl,
const char *name, int min_val, int step)
{
DECLARE_TLV_DB_SCALE(tlv_array, min_val, step, 0);
struct snd_kcontrol_new control = {0};
BUILD_BUG_ON(sizeof(lkup_ctrl->tlv_array) < sizeof(tlv_array));
memcpy(lkup_ctrl->tlv_array, tlv_array, sizeof(tlv_array));
control.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
control.name = name;
control.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
SNDRV_CTL_ELEM_ACCESS_READWRITE;
control.tlv.p = lkup_ctrl->tlv_array;
control.info = peb2466_lkup_ctrl_info;
control.get = peb2466_lkup_ctrl_get;
control.put = peb2466_lkup_ctrl_put;
control.private_value = (unsigned long)lkup_ctrl;
return snd_soc_add_component_controls(component, &control, 1);
}
enum peb2466_tone_freq {
PEB2466_TONE_697HZ,
PEB2466_TONE_800HZ,
PEB2466_TONE_950HZ,
PEB2466_TONE_1000HZ,
PEB2466_TONE_1008HZ,
PEB2466_TONE_2000HZ,
};
static const u8 peb2466_tone_lookup[][4] = {
[PEB2466_TONE_697HZ] = {0x0a, 0x33, 0x5a, 0x2c},
[PEB2466_TONE_800HZ] = {0x12, 0xD6, 0x5a, 0xc0},
[PEB2466_TONE_950HZ] = {0x1c, 0xf0, 0x5c, 0xc0},
[PEB2466_TONE_1000HZ] = {0}, /* lookup value not used for 1000Hz */
[PEB2466_TONE_1008HZ] = {0x1a, 0xae, 0x57, 0x70},
[PEB2466_TONE_2000HZ] = {0x00, 0x80, 0x50, 0x09},
};
static const char * const peb2466_tone_freq_txt[] = {
[PEB2466_TONE_697HZ] = "697Hz",
[PEB2466_TONE_800HZ] = "800Hz",
[PEB2466_TONE_950HZ] = "950Hz",
[PEB2466_TONE_1000HZ] = "1000Hz",
[PEB2466_TONE_1008HZ] = "1008Hz",
[PEB2466_TONE_2000HZ] = "2000Hz"
};
static const struct soc_enum peb2466_tg_freq[][2] = {
[0] = {
SOC_ENUM_SINGLE(PEB2466_TG1(0), 0, ARRAY_SIZE(peb2466_tone_freq_txt),
peb2466_tone_freq_txt),
SOC_ENUM_SINGLE(PEB2466_TG2(0), 0, ARRAY_SIZE(peb2466_tone_freq_txt),
peb2466_tone_freq_txt)
},
[1] = {
SOC_ENUM_SINGLE(PEB2466_TG1(1), 0, ARRAY_SIZE(peb2466_tone_freq_txt),
peb2466_tone_freq_txt),
SOC_ENUM_SINGLE(PEB2466_TG2(1), 0, ARRAY_SIZE(peb2466_tone_freq_txt),
peb2466_tone_freq_txt)
},
[2] = {
SOC_ENUM_SINGLE(PEB2466_TG1(2), 0, ARRAY_SIZE(peb2466_tone_freq_txt),
peb2466_tone_freq_txt),
SOC_ENUM_SINGLE(PEB2466_TG2(2), 0, ARRAY_SIZE(peb2466_tone_freq_txt),
peb2466_tone_freq_txt)
},
[3] = {
SOC_ENUM_SINGLE(PEB2466_TG1(3), 0, ARRAY_SIZE(peb2466_tone_freq_txt),
peb2466_tone_freq_txt),
SOC_ENUM_SINGLE(PEB2466_TG2(3), 0, ARRAY_SIZE(peb2466_tone_freq_txt),
peb2466_tone_freq_txt)
}
};
static int peb2466_tg_freq_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
switch (e->reg) {
case PEB2466_TG1(0):
ucontrol->value.enumerated.item[0] = peb2466->ch[0].tg1_freq_item;
break;
case PEB2466_TG2(0):
ucontrol->value.enumerated.item[0] = peb2466->ch[0].tg2_freq_item;
break;
case PEB2466_TG1(1):
ucontrol->value.enumerated.item[0] = peb2466->ch[1].tg1_freq_item;
break;
case PEB2466_TG2(1):
ucontrol->value.enumerated.item[0] = peb2466->ch[1].tg2_freq_item;
break;
case PEB2466_TG1(2):
ucontrol->value.enumerated.item[0] = peb2466->ch[2].tg1_freq_item;
break;
case PEB2466_TG2(2):
ucontrol->value.enumerated.item[0] = peb2466->ch[2].tg2_freq_item;
break;
case PEB2466_TG1(3):
ucontrol->value.enumerated.item[0] = peb2466->ch[3].tg1_freq_item;
break;
case PEB2466_TG2(3):
ucontrol->value.enumerated.item[0] = peb2466->ch[3].tg2_freq_item;
break;
default:
return -EINVAL;
}
return 0;
}
static int peb2466_tg_freq_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int *tg_freq_item;
u8 cr1_reg, cr1_mask;
unsigned int index;
int ret;
index = ucontrol->value.enumerated.item[0];
if (index >= ARRAY_SIZE(peb2466_tone_lookup))
return -EINVAL;
switch (e->reg) {
case PEB2466_TG1(0):
tg_freq_item = &peb2466->ch[0].tg1_freq_item;
cr1_reg = PEB2466_CR1(0);
cr1_mask = PEB2466_CR1_PTG1;
break;
case PEB2466_TG2(0):
tg_freq_item = &peb2466->ch[0].tg2_freq_item;
cr1_reg = PEB2466_CR1(0);
cr1_mask = PEB2466_CR1_PTG2;
break;
case PEB2466_TG1(1):
tg_freq_item = &peb2466->ch[1].tg1_freq_item;
cr1_reg = PEB2466_CR1(1);
cr1_mask = PEB2466_CR1_PTG1;
break;
case PEB2466_TG2(1):
tg_freq_item = &peb2466->ch[1].tg2_freq_item;
cr1_reg = PEB2466_CR1(1);
cr1_mask = PEB2466_CR1_PTG2;
break;
case PEB2466_TG1(2):
tg_freq_item = &peb2466->ch[2].tg1_freq_item;
cr1_reg = PEB2466_CR1(2);
cr1_mask = PEB2466_CR1_PTG1;
break;
case PEB2466_TG2(2):
tg_freq_item = &peb2466->ch[2].tg2_freq_item;
cr1_reg = PEB2466_CR1(2);
cr1_mask = PEB2466_CR1_PTG2;
break;
case PEB2466_TG1(3):
tg_freq_item = &peb2466->ch[3].tg1_freq_item;
cr1_reg = PEB2466_CR1(3);
cr1_mask = PEB2466_CR1_PTG1;
break;
case PEB2466_TG2(3):
tg_freq_item = &peb2466->ch[3].tg2_freq_item;
cr1_reg = PEB2466_CR1(3);
cr1_mask = PEB2466_CR1_PTG2;
break;
default:
return -EINVAL;
}
if (index == *tg_freq_item)
return 0;
if (index == PEB2466_TONE_1000HZ) {
ret = regmap_update_bits(peb2466->regmap, cr1_reg, cr1_mask, 0);
if (ret)
return ret;
} else {
ret = peb2466_write_buf(peb2466, e->reg, peb2466_tone_lookup[index], 4);
if (ret)
return ret;
ret = regmap_update_bits(peb2466->regmap, cr1_reg, cr1_mask, cr1_mask);
if (ret)
return ret;
}
*tg_freq_item = index;
return 1; /* The value changed */
}
static const struct snd_kcontrol_new peb2466_ch0_out_mix_controls[] = {
SOC_DAPM_SINGLE("TG1 Switch", PEB2466_CR1(0), 6, 1, 0),
SOC_DAPM_SINGLE("TG2 Switch", PEB2466_CR1(0), 7, 1, 0),
SOC_DAPM_SINGLE("Voice Switch", PEB2466_CR2(0), 0, 1, 0)
};
static const struct snd_kcontrol_new peb2466_ch1_out_mix_controls[] = {
SOC_DAPM_SINGLE("TG1 Switch", PEB2466_CR1(1), 6, 1, 0),
SOC_DAPM_SINGLE("TG2 Switch", PEB2466_CR1(1), 7, 1, 0),
SOC_DAPM_SINGLE("Voice Switch", PEB2466_CR2(1), 0, 1, 0)
};
static const struct snd_kcontrol_new peb2466_ch2_out_mix_controls[] = {
SOC_DAPM_SINGLE("TG1 Switch", PEB2466_CR1(2), 6, 1, 0),
SOC_DAPM_SINGLE("TG2 Switch", PEB2466_CR1(2), 7, 1, 0),
SOC_DAPM_SINGLE("Voice Switch", PEB2466_CR2(2), 0, 1, 0)
};
static const struct snd_kcontrol_new peb2466_ch3_out_mix_controls[] = {
SOC_DAPM_SINGLE("TG1 Switch", PEB2466_CR1(3), 6, 1, 0),
SOC_DAPM_SINGLE("TG2 Switch", PEB2466_CR1(3), 7, 1, 0),
SOC_DAPM_SINGLE("Voice Switch", PEB2466_CR2(3), 0, 1, 0)
};
static const struct snd_kcontrol_new peb2466_controls[] = {
/* Attenuators */
SOC_SINGLE("DAC0 -6dB Playback Switch", PEB2466_CR3(0), 2, 1, 0),
SOC_SINGLE("DAC1 -6dB Playback Switch", PEB2466_CR3(1), 2, 1, 0),
SOC_SINGLE("DAC2 -6dB Playback Switch", PEB2466_CR3(2), 2, 1, 0),
SOC_SINGLE("DAC3 -6dB Playback Switch", PEB2466_CR3(3), 2, 1, 0),
/* Amplifiers */
SOC_SINGLE("ADC0 +6dB Capture Switch", PEB2466_CR3(0), 3, 1, 0),
SOC_SINGLE("ADC1 +6dB Capture Switch", PEB2466_CR3(1), 3, 1, 0),
SOC_SINGLE("ADC2 +6dB Capture Switch", PEB2466_CR3(2), 3, 1, 0),
SOC_SINGLE("ADC3 +6dB Capture Switch", PEB2466_CR3(3), 3, 1, 0),
/* Tone generators */
SOC_ENUM_EXT("DAC0 TG1 Freq", peb2466_tg_freq[0][0],
peb2466_tg_freq_get, peb2466_tg_freq_put),
SOC_ENUM_EXT("DAC1 TG1 Freq", peb2466_tg_freq[1][0],
peb2466_tg_freq_get, peb2466_tg_freq_put),
SOC_ENUM_EXT("DAC2 TG1 Freq", peb2466_tg_freq[2][0],
peb2466_tg_freq_get, peb2466_tg_freq_put),
SOC_ENUM_EXT("DAC3 TG1 Freq", peb2466_tg_freq[3][0],
peb2466_tg_freq_get, peb2466_tg_freq_put),
SOC_ENUM_EXT("DAC0 TG2 Freq", peb2466_tg_freq[0][1],
peb2466_tg_freq_get, peb2466_tg_freq_put),
SOC_ENUM_EXT("DAC1 TG2 Freq", peb2466_tg_freq[1][1],
peb2466_tg_freq_get, peb2466_tg_freq_put),
SOC_ENUM_EXT("DAC2 TG2 Freq", peb2466_tg_freq[2][1],
peb2466_tg_freq_get, peb2466_tg_freq_put),
SOC_ENUM_EXT("DAC3 TG2 Freq", peb2466_tg_freq[3][1],
peb2466_tg_freq_get, peb2466_tg_freq_put),
};
static const struct snd_soc_dapm_widget peb2466_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("CH0 PWR", PEB2466_CR1(0), 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CH1 PWR", PEB2466_CR1(1), 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CH2 PWR", PEB2466_CR1(2), 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CH3 PWR", PEB2466_CR1(3), 0, 0, NULL, 0),
SND_SOC_DAPM_DAC("CH0 DIN", "Playback", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("CH1 DIN", "Playback", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("CH2 DIN", "Playback", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("CH3 DIN", "Playback", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SIGGEN("CH0 TG1"),
SND_SOC_DAPM_SIGGEN("CH1 TG1"),
SND_SOC_DAPM_SIGGEN("CH2 TG1"),
SND_SOC_DAPM_SIGGEN("CH3 TG1"),
SND_SOC_DAPM_SIGGEN("CH0 TG2"),
SND_SOC_DAPM_SIGGEN("CH1 TG2"),
SND_SOC_DAPM_SIGGEN("CH2 TG2"),
SND_SOC_DAPM_SIGGEN("CH3 TG2"),
SND_SOC_DAPM_MIXER("DAC0 Mixer", SND_SOC_NOPM, 0, 0,
peb2466_ch0_out_mix_controls,
ARRAY_SIZE(peb2466_ch0_out_mix_controls)),
SND_SOC_DAPM_MIXER("DAC1 Mixer", SND_SOC_NOPM, 0, 0,
peb2466_ch1_out_mix_controls,
ARRAY_SIZE(peb2466_ch1_out_mix_controls)),
SND_SOC_DAPM_MIXER("DAC2 Mixer", SND_SOC_NOPM, 0, 0,
peb2466_ch2_out_mix_controls,
ARRAY_SIZE(peb2466_ch2_out_mix_controls)),
SND_SOC_DAPM_MIXER("DAC3 Mixer", SND_SOC_NOPM, 0, 0,
peb2466_ch3_out_mix_controls,
ARRAY_SIZE(peb2466_ch3_out_mix_controls)),
SND_SOC_DAPM_PGA("DAC0 PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DAC1 PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DAC2 PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DAC3 PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("OUT0"),
SND_SOC_DAPM_OUTPUT("OUT1"),
SND_SOC_DAPM_OUTPUT("OUT2"),
SND_SOC_DAPM_OUTPUT("OUT3"),
SND_SOC_DAPM_INPUT("IN0"),
SND_SOC_DAPM_INPUT("IN1"),
SND_SOC_DAPM_INPUT("IN2"),
SND_SOC_DAPM_INPUT("IN3"),
SND_SOC_DAPM_DAC("ADC0", "Capture", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("ADC1", "Capture", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("ADC2", "Capture", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("ADC3", "Capture", SND_SOC_NOPM, 0, 0),
};
static const struct snd_soc_dapm_route peb2466_dapm_routes[] = {
{ "CH0 DIN", NULL, "CH0 PWR" },
{ "CH1 DIN", NULL, "CH1 PWR" },
{ "CH2 DIN", NULL, "CH2 PWR" },
{ "CH3 DIN", NULL, "CH3 PWR" },
{ "CH0 TG1", NULL, "CH0 PWR" },
{ "CH1 TG1", NULL, "CH1 PWR" },
{ "CH2 TG1", NULL, "CH2 PWR" },
{ "CH3 TG1", NULL, "CH3 PWR" },
{ "CH0 TG2", NULL, "CH0 PWR" },
{ "CH1 TG2", NULL, "CH1 PWR" },
{ "CH2 TG2", NULL, "CH2 PWR" },
{ "CH3 TG2", NULL, "CH3 PWR" },
{ "DAC0 Mixer", "TG1 Switch", "CH0 TG1" },
{ "DAC0 Mixer", "TG2 Switch", "CH0 TG2" },
{ "DAC0 Mixer", "Voice Switch", "CH0 DIN" },
{ "DAC0 Mixer", NULL, "CH0 DIN" },
{ "DAC1 Mixer", "TG1 Switch", "CH1 TG1" },
{ "DAC1 Mixer", "TG2 Switch", "CH1 TG2" },
{ "DAC1 Mixer", "Voice Switch", "CH1 DIN" },
{ "DAC1 Mixer", NULL, "CH1 DIN" },
{ "DAC2 Mixer", "TG1 Switch", "CH2 TG1" },
{ "DAC2 Mixer", "TG2 Switch", "CH2 TG2" },
{ "DAC2 Mixer", "Voice Switch", "CH2 DIN" },
{ "DAC2 Mixer", NULL, "CH2 DIN" },
{ "DAC3 Mixer", "TG1 Switch", "CH3 TG1" },
{ "DAC3 Mixer", "TG2 Switch", "CH3 TG2" },
{ "DAC3 Mixer", "Voice Switch", "CH3 DIN" },
{ "DAC3 Mixer", NULL, "CH3 DIN" },
{ "DAC0 PGA", NULL, "DAC0 Mixer" },
{ "DAC1 PGA", NULL, "DAC1 Mixer" },
{ "DAC2 PGA", NULL, "DAC2 Mixer" },
{ "DAC3 PGA", NULL, "DAC3 Mixer" },
{ "OUT0", NULL, "DAC0 PGA" },
{ "OUT1", NULL, "DAC1 PGA" },
{ "OUT2", NULL, "DAC2 PGA" },
{ "OUT3", NULL, "DAC3 PGA" },
{ "ADC0", NULL, "IN0" },
{ "ADC1", NULL, "IN1" },
{ "ADC2", NULL, "IN2" },
{ "ADC3", NULL, "IN3" },
{ "ADC0", NULL, "CH0 PWR" },
{ "ADC1", NULL, "CH1 PWR" },
{ "ADC2", NULL, "CH2 PWR" },
{ "ADC3", NULL, "CH3 PWR" },
};
static int peb2466_dai_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int width)
{
struct peb2466 *peb2466 = snd_soc_component_get_drvdata(dai->component);
unsigned int chan;
unsigned int mask;
u8 slot;
int ret;
switch (width) {
case 0:
/* Not set -> default 8 */
case 8:
break;
default:
dev_err(dai->dev, "tdm slot width %d not supported\n", width);
return -EINVAL;
}
mask = tx_mask;
slot = 0;
chan = 0;
while (mask && chan < PEB2466_NB_CHANNEL) {
if (mask & 0x1) {
ret = regmap_write(peb2466->regmap, PEB2466_CR5(chan), slot);
if (ret) {
dev_err(dai->dev, "chan %d set tx tdm slot failed (%d)\n",
chan, ret);
return ret;
}
chan++;
}
mask >>= 1;
slot++;
}
if (mask) {
dev_err(dai->dev, "too much tx slots defined (mask = 0x%x) support max %d\n",
tx_mask, PEB2466_NB_CHANNEL);
return -EINVAL;
}
peb2466->max_chan_playback = chan;
mask = rx_mask;
slot = 0;
chan = 0;
while (mask && chan < PEB2466_NB_CHANNEL) {
if (mask & 0x1) {
ret = regmap_write(peb2466->regmap, PEB2466_CR4(chan), slot);
if (ret) {
dev_err(dai->dev, "chan %d set rx tdm slot failed (%d)\n",
chan, ret);
return ret;
}
chan++;
}
mask >>= 1;
slot++;
}
if (mask) {
dev_err(dai->dev, "too much rx slots defined (mask = 0x%x) support max %d\n",
rx_mask, PEB2466_NB_CHANNEL);
return -EINVAL;
}
peb2466->max_chan_capture = chan;
return 0;
}
static int peb2466_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct peb2466 *peb2466 = snd_soc_component_get_drvdata(dai->component);
u8 xr6;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
xr6 = PEB2466_XR6_PCM_OFFSET(1);
break;
case SND_SOC_DAIFMT_DSP_B:
xr6 = PEB2466_XR6_PCM_OFFSET(0);
break;
default:
dev_err(dai->dev, "Unsupported format 0x%x\n",
fmt & SND_SOC_DAIFMT_FORMAT_MASK);
return -EINVAL;
}
return regmap_write(peb2466->regmap, PEB2466_XR6, xr6);
}
static int peb2466_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct peb2466 *peb2466 = snd_soc_component_get_drvdata(dai->component);
unsigned int ch;
int ret;
u8 cr1;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_MU_LAW:
cr1 = PEB2466_CR1_LAW_MULAW;
break;
case SNDRV_PCM_FORMAT_A_LAW:
cr1 = PEB2466_CR1_LAW_ALAW;
break;
default:
dev_err(&peb2466->spi->dev, "Unsupported format 0x%x\n",
params_format(params));
return -EINVAL;
}
for (ch = 0; ch < PEB2466_NB_CHANNEL; ch++) {
ret = regmap_update_bits(peb2466->regmap, PEB2466_CR1(ch),
PEB2466_CR1_LAW_MASK, cr1);
if (ret)
return ret;
}
return 0;
}
static const unsigned int peb2466_sample_bits[] = {8};
static struct snd_pcm_hw_constraint_list peb2466_sample_bits_constr = {
.list = peb2466_sample_bits,
.count = ARRAY_SIZE(peb2466_sample_bits),
};
static int peb2466_dai_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct peb2466 *peb2466 = snd_soc_component_get_drvdata(dai->component);
unsigned int max_ch;
int ret;
max_ch = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
peb2466->max_chan_playback : peb2466->max_chan_capture;
/*
* Disable stream support (min = 0, max = 0) if no timeslots were
* configured.
*/
ret = snd_pcm_hw_constraint_minmax(substream->runtime,
SNDRV_PCM_HW_PARAM_CHANNELS,
max_ch ? 1 : 0, max_ch);
if (ret < 0)
return ret;
return snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
&peb2466_sample_bits_constr);
}
static u64 peb2466_dai_formats[] = {
SND_SOC_POSSIBLE_DAIFMT_DSP_A |
SND_SOC_POSSIBLE_DAIFMT_DSP_B,
};
static const struct snd_soc_dai_ops peb2466_dai_ops = {
.startup = peb2466_dai_startup,
.hw_params = peb2466_dai_hw_params,
.set_tdm_slot = peb2466_dai_set_tdm_slot,
.set_fmt = peb2466_dai_set_fmt,
.auto_selectable_formats = peb2466_dai_formats,
.num_auto_selectable_formats = ARRAY_SIZE(peb2466_dai_formats),
};
static struct snd_soc_dai_driver peb2466_dai_driver = {
.name = "peb2466",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = PEB2466_NB_CHANNEL,
.rates = SNDRV_PCM_RATE_8000,
.formats = SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = PEB2466_NB_CHANNEL,
.rates = SNDRV_PCM_RATE_8000,
.formats = SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW,
},
.ops = &peb2466_dai_ops,
};
static int peb2466_reset_audio(struct peb2466 *peb2466)
{
static const struct reg_sequence reg_reset[] = {
{ .reg = PEB2466_XR6, .def = 0x00 },
{ .reg = PEB2466_CR5(0), .def = 0x00 },
{ .reg = PEB2466_CR4(0), .def = 0x00 },
{ .reg = PEB2466_CR3(0), .def = 0x00 },
{ .reg = PEB2466_CR2(0), .def = 0x00 },
{ .reg = PEB2466_CR1(0), .def = 0x00 },
{ .reg = PEB2466_CR0(0), .def = PEB2466_CR0_IMR1 },
{ .reg = PEB2466_CR5(1), .def = 0x00 },
{ .reg = PEB2466_CR4(1), .def = 0x00 },
{ .reg = PEB2466_CR3(1), .def = 0x00 },
{ .reg = PEB2466_CR2(1), .def = 0x00 },
{ .reg = PEB2466_CR1(1), .def = 0x00 },
{ .reg = PEB2466_CR0(1), .def = PEB2466_CR0_IMR1 },
{ .reg = PEB2466_CR5(2), .def = 0x00 },
{ .reg = PEB2466_CR4(2), .def = 0x00 },
{ .reg = PEB2466_CR3(2), .def = 0x00 },
{ .reg = PEB2466_CR2(2), .def = 0x00 },
{ .reg = PEB2466_CR1(2), .def = 0x00 },
{ .reg = PEB2466_CR0(2), .def = PEB2466_CR0_IMR1 },
{ .reg = PEB2466_CR5(3), .def = 0x00 },
{ .reg = PEB2466_CR4(3), .def = 0x00 },
{ .reg = PEB2466_CR3(3), .def = 0x00 },
{ .reg = PEB2466_CR2(3), .def = 0x00 },
{ .reg = PEB2466_CR1(3), .def = 0x00 },
{ .reg = PEB2466_CR0(3), .def = PEB2466_CR0_IMR1 },
};
static const u8 imr1_p1[8] = {0x00, 0x90, 0x09, 0x00, 0x90, 0x09, 0x00, 0x00};
static const u8 imr1_p2[8] = {0x7F, 0xFF, 0x00, 0x00, 0x90, 0x14, 0x40, 0x08};
static const u8 zero[8] = {0};
int ret;
int i;
for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) {
peb2466->ch[i].tg1_freq_item = PEB2466_TONE_1000HZ;
peb2466->ch[i].tg2_freq_item = PEB2466_TONE_1000HZ;
/*
* Even if not used, disabling IM/R1 filter is not recommended.
* Instead, we must configure it with default coefficients and
* enable it.
* The filter will be enabled right after (in the following
* regmap_multi_reg_write() call).
*/
ret = peb2466_write_buf(peb2466, PEB2466_IMR1_FILTER_P1(i), imr1_p1, 8);
if (ret)
return ret;
ret = peb2466_write_buf(peb2466, PEB2466_IMR1_FILTER_P2(i), imr1_p2, 8);
if (ret)
return ret;
/* Set all other filters coefficients to zero */
ret = peb2466_write_buf(peb2466, PEB2466_TH_FILTER_P1(i), zero, 8);
if (ret)
return ret;
ret = peb2466_write_buf(peb2466, PEB2466_TH_FILTER_P2(i), zero, 8);
if (ret)
return ret;
ret = peb2466_write_buf(peb2466, PEB2466_TH_FILTER_P3(i), zero, 8);
if (ret)
return ret;
ret = peb2466_write_buf(peb2466, PEB2466_FRX_FILTER(i), zero, 8);
if (ret)
return ret;
ret = peb2466_write_buf(peb2466, PEB2466_FRR_FILTER(i), zero, 8);
if (ret)
return ret;
ret = peb2466_write_buf(peb2466, PEB2466_AX_FILTER(i), zero, 4);
if (ret)
return ret;
ret = peb2466_write_buf(peb2466, PEB2466_AR_FILTER(i), zero, 4);
if (ret)
return ret;
}
return regmap_multi_reg_write(peb2466->regmap, reg_reset, ARRAY_SIZE(reg_reset));
}
static int peb2466_fw_parse_thfilter(struct snd_soc_component *component,
u16 tag, u32 lng, const u8 *data)
{
struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component);
u8 mask;
int ret;
int i;
dev_info(component->dev, "fw TH filter: mask %x, %*phN\n", *data,
lng - 1, data + 1);
/*
* TH_FILTER TLV data:
* - @0 1 byte: Chan mask (bit set means related channel is concerned)
* - @1 8 bytes: TH-Filter coefficients part1
* - @9 8 bytes: TH-Filter coefficients part2
* - @17 8 bytes: TH-Filter coefficients part3
*/
mask = *data;
for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) {
if (!(mask & (1 << i)))
continue;
ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i),
PEB2466_CR0_TH, 0);
if (ret)
return ret;
ret = peb2466_write_buf(peb2466, PEB2466_TH_FILTER_P1(i), data + 1, 8);
if (ret)
return ret;
ret = peb2466_write_buf(peb2466, PEB2466_TH_FILTER_P2(i), data + 9, 8);
if (ret)
return ret;
ret = peb2466_write_buf(peb2466, PEB2466_TH_FILTER_P3(i), data + 17, 8);
if (ret)
return ret;
ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i),
PEB2466_CR0_TH | PEB2466_CR0_THSEL_MASK,
PEB2466_CR0_TH | PEB2466_CR0_THSEL(i));
if (ret)
return ret;
}
return 0;
}
static int peb2466_fw_parse_imr1filter(struct snd_soc_component *component,
u16 tag, u32 lng, const u8 *data)
{
struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component);
u8 mask;
int ret;
int i;
dev_info(component->dev, "fw IM/R1 filter: mask %x, %*phN\n", *data,
lng - 1, data + 1);
/*
* IMR1_FILTER TLV data:
* - @0 1 byte: Chan mask (bit set means related channel is concerned)
* - @1 8 bytes: IM/R1-Filter coefficients part1
* - @9 8 bytes: IM/R1-Filter coefficients part2
*/
mask = *data;
for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) {
if (!(mask & (1 << i)))
continue;
ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i),
PEB2466_CR0_IMR1, 0);
if (ret)
return ret;
ret = peb2466_write_buf(peb2466, PEB2466_IMR1_FILTER_P1(i), data + 1, 8);
if (ret)
return ret;
ret = peb2466_write_buf(peb2466, PEB2466_IMR1_FILTER_P2(i), data + 9, 8);
if (ret)
return ret;
ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i),
PEB2466_CR0_IMR1, PEB2466_CR0_IMR1);
if (ret)
return ret;
}
return 0;
}
static int peb2466_fw_parse_frxfilter(struct snd_soc_component *component,
u16 tag, u32 lng, const u8 *data)
{
struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component);
u8 mask;
int ret;
int i;
dev_info(component->dev, "fw FRX filter: mask %x, %*phN\n", *data,
lng - 1, data + 1);
/*
* FRX_FILTER TLV data:
* - @0 1 byte: Chan mask (bit set means related channel is concerned)
* - @1 8 bytes: FRX-Filter coefficients
*/
mask = *data;
for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) {
if (!(mask & (1 << i)))
continue;
ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i),
PEB2466_CR0_FRX, 0);
if (ret)
return ret;
ret = peb2466_write_buf(peb2466, PEB2466_FRX_FILTER(i), data + 1, 8);
if (ret)
return ret;
ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i),
PEB2466_CR0_FRX, PEB2466_CR0_FRX);
if (ret)
return ret;
}
return 0;
}
static int peb2466_fw_parse_frrfilter(struct snd_soc_component *component,
u16 tag, u32 lng, const u8 *data)
{
struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component);
u8 mask;
int ret;
int i;
dev_info(component->dev, "fw FRR filter: mask %x, %*phN\n", *data,
lng - 1, data + 1);
/*
* FRR_FILTER TLV data:
* - @0 1 byte: Chan mask (bit set means related channel is concerned)
* - @1 8 bytes: FRR-Filter coefficients
*/
mask = *data;
for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) {
if (!(mask & (1 << i)))
continue;
ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i),
PEB2466_CR0_FRR, 0);
if (ret)
return ret;
ret = peb2466_write_buf(peb2466, PEB2466_FRR_FILTER(i), data + 1, 8);
if (ret)
return ret;
ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i),
PEB2466_CR0_FRR, PEB2466_CR0_FRR);
if (ret)
return ret;
}
return 0;
}
static int peb2466_fw_parse_axfilter(struct snd_soc_component *component,
u16 tag, u32 lng, const u8 *data)
{
struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component);
u8 mask;
int ret;
int i;
dev_info(component->dev, "fw AX filter: mask %x, %*phN\n", *data,
lng - 1, data + 1);
/*
* AX_FILTER TLV data:
* - @0 1 byte: Chan mask (bit set means related channel is concerned)
* - @1 4 bytes: AX-Filter coefficients
*/
mask = *data;
for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) {
if (!(mask & (1 << i)))
continue;
ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i),
PEB2466_CR0_AX, 0);
if (ret)
return ret;
ret = peb2466_write_buf(peb2466, PEB2466_AX_FILTER(i), data + 1, 4);
if (ret)
return ret;
ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i),
PEB2466_CR0_AX, PEB2466_CR0_AX);
if (ret)
return ret;
}
return 0;
}
static int peb2466_fw_parse_arfilter(struct snd_soc_component *component,
u16 tag, u32 lng, const u8 *data)
{
struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component);
u8 mask;
int ret;
int i;
dev_info(component->dev, "fw AR filter: mask %x, %*phN\n", *data,
lng - 1, data + 1);
/*
* AR_FILTER TLV data:
* - @0 1 byte: Chan mask (bit set means related channel is concerned)
* - @1 4 bytes: AR-Filter coefficients
*/
mask = *data;
for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) {
if (!(mask & (1 << i)))
continue;
ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i),
PEB2466_CR0_AR, 0);
if (ret)
return ret;
ret = peb2466_write_buf(peb2466, PEB2466_AR_FILTER(i), data + 1, 4);
if (ret)
return ret;
ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i),
PEB2466_CR0_AR, PEB2466_CR0_AR);
if (ret)
return ret;
}
return 0;
}
static const char * const peb2466_ax_ctrl_names[] = {
"ADC0 Capture Volume",
"ADC1 Capture Volume",
"ADC2 Capture Volume",
"ADC3 Capture Volume",
};
static int peb2466_fw_parse_axtable(struct snd_soc_component *component,
u16 tag, u32 lng, const u8 *data)
{
struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component);
struct peb2466_lkup_ctrl *lkup_ctrl;
struct peb2466_lookup *lookup;
u8 (*table)[4];
u32 table_size;
u32 init_index;
s32 min_val;
s32 step;
u8 mask;
int ret;
int i;
/*
* AX_TABLE TLV data:
* - @0 1 byte: Chan mask (bit set means related channel is concerned)
* - @1 32bits signed: Min table value in centi dB (MinVal)
* ie -300 means -3.0 dB
* - @5 32bits signed: Step from on item to other item in centi dB (Step)
* ie 25 means 0.25 dB)
* - @9 32bits unsigned: Item index in the table to use for the initial
* value
* - @13 N*4 bytes: Table composed of 4 bytes items.
* Each item correspond to an AX filter value.
*
* The conversion from raw value item in the table to/from the value in
* dB is: Raw value at index i <-> (MinVal + i * Step) in centi dB.
*/
/* Check Lng and extract the table size. */
if (lng < 13 || ((lng - 13) % 4)) {
dev_err(component->dev, "fw AX table lng %u invalid\n", lng);
return -EINVAL;
}
table_size = lng - 13;
min_val = get_unaligned_be32(data + 1);
step = get_unaligned_be32(data + 5);
init_index = get_unaligned_be32(data + 9);
if (init_index >= (table_size / 4)) {
dev_err(component->dev, "fw AX table index %u out of table[%u]\n",
init_index, table_size / 4);
return -EINVAL;
}
dev_info(component->dev,
"fw AX table: mask %x, min %d, step %d, %u items, tbl[%u] %*phN\n",
*data, min_val, step, table_size / 4, init_index,
4, data + 13 + (init_index * 4));
BUILD_BUG_ON(sizeof(*table) != 4);
table = devm_kzalloc(&peb2466->spi->dev, table_size, GFP_KERNEL);
if (!table)
return -ENOMEM;
memcpy(table, data + 13, table_size);
mask = *data;
BUILD_BUG_ON(ARRAY_SIZE(peb2466_ax_ctrl_names) != ARRAY_SIZE(peb2466->ch));
for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) {
if (!(mask & (1 << i)))
continue;
lookup = &peb2466->ch[i].ax_lookup;
lookup->table = table;
lookup->count = table_size / 4;
ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i),
PEB2466_CR0_AX, 0);
if (ret)
return ret;
ret = peb2466_write_buf(peb2466, PEB2466_AX_FILTER(i),
lookup->table[init_index], 4);
if (ret)
return ret;
ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i),
PEB2466_CR0_AX, PEB2466_CR0_AX);
if (ret)
return ret;
lkup_ctrl = &peb2466->ch[i].ax_lkup_ctrl;
lkup_ctrl->lookup = lookup;
lkup_ctrl->reg = PEB2466_AX_FILTER(i);
lkup_ctrl->index = init_index;
ret = peb2466_add_lkup_ctrl(component, lkup_ctrl,
peb2466_ax_ctrl_names[i],
min_val, step);
if (ret)
return ret;
}
return 0;
}
static const char * const peb2466_ar_ctrl_names[] = {
"DAC0 Playback Volume",
"DAC1 Playback Volume",
"DAC2 Playback Volume",
"DAC3 Playback Volume",
};
static int peb2466_fw_parse_artable(struct snd_soc_component *component,
u16 tag, u32 lng, const u8 *data)
{
struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component);
struct peb2466_lkup_ctrl *lkup_ctrl;
struct peb2466_lookup *lookup;
u8 (*table)[4];
u32 table_size;
u32 init_index;
s32 min_val;
s32 step;
u8 mask;
int ret;
int i;
/*
* AR_TABLE TLV data:
* - @0 1 byte: Chan mask (bit set means related channel is concerned)
* - @1 32bits signed: Min table value in centi dB (MinVal)
* ie -300 means -3.0 dB
* - @5 32bits signed: Step from on item to other item in centi dB (Step)
* ie 25 means 0.25 dB)
* - @9 32bits unsigned: Item index in the table to use for the initial
* value
* - @13 N*4 bytes: Table composed of 4 bytes items.
* Each item correspond to an AR filter value.
*
* The conversion from raw value item in the table to/from the value in
* dB is: Raw value at index i <-> (MinVal + i * Step) in centi dB.
*/
/* Check Lng and extract the table size. */
if (lng < 13 || ((lng - 13) % 4)) {
dev_err(component->dev, "fw AR table lng %u invalid\n", lng);
return -EINVAL;
}
table_size = lng - 13;
min_val = get_unaligned_be32(data + 1);
step = get_unaligned_be32(data + 5);
init_index = get_unaligned_be32(data + 9);
if (init_index >= (table_size / 4)) {
dev_err(component->dev, "fw AR table index %u out of table[%u]\n",
init_index, table_size / 4);
return -EINVAL;
}
dev_info(component->dev,
"fw AR table: mask %x, min %d, step %d, %u items, tbl[%u] %*phN\n",
*data, min_val, step, table_size / 4, init_index,
4, data + 13 + (init_index * 4));
BUILD_BUG_ON(sizeof(*table) != 4);
table = devm_kzalloc(&peb2466->spi->dev, table_size, GFP_KERNEL);
if (!table)
return -ENOMEM;
memcpy(table, data + 13, table_size);
mask = *data;
BUILD_BUG_ON(ARRAY_SIZE(peb2466_ar_ctrl_names) != ARRAY_SIZE(peb2466->ch));
for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) {
if (!(mask & (1 << i)))
continue;
lookup = &peb2466->ch[i].ar_lookup;
lookup->table = table;
lookup->count = table_size / 4;
ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i),
PEB2466_CR0_AR, 0);
if (ret)
return ret;
ret = peb2466_write_buf(peb2466, PEB2466_AR_FILTER(i),
lookup->table[init_index], 4);
if (ret)
return ret;
ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i),
PEB2466_CR0_AR, PEB2466_CR0_AR);
if (ret)
return ret;
lkup_ctrl = &peb2466->ch[i].ar_lkup_ctrl;
lkup_ctrl->lookup = lookup;
lkup_ctrl->reg = PEB2466_AR_FILTER(i);
lkup_ctrl->index = init_index;
ret = peb2466_add_lkup_ctrl(component, lkup_ctrl,
peb2466_ar_ctrl_names[i],
min_val, step);
if (ret)
return ret;
}
return 0;
}
struct peb2466_fw_tag_def {
u16 tag;
u32 lng_min;
u32 lng_max;
int (*parse)(struct snd_soc_component *component,
u16 tag, u32 lng, const u8 *data);
};
#define PEB2466_TAG_DEF_LNG_EQ(__tag, __lng, __parse) { \
.tag = __tag, \
.lng_min = __lng, \
.lng_max = __lng, \
.parse = __parse, \
}
#define PEB2466_TAG_DEF_LNG_MIN(__tag, __lng_min, __parse) { \
.tag = __tag, \
.lng_min = __lng_min, \
.lng_max = U32_MAX, \
.parse = __parse, \
}
static const struct peb2466_fw_tag_def peb2466_fw_tag_defs[] = {
/* TH FILTER */
PEB2466_TAG_DEF_LNG_EQ(0x0001, 1 + 3 * 8, peb2466_fw_parse_thfilter),
/* IMR1 FILTER */
PEB2466_TAG_DEF_LNG_EQ(0x0002, 1 + 2 * 8, peb2466_fw_parse_imr1filter),
/* FRX FILTER */
PEB2466_TAG_DEF_LNG_EQ(0x0003, 1 + 8, peb2466_fw_parse_frxfilter),
/* FRR FILTER */
PEB2466_TAG_DEF_LNG_EQ(0x0004, 1 + 8, peb2466_fw_parse_frrfilter),
/* AX FILTER */
PEB2466_TAG_DEF_LNG_EQ(0x0005, 1 + 4, peb2466_fw_parse_axfilter),
/* AR FILTER */
PEB2466_TAG_DEF_LNG_EQ(0x0006, 1 + 4, peb2466_fw_parse_arfilter),
/* AX TABLE */
PEB2466_TAG_DEF_LNG_MIN(0x0105, 1 + 3 * 4, peb2466_fw_parse_axtable),
/* AR TABLE */
PEB2466_TAG_DEF_LNG_MIN(0x0106, 1 + 3 * 4, peb2466_fw_parse_artable),
};
static const struct peb2466_fw_tag_def *peb2466_fw_get_tag_def(u16 tag)
{
int i;
for (i = 0; i < ARRAY_SIZE(peb2466_fw_tag_defs); i++) {
if (peb2466_fw_tag_defs[i].tag == tag)
return &peb2466_fw_tag_defs[i];
}
return NULL;
}
static int peb2466_fw_parse(struct snd_soc_component *component,
const u8 *data, size_t size)
{
const struct peb2466_fw_tag_def *tag_def;
size_t left;
const u8 *buf;
u16 val16;
u16 tag;
u32 lng;
int ret;
/*
* Coefficients firmware binary structure (16bits and 32bits are
* big-endian values).
*
* @0, 16bits: Magic (0x2466)
* @2, 16bits: Version (0x0100 for version 1.0)
* @4, 2+4+N bytes: TLV block
* @4+(2+4+N) bytes: Next TLV block
* ...
*
* Detail of a TLV block:
* @0, 16bits: Tag
* @2, 32bits: Lng
* @6, lng bytes: Data
*
* The detail the Data for a given TLV Tag is provided in the related
* parser.
*/
left = size;
buf = data;
if (left < 4) {
dev_err(component->dev, "fw size %zu, exp at least 4\n", left);
return -EINVAL;
}
/* Check magic */
val16 = get_unaligned_be16(buf);
if (val16 != 0x2466) {
dev_err(component->dev, "fw magic 0x%04x exp 0x2466\n", val16);
return -EINVAL;
}
buf += 2;
left -= 2;
/* Check version */
val16 = get_unaligned_be16(buf);
if (val16 != 0x0100) {
dev_err(component->dev, "fw magic 0x%04x exp 0x0100\n", val16);
return -EINVAL;
}
buf += 2;
left -= 2;
while (left) {
if (left < 6) {
dev_err(component->dev, "fw %td/%zu left %zu, exp at least 6\n",
buf - data, size, left);
return -EINVAL;
}
/* Check tag and lng */
tag = get_unaligned_be16(buf);
lng = get_unaligned_be32(buf + 2);
tag_def = peb2466_fw_get_tag_def(tag);
if (!tag_def) {
dev_err(component->dev, "fw %td/%zu tag 0x%04x unknown\n",
buf - data, size, tag);
return -EINVAL;
}
if (lng < tag_def->lng_min || lng > tag_def->lng_max) {
dev_err(component->dev, "fw %td/%zu tag 0x%04x lng %u, exp [%u;%u]\n",
buf - data, size, tag, lng, tag_def->lng_min, tag_def->lng_max);
return -EINVAL;
}
buf += 6;
left -= 6;
if (left < lng) {
dev_err(component->dev, "fw %td/%zu tag 0x%04x lng %u, left %zu\n",
buf - data, size, tag, lng, left);
return -EINVAL;
}
/* TLV block is valid -> parse the data part */
ret = tag_def->parse(component, tag, lng, buf);
if (ret) {
dev_err(component->dev, "fw %td/%zu tag 0x%04x lng %u parse failed\n",
buf - data, size, tag, lng);
return ret;
}
buf += lng;
left -= lng;
}
return 0;
}
static int peb2466_load_coeffs(struct snd_soc_component *component, const char *fw_name)
{
const struct firmware *fw;
int ret;
ret = request_firmware(&fw, fw_name, component->dev);
if (ret)
return ret;
ret = peb2466_fw_parse(component, fw->data, fw->size);
release_firmware(fw);
return ret;
}
static int peb2466_component_probe(struct snd_soc_component *component)
{
struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component);
const char *firmware_name;
int ret;
/* reset peb2466 audio part */
ret = peb2466_reset_audio(peb2466);
if (ret)
return ret;
ret = of_property_read_string(peb2466->spi->dev.of_node,
"firmware-name", &firmware_name);
if (ret)
return (ret == -EINVAL) ? 0 : ret;
return peb2466_load_coeffs(component, firmware_name);
}
static const struct snd_soc_component_driver peb2466_component_driver = {
.probe = peb2466_component_probe,
.controls = peb2466_controls,
.num_controls = ARRAY_SIZE(peb2466_controls),
.dapm_widgets = peb2466_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(peb2466_dapm_widgets),
.dapm_routes = peb2466_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(peb2466_dapm_routes),
.endianness = 1,
};
/*
* The mapping used for the relationship between the gpio offset and the
* physical pin is the following:
*
* offset pin
* 0 SI1_0
* 1 SI1_1
* 2 SI2_0
* 3 SI2_1
* 4 SI3_0
* 5 SI3_1
* 6 SI4_0
* 7 SI4_1
* 8 SO1_0
* 9 SO1_1
* 10 SO2_0
* 11 SO2_1
* 12 SO3_0
* 13 SO3_1
* 14 SO4_0
* 15 SO4_1
* 16 SB1_0
* 17 SB1_1
* 18 SB2_0
* 19 SB2_1
* 20 SB3_0
* 21 SB3_1
* 22 SB4_0
* 23 SB4_1
* 24 SB1_2
* 25 SB2_2
* 26 SB3_2
* 27 SB4_2
*/
static int peb2466_chip_gpio_offset_to_data_regmask(unsigned int offset,
unsigned int *xr_reg,
unsigned int *mask)
{
if (offset < 16) {
/*
* SIx_{0,1} and SOx_{0,1}
* Read accesses read SIx_{0,1} values
* Write accesses write SOx_{0,1} values
*/
*xr_reg = PEB2466_XR0;
*mask = (1 << (offset % 8));
return 0;
}
if (offset < 24) {
/* SBx_{0,1} */
*xr_reg = PEB2466_XR1;
*mask = (1 << (offset - 16));
return 0;
}
if (offset < 28) {
/* SBx_2 */
*xr_reg = PEB2466_XR3;
*mask = (1 << (offset - 24 + 4));
return 0;
}
return -EINVAL;
}
static int peb2466_chip_gpio_offset_to_dir_regmask(unsigned int offset,
unsigned int *xr_reg,
unsigned int *mask)
{
if (offset < 16) {
/* Direction cannot be changed for these GPIOs */
return -EINVAL;
}
if (offset < 24) {
*xr_reg = PEB2466_XR2;
*mask = (1 << (offset - 16));
return 0;
}
if (offset < 28) {
*xr_reg = PEB2466_XR3;
*mask = (1 << (offset - 24));
return 0;
}
return -EINVAL;
}
static unsigned int *peb2466_chip_gpio_get_cache(struct peb2466 *peb2466,
unsigned int xr_reg)
{
unsigned int *cache;
switch (xr_reg) {
case PEB2466_XR0:
cache = &peb2466->gpio.cache.xr0;
break;
case PEB2466_XR1:
cache = &peb2466->gpio.cache.xr1;
break;
case PEB2466_XR2:
cache = &peb2466->gpio.cache.xr2;
break;
case PEB2466_XR3:
cache = &peb2466->gpio.cache.xr3;
break;
default:
cache = NULL;
break;
}
return cache;
}
static int peb2466_chip_gpio_update_bits(struct peb2466 *peb2466, unsigned int xr_reg,
unsigned int mask, unsigned int val)
{
unsigned int tmp;
unsigned int *cache;
int ret;
/*
* Read and write accesses use different peb2466 internal signals (input
* signals on reads and output signals on writes). regmap_update_bits
* cannot be used to read/modify/write the value.
* So, a specific cache value is used.
*/
mutex_lock(&peb2466->gpio.lock);
cache = peb2466_chip_gpio_get_cache(peb2466, xr_reg);
if (!cache) {
ret = -EINVAL;
goto end;
}
tmp = *cache;
tmp &= ~mask;
tmp |= val;
ret = regmap_write(peb2466->regmap, xr_reg, tmp);
if (ret)
goto end;
*cache = tmp;
ret = 0;
end:
mutex_unlock(&peb2466->gpio.lock);
return ret;
}
static void peb2466_chip_gpio_set(struct gpio_chip *c, unsigned int offset, int val)
{
struct peb2466 *peb2466 = gpiochip_get_data(c);
unsigned int xr_reg;
unsigned int mask;
int ret;
if (offset < 8) {
/*
* SIx_{0,1} signals cannot be set and writing the related
* register will change the SOx_{0,1} signals
*/
dev_warn(&peb2466->spi->dev, "cannot set gpio %d (read-only)\n",
offset);
return;
}
ret = peb2466_chip_gpio_offset_to_data_regmask(offset, &xr_reg, &mask);
if (ret) {
dev_err(&peb2466->spi->dev, "cannot set gpio %d (%d)\n",
offset, ret);
return;
}
ret = peb2466_chip_gpio_update_bits(peb2466, xr_reg, mask, val ? mask : 0);
if (ret) {
dev_err(&peb2466->spi->dev, "set gpio %d (0x%x, 0x%x) failed (%d)\n",
offset, xr_reg, mask, ret);
}
}
static int peb2466_chip_gpio_get(struct gpio_chip *c, unsigned int offset)
{
struct peb2466 *peb2466 = gpiochip_get_data(c);
bool use_cache = false;
unsigned int *cache;
unsigned int xr_reg;
unsigned int mask;
unsigned int val;
int ret;
if (offset >= 8 && offset < 16) {
/*
* SOx_{0,1} signals cannot be read. Reading the related
* register will read the SIx_{0,1} signals.
* Use the cache to get value;
*/
use_cache = true;
}
ret = peb2466_chip_gpio_offset_to_data_regmask(offset, &xr_reg, &mask);
if (ret) {
dev_err(&peb2466->spi->dev, "cannot get gpio %d (%d)\n",
offset, ret);
return -EINVAL;
}
if (use_cache) {
cache = peb2466_chip_gpio_get_cache(peb2466, xr_reg);
if (!cache)
return -EINVAL;
val = *cache;
} else {
ret = regmap_read(peb2466->regmap, xr_reg, &val);
if (ret) {
dev_err(&peb2466->spi->dev, "get gpio %d (0x%x, 0x%x) failed (%d)\n",
offset, xr_reg, mask, ret);
return ret;
}
}
return !!(val & mask);
}
static int peb2466_chip_get_direction(struct gpio_chip *c, unsigned int offset)
{
struct peb2466 *peb2466 = gpiochip_get_data(c);
unsigned int xr_reg;
unsigned int mask;
unsigned int val;
int ret;
if (offset < 8) {
/* SIx_{0,1} */
return GPIO_LINE_DIRECTION_IN;
}
if (offset < 16) {
/* SOx_{0,1} */
return GPIO_LINE_DIRECTION_OUT;
}
ret = peb2466_chip_gpio_offset_to_dir_regmask(offset, &xr_reg, &mask);
if (ret) {
dev_err(&peb2466->spi->dev, "cannot get gpio %d direction (%d)\n",
offset, ret);
return ret;
}
ret = regmap_read(peb2466->regmap, xr_reg, &val);
if (ret) {
dev_err(&peb2466->spi->dev, "get dir gpio %d (0x%x, 0x%x) failed (%d)\n",
offset, xr_reg, mask, ret);
return ret;
}
return val & mask ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
}
static int peb2466_chip_direction_input(struct gpio_chip *c, unsigned int offset)
{
struct peb2466 *peb2466 = gpiochip_get_data(c);
unsigned int xr_reg;
unsigned int mask;
int ret;
if (offset < 8) {
/* SIx_{0,1} */
return 0;
}
if (offset < 16) {
/* SOx_{0,1} */
return -EINVAL;
}
ret = peb2466_chip_gpio_offset_to_dir_regmask(offset, &xr_reg, &mask);
if (ret) {
dev_err(&peb2466->spi->dev, "cannot set gpio %d direction (%d)\n",
offset, ret);
return ret;
}
ret = peb2466_chip_gpio_update_bits(peb2466, xr_reg, mask, 0);
if (ret) {
dev_err(&peb2466->spi->dev, "Set dir in gpio %d (0x%x, 0x%x) failed (%d)\n",
offset, xr_reg, mask, ret);
return ret;
}
return 0;
}
static int peb2466_chip_direction_output(struct gpio_chip *c, unsigned int offset, int val)
{
struct peb2466 *peb2466 = gpiochip_get_data(c);
unsigned int xr_reg;
unsigned int mask;
int ret;
if (offset < 8) {
/* SIx_{0,1} */
return -EINVAL;
}
peb2466_chip_gpio_set(c, offset, val);
if (offset < 16) {
/* SOx_{0,1} */
return 0;
}
ret = peb2466_chip_gpio_offset_to_dir_regmask(offset, &xr_reg, &mask);
if (ret) {
dev_err(&peb2466->spi->dev, "cannot set gpio %d direction (%d)\n",
offset, ret);
return ret;
}
ret = peb2466_chip_gpio_update_bits(peb2466, xr_reg, mask, mask);
if (ret) {
dev_err(&peb2466->spi->dev, "Set dir in gpio %d (0x%x, 0x%x) failed (%d)\n",
offset, xr_reg, mask, ret);
return ret;
}
return 0;
}
static int peb2466_reset_gpio(struct peb2466 *peb2466)
{
static const struct reg_sequence reg_reset[] = {
/* Output pins at 0, input/output pins as input */
{ .reg = PEB2466_XR0, .def = 0 },
{ .reg = PEB2466_XR1, .def = 0 },
{ .reg = PEB2466_XR2, .def = 0 },
{ .reg = PEB2466_XR3, .def = 0 },
};
peb2466->gpio.cache.xr0 = 0;
peb2466->gpio.cache.xr1 = 0;
peb2466->gpio.cache.xr2 = 0;
peb2466->gpio.cache.xr3 = 0;
return regmap_multi_reg_write(peb2466->regmap, reg_reset, ARRAY_SIZE(reg_reset));
}
static int peb2466_gpio_init(struct peb2466 *peb2466)
{
int ret;
mutex_init(&peb2466->gpio.lock);
ret = peb2466_reset_gpio(peb2466);
if (ret)
return ret;
peb2466->gpio.gpio_chip.owner = THIS_MODULE;
peb2466->gpio.gpio_chip.label = dev_name(&peb2466->spi->dev);
peb2466->gpio.gpio_chip.parent = &peb2466->spi->dev;
peb2466->gpio.gpio_chip.base = -1;
peb2466->gpio.gpio_chip.ngpio = 28;
peb2466->gpio.gpio_chip.get_direction = peb2466_chip_get_direction;
peb2466->gpio.gpio_chip.direction_input = peb2466_chip_direction_input;
peb2466->gpio.gpio_chip.direction_output = peb2466_chip_direction_output;
peb2466->gpio.gpio_chip.get = peb2466_chip_gpio_get;
peb2466->gpio.gpio_chip.set = peb2466_chip_gpio_set;
peb2466->gpio.gpio_chip.can_sleep = true;
return devm_gpiochip_add_data(&peb2466->spi->dev, &peb2466->gpio.gpio_chip,
peb2466);
}
static int peb2466_spi_probe(struct spi_device *spi)
{
struct peb2466 *peb2466;
unsigned long mclk_rate;
int ret;
u8 xr5;
spi->bits_per_word = 8;
ret = spi_setup(spi);
if (ret < 0)
return ret;
peb2466 = devm_kzalloc(&spi->dev, sizeof(*peb2466), GFP_KERNEL);
if (!peb2466)
return -ENOMEM;
peb2466->spi = spi;
peb2466->regmap = devm_regmap_init(&peb2466->spi->dev, NULL, peb2466,
&peb2466_regmap_config);
if (IS_ERR(peb2466->regmap))
return PTR_ERR(peb2466->regmap);
peb2466->reset_gpio = devm_gpiod_get_optional(&peb2466->spi->dev,
"reset", GPIOD_OUT_LOW);
if (IS_ERR(peb2466->reset_gpio))
return PTR_ERR(peb2466->reset_gpio);
peb2466->mclk = devm_clk_get(&peb2466->spi->dev, "mclk");
if (IS_ERR(peb2466->mclk))
return PTR_ERR(peb2466->mclk);
ret = clk_prepare_enable(peb2466->mclk);
if (ret)
return ret;
if (peb2466->reset_gpio) {
gpiod_set_value_cansleep(peb2466->reset_gpio, 1);
udelay(4);
gpiod_set_value_cansleep(peb2466->reset_gpio, 0);
udelay(4);
}
spi_set_drvdata(spi, peb2466);
mclk_rate = clk_get_rate(peb2466->mclk);
switch (mclk_rate) {
case 1536000:
xr5 = PEB2466_XR5_MCLK_1536;
break;
case 2048000:
xr5 = PEB2466_XR5_MCLK_2048;
break;
case 4096000:
xr5 = PEB2466_XR5_MCLK_4096;
break;
case 8192000:
xr5 = PEB2466_XR5_MCLK_8192;
break;
default:
dev_err(&peb2466->spi->dev, "Unsupported clock rate %lu\n",
mclk_rate);
ret = -EINVAL;
goto failed;
}
ret = regmap_write(peb2466->regmap, PEB2466_XR5, xr5);
if (ret) {
dev_err(&peb2466->spi->dev, "Setting MCLK failed (%d)\n", ret);
goto failed;
}
ret = devm_snd_soc_register_component(&spi->dev, &peb2466_component_driver,
&peb2466_dai_driver, 1);
if (ret)
goto failed;
if (IS_ENABLED(CONFIG_GPIOLIB)) {
ret = peb2466_gpio_init(peb2466);
if (ret)
goto failed;
}
return 0;
failed:
clk_disable_unprepare(peb2466->mclk);
return ret;
}
static void peb2466_spi_remove(struct spi_device *spi)
{
struct peb2466 *peb2466 = spi_get_drvdata(spi);
clk_disable_unprepare(peb2466->mclk);
}
static const struct of_device_id peb2466_of_match[] = {
{ .compatible = "infineon,peb2466", },
{ }
};
MODULE_DEVICE_TABLE(of, peb2466_of_match);
static const struct spi_device_id peb2466_id_table[] = {
{ "peb2466", 0 },
{ }
};
MODULE_DEVICE_TABLE(spi, peb2466_id_table);
static struct spi_driver peb2466_spi_driver = {
.driver = {
.name = "peb2466",
.of_match_table = peb2466_of_match,
},
.id_table = peb2466_id_table,
.probe = peb2466_spi_probe,
.remove = peb2466_spi_remove,
};
module_spi_driver(peb2466_spi_driver);
MODULE_AUTHOR("Herve Codina <[email protected]>");
MODULE_DESCRIPTION("PEB2466 ALSA SoC driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/peb2466.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm5100-tables.c -- WM5100 ALSA SoC Audio driver data
*
* Copyright 2011-2 Wolfson Microelectronics plc
*
* Author: Mark Brown <[email protected]>
*/
#include "wm5100.h"
bool wm5100_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM5100_SOFTWARE_RESET:
case WM5100_DEVICE_REVISION:
case WM5100_FX_CTRL:
case WM5100_INTERRUPT_STATUS_1:
case WM5100_INTERRUPT_STATUS_2:
case WM5100_INTERRUPT_STATUS_3:
case WM5100_INTERRUPT_STATUS_4:
case WM5100_INTERRUPT_RAW_STATUS_2:
case WM5100_INTERRUPT_RAW_STATUS_3:
case WM5100_INTERRUPT_RAW_STATUS_4:
case WM5100_OUTPUT_STATUS_1:
case WM5100_OUTPUT_STATUS_2:
case WM5100_INPUT_ENABLES_STATUS:
case WM5100_MIC_DETECT_3:
return true;
default:
if ((reg >= WM5100_DSP1_PM_0 && reg <= WM5100_DSP1_PM_1535) ||
(reg >= WM5100_DSP1_ZM_0 && reg <= WM5100_DSP1_ZM_2047) ||
(reg >= WM5100_DSP1_DM_0 && reg <= WM5100_DSP1_DM_511) ||
(reg >= WM5100_DSP2_PM_0 && reg <= WM5100_DSP2_PM_1535) ||
(reg >= WM5100_DSP2_ZM_0 && reg <= WM5100_DSP2_ZM_2047) ||
(reg >= WM5100_DSP2_DM_0 && reg <= WM5100_DSP2_DM_511) ||
(reg >= WM5100_DSP3_PM_0 && reg <= WM5100_DSP3_PM_1535) ||
(reg >= WM5100_DSP3_ZM_0 && reg <= WM5100_DSP3_ZM_2047) ||
(reg >= WM5100_DSP3_DM_0 && reg <= WM5100_DSP3_DM_511))
return true;
else
return false;
}
}
bool wm5100_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM5100_SOFTWARE_RESET:
case WM5100_DEVICE_REVISION:
case WM5100_CTRL_IF_1:
case WM5100_TONE_GENERATOR_1:
case WM5100_PWM_DRIVE_1:
case WM5100_PWM_DRIVE_2:
case WM5100_PWM_DRIVE_3:
case WM5100_CLOCKING_1:
case WM5100_CLOCKING_3:
case WM5100_CLOCKING_4:
case WM5100_CLOCKING_5:
case WM5100_CLOCKING_6:
case WM5100_CLOCKING_7:
case WM5100_CLOCKING_8:
case WM5100_ASRC_ENABLE:
case WM5100_ASRC_STATUS:
case WM5100_ASRC_RATE1:
case WM5100_ISRC_1_CTRL_1:
case WM5100_ISRC_1_CTRL_2:
case WM5100_ISRC_2_CTRL1:
case WM5100_ISRC_2_CTRL_2:
case WM5100_FLL1_CONTROL_1:
case WM5100_FLL1_CONTROL_2:
case WM5100_FLL1_CONTROL_3:
case WM5100_FLL1_CONTROL_5:
case WM5100_FLL1_CONTROL_6:
case WM5100_FLL1_EFS_1:
case WM5100_FLL2_CONTROL_1:
case WM5100_FLL2_CONTROL_2:
case WM5100_FLL2_CONTROL_3:
case WM5100_FLL2_CONTROL_5:
case WM5100_FLL2_CONTROL_6:
case WM5100_FLL2_EFS_1:
case WM5100_MIC_CHARGE_PUMP_1:
case WM5100_MIC_CHARGE_PUMP_2:
case WM5100_HP_CHARGE_PUMP_1:
case WM5100_LDO1_CONTROL:
case WM5100_MIC_BIAS_CTRL_1:
case WM5100_MIC_BIAS_CTRL_2:
case WM5100_MIC_BIAS_CTRL_3:
case WM5100_ACCESSORY_DETECT_MODE_1:
case WM5100_HEADPHONE_DETECT_1:
case WM5100_HEADPHONE_DETECT_2:
case WM5100_MIC_DETECT_1:
case WM5100_MIC_DETECT_2:
case WM5100_MIC_DETECT_3:
case WM5100_MISC_CONTROL:
case WM5100_INPUT_ENABLES:
case WM5100_INPUT_ENABLES_STATUS:
case WM5100_IN1L_CONTROL:
case WM5100_IN1R_CONTROL:
case WM5100_IN2L_CONTROL:
case WM5100_IN2R_CONTROL:
case WM5100_IN3L_CONTROL:
case WM5100_IN3R_CONTROL:
case WM5100_IN4L_CONTROL:
case WM5100_IN4R_CONTROL:
case WM5100_RXANC_SRC:
case WM5100_INPUT_VOLUME_RAMP:
case WM5100_ADC_DIGITAL_VOLUME_1L:
case WM5100_ADC_DIGITAL_VOLUME_1R:
case WM5100_ADC_DIGITAL_VOLUME_2L:
case WM5100_ADC_DIGITAL_VOLUME_2R:
case WM5100_ADC_DIGITAL_VOLUME_3L:
case WM5100_ADC_DIGITAL_VOLUME_3R:
case WM5100_ADC_DIGITAL_VOLUME_4L:
case WM5100_ADC_DIGITAL_VOLUME_4R:
case WM5100_OUTPUT_ENABLES_2:
case WM5100_OUTPUT_STATUS_1:
case WM5100_OUTPUT_STATUS_2:
case WM5100_CHANNEL_ENABLES_1:
case WM5100_OUT_VOLUME_1L:
case WM5100_OUT_VOLUME_1R:
case WM5100_DAC_VOLUME_LIMIT_1L:
case WM5100_DAC_VOLUME_LIMIT_1R:
case WM5100_OUT_VOLUME_2L:
case WM5100_OUT_VOLUME_2R:
case WM5100_DAC_VOLUME_LIMIT_2L:
case WM5100_DAC_VOLUME_LIMIT_2R:
case WM5100_OUT_VOLUME_3L:
case WM5100_OUT_VOLUME_3R:
case WM5100_DAC_VOLUME_LIMIT_3L:
case WM5100_DAC_VOLUME_LIMIT_3R:
case WM5100_OUT_VOLUME_4L:
case WM5100_OUT_VOLUME_4R:
case WM5100_DAC_VOLUME_LIMIT_5L:
case WM5100_DAC_VOLUME_LIMIT_5R:
case WM5100_DAC_VOLUME_LIMIT_6L:
case WM5100_DAC_VOLUME_LIMIT_6R:
case WM5100_DAC_AEC_CONTROL_1:
case WM5100_OUTPUT_VOLUME_RAMP:
case WM5100_DAC_DIGITAL_VOLUME_1L:
case WM5100_DAC_DIGITAL_VOLUME_1R:
case WM5100_DAC_DIGITAL_VOLUME_2L:
case WM5100_DAC_DIGITAL_VOLUME_2R:
case WM5100_DAC_DIGITAL_VOLUME_3L:
case WM5100_DAC_DIGITAL_VOLUME_3R:
case WM5100_DAC_DIGITAL_VOLUME_4L:
case WM5100_DAC_DIGITAL_VOLUME_4R:
case WM5100_DAC_DIGITAL_VOLUME_5L:
case WM5100_DAC_DIGITAL_VOLUME_5R:
case WM5100_DAC_DIGITAL_VOLUME_6L:
case WM5100_DAC_DIGITAL_VOLUME_6R:
case WM5100_PDM_SPK1_CTRL_1:
case WM5100_PDM_SPK1_CTRL_2:
case WM5100_PDM_SPK2_CTRL_1:
case WM5100_PDM_SPK2_CTRL_2:
case WM5100_AUDIO_IF_1_1:
case WM5100_AUDIO_IF_1_2:
case WM5100_AUDIO_IF_1_3:
case WM5100_AUDIO_IF_1_4:
case WM5100_AUDIO_IF_1_5:
case WM5100_AUDIO_IF_1_6:
case WM5100_AUDIO_IF_1_7:
case WM5100_AUDIO_IF_1_8:
case WM5100_AUDIO_IF_1_9:
case WM5100_AUDIO_IF_1_10:
case WM5100_AUDIO_IF_1_11:
case WM5100_AUDIO_IF_1_12:
case WM5100_AUDIO_IF_1_13:
case WM5100_AUDIO_IF_1_14:
case WM5100_AUDIO_IF_1_15:
case WM5100_AUDIO_IF_1_16:
case WM5100_AUDIO_IF_1_17:
case WM5100_AUDIO_IF_1_18:
case WM5100_AUDIO_IF_1_19:
case WM5100_AUDIO_IF_1_20:
case WM5100_AUDIO_IF_1_21:
case WM5100_AUDIO_IF_1_22:
case WM5100_AUDIO_IF_1_23:
case WM5100_AUDIO_IF_1_24:
case WM5100_AUDIO_IF_1_25:
case WM5100_AUDIO_IF_1_26:
case WM5100_AUDIO_IF_1_27:
case WM5100_AUDIO_IF_2_1:
case WM5100_AUDIO_IF_2_2:
case WM5100_AUDIO_IF_2_3:
case WM5100_AUDIO_IF_2_4:
case WM5100_AUDIO_IF_2_5:
case WM5100_AUDIO_IF_2_6:
case WM5100_AUDIO_IF_2_7:
case WM5100_AUDIO_IF_2_8:
case WM5100_AUDIO_IF_2_9:
case WM5100_AUDIO_IF_2_10:
case WM5100_AUDIO_IF_2_11:
case WM5100_AUDIO_IF_2_18:
case WM5100_AUDIO_IF_2_19:
case WM5100_AUDIO_IF_2_26:
case WM5100_AUDIO_IF_2_27:
case WM5100_AUDIO_IF_3_1:
case WM5100_AUDIO_IF_3_2:
case WM5100_AUDIO_IF_3_3:
case WM5100_AUDIO_IF_3_4:
case WM5100_AUDIO_IF_3_5:
case WM5100_AUDIO_IF_3_6:
case WM5100_AUDIO_IF_3_7:
case WM5100_AUDIO_IF_3_8:
case WM5100_AUDIO_IF_3_9:
case WM5100_AUDIO_IF_3_10:
case WM5100_AUDIO_IF_3_11:
case WM5100_AUDIO_IF_3_18:
case WM5100_AUDIO_IF_3_19:
case WM5100_AUDIO_IF_3_26:
case WM5100_AUDIO_IF_3_27:
case WM5100_PWM1MIX_INPUT_1_SOURCE:
case WM5100_PWM1MIX_INPUT_1_VOLUME:
case WM5100_PWM1MIX_INPUT_2_SOURCE:
case WM5100_PWM1MIX_INPUT_2_VOLUME:
case WM5100_PWM1MIX_INPUT_3_SOURCE:
case WM5100_PWM1MIX_INPUT_3_VOLUME:
case WM5100_PWM1MIX_INPUT_4_SOURCE:
case WM5100_PWM1MIX_INPUT_4_VOLUME:
case WM5100_PWM2MIX_INPUT_1_SOURCE:
case WM5100_PWM2MIX_INPUT_1_VOLUME:
case WM5100_PWM2MIX_INPUT_2_SOURCE:
case WM5100_PWM2MIX_INPUT_2_VOLUME:
case WM5100_PWM2MIX_INPUT_3_SOURCE:
case WM5100_PWM2MIX_INPUT_3_VOLUME:
case WM5100_PWM2MIX_INPUT_4_SOURCE:
case WM5100_PWM2MIX_INPUT_4_VOLUME:
case WM5100_OUT1LMIX_INPUT_1_SOURCE:
case WM5100_OUT1LMIX_INPUT_1_VOLUME:
case WM5100_OUT1LMIX_INPUT_2_SOURCE:
case WM5100_OUT1LMIX_INPUT_2_VOLUME:
case WM5100_OUT1LMIX_INPUT_3_SOURCE:
case WM5100_OUT1LMIX_INPUT_3_VOLUME:
case WM5100_OUT1LMIX_INPUT_4_SOURCE:
case WM5100_OUT1LMIX_INPUT_4_VOLUME:
case WM5100_OUT1RMIX_INPUT_1_SOURCE:
case WM5100_OUT1RMIX_INPUT_1_VOLUME:
case WM5100_OUT1RMIX_INPUT_2_SOURCE:
case WM5100_OUT1RMIX_INPUT_2_VOLUME:
case WM5100_OUT1RMIX_INPUT_3_SOURCE:
case WM5100_OUT1RMIX_INPUT_3_VOLUME:
case WM5100_OUT1RMIX_INPUT_4_SOURCE:
case WM5100_OUT1RMIX_INPUT_4_VOLUME:
case WM5100_OUT2LMIX_INPUT_1_SOURCE:
case WM5100_OUT2LMIX_INPUT_1_VOLUME:
case WM5100_OUT2LMIX_INPUT_2_SOURCE:
case WM5100_OUT2LMIX_INPUT_2_VOLUME:
case WM5100_OUT2LMIX_INPUT_3_SOURCE:
case WM5100_OUT2LMIX_INPUT_3_VOLUME:
case WM5100_OUT2LMIX_INPUT_4_SOURCE:
case WM5100_OUT2LMIX_INPUT_4_VOLUME:
case WM5100_OUT2RMIX_INPUT_1_SOURCE:
case WM5100_OUT2RMIX_INPUT_1_VOLUME:
case WM5100_OUT2RMIX_INPUT_2_SOURCE:
case WM5100_OUT2RMIX_INPUT_2_VOLUME:
case WM5100_OUT2RMIX_INPUT_3_SOURCE:
case WM5100_OUT2RMIX_INPUT_3_VOLUME:
case WM5100_OUT2RMIX_INPUT_4_SOURCE:
case WM5100_OUT2RMIX_INPUT_4_VOLUME:
case WM5100_OUT3LMIX_INPUT_1_SOURCE:
case WM5100_OUT3LMIX_INPUT_1_VOLUME:
case WM5100_OUT3LMIX_INPUT_2_SOURCE:
case WM5100_OUT3LMIX_INPUT_2_VOLUME:
case WM5100_OUT3LMIX_INPUT_3_SOURCE:
case WM5100_OUT3LMIX_INPUT_3_VOLUME:
case WM5100_OUT3LMIX_INPUT_4_SOURCE:
case WM5100_OUT3LMIX_INPUT_4_VOLUME:
case WM5100_OUT3RMIX_INPUT_1_SOURCE:
case WM5100_OUT3RMIX_INPUT_1_VOLUME:
case WM5100_OUT3RMIX_INPUT_2_SOURCE:
case WM5100_OUT3RMIX_INPUT_2_VOLUME:
case WM5100_OUT3RMIX_INPUT_3_SOURCE:
case WM5100_OUT3RMIX_INPUT_3_VOLUME:
case WM5100_OUT3RMIX_INPUT_4_SOURCE:
case WM5100_OUT3RMIX_INPUT_4_VOLUME:
case WM5100_OUT4LMIX_INPUT_1_SOURCE:
case WM5100_OUT4LMIX_INPUT_1_VOLUME:
case WM5100_OUT4LMIX_INPUT_2_SOURCE:
case WM5100_OUT4LMIX_INPUT_2_VOLUME:
case WM5100_OUT4LMIX_INPUT_3_SOURCE:
case WM5100_OUT4LMIX_INPUT_3_VOLUME:
case WM5100_OUT4LMIX_INPUT_4_SOURCE:
case WM5100_OUT4LMIX_INPUT_4_VOLUME:
case WM5100_OUT4RMIX_INPUT_1_SOURCE:
case WM5100_OUT4RMIX_INPUT_1_VOLUME:
case WM5100_OUT4RMIX_INPUT_2_SOURCE:
case WM5100_OUT4RMIX_INPUT_2_VOLUME:
case WM5100_OUT4RMIX_INPUT_3_SOURCE:
case WM5100_OUT4RMIX_INPUT_3_VOLUME:
case WM5100_OUT4RMIX_INPUT_4_SOURCE:
case WM5100_OUT4RMIX_INPUT_4_VOLUME:
case WM5100_OUT5LMIX_INPUT_1_SOURCE:
case WM5100_OUT5LMIX_INPUT_1_VOLUME:
case WM5100_OUT5LMIX_INPUT_2_SOURCE:
case WM5100_OUT5LMIX_INPUT_2_VOLUME:
case WM5100_OUT5LMIX_INPUT_3_SOURCE:
case WM5100_OUT5LMIX_INPUT_3_VOLUME:
case WM5100_OUT5LMIX_INPUT_4_SOURCE:
case WM5100_OUT5LMIX_INPUT_4_VOLUME:
case WM5100_OUT5RMIX_INPUT_1_SOURCE:
case WM5100_OUT5RMIX_INPUT_1_VOLUME:
case WM5100_OUT5RMIX_INPUT_2_SOURCE:
case WM5100_OUT5RMIX_INPUT_2_VOLUME:
case WM5100_OUT5RMIX_INPUT_3_SOURCE:
case WM5100_OUT5RMIX_INPUT_3_VOLUME:
case WM5100_OUT5RMIX_INPUT_4_SOURCE:
case WM5100_OUT5RMIX_INPUT_4_VOLUME:
case WM5100_OUT6LMIX_INPUT_1_SOURCE:
case WM5100_OUT6LMIX_INPUT_1_VOLUME:
case WM5100_OUT6LMIX_INPUT_2_SOURCE:
case WM5100_OUT6LMIX_INPUT_2_VOLUME:
case WM5100_OUT6LMIX_INPUT_3_SOURCE:
case WM5100_OUT6LMIX_INPUT_3_VOLUME:
case WM5100_OUT6LMIX_INPUT_4_SOURCE:
case WM5100_OUT6LMIX_INPUT_4_VOLUME:
case WM5100_OUT6RMIX_INPUT_1_SOURCE:
case WM5100_OUT6RMIX_INPUT_1_VOLUME:
case WM5100_OUT6RMIX_INPUT_2_SOURCE:
case WM5100_OUT6RMIX_INPUT_2_VOLUME:
case WM5100_OUT6RMIX_INPUT_3_SOURCE:
case WM5100_OUT6RMIX_INPUT_3_VOLUME:
case WM5100_OUT6RMIX_INPUT_4_SOURCE:
case WM5100_OUT6RMIX_INPUT_4_VOLUME:
case WM5100_AIF1TX1MIX_INPUT_1_SOURCE:
case WM5100_AIF1TX1MIX_INPUT_1_VOLUME:
case WM5100_AIF1TX1MIX_INPUT_2_SOURCE:
case WM5100_AIF1TX1MIX_INPUT_2_VOLUME:
case WM5100_AIF1TX1MIX_INPUT_3_SOURCE:
case WM5100_AIF1TX1MIX_INPUT_3_VOLUME:
case WM5100_AIF1TX1MIX_INPUT_4_SOURCE:
case WM5100_AIF1TX1MIX_INPUT_4_VOLUME:
case WM5100_AIF1TX2MIX_INPUT_1_SOURCE:
case WM5100_AIF1TX2MIX_INPUT_1_VOLUME:
case WM5100_AIF1TX2MIX_INPUT_2_SOURCE:
case WM5100_AIF1TX2MIX_INPUT_2_VOLUME:
case WM5100_AIF1TX2MIX_INPUT_3_SOURCE:
case WM5100_AIF1TX2MIX_INPUT_3_VOLUME:
case WM5100_AIF1TX2MIX_INPUT_4_SOURCE:
case WM5100_AIF1TX2MIX_INPUT_4_VOLUME:
case WM5100_AIF1TX3MIX_INPUT_1_SOURCE:
case WM5100_AIF1TX3MIX_INPUT_1_VOLUME:
case WM5100_AIF1TX3MIX_INPUT_2_SOURCE:
case WM5100_AIF1TX3MIX_INPUT_2_VOLUME:
case WM5100_AIF1TX3MIX_INPUT_3_SOURCE:
case WM5100_AIF1TX3MIX_INPUT_3_VOLUME:
case WM5100_AIF1TX3MIX_INPUT_4_SOURCE:
case WM5100_AIF1TX3MIX_INPUT_4_VOLUME:
case WM5100_AIF1TX4MIX_INPUT_1_SOURCE:
case WM5100_AIF1TX4MIX_INPUT_1_VOLUME:
case WM5100_AIF1TX4MIX_INPUT_2_SOURCE:
case WM5100_AIF1TX4MIX_INPUT_2_VOLUME:
case WM5100_AIF1TX4MIX_INPUT_3_SOURCE:
case WM5100_AIF1TX4MIX_INPUT_3_VOLUME:
case WM5100_AIF1TX4MIX_INPUT_4_SOURCE:
case WM5100_AIF1TX4MIX_INPUT_4_VOLUME:
case WM5100_AIF1TX5MIX_INPUT_1_SOURCE:
case WM5100_AIF1TX5MIX_INPUT_1_VOLUME:
case WM5100_AIF1TX5MIX_INPUT_2_SOURCE:
case WM5100_AIF1TX5MIX_INPUT_2_VOLUME:
case WM5100_AIF1TX5MIX_INPUT_3_SOURCE:
case WM5100_AIF1TX5MIX_INPUT_3_VOLUME:
case WM5100_AIF1TX5MIX_INPUT_4_SOURCE:
case WM5100_AIF1TX5MIX_INPUT_4_VOLUME:
case WM5100_AIF1TX6MIX_INPUT_1_SOURCE:
case WM5100_AIF1TX6MIX_INPUT_1_VOLUME:
case WM5100_AIF1TX6MIX_INPUT_2_SOURCE:
case WM5100_AIF1TX6MIX_INPUT_2_VOLUME:
case WM5100_AIF1TX6MIX_INPUT_3_SOURCE:
case WM5100_AIF1TX6MIX_INPUT_3_VOLUME:
case WM5100_AIF1TX6MIX_INPUT_4_SOURCE:
case WM5100_AIF1TX6MIX_INPUT_4_VOLUME:
case WM5100_AIF1TX7MIX_INPUT_1_SOURCE:
case WM5100_AIF1TX7MIX_INPUT_1_VOLUME:
case WM5100_AIF1TX7MIX_INPUT_2_SOURCE:
case WM5100_AIF1TX7MIX_INPUT_2_VOLUME:
case WM5100_AIF1TX7MIX_INPUT_3_SOURCE:
case WM5100_AIF1TX7MIX_INPUT_3_VOLUME:
case WM5100_AIF1TX7MIX_INPUT_4_SOURCE:
case WM5100_AIF1TX7MIX_INPUT_4_VOLUME:
case WM5100_AIF1TX8MIX_INPUT_1_SOURCE:
case WM5100_AIF1TX8MIX_INPUT_1_VOLUME:
case WM5100_AIF1TX8MIX_INPUT_2_SOURCE:
case WM5100_AIF1TX8MIX_INPUT_2_VOLUME:
case WM5100_AIF1TX8MIX_INPUT_3_SOURCE:
case WM5100_AIF1TX8MIX_INPUT_3_VOLUME:
case WM5100_AIF1TX8MIX_INPUT_4_SOURCE:
case WM5100_AIF1TX8MIX_INPUT_4_VOLUME:
case WM5100_AIF2TX1MIX_INPUT_1_SOURCE:
case WM5100_AIF2TX1MIX_INPUT_1_VOLUME:
case WM5100_AIF2TX1MIX_INPUT_2_SOURCE:
case WM5100_AIF2TX1MIX_INPUT_2_VOLUME:
case WM5100_AIF2TX1MIX_INPUT_3_SOURCE:
case WM5100_AIF2TX1MIX_INPUT_3_VOLUME:
case WM5100_AIF2TX1MIX_INPUT_4_SOURCE:
case WM5100_AIF2TX1MIX_INPUT_4_VOLUME:
case WM5100_AIF2TX2MIX_INPUT_1_SOURCE:
case WM5100_AIF2TX2MIX_INPUT_1_VOLUME:
case WM5100_AIF2TX2MIX_INPUT_2_SOURCE:
case WM5100_AIF2TX2MIX_INPUT_2_VOLUME:
case WM5100_AIF2TX2MIX_INPUT_3_SOURCE:
case WM5100_AIF2TX2MIX_INPUT_3_VOLUME:
case WM5100_AIF2TX2MIX_INPUT_4_SOURCE:
case WM5100_AIF2TX2MIX_INPUT_4_VOLUME:
case WM5100_AIF3TX1MIX_INPUT_1_SOURCE:
case WM5100_AIF3TX1MIX_INPUT_1_VOLUME:
case WM5100_AIF3TX1MIX_INPUT_2_SOURCE:
case WM5100_AIF3TX1MIX_INPUT_2_VOLUME:
case WM5100_AIF3TX1MIX_INPUT_3_SOURCE:
case WM5100_AIF3TX1MIX_INPUT_3_VOLUME:
case WM5100_AIF3TX1MIX_INPUT_4_SOURCE:
case WM5100_AIF3TX1MIX_INPUT_4_VOLUME:
case WM5100_AIF3TX2MIX_INPUT_1_SOURCE:
case WM5100_AIF3TX2MIX_INPUT_1_VOLUME:
case WM5100_AIF3TX2MIX_INPUT_2_SOURCE:
case WM5100_AIF3TX2MIX_INPUT_2_VOLUME:
case WM5100_AIF3TX2MIX_INPUT_3_SOURCE:
case WM5100_AIF3TX2MIX_INPUT_3_VOLUME:
case WM5100_AIF3TX2MIX_INPUT_4_SOURCE:
case WM5100_AIF3TX2MIX_INPUT_4_VOLUME:
case WM5100_EQ1MIX_INPUT_1_SOURCE:
case WM5100_EQ1MIX_INPUT_1_VOLUME:
case WM5100_EQ1MIX_INPUT_2_SOURCE:
case WM5100_EQ1MIX_INPUT_2_VOLUME:
case WM5100_EQ1MIX_INPUT_3_SOURCE:
case WM5100_EQ1MIX_INPUT_3_VOLUME:
case WM5100_EQ1MIX_INPUT_4_SOURCE:
case WM5100_EQ1MIX_INPUT_4_VOLUME:
case WM5100_EQ2MIX_INPUT_1_SOURCE:
case WM5100_EQ2MIX_INPUT_1_VOLUME:
case WM5100_EQ2MIX_INPUT_2_SOURCE:
case WM5100_EQ2MIX_INPUT_2_VOLUME:
case WM5100_EQ2MIX_INPUT_3_SOURCE:
case WM5100_EQ2MIX_INPUT_3_VOLUME:
case WM5100_EQ2MIX_INPUT_4_SOURCE:
case WM5100_EQ2MIX_INPUT_4_VOLUME:
case WM5100_EQ3MIX_INPUT_1_SOURCE:
case WM5100_EQ3MIX_INPUT_1_VOLUME:
case WM5100_EQ3MIX_INPUT_2_SOURCE:
case WM5100_EQ3MIX_INPUT_2_VOLUME:
case WM5100_EQ3MIX_INPUT_3_SOURCE:
case WM5100_EQ3MIX_INPUT_3_VOLUME:
case WM5100_EQ3MIX_INPUT_4_SOURCE:
case WM5100_EQ3MIX_INPUT_4_VOLUME:
case WM5100_EQ4MIX_INPUT_1_SOURCE:
case WM5100_EQ4MIX_INPUT_1_VOLUME:
case WM5100_EQ4MIX_INPUT_2_SOURCE:
case WM5100_EQ4MIX_INPUT_2_VOLUME:
case WM5100_EQ4MIX_INPUT_3_SOURCE:
case WM5100_EQ4MIX_INPUT_3_VOLUME:
case WM5100_EQ4MIX_INPUT_4_SOURCE:
case WM5100_EQ4MIX_INPUT_4_VOLUME:
case WM5100_DRC1LMIX_INPUT_1_SOURCE:
case WM5100_DRC1LMIX_INPUT_1_VOLUME:
case WM5100_DRC1LMIX_INPUT_2_SOURCE:
case WM5100_DRC1LMIX_INPUT_2_VOLUME:
case WM5100_DRC1LMIX_INPUT_3_SOURCE:
case WM5100_DRC1LMIX_INPUT_3_VOLUME:
case WM5100_DRC1LMIX_INPUT_4_SOURCE:
case WM5100_DRC1LMIX_INPUT_4_VOLUME:
case WM5100_DRC1RMIX_INPUT_1_SOURCE:
case WM5100_DRC1RMIX_INPUT_1_VOLUME:
case WM5100_DRC1RMIX_INPUT_2_SOURCE:
case WM5100_DRC1RMIX_INPUT_2_VOLUME:
case WM5100_DRC1RMIX_INPUT_3_SOURCE:
case WM5100_DRC1RMIX_INPUT_3_VOLUME:
case WM5100_DRC1RMIX_INPUT_4_SOURCE:
case WM5100_DRC1RMIX_INPUT_4_VOLUME:
case WM5100_HPLP1MIX_INPUT_1_SOURCE:
case WM5100_HPLP1MIX_INPUT_1_VOLUME:
case WM5100_HPLP1MIX_INPUT_2_SOURCE:
case WM5100_HPLP1MIX_INPUT_2_VOLUME:
case WM5100_HPLP1MIX_INPUT_3_SOURCE:
case WM5100_HPLP1MIX_INPUT_3_VOLUME:
case WM5100_HPLP1MIX_INPUT_4_SOURCE:
case WM5100_HPLP1MIX_INPUT_4_VOLUME:
case WM5100_HPLP2MIX_INPUT_1_SOURCE:
case WM5100_HPLP2MIX_INPUT_1_VOLUME:
case WM5100_HPLP2MIX_INPUT_2_SOURCE:
case WM5100_HPLP2MIX_INPUT_2_VOLUME:
case WM5100_HPLP2MIX_INPUT_3_SOURCE:
case WM5100_HPLP2MIX_INPUT_3_VOLUME:
case WM5100_HPLP2MIX_INPUT_4_SOURCE:
case WM5100_HPLP2MIX_INPUT_4_VOLUME:
case WM5100_HPLP3MIX_INPUT_1_SOURCE:
case WM5100_HPLP3MIX_INPUT_1_VOLUME:
case WM5100_HPLP3MIX_INPUT_2_SOURCE:
case WM5100_HPLP3MIX_INPUT_2_VOLUME:
case WM5100_HPLP3MIX_INPUT_3_SOURCE:
case WM5100_HPLP3MIX_INPUT_3_VOLUME:
case WM5100_HPLP3MIX_INPUT_4_SOURCE:
case WM5100_HPLP3MIX_INPUT_4_VOLUME:
case WM5100_HPLP4MIX_INPUT_1_SOURCE:
case WM5100_HPLP4MIX_INPUT_1_VOLUME:
case WM5100_HPLP4MIX_INPUT_2_SOURCE:
case WM5100_HPLP4MIX_INPUT_2_VOLUME:
case WM5100_HPLP4MIX_INPUT_3_SOURCE:
case WM5100_HPLP4MIX_INPUT_3_VOLUME:
case WM5100_HPLP4MIX_INPUT_4_SOURCE:
case WM5100_HPLP4MIX_INPUT_4_VOLUME:
case WM5100_DSP1LMIX_INPUT_1_SOURCE:
case WM5100_DSP1LMIX_INPUT_1_VOLUME:
case WM5100_DSP1LMIX_INPUT_2_SOURCE:
case WM5100_DSP1LMIX_INPUT_2_VOLUME:
case WM5100_DSP1LMIX_INPUT_3_SOURCE:
case WM5100_DSP1LMIX_INPUT_3_VOLUME:
case WM5100_DSP1LMIX_INPUT_4_SOURCE:
case WM5100_DSP1LMIX_INPUT_4_VOLUME:
case WM5100_DSP1RMIX_INPUT_1_SOURCE:
case WM5100_DSP1RMIX_INPUT_1_VOLUME:
case WM5100_DSP1RMIX_INPUT_2_SOURCE:
case WM5100_DSP1RMIX_INPUT_2_VOLUME:
case WM5100_DSP1RMIX_INPUT_3_SOURCE:
case WM5100_DSP1RMIX_INPUT_3_VOLUME:
case WM5100_DSP1RMIX_INPUT_4_SOURCE:
case WM5100_DSP1RMIX_INPUT_4_VOLUME:
case WM5100_DSP1AUX1MIX_INPUT_1_SOURCE:
case WM5100_DSP1AUX2MIX_INPUT_1_SOURCE:
case WM5100_DSP1AUX3MIX_INPUT_1_SOURCE:
case WM5100_DSP1AUX4MIX_INPUT_1_SOURCE:
case WM5100_DSP1AUX5MIX_INPUT_1_SOURCE:
case WM5100_DSP1AUX6MIX_INPUT_1_SOURCE:
case WM5100_DSP2LMIX_INPUT_1_SOURCE:
case WM5100_DSP2LMIX_INPUT_1_VOLUME:
case WM5100_DSP2LMIX_INPUT_2_SOURCE:
case WM5100_DSP2LMIX_INPUT_2_VOLUME:
case WM5100_DSP2LMIX_INPUT_3_SOURCE:
case WM5100_DSP2LMIX_INPUT_3_VOLUME:
case WM5100_DSP2LMIX_INPUT_4_SOURCE:
case WM5100_DSP2LMIX_INPUT_4_VOLUME:
case WM5100_DSP2RMIX_INPUT_1_SOURCE:
case WM5100_DSP2RMIX_INPUT_1_VOLUME:
case WM5100_DSP2RMIX_INPUT_2_SOURCE:
case WM5100_DSP2RMIX_INPUT_2_VOLUME:
case WM5100_DSP2RMIX_INPUT_3_SOURCE:
case WM5100_DSP2RMIX_INPUT_3_VOLUME:
case WM5100_DSP2RMIX_INPUT_4_SOURCE:
case WM5100_DSP2RMIX_INPUT_4_VOLUME:
case WM5100_DSP2AUX1MIX_INPUT_1_SOURCE:
case WM5100_DSP2AUX2MIX_INPUT_1_SOURCE:
case WM5100_DSP2AUX3MIX_INPUT_1_SOURCE:
case WM5100_DSP2AUX4MIX_INPUT_1_SOURCE:
case WM5100_DSP2AUX5MIX_INPUT_1_SOURCE:
case WM5100_DSP2AUX6MIX_INPUT_1_SOURCE:
case WM5100_DSP3LMIX_INPUT_1_SOURCE:
case WM5100_DSP3LMIX_INPUT_1_VOLUME:
case WM5100_DSP3LMIX_INPUT_2_SOURCE:
case WM5100_DSP3LMIX_INPUT_2_VOLUME:
case WM5100_DSP3LMIX_INPUT_3_SOURCE:
case WM5100_DSP3LMIX_INPUT_3_VOLUME:
case WM5100_DSP3LMIX_INPUT_4_SOURCE:
case WM5100_DSP3LMIX_INPUT_4_VOLUME:
case WM5100_DSP3RMIX_INPUT_1_SOURCE:
case WM5100_DSP3RMIX_INPUT_1_VOLUME:
case WM5100_DSP3RMIX_INPUT_2_SOURCE:
case WM5100_DSP3RMIX_INPUT_2_VOLUME:
case WM5100_DSP3RMIX_INPUT_3_SOURCE:
case WM5100_DSP3RMIX_INPUT_3_VOLUME:
case WM5100_DSP3RMIX_INPUT_4_SOURCE:
case WM5100_DSP3RMIX_INPUT_4_VOLUME:
case WM5100_DSP3AUX1MIX_INPUT_1_SOURCE:
case WM5100_DSP3AUX2MIX_INPUT_1_SOURCE:
case WM5100_DSP3AUX3MIX_INPUT_1_SOURCE:
case WM5100_DSP3AUX4MIX_INPUT_1_SOURCE:
case WM5100_DSP3AUX5MIX_INPUT_1_SOURCE:
case WM5100_DSP3AUX6MIX_INPUT_1_SOURCE:
case WM5100_ASRC1LMIX_INPUT_1_SOURCE:
case WM5100_ASRC1RMIX_INPUT_1_SOURCE:
case WM5100_ASRC2LMIX_INPUT_1_SOURCE:
case WM5100_ASRC2RMIX_INPUT_1_SOURCE:
case WM5100_ISRC1DEC1MIX_INPUT_1_SOURCE:
case WM5100_ISRC1DEC2MIX_INPUT_1_SOURCE:
case WM5100_ISRC1DEC3MIX_INPUT_1_SOURCE:
case WM5100_ISRC1DEC4MIX_INPUT_1_SOURCE:
case WM5100_ISRC1INT1MIX_INPUT_1_SOURCE:
case WM5100_ISRC1INT2MIX_INPUT_1_SOURCE:
case WM5100_ISRC1INT3MIX_INPUT_1_SOURCE:
case WM5100_ISRC1INT4MIX_INPUT_1_SOURCE:
case WM5100_ISRC2DEC1MIX_INPUT_1_SOURCE:
case WM5100_ISRC2DEC2MIX_INPUT_1_SOURCE:
case WM5100_ISRC2DEC3MIX_INPUT_1_SOURCE:
case WM5100_ISRC2DEC4MIX_INPUT_1_SOURCE:
case WM5100_ISRC2INT1MIX_INPUT_1_SOURCE:
case WM5100_ISRC2INT2MIX_INPUT_1_SOURCE:
case WM5100_ISRC2INT3MIX_INPUT_1_SOURCE:
case WM5100_ISRC2INT4MIX_INPUT_1_SOURCE:
case WM5100_GPIO_CTRL_1:
case WM5100_GPIO_CTRL_2:
case WM5100_GPIO_CTRL_3:
case WM5100_GPIO_CTRL_4:
case WM5100_GPIO_CTRL_5:
case WM5100_GPIO_CTRL_6:
case WM5100_MISC_PAD_CTRL_1:
case WM5100_MISC_PAD_CTRL_2:
case WM5100_MISC_PAD_CTRL_3:
case WM5100_MISC_PAD_CTRL_4:
case WM5100_MISC_PAD_CTRL_5:
case WM5100_MISC_GPIO_1:
case WM5100_INTERRUPT_STATUS_1:
case WM5100_INTERRUPT_STATUS_2:
case WM5100_INTERRUPT_STATUS_3:
case WM5100_INTERRUPT_STATUS_4:
case WM5100_INTERRUPT_RAW_STATUS_2:
case WM5100_INTERRUPT_RAW_STATUS_3:
case WM5100_INTERRUPT_RAW_STATUS_4:
case WM5100_INTERRUPT_STATUS_1_MASK:
case WM5100_INTERRUPT_STATUS_2_MASK:
case WM5100_INTERRUPT_STATUS_3_MASK:
case WM5100_INTERRUPT_STATUS_4_MASK:
case WM5100_INTERRUPT_CONTROL:
case WM5100_IRQ_DEBOUNCE_1:
case WM5100_IRQ_DEBOUNCE_2:
case WM5100_FX_CTRL:
case WM5100_EQ1_1:
case WM5100_EQ1_2:
case WM5100_EQ1_3:
case WM5100_EQ1_4:
case WM5100_EQ1_5:
case WM5100_EQ1_6:
case WM5100_EQ1_7:
case WM5100_EQ1_8:
case WM5100_EQ1_9:
case WM5100_EQ1_10:
case WM5100_EQ1_11:
case WM5100_EQ1_12:
case WM5100_EQ1_13:
case WM5100_EQ1_14:
case WM5100_EQ1_15:
case WM5100_EQ1_16:
case WM5100_EQ1_17:
case WM5100_EQ1_18:
case WM5100_EQ1_19:
case WM5100_EQ1_20:
case WM5100_EQ2_1:
case WM5100_EQ2_2:
case WM5100_EQ2_3:
case WM5100_EQ2_4:
case WM5100_EQ2_5:
case WM5100_EQ2_6:
case WM5100_EQ2_7:
case WM5100_EQ2_8:
case WM5100_EQ2_9:
case WM5100_EQ2_10:
case WM5100_EQ2_11:
case WM5100_EQ2_12:
case WM5100_EQ2_13:
case WM5100_EQ2_14:
case WM5100_EQ2_15:
case WM5100_EQ2_16:
case WM5100_EQ2_17:
case WM5100_EQ2_18:
case WM5100_EQ2_19:
case WM5100_EQ2_20:
case WM5100_EQ3_1:
case WM5100_EQ3_2:
case WM5100_EQ3_3:
case WM5100_EQ3_4:
case WM5100_EQ3_5:
case WM5100_EQ3_6:
case WM5100_EQ3_7:
case WM5100_EQ3_8:
case WM5100_EQ3_9:
case WM5100_EQ3_10:
case WM5100_EQ3_11:
case WM5100_EQ3_12:
case WM5100_EQ3_13:
case WM5100_EQ3_14:
case WM5100_EQ3_15:
case WM5100_EQ3_16:
case WM5100_EQ3_17:
case WM5100_EQ3_18:
case WM5100_EQ3_19:
case WM5100_EQ3_20:
case WM5100_EQ4_1:
case WM5100_EQ4_2:
case WM5100_EQ4_3:
case WM5100_EQ4_4:
case WM5100_EQ4_5:
case WM5100_EQ4_6:
case WM5100_EQ4_7:
case WM5100_EQ4_8:
case WM5100_EQ4_9:
case WM5100_EQ4_10:
case WM5100_EQ4_11:
case WM5100_EQ4_12:
case WM5100_EQ4_13:
case WM5100_EQ4_14:
case WM5100_EQ4_15:
case WM5100_EQ4_16:
case WM5100_EQ4_17:
case WM5100_EQ4_18:
case WM5100_EQ4_19:
case WM5100_EQ4_20:
case WM5100_DRC1_CTRL1:
case WM5100_DRC1_CTRL2:
case WM5100_DRC1_CTRL3:
case WM5100_DRC1_CTRL4:
case WM5100_DRC1_CTRL5:
case WM5100_HPLPF1_1:
case WM5100_HPLPF1_2:
case WM5100_HPLPF2_1:
case WM5100_HPLPF2_2:
case WM5100_HPLPF3_1:
case WM5100_HPLPF3_2:
case WM5100_HPLPF4_1:
case WM5100_HPLPF4_2:
case WM5100_DSP1_CONTROL_1:
case WM5100_DSP1_CONTROL_2:
case WM5100_DSP1_CONTROL_3:
case WM5100_DSP1_CONTROL_4:
case WM5100_DSP1_CONTROL_5:
case WM5100_DSP1_CONTROL_6:
case WM5100_DSP1_CONTROL_7:
case WM5100_DSP1_CONTROL_8:
case WM5100_DSP1_CONTROL_9:
case WM5100_DSP1_CONTROL_10:
case WM5100_DSP1_CONTROL_11:
case WM5100_DSP1_CONTROL_12:
case WM5100_DSP1_CONTROL_13:
case WM5100_DSP1_CONTROL_14:
case WM5100_DSP1_CONTROL_15:
case WM5100_DSP1_CONTROL_16:
case WM5100_DSP1_CONTROL_17:
case WM5100_DSP1_CONTROL_18:
case WM5100_DSP1_CONTROL_19:
case WM5100_DSP1_CONTROL_20:
case WM5100_DSP1_CONTROL_21:
case WM5100_DSP1_CONTROL_22:
case WM5100_DSP1_CONTROL_23:
case WM5100_DSP1_CONTROL_24:
case WM5100_DSP1_CONTROL_25:
case WM5100_DSP1_CONTROL_26:
case WM5100_DSP1_CONTROL_27:
case WM5100_DSP1_CONTROL_28:
case WM5100_DSP1_CONTROL_29:
case WM5100_DSP1_CONTROL_30:
case WM5100_DSP2_CONTROL_1:
case WM5100_DSP2_CONTROL_2:
case WM5100_DSP2_CONTROL_3:
case WM5100_DSP2_CONTROL_4:
case WM5100_DSP2_CONTROL_5:
case WM5100_DSP2_CONTROL_6:
case WM5100_DSP2_CONTROL_7:
case WM5100_DSP2_CONTROL_8:
case WM5100_DSP2_CONTROL_9:
case WM5100_DSP2_CONTROL_10:
case WM5100_DSP2_CONTROL_11:
case WM5100_DSP2_CONTROL_12:
case WM5100_DSP2_CONTROL_13:
case WM5100_DSP2_CONTROL_14:
case WM5100_DSP2_CONTROL_15:
case WM5100_DSP2_CONTROL_16:
case WM5100_DSP2_CONTROL_17:
case WM5100_DSP2_CONTROL_18:
case WM5100_DSP2_CONTROL_19:
case WM5100_DSP2_CONTROL_20:
case WM5100_DSP2_CONTROL_21:
case WM5100_DSP2_CONTROL_22:
case WM5100_DSP2_CONTROL_23:
case WM5100_DSP2_CONTROL_24:
case WM5100_DSP2_CONTROL_25:
case WM5100_DSP2_CONTROL_26:
case WM5100_DSP2_CONTROL_27:
case WM5100_DSP2_CONTROL_28:
case WM5100_DSP2_CONTROL_29:
case WM5100_DSP2_CONTROL_30:
case WM5100_DSP3_CONTROL_1:
case WM5100_DSP3_CONTROL_2:
case WM5100_DSP3_CONTROL_3:
case WM5100_DSP3_CONTROL_4:
case WM5100_DSP3_CONTROL_5:
case WM5100_DSP3_CONTROL_6:
case WM5100_DSP3_CONTROL_7:
case WM5100_DSP3_CONTROL_8:
case WM5100_DSP3_CONTROL_9:
case WM5100_DSP3_CONTROL_10:
case WM5100_DSP3_CONTROL_11:
case WM5100_DSP3_CONTROL_12:
case WM5100_DSP3_CONTROL_13:
case WM5100_DSP3_CONTROL_14:
case WM5100_DSP3_CONTROL_15:
case WM5100_DSP3_CONTROL_16:
case WM5100_DSP3_CONTROL_17:
case WM5100_DSP3_CONTROL_18:
case WM5100_DSP3_CONTROL_19:
case WM5100_DSP3_CONTROL_20:
case WM5100_DSP3_CONTROL_21:
case WM5100_DSP3_CONTROL_22:
case WM5100_DSP3_CONTROL_23:
case WM5100_DSP3_CONTROL_24:
case WM5100_DSP3_CONTROL_25:
case WM5100_DSP3_CONTROL_26:
case WM5100_DSP3_CONTROL_27:
case WM5100_DSP3_CONTROL_28:
case WM5100_DSP3_CONTROL_29:
case WM5100_DSP3_CONTROL_30:
return true;
default:
if ((reg >= WM5100_DSP1_PM_0 && reg <= WM5100_DSP1_PM_1535) ||
(reg >= WM5100_DSP1_ZM_0 && reg <= WM5100_DSP1_ZM_2047) ||
(reg >= WM5100_DSP1_DM_0 && reg <= WM5100_DSP1_DM_511) ||
(reg >= WM5100_DSP2_PM_0 && reg <= WM5100_DSP2_PM_1535) ||
(reg >= WM5100_DSP2_ZM_0 && reg <= WM5100_DSP2_ZM_2047) ||
(reg >= WM5100_DSP2_DM_0 && reg <= WM5100_DSP2_DM_511) ||
(reg >= WM5100_DSP3_PM_0 && reg <= WM5100_DSP3_PM_1535) ||
(reg >= WM5100_DSP3_ZM_0 && reg <= WM5100_DSP3_ZM_2047) ||
(reg >= WM5100_DSP3_DM_0 && reg <= WM5100_DSP3_DM_511))
return true;
else
return false;
}
}
struct reg_default wm5100_reg_defaults[WM5100_REGISTER_COUNT] = {
{ 0x0000, 0x0000 }, /* R0 - software reset */
{ 0x0001, 0x0000 }, /* R1 - Device Revision */
{ 0x0010, 0x0801 }, /* R16 - Ctrl IF 1 */
{ 0x0020, 0x0000 }, /* R32 - Tone Generator 1 */
{ 0x0030, 0x0000 }, /* R48 - PWM Drive 1 */
{ 0x0031, 0x0100 }, /* R49 - PWM Drive 2 */
{ 0x0032, 0x0100 }, /* R50 - PWM Drive 3 */
{ 0x0100, 0x0002 }, /* R256 - Clocking 1 */
{ 0x0101, 0x0000 }, /* R257 - Clocking 3 */
{ 0x0102, 0x0011 }, /* R258 - Clocking 4 */
{ 0x0103, 0x0011 }, /* R259 - Clocking 5 */
{ 0x0104, 0x0011 }, /* R260 - Clocking 6 */
{ 0x0107, 0x0000 }, /* R263 - Clocking 7 */
{ 0x0108, 0x0000 }, /* R264 - Clocking 8 */
{ 0x0120, 0x0000 }, /* R288 - ASRC_ENABLE */
{ 0x0121, 0x0000 }, /* R289 - ASRC_STATUS */
{ 0x0122, 0x0000 }, /* R290 - ASRC_RATE1 */
{ 0x0141, 0x8000 }, /* R321 - ISRC 1 CTRL 1 */
{ 0x0142, 0x0000 }, /* R322 - ISRC 1 CTRL 2 */
{ 0x0143, 0x8000 }, /* R323 - ISRC 2 CTRL1 */
{ 0x0144, 0x0000 }, /* R324 - ISRC 2 CTRL 2 */
{ 0x0182, 0x0000 }, /* R386 - FLL1 Control 1 */
{ 0x0183, 0x0000 }, /* R387 - FLL1 Control 2 */
{ 0x0184, 0x0000 }, /* R388 - FLL1 Control 3 */
{ 0x0186, 0x0177 }, /* R390 - FLL1 Control 5 */
{ 0x0187, 0x0001 }, /* R391 - FLL1 Control 6 */
{ 0x0188, 0x0000 }, /* R392 - FLL1 EFS 1 */
{ 0x01A2, 0x0000 }, /* R418 - FLL2 Control 1 */
{ 0x01A3, 0x0000 }, /* R419 - FLL2 Control 2 */
{ 0x01A4, 0x0000 }, /* R420 - FLL2 Control 3 */
{ 0x01A6, 0x0177 }, /* R422 - FLL2 Control 5 */
{ 0x01A7, 0x0001 }, /* R423 - FLL2 Control 6 */
{ 0x01A8, 0x0000 }, /* R424 - FLL2 EFS 1 */
{ 0x0200, 0x0020 }, /* R512 - Mic Charge Pump 1 */
{ 0x0201, 0xB084 }, /* R513 - Mic Charge Pump 2 */
{ 0x0202, 0xBBDE }, /* R514 - HP Charge Pump 1 */
{ 0x0211, 0x20D4 }, /* R529 - LDO1 Control */
{ 0x0215, 0x0062 }, /* R533 - Mic Bias Ctrl 1 */
{ 0x0216, 0x0062 }, /* R534 - Mic Bias Ctrl 2 */
{ 0x0217, 0x0062 }, /* R535 - Mic Bias Ctrl 3 */
{ 0x0280, 0x0004 }, /* R640 - Accessory Detect Mode 1 */
{ 0x0288, 0x0020 }, /* R648 - Headphone Detect 1 */
{ 0x0289, 0x0000 }, /* R649 - Headphone Detect 2 */
{ 0x0290, 0x1100 }, /* R656 - Mic Detect 1 */
{ 0x0291, 0x009F }, /* R657 - Mic Detect 2 */
{ 0x0292, 0x0000 }, /* R658 - Mic Detect 3 */
{ 0x0301, 0x0000 }, /* R769 - Input Enables */
{ 0x0302, 0x0000 }, /* R770 - Input Enables Status */
{ 0x0310, 0x2280 }, /* R784 - Status */
{ 0x0311, 0x0080 }, /* R785 - IN1R Control */
{ 0x0312, 0x2280 }, /* R786 - IN2L Control */
{ 0x0313, 0x0080 }, /* R787 - IN2R Control */
{ 0x0314, 0x2280 }, /* R788 - IN3L Control */
{ 0x0315, 0x0080 }, /* R789 - IN3R Control */
{ 0x0316, 0x2280 }, /* R790 - IN4L Control */
{ 0x0317, 0x0080 }, /* R791 - IN4R Control */
{ 0x0318, 0x0000 }, /* R792 - RXANC_SRC */
{ 0x0319, 0x0022 }, /* R793 - Input Volume Ramp */
{ 0x0320, 0x0180 }, /* R800 - ADC Digital Volume 1L */
{ 0x0321, 0x0180 }, /* R801 - ADC Digital Volume 1R */
{ 0x0322, 0x0180 }, /* R802 - ADC Digital Volume 2L */
{ 0x0323, 0x0180 }, /* R803 - ADC Digital Volume 2R */
{ 0x0324, 0x0180 }, /* R804 - ADC Digital Volume 3L */
{ 0x0325, 0x0180 }, /* R805 - ADC Digital Volume 3R */
{ 0x0326, 0x0180 }, /* R806 - ADC Digital Volume 4L */
{ 0x0327, 0x0180 }, /* R807 - ADC Digital Volume 4R */
{ 0x0401, 0x0000 }, /* R1025 - Output Enables 2 */
{ 0x0402, 0x0000 }, /* R1026 - Output Status 1 */
{ 0x0403, 0x0000 }, /* R1027 - Output Status 2 */
{ 0x0408, 0x0000 }, /* R1032 - Channel Enables 1 */
{ 0x0410, 0x0080 }, /* R1040 - Out Volume 1L */
{ 0x0411, 0x0080 }, /* R1041 - Out Volume 1R */
{ 0x0412, 0x0080 }, /* R1042 - DAC Volume Limit 1L */
{ 0x0413, 0x0080 }, /* R1043 - DAC Volume Limit 1R */
{ 0x0414, 0x0080 }, /* R1044 - Out Volume 2L */
{ 0x0415, 0x0080 }, /* R1045 - Out Volume 2R */
{ 0x0416, 0x0080 }, /* R1046 - DAC Volume Limit 2L */
{ 0x0417, 0x0080 }, /* R1047 - DAC Volume Limit 2R */
{ 0x0418, 0x0080 }, /* R1048 - Out Volume 3L */
{ 0x0419, 0x0080 }, /* R1049 - Out Volume 3R */
{ 0x041A, 0x0080 }, /* R1050 - DAC Volume Limit 3L */
{ 0x041B, 0x0080 }, /* R1051 - DAC Volume Limit 3R */
{ 0x041C, 0x0080 }, /* R1052 - Out Volume 4L */
{ 0x041D, 0x0080 }, /* R1053 - Out Volume 4R */
{ 0x041E, 0x0080 }, /* R1054 - DAC Volume Limit 5L */
{ 0x041F, 0x0080 }, /* R1055 - DAC Volume Limit 5R */
{ 0x0420, 0x0080 }, /* R1056 - DAC Volume Limit 6L */
{ 0x0421, 0x0080 }, /* R1057 - DAC Volume Limit 6R */
{ 0x0440, 0x0000 }, /* R1088 - DAC AEC Control 1 */
{ 0x0441, 0x0022 }, /* R1089 - Output Volume Ramp */
{ 0x0480, 0x0180 }, /* R1152 - DAC Digital Volume 1L */
{ 0x0481, 0x0180 }, /* R1153 - DAC Digital Volume 1R */
{ 0x0482, 0x0180 }, /* R1154 - DAC Digital Volume 2L */
{ 0x0483, 0x0180 }, /* R1155 - DAC Digital Volume 2R */
{ 0x0484, 0x0180 }, /* R1156 - DAC Digital Volume 3L */
{ 0x0485, 0x0180 }, /* R1157 - DAC Digital Volume 3R */
{ 0x0486, 0x0180 }, /* R1158 - DAC Digital Volume 4L */
{ 0x0487, 0x0180 }, /* R1159 - DAC Digital Volume 4R */
{ 0x0488, 0x0180 }, /* R1160 - DAC Digital Volume 5L */
{ 0x0489, 0x0180 }, /* R1161 - DAC Digital Volume 5R */
{ 0x048A, 0x0180 }, /* R1162 - DAC Digital Volume 6L */
{ 0x048B, 0x0180 }, /* R1163 - DAC Digital Volume 6R */
{ 0x04C0, 0x0069 }, /* R1216 - PDM SPK1 CTRL 1 */
{ 0x04C1, 0x0000 }, /* R1217 - PDM SPK1 CTRL 2 */
{ 0x04C2, 0x0069 }, /* R1218 - PDM SPK2 CTRL 1 */
{ 0x04C3, 0x0000 }, /* R1219 - PDM SPK2 CTRL 2 */
{ 0x0500, 0x000C }, /* R1280 - Audio IF 1_1 */
{ 0x0501, 0x0008 }, /* R1281 - Audio IF 1_2 */
{ 0x0502, 0x0000 }, /* R1282 - Audio IF 1_3 */
{ 0x0503, 0x0000 }, /* R1283 - Audio IF 1_4 */
{ 0x0504, 0x0000 }, /* R1284 - Audio IF 1_5 */
{ 0x0505, 0x0300 }, /* R1285 - Audio IF 1_6 */
{ 0x0506, 0x0300 }, /* R1286 - Audio IF 1_7 */
{ 0x0507, 0x1820 }, /* R1287 - Audio IF 1_8 */
{ 0x0508, 0x1820 }, /* R1288 - Audio IF 1_9 */
{ 0x0509, 0x0000 }, /* R1289 - Audio IF 1_10 */
{ 0x050A, 0x0001 }, /* R1290 - Audio IF 1_11 */
{ 0x050B, 0x0002 }, /* R1291 - Audio IF 1_12 */
{ 0x050C, 0x0003 }, /* R1292 - Audio IF 1_13 */
{ 0x050D, 0x0004 }, /* R1293 - Audio IF 1_14 */
{ 0x050E, 0x0005 }, /* R1294 - Audio IF 1_15 */
{ 0x050F, 0x0006 }, /* R1295 - Audio IF 1_16 */
{ 0x0510, 0x0007 }, /* R1296 - Audio IF 1_17 */
{ 0x0511, 0x0000 }, /* R1297 - Audio IF 1_18 */
{ 0x0512, 0x0001 }, /* R1298 - Audio IF 1_19 */
{ 0x0513, 0x0002 }, /* R1299 - Audio IF 1_20 */
{ 0x0514, 0x0003 }, /* R1300 - Audio IF 1_21 */
{ 0x0515, 0x0004 }, /* R1301 - Audio IF 1_22 */
{ 0x0516, 0x0005 }, /* R1302 - Audio IF 1_23 */
{ 0x0517, 0x0006 }, /* R1303 - Audio IF 1_24 */
{ 0x0518, 0x0007 }, /* R1304 - Audio IF 1_25 */
{ 0x0519, 0x0000 }, /* R1305 - Audio IF 1_26 */
{ 0x051A, 0x0000 }, /* R1306 - Audio IF 1_27 */
{ 0x0540, 0x000C }, /* R1344 - Audio IF 2_1 */
{ 0x0541, 0x0008 }, /* R1345 - Audio IF 2_2 */
{ 0x0542, 0x0000 }, /* R1346 - Audio IF 2_3 */
{ 0x0543, 0x0000 }, /* R1347 - Audio IF 2_4 */
{ 0x0544, 0x0000 }, /* R1348 - Audio IF 2_5 */
{ 0x0545, 0x0300 }, /* R1349 - Audio IF 2_6 */
{ 0x0546, 0x0300 }, /* R1350 - Audio IF 2_7 */
{ 0x0547, 0x1820 }, /* R1351 - Audio IF 2_8 */
{ 0x0548, 0x1820 }, /* R1352 - Audio IF 2_9 */
{ 0x0549, 0x0000 }, /* R1353 - Audio IF 2_10 */
{ 0x054A, 0x0001 }, /* R1354 - Audio IF 2_11 */
{ 0x0551, 0x0000 }, /* R1361 - Audio IF 2_18 */
{ 0x0552, 0x0001 }, /* R1362 - Audio IF 2_19 */
{ 0x0559, 0x0000 }, /* R1369 - Audio IF 2_26 */
{ 0x055A, 0x0000 }, /* R1370 - Audio IF 2_27 */
{ 0x0580, 0x000C }, /* R1408 - Audio IF 3_1 */
{ 0x0581, 0x0008 }, /* R1409 - Audio IF 3_2 */
{ 0x0582, 0x0000 }, /* R1410 - Audio IF 3_3 */
{ 0x0583, 0x0000 }, /* R1411 - Audio IF 3_4 */
{ 0x0584, 0x0000 }, /* R1412 - Audio IF 3_5 */
{ 0x0585, 0x0300 }, /* R1413 - Audio IF 3_6 */
{ 0x0586, 0x0300 }, /* R1414 - Audio IF 3_7 */
{ 0x0587, 0x1820 }, /* R1415 - Audio IF 3_8 */
{ 0x0588, 0x1820 }, /* R1416 - Audio IF 3_9 */
{ 0x0589, 0x0000 }, /* R1417 - Audio IF 3_10 */
{ 0x058A, 0x0001 }, /* R1418 - Audio IF 3_11 */
{ 0x0591, 0x0000 }, /* R1425 - Audio IF 3_18 */
{ 0x0592, 0x0001 }, /* R1426 - Audio IF 3_19 */
{ 0x0599, 0x0000 }, /* R1433 - Audio IF 3_26 */
{ 0x059A, 0x0000 }, /* R1434 - Audio IF 3_27 */
{ 0x0640, 0x0000 }, /* R1600 - PWM1MIX Input 1 Source */
{ 0x0641, 0x0080 }, /* R1601 - PWM1MIX Input 1 Volume */
{ 0x0642, 0x0000 }, /* R1602 - PWM1MIX Input 2 Source */
{ 0x0643, 0x0080 }, /* R1603 - PWM1MIX Input 2 Volume */
{ 0x0644, 0x0000 }, /* R1604 - PWM1MIX Input 3 Source */
{ 0x0645, 0x0080 }, /* R1605 - PWM1MIX Input 3 Volume */
{ 0x0646, 0x0000 }, /* R1606 - PWM1MIX Input 4 Source */
{ 0x0647, 0x0080 }, /* R1607 - PWM1MIX Input 4 Volume */
{ 0x0648, 0x0000 }, /* R1608 - PWM2MIX Input 1 Source */
{ 0x0649, 0x0080 }, /* R1609 - PWM2MIX Input 1 Volume */
{ 0x064A, 0x0000 }, /* R1610 - PWM2MIX Input 2 Source */
{ 0x064B, 0x0080 }, /* R1611 - PWM2MIX Input 2 Volume */
{ 0x064C, 0x0000 }, /* R1612 - PWM2MIX Input 3 Source */
{ 0x064D, 0x0080 }, /* R1613 - PWM2MIX Input 3 Volume */
{ 0x064E, 0x0000 }, /* R1614 - PWM2MIX Input 4 Source */
{ 0x064F, 0x0080 }, /* R1615 - PWM2MIX Input 4 Volume */
{ 0x0680, 0x0000 }, /* R1664 - OUT1LMIX Input 1 Source */
{ 0x0681, 0x0080 }, /* R1665 - OUT1LMIX Input 1 Volume */
{ 0x0682, 0x0000 }, /* R1666 - OUT1LMIX Input 2 Source */
{ 0x0683, 0x0080 }, /* R1667 - OUT1LMIX Input 2 Volume */
{ 0x0684, 0x0000 }, /* R1668 - OUT1LMIX Input 3 Source */
{ 0x0685, 0x0080 }, /* R1669 - OUT1LMIX Input 3 Volume */
{ 0x0686, 0x0000 }, /* R1670 - OUT1LMIX Input 4 Source */
{ 0x0687, 0x0080 }, /* R1671 - OUT1LMIX Input 4 Volume */
{ 0x0688, 0x0000 }, /* R1672 - OUT1RMIX Input 1 Source */
{ 0x0689, 0x0080 }, /* R1673 - OUT1RMIX Input 1 Volume */
{ 0x068A, 0x0000 }, /* R1674 - OUT1RMIX Input 2 Source */
{ 0x068B, 0x0080 }, /* R1675 - OUT1RMIX Input 2 Volume */
{ 0x068C, 0x0000 }, /* R1676 - OUT1RMIX Input 3 Source */
{ 0x068D, 0x0080 }, /* R1677 - OUT1RMIX Input 3 Volume */
{ 0x068E, 0x0000 }, /* R1678 - OUT1RMIX Input 4 Source */
{ 0x068F, 0x0080 }, /* R1679 - OUT1RMIX Input 4 Volume */
{ 0x0690, 0x0000 }, /* R1680 - OUT2LMIX Input 1 Source */
{ 0x0691, 0x0080 }, /* R1681 - OUT2LMIX Input 1 Volume */
{ 0x0692, 0x0000 }, /* R1682 - OUT2LMIX Input 2 Source */
{ 0x0693, 0x0080 }, /* R1683 - OUT2LMIX Input 2 Volume */
{ 0x0694, 0x0000 }, /* R1684 - OUT2LMIX Input 3 Source */
{ 0x0695, 0x0080 }, /* R1685 - OUT2LMIX Input 3 Volume */
{ 0x0696, 0x0000 }, /* R1686 - OUT2LMIX Input 4 Source */
{ 0x0697, 0x0080 }, /* R1687 - OUT2LMIX Input 4 Volume */
{ 0x0698, 0x0000 }, /* R1688 - OUT2RMIX Input 1 Source */
{ 0x0699, 0x0080 }, /* R1689 - OUT2RMIX Input 1 Volume */
{ 0x069A, 0x0000 }, /* R1690 - OUT2RMIX Input 2 Source */
{ 0x069B, 0x0080 }, /* R1691 - OUT2RMIX Input 2 Volume */
{ 0x069C, 0x0000 }, /* R1692 - OUT2RMIX Input 3 Source */
{ 0x069D, 0x0080 }, /* R1693 - OUT2RMIX Input 3 Volume */
{ 0x069E, 0x0000 }, /* R1694 - OUT2RMIX Input 4 Source */
{ 0x069F, 0x0080 }, /* R1695 - OUT2RMIX Input 4 Volume */
{ 0x06A0, 0x0000 }, /* R1696 - OUT3LMIX Input 1 Source */
{ 0x06A1, 0x0080 }, /* R1697 - OUT3LMIX Input 1 Volume */
{ 0x06A2, 0x0000 }, /* R1698 - OUT3LMIX Input 2 Source */
{ 0x06A3, 0x0080 }, /* R1699 - OUT3LMIX Input 2 Volume */
{ 0x06A4, 0x0000 }, /* R1700 - OUT3LMIX Input 3 Source */
{ 0x06A5, 0x0080 }, /* R1701 - OUT3LMIX Input 3 Volume */
{ 0x06A6, 0x0000 }, /* R1702 - OUT3LMIX Input 4 Source */
{ 0x06A7, 0x0080 }, /* R1703 - OUT3LMIX Input 4 Volume */
{ 0x06A8, 0x0000 }, /* R1704 - OUT3RMIX Input 1 Source */
{ 0x06A9, 0x0080 }, /* R1705 - OUT3RMIX Input 1 Volume */
{ 0x06AA, 0x0000 }, /* R1706 - OUT3RMIX Input 2 Source */
{ 0x06AB, 0x0080 }, /* R1707 - OUT3RMIX Input 2 Volume */
{ 0x06AC, 0x0000 }, /* R1708 - OUT3RMIX Input 3 Source */
{ 0x06AD, 0x0080 }, /* R1709 - OUT3RMIX Input 3 Volume */
{ 0x06AE, 0x0000 }, /* R1710 - OUT3RMIX Input 4 Source */
{ 0x06AF, 0x0080 }, /* R1711 - OUT3RMIX Input 4 Volume */
{ 0x06B0, 0x0000 }, /* R1712 - OUT4LMIX Input 1 Source */
{ 0x06B1, 0x0080 }, /* R1713 - OUT4LMIX Input 1 Volume */
{ 0x06B2, 0x0000 }, /* R1714 - OUT4LMIX Input 2 Source */
{ 0x06B3, 0x0080 }, /* R1715 - OUT4LMIX Input 2 Volume */
{ 0x06B4, 0x0000 }, /* R1716 - OUT4LMIX Input 3 Source */
{ 0x06B5, 0x0080 }, /* R1717 - OUT4LMIX Input 3 Volume */
{ 0x06B6, 0x0000 }, /* R1718 - OUT4LMIX Input 4 Source */
{ 0x06B7, 0x0080 }, /* R1719 - OUT4LMIX Input 4 Volume */
{ 0x06B8, 0x0000 }, /* R1720 - OUT4RMIX Input 1 Source */
{ 0x06B9, 0x0080 }, /* R1721 - OUT4RMIX Input 1 Volume */
{ 0x06BA, 0x0000 }, /* R1722 - OUT4RMIX Input 2 Source */
{ 0x06BB, 0x0080 }, /* R1723 - OUT4RMIX Input 2 Volume */
{ 0x06BC, 0x0000 }, /* R1724 - OUT4RMIX Input 3 Source */
{ 0x06BD, 0x0080 }, /* R1725 - OUT4RMIX Input 3 Volume */
{ 0x06BE, 0x0000 }, /* R1726 - OUT4RMIX Input 4 Source */
{ 0x06BF, 0x0080 }, /* R1727 - OUT4RMIX Input 4 Volume */
{ 0x06C0, 0x0000 }, /* R1728 - OUT5LMIX Input 1 Source */
{ 0x06C1, 0x0080 }, /* R1729 - OUT5LMIX Input 1 Volume */
{ 0x06C2, 0x0000 }, /* R1730 - OUT5LMIX Input 2 Source */
{ 0x06C3, 0x0080 }, /* R1731 - OUT5LMIX Input 2 Volume */
{ 0x06C4, 0x0000 }, /* R1732 - OUT5LMIX Input 3 Source */
{ 0x06C5, 0x0080 }, /* R1733 - OUT5LMIX Input 3 Volume */
{ 0x06C6, 0x0000 }, /* R1734 - OUT5LMIX Input 4 Source */
{ 0x06C7, 0x0080 }, /* R1735 - OUT5LMIX Input 4 Volume */
{ 0x06C8, 0x0000 }, /* R1736 - OUT5RMIX Input 1 Source */
{ 0x06C9, 0x0080 }, /* R1737 - OUT5RMIX Input 1 Volume */
{ 0x06CA, 0x0000 }, /* R1738 - OUT5RMIX Input 2 Source */
{ 0x06CB, 0x0080 }, /* R1739 - OUT5RMIX Input 2 Volume */
{ 0x06CC, 0x0000 }, /* R1740 - OUT5RMIX Input 3 Source */
{ 0x06CD, 0x0080 }, /* R1741 - OUT5RMIX Input 3 Volume */
{ 0x06CE, 0x0000 }, /* R1742 - OUT5RMIX Input 4 Source */
{ 0x06CF, 0x0080 }, /* R1743 - OUT5RMIX Input 4 Volume */
{ 0x06D0, 0x0000 }, /* R1744 - OUT6LMIX Input 1 Source */
{ 0x06D1, 0x0080 }, /* R1745 - OUT6LMIX Input 1 Volume */
{ 0x06D2, 0x0000 }, /* R1746 - OUT6LMIX Input 2 Source */
{ 0x06D3, 0x0080 }, /* R1747 - OUT6LMIX Input 2 Volume */
{ 0x06D4, 0x0000 }, /* R1748 - OUT6LMIX Input 3 Source */
{ 0x06D5, 0x0080 }, /* R1749 - OUT6LMIX Input 3 Volume */
{ 0x06D6, 0x0000 }, /* R1750 - OUT6LMIX Input 4 Source */
{ 0x06D7, 0x0080 }, /* R1751 - OUT6LMIX Input 4 Volume */
{ 0x06D8, 0x0000 }, /* R1752 - OUT6RMIX Input 1 Source */
{ 0x06D9, 0x0080 }, /* R1753 - OUT6RMIX Input 1 Volume */
{ 0x06DA, 0x0000 }, /* R1754 - OUT6RMIX Input 2 Source */
{ 0x06DB, 0x0080 }, /* R1755 - OUT6RMIX Input 2 Volume */
{ 0x06DC, 0x0000 }, /* R1756 - OUT6RMIX Input 3 Source */
{ 0x06DD, 0x0080 }, /* R1757 - OUT6RMIX Input 3 Volume */
{ 0x06DE, 0x0000 }, /* R1758 - OUT6RMIX Input 4 Source */
{ 0x06DF, 0x0080 }, /* R1759 - OUT6RMIX Input 4 Volume */
{ 0x0700, 0x0000 }, /* R1792 - AIF1TX1MIX Input 1 Source */
{ 0x0701, 0x0080 }, /* R1793 - AIF1TX1MIX Input 1 Volume */
{ 0x0702, 0x0000 }, /* R1794 - AIF1TX1MIX Input 2 Source */
{ 0x0703, 0x0080 }, /* R1795 - AIF1TX1MIX Input 2 Volume */
{ 0x0704, 0x0000 }, /* R1796 - AIF1TX1MIX Input 3 Source */
{ 0x0705, 0x0080 }, /* R1797 - AIF1TX1MIX Input 3 Volume */
{ 0x0706, 0x0000 }, /* R1798 - AIF1TX1MIX Input 4 Source */
{ 0x0707, 0x0080 }, /* R1799 - AIF1TX1MIX Input 4 Volume */
{ 0x0708, 0x0000 }, /* R1800 - AIF1TX2MIX Input 1 Source */
{ 0x0709, 0x0080 }, /* R1801 - AIF1TX2MIX Input 1 Volume */
{ 0x070A, 0x0000 }, /* R1802 - AIF1TX2MIX Input 2 Source */
{ 0x070B, 0x0080 }, /* R1803 - AIF1TX2MIX Input 2 Volume */
{ 0x070C, 0x0000 }, /* R1804 - AIF1TX2MIX Input 3 Source */
{ 0x070D, 0x0080 }, /* R1805 - AIF1TX2MIX Input 3 Volume */
{ 0x070E, 0x0000 }, /* R1806 - AIF1TX2MIX Input 4 Source */
{ 0x070F, 0x0080 }, /* R1807 - AIF1TX2MIX Input 4 Volume */
{ 0x0710, 0x0000 }, /* R1808 - AIF1TX3MIX Input 1 Source */
{ 0x0711, 0x0080 }, /* R1809 - AIF1TX3MIX Input 1 Volume */
{ 0x0712, 0x0000 }, /* R1810 - AIF1TX3MIX Input 2 Source */
{ 0x0713, 0x0080 }, /* R1811 - AIF1TX3MIX Input 2 Volume */
{ 0x0714, 0x0000 }, /* R1812 - AIF1TX3MIX Input 3 Source */
{ 0x0715, 0x0080 }, /* R1813 - AIF1TX3MIX Input 3 Volume */
{ 0x0716, 0x0000 }, /* R1814 - AIF1TX3MIX Input 4 Source */
{ 0x0717, 0x0080 }, /* R1815 - AIF1TX3MIX Input 4 Volume */
{ 0x0718, 0x0000 }, /* R1816 - AIF1TX4MIX Input 1 Source */
{ 0x0719, 0x0080 }, /* R1817 - AIF1TX4MIX Input 1 Volume */
{ 0x071A, 0x0000 }, /* R1818 - AIF1TX4MIX Input 2 Source */
{ 0x071B, 0x0080 }, /* R1819 - AIF1TX4MIX Input 2 Volume */
{ 0x071C, 0x0000 }, /* R1820 - AIF1TX4MIX Input 3 Source */
{ 0x071D, 0x0080 }, /* R1821 - AIF1TX4MIX Input 3 Volume */
{ 0x071E, 0x0000 }, /* R1822 - AIF1TX4MIX Input 4 Source */
{ 0x071F, 0x0080 }, /* R1823 - AIF1TX4MIX Input 4 Volume */
{ 0x0720, 0x0000 }, /* R1824 - AIF1TX5MIX Input 1 Source */
{ 0x0721, 0x0080 }, /* R1825 - AIF1TX5MIX Input 1 Volume */
{ 0x0722, 0x0000 }, /* R1826 - AIF1TX5MIX Input 2 Source */
{ 0x0723, 0x0080 }, /* R1827 - AIF1TX5MIX Input 2 Volume */
{ 0x0724, 0x0000 }, /* R1828 - AIF1TX5MIX Input 3 Source */
{ 0x0725, 0x0080 }, /* R1829 - AIF1TX5MIX Input 3 Volume */
{ 0x0726, 0x0000 }, /* R1830 - AIF1TX5MIX Input 4 Source */
{ 0x0727, 0x0080 }, /* R1831 - AIF1TX5MIX Input 4 Volume */
{ 0x0728, 0x0000 }, /* R1832 - AIF1TX6MIX Input 1 Source */
{ 0x0729, 0x0080 }, /* R1833 - AIF1TX6MIX Input 1 Volume */
{ 0x072A, 0x0000 }, /* R1834 - AIF1TX6MIX Input 2 Source */
{ 0x072B, 0x0080 }, /* R1835 - AIF1TX6MIX Input 2 Volume */
{ 0x072C, 0x0000 }, /* R1836 - AIF1TX6MIX Input 3 Source */
{ 0x072D, 0x0080 }, /* R1837 - AIF1TX6MIX Input 3 Volume */
{ 0x072E, 0x0000 }, /* R1838 - AIF1TX6MIX Input 4 Source */
{ 0x072F, 0x0080 }, /* R1839 - AIF1TX6MIX Input 4 Volume */
{ 0x0730, 0x0000 }, /* R1840 - AIF1TX7MIX Input 1 Source */
{ 0x0731, 0x0080 }, /* R1841 - AIF1TX7MIX Input 1 Volume */
{ 0x0732, 0x0000 }, /* R1842 - AIF1TX7MIX Input 2 Source */
{ 0x0733, 0x0080 }, /* R1843 - AIF1TX7MIX Input 2 Volume */
{ 0x0734, 0x0000 }, /* R1844 - AIF1TX7MIX Input 3 Source */
{ 0x0735, 0x0080 }, /* R1845 - AIF1TX7MIX Input 3 Volume */
{ 0x0736, 0x0000 }, /* R1846 - AIF1TX7MIX Input 4 Source */
{ 0x0737, 0x0080 }, /* R1847 - AIF1TX7MIX Input 4 Volume */
{ 0x0738, 0x0000 }, /* R1848 - AIF1TX8MIX Input 1 Source */
{ 0x0739, 0x0080 }, /* R1849 - AIF1TX8MIX Input 1 Volume */
{ 0x073A, 0x0000 }, /* R1850 - AIF1TX8MIX Input 2 Source */
{ 0x073B, 0x0080 }, /* R1851 - AIF1TX8MIX Input 2 Volume */
{ 0x073C, 0x0000 }, /* R1852 - AIF1TX8MIX Input 3 Source */
{ 0x073D, 0x0080 }, /* R1853 - AIF1TX8MIX Input 3 Volume */
{ 0x073E, 0x0000 }, /* R1854 - AIF1TX8MIX Input 4 Source */
{ 0x073F, 0x0080 }, /* R1855 - AIF1TX8MIX Input 4 Volume */
{ 0x0740, 0x0000 }, /* R1856 - AIF2TX1MIX Input 1 Source */
{ 0x0741, 0x0080 }, /* R1857 - AIF2TX1MIX Input 1 Volume */
{ 0x0742, 0x0000 }, /* R1858 - AIF2TX1MIX Input 2 Source */
{ 0x0743, 0x0080 }, /* R1859 - AIF2TX1MIX Input 2 Volume */
{ 0x0744, 0x0000 }, /* R1860 - AIF2TX1MIX Input 3 Source */
{ 0x0745, 0x0080 }, /* R1861 - AIF2TX1MIX Input 3 Volume */
{ 0x0746, 0x0000 }, /* R1862 - AIF2TX1MIX Input 4 Source */
{ 0x0747, 0x0080 }, /* R1863 - AIF2TX1MIX Input 4 Volume */
{ 0x0748, 0x0000 }, /* R1864 - AIF2TX2MIX Input 1 Source */
{ 0x0749, 0x0080 }, /* R1865 - AIF2TX2MIX Input 1 Volume */
{ 0x074A, 0x0000 }, /* R1866 - AIF2TX2MIX Input 2 Source */
{ 0x074B, 0x0080 }, /* R1867 - AIF2TX2MIX Input 2 Volume */
{ 0x074C, 0x0000 }, /* R1868 - AIF2TX2MIX Input 3 Source */
{ 0x074D, 0x0080 }, /* R1869 - AIF2TX2MIX Input 3 Volume */
{ 0x074E, 0x0000 }, /* R1870 - AIF2TX2MIX Input 4 Source */
{ 0x074F, 0x0080 }, /* R1871 - AIF2TX2MIX Input 4 Volume */
{ 0x0780, 0x0000 }, /* R1920 - AIF3TX1MIX Input 1 Source */
{ 0x0781, 0x0080 }, /* R1921 - AIF3TX1MIX Input 1 Volume */
{ 0x0782, 0x0000 }, /* R1922 - AIF3TX1MIX Input 2 Source */
{ 0x0783, 0x0080 }, /* R1923 - AIF3TX1MIX Input 2 Volume */
{ 0x0784, 0x0000 }, /* R1924 - AIF3TX1MIX Input 3 Source */
{ 0x0785, 0x0080 }, /* R1925 - AIF3TX1MIX Input 3 Volume */
{ 0x0786, 0x0000 }, /* R1926 - AIF3TX1MIX Input 4 Source */
{ 0x0787, 0x0080 }, /* R1927 - AIF3TX1MIX Input 4 Volume */
{ 0x0788, 0x0000 }, /* R1928 - AIF3TX2MIX Input 1 Source */
{ 0x0789, 0x0080 }, /* R1929 - AIF3TX2MIX Input 1 Volume */
{ 0x078A, 0x0000 }, /* R1930 - AIF3TX2MIX Input 2 Source */
{ 0x078B, 0x0080 }, /* R1931 - AIF3TX2MIX Input 2 Volume */
{ 0x078C, 0x0000 }, /* R1932 - AIF3TX2MIX Input 3 Source */
{ 0x078D, 0x0080 }, /* R1933 - AIF3TX2MIX Input 3 Volume */
{ 0x078E, 0x0000 }, /* R1934 - AIF3TX2MIX Input 4 Source */
{ 0x078F, 0x0080 }, /* R1935 - AIF3TX2MIX Input 4 Volume */
{ 0x0880, 0x0000 }, /* R2176 - EQ1MIX Input 1 Source */
{ 0x0881, 0x0080 }, /* R2177 - EQ1MIX Input 1 Volume */
{ 0x0882, 0x0000 }, /* R2178 - EQ1MIX Input 2 Source */
{ 0x0883, 0x0080 }, /* R2179 - EQ1MIX Input 2 Volume */
{ 0x0884, 0x0000 }, /* R2180 - EQ1MIX Input 3 Source */
{ 0x0885, 0x0080 }, /* R2181 - EQ1MIX Input 3 Volume */
{ 0x0886, 0x0000 }, /* R2182 - EQ1MIX Input 4 Source */
{ 0x0887, 0x0080 }, /* R2183 - EQ1MIX Input 4 Volume */
{ 0x0888, 0x0000 }, /* R2184 - EQ2MIX Input 1 Source */
{ 0x0889, 0x0080 }, /* R2185 - EQ2MIX Input 1 Volume */
{ 0x088A, 0x0000 }, /* R2186 - EQ2MIX Input 2 Source */
{ 0x088B, 0x0080 }, /* R2187 - EQ2MIX Input 2 Volume */
{ 0x088C, 0x0000 }, /* R2188 - EQ2MIX Input 3 Source */
{ 0x088D, 0x0080 }, /* R2189 - EQ2MIX Input 3 Volume */
{ 0x088E, 0x0000 }, /* R2190 - EQ2MIX Input 4 Source */
{ 0x088F, 0x0080 }, /* R2191 - EQ2MIX Input 4 Volume */
{ 0x0890, 0x0000 }, /* R2192 - EQ3MIX Input 1 Source */
{ 0x0891, 0x0080 }, /* R2193 - EQ3MIX Input 1 Volume */
{ 0x0892, 0x0000 }, /* R2194 - EQ3MIX Input 2 Source */
{ 0x0893, 0x0080 }, /* R2195 - EQ3MIX Input 2 Volume */
{ 0x0894, 0x0000 }, /* R2196 - EQ3MIX Input 3 Source */
{ 0x0895, 0x0080 }, /* R2197 - EQ3MIX Input 3 Volume */
{ 0x0896, 0x0000 }, /* R2198 - EQ3MIX Input 4 Source */
{ 0x0897, 0x0080 }, /* R2199 - EQ3MIX Input 4 Volume */
{ 0x0898, 0x0000 }, /* R2200 - EQ4MIX Input 1 Source */
{ 0x0899, 0x0080 }, /* R2201 - EQ4MIX Input 1 Volume */
{ 0x089A, 0x0000 }, /* R2202 - EQ4MIX Input 2 Source */
{ 0x089B, 0x0080 }, /* R2203 - EQ4MIX Input 2 Volume */
{ 0x089C, 0x0000 }, /* R2204 - EQ4MIX Input 3 Source */
{ 0x089D, 0x0080 }, /* R2205 - EQ4MIX Input 3 Volume */
{ 0x089E, 0x0000 }, /* R2206 - EQ4MIX Input 4 Source */
{ 0x089F, 0x0080 }, /* R2207 - EQ4MIX Input 4 Volume */
{ 0x08C0, 0x0000 }, /* R2240 - DRC1LMIX Input 1 Source */
{ 0x08C1, 0x0080 }, /* R2241 - DRC1LMIX Input 1 Volume */
{ 0x08C2, 0x0000 }, /* R2242 - DRC1LMIX Input 2 Source */
{ 0x08C3, 0x0080 }, /* R2243 - DRC1LMIX Input 2 Volume */
{ 0x08C4, 0x0000 }, /* R2244 - DRC1LMIX Input 3 Source */
{ 0x08C5, 0x0080 }, /* R2245 - DRC1LMIX Input 3 Volume */
{ 0x08C6, 0x0000 }, /* R2246 - DRC1LMIX Input 4 Source */
{ 0x08C7, 0x0080 }, /* R2247 - DRC1LMIX Input 4 Volume */
{ 0x08C8, 0x0000 }, /* R2248 - DRC1RMIX Input 1 Source */
{ 0x08C9, 0x0080 }, /* R2249 - DRC1RMIX Input 1 Volume */
{ 0x08CA, 0x0000 }, /* R2250 - DRC1RMIX Input 2 Source */
{ 0x08CB, 0x0080 }, /* R2251 - DRC1RMIX Input 2 Volume */
{ 0x08CC, 0x0000 }, /* R2252 - DRC1RMIX Input 3 Source */
{ 0x08CD, 0x0080 }, /* R2253 - DRC1RMIX Input 3 Volume */
{ 0x08CE, 0x0000 }, /* R2254 - DRC1RMIX Input 4 Source */
{ 0x08CF, 0x0080 }, /* R2255 - DRC1RMIX Input 4 Volume */
{ 0x0900, 0x0000 }, /* R2304 - HPLP1MIX Input 1 Source */
{ 0x0901, 0x0080 }, /* R2305 - HPLP1MIX Input 1 Volume */
{ 0x0902, 0x0000 }, /* R2306 - HPLP1MIX Input 2 Source */
{ 0x0903, 0x0080 }, /* R2307 - HPLP1MIX Input 2 Volume */
{ 0x0904, 0x0000 }, /* R2308 - HPLP1MIX Input 3 Source */
{ 0x0905, 0x0080 }, /* R2309 - HPLP1MIX Input 3 Volume */
{ 0x0906, 0x0000 }, /* R2310 - HPLP1MIX Input 4 Source */
{ 0x0907, 0x0080 }, /* R2311 - HPLP1MIX Input 4 Volume */
{ 0x0908, 0x0000 }, /* R2312 - HPLP2MIX Input 1 Source */
{ 0x0909, 0x0080 }, /* R2313 - HPLP2MIX Input 1 Volume */
{ 0x090A, 0x0000 }, /* R2314 - HPLP2MIX Input 2 Source */
{ 0x090B, 0x0080 }, /* R2315 - HPLP2MIX Input 2 Volume */
{ 0x090C, 0x0000 }, /* R2316 - HPLP2MIX Input 3 Source */
{ 0x090D, 0x0080 }, /* R2317 - HPLP2MIX Input 3 Volume */
{ 0x090E, 0x0000 }, /* R2318 - HPLP2MIX Input 4 Source */
{ 0x090F, 0x0080 }, /* R2319 - HPLP2MIX Input 4 Volume */
{ 0x0910, 0x0000 }, /* R2320 - HPLP3MIX Input 1 Source */
{ 0x0911, 0x0080 }, /* R2321 - HPLP3MIX Input 1 Volume */
{ 0x0912, 0x0000 }, /* R2322 - HPLP3MIX Input 2 Source */
{ 0x0913, 0x0080 }, /* R2323 - HPLP3MIX Input 2 Volume */
{ 0x0914, 0x0000 }, /* R2324 - HPLP3MIX Input 3 Source */
{ 0x0915, 0x0080 }, /* R2325 - HPLP3MIX Input 3 Volume */
{ 0x0916, 0x0000 }, /* R2326 - HPLP3MIX Input 4 Source */
{ 0x0917, 0x0080 }, /* R2327 - HPLP3MIX Input 4 Volume */
{ 0x0918, 0x0000 }, /* R2328 - HPLP4MIX Input 1 Source */
{ 0x0919, 0x0080 }, /* R2329 - HPLP4MIX Input 1 Volume */
{ 0x091A, 0x0000 }, /* R2330 - HPLP4MIX Input 2 Source */
{ 0x091B, 0x0080 }, /* R2331 - HPLP4MIX Input 2 Volume */
{ 0x091C, 0x0000 }, /* R2332 - HPLP4MIX Input 3 Source */
{ 0x091D, 0x0080 }, /* R2333 - HPLP4MIX Input 3 Volume */
{ 0x091E, 0x0000 }, /* R2334 - HPLP4MIX Input 4 Source */
{ 0x091F, 0x0080 }, /* R2335 - HPLP4MIX Input 4 Volume */
{ 0x0940, 0x0000 }, /* R2368 - DSP1LMIX Input 1 Source */
{ 0x0941, 0x0080 }, /* R2369 - DSP1LMIX Input 1 Volume */
{ 0x0942, 0x0000 }, /* R2370 - DSP1LMIX Input 2 Source */
{ 0x0943, 0x0080 }, /* R2371 - DSP1LMIX Input 2 Volume */
{ 0x0944, 0x0000 }, /* R2372 - DSP1LMIX Input 3 Source */
{ 0x0945, 0x0080 }, /* R2373 - DSP1LMIX Input 3 Volume */
{ 0x0946, 0x0000 }, /* R2374 - DSP1LMIX Input 4 Source */
{ 0x0947, 0x0080 }, /* R2375 - DSP1LMIX Input 4 Volume */
{ 0x0948, 0x0000 }, /* R2376 - DSP1RMIX Input 1 Source */
{ 0x0949, 0x0080 }, /* R2377 - DSP1RMIX Input 1 Volume */
{ 0x094A, 0x0000 }, /* R2378 - DSP1RMIX Input 2 Source */
{ 0x094B, 0x0080 }, /* R2379 - DSP1RMIX Input 2 Volume */
{ 0x094C, 0x0000 }, /* R2380 - DSP1RMIX Input 3 Source */
{ 0x094D, 0x0080 }, /* R2381 - DSP1RMIX Input 3 Volume */
{ 0x094E, 0x0000 }, /* R2382 - DSP1RMIX Input 4 Source */
{ 0x094F, 0x0080 }, /* R2383 - DSP1RMIX Input 4 Volume */
{ 0x0950, 0x0000 }, /* R2384 - DSP1AUX1MIX Input 1 Source */
{ 0x0958, 0x0000 }, /* R2392 - DSP1AUX2MIX Input 1 Source */
{ 0x0960, 0x0000 }, /* R2400 - DSP1AUX3MIX Input 1 Source */
{ 0x0968, 0x0000 }, /* R2408 - DSP1AUX4MIX Input 1 Source */
{ 0x0970, 0x0000 }, /* R2416 - DSP1AUX5MIX Input 1 Source */
{ 0x0978, 0x0000 }, /* R2424 - DSP1AUX6MIX Input 1 Source */
{ 0x0980, 0x0000 }, /* R2432 - DSP2LMIX Input 1 Source */
{ 0x0981, 0x0080 }, /* R2433 - DSP2LMIX Input 1 Volume */
{ 0x0982, 0x0000 }, /* R2434 - DSP2LMIX Input 2 Source */
{ 0x0983, 0x0080 }, /* R2435 - DSP2LMIX Input 2 Volume */
{ 0x0984, 0x0000 }, /* R2436 - DSP2LMIX Input 3 Source */
{ 0x0985, 0x0080 }, /* R2437 - DSP2LMIX Input 3 Volume */
{ 0x0986, 0x0000 }, /* R2438 - DSP2LMIX Input 4 Source */
{ 0x0987, 0x0080 }, /* R2439 - DSP2LMIX Input 4 Volume */
{ 0x0988, 0x0000 }, /* R2440 - DSP2RMIX Input 1 Source */
{ 0x0989, 0x0080 }, /* R2441 - DSP2RMIX Input 1 Volume */
{ 0x098A, 0x0000 }, /* R2442 - DSP2RMIX Input 2 Source */
{ 0x098B, 0x0080 }, /* R2443 - DSP2RMIX Input 2 Volume */
{ 0x098C, 0x0000 }, /* R2444 - DSP2RMIX Input 3 Source */
{ 0x098D, 0x0080 }, /* R2445 - DSP2RMIX Input 3 Volume */
{ 0x098E, 0x0000 }, /* R2446 - DSP2RMIX Input 4 Source */
{ 0x098F, 0x0080 }, /* R2447 - DSP2RMIX Input 4 Volume */
{ 0x0990, 0x0000 }, /* R2448 - DSP2AUX1MIX Input 1 Source */
{ 0x0998, 0x0000 }, /* R2456 - DSP2AUX2MIX Input 1 Source */
{ 0x09A0, 0x0000 }, /* R2464 - DSP2AUX3MIX Input 1 Source */
{ 0x09A8, 0x0000 }, /* R2472 - DSP2AUX4MIX Input 1 Source */
{ 0x09B0, 0x0000 }, /* R2480 - DSP2AUX5MIX Input 1 Source */
{ 0x09B8, 0x0000 }, /* R2488 - DSP2AUX6MIX Input 1 Source */
{ 0x09C0, 0x0000 }, /* R2496 - DSP3LMIX Input 1 Source */
{ 0x09C1, 0x0080 }, /* R2497 - DSP3LMIX Input 1 Volume */
{ 0x09C2, 0x0000 }, /* R2498 - DSP3LMIX Input 2 Source */
{ 0x09C3, 0x0080 }, /* R2499 - DSP3LMIX Input 2 Volume */
{ 0x09C4, 0x0000 }, /* R2500 - DSP3LMIX Input 3 Source */
{ 0x09C5, 0x0080 }, /* R2501 - DSP3LMIX Input 3 Volume */
{ 0x09C6, 0x0000 }, /* R2502 - DSP3LMIX Input 4 Source */
{ 0x09C7, 0x0080 }, /* R2503 - DSP3LMIX Input 4 Volume */
{ 0x09C8, 0x0000 }, /* R2504 - DSP3RMIX Input 1 Source */
{ 0x09C9, 0x0080 }, /* R2505 - DSP3RMIX Input 1 Volume */
{ 0x09CA, 0x0000 }, /* R2506 - DSP3RMIX Input 2 Source */
{ 0x09CB, 0x0080 }, /* R2507 - DSP3RMIX Input 2 Volume */
{ 0x09CC, 0x0000 }, /* R2508 - DSP3RMIX Input 3 Source */
{ 0x09CD, 0x0080 }, /* R2509 - DSP3RMIX Input 3 Volume */
{ 0x09CE, 0x0000 }, /* R2510 - DSP3RMIX Input 4 Source */
{ 0x09CF, 0x0080 }, /* R2511 - DSP3RMIX Input 4 Volume */
{ 0x09D0, 0x0000 }, /* R2512 - DSP3AUX1MIX Input 1 Source */
{ 0x09D8, 0x0000 }, /* R2520 - DSP3AUX2MIX Input 1 Source */
{ 0x09E0, 0x0000 }, /* R2528 - DSP3AUX3MIX Input 1 Source */
{ 0x09E8, 0x0000 }, /* R2536 - DSP3AUX4MIX Input 1 Source */
{ 0x09F0, 0x0000 }, /* R2544 - DSP3AUX5MIX Input 1 Source */
{ 0x09F8, 0x0000 }, /* R2552 - DSP3AUX6MIX Input 1 Source */
{ 0x0A80, 0x0000 }, /* R2688 - ASRC1LMIX Input 1 Source */
{ 0x0A88, 0x0000 }, /* R2696 - ASRC1RMIX Input 1 Source */
{ 0x0A90, 0x0000 }, /* R2704 - ASRC2LMIX Input 1 Source */
{ 0x0A98, 0x0000 }, /* R2712 - ASRC2RMIX Input 1 Source */
{ 0x0B00, 0x0000 }, /* R2816 - ISRC1DEC1MIX Input 1 Source */
{ 0x0B08, 0x0000 }, /* R2824 - ISRC1DEC2MIX Input 1 Source */
{ 0x0B10, 0x0000 }, /* R2832 - ISRC1DEC3MIX Input 1 Source */
{ 0x0B18, 0x0000 }, /* R2840 - ISRC1DEC4MIX Input 1 Source */
{ 0x0B20, 0x0000 }, /* R2848 - ISRC1INT1MIX Input 1 Source */
{ 0x0B28, 0x0000 }, /* R2856 - ISRC1INT2MIX Input 1 Source */
{ 0x0B30, 0x0000 }, /* R2864 - ISRC1INT3MIX Input 1 Source */
{ 0x0B38, 0x0000 }, /* R2872 - ISRC1INT4MIX Input 1 Source */
{ 0x0B40, 0x0000 }, /* R2880 - ISRC2DEC1MIX Input 1 Source */
{ 0x0B48, 0x0000 }, /* R2888 - ISRC2DEC2MIX Input 1 Source */
{ 0x0B50, 0x0000 }, /* R2896 - ISRC2DEC3MIX Input 1 Source */
{ 0x0B58, 0x0000 }, /* R2904 - ISRC2DEC4MIX Input 1 Source */
{ 0x0B60, 0x0000 }, /* R2912 - ISRC2INT1MIX Input 1 Source */
{ 0x0B68, 0x0000 }, /* R2920 - ISRC2INT2MIX Input 1 Source */
{ 0x0B70, 0x0000 }, /* R2928 - ISRC2INT3MIX Input 1 Source */
{ 0x0B78, 0x0000 }, /* R2936 - ISRC2INT4MIX Input 1 Source */
{ 0x0C00, 0xA001 }, /* R3072 - GPIO CTRL 1 */
{ 0x0C01, 0xA001 }, /* R3073 - GPIO CTRL 2 */
{ 0x0C02, 0xA001 }, /* R3074 - GPIO CTRL 3 */
{ 0x0C03, 0xA001 }, /* R3075 - GPIO CTRL 4 */
{ 0x0C04, 0xA001 }, /* R3076 - GPIO CTRL 5 */
{ 0x0C05, 0xA001 }, /* R3077 - GPIO CTRL 6 */
{ 0x0C23, 0x4003 }, /* R3107 - Misc Pad Ctrl 1 */
{ 0x0C24, 0x0000 }, /* R3108 - Misc Pad Ctrl 2 */
{ 0x0C25, 0x0000 }, /* R3109 - Misc Pad Ctrl 3 */
{ 0x0C26, 0x0000 }, /* R3110 - Misc Pad Ctrl 4 */
{ 0x0C27, 0x0000 }, /* R3111 - Misc Pad Ctrl 5 */
{ 0x0C28, 0x0000 }, /* R3112 - Misc GPIO 1 */
{ 0x0D00, 0x0000 }, /* R3328 - Interrupt Status 1 */
{ 0x0D01, 0x0000 }, /* R3329 - Interrupt Status 2 */
{ 0x0D02, 0x0000 }, /* R3330 - Interrupt Status 3 */
{ 0x0D03, 0x0000 }, /* R3331 - Interrupt Status 4 */
{ 0x0D04, 0x0000 }, /* R3332 - Interrupt Raw Status 2 */
{ 0x0D05, 0x0000 }, /* R3333 - Interrupt Raw Status 3 */
{ 0x0D06, 0x0000 }, /* R3334 - Interrupt Raw Status 4 */
{ 0x0D07, 0xFFFF }, /* R3335 - Interrupt Status 1 Mask */
{ 0x0D08, 0xFFFF }, /* R3336 - Interrupt Status 2 Mask */
{ 0x0D09, 0xFFFF }, /* R3337 - Interrupt Status 3 Mask */
{ 0x0D0A, 0xFFFF }, /* R3338 - Interrupt Status 4 Mask */
{ 0x0D1F, 0x0000 }, /* R3359 - Interrupt Control */
{ 0x0D20, 0xFFFF }, /* R3360 - IRQ Debounce 1 */
{ 0x0D21, 0xFFFF }, /* R3361 - IRQ Debounce 2 */
{ 0x0E00, 0x0000 }, /* R3584 - FX_Ctrl */
{ 0x0E10, 0x6318 }, /* R3600 - EQ1_1 */
{ 0x0E11, 0x6300 }, /* R3601 - EQ1_2 */
{ 0x0E12, 0x0FC8 }, /* R3602 - EQ1_3 */
{ 0x0E13, 0x03FE }, /* R3603 - EQ1_4 */
{ 0x0E14, 0x00E0 }, /* R3604 - EQ1_5 */
{ 0x0E15, 0x1EC4 }, /* R3605 - EQ1_6 */
{ 0x0E16, 0xF136 }, /* R3606 - EQ1_7 */
{ 0x0E17, 0x0409 }, /* R3607 - EQ1_8 */
{ 0x0E18, 0x04CC }, /* R3608 - EQ1_9 */
{ 0x0E19, 0x1C9B }, /* R3609 - EQ1_10 */
{ 0x0E1A, 0xF337 }, /* R3610 - EQ1_11 */
{ 0x0E1B, 0x040B }, /* R3611 - EQ1_12 */
{ 0x0E1C, 0x0CBB }, /* R3612 - EQ1_13 */
{ 0x0E1D, 0x16F8 }, /* R3613 - EQ1_14 */
{ 0x0E1E, 0xF7D9 }, /* R3614 - EQ1_15 */
{ 0x0E1F, 0x040A }, /* R3615 - EQ1_16 */
{ 0x0E20, 0x1F14 }, /* R3616 - EQ1_17 */
{ 0x0E21, 0x058C }, /* R3617 - EQ1_18 */
{ 0x0E22, 0x0563 }, /* R3618 - EQ1_19 */
{ 0x0E23, 0x4000 }, /* R3619 - EQ1_20 */
{ 0x0E26, 0x6318 }, /* R3622 - EQ2_1 */
{ 0x0E27, 0x6300 }, /* R3623 - EQ2_2 */
{ 0x0E28, 0x0FC8 }, /* R3624 - EQ2_3 */
{ 0x0E29, 0x03FE }, /* R3625 - EQ2_4 */
{ 0x0E2A, 0x00E0 }, /* R3626 - EQ2_5 */
{ 0x0E2B, 0x1EC4 }, /* R3627 - EQ2_6 */
{ 0x0E2C, 0xF136 }, /* R3628 - EQ2_7 */
{ 0x0E2D, 0x0409 }, /* R3629 - EQ2_8 */
{ 0x0E2E, 0x04CC }, /* R3630 - EQ2_9 */
{ 0x0E2F, 0x1C9B }, /* R3631 - EQ2_10 */
{ 0x0E30, 0xF337 }, /* R3632 - EQ2_11 */
{ 0x0E31, 0x040B }, /* R3633 - EQ2_12 */
{ 0x0E32, 0x0CBB }, /* R3634 - EQ2_13 */
{ 0x0E33, 0x16F8 }, /* R3635 - EQ2_14 */
{ 0x0E34, 0xF7D9 }, /* R3636 - EQ2_15 */
{ 0x0E35, 0x040A }, /* R3637 - EQ2_16 */
{ 0x0E36, 0x1F14 }, /* R3638 - EQ2_17 */
{ 0x0E37, 0x058C }, /* R3639 - EQ2_18 */
{ 0x0E38, 0x0563 }, /* R3640 - EQ2_19 */
{ 0x0E39, 0x4000 }, /* R3641 - EQ2_20 */
{ 0x0E3C, 0x6318 }, /* R3644 - EQ3_1 */
{ 0x0E3D, 0x6300 }, /* R3645 - EQ3_2 */
{ 0x0E3E, 0x0FC8 }, /* R3646 - EQ3_3 */
{ 0x0E3F, 0x03FE }, /* R3647 - EQ3_4 */
{ 0x0E40, 0x00E0 }, /* R3648 - EQ3_5 */
{ 0x0E41, 0x1EC4 }, /* R3649 - EQ3_6 */
{ 0x0E42, 0xF136 }, /* R3650 - EQ3_7 */
{ 0x0E43, 0x0409 }, /* R3651 - EQ3_8 */
{ 0x0E44, 0x04CC }, /* R3652 - EQ3_9 */
{ 0x0E45, 0x1C9B }, /* R3653 - EQ3_10 */
{ 0x0E46, 0xF337 }, /* R3654 - EQ3_11 */
{ 0x0E47, 0x040B }, /* R3655 - EQ3_12 */
{ 0x0E48, 0x0CBB }, /* R3656 - EQ3_13 */
{ 0x0E49, 0x16F8 }, /* R3657 - EQ3_14 */
{ 0x0E4A, 0xF7D9 }, /* R3658 - EQ3_15 */
{ 0x0E4B, 0x040A }, /* R3659 - EQ3_16 */
{ 0x0E4C, 0x1F14 }, /* R3660 - EQ3_17 */
{ 0x0E4D, 0x058C }, /* R3661 - EQ3_18 */
{ 0x0E4E, 0x0563 }, /* R3662 - EQ3_19 */
{ 0x0E4F, 0x4000 }, /* R3663 - EQ3_20 */
{ 0x0E52, 0x6318 }, /* R3666 - EQ4_1 */
{ 0x0E53, 0x6300 }, /* R3667 - EQ4_2 */
{ 0x0E54, 0x0FC8 }, /* R3668 - EQ4_3 */
{ 0x0E55, 0x03FE }, /* R3669 - EQ4_4 */
{ 0x0E56, 0x00E0 }, /* R3670 - EQ4_5 */
{ 0x0E57, 0x1EC4 }, /* R3671 - EQ4_6 */
{ 0x0E58, 0xF136 }, /* R3672 - EQ4_7 */
{ 0x0E59, 0x0409 }, /* R3673 - EQ4_8 */
{ 0x0E5A, 0x04CC }, /* R3674 - EQ4_9 */
{ 0x0E5B, 0x1C9B }, /* R3675 - EQ4_10 */
{ 0x0E5C, 0xF337 }, /* R3676 - EQ4_11 */
{ 0x0E5D, 0x040B }, /* R3677 - EQ4_12 */
{ 0x0E5E, 0x0CBB }, /* R3678 - EQ4_13 */
{ 0x0E5F, 0x16F8 }, /* R3679 - EQ4_14 */
{ 0x0E60, 0xF7D9 }, /* R3680 - EQ4_15 */
{ 0x0E61, 0x040A }, /* R3681 - EQ4_16 */
{ 0x0E62, 0x1F14 }, /* R3682 - EQ4_17 */
{ 0x0E63, 0x058C }, /* R3683 - EQ4_18 */
{ 0x0E64, 0x0563 }, /* R3684 - EQ4_19 */
{ 0x0E65, 0x4000 }, /* R3685 - EQ4_20 */
{ 0x0E80, 0x0018 }, /* R3712 - DRC1 ctrl1 */
{ 0x0E81, 0x0933 }, /* R3713 - DRC1 ctrl2 */
{ 0x0E82, 0x0018 }, /* R3714 - DRC1 ctrl3 */
{ 0x0E83, 0x0000 }, /* R3715 - DRC1 ctrl4 */
{ 0x0E84, 0x0000 }, /* R3716 - DRC1 ctrl5 */
{ 0x0EC0, 0x0000 }, /* R3776 - HPLPF1_1 */
{ 0x0EC1, 0x0000 }, /* R3777 - HPLPF1_2 */
{ 0x0EC4, 0x0000 }, /* R3780 - HPLPF2_1 */
{ 0x0EC5, 0x0000 }, /* R3781 - HPLPF2_2 */
{ 0x0EC8, 0x0000 }, /* R3784 - HPLPF3_1 */
{ 0x0EC9, 0x0000 }, /* R3785 - HPLPF3_2 */
{ 0x0ECC, 0x0000 }, /* R3788 - HPLPF4_1 */
{ 0x0ECD, 0x0000 }, /* R3789 - HPLPF4_2 */
{ 0x0F02, 0x0000 }, /* R3842 - DSP1 Control 2 */
{ 0x0F03, 0x0000 }, /* R3843 - DSP1 Control 3 */
{ 0x0F04, 0x0000 }, /* R3844 - DSP1 Control 4 */
{ 0x1002, 0x0000 }, /* R4098 - DSP2 Control 2 */
{ 0x1003, 0x0000 }, /* R4099 - DSP2 Control 3 */
{ 0x1004, 0x0000 }, /* R4100 - DSP2 Control 4 */
{ 0x1102, 0x0000 }, /* R4354 - DSP3 Control 2 */
{ 0x1103, 0x0000 }, /* R4355 - DSP3 Control 3 */
{ 0x1104, 0x0000 }, /* R4356 - DSP3 Control 4 */
};
| linux-master | sound/soc/codecs/wm5100-tables.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* PCM179X ASoC I2C driver
*
* Copyright (c) Teenage Engineering AB 2016
*
* Jacob Siverskog <[email protected]>
*/
#include <linux/module.h>
#include <linux/of.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include "pcm179x.h"
static int pcm179x_i2c_probe(struct i2c_client *client)
{
struct regmap *regmap;
int ret;
regmap = devm_regmap_init_i2c(client, &pcm179x_regmap_config);
if (IS_ERR(regmap)) {
ret = PTR_ERR(regmap);
dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret);
return ret;
}
return pcm179x_common_init(&client->dev, regmap);
}
#ifdef CONFIG_OF
static const struct of_device_id pcm179x_of_match[] = {
{ .compatible = "ti,pcm1792a", },
{ }
};
MODULE_DEVICE_TABLE(of, pcm179x_of_match);
#endif
static const struct i2c_device_id pcm179x_i2c_ids[] = {
{ "pcm179x", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, pcm179x_i2c_ids);
static struct i2c_driver pcm179x_i2c_driver = {
.driver = {
.name = "pcm179x",
.of_match_table = of_match_ptr(pcm179x_of_match),
},
.id_table = pcm179x_i2c_ids,
.probe = pcm179x_i2c_probe,
};
module_i2c_driver(pcm179x_i2c_driver);
MODULE_DESCRIPTION("ASoC PCM179X I2C driver");
MODULE_AUTHOR("Jacob Siverskog <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/pcm179x-i2c.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Driver for ADAU1381/ADAU1781 CODEC
*
* Copyright 2014 Analog Devices Inc.
* Author: Lars-Peter Clausen <[email protected]>
*/
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include <sound/soc.h>
#include "adau1781.h"
static void adau1781_spi_switch_mode(struct device *dev)
{
struct spi_device *spi = to_spi_device(dev);
/*
* To get the device into SPI mode CLATCH has to be pulled low three
* times. Do this by issuing three dummy reads.
*/
spi_w8r8(spi, 0x00);
spi_w8r8(spi, 0x00);
spi_w8r8(spi, 0x00);
}
static int adau1781_spi_probe(struct spi_device *spi)
{
const struct spi_device_id *id = spi_get_device_id(spi);
struct regmap_config config;
if (!id)
return -EINVAL;
config = adau1781_regmap_config;
config.val_bits = 8;
config.reg_bits = 24;
config.read_flag_mask = 0x1;
return adau1781_probe(&spi->dev,
devm_regmap_init_spi(spi, &config),
id->driver_data, adau1781_spi_switch_mode);
}
static void adau1781_spi_remove(struct spi_device *spi)
{
adau17x1_remove(&spi->dev);
}
static const struct spi_device_id adau1781_spi_id[] = {
{ "adau1381", ADAU1381 },
{ "adau1781", ADAU1781 },
{ }
};
MODULE_DEVICE_TABLE(spi, adau1781_spi_id);
#if defined(CONFIG_OF)
static const struct of_device_id adau1781_spi_dt_ids[] = {
{ .compatible = "adi,adau1381", },
{ .compatible = "adi,adau1781", },
{ },
};
MODULE_DEVICE_TABLE(of, adau1781_spi_dt_ids);
#endif
static struct spi_driver adau1781_spi_driver = {
.driver = {
.name = "adau1781",
.of_match_table = of_match_ptr(adau1781_spi_dt_ids),
},
.probe = adau1781_spi_probe,
.remove = adau1781_spi_remove,
.id_table = adau1781_spi_id,
};
module_spi_driver(adau1781_spi_driver);
MODULE_DESCRIPTION("ASoC ADAU1381/ADAU1781 CODEC SPI driver");
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/adau1781-spi.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Linaro Ltd.
*/
#include <linux/bitfield.h>
#include <linux/device.h>
#include <linux/gpio/consumer.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <linux/soundwire/sdw.h>
#include <linux/soundwire/sdw_registers.h>
#include <linux/soundwire/sdw_type.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc-dapm.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#define WSA884X_BASE 0x3000
#define WSA884X_ANA_BG_TSADC_BASE (WSA884X_BASE + 0x0001)
#define WSA884X_BG_CTRL (WSA884X_ANA_BG_TSADC_BASE + 0x00)
#define WSA884X_ADC_CTRL (WSA884X_ANA_BG_TSADC_BASE + 0x01)
#define WSA884X_BOP1_PROG (WSA884X_ANA_BG_TSADC_BASE + 0x02)
#define WSA884X_BOP2_PROG (WSA884X_ANA_BG_TSADC_BASE + 0x03)
#define WSA884X_BOP2_PROG_BOP2_VTH_MASK 0xf0
#define WSA884X_BOP2_PROG_BOP2_VTH_SHIFT 4
#define WSA884X_BOP2_PROG_BOP2_HYST_MASK 0x0f
#define WSA884X_BOP2_PROG_BOP2_HYST_SHIFT 0
#define WSA884X_UVLO_PROG (WSA884X_ANA_BG_TSADC_BASE + 0x04)
#define WSA884X_UVLO_PROG1 (WSA884X_ANA_BG_TSADC_BASE + 0x05)
#define WSA884X_SPARE_CTRL_0 (WSA884X_ANA_BG_TSADC_BASE + 0x06)
#define WSA884X_SPARE_CTRL_1 (WSA884X_ANA_BG_TSADC_BASE + 0x07)
#define WSA884X_SPARE_CTRL_2 (WSA884X_ANA_BG_TSADC_BASE + 0x08)
#define WSA884X_SPARE_CTRL_3 (WSA884X_ANA_BG_TSADC_BASE + 0x09)
#define WSA884X_REF_CTRL (WSA884X_ANA_BG_TSADC_BASE + 0x0a)
#define WSA884X_REF_CTRL_BG_RDY_SEL_MASK 0x03
#define WSA884X_REF_CTRL_BG_RDY_SEL_SHIFT 0
#define WSA884X_BG_TEST_CTL (WSA884X_ANA_BG_TSADC_BASE + 0x0b)
#define WSA884X_BG_BIAS (WSA884X_ANA_BG_TSADC_BASE + 0x0c)
#define WSA884X_ADC_PROG (WSA884X_ANA_BG_TSADC_BASE + 0x0d)
#define WSA884X_ADC_IREF_CTL (WSA884X_ANA_BG_TSADC_BASE + 0x0e)
#define WSA884X_ADC_ISENS_CTL (WSA884X_ANA_BG_TSADC_BASE + 0x0f)
#define WSA884X_ADC_CLK_CTL (WSA884X_ANA_BG_TSADC_BASE + 0x10)
#define WSA884X_ADC_TEST_CTL (WSA884X_ANA_BG_TSADC_BASE + 0x11)
#define WSA884X_ADC_BIAS (WSA884X_ANA_BG_TSADC_BASE + 0x12)
#define WSA884X_VBAT_SNS (WSA884X_ANA_BG_TSADC_BASE + 0x13)
#define WSA884X_DOUT_MSB (WSA884X_ANA_BG_TSADC_BASE + 0x14)
#define WSA884X_DOUT_LSB (WSA884X_ANA_BG_TSADC_BASE + 0x15)
#define WSA884X_BOP_ATEST_SEL (WSA884X_ANA_BG_TSADC_BASE + 0x16)
#define WSA884X_MISC0 (WSA884X_ANA_BG_TSADC_BASE + 0x17)
#define WSA884X_MISC1 (WSA884X_ANA_BG_TSADC_BASE + 0x18)
#define WSA884X_MISC2 (WSA884X_ANA_BG_TSADC_BASE + 0x19)
#define WSA884X_MISC3 (WSA884X_ANA_BG_TSADC_BASE + 0x1a)
#define WSA884X_SPARE_TSBG_0 (WSA884X_ANA_BG_TSADC_BASE + 0x1b)
#define WSA884X_SPARE_TUNE_0 (WSA884X_ANA_BG_TSADC_BASE + 0x1c)
#define WSA884X_SPARE_TUNE_1 (WSA884X_ANA_BG_TSADC_BASE + 0x1d)
#define WSA884X_ANA_IVSENSE_BASE (WSA884X_BASE + 0x0020)
#define WSA884X_VSENSE1 (WSA884X_ANA_IVSENSE_BASE + 0x00)
#define WSA884X_VSENSE1_GAIN_VSENSE_FE_MASK 0xe0
#define WSA884X_VSENSE1_GAIN_VSENSE_FE_SHIFT 5
#define WSA884X_ISENSE2 (WSA884X_ANA_IVSENSE_BASE + 0x01)
#define WSA884X_ISENSE2_ISENSE_GAIN_CTL_MASK 0xe0
#define WSA884X_ISENSE2_ISENSE_GAIN_CTL_SHIFT 5
#define WSA884X_SPARE_CTL_1 (WSA884X_ANA_IVSENSE_BASE + 0x02)
#define WSA884X_SPARE_CTL_2 (WSA884X_ANA_IVSENSE_BASE + 0x03)
#define WSA884X_SPARE_CTL_3 (WSA884X_ANA_IVSENSE_BASE + 0x04)
#define WSA884X_SPARE_CTL_4 (WSA884X_ANA_IVSENSE_BASE + 0x05)
#define WSA884X_EN (WSA884X_ANA_IVSENSE_BASE + 0x06)
#define WSA884X_OVERRIDE1 (WSA884X_ANA_IVSENSE_BASE + 0x07)
#define WSA884X_OVERRIDE2 (WSA884X_ANA_IVSENSE_BASE + 0x08)
#define WSA884X_ISENSE1 (WSA884X_ANA_IVSENSE_BASE + 0x09)
#define WSA884X_ISENSE_CAL (WSA884X_ANA_IVSENSE_BASE + 0x0a)
#define WSA884X_MISC (WSA884X_ANA_IVSENSE_BASE + 0x0b)
#define WSA884X_ADC_0 (WSA884X_ANA_IVSENSE_BASE + 0x0c)
#define WSA884X_ADC_1 (WSA884X_ANA_IVSENSE_BASE + 0x0d)
#define WSA884X_ADC_2 (WSA884X_ANA_IVSENSE_BASE + 0x0e)
#define WSA884X_ADC_3 (WSA884X_ANA_IVSENSE_BASE + 0x0f)
#define WSA884X_ADC_4 (WSA884X_ANA_IVSENSE_BASE + 0x10)
#define WSA884X_ADC_5 (WSA884X_ANA_IVSENSE_BASE + 0x11)
#define WSA884X_ADC_6 (WSA884X_ANA_IVSENSE_BASE + 0x12)
#define WSA884X_ADC_7 (WSA884X_ANA_IVSENSE_BASE + 0x13)
#define WSA884X_STATUS (WSA884X_ANA_IVSENSE_BASE + 0x14)
#define WSA884X_IVSENSE_SPARE_TUNE_1 (WSA884X_ANA_IVSENSE_BASE + 0x15)
#define WSA884X_SPARE_TUNE_2 (WSA884X_ANA_IVSENSE_BASE + 0x16)
#define WSA884X_SPARE_TUNE_3 (WSA884X_ANA_IVSENSE_BASE + 0x17)
#define WSA884X_SPARE_TUNE_4 (WSA884X_ANA_IVSENSE_BASE + 0x18)
#define WSA884X_ANA_SPK_TOP_BASE (WSA884X_BASE + 0x0040)
#define WSA884X_TOP_CTRL1 (WSA884X_ANA_SPK_TOP_BASE + 0x00)
#define WSA884X_TOP_CTRL1_OCP_LOWVBAT_ITH_EN_MASK 0x01
#define WSA884X_CLIP_DET_CTRL1 (WSA884X_ANA_SPK_TOP_BASE + 0x01)
#define WSA884X_CLIP_DET_CTRL2 (WSA884X_ANA_SPK_TOP_BASE + 0x02)
#define WSA884X_DAC_CTRL1 (WSA884X_ANA_SPK_TOP_BASE + 0x03)
#define WSA884X_DAC_VCM_CTRL_REG1 (WSA884X_ANA_SPK_TOP_BASE + 0x04)
#define WSA884X_DAC_VCM_CTRL_REG2 (WSA884X_ANA_SPK_TOP_BASE + 0x05)
#define WSA884X_DAC_VCM_CTRL_REG3 (WSA884X_ANA_SPK_TOP_BASE + 0x06)
#define WSA884X_DAC_VCM_CTRL_REG4 (WSA884X_ANA_SPK_TOP_BASE + 0x07)
#define WSA884X_DAC_VCM_CTRL_REG5 (WSA884X_ANA_SPK_TOP_BASE + 0x08)
#define WSA884X_DAC_VCM_CTRL_REG6 (WSA884X_ANA_SPK_TOP_BASE + 0x09)
#define WSA884X_PWM_CLK_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x0a)
#define WSA884X_PWM_CLK_CTL_VCMO_INT1_IDLE_MODE_OVRT_MASK 0x80
#define WSA884X_PWM_CLK_CTL_VCMO_INT1_IDLE_MODE_OVRT_SHIFT 7
#define WSA884X_PWM_CLK_CTL_REG_MCLK_DIV_RATIO_MASK 0x40
#define WSA884X_PWM_CLK_CTL_REG_MCLK_DIV_RATIO_SHIFT 6
#define WSA884X_PWM_CLK_CTL_PWM_DEGLITCH_CLK_DELAY_CTRL_MASK 0x30
#define WSA884X_PWM_CLK_CTL_PWM_DEGLITCH_CLK_DELAY_CTRL_SHIFT 4
#define WSA884X_PWM_CLK_CTL_PWM_CLK_FREQ_SEL_MASK 0x08
#define WSA884X_PWM_CLK_CTL_PWM_CLK_FREQ_SEL_SHIFT 3
#define WSA884X_PWM_CLK_CTL_PWM_CLK_DIV_RATIO_MASK 0x06
#define WSA884X_PWM_CLK_CTL_PWM_CLK_DIV_RATIO_SHIFT 1
#define WSA884X_PWM_CLK_CTL_PWM_CLK_DIV_BYPASS_MASK 0x01
#define WSA884X_PWM_CLK_CTL_PWM_CLK_DIV_BYPASS_SHIFT 0
#define WSA884X_DRV_LF_LDO_SEL (WSA884X_ANA_SPK_TOP_BASE + 0x0b)
#define WSA884X_OCP_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x0c)
#define WSA884X_PDRV_HS_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x0d)
#define WSA884X_PDRV_LS_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x0e)
#define WSA884X_SPK_TOP_SPARE_CTL_1 (WSA884X_ANA_SPK_TOP_BASE + 0x0f)
#define WSA884X_SPK_TOP_SPARE_CTL_2 (WSA884X_ANA_SPK_TOP_BASE + 0x10)
#define WSA884X_SPK_TOP_SPARE_CTL_3 (WSA884X_ANA_SPK_TOP_BASE + 0x11)
#define WSA884X_SPK_TOP_SPARE_CTL_4 (WSA884X_ANA_SPK_TOP_BASE + 0x12)
#define WSA884X_SPARE_CTL_5 (WSA884X_ANA_SPK_TOP_BASE + 0x13)
#define WSA884X_DAC_EN_DEBUG_REG (WSA884X_ANA_SPK_TOP_BASE + 0x14)
#define WSA884X_DAC_OPAMP_BIAS1_REG (WSA884X_ANA_SPK_TOP_BASE + 0x15)
#define WSA884X_DAC_OPAMP_BIAS2_REG (WSA884X_ANA_SPK_TOP_BASE + 0x16)
#define WSA884X_DAC_TUNE1 (WSA884X_ANA_SPK_TOP_BASE + 0x17)
#define WSA884X_DAC_VOLTAGE_CTRL_REG (WSA884X_ANA_SPK_TOP_BASE + 0x18)
#define WSA884X_ATEST1_REG (WSA884X_ANA_SPK_TOP_BASE + 0x19)
#define WSA884X_ATEST2_REG (WSA884X_ANA_SPK_TOP_BASE + 0x1a)
#define WSA884X_TOP_BIAS_REG1 (WSA884X_ANA_SPK_TOP_BASE + 0x1b)
#define WSA884X_TOP_BIAS_REG2 (WSA884X_ANA_SPK_TOP_BASE + 0x1c)
#define WSA884X_TOP_BIAS_REG3 (WSA884X_ANA_SPK_TOP_BASE + 0x1d)
#define WSA884X_TOP_BIAS_REG4 (WSA884X_ANA_SPK_TOP_BASE + 0x1e)
#define WSA884X_PWRSTG_DBG2 (WSA884X_ANA_SPK_TOP_BASE + 0x1f)
#define WSA884X_DRV_LF_BLK_EN (WSA884X_ANA_SPK_TOP_BASE + 0x20)
#define WSA884X_DRV_LF_EN (WSA884X_ANA_SPK_TOP_BASE + 0x21)
#define WSA884X_DRV_LF_MASK_DCC_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x22)
#define WSA884X_DRV_LF_MISC_CTL1 (WSA884X_ANA_SPK_TOP_BASE + 0x23)
#define WSA884X_DRV_LF_REG_GAIN (WSA884X_ANA_SPK_TOP_BASE + 0x24)
#define WSA884X_DRV_OS_CAL_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x25)
#define WSA884X_DRV_OS_CAL_CTL1 (WSA884X_ANA_SPK_TOP_BASE + 0x26)
#define WSA884X_PWRSTG_DBG (WSA884X_ANA_SPK_TOP_BASE + 0x27)
#define WSA884X_BBM_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x28)
#define WSA884X_TOP_MISC1 (WSA884X_ANA_SPK_TOP_BASE + 0x29)
#define WSA884X_DAC_VCM_CTRL_REG7 (WSA884X_ANA_SPK_TOP_BASE + 0x2a)
#define WSA884X_TOP_BIAS_REG5 (WSA884X_ANA_SPK_TOP_BASE + 0x2b)
#define WSA884X_DRV_LF_MISC_CTL2 (WSA884X_ANA_SPK_TOP_BASE + 0x2c)
#define WSA884X_SPK_TOP_SPARE_TUNE_2 (WSA884X_ANA_SPK_TOP_BASE + 0x2d)
#define WSA884X_SPK_TOP_SPARE_TUNE_3 (WSA884X_ANA_SPK_TOP_BASE + 0x2e)
#define WSA884X_SPK_TOP_SPARE_TUNE_4 (WSA884X_ANA_SPK_TOP_BASE + 0x2f)
#define WSA884X_SPARE_TUNE_5 (WSA884X_ANA_SPK_TOP_BASE + 0x30)
#define WSA884X_SPARE_TUNE_6 (WSA884X_ANA_SPK_TOP_BASE + 0x31)
#define WSA884X_SPARE_TUNE_7 (WSA884X_ANA_SPK_TOP_BASE + 0x32)
#define WSA884X_SPARE_TUNE_8 (WSA884X_ANA_SPK_TOP_BASE + 0x33)
#define WSA884X_SPARE_TUNE_9 (WSA884X_ANA_SPK_TOP_BASE + 0x34)
#define WSA884X_SPARE_TUNE_10 (WSA884X_ANA_SPK_TOP_BASE + 0x35)
#define WSA884X_PA_STATUS0 (WSA884X_ANA_SPK_TOP_BASE + 0x36)
#define WSA884X_PA_STATUS1 (WSA884X_ANA_SPK_TOP_BASE + 0x37)
#define WSA884X_PA_STATUS2 (WSA884X_ANA_SPK_TOP_BASE + 0x38)
#define WSA884X_PA_STATUS3 (WSA884X_ANA_SPK_TOP_BASE + 0x39)
#define WSA884X_PA_STATUS4 (WSA884X_ANA_SPK_TOP_BASE + 0x3a)
#define WSA884X_PA_STATUS5 (WSA884X_ANA_SPK_TOP_BASE + 0x3b)
#define WSA884X_SPARE_RO_1 (WSA884X_ANA_SPK_TOP_BASE + 0x3c)
#define WSA884X_SPARE_RO_2 (WSA884X_ANA_SPK_TOP_BASE + 0x3d)
#define WSA884X_SPARE_RO_3 (WSA884X_ANA_SPK_TOP_BASE + 0x3e)
#define WSA884X_ANA_BOOST_BASE (WSA884X_BASE + 0x0090)
#define WSA884X_STB_CTRL1 (WSA884X_ANA_BOOST_BASE + 0x00)
#define WSA884X_STB_CTRL1_SLOPE_COMP_CURRENT_MASK 0xf8
#define WSA884X_STB_CTRL1_SLOPE_COMP_CURRENT_SHIFT 3
#define WSA884X_STB_CTRL1_VOUT_FS_MASK 0x07
#define WSA884X_STB_CTRL1_VOUT_FS_SHIFT 0
#define WSA884X_CURRENT_LIMIT (WSA884X_ANA_BOOST_BASE + 0x01)
#define WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_OVRD_EN_MASK 0x80
#define WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_OVRD_EN_SHIFT 7
#define WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_MASK 0x7c
#define WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_SHIFT 2
#define WSA884X_CURRENT_LIMIT_CLK_PHASE_SHIFT 0
#define WSA884X_BYP_CTRL1 (WSA884X_ANA_BOOST_BASE + 0x02)
#define WSA884X_SPARE_CTL_0 (WSA884X_ANA_BOOST_BASE + 0x03)
#define WSA884X_BOOST_SPARE_CTL_1 (WSA884X_ANA_BOOST_BASE + 0x04)
#define WSA884X_SPARE_RO_0 (WSA884X_ANA_BOOST_BASE + 0x05)
#define WSA884X_BOOST_SPARE_RO_1 (WSA884X_ANA_BOOST_BASE + 0x06)
#define WSA884X_IBIAS1 (WSA884X_ANA_BOOST_BASE + 0x07)
#define WSA884X_IBIAS2 (WSA884X_ANA_BOOST_BASE + 0x08)
#define WSA884X_IBIAS3 (WSA884X_ANA_BOOST_BASE + 0x09)
#define WSA884X_EN_CTRL (WSA884X_ANA_BOOST_BASE + 0x0a)
#define WSA884X_STB_CTRL2 (WSA884X_ANA_BOOST_BASE + 0x0b)
#define WSA884X_STB_CTRL3 (WSA884X_ANA_BOOST_BASE + 0x0c)
#define WSA884X_STB_CTRL4 (WSA884X_ANA_BOOST_BASE + 0x0d)
#define WSA884X_BYP_CTRL2 (WSA884X_ANA_BOOST_BASE + 0x0e)
#define WSA884X_BYP_CTRL3 (WSA884X_ANA_BOOST_BASE + 0x0f)
#define WSA884X_ZX_CTRL1 (WSA884X_ANA_BOOST_BASE + 0x10)
#define WSA884X_ZX_CTRL1_ZX_DET_EN_MASK 0x80
#define WSA884X_ZX_CTRL1_ZX_DET_EN_SHIFT 7
#define WSA884X_ZX_CTRL1_ZX_DET_SW_EN_MASK 0x40
#define WSA884X_ZX_CTRL1_ZX_DET_SW_EN_SHIFT 6
#define WSA884X_ZX_CTRL1_ZX_DET_STAGE_DEFAULT_MASK 0x20
#define WSA884X_ZX_CTRL1_ZX_DET_STAGE_DEFAULT_SHIFT 5
#define WSA884X_ZX_CTRL1_ZX_DET_SW_SEL_MASK 0x18
#define WSA884X_ZX_CTRL1_ZX_DET_SW_SEL_SHIFT 3
#define WSA884X_ZX_CTRL1_ZX_BYP_MASK_IGNORE_MASK 0x04
#define WSA884X_ZX_CTRL1_ZX_BYP_MASK_IGNORE_SHIFT 2
#define WSA884X_ZX_CTRL1_ZX_BYP_MASK_DEL_MASK 0x02
#define WSA884X_ZX_CTRL1_ZX_BYP_MASK_DEL_SHIFT 1
#define WSA884X_ZX_CTRL1_BOOTCAP_REFRESH_DIS_MASK 0x01
#define WSA884X_ZX_CTRL1_BOOTCAP_REFRESH_DIS_SHIFT 0
#define WSA884X_ZX_CTRL2 (WSA884X_ANA_BOOST_BASE + 0x11)
#define WSA884X_BLEEDER_CTRL (WSA884X_ANA_BOOST_BASE + 0x12)
#define WSA884X_BOOST_MISC (WSA884X_ANA_BOOST_BASE + 0x13)
#define WSA884X_PWRSTAGE_CTRL1 (WSA884X_ANA_BOOST_BASE + 0x14)
#define WSA884X_PWRSTAGE_CTRL2 (WSA884X_ANA_BOOST_BASE + 0x15)
#define WSA884X_PWRSTAGE_CTRL3 (WSA884X_ANA_BOOST_BASE + 0x16)
#define WSA884X_PWRSTAGE_CTRL4 (WSA884X_ANA_BOOST_BASE + 0x17)
#define WSA884X_MAXD_REG1 (WSA884X_ANA_BOOST_BASE + 0x18)
#define WSA884X_MAXD_REG2 (WSA884X_ANA_BOOST_BASE + 0x19)
#define WSA884X_ILIM_CTRL1 (WSA884X_ANA_BOOST_BASE + 0x1a)
#define WSA884X_ILIM_CTRL1_EN_AUTO_MAXD_SEL_MASK 0x80
#define WSA884X_ILIM_CTRL1_EN_AUTO_MAXD_SEL_SHIFT 0x07
#define WSA884X_ILIM_CTRL1_EN_ILIM_SW_CLH_MASK 0x40
#define WSA884X_ILIM_CTRL1_EN_ILIM_SW_CLH_SHIFT 0x06
#define WSA884X_ILIM_CTRL1_ILIM_OFFSET_CLH_MASK 0x38
#define WSA884X_ILIM_CTRL1_ILIM_OFFSET_CLH_SHIFT 0x03
#define WSA884X_ILIM_CTRL1_ILIM_OFFSET_PB_MASK 0x07
#define WSA884X_ILIM_CTRL1_ILIM_OFFSET_PB_SHIFT 0x00
#define WSA884X_ILIM_CTRL2 (WSA884X_ANA_BOOST_BASE + 0x1b)
#define WSA884X_TEST_CTRL1 (WSA884X_ANA_BOOST_BASE + 0x1c)
#define WSA884X_TEST_CTRL2 (WSA884X_ANA_BOOST_BASE + 0x1d)
#define WSA884X_SPARE1 (WSA884X_ANA_BOOST_BASE + 0x1e)
#define WSA884X_BOOT_CAP_CHECK (WSA884X_ANA_BOOST_BASE + 0x1f)
#define WSA884X_ANA_PON_LDOL_BASE (WSA884X_BASE + 0x00b0)
#define WSA884X_PON_CTL_0 (WSA884X_ANA_PON_LDOL_BASE + 0x00)
#define WSA884X_PWRSAV_CTL (WSA884X_ANA_PON_LDOL_BASE + 0x01)
#define WSA884X_PON_LDOL_SPARE_CTL_0 (WSA884X_ANA_PON_LDOL_BASE + 0x02)
#define WSA884X_PON_LDOL_SPARE_CTL_1 (WSA884X_ANA_PON_LDOL_BASE + 0x03)
#define WSA884X_PON_LDOL_SPARE_CTL_2 (WSA884X_ANA_PON_LDOL_BASE + 0x04)
#define WSA884X_PON_LDOL_SPARE_CTL_3 (WSA884X_ANA_PON_LDOL_BASE + 0x05)
#define WSA884X_PON_CLT_1 (WSA884X_ANA_PON_LDOL_BASE + 0x06)
#define WSA884X_PON_CTL_2 (WSA884X_ANA_PON_LDOL_BASE + 0x07)
#define WSA884X_PON_CTL_3 (WSA884X_ANA_PON_LDOL_BASE + 0x08)
#define WSA884X_CKWD_CTL_0 (WSA884X_ANA_PON_LDOL_BASE + 0x09)
#define WSA884X_CKWD_CTL_1 (WSA884X_ANA_PON_LDOL_BASE + 0x0a)
#define WSA884X_CKWD_CTL_1_VPP_SW_CTL_MASK 0x20
#define WSA884X_CKWD_CTL_1_VPP_SW_CTL_SHIFT 5
#define WSA884X_CKWD_CTL_1_CKWD_VCOMP_VREF_SEL_MASK 0x1f
#define WSA884X_CKWD_CTL_1_CKWD_VCOMP_VREF_SEL_SHIFT 0
#define WSA884X_CKWD_CTL_2 (WSA884X_ANA_PON_LDOL_BASE + 0x0b)
#define WSA884X_CKSK_CTL_0 (WSA884X_ANA_PON_LDOL_BASE + 0x0c)
#define WSA884X_PADSW_CTL_0 (WSA884X_ANA_PON_LDOL_BASE + 0x0d)
#define WSA884X_TEST_0 (WSA884X_ANA_PON_LDOL_BASE + 0x0e)
#define WSA884X_TEST_1 (WSA884X_ANA_PON_LDOL_BASE + 0x0f)
#define WSA884X_STATUS_0 (WSA884X_ANA_PON_LDOL_BASE + 0x10)
#define WSA884X_STATUS_1 (WSA884X_ANA_PON_LDOL_BASE + 0x11)
#define WSA884X_PON_LDOL_SPARE_TUNE_0 (WSA884X_ANA_PON_LDOL_BASE + 0x12)
#define WSA884X_PON_LDOL_SPARE_TUNE_1 (WSA884X_ANA_PON_LDOL_BASE + 0x13)
#define WSA884X_PON_LDOL_SPARE_TUNE_2 (WSA884X_ANA_PON_LDOL_BASE + 0x14)
#define WSA884X_PON_LDOL_SPARE_TUNE_3 (WSA884X_ANA_PON_LDOL_BASE + 0x15)
#define WSA884X_PON_LDOL_SPARE_TUNE_4 (WSA884X_ANA_PON_LDOL_BASE + 0x16)
#define WSA884X_DIG_CTRL0_BASE (WSA884X_BASE + 0x0400)
#define WSA884X_DIG_CTRL0_PAGE (WSA884X_DIG_CTRL0_BASE + 0x00)
#define WSA884X_CHIP_ID0 (WSA884X_DIG_CTRL0_BASE + 0x01)
#define WSA884X_CHIP_ID1 (WSA884X_DIG_CTRL0_BASE + 0x02)
#define WSA884X_CHIP_ID2 (WSA884X_DIG_CTRL0_BASE + 0x03)
#define WSA884X_CHIP_ID3 (WSA884X_DIG_CTRL0_BASE + 0x04)
#define WSA884X_BUS_ID (WSA884X_DIG_CTRL0_BASE + 0x05)
#define WSA884X_CDC_RST_CTL (WSA884X_DIG_CTRL0_BASE + 0x10)
#define WSA884X_SWR_RESET_EN (WSA884X_DIG_CTRL0_BASE + 0x14)
#define WSA884X_TOP_CLK_CFG (WSA884X_DIG_CTRL0_BASE + 0x18)
#define WSA884X_SWR_CLK_RATE (WSA884X_DIG_CTRL0_BASE + 0x19)
#define WSA884X_CDC_PATH_MODE (WSA884X_DIG_CTRL0_BASE + 0x1a)
#define WSA884X_CDC_PATH_MODE_RXD_MODE_MASK 0x02
#define WSA884X_CDC_PATH_MODE_RXD_MODE_SHIFT 0
#define WSA884X_CDC_PATH_MODE_TXD_MODE_MASK 0x01
#define WSA884X_CDC_PATH_MODE_TXD_MODE_SHIFT 0
#define WSA884X_CDC_CLK_CTL (WSA884X_DIG_CTRL0_BASE + 0x1c)
#define WSA884X_PA_FSM_EN (WSA884X_DIG_CTRL0_BASE + 0x30)
#define WSA884X_PA_FSM_EN_GLOBAL_PA_EN_MASK 0x01
#define WSA884X_PA_FSM_EN_GLOBAL_PA_EN_SHIFT 0
#define WSA884X_PA_FSM_CTL0 (WSA884X_DIG_CTRL0_BASE + 0x31)
#define WSA884X_PA_FSM_CTL1 (WSA884X_DIG_CTRL0_BASE + 0x32)
#define WSA884X_PA_FSM_CTL1_NOISE_GATE_BLOCK_MASK 0x38
#define WSA884X_PA_FSM_TIMER0 (WSA884X_DIG_CTRL0_BASE + 0x33)
#define WSA884X_PA_FSM_TIMER1 (WSA884X_DIG_CTRL0_BASE + 0x34)
#define WSA884X_PA_FSM_STA0 (WSA884X_DIG_CTRL0_BASE + 0x35)
#define WSA884X_PA_FSM_STA1 (WSA884X_DIG_CTRL0_BASE + 0x36)
#define WSA884X_PA_FSM_ERR_CTL (WSA884X_DIG_CTRL0_BASE + 0x37)
#define WSA884X_PA_FSM_ERR_COND0 (WSA884X_DIG_CTRL0_BASE + 0x38)
#define WSA884X_PA_FSM_ERR_COND1 (WSA884X_DIG_CTRL0_BASE + 0x39)
#define WSA884X_PA_FSM_MSK0 (WSA884X_DIG_CTRL0_BASE + 0x3a)
#define WSA884X_PA_FSM_MSK1 (WSA884X_DIG_CTRL0_BASE + 0x3b)
#define WSA884X_PA_FSM_BYP_CTL (WSA884X_DIG_CTRL0_BASE + 0x3c)
#define WSA884X_PA_FSM_BYP0 (WSA884X_DIG_CTRL0_BASE + 0x3d)
#define WSA884X_PA_FSM_BYP1 (WSA884X_DIG_CTRL0_BASE + 0x3e)
#define WSA884X_TADC_VALUE_CTL (WSA884X_DIG_CTRL0_BASE + 0x50)
#define WSA884X_TEMP_DETECT_CTL (WSA884X_DIG_CTRL0_BASE + 0x51)
#define WSA884X_TEMP_DIN_MSB (WSA884X_DIG_CTRL0_BASE + 0x52)
#define WSA884X_TEMP_DIN_LSB (WSA884X_DIG_CTRL0_BASE + 0x53)
#define WSA884X_TEMP_DOUT_MSB (WSA884X_DIG_CTRL0_BASE + 0x54)
#define WSA884X_TEMP_DOUT_LSB (WSA884X_DIG_CTRL0_BASE + 0x55)
#define WSA884X_TEMP_CONFIG0 (WSA884X_DIG_CTRL0_BASE + 0x56)
#define WSA884X_TEMP_CONFIG1 (WSA884X_DIG_CTRL0_BASE + 0x57)
#define WSA884X_VBAT_THRM_FLT_CTL (WSA884X_DIG_CTRL0_BASE + 0x58)
#define WSA884X_VBAT_THRM_FLT_CTL_THRM_COEF_SEL_MASK 0xe0
#define WSA884X_VBAT_THRM_FLT_CTL_THRM_COEF_SEL_SHIFT 5
#define WSA884X_VBAT_THRM_FLT_CTL_THRM_FLT_EN_SHIFT 4
#define WSA884X_VBAT_THRM_FLT_CTL_VBAT_COEF_SEL_MASK 0x0e
#define WSA884X_VBAT_THRM_FLT_CTL_VBAT_COEF_SEL_SHIFT 1
#define WSA884X_VBAT_THRM_FLT_CTL_VBAT_FLT_EN_SHIFT 0
#define WSA884X_VBAT_CAL_CTL (WSA884X_DIG_CTRL0_BASE + 0x59)
#define WSA884X_VBAT_CAL_CTL_RESERVE_MASK 0x0e
#define WSA884X_VBAT_CAL_CTL_VBAT_CAL_EN_MASK 0x01
#define WSA884X_VBAT_DIN_MSB (WSA884X_DIG_CTRL0_BASE + 0x5a)
#define WSA884X_VBAT_DIN_LSB (WSA884X_DIG_CTRL0_BASE + 0x5b)
#define WSA884X_VBAT_DOUT_MSB (WSA884X_DIG_CTRL0_BASE + 0x5c)
#define WSA884X_VBAT_DOUT_LSB (WSA884X_DIG_CTRL0_BASE + 0x5d)
#define WSA884X_VBAT_CAL_MSB (WSA884X_DIG_CTRL0_BASE + 0x5e)
#define WSA884X_VBAT_CAL_LSB (WSA884X_DIG_CTRL0_BASE + 0x5f)
#define WSA884X_UVLO_DEGLITCH_CTL (WSA884X_DIG_CTRL0_BASE + 0x60)
#define WSA884X_BOP_DEGLITCH_CTL (WSA884X_DIG_CTRL0_BASE + 0x61)
#define WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_SETTING_MASK 0x1e
#define WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_SETTING_SHIFT 1
#define WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_EN_MASK 0x1
#define WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_EN_SHIFT 0
#define WSA884X_VBAT_ZONE_DETC_CTL (WSA884X_DIG_CTRL0_BASE + 0x64)
#define WSA884X_CPS_CTL (WSA884X_DIG_CTRL0_BASE + 0x68)
#define WSA884X_CDC_RX_CTL (WSA884X_DIG_CTRL0_BASE + 0x70)
#define WSA884X_CDC_SPK_DSM_A1_0 (WSA884X_DIG_CTRL0_BASE + 0x71)
#define WSA884X_CDC_SPK_DSM_A1_1 (WSA884X_DIG_CTRL0_BASE + 0x72)
#define WSA884X_CDC_SPK_DSM_A2_0 (WSA884X_DIG_CTRL0_BASE + 0x73)
#define WSA884X_CDC_SPK_DSM_A2_1 (WSA884X_DIG_CTRL0_BASE + 0x74)
#define WSA884X_CDC_SPK_DSM_A3_0 (WSA884X_DIG_CTRL0_BASE + 0x75)
#define WSA884X_CDC_SPK_DSM_A3_1 (WSA884X_DIG_CTRL0_BASE + 0x76)
#define WSA884X_CDC_SPK_DSM_A4_0 (WSA884X_DIG_CTRL0_BASE + 0x77)
#define WSA884X_CDC_SPK_DSM_A4_1 (WSA884X_DIG_CTRL0_BASE + 0x78)
#define WSA884X_CDC_SPK_DSM_A5_0 (WSA884X_DIG_CTRL0_BASE + 0x79)
#define WSA884X_CDC_SPK_DSM_A5_1 (WSA884X_DIG_CTRL0_BASE + 0x7a)
#define WSA884X_CDC_SPK_DSM_A6_0 (WSA884X_DIG_CTRL0_BASE + 0x7b)
#define WSA884X_CDC_SPK_DSM_A7_0 (WSA884X_DIG_CTRL0_BASE + 0x7c)
#define WSA884X_CDC_SPK_DSM_C_0 (WSA884X_DIG_CTRL0_BASE + 0x7d)
#define WSA884X_CDC_SPK_DSM_C_0_COEF_C3_MASK 0xf0
#define WSA884X_CDC_SPK_DSM_C_0_COEF_C3_SHIFT 4
#define WSA884X_CDC_SPK_DSM_C_0_COEF_C2_MASK 0x0f
#define WSA884X_CDC_SPK_DSM_C_0_COEF_C2_SHIFT 0
#define WSA884X_CDC_SPK_DSM_C_1 (WSA884X_DIG_CTRL0_BASE + 0x7e)
#define WSA884X_CDC_SPK_DSM_C_2 (WSA884X_DIG_CTRL0_BASE + 0x7f)
#define WSA884X_CDC_SPK_DSM_C_2_COEF_C7_MASK 0xf0
#define WSA884X_CDC_SPK_DSM_C_2_COEF_C7_SHIFT 4
#define WSA884X_CDC_SPK_DSM_C_2_COEF_C6_MASK 0x0f
#define WSA884X_CDC_SPK_DSM_C_2_COEF_C6_SHIFT 0
#define WSA884X_CDC_SPK_DSM_C_3 (WSA884X_DIG_CTRL0_BASE + 0x80)
#define WSA884X_CDC_SPK_DSM_C_3_COEF_C7_MASK 0x3f
#define WSA884X_CDC_SPK_DSM_C_3_COEF_C7_SHIFT 0
#define WSA884X_CDC_SPK_DSM_R1 (WSA884X_DIG_CTRL0_BASE + 0x81)
#define WSA884X_CDC_SPK_DSM_R2 (WSA884X_DIG_CTRL0_BASE + 0x82)
#define WSA884X_CDC_SPK_DSM_R3 (WSA884X_DIG_CTRL0_BASE + 0x83)
#define WSA884X_CDC_SPK_DSM_R4 (WSA884X_DIG_CTRL0_BASE + 0x84)
#define WSA884X_CDC_SPK_DSM_R5 (WSA884X_DIG_CTRL0_BASE + 0x85)
#define WSA884X_CDC_SPK_DSM_R6 (WSA884X_DIG_CTRL0_BASE + 0x86)
#define WSA884X_CDC_SPK_DSM_R7 (WSA884X_DIG_CTRL0_BASE + 0x87)
#define WSA884X_CDC_SPK_GAIN_PDM_0 (WSA884X_DIG_CTRL0_BASE + 0x88)
#define WSA884X_CDC_SPK_GAIN_PDM_1 (WSA884X_DIG_CTRL0_BASE + 0x89)
#define WSA884X_CDC_SPK_GAIN_PDM_2 (WSA884X_DIG_CTRL0_BASE + 0x8a)
#define WSA884X_PDM_WD_CTL (WSA884X_DIG_CTRL0_BASE + 0x8b)
#define WSA884X_PDM_WD_CTL_HOLD_OFF_MASK 0x04
#define WSA884X_PDM_WD_CTL_HOLD_OFF_SHIFT 2
#define WSA884X_PDM_WD_CTL_TIME_OUT_SEL_MASK 0x02
#define WSA884X_PDM_WD_CTL_TIME_OUT_SEL_SHIFT 1
#define WSA884X_PDM_WD_CTL_PDM_WD_EN_MASK 0x01
#define WSA884X_PDM_WD_CTL_PDM_WD_EN_SHIFT 0
#define WSA884X_DEM_BYPASS_DATA0 (WSA884X_DIG_CTRL0_BASE + 0x90)
#define WSA884X_DEM_BYPASS_DATA1 (WSA884X_DIG_CTRL0_BASE + 0x91)
#define WSA884X_DEM_BYPASS_DATA2 (WSA884X_DIG_CTRL0_BASE + 0x92)
#define WSA884X_DEM_BYPASS_DATA3 (WSA884X_DIG_CTRL0_BASE + 0x93)
#define WSA884X_DRE_CTL_0 (WSA884X_DIG_CTRL0_BASE + 0xb0)
#define WSA884X_DRE_CTL_0_PROG_DELAY_MASK 0xf0
#define WSA884X_DRE_CTL_0_PROG_DELAY_SHIFT 4
#define WSA884X_DRE_CTL_0_OFFSET_MASK 0x07
#define WSA884X_DRE_CTL_0_OFFSET_SHIFT 0
#define WSA884X_DRE_CTL_1 (WSA884X_DIG_CTRL0_BASE + 0xb1)
#define WSA884X_DRE_CTL_1_CSR_GAIN_MASK 0x3e
#define WSA884X_DRE_CTL_1_CSR_GAIN_SHIFT 1
#define WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK 0x01
#define WSA884X_DRE_CTL_1_CSR_GAIN_EN_SHIFT 0
#define WSA884X_DRE_IDLE_DET_CTL (WSA884X_DIG_CTRL0_BASE + 0xb2)
#define WSA884X_GAIN_RAMPING_CTL (WSA884X_DIG_CTRL0_BASE + 0xb8)
#define WSA884X_GAIN_RAMPING_MIN (WSA884X_DIG_CTRL0_BASE + 0xb9)
#define WSA884X_GAIN_RAMPING_MIN_MIN_GAIN_MASK 0x1f
#define WSA884X_GAIN_RAMPING_MIN_MIN_GAIN_SHIFT 0
#define WSA884X_TAGC_CTL (WSA884X_DIG_CTRL0_BASE + 0xc0)
#define WSA884X_TAGC_TIME (WSA884X_DIG_CTRL0_BASE + 0xc1)
#define WSA884X_TAGC_FORCE_VAL (WSA884X_DIG_CTRL0_BASE + 0xc2)
#define WSA884X_VAGC_CTL (WSA884X_DIG_CTRL0_BASE + 0xc8)
#define WSA884X_VAGC_TIME (WSA884X_DIG_CTRL0_BASE + 0xc9)
#define WSA884X_VAGC_ATTN_LVL_1 (WSA884X_DIG_CTRL0_BASE + 0xca)
#define WSA884X_VAGC_ATTN_LVL_2 (WSA884X_DIG_CTRL0_BASE + 0xcb)
#define WSA884X_VAGC_ATTN_LVL_3 (WSA884X_DIG_CTRL0_BASE + 0xcc)
#define WSA884X_CLSH_CTL_0 (WSA884X_DIG_CTRL0_BASE + 0xd0)
#define WSA884X_CLSH_CTL_0_CSR_GAIN_EN_SHIFT 7
#define WSA884X_CLSH_CTL_0_DLY_CODE_MASK 0x70
#define WSA884X_CLSH_CTL_0_DLY_CODE_SHIFT 4
#define WSA884X_CLSH_CTL_0_DLY_RST_SHIFT 3
#define WSA884X_CLSH_CTL_0_DLY_EN_SHIFT 2
#define WSA884X_CLSH_CTL_0_INPUT_EN_SHIFT 1
#define WSA884X_CLSH_CTL_0_CLSH_EN_SHIFT 0
#define WSA884X_CLSH_CTL_1 (WSA884X_DIG_CTRL0_BASE + 0xd1)
#define WSA884X_CLSH_V_HD_PA (WSA884X_DIG_CTRL0_BASE + 0xd2)
#define WSA884X_CLSH_V_PA_MIN (WSA884X_DIG_CTRL0_BASE + 0xd3)
#define WSA884X_CLSH_OVRD_VAL (WSA884X_DIG_CTRL0_BASE + 0xd4)
#define WSA884X_CLSH_HARD_MAX (WSA884X_DIG_CTRL0_BASE + 0xd5)
#define WSA884X_CLSH_SOFT_MAX (WSA884X_DIG_CTRL0_BASE + 0xd6)
#define WSA884X_CLSH_SIG_DP (WSA884X_DIG_CTRL0_BASE + 0xd7)
#define WSA884X_PBR_DELAY_CTL (WSA884X_DIG_CTRL0_BASE + 0xd8)
#define WSA884X_CLSH_SRL_MAX_PBR (WSA884X_DIG_CTRL0_BASE + 0xe0)
#define WSA884X_PBR_MAX_VOLTAGE 20
#define WSA884X_PBR_MAX_CODE 255
#define WSA884X_VTH_TO_REG(vth) \
((vth) != 0 ? (((vth) - 150) * WSA884X_PBR_MAX_CODE / (WSA884X_PBR_MAX_VOLTAGE * 100) + 1) : 0)
#define WSA884X_CLSH_VTH1 (WSA884X_DIG_CTRL0_BASE + 0xe1)
#define WSA884X_CLSH_VTH2 (WSA884X_DIG_CTRL0_BASE + 0xe2)
#define WSA884X_CLSH_VTH3 (WSA884X_DIG_CTRL0_BASE + 0xe3)
#define WSA884X_CLSH_VTH4 (WSA884X_DIG_CTRL0_BASE + 0xe4)
#define WSA884X_CLSH_VTH5 (WSA884X_DIG_CTRL0_BASE + 0xe5)
#define WSA884X_CLSH_VTH6 (WSA884X_DIG_CTRL0_BASE + 0xe6)
#define WSA884X_CLSH_VTH7 (WSA884X_DIG_CTRL0_BASE + 0xe7)
#define WSA884X_CLSH_VTH8 (WSA884X_DIG_CTRL0_BASE + 0xe8)
#define WSA884X_CLSH_VTH9 (WSA884X_DIG_CTRL0_BASE + 0xe9)
#define WSA884X_CLSH_VTH10 (WSA884X_DIG_CTRL0_BASE + 0xea)
#define WSA884X_CLSH_VTH11 (WSA884X_DIG_CTRL0_BASE + 0xeb)
#define WSA884X_CLSH_VTH12 (WSA884X_DIG_CTRL0_BASE + 0xec)
#define WSA884X_CLSH_VTH13 (WSA884X_DIG_CTRL0_BASE + 0xed)
#define WSA884X_CLSH_VTH14 (WSA884X_DIG_CTRL0_BASE + 0xee)
#define WSA884X_CLSH_VTH15 (WSA884X_DIG_CTRL0_BASE + 0xef)
#define WSA884X_DIG_CTRL1_BASE (WSA884X_BASE + 0x0500)
#define WSA884X_DIG_CTRL1_PAGE (WSA884X_DIG_CTRL1_BASE + 0x00)
#define WSA884X_VPHX_SYS_EN_STATUS (WSA884X_DIG_CTRL1_BASE + 0x01)
#define WSA884X_ANA_WO_CTL_0 (WSA884X_DIG_CTRL1_BASE + 0x04)
#define WSA884X_ANA_WO_CTL_0_MODE_SHIFT 0
#define WSA884X_ANA_WO_CTL_0_VPHX_SYS_EN_MASK 0xc0
#define WSA884X_ANA_WO_CTL_0_PA_AUX_DISABLE 0x0
#define WSA884X_ANA_WO_CTL_0_PA_AUX_18_DB 0xa
#define WSA884X_ANA_WO_CTL_0_PA_AUX_0_DB 0x7
#define WSA884X_ANA_WO_CTL_0_PA_AUX_GAIN_MASK 0x3c
#define WSA884X_ANA_WO_CTL_0_PA_MIN_GAIN_BYP_MASK 0x02
#define WSA884X_ANA_WO_CTL_0_DAC_CM_CLAMP_EN_MODE_SPEAKER 0x1
#define WSA884X_ANA_WO_CTL_0_DAC_CM_CLAMP_EN_MASK 0x01
#define WSA884X_ANA_WO_CTL_1 (WSA884X_DIG_CTRL1_BASE + 0x05)
#define WSA884X_PIN_CTL (WSA884X_DIG_CTRL1_BASE + 0x10)
#define WSA884X_PIN_CTL_OE (WSA884X_DIG_CTRL1_BASE + 0x11)
#define WSA884X_PIN_WDATA_IOPAD (WSA884X_DIG_CTRL1_BASE + 0x12)
#define WSA884X_PIN_STATUS (WSA884X_DIG_CTRL1_BASE + 0x13)
#define WSA884X_I2C_SLAVE_CTL (WSA884X_DIG_CTRL1_BASE + 0x14)
#define WSA884X_SPMI_PAD_CTL0 (WSA884X_DIG_CTRL1_BASE + 0x15)
#define WSA884X_SPMI_PAD_CTL1 (WSA884X_DIG_CTRL1_BASE + 0x16)
#define WSA884X_SPMI_PAD_CTL2 (WSA884X_DIG_CTRL1_BASE + 0x17)
#define WSA884X_MEM_CTL (WSA884X_DIG_CTRL1_BASE + 0x18)
#define WSA884X_SWR_HM_TEST0 (WSA884X_DIG_CTRL1_BASE + 0x19)
#define WSA884X_SWR_HM_TEST1 (WSA884X_DIG_CTRL1_BASE + 0x1a)
#define WSA884X_OTP_CTRL0 (WSA884X_DIG_CTRL1_BASE + 0x30)
#define WSA884X_OTP_CTRL1 (WSA884X_DIG_CTRL1_BASE + 0x31)
#define WSA884X_OTP_CTRL2 (WSA884X_DIG_CTRL1_BASE + 0x32)
#define WSA884X_OTP_STAT (WSA884X_DIG_CTRL1_BASE + 0x33)
#define WSA884X_OTP_PRG_TCSP0 (WSA884X_DIG_CTRL1_BASE + 0x34)
#define WSA884X_OTP_PRG_TCSP1 (WSA884X_DIG_CTRL1_BASE + 0x35)
#define WSA884X_OTP_PRG_TPPS (WSA884X_DIG_CTRL1_BASE + 0x36)
#define WSA884X_OTP_PRG_TVPS (WSA884X_DIG_CTRL1_BASE + 0x37)
#define WSA884X_OTP_PRG_TVPH (WSA884X_DIG_CTRL1_BASE + 0x38)
#define WSA884X_OTP_PRG_TPPR0 (WSA884X_DIG_CTRL1_BASE + 0x39)
#define WSA884X_OTP_PRG_TPPR1 (WSA884X_DIG_CTRL1_BASE + 0x3a)
#define WSA884X_OTP_PRG_TPPH (WSA884X_DIG_CTRL1_BASE + 0x3b)
#define WSA884X_OTP_PRG_END (WSA884X_DIG_CTRL1_BASE + 0x3c)
#define WSA884X_WAVG_PLAY (WSA884X_DIG_CTRL1_BASE + 0x40)
#define WSA884X_WAVG_CTL (WSA884X_DIG_CTRL1_BASE + 0x41)
#define WSA884X_WAVG_LRA_PER_0 (WSA884X_DIG_CTRL1_BASE + 0x43)
#define WSA884X_WAVG_LRA_PER_1 (WSA884X_DIG_CTRL1_BASE + 0x44)
#define WSA884X_WAVG_DELTA_THETA_0 (WSA884X_DIG_CTRL1_BASE + 0x45)
#define WSA884X_WAVG_DELTA_THETA_1 (WSA884X_DIG_CTRL1_BASE + 0x46)
#define WSA884X_WAVG_DIRECT_AMP_0 (WSA884X_DIG_CTRL1_BASE + 0x47)
#define WSA884X_WAVG_DIRECT_AMP_1 (WSA884X_DIG_CTRL1_BASE + 0x48)
#define WSA884X_WAVG_PTRN_AMP0_0 (WSA884X_DIG_CTRL1_BASE + 0x49)
#define WSA884X_WAVG_PTRN_AMP0_1 (WSA884X_DIG_CTRL1_BASE + 0x4a)
#define WSA884X_WAVG_PTRN_AMP1_0 (WSA884X_DIG_CTRL1_BASE + 0x4b)
#define WSA884X_WAVG_PTRN_AMP1_1 (WSA884X_DIG_CTRL1_BASE + 0x4c)
#define WSA884X_WAVG_PTRN_AMP2_0 (WSA884X_DIG_CTRL1_BASE + 0x4d)
#define WSA884X_WAVG_PTRN_AMP2_1 (WSA884X_DIG_CTRL1_BASE + 0x4e)
#define WSA884X_WAVG_PTRN_AMP3_0 (WSA884X_DIG_CTRL1_BASE + 0x4f)
#define WSA884X_WAVG_PTRN_AMP3_1 (WSA884X_DIG_CTRL1_BASE + 0x50)
#define WSA884X_WAVG_PTRN_AMP4_0 (WSA884X_DIG_CTRL1_BASE + 0x51)
#define WSA884X_WAVG_PTRN_AMP4_1 (WSA884X_DIG_CTRL1_BASE + 0x52)
#define WSA884X_WAVG_PTRN_AMP5_0 (WSA884X_DIG_CTRL1_BASE + 0x53)
#define WSA884X_WAVG_PTRN_AMP5_1 (WSA884X_DIG_CTRL1_BASE + 0x54)
#define WSA884X_WAVG_PTRN_AMP6_0 (WSA884X_DIG_CTRL1_BASE + 0x55)
#define WSA884X_WAVG_PTRN_AMP6_1 (WSA884X_DIG_CTRL1_BASE + 0x56)
#define WSA884X_WAVG_PTRN_AMP7_0 (WSA884X_DIG_CTRL1_BASE + 0x57)
#define WSA884X_WAVG_PTRN_AMP7_1 (WSA884X_DIG_CTRL1_BASE + 0x58)
#define WSA884X_WAVG_PER_0_1 (WSA884X_DIG_CTRL1_BASE + 0x59)
#define WSA884X_WAVG_PER_2_3 (WSA884X_DIG_CTRL1_BASE + 0x5a)
#define WSA884X_WAVG_PER_4_5 (WSA884X_DIG_CTRL1_BASE + 0x5b)
#define WSA884X_WAVG_PER_6_7 (WSA884X_DIG_CTRL1_BASE + 0x5c)
#define WSA884X_WAVG_STA (WSA884X_DIG_CTRL1_BASE + 0x5d)
#define WSA884X_INTR_MODE (WSA884X_DIG_CTRL1_BASE + 0x80)
#define WSA884X_INTR_MASK0 (WSA884X_DIG_CTRL1_BASE + 0x81)
#define WSA884X_INTR_MASK1 (WSA884X_DIG_CTRL1_BASE + 0x82)
#define WSA884X_INTR_STATUS0 (WSA884X_DIG_CTRL1_BASE + 0x83)
#define WSA884X_INTR_STATUS1 (WSA884X_DIG_CTRL1_BASE + 0x84)
#define WSA884X_INTR_CLEAR0 (WSA884X_DIG_CTRL1_BASE + 0x85)
#define WSA884X_INTR_CLEAR1 (WSA884X_DIG_CTRL1_BASE + 0x86)
#define WSA884X_INTR_LEVEL0 (WSA884X_DIG_CTRL1_BASE + 0x87)
#define WSA884X_INTR_LEVEL1 (WSA884X_DIG_CTRL1_BASE + 0x88)
#define WSA884X_INTR_SET0 (WSA884X_DIG_CTRL1_BASE + 0x89)
#define WSA884X_INTR_SET1 (WSA884X_DIG_CTRL1_BASE + 0x8a)
#define WSA884X_INTR_TEST0 (WSA884X_DIG_CTRL1_BASE + 0x8b)
#define WSA884X_INTR_TEST1 (WSA884X_DIG_CTRL1_BASE + 0x8c)
#define WSA884X_PDM_TEST_MODE (WSA884X_DIG_CTRL1_BASE + 0xc0)
#define WSA884X_ATE_TEST_MODE (WSA884X_DIG_CTRL1_BASE + 0xc1)
#define WSA884X_PA_FSM_DBG (WSA884X_DIG_CTRL1_BASE + 0xc2)
#define WSA884X_DIG_DEBUG_MODE (WSA884X_DIG_CTRL1_BASE + 0xc3)
#define WSA884X_DIG_DEBUG_SEL (WSA884X_DIG_CTRL1_BASE + 0xc4)
#define WSA884X_DIG_DEBUG_EN (WSA884X_DIG_CTRL1_BASE + 0xc5)
#define WSA884X_TADC_DETECT_DBG_CTL (WSA884X_DIG_CTRL1_BASE + 0xc9)
#define WSA884X_TADC_DEBUG_MSB (WSA884X_DIG_CTRL1_BASE + 0xca)
#define WSA884X_TADC_DEBUG_LSB (WSA884X_DIG_CTRL1_BASE + 0xcb)
#define WSA884X_SAMPLE_EDGE_SEL (WSA884X_DIG_CTRL1_BASE + 0xcc)
#define WSA884X_SWR_EDGE_SEL (WSA884X_DIG_CTRL1_BASE + 0xcd)
#define WSA884X_TEST_MODE_CTL (WSA884X_DIG_CTRL1_BASE + 0xce)
#define WSA884X_IOPAD_CTL (WSA884X_DIG_CTRL1_BASE + 0xcf)
#define WSA884X_ANA_CSR_DBG_ADD (WSA884X_DIG_CTRL1_BASE + 0xd0)
#define WSA884X_ANA_CSR_DBG_CTL (WSA884X_DIG_CTRL1_BASE + 0xd1)
#define WSA884X_CLK_DBG_CTL (WSA884X_DIG_CTRL1_BASE + 0xd2)
#define WSA884X_SPARE_R (WSA884X_DIG_CTRL1_BASE + 0xf0)
#define WSA884X_SPARE_0 (WSA884X_DIG_CTRL1_BASE + 0xf1)
#define WSA884X_SPARE_1 (WSA884X_DIG_CTRL1_BASE + 0xf2)
#define WSA884X_SPARE_2 (WSA884X_DIG_CTRL1_BASE + 0xf3)
#define WSA884X_SCODE (WSA884X_DIG_CTRL1_BASE + 0xff)
#define WSA884X_DIG_TRIM_BASE (WSA884X_BASE + 0x0800)
#define WSA884X_DIG_TRIM_PAGE (WSA884X_DIG_TRIM_BASE + 0x00)
#define WSA884X_OTP_REG_0 (WSA884X_DIG_TRIM_BASE + 0x80)
#define WSA884X_OTP_ID_WSA8840 0x0
#define WSA884X_OTP_ID_WSA8845 0x5
#define WSA884X_OTP_ID_WSA8845H 0xc
#define WSA884X_OTP_REG_0_ID_MASK 0x0f
#define WSA884X_OTP_REG_1 (WSA884X_DIG_TRIM_BASE + 0x81)
#define WSA884X_OTP_REG_2 (WSA884X_DIG_TRIM_BASE + 0x82)
#define WSA884X_OTP_REG_3 (WSA884X_DIG_TRIM_BASE + 0x83)
#define WSA884X_OTP_REG_4 (WSA884X_DIG_TRIM_BASE + 0x84)
#define WSA884X_OTP_REG_5 (WSA884X_DIG_TRIM_BASE + 0x85)
#define WSA884X_OTP_REG_6 (WSA884X_DIG_TRIM_BASE + 0x86)
#define WSA884X_OTP_REG_7 (WSA884X_DIG_TRIM_BASE + 0x87)
#define WSA884X_OTP_REG_8 (WSA884X_DIG_TRIM_BASE + 0x88)
#define WSA884X_OTP_REG_9 (WSA884X_DIG_TRIM_BASE + 0x89)
#define WSA884X_OTP_REG_10 (WSA884X_DIG_TRIM_BASE + 0x8a)
#define WSA884X_OTP_REG_11 (WSA884X_DIG_TRIM_BASE + 0x8b)
#define WSA884X_OTP_REG_12 (WSA884X_DIG_TRIM_BASE + 0x8c)
#define WSA884X_OTP_REG_13 (WSA884X_DIG_TRIM_BASE + 0x8d)
#define WSA884X_OTP_REG_14 (WSA884X_DIG_TRIM_BASE + 0x8e)
#define WSA884X_OTP_REG_15 (WSA884X_DIG_TRIM_BASE + 0x8f)
#define WSA884X_OTP_REG_16 (WSA884X_DIG_TRIM_BASE + 0x90)
#define WSA884X_OTP_REG_17 (WSA884X_DIG_TRIM_BASE + 0x91)
#define WSA884X_OTP_REG_18 (WSA884X_DIG_TRIM_BASE + 0x92)
#define WSA884X_OTP_REG_19 (WSA884X_DIG_TRIM_BASE + 0x93)
#define WSA884X_OTP_REG_20 (WSA884X_DIG_TRIM_BASE + 0x94)
#define WSA884X_OTP_REG_21 (WSA884X_DIG_TRIM_BASE + 0x95)
#define WSA884X_OTP_REG_22 (WSA884X_DIG_TRIM_BASE + 0x96)
#define WSA884X_OTP_REG_23 (WSA884X_DIG_TRIM_BASE + 0x97)
#define WSA884X_OTP_REG_24 (WSA884X_DIG_TRIM_BASE + 0x98)
#define WSA884X_OTP_REG_25 (WSA884X_DIG_TRIM_BASE + 0x99)
#define WSA884X_OTP_REG_26 (WSA884X_DIG_TRIM_BASE + 0x9a)
#define WSA884X_OTP_REG_27 (WSA884X_DIG_TRIM_BASE + 0x9b)
#define WSA884X_OTP_REG_28 (WSA884X_DIG_TRIM_BASE + 0x9c)
#define WSA884X_OTP_REG_29 (WSA884X_DIG_TRIM_BASE + 0x9d)
#define WSA884X_OTP_REG_30 (WSA884X_DIG_TRIM_BASE + 0x9e)
#define WSA884X_OTP_REG_31 (WSA884X_DIG_TRIM_BASE + 0x9f)
#define WSA884X_OTP_REG_32 (WSA884X_DIG_TRIM_BASE + 0xa0)
#define WSA884X_OTP_REG_33 (WSA884X_DIG_TRIM_BASE + 0xa1)
#define WSA884X_OTP_REG_34 (WSA884X_DIG_TRIM_BASE + 0xa2)
#define WSA884X_OTP_REG_35 (WSA884X_DIG_TRIM_BASE + 0xa3)
#define WSA884X_OTP_REG_36 (WSA884X_DIG_TRIM_BASE + 0xa4)
#define WSA884X_OTP_REG_37 (WSA884X_DIG_TRIM_BASE + 0xa5)
#define WSA884X_OTP_REG_38 (WSA884X_DIG_TRIM_BASE + 0xa6)
#define WSA884X_OTP_REG_38_RESERVER_MASK 0xf0
#define WSA884X_OTP_REG_38_RESERVER_SHIFT 4
#define WSA884X_OTP_REG_38_BST_CFG_SEL_MASK 0x08
#define WSA884X_OTP_REG_38_BST_CFG_SEL_SHIFT 3
#define WSA884X_OTP_REG_38_BOOST_ILIM_TUNE_MASK 0x07
#define WSA884X_OTP_REG_38_BOOST_ILIM_TUNE_SHIFT 0
#define WSA884X_OTP_REG_39 (WSA884X_DIG_TRIM_BASE + 0xa7)
#define WSA884X_OTP_REG_40 (WSA884X_DIG_TRIM_BASE + 0xa8)
#define WSA884X_OTP_REG_40_SPARE_TYPE2_MASK 0xc0
#define WSA884X_OTP_REG_40_SPARE_TYPE2_SHIFT 6
#define WSA884X_OTP_REG_40_ISENSE_RESCAL_MASK 0x3c
#define WSA884X_OTP_REG_40_ISENSE_RESCAL_SHIFT 2
#define WSA884X_OTP_REG_40_ATE_BOOST_RDSON_TEST_MASK 0x2
#define WSA884X_OTP_REG_40_ATE_BOOST_RDSON_TEST_SHIFT 1
#define WSA884X_OTP_REG_40_ATE_CLASSD_RDSON_TEST_MASK 0x1
#define WSA884X_OTP_REG_40_ATE_CLASSD_RDSON_TEST_SHIFT 0
#define WSA884X_OTP_REG_41 (WSA884X_DIG_TRIM_BASE + 0xa9)
#define WSA884X_OTP_REG_63 (WSA884X_DIG_TRIM_BASE + 0xbf)
#define WSA884X_DIG_EMEM_BASE (WSA884X_BASE + 0x08C0)
#define WSA884X_EMEM_0 (WSA884X_DIG_EMEM_BASE + 0x00)
#define WSA884X_EMEM_1 (WSA884X_DIG_EMEM_BASE + 0x01)
#define WSA884X_EMEM_2 (WSA884X_DIG_EMEM_BASE + 0x02)
#define WSA884X_EMEM_3 (WSA884X_DIG_EMEM_BASE + 0x03)
#define WSA884X_EMEM_4 (WSA884X_DIG_EMEM_BASE + 0x04)
#define WSA884X_EMEM_5 (WSA884X_DIG_EMEM_BASE + 0x05)
#define WSA884X_EMEM_6 (WSA884X_DIG_EMEM_BASE + 0x06)
#define WSA884X_EMEM_7 (WSA884X_DIG_EMEM_BASE + 0x07)
#define WSA884X_EMEM_8 (WSA884X_DIG_EMEM_BASE + 0x08)
#define WSA884X_EMEM_9 (WSA884X_DIG_EMEM_BASE + 0x09)
#define WSA884X_EMEM_10 (WSA884X_DIG_EMEM_BASE + 0x0a)
#define WSA884X_EMEM_11 (WSA884X_DIG_EMEM_BASE + 0x0b)
#define WSA884X_EMEM_12 (WSA884X_DIG_EMEM_BASE + 0x0c)
#define WSA884X_EMEM_13 (WSA884X_DIG_EMEM_BASE + 0x0d)
#define WSA884X_EMEM_14 (WSA884X_DIG_EMEM_BASE + 0x0e)
#define WSA884X_EMEM_15 (WSA884X_DIG_EMEM_BASE + 0x0f)
#define WSA884X_EMEM_16 (WSA884X_DIG_EMEM_BASE + 0x10)
#define WSA884X_EMEM_17 (WSA884X_DIG_EMEM_BASE + 0x11)
#define WSA884X_EMEM_18 (WSA884X_DIG_EMEM_BASE + 0x12)
#define WSA884X_EMEM_19 (WSA884X_DIG_EMEM_BASE + 0x13)
#define WSA884X_EMEM_20 (WSA884X_DIG_EMEM_BASE + 0x14)
#define WSA884X_EMEM_21 (WSA884X_DIG_EMEM_BASE + 0x15)
#define WSA884X_EMEM_22 (WSA884X_DIG_EMEM_BASE + 0x16)
#define WSA884X_EMEM_23 (WSA884X_DIG_EMEM_BASE + 0x17)
#define WSA884X_EMEM_24 (WSA884X_DIG_EMEM_BASE + 0x18)
#define WSA884X_EMEM_25 (WSA884X_DIG_EMEM_BASE + 0x19)
#define WSA884X_EMEM_26 (WSA884X_DIG_EMEM_BASE + 0x1a)
#define WSA884X_EMEM_27 (WSA884X_DIG_EMEM_BASE + 0x1b)
#define WSA884X_EMEM_28 (WSA884X_DIG_EMEM_BASE + 0x1c)
#define WSA884X_EMEM_29 (WSA884X_DIG_EMEM_BASE + 0x1d)
#define WSA884X_EMEM_30 (WSA884X_DIG_EMEM_BASE + 0x1e)
#define WSA884X_EMEM_31 (WSA884X_DIG_EMEM_BASE + 0x1f)
#define WSA884X_EMEM_32 (WSA884X_DIG_EMEM_BASE + 0x20)
#define WSA884X_EMEM_33 (WSA884X_DIG_EMEM_BASE + 0x21)
#define WSA884X_EMEM_34 (WSA884X_DIG_EMEM_BASE + 0x22)
#define WSA884X_EMEM_35 (WSA884X_DIG_EMEM_BASE + 0x23)
#define WSA884X_EMEM_36 (WSA884X_DIG_EMEM_BASE + 0x24)
#define WSA884X_EMEM_37 (WSA884X_DIG_EMEM_BASE + 0x25)
#define WSA884X_EMEM_38 (WSA884X_DIG_EMEM_BASE + 0x26)
#define WSA884X_EMEM_39 (WSA884X_DIG_EMEM_BASE + 0x27)
#define WSA884X_EMEM_40 (WSA884X_DIG_EMEM_BASE + 0x28)
#define WSA884X_EMEM_41 (WSA884X_DIG_EMEM_BASE + 0x29)
#define WSA884X_EMEM_42 (WSA884X_DIG_EMEM_BASE + 0x2a)
#define WSA884X_EMEM_43 (WSA884X_DIG_EMEM_BASE + 0x2b)
#define WSA884X_EMEM_44 (WSA884X_DIG_EMEM_BASE + 0x2c)
#define WSA884X_EMEM_45 (WSA884X_DIG_EMEM_BASE + 0x2d)
#define WSA884X_EMEM_46 (WSA884X_DIG_EMEM_BASE + 0x2e)
#define WSA884X_EMEM_47 (WSA884X_DIG_EMEM_BASE + 0x2f)
#define WSA884X_EMEM_48 (WSA884X_DIG_EMEM_BASE + 0x30)
#define WSA884X_EMEM_49 (WSA884X_DIG_EMEM_BASE + 0x31)
#define WSA884X_EMEM_50 (WSA884X_DIG_EMEM_BASE + 0x32)
#define WSA884X_EMEM_51 (WSA884X_DIG_EMEM_BASE + 0x33)
#define WSA884X_EMEM_52 (WSA884X_DIG_EMEM_BASE + 0x34)
#define WSA884X_EMEM_53 (WSA884X_DIG_EMEM_BASE + 0x35)
#define WSA884X_EMEM_54 (WSA884X_DIG_EMEM_BASE + 0x36)
#define WSA884X_EMEM_55 (WSA884X_DIG_EMEM_BASE + 0x37)
#define WSA884X_EMEM_56 (WSA884X_DIG_EMEM_BASE + 0x38)
#define WSA884X_EMEM_57 (WSA884X_DIG_EMEM_BASE + 0x39)
#define WSA884X_EMEM_58 (WSA884X_DIG_EMEM_BASE + 0x3a)
#define WSA884X_EMEM_59 (WSA884X_DIG_EMEM_BASE + 0x3b)
#define WSA884X_EMEM_60 (WSA884X_DIG_EMEM_BASE + 0x3c)
#define WSA884X_EMEM_61 (WSA884X_DIG_EMEM_BASE + 0x3d)
#define WSA884X_EMEM_62 (WSA884X_DIG_EMEM_BASE + 0x3e)
#define WSA884X_EMEM_63 (WSA884X_DIG_EMEM_BASE + 0x3f)
#define WSA884X_NUM_REGISTERS (WSA884X_EMEM_63 + 1)
#define WSA884X_MAX_REGISTER (WSA884X_NUM_REGISTERS - 1)
#define WSA884X_SUPPLIES_NUM 2
#define WSA884X_MAX_SWR_PORTS 6
#define WSA884X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
SNDRV_PCM_RATE_384000)
/* Fractional Rates */
#define WSA884X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
#define WSA884X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
struct wsa884x_priv {
struct regmap *regmap;
struct device *dev;
struct regulator_bulk_data supplies[WSA884X_SUPPLIES_NUM];
struct sdw_slave *slave;
struct sdw_stream_config sconfig;
struct sdw_stream_runtime *sruntime;
struct sdw_port_config port_config[WSA884X_MAX_SWR_PORTS];
struct gpio_desc *sd_n;
bool port_prepared[WSA884X_MAX_SWR_PORTS];
bool port_enable[WSA884X_MAX_SWR_PORTS];
unsigned int variant;
int active_ports;
int dev_mode;
bool hw_init;
};
enum {
COMP_OFFSET0,
COMP_OFFSET1,
COMP_OFFSET2,
COMP_OFFSET3,
COMP_OFFSET4,
};
enum wsa884x_gain {
G_21_DB = 0,
G_19P5_DB,
G_18_DB,
G_16P5_DB,
G_15_DB,
G_13P5_DB,
G_12_DB,
G_10P5_DB,
G_9_DB,
G_7P5_DB,
G_6_DB,
G_4P5_DB,
G_3_DB,
G_1P5_DB,
G_0_DB,
G_M1P5_DB,
G_M3_DB,
G_M4P5_DB,
G_M6_DB,
G_MAX_DB,
};
enum wsa884x_isense {
ISENSE_6_DB = 0,
ISENSE_12_DB,
ISENSE_15_DB,
ISENSE_18_DB,
};
enum wsa884x_vsense {
VSENSE_M12_DB = 0,
VSENSE_M15_DB,
VSENSE_M18_DB,
VSENSE_M21_DB,
VSENSE_M24_DB,
};
enum wsa884x_port_ids {
WSA884X_PORT_DAC,
WSA884X_PORT_COMP,
WSA884X_PORT_BOOST,
WSA884X_PORT_PBR,
WSA884X_PORT_VISENSE,
WSA884X_PORT_CPS,
};
static const char * const wsa884x_supply_name[] = {
"vdd-io",
"vdd-1p8",
};
static const char * const wsa884x_dev_mode_text[] = {
"Speaker", "Receiver"
};
enum wsa884x_mode {
WSA884X_SPEAKER,
WSA884X_RECEIVER,
};
static const struct soc_enum wsa884x_dev_mode_enum =
SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(wsa884x_dev_mode_text), wsa884x_dev_mode_text);
static struct sdw_dpn_prop wsa884x_sink_dpn_prop[WSA884X_MAX_SWR_PORTS] = {
{
.num = WSA884X_PORT_DAC + 1,
.type = SDW_DPN_SIMPLE,
.min_ch = 1,
.max_ch = 1,
.simple_ch_prep_sm = true,
.read_only_wordlength = true,
}, {
.num = WSA884X_PORT_COMP + 1,
.type = SDW_DPN_SIMPLE,
.min_ch = 1,
.max_ch = 1,
.simple_ch_prep_sm = true,
.read_only_wordlength = true,
}, {
.num = WSA884X_PORT_BOOST + 1,
.type = SDW_DPN_SIMPLE,
.min_ch = 1,
.max_ch = 1,
.simple_ch_prep_sm = true,
.read_only_wordlength = true,
}, {
.num = WSA884X_PORT_PBR + 1,
.type = SDW_DPN_SIMPLE,
.min_ch = 1,
.max_ch = 1,
.simple_ch_prep_sm = true,
.read_only_wordlength = true,
}, {
.num = WSA884X_PORT_VISENSE + 1,
.type = SDW_DPN_SIMPLE,
.min_ch = 1,
.max_ch = 1,
.simple_ch_prep_sm = true,
.read_only_wordlength = true,
}, {
.num = WSA884X_PORT_CPS + 1,
.type = SDW_DPN_SIMPLE,
.min_ch = 1,
.max_ch = 1,
.simple_ch_prep_sm = true,
.read_only_wordlength = true,
}
};
static const struct sdw_port_config wsa884x_pconfig[WSA884X_MAX_SWR_PORTS] = {
{
.num = WSA884X_PORT_DAC + 1,
.ch_mask = 0x1,
}, {
.num = WSA884X_PORT_COMP + 1,
.ch_mask = 0xf,
}, {
.num = WSA884X_PORT_BOOST + 1,
.ch_mask = 0x3,
}, {
.num = WSA884X_PORT_PBR + 1,
.ch_mask = 0x1,
}, {
.num = WSA884X_PORT_VISENSE + 1,
.ch_mask = 0x3,
}, {
.num = WSA884X_PORT_CPS + 1,
.ch_mask = 0x3,
},
};
static struct reg_default wsa884x_defaults[] = {
{ WSA884X_BG_CTRL, 0xa5 },
{ WSA884X_ADC_CTRL, 0x00 },
{ WSA884X_BOP1_PROG, 0x22 },
{ WSA884X_BOP2_PROG, 0x44 },
{ WSA884X_UVLO_PROG, 0x99 },
{ WSA884X_UVLO_PROG1, 0x70 },
{ WSA884X_SPARE_CTRL_0, 0x00 },
{ WSA884X_SPARE_CTRL_1, 0x00 },
{ WSA884X_SPARE_CTRL_2, 0x00 },
{ WSA884X_SPARE_CTRL_3, 0x00 },
{ WSA884X_REF_CTRL, 0xd2 },
{ WSA884X_BG_TEST_CTL, 0x06 },
{ WSA884X_BG_BIAS, 0xd7 },
{ WSA884X_ADC_PROG, 0x08 },
{ WSA884X_ADC_IREF_CTL, 0x57 },
{ WSA884X_ADC_ISENS_CTL, 0x47 },
{ WSA884X_ADC_CLK_CTL, 0x87 },
{ WSA884X_ADC_TEST_CTL, 0x00 },
{ WSA884X_ADC_BIAS, 0x51 },
{ WSA884X_VBAT_SNS, 0xa0 },
{ WSA884X_BOP_ATEST_SEL, 0x00 },
{ WSA884X_MISC0, 0x04 },
{ WSA884X_MISC1, 0x75 },
{ WSA884X_MISC2, 0x00 },
{ WSA884X_MISC3, 0x10 },
{ WSA884X_SPARE_TSBG_0, 0x00 },
{ WSA884X_SPARE_TUNE_0, 0x00 },
{ WSA884X_SPARE_TUNE_1, 0x00 },
{ WSA884X_VSENSE1, 0xe7 },
{ WSA884X_ISENSE2, 0x27 },
{ WSA884X_SPARE_CTL_1, 0x00 },
{ WSA884X_SPARE_CTL_2, 0x00 },
{ WSA884X_SPARE_CTL_3, 0x00 },
{ WSA884X_SPARE_CTL_4, 0x00 },
{ WSA884X_EN, 0x10 },
{ WSA884X_OVERRIDE1, 0x00 },
{ WSA884X_OVERRIDE2, 0x08 },
{ WSA884X_ISENSE1, 0xd4 },
{ WSA884X_ISENSE_CAL, 0x00 },
{ WSA884X_MISC, 0x00 },
{ WSA884X_ADC_0, 0x00 },
{ WSA884X_ADC_1, 0x00 },
{ WSA884X_ADC_2, 0x40 },
{ WSA884X_ADC_3, 0x80 },
{ WSA884X_ADC_4, 0x25 },
{ WSA884X_ADC_5, 0x24 },
{ WSA884X_ADC_6, 0x0a },
{ WSA884X_ADC_7, 0x81 },
{ WSA884X_IVSENSE_SPARE_TUNE_1, 0x00 },
{ WSA884X_SPARE_TUNE_2, 0x00 },
{ WSA884X_SPARE_TUNE_3, 0x00 },
{ WSA884X_SPARE_TUNE_4, 0x00 },
{ WSA884X_TOP_CTRL1, 0xd3 },
{ WSA884X_CLIP_DET_CTRL1, 0x7e },
{ WSA884X_CLIP_DET_CTRL2, 0x4c },
{ WSA884X_DAC_CTRL1, 0xa4 },
{ WSA884X_DAC_VCM_CTRL_REG1, 0x02 },
{ WSA884X_DAC_VCM_CTRL_REG2, 0x00 },
{ WSA884X_DAC_VCM_CTRL_REG3, 0x00 },
{ WSA884X_DAC_VCM_CTRL_REG4, 0x00 },
{ WSA884X_DAC_VCM_CTRL_REG5, 0x00 },
{ WSA884X_DAC_VCM_CTRL_REG6, 0x00 },
{ WSA884X_PWM_CLK_CTL, 0x20 },
{ WSA884X_DRV_LF_LDO_SEL, 0xaa },
{ WSA884X_OCP_CTL, 0xc6 },
{ WSA884X_PDRV_HS_CTL, 0x52 },
{ WSA884X_PDRV_LS_CTL, 0x4a },
{ WSA884X_SPK_TOP_SPARE_CTL_1, 0x00 },
{ WSA884X_SPK_TOP_SPARE_CTL_2, 0x00 },
{ WSA884X_SPK_TOP_SPARE_CTL_3, 0x00 },
{ WSA884X_SPK_TOP_SPARE_CTL_4, 0x00 },
{ WSA884X_SPARE_CTL_5, 0x00 },
{ WSA884X_DAC_EN_DEBUG_REG, 0x00 },
{ WSA884X_DAC_OPAMP_BIAS1_REG, 0x48 },
{ WSA884X_DAC_OPAMP_BIAS2_REG, 0x48 },
{ WSA884X_DAC_TUNE1, 0x02 },
{ WSA884X_DAC_VOLTAGE_CTRL_REG, 0x05 },
{ WSA884X_ATEST1_REG, 0x00 },
{ WSA884X_ATEST2_REG, 0x00 },
{ WSA884X_TOP_BIAS_REG1, 0x6a },
{ WSA884X_TOP_BIAS_REG2, 0x65 },
{ WSA884X_TOP_BIAS_REG3, 0x55 },
{ WSA884X_TOP_BIAS_REG4, 0xa9 },
{ WSA884X_PWRSTG_DBG2, 0x21 },
{ WSA884X_DRV_LF_BLK_EN, 0x0f },
{ WSA884X_DRV_LF_EN, 0x0a },
{ WSA884X_DRV_LF_MASK_DCC_CTL, 0x08 },
{ WSA884X_DRV_LF_MISC_CTL1, 0x30 },
{ WSA884X_DRV_LF_REG_GAIN, 0x00 },
{ WSA884X_DRV_OS_CAL_CTL, 0x00 },
{ WSA884X_DRV_OS_CAL_CTL1, 0x90 },
{ WSA884X_PWRSTG_DBG, 0x08 },
{ WSA884X_BBM_CTL, 0x92 },
{ WSA884X_TOP_MISC1, 0x00 },
{ WSA884X_DAC_VCM_CTRL_REG7, 0x00 },
{ WSA884X_TOP_BIAS_REG5, 0x15 },
{ WSA884X_DRV_LF_MISC_CTL2, 0x00 },
{ WSA884X_STB_CTRL1, 0x42 },
{ WSA884X_CURRENT_LIMIT, 0x54 },
{ WSA884X_BYP_CTRL1, 0x01 },
{ WSA884X_SPARE_CTL_0, 0x00 },
{ WSA884X_BOOST_SPARE_CTL_1, 0x00 },
{ WSA884X_IBIAS1, 0x00 },
{ WSA884X_IBIAS2, 0x00 },
{ WSA884X_IBIAS3, 0x00 },
{ WSA884X_EN_CTRL, 0x42 },
{ WSA884X_STB_CTRL2, 0x03 },
{ WSA884X_STB_CTRL3, 0x3c },
{ WSA884X_STB_CTRL4, 0x30 },
{ WSA884X_BYP_CTRL2, 0x97 },
{ WSA884X_BYP_CTRL3, 0x11 },
{ WSA884X_ZX_CTRL1, 0xf0 },
{ WSA884X_ZX_CTRL2, 0x04 },
{ WSA884X_BLEEDER_CTRL, 0x04 },
{ WSA884X_BOOST_MISC, 0x62 },
{ WSA884X_PWRSTAGE_CTRL1, 0x00 },
{ WSA884X_PWRSTAGE_CTRL2, 0x31 },
{ WSA884X_PWRSTAGE_CTRL3, 0x81 },
{ WSA884X_PWRSTAGE_CTRL4, 0x5f },
{ WSA884X_MAXD_REG1, 0x00 },
{ WSA884X_MAXD_REG2, 0x5b },
{ WSA884X_ILIM_CTRL1, 0xe2 },
{ WSA884X_ILIM_CTRL2, 0x90 },
{ WSA884X_TEST_CTRL1, 0x00 },
{ WSA884X_TEST_CTRL2, 0x00 },
{ WSA884X_SPARE1, 0x00 },
{ WSA884X_BOOT_CAP_CHECK, 0x01 },
{ WSA884X_PON_CTL_0, 0x12 },
{ WSA884X_PWRSAV_CTL, 0xaa },
{ WSA884X_PON_LDOL_SPARE_CTL_0, 0x00 },
{ WSA884X_PON_LDOL_SPARE_CTL_1, 0x00 },
{ WSA884X_PON_LDOL_SPARE_CTL_2, 0x00 },
{ WSA884X_PON_LDOL_SPARE_CTL_3, 0x00 },
{ WSA884X_PON_CLT_1, 0xe1 },
{ WSA884X_PON_CTL_2, 0x00 },
{ WSA884X_PON_CTL_3, 0x70 },
{ WSA884X_CKWD_CTL_0, 0x14 },
{ WSA884X_CKWD_CTL_1, 0x3b },
{ WSA884X_CKWD_CTL_2, 0x00 },
{ WSA884X_CKSK_CTL_0, 0x00 },
{ WSA884X_PADSW_CTL_0, 0x00 },
{ WSA884X_TEST_0, 0x00 },
{ WSA884X_TEST_1, 0x00 },
{ WSA884X_PON_LDOL_SPARE_TUNE_0, 0x00 },
{ WSA884X_PON_LDOL_SPARE_TUNE_1, 0x00 },
{ WSA884X_PON_LDOL_SPARE_TUNE_2, 0x00 },
{ WSA884X_PON_LDOL_SPARE_TUNE_3, 0x00 },
{ WSA884X_PON_LDOL_SPARE_TUNE_4, 0x00 },
{ WSA884X_DIG_CTRL0_PAGE, 0x00 },
{ WSA884X_CDC_RST_CTL, 0x01 },
{ WSA884X_SWR_RESET_EN, 0x00 },
{ WSA884X_TOP_CLK_CFG, 0x00 },
{ WSA884X_SWR_CLK_RATE, 0x00 },
{ WSA884X_CDC_PATH_MODE, 0x00 },
{ WSA884X_CDC_CLK_CTL, 0x1f },
{ WSA884X_PA_FSM_EN, 0x00 },
{ WSA884X_PA_FSM_CTL0, 0x00 },
{ WSA884X_PA_FSM_CTL1, 0xfe },
{ WSA884X_PA_FSM_TIMER0, 0x80 },
{ WSA884X_PA_FSM_TIMER1, 0x80 },
{ WSA884X_PA_FSM_ERR_CTL, 0x00 },
{ WSA884X_PA_FSM_MSK0, 0x00 },
{ WSA884X_PA_FSM_MSK1, 0x00 },
{ WSA884X_PA_FSM_BYP_CTL, 0x00 },
{ WSA884X_PA_FSM_BYP0, 0x00 },
{ WSA884X_PA_FSM_BYP1, 0x00 },
{ WSA884X_TADC_VALUE_CTL, 0x03 },
{ WSA884X_TEMP_DETECT_CTL, 0x01 },
{ WSA884X_TEMP_CONFIG0, 0x00 },
{ WSA884X_TEMP_CONFIG1, 0x00 },
{ WSA884X_VBAT_THRM_FLT_CTL, 0x7f },
{ WSA884X_VBAT_CAL_CTL, 0x01 },
{ WSA884X_UVLO_DEGLITCH_CTL, 0x05 },
{ WSA884X_BOP_DEGLITCH_CTL, 0x05 },
{ WSA884X_VBAT_ZONE_DETC_CTL, 0x31 },
{ WSA884X_CPS_CTL, 0x00 },
{ WSA884X_CDC_RX_CTL, 0xfe },
{ WSA884X_CDC_SPK_DSM_A1_0, 0x00 },
{ WSA884X_CDC_SPK_DSM_A1_1, 0x01 },
{ WSA884X_CDC_SPK_DSM_A2_0, 0x96 },
{ WSA884X_CDC_SPK_DSM_A2_1, 0x09 },
{ WSA884X_CDC_SPK_DSM_A3_0, 0xab },
{ WSA884X_CDC_SPK_DSM_A3_1, 0x05 },
{ WSA884X_CDC_SPK_DSM_A4_0, 0x1c },
{ WSA884X_CDC_SPK_DSM_A4_1, 0x02 },
{ WSA884X_CDC_SPK_DSM_A5_0, 0x17 },
{ WSA884X_CDC_SPK_DSM_A5_1, 0x02 },
{ WSA884X_CDC_SPK_DSM_A6_0, 0xaa },
{ WSA884X_CDC_SPK_DSM_A7_0, 0xe3 },
{ WSA884X_CDC_SPK_DSM_C_0, 0x69 },
{ WSA884X_CDC_SPK_DSM_C_1, 0x54 },
{ WSA884X_CDC_SPK_DSM_C_2, 0x02 },
{ WSA884X_CDC_SPK_DSM_C_3, 0x15 },
{ WSA884X_CDC_SPK_DSM_R1, 0xa4 },
{ WSA884X_CDC_SPK_DSM_R2, 0xb5 },
{ WSA884X_CDC_SPK_DSM_R3, 0x86 },
{ WSA884X_CDC_SPK_DSM_R4, 0x85 },
{ WSA884X_CDC_SPK_DSM_R5, 0xaa },
{ WSA884X_CDC_SPK_DSM_R6, 0xe2 },
{ WSA884X_CDC_SPK_DSM_R7, 0x62 },
{ WSA884X_CDC_SPK_GAIN_PDM_0, 0x00 },
{ WSA884X_CDC_SPK_GAIN_PDM_1, 0xfc },
{ WSA884X_CDC_SPK_GAIN_PDM_2, 0x05 },
{ WSA884X_PDM_WD_CTL, 0x00 },
{ WSA884X_DEM_BYPASS_DATA0, 0x00 },
{ WSA884X_DEM_BYPASS_DATA1, 0x00 },
{ WSA884X_DEM_BYPASS_DATA2, 0x00 },
{ WSA884X_DEM_BYPASS_DATA3, 0x00 },
{ WSA884X_DRE_CTL_0, 0x70 },
{ WSA884X_DRE_CTL_1, 0x04 },
{ WSA884X_DRE_IDLE_DET_CTL, 0x2f },
{ WSA884X_GAIN_RAMPING_CTL, 0x50 },
{ WSA884X_GAIN_RAMPING_MIN, 0x12 },
{ WSA884X_TAGC_CTL, 0x15 },
{ WSA884X_TAGC_TIME, 0xbc },
{ WSA884X_TAGC_FORCE_VAL, 0x00 },
{ WSA884X_VAGC_CTL, 0x01 },
{ WSA884X_VAGC_TIME, 0x0f },
{ WSA884X_VAGC_ATTN_LVL_1, 0x03 },
{ WSA884X_VAGC_ATTN_LVL_2, 0x06 },
{ WSA884X_VAGC_ATTN_LVL_3, 0x09 },
{ WSA884X_CLSH_CTL_0, 0x37 },
{ WSA884X_CLSH_CTL_1, 0x81 },
{ WSA884X_CLSH_V_HD_PA, 0x0c },
{ WSA884X_CLSH_V_PA_MIN, 0x00 },
{ WSA884X_CLSH_OVRD_VAL, 0x00 },
{ WSA884X_CLSH_HARD_MAX, 0xff },
{ WSA884X_CLSH_SOFT_MAX, 0xf5 },
{ WSA884X_CLSH_SIG_DP, 0x00 },
{ WSA884X_PBR_DELAY_CTL, 0x07 },
{ WSA884X_CLSH_SRL_MAX_PBR, 0x02 },
{ WSA884X_CLSH_VTH1, 0x00 },
{ WSA884X_CLSH_VTH2, 0x00 },
{ WSA884X_CLSH_VTH3, 0x00 },
{ WSA884X_CLSH_VTH4, 0x00 },
{ WSA884X_CLSH_VTH5, 0x00 },
{ WSA884X_CLSH_VTH6, 0x00 },
{ WSA884X_CLSH_VTH7, 0x00 },
{ WSA884X_CLSH_VTH8, 0x00 },
{ WSA884X_CLSH_VTH9, 0x00 },
{ WSA884X_CLSH_VTH10, 0x00 },
{ WSA884X_CLSH_VTH11, 0x00 },
{ WSA884X_CLSH_VTH12, 0x00 },
{ WSA884X_CLSH_VTH13, 0x00 },
{ WSA884X_CLSH_VTH14, 0x00 },
{ WSA884X_CLSH_VTH15, 0x00 },
{ WSA884X_DIG_CTRL1_PAGE, 0x00 },
{ WSA884X_PIN_CTL, 0x04 },
{ WSA884X_PIN_CTL_OE, 0x00 },
{ WSA884X_PIN_WDATA_IOPAD, 0x00 },
{ WSA884X_I2C_SLAVE_CTL, 0x00 },
{ WSA884X_SPMI_PAD_CTL0, 0x2f },
{ WSA884X_SPMI_PAD_CTL1, 0x2f },
{ WSA884X_SPMI_PAD_CTL2, 0x2f },
{ WSA884X_MEM_CTL, 0x00 },
{ WSA884X_SWR_HM_TEST0, 0x08 },
{ WSA884X_OTP_CTRL0, 0x00 },
{ WSA884X_OTP_CTRL2, 0x00 },
{ WSA884X_OTP_PRG_TCSP0, 0x77 },
{ WSA884X_OTP_PRG_TCSP1, 0x00 },
{ WSA884X_OTP_PRG_TPPS, 0x47 },
{ WSA884X_OTP_PRG_TVPS, 0x3b },
{ WSA884X_OTP_PRG_TVPH, 0x47 },
{ WSA884X_OTP_PRG_TPPR0, 0x47 },
{ WSA884X_OTP_PRG_TPPR1, 0x00 },
{ WSA884X_OTP_PRG_TPPH, 0x47 },
{ WSA884X_OTP_PRG_END, 0x47 },
{ WSA884X_WAVG_PLAY, 0x00 },
{ WSA884X_WAVG_CTL, 0x06 },
{ WSA884X_WAVG_LRA_PER_0, 0xd1 },
{ WSA884X_WAVG_LRA_PER_1, 0x00 },
{ WSA884X_WAVG_DELTA_THETA_0, 0xe6 },
{ WSA884X_WAVG_DELTA_THETA_1, 0x04 },
{ WSA884X_WAVG_DIRECT_AMP_0, 0x50 },
{ WSA884X_WAVG_DIRECT_AMP_1, 0x00 },
{ WSA884X_WAVG_PTRN_AMP0_0, 0x50 },
{ WSA884X_WAVG_PTRN_AMP0_1, 0x00 },
{ WSA884X_WAVG_PTRN_AMP1_0, 0x50 },
{ WSA884X_WAVG_PTRN_AMP1_1, 0x00 },
{ WSA884X_WAVG_PTRN_AMP2_0, 0x50 },
{ WSA884X_WAVG_PTRN_AMP2_1, 0x00 },
{ WSA884X_WAVG_PTRN_AMP3_0, 0x50 },
{ WSA884X_WAVG_PTRN_AMP3_1, 0x00 },
{ WSA884X_WAVG_PTRN_AMP4_0, 0x50 },
{ WSA884X_WAVG_PTRN_AMP4_1, 0x00 },
{ WSA884X_WAVG_PTRN_AMP5_0, 0x50 },
{ WSA884X_WAVG_PTRN_AMP5_1, 0x00 },
{ WSA884X_WAVG_PTRN_AMP6_0, 0x50 },
{ WSA884X_WAVG_PTRN_AMP6_1, 0x00 },
{ WSA884X_WAVG_PTRN_AMP7_0, 0x50 },
{ WSA884X_WAVG_PTRN_AMP7_1, 0x00 },
{ WSA884X_WAVG_PER_0_1, 0x88 },
{ WSA884X_WAVG_PER_2_3, 0x88 },
{ WSA884X_WAVG_PER_4_5, 0x88 },
{ WSA884X_WAVG_PER_6_7, 0x88 },
{ WSA884X_INTR_MODE, 0x00 },
{ WSA884X_INTR_MASK0, 0x90 },
{ WSA884X_INTR_MASK1, 0x00 },
{ WSA884X_INTR_CLEAR0, 0x00 },
{ WSA884X_INTR_CLEAR1, 0x00 },
{ WSA884X_INTR_LEVEL0, 0x04 },
{ WSA884X_INTR_LEVEL1, 0x00 },
{ WSA884X_INTR_SET0, 0x00 },
{ WSA884X_INTR_SET1, 0x00 },
{ WSA884X_INTR_TEST0, 0x00 },
{ WSA884X_INTR_TEST1, 0x00 },
{ WSA884X_PDM_TEST_MODE, 0x00 },
{ WSA884X_PA_FSM_DBG, 0x00 },
{ WSA884X_DIG_DEBUG_MODE, 0x00 },
{ WSA884X_DIG_DEBUG_SEL, 0x00 },
{ WSA884X_DIG_DEBUG_EN, 0x00 },
{ WSA884X_TADC_DETECT_DBG_CTL, 0x00 },
{ WSA884X_TADC_DEBUG_MSB, 0x00 },
{ WSA884X_TADC_DEBUG_LSB, 0x00 },
{ WSA884X_SAMPLE_EDGE_SEL, 0x7f },
{ WSA884X_SWR_EDGE_SEL, 0x00 },
{ WSA884X_TEST_MODE_CTL, 0x05 },
{ WSA884X_IOPAD_CTL, 0x00 },
{ WSA884X_ANA_CSR_DBG_ADD, 0x00 },
{ WSA884X_ANA_CSR_DBG_CTL, 0x12 },
{ WSA884X_CLK_DBG_CTL, 0x00 },
{ WSA884X_SPARE_0, 0x00 },
{ WSA884X_SPARE_1, 0x00 },
{ WSA884X_SPARE_2, 0x00 },
{ WSA884X_SCODE, 0x00 },
{ WSA884X_DIG_TRIM_PAGE, 0x00 },
{ WSA884X_EMEM_0, 0x00 },
{ WSA884X_EMEM_1, 0x00 },
{ WSA884X_EMEM_2, 0x00 },
{ WSA884X_EMEM_3, 0x00 },
{ WSA884X_EMEM_4, 0x00 },
{ WSA884X_EMEM_5, 0x00 },
{ WSA884X_EMEM_6, 0x00 },
{ WSA884X_EMEM_7, 0x00 },
{ WSA884X_EMEM_8, 0x00 },
{ WSA884X_EMEM_9, 0x00 },
{ WSA884X_EMEM_10, 0x00 },
{ WSA884X_EMEM_11, 0x00 },
{ WSA884X_EMEM_12, 0x00 },
{ WSA884X_EMEM_13, 0x00 },
{ WSA884X_EMEM_14, 0x00 },
{ WSA884X_EMEM_15, 0x00 },
{ WSA884X_EMEM_16, 0x00 },
{ WSA884X_EMEM_17, 0x00 },
{ WSA884X_EMEM_18, 0x00 },
{ WSA884X_EMEM_19, 0x00 },
{ WSA884X_EMEM_20, 0x00 },
{ WSA884X_EMEM_21, 0x00 },
{ WSA884X_EMEM_22, 0x00 },
{ WSA884X_EMEM_23, 0x00 },
{ WSA884X_EMEM_24, 0x00 },
{ WSA884X_EMEM_25, 0x00 },
{ WSA884X_EMEM_26, 0x00 },
{ WSA884X_EMEM_27, 0x00 },
{ WSA884X_EMEM_28, 0x00 },
{ WSA884X_EMEM_29, 0x00 },
{ WSA884X_EMEM_30, 0x00 },
{ WSA884X_EMEM_31, 0x00 },
{ WSA884X_EMEM_32, 0x00 },
{ WSA884X_EMEM_33, 0x00 },
{ WSA884X_EMEM_34, 0x00 },
{ WSA884X_EMEM_35, 0x00 },
{ WSA884X_EMEM_36, 0x00 },
{ WSA884X_EMEM_37, 0x00 },
{ WSA884X_EMEM_38, 0x00 },
{ WSA884X_EMEM_39, 0x00 },
{ WSA884X_EMEM_40, 0x00 },
{ WSA884X_EMEM_41, 0x00 },
{ WSA884X_EMEM_42, 0x00 },
{ WSA884X_EMEM_43, 0x00 },
{ WSA884X_EMEM_44, 0x00 },
{ WSA884X_EMEM_45, 0x00 },
{ WSA884X_EMEM_46, 0x00 },
{ WSA884X_EMEM_47, 0x00 },
{ WSA884X_EMEM_48, 0x00 },
{ WSA884X_EMEM_49, 0x00 },
{ WSA884X_EMEM_50, 0x00 },
{ WSA884X_EMEM_51, 0x00 },
{ WSA884X_EMEM_52, 0x00 },
{ WSA884X_EMEM_53, 0x00 },
{ WSA884X_EMEM_54, 0x00 },
{ WSA884X_EMEM_55, 0x00 },
{ WSA884X_EMEM_56, 0x00 },
{ WSA884X_EMEM_57, 0x00 },
{ WSA884X_EMEM_58, 0x00 },
{ WSA884X_EMEM_59, 0x00 },
{ WSA884X_EMEM_60, 0x00 },
{ WSA884X_EMEM_61, 0x00 },
{ WSA884X_EMEM_62, 0x00 },
{ WSA884X_EMEM_63, 0x00 },
};
static bool wsa884x_readonly_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case WSA884X_DOUT_MSB:
case WSA884X_DOUT_LSB:
case WSA884X_STATUS:
case WSA884X_SPK_TOP_SPARE_TUNE_2:
case WSA884X_SPK_TOP_SPARE_TUNE_3:
case WSA884X_SPK_TOP_SPARE_TUNE_4:
case WSA884X_SPARE_TUNE_5:
case WSA884X_SPARE_TUNE_6:
case WSA884X_SPARE_TUNE_7:
case WSA884X_SPARE_TUNE_8:
case WSA884X_SPARE_TUNE_9:
case WSA884X_SPARE_TUNE_10:
case WSA884X_PA_STATUS0:
case WSA884X_PA_STATUS1:
case WSA884X_PA_STATUS2:
case WSA884X_PA_STATUS3:
case WSA884X_PA_STATUS4:
case WSA884X_PA_STATUS5:
case WSA884X_SPARE_RO_1:
case WSA884X_SPARE_RO_2:
case WSA884X_SPARE_RO_3:
case WSA884X_SPARE_RO_0:
case WSA884X_BOOST_SPARE_RO_1:
case WSA884X_STATUS_0:
case WSA884X_STATUS_1:
case WSA884X_CHIP_ID0:
case WSA884X_CHIP_ID1:
case WSA884X_CHIP_ID2:
case WSA884X_CHIP_ID3:
case WSA884X_BUS_ID:
case WSA884X_PA_FSM_STA0:
case WSA884X_PA_FSM_STA1:
case WSA884X_PA_FSM_ERR_COND0:
case WSA884X_PA_FSM_ERR_COND1:
case WSA884X_TEMP_DIN_MSB:
case WSA884X_TEMP_DIN_LSB:
case WSA884X_TEMP_DOUT_MSB:
case WSA884X_TEMP_DOUT_LSB:
case WSA884X_VBAT_DIN_MSB:
case WSA884X_VBAT_DIN_LSB:
case WSA884X_VBAT_DOUT_MSB:
case WSA884X_VBAT_DOUT_LSB:
case WSA884X_VBAT_CAL_MSB:
case WSA884X_VBAT_CAL_LSB:
case WSA884X_VPHX_SYS_EN_STATUS:
case WSA884X_PIN_STATUS:
case WSA884X_SWR_HM_TEST1:
case WSA884X_OTP_CTRL1:
case WSA884X_OTP_STAT:
case WSA884X_WAVG_STA:
case WSA884X_INTR_STATUS0:
case WSA884X_INTR_STATUS1:
case WSA884X_ATE_TEST_MODE:
case WSA884X_SPARE_R:
return true;
}
return false;
}
static bool wsa884x_writeable_register(struct device *dev, unsigned int reg)
{
return !wsa884x_readonly_register(dev, reg);
}
static bool wsa884x_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case WSA884X_ANA_WO_CTL_0:
case WSA884X_ANA_WO_CTL_1:
return true;
}
return wsa884x_readonly_register(dev, reg);
}
static struct regmap_config wsa884x_regmap_config = {
.reg_bits = 32,
.val_bits = 8,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = wsa884x_defaults,
.max_register = WSA884X_MAX_REGISTER,
.num_reg_defaults = ARRAY_SIZE(wsa884x_defaults),
.volatile_reg = wsa884x_volatile_register,
.writeable_reg = wsa884x_writeable_register,
.reg_format_endian = REGMAP_ENDIAN_NATIVE,
.val_format_endian = REGMAP_ENDIAN_NATIVE,
.use_single_read = true,
};
static const struct reg_sequence wsa884x_reg_init[] = {
{ WSA884X_BOP2_PROG, FIELD_PREP_CONST(WSA884X_BOP2_PROG_BOP2_VTH_MASK, 0x6) |
FIELD_PREP_CONST(WSA884X_BOP2_PROG_BOP2_HYST_MASK, 0x6) },
{ WSA884X_REF_CTRL, (0xd2 & ~WSA884X_REF_CTRL_BG_RDY_SEL_MASK) |
FIELD_PREP_CONST(WSA884X_REF_CTRL_BG_RDY_SEL_MASK, 0x1) },
/*
* Downstream suggests for batteries different than 1-Stacked (1S):
* { WSA884X_TOP_CTRL1, 0xd3 & ~WSA884X_TOP_CTRL1_OCP_LOWVBAT_ITH_EN_MASK },
*/
{ WSA884X_STB_CTRL1, (0x42 & ~WSA884X_STB_CTRL1_SLOPE_COMP_CURRENT_MASK) |
FIELD_PREP_CONST(WSA884X_STB_CTRL1_SLOPE_COMP_CURRENT_MASK, 0xd) },
{ WSA884X_CURRENT_LIMIT, (0x54 & ~WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_MASK) |
FIELD_PREP_CONST(WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_MASK, 0x9) },
{ WSA884X_ZX_CTRL1, (0xf0 & ~WSA884X_ZX_CTRL1_ZX_DET_SW_SEL_MASK) |
FIELD_PREP_CONST(WSA884X_ZX_CTRL1_ZX_DET_SW_SEL_MASK, 0x3) },
{ WSA884X_ILIM_CTRL1, (0xe2 & ~WSA884X_ILIM_CTRL1_ILIM_OFFSET_PB_MASK) |
FIELD_PREP_CONST(WSA884X_ILIM_CTRL1_ILIM_OFFSET_PB_MASK, 0x3) },
{ WSA884X_CKWD_CTL_1, FIELD_PREP_CONST(WSA884X_CKWD_CTL_1_VPP_SW_CTL_MASK, 0x0) |
FIELD_PREP_CONST(WSA884X_CKWD_CTL_1_CKWD_VCOMP_VREF_SEL_MASK, 0x13) },
{ WSA884X_PA_FSM_CTL1, (0xfe & ~WSA884X_PA_FSM_CTL1_NOISE_GATE_BLOCK_MASK) |
FIELD_PREP_CONST(WSA884X_PA_FSM_CTL1_NOISE_GATE_BLOCK_MASK, 0x4) }, /* == 0xfe */
{ WSA884X_VBAT_THRM_FLT_CTL, (0x7f & ~WSA884X_VBAT_THRM_FLT_CTL_VBAT_COEF_SEL_MASK) |
FIELD_PREP_CONST(WSA884X_VBAT_THRM_FLT_CTL_VBAT_COEF_SEL_MASK, 0x4) },
{ WSA884X_VBAT_CAL_CTL, FIELD_PREP_CONST(WSA884X_VBAT_CAL_CTL_RESERVE_MASK, 0x2) |
FIELD_PREP_CONST(WSA884X_VBAT_CAL_CTL_VBAT_CAL_EN_MASK, 0x1) },
{ WSA884X_BOP_DEGLITCH_CTL, FIELD_PREP_CONST(WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_SETTING_MASK, 0x8) |
FIELD_PREP_CONST(WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_EN_MASK, 0x1) },
{ WSA884X_CDC_SPK_DSM_A2_0, 0x0a },
{ WSA884X_CDC_SPK_DSM_A2_1, 0x08 },
{ WSA884X_CDC_SPK_DSM_A3_0, 0xf3 },
{ WSA884X_CDC_SPK_DSM_A3_1, 0x07 },
{ WSA884X_CDC_SPK_DSM_A4_0, 0x79 },
{ WSA884X_CDC_SPK_DSM_A5_0, 0x0b },
{ WSA884X_CDC_SPK_DSM_A6_0, 0x8a },
{ WSA884X_CDC_SPK_DSM_A7_0, 0x9b },
{ WSA884X_CDC_SPK_DSM_C_0, FIELD_PREP_CONST(WSA884X_CDC_SPK_DSM_C_0_COEF_C3_MASK, 0x6) |
FIELD_PREP_CONST(WSA884X_CDC_SPK_DSM_C_0_COEF_C2_MASK, 0x8) },
{ WSA884X_CDC_SPK_DSM_C_2, FIELD_PREP_CONST(WSA884X_CDC_SPK_DSM_C_2_COEF_C7_MASK, 0xf) },
{ WSA884X_CDC_SPK_DSM_C_3, FIELD_PREP_CONST(WSA884X_CDC_SPK_DSM_C_3_COEF_C7_MASK, 0x20) },
{ WSA884X_CDC_SPK_DSM_R1, 0x83 },
{ WSA884X_CDC_SPK_DSM_R2, 0x7f },
{ WSA884X_CDC_SPK_DSM_R3, 0x9d },
{ WSA884X_CDC_SPK_DSM_R4, 0x82 },
{ WSA884X_CDC_SPK_DSM_R5, 0x8b },
{ WSA884X_CDC_SPK_DSM_R6, 0x9b },
{ WSA884X_CDC_SPK_DSM_R7, 0x3f },
/* Speaker mode by default */
{ WSA884X_DRE_CTL_0, FIELD_PREP_CONST(WSA884X_DRE_CTL_0_PROG_DELAY_MASK, 0x7) },
{ WSA884X_CLSH_CTL_0, (0x37 & ~WSA884X_CLSH_CTL_0_DLY_CODE_MASK) |
FIELD_PREP_CONST(WSA884X_CLSH_CTL_0_DLY_CODE_MASK, 0x6) },
/*
* WSA884X_CLSH_VTH values for speaker mode with G_21_DB system gain,
* battery 1S and rload 8 Ohms.
*/
{ WSA884X_CLSH_VTH1, WSA884X_VTH_TO_REG(863), },
{ WSA884X_CLSH_VTH2, WSA884X_VTH_TO_REG(918), },
{ WSA884X_CLSH_VTH3, WSA884X_VTH_TO_REG(980), },
{ WSA884X_CLSH_VTH4, WSA884X_VTH_TO_REG(1043), },
{ WSA884X_CLSH_VTH5, WSA884X_VTH_TO_REG(1098), },
{ WSA884X_CLSH_VTH6, WSA884X_VTH_TO_REG(1137), },
{ WSA884X_CLSH_VTH7, WSA884X_VTH_TO_REG(1184), },
{ WSA884X_CLSH_VTH8, WSA884X_VTH_TO_REG(1239), },
{ WSA884X_CLSH_VTH9, WSA884X_VTH_TO_REG(1278), },
{ WSA884X_CLSH_VTH10, WSA884X_VTH_TO_REG(1380), },
{ WSA884X_CLSH_VTH11, WSA884X_VTH_TO_REG(1482), },
{ WSA884X_CLSH_VTH12, WSA884X_VTH_TO_REG(1584), },
{ WSA884X_CLSH_VTH13, WSA884X_VTH_TO_REG(1663), },
{ WSA884X_CLSH_VTH14, WSA884X_VTH_TO_REG(1780), },
{ WSA884X_CLSH_VTH15, WSA884X_VTH_TO_REG(2000), },
{ WSA884X_ANA_WO_CTL_1, 0x00 },
{ WSA884X_OTP_REG_38, 0x00 },
{ WSA884X_OTP_REG_40, FIELD_PREP_CONST(WSA884X_OTP_REG_40_ISENSE_RESCAL_MASK, 0x8) },
};
static void wsa884x_set_gain_parameters(struct wsa884x_priv *wsa884x)
{
struct regmap *regmap = wsa884x->regmap;
unsigned int min_gain, igain, vgain, comp_offset;
/*
* Downstream sets gain parameters customized per boards per use-case.
* Choose here some sane values matching knowon users, like QRD8550
* board:.
*
* Values match here downstream:
* For WSA884X_RECEIVER - G_7P5_DB system gain
* For WSA884X_SPEAKER - G_21_DB system gain
*/
if (wsa884x->dev_mode == WSA884X_RECEIVER) {
comp_offset = COMP_OFFSET4;
min_gain = G_M6_DB;
igain = ISENSE_18_DB;
vgain = VSENSE_M12_DB;
} else {
/* WSA884X_SPEAKER */
comp_offset = COMP_OFFSET0;
min_gain = G_0_DB;
igain = ISENSE_12_DB;
vgain = VSENSE_M24_DB;
}
regmap_update_bits(regmap, WSA884X_ISENSE2,
WSA884X_ISENSE2_ISENSE_GAIN_CTL_MASK,
FIELD_PREP(WSA884X_ISENSE2_ISENSE_GAIN_CTL_MASK, igain));
regmap_update_bits(regmap, WSA884X_VSENSE1,
WSA884X_VSENSE1_GAIN_VSENSE_FE_MASK,
FIELD_PREP(WSA884X_VSENSE1_GAIN_VSENSE_FE_MASK, vgain));
regmap_update_bits(regmap, WSA884X_GAIN_RAMPING_MIN,
WSA884X_GAIN_RAMPING_MIN_MIN_GAIN_MASK,
FIELD_PREP(WSA884X_GAIN_RAMPING_MIN_MIN_GAIN_MASK, min_gain));
if (wsa884x->port_enable[WSA884X_PORT_COMP]) {
regmap_update_bits(regmap, WSA884X_DRE_CTL_0,
WSA884X_DRE_CTL_0_OFFSET_MASK,
FIELD_PREP(WSA884X_DRE_CTL_0_OFFSET_MASK, comp_offset));
regmap_update_bits(regmap, WSA884X_DRE_CTL_1,
WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK,
FIELD_PREP(WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK, 0x0));
} else {
regmap_update_bits(regmap, WSA884X_DRE_CTL_1,
WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK,
FIELD_PREP(WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK, 0x1));
}
}
static void wsa884x_init(struct wsa884x_priv *wsa884x)
{
unsigned int wo_ctl_0;
unsigned int variant = 0;
if (!regmap_read(wsa884x->regmap, WSA884X_OTP_REG_0, &variant))
wsa884x->variant = variant & WSA884X_OTP_REG_0_ID_MASK;
regmap_multi_reg_write(wsa884x->regmap, wsa884x_reg_init,
ARRAY_SIZE(wsa884x_reg_init));
wo_ctl_0 = 0xc;
wo_ctl_0 |= FIELD_PREP(WSA884X_ANA_WO_CTL_0_DAC_CM_CLAMP_EN_MASK,
WSA884X_ANA_WO_CTL_0_DAC_CM_CLAMP_EN_MODE_SPEAKER);
/* Assume that compander is enabled by default unless it is haptics sku */
if (wsa884x->variant == WSA884X_OTP_ID_WSA8845H)
wo_ctl_0 |= FIELD_PREP(WSA884X_ANA_WO_CTL_0_PA_AUX_GAIN_MASK,
WSA884X_ANA_WO_CTL_0_PA_AUX_18_DB);
else
wo_ctl_0 |= FIELD_PREP(WSA884X_ANA_WO_CTL_0_PA_AUX_GAIN_MASK,
WSA884X_ANA_WO_CTL_0_PA_AUX_0_DB);
regmap_write(wsa884x->regmap, WSA884X_ANA_WO_CTL_0, wo_ctl_0);
wsa884x_set_gain_parameters(wsa884x);
wsa884x->hw_init = false;
}
static int wsa884x_update_status(struct sdw_slave *slave,
enum sdw_slave_status status)
{
struct wsa884x_priv *wsa884x = dev_get_drvdata(&slave->dev);
int ret;
if (status == SDW_SLAVE_UNATTACHED) {
wsa884x->hw_init = false;
regcache_cache_only(wsa884x->regmap, true);
regcache_mark_dirty(wsa884x->regmap);
return 0;
}
if (wsa884x->hw_init || status != SDW_SLAVE_ATTACHED)
return 0;
regcache_cache_only(wsa884x->regmap, false);
ret = regcache_sync(wsa884x->regmap);
if (ret < 0) {
dev_err(&slave->dev, "Cannot sync regmap cache\n");
return ret;
}
wsa884x_init(wsa884x);
return 0;
}
static int wsa884x_port_prep(struct sdw_slave *slave,
struct sdw_prepare_ch *prepare_ch,
enum sdw_port_prep_ops state)
{
struct wsa884x_priv *wsa884x = dev_get_drvdata(&slave->dev);
if (state == SDW_OPS_PORT_POST_PREP)
wsa884x->port_prepared[prepare_ch->num - 1] = true;
else
wsa884x->port_prepared[prepare_ch->num - 1] = false;
return 0;
}
static const struct sdw_slave_ops wsa884x_slave_ops = {
.update_status = wsa884x_update_status,
.port_prep = wsa884x_port_prep,
};
static int wsa884x_dev_mode_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
ucontrol->value.enumerated.item[0] = wsa884x->dev_mode;
return 0;
}
static int wsa884x_dev_mode_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
if (wsa884x->dev_mode == ucontrol->value.enumerated.item[0])
return 0;
wsa884x->dev_mode = ucontrol->value.enumerated.item[0];
return 1;
}
static int wsa884x_get_swr_port(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(comp);
struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
int portidx = mixer->reg;
ucontrol->value.integer.value[0] = wsa884x->port_enable[portidx];
return 0;
}
static int wsa884x_set_swr_port(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(comp);
struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
int portidx = mixer->reg;
if (ucontrol->value.integer.value[0]) {
if (wsa884x->port_enable[portidx])
return 0;
wsa884x->port_enable[portidx] = true;
} else {
if (!wsa884x->port_enable[portidx])
return 0;
wsa884x->port_enable[portidx] = false;
}
return 1;
}
static int wsa884x_codec_probe(struct snd_soc_component *comp)
{
struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(comp);
snd_soc_component_init_regmap(comp, wsa884x->regmap);
return 0;
}
static void wsa884x_spkr_post_pmu(struct snd_soc_component *component,
struct wsa884x_priv *wsa884x)
{
unsigned int curr_limit, curr_ovrd_en;
wsa884x_set_gain_parameters(wsa884x);
if (wsa884x->dev_mode == WSA884X_RECEIVER) {
snd_soc_component_write_field(component, WSA884X_DRE_CTL_0,
WSA884X_DRE_CTL_0_PROG_DELAY_MASK, 0x3);
snd_soc_component_write_field(component, WSA884X_CDC_PATH_MODE,
WSA884X_CDC_PATH_MODE_RXD_MODE_MASK,
0x1);
snd_soc_component_write_field(component, WSA884X_PWM_CLK_CTL,
WSA884X_PWM_CLK_CTL_PWM_CLK_FREQ_SEL_MASK,
0x1);
} else {
/* WSA884X_SPEAKER */
snd_soc_component_write_field(component, WSA884X_DRE_CTL_0,
WSA884X_DRE_CTL_0_PROG_DELAY_MASK, 0xf);
}
if (wsa884x->port_enable[WSA884X_PORT_PBR]) {
curr_ovrd_en = 0x0;
curr_limit = 0x15;
} else {
curr_ovrd_en = 0x1;
if (wsa884x->dev_mode == WSA884X_RECEIVER)
curr_limit = 0x9;
else
curr_limit = 0x15;
}
snd_soc_component_write_field(component, WSA884X_CURRENT_LIMIT,
WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_OVRD_EN_MASK,
curr_ovrd_en);
snd_soc_component_write_field(component, WSA884X_CURRENT_LIMIT,
WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_MASK,
curr_limit);
}
static int wsa884x_spkr_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
wsa884x_spkr_post_pmu(component, wsa884x);
snd_soc_component_write_field(component, WSA884X_PDM_WD_CTL,
WSA884X_PDM_WD_CTL_PDM_WD_EN_MASK,
0x1);
snd_soc_component_write_field(component, WSA884X_PA_FSM_EN,
WSA884X_PA_FSM_EN_GLOBAL_PA_EN_MASK,
0x1);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_write_field(component, WSA884X_PA_FSM_EN,
WSA884X_PA_FSM_EN_GLOBAL_PA_EN_MASK,
0x0);
snd_soc_component_write_field(component, WSA884X_PDM_WD_CTL,
WSA884X_PDM_WD_CTL_PDM_WD_EN_MASK,
0x0);
break;
}
return 0;
}
static const struct snd_soc_dapm_widget wsa884x_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("IN"),
SND_SOC_DAPM_SPK("SPKR", wsa884x_spkr_event),
};
static const DECLARE_TLV_DB_SCALE(pa_gain, -900, 150, -900);
static const struct snd_kcontrol_new wsa884x_snd_controls[] = {
SOC_SINGLE_RANGE_TLV("PA Volume", WSA884X_DRE_CTL_1,
WSA884X_DRE_CTL_1_CSR_GAIN_SHIFT,
0x0, 0x1f, 1, pa_gain),
SOC_ENUM_EXT("WSA MODE", wsa884x_dev_mode_enum,
wsa884x_dev_mode_get, wsa884x_dev_mode_put),
SOC_SINGLE_EXT("DAC Switch", WSA884X_PORT_DAC, 0, 1, 0,
wsa884x_get_swr_port, wsa884x_set_swr_port),
SOC_SINGLE_EXT("COMP Switch", WSA884X_PORT_COMP, 0, 1, 0,
wsa884x_get_swr_port, wsa884x_set_swr_port),
SOC_SINGLE_EXT("BOOST Switch", WSA884X_PORT_BOOST, 0, 1, 0,
wsa884x_get_swr_port, wsa884x_set_swr_port),
SOC_SINGLE_EXT("PBR Switch", WSA884X_PORT_PBR, 0, 1, 0,
wsa884x_get_swr_port, wsa884x_set_swr_port),
SOC_SINGLE_EXT("VISENSE Switch", WSA884X_PORT_VISENSE, 0, 1, 0,
wsa884x_get_swr_port, wsa884x_set_swr_port),
SOC_SINGLE_EXT("CPS Switch", WSA884X_PORT_CPS, 0, 1, 0,
wsa884x_get_swr_port, wsa884x_set_swr_port),
};
static const struct snd_soc_dapm_route wsa884x_audio_map[] = {
{"SPKR", NULL, "IN"},
};
static const struct snd_soc_component_driver wsa884x_component_drv = {
.name = "WSA884x",
.probe = wsa884x_codec_probe,
.controls = wsa884x_snd_controls,
.num_controls = ARRAY_SIZE(wsa884x_snd_controls),
.dapm_widgets = wsa884x_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wsa884x_dapm_widgets),
.dapm_routes = wsa884x_audio_map,
.num_dapm_routes = ARRAY_SIZE(wsa884x_audio_map),
};
static int wsa884x_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct wsa884x_priv *wsa884x = dev_get_drvdata(dai->dev);
int i;
wsa884x->active_ports = 0;
for (i = 0; i < WSA884X_MAX_SWR_PORTS; i++) {
if (!wsa884x->port_enable[i])
continue;
wsa884x->port_config[wsa884x->active_ports] = wsa884x_pconfig[i];
wsa884x->active_ports++;
}
wsa884x->sconfig.frame_rate = params_rate(params);
return sdw_stream_add_slave(wsa884x->slave, &wsa884x->sconfig,
wsa884x->port_config, wsa884x->active_ports,
wsa884x->sruntime);
}
static int wsa884x_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct wsa884x_priv *wsa884x = dev_get_drvdata(dai->dev);
sdw_stream_remove_slave(wsa884x->slave, wsa884x->sruntime);
return 0;
}
static int wsa884x_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
{
struct snd_soc_component *component = dai->component;
if (mute) {
snd_soc_component_write_field(component, WSA884X_DRE_CTL_1,
WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK,
0x0);
snd_soc_component_write_field(component, WSA884X_PA_FSM_EN,
WSA884X_PA_FSM_EN_GLOBAL_PA_EN_MASK,
0x0);
} else {
snd_soc_component_write_field(component, WSA884X_DRE_CTL_1,
WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK,
0x1);
snd_soc_component_write_field(component, WSA884X_PA_FSM_EN,
WSA884X_PA_FSM_EN_GLOBAL_PA_EN_MASK,
0x1);
}
return 0;
}
static int wsa884x_set_stream(struct snd_soc_dai *dai,
void *stream, int direction)
{
struct wsa884x_priv *wsa884x = dev_get_drvdata(dai->dev);
wsa884x->sruntime = stream;
return 0;
}
static const struct snd_soc_dai_ops wsa884x_dai_ops = {
.hw_params = wsa884x_hw_params,
.hw_free = wsa884x_hw_free,
.mute_stream = wsa884x_mute_stream,
.set_stream = wsa884x_set_stream,
};
static struct snd_soc_dai_driver wsa884x_dais[] = {
{
.name = "SPKR",
.playback = {
.stream_name = "SPKR Playback",
.rates = WSA884X_RATES | WSA884X_FRAC_RATES,
.formats = WSA884X_FORMATS,
.rate_min = 8000,
.rate_max = 384000,
.channels_min = 1,
.channels_max = 1,
},
.ops = &wsa884x_dai_ops,
},
};
static void wsa884x_gpio_powerdown(void *data)
{
gpiod_direction_output(data, 1);
}
static void wsa884x_regulator_disable(void *data)
{
regulator_bulk_disable(WSA884X_SUPPLIES_NUM, data);
}
static int wsa884x_probe(struct sdw_slave *pdev,
const struct sdw_device_id *id)
{
struct device *dev = &pdev->dev;
struct wsa884x_priv *wsa884x;
unsigned int i;
int ret;
wsa884x = devm_kzalloc(dev, sizeof(*wsa884x), GFP_KERNEL);
if (!wsa884x)
return -ENOMEM;
for (i = 0; i < WSA884X_SUPPLIES_NUM; i++)
wsa884x->supplies[i].supply = wsa884x_supply_name[i];
ret = devm_regulator_bulk_get(dev, WSA884X_SUPPLIES_NUM,
wsa884x->supplies);
if (ret)
return dev_err_probe(dev, ret, "Failed to get regulators\n");
ret = regulator_bulk_enable(WSA884X_SUPPLIES_NUM, wsa884x->supplies);
if (ret)
return dev_err_probe(dev, ret, "Failed to enable regulators\n");
ret = devm_add_action_or_reset(dev, wsa884x_regulator_disable,
wsa884x->supplies);
if (ret)
return ret;
wsa884x->sd_n = devm_gpiod_get_optional(dev, "powerdown",
GPIOD_OUT_HIGH);
if (IS_ERR(wsa884x->sd_n))
return dev_err_probe(dev, PTR_ERR(wsa884x->sd_n),
"Shutdown Control GPIO not found\n");
dev_set_drvdata(dev, wsa884x);
wsa884x->slave = pdev;
wsa884x->dev = dev;
wsa884x->dev_mode = WSA884X_SPEAKER;
wsa884x->sconfig.ch_count = 1;
wsa884x->sconfig.bps = 1;
wsa884x->sconfig.direction = SDW_DATA_DIR_RX;
wsa884x->sconfig.type = SDW_STREAM_PDM;
pdev->prop.sink_ports = GENMASK(WSA884X_MAX_SWR_PORTS, 0);
pdev->prop.simple_clk_stop_capable = true;
pdev->prop.sink_dpn_prop = wsa884x_sink_dpn_prop;
pdev->prop.scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
/* Bring out of reset */
gpiod_direction_output(wsa884x->sd_n, 0);
ret = devm_add_action_or_reset(dev, wsa884x_gpio_powerdown, wsa884x->sd_n);
if (ret)
return ret;
wsa884x->regmap = devm_regmap_init_sdw(pdev, &wsa884x_regmap_config);
if (IS_ERR(wsa884x->regmap))
return dev_err_probe(dev, PTR_ERR(wsa884x->regmap),
"regmap_init failed\n");
/* Start in cache-only until device is enumerated */
regcache_cache_only(wsa884x->regmap, true);
wsa884x->hw_init = true;
pm_runtime_set_autosuspend_delay(dev, 3000);
pm_runtime_use_autosuspend(dev);
pm_runtime_mark_last_busy(dev);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
return devm_snd_soc_register_component(dev,
&wsa884x_component_drv,
wsa884x_dais,
ARRAY_SIZE(wsa884x_dais));
}
static int __maybe_unused wsa884x_runtime_suspend(struct device *dev)
{
struct regmap *regmap = dev_get_regmap(dev, NULL);
regcache_cache_only(regmap, true);
regcache_mark_dirty(regmap);
return 0;
}
static int __maybe_unused wsa884x_runtime_resume(struct device *dev)
{
struct regmap *regmap = dev_get_regmap(dev, NULL);
regcache_cache_only(regmap, false);
regcache_sync(regmap);
return 0;
}
static const struct dev_pm_ops wsa884x_pm_ops = {
SET_RUNTIME_PM_OPS(wsa884x_runtime_suspend, wsa884x_runtime_resume, NULL)
};
static const struct sdw_device_id wsa884x_swr_id[] = {
SDW_SLAVE_ENTRY(0x0217, 0x204, 0),
{},
};
MODULE_DEVICE_TABLE(sdw, wsa884x_swr_id);
static struct sdw_driver wsa884x_codec_driver = {
.driver = {
.name = "wsa884x-codec",
.pm = &wsa884x_pm_ops,
},
.probe = wsa884x_probe,
.ops = &wsa884x_slave_ops,
.id_table = wsa884x_swr_id,
};
module_sdw_driver(wsa884x_codec_driver);
MODULE_AUTHOR("Krzysztof Kozlowski <[email protected]>");
MODULE_DESCRIPTION("WSA884x codec driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wsa884x.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* cs42l56.c -- CS42L56 ALSA SoC audio driver
*
* Copyright 2014 CirrusLogic, Inc.
*
* Author: Brian Austin <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/input.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/workqueue.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/cs42l56.h>
#include "cs42l56.h"
#define CS42L56_NUM_SUPPLIES 3
static const char *const cs42l56_supply_names[CS42L56_NUM_SUPPLIES] = {
"VA",
"VCP",
"VLDO",
};
struct cs42l56_private {
struct regmap *regmap;
struct snd_soc_component *component;
struct device *dev;
struct cs42l56_platform_data pdata;
struct regulator_bulk_data supplies[CS42L56_NUM_SUPPLIES];
u32 mclk;
u8 mclk_prediv;
u8 mclk_div2;
u8 mclk_ratio;
u8 iface;
u8 iface_fmt;
u8 iface_inv;
#if IS_ENABLED(CONFIG_INPUT)
struct input_dev *beep;
struct work_struct beep_work;
int beep_rate;
#endif
};
static const struct reg_default cs42l56_reg_defaults[] = {
{ 3, 0x7f }, /* r03 - Power Ctl 1 */
{ 4, 0xff }, /* r04 - Power Ctl 2 */
{ 5, 0x00 }, /* ro5 - Clocking Ctl 1 */
{ 6, 0x0b }, /* r06 - Clocking Ctl 2 */
{ 7, 0x00 }, /* r07 - Serial Format */
{ 8, 0x05 }, /* r08 - Class H Ctl */
{ 9, 0x0c }, /* r09 - Misc Ctl */
{ 10, 0x80 }, /* r0a - INT Status */
{ 11, 0x00 }, /* r0b - Playback Ctl */
{ 12, 0x0c }, /* r0c - DSP Mute Ctl */
{ 13, 0x00 }, /* r0d - ADCA Mixer Volume */
{ 14, 0x00 }, /* r0e - ADCB Mixer Volume */
{ 15, 0x00 }, /* r0f - PCMA Mixer Volume */
{ 16, 0x00 }, /* r10 - PCMB Mixer Volume */
{ 17, 0x00 }, /* r11 - Analog Input Advisory Volume */
{ 18, 0x00 }, /* r12 - Digital Input Advisory Volume */
{ 19, 0x00 }, /* r13 - Master A Volume */
{ 20, 0x00 }, /* r14 - Master B Volume */
{ 21, 0x00 }, /* r15 - Beep Freq / On Time */
{ 22, 0x00 }, /* r16 - Beep Volume / Off Time */
{ 23, 0x00 }, /* r17 - Beep Tone Ctl */
{ 24, 0x88 }, /* r18 - Tone Ctl */
{ 25, 0x00 }, /* r19 - Channel Mixer & Swap */
{ 26, 0x00 }, /* r1a - AIN Ref Config / ADC Mux */
{ 27, 0xa0 }, /* r1b - High-Pass Filter Ctl */
{ 28, 0x00 }, /* r1c - Misc ADC Ctl */
{ 29, 0x00 }, /* r1d - Gain & Bias Ctl */
{ 30, 0x00 }, /* r1e - PGAA Mux & Volume */
{ 31, 0x00 }, /* r1f - PGAB Mux & Volume */
{ 32, 0x00 }, /* r20 - ADCA Attenuator */
{ 33, 0x00 }, /* r21 - ADCB Attenuator */
{ 34, 0x00 }, /* r22 - ALC Enable & Attack Rate */
{ 35, 0xbf }, /* r23 - ALC Release Rate */
{ 36, 0x00 }, /* r24 - ALC Threshold */
{ 37, 0x00 }, /* r25 - Noise Gate Ctl */
{ 38, 0x00 }, /* r26 - ALC, Limiter, SFT, ZeroCross */
{ 39, 0x00 }, /* r27 - Analog Mute, LO & HP Mux */
{ 40, 0x00 }, /* r28 - HP A Volume */
{ 41, 0x00 }, /* r29 - HP B Volume */
{ 42, 0x00 }, /* r2a - LINEOUT A Volume */
{ 43, 0x00 }, /* r2b - LINEOUT B Volume */
{ 44, 0x00 }, /* r2c - Limit Threshold Ctl */
{ 45, 0x7f }, /* r2d - Limiter Ctl & Release Rate */
{ 46, 0x00 }, /* r2e - Limiter Attack Rate */
};
static bool cs42l56_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS42L56_CHIP_ID_1 ... CS42L56_LIM_ATTACK_RATE:
return true;
default:
return false;
}
}
static bool cs42l56_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS42L56_INT_STATUS:
return true;
default:
return false;
}
}
static DECLARE_TLV_DB_SCALE(beep_tlv, -5000, 200, 0);
static DECLARE_TLV_DB_SCALE(hl_tlv, -6000, 50, 0);
static DECLARE_TLV_DB_SCALE(adv_tlv, -10200, 50, 0);
static DECLARE_TLV_DB_SCALE(adc_tlv, -9600, 100, 0);
static DECLARE_TLV_DB_SCALE(tone_tlv, -1050, 150, 0);
static DECLARE_TLV_DB_SCALE(preamp_tlv, 0, 1000, 0);
static DECLARE_TLV_DB_SCALE(pga_tlv, -600, 50, 0);
static const DECLARE_TLV_DB_RANGE(ngnb_tlv,
0, 1, TLV_DB_SCALE_ITEM(-8200, 600, 0),
2, 5, TLV_DB_SCALE_ITEM(-7600, 300, 0)
);
static const DECLARE_TLV_DB_RANGE(ngb_tlv,
0, 2, TLV_DB_SCALE_ITEM(-6400, 600, 0),
3, 7, TLV_DB_SCALE_ITEM(-4600, 300, 0)
);
static const DECLARE_TLV_DB_RANGE(alc_tlv,
0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0),
3, 7, TLV_DB_SCALE_ITEM(-1200, 300, 0)
);
static const char * const beep_config_text[] = {
"Off", "Single", "Multiple", "Continuous"
};
static const struct soc_enum beep_config_enum =
SOC_ENUM_SINGLE(CS42L56_BEEP_TONE_CFG, 6,
ARRAY_SIZE(beep_config_text), beep_config_text);
static const char * const beep_pitch_text[] = {
"C4", "C5", "D5", "E5", "F5", "G5", "A5", "B5",
"C6", "D6", "E6", "F6", "G6", "A6", "B6", "C7"
};
static const struct soc_enum beep_pitch_enum =
SOC_ENUM_SINGLE(CS42L56_BEEP_FREQ_ONTIME, 4,
ARRAY_SIZE(beep_pitch_text), beep_pitch_text);
static const char * const beep_ontime_text[] = {
"86 ms", "430 ms", "780 ms", "1.20 s", "1.50 s",
"1.80 s", "2.20 s", "2.50 s", "2.80 s", "3.20 s",
"3.50 s", "3.80 s", "4.20 s", "4.50 s", "4.80 s", "5.20 s"
};
static const struct soc_enum beep_ontime_enum =
SOC_ENUM_SINGLE(CS42L56_BEEP_FREQ_ONTIME, 0,
ARRAY_SIZE(beep_ontime_text), beep_ontime_text);
static const char * const beep_offtime_text[] = {
"1.23 s", "2.58 s", "3.90 s", "5.20 s",
"6.60 s", "8.05 s", "9.35 s", "10.80 s"
};
static const struct soc_enum beep_offtime_enum =
SOC_ENUM_SINGLE(CS42L56_BEEP_FREQ_OFFTIME, 5,
ARRAY_SIZE(beep_offtime_text), beep_offtime_text);
static const char * const beep_treble_text[] = {
"5kHz", "7kHz", "10kHz", "15kHz"
};
static const struct soc_enum beep_treble_enum =
SOC_ENUM_SINGLE(CS42L56_BEEP_TONE_CFG, 3,
ARRAY_SIZE(beep_treble_text), beep_treble_text);
static const char * const beep_bass_text[] = {
"50Hz", "100Hz", "200Hz", "250Hz"
};
static const struct soc_enum beep_bass_enum =
SOC_ENUM_SINGLE(CS42L56_BEEP_TONE_CFG, 1,
ARRAY_SIZE(beep_bass_text), beep_bass_text);
static const char * const pgaa_mux_text[] = {
"AIN1A", "AIN2A", "AIN3A"};
static const struct soc_enum pgaa_mux_enum =
SOC_ENUM_SINGLE(CS42L56_PGAA_MUX_VOLUME, 0,
ARRAY_SIZE(pgaa_mux_text),
pgaa_mux_text);
static const struct snd_kcontrol_new pgaa_mux =
SOC_DAPM_ENUM("Route", pgaa_mux_enum);
static const char * const pgab_mux_text[] = {
"AIN1B", "AIN2B", "AIN3B"};
static const struct soc_enum pgab_mux_enum =
SOC_ENUM_SINGLE(CS42L56_PGAB_MUX_VOLUME, 0,
ARRAY_SIZE(pgab_mux_text),
pgab_mux_text);
static const struct snd_kcontrol_new pgab_mux =
SOC_DAPM_ENUM("Route", pgab_mux_enum);
static const char * const adca_mux_text[] = {
"PGAA", "AIN1A", "AIN2A", "AIN3A"};
static const struct soc_enum adca_mux_enum =
SOC_ENUM_SINGLE(CS42L56_AIN_REFCFG_ADC_MUX, 0,
ARRAY_SIZE(adca_mux_text),
adca_mux_text);
static const struct snd_kcontrol_new adca_mux =
SOC_DAPM_ENUM("Route", adca_mux_enum);
static const char * const adcb_mux_text[] = {
"PGAB", "AIN1B", "AIN2B", "AIN3B"};
static const struct soc_enum adcb_mux_enum =
SOC_ENUM_SINGLE(CS42L56_AIN_REFCFG_ADC_MUX, 2,
ARRAY_SIZE(adcb_mux_text),
adcb_mux_text);
static const struct snd_kcontrol_new adcb_mux =
SOC_DAPM_ENUM("Route", adcb_mux_enum);
static const char * const left_swap_text[] = {
"Left", "LR 2", "Right"};
static const char * const right_swap_text[] = {
"Right", "LR 2", "Left"};
static const unsigned int swap_values[] = { 0, 1, 3 };
static const struct soc_enum adca_swap_enum =
SOC_VALUE_ENUM_SINGLE(CS42L56_CHAN_MIX_SWAP, 0, 3,
ARRAY_SIZE(left_swap_text),
left_swap_text,
swap_values);
static const struct snd_kcontrol_new adca_swap_mux =
SOC_DAPM_ENUM("Route", adca_swap_enum);
static const struct soc_enum pcma_swap_enum =
SOC_VALUE_ENUM_SINGLE(CS42L56_CHAN_MIX_SWAP, 4, 3,
ARRAY_SIZE(left_swap_text),
left_swap_text,
swap_values);
static const struct snd_kcontrol_new pcma_swap_mux =
SOC_DAPM_ENUM("Route", pcma_swap_enum);
static const struct soc_enum adcb_swap_enum =
SOC_VALUE_ENUM_SINGLE(CS42L56_CHAN_MIX_SWAP, 2, 3,
ARRAY_SIZE(right_swap_text),
right_swap_text,
swap_values);
static const struct snd_kcontrol_new adcb_swap_mux =
SOC_DAPM_ENUM("Route", adcb_swap_enum);
static const struct soc_enum pcmb_swap_enum =
SOC_VALUE_ENUM_SINGLE(CS42L56_CHAN_MIX_SWAP, 6, 3,
ARRAY_SIZE(right_swap_text),
right_swap_text,
swap_values);
static const struct snd_kcontrol_new pcmb_swap_mux =
SOC_DAPM_ENUM("Route", pcmb_swap_enum);
static const struct snd_kcontrol_new hpa_switch =
SOC_DAPM_SINGLE("Switch", CS42L56_PWRCTL_2, 6, 1, 1);
static const struct snd_kcontrol_new hpb_switch =
SOC_DAPM_SINGLE("Switch", CS42L56_PWRCTL_2, 4, 1, 1);
static const struct snd_kcontrol_new loa_switch =
SOC_DAPM_SINGLE("Switch", CS42L56_PWRCTL_2, 2, 1, 1);
static const struct snd_kcontrol_new lob_switch =
SOC_DAPM_SINGLE("Switch", CS42L56_PWRCTL_2, 0, 1, 1);
static const char * const hploa_input_text[] = {
"DACA", "PGAA"};
static const struct soc_enum lineouta_input_enum =
SOC_ENUM_SINGLE(CS42L56_AMUTE_HPLO_MUX, 2,
ARRAY_SIZE(hploa_input_text),
hploa_input_text);
static const struct snd_kcontrol_new lineouta_input =
SOC_DAPM_ENUM("Route", lineouta_input_enum);
static const struct soc_enum hpa_input_enum =
SOC_ENUM_SINGLE(CS42L56_AMUTE_HPLO_MUX, 0,
ARRAY_SIZE(hploa_input_text),
hploa_input_text);
static const struct snd_kcontrol_new hpa_input =
SOC_DAPM_ENUM("Route", hpa_input_enum);
static const char * const hplob_input_text[] = {
"DACB", "PGAB"};
static const struct soc_enum lineoutb_input_enum =
SOC_ENUM_SINGLE(CS42L56_AMUTE_HPLO_MUX, 3,
ARRAY_SIZE(hplob_input_text),
hplob_input_text);
static const struct snd_kcontrol_new lineoutb_input =
SOC_DAPM_ENUM("Route", lineoutb_input_enum);
static const struct soc_enum hpb_input_enum =
SOC_ENUM_SINGLE(CS42L56_AMUTE_HPLO_MUX, 1,
ARRAY_SIZE(hplob_input_text),
hplob_input_text);
static const struct snd_kcontrol_new hpb_input =
SOC_DAPM_ENUM("Route", hpb_input_enum);
static const char * const dig_mux_text[] = {
"ADC", "DSP"};
static const struct soc_enum dig_mux_enum =
SOC_ENUM_SINGLE(CS42L56_MISC_CTL, 7,
ARRAY_SIZE(dig_mux_text),
dig_mux_text);
static const struct snd_kcontrol_new dig_mux =
SOC_DAPM_ENUM("Route", dig_mux_enum);
static const char * const hpf_freq_text[] = {
"1.8Hz", "119Hz", "236Hz", "464Hz"
};
static const struct soc_enum hpfa_freq_enum =
SOC_ENUM_SINGLE(CS42L56_HPF_CTL, 0,
ARRAY_SIZE(hpf_freq_text), hpf_freq_text);
static const struct soc_enum hpfb_freq_enum =
SOC_ENUM_SINGLE(CS42L56_HPF_CTL, 2,
ARRAY_SIZE(hpf_freq_text), hpf_freq_text);
static const char * const ng_delay_text[] = {
"50ms", "100ms", "150ms", "200ms"
};
static const struct soc_enum ng_delay_enum =
SOC_ENUM_SINGLE(CS42L56_NOISE_GATE_CTL, 0,
ARRAY_SIZE(ng_delay_text), ng_delay_text);
static const struct snd_kcontrol_new cs42l56_snd_controls[] = {
SOC_DOUBLE_R_SX_TLV("Master Volume", CS42L56_MASTER_A_VOLUME,
CS42L56_MASTER_B_VOLUME, 0, 0x34, 0xE4, adv_tlv),
SOC_DOUBLE("Master Mute Switch", CS42L56_DSP_MUTE_CTL, 0, 1, 1, 1),
SOC_DOUBLE_R_SX_TLV("ADC Mixer Volume", CS42L56_ADCA_MIX_VOLUME,
CS42L56_ADCB_MIX_VOLUME, 0, 0x88, 0x90, hl_tlv),
SOC_DOUBLE("ADC Mixer Mute Switch", CS42L56_DSP_MUTE_CTL, 6, 7, 1, 1),
SOC_DOUBLE_R_SX_TLV("PCM Mixer Volume", CS42L56_PCMA_MIX_VOLUME,
CS42L56_PCMB_MIX_VOLUME, 0, 0x88, 0x90, hl_tlv),
SOC_DOUBLE("PCM Mixer Mute Switch", CS42L56_DSP_MUTE_CTL, 4, 5, 1, 1),
SOC_SINGLE_TLV("Analog Advisory Volume",
CS42L56_ANAINPUT_ADV_VOLUME, 0, 0x00, 1, adv_tlv),
SOC_SINGLE_TLV("Digital Advisory Volume",
CS42L56_DIGINPUT_ADV_VOLUME, 0, 0x00, 1, adv_tlv),
SOC_DOUBLE_R_SX_TLV("PGA Volume", CS42L56_PGAA_MUX_VOLUME,
CS42L56_PGAB_MUX_VOLUME, 0, 0x34, 0x24, pga_tlv),
SOC_DOUBLE_R_TLV("ADC Volume", CS42L56_ADCA_ATTENUATOR,
CS42L56_ADCB_ATTENUATOR, 0, 0x00, 1, adc_tlv),
SOC_DOUBLE("ADC Mute Switch", CS42L56_MISC_ADC_CTL, 2, 3, 1, 1),
SOC_DOUBLE("ADC Boost Switch", CS42L56_GAIN_BIAS_CTL, 3, 2, 1, 1),
SOC_DOUBLE_R_SX_TLV("Headphone Volume", CS42L56_HPA_VOLUME,
CS42L56_HPB_VOLUME, 0, 0x44, 0x48, hl_tlv),
SOC_DOUBLE_R_SX_TLV("LineOut Volume", CS42L56_LOA_VOLUME,
CS42L56_LOB_VOLUME, 0, 0x44, 0x48, hl_tlv),
SOC_SINGLE_TLV("Bass Shelving Volume", CS42L56_TONE_CTL,
0, 0x00, 1, tone_tlv),
SOC_SINGLE_TLV("Treble Shelving Volume", CS42L56_TONE_CTL,
4, 0x00, 1, tone_tlv),
SOC_DOUBLE_TLV("PGA Preamp Volume", CS42L56_GAIN_BIAS_CTL,
4, 6, 0x02, 1, preamp_tlv),
SOC_SINGLE("DSP Switch", CS42L56_PLAYBACK_CTL, 7, 1, 1),
SOC_SINGLE("Gang Playback Switch", CS42L56_PLAYBACK_CTL, 4, 1, 1),
SOC_SINGLE("Gang ADC Switch", CS42L56_MISC_ADC_CTL, 7, 1, 1),
SOC_SINGLE("Gang PGA Switch", CS42L56_MISC_ADC_CTL, 6, 1, 1),
SOC_SINGLE("PCMA Invert", CS42L56_PLAYBACK_CTL, 2, 1, 1),
SOC_SINGLE("PCMB Invert", CS42L56_PLAYBACK_CTL, 3, 1, 1),
SOC_SINGLE("ADCA Invert", CS42L56_MISC_ADC_CTL, 2, 1, 1),
SOC_SINGLE("ADCB Invert", CS42L56_MISC_ADC_CTL, 3, 1, 1),
SOC_DOUBLE("HPF Switch", CS42L56_HPF_CTL, 5, 7, 1, 1),
SOC_DOUBLE("HPF Freeze Switch", CS42L56_HPF_CTL, 4, 6, 1, 1),
SOC_ENUM("HPFA Corner Freq", hpfa_freq_enum),
SOC_ENUM("HPFB Corner Freq", hpfb_freq_enum),
SOC_SINGLE("Analog Soft Ramp", CS42L56_MISC_CTL, 4, 1, 1),
SOC_DOUBLE("Analog Soft Ramp Disable", CS42L56_ALC_LIM_SFT_ZC,
7, 5, 1, 1),
SOC_SINGLE("Analog Zero Cross", CS42L56_MISC_CTL, 3, 1, 1),
SOC_DOUBLE("Analog Zero Cross Disable", CS42L56_ALC_LIM_SFT_ZC,
6, 4, 1, 1),
SOC_SINGLE("Digital Soft Ramp", CS42L56_MISC_CTL, 2, 1, 1),
SOC_SINGLE("Digital Soft Ramp Disable", CS42L56_ALC_LIM_SFT_ZC,
3, 1, 1),
SOC_SINGLE("HL Deemphasis", CS42L56_PLAYBACK_CTL, 6, 1, 1),
SOC_SINGLE("ALC Switch", CS42L56_ALC_EN_ATTACK_RATE, 6, 1, 1),
SOC_SINGLE("ALC Limit All Switch", CS42L56_ALC_RELEASE_RATE, 7, 1, 1),
SOC_SINGLE_RANGE("ALC Attack", CS42L56_ALC_EN_ATTACK_RATE,
0, 0, 0x3f, 0),
SOC_SINGLE_RANGE("ALC Release", CS42L56_ALC_RELEASE_RATE,
0, 0x3f, 0, 0),
SOC_SINGLE_TLV("ALC MAX", CS42L56_ALC_THRESHOLD,
5, 0x07, 1, alc_tlv),
SOC_SINGLE_TLV("ALC MIN", CS42L56_ALC_THRESHOLD,
2, 0x07, 1, alc_tlv),
SOC_SINGLE("Limiter Switch", CS42L56_LIM_CTL_RELEASE_RATE, 7, 1, 1),
SOC_SINGLE("Limit All Switch", CS42L56_LIM_CTL_RELEASE_RATE, 6, 1, 1),
SOC_SINGLE_RANGE("Limiter Attack", CS42L56_LIM_ATTACK_RATE,
0, 0, 0x3f, 0),
SOC_SINGLE_RANGE("Limiter Release", CS42L56_LIM_CTL_RELEASE_RATE,
0, 0x3f, 0, 0),
SOC_SINGLE_TLV("Limiter MAX", CS42L56_LIM_THRESHOLD_CTL,
5, 0x07, 1, alc_tlv),
SOC_SINGLE_TLV("Limiter Cushion", CS42L56_ALC_THRESHOLD,
2, 0x07, 1, alc_tlv),
SOC_SINGLE("NG Switch", CS42L56_NOISE_GATE_CTL, 6, 1, 1),
SOC_SINGLE("NG All Switch", CS42L56_NOISE_GATE_CTL, 7, 1, 1),
SOC_SINGLE("NG Boost Switch", CS42L56_NOISE_GATE_CTL, 5, 1, 1),
SOC_SINGLE_TLV("NG Unboost Threshold", CS42L56_NOISE_GATE_CTL,
2, 0x07, 1, ngnb_tlv),
SOC_SINGLE_TLV("NG Boost Threshold", CS42L56_NOISE_GATE_CTL,
2, 0x07, 1, ngb_tlv),
SOC_ENUM("NG Delay", ng_delay_enum),
SOC_ENUM("Beep Config", beep_config_enum),
SOC_ENUM("Beep Pitch", beep_pitch_enum),
SOC_ENUM("Beep on Time", beep_ontime_enum),
SOC_ENUM("Beep off Time", beep_offtime_enum),
SOC_SINGLE_SX_TLV("Beep Volume", CS42L56_BEEP_FREQ_OFFTIME,
0, 0x07, 0x23, beep_tlv),
SOC_SINGLE("Beep Tone Ctl Switch", CS42L56_BEEP_TONE_CFG, 0, 1, 1),
SOC_ENUM("Beep Treble Corner Freq", beep_treble_enum),
SOC_ENUM("Beep Bass Corner Freq", beep_bass_enum),
};
static const struct snd_soc_dapm_widget cs42l56_dapm_widgets[] = {
SND_SOC_DAPM_SIGGEN("Beep"),
SND_SOC_DAPM_SUPPLY("VBUF", CS42L56_PWRCTL_1, 5, 1, NULL, 0),
SND_SOC_DAPM_MICBIAS("MIC1 Bias", CS42L56_PWRCTL_1, 4, 1),
SND_SOC_DAPM_SUPPLY("Charge Pump", CS42L56_PWRCTL_1, 3, 1, NULL, 0),
SND_SOC_DAPM_INPUT("AIN1A"),
SND_SOC_DAPM_INPUT("AIN2A"),
SND_SOC_DAPM_INPUT("AIN1B"),
SND_SOC_DAPM_INPUT("AIN2B"),
SND_SOC_DAPM_INPUT("AIN3A"),
SND_SOC_DAPM_INPUT("AIN3B"),
SND_SOC_DAPM_AIF_OUT("SDOUT", NULL, 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("SDIN", NULL, 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_MUX("Digital Output Mux", SND_SOC_NOPM,
0, 0, &dig_mux),
SND_SOC_DAPM_PGA("PGAA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("PGAB", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX("PGAA Input Mux",
SND_SOC_NOPM, 0, 0, &pgaa_mux),
SND_SOC_DAPM_MUX("PGAB Input Mux",
SND_SOC_NOPM, 0, 0, &pgab_mux),
SND_SOC_DAPM_MUX("ADCA Mux", SND_SOC_NOPM,
0, 0, &adca_mux),
SND_SOC_DAPM_MUX("ADCB Mux", SND_SOC_NOPM,
0, 0, &adcb_mux),
SND_SOC_DAPM_ADC("ADCA", NULL, CS42L56_PWRCTL_1, 1, 1),
SND_SOC_DAPM_ADC("ADCB", NULL, CS42L56_PWRCTL_1, 2, 1),
SND_SOC_DAPM_MUX("ADCA Swap Mux", SND_SOC_NOPM, 0, 0,
&adca_swap_mux),
SND_SOC_DAPM_MUX("ADCB Swap Mux", SND_SOC_NOPM, 0, 0,
&adcb_swap_mux),
SND_SOC_DAPM_MUX("PCMA Swap Mux", SND_SOC_NOPM, 0, 0,
&pcma_swap_mux),
SND_SOC_DAPM_MUX("PCMB Swap Mux", SND_SOC_NOPM, 0, 0,
&pcmb_swap_mux),
SND_SOC_DAPM_DAC("DACA", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DACB", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_OUTPUT("HPA"),
SND_SOC_DAPM_OUTPUT("LOA"),
SND_SOC_DAPM_OUTPUT("HPB"),
SND_SOC_DAPM_OUTPUT("LOB"),
SND_SOC_DAPM_SWITCH("Headphone Right",
CS42L56_PWRCTL_2, 4, 1, &hpb_switch),
SND_SOC_DAPM_SWITCH("Headphone Left",
CS42L56_PWRCTL_2, 6, 1, &hpa_switch),
SND_SOC_DAPM_SWITCH("Lineout Right",
CS42L56_PWRCTL_2, 0, 1, &lob_switch),
SND_SOC_DAPM_SWITCH("Lineout Left",
CS42L56_PWRCTL_2, 2, 1, &loa_switch),
SND_SOC_DAPM_MUX("LINEOUTA Input Mux", SND_SOC_NOPM,
0, 0, &lineouta_input),
SND_SOC_DAPM_MUX("LINEOUTB Input Mux", SND_SOC_NOPM,
0, 0, &lineoutb_input),
SND_SOC_DAPM_MUX("HPA Input Mux", SND_SOC_NOPM,
0, 0, &hpa_input),
SND_SOC_DAPM_MUX("HPB Input Mux", SND_SOC_NOPM,
0, 0, &hpb_input),
};
static const struct snd_soc_dapm_route cs42l56_audio_map[] = {
{"HiFi Capture", "DSP", "Digital Output Mux"},
{"HiFi Capture", "ADC", "Digital Output Mux"},
{"Digital Output Mux", NULL, "ADCA"},
{"Digital Output Mux", NULL, "ADCB"},
{"ADCB", NULL, "ADCB Swap Mux"},
{"ADCA", NULL, "ADCA Swap Mux"},
{"ADCA Swap Mux", NULL, "ADCA"},
{"ADCB Swap Mux", NULL, "ADCB"},
{"DACA", "Left", "ADCA Swap Mux"},
{"DACA", "LR 2", "ADCA Swap Mux"},
{"DACA", "Right", "ADCA Swap Mux"},
{"DACB", "Left", "ADCB Swap Mux"},
{"DACB", "LR 2", "ADCB Swap Mux"},
{"DACB", "Right", "ADCB Swap Mux"},
{"ADCA Mux", NULL, "AIN3A"},
{"ADCA Mux", NULL, "AIN2A"},
{"ADCA Mux", NULL, "AIN1A"},
{"ADCA Mux", NULL, "PGAA"},
{"ADCB Mux", NULL, "AIN3B"},
{"ADCB Mux", NULL, "AIN2B"},
{"ADCB Mux", NULL, "AIN1B"},
{"ADCB Mux", NULL, "PGAB"},
{"PGAA", "AIN1A", "PGAA Input Mux"},
{"PGAA", "AIN2A", "PGAA Input Mux"},
{"PGAA", "AIN3A", "PGAA Input Mux"},
{"PGAB", "AIN1B", "PGAB Input Mux"},
{"PGAB", "AIN2B", "PGAB Input Mux"},
{"PGAB", "AIN3B", "PGAB Input Mux"},
{"PGAA Input Mux", NULL, "AIN1A"},
{"PGAA Input Mux", NULL, "AIN2A"},
{"PGAA Input Mux", NULL, "AIN3A"},
{"PGAB Input Mux", NULL, "AIN1B"},
{"PGAB Input Mux", NULL, "AIN2B"},
{"PGAB Input Mux", NULL, "AIN3B"},
{"LOB", "Switch", "LINEOUTB Input Mux"},
{"LOA", "Switch", "LINEOUTA Input Mux"},
{"LINEOUTA Input Mux", "PGAA", "PGAA"},
{"LINEOUTB Input Mux", "PGAB", "PGAB"},
{"LINEOUTA Input Mux", "DACA", "DACA"},
{"LINEOUTB Input Mux", "DACB", "DACB"},
{"HPA", "Switch", "HPB Input Mux"},
{"HPB", "Switch", "HPA Input Mux"},
{"HPA Input Mux", "PGAA", "PGAA"},
{"HPB Input Mux", "PGAB", "PGAB"},
{"HPA Input Mux", "DACA", "DACA"},
{"HPB Input Mux", "DACB", "DACB"},
{"DACA", NULL, "PCMA Swap Mux"},
{"DACB", NULL, "PCMB Swap Mux"},
{"PCMB Swap Mux", "Left", "HiFi Playback"},
{"PCMB Swap Mux", "LR 2", "HiFi Playback"},
{"PCMB Swap Mux", "Right", "HiFi Playback"},
{"PCMA Swap Mux", "Left", "HiFi Playback"},
{"PCMA Swap Mux", "LR 2", "HiFi Playback"},
{"PCMA Swap Mux", "Right", "HiFi Playback"},
};
struct cs42l56_clk_para {
u32 mclk;
u32 srate;
u8 ratio;
};
static const struct cs42l56_clk_para clk_ratio_table[] = {
/* 8k */
{ 6000000, 8000, CS42L56_MCLK_LRCLK_768 },
{ 6144000, 8000, CS42L56_MCLK_LRCLK_750 },
{ 12000000, 8000, CS42L56_MCLK_LRCLK_768 },
{ 12288000, 8000, CS42L56_MCLK_LRCLK_750 },
{ 24000000, 8000, CS42L56_MCLK_LRCLK_768 },
{ 24576000, 8000, CS42L56_MCLK_LRCLK_750 },
/* 11.025k */
{ 5644800, 11025, CS42L56_MCLK_LRCLK_512},
{ 11289600, 11025, CS42L56_MCLK_LRCLK_512},
{ 22579200, 11025, CS42L56_MCLK_LRCLK_512 },
/* 11.0294k */
{ 6000000, 110294, CS42L56_MCLK_LRCLK_544 },
{ 12000000, 110294, CS42L56_MCLK_LRCLK_544 },
{ 24000000, 110294, CS42L56_MCLK_LRCLK_544 },
/* 12k */
{ 6000000, 12000, CS42L56_MCLK_LRCLK_500 },
{ 6144000, 12000, CS42L56_MCLK_LRCLK_512 },
{ 12000000, 12000, CS42L56_MCLK_LRCLK_500 },
{ 12288000, 12000, CS42L56_MCLK_LRCLK_512 },
{ 24000000, 12000, CS42L56_MCLK_LRCLK_500 },
{ 24576000, 12000, CS42L56_MCLK_LRCLK_512 },
/* 16k */
{ 6000000, 16000, CS42L56_MCLK_LRCLK_375 },
{ 6144000, 16000, CS42L56_MCLK_LRCLK_384 },
{ 12000000, 16000, CS42L56_MCLK_LRCLK_375 },
{ 12288000, 16000, CS42L56_MCLK_LRCLK_384 },
{ 24000000, 16000, CS42L56_MCLK_LRCLK_375 },
{ 24576000, 16000, CS42L56_MCLK_LRCLK_384 },
/* 22.050k */
{ 5644800, 22050, CS42L56_MCLK_LRCLK_256 },
{ 11289600, 22050, CS42L56_MCLK_LRCLK_256 },
{ 22579200, 22050, CS42L56_MCLK_LRCLK_256 },
/* 22.0588k */
{ 6000000, 220588, CS42L56_MCLK_LRCLK_272 },
{ 12000000, 220588, CS42L56_MCLK_LRCLK_272 },
{ 24000000, 220588, CS42L56_MCLK_LRCLK_272 },
/* 24k */
{ 6000000, 24000, CS42L56_MCLK_LRCLK_250 },
{ 6144000, 24000, CS42L56_MCLK_LRCLK_256 },
{ 12000000, 24000, CS42L56_MCLK_LRCLK_250 },
{ 12288000, 24000, CS42L56_MCLK_LRCLK_256 },
{ 24000000, 24000, CS42L56_MCLK_LRCLK_250 },
{ 24576000, 24000, CS42L56_MCLK_LRCLK_256 },
/* 32k */
{ 6000000, 32000, CS42L56_MCLK_LRCLK_187P5 },
{ 6144000, 32000, CS42L56_MCLK_LRCLK_192 },
{ 12000000, 32000, CS42L56_MCLK_LRCLK_187P5 },
{ 12288000, 32000, CS42L56_MCLK_LRCLK_192 },
{ 24000000, 32000, CS42L56_MCLK_LRCLK_187P5 },
{ 24576000, 32000, CS42L56_MCLK_LRCLK_192 },
/* 44.118k */
{ 6000000, 44118, CS42L56_MCLK_LRCLK_136 },
{ 12000000, 44118, CS42L56_MCLK_LRCLK_136 },
{ 24000000, 44118, CS42L56_MCLK_LRCLK_136 },
/* 44.1k */
{ 5644800, 44100, CS42L56_MCLK_LRCLK_128 },
{ 11289600, 44100, CS42L56_MCLK_LRCLK_128 },
{ 22579200, 44100, CS42L56_MCLK_LRCLK_128 },
/* 48k */
{ 6000000, 48000, CS42L56_MCLK_LRCLK_125 },
{ 6144000, 48000, CS42L56_MCLK_LRCLK_128 },
{ 12000000, 48000, CS42L56_MCLK_LRCLK_125 },
{ 12288000, 48000, CS42L56_MCLK_LRCLK_128 },
{ 24000000, 48000, CS42L56_MCLK_LRCLK_125 },
{ 24576000, 48000, CS42L56_MCLK_LRCLK_128 },
};
static int cs42l56_get_mclk_ratio(int mclk, int rate)
{
int i;
for (i = 0; i < ARRAY_SIZE(clk_ratio_table); i++) {
if (clk_ratio_table[i].mclk == mclk &&
clk_ratio_table[i].srate == rate)
return clk_ratio_table[i].ratio;
}
return -EINVAL;
}
static int cs42l56_set_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct cs42l56_private *cs42l56 = snd_soc_component_get_drvdata(component);
switch (freq) {
case CS42L56_MCLK_5P6448MHZ:
case CS42L56_MCLK_6MHZ:
case CS42L56_MCLK_6P144MHZ:
cs42l56->mclk_div2 = 0;
cs42l56->mclk_prediv = 0;
break;
case CS42L56_MCLK_11P2896MHZ:
case CS42L56_MCLK_12MHZ:
case CS42L56_MCLK_12P288MHZ:
cs42l56->mclk_div2 = CS42L56_MCLK_DIV2;
cs42l56->mclk_prediv = 0;
break;
case CS42L56_MCLK_22P5792MHZ:
case CS42L56_MCLK_24MHZ:
case CS42L56_MCLK_24P576MHZ:
cs42l56->mclk_div2 = CS42L56_MCLK_DIV2;
cs42l56->mclk_prediv = CS42L56_MCLK_PREDIV;
break;
default:
return -EINVAL;
}
cs42l56->mclk = freq;
snd_soc_component_update_bits(component, CS42L56_CLKCTL_1,
CS42L56_MCLK_PREDIV_MASK,
cs42l56->mclk_prediv);
snd_soc_component_update_bits(component, CS42L56_CLKCTL_1,
CS42L56_MCLK_DIV2_MASK,
cs42l56->mclk_div2);
return 0;
}
static int cs42l56_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct cs42l56_private *cs42l56 = snd_soc_component_get_drvdata(component);
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
cs42l56->iface = CS42L56_MASTER_MODE;
break;
case SND_SOC_DAIFMT_CBS_CFS:
cs42l56->iface = CS42L56_SLAVE_MODE;
break;
default:
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
cs42l56->iface_fmt = CS42L56_DIG_FMT_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
cs42l56->iface_fmt = CS42L56_DIG_FMT_LEFT_J;
break;
default:
return -EINVAL;
}
/* sclk inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
cs42l56->iface_inv = 0;
break;
case SND_SOC_DAIFMT_IB_NF:
cs42l56->iface_inv = CS42L56_SCLK_INV;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, CS42L56_CLKCTL_1,
CS42L56_MS_MODE_MASK, cs42l56->iface);
snd_soc_component_update_bits(component, CS42L56_SERIAL_FMT,
CS42L56_DIG_FMT_MASK, cs42l56->iface_fmt);
snd_soc_component_update_bits(component, CS42L56_CLKCTL_1,
CS42L56_SCLK_INV_MASK, cs42l56->iface_inv);
return 0;
}
static int cs42l56_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
if (mute) {
/* Hit the DSP Mixer first */
snd_soc_component_update_bits(component, CS42L56_DSP_MUTE_CTL,
CS42L56_ADCAMIX_MUTE_MASK |
CS42L56_ADCBMIX_MUTE_MASK |
CS42L56_PCMAMIX_MUTE_MASK |
CS42L56_PCMBMIX_MUTE_MASK |
CS42L56_MSTB_MUTE_MASK |
CS42L56_MSTA_MUTE_MASK,
CS42L56_MUTE_ALL);
/* Mute ADC's */
snd_soc_component_update_bits(component, CS42L56_MISC_ADC_CTL,
CS42L56_ADCA_MUTE_MASK |
CS42L56_ADCB_MUTE_MASK,
CS42L56_MUTE_ALL);
/* HP And LO */
snd_soc_component_update_bits(component, CS42L56_HPA_VOLUME,
CS42L56_HP_MUTE_MASK, CS42L56_MUTE_ALL);
snd_soc_component_update_bits(component, CS42L56_HPB_VOLUME,
CS42L56_HP_MUTE_MASK, CS42L56_MUTE_ALL);
snd_soc_component_update_bits(component, CS42L56_LOA_VOLUME,
CS42L56_LO_MUTE_MASK, CS42L56_MUTE_ALL);
snd_soc_component_update_bits(component, CS42L56_LOB_VOLUME,
CS42L56_LO_MUTE_MASK, CS42L56_MUTE_ALL);
} else {
snd_soc_component_update_bits(component, CS42L56_DSP_MUTE_CTL,
CS42L56_ADCAMIX_MUTE_MASK |
CS42L56_ADCBMIX_MUTE_MASK |
CS42L56_PCMAMIX_MUTE_MASK |
CS42L56_PCMBMIX_MUTE_MASK |
CS42L56_MSTB_MUTE_MASK |
CS42L56_MSTA_MUTE_MASK,
CS42L56_UNMUTE);
snd_soc_component_update_bits(component, CS42L56_MISC_ADC_CTL,
CS42L56_ADCA_MUTE_MASK |
CS42L56_ADCB_MUTE_MASK,
CS42L56_UNMUTE);
snd_soc_component_update_bits(component, CS42L56_HPA_VOLUME,
CS42L56_HP_MUTE_MASK, CS42L56_UNMUTE);
snd_soc_component_update_bits(component, CS42L56_HPB_VOLUME,
CS42L56_HP_MUTE_MASK, CS42L56_UNMUTE);
snd_soc_component_update_bits(component, CS42L56_LOA_VOLUME,
CS42L56_LO_MUTE_MASK, CS42L56_UNMUTE);
snd_soc_component_update_bits(component, CS42L56_LOB_VOLUME,
CS42L56_LO_MUTE_MASK, CS42L56_UNMUTE);
}
return 0;
}
static int cs42l56_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct cs42l56_private *cs42l56 = snd_soc_component_get_drvdata(component);
int ratio;
ratio = cs42l56_get_mclk_ratio(cs42l56->mclk, params_rate(params));
if (ratio >= 0) {
snd_soc_component_update_bits(component, CS42L56_CLKCTL_2,
CS42L56_CLK_RATIO_MASK, ratio);
} else {
dev_err(component->dev, "unsupported mclk/sclk/lrclk ratio\n");
return -EINVAL;
}
return 0;
}
static int cs42l56_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct cs42l56_private *cs42l56 = snd_soc_component_get_drvdata(component);
int ret;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
snd_soc_component_update_bits(component, CS42L56_CLKCTL_1,
CS42L56_MCLK_DIS_MASK, 0);
snd_soc_component_update_bits(component, CS42L56_PWRCTL_1,
CS42L56_PDN_ALL_MASK, 0);
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
regcache_cache_only(cs42l56->regmap, false);
regcache_sync(cs42l56->regmap);
ret = regulator_bulk_enable(ARRAY_SIZE(cs42l56->supplies),
cs42l56->supplies);
if (ret != 0) {
dev_err(cs42l56->dev,
"Failed to enable regulators: %d\n",
ret);
return ret;
}
}
snd_soc_component_update_bits(component, CS42L56_PWRCTL_1,
CS42L56_PDN_ALL_MASK, 1);
break;
case SND_SOC_BIAS_OFF:
snd_soc_component_update_bits(component, CS42L56_PWRCTL_1,
CS42L56_PDN_ALL_MASK, 1);
snd_soc_component_update_bits(component, CS42L56_CLKCTL_1,
CS42L56_MCLK_DIS_MASK, 1);
regcache_cache_only(cs42l56->regmap, true);
regulator_bulk_disable(ARRAY_SIZE(cs42l56->supplies),
cs42l56->supplies);
break;
}
return 0;
}
#define CS42L56_RATES (SNDRV_PCM_RATE_8000_48000)
#define CS42L56_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \
SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops cs42l56_ops = {
.hw_params = cs42l56_pcm_hw_params,
.mute_stream = cs42l56_mute,
.set_fmt = cs42l56_set_dai_fmt,
.set_sysclk = cs42l56_set_sysclk,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver cs42l56_dai = {
.name = "cs42l56",
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 1,
.channels_max = 2,
.rates = CS42L56_RATES,
.formats = CS42L56_FORMATS,
},
.capture = {
.stream_name = "HiFi Capture",
.channels_min = 1,
.channels_max = 2,
.rates = CS42L56_RATES,
.formats = CS42L56_FORMATS,
},
.ops = &cs42l56_ops,
};
static int beep_freq[] = {
261, 522, 585, 667, 706, 774, 889, 1000,
1043, 1200, 1333, 1412, 1600, 1714, 2000, 2182
};
static void cs42l56_beep_work(struct work_struct *work)
{
struct cs42l56_private *cs42l56 =
container_of(work, struct cs42l56_private, beep_work);
struct snd_soc_component *component = cs42l56->component;
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
int i;
int val = 0;
int best = 0;
if (cs42l56->beep_rate) {
for (i = 0; i < ARRAY_SIZE(beep_freq); i++) {
if (abs(cs42l56->beep_rate - beep_freq[i]) <
abs(cs42l56->beep_rate - beep_freq[best]))
best = i;
}
dev_dbg(component->dev, "Set beep rate %dHz for requested %dHz\n",
beep_freq[best], cs42l56->beep_rate);
val = (best << CS42L56_BEEP_RATE_SHIFT);
snd_soc_dapm_enable_pin(dapm, "Beep");
} else {
dev_dbg(component->dev, "Disabling beep\n");
snd_soc_dapm_disable_pin(dapm, "Beep");
}
snd_soc_component_update_bits(component, CS42L56_BEEP_FREQ_ONTIME,
CS42L56_BEEP_FREQ_MASK, val);
snd_soc_dapm_sync(dapm);
}
/* For usability define a way of injecting beep events for the device -
* many systems will not have a keyboard.
*/
static int cs42l56_beep_event(struct input_dev *dev, unsigned int type,
unsigned int code, int hz)
{
struct snd_soc_component *component = input_get_drvdata(dev);
struct cs42l56_private *cs42l56 = snd_soc_component_get_drvdata(component);
dev_dbg(component->dev, "Beep event %x %x\n", code, hz);
switch (code) {
case SND_BELL:
if (hz)
hz = 261;
break;
case SND_TONE:
break;
default:
return -1;
}
/* Kick the beep from a workqueue */
cs42l56->beep_rate = hz;
schedule_work(&cs42l56->beep_work);
return 0;
}
static ssize_t beep_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct cs42l56_private *cs42l56 = dev_get_drvdata(dev);
long int time;
int ret;
ret = kstrtol(buf, 10, &time);
if (ret != 0)
return ret;
input_event(cs42l56->beep, EV_SND, SND_TONE, time);
return count;
}
static DEVICE_ATTR_WO(beep);
static void cs42l56_init_beep(struct snd_soc_component *component)
{
struct cs42l56_private *cs42l56 = snd_soc_component_get_drvdata(component);
int ret;
cs42l56->beep = devm_input_allocate_device(component->dev);
if (!cs42l56->beep) {
dev_err(component->dev, "Failed to allocate beep device\n");
return;
}
INIT_WORK(&cs42l56->beep_work, cs42l56_beep_work);
cs42l56->beep_rate = 0;
cs42l56->beep->name = "CS42L56 Beep Generator";
cs42l56->beep->phys = dev_name(component->dev);
cs42l56->beep->id.bustype = BUS_I2C;
cs42l56->beep->evbit[0] = BIT_MASK(EV_SND);
cs42l56->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
cs42l56->beep->event = cs42l56_beep_event;
cs42l56->beep->dev.parent = component->dev;
input_set_drvdata(cs42l56->beep, component);
ret = input_register_device(cs42l56->beep);
if (ret != 0) {
cs42l56->beep = NULL;
dev_err(component->dev, "Failed to register beep device\n");
}
ret = device_create_file(component->dev, &dev_attr_beep);
if (ret != 0) {
dev_err(component->dev, "Failed to create keyclick file: %d\n",
ret);
}
}
static void cs42l56_free_beep(struct snd_soc_component *component)
{
struct cs42l56_private *cs42l56 = snd_soc_component_get_drvdata(component);
device_remove_file(component->dev, &dev_attr_beep);
cancel_work_sync(&cs42l56->beep_work);
cs42l56->beep = NULL;
snd_soc_component_update_bits(component, CS42L56_BEEP_TONE_CFG,
CS42L56_BEEP_EN_MASK, 0);
}
static int cs42l56_probe(struct snd_soc_component *component)
{
cs42l56_init_beep(component);
return 0;
}
static void cs42l56_remove(struct snd_soc_component *component)
{
cs42l56_free_beep(component);
}
static const struct snd_soc_component_driver soc_component_dev_cs42l56 = {
.probe = cs42l56_probe,
.remove = cs42l56_remove,
.set_bias_level = cs42l56_set_bias_level,
.controls = cs42l56_snd_controls,
.num_controls = ARRAY_SIZE(cs42l56_snd_controls),
.dapm_widgets = cs42l56_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(cs42l56_dapm_widgets),
.dapm_routes = cs42l56_audio_map,
.num_dapm_routes = ARRAY_SIZE(cs42l56_audio_map),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config cs42l56_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = CS42L56_MAX_REGISTER,
.reg_defaults = cs42l56_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(cs42l56_reg_defaults),
.readable_reg = cs42l56_readable_register,
.volatile_reg = cs42l56_volatile_register,
.cache_type = REGCACHE_MAPLE,
};
static int cs42l56_handle_of_data(struct i2c_client *i2c_client,
struct cs42l56_platform_data *pdata)
{
struct device_node *np = i2c_client->dev.of_node;
u32 val32;
if (of_property_read_bool(np, "cirrus,ain1a-reference-cfg"))
pdata->ain1a_ref_cfg = true;
if (of_property_read_bool(np, "cirrus,ain2a-reference-cfg"))
pdata->ain2a_ref_cfg = true;
if (of_property_read_bool(np, "cirrus,ain1b-reference-cfg"))
pdata->ain1b_ref_cfg = true;
if (of_property_read_bool(np, "cirrus,ain2b-reference-cfg"))
pdata->ain2b_ref_cfg = true;
if (of_property_read_u32(np, "cirrus,micbias-lvl", &val32) >= 0)
pdata->micbias_lvl = val32;
if (of_property_read_u32(np, "cirrus,chgfreq-divisor", &val32) >= 0)
pdata->chgfreq = val32;
if (of_property_read_u32(np, "cirrus,adaptive-pwr-cfg", &val32) >= 0)
pdata->adaptive_pwr = val32;
if (of_property_read_u32(np, "cirrus,hpf-left-freq", &val32) >= 0)
pdata->hpfa_freq = val32;
if (of_property_read_u32(np, "cirrus,hpf-left-freq", &val32) >= 0)
pdata->hpfb_freq = val32;
pdata->gpio_nreset = of_get_named_gpio(np, "cirrus,gpio-nreset", 0);
return 0;
}
static int cs42l56_i2c_probe(struct i2c_client *i2c_client)
{
struct cs42l56_private *cs42l56;
struct cs42l56_platform_data *pdata =
dev_get_platdata(&i2c_client->dev);
int ret, i;
unsigned int devid;
unsigned int alpha_rev, metal_rev;
unsigned int reg;
cs42l56 = devm_kzalloc(&i2c_client->dev, sizeof(*cs42l56), GFP_KERNEL);
if (cs42l56 == NULL)
return -ENOMEM;
cs42l56->dev = &i2c_client->dev;
cs42l56->regmap = devm_regmap_init_i2c(i2c_client, &cs42l56_regmap);
if (IS_ERR(cs42l56->regmap)) {
ret = PTR_ERR(cs42l56->regmap);
dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
return ret;
}
if (pdata) {
cs42l56->pdata = *pdata;
} else {
if (i2c_client->dev.of_node) {
ret = cs42l56_handle_of_data(i2c_client,
&cs42l56->pdata);
if (ret != 0)
return ret;
}
}
if (cs42l56->pdata.gpio_nreset) {
ret = gpio_request_one(cs42l56->pdata.gpio_nreset,
GPIOF_OUT_INIT_HIGH, "CS42L56 /RST");
if (ret < 0) {
dev_err(&i2c_client->dev,
"Failed to request /RST %d: %d\n",
cs42l56->pdata.gpio_nreset, ret);
return ret;
}
gpio_set_value_cansleep(cs42l56->pdata.gpio_nreset, 0);
gpio_set_value_cansleep(cs42l56->pdata.gpio_nreset, 1);
}
i2c_set_clientdata(i2c_client, cs42l56);
for (i = 0; i < ARRAY_SIZE(cs42l56->supplies); i++)
cs42l56->supplies[i].supply = cs42l56_supply_names[i];
ret = devm_regulator_bulk_get(&i2c_client->dev,
ARRAY_SIZE(cs42l56->supplies),
cs42l56->supplies);
if (ret != 0) {
dev_err(&i2c_client->dev,
"Failed to request supplies: %d\n", ret);
return ret;
}
ret = regulator_bulk_enable(ARRAY_SIZE(cs42l56->supplies),
cs42l56->supplies);
if (ret != 0) {
dev_err(&i2c_client->dev,
"Failed to enable supplies: %d\n", ret);
return ret;
}
ret = regmap_read(cs42l56->regmap, CS42L56_CHIP_ID_1, ®);
if (ret) {
dev_err(&i2c_client->dev, "Failed to read chip ID: %d\n", ret);
goto err_enable;
}
devid = reg & CS42L56_CHIP_ID_MASK;
if (devid != CS42L56_DEVID) {
dev_err(&i2c_client->dev,
"CS42L56 Device ID (%X). Expected %X\n",
devid, CS42L56_DEVID);
ret = -EINVAL;
goto err_enable;
}
alpha_rev = reg & CS42L56_AREV_MASK;
metal_rev = reg & CS42L56_MTLREV_MASK;
dev_info(&i2c_client->dev, "Cirrus Logic CS42L56 ");
dev_info(&i2c_client->dev, "Alpha Rev %X Metal Rev %X\n",
alpha_rev, metal_rev);
if (cs42l56->pdata.ain1a_ref_cfg)
regmap_update_bits(cs42l56->regmap, CS42L56_AIN_REFCFG_ADC_MUX,
CS42L56_AIN1A_REF_MASK,
CS42L56_AIN1A_REF_MASK);
if (cs42l56->pdata.ain1b_ref_cfg)
regmap_update_bits(cs42l56->regmap, CS42L56_AIN_REFCFG_ADC_MUX,
CS42L56_AIN1B_REF_MASK,
CS42L56_AIN1B_REF_MASK);
if (cs42l56->pdata.ain2a_ref_cfg)
regmap_update_bits(cs42l56->regmap, CS42L56_AIN_REFCFG_ADC_MUX,
CS42L56_AIN2A_REF_MASK,
CS42L56_AIN2A_REF_MASK);
if (cs42l56->pdata.ain2b_ref_cfg)
regmap_update_bits(cs42l56->regmap, CS42L56_AIN_REFCFG_ADC_MUX,
CS42L56_AIN2B_REF_MASK,
CS42L56_AIN2B_REF_MASK);
if (cs42l56->pdata.micbias_lvl)
regmap_update_bits(cs42l56->regmap, CS42L56_GAIN_BIAS_CTL,
CS42L56_MIC_BIAS_MASK,
cs42l56->pdata.micbias_lvl);
if (cs42l56->pdata.chgfreq)
regmap_update_bits(cs42l56->regmap, CS42L56_CLASSH_CTL,
CS42L56_CHRG_FREQ_MASK,
cs42l56->pdata.chgfreq);
if (cs42l56->pdata.hpfb_freq)
regmap_update_bits(cs42l56->regmap, CS42L56_HPF_CTL,
CS42L56_HPFB_FREQ_MASK,
cs42l56->pdata.hpfb_freq);
if (cs42l56->pdata.hpfa_freq)
regmap_update_bits(cs42l56->regmap, CS42L56_HPF_CTL,
CS42L56_HPFA_FREQ_MASK,
cs42l56->pdata.hpfa_freq);
if (cs42l56->pdata.adaptive_pwr)
regmap_update_bits(cs42l56->regmap, CS42L56_CLASSH_CTL,
CS42L56_ADAPT_PWR_MASK,
cs42l56->pdata.adaptive_pwr);
ret = devm_snd_soc_register_component(&i2c_client->dev,
&soc_component_dev_cs42l56, &cs42l56_dai, 1);
if (ret < 0)
goto err_enable;
return 0;
err_enable:
regulator_bulk_disable(ARRAY_SIZE(cs42l56->supplies),
cs42l56->supplies);
return ret;
}
static void cs42l56_i2c_remove(struct i2c_client *client)
{
struct cs42l56_private *cs42l56 = i2c_get_clientdata(client);
regulator_bulk_disable(ARRAY_SIZE(cs42l56->supplies),
cs42l56->supplies);
}
static const struct of_device_id cs42l56_of_match[] = {
{ .compatible = "cirrus,cs42l56", },
{ }
};
MODULE_DEVICE_TABLE(of, cs42l56_of_match);
static const struct i2c_device_id cs42l56_id[] = {
{ "cs42l56", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, cs42l56_id);
static struct i2c_driver cs42l56_i2c_driver = {
.driver = {
.name = "cs42l56",
.of_match_table = cs42l56_of_match,
},
.id_table = cs42l56_id,
.probe = cs42l56_i2c_probe,
.remove = cs42l56_i2c_remove,
};
module_i2c_driver(cs42l56_i2c_driver);
MODULE_DESCRIPTION("ASoC CS42L56 driver");
MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cs42l56.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Nuvoton NAU8825 audio codec driver
*
* Copyright 2015 Google Chromium project.
* Author: Anatol Pomozov <[email protected]>
* Copyright 2015 Nuvoton Technology Corp.
* Co-author: Meng-Huang Kuo <[email protected]>
*/
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/int_log.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/acpi.h>
#include <linux/math64.h>
#include <linux/semaphore.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/jack.h>
#include "nau8825.h"
#define NUVOTON_CODEC_DAI "nau8825-hifi"
#define NAU_FREF_MAX 13500000
#define NAU_FVCO_MAX 124000000
#define NAU_FVCO_MIN 90000000
/* cross talk suppression detection */
#define GAIN_AUGMENT 22500
#define SIDETONE_BASE 207000
/* the maximum frequency of CLK_ADC and CLK_DAC */
#define CLK_DA_AD_MAX 6144000
static int nau8825_configure_sysclk(struct nau8825 *nau8825,
int clk_id, unsigned int freq);
static bool nau8825_is_jack_inserted(struct regmap *regmap);
struct nau8825_fll {
int mclk_src;
int ratio;
int fll_frac;
int fll_frac_num;
int fll_int;
int clk_ref_div;
};
struct nau8825_fll_attr {
unsigned int param;
unsigned int val;
};
/* scaling for mclk from sysclk_src output */
static const struct nau8825_fll_attr mclk_src_scaling[] = {
{ 1, 0x0 },
{ 2, 0x2 },
{ 4, 0x3 },
{ 8, 0x4 },
{ 16, 0x5 },
{ 32, 0x6 },
{ 3, 0x7 },
{ 6, 0xa },
{ 12, 0xb },
{ 24, 0xc },
{ 48, 0xd },
{ 96, 0xe },
{ 5, 0xf },
};
/* ratio for input clk freq */
static const struct nau8825_fll_attr fll_ratio[] = {
{ 512000, 0x01 },
{ 256000, 0x02 },
{ 128000, 0x04 },
{ 64000, 0x08 },
{ 32000, 0x10 },
{ 8000, 0x20 },
{ 4000, 0x40 },
};
static const struct nau8825_fll_attr fll_pre_scalar[] = {
{ 1, 0x0 },
{ 2, 0x1 },
{ 4, 0x2 },
{ 8, 0x3 },
};
/* over sampling rate */
struct nau8825_osr_attr {
unsigned int osr;
unsigned int clk_src;
};
static const struct nau8825_osr_attr osr_dac_sel[] = {
{ 64, 2 }, /* OSR 64, SRC 1/4 */
{ 256, 0 }, /* OSR 256, SRC 1 */
{ 128, 1 }, /* OSR 128, SRC 1/2 */
{ 0, 0 },
{ 32, 3 }, /* OSR 32, SRC 1/8 */
};
static const struct nau8825_osr_attr osr_adc_sel[] = {
{ 32, 3 }, /* OSR 32, SRC 1/8 */
{ 64, 2 }, /* OSR 64, SRC 1/4 */
{ 128, 1 }, /* OSR 128, SRC 1/2 */
{ 256, 0 }, /* OSR 256, SRC 1 */
};
static const struct reg_default nau8825_reg_defaults[] = {
{ NAU8825_REG_ENA_CTRL, 0x00ff },
{ NAU8825_REG_IIC_ADDR_SET, 0x0 },
{ NAU8825_REG_CLK_DIVIDER, 0x0050 },
{ NAU8825_REG_FLL1, 0x0 },
{ NAU8825_REG_FLL2, 0x3126 },
{ NAU8825_REG_FLL3, 0x0008 },
{ NAU8825_REG_FLL4, 0x0010 },
{ NAU8825_REG_FLL5, 0x0 },
{ NAU8825_REG_FLL6, 0x6000 },
{ NAU8825_REG_FLL_VCO_RSV, 0xf13c },
{ NAU8825_REG_HSD_CTRL, 0x000c },
{ NAU8825_REG_JACK_DET_CTRL, 0x0 },
{ NAU8825_REG_INTERRUPT_MASK, 0x0 },
{ NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff },
{ NAU8825_REG_SAR_CTRL, 0x0015 },
{ NAU8825_REG_KEYDET_CTRL, 0x0110 },
{ NAU8825_REG_VDET_THRESHOLD_1, 0x0 },
{ NAU8825_REG_VDET_THRESHOLD_2, 0x0 },
{ NAU8825_REG_VDET_THRESHOLD_3, 0x0 },
{ NAU8825_REG_VDET_THRESHOLD_4, 0x0 },
{ NAU8825_REG_GPIO34_CTRL, 0x0 },
{ NAU8825_REG_GPIO12_CTRL, 0x0 },
{ NAU8825_REG_TDM_CTRL, 0x0 },
{ NAU8825_REG_I2S_PCM_CTRL1, 0x000b },
{ NAU8825_REG_I2S_PCM_CTRL2, 0x8010 },
{ NAU8825_REG_LEFT_TIME_SLOT, 0x0 },
{ NAU8825_REG_RIGHT_TIME_SLOT, 0x0 },
{ NAU8825_REG_BIQ_CTRL, 0x0 },
{ NAU8825_REG_BIQ_COF1, 0x0 },
{ NAU8825_REG_BIQ_COF2, 0x0 },
{ NAU8825_REG_BIQ_COF3, 0x0 },
{ NAU8825_REG_BIQ_COF4, 0x0 },
{ NAU8825_REG_BIQ_COF5, 0x0 },
{ NAU8825_REG_BIQ_COF6, 0x0 },
{ NAU8825_REG_BIQ_COF7, 0x0 },
{ NAU8825_REG_BIQ_COF8, 0x0 },
{ NAU8825_REG_BIQ_COF9, 0x0 },
{ NAU8825_REG_BIQ_COF10, 0x0 },
{ NAU8825_REG_ADC_RATE, 0x0010 },
{ NAU8825_REG_DAC_CTRL1, 0x0001 },
{ NAU8825_REG_DAC_CTRL2, 0x0 },
{ NAU8825_REG_DAC_DGAIN_CTRL, 0x0 },
{ NAU8825_REG_ADC_DGAIN_CTRL, 0x00cf },
{ NAU8825_REG_MUTE_CTRL, 0x0 },
{ NAU8825_REG_HSVOL_CTRL, 0x0 },
{ NAU8825_REG_DACL_CTRL, 0x02cf },
{ NAU8825_REG_DACR_CTRL, 0x00cf },
{ NAU8825_REG_ADC_DRC_KNEE_IP12, 0x1486 },
{ NAU8825_REG_ADC_DRC_KNEE_IP34, 0x0f12 },
{ NAU8825_REG_ADC_DRC_SLOPES, 0x25ff },
{ NAU8825_REG_ADC_DRC_ATKDCY, 0x3457 },
{ NAU8825_REG_DAC_DRC_KNEE_IP12, 0x1486 },
{ NAU8825_REG_DAC_DRC_KNEE_IP34, 0x0f12 },
{ NAU8825_REG_DAC_DRC_SLOPES, 0x25f9 },
{ NAU8825_REG_DAC_DRC_ATKDCY, 0x3457 },
{ NAU8825_REG_IMM_MODE_CTRL, 0x0 },
{ NAU8825_REG_CLASSG_CTRL, 0x0 },
{ NAU8825_REG_OPT_EFUSE_CTRL, 0x0 },
{ NAU8825_REG_MISC_CTRL, 0x0 },
{ NAU8825_REG_FLL2_LOWER, 0x0 },
{ NAU8825_REG_FLL2_UPPER, 0x0 },
{ NAU8825_REG_BIAS_ADJ, 0x0 },
{ NAU8825_REG_TRIM_SETTINGS, 0x0 },
{ NAU8825_REG_ANALOG_CONTROL_1, 0x0 },
{ NAU8825_REG_ANALOG_CONTROL_2, 0x0 },
{ NAU8825_REG_ANALOG_ADC_1, 0x0011 },
{ NAU8825_REG_ANALOG_ADC_2, 0x0020 },
{ NAU8825_REG_RDAC, 0x0008 },
{ NAU8825_REG_MIC_BIAS, 0x0006 },
{ NAU8825_REG_BOOST, 0x0 },
{ NAU8825_REG_FEPGA, 0x0 },
{ NAU8825_REG_POWER_UP_CONTROL, 0x0 },
{ NAU8825_REG_CHARGE_PUMP, 0x0 },
};
/* register backup table when cross talk detection */
static struct reg_default nau8825_xtalk_baktab[] = {
{ NAU8825_REG_ADC_DGAIN_CTRL, 0x00cf },
{ NAU8825_REG_HSVOL_CTRL, 0 },
{ NAU8825_REG_DACL_CTRL, 0x00cf },
{ NAU8825_REG_DACR_CTRL, 0x02cf },
};
/* The regmap patch for Rev C */
static const struct reg_sequence nau8825_regmap_patch[] = {
{ NAU8825_REG_FLL2, 0x0000 },
{ NAU8825_REG_FLL4, 0x8010 },
{ NAU8825_REG_FLL_VCO_RSV, 0x0bc0 },
{ NAU8825_REG_INTERRUPT_MASK, 0x0800 },
{ NAU8825_REG_DACL_CTRL, 0x00cf },
{ NAU8825_REG_DACR_CTRL, 0x02cf },
{ NAU8825_REG_OPT_EFUSE_CTRL, 0x0400 },
{ NAU8825_REG_FLL2_LOWER, 0x26e9 },
{ NAU8825_REG_FLL2_UPPER, 0x0031 },
{ NAU8825_REG_ANALOG_CONTROL_2, 0x0020 },
{ NAU8825_REG_ANALOG_ADC_2, 0x0220 },
{ NAU8825_REG_MIC_BIAS, 0x0046 },
};
/**
* nau8825_sema_acquire - acquire the semaphore of nau88l25
* @nau8825: component to register the codec private data with
* @timeout: how long in jiffies to wait before failure or zero to wait
* until release
*
* Attempts to acquire the semaphore with number of jiffies. If no more
* tasks are allowed to acquire the semaphore, calling this function will
* put the task to sleep. If the semaphore is not released within the
* specified number of jiffies, this function returns.
* If the semaphore is not released within the specified number of jiffies,
* this function returns -ETIME. If the sleep is interrupted by a signal,
* this function will return -EINTR. It returns 0 if the semaphore was
* acquired successfully.
*
* Acquires the semaphore without jiffies. Try to acquire the semaphore
* atomically. Returns 0 if the semaphore has been acquired successfully
* or 1 if it cannot be acquired.
*/
static int nau8825_sema_acquire(struct nau8825 *nau8825, long timeout)
{
int ret;
if (timeout) {
ret = down_timeout(&nau8825->xtalk_sem, timeout);
if (ret < 0)
dev_warn(nau8825->dev, "Acquire semaphore timeout\n");
} else {
ret = down_trylock(&nau8825->xtalk_sem);
if (ret)
dev_warn(nau8825->dev, "Acquire semaphore fail\n");
}
return ret;
}
/**
* nau8825_sema_release - release the semaphore of nau88l25
* @nau8825: component to register the codec private data with
*
* Release the semaphore which may be called from any context and
* even by tasks which have never called down().
*/
static inline void nau8825_sema_release(struct nau8825 *nau8825)
{
up(&nau8825->xtalk_sem);
}
/**
* nau8825_sema_reset - reset the semaphore for nau88l25
* @nau8825: component to register the codec private data with
*
* Reset the counter of the semaphore. Call this function to restart
* a new round task management.
*/
static inline void nau8825_sema_reset(struct nau8825 *nau8825)
{
nau8825->xtalk_sem.count = 1;
}
/**
* nau8825_hpvol_ramp - Ramp up the headphone volume change gradually to target level.
*
* @nau8825: component to register the codec private data with
* @vol_from: the volume to start up
* @vol_to: the target volume
* @step: the volume span to move on
*
* The headphone volume is from 0dB to minimum -54dB and -1dB per step.
* If the volume changes sharp, there is a pop noise heard in headphone. We
* provide the function to ramp up the volume up or down by delaying 10ms
* per step.
*/
static void nau8825_hpvol_ramp(struct nau8825 *nau8825,
unsigned int vol_from, unsigned int vol_to, unsigned int step)
{
unsigned int value, volume, ramp_up, from, to;
if (vol_from == vol_to || step == 0) {
return;
} else if (vol_from < vol_to) {
ramp_up = true;
from = vol_from;
to = vol_to;
} else {
ramp_up = false;
from = vol_to;
to = vol_from;
}
/* only handle volume from 0dB to minimum -54dB */
if (to > NAU8825_HP_VOL_MIN)
to = NAU8825_HP_VOL_MIN;
for (volume = from; volume < to; volume += step) {
if (ramp_up)
value = volume;
else
value = to - volume + from;
regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL,
NAU8825_HPL_VOL_MASK | NAU8825_HPR_VOL_MASK,
(value << NAU8825_HPL_VOL_SFT) | value);
usleep_range(10000, 10500);
}
if (ramp_up)
value = to;
else
value = from;
regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL,
NAU8825_HPL_VOL_MASK | NAU8825_HPR_VOL_MASK,
(value << NAU8825_HPL_VOL_SFT) | value);
}
/**
* nau8825_intlog10_dec3 - Computes log10 of a value, rounding the result to 3 decimal places.
* @value: input for log10
*
* return log10(value) * 1000
*/
static u32 nau8825_intlog10_dec3(u32 value)
{
return intlog10(value) / ((1 << 24) / 1000);
}
/**
* nau8825_xtalk_sidetone - computes cross talk suppression sidetone gain.
*
* @sig_org: orignal signal level
* @sig_cros: cross talk signal level
*
* The orignal and cross talk signal vlues need to be characterized.
* Once these values have been characterized, this sidetone value
* can be converted to decibel with the equation below.
* sidetone = 20 * log (original signal level / crosstalk signal level)
*
* return cross talk sidetone gain
*/
static u32 nau8825_xtalk_sidetone(u32 sig_org, u32 sig_cros)
{
u32 gain, sidetone;
if (WARN_ON(sig_org == 0 || sig_cros == 0))
return 0;
sig_org = nau8825_intlog10_dec3(sig_org);
sig_cros = nau8825_intlog10_dec3(sig_cros);
if (sig_org >= sig_cros)
gain = (sig_org - sig_cros) * 20 + GAIN_AUGMENT;
else
gain = (sig_cros - sig_org) * 20 + GAIN_AUGMENT;
sidetone = SIDETONE_BASE - gain * 2;
sidetone /= 1000;
return sidetone;
}
static int nau8825_xtalk_baktab_index_by_reg(unsigned int reg)
{
int index;
for (index = 0; index < ARRAY_SIZE(nau8825_xtalk_baktab); index++)
if (nau8825_xtalk_baktab[index].reg == reg)
return index;
return -EINVAL;
}
static void nau8825_xtalk_backup(struct nau8825 *nau8825)
{
int i;
if (nau8825->xtalk_baktab_initialized)
return;
/* Backup some register values to backup table */
for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++)
regmap_read(nau8825->regmap, nau8825_xtalk_baktab[i].reg,
&nau8825_xtalk_baktab[i].def);
nau8825->xtalk_baktab_initialized = true;
}
static void nau8825_xtalk_restore(struct nau8825 *nau8825, bool cause_cancel)
{
int i, volume;
if (!nau8825->xtalk_baktab_initialized)
return;
/* Restore register values from backup table; When the driver restores
* the headphone volume in XTALK_DONE state, it needs recover to
* original level gradually with 3dB per step for less pop noise.
* Otherwise, the restore should do ASAP.
*/
for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++) {
if (!cause_cancel && nau8825_xtalk_baktab[i].reg ==
NAU8825_REG_HSVOL_CTRL) {
/* Ramping up the volume change to reduce pop noise */
volume = nau8825_xtalk_baktab[i].def &
NAU8825_HPR_VOL_MASK;
nau8825_hpvol_ramp(nau8825, 0, volume, 3);
continue;
}
regmap_write(nau8825->regmap, nau8825_xtalk_baktab[i].reg,
nau8825_xtalk_baktab[i].def);
}
nau8825->xtalk_baktab_initialized = false;
}
static void nau8825_xtalk_prepare_dac(struct nau8825 *nau8825)
{
/* Enable power of DAC path */
regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
NAU8825_ENABLE_DACR | NAU8825_ENABLE_DACL |
NAU8825_ENABLE_ADC | NAU8825_ENABLE_ADC_CLK |
NAU8825_ENABLE_DAC_CLK, NAU8825_ENABLE_DACR |
NAU8825_ENABLE_DACL | NAU8825_ENABLE_ADC |
NAU8825_ENABLE_ADC_CLK | NAU8825_ENABLE_DAC_CLK);
/* Prevent startup click by letting charge pump to ramp up and
* change bump enable
*/
regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN,
NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN);
/* Enable clock sync of DAC and DAC clock */
regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC,
NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN |
NAU8825_RDAC_FS_BCLK_ENB,
NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN);
/* Power up output driver with 2 stage */
regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L,
NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L);
regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L,
NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L);
/* HP outputs not shouted to ground */
regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL,
NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L, 0);
/* Enable HP boost driver */
regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
NAU8825_HP_BOOST_DIS, NAU8825_HP_BOOST_DIS);
/* Enable class G compare path to supply 1.8V or 0.9V. */
regmap_update_bits(nau8825->regmap, NAU8825_REG_CLASSG_CTRL,
NAU8825_CLASSG_LDAC_EN | NAU8825_CLASSG_RDAC_EN,
NAU8825_CLASSG_LDAC_EN | NAU8825_CLASSG_RDAC_EN);
}
static void nau8825_xtalk_prepare_adc(struct nau8825 *nau8825)
{
/* Power up left ADC and raise 5dB than Vmid for Vref */
regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2,
NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_MASK,
NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_VMID_PLUS_0_5DB);
}
static void nau8825_xtalk_clock(struct nau8825 *nau8825)
{
/* Recover FLL default value */
regmap_write(nau8825->regmap, NAU8825_REG_FLL1, 0x0);
regmap_write(nau8825->regmap, NAU8825_REG_FLL2, 0x3126);
regmap_write(nau8825->regmap, NAU8825_REG_FLL3, 0x0008);
regmap_write(nau8825->regmap, NAU8825_REG_FLL4, 0x0010);
regmap_write(nau8825->regmap, NAU8825_REG_FLL5, 0x0);
regmap_write(nau8825->regmap, NAU8825_REG_FLL6, 0x6000);
/* Enable internal VCO clock for detection signal generated */
regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6, NAU8825_DCO_EN,
NAU8825_DCO_EN);
/* Given specific clock frequency of internal clock to
* generate signal.
*/
regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
NAU8825_CLK_MCLK_SRC_MASK, 0xf);
regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1,
NAU8825_FLL_RATIO_MASK, 0x10);
}
static void nau8825_xtalk_prepare(struct nau8825 *nau8825)
{
int volume, index;
/* Backup those registers changed by cross talk detection */
nau8825_xtalk_backup(nau8825);
/* Config IIS as master to output signal by codec */
regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
NAU8825_I2S_MS_MASK | NAU8825_I2S_LRC_DIV_MASK |
NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_MASTER |
(0x2 << NAU8825_I2S_LRC_DIV_SFT) | 0x1);
/* Ramp up headphone volume to 0dB to get better performance and
* avoid pop noise in headphone.
*/
index = nau8825_xtalk_baktab_index_by_reg(NAU8825_REG_HSVOL_CTRL);
if (index != -EINVAL) {
volume = nau8825_xtalk_baktab[index].def &
NAU8825_HPR_VOL_MASK;
nau8825_hpvol_ramp(nau8825, volume, 0, 3);
}
nau8825_xtalk_clock(nau8825);
nau8825_xtalk_prepare_dac(nau8825);
nau8825_xtalk_prepare_adc(nau8825);
/* Config channel path and digital gain */
regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL,
NAU8825_DACL_CH_SEL_MASK | NAU8825_DACL_CH_VOL_MASK,
NAU8825_DACL_CH_SEL_L | 0xab);
regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL,
NAU8825_DACR_CH_SEL_MASK | NAU8825_DACR_CH_VOL_MASK,
NAU8825_DACR_CH_SEL_R | 0xab);
/* Config cross talk parameters and generate the 23Hz sine wave with
* 1/16 full scale of signal level for impedance measurement.
*/
regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL,
NAU8825_IMM_THD_MASK | NAU8825_IMM_GEN_VOL_MASK |
NAU8825_IMM_CYC_MASK | NAU8825_IMM_DAC_SRC_MASK,
(0x9 << NAU8825_IMM_THD_SFT) | NAU8825_IMM_GEN_VOL_1_16th |
NAU8825_IMM_CYC_8192 | NAU8825_IMM_DAC_SRC_SIN);
/* RMS intrruption enable */
regmap_update_bits(nau8825->regmap,
NAU8825_REG_INTERRUPT_MASK, NAU8825_IRQ_RMS_EN, 0);
/* Power up left and right DAC */
if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825)
regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 0);
else
regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
}
static void nau8825_xtalk_clean_dac(struct nau8825 *nau8825)
{
/* Disable HP boost driver */
regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
NAU8825_HP_BOOST_DIS, 0);
/* HP outputs shouted to ground */
regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL,
NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L,
NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L);
/* Power down left and right DAC */
if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825)
regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
else
regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 0);
/* Enable the TESTDAC and disable L/R HP impedance */
regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP |
NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
/* Power down output driver with 2 stage */
regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L, 0);
regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L, 0);
/* Disable clock sync of DAC and DAC clock */
regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC,
NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN, 0);
/* Disable charge pump ramp up function and change bump */
regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN, 0);
/* Disable power of DAC path */
regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
NAU8825_ENABLE_DACR | NAU8825_ENABLE_DACL |
NAU8825_ENABLE_ADC_CLK | NAU8825_ENABLE_DAC_CLK, 0);
if (!nau8825->irq)
regmap_update_bits(nau8825->regmap,
NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0);
}
static void nau8825_xtalk_clean_adc(struct nau8825 *nau8825)
{
/* Power down left ADC and restore voltage to Vmid */
regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2,
NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_MASK, 0);
}
static void nau8825_xtalk_clean(struct nau8825 *nau8825, bool cause_cancel)
{
/* Enable internal VCO needed for interruptions */
nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0);
nau8825_xtalk_clean_dac(nau8825);
nau8825_xtalk_clean_adc(nau8825);
/* Clear cross talk parameters and disable */
regmap_write(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL, 0);
/* RMS intrruption disable */
regmap_update_bits(nau8825->regmap, NAU8825_REG_INTERRUPT_MASK,
NAU8825_IRQ_RMS_EN, NAU8825_IRQ_RMS_EN);
/* Recover default value for IIS */
regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
NAU8825_I2S_MS_MASK | NAU8825_I2S_LRC_DIV_MASK |
NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_SLAVE);
/* Restore value of specific register for cross talk */
nau8825_xtalk_restore(nau8825, cause_cancel);
}
static void nau8825_xtalk_imm_start(struct nau8825 *nau8825, int vol)
{
/* Apply ADC volume for better cross talk performance */
regmap_update_bits(nau8825->regmap, NAU8825_REG_ADC_DGAIN_CTRL,
NAU8825_ADC_DIG_VOL_MASK, vol);
/* Disables JKTIP(HPL) DAC channel for right to left measurement.
* Do it before sending signal in order to erase pop noise.
*/
regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
NAU8825_BIAS_TESTDACR_EN | NAU8825_BIAS_TESTDACL_EN,
NAU8825_BIAS_TESTDACL_EN);
switch (nau8825->xtalk_state) {
case NAU8825_XTALK_HPR_R2L:
/* Enable right headphone impedance */
regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP,
NAU8825_BIAS_HPR_IMP);
break;
case NAU8825_XTALK_HPL_R2L:
/* Enable left headphone impedance */
regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP,
NAU8825_BIAS_HPL_IMP);
break;
default:
break;
}
msleep(100);
/* Impedance measurement mode enable */
regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL,
NAU8825_IMM_EN, NAU8825_IMM_EN);
}
static void nau8825_xtalk_imm_stop(struct nau8825 *nau8825)
{
/* Impedance measurement mode disable */
regmap_update_bits(nau8825->regmap,
NAU8825_REG_IMM_MODE_CTRL, NAU8825_IMM_EN, 0);
}
/* The cross talk measurement function can reduce cross talk across the
* JKTIP(HPL) and JKR1(HPR) outputs which measures the cross talk signal
* level to determine what cross talk reduction gain is. This system works by
* sending a 23Hz -24dBV sine wave into the headset output DAC and through
* the PGA. The output of the PGA is then connected to an internal current
* sense which measures the attenuated 23Hz signal and passing the output to
* an ADC which converts the measurement to a binary code. With two separated
* measurement, one for JKR1(HPR) and the other JKTIP(HPL), measurement data
* can be separated read in IMM_RMS_L for HSR and HSL after each measurement.
* Thus, the measurement function has four states to complete whole sequence.
* 1. Prepare state : Prepare the resource for detection and transfer to HPR
* IMM stat to make JKR1(HPR) impedance measure.
* 2. HPR IMM state : Read out orignal signal level of JKR1(HPR) and transfer
* to HPL IMM state to make JKTIP(HPL) impedance measure.
* 3. HPL IMM state : Read out cross talk signal level of JKTIP(HPL) and
* transfer to IMM state to determine suppression sidetone gain.
* 4. IMM state : Computes cross talk suppression sidetone gain with orignal
* and cross talk signal level. Apply this gain and then restore codec
* configuration. Then transfer to Done state for ending.
*/
static void nau8825_xtalk_measure(struct nau8825 *nau8825)
{
u32 sidetone;
switch (nau8825->xtalk_state) {
case NAU8825_XTALK_PREPARE:
/* In prepare state, set up clock, intrruption, DAC path, ADC
* path and cross talk detection parameters for preparation.
*/
nau8825_xtalk_prepare(nau8825);
msleep(280);
/* Trigger right headphone impedance detection */
nau8825->xtalk_state = NAU8825_XTALK_HPR_R2L;
nau8825_xtalk_imm_start(nau8825, 0x00d2);
break;
case NAU8825_XTALK_HPR_R2L:
/* In right headphone IMM state, read out right headphone
* impedance measure result, and then start up left side.
*/
regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L,
&nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]);
dev_dbg(nau8825->dev, "HPR_R2L imm: %x\n",
nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]);
/* Disable then re-enable IMM mode to update */
nau8825_xtalk_imm_stop(nau8825);
/* Trigger left headphone impedance detection */
nau8825->xtalk_state = NAU8825_XTALK_HPL_R2L;
nau8825_xtalk_imm_start(nau8825, 0x00ff);
break;
case NAU8825_XTALK_HPL_R2L:
/* In left headphone IMM state, read out left headphone
* impedance measure result, and delay some time to wait
* detection sine wave output finish. Then, we can calculate
* the cross talk suppresstion side tone according to the L/R
* headphone imedance.
*/
regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L,
&nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
dev_dbg(nau8825->dev, "HPL_R2L imm: %x\n",
nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
nau8825_xtalk_imm_stop(nau8825);
msleep(150);
nau8825->xtalk_state = NAU8825_XTALK_IMM;
break;
case NAU8825_XTALK_IMM:
/* In impedance measure state, the orignal and cross talk
* signal level vlues are ready. The side tone gain is deter-
* mined with these signal level. After all, restore codec
* configuration.
*/
sidetone = nau8825_xtalk_sidetone(
nau8825->imp_rms[NAU8825_XTALK_HPR_R2L],
nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
dev_dbg(nau8825->dev, "cross talk sidetone: %x\n", sidetone);
regmap_write(nau8825->regmap, NAU8825_REG_DAC_DGAIN_CTRL,
(sidetone << 8) | sidetone);
nau8825_xtalk_clean(nau8825, false);
nau8825->xtalk_state = NAU8825_XTALK_DONE;
break;
default:
break;
}
}
static void nau8825_xtalk_work(struct work_struct *work)
{
struct nau8825 *nau8825 = container_of(
work, struct nau8825, xtalk_work);
nau8825_xtalk_measure(nau8825);
/* To determine the cross talk side tone gain when reach
* the impedance measure state.
*/
if (nau8825->xtalk_state == NAU8825_XTALK_IMM)
nau8825_xtalk_measure(nau8825);
/* Delay jack report until cross talk detection process
* completed. It can avoid application to do playback
* preparation before cross talk detection is still working.
* Meanwhile, the protection of the cross talk detection
* is released.
*/
if (nau8825->xtalk_state == NAU8825_XTALK_DONE) {
snd_soc_jack_report(nau8825->jack, nau8825->xtalk_event,
nau8825->xtalk_event_mask);
nau8825_sema_release(nau8825);
nau8825->xtalk_protect = false;
}
}
static void nau8825_xtalk_cancel(struct nau8825 *nau8825)
{
/* If the crosstalk is eanbled and the process is on going,
* the driver forces to cancel the crosstalk task and
* restores the configuration to original status.
*/
if (nau8825->xtalk_enable && nau8825->xtalk_state !=
NAU8825_XTALK_DONE) {
cancel_work_sync(&nau8825->xtalk_work);
nau8825_xtalk_clean(nau8825, true);
}
/* Reset parameters for cross talk suppression function */
nau8825_sema_reset(nau8825);
nau8825->xtalk_state = NAU8825_XTALK_DONE;
nau8825->xtalk_protect = false;
}
static bool nau8825_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case NAU8825_REG_ENA_CTRL ... NAU8825_REG_FLL_VCO_RSV:
case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL:
case NAU8825_REG_INTERRUPT_MASK ... NAU8825_REG_KEYDET_CTRL:
case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL:
case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY:
case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY:
case NAU8825_REG_IMM_MODE_CTRL ... NAU8825_REG_IMM_RMS_R:
case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL:
case NAU8825_REG_MISC_CTRL:
case NAU8825_REG_I2C_DEVICE_ID ... NAU8825_REG_FLL2_UPPER:
case NAU8825_REG_BIAS_ADJ:
case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2:
case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS:
case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA:
case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_GENERAL_STATUS:
return true;
default:
return false;
}
}
static bool nau8825_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case NAU8825_REG_RESET ... NAU8825_REG_FLL_VCO_RSV:
case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL:
case NAU8825_REG_INTERRUPT_MASK:
case NAU8825_REG_INT_CLR_KEY_STATUS ... NAU8825_REG_KEYDET_CTRL:
case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL:
case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY:
case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY:
case NAU8825_REG_IMM_MODE_CTRL:
case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL:
case NAU8825_REG_MISC_CTRL:
case NAU8825_REG_FLL2_LOWER ... NAU8825_REG_FLL2_UPPER:
case NAU8825_REG_BIAS_ADJ:
case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2:
case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS:
case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA:
case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_CHARGE_PUMP:
return true;
default:
return false;
}
}
static bool nau8825_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case NAU8825_REG_RESET:
case NAU8825_REG_IRQ_STATUS:
case NAU8825_REG_INT_CLR_KEY_STATUS:
case NAU8825_REG_IMM_RMS_L:
case NAU8825_REG_IMM_RMS_R:
case NAU8825_REG_I2C_DEVICE_ID:
case NAU8825_REG_SARDOUT_RAM_STATUS:
case NAU8825_REG_CHARGE_PUMP_INPUT_READ:
case NAU8825_REG_GENERAL_STATUS:
case NAU8825_REG_BIQ_CTRL ... NAU8825_REG_BIQ_COF10:
return true;
default:
return false;
}
}
static int nau8825_fepga_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_update_bits(nau8825->regmap, NAU8825_REG_FEPGA,
NAU8825_ACDC_CTRL_MASK,
NAU8825_ACDC_VREF_MICP | NAU8825_ACDC_VREF_MICN);
regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
NAU8825_DISCHRG_EN, NAU8825_DISCHRG_EN);
msleep(40);
regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
NAU8825_DISCHRG_EN, 0);
regmap_update_bits(nau8825->regmap, NAU8825_REG_FEPGA,
NAU8825_ACDC_CTRL_MASK, 0);
break;
default:
break;
}
return 0;
}
static int nau8825_adc_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
msleep(nau8825->adc_delay);
regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
NAU8825_ENABLE_ADC, NAU8825_ENABLE_ADC);
break;
case SND_SOC_DAPM_POST_PMD:
if (!nau8825->irq)
regmap_update_bits(nau8825->regmap,
NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0);
break;
default:
return -EINVAL;
}
return 0;
}
static int nau8825_pump_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
/* Prevent startup click by letting charge pump to ramp up */
msleep(10);
regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
NAU8825_JAMNODCLOW, NAU8825_JAMNODCLOW);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
NAU8825_JAMNODCLOW, 0);
break;
default:
return -EINVAL;
}
return 0;
}
static int nau8825_output_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* Disables the TESTDAC to let DAC signal pass through. */
regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
NAU8825_BIAS_TESTDAC_EN, 0);
if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825)
regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 0);
else
regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
break;
case SND_SOC_DAPM_POST_PMD:
regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825)
regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
else
regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 0);
break;
default:
return -EINVAL;
}
return 0;
}
static int system_clock_control(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *k, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
struct regmap *regmap = nau8825->regmap;
if (SND_SOC_DAPM_EVENT_OFF(event)) {
dev_dbg(nau8825->dev, "system clock control : POWER OFF\n");
/* Set clock source to disable or internal clock before the
* playback or capture end. Codec needs clock for Jack
* detection and button press if jack inserted; otherwise,
* the clock should be closed.
*/
if (nau8825_is_jack_inserted(regmap)) {
nau8825_configure_sysclk(nau8825,
NAU8825_CLK_INTERNAL, 0);
} else {
nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0);
}
}
return 0;
}
static int nau8825_biq_coeff_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct soc_bytes_ext *params = (void *)kcontrol->private_value;
if (!component->regmap)
return -EINVAL;
regmap_raw_read(component->regmap, NAU8825_REG_BIQ_COF1,
ucontrol->value.bytes.data, params->max);
return 0;
}
static int nau8825_biq_coeff_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct soc_bytes_ext *params = (void *)kcontrol->private_value;
void *data;
if (!component->regmap)
return -EINVAL;
data = kmemdup(ucontrol->value.bytes.data,
params->max, GFP_KERNEL | GFP_DMA);
if (!data)
return -ENOMEM;
regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL,
NAU8825_BIQ_WRT_EN, 0);
regmap_raw_write(component->regmap, NAU8825_REG_BIQ_COF1,
data, params->max);
regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL,
NAU8825_BIQ_WRT_EN, NAU8825_BIQ_WRT_EN);
kfree(data);
return 0;
}
static const char * const nau8825_biq_path[] = {
"ADC", "DAC"
};
static const struct soc_enum nau8825_biq_path_enum =
SOC_ENUM_SINGLE(NAU8825_REG_BIQ_CTRL, NAU8825_BIQ_PATH_SFT,
ARRAY_SIZE(nau8825_biq_path), nau8825_biq_path);
static const char * const nau8825_adc_decimation[] = {
"32", "64", "128", "256"
};
static const struct soc_enum nau8825_adc_decimation_enum =
SOC_ENUM_SINGLE(NAU8825_REG_ADC_RATE, NAU8825_ADC_SYNC_DOWN_SFT,
ARRAY_SIZE(nau8825_adc_decimation), nau8825_adc_decimation);
static const char * const nau8825_dac_oversampl[] = {
"64", "256", "128", "", "32"
};
static const struct soc_enum nau8825_dac_oversampl_enum =
SOC_ENUM_SINGLE(NAU8825_REG_DAC_CTRL1, NAU8825_DAC_OVERSAMPLE_SFT,
ARRAY_SIZE(nau8825_dac_oversampl), nau8825_dac_oversampl);
static const DECLARE_TLV_DB_MINMAX_MUTE(adc_vol_tlv, -10300, 2400);
static const DECLARE_TLV_DB_MINMAX_MUTE(sidetone_vol_tlv, -4200, 0);
static const DECLARE_TLV_DB_MINMAX(dac_vol_tlv, -5400, 0);
static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
static const DECLARE_TLV_DB_MINMAX_MUTE(crosstalk_vol_tlv, -9600, 2400);
static const struct snd_kcontrol_new nau8825_controls[] = {
SOC_SINGLE_TLV("Mic Volume", NAU8825_REG_ADC_DGAIN_CTRL,
0, 0xff, 0, adc_vol_tlv),
SOC_DOUBLE_TLV("Headphone Bypass Volume", NAU8825_REG_ADC_DGAIN_CTRL,
12, 8, 0x0f, 0, sidetone_vol_tlv),
SOC_DOUBLE_TLV("Headphone Volume", NAU8825_REG_HSVOL_CTRL,
6, 0, 0x3f, 1, dac_vol_tlv),
SOC_SINGLE_TLV("Frontend PGA Volume", NAU8825_REG_POWER_UP_CONTROL,
8, 37, 0, fepga_gain_tlv),
SOC_DOUBLE_TLV("Headphone Crosstalk Volume", NAU8825_REG_DAC_DGAIN_CTRL,
0, 8, 0xff, 0, crosstalk_vol_tlv),
SOC_ENUM("ADC Decimation Rate", nau8825_adc_decimation_enum),
SOC_ENUM("DAC Oversampling Rate", nau8825_dac_oversampl_enum),
/* programmable biquad filter */
SOC_ENUM("BIQ Path Select", nau8825_biq_path_enum),
SND_SOC_BYTES_EXT("BIQ Coefficients", 20,
nau8825_biq_coeff_get, nau8825_biq_coeff_put),
};
/* DAC Mux 0x33[9] and 0x34[9] */
static const char * const nau8825_dac_src[] = {
"DACL", "DACR",
};
static SOC_ENUM_SINGLE_DECL(
nau8825_dacl_enum, NAU8825_REG_DACL_CTRL,
NAU8825_DACL_CH_SEL_SFT, nau8825_dac_src);
static SOC_ENUM_SINGLE_DECL(
nau8825_dacr_enum, NAU8825_REG_DACR_CTRL,
NAU8825_DACR_CH_SEL_SFT, nau8825_dac_src);
static const struct snd_kcontrol_new nau8825_dacl_mux =
SOC_DAPM_ENUM("DACL Source", nau8825_dacl_enum);
static const struct snd_kcontrol_new nau8825_dacr_mux =
SOC_DAPM_ENUM("DACR Source", nau8825_dacr_enum);
static const struct snd_soc_dapm_widget nau8825_dapm_widgets[] = {
SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, NAU8825_REG_I2S_PCM_CTRL2,
15, 1),
SND_SOC_DAPM_AIF_IN("AIFRX", "Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SUPPLY("System Clock", SND_SOC_NOPM, 0, 0,
system_clock_control, SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_INPUT("MIC"),
SND_SOC_DAPM_MICBIAS("MICBIAS", NAU8825_REG_MIC_BIAS, 8, 0),
SND_SOC_DAPM_PGA_E("Frontend PGA", NAU8825_REG_POWER_UP_CONTROL, 14, 0,
NULL, 0, nau8825_fepga_event, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_ADC_E("ADC", NULL, SND_SOC_NOPM, 0, 0,
nau8825_adc_event, SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("ADC Clock", NAU8825_REG_ENA_CTRL, 7, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC Power", NAU8825_REG_ANALOG_ADC_2, 6, 0, NULL,
0),
/* ADC for button press detection. A dapm supply widget is used to
* prevent dapm_power_widgets keeping the codec at SND_SOC_BIAS_ON
* during suspend.
*/
SND_SOC_DAPM_SUPPLY("SAR", NAU8825_REG_SAR_CTRL,
NAU8825_SAR_ADC_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("ADACL", 2, NAU8825_REG_RDAC, 12, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("ADACR", 2, NAU8825_REG_RDAC, 13, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("ADACL Clock", 3, NAU8825_REG_RDAC, 8, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("ADACR Clock", 3, NAU8825_REG_RDAC, 9, 0, NULL, 0),
SND_SOC_DAPM_DAC("DDACR", NULL, NAU8825_REG_ENA_CTRL,
NAU8825_ENABLE_DACR_SFT, 0),
SND_SOC_DAPM_DAC("DDACL", NULL, NAU8825_REG_ENA_CTRL,
NAU8825_ENABLE_DACL_SFT, 0),
SND_SOC_DAPM_SUPPLY("DDAC Clock", NAU8825_REG_ENA_CTRL, 6, 0, NULL, 0),
SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacl_mux),
SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacr_mux),
SND_SOC_DAPM_PGA_S("HP amp L", 0,
NAU8825_REG_CLASSG_CTRL, 1, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("HP amp R", 0,
NAU8825_REG_CLASSG_CTRL, 2, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8825_REG_CHARGE_PUMP, 5, 0,
nau8825_pump_event, SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA_S("Output Driver R Stage 1", 4,
NAU8825_REG_POWER_UP_CONTROL, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("Output Driver L Stage 1", 4,
NAU8825_REG_POWER_UP_CONTROL, 4, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("Output Driver R Stage 2", 5,
NAU8825_REG_POWER_UP_CONTROL, 3, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("Output Driver L Stage 2", 5,
NAU8825_REG_POWER_UP_CONTROL, 2, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("Output Driver R Stage 3", 6,
NAU8825_REG_POWER_UP_CONTROL, 1, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("Output Driver L Stage 3", 6,
NAU8825_REG_POWER_UP_CONTROL, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("Output DACL", 7,
SND_SOC_NOPM, 0, 0, nau8825_output_dac_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_S("Output DACR", 7,
SND_SOC_NOPM, 0, 0, nau8825_output_dac_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
/* HPOL/R are ungrounded by disabling 16 Ohm pull-downs on playback */
SND_SOC_DAPM_PGA_S("HPOL Pulldown", 8,
NAU8825_REG_HSD_CTRL, 0, 1, NULL, 0),
SND_SOC_DAPM_PGA_S("HPOR Pulldown", 8,
NAU8825_REG_HSD_CTRL, 1, 1, NULL, 0),
/* High current HPOL/R boost driver */
SND_SOC_DAPM_PGA_S("HP Boost Driver", 9,
NAU8825_REG_BOOST, 9, 1, NULL, 0),
/* Class G operation control*/
SND_SOC_DAPM_PGA_S("Class G", 10,
NAU8825_REG_CLASSG_CTRL, 0, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("HPOL"),
SND_SOC_DAPM_OUTPUT("HPOR"),
};
static const struct snd_soc_dapm_route nau8825_dapm_routes[] = {
{"Frontend PGA", NULL, "MIC"},
{"ADC", NULL, "Frontend PGA"},
{"ADC", NULL, "ADC Clock"},
{"ADC", NULL, "ADC Power"},
{"AIFTX", NULL, "ADC"},
{"AIFTX", NULL, "System Clock"},
{"AIFRX", NULL, "System Clock"},
{"DDACL", NULL, "AIFRX"},
{"DDACR", NULL, "AIFRX"},
{"DDACL", NULL, "DDAC Clock"},
{"DDACR", NULL, "DDAC Clock"},
{"DACL Mux", "DACL", "DDACL"},
{"DACL Mux", "DACR", "DDACR"},
{"DACR Mux", "DACL", "DDACL"},
{"DACR Mux", "DACR", "DDACR"},
{"HP amp L", NULL, "DACL Mux"},
{"HP amp R", NULL, "DACR Mux"},
{"Charge Pump", NULL, "HP amp L"},
{"Charge Pump", NULL, "HP amp R"},
{"ADACL", NULL, "Charge Pump"},
{"ADACR", NULL, "Charge Pump"},
{"ADACL Clock", NULL, "ADACL"},
{"ADACR Clock", NULL, "ADACR"},
{"Output Driver L Stage 1", NULL, "ADACL Clock"},
{"Output Driver R Stage 1", NULL, "ADACR Clock"},
{"Output Driver L Stage 2", NULL, "Output Driver L Stage 1"},
{"Output Driver R Stage 2", NULL, "Output Driver R Stage 1"},
{"Output Driver L Stage 3", NULL, "Output Driver L Stage 2"},
{"Output Driver R Stage 3", NULL, "Output Driver R Stage 2"},
{"Output DACL", NULL, "Output Driver L Stage 3"},
{"Output DACR", NULL, "Output Driver R Stage 3"},
{"HPOL Pulldown", NULL, "Output DACL"},
{"HPOR Pulldown", NULL, "Output DACR"},
{"HP Boost Driver", NULL, "HPOL Pulldown"},
{"HP Boost Driver", NULL, "HPOR Pulldown"},
{"Class G", NULL, "HP Boost Driver"},
{"HPOL", NULL, "Class G"},
{"HPOR", NULL, "Class G"},
};
static const struct nau8825_osr_attr *
nau8825_get_osr(struct nau8825 *nau8825, int stream)
{
unsigned int osr;
if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
regmap_read(nau8825->regmap,
NAU8825_REG_DAC_CTRL1, &osr);
osr &= NAU8825_DAC_OVERSAMPLE_MASK;
if (osr >= ARRAY_SIZE(osr_dac_sel))
return NULL;
return &osr_dac_sel[osr];
} else {
regmap_read(nau8825->regmap,
NAU8825_REG_ADC_RATE, &osr);
osr &= NAU8825_ADC_SYNC_DOWN_MASK;
if (osr >= ARRAY_SIZE(osr_adc_sel))
return NULL;
return &osr_adc_sel[osr];
}
}
static int nau8825_dai_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
const struct nau8825_osr_attr *osr;
osr = nau8825_get_osr(nau8825, substream->stream);
if (!osr || !osr->osr)
return -EINVAL;
return snd_pcm_hw_constraint_minmax(substream->runtime,
SNDRV_PCM_HW_PARAM_RATE,
0, CLK_DA_AD_MAX / osr->osr);
}
static int nau8825_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
unsigned int val_len = 0, ctrl_val, bclk_fs, bclk_div;
const struct nau8825_osr_attr *osr;
int err = -EINVAL;
nau8825_sema_acquire(nau8825, 3 * HZ);
/* CLK_DAC or CLK_ADC = OSR * FS
* DAC or ADC clock frequency is defined as Over Sampling Rate (OSR)
* multiplied by the audio sample rate (Fs). Note that the OSR and Fs
* values must be selected such that the maximum frequency is less
* than 6.144 MHz.
*/
osr = nau8825_get_osr(nau8825, substream->stream);
if (!osr || !osr->osr)
goto error;
if (params_rate(params) * osr->osr > CLK_DA_AD_MAX)
goto error;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
NAU8825_CLK_DAC_SRC_MASK,
osr->clk_src << NAU8825_CLK_DAC_SRC_SFT);
else
regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
NAU8825_CLK_ADC_SRC_MASK,
osr->clk_src << NAU8825_CLK_ADC_SRC_SFT);
/* make BCLK and LRC divde configuration if the codec as master. */
regmap_read(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, &ctrl_val);
if (ctrl_val & NAU8825_I2S_MS_MASTER) {
/* get the bclk and fs ratio */
bclk_fs = snd_soc_params_to_bclk(params) / params_rate(params);
if (bclk_fs <= 32)
bclk_div = 2;
else if (bclk_fs <= 64)
bclk_div = 1;
else if (bclk_fs <= 128)
bclk_div = 0;
else
goto error;
regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
NAU8825_I2S_LRC_DIV_MASK | NAU8825_I2S_BLK_DIV_MASK,
((bclk_div + 1) << NAU8825_I2S_LRC_DIV_SFT) | bclk_div);
}
switch (params_width(params)) {
case 16:
val_len |= NAU8825_I2S_DL_16;
break;
case 20:
val_len |= NAU8825_I2S_DL_20;
break;
case 24:
val_len |= NAU8825_I2S_DL_24;
break;
case 32:
val_len |= NAU8825_I2S_DL_32;
break;
default:
goto error;
}
regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1,
NAU8825_I2S_DL_MASK, val_len);
err = 0;
error:
/* Release the semaphore. */
nau8825_sema_release(nau8825);
return err;
}
static int nau8825_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
unsigned int ctrl1_val = 0, ctrl2_val = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
ctrl2_val |= NAU8825_I2S_MS_MASTER;
break;
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
ctrl1_val |= NAU8825_I2S_BP_INV;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
ctrl1_val |= NAU8825_I2S_DF_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
ctrl1_val |= NAU8825_I2S_DF_LEFT;
break;
case SND_SOC_DAIFMT_RIGHT_J:
ctrl1_val |= NAU8825_I2S_DF_RIGTH;
break;
case SND_SOC_DAIFMT_DSP_A:
ctrl1_val |= NAU8825_I2S_DF_PCM_AB;
break;
case SND_SOC_DAIFMT_DSP_B:
ctrl1_val |= NAU8825_I2S_DF_PCM_AB;
ctrl1_val |= NAU8825_I2S_PCMB_EN;
break;
default:
return -EINVAL;
}
nau8825_sema_acquire(nau8825, 3 * HZ);
regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1,
NAU8825_I2S_DL_MASK | NAU8825_I2S_DF_MASK |
NAU8825_I2S_BP_MASK | NAU8825_I2S_PCMB_MASK,
ctrl1_val);
regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
NAU8825_I2S_MS_MASK, ctrl2_val);
/* Release the semaphore. */
nau8825_sema_release(nau8825);
return 0;
}
/**
* nau8825_set_tdm_slot - configure DAI TDM.
* @dai: DAI
* @tx_mask: bitmask representing active TX slots.
* @rx_mask: bitmask representing active RX slots.
* @slots: Number of slots in use.
* @slot_width: Width in bits for each slot.
*
* Configures a DAI for TDM operation. Support TDM 4/8 slots.
* The limitation is DAC and ADC need shift 4 slots at 8 slots mode.
*/
static int nau8825_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
unsigned int ctrl_val = 0, ctrl_offset = 0, value = 0, dac_s, adc_s;
if (slots != 4 && slots != 8) {
dev_err(nau8825->dev, "Only support 4 or 8 slots!\n");
return -EINVAL;
}
/* The driver is limited to 1-channel for ADC, and 2-channel for DAC on TDM mode */
if (hweight_long((unsigned long) tx_mask) != 1 ||
hweight_long((unsigned long) rx_mask) != 2) {
dev_err(nau8825->dev,
"The limitation is 1-channel for ADC, and 2-channel for DAC on TDM mode.\n");
return -EINVAL;
}
if (((tx_mask & 0xf) && (tx_mask & 0xf0)) ||
((rx_mask & 0xf) && (rx_mask & 0xf0)) ||
((tx_mask & 0xf) && (rx_mask & 0xf0)) ||
((rx_mask & 0xf) && (tx_mask & 0xf0))) {
dev_err(nau8825->dev,
"Slot assignment of DAC and ADC need to set same interval.\n");
return -EINVAL;
}
/* The offset of fixed 4 slots for 8 slots support */
if (rx_mask & 0xf0) {
regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
NAU8825_I2S_PCM_TS_EN_MASK, NAU8825_I2S_PCM_TS_EN);
regmap_read(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1, &value);
ctrl_val |= NAU8825_TDM_OFFSET_EN;
ctrl_offset = 4 * slot_width;
if (!(value & NAU8825_I2S_PCMB_MASK))
ctrl_offset += 1;
dac_s = (rx_mask & 0xf0) >> 4;
adc_s = fls((tx_mask & 0xf0) >> 4);
} else {
dac_s = rx_mask & 0xf;
adc_s = fls(tx_mask & 0xf);
}
ctrl_val |= NAU8825_TDM_MODE;
switch (dac_s) {
case 0x3:
ctrl_val |= 1 << NAU8825_TDM_DACR_RX_SFT;
break;
case 0x5:
ctrl_val |= 2 << NAU8825_TDM_DACR_RX_SFT;
break;
case 0x6:
ctrl_val |= 1 << NAU8825_TDM_DACL_RX_SFT;
ctrl_val |= 2 << NAU8825_TDM_DACR_RX_SFT;
break;
case 0x9:
ctrl_val |= 3 << NAU8825_TDM_DACR_RX_SFT;
break;
case 0xa:
ctrl_val |= 1 << NAU8825_TDM_DACL_RX_SFT;
ctrl_val |= 3 << NAU8825_TDM_DACR_RX_SFT;
break;
case 0xc:
ctrl_val |= 2 << NAU8825_TDM_DACL_RX_SFT;
ctrl_val |= 3 << NAU8825_TDM_DACR_RX_SFT;
break;
default:
return -EINVAL;
}
ctrl_val |= adc_s - 1;
regmap_update_bits(nau8825->regmap, NAU8825_REG_TDM_CTRL,
NAU8825_TDM_MODE | NAU8825_TDM_OFFSET_EN |
NAU8825_TDM_DACL_RX_MASK | NAU8825_TDM_DACR_RX_MASK |
NAU8825_TDM_TX_MASK, ctrl_val);
regmap_update_bits(nau8825->regmap, NAU8825_REG_LEFT_TIME_SLOT,
NAU8825_TSLOT_L0_MASK, ctrl_offset);
return 0;
}
static const struct snd_soc_dai_ops nau8825_dai_ops = {
.startup = nau8825_dai_startup,
.hw_params = nau8825_hw_params,
.set_fmt = nau8825_set_dai_fmt,
.set_tdm_slot = nau8825_set_tdm_slot,
};
#define NAU8825_RATES SNDRV_PCM_RATE_8000_192000
#define NAU8825_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
| SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver nau8825_dai = {
.name = "nau8825-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = NAU8825_RATES,
.formats = NAU8825_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2, /* Only 1 channel of data */
.rates = NAU8825_RATES,
.formats = NAU8825_FORMATS,
},
.ops = &nau8825_dai_ops,
};
/**
* nau8825_enable_jack_detect - Specify a jack for event reporting
*
* @component: component to register the jack with
* @jack: jack to use to report headset and button events on
*
* After this function has been called the headset insert/remove and button
* events will be routed to the given jack. Jack can be null to stop
* reporting.
*/
int nau8825_enable_jack_detect(struct snd_soc_component *component,
struct snd_soc_jack *jack)
{
struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
struct regmap *regmap = nau8825->regmap;
nau8825->jack = jack;
if (!nau8825->jack) {
regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL,
NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R |
NAU8825_SPKR_DWN1L, 0);
return 0;
}
/* Ground HP Outputs[1:0], needed for headset auto detection
* Enable Automatic Mic/Gnd switching reading on insert interrupt[6]
*/
regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL,
NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L,
NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L);
return 0;
}
EXPORT_SYMBOL_GPL(nau8825_enable_jack_detect);
static bool nau8825_is_jack_inserted(struct regmap *regmap)
{
bool active_high, is_high;
int status, jkdet;
regmap_read(regmap, NAU8825_REG_JACK_DET_CTRL, &jkdet);
active_high = jkdet & NAU8825_JACK_POLARITY;
regmap_read(regmap, NAU8825_REG_I2C_DEVICE_ID, &status);
is_high = status & NAU8825_GPIO2JD1;
/* return jack connection status according to jack insertion logic
* active high or active low.
*/
return active_high == is_high;
}
static void nau8825_restart_jack_detection(struct regmap *regmap)
{
/* this will restart the entire jack detection process including MIC/GND
* switching and create interrupts. We have to go from 0 to 1 and back
* to 0 to restart.
*/
regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
NAU8825_JACK_DET_RESTART, NAU8825_JACK_DET_RESTART);
regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
NAU8825_JACK_DET_RESTART, 0);
}
static void nau8825_int_status_clear_all(struct regmap *regmap)
{
int active_irq, clear_irq, i;
/* Reset the intrruption status from rightmost bit if the corres-
* ponding irq event occurs.
*/
regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq);
for (i = 0; i < NAU8825_REG_DATA_LEN; i++) {
clear_irq = (0x1 << i);
if (active_irq & clear_irq)
regmap_write(regmap,
NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq);
}
}
static void nau8825_eject_jack(struct nau8825 *nau8825)
{
struct snd_soc_dapm_context *dapm = nau8825->dapm;
struct regmap *regmap = nau8825->regmap;
/* Force to cancel the cross talk detection process */
nau8825_xtalk_cancel(nau8825);
snd_soc_dapm_disable_pin(dapm, "SAR");
snd_soc_dapm_disable_pin(dapm, "MICBIAS");
/* Detach 2kOhm Resistors from MICBIAS to MICGND1/2 */
regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0);
/* ground HPL/HPR, MICGRND1/2 */
regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 0xf, 0xf);
snd_soc_dapm_sync(dapm);
/* Clear all interruption status */
nau8825_int_status_clear_all(regmap);
/* Enable the insertion interruption, disable the ejection inter-
* ruption, and then bypass de-bounce circuit.
*/
regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL,
NAU8825_IRQ_EJECT_DIS | NAU8825_IRQ_INSERT_DIS,
NAU8825_IRQ_EJECT_DIS);
regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_EJECT_EN |
NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_INSERT_EN,
NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_EJECT_EN |
NAU8825_IRQ_HEADSET_COMPLETE_EN);
regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
NAU8825_JACK_DET_DB_BYPASS, NAU8825_JACK_DET_DB_BYPASS);
/* Disable ADC needed for interruptions at audo mode */
regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL,
NAU8825_ENABLE_ADC, 0);
/* Close clock for jack type detection at manual mode */
nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0);
}
/* Enable audo mode interruptions with internal clock. */
static void nau8825_setup_auto_irq(struct nau8825 *nau8825)
{
struct regmap *regmap = nau8825->regmap;
/* Enable HSD function */
regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL,
NAU8825_HSD_AUTO_MODE, NAU8825_HSD_AUTO_MODE);
/* Enable headset jack type detection complete interruption and
* jack ejection interruption.
*/
regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_EJECT_EN, 0);
/* Enable internal VCO needed for interruptions */
nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0);
/* Raise up the internal clock for jack detection */
regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
NAU8825_CLK_MCLK_SRC_MASK, 0);
/* Enable ADC needed for interruptions */
regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL,
NAU8825_ENABLE_ADC, NAU8825_ENABLE_ADC);
/* Chip needs one FSCLK cycle in order to generate interruptions,
* as we cannot guarantee one will be provided by the system. Turning
* master mode on then off enables us to generate that FSCLK cycle
* with a minimum of contention on the clock bus.
*/
regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2,
NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_MASTER);
regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2,
NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_SLAVE);
/* Not bypass de-bounce circuit */
regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
NAU8825_JACK_DET_DB_BYPASS, 0);
/* Unmask all interruptions */
regmap_write(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL, 0);
/* Restart the jack detection process at auto mode */
nau8825_restart_jack_detection(regmap);
}
static int nau8825_button_decode(int value)
{
int buttons = 0;
/* The chip supports up to 8 buttons, but ALSA defines only 6 buttons */
if (value & BIT(0))
buttons |= SND_JACK_BTN_0;
if (value & BIT(1))
buttons |= SND_JACK_BTN_1;
if (value & BIT(2))
buttons |= SND_JACK_BTN_2;
if (value & BIT(3))
buttons |= SND_JACK_BTN_3;
if (value & BIT(4))
buttons |= SND_JACK_BTN_4;
if (value & BIT(5))
buttons |= SND_JACK_BTN_5;
return buttons;
}
static int nau8825_high_imped_detection(struct nau8825 *nau8825)
{
struct regmap *regmap = nau8825->regmap;
struct snd_soc_dapm_context *dapm = nau8825->dapm;
unsigned int adc_mg1, adc_mg2;
/* Initial phase */
regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL,
NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2 | NAU8825_SPKR_DWN1R |
NAU8825_SPKR_DWN1L, NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2);
regmap_update_bits(regmap, NAU8825_REG_ANALOG_CONTROL_1,
NAU8825_TESTDACIN_MASK, NAU8825_TESTDACIN_GND);
regmap_write(regmap, NAU8825_REG_TRIM_SETTINGS, 0x6);
regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
NAU8825_MICBIAS_LOWNOISE_MASK | NAU8825_MICBIAS_VOLTAGE_MASK,
NAU8825_MICBIAS_LOWNOISE_EN);
regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
NAU8825_SAR_INPUT_MASK | NAU8825_SAR_TRACKING_GAIN_MASK |
NAU8825_SAR_HV_SEL_MASK | NAU8825_SAR_RES_SEL_MASK |
NAU8825_SAR_COMPARE_TIME_MASK | NAU8825_SAR_SAMPLING_TIME_MASK,
NAU8825_SAR_HV_SEL_VDDMIC | NAU8825_SAR_RES_SEL_70K);
snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
snd_soc_dapm_force_enable_pin(dapm, "SAR");
snd_soc_dapm_sync(dapm);
/* Configure settings for first reading of SARADC */
regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL,
NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2 | NAU8825_SPKR_DWN1R |
NAU8825_SPKR_DWN1L, NAU8825_SPKR_ENGND2);
regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
NAU8825_MICBIAS_JKR2);
regmap_read(regmap, NAU8825_REG_SARDOUT_RAM_STATUS, &adc_mg1);
/* Configure settings for second reading of SARADC */
regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0);
regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL,
NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2 | NAU8825_SPKR_DWN1R |
NAU8825_SPKR_DWN1L, NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2 |
NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L);
regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL,
NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2 | NAU8825_SPKR_DWN1R |
NAU8825_SPKR_DWN1L, NAU8825_SPKR_ENGND1);
regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
NAU8825_MICBIAS_JKSLV);
regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
NAU8825_SAR_INPUT_MASK, NAU8825_SAR_INPUT_JKSLV);
regmap_read(regmap, NAU8825_REG_SARDOUT_RAM_STATUS, &adc_mg2);
/* Disable phase */
snd_soc_dapm_disable_pin(dapm, "SAR");
snd_soc_dapm_disable_pin(dapm, "MICBIAS");
snd_soc_dapm_sync(dapm);
regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_LOWNOISE_MASK |
NAU8825_MICBIAS_VOLTAGE_MASK, nau8825->micbias_voltage);
regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL,
NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2 | NAU8825_SPKR_DWN1R |
NAU8825_SPKR_DWN1L, NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2 |
NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L);
regmap_update_bits(regmap, NAU8825_REG_ANALOG_CONTROL_1,
NAU8825_TESTDACIN_MASK, NAU8825_TESTDACIN_GND);
regmap_write(regmap, NAU8825_REG_TRIM_SETTINGS, 0);
regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
NAU8825_SAR_TRACKING_GAIN_MASK | NAU8825_SAR_HV_SEL_MASK,
nau8825->sar_voltage << NAU8825_SAR_TRACKING_GAIN_SFT);
regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
NAU8825_SAR_COMPARE_TIME_MASK | NAU8825_SAR_SAMPLING_TIME_MASK,
(nau8825->sar_compare_time << NAU8825_SAR_COMPARE_TIME_SFT) |
(nau8825->sar_sampling_time << NAU8825_SAR_SAMPLING_TIME_SFT));
dev_dbg(nau8825->dev, "adc_mg1:%x, adc_mg2:%x\n", adc_mg1, adc_mg2);
/* Confirmation phase */
if (adc_mg1 > adc_mg2) {
dev_dbg(nau8825->dev, "OMTP (micgnd1) mic connected\n");
/* Unground MICGND1 */
regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL,
NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2,
NAU8825_SPKR_ENGND2);
/* Attach 2kOhm Resistor from MICBIAS to MICGND1 */
regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
NAU8825_MICBIAS_JKR2);
/* Attach SARADC to MICGND1 */
regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
NAU8825_SAR_INPUT_MASK,
NAU8825_SAR_INPUT_JKR2);
} else if (adc_mg1 < adc_mg2) {
dev_dbg(nau8825->dev, "CTIA (micgnd2) mic connected\n");
/* Unground MICGND2 */
regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL,
NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2,
NAU8825_SPKR_ENGND1);
/* Attach 2kOhm Resistor from MICBIAS to MICGND2 */
regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
NAU8825_MICBIAS_JKSLV);
/* Attach SARADC to MICGND2 */
regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
NAU8825_SAR_INPUT_MASK,
NAU8825_SAR_INPUT_JKSLV);
} else {
dev_err(nau8825->dev, "Jack broken.\n");
return -EINVAL;
}
return 0;
}
static int nau8825_jack_insert(struct nau8825 *nau8825)
{
struct regmap *regmap = nau8825->regmap;
struct snd_soc_dapm_context *dapm = nau8825->dapm;
int jack_status_reg, mic_detected;
int type = 0;
regmap_read(regmap, NAU8825_REG_GENERAL_STATUS, &jack_status_reg);
mic_detected = (jack_status_reg >> 10) & 3;
/* The JKSLV and JKR2 all detected in high impedance headset */
if (mic_detected == 0x3)
nau8825->high_imped = true;
else
nau8825->high_imped = false;
switch (mic_detected) {
case 0:
/* no mic */
type = SND_JACK_HEADPHONE;
break;
case 1:
dev_dbg(nau8825->dev, "OMTP (micgnd1) mic connected\n");
type = SND_JACK_HEADSET;
/* Unground MICGND1 */
regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2,
1 << 2);
/* Attach 2kOhm Resistor from MICBIAS to MICGND1 */
regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
NAU8825_MICBIAS_JKR2);
/* Attach SARADC to MICGND1 */
regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
NAU8825_SAR_INPUT_MASK,
NAU8825_SAR_INPUT_JKR2);
snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
snd_soc_dapm_force_enable_pin(dapm, "SAR");
snd_soc_dapm_sync(dapm);
break;
case 2:
dev_dbg(nau8825->dev, "CTIA (micgnd2) mic connected\n");
type = SND_JACK_HEADSET;
/* Unground MICGND2 */
regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2,
2 << 2);
/* Attach 2kOhm Resistor from MICBIAS to MICGND2 */
regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
NAU8825_MICBIAS_JKSLV);
/* Attach SARADC to MICGND2 */
regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
NAU8825_SAR_INPUT_MASK,
NAU8825_SAR_INPUT_JKSLV);
snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
snd_soc_dapm_force_enable_pin(dapm, "SAR");
snd_soc_dapm_sync(dapm);
break;
case 3:
/* Detection failure case */
dev_warn(nau8825->dev,
"Detection failure. Try the manually mechanism for jack type checking.\n");
if (!nau8825_high_imped_detection(nau8825)) {
type = SND_JACK_HEADSET;
snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
snd_soc_dapm_force_enable_pin(dapm, "SAR");
snd_soc_dapm_sync(dapm);
} else
type = SND_JACK_HEADPHONE;
break;
}
/* Update to the default divider of internal clock for power saving */
regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
NAU8825_CLK_MCLK_SRC_MASK, 0xf);
/* Disable HSD function */
regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, NAU8825_HSD_AUTO_MODE, 0);
/* Leaving HPOL/R grounded after jack insert by default. They will be
* ungrounded as part of the widget power up sequence at the beginning
* of playback to reduce pop.
*/
return type;
}
#define NAU8825_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \
SND_JACK_BTN_2 | SND_JACK_BTN_3)
static irqreturn_t nau8825_interrupt(int irq, void *data)
{
struct nau8825 *nau8825 = (struct nau8825 *)data;
struct regmap *regmap = nau8825->regmap;
int active_irq, clear_irq = 0, event = 0, event_mask = 0;
if (regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq)) {
dev_err(nau8825->dev, "failed to read irq status\n");
return IRQ_NONE;
}
if ((active_irq & NAU8825_JACK_EJECTION_IRQ_MASK) ==
NAU8825_JACK_EJECTION_DETECTED) {
nau8825_eject_jack(nau8825);
event_mask |= SND_JACK_HEADSET;
clear_irq = NAU8825_JACK_EJECTION_IRQ_MASK;
} else if (active_irq & NAU8825_KEY_SHORT_PRESS_IRQ) {
int key_status;
regmap_read(regmap, NAU8825_REG_INT_CLR_KEY_STATUS,
&key_status);
/* upper 8 bits of the register are for short pressed keys,
* lower 8 bits - for long pressed buttons
*/
nau8825->button_pressed = nau8825_button_decode(
key_status >> 8);
event |= nau8825->button_pressed;
event_mask |= NAU8825_BUTTONS;
clear_irq = NAU8825_KEY_SHORT_PRESS_IRQ;
} else if (active_irq & NAU8825_KEY_RELEASE_IRQ) {
event_mask = NAU8825_BUTTONS;
clear_irq = NAU8825_KEY_RELEASE_IRQ;
} else if (active_irq & NAU8825_HEADSET_COMPLETION_IRQ) {
if (nau8825_is_jack_inserted(regmap)) {
event |= nau8825_jack_insert(nau8825);
if (nau8825->xtalk_enable && !nau8825->high_imped) {
/* Apply the cross talk suppression in the
* headset without high impedance.
*/
if (!nau8825->xtalk_protect) {
/* Raise protection for cross talk de-
* tection if no protection before.
* The driver has to cancel the pro-
* cess and restore changes if process
* is ongoing when ejection.
*/
int ret;
nau8825->xtalk_protect = true;
ret = nau8825_sema_acquire(nau8825, 0);
if (ret)
nau8825->xtalk_protect = false;
}
/* Startup cross talk detection process */
if (nau8825->xtalk_protect) {
nau8825->xtalk_state =
NAU8825_XTALK_PREPARE;
schedule_work(&nau8825->xtalk_work);
}
} else {
/* The cross talk suppression shouldn't apply
* in the headset with high impedance. Thus,
* relieve the protection raised before.
*/
if (nau8825->xtalk_protect) {
nau8825_sema_release(nau8825);
nau8825->xtalk_protect = false;
}
}
} else {
dev_warn(nau8825->dev, "Headset completion IRQ fired but no headset connected\n");
nau8825_eject_jack(nau8825);
}
event_mask |= SND_JACK_HEADSET;
clear_irq = NAU8825_HEADSET_COMPLETION_IRQ;
/* Record the interruption report event for driver to report
* the event later. The jack report will delay until cross
* talk detection process is done.
*/
if (nau8825->xtalk_state == NAU8825_XTALK_PREPARE) {
nau8825->xtalk_event = event;
nau8825->xtalk_event_mask = event_mask;
}
} else if (active_irq & NAU8825_IMPEDANCE_MEAS_IRQ) {
/* crosstalk detection enable and process on going */
if (nau8825->xtalk_enable && nau8825->xtalk_protect)
schedule_work(&nau8825->xtalk_work);
clear_irq = NAU8825_IMPEDANCE_MEAS_IRQ;
} else if ((active_irq & NAU8825_JACK_INSERTION_IRQ_MASK) ==
NAU8825_JACK_INSERTION_DETECTED) {
/* One more step to check GPIO status directly. Thus, the
* driver can confirm the real insertion interruption because
* the intrruption at manual mode has bypassed debounce
* circuit which can get rid of unstable status.
*/
if (nau8825_is_jack_inserted(regmap)) {
/* Turn off insertion interruption at manual mode */
regmap_update_bits(regmap,
NAU8825_REG_INTERRUPT_DIS_CTRL,
NAU8825_IRQ_INSERT_DIS,
NAU8825_IRQ_INSERT_DIS);
regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
NAU8825_IRQ_INSERT_EN, NAU8825_IRQ_INSERT_EN);
/* Enable interruption for jack type detection at audo
* mode which can detect microphone and jack type.
*/
nau8825_setup_auto_irq(nau8825);
}
}
if (!clear_irq)
clear_irq = active_irq;
/* clears the rightmost interruption */
regmap_write(regmap, NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq);
/* Delay jack report until cross talk detection is done. It can avoid
* application to do playback preparation when cross talk detection
* process is still working. Otherwise, the resource like clock and
* power will be issued by them at the same time and conflict happens.
*/
if (event_mask && nau8825->xtalk_state == NAU8825_XTALK_DONE)
snd_soc_jack_report(nau8825->jack, event, event_mask);
return IRQ_HANDLED;
}
static void nau8825_setup_buttons(struct nau8825 *nau8825)
{
struct regmap *regmap = nau8825->regmap;
regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
NAU8825_SAR_TRACKING_GAIN_MASK,
nau8825->sar_voltage << NAU8825_SAR_TRACKING_GAIN_SFT);
regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
NAU8825_SAR_COMPARE_TIME_MASK,
nau8825->sar_compare_time << NAU8825_SAR_COMPARE_TIME_SFT);
regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
NAU8825_SAR_SAMPLING_TIME_MASK,
nau8825->sar_sampling_time << NAU8825_SAR_SAMPLING_TIME_SFT);
regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
NAU8825_KEYDET_LEVELS_NR_MASK,
(nau8825->sar_threshold_num - 1) << NAU8825_KEYDET_LEVELS_NR_SFT);
regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
NAU8825_KEYDET_HYSTERESIS_MASK,
nau8825->sar_hysteresis << NAU8825_KEYDET_HYSTERESIS_SFT);
regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
NAU8825_KEYDET_SHORTKEY_DEBOUNCE_MASK,
nau8825->key_debounce << NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT);
regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_1,
(nau8825->sar_threshold[0] << 8) | nau8825->sar_threshold[1]);
regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_2,
(nau8825->sar_threshold[2] << 8) | nau8825->sar_threshold[3]);
regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_3,
(nau8825->sar_threshold[4] << 8) | nau8825->sar_threshold[5]);
regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_4,
(nau8825->sar_threshold[6] << 8) | nau8825->sar_threshold[7]);
/* Enable short press and release interruptions */
regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
NAU8825_IRQ_KEY_SHORT_PRESS_EN | NAU8825_IRQ_KEY_RELEASE_EN,
0);
}
static void nau8825_init_regs(struct nau8825 *nau8825)
{
struct regmap *regmap = nau8825->regmap;
/* Latch IIC LSB value */
regmap_write(regmap, NAU8825_REG_IIC_ADDR_SET, 0x0001);
/* Enable Bias/Vmid */
regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
NAU8825_BIAS_VMID, NAU8825_BIAS_VMID);
regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
NAU8825_GLOBAL_BIAS_EN, NAU8825_GLOBAL_BIAS_EN);
/* VMID Tieoff */
regmap_update_bits(regmap, NAU8825_REG_BIAS_ADJ,
NAU8825_BIAS_VMID_SEL_MASK,
nau8825->vref_impedance << NAU8825_BIAS_VMID_SEL_SFT);
/* Disable Boost Driver, Automatic Short circuit protection enable */
regmap_update_bits(regmap, NAU8825_REG_BOOST,
NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS |
NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN,
NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS |
NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN);
regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
NAU8825_JKDET_OUTPUT_EN,
nau8825->jkdet_enable ? 0 : NAU8825_JKDET_OUTPUT_EN);
regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
NAU8825_JKDET_PULL_EN,
nau8825->jkdet_pull_enable ? 0 : NAU8825_JKDET_PULL_EN);
regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
NAU8825_JKDET_PULL_UP,
nau8825->jkdet_pull_up ? NAU8825_JKDET_PULL_UP : 0);
regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
NAU8825_JACK_POLARITY,
/* jkdet_polarity - 1 is for active-low */
nau8825->jkdet_polarity ? 0 : NAU8825_JACK_POLARITY);
regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
NAU8825_JACK_INSERT_DEBOUNCE_MASK,
nau8825->jack_insert_debounce << NAU8825_JACK_INSERT_DEBOUNCE_SFT);
regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
NAU8825_JACK_EJECT_DEBOUNCE_MASK,
nau8825->jack_eject_debounce << NAU8825_JACK_EJECT_DEBOUNCE_SFT);
/* Pull up IRQ pin */
regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
NAU8825_IRQ_PIN_PULLUP | NAU8825_IRQ_PIN_PULL_EN,
NAU8825_IRQ_PIN_PULLUP | NAU8825_IRQ_PIN_PULL_EN);
/* Mask unneeded IRQs: 1 - disable, 0 - enable */
regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 0x7ff, 0x7ff);
regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
NAU8825_MICBIAS_VOLTAGE_MASK, nau8825->micbias_voltage);
if (nau8825->sar_threshold_num)
nau8825_setup_buttons(nau8825);
/* Default oversampling/decimations settings are unusable
* (audible hiss). Set it to something better.
*/
regmap_update_bits(regmap, NAU8825_REG_ADC_RATE,
NAU8825_ADC_SYNC_DOWN_MASK | NAU8825_ADC_SINC4_EN,
NAU8825_ADC_SYNC_DOWN_64);
regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1,
NAU8825_DAC_OVERSAMPLE_MASK, NAU8825_DAC_OVERSAMPLE_64);
/* Disable DACR/L power */
if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825)
regmap_update_bits(regmap, NAU8825_REG_CHARGE_PUMP,
NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
/* Enable TESTDAC. This sets the analog DAC inputs to a '0' input
* signal to avoid any glitches due to power up transients in both
* the analog and digital DAC circuit.
*/
regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
/* CICCLP off */
regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1,
NAU8825_DAC_CLIP_OFF, NAU8825_DAC_CLIP_OFF);
/* Class AB bias current to 2x, DAC Capacitor enable MSB/LSB */
regmap_update_bits(regmap, NAU8825_REG_ANALOG_CONTROL_2,
NAU8825_HP_NON_CLASSG_CURRENT_2xADJ |
NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB,
NAU8825_HP_NON_CLASSG_CURRENT_2xADJ |
NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB);
/* Class G timer 64ms */
regmap_update_bits(regmap, NAU8825_REG_CLASSG_CTRL,
NAU8825_CLASSG_TIMER_MASK,
0x20 << NAU8825_CLASSG_TIMER_SFT);
/* DAC clock delay 2ns, VREF */
regmap_update_bits(regmap, NAU8825_REG_RDAC,
NAU8825_RDAC_CLK_DELAY_MASK | NAU8825_RDAC_VREF_MASK,
(0x2 << NAU8825_RDAC_CLK_DELAY_SFT) |
(0x3 << NAU8825_RDAC_VREF_SFT));
/* Config L/R channel */
regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL,
NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_L);
regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL,
NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_R);
/* Disable short Frame Sync detection logic */
regmap_update_bits(regmap, NAU8825_REG_LEFT_TIME_SLOT,
NAU8825_DIS_FS_SHORT_DET, NAU8825_DIS_FS_SHORT_DET);
/* ADCDAT IO drive strength control */
regmap_update_bits(regmap, NAU8825_REG_CHARGE_PUMP,
NAU8825_ADCOUT_DS_MASK,
nau8825->adcout_ds << NAU8825_ADCOUT_DS_SFT);
}
static const struct regmap_config nau8825_regmap_config = {
.val_bits = NAU8825_REG_DATA_LEN,
.reg_bits = NAU8825_REG_ADDR_LEN,
.max_register = NAU8825_REG_MAX,
.readable_reg = nau8825_readable_reg,
.writeable_reg = nau8825_writeable_reg,
.volatile_reg = nau8825_volatile_reg,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = nau8825_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(nau8825_reg_defaults),
};
static int nau8825_component_probe(struct snd_soc_component *component)
{
struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
nau8825->dapm = dapm;
return 0;
}
static void nau8825_component_remove(struct snd_soc_component *component)
{
struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
/* Cancel and reset cross tak suppresstion detection funciton */
nau8825_xtalk_cancel(nau8825);
}
/**
* nau8825_calc_fll_param - Calculate FLL parameters.
* @fll_in: external clock provided to codec.
* @fs: sampling rate.
* @fll_param: Pointer to structure of FLL parameters.
*
* Calculate FLL parameters to configure codec.
*
* Returns 0 for success or negative error code.
*/
static int nau8825_calc_fll_param(unsigned int fll_in, unsigned int fs,
struct nau8825_fll *fll_param)
{
u64 fvco, fvco_max;
unsigned int fref, i, fvco_sel;
/* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing
* freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
* FREF = freq_in / NAU8825_FLL_REF_DIV_MASK
*/
for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
fref = fll_in / fll_pre_scalar[i].param;
if (fref <= NAU_FREF_MAX)
break;
}
if (i == ARRAY_SIZE(fll_pre_scalar))
return -EINVAL;
fll_param->clk_ref_div = fll_pre_scalar[i].val;
/* Choose the FLL ratio based on FREF */
for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
if (fref >= fll_ratio[i].param)
break;
}
if (i == ARRAY_SIZE(fll_ratio))
return -EINVAL;
fll_param->ratio = fll_ratio[i].val;
/* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.
* FDCO must be within the 90MHz - 124MHz or the FFL cannot be
* guaranteed across the full range of operation.
* FDCO = freq_out * 2 * mclk_src_scaling
*/
fvco_max = 0;
fvco_sel = ARRAY_SIZE(mclk_src_scaling);
for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param;
if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&
fvco_max < fvco) {
fvco_max = fvco;
fvco_sel = i;
}
}
if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel)
return -EINVAL;
fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
/* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional
* input based on FDCO, FREF and FLL ratio.
*/
fvco = div_u64(fvco_max << fll_param->fll_frac_num, fref * fll_param->ratio);
fll_param->fll_int = (fvco >> fll_param->fll_frac_num) & 0x3FF;
if (fll_param->fll_frac_num == 16)
fll_param->fll_frac = fvco & 0xFFFF;
else
fll_param->fll_frac = fvco & 0xFFFFFF;
return 0;
}
static void nau8825_fll_apply(struct nau8825 *nau8825,
struct nau8825_fll *fll_param)
{
regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
NAU8825_CLK_SRC_MASK | NAU8825_CLK_MCLK_SRC_MASK,
NAU8825_CLK_SRC_MCLK | fll_param->mclk_src);
/* Make DSP operate at high speed for better performance. */
regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1,
NAU8825_FLL_RATIO_MASK | NAU8825_ICTRL_LATCH_MASK,
fll_param->ratio | (0x6 << NAU8825_ICTRL_LATCH_SFT));
/* FLL 16/24 bit fractional input */
if (fll_param->fll_frac_num == 16)
regmap_write(nau8825->regmap, NAU8825_REG_FLL2,
fll_param->fll_frac);
else {
regmap_write(nau8825->regmap, NAU8825_REG_FLL2_LOWER,
fll_param->fll_frac & 0xffff);
regmap_write(nau8825->regmap, NAU8825_REG_FLL2_UPPER,
(fll_param->fll_frac >> 16) & 0xff);
}
/* FLL 10-bit integer input */
regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL3,
NAU8825_FLL_INTEGER_MASK, fll_param->fll_int);
/* FLL pre-scaler */
regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL4,
NAU8825_FLL_REF_DIV_MASK,
fll_param->clk_ref_div << NAU8825_FLL_REF_DIV_SFT);
/* select divided VCO input */
regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
NAU8825_FLL_CLK_SW_MASK, NAU8825_FLL_CLK_SW_REF);
/* Disable free-running mode */
regmap_update_bits(nau8825->regmap,
NAU8825_REG_FLL6, NAU8825_DCO_EN, 0);
if (fll_param->fll_frac) {
/* set FLL loop filter enable and cutoff frequency at 500Khz */
regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
NAU8825_FLL_FTR_SW_MASK,
NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
NAU8825_FLL_FTR_SW_FILTER);
regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6,
NAU8825_SDM_EN | NAU8825_CUTOFF500,
NAU8825_SDM_EN | NAU8825_CUTOFF500);
} else {
/* disable FLL loop filter and cutoff frequency */
regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
NAU8825_FLL_FTR_SW_MASK, NAU8825_FLL_FTR_SW_ACCU);
regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6,
NAU8825_SDM_EN | NAU8825_CUTOFF500, 0);
}
}
/* freq_out must be 256*Fs in order to achieve the best performance */
static int nau8825_set_pll(struct snd_soc_component *component, int pll_id, int source,
unsigned int freq_in, unsigned int freq_out)
{
struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
struct nau8825_fll fll_param;
int ret, fs;
if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825)
fll_param.fll_frac_num = 16;
else
fll_param.fll_frac_num = 24;
fs = freq_out / 256;
ret = nau8825_calc_fll_param(freq_in, fs, &fll_param);
if (ret < 0) {
dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
return ret;
}
dev_dbg(component->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac,
fll_param.fll_int, fll_param.clk_ref_div);
nau8825_fll_apply(nau8825, &fll_param);
mdelay(2);
regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
return 0;
}
static int nau8825_mclk_prepare(struct nau8825 *nau8825, unsigned int freq)
{
int ret;
nau8825->mclk = devm_clk_get(nau8825->dev, "mclk");
if (IS_ERR(nau8825->mclk)) {
dev_info(nau8825->dev, "No 'mclk' clock found, assume MCLK is managed externally");
return 0;
}
if (!nau8825->mclk_freq) {
ret = clk_prepare_enable(nau8825->mclk);
if (ret) {
dev_err(nau8825->dev, "Unable to prepare codec mclk\n");
return ret;
}
}
if (nau8825->mclk_freq != freq) {
freq = clk_round_rate(nau8825->mclk, freq);
ret = clk_set_rate(nau8825->mclk, freq);
if (ret) {
dev_err(nau8825->dev, "Unable to set mclk rate\n");
return ret;
}
nau8825->mclk_freq = freq;
}
return 0;
}
static void nau8825_configure_mclk_as_sysclk(struct regmap *regmap)
{
regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_MCLK);
regmap_update_bits(regmap, NAU8825_REG_FLL6,
NAU8825_DCO_EN, 0);
/* Make DSP operate as default setting for power saving. */
regmap_update_bits(regmap, NAU8825_REG_FLL1,
NAU8825_ICTRL_LATCH_MASK, 0);
}
static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id,
unsigned int freq)
{
struct regmap *regmap = nau8825->regmap;
int ret;
switch (clk_id) {
case NAU8825_CLK_DIS:
/* Clock provided externally and disable internal VCO clock */
nau8825_configure_mclk_as_sysclk(regmap);
if (nau8825->mclk_freq) {
clk_disable_unprepare(nau8825->mclk);
nau8825->mclk_freq = 0;
}
break;
case NAU8825_CLK_MCLK:
/* Acquire the semaphore to synchronize the playback and
* interrupt handler. In order to avoid the playback inter-
* fered by cross talk process, the driver make the playback
* preparation halted until cross talk process finish.
*/
nau8825_sema_acquire(nau8825, 3 * HZ);
nau8825_configure_mclk_as_sysclk(regmap);
/* MCLK not changed by clock tree */
regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
NAU8825_CLK_MCLK_SRC_MASK, 0);
/* Release the semaphore. */
nau8825_sema_release(nau8825);
ret = nau8825_mclk_prepare(nau8825, freq);
if (ret)
return ret;
break;
case NAU8825_CLK_INTERNAL:
if (nau8825_is_jack_inserted(nau8825->regmap)) {
regmap_update_bits(regmap, NAU8825_REG_FLL6,
NAU8825_DCO_EN, NAU8825_DCO_EN);
regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
/* Decrease the VCO frequency and make DSP operate
* as default setting for power saving.
*/
regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
NAU8825_CLK_MCLK_SRC_MASK, 0xf);
regmap_update_bits(regmap, NAU8825_REG_FLL1,
NAU8825_ICTRL_LATCH_MASK |
NAU8825_FLL_RATIO_MASK, 0x10);
regmap_update_bits(regmap, NAU8825_REG_FLL6,
NAU8825_SDM_EN, NAU8825_SDM_EN);
} else {
/* The clock turns off intentionally for power saving
* when no headset connected.
*/
nau8825_configure_mclk_as_sysclk(regmap);
dev_warn(nau8825->dev, "Disable clock for power saving when no headset connected\n");
}
if (nau8825->mclk_freq) {
clk_disable_unprepare(nau8825->mclk);
nau8825->mclk_freq = 0;
}
break;
case NAU8825_CLK_FLL_MCLK:
/* Acquire the semaphore to synchronize the playback and
* interrupt handler. In order to avoid the playback inter-
* fered by cross talk process, the driver make the playback
* preparation halted until cross talk process finish.
*/
nau8825_sema_acquire(nau8825, 3 * HZ);
/* Higher FLL reference input frequency can only set lower
* gain error, such as 0000 for input reference from MCLK
* 12.288Mhz.
*/
regmap_update_bits(regmap, NAU8825_REG_FLL3,
NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK,
NAU8825_FLL_CLK_SRC_MCLK | 0);
/* Release the semaphore. */
nau8825_sema_release(nau8825);
ret = nau8825_mclk_prepare(nau8825, freq);
if (ret)
return ret;
break;
case NAU8825_CLK_FLL_BLK:
/* Acquire the semaphore to synchronize the playback and
* interrupt handler. In order to avoid the playback inter-
* fered by cross talk process, the driver make the playback
* preparation halted until cross talk process finish.
*/
nau8825_sema_acquire(nau8825, 3 * HZ);
/* If FLL reference input is from low frequency source,
* higher error gain can apply such as 0xf which has
* the most sensitive gain error correction threshold,
* Therefore, FLL has the most accurate DCO to
* target frequency.
*/
regmap_update_bits(regmap, NAU8825_REG_FLL3,
NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK,
NAU8825_FLL_CLK_SRC_BLK |
(0xf << NAU8825_GAIN_ERR_SFT));
/* Release the semaphore. */
nau8825_sema_release(nau8825);
if (nau8825->mclk_freq) {
clk_disable_unprepare(nau8825->mclk);
nau8825->mclk_freq = 0;
}
break;
case NAU8825_CLK_FLL_FS:
/* Acquire the semaphore to synchronize the playback and
* interrupt handler. In order to avoid the playback inter-
* fered by cross talk process, the driver make the playback
* preparation halted until cross talk process finish.
*/
nau8825_sema_acquire(nau8825, 3 * HZ);
/* If FLL reference input is from low frequency source,
* higher error gain can apply such as 0xf which has
* the most sensitive gain error correction threshold,
* Therefore, FLL has the most accurate DCO to
* target frequency.
*/
regmap_update_bits(regmap, NAU8825_REG_FLL3,
NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK,
NAU8825_FLL_CLK_SRC_FS |
(0xf << NAU8825_GAIN_ERR_SFT));
/* Release the semaphore. */
nau8825_sema_release(nau8825);
if (nau8825->mclk_freq) {
clk_disable_unprepare(nau8825->mclk);
nau8825->mclk_freq = 0;
}
break;
default:
dev_err(nau8825->dev, "Invalid clock id (%d)\n", clk_id);
return -EINVAL;
}
dev_dbg(nau8825->dev, "Sysclk is %dHz and clock id is %d\n", freq,
clk_id);
return 0;
}
static int nau8825_set_sysclk(struct snd_soc_component *component, int clk_id,
int source, unsigned int freq, int dir)
{
struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
return nau8825_configure_sysclk(nau8825, clk_id, freq);
}
static int nau8825_resume_setup(struct nau8825 *nau8825)
{
struct regmap *regmap = nau8825->regmap;
/* Close clock when jack type detection at manual mode */
nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0);
/* Clear all interruption status */
nau8825_int_status_clear_all(regmap);
/* Enable both insertion and ejection interruptions, and then
* bypass de-bounce circuit.
*/
regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_HEADSET_COMPLETE_EN |
NAU8825_IRQ_EJECT_EN | NAU8825_IRQ_INSERT_EN,
NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_HEADSET_COMPLETE_EN);
regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
NAU8825_JACK_DET_DB_BYPASS, NAU8825_JACK_DET_DB_BYPASS);
regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL,
NAU8825_IRQ_INSERT_DIS | NAU8825_IRQ_EJECT_DIS, 0);
return 0;
}
static int nau8825_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
int ret;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
if (nau8825->mclk_freq) {
ret = clk_prepare_enable(nau8825->mclk);
if (ret) {
dev_err(nau8825->dev, "Unable to prepare component mclk\n");
return ret;
}
}
/* Setup codec configuration after resume */
nau8825_resume_setup(nau8825);
}
break;
case SND_SOC_BIAS_OFF:
/* Reset the configuration of jack type for detection */
/* Detach 2kOhm Resistors from MICBIAS to MICGND1/2 */
regmap_update_bits(nau8825->regmap, NAU8825_REG_MIC_BIAS,
NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0);
/* ground HPL/HPR, MICGRND1/2 */
regmap_update_bits(nau8825->regmap,
NAU8825_REG_HSD_CTRL, 0xf, 0xf);
/* Cancel and reset cross talk detection funciton */
nau8825_xtalk_cancel(nau8825);
/* Turn off all interruptions before system shutdown. Keep the
* interruption quiet before resume setup completes.
*/
regmap_write(nau8825->regmap,
NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff);
/* Disable ADC needed for interruptions at audo mode */
regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
NAU8825_ENABLE_ADC, 0);
if (nau8825->mclk_freq)
clk_disable_unprepare(nau8825->mclk);
break;
}
return 0;
}
static int __maybe_unused nau8825_suspend(struct snd_soc_component *component)
{
struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
disable_irq(nau8825->irq);
snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
/* Power down codec power; don't suppoet button wakeup */
snd_soc_dapm_disable_pin(nau8825->dapm, "SAR");
snd_soc_dapm_disable_pin(nau8825->dapm, "MICBIAS");
snd_soc_dapm_sync(nau8825->dapm);
regcache_cache_only(nau8825->regmap, true);
regcache_mark_dirty(nau8825->regmap);
return 0;
}
static int __maybe_unused nau8825_resume(struct snd_soc_component *component)
{
struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
int ret;
regcache_cache_only(nau8825->regmap, false);
regcache_sync(nau8825->regmap);
nau8825->xtalk_protect = true;
ret = nau8825_sema_acquire(nau8825, 0);
if (ret)
nau8825->xtalk_protect = false;
enable_irq(nau8825->irq);
return 0;
}
static int nau8825_set_jack(struct snd_soc_component *component,
struct snd_soc_jack *jack, void *data)
{
return nau8825_enable_jack_detect(component, jack);
}
static const struct snd_soc_component_driver nau8825_component_driver = {
.probe = nau8825_component_probe,
.remove = nau8825_component_remove,
.set_sysclk = nau8825_set_sysclk,
.set_pll = nau8825_set_pll,
.set_bias_level = nau8825_set_bias_level,
.suspend = nau8825_suspend,
.resume = nau8825_resume,
.controls = nau8825_controls,
.num_controls = ARRAY_SIZE(nau8825_controls),
.dapm_widgets = nau8825_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(nau8825_dapm_widgets),
.dapm_routes = nau8825_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(nau8825_dapm_routes),
.set_jack = nau8825_set_jack,
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static void nau8825_reset_chip(struct regmap *regmap)
{
regmap_write(regmap, NAU8825_REG_RESET, 0x00);
regmap_write(regmap, NAU8825_REG_RESET, 0x00);
}
static void nau8825_print_device_properties(struct nau8825 *nau8825)
{
int i;
struct device *dev = nau8825->dev;
dev_dbg(dev, "jkdet-enable: %d\n", nau8825->jkdet_enable);
dev_dbg(dev, "jkdet-pull-enable: %d\n", nau8825->jkdet_pull_enable);
dev_dbg(dev, "jkdet-pull-up: %d\n", nau8825->jkdet_pull_up);
dev_dbg(dev, "jkdet-polarity: %d\n", nau8825->jkdet_polarity);
dev_dbg(dev, "micbias-voltage: %d\n", nau8825->micbias_voltage);
dev_dbg(dev, "vref-impedance: %d\n", nau8825->vref_impedance);
dev_dbg(dev, "sar-threshold-num: %d\n", nau8825->sar_threshold_num);
for (i = 0; i < nau8825->sar_threshold_num; i++)
dev_dbg(dev, "sar-threshold[%d]=%d\n", i,
nau8825->sar_threshold[i]);
dev_dbg(dev, "sar-hysteresis: %d\n", nau8825->sar_hysteresis);
dev_dbg(dev, "sar-voltage: %d\n", nau8825->sar_voltage);
dev_dbg(dev, "sar-compare-time: %d\n", nau8825->sar_compare_time);
dev_dbg(dev, "sar-sampling-time: %d\n", nau8825->sar_sampling_time);
dev_dbg(dev, "short-key-debounce: %d\n", nau8825->key_debounce);
dev_dbg(dev, "jack-insert-debounce: %d\n",
nau8825->jack_insert_debounce);
dev_dbg(dev, "jack-eject-debounce: %d\n",
nau8825->jack_eject_debounce);
dev_dbg(dev, "crosstalk-enable: %d\n",
nau8825->xtalk_enable);
dev_dbg(dev, "adcout-drive-strong: %d\n", nau8825->adcout_ds);
dev_dbg(dev, "adc-delay-ms: %d\n", nau8825->adc_delay);
}
static int nau8825_read_device_properties(struct device *dev,
struct nau8825 *nau8825) {
int ret;
nau8825->jkdet_enable = device_property_read_bool(dev,
"nuvoton,jkdet-enable");
nau8825->jkdet_pull_enable = device_property_read_bool(dev,
"nuvoton,jkdet-pull-enable");
nau8825->jkdet_pull_up = device_property_read_bool(dev,
"nuvoton,jkdet-pull-up");
ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity",
&nau8825->jkdet_polarity);
if (ret)
nau8825->jkdet_polarity = 1;
ret = device_property_read_u32(dev, "nuvoton,micbias-voltage",
&nau8825->micbias_voltage);
if (ret)
nau8825->micbias_voltage = 6;
ret = device_property_read_u32(dev, "nuvoton,vref-impedance",
&nau8825->vref_impedance);
if (ret)
nau8825->vref_impedance = 2;
ret = device_property_read_u32(dev, "nuvoton,sar-threshold-num",
&nau8825->sar_threshold_num);
if (ret)
nau8825->sar_threshold_num = 4;
ret = device_property_read_u32_array(dev, "nuvoton,sar-threshold",
nau8825->sar_threshold, nau8825->sar_threshold_num);
if (ret) {
nau8825->sar_threshold[0] = 0x08;
nau8825->sar_threshold[1] = 0x12;
nau8825->sar_threshold[2] = 0x26;
nau8825->sar_threshold[3] = 0x73;
}
ret = device_property_read_u32(dev, "nuvoton,sar-hysteresis",
&nau8825->sar_hysteresis);
if (ret)
nau8825->sar_hysteresis = 0;
ret = device_property_read_u32(dev, "nuvoton,sar-voltage",
&nau8825->sar_voltage);
if (ret)
nau8825->sar_voltage = 6;
ret = device_property_read_u32(dev, "nuvoton,sar-compare-time",
&nau8825->sar_compare_time);
if (ret)
nau8825->sar_compare_time = 1;
ret = device_property_read_u32(dev, "nuvoton,sar-sampling-time",
&nau8825->sar_sampling_time);
if (ret)
nau8825->sar_sampling_time = 1;
ret = device_property_read_u32(dev, "nuvoton,short-key-debounce",
&nau8825->key_debounce);
if (ret)
nau8825->key_debounce = 3;
ret = device_property_read_u32(dev, "nuvoton,jack-insert-debounce",
&nau8825->jack_insert_debounce);
if (ret)
nau8825->jack_insert_debounce = 7;
ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce",
&nau8825->jack_eject_debounce);
if (ret)
nau8825->jack_eject_debounce = 0;
nau8825->xtalk_enable = device_property_read_bool(dev,
"nuvoton,crosstalk-enable");
nau8825->adcout_ds = device_property_read_bool(dev, "nuvoton,adcout-drive-strong");
ret = device_property_read_u32(dev, "nuvoton,adc-delay-ms", &nau8825->adc_delay);
if (ret)
nau8825->adc_delay = 125;
if (nau8825->adc_delay < 125 || nau8825->adc_delay > 500)
dev_warn(dev, "Please set the suitable delay time!\n");
nau8825->mclk = devm_clk_get(dev, "mclk");
if (PTR_ERR(nau8825->mclk) == -EPROBE_DEFER) {
return -EPROBE_DEFER;
} else if (PTR_ERR(nau8825->mclk) == -ENOENT) {
/* The MCLK is managed externally or not used at all */
nau8825->mclk = NULL;
dev_info(dev, "No 'mclk' clock found, assume MCLK is managed externally");
} else if (IS_ERR(nau8825->mclk)) {
return -EINVAL;
}
return 0;
}
static int nau8825_setup_irq(struct nau8825 *nau8825)
{
int ret;
ret = devm_request_threaded_irq(nau8825->dev, nau8825->irq, NULL,
nau8825_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT,
"nau8825", nau8825);
if (ret) {
dev_err(nau8825->dev, "Cannot request irq %d (%d)\n",
nau8825->irq, ret);
return ret;
}
return 0;
}
static int nau8825_i2c_probe(struct i2c_client *i2c)
{
struct device *dev = &i2c->dev;
struct nau8825 *nau8825 = dev_get_platdata(&i2c->dev);
int ret, value;
if (!nau8825) {
nau8825 = devm_kzalloc(dev, sizeof(*nau8825), GFP_KERNEL);
if (!nau8825)
return -ENOMEM;
ret = nau8825_read_device_properties(dev, nau8825);
if (ret)
return ret;
}
i2c_set_clientdata(i2c, nau8825);
nau8825->regmap = devm_regmap_init_i2c(i2c, &nau8825_regmap_config);
if (IS_ERR(nau8825->regmap))
return PTR_ERR(nau8825->regmap);
nau8825->dev = dev;
nau8825->irq = i2c->irq;
/* Initiate parameters, semaphore and work queue which are needed in
* cross talk suppression measurment function.
*/
nau8825->xtalk_state = NAU8825_XTALK_DONE;
nau8825->xtalk_protect = false;
nau8825->xtalk_baktab_initialized = false;
sema_init(&nau8825->xtalk_sem, 1);
INIT_WORK(&nau8825->xtalk_work, nau8825_xtalk_work);
nau8825_print_device_properties(nau8825);
nau8825_reset_chip(nau8825->regmap);
ret = regmap_read(nau8825->regmap, NAU8825_REG_I2C_DEVICE_ID, &value);
if (ret < 0) {
dev_err(dev, "Failed to read device id from the NAU8825: %d\n",
ret);
return ret;
}
nau8825->sw_id = value & NAU8825_SOFTWARE_ID_MASK;
switch (nau8825->sw_id) {
case NAU8825_SOFTWARE_ID_NAU8825:
break;
case NAU8825_SOFTWARE_ID_NAU8825C:
ret = regmap_register_patch(nau8825->regmap, nau8825_regmap_patch,
ARRAY_SIZE(nau8825_regmap_patch));
if (ret) {
dev_err(dev, "Failed to register Rev C patch: %d\n", ret);
return ret;
}
break;
default:
dev_err(dev, "Not a NAU8825 chip\n");
return -ENODEV;
}
nau8825_init_regs(nau8825);
if (i2c->irq)
nau8825_setup_irq(nau8825);
return devm_snd_soc_register_component(&i2c->dev,
&nau8825_component_driver,
&nau8825_dai, 1);
}
static void nau8825_i2c_remove(struct i2c_client *client)
{}
static const struct i2c_device_id nau8825_i2c_ids[] = {
{ "nau8825", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, nau8825_i2c_ids);
#ifdef CONFIG_OF
static const struct of_device_id nau8825_of_ids[] = {
{ .compatible = "nuvoton,nau8825", },
{}
};
MODULE_DEVICE_TABLE(of, nau8825_of_ids);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id nau8825_acpi_match[] = {
{ "10508825", 0 },
{},
};
MODULE_DEVICE_TABLE(acpi, nau8825_acpi_match);
#endif
static struct i2c_driver nau8825_driver = {
.driver = {
.name = "nau8825",
.of_match_table = of_match_ptr(nau8825_of_ids),
.acpi_match_table = ACPI_PTR(nau8825_acpi_match),
},
.probe = nau8825_i2c_probe,
.remove = nau8825_i2c_remove,
.id_table = nau8825_i2c_ids,
};
module_i2c_driver(nau8825_driver);
MODULE_DESCRIPTION("ASoC nau8825 driver");
MODULE_AUTHOR("Anatol Pomozov <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/nau8825.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8998.c -- ALSA SoC Audio driver for WM8998 codecs
*
* Copyright 2015 Cirrus Logic, Inc.
*
* Author: Richard Fitzgerald <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/jack.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <linux/mfd/arizona/core.h>
#include <linux/mfd/arizona/registers.h>
#include "arizona.h"
#include "wm8998.h"
struct wm8998_priv {
struct arizona_priv core;
struct arizona_fll fll[2];
};
static int wm8998_asrc_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
unsigned int val;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
val = snd_soc_component_read(component, ARIZONA_ASRC_RATE1);
val &= ARIZONA_ASRC_RATE1_MASK;
val >>= ARIZONA_ASRC_RATE1_SHIFT;
switch (val) {
case 0:
case 1:
case 2:
val = snd_soc_component_read(component,
ARIZONA_SAMPLE_RATE_1 + val);
if (val >= 0x11) {
dev_warn(component->dev,
"Unsupported ASRC rate1 (%s)\n",
arizona_sample_rate_val_to_name(val));
return -EINVAL;
}
break;
default:
dev_err(component->dev,
"Illegal ASRC rate1 selector (0x%x)\n",
val);
return -EINVAL;
}
val = snd_soc_component_read(component, ARIZONA_ASRC_RATE2);
val &= ARIZONA_ASRC_RATE2_MASK;
val >>= ARIZONA_ASRC_RATE2_SHIFT;
switch (val) {
case 8:
case 9:
val -= 0x8;
val = snd_soc_component_read(component,
ARIZONA_ASYNC_SAMPLE_RATE_1 + val);
if (val >= 0x11) {
dev_warn(component->dev,
"Unsupported ASRC rate2 (%s)\n",
arizona_sample_rate_val_to_name(val));
return -EINVAL;
}
break;
default:
dev_err(component->dev,
"Illegal ASRC rate2 selector (0x%x)\n",
val);
return -EINVAL;
}
break;
default:
return -EINVAL;
}
return 0;
}
static int wm8998_inmux_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct wm8998_priv *wm8998 = snd_soc_component_get_drvdata(component);
struct arizona *arizona = wm8998->core.arizona;
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int mode_reg, mode_index;
unsigned int mux, inmode, src_val, mode_val;
int change, ret;
mux = ucontrol->value.enumerated.item[0];
if (mux > 1)
return -EINVAL;
switch (e->reg) {
case ARIZONA_ADC_DIGITAL_VOLUME_2L:
mode_reg = ARIZONA_IN2L_CONTROL;
mode_index = 1 + (2 * mux);
break;
default:
mode_reg = ARIZONA_IN1L_CONTROL;
mode_index = (2 * mux);
break;
}
inmode = arizona->pdata.inmode[mode_index];
if (inmode & ARIZONA_INMODE_DMIC)
mode_val = 1 << ARIZONA_IN1_MODE_SHIFT;
else
mode_val = 0;
src_val = mux << ARIZONA_IN1L_SRC_SHIFT;
if (inmode & ARIZONA_INMODE_SE)
src_val |= 1 << ARIZONA_IN1L_SRC_SE_SHIFT;
snd_soc_component_update_bits(component, mode_reg,
ARIZONA_IN1_MODE_MASK, mode_val);
change = snd_soc_component_update_bits(component, e->reg,
ARIZONA_IN1L_SRC_MASK |
ARIZONA_IN1L_SRC_SE_MASK,
src_val);
ret = snd_soc_dapm_mux_update_power(dapm, kcontrol,
ucontrol->value.enumerated.item[0],
e, NULL);
if (ret < 0) {
dev_err(arizona->dev, "Failed to update demux power state: %d\n", ret);
return ret;
}
return change;
}
static const char * const wm8998_inmux_texts[] = {
"A",
"B",
};
static SOC_ENUM_SINGLE_DECL(wm8998_in1muxl_enum,
ARIZONA_ADC_DIGITAL_VOLUME_1L,
ARIZONA_IN1L_SRC_SHIFT,
wm8998_inmux_texts);
static SOC_ENUM_SINGLE_DECL(wm8998_in1muxr_enum,
ARIZONA_ADC_DIGITAL_VOLUME_1R,
ARIZONA_IN1R_SRC_SHIFT,
wm8998_inmux_texts);
static SOC_ENUM_SINGLE_DECL(wm8998_in2mux_enum,
ARIZONA_ADC_DIGITAL_VOLUME_2L,
ARIZONA_IN2L_SRC_SHIFT,
wm8998_inmux_texts);
static const struct snd_kcontrol_new wm8998_in1mux[2] = {
SOC_DAPM_ENUM_EXT("IN1L Mux", wm8998_in1muxl_enum,
snd_soc_dapm_get_enum_double, wm8998_inmux_put),
SOC_DAPM_ENUM_EXT("IN1R Mux", wm8998_in1muxr_enum,
snd_soc_dapm_get_enum_double, wm8998_inmux_put),
};
static const struct snd_kcontrol_new wm8998_in2mux =
SOC_DAPM_ENUM_EXT("IN2 Mux", wm8998_in2mux_enum,
snd_soc_dapm_get_enum_double, wm8998_inmux_put);
static DECLARE_TLV_DB_SCALE(ana_tlv, 0, 100, 0);
static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0);
static DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
#define WM8998_NG_SRC(name, base) \
SOC_SINGLE(name " NG HPOUTL Switch", base, 0, 1, 0), \
SOC_SINGLE(name " NG HPOUTR Switch", base, 1, 1, 0), \
SOC_SINGLE(name " NG LINEOUTL Switch", base, 2, 1, 0), \
SOC_SINGLE(name " NG LINEOUTR Switch", base, 3, 1, 0), \
SOC_SINGLE(name " NG EPOUT Switch", base, 4, 1, 0), \
SOC_SINGLE(name " NG SPKOUTL Switch", base, 6, 1, 0), \
SOC_SINGLE(name " NG SPKOUTR Switch", base, 7, 1, 0)
static const struct snd_kcontrol_new wm8998_snd_controls[] = {
SOC_ENUM("IN1 OSR", arizona_in_dmic_osr[0]),
SOC_ENUM("IN2 OSR", arizona_in_dmic_osr[1]),
SOC_SINGLE_RANGE_TLV("IN1L Volume", ARIZONA_IN1L_CONTROL,
ARIZONA_IN1L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv),
SOC_SINGLE_RANGE_TLV("IN1R Volume", ARIZONA_IN1R_CONTROL,
ARIZONA_IN1R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv),
SOC_SINGLE_RANGE_TLV("IN2 Volume", ARIZONA_IN2L_CONTROL,
ARIZONA_IN2L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv),
SOC_ENUM("IN HPF Cutoff Frequency", arizona_in_hpf_cut_enum),
SOC_SINGLE("IN1L HPF Switch", ARIZONA_IN1L_CONTROL,
ARIZONA_IN1L_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN1R HPF Switch", ARIZONA_IN1R_CONTROL,
ARIZONA_IN1R_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN2 HPF Switch", ARIZONA_IN2L_CONTROL,
ARIZONA_IN2L_HPF_SHIFT, 1, 0),
SOC_SINGLE_TLV("IN1L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1L,
ARIZONA_IN1L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
SOC_SINGLE_TLV("IN1R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1R,
ARIZONA_IN1R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
SOC_SINGLE_TLV("IN2 Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2L,
ARIZONA_IN2L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
SOC_ENUM("Input Ramp Up", arizona_in_vi_ramp),
SOC_ENUM("Input Ramp Down", arizona_in_vd_ramp),
ARIZONA_GAINMUX_CONTROLS("EQ1", ARIZONA_EQ1MIX_INPUT_1_SOURCE),
ARIZONA_GAINMUX_CONTROLS("EQ2", ARIZONA_EQ2MIX_INPUT_1_SOURCE),
ARIZONA_GAINMUX_CONTROLS("EQ3", ARIZONA_EQ3MIX_INPUT_1_SOURCE),
ARIZONA_GAINMUX_CONTROLS("EQ4", ARIZONA_EQ4MIX_INPUT_1_SOURCE),
SND_SOC_BYTES("EQ1 Coefficients", ARIZONA_EQ1_3, 19),
SOC_SINGLE("EQ1 Mode Switch", ARIZONA_EQ1_2, ARIZONA_EQ1_B1_MODE_SHIFT, 1, 0),
SOC_SINGLE_TLV("EQ1 B1 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B1_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ1 B2 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B2_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ1 B3 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B3_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ1 B4 Volume", ARIZONA_EQ1_2, ARIZONA_EQ1_B4_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ1 B5 Volume", ARIZONA_EQ1_2, ARIZONA_EQ1_B5_GAIN_SHIFT,
24, 0, eq_tlv),
SND_SOC_BYTES("EQ2 Coefficients", ARIZONA_EQ2_3, 19),
SOC_SINGLE("EQ2 Mode Switch", ARIZONA_EQ2_2, ARIZONA_EQ2_B1_MODE_SHIFT, 1, 0),
SOC_SINGLE_TLV("EQ2 B1 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B1_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ2 B2 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B2_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ2 B3 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B3_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ2 B4 Volume", ARIZONA_EQ2_2, ARIZONA_EQ2_B4_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ2 B5 Volume", ARIZONA_EQ2_2, ARIZONA_EQ2_B5_GAIN_SHIFT,
24, 0, eq_tlv),
SND_SOC_BYTES("EQ3 Coefficients", ARIZONA_EQ3_3, 19),
SOC_SINGLE("EQ3 Mode Switch", ARIZONA_EQ3_2, ARIZONA_EQ3_B1_MODE_SHIFT, 1, 0),
SOC_SINGLE_TLV("EQ3 B1 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B1_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ3 B2 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B2_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ3 B3 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B3_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ3 B4 Volume", ARIZONA_EQ3_2, ARIZONA_EQ3_B4_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ3 B5 Volume", ARIZONA_EQ3_2, ARIZONA_EQ3_B5_GAIN_SHIFT,
24, 0, eq_tlv),
SND_SOC_BYTES("EQ4 Coefficients", ARIZONA_EQ4_3, 19),
SOC_SINGLE("EQ4 Mode Switch", ARIZONA_EQ4_2, ARIZONA_EQ4_B1_MODE_SHIFT, 1, 0),
SOC_SINGLE_TLV("EQ4 B1 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B1_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ4 B2 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B2_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ4 B3 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B3_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ4 B4 Volume", ARIZONA_EQ4_2, ARIZONA_EQ4_B4_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ4 B5 Volume", ARIZONA_EQ4_2, ARIZONA_EQ4_B5_GAIN_SHIFT,
24, 0, eq_tlv),
ARIZONA_GAINMUX_CONTROLS("DRC1L", ARIZONA_DRC1LMIX_INPUT_1_SOURCE),
ARIZONA_GAINMUX_CONTROLS("DRC1R", ARIZONA_DRC1RMIX_INPUT_1_SOURCE),
SND_SOC_BYTES_MASK("DRC1", ARIZONA_DRC1_CTRL1, 5,
ARIZONA_DRC1R_ENA | ARIZONA_DRC1L_ENA),
ARIZONA_MIXER_CONTROLS("LHPF1", ARIZONA_HPLP1MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("LHPF2", ARIZONA_HPLP2MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("LHPF3", ARIZONA_HPLP3MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("LHPF4", ARIZONA_HPLP4MIX_INPUT_1_SOURCE),
SND_SOC_BYTES("LHPF1 Coefficients", ARIZONA_HPLPF1_2, 1),
SND_SOC_BYTES("LHPF2 Coefficients", ARIZONA_HPLPF2_2, 1),
SND_SOC_BYTES("LHPF3 Coefficients", ARIZONA_HPLPF3_2, 1),
SND_SOC_BYTES("LHPF4 Coefficients", ARIZONA_HPLPF4_2, 1),
SOC_ENUM("LHPF1 Mode", arizona_lhpf1_mode),
SOC_ENUM("LHPF2 Mode", arizona_lhpf2_mode),
SOC_ENUM("LHPF3 Mode", arizona_lhpf3_mode),
SOC_ENUM("LHPF4 Mode", arizona_lhpf4_mode),
SOC_ENUM("ISRC1 FSL", arizona_isrc_fsl[0]),
SOC_ENUM("ISRC2 FSL", arizona_isrc_fsl[1]),
SOC_ENUM("ISRC1 FSH", arizona_isrc_fsh[0]),
SOC_ENUM("ISRC2 FSH", arizona_isrc_fsh[1]),
SOC_ENUM("ASRC RATE 1", arizona_asrc_rate1),
ARIZONA_MIXER_CONTROLS("HPOUTL", ARIZONA_OUT1LMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("HPOUTR", ARIZONA_OUT1RMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("LINEOUTL", ARIZONA_OUT2LMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("LINEOUTR", ARIZONA_OUT2RMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("EPOUT", ARIZONA_OUT3LMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SPKOUTL", ARIZONA_OUT4LMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SPKOUTR", ARIZONA_OUT4RMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SPKDATL", ARIZONA_OUT5LMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SPKDATR", ARIZONA_OUT5RMIX_INPUT_1_SOURCE),
SOC_DOUBLE_R("HPOUT Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_1L,
ARIZONA_DAC_DIGITAL_VOLUME_1R, ARIZONA_OUT1L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R("LINEOUT Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_2L,
ARIZONA_DAC_DIGITAL_VOLUME_2R, ARIZONA_OUT2L_MUTE_SHIFT, 1, 1),
SOC_SINGLE("EPOUT Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_3L,
ARIZONA_OUT3L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R("Speaker Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_4L,
ARIZONA_DAC_DIGITAL_VOLUME_4R, ARIZONA_OUT4L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R("SPKDAT Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_5L,
ARIZONA_DAC_DIGITAL_VOLUME_5R, ARIZONA_OUT5L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R_TLV("HPOUT Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_1L,
ARIZONA_DAC_DIGITAL_VOLUME_1R, ARIZONA_OUT1L_VOL_SHIFT,
0xbf, 0, digital_tlv),
SOC_DOUBLE_R_TLV("LINEOUT Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_2L,
ARIZONA_DAC_DIGITAL_VOLUME_2R, ARIZONA_OUT2L_VOL_SHIFT,
0xbf, 0, digital_tlv),
SOC_SINGLE_TLV("EPOUT Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_3L,
ARIZONA_OUT3L_VOL_SHIFT, 0xbf, 0, digital_tlv),
SOC_DOUBLE_R_TLV("Speaker Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_4L,
ARIZONA_DAC_DIGITAL_VOLUME_4R, ARIZONA_OUT4L_VOL_SHIFT,
0xbf, 0, digital_tlv),
SOC_DOUBLE_R_TLV("SPKDAT Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_5L,
ARIZONA_DAC_DIGITAL_VOLUME_5R, ARIZONA_OUT5L_VOL_SHIFT,
0xbf, 0, digital_tlv),
SOC_DOUBLE("SPKDAT Switch", ARIZONA_PDM_SPK1_CTRL_1, ARIZONA_SPK1L_MUTE_SHIFT,
ARIZONA_SPK1R_MUTE_SHIFT, 1, 1),
SOC_ENUM("Output Ramp Up", arizona_out_vi_ramp),
SOC_ENUM("Output Ramp Down", arizona_out_vd_ramp),
SOC_SINGLE("Noise Gate Switch", ARIZONA_NOISE_GATE_CONTROL,
ARIZONA_NGATE_ENA_SHIFT, 1, 0),
SOC_SINGLE_TLV("Noise Gate Threshold Volume", ARIZONA_NOISE_GATE_CONTROL,
ARIZONA_NGATE_THR_SHIFT, 7, 1, ng_tlv),
SOC_ENUM("Noise Gate Hold", arizona_ng_hold),
WM8998_NG_SRC("HPOUTL", ARIZONA_NOISE_GATE_SELECT_1L),
WM8998_NG_SRC("HPOUTR", ARIZONA_NOISE_GATE_SELECT_1R),
WM8998_NG_SRC("LINEOUTL", ARIZONA_NOISE_GATE_SELECT_2L),
WM8998_NG_SRC("LINEOUTR", ARIZONA_NOISE_GATE_SELECT_2R),
WM8998_NG_SRC("EPOUT", ARIZONA_NOISE_GATE_SELECT_3L),
WM8998_NG_SRC("SPKOUTL", ARIZONA_NOISE_GATE_SELECT_4L),
WM8998_NG_SRC("SPKOUTR", ARIZONA_NOISE_GATE_SELECT_4R),
WM8998_NG_SRC("SPKDATL", ARIZONA_NOISE_GATE_SELECT_5L),
WM8998_NG_SRC("SPKDATR", ARIZONA_NOISE_GATE_SELECT_5R),
ARIZONA_MIXER_CONTROLS("AIF1TX1", ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF1TX2", ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF1TX3", ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF1TX4", ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF1TX5", ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF1TX6", ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF2TX1", ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF2TX2", ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF2TX3", ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF2TX4", ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF2TX5", ARIZONA_AIF2TX5MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF2TX6", ARIZONA_AIF2TX6MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF3TX1", ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF3TX2", ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE),
ARIZONA_GAINMUX_CONTROLS("SLIMTX1", ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE),
ARIZONA_GAINMUX_CONTROLS("SLIMTX2", ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE),
ARIZONA_GAINMUX_CONTROLS("SLIMTX3", ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE),
ARIZONA_GAINMUX_CONTROLS("SLIMTX4", ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE),
ARIZONA_GAINMUX_CONTROLS("SLIMTX5", ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE),
ARIZONA_GAINMUX_CONTROLS("SLIMTX6", ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE),
ARIZONA_GAINMUX_CONTROLS("SPDIFTX1", ARIZONA_SPDIFTX1MIX_INPUT_1_SOURCE),
ARIZONA_GAINMUX_CONTROLS("SPDIFTX2", ARIZONA_SPDIFTX2MIX_INPUT_1_SOURCE),
};
ARIZONA_MUX_ENUMS(EQ1, ARIZONA_EQ1MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(EQ2, ARIZONA_EQ2MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(EQ3, ARIZONA_EQ3MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(EQ4, ARIZONA_EQ4MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(DRC1L, ARIZONA_DRC1LMIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(DRC1R, ARIZONA_DRC1RMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(LHPF1, ARIZONA_HPLP1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(LHPF2, ARIZONA_HPLP2MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(LHPF3, ARIZONA_HPLP3MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(LHPF4, ARIZONA_HPLP4MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(PWM1, ARIZONA_PWM1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(PWM2, ARIZONA_PWM2MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(OUT1L, ARIZONA_OUT1LMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(OUT1R, ARIZONA_OUT1RMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(OUT2L, ARIZONA_OUT2LMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(OUT2R, ARIZONA_OUT2RMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(OUT3, ARIZONA_OUT3LMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SPKOUTL, ARIZONA_OUT4LMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SPKOUTR, ARIZONA_OUT4RMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SPKDATL, ARIZONA_OUT5LMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SPKDATR, ARIZONA_OUT5RMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX1, ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX2, ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX3, ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX4, ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX5, ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX6, ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF2TX1, ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF2TX2, ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF2TX3, ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF2TX4, ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF2TX5, ARIZONA_AIF2TX5MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF2TX6, ARIZONA_AIF2TX6MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF3TX1, ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF3TX2, ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(SLIMTX1, ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(SLIMTX2, ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(SLIMTX3, ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(SLIMTX4, ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(SLIMTX5, ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(SLIMTX6, ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(SPD1TX1, ARIZONA_SPDIFTX1MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(SPD1TX2, ARIZONA_SPDIFTX2MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ASRC1L, ARIZONA_ASRC1LMIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ASRC1R, ARIZONA_ASRC1RMIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ASRC2L, ARIZONA_ASRC2LMIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ASRC2R, ARIZONA_ASRC2RMIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC1INT1, ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC1INT2, ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC1INT3, ARIZONA_ISRC1INT3MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC1INT4, ARIZONA_ISRC1INT4MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC1DEC1, ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC1DEC2, ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC1DEC3, ARIZONA_ISRC1DEC3MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC1DEC4, ARIZONA_ISRC1DEC4MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC2INT1, ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC2INT2, ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC2DEC1, ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC2DEC2, ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE);
static const char * const wm8998_aec_loopback_texts[] = {
"HPOUTL", "HPOUTR", "LINEOUTL", "LINEOUTR", "EPOUT",
"SPKOUTL", "SPKOUTR", "SPKDATL", "SPKDATR",
};
static const unsigned int wm8998_aec_loopback_values[] = {
0, 1, 2, 3, 4, 6, 7, 8, 9,
};
static SOC_VALUE_ENUM_SINGLE_DECL(wm8998_aec1_loopback,
ARIZONA_DAC_AEC_CONTROL_1,
ARIZONA_AEC_LOOPBACK_SRC_SHIFT, 0xf,
wm8998_aec_loopback_texts,
wm8998_aec_loopback_values);
static SOC_VALUE_ENUM_SINGLE_DECL(wm8998_aec2_loopback,
ARIZONA_DAC_AEC_CONTROL_2,
ARIZONA_AEC_LOOPBACK_SRC_SHIFT, 0xf,
wm8998_aec_loopback_texts,
wm8998_aec_loopback_values);
static const struct snd_kcontrol_new wm8998_aec_loopback_mux[] = {
SOC_DAPM_ENUM("AEC1 Loopback", wm8998_aec1_loopback),
SOC_DAPM_ENUM("AEC2 Loopback", wm8998_aec2_loopback),
};
static const struct snd_soc_dapm_widget wm8998_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("SYSCLK", ARIZONA_SYSTEM_CLOCK_1,
ARIZONA_SYSCLK_ENA_SHIFT, 0, arizona_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("ASYNCCLK", ARIZONA_ASYNC_CLOCK_1,
ARIZONA_ASYNC_CLK_ENA_SHIFT, 0, arizona_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("OPCLK", ARIZONA_OUTPUT_SYSTEM_CLOCK,
ARIZONA_OPCLK_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ASYNCOPCLK", ARIZONA_OUTPUT_ASYNC_CLOCK,
ARIZONA_OPCLK_ASYNC_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD2", 0, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD3", 0, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("MICVDD", 0, SND_SOC_DAPM_REGULATOR_BYPASS),
SND_SOC_DAPM_REGULATOR_SUPPLY("SPKVDDL", 0, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("SPKVDDR", 0, 0),
SND_SOC_DAPM_SIGGEN("TONE"),
SND_SOC_DAPM_SIGGEN("HAPTICS"),
SND_SOC_DAPM_INPUT("IN1AL"),
SND_SOC_DAPM_INPUT("IN1AR"),
SND_SOC_DAPM_INPUT("IN1BL"),
SND_SOC_DAPM_INPUT("IN1BR"),
SND_SOC_DAPM_INPUT("IN2A"),
SND_SOC_DAPM_INPUT("IN2B"),
SND_SOC_DAPM_MUX("IN1L Mux", SND_SOC_NOPM, 0, 0, &wm8998_in1mux[0]),
SND_SOC_DAPM_MUX("IN1R Mux", SND_SOC_NOPM, 0, 0, &wm8998_in1mux[1]),
SND_SOC_DAPM_MUX("IN2 Mux", SND_SOC_NOPM, 0, 0, &wm8998_in2mux),
SND_SOC_DAPM_OUTPUT("DRC1 Signal Activity"),
SND_SOC_DAPM_PGA_E("IN1L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN1L_ENA_SHIFT,
0, NULL, 0, arizona_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN1R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN1R_ENA_SHIFT,
0, NULL, 0, arizona_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN2 PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN2L_ENA_SHIFT,
0, NULL, 0, arizona_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY("MICBIAS1", ARIZONA_MIC_BIAS_CTRL_1,
ARIZONA_MICB1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS2", ARIZONA_MIC_BIAS_CTRL_2,
ARIZONA_MICB1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS3", ARIZONA_MIC_BIAS_CTRL_3,
ARIZONA_MICB1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("Tone Generator 1", ARIZONA_TONE_GENERATOR_1,
ARIZONA_TONE1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("Tone Generator 2", ARIZONA_TONE_GENERATOR_1,
ARIZONA_TONE2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ1", ARIZONA_EQ1_1, ARIZONA_EQ1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ2", ARIZONA_EQ2_1, ARIZONA_EQ2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ3", ARIZONA_EQ3_1, ARIZONA_EQ3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ4", ARIZONA_EQ4_1, ARIZONA_EQ4_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("DRC1L", ARIZONA_DRC1_CTRL1, ARIZONA_DRC1L_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("DRC1R", ARIZONA_DRC1_CTRL1, ARIZONA_DRC1R_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF1", ARIZONA_HPLPF1_1, ARIZONA_LHPF1_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF2", ARIZONA_HPLPF2_1, ARIZONA_LHPF2_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF3", ARIZONA_HPLPF3_1, ARIZONA_LHPF3_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF4", ARIZONA_HPLPF4_1, ARIZONA_LHPF4_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("PWM1 Driver", ARIZONA_PWM_DRIVE_1, ARIZONA_PWM1_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA("PWM2 Driver", ARIZONA_PWM_DRIVE_1, ARIZONA_PWM2_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA_E("ASRC1L", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC1L_ENA_SHIFT, 0,
NULL, 0, wm8998_asrc_ev, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_PGA_E("ASRC1R", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC1R_ENA_SHIFT, 0,
NULL, 0, wm8998_asrc_ev, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_PGA_E("ASRC2L", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC2L_ENA_SHIFT, 0,
NULL, 0, wm8998_asrc_ev, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_PGA_E("ASRC2R", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC2R_ENA_SHIFT, 0,
NULL, 0, wm8998_asrc_ev, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_PGA("ISRC1INT1", ARIZONA_ISRC_1_CTRL_3,
ARIZONA_ISRC1_INT0_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1INT2", ARIZONA_ISRC_1_CTRL_3,
ARIZONA_ISRC1_INT1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1INT3", ARIZONA_ISRC_1_CTRL_3,
ARIZONA_ISRC1_INT2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1INT4", ARIZONA_ISRC_1_CTRL_3,
ARIZONA_ISRC1_INT3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC1", ARIZONA_ISRC_1_CTRL_3,
ARIZONA_ISRC1_DEC0_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC2", ARIZONA_ISRC_1_CTRL_3,
ARIZONA_ISRC1_DEC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC3", ARIZONA_ISRC_1_CTRL_3,
ARIZONA_ISRC1_DEC2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC4", ARIZONA_ISRC_1_CTRL_3,
ARIZONA_ISRC1_DEC3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2INT1", ARIZONA_ISRC_2_CTRL_3,
ARIZONA_ISRC2_INT0_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2INT2", ARIZONA_ISRC_2_CTRL_3,
ARIZONA_ISRC2_INT1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2DEC1", ARIZONA_ISRC_2_CTRL_3,
ARIZONA_ISRC2_DEC0_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2DEC2", ARIZONA_ISRC_2_CTRL_3,
ARIZONA_ISRC2_DEC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_MUX("AEC1 Loopback", ARIZONA_DAC_AEC_CONTROL_1,
ARIZONA_AEC_LOOPBACK_ENA_SHIFT, 0,
&wm8998_aec_loopback_mux[0]),
SND_SOC_DAPM_MUX("AEC2 Loopback", ARIZONA_DAC_AEC_CONTROL_2,
ARIZONA_AEC_LOOPBACK_ENA_SHIFT, 0,
&wm8998_aec_loopback_mux[1]),
SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 0,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 1,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 2,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 3,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 4,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX6", NULL, 5,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 0,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 1,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 2,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 3,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 4,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX6", NULL, 5,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0,
ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX2", NULL, 1,
ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX3", NULL, 2,
ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX4", NULL, 3,
ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX5", NULL, 4,
ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX6", NULL, 5,
ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0,
ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX2", NULL, 1,
ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX3", NULL, 2,
ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX4", NULL, 3,
ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX5", NULL, 4,
ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX6", NULL, 5,
ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX1", NULL, 0,
ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE,
ARIZONA_SLIMRX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX2", NULL, 1,
ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE,
ARIZONA_SLIMRX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX3", NULL, 2,
ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE,
ARIZONA_SLIMRX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX4", NULL, 3,
ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE,
ARIZONA_SLIMRX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX1", NULL, 0,
ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE,
ARIZONA_SLIMTX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX2", NULL, 1,
ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE,
ARIZONA_SLIMTX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX3", NULL, 2,
ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE,
ARIZONA_SLIMTX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX4", NULL, 3,
ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE,
ARIZONA_SLIMTX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX5", NULL, 4,
ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE,
ARIZONA_SLIMTX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX6", NULL, 5,
ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE,
ARIZONA_SLIMTX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF3TX1", NULL, 0,
ARIZONA_AIF3_TX_ENABLES, ARIZONA_AIF3TX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF3TX2", NULL, 1,
ARIZONA_AIF3_TX_ENABLES, ARIZONA_AIF3TX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF3RX1", NULL, 0,
ARIZONA_AIF3_RX_ENABLES, ARIZONA_AIF3RX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF3RX2", NULL, 1,
ARIZONA_AIF3_RX_ENABLES, ARIZONA_AIF3RX2_ENA_SHIFT, 0),
SND_SOC_DAPM_PGA_E("OUT1L", SND_SOC_NOPM,
ARIZONA_OUT1L_ENA_SHIFT, 0, NULL, 0, arizona_hp_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT1R", SND_SOC_NOPM,
ARIZONA_OUT1R_ENA_SHIFT, 0, NULL, 0, arizona_hp_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT2L", ARIZONA_OUTPUT_ENABLES_1,
ARIZONA_OUT2L_ENA_SHIFT, 0, NULL, 0, arizona_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT2R", ARIZONA_OUTPUT_ENABLES_1,
ARIZONA_OUT2R_ENA_SHIFT, 0, NULL, 0, arizona_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT3", ARIZONA_OUTPUT_ENABLES_1,
ARIZONA_OUT3L_ENA_SHIFT, 0, NULL, 0, arizona_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT5L", ARIZONA_OUTPUT_ENABLES_1,
ARIZONA_OUT5L_ENA_SHIFT, 0, NULL, 0, arizona_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT5R", ARIZONA_OUTPUT_ENABLES_1,
ARIZONA_OUT5R_ENA_SHIFT, 0, NULL, 0, arizona_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA("SPD1TX1", ARIZONA_SPD1_TX_CONTROL,
ARIZONA_SPD1_VAL1_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("SPD1TX2", ARIZONA_SPD1_TX_CONTROL,
ARIZONA_SPD1_VAL2_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("SPD1", ARIZONA_SPD1_TX_CONTROL,
ARIZONA_SPD1_ENA_SHIFT, 0, NULL, 0),
ARIZONA_MUX_WIDGETS(EQ1, "EQ1"),
ARIZONA_MUX_WIDGETS(EQ2, "EQ2"),
ARIZONA_MUX_WIDGETS(EQ3, "EQ3"),
ARIZONA_MUX_WIDGETS(EQ4, "EQ4"),
ARIZONA_MUX_WIDGETS(DRC1L, "DRC1L"),
ARIZONA_MUX_WIDGETS(DRC1R, "DRC1R"),
ARIZONA_MIXER_WIDGETS(LHPF1, "LHPF1"),
ARIZONA_MIXER_WIDGETS(LHPF2, "LHPF2"),
ARIZONA_MIXER_WIDGETS(LHPF3, "LHPF3"),
ARIZONA_MIXER_WIDGETS(LHPF4, "LHPF4"),
ARIZONA_MIXER_WIDGETS(PWM1, "PWM1"),
ARIZONA_MIXER_WIDGETS(PWM2, "PWM2"),
ARIZONA_MIXER_WIDGETS(OUT1L, "HPOUTL"),
ARIZONA_MIXER_WIDGETS(OUT1R, "HPOUTR"),
ARIZONA_MIXER_WIDGETS(OUT2L, "LINEOUTL"),
ARIZONA_MIXER_WIDGETS(OUT2R, "LINEOUTR"),
ARIZONA_MIXER_WIDGETS(OUT3, "EPOUT"),
ARIZONA_MIXER_WIDGETS(SPKOUTL, "SPKOUTL"),
ARIZONA_MIXER_WIDGETS(SPKOUTR, "SPKOUTR"),
ARIZONA_MIXER_WIDGETS(SPKDATL, "SPKDATL"),
ARIZONA_MIXER_WIDGETS(SPKDATR, "SPKDATR"),
ARIZONA_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"),
ARIZONA_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"),
ARIZONA_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"),
ARIZONA_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"),
ARIZONA_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"),
ARIZONA_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"),
ARIZONA_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"),
ARIZONA_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"),
ARIZONA_MIXER_WIDGETS(AIF2TX3, "AIF2TX3"),
ARIZONA_MIXER_WIDGETS(AIF2TX4, "AIF2TX4"),
ARIZONA_MIXER_WIDGETS(AIF2TX5, "AIF2TX5"),
ARIZONA_MIXER_WIDGETS(AIF2TX6, "AIF2TX6"),
ARIZONA_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"),
ARIZONA_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"),
ARIZONA_MUX_WIDGETS(SLIMTX1, "SLIMTX1"),
ARIZONA_MUX_WIDGETS(SLIMTX2, "SLIMTX2"),
ARIZONA_MUX_WIDGETS(SLIMTX3, "SLIMTX3"),
ARIZONA_MUX_WIDGETS(SLIMTX4, "SLIMTX4"),
ARIZONA_MUX_WIDGETS(SLIMTX5, "SLIMTX5"),
ARIZONA_MUX_WIDGETS(SLIMTX6, "SLIMTX6"),
ARIZONA_MUX_WIDGETS(SPD1TX1, "SPDIFTX1"),
ARIZONA_MUX_WIDGETS(SPD1TX2, "SPDIFTX2"),
ARIZONA_MUX_WIDGETS(ASRC1L, "ASRC1L"),
ARIZONA_MUX_WIDGETS(ASRC1R, "ASRC1R"),
ARIZONA_MUX_WIDGETS(ASRC2L, "ASRC2L"),
ARIZONA_MUX_WIDGETS(ASRC2R, "ASRC2R"),
ARIZONA_MUX_WIDGETS(ISRC1DEC1, "ISRC1DEC1"),
ARIZONA_MUX_WIDGETS(ISRC1DEC2, "ISRC1DEC2"),
ARIZONA_MUX_WIDGETS(ISRC1DEC3, "ISRC1DEC3"),
ARIZONA_MUX_WIDGETS(ISRC1DEC4, "ISRC1DEC4"),
ARIZONA_MUX_WIDGETS(ISRC1INT1, "ISRC1INT1"),
ARIZONA_MUX_WIDGETS(ISRC1INT2, "ISRC1INT2"),
ARIZONA_MUX_WIDGETS(ISRC1INT3, "ISRC1INT3"),
ARIZONA_MUX_WIDGETS(ISRC1INT4, "ISRC1INT4"),
ARIZONA_MUX_WIDGETS(ISRC2DEC1, "ISRC2DEC1"),
ARIZONA_MUX_WIDGETS(ISRC2DEC2, "ISRC2DEC2"),
ARIZONA_MUX_WIDGETS(ISRC2INT1, "ISRC2INT1"),
ARIZONA_MUX_WIDGETS(ISRC2INT2, "ISRC2INT2"),
SND_SOC_DAPM_OUTPUT("HPOUTL"),
SND_SOC_DAPM_OUTPUT("HPOUTR"),
SND_SOC_DAPM_OUTPUT("LINEOUTL"),
SND_SOC_DAPM_OUTPUT("LINEOUTR"),
SND_SOC_DAPM_OUTPUT("EPOUT"),
SND_SOC_DAPM_OUTPUT("SPKOUTLN"),
SND_SOC_DAPM_OUTPUT("SPKOUTLP"),
SND_SOC_DAPM_OUTPUT("SPKOUTRN"),
SND_SOC_DAPM_OUTPUT("SPKOUTRP"),
SND_SOC_DAPM_OUTPUT("SPKDATL"),
SND_SOC_DAPM_OUTPUT("SPKDATR"),
SND_SOC_DAPM_OUTPUT("SPDIF"),
SND_SOC_DAPM_OUTPUT("MICSUPP"),
};
#define ARIZONA_MIXER_INPUT_ROUTES(name) \
{ name, "Tone Generator 1", "Tone Generator 1" }, \
{ name, "Tone Generator 2", "Tone Generator 2" }, \
{ name, "Haptics", "HAPTICS" }, \
{ name, "AEC", "AEC1 Loopback" }, \
{ name, "AEC2", "AEC2 Loopback" }, \
{ name, "IN1L", "IN1L PGA" }, \
{ name, "IN1R", "IN1R PGA" }, \
{ name, "IN2L", "IN2 PGA" }, \
{ name, "AIF1RX1", "AIF1RX1" }, \
{ name, "AIF1RX2", "AIF1RX2" }, \
{ name, "AIF1RX3", "AIF1RX3" }, \
{ name, "AIF1RX4", "AIF1RX4" }, \
{ name, "AIF1RX5", "AIF1RX5" }, \
{ name, "AIF1RX6", "AIF1RX6" }, \
{ name, "AIF2RX1", "AIF2RX1" }, \
{ name, "AIF2RX2", "AIF2RX2" }, \
{ name, "AIF2RX3", "AIF2RX3" }, \
{ name, "AIF2RX4", "AIF2RX4" }, \
{ name, "AIF2RX5", "AIF2RX5" }, \
{ name, "AIF2RX6", "AIF2RX6" }, \
{ name, "AIF3RX1", "AIF3RX1" }, \
{ name, "AIF3RX2", "AIF3RX2" }, \
{ name, "SLIMRX1", "SLIMRX1" }, \
{ name, "SLIMRX2", "SLIMRX2" }, \
{ name, "SLIMRX3", "SLIMRX3" }, \
{ name, "SLIMRX4", "SLIMRX4" }, \
{ name, "EQ1", "EQ1" }, \
{ name, "EQ2", "EQ2" }, \
{ name, "EQ3", "EQ3" }, \
{ name, "EQ4", "EQ4" }, \
{ name, "DRC1L", "DRC1L" }, \
{ name, "DRC1R", "DRC1R" }, \
{ name, "LHPF1", "LHPF1" }, \
{ name, "LHPF2", "LHPF2" }, \
{ name, "LHPF3", "LHPF3" }, \
{ name, "LHPF4", "LHPF4" }, \
{ name, "ASRC1L", "ASRC1L" }, \
{ name, "ASRC1R", "ASRC1R" }, \
{ name, "ASRC2L", "ASRC2L" }, \
{ name, "ASRC2R", "ASRC2R" }, \
{ name, "ISRC1DEC1", "ISRC1DEC1" }, \
{ name, "ISRC1DEC2", "ISRC1DEC2" }, \
{ name, "ISRC1DEC3", "ISRC1DEC3" }, \
{ name, "ISRC1DEC4", "ISRC1DEC4" }, \
{ name, "ISRC1INT1", "ISRC1INT1" }, \
{ name, "ISRC1INT2", "ISRC1INT2" }, \
{ name, "ISRC1INT3", "ISRC1INT3" }, \
{ name, "ISRC1INT4", "ISRC1INT4" }, \
{ name, "ISRC2DEC1", "ISRC2DEC1" }, \
{ name, "ISRC2DEC2", "ISRC2DEC2" }, \
{ name, "ISRC2INT1", "ISRC2INT1" }, \
{ name, "ISRC2INT2", "ISRC2INT2" }
static const struct snd_soc_dapm_route wm8998_dapm_routes[] = {
{ "AIF2 Capture", NULL, "DBVDD2" },
{ "AIF2 Playback", NULL, "DBVDD2" },
{ "AIF3 Capture", NULL, "DBVDD3" },
{ "AIF3 Playback", NULL, "DBVDD3" },
{ "OUT1L", NULL, "CPVDD" },
{ "OUT1R", NULL, "CPVDD" },
{ "OUT2L", NULL, "CPVDD" },
{ "OUT2R", NULL, "CPVDD" },
{ "OUT3", NULL, "CPVDD" },
{ "OUT4L", NULL, "SPKVDDL" },
{ "OUT4R", NULL, "SPKVDDR" },
{ "OUT1L", NULL, "SYSCLK" },
{ "OUT1R", NULL, "SYSCLK" },
{ "OUT2L", NULL, "SYSCLK" },
{ "OUT2R", NULL, "SYSCLK" },
{ "OUT3", NULL, "SYSCLK" },
{ "OUT4L", NULL, "SYSCLK" },
{ "OUT4R", NULL, "SYSCLK" },
{ "OUT5L", NULL, "SYSCLK" },
{ "OUT5R", NULL, "SYSCLK" },
{ "IN1AL", NULL, "SYSCLK" },
{ "IN1AR", NULL, "SYSCLK" },
{ "IN1BL", NULL, "SYSCLK" },
{ "IN1BR", NULL, "SYSCLK" },
{ "IN2A", NULL, "SYSCLK" },
{ "IN2B", NULL, "SYSCLK" },
{ "ASRC1L", NULL, "SYSCLK" },
{ "ASRC1R", NULL, "SYSCLK" },
{ "ASRC2L", NULL, "SYSCLK" },
{ "ASRC2R", NULL, "SYSCLK" },
{ "ASRC1L", NULL, "ASYNCCLK" },
{ "ASRC1R", NULL, "ASYNCCLK" },
{ "ASRC2L", NULL, "ASYNCCLK" },
{ "ASRC2R", NULL, "ASYNCCLK" },
{ "SPD1", NULL, "SYSCLK" },
{ "SPD1", NULL, "SPD1TX1" },
{ "SPD1", NULL, "SPD1TX2" },
{ "MICBIAS1", NULL, "MICVDD" },
{ "MICBIAS2", NULL, "MICVDD" },
{ "MICBIAS3", NULL, "MICVDD" },
{ "Tone Generator 1", NULL, "SYSCLK" },
{ "Tone Generator 2", NULL, "SYSCLK" },
{ "Tone Generator 1", NULL, "TONE" },
{ "Tone Generator 2", NULL, "TONE" },
{ "AIF1 Capture", NULL, "AIF1TX1" },
{ "AIF1 Capture", NULL, "AIF1TX2" },
{ "AIF1 Capture", NULL, "AIF1TX3" },
{ "AIF1 Capture", NULL, "AIF1TX4" },
{ "AIF1 Capture", NULL, "AIF1TX5" },
{ "AIF1 Capture", NULL, "AIF1TX6" },
{ "AIF1RX1", NULL, "AIF1 Playback" },
{ "AIF1RX2", NULL, "AIF1 Playback" },
{ "AIF1RX3", NULL, "AIF1 Playback" },
{ "AIF1RX4", NULL, "AIF1 Playback" },
{ "AIF1RX5", NULL, "AIF1 Playback" },
{ "AIF1RX6", NULL, "AIF1 Playback" },
{ "AIF2 Capture", NULL, "AIF2TX1" },
{ "AIF2 Capture", NULL, "AIF2TX2" },
{ "AIF2 Capture", NULL, "AIF2TX3" },
{ "AIF2 Capture", NULL, "AIF2TX4" },
{ "AIF2 Capture", NULL, "AIF2TX5" },
{ "AIF2 Capture", NULL, "AIF2TX6" },
{ "AIF2RX1", NULL, "AIF2 Playback" },
{ "AIF2RX2", NULL, "AIF2 Playback" },
{ "AIF2RX3", NULL, "AIF2 Playback" },
{ "AIF2RX4", NULL, "AIF2 Playback" },
{ "AIF2RX5", NULL, "AIF2 Playback" },
{ "AIF2RX6", NULL, "AIF2 Playback" },
{ "AIF3 Capture", NULL, "AIF3TX1" },
{ "AIF3 Capture", NULL, "AIF3TX2" },
{ "AIF3RX1", NULL, "AIF3 Playback" },
{ "AIF3RX2", NULL, "AIF3 Playback" },
{ "Slim1 Capture", NULL, "SLIMTX1" },
{ "Slim1 Capture", NULL, "SLIMTX2" },
{ "Slim1 Capture", NULL, "SLIMTX3" },
{ "Slim1 Capture", NULL, "SLIMTX4" },
{ "Slim2 Capture", NULL, "SLIMTX5" },
{ "Slim2 Capture", NULL, "SLIMTX6" },
{ "SLIMRX1", NULL, "Slim1 Playback" },
{ "SLIMRX2", NULL, "Slim1 Playback" },
{ "SLIMRX3", NULL, "Slim2 Playback" },
{ "SLIMRX4", NULL, "Slim2 Playback" },
{ "AIF1 Playback", NULL, "SYSCLK" },
{ "AIF2 Playback", NULL, "SYSCLK" },
{ "AIF3 Playback", NULL, "SYSCLK" },
{ "Slim1 Playback", NULL, "SYSCLK" },
{ "Slim2 Playback", NULL, "SYSCLK" },
{ "AIF1 Capture", NULL, "SYSCLK" },
{ "AIF2 Capture", NULL, "SYSCLK" },
{ "AIF3 Capture", NULL, "SYSCLK" },
{ "Slim1 Capture", NULL, "SYSCLK" },
{ "Slim2 Capture", NULL, "SYSCLK" },
{ "IN1L Mux", "A", "IN1AL" },
{ "IN1R Mux", "A", "IN1AR" },
{ "IN1L Mux", "B", "IN1BL" },
{ "IN1R Mux", "B", "IN1BR" },
{ "IN2 Mux", "A", "IN2A" },
{ "IN2 Mux", "B", "IN2B" },
{ "IN1L PGA", NULL, "IN1L Mux" },
{ "IN1R PGA", NULL, "IN1R Mux" },
{ "IN2 PGA", NULL, "IN2 Mux" },
ARIZONA_MIXER_ROUTES("OUT1L", "HPOUTL"),
ARIZONA_MIXER_ROUTES("OUT1R", "HPOUTR"),
ARIZONA_MIXER_ROUTES("OUT2L", "LINEOUTL"),
ARIZONA_MIXER_ROUTES("OUT2R", "LINEOUTR"),
ARIZONA_MIXER_ROUTES("OUT3", "EPOUT"),
ARIZONA_MIXER_ROUTES("OUT4L", "SPKOUTL"),
ARIZONA_MIXER_ROUTES("OUT4R", "SPKOUTR"),
ARIZONA_MIXER_ROUTES("OUT5L", "SPKDATL"),
ARIZONA_MIXER_ROUTES("OUT5R", "SPKDATR"),
ARIZONA_MIXER_ROUTES("PWM1 Driver", "PWM1"),
ARIZONA_MIXER_ROUTES("PWM2 Driver", "PWM2"),
ARIZONA_MIXER_ROUTES("AIF1TX1", "AIF1TX1"),
ARIZONA_MIXER_ROUTES("AIF1TX2", "AIF1TX2"),
ARIZONA_MIXER_ROUTES("AIF1TX3", "AIF1TX3"),
ARIZONA_MIXER_ROUTES("AIF1TX4", "AIF1TX4"),
ARIZONA_MIXER_ROUTES("AIF1TX5", "AIF1TX5"),
ARIZONA_MIXER_ROUTES("AIF1TX6", "AIF1TX6"),
ARIZONA_MIXER_ROUTES("AIF2TX1", "AIF2TX1"),
ARIZONA_MIXER_ROUTES("AIF2TX2", "AIF2TX2"),
ARIZONA_MIXER_ROUTES("AIF2TX3", "AIF2TX3"),
ARIZONA_MIXER_ROUTES("AIF2TX4", "AIF2TX4"),
ARIZONA_MIXER_ROUTES("AIF2TX5", "AIF2TX5"),
ARIZONA_MIXER_ROUTES("AIF2TX6", "AIF2TX6"),
ARIZONA_MIXER_ROUTES("AIF3TX1", "AIF3TX1"),
ARIZONA_MIXER_ROUTES("AIF3TX2", "AIF3TX2"),
ARIZONA_MUX_ROUTES("SLIMTX1", "SLIMTX1"),
ARIZONA_MUX_ROUTES("SLIMTX2", "SLIMTX2"),
ARIZONA_MUX_ROUTES("SLIMTX3", "SLIMTX3"),
ARIZONA_MUX_ROUTES("SLIMTX4", "SLIMTX4"),
ARIZONA_MUX_ROUTES("SLIMTX5", "SLIMTX5"),
ARIZONA_MUX_ROUTES("SLIMTX6", "SLIMTX6"),
ARIZONA_MUX_ROUTES("SPD1TX1", "SPDIFTX1"),
ARIZONA_MUX_ROUTES("SPD1TX2", "SPDIFTX2"),
ARIZONA_MUX_ROUTES("EQ1", "EQ1"),
ARIZONA_MUX_ROUTES("EQ2", "EQ2"),
ARIZONA_MUX_ROUTES("EQ3", "EQ3"),
ARIZONA_MUX_ROUTES("EQ4", "EQ4"),
ARIZONA_MUX_ROUTES("DRC1L", "DRC1L"),
ARIZONA_MUX_ROUTES("DRC1R", "DRC1R"),
ARIZONA_MIXER_ROUTES("LHPF1", "LHPF1"),
ARIZONA_MIXER_ROUTES("LHPF2", "LHPF2"),
ARIZONA_MIXER_ROUTES("LHPF3", "LHPF3"),
ARIZONA_MIXER_ROUTES("LHPF4", "LHPF4"),
ARIZONA_MUX_ROUTES("ASRC1L", "ASRC1L"),
ARIZONA_MUX_ROUTES("ASRC1R", "ASRC1R"),
ARIZONA_MUX_ROUTES("ASRC2L", "ASRC2L"),
ARIZONA_MUX_ROUTES("ASRC2R", "ASRC2R"),
ARIZONA_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"),
ARIZONA_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"),
ARIZONA_MUX_ROUTES("ISRC1INT3", "ISRC1INT3"),
ARIZONA_MUX_ROUTES("ISRC1INT4", "ISRC1INT4"),
ARIZONA_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"),
ARIZONA_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"),
ARIZONA_MUX_ROUTES("ISRC1DEC3", "ISRC1DEC3"),
ARIZONA_MUX_ROUTES("ISRC1DEC4", "ISRC1DEC4"),
ARIZONA_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"),
ARIZONA_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"),
ARIZONA_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"),
ARIZONA_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"),
{ "AEC1 Loopback", "HPOUTL", "OUT1L" },
{ "AEC1 Loopback", "HPOUTR", "OUT1R" },
{ "AEC2 Loopback", "HPOUTL", "OUT1L" },
{ "AEC2 Loopback", "HPOUTR", "OUT1R" },
{ "HPOUTL", NULL, "OUT1L" },
{ "HPOUTR", NULL, "OUT1R" },
{ "AEC1 Loopback", "LINEOUTL", "OUT2L" },
{ "AEC1 Loopback", "LINEOUTR", "OUT2R" },
{ "AEC2 Loopback", "LINEOUTL", "OUT2L" },
{ "AEC2 Loopback", "LINEOUTR", "OUT2R" },
{ "LINEOUTL", NULL, "OUT2L" },
{ "LINEOUTR", NULL, "OUT2R" },
{ "AEC1 Loopback", "EPOUT", "OUT3" },
{ "AEC2 Loopback", "EPOUT", "OUT3" },
{ "EPOUT", NULL, "OUT3" },
{ "AEC1 Loopback", "SPKOUTL", "OUT4L" },
{ "AEC2 Loopback", "SPKOUTL", "OUT4L" },
{ "SPKOUTLN", NULL, "OUT4L" },
{ "SPKOUTLP", NULL, "OUT4L" },
{ "AEC1 Loopback", "SPKOUTR", "OUT4R" },
{ "AEC2 Loopback", "SPKOUTR", "OUT4R" },
{ "SPKOUTRN", NULL, "OUT4R" },
{ "SPKOUTRP", NULL, "OUT4R" },
{ "SPDIF", NULL, "SPD1" },
{ "AEC1 Loopback", "SPKDATL", "OUT5L" },
{ "AEC1 Loopback", "SPKDATR", "OUT5R" },
{ "AEC2 Loopback", "SPKDATL", "OUT5L" },
{ "AEC2 Loopback", "SPKDATR", "OUT5R" },
{ "SPKDATL", NULL, "OUT5L" },
{ "SPKDATR", NULL, "OUT5R" },
{ "MICSUPP", NULL, "SYSCLK" },
{ "DRC1 Signal Activity", NULL, "SYSCLK" },
{ "DRC1 Signal Activity", NULL, "DRC1L" },
{ "DRC1 Signal Activity", NULL, "DRC1R" },
};
#define WM8998_RATES SNDRV_PCM_RATE_KNOT
#define WM8998_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver wm8998_dai[] = {
{
.name = "wm8998-aif1",
.id = 1,
.base = ARIZONA_AIF1_BCLK_CTRL,
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 6,
.rates = WM8998_RATES,
.formats = WM8998_FORMATS,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 1,
.channels_max = 6,
.rates = WM8998_RATES,
.formats = WM8998_FORMATS,
},
.ops = &arizona_dai_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
{
.name = "wm8998-aif2",
.id = 2,
.base = ARIZONA_AIF2_BCLK_CTRL,
.playback = {
.stream_name = "AIF2 Playback",
.channels_min = 1,
.channels_max = 6,
.rates = WM8998_RATES,
.formats = WM8998_FORMATS,
},
.capture = {
.stream_name = "AIF2 Capture",
.channels_min = 1,
.channels_max = 6,
.rates = WM8998_RATES,
.formats = WM8998_FORMATS,
},
.ops = &arizona_dai_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
{
.name = "wm8998-aif3",
.id = 3,
.base = ARIZONA_AIF3_BCLK_CTRL,
.playback = {
.stream_name = "AIF3 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM8998_RATES,
.formats = WM8998_FORMATS,
},
.capture = {
.stream_name = "AIF3 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM8998_RATES,
.formats = WM8998_FORMATS,
},
.ops = &arizona_dai_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
{
.name = "wm8998-slim1",
.id = 4,
.playback = {
.stream_name = "Slim1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM8998_RATES,
.formats = WM8998_FORMATS,
},
.capture = {
.stream_name = "Slim1 Capture",
.channels_min = 1,
.channels_max = 4,
.rates = WM8998_RATES,
.formats = WM8998_FORMATS,
},
.ops = &arizona_simple_dai_ops,
},
{
.name = "wm8998-slim2",
.id = 5,
.playback = {
.stream_name = "Slim2 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM8998_RATES,
.formats = WM8998_FORMATS,
},
.capture = {
.stream_name = "Slim2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM8998_RATES,
.formats = WM8998_FORMATS,
},
.ops = &arizona_simple_dai_ops,
},
};
static int wm8998_set_fll(struct snd_soc_component *component, int fll_id,
int source, unsigned int Fref, unsigned int Fout)
{
struct wm8998_priv *wm8998 = snd_soc_component_get_drvdata(component);
switch (fll_id) {
case WM8998_FLL1:
return arizona_set_fll(&wm8998->fll[0], source, Fref, Fout);
case WM8998_FLL2:
return arizona_set_fll(&wm8998->fll[1], source, Fref, Fout);
case WM8998_FLL1_REFCLK:
return arizona_set_fll_refclk(&wm8998->fll[0], source, Fref,
Fout);
case WM8998_FLL2_REFCLK:
return arizona_set_fll_refclk(&wm8998->fll[1], source, Fref,
Fout);
default:
return -EINVAL;
}
}
static int wm8998_component_probe(struct snd_soc_component *component)
{
struct wm8998_priv *priv = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct arizona *arizona = priv->core.arizona;
int ret;
arizona->dapm = dapm;
snd_soc_component_init_regmap(component, arizona->regmap);
ret = arizona_init_spk(component);
if (ret < 0)
return ret;
arizona_init_gpio(component);
snd_soc_component_disable_pin(component, "HAPTICS");
return 0;
}
static void wm8998_component_remove(struct snd_soc_component *component)
{
struct wm8998_priv *priv = snd_soc_component_get_drvdata(component);
priv->core.arizona->dapm = NULL;
}
#define WM8998_DIG_VU 0x0200
static unsigned int wm8998_digital_vu[] = {
ARIZONA_DAC_DIGITAL_VOLUME_1L,
ARIZONA_DAC_DIGITAL_VOLUME_1R,
ARIZONA_DAC_DIGITAL_VOLUME_2L,
ARIZONA_DAC_DIGITAL_VOLUME_2R,
ARIZONA_DAC_DIGITAL_VOLUME_3L,
ARIZONA_DAC_DIGITAL_VOLUME_4L,
ARIZONA_DAC_DIGITAL_VOLUME_4R,
ARIZONA_DAC_DIGITAL_VOLUME_5L,
ARIZONA_DAC_DIGITAL_VOLUME_5R,
};
static const struct snd_soc_component_driver soc_component_dev_wm8998 = {
.probe = wm8998_component_probe,
.remove = wm8998_component_remove,
.set_sysclk = arizona_set_sysclk,
.set_pll = wm8998_set_fll,
.set_jack = arizona_jack_set_jack,
.controls = wm8998_snd_controls,
.num_controls = ARRAY_SIZE(wm8998_snd_controls),
.dapm_widgets = wm8998_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8998_dapm_widgets),
.dapm_routes = wm8998_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(wm8998_dapm_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
static int wm8998_probe(struct platform_device *pdev)
{
struct arizona *arizona = dev_get_drvdata(pdev->dev.parent);
struct wm8998_priv *wm8998;
int i, ret;
wm8998 = devm_kzalloc(&pdev->dev, sizeof(struct wm8998_priv),
GFP_KERNEL);
if (!wm8998)
return -ENOMEM;
platform_set_drvdata(pdev, wm8998);
if (IS_ENABLED(CONFIG_OF)) {
if (!dev_get_platdata(arizona->dev)) {
ret = arizona_of_get_audio_pdata(arizona);
if (ret < 0)
return ret;
}
}
wm8998->core.arizona = arizona;
wm8998->core.num_inputs = 3; /* IN1L, IN1R, IN2 */
/* This may return -EPROBE_DEFER, so do this early on */
ret = arizona_jack_codec_dev_probe(&wm8998->core, &pdev->dev);
if (ret)
return ret;
for (i = 0; i < ARRAY_SIZE(wm8998->fll); i++)
wm8998->fll[i].vco_mult = 1;
arizona_init_fll(arizona, 1, ARIZONA_FLL1_CONTROL_1 - 1,
ARIZONA_IRQ_FLL1_LOCK, ARIZONA_IRQ_FLL1_CLOCK_OK,
&wm8998->fll[0]);
arizona_init_fll(arizona, 2, ARIZONA_FLL2_CONTROL_1 - 1,
ARIZONA_IRQ_FLL2_LOCK, ARIZONA_IRQ_FLL2_CLOCK_OK,
&wm8998->fll[1]);
for (i = 0; i < ARRAY_SIZE(wm8998_dai); i++)
arizona_init_dai(&wm8998->core, i);
/* Latch volume update bits */
for (i = 0; i < ARRAY_SIZE(wm8998_digital_vu); i++)
regmap_update_bits(arizona->regmap, wm8998_digital_vu[i],
WM8998_DIG_VU, WM8998_DIG_VU);
pm_runtime_enable(&pdev->dev);
pm_runtime_idle(&pdev->dev);
arizona_init_common(arizona);
ret = arizona_init_spk_irqs(arizona);
if (ret < 0)
goto err_pm_disable;
ret = devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_wm8998,
wm8998_dai,
ARRAY_SIZE(wm8998_dai));
if (ret < 0) {
dev_err(&pdev->dev, "Failed to register component: %d\n", ret);
goto err_spk_irqs;
}
return ret;
err_spk_irqs:
arizona_free_spk_irqs(arizona);
err_pm_disable:
pm_runtime_disable(&pdev->dev);
arizona_jack_codec_dev_remove(&wm8998->core);
return ret;
}
static void wm8998_remove(struct platform_device *pdev)
{
struct wm8998_priv *wm8998 = platform_get_drvdata(pdev);
struct arizona *arizona = wm8998->core.arizona;
pm_runtime_disable(&pdev->dev);
arizona_free_spk_irqs(arizona);
arizona_jack_codec_dev_remove(&wm8998->core);
}
static struct platform_driver wm8998_codec_driver = {
.driver = {
.name = "wm8998-codec",
},
.probe = wm8998_probe,
.remove_new = wm8998_remove,
};
module_platform_driver(wm8998_codec_driver);
MODULE_DESCRIPTION("ASoC WM8998 driver");
MODULE_AUTHOR("Richard Fitzgerald <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:wm8998-codec");
| linux-master | sound/soc/codecs/wm8998.c |
// SPDX-License-Identifier: GPL-2.0-only
// Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
#include <linux/module.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/tlv.h>
#include <linux/of_clk.h>
#include <linux/clk-provider.h>
#include "lpass-macro-common.h"
#define CDC_TX_CLK_RST_CTRL_MCLK_CONTROL (0x0000)
#define CDC_TX_MCLK_EN_MASK BIT(0)
#define CDC_TX_MCLK_ENABLE BIT(0)
#define CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL (0x0004)
#define CDC_TX_FS_CNT_EN_MASK BIT(0)
#define CDC_TX_FS_CNT_ENABLE BIT(0)
#define CDC_TX_CLK_RST_CTRL_SWR_CONTROL (0x0008)
#define CDC_TX_SWR_RESET_MASK BIT(1)
#define CDC_TX_SWR_RESET_ENABLE BIT(1)
#define CDC_TX_SWR_CLK_EN_MASK BIT(0)
#define CDC_TX_SWR_CLK_ENABLE BIT(0)
#define CDC_TX_TOP_CSR_TOP_CFG0 (0x0080)
#define CDC_TX_TOP_CSR_ANC_CFG (0x0084)
#define CDC_TX_TOP_CSR_SWR_CTRL (0x0088)
#define CDC_TX_TOP_CSR_FREQ_MCLK (0x0090)
#define CDC_TX_TOP_CSR_DEBUG_BUS (0x0094)
#define CDC_TX_TOP_CSR_DEBUG_EN (0x0098)
#define CDC_TX_TOP_CSR_TX_I2S_CTL (0x00A4)
#define CDC_TX_TOP_CSR_I2S_CLK (0x00A8)
#define CDC_TX_TOP_CSR_I2S_RESET (0x00AC)
#define CDC_TX_TOP_CSR_SWR_DMICn_CTL(n) (0x00C0 + n * 0x4)
#define CDC_TX_TOP_CSR_SWR_DMIC0_CTL (0x00C0)
#define CDC_TX_SWR_DMIC_CLK_SEL_MASK GENMASK(3, 1)
#define CDC_TX_TOP_CSR_SWR_DMIC1_CTL (0x00C4)
#define CDC_TX_TOP_CSR_SWR_DMIC2_CTL (0x00C8)
#define CDC_TX_TOP_CSR_SWR_DMIC3_CTL (0x00CC)
#define CDC_TX_TOP_CSR_SWR_AMIC0_CTL (0x00D0)
#define CDC_TX_TOP_CSR_SWR_AMIC1_CTL (0x00D4)
#define CDC_TX_INP_MUX_ADC_MUXn_CFG0(n) (0x0100 + 0x8 * n)
#define CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK GENMASK(3, 0)
#define CDC_TX_MACRO_DMIC_MUX_SEL_MASK GENMASK(7, 4)
#define CDC_TX_INP_MUX_ADC_MUX0_CFG0 (0x0100)
#define CDC_TX_INP_MUX_ADC_MUXn_CFG1(n) (0x0104 + 0x8 * n)
#define CDC_TX_INP_MUX_ADC_MUX0_CFG1 (0x0104)
#define CDC_TX_INP_MUX_ADC_MUX1_CFG0 (0x0108)
#define CDC_TX_INP_MUX_ADC_MUX1_CFG1 (0x010C)
#define CDC_TX_INP_MUX_ADC_MUX2_CFG0 (0x0110)
#define CDC_TX_INP_MUX_ADC_MUX2_CFG1 (0x0114)
#define CDC_TX_INP_MUX_ADC_MUX3_CFG0 (0x0118)
#define CDC_TX_INP_MUX_ADC_MUX3_CFG1 (0x011C)
#define CDC_TX_INP_MUX_ADC_MUX4_CFG0 (0x0120)
#define CDC_TX_INP_MUX_ADC_MUX4_CFG1 (0x0124)
#define CDC_TX_INP_MUX_ADC_MUX5_CFG0 (0x0128)
#define CDC_TX_INP_MUX_ADC_MUX5_CFG1 (0x012C)
#define CDC_TX_INP_MUX_ADC_MUX6_CFG0 (0x0130)
#define CDC_TX_INP_MUX_ADC_MUX6_CFG1 (0x0134)
#define CDC_TX_INP_MUX_ADC_MUX7_CFG0 (0x0138)
#define CDC_TX_INP_MUX_ADC_MUX7_CFG1 (0x013C)
#define CDC_TX_ANC0_CLK_RESET_CTL (0x0200)
#define CDC_TX_ANC0_MODE_1_CTL (0x0204)
#define CDC_TX_ANC0_MODE_2_CTL (0x0208)
#define CDC_TX_ANC0_FF_SHIFT (0x020C)
#define CDC_TX_ANC0_FB_SHIFT (0x0210)
#define CDC_TX_ANC0_LPF_FF_A_CTL (0x0214)
#define CDC_TX_ANC0_LPF_FF_B_CTL (0x0218)
#define CDC_TX_ANC0_LPF_FB_CTL (0x021C)
#define CDC_TX_ANC0_SMLPF_CTL (0x0220)
#define CDC_TX_ANC0_DCFLT_SHIFT_CTL (0x0224)
#define CDC_TX_ANC0_IIR_ADAPT_CTL (0x0228)
#define CDC_TX_ANC0_IIR_COEFF_1_CTL (0x022C)
#define CDC_TX_ANC0_IIR_COEFF_2_CTL (0x0230)
#define CDC_TX_ANC0_FF_A_GAIN_CTL (0x0234)
#define CDC_TX_ANC0_FF_B_GAIN_CTL (0x0238)
#define CDC_TX_ANC0_FB_GAIN_CTL (0x023C)
#define CDC_TXn_TX_PATH_CTL(n) (0x0400 + 0x80 * n)
#define CDC_TXn_PCM_RATE_MASK GENMASK(3, 0)
#define CDC_TXn_PGA_MUTE_MASK BIT(4)
#define CDC_TXn_CLK_EN_MASK BIT(5)
#define CDC_TX0_TX_PATH_CTL (0x0400)
#define CDC_TXn_TX_PATH_CFG0(n) (0x0404 + 0x80 * n)
#define CDC_TX0_TX_PATH_CFG0 (0x0404)
#define CDC_TXn_PH_EN_MASK BIT(0)
#define CDC_TXn_ADC_MODE_MASK GENMASK(2, 1)
#define CDC_TXn_HPF_CUT_FREQ_MASK GENMASK(6, 5)
#define CDC_TXn_ADC_DMIC_SEL_MASK BIT(7)
#define CDC_TX0_TX_PATH_CFG1 (0x0408)
#define CDC_TXn_TX_VOL_CTL(n) (0x040C + 0x80 * n)
#define CDC_TX0_TX_VOL_CTL (0x040C)
#define CDC_TX0_TX_PATH_SEC0 (0x0410)
#define CDC_TX0_TX_PATH_SEC1 (0x0414)
#define CDC_TXn_TX_PATH_SEC2(n) (0x0418 + 0x80 * n)
#define CDC_TXn_HPF_F_CHANGE_MASK BIT(1)
#define CDC_TXn_HPF_ZERO_GATE_MASK BIT(0)
#define CDC_TX0_TX_PATH_SEC2 (0x0418)
#define CDC_TX0_TX_PATH_SEC3 (0x041C)
#define CDC_TX0_TX_PATH_SEC4 (0x0420)
#define CDC_TX0_TX_PATH_SEC5 (0x0424)
#define CDC_TX0_TX_PATH_SEC6 (0x0428)
#define CDC_TX0_TX_PATH_SEC7 (0x042C)
#define CDC_TX0_MBHC_CTL_EN_MASK BIT(6)
#define CDC_TX1_TX_PATH_CTL (0x0480)
#define CDC_TX1_TX_PATH_CFG0 (0x0484)
#define CDC_TX1_TX_PATH_CFG1 (0x0488)
#define CDC_TX1_TX_VOL_CTL (0x048C)
#define CDC_TX1_TX_PATH_SEC0 (0x0490)
#define CDC_TX1_TX_PATH_SEC1 (0x0494)
#define CDC_TX1_TX_PATH_SEC2 (0x0498)
#define CDC_TX1_TX_PATH_SEC3 (0x049C)
#define CDC_TX1_TX_PATH_SEC4 (0x04A0)
#define CDC_TX1_TX_PATH_SEC5 (0x04A4)
#define CDC_TX1_TX_PATH_SEC6 (0x04A8)
#define CDC_TX2_TX_PATH_CTL (0x0500)
#define CDC_TX2_TX_PATH_CFG0 (0x0504)
#define CDC_TX2_TX_PATH_CFG1 (0x0508)
#define CDC_TX2_TX_VOL_CTL (0x050C)
#define CDC_TX2_TX_PATH_SEC0 (0x0510)
#define CDC_TX2_TX_PATH_SEC1 (0x0514)
#define CDC_TX2_TX_PATH_SEC2 (0x0518)
#define CDC_TX2_TX_PATH_SEC3 (0x051C)
#define CDC_TX2_TX_PATH_SEC4 (0x0520)
#define CDC_TX2_TX_PATH_SEC5 (0x0524)
#define CDC_TX2_TX_PATH_SEC6 (0x0528)
#define CDC_TX3_TX_PATH_CTL (0x0580)
#define CDC_TX3_TX_PATH_CFG0 (0x0584)
#define CDC_TX3_TX_PATH_CFG1 (0x0588)
#define CDC_TX3_TX_VOL_CTL (0x058C)
#define CDC_TX3_TX_PATH_SEC0 (0x0590)
#define CDC_TX3_TX_PATH_SEC1 (0x0594)
#define CDC_TX3_TX_PATH_SEC2 (0x0598)
#define CDC_TX3_TX_PATH_SEC3 (0x059C)
#define CDC_TX3_TX_PATH_SEC4 (0x05A0)
#define CDC_TX3_TX_PATH_SEC5 (0x05A4)
#define CDC_TX3_TX_PATH_SEC6 (0x05A8)
#define CDC_TX4_TX_PATH_CTL (0x0600)
#define CDC_TX4_TX_PATH_CFG0 (0x0604)
#define CDC_TX4_TX_PATH_CFG1 (0x0608)
#define CDC_TX4_TX_VOL_CTL (0x060C)
#define CDC_TX4_TX_PATH_SEC0 (0x0610)
#define CDC_TX4_TX_PATH_SEC1 (0x0614)
#define CDC_TX4_TX_PATH_SEC2 (0x0618)
#define CDC_TX4_TX_PATH_SEC3 (0x061C)
#define CDC_TX4_TX_PATH_SEC4 (0x0620)
#define CDC_TX4_TX_PATH_SEC5 (0x0624)
#define CDC_TX4_TX_PATH_SEC6 (0x0628)
#define CDC_TX5_TX_PATH_CTL (0x0680)
#define CDC_TX5_TX_PATH_CFG0 (0x0684)
#define CDC_TX5_TX_PATH_CFG1 (0x0688)
#define CDC_TX5_TX_VOL_CTL (0x068C)
#define CDC_TX5_TX_PATH_SEC0 (0x0690)
#define CDC_TX5_TX_PATH_SEC1 (0x0694)
#define CDC_TX5_TX_PATH_SEC2 (0x0698)
#define CDC_TX5_TX_PATH_SEC3 (0x069C)
#define CDC_TX5_TX_PATH_SEC4 (0x06A0)
#define CDC_TX5_TX_PATH_SEC5 (0x06A4)
#define CDC_TX5_TX_PATH_SEC6 (0x06A8)
#define CDC_TX6_TX_PATH_CTL (0x0700)
#define CDC_TX6_TX_PATH_CFG0 (0x0704)
#define CDC_TX6_TX_PATH_CFG1 (0x0708)
#define CDC_TX6_TX_VOL_CTL (0x070C)
#define CDC_TX6_TX_PATH_SEC0 (0x0710)
#define CDC_TX6_TX_PATH_SEC1 (0x0714)
#define CDC_TX6_TX_PATH_SEC2 (0x0718)
#define CDC_TX6_TX_PATH_SEC3 (0x071C)
#define CDC_TX6_TX_PATH_SEC4 (0x0720)
#define CDC_TX6_TX_PATH_SEC5 (0x0724)
#define CDC_TX6_TX_PATH_SEC6 (0x0728)
#define CDC_TX7_TX_PATH_CTL (0x0780)
#define CDC_TX7_TX_PATH_CFG0 (0x0784)
#define CDC_TX7_TX_PATH_CFG1 (0x0788)
#define CDC_TX7_TX_VOL_CTL (0x078C)
#define CDC_TX7_TX_PATH_SEC0 (0x0790)
#define CDC_TX7_TX_PATH_SEC1 (0x0794)
#define CDC_TX7_TX_PATH_SEC2 (0x0798)
#define CDC_TX7_TX_PATH_SEC3 (0x079C)
#define CDC_TX7_TX_PATH_SEC4 (0x07A0)
#define CDC_TX7_TX_PATH_SEC5 (0x07A4)
#define CDC_TX7_TX_PATH_SEC6 (0x07A8)
#define TX_MAX_OFFSET (0x07A8)
#define TX_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
#define TX_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S24_3LE)
#define CF_MIN_3DB_4HZ 0x0
#define CF_MIN_3DB_75HZ 0x1
#define CF_MIN_3DB_150HZ 0x2
#define TX_ADC_MAX 5
#define TX_ADC_TO_DMIC(n) ((n - TX_ADC_MAX)/2)
#define NUM_DECIMATORS 8
#define TX_NUM_CLKS_MAX 5
#define TX_MACRO_DMIC_UNMUTE_DELAY_MS 40
#define TX_MACRO_AMIC_UNMUTE_DELAY_MS 100
#define TX_MACRO_DMIC_HPF_DELAY_MS 300
#define TX_MACRO_AMIC_HPF_DELAY_MS 300
#define MCLK_FREQ 19200000
enum {
TX_MACRO_AIF_INVALID = 0,
TX_MACRO_AIF1_CAP,
TX_MACRO_AIF2_CAP,
TX_MACRO_AIF3_CAP,
TX_MACRO_MAX_DAIS
};
enum {
TX_MACRO_DEC0,
TX_MACRO_DEC1,
TX_MACRO_DEC2,
TX_MACRO_DEC3,
TX_MACRO_DEC4,
TX_MACRO_DEC5,
TX_MACRO_DEC6,
TX_MACRO_DEC7,
TX_MACRO_DEC_MAX,
};
enum {
TX_MACRO_CLK_DIV_2,
TX_MACRO_CLK_DIV_3,
TX_MACRO_CLK_DIV_4,
TX_MACRO_CLK_DIV_6,
TX_MACRO_CLK_DIV_8,
TX_MACRO_CLK_DIV_16,
};
enum {
MSM_DMIC,
SWR_MIC,
ANC_FB_TUNE1
};
struct tx_mute_work {
struct tx_macro *tx;
u8 decimator;
struct delayed_work dwork;
};
struct hpf_work {
struct tx_macro *tx;
u8 decimator;
u8 hpf_cut_off_freq;
struct delayed_work dwork;
};
struct tx_macro {
struct device *dev;
struct snd_soc_component *component;
struct hpf_work tx_hpf_work[NUM_DECIMATORS];
struct tx_mute_work tx_mute_dwork[NUM_DECIMATORS];
unsigned long active_ch_mask[TX_MACRO_MAX_DAIS];
unsigned long active_ch_cnt[TX_MACRO_MAX_DAIS];
int active_decimator[TX_MACRO_MAX_DAIS];
struct regmap *regmap;
struct clk *mclk;
struct clk *npl;
struct clk *macro;
struct clk *dcodec;
struct clk *fsgen;
struct clk_hw hw;
bool dec_active[NUM_DECIMATORS];
int tx_mclk_users;
u16 dmic_clk_div;
bool bcs_enable;
int dec_mode[NUM_DECIMATORS];
struct lpass_macro *pds;
bool bcs_clk_en;
};
#define to_tx_macro(_hw) container_of(_hw, struct tx_macro, hw)
static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
static struct reg_default tx_defaults[] = {
/* TX Macro */
{ CDC_TX_CLK_RST_CTRL_MCLK_CONTROL, 0x00 },
{ CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00 },
{ CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 0x00},
{ CDC_TX_TOP_CSR_TOP_CFG0, 0x00},
{ CDC_TX_TOP_CSR_ANC_CFG, 0x00},
{ CDC_TX_TOP_CSR_SWR_CTRL, 0x00},
{ CDC_TX_TOP_CSR_FREQ_MCLK, 0x00},
{ CDC_TX_TOP_CSR_DEBUG_BUS, 0x00},
{ CDC_TX_TOP_CSR_DEBUG_EN, 0x00},
{ CDC_TX_TOP_CSR_TX_I2S_CTL, 0x0C},
{ CDC_TX_TOP_CSR_I2S_CLK, 0x00},
{ CDC_TX_TOP_CSR_I2S_RESET, 0x00},
{ CDC_TX_TOP_CSR_SWR_DMIC0_CTL, 0x00},
{ CDC_TX_TOP_CSR_SWR_DMIC1_CTL, 0x00},
{ CDC_TX_TOP_CSR_SWR_DMIC2_CTL, 0x00},
{ CDC_TX_TOP_CSR_SWR_DMIC3_CTL, 0x00},
{ CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0x00},
{ CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0x00},
{ CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0x00},
{ CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0x00},
{ CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0x00},
{ CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0x00},
{ CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0x00},
{ CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0x00},
{ CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0x00},
{ CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0x00},
{ CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0x00},
{ CDC_TX_INP_MUX_ADC_MUX4_CFG1, 0x00},
{ CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0x00},
{ CDC_TX_INP_MUX_ADC_MUX5_CFG1, 0x00},
{ CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0x00},
{ CDC_TX_INP_MUX_ADC_MUX6_CFG1, 0x00},
{ CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0x00},
{ CDC_TX_INP_MUX_ADC_MUX7_CFG1, 0x00},
{ CDC_TX_ANC0_CLK_RESET_CTL, 0x00},
{ CDC_TX_ANC0_MODE_1_CTL, 0x00},
{ CDC_TX_ANC0_MODE_2_CTL, 0x00},
{ CDC_TX_ANC0_FF_SHIFT, 0x00},
{ CDC_TX_ANC0_FB_SHIFT, 0x00},
{ CDC_TX_ANC0_LPF_FF_A_CTL, 0x00},
{ CDC_TX_ANC0_LPF_FF_B_CTL, 0x00},
{ CDC_TX_ANC0_LPF_FB_CTL, 0x00},
{ CDC_TX_ANC0_SMLPF_CTL, 0x00},
{ CDC_TX_ANC0_DCFLT_SHIFT_CTL, 0x00},
{ CDC_TX_ANC0_IIR_ADAPT_CTL, 0x00},
{ CDC_TX_ANC0_IIR_COEFF_1_CTL, 0x00},
{ CDC_TX_ANC0_IIR_COEFF_2_CTL, 0x00},
{ CDC_TX_ANC0_FF_A_GAIN_CTL, 0x00},
{ CDC_TX_ANC0_FF_B_GAIN_CTL, 0x00},
{ CDC_TX_ANC0_FB_GAIN_CTL, 0x00},
{ CDC_TX0_TX_PATH_CTL, 0x04},
{ CDC_TX0_TX_PATH_CFG0, 0x10},
{ CDC_TX0_TX_PATH_CFG1, 0x0B},
{ CDC_TX0_TX_VOL_CTL, 0x00},
{ CDC_TX0_TX_PATH_SEC0, 0x00},
{ CDC_TX0_TX_PATH_SEC1, 0x00},
{ CDC_TX0_TX_PATH_SEC2, 0x01},
{ CDC_TX0_TX_PATH_SEC3, 0x3C},
{ CDC_TX0_TX_PATH_SEC4, 0x20},
{ CDC_TX0_TX_PATH_SEC5, 0x00},
{ CDC_TX0_TX_PATH_SEC6, 0x00},
{ CDC_TX0_TX_PATH_SEC7, 0x25},
{ CDC_TX1_TX_PATH_CTL, 0x04},
{ CDC_TX1_TX_PATH_CFG0, 0x10},
{ CDC_TX1_TX_PATH_CFG1, 0x0B},
{ CDC_TX1_TX_VOL_CTL, 0x00},
{ CDC_TX1_TX_PATH_SEC0, 0x00},
{ CDC_TX1_TX_PATH_SEC1, 0x00},
{ CDC_TX1_TX_PATH_SEC2, 0x01},
{ CDC_TX1_TX_PATH_SEC3, 0x3C},
{ CDC_TX1_TX_PATH_SEC4, 0x20},
{ CDC_TX1_TX_PATH_SEC5, 0x00},
{ CDC_TX1_TX_PATH_SEC6, 0x00},
{ CDC_TX2_TX_PATH_CTL, 0x04},
{ CDC_TX2_TX_PATH_CFG0, 0x10},
{ CDC_TX2_TX_PATH_CFG1, 0x0B},
{ CDC_TX2_TX_VOL_CTL, 0x00},
{ CDC_TX2_TX_PATH_SEC0, 0x00},
{ CDC_TX2_TX_PATH_SEC1, 0x00},
{ CDC_TX2_TX_PATH_SEC2, 0x01},
{ CDC_TX2_TX_PATH_SEC3, 0x3C},
{ CDC_TX2_TX_PATH_SEC4, 0x20},
{ CDC_TX2_TX_PATH_SEC5, 0x00},
{ CDC_TX2_TX_PATH_SEC6, 0x00},
{ CDC_TX3_TX_PATH_CTL, 0x04},
{ CDC_TX3_TX_PATH_CFG0, 0x10},
{ CDC_TX3_TX_PATH_CFG1, 0x0B},
{ CDC_TX3_TX_VOL_CTL, 0x00},
{ CDC_TX3_TX_PATH_SEC0, 0x00},
{ CDC_TX3_TX_PATH_SEC1, 0x00},
{ CDC_TX3_TX_PATH_SEC2, 0x01},
{ CDC_TX3_TX_PATH_SEC3, 0x3C},
{ CDC_TX3_TX_PATH_SEC4, 0x20},
{ CDC_TX3_TX_PATH_SEC5, 0x00},
{ CDC_TX3_TX_PATH_SEC6, 0x00},
{ CDC_TX4_TX_PATH_CTL, 0x04},
{ CDC_TX4_TX_PATH_CFG0, 0x10},
{ CDC_TX4_TX_PATH_CFG1, 0x0B},
{ CDC_TX4_TX_VOL_CTL, 0x00},
{ CDC_TX4_TX_PATH_SEC0, 0x00},
{ CDC_TX4_TX_PATH_SEC1, 0x00},
{ CDC_TX4_TX_PATH_SEC2, 0x01},
{ CDC_TX4_TX_PATH_SEC3, 0x3C},
{ CDC_TX4_TX_PATH_SEC4, 0x20},
{ CDC_TX4_TX_PATH_SEC5, 0x00},
{ CDC_TX4_TX_PATH_SEC6, 0x00},
{ CDC_TX5_TX_PATH_CTL, 0x04},
{ CDC_TX5_TX_PATH_CFG0, 0x10},
{ CDC_TX5_TX_PATH_CFG1, 0x0B},
{ CDC_TX5_TX_VOL_CTL, 0x00},
{ CDC_TX5_TX_PATH_SEC0, 0x00},
{ CDC_TX5_TX_PATH_SEC1, 0x00},
{ CDC_TX5_TX_PATH_SEC2, 0x01},
{ CDC_TX5_TX_PATH_SEC3, 0x3C},
{ CDC_TX5_TX_PATH_SEC4, 0x20},
{ CDC_TX5_TX_PATH_SEC5, 0x00},
{ CDC_TX5_TX_PATH_SEC6, 0x00},
{ CDC_TX6_TX_PATH_CTL, 0x04},
{ CDC_TX6_TX_PATH_CFG0, 0x10},
{ CDC_TX6_TX_PATH_CFG1, 0x0B},
{ CDC_TX6_TX_VOL_CTL, 0x00},
{ CDC_TX6_TX_PATH_SEC0, 0x00},
{ CDC_TX6_TX_PATH_SEC1, 0x00},
{ CDC_TX6_TX_PATH_SEC2, 0x01},
{ CDC_TX6_TX_PATH_SEC3, 0x3C},
{ CDC_TX6_TX_PATH_SEC4, 0x20},
{ CDC_TX6_TX_PATH_SEC5, 0x00},
{ CDC_TX6_TX_PATH_SEC6, 0x00},
{ CDC_TX7_TX_PATH_CTL, 0x04},
{ CDC_TX7_TX_PATH_CFG0, 0x10},
{ CDC_TX7_TX_PATH_CFG1, 0x0B},
{ CDC_TX7_TX_VOL_CTL, 0x00},
{ CDC_TX7_TX_PATH_SEC0, 0x00},
{ CDC_TX7_TX_PATH_SEC1, 0x00},
{ CDC_TX7_TX_PATH_SEC2, 0x01},
{ CDC_TX7_TX_PATH_SEC3, 0x3C},
{ CDC_TX7_TX_PATH_SEC4, 0x20},
{ CDC_TX7_TX_PATH_SEC5, 0x00},
{ CDC_TX7_TX_PATH_SEC6, 0x00},
};
static bool tx_is_volatile_register(struct device *dev, unsigned int reg)
{
/* Update volatile list for tx/tx macros */
switch (reg) {
case CDC_TX_TOP_CSR_SWR_DMIC0_CTL:
case CDC_TX_TOP_CSR_SWR_DMIC1_CTL:
case CDC_TX_TOP_CSR_SWR_DMIC2_CTL:
case CDC_TX_TOP_CSR_SWR_DMIC3_CTL:
return true;
}
return false;
}
static bool tx_is_rw_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CDC_TX_CLK_RST_CTRL_MCLK_CONTROL:
case CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL:
case CDC_TX_CLK_RST_CTRL_SWR_CONTROL:
case CDC_TX_TOP_CSR_TOP_CFG0:
case CDC_TX_TOP_CSR_ANC_CFG:
case CDC_TX_TOP_CSR_SWR_CTRL:
case CDC_TX_TOP_CSR_FREQ_MCLK:
case CDC_TX_TOP_CSR_DEBUG_BUS:
case CDC_TX_TOP_CSR_DEBUG_EN:
case CDC_TX_TOP_CSR_TX_I2S_CTL:
case CDC_TX_TOP_CSR_I2S_CLK:
case CDC_TX_TOP_CSR_I2S_RESET:
case CDC_TX_TOP_CSR_SWR_DMIC0_CTL:
case CDC_TX_TOP_CSR_SWR_DMIC1_CTL:
case CDC_TX_TOP_CSR_SWR_DMIC2_CTL:
case CDC_TX_TOP_CSR_SWR_DMIC3_CTL:
case CDC_TX_TOP_CSR_SWR_AMIC0_CTL:
case CDC_TX_TOP_CSR_SWR_AMIC1_CTL:
case CDC_TX_ANC0_CLK_RESET_CTL:
case CDC_TX_ANC0_MODE_1_CTL:
case CDC_TX_ANC0_MODE_2_CTL:
case CDC_TX_ANC0_FF_SHIFT:
case CDC_TX_ANC0_FB_SHIFT:
case CDC_TX_ANC0_LPF_FF_A_CTL:
case CDC_TX_ANC0_LPF_FF_B_CTL:
case CDC_TX_ANC0_LPF_FB_CTL:
case CDC_TX_ANC0_SMLPF_CTL:
case CDC_TX_ANC0_DCFLT_SHIFT_CTL:
case CDC_TX_ANC0_IIR_ADAPT_CTL:
case CDC_TX_ANC0_IIR_COEFF_1_CTL:
case CDC_TX_ANC0_IIR_COEFF_2_CTL:
case CDC_TX_ANC0_FF_A_GAIN_CTL:
case CDC_TX_ANC0_FF_B_GAIN_CTL:
case CDC_TX_ANC0_FB_GAIN_CTL:
case CDC_TX_INP_MUX_ADC_MUX0_CFG0:
case CDC_TX_INP_MUX_ADC_MUX0_CFG1:
case CDC_TX_INP_MUX_ADC_MUX1_CFG0:
case CDC_TX_INP_MUX_ADC_MUX1_CFG1:
case CDC_TX_INP_MUX_ADC_MUX2_CFG0:
case CDC_TX_INP_MUX_ADC_MUX2_CFG1:
case CDC_TX_INP_MUX_ADC_MUX3_CFG0:
case CDC_TX_INP_MUX_ADC_MUX3_CFG1:
case CDC_TX_INP_MUX_ADC_MUX4_CFG0:
case CDC_TX_INP_MUX_ADC_MUX4_CFG1:
case CDC_TX_INP_MUX_ADC_MUX5_CFG0:
case CDC_TX_INP_MUX_ADC_MUX5_CFG1:
case CDC_TX_INP_MUX_ADC_MUX6_CFG0:
case CDC_TX_INP_MUX_ADC_MUX6_CFG1:
case CDC_TX_INP_MUX_ADC_MUX7_CFG0:
case CDC_TX_INP_MUX_ADC_MUX7_CFG1:
case CDC_TX0_TX_PATH_CTL:
case CDC_TX0_TX_PATH_CFG0:
case CDC_TX0_TX_PATH_CFG1:
case CDC_TX0_TX_VOL_CTL:
case CDC_TX0_TX_PATH_SEC0:
case CDC_TX0_TX_PATH_SEC1:
case CDC_TX0_TX_PATH_SEC2:
case CDC_TX0_TX_PATH_SEC3:
case CDC_TX0_TX_PATH_SEC4:
case CDC_TX0_TX_PATH_SEC5:
case CDC_TX0_TX_PATH_SEC6:
case CDC_TX0_TX_PATH_SEC7:
case CDC_TX1_TX_PATH_CTL:
case CDC_TX1_TX_PATH_CFG0:
case CDC_TX1_TX_PATH_CFG1:
case CDC_TX1_TX_VOL_CTL:
case CDC_TX1_TX_PATH_SEC0:
case CDC_TX1_TX_PATH_SEC1:
case CDC_TX1_TX_PATH_SEC2:
case CDC_TX1_TX_PATH_SEC3:
case CDC_TX1_TX_PATH_SEC4:
case CDC_TX1_TX_PATH_SEC5:
case CDC_TX1_TX_PATH_SEC6:
case CDC_TX2_TX_PATH_CTL:
case CDC_TX2_TX_PATH_CFG0:
case CDC_TX2_TX_PATH_CFG1:
case CDC_TX2_TX_VOL_CTL:
case CDC_TX2_TX_PATH_SEC0:
case CDC_TX2_TX_PATH_SEC1:
case CDC_TX2_TX_PATH_SEC2:
case CDC_TX2_TX_PATH_SEC3:
case CDC_TX2_TX_PATH_SEC4:
case CDC_TX2_TX_PATH_SEC5:
case CDC_TX2_TX_PATH_SEC6:
case CDC_TX3_TX_PATH_CTL:
case CDC_TX3_TX_PATH_CFG0:
case CDC_TX3_TX_PATH_CFG1:
case CDC_TX3_TX_VOL_CTL:
case CDC_TX3_TX_PATH_SEC0:
case CDC_TX3_TX_PATH_SEC1:
case CDC_TX3_TX_PATH_SEC2:
case CDC_TX3_TX_PATH_SEC3:
case CDC_TX3_TX_PATH_SEC4:
case CDC_TX3_TX_PATH_SEC5:
case CDC_TX3_TX_PATH_SEC6:
case CDC_TX4_TX_PATH_CTL:
case CDC_TX4_TX_PATH_CFG0:
case CDC_TX4_TX_PATH_CFG1:
case CDC_TX4_TX_VOL_CTL:
case CDC_TX4_TX_PATH_SEC0:
case CDC_TX4_TX_PATH_SEC1:
case CDC_TX4_TX_PATH_SEC2:
case CDC_TX4_TX_PATH_SEC3:
case CDC_TX4_TX_PATH_SEC4:
case CDC_TX4_TX_PATH_SEC5:
case CDC_TX4_TX_PATH_SEC6:
case CDC_TX5_TX_PATH_CTL:
case CDC_TX5_TX_PATH_CFG0:
case CDC_TX5_TX_PATH_CFG1:
case CDC_TX5_TX_VOL_CTL:
case CDC_TX5_TX_PATH_SEC0:
case CDC_TX5_TX_PATH_SEC1:
case CDC_TX5_TX_PATH_SEC2:
case CDC_TX5_TX_PATH_SEC3:
case CDC_TX5_TX_PATH_SEC4:
case CDC_TX5_TX_PATH_SEC5:
case CDC_TX5_TX_PATH_SEC6:
case CDC_TX6_TX_PATH_CTL:
case CDC_TX6_TX_PATH_CFG0:
case CDC_TX6_TX_PATH_CFG1:
case CDC_TX6_TX_VOL_CTL:
case CDC_TX6_TX_PATH_SEC0:
case CDC_TX6_TX_PATH_SEC1:
case CDC_TX6_TX_PATH_SEC2:
case CDC_TX6_TX_PATH_SEC3:
case CDC_TX6_TX_PATH_SEC4:
case CDC_TX6_TX_PATH_SEC5:
case CDC_TX6_TX_PATH_SEC6:
case CDC_TX7_TX_PATH_CTL:
case CDC_TX7_TX_PATH_CFG0:
case CDC_TX7_TX_PATH_CFG1:
case CDC_TX7_TX_VOL_CTL:
case CDC_TX7_TX_PATH_SEC0:
case CDC_TX7_TX_PATH_SEC1:
case CDC_TX7_TX_PATH_SEC2:
case CDC_TX7_TX_PATH_SEC3:
case CDC_TX7_TX_PATH_SEC4:
case CDC_TX7_TX_PATH_SEC5:
case CDC_TX7_TX_PATH_SEC6:
return true;
}
return false;
}
static const struct regmap_config tx_regmap_config = {
.name = "tx_macro",
.reg_bits = 16,
.val_bits = 32,
.reg_stride = 4,
.cache_type = REGCACHE_FLAT,
.max_register = TX_MAX_OFFSET,
.reg_defaults = tx_defaults,
.num_reg_defaults = ARRAY_SIZE(tx_defaults),
.writeable_reg = tx_is_rw_register,
.volatile_reg = tx_is_volatile_register,
.readable_reg = tx_is_rw_register,
};
static int tx_macro_mclk_enable(struct tx_macro *tx,
bool mclk_enable)
{
struct regmap *regmap = tx->regmap;
if (mclk_enable) {
if (tx->tx_mclk_users == 0) {
/* 9.6MHz MCLK, set value 0x00 if other frequency */
regmap_update_bits(regmap, CDC_TX_TOP_CSR_FREQ_MCLK, 0x01, 0x01);
regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_MCLK_CONTROL,
CDC_TX_MCLK_EN_MASK,
CDC_TX_MCLK_ENABLE);
regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL,
CDC_TX_FS_CNT_EN_MASK,
CDC_TX_FS_CNT_ENABLE);
regcache_mark_dirty(regmap);
regcache_sync(regmap);
}
tx->tx_mclk_users++;
} else {
if (tx->tx_mclk_users <= 0) {
dev_err(tx->dev, "clock already disabled\n");
tx->tx_mclk_users = 0;
goto exit;
}
tx->tx_mclk_users--;
if (tx->tx_mclk_users == 0) {
regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL,
CDC_TX_FS_CNT_EN_MASK, 0x0);
regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_MCLK_CONTROL,
CDC_TX_MCLK_EN_MASK, 0x0);
}
}
exit:
return 0;
}
static bool is_amic_enabled(struct snd_soc_component *component, u8 decimator)
{
u16 adc_mux_reg, adc_reg, adc_n;
adc_mux_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG1(decimator);
if (snd_soc_component_read(component, adc_mux_reg) & SWR_MIC) {
adc_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG0(decimator);
adc_n = snd_soc_component_read_field(component, adc_reg,
CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK);
if (adc_n < TX_ADC_MAX)
return true;
}
return false;
}
static void tx_macro_tx_hpf_corner_freq_callback(struct work_struct *work)
{
struct delayed_work *hpf_delayed_work;
struct hpf_work *hpf_work;
struct tx_macro *tx;
struct snd_soc_component *component;
u16 dec_cfg_reg, hpf_gate_reg;
u8 hpf_cut_off_freq;
hpf_delayed_work = to_delayed_work(work);
hpf_work = container_of(hpf_delayed_work, struct hpf_work, dwork);
tx = hpf_work->tx;
component = tx->component;
hpf_cut_off_freq = hpf_work->hpf_cut_off_freq;
dec_cfg_reg = CDC_TXn_TX_PATH_CFG0(hpf_work->decimator);
hpf_gate_reg = CDC_TXn_TX_PATH_SEC2(hpf_work->decimator);
if (is_amic_enabled(component, hpf_work->decimator)) {
snd_soc_component_write_field(component,
dec_cfg_reg,
CDC_TXn_HPF_CUT_FREQ_MASK,
hpf_cut_off_freq);
snd_soc_component_update_bits(component, hpf_gate_reg,
CDC_TXn_HPF_F_CHANGE_MASK |
CDC_TXn_HPF_ZERO_GATE_MASK,
0x02);
snd_soc_component_update_bits(component, hpf_gate_reg,
CDC_TXn_HPF_F_CHANGE_MASK |
CDC_TXn_HPF_ZERO_GATE_MASK,
0x01);
} else {
snd_soc_component_write_field(component, dec_cfg_reg,
CDC_TXn_HPF_CUT_FREQ_MASK,
hpf_cut_off_freq);
snd_soc_component_write_field(component, hpf_gate_reg,
CDC_TXn_HPF_F_CHANGE_MASK, 0x1);
/* Minimum 1 clk cycle delay is required as per HW spec */
usleep_range(1000, 1010);
snd_soc_component_write_field(component, hpf_gate_reg,
CDC_TXn_HPF_F_CHANGE_MASK, 0x0);
}
}
static void tx_macro_mute_update_callback(struct work_struct *work)
{
struct tx_mute_work *tx_mute_dwork;
struct snd_soc_component *component;
struct tx_macro *tx;
struct delayed_work *delayed_work;
u8 decimator;
delayed_work = to_delayed_work(work);
tx_mute_dwork = container_of(delayed_work, struct tx_mute_work, dwork);
tx = tx_mute_dwork->tx;
component = tx->component;
decimator = tx_mute_dwork->decimator;
snd_soc_component_write_field(component, CDC_TXn_TX_PATH_CTL(decimator),
CDC_TXn_PGA_MUTE_MASK, 0x0);
}
static int tx_macro_mclk_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct tx_macro *tx = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
tx_macro_mclk_enable(tx, true);
break;
case SND_SOC_DAPM_POST_PMD:
tx_macro_mclk_enable(tx, false);
break;
default:
break;
}
return 0;
}
static int tx_macro_put_dec_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int val, dmic;
u16 mic_sel_reg;
u16 dmic_clk_reg;
struct tx_macro *tx = snd_soc_component_get_drvdata(component);
val = ucontrol->value.enumerated.item[0];
if (val >= e->items)
return -EINVAL;
switch (e->reg) {
case CDC_TX_INP_MUX_ADC_MUX0_CFG0:
mic_sel_reg = CDC_TX0_TX_PATH_CFG0;
break;
case CDC_TX_INP_MUX_ADC_MUX1_CFG0:
mic_sel_reg = CDC_TX1_TX_PATH_CFG0;
break;
case CDC_TX_INP_MUX_ADC_MUX2_CFG0:
mic_sel_reg = CDC_TX2_TX_PATH_CFG0;
break;
case CDC_TX_INP_MUX_ADC_MUX3_CFG0:
mic_sel_reg = CDC_TX3_TX_PATH_CFG0;
break;
case CDC_TX_INP_MUX_ADC_MUX4_CFG0:
mic_sel_reg = CDC_TX4_TX_PATH_CFG0;
break;
case CDC_TX_INP_MUX_ADC_MUX5_CFG0:
mic_sel_reg = CDC_TX5_TX_PATH_CFG0;
break;
case CDC_TX_INP_MUX_ADC_MUX6_CFG0:
mic_sel_reg = CDC_TX6_TX_PATH_CFG0;
break;
case CDC_TX_INP_MUX_ADC_MUX7_CFG0:
mic_sel_reg = CDC_TX7_TX_PATH_CFG0;
break;
default:
dev_err(component->dev, "Error in configuration!!\n");
return -EINVAL;
}
if (val != 0) {
if (widget->shift) { /* MSM DMIC */
snd_soc_component_write_field(component, mic_sel_reg,
CDC_TXn_ADC_DMIC_SEL_MASK, 1);
} else if (val < 5) {
snd_soc_component_write_field(component, mic_sel_reg,
CDC_TXn_ADC_DMIC_SEL_MASK, 0);
} else {
snd_soc_component_write_field(component, mic_sel_reg,
CDC_TXn_ADC_DMIC_SEL_MASK, 1);
dmic = TX_ADC_TO_DMIC(val);
dmic_clk_reg = CDC_TX_TOP_CSR_SWR_DMICn_CTL(dmic);
snd_soc_component_write_field(component, dmic_clk_reg,
CDC_TX_SWR_DMIC_CLK_SEL_MASK,
tx->dmic_clk_div);
}
}
return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
}
static int tx_macro_tx_mixer_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value;
u32 dai_id = widget->shift;
u32 dec_id = mc->shift;
struct tx_macro *tx = snd_soc_component_get_drvdata(component);
if (test_bit(dec_id, &tx->active_ch_mask[dai_id]))
ucontrol->value.integer.value[0] = 1;
else
ucontrol->value.integer.value[0] = 0;
return 0;
}
static int tx_macro_tx_mixer_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
struct snd_soc_dapm_update *update = NULL;
struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value;
u32 dai_id = widget->shift;
u32 dec_id = mc->shift;
u32 enable = ucontrol->value.integer.value[0];
struct tx_macro *tx = snd_soc_component_get_drvdata(component);
if (enable) {
if (tx->active_decimator[dai_id] == dec_id)
return 0;
set_bit(dec_id, &tx->active_ch_mask[dai_id]);
tx->active_ch_cnt[dai_id]++;
tx->active_decimator[dai_id] = dec_id;
} else {
if (tx->active_decimator[dai_id] == -1)
return 0;
tx->active_ch_cnt[dai_id]--;
clear_bit(dec_id, &tx->active_ch_mask[dai_id]);
tx->active_decimator[dai_id] = -1;
}
snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, update);
return 1;
}
static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
u8 decimator;
u16 tx_vol_ctl_reg, dec_cfg_reg, hpf_gate_reg, tx_gain_ctl_reg;
u8 hpf_cut_off_freq;
int hpf_delay = TX_MACRO_DMIC_HPF_DELAY_MS;
int unmute_delay = TX_MACRO_DMIC_UNMUTE_DELAY_MS;
u16 adc_mux_reg, adc_reg, adc_n, dmic;
u16 dmic_clk_reg;
struct tx_macro *tx = snd_soc_component_get_drvdata(component);
decimator = w->shift;
tx_vol_ctl_reg = CDC_TXn_TX_PATH_CTL(decimator);
hpf_gate_reg = CDC_TXn_TX_PATH_SEC2(decimator);
dec_cfg_reg = CDC_TXn_TX_PATH_CFG0(decimator);
tx_gain_ctl_reg = CDC_TXn_TX_VOL_CTL(decimator);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
adc_mux_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG1(decimator);
if (snd_soc_component_read(component, adc_mux_reg) & SWR_MIC) {
adc_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG0(decimator);
adc_n = snd_soc_component_read(component, adc_reg) &
CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK;
if (adc_n >= TX_ADC_MAX) {
dmic = TX_ADC_TO_DMIC(adc_n);
dmic_clk_reg = CDC_TX_TOP_CSR_SWR_DMICn_CTL(dmic);
snd_soc_component_write_field(component, dmic_clk_reg,
CDC_TX_SWR_DMIC_CLK_SEL_MASK,
tx->dmic_clk_div);
}
}
snd_soc_component_write_field(component, dec_cfg_reg,
CDC_TXn_ADC_MODE_MASK,
tx->dec_mode[decimator]);
/* Enable TX PGA Mute */
snd_soc_component_write_field(component, tx_vol_ctl_reg,
CDC_TXn_PGA_MUTE_MASK, 0x1);
break;
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_write_field(component, tx_vol_ctl_reg,
CDC_TXn_CLK_EN_MASK, 0x1);
if (!is_amic_enabled(component, decimator)) {
snd_soc_component_update_bits(component, hpf_gate_reg, 0x01, 0x00);
/* Minimum 1 clk cycle delay is required as per HW spec */
usleep_range(1000, 1010);
}
hpf_cut_off_freq = snd_soc_component_read_field(component, dec_cfg_reg,
CDC_TXn_HPF_CUT_FREQ_MASK);
tx->tx_hpf_work[decimator].hpf_cut_off_freq =
hpf_cut_off_freq;
if (hpf_cut_off_freq != CF_MIN_3DB_150HZ)
snd_soc_component_write_field(component, dec_cfg_reg,
CDC_TXn_HPF_CUT_FREQ_MASK,
CF_MIN_3DB_150HZ);
if (is_amic_enabled(component, decimator)) {
hpf_delay = TX_MACRO_AMIC_HPF_DELAY_MS;
unmute_delay = TX_MACRO_AMIC_UNMUTE_DELAY_MS;
}
/* schedule work queue to Remove Mute */
queue_delayed_work(system_freezable_wq,
&tx->tx_mute_dwork[decimator].dwork,
msecs_to_jiffies(unmute_delay));
if (tx->tx_hpf_work[decimator].hpf_cut_off_freq != CF_MIN_3DB_150HZ) {
queue_delayed_work(system_freezable_wq,
&tx->tx_hpf_work[decimator].dwork,
msecs_to_jiffies(hpf_delay));
snd_soc_component_update_bits(component, hpf_gate_reg,
CDC_TXn_HPF_F_CHANGE_MASK |
CDC_TXn_HPF_ZERO_GATE_MASK,
0x02);
if (!is_amic_enabled(component, decimator))
snd_soc_component_update_bits(component, hpf_gate_reg,
CDC_TXn_HPF_F_CHANGE_MASK |
CDC_TXn_HPF_ZERO_GATE_MASK,
0x00);
snd_soc_component_update_bits(component, hpf_gate_reg,
CDC_TXn_HPF_F_CHANGE_MASK |
CDC_TXn_HPF_ZERO_GATE_MASK,
0x01);
/*
* 6ms delay is required as per HW spec
*/
usleep_range(6000, 6010);
}
/* apply gain after decimator is enabled */
snd_soc_component_write(component, tx_gain_ctl_reg,
snd_soc_component_read(component,
tx_gain_ctl_reg));
if (tx->bcs_enable) {
snd_soc_component_update_bits(component, dec_cfg_reg,
0x01, 0x01);
tx->bcs_clk_en = true;
}
break;
case SND_SOC_DAPM_PRE_PMD:
hpf_cut_off_freq =
tx->tx_hpf_work[decimator].hpf_cut_off_freq;
snd_soc_component_write_field(component, tx_vol_ctl_reg,
CDC_TXn_PGA_MUTE_MASK, 0x1);
if (cancel_delayed_work_sync(
&tx->tx_hpf_work[decimator].dwork)) {
if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) {
snd_soc_component_write_field(
component, dec_cfg_reg,
CDC_TXn_HPF_CUT_FREQ_MASK,
hpf_cut_off_freq);
if (is_amic_enabled(component, decimator))
snd_soc_component_update_bits(component,
hpf_gate_reg,
CDC_TXn_HPF_F_CHANGE_MASK |
CDC_TXn_HPF_ZERO_GATE_MASK,
0x02);
else
snd_soc_component_update_bits(component,
hpf_gate_reg,
CDC_TXn_HPF_F_CHANGE_MASK |
CDC_TXn_HPF_ZERO_GATE_MASK,
0x03);
/*
* Minimum 1 clk cycle delay is required
* as per HW spec
*/
usleep_range(1000, 1010);
snd_soc_component_update_bits(component, hpf_gate_reg,
CDC_TXn_HPF_F_CHANGE_MASK |
CDC_TXn_HPF_ZERO_GATE_MASK,
0x1);
}
}
cancel_delayed_work_sync(&tx->tx_mute_dwork[decimator].dwork);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_write_field(component, tx_vol_ctl_reg,
CDC_TXn_CLK_EN_MASK, 0x0);
snd_soc_component_write_field(component, dec_cfg_reg,
CDC_TXn_ADC_MODE_MASK, 0x0);
snd_soc_component_write_field(component, tx_vol_ctl_reg,
CDC_TXn_PGA_MUTE_MASK, 0x0);
if (tx->bcs_enable) {
snd_soc_component_write_field(component, dec_cfg_reg,
CDC_TXn_PH_EN_MASK, 0x0);
snd_soc_component_write_field(component,
CDC_TX0_TX_PATH_SEC7,
CDC_TX0_MBHC_CTL_EN_MASK,
0x0);
tx->bcs_clk_en = false;
}
break;
}
return 0;
}
static int tx_macro_dec_mode_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct tx_macro *tx = snd_soc_component_get_drvdata(component);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
int path = e->shift_l;
ucontrol->value.integer.value[0] = tx->dec_mode[path];
return 0;
}
static int tx_macro_dec_mode_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
int value = ucontrol->value.integer.value[0];
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
int path = e->shift_l;
struct tx_macro *tx = snd_soc_component_get_drvdata(component);
if (tx->dec_mode[path] == value)
return 0;
tx->dec_mode[path] = value;
return 1;
}
static int tx_macro_get_bcs(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct tx_macro *tx = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = tx->bcs_enable;
return 0;
}
static int tx_macro_set_bcs(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
int value = ucontrol->value.integer.value[0];
struct tx_macro *tx = snd_soc_component_get_drvdata(component);
tx->bcs_enable = value;
return 0;
}
static int tx_macro_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
u32 sample_rate;
u8 decimator;
int tx_fs_rate;
struct tx_macro *tx = snd_soc_component_get_drvdata(component);
sample_rate = params_rate(params);
switch (sample_rate) {
case 8000:
tx_fs_rate = 0;
break;
case 16000:
tx_fs_rate = 1;
break;
case 32000:
tx_fs_rate = 3;
break;
case 48000:
tx_fs_rate = 4;
break;
case 96000:
tx_fs_rate = 5;
break;
case 192000:
tx_fs_rate = 6;
break;
case 384000:
tx_fs_rate = 7;
break;
default:
dev_err(component->dev, "%s: Invalid TX sample rate: %d\n",
__func__, params_rate(params));
return -EINVAL;
}
for_each_set_bit(decimator, &tx->active_ch_mask[dai->id], TX_MACRO_DEC_MAX)
snd_soc_component_update_bits(component, CDC_TXn_TX_PATH_CTL(decimator),
CDC_TXn_PCM_RATE_MASK,
tx_fs_rate);
return 0;
}
static int tx_macro_get_channel_map(struct snd_soc_dai *dai,
unsigned int *tx_num, unsigned int *tx_slot,
unsigned int *rx_num, unsigned int *rx_slot)
{
struct snd_soc_component *component = dai->component;
struct tx_macro *tx = snd_soc_component_get_drvdata(component);
switch (dai->id) {
case TX_MACRO_AIF1_CAP:
case TX_MACRO_AIF2_CAP:
case TX_MACRO_AIF3_CAP:
*tx_slot = tx->active_ch_mask[dai->id];
*tx_num = tx->active_ch_cnt[dai->id];
break;
default:
break;
}
return 0;
}
static int tx_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
{
struct snd_soc_component *component = dai->component;
struct tx_macro *tx = snd_soc_component_get_drvdata(component);
u8 decimator;
/* active decimator not set yet */
if (tx->active_decimator[dai->id] == -1)
return 0;
decimator = tx->active_decimator[dai->id];
if (mute)
snd_soc_component_write_field(component,
CDC_TXn_TX_PATH_CTL(decimator),
CDC_TXn_PGA_MUTE_MASK, 0x1);
else
snd_soc_component_update_bits(component,
CDC_TXn_TX_PATH_CTL(decimator),
CDC_TXn_PGA_MUTE_MASK, 0x0);
return 0;
}
static const struct snd_soc_dai_ops tx_macro_dai_ops = {
.hw_params = tx_macro_hw_params,
.get_channel_map = tx_macro_get_channel_map,
.mute_stream = tx_macro_digital_mute,
};
static struct snd_soc_dai_driver tx_macro_dai[] = {
{
.name = "tx_macro_tx1",
.id = TX_MACRO_AIF1_CAP,
.capture = {
.stream_name = "TX_AIF1 Capture",
.rates = TX_MACRO_RATES,
.formats = TX_MACRO_FORMATS,
.rate_max = 192000,
.rate_min = 8000,
.channels_min = 1,
.channels_max = 8,
},
.ops = &tx_macro_dai_ops,
},
{
.name = "tx_macro_tx2",
.id = TX_MACRO_AIF2_CAP,
.capture = {
.stream_name = "TX_AIF2 Capture",
.rates = TX_MACRO_RATES,
.formats = TX_MACRO_FORMATS,
.rate_max = 192000,
.rate_min = 8000,
.channels_min = 1,
.channels_max = 8,
},
.ops = &tx_macro_dai_ops,
},
{
.name = "tx_macro_tx3",
.id = TX_MACRO_AIF3_CAP,
.capture = {
.stream_name = "TX_AIF3 Capture",
.rates = TX_MACRO_RATES,
.formats = TX_MACRO_FORMATS,
.rate_max = 192000,
.rate_min = 8000,
.channels_min = 1,
.channels_max = 8,
},
.ops = &tx_macro_dai_ops,
},
};
static const char * const adc_mux_text[] = {
"MSM_DMIC", "SWR_MIC", "ANC_FB_TUNE1"
};
static SOC_ENUM_SINGLE_DECL(tx_dec0_enum, CDC_TX_INP_MUX_ADC_MUX0_CFG1,
0, adc_mux_text);
static SOC_ENUM_SINGLE_DECL(tx_dec1_enum, CDC_TX_INP_MUX_ADC_MUX1_CFG1,
0, adc_mux_text);
static SOC_ENUM_SINGLE_DECL(tx_dec2_enum, CDC_TX_INP_MUX_ADC_MUX2_CFG1,
0, adc_mux_text);
static SOC_ENUM_SINGLE_DECL(tx_dec3_enum, CDC_TX_INP_MUX_ADC_MUX3_CFG1,
0, adc_mux_text);
static SOC_ENUM_SINGLE_DECL(tx_dec4_enum, CDC_TX_INP_MUX_ADC_MUX4_CFG1,
0, adc_mux_text);
static SOC_ENUM_SINGLE_DECL(tx_dec5_enum, CDC_TX_INP_MUX_ADC_MUX5_CFG1,
0, adc_mux_text);
static SOC_ENUM_SINGLE_DECL(tx_dec6_enum, CDC_TX_INP_MUX_ADC_MUX6_CFG1,
0, adc_mux_text);
static SOC_ENUM_SINGLE_DECL(tx_dec7_enum, CDC_TX_INP_MUX_ADC_MUX7_CFG1,
0, adc_mux_text);
static const struct snd_kcontrol_new tx_dec0_mux = SOC_DAPM_ENUM("tx_dec0", tx_dec0_enum);
static const struct snd_kcontrol_new tx_dec1_mux = SOC_DAPM_ENUM("tx_dec1", tx_dec1_enum);
static const struct snd_kcontrol_new tx_dec2_mux = SOC_DAPM_ENUM("tx_dec2", tx_dec2_enum);
static const struct snd_kcontrol_new tx_dec3_mux = SOC_DAPM_ENUM("tx_dec3", tx_dec3_enum);
static const struct snd_kcontrol_new tx_dec4_mux = SOC_DAPM_ENUM("tx_dec4", tx_dec4_enum);
static const struct snd_kcontrol_new tx_dec5_mux = SOC_DAPM_ENUM("tx_dec5", tx_dec5_enum);
static const struct snd_kcontrol_new tx_dec6_mux = SOC_DAPM_ENUM("tx_dec6", tx_dec6_enum);
static const struct snd_kcontrol_new tx_dec7_mux = SOC_DAPM_ENUM("tx_dec7", tx_dec7_enum);
static const char * const smic_mux_text[] = {
"ZERO", "ADC0", "ADC1", "ADC2", "ADC3", "SWR_DMIC0",
"SWR_DMIC1", "SWR_DMIC2", "SWR_DMIC3", "SWR_DMIC4",
"SWR_DMIC5", "SWR_DMIC6", "SWR_DMIC7"
};
static SOC_ENUM_SINGLE_DECL(tx_smic0_enum, CDC_TX_INP_MUX_ADC_MUX0_CFG0,
0, smic_mux_text);
static SOC_ENUM_SINGLE_DECL(tx_smic1_enum, CDC_TX_INP_MUX_ADC_MUX1_CFG0,
0, smic_mux_text);
static SOC_ENUM_SINGLE_DECL(tx_smic2_enum, CDC_TX_INP_MUX_ADC_MUX2_CFG0,
0, smic_mux_text);
static SOC_ENUM_SINGLE_DECL(tx_smic3_enum, CDC_TX_INP_MUX_ADC_MUX3_CFG0,
0, smic_mux_text);
static SOC_ENUM_SINGLE_DECL(tx_smic4_enum, CDC_TX_INP_MUX_ADC_MUX4_CFG0,
0, smic_mux_text);
static SOC_ENUM_SINGLE_DECL(tx_smic5_enum, CDC_TX_INP_MUX_ADC_MUX5_CFG0,
0, smic_mux_text);
static SOC_ENUM_SINGLE_DECL(tx_smic6_enum, CDC_TX_INP_MUX_ADC_MUX6_CFG0,
0, smic_mux_text);
static SOC_ENUM_SINGLE_DECL(tx_smic7_enum, CDC_TX_INP_MUX_ADC_MUX7_CFG0,
0, smic_mux_text);
static const struct snd_kcontrol_new tx_smic0_mux = SOC_DAPM_ENUM_EXT("tx_smic0", tx_smic0_enum,
snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
static const struct snd_kcontrol_new tx_smic1_mux = SOC_DAPM_ENUM_EXT("tx_smic1", tx_smic1_enum,
snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
static const struct snd_kcontrol_new tx_smic2_mux = SOC_DAPM_ENUM_EXT("tx_smic2", tx_smic2_enum,
snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
static const struct snd_kcontrol_new tx_smic3_mux = SOC_DAPM_ENUM_EXT("tx_smic3", tx_smic3_enum,
snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
static const struct snd_kcontrol_new tx_smic4_mux = SOC_DAPM_ENUM_EXT("tx_smic4", tx_smic4_enum,
snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
static const struct snd_kcontrol_new tx_smic5_mux = SOC_DAPM_ENUM_EXT("tx_smic5", tx_smic5_enum,
snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
static const struct snd_kcontrol_new tx_smic6_mux = SOC_DAPM_ENUM_EXT("tx_smic6", tx_smic6_enum,
snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
static const struct snd_kcontrol_new tx_smic7_mux = SOC_DAPM_ENUM_EXT("tx_smic7", tx_smic7_enum,
snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
static const char * const dmic_mux_text[] = {
"ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3",
"DMIC4", "DMIC5", "DMIC6", "DMIC7"
};
static SOC_ENUM_SINGLE_DECL(tx_dmic0_enum, CDC_TX_INP_MUX_ADC_MUX0_CFG0,
4, dmic_mux_text);
static SOC_ENUM_SINGLE_DECL(tx_dmic1_enum, CDC_TX_INP_MUX_ADC_MUX1_CFG0,
4, dmic_mux_text);
static SOC_ENUM_SINGLE_DECL(tx_dmic2_enum, CDC_TX_INP_MUX_ADC_MUX2_CFG0,
4, dmic_mux_text);
static SOC_ENUM_SINGLE_DECL(tx_dmic3_enum, CDC_TX_INP_MUX_ADC_MUX3_CFG0,
4, dmic_mux_text);
static SOC_ENUM_SINGLE_DECL(tx_dmic4_enum, CDC_TX_INP_MUX_ADC_MUX4_CFG0,
4, dmic_mux_text);
static SOC_ENUM_SINGLE_DECL(tx_dmic5_enum, CDC_TX_INP_MUX_ADC_MUX5_CFG0,
4, dmic_mux_text);
static SOC_ENUM_SINGLE_DECL(tx_dmic6_enum, CDC_TX_INP_MUX_ADC_MUX6_CFG0,
4, dmic_mux_text);
static SOC_ENUM_SINGLE_DECL(tx_dmic7_enum, CDC_TX_INP_MUX_ADC_MUX7_CFG0,
4, dmic_mux_text);
static const struct snd_kcontrol_new tx_dmic0_mux = SOC_DAPM_ENUM_EXT("tx_dmic0", tx_dmic0_enum,
snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
static const struct snd_kcontrol_new tx_dmic1_mux = SOC_DAPM_ENUM_EXT("tx_dmic1", tx_dmic1_enum,
snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
static const struct snd_kcontrol_new tx_dmic2_mux = SOC_DAPM_ENUM_EXT("tx_dmic2", tx_dmic2_enum,
snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
static const struct snd_kcontrol_new tx_dmic3_mux = SOC_DAPM_ENUM_EXT("tx_dmic3", tx_dmic3_enum,
snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
static const struct snd_kcontrol_new tx_dmic4_mux = SOC_DAPM_ENUM_EXT("tx_dmic4", tx_dmic4_enum,
snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
static const struct snd_kcontrol_new tx_dmic5_mux = SOC_DAPM_ENUM_EXT("tx_dmic5", tx_dmic5_enum,
snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
static const struct snd_kcontrol_new tx_dmic6_mux = SOC_DAPM_ENUM_EXT("tx_dmic6", tx_dmic6_enum,
snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
static const struct snd_kcontrol_new tx_dmic7_mux = SOC_DAPM_ENUM_EXT("tx_dmic7", tx_dmic7_enum,
snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
static const char * const dec_mode_mux_text[] = {
"ADC_DEFAULT", "ADC_LOW_PWR", "ADC_HIGH_PERF",
};
static const struct soc_enum dec_mode_mux_enum[] = {
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(dec_mode_mux_text),
dec_mode_mux_text),
SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(dec_mode_mux_text),
dec_mode_mux_text),
SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(dec_mode_mux_text),
dec_mode_mux_text),
SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(dec_mode_mux_text),
dec_mode_mux_text),
SOC_ENUM_SINGLE(SND_SOC_NOPM, 4, ARRAY_SIZE(dec_mode_mux_text),
dec_mode_mux_text),
SOC_ENUM_SINGLE(SND_SOC_NOPM, 5, ARRAY_SIZE(dec_mode_mux_text),
dec_mode_mux_text),
SOC_ENUM_SINGLE(SND_SOC_NOPM, 6, ARRAY_SIZE(dec_mode_mux_text),
dec_mode_mux_text),
SOC_ENUM_SINGLE(SND_SOC_NOPM, 7, ARRAY_SIZE(dec_mode_mux_text),
dec_mode_mux_text),
};
static const struct snd_kcontrol_new tx_aif1_cap_mixer[] = {
SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0,
tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0,
tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0,
tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0,
tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0,
tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0,
tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0,
tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0,
tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
};
static const struct snd_kcontrol_new tx_aif2_cap_mixer[] = {
SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0,
tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0,
tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0,
tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0,
tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0,
tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0,
tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0,
tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0,
tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
};
static const struct snd_kcontrol_new tx_aif3_cap_mixer[] = {
SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0,
tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0,
tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0,
tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0,
tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0,
tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0,
tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0,
tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0,
tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
};
static const struct snd_soc_dapm_widget tx_macro_dapm_widgets[] = {
SND_SOC_DAPM_AIF_OUT("TX_AIF1 CAP", "TX_AIF1 Capture", 0,
SND_SOC_NOPM, TX_MACRO_AIF1_CAP, 0),
SND_SOC_DAPM_AIF_OUT("TX_AIF2 CAP", "TX_AIF2 Capture", 0,
SND_SOC_NOPM, TX_MACRO_AIF2_CAP, 0),
SND_SOC_DAPM_AIF_OUT("TX_AIF3 CAP", "TX_AIF3 Capture", 0,
SND_SOC_NOPM, TX_MACRO_AIF3_CAP, 0),
SND_SOC_DAPM_MIXER("TX_AIF1_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF1_CAP, 0,
tx_aif1_cap_mixer, ARRAY_SIZE(tx_aif1_cap_mixer)),
SND_SOC_DAPM_MIXER("TX_AIF2_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF2_CAP, 0,
tx_aif2_cap_mixer, ARRAY_SIZE(tx_aif2_cap_mixer)),
SND_SOC_DAPM_MIXER("TX_AIF3_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF3_CAP, 0,
tx_aif3_cap_mixer, ARRAY_SIZE(tx_aif3_cap_mixer)),
SND_SOC_DAPM_MUX("TX SMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_smic0_mux),
SND_SOC_DAPM_MUX("TX SMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_smic1_mux),
SND_SOC_DAPM_MUX("TX SMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_smic2_mux),
SND_SOC_DAPM_MUX("TX SMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_smic3_mux),
SND_SOC_DAPM_MUX("TX SMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_smic4_mux),
SND_SOC_DAPM_MUX("TX SMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_smic5_mux),
SND_SOC_DAPM_MUX("TX SMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_smic6_mux),
SND_SOC_DAPM_MUX("TX SMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_smic7_mux),
SND_SOC_DAPM_MUX("TX DMIC MUX0", SND_SOC_NOPM, 4, 0, &tx_dmic0_mux),
SND_SOC_DAPM_MUX("TX DMIC MUX1", SND_SOC_NOPM, 4, 0, &tx_dmic1_mux),
SND_SOC_DAPM_MUX("TX DMIC MUX2", SND_SOC_NOPM, 4, 0, &tx_dmic2_mux),
SND_SOC_DAPM_MUX("TX DMIC MUX3", SND_SOC_NOPM, 4, 0, &tx_dmic3_mux),
SND_SOC_DAPM_MUX("TX DMIC MUX4", SND_SOC_NOPM, 4, 0, &tx_dmic4_mux),
SND_SOC_DAPM_MUX("TX DMIC MUX5", SND_SOC_NOPM, 4, 0, &tx_dmic5_mux),
SND_SOC_DAPM_MUX("TX DMIC MUX6", SND_SOC_NOPM, 4, 0, &tx_dmic6_mux),
SND_SOC_DAPM_MUX("TX DMIC MUX7", SND_SOC_NOPM, 4, 0, &tx_dmic7_mux),
SND_SOC_DAPM_INPUT("TX SWR_ADC0"),
SND_SOC_DAPM_INPUT("TX SWR_ADC1"),
SND_SOC_DAPM_INPUT("TX SWR_ADC2"),
SND_SOC_DAPM_INPUT("TX SWR_ADC3"),
SND_SOC_DAPM_INPUT("TX SWR_DMIC0"),
SND_SOC_DAPM_INPUT("TX SWR_DMIC1"),
SND_SOC_DAPM_INPUT("TX SWR_DMIC2"),
SND_SOC_DAPM_INPUT("TX SWR_DMIC3"),
SND_SOC_DAPM_INPUT("TX SWR_DMIC4"),
SND_SOC_DAPM_INPUT("TX SWR_DMIC5"),
SND_SOC_DAPM_INPUT("TX SWR_DMIC6"),
SND_SOC_DAPM_INPUT("TX SWR_DMIC7"),
SND_SOC_DAPM_INPUT("TX DMIC0"),
SND_SOC_DAPM_INPUT("TX DMIC1"),
SND_SOC_DAPM_INPUT("TX DMIC2"),
SND_SOC_DAPM_INPUT("TX DMIC3"),
SND_SOC_DAPM_INPUT("TX DMIC4"),
SND_SOC_DAPM_INPUT("TX DMIC5"),
SND_SOC_DAPM_INPUT("TX DMIC6"),
SND_SOC_DAPM_INPUT("TX DMIC7"),
SND_SOC_DAPM_MUX_E("TX DEC0 MUX", SND_SOC_NOPM,
TX_MACRO_DEC0, 0,
&tx_dec0_mux, tx_macro_enable_dec,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("TX DEC1 MUX", SND_SOC_NOPM,
TX_MACRO_DEC1, 0,
&tx_dec1_mux, tx_macro_enable_dec,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("TX DEC2 MUX", SND_SOC_NOPM,
TX_MACRO_DEC2, 0,
&tx_dec2_mux, tx_macro_enable_dec,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("TX DEC3 MUX", SND_SOC_NOPM,
TX_MACRO_DEC3, 0,
&tx_dec3_mux, tx_macro_enable_dec,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("TX DEC4 MUX", SND_SOC_NOPM,
TX_MACRO_DEC4, 0,
&tx_dec4_mux, tx_macro_enable_dec,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("TX DEC5 MUX", SND_SOC_NOPM,
TX_MACRO_DEC5, 0,
&tx_dec5_mux, tx_macro_enable_dec,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("TX DEC6 MUX", SND_SOC_NOPM,
TX_MACRO_DEC6, 0,
&tx_dec6_mux, tx_macro_enable_dec,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("TX DEC7 MUX", SND_SOC_NOPM,
TX_MACRO_DEC7, 0,
&tx_dec7_mux, tx_macro_enable_dec,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("TX_MCLK", 0, SND_SOC_NOPM, 0, 0,
tx_macro_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("TX_SWR_CLK", 0, SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("VA_SWR_CLK", 0, SND_SOC_NOPM, 0, 0,
NULL, 0),
};
static const struct snd_soc_dapm_route tx_audio_map[] = {
{"TX_AIF1 CAP", NULL, "TX_MCLK"},
{"TX_AIF2 CAP", NULL, "TX_MCLK"},
{"TX_AIF3 CAP", NULL, "TX_MCLK"},
{"TX_AIF1 CAP", NULL, "TX_AIF1_CAP Mixer"},
{"TX_AIF2 CAP", NULL, "TX_AIF2_CAP Mixer"},
{"TX_AIF3 CAP", NULL, "TX_AIF3_CAP Mixer"},
{"TX_AIF1_CAP Mixer", "DEC0", "TX DEC0 MUX"},
{"TX_AIF1_CAP Mixer", "DEC1", "TX DEC1 MUX"},
{"TX_AIF1_CAP Mixer", "DEC2", "TX DEC2 MUX"},
{"TX_AIF1_CAP Mixer", "DEC3", "TX DEC3 MUX"},
{"TX_AIF1_CAP Mixer", "DEC4", "TX DEC4 MUX"},
{"TX_AIF1_CAP Mixer", "DEC5", "TX DEC5 MUX"},
{"TX_AIF1_CAP Mixer", "DEC6", "TX DEC6 MUX"},
{"TX_AIF1_CAP Mixer", "DEC7", "TX DEC7 MUX"},
{"TX_AIF2_CAP Mixer", "DEC0", "TX DEC0 MUX"},
{"TX_AIF2_CAP Mixer", "DEC1", "TX DEC1 MUX"},
{"TX_AIF2_CAP Mixer", "DEC2", "TX DEC2 MUX"},
{"TX_AIF2_CAP Mixer", "DEC3", "TX DEC3 MUX"},
{"TX_AIF2_CAP Mixer", "DEC4", "TX DEC4 MUX"},
{"TX_AIF2_CAP Mixer", "DEC5", "TX DEC5 MUX"},
{"TX_AIF2_CAP Mixer", "DEC6", "TX DEC6 MUX"},
{"TX_AIF2_CAP Mixer", "DEC7", "TX DEC7 MUX"},
{"TX_AIF3_CAP Mixer", "DEC0", "TX DEC0 MUX"},
{"TX_AIF3_CAP Mixer", "DEC1", "TX DEC1 MUX"},
{"TX_AIF3_CAP Mixer", "DEC2", "TX DEC2 MUX"},
{"TX_AIF3_CAP Mixer", "DEC3", "TX DEC3 MUX"},
{"TX_AIF3_CAP Mixer", "DEC4", "TX DEC4 MUX"},
{"TX_AIF3_CAP Mixer", "DEC5", "TX DEC5 MUX"},
{"TX_AIF3_CAP Mixer", "DEC6", "TX DEC6 MUX"},
{"TX_AIF3_CAP Mixer", "DEC7", "TX DEC7 MUX"},
{"TX DEC0 MUX", NULL, "TX_MCLK"},
{"TX DEC1 MUX", NULL, "TX_MCLK"},
{"TX DEC2 MUX", NULL, "TX_MCLK"},
{"TX DEC3 MUX", NULL, "TX_MCLK"},
{"TX DEC4 MUX", NULL, "TX_MCLK"},
{"TX DEC5 MUX", NULL, "TX_MCLK"},
{"TX DEC6 MUX", NULL, "TX_MCLK"},
{"TX DEC7 MUX", NULL, "TX_MCLK"},
{"TX DEC0 MUX", "MSM_DMIC", "TX DMIC MUX0"},
{"TX DMIC MUX0", "DMIC0", "TX DMIC0"},
{"TX DMIC MUX0", "DMIC1", "TX DMIC1"},
{"TX DMIC MUX0", "DMIC2", "TX DMIC2"},
{"TX DMIC MUX0", "DMIC3", "TX DMIC3"},
{"TX DMIC MUX0", "DMIC4", "TX DMIC4"},
{"TX DMIC MUX0", "DMIC5", "TX DMIC5"},
{"TX DMIC MUX0", "DMIC6", "TX DMIC6"},
{"TX DMIC MUX0", "DMIC7", "TX DMIC7"},
{"TX DEC0 MUX", "SWR_MIC", "TX SMIC MUX0"},
{"TX SMIC MUX0", NULL, "TX_SWR_CLK"},
{"TX SMIC MUX0", "ADC0", "TX SWR_ADC0"},
{"TX SMIC MUX0", "ADC1", "TX SWR_ADC1"},
{"TX SMIC MUX0", "ADC2", "TX SWR_ADC2"},
{"TX SMIC MUX0", "ADC3", "TX SWR_ADC3"},
{"TX SMIC MUX0", "SWR_DMIC0", "TX SWR_DMIC0"},
{"TX SMIC MUX0", "SWR_DMIC1", "TX SWR_DMIC1"},
{"TX SMIC MUX0", "SWR_DMIC2", "TX SWR_DMIC2"},
{"TX SMIC MUX0", "SWR_DMIC3", "TX SWR_DMIC3"},
{"TX SMIC MUX0", "SWR_DMIC4", "TX SWR_DMIC4"},
{"TX SMIC MUX0", "SWR_DMIC5", "TX SWR_DMIC5"},
{"TX SMIC MUX0", "SWR_DMIC6", "TX SWR_DMIC6"},
{"TX SMIC MUX0", "SWR_DMIC7", "TX SWR_DMIC7"},
{"TX DEC1 MUX", "MSM_DMIC", "TX DMIC MUX1"},
{"TX DMIC MUX1", "DMIC0", "TX DMIC0"},
{"TX DMIC MUX1", "DMIC1", "TX DMIC1"},
{"TX DMIC MUX1", "DMIC2", "TX DMIC2"},
{"TX DMIC MUX1", "DMIC3", "TX DMIC3"},
{"TX DMIC MUX1", "DMIC4", "TX DMIC4"},
{"TX DMIC MUX1", "DMIC5", "TX DMIC5"},
{"TX DMIC MUX1", "DMIC6", "TX DMIC6"},
{"TX DMIC MUX1", "DMIC7", "TX DMIC7"},
{"TX DEC1 MUX", "SWR_MIC", "TX SMIC MUX1"},
{"TX SMIC MUX1", NULL, "TX_SWR_CLK"},
{"TX SMIC MUX1", "ADC0", "TX SWR_ADC0"},
{"TX SMIC MUX1", "ADC1", "TX SWR_ADC1"},
{"TX SMIC MUX1", "ADC2", "TX SWR_ADC2"},
{"TX SMIC MUX1", "ADC3", "TX SWR_ADC3"},
{"TX SMIC MUX1", "SWR_DMIC0", "TX SWR_DMIC0"},
{"TX SMIC MUX1", "SWR_DMIC1", "TX SWR_DMIC1"},
{"TX SMIC MUX1", "SWR_DMIC2", "TX SWR_DMIC2"},
{"TX SMIC MUX1", "SWR_DMIC3", "TX SWR_DMIC3"},
{"TX SMIC MUX1", "SWR_DMIC4", "TX SWR_DMIC4"},
{"TX SMIC MUX1", "SWR_DMIC5", "TX SWR_DMIC5"},
{"TX SMIC MUX1", "SWR_DMIC6", "TX SWR_DMIC6"},
{"TX SMIC MUX1", "SWR_DMIC7", "TX SWR_DMIC7"},
{"TX DEC2 MUX", "MSM_DMIC", "TX DMIC MUX2"},
{"TX DMIC MUX2", "DMIC0", "TX DMIC0"},
{"TX DMIC MUX2", "DMIC1", "TX DMIC1"},
{"TX DMIC MUX2", "DMIC2", "TX DMIC2"},
{"TX DMIC MUX2", "DMIC3", "TX DMIC3"},
{"TX DMIC MUX2", "DMIC4", "TX DMIC4"},
{"TX DMIC MUX2", "DMIC5", "TX DMIC5"},
{"TX DMIC MUX2", "DMIC6", "TX DMIC6"},
{"TX DMIC MUX2", "DMIC7", "TX DMIC7"},
{"TX DEC2 MUX", "SWR_MIC", "TX SMIC MUX2"},
{"TX SMIC MUX2", NULL, "TX_SWR_CLK"},
{"TX SMIC MUX2", "ADC0", "TX SWR_ADC0"},
{"TX SMIC MUX2", "ADC1", "TX SWR_ADC1"},
{"TX SMIC MUX2", "ADC2", "TX SWR_ADC2"},
{"TX SMIC MUX2", "ADC3", "TX SWR_ADC3"},
{"TX SMIC MUX2", "SWR_DMIC0", "TX SWR_DMIC0"},
{"TX SMIC MUX2", "SWR_DMIC1", "TX SWR_DMIC1"},
{"TX SMIC MUX2", "SWR_DMIC2", "TX SWR_DMIC2"},
{"TX SMIC MUX2", "SWR_DMIC3", "TX SWR_DMIC3"},
{"TX SMIC MUX2", "SWR_DMIC4", "TX SWR_DMIC4"},
{"TX SMIC MUX2", "SWR_DMIC5", "TX SWR_DMIC5"},
{"TX SMIC MUX2", "SWR_DMIC6", "TX SWR_DMIC6"},
{"TX SMIC MUX2", "SWR_DMIC7", "TX SWR_DMIC7"},
{"TX DEC3 MUX", "MSM_DMIC", "TX DMIC MUX3"},
{"TX DMIC MUX3", "DMIC0", "TX DMIC0"},
{"TX DMIC MUX3", "DMIC1", "TX DMIC1"},
{"TX DMIC MUX3", "DMIC2", "TX DMIC2"},
{"TX DMIC MUX3", "DMIC3", "TX DMIC3"},
{"TX DMIC MUX3", "DMIC4", "TX DMIC4"},
{"TX DMIC MUX3", "DMIC5", "TX DMIC5"},
{"TX DMIC MUX3", "DMIC6", "TX DMIC6"},
{"TX DMIC MUX3", "DMIC7", "TX DMIC7"},
{"TX DEC3 MUX", "SWR_MIC", "TX SMIC MUX3"},
{"TX SMIC MUX3", NULL, "TX_SWR_CLK"},
{"TX SMIC MUX3", "ADC0", "TX SWR_ADC0"},
{"TX SMIC MUX3", "ADC1", "TX SWR_ADC1"},
{"TX SMIC MUX3", "ADC2", "TX SWR_ADC2"},
{"TX SMIC MUX3", "ADC3", "TX SWR_ADC3"},
{"TX SMIC MUX3", "SWR_DMIC0", "TX SWR_DMIC0"},
{"TX SMIC MUX3", "SWR_DMIC1", "TX SWR_DMIC1"},
{"TX SMIC MUX3", "SWR_DMIC2", "TX SWR_DMIC2"},
{"TX SMIC MUX3", "SWR_DMIC3", "TX SWR_DMIC3"},
{"TX SMIC MUX3", "SWR_DMIC4", "TX SWR_DMIC4"},
{"TX SMIC MUX3", "SWR_DMIC5", "TX SWR_DMIC5"},
{"TX SMIC MUX3", "SWR_DMIC6", "TX SWR_DMIC6"},
{"TX SMIC MUX3", "SWR_DMIC7", "TX SWR_DMIC7"},
{"TX DEC4 MUX", "MSM_DMIC", "TX DMIC MUX4"},
{"TX DMIC MUX4", "DMIC0", "TX DMIC0"},
{"TX DMIC MUX4", "DMIC1", "TX DMIC1"},
{"TX DMIC MUX4", "DMIC2", "TX DMIC2"},
{"TX DMIC MUX4", "DMIC3", "TX DMIC3"},
{"TX DMIC MUX4", "DMIC4", "TX DMIC4"},
{"TX DMIC MUX4", "DMIC5", "TX DMIC5"},
{"TX DMIC MUX4", "DMIC6", "TX DMIC6"},
{"TX DMIC MUX4", "DMIC7", "TX DMIC7"},
{"TX DEC4 MUX", "SWR_MIC", "TX SMIC MUX4"},
{"TX SMIC MUX4", NULL, "TX_SWR_CLK"},
{"TX SMIC MUX4", "ADC0", "TX SWR_ADC0"},
{"TX SMIC MUX4", "ADC1", "TX SWR_ADC1"},
{"TX SMIC MUX4", "ADC2", "TX SWR_ADC2"},
{"TX SMIC MUX4", "ADC3", "TX SWR_ADC3"},
{"TX SMIC MUX4", "SWR_DMIC0", "TX SWR_DMIC0"},
{"TX SMIC MUX4", "SWR_DMIC1", "TX SWR_DMIC1"},
{"TX SMIC MUX4", "SWR_DMIC2", "TX SWR_DMIC2"},
{"TX SMIC MUX4", "SWR_DMIC3", "TX SWR_DMIC3"},
{"TX SMIC MUX4", "SWR_DMIC4", "TX SWR_DMIC4"},
{"TX SMIC MUX4", "SWR_DMIC5", "TX SWR_DMIC5"},
{"TX SMIC MUX4", "SWR_DMIC6", "TX SWR_DMIC6"},
{"TX SMIC MUX4", "SWR_DMIC7", "TX SWR_DMIC7"},
{"TX DEC5 MUX", "MSM_DMIC", "TX DMIC MUX5"},
{"TX DMIC MUX5", "DMIC0", "TX DMIC0"},
{"TX DMIC MUX5", "DMIC1", "TX DMIC1"},
{"TX DMIC MUX5", "DMIC2", "TX DMIC2"},
{"TX DMIC MUX5", "DMIC3", "TX DMIC3"},
{"TX DMIC MUX5", "DMIC4", "TX DMIC4"},
{"TX DMIC MUX5", "DMIC5", "TX DMIC5"},
{"TX DMIC MUX5", "DMIC6", "TX DMIC6"},
{"TX DMIC MUX5", "DMIC7", "TX DMIC7"},
{"TX DEC5 MUX", "SWR_MIC", "TX SMIC MUX5"},
{"TX SMIC MUX5", NULL, "TX_SWR_CLK"},
{"TX SMIC MUX5", "ADC0", "TX SWR_ADC0"},
{"TX SMIC MUX5", "ADC1", "TX SWR_ADC1"},
{"TX SMIC MUX5", "ADC2", "TX SWR_ADC2"},
{"TX SMIC MUX5", "ADC3", "TX SWR_ADC3"},
{"TX SMIC MUX5", "SWR_DMIC0", "TX SWR_DMIC0"},
{"TX SMIC MUX5", "SWR_DMIC1", "TX SWR_DMIC1"},
{"TX SMIC MUX5", "SWR_DMIC2", "TX SWR_DMIC2"},
{"TX SMIC MUX5", "SWR_DMIC3", "TX SWR_DMIC3"},
{"TX SMIC MUX5", "SWR_DMIC4", "TX SWR_DMIC4"},
{"TX SMIC MUX5", "SWR_DMIC5", "TX SWR_DMIC5"},
{"TX SMIC MUX5", "SWR_DMIC6", "TX SWR_DMIC6"},
{"TX SMIC MUX5", "SWR_DMIC7", "TX SWR_DMIC7"},
{"TX DEC6 MUX", "MSM_DMIC", "TX DMIC MUX6"},
{"TX DMIC MUX6", "DMIC0", "TX DMIC0"},
{"TX DMIC MUX6", "DMIC1", "TX DMIC1"},
{"TX DMIC MUX6", "DMIC2", "TX DMIC2"},
{"TX DMIC MUX6", "DMIC3", "TX DMIC3"},
{"TX DMIC MUX6", "DMIC4", "TX DMIC4"},
{"TX DMIC MUX6", "DMIC5", "TX DMIC5"},
{"TX DMIC MUX6", "DMIC6", "TX DMIC6"},
{"TX DMIC MUX6", "DMIC7", "TX DMIC7"},
{"TX DEC6 MUX", "SWR_MIC", "TX SMIC MUX6"},
{"TX SMIC MUX6", NULL, "TX_SWR_CLK"},
{"TX SMIC MUX6", "ADC0", "TX SWR_ADC0"},
{"TX SMIC MUX6", "ADC1", "TX SWR_ADC1"},
{"TX SMIC MUX6", "ADC2", "TX SWR_ADC2"},
{"TX SMIC MUX6", "ADC3", "TX SWR_ADC3"},
{"TX SMIC MUX6", "SWR_DMIC0", "TX SWR_DMIC0"},
{"TX SMIC MUX6", "SWR_DMIC1", "TX SWR_DMIC1"},
{"TX SMIC MUX6", "SWR_DMIC2", "TX SWR_DMIC2"},
{"TX SMIC MUX6", "SWR_DMIC3", "TX SWR_DMIC3"},
{"TX SMIC MUX6", "SWR_DMIC4", "TX SWR_DMIC4"},
{"TX SMIC MUX6", "SWR_DMIC5", "TX SWR_DMIC5"},
{"TX SMIC MUX6", "SWR_DMIC6", "TX SWR_DMIC6"},
{"TX SMIC MUX6", "SWR_DMIC7", "TX SWR_DMIC7"},
{"TX DEC7 MUX", "MSM_DMIC", "TX DMIC MUX7"},
{"TX DMIC MUX7", "DMIC0", "TX DMIC0"},
{"TX DMIC MUX7", "DMIC1", "TX DMIC1"},
{"TX DMIC MUX7", "DMIC2", "TX DMIC2"},
{"TX DMIC MUX7", "DMIC3", "TX DMIC3"},
{"TX DMIC MUX7", "DMIC4", "TX DMIC4"},
{"TX DMIC MUX7", "DMIC5", "TX DMIC5"},
{"TX DMIC MUX7", "DMIC6", "TX DMIC6"},
{"TX DMIC MUX7", "DMIC7", "TX DMIC7"},
{"TX DEC7 MUX", "SWR_MIC", "TX SMIC MUX7"},
{"TX SMIC MUX7", NULL, "TX_SWR_CLK"},
{"TX SMIC MUX7", "ADC0", "TX SWR_ADC0"},
{"TX SMIC MUX7", "ADC1", "TX SWR_ADC1"},
{"TX SMIC MUX7", "ADC2", "TX SWR_ADC2"},
{"TX SMIC MUX7", "ADC3", "TX SWR_ADC3"},
{"TX SMIC MUX7", "SWR_DMIC0", "TX SWR_DMIC0"},
{"TX SMIC MUX7", "SWR_DMIC1", "TX SWR_DMIC1"},
{"TX SMIC MUX7", "SWR_DMIC2", "TX SWR_DMIC2"},
{"TX SMIC MUX7", "SWR_DMIC3", "TX SWR_DMIC3"},
{"TX SMIC MUX7", "SWR_DMIC4", "TX SWR_DMIC4"},
{"TX SMIC MUX7", "SWR_DMIC5", "TX SWR_DMIC5"},
{"TX SMIC MUX7", "SWR_DMIC6", "TX SWR_DMIC6"},
{"TX SMIC MUX7", "SWR_DMIC7", "TX SWR_DMIC7"},
};
static const struct snd_kcontrol_new tx_macro_snd_controls[] = {
SOC_SINGLE_S8_TLV("TX_DEC0 Volume",
CDC_TX0_TX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("TX_DEC1 Volume",
CDC_TX1_TX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("TX_DEC2 Volume",
CDC_TX2_TX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("TX_DEC3 Volume",
CDC_TX3_TX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("TX_DEC4 Volume",
CDC_TX4_TX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("TX_DEC5 Volume",
CDC_TX5_TX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("TX_DEC6 Volume",
CDC_TX6_TX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("TX_DEC7 Volume",
CDC_TX7_TX_VOL_CTL,
-84, 40, digital_gain),
SOC_ENUM_EXT("DEC0 MODE", dec_mode_mux_enum[0],
tx_macro_dec_mode_get, tx_macro_dec_mode_put),
SOC_ENUM_EXT("DEC1 MODE", dec_mode_mux_enum[1],
tx_macro_dec_mode_get, tx_macro_dec_mode_put),
SOC_ENUM_EXT("DEC2 MODE", dec_mode_mux_enum[2],
tx_macro_dec_mode_get, tx_macro_dec_mode_put),
SOC_ENUM_EXT("DEC3 MODE", dec_mode_mux_enum[3],
tx_macro_dec_mode_get, tx_macro_dec_mode_put),
SOC_ENUM_EXT("DEC4 MODE", dec_mode_mux_enum[4],
tx_macro_dec_mode_get, tx_macro_dec_mode_put),
SOC_ENUM_EXT("DEC5 MODE", dec_mode_mux_enum[5],
tx_macro_dec_mode_get, tx_macro_dec_mode_put),
SOC_ENUM_EXT("DEC6 MODE", dec_mode_mux_enum[6],
tx_macro_dec_mode_get, tx_macro_dec_mode_put),
SOC_ENUM_EXT("DEC7 MODE", dec_mode_mux_enum[7],
tx_macro_dec_mode_get, tx_macro_dec_mode_put),
SOC_SINGLE_EXT("DEC0_BCS Switch", SND_SOC_NOPM, 0, 1, 0,
tx_macro_get_bcs, tx_macro_set_bcs),
};
static int tx_macro_component_probe(struct snd_soc_component *comp)
{
struct tx_macro *tx = snd_soc_component_get_drvdata(comp);
int i;
snd_soc_component_init_regmap(comp, tx->regmap);
for (i = 0; i < NUM_DECIMATORS; i++) {
tx->tx_hpf_work[i].tx = tx;
tx->tx_hpf_work[i].decimator = i;
INIT_DELAYED_WORK(&tx->tx_hpf_work[i].dwork,
tx_macro_tx_hpf_corner_freq_callback);
}
for (i = 0; i < NUM_DECIMATORS; i++) {
tx->tx_mute_dwork[i].tx = tx;
tx->tx_mute_dwork[i].decimator = i;
INIT_DELAYED_WORK(&tx->tx_mute_dwork[i].dwork,
tx_macro_mute_update_callback);
}
tx->component = comp;
snd_soc_component_update_bits(comp, CDC_TX0_TX_PATH_SEC7, 0x3F,
0x0A);
/* Enable swr mic0 and mic1 clock */
snd_soc_component_update_bits(comp, CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0xFF, 0x00);
snd_soc_component_update_bits(comp, CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0xFF, 0x00);
return 0;
}
static int swclk_gate_enable(struct clk_hw *hw)
{
struct tx_macro *tx = to_tx_macro(hw);
struct regmap *regmap = tx->regmap;
int ret;
ret = clk_prepare_enable(tx->mclk);
if (ret) {
dev_err(tx->dev, "failed to enable mclk\n");
return ret;
}
tx_macro_mclk_enable(tx, true);
regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
CDC_TX_SWR_CLK_EN_MASK,
CDC_TX_SWR_CLK_ENABLE);
return 0;
}
static void swclk_gate_disable(struct clk_hw *hw)
{
struct tx_macro *tx = to_tx_macro(hw);
struct regmap *regmap = tx->regmap;
regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
CDC_TX_SWR_CLK_EN_MASK, 0x0);
tx_macro_mclk_enable(tx, false);
clk_disable_unprepare(tx->mclk);
}
static int swclk_gate_is_enabled(struct clk_hw *hw)
{
struct tx_macro *tx = to_tx_macro(hw);
int ret, val;
regmap_read(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, &val);
ret = val & BIT(0);
return ret;
}
static unsigned long swclk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
return parent_rate / 2;
}
static const struct clk_ops swclk_gate_ops = {
.prepare = swclk_gate_enable,
.unprepare = swclk_gate_disable,
.is_enabled = swclk_gate_is_enabled,
.recalc_rate = swclk_recalc_rate,
};
static int tx_macro_register_mclk_output(struct tx_macro *tx)
{
struct device *dev = tx->dev;
const char *parent_clk_name = NULL;
const char *clk_name = "lpass-tx-mclk";
struct clk_hw *hw;
struct clk_init_data init;
int ret;
if (tx->npl)
parent_clk_name = __clk_get_name(tx->npl);
else
parent_clk_name = __clk_get_name(tx->mclk);
init.name = clk_name;
init.ops = &swclk_gate_ops;
init.flags = 0;
init.parent_names = &parent_clk_name;
init.num_parents = 1;
tx->hw.init = &init;
hw = &tx->hw;
ret = devm_clk_hw_register(dev, hw);
if (ret)
return ret;
return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
}
static const struct snd_soc_component_driver tx_macro_component_drv = {
.name = "RX-MACRO",
.probe = tx_macro_component_probe,
.controls = tx_macro_snd_controls,
.num_controls = ARRAY_SIZE(tx_macro_snd_controls),
.dapm_widgets = tx_macro_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(tx_macro_dapm_widgets),
.dapm_routes = tx_audio_map,
.num_dapm_routes = ARRAY_SIZE(tx_audio_map),
};
static int tx_macro_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
kernel_ulong_t flags;
struct tx_macro *tx;
void __iomem *base;
int ret, reg;
flags = (kernel_ulong_t)device_get_match_data(dev);
tx = devm_kzalloc(dev, sizeof(*tx), GFP_KERNEL);
if (!tx)
return -ENOMEM;
tx->macro = devm_clk_get_optional(dev, "macro");
if (IS_ERR(tx->macro))
return dev_err_probe(dev, PTR_ERR(tx->macro), "unable to get macro clock\n");
tx->dcodec = devm_clk_get_optional(dev, "dcodec");
if (IS_ERR(tx->dcodec))
return dev_err_probe(dev, PTR_ERR(tx->dcodec), "unable to get dcodec clock\n");
tx->mclk = devm_clk_get(dev, "mclk");
if (IS_ERR(tx->mclk))
return dev_err_probe(dev, PTR_ERR(tx->mclk), "unable to get mclk clock\n");
if (flags & LPASS_MACRO_FLAG_HAS_NPL_CLOCK) {
tx->npl = devm_clk_get(dev, "npl");
if (IS_ERR(tx->npl))
return dev_err_probe(dev, PTR_ERR(tx->npl), "unable to get npl clock\n");
}
tx->fsgen = devm_clk_get(dev, "fsgen");
if (IS_ERR(tx->fsgen))
return dev_err_probe(dev, PTR_ERR(tx->fsgen), "unable to get fsgen clock\n");
tx->pds = lpass_macro_pds_init(dev);
if (IS_ERR(tx->pds))
return PTR_ERR(tx->pds);
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base)) {
ret = PTR_ERR(base);
goto err;
}
/* Update defaults for lpass sc7280 */
if (of_device_is_compatible(np, "qcom,sc7280-lpass-tx-macro")) {
for (reg = 0; reg < ARRAY_SIZE(tx_defaults); reg++) {
switch (tx_defaults[reg].reg) {
case CDC_TX_TOP_CSR_SWR_AMIC0_CTL:
case CDC_TX_TOP_CSR_SWR_AMIC1_CTL:
tx_defaults[reg].def = 0x0E;
break;
default:
break;
}
}
}
tx->regmap = devm_regmap_init_mmio(dev, base, &tx_regmap_config);
if (IS_ERR(tx->regmap)) {
ret = PTR_ERR(tx->regmap);
goto err;
}
dev_set_drvdata(dev, tx);
tx->dev = dev;
/* set MCLK and NPL rates */
clk_set_rate(tx->mclk, MCLK_FREQ);
clk_set_rate(tx->npl, MCLK_FREQ);
ret = clk_prepare_enable(tx->macro);
if (ret)
goto err;
ret = clk_prepare_enable(tx->dcodec);
if (ret)
goto err_dcodec;
ret = clk_prepare_enable(tx->mclk);
if (ret)
goto err_mclk;
ret = clk_prepare_enable(tx->npl);
if (ret)
goto err_npl;
ret = clk_prepare_enable(tx->fsgen);
if (ret)
goto err_fsgen;
/* reset soundwire block */
regmap_update_bits(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
CDC_TX_SWR_RESET_MASK, CDC_TX_SWR_RESET_ENABLE);
regmap_update_bits(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
CDC_TX_SWR_CLK_EN_MASK,
CDC_TX_SWR_CLK_ENABLE);
regmap_update_bits(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
CDC_TX_SWR_RESET_MASK, 0x0);
ret = devm_snd_soc_register_component(dev, &tx_macro_component_drv,
tx_macro_dai,
ARRAY_SIZE(tx_macro_dai));
if (ret)
goto err_clkout;
pm_runtime_set_autosuspend_delay(dev, 3000);
pm_runtime_use_autosuspend(dev);
pm_runtime_mark_last_busy(dev);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
ret = tx_macro_register_mclk_output(tx);
if (ret)
goto err_clkout;
return 0;
err_clkout:
clk_disable_unprepare(tx->fsgen);
err_fsgen:
clk_disable_unprepare(tx->npl);
err_npl:
clk_disable_unprepare(tx->mclk);
err_mclk:
clk_disable_unprepare(tx->dcodec);
err_dcodec:
clk_disable_unprepare(tx->macro);
err:
lpass_macro_pds_exit(tx->pds);
return ret;
}
static void tx_macro_remove(struct platform_device *pdev)
{
struct tx_macro *tx = dev_get_drvdata(&pdev->dev);
clk_disable_unprepare(tx->macro);
clk_disable_unprepare(tx->dcodec);
clk_disable_unprepare(tx->mclk);
clk_disable_unprepare(tx->npl);
clk_disable_unprepare(tx->fsgen);
lpass_macro_pds_exit(tx->pds);
}
static int __maybe_unused tx_macro_runtime_suspend(struct device *dev)
{
struct tx_macro *tx = dev_get_drvdata(dev);
regcache_cache_only(tx->regmap, true);
regcache_mark_dirty(tx->regmap);
clk_disable_unprepare(tx->fsgen);
clk_disable_unprepare(tx->npl);
clk_disable_unprepare(tx->mclk);
return 0;
}
static int __maybe_unused tx_macro_runtime_resume(struct device *dev)
{
struct tx_macro *tx = dev_get_drvdata(dev);
int ret;
ret = clk_prepare_enable(tx->mclk);
if (ret) {
dev_err(dev, "unable to prepare mclk\n");
return ret;
}
ret = clk_prepare_enable(tx->npl);
if (ret) {
dev_err(dev, "unable to prepare npl\n");
goto err_npl;
}
ret = clk_prepare_enable(tx->fsgen);
if (ret) {
dev_err(dev, "unable to prepare fsgen\n");
goto err_fsgen;
}
regcache_cache_only(tx->regmap, false);
regcache_sync(tx->regmap);
return 0;
err_fsgen:
clk_disable_unprepare(tx->npl);
err_npl:
clk_disable_unprepare(tx->mclk);
return ret;
}
static const struct dev_pm_ops tx_macro_pm_ops = {
SET_RUNTIME_PM_OPS(tx_macro_runtime_suspend, tx_macro_runtime_resume, NULL)
};
static const struct of_device_id tx_macro_dt_match[] = {
{
.compatible = "qcom,sc7280-lpass-tx-macro",
.data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
}, {
.compatible = "qcom,sm8250-lpass-tx-macro",
.data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
}, {
.compatible = "qcom,sm8450-lpass-tx-macro",
.data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
}, {
.compatible = "qcom,sm8550-lpass-tx-macro",
}, {
.compatible = "qcom,sc8280xp-lpass-tx-macro",
.data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
},
{ }
};
MODULE_DEVICE_TABLE(of, tx_macro_dt_match);
static struct platform_driver tx_macro_driver = {
.driver = {
.name = "tx_macro",
.of_match_table = tx_macro_dt_match,
.suppress_bind_attrs = true,
.pm = &tx_macro_pm_ops,
},
.probe = tx_macro_probe,
.remove_new = tx_macro_remove,
};
module_platform_driver(tx_macro_driver);
MODULE_DESCRIPTION("TX macro driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/lpass-tx-macro.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ADAU1977/ADAU1978/ADAU1979 driver
*
* Copyright 2014 Analog Devices Inc.
* Author: Lars-Peter Clausen <[email protected]>
*/
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/spi/spi.h>
#include <sound/soc.h>
#include "adau1977.h"
static void adau1977_spi_switch_mode(struct device *dev)
{
struct spi_device *spi = to_spi_device(dev);
/*
* To get the device into SPI mode CLATCH has to be pulled low three
* times. Do this by issuing three dummy reads.
*/
spi_w8r8(spi, 0x00);
spi_w8r8(spi, 0x00);
spi_w8r8(spi, 0x00);
}
static int adau1977_spi_probe(struct spi_device *spi)
{
const struct spi_device_id *id = spi_get_device_id(spi);
struct regmap_config config;
if (!id)
return -EINVAL;
config = adau1977_regmap_config;
config.val_bits = 8;
config.reg_bits = 16;
config.read_flag_mask = 0x1;
return adau1977_probe(&spi->dev,
devm_regmap_init_spi(spi, &config),
id->driver_data, adau1977_spi_switch_mode);
}
static const struct spi_device_id adau1977_spi_ids[] = {
{ "adau1977", ADAU1977 },
{ "adau1978", ADAU1978 },
{ "adau1979", ADAU1978 },
{ }
};
MODULE_DEVICE_TABLE(spi, adau1977_spi_ids);
static const struct of_device_id adau1977_spi_of_match[] __maybe_unused = {
{ .compatible = "adi,adau1977" },
{ .compatible = "adi,adau1978" },
{ .compatible = "adi,adau1979" },
{ },
};
MODULE_DEVICE_TABLE(of, adau1977_spi_of_match);
static struct spi_driver adau1977_spi_driver = {
.driver = {
.name = "adau1977",
.of_match_table = of_match_ptr(adau1977_spi_of_match),
},
.probe = adau1977_spi_probe,
.id_table = adau1977_spi_ids,
};
module_spi_driver(adau1977_spi_driver);
MODULE_DESCRIPTION("ASoC ADAU1977/ADAU1978/ADAU1979 driver");
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/adau1977-spi.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020 Bootlin SA
* Author: Alexandre Belloni <[email protected]>
*/
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/regulator/consumer.h>
#include <sound/soc.h>
struct simple_mux {
struct gpio_desc *gpiod_mux;
unsigned int mux;
};
static const char * const simple_mux_texts[] = {
"Input 1", "Input 2"
};
static SOC_ENUM_SINGLE_EXT_DECL(simple_mux_enum, simple_mux_texts);
static int simple_mux_control_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kcontrol);
struct snd_soc_component *c = snd_soc_dapm_to_component(dapm);
struct simple_mux *priv = snd_soc_component_get_drvdata(c);
ucontrol->value.enumerated.item[0] = priv->mux;
return 0;
}
static int simple_mux_control_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kcontrol);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
struct snd_soc_component *c = snd_soc_dapm_to_component(dapm);
struct simple_mux *priv = snd_soc_component_get_drvdata(c);
if (ucontrol->value.enumerated.item[0] > e->items)
return -EINVAL;
if (priv->mux == ucontrol->value.enumerated.item[0])
return 0;
priv->mux = ucontrol->value.enumerated.item[0];
gpiod_set_value_cansleep(priv->gpiod_mux, priv->mux);
return snd_soc_dapm_mux_update_power(dapm, kcontrol,
ucontrol->value.enumerated.item[0],
e, NULL);
}
static unsigned int simple_mux_read(struct snd_soc_component *component,
unsigned int reg)
{
struct simple_mux *priv = snd_soc_component_get_drvdata(component);
return priv->mux;
}
static const struct snd_kcontrol_new simple_mux_mux =
SOC_DAPM_ENUM_EXT("Muxer", simple_mux_enum, simple_mux_control_get, simple_mux_control_put);
static const struct snd_soc_dapm_widget simple_mux_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("IN1"),
SND_SOC_DAPM_INPUT("IN2"),
SND_SOC_DAPM_MUX("MUX", SND_SOC_NOPM, 0, 0, &simple_mux_mux),
SND_SOC_DAPM_OUTPUT("OUT"),
};
static const struct snd_soc_dapm_route simple_mux_dapm_routes[] = {
{ "OUT", NULL, "MUX" },
{ "MUX", "Input 1", "IN1" },
{ "MUX", "Input 2", "IN2" },
};
static const struct snd_soc_component_driver simple_mux_component_driver = {
.dapm_widgets = simple_mux_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(simple_mux_dapm_widgets),
.dapm_routes = simple_mux_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(simple_mux_dapm_routes),
.read = simple_mux_read,
};
static int simple_mux_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct simple_mux *priv;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
dev_set_drvdata(dev, priv);
priv->gpiod_mux = devm_gpiod_get(dev, "mux", GPIOD_OUT_LOW);
if (IS_ERR(priv->gpiod_mux))
return dev_err_probe(dev, PTR_ERR(priv->gpiod_mux),
"Failed to get 'mux' gpio");
return devm_snd_soc_register_component(dev, &simple_mux_component_driver, NULL, 0);
}
#ifdef CONFIG_OF
static const struct of_device_id simple_mux_ids[] = {
{ .compatible = "simple-audio-mux", },
{ }
};
MODULE_DEVICE_TABLE(of, simple_mux_ids);
#endif
static struct platform_driver simple_mux_driver = {
.driver = {
.name = "simple-mux",
.of_match_table = of_match_ptr(simple_mux_ids),
},
.probe = simple_mux_probe,
};
module_platform_driver(simple_mux_driver);
MODULE_DESCRIPTION("ASoC Simple Audio Mux driver");
MODULE_AUTHOR("Alexandre Belloni <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/simple-mux.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019 Google, Inc.
*
* ChromeOS Embedded Controller codec driver.
*
* This driver uses the cros-ec interface to communicate with the ChromeOS
* EC for audio function.
*/
#include <crypto/sha2.h>
#include <linux/acpi.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_data/cros_ec_commands.h>
#include <linux/platform_data/cros_ec_proto.h>
#include <linux/platform_device.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
struct cros_ec_codec_priv {
struct device *dev;
struct cros_ec_device *ec_device;
/* common */
uint32_t ec_capabilities;
uint64_t ec_shm_addr;
uint32_t ec_shm_len;
uint64_t ap_shm_phys_addr;
uint32_t ap_shm_len;
uint64_t ap_shm_addr;
uint64_t ap_shm_last_alloc;
/* DMIC */
atomic_t dmic_probed;
/* I2S_RX */
uint32_t i2s_rx_bclk_ratio;
/* WoV */
bool wov_enabled;
uint8_t *wov_audio_shm_p;
uint32_t wov_audio_shm_len;
uint8_t wov_audio_shm_type;
uint8_t *wov_lang_shm_p;
uint32_t wov_lang_shm_len;
uint8_t wov_lang_shm_type;
struct mutex wov_dma_lock;
uint8_t wov_buf[64000];
uint32_t wov_rp, wov_wp;
size_t wov_dma_offset;
bool wov_burst_read;
struct snd_pcm_substream *wov_substream;
struct delayed_work wov_copy_work;
struct notifier_block wov_notifier;
};
static int ec_codec_capable(struct cros_ec_codec_priv *priv, uint8_t cap)
{
return priv->ec_capabilities & BIT(cap);
}
static int send_ec_host_command(struct cros_ec_device *ec_dev, uint32_t cmd,
uint8_t *out, size_t outsize,
uint8_t *in, size_t insize)
{
int ret;
struct cros_ec_command *msg;
msg = kmalloc(sizeof(*msg) + max(outsize, insize), GFP_KERNEL);
if (!msg)
return -ENOMEM;
msg->version = 0;
msg->command = cmd;
msg->outsize = outsize;
msg->insize = insize;
if (outsize)
memcpy(msg->data, out, outsize);
ret = cros_ec_cmd_xfer_status(ec_dev, msg);
if (ret < 0)
goto error;
if (in && insize)
memcpy(in, msg->data, insize);
ret = 0;
error:
kfree(msg);
return ret;
}
static int dmic_get_gain(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct cros_ec_codec_priv *priv =
snd_soc_component_get_drvdata(component);
struct ec_param_ec_codec_dmic p;
struct ec_response_ec_codec_dmic_get_gain_idx r;
int ret;
p.cmd = EC_CODEC_DMIC_GET_GAIN_IDX;
p.get_gain_idx_param.channel = EC_CODEC_DMIC_CHANNEL_0;
ret = send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC_DMIC,
(uint8_t *)&p, sizeof(p),
(uint8_t *)&r, sizeof(r));
if (ret < 0)
return ret;
ucontrol->value.integer.value[0] = r.gain;
p.cmd = EC_CODEC_DMIC_GET_GAIN_IDX;
p.get_gain_idx_param.channel = EC_CODEC_DMIC_CHANNEL_1;
ret = send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC_DMIC,
(uint8_t *)&p, sizeof(p),
(uint8_t *)&r, sizeof(r));
if (ret < 0)
return ret;
ucontrol->value.integer.value[1] = r.gain;
return 0;
}
static int dmic_put_gain(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct cros_ec_codec_priv *priv =
snd_soc_component_get_drvdata(component);
struct soc_mixer_control *control =
(struct soc_mixer_control *)kcontrol->private_value;
int max_dmic_gain = control->max;
int left = ucontrol->value.integer.value[0];
int right = ucontrol->value.integer.value[1];
struct ec_param_ec_codec_dmic p;
int ret;
if (left > max_dmic_gain || right > max_dmic_gain)
return -EINVAL;
dev_dbg(component->dev, "set mic gain to %u, %u\n", left, right);
p.cmd = EC_CODEC_DMIC_SET_GAIN_IDX;
p.set_gain_idx_param.channel = EC_CODEC_DMIC_CHANNEL_0;
p.set_gain_idx_param.gain = left;
ret = send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC_DMIC,
(uint8_t *)&p, sizeof(p), NULL, 0);
if (ret < 0)
return ret;
p.cmd = EC_CODEC_DMIC_SET_GAIN_IDX;
p.set_gain_idx_param.channel = EC_CODEC_DMIC_CHANNEL_1;
p.set_gain_idx_param.gain = right;
return send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC_DMIC,
(uint8_t *)&p, sizeof(p), NULL, 0);
}
static const DECLARE_TLV_DB_SCALE(dmic_gain_tlv, 0, 100, 0);
enum {
DMIC_CTL_GAIN = 0,
};
static struct snd_kcontrol_new dmic_controls[] = {
[DMIC_CTL_GAIN] =
SOC_DOUBLE_EXT_TLV("EC Mic Gain", SND_SOC_NOPM, SND_SOC_NOPM,
0, 0, 0, dmic_get_gain, dmic_put_gain,
dmic_gain_tlv),
};
static int dmic_probe(struct snd_soc_component *component)
{
struct cros_ec_codec_priv *priv =
snd_soc_component_get_drvdata(component);
struct device *dev = priv->dev;
struct soc_mixer_control *control;
struct ec_param_ec_codec_dmic p;
struct ec_response_ec_codec_dmic_get_max_gain r;
int ret;
if (!atomic_add_unless(&priv->dmic_probed, 1, 1))
return 0;
p.cmd = EC_CODEC_DMIC_GET_MAX_GAIN;
ret = send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC_DMIC,
(uint8_t *)&p, sizeof(p),
(uint8_t *)&r, sizeof(r));
if (ret < 0) {
dev_warn(dev, "get_max_gain() unsupported\n");
return 0;
}
dev_dbg(dev, "max gain = %d\n", r.max_gain);
control = (struct soc_mixer_control *)
dmic_controls[DMIC_CTL_GAIN].private_value;
control->max = r.max_gain;
control->platform_max = r.max_gain;
return snd_soc_add_component_controls(component,
&dmic_controls[DMIC_CTL_GAIN], 1);
}
static int i2s_rx_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct cros_ec_codec_priv *priv =
snd_soc_component_get_drvdata(component);
struct ec_param_ec_codec_i2s_rx p;
enum ec_codec_i2s_rx_sample_depth depth;
uint32_t bclk;
int ret;
if (params_rate(params) != 48000)
return -EINVAL;
switch (params_width(params)) {
case 16:
depth = EC_CODEC_I2S_RX_SAMPLE_DEPTH_16;
break;
case 24:
depth = EC_CODEC_I2S_RX_SAMPLE_DEPTH_24;
break;
default:
return -EINVAL;
}
dev_dbg(component->dev, "set depth to %u\n", depth);
p.cmd = EC_CODEC_I2S_RX_SET_SAMPLE_DEPTH;
p.set_sample_depth_param.depth = depth;
ret = send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC_I2S_RX,
(uint8_t *)&p, sizeof(p), NULL, 0);
if (ret < 0)
return ret;
if (priv->i2s_rx_bclk_ratio)
bclk = params_rate(params) * priv->i2s_rx_bclk_ratio;
else
bclk = snd_soc_params_to_bclk(params);
dev_dbg(component->dev, "set bclk to %u\n", bclk);
p.cmd = EC_CODEC_I2S_RX_SET_BCLK;
p.set_bclk_param.bclk = bclk;
return send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC_I2S_RX,
(uint8_t *)&p, sizeof(p), NULL, 0);
}
static int i2s_rx_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
{
struct snd_soc_component *component = dai->component;
struct cros_ec_codec_priv *priv =
snd_soc_component_get_drvdata(component);
priv->i2s_rx_bclk_ratio = ratio;
return 0;
}
static int i2s_rx_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct cros_ec_codec_priv *priv =
snd_soc_component_get_drvdata(component);
struct ec_param_ec_codec_i2s_rx p;
enum ec_codec_i2s_rx_daifmt daifmt;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
daifmt = EC_CODEC_I2S_RX_DAIFMT_I2S;
break;
case SND_SOC_DAIFMT_RIGHT_J:
daifmt = EC_CODEC_I2S_RX_DAIFMT_RIGHT_J;
break;
case SND_SOC_DAIFMT_LEFT_J:
daifmt = EC_CODEC_I2S_RX_DAIFMT_LEFT_J;
break;
default:
return -EINVAL;
}
dev_dbg(component->dev, "set format to %u\n", daifmt);
p.cmd = EC_CODEC_I2S_RX_SET_DAIFMT;
p.set_daifmt_param.daifmt = daifmt;
return send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC_I2S_RX,
(uint8_t *)&p, sizeof(p), NULL, 0);
}
static const struct snd_soc_dai_ops i2s_rx_dai_ops = {
.hw_params = i2s_rx_hw_params,
.set_fmt = i2s_rx_set_fmt,
.set_bclk_ratio = i2s_rx_set_bclk_ratio,
};
static int i2s_rx_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct cros_ec_codec_priv *priv =
snd_soc_component_get_drvdata(component);
struct ec_param_ec_codec_i2s_rx p = {};
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
dev_dbg(component->dev, "enable I2S RX\n");
p.cmd = EC_CODEC_I2S_RX_ENABLE;
break;
case SND_SOC_DAPM_PRE_PMD:
dev_dbg(component->dev, "disable I2S RX\n");
p.cmd = EC_CODEC_I2S_RX_DISABLE;
break;
default:
return 0;
}
return send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC_I2S_RX,
(uint8_t *)&p, sizeof(p), NULL, 0);
}
static struct snd_soc_dapm_widget i2s_rx_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("DMIC"),
SND_SOC_DAPM_SUPPLY("I2S RX Enable", SND_SOC_NOPM, 0, 0, i2s_rx_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_AIF_OUT("I2S RX", "I2S Capture", 0, SND_SOC_NOPM, 0, 0),
};
static struct snd_soc_dapm_route i2s_rx_dapm_routes[] = {
{"I2S RX", NULL, "DMIC"},
{"I2S RX", NULL, "I2S RX Enable"},
};
static struct snd_soc_dai_driver i2s_rx_dai_driver = {
.name = "EC Codec I2S RX",
.capture = {
.stream_name = "I2S Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
},
.ops = &i2s_rx_dai_ops,
};
static int i2s_rx_probe(struct snd_soc_component *component)
{
return dmic_probe(component);
}
static const struct snd_soc_component_driver i2s_rx_component_driver = {
.probe = i2s_rx_probe,
.dapm_widgets = i2s_rx_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(i2s_rx_dapm_widgets),
.dapm_routes = i2s_rx_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(i2s_rx_dapm_routes),
.endianness = 1,
};
static void *wov_map_shm(struct cros_ec_codec_priv *priv,
uint8_t shm_id, uint32_t *len, uint8_t *type)
{
struct ec_param_ec_codec p;
struct ec_response_ec_codec_get_shm_addr r;
uint32_t req, offset;
p.cmd = EC_CODEC_GET_SHM_ADDR;
p.get_shm_addr_param.shm_id = shm_id;
if (send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC,
(uint8_t *)&p, sizeof(p),
(uint8_t *)&r, sizeof(r)) < 0) {
dev_err(priv->dev, "failed to EC_CODEC_GET_SHM_ADDR\n");
return NULL;
}
dev_dbg(priv->dev, "phys_addr=%#llx, len=%#x\n", r.phys_addr, r.len);
*len = r.len;
*type = r.type;
switch (r.type) {
case EC_CODEC_SHM_TYPE_EC_RAM:
return (void __force *)devm_ioremap_wc(priv->dev,
r.phys_addr + priv->ec_shm_addr, r.len);
case EC_CODEC_SHM_TYPE_SYSTEM_RAM:
if (r.phys_addr) {
dev_err(priv->dev, "unknown status\n");
return NULL;
}
req = round_up(r.len, PAGE_SIZE);
dev_dbg(priv->dev, "round up from %u to %u\n", r.len, req);
if (priv->ap_shm_last_alloc + req >
priv->ap_shm_phys_addr + priv->ap_shm_len) {
dev_err(priv->dev, "insufficient space for AP SHM\n");
return NULL;
}
dev_dbg(priv->dev, "alloc AP SHM addr=%#llx, len=%#x\n",
priv->ap_shm_last_alloc, req);
p.cmd = EC_CODEC_SET_SHM_ADDR;
p.set_shm_addr_param.phys_addr = priv->ap_shm_last_alloc;
p.set_shm_addr_param.len = req;
p.set_shm_addr_param.shm_id = shm_id;
if (send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC,
(uint8_t *)&p, sizeof(p),
NULL, 0) < 0) {
dev_err(priv->dev, "failed to EC_CODEC_SET_SHM_ADDR\n");
return NULL;
}
/*
* Note: EC codec only requests for `r.len' but we allocate
* round up PAGE_SIZE `req'.
*/
offset = priv->ap_shm_last_alloc - priv->ap_shm_phys_addr;
priv->ap_shm_last_alloc += req;
return (void *)(uintptr_t)(priv->ap_shm_addr + offset);
default:
return NULL;
}
}
static bool wov_queue_full(struct cros_ec_codec_priv *priv)
{
return ((priv->wov_wp + 1) % sizeof(priv->wov_buf)) == priv->wov_rp;
}
static size_t wov_queue_size(struct cros_ec_codec_priv *priv)
{
if (priv->wov_wp >= priv->wov_rp)
return priv->wov_wp - priv->wov_rp;
else
return sizeof(priv->wov_buf) - priv->wov_rp + priv->wov_wp;
}
static void wov_queue_dequeue(struct cros_ec_codec_priv *priv, size_t len)
{
struct snd_pcm_runtime *runtime = priv->wov_substream->runtime;
size_t req;
while (len) {
req = min(len, runtime->dma_bytes - priv->wov_dma_offset);
if (priv->wov_wp >= priv->wov_rp)
req = min(req, (size_t)priv->wov_wp - priv->wov_rp);
else
req = min(req, sizeof(priv->wov_buf) - priv->wov_rp);
memcpy(runtime->dma_area + priv->wov_dma_offset,
priv->wov_buf + priv->wov_rp, req);
priv->wov_dma_offset += req;
if (priv->wov_dma_offset == runtime->dma_bytes)
priv->wov_dma_offset = 0;
priv->wov_rp += req;
if (priv->wov_rp == sizeof(priv->wov_buf))
priv->wov_rp = 0;
len -= req;
}
snd_pcm_period_elapsed(priv->wov_substream);
}
static void wov_queue_try_dequeue(struct cros_ec_codec_priv *priv)
{
size_t period_bytes = snd_pcm_lib_period_bytes(priv->wov_substream);
while (period_bytes && wov_queue_size(priv) >= period_bytes) {
wov_queue_dequeue(priv, period_bytes);
period_bytes = snd_pcm_lib_period_bytes(priv->wov_substream);
}
}
static void wov_queue_enqueue(struct cros_ec_codec_priv *priv,
uint8_t *addr, size_t len, bool iomem)
{
size_t req;
while (len) {
if (wov_queue_full(priv)) {
wov_queue_try_dequeue(priv);
if (wov_queue_full(priv)) {
dev_err(priv->dev, "overrun detected\n");
return;
}
}
if (priv->wov_wp >= priv->wov_rp)
req = sizeof(priv->wov_buf) - priv->wov_wp;
else
/* Note: waste 1-byte to differentiate full and empty */
req = priv->wov_rp - priv->wov_wp - 1;
req = min(req, len);
if (iomem)
memcpy_fromio(priv->wov_buf + priv->wov_wp,
(void __force __iomem *)addr, req);
else
memcpy(priv->wov_buf + priv->wov_wp, addr, req);
priv->wov_wp += req;
if (priv->wov_wp == sizeof(priv->wov_buf))
priv->wov_wp = 0;
addr += req;
len -= req;
}
wov_queue_try_dequeue(priv);
}
static int wov_read_audio_shm(struct cros_ec_codec_priv *priv)
{
struct ec_param_ec_codec_wov p;
struct ec_response_ec_codec_wov_read_audio_shm r;
int ret;
p.cmd = EC_CODEC_WOV_READ_AUDIO_SHM;
ret = send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC_WOV,
(uint8_t *)&p, sizeof(p),
(uint8_t *)&r, sizeof(r));
if (ret) {
dev_err(priv->dev, "failed to EC_CODEC_WOV_READ_AUDIO_SHM\n");
return ret;
}
if (!r.len)
dev_dbg(priv->dev, "no data, sleep\n");
else
wov_queue_enqueue(priv, priv->wov_audio_shm_p + r.offset, r.len,
priv->wov_audio_shm_type == EC_CODEC_SHM_TYPE_EC_RAM);
return -EAGAIN;
}
static int wov_read_audio(struct cros_ec_codec_priv *priv)
{
struct ec_param_ec_codec_wov p;
struct ec_response_ec_codec_wov_read_audio r;
int remain = priv->wov_burst_read ? 16000 : 320;
int ret;
while (remain >= 0) {
p.cmd = EC_CODEC_WOV_READ_AUDIO;
ret = send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC_WOV,
(uint8_t *)&p, sizeof(p),
(uint8_t *)&r, sizeof(r));
if (ret) {
dev_err(priv->dev,
"failed to EC_CODEC_WOV_READ_AUDIO\n");
return ret;
}
if (!r.len) {
dev_dbg(priv->dev, "no data, sleep\n");
priv->wov_burst_read = false;
break;
}
wov_queue_enqueue(priv, r.buf, r.len, false);
remain -= r.len;
}
return -EAGAIN;
}
static void wov_copy_work(struct work_struct *w)
{
struct cros_ec_codec_priv *priv =
container_of(w, struct cros_ec_codec_priv, wov_copy_work.work);
int ret;
mutex_lock(&priv->wov_dma_lock);
if (!priv->wov_substream) {
dev_warn(priv->dev, "no pcm substream\n");
goto leave;
}
if (ec_codec_capable(priv, EC_CODEC_CAP_WOV_AUDIO_SHM))
ret = wov_read_audio_shm(priv);
else
ret = wov_read_audio(priv);
if (ret == -EAGAIN)
schedule_delayed_work(&priv->wov_copy_work,
msecs_to_jiffies(10));
else if (ret)
dev_err(priv->dev, "failed to read audio data\n");
leave:
mutex_unlock(&priv->wov_dma_lock);
}
static int wov_enable_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *c = snd_soc_kcontrol_component(kcontrol);
struct cros_ec_codec_priv *priv = snd_soc_component_get_drvdata(c);
ucontrol->value.integer.value[0] = priv->wov_enabled;
return 0;
}
static int wov_enable_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *c = snd_soc_kcontrol_component(kcontrol);
struct cros_ec_codec_priv *priv = snd_soc_component_get_drvdata(c);
int enabled = ucontrol->value.integer.value[0];
struct ec_param_ec_codec_wov p;
int ret;
if (priv->wov_enabled != enabled) {
if (enabled)
p.cmd = EC_CODEC_WOV_ENABLE;
else
p.cmd = EC_CODEC_WOV_DISABLE;
ret = send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC_WOV,
(uint8_t *)&p, sizeof(p), NULL, 0);
if (ret) {
dev_err(priv->dev, "failed to %s wov\n",
enabled ? "enable" : "disable");
return ret;
}
priv->wov_enabled = enabled;
}
return 0;
}
static int wov_set_lang_shm(struct cros_ec_codec_priv *priv,
uint8_t *buf, size_t size, uint8_t *digest)
{
struct ec_param_ec_codec_wov p;
struct ec_param_ec_codec_wov_set_lang_shm *pp = &p.set_lang_shm_param;
int ret;
if (size > priv->wov_lang_shm_len) {
dev_err(priv->dev, "no enough SHM size: %d\n",
priv->wov_lang_shm_len);
return -EIO;
}
switch (priv->wov_lang_shm_type) {
case EC_CODEC_SHM_TYPE_EC_RAM:
memcpy_toio((void __force __iomem *)priv->wov_lang_shm_p,
buf, size);
memset_io((void __force __iomem *)priv->wov_lang_shm_p + size,
0, priv->wov_lang_shm_len - size);
break;
case EC_CODEC_SHM_TYPE_SYSTEM_RAM:
memcpy(priv->wov_lang_shm_p, buf, size);
memset(priv->wov_lang_shm_p + size, 0,
priv->wov_lang_shm_len - size);
/* make sure write to memory before calling host command */
wmb();
break;
}
p.cmd = EC_CODEC_WOV_SET_LANG_SHM;
memcpy(pp->hash, digest, SHA256_DIGEST_SIZE);
pp->total_len = size;
ret = send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC_WOV,
(uint8_t *)&p, sizeof(p), NULL, 0);
if (ret) {
dev_err(priv->dev, "failed to EC_CODEC_WOV_SET_LANG_SHM\n");
return ret;
}
return 0;
}
static int wov_set_lang(struct cros_ec_codec_priv *priv,
uint8_t *buf, size_t size, uint8_t *digest)
{
struct ec_param_ec_codec_wov p;
struct ec_param_ec_codec_wov_set_lang *pp = &p.set_lang_param;
size_t i, req;
int ret;
for (i = 0; i < size; i += req) {
req = min(size - i, ARRAY_SIZE(pp->buf));
p.cmd = EC_CODEC_WOV_SET_LANG;
memcpy(pp->hash, digest, SHA256_DIGEST_SIZE);
pp->total_len = size;
pp->offset = i;
memcpy(pp->buf, buf + i, req);
pp->len = req;
ret = send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC_WOV,
(uint8_t *)&p, sizeof(p), NULL, 0);
if (ret) {
dev_err(priv->dev, "failed to EC_CODEC_WOV_SET_LANG\n");
return ret;
}
}
return 0;
}
static int wov_hotword_model_put(struct snd_kcontrol *kcontrol,
const unsigned int __user *bytes,
unsigned int size)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct cros_ec_codec_priv *priv =
snd_soc_component_get_drvdata(component);
struct ec_param_ec_codec_wov p;
struct ec_response_ec_codec_wov_get_lang r;
uint8_t digest[SHA256_DIGEST_SIZE];
uint8_t *buf;
int ret;
/* Skips the TLV header. */
bytes += 2;
size -= 8;
dev_dbg(priv->dev, "%s: size=%d\n", __func__, size);
buf = memdup_user(bytes, size);
if (IS_ERR(buf))
return PTR_ERR(buf);
sha256(buf, size, digest);
dev_dbg(priv->dev, "hash=%*phN\n", SHA256_DIGEST_SIZE, digest);
p.cmd = EC_CODEC_WOV_GET_LANG;
ret = send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC_WOV,
(uint8_t *)&p, sizeof(p),
(uint8_t *)&r, sizeof(r));
if (ret)
goto leave;
if (memcmp(digest, r.hash, SHA256_DIGEST_SIZE) == 0) {
dev_dbg(priv->dev, "not updated");
goto leave;
}
if (ec_codec_capable(priv, EC_CODEC_CAP_WOV_LANG_SHM))
ret = wov_set_lang_shm(priv, buf, size, digest);
else
ret = wov_set_lang(priv, buf, size, digest);
leave:
kfree(buf);
return ret;
}
static struct snd_kcontrol_new wov_controls[] = {
SOC_SINGLE_BOOL_EXT("Wake-on-Voice Switch", 0,
wov_enable_get, wov_enable_put),
SND_SOC_BYTES_TLV("Hotword Model", 0x11000, NULL,
wov_hotword_model_put),
};
static struct snd_soc_dai_driver wov_dai_driver = {
.name = "Wake on Voice",
.capture = {
.stream_name = "WoV Capture",
.channels_min = 1,
.channels_max = 1,
.rates = SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
};
static int wov_host_event(struct notifier_block *nb,
unsigned long queued_during_suspend, void *notify)
{
struct cros_ec_codec_priv *priv =
container_of(nb, struct cros_ec_codec_priv, wov_notifier);
u32 host_event;
dev_dbg(priv->dev, "%s\n", __func__);
host_event = cros_ec_get_host_event(priv->ec_device);
if (host_event & EC_HOST_EVENT_MASK(EC_HOST_EVENT_WOV)) {
schedule_delayed_work(&priv->wov_copy_work, 0);
return NOTIFY_OK;
} else {
return NOTIFY_DONE;
}
}
static int wov_probe(struct snd_soc_component *component)
{
struct cros_ec_codec_priv *priv =
snd_soc_component_get_drvdata(component);
int ret;
mutex_init(&priv->wov_dma_lock);
INIT_DELAYED_WORK(&priv->wov_copy_work, wov_copy_work);
priv->wov_notifier.notifier_call = wov_host_event;
ret = blocking_notifier_chain_register(
&priv->ec_device->event_notifier, &priv->wov_notifier);
if (ret)
return ret;
if (ec_codec_capable(priv, EC_CODEC_CAP_WOV_LANG_SHM)) {
priv->wov_lang_shm_p = wov_map_shm(priv,
EC_CODEC_SHM_ID_WOV_LANG,
&priv->wov_lang_shm_len,
&priv->wov_lang_shm_type);
if (!priv->wov_lang_shm_p)
return -EFAULT;
}
if (ec_codec_capable(priv, EC_CODEC_CAP_WOV_AUDIO_SHM)) {
priv->wov_audio_shm_p = wov_map_shm(priv,
EC_CODEC_SHM_ID_WOV_AUDIO,
&priv->wov_audio_shm_len,
&priv->wov_audio_shm_type);
if (!priv->wov_audio_shm_p)
return -EFAULT;
}
return dmic_probe(component);
}
static void wov_remove(struct snd_soc_component *component)
{
struct cros_ec_codec_priv *priv =
snd_soc_component_get_drvdata(component);
blocking_notifier_chain_unregister(
&priv->ec_device->event_notifier, &priv->wov_notifier);
}
static int wov_pcm_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
static const struct snd_pcm_hardware hw_param = {
.info = SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_MMAP_VALID,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.rates = SNDRV_PCM_RATE_16000,
.channels_min = 1,
.channels_max = 1,
.period_bytes_min = PAGE_SIZE,
.period_bytes_max = 0x20000 / 8,
.periods_min = 8,
.periods_max = 8,
.buffer_bytes_max = 0x20000,
};
return snd_soc_set_runtime_hwparams(substream, &hw_param);
}
static int wov_pcm_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *hw_params)
{
struct cros_ec_codec_priv *priv =
snd_soc_component_get_drvdata(component);
mutex_lock(&priv->wov_dma_lock);
priv->wov_substream = substream;
priv->wov_rp = priv->wov_wp = 0;
priv->wov_dma_offset = 0;
priv->wov_burst_read = true;
mutex_unlock(&priv->wov_dma_lock);
return 0;
}
static int wov_pcm_hw_free(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct cros_ec_codec_priv *priv =
snd_soc_component_get_drvdata(component);
mutex_lock(&priv->wov_dma_lock);
wov_queue_dequeue(priv, wov_queue_size(priv));
priv->wov_substream = NULL;
mutex_unlock(&priv->wov_dma_lock);
cancel_delayed_work_sync(&priv->wov_copy_work);
return 0;
}
static snd_pcm_uframes_t wov_pcm_pointer(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct cros_ec_codec_priv *priv =
snd_soc_component_get_drvdata(component);
return bytes_to_frames(runtime, priv->wov_dma_offset);
}
static int wov_pcm_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_VMALLOC,
NULL, 0, 0);
return 0;
}
static const struct snd_soc_component_driver wov_component_driver = {
.probe = wov_probe,
.remove = wov_remove,
.controls = wov_controls,
.num_controls = ARRAY_SIZE(wov_controls),
.open = wov_pcm_open,
.hw_params = wov_pcm_hw_params,
.hw_free = wov_pcm_hw_free,
.pointer = wov_pcm_pointer,
.pcm_construct = wov_pcm_new,
};
static int cros_ec_codec_platform_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct cros_ec_device *ec_device = dev_get_drvdata(pdev->dev.parent);
struct cros_ec_codec_priv *priv;
struct ec_param_ec_codec p;
struct ec_response_ec_codec_get_capabilities r;
int ret;
#ifdef CONFIG_OF
struct device_node *node;
struct resource res;
u64 ec_shm_size;
const __be32 *regaddr_p;
#endif
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
#ifdef CONFIG_OF
regaddr_p = of_get_address(dev->of_node, 0, &ec_shm_size, NULL);
if (regaddr_p) {
priv->ec_shm_addr = of_read_number(regaddr_p, 2);
priv->ec_shm_len = ec_shm_size;
dev_dbg(dev, "ec_shm_addr=%#llx len=%#x\n",
priv->ec_shm_addr, priv->ec_shm_len);
}
node = of_parse_phandle(dev->of_node, "memory-region", 0);
if (node) {
ret = of_address_to_resource(node, 0, &res);
if (!ret) {
priv->ap_shm_phys_addr = res.start;
priv->ap_shm_len = resource_size(&res);
priv->ap_shm_addr =
(uint64_t)(uintptr_t)devm_ioremap_wc(
dev, priv->ap_shm_phys_addr,
priv->ap_shm_len);
priv->ap_shm_last_alloc = priv->ap_shm_phys_addr;
dev_dbg(dev, "ap_shm_phys_addr=%#llx len=%#x\n",
priv->ap_shm_phys_addr, priv->ap_shm_len);
}
of_node_put(node);
}
#endif
priv->dev = dev;
priv->ec_device = ec_device;
atomic_set(&priv->dmic_probed, 0);
p.cmd = EC_CODEC_GET_CAPABILITIES;
ret = send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC,
(uint8_t *)&p, sizeof(p),
(uint8_t *)&r, sizeof(r));
if (ret) {
dev_err(dev, "failed to EC_CODEC_GET_CAPABILITIES\n");
return ret;
}
priv->ec_capabilities = r.capabilities;
/* Reset EC codec i2s rx. */
p.cmd = EC_CODEC_I2S_RX_RESET;
ret = send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC_I2S_RX,
(uint8_t *)&p, sizeof(p), NULL, 0);
if (ret == -ENOPROTOOPT) {
dev_info(dev,
"Missing reset command. Please update EC firmware.\n");
} else if (ret) {
dev_err(dev, "failed to EC_CODEC_I2S_RESET: %d\n", ret);
return ret;
}
platform_set_drvdata(pdev, priv);
ret = devm_snd_soc_register_component(dev, &i2s_rx_component_driver,
&i2s_rx_dai_driver, 1);
if (ret)
return ret;
return devm_snd_soc_register_component(dev, &wov_component_driver,
&wov_dai_driver, 1);
}
#ifdef CONFIG_OF
static const struct of_device_id cros_ec_codec_of_match[] = {
{ .compatible = "google,cros-ec-codec" },
{},
};
MODULE_DEVICE_TABLE(of, cros_ec_codec_of_match);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id cros_ec_codec_acpi_id[] = {
{ "GOOG0013", 0 },
{ }
};
MODULE_DEVICE_TABLE(acpi, cros_ec_codec_acpi_id);
#endif
static struct platform_driver cros_ec_codec_platform_driver = {
.driver = {
.name = "cros-ec-codec",
.of_match_table = of_match_ptr(cros_ec_codec_of_match),
.acpi_match_table = ACPI_PTR(cros_ec_codec_acpi_id),
},
.probe = cros_ec_codec_platform_probe,
};
module_platform_driver(cros_ec_codec_platform_driver);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("ChromeOS EC codec driver");
MODULE_AUTHOR("Cheng-Yi Chiang <[email protected]>");
MODULE_ALIAS("platform:cros-ec-codec");
| linux-master | sound/soc/codecs/cros_ec_codec.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* 88pm860x-codec.c -- 88PM860x ALSA SoC Audio Driver
*
* Copyright 2010 Marvell International Ltd.
* Author: Haojian Zhuang <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/mfd/88pm860x.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <sound/initval.h>
#include <sound/jack.h>
#include <trace/events/asoc.h>
#include "88pm860x-codec.h"
#define MAX_NAME_LEN 20
#define REG_CACHE_SIZE 0x40
#define REG_CACHE_BASE 0xb0
/* Status Register 1 (0x01) */
#define REG_STATUS_1 0x01
#define MIC_STATUS (1 << 7)
#define HOOK_STATUS (1 << 6)
#define HEADSET_STATUS (1 << 5)
/* Mic Detection Register (0x37) */
#define REG_MIC_DET 0x37
#define CONTINUOUS_POLLING (3 << 1)
#define EN_MIC_DET (1 << 0)
#define MICDET_MASK 0x07
/* Headset Detection Register (0x38) */
#define REG_HS_DET 0x38
#define EN_HS_DET (1 << 0)
/* Misc2 Register (0x42) */
#define REG_MISC2 0x42
#define AUDIO_PLL (1 << 5)
#define AUDIO_SECTION_RESET (1 << 4)
#define AUDIO_SECTION_ON (1 << 3)
/* PCM Interface Register 2 (0xb1) */
#define PCM_INF2_BCLK (1 << 6) /* Bit clock polarity */
#define PCM_INF2_FS (1 << 5) /* Frame Sync polarity */
#define PCM_INF2_MASTER (1 << 4) /* Master / Slave */
#define PCM_INF2_18WL (1 << 3) /* 18 / 16 bits */
#define PCM_GENERAL_I2S 0
#define PCM_EXACT_I2S 1
#define PCM_LEFT_I2S 2
#define PCM_RIGHT_I2S 3
#define PCM_SHORT_FS 4
#define PCM_LONG_FS 5
#define PCM_MODE_MASK 7
/* I2S Interface Register 4 (0xbe) */
#define I2S_EQU_BYP (1 << 6)
/* DAC Offset Register (0xcb) */
#define DAC_MUTE (1 << 7)
#define MUTE_LEFT (1 << 6)
#define MUTE_RIGHT (1 << 2)
/* ADC Analog Register 1 (0xd0) */
#define REG_ADC_ANA_1 0xd0
#define MIC1BIAS_MASK 0x60
/* Earpiece/Speaker Control Register 2 (0xda) */
#define REG_EAR2 0xda
#define RSYNC_CHANGE (1 << 2)
/* Audio Supplies Register 2 (0xdc) */
#define REG_SUPPLIES2 0xdc
#define LDO15_READY (1 << 4)
#define LDO15_EN (1 << 3)
#define CPUMP_READY (1 << 2)
#define CPUMP_EN (1 << 1)
#define AUDIO_EN (1 << 0)
#define SUPPLY_MASK (LDO15_EN | CPUMP_EN | AUDIO_EN)
/* Audio Enable Register 1 (0xdd) */
#define ADC_MOD_RIGHT (1 << 1)
#define ADC_MOD_LEFT (1 << 0)
/* Audio Enable Register 2 (0xde) */
#define ADC_LEFT (1 << 5)
#define ADC_RIGHT (1 << 4)
/* DAC Enable Register 2 (0xe1) */
#define DAC_LEFT (1 << 5)
#define DAC_RIGHT (1 << 4)
#define MODULATOR (1 << 3)
/* Shorts Register (0xeb) */
#define REG_SHORTS 0xeb
#define CLR_SHORT_LO2 (1 << 7)
#define SHORT_LO2 (1 << 6)
#define CLR_SHORT_LO1 (1 << 5)
#define SHORT_LO1 (1 << 4)
#define CLR_SHORT_HS2 (1 << 3)
#define SHORT_HS2 (1 << 2)
#define CLR_SHORT_HS1 (1 << 1)
#define SHORT_HS1 (1 << 0)
/*
* This widget should be just after DAC & PGA in DAPM power-on sequence and
* before DAC & PGA in DAPM power-off sequence.
*/
#define PM860X_DAPM_OUTPUT(wname, wevent) \
SND_SOC_DAPM_PGA_E(wname, SND_SOC_NOPM, 0, 0, NULL, 0, wevent, \
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD)
struct pm860x_det {
struct snd_soc_jack *hp_jack;
struct snd_soc_jack *mic_jack;
int hp_det;
int mic_det;
int hook_det;
int hs_shrt;
int lo_shrt;
};
struct pm860x_priv {
unsigned int sysclk;
unsigned int pcmclk;
unsigned int dir;
unsigned int filter;
struct snd_soc_component *component;
struct i2c_client *i2c;
struct regmap *regmap;
struct pm860x_chip *chip;
struct pm860x_det det;
int irq[4];
unsigned char name[4][MAX_NAME_LEN];
};
/* -9450dB to 0dB in 150dB steps ( mute instead of -9450dB) */
static const DECLARE_TLV_DB_SCALE(dpga_tlv, -9450, 150, 1);
/* -9dB to 0db in 3dB steps */
static const DECLARE_TLV_DB_SCALE(adc_tlv, -900, 300, 0);
/* {-23, -17, -13.5, -11, -9, -6, -3, 0}dB */
static const DECLARE_TLV_DB_RANGE(mic_tlv,
0, 0, TLV_DB_SCALE_ITEM(-2300, 0, 0),
1, 1, TLV_DB_SCALE_ITEM(-1700, 0, 0),
2, 2, TLV_DB_SCALE_ITEM(-1350, 0, 0),
3, 3, TLV_DB_SCALE_ITEM(-1100, 0, 0),
4, 7, TLV_DB_SCALE_ITEM(-900, 300, 0)
);
/* {0, 0, 0, -6, 0, 6, 12, 18}dB */
static const DECLARE_TLV_DB_RANGE(aux_tlv,
0, 2, TLV_DB_SCALE_ITEM(0, 0, 0),
3, 7, TLV_DB_SCALE_ITEM(-600, 600, 0)
);
/* {-16, -13, -10, -7, -5.2, -3,3, -2.2, 0}dB, mute instead of -16dB */
static const DECLARE_TLV_DB_RANGE(out_tlv,
0, 3, TLV_DB_SCALE_ITEM(-1600, 300, 1),
4, 4, TLV_DB_SCALE_ITEM(-520, 0, 0),
5, 5, TLV_DB_SCALE_ITEM(-330, 0, 0),
6, 7, TLV_DB_SCALE_ITEM(-220, 220, 0)
);
static const DECLARE_TLV_DB_RANGE(st_tlv,
0, 1, TLV_DB_SCALE_ITEM(-12041, 602, 0),
2, 3, TLV_DB_SCALE_ITEM(-11087, 250, 0),
4, 5, TLV_DB_SCALE_ITEM(-10643, 158, 0),
6, 7, TLV_DB_SCALE_ITEM(-10351, 116, 0),
8, 9, TLV_DB_SCALE_ITEM(-10133, 92, 0),
10, 13, TLV_DB_SCALE_ITEM(-9958, 70, 0),
14, 17, TLV_DB_SCALE_ITEM(-9689, 53, 0),
18, 271, TLV_DB_SCALE_ITEM(-9484, 37, 0)
);
/* Sidetone Gain = M * 2^(-5-N) */
struct st_gain {
unsigned int db;
unsigned int m;
unsigned int n;
};
static struct st_gain st_table[] = {
{-12041, 1, 15}, {-11439, 1, 14}, {-11087, 3, 15}, {-10837, 1, 13},
{-10643, 5, 15}, {-10485, 3, 14}, {-10351, 7, 15}, {-10235, 1, 12},
{-10133, 9, 15}, {-10041, 5, 14}, { -9958, 11, 15}, { -9883, 3, 13},
{ -9813, 13, 15}, { -9749, 7, 14}, { -9689, 15, 15}, { -9633, 1, 11},
{ -9580, 17, 15}, { -9531, 9, 14}, { -9484, 19, 15}, { -9439, 5, 13},
{ -9397, 21, 15}, { -9356, 11, 14}, { -9318, 23, 15}, { -9281, 3, 12},
{ -9245, 25, 15}, { -9211, 13, 14}, { -9178, 27, 15}, { -9147, 7, 13},
{ -9116, 29, 15}, { -9087, 15, 14}, { -9058, 31, 15}, { -9031, 1, 10},
{ -8978, 17, 14}, { -8929, 9, 13}, { -8882, 19, 14}, { -8837, 5, 12},
{ -8795, 21, 14}, { -8754, 11, 13}, { -8716, 23, 14}, { -8679, 3, 11},
{ -8643, 25, 14}, { -8609, 13, 13}, { -8576, 27, 14}, { -8545, 7, 12},
{ -8514, 29, 14}, { -8485, 15, 13}, { -8456, 31, 14}, { -8429, 1, 9},
{ -8376, 17, 13}, { -8327, 9, 12}, { -8280, 19, 13}, { -8235, 5, 11},
{ -8193, 21, 13}, { -8152, 11, 12}, { -8114, 23, 13}, { -8077, 3, 10},
{ -8041, 25, 13}, { -8007, 13, 12}, { -7974, 27, 13}, { -7943, 7, 11},
{ -7912, 29, 13}, { -7883, 15, 12}, { -7854, 31, 13}, { -7827, 1, 8},
{ -7774, 17, 12}, { -7724, 9, 11}, { -7678, 19, 12}, { -7633, 5, 10},
{ -7591, 21, 12}, { -7550, 11, 11}, { -7512, 23, 12}, { -7475, 3, 9},
{ -7439, 25, 12}, { -7405, 13, 11}, { -7372, 27, 12}, { -7341, 7, 10},
{ -7310, 29, 12}, { -7281, 15, 11}, { -7252, 31, 12}, { -7225, 1, 7},
{ -7172, 17, 11}, { -7122, 9, 10}, { -7075, 19, 11}, { -7031, 5, 9},
{ -6989, 21, 11}, { -6948, 11, 10}, { -6910, 23, 11}, { -6873, 3, 8},
{ -6837, 25, 11}, { -6803, 13, 10}, { -6770, 27, 11}, { -6739, 7, 9},
{ -6708, 29, 11}, { -6679, 15, 10}, { -6650, 31, 11}, { -6623, 1, 6},
{ -6570, 17, 10}, { -6520, 9, 9}, { -6473, 19, 10}, { -6429, 5, 8},
{ -6386, 21, 10}, { -6346, 11, 9}, { -6307, 23, 10}, { -6270, 3, 7},
{ -6235, 25, 10}, { -6201, 13, 9}, { -6168, 27, 10}, { -6137, 7, 8},
{ -6106, 29, 10}, { -6077, 15, 9}, { -6048, 31, 10}, { -6021, 1, 5},
{ -5968, 17, 9}, { -5918, 9, 8}, { -5871, 19, 9}, { -5827, 5, 7},
{ -5784, 21, 9}, { -5744, 11, 8}, { -5705, 23, 9}, { -5668, 3, 6},
{ -5633, 25, 9}, { -5599, 13, 8}, { -5566, 27, 9}, { -5535, 7, 7},
{ -5504, 29, 9}, { -5475, 15, 8}, { -5446, 31, 9}, { -5419, 1, 4},
{ -5366, 17, 8}, { -5316, 9, 7}, { -5269, 19, 8}, { -5225, 5, 6},
{ -5182, 21, 8}, { -5142, 11, 7}, { -5103, 23, 8}, { -5066, 3, 5},
{ -5031, 25, 8}, { -4997, 13, 7}, { -4964, 27, 8}, { -4932, 7, 6},
{ -4902, 29, 8}, { -4873, 15, 7}, { -4844, 31, 8}, { -4816, 1, 3},
{ -4764, 17, 7}, { -4714, 9, 6}, { -4667, 19, 7}, { -4623, 5, 5},
{ -4580, 21, 7}, { -4540, 11, 6}, { -4501, 23, 7}, { -4464, 3, 4},
{ -4429, 25, 7}, { -4395, 13, 6}, { -4362, 27, 7}, { -4330, 7, 5},
{ -4300, 29, 7}, { -4270, 15, 6}, { -4242, 31, 7}, { -4214, 1, 2},
{ -4162, 17, 6}, { -4112, 9, 5}, { -4065, 19, 6}, { -4021, 5, 4},
{ -3978, 21, 6}, { -3938, 11, 5}, { -3899, 23, 6}, { -3862, 3, 3},
{ -3827, 25, 6}, { -3793, 13, 5}, { -3760, 27, 6}, { -3728, 7, 4},
{ -3698, 29, 6}, { -3668, 15, 5}, { -3640, 31, 6}, { -3612, 1, 1},
{ -3560, 17, 5}, { -3510, 9, 4}, { -3463, 19, 5}, { -3419, 5, 3},
{ -3376, 21, 5}, { -3336, 11, 4}, { -3297, 23, 5}, { -3260, 3, 2},
{ -3225, 25, 5}, { -3191, 13, 4}, { -3158, 27, 5}, { -3126, 7, 3},
{ -3096, 29, 5}, { -3066, 15, 4}, { -3038, 31, 5}, { -3010, 1, 0},
{ -2958, 17, 4}, { -2908, 9, 3}, { -2861, 19, 4}, { -2816, 5, 2},
{ -2774, 21, 4}, { -2734, 11, 3}, { -2695, 23, 4}, { -2658, 3, 1},
{ -2623, 25, 4}, { -2589, 13, 3}, { -2556, 27, 4}, { -2524, 7, 2},
{ -2494, 29, 4}, { -2464, 15, 3}, { -2436, 31, 4}, { -2408, 2, 0},
{ -2356, 17, 3}, { -2306, 9, 2}, { -2259, 19, 3}, { -2214, 5, 1},
{ -2172, 21, 3}, { -2132, 11, 2}, { -2093, 23, 3}, { -2056, 3, 0},
{ -2021, 25, 3}, { -1987, 13, 2}, { -1954, 27, 3}, { -1922, 7, 1},
{ -1892, 29, 3}, { -1862, 15, 2}, { -1834, 31, 3}, { -1806, 4, 0},
{ -1754, 17, 2}, { -1704, 9, 1}, { -1657, 19, 2}, { -1612, 5, 0},
{ -1570, 21, 2}, { -1530, 11, 1}, { -1491, 23, 2}, { -1454, 6, 0},
{ -1419, 25, 2}, { -1384, 13, 1}, { -1352, 27, 2}, { -1320, 7, 0},
{ -1290, 29, 2}, { -1260, 15, 1}, { -1232, 31, 2}, { -1204, 8, 0},
{ -1151, 17, 1}, { -1102, 9, 0}, { -1055, 19, 1}, { -1010, 10, 0},
{ -968, 21, 1}, { -928, 11, 0}, { -889, 23, 1}, { -852, 12, 0},
{ -816, 25, 1}, { -782, 13, 0}, { -750, 27, 1}, { -718, 14, 0},
{ -688, 29, 1}, { -658, 15, 0}, { -630, 31, 1}, { -602, 16, 0},
{ -549, 17, 0}, { -500, 18, 0}, { -453, 19, 0}, { -408, 20, 0},
{ -366, 21, 0}, { -325, 22, 0}, { -287, 23, 0}, { -250, 24, 0},
{ -214, 25, 0}, { -180, 26, 0}, { -148, 27, 0}, { -116, 28, 0},
{ -86, 29, 0}, { -56, 30, 0}, { -28, 31, 0}, { 0, 0, 0},
};
static int snd_soc_get_volsw_2r_st(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
unsigned int reg = mc->reg;
unsigned int reg2 = mc->rreg;
int val[2], val2[2], i;
val[0] = snd_soc_component_read(component, reg) & 0x3f;
val[1] = (snd_soc_component_read(component, PM860X_SIDETONE_SHIFT) >> 4) & 0xf;
val2[0] = snd_soc_component_read(component, reg2) & 0x3f;
val2[1] = (snd_soc_component_read(component, PM860X_SIDETONE_SHIFT)) & 0xf;
for (i = 0; i < ARRAY_SIZE(st_table); i++) {
if ((st_table[i].m == val[0]) && (st_table[i].n == val[1]))
ucontrol->value.integer.value[0] = i;
if ((st_table[i].m == val2[0]) && (st_table[i].n == val2[1]))
ucontrol->value.integer.value[1] = i;
}
return 0;
}
static int snd_soc_put_volsw_2r_st(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
unsigned int reg = mc->reg;
unsigned int reg2 = mc->rreg;
int err;
unsigned int val, val2;
val = ucontrol->value.integer.value[0];
val2 = ucontrol->value.integer.value[1];
if (val >= ARRAY_SIZE(st_table) || val2 >= ARRAY_SIZE(st_table))
return -EINVAL;
err = snd_soc_component_update_bits(component, reg, 0x3f, st_table[val].m);
if (err < 0)
return err;
err = snd_soc_component_update_bits(component, PM860X_SIDETONE_SHIFT, 0xf0,
st_table[val].n << 4);
if (err < 0)
return err;
err = snd_soc_component_update_bits(component, reg2, 0x3f, st_table[val2].m);
if (err < 0)
return err;
err = snd_soc_component_update_bits(component, PM860X_SIDETONE_SHIFT, 0x0f,
st_table[val2].n);
return err;
}
static int snd_soc_get_volsw_2r_out(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
unsigned int reg = mc->reg;
unsigned int reg2 = mc->rreg;
unsigned int shift = mc->shift;
int max = mc->max, val, val2;
unsigned int mask = (1 << fls(max)) - 1;
val = snd_soc_component_read(component, reg) >> shift;
val2 = snd_soc_component_read(component, reg2) >> shift;
ucontrol->value.integer.value[0] = (max - val) & mask;
ucontrol->value.integer.value[1] = (max - val2) & mask;
return 0;
}
static int snd_soc_put_volsw_2r_out(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
unsigned int reg = mc->reg;
unsigned int reg2 = mc->rreg;
unsigned int shift = mc->shift;
int max = mc->max;
unsigned int mask = (1 << fls(max)) - 1;
int err;
unsigned int val, val2, val_mask;
val_mask = mask << shift;
val = ((max - ucontrol->value.integer.value[0]) & mask);
val2 = ((max - ucontrol->value.integer.value[1]) & mask);
val = val << shift;
val2 = val2 << shift;
err = snd_soc_component_update_bits(component, reg, val_mask, val);
if (err < 0)
return err;
err = snd_soc_component_update_bits(component, reg2, val_mask, val2);
return err;
}
/* DAPM Widget Events */
/*
* A lot registers are belong to RSYNC domain. It requires enabling RSYNC bit
* after updating these registers. Otherwise, these updated registers won't
* be effective.
*/
static int pm860x_rsync_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
/*
* In order to avoid current on the load, mute power-on and power-off
* should be transients.
* Unmute by DAC_MUTE. It should be unmuted when DAPM sequence is
* finished.
*/
snd_soc_component_update_bits(component, PM860X_DAC_OFFSET, DAC_MUTE, 0);
snd_soc_component_update_bits(component, PM860X_EAR_CTRL_2,
RSYNC_CHANGE, RSYNC_CHANGE);
return 0;
}
static int pm860x_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
unsigned int dac = 0;
int data;
if (!strcmp(w->name, "Left DAC"))
dac = DAC_LEFT;
if (!strcmp(w->name, "Right DAC"))
dac = DAC_RIGHT;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
if (dac) {
/* Auto mute in power-on sequence. */
dac |= MODULATOR;
snd_soc_component_update_bits(component, PM860X_DAC_OFFSET,
DAC_MUTE, DAC_MUTE);
snd_soc_component_update_bits(component, PM860X_EAR_CTRL_2,
RSYNC_CHANGE, RSYNC_CHANGE);
/* update dac */
snd_soc_component_update_bits(component, PM860X_DAC_EN_2,
dac, dac);
}
break;
case SND_SOC_DAPM_PRE_PMD:
if (dac) {
/* Auto mute in power-off sequence. */
snd_soc_component_update_bits(component, PM860X_DAC_OFFSET,
DAC_MUTE, DAC_MUTE);
snd_soc_component_update_bits(component, PM860X_EAR_CTRL_2,
RSYNC_CHANGE, RSYNC_CHANGE);
/* update dac */
data = snd_soc_component_read(component, PM860X_DAC_EN_2);
data &= ~dac;
if (!(data & (DAC_LEFT | DAC_RIGHT)))
data &= ~MODULATOR;
snd_soc_component_write(component, PM860X_DAC_EN_2, data);
}
break;
}
return 0;
}
static const char *pm860x_opamp_texts[] = {"-50%", "-25%", "0%", "75%"};
static const char *pm860x_pa_texts[] = {"-33%", "0%", "33%", "66%"};
static SOC_ENUM_SINGLE_DECL(pm860x_hs1_opamp_enum,
PM860X_HS1_CTRL, 5, pm860x_opamp_texts);
static SOC_ENUM_SINGLE_DECL(pm860x_hs2_opamp_enum,
PM860X_HS2_CTRL, 5, pm860x_opamp_texts);
static SOC_ENUM_SINGLE_DECL(pm860x_hs1_pa_enum,
PM860X_HS1_CTRL, 3, pm860x_pa_texts);
static SOC_ENUM_SINGLE_DECL(pm860x_hs2_pa_enum,
PM860X_HS2_CTRL, 3, pm860x_pa_texts);
static SOC_ENUM_SINGLE_DECL(pm860x_lo1_opamp_enum,
PM860X_LO1_CTRL, 5, pm860x_opamp_texts);
static SOC_ENUM_SINGLE_DECL(pm860x_lo2_opamp_enum,
PM860X_LO2_CTRL, 5, pm860x_opamp_texts);
static SOC_ENUM_SINGLE_DECL(pm860x_lo1_pa_enum,
PM860X_LO1_CTRL, 3, pm860x_pa_texts);
static SOC_ENUM_SINGLE_DECL(pm860x_lo2_pa_enum,
PM860X_LO2_CTRL, 3, pm860x_pa_texts);
static SOC_ENUM_SINGLE_DECL(pm860x_spk_pa_enum,
PM860X_EAR_CTRL_1, 5, pm860x_pa_texts);
static SOC_ENUM_SINGLE_DECL(pm860x_ear_pa_enum,
PM860X_EAR_CTRL_2, 0, pm860x_pa_texts);
static SOC_ENUM_SINGLE_DECL(pm860x_spk_ear_opamp_enum,
PM860X_EAR_CTRL_1, 3, pm860x_opamp_texts);
static const struct snd_kcontrol_new pm860x_snd_controls[] = {
SOC_DOUBLE_R_TLV("ADC Capture Volume", PM860X_ADC_ANA_2,
PM860X_ADC_ANA_3, 6, 3, 0, adc_tlv),
SOC_DOUBLE_TLV("AUX Capture Volume", PM860X_ADC_ANA_3, 0, 3, 7, 0,
aux_tlv),
SOC_SINGLE_TLV("MIC1 Capture Volume", PM860X_ADC_ANA_2, 0, 7, 0,
mic_tlv),
SOC_SINGLE_TLV("MIC3 Capture Volume", PM860X_ADC_ANA_2, 3, 7, 0,
mic_tlv),
SOC_DOUBLE_R_EXT_TLV("Sidetone Volume", PM860X_SIDETONE_L_GAIN,
PM860X_SIDETONE_R_GAIN, 0, ARRAY_SIZE(st_table)-1,
0, snd_soc_get_volsw_2r_st,
snd_soc_put_volsw_2r_st, st_tlv),
SOC_SINGLE_TLV("Speaker Playback Volume", PM860X_EAR_CTRL_1,
0, 7, 0, out_tlv),
SOC_DOUBLE_R_TLV("Line Playback Volume", PM860X_LO1_CTRL,
PM860X_LO2_CTRL, 0, 7, 0, out_tlv),
SOC_DOUBLE_R_TLV("Headset Playback Volume", PM860X_HS1_CTRL,
PM860X_HS2_CTRL, 0, 7, 0, out_tlv),
SOC_DOUBLE_R_EXT_TLV("Hifi Left Playback Volume",
PM860X_HIFIL_GAIN_LEFT,
PM860X_HIFIL_GAIN_RIGHT, 0, 63, 0,
snd_soc_get_volsw_2r_out,
snd_soc_put_volsw_2r_out, dpga_tlv),
SOC_DOUBLE_R_EXT_TLV("Hifi Right Playback Volume",
PM860X_HIFIR_GAIN_LEFT,
PM860X_HIFIR_GAIN_RIGHT, 0, 63, 0,
snd_soc_get_volsw_2r_out,
snd_soc_put_volsw_2r_out, dpga_tlv),
SOC_DOUBLE_R_EXT_TLV("Lofi Playback Volume", PM860X_LOFI_GAIN_LEFT,
PM860X_LOFI_GAIN_RIGHT, 0, 63, 0,
snd_soc_get_volsw_2r_out,
snd_soc_put_volsw_2r_out, dpga_tlv),
SOC_ENUM("Headset1 Operational Amplifier Current",
pm860x_hs1_opamp_enum),
SOC_ENUM("Headset2 Operational Amplifier Current",
pm860x_hs2_opamp_enum),
SOC_ENUM("Headset1 Amplifier Current", pm860x_hs1_pa_enum),
SOC_ENUM("Headset2 Amplifier Current", pm860x_hs2_pa_enum),
SOC_ENUM("Lineout1 Operational Amplifier Current",
pm860x_lo1_opamp_enum),
SOC_ENUM("Lineout2 Operational Amplifier Current",
pm860x_lo2_opamp_enum),
SOC_ENUM("Lineout1 Amplifier Current", pm860x_lo1_pa_enum),
SOC_ENUM("Lineout2 Amplifier Current", pm860x_lo2_pa_enum),
SOC_ENUM("Speaker Operational Amplifier Current",
pm860x_spk_ear_opamp_enum),
SOC_ENUM("Speaker Amplifier Current", pm860x_spk_pa_enum),
SOC_ENUM("Earpiece Amplifier Current", pm860x_ear_pa_enum),
};
/*
* DAPM Controls
*/
/* AUX1 Switch */
static const struct snd_kcontrol_new aux1_switch_controls =
SOC_DAPM_SINGLE("Switch", PM860X_ANA_TO_ANA, 4, 1, 0);
/* AUX2 Switch */
static const struct snd_kcontrol_new aux2_switch_controls =
SOC_DAPM_SINGLE("Switch", PM860X_ANA_TO_ANA, 5, 1, 0);
/* Left Ex. PA Switch */
static const struct snd_kcontrol_new lepa_switch_controls =
SOC_DAPM_SINGLE("Switch", PM860X_DAC_EN_2, 2, 1, 0);
/* Right Ex. PA Switch */
static const struct snd_kcontrol_new repa_switch_controls =
SOC_DAPM_SINGLE("Switch", PM860X_DAC_EN_2, 1, 1, 0);
/* I2S Mux / Mux9 */
static const char *i2s_din_text[] = {
"DIN", "DIN1",
};
static SOC_ENUM_SINGLE_DECL(i2s_din_enum,
PM860X_I2S_IFACE_3, 1, i2s_din_text);
static const struct snd_kcontrol_new i2s_din_mux =
SOC_DAPM_ENUM("I2S DIN Mux", i2s_din_enum);
/* I2S Mic Mux / Mux8 */
static const char *i2s_mic_text[] = {
"Ex PA", "ADC",
};
static SOC_ENUM_SINGLE_DECL(i2s_mic_enum,
PM860X_I2S_IFACE_3, 4, i2s_mic_text);
static const struct snd_kcontrol_new i2s_mic_mux =
SOC_DAPM_ENUM("I2S Mic Mux", i2s_mic_enum);
/* ADCL Mux / Mux2 */
static const char *adcl_text[] = {
"ADCR", "ADCL",
};
static SOC_ENUM_SINGLE_DECL(adcl_enum,
PM860X_PCM_IFACE_3, 4, adcl_text);
static const struct snd_kcontrol_new adcl_mux =
SOC_DAPM_ENUM("ADC Left Mux", adcl_enum);
/* ADCR Mux / Mux3 */
static const char *adcr_text[] = {
"ADCL", "ADCR",
};
static SOC_ENUM_SINGLE_DECL(adcr_enum,
PM860X_PCM_IFACE_3, 2, adcr_text);
static const struct snd_kcontrol_new adcr_mux =
SOC_DAPM_ENUM("ADC Right Mux", adcr_enum);
/* ADCR EC Mux / Mux6 */
static const char *adcr_ec_text[] = {
"ADCR", "EC",
};
static SOC_ENUM_SINGLE_DECL(adcr_ec_enum,
PM860X_ADC_EN_2, 3, adcr_ec_text);
static const struct snd_kcontrol_new adcr_ec_mux =
SOC_DAPM_ENUM("ADCR EC Mux", adcr_ec_enum);
/* EC Mux / Mux4 */
static const char *ec_text[] = {
"Left", "Right", "Left + Right",
};
static SOC_ENUM_SINGLE_DECL(ec_enum,
PM860X_EC_PATH, 1, ec_text);
static const struct snd_kcontrol_new ec_mux =
SOC_DAPM_ENUM("EC Mux", ec_enum);
static const char *dac_text[] = {
"No input", "Right", "Left", "No input",
};
/* DAC Headset 1 Mux / Mux10 */
static SOC_ENUM_SINGLE_DECL(dac_hs1_enum,
PM860X_ANA_INPUT_SEL_1, 0, dac_text);
static const struct snd_kcontrol_new dac_hs1_mux =
SOC_DAPM_ENUM("DAC HS1 Mux", dac_hs1_enum);
/* DAC Headset 2 Mux / Mux11 */
static SOC_ENUM_SINGLE_DECL(dac_hs2_enum,
PM860X_ANA_INPUT_SEL_1, 2, dac_text);
static const struct snd_kcontrol_new dac_hs2_mux =
SOC_DAPM_ENUM("DAC HS2 Mux", dac_hs2_enum);
/* DAC Lineout 1 Mux / Mux12 */
static SOC_ENUM_SINGLE_DECL(dac_lo1_enum,
PM860X_ANA_INPUT_SEL_1, 4, dac_text);
static const struct snd_kcontrol_new dac_lo1_mux =
SOC_DAPM_ENUM("DAC LO1 Mux", dac_lo1_enum);
/* DAC Lineout 2 Mux / Mux13 */
static SOC_ENUM_SINGLE_DECL(dac_lo2_enum,
PM860X_ANA_INPUT_SEL_1, 6, dac_text);
static const struct snd_kcontrol_new dac_lo2_mux =
SOC_DAPM_ENUM("DAC LO2 Mux", dac_lo2_enum);
/* DAC Spearker Earphone Mux / Mux14 */
static SOC_ENUM_SINGLE_DECL(dac_spk_ear_enum,
PM860X_ANA_INPUT_SEL_2, 0, dac_text);
static const struct snd_kcontrol_new dac_spk_ear_mux =
SOC_DAPM_ENUM("DAC SP Mux", dac_spk_ear_enum);
/* Headset 1 Mux / Mux15 */
static const char *in_text[] = {
"Digital", "Analog",
};
static SOC_ENUM_SINGLE_DECL(hs1_enum,
PM860X_ANA_TO_ANA, 0, in_text);
static const struct snd_kcontrol_new hs1_mux =
SOC_DAPM_ENUM("Headset1 Mux", hs1_enum);
/* Headset 2 Mux / Mux16 */
static SOC_ENUM_SINGLE_DECL(hs2_enum,
PM860X_ANA_TO_ANA, 1, in_text);
static const struct snd_kcontrol_new hs2_mux =
SOC_DAPM_ENUM("Headset2 Mux", hs2_enum);
/* Lineout 1 Mux / Mux17 */
static SOC_ENUM_SINGLE_DECL(lo1_enum,
PM860X_ANA_TO_ANA, 2, in_text);
static const struct snd_kcontrol_new lo1_mux =
SOC_DAPM_ENUM("Lineout1 Mux", lo1_enum);
/* Lineout 2 Mux / Mux18 */
static SOC_ENUM_SINGLE_DECL(lo2_enum,
PM860X_ANA_TO_ANA, 3, in_text);
static const struct snd_kcontrol_new lo2_mux =
SOC_DAPM_ENUM("Lineout2 Mux", lo2_enum);
/* Speaker Earpiece Demux */
static const char *spk_text[] = {
"Earpiece", "Speaker",
};
static SOC_ENUM_SINGLE_DECL(spk_enum,
PM860X_ANA_TO_ANA, 6, spk_text);
static const struct snd_kcontrol_new spk_demux =
SOC_DAPM_ENUM("Speaker Earpiece Demux", spk_enum);
/* MIC Mux / Mux1 */
static const char *mic_text[] = {
"Mic 1", "Mic 2",
};
static SOC_ENUM_SINGLE_DECL(mic_enum,
PM860X_ADC_ANA_4, 4, mic_text);
static const struct snd_kcontrol_new mic_mux =
SOC_DAPM_ENUM("MIC Mux", mic_enum);
static const struct snd_soc_dapm_widget pm860x_dapm_widgets[] = {
SND_SOC_DAPM_AIF_IN("PCM SDI", "PCM Playback", 0,
PM860X_ADC_EN_2, 0, 0),
SND_SOC_DAPM_AIF_OUT("PCM SDO", "PCM Capture", 0,
PM860X_PCM_IFACE_3, 1, 1),
SND_SOC_DAPM_AIF_IN("I2S DIN", "I2S Playback", 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("I2S DIN1", "I2S Playback", 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("I2S DOUT", "I2S Capture", 0,
PM860X_I2S_IFACE_3, 5, 1),
SND_SOC_DAPM_SUPPLY("I2S CLK", PM860X_DAC_EN_2, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX("I2S Mic Mux", SND_SOC_NOPM, 0, 0, &i2s_mic_mux),
SND_SOC_DAPM_MUX("ADC Left Mux", SND_SOC_NOPM, 0, 0, &adcl_mux),
SND_SOC_DAPM_MUX("ADC Right Mux", SND_SOC_NOPM, 0, 0, &adcr_mux),
SND_SOC_DAPM_MUX("EC Mux", SND_SOC_NOPM, 0, 0, &ec_mux),
SND_SOC_DAPM_MUX("ADCR EC Mux", SND_SOC_NOPM, 0, 0, &adcr_ec_mux),
SND_SOC_DAPM_SWITCH("Left EPA", SND_SOC_NOPM, 0, 0,
&lepa_switch_controls),
SND_SOC_DAPM_SWITCH("Right EPA", SND_SOC_NOPM, 0, 0,
&repa_switch_controls),
SND_SOC_DAPM_REG(snd_soc_dapm_supply, "Left ADC MOD", PM860X_ADC_EN_1,
0, 1, 1, 0),
SND_SOC_DAPM_REG(snd_soc_dapm_supply, "Right ADC MOD", PM860X_ADC_EN_1,
1, 1, 1, 0),
SND_SOC_DAPM_ADC("Left ADC", NULL, PM860X_ADC_EN_2, 5, 0),
SND_SOC_DAPM_ADC("Right ADC", NULL, PM860X_ADC_EN_2, 4, 0),
SND_SOC_DAPM_SWITCH("AUX1 Switch", SND_SOC_NOPM, 0, 0,
&aux1_switch_controls),
SND_SOC_DAPM_SWITCH("AUX2 Switch", SND_SOC_NOPM, 0, 0,
&aux2_switch_controls),
SND_SOC_DAPM_MUX("MIC Mux", SND_SOC_NOPM, 0, 0, &mic_mux),
SND_SOC_DAPM_MICBIAS("Mic1 Bias", PM860X_ADC_ANA_1, 2, 0),
SND_SOC_DAPM_MICBIAS("Mic3 Bias", PM860X_ADC_ANA_1, 7, 0),
SND_SOC_DAPM_PGA("MIC1 Volume", PM860X_ADC_EN_1, 2, 0, NULL, 0),
SND_SOC_DAPM_PGA("MIC3 Volume", PM860X_ADC_EN_1, 3, 0, NULL, 0),
SND_SOC_DAPM_PGA("AUX1 Volume", PM860X_ADC_EN_1, 4, 0, NULL, 0),
SND_SOC_DAPM_PGA("AUX2 Volume", PM860X_ADC_EN_1, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA("Sidetone PGA", PM860X_ADC_EN_2, 1, 0, NULL, 0),
SND_SOC_DAPM_PGA("Lofi PGA", PM860X_ADC_EN_2, 2, 0, NULL, 0),
SND_SOC_DAPM_INPUT("AUX1"),
SND_SOC_DAPM_INPUT("AUX2"),
SND_SOC_DAPM_INPUT("MIC1P"),
SND_SOC_DAPM_INPUT("MIC1N"),
SND_SOC_DAPM_INPUT("MIC2P"),
SND_SOC_DAPM_INPUT("MIC2N"),
SND_SOC_DAPM_INPUT("MIC3P"),
SND_SOC_DAPM_INPUT("MIC3N"),
SND_SOC_DAPM_DAC_E("Left DAC", NULL, SND_SOC_NOPM, 0, 0,
pm860x_dac_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_DAC_E("Right DAC", NULL, SND_SOC_NOPM, 0, 0,
pm860x_dac_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_MUX("I2S DIN Mux", SND_SOC_NOPM, 0, 0, &i2s_din_mux),
SND_SOC_DAPM_MUX("DAC HS1 Mux", SND_SOC_NOPM, 0, 0, &dac_hs1_mux),
SND_SOC_DAPM_MUX("DAC HS2 Mux", SND_SOC_NOPM, 0, 0, &dac_hs2_mux),
SND_SOC_DAPM_MUX("DAC LO1 Mux", SND_SOC_NOPM, 0, 0, &dac_lo1_mux),
SND_SOC_DAPM_MUX("DAC LO2 Mux", SND_SOC_NOPM, 0, 0, &dac_lo2_mux),
SND_SOC_DAPM_MUX("DAC SP Mux", SND_SOC_NOPM, 0, 0, &dac_spk_ear_mux),
SND_SOC_DAPM_MUX("Headset1 Mux", SND_SOC_NOPM, 0, 0, &hs1_mux),
SND_SOC_DAPM_MUX("Headset2 Mux", SND_SOC_NOPM, 0, 0, &hs2_mux),
SND_SOC_DAPM_MUX("Lineout1 Mux", SND_SOC_NOPM, 0, 0, &lo1_mux),
SND_SOC_DAPM_MUX("Lineout2 Mux", SND_SOC_NOPM, 0, 0, &lo2_mux),
SND_SOC_DAPM_MUX("Speaker Earpiece Demux", SND_SOC_NOPM, 0, 0,
&spk_demux),
SND_SOC_DAPM_PGA("Headset1 PGA", PM860X_DAC_EN_1, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Headset2 PGA", PM860X_DAC_EN_1, 1, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("HS1"),
SND_SOC_DAPM_OUTPUT("HS2"),
SND_SOC_DAPM_PGA("Lineout1 PGA", PM860X_DAC_EN_1, 2, 0, NULL, 0),
SND_SOC_DAPM_PGA("Lineout2 PGA", PM860X_DAC_EN_1, 3, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("LINEOUT1"),
SND_SOC_DAPM_OUTPUT("LINEOUT2"),
SND_SOC_DAPM_PGA("Earpiece PGA", PM860X_DAC_EN_1, 4, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("EARP"),
SND_SOC_DAPM_OUTPUT("EARN"),
SND_SOC_DAPM_PGA("Speaker PGA", PM860X_DAC_EN_1, 5, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("LSP"),
SND_SOC_DAPM_OUTPUT("LSN"),
SND_SOC_DAPM_REG(snd_soc_dapm_supply, "VCODEC", PM860X_AUDIO_SUPPLIES_2,
0, SUPPLY_MASK, SUPPLY_MASK, 0),
PM860X_DAPM_OUTPUT("RSYNC", pm860x_rsync_event),
};
static const struct snd_soc_dapm_route pm860x_dapm_routes[] = {
/* supply */
{"Left DAC", NULL, "VCODEC"},
{"Right DAC", NULL, "VCODEC"},
{"Left ADC", NULL, "VCODEC"},
{"Right ADC", NULL, "VCODEC"},
{"Left ADC", NULL, "Left ADC MOD"},
{"Right ADC", NULL, "Right ADC MOD"},
/* I2S Clock */
{"I2S DIN", NULL, "I2S CLK"},
{"I2S DIN1", NULL, "I2S CLK"},
{"I2S DOUT", NULL, "I2S CLK"},
/* PCM/AIF1 Inputs */
{"PCM SDO", NULL, "ADC Left Mux"},
{"PCM SDO", NULL, "ADCR EC Mux"},
/* PCM/AFI2 Outputs */
{"Lofi PGA", NULL, "PCM SDI"},
{"Lofi PGA", NULL, "Sidetone PGA"},
{"Left DAC", NULL, "Lofi PGA"},
{"Right DAC", NULL, "Lofi PGA"},
/* I2S/AIF2 Inputs */
{"MIC Mux", "Mic 1", "MIC1P"},
{"MIC Mux", "Mic 1", "MIC1N"},
{"MIC Mux", "Mic 2", "MIC2P"},
{"MIC Mux", "Mic 2", "MIC2N"},
{"MIC1 Volume", NULL, "MIC Mux"},
{"MIC3 Volume", NULL, "MIC3P"},
{"MIC3 Volume", NULL, "MIC3N"},
{"Left ADC", NULL, "MIC1 Volume"},
{"Right ADC", NULL, "MIC3 Volume"},
{"ADC Left Mux", "ADCR", "Right ADC"},
{"ADC Left Mux", "ADCL", "Left ADC"},
{"ADC Right Mux", "ADCL", "Left ADC"},
{"ADC Right Mux", "ADCR", "Right ADC"},
{"Left EPA", "Switch", "Left DAC"},
{"Right EPA", "Switch", "Right DAC"},
{"EC Mux", "Left", "Left DAC"},
{"EC Mux", "Right", "Right DAC"},
{"EC Mux", "Left + Right", "Left DAC"},
{"EC Mux", "Left + Right", "Right DAC"},
{"ADCR EC Mux", "ADCR", "ADC Right Mux"},
{"ADCR EC Mux", "EC", "EC Mux"},
{"I2S Mic Mux", "Ex PA", "Left EPA"},
{"I2S Mic Mux", "Ex PA", "Right EPA"},
{"I2S Mic Mux", "ADC", "ADC Left Mux"},
{"I2S Mic Mux", "ADC", "ADCR EC Mux"},
{"I2S DOUT", NULL, "I2S Mic Mux"},
/* I2S/AIF2 Outputs */
{"I2S DIN Mux", "DIN", "I2S DIN"},
{"I2S DIN Mux", "DIN1", "I2S DIN1"},
{"Left DAC", NULL, "I2S DIN Mux"},
{"Right DAC", NULL, "I2S DIN Mux"},
{"DAC HS1 Mux", "Left", "Left DAC"},
{"DAC HS1 Mux", "Right", "Right DAC"},
{"DAC HS2 Mux", "Left", "Left DAC"},
{"DAC HS2 Mux", "Right", "Right DAC"},
{"DAC LO1 Mux", "Left", "Left DAC"},
{"DAC LO1 Mux", "Right", "Right DAC"},
{"DAC LO2 Mux", "Left", "Left DAC"},
{"DAC LO2 Mux", "Right", "Right DAC"},
{"Headset1 Mux", "Digital", "DAC HS1 Mux"},
{"Headset2 Mux", "Digital", "DAC HS2 Mux"},
{"Lineout1 Mux", "Digital", "DAC LO1 Mux"},
{"Lineout2 Mux", "Digital", "DAC LO2 Mux"},
{"Headset1 PGA", NULL, "Headset1 Mux"},
{"Headset2 PGA", NULL, "Headset2 Mux"},
{"Lineout1 PGA", NULL, "Lineout1 Mux"},
{"Lineout2 PGA", NULL, "Lineout2 Mux"},
{"DAC SP Mux", "Left", "Left DAC"},
{"DAC SP Mux", "Right", "Right DAC"},
{"Speaker Earpiece Demux", "Speaker", "DAC SP Mux"},
{"Speaker PGA", NULL, "Speaker Earpiece Demux"},
{"Earpiece PGA", NULL, "Speaker Earpiece Demux"},
{"RSYNC", NULL, "Headset1 PGA"},
{"RSYNC", NULL, "Headset2 PGA"},
{"RSYNC", NULL, "Lineout1 PGA"},
{"RSYNC", NULL, "Lineout2 PGA"},
{"RSYNC", NULL, "Speaker PGA"},
{"RSYNC", NULL, "Speaker PGA"},
{"RSYNC", NULL, "Earpiece PGA"},
{"RSYNC", NULL, "Earpiece PGA"},
{"HS1", NULL, "RSYNC"},
{"HS2", NULL, "RSYNC"},
{"LINEOUT1", NULL, "RSYNC"},
{"LINEOUT2", NULL, "RSYNC"},
{"LSP", NULL, "RSYNC"},
{"LSN", NULL, "RSYNC"},
{"EARP", NULL, "RSYNC"},
{"EARN", NULL, "RSYNC"},
};
/*
* Use MUTE_LEFT & MUTE_RIGHT to implement digital mute.
* These bits can also be used to mute.
*/
static int pm860x_mute_stream(struct snd_soc_dai *codec_dai, int mute, int direction)
{
struct snd_soc_component *component = codec_dai->component;
int data = 0, mask = MUTE_LEFT | MUTE_RIGHT;
if (mute)
data = mask;
snd_soc_component_update_bits(component, PM860X_DAC_OFFSET, mask, data);
snd_soc_component_update_bits(component, PM860X_EAR_CTRL_2,
RSYNC_CHANGE, RSYNC_CHANGE);
return 0;
}
static int pm860x_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
unsigned char inf = 0, mask = 0;
/* bit size */
switch (params_width(params)) {
case 16:
inf &= ~PCM_INF2_18WL;
break;
case 18:
inf |= PCM_INF2_18WL;
break;
default:
return -EINVAL;
}
mask |= PCM_INF2_18WL;
snd_soc_component_update_bits(component, PM860X_PCM_IFACE_2, mask, inf);
/* sample rate */
switch (params_rate(params)) {
case 8000:
inf = 0;
break;
case 16000:
inf = 3;
break;
case 32000:
inf = 6;
break;
case 48000:
inf = 8;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, PM860X_PCM_RATE, 0x0f, inf);
return 0;
}
static int pm860x_pcm_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct pm860x_priv *pm860x = snd_soc_component_get_drvdata(component);
unsigned char inf = 0, mask = 0;
int ret = -EINVAL;
mask |= PCM_INF2_BCLK | PCM_INF2_FS | PCM_INF2_MASTER;
/* set audio interface clocking */
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
case SND_SOC_DAIFMT_CBP_CFC:
if (pm860x->dir == PM860X_CLK_DIR_OUT) {
inf |= PCM_INF2_MASTER;
ret = 0;
}
break;
case SND_SOC_DAIFMT_CBC_CFC:
if (pm860x->dir == PM860X_CLK_DIR_IN) {
inf &= ~PCM_INF2_MASTER;
ret = 0;
}
break;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
inf |= PCM_EXACT_I2S;
ret = 0;
break;
}
mask |= PCM_MODE_MASK;
if (ret)
return ret;
snd_soc_component_update_bits(component, PM860X_PCM_IFACE_2, mask, inf);
return 0;
}
static int pm860x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct pm860x_priv *pm860x = snd_soc_component_get_drvdata(component);
if (dir == PM860X_CLK_DIR_OUT)
pm860x->dir = PM860X_CLK_DIR_OUT;
else /* Slave mode is not supported */
return -EINVAL;
return 0;
}
static int pm860x_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
unsigned char inf;
/* bit size */
switch (params_width(params)) {
case 16:
inf = 0;
break;
case 18:
inf = PCM_INF2_18WL;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, PM860X_I2S_IFACE_2, PCM_INF2_18WL, inf);
/* sample rate */
switch (params_rate(params)) {
case 8000:
inf = 0;
break;
case 11025:
inf = 1;
break;
case 16000:
inf = 3;
break;
case 22050:
inf = 4;
break;
case 32000:
inf = 6;
break;
case 44100:
inf = 7;
break;
case 48000:
inf = 8;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, PM860X_I2S_IFACE_4, 0xf, inf);
return 0;
}
static int pm860x_i2s_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct pm860x_priv *pm860x = snd_soc_component_get_drvdata(component);
unsigned char inf = 0, mask = 0;
mask |= PCM_INF2_BCLK | PCM_INF2_FS | PCM_INF2_MASTER;
/* set audio interface clocking */
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
if (pm860x->dir == PM860X_CLK_DIR_OUT)
inf |= PCM_INF2_MASTER;
else
return -EINVAL;
break;
case SND_SOC_DAIFMT_CBC_CFC:
if (pm860x->dir == PM860X_CLK_DIR_IN)
inf &= ~PCM_INF2_MASTER;
else
return -EINVAL;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
inf |= PCM_EXACT_I2S;
break;
default:
return -EINVAL;
}
mask |= PCM_MODE_MASK;
snd_soc_component_update_bits(component, PM860X_I2S_IFACE_2, mask, inf);
return 0;
}
static int pm860x_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct pm860x_priv *pm860x = snd_soc_component_get_drvdata(component);
int data;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
/* Enable Audio PLL & Audio section */
data = AUDIO_PLL | AUDIO_SECTION_ON;
pm860x_reg_write(pm860x->i2c, REG_MISC2, data);
udelay(300);
data = AUDIO_PLL | AUDIO_SECTION_RESET
| AUDIO_SECTION_ON;
pm860x_reg_write(pm860x->i2c, REG_MISC2, data);
}
break;
case SND_SOC_BIAS_OFF:
data = AUDIO_PLL | AUDIO_SECTION_RESET | AUDIO_SECTION_ON;
pm860x_set_bits(pm860x->i2c, REG_MISC2, data, 0);
break;
}
return 0;
}
static const struct snd_soc_dai_ops pm860x_pcm_dai_ops = {
.mute_stream = pm860x_mute_stream,
.hw_params = pm860x_pcm_hw_params,
.set_fmt = pm860x_pcm_set_dai_fmt,
.set_sysclk = pm860x_set_dai_sysclk,
.no_capture_mute = 1,
};
static const struct snd_soc_dai_ops pm860x_i2s_dai_ops = {
.mute_stream = pm860x_mute_stream,
.hw_params = pm860x_i2s_hw_params,
.set_fmt = pm860x_i2s_set_dai_fmt,
.set_sysclk = pm860x_set_dai_sysclk,
.no_capture_mute = 1,
};
#define PM860X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | \
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)
static struct snd_soc_dai_driver pm860x_dai[] = {
{
/* DAI PCM */
.name = "88pm860x-pcm",
.id = 1,
.playback = {
.stream_name = "PCM Playback",
.channels_min = 2,
.channels_max = 2,
.rates = PM860X_RATES,
.formats = SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S18_3LE,
},
.capture = {
.stream_name = "PCM Capture",
.channels_min = 2,
.channels_max = 2,
.rates = PM860X_RATES,
.formats = SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S18_3LE,
},
.ops = &pm860x_pcm_dai_ops,
}, {
/* DAI I2S */
.name = "88pm860x-i2s",
.id = 2,
.playback = {
.stream_name = "I2S Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S18_3LE,
},
.capture = {
.stream_name = "I2S Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S18_3LE,
},
.ops = &pm860x_i2s_dai_ops,
},
};
static irqreturn_t pm860x_component_handler(int irq, void *data)
{
struct pm860x_priv *pm860x = data;
int status, shrt, report = 0, mic_report = 0;
int mask;
status = pm860x_reg_read(pm860x->i2c, REG_STATUS_1);
shrt = pm860x_reg_read(pm860x->i2c, REG_SHORTS);
mask = pm860x->det.hs_shrt | pm860x->det.hook_det | pm860x->det.lo_shrt
| pm860x->det.hp_det;
#ifndef CONFIG_SND_SOC_88PM860X_MODULE
if (status & (HEADSET_STATUS | MIC_STATUS | SHORT_HS1 | SHORT_HS2 |
SHORT_LO1 | SHORT_LO2))
trace_snd_soc_jack_irq(dev_name(pm860x->component->dev));
#endif
if ((pm860x->det.hp_det & SND_JACK_HEADPHONE)
&& (status & HEADSET_STATUS))
report |= SND_JACK_HEADPHONE;
if ((pm860x->det.mic_det & SND_JACK_MICROPHONE)
&& (status & MIC_STATUS))
mic_report |= SND_JACK_MICROPHONE;
if (pm860x->det.hs_shrt && (shrt & (SHORT_HS1 | SHORT_HS2)))
report |= pm860x->det.hs_shrt;
if (pm860x->det.hook_det && (status & HOOK_STATUS))
report |= pm860x->det.hook_det;
if (pm860x->det.lo_shrt && (shrt & (SHORT_LO1 | SHORT_LO2)))
report |= pm860x->det.lo_shrt;
if (report)
snd_soc_jack_report(pm860x->det.hp_jack, report, mask);
if (mic_report)
snd_soc_jack_report(pm860x->det.mic_jack, SND_JACK_MICROPHONE,
SND_JACK_MICROPHONE);
dev_dbg(pm860x->component->dev, "headphone report:0x%x, mask:%x\n",
report, mask);
dev_dbg(pm860x->component->dev, "microphone report:0x%x\n", mic_report);
return IRQ_HANDLED;
}
int pm860x_hs_jack_detect(struct snd_soc_component *component,
struct snd_soc_jack *jack,
int det, int hook, int hs_shrt, int lo_shrt)
{
struct pm860x_priv *pm860x = snd_soc_component_get_drvdata(component);
int data;
pm860x->det.hp_jack = jack;
pm860x->det.hp_det = det;
pm860x->det.hook_det = hook;
pm860x->det.hs_shrt = hs_shrt;
pm860x->det.lo_shrt = lo_shrt;
if (det & SND_JACK_HEADPHONE)
pm860x_set_bits(pm860x->i2c, REG_HS_DET,
EN_HS_DET, EN_HS_DET);
/* headset short detect */
if (hs_shrt) {
data = CLR_SHORT_HS2 | CLR_SHORT_HS1;
pm860x_set_bits(pm860x->i2c, REG_SHORTS, data, data);
}
/* Lineout short detect */
if (lo_shrt) {
data = CLR_SHORT_LO2 | CLR_SHORT_LO1;
pm860x_set_bits(pm860x->i2c, REG_SHORTS, data, data);
}
/* sync status */
pm860x_component_handler(0, pm860x);
return 0;
}
EXPORT_SYMBOL_GPL(pm860x_hs_jack_detect);
int pm860x_mic_jack_detect(struct snd_soc_component *component,
struct snd_soc_jack *jack, int det)
{
struct pm860x_priv *pm860x = snd_soc_component_get_drvdata(component);
pm860x->det.mic_jack = jack;
pm860x->det.mic_det = det;
if (det & SND_JACK_MICROPHONE)
pm860x_set_bits(pm860x->i2c, REG_MIC_DET,
MICDET_MASK, MICDET_MASK);
/* sync status */
pm860x_component_handler(0, pm860x);
return 0;
}
EXPORT_SYMBOL_GPL(pm860x_mic_jack_detect);
static int pm860x_probe(struct snd_soc_component *component)
{
struct pm860x_priv *pm860x = snd_soc_component_get_drvdata(component);
int i, ret;
pm860x->component = component;
snd_soc_component_init_regmap(component, pm860x->regmap);
for (i = 0; i < 4; i++) {
ret = request_threaded_irq(pm860x->irq[i], NULL,
pm860x_component_handler, IRQF_ONESHOT,
pm860x->name[i], pm860x);
if (ret < 0) {
dev_err(component->dev, "Failed to request IRQ!\n");
goto out;
}
}
return 0;
out:
while (--i >= 0)
free_irq(pm860x->irq[i], pm860x);
return ret;
}
static void pm860x_remove(struct snd_soc_component *component)
{
struct pm860x_priv *pm860x = snd_soc_component_get_drvdata(component);
int i;
for (i = 3; i >= 0; i--)
free_irq(pm860x->irq[i], pm860x);
}
static const struct snd_soc_component_driver soc_component_dev_pm860x = {
.probe = pm860x_probe,
.remove = pm860x_remove,
.set_bias_level = pm860x_set_bias_level,
.controls = pm860x_snd_controls,
.num_controls = ARRAY_SIZE(pm860x_snd_controls),
.dapm_widgets = pm860x_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(pm860x_dapm_widgets),
.dapm_routes = pm860x_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(pm860x_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int pm860x_codec_probe(struct platform_device *pdev)
{
struct pm860x_chip *chip = dev_get_drvdata(pdev->dev.parent);
struct pm860x_priv *pm860x;
struct resource *res;
int i, ret;
pm860x = devm_kzalloc(&pdev->dev, sizeof(struct pm860x_priv),
GFP_KERNEL);
if (pm860x == NULL)
return -ENOMEM;
pm860x->chip = chip;
pm860x->i2c = (chip->id == CHIP_PM8607) ? chip->client
: chip->companion;
pm860x->regmap = (chip->id == CHIP_PM8607) ? chip->regmap
: chip->regmap_companion;
platform_set_drvdata(pdev, pm860x);
for (i = 0; i < 4; i++) {
res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
if (!res) {
dev_err(&pdev->dev, "Failed to get IRQ resources\n");
return -EINVAL;
}
pm860x->irq[i] = res->start + chip->irq_base;
strscpy(pm860x->name[i], res->name, MAX_NAME_LEN);
}
ret = devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_pm860x,
pm860x_dai, ARRAY_SIZE(pm860x_dai));
if (ret) {
dev_err(&pdev->dev, "Failed to register component\n");
return -EINVAL;
}
return ret;
}
static struct platform_driver pm860x_codec_driver = {
.driver = {
.name = "88pm860x-codec",
},
.probe = pm860x_codec_probe,
};
module_platform_driver(pm860x_codec_driver);
MODULE_DESCRIPTION("ASoC 88PM860x driver");
MODULE_AUTHOR("Haojian Zhuang <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:88pm860x-codec");
| linux-master | sound/soc/codecs/88pm860x-codec.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* cs35l33.c -- CS35L33 ALSA SoC audio driver
*
* Copyright 2016 Cirrus Logic, Inc.
*
* Author: Paul Handrigan <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/workqueue.h>
#include <linux/platform_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <sound/cs35l33.h>
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <linux/regulator/machine.h>
#include <linux/of_gpio.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include "cs35l33.h"
#include "cirrus_legacy.h"
#define CS35L33_BOOT_DELAY 50
struct cs35l33_private {
struct snd_soc_component *component;
struct cs35l33_pdata pdata;
struct regmap *regmap;
struct gpio_desc *reset_gpio;
bool amp_cal;
int mclk_int;
struct regulator_bulk_data core_supplies[2];
int num_core_supplies;
bool is_tdm_mode;
bool enable_soft_ramp;
};
static const struct reg_default cs35l33_reg[] = {
{CS35L33_PWRCTL1, 0x85},
{CS35L33_PWRCTL2, 0xFE},
{CS35L33_CLK_CTL, 0x0C},
{CS35L33_BST_PEAK_CTL, 0x90},
{CS35L33_PROTECT_CTL, 0x55},
{CS35L33_BST_CTL1, 0x00},
{CS35L33_BST_CTL2, 0x01},
{CS35L33_ADSP_CTL, 0x00},
{CS35L33_ADC_CTL, 0xC8},
{CS35L33_DAC_CTL, 0x14},
{CS35L33_DIG_VOL_CTL, 0x00},
{CS35L33_CLASSD_CTL, 0x04},
{CS35L33_AMP_CTL, 0x90},
{CS35L33_INT_MASK_1, 0xFF},
{CS35L33_INT_MASK_2, 0xFF},
{CS35L33_DIAG_LOCK, 0x00},
{CS35L33_DIAG_CTRL_1, 0x40},
{CS35L33_DIAG_CTRL_2, 0x00},
{CS35L33_HG_MEMLDO_CTL, 0x62},
{CS35L33_HG_REL_RATE, 0x03},
{CS35L33_LDO_DEL, 0x12},
{CS35L33_HG_HEAD, 0x0A},
{CS35L33_HG_EN, 0x05},
{CS35L33_TX_VMON, 0x00},
{CS35L33_TX_IMON, 0x03},
{CS35L33_TX_VPMON, 0x02},
{CS35L33_TX_VBSTMON, 0x05},
{CS35L33_TX_FLAG, 0x06},
{CS35L33_TX_EN1, 0x00},
{CS35L33_TX_EN2, 0x00},
{CS35L33_TX_EN3, 0x00},
{CS35L33_TX_EN4, 0x00},
{CS35L33_RX_AUD, 0x40},
{CS35L33_RX_SPLY, 0x03},
{CS35L33_RX_ALIVE, 0x04},
{CS35L33_BST_CTL4, 0x63},
};
static const struct reg_sequence cs35l33_patch[] = {
{ 0x00, 0x99, 0 },
{ 0x59, 0x02, 0 },
{ 0x52, 0x30, 0 },
{ 0x39, 0x45, 0 },
{ 0x57, 0x30, 0 },
{ 0x2C, 0x68, 0 },
{ 0x00, 0x00, 0 },
};
static bool cs35l33_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS35L33_DEVID_AB:
case CS35L33_DEVID_CD:
case CS35L33_DEVID_E:
case CS35L33_REV_ID:
case CS35L33_INT_STATUS_1:
case CS35L33_INT_STATUS_2:
case CS35L33_HG_STATUS:
return true;
default:
return false;
}
}
static bool cs35l33_writeable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
/* these are read only registers */
case CS35L33_DEVID_AB:
case CS35L33_DEVID_CD:
case CS35L33_DEVID_E:
case CS35L33_REV_ID:
case CS35L33_INT_STATUS_1:
case CS35L33_INT_STATUS_2:
case CS35L33_HG_STATUS:
return false;
default:
return true;
}
}
static bool cs35l33_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS35L33_DEVID_AB:
case CS35L33_DEVID_CD:
case CS35L33_DEVID_E:
case CS35L33_REV_ID:
case CS35L33_PWRCTL1:
case CS35L33_PWRCTL2:
case CS35L33_CLK_CTL:
case CS35L33_BST_PEAK_CTL:
case CS35L33_PROTECT_CTL:
case CS35L33_BST_CTL1:
case CS35L33_BST_CTL2:
case CS35L33_ADSP_CTL:
case CS35L33_ADC_CTL:
case CS35L33_DAC_CTL:
case CS35L33_DIG_VOL_CTL:
case CS35L33_CLASSD_CTL:
case CS35L33_AMP_CTL:
case CS35L33_INT_MASK_1:
case CS35L33_INT_MASK_2:
case CS35L33_INT_STATUS_1:
case CS35L33_INT_STATUS_2:
case CS35L33_DIAG_LOCK:
case CS35L33_DIAG_CTRL_1:
case CS35L33_DIAG_CTRL_2:
case CS35L33_HG_MEMLDO_CTL:
case CS35L33_HG_REL_RATE:
case CS35L33_LDO_DEL:
case CS35L33_HG_HEAD:
case CS35L33_HG_EN:
case CS35L33_TX_VMON:
case CS35L33_TX_IMON:
case CS35L33_TX_VPMON:
case CS35L33_TX_VBSTMON:
case CS35L33_TX_FLAG:
case CS35L33_TX_EN1:
case CS35L33_TX_EN2:
case CS35L33_TX_EN3:
case CS35L33_TX_EN4:
case CS35L33_RX_AUD:
case CS35L33_RX_SPLY:
case CS35L33_RX_ALIVE:
case CS35L33_BST_CTL4:
return true;
default:
return false;
}
}
static DECLARE_TLV_DB_SCALE(classd_ctl_tlv, 900, 100, 0);
static DECLARE_TLV_DB_SCALE(dac_tlv, -10200, 50, 0);
static const struct snd_kcontrol_new cs35l33_snd_controls[] = {
SOC_SINGLE_TLV("SPK Amp Volume", CS35L33_AMP_CTL,
4, 0x09, 0, classd_ctl_tlv),
SOC_SINGLE_SX_TLV("DAC Volume", CS35L33_DIG_VOL_CTL,
0, 0x34, 0xE4, dac_tlv),
};
static int cs35l33_spkrdrv_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
if (!priv->amp_cal) {
usleep_range(8000, 9000);
priv->amp_cal = true;
regmap_update_bits(priv->regmap, CS35L33_CLASSD_CTL,
CS35L33_AMP_CAL, 0);
dev_dbg(component->dev, "Amp calibration done\n");
}
dev_dbg(component->dev, "Amp turned on\n");
break;
case SND_SOC_DAPM_POST_PMD:
dev_dbg(component->dev, "Amp turned off\n");
break;
default:
dev_err(component->dev, "Invalid event = 0x%x\n", event);
break;
}
return 0;
}
static int cs35l33_sdin_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
unsigned int val;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
regmap_update_bits(priv->regmap, CS35L33_PWRCTL1,
CS35L33_PDN_BST, 0);
val = priv->is_tdm_mode ? 0 : CS35L33_PDN_TDM;
regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
CS35L33_PDN_TDM, val);
dev_dbg(component->dev, "BST turned on\n");
break;
case SND_SOC_DAPM_POST_PMU:
dev_dbg(component->dev, "SDIN turned on\n");
if (!priv->amp_cal) {
regmap_update_bits(priv->regmap, CS35L33_CLASSD_CTL,
CS35L33_AMP_CAL, CS35L33_AMP_CAL);
dev_dbg(component->dev, "Amp calibration started\n");
usleep_range(10000, 11000);
}
break;
case SND_SOC_DAPM_POST_PMD:
regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
CS35L33_PDN_TDM, CS35L33_PDN_TDM);
usleep_range(4000, 4100);
regmap_update_bits(priv->regmap, CS35L33_PWRCTL1,
CS35L33_PDN_BST, CS35L33_PDN_BST);
dev_dbg(component->dev, "BST and SDIN turned off\n");
break;
default:
dev_err(component->dev, "Invalid event = 0x%x\n", event);
}
return 0;
}
static int cs35l33_sdout_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
unsigned int mask = CS35L33_SDOUT_3ST_I2S | CS35L33_PDN_TDM;
unsigned int mask2 = CS35L33_SDOUT_3ST_TDM;
unsigned int val, val2;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
if (priv->is_tdm_mode) {
/* set sdout_3st_i2s and reset pdn_tdm */
val = CS35L33_SDOUT_3ST_I2S;
/* reset sdout_3st_tdm */
val2 = 0;
} else {
/* reset sdout_3st_i2s and set pdn_tdm */
val = CS35L33_PDN_TDM;
/* set sdout_3st_tdm */
val2 = CS35L33_SDOUT_3ST_TDM;
}
dev_dbg(component->dev, "SDOUT turned on\n");
break;
case SND_SOC_DAPM_PRE_PMD:
val = CS35L33_SDOUT_3ST_I2S | CS35L33_PDN_TDM;
val2 = CS35L33_SDOUT_3ST_TDM;
dev_dbg(component->dev, "SDOUT turned off\n");
break;
default:
dev_err(component->dev, "Invalid event = 0x%x\n", event);
return 0;
}
regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
mask, val);
regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
mask2, val2);
return 0;
}
static const struct snd_soc_dapm_widget cs35l33_dapm_widgets[] = {
SND_SOC_DAPM_OUTPUT("SPK"),
SND_SOC_DAPM_OUT_DRV_E("SPKDRV", CS35L33_PWRCTL1, 7, 1, NULL, 0,
cs35l33_spkrdrv_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_AIF_IN_E("SDIN", NULL, 0, CS35L33_PWRCTL2,
2, 1, cs35l33_sdin_event, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_INPUT("MON"),
SND_SOC_DAPM_ADC("VMON", NULL,
CS35L33_PWRCTL2, CS35L33_PDN_VMON_SHIFT, 1),
SND_SOC_DAPM_ADC("IMON", NULL,
CS35L33_PWRCTL2, CS35L33_PDN_IMON_SHIFT, 1),
SND_SOC_DAPM_ADC("VPMON", NULL,
CS35L33_PWRCTL2, CS35L33_PDN_VPMON_SHIFT, 1),
SND_SOC_DAPM_ADC("VBSTMON", NULL,
CS35L33_PWRCTL2, CS35L33_PDN_VBSTMON_SHIFT, 1),
SND_SOC_DAPM_AIF_OUT_E("SDOUT", NULL, 0, SND_SOC_NOPM, 0, 0,
cs35l33_sdout_event, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_PRE_PMD),
};
static const struct snd_soc_dapm_route cs35l33_audio_map[] = {
{"SDIN", NULL, "CS35L33 Playback"},
{"SPKDRV", NULL, "SDIN"},
{"SPK", NULL, "SPKDRV"},
{"VMON", NULL, "MON"},
{"IMON", NULL, "MON"},
{"SDOUT", NULL, "VMON"},
{"SDOUT", NULL, "IMON"},
{"CS35L33 Capture", NULL, "SDOUT"},
};
static const struct snd_soc_dapm_route cs35l33_vphg_auto_route[] = {
{"SPKDRV", NULL, "VPMON"},
{"VPMON", NULL, "CS35L33 Playback"},
};
static const struct snd_soc_dapm_route cs35l33_vp_vbst_mon_route[] = {
{"SDOUT", NULL, "VPMON"},
{"VPMON", NULL, "MON"},
{"SDOUT", NULL, "VBSTMON"},
{"VBSTMON", NULL, "MON"},
};
static int cs35l33_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
unsigned int val;
struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
regmap_update_bits(priv->regmap, CS35L33_PWRCTL1,
CS35L33_PDN_ALL, 0);
regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
CS35L33_MCLKDIS, 0);
break;
case SND_SOC_BIAS_STANDBY:
regmap_update_bits(priv->regmap, CS35L33_PWRCTL1,
CS35L33_PDN_ALL, CS35L33_PDN_ALL);
regmap_read(priv->regmap, CS35L33_INT_STATUS_2, &val);
usleep_range(1000, 1100);
if (val & CS35L33_PDN_DONE)
regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
CS35L33_MCLKDIS, CS35L33_MCLKDIS);
break;
case SND_SOC_BIAS_OFF:
break;
default:
return -EINVAL;
}
return 0;
}
struct cs35l33_mclk_div {
int mclk;
int srate;
u8 adsp_rate;
u8 int_fs_ratio;
};
static const struct cs35l33_mclk_div cs35l33_mclk_coeffs[] = {
/* MCLK, Sample Rate, adsp_rate, int_fs_ratio */
{5644800, 11025, 0x4, CS35L33_INT_FS_RATE},
{5644800, 22050, 0x8, CS35L33_INT_FS_RATE},
{5644800, 44100, 0xC, CS35L33_INT_FS_RATE},
{6000000, 8000, 0x1, 0},
{6000000, 11025, 0x2, 0},
{6000000, 11029, 0x3, 0},
{6000000, 12000, 0x4, 0},
{6000000, 16000, 0x5, 0},
{6000000, 22050, 0x6, 0},
{6000000, 22059, 0x7, 0},
{6000000, 24000, 0x8, 0},
{6000000, 32000, 0x9, 0},
{6000000, 44100, 0xA, 0},
{6000000, 44118, 0xB, 0},
{6000000, 48000, 0xC, 0},
{6144000, 8000, 0x1, CS35L33_INT_FS_RATE},
{6144000, 12000, 0x4, CS35L33_INT_FS_RATE},
{6144000, 16000, 0x5, CS35L33_INT_FS_RATE},
{6144000, 24000, 0x8, CS35L33_INT_FS_RATE},
{6144000, 32000, 0x9, CS35L33_INT_FS_RATE},
{6144000, 48000, 0xC, CS35L33_INT_FS_RATE},
};
static int cs35l33_get_mclk_coeff(int mclk, int srate)
{
int i;
for (i = 0; i < ARRAY_SIZE(cs35l33_mclk_coeffs); i++) {
if (cs35l33_mclk_coeffs[i].mclk == mclk &&
cs35l33_mclk_coeffs[i].srate == srate)
return i;
}
return -EINVAL;
}
static int cs35l33_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
regmap_update_bits(priv->regmap, CS35L33_ADSP_CTL,
CS35L33_MS_MASK, CS35L33_MS_MASK);
dev_dbg(component->dev, "Audio port in master mode\n");
break;
case SND_SOC_DAIFMT_CBS_CFS:
regmap_update_bits(priv->regmap, CS35L33_ADSP_CTL,
CS35L33_MS_MASK, 0);
dev_dbg(component->dev, "Audio port in slave mode\n");
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
/*
* tdm mode in cs35l33 resembles dsp-a mode very
* closely, it is dsp-a with fsync shifted left by half bclk
*/
priv->is_tdm_mode = true;
dev_dbg(component->dev, "Audio port in TDM mode\n");
break;
case SND_SOC_DAIFMT_I2S:
priv->is_tdm_mode = false;
dev_dbg(component->dev, "Audio port in I2S mode\n");
break;
default:
return -EINVAL;
}
return 0;
}
static int cs35l33_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
int sample_size = params_width(params);
int coeff = cs35l33_get_mclk_coeff(priv->mclk_int, params_rate(params));
if (coeff < 0)
return coeff;
regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
CS35L33_ADSP_FS | CS35L33_INT_FS_RATE,
cs35l33_mclk_coeffs[coeff].int_fs_ratio
| cs35l33_mclk_coeffs[coeff].adsp_rate);
if (priv->is_tdm_mode) {
sample_size = (sample_size / 8) - 1;
if (sample_size > 2)
sample_size = 2;
regmap_update_bits(priv->regmap, CS35L33_RX_AUD,
CS35L33_AUDIN_RX_DEPTH,
sample_size << CS35L33_AUDIN_RX_DEPTH_SHIFT);
}
dev_dbg(component->dev, "sample rate=%d, bits per sample=%d\n",
params_rate(params), params_width(params));
return 0;
}
static const unsigned int cs35l33_src_rates[] = {
8000, 11025, 11029, 12000, 16000, 22050,
22059, 24000, 32000, 44100, 44118, 48000
};
static const struct snd_pcm_hw_constraint_list cs35l33_constraints = {
.count = ARRAY_SIZE(cs35l33_src_rates),
.list = cs35l33_src_rates,
};
static int cs35l33_pcm_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&cs35l33_constraints);
return 0;
}
static int cs35l33_set_tristate(struct snd_soc_dai *dai, int tristate)
{
struct snd_soc_component *component = dai->component;
struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
if (tristate) {
regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
CS35L33_SDOUT_3ST_I2S, CS35L33_SDOUT_3ST_I2S);
regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
CS35L33_SDOUT_3ST_TDM, CS35L33_SDOUT_3ST_TDM);
} else {
regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
CS35L33_SDOUT_3ST_I2S, 0);
regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
CS35L33_SDOUT_3ST_TDM, 0);
}
return 0;
}
static int cs35l33_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
unsigned int reg, bit_pos, i;
int slot, slot_num;
if (slot_width != 8)
return -EINVAL;
/* scan rx_mask for aud slot */
slot = ffs(rx_mask) - 1;
if (slot >= 0) {
regmap_update_bits(priv->regmap, CS35L33_RX_AUD,
CS35L33_X_LOC, slot);
dev_dbg(component->dev, "Audio starts from slots %d", slot);
}
/*
* scan tx_mask: vmon(2 slots); imon (2 slots);
* vpmon (1 slot) vbstmon (1 slot)
*/
slot = ffs(tx_mask) - 1;
slot_num = 0;
for (i = 0; i < 2 ; i++) {
/* disable vpmon/vbstmon: enable later if set in tx_mask */
regmap_update_bits(priv->regmap, CS35L33_TX_VPMON + i,
CS35L33_X_STATE | CS35L33_X_LOC, CS35L33_X_STATE
| CS35L33_X_LOC);
}
/* disconnect {vp,vbst}_mon routes: eanble later if set in tx_mask*/
snd_soc_dapm_del_routes(dapm, cs35l33_vp_vbst_mon_route,
ARRAY_SIZE(cs35l33_vp_vbst_mon_route));
while (slot >= 0) {
/* configure VMON_TX_LOC */
if (slot_num == 0) {
regmap_update_bits(priv->regmap, CS35L33_TX_VMON,
CS35L33_X_STATE | CS35L33_X_LOC, slot);
dev_dbg(component->dev, "VMON enabled in slots %d-%d",
slot, slot + 1);
}
/* configure IMON_TX_LOC */
if (slot_num == 3) {
regmap_update_bits(priv->regmap, CS35L33_TX_IMON,
CS35L33_X_STATE | CS35L33_X_LOC, slot);
dev_dbg(component->dev, "IMON enabled in slots %d-%d",
slot, slot + 1);
}
/* configure VPMON_TX_LOC */
if (slot_num == 4) {
regmap_update_bits(priv->regmap, CS35L33_TX_VPMON,
CS35L33_X_STATE | CS35L33_X_LOC, slot);
snd_soc_dapm_add_routes(dapm,
&cs35l33_vp_vbst_mon_route[0], 2);
dev_dbg(component->dev, "VPMON enabled in slots %d", slot);
}
/* configure VBSTMON_TX_LOC */
if (slot_num == 5) {
regmap_update_bits(priv->regmap, CS35L33_TX_VBSTMON,
CS35L33_X_STATE | CS35L33_X_LOC, slot);
snd_soc_dapm_add_routes(dapm,
&cs35l33_vp_vbst_mon_route[2], 2);
dev_dbg(component->dev,
"VBSTMON enabled in slots %d", slot);
}
/* Enable the relevant tx slot */
reg = CS35L33_TX_EN4 - (slot/8);
bit_pos = slot - ((slot / 8) * (8));
regmap_update_bits(priv->regmap, reg,
1 << bit_pos, 1 << bit_pos);
tx_mask &= ~(1 << slot);
slot = ffs(tx_mask) - 1;
slot_num++;
}
return 0;
}
static int cs35l33_component_set_sysclk(struct snd_soc_component *component,
int clk_id, int source, unsigned int freq, int dir)
{
struct cs35l33_private *cs35l33 = snd_soc_component_get_drvdata(component);
switch (freq) {
case CS35L33_MCLK_5644:
case CS35L33_MCLK_6:
case CS35L33_MCLK_6144:
regmap_update_bits(cs35l33->regmap, CS35L33_CLK_CTL,
CS35L33_MCLKDIV2, 0);
cs35l33->mclk_int = freq;
break;
case CS35L33_MCLK_11289:
case CS35L33_MCLK_12:
case CS35L33_MCLK_12288:
regmap_update_bits(cs35l33->regmap, CS35L33_CLK_CTL,
CS35L33_MCLKDIV2, CS35L33_MCLKDIV2);
cs35l33->mclk_int = freq/2;
break;
default:
cs35l33->mclk_int = 0;
return -EINVAL;
}
dev_dbg(component->dev, "external mclk freq=%d, internal mclk freq=%d\n",
freq, cs35l33->mclk_int);
return 0;
}
static const struct snd_soc_dai_ops cs35l33_ops = {
.startup = cs35l33_pcm_startup,
.set_tristate = cs35l33_set_tristate,
.set_fmt = cs35l33_set_dai_fmt,
.hw_params = cs35l33_pcm_hw_params,
.set_tdm_slot = cs35l33_set_tdm_slot,
};
static struct snd_soc_dai_driver cs35l33_dai = {
.name = "cs35l33-dai",
.id = 0,
.playback = {
.stream_name = "CS35L33 Playback",
.channels_min = 1,
.channels_max = 1,
.rates = CS35L33_RATES,
.formats = CS35L33_FORMATS,
},
.capture = {
.stream_name = "CS35L33 Capture",
.channels_min = 2,
.channels_max = 2,
.rates = CS35L33_RATES,
.formats = CS35L33_FORMATS,
},
.ops = &cs35l33_ops,
.symmetric_rate = 1,
};
static int cs35l33_set_hg_data(struct snd_soc_component *component,
struct cs35l33_pdata *pdata)
{
struct cs35l33_hg *hg_config = &pdata->hg_config;
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
if (hg_config->enable_hg_algo) {
regmap_update_bits(priv->regmap, CS35L33_HG_MEMLDO_CTL,
CS35L33_MEM_DEPTH_MASK,
hg_config->mem_depth << CS35L33_MEM_DEPTH_SHIFT);
regmap_write(priv->regmap, CS35L33_HG_REL_RATE,
hg_config->release_rate);
regmap_update_bits(priv->regmap, CS35L33_HG_HEAD,
CS35L33_HD_RM_MASK,
hg_config->hd_rm << CS35L33_HD_RM_SHIFT);
regmap_update_bits(priv->regmap, CS35L33_HG_MEMLDO_CTL,
CS35L33_LDO_THLD_MASK,
hg_config->ldo_thld << CS35L33_LDO_THLD_SHIFT);
regmap_update_bits(priv->regmap, CS35L33_HG_MEMLDO_CTL,
CS35L33_LDO_DISABLE_MASK,
hg_config->ldo_path_disable <<
CS35L33_LDO_DISABLE_SHIFT);
regmap_update_bits(priv->regmap, CS35L33_LDO_DEL,
CS35L33_LDO_ENTRY_DELAY_MASK,
hg_config->ldo_entry_delay <<
CS35L33_LDO_ENTRY_DELAY_SHIFT);
if (hg_config->vp_hg_auto) {
regmap_update_bits(priv->regmap, CS35L33_HG_EN,
CS35L33_VP_HG_AUTO_MASK,
CS35L33_VP_HG_AUTO_MASK);
snd_soc_dapm_add_routes(dapm, cs35l33_vphg_auto_route,
ARRAY_SIZE(cs35l33_vphg_auto_route));
}
regmap_update_bits(priv->regmap, CS35L33_HG_EN,
CS35L33_VP_HG_MASK,
hg_config->vp_hg << CS35L33_VP_HG_SHIFT);
regmap_update_bits(priv->regmap, CS35L33_LDO_DEL,
CS35L33_VP_HG_RATE_MASK,
hg_config->vp_hg_rate << CS35L33_VP_HG_RATE_SHIFT);
regmap_update_bits(priv->regmap, CS35L33_LDO_DEL,
CS35L33_VP_HG_VA_MASK,
hg_config->vp_hg_va << CS35L33_VP_HG_VA_SHIFT);
regmap_update_bits(priv->regmap, CS35L33_HG_EN,
CS35L33_CLASS_HG_EN_MASK, CS35L33_CLASS_HG_EN_MASK);
}
return 0;
}
static int cs35l33_set_bst_ipk(struct snd_soc_component *component, unsigned int bst)
{
struct cs35l33_private *cs35l33 = snd_soc_component_get_drvdata(component);
int ret = 0, steps = 0;
/* Boost current in uA */
if (bst > 3600000 || bst < 1850000) {
dev_err(component->dev, "Invalid boost current %d\n", bst);
ret = -EINVAL;
goto err;
}
if (bst % 15625) {
dev_err(component->dev, "Current not a multiple of 15625uA (%d)\n",
bst);
ret = -EINVAL;
goto err;
}
while (bst > 1850000) {
bst -= 15625;
steps++;
}
regmap_write(cs35l33->regmap, CS35L33_BST_PEAK_CTL,
steps+0x70);
err:
return ret;
}
static int cs35l33_probe(struct snd_soc_component *component)
{
struct cs35l33_private *cs35l33 = snd_soc_component_get_drvdata(component);
cs35l33->component = component;
pm_runtime_get_sync(component->dev);
regmap_update_bits(cs35l33->regmap, CS35L33_PROTECT_CTL,
CS35L33_ALIVE_WD_DIS, 0x8);
regmap_update_bits(cs35l33->regmap, CS35L33_BST_CTL2,
CS35L33_ALIVE_WD_DIS2,
CS35L33_ALIVE_WD_DIS2);
/* Set Platform Data */
regmap_update_bits(cs35l33->regmap, CS35L33_BST_CTL1,
CS35L33_BST_CTL_MASK, cs35l33->pdata.boost_ctl);
regmap_update_bits(cs35l33->regmap, CS35L33_CLASSD_CTL,
CS35L33_AMP_DRV_SEL_MASK,
cs35l33->pdata.amp_drv_sel << CS35L33_AMP_DRV_SEL_SHIFT);
if (cs35l33->pdata.boost_ipk)
cs35l33_set_bst_ipk(component, cs35l33->pdata.boost_ipk);
if (cs35l33->enable_soft_ramp) {
snd_soc_component_update_bits(component, CS35L33_DAC_CTL,
CS35L33_DIGSFT, CS35L33_DIGSFT);
snd_soc_component_update_bits(component, CS35L33_DAC_CTL,
CS35L33_DSR_RATE, cs35l33->pdata.ramp_rate);
} else {
snd_soc_component_update_bits(component, CS35L33_DAC_CTL,
CS35L33_DIGSFT, 0);
}
/* update IMON scaling rate if different from default of 0x8 */
if (cs35l33->pdata.imon_adc_scale != 0x8)
snd_soc_component_update_bits(component, CS35L33_ADC_CTL,
CS35L33_IMON_SCALE, cs35l33->pdata.imon_adc_scale);
cs35l33_set_hg_data(component, &(cs35l33->pdata));
/*
* unmask important interrupts that causes the chip to enter
* speaker safe mode and hence deserves user attention
*/
regmap_update_bits(cs35l33->regmap, CS35L33_INT_MASK_1,
CS35L33_M_OTE | CS35L33_M_OTW | CS35L33_M_AMP_SHORT |
CS35L33_M_CAL_ERR, 0);
pm_runtime_put_sync(component->dev);
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_cs35l33 = {
.probe = cs35l33_probe,
.set_bias_level = cs35l33_set_bias_level,
.set_sysclk = cs35l33_component_set_sysclk,
.controls = cs35l33_snd_controls,
.num_controls = ARRAY_SIZE(cs35l33_snd_controls),
.dapm_widgets = cs35l33_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(cs35l33_dapm_widgets),
.dapm_routes = cs35l33_audio_map,
.num_dapm_routes = ARRAY_SIZE(cs35l33_audio_map),
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config cs35l33_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = CS35L33_MAX_REGISTER,
.reg_defaults = cs35l33_reg,
.num_reg_defaults = ARRAY_SIZE(cs35l33_reg),
.volatile_reg = cs35l33_volatile_register,
.readable_reg = cs35l33_readable_register,
.writeable_reg = cs35l33_writeable_register,
.cache_type = REGCACHE_MAPLE,
.use_single_read = true,
.use_single_write = true,
};
static int __maybe_unused cs35l33_runtime_resume(struct device *dev)
{
struct cs35l33_private *cs35l33 = dev_get_drvdata(dev);
int ret;
dev_dbg(dev, "%s\n", __func__);
gpiod_set_value_cansleep(cs35l33->reset_gpio, 0);
ret = regulator_bulk_enable(cs35l33->num_core_supplies,
cs35l33->core_supplies);
if (ret != 0) {
dev_err(dev, "Failed to enable core supplies: %d\n", ret);
return ret;
}
regcache_cache_only(cs35l33->regmap, false);
gpiod_set_value_cansleep(cs35l33->reset_gpio, 1);
msleep(CS35L33_BOOT_DELAY);
ret = regcache_sync(cs35l33->regmap);
if (ret != 0) {
dev_err(dev, "Failed to restore register cache\n");
goto err;
}
return 0;
err:
regcache_cache_only(cs35l33->regmap, true);
regulator_bulk_disable(cs35l33->num_core_supplies,
cs35l33->core_supplies);
return ret;
}
static int __maybe_unused cs35l33_runtime_suspend(struct device *dev)
{
struct cs35l33_private *cs35l33 = dev_get_drvdata(dev);
dev_dbg(dev, "%s\n", __func__);
/* redo the calibration in next power up */
cs35l33->amp_cal = false;
regcache_cache_only(cs35l33->regmap, true);
regcache_mark_dirty(cs35l33->regmap);
regulator_bulk_disable(cs35l33->num_core_supplies,
cs35l33->core_supplies);
return 0;
}
static const struct dev_pm_ops cs35l33_pm_ops = {
SET_RUNTIME_PM_OPS(cs35l33_runtime_suspend,
cs35l33_runtime_resume,
NULL)
};
static int cs35l33_get_hg_data(const struct device_node *np,
struct cs35l33_pdata *pdata)
{
struct device_node *hg;
struct cs35l33_hg *hg_config = &pdata->hg_config;
u32 val32;
hg = of_get_child_by_name(np, "cirrus,hg-algo");
hg_config->enable_hg_algo = hg ? true : false;
if (hg_config->enable_hg_algo) {
if (of_property_read_u32(hg, "cirrus,mem-depth", &val32) >= 0)
hg_config->mem_depth = val32;
if (of_property_read_u32(hg, "cirrus,release-rate",
&val32) >= 0)
hg_config->release_rate = val32;
if (of_property_read_u32(hg, "cirrus,ldo-thld", &val32) >= 0)
hg_config->ldo_thld = val32;
if (of_property_read_u32(hg, "cirrus,ldo-path-disable",
&val32) >= 0)
hg_config->ldo_path_disable = val32;
if (of_property_read_u32(hg, "cirrus,ldo-entry-delay",
&val32) >= 0)
hg_config->ldo_entry_delay = val32;
hg_config->vp_hg_auto = of_property_read_bool(hg,
"cirrus,vp-hg-auto");
if (of_property_read_u32(hg, "cirrus,vp-hg", &val32) >= 0)
hg_config->vp_hg = val32;
if (of_property_read_u32(hg, "cirrus,vp-hg-rate", &val32) >= 0)
hg_config->vp_hg_rate = val32;
if (of_property_read_u32(hg, "cirrus,vp-hg-va", &val32) >= 0)
hg_config->vp_hg_va = val32;
}
of_node_put(hg);
return 0;
}
static irqreturn_t cs35l33_irq_thread(int irq, void *data)
{
struct cs35l33_private *cs35l33 = data;
struct snd_soc_component *component = cs35l33->component;
unsigned int sticky_val1, sticky_val2, current_val, mask1, mask2;
regmap_read(cs35l33->regmap, CS35L33_INT_STATUS_2,
&sticky_val2);
regmap_read(cs35l33->regmap, CS35L33_INT_STATUS_1,
&sticky_val1);
regmap_read(cs35l33->regmap, CS35L33_INT_MASK_2, &mask2);
regmap_read(cs35l33->regmap, CS35L33_INT_MASK_1, &mask1);
/* Check to see if the unmasked bits are active,
* if not then exit.
*/
if (!(sticky_val1 & ~mask1) && !(sticky_val2 & ~mask2))
return IRQ_NONE;
regmap_read(cs35l33->regmap, CS35L33_INT_STATUS_1,
¤t_val);
/* handle the interrupts */
if (sticky_val1 & CS35L33_AMP_SHORT) {
dev_crit(component->dev, "Amp short error\n");
if (!(current_val & CS35L33_AMP_SHORT)) {
dev_dbg(component->dev,
"Amp short error release\n");
regmap_update_bits(cs35l33->regmap,
CS35L33_AMP_CTL,
CS35L33_AMP_SHORT_RLS, 0);
regmap_update_bits(cs35l33->regmap,
CS35L33_AMP_CTL,
CS35L33_AMP_SHORT_RLS,
CS35L33_AMP_SHORT_RLS);
regmap_update_bits(cs35l33->regmap,
CS35L33_AMP_CTL, CS35L33_AMP_SHORT_RLS,
0);
}
}
if (sticky_val1 & CS35L33_CAL_ERR) {
dev_err(component->dev, "Cal error\n");
/* redo the calibration in next power up */
cs35l33->amp_cal = false;
if (!(current_val & CS35L33_CAL_ERR)) {
dev_dbg(component->dev, "Cal error release\n");
regmap_update_bits(cs35l33->regmap,
CS35L33_AMP_CTL, CS35L33_CAL_ERR_RLS,
0);
regmap_update_bits(cs35l33->regmap,
CS35L33_AMP_CTL, CS35L33_CAL_ERR_RLS,
CS35L33_CAL_ERR_RLS);
regmap_update_bits(cs35l33->regmap,
CS35L33_AMP_CTL, CS35L33_CAL_ERR_RLS,
0);
}
}
if (sticky_val1 & CS35L33_OTE) {
dev_crit(component->dev, "Over temperature error\n");
if (!(current_val & CS35L33_OTE)) {
dev_dbg(component->dev,
"Over temperature error release\n");
regmap_update_bits(cs35l33->regmap,
CS35L33_AMP_CTL, CS35L33_OTE_RLS, 0);
regmap_update_bits(cs35l33->regmap,
CS35L33_AMP_CTL, CS35L33_OTE_RLS,
CS35L33_OTE_RLS);
regmap_update_bits(cs35l33->regmap,
CS35L33_AMP_CTL, CS35L33_OTE_RLS, 0);
}
}
if (sticky_val1 & CS35L33_OTW) {
dev_err(component->dev, "Over temperature warning\n");
if (!(current_val & CS35L33_OTW)) {
dev_dbg(component->dev,
"Over temperature warning release\n");
regmap_update_bits(cs35l33->regmap,
CS35L33_AMP_CTL, CS35L33_OTW_RLS, 0);
regmap_update_bits(cs35l33->regmap,
CS35L33_AMP_CTL, CS35L33_OTW_RLS,
CS35L33_OTW_RLS);
regmap_update_bits(cs35l33->regmap,
CS35L33_AMP_CTL, CS35L33_OTW_RLS, 0);
}
}
if (CS35L33_ALIVE_ERR & sticky_val1)
dev_err(component->dev, "ERROR: ADSPCLK Interrupt\n");
if (CS35L33_MCLK_ERR & sticky_val1)
dev_err(component->dev, "ERROR: MCLK Interrupt\n");
if (CS35L33_VMON_OVFL & sticky_val2)
dev_err(component->dev,
"ERROR: VMON Overflow Interrupt\n");
if (CS35L33_IMON_OVFL & sticky_val2)
dev_err(component->dev,
"ERROR: IMON Overflow Interrupt\n");
if (CS35L33_VPMON_OVFL & sticky_val2)
dev_err(component->dev,
"ERROR: VPMON Overflow Interrupt\n");
return IRQ_HANDLED;
}
static const char * const cs35l33_core_supplies[] = {
"VA",
"VP",
};
static int cs35l33_of_get_pdata(struct device *dev,
struct cs35l33_private *cs35l33)
{
struct device_node *np = dev->of_node;
struct cs35l33_pdata *pdata = &cs35l33->pdata;
u32 val32;
if (!np)
return 0;
if (of_property_read_u32(np, "cirrus,boost-ctl", &val32) >= 0) {
pdata->boost_ctl = val32;
pdata->amp_drv_sel = 1;
}
if (of_property_read_u32(np, "cirrus,ramp-rate", &val32) >= 0) {
pdata->ramp_rate = val32;
cs35l33->enable_soft_ramp = true;
}
if (of_property_read_u32(np, "cirrus,boost-ipk", &val32) >= 0)
pdata->boost_ipk = val32;
if (of_property_read_u32(np, "cirrus,imon-adc-scale", &val32) >= 0) {
if ((val32 == 0x0) || (val32 == 0x7) || (val32 == 0x6))
pdata->imon_adc_scale = val32;
else
/* use default value */
pdata->imon_adc_scale = 0x8;
} else {
/* use default value */
pdata->imon_adc_scale = 0x8;
}
cs35l33_get_hg_data(np, pdata);
return 0;
}
static int cs35l33_i2c_probe(struct i2c_client *i2c_client)
{
struct cs35l33_private *cs35l33;
struct cs35l33_pdata *pdata = dev_get_platdata(&i2c_client->dev);
int ret, devid, i;
unsigned int reg;
cs35l33 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs35l33_private),
GFP_KERNEL);
if (!cs35l33)
return -ENOMEM;
i2c_set_clientdata(i2c_client, cs35l33);
cs35l33->regmap = devm_regmap_init_i2c(i2c_client, &cs35l33_regmap);
if (IS_ERR(cs35l33->regmap)) {
ret = PTR_ERR(cs35l33->regmap);
dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
return ret;
}
regcache_cache_only(cs35l33->regmap, true);
for (i = 0; i < ARRAY_SIZE(cs35l33_core_supplies); i++)
cs35l33->core_supplies[i].supply
= cs35l33_core_supplies[i];
cs35l33->num_core_supplies = ARRAY_SIZE(cs35l33_core_supplies);
ret = devm_regulator_bulk_get(&i2c_client->dev,
cs35l33->num_core_supplies,
cs35l33->core_supplies);
if (ret != 0) {
dev_err(&i2c_client->dev,
"Failed to request core supplies: %d\n",
ret);
return ret;
}
if (pdata) {
cs35l33->pdata = *pdata;
} else {
cs35l33_of_get_pdata(&i2c_client->dev, cs35l33);
pdata = &cs35l33->pdata;
}
ret = devm_request_threaded_irq(&i2c_client->dev, i2c_client->irq, NULL,
cs35l33_irq_thread, IRQF_ONESHOT | IRQF_TRIGGER_LOW,
"cs35l33", cs35l33);
if (ret != 0)
dev_warn(&i2c_client->dev, "Failed to request IRQ: %d\n", ret);
/* We could issue !RST or skip it based on AMP topology */
cs35l33->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
"reset-gpios", GPIOD_OUT_HIGH);
if (IS_ERR(cs35l33->reset_gpio)) {
dev_err(&i2c_client->dev, "%s ERROR: Can't get reset GPIO\n",
__func__);
return PTR_ERR(cs35l33->reset_gpio);
}
ret = regulator_bulk_enable(cs35l33->num_core_supplies,
cs35l33->core_supplies);
if (ret != 0) {
dev_err(&i2c_client->dev,
"Failed to enable core supplies: %d\n",
ret);
return ret;
}
gpiod_set_value_cansleep(cs35l33->reset_gpio, 1);
msleep(CS35L33_BOOT_DELAY);
regcache_cache_only(cs35l33->regmap, false);
/* initialize codec */
devid = cirrus_read_device_id(cs35l33->regmap, CS35L33_DEVID_AB);
if (devid < 0) {
ret = devid;
dev_err(&i2c_client->dev, "Failed to read device ID: %d\n", ret);
goto err_enable;
}
if (devid != CS35L33_CHIP_ID) {
dev_err(&i2c_client->dev,
"CS35L33 Device ID (%X). Expected ID %X\n",
devid, CS35L33_CHIP_ID);
ret = -EINVAL;
goto err_enable;
}
ret = regmap_read(cs35l33->regmap, CS35L33_REV_ID, ®);
if (ret < 0) {
dev_err(&i2c_client->dev, "Get Revision ID failed\n");
goto err_enable;
}
dev_info(&i2c_client->dev,
"Cirrus Logic CS35L33, Revision: %02X\n", reg & 0xFF);
ret = regmap_register_patch(cs35l33->regmap,
cs35l33_patch, ARRAY_SIZE(cs35l33_patch));
if (ret < 0) {
dev_err(&i2c_client->dev,
"Error in applying regmap patch: %d\n", ret);
goto err_enable;
}
/* disable mclk and tdm */
regmap_update_bits(cs35l33->regmap, CS35L33_CLK_CTL,
CS35L33_MCLKDIS | CS35L33_SDOUT_3ST_TDM,
CS35L33_MCLKDIS | CS35L33_SDOUT_3ST_TDM);
pm_runtime_set_autosuspend_delay(&i2c_client->dev, 100);
pm_runtime_use_autosuspend(&i2c_client->dev);
pm_runtime_set_active(&i2c_client->dev);
pm_runtime_enable(&i2c_client->dev);
ret = devm_snd_soc_register_component(&i2c_client->dev,
&soc_component_dev_cs35l33, &cs35l33_dai, 1);
if (ret < 0) {
dev_err(&i2c_client->dev, "%s: Register component failed\n",
__func__);
goto err_enable;
}
return 0;
err_enable:
gpiod_set_value_cansleep(cs35l33->reset_gpio, 0);
regulator_bulk_disable(cs35l33->num_core_supplies,
cs35l33->core_supplies);
return ret;
}
static void cs35l33_i2c_remove(struct i2c_client *client)
{
struct cs35l33_private *cs35l33 = i2c_get_clientdata(client);
gpiod_set_value_cansleep(cs35l33->reset_gpio, 0);
pm_runtime_disable(&client->dev);
regulator_bulk_disable(cs35l33->num_core_supplies,
cs35l33->core_supplies);
}
static const struct of_device_id cs35l33_of_match[] = {
{ .compatible = "cirrus,cs35l33", },
{},
};
MODULE_DEVICE_TABLE(of, cs35l33_of_match);
static const struct i2c_device_id cs35l33_id[] = {
{"cs35l33", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, cs35l33_id);
static struct i2c_driver cs35l33_i2c_driver = {
.driver = {
.name = "cs35l33",
.pm = &cs35l33_pm_ops,
.of_match_table = cs35l33_of_match,
},
.id_table = cs35l33_id,
.probe = cs35l33_i2c_probe,
.remove = cs35l33_i2c_remove,
};
module_i2c_driver(cs35l33_i2c_driver);
MODULE_DESCRIPTION("ASoC CS35L33 driver");
MODULE_AUTHOR("Paul Handrigan, Cirrus Logic Inc, <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cs35l33.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* rt5640.c -- RT5640/RT5639 ALSA SoC audio codec driver
*
* Copyright 2011 Realtek Semiconductor Corp.
* Author: Johnny Hsu <[email protected]>
* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/acpi.h>
#include <sound/core.h>
#include <sound/jack.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "rl6231.h"
#include "rt5640.h"
#define RT5640_DEVICE_ID 0x6231
#define RT5640_PR_RANGE_BASE (0xff + 1)
#define RT5640_PR_SPACING 0x100
#define RT5640_PR_BASE (RT5640_PR_RANGE_BASE + (0 * RT5640_PR_SPACING))
static const struct regmap_range_cfg rt5640_ranges[] = {
{ .name = "PR", .range_min = RT5640_PR_BASE,
.range_max = RT5640_PR_BASE + 0xb4,
.selector_reg = RT5640_PRIV_INDEX,
.selector_mask = 0xff,
.selector_shift = 0x0,
.window_start = RT5640_PRIV_DATA,
.window_len = 0x1, },
};
static const struct reg_sequence init_list[] = {
{RT5640_PR_BASE + 0x3d, 0x3600},
{RT5640_PR_BASE + 0x12, 0x0aa8},
{RT5640_PR_BASE + 0x14, 0x0aaa},
{RT5640_PR_BASE + 0x21, 0xe0e0},
{RT5640_PR_BASE + 0x23, 0x1804},
};
static const struct reg_default rt5640_reg[] = {
{ 0x00, 0x000e },
{ 0x01, 0xc8c8 },
{ 0x02, 0xc8c8 },
{ 0x03, 0xc8c8 },
{ 0x04, 0x8000 },
{ 0x0d, 0x0000 },
{ 0x0e, 0x0000 },
{ 0x0f, 0x0808 },
{ 0x19, 0xafaf },
{ 0x1a, 0xafaf },
{ 0x1b, 0x0000 },
{ 0x1c, 0x2f2f },
{ 0x1d, 0x2f2f },
{ 0x1e, 0x0000 },
{ 0x27, 0x7060 },
{ 0x28, 0x7070 },
{ 0x29, 0x8080 },
{ 0x2a, 0x5454 },
{ 0x2b, 0x5454 },
{ 0x2c, 0xaa00 },
{ 0x2d, 0x0000 },
{ 0x2e, 0xa000 },
{ 0x2f, 0x0000 },
{ 0x3b, 0x0000 },
{ 0x3c, 0x007f },
{ 0x3d, 0x0000 },
{ 0x3e, 0x007f },
{ 0x45, 0xe000 },
{ 0x46, 0x003e },
{ 0x47, 0x003e },
{ 0x48, 0xf800 },
{ 0x49, 0x3800 },
{ 0x4a, 0x0004 },
{ 0x4c, 0xfc00 },
{ 0x4d, 0x0000 },
{ 0x4f, 0x01ff },
{ 0x50, 0x0000 },
{ 0x51, 0x0000 },
{ 0x52, 0x01ff },
{ 0x53, 0xf000 },
{ 0x61, 0x0000 },
{ 0x62, 0x0000 },
{ 0x63, 0x00c0 },
{ 0x64, 0x0000 },
{ 0x65, 0x0000 },
{ 0x66, 0x0000 },
{ 0x6a, 0x0000 },
{ 0x6c, 0x0000 },
{ 0x70, 0x8000 },
{ 0x71, 0x8000 },
{ 0x72, 0x8000 },
{ 0x73, 0x1114 },
{ 0x74, 0x0c00 },
{ 0x75, 0x1d00 },
{ 0x80, 0x0000 },
{ 0x81, 0x0000 },
{ 0x82, 0x0000 },
{ 0x83, 0x0000 },
{ 0x84, 0x0000 },
{ 0x85, 0x0008 },
{ 0x89, 0x0000 },
{ 0x8a, 0x0000 },
{ 0x8b, 0x0600 },
{ 0x8c, 0x0228 },
{ 0x8d, 0xa000 },
{ 0x8e, 0x0004 },
{ 0x8f, 0x1100 },
{ 0x90, 0x0646 },
{ 0x91, 0x0c00 },
{ 0x92, 0x0000 },
{ 0x93, 0x3000 },
{ 0xb0, 0x2080 },
{ 0xb1, 0x0000 },
{ 0xb4, 0x2206 },
{ 0xb5, 0x1f00 },
{ 0xb6, 0x0000 },
{ 0xb8, 0x034b },
{ 0xb9, 0x0066 },
{ 0xba, 0x000b },
{ 0xbb, 0x0000 },
{ 0xbc, 0x0000 },
{ 0xbd, 0x0000 },
{ 0xbe, 0x0000 },
{ 0xbf, 0x0000 },
{ 0xc0, 0x0400 },
{ 0xc2, 0x0000 },
{ 0xc4, 0x0000 },
{ 0xc5, 0x0000 },
{ 0xc6, 0x2000 },
{ 0xc8, 0x0000 },
{ 0xc9, 0x0000 },
{ 0xca, 0x0000 },
{ 0xcb, 0x0000 },
{ 0xcc, 0x0000 },
{ 0xcf, 0x0013 },
{ 0xd0, 0x0680 },
{ 0xd1, 0x1c17 },
{ 0xd2, 0x8c00 },
{ 0xd3, 0xaa20 },
{ 0xd6, 0x0400 },
{ 0xd9, 0x0809 },
{ 0xfe, 0x10ec },
{ 0xff, 0x6231 },
};
static int rt5640_reset(struct snd_soc_component *component)
{
return snd_soc_component_write(component, RT5640_RESET, 0);
}
static bool rt5640_volatile_register(struct device *dev, unsigned int reg)
{
int i;
for (i = 0; i < ARRAY_SIZE(rt5640_ranges); i++)
if ((reg >= rt5640_ranges[i].window_start &&
reg <= rt5640_ranges[i].window_start +
rt5640_ranges[i].window_len) ||
(reg >= rt5640_ranges[i].range_min &&
reg <= rt5640_ranges[i].range_max))
return true;
switch (reg) {
case RT5640_RESET:
case RT5640_ASRC_5:
case RT5640_EQ_CTRL1:
case RT5640_DRC_AGC_1:
case RT5640_ANC_CTRL1:
case RT5640_IRQ_CTRL2:
case RT5640_INT_IRQ_ST:
case RT5640_DSP_CTRL2:
case RT5640_DSP_CTRL3:
case RT5640_PRIV_INDEX:
case RT5640_PRIV_DATA:
case RT5640_PGM_REG_ARR1:
case RT5640_PGM_REG_ARR3:
case RT5640_DUMMY2:
case RT5640_VENDOR_ID:
case RT5640_VENDOR_ID1:
case RT5640_VENDOR_ID2:
return true;
default:
return false;
}
}
static bool rt5640_readable_register(struct device *dev, unsigned int reg)
{
int i;
for (i = 0; i < ARRAY_SIZE(rt5640_ranges); i++)
if ((reg >= rt5640_ranges[i].window_start &&
reg <= rt5640_ranges[i].window_start +
rt5640_ranges[i].window_len) ||
(reg >= rt5640_ranges[i].range_min &&
reg <= rt5640_ranges[i].range_max))
return true;
switch (reg) {
case RT5640_RESET:
case RT5640_SPK_VOL:
case RT5640_HP_VOL:
case RT5640_OUTPUT:
case RT5640_MONO_OUT:
case RT5640_IN1_IN2:
case RT5640_IN3_IN4:
case RT5640_INL_INR_VOL:
case RT5640_DAC1_DIG_VOL:
case RT5640_DAC2_DIG_VOL:
case RT5640_DAC2_CTRL:
case RT5640_ADC_DIG_VOL:
case RT5640_ADC_DATA:
case RT5640_ADC_BST_VOL:
case RT5640_STO_ADC_MIXER:
case RT5640_MONO_ADC_MIXER:
case RT5640_AD_DA_MIXER:
case RT5640_STO_DAC_MIXER:
case RT5640_MONO_DAC_MIXER:
case RT5640_DIG_MIXER:
case RT5640_DSP_PATH1:
case RT5640_DSP_PATH2:
case RT5640_DIG_INF_DATA:
case RT5640_REC_L1_MIXER:
case RT5640_REC_L2_MIXER:
case RT5640_REC_R1_MIXER:
case RT5640_REC_R2_MIXER:
case RT5640_HPO_MIXER:
case RT5640_SPK_L_MIXER:
case RT5640_SPK_R_MIXER:
case RT5640_SPO_L_MIXER:
case RT5640_SPO_R_MIXER:
case RT5640_SPO_CLSD_RATIO:
case RT5640_MONO_MIXER:
case RT5640_OUT_L1_MIXER:
case RT5640_OUT_L2_MIXER:
case RT5640_OUT_L3_MIXER:
case RT5640_OUT_R1_MIXER:
case RT5640_OUT_R2_MIXER:
case RT5640_OUT_R3_MIXER:
case RT5640_LOUT_MIXER:
case RT5640_PWR_DIG1:
case RT5640_PWR_DIG2:
case RT5640_PWR_ANLG1:
case RT5640_PWR_ANLG2:
case RT5640_PWR_MIXER:
case RT5640_PWR_VOL:
case RT5640_PRIV_INDEX:
case RT5640_PRIV_DATA:
case RT5640_I2S1_SDP:
case RT5640_I2S2_SDP:
case RT5640_ADDA_CLK1:
case RT5640_ADDA_CLK2:
case RT5640_DMIC:
case RT5640_GLB_CLK:
case RT5640_PLL_CTRL1:
case RT5640_PLL_CTRL2:
case RT5640_ASRC_1:
case RT5640_ASRC_2:
case RT5640_ASRC_3:
case RT5640_ASRC_4:
case RT5640_ASRC_5:
case RT5640_HP_OVCD:
case RT5640_CLS_D_OVCD:
case RT5640_CLS_D_OUT:
case RT5640_DEPOP_M1:
case RT5640_DEPOP_M2:
case RT5640_DEPOP_M3:
case RT5640_CHARGE_PUMP:
case RT5640_PV_DET_SPK_G:
case RT5640_MICBIAS:
case RT5640_EQ_CTRL1:
case RT5640_EQ_CTRL2:
case RT5640_WIND_FILTER:
case RT5640_DRC_AGC_1:
case RT5640_DRC_AGC_2:
case RT5640_DRC_AGC_3:
case RT5640_SVOL_ZC:
case RT5640_ANC_CTRL1:
case RT5640_ANC_CTRL2:
case RT5640_ANC_CTRL3:
case RT5640_JD_CTRL:
case RT5640_ANC_JD:
case RT5640_IRQ_CTRL1:
case RT5640_IRQ_CTRL2:
case RT5640_INT_IRQ_ST:
case RT5640_GPIO_CTRL1:
case RT5640_GPIO_CTRL2:
case RT5640_GPIO_CTRL3:
case RT5640_DSP_CTRL1:
case RT5640_DSP_CTRL2:
case RT5640_DSP_CTRL3:
case RT5640_DSP_CTRL4:
case RT5640_PGM_REG_ARR1:
case RT5640_PGM_REG_ARR2:
case RT5640_PGM_REG_ARR3:
case RT5640_PGM_REG_ARR4:
case RT5640_PGM_REG_ARR5:
case RT5640_SCB_FUNC:
case RT5640_SCB_CTRL:
case RT5640_BASE_BACK:
case RT5640_MP3_PLUS1:
case RT5640_MP3_PLUS2:
case RT5640_3D_HP:
case RT5640_ADJ_HPF:
case RT5640_HP_CALIB_AMP_DET:
case RT5640_HP_CALIB2:
case RT5640_SV_ZCD1:
case RT5640_SV_ZCD2:
case RT5640_DUMMY1:
case RT5640_DUMMY2:
case RT5640_DUMMY3:
case RT5640_VENDOR_ID:
case RT5640_VENDOR_ID1:
case RT5640_VENDOR_ID2:
return true;
default:
return false;
}
}
static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
static const DECLARE_TLV_DB_MINMAX(dac_vol_tlv, -6562, 0);
static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
static const DECLARE_TLV_DB_MINMAX(adc_vol_tlv, -1762, 3000);
static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
static const DECLARE_TLV_DB_RANGE(bst_tlv,
0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
);
/* Interface data select */
static const char * const rt5640_data_select[] = {
"Normal", "Swap", "left copy to right", "right copy to left"};
static SOC_ENUM_SINGLE_DECL(rt5640_if1_dac_enum, RT5640_DIG_INF_DATA,
RT5640_IF1_DAC_SEL_SFT, rt5640_data_select);
static SOC_ENUM_SINGLE_DECL(rt5640_if1_adc_enum, RT5640_DIG_INF_DATA,
RT5640_IF1_ADC_SEL_SFT, rt5640_data_select);
static SOC_ENUM_SINGLE_DECL(rt5640_if2_dac_enum, RT5640_DIG_INF_DATA,
RT5640_IF2_DAC_SEL_SFT, rt5640_data_select);
static SOC_ENUM_SINGLE_DECL(rt5640_if2_adc_enum, RT5640_DIG_INF_DATA,
RT5640_IF2_ADC_SEL_SFT, rt5640_data_select);
/* Class D speaker gain ratio */
static const char * const rt5640_clsd_spk_ratio[] = {"1.66x", "1.83x", "1.94x",
"2x", "2.11x", "2.22x", "2.33x", "2.44x", "2.55x", "2.66x", "2.77x"};
static SOC_ENUM_SINGLE_DECL(rt5640_clsd_spk_ratio_enum, RT5640_CLS_D_OUT,
RT5640_CLSD_RATIO_SFT, rt5640_clsd_spk_ratio);
static const struct snd_kcontrol_new rt5640_snd_controls[] = {
/* Speaker Output Volume */
SOC_DOUBLE("Speaker Channel Switch", RT5640_SPK_VOL,
RT5640_VOL_L_SFT, RT5640_VOL_R_SFT, 1, 1),
SOC_DOUBLE_TLV("Speaker Playback Volume", RT5640_SPK_VOL,
RT5640_L_VOL_SFT, RT5640_R_VOL_SFT, 39, 1, out_vol_tlv),
/* Headphone Output Volume */
SOC_DOUBLE("HP Channel Switch", RT5640_HP_VOL,
RT5640_VOL_L_SFT, RT5640_VOL_R_SFT, 1, 1),
SOC_DOUBLE_TLV("HP Playback Volume", RT5640_HP_VOL,
RT5640_L_VOL_SFT, RT5640_R_VOL_SFT, 39, 1, out_vol_tlv),
/* OUTPUT Control */
SOC_DOUBLE("OUT Playback Switch", RT5640_OUTPUT,
RT5640_L_MUTE_SFT, RT5640_R_MUTE_SFT, 1, 1),
SOC_DOUBLE("OUT Channel Switch", RT5640_OUTPUT,
RT5640_VOL_L_SFT, RT5640_VOL_R_SFT, 1, 1),
SOC_DOUBLE_TLV("OUT Playback Volume", RT5640_OUTPUT,
RT5640_L_VOL_SFT, RT5640_R_VOL_SFT, 39, 1, out_vol_tlv),
/* DAC Digital Volume */
SOC_DOUBLE("DAC2 Playback Switch", RT5640_DAC2_CTRL,
RT5640_M_DAC_L2_VOL_SFT, RT5640_M_DAC_R2_VOL_SFT, 1, 1),
SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5640_DAC2_DIG_VOL,
RT5640_L_VOL_SFT, RT5640_R_VOL_SFT,
175, 0, dac_vol_tlv),
SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5640_DAC1_DIG_VOL,
RT5640_L_VOL_SFT, RT5640_R_VOL_SFT,
175, 0, dac_vol_tlv),
/* IN1/IN2/IN3 Control */
SOC_SINGLE_TLV("IN1 Boost", RT5640_IN1_IN2,
RT5640_BST_SFT1, 8, 0, bst_tlv),
SOC_SINGLE_TLV("IN2 Boost", RT5640_IN3_IN4,
RT5640_BST_SFT2, 8, 0, bst_tlv),
SOC_SINGLE_TLV("IN3 Boost", RT5640_IN1_IN2,
RT5640_BST_SFT2, 8, 0, bst_tlv),
/* INL/INR Volume Control */
SOC_DOUBLE_TLV("IN Capture Volume", RT5640_INL_INR_VOL,
RT5640_INL_VOL_SFT, RT5640_INR_VOL_SFT,
31, 1, in_vol_tlv),
/* ADC Digital Volume Control */
SOC_DOUBLE("ADC Capture Switch", RT5640_ADC_DIG_VOL,
RT5640_L_MUTE_SFT, RT5640_R_MUTE_SFT, 1, 1),
SOC_DOUBLE_TLV("ADC Capture Volume", RT5640_ADC_DIG_VOL,
RT5640_L_VOL_SFT, RT5640_R_VOL_SFT,
127, 0, adc_vol_tlv),
SOC_DOUBLE("Mono ADC Capture Switch", RT5640_DUMMY1,
RT5640_M_MONO_ADC_L_SFT, RT5640_M_MONO_ADC_R_SFT, 1, 1),
SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5640_ADC_DATA,
RT5640_L_VOL_SFT, RT5640_R_VOL_SFT,
127, 0, adc_vol_tlv),
/* ADC Boost Volume Control */
SOC_DOUBLE_TLV("ADC Boost Gain", RT5640_ADC_BST_VOL,
RT5640_ADC_L_BST_SFT, RT5640_ADC_R_BST_SFT,
3, 0, adc_bst_tlv),
/* Class D speaker gain ratio */
SOC_ENUM("Class D SPK Ratio Control", rt5640_clsd_spk_ratio_enum),
SOC_ENUM("ADC IF1 Data Switch", rt5640_if1_adc_enum),
SOC_ENUM("DAC IF1 Data Switch", rt5640_if1_dac_enum),
SOC_ENUM("ADC IF2 Data Switch", rt5640_if2_adc_enum),
SOC_ENUM("DAC IF2 Data Switch", rt5640_if2_dac_enum),
};
static const struct snd_kcontrol_new rt5640_specific_snd_controls[] = {
/* MONO Output Control */
SOC_SINGLE("Mono Playback Switch", RT5640_MONO_OUT, RT5640_L_MUTE_SFT,
1, 1),
};
/**
* set_dmic_clk - Set parameter of dmic.
*
* @w: DAPM widget.
* @kcontrol: The kcontrol of this widget.
* @event: Event id.
*
*/
static int set_dmic_clk(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
int idx, rate;
rate = rt5640->sysclk / rl6231_get_pre_div(rt5640->regmap,
RT5640_ADDA_CLK1, RT5640_I2S_PD1_SFT);
idx = rl6231_calc_dmic_clk(rate);
if (idx < 0)
dev_err(component->dev, "Failed to set DMIC clock\n");
else
snd_soc_component_update_bits(component, RT5640_DMIC, RT5640_DMIC_CLK_MASK,
idx << RT5640_DMIC_CLK_SFT);
return idx;
}
static int is_using_asrc(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
if (!rt5640->asrc_en)
return 0;
return 1;
}
/* Digital Mixer */
static const struct snd_kcontrol_new rt5640_sto_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5640_STO_ADC_MIXER,
RT5640_M_ADC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5640_STO_ADC_MIXER,
RT5640_M_ADC_L2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5640_sto_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5640_STO_ADC_MIXER,
RT5640_M_ADC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5640_STO_ADC_MIXER,
RT5640_M_ADC_R2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5640_mono_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5640_MONO_ADC_MIXER,
RT5640_M_MONO_ADC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5640_MONO_ADC_MIXER,
RT5640_M_MONO_ADC_L2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5640_mono_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5640_MONO_ADC_MIXER,
RT5640_M_MONO_ADC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5640_MONO_ADC_MIXER,
RT5640_M_MONO_ADC_R2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5640_dac_l_mix[] = {
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5640_AD_DA_MIXER,
RT5640_M_ADCMIX_L_SFT, 1, 1),
SOC_DAPM_SINGLE("INF1 Switch", RT5640_AD_DA_MIXER,
RT5640_M_IF1_DAC_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5640_dac_r_mix[] = {
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5640_AD_DA_MIXER,
RT5640_M_ADCMIX_R_SFT, 1, 1),
SOC_DAPM_SINGLE("INF1 Switch", RT5640_AD_DA_MIXER,
RT5640_M_IF1_DAC_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5640_sto_dac_l_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_STO_DAC_MIXER,
RT5640_M_DAC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_STO_DAC_MIXER,
RT5640_M_DAC_L2_SFT, 1, 1),
SOC_DAPM_SINGLE("ANC Switch", RT5640_STO_DAC_MIXER,
RT5640_M_ANC_DAC_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5640_sto_dac_r_mix[] = {
SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_STO_DAC_MIXER,
RT5640_M_DAC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_STO_DAC_MIXER,
RT5640_M_DAC_R2_SFT, 1, 1),
SOC_DAPM_SINGLE("ANC Switch", RT5640_STO_DAC_MIXER,
RT5640_M_ANC_DAC_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5639_sto_dac_l_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_STO_DAC_MIXER,
RT5640_M_DAC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_STO_DAC_MIXER,
RT5640_M_DAC_L2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5639_sto_dac_r_mix[] = {
SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_STO_DAC_MIXER,
RT5640_M_DAC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_STO_DAC_MIXER,
RT5640_M_DAC_R2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5640_mono_dac_l_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_MONO_DAC_MIXER,
RT5640_M_DAC_L1_MONO_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_MONO_DAC_MIXER,
RT5640_M_DAC_L2_MONO_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_MONO_DAC_MIXER,
RT5640_M_DAC_R2_MONO_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5640_mono_dac_r_mix[] = {
SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_MONO_DAC_MIXER,
RT5640_M_DAC_R1_MONO_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_MONO_DAC_MIXER,
RT5640_M_DAC_R2_MONO_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_MONO_DAC_MIXER,
RT5640_M_DAC_L2_MONO_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5640_dig_l_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_DIG_MIXER,
RT5640_M_STO_L_DAC_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_DIG_MIXER,
RT5640_M_DAC_L2_DAC_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5640_dig_r_mix[] = {
SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_DIG_MIXER,
RT5640_M_STO_R_DAC_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_DIG_MIXER,
RT5640_M_DAC_R2_DAC_R_SFT, 1, 1),
};
/* Analog Input Mixer */
static const struct snd_kcontrol_new rt5640_rec_l_mix[] = {
SOC_DAPM_SINGLE("HPOL Switch", RT5640_REC_L2_MIXER,
RT5640_M_HP_L_RM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("INL Switch", RT5640_REC_L2_MIXER,
RT5640_M_IN_L_RM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST3 Switch", RT5640_REC_L2_MIXER,
RT5640_M_BST2_RM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5640_REC_L2_MIXER,
RT5640_M_BST4_RM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5640_REC_L2_MIXER,
RT5640_M_BST1_RM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("OUT MIXL Switch", RT5640_REC_L2_MIXER,
RT5640_M_OM_L_RM_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5640_rec_r_mix[] = {
SOC_DAPM_SINGLE("HPOR Switch", RT5640_REC_R2_MIXER,
RT5640_M_HP_R_RM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("INR Switch", RT5640_REC_R2_MIXER,
RT5640_M_IN_R_RM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST3 Switch", RT5640_REC_R2_MIXER,
RT5640_M_BST2_RM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5640_REC_R2_MIXER,
RT5640_M_BST4_RM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5640_REC_R2_MIXER,
RT5640_M_BST1_RM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("OUT MIXR Switch", RT5640_REC_R2_MIXER,
RT5640_M_OM_R_RM_R_SFT, 1, 1),
};
/* Analog Output Mixer */
static const struct snd_kcontrol_new rt5640_spk_l_mix[] = {
SOC_DAPM_SINGLE("REC MIXL Switch", RT5640_SPK_L_MIXER,
RT5640_M_RM_L_SM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("INL Switch", RT5640_SPK_L_MIXER,
RT5640_M_IN_L_SM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_SPK_L_MIXER,
RT5640_M_DAC_L1_SM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_SPK_L_MIXER,
RT5640_M_DAC_L2_SM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("OUT MIXL Switch", RT5640_SPK_L_MIXER,
RT5640_M_OM_L_SM_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5640_spk_r_mix[] = {
SOC_DAPM_SINGLE("REC MIXR Switch", RT5640_SPK_R_MIXER,
RT5640_M_RM_R_SM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("INR Switch", RT5640_SPK_R_MIXER,
RT5640_M_IN_R_SM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_SPK_R_MIXER,
RT5640_M_DAC_R1_SM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_SPK_R_MIXER,
RT5640_M_DAC_R2_SM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("OUT MIXR Switch", RT5640_SPK_R_MIXER,
RT5640_M_OM_R_SM_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5640_out_l_mix[] = {
SOC_DAPM_SINGLE("SPK MIXL Switch", RT5640_OUT_L3_MIXER,
RT5640_M_SM_L_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5640_OUT_L3_MIXER,
RT5640_M_BST1_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("INL Switch", RT5640_OUT_L3_MIXER,
RT5640_M_IN_L_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("REC MIXL Switch", RT5640_OUT_L3_MIXER,
RT5640_M_RM_L_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_OUT_L3_MIXER,
RT5640_M_DAC_R2_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_OUT_L3_MIXER,
RT5640_M_DAC_L2_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_OUT_L3_MIXER,
RT5640_M_DAC_L1_OM_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5640_out_r_mix[] = {
SOC_DAPM_SINGLE("SPK MIXR Switch", RT5640_OUT_R3_MIXER,
RT5640_M_SM_L_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5640_OUT_R3_MIXER,
RT5640_M_BST4_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5640_OUT_R3_MIXER,
RT5640_M_BST1_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("INR Switch", RT5640_OUT_R3_MIXER,
RT5640_M_IN_R_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("REC MIXR Switch", RT5640_OUT_R3_MIXER,
RT5640_M_RM_R_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_OUT_R3_MIXER,
RT5640_M_DAC_L2_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_OUT_R3_MIXER,
RT5640_M_DAC_R2_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_OUT_R3_MIXER,
RT5640_M_DAC_R1_OM_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5639_out_l_mix[] = {
SOC_DAPM_SINGLE("BST1 Switch", RT5640_OUT_L3_MIXER,
RT5640_M_BST1_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("INL Switch", RT5640_OUT_L3_MIXER,
RT5640_M_IN_L_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("REC MIXL Switch", RT5640_OUT_L3_MIXER,
RT5640_M_RM_L_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_OUT_L3_MIXER,
RT5640_M_DAC_L1_OM_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5639_out_r_mix[] = {
SOC_DAPM_SINGLE("BST2 Switch", RT5640_OUT_R3_MIXER,
RT5640_M_BST4_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5640_OUT_R3_MIXER,
RT5640_M_BST1_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("INR Switch", RT5640_OUT_R3_MIXER,
RT5640_M_IN_R_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("REC MIXR Switch", RT5640_OUT_R3_MIXER,
RT5640_M_RM_R_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_OUT_R3_MIXER,
RT5640_M_DAC_R1_OM_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5640_spo_l_mix[] = {
SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_SPO_L_MIXER,
RT5640_M_DAC_R1_SPM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_SPO_L_MIXER,
RT5640_M_DAC_L1_SPM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("SPKVOL R Switch", RT5640_SPO_L_MIXER,
RT5640_M_SV_R_SPM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("SPKVOL L Switch", RT5640_SPO_L_MIXER,
RT5640_M_SV_L_SPM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5640_SPO_L_MIXER,
RT5640_M_BST1_SPM_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5640_spo_r_mix[] = {
SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_SPO_R_MIXER,
RT5640_M_DAC_R1_SPM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("SPKVOL R Switch", RT5640_SPO_R_MIXER,
RT5640_M_SV_R_SPM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5640_SPO_R_MIXER,
RT5640_M_BST1_SPM_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5640_hpo_mix[] = {
SOC_DAPM_SINGLE("HPO MIX DAC2 Switch", RT5640_HPO_MIXER,
RT5640_M_DAC2_HM_SFT, 1, 1),
SOC_DAPM_SINGLE("HPO MIX DAC1 Switch", RT5640_HPO_MIXER,
RT5640_M_DAC1_HM_SFT, 1, 1),
SOC_DAPM_SINGLE("HPO MIX HPVOL Switch", RT5640_HPO_MIXER,
RT5640_M_HPVOL_HM_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5639_hpo_mix[] = {
SOC_DAPM_SINGLE("HPO MIX DAC1 Switch", RT5640_HPO_MIXER,
RT5640_M_DAC1_HM_SFT, 1, 1),
SOC_DAPM_SINGLE("HPO MIX HPVOL Switch", RT5640_HPO_MIXER,
RT5640_M_HPVOL_HM_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5640_lout_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_LOUT_MIXER,
RT5640_M_DAC_L1_LM_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_LOUT_MIXER,
RT5640_M_DAC_R1_LM_SFT, 1, 1),
SOC_DAPM_SINGLE("OUTVOL L Switch", RT5640_LOUT_MIXER,
RT5640_M_OV_L_LM_SFT, 1, 1),
SOC_DAPM_SINGLE("OUTVOL R Switch", RT5640_LOUT_MIXER,
RT5640_M_OV_R_LM_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5640_mono_mix[] = {
SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_MONO_MIXER,
RT5640_M_DAC_R2_MM_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_MONO_MIXER,
RT5640_M_DAC_L2_MM_SFT, 1, 1),
SOC_DAPM_SINGLE("OUTVOL R Switch", RT5640_MONO_MIXER,
RT5640_M_OV_R_MM_SFT, 1, 1),
SOC_DAPM_SINGLE("OUTVOL L Switch", RT5640_MONO_MIXER,
RT5640_M_OV_L_MM_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5640_MONO_MIXER,
RT5640_M_BST1_MM_SFT, 1, 1),
};
static const struct snd_kcontrol_new spk_l_enable_control =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5640_SPK_VOL,
RT5640_L_MUTE_SFT, 1, 1);
static const struct snd_kcontrol_new spk_r_enable_control =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5640_SPK_VOL,
RT5640_R_MUTE_SFT, 1, 1);
static const struct snd_kcontrol_new hp_l_enable_control =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5640_HP_VOL,
RT5640_L_MUTE_SFT, 1, 1);
static const struct snd_kcontrol_new hp_r_enable_control =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5640_HP_VOL,
RT5640_R_MUTE_SFT, 1, 1);
/* Stereo ADC source */
static const char * const rt5640_stereo_adc1_src[] = {
"DIG MIX", "ADC"
};
static SOC_ENUM_SINGLE_DECL(rt5640_stereo_adc1_enum, RT5640_STO_ADC_MIXER,
RT5640_ADC_1_SRC_SFT, rt5640_stereo_adc1_src);
static const struct snd_kcontrol_new rt5640_sto_adc_1_mux =
SOC_DAPM_ENUM("Stereo ADC1 Mux", rt5640_stereo_adc1_enum);
static const char * const rt5640_stereo_adc2_src[] = {
"DMIC1", "DMIC2", "DIG MIX"
};
static SOC_ENUM_SINGLE_DECL(rt5640_stereo_adc2_enum, RT5640_STO_ADC_MIXER,
RT5640_ADC_2_SRC_SFT, rt5640_stereo_adc2_src);
static const struct snd_kcontrol_new rt5640_sto_adc_2_mux =
SOC_DAPM_ENUM("Stereo ADC2 Mux", rt5640_stereo_adc2_enum);
/* Mono ADC source */
static const char * const rt5640_mono_adc_l1_src[] = {
"Mono DAC MIXL", "ADCL"
};
static SOC_ENUM_SINGLE_DECL(rt5640_mono_adc_l1_enum, RT5640_MONO_ADC_MIXER,
RT5640_MONO_ADC_L1_SRC_SFT, rt5640_mono_adc_l1_src);
static const struct snd_kcontrol_new rt5640_mono_adc_l1_mux =
SOC_DAPM_ENUM("Mono ADC1 left source", rt5640_mono_adc_l1_enum);
static const char * const rt5640_mono_adc_l2_src[] = {
"DMIC L1", "DMIC L2", "Mono DAC MIXL"
};
static SOC_ENUM_SINGLE_DECL(rt5640_mono_adc_l2_enum, RT5640_MONO_ADC_MIXER,
RT5640_MONO_ADC_L2_SRC_SFT, rt5640_mono_adc_l2_src);
static const struct snd_kcontrol_new rt5640_mono_adc_l2_mux =
SOC_DAPM_ENUM("Mono ADC2 left source", rt5640_mono_adc_l2_enum);
static const char * const rt5640_mono_adc_r1_src[] = {
"Mono DAC MIXR", "ADCR"
};
static SOC_ENUM_SINGLE_DECL(rt5640_mono_adc_r1_enum, RT5640_MONO_ADC_MIXER,
RT5640_MONO_ADC_R1_SRC_SFT, rt5640_mono_adc_r1_src);
static const struct snd_kcontrol_new rt5640_mono_adc_r1_mux =
SOC_DAPM_ENUM("Mono ADC1 right source", rt5640_mono_adc_r1_enum);
static const char * const rt5640_mono_adc_r2_src[] = {
"DMIC R1", "DMIC R2", "Mono DAC MIXR"
};
static SOC_ENUM_SINGLE_DECL(rt5640_mono_adc_r2_enum, RT5640_MONO_ADC_MIXER,
RT5640_MONO_ADC_R2_SRC_SFT, rt5640_mono_adc_r2_src);
static const struct snd_kcontrol_new rt5640_mono_adc_r2_mux =
SOC_DAPM_ENUM("Mono ADC2 right source", rt5640_mono_adc_r2_enum);
/* DAC2 channel source */
static const char * const rt5640_dac_l2_src[] = {
"IF2", "Base L/R"
};
static int rt5640_dac_l2_values[] = {
0,
3,
};
static SOC_VALUE_ENUM_SINGLE_DECL(rt5640_dac_l2_enum,
RT5640_DSP_PATH2, RT5640_DAC_L2_SEL_SFT,
0x3, rt5640_dac_l2_src, rt5640_dac_l2_values);
static const struct snd_kcontrol_new rt5640_dac_l2_mux =
SOC_DAPM_ENUM("DAC2 left channel source", rt5640_dac_l2_enum);
static const char * const rt5640_dac_r2_src[] = {
"IF2",
};
static int rt5640_dac_r2_values[] = {
0,
};
static SOC_VALUE_ENUM_SINGLE_DECL(rt5640_dac_r2_enum,
RT5640_DSP_PATH2, RT5640_DAC_R2_SEL_SFT,
0x3, rt5640_dac_r2_src, rt5640_dac_r2_values);
static const struct snd_kcontrol_new rt5640_dac_r2_mux =
SOC_DAPM_ENUM("DAC2 right channel source", rt5640_dac_r2_enum);
/* digital interface and iis interface map */
static const char * const rt5640_dai_iis_map[] = {
"1:1|2:2", "1:2|2:1", "1:1|2:1", "1:2|2:2"
};
static int rt5640_dai_iis_map_values[] = {
0,
5,
6,
7,
};
static SOC_VALUE_ENUM_SINGLE_DECL(rt5640_dai_iis_map_enum,
RT5640_I2S1_SDP, RT5640_I2S_IF_SFT,
0x7, rt5640_dai_iis_map,
rt5640_dai_iis_map_values);
static const struct snd_kcontrol_new rt5640_dai_mux =
SOC_DAPM_ENUM("DAI select", rt5640_dai_iis_map_enum);
/* SDI select */
static const char * const rt5640_sdi_sel[] = {
"IF1", "IF2"
};
static SOC_ENUM_SINGLE_DECL(rt5640_sdi_sel_enum, RT5640_I2S2_SDP,
RT5640_I2S2_SDI_SFT, rt5640_sdi_sel);
static const struct snd_kcontrol_new rt5640_sdi_mux =
SOC_DAPM_ENUM("SDI select", rt5640_sdi_sel_enum);
static void hp_amp_power_on(struct snd_soc_component *component)
{
struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
/* depop parameters */
regmap_update_bits(rt5640->regmap, RT5640_PR_BASE +
RT5640_CHPUMP_INT_REG1, 0x0700, 0x0200);
regmap_update_bits(rt5640->regmap, RT5640_DEPOP_M2,
RT5640_DEPOP_MASK, RT5640_DEPOP_MAN);
regmap_update_bits(rt5640->regmap, RT5640_DEPOP_M1,
RT5640_HP_CP_MASK | RT5640_HP_SG_MASK | RT5640_HP_CB_MASK,
RT5640_HP_CP_PU | RT5640_HP_SG_DIS | RT5640_HP_CB_PU);
regmap_write(rt5640->regmap, RT5640_PR_BASE + RT5640_HP_DCC_INT1,
0x9f00);
/* headphone amp power on */
regmap_update_bits(rt5640->regmap, RT5640_PWR_ANLG1,
RT5640_PWR_FV1 | RT5640_PWR_FV2, 0);
regmap_update_bits(rt5640->regmap, RT5640_PWR_ANLG1,
RT5640_PWR_HA,
RT5640_PWR_HA);
usleep_range(10000, 15000);
regmap_update_bits(rt5640->regmap, RT5640_PWR_ANLG1,
RT5640_PWR_FV1 | RT5640_PWR_FV2 ,
RT5640_PWR_FV1 | RT5640_PWR_FV2);
}
static void rt5640_pmu_depop(struct snd_soc_component *component)
{
struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
regmap_update_bits(rt5640->regmap, RT5640_DEPOP_M2,
RT5640_DEPOP_MASK | RT5640_DIG_DP_MASK,
RT5640_DEPOP_AUTO | RT5640_DIG_DP_EN);
regmap_update_bits(rt5640->regmap, RT5640_CHARGE_PUMP,
RT5640_PM_HP_MASK, RT5640_PM_HP_HV);
regmap_update_bits(rt5640->regmap, RT5640_DEPOP_M3,
RT5640_CP_FQ1_MASK | RT5640_CP_FQ2_MASK | RT5640_CP_FQ3_MASK,
(RT5640_CP_FQ_192_KHZ << RT5640_CP_FQ1_SFT) |
(RT5640_CP_FQ_12_KHZ << RT5640_CP_FQ2_SFT) |
(RT5640_CP_FQ_192_KHZ << RT5640_CP_FQ3_SFT));
regmap_write(rt5640->regmap, RT5640_PR_BASE +
RT5640_MAMP_INT_REG2, 0x1c00);
regmap_update_bits(rt5640->regmap, RT5640_DEPOP_M1,
RT5640_HP_CP_MASK | RT5640_HP_SG_MASK,
RT5640_HP_CP_PD | RT5640_HP_SG_EN);
regmap_update_bits(rt5640->regmap, RT5640_PR_BASE +
RT5640_CHPUMP_INT_REG1, 0x0700, 0x0400);
}
static int rt5640_hp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
rt5640_pmu_depop(component);
rt5640->hp_mute = false;
break;
case SND_SOC_DAPM_PRE_PMD:
rt5640->hp_mute = true;
msleep(70);
break;
default:
return 0;
}
return 0;
}
static int rt5640_lout_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
hp_amp_power_on(component);
snd_soc_component_update_bits(component, RT5640_PWR_ANLG1,
RT5640_PWR_LM, RT5640_PWR_LM);
snd_soc_component_update_bits(component, RT5640_OUTPUT,
RT5640_L_MUTE | RT5640_R_MUTE, 0);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, RT5640_OUTPUT,
RT5640_L_MUTE | RT5640_R_MUTE,
RT5640_L_MUTE | RT5640_R_MUTE);
snd_soc_component_update_bits(component, RT5640_PWR_ANLG1,
RT5640_PWR_LM, 0);
break;
default:
return 0;
}
return 0;
}
static int rt5640_hp_power_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
hp_amp_power_on(component);
break;
default:
return 0;
}
return 0;
}
static int rt5640_hp_post_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
if (!rt5640->hp_mute)
msleep(80);
break;
default:
return 0;
}
return 0;
}
static const struct snd_soc_dapm_widget rt5640_dapm_widgets[] = {
/* ASRC */
SND_SOC_DAPM_SUPPLY_S("Stereo Filter ASRC", 1, RT5640_ASRC_1,
15, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("I2S2 Filter ASRC", 1, RT5640_ASRC_1,
12, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5640_ASRC_1,
11, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DMIC1 ASRC", 1, RT5640_ASRC_1,
9, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DMIC2 ASRC", 1, RT5640_ASRC_1,
8, 0, NULL, 0),
/* Input Side */
/* micbias */
SND_SOC_DAPM_SUPPLY("LDO2", RT5640_PWR_ANLG1,
RT5640_PWR_LDO2_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5640_PWR_ANLG2,
RT5640_PWR_MB1_BIT, 0, NULL, 0),
/* Input Lines */
SND_SOC_DAPM_INPUT("DMIC1"),
SND_SOC_DAPM_INPUT("DMIC2"),
SND_SOC_DAPM_INPUT("IN1P"),
SND_SOC_DAPM_INPUT("IN1N"),
SND_SOC_DAPM_INPUT("IN2P"),
SND_SOC_DAPM_INPUT("IN2N"),
SND_SOC_DAPM_INPUT("IN3P"),
SND_SOC_DAPM_INPUT("IN3N"),
SND_SOC_DAPM_PGA("DMIC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DMIC R1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DMIC L2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DMIC R2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5640_DMIC, RT5640_DMIC_1_EN_SFT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5640_DMIC, RT5640_DMIC_2_EN_SFT, 0,
NULL, 0),
/* Boost */
SND_SOC_DAPM_PGA("BST1", RT5640_PWR_ANLG2,
RT5640_PWR_BST1_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("BST2", RT5640_PWR_ANLG2,
RT5640_PWR_BST4_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("BST3", RT5640_PWR_ANLG2,
RT5640_PWR_BST2_BIT, 0, NULL, 0),
/* Input Volume */
SND_SOC_DAPM_PGA("INL VOL", RT5640_PWR_VOL,
RT5640_PWR_IN_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("INR VOL", RT5640_PWR_VOL,
RT5640_PWR_IN_R_BIT, 0, NULL, 0),
/* REC Mixer */
SND_SOC_DAPM_MIXER("RECMIXL", RT5640_PWR_MIXER, RT5640_PWR_RM_L_BIT, 0,
rt5640_rec_l_mix, ARRAY_SIZE(rt5640_rec_l_mix)),
SND_SOC_DAPM_MIXER("RECMIXR", RT5640_PWR_MIXER, RT5640_PWR_RM_R_BIT, 0,
rt5640_rec_r_mix, ARRAY_SIZE(rt5640_rec_r_mix)),
/* ADCs */
SND_SOC_DAPM_ADC("ADC L", NULL, RT5640_PWR_DIG1,
RT5640_PWR_ADC_L_BIT, 0),
SND_SOC_DAPM_ADC("ADC R", NULL, RT5640_PWR_DIG1,
RT5640_PWR_ADC_R_BIT, 0),
/* ADC Mux */
SND_SOC_DAPM_MUX("Stereo ADC L2 Mux", SND_SOC_NOPM, 0, 0,
&rt5640_sto_adc_2_mux),
SND_SOC_DAPM_MUX("Stereo ADC R2 Mux", SND_SOC_NOPM, 0, 0,
&rt5640_sto_adc_2_mux),
SND_SOC_DAPM_MUX("Stereo ADC L1 Mux", SND_SOC_NOPM, 0, 0,
&rt5640_sto_adc_1_mux),
SND_SOC_DAPM_MUX("Stereo ADC R1 Mux", SND_SOC_NOPM, 0, 0,
&rt5640_sto_adc_1_mux),
SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
&rt5640_mono_adc_l2_mux),
SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
&rt5640_mono_adc_l1_mux),
SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
&rt5640_mono_adc_r1_mux),
SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
&rt5640_mono_adc_r2_mux),
/* ADC Mixer */
SND_SOC_DAPM_SUPPLY("Stereo Filter", RT5640_PWR_DIG2,
RT5640_PWR_ADC_SF_BIT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Stereo ADC MIXL", SND_SOC_NOPM, 0, 0,
rt5640_sto_adc_l_mix, ARRAY_SIZE(rt5640_sto_adc_l_mix)),
SND_SOC_DAPM_MIXER("Stereo ADC MIXR", SND_SOC_NOPM, 0, 0,
rt5640_sto_adc_r_mix, ARRAY_SIZE(rt5640_sto_adc_r_mix)),
SND_SOC_DAPM_SUPPLY("Mono Left Filter", RT5640_PWR_DIG2,
RT5640_PWR_ADC_MF_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
rt5640_mono_adc_l_mix, ARRAY_SIZE(rt5640_mono_adc_l_mix)),
SND_SOC_DAPM_SUPPLY("Mono Right Filter", RT5640_PWR_DIG2,
RT5640_PWR_ADC_MF_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
rt5640_mono_adc_r_mix, ARRAY_SIZE(rt5640_mono_adc_r_mix)),
/* Digital Interface */
SND_SOC_DAPM_SUPPLY("I2S1", RT5640_PWR_DIG1,
RT5640_PWR_I2S1_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("I2S2", RT5640_PWR_DIG1,
RT5640_PWR_I2S2_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
/* Digital Interface Select */
SND_SOC_DAPM_MUX("DAI1 RX Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
SND_SOC_DAPM_MUX("DAI1 TX Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
SND_SOC_DAPM_MUX("DAI1 IF1 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
SND_SOC_DAPM_MUX("DAI1 IF2 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
SND_SOC_DAPM_MUX("SDI1 TX Mux", SND_SOC_NOPM, 0, 0, &rt5640_sdi_mux),
SND_SOC_DAPM_MUX("DAI2 RX Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
SND_SOC_DAPM_MUX("DAI2 TX Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
SND_SOC_DAPM_MUX("DAI2 IF1 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
SND_SOC_DAPM_MUX("DAI2 IF2 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
SND_SOC_DAPM_MUX("SDI2 TX Mux", SND_SOC_NOPM, 0, 0, &rt5640_sdi_mux),
/* Audio Interface */
SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
/* Output Side */
/* DAC mixer before sound effect */
SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
rt5640_dac_l_mix, ARRAY_SIZE(rt5640_dac_l_mix)),
SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
rt5640_dac_r_mix, ARRAY_SIZE(rt5640_dac_r_mix)),
/* DAC Mixer */
SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
rt5640_mono_dac_l_mix, ARRAY_SIZE(rt5640_mono_dac_l_mix)),
SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
rt5640_mono_dac_r_mix, ARRAY_SIZE(rt5640_mono_dac_r_mix)),
SND_SOC_DAPM_MIXER("DIG MIXL", SND_SOC_NOPM, 0, 0,
rt5640_dig_l_mix, ARRAY_SIZE(rt5640_dig_l_mix)),
SND_SOC_DAPM_MIXER("DIG MIXR", SND_SOC_NOPM, 0, 0,
rt5640_dig_r_mix, ARRAY_SIZE(rt5640_dig_r_mix)),
/* DACs */
SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM,
0, 0),
SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM,
0, 0),
SND_SOC_DAPM_SUPPLY("DAC L1 Power", RT5640_PWR_DIG1,
RT5640_PWR_DAC_L1_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC R1 Power", RT5640_PWR_DIG1,
RT5640_PWR_DAC_R1_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC L2 Power", RT5640_PWR_DIG1,
RT5640_PWR_DAC_L2_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC R2 Power", RT5640_PWR_DIG1,
RT5640_PWR_DAC_R2_BIT, 0, NULL, 0),
/* SPK/OUT Mixer */
SND_SOC_DAPM_MIXER("SPK MIXL", RT5640_PWR_MIXER, RT5640_PWR_SM_L_BIT,
0, rt5640_spk_l_mix, ARRAY_SIZE(rt5640_spk_l_mix)),
SND_SOC_DAPM_MIXER("SPK MIXR", RT5640_PWR_MIXER, RT5640_PWR_SM_R_BIT,
0, rt5640_spk_r_mix, ARRAY_SIZE(rt5640_spk_r_mix)),
/* Ouput Volume */
SND_SOC_DAPM_PGA("SPKVOL L", RT5640_PWR_VOL,
RT5640_PWR_SV_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("SPKVOL R", RT5640_PWR_VOL,
RT5640_PWR_SV_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("OUTVOL L", RT5640_PWR_VOL,
RT5640_PWR_OV_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("OUTVOL R", RT5640_PWR_VOL,
RT5640_PWR_OV_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("HPOVOL L", RT5640_PWR_VOL,
RT5640_PWR_HV_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("HPOVOL R", RT5640_PWR_VOL,
RT5640_PWR_HV_R_BIT, 0, NULL, 0),
/* SPO/HPO/LOUT/Mono Mixer */
SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0,
0, rt5640_spo_l_mix, ARRAY_SIZE(rt5640_spo_l_mix)),
SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0,
0, rt5640_spo_r_mix, ARRAY_SIZE(rt5640_spo_r_mix)),
SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0,
rt5640_lout_mix, ARRAY_SIZE(rt5640_lout_mix)),
SND_SOC_DAPM_SUPPLY_S("Improve HP Amp Drv", 1, SND_SOC_NOPM,
0, 0, rt5640_hp_power_event, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0,
rt5640_hp_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0,
rt5640_lout_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY("HP L Amp", RT5640_PWR_ANLG1,
RT5640_PWR_HP_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("HP R Amp", RT5640_PWR_ANLG1,
RT5640_PWR_HP_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Improve SPK Amp Drv", RT5640_PWR_DIG1,
RT5640_PWR_CLS_D_BIT, 0, NULL, 0),
/* Output Switch */
SND_SOC_DAPM_SWITCH("Speaker L Playback", SND_SOC_NOPM, 0, 0,
&spk_l_enable_control),
SND_SOC_DAPM_SWITCH("Speaker R Playback", SND_SOC_NOPM, 0, 0,
&spk_r_enable_control),
SND_SOC_DAPM_SWITCH("HP L Playback", SND_SOC_NOPM, 0, 0,
&hp_l_enable_control),
SND_SOC_DAPM_SWITCH("HP R Playback", SND_SOC_NOPM, 0, 0,
&hp_r_enable_control),
SND_SOC_DAPM_POST("HP Post", rt5640_hp_post_event),
/* Output Lines */
SND_SOC_DAPM_OUTPUT("SPOLP"),
SND_SOC_DAPM_OUTPUT("SPOLN"),
SND_SOC_DAPM_OUTPUT("SPORP"),
SND_SOC_DAPM_OUTPUT("SPORN"),
SND_SOC_DAPM_OUTPUT("HPOL"),
SND_SOC_DAPM_OUTPUT("HPOR"),
SND_SOC_DAPM_OUTPUT("LOUTL"),
SND_SOC_DAPM_OUTPUT("LOUTR"),
};
static const struct snd_soc_dapm_widget rt5640_specific_dapm_widgets[] = {
/* Audio DSP */
SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
/* ANC */
SND_SOC_DAPM_PGA("ANC", SND_SOC_NOPM, 0, 0, NULL, 0),
/* DAC2 channel Mux */
SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dac_l2_mux),
SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dac_r2_mux),
SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
rt5640_sto_dac_l_mix, ARRAY_SIZE(rt5640_sto_dac_l_mix)),
SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
rt5640_sto_dac_r_mix, ARRAY_SIZE(rt5640_sto_dac_r_mix)),
SND_SOC_DAPM_DAC("DAC R2", NULL, SND_SOC_NOPM, 0,
0),
SND_SOC_DAPM_DAC("DAC L2", NULL, SND_SOC_NOPM, 0,
0),
SND_SOC_DAPM_MIXER("OUT MIXL", RT5640_PWR_MIXER, RT5640_PWR_OM_L_BIT,
0, rt5640_out_l_mix, ARRAY_SIZE(rt5640_out_l_mix)),
SND_SOC_DAPM_MIXER("OUT MIXR", RT5640_PWR_MIXER, RT5640_PWR_OM_R_BIT,
0, rt5640_out_r_mix, ARRAY_SIZE(rt5640_out_r_mix)),
SND_SOC_DAPM_MIXER("HPO MIX L", SND_SOC_NOPM, 0, 0,
rt5640_hpo_mix, ARRAY_SIZE(rt5640_hpo_mix)),
SND_SOC_DAPM_MIXER("HPO MIX R", SND_SOC_NOPM, 0, 0,
rt5640_hpo_mix, ARRAY_SIZE(rt5640_hpo_mix)),
SND_SOC_DAPM_MIXER("Mono MIX", RT5640_PWR_ANLG1, RT5640_PWR_MM_BIT, 0,
rt5640_mono_mix, ARRAY_SIZE(rt5640_mono_mix)),
SND_SOC_DAPM_SUPPLY("Improve MONO Amp Drv", RT5640_PWR_ANLG1,
RT5640_PWR_MA_BIT, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("MONOP"),
SND_SOC_DAPM_OUTPUT("MONON"),
};
static const struct snd_soc_dapm_widget rt5639_specific_dapm_widgets[] = {
SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
rt5639_sto_dac_l_mix, ARRAY_SIZE(rt5639_sto_dac_l_mix)),
SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
rt5639_sto_dac_r_mix, ARRAY_SIZE(rt5639_sto_dac_r_mix)),
SND_SOC_DAPM_MIXER("OUT MIXL", RT5640_PWR_MIXER, RT5640_PWR_OM_L_BIT,
0, rt5639_out_l_mix, ARRAY_SIZE(rt5639_out_l_mix)),
SND_SOC_DAPM_MIXER("OUT MIXR", RT5640_PWR_MIXER, RT5640_PWR_OM_R_BIT,
0, rt5639_out_r_mix, ARRAY_SIZE(rt5639_out_r_mix)),
SND_SOC_DAPM_MIXER("HPO MIX L", SND_SOC_NOPM, 0, 0,
rt5639_hpo_mix, ARRAY_SIZE(rt5639_hpo_mix)),
SND_SOC_DAPM_MIXER("HPO MIX R", SND_SOC_NOPM, 0, 0,
rt5639_hpo_mix, ARRAY_SIZE(rt5639_hpo_mix)),
};
static const struct snd_soc_dapm_route rt5640_dapm_routes[] = {
{ "I2S1", NULL, "Stereo Filter ASRC", is_using_asrc },
{ "I2S2", NULL, "I2S2 ASRC", is_using_asrc },
{ "I2S2", NULL, "I2S2 Filter ASRC", is_using_asrc },
{ "DMIC1", NULL, "DMIC1 ASRC", is_using_asrc },
{ "DMIC2", NULL, "DMIC2 ASRC", is_using_asrc },
{"IN1P", NULL, "LDO2"},
{"IN2P", NULL, "LDO2"},
{"IN3P", NULL, "LDO2"},
{"DMIC L1", NULL, "DMIC1"},
{"DMIC R1", NULL, "DMIC1"},
{"DMIC L2", NULL, "DMIC2"},
{"DMIC R2", NULL, "DMIC2"},
{"BST1", NULL, "IN1P"},
{"BST1", NULL, "IN1N"},
{"BST2", NULL, "IN2P"},
{"BST2", NULL, "IN2N"},
{"BST3", NULL, "IN3P"},
{"BST3", NULL, "IN3N"},
{"INL VOL", NULL, "IN2P"},
{"INR VOL", NULL, "IN2N"},
{"RECMIXL", "HPOL Switch", "HPOL"},
{"RECMIXL", "INL Switch", "INL VOL"},
{"RECMIXL", "BST3 Switch", "BST3"},
{"RECMIXL", "BST2 Switch", "BST2"},
{"RECMIXL", "BST1 Switch", "BST1"},
{"RECMIXL", "OUT MIXL Switch", "OUT MIXL"},
{"RECMIXR", "HPOR Switch", "HPOR"},
{"RECMIXR", "INR Switch", "INR VOL"},
{"RECMIXR", "BST3 Switch", "BST3"},
{"RECMIXR", "BST2 Switch", "BST2"},
{"RECMIXR", "BST1 Switch", "BST1"},
{"RECMIXR", "OUT MIXR Switch", "OUT MIXR"},
{"ADC L", NULL, "RECMIXL"},
{"ADC R", NULL, "RECMIXR"},
{"DMIC L1", NULL, "DMIC CLK"},
{"DMIC L1", NULL, "DMIC1 Power"},
{"DMIC R1", NULL, "DMIC CLK"},
{"DMIC R1", NULL, "DMIC1 Power"},
{"DMIC L2", NULL, "DMIC CLK"},
{"DMIC L2", NULL, "DMIC2 Power"},
{"DMIC R2", NULL, "DMIC CLK"},
{"DMIC R2", NULL, "DMIC2 Power"},
{"Stereo ADC L2 Mux", "DMIC1", "DMIC L1"},
{"Stereo ADC L2 Mux", "DMIC2", "DMIC L2"},
{"Stereo ADC L2 Mux", "DIG MIX", "DIG MIXL"},
{"Stereo ADC L1 Mux", "ADC", "ADC L"},
{"Stereo ADC L1 Mux", "DIG MIX", "DIG MIXL"},
{"Stereo ADC R1 Mux", "ADC", "ADC R"},
{"Stereo ADC R1 Mux", "DIG MIX", "DIG MIXR"},
{"Stereo ADC R2 Mux", "DMIC1", "DMIC R1"},
{"Stereo ADC R2 Mux", "DMIC2", "DMIC R2"},
{"Stereo ADC R2 Mux", "DIG MIX", "DIG MIXR"},
{"Mono ADC L2 Mux", "DMIC L1", "DMIC L1"},
{"Mono ADC L2 Mux", "DMIC L2", "DMIC L2"},
{"Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL"},
{"Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL"},
{"Mono ADC L1 Mux", "ADCL", "ADC L"},
{"Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR"},
{"Mono ADC R1 Mux", "ADCR", "ADC R"},
{"Mono ADC R2 Mux", "DMIC R1", "DMIC R1"},
{"Mono ADC R2 Mux", "DMIC R2", "DMIC R2"},
{"Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR"},
{"Stereo ADC MIXL", "ADC1 Switch", "Stereo ADC L1 Mux"},
{"Stereo ADC MIXL", "ADC2 Switch", "Stereo ADC L2 Mux"},
{"Stereo ADC MIXL", NULL, "Stereo Filter"},
{"Stereo ADC MIXR", "ADC1 Switch", "Stereo ADC R1 Mux"},
{"Stereo ADC MIXR", "ADC2 Switch", "Stereo ADC R2 Mux"},
{"Stereo ADC MIXR", NULL, "Stereo Filter"},
{"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"},
{"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
{"Mono ADC MIXL", NULL, "Mono Left Filter"},
{"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
{"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
{"Mono ADC MIXR", NULL, "Mono Right Filter"},
{"IF2 ADC L", NULL, "Mono ADC MIXL"},
{"IF2 ADC R", NULL, "Mono ADC MIXR"},
{"IF1 ADC L", NULL, "Stereo ADC MIXL"},
{"IF1 ADC R", NULL, "Stereo ADC MIXR"},
{"IF1 ADC", NULL, "I2S1"},
{"IF1 ADC", NULL, "IF1 ADC L"},
{"IF1 ADC", NULL, "IF1 ADC R"},
{"IF2 ADC", NULL, "I2S2"},
{"IF2 ADC", NULL, "IF2 ADC L"},
{"IF2 ADC", NULL, "IF2 ADC R"},
{"DAI1 TX Mux", "1:1|2:2", "IF1 ADC"},
{"DAI1 TX Mux", "1:2|2:1", "IF2 ADC"},
{"DAI1 IF1 Mux", "1:1|2:1", "IF1 ADC"},
{"DAI1 IF2 Mux", "1:1|2:1", "IF2 ADC"},
{"SDI1 TX Mux", "IF1", "DAI1 IF1 Mux"},
{"SDI1 TX Mux", "IF2", "DAI1 IF2 Mux"},
{"DAI2 TX Mux", "1:2|2:1", "IF1 ADC"},
{"DAI2 TX Mux", "1:1|2:2", "IF2 ADC"},
{"DAI2 IF1 Mux", "1:2|2:2", "IF1 ADC"},
{"DAI2 IF2 Mux", "1:2|2:2", "IF2 ADC"},
{"SDI2 TX Mux", "IF1", "DAI2 IF1 Mux"},
{"SDI2 TX Mux", "IF2", "DAI2 IF2 Mux"},
{"AIF1TX", NULL, "DAI1 TX Mux"},
{"AIF1TX", NULL, "SDI1 TX Mux"},
{"AIF2TX", NULL, "DAI2 TX Mux"},
{"AIF2TX", NULL, "SDI2 TX Mux"},
{"DAI1 RX Mux", "1:1|2:2", "AIF1RX"},
{"DAI1 RX Mux", "1:1|2:1", "AIF1RX"},
{"DAI1 RX Mux", "1:2|2:1", "AIF2RX"},
{"DAI1 RX Mux", "1:2|2:2", "AIF2RX"},
{"DAI2 RX Mux", "1:2|2:1", "AIF1RX"},
{"DAI2 RX Mux", "1:1|2:1", "AIF1RX"},
{"DAI2 RX Mux", "1:1|2:2", "AIF2RX"},
{"DAI2 RX Mux", "1:2|2:2", "AIF2RX"},
{"IF1 DAC", NULL, "I2S1"},
{"IF1 DAC", NULL, "DAI1 RX Mux"},
{"IF2 DAC", NULL, "I2S2"},
{"IF2 DAC", NULL, "DAI2 RX Mux"},
{"IF1 DAC L", NULL, "IF1 DAC"},
{"IF1 DAC R", NULL, "IF1 DAC"},
{"IF2 DAC L", NULL, "IF2 DAC"},
{"IF2 DAC R", NULL, "IF2 DAC"},
{"DAC MIXL", "Stereo ADC Switch", "Stereo ADC MIXL"},
{"DAC MIXL", "INF1 Switch", "IF1 DAC L"},
{"DAC MIXL", NULL, "DAC L1 Power"},
{"DAC MIXR", "Stereo ADC Switch", "Stereo ADC MIXR"},
{"DAC MIXR", "INF1 Switch", "IF1 DAC R"},
{"DAC MIXR", NULL, "DAC R1 Power"},
{"Stereo DAC MIXL", "DAC L1 Switch", "DAC MIXL"},
{"Stereo DAC MIXR", "DAC R1 Switch", "DAC MIXR"},
{"Mono DAC MIXL", "DAC L1 Switch", "DAC MIXL"},
{"Mono DAC MIXR", "DAC R1 Switch", "DAC MIXR"},
{"DIG MIXL", "DAC L1 Switch", "DAC MIXL"},
{"DIG MIXR", "DAC R1 Switch", "DAC MIXR"},
{"DAC L1", NULL, "Stereo DAC MIXL"},
{"DAC L1", NULL, "DAC L1 Power"},
{"DAC R1", NULL, "Stereo DAC MIXR"},
{"DAC R1", NULL, "DAC R1 Power"},
{"SPK MIXL", "REC MIXL Switch", "RECMIXL"},
{"SPK MIXL", "INL Switch", "INL VOL"},
{"SPK MIXL", "DAC L1 Switch", "DAC L1"},
{"SPK MIXL", "OUT MIXL Switch", "OUT MIXL"},
{"SPK MIXR", "REC MIXR Switch", "RECMIXR"},
{"SPK MIXR", "INR Switch", "INR VOL"},
{"SPK MIXR", "DAC R1 Switch", "DAC R1"},
{"SPK MIXR", "OUT MIXR Switch", "OUT MIXR"},
{"OUT MIXL", "BST1 Switch", "BST1"},
{"OUT MIXL", "INL Switch", "INL VOL"},
{"OUT MIXL", "REC MIXL Switch", "RECMIXL"},
{"OUT MIXL", "DAC L1 Switch", "DAC L1"},
{"OUT MIXR", "BST2 Switch", "BST2"},
{"OUT MIXR", "BST1 Switch", "BST1"},
{"OUT MIXR", "INR Switch", "INR VOL"},
{"OUT MIXR", "REC MIXR Switch", "RECMIXR"},
{"OUT MIXR", "DAC R1 Switch", "DAC R1"},
{"SPKVOL L", NULL, "SPK MIXL"},
{"SPKVOL R", NULL, "SPK MIXR"},
{"HPOVOL L", NULL, "OUT MIXL"},
{"HPOVOL R", NULL, "OUT MIXR"},
{"OUTVOL L", NULL, "OUT MIXL"},
{"OUTVOL R", NULL, "OUT MIXR"},
{"SPOL MIX", "DAC R1 Switch", "DAC R1"},
{"SPOL MIX", "DAC L1 Switch", "DAC L1"},
{"SPOL MIX", "SPKVOL R Switch", "SPKVOL R"},
{"SPOL MIX", "SPKVOL L Switch", "SPKVOL L"},
{"SPOL MIX", "BST1 Switch", "BST1"},
{"SPOR MIX", "DAC R1 Switch", "DAC R1"},
{"SPOR MIX", "SPKVOL R Switch", "SPKVOL R"},
{"SPOR MIX", "BST1 Switch", "BST1"},
{"HPO MIX L", "HPO MIX DAC1 Switch", "DAC L1"},
{"HPO MIX L", "HPO MIX HPVOL Switch", "HPOVOL L"},
{"HPO MIX L", NULL, "HP L Amp"},
{"HPO MIX R", "HPO MIX DAC1 Switch", "DAC R1"},
{"HPO MIX R", "HPO MIX HPVOL Switch", "HPOVOL R"},
{"HPO MIX R", NULL, "HP R Amp"},
{"LOUT MIX", "DAC L1 Switch", "DAC L1"},
{"LOUT MIX", "DAC R1 Switch", "DAC R1"},
{"LOUT MIX", "OUTVOL L Switch", "OUTVOL L"},
{"LOUT MIX", "OUTVOL R Switch", "OUTVOL R"},
{"HP Amp", NULL, "HPO MIX L"},
{"HP Amp", NULL, "HPO MIX R"},
{"Speaker L Playback", "Switch", "SPOL MIX"},
{"Speaker R Playback", "Switch", "SPOR MIX"},
{"SPOLP", NULL, "Speaker L Playback"},
{"SPOLN", NULL, "Speaker L Playback"},
{"SPORP", NULL, "Speaker R Playback"},
{"SPORN", NULL, "Speaker R Playback"},
{"SPOLP", NULL, "Improve SPK Amp Drv"},
{"SPOLN", NULL, "Improve SPK Amp Drv"},
{"SPORP", NULL, "Improve SPK Amp Drv"},
{"SPORN", NULL, "Improve SPK Amp Drv"},
{"HPOL", NULL, "Improve HP Amp Drv"},
{"HPOR", NULL, "Improve HP Amp Drv"},
{"HP L Playback", "Switch", "HP Amp"},
{"HP R Playback", "Switch", "HP Amp"},
{"HPOL", NULL, "HP L Playback"},
{"HPOR", NULL, "HP R Playback"},
{"LOUT amp", NULL, "LOUT MIX"},
{"LOUTL", NULL, "LOUT amp"},
{"LOUTR", NULL, "LOUT amp"},
};
static const struct snd_soc_dapm_route rt5640_specific_dapm_routes[] = {
{"ANC", NULL, "Stereo ADC MIXL"},
{"ANC", NULL, "Stereo ADC MIXR"},
{"Audio DSP", NULL, "DAC MIXL"},
{"Audio DSP", NULL, "DAC MIXR"},
{"DAC L2 Mux", "IF2", "IF2 DAC L"},
{"DAC L2 Mux", "Base L/R", "Audio DSP"},
{"DAC L2 Mux", NULL, "DAC L2 Power"},
{"DAC R2 Mux", "IF2", "IF2 DAC R"},
{"DAC R2 Mux", NULL, "DAC R2 Power"},
{"Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
{"Stereo DAC MIXL", "ANC Switch", "ANC"},
{"Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
{"Stereo DAC MIXR", "ANC Switch", "ANC"},
{"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
{"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
{"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
{"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
{"DIG MIXR", "DAC R2 Switch", "DAC R2 Mux"},
{"DIG MIXL", "DAC L2 Switch", "DAC L2 Mux"},
{"DAC L2", NULL, "Mono DAC MIXL"},
{"DAC L2", NULL, "DAC L2 Power"},
{"DAC R2", NULL, "Mono DAC MIXR"},
{"DAC R2", NULL, "DAC R2 Power"},
{"SPK MIXL", "DAC L2 Switch", "DAC L2"},
{"SPK MIXR", "DAC R2 Switch", "DAC R2"},
{"OUT MIXL", "SPK MIXL Switch", "SPK MIXL"},
{"OUT MIXR", "SPK MIXR Switch", "SPK MIXR"},
{"OUT MIXL", "DAC R2 Switch", "DAC R2"},
{"OUT MIXL", "DAC L2 Switch", "DAC L2"},
{"OUT MIXR", "DAC L2 Switch", "DAC L2"},
{"OUT MIXR", "DAC R2 Switch", "DAC R2"},
{"HPO MIX L", "HPO MIX DAC2 Switch", "DAC L2"},
{"HPO MIX R", "HPO MIX DAC2 Switch", "DAC R2"},
{"Mono MIX", "DAC R2 Switch", "DAC R2"},
{"Mono MIX", "DAC L2 Switch", "DAC L2"},
{"Mono MIX", "OUTVOL R Switch", "OUTVOL R"},
{"Mono MIX", "OUTVOL L Switch", "OUTVOL L"},
{"Mono MIX", "BST1 Switch", "BST1"},
{"MONOP", NULL, "Mono MIX"},
{"MONON", NULL, "Mono MIX"},
{"MONOP", NULL, "Improve MONO Amp Drv"},
};
static const struct snd_soc_dapm_route rt5639_specific_dapm_routes[] = {
{"Stereo DAC MIXL", "DAC L2 Switch", "IF2 DAC L"},
{"Stereo DAC MIXR", "DAC R2 Switch", "IF2 DAC R"},
{"Mono DAC MIXL", "DAC L2 Switch", "IF2 DAC L"},
{"Mono DAC MIXL", "DAC R2 Switch", "IF2 DAC R"},
{"Mono DAC MIXR", "DAC R2 Switch", "IF2 DAC R"},
{"Mono DAC MIXR", "DAC L2 Switch", "IF2 DAC L"},
{"DIG MIXL", "DAC L2 Switch", "IF2 DAC L"},
{"DIG MIXR", "DAC R2 Switch", "IF2 DAC R"},
{"IF2 DAC L", NULL, "DAC L2 Power"},
{"IF2 DAC R", NULL, "DAC R2 Power"},
};
static int get_sdp_info(struct snd_soc_component *component, int dai_id)
{
int ret = 0, val;
if (component == NULL)
return -EINVAL;
val = snd_soc_component_read(component, RT5640_I2S1_SDP);
val = (val & RT5640_I2S_IF_MASK) >> RT5640_I2S_IF_SFT;
switch (dai_id) {
case RT5640_AIF1:
switch (val) {
case RT5640_IF_123:
case RT5640_IF_132:
ret |= RT5640_U_IF1;
break;
case RT5640_IF_113:
ret |= RT5640_U_IF1;
fallthrough;
case RT5640_IF_312:
case RT5640_IF_213:
ret |= RT5640_U_IF2;
break;
}
break;
case RT5640_AIF2:
switch (val) {
case RT5640_IF_231:
case RT5640_IF_213:
ret |= RT5640_U_IF1;
break;
case RT5640_IF_223:
ret |= RT5640_U_IF1;
fallthrough;
case RT5640_IF_123:
case RT5640_IF_321:
ret |= RT5640_U_IF2;
break;
}
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static int rt5640_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
unsigned int val_len = 0, val_clk, mask_clk;
int dai_sel, pre_div, bclk_ms, frame_size;
rt5640->lrck[dai->id] = params_rate(params);
pre_div = rl6231_get_clk_info(rt5640->sysclk, rt5640->lrck[dai->id]);
if (pre_div < 0) {
dev_err(component->dev, "Unsupported clock setting %d for DAI %d\n",
rt5640->lrck[dai->id], dai->id);
return -EINVAL;
}
frame_size = snd_soc_params_to_frame_size(params);
if (frame_size < 0) {
dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
return frame_size;
}
if (frame_size > 32)
bclk_ms = 1;
else
bclk_ms = 0;
rt5640->bclk[dai->id] = rt5640->lrck[dai->id] * (32 << bclk_ms);
dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
rt5640->bclk[dai->id], rt5640->lrck[dai->id]);
dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
bclk_ms, pre_div, dai->id);
switch (params_width(params)) {
case 16:
break;
case 20:
val_len |= RT5640_I2S_DL_20;
break;
case 24:
val_len |= RT5640_I2S_DL_24;
break;
case 8:
val_len |= RT5640_I2S_DL_8;
break;
default:
return -EINVAL;
}
dai_sel = get_sdp_info(component, dai->id);
if (dai_sel < 0) {
dev_err(component->dev, "Failed to get sdp info: %d\n", dai_sel);
return -EINVAL;
}
if (dai_sel & RT5640_U_IF1) {
mask_clk = RT5640_I2S_BCLK_MS1_MASK | RT5640_I2S_PD1_MASK;
val_clk = bclk_ms << RT5640_I2S_BCLK_MS1_SFT |
pre_div << RT5640_I2S_PD1_SFT;
snd_soc_component_update_bits(component, RT5640_I2S1_SDP,
RT5640_I2S_DL_MASK, val_len);
snd_soc_component_update_bits(component, RT5640_ADDA_CLK1, mask_clk, val_clk);
}
if (dai_sel & RT5640_U_IF2) {
mask_clk = RT5640_I2S_BCLK_MS2_MASK | RT5640_I2S_PD2_MASK;
val_clk = bclk_ms << RT5640_I2S_BCLK_MS2_SFT |
pre_div << RT5640_I2S_PD2_SFT;
snd_soc_component_update_bits(component, RT5640_I2S2_SDP,
RT5640_I2S_DL_MASK, val_len);
snd_soc_component_update_bits(component, RT5640_ADDA_CLK1, mask_clk, val_clk);
}
return 0;
}
static int rt5640_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0;
int dai_sel;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
rt5640->master[dai->id] = 1;
break;
case SND_SOC_DAIFMT_CBS_CFS:
reg_val |= RT5640_I2S_MS_S;
rt5640->master[dai->id] = 0;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
reg_val |= RT5640_I2S_BP_INV;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_LEFT_J:
reg_val |= RT5640_I2S_DF_LEFT;
break;
case SND_SOC_DAIFMT_DSP_A:
reg_val |= RT5640_I2S_DF_PCM_A;
break;
case SND_SOC_DAIFMT_DSP_B:
reg_val |= RT5640_I2S_DF_PCM_B;
break;
default:
return -EINVAL;
}
dai_sel = get_sdp_info(component, dai->id);
if (dai_sel < 0) {
dev_err(component->dev, "Failed to get sdp info: %d\n", dai_sel);
return -EINVAL;
}
if (dai_sel & RT5640_U_IF1) {
snd_soc_component_update_bits(component, RT5640_I2S1_SDP,
RT5640_I2S_MS_MASK | RT5640_I2S_BP_MASK |
RT5640_I2S_DF_MASK, reg_val);
}
if (dai_sel & RT5640_U_IF2) {
snd_soc_component_update_bits(component, RT5640_I2S2_SDP,
RT5640_I2S_MS_MASK | RT5640_I2S_BP_MASK |
RT5640_I2S_DF_MASK, reg_val);
}
return 0;
}
static int rt5640_set_dai_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0;
unsigned int pll_bit = 0;
int ret;
switch (clk_id) {
case RT5640_SCLK_S_MCLK:
ret = clk_set_rate(rt5640->mclk, freq);
if (ret)
return ret;
reg_val |= RT5640_SCLK_SRC_MCLK;
break;
case RT5640_SCLK_S_PLL1:
reg_val |= RT5640_SCLK_SRC_PLL1;
pll_bit |= RT5640_PWR_PLL;
break;
case RT5640_SCLK_S_RCCLK:
reg_val |= RT5640_SCLK_SRC_RCCLK;
break;
default:
dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
return -EINVAL;
}
snd_soc_component_update_bits(component, RT5640_PWR_ANLG2,
RT5640_PWR_PLL, pll_bit);
snd_soc_component_update_bits(component, RT5640_GLB_CLK,
RT5640_SCLK_SRC_MASK, reg_val);
rt5640->sysclk = freq;
rt5640->sysclk_src = clk_id;
dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
return 0;
}
static int rt5640_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
unsigned int freq_in, unsigned int freq_out)
{
struct snd_soc_component *component = dai->component;
struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
struct rl6231_pll_code pll_code;
int ret;
if (source == rt5640->pll_src && freq_in == rt5640->pll_in &&
freq_out == rt5640->pll_out)
return 0;
if (!freq_in || !freq_out) {
dev_dbg(component->dev, "PLL disabled\n");
rt5640->pll_in = 0;
rt5640->pll_out = 0;
snd_soc_component_update_bits(component, RT5640_GLB_CLK,
RT5640_SCLK_SRC_MASK, RT5640_SCLK_SRC_MCLK);
return 0;
}
switch (source) {
case RT5640_PLL1_S_MCLK:
snd_soc_component_update_bits(component, RT5640_GLB_CLK,
RT5640_PLL1_SRC_MASK, RT5640_PLL1_SRC_MCLK);
break;
case RT5640_PLL1_S_BCLK1:
snd_soc_component_update_bits(component, RT5640_GLB_CLK,
RT5640_PLL1_SRC_MASK, RT5640_PLL1_SRC_BCLK1);
break;
case RT5640_PLL1_S_BCLK2:
snd_soc_component_update_bits(component, RT5640_GLB_CLK,
RT5640_PLL1_SRC_MASK, RT5640_PLL1_SRC_BCLK2);
break;
default:
dev_err(component->dev, "Unknown PLL source %d\n", source);
return -EINVAL;
}
ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
if (ret < 0) {
dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
return ret;
}
dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
pll_code.n_code, pll_code.k_code);
snd_soc_component_write(component, RT5640_PLL_CTRL1,
(pll_code.n_code << RT5640_PLL_N_SFT) | pll_code.k_code);
snd_soc_component_write(component, RT5640_PLL_CTRL2,
((pll_code.m_bp ? 0 : pll_code.m_code) << RT5640_PLL_M_SFT) |
(pll_code.m_bp << RT5640_PLL_M_BP_SFT));
rt5640->pll_in = freq_in;
rt5640->pll_out = freq_out;
rt5640->pll_src = source;
return 0;
}
static int rt5640_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
int ret;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
/*
* SND_SOC_BIAS_PREPARE is called while preparing for a
* transition to ON or away from ON. If current bias_level
* is SND_SOC_BIAS_ON, then it is preparing for a transition
* away from ON. Disable the clock in that case, otherwise
* enable it.
*/
if (IS_ERR(rt5640->mclk))
break;
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) {
clk_disable_unprepare(rt5640->mclk);
} else {
ret = clk_prepare_enable(rt5640->mclk);
if (ret)
return ret;
}
break;
case SND_SOC_BIAS_STANDBY:
if (SND_SOC_BIAS_OFF == snd_soc_component_get_bias_level(component)) {
snd_soc_component_update_bits(component, RT5640_PWR_ANLG1,
RT5640_PWR_VREF1 | RT5640_PWR_MB |
RT5640_PWR_BG | RT5640_PWR_VREF2,
RT5640_PWR_VREF1 | RT5640_PWR_MB |
RT5640_PWR_BG | RT5640_PWR_VREF2);
usleep_range(10000, 15000);
snd_soc_component_update_bits(component, RT5640_PWR_ANLG1,
RT5640_PWR_FV1 | RT5640_PWR_FV2,
RT5640_PWR_FV1 | RT5640_PWR_FV2);
snd_soc_component_update_bits(component, RT5640_DUMMY1,
0x1, 0x1);
snd_soc_component_update_bits(component, RT5640_MICBIAS,
0x0030, 0x0030);
}
break;
case SND_SOC_BIAS_OFF:
snd_soc_component_write(component, RT5640_DEPOP_M1, 0x0004);
snd_soc_component_write(component, RT5640_DEPOP_M2, 0x1100);
snd_soc_component_update_bits(component, RT5640_DUMMY1, 0x1, 0);
snd_soc_component_write(component, RT5640_PWR_DIG1, 0x0000);
snd_soc_component_write(component, RT5640_PWR_DIG2, 0x0000);
snd_soc_component_write(component, RT5640_PWR_VOL, 0x0000);
snd_soc_component_write(component, RT5640_PWR_MIXER, 0x0000);
if (rt5640->jd_src == RT5640_JD_SRC_HDA_HEADER)
snd_soc_component_write(component, RT5640_PWR_ANLG1,
0x2818);
else
snd_soc_component_write(component, RT5640_PWR_ANLG1,
0x0000);
snd_soc_component_write(component, RT5640_PWR_ANLG2, 0x0000);
break;
default:
break;
}
return 0;
}
int rt5640_dmic_enable(struct snd_soc_component *component,
bool dmic1_data_pin, bool dmic2_data_pin)
{
struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
regmap_update_bits(rt5640->regmap, RT5640_GPIO_CTRL1,
RT5640_GP2_PIN_MASK, RT5640_GP2_PIN_DMIC1_SCL);
if (dmic1_data_pin) {
regmap_update_bits(rt5640->regmap, RT5640_DMIC,
RT5640_DMIC_1_DP_MASK, RT5640_DMIC_1_DP_GPIO3);
regmap_update_bits(rt5640->regmap, RT5640_GPIO_CTRL1,
RT5640_GP3_PIN_MASK, RT5640_GP3_PIN_DMIC1_SDA);
}
if (dmic2_data_pin) {
regmap_update_bits(rt5640->regmap, RT5640_DMIC,
RT5640_DMIC_2_DP_MASK, RT5640_DMIC_2_DP_GPIO4);
regmap_update_bits(rt5640->regmap, RT5640_GPIO_CTRL1,
RT5640_GP4_PIN_MASK, RT5640_GP4_PIN_DMIC2_SDA);
}
return 0;
}
EXPORT_SYMBOL_GPL(rt5640_dmic_enable);
int rt5640_sel_asrc_clk_src(struct snd_soc_component *component,
unsigned int filter_mask, unsigned int clk_src)
{
struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
unsigned int asrc2_mask = 0;
unsigned int asrc2_value = 0;
switch (clk_src) {
case RT5640_CLK_SEL_SYS:
case RT5640_CLK_SEL_ASRC:
break;
default:
return -EINVAL;
}
if (!filter_mask)
return -EINVAL;
if (filter_mask & RT5640_DA_STEREO_FILTER) {
asrc2_mask |= RT5640_STO_DAC_M_MASK;
asrc2_value = (asrc2_value & ~RT5640_STO_DAC_M_MASK)
| (clk_src << RT5640_STO_DAC_M_SFT);
}
if (filter_mask & RT5640_DA_MONO_L_FILTER) {
asrc2_mask |= RT5640_MDA_L_M_MASK;
asrc2_value = (asrc2_value & ~RT5640_MDA_L_M_MASK)
| (clk_src << RT5640_MDA_L_M_SFT);
}
if (filter_mask & RT5640_DA_MONO_R_FILTER) {
asrc2_mask |= RT5640_MDA_R_M_MASK;
asrc2_value = (asrc2_value & ~RT5640_MDA_R_M_MASK)
| (clk_src << RT5640_MDA_R_M_SFT);
}
if (filter_mask & RT5640_AD_STEREO_FILTER) {
asrc2_mask |= RT5640_ADC_M_MASK;
asrc2_value = (asrc2_value & ~RT5640_ADC_M_MASK)
| (clk_src << RT5640_ADC_M_SFT);
}
if (filter_mask & RT5640_AD_MONO_L_FILTER) {
asrc2_mask |= RT5640_MAD_L_M_MASK;
asrc2_value = (asrc2_value & ~RT5640_MAD_L_M_MASK)
| (clk_src << RT5640_MAD_L_M_SFT);
}
if (filter_mask & RT5640_AD_MONO_R_FILTER) {
asrc2_mask |= RT5640_MAD_R_M_MASK;
asrc2_value = (asrc2_value & ~RT5640_MAD_R_M_MASK)
| (clk_src << RT5640_MAD_R_M_SFT);
}
snd_soc_component_update_bits(component, RT5640_ASRC_2,
asrc2_mask, asrc2_value);
if (snd_soc_component_read(component, RT5640_ASRC_2)) {
rt5640->asrc_en = true;
snd_soc_component_update_bits(component, RT5640_JD_CTRL, 0x3, 0x3);
} else {
rt5640->asrc_en = false;
snd_soc_component_update_bits(component, RT5640_JD_CTRL, 0x3, 0x0);
}
return 0;
}
EXPORT_SYMBOL_GPL(rt5640_sel_asrc_clk_src);
void rt5640_enable_micbias1_for_ovcd(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
snd_soc_dapm_mutex_lock(dapm);
snd_soc_dapm_force_enable_pin_unlocked(dapm, "LDO2");
snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS1");
/* OVCD is unreliable when used with RCCLK as sysclk-source */
if (rt5640->use_platform_clock)
snd_soc_dapm_force_enable_pin_unlocked(dapm, "Platform Clock");
snd_soc_dapm_sync_unlocked(dapm);
snd_soc_dapm_mutex_unlock(dapm);
}
EXPORT_SYMBOL_GPL(rt5640_enable_micbias1_for_ovcd);
void rt5640_disable_micbias1_for_ovcd(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
snd_soc_dapm_mutex_lock(dapm);
if (rt5640->use_platform_clock)
snd_soc_dapm_disable_pin_unlocked(dapm, "Platform Clock");
snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS1");
snd_soc_dapm_disable_pin_unlocked(dapm, "LDO2");
snd_soc_dapm_sync_unlocked(dapm);
snd_soc_dapm_mutex_unlock(dapm);
}
EXPORT_SYMBOL_GPL(rt5640_disable_micbias1_for_ovcd);
static void rt5640_enable_micbias1_ovcd_irq(struct snd_soc_component *component)
{
struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
snd_soc_component_update_bits(component, RT5640_IRQ_CTRL2,
RT5640_IRQ_MB1_OC_MASK, RT5640_IRQ_MB1_OC_NOR);
rt5640->ovcd_irq_enabled = true;
}
static void rt5640_disable_micbias1_ovcd_irq(struct snd_soc_component *component)
{
struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
snd_soc_component_update_bits(component, RT5640_IRQ_CTRL2,
RT5640_IRQ_MB1_OC_MASK, RT5640_IRQ_MB1_OC_BP);
rt5640->ovcd_irq_enabled = false;
}
static void rt5640_clear_micbias1_ovcd(struct snd_soc_component *component)
{
snd_soc_component_update_bits(component, RT5640_IRQ_CTRL2,
RT5640_MB1_OC_STATUS, 0);
}
static bool rt5640_micbias1_ovcd(struct snd_soc_component *component)
{
int val;
val = snd_soc_component_read(component, RT5640_IRQ_CTRL2);
dev_dbg(component->dev, "irq ctrl2 %#04x\n", val);
return (val & RT5640_MB1_OC_STATUS);
}
static bool rt5640_jack_inserted(struct snd_soc_component *component)
{
struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
int val;
if (rt5640->jd_gpio)
val = gpiod_get_value(rt5640->jd_gpio) ? RT5640_JD_STATUS : 0;
else
val = snd_soc_component_read(component, RT5640_INT_IRQ_ST);
dev_dbg(component->dev, "irq status %#04x\n", val);
if (rt5640->jd_inverted)
return !(val & RT5640_JD_STATUS);
else
return (val & RT5640_JD_STATUS);
}
/* Jack detect and button-press timings */
#define JACK_SETTLE_TIME 100 /* milli seconds */
#define JACK_DETECT_COUNT 5
#define JACK_DETECT_MAXCOUNT 20 /* Aprox. 2 seconds worth of tries */
#define JACK_UNPLUG_TIME 80 /* milli seconds */
#define BP_POLL_TIME 10 /* milli seconds */
#define BP_POLL_MAXCOUNT 200 /* assume something is wrong after this */
#define BP_THRESHOLD 3
static void rt5640_start_button_press_work(struct snd_soc_component *component)
{
struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
rt5640->poll_count = 0;
rt5640->press_count = 0;
rt5640->release_count = 0;
rt5640->pressed = false;
rt5640->press_reported = false;
rt5640_clear_micbias1_ovcd(component);
schedule_delayed_work(&rt5640->bp_work, msecs_to_jiffies(BP_POLL_TIME));
}
static void rt5640_button_press_work(struct work_struct *work)
{
struct rt5640_priv *rt5640 =
container_of(work, struct rt5640_priv, bp_work.work);
struct snd_soc_component *component = rt5640->component;
/* Check the jack was not removed underneath us */
if (!rt5640_jack_inserted(component))
return;
if (rt5640_micbias1_ovcd(component)) {
rt5640->release_count = 0;
rt5640->press_count++;
/* Remember till after JACK_UNPLUG_TIME wait */
if (rt5640->press_count >= BP_THRESHOLD)
rt5640->pressed = true;
rt5640_clear_micbias1_ovcd(component);
} else {
rt5640->press_count = 0;
rt5640->release_count++;
}
/*
* The pins get temporarily shorted on jack unplug, so we poll for
* at least JACK_UNPLUG_TIME milli-seconds before reporting a press.
*/
rt5640->poll_count++;
if (rt5640->poll_count < (JACK_UNPLUG_TIME / BP_POLL_TIME)) {
schedule_delayed_work(&rt5640->bp_work,
msecs_to_jiffies(BP_POLL_TIME));
return;
}
if (rt5640->pressed && !rt5640->press_reported) {
dev_dbg(component->dev, "headset button press\n");
snd_soc_jack_report(rt5640->jack, SND_JACK_BTN_0,
SND_JACK_BTN_0);
rt5640->press_reported = true;
}
if (rt5640->release_count >= BP_THRESHOLD) {
if (rt5640->press_reported) {
dev_dbg(component->dev, "headset button release\n");
snd_soc_jack_report(rt5640->jack, 0, SND_JACK_BTN_0);
}
/* Re-enable OVCD IRQ to detect next press */
rt5640_enable_micbias1_ovcd_irq(component);
return; /* Stop polling */
}
schedule_delayed_work(&rt5640->bp_work, msecs_to_jiffies(BP_POLL_TIME));
}
int rt5640_detect_headset(struct snd_soc_component *component, struct gpio_desc *hp_det_gpio)
{
int i, headset_count = 0, headphone_count = 0;
/*
* We get the insertion event before the jack is fully inserted at which
* point the second ring on a TRRS connector may short the 2nd ring and
* sleeve contacts, also the overcurrent detection is not entirely
* reliable. So we try several times with a wait in between until we
* detect the same type JACK_DETECT_COUNT times in a row.
*/
for (i = 0; i < JACK_DETECT_MAXCOUNT; i++) {
/* Clear any previous over-current status flag */
rt5640_clear_micbias1_ovcd(component);
msleep(JACK_SETTLE_TIME);
/* Check the jack is still connected before checking ovcd */
if (hp_det_gpio) {
if (gpiod_get_value_cansleep(hp_det_gpio))
return 0;
} else {
if (!rt5640_jack_inserted(component))
return 0;
}
if (rt5640_micbias1_ovcd(component)) {
/*
* Over current detected, there is a short between the
* 2nd ring contact and the ground, so a TRS connector
* without a mic contact and thus plain headphones.
*/
dev_dbg(component->dev, "jack mic-gnd shorted\n");
headset_count = 0;
headphone_count++;
if (headphone_count == JACK_DETECT_COUNT)
return SND_JACK_HEADPHONE;
} else {
dev_dbg(component->dev, "jack mic-gnd open\n");
headphone_count = 0;
headset_count++;
if (headset_count == JACK_DETECT_COUNT)
return SND_JACK_HEADSET;
}
}
dev_err(component->dev, "Error detecting headset vs headphones, bad contact?, assuming headphones\n");
return SND_JACK_HEADPHONE;
}
EXPORT_SYMBOL_GPL(rt5640_detect_headset);
static void rt5640_jack_work(struct work_struct *work)
{
struct rt5640_priv *rt5640 =
container_of(work, struct rt5640_priv, jack_work.work);
struct snd_soc_component *component = rt5640->component;
int status;
if (rt5640->jd_src == RT5640_JD_SRC_HDA_HEADER) {
int val, jack_type = 0, hda_mic_plugged, hda_hp_plugged;
/* mic jack */
val = snd_soc_component_read(component, RT5640_INT_IRQ_ST);
hda_mic_plugged = !(val & RT5640_JD_STATUS);
dev_dbg(component->dev, "mic jack status %d\n",
hda_mic_plugged);
snd_soc_component_update_bits(component, RT5640_IRQ_CTRL1,
RT5640_JD_P_MASK, !hda_mic_plugged << RT5640_JD_P_SFT);
if (hda_mic_plugged)
jack_type |= SND_JACK_MICROPHONE;
/* headphone jack */
val = snd_soc_component_read(component, RT5640_DUMMY2);
hda_hp_plugged = !(val & (0x1 << 11));
dev_dbg(component->dev, "headphone jack status %d\n",
hda_hp_plugged);
snd_soc_component_update_bits(component, RT5640_DUMMY2,
(0x1 << 10), !hda_hp_plugged << 10);
if (hda_hp_plugged)
jack_type |= SND_JACK_HEADPHONE;
snd_soc_jack_report(rt5640->jack, jack_type, SND_JACK_HEADSET);
return;
}
if (!rt5640_jack_inserted(component)) {
/* Jack removed, or spurious IRQ? */
if (rt5640->jack->status & SND_JACK_HEADPHONE) {
if (rt5640->jack->status & SND_JACK_MICROPHONE) {
cancel_delayed_work_sync(&rt5640->bp_work);
rt5640_disable_micbias1_ovcd_irq(component);
rt5640_disable_micbias1_for_ovcd(component);
}
snd_soc_jack_report(rt5640->jack, 0,
SND_JACK_HEADSET | SND_JACK_BTN_0);
dev_dbg(component->dev, "jack unplugged\n");
}
} else if (!(rt5640->jack->status & SND_JACK_HEADPHONE)) {
/* Jack inserted */
WARN_ON(rt5640->ovcd_irq_enabled);
rt5640_enable_micbias1_for_ovcd(component);
status = rt5640_detect_headset(component, NULL);
if (status == SND_JACK_HEADSET) {
/* Enable ovcd IRQ for button press detect. */
rt5640_enable_micbias1_ovcd_irq(component);
} else {
/* No more need for overcurrent detect. */
rt5640_disable_micbias1_for_ovcd(component);
}
dev_dbg(component->dev, "detect status %#02x\n", status);
snd_soc_jack_report(rt5640->jack, status, SND_JACK_HEADSET);
} else if (rt5640->ovcd_irq_enabled && rt5640_micbias1_ovcd(component)) {
dev_dbg(component->dev, "OVCD IRQ\n");
/*
* The ovcd IRQ keeps firing while the button is pressed, so
* we disable it and start polling the button until released.
*
* The disable will make the IRQ pin 0 again and since we get
* IRQs on both edges (so as to detect both jack plugin and
* unplug) this means we will immediately get another IRQ.
* The ovcd_irq_enabled check above makes the 2ND IRQ a NOP.
*/
rt5640_disable_micbias1_ovcd_irq(component);
rt5640_start_button_press_work(component);
/*
* If the jack-detect IRQ flag goes high (unplug) after our
* above rt5640_jack_inserted() check and before we have
* disabled the OVCD IRQ, the IRQ pin will stay high and as
* we react to edges, we miss the unplug event -> recheck.
*/
queue_delayed_work(system_long_wq, &rt5640->jack_work, 0);
}
}
static irqreturn_t rt5640_irq(int irq, void *data)
{
struct rt5640_priv *rt5640 = data;
int delay = 0;
if (rt5640->jd_src == RT5640_JD_SRC_HDA_HEADER)
delay = 100;
if (rt5640->jack)
mod_delayed_work(system_long_wq, &rt5640->jack_work, delay);
return IRQ_HANDLED;
}
static irqreturn_t rt5640_jd_gpio_irq(int irq, void *data)
{
struct rt5640_priv *rt5640 = data;
queue_delayed_work(system_long_wq, &rt5640->jack_work,
msecs_to_jiffies(JACK_SETTLE_TIME));
return IRQ_HANDLED;
}
static void rt5640_cancel_work(void *data)
{
struct rt5640_priv *rt5640 = data;
cancel_delayed_work_sync(&rt5640->jack_work);
cancel_delayed_work_sync(&rt5640->bp_work);
}
void rt5640_set_ovcd_params(struct snd_soc_component *component)
{
struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
snd_soc_component_write(component, RT5640_PR_BASE + RT5640_BIAS_CUR4,
0xa800 | rt5640->ovcd_sf);
snd_soc_component_update_bits(component, RT5640_MICBIAS,
RT5640_MIC1_OVTH_MASK | RT5640_MIC1_OVCD_MASK,
rt5640->ovcd_th | RT5640_MIC1_OVCD_EN);
/*
* The over-current-detect is only reliable in detecting the absence
* of over-current, when the mic-contact in the jack is short-circuited,
* the hardware periodically retries if it can apply the bias-current
* leading to the ovcd status flip-flopping 1-0-1 with it being 0 about
* 10% of the time, as we poll the ovcd status bit we might hit that
* 10%, so we enable sticky mode and when checking OVCD we clear the
* status, msleep() a bit and then check to get a reliable reading.
*/
snd_soc_component_update_bits(component, RT5640_IRQ_CTRL2,
RT5640_MB1_OC_STKY_MASK, RT5640_MB1_OC_STKY_EN);
}
EXPORT_SYMBOL_GPL(rt5640_set_ovcd_params);
static void rt5640_disable_jack_detect(struct snd_soc_component *component)
{
struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
/*
* soc_remove_component() force-disables jack and thus rt5640->jack
* could be NULL at the time of driver's module unloading.
*/
if (!rt5640->jack)
return;
if (rt5640->jd_gpio_irq_requested)
free_irq(rt5640->jd_gpio_irq, rt5640);
if (rt5640->irq_requested)
free_irq(rt5640->irq, rt5640);
rt5640_cancel_work(rt5640);
if (rt5640->jack->status & SND_JACK_MICROPHONE) {
rt5640_disable_micbias1_ovcd_irq(component);
rt5640_disable_micbias1_for_ovcd(component);
snd_soc_jack_report(rt5640->jack, 0, SND_JACK_BTN_0);
}
rt5640->jd_gpio_irq_requested = false;
rt5640->irq_requested = false;
rt5640->jd_gpio = NULL;
rt5640->jack = NULL;
}
static void rt5640_enable_jack_detect(struct snd_soc_component *component,
struct snd_soc_jack *jack,
struct rt5640_set_jack_data *jack_data)
{
struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
int ret;
/* Select JD-source */
snd_soc_component_update_bits(component, RT5640_JD_CTRL,
RT5640_JD_MASK, rt5640->jd_src << RT5640_JD_SFT);
/* Selecting GPIO01 as an interrupt */
snd_soc_component_update_bits(component, RT5640_GPIO_CTRL1,
RT5640_GP1_PIN_MASK, RT5640_GP1_PIN_IRQ);
/* Set GPIO1 output */
snd_soc_component_update_bits(component, RT5640_GPIO_CTRL3,
RT5640_GP1_PF_MASK, RT5640_GP1_PF_OUT);
snd_soc_component_write(component, RT5640_DUMMY1, 0x3f41);
rt5640_set_ovcd_params(component);
/*
* All IRQs get or-ed together, so we need the jack IRQ to report 0
* when a jack is inserted so that the OVCD IRQ then toggles the IRQ
* pin 0/1 instead of it being stuck to 1. So we invert the JD polarity
* on systems where the hardware does not already do this.
*/
if (rt5640->jd_inverted) {
if (rt5640->jd_src == RT5640_JD_SRC_JD1_IN4P)
snd_soc_component_write(component, RT5640_IRQ_CTRL1,
RT5640_IRQ_JD_NOR);
else if (rt5640->jd_src == RT5640_JD_SRC_JD2_IN4N)
snd_soc_component_update_bits(component, RT5640_DUMMY2,
RT5640_IRQ_JD2_MASK | RT5640_JD2_MASK,
RT5640_IRQ_JD2_NOR | RT5640_JD2_EN);
} else {
if (rt5640->jd_src == RT5640_JD_SRC_JD1_IN4P)
snd_soc_component_write(component, RT5640_IRQ_CTRL1,
RT5640_IRQ_JD_NOR | RT5640_JD_P_INV);
else if (rt5640->jd_src == RT5640_JD_SRC_JD2_IN4N)
snd_soc_component_update_bits(component, RT5640_DUMMY2,
RT5640_IRQ_JD2_MASK | RT5640_JD2_P_MASK |
RT5640_JD2_MASK,
RT5640_IRQ_JD2_NOR | RT5640_JD2_P_INV |
RT5640_JD2_EN);
}
rt5640->jack = jack;
if (rt5640->jack->status & SND_JACK_MICROPHONE) {
rt5640_enable_micbias1_for_ovcd(component);
rt5640_enable_micbias1_ovcd_irq(component);
}
if (jack_data && jack_data->codec_irq_override)
rt5640->irq = jack_data->codec_irq_override;
if (jack_data && jack_data->jd_gpio) {
rt5640->jd_gpio = jack_data->jd_gpio;
rt5640->jd_gpio_irq = gpiod_to_irq(rt5640->jd_gpio);
ret = request_irq(rt5640->jd_gpio_irq, rt5640_jd_gpio_irq,
IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
"rt5640-jd-gpio", rt5640);
if (ret) {
dev_warn(component->dev, "Failed to request jd GPIO IRQ %d: %d\n",
rt5640->jd_gpio_irq, ret);
rt5640_disable_jack_detect(component);
return;
}
rt5640->jd_gpio_irq_requested = true;
}
if (jack_data && jack_data->use_platform_clock)
rt5640->use_platform_clock = jack_data->use_platform_clock;
ret = request_irq(rt5640->irq, rt5640_irq,
IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
"rt5640", rt5640);
if (ret) {
dev_warn(component->dev, "Failed to request IRQ %d: %d\n", rt5640->irq, ret);
rt5640_disable_jack_detect(component);
return;
}
rt5640->irq_requested = true;
/* sync initial jack state */
queue_delayed_work(system_long_wq, &rt5640->jack_work, 0);
}
static const struct snd_soc_dapm_route rt5640_hda_jack_dapm_routes[] = {
{"IN1P", NULL, "MICBIAS1"},
{"IN2P", NULL, "MICBIAS1"},
{"IN3P", NULL, "MICBIAS1"},
};
static void rt5640_enable_hda_jack_detect(
struct snd_soc_component *component, struct snd_soc_jack *jack)
{
struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm =
snd_soc_component_get_dapm(component);
int ret;
/* Select JD1 for Mic */
snd_soc_component_update_bits(component, RT5640_JD_CTRL,
RT5640_JD_MASK, RT5640_JD_JD1_IN4P);
snd_soc_component_write(component, RT5640_IRQ_CTRL1, RT5640_IRQ_JD_NOR);
/* Select JD2 for Headphone */
snd_soc_component_update_bits(component, RT5640_DUMMY2, 0x1100, 0x1100);
/* Selecting GPIO01 as an interrupt */
snd_soc_component_update_bits(component, RT5640_GPIO_CTRL1,
RT5640_GP1_PIN_MASK, RT5640_GP1_PIN_IRQ);
/* Set GPIO1 output */
snd_soc_component_update_bits(component, RT5640_GPIO_CTRL3,
RT5640_GP1_PF_MASK, RT5640_GP1_PF_OUT);
snd_soc_component_update_bits(component, RT5640_DUMMY1, 0x400, 0x0);
snd_soc_component_update_bits(component, RT5640_PWR_ANLG1,
RT5640_PWR_VREF2 | RT5640_PWR_MB | RT5640_PWR_BG,
RT5640_PWR_VREF2 | RT5640_PWR_MB | RT5640_PWR_BG);
usleep_range(10000, 15000);
snd_soc_component_update_bits(component, RT5640_PWR_ANLG1,
RT5640_PWR_FV2, RT5640_PWR_FV2);
rt5640->jack = jack;
ret = request_irq(rt5640->irq, rt5640_irq,
IRQF_TRIGGER_RISING | IRQF_ONESHOT, "rt5640", rt5640);
if (ret) {
dev_warn(component->dev, "Failed to request IRQ %d: %d\n", rt5640->irq, ret);
rt5640->jack = NULL;
return;
}
rt5640->irq_requested = true;
/* sync initial jack state */
queue_delayed_work(system_long_wq, &rt5640->jack_work, 0);
snd_soc_dapm_add_routes(dapm, rt5640_hda_jack_dapm_routes,
ARRAY_SIZE(rt5640_hda_jack_dapm_routes));
}
static int rt5640_set_jack(struct snd_soc_component *component,
struct snd_soc_jack *jack, void *data)
{
struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
if (jack) {
if (rt5640->jd_src == RT5640_JD_SRC_HDA_HEADER)
rt5640_enable_hda_jack_detect(component, jack);
else
rt5640_enable_jack_detect(component, jack, data);
} else {
rt5640_disable_jack_detect(component);
}
return 0;
}
static int rt5640_probe(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
u32 dmic1_data_pin = 0;
u32 dmic2_data_pin = 0;
bool dmic_en = false;
u32 val;
/* Check if MCLK provided */
rt5640->mclk = devm_clk_get(component->dev, "mclk");
if (PTR_ERR(rt5640->mclk) == -EPROBE_DEFER)
return -EPROBE_DEFER;
rt5640->component = component;
snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
snd_soc_component_update_bits(component, RT5640_DUMMY1, 0x0301, 0x0301);
snd_soc_component_update_bits(component, RT5640_MICBIAS, 0x0030, 0x0030);
snd_soc_component_update_bits(component, RT5640_DSP_PATH2, 0xfc00, 0x0c00);
switch (snd_soc_component_read(component, RT5640_RESET) & RT5640_ID_MASK) {
case RT5640_ID_5640:
case RT5640_ID_5642:
snd_soc_add_component_controls(component,
rt5640_specific_snd_controls,
ARRAY_SIZE(rt5640_specific_snd_controls));
snd_soc_dapm_new_controls(dapm,
rt5640_specific_dapm_widgets,
ARRAY_SIZE(rt5640_specific_dapm_widgets));
snd_soc_dapm_add_routes(dapm,
rt5640_specific_dapm_routes,
ARRAY_SIZE(rt5640_specific_dapm_routes));
break;
case RT5640_ID_5639:
snd_soc_dapm_new_controls(dapm,
rt5639_specific_dapm_widgets,
ARRAY_SIZE(rt5639_specific_dapm_widgets));
snd_soc_dapm_add_routes(dapm,
rt5639_specific_dapm_routes,
ARRAY_SIZE(rt5639_specific_dapm_routes));
break;
default:
dev_err(component->dev,
"The driver is for RT5639 RT5640 or RT5642 only\n");
return -ENODEV;
}
/*
* Note on some platforms the platform code may need to add device-props
* rather then relying only on properties set by the firmware.
* Therefor the property parsing MUST be done here, rather then from
* rt5640_i2c_probe(), so that the platform-code can attach extra
* properties before calling snd_soc_register_card().
*/
if (device_property_read_bool(component->dev, "realtek,in1-differential"))
snd_soc_component_update_bits(component, RT5640_IN1_IN2,
RT5640_IN_DF1, RT5640_IN_DF1);
if (device_property_read_bool(component->dev, "realtek,in2-differential"))
snd_soc_component_update_bits(component, RT5640_IN3_IN4,
RT5640_IN_DF2, RT5640_IN_DF2);
if (device_property_read_bool(component->dev, "realtek,in3-differential"))
snd_soc_component_update_bits(component, RT5640_IN1_IN2,
RT5640_IN_DF2, RT5640_IN_DF2);
if (device_property_read_bool(component->dev, "realtek,lout-differential"))
snd_soc_component_update_bits(component, RT5640_DUMMY1,
RT5640_EN_LOUT_DF, RT5640_EN_LOUT_DF);
if (device_property_read_u32(component->dev, "realtek,dmic1-data-pin",
&val) == 0 && val) {
dmic1_data_pin = val - 1;
dmic_en = true;
}
if (device_property_read_u32(component->dev, "realtek,dmic2-data-pin",
&val) == 0 && val) {
dmic2_data_pin = val - 1;
dmic_en = true;
}
if (dmic_en)
rt5640_dmic_enable(component, dmic1_data_pin, dmic2_data_pin);
if (device_property_read_u32(component->dev,
"realtek,jack-detect-source", &val) == 0) {
if (val <= RT5640_JD_SRC_HDA_HEADER)
rt5640->jd_src = val;
else
dev_warn(component->dev, "Warning: Invalid jack-detect-source value: %d, leaving jack-detect disabled\n",
val);
}
if (!device_property_read_bool(component->dev, "realtek,jack-detect-not-inverted"))
rt5640->jd_inverted = true;
/*
* Testing on various boards has shown that good defaults for the OVCD
* threshold and scale-factor are 2000µA and 0.75. For an effective
* limit of 1500µA, this seems to be more reliable then 1500µA and 1.0.
*/
rt5640->ovcd_th = RT5640_MIC1_OVTH_2000UA;
rt5640->ovcd_sf = RT5640_MIC_OVCD_SF_0P75;
if (device_property_read_u32(component->dev,
"realtek,over-current-threshold-microamp", &val) == 0) {
switch (val) {
case 600:
rt5640->ovcd_th = RT5640_MIC1_OVTH_600UA;
break;
case 1500:
rt5640->ovcd_th = RT5640_MIC1_OVTH_1500UA;
break;
case 2000:
rt5640->ovcd_th = RT5640_MIC1_OVTH_2000UA;
break;
default:
dev_warn(component->dev, "Warning: Invalid over-current-threshold-microamp value: %d, defaulting to 2000uA\n",
val);
}
}
if (device_property_read_u32(component->dev,
"realtek,over-current-scale-factor", &val) == 0) {
if (val <= RT5640_OVCD_SF_1P5)
rt5640->ovcd_sf = val << RT5640_MIC_OVCD_SF_SFT;
else
dev_warn(component->dev, "Warning: Invalid over-current-scale-factor value: %d, defaulting to 0.75\n",
val);
}
return 0;
}
static void rt5640_remove(struct snd_soc_component *component)
{
rt5640_reset(component);
}
#ifdef CONFIG_PM
static int rt5640_suspend(struct snd_soc_component *component)
{
struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
if (rt5640->jack) {
/* disable jack interrupts during system suspend */
disable_irq(rt5640->irq);
rt5640_cancel_work(rt5640);
}
snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
rt5640_reset(component);
regcache_cache_only(rt5640->regmap, true);
regcache_mark_dirty(rt5640->regmap);
if (rt5640->ldo1_en)
gpiod_set_value_cansleep(rt5640->ldo1_en, 0);
return 0;
}
static int rt5640_resume(struct snd_soc_component *component)
{
struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
if (rt5640->ldo1_en) {
gpiod_set_value_cansleep(rt5640->ldo1_en, 1);
msleep(400);
}
regcache_cache_only(rt5640->regmap, false);
regcache_sync(rt5640->regmap);
if (rt5640->jack) {
if (rt5640->jd_src == RT5640_JD_SRC_HDA_HEADER) {
snd_soc_component_update_bits(component,
RT5640_DUMMY2, 0x1100, 0x1100);
} else {
if (rt5640->jd_inverted) {
if (rt5640->jd_src == RT5640_JD_SRC_JD2_IN4N)
snd_soc_component_update_bits(
component, RT5640_DUMMY2,
RT5640_IRQ_JD2_MASK |
RT5640_JD2_MASK,
RT5640_IRQ_JD2_NOR |
RT5640_JD2_EN);
} else {
if (rt5640->jd_src == RT5640_JD_SRC_JD2_IN4N)
snd_soc_component_update_bits(
component, RT5640_DUMMY2,
RT5640_IRQ_JD2_MASK |
RT5640_JD2_P_MASK |
RT5640_JD2_MASK,
RT5640_IRQ_JD2_NOR |
RT5640_JD2_P_INV |
RT5640_JD2_EN);
}
}
enable_irq(rt5640->irq);
queue_delayed_work(system_long_wq, &rt5640->jack_work, 0);
}
return 0;
}
#else
#define rt5640_suspend NULL
#define rt5640_resume NULL
#endif
#define RT5640_STEREO_RATES SNDRV_PCM_RATE_8000_96000
#define RT5640_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
static const struct snd_soc_dai_ops rt5640_aif_dai_ops = {
.hw_params = rt5640_hw_params,
.set_fmt = rt5640_set_dai_fmt,
.set_sysclk = rt5640_set_dai_sysclk,
.set_pll = rt5640_set_dai_pll,
};
static struct snd_soc_dai_driver rt5640_dai[] = {
{
.name = "rt5640-aif1",
.id = RT5640_AIF1,
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT5640_STEREO_RATES,
.formats = RT5640_FORMATS,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT5640_STEREO_RATES,
.formats = RT5640_FORMATS,
},
.ops = &rt5640_aif_dai_ops,
},
{
.name = "rt5640-aif2",
.id = RT5640_AIF2,
.playback = {
.stream_name = "AIF2 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT5640_STEREO_RATES,
.formats = RT5640_FORMATS,
},
.capture = {
.stream_name = "AIF2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT5640_STEREO_RATES,
.formats = RT5640_FORMATS,
},
.ops = &rt5640_aif_dai_ops,
},
};
static const struct snd_soc_component_driver soc_component_dev_rt5640 = {
.probe = rt5640_probe,
.remove = rt5640_remove,
.suspend = rt5640_suspend,
.resume = rt5640_resume,
.set_bias_level = rt5640_set_bias_level,
.set_jack = rt5640_set_jack,
.controls = rt5640_snd_controls,
.num_controls = ARRAY_SIZE(rt5640_snd_controls),
.dapm_widgets = rt5640_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt5640_dapm_widgets),
.dapm_routes = rt5640_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(rt5640_dapm_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config rt5640_regmap = {
.reg_bits = 8,
.val_bits = 16,
.use_single_read = true,
.use_single_write = true,
.max_register = RT5640_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5640_ranges) *
RT5640_PR_SPACING),
.volatile_reg = rt5640_volatile_register,
.readable_reg = rt5640_readable_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = rt5640_reg,
.num_reg_defaults = ARRAY_SIZE(rt5640_reg),
.ranges = rt5640_ranges,
.num_ranges = ARRAY_SIZE(rt5640_ranges),
};
static const struct i2c_device_id rt5640_i2c_id[] = {
{ "rt5640", 0 },
{ "rt5639", 0 },
{ "rt5642", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, rt5640_i2c_id);
#if defined(CONFIG_OF)
static const struct of_device_id rt5640_of_match[] = {
{ .compatible = "realtek,rt5639", },
{ .compatible = "realtek,rt5640", },
{},
};
MODULE_DEVICE_TABLE(of, rt5640_of_match);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id rt5640_acpi_match[] = {
{ "INT33CA", 0 },
{ "10EC3276", 0 },
{ "10EC5640", 0 },
{ "10EC5642", 0 },
{ "INTCCFFD", 0 },
{ },
};
MODULE_DEVICE_TABLE(acpi, rt5640_acpi_match);
#endif
static int rt5640_i2c_probe(struct i2c_client *i2c)
{
struct rt5640_priv *rt5640;
int ret;
unsigned int val;
rt5640 = devm_kzalloc(&i2c->dev,
sizeof(struct rt5640_priv),
GFP_KERNEL);
if (NULL == rt5640)
return -ENOMEM;
i2c_set_clientdata(i2c, rt5640);
rt5640->ldo1_en = devm_gpiod_get_optional(&i2c->dev,
"realtek,ldo1-en",
GPIOD_OUT_HIGH);
if (IS_ERR(rt5640->ldo1_en))
return PTR_ERR(rt5640->ldo1_en);
if (rt5640->ldo1_en) {
gpiod_set_consumer_name(rt5640->ldo1_en, "RT5640 LDO1_EN");
msleep(400);
}
rt5640->regmap = devm_regmap_init_i2c(i2c, &rt5640_regmap);
if (IS_ERR(rt5640->regmap)) {
ret = PTR_ERR(rt5640->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
regmap_read(rt5640->regmap, RT5640_VENDOR_ID2, &val);
if (val != RT5640_DEVICE_ID) {
dev_err(&i2c->dev,
"Device with ID register %#x is not rt5640/39\n", val);
return -ENODEV;
}
regmap_write(rt5640->regmap, RT5640_RESET, 0);
ret = regmap_register_patch(rt5640->regmap, init_list,
ARRAY_SIZE(init_list));
if (ret != 0)
dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
regmap_update_bits(rt5640->regmap, RT5640_DUMMY1,
RT5640_MCLK_DET, RT5640_MCLK_DET);
rt5640->hp_mute = true;
rt5640->irq = i2c->irq;
INIT_DELAYED_WORK(&rt5640->bp_work, rt5640_button_press_work);
INIT_DELAYED_WORK(&rt5640->jack_work, rt5640_jack_work);
/* Make sure work is stopped on probe-error / remove */
ret = devm_add_action_or_reset(&i2c->dev, rt5640_cancel_work, rt5640);
if (ret)
return ret;
return devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_rt5640,
rt5640_dai, ARRAY_SIZE(rt5640_dai));
}
static struct i2c_driver rt5640_i2c_driver = {
.driver = {
.name = "rt5640",
.acpi_match_table = ACPI_PTR(rt5640_acpi_match),
.of_match_table = of_match_ptr(rt5640_of_match),
},
.probe = rt5640_i2c_probe,
.id_table = rt5640_i2c_id,
};
module_i2c_driver(rt5640_i2c_driver);
MODULE_DESCRIPTION("ASoC RT5640/RT5639 driver");
MODULE_AUTHOR("Johnny Hsu <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/rt5640.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* wm8971.c -- WM8971 ALSA SoC Audio driver
*
* Copyright 2005 Lab126, Inc.
*
* Author: Kenneth Kiraly <[email protected]>
*
* Based on wm8753.c by Liam Girdwood
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include "wm8971.h"
#define WM8971_REG_COUNT 43
/* codec private data */
struct wm8971_priv {
unsigned int sysclk;
struct delayed_work charge_work;
struct regmap *regmap;
};
/*
* wm8971 register cache
* We can't read the WM8971 register space when we
* are using 2 wire for device control, so we cache them instead.
*/
static const struct reg_default wm8971_reg_defaults[] = {
{ 0, 0x0097 },
{ 1, 0x0097 },
{ 2, 0x0079 },
{ 3, 0x0079 },
{ 4, 0x0000 },
{ 5, 0x0008 },
{ 6, 0x0000 },
{ 7, 0x000a },
{ 8, 0x0000 },
{ 9, 0x0000 },
{ 10, 0x00ff },
{ 11, 0x00ff },
{ 12, 0x000f },
{ 13, 0x000f },
{ 14, 0x0000 },
{ 15, 0x0000 },
{ 16, 0x0000 },
{ 17, 0x007b },
{ 18, 0x0000 },
{ 19, 0x0032 },
{ 20, 0x0000 },
{ 21, 0x00c3 },
{ 22, 0x00c3 },
{ 23, 0x00c0 },
{ 24, 0x0000 },
{ 25, 0x0000 },
{ 26, 0x0000 },
{ 27, 0x0000 },
{ 28, 0x0000 },
{ 29, 0x0000 },
{ 30, 0x0000 },
{ 31, 0x0000 },
{ 32, 0x0000 },
{ 33, 0x0000 },
{ 34, 0x0050 },
{ 35, 0x0050 },
{ 36, 0x0050 },
{ 37, 0x0050 },
{ 38, 0x0050 },
{ 39, 0x0050 },
{ 40, 0x0079 },
{ 41, 0x0079 },
{ 42, 0x0079 },
};
#define wm8971_reset(c) snd_soc_component_write(c, WM8971_RESET, 0)
/* WM8971 Controls */
static const char *wm8971_bass[] = { "Linear Control", "Adaptive Boost" };
static const char *wm8971_bass_filter[] = { "130Hz @ 48kHz",
"200Hz @ 48kHz" };
static const char *wm8971_treble[] = { "8kHz", "4kHz" };
static const char *wm8971_alc_func[] = { "Off", "Right", "Left", "Stereo" };
static const char *wm8971_ng_type[] = { "Constant PGA Gain",
"Mute ADC Output" };
static const char *wm8971_deemp[] = { "None", "32kHz", "44.1kHz", "48kHz" };
static const char *wm8971_mono_mux[] = {"Stereo", "Mono (Left)",
"Mono (Right)", "Digital Mono"};
static const char *wm8971_dac_phase[] = { "Non Inverted", "Inverted" };
static const char *wm8971_lline_mux[] = {"Line", "NC", "NC", "PGA",
"Differential"};
static const char *wm8971_rline_mux[] = {"Line", "Mic", "NC", "PGA",
"Differential"};
static const char *wm8971_lpga_sel[] = {"Line", "NC", "NC", "Differential"};
static const char *wm8971_rpga_sel[] = {"Line", "Mic", "NC", "Differential"};
static const char *wm8971_adcpol[] = {"Normal", "L Invert", "R Invert",
"L + R Invert"};
static const struct soc_enum wm8971_enum[] = {
SOC_ENUM_SINGLE(WM8971_BASS, 7, 2, wm8971_bass), /* 0 */
SOC_ENUM_SINGLE(WM8971_BASS, 6, 2, wm8971_bass_filter),
SOC_ENUM_SINGLE(WM8971_TREBLE, 6, 2, wm8971_treble),
SOC_ENUM_SINGLE(WM8971_ALC1, 7, 4, wm8971_alc_func),
SOC_ENUM_SINGLE(WM8971_NGATE, 1, 2, wm8971_ng_type), /* 4 */
SOC_ENUM_SINGLE(WM8971_ADCDAC, 1, 4, wm8971_deemp),
SOC_ENUM_SINGLE(WM8971_ADCTL1, 4, 4, wm8971_mono_mux),
SOC_ENUM_SINGLE(WM8971_ADCTL1, 1, 2, wm8971_dac_phase),
SOC_ENUM_SINGLE(WM8971_LOUTM1, 0, 5, wm8971_lline_mux), /* 8 */
SOC_ENUM_SINGLE(WM8971_ROUTM1, 0, 5, wm8971_rline_mux),
SOC_ENUM_SINGLE(WM8971_LADCIN, 6, 4, wm8971_lpga_sel),
SOC_ENUM_SINGLE(WM8971_RADCIN, 6, 4, wm8971_rpga_sel),
SOC_ENUM_SINGLE(WM8971_ADCDAC, 5, 4, wm8971_adcpol), /* 12 */
SOC_ENUM_SINGLE(WM8971_ADCIN, 6, 4, wm8971_mono_mux),
};
static const struct snd_kcontrol_new wm8971_snd_controls[] = {
SOC_DOUBLE_R("Capture Volume", WM8971_LINVOL, WM8971_RINVOL, 0, 63, 0),
SOC_DOUBLE_R("Capture ZC Switch", WM8971_LINVOL, WM8971_RINVOL,
6, 1, 0),
SOC_DOUBLE_R("Capture Switch", WM8971_LINVOL, WM8971_RINVOL, 7, 1, 1),
SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8971_LOUT1V,
WM8971_ROUT1V, 7, 1, 0),
SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8971_LOUT2V,
WM8971_ROUT2V, 7, 1, 0),
SOC_SINGLE("Mono Playback ZC Switch", WM8971_MOUTV, 7, 1, 0),
SOC_DOUBLE_R("PCM Volume", WM8971_LDAC, WM8971_RDAC, 0, 255, 0),
SOC_DOUBLE_R("Bypass Left Playback Volume", WM8971_LOUTM1,
WM8971_LOUTM2, 4, 7, 1),
SOC_DOUBLE_R("Bypass Right Playback Volume", WM8971_ROUTM1,
WM8971_ROUTM2, 4, 7, 1),
SOC_DOUBLE_R("Bypass Mono Playback Volume", WM8971_MOUTM1,
WM8971_MOUTM2, 4, 7, 1),
SOC_DOUBLE_R("Headphone Playback Volume", WM8971_LOUT1V,
WM8971_ROUT1V, 0, 127, 0),
SOC_DOUBLE_R("Speaker Playback Volume", WM8971_LOUT2V,
WM8971_ROUT2V, 0, 127, 0),
SOC_ENUM("Bass Boost", wm8971_enum[0]),
SOC_ENUM("Bass Filter", wm8971_enum[1]),
SOC_SINGLE("Bass Volume", WM8971_BASS, 0, 7, 1),
SOC_SINGLE("Treble Volume", WM8971_TREBLE, 0, 7, 0),
SOC_ENUM("Treble Cut-off", wm8971_enum[2]),
SOC_SINGLE("Capture Filter Switch", WM8971_ADCDAC, 0, 1, 1),
SOC_SINGLE("ALC Target Volume", WM8971_ALC1, 0, 7, 0),
SOC_SINGLE("ALC Max Volume", WM8971_ALC1, 4, 7, 0),
SOC_SINGLE("ALC Capture Target Volume", WM8971_ALC1, 0, 7, 0),
SOC_SINGLE("ALC Capture Max Volume", WM8971_ALC1, 4, 7, 0),
SOC_ENUM("ALC Capture Function", wm8971_enum[3]),
SOC_SINGLE("ALC Capture ZC Switch", WM8971_ALC2, 7, 1, 0),
SOC_SINGLE("ALC Capture Hold Time", WM8971_ALC2, 0, 15, 0),
SOC_SINGLE("ALC Capture Decay Time", WM8971_ALC3, 4, 15, 0),
SOC_SINGLE("ALC Capture Attack Time", WM8971_ALC3, 0, 15, 0),
SOC_SINGLE("ALC Capture NG Threshold", WM8971_NGATE, 3, 31, 0),
SOC_ENUM("ALC Capture NG Type", wm8971_enum[4]),
SOC_SINGLE("ALC Capture NG Switch", WM8971_NGATE, 0, 1, 0),
SOC_SINGLE("Capture 6dB Attenuate", WM8971_ADCDAC, 8, 1, 0),
SOC_SINGLE("Playback 6dB Attenuate", WM8971_ADCDAC, 7, 1, 0),
SOC_ENUM("Playback De-emphasis", wm8971_enum[5]),
SOC_ENUM("Playback Function", wm8971_enum[6]),
SOC_ENUM("Playback Phase", wm8971_enum[7]),
SOC_DOUBLE_R("Mic Boost", WM8971_LADCIN, WM8971_RADCIN, 4, 3, 0),
};
/*
* DAPM Controls
*/
/* Left Mixer */
static const struct snd_kcontrol_new wm8971_left_mixer_controls[] = {
SOC_DAPM_SINGLE("Playback Switch", WM8971_LOUTM1, 8, 1, 0),
SOC_DAPM_SINGLE("Left Bypass Switch", WM8971_LOUTM1, 7, 1, 0),
SOC_DAPM_SINGLE("Right Playback Switch", WM8971_LOUTM2, 8, 1, 0),
SOC_DAPM_SINGLE("Right Bypass Switch", WM8971_LOUTM2, 7, 1, 0),
};
/* Right Mixer */
static const struct snd_kcontrol_new wm8971_right_mixer_controls[] = {
SOC_DAPM_SINGLE("Left Playback Switch", WM8971_ROUTM1, 8, 1, 0),
SOC_DAPM_SINGLE("Left Bypass Switch", WM8971_ROUTM1, 7, 1, 0),
SOC_DAPM_SINGLE("Playback Switch", WM8971_ROUTM2, 8, 1, 0),
SOC_DAPM_SINGLE("Right Bypass Switch", WM8971_ROUTM2, 7, 1, 0),
};
/* Mono Mixer */
static const struct snd_kcontrol_new wm8971_mono_mixer_controls[] = {
SOC_DAPM_SINGLE("Left Playback Switch", WM8971_MOUTM1, 8, 1, 0),
SOC_DAPM_SINGLE("Left Bypass Switch", WM8971_MOUTM1, 7, 1, 0),
SOC_DAPM_SINGLE("Right Playback Switch", WM8971_MOUTM2, 8, 1, 0),
SOC_DAPM_SINGLE("Right Bypass Switch", WM8971_MOUTM2, 7, 1, 0),
};
/* Left Line Mux */
static const struct snd_kcontrol_new wm8971_left_line_controls =
SOC_DAPM_ENUM("Route", wm8971_enum[8]);
/* Right Line Mux */
static const struct snd_kcontrol_new wm8971_right_line_controls =
SOC_DAPM_ENUM("Route", wm8971_enum[9]);
/* Left PGA Mux */
static const struct snd_kcontrol_new wm8971_left_pga_controls =
SOC_DAPM_ENUM("Route", wm8971_enum[10]);
/* Right PGA Mux */
static const struct snd_kcontrol_new wm8971_right_pga_controls =
SOC_DAPM_ENUM("Route", wm8971_enum[11]);
/* Mono ADC Mux */
static const struct snd_kcontrol_new wm8971_monomux_controls =
SOC_DAPM_ENUM("Route", wm8971_enum[13]);
static const struct snd_soc_dapm_widget wm8971_dapm_widgets[] = {
SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
&wm8971_left_mixer_controls[0],
ARRAY_SIZE(wm8971_left_mixer_controls)),
SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
&wm8971_right_mixer_controls[0],
ARRAY_SIZE(wm8971_right_mixer_controls)),
SND_SOC_DAPM_MIXER("Mono Mixer", WM8971_PWR2, 2, 0,
&wm8971_mono_mixer_controls[0],
ARRAY_SIZE(wm8971_mono_mixer_controls)),
SND_SOC_DAPM_PGA("Right Out 2", WM8971_PWR2, 3, 0, NULL, 0),
SND_SOC_DAPM_PGA("Left Out 2", WM8971_PWR2, 4, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Out 1", WM8971_PWR2, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA("Left Out 1", WM8971_PWR2, 6, 0, NULL, 0),
SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8971_PWR2, 7, 0),
SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8971_PWR2, 8, 0),
SND_SOC_DAPM_PGA("Mono Out 1", WM8971_PWR2, 2, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Mic Bias", WM8971_PWR1, 1, 0, NULL, 0),
SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8971_PWR1, 2, 0),
SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8971_PWR1, 3, 0),
SND_SOC_DAPM_MUX("Left PGA Mux", WM8971_PWR1, 5, 0,
&wm8971_left_pga_controls),
SND_SOC_DAPM_MUX("Right PGA Mux", WM8971_PWR1, 4, 0,
&wm8971_right_pga_controls),
SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
&wm8971_left_line_controls),
SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
&wm8971_right_line_controls),
SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
&wm8971_monomux_controls),
SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
&wm8971_monomux_controls),
SND_SOC_DAPM_OUTPUT("LOUT1"),
SND_SOC_DAPM_OUTPUT("ROUT1"),
SND_SOC_DAPM_OUTPUT("LOUT2"),
SND_SOC_DAPM_OUTPUT("ROUT2"),
SND_SOC_DAPM_OUTPUT("MONO"),
SND_SOC_DAPM_INPUT("LINPUT1"),
SND_SOC_DAPM_INPUT("RINPUT1"),
SND_SOC_DAPM_INPUT("MIC"),
};
static const struct snd_soc_dapm_route wm8971_dapm_routes[] = {
/* left mixer */
{"Left Mixer", "Playback Switch", "Left DAC"},
{"Left Mixer", "Left Bypass Switch", "Left Line Mux"},
{"Left Mixer", "Right Playback Switch", "Right DAC"},
{"Left Mixer", "Right Bypass Switch", "Right Line Mux"},
/* right mixer */
{"Right Mixer", "Left Playback Switch", "Left DAC"},
{"Right Mixer", "Left Bypass Switch", "Left Line Mux"},
{"Right Mixer", "Playback Switch", "Right DAC"},
{"Right Mixer", "Right Bypass Switch", "Right Line Mux"},
/* left out 1 */
{"Left Out 1", NULL, "Left Mixer"},
{"LOUT1", NULL, "Left Out 1"},
/* left out 2 */
{"Left Out 2", NULL, "Left Mixer"},
{"LOUT2", NULL, "Left Out 2"},
/* right out 1 */
{"Right Out 1", NULL, "Right Mixer"},
{"ROUT1", NULL, "Right Out 1"},
/* right out 2 */
{"Right Out 2", NULL, "Right Mixer"},
{"ROUT2", NULL, "Right Out 2"},
/* mono mixer */
{"Mono Mixer", "Left Playback Switch", "Left DAC"},
{"Mono Mixer", "Left Bypass Switch", "Left Line Mux"},
{"Mono Mixer", "Right Playback Switch", "Right DAC"},
{"Mono Mixer", "Right Bypass Switch", "Right Line Mux"},
/* mono out */
{"Mono Out", NULL, "Mono Mixer"},
{"MONO1", NULL, "Mono Out"},
/* Left Line Mux */
{"Left Line Mux", "Line", "LINPUT1"},
{"Left Line Mux", "PGA", "Left PGA Mux"},
{"Left Line Mux", "Differential", "Differential Mux"},
/* Right Line Mux */
{"Right Line Mux", "Line", "RINPUT1"},
{"Right Line Mux", "Mic", "MIC"},
{"Right Line Mux", "PGA", "Right PGA Mux"},
{"Right Line Mux", "Differential", "Differential Mux"},
/* Left PGA Mux */
{"Left PGA Mux", "Line", "LINPUT1"},
{"Left PGA Mux", "Differential", "Differential Mux"},
/* Right PGA Mux */
{"Right PGA Mux", "Line", "RINPUT1"},
{"Right PGA Mux", "Differential", "Differential Mux"},
/* Differential Mux */
{"Differential Mux", "Line", "LINPUT1"},
{"Differential Mux", "Line", "RINPUT1"},
/* Left ADC Mux */
{"Left ADC Mux", "Stereo", "Left PGA Mux"},
{"Left ADC Mux", "Mono (Left)", "Left PGA Mux"},
{"Left ADC Mux", "Digital Mono", "Left PGA Mux"},
/* Right ADC Mux */
{"Right ADC Mux", "Stereo", "Right PGA Mux"},
{"Right ADC Mux", "Mono (Right)", "Right PGA Mux"},
{"Right ADC Mux", "Digital Mono", "Right PGA Mux"},
/* ADC */
{"Left ADC", NULL, "Left ADC Mux"},
{"Right ADC", NULL, "Right ADC Mux"},
};
struct _coeff_div {
u32 mclk;
u32 rate;
u16 fs;
u8 sr:5;
u8 usb:1;
};
/* codec hifi mclk clock divider coefficients */
static const struct _coeff_div coeff_div[] = {
/* 8k */
{12288000, 8000, 1536, 0x6, 0x0},
{11289600, 8000, 1408, 0x16, 0x0},
{18432000, 8000, 2304, 0x7, 0x0},
{16934400, 8000, 2112, 0x17, 0x0},
{12000000, 8000, 1500, 0x6, 0x1},
/* 11.025k */
{11289600, 11025, 1024, 0x18, 0x0},
{16934400, 11025, 1536, 0x19, 0x0},
{12000000, 11025, 1088, 0x19, 0x1},
/* 16k */
{12288000, 16000, 768, 0xa, 0x0},
{18432000, 16000, 1152, 0xb, 0x0},
{12000000, 16000, 750, 0xa, 0x1},
/* 22.05k */
{11289600, 22050, 512, 0x1a, 0x0},
{16934400, 22050, 768, 0x1b, 0x0},
{12000000, 22050, 544, 0x1b, 0x1},
/* 32k */
{12288000, 32000, 384, 0xc, 0x0},
{18432000, 32000, 576, 0xd, 0x0},
{12000000, 32000, 375, 0xa, 0x1},
/* 44.1k */
{11289600, 44100, 256, 0x10, 0x0},
{16934400, 44100, 384, 0x11, 0x0},
{12000000, 44100, 272, 0x11, 0x1},
/* 48k */
{12288000, 48000, 256, 0x0, 0x0},
{18432000, 48000, 384, 0x1, 0x0},
{12000000, 48000, 250, 0x0, 0x1},
/* 88.2k */
{11289600, 88200, 128, 0x1e, 0x0},
{16934400, 88200, 192, 0x1f, 0x0},
{12000000, 88200, 136, 0x1f, 0x1},
/* 96k */
{12288000, 96000, 128, 0xe, 0x0},
{18432000, 96000, 192, 0xf, 0x0},
{12000000, 96000, 125, 0xe, 0x1},
};
static int get_coeff(int mclk, int rate)
{
int i;
for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
return i;
}
return -EINVAL;
}
static int wm8971_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct wm8971_priv *wm8971 = snd_soc_component_get_drvdata(component);
switch (freq) {
case 11289600:
case 12000000:
case 12288000:
case 16934400:
case 18432000:
wm8971->sysclk = freq;
return 0;
}
return -EINVAL;
}
static int wm8971_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
u16 iface = 0;
/* set master/slave audio interface */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
iface = 0x0040;
break;
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface |= 0x0002;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
iface |= 0x0001;
break;
case SND_SOC_DAIFMT_DSP_A:
iface |= 0x0003;
break;
case SND_SOC_DAIFMT_DSP_B:
iface |= 0x0013;
break;
default:
return -EINVAL;
}
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
iface |= 0x0090;
break;
case SND_SOC_DAIFMT_IB_NF:
iface |= 0x0080;
break;
case SND_SOC_DAIFMT_NB_IF:
iface |= 0x0010;
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, WM8971_IFACE, iface);
return 0;
}
static int wm8971_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm8971_priv *wm8971 = snd_soc_component_get_drvdata(component);
u16 iface = snd_soc_component_read(component, WM8971_IFACE) & 0x1f3;
u16 srate = snd_soc_component_read(component, WM8971_SRATE) & 0x1c0;
int coeff = get_coeff(wm8971->sysclk, params_rate(params));
/* bit size */
switch (params_width(params)) {
case 16:
break;
case 20:
iface |= 0x0004;
break;
case 24:
iface |= 0x0008;
break;
case 32:
iface |= 0x000c;
break;
}
/* set iface & srate */
snd_soc_component_write(component, WM8971_IFACE, iface);
if (coeff >= 0)
snd_soc_component_write(component, WM8971_SRATE, srate |
(coeff_div[coeff].sr << 1) | coeff_div[coeff].usb);
return 0;
}
static int wm8971_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
u16 mute_reg = snd_soc_component_read(component, WM8971_ADCDAC) & 0xfff7;
if (mute)
snd_soc_component_write(component, WM8971_ADCDAC, mute_reg | 0x8);
else
snd_soc_component_write(component, WM8971_ADCDAC, mute_reg);
return 0;
}
static void wm8971_charge_work(struct work_struct *work)
{
struct wm8971_priv *wm8971 =
container_of(work, struct wm8971_priv, charge_work.work);
/* Set to 500k */
regmap_update_bits(wm8971->regmap, WM8971_PWR1, 0x0180, 0x0100);
}
static int wm8971_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct wm8971_priv *wm8971 = snd_soc_component_get_drvdata(component);
u16 pwr_reg = snd_soc_component_read(component, WM8971_PWR1) & 0xfe3e;
switch (level) {
case SND_SOC_BIAS_ON:
/* set vmid to 50k and unmute dac */
snd_soc_component_write(component, WM8971_PWR1, pwr_reg | 0x00c1);
break;
case SND_SOC_BIAS_PREPARE:
/* Wait until fully charged */
flush_delayed_work(&wm8971->charge_work);
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
snd_soc_component_cache_sync(component);
/* charge output caps - set vmid to 5k for quick power up */
snd_soc_component_write(component, WM8971_PWR1, pwr_reg | 0x01c0);
queue_delayed_work(system_power_efficient_wq,
&wm8971->charge_work, msecs_to_jiffies(1000));
} else {
/* mute dac and set vmid to 500k, enable VREF */
snd_soc_component_write(component, WM8971_PWR1, pwr_reg | 0x0140);
}
break;
case SND_SOC_BIAS_OFF:
cancel_delayed_work_sync(&wm8971->charge_work);
snd_soc_component_write(component, WM8971_PWR1, 0x0001);
break;
}
return 0;
}
#define WM8971_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
#define WM8971_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE)
static const struct snd_soc_dai_ops wm8971_dai_ops = {
.hw_params = wm8971_pcm_hw_params,
.mute_stream = wm8971_mute,
.set_fmt = wm8971_set_dai_fmt,
.set_sysclk = wm8971_set_dai_sysclk,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver wm8971_dai = {
.name = "wm8971-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM8971_RATES,
.formats = WM8971_FORMATS,},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM8971_RATES,
.formats = WM8971_FORMATS,},
.ops = &wm8971_dai_ops,
};
static int wm8971_probe(struct snd_soc_component *component)
{
struct wm8971_priv *wm8971 = snd_soc_component_get_drvdata(component);
INIT_DELAYED_WORK(&wm8971->charge_work, wm8971_charge_work);
wm8971_reset(component);
/* set the update bits */
snd_soc_component_update_bits(component, WM8971_LDAC, 0x0100, 0x0100);
snd_soc_component_update_bits(component, WM8971_RDAC, 0x0100, 0x0100);
snd_soc_component_update_bits(component, WM8971_LOUT1V, 0x0100, 0x0100);
snd_soc_component_update_bits(component, WM8971_ROUT1V, 0x0100, 0x0100);
snd_soc_component_update_bits(component, WM8971_LOUT2V, 0x0100, 0x0100);
snd_soc_component_update_bits(component, WM8971_ROUT2V, 0x0100, 0x0100);
snd_soc_component_update_bits(component, WM8971_LINVOL, 0x0100, 0x0100);
snd_soc_component_update_bits(component, WM8971_RINVOL, 0x0100, 0x0100);
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_wm8971 = {
.probe = wm8971_probe,
.set_bias_level = wm8971_set_bias_level,
.controls = wm8971_snd_controls,
.num_controls = ARRAY_SIZE(wm8971_snd_controls),
.dapm_widgets = wm8971_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8971_dapm_widgets),
.dapm_routes = wm8971_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(wm8971_dapm_routes),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config wm8971_regmap = {
.reg_bits = 7,
.val_bits = 9,
.max_register = WM8971_MOUTV,
.reg_defaults = wm8971_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8971_reg_defaults),
.cache_type = REGCACHE_MAPLE,
};
static int wm8971_i2c_probe(struct i2c_client *i2c)
{
struct wm8971_priv *wm8971;
wm8971 = devm_kzalloc(&i2c->dev, sizeof(struct wm8971_priv),
GFP_KERNEL);
if (wm8971 == NULL)
return -ENOMEM;
wm8971->regmap = devm_regmap_init_i2c(i2c, &wm8971_regmap);
if (IS_ERR(wm8971->regmap))
return PTR_ERR(wm8971->regmap);
i2c_set_clientdata(i2c, wm8971);
return devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_wm8971, &wm8971_dai, 1);
}
static const struct i2c_device_id wm8971_i2c_id[] = {
{ "wm8971", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8971_i2c_id);
static struct i2c_driver wm8971_i2c_driver = {
.driver = {
.name = "wm8971",
},
.probe = wm8971_i2c_probe,
.id_table = wm8971_i2c_id,
};
module_i2c_driver(wm8971_i2c_driver);
MODULE_DESCRIPTION("ASoC WM8971 driver");
MODULE_AUTHOR("Lab126");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8971.c |
// SPDX-License-Identifier: GPL-2.0-only
// Copyright (c) 2020, Maxim Integrated
#include <linux/acpi.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/sdw.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <linux/of.h>
#include <linux/soundwire/sdw.h>
#include <linux/soundwire/sdw_type.h>
#include <linux/soundwire/sdw_registers.h>
#include "max98373.h"
#include "max98373-sdw.h"
static const u32 max98373_sdw_cache_reg[] = {
MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK,
MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK,
MAX98373_R20B6_BDE_CUR_STATE_READBACK,
};
static struct reg_default max98373_reg[] = {
{MAX98373_R0040_SCP_INIT_STAT_1, 0x00},
{MAX98373_R0041_SCP_INIT_MASK_1, 0x00},
{MAX98373_R0042_SCP_INIT_STAT_2, 0x00},
{MAX98373_R0044_SCP_CTRL, 0x00},
{MAX98373_R0045_SCP_SYSTEM_CTRL, 0x00},
{MAX98373_R0046_SCP_DEV_NUMBER, 0x00},
{MAX98373_R0050_SCP_DEV_ID_0, 0x21},
{MAX98373_R0051_SCP_DEV_ID_1, 0x01},
{MAX98373_R0052_SCP_DEV_ID_2, 0x9F},
{MAX98373_R0053_SCP_DEV_ID_3, 0x87},
{MAX98373_R0054_SCP_DEV_ID_4, 0x08},
{MAX98373_R0055_SCP_DEV_ID_5, 0x00},
{MAX98373_R0060_SCP_FRAME_CTLR, 0x00},
{MAX98373_R0070_SCP_FRAME_CTLR, 0x00},
{MAX98373_R0100_DP1_INIT_STAT, 0x00},
{MAX98373_R0101_DP1_INIT_MASK, 0x00},
{MAX98373_R0102_DP1_PORT_CTRL, 0x00},
{MAX98373_R0103_DP1_BLOCK_CTRL_1, 0x00},
{MAX98373_R0104_DP1_PREPARE_STATUS, 0x00},
{MAX98373_R0105_DP1_PREPARE_CTRL, 0x00},
{MAX98373_R0120_DP1_CHANNEL_EN, 0x00},
{MAX98373_R0122_DP1_SAMPLE_CTRL1, 0x00},
{MAX98373_R0123_DP1_SAMPLE_CTRL2, 0x00},
{MAX98373_R0124_DP1_OFFSET_CTRL1, 0x00},
{MAX98373_R0125_DP1_OFFSET_CTRL2, 0x00},
{MAX98373_R0126_DP1_HCTRL, 0x00},
{MAX98373_R0127_DP1_BLOCK_CTRL3, 0x00},
{MAX98373_R0130_DP1_CHANNEL_EN, 0x00},
{MAX98373_R0132_DP1_SAMPLE_CTRL1, 0x00},
{MAX98373_R0133_DP1_SAMPLE_CTRL2, 0x00},
{MAX98373_R0134_DP1_OFFSET_CTRL1, 0x00},
{MAX98373_R0135_DP1_OFFSET_CTRL2, 0x00},
{MAX98373_R0136_DP1_HCTRL, 0x0136},
{MAX98373_R0137_DP1_BLOCK_CTRL3, 0x00},
{MAX98373_R0300_DP3_INIT_STAT, 0x00},
{MAX98373_R0301_DP3_INIT_MASK, 0x00},
{MAX98373_R0302_DP3_PORT_CTRL, 0x00},
{MAX98373_R0303_DP3_BLOCK_CTRL_1, 0x00},
{MAX98373_R0304_DP3_PREPARE_STATUS, 0x00},
{MAX98373_R0305_DP3_PREPARE_CTRL, 0x00},
{MAX98373_R0320_DP3_CHANNEL_EN, 0x00},
{MAX98373_R0322_DP3_SAMPLE_CTRL1, 0x00},
{MAX98373_R0323_DP3_SAMPLE_CTRL2, 0x00},
{MAX98373_R0324_DP3_OFFSET_CTRL1, 0x00},
{MAX98373_R0325_DP3_OFFSET_CTRL2, 0x00},
{MAX98373_R0326_DP3_HCTRL, 0x00},
{MAX98373_R0327_DP3_BLOCK_CTRL3, 0x00},
{MAX98373_R0330_DP3_CHANNEL_EN, 0x00},
{MAX98373_R0332_DP3_SAMPLE_CTRL1, 0x00},
{MAX98373_R0333_DP3_SAMPLE_CTRL2, 0x00},
{MAX98373_R0334_DP3_OFFSET_CTRL1, 0x00},
{MAX98373_R0335_DP3_OFFSET_CTRL2, 0x00},
{MAX98373_R0336_DP3_HCTRL, 0x00},
{MAX98373_R0337_DP3_BLOCK_CTRL3, 0x00},
{MAX98373_R2000_SW_RESET, 0x00},
{MAX98373_R2001_INT_RAW1, 0x00},
{MAX98373_R2002_INT_RAW2, 0x00},
{MAX98373_R2003_INT_RAW3, 0x00},
{MAX98373_R2004_INT_STATE1, 0x00},
{MAX98373_R2005_INT_STATE2, 0x00},
{MAX98373_R2006_INT_STATE3, 0x00},
{MAX98373_R2007_INT_FLAG1, 0x00},
{MAX98373_R2008_INT_FLAG2, 0x00},
{MAX98373_R2009_INT_FLAG3, 0x00},
{MAX98373_R200A_INT_EN1, 0x00},
{MAX98373_R200B_INT_EN2, 0x00},
{MAX98373_R200C_INT_EN3, 0x00},
{MAX98373_R200D_INT_FLAG_CLR1, 0x00},
{MAX98373_R200E_INT_FLAG_CLR2, 0x00},
{MAX98373_R200F_INT_FLAG_CLR3, 0x00},
{MAX98373_R2010_IRQ_CTRL, 0x00},
{MAX98373_R2014_THERM_WARN_THRESH, 0x10},
{MAX98373_R2015_THERM_SHDN_THRESH, 0x27},
{MAX98373_R2016_THERM_HYSTERESIS, 0x01},
{MAX98373_R2017_THERM_FOLDBACK_SET, 0xC0},
{MAX98373_R2018_THERM_FOLDBACK_EN, 0x00},
{MAX98373_R201E_PIN_DRIVE_STRENGTH, 0x55},
{MAX98373_R2020_PCM_TX_HIZ_EN_1, 0xFE},
{MAX98373_R2021_PCM_TX_HIZ_EN_2, 0xFF},
{MAX98373_R2022_PCM_TX_SRC_1, 0x00},
{MAX98373_R2023_PCM_TX_SRC_2, 0x00},
{MAX98373_R2024_PCM_DATA_FMT_CFG, 0xC0},
{MAX98373_R2025_AUDIO_IF_MODE, 0x00},
{MAX98373_R2026_PCM_CLOCK_RATIO, 0x04},
{MAX98373_R2027_PCM_SR_SETUP_1, 0x08},
{MAX98373_R2028_PCM_SR_SETUP_2, 0x88},
{MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 0x00},
{MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 0x00},
{MAX98373_R202B_PCM_RX_EN, 0x00},
{MAX98373_R202C_PCM_TX_EN, 0x00},
{MAX98373_R202E_ICC_RX_CH_EN_1, 0x00},
{MAX98373_R202F_ICC_RX_CH_EN_2, 0x00},
{MAX98373_R2030_ICC_TX_HIZ_EN_1, 0xFF},
{MAX98373_R2031_ICC_TX_HIZ_EN_2, 0xFF},
{MAX98373_R2032_ICC_LINK_EN_CFG, 0x30},
{MAX98373_R2034_ICC_TX_CNTL, 0x00},
{MAX98373_R2035_ICC_TX_EN, 0x00},
{MAX98373_R2036_SOUNDWIRE_CTRL, 0x05},
{MAX98373_R203D_AMP_DIG_VOL_CTRL, 0x00},
{MAX98373_R203E_AMP_PATH_GAIN, 0x08},
{MAX98373_R203F_AMP_DSP_CFG, 0x02},
{MAX98373_R2040_TONE_GEN_CFG, 0x00},
{MAX98373_R2041_AMP_CFG, 0x03},
{MAX98373_R2042_AMP_EDGE_RATE_CFG, 0x00},
{MAX98373_R2043_AMP_EN, 0x00},
{MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 0x04},
{MAX98373_R2047_IV_SENSE_ADC_EN, 0x00},
{MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0x00},
{MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 0x00},
{MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 0x00},
{MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0x00},
{MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0x00},
{MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0x00},
{MAX98373_R2090_BDE_LVL_HOLD, 0x00},
{MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0x00},
{MAX98373_R2092_BDE_CLIPPER_MODE, 0x00},
{MAX98373_R2097_BDE_L1_THRESH, 0x00},
{MAX98373_R2098_BDE_L2_THRESH, 0x00},
{MAX98373_R2099_BDE_L3_THRESH, 0x00},
{MAX98373_R209A_BDE_L4_THRESH, 0x00},
{MAX98373_R209B_BDE_THRESH_HYST, 0x00},
{MAX98373_R20A8_BDE_L1_CFG_1, 0x00},
{MAX98373_R20A9_BDE_L1_CFG_2, 0x00},
{MAX98373_R20AA_BDE_L1_CFG_3, 0x00},
{MAX98373_R20AB_BDE_L2_CFG_1, 0x00},
{MAX98373_R20AC_BDE_L2_CFG_2, 0x00},
{MAX98373_R20AD_BDE_L2_CFG_3, 0x00},
{MAX98373_R20AE_BDE_L3_CFG_1, 0x00},
{MAX98373_R20AF_BDE_L3_CFG_2, 0x00},
{MAX98373_R20B0_BDE_L3_CFG_3, 0x00},
{MAX98373_R20B1_BDE_L4_CFG_1, 0x00},
{MAX98373_R20B2_BDE_L4_CFG_2, 0x00},
{MAX98373_R20B3_BDE_L4_CFG_3, 0x00},
{MAX98373_R20B4_BDE_INFINITE_HOLD_RELEASE, 0x00},
{MAX98373_R20B5_BDE_EN, 0x00},
{MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0x00},
{MAX98373_R20D1_DHT_CFG, 0x01},
{MAX98373_R20D2_DHT_ATTACK_CFG, 0x02},
{MAX98373_R20D3_DHT_RELEASE_CFG, 0x03},
{MAX98373_R20D4_DHT_EN, 0x00},
{MAX98373_R20E0_LIMITER_THRESH_CFG, 0x00},
{MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0x00},
{MAX98373_R20E2_LIMITER_EN, 0x00},
{MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 0x00},
{MAX98373_R20FF_GLOBAL_SHDN, 0x00},
{MAX98373_R21FF_REV_ID, 0x42},
};
static bool max98373_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX98373_R21FF_REV_ID:
case MAX98373_R2010_IRQ_CTRL:
/* SoundWire Control Port Registers */
case MAX98373_R0040_SCP_INIT_STAT_1 ... MAX98373_R0070_SCP_FRAME_CTLR:
/* Soundwire Data Port 1 Registers */
case MAX98373_R0100_DP1_INIT_STAT ... MAX98373_R0137_DP1_BLOCK_CTRL3:
/* Soundwire Data Port 3 Registers */
case MAX98373_R0300_DP3_INIT_STAT ... MAX98373_R0337_DP3_BLOCK_CTRL3:
case MAX98373_R2000_SW_RESET ... MAX98373_R200C_INT_EN3:
case MAX98373_R2014_THERM_WARN_THRESH
... MAX98373_R2018_THERM_FOLDBACK_EN:
case MAX98373_R201E_PIN_DRIVE_STRENGTH
... MAX98373_R2036_SOUNDWIRE_CTRL:
case MAX98373_R203D_AMP_DIG_VOL_CTRL ... MAX98373_R2043_AMP_EN:
case MAX98373_R2046_IV_SENSE_ADC_DSP_CFG
... MAX98373_R2047_IV_SENSE_ADC_EN:
case MAX98373_R2051_MEAS_ADC_SAMPLING_RATE
... MAX98373_R2056_MEAS_ADC_PVDD_CH_EN:
case MAX98373_R2090_BDE_LVL_HOLD ... MAX98373_R2092_BDE_CLIPPER_MODE:
case MAX98373_R2097_BDE_L1_THRESH
... MAX98373_R209B_BDE_THRESH_HYST:
case MAX98373_R20A8_BDE_L1_CFG_1 ... MAX98373_R20B3_BDE_L4_CFG_3:
case MAX98373_R20B5_BDE_EN ... MAX98373_R20B6_BDE_CUR_STATE_READBACK:
case MAX98373_R20D1_DHT_CFG ... MAX98373_R20D4_DHT_EN:
case MAX98373_R20E0_LIMITER_THRESH_CFG ... MAX98373_R20E2_LIMITER_EN:
case MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG
... MAX98373_R20FF_GLOBAL_SHDN:
return true;
default:
return false;
}
};
static bool max98373_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK:
case MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK:
case MAX98373_R20B6_BDE_CUR_STATE_READBACK:
case MAX98373_R20FF_GLOBAL_SHDN:
case MAX98373_R21FF_REV_ID:
/* SoundWire Control Port Registers */
case MAX98373_R0040_SCP_INIT_STAT_1 ... MAX98373_R0070_SCP_FRAME_CTLR:
/* Soundwire Data Port 1 Registers */
case MAX98373_R0100_DP1_INIT_STAT ... MAX98373_R0137_DP1_BLOCK_CTRL3:
/* Soundwire Data Port 3 Registers */
case MAX98373_R0300_DP3_INIT_STAT ... MAX98373_R0337_DP3_BLOCK_CTRL3:
case MAX98373_R2000_SW_RESET ... MAX98373_R2009_INT_FLAG3:
return true;
default:
return false;
}
}
static const struct regmap_config max98373_sdw_regmap = {
.reg_bits = 32,
.val_bits = 8,
.max_register = MAX98373_R21FF_REV_ID,
.reg_defaults = max98373_reg,
.num_reg_defaults = ARRAY_SIZE(max98373_reg),
.readable_reg = max98373_readable_register,
.volatile_reg = max98373_volatile_reg,
.cache_type = REGCACHE_RBTREE,
.use_single_read = true,
.use_single_write = true,
};
/* Power management functions and structure */
static __maybe_unused int max98373_suspend(struct device *dev)
{
struct max98373_priv *max98373 = dev_get_drvdata(dev);
int i;
/* cache feedback register values before suspend */
for (i = 0; i < max98373->cache_num; i++)
regmap_read(max98373->regmap, max98373->cache[i].reg, &max98373->cache[i].val);
regcache_cache_only(max98373->regmap, true);
return 0;
}
#define MAX98373_PROBE_TIMEOUT 5000
static __maybe_unused int max98373_resume(struct device *dev)
{
struct sdw_slave *slave = dev_to_sdw_dev(dev);
struct max98373_priv *max98373 = dev_get_drvdata(dev);
unsigned long time;
if (!max98373->first_hw_init)
return 0;
if (!slave->unattach_request)
goto regmap_sync;
time = wait_for_completion_timeout(&slave->initialization_complete,
msecs_to_jiffies(MAX98373_PROBE_TIMEOUT));
if (!time) {
dev_err(dev, "Initialization not complete, timed out\n");
sdw_show_ping_status(slave->bus, true);
return -ETIMEDOUT;
}
regmap_sync:
slave->unattach_request = 0;
regcache_cache_only(max98373->regmap, false);
regcache_sync(max98373->regmap);
return 0;
}
static const struct dev_pm_ops max98373_pm = {
SET_SYSTEM_SLEEP_PM_OPS(max98373_suspend, max98373_resume)
SET_RUNTIME_PM_OPS(max98373_suspend, max98373_resume, NULL)
};
static int max98373_read_prop(struct sdw_slave *slave)
{
struct sdw_slave_prop *prop = &slave->prop;
int nval, i;
u32 bit;
unsigned long addr;
struct sdw_dpn_prop *dpn;
prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
/* BITMAP: 00001000 Dataport 3 is active */
prop->source_ports = BIT(3);
/* BITMAP: 00000010 Dataport 1 is active */
prop->sink_ports = BIT(1);
prop->paging_support = true;
prop->clk_stop_timeout = 20;
nval = hweight32(prop->source_ports);
prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
sizeof(*prop->src_dpn_prop),
GFP_KERNEL);
if (!prop->src_dpn_prop)
return -ENOMEM;
i = 0;
dpn = prop->src_dpn_prop;
addr = prop->source_ports;
for_each_set_bit(bit, &addr, 32) {
dpn[i].num = bit;
dpn[i].type = SDW_DPN_FULL;
dpn[i].simple_ch_prep_sm = true;
dpn[i].ch_prep_timeout = 10;
i++;
}
/* do this again for sink now */
nval = hweight32(prop->sink_ports);
prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
sizeof(*prop->sink_dpn_prop),
GFP_KERNEL);
if (!prop->sink_dpn_prop)
return -ENOMEM;
i = 0;
dpn = prop->sink_dpn_prop;
addr = prop->sink_ports;
for_each_set_bit(bit, &addr, 32) {
dpn[i].num = bit;
dpn[i].type = SDW_DPN_FULL;
dpn[i].simple_ch_prep_sm = true;
dpn[i].ch_prep_timeout = 10;
i++;
}
/* set the timeout values */
prop->clk_stop_timeout = 20;
return 0;
}
static int max98373_io_init(struct sdw_slave *slave)
{
struct device *dev = &slave->dev;
struct max98373_priv *max98373 = dev_get_drvdata(dev);
regcache_cache_only(max98373->regmap, false);
if (max98373->first_hw_init)
regcache_cache_bypass(max98373->regmap, true);
/*
* PM runtime status is marked as 'active' only when a Slave reports as Attached
*/
if (!max98373->first_hw_init)
/* update count of parent 'active' children */
pm_runtime_set_active(dev);
pm_runtime_get_noresume(dev);
/* Software Reset */
max98373_reset(max98373, dev);
/* Set soundwire mode */
regmap_write(max98373->regmap, MAX98373_R2025_AUDIO_IF_MODE, 3);
/* Enable ADC */
regmap_write(max98373->regmap, MAX98373_R2047_IV_SENSE_ADC_EN, 3);
/* Set default Soundwire clock */
regmap_write(max98373->regmap, MAX98373_R2036_SOUNDWIRE_CTRL, 5);
/* Set default sampling rate for speaker and IVDAC */
regmap_write(max98373->regmap, MAX98373_R2028_PCM_SR_SETUP_2, 0x88);
/* IV default slot configuration */
regmap_write(max98373->regmap,
MAX98373_R2020_PCM_TX_HIZ_EN_1,
0xFF);
regmap_write(max98373->regmap,
MAX98373_R2021_PCM_TX_HIZ_EN_2,
0xFF);
/* L/R mix configuration */
regmap_write(max98373->regmap,
MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
0x80);
regmap_write(max98373->regmap,
MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2,
0x1);
/* Enable DC blocker */
regmap_write(max98373->regmap,
MAX98373_R203F_AMP_DSP_CFG,
0x3);
/* Enable IMON VMON DC blocker */
regmap_write(max98373->regmap,
MAX98373_R2046_IV_SENSE_ADC_DSP_CFG,
0x7);
/* voltage, current slot configuration */
regmap_write(max98373->regmap,
MAX98373_R2022_PCM_TX_SRC_1,
(max98373->i_slot << MAX98373_PCM_TX_CH_SRC_A_I_SHIFT |
max98373->v_slot) & 0xFF);
if (max98373->v_slot < 8)
regmap_update_bits(max98373->regmap,
MAX98373_R2020_PCM_TX_HIZ_EN_1,
1 << max98373->v_slot, 0);
else
regmap_update_bits(max98373->regmap,
MAX98373_R2021_PCM_TX_HIZ_EN_2,
1 << (max98373->v_slot - 8), 0);
if (max98373->i_slot < 8)
regmap_update_bits(max98373->regmap,
MAX98373_R2020_PCM_TX_HIZ_EN_1,
1 << max98373->i_slot, 0);
else
regmap_update_bits(max98373->regmap,
MAX98373_R2021_PCM_TX_HIZ_EN_2,
1 << (max98373->i_slot - 8), 0);
/* speaker feedback slot configuration */
regmap_write(max98373->regmap,
MAX98373_R2023_PCM_TX_SRC_2,
max98373->spkfb_slot & 0xFF);
/* Set interleave mode */
if (max98373->interleave_mode)
regmap_update_bits(max98373->regmap,
MAX98373_R2024_PCM_DATA_FMT_CFG,
MAX98373_PCM_TX_CH_INTERLEAVE_MASK,
MAX98373_PCM_TX_CH_INTERLEAVE_MASK);
/* Speaker enable */
regmap_update_bits(max98373->regmap,
MAX98373_R2043_AMP_EN,
MAX98373_SPK_EN_MASK, 1);
regmap_write(max98373->regmap, MAX98373_R20B5_BDE_EN, 1);
regmap_write(max98373->regmap, MAX98373_R20E2_LIMITER_EN, 1);
if (max98373->first_hw_init) {
regcache_cache_bypass(max98373->regmap, false);
regcache_mark_dirty(max98373->regmap);
}
max98373->first_hw_init = true;
max98373->hw_init = true;
pm_runtime_mark_last_busy(dev);
pm_runtime_put_autosuspend(dev);
return 0;
}
static int max98373_clock_calculate(struct sdw_slave *slave,
unsigned int clk_freq)
{
int x, y;
static const int max98373_clk_family[] = {
7680000, 8400000, 9600000, 11289600,
12000000, 12288000, 13000000
};
for (x = 0; x < 4; x++)
for (y = 0; y < ARRAY_SIZE(max98373_clk_family); y++)
if (clk_freq == (max98373_clk_family[y] >> x))
return (x << 3) + y;
/* Set default clock (12.288 Mhz) if the value is not in the list */
dev_err(&slave->dev, "Requested clock not found. (clk_freq = %d)\n",
clk_freq);
return 0x5;
}
static int max98373_clock_config(struct sdw_slave *slave,
struct sdw_bus_params *params)
{
struct device *dev = &slave->dev;
struct max98373_priv *max98373 = dev_get_drvdata(dev);
unsigned int clk_freq, value;
clk_freq = (params->curr_dr_freq >> 1);
/*
* Select the proper value for the register based on the
* requested clock. If the value is not in the list,
* use reasonable default - 12.288 Mhz
*/
value = max98373_clock_calculate(slave, clk_freq);
/* SWCLK */
regmap_write(max98373->regmap, MAX98373_R2036_SOUNDWIRE_CTRL, value);
/* The default Sampling Rate value for IV is 48KHz*/
regmap_write(max98373->regmap, MAX98373_R2028_PCM_SR_SETUP_2, 0x88);
return 0;
}
#define MAX98373_RATES SNDRV_PCM_RATE_8000_96000
#define MAX98373_FORMATS (SNDRV_PCM_FMTBIT_S32_LE)
static int max98373_sdw_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct max98373_priv *max98373 =
snd_soc_component_get_drvdata(component);
struct sdw_stream_config stream_config = {0};
struct sdw_port_config port_config = {0};
struct sdw_stream_runtime *sdw_stream;
int ret, chan_sz, sampling_rate;
sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
if (!sdw_stream)
return -EINVAL;
if (!max98373->slave)
return -EINVAL;
snd_sdw_params_to_config(substream, params, &stream_config, &port_config);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
port_config.num = 1;
if (max98373->slot) {
stream_config.ch_count = max98373->slot;
port_config.ch_mask = max98373->rx_mask;
}
} else {
port_config.num = 3;
/* only IV are supported by capture */
stream_config.ch_count = 2;
port_config.ch_mask = GENMASK((int)stream_config.ch_count - 1, 0);
}
ret = sdw_stream_add_slave(max98373->slave, &stream_config,
&port_config, 1, sdw_stream);
if (ret) {
dev_err(dai->dev, "Unable to configure port\n");
return ret;
}
if (params_channels(params) > 16) {
dev_err(component->dev, "Unsupported channels %d\n",
params_channels(params));
return -EINVAL;
}
/* Channel size configuration */
switch (snd_pcm_format_width(params_format(params))) {
case 16:
chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16;
break;
case 24:
chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24;
break;
case 32:
chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32;
break;
default:
dev_err(component->dev, "Channel size unsupported %d\n",
params_format(params));
return -EINVAL;
}
max98373->ch_size = snd_pcm_format_width(params_format(params));
regmap_update_bits(max98373->regmap,
MAX98373_R2024_PCM_DATA_FMT_CFG,
MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
dev_dbg(component->dev, "Format supported %d", params_format(params));
/* Sampling rate configuration */
switch (params_rate(params)) {
case 8000:
sampling_rate = MAX98373_PCM_SR_SET1_SR_8000;
break;
case 11025:
sampling_rate = MAX98373_PCM_SR_SET1_SR_11025;
break;
case 12000:
sampling_rate = MAX98373_PCM_SR_SET1_SR_12000;
break;
case 16000:
sampling_rate = MAX98373_PCM_SR_SET1_SR_16000;
break;
case 22050:
sampling_rate = MAX98373_PCM_SR_SET1_SR_22050;
break;
case 24000:
sampling_rate = MAX98373_PCM_SR_SET1_SR_24000;
break;
case 32000:
sampling_rate = MAX98373_PCM_SR_SET1_SR_32000;
break;
case 44100:
sampling_rate = MAX98373_PCM_SR_SET1_SR_44100;
break;
case 48000:
sampling_rate = MAX98373_PCM_SR_SET1_SR_48000;
break;
case 88200:
sampling_rate = MAX98373_PCM_SR_SET1_SR_88200;
break;
case 96000:
sampling_rate = MAX98373_PCM_SR_SET1_SR_96000;
break;
default:
dev_err(component->dev, "Rate %d is not supported\n",
params_rate(params));
return -EINVAL;
}
/* set correct sampling frequency */
regmap_update_bits(max98373->regmap,
MAX98373_R2028_PCM_SR_SETUP_2,
MAX98373_PCM_SR_SET2_SR_MASK,
sampling_rate << MAX98373_PCM_SR_SET2_SR_SHIFT);
/* set sampling rate of IV */
regmap_update_bits(max98373->regmap,
MAX98373_R2028_PCM_SR_SETUP_2,
MAX98373_PCM_SR_SET2_IVADC_SR_MASK,
sampling_rate);
return 0;
}
static int max98373_pcm_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct max98373_priv *max98373 =
snd_soc_component_get_drvdata(component);
struct sdw_stream_runtime *sdw_stream =
snd_soc_dai_get_dma_data(dai, substream);
if (!max98373->slave)
return -EINVAL;
sdw_stream_remove_slave(max98373->slave, sdw_stream);
return 0;
}
static int max98373_set_sdw_stream(struct snd_soc_dai *dai,
void *sdw_stream, int direction)
{
snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
return 0;
}
static void max98373_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
snd_soc_dai_set_dma_data(dai, substream, NULL);
}
static int max98373_sdw_set_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask,
unsigned int rx_mask,
int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
struct max98373_priv *max98373 =
snd_soc_component_get_drvdata(component);
/* tx_mask is unused since it's irrelevant for I/V feedback */
if (tx_mask)
return -EINVAL;
if (!rx_mask && !slots && !slot_width)
max98373->tdm_mode = false;
else
max98373->tdm_mode = true;
max98373->rx_mask = rx_mask;
max98373->slot = slots;
return 0;
}
static const struct snd_soc_dai_ops max98373_dai_sdw_ops = {
.hw_params = max98373_sdw_dai_hw_params,
.hw_free = max98373_pcm_hw_free,
.set_stream = max98373_set_sdw_stream,
.shutdown = max98373_shutdown,
.set_tdm_slot = max98373_sdw_set_tdm_slot,
};
static struct snd_soc_dai_driver max98373_sdw_dai[] = {
{
.name = "max98373-aif1",
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MAX98373_RATES,
.formats = MAX98373_FORMATS,
},
.capture = {
.stream_name = "HiFi Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MAX98373_RATES,
.formats = MAX98373_FORMATS,
},
.ops = &max98373_dai_sdw_ops,
}
};
static int max98373_init(struct sdw_slave *slave, struct regmap *regmap)
{
struct max98373_priv *max98373;
int ret;
int i;
struct device *dev = &slave->dev;
/* Allocate and assign private driver data structure */
max98373 = devm_kzalloc(dev, sizeof(*max98373), GFP_KERNEL);
if (!max98373)
return -ENOMEM;
dev_set_drvdata(dev, max98373);
max98373->regmap = regmap;
max98373->slave = slave;
regcache_cache_only(max98373->regmap, true);
max98373->cache_num = ARRAY_SIZE(max98373_sdw_cache_reg);
max98373->cache = devm_kcalloc(dev, max98373->cache_num,
sizeof(*max98373->cache),
GFP_KERNEL);
if (!max98373->cache)
return -ENOMEM;
for (i = 0; i < max98373->cache_num; i++)
max98373->cache[i].reg = max98373_sdw_cache_reg[i];
/* Read voltage and slot configuration */
max98373_slot_config(dev, max98373);
max98373->hw_init = false;
max98373->first_hw_init = false;
/* codec registration */
ret = devm_snd_soc_register_component(dev, &soc_codec_dev_max98373_sdw,
max98373_sdw_dai,
ARRAY_SIZE(max98373_sdw_dai));
if (ret < 0) {
dev_err(dev, "Failed to register codec: %d\n", ret);
return ret;
}
/* set autosuspend parameters */
pm_runtime_set_autosuspend_delay(dev, 3000);
pm_runtime_use_autosuspend(dev);
/* make sure the device does not suspend immediately */
pm_runtime_mark_last_busy(dev);
pm_runtime_enable(dev);
/* important note: the device is NOT tagged as 'active' and will remain
* 'suspended' until the hardware is enumerated/initialized. This is required
* to make sure the ASoC framework use of pm_runtime_get_sync() does not silently
* fail with -EACCESS because of race conditions between card creation and enumeration
*/
return 0;
}
static int max98373_update_status(struct sdw_slave *slave,
enum sdw_slave_status status)
{
struct max98373_priv *max98373 = dev_get_drvdata(&slave->dev);
if (status == SDW_SLAVE_UNATTACHED)
max98373->hw_init = false;
/*
* Perform initialization only if slave status is SDW_SLAVE_ATTACHED
*/
if (max98373->hw_init || status != SDW_SLAVE_ATTACHED)
return 0;
/* perform I/O transfers required for Slave initialization */
return max98373_io_init(slave);
}
static int max98373_bus_config(struct sdw_slave *slave,
struct sdw_bus_params *params)
{
int ret;
ret = max98373_clock_config(slave, params);
if (ret < 0)
dev_err(&slave->dev, "Invalid clk config");
return ret;
}
/*
* slave_ops: callbacks for get_clock_stop_mode, clock_stop and
* port_prep are not defined for now
*/
static struct sdw_slave_ops max98373_slave_ops = {
.read_prop = max98373_read_prop,
.update_status = max98373_update_status,
.bus_config = max98373_bus_config,
};
static int max98373_sdw_probe(struct sdw_slave *slave,
const struct sdw_device_id *id)
{
struct regmap *regmap;
/* Regmap Initialization */
regmap = devm_regmap_init_sdw(slave, &max98373_sdw_regmap);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return max98373_init(slave, regmap);
}
static int max98373_sdw_remove(struct sdw_slave *slave)
{
pm_runtime_disable(&slave->dev);
return 0;
}
#if defined(CONFIG_OF)
static const struct of_device_id max98373_of_match[] = {
{ .compatible = "maxim,max98373", },
{},
};
MODULE_DEVICE_TABLE(of, max98373_of_match);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id max98373_acpi_match[] = {
{ "MX98373", 0 },
{},
};
MODULE_DEVICE_TABLE(acpi, max98373_acpi_match);
#endif
static const struct sdw_device_id max98373_id[] = {
SDW_SLAVE_ENTRY(0x019F, 0x8373, 0),
{},
};
MODULE_DEVICE_TABLE(sdw, max98373_id);
static struct sdw_driver max98373_sdw_driver = {
.driver = {
.name = "max98373",
.owner = THIS_MODULE,
.of_match_table = of_match_ptr(max98373_of_match),
.acpi_match_table = ACPI_PTR(max98373_acpi_match),
.pm = &max98373_pm,
},
.probe = max98373_sdw_probe,
.remove = max98373_sdw_remove,
.ops = &max98373_slave_ops,
.id_table = max98373_id,
};
module_sdw_driver(max98373_sdw_driver);
MODULE_DESCRIPTION("ASoC MAX98373 driver SDW");
MODULE_AUTHOR("Oleg Sherbakov <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/max98373-sdw.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Cirrus Logic Madera class codecs common support
//
// Copyright (C) 2015-2019 Cirrus Logic, Inc. and
// Cirrus Logic International Semiconductor Ltd.
//
#include <linux/delay.h>
#include <linux/gcd.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/tlv.h>
#include <linux/irqchip/irq-madera.h>
#include <linux/mfd/madera/core.h>
#include <linux/mfd/madera/registers.h>
#include <linux/mfd/madera/pdata.h>
#include <sound/madera-pdata.h>
#include <dt-bindings/sound/madera.h>
#include "madera.h"
#define MADERA_AIF_BCLK_CTRL 0x00
#define MADERA_AIF_TX_PIN_CTRL 0x01
#define MADERA_AIF_RX_PIN_CTRL 0x02
#define MADERA_AIF_RATE_CTRL 0x03
#define MADERA_AIF_FORMAT 0x04
#define MADERA_AIF_RX_BCLK_RATE 0x06
#define MADERA_AIF_FRAME_CTRL_1 0x07
#define MADERA_AIF_FRAME_CTRL_2 0x08
#define MADERA_AIF_FRAME_CTRL_3 0x09
#define MADERA_AIF_FRAME_CTRL_4 0x0A
#define MADERA_AIF_FRAME_CTRL_5 0x0B
#define MADERA_AIF_FRAME_CTRL_6 0x0C
#define MADERA_AIF_FRAME_CTRL_7 0x0D
#define MADERA_AIF_FRAME_CTRL_8 0x0E
#define MADERA_AIF_FRAME_CTRL_9 0x0F
#define MADERA_AIF_FRAME_CTRL_10 0x10
#define MADERA_AIF_FRAME_CTRL_11 0x11
#define MADERA_AIF_FRAME_CTRL_12 0x12
#define MADERA_AIF_FRAME_CTRL_13 0x13
#define MADERA_AIF_FRAME_CTRL_14 0x14
#define MADERA_AIF_FRAME_CTRL_15 0x15
#define MADERA_AIF_FRAME_CTRL_16 0x16
#define MADERA_AIF_FRAME_CTRL_17 0x17
#define MADERA_AIF_FRAME_CTRL_18 0x18
#define MADERA_AIF_TX_ENABLES 0x19
#define MADERA_AIF_RX_ENABLES 0x1A
#define MADERA_AIF_FORCE_WRITE 0x1B
#define MADERA_DSP_CONFIG_1_OFFS 0x00
#define MADERA_DSP_CONFIG_2_OFFS 0x02
#define MADERA_DSP_CLK_SEL_MASK 0x70000
#define MADERA_DSP_CLK_SEL_SHIFT 16
#define MADERA_DSP_RATE_MASK 0x7800
#define MADERA_DSP_RATE_SHIFT 11
#define MADERA_SYSCLK_6MHZ 0
#define MADERA_SYSCLK_12MHZ 1
#define MADERA_SYSCLK_24MHZ 2
#define MADERA_SYSCLK_49MHZ 3
#define MADERA_SYSCLK_98MHZ 4
#define MADERA_DSPCLK_9MHZ 0
#define MADERA_DSPCLK_18MHZ 1
#define MADERA_DSPCLK_36MHZ 2
#define MADERA_DSPCLK_73MHZ 3
#define MADERA_DSPCLK_147MHZ 4
#define MADERA_FLL_VCO_CORNER 141900000
#define MADERA_FLL_MAX_FREF 13500000
#define MADERA_FLL_MAX_N 1023
#define MADERA_FLL_MIN_FOUT 90000000
#define MADERA_FLL_MAX_FOUT 100000000
#define MADERA_FLL_MAX_FRATIO 16
#define MADERA_FLL_MAX_REFDIV 8
#define MADERA_FLL_OUTDIV 3
#define MADERA_FLL_VCO_MULT 3
#define MADERA_FLLAO_MAX_FREF 12288000
#define MADERA_FLLAO_MIN_N 4
#define MADERA_FLLAO_MAX_N 1023
#define MADERA_FLLAO_MAX_FBDIV 254
#define MADERA_FLLHJ_INT_MAX_N 1023
#define MADERA_FLLHJ_INT_MIN_N 1
#define MADERA_FLLHJ_FRAC_MAX_N 255
#define MADERA_FLLHJ_FRAC_MIN_N 4
#define MADERA_FLLHJ_LOW_THRESH 192000
#define MADERA_FLLHJ_MID_THRESH 1152000
#define MADERA_FLLHJ_MAX_THRESH 13000000
#define MADERA_FLLHJ_LOW_GAINS 0x23f0
#define MADERA_FLLHJ_MID_GAINS 0x22f2
#define MADERA_FLLHJ_HIGH_GAINS 0x21f0
#define MADERA_FLL_SYNCHRONISER_OFFS 0x10
#define CS47L35_FLL_SYNCHRONISER_OFFS 0xE
#define MADERA_FLL_CONTROL_1_OFFS 0x1
#define MADERA_FLL_CONTROL_2_OFFS 0x2
#define MADERA_FLL_CONTROL_3_OFFS 0x3
#define MADERA_FLL_CONTROL_4_OFFS 0x4
#define MADERA_FLL_CONTROL_5_OFFS 0x5
#define MADERA_FLL_CONTROL_6_OFFS 0x6
#define MADERA_FLL_GAIN_OFFS 0x8
#define MADERA_FLL_CONTROL_7_OFFS 0x9
#define MADERA_FLL_EFS_2_OFFS 0xA
#define MADERA_FLL_SYNCHRONISER_1_OFFS 0x1
#define MADERA_FLL_SYNCHRONISER_2_OFFS 0x2
#define MADERA_FLL_SYNCHRONISER_3_OFFS 0x3
#define MADERA_FLL_SYNCHRONISER_4_OFFS 0x4
#define MADERA_FLL_SYNCHRONISER_5_OFFS 0x5
#define MADERA_FLL_SYNCHRONISER_6_OFFS 0x6
#define MADERA_FLL_SYNCHRONISER_7_OFFS 0x7
#define MADERA_FLL_SPREAD_SPECTRUM_OFFS 0x9
#define MADERA_FLL_GPIO_CLOCK_OFFS 0xA
#define MADERA_FLL_CONTROL_10_OFFS 0xA
#define MADERA_FLL_CONTROL_11_OFFS 0xB
#define MADERA_FLL1_DIGITAL_TEST_1_OFFS 0xD
#define MADERA_FLLAO_CONTROL_1_OFFS 0x1
#define MADERA_FLLAO_CONTROL_2_OFFS 0x2
#define MADERA_FLLAO_CONTROL_3_OFFS 0x3
#define MADERA_FLLAO_CONTROL_4_OFFS 0x4
#define MADERA_FLLAO_CONTROL_5_OFFS 0x5
#define MADERA_FLLAO_CONTROL_6_OFFS 0x6
#define MADERA_FLLAO_CONTROL_7_OFFS 0x8
#define MADERA_FLLAO_CONTROL_8_OFFS 0xA
#define MADERA_FLLAO_CONTROL_9_OFFS 0xB
#define MADERA_FLLAO_CONTROL_10_OFFS 0xC
#define MADERA_FLLAO_CONTROL_11_OFFS 0xD
#define MADERA_FMT_DSP_MODE_A 0
#define MADERA_FMT_DSP_MODE_B 1
#define MADERA_FMT_I2S_MODE 2
#define MADERA_FMT_LEFT_JUSTIFIED_MODE 3
#define madera_fll_err(_fll, fmt, ...) \
dev_err(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
#define madera_fll_warn(_fll, fmt, ...) \
dev_warn(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
#define madera_fll_dbg(_fll, fmt, ...) \
dev_dbg(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
#define madera_aif_err(_dai, fmt, ...) \
dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
#define madera_aif_warn(_dai, fmt, ...) \
dev_warn(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
#define madera_aif_dbg(_dai, fmt, ...) \
dev_dbg(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
static const int madera_dsp_bus_error_irqs[MADERA_MAX_ADSP] = {
MADERA_IRQ_DSP1_BUS_ERR,
MADERA_IRQ_DSP2_BUS_ERR,
MADERA_IRQ_DSP3_BUS_ERR,
MADERA_IRQ_DSP4_BUS_ERR,
MADERA_IRQ_DSP5_BUS_ERR,
MADERA_IRQ_DSP6_BUS_ERR,
MADERA_IRQ_DSP7_BUS_ERR,
};
int madera_clk_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct madera_priv *priv = snd_soc_component_get_drvdata(component);
struct madera *madera = priv->madera;
unsigned int val;
int clk_idx;
int ret;
ret = regmap_read(madera->regmap, w->reg, &val);
if (ret) {
dev_err(madera->dev, "Failed to check clock source: %d\n", ret);
return ret;
}
switch ((val & MADERA_SYSCLK_SRC_MASK) >> MADERA_SYSCLK_SRC_SHIFT) {
case MADERA_CLK_SRC_MCLK1:
clk_idx = MADERA_MCLK1;
break;
case MADERA_CLK_SRC_MCLK2:
clk_idx = MADERA_MCLK2;
break;
case MADERA_CLK_SRC_MCLK3:
clk_idx = MADERA_MCLK3;
break;
default:
return 0;
}
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
return clk_prepare_enable(madera->mclk[clk_idx].clk);
case SND_SOC_DAPM_POST_PMD:
clk_disable_unprepare(madera->mclk[clk_idx].clk);
return 0;
default:
return 0;
}
}
EXPORT_SYMBOL_GPL(madera_clk_ev);
static void madera_spin_sysclk(struct madera_priv *priv)
{
struct madera *madera = priv->madera;
unsigned int val;
int ret, i;
/* Skip this if the chip is down */
if (pm_runtime_suspended(madera->dev))
return;
/*
* Just read a register a few times to ensure the internal
* oscillator sends out a few clocks.
*/
for (i = 0; i < 4; i++) {
ret = regmap_read(madera->regmap, MADERA_SOFTWARE_RESET, &val);
if (ret)
dev_err(madera->dev,
"Failed to read sysclk spin %d: %d\n", i, ret);
}
udelay(300);
}
int madera_sysclk_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct madera_priv *priv = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
case SND_SOC_DAPM_PRE_PMD:
madera_spin_sysclk(priv);
break;
default:
break;
}
return madera_clk_ev(w, kcontrol, event);
}
EXPORT_SYMBOL_GPL(madera_sysclk_ev);
static int madera_check_speaker_overheat(struct madera *madera,
bool *warn, bool *shutdown)
{
unsigned int val;
int ret;
ret = regmap_read(madera->regmap, MADERA_IRQ1_RAW_STATUS_15, &val);
if (ret) {
dev_err(madera->dev, "Failed to read thermal status: %d\n",
ret);
return ret;
}
*warn = val & MADERA_SPK_OVERHEAT_WARN_STS1;
*shutdown = val & MADERA_SPK_OVERHEAT_STS1;
return 0;
}
int madera_spk_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct madera_priv *priv = snd_soc_component_get_drvdata(component);
struct madera *madera = priv->madera;
bool warn, shutdown;
int ret;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
ret = madera_check_speaker_overheat(madera, &warn, &shutdown);
if (ret)
return ret;
if (shutdown) {
dev_crit(madera->dev,
"Speaker not enabled due to temperature\n");
return -EBUSY;
}
regmap_update_bits(madera->regmap, MADERA_OUTPUT_ENABLES_1,
1 << w->shift, 1 << w->shift);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_update_bits(madera->regmap, MADERA_OUTPUT_ENABLES_1,
1 << w->shift, 0);
break;
default:
break;
}
return 0;
}
EXPORT_SYMBOL_GPL(madera_spk_ev);
static irqreturn_t madera_thermal_warn(int irq, void *data)
{
struct madera *madera = data;
bool warn, shutdown;
int ret;
ret = madera_check_speaker_overheat(madera, &warn, &shutdown);
if (ret || shutdown) { /* for safety attempt to shutdown on error */
dev_crit(madera->dev, "Thermal shutdown\n");
ret = regmap_update_bits(madera->regmap,
MADERA_OUTPUT_ENABLES_1,
MADERA_OUT4L_ENA |
MADERA_OUT4R_ENA, 0);
if (ret != 0)
dev_crit(madera->dev,
"Failed to disable speaker outputs: %d\n",
ret);
} else if (warn) {
dev_alert(madera->dev, "Thermal warning\n");
} else {
dev_info(madera->dev, "Spurious thermal warning\n");
return IRQ_NONE;
}
return IRQ_HANDLED;
}
int madera_init_overheat(struct madera_priv *priv)
{
struct madera *madera = priv->madera;
struct device *dev = madera->dev;
int ret;
ret = madera_request_irq(madera, MADERA_IRQ_SPK_OVERHEAT_WARN,
"Thermal warning", madera_thermal_warn,
madera);
if (ret)
dev_err(dev, "Failed to get thermal warning IRQ: %d\n", ret);
ret = madera_request_irq(madera, MADERA_IRQ_SPK_OVERHEAT,
"Thermal shutdown", madera_thermal_warn,
madera);
if (ret)
dev_err(dev, "Failed to get thermal shutdown IRQ: %d\n", ret);
return 0;
}
EXPORT_SYMBOL_GPL(madera_init_overheat);
int madera_free_overheat(struct madera_priv *priv)
{
struct madera *madera = priv->madera;
madera_free_irq(madera, MADERA_IRQ_SPK_OVERHEAT_WARN, madera);
madera_free_irq(madera, MADERA_IRQ_SPK_OVERHEAT, madera);
return 0;
}
EXPORT_SYMBOL_GPL(madera_free_overheat);
static int madera_get_variable_u32_array(struct device *dev,
const char *propname,
u32 *dest, int n_max,
int multiple)
{
int n, ret;
n = device_property_count_u32(dev, propname);
if (n < 0) {
if (n == -EINVAL)
return 0; /* missing, ignore */
dev_warn(dev, "%s malformed (%d)\n", propname, n);
return n;
} else if ((n % multiple) != 0) {
dev_warn(dev, "%s not a multiple of %d entries\n",
propname, multiple);
return -EINVAL;
}
if (n > n_max)
n = n_max;
ret = device_property_read_u32_array(dev, propname, dest, n);
if (ret < 0)
return ret;
return n;
}
static void madera_prop_get_inmode(struct madera_priv *priv)
{
struct madera *madera = priv->madera;
struct madera_codec_pdata *pdata = &madera->pdata.codec;
u32 tmp[MADERA_MAX_INPUT * MADERA_MAX_MUXED_CHANNELS];
int n, i, in_idx, ch_idx;
BUILD_BUG_ON(ARRAY_SIZE(pdata->inmode) != MADERA_MAX_INPUT);
BUILD_BUG_ON(ARRAY_SIZE(pdata->inmode[0]) != MADERA_MAX_MUXED_CHANNELS);
n = madera_get_variable_u32_array(madera->dev, "cirrus,inmode",
tmp, ARRAY_SIZE(tmp),
MADERA_MAX_MUXED_CHANNELS);
if (n < 0)
return;
in_idx = 0;
ch_idx = 0;
for (i = 0; i < n; ++i) {
pdata->inmode[in_idx][ch_idx] = tmp[i];
if (++ch_idx == MADERA_MAX_MUXED_CHANNELS) {
ch_idx = 0;
++in_idx;
}
}
}
static void madera_prop_get_pdata(struct madera_priv *priv)
{
struct madera *madera = priv->madera;
struct madera_codec_pdata *pdata = &madera->pdata.codec;
u32 out_mono[ARRAY_SIZE(pdata->out_mono)];
int i, n;
madera_prop_get_inmode(priv);
n = madera_get_variable_u32_array(madera->dev, "cirrus,out-mono",
out_mono, ARRAY_SIZE(out_mono), 1);
if (n > 0)
for (i = 0; i < n; ++i)
pdata->out_mono[i] = !!out_mono[i];
madera_get_variable_u32_array(madera->dev,
"cirrus,max-channels-clocked",
pdata->max_channels_clocked,
ARRAY_SIZE(pdata->max_channels_clocked),
1);
madera_get_variable_u32_array(madera->dev, "cirrus,pdm-fmt",
pdata->pdm_fmt,
ARRAY_SIZE(pdata->pdm_fmt), 1);
madera_get_variable_u32_array(madera->dev, "cirrus,pdm-mute",
pdata->pdm_mute,
ARRAY_SIZE(pdata->pdm_mute), 1);
madera_get_variable_u32_array(madera->dev, "cirrus,dmic-ref",
pdata->dmic_ref,
ARRAY_SIZE(pdata->dmic_ref), 1);
}
int madera_core_init(struct madera_priv *priv)
{
int i;
/* trap undersized array initializers */
BUILD_BUG_ON(!madera_mixer_texts[MADERA_NUM_MIXER_INPUTS - 1]);
BUILD_BUG_ON(!madera_mixer_values[MADERA_NUM_MIXER_INPUTS - 1]);
if (!dev_get_platdata(priv->madera->dev))
madera_prop_get_pdata(priv);
mutex_init(&priv->rate_lock);
for (i = 0; i < MADERA_MAX_HP_OUTPUT; i++)
priv->madera->out_clamp[i] = true;
return 0;
}
EXPORT_SYMBOL_GPL(madera_core_init);
int madera_core_free(struct madera_priv *priv)
{
mutex_destroy(&priv->rate_lock);
return 0;
}
EXPORT_SYMBOL_GPL(madera_core_free);
static void madera_debug_dump_domain_groups(const struct madera_priv *priv)
{
struct madera *madera = priv->madera;
int i;
for (i = 0; i < ARRAY_SIZE(priv->domain_group_ref); ++i)
dev_dbg(madera->dev, "domain_grp_ref[%d]=%d\n", i,
priv->domain_group_ref[i]);
}
int madera_domain_clk_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct madera_priv *priv = snd_soc_component_get_drvdata(component);
int dom_grp = w->shift;
if (dom_grp >= ARRAY_SIZE(priv->domain_group_ref)) {
WARN(true, "%s dom_grp exceeds array size\n", __func__);
return -EINVAL;
}
/*
* We can't rely on the DAPM mutex for locking because we need a lock
* that can safely be called in hw_params
*/
mutex_lock(&priv->rate_lock);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
dev_dbg(priv->madera->dev, "Inc ref on domain group %d\n",
dom_grp);
++priv->domain_group_ref[dom_grp];
break;
case SND_SOC_DAPM_POST_PMD:
dev_dbg(priv->madera->dev, "Dec ref on domain group %d\n",
dom_grp);
--priv->domain_group_ref[dom_grp];
break;
default:
break;
}
madera_debug_dump_domain_groups(priv);
mutex_unlock(&priv->rate_lock);
return 0;
}
EXPORT_SYMBOL_GPL(madera_domain_clk_ev);
int madera_out1_demux_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_dapm_kcontrol_component(kcontrol);
struct snd_soc_dapm_context *dapm =
snd_soc_dapm_kcontrol_dapm(kcontrol);
struct madera_priv *priv = snd_soc_component_get_drvdata(component);
struct madera *madera = priv->madera;
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int ep_sel, mux, change;
bool out_mono;
int ret;
if (ucontrol->value.enumerated.item[0] > e->items - 1)
return -EINVAL;
mux = ucontrol->value.enumerated.item[0];
snd_soc_dapm_mutex_lock(dapm);
ep_sel = mux << MADERA_EP_SEL_SHIFT;
change = snd_soc_component_test_bits(component, MADERA_OUTPUT_ENABLES_1,
MADERA_EP_SEL_MASK,
ep_sel);
if (!change)
goto end;
/* EP_SEL should not be modified while HP or EP driver is enabled */
ret = regmap_update_bits(madera->regmap, MADERA_OUTPUT_ENABLES_1,
MADERA_OUT1L_ENA | MADERA_OUT1R_ENA, 0);
if (ret)
dev_warn(madera->dev, "Failed to disable outputs: %d\n", ret);
usleep_range(2000, 3000); /* wait for wseq to complete */
/* change demux setting */
ret = 0;
if (madera->out_clamp[0])
ret = regmap_update_bits(madera->regmap,
MADERA_OUTPUT_ENABLES_1,
MADERA_EP_SEL_MASK, ep_sel);
if (ret) {
dev_err(madera->dev, "Failed to set OUT1 demux: %d\n", ret);
} else {
/* apply correct setting for mono mode */
if (!ep_sel && !madera->pdata.codec.out_mono[0])
out_mono = false; /* stereo HP */
else
out_mono = true; /* EP or mono HP */
ret = madera_set_output_mode(component, 1, out_mono);
if (ret)
dev_warn(madera->dev,
"Failed to set output mode: %d\n", ret);
}
/*
* if HPDET has disabled the clamp while switching to HPOUT
* OUT1 should remain disabled
*/
if (ep_sel ||
(madera->out_clamp[0] && !madera->out_shorted[0])) {
ret = regmap_update_bits(madera->regmap,
MADERA_OUTPUT_ENABLES_1,
MADERA_OUT1L_ENA | MADERA_OUT1R_ENA,
madera->hp_ena);
if (ret)
dev_warn(madera->dev,
"Failed to restore earpiece outputs: %d\n",
ret);
else if (madera->hp_ena)
msleep(34); /* wait for enable wseq */
else
usleep_range(2000, 3000); /* wait for disable wseq */
}
end:
snd_soc_dapm_mutex_unlock(dapm);
ret = snd_soc_dapm_mux_update_power(dapm, kcontrol, mux, e, NULL);
if (ret < 0) {
dev_err(madera->dev, "Failed to update demux power state: %d\n", ret);
return ret;
}
return change;
}
EXPORT_SYMBOL_GPL(madera_out1_demux_put);
int madera_out1_demux_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_dapm_kcontrol_component(kcontrol);
unsigned int val;
val = snd_soc_component_read(component, MADERA_OUTPUT_ENABLES_1);
val &= MADERA_EP_SEL_MASK;
val >>= MADERA_EP_SEL_SHIFT;
ucontrol->value.enumerated.item[0] = val;
return 0;
}
EXPORT_SYMBOL_GPL(madera_out1_demux_get);
static int madera_inmux_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_dapm_kcontrol_component(kcontrol);
struct snd_soc_dapm_context *dapm =
snd_soc_dapm_kcontrol_dapm(kcontrol);
struct madera_priv *priv = snd_soc_component_get_drvdata(component);
struct madera *madera = priv->madera;
struct regmap *regmap = madera->regmap;
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int mux, val, mask;
unsigned int inmode;
bool changed;
int ret;
mux = ucontrol->value.enumerated.item[0];
if (mux > 1)
return -EINVAL;
val = mux << e->shift_l;
mask = (e->mask << e->shift_l) | MADERA_IN1L_SRC_SE_MASK;
switch (e->reg) {
case MADERA_ADC_DIGITAL_VOLUME_1L:
inmode = madera->pdata.codec.inmode[0][2 * mux];
break;
case MADERA_ADC_DIGITAL_VOLUME_1R:
inmode = madera->pdata.codec.inmode[0][1 + (2 * mux)];
break;
case MADERA_ADC_DIGITAL_VOLUME_2L:
inmode = madera->pdata.codec.inmode[1][2 * mux];
break;
case MADERA_ADC_DIGITAL_VOLUME_2R:
inmode = madera->pdata.codec.inmode[1][1 + (2 * mux)];
break;
default:
return -EINVAL;
}
if (inmode & MADERA_INMODE_SE)
val |= 1 << MADERA_IN1L_SRC_SE_SHIFT;
dev_dbg(madera->dev, "mux=%u reg=0x%x inmode=0x%x mask=0x%x val=0x%x\n",
mux, e->reg, inmode, mask, val);
ret = regmap_update_bits_check(regmap, e->reg, mask, val, &changed);
if (ret < 0)
return ret;
if (changed)
return snd_soc_dapm_mux_update_power(dapm, kcontrol,
mux, e, NULL);
else
return 0;
}
static const char * const madera_inmux_texts[] = {
"A",
"B",
};
static SOC_ENUM_SINGLE_DECL(madera_in1muxl_enum,
MADERA_ADC_DIGITAL_VOLUME_1L,
MADERA_IN1L_SRC_SHIFT,
madera_inmux_texts);
static SOC_ENUM_SINGLE_DECL(madera_in1muxr_enum,
MADERA_ADC_DIGITAL_VOLUME_1R,
MADERA_IN1R_SRC_SHIFT,
madera_inmux_texts);
static SOC_ENUM_SINGLE_DECL(madera_in2muxl_enum,
MADERA_ADC_DIGITAL_VOLUME_2L,
MADERA_IN2L_SRC_SHIFT,
madera_inmux_texts);
static SOC_ENUM_SINGLE_DECL(madera_in2muxr_enum,
MADERA_ADC_DIGITAL_VOLUME_2R,
MADERA_IN2R_SRC_SHIFT,
madera_inmux_texts);
const struct snd_kcontrol_new madera_inmux[] = {
SOC_DAPM_ENUM_EXT("IN1L Mux", madera_in1muxl_enum,
snd_soc_dapm_get_enum_double, madera_inmux_put),
SOC_DAPM_ENUM_EXT("IN1R Mux", madera_in1muxr_enum,
snd_soc_dapm_get_enum_double, madera_inmux_put),
SOC_DAPM_ENUM_EXT("IN2L Mux", madera_in2muxl_enum,
snd_soc_dapm_get_enum_double, madera_inmux_put),
SOC_DAPM_ENUM_EXT("IN2R Mux", madera_in2muxr_enum,
snd_soc_dapm_get_enum_double, madera_inmux_put),
};
EXPORT_SYMBOL_GPL(madera_inmux);
static const char * const madera_dmode_texts[] = {
"Analog",
"Digital",
};
static SOC_ENUM_SINGLE_DECL(madera_in1dmode_enum,
MADERA_IN1L_CONTROL,
MADERA_IN1_MODE_SHIFT,
madera_dmode_texts);
static SOC_ENUM_SINGLE_DECL(madera_in2dmode_enum,
MADERA_IN2L_CONTROL,
MADERA_IN2_MODE_SHIFT,
madera_dmode_texts);
static SOC_ENUM_SINGLE_DECL(madera_in3dmode_enum,
MADERA_IN3L_CONTROL,
MADERA_IN3_MODE_SHIFT,
madera_dmode_texts);
const struct snd_kcontrol_new madera_inmode[] = {
SOC_DAPM_ENUM("IN1 Mode", madera_in1dmode_enum),
SOC_DAPM_ENUM("IN2 Mode", madera_in2dmode_enum),
SOC_DAPM_ENUM("IN3 Mode", madera_in3dmode_enum),
};
EXPORT_SYMBOL_GPL(madera_inmode);
static bool madera_can_change_grp_rate(const struct madera_priv *priv,
unsigned int reg)
{
int count;
switch (reg) {
case MADERA_FX_CTRL1:
count = priv->domain_group_ref[MADERA_DOM_GRP_FX];
break;
case MADERA_ASRC1_RATE1:
case MADERA_ASRC1_RATE2:
count = priv->domain_group_ref[MADERA_DOM_GRP_ASRC1];
break;
case MADERA_ASRC2_RATE1:
case MADERA_ASRC2_RATE2:
count = priv->domain_group_ref[MADERA_DOM_GRP_ASRC2];
break;
case MADERA_ISRC_1_CTRL_1:
case MADERA_ISRC_1_CTRL_2:
count = priv->domain_group_ref[MADERA_DOM_GRP_ISRC1];
break;
case MADERA_ISRC_2_CTRL_1:
case MADERA_ISRC_2_CTRL_2:
count = priv->domain_group_ref[MADERA_DOM_GRP_ISRC2];
break;
case MADERA_ISRC_3_CTRL_1:
case MADERA_ISRC_3_CTRL_2:
count = priv->domain_group_ref[MADERA_DOM_GRP_ISRC3];
break;
case MADERA_ISRC_4_CTRL_1:
case MADERA_ISRC_4_CTRL_2:
count = priv->domain_group_ref[MADERA_DOM_GRP_ISRC4];
break;
case MADERA_OUTPUT_RATE_1:
count = priv->domain_group_ref[MADERA_DOM_GRP_OUT];
break;
case MADERA_SPD1_TX_CONTROL:
count = priv->domain_group_ref[MADERA_DOM_GRP_SPD];
break;
case MADERA_DSP1_CONFIG_1:
case MADERA_DSP1_CONFIG_2:
count = priv->domain_group_ref[MADERA_DOM_GRP_DSP1];
break;
case MADERA_DSP2_CONFIG_1:
case MADERA_DSP2_CONFIG_2:
count = priv->domain_group_ref[MADERA_DOM_GRP_DSP2];
break;
case MADERA_DSP3_CONFIG_1:
case MADERA_DSP3_CONFIG_2:
count = priv->domain_group_ref[MADERA_DOM_GRP_DSP3];
break;
case MADERA_DSP4_CONFIG_1:
case MADERA_DSP4_CONFIG_2:
count = priv->domain_group_ref[MADERA_DOM_GRP_DSP4];
break;
case MADERA_DSP5_CONFIG_1:
case MADERA_DSP5_CONFIG_2:
count = priv->domain_group_ref[MADERA_DOM_GRP_DSP5];
break;
case MADERA_DSP6_CONFIG_1:
case MADERA_DSP6_CONFIG_2:
count = priv->domain_group_ref[MADERA_DOM_GRP_DSP6];
break;
case MADERA_DSP7_CONFIG_1:
case MADERA_DSP7_CONFIG_2:
count = priv->domain_group_ref[MADERA_DOM_GRP_DSP7];
break;
case MADERA_AIF1_RATE_CTRL:
count = priv->domain_group_ref[MADERA_DOM_GRP_AIF1];
break;
case MADERA_AIF2_RATE_CTRL:
count = priv->domain_group_ref[MADERA_DOM_GRP_AIF2];
break;
case MADERA_AIF3_RATE_CTRL:
count = priv->domain_group_ref[MADERA_DOM_GRP_AIF3];
break;
case MADERA_AIF4_RATE_CTRL:
count = priv->domain_group_ref[MADERA_DOM_GRP_AIF4];
break;
case MADERA_SLIMBUS_RATES_1:
case MADERA_SLIMBUS_RATES_2:
case MADERA_SLIMBUS_RATES_3:
case MADERA_SLIMBUS_RATES_4:
case MADERA_SLIMBUS_RATES_5:
case MADERA_SLIMBUS_RATES_6:
case MADERA_SLIMBUS_RATES_7:
case MADERA_SLIMBUS_RATES_8:
count = priv->domain_group_ref[MADERA_DOM_GRP_SLIMBUS];
break;
case MADERA_PWM_DRIVE_1:
count = priv->domain_group_ref[MADERA_DOM_GRP_PWM];
break;
default:
return false;
}
dev_dbg(priv->madera->dev, "Rate reg 0x%x group ref %d\n", reg, count);
if (count)
return false;
else
return true;
}
static int madera_adsp_rate_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct madera_priv *priv = snd_soc_component_get_drvdata(component);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int cached_rate;
const int adsp_num = e->shift_l;
int item;
mutex_lock(&priv->rate_lock);
cached_rate = priv->adsp_rate_cache[adsp_num];
mutex_unlock(&priv->rate_lock);
item = snd_soc_enum_val_to_item(e, cached_rate);
ucontrol->value.enumerated.item[0] = item;
return 0;
}
static int madera_adsp_rate_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct madera_priv *priv = snd_soc_component_get_drvdata(component);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
const int adsp_num = e->shift_l;
const unsigned int item = ucontrol->value.enumerated.item[0];
int ret = 0;
if (item >= e->items)
return -EINVAL;
/*
* We don't directly write the rate register here but we want to
* maintain consistent behaviour that rate domains cannot be changed
* while in use since this is a hardware requirement
*/
mutex_lock(&priv->rate_lock);
if (!madera_can_change_grp_rate(priv, priv->adsp[adsp_num].cs_dsp.base)) {
dev_warn(priv->madera->dev,
"Cannot change '%s' while in use by active audio paths\n",
kcontrol->id.name);
ret = -EBUSY;
} else if (priv->adsp_rate_cache[adsp_num] != e->values[item]) {
/* Volatile register so defer until the codec is powered up */
priv->adsp_rate_cache[adsp_num] = e->values[item];
ret = 1;
}
mutex_unlock(&priv->rate_lock);
return ret;
}
static const struct soc_enum madera_adsp_rate_enum[] = {
SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, 0xf, MADERA_RATE_ENUM_SIZE,
madera_rate_text, madera_rate_val),
SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 1, 0xf, MADERA_RATE_ENUM_SIZE,
madera_rate_text, madera_rate_val),
SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 2, 0xf, MADERA_RATE_ENUM_SIZE,
madera_rate_text, madera_rate_val),
SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 3, 0xf, MADERA_RATE_ENUM_SIZE,
madera_rate_text, madera_rate_val),
SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 4, 0xf, MADERA_RATE_ENUM_SIZE,
madera_rate_text, madera_rate_val),
SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 5, 0xf, MADERA_RATE_ENUM_SIZE,
madera_rate_text, madera_rate_val),
SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 6, 0xf, MADERA_RATE_ENUM_SIZE,
madera_rate_text, madera_rate_val),
};
const struct snd_kcontrol_new madera_adsp_rate_controls[] = {
SOC_ENUM_EXT("DSP1 Rate", madera_adsp_rate_enum[0],
madera_adsp_rate_get, madera_adsp_rate_put),
SOC_ENUM_EXT("DSP2 Rate", madera_adsp_rate_enum[1],
madera_adsp_rate_get, madera_adsp_rate_put),
SOC_ENUM_EXT("DSP3 Rate", madera_adsp_rate_enum[2],
madera_adsp_rate_get, madera_adsp_rate_put),
SOC_ENUM_EXT("DSP4 Rate", madera_adsp_rate_enum[3],
madera_adsp_rate_get, madera_adsp_rate_put),
SOC_ENUM_EXT("DSP5 Rate", madera_adsp_rate_enum[4],
madera_adsp_rate_get, madera_adsp_rate_put),
SOC_ENUM_EXT("DSP6 Rate", madera_adsp_rate_enum[5],
madera_adsp_rate_get, madera_adsp_rate_put),
SOC_ENUM_EXT("DSP7 Rate", madera_adsp_rate_enum[6],
madera_adsp_rate_get, madera_adsp_rate_put),
};
EXPORT_SYMBOL_GPL(madera_adsp_rate_controls);
static int madera_write_adsp_clk_setting(struct madera_priv *priv,
struct wm_adsp *dsp,
unsigned int freq)
{
unsigned int val;
unsigned int mask = MADERA_DSP_RATE_MASK;
int ret;
val = priv->adsp_rate_cache[dsp->cs_dsp.num - 1] << MADERA_DSP_RATE_SHIFT;
switch (priv->madera->type) {
case CS47L35:
case CS47L85:
case WM1840:
/* use legacy frequency registers */
mask |= MADERA_DSP_CLK_SEL_MASK;
val |= (freq << MADERA_DSP_CLK_SEL_SHIFT);
break;
default:
/* Configure exact dsp frequency */
dev_dbg(priv->madera->dev, "Set DSP frequency to 0x%x\n", freq);
ret = regmap_write(dsp->cs_dsp.regmap,
dsp->cs_dsp.base + MADERA_DSP_CONFIG_2_OFFS, freq);
if (ret)
goto err;
break;
}
ret = regmap_update_bits(dsp->cs_dsp.regmap,
dsp->cs_dsp.base + MADERA_DSP_CONFIG_1_OFFS,
mask, val);
if (ret)
goto err;
dev_dbg(priv->madera->dev, "Set DSP clocking to 0x%x\n", val);
return 0;
err:
dev_err(dsp->cs_dsp.dev, "Failed to set DSP%d clock: %d\n", dsp->cs_dsp.num, ret);
return ret;
}
int madera_set_adsp_clk(struct madera_priv *priv, int dsp_num,
unsigned int freq)
{
struct wm_adsp *dsp = &priv->adsp[dsp_num];
struct madera *madera = priv->madera;
unsigned int cur, new;
int ret;
/*
* This is called at a higher DAPM priority than the mux widgets so
* the muxes are still off at this point and it's safe to change
* the rate domain control.
* Also called at a lower DAPM priority than the domain group widgets
* so locking the reads of adsp_rate_cache is not necessary as we know
* changes are locked out by the domain_group_ref reference count.
*/
ret = regmap_read(dsp->cs_dsp.regmap, dsp->cs_dsp.base, &cur);
if (ret) {
dev_err(madera->dev,
"Failed to read current DSP rate: %d\n", ret);
return ret;
}
cur &= MADERA_DSP_RATE_MASK;
new = priv->adsp_rate_cache[dsp->cs_dsp.num - 1] << MADERA_DSP_RATE_SHIFT;
if (new == cur) {
dev_dbg(madera->dev, "DSP rate not changed\n");
return madera_write_adsp_clk_setting(priv, dsp, freq);
} else {
dev_dbg(madera->dev, "DSP rate changed\n");
/* The write must be guarded by a number of SYSCLK cycles */
madera_spin_sysclk(priv);
ret = madera_write_adsp_clk_setting(priv, dsp, freq);
madera_spin_sysclk(priv);
return ret;
}
}
EXPORT_SYMBOL_GPL(madera_set_adsp_clk);
int madera_rate_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct madera_priv *priv = snd_soc_component_get_drvdata(component);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int item = ucontrol->value.enumerated.item[0];
unsigned int val;
int ret;
if (item >= e->items)
return -EINVAL;
/*
* Prevent the domain powering up while we're checking whether it's
* safe to change rate domain
*/
mutex_lock(&priv->rate_lock);
val = snd_soc_component_read(component, e->reg);
val >>= e->shift_l;
val &= e->mask;
if (snd_soc_enum_item_to_val(e, item) == val) {
ret = 0;
goto out;
}
if (!madera_can_change_grp_rate(priv, e->reg)) {
dev_warn(priv->madera->dev,
"Cannot change '%s' while in use by active audio paths\n",
kcontrol->id.name);
ret = -EBUSY;
} else {
/* The write must be guarded by a number of SYSCLK cycles */
madera_spin_sysclk(priv);
ret = snd_soc_put_enum_double(kcontrol, ucontrol);
madera_spin_sysclk(priv);
}
out:
mutex_unlock(&priv->rate_lock);
return ret;
}
EXPORT_SYMBOL_GPL(madera_rate_put);
static void madera_configure_input_mode(struct madera *madera)
{
unsigned int dig_mode, ana_mode_l, ana_mode_r;
int max_analogue_inputs, max_dmic_sup, i;
switch (madera->type) {
case CS47L15:
max_analogue_inputs = 1;
max_dmic_sup = 2;
break;
case CS47L35:
max_analogue_inputs = 2;
max_dmic_sup = 2;
break;
case CS47L85:
case WM1840:
max_analogue_inputs = 3;
max_dmic_sup = 3;
break;
case CS47L90:
case CS47L91:
max_analogue_inputs = 2;
max_dmic_sup = 2;
break;
default:
max_analogue_inputs = 2;
max_dmic_sup = 4;
break;
}
/*
* Initialize input modes from the A settings. For muxed inputs the
* B settings will be applied if the mux is changed
*/
for (i = 0; i < max_dmic_sup; i++) {
dev_dbg(madera->dev, "IN%d mode %u:%u:%u:%u\n", i + 1,
madera->pdata.codec.inmode[i][0],
madera->pdata.codec.inmode[i][1],
madera->pdata.codec.inmode[i][2],
madera->pdata.codec.inmode[i][3]);
dig_mode = madera->pdata.codec.dmic_ref[i] <<
MADERA_IN1_DMIC_SUP_SHIFT;
switch (madera->pdata.codec.inmode[i][0]) {
case MADERA_INMODE_DIFF:
ana_mode_l = 0;
break;
case MADERA_INMODE_SE:
ana_mode_l = 1 << MADERA_IN1L_SRC_SE_SHIFT;
break;
default:
dev_warn(madera->dev,
"IN%dAL Illegal inmode %u ignored\n",
i + 1, madera->pdata.codec.inmode[i][0]);
continue;
}
switch (madera->pdata.codec.inmode[i][1]) {
case MADERA_INMODE_DIFF:
ana_mode_r = 0;
break;
case MADERA_INMODE_SE:
ana_mode_r = 1 << MADERA_IN1R_SRC_SE_SHIFT;
break;
default:
dev_warn(madera->dev,
"IN%dAR Illegal inmode %u ignored\n",
i + 1, madera->pdata.codec.inmode[i][1]);
continue;
}
dev_dbg(madera->dev,
"IN%dA DMIC mode=0x%x Analogue mode=0x%x,0x%x\n",
i + 1, dig_mode, ana_mode_l, ana_mode_r);
regmap_update_bits(madera->regmap,
MADERA_IN1L_CONTROL + (i * 8),
MADERA_IN1_DMIC_SUP_MASK, dig_mode);
if (i >= max_analogue_inputs)
continue;
regmap_update_bits(madera->regmap,
MADERA_ADC_DIGITAL_VOLUME_1L + (i * 8),
MADERA_IN1L_SRC_SE_MASK, ana_mode_l);
regmap_update_bits(madera->regmap,
MADERA_ADC_DIGITAL_VOLUME_1R + (i * 8),
MADERA_IN1R_SRC_SE_MASK, ana_mode_r);
}
}
int madera_init_inputs(struct snd_soc_component *component)
{
struct madera_priv *priv = snd_soc_component_get_drvdata(component);
struct madera *madera = priv->madera;
madera_configure_input_mode(madera);
return 0;
}
EXPORT_SYMBOL_GPL(madera_init_inputs);
static const struct snd_soc_dapm_route madera_mono_routes[] = {
{ "OUT1R", NULL, "OUT1L" },
{ "OUT2R", NULL, "OUT2L" },
{ "OUT3R", NULL, "OUT3L" },
{ "OUT4R", NULL, "OUT4L" },
{ "OUT5R", NULL, "OUT5L" },
{ "OUT6R", NULL, "OUT6L" },
};
int madera_init_outputs(struct snd_soc_component *component,
const struct snd_soc_dapm_route *routes,
int n_mono_routes, int n_real)
{
struct snd_soc_dapm_context *dapm =
snd_soc_component_get_dapm(component);
struct madera_priv *priv = snd_soc_component_get_drvdata(component);
struct madera *madera = priv->madera;
const struct madera_codec_pdata *pdata = &madera->pdata.codec;
unsigned int val;
int i;
if (n_mono_routes > MADERA_MAX_OUTPUT) {
dev_warn(madera->dev,
"Requested %d mono outputs, using maximum allowed %d\n",
n_mono_routes, MADERA_MAX_OUTPUT);
n_mono_routes = MADERA_MAX_OUTPUT;
}
if (!routes)
routes = madera_mono_routes;
for (i = 0; i < n_mono_routes; i++) {
/* Default is 0 so noop with defaults */
if (pdata->out_mono[i]) {
val = MADERA_OUT1_MONO;
snd_soc_dapm_add_routes(dapm, &routes[i], 1);
} else {
val = 0;
}
if (i >= n_real)
continue;
regmap_update_bits(madera->regmap,
MADERA_OUTPUT_PATH_CONFIG_1L + (i * 8),
MADERA_OUT1_MONO, val);
dev_dbg(madera->dev, "OUT%d mono=0x%x\n", i + 1, val);
}
for (i = 0; i < MADERA_MAX_PDM_SPK; i++) {
dev_dbg(madera->dev, "PDM%d fmt=0x%x mute=0x%x\n", i + 1,
pdata->pdm_fmt[i], pdata->pdm_mute[i]);
if (pdata->pdm_mute[i])
regmap_update_bits(madera->regmap,
MADERA_PDM_SPK1_CTRL_1 + (i * 2),
MADERA_SPK1_MUTE_ENDIAN_MASK |
MADERA_SPK1_MUTE_SEQ1_MASK,
pdata->pdm_mute[i]);
if (pdata->pdm_fmt[i])
regmap_update_bits(madera->regmap,
MADERA_PDM_SPK1_CTRL_2 + (i * 2),
MADERA_SPK1_FMT_MASK,
pdata->pdm_fmt[i]);
}
return 0;
}
EXPORT_SYMBOL_GPL(madera_init_outputs);
int madera_init_bus_error_irq(struct madera_priv *priv, int dsp_num,
irq_handler_t handler)
{
struct madera *madera = priv->madera;
int ret;
ret = madera_request_irq(madera,
madera_dsp_bus_error_irqs[dsp_num],
"ADSP2 bus error",
handler,
&priv->adsp[dsp_num]);
if (ret)
dev_err(madera->dev,
"Failed to request DSP Lock region IRQ: %d\n", ret);
return ret;
}
EXPORT_SYMBOL_GPL(madera_init_bus_error_irq);
void madera_free_bus_error_irq(struct madera_priv *priv, int dsp_num)
{
struct madera *madera = priv->madera;
madera_free_irq(madera,
madera_dsp_bus_error_irqs[dsp_num],
&priv->adsp[dsp_num]);
}
EXPORT_SYMBOL_GPL(madera_free_bus_error_irq);
const char * const madera_mixer_texts[] = {
"None",
"Tone Generator 1",
"Tone Generator 2",
"Haptics",
"AEC1",
"AEC2",
"Mic Mute Mixer",
"Noise Generator",
"IN1L",
"IN1R",
"IN2L",
"IN2R",
"IN3L",
"IN3R",
"IN4L",
"IN4R",
"IN5L",
"IN5R",
"IN6L",
"IN6R",
"AIF1RX1",
"AIF1RX2",
"AIF1RX3",
"AIF1RX4",
"AIF1RX5",
"AIF1RX6",
"AIF1RX7",
"AIF1RX8",
"AIF2RX1",
"AIF2RX2",
"AIF2RX3",
"AIF2RX4",
"AIF2RX5",
"AIF2RX6",
"AIF2RX7",
"AIF2RX8",
"AIF3RX1",
"AIF3RX2",
"AIF3RX3",
"AIF3RX4",
"AIF4RX1",
"AIF4RX2",
"SLIMRX1",
"SLIMRX2",
"SLIMRX3",
"SLIMRX4",
"SLIMRX5",
"SLIMRX6",
"SLIMRX7",
"SLIMRX8",
"EQ1",
"EQ2",
"EQ3",
"EQ4",
"DRC1L",
"DRC1R",
"DRC2L",
"DRC2R",
"LHPF1",
"LHPF2",
"LHPF3",
"LHPF4",
"DSP1.1",
"DSP1.2",
"DSP1.3",
"DSP1.4",
"DSP1.5",
"DSP1.6",
"DSP2.1",
"DSP2.2",
"DSP2.3",
"DSP2.4",
"DSP2.5",
"DSP2.6",
"DSP3.1",
"DSP3.2",
"DSP3.3",
"DSP3.4",
"DSP3.5",
"DSP3.6",
"DSP4.1",
"DSP4.2",
"DSP4.3",
"DSP4.4",
"DSP4.5",
"DSP4.6",
"DSP5.1",
"DSP5.2",
"DSP5.3",
"DSP5.4",
"DSP5.5",
"DSP5.6",
"DSP6.1",
"DSP6.2",
"DSP6.3",
"DSP6.4",
"DSP6.5",
"DSP6.6",
"DSP7.1",
"DSP7.2",
"DSP7.3",
"DSP7.4",
"DSP7.5",
"DSP7.6",
"ASRC1IN1L",
"ASRC1IN1R",
"ASRC1IN2L",
"ASRC1IN2R",
"ASRC2IN1L",
"ASRC2IN1R",
"ASRC2IN2L",
"ASRC2IN2R",
"ISRC1INT1",
"ISRC1INT2",
"ISRC1INT3",
"ISRC1INT4",
"ISRC1DEC1",
"ISRC1DEC2",
"ISRC1DEC3",
"ISRC1DEC4",
"ISRC2INT1",
"ISRC2INT2",
"ISRC2INT3",
"ISRC2INT4",
"ISRC2DEC1",
"ISRC2DEC2",
"ISRC2DEC3",
"ISRC2DEC4",
"ISRC3INT1",
"ISRC3INT2",
"ISRC3INT3",
"ISRC3INT4",
"ISRC3DEC1",
"ISRC3DEC2",
"ISRC3DEC3",
"ISRC3DEC4",
"ISRC4INT1",
"ISRC4INT2",
"ISRC4DEC1",
"ISRC4DEC2",
"DFC1",
"DFC2",
"DFC3",
"DFC4",
"DFC5",
"DFC6",
"DFC7",
"DFC8",
};
EXPORT_SYMBOL_GPL(madera_mixer_texts);
const unsigned int madera_mixer_values[] = {
0x00, /* None */
0x04, /* Tone Generator 1 */
0x05, /* Tone Generator 2 */
0x06, /* Haptics */
0x08, /* AEC */
0x09, /* AEC2 */
0x0c, /* Noise mixer */
0x0d, /* Comfort noise */
0x10, /* IN1L */
0x11,
0x12,
0x13,
0x14,
0x15,
0x16,
0x17,
0x18,
0x19,
0x1A,
0x1B,
0x20, /* AIF1RX1 */
0x21,
0x22,
0x23,
0x24,
0x25,
0x26,
0x27,
0x28, /* AIF2RX1 */
0x29,
0x2a,
0x2b,
0x2c,
0x2d,
0x2e,
0x2f,
0x30, /* AIF3RX1 */
0x31,
0x32,
0x33,
0x34, /* AIF4RX1 */
0x35,
0x38, /* SLIMRX1 */
0x39,
0x3a,
0x3b,
0x3c,
0x3d,
0x3e,
0x3f,
0x50, /* EQ1 */
0x51,
0x52,
0x53,
0x58, /* DRC1L */
0x59,
0x5a,
0x5b,
0x60, /* LHPF1 */
0x61,
0x62,
0x63,
0x68, /* DSP1.1 */
0x69,
0x6a,
0x6b,
0x6c,
0x6d,
0x70, /* DSP2.1 */
0x71,
0x72,
0x73,
0x74,
0x75,
0x78, /* DSP3.1 */
0x79,
0x7a,
0x7b,
0x7c,
0x7d,
0x80, /* DSP4.1 */
0x81,
0x82,
0x83,
0x84,
0x85,
0x88, /* DSP5.1 */
0x89,
0x8a,
0x8b,
0x8c,
0x8d,
0xc0, /* DSP6.1 */
0xc1,
0xc2,
0xc3,
0xc4,
0xc5,
0xc8, /* DSP7.1 */
0xc9,
0xca,
0xcb,
0xcc,
0xcd,
0x90, /* ASRC1IN1L */
0x91,
0x92,
0x93,
0x94, /* ASRC2IN1L */
0x95,
0x96,
0x97,
0xa0, /* ISRC1INT1 */
0xa1,
0xa2,
0xa3,
0xa4, /* ISRC1DEC1 */
0xa5,
0xa6,
0xa7,
0xa8, /* ISRC2DEC1 */
0xa9,
0xaa,
0xab,
0xac, /* ISRC2INT1 */
0xad,
0xae,
0xaf,
0xb0, /* ISRC3DEC1 */
0xb1,
0xb2,
0xb3,
0xb4, /* ISRC3INT1 */
0xb5,
0xb6,
0xb7,
0xb8, /* ISRC4INT1 */
0xb9,
0xbc, /* ISRC4DEC1 */
0xbd,
0xf8, /* DFC1 */
0xf9,
0xfa,
0xfb,
0xfc,
0xfd,
0xfe,
0xff, /* DFC8 */
};
EXPORT_SYMBOL_GPL(madera_mixer_values);
const DECLARE_TLV_DB_SCALE(madera_ana_tlv, 0, 100, 0);
EXPORT_SYMBOL_GPL(madera_ana_tlv);
const DECLARE_TLV_DB_SCALE(madera_eq_tlv, -1200, 100, 0);
EXPORT_SYMBOL_GPL(madera_eq_tlv);
const DECLARE_TLV_DB_SCALE(madera_digital_tlv, -6400, 50, 0);
EXPORT_SYMBOL_GPL(madera_digital_tlv);
const DECLARE_TLV_DB_SCALE(madera_noise_tlv, -13200, 600, 0);
EXPORT_SYMBOL_GPL(madera_noise_tlv);
const DECLARE_TLV_DB_SCALE(madera_ng_tlv, -12000, 600, 0);
EXPORT_SYMBOL_GPL(madera_ng_tlv);
const DECLARE_TLV_DB_SCALE(madera_mixer_tlv, -3200, 100, 0);
EXPORT_SYMBOL_GPL(madera_mixer_tlv);
const char * const madera_rate_text[MADERA_RATE_ENUM_SIZE] = {
"SYNCCLK rate 1", "SYNCCLK rate 2", "SYNCCLK rate 3",
"ASYNCCLK rate 1", "ASYNCCLK rate 2",
};
EXPORT_SYMBOL_GPL(madera_rate_text);
const unsigned int madera_rate_val[MADERA_RATE_ENUM_SIZE] = {
0x0, 0x1, 0x2, 0x8, 0x9,
};
EXPORT_SYMBOL_GPL(madera_rate_val);
static const char * const madera_dfc_width_text[MADERA_DFC_WIDTH_ENUM_SIZE] = {
"8 bit", "16 bit", "20 bit", "24 bit", "32 bit",
};
static const unsigned int madera_dfc_width_val[MADERA_DFC_WIDTH_ENUM_SIZE] = {
7, 15, 19, 23, 31,
};
static const char * const madera_dfc_type_text[MADERA_DFC_TYPE_ENUM_SIZE] = {
"Fixed", "Unsigned Fixed", "Single Precision Floating",
"Half Precision Floating", "Arm Alternative Floating",
};
static const unsigned int madera_dfc_type_val[MADERA_DFC_TYPE_ENUM_SIZE] = {
0, 1, 2, 4, 5,
};
const struct soc_enum madera_dfc_width[] = {
SOC_VALUE_ENUM_SINGLE(MADERA_DFC1_RX,
MADERA_DFC1_RX_DATA_WIDTH_SHIFT,
MADERA_DFC1_RX_DATA_WIDTH_MASK >>
MADERA_DFC1_RX_DATA_WIDTH_SHIFT,
ARRAY_SIZE(madera_dfc_width_text),
madera_dfc_width_text,
madera_dfc_width_val),
SOC_VALUE_ENUM_SINGLE(MADERA_DFC1_TX,
MADERA_DFC1_TX_DATA_WIDTH_SHIFT,
MADERA_DFC1_TX_DATA_WIDTH_MASK >>
MADERA_DFC1_TX_DATA_WIDTH_SHIFT,
ARRAY_SIZE(madera_dfc_width_text),
madera_dfc_width_text,
madera_dfc_width_val),
SOC_VALUE_ENUM_SINGLE(MADERA_DFC2_RX,
MADERA_DFC1_RX_DATA_WIDTH_SHIFT,
MADERA_DFC1_RX_DATA_WIDTH_MASK >>
MADERA_DFC1_RX_DATA_WIDTH_SHIFT,
ARRAY_SIZE(madera_dfc_width_text),
madera_dfc_width_text,
madera_dfc_width_val),
SOC_VALUE_ENUM_SINGLE(MADERA_DFC2_TX,
MADERA_DFC1_TX_DATA_WIDTH_SHIFT,
MADERA_DFC1_TX_DATA_WIDTH_MASK >>
MADERA_DFC1_TX_DATA_WIDTH_SHIFT,
ARRAY_SIZE(madera_dfc_width_text),
madera_dfc_width_text,
madera_dfc_width_val),
SOC_VALUE_ENUM_SINGLE(MADERA_DFC3_RX,
MADERA_DFC1_RX_DATA_WIDTH_SHIFT,
MADERA_DFC1_RX_DATA_WIDTH_MASK >>
MADERA_DFC1_RX_DATA_WIDTH_SHIFT,
ARRAY_SIZE(madera_dfc_width_text),
madera_dfc_width_text,
madera_dfc_width_val),
SOC_VALUE_ENUM_SINGLE(MADERA_DFC3_TX,
MADERA_DFC1_TX_DATA_WIDTH_SHIFT,
MADERA_DFC1_TX_DATA_WIDTH_MASK >>
MADERA_DFC1_TX_DATA_WIDTH_SHIFT,
ARRAY_SIZE(madera_dfc_width_text),
madera_dfc_width_text,
madera_dfc_width_val),
SOC_VALUE_ENUM_SINGLE(MADERA_DFC4_RX,
MADERA_DFC1_RX_DATA_WIDTH_SHIFT,
MADERA_DFC1_RX_DATA_WIDTH_MASK >>
MADERA_DFC1_RX_DATA_WIDTH_SHIFT,
ARRAY_SIZE(madera_dfc_width_text),
madera_dfc_width_text,
madera_dfc_width_val),
SOC_VALUE_ENUM_SINGLE(MADERA_DFC4_TX,
MADERA_DFC1_TX_DATA_WIDTH_SHIFT,
MADERA_DFC1_TX_DATA_WIDTH_MASK >>
MADERA_DFC1_TX_DATA_WIDTH_SHIFT,
ARRAY_SIZE(madera_dfc_width_text),
madera_dfc_width_text,
madera_dfc_width_val),
SOC_VALUE_ENUM_SINGLE(MADERA_DFC5_RX,
MADERA_DFC1_RX_DATA_WIDTH_SHIFT,
MADERA_DFC1_RX_DATA_WIDTH_MASK >>
MADERA_DFC1_RX_DATA_WIDTH_SHIFT,
ARRAY_SIZE(madera_dfc_width_text),
madera_dfc_width_text,
madera_dfc_width_val),
SOC_VALUE_ENUM_SINGLE(MADERA_DFC5_TX,
MADERA_DFC1_TX_DATA_WIDTH_SHIFT,
MADERA_DFC1_TX_DATA_WIDTH_MASK >>
MADERA_DFC1_TX_DATA_WIDTH_SHIFT,
ARRAY_SIZE(madera_dfc_width_text),
madera_dfc_width_text,
madera_dfc_width_val),
SOC_VALUE_ENUM_SINGLE(MADERA_DFC6_RX,
MADERA_DFC1_RX_DATA_WIDTH_SHIFT,
MADERA_DFC1_RX_DATA_WIDTH_MASK >>
MADERA_DFC1_RX_DATA_WIDTH_SHIFT,
ARRAY_SIZE(madera_dfc_width_text),
madera_dfc_width_text,
madera_dfc_width_val),
SOC_VALUE_ENUM_SINGLE(MADERA_DFC6_TX,
MADERA_DFC1_TX_DATA_WIDTH_SHIFT,
MADERA_DFC1_TX_DATA_WIDTH_MASK >>
MADERA_DFC1_TX_DATA_WIDTH_SHIFT,
ARRAY_SIZE(madera_dfc_width_text),
madera_dfc_width_text,
madera_dfc_width_val),
SOC_VALUE_ENUM_SINGLE(MADERA_DFC7_RX,
MADERA_DFC1_RX_DATA_WIDTH_SHIFT,
MADERA_DFC1_RX_DATA_WIDTH_MASK >>
MADERA_DFC1_RX_DATA_WIDTH_SHIFT,
ARRAY_SIZE(madera_dfc_width_text),
madera_dfc_width_text,
madera_dfc_width_val),
SOC_VALUE_ENUM_SINGLE(MADERA_DFC7_TX,
MADERA_DFC1_TX_DATA_WIDTH_SHIFT,
MADERA_DFC1_TX_DATA_WIDTH_MASK >>
MADERA_DFC1_TX_DATA_WIDTH_SHIFT,
ARRAY_SIZE(madera_dfc_width_text),
madera_dfc_width_text,
madera_dfc_width_val),
SOC_VALUE_ENUM_SINGLE(MADERA_DFC8_RX,
MADERA_DFC1_RX_DATA_WIDTH_SHIFT,
MADERA_DFC1_RX_DATA_WIDTH_MASK >>
MADERA_DFC1_RX_DATA_WIDTH_SHIFT,
ARRAY_SIZE(madera_dfc_width_text),
madera_dfc_width_text,
madera_dfc_width_val),
SOC_VALUE_ENUM_SINGLE(MADERA_DFC8_TX,
MADERA_DFC1_TX_DATA_WIDTH_SHIFT,
MADERA_DFC1_TX_DATA_WIDTH_MASK >>
MADERA_DFC1_TX_DATA_WIDTH_SHIFT,
ARRAY_SIZE(madera_dfc_width_text),
madera_dfc_width_text,
madera_dfc_width_val),
};
EXPORT_SYMBOL_GPL(madera_dfc_width);
const struct soc_enum madera_dfc_type[] = {
SOC_VALUE_ENUM_SINGLE(MADERA_DFC1_RX,
MADERA_DFC1_RX_DATA_TYPE_SHIFT,
MADERA_DFC1_RX_DATA_TYPE_MASK >>
MADERA_DFC1_RX_DATA_TYPE_SHIFT,
ARRAY_SIZE(madera_dfc_type_text),
madera_dfc_type_text,
madera_dfc_type_val),
SOC_VALUE_ENUM_SINGLE(MADERA_DFC1_TX,
MADERA_DFC1_TX_DATA_TYPE_SHIFT,
MADERA_DFC1_TX_DATA_TYPE_MASK >>
MADERA_DFC1_TX_DATA_TYPE_SHIFT,
ARRAY_SIZE(madera_dfc_type_text),
madera_dfc_type_text,
madera_dfc_type_val),
SOC_VALUE_ENUM_SINGLE(MADERA_DFC2_RX,
MADERA_DFC1_RX_DATA_TYPE_SHIFT,
MADERA_DFC1_RX_DATA_TYPE_MASK >>
MADERA_DFC1_RX_DATA_TYPE_SHIFT,
ARRAY_SIZE(madera_dfc_type_text),
madera_dfc_type_text,
madera_dfc_type_val),
SOC_VALUE_ENUM_SINGLE(MADERA_DFC2_TX,
MADERA_DFC1_TX_DATA_TYPE_SHIFT,
MADERA_DFC1_TX_DATA_TYPE_MASK >>
MADERA_DFC1_TX_DATA_TYPE_SHIFT,
ARRAY_SIZE(madera_dfc_type_text),
madera_dfc_type_text,
madera_dfc_type_val),
SOC_VALUE_ENUM_SINGLE(MADERA_DFC3_RX,
MADERA_DFC1_RX_DATA_TYPE_SHIFT,
MADERA_DFC1_RX_DATA_TYPE_MASK >>
MADERA_DFC1_RX_DATA_TYPE_SHIFT,
ARRAY_SIZE(madera_dfc_type_text),
madera_dfc_type_text,
madera_dfc_type_val),
SOC_VALUE_ENUM_SINGLE(MADERA_DFC3_TX,
MADERA_DFC1_TX_DATA_TYPE_SHIFT,
MADERA_DFC1_TX_DATA_TYPE_MASK >>
MADERA_DFC1_TX_DATA_TYPE_SHIFT,
ARRAY_SIZE(madera_dfc_type_text),
madera_dfc_type_text,
madera_dfc_type_val),
SOC_VALUE_ENUM_SINGLE(MADERA_DFC4_RX,
MADERA_DFC1_RX_DATA_TYPE_SHIFT,
MADERA_DFC1_RX_DATA_TYPE_MASK >>
MADERA_DFC1_RX_DATA_TYPE_SHIFT,
ARRAY_SIZE(madera_dfc_type_text),
madera_dfc_type_text,
madera_dfc_type_val),
SOC_VALUE_ENUM_SINGLE(MADERA_DFC4_TX,
MADERA_DFC1_TX_DATA_TYPE_SHIFT,
MADERA_DFC1_TX_DATA_TYPE_MASK >>
MADERA_DFC1_TX_DATA_TYPE_SHIFT,
ARRAY_SIZE(madera_dfc_type_text),
madera_dfc_type_text,
madera_dfc_type_val),
SOC_VALUE_ENUM_SINGLE(MADERA_DFC5_RX,
MADERA_DFC1_RX_DATA_TYPE_SHIFT,
MADERA_DFC1_RX_DATA_TYPE_MASK >>
MADERA_DFC1_RX_DATA_TYPE_SHIFT,
ARRAY_SIZE(madera_dfc_type_text),
madera_dfc_type_text,
madera_dfc_type_val),
SOC_VALUE_ENUM_SINGLE(MADERA_DFC5_TX,
MADERA_DFC1_TX_DATA_TYPE_SHIFT,
MADERA_DFC1_TX_DATA_TYPE_MASK >>
MADERA_DFC1_TX_DATA_TYPE_SHIFT,
ARRAY_SIZE(madera_dfc_type_text),
madera_dfc_type_text,
madera_dfc_type_val),
SOC_VALUE_ENUM_SINGLE(MADERA_DFC6_RX,
MADERA_DFC1_RX_DATA_TYPE_SHIFT,
MADERA_DFC1_RX_DATA_TYPE_MASK >>
MADERA_DFC1_RX_DATA_TYPE_SHIFT,
ARRAY_SIZE(madera_dfc_type_text),
madera_dfc_type_text,
madera_dfc_type_val),
SOC_VALUE_ENUM_SINGLE(MADERA_DFC6_TX,
MADERA_DFC1_TX_DATA_TYPE_SHIFT,
MADERA_DFC1_TX_DATA_TYPE_MASK >>
MADERA_DFC1_TX_DATA_TYPE_SHIFT,
ARRAY_SIZE(madera_dfc_type_text),
madera_dfc_type_text,
madera_dfc_type_val),
SOC_VALUE_ENUM_SINGLE(MADERA_DFC7_RX,
MADERA_DFC1_RX_DATA_TYPE_SHIFT,
MADERA_DFC1_RX_DATA_TYPE_MASK >>
MADERA_DFC1_RX_DATA_TYPE_SHIFT,
ARRAY_SIZE(madera_dfc_type_text),
madera_dfc_type_text,
madera_dfc_type_val),
SOC_VALUE_ENUM_SINGLE(MADERA_DFC7_TX,
MADERA_DFC1_TX_DATA_TYPE_SHIFT,
MADERA_DFC1_TX_DATA_TYPE_MASK >>
MADERA_DFC1_TX_DATA_TYPE_SHIFT,
ARRAY_SIZE(madera_dfc_type_text),
madera_dfc_type_text,
madera_dfc_type_val),
SOC_VALUE_ENUM_SINGLE(MADERA_DFC8_RX,
MADERA_DFC1_RX_DATA_TYPE_SHIFT,
MADERA_DFC1_RX_DATA_TYPE_MASK >>
MADERA_DFC1_RX_DATA_TYPE_SHIFT,
ARRAY_SIZE(madera_dfc_type_text),
madera_dfc_type_text,
madera_dfc_type_val),
SOC_VALUE_ENUM_SINGLE(MADERA_DFC8_TX,
MADERA_DFC1_TX_DATA_TYPE_SHIFT,
MADERA_DFC1_TX_DATA_TYPE_MASK >>
MADERA_DFC1_TX_DATA_TYPE_SHIFT,
ARRAY_SIZE(madera_dfc_type_text),
madera_dfc_type_text,
madera_dfc_type_val),
};
EXPORT_SYMBOL_GPL(madera_dfc_type);
const struct soc_enum madera_isrc_fsh[] = {
SOC_VALUE_ENUM_SINGLE(MADERA_ISRC_1_CTRL_1,
MADERA_ISRC1_FSH_SHIFT, 0xf,
MADERA_RATE_ENUM_SIZE,
madera_rate_text, madera_rate_val),
SOC_VALUE_ENUM_SINGLE(MADERA_ISRC_2_CTRL_1,
MADERA_ISRC2_FSH_SHIFT, 0xf,
MADERA_RATE_ENUM_SIZE,
madera_rate_text, madera_rate_val),
SOC_VALUE_ENUM_SINGLE(MADERA_ISRC_3_CTRL_1,
MADERA_ISRC3_FSH_SHIFT, 0xf,
MADERA_RATE_ENUM_SIZE,
madera_rate_text, madera_rate_val),
SOC_VALUE_ENUM_SINGLE(MADERA_ISRC_4_CTRL_1,
MADERA_ISRC4_FSH_SHIFT, 0xf,
MADERA_RATE_ENUM_SIZE,
madera_rate_text, madera_rate_val),
};
EXPORT_SYMBOL_GPL(madera_isrc_fsh);
const struct soc_enum madera_isrc_fsl[] = {
SOC_VALUE_ENUM_SINGLE(MADERA_ISRC_1_CTRL_2,
MADERA_ISRC1_FSL_SHIFT, 0xf,
MADERA_RATE_ENUM_SIZE,
madera_rate_text, madera_rate_val),
SOC_VALUE_ENUM_SINGLE(MADERA_ISRC_2_CTRL_2,
MADERA_ISRC2_FSL_SHIFT, 0xf,
MADERA_RATE_ENUM_SIZE,
madera_rate_text, madera_rate_val),
SOC_VALUE_ENUM_SINGLE(MADERA_ISRC_3_CTRL_2,
MADERA_ISRC3_FSL_SHIFT, 0xf,
MADERA_RATE_ENUM_SIZE,
madera_rate_text, madera_rate_val),
SOC_VALUE_ENUM_SINGLE(MADERA_ISRC_4_CTRL_2,
MADERA_ISRC4_FSL_SHIFT, 0xf,
MADERA_RATE_ENUM_SIZE,
madera_rate_text, madera_rate_val),
};
EXPORT_SYMBOL_GPL(madera_isrc_fsl);
const struct soc_enum madera_asrc1_rate[] = {
SOC_VALUE_ENUM_SINGLE(MADERA_ASRC1_RATE1,
MADERA_ASRC1_RATE1_SHIFT, 0xf,
MADERA_SYNC_RATE_ENUM_SIZE,
madera_rate_text, madera_rate_val),
SOC_VALUE_ENUM_SINGLE(MADERA_ASRC1_RATE2,
MADERA_ASRC1_RATE1_SHIFT, 0xf,
MADERA_ASYNC_RATE_ENUM_SIZE,
madera_rate_text + MADERA_SYNC_RATE_ENUM_SIZE,
madera_rate_val + MADERA_SYNC_RATE_ENUM_SIZE),
};
EXPORT_SYMBOL_GPL(madera_asrc1_rate);
const struct soc_enum madera_asrc1_bidir_rate[] = {
SOC_VALUE_ENUM_SINGLE(MADERA_ASRC1_RATE1,
MADERA_ASRC1_RATE1_SHIFT, 0xf,
MADERA_RATE_ENUM_SIZE,
madera_rate_text, madera_rate_val),
SOC_VALUE_ENUM_SINGLE(MADERA_ASRC1_RATE2,
MADERA_ASRC1_RATE2_SHIFT, 0xf,
MADERA_RATE_ENUM_SIZE,
madera_rate_text, madera_rate_val),
};
EXPORT_SYMBOL_GPL(madera_asrc1_bidir_rate);
const struct soc_enum madera_asrc2_rate[] = {
SOC_VALUE_ENUM_SINGLE(MADERA_ASRC2_RATE1,
MADERA_ASRC2_RATE1_SHIFT, 0xf,
MADERA_SYNC_RATE_ENUM_SIZE,
madera_rate_text, madera_rate_val),
SOC_VALUE_ENUM_SINGLE(MADERA_ASRC2_RATE2,
MADERA_ASRC2_RATE2_SHIFT, 0xf,
MADERA_ASYNC_RATE_ENUM_SIZE,
madera_rate_text + MADERA_SYNC_RATE_ENUM_SIZE,
madera_rate_val + MADERA_SYNC_RATE_ENUM_SIZE),
};
EXPORT_SYMBOL_GPL(madera_asrc2_rate);
static const char * const madera_vol_ramp_text[] = {
"0ms/6dB", "0.5ms/6dB", "1ms/6dB", "2ms/6dB", "4ms/6dB", "8ms/6dB",
"15ms/6dB", "30ms/6dB",
};
SOC_ENUM_SINGLE_DECL(madera_in_vd_ramp,
MADERA_INPUT_VOLUME_RAMP,
MADERA_IN_VD_RAMP_SHIFT,
madera_vol_ramp_text);
EXPORT_SYMBOL_GPL(madera_in_vd_ramp);
SOC_ENUM_SINGLE_DECL(madera_in_vi_ramp,
MADERA_INPUT_VOLUME_RAMP,
MADERA_IN_VI_RAMP_SHIFT,
madera_vol_ramp_text);
EXPORT_SYMBOL_GPL(madera_in_vi_ramp);
SOC_ENUM_SINGLE_DECL(madera_out_vd_ramp,
MADERA_OUTPUT_VOLUME_RAMP,
MADERA_OUT_VD_RAMP_SHIFT,
madera_vol_ramp_text);
EXPORT_SYMBOL_GPL(madera_out_vd_ramp);
SOC_ENUM_SINGLE_DECL(madera_out_vi_ramp,
MADERA_OUTPUT_VOLUME_RAMP,
MADERA_OUT_VI_RAMP_SHIFT,
madera_vol_ramp_text);
EXPORT_SYMBOL_GPL(madera_out_vi_ramp);
static const char * const madera_lhpf_mode_text[] = {
"Low-pass", "High-pass"
};
SOC_ENUM_SINGLE_DECL(madera_lhpf1_mode,
MADERA_HPLPF1_1,
MADERA_LHPF1_MODE_SHIFT,
madera_lhpf_mode_text);
EXPORT_SYMBOL_GPL(madera_lhpf1_mode);
SOC_ENUM_SINGLE_DECL(madera_lhpf2_mode,
MADERA_HPLPF2_1,
MADERA_LHPF2_MODE_SHIFT,
madera_lhpf_mode_text);
EXPORT_SYMBOL_GPL(madera_lhpf2_mode);
SOC_ENUM_SINGLE_DECL(madera_lhpf3_mode,
MADERA_HPLPF3_1,
MADERA_LHPF3_MODE_SHIFT,
madera_lhpf_mode_text);
EXPORT_SYMBOL_GPL(madera_lhpf3_mode);
SOC_ENUM_SINGLE_DECL(madera_lhpf4_mode,
MADERA_HPLPF4_1,
MADERA_LHPF4_MODE_SHIFT,
madera_lhpf_mode_text);
EXPORT_SYMBOL_GPL(madera_lhpf4_mode);
static const char * const madera_ng_hold_text[] = {
"30ms", "120ms", "250ms", "500ms",
};
SOC_ENUM_SINGLE_DECL(madera_ng_hold,
MADERA_NOISE_GATE_CONTROL,
MADERA_NGATE_HOLD_SHIFT,
madera_ng_hold_text);
EXPORT_SYMBOL_GPL(madera_ng_hold);
static const char * const madera_in_hpf_cut_text[] = {
"2.5Hz", "5Hz", "10Hz", "20Hz", "40Hz"
};
SOC_ENUM_SINGLE_DECL(madera_in_hpf_cut_enum,
MADERA_HPF_CONTROL,
MADERA_IN_HPF_CUT_SHIFT,
madera_in_hpf_cut_text);
EXPORT_SYMBOL_GPL(madera_in_hpf_cut_enum);
static const char * const madera_in_dmic_osr_text[MADERA_OSR_ENUM_SIZE] = {
"384kHz", "768kHz", "1.536MHz", "3.072MHz", "6.144MHz",
};
static const unsigned int madera_in_dmic_osr_val[MADERA_OSR_ENUM_SIZE] = {
2, 3, 4, 5, 6,
};
const struct soc_enum madera_in_dmic_osr[] = {
SOC_VALUE_ENUM_SINGLE(MADERA_DMIC1L_CONTROL, MADERA_IN1_OSR_SHIFT,
0x7, MADERA_OSR_ENUM_SIZE,
madera_in_dmic_osr_text, madera_in_dmic_osr_val),
SOC_VALUE_ENUM_SINGLE(MADERA_DMIC2L_CONTROL, MADERA_IN2_OSR_SHIFT,
0x7, MADERA_OSR_ENUM_SIZE,
madera_in_dmic_osr_text, madera_in_dmic_osr_val),
SOC_VALUE_ENUM_SINGLE(MADERA_DMIC3L_CONTROL, MADERA_IN3_OSR_SHIFT,
0x7, MADERA_OSR_ENUM_SIZE,
madera_in_dmic_osr_text, madera_in_dmic_osr_val),
SOC_VALUE_ENUM_SINGLE(MADERA_DMIC4L_CONTROL, MADERA_IN4_OSR_SHIFT,
0x7, MADERA_OSR_ENUM_SIZE,
madera_in_dmic_osr_text, madera_in_dmic_osr_val),
SOC_VALUE_ENUM_SINGLE(MADERA_DMIC5L_CONTROL, MADERA_IN5_OSR_SHIFT,
0x7, MADERA_OSR_ENUM_SIZE,
madera_in_dmic_osr_text, madera_in_dmic_osr_val),
SOC_VALUE_ENUM_SINGLE(MADERA_DMIC6L_CONTROL, MADERA_IN6_OSR_SHIFT,
0x7, MADERA_OSR_ENUM_SIZE,
madera_in_dmic_osr_text, madera_in_dmic_osr_val),
};
EXPORT_SYMBOL_GPL(madera_in_dmic_osr);
static const char * const madera_anc_input_src_text[] = {
"None", "IN1", "IN2", "IN3", "IN4", "IN5", "IN6",
};
static const char * const madera_anc_channel_src_text[] = {
"None", "Left", "Right", "Combine",
};
const struct soc_enum madera_anc_input_src[] = {
SOC_ENUM_SINGLE(MADERA_ANC_SRC,
MADERA_IN_RXANCL_SEL_SHIFT,
ARRAY_SIZE(madera_anc_input_src_text),
madera_anc_input_src_text),
SOC_ENUM_SINGLE(MADERA_FCL_ADC_REFORMATTER_CONTROL,
MADERA_FCL_MIC_MODE_SEL_SHIFT,
ARRAY_SIZE(madera_anc_channel_src_text),
madera_anc_channel_src_text),
SOC_ENUM_SINGLE(MADERA_ANC_SRC,
MADERA_IN_RXANCR_SEL_SHIFT,
ARRAY_SIZE(madera_anc_input_src_text),
madera_anc_input_src_text),
SOC_ENUM_SINGLE(MADERA_FCR_ADC_REFORMATTER_CONTROL,
MADERA_FCR_MIC_MODE_SEL_SHIFT,
ARRAY_SIZE(madera_anc_channel_src_text),
madera_anc_channel_src_text),
};
EXPORT_SYMBOL_GPL(madera_anc_input_src);
static const char * const madera_anc_ng_texts[] = {
"None", "Internal", "External",
};
SOC_ENUM_SINGLE_DECL(madera_anc_ng_enum, SND_SOC_NOPM, 0, madera_anc_ng_texts);
EXPORT_SYMBOL_GPL(madera_anc_ng_enum);
static const char * const madera_out_anc_src_text[] = {
"None", "RXANCL", "RXANCR",
};
const struct soc_enum madera_output_anc_src[] = {
SOC_ENUM_SINGLE(MADERA_OUTPUT_PATH_CONFIG_1L,
MADERA_OUT1L_ANC_SRC_SHIFT,
ARRAY_SIZE(madera_out_anc_src_text),
madera_out_anc_src_text),
SOC_ENUM_SINGLE(MADERA_OUTPUT_PATH_CONFIG_1R,
MADERA_OUT1R_ANC_SRC_SHIFT,
ARRAY_SIZE(madera_out_anc_src_text),
madera_out_anc_src_text),
SOC_ENUM_SINGLE(MADERA_OUTPUT_PATH_CONFIG_2L,
MADERA_OUT2L_ANC_SRC_SHIFT,
ARRAY_SIZE(madera_out_anc_src_text),
madera_out_anc_src_text),
SOC_ENUM_SINGLE(MADERA_OUTPUT_PATH_CONFIG_2R,
MADERA_OUT2R_ANC_SRC_SHIFT,
ARRAY_SIZE(madera_out_anc_src_text),
madera_out_anc_src_text),
SOC_ENUM_SINGLE(MADERA_OUTPUT_PATH_CONFIG_3L,
MADERA_OUT3L_ANC_SRC_SHIFT,
ARRAY_SIZE(madera_out_anc_src_text),
madera_out_anc_src_text),
SOC_ENUM_SINGLE(MADERA_OUTPUT_PATH_CONFIG_3R,
MADERA_OUT3R_ANC_SRC_SHIFT,
ARRAY_SIZE(madera_out_anc_src_text),
madera_out_anc_src_text),
SOC_ENUM_SINGLE(MADERA_OUTPUT_PATH_CONFIG_4L,
MADERA_OUT4L_ANC_SRC_SHIFT,
ARRAY_SIZE(madera_out_anc_src_text),
madera_out_anc_src_text),
SOC_ENUM_SINGLE(MADERA_OUTPUT_PATH_CONFIG_4R,
MADERA_OUT4R_ANC_SRC_SHIFT,
ARRAY_SIZE(madera_out_anc_src_text),
madera_out_anc_src_text),
SOC_ENUM_SINGLE(MADERA_OUTPUT_PATH_CONFIG_5L,
MADERA_OUT5L_ANC_SRC_SHIFT,
ARRAY_SIZE(madera_out_anc_src_text),
madera_out_anc_src_text),
SOC_ENUM_SINGLE(MADERA_OUTPUT_PATH_CONFIG_5R,
MADERA_OUT5R_ANC_SRC_SHIFT,
ARRAY_SIZE(madera_out_anc_src_text),
madera_out_anc_src_text),
SOC_ENUM_SINGLE(MADERA_OUTPUT_PATH_CONFIG_6L,
MADERA_OUT6L_ANC_SRC_SHIFT,
ARRAY_SIZE(madera_out_anc_src_text),
madera_out_anc_src_text),
SOC_ENUM_SINGLE(MADERA_OUTPUT_PATH_CONFIG_6R,
MADERA_OUT6R_ANC_SRC_SHIFT,
ARRAY_SIZE(madera_out_anc_src_text),
madera_out_anc_src_text),
};
EXPORT_SYMBOL_GPL(madera_output_anc_src);
int madera_dfc_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct snd_soc_dapm_context *dapm =
snd_soc_component_get_dapm(component);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int reg = e->reg;
unsigned int val;
int ret = 0;
reg = ((reg / 6) * 6) - 2;
snd_soc_dapm_mutex_lock(dapm);
val = snd_soc_component_read(component, reg);
if (val & MADERA_DFC1_ENA) {
ret = -EBUSY;
dev_err(component->dev, "Can't change mode on an active DFC\n");
goto exit;
}
ret = snd_soc_put_enum_double(kcontrol, ucontrol);
exit:
snd_soc_dapm_mutex_unlock(dapm);
return ret;
}
EXPORT_SYMBOL_GPL(madera_dfc_put);
int madera_lp_mode_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct snd_soc_dapm_context *dapm =
snd_soc_component_get_dapm(component);
unsigned int val, mask;
int ret;
snd_soc_dapm_mutex_lock(dapm);
/* Cannot change lp mode on an active input */
val = snd_soc_component_read(component, MADERA_INPUT_ENABLES);
mask = (mc->reg - MADERA_ADC_DIGITAL_VOLUME_1L) / 4;
mask ^= 0x1; /* Flip bottom bit for channel order */
if (val & (1 << mask)) {
ret = -EBUSY;
dev_err(component->dev,
"Can't change lp mode on an active input\n");
goto exit;
}
ret = snd_soc_put_volsw(kcontrol, ucontrol);
exit:
snd_soc_dapm_mutex_unlock(dapm);
return ret;
}
EXPORT_SYMBOL_GPL(madera_lp_mode_put);
const struct snd_kcontrol_new madera_dsp_trigger_output_mux[] = {
SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0),
SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0),
SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0),
SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0),
SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0),
SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0),
SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0),
};
EXPORT_SYMBOL_GPL(madera_dsp_trigger_output_mux);
const struct snd_kcontrol_new madera_drc_activity_output_mux[] = {
SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0),
SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0),
};
EXPORT_SYMBOL_GPL(madera_drc_activity_output_mux);
static void madera_in_set_vu(struct madera_priv *priv, bool enable)
{
unsigned int val;
int i, ret;
if (enable)
val = MADERA_IN_VU;
else
val = 0;
for (i = 0; i < priv->num_inputs; i++) {
ret = regmap_update_bits(priv->madera->regmap,
MADERA_ADC_DIGITAL_VOLUME_1L + (i * 4),
MADERA_IN_VU, val);
if (ret)
dev_warn(priv->madera->dev,
"Failed to modify VU bits: %d\n", ret);
}
}
int madera_in_ev(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct madera_priv *priv = snd_soc_component_get_drvdata(component);
unsigned int reg, val;
if (w->shift % 2)
reg = MADERA_ADC_DIGITAL_VOLUME_1L + ((w->shift / 2) * 8);
else
reg = MADERA_ADC_DIGITAL_VOLUME_1R + ((w->shift / 2) * 8);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
priv->in_pending++;
break;
case SND_SOC_DAPM_POST_PMU:
priv->in_pending--;
snd_soc_component_update_bits(component, reg,
MADERA_IN1L_MUTE, 0);
/* If this is the last input pending then allow VU */
if (priv->in_pending == 0) {
usleep_range(1000, 3000);
madera_in_set_vu(priv, true);
}
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, reg,
MADERA_IN1L_MUTE | MADERA_IN_VU,
MADERA_IN1L_MUTE | MADERA_IN_VU);
break;
case SND_SOC_DAPM_POST_PMD:
/* Disable volume updates if no inputs are enabled */
val = snd_soc_component_read(component, MADERA_INPUT_ENABLES);
if (!val)
madera_in_set_vu(priv, false);
break;
default:
break;
}
return 0;
}
EXPORT_SYMBOL_GPL(madera_in_ev);
int madera_out_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct madera_priv *priv = snd_soc_component_get_drvdata(component);
struct madera *madera = priv->madera;
int out_up_delay;
switch (madera->type) {
case CS47L90:
case CS47L91:
case CS42L92:
case CS47L92:
case CS47L93:
out_up_delay = 6;
break;
default:
out_up_delay = 17;
break;
}
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
switch (w->shift) {
case MADERA_OUT1L_ENA_SHIFT:
case MADERA_OUT1R_ENA_SHIFT:
case MADERA_OUT2L_ENA_SHIFT:
case MADERA_OUT2R_ENA_SHIFT:
case MADERA_OUT3L_ENA_SHIFT:
case MADERA_OUT3R_ENA_SHIFT:
priv->out_up_pending++;
priv->out_up_delay += out_up_delay;
break;
default:
break;
}
break;
case SND_SOC_DAPM_POST_PMU:
switch (w->shift) {
case MADERA_OUT1L_ENA_SHIFT:
case MADERA_OUT1R_ENA_SHIFT:
case MADERA_OUT2L_ENA_SHIFT:
case MADERA_OUT2R_ENA_SHIFT:
case MADERA_OUT3L_ENA_SHIFT:
case MADERA_OUT3R_ENA_SHIFT:
priv->out_up_pending--;
if (!priv->out_up_pending) {
msleep(priv->out_up_delay);
priv->out_up_delay = 0;
}
break;
default:
break;
}
break;
case SND_SOC_DAPM_PRE_PMD:
switch (w->shift) {
case MADERA_OUT1L_ENA_SHIFT:
case MADERA_OUT1R_ENA_SHIFT:
case MADERA_OUT2L_ENA_SHIFT:
case MADERA_OUT2R_ENA_SHIFT:
case MADERA_OUT3L_ENA_SHIFT:
case MADERA_OUT3R_ENA_SHIFT:
priv->out_down_pending++;
priv->out_down_delay++;
break;
default:
break;
}
break;
case SND_SOC_DAPM_POST_PMD:
switch (w->shift) {
case MADERA_OUT1L_ENA_SHIFT:
case MADERA_OUT1R_ENA_SHIFT:
case MADERA_OUT2L_ENA_SHIFT:
case MADERA_OUT2R_ENA_SHIFT:
case MADERA_OUT3L_ENA_SHIFT:
case MADERA_OUT3R_ENA_SHIFT:
priv->out_down_pending--;
if (!priv->out_down_pending) {
msleep(priv->out_down_delay);
priv->out_down_delay = 0;
}
break;
default:
break;
}
break;
default:
break;
}
return 0;
}
EXPORT_SYMBOL_GPL(madera_out_ev);
int madera_hp_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct madera_priv *priv = snd_soc_component_get_drvdata(component);
struct madera *madera = priv->madera;
unsigned int mask = 1 << w->shift;
unsigned int out_num = w->shift / 2;
unsigned int val;
unsigned int ep_sel = 0;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
val = mask;
break;
case SND_SOC_DAPM_PRE_PMD:
val = 0;
break;
case SND_SOC_DAPM_PRE_PMU:
case SND_SOC_DAPM_POST_PMD:
return madera_out_ev(w, kcontrol, event);
default:
return 0;
}
/* Store the desired state for the HP outputs */
madera->hp_ena &= ~mask;
madera->hp_ena |= val;
switch (madera->type) {
case CS42L92:
case CS47L92:
case CS47L93:
break;
default:
/* if OUT1 is routed to EPOUT, ignore HP clamp and impedance */
regmap_read(madera->regmap, MADERA_OUTPUT_ENABLES_1, &ep_sel);
ep_sel &= MADERA_EP_SEL_MASK;
break;
}
/* Force off if HPDET has disabled the clamp for this output */
if (!ep_sel &&
(!madera->out_clamp[out_num] || madera->out_shorted[out_num]))
val = 0;
regmap_update_bits(madera->regmap, MADERA_OUTPUT_ENABLES_1, mask, val);
return madera_out_ev(w, kcontrol, event);
}
EXPORT_SYMBOL_GPL(madera_hp_ev);
int madera_anc_ev(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
unsigned int val;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
val = 1 << w->shift;
break;
case SND_SOC_DAPM_PRE_PMD:
val = 1 << (w->shift + 1);
break;
default:
return 0;
}
snd_soc_component_write(component, MADERA_CLOCK_CONTROL, val);
return 0;
}
EXPORT_SYMBOL_GPL(madera_anc_ev);
static const unsigned int madera_opclk_ref_48k_rates[] = {
6144000,
12288000,
24576000,
49152000,
};
static const unsigned int madera_opclk_ref_44k1_rates[] = {
5644800,
11289600,
22579200,
45158400,
};
static int madera_set_opclk(struct snd_soc_component *component,
unsigned int clk, unsigned int freq)
{
struct madera_priv *priv = snd_soc_component_get_drvdata(component);
unsigned int mask = MADERA_OPCLK_DIV_MASK | MADERA_OPCLK_SEL_MASK;
unsigned int reg, val;
const unsigned int *rates;
int ref, div, refclk;
BUILD_BUG_ON(ARRAY_SIZE(madera_opclk_ref_48k_rates) !=
ARRAY_SIZE(madera_opclk_ref_44k1_rates));
switch (clk) {
case MADERA_CLK_OPCLK:
reg = MADERA_OUTPUT_SYSTEM_CLOCK;
refclk = priv->sysclk;
break;
case MADERA_CLK_ASYNC_OPCLK:
reg = MADERA_OUTPUT_ASYNC_CLOCK;
refclk = priv->asyncclk;
break;
default:
return -EINVAL;
}
if (refclk % 4000)
rates = madera_opclk_ref_44k1_rates;
else
rates = madera_opclk_ref_48k_rates;
for (ref = 0; ref < ARRAY_SIZE(madera_opclk_ref_48k_rates); ++ref) {
if (rates[ref] > refclk)
continue;
div = 2;
while ((rates[ref] / div >= freq) && (div <= 30)) {
if (rates[ref] / div == freq) {
dev_dbg(component->dev, "Configured %dHz OPCLK\n",
freq);
val = (div << MADERA_OPCLK_DIV_SHIFT) | ref;
snd_soc_component_update_bits(component, reg,
mask, val);
return 0;
}
div += 2;
}
}
dev_err(component->dev, "Unable to generate %dHz OPCLK\n", freq);
return -EINVAL;
}
static int madera_get_sysclk_setting(unsigned int freq)
{
switch (freq) {
case 0:
case 5644800:
case 6144000:
return 0;
case 11289600:
case 12288000:
return MADERA_SYSCLK_12MHZ << MADERA_SYSCLK_FREQ_SHIFT;
case 22579200:
case 24576000:
return MADERA_SYSCLK_24MHZ << MADERA_SYSCLK_FREQ_SHIFT;
case 45158400:
case 49152000:
return MADERA_SYSCLK_49MHZ << MADERA_SYSCLK_FREQ_SHIFT;
case 90316800:
case 98304000:
return MADERA_SYSCLK_98MHZ << MADERA_SYSCLK_FREQ_SHIFT;
default:
return -EINVAL;
}
}
static int madera_get_legacy_dspclk_setting(struct madera *madera,
unsigned int freq)
{
switch (freq) {
case 0:
return 0;
case 45158400:
case 49152000:
switch (madera->type) {
case CS47L85:
case WM1840:
if (madera->rev < 3)
return -EINVAL;
else
return MADERA_SYSCLK_49MHZ <<
MADERA_SYSCLK_FREQ_SHIFT;
default:
return -EINVAL;
}
case 135475200:
case 147456000:
return MADERA_DSPCLK_147MHZ << MADERA_DSP_CLK_FREQ_LEGACY_SHIFT;
default:
return -EINVAL;
}
}
static int madera_get_dspclk_setting(struct madera *madera,
unsigned int freq,
unsigned int *clock_2_val)
{
switch (madera->type) {
case CS47L35:
case CS47L85:
case WM1840:
*clock_2_val = 0; /* don't use MADERA_DSP_CLOCK_2 */
return madera_get_legacy_dspclk_setting(madera, freq);
default:
if (freq > 150000000)
return -EINVAL;
/* Use new exact frequency control */
*clock_2_val = freq / 15625; /* freq * (2^6) / (10^6) */
return 0;
}
}
static int madera_set_outclk(struct snd_soc_component *component,
unsigned int source, unsigned int freq)
{
int div, div_inc, rate;
switch (source) {
case MADERA_OUTCLK_SYSCLK:
dev_dbg(component->dev, "Configured OUTCLK to SYSCLK\n");
snd_soc_component_update_bits(component, MADERA_OUTPUT_RATE_1,
MADERA_OUT_CLK_SRC_MASK, source);
return 0;
case MADERA_OUTCLK_ASYNCCLK:
dev_dbg(component->dev, "Configured OUTCLK to ASYNCCLK\n");
snd_soc_component_update_bits(component, MADERA_OUTPUT_RATE_1,
MADERA_OUT_CLK_SRC_MASK, source);
return 0;
case MADERA_OUTCLK_MCLK1:
case MADERA_OUTCLK_MCLK2:
case MADERA_OUTCLK_MCLK3:
break;
default:
return -EINVAL;
}
if (freq % 4000)
rate = 5644800;
else
rate = 6144000;
div = 1;
div_inc = 0;
while (div <= 8) {
if (freq / div == rate && !(freq % div)) {
dev_dbg(component->dev, "Configured %dHz OUTCLK\n", rate);
snd_soc_component_update_bits(component,
MADERA_OUTPUT_RATE_1,
MADERA_OUT_EXT_CLK_DIV_MASK |
MADERA_OUT_CLK_SRC_MASK,
(div_inc << MADERA_OUT_EXT_CLK_DIV_SHIFT) |
source);
return 0;
}
div_inc++;
div *= 2;
}
dev_err(component->dev,
"Unable to generate %dHz OUTCLK from %dHz MCLK\n",
rate, freq);
return -EINVAL;
}
int madera_set_sysclk(struct snd_soc_component *component, int clk_id,
int source, unsigned int freq, int dir)
{
struct madera_priv *priv = snd_soc_component_get_drvdata(component);
struct madera *madera = priv->madera;
char *name;
unsigned int reg, clock_2_val = 0;
unsigned int mask = MADERA_SYSCLK_FREQ_MASK | MADERA_SYSCLK_SRC_MASK;
unsigned int val = source << MADERA_SYSCLK_SRC_SHIFT;
int clk_freq_sel, *clk;
int ret = 0;
switch (clk_id) {
case MADERA_CLK_SYSCLK_1:
name = "SYSCLK";
reg = MADERA_SYSTEM_CLOCK_1;
clk = &priv->sysclk;
clk_freq_sel = madera_get_sysclk_setting(freq);
mask |= MADERA_SYSCLK_FRAC;
break;
case MADERA_CLK_ASYNCCLK_1:
name = "ASYNCCLK";
reg = MADERA_ASYNC_CLOCK_1;
clk = &priv->asyncclk;
clk_freq_sel = madera_get_sysclk_setting(freq);
break;
case MADERA_CLK_DSPCLK:
name = "DSPCLK";
reg = MADERA_DSP_CLOCK_1;
clk = &priv->dspclk;
clk_freq_sel = madera_get_dspclk_setting(madera, freq,
&clock_2_val);
break;
case MADERA_CLK_OPCLK:
case MADERA_CLK_ASYNC_OPCLK:
return madera_set_opclk(component, clk_id, freq);
case MADERA_CLK_OUTCLK:
return madera_set_outclk(component, source, freq);
default:
return -EINVAL;
}
if (clk_freq_sel < 0) {
dev_err(madera->dev,
"Failed to get clk setting for %dHZ\n", freq);
return clk_freq_sel;
}
*clk = freq;
if (freq == 0) {
dev_dbg(madera->dev, "%s cleared\n", name);
return 0;
}
val |= clk_freq_sel;
if (clock_2_val) {
ret = regmap_write(madera->regmap, MADERA_DSP_CLOCK_2,
clock_2_val);
if (ret) {
dev_err(madera->dev,
"Failed to write DSP_CONFIG2: %d\n", ret);
return ret;
}
/*
* We're using the frequency setting in MADERA_DSP_CLOCK_2 so
* don't change the frequency select bits in MADERA_DSP_CLOCK_1
*/
mask = MADERA_SYSCLK_SRC_MASK;
}
if (freq % 6144000)
val |= MADERA_SYSCLK_FRAC;
dev_dbg(madera->dev, "%s set to %uHz\n", name, freq);
return regmap_update_bits(madera->regmap, reg, mask, val);
}
EXPORT_SYMBOL_GPL(madera_set_sysclk);
static int madera_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct madera_priv *priv = snd_soc_component_get_drvdata(component);
struct madera *madera = priv->madera;
int lrclk, bclk, mode, base;
base = dai->driver->base;
lrclk = 0;
bclk = 0;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
mode = MADERA_FMT_DSP_MODE_A;
break;
case SND_SOC_DAIFMT_DSP_B:
if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) !=
SND_SOC_DAIFMT_CBM_CFM) {
madera_aif_err(dai, "DSP_B not valid in slave mode\n");
return -EINVAL;
}
mode = MADERA_FMT_DSP_MODE_B;
break;
case SND_SOC_DAIFMT_I2S:
mode = MADERA_FMT_I2S_MODE;
break;
case SND_SOC_DAIFMT_LEFT_J:
if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) !=
SND_SOC_DAIFMT_CBM_CFM) {
madera_aif_err(dai, "LEFT_J not valid in slave mode\n");
return -EINVAL;
}
mode = MADERA_FMT_LEFT_JUSTIFIED_MODE;
break;
default:
madera_aif_err(dai, "Unsupported DAI format %d\n",
fmt & SND_SOC_DAIFMT_FORMAT_MASK);
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
break;
case SND_SOC_DAIFMT_CBS_CFM:
lrclk |= MADERA_AIF1TX_LRCLK_MSTR;
break;
case SND_SOC_DAIFMT_CBM_CFS:
bclk |= MADERA_AIF1_BCLK_MSTR;
break;
case SND_SOC_DAIFMT_CBM_CFM:
bclk |= MADERA_AIF1_BCLK_MSTR;
lrclk |= MADERA_AIF1TX_LRCLK_MSTR;
break;
default:
madera_aif_err(dai, "Unsupported master mode %d\n",
fmt & SND_SOC_DAIFMT_MASTER_MASK);
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
bclk |= MADERA_AIF1_BCLK_INV;
lrclk |= MADERA_AIF1TX_LRCLK_INV;
break;
case SND_SOC_DAIFMT_IB_NF:
bclk |= MADERA_AIF1_BCLK_INV;
break;
case SND_SOC_DAIFMT_NB_IF:
lrclk |= MADERA_AIF1TX_LRCLK_INV;
break;
default:
madera_aif_err(dai, "Unsupported invert mode %d\n",
fmt & SND_SOC_DAIFMT_INV_MASK);
return -EINVAL;
}
regmap_update_bits(madera->regmap, base + MADERA_AIF_BCLK_CTRL,
MADERA_AIF1_BCLK_INV | MADERA_AIF1_BCLK_MSTR,
bclk);
regmap_update_bits(madera->regmap, base + MADERA_AIF_TX_PIN_CTRL,
MADERA_AIF1TX_LRCLK_INV | MADERA_AIF1TX_LRCLK_MSTR,
lrclk);
regmap_update_bits(madera->regmap, base + MADERA_AIF_RX_PIN_CTRL,
MADERA_AIF1RX_LRCLK_INV | MADERA_AIF1RX_LRCLK_MSTR,
lrclk);
regmap_update_bits(madera->regmap, base + MADERA_AIF_FORMAT,
MADERA_AIF1_FMT_MASK, mode);
return 0;
}
static const int madera_48k_bclk_rates[] = {
-1,
48000,
64000,
96000,
128000,
192000,
256000,
384000,
512000,
768000,
1024000,
1536000,
2048000,
3072000,
4096000,
6144000,
8192000,
12288000,
24576000,
};
static const int madera_44k1_bclk_rates[] = {
-1,
44100,
58800,
88200,
117600,
177640,
235200,
352800,
470400,
705600,
940800,
1411200,
1881600,
2822400,
3763200,
5644800,
7526400,
11289600,
22579200,
};
static const unsigned int madera_sr_vals[] = {
0,
12000,
24000,
48000,
96000,
192000,
384000,
768000,
0,
11025,
22050,
44100,
88200,
176400,
352800,
705600,
4000,
8000,
16000,
32000,
64000,
128000,
256000,
512000,
};
#define MADERA_192K_48K_RATE_MASK 0x0F003E
#define MADERA_192K_44K1_RATE_MASK 0x003E00
#define MADERA_192K_RATE_MASK (MADERA_192K_48K_RATE_MASK | \
MADERA_192K_44K1_RATE_MASK)
#define MADERA_384K_48K_RATE_MASK 0x0F007E
#define MADERA_384K_44K1_RATE_MASK 0x007E00
#define MADERA_384K_RATE_MASK (MADERA_384K_48K_RATE_MASK | \
MADERA_384K_44K1_RATE_MASK)
static const struct snd_pcm_hw_constraint_list madera_constraint = {
.count = ARRAY_SIZE(madera_sr_vals),
.list = madera_sr_vals,
};
static int madera_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct madera_priv *priv = snd_soc_component_get_drvdata(component);
struct madera_dai_priv *dai_priv = &priv->dai[dai->id - 1];
struct madera *madera = priv->madera;
unsigned int base_rate;
if (!substream->runtime)
return 0;
switch (dai_priv->clk) {
case MADERA_CLK_SYSCLK_1:
case MADERA_CLK_SYSCLK_2:
case MADERA_CLK_SYSCLK_3:
base_rate = priv->sysclk;
break;
case MADERA_CLK_ASYNCCLK_1:
case MADERA_CLK_ASYNCCLK_2:
base_rate = priv->asyncclk;
break;
default:
return 0;
}
switch (madera->type) {
case CS42L92:
case CS47L92:
case CS47L93:
if (base_rate == 0)
dai_priv->constraint.mask = MADERA_384K_RATE_MASK;
else if (base_rate % 4000)
dai_priv->constraint.mask = MADERA_384K_44K1_RATE_MASK;
else
dai_priv->constraint.mask = MADERA_384K_48K_RATE_MASK;
break;
default:
if (base_rate == 0)
dai_priv->constraint.mask = MADERA_192K_RATE_MASK;
else if (base_rate % 4000)
dai_priv->constraint.mask = MADERA_192K_44K1_RATE_MASK;
else
dai_priv->constraint.mask = MADERA_192K_48K_RATE_MASK;
break;
}
return snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&dai_priv->constraint);
}
static int madera_hw_params_rate(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct madera_priv *priv = snd_soc_component_get_drvdata(component);
struct madera_dai_priv *dai_priv = &priv->dai[dai->id - 1];
int base = dai->driver->base;
int i, sr_val;
unsigned int reg, cur, tar;
int ret;
for (i = 0; i < ARRAY_SIZE(madera_sr_vals); i++)
if (madera_sr_vals[i] == params_rate(params))
break;
if (i == ARRAY_SIZE(madera_sr_vals)) {
madera_aif_err(dai, "Unsupported sample rate %dHz\n",
params_rate(params));
return -EINVAL;
}
sr_val = i;
switch (dai_priv->clk) {
case MADERA_CLK_SYSCLK_1:
reg = MADERA_SAMPLE_RATE_1;
tar = 0 << MADERA_AIF1_RATE_SHIFT;
break;
case MADERA_CLK_SYSCLK_2:
reg = MADERA_SAMPLE_RATE_2;
tar = 1 << MADERA_AIF1_RATE_SHIFT;
break;
case MADERA_CLK_SYSCLK_3:
reg = MADERA_SAMPLE_RATE_3;
tar = 2 << MADERA_AIF1_RATE_SHIFT;
break;
case MADERA_CLK_ASYNCCLK_1:
reg = MADERA_ASYNC_SAMPLE_RATE_1;
tar = 8 << MADERA_AIF1_RATE_SHIFT;
break;
case MADERA_CLK_ASYNCCLK_2:
reg = MADERA_ASYNC_SAMPLE_RATE_2;
tar = 9 << MADERA_AIF1_RATE_SHIFT;
break;
default:
madera_aif_err(dai, "Invalid clock %d\n", dai_priv->clk);
return -EINVAL;
}
snd_soc_component_update_bits(component, reg, MADERA_SAMPLE_RATE_1_MASK,
sr_val);
if (!base)
return 0;
ret = regmap_read(priv->madera->regmap,
base + MADERA_AIF_RATE_CTRL, &cur);
if (ret != 0) {
madera_aif_err(dai, "Failed to check rate: %d\n", ret);
return ret;
}
if ((cur & MADERA_AIF1_RATE_MASK) == (tar & MADERA_AIF1_RATE_MASK))
return 0;
mutex_lock(&priv->rate_lock);
if (!madera_can_change_grp_rate(priv, base + MADERA_AIF_RATE_CTRL)) {
madera_aif_warn(dai, "Cannot change rate while active\n");
ret = -EBUSY;
goto out;
}
/* Guard the rate change with SYSCLK cycles */
madera_spin_sysclk(priv);
snd_soc_component_update_bits(component, base + MADERA_AIF_RATE_CTRL,
MADERA_AIF1_RATE_MASK, tar);
madera_spin_sysclk(priv);
out:
mutex_unlock(&priv->rate_lock);
return ret;
}
static int madera_aif_cfg_changed(struct snd_soc_component *component,
int base, int bclk, int lrclk, int frame)
{
unsigned int val;
val = snd_soc_component_read(component, base + MADERA_AIF_BCLK_CTRL);
if (bclk != (val & MADERA_AIF1_BCLK_FREQ_MASK))
return 1;
val = snd_soc_component_read(component, base + MADERA_AIF_RX_BCLK_RATE);
if (lrclk != (val & MADERA_AIF1RX_BCPF_MASK))
return 1;
val = snd_soc_component_read(component, base + MADERA_AIF_FRAME_CTRL_1);
if (frame != (val & (MADERA_AIF1TX_WL_MASK |
MADERA_AIF1TX_SLOT_LEN_MASK)))
return 1;
return 0;
}
static int madera_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct madera_priv *priv = snd_soc_component_get_drvdata(component);
struct madera *madera = priv->madera;
int base = dai->driver->base;
const int *rates;
int i, ret;
unsigned int val;
unsigned int channels = params_channels(params);
unsigned int rate = params_rate(params);
unsigned int chan_limit =
madera->pdata.codec.max_channels_clocked[dai->id - 1];
int tdm_width = priv->tdm_width[dai->id - 1];
int tdm_slots = priv->tdm_slots[dai->id - 1];
int bclk, lrclk, wl, frame, bclk_target, num_rates;
int reconfig;
unsigned int aif_tx_state = 0, aif_rx_state = 0;
if (rate % 4000) {
rates = &madera_44k1_bclk_rates[0];
num_rates = ARRAY_SIZE(madera_44k1_bclk_rates);
} else {
rates = &madera_48k_bclk_rates[0];
num_rates = ARRAY_SIZE(madera_48k_bclk_rates);
}
wl = snd_pcm_format_width(params_format(params));
if (tdm_slots) {
madera_aif_dbg(dai, "Configuring for %d %d bit TDM slots\n",
tdm_slots, tdm_width);
bclk_target = tdm_slots * tdm_width * rate;
channels = tdm_slots;
} else {
bclk_target = snd_soc_params_to_bclk(params);
tdm_width = wl;
}
if (chan_limit && chan_limit < channels) {
madera_aif_dbg(dai, "Limiting to %d channels\n", chan_limit);
bclk_target /= channels;
bclk_target *= chan_limit;
}
/* Force multiple of 2 channels for I2S mode */
val = snd_soc_component_read(component, base + MADERA_AIF_FORMAT);
val &= MADERA_AIF1_FMT_MASK;
if ((channels & 1) && val == MADERA_FMT_I2S_MODE) {
madera_aif_dbg(dai, "Forcing stereo mode\n");
bclk_target /= channels;
bclk_target *= channels + 1;
}
for (i = 0; i < num_rates; i++) {
if (rates[i] >= bclk_target && rates[i] % rate == 0) {
bclk = i;
break;
}
}
if (i == num_rates) {
madera_aif_err(dai, "Unsupported sample rate %dHz\n", rate);
return -EINVAL;
}
lrclk = rates[bclk] / rate;
madera_aif_dbg(dai, "BCLK %dHz LRCLK %dHz\n",
rates[bclk], rates[bclk] / lrclk);
frame = wl << MADERA_AIF1TX_WL_SHIFT | tdm_width;
reconfig = madera_aif_cfg_changed(component, base, bclk, lrclk, frame);
if (reconfig < 0)
return reconfig;
if (reconfig) {
/* Save AIF TX/RX state */
regmap_read(madera->regmap, base + MADERA_AIF_TX_ENABLES,
&aif_tx_state);
regmap_read(madera->regmap, base + MADERA_AIF_RX_ENABLES,
&aif_rx_state);
/* Disable AIF TX/RX before reconfiguring it */
regmap_update_bits(madera->regmap,
base + MADERA_AIF_TX_ENABLES, 0xff, 0x0);
regmap_update_bits(madera->regmap,
base + MADERA_AIF_RX_ENABLES, 0xff, 0x0);
}
ret = madera_hw_params_rate(substream, params, dai);
if (ret != 0)
goto restore_aif;
if (reconfig) {
regmap_update_bits(madera->regmap,
base + MADERA_AIF_BCLK_CTRL,
MADERA_AIF1_BCLK_FREQ_MASK, bclk);
regmap_update_bits(madera->regmap,
base + MADERA_AIF_RX_BCLK_RATE,
MADERA_AIF1RX_BCPF_MASK, lrclk);
regmap_update_bits(madera->regmap,
base + MADERA_AIF_FRAME_CTRL_1,
MADERA_AIF1TX_WL_MASK |
MADERA_AIF1TX_SLOT_LEN_MASK, frame);
regmap_update_bits(madera->regmap,
base + MADERA_AIF_FRAME_CTRL_2,
MADERA_AIF1RX_WL_MASK |
MADERA_AIF1RX_SLOT_LEN_MASK, frame);
}
restore_aif:
if (reconfig) {
/* Restore AIF TX/RX state */
regmap_update_bits(madera->regmap,
base + MADERA_AIF_TX_ENABLES,
0xff, aif_tx_state);
regmap_update_bits(madera->regmap,
base + MADERA_AIF_RX_ENABLES,
0xff, aif_rx_state);
}
return ret;
}
static int madera_is_syncclk(int clk_id)
{
switch (clk_id) {
case MADERA_CLK_SYSCLK_1:
case MADERA_CLK_SYSCLK_2:
case MADERA_CLK_SYSCLK_3:
return 1;
case MADERA_CLK_ASYNCCLK_1:
case MADERA_CLK_ASYNCCLK_2:
return 0;
default:
return -EINVAL;
}
}
static int madera_dai_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct snd_soc_dapm_context *dapm =
snd_soc_component_get_dapm(component);
struct madera_priv *priv = snd_soc_component_get_drvdata(component);
struct madera_dai_priv *dai_priv = &priv->dai[dai->id - 1];
struct snd_soc_dapm_route routes[2];
int is_sync;
is_sync = madera_is_syncclk(clk_id);
if (is_sync < 0) {
dev_err(component->dev, "Illegal DAI clock id %d\n", clk_id);
return is_sync;
}
if (is_sync == madera_is_syncclk(dai_priv->clk))
return 0;
if (snd_soc_dai_active(dai)) {
dev_err(component->dev, "Can't change clock on active DAI %d\n",
dai->id);
return -EBUSY;
}
dev_dbg(component->dev, "Setting AIF%d to %s\n", dai->id,
is_sync ? "SYSCLK" : "ASYNCCLK");
/*
* A connection to SYSCLK is always required, we only add and remove
* a connection to ASYNCCLK
*/
memset(&routes, 0, sizeof(routes));
routes[0].sink = dai->driver->capture.stream_name;
routes[1].sink = dai->driver->playback.stream_name;
routes[0].source = "ASYNCCLK";
routes[1].source = "ASYNCCLK";
if (is_sync)
snd_soc_dapm_del_routes(dapm, routes, ARRAY_SIZE(routes));
else
snd_soc_dapm_add_routes(dapm, routes, ARRAY_SIZE(routes));
dai_priv->clk = clk_id;
return snd_soc_dapm_sync(dapm);
}
static int madera_set_tristate(struct snd_soc_dai *dai, int tristate)
{
struct snd_soc_component *component = dai->component;
int base = dai->driver->base;
unsigned int reg;
int ret;
if (tristate)
reg = MADERA_AIF1_TRI;
else
reg = 0;
ret = snd_soc_component_update_bits(component,
base + MADERA_AIF_RATE_CTRL,
MADERA_AIF1_TRI, reg);
if (ret < 0)
return ret;
else
return 0;
}
static void madera_set_channels_to_mask(struct snd_soc_dai *dai,
unsigned int base,
int channels, unsigned int mask)
{
struct snd_soc_component *component = dai->component;
struct madera_priv *priv = snd_soc_component_get_drvdata(component);
struct madera *madera = priv->madera;
int slot, i;
for (i = 0; i < channels; ++i) {
slot = ffs(mask) - 1;
if (slot < 0)
return;
regmap_write(madera->regmap, base + i, slot);
mask &= ~(1 << slot);
}
if (mask)
madera_aif_warn(dai, "Too many channels in TDM mask\n");
}
static int madera_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
struct madera_priv *priv = snd_soc_component_get_drvdata(component);
int base = dai->driver->base;
int rx_max_chan = dai->driver->playback.channels_max;
int tx_max_chan = dai->driver->capture.channels_max;
/* Only support TDM for the physical AIFs */
if (dai->id > MADERA_MAX_AIF)
return -ENOTSUPP;
if (slots == 0) {
tx_mask = (1 << tx_max_chan) - 1;
rx_mask = (1 << rx_max_chan) - 1;
}
madera_set_channels_to_mask(dai, base + MADERA_AIF_FRAME_CTRL_3,
tx_max_chan, tx_mask);
madera_set_channels_to_mask(dai, base + MADERA_AIF_FRAME_CTRL_11,
rx_max_chan, rx_mask);
priv->tdm_width[dai->id - 1] = slot_width;
priv->tdm_slots[dai->id - 1] = slots;
return 0;
}
const struct snd_soc_dai_ops madera_dai_ops = {
.startup = &madera_startup,
.set_fmt = &madera_set_fmt,
.set_tdm_slot = &madera_set_tdm_slot,
.hw_params = &madera_hw_params,
.set_sysclk = &madera_dai_set_sysclk,
.set_tristate = &madera_set_tristate,
};
EXPORT_SYMBOL_GPL(madera_dai_ops);
const struct snd_soc_dai_ops madera_simple_dai_ops = {
.startup = &madera_startup,
.hw_params = &madera_hw_params_rate,
.set_sysclk = &madera_dai_set_sysclk,
};
EXPORT_SYMBOL_GPL(madera_simple_dai_ops);
int madera_init_dai(struct madera_priv *priv, int id)
{
struct madera_dai_priv *dai_priv = &priv->dai[id];
dai_priv->clk = MADERA_CLK_SYSCLK_1;
dai_priv->constraint = madera_constraint;
return 0;
}
EXPORT_SYMBOL_GPL(madera_init_dai);
static const struct {
unsigned int min;
unsigned int max;
u16 fratio;
int ratio;
} fll_sync_fratios[] = {
{ 0, 64000, 4, 16 },
{ 64000, 128000, 3, 8 },
{ 128000, 256000, 2, 4 },
{ 256000, 1000000, 1, 2 },
{ 1000000, 13500000, 0, 1 },
};
static const unsigned int pseudo_fref_max[MADERA_FLL_MAX_FRATIO] = {
13500000,
6144000,
6144000,
3072000,
3072000,
2822400,
2822400,
1536000,
1536000,
1536000,
1536000,
1536000,
1536000,
1536000,
1536000,
768000,
};
struct madera_fll_gains {
unsigned int min;
unsigned int max;
int gain; /* main gain */
int alt_gain; /* alternate integer gain */
};
static const struct madera_fll_gains madera_fll_sync_gains[] = {
{ 0, 256000, 0, -1 },
{ 256000, 1000000, 2, -1 },
{ 1000000, 13500000, 4, -1 },
};
static const struct madera_fll_gains madera_fll_main_gains[] = {
{ 0, 100000, 0, 2 },
{ 100000, 375000, 2, 2 },
{ 375000, 768000, 3, 2 },
{ 768001, 1500000, 3, 3 },
{ 1500000, 6000000, 4, 3 },
{ 6000000, 13500000, 5, 3 },
};
static int madera_find_sync_fratio(unsigned int fref, int *fratio)
{
int i;
for (i = 0; i < ARRAY_SIZE(fll_sync_fratios); i++) {
if (fll_sync_fratios[i].min <= fref &&
fref <= fll_sync_fratios[i].max) {
if (fratio)
*fratio = fll_sync_fratios[i].fratio;
return fll_sync_fratios[i].ratio;
}
}
return -EINVAL;
}
static int madera_find_main_fratio(unsigned int fref, unsigned int fout,
int *fratio)
{
int ratio = 1;
while ((fout / (ratio * fref)) > MADERA_FLL_MAX_N)
ratio++;
if (fratio)
*fratio = ratio - 1;
return ratio;
}
static int madera_find_fratio(struct madera_fll *fll, unsigned int fref,
bool sync, int *fratio)
{
switch (fll->madera->type) {
case CS47L35:
switch (fll->madera->rev) {
case 0:
/* rev A0 uses sync calculation for both loops */
return madera_find_sync_fratio(fref, fratio);
default:
if (sync)
return madera_find_sync_fratio(fref, fratio);
else
return madera_find_main_fratio(fref,
fll->fout,
fratio);
}
break;
case CS47L85:
case WM1840:
/* these use the same calculation for main and sync loops */
return madera_find_sync_fratio(fref, fratio);
default:
if (sync)
return madera_find_sync_fratio(fref, fratio);
else
return madera_find_main_fratio(fref, fll->fout, fratio);
}
}
static int madera_calc_fratio(struct madera_fll *fll,
struct madera_fll_cfg *cfg,
unsigned int fref, bool sync)
{
int init_ratio, ratio;
int refdiv, div;
/* fref must be <=13.5MHz, find initial refdiv */
div = 1;
cfg->refdiv = 0;
while (fref > MADERA_FLL_MAX_FREF) {
div *= 2;
fref /= 2;
cfg->refdiv++;
if (div > MADERA_FLL_MAX_REFDIV)
return -EINVAL;
}
/* Find an appropriate FLL_FRATIO */
init_ratio = madera_find_fratio(fll, fref, sync, &cfg->fratio);
if (init_ratio < 0) {
madera_fll_err(fll, "Unable to find FRATIO for fref=%uHz\n",
fref);
return init_ratio;
}
if (!sync)
cfg->fratio = init_ratio - 1;
switch (fll->madera->type) {
case CS47L35:
switch (fll->madera->rev) {
case 0:
if (sync)
return init_ratio;
break;
default:
return init_ratio;
}
break;
case CS47L85:
case WM1840:
if (sync)
return init_ratio;
break;
default:
return init_ratio;
}
/*
* For CS47L35 rev A0, CS47L85 and WM1840 adjust FRATIO/refdiv to avoid
* integer mode if possible
*/
refdiv = cfg->refdiv;
while (div <= MADERA_FLL_MAX_REFDIV) {
/*
* start from init_ratio because this may already give a
* fractional N.K
*/
for (ratio = init_ratio; ratio > 0; ratio--) {
if (fll->fout % (ratio * fref)) {
cfg->refdiv = refdiv;
cfg->fratio = ratio - 1;
return ratio;
}
}
for (ratio = init_ratio + 1; ratio <= MADERA_FLL_MAX_FRATIO;
ratio++) {
if ((MADERA_FLL_VCO_CORNER / 2) /
(MADERA_FLL_VCO_MULT * ratio) < fref)
break;
if (fref > pseudo_fref_max[ratio - 1])
break;
if (fll->fout % (ratio * fref)) {
cfg->refdiv = refdiv;
cfg->fratio = ratio - 1;
return ratio;
}
}
div *= 2;
fref /= 2;
refdiv++;
init_ratio = madera_find_fratio(fll, fref, sync, NULL);
}
madera_fll_warn(fll, "Falling back to integer mode operation\n");
return cfg->fratio + 1;
}
static int madera_find_fll_gain(struct madera_fll *fll,
struct madera_fll_cfg *cfg,
unsigned int fref,
const struct madera_fll_gains *gains,
int n_gains)
{
int i;
for (i = 0; i < n_gains; i++) {
if (gains[i].min <= fref && fref <= gains[i].max) {
cfg->gain = gains[i].gain;
cfg->alt_gain = gains[i].alt_gain;
return 0;
}
}
madera_fll_err(fll, "Unable to find gain for fref=%uHz\n", fref);
return -EINVAL;
}
static int madera_calc_fll(struct madera_fll *fll,
struct madera_fll_cfg *cfg,
unsigned int fref, bool sync)
{
unsigned int gcd_fll;
const struct madera_fll_gains *gains;
int n_gains;
int ratio, ret;
madera_fll_dbg(fll, "fref=%u Fout=%u fvco=%u\n",
fref, fll->fout, fll->fout * MADERA_FLL_VCO_MULT);
/* Find an appropriate FLL_FRATIO and refdiv */
ratio = madera_calc_fratio(fll, cfg, fref, sync);
if (ratio < 0)
return ratio;
/* Apply the division for our remaining calculations */
fref = fref / (1 << cfg->refdiv);
cfg->n = fll->fout / (ratio * fref);
if (fll->fout % (ratio * fref)) {
gcd_fll = gcd(fll->fout, ratio * fref);
madera_fll_dbg(fll, "GCD=%u\n", gcd_fll);
cfg->theta = (fll->fout - (cfg->n * ratio * fref))
/ gcd_fll;
cfg->lambda = (ratio * fref) / gcd_fll;
} else {
cfg->theta = 0;
cfg->lambda = 0;
}
/*
* Round down to 16bit range with cost of accuracy lost.
* Denominator must be bigger than numerator so we only
* take care of it.
*/
while (cfg->lambda >= (1 << 16)) {
cfg->theta >>= 1;
cfg->lambda >>= 1;
}
switch (fll->madera->type) {
case CS47L35:
switch (fll->madera->rev) {
case 0:
/* Rev A0 uses the sync gains for both loops */
gains = madera_fll_sync_gains;
n_gains = ARRAY_SIZE(madera_fll_sync_gains);
break;
default:
if (sync) {
gains = madera_fll_sync_gains;
n_gains = ARRAY_SIZE(madera_fll_sync_gains);
} else {
gains = madera_fll_main_gains;
n_gains = ARRAY_SIZE(madera_fll_main_gains);
}
break;
}
break;
case CS47L85:
case WM1840:
/* These use the sync gains for both loops */
gains = madera_fll_sync_gains;
n_gains = ARRAY_SIZE(madera_fll_sync_gains);
break;
default:
if (sync) {
gains = madera_fll_sync_gains;
n_gains = ARRAY_SIZE(madera_fll_sync_gains);
} else {
gains = madera_fll_main_gains;
n_gains = ARRAY_SIZE(madera_fll_main_gains);
}
break;
}
ret = madera_find_fll_gain(fll, cfg, fref, gains, n_gains);
if (ret)
return ret;
madera_fll_dbg(fll, "N=%d THETA=%d LAMBDA=%d\n",
cfg->n, cfg->theta, cfg->lambda);
madera_fll_dbg(fll, "FRATIO=0x%x(%d) REFCLK_DIV=0x%x(%d)\n",
cfg->fratio, ratio, cfg->refdiv, 1 << cfg->refdiv);
madera_fll_dbg(fll, "GAIN=0x%x(%d)\n", cfg->gain, 1 << cfg->gain);
return 0;
}
static bool madera_write_fll(struct madera *madera, unsigned int base,
struct madera_fll_cfg *cfg, int source,
bool sync, int gain)
{
bool change, fll_change;
fll_change = false;
regmap_update_bits_check(madera->regmap,
base + MADERA_FLL_CONTROL_3_OFFS,
MADERA_FLL1_THETA_MASK,
cfg->theta, &change);
fll_change |= change;
regmap_update_bits_check(madera->regmap,
base + MADERA_FLL_CONTROL_4_OFFS,
MADERA_FLL1_LAMBDA_MASK,
cfg->lambda, &change);
fll_change |= change;
regmap_update_bits_check(madera->regmap,
base + MADERA_FLL_CONTROL_5_OFFS,
MADERA_FLL1_FRATIO_MASK,
cfg->fratio << MADERA_FLL1_FRATIO_SHIFT,
&change);
fll_change |= change;
regmap_update_bits_check(madera->regmap,
base + MADERA_FLL_CONTROL_6_OFFS,
MADERA_FLL1_REFCLK_DIV_MASK |
MADERA_FLL1_REFCLK_SRC_MASK,
cfg->refdiv << MADERA_FLL1_REFCLK_DIV_SHIFT |
source << MADERA_FLL1_REFCLK_SRC_SHIFT,
&change);
fll_change |= change;
if (sync) {
regmap_update_bits_check(madera->regmap,
base + MADERA_FLL_SYNCHRONISER_7_OFFS,
MADERA_FLL1_GAIN_MASK,
gain << MADERA_FLL1_GAIN_SHIFT,
&change);
fll_change |= change;
} else {
regmap_update_bits_check(madera->regmap,
base + MADERA_FLL_CONTROL_7_OFFS,
MADERA_FLL1_GAIN_MASK,
gain << MADERA_FLL1_GAIN_SHIFT,
&change);
fll_change |= change;
}
regmap_update_bits_check(madera->regmap,
base + MADERA_FLL_CONTROL_2_OFFS,
MADERA_FLL1_CTRL_UPD | MADERA_FLL1_N_MASK,
MADERA_FLL1_CTRL_UPD | cfg->n, &change);
fll_change |= change;
return fll_change;
}
static int madera_is_enabled_fll(struct madera_fll *fll, int base)
{
struct madera *madera = fll->madera;
unsigned int reg;
int ret;
ret = regmap_read(madera->regmap,
base + MADERA_FLL_CONTROL_1_OFFS, ®);
if (ret != 0) {
madera_fll_err(fll, "Failed to read current state: %d\n", ret);
return ret;
}
return reg & MADERA_FLL1_ENA;
}
static int madera_wait_for_fll(struct madera_fll *fll, bool requested)
{
struct madera *madera = fll->madera;
unsigned int val = 0;
bool status;
int i;
madera_fll_dbg(fll, "Waiting for FLL...\n");
for (i = 0; i < 30; i++) {
regmap_read(madera->regmap, MADERA_IRQ1_RAW_STATUS_2, &val);
status = val & (MADERA_FLL1_LOCK_STS1 << (fll->id - 1));
if (status == requested)
return 0;
switch (i) {
case 0 ... 5:
usleep_range(75, 125);
break;
case 11 ... 20:
usleep_range(750, 1250);
break;
default:
msleep(20);
break;
}
}
madera_fll_warn(fll, "Timed out waiting for lock\n");
return -ETIMEDOUT;
}
static bool madera_set_fll_phase_integrator(struct madera_fll *fll,
struct madera_fll_cfg *ref_cfg,
bool sync)
{
unsigned int val;
bool reg_change;
if (!sync && ref_cfg->theta == 0)
val = (1 << MADERA_FLL1_PHASE_ENA_SHIFT) |
(2 << MADERA_FLL1_PHASE_GAIN_SHIFT);
else
val = 2 << MADERA_FLL1_PHASE_GAIN_SHIFT;
regmap_update_bits_check(fll->madera->regmap,
fll->base + MADERA_FLL_EFS_2_OFFS,
MADERA_FLL1_PHASE_ENA_MASK |
MADERA_FLL1_PHASE_GAIN_MASK,
val, ®_change);
return reg_change;
}
static int madera_set_fll_clks_reg(struct madera_fll *fll, bool ena,
unsigned int reg, unsigned int mask,
unsigned int shift)
{
struct madera *madera = fll->madera;
unsigned int src;
struct clk *clk;
int ret;
ret = regmap_read(madera->regmap, reg, &src);
if (ret != 0) {
madera_fll_err(fll, "Failed to read current source: %d\n",
ret);
return ret;
}
src = (src & mask) >> shift;
switch (src) {
case MADERA_FLL_SRC_MCLK1:
clk = madera->mclk[MADERA_MCLK1].clk;
break;
case MADERA_FLL_SRC_MCLK2:
clk = madera->mclk[MADERA_MCLK2].clk;
break;
case MADERA_FLL_SRC_MCLK3:
clk = madera->mclk[MADERA_MCLK3].clk;
break;
default:
return 0;
}
if (ena) {
return clk_prepare_enable(clk);
} else {
clk_disable_unprepare(clk);
return 0;
}
}
static inline int madera_set_fll_clks(struct madera_fll *fll, int base, bool ena)
{
return madera_set_fll_clks_reg(fll, ena,
base + MADERA_FLL_CONTROL_6_OFFS,
MADERA_FLL1_REFCLK_SRC_MASK,
MADERA_FLL1_REFCLK_DIV_SHIFT);
}
static inline int madera_set_fllao_clks(struct madera_fll *fll, int base, bool ena)
{
return madera_set_fll_clks_reg(fll, ena,
base + MADERA_FLLAO_CONTROL_6_OFFS,
MADERA_FLL_AO_REFCLK_SRC_MASK,
MADERA_FLL_AO_REFCLK_SRC_SHIFT);
}
static inline int madera_set_fllhj_clks(struct madera_fll *fll, int base, bool ena)
{
return madera_set_fll_clks_reg(fll, ena,
base + MADERA_FLL_CONTROL_1_OFFS,
CS47L92_FLL1_REFCLK_SRC_MASK,
CS47L92_FLL1_REFCLK_SRC_SHIFT);
}
static void madera_disable_fll(struct madera_fll *fll)
{
struct madera *madera = fll->madera;
unsigned int sync_base;
bool ref_change, sync_change;
switch (madera->type) {
case CS47L35:
sync_base = fll->base + CS47L35_FLL_SYNCHRONISER_OFFS;
break;
default:
sync_base = fll->base + MADERA_FLL_SYNCHRONISER_OFFS;
break;
}
madera_fll_dbg(fll, "Disabling FLL\n");
regmap_update_bits(madera->regmap,
fll->base + MADERA_FLL_CONTROL_1_OFFS,
MADERA_FLL1_FREERUN, MADERA_FLL1_FREERUN);
regmap_update_bits_check(madera->regmap,
fll->base + MADERA_FLL_CONTROL_1_OFFS,
MADERA_FLL1_ENA, 0, &ref_change);
regmap_update_bits_check(madera->regmap,
sync_base + MADERA_FLL_SYNCHRONISER_1_OFFS,
MADERA_FLL1_SYNC_ENA, 0, &sync_change);
regmap_update_bits(madera->regmap,
fll->base + MADERA_FLL_CONTROL_1_OFFS,
MADERA_FLL1_FREERUN, 0);
madera_wait_for_fll(fll, false);
if (sync_change)
madera_set_fll_clks(fll, sync_base, false);
if (ref_change) {
madera_set_fll_clks(fll, fll->base, false);
pm_runtime_put_autosuspend(madera->dev);
}
}
static int madera_enable_fll(struct madera_fll *fll)
{
struct madera *madera = fll->madera;
bool have_sync = false;
int already_enabled = madera_is_enabled_fll(fll, fll->base);
int sync_enabled;
struct madera_fll_cfg cfg;
unsigned int sync_base;
int gain, ret;
bool fll_change = false;
if (already_enabled < 0)
return already_enabled; /* error getting current state */
if (fll->ref_src < 0 || fll->ref_freq == 0) {
madera_fll_err(fll, "No REFCLK\n");
ret = -EINVAL;
goto err;
}
madera_fll_dbg(fll, "Enabling FLL, initially %s\n",
already_enabled ? "enabled" : "disabled");
if (fll->fout < MADERA_FLL_MIN_FOUT ||
fll->fout > MADERA_FLL_MAX_FOUT) {
madera_fll_err(fll, "invalid fout %uHz\n", fll->fout);
ret = -EINVAL;
goto err;
}
switch (madera->type) {
case CS47L35:
sync_base = fll->base + CS47L35_FLL_SYNCHRONISER_OFFS;
break;
default:
sync_base = fll->base + MADERA_FLL_SYNCHRONISER_OFFS;
break;
}
sync_enabled = madera_is_enabled_fll(fll, sync_base);
if (sync_enabled < 0)
return sync_enabled;
if (already_enabled) {
/* Facilitate smooth refclk across the transition */
regmap_update_bits(fll->madera->regmap,
fll->base + MADERA_FLL_CONTROL_1_OFFS,
MADERA_FLL1_FREERUN,
MADERA_FLL1_FREERUN);
udelay(32);
regmap_update_bits(fll->madera->regmap,
fll->base + MADERA_FLL_CONTROL_7_OFFS,
MADERA_FLL1_GAIN_MASK, 0);
if (sync_enabled > 0)
madera_set_fll_clks(fll, sync_base, false);
madera_set_fll_clks(fll, fll->base, false);
}
/* Apply SYNCCLK setting */
if (fll->sync_src >= 0) {
ret = madera_calc_fll(fll, &cfg, fll->sync_freq, true);
if (ret < 0)
goto err;
fll_change |= madera_write_fll(madera, sync_base,
&cfg, fll->sync_src,
true, cfg.gain);
have_sync = true;
}
if (already_enabled && !!sync_enabled != have_sync)
madera_fll_warn(fll, "Synchroniser changed on active FLL\n");
/* Apply REFCLK setting */
ret = madera_calc_fll(fll, &cfg, fll->ref_freq, false);
if (ret < 0)
goto err;
/* Ref path hardcodes lambda to 65536 when sync is on */
if (have_sync && cfg.lambda)
cfg.theta = (cfg.theta * (1 << 16)) / cfg.lambda;
switch (fll->madera->type) {
case CS47L35:
switch (fll->madera->rev) {
case 0:
gain = cfg.gain;
break;
default:
fll_change |=
madera_set_fll_phase_integrator(fll, &cfg,
have_sync);
if (!have_sync && cfg.theta == 0)
gain = cfg.alt_gain;
else
gain = cfg.gain;
break;
}
break;
case CS47L85:
case WM1840:
gain = cfg.gain;
break;
default:
fll_change |= madera_set_fll_phase_integrator(fll, &cfg,
have_sync);
if (!have_sync && cfg.theta == 0)
gain = cfg.alt_gain;
else
gain = cfg.gain;
break;
}
fll_change |= madera_write_fll(madera, fll->base,
&cfg, fll->ref_src,
false, gain);
/*
* Increase the bandwidth if we're not using a low frequency
* sync source.
*/
if (have_sync && fll->sync_freq > 100000)
regmap_update_bits(madera->regmap,
sync_base + MADERA_FLL_SYNCHRONISER_7_OFFS,
MADERA_FLL1_SYNC_DFSAT_MASK, 0);
else
regmap_update_bits(madera->regmap,
sync_base + MADERA_FLL_SYNCHRONISER_7_OFFS,
MADERA_FLL1_SYNC_DFSAT_MASK,
MADERA_FLL1_SYNC_DFSAT);
if (!already_enabled)
pm_runtime_get_sync(madera->dev);
if (have_sync) {
madera_set_fll_clks(fll, sync_base, true);
regmap_update_bits(madera->regmap,
sync_base + MADERA_FLL_SYNCHRONISER_1_OFFS,
MADERA_FLL1_SYNC_ENA,
MADERA_FLL1_SYNC_ENA);
}
madera_set_fll_clks(fll, fll->base, true);
regmap_update_bits(madera->regmap,
fll->base + MADERA_FLL_CONTROL_1_OFFS,
MADERA_FLL1_ENA, MADERA_FLL1_ENA);
if (already_enabled)
regmap_update_bits(madera->regmap,
fll->base + MADERA_FLL_CONTROL_1_OFFS,
MADERA_FLL1_FREERUN, 0);
if (fll_change || !already_enabled)
madera_wait_for_fll(fll, true);
return 0;
err:
/* In case of error don't leave the FLL running with an old config */
madera_disable_fll(fll);
return ret;
}
static int madera_apply_fll(struct madera_fll *fll)
{
if (fll->fout) {
return madera_enable_fll(fll);
} else {
madera_disable_fll(fll);
return 0;
}
}
int madera_set_fll_syncclk(struct madera_fll *fll, int source,
unsigned int fref, unsigned int fout)
{
/*
* fout is ignored, since the synchronizer is an optional extra
* constraint on the Fout generated from REFCLK, so the Fout is
* set when configuring REFCLK
*/
if (fll->sync_src == source && fll->sync_freq == fref)
return 0;
fll->sync_src = source;
fll->sync_freq = fref;
return madera_apply_fll(fll);
}
EXPORT_SYMBOL_GPL(madera_set_fll_syncclk);
int madera_set_fll_refclk(struct madera_fll *fll, int source,
unsigned int fref, unsigned int fout)
{
int ret;
if (fll->ref_src == source &&
fll->ref_freq == fref && fll->fout == fout)
return 0;
/*
* Changes of fout on an enabled FLL aren't allowed except when
* setting fout==0 to disable the FLL
*/
if (fout && fout != fll->fout) {
ret = madera_is_enabled_fll(fll, fll->base);
if (ret < 0)
return ret;
if (ret) {
madera_fll_err(fll, "Can't change Fout on active FLL\n");
return -EBUSY;
}
}
fll->ref_src = source;
fll->ref_freq = fref;
fll->fout = fout;
return madera_apply_fll(fll);
}
EXPORT_SYMBOL_GPL(madera_set_fll_refclk);
int madera_init_fll(struct madera *madera, int id, int base,
struct madera_fll *fll)
{
fll->id = id;
fll->base = base;
fll->madera = madera;
fll->ref_src = MADERA_FLL_SRC_NONE;
fll->sync_src = MADERA_FLL_SRC_NONE;
regmap_update_bits(madera->regmap,
fll->base + MADERA_FLL_CONTROL_1_OFFS,
MADERA_FLL1_FREERUN, 0);
return 0;
}
EXPORT_SYMBOL_GPL(madera_init_fll);
static const struct reg_sequence madera_fll_ao_32K_49M_patch[] = {
{ MADERA_FLLAO_CONTROL_2, 0x02EE },
{ MADERA_FLLAO_CONTROL_3, 0x0000 },
{ MADERA_FLLAO_CONTROL_4, 0x0001 },
{ MADERA_FLLAO_CONTROL_5, 0x0002 },
{ MADERA_FLLAO_CONTROL_6, 0x8001 },
{ MADERA_FLLAO_CONTROL_7, 0x0004 },
{ MADERA_FLLAO_CONTROL_8, 0x0077 },
{ MADERA_FLLAO_CONTROL_10, 0x06D8 },
{ MADERA_FLLAO_CONTROL_11, 0x0085 },
{ MADERA_FLLAO_CONTROL_2, 0x82EE },
};
static const struct reg_sequence madera_fll_ao_32K_45M_patch[] = {
{ MADERA_FLLAO_CONTROL_2, 0x02B1 },
{ MADERA_FLLAO_CONTROL_3, 0x0001 },
{ MADERA_FLLAO_CONTROL_4, 0x0010 },
{ MADERA_FLLAO_CONTROL_5, 0x0002 },
{ MADERA_FLLAO_CONTROL_6, 0x8001 },
{ MADERA_FLLAO_CONTROL_7, 0x0004 },
{ MADERA_FLLAO_CONTROL_8, 0x0077 },
{ MADERA_FLLAO_CONTROL_10, 0x06D8 },
{ MADERA_FLLAO_CONTROL_11, 0x0005 },
{ MADERA_FLLAO_CONTROL_2, 0x82B1 },
};
struct madera_fllao_patch {
unsigned int fin;
unsigned int fout;
const struct reg_sequence *patch;
unsigned int patch_size;
};
static const struct madera_fllao_patch madera_fllao_settings[] = {
{
.fin = 32768,
.fout = 49152000,
.patch = madera_fll_ao_32K_49M_patch,
.patch_size = ARRAY_SIZE(madera_fll_ao_32K_49M_patch),
},
{
.fin = 32768,
.fout = 45158400,
.patch = madera_fll_ao_32K_45M_patch,
.patch_size = ARRAY_SIZE(madera_fll_ao_32K_45M_patch),
},
};
static int madera_enable_fll_ao(struct madera_fll *fll,
const struct reg_sequence *patch,
unsigned int patch_size)
{
struct madera *madera = fll->madera;
int already_enabled = madera_is_enabled_fll(fll, fll->base);
unsigned int val;
int i;
if (already_enabled < 0)
return already_enabled;
if (!already_enabled)
pm_runtime_get_sync(madera->dev);
madera_fll_dbg(fll, "Enabling FLL_AO, initially %s\n",
already_enabled ? "enabled" : "disabled");
/* FLL_AO_HOLD must be set before configuring any registers */
regmap_update_bits(fll->madera->regmap,
fll->base + MADERA_FLLAO_CONTROL_1_OFFS,
MADERA_FLL_AO_HOLD, MADERA_FLL_AO_HOLD);
if (already_enabled)
madera_set_fllao_clks(fll, fll->base, false);
for (i = 0; i < patch_size; i++) {
val = patch[i].def;
/* modify the patch to apply fll->ref_src as input clock */
if (patch[i].reg == MADERA_FLLAO_CONTROL_6) {
val &= ~MADERA_FLL_AO_REFCLK_SRC_MASK;
val |= (fll->ref_src << MADERA_FLL_AO_REFCLK_SRC_SHIFT)
& MADERA_FLL_AO_REFCLK_SRC_MASK;
}
regmap_write(madera->regmap, patch[i].reg, val);
}
madera_set_fllao_clks(fll, fll->base, true);
regmap_update_bits(madera->regmap,
fll->base + MADERA_FLLAO_CONTROL_1_OFFS,
MADERA_FLL_AO_ENA, MADERA_FLL_AO_ENA);
/* Release the hold so that fll_ao locks to external frequency */
regmap_update_bits(madera->regmap,
fll->base + MADERA_FLLAO_CONTROL_1_OFFS,
MADERA_FLL_AO_HOLD, 0);
if (!already_enabled)
madera_wait_for_fll(fll, true);
return 0;
}
static int madera_disable_fll_ao(struct madera_fll *fll)
{
struct madera *madera = fll->madera;
bool change;
madera_fll_dbg(fll, "Disabling FLL_AO\n");
regmap_update_bits(madera->regmap,
fll->base + MADERA_FLLAO_CONTROL_1_OFFS,
MADERA_FLL_AO_HOLD, MADERA_FLL_AO_HOLD);
regmap_update_bits_check(madera->regmap,
fll->base + MADERA_FLLAO_CONTROL_1_OFFS,
MADERA_FLL_AO_ENA, 0, &change);
madera_wait_for_fll(fll, false);
/*
* ctrl_up gates the writes to all fll_ao register, setting it to 0
* here ensures that after a runtime suspend/resume cycle when one
* enables the fllao then ctrl_up is the last bit that is configured
* by the fllao enable code rather than the cache sync operation which
* would have updated it much earlier before writing out all fllao
* registers
*/
regmap_update_bits(madera->regmap,
fll->base + MADERA_FLLAO_CONTROL_2_OFFS,
MADERA_FLL_AO_CTRL_UPD_MASK, 0);
if (change) {
madera_set_fllao_clks(fll, fll->base, false);
pm_runtime_put_autosuspend(madera->dev);
}
return 0;
}
int madera_set_fll_ao_refclk(struct madera_fll *fll, int source,
unsigned int fin, unsigned int fout)
{
int ret = 0;
const struct reg_sequence *patch = NULL;
int patch_size = 0;
unsigned int i;
if (fll->ref_src == source &&
fll->ref_freq == fin && fll->fout == fout)
return 0;
madera_fll_dbg(fll, "Change FLL_AO refclk to fin=%u fout=%u source=%d\n",
fin, fout, source);
if (fout && (fll->ref_freq != fin || fll->fout != fout)) {
for (i = 0; i < ARRAY_SIZE(madera_fllao_settings); i++) {
if (madera_fllao_settings[i].fin == fin &&
madera_fllao_settings[i].fout == fout)
break;
}
if (i == ARRAY_SIZE(madera_fllao_settings)) {
madera_fll_err(fll,
"No matching configuration for FLL_AO\n");
return -EINVAL;
}
patch = madera_fllao_settings[i].patch;
patch_size = madera_fllao_settings[i].patch_size;
}
fll->ref_src = source;
fll->ref_freq = fin;
fll->fout = fout;
if (fout)
ret = madera_enable_fll_ao(fll, patch, patch_size);
else
madera_disable_fll_ao(fll);
return ret;
}
EXPORT_SYMBOL_GPL(madera_set_fll_ao_refclk);
static int madera_fllhj_disable(struct madera_fll *fll)
{
struct madera *madera = fll->madera;
bool change;
madera_fll_dbg(fll, "Disabling FLL\n");
/* Disable lockdet, but don't set ctrl_upd update but. This allows the
* lock status bit to clear as normal, but should the FLL be enabled
* again due to a control clock being required, the lock won't re-assert
* as the FLL config registers are automatically applied when the FLL
* enables.
*/
regmap_update_bits(madera->regmap,
fll->base + MADERA_FLL_CONTROL_11_OFFS,
MADERA_FLL1_LOCKDET_MASK, 0);
regmap_update_bits(madera->regmap,
fll->base + MADERA_FLL_CONTROL_1_OFFS,
MADERA_FLL1_HOLD_MASK, MADERA_FLL1_HOLD_MASK);
regmap_update_bits_check(madera->regmap,
fll->base + MADERA_FLL_CONTROL_1_OFFS,
MADERA_FLL1_ENA_MASK, 0, &change);
madera_wait_for_fll(fll, false);
/* ctrl_up gates the writes to all the fll's registers, setting it to 0
* here ensures that after a runtime suspend/resume cycle when one
* enables the fll then ctrl_up is the last bit that is configured
* by the fll enable code rather than the cache sync operation which
* would have updated it much earlier before writing out all fll
* registers
*/
regmap_update_bits(madera->regmap,
fll->base + MADERA_FLL_CONTROL_2_OFFS,
MADERA_FLL1_CTRL_UPD_MASK, 0);
if (change) {
madera_set_fllhj_clks(fll, fll->base, false);
pm_runtime_put_autosuspend(madera->dev);
}
return 0;
}
static int madera_fllhj_apply(struct madera_fll *fll, int fin)
{
struct madera *madera = fll->madera;
int refdiv, fref, fout, lockdet_thr, fbdiv, hp, fast_clk, fllgcd;
bool frac = false;
unsigned int fll_n, min_n, max_n, ratio, theta, lambda;
unsigned int gains, val, num;
madera_fll_dbg(fll, "fin=%d, fout=%d\n", fin, fll->fout);
for (refdiv = 0; refdiv < 4; refdiv++)
if ((fin / (1 << refdiv)) <= MADERA_FLLHJ_MAX_THRESH)
break;
fref = fin / (1 << refdiv);
/* Use simple heuristic approach to find a configuration that
* should work for most input clocks.
*/
fast_clk = 0;
fout = fll->fout;
frac = fout % fref;
if (fref < MADERA_FLLHJ_LOW_THRESH) {
lockdet_thr = 2;
gains = MADERA_FLLHJ_LOW_GAINS;
if (frac)
fbdiv = 256;
else
fbdiv = 4;
} else if (fref < MADERA_FLLHJ_MID_THRESH) {
lockdet_thr = 8;
gains = MADERA_FLLHJ_MID_GAINS;
fbdiv = 1;
} else {
lockdet_thr = 8;
gains = MADERA_FLLHJ_HIGH_GAINS;
fbdiv = 1;
/* For high speed input clocks, enable 300MHz fast oscillator
* when we're in fractional divider mode.
*/
if (frac) {
fast_clk = 0x3;
fout = fll->fout * 6;
}
}
/* Use high performance mode for fractional configurations. */
if (frac) {
hp = 0x3;
min_n = MADERA_FLLHJ_FRAC_MIN_N;
max_n = MADERA_FLLHJ_FRAC_MAX_N;
} else {
hp = 0x0;
min_n = MADERA_FLLHJ_INT_MIN_N;
max_n = MADERA_FLLHJ_INT_MAX_N;
}
ratio = fout / fref;
madera_fll_dbg(fll, "refdiv=%d, fref=%d, frac:%d\n",
refdiv, fref, frac);
while (ratio / fbdiv < min_n) {
fbdiv /= 2;
if (fbdiv < 1) {
madera_fll_err(fll, "FBDIV (%d) must be >= 1\n", fbdiv);
return -EINVAL;
}
}
while (frac && (ratio / fbdiv > max_n)) {
fbdiv *= 2;
if (fbdiv >= 1024) {
madera_fll_err(fll, "FBDIV (%u) >= 1024\n", fbdiv);
return -EINVAL;
}
}
madera_fll_dbg(fll, "lockdet=%d, hp=0x%x, fbdiv:%d\n",
lockdet_thr, hp, fbdiv);
/* Calculate N.K values */
fllgcd = gcd(fout, fbdiv * fref);
num = fout / fllgcd;
lambda = (fref * fbdiv) / fllgcd;
fll_n = num / lambda;
theta = num % lambda;
madera_fll_dbg(fll, "fll_n=%d, gcd=%d, theta=%d, lambda=%d\n",
fll_n, fllgcd, theta, lambda);
/* Some sanity checks before any registers are written. */
if (fll_n < min_n || fll_n > max_n) {
madera_fll_err(fll, "N not in valid %s mode range %d-%d: %d\n",
frac ? "fractional" : "integer", min_n, max_n,
fll_n);
return -EINVAL;
}
if (fbdiv < 1 || (frac && fbdiv >= 1024) || (!frac && fbdiv >= 256)) {
madera_fll_err(fll, "Invalid fbdiv for %s mode (%u)\n",
frac ? "fractional" : "integer", fbdiv);
return -EINVAL;
}
/* clear the ctrl_upd bit to guarantee we write to it later. */
regmap_write(madera->regmap,
fll->base + MADERA_FLL_CONTROL_2_OFFS,
fll_n << MADERA_FLL1_N_SHIFT);
regmap_update_bits(madera->regmap,
fll->base + MADERA_FLL_CONTROL_3_OFFS,
MADERA_FLL1_THETA_MASK,
theta << MADERA_FLL1_THETA_SHIFT);
regmap_update_bits(madera->regmap,
fll->base + MADERA_FLL_CONTROL_4_OFFS,
MADERA_FLL1_LAMBDA_MASK,
lambda << MADERA_FLL1_LAMBDA_SHIFT);
regmap_update_bits(madera->regmap,
fll->base + MADERA_FLL_CONTROL_5_OFFS,
MADERA_FLL1_FB_DIV_MASK,
fbdiv << MADERA_FLL1_FB_DIV_SHIFT);
regmap_update_bits(madera->regmap,
fll->base + MADERA_FLL_CONTROL_6_OFFS,
MADERA_FLL1_REFCLK_DIV_MASK,
refdiv << MADERA_FLL1_REFCLK_DIV_SHIFT);
regmap_update_bits(madera->regmap,
fll->base + MADERA_FLL_GAIN_OFFS,
0xffff,
gains);
val = hp << MADERA_FLL1_HP_SHIFT;
val |= 1 << MADERA_FLL1_PHASEDET_ENA_SHIFT;
regmap_update_bits(madera->regmap,
fll->base + MADERA_FLL_CONTROL_10_OFFS,
MADERA_FLL1_HP_MASK | MADERA_FLL1_PHASEDET_ENA_MASK,
val);
regmap_update_bits(madera->regmap,
fll->base + MADERA_FLL_CONTROL_11_OFFS,
MADERA_FLL1_LOCKDET_THR_MASK,
lockdet_thr << MADERA_FLL1_LOCKDET_THR_SHIFT);
regmap_update_bits(madera->regmap,
fll->base + MADERA_FLL1_DIGITAL_TEST_1_OFFS,
MADERA_FLL1_SYNC_EFS_ENA_MASK |
MADERA_FLL1_CLK_VCO_FAST_SRC_MASK,
fast_clk);
return 0;
}
static int madera_fllhj_enable(struct madera_fll *fll)
{
struct madera *madera = fll->madera;
int already_enabled = madera_is_enabled_fll(fll, fll->base);
int ret;
if (already_enabled < 0)
return already_enabled;
if (!already_enabled)
pm_runtime_get_sync(madera->dev);
madera_fll_dbg(fll, "Enabling FLL, initially %s\n",
already_enabled ? "enabled" : "disabled");
/* FLLn_HOLD must be set before configuring any registers */
regmap_update_bits(fll->madera->regmap,
fll->base + MADERA_FLL_CONTROL_1_OFFS,
MADERA_FLL1_HOLD_MASK,
MADERA_FLL1_HOLD_MASK);
if (already_enabled)
madera_set_fllhj_clks(fll, fll->base, false);
/* Apply refclk */
ret = madera_fllhj_apply(fll, fll->ref_freq);
if (ret) {
madera_fll_err(fll, "Failed to set FLL: %d\n", ret);
goto out;
}
regmap_update_bits(madera->regmap,
fll->base + MADERA_FLL_CONTROL_1_OFFS,
CS47L92_FLL1_REFCLK_SRC_MASK,
fll->ref_src << CS47L92_FLL1_REFCLK_SRC_SHIFT);
madera_set_fllhj_clks(fll, fll->base, true);
regmap_update_bits(madera->regmap,
fll->base + MADERA_FLL_CONTROL_1_OFFS,
MADERA_FLL1_ENA_MASK,
MADERA_FLL1_ENA_MASK);
out:
regmap_update_bits(madera->regmap,
fll->base + MADERA_FLL_CONTROL_11_OFFS,
MADERA_FLL1_LOCKDET_MASK,
MADERA_FLL1_LOCKDET_MASK);
regmap_update_bits(madera->regmap,
fll->base + MADERA_FLL_CONTROL_2_OFFS,
MADERA_FLL1_CTRL_UPD_MASK,
MADERA_FLL1_CTRL_UPD_MASK);
/* Release the hold so that flln locks to external frequency */
regmap_update_bits(madera->regmap,
fll->base + MADERA_FLL_CONTROL_1_OFFS,
MADERA_FLL1_HOLD_MASK,
0);
if (!already_enabled)
madera_wait_for_fll(fll, true);
return 0;
}
static int madera_fllhj_validate(struct madera_fll *fll,
unsigned int ref_in,
unsigned int fout)
{
if (fout && !ref_in) {
madera_fll_err(fll, "fllout set without valid input clk\n");
return -EINVAL;
}
if (fll->fout && fout != fll->fout) {
madera_fll_err(fll, "Can't change output on active FLL\n");
return -EINVAL;
}
if (ref_in / MADERA_FLL_MAX_REFDIV > MADERA_FLLHJ_MAX_THRESH) {
madera_fll_err(fll, "Can't scale %dMHz to <=13MHz\n", ref_in);
return -EINVAL;
}
return 0;
}
int madera_fllhj_set_refclk(struct madera_fll *fll, int source,
unsigned int fin, unsigned int fout)
{
int ret = 0;
/* To remain consistent with previous FLLs, we expect fout to be
* provided in the form of the required sysclk rate, which is
* 2x the calculated fll out.
*/
if (fout)
fout /= 2;
if (fll->ref_src == source && fll->ref_freq == fin &&
fll->fout == fout)
return 0;
if (fin && fout && madera_fllhj_validate(fll, fin, fout))
return -EINVAL;
fll->ref_src = source;
fll->ref_freq = fin;
fll->fout = fout;
if (fout)
ret = madera_fllhj_enable(fll);
else
madera_fllhj_disable(fll);
return ret;
}
EXPORT_SYMBOL_GPL(madera_fllhj_set_refclk);
/**
* madera_set_output_mode - Set the mode of the specified output
*
* @component: Device to configure
* @output: Output number
* @differential: True to set the output to differential mode
*
* Some systems use external analogue switches to connect more
* analogue devices to the CODEC than are supported by the device. In
* some systems this requires changing the switched output from single
* ended to differential mode dynamically at runtime, an operation
* supported using this function.
*
* Most systems have a single static configuration and should use
* platform data instead.
*/
int madera_set_output_mode(struct snd_soc_component *component, int output,
bool differential)
{
unsigned int reg, val;
int ret;
if (output < 1 || output > MADERA_MAX_OUTPUT)
return -EINVAL;
reg = MADERA_OUTPUT_PATH_CONFIG_1L + (output - 1) * 8;
if (differential)
val = MADERA_OUT1_MONO;
else
val = 0;
ret = snd_soc_component_update_bits(component, reg, MADERA_OUT1_MONO,
val);
if (ret < 0)
return ret;
else
return 0;
}
EXPORT_SYMBOL_GPL(madera_set_output_mode);
static bool madera_eq_filter_unstable(bool mode, __be16 _a, __be16 _b)
{
s16 a = be16_to_cpu(_a);
s16 b = be16_to_cpu(_b);
if (!mode) {
return abs(a) >= 4096;
} else {
if (abs(b) >= 4096)
return true;
return (abs((a << 16) / (4096 - b)) >= 4096 << 4);
}
}
int madera_eq_coeff_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct madera_priv *priv = snd_soc_component_get_drvdata(component);
struct madera *madera = priv->madera;
struct soc_bytes *params = (void *)kcontrol->private_value;
unsigned int val;
__be16 *data;
int len;
int ret;
len = params->num_regs * regmap_get_val_bytes(madera->regmap);
data = kmemdup(ucontrol->value.bytes.data, len, GFP_KERNEL | GFP_DMA);
if (!data)
return -ENOMEM;
data[0] &= cpu_to_be16(MADERA_EQ1_B1_MODE);
if (madera_eq_filter_unstable(!!data[0], data[1], data[2]) ||
madera_eq_filter_unstable(true, data[4], data[5]) ||
madera_eq_filter_unstable(true, data[8], data[9]) ||
madera_eq_filter_unstable(true, data[12], data[13]) ||
madera_eq_filter_unstable(false, data[16], data[17])) {
dev_err(madera->dev, "Rejecting unstable EQ coefficients\n");
ret = -EINVAL;
goto out;
}
ret = regmap_read(madera->regmap, params->base, &val);
if (ret != 0)
goto out;
val &= ~MADERA_EQ1_B1_MODE;
data[0] |= cpu_to_be16(val);
ret = regmap_raw_write(madera->regmap, params->base, data, len);
out:
kfree(data);
return ret;
}
EXPORT_SYMBOL_GPL(madera_eq_coeff_put);
int madera_lhpf_coeff_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct madera_priv *priv = snd_soc_component_get_drvdata(component);
struct madera *madera = priv->madera;
__be16 *data = (__be16 *)ucontrol->value.bytes.data;
s16 val = be16_to_cpu(*data);
if (abs(val) >= 4096) {
dev_err(madera->dev, "Rejecting unstable LHPF coefficients\n");
return -EINVAL;
}
return snd_soc_bytes_put(kcontrol, ucontrol);
}
EXPORT_SYMBOL_GPL(madera_lhpf_coeff_put);
MODULE_SOFTDEP("pre: madera");
MODULE_DESCRIPTION("ASoC Cirrus Logic Madera codec support");
MODULE_AUTHOR("Charles Keepax <[email protected]>");
MODULE_AUTHOR("Richard Fitzgerald <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/madera.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* wm8996.c - WM8996 audio codec interface
*
* Copyright 2011-2 Wolfson Microelectronics PLC.
* Author: Mark Brown <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/gcd.h>
#include <linux/gpio/driver.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <linux/workqueue.h>
#include <sound/core.h>
#include <sound/jack.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <trace/events/asoc.h>
#include <sound/wm8996.h>
#include "wm8996.h"
#define WM8996_AIFS 2
#define HPOUT1L 1
#define HPOUT1R 2
#define HPOUT2L 4
#define HPOUT2R 8
#define WM8996_NUM_SUPPLIES 3
static const char *wm8996_supply_names[WM8996_NUM_SUPPLIES] = {
"DBVDD",
"AVDD1",
"AVDD2",
};
struct wm8996_priv {
struct device *dev;
struct regmap *regmap;
struct snd_soc_component *component;
int ldo1ena;
int sysclk;
int sysclk_src;
int fll_src;
int fll_fref;
int fll_fout;
struct completion fll_lock;
u16 dcs_pending;
struct completion dcs_done;
u16 hpout_ena;
u16 hpout_pending;
struct regulator_bulk_data supplies[WM8996_NUM_SUPPLIES];
struct notifier_block disable_nb[WM8996_NUM_SUPPLIES];
int bg_ena;
struct wm8996_pdata pdata;
int rx_rate[WM8996_AIFS];
int bclk_rate[WM8996_AIFS];
/* Platform dependant ReTune mobile configuration */
int num_retune_mobile_texts;
const char **retune_mobile_texts;
int retune_mobile_cfg[2];
struct soc_enum retune_mobile_enum;
struct snd_soc_jack *jack;
bool detecting;
bool jack_mic;
int jack_flips;
wm8996_polarity_fn polarity_cb;
#ifdef CONFIG_GPIOLIB
struct gpio_chip gpio_chip;
#endif
};
/* We can't use the same notifier block for more than one supply and
* there's no way I can see to get from a callback to the caller
* except container_of().
*/
#define WM8996_REGULATOR_EVENT(n) \
static int wm8996_regulator_event_##n(struct notifier_block *nb, \
unsigned long event, void *data) \
{ \
struct wm8996_priv *wm8996 = container_of(nb, struct wm8996_priv, \
disable_nb[n]); \
if (event & REGULATOR_EVENT_DISABLE) { \
regcache_mark_dirty(wm8996->regmap); \
} \
return 0; \
}
WM8996_REGULATOR_EVENT(0)
WM8996_REGULATOR_EVENT(1)
WM8996_REGULATOR_EVENT(2)
static const struct reg_default wm8996_reg[] = {
{ WM8996_POWER_MANAGEMENT_1, 0x0 },
{ WM8996_POWER_MANAGEMENT_2, 0x0 },
{ WM8996_POWER_MANAGEMENT_3, 0x0 },
{ WM8996_POWER_MANAGEMENT_4, 0x0 },
{ WM8996_POWER_MANAGEMENT_5, 0x0 },
{ WM8996_POWER_MANAGEMENT_6, 0x0 },
{ WM8996_POWER_MANAGEMENT_7, 0x10 },
{ WM8996_POWER_MANAGEMENT_8, 0x0 },
{ WM8996_LEFT_LINE_INPUT_VOLUME, 0x0 },
{ WM8996_RIGHT_LINE_INPUT_VOLUME, 0x0 },
{ WM8996_LINE_INPUT_CONTROL, 0x0 },
{ WM8996_DAC1_HPOUT1_VOLUME, 0x88 },
{ WM8996_DAC2_HPOUT2_VOLUME, 0x88 },
{ WM8996_DAC1_LEFT_VOLUME, 0x2c0 },
{ WM8996_DAC1_RIGHT_VOLUME, 0x2c0 },
{ WM8996_DAC2_LEFT_VOLUME, 0x2c0 },
{ WM8996_DAC2_RIGHT_VOLUME, 0x2c0 },
{ WM8996_OUTPUT1_LEFT_VOLUME, 0x80 },
{ WM8996_OUTPUT1_RIGHT_VOLUME, 0x80 },
{ WM8996_OUTPUT2_LEFT_VOLUME, 0x80 },
{ WM8996_OUTPUT2_RIGHT_VOLUME, 0x80 },
{ WM8996_MICBIAS_1, 0x39 },
{ WM8996_MICBIAS_2, 0x39 },
{ WM8996_LDO_1, 0x3 },
{ WM8996_LDO_2, 0x13 },
{ WM8996_ACCESSORY_DETECT_MODE_1, 0x4 },
{ WM8996_ACCESSORY_DETECT_MODE_2, 0x0 },
{ WM8996_HEADPHONE_DETECT_1, 0x20 },
{ WM8996_HEADPHONE_DETECT_2, 0x0 },
{ WM8996_MIC_DETECT_1, 0x7600 },
{ WM8996_MIC_DETECT_2, 0xbf },
{ WM8996_CHARGE_PUMP_1, 0x1f25 },
{ WM8996_CHARGE_PUMP_2, 0xab19 },
{ WM8996_DC_SERVO_1, 0x0 },
{ WM8996_DC_SERVO_3, 0x0 },
{ WM8996_DC_SERVO_5, 0x2a2a },
{ WM8996_DC_SERVO_6, 0x0 },
{ WM8996_DC_SERVO_7, 0x0 },
{ WM8996_ANALOGUE_HP_1, 0x0 },
{ WM8996_ANALOGUE_HP_2, 0x0 },
{ WM8996_CONTROL_INTERFACE_1, 0x8004 },
{ WM8996_WRITE_SEQUENCER_CTRL_1, 0x0 },
{ WM8996_WRITE_SEQUENCER_CTRL_2, 0x0 },
{ WM8996_AIF_CLOCKING_1, 0x0 },
{ WM8996_AIF_CLOCKING_2, 0x0 },
{ WM8996_CLOCKING_1, 0x10 },
{ WM8996_CLOCKING_2, 0x0 },
{ WM8996_AIF_RATE, 0x83 },
{ WM8996_FLL_CONTROL_1, 0x0 },
{ WM8996_FLL_CONTROL_2, 0x0 },
{ WM8996_FLL_CONTROL_3, 0x0 },
{ WM8996_FLL_CONTROL_4, 0x5dc0 },
{ WM8996_FLL_CONTROL_5, 0xc84 },
{ WM8996_FLL_EFS_1, 0x0 },
{ WM8996_FLL_EFS_2, 0x2 },
{ WM8996_AIF1_CONTROL, 0x0 },
{ WM8996_AIF1_BCLK, 0x0 },
{ WM8996_AIF1_TX_LRCLK_1, 0x80 },
{ WM8996_AIF1_TX_LRCLK_2, 0x8 },
{ WM8996_AIF1_RX_LRCLK_1, 0x80 },
{ WM8996_AIF1_RX_LRCLK_2, 0x0 },
{ WM8996_AIF1TX_DATA_CONFIGURATION_1, 0x1818 },
{ WM8996_AIF1TX_DATA_CONFIGURATION_2, 0 },
{ WM8996_AIF1RX_DATA_CONFIGURATION, 0x1818 },
{ WM8996_AIF1TX_CHANNEL_0_CONFIGURATION, 0x0 },
{ WM8996_AIF1TX_CHANNEL_1_CONFIGURATION, 0x0 },
{ WM8996_AIF1TX_CHANNEL_2_CONFIGURATION, 0x0 },
{ WM8996_AIF1TX_CHANNEL_3_CONFIGURATION, 0x0 },
{ WM8996_AIF1TX_CHANNEL_4_CONFIGURATION, 0x0 },
{ WM8996_AIF1TX_CHANNEL_5_CONFIGURATION, 0x0 },
{ WM8996_AIF1RX_CHANNEL_0_CONFIGURATION, 0x0 },
{ WM8996_AIF1RX_CHANNEL_1_CONFIGURATION, 0x0 },
{ WM8996_AIF1RX_CHANNEL_2_CONFIGURATION, 0x0 },
{ WM8996_AIF1RX_CHANNEL_3_CONFIGURATION, 0x0 },
{ WM8996_AIF1RX_CHANNEL_4_CONFIGURATION, 0x0 },
{ WM8996_AIF1RX_CHANNEL_5_CONFIGURATION, 0x0 },
{ WM8996_AIF1RX_MONO_CONFIGURATION, 0x0 },
{ WM8996_AIF1TX_TEST, 0x7 },
{ WM8996_AIF2_CONTROL, 0x0 },
{ WM8996_AIF2_BCLK, 0x0 },
{ WM8996_AIF2_TX_LRCLK_1, 0x80 },
{ WM8996_AIF2_TX_LRCLK_2, 0x8 },
{ WM8996_AIF2_RX_LRCLK_1, 0x80 },
{ WM8996_AIF2_RX_LRCLK_2, 0x0 },
{ WM8996_AIF2TX_DATA_CONFIGURATION_1, 0x1818 },
{ WM8996_AIF2RX_DATA_CONFIGURATION, 0x1818 },
{ WM8996_AIF2RX_DATA_CONFIGURATION, 0x0 },
{ WM8996_AIF2TX_CHANNEL_0_CONFIGURATION, 0x0 },
{ WM8996_AIF2TX_CHANNEL_1_CONFIGURATION, 0x0 },
{ WM8996_AIF2RX_CHANNEL_0_CONFIGURATION, 0x0 },
{ WM8996_AIF2RX_CHANNEL_1_CONFIGURATION, 0x0 },
{ WM8996_AIF2RX_MONO_CONFIGURATION, 0x0 },
{ WM8996_AIF2TX_TEST, 0x1 },
{ WM8996_DSP1_TX_LEFT_VOLUME, 0xc0 },
{ WM8996_DSP1_TX_RIGHT_VOLUME, 0xc0 },
{ WM8996_DSP1_RX_LEFT_VOLUME, 0xc0 },
{ WM8996_DSP1_RX_RIGHT_VOLUME, 0xc0 },
{ WM8996_DSP1_TX_FILTERS, 0x2000 },
{ WM8996_DSP1_RX_FILTERS_1, 0x200 },
{ WM8996_DSP1_RX_FILTERS_2, 0x10 },
{ WM8996_DSP1_DRC_1, 0x98 },
{ WM8996_DSP1_DRC_2, 0x845 },
{ WM8996_DSP1_RX_EQ_GAINS_1, 0x6318 },
{ WM8996_DSP1_RX_EQ_GAINS_2, 0x6300 },
{ WM8996_DSP1_RX_EQ_BAND_1_A, 0xfca },
{ WM8996_DSP1_RX_EQ_BAND_1_B, 0x400 },
{ WM8996_DSP1_RX_EQ_BAND_1_PG, 0xd8 },
{ WM8996_DSP1_RX_EQ_BAND_2_A, 0x1eb5 },
{ WM8996_DSP1_RX_EQ_BAND_2_B, 0xf145 },
{ WM8996_DSP1_RX_EQ_BAND_2_C, 0xb75 },
{ WM8996_DSP1_RX_EQ_BAND_2_PG, 0x1c5 },
{ WM8996_DSP1_RX_EQ_BAND_3_A, 0x1c58 },
{ WM8996_DSP1_RX_EQ_BAND_3_B, 0xf373 },
{ WM8996_DSP1_RX_EQ_BAND_3_C, 0xa54 },
{ WM8996_DSP1_RX_EQ_BAND_3_PG, 0x558 },
{ WM8996_DSP1_RX_EQ_BAND_4_A, 0x168e },
{ WM8996_DSP1_RX_EQ_BAND_4_B, 0xf829 },
{ WM8996_DSP1_RX_EQ_BAND_4_C, 0x7ad },
{ WM8996_DSP1_RX_EQ_BAND_4_PG, 0x1103 },
{ WM8996_DSP1_RX_EQ_BAND_5_A, 0x564 },
{ WM8996_DSP1_RX_EQ_BAND_5_B, 0x559 },
{ WM8996_DSP1_RX_EQ_BAND_5_PG, 0x4000 },
{ WM8996_DSP2_TX_LEFT_VOLUME, 0xc0 },
{ WM8996_DSP2_TX_RIGHT_VOLUME, 0xc0 },
{ WM8996_DSP2_RX_LEFT_VOLUME, 0xc0 },
{ WM8996_DSP2_RX_RIGHT_VOLUME, 0xc0 },
{ WM8996_DSP2_TX_FILTERS, 0x2000 },
{ WM8996_DSP2_RX_FILTERS_1, 0x200 },
{ WM8996_DSP2_RX_FILTERS_2, 0x10 },
{ WM8996_DSP2_DRC_1, 0x98 },
{ WM8996_DSP2_DRC_2, 0x845 },
{ WM8996_DSP2_RX_EQ_GAINS_1, 0x6318 },
{ WM8996_DSP2_RX_EQ_GAINS_2, 0x6300 },
{ WM8996_DSP2_RX_EQ_BAND_1_A, 0xfca },
{ WM8996_DSP2_RX_EQ_BAND_1_B, 0x400 },
{ WM8996_DSP2_RX_EQ_BAND_1_PG, 0xd8 },
{ WM8996_DSP2_RX_EQ_BAND_2_A, 0x1eb5 },
{ WM8996_DSP2_RX_EQ_BAND_2_B, 0xf145 },
{ WM8996_DSP2_RX_EQ_BAND_2_C, 0xb75 },
{ WM8996_DSP2_RX_EQ_BAND_2_PG, 0x1c5 },
{ WM8996_DSP2_RX_EQ_BAND_3_A, 0x1c58 },
{ WM8996_DSP2_RX_EQ_BAND_3_B, 0xf373 },
{ WM8996_DSP2_RX_EQ_BAND_3_C, 0xa54 },
{ WM8996_DSP2_RX_EQ_BAND_3_PG, 0x558 },
{ WM8996_DSP2_RX_EQ_BAND_4_A, 0x168e },
{ WM8996_DSP2_RX_EQ_BAND_4_B, 0xf829 },
{ WM8996_DSP2_RX_EQ_BAND_4_C, 0x7ad },
{ WM8996_DSP2_RX_EQ_BAND_4_PG, 0x1103 },
{ WM8996_DSP2_RX_EQ_BAND_5_A, 0x564 },
{ WM8996_DSP2_RX_EQ_BAND_5_B, 0x559 },
{ WM8996_DSP2_RX_EQ_BAND_5_PG, 0x4000 },
{ WM8996_DAC1_MIXER_VOLUMES, 0x0 },
{ WM8996_DAC1_LEFT_MIXER_ROUTING, 0x0 },
{ WM8996_DAC1_RIGHT_MIXER_ROUTING, 0x0 },
{ WM8996_DAC2_MIXER_VOLUMES, 0x0 },
{ WM8996_DAC2_LEFT_MIXER_ROUTING, 0x0 },
{ WM8996_DAC2_RIGHT_MIXER_ROUTING, 0x0 },
{ WM8996_DSP1_TX_LEFT_MIXER_ROUTING, 0x0 },
{ WM8996_DSP1_TX_RIGHT_MIXER_ROUTING, 0x0 },
{ WM8996_DSP2_TX_LEFT_MIXER_ROUTING, 0x0 },
{ WM8996_DSP2_TX_RIGHT_MIXER_ROUTING, 0x0 },
{ WM8996_DSP_TX_MIXER_SELECT, 0x0 },
{ WM8996_DAC_SOFTMUTE, 0x0 },
{ WM8996_OVERSAMPLING, 0xd },
{ WM8996_SIDETONE, 0x1040 },
{ WM8996_GPIO_1, 0xa101 },
{ WM8996_GPIO_2, 0xa101 },
{ WM8996_GPIO_3, 0xa101 },
{ WM8996_GPIO_4, 0xa101 },
{ WM8996_GPIO_5, 0xa101 },
{ WM8996_PULL_CONTROL_1, 0x0 },
{ WM8996_PULL_CONTROL_2, 0x140 },
{ WM8996_INTERRUPT_STATUS_1_MASK, 0x1f },
{ WM8996_INTERRUPT_STATUS_2_MASK, 0x1ecf },
{ WM8996_LEFT_PDM_SPEAKER, 0x0 },
{ WM8996_RIGHT_PDM_SPEAKER, 0x1 },
{ WM8996_PDM_SPEAKER_MUTE_SEQUENCE, 0x69 },
{ WM8996_PDM_SPEAKER_VOLUME, 0x66 },
};
static const DECLARE_TLV_DB_SCALE(inpga_tlv, 0, 100, 0);
static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
static const DECLARE_TLV_DB_SCALE(out_digital_tlv, -1200, 150, 0);
static const DECLARE_TLV_DB_SCALE(out_tlv, -900, 75, 0);
static const DECLARE_TLV_DB_SCALE(spk_tlv, -900, 150, 0);
static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
static const DECLARE_TLV_DB_SCALE(threedstereo_tlv, -1600, 183, 1);
static const char *sidetone_hpf_text[] = {
"2.9kHz", "1.5kHz", "735Hz", "403Hz", "196Hz", "98Hz", "49Hz"
};
static SOC_ENUM_SINGLE_DECL(sidetone_hpf,
WM8996_SIDETONE, 7, sidetone_hpf_text);
static const char *hpf_mode_text[] = {
"HiFi", "Custom", "Voice"
};
static SOC_ENUM_SINGLE_DECL(dsp1tx_hpf_mode,
WM8996_DSP1_TX_FILTERS, 3, hpf_mode_text);
static SOC_ENUM_SINGLE_DECL(dsp2tx_hpf_mode,
WM8996_DSP2_TX_FILTERS, 3, hpf_mode_text);
static const char *hpf_cutoff_text[] = {
"50Hz", "75Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
};
static SOC_ENUM_SINGLE_DECL(dsp1tx_hpf_cutoff,
WM8996_DSP1_TX_FILTERS, 0, hpf_cutoff_text);
static SOC_ENUM_SINGLE_DECL(dsp2tx_hpf_cutoff,
WM8996_DSP2_TX_FILTERS, 0, hpf_cutoff_text);
static void wm8996_set_retune_mobile(struct snd_soc_component *component, int block)
{
struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
struct wm8996_pdata *pdata = &wm8996->pdata;
int base, best, best_val, save, i, cfg, iface;
if (!wm8996->num_retune_mobile_texts)
return;
switch (block) {
case 0:
base = WM8996_DSP1_RX_EQ_GAINS_1;
if (snd_soc_component_read(component, WM8996_POWER_MANAGEMENT_8) &
WM8996_DSP1RX_SRC)
iface = 1;
else
iface = 0;
break;
case 1:
base = WM8996_DSP1_RX_EQ_GAINS_2;
if (snd_soc_component_read(component, WM8996_POWER_MANAGEMENT_8) &
WM8996_DSP2RX_SRC)
iface = 1;
else
iface = 0;
break;
default:
return;
}
/* Find the version of the currently selected configuration
* with the nearest sample rate. */
cfg = wm8996->retune_mobile_cfg[block];
best = 0;
best_val = INT_MAX;
for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
if (strcmp(pdata->retune_mobile_cfgs[i].name,
wm8996->retune_mobile_texts[cfg]) == 0 &&
abs(pdata->retune_mobile_cfgs[i].rate
- wm8996->rx_rate[iface]) < best_val) {
best = i;
best_val = abs(pdata->retune_mobile_cfgs[i].rate
- wm8996->rx_rate[iface]);
}
}
dev_dbg(component->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
block,
pdata->retune_mobile_cfgs[best].name,
pdata->retune_mobile_cfgs[best].rate,
wm8996->rx_rate[iface]);
/* The EQ will be disabled while reconfiguring it, remember the
* current configuration.
*/
save = snd_soc_component_read(component, base);
save &= WM8996_DSP1RX_EQ_ENA;
for (i = 0; i < ARRAY_SIZE(pdata->retune_mobile_cfgs[best].regs); i++)
snd_soc_component_update_bits(component, base + i, 0xffff,
pdata->retune_mobile_cfgs[best].regs[i]);
snd_soc_component_update_bits(component, base, WM8996_DSP1RX_EQ_ENA, save);
}
/* Icky as hell but saves code duplication */
static int wm8996_get_retune_mobile_block(const char *name)
{
if (strcmp(name, "DSP1 EQ Mode") == 0)
return 0;
if (strcmp(name, "DSP2 EQ Mode") == 0)
return 1;
return -EINVAL;
}
static int wm8996_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
struct wm8996_pdata *pdata = &wm8996->pdata;
int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
int value = ucontrol->value.enumerated.item[0];
if (block < 0)
return block;
if (value >= pdata->num_retune_mobile_cfgs)
return -EINVAL;
wm8996->retune_mobile_cfg[block] = value;
wm8996_set_retune_mobile(component, block);
return 0;
}
static int wm8996_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
if (block < 0)
return block;
ucontrol->value.enumerated.item[0] = wm8996->retune_mobile_cfg[block];
return 0;
}
static const struct snd_kcontrol_new wm8996_snd_controls[] = {
SOC_DOUBLE_R_TLV("Capture Volume", WM8996_LEFT_LINE_INPUT_VOLUME,
WM8996_RIGHT_LINE_INPUT_VOLUME, 0, 31, 0, inpga_tlv),
SOC_DOUBLE_R("Capture ZC Switch", WM8996_LEFT_LINE_INPUT_VOLUME,
WM8996_RIGHT_LINE_INPUT_VOLUME, 5, 1, 0),
SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8996_DAC1_MIXER_VOLUMES,
0, 5, 24, 0, sidetone_tlv),
SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8996_DAC2_MIXER_VOLUMES,
0, 5, 24, 0, sidetone_tlv),
SOC_SINGLE("Sidetone LPF Switch", WM8996_SIDETONE, 12, 1, 0),
SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf),
SOC_SINGLE("Sidetone HPF Switch", WM8996_SIDETONE, 6, 1, 0),
SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8996_DSP1_TX_LEFT_VOLUME,
WM8996_DSP1_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8996_DSP2_TX_LEFT_VOLUME,
WM8996_DSP2_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
SOC_SINGLE("DSP1 Capture Notch Filter Switch", WM8996_DSP1_TX_FILTERS,
13, 1, 0),
SOC_DOUBLE("DSP1 Capture HPF Switch", WM8996_DSP1_TX_FILTERS, 12, 11, 1, 0),
SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_mode),
SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf_cutoff),
SOC_SINGLE("DSP2 Capture Notch Filter Switch", WM8996_DSP2_TX_FILTERS,
13, 1, 0),
SOC_DOUBLE("DSP2 Capture HPF Switch", WM8996_DSP2_TX_FILTERS, 12, 11, 1, 0),
SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_mode),
SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf_cutoff),
SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM8996_DSP1_RX_LEFT_VOLUME,
WM8996_DSP1_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
SOC_SINGLE("DSP1 Playback Switch", WM8996_DSP1_RX_FILTERS_1, 9, 1, 1),
SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM8996_DSP2_RX_LEFT_VOLUME,
WM8996_DSP2_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
SOC_SINGLE("DSP2 Playback Switch", WM8996_DSP2_RX_FILTERS_1, 9, 1, 1),
SOC_DOUBLE_R_TLV("DAC1 Volume", WM8996_DAC1_LEFT_VOLUME,
WM8996_DAC1_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
SOC_DOUBLE_R("DAC1 Switch", WM8996_DAC1_LEFT_VOLUME,
WM8996_DAC1_RIGHT_VOLUME, 9, 1, 1),
SOC_DOUBLE_R_TLV("DAC2 Volume", WM8996_DAC2_LEFT_VOLUME,
WM8996_DAC2_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
SOC_DOUBLE_R("DAC2 Switch", WM8996_DAC2_LEFT_VOLUME,
WM8996_DAC2_RIGHT_VOLUME, 9, 1, 1),
SOC_SINGLE("Speaker High Performance Switch", WM8996_OVERSAMPLING, 3, 1, 0),
SOC_SINGLE("DMIC High Performance Switch", WM8996_OVERSAMPLING, 2, 1, 0),
SOC_SINGLE("ADC High Performance Switch", WM8996_OVERSAMPLING, 1, 1, 0),
SOC_SINGLE("DAC High Performance Switch", WM8996_OVERSAMPLING, 0, 1, 0),
SOC_SINGLE("DAC Soft Mute Switch", WM8996_DAC_SOFTMUTE, 1, 1, 0),
SOC_SINGLE("DAC Slow Soft Mute Switch", WM8996_DAC_SOFTMUTE, 0, 1, 0),
SOC_SINGLE("DSP1 3D Stereo Switch", WM8996_DSP1_RX_FILTERS_2, 8, 1, 0),
SOC_SINGLE("DSP2 3D Stereo Switch", WM8996_DSP2_RX_FILTERS_2, 8, 1, 0),
SOC_SINGLE_TLV("DSP1 3D Stereo Volume", WM8996_DSP1_RX_FILTERS_2, 10, 15,
0, threedstereo_tlv),
SOC_SINGLE_TLV("DSP2 3D Stereo Volume", WM8996_DSP2_RX_FILTERS_2, 10, 15,
0, threedstereo_tlv),
SOC_DOUBLE_TLV("Digital Output 1 Volume", WM8996_DAC1_HPOUT1_VOLUME, 0, 4,
8, 0, out_digital_tlv),
SOC_DOUBLE_TLV("Digital Output 2 Volume", WM8996_DAC2_HPOUT2_VOLUME, 0, 4,
8, 0, out_digital_tlv),
SOC_DOUBLE_R_TLV("Output 1 Volume", WM8996_OUTPUT1_LEFT_VOLUME,
WM8996_OUTPUT1_RIGHT_VOLUME, 0, 12, 0, out_tlv),
SOC_DOUBLE_R("Output 1 ZC Switch", WM8996_OUTPUT1_LEFT_VOLUME,
WM8996_OUTPUT1_RIGHT_VOLUME, 7, 1, 0),
SOC_DOUBLE_R_TLV("Output 2 Volume", WM8996_OUTPUT2_LEFT_VOLUME,
WM8996_OUTPUT2_RIGHT_VOLUME, 0, 12, 0, out_tlv),
SOC_DOUBLE_R("Output 2 ZC Switch", WM8996_OUTPUT2_LEFT_VOLUME,
WM8996_OUTPUT2_RIGHT_VOLUME, 7, 1, 0),
SOC_DOUBLE_TLV("Speaker Volume", WM8996_PDM_SPEAKER_VOLUME, 0, 4, 8, 0,
spk_tlv),
SOC_DOUBLE_R("Speaker Switch", WM8996_LEFT_PDM_SPEAKER,
WM8996_RIGHT_PDM_SPEAKER, 3, 1, 1),
SOC_DOUBLE_R("Speaker ZC Switch", WM8996_LEFT_PDM_SPEAKER,
WM8996_RIGHT_PDM_SPEAKER, 2, 1, 0),
SOC_SINGLE("DSP1 EQ Switch", WM8996_DSP1_RX_EQ_GAINS_1, 0, 1, 0),
SOC_SINGLE("DSP2 EQ Switch", WM8996_DSP2_RX_EQ_GAINS_1, 0, 1, 0),
SOC_SINGLE("DSP1 DRC TXL Switch", WM8996_DSP1_DRC_1, 0, 1, 0),
SOC_SINGLE("DSP1 DRC TXR Switch", WM8996_DSP1_DRC_1, 1, 1, 0),
SOC_SINGLE("DSP1 DRC RX Switch", WM8996_DSP1_DRC_1, 2, 1, 0),
SND_SOC_BYTES_MASK("DSP1 DRC", WM8996_DSP1_DRC_1, 5,
WM8996_DSP1RX_DRC_ENA | WM8996_DSP1TXL_DRC_ENA |
WM8996_DSP1TXR_DRC_ENA),
SOC_SINGLE("DSP2 DRC TXL Switch", WM8996_DSP2_DRC_1, 0, 1, 0),
SOC_SINGLE("DSP2 DRC TXR Switch", WM8996_DSP2_DRC_1, 1, 1, 0),
SOC_SINGLE("DSP2 DRC RX Switch", WM8996_DSP2_DRC_1, 2, 1, 0),
SND_SOC_BYTES_MASK("DSP2 DRC", WM8996_DSP2_DRC_1, 5,
WM8996_DSP2RX_DRC_ENA | WM8996_DSP2TXL_DRC_ENA |
WM8996_DSP2TXR_DRC_ENA),
};
static const struct snd_kcontrol_new wm8996_eq_controls[] = {
SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 11, 31, 0,
eq_tlv),
SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 6, 31, 0,
eq_tlv),
SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 1, 31, 0,
eq_tlv),
SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 11, 31, 0,
eq_tlv),
SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 6, 31, 0,
eq_tlv),
SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 11, 31, 0,
eq_tlv),
SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 6, 31, 0,
eq_tlv),
SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 1, 31, 0,
eq_tlv),
SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 11, 31, 0,
eq_tlv),
SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 6, 31, 0,
eq_tlv),
};
static void wm8996_bg_enable(struct snd_soc_component *component)
{
struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
wm8996->bg_ena++;
if (wm8996->bg_ena == 1) {
snd_soc_component_update_bits(component, WM8996_POWER_MANAGEMENT_1,
WM8996_BG_ENA, WM8996_BG_ENA);
msleep(2);
}
}
static void wm8996_bg_disable(struct snd_soc_component *component)
{
struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
wm8996->bg_ena--;
if (!wm8996->bg_ena)
snd_soc_component_update_bits(component, WM8996_POWER_MANAGEMENT_1,
WM8996_BG_ENA, 0);
}
static int bg_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
int ret = 0;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
wm8996_bg_enable(component);
break;
case SND_SOC_DAPM_POST_PMD:
wm8996_bg_disable(component);
break;
default:
WARN(1, "Invalid event %d\n", event);
ret = -EINVAL;
}
return ret;
}
static int cp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
switch (event) {
case SND_SOC_DAPM_POST_PMU:
msleep(5);
break;
default:
WARN(1, "Invalid event %d\n", event);
}
return 0;
}
static int rmv_short_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
/* Record which outputs we enabled */
switch (event) {
case SND_SOC_DAPM_PRE_PMD:
wm8996->hpout_pending &= ~w->shift;
break;
case SND_SOC_DAPM_PRE_PMU:
wm8996->hpout_pending |= w->shift;
break;
default:
WARN(1, "Invalid event %d\n", event);
return -EINVAL;
}
return 0;
}
static void wait_for_dc_servo(struct snd_soc_component *component, u16 mask)
{
struct i2c_client *i2c = to_i2c_client(component->dev);
struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
int ret;
unsigned long timeout = 200;
snd_soc_component_write(component, WM8996_DC_SERVO_2, mask);
/* Use the interrupt if possible */
do {
if (i2c->irq) {
timeout = wait_for_completion_timeout(&wm8996->dcs_done,
msecs_to_jiffies(200));
if (timeout == 0)
dev_err(component->dev, "DC servo timed out\n");
} else {
msleep(1);
timeout--;
}
ret = snd_soc_component_read(component, WM8996_DC_SERVO_2);
dev_dbg(component->dev, "DC servo state: %x\n", ret);
} while (timeout && ret & mask);
if (timeout == 0)
dev_err(component->dev, "DC servo timed out for %x\n", mask);
else
dev_dbg(component->dev, "DC servo complete for %x\n", mask);
}
static void wm8996_seq_notifier(struct snd_soc_component *component,
enum snd_soc_dapm_type event, int subseq)
{
struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
u16 val, mask;
/* Complete any pending DC servo starts */
if (wm8996->dcs_pending) {
dev_dbg(component->dev, "Starting DC servo for %x\n",
wm8996->dcs_pending);
/* Trigger a startup sequence */
wait_for_dc_servo(component, wm8996->dcs_pending
<< WM8996_DCS_TRIG_STARTUP_0_SHIFT);
wm8996->dcs_pending = 0;
}
if (wm8996->hpout_pending != wm8996->hpout_ena) {
dev_dbg(component->dev, "Applying RMV_SHORTs %x->%x\n",
wm8996->hpout_ena, wm8996->hpout_pending);
val = 0;
mask = 0;
if (wm8996->hpout_pending & HPOUT1L) {
val |= WM8996_HPOUT1L_RMV_SHORT | WM8996_HPOUT1L_OUTP;
mask |= WM8996_HPOUT1L_RMV_SHORT | WM8996_HPOUT1L_OUTP;
} else {
mask |= WM8996_HPOUT1L_RMV_SHORT |
WM8996_HPOUT1L_OUTP |
WM8996_HPOUT1L_DLY;
}
if (wm8996->hpout_pending & HPOUT1R) {
val |= WM8996_HPOUT1R_RMV_SHORT | WM8996_HPOUT1R_OUTP;
mask |= WM8996_HPOUT1R_RMV_SHORT | WM8996_HPOUT1R_OUTP;
} else {
mask |= WM8996_HPOUT1R_RMV_SHORT |
WM8996_HPOUT1R_OUTP |
WM8996_HPOUT1R_DLY;
}
snd_soc_component_update_bits(component, WM8996_ANALOGUE_HP_1, mask, val);
val = 0;
mask = 0;
if (wm8996->hpout_pending & HPOUT2L) {
val |= WM8996_HPOUT2L_RMV_SHORT | WM8996_HPOUT2L_OUTP;
mask |= WM8996_HPOUT2L_RMV_SHORT | WM8996_HPOUT2L_OUTP;
} else {
mask |= WM8996_HPOUT2L_RMV_SHORT |
WM8996_HPOUT2L_OUTP |
WM8996_HPOUT2L_DLY;
}
if (wm8996->hpout_pending & HPOUT2R) {
val |= WM8996_HPOUT2R_RMV_SHORT | WM8996_HPOUT2R_OUTP;
mask |= WM8996_HPOUT2R_RMV_SHORT | WM8996_HPOUT2R_OUTP;
} else {
mask |= WM8996_HPOUT2R_RMV_SHORT |
WM8996_HPOUT2R_OUTP |
WM8996_HPOUT2R_DLY;
}
snd_soc_component_update_bits(component, WM8996_ANALOGUE_HP_2, mask, val);
wm8996->hpout_ena = wm8996->hpout_pending;
}
}
static int dcs_start(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
wm8996->dcs_pending |= 1 << w->shift;
break;
default:
WARN(1, "Invalid event %d\n", event);
return -EINVAL;
}
return 0;
}
static const char *sidetone_text[] = {
"IN1", "IN2",
};
static SOC_ENUM_SINGLE_DECL(left_sidetone_enum,
WM8996_SIDETONE, 0, sidetone_text);
static const struct snd_kcontrol_new left_sidetone =
SOC_DAPM_ENUM("Left Sidetone", left_sidetone_enum);
static SOC_ENUM_SINGLE_DECL(right_sidetone_enum,
WM8996_SIDETONE, 1, sidetone_text);
static const struct snd_kcontrol_new right_sidetone =
SOC_DAPM_ENUM("Right Sidetone", right_sidetone_enum);
static const char *spk_text[] = {
"DAC1L", "DAC1R", "DAC2L", "DAC2R"
};
static SOC_ENUM_SINGLE_DECL(spkl_enum,
WM8996_LEFT_PDM_SPEAKER, 0, spk_text);
static const struct snd_kcontrol_new spkl_mux =
SOC_DAPM_ENUM("SPKL", spkl_enum);
static SOC_ENUM_SINGLE_DECL(spkr_enum,
WM8996_RIGHT_PDM_SPEAKER, 0, spk_text);
static const struct snd_kcontrol_new spkr_mux =
SOC_DAPM_ENUM("SPKR", spkr_enum);
static const char *dsp1rx_text[] = {
"AIF1", "AIF2"
};
static SOC_ENUM_SINGLE_DECL(dsp1rx_enum,
WM8996_POWER_MANAGEMENT_8, 0, dsp1rx_text);
static const struct snd_kcontrol_new dsp1rx =
SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum);
static const char *dsp2rx_text[] = {
"AIF2", "AIF1"
};
static SOC_ENUM_SINGLE_DECL(dsp2rx_enum,
WM8996_POWER_MANAGEMENT_8, 4, dsp2rx_text);
static const struct snd_kcontrol_new dsp2rx =
SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum);
static const char *aif2tx_text[] = {
"DSP2", "DSP1", "AIF1"
};
static SOC_ENUM_SINGLE_DECL(aif2tx_enum,
WM8996_POWER_MANAGEMENT_8, 6, aif2tx_text);
static const struct snd_kcontrol_new aif2tx =
SOC_DAPM_ENUM("AIF2TX", aif2tx_enum);
static const char *inmux_text[] = {
"ADC", "DMIC1", "DMIC2"
};
static SOC_ENUM_SINGLE_DECL(in1_enum,
WM8996_POWER_MANAGEMENT_7, 0, inmux_text);
static const struct snd_kcontrol_new in1_mux =
SOC_DAPM_ENUM("IN1 Mux", in1_enum);
static SOC_ENUM_SINGLE_DECL(in2_enum,
WM8996_POWER_MANAGEMENT_7, 4, inmux_text);
static const struct snd_kcontrol_new in2_mux =
SOC_DAPM_ENUM("IN2 Mux", in2_enum);
static const struct snd_kcontrol_new dac2r_mix[] = {
SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING,
5, 1, 0),
SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING,
4, 1, 0),
SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 1, 1, 0),
SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 0, 1, 0),
};
static const struct snd_kcontrol_new dac2l_mix[] = {
SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING,
5, 1, 0),
SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING,
4, 1, 0),
SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 1, 1, 0),
SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 0, 1, 0),
};
static const struct snd_kcontrol_new dac1r_mix[] = {
SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING,
5, 1, 0),
SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING,
4, 1, 0),
SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 1, 1, 0),
SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 0, 1, 0),
};
static const struct snd_kcontrol_new dac1l_mix[] = {
SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING,
5, 1, 0),
SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING,
4, 1, 0),
SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 1, 1, 0),
SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 0, 1, 0),
};
static const struct snd_kcontrol_new dsp1txl[] = {
SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING,
1, 1, 0),
SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING,
0, 1, 0),
};
static const struct snd_kcontrol_new dsp1txr[] = {
SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING,
1, 1, 0),
SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING,
0, 1, 0),
};
static const struct snd_kcontrol_new dsp2txl[] = {
SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING,
1, 1, 0),
SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING,
0, 1, 0),
};
static const struct snd_kcontrol_new dsp2txr[] = {
SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING,
1, 1, 0),
SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING,
0, 1, 0),
};
static const struct snd_soc_dapm_widget wm8996_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("IN1LN"),
SND_SOC_DAPM_INPUT("IN1LP"),
SND_SOC_DAPM_INPUT("IN1RN"),
SND_SOC_DAPM_INPUT("IN1RP"),
SND_SOC_DAPM_INPUT("IN2LN"),
SND_SOC_DAPM_INPUT("IN2LP"),
SND_SOC_DAPM_INPUT("IN2RN"),
SND_SOC_DAPM_INPUT("IN2RP"),
SND_SOC_DAPM_INPUT("DMIC1DAT"),
SND_SOC_DAPM_INPUT("DMIC2DAT"),
SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20, 0),
SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8996_AIF_CLOCKING_1, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8996_CLOCKING_1, 1, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8996_CLOCKING_1, 2, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8996_CHARGE_PUMP_1, 15, 0, cp_event,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY("Bandgap", SND_SOC_NOPM, 0, 0, bg_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("LDO2", WM8996_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICB1 Audio", WM8996_MICBIAS_1, 4, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICB2 Audio", WM8996_MICBIAS_2, 4, 1, NULL, 0),
SND_SOC_DAPM_MICBIAS("MICB2", WM8996_POWER_MANAGEMENT_1, 9, 0),
SND_SOC_DAPM_MICBIAS("MICB1", WM8996_POWER_MANAGEMENT_1, 8, 0),
SND_SOC_DAPM_PGA("IN1L PGA", WM8996_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA("IN1R PGA", WM8996_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
SND_SOC_DAPM_MUX("IN1L Mux", WM8996_POWER_MANAGEMENT_7, 2, 0, &in1_mux),
SND_SOC_DAPM_MUX("IN1R Mux", WM8996_POWER_MANAGEMENT_7, 3, 0, &in1_mux),
SND_SOC_DAPM_MUX("IN2L Mux", WM8996_POWER_MANAGEMENT_7, 6, 0, &in2_mux),
SND_SOC_DAPM_MUX("IN2R Mux", WM8996_POWER_MANAGEMENT_7, 7, 0, &in2_mux),
SND_SOC_DAPM_SUPPLY("DMIC2", WM8996_POWER_MANAGEMENT_7, 9, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DMIC1", WM8996_POWER_MANAGEMENT_7, 8, 0, NULL, 0),
SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8996_POWER_MANAGEMENT_3, 5, 0),
SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8996_POWER_MANAGEMENT_3, 4, 0),
SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8996_POWER_MANAGEMENT_3, 3, 0),
SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8996_POWER_MANAGEMENT_3, 2, 0),
SND_SOC_DAPM_ADC("ADCL", NULL, WM8996_POWER_MANAGEMENT_3, 1, 0),
SND_SOC_DAPM_ADC("ADCR", NULL, WM8996_POWER_MANAGEMENT_3, 0, 0),
SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &left_sidetone),
SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &right_sidetone),
SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 11, 0),
SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 10, 0),
SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 9, 0),
SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 8, 0),
SND_SOC_DAPM_MIXER("DSP2TXL", WM8996_POWER_MANAGEMENT_5, 11, 0,
dsp2txl, ARRAY_SIZE(dsp2txl)),
SND_SOC_DAPM_MIXER("DSP2TXR", WM8996_POWER_MANAGEMENT_5, 10, 0,
dsp2txr, ARRAY_SIZE(dsp2txr)),
SND_SOC_DAPM_MIXER("DSP1TXL", WM8996_POWER_MANAGEMENT_5, 9, 0,
dsp1txl, ARRAY_SIZE(dsp1txl)),
SND_SOC_DAPM_MIXER("DSP1TXR", WM8996_POWER_MANAGEMENT_5, 8, 0,
dsp1txr, ARRAY_SIZE(dsp1txr)),
SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM, 0, 0,
dac2l_mix, ARRAY_SIZE(dac2l_mix)),
SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM, 0, 0,
dac2r_mix, ARRAY_SIZE(dac2r_mix)),
SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
dac1l_mix, ARRAY_SIZE(dac1l_mix)),
SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
dac1r_mix, ARRAY_SIZE(dac1r_mix)),
SND_SOC_DAPM_DAC("DAC2L", NULL, WM8996_POWER_MANAGEMENT_5, 3, 0),
SND_SOC_DAPM_DAC("DAC2R", NULL, WM8996_POWER_MANAGEMENT_5, 2, 0),
SND_SOC_DAPM_DAC("DAC1L", NULL, WM8996_POWER_MANAGEMENT_5, 1, 0),
SND_SOC_DAPM_DAC("DAC1R", NULL, WM8996_POWER_MANAGEMENT_5, 0, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0, WM8996_POWER_MANAGEMENT_4, 9, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX0", NULL, 1, WM8996_POWER_MANAGEMENT_4, 8, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0, WM8996_POWER_MANAGEMENT_6, 9, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX0", NULL, 1, WM8996_POWER_MANAGEMENT_6, 8, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 5, WM8996_POWER_MANAGEMENT_4, 5, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 4, WM8996_POWER_MANAGEMENT_4, 4, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 3, WM8996_POWER_MANAGEMENT_4, 3, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 2, WM8996_POWER_MANAGEMENT_4, 2, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 1, WM8996_POWER_MANAGEMENT_4, 1, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX0", NULL, 0, WM8996_POWER_MANAGEMENT_4, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 5, WM8996_POWER_MANAGEMENT_6, 5, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 4, WM8996_POWER_MANAGEMENT_6, 4, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 3, WM8996_POWER_MANAGEMENT_6, 3, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 2, WM8996_POWER_MANAGEMENT_6, 2, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 1, WM8996_POWER_MANAGEMENT_6, 1, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX0", NULL, 0, WM8996_POWER_MANAGEMENT_6, 0, 0),
/* We route as stereo pairs so define some dummy widgets to squash
* things down for now. RXA = 0,1, RXB = 2,3 and so on */
SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM, 0, 0, &dsp1rx),
SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM, 0, 0, &dsp2rx),
SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM, 0, 0, &aif2tx),
SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM, 0, 0, &spkl_mux),
SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM, 0, 0, &spkr_mux),
SND_SOC_DAPM_PGA("SPKL PGA", WM8996_LEFT_PDM_SPEAKER, 4, 0, NULL, 0),
SND_SOC_DAPM_PGA("SPKR PGA", WM8996_RIGHT_PDM_SPEAKER, 4, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8996_POWER_MANAGEMENT_1, 7, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8996_ANALOGUE_HP_2, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8996_DC_SERVO_1, 2, 0, dcs_start,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2L, 0,
rmv_short_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8996_POWER_MANAGEMENT_1, 6, 0,NULL, 0),
SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8996_ANALOGUE_HP_2, 1, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8996_DC_SERVO_1, 3, 0, dcs_start,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2R, 0,
rmv_short_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8996_POWER_MANAGEMENT_1, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8996_ANALOGUE_HP_1, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8996_DC_SERVO_1, 0, 0, dcs_start,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1L, 0,
rmv_short_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8996_POWER_MANAGEMENT_1, 4, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8996_ANALOGUE_HP_1, 1, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8996_DC_SERVO_1, 1, 0, dcs_start,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1R, 0,
rmv_short_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_OUTPUT("HPOUT1L"),
SND_SOC_DAPM_OUTPUT("HPOUT1R"),
SND_SOC_DAPM_OUTPUT("HPOUT2L"),
SND_SOC_DAPM_OUTPUT("HPOUT2R"),
SND_SOC_DAPM_OUTPUT("SPKDAT"),
};
static const struct snd_soc_dapm_route wm8996_dapm_routes[] = {
{ "AIFCLK", NULL, "SYSCLK" },
{ "SYSDSPCLK", NULL, "SYSCLK" },
{ "Charge Pump", NULL, "SYSCLK" },
{ "Charge Pump", NULL, "CPVDD" },
{ "MICB1", NULL, "LDO2" },
{ "MICB1", NULL, "MICB1 Audio" },
{ "MICB1", NULL, "Bandgap" },
{ "MICB2", NULL, "LDO2" },
{ "MICB2", NULL, "MICB2 Audio" },
{ "MICB2", NULL, "Bandgap" },
{ "AIF1RX0", NULL, "AIF1 Playback" },
{ "AIF1RX1", NULL, "AIF1 Playback" },
{ "AIF1RX2", NULL, "AIF1 Playback" },
{ "AIF1RX3", NULL, "AIF1 Playback" },
{ "AIF1RX4", NULL, "AIF1 Playback" },
{ "AIF1RX5", NULL, "AIF1 Playback" },
{ "AIF2RX0", NULL, "AIF2 Playback" },
{ "AIF2RX1", NULL, "AIF2 Playback" },
{ "AIF1 Capture", NULL, "AIF1TX0" },
{ "AIF1 Capture", NULL, "AIF1TX1" },
{ "AIF1 Capture", NULL, "AIF1TX2" },
{ "AIF1 Capture", NULL, "AIF1TX3" },
{ "AIF1 Capture", NULL, "AIF1TX4" },
{ "AIF1 Capture", NULL, "AIF1TX5" },
{ "AIF2 Capture", NULL, "AIF2TX0" },
{ "AIF2 Capture", NULL, "AIF2TX1" },
{ "IN1L PGA", NULL, "IN2LN" },
{ "IN1L PGA", NULL, "IN2LP" },
{ "IN1L PGA", NULL, "IN1LN" },
{ "IN1L PGA", NULL, "IN1LP" },
{ "IN1L PGA", NULL, "Bandgap" },
{ "IN1R PGA", NULL, "IN2RN" },
{ "IN1R PGA", NULL, "IN2RP" },
{ "IN1R PGA", NULL, "IN1RN" },
{ "IN1R PGA", NULL, "IN1RP" },
{ "IN1R PGA", NULL, "Bandgap" },
{ "ADCL", NULL, "IN1L PGA" },
{ "ADCR", NULL, "IN1R PGA" },
{ "DMIC1L", NULL, "DMIC1DAT" },
{ "DMIC1R", NULL, "DMIC1DAT" },
{ "DMIC2L", NULL, "DMIC2DAT" },
{ "DMIC2R", NULL, "DMIC2DAT" },
{ "DMIC2L", NULL, "DMIC2" },
{ "DMIC2R", NULL, "DMIC2" },
{ "DMIC1L", NULL, "DMIC1" },
{ "DMIC1R", NULL, "DMIC1" },
{ "IN1L Mux", "ADC", "ADCL" },
{ "IN1L Mux", "DMIC1", "DMIC1L" },
{ "IN1L Mux", "DMIC2", "DMIC2L" },
{ "IN1R Mux", "ADC", "ADCR" },
{ "IN1R Mux", "DMIC1", "DMIC1R" },
{ "IN1R Mux", "DMIC2", "DMIC2R" },
{ "IN2L Mux", "ADC", "ADCL" },
{ "IN2L Mux", "DMIC1", "DMIC1L" },
{ "IN2L Mux", "DMIC2", "DMIC2L" },
{ "IN2R Mux", "ADC", "ADCR" },
{ "IN2R Mux", "DMIC1", "DMIC1R" },
{ "IN2R Mux", "DMIC2", "DMIC2R" },
{ "Left Sidetone", "IN1", "IN1L Mux" },
{ "Left Sidetone", "IN2", "IN2L Mux" },
{ "Right Sidetone", "IN1", "IN1R Mux" },
{ "Right Sidetone", "IN2", "IN2R Mux" },
{ "DSP1TXL", "IN1 Switch", "IN1L Mux" },
{ "DSP1TXR", "IN1 Switch", "IN1R Mux" },
{ "DSP2TXL", "IN1 Switch", "IN2L Mux" },
{ "DSP2TXR", "IN1 Switch", "IN2R Mux" },
{ "AIF1TX0", NULL, "DSP1TXL" },
{ "AIF1TX1", NULL, "DSP1TXR" },
{ "AIF1TX2", NULL, "DSP2TXL" },
{ "AIF1TX3", NULL, "DSP2TXR" },
{ "AIF1TX4", NULL, "AIF2RX0" },
{ "AIF1TX5", NULL, "AIF2RX1" },
{ "AIF1RX0", NULL, "AIFCLK" },
{ "AIF1RX1", NULL, "AIFCLK" },
{ "AIF1RX2", NULL, "AIFCLK" },
{ "AIF1RX3", NULL, "AIFCLK" },
{ "AIF1RX4", NULL, "AIFCLK" },
{ "AIF1RX5", NULL, "AIFCLK" },
{ "AIF2RX0", NULL, "AIFCLK" },
{ "AIF2RX1", NULL, "AIFCLK" },
{ "AIF1TX0", NULL, "AIFCLK" },
{ "AIF1TX1", NULL, "AIFCLK" },
{ "AIF1TX2", NULL, "AIFCLK" },
{ "AIF1TX3", NULL, "AIFCLK" },
{ "AIF1TX4", NULL, "AIFCLK" },
{ "AIF1TX5", NULL, "AIFCLK" },
{ "AIF2TX0", NULL, "AIFCLK" },
{ "AIF2TX1", NULL, "AIFCLK" },
{ "DSP1RXL", NULL, "SYSDSPCLK" },
{ "DSP1RXR", NULL, "SYSDSPCLK" },
{ "DSP2RXL", NULL, "SYSDSPCLK" },
{ "DSP2RXR", NULL, "SYSDSPCLK" },
{ "DSP1TXL", NULL, "SYSDSPCLK" },
{ "DSP1TXR", NULL, "SYSDSPCLK" },
{ "DSP2TXL", NULL, "SYSDSPCLK" },
{ "DSP2TXR", NULL, "SYSDSPCLK" },
{ "AIF1RXA", NULL, "AIF1RX0" },
{ "AIF1RXA", NULL, "AIF1RX1" },
{ "AIF1RXB", NULL, "AIF1RX2" },
{ "AIF1RXB", NULL, "AIF1RX3" },
{ "AIF1RXC", NULL, "AIF1RX4" },
{ "AIF1RXC", NULL, "AIF1RX5" },
{ "AIF2RX", NULL, "AIF2RX0" },
{ "AIF2RX", NULL, "AIF2RX1" },
{ "AIF2TX", "DSP2", "DSP2TX" },
{ "AIF2TX", "DSP1", "DSP1RX" },
{ "AIF2TX", "AIF1", "AIF1RXC" },
{ "DSP1RXL", NULL, "DSP1RX" },
{ "DSP1RXR", NULL, "DSP1RX" },
{ "DSP2RXL", NULL, "DSP2RX" },
{ "DSP2RXR", NULL, "DSP2RX" },
{ "DSP2TX", NULL, "DSP2TXL" },
{ "DSP2TX", NULL, "DSP2TXR" },
{ "DSP1RX", "AIF1", "AIF1RXA" },
{ "DSP1RX", "AIF2", "AIF2RX" },
{ "DSP2RX", "AIF1", "AIF1RXB" },
{ "DSP2RX", "AIF2", "AIF2RX" },
{ "DAC2L Mixer", "DSP2 Switch", "DSP2RXL" },
{ "DAC2L Mixer", "DSP1 Switch", "DSP1RXL" },
{ "DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
{ "DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
{ "DAC2R Mixer", "DSP2 Switch", "DSP2RXR" },
{ "DAC2R Mixer", "DSP1 Switch", "DSP1RXR" },
{ "DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
{ "DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
{ "DAC1L Mixer", "DSP2 Switch", "DSP2RXL" },
{ "DAC1L Mixer", "DSP1 Switch", "DSP1RXL" },
{ "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
{ "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
{ "DAC1R Mixer", "DSP2 Switch", "DSP2RXR" },
{ "DAC1R Mixer", "DSP1 Switch", "DSP1RXR" },
{ "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
{ "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
{ "DAC1L", NULL, "DAC1L Mixer" },
{ "DAC1R", NULL, "DAC1R Mixer" },
{ "DAC2L", NULL, "DAC2L Mixer" },
{ "DAC2R", NULL, "DAC2R Mixer" },
{ "HPOUT2L PGA", NULL, "Charge Pump" },
{ "HPOUT2L PGA", NULL, "Bandgap" },
{ "HPOUT2L PGA", NULL, "DAC2L" },
{ "HPOUT2L_DLY", NULL, "HPOUT2L PGA" },
{ "HPOUT2L_DCS", NULL, "HPOUT2L_DLY" },
{ "HPOUT2L_RMV_SHORT", NULL, "HPOUT2L_DCS" },
{ "HPOUT2R PGA", NULL, "Charge Pump" },
{ "HPOUT2R PGA", NULL, "Bandgap" },
{ "HPOUT2R PGA", NULL, "DAC2R" },
{ "HPOUT2R_DLY", NULL, "HPOUT2R PGA" },
{ "HPOUT2R_DCS", NULL, "HPOUT2R_DLY" },
{ "HPOUT2R_RMV_SHORT", NULL, "HPOUT2R_DCS" },
{ "HPOUT1L PGA", NULL, "Charge Pump" },
{ "HPOUT1L PGA", NULL, "Bandgap" },
{ "HPOUT1L PGA", NULL, "DAC1L" },
{ "HPOUT1L_DLY", NULL, "HPOUT1L PGA" },
{ "HPOUT1L_DCS", NULL, "HPOUT1L_DLY" },
{ "HPOUT1L_RMV_SHORT", NULL, "HPOUT1L_DCS" },
{ "HPOUT1R PGA", NULL, "Charge Pump" },
{ "HPOUT1R PGA", NULL, "Bandgap" },
{ "HPOUT1R PGA", NULL, "DAC1R" },
{ "HPOUT1R_DLY", NULL, "HPOUT1R PGA" },
{ "HPOUT1R_DCS", NULL, "HPOUT1R_DLY" },
{ "HPOUT1R_RMV_SHORT", NULL, "HPOUT1R_DCS" },
{ "HPOUT2L", NULL, "HPOUT2L_RMV_SHORT" },
{ "HPOUT2R", NULL, "HPOUT2R_RMV_SHORT" },
{ "HPOUT1L", NULL, "HPOUT1L_RMV_SHORT" },
{ "HPOUT1R", NULL, "HPOUT1R_RMV_SHORT" },
{ "SPKL", "DAC1L", "DAC1L" },
{ "SPKL", "DAC1R", "DAC1R" },
{ "SPKL", "DAC2L", "DAC2L" },
{ "SPKL", "DAC2R", "DAC2R" },
{ "SPKR", "DAC1L", "DAC1L" },
{ "SPKR", "DAC1R", "DAC1R" },
{ "SPKR", "DAC2L", "DAC2L" },
{ "SPKR", "DAC2R", "DAC2R" },
{ "SPKL PGA", NULL, "SPKL" },
{ "SPKR PGA", NULL, "SPKR" },
{ "SPKDAT", NULL, "SPKL PGA" },
{ "SPKDAT", NULL, "SPKR PGA" },
};
static bool wm8996_readable_register(struct device *dev, unsigned int reg)
{
/* Due to the sparseness of the register map the compiler
* output from an explicit switch statement ends up being much
* more efficient than a table.
*/
switch (reg) {
case WM8996_SOFTWARE_RESET:
case WM8996_POWER_MANAGEMENT_1:
case WM8996_POWER_MANAGEMENT_2:
case WM8996_POWER_MANAGEMENT_3:
case WM8996_POWER_MANAGEMENT_4:
case WM8996_POWER_MANAGEMENT_5:
case WM8996_POWER_MANAGEMENT_6:
case WM8996_POWER_MANAGEMENT_7:
case WM8996_POWER_MANAGEMENT_8:
case WM8996_LEFT_LINE_INPUT_VOLUME:
case WM8996_RIGHT_LINE_INPUT_VOLUME:
case WM8996_LINE_INPUT_CONTROL:
case WM8996_DAC1_HPOUT1_VOLUME:
case WM8996_DAC2_HPOUT2_VOLUME:
case WM8996_DAC1_LEFT_VOLUME:
case WM8996_DAC1_RIGHT_VOLUME:
case WM8996_DAC2_LEFT_VOLUME:
case WM8996_DAC2_RIGHT_VOLUME:
case WM8996_OUTPUT1_LEFT_VOLUME:
case WM8996_OUTPUT1_RIGHT_VOLUME:
case WM8996_OUTPUT2_LEFT_VOLUME:
case WM8996_OUTPUT2_RIGHT_VOLUME:
case WM8996_MICBIAS_1:
case WM8996_MICBIAS_2:
case WM8996_LDO_1:
case WM8996_LDO_2:
case WM8996_ACCESSORY_DETECT_MODE_1:
case WM8996_ACCESSORY_DETECT_MODE_2:
case WM8996_HEADPHONE_DETECT_1:
case WM8996_HEADPHONE_DETECT_2:
case WM8996_MIC_DETECT_1:
case WM8996_MIC_DETECT_2:
case WM8996_MIC_DETECT_3:
case WM8996_CHARGE_PUMP_1:
case WM8996_CHARGE_PUMP_2:
case WM8996_DC_SERVO_1:
case WM8996_DC_SERVO_2:
case WM8996_DC_SERVO_3:
case WM8996_DC_SERVO_5:
case WM8996_DC_SERVO_6:
case WM8996_DC_SERVO_7:
case WM8996_DC_SERVO_READBACK_0:
case WM8996_ANALOGUE_HP_1:
case WM8996_ANALOGUE_HP_2:
case WM8996_CHIP_REVISION:
case WM8996_CONTROL_INTERFACE_1:
case WM8996_WRITE_SEQUENCER_CTRL_1:
case WM8996_WRITE_SEQUENCER_CTRL_2:
case WM8996_AIF_CLOCKING_1:
case WM8996_AIF_CLOCKING_2:
case WM8996_CLOCKING_1:
case WM8996_CLOCKING_2:
case WM8996_AIF_RATE:
case WM8996_FLL_CONTROL_1:
case WM8996_FLL_CONTROL_2:
case WM8996_FLL_CONTROL_3:
case WM8996_FLL_CONTROL_4:
case WM8996_FLL_CONTROL_5:
case WM8996_FLL_CONTROL_6:
case WM8996_FLL_EFS_1:
case WM8996_FLL_EFS_2:
case WM8996_AIF1_CONTROL:
case WM8996_AIF1_BCLK:
case WM8996_AIF1_TX_LRCLK_1:
case WM8996_AIF1_TX_LRCLK_2:
case WM8996_AIF1_RX_LRCLK_1:
case WM8996_AIF1_RX_LRCLK_2:
case WM8996_AIF1TX_DATA_CONFIGURATION_1:
case WM8996_AIF1TX_DATA_CONFIGURATION_2:
case WM8996_AIF1RX_DATA_CONFIGURATION:
case WM8996_AIF1TX_CHANNEL_0_CONFIGURATION:
case WM8996_AIF1TX_CHANNEL_1_CONFIGURATION:
case WM8996_AIF1TX_CHANNEL_2_CONFIGURATION:
case WM8996_AIF1TX_CHANNEL_3_CONFIGURATION:
case WM8996_AIF1TX_CHANNEL_4_CONFIGURATION:
case WM8996_AIF1TX_CHANNEL_5_CONFIGURATION:
case WM8996_AIF1RX_CHANNEL_0_CONFIGURATION:
case WM8996_AIF1RX_CHANNEL_1_CONFIGURATION:
case WM8996_AIF1RX_CHANNEL_2_CONFIGURATION:
case WM8996_AIF1RX_CHANNEL_3_CONFIGURATION:
case WM8996_AIF1RX_CHANNEL_4_CONFIGURATION:
case WM8996_AIF1RX_CHANNEL_5_CONFIGURATION:
case WM8996_AIF1RX_MONO_CONFIGURATION:
case WM8996_AIF1TX_TEST:
case WM8996_AIF2_CONTROL:
case WM8996_AIF2_BCLK:
case WM8996_AIF2_TX_LRCLK_1:
case WM8996_AIF2_TX_LRCLK_2:
case WM8996_AIF2_RX_LRCLK_1:
case WM8996_AIF2_RX_LRCLK_2:
case WM8996_AIF2TX_DATA_CONFIGURATION_1:
case WM8996_AIF2TX_DATA_CONFIGURATION_2:
case WM8996_AIF2RX_DATA_CONFIGURATION:
case WM8996_AIF2TX_CHANNEL_0_CONFIGURATION:
case WM8996_AIF2TX_CHANNEL_1_CONFIGURATION:
case WM8996_AIF2RX_CHANNEL_0_CONFIGURATION:
case WM8996_AIF2RX_CHANNEL_1_CONFIGURATION:
case WM8996_AIF2RX_MONO_CONFIGURATION:
case WM8996_AIF2TX_TEST:
case WM8996_DSP1_TX_LEFT_VOLUME:
case WM8996_DSP1_TX_RIGHT_VOLUME:
case WM8996_DSP1_RX_LEFT_VOLUME:
case WM8996_DSP1_RX_RIGHT_VOLUME:
case WM8996_DSP1_TX_FILTERS:
case WM8996_DSP1_RX_FILTERS_1:
case WM8996_DSP1_RX_FILTERS_2:
case WM8996_DSP1_DRC_1:
case WM8996_DSP1_DRC_2:
case WM8996_DSP1_DRC_3:
case WM8996_DSP1_DRC_4:
case WM8996_DSP1_DRC_5:
case WM8996_DSP1_RX_EQ_GAINS_1:
case WM8996_DSP1_RX_EQ_GAINS_2:
case WM8996_DSP1_RX_EQ_BAND_1_A:
case WM8996_DSP1_RX_EQ_BAND_1_B:
case WM8996_DSP1_RX_EQ_BAND_1_PG:
case WM8996_DSP1_RX_EQ_BAND_2_A:
case WM8996_DSP1_RX_EQ_BAND_2_B:
case WM8996_DSP1_RX_EQ_BAND_2_C:
case WM8996_DSP1_RX_EQ_BAND_2_PG:
case WM8996_DSP1_RX_EQ_BAND_3_A:
case WM8996_DSP1_RX_EQ_BAND_3_B:
case WM8996_DSP1_RX_EQ_BAND_3_C:
case WM8996_DSP1_RX_EQ_BAND_3_PG:
case WM8996_DSP1_RX_EQ_BAND_4_A:
case WM8996_DSP1_RX_EQ_BAND_4_B:
case WM8996_DSP1_RX_EQ_BAND_4_C:
case WM8996_DSP1_RX_EQ_BAND_4_PG:
case WM8996_DSP1_RX_EQ_BAND_5_A:
case WM8996_DSP1_RX_EQ_BAND_5_B:
case WM8996_DSP1_RX_EQ_BAND_5_PG:
case WM8996_DSP2_TX_LEFT_VOLUME:
case WM8996_DSP2_TX_RIGHT_VOLUME:
case WM8996_DSP2_RX_LEFT_VOLUME:
case WM8996_DSP2_RX_RIGHT_VOLUME:
case WM8996_DSP2_TX_FILTERS:
case WM8996_DSP2_RX_FILTERS_1:
case WM8996_DSP2_RX_FILTERS_2:
case WM8996_DSP2_DRC_1:
case WM8996_DSP2_DRC_2:
case WM8996_DSP2_DRC_3:
case WM8996_DSP2_DRC_4:
case WM8996_DSP2_DRC_5:
case WM8996_DSP2_RX_EQ_GAINS_1:
case WM8996_DSP2_RX_EQ_GAINS_2:
case WM8996_DSP2_RX_EQ_BAND_1_A:
case WM8996_DSP2_RX_EQ_BAND_1_B:
case WM8996_DSP2_RX_EQ_BAND_1_PG:
case WM8996_DSP2_RX_EQ_BAND_2_A:
case WM8996_DSP2_RX_EQ_BAND_2_B:
case WM8996_DSP2_RX_EQ_BAND_2_C:
case WM8996_DSP2_RX_EQ_BAND_2_PG:
case WM8996_DSP2_RX_EQ_BAND_3_A:
case WM8996_DSP2_RX_EQ_BAND_3_B:
case WM8996_DSP2_RX_EQ_BAND_3_C:
case WM8996_DSP2_RX_EQ_BAND_3_PG:
case WM8996_DSP2_RX_EQ_BAND_4_A:
case WM8996_DSP2_RX_EQ_BAND_4_B:
case WM8996_DSP2_RX_EQ_BAND_4_C:
case WM8996_DSP2_RX_EQ_BAND_4_PG:
case WM8996_DSP2_RX_EQ_BAND_5_A:
case WM8996_DSP2_RX_EQ_BAND_5_B:
case WM8996_DSP2_RX_EQ_BAND_5_PG:
case WM8996_DAC1_MIXER_VOLUMES:
case WM8996_DAC1_LEFT_MIXER_ROUTING:
case WM8996_DAC1_RIGHT_MIXER_ROUTING:
case WM8996_DAC2_MIXER_VOLUMES:
case WM8996_DAC2_LEFT_MIXER_ROUTING:
case WM8996_DAC2_RIGHT_MIXER_ROUTING:
case WM8996_DSP1_TX_LEFT_MIXER_ROUTING:
case WM8996_DSP1_TX_RIGHT_MIXER_ROUTING:
case WM8996_DSP2_TX_LEFT_MIXER_ROUTING:
case WM8996_DSP2_TX_RIGHT_MIXER_ROUTING:
case WM8996_DSP_TX_MIXER_SELECT:
case WM8996_DAC_SOFTMUTE:
case WM8996_OVERSAMPLING:
case WM8996_SIDETONE:
case WM8996_GPIO_1:
case WM8996_GPIO_2:
case WM8996_GPIO_3:
case WM8996_GPIO_4:
case WM8996_GPIO_5:
case WM8996_PULL_CONTROL_1:
case WM8996_PULL_CONTROL_2:
case WM8996_INTERRUPT_STATUS_1:
case WM8996_INTERRUPT_STATUS_2:
case WM8996_INTERRUPT_RAW_STATUS_2:
case WM8996_INTERRUPT_STATUS_1_MASK:
case WM8996_INTERRUPT_STATUS_2_MASK:
case WM8996_INTERRUPT_CONTROL:
case WM8996_LEFT_PDM_SPEAKER:
case WM8996_RIGHT_PDM_SPEAKER:
case WM8996_PDM_SPEAKER_MUTE_SEQUENCE:
case WM8996_PDM_SPEAKER_VOLUME:
return true;
default:
return false;
}
}
static bool wm8996_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8996_SOFTWARE_RESET:
case WM8996_CHIP_REVISION:
case WM8996_LDO_1:
case WM8996_LDO_2:
case WM8996_INTERRUPT_STATUS_1:
case WM8996_INTERRUPT_STATUS_2:
case WM8996_INTERRUPT_RAW_STATUS_2:
case WM8996_DC_SERVO_READBACK_0:
case WM8996_DC_SERVO_2:
case WM8996_DC_SERVO_6:
case WM8996_DC_SERVO_7:
case WM8996_FLL_CONTROL_6:
case WM8996_MIC_DETECT_3:
case WM8996_HEADPHONE_DETECT_1:
case WM8996_HEADPHONE_DETECT_2:
return true;
default:
return false;
}
}
static const int bclk_divs[] = {
1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96
};
static void wm8996_update_bclk(struct snd_soc_component *component)
{
struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
int aif, best, cur_val, bclk_rate, bclk_reg, i;
/* Don't bother if we're in a low frequency idle mode that
* can't support audio.
*/
if (wm8996->sysclk < 64000)
return;
for (aif = 0; aif < WM8996_AIFS; aif++) {
switch (aif) {
case 0:
bclk_reg = WM8996_AIF1_BCLK;
break;
case 1:
bclk_reg = WM8996_AIF2_BCLK;
break;
}
bclk_rate = wm8996->bclk_rate[aif];
/* Pick a divisor for BCLK as close as we can get to ideal */
best = 0;
for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
cur_val = (wm8996->sysclk / bclk_divs[i]) - bclk_rate;
if (cur_val < 0) /* BCLK table is sorted */
break;
best = i;
}
bclk_rate = wm8996->sysclk / bclk_divs[best];
dev_dbg(component->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
bclk_divs[best], bclk_rate);
snd_soc_component_update_bits(component, bclk_reg,
WM8996_AIF1_BCLK_DIV_MASK, best);
}
}
static int wm8996_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
int ret;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
/* Put the MICBIASes into regulating mode */
snd_soc_component_update_bits(component, WM8996_MICBIAS_1,
WM8996_MICB1_MODE, 0);
snd_soc_component_update_bits(component, WM8996_MICBIAS_2,
WM8996_MICB2_MODE, 0);
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies),
wm8996->supplies);
if (ret != 0) {
dev_err(component->dev,
"Failed to enable supplies: %d\n",
ret);
return ret;
}
if (wm8996->pdata.ldo_ena >= 0) {
gpio_set_value_cansleep(wm8996->pdata.ldo_ena,
1);
msleep(5);
}
regcache_cache_only(wm8996->regmap, false);
regcache_sync(wm8996->regmap);
}
/* Bypass the MICBIASes for lowest power */
snd_soc_component_update_bits(component, WM8996_MICBIAS_1,
WM8996_MICB1_MODE, WM8996_MICB1_MODE);
snd_soc_component_update_bits(component, WM8996_MICBIAS_2,
WM8996_MICB2_MODE, WM8996_MICB2_MODE);
break;
case SND_SOC_BIAS_OFF:
regcache_cache_only(wm8996->regmap, true);
if (wm8996->pdata.ldo_ena >= 0) {
gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
regcache_cache_only(wm8996->regmap, true);
}
regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies),
wm8996->supplies);
break;
}
return 0;
}
static int wm8996_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
int aifctrl = 0;
int bclk = 0;
int lrclk_tx = 0;
int lrclk_rx = 0;
int aifctrl_reg, bclk_reg, lrclk_tx_reg, lrclk_rx_reg;
switch (dai->id) {
case 0:
aifctrl_reg = WM8996_AIF1_CONTROL;
bclk_reg = WM8996_AIF1_BCLK;
lrclk_tx_reg = WM8996_AIF1_TX_LRCLK_2;
lrclk_rx_reg = WM8996_AIF1_RX_LRCLK_2;
break;
case 1:
aifctrl_reg = WM8996_AIF2_CONTROL;
bclk_reg = WM8996_AIF2_BCLK;
lrclk_tx_reg = WM8996_AIF2_TX_LRCLK_2;
lrclk_rx_reg = WM8996_AIF2_RX_LRCLK_2;
break;
default:
WARN(1, "Invalid dai id %d\n", dai->id);
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
bclk |= WM8996_AIF1_BCLK_INV;
break;
case SND_SOC_DAIFMT_NB_IF:
lrclk_tx |= WM8996_AIF1TX_LRCLK_INV;
lrclk_rx |= WM8996_AIF1RX_LRCLK_INV;
break;
case SND_SOC_DAIFMT_IB_IF:
bclk |= WM8996_AIF1_BCLK_INV;
lrclk_tx |= WM8996_AIF1TX_LRCLK_INV;
lrclk_rx |= WM8996_AIF1RX_LRCLK_INV;
break;
}
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
break;
case SND_SOC_DAIFMT_CBS_CFM:
lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR;
lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR;
break;
case SND_SOC_DAIFMT_CBM_CFS:
bclk |= WM8996_AIF1_BCLK_MSTR;
break;
case SND_SOC_DAIFMT_CBM_CFM:
bclk |= WM8996_AIF1_BCLK_MSTR;
lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR;
lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
break;
case SND_SOC_DAIFMT_DSP_B:
aifctrl |= 1;
break;
case SND_SOC_DAIFMT_I2S:
aifctrl |= 2;
break;
case SND_SOC_DAIFMT_LEFT_J:
aifctrl |= 3;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, aifctrl_reg, WM8996_AIF1_FMT_MASK, aifctrl);
snd_soc_component_update_bits(component, bclk_reg,
WM8996_AIF1_BCLK_INV | WM8996_AIF1_BCLK_MSTR,
bclk);
snd_soc_component_update_bits(component, lrclk_tx_reg,
WM8996_AIF1TX_LRCLK_INV |
WM8996_AIF1TX_LRCLK_MSTR,
lrclk_tx);
snd_soc_component_update_bits(component, lrclk_rx_reg,
WM8996_AIF1RX_LRCLK_INV |
WM8996_AIF1RX_LRCLK_MSTR,
lrclk_rx);
return 0;
}
static const int dsp_divs[] = {
48000, 32000, 16000, 8000
};
static int wm8996_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
int bits, i, bclk_rate, best;
int aifdata = 0;
int lrclk = 0;
int dsp = 0;
int aifdata_reg, lrclk_reg, dsp_shift;
switch (dai->id) {
case 0:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
(snd_soc_component_read(component, WM8996_GPIO_1)) & WM8996_GP1_FN_MASK) {
aifdata_reg = WM8996_AIF1RX_DATA_CONFIGURATION;
lrclk_reg = WM8996_AIF1_RX_LRCLK_1;
} else {
aifdata_reg = WM8996_AIF1TX_DATA_CONFIGURATION_1;
lrclk_reg = WM8996_AIF1_TX_LRCLK_1;
}
dsp_shift = 0;
break;
case 1:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
(snd_soc_component_read(component, WM8996_GPIO_2)) & WM8996_GP2_FN_MASK) {
aifdata_reg = WM8996_AIF2RX_DATA_CONFIGURATION;
lrclk_reg = WM8996_AIF2_RX_LRCLK_1;
} else {
aifdata_reg = WM8996_AIF2TX_DATA_CONFIGURATION_1;
lrclk_reg = WM8996_AIF2_TX_LRCLK_1;
}
dsp_shift = WM8996_DSP2_DIV_SHIFT;
break;
default:
WARN(1, "Invalid dai id %d\n", dai->id);
return -EINVAL;
}
bclk_rate = snd_soc_params_to_bclk(params);
if (bclk_rate < 0) {
dev_err(component->dev, "Unsupported BCLK rate: %d\n", bclk_rate);
return bclk_rate;
}
wm8996->bclk_rate[dai->id] = bclk_rate;
wm8996->rx_rate[dai->id] = params_rate(params);
/* Needs looking at for TDM */
bits = params_width(params);
if (bits < 0)
return bits;
aifdata |= (bits << WM8996_AIF1TX_WL_SHIFT) | bits;
best = 0;
for (i = 0; i < ARRAY_SIZE(dsp_divs); i++) {
if (abs(dsp_divs[i] - params_rate(params)) <
abs(dsp_divs[best] - params_rate(params)))
best = i;
}
dsp |= i << dsp_shift;
wm8996_update_bclk(component);
lrclk = bclk_rate / params_rate(params);
dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
lrclk, bclk_rate / lrclk);
snd_soc_component_update_bits(component, aifdata_reg,
WM8996_AIF1TX_WL_MASK |
WM8996_AIF1TX_SLOT_LEN_MASK,
aifdata);
snd_soc_component_update_bits(component, lrclk_reg, WM8996_AIF1RX_RATE_MASK,
lrclk);
snd_soc_component_update_bits(component, WM8996_AIF_CLOCKING_2,
WM8996_DSP1_DIV_MASK << dsp_shift, dsp);
return 0;
}
static int wm8996_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
int lfclk = 0;
int ratediv = 0;
int sync = WM8996_REG_SYNC;
int src;
int old;
if (freq == wm8996->sysclk && clk_id == wm8996->sysclk_src)
return 0;
/* Disable SYSCLK while we reconfigure */
old = snd_soc_component_read(component, WM8996_AIF_CLOCKING_1) & WM8996_SYSCLK_ENA;
snd_soc_component_update_bits(component, WM8996_AIF_CLOCKING_1,
WM8996_SYSCLK_ENA, 0);
switch (clk_id) {
case WM8996_SYSCLK_MCLK1:
wm8996->sysclk = freq;
src = 0;
break;
case WM8996_SYSCLK_MCLK2:
wm8996->sysclk = freq;
src = 1;
break;
case WM8996_SYSCLK_FLL:
wm8996->sysclk = freq;
src = 2;
break;
default:
dev_err(component->dev, "Unsupported clock source %d\n", clk_id);
return -EINVAL;
}
switch (wm8996->sysclk) {
case 5644800:
case 6144000:
snd_soc_component_update_bits(component, WM8996_AIF_RATE,
WM8996_SYSCLK_RATE, 0);
break;
case 22579200:
case 24576000:
ratediv = WM8996_SYSCLK_DIV;
wm8996->sysclk /= 2;
fallthrough;
case 11289600:
case 12288000:
snd_soc_component_update_bits(component, WM8996_AIF_RATE,
WM8996_SYSCLK_RATE, WM8996_SYSCLK_RATE);
break;
case 32000:
case 32768:
lfclk = WM8996_LFCLK_ENA;
sync = 0;
break;
default:
dev_warn(component->dev, "Unsupported clock rate %dHz\n",
wm8996->sysclk);
return -EINVAL;
}
wm8996_update_bclk(component);
snd_soc_component_update_bits(component, WM8996_AIF_CLOCKING_1,
WM8996_SYSCLK_SRC_MASK | WM8996_SYSCLK_DIV_MASK,
src << WM8996_SYSCLK_SRC_SHIFT | ratediv);
snd_soc_component_update_bits(component, WM8996_CLOCKING_1, WM8996_LFCLK_ENA, lfclk);
snd_soc_component_update_bits(component, WM8996_CONTROL_INTERFACE_1,
WM8996_REG_SYNC, sync);
snd_soc_component_update_bits(component, WM8996_AIF_CLOCKING_1,
WM8996_SYSCLK_ENA, old);
wm8996->sysclk_src = clk_id;
return 0;
}
struct _fll_div {
u16 fll_fratio;
u16 fll_outdiv;
u16 fll_refclk_div;
u16 fll_loop_gain;
u16 fll_ref_freq;
u16 n;
u16 theta;
u16 lambda;
};
static struct {
unsigned int min;
unsigned int max;
u16 fll_fratio;
int ratio;
} fll_fratios[] = {
{ 0, 64000, 4, 16 },
{ 64000, 128000, 3, 8 },
{ 128000, 256000, 2, 4 },
{ 256000, 1000000, 1, 2 },
{ 1000000, 13500000, 0, 1 },
};
static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
unsigned int Fout)
{
unsigned int target;
unsigned int div;
unsigned int fratio, gcd_fll;
int i;
/* Fref must be <=13.5MHz */
div = 1;
fll_div->fll_refclk_div = 0;
while ((Fref / div) > 13500000) {
div *= 2;
fll_div->fll_refclk_div++;
if (div > 8) {
pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
Fref);
return -EINVAL;
}
}
pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
/* Apply the division for our remaining calculations */
Fref /= div;
if (Fref >= 3000000)
fll_div->fll_loop_gain = 5;
else
fll_div->fll_loop_gain = 0;
if (Fref >= 48000)
fll_div->fll_ref_freq = 0;
else
fll_div->fll_ref_freq = 1;
/* Fvco should be 90-100MHz; don't check the upper bound */
div = 2;
while (Fout * div < 90000000) {
div++;
if (div > 64) {
pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
Fout);
return -EINVAL;
}
}
target = Fout * div;
fll_div->fll_outdiv = div - 1;
pr_debug("FLL Fvco=%dHz\n", target);
/* Find an appropraite FLL_FRATIO and factor it out of the target */
for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
fll_div->fll_fratio = fll_fratios[i].fll_fratio;
fratio = fll_fratios[i].ratio;
break;
}
}
if (i == ARRAY_SIZE(fll_fratios)) {
pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
return -EINVAL;
}
fll_div->n = target / (fratio * Fref);
if (target % Fref == 0) {
fll_div->theta = 0;
fll_div->lambda = 0;
} else {
gcd_fll = gcd(target, fratio * Fref);
fll_div->theta = (target - (fll_div->n * fratio * Fref))
/ gcd_fll;
fll_div->lambda = (fratio * Fref) / gcd_fll;
}
pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
fll_div->n, fll_div->theta, fll_div->lambda);
pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
fll_div->fll_fratio, fll_div->fll_outdiv,
fll_div->fll_refclk_div);
return 0;
}
static int wm8996_set_fll(struct snd_soc_component *component, int fll_id, int source,
unsigned int Fref, unsigned int Fout)
{
struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
struct i2c_client *i2c = to_i2c_client(component->dev);
struct _fll_div fll_div;
unsigned long timeout, time_left;
int ret, reg, retry;
/* Any change? */
if (source == wm8996->fll_src && Fref == wm8996->fll_fref &&
Fout == wm8996->fll_fout)
return 0;
if (Fout == 0) {
dev_dbg(component->dev, "FLL disabled\n");
wm8996->fll_fref = 0;
wm8996->fll_fout = 0;
snd_soc_component_update_bits(component, WM8996_FLL_CONTROL_1,
WM8996_FLL_ENA, 0);
wm8996_bg_disable(component);
return 0;
}
ret = fll_factors(&fll_div, Fref, Fout);
if (ret != 0)
return ret;
switch (source) {
case WM8996_FLL_MCLK1:
reg = 0;
break;
case WM8996_FLL_MCLK2:
reg = 1;
break;
case WM8996_FLL_DACLRCLK1:
reg = 2;
break;
case WM8996_FLL_BCLK1:
reg = 3;
break;
default:
dev_err(component->dev, "Unknown FLL source %d\n", ret);
return -EINVAL;
}
reg |= fll_div.fll_refclk_div << WM8996_FLL_REFCLK_DIV_SHIFT;
reg |= fll_div.fll_ref_freq << WM8996_FLL_REF_FREQ_SHIFT;
snd_soc_component_update_bits(component, WM8996_FLL_CONTROL_5,
WM8996_FLL_REFCLK_DIV_MASK | WM8996_FLL_REF_FREQ |
WM8996_FLL_REFCLK_SRC_MASK, reg);
reg = 0;
if (fll_div.theta || fll_div.lambda)
reg |= WM8996_FLL_EFS_ENA | (3 << WM8996_FLL_LFSR_SEL_SHIFT);
else
reg |= 1 << WM8996_FLL_LFSR_SEL_SHIFT;
snd_soc_component_write(component, WM8996_FLL_EFS_2, reg);
snd_soc_component_update_bits(component, WM8996_FLL_CONTROL_2,
WM8996_FLL_OUTDIV_MASK |
WM8996_FLL_FRATIO_MASK,
(fll_div.fll_outdiv << WM8996_FLL_OUTDIV_SHIFT) |
(fll_div.fll_fratio));
snd_soc_component_write(component, WM8996_FLL_CONTROL_3, fll_div.theta);
snd_soc_component_update_bits(component, WM8996_FLL_CONTROL_4,
WM8996_FLL_N_MASK | WM8996_FLL_LOOP_GAIN_MASK,
(fll_div.n << WM8996_FLL_N_SHIFT) |
fll_div.fll_loop_gain);
snd_soc_component_write(component, WM8996_FLL_EFS_1, fll_div.lambda);
/* Enable the bandgap if it's not already enabled */
ret = snd_soc_component_read(component, WM8996_FLL_CONTROL_1);
if (!(ret & WM8996_FLL_ENA))
wm8996_bg_enable(component);
/* Clear any pending completions (eg, from failed startups) */
try_wait_for_completion(&wm8996->fll_lock);
snd_soc_component_update_bits(component, WM8996_FLL_CONTROL_1,
WM8996_FLL_ENA, WM8996_FLL_ENA);
/* The FLL supports live reconfiguration - kick that in case we were
* already enabled.
*/
snd_soc_component_write(component, WM8996_FLL_CONTROL_6, WM8996_FLL_SWITCH_CLK);
/* Wait for the FLL to lock, using the interrupt if possible */
if (Fref > 1000000)
timeout = usecs_to_jiffies(300);
else
timeout = msecs_to_jiffies(2);
/* Allow substantially longer if we've actually got the IRQ, poll
* at a slightly higher rate if we don't.
*/
if (i2c->irq)
timeout *= 10;
else
/* ensure timeout of atleast 1 jiffies */
timeout = (timeout/2) ? : 1;
for (retry = 0; retry < 10; retry++) {
time_left = wait_for_completion_timeout(&wm8996->fll_lock,
timeout);
if (time_left != 0) {
WARN_ON(!i2c->irq);
ret = 1;
break;
}
ret = snd_soc_component_read(component, WM8996_INTERRUPT_RAW_STATUS_2);
if (ret & WM8996_FLL_LOCK_STS)
break;
}
if (retry == 10) {
dev_err(component->dev, "Timed out waiting for FLL\n");
ret = -ETIMEDOUT;
}
dev_dbg(component->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
wm8996->fll_fref = Fref;
wm8996->fll_fout = Fout;
wm8996->fll_src = source;
return ret;
}
#ifdef CONFIG_GPIOLIB
static void wm8996_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct wm8996_priv *wm8996 = gpiochip_get_data(chip);
regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
WM8996_GP1_LVL, !!value << WM8996_GP1_LVL_SHIFT);
}
static int wm8996_gpio_direction_out(struct gpio_chip *chip,
unsigned offset, int value)
{
struct wm8996_priv *wm8996 = gpiochip_get_data(chip);
int val;
val = (1 << WM8996_GP1_FN_SHIFT) | (!!value << WM8996_GP1_LVL_SHIFT);
return regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
WM8996_GP1_FN_MASK | WM8996_GP1_DIR |
WM8996_GP1_LVL, val);
}
static int wm8996_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct wm8996_priv *wm8996 = gpiochip_get_data(chip);
unsigned int reg;
int ret;
ret = regmap_read(wm8996->regmap, WM8996_GPIO_1 + offset, ®);
if (ret < 0)
return ret;
return (reg & WM8996_GP1_LVL) != 0;
}
static int wm8996_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
{
struct wm8996_priv *wm8996 = gpiochip_get_data(chip);
return regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
WM8996_GP1_FN_MASK | WM8996_GP1_DIR,
(1 << WM8996_GP1_FN_SHIFT) |
(1 << WM8996_GP1_DIR_SHIFT));
}
static const struct gpio_chip wm8996_template_chip = {
.label = "wm8996",
.owner = THIS_MODULE,
.direction_output = wm8996_gpio_direction_out,
.set = wm8996_gpio_set,
.direction_input = wm8996_gpio_direction_in,
.get = wm8996_gpio_get,
.can_sleep = 1,
};
static void wm8996_init_gpio(struct wm8996_priv *wm8996)
{
int ret;
wm8996->gpio_chip = wm8996_template_chip;
wm8996->gpio_chip.ngpio = 5;
wm8996->gpio_chip.parent = wm8996->dev;
if (wm8996->pdata.gpio_base)
wm8996->gpio_chip.base = wm8996->pdata.gpio_base;
else
wm8996->gpio_chip.base = -1;
ret = gpiochip_add_data(&wm8996->gpio_chip, wm8996);
if (ret != 0)
dev_err(wm8996->dev, "Failed to add GPIOs: %d\n", ret);
}
static void wm8996_free_gpio(struct wm8996_priv *wm8996)
{
gpiochip_remove(&wm8996->gpio_chip);
}
#else
static void wm8996_init_gpio(struct wm8996_priv *wm8996)
{
}
static void wm8996_free_gpio(struct wm8996_priv *wm8996)
{
}
#endif
/**
* wm8996_detect - Enable default WM8996 jack detection
* @component: ASoC component
* @jack: jack pointer
* @polarity_cb: polarity callback
*
* The WM8996 has advanced accessory detection support for headsets.
* This function provides a default implementation which integrates
* the majority of this functionality with minimal user configuration.
*
* This will detect headset, headphone and short circuit button and
* will also detect inverted microphone ground connections and update
* the polarity of the connections.
*/
int wm8996_detect(struct snd_soc_component *component, struct snd_soc_jack *jack,
wm8996_polarity_fn polarity_cb)
{
struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
wm8996->jack = jack;
wm8996->detecting = true;
wm8996->polarity_cb = polarity_cb;
wm8996->jack_flips = 0;
if (wm8996->polarity_cb)
wm8996->polarity_cb(component, 0);
/* Clear discarge to avoid noise during detection */
snd_soc_component_update_bits(component, WM8996_MICBIAS_1,
WM8996_MICB1_DISCH, 0);
snd_soc_component_update_bits(component, WM8996_MICBIAS_2,
WM8996_MICB2_DISCH, 0);
/* LDO2 powers the microphones, SYSCLK clocks detection */
snd_soc_dapm_mutex_lock(dapm);
snd_soc_dapm_force_enable_pin_unlocked(dapm, "LDO2");
snd_soc_dapm_force_enable_pin_unlocked(dapm, "SYSCLK");
snd_soc_dapm_mutex_unlock(dapm);
/* We start off just enabling microphone detection - even a
* plain headphone will trigger detection.
*/
snd_soc_component_update_bits(component, WM8996_MIC_DETECT_1,
WM8996_MICD_ENA, WM8996_MICD_ENA);
/* Slowest detection rate, gives debounce for initial detection */
snd_soc_component_update_bits(component, WM8996_MIC_DETECT_1,
WM8996_MICD_RATE_MASK,
WM8996_MICD_RATE_MASK);
/* Enable interrupts and we're off */
snd_soc_component_update_bits(component, WM8996_INTERRUPT_STATUS_2_MASK,
WM8996_IM_MICD_EINT | WM8996_HP_DONE_EINT, 0);
return 0;
}
EXPORT_SYMBOL_GPL(wm8996_detect);
static void wm8996_hpdet_irq(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
int val, reg, report;
/* Assume headphone in error conditions; we need to report
* something or we stall our state machine.
*/
report = SND_JACK_HEADPHONE;
reg = snd_soc_component_read(component, WM8996_HEADPHONE_DETECT_2);
if (reg < 0) {
dev_err(component->dev, "Failed to read HPDET status\n");
goto out;
}
if (!(reg & WM8996_HP_DONE)) {
dev_err(component->dev, "Got HPDET IRQ but HPDET is busy\n");
goto out;
}
val = reg & WM8996_HP_LVL_MASK;
dev_dbg(component->dev, "HPDET measured %d ohms\n", val);
/* If we've got high enough impedence then report as line,
* otherwise assume headphone.
*/
if (val >= 126)
report = SND_JACK_LINEOUT;
else
report = SND_JACK_HEADPHONE;
out:
if (wm8996->jack_mic)
report |= SND_JACK_MICROPHONE;
snd_soc_jack_report(wm8996->jack, report,
SND_JACK_LINEOUT | SND_JACK_HEADSET);
wm8996->detecting = false;
/* If the output isn't running re-clamp it */
if (!(snd_soc_component_read(component, WM8996_POWER_MANAGEMENT_1) &
(WM8996_HPOUT1L_ENA | WM8996_HPOUT1R_RMV_SHORT)))
snd_soc_component_update_bits(component, WM8996_ANALOGUE_HP_1,
WM8996_HPOUT1L_RMV_SHORT |
WM8996_HPOUT1R_RMV_SHORT, 0);
/* Go back to looking at the microphone */
snd_soc_component_update_bits(component, WM8996_ACCESSORY_DETECT_MODE_1,
WM8996_JD_MODE_MASK, 0);
snd_soc_component_update_bits(component, WM8996_MIC_DETECT_1, WM8996_MICD_ENA,
WM8996_MICD_ENA);
snd_soc_dapm_disable_pin(dapm, "Bandgap");
snd_soc_dapm_sync(dapm);
}
static void wm8996_hpdet_start(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
/* Unclamp the output, we can't measure while we're shorting it */
snd_soc_component_update_bits(component, WM8996_ANALOGUE_HP_1,
WM8996_HPOUT1L_RMV_SHORT |
WM8996_HPOUT1R_RMV_SHORT,
WM8996_HPOUT1L_RMV_SHORT |
WM8996_HPOUT1R_RMV_SHORT);
/* We need bandgap for HPDET */
snd_soc_dapm_force_enable_pin(dapm, "Bandgap");
snd_soc_dapm_sync(dapm);
/* Go into headphone detect left mode */
snd_soc_component_update_bits(component, WM8996_MIC_DETECT_1, WM8996_MICD_ENA, 0);
snd_soc_component_update_bits(component, WM8996_ACCESSORY_DETECT_MODE_1,
WM8996_JD_MODE_MASK, 1);
/* Trigger a measurement */
snd_soc_component_update_bits(component, WM8996_HEADPHONE_DETECT_1,
WM8996_HP_POLL, WM8996_HP_POLL);
}
static void wm8996_report_headphone(struct snd_soc_component *component)
{
dev_dbg(component->dev, "Headphone detected\n");
wm8996_hpdet_start(component);
/* Increase the detection rate a bit for responsiveness. */
snd_soc_component_update_bits(component, WM8996_MIC_DETECT_1,
WM8996_MICD_RATE_MASK |
WM8996_MICD_BIAS_STARTTIME_MASK,
7 << WM8996_MICD_RATE_SHIFT |
7 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
}
static void wm8996_micd(struct snd_soc_component *component)
{
struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
int val, reg;
val = snd_soc_component_read(component, WM8996_MIC_DETECT_3);
dev_dbg(component->dev, "Microphone event: %x\n", val);
if (!(val & WM8996_MICD_VALID)) {
dev_warn(component->dev, "Microphone detection state invalid\n");
return;
}
/* No accessory, reset everything and report removal */
if (!(val & WM8996_MICD_STS)) {
dev_dbg(component->dev, "Jack removal detected\n");
wm8996->jack_mic = false;
wm8996->detecting = true;
wm8996->jack_flips = 0;
snd_soc_jack_report(wm8996->jack, 0,
SND_JACK_LINEOUT | SND_JACK_HEADSET |
SND_JACK_BTN_0);
snd_soc_component_update_bits(component, WM8996_MIC_DETECT_1,
WM8996_MICD_RATE_MASK |
WM8996_MICD_BIAS_STARTTIME_MASK,
WM8996_MICD_RATE_MASK |
9 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
return;
}
/* If the measurement is very high we've got a microphone,
* either we just detected one or if we already reported then
* we've got a button release event.
*/
if (val & 0x400) {
if (wm8996->detecting) {
dev_dbg(component->dev, "Microphone detected\n");
wm8996->jack_mic = true;
wm8996_hpdet_start(component);
/* Increase poll rate to give better responsiveness
* for buttons */
snd_soc_component_update_bits(component, WM8996_MIC_DETECT_1,
WM8996_MICD_RATE_MASK |
WM8996_MICD_BIAS_STARTTIME_MASK,
5 << WM8996_MICD_RATE_SHIFT |
7 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
} else {
dev_dbg(component->dev, "Mic button up\n");
snd_soc_jack_report(wm8996->jack, 0, SND_JACK_BTN_0);
}
return;
}
/* If we detected a lower impedence during initial startup
* then we probably have the wrong polarity, flip it. Don't
* do this for the lowest impedences to speed up detection of
* plain headphones. If both polarities report a low
* impedence then give up and report headphones.
*/
if (wm8996->detecting && (val & 0x3f0)) {
wm8996->jack_flips++;
if (wm8996->jack_flips > 1) {
wm8996_report_headphone(component);
return;
}
reg = snd_soc_component_read(component, WM8996_ACCESSORY_DETECT_MODE_2);
reg ^= WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC |
WM8996_MICD_BIAS_SRC;
snd_soc_component_update_bits(component, WM8996_ACCESSORY_DETECT_MODE_2,
WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC |
WM8996_MICD_BIAS_SRC, reg);
if (wm8996->polarity_cb)
wm8996->polarity_cb(component,
(reg & WM8996_MICD_SRC) != 0);
dev_dbg(component->dev, "Set microphone polarity to %d\n",
(reg & WM8996_MICD_SRC) != 0);
return;
}
/* Don't distinguish between buttons, just report any low
* impedence as BTN_0.
*/
if (val & 0x3fc) {
if (wm8996->jack_mic) {
dev_dbg(component->dev, "Mic button detected\n");
snd_soc_jack_report(wm8996->jack, SND_JACK_BTN_0,
SND_JACK_BTN_0);
} else if (wm8996->detecting) {
wm8996_report_headphone(component);
}
}
}
static irqreturn_t wm8996_irq(int irq, void *data)
{
struct snd_soc_component *component = data;
struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
int irq_val;
irq_val = snd_soc_component_read(component, WM8996_INTERRUPT_STATUS_2);
if (irq_val < 0) {
dev_err(component->dev, "Failed to read IRQ status: %d\n",
irq_val);
return IRQ_NONE;
}
irq_val &= ~snd_soc_component_read(component, WM8996_INTERRUPT_STATUS_2_MASK);
if (!irq_val)
return IRQ_NONE;
snd_soc_component_write(component, WM8996_INTERRUPT_STATUS_2, irq_val);
if (irq_val & (WM8996_DCS_DONE_01_EINT | WM8996_DCS_DONE_23_EINT)) {
dev_dbg(component->dev, "DC servo IRQ\n");
complete(&wm8996->dcs_done);
}
if (irq_val & WM8996_FIFOS_ERR_EINT)
dev_err(component->dev, "Digital core FIFO error\n");
if (irq_val & WM8996_FLL_LOCK_EINT) {
dev_dbg(component->dev, "FLL locked\n");
complete(&wm8996->fll_lock);
}
if (irq_val & WM8996_MICD_EINT)
wm8996_micd(component);
if (irq_val & WM8996_HP_DONE_EINT)
wm8996_hpdet_irq(component);
return IRQ_HANDLED;
}
static irqreturn_t wm8996_edge_irq(int irq, void *data)
{
irqreturn_t ret = IRQ_NONE;
irqreturn_t val;
do {
val = wm8996_irq(irq, data);
if (val != IRQ_NONE)
ret = val;
} while (val != IRQ_NONE);
return ret;
}
static void wm8996_retune_mobile_pdata(struct snd_soc_component *component)
{
struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
struct wm8996_pdata *pdata = &wm8996->pdata;
struct snd_kcontrol_new controls[] = {
SOC_ENUM_EXT("DSP1 EQ Mode",
wm8996->retune_mobile_enum,
wm8996_get_retune_mobile_enum,
wm8996_put_retune_mobile_enum),
SOC_ENUM_EXT("DSP2 EQ Mode",
wm8996->retune_mobile_enum,
wm8996_get_retune_mobile_enum,
wm8996_put_retune_mobile_enum),
};
int ret, i, j;
const char **t;
/* We need an array of texts for the enum API but the number
* of texts is likely to be less than the number of
* configurations due to the sample rate dependency of the
* configurations. */
wm8996->num_retune_mobile_texts = 0;
wm8996->retune_mobile_texts = NULL;
for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
for (j = 0; j < wm8996->num_retune_mobile_texts; j++) {
if (strcmp(pdata->retune_mobile_cfgs[i].name,
wm8996->retune_mobile_texts[j]) == 0)
break;
}
if (j != wm8996->num_retune_mobile_texts)
continue;
/* Expand the array... */
t = krealloc(wm8996->retune_mobile_texts,
sizeof(char *) *
(wm8996->num_retune_mobile_texts + 1),
GFP_KERNEL);
if (t == NULL)
continue;
/* ...store the new entry... */
t[wm8996->num_retune_mobile_texts] =
pdata->retune_mobile_cfgs[i].name;
/* ...and remember the new version. */
wm8996->num_retune_mobile_texts++;
wm8996->retune_mobile_texts = t;
}
dev_dbg(component->dev, "Allocated %d unique ReTune Mobile names\n",
wm8996->num_retune_mobile_texts);
wm8996->retune_mobile_enum.items = wm8996->num_retune_mobile_texts;
wm8996->retune_mobile_enum.texts = wm8996->retune_mobile_texts;
ret = snd_soc_add_component_controls(component, controls, ARRAY_SIZE(controls));
if (ret != 0)
dev_err(component->dev,
"Failed to add ReTune Mobile controls: %d\n", ret);
}
static const struct regmap_config wm8996_regmap = {
.reg_bits = 16,
.val_bits = 16,
.max_register = WM8996_MAX_REGISTER,
.reg_defaults = wm8996_reg,
.num_reg_defaults = ARRAY_SIZE(wm8996_reg),
.volatile_reg = wm8996_volatile_register,
.readable_reg = wm8996_readable_register,
.cache_type = REGCACHE_MAPLE,
};
static int wm8996_probe(struct snd_soc_component *component)
{
int ret;
struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
struct i2c_client *i2c = to_i2c_client(component->dev);
int irq_flags;
wm8996->component = component;
init_completion(&wm8996->dcs_done);
init_completion(&wm8996->fll_lock);
if (wm8996->pdata.num_retune_mobile_cfgs)
wm8996_retune_mobile_pdata(component);
else
snd_soc_add_component_controls(component, wm8996_eq_controls,
ARRAY_SIZE(wm8996_eq_controls));
if (i2c->irq) {
if (wm8996->pdata.irq_flags)
irq_flags = wm8996->pdata.irq_flags;
else
irq_flags = IRQF_TRIGGER_LOW;
irq_flags |= IRQF_ONESHOT;
if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
ret = request_threaded_irq(i2c->irq, NULL,
wm8996_edge_irq,
irq_flags, "wm8996", component);
else
ret = request_threaded_irq(i2c->irq, NULL, wm8996_irq,
irq_flags, "wm8996", component);
if (ret == 0) {
/* Unmask the interrupt */
snd_soc_component_update_bits(component, WM8996_INTERRUPT_CONTROL,
WM8996_IM_IRQ, 0);
/* Enable error reporting and DC servo status */
snd_soc_component_update_bits(component,
WM8996_INTERRUPT_STATUS_2_MASK,
WM8996_IM_DCS_DONE_23_EINT |
WM8996_IM_DCS_DONE_01_EINT |
WM8996_IM_FLL_LOCK_EINT |
WM8996_IM_FIFOS_ERR_EINT,
0);
} else {
dev_err(component->dev, "Failed to request IRQ: %d\n",
ret);
return ret;
}
}
return 0;
}
static void wm8996_remove(struct snd_soc_component *component)
{
struct i2c_client *i2c = to_i2c_client(component->dev);
snd_soc_component_update_bits(component, WM8996_INTERRUPT_CONTROL,
WM8996_IM_IRQ, WM8996_IM_IRQ);
if (i2c->irq)
free_irq(i2c->irq, component);
}
static const struct snd_soc_component_driver soc_component_dev_wm8996 = {
.probe = wm8996_probe,
.remove = wm8996_remove,
.set_bias_level = wm8996_set_bias_level,
.seq_notifier = wm8996_seq_notifier,
.controls = wm8996_snd_controls,
.num_controls = ARRAY_SIZE(wm8996_snd_controls),
.dapm_widgets = wm8996_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8996_dapm_widgets),
.dapm_routes = wm8996_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(wm8996_dapm_routes),
.set_pll = wm8996_set_fll,
.use_pmdown_time = 1,
.endianness = 1,
};
#define WM8996_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\
SNDRV_PCM_RATE_48000)
#define WM8996_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops wm8996_dai_ops = {
.set_fmt = wm8996_set_fmt,
.hw_params = wm8996_hw_params,
.set_sysclk = wm8996_set_sysclk,
};
static struct snd_soc_dai_driver wm8996_dai[] = {
{
.name = "wm8996-aif1",
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 6,
.rates = WM8996_RATES,
.formats = WM8996_FORMATS,
.sig_bits = 24,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 1,
.channels_max = 6,
.rates = WM8996_RATES,
.formats = WM8996_FORMATS,
.sig_bits = 24,
},
.ops = &wm8996_dai_ops,
},
{
.name = "wm8996-aif2",
.playback = {
.stream_name = "AIF2 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM8996_RATES,
.formats = WM8996_FORMATS,
.sig_bits = 24,
},
.capture = {
.stream_name = "AIF2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM8996_RATES,
.formats = WM8996_FORMATS,
.sig_bits = 24,
},
.ops = &wm8996_dai_ops,
},
};
static int wm8996_i2c_probe(struct i2c_client *i2c)
{
struct wm8996_priv *wm8996;
int ret, i;
unsigned int reg;
wm8996 = devm_kzalloc(&i2c->dev, sizeof(struct wm8996_priv),
GFP_KERNEL);
if (wm8996 == NULL)
return -ENOMEM;
i2c_set_clientdata(i2c, wm8996);
wm8996->dev = &i2c->dev;
if (dev_get_platdata(&i2c->dev))
memcpy(&wm8996->pdata, dev_get_platdata(&i2c->dev),
sizeof(wm8996->pdata));
if (wm8996->pdata.ldo_ena > 0) {
ret = gpio_request_one(wm8996->pdata.ldo_ena,
GPIOF_OUT_INIT_LOW, "WM8996 ENA");
if (ret < 0) {
dev_err(&i2c->dev, "Failed to request GPIO %d: %d\n",
wm8996->pdata.ldo_ena, ret);
goto err;
}
}
for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++)
wm8996->supplies[i].supply = wm8996_supply_names[i];
ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8996->supplies),
wm8996->supplies);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
goto err_gpio;
}
wm8996->disable_nb[0].notifier_call = wm8996_regulator_event_0;
wm8996->disable_nb[1].notifier_call = wm8996_regulator_event_1;
wm8996->disable_nb[2].notifier_call = wm8996_regulator_event_2;
/* This should really be moved into the regulator core */
for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) {
ret = devm_regulator_register_notifier(
wm8996->supplies[i].consumer,
&wm8996->disable_nb[i]);
if (ret != 0) {
dev_err(&i2c->dev,
"Failed to register regulator notifier: %d\n",
ret);
}
}
ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies),
wm8996->supplies);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
goto err_gpio;
}
if (wm8996->pdata.ldo_ena > 0) {
gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 1);
msleep(5);
}
wm8996->regmap = devm_regmap_init_i2c(i2c, &wm8996_regmap);
if (IS_ERR(wm8996->regmap)) {
ret = PTR_ERR(wm8996->regmap);
dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);
goto err_enable;
}
ret = regmap_read(wm8996->regmap, WM8996_SOFTWARE_RESET, ®);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
goto err_regmap;
}
if (reg != 0x8915) {
dev_err(&i2c->dev, "Device is not a WM8996, ID %x\n", reg);
ret = -EINVAL;
goto err_regmap;
}
ret = regmap_read(wm8996->regmap, WM8996_CHIP_REVISION, ®);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to read device revision: %d\n",
ret);
goto err_regmap;
}
dev_info(&i2c->dev, "revision %c\n",
(reg & WM8996_CHIP_REV_MASK) + 'A');
if (wm8996->pdata.ldo_ena > 0) {
gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
regcache_cache_only(wm8996->regmap, true);
} else {
ret = regmap_write(wm8996->regmap, WM8996_SOFTWARE_RESET,
0x8915);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
goto err_regmap;
}
}
regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
/* Apply platform data settings */
regmap_update_bits(wm8996->regmap, WM8996_LINE_INPUT_CONTROL,
WM8996_INL_MODE_MASK | WM8996_INR_MODE_MASK,
wm8996->pdata.inl_mode << WM8996_INL_MODE_SHIFT |
wm8996->pdata.inr_mode);
for (i = 0; i < ARRAY_SIZE(wm8996->pdata.gpio_default); i++) {
if (!wm8996->pdata.gpio_default[i])
continue;
regmap_write(wm8996->regmap, WM8996_GPIO_1 + i,
wm8996->pdata.gpio_default[i] & 0xffff);
}
if (wm8996->pdata.spkmute_seq)
regmap_update_bits(wm8996->regmap,
WM8996_PDM_SPEAKER_MUTE_SEQUENCE,
WM8996_SPK_MUTE_ENDIAN |
WM8996_SPK_MUTE_SEQ1_MASK,
wm8996->pdata.spkmute_seq);
regmap_update_bits(wm8996->regmap, WM8996_ACCESSORY_DETECT_MODE_2,
WM8996_MICD_BIAS_SRC | WM8996_HPOUT1FB_SRC |
WM8996_MICD_SRC, wm8996->pdata.micdet_def);
/* Latch volume update bits */
regmap_update_bits(wm8996->regmap, WM8996_LEFT_LINE_INPUT_VOLUME,
WM8996_IN1_VU, WM8996_IN1_VU);
regmap_update_bits(wm8996->regmap, WM8996_RIGHT_LINE_INPUT_VOLUME,
WM8996_IN1_VU, WM8996_IN1_VU);
regmap_update_bits(wm8996->regmap, WM8996_DAC1_LEFT_VOLUME,
WM8996_DAC1_VU, WM8996_DAC1_VU);
regmap_update_bits(wm8996->regmap, WM8996_DAC1_RIGHT_VOLUME,
WM8996_DAC1_VU, WM8996_DAC1_VU);
regmap_update_bits(wm8996->regmap, WM8996_DAC2_LEFT_VOLUME,
WM8996_DAC2_VU, WM8996_DAC2_VU);
regmap_update_bits(wm8996->regmap, WM8996_DAC2_RIGHT_VOLUME,
WM8996_DAC2_VU, WM8996_DAC2_VU);
regmap_update_bits(wm8996->regmap, WM8996_OUTPUT1_LEFT_VOLUME,
WM8996_DAC1_VU, WM8996_DAC1_VU);
regmap_update_bits(wm8996->regmap, WM8996_OUTPUT1_RIGHT_VOLUME,
WM8996_DAC1_VU, WM8996_DAC1_VU);
regmap_update_bits(wm8996->regmap, WM8996_OUTPUT2_LEFT_VOLUME,
WM8996_DAC2_VU, WM8996_DAC2_VU);
regmap_update_bits(wm8996->regmap, WM8996_OUTPUT2_RIGHT_VOLUME,
WM8996_DAC2_VU, WM8996_DAC2_VU);
regmap_update_bits(wm8996->regmap, WM8996_DSP1_TX_LEFT_VOLUME,
WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
regmap_update_bits(wm8996->regmap, WM8996_DSP1_TX_RIGHT_VOLUME,
WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
regmap_update_bits(wm8996->regmap, WM8996_DSP2_TX_LEFT_VOLUME,
WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
regmap_update_bits(wm8996->regmap, WM8996_DSP2_TX_RIGHT_VOLUME,
WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
regmap_update_bits(wm8996->regmap, WM8996_DSP1_RX_LEFT_VOLUME,
WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
regmap_update_bits(wm8996->regmap, WM8996_DSP1_RX_RIGHT_VOLUME,
WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
regmap_update_bits(wm8996->regmap, WM8996_DSP2_RX_LEFT_VOLUME,
WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
regmap_update_bits(wm8996->regmap, WM8996_DSP2_RX_RIGHT_VOLUME,
WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
/* No support currently for the underclocked TDM modes and
* pick a default TDM layout with each channel pair working with
* slots 0 and 1. */
regmap_update_bits(wm8996->regmap,
WM8996_AIF1RX_CHANNEL_0_CONFIGURATION,
WM8996_AIF1RX_CHAN0_SLOTS_MASK |
WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
1 << WM8996_AIF1RX_CHAN0_SLOTS_SHIFT | 0);
regmap_update_bits(wm8996->regmap,
WM8996_AIF1RX_CHANNEL_1_CONFIGURATION,
WM8996_AIF1RX_CHAN1_SLOTS_MASK |
WM8996_AIF1RX_CHAN1_START_SLOT_MASK,
1 << WM8996_AIF1RX_CHAN1_SLOTS_SHIFT | 1);
regmap_update_bits(wm8996->regmap,
WM8996_AIF1RX_CHANNEL_2_CONFIGURATION,
WM8996_AIF1RX_CHAN2_SLOTS_MASK |
WM8996_AIF1RX_CHAN2_START_SLOT_MASK,
1 << WM8996_AIF1RX_CHAN2_SLOTS_SHIFT | 0);
regmap_update_bits(wm8996->regmap,
WM8996_AIF1RX_CHANNEL_3_CONFIGURATION,
WM8996_AIF1RX_CHAN3_SLOTS_MASK |
WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
1 << WM8996_AIF1RX_CHAN3_SLOTS_SHIFT | 1);
regmap_update_bits(wm8996->regmap,
WM8996_AIF1RX_CHANNEL_4_CONFIGURATION,
WM8996_AIF1RX_CHAN4_SLOTS_MASK |
WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
1 << WM8996_AIF1RX_CHAN4_SLOTS_SHIFT | 0);
regmap_update_bits(wm8996->regmap,
WM8996_AIF1RX_CHANNEL_5_CONFIGURATION,
WM8996_AIF1RX_CHAN5_SLOTS_MASK |
WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
1 << WM8996_AIF1RX_CHAN5_SLOTS_SHIFT | 1);
regmap_update_bits(wm8996->regmap,
WM8996_AIF2RX_CHANNEL_0_CONFIGURATION,
WM8996_AIF2RX_CHAN0_SLOTS_MASK |
WM8996_AIF2RX_CHAN0_START_SLOT_MASK,
1 << WM8996_AIF2RX_CHAN0_SLOTS_SHIFT | 0);
regmap_update_bits(wm8996->regmap,
WM8996_AIF2RX_CHANNEL_1_CONFIGURATION,
WM8996_AIF2RX_CHAN1_SLOTS_MASK |
WM8996_AIF2RX_CHAN1_START_SLOT_MASK,
1 << WM8996_AIF2RX_CHAN1_SLOTS_SHIFT | 1);
regmap_update_bits(wm8996->regmap,
WM8996_AIF1TX_CHANNEL_0_CONFIGURATION,
WM8996_AIF1TX_CHAN0_SLOTS_MASK |
WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
1 << WM8996_AIF1TX_CHAN0_SLOTS_SHIFT | 0);
regmap_update_bits(wm8996->regmap,
WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
WM8996_AIF1TX_CHAN1_SLOTS_MASK |
WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
regmap_update_bits(wm8996->regmap,
WM8996_AIF1TX_CHANNEL_2_CONFIGURATION,
WM8996_AIF1TX_CHAN2_SLOTS_MASK |
WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
1 << WM8996_AIF1TX_CHAN2_SLOTS_SHIFT | 0);
regmap_update_bits(wm8996->regmap,
WM8996_AIF1TX_CHANNEL_3_CONFIGURATION,
WM8996_AIF1TX_CHAN3_SLOTS_MASK |
WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
1 << WM8996_AIF1TX_CHAN3_SLOTS_SHIFT | 1);
regmap_update_bits(wm8996->regmap,
WM8996_AIF1TX_CHANNEL_4_CONFIGURATION,
WM8996_AIF1TX_CHAN4_SLOTS_MASK |
WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
1 << WM8996_AIF1TX_CHAN4_SLOTS_SHIFT | 0);
regmap_update_bits(wm8996->regmap,
WM8996_AIF1TX_CHANNEL_5_CONFIGURATION,
WM8996_AIF1TX_CHAN5_SLOTS_MASK |
WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
1 << WM8996_AIF1TX_CHAN5_SLOTS_SHIFT | 1);
regmap_update_bits(wm8996->regmap,
WM8996_AIF2TX_CHANNEL_0_CONFIGURATION,
WM8996_AIF2TX_CHAN0_SLOTS_MASK |
WM8996_AIF2TX_CHAN0_START_SLOT_MASK,
1 << WM8996_AIF2TX_CHAN0_SLOTS_SHIFT | 0);
regmap_update_bits(wm8996->regmap,
WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
WM8996_AIF2TX_CHAN1_SLOTS_MASK |
WM8996_AIF2TX_CHAN1_START_SLOT_MASK,
1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
/* If the TX LRCLK pins are not in LRCLK mode configure the
* AIFs to source their clocks from the RX LRCLKs.
*/
ret = regmap_read(wm8996->regmap, WM8996_GPIO_1, ®);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to read GPIO1: %d\n", ret);
goto err_regmap;
}
if (reg & WM8996_GP1_FN_MASK)
regmap_update_bits(wm8996->regmap, WM8996_AIF1_TX_LRCLK_2,
WM8996_AIF1TX_LRCLK_MODE,
WM8996_AIF1TX_LRCLK_MODE);
ret = regmap_read(wm8996->regmap, WM8996_GPIO_2, ®);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to read GPIO2: %d\n", ret);
goto err_regmap;
}
if (reg & WM8996_GP2_FN_MASK)
regmap_update_bits(wm8996->regmap, WM8996_AIF2_TX_LRCLK_2,
WM8996_AIF2TX_LRCLK_MODE,
WM8996_AIF2TX_LRCLK_MODE);
wm8996_init_gpio(wm8996);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_wm8996, wm8996_dai,
ARRAY_SIZE(wm8996_dai));
if (ret < 0)
goto err_gpiolib;
return ret;
err_gpiolib:
wm8996_free_gpio(wm8996);
err_regmap:
err_enable:
if (wm8996->pdata.ldo_ena > 0)
gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
err_gpio:
if (wm8996->pdata.ldo_ena > 0)
gpio_free(wm8996->pdata.ldo_ena);
err:
return ret;
}
static void wm8996_i2c_remove(struct i2c_client *client)
{
struct wm8996_priv *wm8996 = i2c_get_clientdata(client);
wm8996_free_gpio(wm8996);
if (wm8996->pdata.ldo_ena > 0) {
gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
gpio_free(wm8996->pdata.ldo_ena);
}
}
static const struct i2c_device_id wm8996_i2c_id[] = {
{ "wm8996", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8996_i2c_id);
static struct i2c_driver wm8996_i2c_driver = {
.driver = {
.name = "wm8996",
},
.probe = wm8996_i2c_probe,
.remove = wm8996_i2c_remove,
.id_table = wm8996_i2c_id,
};
module_i2c_driver(wm8996_i2c_driver);
MODULE_DESCRIPTION("ASoC WM8996 driver");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8996.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* DA9055 ALSA Soc codec driver
*
* Copyright (c) 2012 Dialog Semiconductor
*
* Tested on (Samsung SMDK6410 board + DA9055 EVB) using I2S and I2C
* Written by David Chen <[email protected]> and
* Ashish Chavan <[email protected]>
*/
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/da9055.h>
/* DA9055 register space */
/* Status Registers */
#define DA9055_STATUS1 0x02
#define DA9055_PLL_STATUS 0x03
#define DA9055_AUX_L_GAIN_STATUS 0x04
#define DA9055_AUX_R_GAIN_STATUS 0x05
#define DA9055_MIC_L_GAIN_STATUS 0x06
#define DA9055_MIC_R_GAIN_STATUS 0x07
#define DA9055_MIXIN_L_GAIN_STATUS 0x08
#define DA9055_MIXIN_R_GAIN_STATUS 0x09
#define DA9055_ADC_L_GAIN_STATUS 0x0A
#define DA9055_ADC_R_GAIN_STATUS 0x0B
#define DA9055_DAC_L_GAIN_STATUS 0x0C
#define DA9055_DAC_R_GAIN_STATUS 0x0D
#define DA9055_HP_L_GAIN_STATUS 0x0E
#define DA9055_HP_R_GAIN_STATUS 0x0F
#define DA9055_LINE_GAIN_STATUS 0x10
/* System Initialisation Registers */
#define DA9055_CIF_CTRL 0x20
#define DA9055_DIG_ROUTING_AIF 0X21
#define DA9055_SR 0x22
#define DA9055_REFERENCES 0x23
#define DA9055_PLL_FRAC_TOP 0x24
#define DA9055_PLL_FRAC_BOT 0x25
#define DA9055_PLL_INTEGER 0x26
#define DA9055_PLL_CTRL 0x27
#define DA9055_AIF_CLK_MODE 0x28
#define DA9055_AIF_CTRL 0x29
#define DA9055_DIG_ROUTING_DAC 0x2A
#define DA9055_ALC_CTRL1 0x2B
/* Input - Gain, Select and Filter Registers */
#define DA9055_AUX_L_GAIN 0x30
#define DA9055_AUX_R_GAIN 0x31
#define DA9055_MIXIN_L_SELECT 0x32
#define DA9055_MIXIN_R_SELECT 0x33
#define DA9055_MIXIN_L_GAIN 0x34
#define DA9055_MIXIN_R_GAIN 0x35
#define DA9055_ADC_L_GAIN 0x36
#define DA9055_ADC_R_GAIN 0x37
#define DA9055_ADC_FILTERS1 0x38
#define DA9055_MIC_L_GAIN 0x39
#define DA9055_MIC_R_GAIN 0x3A
/* Output - Gain, Select and Filter Registers */
#define DA9055_DAC_FILTERS5 0x40
#define DA9055_DAC_FILTERS2 0x41
#define DA9055_DAC_FILTERS3 0x42
#define DA9055_DAC_FILTERS4 0x43
#define DA9055_DAC_FILTERS1 0x44
#define DA9055_DAC_L_GAIN 0x45
#define DA9055_DAC_R_GAIN 0x46
#define DA9055_CP_CTRL 0x47
#define DA9055_HP_L_GAIN 0x48
#define DA9055_HP_R_GAIN 0x49
#define DA9055_LINE_GAIN 0x4A
#define DA9055_MIXOUT_L_SELECT 0x4B
#define DA9055_MIXOUT_R_SELECT 0x4C
/* System Controller Registers */
#define DA9055_SYSTEM_MODES_INPUT 0x50
#define DA9055_SYSTEM_MODES_OUTPUT 0x51
/* Control Registers */
#define DA9055_AUX_L_CTRL 0x60
#define DA9055_AUX_R_CTRL 0x61
#define DA9055_MIC_BIAS_CTRL 0x62
#define DA9055_MIC_L_CTRL 0x63
#define DA9055_MIC_R_CTRL 0x64
#define DA9055_MIXIN_L_CTRL 0x65
#define DA9055_MIXIN_R_CTRL 0x66
#define DA9055_ADC_L_CTRL 0x67
#define DA9055_ADC_R_CTRL 0x68
#define DA9055_DAC_L_CTRL 0x69
#define DA9055_DAC_R_CTRL 0x6A
#define DA9055_HP_L_CTRL 0x6B
#define DA9055_HP_R_CTRL 0x6C
#define DA9055_LINE_CTRL 0x6D
#define DA9055_MIXOUT_L_CTRL 0x6E
#define DA9055_MIXOUT_R_CTRL 0x6F
/* Configuration Registers */
#define DA9055_LDO_CTRL 0x90
#define DA9055_IO_CTRL 0x91
#define DA9055_GAIN_RAMP_CTRL 0x92
#define DA9055_MIC_CONFIG 0x93
#define DA9055_PC_COUNT 0x94
#define DA9055_CP_VOL_THRESHOLD1 0x95
#define DA9055_CP_DELAY 0x96
#define DA9055_CP_DETECTOR 0x97
#define DA9055_AIF_OFFSET 0x98
#define DA9055_DIG_CTRL 0x99
#define DA9055_ALC_CTRL2 0x9A
#define DA9055_ALC_CTRL3 0x9B
#define DA9055_ALC_NOISE 0x9C
#define DA9055_ALC_TARGET_MIN 0x9D
#define DA9055_ALC_TARGET_MAX 0x9E
#define DA9055_ALC_GAIN_LIMITS 0x9F
#define DA9055_ALC_ANA_GAIN_LIMITS 0xA0
#define DA9055_ALC_ANTICLIP_CTRL 0xA1
#define DA9055_ALC_ANTICLIP_LEVEL 0xA2
#define DA9055_ALC_OFFSET_OP2M_L 0xA6
#define DA9055_ALC_OFFSET_OP2U_L 0xA7
#define DA9055_ALC_OFFSET_OP2M_R 0xAB
#define DA9055_ALC_OFFSET_OP2U_R 0xAC
#define DA9055_ALC_CIC_OP_LVL_CTRL 0xAD
#define DA9055_ALC_CIC_OP_LVL_DATA 0xAE
#define DA9055_DAC_NG_SETUP_TIME 0xAF
#define DA9055_DAC_NG_OFF_THRESHOLD 0xB0
#define DA9055_DAC_NG_ON_THRESHOLD 0xB1
#define DA9055_DAC_NG_CTRL 0xB2
/* SR bit fields */
#define DA9055_SR_8000 (0x1 << 0)
#define DA9055_SR_11025 (0x2 << 0)
#define DA9055_SR_12000 (0x3 << 0)
#define DA9055_SR_16000 (0x5 << 0)
#define DA9055_SR_22050 (0x6 << 0)
#define DA9055_SR_24000 (0x7 << 0)
#define DA9055_SR_32000 (0x9 << 0)
#define DA9055_SR_44100 (0xA << 0)
#define DA9055_SR_48000 (0xB << 0)
#define DA9055_SR_88200 (0xE << 0)
#define DA9055_SR_96000 (0xF << 0)
/* REFERENCES bit fields */
#define DA9055_BIAS_EN (1 << 3)
#define DA9055_VMID_EN (1 << 7)
/* PLL_CTRL bit fields */
#define DA9055_PLL_INDIV_10_20_MHZ (1 << 2)
#define DA9055_PLL_SRM_EN (1 << 6)
#define DA9055_PLL_EN (1 << 7)
/* AIF_CLK_MODE bit fields */
#define DA9055_AIF_BCLKS_PER_WCLK_32 (0 << 0)
#define DA9055_AIF_BCLKS_PER_WCLK_64 (1 << 0)
#define DA9055_AIF_BCLKS_PER_WCLK_128 (2 << 0)
#define DA9055_AIF_BCLKS_PER_WCLK_256 (3 << 0)
#define DA9055_AIF_CLK_EN_SLAVE_MODE (0 << 7)
#define DA9055_AIF_CLK_EN_MASTER_MODE (1 << 7)
/* AIF_CTRL bit fields */
#define DA9055_AIF_FORMAT_I2S_MODE (0 << 0)
#define DA9055_AIF_FORMAT_LEFT_J (1 << 0)
#define DA9055_AIF_FORMAT_RIGHT_J (2 << 0)
#define DA9055_AIF_FORMAT_DSP (3 << 0)
#define DA9055_AIF_WORD_S16_LE (0 << 2)
#define DA9055_AIF_WORD_S20_3LE (1 << 2)
#define DA9055_AIF_WORD_S24_LE (2 << 2)
#define DA9055_AIF_WORD_S32_LE (3 << 2)
/* MIC_L_CTRL bit fields */
#define DA9055_MIC_L_MUTE_EN (1 << 6)
/* MIC_R_CTRL bit fields */
#define DA9055_MIC_R_MUTE_EN (1 << 6)
/* MIXIN_L_CTRL bit fields */
#define DA9055_MIXIN_L_MIX_EN (1 << 3)
/* MIXIN_R_CTRL bit fields */
#define DA9055_MIXIN_R_MIX_EN (1 << 3)
/* ADC_L_CTRL bit fields */
#define DA9055_ADC_L_EN (1 << 7)
/* ADC_R_CTRL bit fields */
#define DA9055_ADC_R_EN (1 << 7)
/* DAC_L_CTRL bit fields */
#define DA9055_DAC_L_MUTE_EN (1 << 6)
/* DAC_R_CTRL bit fields */
#define DA9055_DAC_R_MUTE_EN (1 << 6)
/* HP_L_CTRL bit fields */
#define DA9055_HP_L_AMP_OE (1 << 3)
/* HP_R_CTRL bit fields */
#define DA9055_HP_R_AMP_OE (1 << 3)
/* LINE_CTRL bit fields */
#define DA9055_LINE_AMP_OE (1 << 3)
/* MIXOUT_L_CTRL bit fields */
#define DA9055_MIXOUT_L_MIX_EN (1 << 3)
/* MIXOUT_R_CTRL bit fields */
#define DA9055_MIXOUT_R_MIX_EN (1 << 3)
/* MIC bias select bit fields */
#define DA9055_MICBIAS2_EN (1 << 6)
/* ALC_CIC_OP_LEVEL_CTRL bit fields */
#define DA9055_ALC_DATA_MIDDLE (2 << 0)
#define DA9055_ALC_DATA_TOP (3 << 0)
#define DA9055_ALC_CIC_OP_CHANNEL_LEFT (0 << 7)
#define DA9055_ALC_CIC_OP_CHANNEL_RIGHT (1 << 7)
#define DA9055_AIF_BCLK_MASK (3 << 0)
#define DA9055_AIF_CLK_MODE_MASK (1 << 7)
#define DA9055_AIF_FORMAT_MASK (3 << 0)
#define DA9055_AIF_WORD_LENGTH_MASK (3 << 2)
#define DA9055_GAIN_RAMPING_EN (1 << 5)
#define DA9055_MICBIAS_LEVEL_MASK (3 << 4)
#define DA9055_ALC_OFFSET_15_8 0x00FF00
#define DA9055_ALC_OFFSET_17_16 0x030000
#define DA9055_ALC_AVG_ITERATIONS 5
struct pll_div {
int fref;
int fout;
u8 frac_top;
u8 frac_bot;
u8 integer;
u8 mode; /* 0 = slave, 1 = master */
};
/* PLL divisor table */
static const struct pll_div da9055_pll_div[] = {
/* for MASTER mode, fs = 44.1Khz and its harmonics */
{11289600, 2822400, 0x00, 0x00, 0x20, 1}, /* MCLK=11.2896Mhz */
{12000000, 2822400, 0x03, 0x61, 0x1E, 1}, /* MCLK=12Mhz */
{12288000, 2822400, 0x0C, 0xCC, 0x1D, 1}, /* MCLK=12.288Mhz */
{13000000, 2822400, 0x19, 0x45, 0x1B, 1}, /* MCLK=13Mhz */
{13500000, 2822400, 0x18, 0x56, 0x1A, 1}, /* MCLK=13.5Mhz */
{14400000, 2822400, 0x02, 0xD0, 0x19, 1}, /* MCLK=14.4Mhz */
{19200000, 2822400, 0x1A, 0x1C, 0x12, 1}, /* MCLK=19.2Mhz */
{19680000, 2822400, 0x0B, 0x6D, 0x12, 1}, /* MCLK=19.68Mhz */
{19800000, 2822400, 0x07, 0xDD, 0x12, 1}, /* MCLK=19.8Mhz */
/* for MASTER mode, fs = 48Khz and its harmonics */
{11289600, 3072000, 0x1A, 0x8E, 0x22, 1}, /* MCLK=11.2896Mhz */
{12000000, 3072000, 0x18, 0x93, 0x20, 1}, /* MCLK=12Mhz */
{12288000, 3072000, 0x00, 0x00, 0x20, 1}, /* MCLK=12.288Mhz */
{13000000, 3072000, 0x07, 0xEA, 0x1E, 1}, /* MCLK=13Mhz */
{13500000, 3072000, 0x04, 0x11, 0x1D, 1}, /* MCLK=13.5Mhz */
{14400000, 3072000, 0x09, 0xD0, 0x1B, 1}, /* MCLK=14.4Mhz */
{19200000, 3072000, 0x0F, 0x5C, 0x14, 1}, /* MCLK=19.2Mhz */
{19680000, 3072000, 0x1F, 0x60, 0x13, 1}, /* MCLK=19.68Mhz */
{19800000, 3072000, 0x1B, 0x80, 0x13, 1}, /* MCLK=19.8Mhz */
/* for SLAVE mode with SRM */
{11289600, 2822400, 0x0D, 0x47, 0x21, 0}, /* MCLK=11.2896Mhz */
{12000000, 2822400, 0x0D, 0xFA, 0x1F, 0}, /* MCLK=12Mhz */
{12288000, 2822400, 0x16, 0x66, 0x1E, 0}, /* MCLK=12.288Mhz */
{13000000, 2822400, 0x00, 0x98, 0x1D, 0}, /* MCLK=13Mhz */
{13500000, 2822400, 0x1E, 0x33, 0x1B, 0}, /* MCLK=13.5Mhz */
{14400000, 2822400, 0x06, 0x50, 0x1A, 0}, /* MCLK=14.4Mhz */
{19200000, 2822400, 0x14, 0xBC, 0x13, 0}, /* MCLK=19.2Mhz */
{19680000, 2822400, 0x05, 0x66, 0x13, 0}, /* MCLK=19.68Mhz */
{19800000, 2822400, 0x01, 0xAE, 0x13, 0}, /* MCLK=19.8Mhz */
};
enum clk_src {
DA9055_CLKSRC_MCLK
};
/* Gain and Volume */
static const DECLARE_TLV_DB_RANGE(aux_vol_tlv,
0x0, 0x10, TLV_DB_SCALE_ITEM(-5400, 0, 0),
/* -54dB to 15dB */
0x11, 0x3f, TLV_DB_SCALE_ITEM(-5400, 150, 0)
);
static const DECLARE_TLV_DB_RANGE(digital_gain_tlv,
0x0, 0x07, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
/* -78dB to 12dB */
0x08, 0x7f, TLV_DB_SCALE_ITEM(-7800, 75, 0)
);
static const DECLARE_TLV_DB_RANGE(alc_analog_gain_tlv,
0x0, 0x0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
/* 0dB to 36dB */
0x01, 0x07, TLV_DB_SCALE_ITEM(0, 600, 0)
);
static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -600, 600, 0);
static const DECLARE_TLV_DB_SCALE(mixin_gain_tlv, -450, 150, 0);
static const DECLARE_TLV_DB_SCALE(eq_gain_tlv, -1050, 150, 0);
static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -5700, 100, 0);
static const DECLARE_TLV_DB_SCALE(lineout_vol_tlv, -4800, 100, 0);
static const DECLARE_TLV_DB_SCALE(alc_threshold_tlv, -9450, 150, 0);
static const DECLARE_TLV_DB_SCALE(alc_gain_tlv, 0, 600, 0);
/* ADC and DAC high pass filter cutoff value */
static const char * const da9055_hpf_cutoff_txt[] = {
"Fs/24000", "Fs/12000", "Fs/6000", "Fs/3000"
};
static SOC_ENUM_SINGLE_DECL(da9055_dac_hpf_cutoff,
DA9055_DAC_FILTERS1, 4, da9055_hpf_cutoff_txt);
static SOC_ENUM_SINGLE_DECL(da9055_adc_hpf_cutoff,
DA9055_ADC_FILTERS1, 4, da9055_hpf_cutoff_txt);
/* ADC and DAC voice mode (8kHz) high pass cutoff value */
static const char * const da9055_vf_cutoff_txt[] = {
"2.5Hz", "25Hz", "50Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
};
static SOC_ENUM_SINGLE_DECL(da9055_dac_vf_cutoff,
DA9055_DAC_FILTERS1, 0, da9055_vf_cutoff_txt);
static SOC_ENUM_SINGLE_DECL(da9055_adc_vf_cutoff,
DA9055_ADC_FILTERS1, 0, da9055_vf_cutoff_txt);
/* Gain ramping rate value */
static const char * const da9055_gain_ramping_txt[] = {
"nominal rate", "nominal rate * 4", "nominal rate * 8",
"nominal rate / 8"
};
static SOC_ENUM_SINGLE_DECL(da9055_gain_ramping_rate,
DA9055_GAIN_RAMP_CTRL, 0, da9055_gain_ramping_txt);
/* DAC noise gate setup time value */
static const char * const da9055_dac_ng_setup_time_txt[] = {
"256 samples", "512 samples", "1024 samples", "2048 samples"
};
static SOC_ENUM_SINGLE_DECL(da9055_dac_ng_setup_time,
DA9055_DAC_NG_SETUP_TIME, 0,
da9055_dac_ng_setup_time_txt);
/* DAC noise gate rampup rate value */
static const char * const da9055_dac_ng_rampup_txt[] = {
"0.02 ms/dB", "0.16 ms/dB"
};
static SOC_ENUM_SINGLE_DECL(da9055_dac_ng_rampup_rate,
DA9055_DAC_NG_SETUP_TIME, 2,
da9055_dac_ng_rampup_txt);
/* DAC noise gate rampdown rate value */
static const char * const da9055_dac_ng_rampdown_txt[] = {
"0.64 ms/dB", "20.48 ms/dB"
};
static SOC_ENUM_SINGLE_DECL(da9055_dac_ng_rampdown_rate,
DA9055_DAC_NG_SETUP_TIME, 3,
da9055_dac_ng_rampdown_txt);
/* DAC soft mute rate value */
static const char * const da9055_dac_soft_mute_rate_txt[] = {
"1", "2", "4", "8", "16", "32", "64"
};
static SOC_ENUM_SINGLE_DECL(da9055_dac_soft_mute_rate,
DA9055_DAC_FILTERS5, 4,
da9055_dac_soft_mute_rate_txt);
/* DAC routing select */
static const char * const da9055_dac_src_txt[] = {
"ADC output left", "ADC output right", "AIF input left",
"AIF input right"
};
static SOC_ENUM_SINGLE_DECL(da9055_dac_l_src,
DA9055_DIG_ROUTING_DAC, 0, da9055_dac_src_txt);
static SOC_ENUM_SINGLE_DECL(da9055_dac_r_src,
DA9055_DIG_ROUTING_DAC, 4, da9055_dac_src_txt);
/* MIC PGA Left source select */
static const char * const da9055_mic_l_src_txt[] = {
"MIC1_P_N", "MIC1_P", "MIC1_N", "MIC2_L"
};
static SOC_ENUM_SINGLE_DECL(da9055_mic_l_src,
DA9055_MIXIN_L_SELECT, 4, da9055_mic_l_src_txt);
/* MIC PGA Right source select */
static const char * const da9055_mic_r_src_txt[] = {
"MIC2_R_L", "MIC2_R", "MIC2_L"
};
static SOC_ENUM_SINGLE_DECL(da9055_mic_r_src,
DA9055_MIXIN_R_SELECT, 4, da9055_mic_r_src_txt);
/* ALC Input Signal Tracking rate select */
static const char * const da9055_signal_tracking_rate_txt[] = {
"1/4", "1/16", "1/256", "1/65536"
};
static SOC_ENUM_SINGLE_DECL(da9055_integ_attack_rate,
DA9055_ALC_CTRL3, 4,
da9055_signal_tracking_rate_txt);
static SOC_ENUM_SINGLE_DECL(da9055_integ_release_rate,
DA9055_ALC_CTRL3, 6,
da9055_signal_tracking_rate_txt);
/* ALC Attack Rate select */
static const char * const da9055_attack_rate_txt[] = {
"44/fs", "88/fs", "176/fs", "352/fs", "704/fs", "1408/fs", "2816/fs",
"5632/fs", "11264/fs", "22528/fs", "45056/fs", "90112/fs", "180224/fs"
};
static SOC_ENUM_SINGLE_DECL(da9055_attack_rate,
DA9055_ALC_CTRL2, 0, da9055_attack_rate_txt);
/* ALC Release Rate select */
static const char * const da9055_release_rate_txt[] = {
"176/fs", "352/fs", "704/fs", "1408/fs", "2816/fs", "5632/fs",
"11264/fs", "22528/fs", "45056/fs", "90112/fs", "180224/fs"
};
static SOC_ENUM_SINGLE_DECL(da9055_release_rate,
DA9055_ALC_CTRL2, 4, da9055_release_rate_txt);
/* ALC Hold Time select */
static const char * const da9055_hold_time_txt[] = {
"62/fs", "124/fs", "248/fs", "496/fs", "992/fs", "1984/fs", "3968/fs",
"7936/fs", "15872/fs", "31744/fs", "63488/fs", "126976/fs",
"253952/fs", "507904/fs", "1015808/fs", "2031616/fs"
};
static SOC_ENUM_SINGLE_DECL(da9055_hold_time,
DA9055_ALC_CTRL3, 0, da9055_hold_time_txt);
static int da9055_get_alc_data(struct snd_soc_component *component, u8 reg_val)
{
int mid_data, top_data;
int sum = 0;
u8 iteration;
for (iteration = 0; iteration < DA9055_ALC_AVG_ITERATIONS;
iteration++) {
/* Select the left or right channel and capture data */
snd_soc_component_write(component, DA9055_ALC_CIC_OP_LVL_CTRL, reg_val);
/* Select middle 8 bits for read back from data register */
snd_soc_component_write(component, DA9055_ALC_CIC_OP_LVL_CTRL,
reg_val | DA9055_ALC_DATA_MIDDLE);
mid_data = snd_soc_component_read(component, DA9055_ALC_CIC_OP_LVL_DATA);
/* Select top 8 bits for read back from data register */
snd_soc_component_write(component, DA9055_ALC_CIC_OP_LVL_CTRL,
reg_val | DA9055_ALC_DATA_TOP);
top_data = snd_soc_component_read(component, DA9055_ALC_CIC_OP_LVL_DATA);
sum += ((mid_data << 8) | (top_data << 16));
}
return sum / DA9055_ALC_AVG_ITERATIONS;
}
static int da9055_put_alc_sw(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
u8 reg_val, adc_left, adc_right, mic_left, mic_right;
int avg_left_data, avg_right_data, offset_l, offset_r;
if (ucontrol->value.integer.value[0]) {
/*
* While enabling ALC (or ALC sync mode), calibration of the DC
* offsets must be done first
*/
/* Save current values from Mic control registers */
mic_left = snd_soc_component_read(component, DA9055_MIC_L_CTRL);
mic_right = snd_soc_component_read(component, DA9055_MIC_R_CTRL);
/* Mute Mic PGA Left and Right */
snd_soc_component_update_bits(component, DA9055_MIC_L_CTRL,
DA9055_MIC_L_MUTE_EN, DA9055_MIC_L_MUTE_EN);
snd_soc_component_update_bits(component, DA9055_MIC_R_CTRL,
DA9055_MIC_R_MUTE_EN, DA9055_MIC_R_MUTE_EN);
/* Save current values from ADC control registers */
adc_left = snd_soc_component_read(component, DA9055_ADC_L_CTRL);
adc_right = snd_soc_component_read(component, DA9055_ADC_R_CTRL);
/* Enable ADC Left and Right */
snd_soc_component_update_bits(component, DA9055_ADC_L_CTRL,
DA9055_ADC_L_EN, DA9055_ADC_L_EN);
snd_soc_component_update_bits(component, DA9055_ADC_R_CTRL,
DA9055_ADC_R_EN, DA9055_ADC_R_EN);
/* Calculate average for Left and Right data */
/* Left Data */
avg_left_data = da9055_get_alc_data(component,
DA9055_ALC_CIC_OP_CHANNEL_LEFT);
/* Right Data */
avg_right_data = da9055_get_alc_data(component,
DA9055_ALC_CIC_OP_CHANNEL_RIGHT);
/* Calculate DC offset */
offset_l = -avg_left_data;
offset_r = -avg_right_data;
reg_val = (offset_l & DA9055_ALC_OFFSET_15_8) >> 8;
snd_soc_component_write(component, DA9055_ALC_OFFSET_OP2M_L, reg_val);
reg_val = (offset_l & DA9055_ALC_OFFSET_17_16) >> 16;
snd_soc_component_write(component, DA9055_ALC_OFFSET_OP2U_L, reg_val);
reg_val = (offset_r & DA9055_ALC_OFFSET_15_8) >> 8;
snd_soc_component_write(component, DA9055_ALC_OFFSET_OP2M_R, reg_val);
reg_val = (offset_r & DA9055_ALC_OFFSET_17_16) >> 16;
snd_soc_component_write(component, DA9055_ALC_OFFSET_OP2U_R, reg_val);
/* Restore original values of ADC control registers */
snd_soc_component_write(component, DA9055_ADC_L_CTRL, adc_left);
snd_soc_component_write(component, DA9055_ADC_R_CTRL, adc_right);
/* Restore original values of Mic control registers */
snd_soc_component_write(component, DA9055_MIC_L_CTRL, mic_left);
snd_soc_component_write(component, DA9055_MIC_R_CTRL, mic_right);
}
return snd_soc_put_volsw(kcontrol, ucontrol);
}
static const struct snd_kcontrol_new da9055_snd_controls[] = {
/* Volume controls */
SOC_DOUBLE_R_TLV("Mic Volume",
DA9055_MIC_L_GAIN, DA9055_MIC_R_GAIN,
0, 0x7, 0, mic_vol_tlv),
SOC_DOUBLE_R_TLV("Aux Volume",
DA9055_AUX_L_GAIN, DA9055_AUX_R_GAIN,
0, 0x3f, 0, aux_vol_tlv),
SOC_DOUBLE_R_TLV("Mixin PGA Volume",
DA9055_MIXIN_L_GAIN, DA9055_MIXIN_R_GAIN,
0, 0xf, 0, mixin_gain_tlv),
SOC_DOUBLE_R_TLV("ADC Volume",
DA9055_ADC_L_GAIN, DA9055_ADC_R_GAIN,
0, 0x7f, 0, digital_gain_tlv),
SOC_DOUBLE_R_TLV("DAC Volume",
DA9055_DAC_L_GAIN, DA9055_DAC_R_GAIN,
0, 0x7f, 0, digital_gain_tlv),
SOC_DOUBLE_R_TLV("Headphone Volume",
DA9055_HP_L_GAIN, DA9055_HP_R_GAIN,
0, 0x3f, 0, hp_vol_tlv),
SOC_SINGLE_TLV("Lineout Volume", DA9055_LINE_GAIN, 0, 0x3f, 0,
lineout_vol_tlv),
/* DAC Equalizer controls */
SOC_SINGLE("DAC EQ Switch", DA9055_DAC_FILTERS4, 7, 1, 0),
SOC_SINGLE_TLV("DAC EQ1 Volume", DA9055_DAC_FILTERS2, 0, 0xf, 0,
eq_gain_tlv),
SOC_SINGLE_TLV("DAC EQ2 Volume", DA9055_DAC_FILTERS2, 4, 0xf, 0,
eq_gain_tlv),
SOC_SINGLE_TLV("DAC EQ3 Volume", DA9055_DAC_FILTERS3, 0, 0xf, 0,
eq_gain_tlv),
SOC_SINGLE_TLV("DAC EQ4 Volume", DA9055_DAC_FILTERS3, 4, 0xf, 0,
eq_gain_tlv),
SOC_SINGLE_TLV("DAC EQ5 Volume", DA9055_DAC_FILTERS4, 0, 0xf, 0,
eq_gain_tlv),
/* High Pass Filter and Voice Mode controls */
SOC_SINGLE("ADC HPF Switch", DA9055_ADC_FILTERS1, 7, 1, 0),
SOC_ENUM("ADC HPF Cutoff", da9055_adc_hpf_cutoff),
SOC_SINGLE("ADC Voice Mode Switch", DA9055_ADC_FILTERS1, 3, 1, 0),
SOC_ENUM("ADC Voice Cutoff", da9055_adc_vf_cutoff),
SOC_SINGLE("DAC HPF Switch", DA9055_DAC_FILTERS1, 7, 1, 0),
SOC_ENUM("DAC HPF Cutoff", da9055_dac_hpf_cutoff),
SOC_SINGLE("DAC Voice Mode Switch", DA9055_DAC_FILTERS1, 3, 1, 0),
SOC_ENUM("DAC Voice Cutoff", da9055_dac_vf_cutoff),
/* Mute controls */
SOC_DOUBLE_R("Mic Switch", DA9055_MIC_L_CTRL,
DA9055_MIC_R_CTRL, 6, 1, 0),
SOC_DOUBLE_R("Aux Switch", DA9055_AUX_L_CTRL,
DA9055_AUX_R_CTRL, 6, 1, 0),
SOC_DOUBLE_R("Mixin PGA Switch", DA9055_MIXIN_L_CTRL,
DA9055_MIXIN_R_CTRL, 6, 1, 0),
SOC_DOUBLE_R("ADC Switch", DA9055_ADC_L_CTRL,
DA9055_ADC_R_CTRL, 6, 1, 0),
SOC_DOUBLE_R("Headphone Switch", DA9055_HP_L_CTRL,
DA9055_HP_R_CTRL, 6, 1, 0),
SOC_SINGLE("Lineout Switch", DA9055_LINE_CTRL, 6, 1, 0),
SOC_SINGLE("DAC Soft Mute Switch", DA9055_DAC_FILTERS5, 7, 1, 0),
SOC_ENUM("DAC Soft Mute Rate", da9055_dac_soft_mute_rate),
/* Zero Cross controls */
SOC_DOUBLE_R("Aux ZC Switch", DA9055_AUX_L_CTRL,
DA9055_AUX_R_CTRL, 4, 1, 0),
SOC_DOUBLE_R("Mixin PGA ZC Switch", DA9055_MIXIN_L_CTRL,
DA9055_MIXIN_R_CTRL, 4, 1, 0),
SOC_DOUBLE_R("Headphone ZC Switch", DA9055_HP_L_CTRL,
DA9055_HP_R_CTRL, 4, 1, 0),
SOC_SINGLE("Lineout ZC Switch", DA9055_LINE_CTRL, 4, 1, 0),
/* Gain Ramping controls */
SOC_DOUBLE_R("Aux Gain Ramping Switch", DA9055_AUX_L_CTRL,
DA9055_AUX_R_CTRL, 5, 1, 0),
SOC_DOUBLE_R("Mixin Gain Ramping Switch", DA9055_MIXIN_L_CTRL,
DA9055_MIXIN_R_CTRL, 5, 1, 0),
SOC_DOUBLE_R("ADC Gain Ramping Switch", DA9055_ADC_L_CTRL,
DA9055_ADC_R_CTRL, 5, 1, 0),
SOC_DOUBLE_R("DAC Gain Ramping Switch", DA9055_DAC_L_CTRL,
DA9055_DAC_R_CTRL, 5, 1, 0),
SOC_DOUBLE_R("Headphone Gain Ramping Switch", DA9055_HP_L_CTRL,
DA9055_HP_R_CTRL, 5, 1, 0),
SOC_SINGLE("Lineout Gain Ramping Switch", DA9055_LINE_CTRL, 5, 1, 0),
SOC_ENUM("Gain Ramping Rate", da9055_gain_ramping_rate),
/* DAC Noise Gate controls */
SOC_SINGLE("DAC NG Switch", DA9055_DAC_NG_CTRL, 7, 1, 0),
SOC_SINGLE("DAC NG ON Threshold", DA9055_DAC_NG_ON_THRESHOLD,
0, 0x7, 0),
SOC_SINGLE("DAC NG OFF Threshold", DA9055_DAC_NG_OFF_THRESHOLD,
0, 0x7, 0),
SOC_ENUM("DAC NG Setup Time", da9055_dac_ng_setup_time),
SOC_ENUM("DAC NG Rampup Rate", da9055_dac_ng_rampup_rate),
SOC_ENUM("DAC NG Rampdown Rate", da9055_dac_ng_rampdown_rate),
/* DAC Invertion control */
SOC_SINGLE("DAC Left Invert", DA9055_DIG_CTRL, 3, 1, 0),
SOC_SINGLE("DAC Right Invert", DA9055_DIG_CTRL, 7, 1, 0),
/* DMIC controls */
SOC_DOUBLE_R("DMIC Switch", DA9055_MIXIN_L_SELECT,
DA9055_MIXIN_R_SELECT, 7, 1, 0),
/* ALC Controls */
SOC_DOUBLE_EXT("ALC Switch", DA9055_ALC_CTRL1, 3, 7, 1, 0,
snd_soc_get_volsw, da9055_put_alc_sw),
SOC_SINGLE_EXT("ALC Sync Mode Switch", DA9055_ALC_CTRL1, 1, 1, 0,
snd_soc_get_volsw, da9055_put_alc_sw),
SOC_SINGLE("ALC Offset Switch", DA9055_ALC_CTRL1, 0, 1, 0),
SOC_SINGLE("ALC Anticlip Mode Switch", DA9055_ALC_ANTICLIP_CTRL,
7, 1, 0),
SOC_SINGLE("ALC Anticlip Level", DA9055_ALC_ANTICLIP_LEVEL,
0, 0x7f, 0),
SOC_SINGLE_TLV("ALC Min Threshold Volume", DA9055_ALC_TARGET_MIN,
0, 0x3f, 1, alc_threshold_tlv),
SOC_SINGLE_TLV("ALC Max Threshold Volume", DA9055_ALC_TARGET_MAX,
0, 0x3f, 1, alc_threshold_tlv),
SOC_SINGLE_TLV("ALC Noise Threshold Volume", DA9055_ALC_NOISE,
0, 0x3f, 1, alc_threshold_tlv),
SOC_SINGLE_TLV("ALC Max Gain Volume", DA9055_ALC_GAIN_LIMITS,
4, 0xf, 0, alc_gain_tlv),
SOC_SINGLE_TLV("ALC Max Attenuation Volume", DA9055_ALC_GAIN_LIMITS,
0, 0xf, 0, alc_gain_tlv),
SOC_SINGLE_TLV("ALC Min Analog Gain Volume",
DA9055_ALC_ANA_GAIN_LIMITS,
0, 0x7, 0, alc_analog_gain_tlv),
SOC_SINGLE_TLV("ALC Max Analog Gain Volume",
DA9055_ALC_ANA_GAIN_LIMITS,
4, 0x7, 0, alc_analog_gain_tlv),
SOC_ENUM("ALC Attack Rate", da9055_attack_rate),
SOC_ENUM("ALC Release Rate", da9055_release_rate),
SOC_ENUM("ALC Hold Time", da9055_hold_time),
/*
* Rate at which input signal envelope is tracked as the signal gets
* larger
*/
SOC_ENUM("ALC Integ Attack Rate", da9055_integ_attack_rate),
/*
* Rate at which input signal envelope is tracked as the signal gets
* smaller
*/
SOC_ENUM("ALC Integ Release Rate", da9055_integ_release_rate),
};
/* DAPM Controls */
/* Mic PGA Left Source */
static const struct snd_kcontrol_new da9055_mic_l_mux_controls =
SOC_DAPM_ENUM("Route", da9055_mic_l_src);
/* Mic PGA Right Source */
static const struct snd_kcontrol_new da9055_mic_r_mux_controls =
SOC_DAPM_ENUM("Route", da9055_mic_r_src);
/* In Mixer Left */
static const struct snd_kcontrol_new da9055_dapm_mixinl_controls[] = {
SOC_DAPM_SINGLE("Aux Left Switch", DA9055_MIXIN_L_SELECT, 0, 1, 0),
SOC_DAPM_SINGLE("Mic Left Switch", DA9055_MIXIN_L_SELECT, 1, 1, 0),
SOC_DAPM_SINGLE("Mic Right Switch", DA9055_MIXIN_L_SELECT, 2, 1, 0),
};
/* In Mixer Right */
static const struct snd_kcontrol_new da9055_dapm_mixinr_controls[] = {
SOC_DAPM_SINGLE("Aux Right Switch", DA9055_MIXIN_R_SELECT, 0, 1, 0),
SOC_DAPM_SINGLE("Mic Right Switch", DA9055_MIXIN_R_SELECT, 1, 1, 0),
SOC_DAPM_SINGLE("Mic Left Switch", DA9055_MIXIN_R_SELECT, 2, 1, 0),
SOC_DAPM_SINGLE("Mixin Left Switch", DA9055_MIXIN_R_SELECT, 3, 1, 0),
};
/* DAC Left Source */
static const struct snd_kcontrol_new da9055_dac_l_mux_controls =
SOC_DAPM_ENUM("Route", da9055_dac_l_src);
/* DAC Right Source */
static const struct snd_kcontrol_new da9055_dac_r_mux_controls =
SOC_DAPM_ENUM("Route", da9055_dac_r_src);
/* Out Mixer Left */
static const struct snd_kcontrol_new da9055_dapm_mixoutl_controls[] = {
SOC_DAPM_SINGLE("Aux Left Switch", DA9055_MIXOUT_L_SELECT, 0, 1, 0),
SOC_DAPM_SINGLE("Mixin Left Switch", DA9055_MIXOUT_L_SELECT, 1, 1, 0),
SOC_DAPM_SINGLE("Mixin Right Switch", DA9055_MIXOUT_L_SELECT, 2, 1, 0),
SOC_DAPM_SINGLE("DAC Left Switch", DA9055_MIXOUT_L_SELECT, 3, 1, 0),
SOC_DAPM_SINGLE("Aux Left Invert Switch", DA9055_MIXOUT_L_SELECT,
4, 1, 0),
SOC_DAPM_SINGLE("Mixin Left Invert Switch", DA9055_MIXOUT_L_SELECT,
5, 1, 0),
SOC_DAPM_SINGLE("Mixin Right Invert Switch", DA9055_MIXOUT_L_SELECT,
6, 1, 0),
};
/* Out Mixer Right */
static const struct snd_kcontrol_new da9055_dapm_mixoutr_controls[] = {
SOC_DAPM_SINGLE("Aux Right Switch", DA9055_MIXOUT_R_SELECT, 0, 1, 0),
SOC_DAPM_SINGLE("Mixin Right Switch", DA9055_MIXOUT_R_SELECT, 1, 1, 0),
SOC_DAPM_SINGLE("Mixin Left Switch", DA9055_MIXOUT_R_SELECT, 2, 1, 0),
SOC_DAPM_SINGLE("DAC Right Switch", DA9055_MIXOUT_R_SELECT, 3, 1, 0),
SOC_DAPM_SINGLE("Aux Right Invert Switch", DA9055_MIXOUT_R_SELECT,
4, 1, 0),
SOC_DAPM_SINGLE("Mixin Right Invert Switch", DA9055_MIXOUT_R_SELECT,
5, 1, 0),
SOC_DAPM_SINGLE("Mixin Left Invert Switch", DA9055_MIXOUT_R_SELECT,
6, 1, 0),
};
/* Headphone Output Enable */
static const struct snd_kcontrol_new da9055_dapm_hp_l_control =
SOC_DAPM_SINGLE("Switch", DA9055_HP_L_CTRL, 3, 1, 0);
static const struct snd_kcontrol_new da9055_dapm_hp_r_control =
SOC_DAPM_SINGLE("Switch", DA9055_HP_R_CTRL, 3, 1, 0);
/* Lineout Output Enable */
static const struct snd_kcontrol_new da9055_dapm_lineout_control =
SOC_DAPM_SINGLE("Switch", DA9055_LINE_CTRL, 3, 1, 0);
/* DAPM widgets */
static const struct snd_soc_dapm_widget da9055_dapm_widgets[] = {
/* Input Side */
/* Input Lines */
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_INPUT("MIC2"),
SND_SOC_DAPM_INPUT("AUXL"),
SND_SOC_DAPM_INPUT("AUXR"),
/* MUXs for Mic PGA source selection */
SND_SOC_DAPM_MUX("Mic Left Source", SND_SOC_NOPM, 0, 0,
&da9055_mic_l_mux_controls),
SND_SOC_DAPM_MUX("Mic Right Source", SND_SOC_NOPM, 0, 0,
&da9055_mic_r_mux_controls),
/* Input PGAs */
SND_SOC_DAPM_PGA("Mic Left", DA9055_MIC_L_CTRL, 7, 0, NULL, 0),
SND_SOC_DAPM_PGA("Mic Right", DA9055_MIC_R_CTRL, 7, 0, NULL, 0),
SND_SOC_DAPM_PGA("Aux Left", DA9055_AUX_L_CTRL, 7, 0, NULL, 0),
SND_SOC_DAPM_PGA("Aux Right", DA9055_AUX_R_CTRL, 7, 0, NULL, 0),
SND_SOC_DAPM_PGA("MIXIN Left", DA9055_MIXIN_L_CTRL, 7, 0, NULL, 0),
SND_SOC_DAPM_PGA("MIXIN Right", DA9055_MIXIN_R_CTRL, 7, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Mic Bias", DA9055_MIC_BIAS_CTRL, 7, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("AIF", DA9055_AIF_CTRL, 7, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Charge Pump", DA9055_CP_CTRL, 7, 0, NULL, 0),
/* Input Mixers */
SND_SOC_DAPM_MIXER("In Mixer Left", SND_SOC_NOPM, 0, 0,
&da9055_dapm_mixinl_controls[0],
ARRAY_SIZE(da9055_dapm_mixinl_controls)),
SND_SOC_DAPM_MIXER("In Mixer Right", SND_SOC_NOPM, 0, 0,
&da9055_dapm_mixinr_controls[0],
ARRAY_SIZE(da9055_dapm_mixinr_controls)),
/* ADCs */
SND_SOC_DAPM_ADC("ADC Left", "Capture", DA9055_ADC_L_CTRL, 7, 0),
SND_SOC_DAPM_ADC("ADC Right", "Capture", DA9055_ADC_R_CTRL, 7, 0),
/* Output Side */
/* MUXs for DAC source selection */
SND_SOC_DAPM_MUX("DAC Left Source", SND_SOC_NOPM, 0, 0,
&da9055_dac_l_mux_controls),
SND_SOC_DAPM_MUX("DAC Right Source", SND_SOC_NOPM, 0, 0,
&da9055_dac_r_mux_controls),
/* AIF input */
SND_SOC_DAPM_AIF_IN("AIFIN Left", "Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIFIN Right", "Playback", 0, SND_SOC_NOPM, 0, 0),
/* DACs */
SND_SOC_DAPM_DAC("DAC Left", "Playback", DA9055_DAC_L_CTRL, 7, 0),
SND_SOC_DAPM_DAC("DAC Right", "Playback", DA9055_DAC_R_CTRL, 7, 0),
/* Output Mixers */
SND_SOC_DAPM_MIXER("Out Mixer Left", SND_SOC_NOPM, 0, 0,
&da9055_dapm_mixoutl_controls[0],
ARRAY_SIZE(da9055_dapm_mixoutl_controls)),
SND_SOC_DAPM_MIXER("Out Mixer Right", SND_SOC_NOPM, 0, 0,
&da9055_dapm_mixoutr_controls[0],
ARRAY_SIZE(da9055_dapm_mixoutr_controls)),
/* Output Enable Switches */
SND_SOC_DAPM_SWITCH("Headphone Left Enable", SND_SOC_NOPM, 0, 0,
&da9055_dapm_hp_l_control),
SND_SOC_DAPM_SWITCH("Headphone Right Enable", SND_SOC_NOPM, 0, 0,
&da9055_dapm_hp_r_control),
SND_SOC_DAPM_SWITCH("Lineout Enable", SND_SOC_NOPM, 0, 0,
&da9055_dapm_lineout_control),
/* Output PGAs */
SND_SOC_DAPM_PGA("MIXOUT Left", DA9055_MIXOUT_L_CTRL, 7, 0, NULL, 0),
SND_SOC_DAPM_PGA("MIXOUT Right", DA9055_MIXOUT_R_CTRL, 7, 0, NULL, 0),
SND_SOC_DAPM_PGA("Lineout", DA9055_LINE_CTRL, 7, 0, NULL, 0),
SND_SOC_DAPM_PGA("Headphone Left", DA9055_HP_L_CTRL, 7, 0, NULL, 0),
SND_SOC_DAPM_PGA("Headphone Right", DA9055_HP_R_CTRL, 7, 0, NULL, 0),
/* Output Lines */
SND_SOC_DAPM_OUTPUT("HPL"),
SND_SOC_DAPM_OUTPUT("HPR"),
SND_SOC_DAPM_OUTPUT("LINE"),
};
/* DAPM audio route definition */
static const struct snd_soc_dapm_route da9055_audio_map[] = {
/* Dest Connecting Widget source */
/* Input path */
{"Mic Left Source", "MIC1_P_N", "MIC1"},
{"Mic Left Source", "MIC1_P", "MIC1"},
{"Mic Left Source", "MIC1_N", "MIC1"},
{"Mic Left Source", "MIC2_L", "MIC2"},
{"Mic Right Source", "MIC2_R_L", "MIC2"},
{"Mic Right Source", "MIC2_R", "MIC2"},
{"Mic Right Source", "MIC2_L", "MIC2"},
{"Mic Left", NULL, "Mic Left Source"},
{"Mic Right", NULL, "Mic Right Source"},
{"Aux Left", NULL, "AUXL"},
{"Aux Right", NULL, "AUXR"},
{"In Mixer Left", "Mic Left Switch", "Mic Left"},
{"In Mixer Left", "Mic Right Switch", "Mic Right"},
{"In Mixer Left", "Aux Left Switch", "Aux Left"},
{"In Mixer Right", "Mic Right Switch", "Mic Right"},
{"In Mixer Right", "Mic Left Switch", "Mic Left"},
{"In Mixer Right", "Aux Right Switch", "Aux Right"},
{"In Mixer Right", "Mixin Left Switch", "MIXIN Left"},
{"MIXIN Left", NULL, "In Mixer Left"},
{"ADC Left", NULL, "MIXIN Left"},
{"MIXIN Right", NULL, "In Mixer Right"},
{"ADC Right", NULL, "MIXIN Right"},
{"ADC Left", NULL, "AIF"},
{"ADC Right", NULL, "AIF"},
/* Output path */
{"AIFIN Left", NULL, "AIF"},
{"AIFIN Right", NULL, "AIF"},
{"DAC Left Source", "ADC output left", "ADC Left"},
{"DAC Left Source", "ADC output right", "ADC Right"},
{"DAC Left Source", "AIF input left", "AIFIN Left"},
{"DAC Left Source", "AIF input right", "AIFIN Right"},
{"DAC Right Source", "ADC output left", "ADC Left"},
{"DAC Right Source", "ADC output right", "ADC Right"},
{"DAC Right Source", "AIF input left", "AIFIN Left"},
{"DAC Right Source", "AIF input right", "AIFIN Right"},
{"DAC Left", NULL, "DAC Left Source"},
{"DAC Right", NULL, "DAC Right Source"},
{"Out Mixer Left", "Aux Left Switch", "Aux Left"},
{"Out Mixer Left", "Mixin Left Switch", "MIXIN Left"},
{"Out Mixer Left", "Mixin Right Switch", "MIXIN Right"},
{"Out Mixer Left", "Aux Left Invert Switch", "Aux Left"},
{"Out Mixer Left", "Mixin Left Invert Switch", "MIXIN Left"},
{"Out Mixer Left", "Mixin Right Invert Switch", "MIXIN Right"},
{"Out Mixer Left", "DAC Left Switch", "DAC Left"},
{"Out Mixer Right", "Aux Right Switch", "Aux Right"},
{"Out Mixer Right", "Mixin Right Switch", "MIXIN Right"},
{"Out Mixer Right", "Mixin Left Switch", "MIXIN Left"},
{"Out Mixer Right", "Aux Right Invert Switch", "Aux Right"},
{"Out Mixer Right", "Mixin Right Invert Switch", "MIXIN Right"},
{"Out Mixer Right", "Mixin Left Invert Switch", "MIXIN Left"},
{"Out Mixer Right", "DAC Right Switch", "DAC Right"},
{"MIXOUT Left", NULL, "Out Mixer Left"},
{"Headphone Left Enable", "Switch", "MIXOUT Left"},
{"Headphone Left", NULL, "Headphone Left Enable"},
{"Headphone Left", NULL, "Charge Pump"},
{"HPL", NULL, "Headphone Left"},
{"MIXOUT Right", NULL, "Out Mixer Right"},
{"Headphone Right Enable", "Switch", "MIXOUT Right"},
{"Headphone Right", NULL, "Headphone Right Enable"},
{"Headphone Right", NULL, "Charge Pump"},
{"HPR", NULL, "Headphone Right"},
{"MIXOUT Right", NULL, "Out Mixer Right"},
{"Lineout Enable", "Switch", "MIXOUT Right"},
{"Lineout", NULL, "Lineout Enable"},
{"LINE", NULL, "Lineout"},
};
/* Codec private data */
struct da9055_priv {
struct regmap *regmap;
unsigned int mclk_rate;
int master;
struct da9055_platform_data *pdata;
};
static const struct reg_default da9055_reg_defaults[] = {
{ 0x21, 0x10 },
{ 0x22, 0x0A },
{ 0x23, 0x00 },
{ 0x24, 0x00 },
{ 0x25, 0x00 },
{ 0x26, 0x00 },
{ 0x27, 0x0C },
{ 0x28, 0x01 },
{ 0x29, 0x08 },
{ 0x2A, 0x32 },
{ 0x2B, 0x00 },
{ 0x30, 0x35 },
{ 0x31, 0x35 },
{ 0x32, 0x00 },
{ 0x33, 0x00 },
{ 0x34, 0x03 },
{ 0x35, 0x03 },
{ 0x36, 0x6F },
{ 0x37, 0x6F },
{ 0x38, 0x80 },
{ 0x39, 0x01 },
{ 0x3A, 0x01 },
{ 0x40, 0x00 },
{ 0x41, 0x88 },
{ 0x42, 0x88 },
{ 0x43, 0x08 },
{ 0x44, 0x80 },
{ 0x45, 0x6F },
{ 0x46, 0x6F },
{ 0x47, 0x61 },
{ 0x48, 0x35 },
{ 0x49, 0x35 },
{ 0x4A, 0x35 },
{ 0x4B, 0x00 },
{ 0x4C, 0x00 },
{ 0x60, 0x44 },
{ 0x61, 0x44 },
{ 0x62, 0x00 },
{ 0x63, 0x40 },
{ 0x64, 0x40 },
{ 0x65, 0x40 },
{ 0x66, 0x40 },
{ 0x67, 0x40 },
{ 0x68, 0x40 },
{ 0x69, 0x48 },
{ 0x6A, 0x40 },
{ 0x6B, 0x41 },
{ 0x6C, 0x40 },
{ 0x6D, 0x40 },
{ 0x6E, 0x10 },
{ 0x6F, 0x10 },
{ 0x90, 0x80 },
{ 0x92, 0x02 },
{ 0x93, 0x00 },
{ 0x99, 0x00 },
{ 0x9A, 0x00 },
{ 0x9B, 0x00 },
{ 0x9C, 0x3F },
{ 0x9D, 0x00 },
{ 0x9E, 0x3F },
{ 0x9F, 0xFF },
{ 0xA0, 0x71 },
{ 0xA1, 0x00 },
{ 0xA2, 0x00 },
{ 0xA6, 0x00 },
{ 0xA7, 0x00 },
{ 0xAB, 0x00 },
{ 0xAC, 0x00 },
{ 0xAD, 0x00 },
{ 0xAF, 0x08 },
{ 0xB0, 0x00 },
{ 0xB1, 0x00 },
{ 0xB2, 0x00 },
};
static bool da9055_volatile_register(struct device *dev,
unsigned int reg)
{
switch (reg) {
case DA9055_STATUS1:
case DA9055_PLL_STATUS:
case DA9055_AUX_L_GAIN_STATUS:
case DA9055_AUX_R_GAIN_STATUS:
case DA9055_MIC_L_GAIN_STATUS:
case DA9055_MIC_R_GAIN_STATUS:
case DA9055_MIXIN_L_GAIN_STATUS:
case DA9055_MIXIN_R_GAIN_STATUS:
case DA9055_ADC_L_GAIN_STATUS:
case DA9055_ADC_R_GAIN_STATUS:
case DA9055_DAC_L_GAIN_STATUS:
case DA9055_DAC_R_GAIN_STATUS:
case DA9055_HP_L_GAIN_STATUS:
case DA9055_HP_R_GAIN_STATUS:
case DA9055_LINE_GAIN_STATUS:
case DA9055_ALC_CIC_OP_LVL_DATA:
return true;
default:
return false;
}
}
/* Set DAI word length */
static int da9055_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct da9055_priv *da9055 = snd_soc_component_get_drvdata(component);
u8 aif_ctrl, fs;
u32 sysclk;
switch (params_width(params)) {
case 16:
aif_ctrl = DA9055_AIF_WORD_S16_LE;
break;
case 20:
aif_ctrl = DA9055_AIF_WORD_S20_3LE;
break;
case 24:
aif_ctrl = DA9055_AIF_WORD_S24_LE;
break;
case 32:
aif_ctrl = DA9055_AIF_WORD_S32_LE;
break;
default:
return -EINVAL;
}
/* Set AIF format */
snd_soc_component_update_bits(component, DA9055_AIF_CTRL, DA9055_AIF_WORD_LENGTH_MASK,
aif_ctrl);
switch (params_rate(params)) {
case 8000:
fs = DA9055_SR_8000;
sysclk = 3072000;
break;
case 11025:
fs = DA9055_SR_11025;
sysclk = 2822400;
break;
case 12000:
fs = DA9055_SR_12000;
sysclk = 3072000;
break;
case 16000:
fs = DA9055_SR_16000;
sysclk = 3072000;
break;
case 22050:
fs = DA9055_SR_22050;
sysclk = 2822400;
break;
case 32000:
fs = DA9055_SR_32000;
sysclk = 3072000;
break;
case 44100:
fs = DA9055_SR_44100;
sysclk = 2822400;
break;
case 48000:
fs = DA9055_SR_48000;
sysclk = 3072000;
break;
case 88200:
fs = DA9055_SR_88200;
sysclk = 2822400;
break;
case 96000:
fs = DA9055_SR_96000;
sysclk = 3072000;
break;
default:
return -EINVAL;
}
if (da9055->mclk_rate) {
/* PLL Mode, Write actual FS */
snd_soc_component_write(component, DA9055_SR, fs);
} else {
/*
* Non-PLL Mode
* When PLL is bypassed, chip assumes constant MCLK of
* 12.288MHz and uses sample rate value to divide this MCLK
* to derive its sys clk. As sys clk has to be 256 * Fs, we
* need to write constant sample rate i.e. 48KHz.
*/
snd_soc_component_write(component, DA9055_SR, DA9055_SR_48000);
}
if (da9055->mclk_rate && (da9055->mclk_rate != sysclk)) {
/* PLL Mode */
if (!da9055->master) {
/* PLL slave mode, enable PLL and also SRM */
snd_soc_component_update_bits(component, DA9055_PLL_CTRL,
DA9055_PLL_EN | DA9055_PLL_SRM_EN,
DA9055_PLL_EN | DA9055_PLL_SRM_EN);
} else {
/* PLL master mode, only enable PLL */
snd_soc_component_update_bits(component, DA9055_PLL_CTRL,
DA9055_PLL_EN, DA9055_PLL_EN);
}
} else {
/* Non PLL Mode, disable PLL */
snd_soc_component_update_bits(component, DA9055_PLL_CTRL, DA9055_PLL_EN, 0);
}
return 0;
}
/* Set DAI mode and Format */
static int da9055_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct da9055_priv *da9055 = snd_soc_component_get_drvdata(component);
u8 aif_clk_mode, aif_ctrl, mode;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
/* DA9055 in I2S Master Mode */
mode = 1;
aif_clk_mode = DA9055_AIF_CLK_EN_MASTER_MODE;
break;
case SND_SOC_DAIFMT_CBS_CFS:
/* DA9055 in I2S Slave Mode */
mode = 0;
aif_clk_mode = DA9055_AIF_CLK_EN_SLAVE_MODE;
break;
default:
return -EINVAL;
}
/* Don't allow change of mode if PLL is enabled */
if ((snd_soc_component_read(component, DA9055_PLL_CTRL) & DA9055_PLL_EN) &&
(da9055->master != mode))
return -EINVAL;
da9055->master = mode;
/* Only I2S is supported */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
aif_ctrl = DA9055_AIF_FORMAT_I2S_MODE;
break;
case SND_SOC_DAIFMT_LEFT_J:
aif_ctrl = DA9055_AIF_FORMAT_LEFT_J;
break;
case SND_SOC_DAIFMT_RIGHT_J:
aif_ctrl = DA9055_AIF_FORMAT_RIGHT_J;
break;
case SND_SOC_DAIFMT_DSP_A:
aif_ctrl = DA9055_AIF_FORMAT_DSP;
break;
default:
return -EINVAL;
}
/* By default only 32 BCLK per WCLK is supported */
aif_clk_mode |= DA9055_AIF_BCLKS_PER_WCLK_32;
snd_soc_component_update_bits(component, DA9055_AIF_CLK_MODE,
(DA9055_AIF_CLK_MODE_MASK | DA9055_AIF_BCLK_MASK),
aif_clk_mode);
snd_soc_component_update_bits(component, DA9055_AIF_CTRL, DA9055_AIF_FORMAT_MASK,
aif_ctrl);
return 0;
}
static int da9055_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
if (mute) {
snd_soc_component_update_bits(component, DA9055_DAC_L_CTRL,
DA9055_DAC_L_MUTE_EN, DA9055_DAC_L_MUTE_EN);
snd_soc_component_update_bits(component, DA9055_DAC_R_CTRL,
DA9055_DAC_R_MUTE_EN, DA9055_DAC_R_MUTE_EN);
} else {
snd_soc_component_update_bits(component, DA9055_DAC_L_CTRL,
DA9055_DAC_L_MUTE_EN, 0);
snd_soc_component_update_bits(component, DA9055_DAC_R_CTRL,
DA9055_DAC_R_MUTE_EN, 0);
}
return 0;
}
#define DA9055_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static int da9055_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct da9055_priv *da9055 = snd_soc_component_get_drvdata(component);
switch (clk_id) {
case DA9055_CLKSRC_MCLK:
switch (freq) {
case 11289600:
case 12000000:
case 12288000:
case 13000000:
case 13500000:
case 14400000:
case 19200000:
case 19680000:
case 19800000:
da9055->mclk_rate = freq;
return 0;
default:
dev_err(codec_dai->dev, "Unsupported MCLK value %d\n",
freq);
return -EINVAL;
}
break;
default:
dev_err(codec_dai->dev, "Unknown clock source %d\n", clk_id);
return -EINVAL;
}
}
/*
* da9055_set_dai_pll : Configure the codec PLL
* @param codec_dai : Pointer to codec DAI
* @param pll_id : da9055 has only one pll, so pll_id is always zero
* @param fref : Input MCLK frequency
* @param fout : FsDM value
* @return int : Zero for success, negative error code for error
*
* Note: Supported PLL input frequencies are 11.2896MHz, 12MHz, 12.288MHz,
* 13MHz, 13.5MHz, 14.4MHz, 19.2MHz, 19.6MHz and 19.8MHz
*/
static int da9055_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
int source, unsigned int fref, unsigned int fout)
{
struct snd_soc_component *component = codec_dai->component;
struct da9055_priv *da9055 = snd_soc_component_get_drvdata(component);
u8 pll_frac_top, pll_frac_bot, pll_integer, cnt;
/* Disable PLL before setting the divisors */
snd_soc_component_update_bits(component, DA9055_PLL_CTRL, DA9055_PLL_EN, 0);
/* In slave mode, there is only one set of divisors */
if (!da9055->master && (fout != 2822400))
goto pll_err;
/* Search pll div array for correct divisors */
for (cnt = 0; cnt < ARRAY_SIZE(da9055_pll_div); cnt++) {
/* Check fref, mode and fout */
if ((fref == da9055_pll_div[cnt].fref) &&
(da9055->master == da9055_pll_div[cnt].mode) &&
(fout == da9055_pll_div[cnt].fout)) {
/* All match, pick up divisors */
pll_frac_top = da9055_pll_div[cnt].frac_top;
pll_frac_bot = da9055_pll_div[cnt].frac_bot;
pll_integer = da9055_pll_div[cnt].integer;
break;
}
}
if (cnt >= ARRAY_SIZE(da9055_pll_div))
goto pll_err;
/* Write PLL dividers */
snd_soc_component_write(component, DA9055_PLL_FRAC_TOP, pll_frac_top);
snd_soc_component_write(component, DA9055_PLL_FRAC_BOT, pll_frac_bot);
snd_soc_component_write(component, DA9055_PLL_INTEGER, pll_integer);
return 0;
pll_err:
dev_err(codec_dai->dev, "Error in setting up PLL\n");
return -EINVAL;
}
/* DAI operations */
static const struct snd_soc_dai_ops da9055_dai_ops = {
.hw_params = da9055_hw_params,
.set_fmt = da9055_set_dai_fmt,
.set_sysclk = da9055_set_dai_sysclk,
.set_pll = da9055_set_dai_pll,
.mute_stream = da9055_mute,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver da9055_dai = {
.name = "da9055-hifi",
/* Playback Capabilities */
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = DA9055_FORMATS,
},
/* Capture Capabilities */
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = DA9055_FORMATS,
},
.ops = &da9055_dai_ops,
.symmetric_rate = 1,
};
static int da9055_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
switch (level) {
case SND_SOC_BIAS_ON:
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
/* Enable VMID reference & master bias */
snd_soc_component_update_bits(component, DA9055_REFERENCES,
DA9055_VMID_EN | DA9055_BIAS_EN,
DA9055_VMID_EN | DA9055_BIAS_EN);
}
break;
case SND_SOC_BIAS_OFF:
/* Disable VMID reference & master bias */
snd_soc_component_update_bits(component, DA9055_REFERENCES,
DA9055_VMID_EN | DA9055_BIAS_EN, 0);
break;
}
return 0;
}
static int da9055_probe(struct snd_soc_component *component)
{
struct da9055_priv *da9055 = snd_soc_component_get_drvdata(component);
/* Enable all Gain Ramps */
snd_soc_component_update_bits(component, DA9055_AUX_L_CTRL,
DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
snd_soc_component_update_bits(component, DA9055_AUX_R_CTRL,
DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
snd_soc_component_update_bits(component, DA9055_MIXIN_L_CTRL,
DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
snd_soc_component_update_bits(component, DA9055_MIXIN_R_CTRL,
DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
snd_soc_component_update_bits(component, DA9055_ADC_L_CTRL,
DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
snd_soc_component_update_bits(component, DA9055_ADC_R_CTRL,
DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
snd_soc_component_update_bits(component, DA9055_DAC_L_CTRL,
DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
snd_soc_component_update_bits(component, DA9055_DAC_R_CTRL,
DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
snd_soc_component_update_bits(component, DA9055_HP_L_CTRL,
DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
snd_soc_component_update_bits(component, DA9055_HP_R_CTRL,
DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
snd_soc_component_update_bits(component, DA9055_LINE_CTRL,
DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
/*
* There are two separate control bits for input and output mixers.
* One to enable corresponding amplifier and other to enable its
* output. As amplifier bits are related to power control, they are
* being managed by DAPM while other (non power related) bits are
* enabled here
*/
snd_soc_component_update_bits(component, DA9055_MIXIN_L_CTRL,
DA9055_MIXIN_L_MIX_EN, DA9055_MIXIN_L_MIX_EN);
snd_soc_component_update_bits(component, DA9055_MIXIN_R_CTRL,
DA9055_MIXIN_R_MIX_EN, DA9055_MIXIN_R_MIX_EN);
snd_soc_component_update_bits(component, DA9055_MIXOUT_L_CTRL,
DA9055_MIXOUT_L_MIX_EN, DA9055_MIXOUT_L_MIX_EN);
snd_soc_component_update_bits(component, DA9055_MIXOUT_R_CTRL,
DA9055_MIXOUT_R_MIX_EN, DA9055_MIXOUT_R_MIX_EN);
/* Set this as per your system configuration */
snd_soc_component_write(component, DA9055_PLL_CTRL, DA9055_PLL_INDIV_10_20_MHZ);
/* Set platform data values */
if (da9055->pdata) {
/* set mic bias source */
if (da9055->pdata->micbias_source) {
snd_soc_component_update_bits(component, DA9055_MIXIN_R_SELECT,
DA9055_MICBIAS2_EN,
DA9055_MICBIAS2_EN);
} else {
snd_soc_component_update_bits(component, DA9055_MIXIN_R_SELECT,
DA9055_MICBIAS2_EN, 0);
}
/* set mic bias voltage */
switch (da9055->pdata->micbias) {
case DA9055_MICBIAS_2_2V:
case DA9055_MICBIAS_2_1V:
case DA9055_MICBIAS_1_8V:
case DA9055_MICBIAS_1_6V:
snd_soc_component_update_bits(component, DA9055_MIC_CONFIG,
DA9055_MICBIAS_LEVEL_MASK,
(da9055->pdata->micbias) << 4);
break;
}
}
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_da9055 = {
.probe = da9055_probe,
.set_bias_level = da9055_set_bias_level,
.controls = da9055_snd_controls,
.num_controls = ARRAY_SIZE(da9055_snd_controls),
.dapm_widgets = da9055_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(da9055_dapm_widgets),
.dapm_routes = da9055_audio_map,
.num_dapm_routes = ARRAY_SIZE(da9055_audio_map),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config da9055_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.reg_defaults = da9055_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(da9055_reg_defaults),
.volatile_reg = da9055_volatile_register,
.cache_type = REGCACHE_RBTREE,
};
static int da9055_i2c_probe(struct i2c_client *i2c)
{
struct da9055_priv *da9055;
struct da9055_platform_data *pdata = dev_get_platdata(&i2c->dev);
int ret;
da9055 = devm_kzalloc(&i2c->dev, sizeof(struct da9055_priv),
GFP_KERNEL);
if (!da9055)
return -ENOMEM;
if (pdata)
da9055->pdata = pdata;
i2c_set_clientdata(i2c, da9055);
da9055->regmap = devm_regmap_init_i2c(i2c, &da9055_regmap_config);
if (IS_ERR(da9055->regmap)) {
ret = PTR_ERR(da9055->regmap);
dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);
return ret;
}
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_da9055, &da9055_dai, 1);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to register da9055 component: %d\n",
ret);
}
return ret;
}
/*
* DO NOT change the device Ids. The naming is intentionally specific as both
* the CODEC and PMIC parts of this chip are instantiated separately as I2C
* devices (both have configurable I2C addresses, and are to all intents and
* purposes separate). As a result there are specific DA9055 Ids for CODEC
* and PMIC, which must be different to operate together.
*/
static const struct i2c_device_id da9055_i2c_id[] = {
{ "da9055-codec", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, da9055_i2c_id);
#ifdef CONFIG_OF
static const struct of_device_id da9055_of_match[] = {
{ .compatible = "dlg,da9055-codec", },
{ }
};
MODULE_DEVICE_TABLE(of, da9055_of_match);
#endif
/* I2C codec control layer */
static struct i2c_driver da9055_i2c_driver = {
.driver = {
.name = "da9055-codec",
.of_match_table = of_match_ptr(da9055_of_match),
},
.probe = da9055_i2c_probe,
.id_table = da9055_i2c_id,
};
module_i2c_driver(da9055_i2c_driver);
MODULE_DESCRIPTION("ASoC DA9055 Codec driver");
MODULE_AUTHOR("David Chen, Ashish Chavan");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/da9055.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* cs42l52.c -- CS42L52 ALSA SoC audio driver
*
* Copyright 2012 CirrusLogic, Inc.
*
* Author: Georgi Vlaev <[email protected]>
* Author: Brian Austin <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/of_gpio.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/input.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/workqueue.h>
#include <linux/platform_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/cs42l52.h>
#include "cs42l52.h"
struct sp_config {
u8 spc, format, spfs;
u32 srate;
};
struct cs42l52_private {
struct regmap *regmap;
struct snd_soc_component *component;
struct device *dev;
struct sp_config config;
struct cs42l52_platform_data pdata;
u32 sysclk;
u8 mclksel;
u32 mclk;
u8 flags;
struct input_dev *beep;
struct work_struct beep_work;
int beep_rate;
};
static const struct reg_default cs42l52_reg_defaults[] = {
{ CS42L52_PWRCTL1, 0x9F }, /* r02 PWRCTL 1 */
{ CS42L52_PWRCTL2, 0x07 }, /* r03 PWRCTL 2 */
{ CS42L52_PWRCTL3, 0xFF }, /* r04 PWRCTL 3 */
{ CS42L52_CLK_CTL, 0xA0 }, /* r05 Clocking Ctl */
{ CS42L52_IFACE_CTL1, 0x00 }, /* r06 Interface Ctl 1 */
{ CS42L52_ADC_PGA_A, 0x80 }, /* r08 Input A Select */
{ CS42L52_ADC_PGA_B, 0x80 }, /* r09 Input B Select */
{ CS42L52_ANALOG_HPF_CTL, 0xA5 }, /* r0A Analog HPF Ctl */
{ CS42L52_ADC_HPF_FREQ, 0x00 }, /* r0B ADC HPF Corner Freq */
{ CS42L52_ADC_MISC_CTL, 0x00 }, /* r0C Misc. ADC Ctl */
{ CS42L52_PB_CTL1, 0x60 }, /* r0D Playback Ctl 1 */
{ CS42L52_MISC_CTL, 0x02 }, /* r0E Misc. Ctl */
{ CS42L52_PB_CTL2, 0x00 }, /* r0F Playback Ctl 2 */
{ CS42L52_MICA_CTL, 0x00 }, /* r10 MICA Amp Ctl */
{ CS42L52_MICB_CTL, 0x00 }, /* r11 MICB Amp Ctl */
{ CS42L52_PGAA_CTL, 0x00 }, /* r12 PGAA Vol, Misc. */
{ CS42L52_PGAB_CTL, 0x00 }, /* r13 PGAB Vol, Misc. */
{ CS42L52_PASSTHRUA_VOL, 0x00 }, /* r14 Bypass A Vol */
{ CS42L52_PASSTHRUB_VOL, 0x00 }, /* r15 Bypass B Vol */
{ CS42L52_ADCA_VOL, 0x00 }, /* r16 ADCA Volume */
{ CS42L52_ADCB_VOL, 0x00 }, /* r17 ADCB Volume */
{ CS42L52_ADCA_MIXER_VOL, 0x80 }, /* r18 ADCA Mixer Volume */
{ CS42L52_ADCB_MIXER_VOL, 0x80 }, /* r19 ADCB Mixer Volume */
{ CS42L52_PCMA_MIXER_VOL, 0x00 }, /* r1A PCMA Mixer Volume */
{ CS42L52_PCMB_MIXER_VOL, 0x00 }, /* r1B PCMB Mixer Volume */
{ CS42L52_BEEP_FREQ, 0x00 }, /* r1C Beep Freq on Time */
{ CS42L52_BEEP_VOL, 0x00 }, /* r1D Beep Volume off Time */
{ CS42L52_BEEP_TONE_CTL, 0x00 }, /* r1E Beep Tone Cfg. */
{ CS42L52_TONE_CTL, 0x00 }, /* r1F Tone Ctl */
{ CS42L52_MASTERA_VOL, 0x00 }, /* r20 Master A Volume */
{ CS42L52_MASTERB_VOL, 0x00 }, /* r21 Master B Volume */
{ CS42L52_HPA_VOL, 0x00 }, /* r22 Headphone A Volume */
{ CS42L52_HPB_VOL, 0x00 }, /* r23 Headphone B Volume */
{ CS42L52_SPKA_VOL, 0x00 }, /* r24 Speaker A Volume */
{ CS42L52_SPKB_VOL, 0x00 }, /* r25 Speaker B Volume */
{ CS42L52_ADC_PCM_MIXER, 0x00 }, /* r26 Channel Mixer and Swap */
{ CS42L52_LIMITER_CTL1, 0x00 }, /* r27 Limit Ctl 1 Thresholds */
{ CS42L52_LIMITER_CTL2, 0x7F }, /* r28 Limit Ctl 2 Release Rate */
{ CS42L52_LIMITER_AT_RATE, 0xC0 }, /* r29 Limiter Attack Rate */
{ CS42L52_ALC_CTL, 0x00 }, /* r2A ALC Ctl 1 Attack Rate */
{ CS42L52_ALC_RATE, 0x3F }, /* r2B ALC Release Rate */
{ CS42L52_ALC_THRESHOLD, 0x3f }, /* r2C ALC Thresholds */
{ CS42L52_NOISE_GATE_CTL, 0x00 }, /* r2D Noise Gate Ctl */
{ CS42L52_CLK_STATUS, 0x00 }, /* r2E Overflow and Clock Status */
{ CS42L52_BATT_COMPEN, 0x00 }, /* r2F battery Compensation */
{ CS42L52_BATT_LEVEL, 0x00 }, /* r30 VP Battery Level */
{ CS42L52_SPK_STATUS, 0x00 }, /* r31 Speaker Status */
{ CS42L52_TEM_CTL, 0x3B }, /* r32 Temp Ctl */
{ CS42L52_THE_FOLDBACK, 0x00 }, /* r33 Foldback */
};
static bool cs42l52_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS42L52_CHIP ... CS42L52_CHARGE_PUMP:
return true;
default:
return false;
}
}
static bool cs42l52_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS42L52_IFACE_CTL2:
case CS42L52_CLK_STATUS:
case CS42L52_BATT_LEVEL:
case CS42L52_SPK_STATUS:
case CS42L52_CHARGE_PUMP:
return true;
default:
return false;
}
}
static DECLARE_TLV_DB_SCALE(hl_tlv, -10200, 50, 0);
static DECLARE_TLV_DB_SCALE(hpd_tlv, -9600, 50, 1);
static DECLARE_TLV_DB_SCALE(ipd_tlv, -9600, 100, 0);
static DECLARE_TLV_DB_SCALE(mic_tlv, 1600, 100, 0);
static DECLARE_TLV_DB_SCALE(pga_tlv, -600, 50, 0);
static DECLARE_TLV_DB_SCALE(pass_tlv, -6000, 50, 0);
static DECLARE_TLV_DB_SCALE(mix_tlv, -5150, 50, 0);
static DECLARE_TLV_DB_SCALE(beep_tlv, -56, 200, 0);
static const DECLARE_TLV_DB_RANGE(limiter_tlv,
0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0),
3, 7, TLV_DB_SCALE_ITEM(-1200, 300, 0)
);
static const char * const cs42l52_adca_text[] = {
"Input1A", "Input2A", "Input3A", "Input4A", "PGA Input Left"};
static const char * const cs42l52_adcb_text[] = {
"Input1B", "Input2B", "Input3B", "Input4B", "PGA Input Right"};
static SOC_ENUM_SINGLE_DECL(adca_enum,
CS42L52_ADC_PGA_A, 5, cs42l52_adca_text);
static SOC_ENUM_SINGLE_DECL(adcb_enum,
CS42L52_ADC_PGA_B, 5, cs42l52_adcb_text);
static const struct snd_kcontrol_new adca_mux =
SOC_DAPM_ENUM("Left ADC Input Capture Mux", adca_enum);
static const struct snd_kcontrol_new adcb_mux =
SOC_DAPM_ENUM("Right ADC Input Capture Mux", adcb_enum);
static const char * const mic_bias_level_text[] = {
"0.5 +VA", "0.6 +VA", "0.7 +VA",
"0.8 +VA", "0.83 +VA", "0.91 +VA"
};
static SOC_ENUM_SINGLE_DECL(mic_bias_level_enum,
CS42L52_IFACE_CTL2, 0, mic_bias_level_text);
static const char * const cs42l52_mic_text[] = { "MIC1", "MIC2" };
static SOC_ENUM_SINGLE_DECL(mica_enum,
CS42L52_MICA_CTL, 5, cs42l52_mic_text);
static SOC_ENUM_SINGLE_DECL(micb_enum,
CS42L52_MICB_CTL, 5, cs42l52_mic_text);
static const char * const digital_output_mux_text[] = {"ADC", "DSP"};
static SOC_ENUM_SINGLE_DECL(digital_output_mux_enum,
CS42L52_ADC_MISC_CTL, 6,
digital_output_mux_text);
static const struct snd_kcontrol_new digital_output_mux =
SOC_DAPM_ENUM("Digital Output Mux", digital_output_mux_enum);
static const char * const hp_gain_num_text[] = {
"0.3959", "0.4571", "0.5111", "0.6047",
"0.7099", "0.8399", "1.000", "1.1430"
};
static SOC_ENUM_SINGLE_DECL(hp_gain_enum,
CS42L52_PB_CTL1, 5,
hp_gain_num_text);
static const char * const beep_pitch_text[] = {
"C4", "C5", "D5", "E5", "F5", "G5", "A5", "B5",
"C6", "D6", "E6", "F6", "G6", "A6", "B6", "C7"
};
static SOC_ENUM_SINGLE_DECL(beep_pitch_enum,
CS42L52_BEEP_FREQ, 4,
beep_pitch_text);
static const char * const beep_ontime_text[] = {
"86 ms", "430 ms", "780 ms", "1.20 s", "1.50 s",
"1.80 s", "2.20 s", "2.50 s", "2.80 s", "3.20 s",
"3.50 s", "3.80 s", "4.20 s", "4.50 s", "4.80 s", "5.20 s"
};
static SOC_ENUM_SINGLE_DECL(beep_ontime_enum,
CS42L52_BEEP_FREQ, 0,
beep_ontime_text);
static const char * const beep_offtime_text[] = {
"1.23 s", "2.58 s", "3.90 s", "5.20 s",
"6.60 s", "8.05 s", "9.35 s", "10.80 s"
};
static SOC_ENUM_SINGLE_DECL(beep_offtime_enum,
CS42L52_BEEP_VOL, 5,
beep_offtime_text);
static const char * const beep_config_text[] = {
"Off", "Single", "Multiple", "Continuous"
};
static SOC_ENUM_SINGLE_DECL(beep_config_enum,
CS42L52_BEEP_TONE_CTL, 6,
beep_config_text);
static const char * const beep_bass_text[] = {
"50 Hz", "100 Hz", "200 Hz", "250 Hz"
};
static SOC_ENUM_SINGLE_DECL(beep_bass_enum,
CS42L52_BEEP_TONE_CTL, 1,
beep_bass_text);
static const char * const beep_treble_text[] = {
"5 kHz", "7 kHz", "10 kHz", " 15 kHz"
};
static SOC_ENUM_SINGLE_DECL(beep_treble_enum,
CS42L52_BEEP_TONE_CTL, 3,
beep_treble_text);
static const char * const ng_threshold_text[] = {
"-34dB", "-37dB", "-40dB", "-43dB",
"-46dB", "-52dB", "-58dB", "-64dB"
};
static SOC_ENUM_SINGLE_DECL(ng_threshold_enum,
CS42L52_NOISE_GATE_CTL, 2,
ng_threshold_text);
static const char * const cs42l52_ng_delay_text[] = {
"50ms", "100ms", "150ms", "200ms"};
static SOC_ENUM_SINGLE_DECL(ng_delay_enum,
CS42L52_NOISE_GATE_CTL, 0,
cs42l52_ng_delay_text);
static const char * const cs42l52_ng_type_text[] = {
"Apply Specific", "Apply All"
};
static SOC_ENUM_SINGLE_DECL(ng_type_enum,
CS42L52_NOISE_GATE_CTL, 6,
cs42l52_ng_type_text);
static const char * const left_swap_text[] = {
"Left", "LR 2", "Right"};
static const char * const right_swap_text[] = {
"Right", "LR 2", "Left"};
static const unsigned int swap_values[] = { 0, 1, 3 };
static const struct soc_enum adca_swap_enum =
SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 2, 3,
ARRAY_SIZE(left_swap_text),
left_swap_text,
swap_values);
static const struct snd_kcontrol_new adca_mixer =
SOC_DAPM_ENUM("Route", adca_swap_enum);
static const struct soc_enum pcma_swap_enum =
SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 6, 3,
ARRAY_SIZE(left_swap_text),
left_swap_text,
swap_values);
static const struct snd_kcontrol_new pcma_mixer =
SOC_DAPM_ENUM("Route", pcma_swap_enum);
static const struct soc_enum adcb_swap_enum =
SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 0, 3,
ARRAY_SIZE(right_swap_text),
right_swap_text,
swap_values);
static const struct snd_kcontrol_new adcb_mixer =
SOC_DAPM_ENUM("Route", adcb_swap_enum);
static const struct soc_enum pcmb_swap_enum =
SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 4, 3,
ARRAY_SIZE(right_swap_text),
right_swap_text,
swap_values);
static const struct snd_kcontrol_new pcmb_mixer =
SOC_DAPM_ENUM("Route", pcmb_swap_enum);
static const struct snd_kcontrol_new passthrul_ctl =
SOC_DAPM_SINGLE("Switch", CS42L52_MISC_CTL, 6, 1, 0);
static const struct snd_kcontrol_new passthrur_ctl =
SOC_DAPM_SINGLE("Switch", CS42L52_MISC_CTL, 7, 1, 0);
static const struct snd_kcontrol_new spkl_ctl =
SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 0, 1, 1);
static const struct snd_kcontrol_new spkr_ctl =
SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 2, 1, 1);
static const struct snd_kcontrol_new hpl_ctl =
SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 4, 1, 1);
static const struct snd_kcontrol_new hpr_ctl =
SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 6, 1, 1);
static const struct snd_kcontrol_new cs42l52_snd_controls[] = {
SOC_DOUBLE_R_SX_TLV("Master Volume", CS42L52_MASTERA_VOL,
CS42L52_MASTERB_VOL, 0, 0x34, 0xE4, hl_tlv),
SOC_DOUBLE_R_SX_TLV("Headphone Volume", CS42L52_HPA_VOL,
CS42L52_HPB_VOL, 0, 0x34, 0xC0, hpd_tlv),
SOC_ENUM("Headphone Analog Gain", hp_gain_enum),
SOC_DOUBLE_R_SX_TLV("Speaker Volume", CS42L52_SPKA_VOL,
CS42L52_SPKB_VOL, 0, 0x40, 0xC0, hl_tlv),
SOC_DOUBLE_R_SX_TLV("Bypass Volume", CS42L52_PASSTHRUA_VOL,
CS42L52_PASSTHRUB_VOL, 0, 0x88, 0x90, pass_tlv),
SOC_DOUBLE("Bypass Mute", CS42L52_MISC_CTL, 4, 5, 1, 0),
SOC_DOUBLE_R_TLV("MIC Gain Volume", CS42L52_MICA_CTL,
CS42L52_MICB_CTL, 0, 0x10, 0, mic_tlv),
SOC_ENUM("MIC Bias Level", mic_bias_level_enum),
SOC_DOUBLE_R_SX_TLV("ADC Volume", CS42L52_ADCA_VOL,
CS42L52_ADCB_VOL, 0, 0xA0, 0x78, ipd_tlv),
SOC_DOUBLE_R_SX_TLV("ADC Mixer Volume",
CS42L52_ADCA_MIXER_VOL, CS42L52_ADCB_MIXER_VOL,
0, 0x19, 0x7F, mix_tlv),
SOC_DOUBLE("ADC Switch", CS42L52_ADC_MISC_CTL, 0, 1, 1, 0),
SOC_DOUBLE_R("ADC Mixer Switch", CS42L52_ADCA_MIXER_VOL,
CS42L52_ADCB_MIXER_VOL, 7, 1, 1),
SOC_DOUBLE_R_SX_TLV("PGA Volume", CS42L52_PGAA_CTL,
CS42L52_PGAB_CTL, 0, 0x28, 0x24, pga_tlv),
SOC_DOUBLE_R_SX_TLV("PCM Mixer Volume",
CS42L52_PCMA_MIXER_VOL, CS42L52_PCMB_MIXER_VOL,
0, 0x19, 0x7f, mix_tlv),
SOC_DOUBLE_R("PCM Mixer Switch",
CS42L52_PCMA_MIXER_VOL, CS42L52_PCMB_MIXER_VOL, 7, 1, 1),
SOC_ENUM("Beep Config", beep_config_enum),
SOC_ENUM("Beep Pitch", beep_pitch_enum),
SOC_ENUM("Beep on Time", beep_ontime_enum),
SOC_ENUM("Beep off Time", beep_offtime_enum),
SOC_SINGLE_SX_TLV("Beep Volume", CS42L52_BEEP_VOL,
0, 0x07, 0x1f, beep_tlv),
SOC_SINGLE("Beep Mixer Switch", CS42L52_BEEP_TONE_CTL, 5, 1, 1),
SOC_ENUM("Beep Treble Corner Freq", beep_treble_enum),
SOC_ENUM("Beep Bass Corner Freq", beep_bass_enum),
SOC_SINGLE("Tone Control Switch", CS42L52_BEEP_TONE_CTL, 0, 1, 1),
SOC_SINGLE_TLV("Treble Gain Volume",
CS42L52_TONE_CTL, 4, 15, 1, hl_tlv),
SOC_SINGLE_TLV("Bass Gain Volume",
CS42L52_TONE_CTL, 0, 15, 1, hl_tlv),
/* Limiter */
SOC_SINGLE_TLV("Limiter Max Threshold Volume",
CS42L52_LIMITER_CTL1, 5, 7, 0, limiter_tlv),
SOC_SINGLE_TLV("Limiter Cushion Threshold Volume",
CS42L52_LIMITER_CTL1, 2, 7, 0, limiter_tlv),
SOC_SINGLE_TLV("Limiter Release Rate Volume",
CS42L52_LIMITER_CTL2, 0, 63, 0, limiter_tlv),
SOC_SINGLE_TLV("Limiter Attack Rate Volume",
CS42L52_LIMITER_AT_RATE, 0, 63, 0, limiter_tlv),
SOC_SINGLE("Limiter SR Switch", CS42L52_LIMITER_CTL1, 1, 1, 0),
SOC_SINGLE("Limiter ZC Switch", CS42L52_LIMITER_CTL1, 0, 1, 0),
SOC_SINGLE("Limiter Switch", CS42L52_LIMITER_CTL2, 7, 1, 0),
/* ALC */
SOC_SINGLE_TLV("ALC Attack Rate Volume", CS42L52_ALC_CTL,
0, 63, 0, limiter_tlv),
SOC_SINGLE_TLV("ALC Release Rate Volume", CS42L52_ALC_RATE,
0, 63, 0, limiter_tlv),
SOC_SINGLE_TLV("ALC Max Threshold Volume", CS42L52_ALC_THRESHOLD,
5, 7, 0, limiter_tlv),
SOC_SINGLE_TLV("ALC Min Threshold Volume", CS42L52_ALC_THRESHOLD,
2, 7, 0, limiter_tlv),
SOC_DOUBLE_R("ALC SR Capture Switch", CS42L52_PGAA_CTL,
CS42L52_PGAB_CTL, 7, 1, 1),
SOC_DOUBLE_R("ALC ZC Capture Switch", CS42L52_PGAA_CTL,
CS42L52_PGAB_CTL, 6, 1, 1),
SOC_DOUBLE("ALC Capture Switch", CS42L52_ALC_CTL, 6, 7, 1, 0),
/* Noise gate */
SOC_ENUM("NG Type Switch", ng_type_enum),
SOC_SINGLE("NG Enable Switch", CS42L52_NOISE_GATE_CTL, 6, 1, 0),
SOC_SINGLE("NG Boost Switch", CS42L52_NOISE_GATE_CTL, 5, 1, 1),
SOC_ENUM("NG Threshold", ng_threshold_enum),
SOC_ENUM("NG Delay", ng_delay_enum),
SOC_DOUBLE("HPF Switch", CS42L52_ANALOG_HPF_CTL, 5, 7, 1, 0),
SOC_DOUBLE("Analog SR Switch", CS42L52_ANALOG_HPF_CTL, 1, 3, 1, 1),
SOC_DOUBLE("Analog ZC Switch", CS42L52_ANALOG_HPF_CTL, 0, 2, 1, 1),
SOC_SINGLE("Digital SR Switch", CS42L52_MISC_CTL, 1, 1, 0),
SOC_SINGLE("Digital ZC Switch", CS42L52_MISC_CTL, 0, 1, 0),
SOC_SINGLE("Deemphasis Switch", CS42L52_MISC_CTL, 2, 1, 0),
SOC_SINGLE("Batt Compensation Switch", CS42L52_BATT_COMPEN, 7, 1, 0),
SOC_SINGLE("Batt VP Monitor Switch", CS42L52_BATT_COMPEN, 6, 1, 0),
SOC_SINGLE("Batt VP ref", CS42L52_BATT_COMPEN, 0, 0x0f, 0),
SOC_SINGLE("PGA AIN1L Switch", CS42L52_ADC_PGA_A, 0, 1, 0),
SOC_SINGLE("PGA AIN1R Switch", CS42L52_ADC_PGA_B, 0, 1, 0),
SOC_SINGLE("PGA AIN2L Switch", CS42L52_ADC_PGA_A, 1, 1, 0),
SOC_SINGLE("PGA AIN2R Switch", CS42L52_ADC_PGA_B, 1, 1, 0),
SOC_SINGLE("PGA AIN3L Switch", CS42L52_ADC_PGA_A, 2, 1, 0),
SOC_SINGLE("PGA AIN3R Switch", CS42L52_ADC_PGA_B, 2, 1, 0),
SOC_SINGLE("PGA AIN4L Switch", CS42L52_ADC_PGA_A, 3, 1, 0),
SOC_SINGLE("PGA AIN4R Switch", CS42L52_ADC_PGA_B, 3, 1, 0),
SOC_SINGLE("PGA MICA Switch", CS42L52_ADC_PGA_A, 4, 1, 0),
SOC_SINGLE("PGA MICB Switch", CS42L52_ADC_PGA_B, 4, 1, 0),
};
static const struct snd_kcontrol_new cs42l52_mica_controls[] = {
SOC_ENUM("MICA Select", mica_enum),
};
static const struct snd_kcontrol_new cs42l52_micb_controls[] = {
SOC_ENUM("MICB Select", micb_enum),
};
static int cs42l52_add_mic_controls(struct snd_soc_component *component)
{
struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component);
struct cs42l52_platform_data *pdata = &cs42l52->pdata;
if (!pdata->mica_diff_cfg)
snd_soc_add_component_controls(component, cs42l52_mica_controls,
ARRAY_SIZE(cs42l52_mica_controls));
if (!pdata->micb_diff_cfg)
snd_soc_add_component_controls(component, cs42l52_micb_controls,
ARRAY_SIZE(cs42l52_micb_controls));
return 0;
}
static const struct snd_soc_dapm_widget cs42l52_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("AIN1L"),
SND_SOC_DAPM_INPUT("AIN1R"),
SND_SOC_DAPM_INPUT("AIN2L"),
SND_SOC_DAPM_INPUT("AIN2R"),
SND_SOC_DAPM_INPUT("AIN3L"),
SND_SOC_DAPM_INPUT("AIN3R"),
SND_SOC_DAPM_INPUT("AIN4L"),
SND_SOC_DAPM_INPUT("AIN4R"),
SND_SOC_DAPM_INPUT("MICA"),
SND_SOC_DAPM_INPUT("MICB"),
SND_SOC_DAPM_SIGGEN("Beep"),
SND_SOC_DAPM_AIF_OUT("AIFOUTL", NULL, 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIFOUTR", NULL, 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("ADC Left", NULL, CS42L52_PWRCTL1, 1, 1),
SND_SOC_DAPM_ADC("ADC Right", NULL, CS42L52_PWRCTL1, 2, 1),
SND_SOC_DAPM_PGA("PGA Left", CS42L52_PWRCTL1, 3, 1, NULL, 0),
SND_SOC_DAPM_PGA("PGA Right", CS42L52_PWRCTL1, 4, 1, NULL, 0),
SND_SOC_DAPM_MUX("ADC Left Mux", SND_SOC_NOPM, 0, 0, &adca_mux),
SND_SOC_DAPM_MUX("ADC Right Mux", SND_SOC_NOPM, 0, 0, &adcb_mux),
SND_SOC_DAPM_MUX("ADC Left Swap", SND_SOC_NOPM,
0, 0, &adca_mixer),
SND_SOC_DAPM_MUX("ADC Right Swap", SND_SOC_NOPM,
0, 0, &adcb_mixer),
SND_SOC_DAPM_MUX("Output Mux", SND_SOC_NOPM,
0, 0, &digital_output_mux),
SND_SOC_DAPM_PGA("PGA MICA", CS42L52_PWRCTL2, 1, 1, NULL, 0),
SND_SOC_DAPM_PGA("PGA MICB", CS42L52_PWRCTL2, 2, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("Mic Bias", CS42L52_PWRCTL2, 0, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("Charge Pump", CS42L52_PWRCTL1, 7, 1, NULL, 0),
SND_SOC_DAPM_AIF_IN("AIFINL", NULL, 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIFINR", NULL, 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DAC Left", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DAC Right", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SWITCH("Bypass Left", CS42L52_MISC_CTL,
6, 0, &passthrul_ctl),
SND_SOC_DAPM_SWITCH("Bypass Right", CS42L52_MISC_CTL,
7, 0, &passthrur_ctl),
SND_SOC_DAPM_MUX("PCM Left Swap", SND_SOC_NOPM,
0, 0, &pcma_mixer),
SND_SOC_DAPM_MUX("PCM Right Swap", SND_SOC_NOPM,
0, 0, &pcmb_mixer),
SND_SOC_DAPM_SWITCH("HP Left Amp", SND_SOC_NOPM, 0, 0, &hpl_ctl),
SND_SOC_DAPM_SWITCH("HP Right Amp", SND_SOC_NOPM, 0, 0, &hpr_ctl),
SND_SOC_DAPM_SWITCH("SPK Left Amp", SND_SOC_NOPM, 0, 0, &spkl_ctl),
SND_SOC_DAPM_SWITCH("SPK Right Amp", SND_SOC_NOPM, 0, 0, &spkr_ctl),
SND_SOC_DAPM_OUTPUT("HPOUTA"),
SND_SOC_DAPM_OUTPUT("HPOUTB"),
SND_SOC_DAPM_OUTPUT("SPKOUTA"),
SND_SOC_DAPM_OUTPUT("SPKOUTB"),
};
static const struct snd_soc_dapm_route cs42l52_audio_map[] = {
{"Capture", NULL, "AIFOUTL"},
{"Capture", NULL, "AIFOUTL"},
{"AIFOUTL", NULL, "Output Mux"},
{"AIFOUTR", NULL, "Output Mux"},
{"Output Mux", "ADC", "ADC Left"},
{"Output Mux", "ADC", "ADC Right"},
{"ADC Left", NULL, "Charge Pump"},
{"ADC Right", NULL, "Charge Pump"},
{"Charge Pump", NULL, "ADC Left Mux"},
{"Charge Pump", NULL, "ADC Right Mux"},
{"ADC Left Mux", "Input1A", "AIN1L"},
{"ADC Right Mux", "Input1B", "AIN1R"},
{"ADC Left Mux", "Input2A", "AIN2L"},
{"ADC Right Mux", "Input2B", "AIN2R"},
{"ADC Left Mux", "Input3A", "AIN3L"},
{"ADC Right Mux", "Input3B", "AIN3R"},
{"ADC Left Mux", "Input4A", "AIN4L"},
{"ADC Right Mux", "Input4B", "AIN4R"},
{"ADC Left Mux", "PGA Input Left", "PGA Left"},
{"ADC Right Mux", "PGA Input Right" , "PGA Right"},
{"PGA Left", "Switch", "AIN1L"},
{"PGA Right", "Switch", "AIN1R"},
{"PGA Left", "Switch", "AIN2L"},
{"PGA Right", "Switch", "AIN2R"},
{"PGA Left", "Switch", "AIN3L"},
{"PGA Right", "Switch", "AIN3R"},
{"PGA Left", "Switch", "AIN4L"},
{"PGA Right", "Switch", "AIN4R"},
{"PGA Left", "Switch", "PGA MICA"},
{"PGA MICA", NULL, "MICA"},
{"PGA Right", "Switch", "PGA MICB"},
{"PGA MICB", NULL, "MICB"},
{"HPOUTA", NULL, "HP Left Amp"},
{"HPOUTB", NULL, "HP Right Amp"},
{"HP Left Amp", NULL, "Bypass Left"},
{"HP Right Amp", NULL, "Bypass Right"},
{"Bypass Left", "Switch", "PGA Left"},
{"Bypass Right", "Switch", "PGA Right"},
{"HP Left Amp", "Switch", "DAC Left"},
{"HP Right Amp", "Switch", "DAC Right"},
{"SPKOUTA", NULL, "SPK Left Amp"},
{"SPKOUTB", NULL, "SPK Right Amp"},
{"SPK Left Amp", NULL, "Beep"},
{"SPK Right Amp", NULL, "Beep"},
{"SPK Left Amp", "Switch", "Playback"},
{"SPK Right Amp", "Switch", "Playback"},
{"DAC Left", NULL, "Beep"},
{"DAC Right", NULL, "Beep"},
{"DAC Left", NULL, "Playback"},
{"DAC Right", NULL, "Playback"},
{"Output Mux", "DSP", "Playback"},
{"Output Mux", "DSP", "Playback"},
{"AIFINL", NULL, "Playback"},
{"AIFINR", NULL, "Playback"},
};
struct cs42l52_clk_para {
u32 mclk;
u32 rate;
u8 speed;
u8 group;
u8 videoclk;
u8 ratio;
u8 mclkdiv2;
};
static const struct cs42l52_clk_para clk_map_table[] = {
/*8k*/
{12288000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
{18432000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
{12000000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
{24000000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
{27000000, 8000, CLK_QS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 0},
/*11.025k*/
{11289600, 11025, CLK_QS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
{16934400, 11025, CLK_QS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
/*16k*/
{12288000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
{18432000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
{12000000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
{24000000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
{27000000, 16000, CLK_HS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 1},
/*22.05k*/
{11289600, 22050, CLK_HS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
{16934400, 22050, CLK_HS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
/* 32k */
{12288000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
{18432000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
{12000000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
{24000000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
{27000000, 32000, CLK_SS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 0},
/* 44.1k */
{11289600, 44100, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
{16934400, 44100, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
/* 48k */
{12288000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
{18432000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
{12000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 0},
{24000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 1},
{27000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_27M_MCLK, CLK_R_125, 1},
/* 88.2k */
{11289600, 88200, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
{16934400, 88200, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
/* 96k */
{12288000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
{18432000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
{12000000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 0},
{24000000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 1},
};
static int cs42l52_get_clk(int mclk, int rate)
{
int i, ret = -EINVAL;
u_int mclk1, mclk2 = 0;
for (i = 0; i < ARRAY_SIZE(clk_map_table); i++) {
if (clk_map_table[i].rate == rate) {
mclk1 = clk_map_table[i].mclk;
if (abs(mclk - mclk1) < abs(mclk - mclk2)) {
mclk2 = mclk1;
ret = i;
}
}
}
return ret;
}
static int cs42l52_set_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component);
if ((freq >= CS42L52_MIN_CLK) && (freq <= CS42L52_MAX_CLK)) {
cs42l52->sysclk = freq;
} else {
dev_err(component->dev, "Invalid freq parameter\n");
return -EINVAL;
}
return 0;
}
static int cs42l52_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component);
u8 iface = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
iface = CS42L52_IFACE_CTL1_MASTER;
break;
case SND_SOC_DAIFMT_CBS_CFS:
iface = CS42L52_IFACE_CTL1_SLAVE;
break;
default:
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface |= CS42L52_IFACE_CTL1_ADC_FMT_I2S |
CS42L52_IFACE_CTL1_DAC_FMT_I2S;
break;
case SND_SOC_DAIFMT_RIGHT_J:
iface |= CS42L52_IFACE_CTL1_DAC_FMT_RIGHT_J;
break;
case SND_SOC_DAIFMT_LEFT_J:
iface |= CS42L52_IFACE_CTL1_ADC_FMT_LEFT_J |
CS42L52_IFACE_CTL1_DAC_FMT_LEFT_J;
break;
case SND_SOC_DAIFMT_DSP_A:
iface |= CS42L52_IFACE_CTL1_DSP_MODE_EN;
break;
case SND_SOC_DAIFMT_DSP_B:
break;
default:
return -EINVAL;
}
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
iface |= CS42L52_IFACE_CTL1_INV_SCLK;
break;
case SND_SOC_DAIFMT_IB_NF:
iface |= CS42L52_IFACE_CTL1_INV_SCLK;
break;
case SND_SOC_DAIFMT_NB_IF:
break;
default:
return -EINVAL;
}
cs42l52->config.format = iface;
snd_soc_component_write(component, CS42L52_IFACE_CTL1, cs42l52->config.format);
return 0;
}
static int cs42l52_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
if (mute)
snd_soc_component_update_bits(component, CS42L52_PB_CTL1,
CS42L52_PB_CTL1_MUTE_MASK,
CS42L52_PB_CTL1_MUTE);
else
snd_soc_component_update_bits(component, CS42L52_PB_CTL1,
CS42L52_PB_CTL1_MUTE_MASK,
CS42L52_PB_CTL1_UNMUTE);
return 0;
}
static int cs42l52_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component);
u32 clk = 0;
int index;
index = cs42l52_get_clk(cs42l52->sysclk, params_rate(params));
if (index >= 0) {
cs42l52->sysclk = clk_map_table[index].mclk;
clk |= (clk_map_table[index].speed << CLK_SPEED_SHIFT) |
(clk_map_table[index].group << CLK_32K_SR_SHIFT) |
(clk_map_table[index].videoclk << CLK_27M_MCLK_SHIFT) |
(clk_map_table[index].ratio << CLK_RATIO_SHIFT) |
clk_map_table[index].mclkdiv2;
snd_soc_component_write(component, CS42L52_CLK_CTL, clk);
} else {
dev_err(component->dev, "can't get correct mclk\n");
return -EINVAL;
}
return 0;
}
static int cs42l52_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
snd_soc_component_update_bits(component, CS42L52_PWRCTL1,
CS42L52_PWRCTL1_PDN_CODEC, 0);
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
regcache_cache_only(cs42l52->regmap, false);
regcache_sync(cs42l52->regmap);
}
snd_soc_component_write(component, CS42L52_PWRCTL1, CS42L52_PWRCTL1_PDN_ALL);
break;
case SND_SOC_BIAS_OFF:
snd_soc_component_write(component, CS42L52_PWRCTL1, CS42L52_PWRCTL1_PDN_ALL);
regcache_cache_only(cs42l52->regmap, true);
break;
}
return 0;
}
#define CS42L52_RATES (SNDRV_PCM_RATE_8000_96000)
#define CS42L52_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE | \
SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_U18_3LE | \
SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_U20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_U24_LE)
static const struct snd_soc_dai_ops cs42l52_ops = {
.hw_params = cs42l52_pcm_hw_params,
.mute_stream = cs42l52_mute,
.set_fmt = cs42l52_set_fmt,
.set_sysclk = cs42l52_set_sysclk,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver cs42l52_dai = {
.name = "cs42l52",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = CS42L52_RATES,
.formats = CS42L52_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = CS42L52_RATES,
.formats = CS42L52_FORMATS,
},
.ops = &cs42l52_ops,
};
static int beep_rates[] = {
261, 522, 585, 667, 706, 774, 889, 1000,
1043, 1200, 1333, 1412, 1600, 1714, 2000, 2182
};
static void cs42l52_beep_work(struct work_struct *work)
{
struct cs42l52_private *cs42l52 =
container_of(work, struct cs42l52_private, beep_work);
struct snd_soc_component *component = cs42l52->component;
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
int i;
int val = 0;
int best = 0;
if (cs42l52->beep_rate) {
for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
if (abs(cs42l52->beep_rate - beep_rates[i]) <
abs(cs42l52->beep_rate - beep_rates[best]))
best = i;
}
dev_dbg(component->dev, "Set beep rate %dHz for requested %dHz\n",
beep_rates[best], cs42l52->beep_rate);
val = (best << CS42L52_BEEP_RATE_SHIFT);
snd_soc_dapm_enable_pin(dapm, "Beep");
} else {
dev_dbg(component->dev, "Disabling beep\n");
snd_soc_dapm_disable_pin(dapm, "Beep");
}
snd_soc_component_update_bits(component, CS42L52_BEEP_FREQ,
CS42L52_BEEP_RATE_MASK, val);
snd_soc_dapm_sync(dapm);
}
/* For usability define a way of injecting beep events for the device -
* many systems will not have a keyboard.
*/
static int cs42l52_beep_event(struct input_dev *dev, unsigned int type,
unsigned int code, int hz)
{
struct snd_soc_component *component = input_get_drvdata(dev);
struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component);
dev_dbg(component->dev, "Beep event %x %x\n", code, hz);
switch (code) {
case SND_BELL:
if (hz)
hz = 261;
break;
case SND_TONE:
break;
default:
return -1;
}
/* Kick the beep from a workqueue */
cs42l52->beep_rate = hz;
schedule_work(&cs42l52->beep_work);
return 0;
}
static ssize_t beep_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct cs42l52_private *cs42l52 = dev_get_drvdata(dev);
long int time;
int ret;
ret = kstrtol(buf, 10, &time);
if (ret != 0)
return ret;
input_event(cs42l52->beep, EV_SND, SND_TONE, time);
return count;
}
static DEVICE_ATTR_WO(beep);
static void cs42l52_init_beep(struct snd_soc_component *component)
{
struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component);
int ret;
cs42l52->beep = devm_input_allocate_device(component->dev);
if (!cs42l52->beep) {
dev_err(component->dev, "Failed to allocate beep device\n");
return;
}
INIT_WORK(&cs42l52->beep_work, cs42l52_beep_work);
cs42l52->beep_rate = 0;
cs42l52->beep->name = "CS42L52 Beep Generator";
cs42l52->beep->phys = dev_name(component->dev);
cs42l52->beep->id.bustype = BUS_I2C;
cs42l52->beep->evbit[0] = BIT_MASK(EV_SND);
cs42l52->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
cs42l52->beep->event = cs42l52_beep_event;
cs42l52->beep->dev.parent = component->dev;
input_set_drvdata(cs42l52->beep, component);
ret = input_register_device(cs42l52->beep);
if (ret != 0) {
cs42l52->beep = NULL;
dev_err(component->dev, "Failed to register beep device\n");
}
ret = device_create_file(component->dev, &dev_attr_beep);
if (ret != 0) {
dev_err(component->dev, "Failed to create keyclick file: %d\n",
ret);
}
}
static void cs42l52_free_beep(struct snd_soc_component *component)
{
struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component);
device_remove_file(component->dev, &dev_attr_beep);
cancel_work_sync(&cs42l52->beep_work);
cs42l52->beep = NULL;
snd_soc_component_update_bits(component, CS42L52_BEEP_TONE_CTL,
CS42L52_BEEP_EN_MASK, 0);
}
static int cs42l52_probe(struct snd_soc_component *component)
{
struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component);
regcache_cache_only(cs42l52->regmap, true);
cs42l52_add_mic_controls(component);
cs42l52_init_beep(component);
cs42l52->sysclk = CS42L52_DEFAULT_CLK;
cs42l52->config.format = CS42L52_DEFAULT_FORMAT;
return 0;
}
static void cs42l52_remove(struct snd_soc_component *component)
{
cs42l52_free_beep(component);
}
static const struct snd_soc_component_driver soc_component_dev_cs42l52 = {
.probe = cs42l52_probe,
.remove = cs42l52_remove,
.set_bias_level = cs42l52_set_bias_level,
.controls = cs42l52_snd_controls,
.num_controls = ARRAY_SIZE(cs42l52_snd_controls),
.dapm_widgets = cs42l52_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(cs42l52_dapm_widgets),
.dapm_routes = cs42l52_audio_map,
.num_dapm_routes = ARRAY_SIZE(cs42l52_audio_map),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
/* Current and threshold powerup sequence Pg37 */
static const struct reg_sequence cs42l52_threshold_patch[] = {
{ 0x00, 0x99 },
{ 0x3E, 0xBA },
{ 0x47, 0x80 },
{ 0x32, 0xBB },
{ 0x32, 0x3B },
{ 0x00, 0x00 },
};
static const struct regmap_config cs42l52_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = CS42L52_MAX_REGISTER,
.reg_defaults = cs42l52_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(cs42l52_reg_defaults),
.readable_reg = cs42l52_readable_register,
.volatile_reg = cs42l52_volatile_register,
.cache_type = REGCACHE_MAPLE,
};
static int cs42l52_i2c_probe(struct i2c_client *i2c_client)
{
struct cs42l52_private *cs42l52;
struct cs42l52_platform_data *pdata = dev_get_platdata(&i2c_client->dev);
int ret;
unsigned int devid;
unsigned int reg;
u32 val32;
cs42l52 = devm_kzalloc(&i2c_client->dev, sizeof(*cs42l52), GFP_KERNEL);
if (cs42l52 == NULL)
return -ENOMEM;
cs42l52->dev = &i2c_client->dev;
cs42l52->regmap = devm_regmap_init_i2c(i2c_client, &cs42l52_regmap);
if (IS_ERR(cs42l52->regmap)) {
ret = PTR_ERR(cs42l52->regmap);
dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
return ret;
}
if (pdata) {
cs42l52->pdata = *pdata;
} else {
pdata = devm_kzalloc(&i2c_client->dev, sizeof(*pdata),
GFP_KERNEL);
if (!pdata)
return -ENOMEM;
if (i2c_client->dev.of_node) {
if (of_property_read_bool(i2c_client->dev.of_node,
"cirrus,mica-differential-cfg"))
pdata->mica_diff_cfg = true;
if (of_property_read_bool(i2c_client->dev.of_node,
"cirrus,micb-differential-cfg"))
pdata->micb_diff_cfg = true;
if (of_property_read_u32(i2c_client->dev.of_node,
"cirrus,micbias-lvl", &val32) >= 0)
pdata->micbias_lvl = val32;
if (of_property_read_u32(i2c_client->dev.of_node,
"cirrus,chgfreq-divisor", &val32) >= 0)
pdata->chgfreq = val32;
pdata->reset_gpio =
of_get_named_gpio(i2c_client->dev.of_node,
"cirrus,reset-gpio", 0);
}
cs42l52->pdata = *pdata;
}
if (cs42l52->pdata.reset_gpio) {
ret = devm_gpio_request_one(&i2c_client->dev,
cs42l52->pdata.reset_gpio,
GPIOF_OUT_INIT_HIGH,
"CS42L52 /RST");
if (ret < 0) {
dev_err(&i2c_client->dev, "Failed to request /RST %d: %d\n",
cs42l52->pdata.reset_gpio, ret);
return ret;
}
gpio_set_value_cansleep(cs42l52->pdata.reset_gpio, 0);
gpio_set_value_cansleep(cs42l52->pdata.reset_gpio, 1);
}
i2c_set_clientdata(i2c_client, cs42l52);
ret = regmap_register_patch(cs42l52->regmap, cs42l52_threshold_patch,
ARRAY_SIZE(cs42l52_threshold_patch));
if (ret != 0)
dev_warn(cs42l52->dev, "Failed to apply regmap patch: %d\n",
ret);
ret = regmap_read(cs42l52->regmap, CS42L52_CHIP, ®);
if (ret) {
dev_err(&i2c_client->dev, "Failed to read chip ID: %d\n", ret);
return ret;
}
devid = reg & CS42L52_CHIP_ID_MASK;
if (devid != CS42L52_CHIP_ID) {
ret = -ENODEV;
dev_err(&i2c_client->dev,
"CS42L52 Device ID (%X). Expected %X\n",
devid, CS42L52_CHIP_ID);
return ret;
}
dev_info(&i2c_client->dev, "Cirrus Logic CS42L52, Revision: %02X\n",
reg & CS42L52_CHIP_REV_MASK);
/* Set Platform Data */
if (cs42l52->pdata.mica_diff_cfg)
regmap_update_bits(cs42l52->regmap, CS42L52_MICA_CTL,
CS42L52_MIC_CTL_TYPE_MASK,
cs42l52->pdata.mica_diff_cfg <<
CS42L52_MIC_CTL_TYPE_SHIFT);
if (cs42l52->pdata.micb_diff_cfg)
regmap_update_bits(cs42l52->regmap, CS42L52_MICB_CTL,
CS42L52_MIC_CTL_TYPE_MASK,
cs42l52->pdata.micb_diff_cfg <<
CS42L52_MIC_CTL_TYPE_SHIFT);
if (cs42l52->pdata.chgfreq)
regmap_update_bits(cs42l52->regmap, CS42L52_CHARGE_PUMP,
CS42L52_CHARGE_PUMP_MASK,
cs42l52->pdata.chgfreq <<
CS42L52_CHARGE_PUMP_SHIFT);
if (cs42l52->pdata.micbias_lvl)
regmap_update_bits(cs42l52->regmap, CS42L52_IFACE_CTL2,
CS42L52_IFACE_CTL2_BIAS_LVL,
cs42l52->pdata.micbias_lvl);
return devm_snd_soc_register_component(&i2c_client->dev,
&soc_component_dev_cs42l52, &cs42l52_dai, 1);
}
static const struct of_device_id cs42l52_of_match[] = {
{ .compatible = "cirrus,cs42l52", },
{},
};
MODULE_DEVICE_TABLE(of, cs42l52_of_match);
static const struct i2c_device_id cs42l52_id[] = {
{ "cs42l52", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, cs42l52_id);
static struct i2c_driver cs42l52_i2c_driver = {
.driver = {
.name = "cs42l52",
.of_match_table = cs42l52_of_match,
},
.id_table = cs42l52_id,
.probe = cs42l52_i2c_probe,
};
module_i2c_driver(cs42l52_i2c_driver);
MODULE_DESCRIPTION("ASoC CS42L52 driver");
MODULE_AUTHOR("Georgi Vlaev, Nucleus Systems Ltd, <[email protected]>");
MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cs42l52.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Load Analog Devices SigmaStudio firmware files
*
* Copyright 2009-2011 Analog Devices Inc.
*/
#include <linux/export.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <asm/unaligned.h>
#include "sigmadsp.h"
static int sigmadsp_write_i2c(void *control_data,
unsigned int addr, const uint8_t data[], size_t len)
{
uint8_t *buf;
int ret;
buf = kzalloc(2 + len, GFP_KERNEL | GFP_DMA);
if (!buf)
return -ENOMEM;
put_unaligned_be16(addr, buf);
memcpy(buf + 2, data, len);
ret = i2c_master_send(control_data, buf, len + 2);
kfree(buf);
if (ret < 0)
return ret;
return 0;
}
static int sigmadsp_read_i2c(void *control_data,
unsigned int addr, uint8_t data[], size_t len)
{
struct i2c_client *client = control_data;
struct i2c_msg msgs[2];
uint8_t buf[2];
int ret;
put_unaligned_be16(addr, buf);
msgs[0].addr = client->addr;
msgs[0].len = sizeof(buf);
msgs[0].buf = buf;
msgs[0].flags = 0;
msgs[1].addr = client->addr;
msgs[1].len = len;
msgs[1].buf = data;
msgs[1].flags = I2C_M_RD;
ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
if (ret < 0)
return ret;
else if (ret != ARRAY_SIZE(msgs))
return -EIO;
return 0;
}
/**
* devm_sigmadsp_init_i2c() - Initialize SigmaDSP instance
* @client: The parent I2C device
* @ops: The sigmadsp_ops to use for this instance
* @firmware_name: Name of the firmware file to load
*
* Allocates a SigmaDSP instance and loads the specified firmware file.
*
* Returns a pointer to a struct sigmadsp on success, or a PTR_ERR() on error.
*/
struct sigmadsp *devm_sigmadsp_init_i2c(struct i2c_client *client,
const struct sigmadsp_ops *ops, const char *firmware_name)
{
struct sigmadsp *sigmadsp;
sigmadsp = devm_sigmadsp_init(&client->dev, ops, firmware_name);
if (IS_ERR(sigmadsp))
return sigmadsp;
sigmadsp->control_data = client;
sigmadsp->write = sigmadsp_write_i2c;
sigmadsp->read = sigmadsp_read_i2c;
return sigmadsp;
}
EXPORT_SYMBOL_GPL(devm_sigmadsp_init_i2c);
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_DESCRIPTION("SigmaDSP I2C firmware loader");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/sigmadsp-i2c.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* max98925.c -- ALSA SoC Stereo MAX98925 driver
* Copyright 2013-15 Maxim Integrated Products
*/
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/cdev.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include "max98925.h"
static const char *const dai_text[] = {
"Left", "Right", "LeftRight", "LeftRightDiv2",
};
static const char * const max98925_boost_voltage_text[] = {
"8.5V", "8.25V", "8.0V", "7.75V", "7.5V", "7.25V", "7.0V", "6.75V",
"6.5V", "6.5V", "6.5V", "6.5V", "6.5V", "6.5V", "6.5V", "6.5V"
};
static SOC_ENUM_SINGLE_DECL(max98925_boost_voltage,
MAX98925_CONFIGURATION, M98925_BST_VOUT_SHIFT,
max98925_boost_voltage_text);
static const char *const hpf_text[] = {
"Disable", "DC Block", "100Hz", "200Hz", "400Hz", "800Hz",
};
static const struct reg_default max98925_reg[] = {
{ 0x0B, 0x00 }, /* IRQ Enable0 */
{ 0x0C, 0x00 }, /* IRQ Enable1 */
{ 0x0D, 0x00 }, /* IRQ Enable2 */
{ 0x0E, 0x00 }, /* IRQ Clear0 */
{ 0x0F, 0x00 }, /* IRQ Clear1 */
{ 0x10, 0x00 }, /* IRQ Clear2 */
{ 0x11, 0xC0 }, /* Map0 */
{ 0x12, 0x00 }, /* Map1 */
{ 0x13, 0x00 }, /* Map2 */
{ 0x14, 0xF0 }, /* Map3 */
{ 0x15, 0x00 }, /* Map4 */
{ 0x16, 0xAB }, /* Map5 */
{ 0x17, 0x89 }, /* Map6 */
{ 0x18, 0x00 }, /* Map7 */
{ 0x19, 0x00 }, /* Map8 */
{ 0x1A, 0x06 }, /* DAI Clock Mode 1 */
{ 0x1B, 0xC0 }, /* DAI Clock Mode 2 */
{ 0x1C, 0x00 }, /* DAI Clock Divider Denominator MSBs */
{ 0x1D, 0x00 }, /* DAI Clock Divider Denominator LSBs */
{ 0x1E, 0xF0 }, /* DAI Clock Divider Numerator MSBs */
{ 0x1F, 0x00 }, /* DAI Clock Divider Numerator LSBs */
{ 0x20, 0x50 }, /* Format */
{ 0x21, 0x00 }, /* TDM Slot Select */
{ 0x22, 0x00 }, /* DOUT Configuration VMON */
{ 0x23, 0x00 }, /* DOUT Configuration IMON */
{ 0x24, 0x00 }, /* DOUT Configuration VBAT */
{ 0x25, 0x00 }, /* DOUT Configuration VBST */
{ 0x26, 0x00 }, /* DOUT Configuration FLAG */
{ 0x27, 0xFF }, /* DOUT HiZ Configuration 1 */
{ 0x28, 0xFF }, /* DOUT HiZ Configuration 2 */
{ 0x29, 0xFF }, /* DOUT HiZ Configuration 3 */
{ 0x2A, 0xFF }, /* DOUT HiZ Configuration 4 */
{ 0x2B, 0x02 }, /* DOUT Drive Strength */
{ 0x2C, 0x90 }, /* Filters */
{ 0x2D, 0x00 }, /* Gain */
{ 0x2E, 0x02 }, /* Gain Ramping */
{ 0x2F, 0x00 }, /* Speaker Amplifier */
{ 0x30, 0x0A }, /* Threshold */
{ 0x31, 0x00 }, /* ALC Attack */
{ 0x32, 0x80 }, /* ALC Atten and Release */
{ 0x33, 0x00 }, /* ALC Infinite Hold Release */
{ 0x34, 0x92 }, /* ALC Configuration */
{ 0x35, 0x01 }, /* Boost Converter */
{ 0x36, 0x00 }, /* Block Enable */
{ 0x37, 0x00 }, /* Configuration */
{ 0x38, 0x00 }, /* Global Enable */
{ 0x3A, 0x00 }, /* Boost Limiter */
};
static const struct soc_enum max98925_dai_enum =
SOC_ENUM_SINGLE(MAX98925_GAIN, 5, ARRAY_SIZE(dai_text), dai_text);
static const struct soc_enum max98925_hpf_enum =
SOC_ENUM_SINGLE(MAX98925_FILTERS, 0, ARRAY_SIZE(hpf_text), hpf_text);
static const struct snd_kcontrol_new max98925_hpf_sel_mux =
SOC_DAPM_ENUM("Rc Filter MUX Mux", max98925_hpf_enum);
static const struct snd_kcontrol_new max98925_dai_sel_mux =
SOC_DAPM_ENUM("DAI IN MUX Mux", max98925_dai_enum);
static int max98925_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct max98925_priv *max98925 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
regmap_update_bits(max98925->regmap,
MAX98925_BLOCK_ENABLE,
M98925_BST_EN_MASK |
M98925_ADC_IMON_EN_MASK | M98925_ADC_VMON_EN_MASK,
M98925_BST_EN_MASK |
M98925_ADC_IMON_EN_MASK | M98925_ADC_VMON_EN_MASK);
break;
case SND_SOC_DAPM_POST_PMD:
regmap_update_bits(max98925->regmap,
MAX98925_BLOCK_ENABLE, M98925_BST_EN_MASK |
M98925_ADC_IMON_EN_MASK | M98925_ADC_VMON_EN_MASK, 0);
break;
default:
return 0;
}
return 0;
}
static const struct snd_soc_dapm_widget max98925_dapm_widgets[] = {
SND_SOC_DAPM_AIF_IN("DAI_OUT", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_MUX("DAI IN MUX", SND_SOC_NOPM, 0, 0,
&max98925_dai_sel_mux),
SND_SOC_DAPM_MUX("Rc Filter MUX", SND_SOC_NOPM, 0, 0,
&max98925_hpf_sel_mux),
SND_SOC_DAPM_DAC_E("Amp Enable", NULL, MAX98925_BLOCK_ENABLE,
M98925_SPK_EN_SHIFT, 0, max98925_dac_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("Global Enable", MAX98925_GLOBAL_ENABLE,
M98925_EN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("BE_OUT"),
};
static const struct snd_soc_dapm_route max98925_audio_map[] = {
{"DAI IN MUX", "Left", "DAI_OUT"},
{"DAI IN MUX", "Right", "DAI_OUT"},
{"DAI IN MUX", "LeftRight", "DAI_OUT"},
{"DAI IN MUX", "LeftRightDiv2", "DAI_OUT"},
{"Rc Filter MUX", "Disable", "DAI IN MUX"},
{"Rc Filter MUX", "DC Block", "DAI IN MUX"},
{"Rc Filter MUX", "100Hz", "DAI IN MUX"},
{"Rc Filter MUX", "200Hz", "DAI IN MUX"},
{"Rc Filter MUX", "400Hz", "DAI IN MUX"},
{"Rc Filter MUX", "800Hz", "DAI IN MUX"},
{"Amp Enable", NULL, "Rc Filter MUX"},
{"BE_OUT", NULL, "Amp Enable"},
{"BE_OUT", NULL, "Global Enable"},
};
static bool max98925_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX98925_VBAT_DATA:
case MAX98925_VBST_DATA:
case MAX98925_LIVE_STATUS0:
case MAX98925_LIVE_STATUS1:
case MAX98925_LIVE_STATUS2:
case MAX98925_STATE0:
case MAX98925_STATE1:
case MAX98925_STATE2:
case MAX98925_FLAG0:
case MAX98925_FLAG1:
case MAX98925_FLAG2:
case MAX98925_REV_VERSION:
return true;
default:
return false;
}
}
static bool max98925_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX98925_IRQ_CLEAR0:
case MAX98925_IRQ_CLEAR1:
case MAX98925_IRQ_CLEAR2:
case MAX98925_ALC_HOLD_RLS:
return false;
default:
return true;
}
}
static DECLARE_TLV_DB_SCALE(max98925_spk_tlv, -600, 100, 0);
static const struct snd_kcontrol_new max98925_snd_controls[] = {
SOC_SINGLE_TLV("Speaker Volume", MAX98925_GAIN,
M98925_SPK_GAIN_SHIFT, (1<<M98925_SPK_GAIN_WIDTH)-1, 0,
max98925_spk_tlv),
SOC_SINGLE("Ramp Switch", MAX98925_GAIN_RAMPING,
M98925_SPK_RMP_EN_SHIFT, 1, 0),
SOC_SINGLE("ZCD Switch", MAX98925_GAIN_RAMPING,
M98925_SPK_ZCD_EN_SHIFT, 1, 0),
SOC_SINGLE("ALC Switch", MAX98925_THRESHOLD,
M98925_ALC_EN_SHIFT, 1, 0),
SOC_SINGLE("ALC Threshold", MAX98925_THRESHOLD, M98925_ALC_TH_SHIFT,
(1<<M98925_ALC_TH_WIDTH)-1, 0),
SOC_ENUM("Boost Output Voltage", max98925_boost_voltage),
};
/* codec sample rate and n/m dividers parameter table */
static const struct {
int rate;
int sr;
int divisors[3][2];
} rate_table[] = {
{
.rate = 8000,
.sr = 0,
.divisors = { {1, 375}, {5, 1764}, {1, 384} }
},
{
.rate = 11025,
.sr = 1,
.divisors = { {147, 40000}, {1, 256}, {147, 40960} }
},
{
.rate = 12000,
.sr = 2,
.divisors = { {1, 250}, {5, 1176}, {1, 256} }
},
{
.rate = 16000,
.sr = 3,
.divisors = { {2, 375}, {5, 882}, {1, 192} }
},
{
.rate = 22050,
.sr = 4,
.divisors = { {147, 20000}, {1, 128}, {147, 20480} }
},
{
.rate = 24000,
.sr = 5,
.divisors = { {1, 125}, {5, 588}, {1, 128} }
},
{
.rate = 32000,
.sr = 6,
.divisors = { {4, 375}, {5, 441}, {1, 96} }
},
{
.rate = 44100,
.sr = 7,
.divisors = { {147, 10000}, {1, 64}, {147, 10240} }
},
{
.rate = 48000,
.sr = 8,
.divisors = { {2, 125}, {5, 294}, {1, 64} }
},
};
static inline int max98925_rate_value(struct snd_soc_component *component,
int rate, int clock, int *value, int *n, int *m)
{
int ret = -EINVAL;
int i;
for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
if (rate_table[i].rate >= rate) {
*value = rate_table[i].sr;
*n = rate_table[i].divisors[clock][0];
*m = rate_table[i].divisors[clock][1];
ret = 0;
break;
}
}
return ret;
}
static void max98925_set_sense_data(struct max98925_priv *max98925)
{
/* set VMON slots */
regmap_update_bits(max98925->regmap,
MAX98925_DOUT_CFG_VMON,
M98925_DAI_VMON_EN_MASK, M98925_DAI_VMON_EN_MASK);
regmap_update_bits(max98925->regmap,
MAX98925_DOUT_CFG_VMON,
M98925_DAI_VMON_SLOT_MASK,
max98925->v_slot << M98925_DAI_VMON_SLOT_SHIFT);
/* set IMON slots */
regmap_update_bits(max98925->regmap,
MAX98925_DOUT_CFG_IMON,
M98925_DAI_IMON_EN_MASK, M98925_DAI_IMON_EN_MASK);
regmap_update_bits(max98925->regmap,
MAX98925_DOUT_CFG_IMON,
M98925_DAI_IMON_SLOT_MASK,
max98925->i_slot << M98925_DAI_IMON_SLOT_SHIFT);
}
static int max98925_dai_set_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct max98925_priv *max98925 = snd_soc_component_get_drvdata(component);
unsigned int invert = 0;
dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt);
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC:
regmap_update_bits(max98925->regmap,
MAX98925_DAI_CLK_MODE2,
M98925_DAI_MAS_MASK, 0);
max98925_set_sense_data(max98925);
break;
case SND_SOC_DAIFMT_CBP_CFP:
/*
* set left channel DAI to provider mode,
* right channel always consumer
*/
regmap_update_bits(max98925->regmap,
MAX98925_DAI_CLK_MODE2,
M98925_DAI_MAS_MASK, M98925_DAI_MAS_MASK);
break;
default:
dev_err(component->dev, "DAI clock mode unsupported");
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_NB_IF:
invert = M98925_DAI_WCI_MASK;
break;
case SND_SOC_DAIFMT_IB_NF:
invert = M98925_DAI_BCI_MASK;
break;
case SND_SOC_DAIFMT_IB_IF:
invert = M98925_DAI_BCI_MASK | M98925_DAI_WCI_MASK;
break;
default:
dev_err(component->dev, "DAI invert mode unsupported");
return -EINVAL;
}
regmap_update_bits(max98925->regmap, MAX98925_FORMAT,
M98925_DAI_BCI_MASK | M98925_DAI_WCI_MASK, invert);
return 0;
}
static int max98925_set_clock(struct max98925_priv *max98925,
struct snd_pcm_hw_params *params)
{
unsigned int dai_sr = 0, clock, mdll, n, m;
struct snd_soc_component *component = max98925->component;
int rate = params_rate(params);
/* BCLK/LRCLK ratio calculation */
int blr_clk_ratio = params_channels(params) * max98925->ch_size;
switch (blr_clk_ratio) {
case 32:
regmap_update_bits(max98925->regmap,
MAX98925_DAI_CLK_MODE2,
M98925_DAI_BSEL_MASK, M98925_DAI_BSEL_32);
break;
case 48:
regmap_update_bits(max98925->regmap,
MAX98925_DAI_CLK_MODE2,
M98925_DAI_BSEL_MASK, M98925_DAI_BSEL_48);
break;
case 64:
regmap_update_bits(max98925->regmap,
MAX98925_DAI_CLK_MODE2,
M98925_DAI_BSEL_MASK, M98925_DAI_BSEL_64);
break;
default:
return -EINVAL;
}
switch (max98925->sysclk) {
case 6000000:
clock = 0;
mdll = M98925_MDLL_MULT_MCLKx16;
break;
case 11289600:
clock = 1;
mdll = M98925_MDLL_MULT_MCLKx8;
break;
case 12000000:
clock = 0;
mdll = M98925_MDLL_MULT_MCLKx8;
break;
case 12288000:
clock = 2;
mdll = M98925_MDLL_MULT_MCLKx8;
break;
default:
dev_info(max98925->component->dev, "unsupported sysclk %d\n",
max98925->sysclk);
return -EINVAL;
}
if (max98925_rate_value(component, rate, clock, &dai_sr, &n, &m))
return -EINVAL;
/* set DAI_SR to correct LRCLK frequency */
regmap_update_bits(max98925->regmap,
MAX98925_DAI_CLK_MODE2,
M98925_DAI_SR_MASK, dai_sr << M98925_DAI_SR_SHIFT);
/* set DAI m divider */
regmap_write(max98925->regmap,
MAX98925_DAI_CLK_DIV_M_MSBS, m >> 8);
regmap_write(max98925->regmap,
MAX98925_DAI_CLK_DIV_M_LSBS, m & 0xFF);
/* set DAI n divider */
regmap_write(max98925->regmap,
MAX98925_DAI_CLK_DIV_N_MSBS, n >> 8);
regmap_write(max98925->regmap,
MAX98925_DAI_CLK_DIV_N_LSBS, n & 0xFF);
/* set MDLL */
regmap_update_bits(max98925->regmap, MAX98925_DAI_CLK_MODE1,
M98925_MDLL_MULT_MASK, mdll << M98925_MDLL_MULT_SHIFT);
return 0;
}
static int max98925_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct max98925_priv *max98925 = snd_soc_component_get_drvdata(component);
switch (params_width(params)) {
case 16:
regmap_update_bits(max98925->regmap,
MAX98925_FORMAT,
M98925_DAI_CHANSZ_MASK, M98925_DAI_CHANSZ_16);
max98925->ch_size = 16;
break;
case 24:
regmap_update_bits(max98925->regmap,
MAX98925_FORMAT,
M98925_DAI_CHANSZ_MASK, M98925_DAI_CHANSZ_24);
max98925->ch_size = 24;
break;
case 32:
regmap_update_bits(max98925->regmap,
MAX98925_FORMAT,
M98925_DAI_CHANSZ_MASK, M98925_DAI_CHANSZ_32);
max98925->ch_size = 32;
break;
default:
pr_err("%s: format unsupported %d",
__func__, params_format(params));
return -EINVAL;
}
dev_dbg(component->dev, "%s: format supported %d",
__func__, params_format(params));
return max98925_set_clock(max98925, params);
}
static int max98925_dai_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct max98925_priv *max98925 = snd_soc_component_get_drvdata(component);
switch (clk_id) {
case 0:
/* use MCLK for Left channel, right channel always BCLK */
regmap_update_bits(max98925->regmap,
MAX98925_DAI_CLK_MODE1,
M98925_DAI_CLK_SOURCE_MASK, 0);
break;
case 1:
/* configure dai clock source to BCLK instead of MCLK */
regmap_update_bits(max98925->regmap,
MAX98925_DAI_CLK_MODE1,
M98925_DAI_CLK_SOURCE_MASK,
M98925_DAI_CLK_SOURCE_MASK);
break;
default:
return -EINVAL;
}
max98925->sysclk = freq;
return 0;
}
#define MAX98925_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops max98925_dai_ops = {
.set_sysclk = max98925_dai_set_sysclk,
.set_fmt = max98925_dai_set_fmt,
.hw_params = max98925_dai_hw_params,
};
static struct snd_soc_dai_driver max98925_dai[] = {
{
.name = "max98925-aif1",
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = MAX98925_FORMATS,
},
.capture = {
.stream_name = "HiFi Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = MAX98925_FORMATS,
},
.ops = &max98925_dai_ops,
}
};
static int max98925_probe(struct snd_soc_component *component)
{
struct max98925_priv *max98925 = snd_soc_component_get_drvdata(component);
max98925->component = component;
regmap_write(max98925->regmap, MAX98925_GLOBAL_ENABLE, 0x00);
/* It's not the default but we need to set DAI_DLY */
regmap_write(max98925->regmap,
MAX98925_FORMAT, M98925_DAI_DLY_MASK);
regmap_write(max98925->regmap, MAX98925_TDM_SLOT_SELECT, 0xC8);
regmap_write(max98925->regmap, MAX98925_DOUT_HIZ_CFG1, 0xFF);
regmap_write(max98925->regmap, MAX98925_DOUT_HIZ_CFG2, 0xFF);
regmap_write(max98925->regmap, MAX98925_DOUT_HIZ_CFG3, 0xFF);
regmap_write(max98925->regmap, MAX98925_DOUT_HIZ_CFG4, 0xF0);
regmap_write(max98925->regmap, MAX98925_FILTERS, 0xD8);
regmap_write(max98925->regmap, MAX98925_ALC_CONFIGURATION, 0xF8);
regmap_write(max98925->regmap, MAX98925_CONFIGURATION, 0xF0);
/* Disable ALC muting */
regmap_write(max98925->regmap, MAX98925_BOOST_LIMITER, 0xF8);
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_max98925 = {
.probe = max98925_probe,
.controls = max98925_snd_controls,
.num_controls = ARRAY_SIZE(max98925_snd_controls),
.dapm_routes = max98925_audio_map,
.num_dapm_routes = ARRAY_SIZE(max98925_audio_map),
.dapm_widgets = max98925_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(max98925_dapm_widgets),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config max98925_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = MAX98925_REV_VERSION,
.reg_defaults = max98925_reg,
.num_reg_defaults = ARRAY_SIZE(max98925_reg),
.volatile_reg = max98925_volatile_register,
.readable_reg = max98925_readable_register,
.cache_type = REGCACHE_RBTREE,
};
static int max98925_i2c_probe(struct i2c_client *i2c)
{
int ret, reg;
u32 value;
struct max98925_priv *max98925;
max98925 = devm_kzalloc(&i2c->dev,
sizeof(*max98925), GFP_KERNEL);
if (!max98925)
return -ENOMEM;
i2c_set_clientdata(i2c, max98925);
max98925->regmap = devm_regmap_init_i2c(i2c, &max98925_regmap);
if (IS_ERR(max98925->regmap)) {
ret = PTR_ERR(max98925->regmap);
dev_err(&i2c->dev,
"Failed to allocate regmap: %d\n", ret);
return ret;
}
if (!of_property_read_u32(i2c->dev.of_node, "vmon-slot-no", &value)) {
if (value > M98925_DAI_VMON_SLOT_1E_1F) {
dev_err(&i2c->dev, "vmon slot number is wrong:\n");
return -EINVAL;
}
max98925->v_slot = value;
}
if (!of_property_read_u32(i2c->dev.of_node, "imon-slot-no", &value)) {
if (value > M98925_DAI_IMON_SLOT_1E_1F) {
dev_err(&i2c->dev, "imon slot number is wrong:\n");
return -EINVAL;
}
max98925->i_slot = value;
}
ret = regmap_read(max98925->regmap, MAX98925_REV_VERSION, ®);
if (ret < 0) {
dev_err(&i2c->dev, "Read revision failed\n");
return ret;
}
if ((reg != MAX98925_VERSION) && (reg != MAX98925_VERSION1)) {
ret = -ENODEV;
dev_err(&i2c->dev, "Invalid revision (%d 0x%02X)\n",
ret, reg);
return ret;
}
dev_info(&i2c->dev, "device version 0x%02X\n", reg);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_max98925,
max98925_dai, ARRAY_SIZE(max98925_dai));
if (ret < 0)
dev_err(&i2c->dev,
"Failed to register component: %d\n", ret);
return ret;
}
static const struct i2c_device_id max98925_i2c_id[] = {
{ "max98925", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, max98925_i2c_id);
#ifdef CONFIG_OF
static const struct of_device_id max98925_of_match[] = {
{ .compatible = "maxim,max98925", },
{ }
};
MODULE_DEVICE_TABLE(of, max98925_of_match);
#endif
static struct i2c_driver max98925_i2c_driver = {
.driver = {
.name = "max98925",
.of_match_table = of_match_ptr(max98925_of_match),
},
.probe = max98925_i2c_probe,
.id_table = max98925_i2c_id,
};
module_i2c_driver(max98925_i2c_driver)
MODULE_DESCRIPTION("ALSA SoC MAX98925 driver");
MODULE_AUTHOR("Ralph Birt <[email protected]>, Anish kumar <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/max98925.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Driver for Cirrus Logic CS35L56 smart amp
//
// Copyright (C) 2023 Cirrus Logic, Inc. and
// Cirrus Logic International Semiconductor Ltd.
#include <linux/completion.h>
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/gpio/consumer.h>
#include <linux/interrupt.h>
#include <linux/math.h>
#include <linux/module.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <linux/soundwire/sdw.h>
#include <linux/types.h>
#include <linux/workqueue.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/tlv.h>
#include "wm_adsp.h"
#include "cs35l56.h"
static int cs35l56_dsp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event);
static void cs35l56_wait_dsp_ready(struct cs35l56_private *cs35l56)
{
/* Wait for patching to complete */
flush_work(&cs35l56->dsp_work);
}
static int cs35l56_dspwait_get_volsw(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component);
cs35l56_wait_dsp_ready(cs35l56);
return snd_soc_get_volsw(kcontrol, ucontrol);
}
static int cs35l56_dspwait_put_volsw(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component);
cs35l56_wait_dsp_ready(cs35l56);
return snd_soc_put_volsw(kcontrol, ucontrol);
}
static DECLARE_TLV_DB_SCALE(vol_tlv, -10000, 25, 0);
static const struct snd_kcontrol_new cs35l56_controls[] = {
SOC_SINGLE_EXT("Speaker Switch",
CS35L56_MAIN_RENDER_USER_MUTE, 0, 1, 1,
cs35l56_dspwait_get_volsw, cs35l56_dspwait_put_volsw),
SOC_SINGLE_S_EXT_TLV("Speaker Volume",
CS35L56_MAIN_RENDER_USER_VOLUME,
6, -400, 400, 9, 0,
cs35l56_dspwait_get_volsw,
cs35l56_dspwait_put_volsw,
vol_tlv),
SOC_SINGLE_EXT("Posture Number", CS35L56_MAIN_POSTURE_NUMBER,
0, 255, 0,
cs35l56_dspwait_get_volsw, cs35l56_dspwait_put_volsw),
};
static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_asp1tx1_enum,
CS35L56_ASP1TX1_INPUT,
0, CS35L56_ASP_TXn_SRC_MASK,
cs35l56_tx_input_texts,
cs35l56_tx_input_values);
static const struct snd_kcontrol_new asp1_tx1_mux =
SOC_DAPM_ENUM("ASP1TX1 SRC", cs35l56_asp1tx1_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_asp1tx2_enum,
CS35L56_ASP1TX2_INPUT,
0, CS35L56_ASP_TXn_SRC_MASK,
cs35l56_tx_input_texts,
cs35l56_tx_input_values);
static const struct snd_kcontrol_new asp1_tx2_mux =
SOC_DAPM_ENUM("ASP1TX2 SRC", cs35l56_asp1tx2_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_asp1tx3_enum,
CS35L56_ASP1TX3_INPUT,
0, CS35L56_ASP_TXn_SRC_MASK,
cs35l56_tx_input_texts,
cs35l56_tx_input_values);
static const struct snd_kcontrol_new asp1_tx3_mux =
SOC_DAPM_ENUM("ASP1TX3 SRC", cs35l56_asp1tx3_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_asp1tx4_enum,
CS35L56_ASP1TX4_INPUT,
0, CS35L56_ASP_TXn_SRC_MASK,
cs35l56_tx_input_texts,
cs35l56_tx_input_values);
static const struct snd_kcontrol_new asp1_tx4_mux =
SOC_DAPM_ENUM("ASP1TX4 SRC", cs35l56_asp1tx4_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_sdw1tx1_enum,
CS35L56_SWIRE_DP3_CH1_INPUT,
0, CS35L56_SWIRETXn_SRC_MASK,
cs35l56_tx_input_texts,
cs35l56_tx_input_values);
static const struct snd_kcontrol_new sdw1_tx1_mux =
SOC_DAPM_ENUM("SDW1TX1 SRC", cs35l56_sdw1tx1_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_sdw1tx2_enum,
CS35L56_SWIRE_DP3_CH2_INPUT,
0, CS35L56_SWIRETXn_SRC_MASK,
cs35l56_tx_input_texts,
cs35l56_tx_input_values);
static const struct snd_kcontrol_new sdw1_tx2_mux =
SOC_DAPM_ENUM("SDW1TX2 SRC", cs35l56_sdw1tx2_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_sdw1tx3_enum,
CS35L56_SWIRE_DP3_CH3_INPUT,
0, CS35L56_SWIRETXn_SRC_MASK,
cs35l56_tx_input_texts,
cs35l56_tx_input_values);
static const struct snd_kcontrol_new sdw1_tx3_mux =
SOC_DAPM_ENUM("SDW1TX3 SRC", cs35l56_sdw1tx3_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_sdw1tx4_enum,
CS35L56_SWIRE_DP3_CH4_INPUT,
0, CS35L56_SWIRETXn_SRC_MASK,
cs35l56_tx_input_texts,
cs35l56_tx_input_values);
static const struct snd_kcontrol_new sdw1_tx4_mux =
SOC_DAPM_ENUM("SDW1TX4 SRC", cs35l56_sdw1tx4_enum);
static int cs35l56_play_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component);
unsigned int val;
int ret;
dev_dbg(cs35l56->base.dev, "play: %d\n", event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* Don't wait for ACK, we check in POST_PMU that it completed */
return regmap_write(cs35l56->base.regmap, CS35L56_DSP_VIRTUAL1_MBOX_1,
CS35L56_MBOX_CMD_AUDIO_PLAY);
case SND_SOC_DAPM_POST_PMU:
/* Wait for firmware to enter PS0 power state */
ret = regmap_read_poll_timeout(cs35l56->base.regmap,
CS35L56_TRANSDUCER_ACTUAL_PS,
val, (val == CS35L56_PS0),
CS35L56_PS0_POLL_US,
CS35L56_PS0_TIMEOUT_US);
if (ret)
dev_err(cs35l56->base.dev, "PS0 wait failed: %d\n", ret);
return ret;
case SND_SOC_DAPM_POST_PMD:
return cs35l56_mbox_send(&cs35l56->base, CS35L56_MBOX_CMD_AUDIO_PAUSE);
default:
return 0;
}
}
static const struct snd_soc_dapm_widget cs35l56_dapm_widgets[] = {
SND_SOC_DAPM_REGULATOR_SUPPLY("VDD_B", 0, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("VDD_AMP", 0, 0),
SND_SOC_DAPM_SUPPLY("PLAY", SND_SOC_NOPM, 0, 0, cs35l56_play_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_OUT_DRV("AMP", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("SPK"),
SND_SOC_DAPM_PGA_E("DSP1", SND_SOC_NOPM, 0, 0, NULL, 0, cs35l56_dsp_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_AIF_IN("ASP1RX1", NULL, 0, CS35L56_ASP1_ENABLES1,
CS35L56_ASP_RX1_EN_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("ASP1RX2", NULL, 1, CS35L56_ASP1_ENABLES1,
CS35L56_ASP_RX2_EN_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("ASP1TX1", NULL, 0, CS35L56_ASP1_ENABLES1,
CS35L56_ASP_TX1_EN_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("ASP1TX2", NULL, 1, CS35L56_ASP1_ENABLES1,
CS35L56_ASP_TX2_EN_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("ASP1TX3", NULL, 2, CS35L56_ASP1_ENABLES1,
CS35L56_ASP_TX3_EN_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("ASP1TX4", NULL, 3, CS35L56_ASP1_ENABLES1,
CS35L56_ASP_TX4_EN_SHIFT, 0),
SND_SOC_DAPM_MUX("ASP1 TX1 Source", SND_SOC_NOPM, 0, 0, &asp1_tx1_mux),
SND_SOC_DAPM_MUX("ASP1 TX2 Source", SND_SOC_NOPM, 0, 0, &asp1_tx2_mux),
SND_SOC_DAPM_MUX("ASP1 TX3 Source", SND_SOC_NOPM, 0, 0, &asp1_tx3_mux),
SND_SOC_DAPM_MUX("ASP1 TX4 Source", SND_SOC_NOPM, 0, 0, &asp1_tx4_mux),
SND_SOC_DAPM_MUX("SDW1 TX1 Source", SND_SOC_NOPM, 0, 0, &sdw1_tx1_mux),
SND_SOC_DAPM_MUX("SDW1 TX2 Source", SND_SOC_NOPM, 0, 0, &sdw1_tx2_mux),
SND_SOC_DAPM_MUX("SDW1 TX3 Source", SND_SOC_NOPM, 0, 0, &sdw1_tx3_mux),
SND_SOC_DAPM_MUX("SDW1 TX4 Source", SND_SOC_NOPM, 0, 0, &sdw1_tx4_mux),
SND_SOC_DAPM_SIGGEN("VMON ADC"),
SND_SOC_DAPM_SIGGEN("IMON ADC"),
SND_SOC_DAPM_SIGGEN("ERRVOL ADC"),
SND_SOC_DAPM_SIGGEN("CLASSH ADC"),
SND_SOC_DAPM_SIGGEN("VDDBMON ADC"),
SND_SOC_DAPM_SIGGEN("VBSTMON ADC"),
SND_SOC_DAPM_SIGGEN("TEMPMON ADC"),
};
#define CS35L56_SRC_ROUTE(name) \
{ name" Source", "ASP1RX1", "ASP1RX1" }, \
{ name" Source", "ASP1RX2", "ASP1RX2" }, \
{ name" Source", "VMON", "VMON ADC" }, \
{ name" Source", "IMON", "IMON ADC" }, \
{ name" Source", "ERRVOL", "ERRVOL ADC" }, \
{ name" Source", "CLASSH", "CLASSH ADC" }, \
{ name" Source", "VDDBMON", "VDDBMON ADC" }, \
{ name" Source", "VBSTMON", "VBSTMON ADC" }, \
{ name" Source", "DSP1TX1", "DSP1" }, \
{ name" Source", "DSP1TX2", "DSP1" }, \
{ name" Source", "DSP1TX3", "DSP1" }, \
{ name" Source", "DSP1TX4", "DSP1" }, \
{ name" Source", "DSP1TX5", "DSP1" }, \
{ name" Source", "DSP1TX6", "DSP1" }, \
{ name" Source", "DSP1TX7", "DSP1" }, \
{ name" Source", "DSP1TX8", "DSP1" }, \
{ name" Source", "TEMPMON", "TEMPMON ADC" }, \
{ name" Source", "INTERPOLATOR", "AMP" }, \
{ name" Source", "SDW1RX1", "SDW1 Playback" }, \
{ name" Source", "SDW1RX2", "SDW1 Playback" },
static const struct snd_soc_dapm_route cs35l56_audio_map[] = {
{ "AMP", NULL, "VDD_B" },
{ "AMP", NULL, "VDD_AMP" },
{ "ASP1 Playback", NULL, "PLAY" },
{ "SDW1 Playback", NULL, "PLAY" },
{ "ASP1RX1", NULL, "ASP1 Playback" },
{ "ASP1RX2", NULL, "ASP1 Playback" },
{ "DSP1", NULL, "ASP1RX1" },
{ "DSP1", NULL, "ASP1RX2" },
{ "DSP1", NULL, "SDW1 Playback" },
{ "AMP", NULL, "DSP1" },
{ "SPK", NULL, "AMP" },
CS35L56_SRC_ROUTE("ASP1 TX1")
CS35L56_SRC_ROUTE("ASP1 TX2")
CS35L56_SRC_ROUTE("ASP1 TX3")
CS35L56_SRC_ROUTE("ASP1 TX4")
{ "ASP1TX1", NULL, "ASP1 TX1 Source" },
{ "ASP1TX2", NULL, "ASP1 TX2 Source" },
{ "ASP1TX3", NULL, "ASP1 TX3 Source" },
{ "ASP1TX4", NULL, "ASP1 TX4 Source" },
{ "ASP1 Capture", NULL, "ASP1TX1" },
{ "ASP1 Capture", NULL, "ASP1TX2" },
{ "ASP1 Capture", NULL, "ASP1TX3" },
{ "ASP1 Capture", NULL, "ASP1TX4" },
CS35L56_SRC_ROUTE("SDW1 TX1")
CS35L56_SRC_ROUTE("SDW1 TX2")
CS35L56_SRC_ROUTE("SDW1 TX3")
CS35L56_SRC_ROUTE("SDW1 TX4")
{ "SDW1 Capture", NULL, "SDW1 TX1 Source" },
{ "SDW1 Capture", NULL, "SDW1 TX2 Source" },
{ "SDW1 Capture", NULL, "SDW1 TX3 Source" },
{ "SDW1 Capture", NULL, "SDW1 TX4 Source" },
};
static int cs35l56_dsp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component);
dev_dbg(cs35l56->base.dev, "%s: %d\n", __func__, event);
return wm_adsp_event(w, kcontrol, event);
}
static int cs35l56_asp_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(codec_dai->component);
unsigned int val;
dev_dbg(cs35l56->base.dev, "%s: %#x\n", __func__, fmt);
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC:
break;
default:
dev_err(cs35l56->base.dev, "Unsupported clock source mode\n");
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
val = CS35L56_ASP_FMT_DSP_A << CS35L56_ASP_FMT_SHIFT;
cs35l56->tdm_mode = true;
break;
case SND_SOC_DAIFMT_I2S:
val = CS35L56_ASP_FMT_I2S << CS35L56_ASP_FMT_SHIFT;
cs35l56->tdm_mode = false;
break;
default:
dev_err(cs35l56->base.dev, "Unsupported DAI format\n");
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_IF:
val |= CS35L56_ASP_FSYNC_INV_MASK;
break;
case SND_SOC_DAIFMT_IB_NF:
val |= CS35L56_ASP_BCLK_INV_MASK;
break;
case SND_SOC_DAIFMT_IB_IF:
val |= CS35L56_ASP_BCLK_INV_MASK | CS35L56_ASP_FSYNC_INV_MASK;
break;
case SND_SOC_DAIFMT_NB_NF:
break;
default:
dev_err(cs35l56->base.dev, "Invalid clock invert\n");
return -EINVAL;
}
regmap_update_bits(cs35l56->base.regmap,
CS35L56_ASP1_CONTROL2,
CS35L56_ASP_FMT_MASK |
CS35L56_ASP_BCLK_INV_MASK | CS35L56_ASP_FSYNC_INV_MASK,
val);
/* Hi-Z DOUT in unused slots and when all TX are disabled */
regmap_update_bits(cs35l56->base.regmap, CS35L56_ASP1_CONTROL3,
CS35L56_ASP1_DOUT_HIZ_CTRL_MASK,
CS35L56_ASP_UNUSED_HIZ_OFF_HIZ);
return 0;
}
static unsigned int cs35l56_make_tdm_config_word(unsigned int reg_val, unsigned long mask)
{
unsigned int channel_shift;
int bit_num;
/* Enable consecutive TX1..TXn for each of the slots set in mask */
channel_shift = 0;
for_each_set_bit(bit_num, &mask, 32) {
reg_val &= ~(0x3f << channel_shift);
reg_val |= bit_num << channel_shift;
channel_shift += 8;
}
return reg_val;
}
static int cs35l56_asp_dai_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int slot_width)
{
struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component);
if ((slots == 0) || (slot_width == 0)) {
dev_dbg(cs35l56->base.dev, "tdm config cleared\n");
cs35l56->asp_slot_width = 0;
cs35l56->asp_slot_count = 0;
return 0;
}
if (slot_width > (CS35L56_ASP_RX_WIDTH_MASK >> CS35L56_ASP_RX_WIDTH_SHIFT)) {
dev_err(cs35l56->base.dev, "tdm invalid slot width %d\n", slot_width);
return -EINVAL;
}
/* More than 32 slots would give an unsupportable BCLK frequency */
if (slots > 32) {
dev_err(cs35l56->base.dev, "tdm invalid slot count %d\n", slots);
return -EINVAL;
}
cs35l56->asp_slot_width = (u8)slot_width;
cs35l56->asp_slot_count = (u8)slots;
// Note: rx/tx is from point of view of the CPU end
if (tx_mask == 0)
tx_mask = 0x3; // ASPRX1/RX2 in slots 0 and 1
if (rx_mask == 0)
rx_mask = 0xf; // ASPTX1..TX4 in slots 0..3
/* Default unused slots to 63 */
regmap_write(cs35l56->base.regmap, CS35L56_ASP1_FRAME_CONTROL1,
cs35l56_make_tdm_config_word(0x3f3f3f3f, rx_mask));
regmap_write(cs35l56->base.regmap, CS35L56_ASP1_FRAME_CONTROL5,
cs35l56_make_tdm_config_word(0x3f3f3f, tx_mask));
dev_dbg(cs35l56->base.dev, "tdm slot width: %u count: %u tx_mask: %#x rx_mask: %#x\n",
cs35l56->asp_slot_width, cs35l56->asp_slot_count, tx_mask, rx_mask);
return 0;
}
static int cs35l56_asp_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component);
unsigned int rate = params_rate(params);
u8 asp_width, asp_wl;
asp_wl = params_width(params);
if (cs35l56->asp_slot_width)
asp_width = cs35l56->asp_slot_width;
else
asp_width = asp_wl;
dev_dbg(cs35l56->base.dev, "%s: wl=%d, width=%d, rate=%d",
__func__, asp_wl, asp_width, rate);
if (!cs35l56->sysclk_set) {
unsigned int slots = cs35l56->asp_slot_count;
unsigned int bclk_freq;
int freq_id;
if (slots == 0) {
slots = params_channels(params);
/* I2S always has an even number of slots */
if (!cs35l56->tdm_mode)
slots = round_up(slots, 2);
}
bclk_freq = asp_width * slots * rate;
freq_id = cs35l56_get_bclk_freq_id(bclk_freq);
if (freq_id < 0) {
dev_err(cs35l56->base.dev, "%s: Invalid BCLK %u\n", __func__, bclk_freq);
return -EINVAL;
}
regmap_update_bits(cs35l56->base.regmap, CS35L56_ASP1_CONTROL1,
CS35L56_ASP_BCLK_FREQ_MASK,
freq_id << CS35L56_ASP_BCLK_FREQ_SHIFT);
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
regmap_update_bits(cs35l56->base.regmap, CS35L56_ASP1_CONTROL2,
CS35L56_ASP_RX_WIDTH_MASK, asp_width <<
CS35L56_ASP_RX_WIDTH_SHIFT);
regmap_update_bits(cs35l56->base.regmap, CS35L56_ASP1_DATA_CONTROL5,
CS35L56_ASP_RX_WL_MASK, asp_wl);
} else {
regmap_update_bits(cs35l56->base.regmap, CS35L56_ASP1_CONTROL2,
CS35L56_ASP_TX_WIDTH_MASK, asp_width <<
CS35L56_ASP_TX_WIDTH_SHIFT);
regmap_update_bits(cs35l56->base.regmap, CS35L56_ASP1_DATA_CONTROL1,
CS35L56_ASP_TX_WL_MASK, asp_wl);
}
return 0;
}
static int cs35l56_asp_dai_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component);
int freq_id;
if (freq == 0) {
cs35l56->sysclk_set = false;
return 0;
}
freq_id = cs35l56_get_bclk_freq_id(freq);
if (freq_id < 0)
return freq_id;
regmap_update_bits(cs35l56->base.regmap, CS35L56_ASP1_CONTROL1,
CS35L56_ASP_BCLK_FREQ_MASK,
freq_id << CS35L56_ASP_BCLK_FREQ_SHIFT);
cs35l56->sysclk_set = true;
return 0;
}
static const struct snd_soc_dai_ops cs35l56_ops = {
.set_fmt = cs35l56_asp_dai_set_fmt,
.set_tdm_slot = cs35l56_asp_dai_set_tdm_slot,
.hw_params = cs35l56_asp_dai_hw_params,
.set_sysclk = cs35l56_asp_dai_set_sysclk,
};
static void cs35l56_sdw_dai_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
snd_soc_dai_set_dma_data(dai, substream, NULL);
}
static int cs35l56_sdw_dai_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int slot_width)
{
struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component);
/* rx/tx are from point of view of the CPU end so opposite to our rx/tx */
cs35l56->rx_mask = tx_mask;
cs35l56->tx_mask = rx_mask;
return 0;
}
static int cs35l56_sdw_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component);
struct sdw_stream_runtime *sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
struct sdw_stream_config sconfig;
struct sdw_port_config pconfig;
int ret;
dev_dbg(cs35l56->base.dev, "%s: rate %d\n", __func__, params_rate(params));
if (!cs35l56->base.init_done)
return -ENODEV;
if (!sdw_stream)
return -EINVAL;
memset(&sconfig, 0, sizeof(sconfig));
memset(&pconfig, 0, sizeof(pconfig));
sconfig.frame_rate = params_rate(params);
sconfig.bps = snd_pcm_format_width(params_format(params));
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
sconfig.direction = SDW_DATA_DIR_RX;
pconfig.num = CS35L56_SDW1_PLAYBACK_PORT;
pconfig.ch_mask = cs35l56->rx_mask;
} else {
sconfig.direction = SDW_DATA_DIR_TX;
pconfig.num = CS35L56_SDW1_CAPTURE_PORT;
pconfig.ch_mask = cs35l56->tx_mask;
}
if (pconfig.ch_mask == 0) {
sconfig.ch_count = params_channels(params);
pconfig.ch_mask = GENMASK(sconfig.ch_count - 1, 0);
} else {
sconfig.ch_count = hweight32(pconfig.ch_mask);
}
ret = sdw_stream_add_slave(cs35l56->sdw_peripheral, &sconfig, &pconfig,
1, sdw_stream);
if (ret) {
dev_err(dai->dev, "Failed to add sdw stream: %d\n", ret);
return ret;
}
return 0;
}
static int cs35l56_sdw_dai_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component);
struct sdw_stream_runtime *sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
if (!cs35l56->sdw_peripheral)
return -EINVAL;
sdw_stream_remove_slave(cs35l56->sdw_peripheral, sdw_stream);
return 0;
}
static int cs35l56_sdw_dai_set_stream(struct snd_soc_dai *dai,
void *sdw_stream, int direction)
{
snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
return 0;
}
static const struct snd_soc_dai_ops cs35l56_sdw_dai_ops = {
.set_tdm_slot = cs35l56_sdw_dai_set_tdm_slot,
.shutdown = cs35l56_sdw_dai_shutdown,
.hw_params = cs35l56_sdw_dai_hw_params,
.hw_free = cs35l56_sdw_dai_hw_free,
.set_stream = cs35l56_sdw_dai_set_stream,
};
static struct snd_soc_dai_driver cs35l56_dai[] = {
{
.name = "cs35l56-asp1",
.id = 0,
.playback = {
.stream_name = "ASP1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = CS35L56_RATES,
.formats = CS35L56_RX_FORMATS,
},
.capture = {
.stream_name = "ASP1 Capture",
.channels_min = 1,
.channels_max = 4,
.rates = CS35L56_RATES,
.formats = CS35L56_TX_FORMATS,
},
.ops = &cs35l56_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
{
.name = "cs35l56-sdw1",
.id = 1,
.playback = {
.stream_name = "SDW1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = CS35L56_RATES,
.formats = CS35L56_RX_FORMATS,
},
.capture = {
.stream_name = "SDW1 Capture",
.channels_min = 1,
.channels_max = 4,
.rates = CS35L56_RATES,
.formats = CS35L56_TX_FORMATS,
},
.symmetric_rate = 1,
.ops = &cs35l56_sdw_dai_ops,
}
};
static void cs35l56_secure_patch(struct cs35l56_private *cs35l56)
{
int ret;
/* Use wm_adsp to load and apply the firmware patch and coefficient files */
ret = wm_adsp_power_up(&cs35l56->dsp, true);
if (ret)
dev_dbg(cs35l56->base.dev, "%s: wm_adsp_power_up ret %d\n", __func__, ret);
else
cs35l56_mbox_send(&cs35l56->base, CS35L56_MBOX_CMD_AUDIO_REINIT);
}
static void cs35l56_patch(struct cs35l56_private *cs35l56)
{
unsigned int firmware_missing;
int ret;
ret = regmap_read(cs35l56->base.regmap, CS35L56_PROTECTION_STATUS, &firmware_missing);
if (ret) {
dev_err(cs35l56->base.dev, "Failed to read PROTECTION_STATUS: %d\n", ret);
return;
}
firmware_missing &= CS35L56_FIRMWARE_MISSING;
/*
* Disable SoundWire interrupts to prevent race with IRQ work.
* Setting sdw_irq_no_unmask prevents the handler re-enabling
* the SoundWire interrupt.
*/
if (cs35l56->sdw_peripheral) {
cs35l56->sdw_irq_no_unmask = true;
flush_work(&cs35l56->sdw_irq_work);
sdw_write_no_pm(cs35l56->sdw_peripheral, CS35L56_SDW_GEN_INT_MASK_1, 0);
sdw_read_no_pm(cs35l56->sdw_peripheral, CS35L56_SDW_GEN_INT_STAT_1);
sdw_write_no_pm(cs35l56->sdw_peripheral, CS35L56_SDW_GEN_INT_STAT_1, 0xFF);
flush_work(&cs35l56->sdw_irq_work);
}
ret = cs35l56_firmware_shutdown(&cs35l56->base);
if (ret)
goto err;
/*
* Use wm_adsp to load and apply the firmware patch and coefficient files,
* but only if firmware is missing. If firmware is already patched just
* power-up wm_adsp without downloading firmware.
*/
ret = wm_adsp_power_up(&cs35l56->dsp, !!firmware_missing);
if (ret) {
dev_dbg(cs35l56->base.dev, "%s: wm_adsp_power_up ret %d\n", __func__, ret);
goto err;
}
mutex_lock(&cs35l56->base.irq_lock);
init_completion(&cs35l56->init_completion);
cs35l56->soft_resetting = true;
cs35l56_system_reset(&cs35l56->base, !!cs35l56->sdw_peripheral);
if (cs35l56->sdw_peripheral) {
/*
* The system-reset causes the CS35L56 to detach from the bus.
* Wait for the manager to re-enumerate the CS35L56 and
* cs35l56_init() to run again.
*/
if (!wait_for_completion_timeout(&cs35l56->init_completion,
msecs_to_jiffies(5000))) {
dev_err(cs35l56->base.dev, "%s: init_completion timed out (SDW)\n",
__func__);
goto err_unlock;
}
} else if (cs35l56_init(cs35l56)) {
goto err_unlock;
}
regmap_clear_bits(cs35l56->base.regmap, CS35L56_PROTECTION_STATUS,
CS35L56_FIRMWARE_MISSING);
cs35l56->base.fw_patched = true;
err_unlock:
mutex_unlock(&cs35l56->base.irq_lock);
err:
/* Re-enable SoundWire interrupts */
if (cs35l56->sdw_peripheral) {
cs35l56->sdw_irq_no_unmask = false;
sdw_write_no_pm(cs35l56->sdw_peripheral, CS35L56_SDW_GEN_INT_MASK_1,
CS35L56_SDW_INT_MASK_CODEC_IRQ);
}
}
static void cs35l56_dsp_work(struct work_struct *work)
{
struct cs35l56_private *cs35l56 = container_of(work,
struct cs35l56_private,
dsp_work);
if (!cs35l56->base.init_done)
return;
pm_runtime_get_sync(cs35l56->base.dev);
/*
* When the device is running in secure mode the firmware files can
* only contain insecure tunings and therefore we do not need to
* shutdown the firmware to apply them and can use the lower cost
* reinit sequence instead.
*/
if (cs35l56->base.secured)
cs35l56_secure_patch(cs35l56);
else
cs35l56_patch(cs35l56);
pm_runtime_mark_last_busy(cs35l56->base.dev);
pm_runtime_put_autosuspend(cs35l56->base.dev);
}
static int cs35l56_component_probe(struct snd_soc_component *component)
{
struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component);
struct dentry *debugfs_root = component->debugfs_root;
BUILD_BUG_ON(ARRAY_SIZE(cs35l56_tx_input_texts) != ARRAY_SIZE(cs35l56_tx_input_values));
if (!wait_for_completion_timeout(&cs35l56->init_completion,
msecs_to_jiffies(5000))) {
dev_err(cs35l56->base.dev, "%s: init_completion timed out\n", __func__);
return -ENODEV;
}
cs35l56->component = component;
wm_adsp2_component_probe(&cs35l56->dsp, component);
debugfs_create_bool("init_done", 0444, debugfs_root, &cs35l56->base.init_done);
debugfs_create_bool("can_hibernate", 0444, debugfs_root, &cs35l56->base.can_hibernate);
debugfs_create_bool("fw_patched", 0444, debugfs_root, &cs35l56->base.fw_patched);
queue_work(cs35l56->dsp_wq, &cs35l56->dsp_work);
return 0;
}
static void cs35l56_component_remove(struct snd_soc_component *component)
{
struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component);
cancel_work_sync(&cs35l56->dsp_work);
}
static int cs35l56_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_STANDBY:
/*
* Wait for patching to complete when transitioning from
* BIAS_OFF to BIAS_STANDBY
*/
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
cs35l56_wait_dsp_ready(cs35l56);
break;
default:
break;
}
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_cs35l56 = {
.probe = cs35l56_component_probe,
.remove = cs35l56_component_remove,
.dapm_widgets = cs35l56_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(cs35l56_dapm_widgets),
.dapm_routes = cs35l56_audio_map,
.num_dapm_routes = ARRAY_SIZE(cs35l56_audio_map),
.controls = cs35l56_controls,
.num_controls = ARRAY_SIZE(cs35l56_controls),
.set_bias_level = cs35l56_set_bias_level,
.suspend_bias_off = 1, /* see cs35l56_system_resume() */
};
static int __maybe_unused cs35l56_runtime_suspend_i2c_spi(struct device *dev)
{
struct cs35l56_private *cs35l56 = dev_get_drvdata(dev);
return cs35l56_runtime_suspend_common(&cs35l56->base);
}
static int __maybe_unused cs35l56_runtime_resume_i2c_spi(struct device *dev)
{
struct cs35l56_private *cs35l56 = dev_get_drvdata(dev);
return cs35l56_runtime_resume_common(&cs35l56->base, false);
}
int cs35l56_system_suspend(struct device *dev)
{
struct cs35l56_private *cs35l56 = dev_get_drvdata(dev);
dev_dbg(dev, "system_suspend\n");
if (cs35l56->component)
flush_work(&cs35l56->dsp_work);
/*
* The interrupt line is normally shared, but after we start suspending
* we can't check if our device is the source of an interrupt, and can't
* clear it. Prevent this race by temporarily disabling the parent irq
* until we reach _no_irq.
*/
if (cs35l56->base.irq)
disable_irq(cs35l56->base.irq);
return pm_runtime_force_suspend(dev);
}
EXPORT_SYMBOL_GPL(cs35l56_system_suspend);
int cs35l56_system_suspend_late(struct device *dev)
{
struct cs35l56_private *cs35l56 = dev_get_drvdata(dev);
dev_dbg(dev, "system_suspend_late\n");
/*
* Assert RESET before removing supplies.
* RESET is usually shared by all amps so it must not be asserted until
* all driver instances have done their suspend() stage.
*/
if (cs35l56->base.reset_gpio) {
gpiod_set_value_cansleep(cs35l56->base.reset_gpio, 0);
cs35l56_wait_min_reset_pulse();
}
regulator_bulk_disable(ARRAY_SIZE(cs35l56->supplies), cs35l56->supplies);
return 0;
}
EXPORT_SYMBOL_GPL(cs35l56_system_suspend_late);
int cs35l56_system_suspend_no_irq(struct device *dev)
{
struct cs35l56_private *cs35l56 = dev_get_drvdata(dev);
dev_dbg(dev, "system_suspend_no_irq\n");
/* Handlers are now disabled so the parent IRQ can safely be re-enabled. */
if (cs35l56->base.irq)
enable_irq(cs35l56->base.irq);
return 0;
}
EXPORT_SYMBOL_GPL(cs35l56_system_suspend_no_irq);
int cs35l56_system_resume_no_irq(struct device *dev)
{
struct cs35l56_private *cs35l56 = dev_get_drvdata(dev);
dev_dbg(dev, "system_resume_no_irq\n");
/*
* WAKE interrupts unmask if the CS35L56 hibernates, which can cause
* spurious interrupts, and the interrupt line is normally shared.
* We can't check if our device is the source of an interrupt, and can't
* clear it, until it has fully resumed. Prevent this race by temporarily
* disabling the parent irq until we complete resume().
*/
if (cs35l56->base.irq)
disable_irq(cs35l56->base.irq);
return 0;
}
EXPORT_SYMBOL_GPL(cs35l56_system_resume_no_irq);
int cs35l56_system_resume_early(struct device *dev)
{
struct cs35l56_private *cs35l56 = dev_get_drvdata(dev);
int ret;
dev_dbg(dev, "system_resume_early\n");
/* Ensure a spec-compliant RESET pulse. */
if (cs35l56->base.reset_gpio) {
gpiod_set_value_cansleep(cs35l56->base.reset_gpio, 0);
cs35l56_wait_min_reset_pulse();
}
/* Enable supplies before releasing RESET. */
ret = regulator_bulk_enable(ARRAY_SIZE(cs35l56->supplies), cs35l56->supplies);
if (ret) {
dev_err(dev, "system_resume_early failed to enable supplies: %d\n", ret);
return ret;
}
/* Release shared RESET before drivers start resume(). */
gpiod_set_value_cansleep(cs35l56->base.reset_gpio, 1);
return 0;
}
EXPORT_SYMBOL_GPL(cs35l56_system_resume_early);
int cs35l56_system_resume(struct device *dev)
{
struct cs35l56_private *cs35l56 = dev_get_drvdata(dev);
int ret;
dev_dbg(dev, "system_resume\n");
/*
* We might have done a hard reset or the CS35L56 was power-cycled
* so wait for control port to be ready.
*/
cs35l56_wait_control_port_ready();
/* Undo pm_runtime_force_suspend() before re-enabling the irq */
ret = pm_runtime_force_resume(dev);
if (cs35l56->base.irq)
enable_irq(cs35l56->base.irq);
if (ret)
return ret;
/* Firmware won't have been loaded if the component hasn't probed */
if (!cs35l56->component)
return 0;
ret = cs35l56_is_fw_reload_needed(&cs35l56->base);
dev_dbg(cs35l56->base.dev, "fw_reload_needed: %d\n", ret);
if (ret < 1)
return ret;
cs35l56->base.fw_patched = false;
wm_adsp_power_down(&cs35l56->dsp);
queue_work(cs35l56->dsp_wq, &cs35l56->dsp_work);
/*
* suspend_bias_off ensures we are now in BIAS_OFF so there will be
* a BIAS_OFF->BIAS_STANDBY transition to complete dsp patching.
*/
return 0;
}
EXPORT_SYMBOL_GPL(cs35l56_system_resume);
static int cs35l56_dsp_init(struct cs35l56_private *cs35l56)
{
struct wm_adsp *dsp;
int ret;
cs35l56->dsp_wq = create_singlethread_workqueue("cs35l56-dsp");
if (!cs35l56->dsp_wq)
return -ENOMEM;
INIT_WORK(&cs35l56->dsp_work, cs35l56_dsp_work);
dsp = &cs35l56->dsp;
cs35l56_init_cs_dsp(&cs35l56->base, &dsp->cs_dsp);
dsp->part = "cs35l56";
dsp->fw = 12;
dsp->wmfw_optional = true;
dev_dbg(cs35l56->base.dev, "DSP system name: '%s'\n", dsp->system_name);
ret = wm_halo_init(dsp);
if (ret != 0) {
dev_err(cs35l56->base.dev, "wm_halo_init failed\n");
return ret;
}
return 0;
}
static int cs35l56_get_firmware_uid(struct cs35l56_private *cs35l56)
{
struct device *dev = cs35l56->base.dev;
const char *prop;
int ret;
ret = device_property_read_string(dev, "cirrus,firmware-uid", &prop);
/* If bad sw node property, return 0 and fallback to legacy firmware path */
if (ret < 0)
return 0;
cs35l56->dsp.system_name = devm_kstrdup(dev, prop, GFP_KERNEL);
if (cs35l56->dsp.system_name == NULL)
return -ENOMEM;
dev_dbg(dev, "Firmware UID: %s\n", cs35l56->dsp.system_name);
return 0;
}
int cs35l56_common_probe(struct cs35l56_private *cs35l56)
{
int ret;
init_completion(&cs35l56->init_completion);
mutex_init(&cs35l56->base.irq_lock);
dev_set_drvdata(cs35l56->base.dev, cs35l56);
cs35l56_fill_supply_names(cs35l56->supplies);
ret = devm_regulator_bulk_get(cs35l56->base.dev, ARRAY_SIZE(cs35l56->supplies),
cs35l56->supplies);
if (ret != 0)
return dev_err_probe(cs35l56->base.dev, ret, "Failed to request supplies\n");
/* Reset could be controlled by the BIOS or shared by multiple amps */
cs35l56->base.reset_gpio = devm_gpiod_get_optional(cs35l56->base.dev, "reset",
GPIOD_OUT_LOW);
if (IS_ERR(cs35l56->base.reset_gpio)) {
ret = PTR_ERR(cs35l56->base.reset_gpio);
/*
* If RESET is shared the first amp to probe will grab the reset
* line and reset all the amps
*/
if (ret != -EBUSY)
return dev_err_probe(cs35l56->base.dev, ret, "Failed to get reset GPIO\n");
dev_info(cs35l56->base.dev, "Reset GPIO busy, assume shared reset\n");
cs35l56->base.reset_gpio = NULL;
}
ret = regulator_bulk_enable(ARRAY_SIZE(cs35l56->supplies), cs35l56->supplies);
if (ret != 0)
return dev_err_probe(cs35l56->base.dev, ret, "Failed to enable supplies\n");
if (cs35l56->base.reset_gpio) {
/* ACPI can override GPIOD_OUT_LOW flag so force it to start low */
gpiod_set_value_cansleep(cs35l56->base.reset_gpio, 0);
cs35l56_wait_min_reset_pulse();
gpiod_set_value_cansleep(cs35l56->base.reset_gpio, 1);
}
ret = cs35l56_get_firmware_uid(cs35l56);
if (ret != 0)
goto err;
ret = cs35l56_dsp_init(cs35l56);
if (ret < 0) {
dev_err_probe(cs35l56->base.dev, ret, "DSP init failed\n");
goto err;
}
ret = devm_snd_soc_register_component(cs35l56->base.dev,
&soc_component_dev_cs35l56,
cs35l56_dai, ARRAY_SIZE(cs35l56_dai));
if (ret < 0) {
dev_err_probe(cs35l56->base.dev, ret, "Register codec failed\n");
goto err;
}
return 0;
err:
gpiod_set_value_cansleep(cs35l56->base.reset_gpio, 0);
regulator_bulk_disable(ARRAY_SIZE(cs35l56->supplies), cs35l56->supplies);
return ret;
}
EXPORT_SYMBOL_NS_GPL(cs35l56_common_probe, SND_SOC_CS35L56_CORE);
int cs35l56_init(struct cs35l56_private *cs35l56)
{
int ret;
/*
* Check whether the actions associated with soft reset or one time
* init need to be performed.
*/
if (cs35l56->soft_resetting)
goto post_soft_reset;
if (cs35l56->base.init_done)
return 0;
pm_runtime_set_autosuspend_delay(cs35l56->base.dev, 100);
pm_runtime_use_autosuspend(cs35l56->base.dev);
pm_runtime_set_active(cs35l56->base.dev);
pm_runtime_enable(cs35l56->base.dev);
ret = cs35l56_hw_init(&cs35l56->base);
if (ret < 0)
return ret;
/* Populate the DSP information with the revision and security state */
cs35l56->dsp.part = devm_kasprintf(cs35l56->base.dev, GFP_KERNEL, "cs35l56%s-%02x",
cs35l56->base.secured ? "s" : "", cs35l56->base.rev);
if (!cs35l56->dsp.part)
return -ENOMEM;
if (!cs35l56->base.reset_gpio) {
dev_dbg(cs35l56->base.dev, "No reset gpio: using soft reset\n");
cs35l56->soft_resetting = true;
cs35l56_system_reset(&cs35l56->base, !!cs35l56->sdw_peripheral);
if (cs35l56->sdw_peripheral) {
/* Keep alive while we wait for re-enumeration */
pm_runtime_get_noresume(cs35l56->base.dev);
return 0;
}
}
post_soft_reset:
if (cs35l56->soft_resetting) {
cs35l56->soft_resetting = false;
/* Done re-enumerating after one-time init so release the keep-alive */
if (cs35l56->sdw_peripheral && !cs35l56->base.init_done)
pm_runtime_put_noidle(cs35l56->base.dev);
regcache_mark_dirty(cs35l56->base.regmap);
ret = cs35l56_wait_for_firmware_boot(&cs35l56->base);
if (ret)
return ret;
dev_dbg(cs35l56->base.dev, "Firmware rebooted after soft reset\n");
}
/* Disable auto-hibernate so that runtime_pm has control */
ret = cs35l56_mbox_send(&cs35l56->base, CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE);
if (ret)
return ret;
ret = cs35l56_set_patch(&cs35l56->base);
if (ret)
return ret;
/* Registers could be dirty after soft reset or SoundWire enumeration */
regcache_sync(cs35l56->base.regmap);
cs35l56->base.init_done = true;
complete(&cs35l56->init_completion);
return 0;
}
EXPORT_SYMBOL_NS_GPL(cs35l56_init, SND_SOC_CS35L56_CORE);
void cs35l56_remove(struct cs35l56_private *cs35l56)
{
cs35l56->base.init_done = false;
/*
* WAKE IRQs unmask if CS35L56 hibernates so free the handler to
* prevent it racing with remove().
*/
if (cs35l56->base.irq)
devm_free_irq(cs35l56->base.dev, cs35l56->base.irq, &cs35l56->base);
flush_workqueue(cs35l56->dsp_wq);
destroy_workqueue(cs35l56->dsp_wq);
pm_runtime_dont_use_autosuspend(cs35l56->base.dev);
pm_runtime_suspend(cs35l56->base.dev);
pm_runtime_disable(cs35l56->base.dev);
regcache_cache_only(cs35l56->base.regmap, true);
gpiod_set_value_cansleep(cs35l56->base.reset_gpio, 0);
regulator_bulk_disable(ARRAY_SIZE(cs35l56->supplies), cs35l56->supplies);
}
EXPORT_SYMBOL_NS_GPL(cs35l56_remove, SND_SOC_CS35L56_CORE);
const struct dev_pm_ops cs35l56_pm_ops_i2c_spi = {
SET_RUNTIME_PM_OPS(cs35l56_runtime_suspend_i2c_spi, cs35l56_runtime_resume_i2c_spi, NULL)
SYSTEM_SLEEP_PM_OPS(cs35l56_system_suspend, cs35l56_system_resume)
LATE_SYSTEM_SLEEP_PM_OPS(cs35l56_system_suspend_late, cs35l56_system_resume_early)
NOIRQ_SYSTEM_SLEEP_PM_OPS(cs35l56_system_suspend_no_irq, cs35l56_system_resume_no_irq)
};
EXPORT_SYMBOL_NS_GPL(cs35l56_pm_ops_i2c_spi, SND_SOC_CS35L56_CORE);
MODULE_DESCRIPTION("ASoC CS35L56 driver");
MODULE_IMPORT_NS(SND_SOC_CS35L56_SHARED);
MODULE_AUTHOR("Richard Fitzgerald <[email protected]>");
MODULE_AUTHOR("Simon Trimmer <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cs35l56.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Texas Instruments PCM186x Universal Audio ADC - I2C
*
* Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com
* Andreas Dannenberg <[email protected]>
* Andrew F. Davis <[email protected]>
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include "pcm186x.h"
static const struct of_device_id pcm186x_of_match[] = {
{ .compatible = "ti,pcm1862", .data = (void *)PCM1862 },
{ .compatible = "ti,pcm1863", .data = (void *)PCM1863 },
{ .compatible = "ti,pcm1864", .data = (void *)PCM1864 },
{ .compatible = "ti,pcm1865", .data = (void *)PCM1865 },
{ }
};
MODULE_DEVICE_TABLE(of, pcm186x_of_match);
static const struct i2c_device_id pcm186x_i2c_id[] = {
{ "pcm1862", PCM1862 },
{ "pcm1863", PCM1863 },
{ "pcm1864", PCM1864 },
{ "pcm1865", PCM1865 },
{ }
};
MODULE_DEVICE_TABLE(i2c, pcm186x_i2c_id);
static int pcm186x_i2c_probe(struct i2c_client *i2c)
{
const struct i2c_device_id *id = i2c_match_id(pcm186x_i2c_id, i2c);
const enum pcm186x_type type = (enum pcm186x_type)id->driver_data;
int irq = i2c->irq;
struct regmap *regmap;
regmap = devm_regmap_init_i2c(i2c, &pcm186x_regmap);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return pcm186x_probe(&i2c->dev, type, irq, regmap);
}
static struct i2c_driver pcm186x_i2c_driver = {
.probe = pcm186x_i2c_probe,
.id_table = pcm186x_i2c_id,
.driver = {
.name = "pcm186x",
.of_match_table = pcm186x_of_match,
},
};
module_i2c_driver(pcm186x_i2c_driver);
MODULE_AUTHOR("Andreas Dannenberg <[email protected]>");
MODULE_AUTHOR("Andrew F. Davis <[email protected]>");
MODULE_DESCRIPTION("PCM186x Universal Audio ADC I2C Interface Driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/pcm186x-i2c.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// nau8821.c -- Nuvoton NAU88L21 audio codec driver
//
// Copyright 2021 Nuvoton Technology Corp.
// Author: John Hsu <[email protected]>
// Co-author: Seven Lee <[email protected]>
//
#include <linux/acpi.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/dmi.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/math64.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/initval.h>
#include <sound/jack.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include "nau8821.h"
#define NAU8821_JD_ACTIVE_HIGH BIT(0)
static int nau8821_quirk;
static int quirk_override = -1;
module_param_named(quirk, quirk_override, uint, 0444);
MODULE_PARM_DESC(quirk, "Board-specific quirk override");
#define NAU_FREF_MAX 13500000
#define NAU_FVCO_MAX 100000000
#define NAU_FVCO_MIN 90000000
#define NAU8821_BUTTON SND_JACK_BTN_0
/* the maximum frequency of CLK_ADC and CLK_DAC */
#define CLK_DA_AD_MAX 6144000
static int nau8821_configure_sysclk(struct nau8821 *nau8821,
int clk_id, unsigned int freq);
static bool nau8821_is_jack_inserted(struct regmap *regmap);
struct nau8821_fll {
int mclk_src;
int ratio;
int fll_frac;
int fll_int;
int clk_ref_div;
};
struct nau8821_fll_attr {
unsigned int param;
unsigned int val;
};
/* scaling for mclk from sysclk_src output */
static const struct nau8821_fll_attr mclk_src_scaling[] = {
{ 1, 0x0 },
{ 2, 0x2 },
{ 4, 0x3 },
{ 8, 0x4 },
{ 16, 0x5 },
{ 32, 0x6 },
{ 3, 0x7 },
{ 6, 0xa },
{ 12, 0xb },
{ 24, 0xc },
{ 48, 0xd },
{ 96, 0xe },
{ 5, 0xf },
};
/* ratio for input clk freq */
static const struct nau8821_fll_attr fll_ratio[] = {
{ 512000, 0x01 },
{ 256000, 0x02 },
{ 128000, 0x04 },
{ 64000, 0x08 },
{ 32000, 0x10 },
{ 8000, 0x20 },
{ 4000, 0x40 },
};
static const struct nau8821_fll_attr fll_pre_scalar[] = {
{ 0, 0x0 },
{ 1, 0x1 },
{ 2, 0x2 },
{ 3, 0x3 },
};
/* over sampling rate */
struct nau8821_osr_attr {
unsigned int osr;
unsigned int clk_src;
};
static const struct nau8821_osr_attr osr_dac_sel[] = {
{ 64, 2 }, /* OSR 64, SRC 1/4 */
{ 256, 0 }, /* OSR 256, SRC 1 */
{ 128, 1 }, /* OSR 128, SRC 1/2 */
{ 0, 0 },
{ 32, 3 }, /* OSR 32, SRC 1/8 */
};
static const struct nau8821_osr_attr osr_adc_sel[] = {
{ 32, 3 }, /* OSR 32, SRC 1/8 */
{ 64, 2 }, /* OSR 64, SRC 1/4 */
{ 128, 1 }, /* OSR 128, SRC 1/2 */
{ 256, 0 }, /* OSR 256, SRC 1 */
};
struct nau8821_dmic_speed {
unsigned int param;
unsigned int val;
};
static const struct nau8821_dmic_speed dmic_speed_sel[] = {
{ 0, 0x0 }, /*SPEED 1, SRC 1 */
{ 1, 0x1 }, /*SPEED 2, SRC 1/2 */
{ 2, 0x2 }, /*SPEED 4, SRC 1/4 */
{ 3, 0x3 }, /*SPEED 8, SRC 1/8 */
};
static const struct reg_default nau8821_reg_defaults[] = {
{ NAU8821_R01_ENA_CTRL, 0x00ff },
{ NAU8821_R03_CLK_DIVIDER, 0x0050 },
{ NAU8821_R04_FLL1, 0x0 },
{ NAU8821_R05_FLL2, 0x00bc },
{ NAU8821_R06_FLL3, 0x0008 },
{ NAU8821_R07_FLL4, 0x0010 },
{ NAU8821_R08_FLL5, 0x4000 },
{ NAU8821_R09_FLL6, 0x6900 },
{ NAU8821_R0A_FLL7, 0x0031 },
{ NAU8821_R0B_FLL8, 0x26e9 },
{ NAU8821_R0D_JACK_DET_CTRL, 0x0 },
{ NAU8821_R0F_INTERRUPT_MASK, 0x0 },
{ NAU8821_R12_INTERRUPT_DIS_CTRL, 0xffff },
{ NAU8821_R13_DMIC_CTRL, 0x0 },
{ NAU8821_R1A_GPIO12_CTRL, 0x0 },
{ NAU8821_R1B_TDM_CTRL, 0x0 },
{ NAU8821_R1C_I2S_PCM_CTRL1, 0x000a },
{ NAU8821_R1D_I2S_PCM_CTRL2, 0x8010 },
{ NAU8821_R1E_LEFT_TIME_SLOT, 0x0 },
{ NAU8821_R1F_RIGHT_TIME_SLOT, 0x0 },
{ NAU8821_R21_BIQ0_COF1, 0x0 },
{ NAU8821_R22_BIQ0_COF2, 0x0 },
{ NAU8821_R23_BIQ0_COF3, 0x0 },
{ NAU8821_R24_BIQ0_COF4, 0x0 },
{ NAU8821_R25_BIQ0_COF5, 0x0 },
{ NAU8821_R26_BIQ0_COF6, 0x0 },
{ NAU8821_R27_BIQ0_COF7, 0x0 },
{ NAU8821_R28_BIQ0_COF8, 0x0 },
{ NAU8821_R29_BIQ0_COF9, 0x0 },
{ NAU8821_R2A_BIQ0_COF10, 0x0 },
{ NAU8821_R2B_ADC_RATE, 0x0002 },
{ NAU8821_R2C_DAC_CTRL1, 0x0082 },
{ NAU8821_R2D_DAC_CTRL2, 0x0 },
{ NAU8821_R2F_DAC_DGAIN_CTRL, 0x0 },
{ NAU8821_R30_ADC_DGAIN_CTRL, 0x0 },
{ NAU8821_R31_MUTE_CTRL, 0x0 },
{ NAU8821_R32_HSVOL_CTRL, 0x0 },
{ NAU8821_R34_DACR_CTRL, 0xcfcf },
{ NAU8821_R35_ADC_DGAIN_CTRL1, 0xcfcf },
{ NAU8821_R36_ADC_DRC_KNEE_IP12, 0x1486 },
{ NAU8821_R37_ADC_DRC_KNEE_IP34, 0x0f12 },
{ NAU8821_R38_ADC_DRC_SLOPES, 0x25ff },
{ NAU8821_R39_ADC_DRC_ATKDCY, 0x3457 },
{ NAU8821_R3A_DAC_DRC_KNEE_IP12, 0x1486 },
{ NAU8821_R3B_DAC_DRC_KNEE_IP34, 0x0f12 },
{ NAU8821_R3C_DAC_DRC_SLOPES, 0x25f9 },
{ NAU8821_R3D_DAC_DRC_ATKDCY, 0x3457 },
{ NAU8821_R41_BIQ1_COF1, 0x0 },
{ NAU8821_R42_BIQ1_COF2, 0x0 },
{ NAU8821_R43_BIQ1_COF3, 0x0 },
{ NAU8821_R44_BIQ1_COF4, 0x0 },
{ NAU8821_R45_BIQ1_COF5, 0x0 },
{ NAU8821_R46_BIQ1_COF6, 0x0 },
{ NAU8821_R47_BIQ1_COF7, 0x0 },
{ NAU8821_R48_BIQ1_COF8, 0x0 },
{ NAU8821_R49_BIQ1_COF9, 0x0 },
{ NAU8821_R4A_BIQ1_COF10, 0x0 },
{ NAU8821_R4B_CLASSG_CTRL, 0x0 },
{ NAU8821_R4C_IMM_MODE_CTRL, 0x0 },
{ NAU8821_R4D_IMM_RMS_L, 0x0 },
{ NAU8821_R53_OTPDOUT_1, 0xaad8 },
{ NAU8821_R54_OTPDOUT_2, 0x0002 },
{ NAU8821_R55_MISC_CTRL, 0x0 },
{ NAU8821_R66_BIAS_ADJ, 0x0 },
{ NAU8821_R68_TRIM_SETTINGS, 0x0 },
{ NAU8821_R69_ANALOG_CONTROL_1, 0x0 },
{ NAU8821_R6A_ANALOG_CONTROL_2, 0x0 },
{ NAU8821_R6B_PGA_MUTE, 0x0 },
{ NAU8821_R71_ANALOG_ADC_1, 0x0011 },
{ NAU8821_R72_ANALOG_ADC_2, 0x0020 },
{ NAU8821_R73_RDAC, 0x0008 },
{ NAU8821_R74_MIC_BIAS, 0x0006 },
{ NAU8821_R76_BOOST, 0x0 },
{ NAU8821_R77_FEPGA, 0x0 },
{ NAU8821_R7E_PGA_GAIN, 0x0 },
{ NAU8821_R7F_POWER_UP_CONTROL, 0x0 },
{ NAU8821_R80_CHARGE_PUMP, 0x0 },
};
static bool nau8821_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case NAU8821_R00_RESET ... NAU8821_R01_ENA_CTRL:
case NAU8821_R03_CLK_DIVIDER ... NAU8821_R0B_FLL8:
case NAU8821_R0D_JACK_DET_CTRL:
case NAU8821_R0F_INTERRUPT_MASK ... NAU8821_R13_DMIC_CTRL:
case NAU8821_R1A_GPIO12_CTRL ... NAU8821_R1F_RIGHT_TIME_SLOT:
case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2D_DAC_CTRL2:
case NAU8821_R2F_DAC_DGAIN_CTRL ... NAU8821_R32_HSVOL_CTRL:
case NAU8821_R34_DACR_CTRL ... NAU8821_R3D_DAC_DRC_ATKDCY:
case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4F_FUSE_CTRL3:
case NAU8821_R51_FUSE_CTRL1:
case NAU8821_R53_OTPDOUT_1 ... NAU8821_R55_MISC_CTRL:
case NAU8821_R58_I2C_DEVICE_ID ... NAU8821_R5A_SOFTWARE_RST:
case NAU8821_R66_BIAS_ADJ:
case NAU8821_R68_TRIM_SETTINGS ... NAU8821_R6B_PGA_MUTE:
case NAU8821_R71_ANALOG_ADC_1 ... NAU8821_R74_MIC_BIAS:
case NAU8821_R76_BOOST ... NAU8821_R77_FEPGA:
case NAU8821_R7E_PGA_GAIN ... NAU8821_R82_GENERAL_STATUS:
return true;
default:
return false;
}
}
static bool nau8821_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case NAU8821_R00_RESET ... NAU8821_R01_ENA_CTRL:
case NAU8821_R03_CLK_DIVIDER ... NAU8821_R0B_FLL8:
case NAU8821_R0D_JACK_DET_CTRL:
case NAU8821_R0F_INTERRUPT_MASK:
case NAU8821_R11_INT_CLR_KEY_STATUS ... NAU8821_R13_DMIC_CTRL:
case NAU8821_R1A_GPIO12_CTRL ... NAU8821_R1F_RIGHT_TIME_SLOT:
case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2D_DAC_CTRL2:
case NAU8821_R2F_DAC_DGAIN_CTRL ... NAU8821_R32_HSVOL_CTRL:
case NAU8821_R34_DACR_CTRL ... NAU8821_R3D_DAC_DRC_ATKDCY:
case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4C_IMM_MODE_CTRL:
case NAU8821_R4E_FUSE_CTRL2 ... NAU8821_R4F_FUSE_CTRL3:
case NAU8821_R51_FUSE_CTRL1:
case NAU8821_R55_MISC_CTRL:
case NAU8821_R5A_SOFTWARE_RST:
case NAU8821_R66_BIAS_ADJ:
case NAU8821_R68_TRIM_SETTINGS ... NAU8821_R6B_PGA_MUTE:
case NAU8821_R71_ANALOG_ADC_1 ... NAU8821_R74_MIC_BIAS:
case NAU8821_R76_BOOST ... NAU8821_R77_FEPGA:
case NAU8821_R7E_PGA_GAIN ... NAU8821_R80_CHARGE_PUMP:
return true;
default:
return false;
}
}
static bool nau8821_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case NAU8821_R00_RESET:
case NAU8821_R10_IRQ_STATUS ... NAU8821_R11_INT_CLR_KEY_STATUS:
case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2A_BIQ0_COF10:
case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4A_BIQ1_COF10:
case NAU8821_R4D_IMM_RMS_L:
case NAU8821_R53_OTPDOUT_1 ... NAU8821_R54_OTPDOUT_2:
case NAU8821_R58_I2C_DEVICE_ID ... NAU8821_R5A_SOFTWARE_RST:
case NAU8821_R81_CHARGE_PUMP_INPUT_READ ... NAU8821_R82_GENERAL_STATUS:
return true;
default:
return false;
}
}
static int nau8821_biq_coeff_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct soc_bytes_ext *params = (void *)kcontrol->private_value;
if (!component->regmap)
return -EINVAL;
regmap_raw_read(component->regmap, NAU8821_R21_BIQ0_COF1,
ucontrol->value.bytes.data, params->max);
return 0;
}
static int nau8821_biq_coeff_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct soc_bytes_ext *params = (void *)kcontrol->private_value;
void *data;
if (!component->regmap)
return -EINVAL;
data = kmemdup(ucontrol->value.bytes.data,
params->max, GFP_KERNEL | GFP_DMA);
if (!data)
return -ENOMEM;
regmap_raw_write(component->regmap, NAU8821_R21_BIQ0_COF1,
data, params->max);
kfree(data);
return 0;
}
static const char * const nau8821_adc_decimation[] = {
"32", "64", "128", "256" };
static const struct soc_enum nau8821_adc_decimation_enum =
SOC_ENUM_SINGLE(NAU8821_R2B_ADC_RATE, NAU8821_ADC_SYNC_DOWN_SFT,
ARRAY_SIZE(nau8821_adc_decimation), nau8821_adc_decimation);
static const char * const nau8821_dac_oversampl[] = {
"64", "256", "128", "", "32" };
static const struct soc_enum nau8821_dac_oversampl_enum =
SOC_ENUM_SINGLE(NAU8821_R2C_DAC_CTRL1, NAU8821_DAC_OVERSAMPLE_SFT,
ARRAY_SIZE(nau8821_dac_oversampl), nau8821_dac_oversampl);
static const char * const nau8821_adc_drc_noise_gate[] = {
"1:1", "2:1", "4:1", "8:1" };
static const struct soc_enum nau8821_adc_drc_noise_gate_enum =
SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES, NAU8821_DRC_NG_SLP_ADC_SFT,
ARRAY_SIZE(nau8821_adc_drc_noise_gate),
nau8821_adc_drc_noise_gate);
static const char * const nau8821_adc_drc_expansion_slope[] = {
"1:1", "2:1", "4:1" };
static const struct soc_enum nau8821_adc_drc_expansion_slope_enum =
SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES, NAU8821_DRC_EXP_SLP_ADC_SFT,
ARRAY_SIZE(nau8821_adc_drc_expansion_slope),
nau8821_adc_drc_expansion_slope);
static const char * const nau8821_adc_drc_lower_region[] = {
"0", "1:2", "1:4", "1:8", "1:16", "", "", "1:1" };
static const struct soc_enum nau8821_adc_drc_lower_region_enum =
SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES,
NAU8821_DRC_CMP2_SLP_ADC_SFT,
ARRAY_SIZE(nau8821_adc_drc_lower_region),
nau8821_adc_drc_lower_region);
static const char * const nau8821_higher_region[] = {
"0", "1:2", "1:4", "1:8", "1:16", "", "", "1:1" };
static const struct soc_enum nau8821_higher_region_enum =
SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES,
NAU8821_DRC_CMP1_SLP_ADC_SFT,
ARRAY_SIZE(nau8821_higher_region),
nau8821_higher_region);
static const char * const nau8821_limiter_slope[] = {
"0", "1:2", "1:4", "1:8", "1:16", "1:32", "1:64", "1:1" };
static const struct soc_enum nau8821_limiter_slope_enum =
SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES,
NAU8821_DRC_LMT_SLP_ADC_SFT, ARRAY_SIZE(nau8821_limiter_slope),
nau8821_limiter_slope);
static const char * const nau8821_detection_attack_time[] = {
"Ts", "3Ts", "7Ts", "15Ts", "31Ts", "63Ts", "127Ts", "255Ts",
"", "511Ts" };
static const struct soc_enum nau8821_detection_attack_time_enum =
SOC_ENUM_SINGLE(NAU8821_R39_ADC_DRC_ATKDCY,
NAU8821_DRC_PK_COEF1_ADC_SFT,
ARRAY_SIZE(nau8821_detection_attack_time),
nau8821_detection_attack_time);
static const char * const nau8821_detection_release_time[] = {
"63Ts", "127Ts", "255Ts", "511Ts", "1023Ts", "2047Ts", "4095Ts",
"8191Ts", "", "16383Ts" };
static const struct soc_enum nau8821_detection_release_time_enum =
SOC_ENUM_SINGLE(NAU8821_R39_ADC_DRC_ATKDCY,
NAU8821_DRC_PK_COEF2_ADC_SFT,
ARRAY_SIZE(nau8821_detection_release_time),
nau8821_detection_release_time);
static const char * const nau8821_attack_time[] = {
"Ts", "3Ts", "7Ts", "15Ts", "31Ts", "63Ts", "127Ts", "255Ts",
"511Ts", "1023Ts", "2047Ts", "4095Ts", "8191Ts" };
static const struct soc_enum nau8821_attack_time_enum =
SOC_ENUM_SINGLE(NAU8821_R39_ADC_DRC_ATKDCY, NAU8821_DRC_ATK_ADC_SFT,
ARRAY_SIZE(nau8821_attack_time), nau8821_attack_time);
static const char * const nau8821_decay_time[] = {
"63Ts", "127Ts", "255Ts", "511Ts", "1023Ts", "2047Ts", "4095Ts",
"8191Ts", "16383Ts", "32757Ts", "65535Ts" };
static const struct soc_enum nau8821_decay_time_enum =
SOC_ENUM_SINGLE(NAU8821_R39_ADC_DRC_ATKDCY, NAU8821_DRC_DCY_ADC_SFT,
ARRAY_SIZE(nau8821_decay_time), nau8821_decay_time);
static const DECLARE_TLV_DB_MINMAX_MUTE(adc_vol_tlv, -6600, 2400);
static const DECLARE_TLV_DB_MINMAX_MUTE(sidetone_vol_tlv, -4200, 0);
static const DECLARE_TLV_DB_MINMAX(hp_vol_tlv, -900, 0);
static const DECLARE_TLV_DB_SCALE(playback_vol_tlv, -6600, 50, 1);
static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
static const DECLARE_TLV_DB_MINMAX_MUTE(crosstalk_vol_tlv, -7000, 2400);
static const DECLARE_TLV_DB_MINMAX(drc_knee4_tlv, -9800, -3500);
static const DECLARE_TLV_DB_MINMAX(drc_knee3_tlv, -8100, -1800);
static const struct snd_kcontrol_new nau8821_controls[] = {
SOC_DOUBLE_TLV("Mic Volume", NAU8821_R35_ADC_DGAIN_CTRL1,
NAU8821_ADCL_CH_VOL_SFT, NAU8821_ADCR_CH_VOL_SFT,
0xff, 0, adc_vol_tlv),
SOC_DOUBLE_TLV("Headphone Bypass Volume", NAU8821_R30_ADC_DGAIN_CTRL,
12, 8, 0x0f, 0, sidetone_vol_tlv),
SOC_DOUBLE_TLV("Headphone Volume", NAU8821_R32_HSVOL_CTRL,
NAU8821_HPL_VOL_SFT, NAU8821_HPR_VOL_SFT, 0x3, 1, hp_vol_tlv),
SOC_DOUBLE_TLV("Digital Playback Volume", NAU8821_R34_DACR_CTRL,
NAU8821_DACL_CH_VOL_SFT, NAU8821_DACR_CH_VOL_SFT,
0xcf, 0, playback_vol_tlv),
SOC_DOUBLE_TLV("Frontend PGA Volume", NAU8821_R7E_PGA_GAIN,
NAU8821_PGA_GAIN_L_SFT, NAU8821_PGA_GAIN_R_SFT,
37, 0, fepga_gain_tlv),
SOC_DOUBLE_TLV("Headphone Crosstalk Volume",
NAU8821_R2F_DAC_DGAIN_CTRL,
0, 8, 0xff, 0, crosstalk_vol_tlv),
SOC_SINGLE_TLV("ADC DRC KNEE4", NAU8821_R37_ADC_DRC_KNEE_IP34,
NAU8821_DRC_KNEE4_IP_ADC_SFT, 0x3f, 1, drc_knee4_tlv),
SOC_SINGLE_TLV("ADC DRC KNEE3", NAU8821_R37_ADC_DRC_KNEE_IP34,
NAU8821_DRC_KNEE3_IP_ADC_SFT, 0x3f, 1, drc_knee3_tlv),
SOC_ENUM("ADC DRC Noise Gate", nau8821_adc_drc_noise_gate_enum),
SOC_ENUM("ADC DRC Expansion Slope", nau8821_adc_drc_expansion_slope_enum),
SOC_ENUM("ADC DRC Lower Region", nau8821_adc_drc_lower_region_enum),
SOC_ENUM("ADC DRC Higher Region", nau8821_higher_region_enum),
SOC_ENUM("ADC DRC Limiter Slope", nau8821_limiter_slope_enum),
SOC_ENUM("ADC DRC Peak Detection Attack Time", nau8821_detection_attack_time_enum),
SOC_ENUM("ADC DRC Peak Detection Release Time", nau8821_detection_release_time_enum),
SOC_ENUM("ADC DRC Attack Time", nau8821_attack_time_enum),
SOC_ENUM("ADC DRC Decay Time", nau8821_decay_time_enum),
SOC_SINGLE("DRC Enable Switch", NAU8821_R36_ADC_DRC_KNEE_IP12,
NAU8821_DRC_ENA_ADC_SFT, 1, 0),
SOC_ENUM("ADC Decimation Rate", nau8821_adc_decimation_enum),
SOC_ENUM("DAC Oversampling Rate", nau8821_dac_oversampl_enum),
SND_SOC_BYTES_EXT("BIQ Coefficients", 20,
nau8821_biq_coeff_get, nau8821_biq_coeff_put),
SOC_SINGLE("ADC Phase Switch", NAU8821_R1B_TDM_CTRL,
NAU8821_ADCPHS_SFT, 1, 0),
};
static const struct snd_kcontrol_new nau8821_dmic_mode_switch =
SOC_DAPM_SINGLE("Switch", NAU8821_R13_DMIC_CTRL,
NAU8821_DMIC_EN_SFT, 1, 0);
static int dmic_clock_control(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *k, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
int i, speed_selection = -1, clk_adc_src, clk_adc;
unsigned int clk_divider_r03;
/* The DMIC clock is gotten from adc clock divided by
* CLK_DMIC_SRC (1, 2, 4, 8). The clock has to be equal or
* less than nau8821->dmic_clk_threshold.
*/
regmap_read(nau8821->regmap, NAU8821_R03_CLK_DIVIDER,
&clk_divider_r03);
clk_adc_src = (clk_divider_r03 & NAU8821_CLK_ADC_SRC_MASK)
>> NAU8821_CLK_ADC_SRC_SFT;
clk_adc = (nau8821->fs * 256) >> clk_adc_src;
for (i = 0 ; i < 4 ; i++)
if ((clk_adc >> dmic_speed_sel[i].param) <=
nau8821->dmic_clk_threshold) {
speed_selection = dmic_speed_sel[i].val;
break;
}
if (i == 4)
return -EINVAL;
dev_dbg(nau8821->dev,
"clk_adc=%d, dmic_clk_threshold = %d, param=%d, val = %d\n",
clk_adc, nau8821->dmic_clk_threshold,
dmic_speed_sel[i].param, dmic_speed_sel[i].val);
regmap_update_bits(nau8821->regmap, NAU8821_R13_DMIC_CTRL,
NAU8821_DMIC_SRC_MASK,
(speed_selection << NAU8821_DMIC_SRC_SFT));
return 0;
}
static int nau8821_left_adc_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
msleep(125);
regmap_update_bits(nau8821->regmap, NAU8821_R01_ENA_CTRL,
NAU8821_EN_ADCL, NAU8821_EN_ADCL);
break;
case SND_SOC_DAPM_POST_PMD:
regmap_update_bits(nau8821->regmap,
NAU8821_R01_ENA_CTRL, NAU8821_EN_ADCL, 0);
break;
default:
return -EINVAL;
}
return 0;
}
static int nau8821_right_adc_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
msleep(125);
regmap_update_bits(nau8821->regmap, NAU8821_R01_ENA_CTRL,
NAU8821_EN_ADCR, NAU8821_EN_ADCR);
break;
case SND_SOC_DAPM_POST_PMD:
regmap_update_bits(nau8821->regmap,
NAU8821_R01_ENA_CTRL, NAU8821_EN_ADCR, 0);
break;
default:
return -EINVAL;
}
return 0;
}
static int nau8821_pump_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct nau8821 *nau8821 =
snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
/* Prevent startup click by letting charge pump to ramp up */
msleep(20);
regmap_update_bits(nau8821->regmap, NAU8821_R80_CHARGE_PUMP,
NAU8821_JAMNODCLOW, NAU8821_JAMNODCLOW);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_update_bits(nau8821->regmap, NAU8821_R80_CHARGE_PUMP,
NAU8821_JAMNODCLOW, 0);
break;
default:
return -EINVAL;
}
return 0;
}
static int nau8821_output_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* Disables the TESTDAC to let DAC signal pass through. */
regmap_update_bits(nau8821->regmap, NAU8821_R66_BIAS_ADJ,
NAU8821_BIAS_TESTDAC_EN, 0);
break;
case SND_SOC_DAPM_POST_PMD:
regmap_update_bits(nau8821->regmap, NAU8821_R66_BIAS_ADJ,
NAU8821_BIAS_TESTDAC_EN, NAU8821_BIAS_TESTDAC_EN);
break;
default:
return -EINVAL;
}
return 0;
}
static int system_clock_control(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *k, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
if (SND_SOC_DAPM_EVENT_OFF(event)) {
dev_dbg(nau8821->dev, "system clock control : POWER OFF\n");
/* Set clock source to disable or internal clock before the
* playback or capture end. Codec needs clock for Jack
* detection and button press if jack inserted; otherwise,
* the clock should be closed.
*/
if (nau8821_is_jack_inserted(nau8821->regmap)) {
nau8821_configure_sysclk(nau8821,
NAU8821_CLK_INTERNAL, 0);
} else {
nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0);
}
}
return 0;
}
static int nau8821_left_fepga_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
if (!nau8821->left_input_single_end)
return 0;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_update_bits(nau8821->regmap, NAU8821_R77_FEPGA,
NAU8821_ACDC_CTRL_MASK | NAU8821_FEPGA_MODEL_MASK,
NAU8821_ACDC_VREF_MICN | NAU8821_FEPGA_MODEL_AAF);
regmap_update_bits(nau8821->regmap, NAU8821_R76_BOOST,
NAU8821_HP_BOOST_DISCHRG_EN, NAU8821_HP_BOOST_DISCHRG_EN);
break;
case SND_SOC_DAPM_POST_PMD:
regmap_update_bits(nau8821->regmap, NAU8821_R77_FEPGA,
NAU8821_ACDC_CTRL_MASK | NAU8821_FEPGA_MODEL_MASK, 0);
regmap_update_bits(nau8821->regmap, NAU8821_R76_BOOST,
NAU8821_HP_BOOST_DISCHRG_EN, 0);
break;
default:
break;
}
return 0;
}
static const struct snd_soc_dapm_widget nau8821_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("System Clock", SND_SOC_NOPM, 0, 0,
system_clock_control, SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("MICBIAS", NAU8821_R74_MIC_BIAS,
NAU8821_MICBIAS_POWERUP_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DMIC Clock", SND_SOC_NOPM, 0, 0,
dmic_clock_control, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_ADC("ADCL Power", NULL, NAU8821_R72_ANALOG_ADC_2,
NAU8821_POWERUP_ADCL_SFT, 0),
SND_SOC_DAPM_ADC("ADCR Power", NULL, NAU8821_R72_ANALOG_ADC_2,
NAU8821_POWERUP_ADCR_SFT, 0),
/* single-ended design only on the left */
SND_SOC_DAPM_PGA_S("Frontend PGA L", 1, NAU8821_R7F_POWER_UP_CONTROL,
NAU8821_PUP_PGA_L_SFT, 0, nau8821_left_fepga_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_S("Frontend PGA R", 1, NAU8821_R7F_POWER_UP_CONTROL,
NAU8821_PUP_PGA_R_SFT, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("ADCL Digital path", 0, NAU8821_R01_ENA_CTRL,
NAU8821_EN_ADCL_SFT, 0, nau8821_left_adc_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_S("ADCR Digital path", 0, NAU8821_R01_ENA_CTRL,
NAU8821_EN_ADCR_SFT, 0, nau8821_right_adc_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SWITCH("DMIC Enable", SND_SOC_NOPM,
0, 0, &nau8821_dmic_mode_switch),
SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, NAU8821_R1D_I2S_PCM_CTRL2,
NAU8821_I2S_TRISTATE_SFT, 1),
SND_SOC_DAPM_AIF_IN("AIFRX", "Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_PGA_S("ADACL", 2, NAU8821_R73_RDAC,
NAU8821_DACL_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("ADACR", 2, NAU8821_R73_RDAC,
NAU8821_DACR_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("ADACL Clock", 3, NAU8821_R73_RDAC,
NAU8821_DACL_CLK_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("ADACR Clock", 3, NAU8821_R73_RDAC,
NAU8821_DACR_CLK_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_DAC("DDACR", NULL, NAU8821_R01_ENA_CTRL,
NAU8821_EN_DACR_SFT, 0),
SND_SOC_DAPM_DAC("DDACL", NULL, NAU8821_R01_ENA_CTRL,
NAU8821_EN_DACL_SFT, 0),
SND_SOC_DAPM_PGA_S("HP amp L", 0, NAU8821_R4B_CLASSG_CTRL,
NAU8821_CLASSG_LDAC_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("HP amp R", 0, NAU8821_R4B_CLASSG_CTRL,
NAU8821_CLASSG_RDAC_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8821_R80_CHARGE_PUMP,
NAU8821_CHANRGE_PUMP_EN_SFT, 0, nau8821_pump_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA_S("Output Driver R Stage 1", 4,
NAU8821_R7F_POWER_UP_CONTROL,
NAU8821_PUP_INTEG_R_SFT, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("Output Driver L Stage 1", 4,
NAU8821_R7F_POWER_UP_CONTROL,
NAU8821_PUP_INTEG_L_SFT, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("Output Driver R Stage 2", 5,
NAU8821_R7F_POWER_UP_CONTROL,
NAU8821_PUP_DRV_INSTG_R_SFT, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("Output Driver L Stage 2", 5,
NAU8821_R7F_POWER_UP_CONTROL,
NAU8821_PUP_DRV_INSTG_L_SFT, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("Output Driver R Stage 3", 6,
NAU8821_R7F_POWER_UP_CONTROL,
NAU8821_PUP_MAIN_DRV_R_SFT, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("Output Driver L Stage 3", 6,
NAU8821_R7F_POWER_UP_CONTROL,
NAU8821_PUP_MAIN_DRV_L_SFT, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("Output DACL", 7,
NAU8821_R80_CHARGE_PUMP, NAU8821_POWER_DOWN_DACL_SFT,
0, nau8821_output_dac_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_S("Output DACR", 7,
NAU8821_R80_CHARGE_PUMP, NAU8821_POWER_DOWN_DACR_SFT,
0, nau8821_output_dac_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
/* HPOL/R are ungrounded by disabling 16 Ohm pull-downs on playback */
SND_SOC_DAPM_PGA_S("HPOL Pulldown", 8,
NAU8821_R0D_JACK_DET_CTRL,
NAU8821_SPKR_DWN1L_SFT, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("HPOR Pulldown", 8,
NAU8821_R0D_JACK_DET_CTRL,
NAU8821_SPKR_DWN1R_SFT, 0, NULL, 0),
/* High current HPOL/R boost driver */
SND_SOC_DAPM_PGA_S("HP Boost Driver", 9,
NAU8821_R76_BOOST, NAU8821_HP_BOOST_DIS_SFT, 1, NULL, 0),
SND_SOC_DAPM_PGA("Class G", NAU8821_R4B_CLASSG_CTRL,
NAU8821_CLASSG_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_INPUT("MICL"),
SND_SOC_DAPM_INPUT("MICR"),
SND_SOC_DAPM_INPUT("DMIC"),
SND_SOC_DAPM_OUTPUT("HPOL"),
SND_SOC_DAPM_OUTPUT("HPOR"),
};
static const struct snd_soc_dapm_route nau8821_dapm_routes[] = {
{"DMIC Enable", "Switch", "DMIC"},
{"DMIC Enable", NULL, "DMIC Clock"},
{"Frontend PGA L", NULL, "MICL"},
{"Frontend PGA R", NULL, "MICR"},
{"Frontend PGA L", NULL, "MICBIAS"},
{"Frontend PGA R", NULL, "MICBIAS"},
{"ADCL Power", NULL, "Frontend PGA L"},
{"ADCR Power", NULL, "Frontend PGA R"},
{"ADCL Digital path", NULL, "ADCL Power"},
{"ADCR Digital path", NULL, "ADCR Power"},
{"ADCL Digital path", NULL, "DMIC Enable"},
{"ADCR Digital path", NULL, "DMIC Enable"},
{"AIFTX", NULL, "ADCL Digital path"},
{"AIFTX", NULL, "ADCR Digital path"},
{"AIFTX", NULL, "System Clock"},
{"AIFRX", NULL, "System Clock"},
{"DDACL", NULL, "AIFRX"},
{"DDACR", NULL, "AIFRX"},
{"HP amp L", NULL, "DDACL"},
{"HP amp R", NULL, "DDACR"},
{"Charge Pump", NULL, "HP amp L"},
{"Charge Pump", NULL, "HP amp R"},
{"ADACL", NULL, "Charge Pump"},
{"ADACR", NULL, "Charge Pump"},
{"ADACL Clock", NULL, "ADACL"},
{"ADACR Clock", NULL, "ADACR"},
{"Output Driver L Stage 1", NULL, "ADACL Clock"},
{"Output Driver R Stage 1", NULL, "ADACR Clock"},
{"Output Driver L Stage 2", NULL, "Output Driver L Stage 1"},
{"Output Driver R Stage 2", NULL, "Output Driver R Stage 1"},
{"Output Driver L Stage 3", NULL, "Output Driver L Stage 2"},
{"Output Driver R Stage 3", NULL, "Output Driver R Stage 2"},
{"Output DACL", NULL, "Output Driver L Stage 3"},
{"Output DACR", NULL, "Output Driver R Stage 3"},
{"HPOL Pulldown", NULL, "Output DACL"},
{"HPOR Pulldown", NULL, "Output DACR"},
{"HP Boost Driver", NULL, "HPOL Pulldown"},
{"HP Boost Driver", NULL, "HPOR Pulldown"},
{"Class G", NULL, "HP Boost Driver"},
{"HPOL", NULL, "Class G"},
{"HPOR", NULL, "Class G"},
};
static const struct nau8821_osr_attr *
nau8821_get_osr(struct nau8821 *nau8821, int stream)
{
unsigned int osr;
if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
regmap_read(nau8821->regmap, NAU8821_R2C_DAC_CTRL1, &osr);
osr &= NAU8821_DAC_OVERSAMPLE_MASK;
if (osr >= ARRAY_SIZE(osr_dac_sel))
return NULL;
return &osr_dac_sel[osr];
} else {
regmap_read(nau8821->regmap, NAU8821_R2B_ADC_RATE, &osr);
osr &= NAU8821_ADC_SYNC_DOWN_MASK;
if (osr >= ARRAY_SIZE(osr_adc_sel))
return NULL;
return &osr_adc_sel[osr];
}
}
static int nau8821_dai_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
const struct nau8821_osr_attr *osr;
osr = nau8821_get_osr(nau8821, substream->stream);
if (!osr || !osr->osr)
return -EINVAL;
return snd_pcm_hw_constraint_minmax(substream->runtime,
SNDRV_PCM_HW_PARAM_RATE,
0, CLK_DA_AD_MAX / osr->osr);
}
static int nau8821_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
unsigned int val_len = 0, ctrl_val, bclk_fs, clk_div;
const struct nau8821_osr_attr *osr;
nau8821->fs = params_rate(params);
/* CLK_DAC or CLK_ADC = OSR * FS
* DAC or ADC clock frequency is defined as Over Sampling Rate (OSR)
* multiplied by the audio sample rate (Fs). Note that the OSR and Fs
* values must be selected such that the maximum frequency is less
* than 6.144 MHz.
*/
osr = nau8821_get_osr(nau8821, substream->stream);
if (!osr || !osr->osr)
return -EINVAL;
if (nau8821->fs * osr->osr > CLK_DA_AD_MAX)
return -EINVAL;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER,
NAU8821_CLK_DAC_SRC_MASK,
osr->clk_src << NAU8821_CLK_DAC_SRC_SFT);
else
regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER,
NAU8821_CLK_ADC_SRC_MASK,
osr->clk_src << NAU8821_CLK_ADC_SRC_SFT);
/* make BCLK and LRC divde configuration if the codec as master. */
regmap_read(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2, &ctrl_val);
if (ctrl_val & NAU8821_I2S_MS_MASTER) {
/* get the bclk and fs ratio */
bclk_fs = snd_soc_params_to_bclk(params) / nau8821->fs;
if (bclk_fs <= 32)
clk_div = 3;
else if (bclk_fs <= 64)
clk_div = 2;
else if (bclk_fs <= 128)
clk_div = 1;
else {
return -EINVAL;
}
regmap_update_bits(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2,
NAU8821_I2S_LRC_DIV_MASK | NAU8821_I2S_BLK_DIV_MASK,
(clk_div << NAU8821_I2S_LRC_DIV_SFT) | clk_div);
}
switch (params_width(params)) {
case 16:
val_len |= NAU8821_I2S_DL_16;
break;
case 20:
val_len |= NAU8821_I2S_DL_20;
break;
case 24:
val_len |= NAU8821_I2S_DL_24;
break;
case 32:
val_len |= NAU8821_I2S_DL_32;
break;
default:
return -EINVAL;
}
regmap_update_bits(nau8821->regmap, NAU8821_R1C_I2S_PCM_CTRL1,
NAU8821_I2S_DL_MASK, val_len);
return 0;
}
static int nau8821_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
unsigned int ctrl1_val = 0, ctrl2_val = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
ctrl2_val |= NAU8821_I2S_MS_MASTER;
break;
case SND_SOC_DAIFMT_CBC_CFC:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
ctrl1_val |= NAU8821_I2S_BP_INV;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
ctrl1_val |= NAU8821_I2S_DF_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
ctrl1_val |= NAU8821_I2S_DF_LEFT;
break;
case SND_SOC_DAIFMT_RIGHT_J:
ctrl1_val |= NAU8821_I2S_DF_RIGTH;
break;
case SND_SOC_DAIFMT_DSP_A:
ctrl1_val |= NAU8821_I2S_DF_PCM_AB;
break;
case SND_SOC_DAIFMT_DSP_B:
ctrl1_val |= NAU8821_I2S_DF_PCM_AB;
ctrl1_val |= NAU8821_I2S_PCMB_EN;
break;
default:
return -EINVAL;
}
regmap_update_bits(nau8821->regmap, NAU8821_R1C_I2S_PCM_CTRL1,
NAU8821_I2S_DL_MASK | NAU8821_I2S_DF_MASK |
NAU8821_I2S_BP_MASK | NAU8821_I2S_PCMB_MASK, ctrl1_val);
regmap_update_bits(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2,
NAU8821_I2S_MS_MASK, ctrl2_val);
return 0;
}
static int nau8821_digital_mute(struct snd_soc_dai *dai, int mute,
int direction)
{
struct snd_soc_component *component = dai->component;
struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
unsigned int val = 0;
if (mute)
val = NAU8821_DAC_SOFT_MUTE;
return regmap_update_bits(nau8821->regmap,
NAU8821_R31_MUTE_CTRL, NAU8821_DAC_SOFT_MUTE, val);
}
static const struct snd_soc_dai_ops nau8821_dai_ops = {
.startup = nau8821_dai_startup,
.hw_params = nau8821_hw_params,
.set_fmt = nau8821_set_dai_fmt,
.mute_stream = nau8821_digital_mute,
.no_capture_mute = 1,
};
#define NAU8821_RATES SNDRV_PCM_RATE_8000_192000
#define NAU8821_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
| SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver nau8821_dai = {
.name = NUVOTON_CODEC_DAI,
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = NAU8821_RATES,
.formats = NAU8821_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = NAU8821_RATES,
.formats = NAU8821_FORMATS,
},
.ops = &nau8821_dai_ops,
};
static bool nau8821_is_jack_inserted(struct regmap *regmap)
{
bool active_high, is_high;
int status, jkdet;
regmap_read(regmap, NAU8821_R0D_JACK_DET_CTRL, &jkdet);
active_high = jkdet & NAU8821_JACK_POLARITY;
regmap_read(regmap, NAU8821_R82_GENERAL_STATUS, &status);
is_high = status & NAU8821_GPIO2_IN;
/* return jack connection status according to jack insertion logic
* active high or active low.
*/
return active_high == is_high;
}
static void nau8821_int_status_clear_all(struct regmap *regmap)
{
int active_irq, clear_irq, i;
/* Reset the intrruption status from rightmost bit if the corres-
* ponding irq event occurs.
*/
regmap_read(regmap, NAU8821_R10_IRQ_STATUS, &active_irq);
for (i = 0; i < NAU8821_REG_DATA_LEN; i++) {
clear_irq = (0x1 << i);
if (active_irq & clear_irq)
regmap_write(regmap,
NAU8821_R11_INT_CLR_KEY_STATUS, clear_irq);
}
}
static void nau8821_eject_jack(struct nau8821 *nau8821)
{
struct snd_soc_dapm_context *dapm = nau8821->dapm;
struct regmap *regmap = nau8821->regmap;
struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
/* Detach 2kOhm Resistors from MICBIAS to MICGND */
regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS,
NAU8821_MICBIAS_JKR2, 0);
/* HPL/HPR short to ground */
regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
NAU8821_SPKR_DWN1R | NAU8821_SPKR_DWN1L, 0);
snd_soc_component_disable_pin(component, "MICBIAS");
snd_soc_dapm_sync(dapm);
/* Clear all interruption status */
nau8821_int_status_clear_all(regmap);
/* Enable the insertion interruption, disable the ejection inter-
* ruption, and then bypass de-bounce circuit.
*/
regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL,
NAU8821_IRQ_EJECT_DIS | NAU8821_IRQ_INSERT_DIS,
NAU8821_IRQ_EJECT_DIS);
/* Mask unneeded IRQs: 1 - disable, 0 - enable */
regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN,
NAU8821_IRQ_EJECT_EN);
regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
NAU8821_JACK_DET_DB_BYPASS, NAU8821_JACK_DET_DB_BYPASS);
/* Close clock for jack type detection at manual mode */
if (dapm->bias_level < SND_SOC_BIAS_PREPARE)
nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0);
/* Recover to normal channel input */
regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE,
NAU8821_ADC_R_SRC_EN, 0);
if (nau8821->key_enable) {
regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
NAU8821_IRQ_KEY_RELEASE_EN |
NAU8821_IRQ_KEY_PRESS_EN,
NAU8821_IRQ_KEY_RELEASE_EN |
NAU8821_IRQ_KEY_PRESS_EN);
regmap_update_bits(regmap,
NAU8821_R12_INTERRUPT_DIS_CTRL,
NAU8821_IRQ_KEY_RELEASE_DIS |
NAU8821_IRQ_KEY_PRESS_DIS,
NAU8821_IRQ_KEY_RELEASE_DIS |
NAU8821_IRQ_KEY_PRESS_DIS);
}
}
static void nau8821_jdet_work(struct work_struct *work)
{
struct nau8821 *nau8821 =
container_of(work, struct nau8821, jdet_work);
struct snd_soc_dapm_context *dapm = nau8821->dapm;
struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
struct regmap *regmap = nau8821->regmap;
int jack_status_reg, mic_detected, event = 0, event_mask = 0;
snd_soc_component_force_enable_pin(component, "MICBIAS");
snd_soc_dapm_sync(dapm);
msleep(20);
regmap_read(regmap, NAU8821_R58_I2C_DEVICE_ID, &jack_status_reg);
mic_detected = !(jack_status_reg & NAU8821_KEYDET);
if (mic_detected) {
dev_dbg(nau8821->dev, "Headset connected\n");
event |= SND_JACK_HEADSET;
/* 2kOhm Resistor from MICBIAS to MICGND1 */
regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS,
NAU8821_MICBIAS_JKR2, NAU8821_MICBIAS_JKR2);
/* Latch Right Channel Analog data
* input into the Right Channel Filter
*/
regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE,
NAU8821_ADC_R_SRC_EN, NAU8821_ADC_R_SRC_EN);
if (nau8821->key_enable) {
regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
NAU8821_IRQ_KEY_RELEASE_EN |
NAU8821_IRQ_KEY_PRESS_EN, 0);
regmap_update_bits(regmap,
NAU8821_R12_INTERRUPT_DIS_CTRL,
NAU8821_IRQ_KEY_RELEASE_DIS |
NAU8821_IRQ_KEY_PRESS_DIS, 0);
}
} else {
dev_dbg(nau8821->dev, "Headphone connected\n");
event |= SND_JACK_HEADPHONE;
snd_soc_component_disable_pin(component, "MICBIAS");
snd_soc_dapm_sync(dapm);
}
event_mask |= SND_JACK_HEADSET;
snd_soc_jack_report(nau8821->jack, event, event_mask);
}
/* Enable interruptions with internal clock. */
static void nau8821_setup_inserted_irq(struct nau8821 *nau8821)
{
struct regmap *regmap = nau8821->regmap;
/* Enable internal VCO needed for interruptions */
if (nau8821->dapm->bias_level < SND_SOC_BIAS_PREPARE)
nau8821_configure_sysclk(nau8821, NAU8821_CLK_INTERNAL, 0);
/* Chip needs one FSCLK cycle in order to generate interruptions,
* as we cannot guarantee one will be provided by the system. Turning
* master mode on then off enables us to generate that FSCLK cycle
* with a minimum of contention on the clock bus.
*/
regmap_update_bits(regmap, NAU8821_R1D_I2S_PCM_CTRL2,
NAU8821_I2S_MS_MASK, NAU8821_I2S_MS_MASTER);
regmap_update_bits(regmap, NAU8821_R1D_I2S_PCM_CTRL2,
NAU8821_I2S_MS_MASK, NAU8821_I2S_MS_SLAVE);
/* Not bypass de-bounce circuit */
regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
NAU8821_JACK_DET_DB_BYPASS, 0);
regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
NAU8821_IRQ_EJECT_EN, 0);
regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL,
NAU8821_IRQ_EJECT_DIS, 0);
}
static irqreturn_t nau8821_interrupt(int irq, void *data)
{
struct nau8821 *nau8821 = (struct nau8821 *)data;
struct regmap *regmap = nau8821->regmap;
int active_irq, clear_irq = 0, event = 0, event_mask = 0;
if (regmap_read(regmap, NAU8821_R10_IRQ_STATUS, &active_irq)) {
dev_err(nau8821->dev, "failed to read irq status\n");
return IRQ_NONE;
}
dev_dbg(nau8821->dev, "IRQ %d\n", active_irq);
if ((active_irq & NAU8821_JACK_EJECT_IRQ_MASK) ==
NAU8821_JACK_EJECT_DETECTED) {
regmap_update_bits(regmap, NAU8821_R71_ANALOG_ADC_1,
NAU8821_MICDET_MASK, NAU8821_MICDET_DIS);
nau8821_eject_jack(nau8821);
event_mask |= SND_JACK_HEADSET;
clear_irq = NAU8821_JACK_EJECT_IRQ_MASK;
} else if (active_irq & NAU8821_KEY_SHORT_PRESS_IRQ) {
event |= NAU8821_BUTTON;
event_mask |= NAU8821_BUTTON;
clear_irq = NAU8821_KEY_SHORT_PRESS_IRQ;
} else if (active_irq & NAU8821_KEY_RELEASE_IRQ) {
event_mask = NAU8821_BUTTON;
clear_irq = NAU8821_KEY_RELEASE_IRQ;
} else if ((active_irq & NAU8821_JACK_INSERT_IRQ_MASK) ==
NAU8821_JACK_INSERT_DETECTED) {
regmap_update_bits(regmap, NAU8821_R71_ANALOG_ADC_1,
NAU8821_MICDET_MASK, NAU8821_MICDET_EN);
if (nau8821_is_jack_inserted(regmap)) {
/* detect microphone and jack type */
cancel_work_sync(&nau8821->jdet_work);
schedule_work(&nau8821->jdet_work);
/* Turn off insertion interruption at manual mode */
regmap_update_bits(regmap,
NAU8821_R12_INTERRUPT_DIS_CTRL,
NAU8821_IRQ_INSERT_DIS,
NAU8821_IRQ_INSERT_DIS);
regmap_update_bits(regmap,
NAU8821_R0F_INTERRUPT_MASK,
NAU8821_IRQ_INSERT_EN,
NAU8821_IRQ_INSERT_EN);
nau8821_setup_inserted_irq(nau8821);
} else {
dev_warn(nau8821->dev,
"Inserted IRQ fired but not connected\n");
nau8821_eject_jack(nau8821);
}
}
if (!clear_irq)
clear_irq = active_irq;
/* clears the rightmost interruption */
regmap_write(regmap, NAU8821_R11_INT_CLR_KEY_STATUS, clear_irq);
if (event_mask)
snd_soc_jack_report(nau8821->jack, event, event_mask);
return IRQ_HANDLED;
}
static const struct regmap_config nau8821_regmap_config = {
.val_bits = NAU8821_REG_DATA_LEN,
.reg_bits = NAU8821_REG_ADDR_LEN,
.max_register = NAU8821_REG_MAX,
.readable_reg = nau8821_readable_reg,
.writeable_reg = nau8821_writeable_reg,
.volatile_reg = nau8821_volatile_reg,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = nau8821_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(nau8821_reg_defaults),
};
static int nau8821_component_probe(struct snd_soc_component *component)
{
struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm =
snd_soc_component_get_dapm(component);
nau8821->dapm = dapm;
return 0;
}
/**
* nau8821_calc_fll_param - Calculate FLL parameters.
* @fll_in: external clock provided to codec.
* @fs: sampling rate.
* @fll_param: Pointer to structure of FLL parameters.
*
* Calculate FLL parameters to configure codec.
*
* Returns 0 for success or negative error code.
*/
static int nau8821_calc_fll_param(unsigned int fll_in,
unsigned int fs, struct nau8821_fll *fll_param)
{
u64 fvco, fvco_max;
unsigned int fref, i, fvco_sel;
/* Ensure the reference clock frequency (FREF) is <= 13.5MHz by
* dividing freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
* FREF = freq_in / NAU8821_FLL_REF_DIV_MASK
*/
for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
fref = fll_in >> fll_pre_scalar[i].param;
if (fref <= NAU_FREF_MAX)
break;
}
if (i == ARRAY_SIZE(fll_pre_scalar))
return -EINVAL;
fll_param->clk_ref_div = fll_pre_scalar[i].val;
/* Choose the FLL ratio based on FREF */
for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
if (fref >= fll_ratio[i].param)
break;
}
if (i == ARRAY_SIZE(fll_ratio))
return -EINVAL;
fll_param->ratio = fll_ratio[i].val;
/* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.
* FDCO must be within the 90MHz - 100MHz or the FFL cannot be
* guaranteed across the full range of operation.
* FDCO = freq_out * 2 * mclk_src_scaling
*/
fvco_max = 0;
fvco_sel = ARRAY_SIZE(mclk_src_scaling);
for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param;
if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&
fvco_max < fvco) {
fvco_max = fvco;
fvco_sel = i;
}
}
if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel)
return -EINVAL;
fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
/* Calculate the FLL 10-bit integer input and the FLL 24-bit fractional
* input based on FDCO, FREF and FLL ratio.
*/
fvco = div_u64(fvco_max << 24, fref * fll_param->ratio);
fll_param->fll_int = (fvco >> 24) & 0x3ff;
fll_param->fll_frac = fvco & 0xffffff;
return 0;
}
static void nau8821_fll_apply(struct nau8821 *nau8821,
struct nau8821_fll *fll_param)
{
struct regmap *regmap = nau8821->regmap;
regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER,
NAU8821_CLK_SRC_MASK | NAU8821_CLK_MCLK_SRC_MASK,
NAU8821_CLK_SRC_MCLK | fll_param->mclk_src);
/* Make DSP operate at high speed for better performance. */
regmap_update_bits(regmap, NAU8821_R04_FLL1,
NAU8821_FLL_RATIO_MASK | NAU8821_ICTRL_LATCH_MASK,
fll_param->ratio | (0x6 << NAU8821_ICTRL_LATCH_SFT));
/* FLL 24-bit fractional input */
regmap_write(regmap, NAU8821_R0A_FLL7,
(fll_param->fll_frac >> 16) & 0xff);
regmap_write(regmap, NAU8821_R0B_FLL8, fll_param->fll_frac & 0xffff);
/* FLL 10-bit integer input */
regmap_update_bits(regmap, NAU8821_R06_FLL3,
NAU8821_FLL_INTEGER_MASK, fll_param->fll_int);
/* FLL pre-scaler */
regmap_update_bits(regmap, NAU8821_R07_FLL4,
NAU8821_HIGHBW_EN | NAU8821_FLL_REF_DIV_MASK,
NAU8821_HIGHBW_EN |
(fll_param->clk_ref_div << NAU8821_FLL_REF_DIV_SFT));
/* select divided VCO input */
regmap_update_bits(regmap, NAU8821_R08_FLL5,
NAU8821_FLL_CLK_SW_MASK, NAU8821_FLL_CLK_SW_REF);
/* Disable free-running mode */
regmap_update_bits(regmap,
NAU8821_R09_FLL6, NAU8821_DCO_EN, 0);
if (fll_param->fll_frac) {
/* set FLL loop filter enable and cutoff frequency at 500Khz */
regmap_update_bits(regmap, NAU8821_R08_FLL5,
NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN |
NAU8821_FLL_FTR_SW_MASK,
NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN |
NAU8821_FLL_FTR_SW_FILTER);
regmap_update_bits(regmap, NAU8821_R09_FLL6,
NAU8821_SDM_EN | NAU8821_CUTOFF500,
NAU8821_SDM_EN | NAU8821_CUTOFF500);
} else {
/* disable FLL loop filter and cutoff frequency */
regmap_update_bits(regmap, NAU8821_R08_FLL5,
NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN |
NAU8821_FLL_FTR_SW_MASK, NAU8821_FLL_FTR_SW_ACCU);
regmap_update_bits(regmap, NAU8821_R09_FLL6,
NAU8821_SDM_EN | NAU8821_CUTOFF500, 0);
}
}
/**
* nau8821_set_fll - FLL configuration of nau8821
* @component: codec component
* @pll_id: PLL requested
* @source: clock source
* @freq_in: frequency of input clock source
* @freq_out: must be 256*Fs in order to achieve the best performance
*
* The FLL function can select BCLK or MCLK as the input clock source.
*
* Returns 0 if the parameters have been applied successfully
* or negative error code.
*/
static int nau8821_set_fll(struct snd_soc_component *component,
int pll_id, int source, unsigned int freq_in, unsigned int freq_out)
{
struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
struct nau8821_fll fll_set_param, *fll_param = &fll_set_param;
int ret, fs;
fs = freq_out >> 8;
ret = nau8821_calc_fll_param(freq_in, fs, fll_param);
if (ret) {
dev_err(nau8821->dev,
"Unsupported input clock %d to output clock %d\n",
freq_in, freq_out);
return ret;
}
dev_dbg(nau8821->dev,
"mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
fll_param->mclk_src, fll_param->ratio, fll_param->fll_frac,
fll_param->fll_int, fll_param->clk_ref_div);
nau8821_fll_apply(nau8821, fll_param);
mdelay(2);
regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER,
NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_VCO);
return 0;
}
static void nau8821_configure_mclk_as_sysclk(struct regmap *regmap)
{
regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER,
NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_MCLK);
regmap_update_bits(regmap, NAU8821_R09_FLL6,
NAU8821_DCO_EN, 0);
/* Make DSP operate as default setting for power saving. */
regmap_update_bits(regmap, NAU8821_R04_FLL1,
NAU8821_ICTRL_LATCH_MASK, 0);
}
static int nau8821_configure_sysclk(struct nau8821 *nau8821,
int clk_id, unsigned int freq)
{
struct regmap *regmap = nau8821->regmap;
switch (clk_id) {
case NAU8821_CLK_DIS:
/* Clock provided externally and disable internal VCO clock */
nau8821_configure_mclk_as_sysclk(regmap);
break;
case NAU8821_CLK_MCLK:
nau8821_configure_mclk_as_sysclk(regmap);
/* MCLK not changed by clock tree */
regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER,
NAU8821_CLK_MCLK_SRC_MASK, 0);
break;
case NAU8821_CLK_INTERNAL:
if (nau8821_is_jack_inserted(regmap)) {
regmap_update_bits(regmap, NAU8821_R09_FLL6,
NAU8821_DCO_EN, NAU8821_DCO_EN);
regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER,
NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_VCO);
/* Decrease the VCO frequency and make DSP operate
* as default setting for power saving.
*/
regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER,
NAU8821_CLK_MCLK_SRC_MASK, 0xf);
regmap_update_bits(regmap, NAU8821_R04_FLL1,
NAU8821_ICTRL_LATCH_MASK |
NAU8821_FLL_RATIO_MASK, 0x10);
regmap_update_bits(regmap, NAU8821_R09_FLL6,
NAU8821_SDM_EN, NAU8821_SDM_EN);
}
break;
case NAU8821_CLK_FLL_MCLK:
/* Higher FLL reference input frequency can only set lower
* gain error, such as 0000 for input reference from MCLK
* 12.288Mhz.
*/
regmap_update_bits(regmap, NAU8821_R06_FLL3,
NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK,
NAU8821_FLL_CLK_SRC_MCLK | 0);
break;
case NAU8821_CLK_FLL_BLK:
/* If FLL reference input is from low frequency source,
* higher error gain can apply such as 0xf which has
* the most sensitive gain error correction threshold,
* Therefore, FLL has the most accurate DCO to
* target frequency.
*/
regmap_update_bits(regmap, NAU8821_R06_FLL3,
NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK,
NAU8821_FLL_CLK_SRC_BLK |
(0xf << NAU8821_GAIN_ERR_SFT));
break;
case NAU8821_CLK_FLL_FS:
/* If FLL reference input is from low frequency source,
* higher error gain can apply such as 0xf which has
* the most sensitive gain error correction threshold,
* Therefore, FLL has the most accurate DCO to
* target frequency.
*/
regmap_update_bits(regmap, NAU8821_R06_FLL3,
NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK,
NAU8821_FLL_CLK_SRC_FS |
(0xf << NAU8821_GAIN_ERR_SFT));
break;
default:
dev_err(nau8821->dev, "Invalid clock id (%d)\n", clk_id);
return -EINVAL;
}
nau8821->clk_id = clk_id;
dev_dbg(nau8821->dev, "Sysclk is %dHz and clock id is %d\n", freq,
nau8821->clk_id);
return 0;
}
static int nau8821_set_sysclk(struct snd_soc_component *component, int clk_id,
int source, unsigned int freq, int dir)
{
struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
return nau8821_configure_sysclk(nau8821, clk_id, freq);
}
static int nau8821_resume_setup(struct nau8821 *nau8821)
{
struct regmap *regmap = nau8821->regmap;
/* Close clock when jack type detection at manual mode */
nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0);
if (nau8821->irq) {
/* Clear all interruption status */
nau8821_int_status_clear_all(regmap);
/* Enable both insertion and ejection interruptions, and then
* bypass de-bounce circuit.
*/
regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN, 0);
regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
NAU8821_JACK_DET_DB_BYPASS,
NAU8821_JACK_DET_DB_BYPASS);
regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL,
NAU8821_IRQ_INSERT_DIS | NAU8821_IRQ_EJECT_DIS, 0);
}
return 0;
}
static int nau8821_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
struct regmap *regmap = nau8821->regmap;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
/* Setup codec configuration after resume */
if (snd_soc_component_get_bias_level(component) ==
SND_SOC_BIAS_OFF)
nau8821_resume_setup(nau8821);
break;
case SND_SOC_BIAS_OFF:
/* HPL/HPR short to ground */
regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
NAU8821_SPKR_DWN1R | NAU8821_SPKR_DWN1L, 0);
if (nau8821->irq) {
/* Reset the configuration of jack type for detection.
* Detach 2kOhm Resistors from MICBIAS to MICGND1/2.
*/
regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS,
NAU8821_MICBIAS_JKR2, 0);
/* Turn off all interruptions before system shutdown.
* Keep theinterruption quiet before resume
* setup completes.
*/
regmap_write(regmap,
NAU8821_R12_INTERRUPT_DIS_CTRL, 0xffff);
regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN,
NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN);
}
break;
default:
break;
}
return 0;
}
static int __maybe_unused nau8821_suspend(struct snd_soc_component *component)
{
struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
if (nau8821->irq)
disable_irq(nau8821->irq);
snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
/* Power down codec power; don't support button wakeup */
snd_soc_component_disable_pin(component, "MICBIAS");
snd_soc_dapm_sync(nau8821->dapm);
regcache_cache_only(nau8821->regmap, true);
regcache_mark_dirty(nau8821->regmap);
return 0;
}
static int __maybe_unused nau8821_resume(struct snd_soc_component *component)
{
struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
regcache_cache_only(nau8821->regmap, false);
regcache_sync(nau8821->regmap);
if (nau8821->irq)
enable_irq(nau8821->irq);
return 0;
}
static const struct snd_soc_component_driver nau8821_component_driver = {
.probe = nau8821_component_probe,
.set_sysclk = nau8821_set_sysclk,
.set_pll = nau8821_set_fll,
.set_bias_level = nau8821_set_bias_level,
.suspend = nau8821_suspend,
.resume = nau8821_resume,
.controls = nau8821_controls,
.num_controls = ARRAY_SIZE(nau8821_controls),
.dapm_widgets = nau8821_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(nau8821_dapm_widgets),
.dapm_routes = nau8821_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(nau8821_dapm_routes),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
/**
* nau8821_enable_jack_detect - Specify a jack for event reporting
*
* @component: component to register the jack with
* @jack: jack to use to report headset and button events on
*
* After this function has been called the headset insert/remove and button
* events will be routed to the given jack. Jack can be null to stop
* reporting.
*/
int nau8821_enable_jack_detect(struct snd_soc_component *component,
struct snd_soc_jack *jack)
{
struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
int ret;
nau8821->jack = jack;
/* Initiate jack detection work queue */
INIT_WORK(&nau8821->jdet_work, nau8821_jdet_work);
ret = devm_request_threaded_irq(nau8821->dev, nau8821->irq, NULL,
nau8821_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT,
"nau8821", nau8821);
if (ret) {
dev_err(nau8821->dev, "Cannot request irq %d (%d)\n",
nau8821->irq, ret);
return ret;
}
return ret;
}
EXPORT_SYMBOL_GPL(nau8821_enable_jack_detect);
static void nau8821_reset_chip(struct regmap *regmap)
{
regmap_write(regmap, NAU8821_R00_RESET, 0xffff);
regmap_write(regmap, NAU8821_R00_RESET, 0xffff);
}
static void nau8821_print_device_properties(struct nau8821 *nau8821)
{
struct device *dev = nau8821->dev;
dev_dbg(dev, "jkdet-enable: %d\n", nau8821->jkdet_enable);
dev_dbg(dev, "jkdet-pull-enable: %d\n", nau8821->jkdet_pull_enable);
dev_dbg(dev, "jkdet-pull-up: %d\n", nau8821->jkdet_pull_up);
dev_dbg(dev, "jkdet-polarity: %d\n", nau8821->jkdet_polarity);
dev_dbg(dev, "micbias-voltage: %d\n", nau8821->micbias_voltage);
dev_dbg(dev, "vref-impedance: %d\n", nau8821->vref_impedance);
dev_dbg(dev, "jack-insert-debounce: %d\n",
nau8821->jack_insert_debounce);
dev_dbg(dev, "jack-eject-debounce: %d\n",
nau8821->jack_eject_debounce);
dev_dbg(dev, "dmic-clk-threshold: %d\n",
nau8821->dmic_clk_threshold);
dev_dbg(dev, "key_enable: %d\n", nau8821->key_enable);
}
static int nau8821_read_device_properties(struct device *dev,
struct nau8821 *nau8821)
{
int ret;
nau8821->jkdet_enable = device_property_read_bool(dev,
"nuvoton,jkdet-enable");
nau8821->jkdet_pull_enable = device_property_read_bool(dev,
"nuvoton,jkdet-pull-enable");
nau8821->jkdet_pull_up = device_property_read_bool(dev,
"nuvoton,jkdet-pull-up");
nau8821->key_enable = device_property_read_bool(dev,
"nuvoton,key-enable");
nau8821->left_input_single_end = device_property_read_bool(dev,
"nuvoton,left-input-single-end");
ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity",
&nau8821->jkdet_polarity);
if (ret)
nau8821->jkdet_polarity = 1;
ret = device_property_read_u32(dev, "nuvoton,micbias-voltage",
&nau8821->micbias_voltage);
if (ret)
nau8821->micbias_voltage = 6;
ret = device_property_read_u32(dev, "nuvoton,vref-impedance",
&nau8821->vref_impedance);
if (ret)
nau8821->vref_impedance = 2;
ret = device_property_read_u32(dev, "nuvoton,jack-insert-debounce",
&nau8821->jack_insert_debounce);
if (ret)
nau8821->jack_insert_debounce = 7;
ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce",
&nau8821->jack_eject_debounce);
if (ret)
nau8821->jack_eject_debounce = 0;
ret = device_property_read_u32(dev, "nuvoton,dmic-clk-threshold",
&nau8821->dmic_clk_threshold);
if (ret)
nau8821->dmic_clk_threshold = 3072000;
return 0;
}
static void nau8821_init_regs(struct nau8821 *nau8821)
{
struct regmap *regmap = nau8821->regmap;
/* Enable Bias/Vmid */
regmap_update_bits(regmap, NAU8821_R66_BIAS_ADJ,
NAU8821_BIAS_VMID, NAU8821_BIAS_VMID);
regmap_update_bits(regmap, NAU8821_R76_BOOST,
NAU8821_GLOBAL_BIAS_EN, NAU8821_GLOBAL_BIAS_EN);
/* VMID Tieoff setting and enable TESTDAC.
* This sets the analog DAC inputs to a '0' input signal to avoid
* any glitches due to power up transients in both the analog and
* digital DAC circuit.
*/
regmap_update_bits(regmap, NAU8821_R66_BIAS_ADJ,
NAU8821_BIAS_VMID_SEL_MASK | NAU8821_BIAS_TESTDAC_EN,
(nau8821->vref_impedance << NAU8821_BIAS_VMID_SEL_SFT) |
NAU8821_BIAS_TESTDAC_EN);
/* Disable short Frame Sync detection logic */
regmap_update_bits(regmap, NAU8821_R1E_LEFT_TIME_SLOT,
NAU8821_DIS_FS_SHORT_DET, NAU8821_DIS_FS_SHORT_DET);
/* Disable Boost Driver, Automatic Short circuit protection enable */
regmap_update_bits(regmap, NAU8821_R76_BOOST,
NAU8821_PRECHARGE_DIS | NAU8821_HP_BOOST_DIS |
NAU8821_HP_BOOST_G_DIS | NAU8821_SHORT_SHUTDOWN_EN,
NAU8821_PRECHARGE_DIS | NAU8821_HP_BOOST_DIS |
NAU8821_HP_BOOST_G_DIS | NAU8821_SHORT_SHUTDOWN_EN);
/* Class G timer 64ms */
regmap_update_bits(regmap, NAU8821_R4B_CLASSG_CTRL,
NAU8821_CLASSG_TIMER_MASK,
0x20 << NAU8821_CLASSG_TIMER_SFT);
/* Class AB bias current to 2x, DAC Capacitor enable MSB/LSB */
regmap_update_bits(regmap, NAU8821_R6A_ANALOG_CONTROL_2,
NAU8821_HP_NON_CLASSG_CURRENT_2xADJ |
NAU8821_DAC_CAPACITOR_MSB | NAU8821_DAC_CAPACITOR_LSB,
NAU8821_HP_NON_CLASSG_CURRENT_2xADJ |
NAU8821_DAC_CAPACITOR_MSB | NAU8821_DAC_CAPACITOR_LSB);
/* Disable DACR/L power */
regmap_update_bits(regmap, NAU8821_R80_CHARGE_PUMP,
NAU8821_POWER_DOWN_DACR | NAU8821_POWER_DOWN_DACL, 0);
/* DAC clock delay 2ns, VREF */
regmap_update_bits(regmap, NAU8821_R73_RDAC,
NAU8821_DAC_CLK_DELAY_MASK | NAU8821_DAC_VREF_MASK,
(0x2 << NAU8821_DAC_CLK_DELAY_SFT) |
(0x3 << NAU8821_DAC_VREF_SFT));
regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS,
NAU8821_MICBIAS_VOLTAGE_MASK, nau8821->micbias_voltage);
/* Default oversampling/decimations settings are unusable
* (audible hiss). Set it to something better.
*/
regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE,
NAU8821_ADC_SYNC_DOWN_MASK, NAU8821_ADC_SYNC_DOWN_64);
regmap_update_bits(regmap, NAU8821_R2C_DAC_CTRL1,
NAU8821_DAC_OVERSAMPLE_MASK, NAU8821_DAC_OVERSAMPLE_64);
if (nau8821->left_input_single_end) {
regmap_update_bits(regmap, NAU8821_R6B_PGA_MUTE,
NAU8821_MUTE_MICNL_EN, NAU8821_MUTE_MICNL_EN);
regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS,
NAU8821_MICBIAS_LOWNOISE_EN, NAU8821_MICBIAS_LOWNOISE_EN);
}
}
static int nau8821_setup_irq(struct nau8821 *nau8821)
{
struct regmap *regmap = nau8821->regmap;
/* Jack detection */
regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL,
NAU8821_JKDET_OUTPUT_EN,
nau8821->jkdet_enable ? 0 : NAU8821_JKDET_OUTPUT_EN);
regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL,
NAU8821_JKDET_PULL_EN,
nau8821->jkdet_pull_enable ? 0 : NAU8821_JKDET_PULL_EN);
regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL,
NAU8821_JKDET_PULL_UP,
nau8821->jkdet_pull_up ? NAU8821_JKDET_PULL_UP : 0);
regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
NAU8821_JACK_POLARITY,
/* jkdet_polarity - 1 is for active-low */
nau8821->jkdet_polarity ? 0 : NAU8821_JACK_POLARITY);
regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
NAU8821_JACK_INSERT_DEBOUNCE_MASK,
nau8821->jack_insert_debounce <<
NAU8821_JACK_INSERT_DEBOUNCE_SFT);
regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
NAU8821_JACK_EJECT_DEBOUNCE_MASK,
nau8821->jack_eject_debounce <<
NAU8821_JACK_EJECT_DEBOUNCE_SFT);
/* Pull up IRQ pin */
regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
NAU8821_IRQ_PIN_PULL_UP | NAU8821_IRQ_PIN_PULL_EN |
NAU8821_IRQ_OUTPUT_EN, NAU8821_IRQ_PIN_PULL_UP |
NAU8821_IRQ_PIN_PULL_EN | NAU8821_IRQ_OUTPUT_EN);
/* Disable interruption before codec initiation done */
/* Mask unneeded IRQs: 1 - disable, 0 - enable */
regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 0x3f5, 0x3f5);
return 0;
}
/* Please keep this list alphabetically sorted */
static const struct dmi_system_id nau8821_quirk_table[] = {
{
/* Positivo CW14Q01P-V2 */
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Positivo Tecnologia SA"),
DMI_MATCH(DMI_BOARD_NAME, "CW14Q01P-V2"),
},
.driver_data = (void *)(NAU8821_JD_ACTIVE_HIGH),
},
{}
};
static void nau8821_check_quirks(void)
{
const struct dmi_system_id *dmi_id;
if (quirk_override != -1) {
nau8821_quirk = quirk_override;
return;
}
dmi_id = dmi_first_match(nau8821_quirk_table);
if (dmi_id)
nau8821_quirk = (unsigned long)dmi_id->driver_data;
}
static int nau8821_i2c_probe(struct i2c_client *i2c)
{
struct device *dev = &i2c->dev;
struct nau8821 *nau8821 = dev_get_platdata(&i2c->dev);
int ret, value;
if (!nau8821) {
nau8821 = devm_kzalloc(dev, sizeof(*nau8821), GFP_KERNEL);
if (!nau8821)
return -ENOMEM;
nau8821_read_device_properties(dev, nau8821);
}
i2c_set_clientdata(i2c, nau8821);
nau8821->regmap = devm_regmap_init_i2c(i2c, &nau8821_regmap_config);
if (IS_ERR(nau8821->regmap))
return PTR_ERR(nau8821->regmap);
nau8821->dev = dev;
nau8821->irq = i2c->irq;
nau8821_check_quirks();
if (nau8821_quirk & NAU8821_JD_ACTIVE_HIGH)
nau8821->jkdet_polarity = 0;
nau8821_print_device_properties(nau8821);
nau8821_reset_chip(nau8821->regmap);
ret = regmap_read(nau8821->regmap, NAU8821_R58_I2C_DEVICE_ID, &value);
if (ret) {
dev_err(dev, "Failed to read device id (%d)\n", ret);
return ret;
}
nau8821_init_regs(nau8821);
if (i2c->irq)
nau8821_setup_irq(nau8821);
ret = devm_snd_soc_register_component(&i2c->dev,
&nau8821_component_driver, &nau8821_dai, 1);
return ret;
}
static const struct i2c_device_id nau8821_i2c_ids[] = {
{ "nau8821", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, nau8821_i2c_ids);
#ifdef CONFIG_OF
static const struct of_device_id nau8821_of_ids[] = {
{ .compatible = "nuvoton,nau8821", },
{}
};
MODULE_DEVICE_TABLE(of, nau8821_of_ids);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id nau8821_acpi_match[] = {
{ "NVTN2020", 0 },
{},
};
MODULE_DEVICE_TABLE(acpi, nau8821_acpi_match);
#endif
static struct i2c_driver nau8821_driver = {
.driver = {
.name = "nau8821",
.of_match_table = of_match_ptr(nau8821_of_ids),
.acpi_match_table = ACPI_PTR(nau8821_acpi_match),
},
.probe = nau8821_i2c_probe,
.id_table = nau8821_i2c_ids,
};
module_i2c_driver(nau8821_driver);
MODULE_DESCRIPTION("ASoC nau8821 driver");
MODULE_AUTHOR("John Hsu <[email protected]>");
MODULE_AUTHOR("Seven Lee <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/nau8821.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8524.c -- WM8524 ALSA SoC Audio driver
*
* Copyright 2009 Wolfson Microelectronics plc
* Copyright 2017 NXP
*
* Based on WM8523 ALSA SoC Audio driver written by Mark Brown
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/gpio/consumer.h>
#include <linux/of_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#define WM8524_NUM_RATES 7
/* codec private data */
struct wm8524_priv {
struct gpio_desc *mute;
unsigned int sysclk;
unsigned int rate_constraint_list[WM8524_NUM_RATES];
struct snd_pcm_hw_constraint_list rate_constraint;
};
static const struct snd_soc_dapm_widget wm8524_dapm_widgets[] = {
SND_SOC_DAPM_DAC("DAC", "Playback", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_OUTPUT("LINEVOUTL"),
SND_SOC_DAPM_OUTPUT("LINEVOUTR"),
};
static const struct snd_soc_dapm_route wm8524_dapm_routes[] = {
{ "LINEVOUTL", NULL, "DAC" },
{ "LINEVOUTR", NULL, "DAC" },
};
static const struct {
int value;
int ratio;
} lrclk_ratios[WM8524_NUM_RATES] = {
{ 1, 128 },
{ 2, 192 },
{ 3, 256 },
{ 4, 384 },
{ 5, 512 },
{ 6, 768 },
{ 7, 1152 },
};
static int wm8524_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm8524_priv *wm8524 = snd_soc_component_get_drvdata(component);
/* The set of sample rates that can be supported depends on the
* MCLK supplied to the CODEC - enforce this.
*/
if (!wm8524->sysclk) {
dev_err(component->dev,
"No MCLK configured, call set_sysclk() on init\n");
return -EINVAL;
}
snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&wm8524->rate_constraint);
gpiod_set_value_cansleep(wm8524->mute, 1);
return 0;
}
static void wm8524_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm8524_priv *wm8524 = snd_soc_component_get_drvdata(component);
gpiod_set_value_cansleep(wm8524->mute, 0);
}
static int wm8524_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct wm8524_priv *wm8524 = snd_soc_component_get_drvdata(component);
unsigned int val;
int i, j = 0;
wm8524->sysclk = freq;
wm8524->rate_constraint.count = 0;
for (i = 0; i < ARRAY_SIZE(lrclk_ratios); i++) {
val = freq / lrclk_ratios[i].ratio;
/* Check that it's a standard rate since core can't
* cope with others and having the odd rates confuses
* constraint matching.
*/
switch (val) {
case 8000:
case 32000:
case 44100:
case 48000:
case 88200:
case 96000:
case 176400:
case 192000:
dev_dbg(component->dev, "Supported sample rate: %dHz\n",
val);
wm8524->rate_constraint_list[j++] = val;
wm8524->rate_constraint.count++;
break;
default:
dev_dbg(component->dev, "Skipping sample rate: %dHz\n",
val);
}
}
/* Need at least one supported rate... */
if (wm8524->rate_constraint.count == 0)
return -EINVAL;
return 0;
}
static int wm8524_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
fmt &= (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_INV_MASK |
SND_SOC_DAIFMT_MASTER_MASK);
if (fmt != (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS)) {
dev_err(codec_dai->dev, "Invalid DAI format\n");
return -EINVAL;
}
return 0;
}
static int wm8524_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
{
struct wm8524_priv *wm8524 = snd_soc_component_get_drvdata(dai->component);
if (wm8524->mute)
gpiod_set_value_cansleep(wm8524->mute, mute);
return 0;
}
#define WM8524_RATES SNDRV_PCM_RATE_8000_192000
#define WM8524_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops wm8524_dai_ops = {
.startup = wm8524_startup,
.shutdown = wm8524_shutdown,
.set_sysclk = wm8524_set_dai_sysclk,
.set_fmt = wm8524_set_fmt,
.mute_stream = wm8524_mute_stream,
};
static struct snd_soc_dai_driver wm8524_dai = {
.name = "wm8524-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = WM8524_RATES,
.formats = WM8524_FORMATS,
},
.ops = &wm8524_dai_ops,
};
static int wm8524_probe(struct snd_soc_component *component)
{
struct wm8524_priv *wm8524 = snd_soc_component_get_drvdata(component);
wm8524->rate_constraint.list = &wm8524->rate_constraint_list[0];
wm8524->rate_constraint.count =
ARRAY_SIZE(wm8524->rate_constraint_list);
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_wm8524 = {
.probe = wm8524_probe,
.dapm_widgets = wm8524_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8524_dapm_widgets),
.dapm_routes = wm8524_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(wm8524_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct of_device_id wm8524_of_match[] = {
{ .compatible = "wlf,wm8524" },
{ /* sentinel*/ }
};
MODULE_DEVICE_TABLE(of, wm8524_of_match);
static int wm8524_codec_probe(struct platform_device *pdev)
{
struct wm8524_priv *wm8524;
int ret;
wm8524 = devm_kzalloc(&pdev->dev, sizeof(struct wm8524_priv),
GFP_KERNEL);
if (wm8524 == NULL)
return -ENOMEM;
platform_set_drvdata(pdev, wm8524);
wm8524->mute = devm_gpiod_get(&pdev->dev, "wlf,mute", GPIOD_OUT_LOW);
if (IS_ERR(wm8524->mute)) {
ret = PTR_ERR(wm8524->mute);
dev_err_probe(&pdev->dev, ret, "Failed to get mute line\n");
return ret;
}
ret = devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_wm8524, &wm8524_dai, 1);
if (ret < 0)
dev_err(&pdev->dev, "Failed to register component: %d\n", ret);
return ret;
}
static struct platform_driver wm8524_codec_driver = {
.probe = wm8524_codec_probe,
.driver = {
.name = "wm8524-codec",
.of_match_table = wm8524_of_match,
},
};
module_platform_driver(wm8524_codec_driver);
MODULE_DESCRIPTION("ASoC WM8524 driver");
MODULE_AUTHOR("Mihai Serban <[email protected]>");
MODULE_ALIAS("platform:wm8524-codec");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8524.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// rt5682.c -- RT5682 ALSA SoC audio component driver
//
// Copyright 2018 Realtek Semiconductor Corp.
// Author: Bard Liao <[email protected]>
//
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/acpi.h>
#include <linux/gpio/consumer.h>
#include <linux/mutex.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/jack.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/rt5682.h>
#include "rl6231.h"
#include "rt5682.h"
const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = {
"AVDD",
"MICVDD",
"VBAT",
"DBVDD",
"LDO1-IN",
};
EXPORT_SYMBOL_GPL(rt5682_supply_names);
static const struct reg_sequence patch_list[] = {
{RT5682_HP_IMP_SENS_CTRL_19, 0x1000},
{RT5682_DAC_ADC_DIG_VOL1, 0xa020},
{RT5682_I2C_CTRL, 0x000f},
{RT5682_PLL2_INTERNAL, 0x8266},
{RT5682_SAR_IL_CMD_1, 0x22b7},
{RT5682_SAR_IL_CMD_3, 0x0365},
{RT5682_SAR_IL_CMD_6, 0x0110},
{RT5682_CHARGE_PUMP_1, 0x0210},
{RT5682_HP_LOGIC_CTRL_2, 0x0007},
{RT5682_SAR_IL_CMD_2, 0xac00},
{RT5682_CBJ_CTRL_7, 0x0104},
};
void rt5682_apply_patch_list(struct rt5682_priv *rt5682, struct device *dev)
{
int ret;
ret = regmap_multi_reg_write(rt5682->regmap, patch_list,
ARRAY_SIZE(patch_list));
if (ret)
dev_warn(dev, "Failed to apply regmap patch: %d\n", ret);
}
EXPORT_SYMBOL_GPL(rt5682_apply_patch_list);
const struct reg_default rt5682_reg[RT5682_REG_NUM] = {
{0x0002, 0x8080},
{0x0003, 0x8000},
{0x0005, 0x0000},
{0x0006, 0x0000},
{0x0008, 0x800f},
{0x000b, 0x0000},
{0x0010, 0x4040},
{0x0011, 0x0000},
{0x0012, 0x1404},
{0x0013, 0x1000},
{0x0014, 0xa00a},
{0x0015, 0x0404},
{0x0016, 0x0404},
{0x0019, 0xafaf},
{0x001c, 0x2f2f},
{0x001f, 0x0000},
{0x0022, 0x5757},
{0x0023, 0x0039},
{0x0024, 0x000b},
{0x0026, 0xc0c4},
{0x0029, 0x8080},
{0x002a, 0xa0a0},
{0x002b, 0x0300},
{0x0030, 0x0000},
{0x003c, 0x0080},
{0x0044, 0x0c0c},
{0x0049, 0x0000},
{0x0061, 0x0000},
{0x0062, 0x0000},
{0x0063, 0x003f},
{0x0064, 0x0000},
{0x0065, 0x0000},
{0x0066, 0x0030},
{0x0067, 0x0000},
{0x006b, 0x0000},
{0x006c, 0x0000},
{0x006d, 0x2200},
{0x006e, 0x0a10},
{0x0070, 0x8000},
{0x0071, 0x8000},
{0x0073, 0x0000},
{0x0074, 0x0000},
{0x0075, 0x0002},
{0x0076, 0x0001},
{0x0079, 0x0000},
{0x007a, 0x0000},
{0x007b, 0x0000},
{0x007c, 0x0100},
{0x007e, 0x0000},
{0x0080, 0x0000},
{0x0081, 0x0000},
{0x0082, 0x0000},
{0x0083, 0x0000},
{0x0084, 0x0000},
{0x0085, 0x0000},
{0x0086, 0x0005},
{0x0087, 0x0000},
{0x0088, 0x0000},
{0x008c, 0x0003},
{0x008d, 0x0000},
{0x008e, 0x0060},
{0x008f, 0x1000},
{0x0091, 0x0c26},
{0x0092, 0x0073},
{0x0093, 0x0000},
{0x0094, 0x0080},
{0x0098, 0x0000},
{0x009a, 0x0000},
{0x009b, 0x0000},
{0x009c, 0x0000},
{0x009d, 0x0000},
{0x009e, 0x100c},
{0x009f, 0x0000},
{0x00a0, 0x0000},
{0x00a3, 0x0002},
{0x00a4, 0x0001},
{0x00ae, 0x2040},
{0x00af, 0x0000},
{0x00b6, 0x0000},
{0x00b7, 0x0000},
{0x00b8, 0x0000},
{0x00b9, 0x0002},
{0x00be, 0x0000},
{0x00c0, 0x0160},
{0x00c1, 0x82a0},
{0x00c2, 0x0000},
{0x00d0, 0x0000},
{0x00d1, 0x2244},
{0x00d2, 0x3300},
{0x00d3, 0x2200},
{0x00d4, 0x0000},
{0x00d9, 0x0009},
{0x00da, 0x0000},
{0x00db, 0x0000},
{0x00dc, 0x00c0},
{0x00dd, 0x2220},
{0x00de, 0x3131},
{0x00df, 0x3131},
{0x00e0, 0x3131},
{0x00e2, 0x0000},
{0x00e3, 0x4000},
{0x00e4, 0x0aa0},
{0x00e5, 0x3131},
{0x00e6, 0x3131},
{0x00e7, 0x3131},
{0x00e8, 0x3131},
{0x00ea, 0xb320},
{0x00eb, 0x0000},
{0x00f0, 0x0000},
{0x00f1, 0x00d0},
{0x00f2, 0x00d0},
{0x00f6, 0x0000},
{0x00fa, 0x0000},
{0x00fb, 0x0000},
{0x00fc, 0x0000},
{0x00fd, 0x0000},
{0x00fe, 0x10ec},
{0x00ff, 0x6530},
{0x0100, 0xa0a0},
{0x010b, 0x0000},
{0x010c, 0xae00},
{0x010d, 0xaaa0},
{0x010e, 0x8aa2},
{0x010f, 0x02a2},
{0x0110, 0xc000},
{0x0111, 0x04a2},
{0x0112, 0x2800},
{0x0113, 0x0000},
{0x0117, 0x0100},
{0x0125, 0x0410},
{0x0132, 0x6026},
{0x0136, 0x5555},
{0x0138, 0x3700},
{0x013a, 0x2000},
{0x013b, 0x2000},
{0x013c, 0x2005},
{0x013f, 0x0000},
{0x0142, 0x0000},
{0x0145, 0x0002},
{0x0146, 0x0000},
{0x0147, 0x0000},
{0x0148, 0x0000},
{0x0149, 0x0000},
{0x0150, 0x79a1},
{0x0156, 0xaaaa},
{0x0160, 0x4ec0},
{0x0161, 0x0080},
{0x0162, 0x0200},
{0x0163, 0x0800},
{0x0164, 0x0000},
{0x0165, 0x0000},
{0x0166, 0x0000},
{0x0167, 0x000f},
{0x0168, 0x000f},
{0x0169, 0x0021},
{0x0190, 0x413d},
{0x0194, 0x0000},
{0x0195, 0x0000},
{0x0197, 0x0022},
{0x0198, 0x0000},
{0x0199, 0x0000},
{0x01af, 0x0000},
{0x01b0, 0x0400},
{0x01b1, 0x0000},
{0x01b2, 0x0000},
{0x01b3, 0x0000},
{0x01b4, 0x0000},
{0x01b5, 0x0000},
{0x01b6, 0x01c3},
{0x01b7, 0x02a0},
{0x01b8, 0x03e9},
{0x01b9, 0x1389},
{0x01ba, 0xc351},
{0x01bb, 0x0009},
{0x01bc, 0x0018},
{0x01bd, 0x002a},
{0x01be, 0x004c},
{0x01bf, 0x0097},
{0x01c0, 0x433d},
{0x01c2, 0x0000},
{0x01c3, 0x0000},
{0x01c4, 0x0000},
{0x01c5, 0x0000},
{0x01c6, 0x0000},
{0x01c7, 0x0000},
{0x01c8, 0x40af},
{0x01c9, 0x0702},
{0x01ca, 0x0000},
{0x01cb, 0x0000},
{0x01cc, 0x5757},
{0x01cd, 0x5757},
{0x01ce, 0x5757},
{0x01cf, 0x5757},
{0x01d0, 0x5757},
{0x01d1, 0x5757},
{0x01d2, 0x5757},
{0x01d3, 0x5757},
{0x01d4, 0x5757},
{0x01d5, 0x5757},
{0x01d6, 0x0000},
{0x01d7, 0x0008},
{0x01d8, 0x0029},
{0x01d9, 0x3333},
{0x01da, 0x0000},
{0x01db, 0x0004},
{0x01dc, 0x0000},
{0x01de, 0x7c00},
{0x01df, 0x0320},
{0x01e0, 0x06a1},
{0x01e1, 0x0000},
{0x01e2, 0x0000},
{0x01e3, 0x0000},
{0x01e4, 0x0000},
{0x01e6, 0x0001},
{0x01e7, 0x0000},
{0x01e8, 0x0000},
{0x01ea, 0x0000},
{0x01eb, 0x0000},
{0x01ec, 0x0000},
{0x01ed, 0x0000},
{0x01ee, 0x0000},
{0x01ef, 0x0000},
{0x01f0, 0x0000},
{0x01f1, 0x0000},
{0x01f2, 0x0000},
{0x01f3, 0x0000},
{0x01f4, 0x0000},
{0x0210, 0x6297},
{0x0211, 0xa005},
{0x0212, 0x824c},
{0x0213, 0xf7ff},
{0x0214, 0xf24c},
{0x0215, 0x0102},
{0x0216, 0x00a3},
{0x0217, 0x0048},
{0x0218, 0xa2c0},
{0x0219, 0x0400},
{0x021a, 0x00c8},
{0x021b, 0x00c0},
{0x021c, 0x0000},
{0x0250, 0x4500},
{0x0251, 0x40b3},
{0x0252, 0x0000},
{0x0253, 0x0000},
{0x0254, 0x0000},
{0x0255, 0x0000},
{0x0256, 0x0000},
{0x0257, 0x0000},
{0x0258, 0x0000},
{0x0259, 0x0000},
{0x025a, 0x0005},
{0x0270, 0x0000},
{0x02ff, 0x0110},
{0x0300, 0x001f},
{0x0301, 0x032c},
{0x0302, 0x5f21},
{0x0303, 0x4000},
{0x0304, 0x4000},
{0x0305, 0x06d5},
{0x0306, 0x8000},
{0x0307, 0x0700},
{0x0310, 0x4560},
{0x0311, 0xa4a8},
{0x0312, 0x7418},
{0x0313, 0x0000},
{0x0314, 0x0006},
{0x0315, 0xffff},
{0x0316, 0xc400},
{0x0317, 0x0000},
{0x03c0, 0x7e00},
{0x03c1, 0x8000},
{0x03c2, 0x8000},
{0x03c3, 0x8000},
{0x03c4, 0x8000},
{0x03c5, 0x8000},
{0x03c6, 0x8000},
{0x03c7, 0x8000},
{0x03c8, 0x8000},
{0x03c9, 0x8000},
{0x03ca, 0x8000},
{0x03cb, 0x8000},
{0x03cc, 0x8000},
{0x03d0, 0x0000},
{0x03d1, 0x0000},
{0x03d2, 0x0000},
{0x03d3, 0x0000},
{0x03d4, 0x2000},
{0x03d5, 0x2000},
{0x03d6, 0x0000},
{0x03d7, 0x0000},
{0x03d8, 0x2000},
{0x03d9, 0x2000},
{0x03da, 0x2000},
{0x03db, 0x2000},
{0x03dc, 0x0000},
{0x03dd, 0x0000},
{0x03de, 0x0000},
{0x03df, 0x2000},
{0x03e0, 0x0000},
{0x03e1, 0x0000},
{0x03e2, 0x0000},
{0x03e3, 0x0000},
{0x03e4, 0x0000},
{0x03e5, 0x0000},
{0x03e6, 0x0000},
{0x03e7, 0x0000},
{0x03e8, 0x0000},
{0x03e9, 0x0000},
{0x03ea, 0x0000},
{0x03eb, 0x0000},
{0x03ec, 0x0000},
{0x03ed, 0x0000},
{0x03ee, 0x0000},
{0x03ef, 0x0000},
{0x03f0, 0x0800},
{0x03f1, 0x0800},
{0x03f2, 0x0800},
{0x03f3, 0x0800},
};
EXPORT_SYMBOL_GPL(rt5682_reg);
bool rt5682_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case RT5682_RESET:
case RT5682_CBJ_CTRL_2:
case RT5682_INT_ST_1:
case RT5682_4BTN_IL_CMD_1:
case RT5682_AJD1_CTRL:
case RT5682_HP_CALIB_CTRL_1:
case RT5682_DEVICE_ID:
case RT5682_I2C_MODE:
case RT5682_HP_CALIB_CTRL_10:
case RT5682_EFUSE_CTRL_2:
case RT5682_JD_TOP_VC_VTRL:
case RT5682_HP_IMP_SENS_CTRL_19:
case RT5682_IL_CMD_1:
case RT5682_SAR_IL_CMD_2:
case RT5682_SAR_IL_CMD_4:
case RT5682_SAR_IL_CMD_10:
case RT5682_SAR_IL_CMD_11:
case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11:
case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11:
return true;
default:
return false;
}
}
EXPORT_SYMBOL_GPL(rt5682_volatile_register);
bool rt5682_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case RT5682_RESET:
case RT5682_VERSION_ID:
case RT5682_VENDOR_ID:
case RT5682_DEVICE_ID:
case RT5682_HP_CTRL_1:
case RT5682_HP_CTRL_2:
case RT5682_HPL_GAIN:
case RT5682_HPR_GAIN:
case RT5682_I2C_CTRL:
case RT5682_CBJ_BST_CTRL:
case RT5682_CBJ_CTRL_1:
case RT5682_CBJ_CTRL_2:
case RT5682_CBJ_CTRL_3:
case RT5682_CBJ_CTRL_4:
case RT5682_CBJ_CTRL_5:
case RT5682_CBJ_CTRL_6:
case RT5682_CBJ_CTRL_7:
case RT5682_DAC1_DIG_VOL:
case RT5682_STO1_ADC_DIG_VOL:
case RT5682_STO1_ADC_BOOST:
case RT5682_HP_IMP_GAIN_1:
case RT5682_HP_IMP_GAIN_2:
case RT5682_SIDETONE_CTRL:
case RT5682_STO1_ADC_MIXER:
case RT5682_AD_DA_MIXER:
case RT5682_STO1_DAC_MIXER:
case RT5682_A_DAC1_MUX:
case RT5682_DIG_INF2_DATA:
case RT5682_REC_MIXER:
case RT5682_CAL_REC:
case RT5682_ALC_BACK_GAIN:
case RT5682_PWR_DIG_1:
case RT5682_PWR_DIG_2:
case RT5682_PWR_ANLG_1:
case RT5682_PWR_ANLG_2:
case RT5682_PWR_ANLG_3:
case RT5682_PWR_MIXER:
case RT5682_PWR_VOL:
case RT5682_CLK_DET:
case RT5682_RESET_LPF_CTRL:
case RT5682_RESET_HPF_CTRL:
case RT5682_DMIC_CTRL_1:
case RT5682_I2S1_SDP:
case RT5682_I2S2_SDP:
case RT5682_ADDA_CLK_1:
case RT5682_ADDA_CLK_2:
case RT5682_I2S1_F_DIV_CTRL_1:
case RT5682_I2S1_F_DIV_CTRL_2:
case RT5682_TDM_CTRL:
case RT5682_TDM_ADDA_CTRL_1:
case RT5682_TDM_ADDA_CTRL_2:
case RT5682_DATA_SEL_CTRL_1:
case RT5682_TDM_TCON_CTRL:
case RT5682_GLB_CLK:
case RT5682_PLL_CTRL_1:
case RT5682_PLL_CTRL_2:
case RT5682_PLL_TRACK_1:
case RT5682_PLL_TRACK_2:
case RT5682_PLL_TRACK_3:
case RT5682_PLL_TRACK_4:
case RT5682_PLL_TRACK_5:
case RT5682_PLL_TRACK_6:
case RT5682_PLL_TRACK_11:
case RT5682_SDW_REF_CLK:
case RT5682_DEPOP_1:
case RT5682_DEPOP_2:
case RT5682_HP_CHARGE_PUMP_1:
case RT5682_HP_CHARGE_PUMP_2:
case RT5682_MICBIAS_1:
case RT5682_MICBIAS_2:
case RT5682_PLL_TRACK_12:
case RT5682_PLL_TRACK_14:
case RT5682_PLL2_CTRL_1:
case RT5682_PLL2_CTRL_2:
case RT5682_PLL2_CTRL_3:
case RT5682_PLL2_CTRL_4:
case RT5682_RC_CLK_CTRL:
case RT5682_I2S_M_CLK_CTRL_1:
case RT5682_I2S2_F_DIV_CTRL_1:
case RT5682_I2S2_F_DIV_CTRL_2:
case RT5682_EQ_CTRL_1:
case RT5682_EQ_CTRL_2:
case RT5682_IRQ_CTRL_1:
case RT5682_IRQ_CTRL_2:
case RT5682_IRQ_CTRL_3:
case RT5682_IRQ_CTRL_4:
case RT5682_INT_ST_1:
case RT5682_GPIO_CTRL_1:
case RT5682_GPIO_CTRL_2:
case RT5682_GPIO_CTRL_3:
case RT5682_HP_AMP_DET_CTRL_1:
case RT5682_HP_AMP_DET_CTRL_2:
case RT5682_MID_HP_AMP_DET:
case RT5682_LOW_HP_AMP_DET:
case RT5682_DELAY_BUF_CTRL:
case RT5682_SV_ZCD_1:
case RT5682_SV_ZCD_2:
case RT5682_IL_CMD_1:
case RT5682_IL_CMD_2:
case RT5682_IL_CMD_3:
case RT5682_IL_CMD_4:
case RT5682_IL_CMD_5:
case RT5682_IL_CMD_6:
case RT5682_4BTN_IL_CMD_1:
case RT5682_4BTN_IL_CMD_2:
case RT5682_4BTN_IL_CMD_3:
case RT5682_4BTN_IL_CMD_4:
case RT5682_4BTN_IL_CMD_5:
case RT5682_4BTN_IL_CMD_6:
case RT5682_4BTN_IL_CMD_7:
case RT5682_ADC_STO1_HP_CTRL_1:
case RT5682_ADC_STO1_HP_CTRL_2:
case RT5682_AJD1_CTRL:
case RT5682_JD1_THD:
case RT5682_JD2_THD:
case RT5682_JD_CTRL_1:
case RT5682_DUMMY_1:
case RT5682_DUMMY_2:
case RT5682_DUMMY_3:
case RT5682_DAC_ADC_DIG_VOL1:
case RT5682_BIAS_CUR_CTRL_2:
case RT5682_BIAS_CUR_CTRL_3:
case RT5682_BIAS_CUR_CTRL_4:
case RT5682_BIAS_CUR_CTRL_5:
case RT5682_BIAS_CUR_CTRL_6:
case RT5682_BIAS_CUR_CTRL_7:
case RT5682_BIAS_CUR_CTRL_8:
case RT5682_BIAS_CUR_CTRL_9:
case RT5682_BIAS_CUR_CTRL_10:
case RT5682_VREF_REC_OP_FB_CAP_CTRL:
case RT5682_CHARGE_PUMP_1:
case RT5682_DIG_IN_CTRL_1:
case RT5682_PAD_DRIVING_CTRL:
case RT5682_SOFT_RAMP_DEPOP:
case RT5682_CHOP_DAC:
case RT5682_CHOP_ADC:
case RT5682_CALIB_ADC_CTRL:
case RT5682_VOL_TEST:
case RT5682_SPKVDD_DET_STA:
case RT5682_TEST_MODE_CTRL_1:
case RT5682_TEST_MODE_CTRL_2:
case RT5682_TEST_MODE_CTRL_3:
case RT5682_TEST_MODE_CTRL_4:
case RT5682_TEST_MODE_CTRL_5:
case RT5682_PLL1_INTERNAL:
case RT5682_PLL2_INTERNAL:
case RT5682_STO_NG2_CTRL_1:
case RT5682_STO_NG2_CTRL_2:
case RT5682_STO_NG2_CTRL_3:
case RT5682_STO_NG2_CTRL_4:
case RT5682_STO_NG2_CTRL_5:
case RT5682_STO_NG2_CTRL_6:
case RT5682_STO_NG2_CTRL_7:
case RT5682_STO_NG2_CTRL_8:
case RT5682_STO_NG2_CTRL_9:
case RT5682_STO_NG2_CTRL_10:
case RT5682_STO1_DAC_SIL_DET:
case RT5682_SIL_PSV_CTRL1:
case RT5682_SIL_PSV_CTRL2:
case RT5682_SIL_PSV_CTRL3:
case RT5682_SIL_PSV_CTRL4:
case RT5682_SIL_PSV_CTRL5:
case RT5682_HP_IMP_SENS_CTRL_01:
case RT5682_HP_IMP_SENS_CTRL_02:
case RT5682_HP_IMP_SENS_CTRL_03:
case RT5682_HP_IMP_SENS_CTRL_04:
case RT5682_HP_IMP_SENS_CTRL_05:
case RT5682_HP_IMP_SENS_CTRL_06:
case RT5682_HP_IMP_SENS_CTRL_07:
case RT5682_HP_IMP_SENS_CTRL_08:
case RT5682_HP_IMP_SENS_CTRL_09:
case RT5682_HP_IMP_SENS_CTRL_10:
case RT5682_HP_IMP_SENS_CTRL_11:
case RT5682_HP_IMP_SENS_CTRL_12:
case RT5682_HP_IMP_SENS_CTRL_13:
case RT5682_HP_IMP_SENS_CTRL_14:
case RT5682_HP_IMP_SENS_CTRL_15:
case RT5682_HP_IMP_SENS_CTRL_16:
case RT5682_HP_IMP_SENS_CTRL_17:
case RT5682_HP_IMP_SENS_CTRL_18:
case RT5682_HP_IMP_SENS_CTRL_19:
case RT5682_HP_IMP_SENS_CTRL_20:
case RT5682_HP_IMP_SENS_CTRL_21:
case RT5682_HP_IMP_SENS_CTRL_22:
case RT5682_HP_IMP_SENS_CTRL_23:
case RT5682_HP_IMP_SENS_CTRL_24:
case RT5682_HP_IMP_SENS_CTRL_25:
case RT5682_HP_IMP_SENS_CTRL_26:
case RT5682_HP_IMP_SENS_CTRL_27:
case RT5682_HP_IMP_SENS_CTRL_28:
case RT5682_HP_IMP_SENS_CTRL_29:
case RT5682_HP_IMP_SENS_CTRL_30:
case RT5682_HP_IMP_SENS_CTRL_31:
case RT5682_HP_IMP_SENS_CTRL_32:
case RT5682_HP_IMP_SENS_CTRL_33:
case RT5682_HP_IMP_SENS_CTRL_34:
case RT5682_HP_IMP_SENS_CTRL_35:
case RT5682_HP_IMP_SENS_CTRL_36:
case RT5682_HP_IMP_SENS_CTRL_37:
case RT5682_HP_IMP_SENS_CTRL_38:
case RT5682_HP_IMP_SENS_CTRL_39:
case RT5682_HP_IMP_SENS_CTRL_40:
case RT5682_HP_IMP_SENS_CTRL_41:
case RT5682_HP_IMP_SENS_CTRL_42:
case RT5682_HP_IMP_SENS_CTRL_43:
case RT5682_HP_LOGIC_CTRL_1:
case RT5682_HP_LOGIC_CTRL_2:
case RT5682_HP_LOGIC_CTRL_3:
case RT5682_HP_CALIB_CTRL_1:
case RT5682_HP_CALIB_CTRL_2:
case RT5682_HP_CALIB_CTRL_3:
case RT5682_HP_CALIB_CTRL_4:
case RT5682_HP_CALIB_CTRL_5:
case RT5682_HP_CALIB_CTRL_6:
case RT5682_HP_CALIB_CTRL_7:
case RT5682_HP_CALIB_CTRL_9:
case RT5682_HP_CALIB_CTRL_10:
case RT5682_HP_CALIB_CTRL_11:
case RT5682_HP_CALIB_STA_1:
case RT5682_HP_CALIB_STA_2:
case RT5682_HP_CALIB_STA_3:
case RT5682_HP_CALIB_STA_4:
case RT5682_HP_CALIB_STA_5:
case RT5682_HP_CALIB_STA_6:
case RT5682_HP_CALIB_STA_7:
case RT5682_HP_CALIB_STA_8:
case RT5682_HP_CALIB_STA_9:
case RT5682_HP_CALIB_STA_10:
case RT5682_HP_CALIB_STA_11:
case RT5682_SAR_IL_CMD_1:
case RT5682_SAR_IL_CMD_2:
case RT5682_SAR_IL_CMD_3:
case RT5682_SAR_IL_CMD_4:
case RT5682_SAR_IL_CMD_5:
case RT5682_SAR_IL_CMD_6:
case RT5682_SAR_IL_CMD_7:
case RT5682_SAR_IL_CMD_8:
case RT5682_SAR_IL_CMD_9:
case RT5682_SAR_IL_CMD_10:
case RT5682_SAR_IL_CMD_11:
case RT5682_SAR_IL_CMD_12:
case RT5682_SAR_IL_CMD_13:
case RT5682_EFUSE_CTRL_1:
case RT5682_EFUSE_CTRL_2:
case RT5682_EFUSE_CTRL_3:
case RT5682_EFUSE_CTRL_4:
case RT5682_EFUSE_CTRL_5:
case RT5682_EFUSE_CTRL_6:
case RT5682_EFUSE_CTRL_7:
case RT5682_EFUSE_CTRL_8:
case RT5682_EFUSE_CTRL_9:
case RT5682_EFUSE_CTRL_10:
case RT5682_EFUSE_CTRL_11:
case RT5682_JD_TOP_VC_VTRL:
case RT5682_DRC1_CTRL_0:
case RT5682_DRC1_CTRL_1:
case RT5682_DRC1_CTRL_2:
case RT5682_DRC1_CTRL_3:
case RT5682_DRC1_CTRL_4:
case RT5682_DRC1_CTRL_5:
case RT5682_DRC1_CTRL_6:
case RT5682_DRC1_HARD_LMT_CTRL_1:
case RT5682_DRC1_HARD_LMT_CTRL_2:
case RT5682_DRC1_PRIV_1:
case RT5682_DRC1_PRIV_2:
case RT5682_DRC1_PRIV_3:
case RT5682_DRC1_PRIV_4:
case RT5682_DRC1_PRIV_5:
case RT5682_DRC1_PRIV_6:
case RT5682_DRC1_PRIV_7:
case RT5682_DRC1_PRIV_8:
case RT5682_EQ_AUTO_RCV_CTRL1:
case RT5682_EQ_AUTO_RCV_CTRL2:
case RT5682_EQ_AUTO_RCV_CTRL3:
case RT5682_EQ_AUTO_RCV_CTRL4:
case RT5682_EQ_AUTO_RCV_CTRL5:
case RT5682_EQ_AUTO_RCV_CTRL6:
case RT5682_EQ_AUTO_RCV_CTRL7:
case RT5682_EQ_AUTO_RCV_CTRL8:
case RT5682_EQ_AUTO_RCV_CTRL9:
case RT5682_EQ_AUTO_RCV_CTRL10:
case RT5682_EQ_AUTO_RCV_CTRL11:
case RT5682_EQ_AUTO_RCV_CTRL12:
case RT5682_EQ_AUTO_RCV_CTRL13:
case RT5682_ADC_L_EQ_LPF1_A1:
case RT5682_R_EQ_LPF1_A1:
case RT5682_L_EQ_LPF1_H0:
case RT5682_R_EQ_LPF1_H0:
case RT5682_L_EQ_BPF1_A1:
case RT5682_R_EQ_BPF1_A1:
case RT5682_L_EQ_BPF1_A2:
case RT5682_R_EQ_BPF1_A2:
case RT5682_L_EQ_BPF1_H0:
case RT5682_R_EQ_BPF1_H0:
case RT5682_L_EQ_BPF2_A1:
case RT5682_R_EQ_BPF2_A1:
case RT5682_L_EQ_BPF2_A2:
case RT5682_R_EQ_BPF2_A2:
case RT5682_L_EQ_BPF2_H0:
case RT5682_R_EQ_BPF2_H0:
case RT5682_L_EQ_BPF3_A1:
case RT5682_R_EQ_BPF3_A1:
case RT5682_L_EQ_BPF3_A2:
case RT5682_R_EQ_BPF3_A2:
case RT5682_L_EQ_BPF3_H0:
case RT5682_R_EQ_BPF3_H0:
case RT5682_L_EQ_BPF4_A1:
case RT5682_R_EQ_BPF4_A1:
case RT5682_L_EQ_BPF4_A2:
case RT5682_R_EQ_BPF4_A2:
case RT5682_L_EQ_BPF4_H0:
case RT5682_R_EQ_BPF4_H0:
case RT5682_L_EQ_HPF1_A1:
case RT5682_R_EQ_HPF1_A1:
case RT5682_L_EQ_HPF1_H0:
case RT5682_R_EQ_HPF1_H0:
case RT5682_L_EQ_PRE_VOL:
case RT5682_R_EQ_PRE_VOL:
case RT5682_L_EQ_POST_VOL:
case RT5682_R_EQ_POST_VOL:
case RT5682_I2C_MODE:
return true;
default:
return false;
}
}
EXPORT_SYMBOL_GPL(rt5682_readable_register);
static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
static const DECLARE_TLV_DB_RANGE(bst_tlv,
0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
);
/* Interface data select */
static const char * const rt5682_data_select[] = {
"L/R", "R/L", "L/L", "R/R"
};
static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum,
RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select);
static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum,
RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select);
static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum,
RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select);
static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum,
RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select);
static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum,
RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select);
static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux =
SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum);
static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux =
SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum);
static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux =
SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum);
static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux =
SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum);
static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux =
SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum);
static const char * const rt5682_dac_select[] = {
"IF1", "SOUND"
};
static SOC_ENUM_SINGLE_DECL(rt5682_dacl_enum,
RT5682_AD_DA_MIXER, RT5682_DAC1_L_SEL_SFT, rt5682_dac_select);
static const struct snd_kcontrol_new rt5682_dac_l_mux =
SOC_DAPM_ENUM("DAC L Mux", rt5682_dacl_enum);
static SOC_ENUM_SINGLE_DECL(rt5682_dacr_enum,
RT5682_AD_DA_MIXER, RT5682_DAC1_R_SEL_SFT, rt5682_dac_select);
static const struct snd_kcontrol_new rt5682_dac_r_mux =
SOC_DAPM_ENUM("DAC R Mux", rt5682_dacr_enum);
void rt5682_reset(struct rt5682_priv *rt5682)
{
regmap_write(rt5682->regmap, RT5682_RESET, 0);
if (!rt5682->is_sdw)
regmap_write(rt5682->regmap, RT5682_I2C_MODE, 1);
}
EXPORT_SYMBOL_GPL(rt5682_reset);
/**
* rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters
* @component: SoC audio component device.
* @filter_mask: mask of filters.
* @clk_src: clock source
*
* The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can
* only support standard 32fs or 64fs i2s format, ASRC should be enabled to
* support special i2s clock format such as Intel's 100fs(100 * sampling rate).
* ASRC function will track i2s clock and generate a corresponding system clock
* for codec. This function provides an API to select the clock source for a
* set of filters specified by the mask. And the component driver will turn on
* ASRC for these filters if ASRC is selected as their clock source.
*/
int rt5682_sel_asrc_clk_src(struct snd_soc_component *component,
unsigned int filter_mask, unsigned int clk_src)
{
switch (clk_src) {
case RT5682_CLK_SEL_SYS:
case RT5682_CLK_SEL_I2S1_ASRC:
case RT5682_CLK_SEL_I2S2_ASRC:
break;
default:
return -EINVAL;
}
if (filter_mask & RT5682_DA_STEREO1_FILTER) {
snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2,
RT5682_FILTER_CLK_SEL_MASK,
clk_src << RT5682_FILTER_CLK_SEL_SFT);
}
if (filter_mask & RT5682_AD_STEREO1_FILTER) {
snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3,
RT5682_FILTER_CLK_SEL_MASK,
clk_src << RT5682_FILTER_CLK_SEL_SFT);
}
return 0;
}
EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src);
static int rt5682_button_detect(struct snd_soc_component *component)
{
int btn_type, val;
val = snd_soc_component_read(component, RT5682_4BTN_IL_CMD_1);
btn_type = val & 0xfff0;
snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val);
dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type);
snd_soc_component_update_bits(component,
RT5682_SAR_IL_CMD_2, 0x10, 0x10);
return btn_type;
}
static void rt5682_enable_push_button_irq(struct snd_soc_component *component,
bool enable)
{
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
if (enable) {
snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN);
snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN);
snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040);
snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK,
RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR);
if (rt5682->is_sdw)
snd_soc_component_update_bits(component,
RT5682_IRQ_CTRL_3,
RT5682_IL_IRQ_MASK | RT5682_IL_IRQ_TYPE_MASK,
RT5682_IL_IRQ_EN | RT5682_IL_IRQ_PUL);
else
snd_soc_component_update_bits(component,
RT5682_IRQ_CTRL_3, RT5682_IL_IRQ_MASK,
RT5682_IL_IRQ_EN);
} else {
snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS);
snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS);
snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS);
snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST);
snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE);
}
}
/**
* rt5682_headset_detect - Detect headset.
* @component: SoC audio component device.
* @jack_insert: Jack insert or not.
*
* Detect whether is headset or not when jack inserted.
*
* Returns detect status.
*/
static int rt5682_headset_detect(struct snd_soc_component *component, int jack_insert)
{
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm = &component->dapm;
unsigned int val, count;
if (jack_insert) {
snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
RT5682_PWR_VREF2 | RT5682_PWR_MB,
RT5682_PWR_VREF2 | RT5682_PWR_MB);
snd_soc_component_update_bits(component,
RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
usleep_range(15000, 20000);
snd_soc_component_update_bits(component,
RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2);
snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
RT5682_PWR_CBJ, RT5682_PWR_CBJ);
snd_soc_component_update_bits(component,
RT5682_HP_CHARGE_PUMP_1,
RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0);
rt5682_enable_push_button_irq(component, false);
snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
usleep_range(55000, 60000);
snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH);
count = 0;
val = snd_soc_component_read(component, RT5682_CBJ_CTRL_2)
& RT5682_JACK_TYPE_MASK;
while (val == 0 && count < 50) {
usleep_range(10000, 15000);
val = snd_soc_component_read(component,
RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
count++;
}
switch (val) {
case 0x1:
case 0x2:
rt5682->jack_type = SND_JACK_HEADSET;
snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_EN);
rt5682_enable_push_button_irq(component, true);
break;
default:
rt5682->jack_type = SND_JACK_HEADPHONE;
break;
}
snd_soc_component_update_bits(component,
RT5682_HP_CHARGE_PUMP_1,
RT5682_OSW_L_MASK | RT5682_OSW_R_MASK,
RT5682_OSW_L_EN | RT5682_OSW_R_EN);
snd_soc_component_update_bits(component, RT5682_MICBIAS_2,
RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK,
RT5682_PWR_CLK25M_PU | RT5682_PWR_CLK1M_PU);
} else {
rt5682_enable_push_button_irq(component, false);
snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
if (!snd_soc_dapm_get_pin_status(dapm, "MICBIAS") &&
!snd_soc_dapm_get_pin_status(dapm, "PLL1") &&
!snd_soc_dapm_get_pin_status(dapm, "PLL2B"))
snd_soc_component_update_bits(component,
RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0);
if (!snd_soc_dapm_get_pin_status(dapm, "Vref2") &&
!snd_soc_dapm_get_pin_status(dapm, "PLL1") &&
!snd_soc_dapm_get_pin_status(dapm, "PLL2B"))
snd_soc_component_update_bits(component,
RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0);
snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
RT5682_PWR_CBJ, 0);
snd_soc_component_update_bits(component, RT5682_MICBIAS_2,
RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK,
RT5682_PWR_CLK25M_PD | RT5682_PWR_CLK1M_PD);
snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_DIS);
rt5682->jack_type = 0;
}
dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type);
return rt5682->jack_type;
}
static int rt5682_set_jack_detect(struct snd_soc_component *component,
struct snd_soc_jack *hs_jack, void *data)
{
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
rt5682->hs_jack = hs_jack;
if (rt5682->is_sdw && !rt5682->first_hw_init)
return 0;
if (!hs_jack) {
regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
RT5682_POW_JDH | RT5682_POW_JDL, 0);
cancel_delayed_work_sync(&rt5682->jack_detect_work);
return 0;
}
if (!rt5682->is_sdw) {
switch (rt5682->pdata.jd_src) {
case RT5682_JD1:
snd_soc_component_update_bits(component,
RT5682_CBJ_CTRL_5, 0x0700, 0x0600);
snd_soc_component_update_bits(component,
RT5682_CBJ_CTRL_2, RT5682_EXT_JD_SRC,
RT5682_EXT_JD_SRC_MANUAL);
snd_soc_component_write(component, RT5682_CBJ_CTRL_1,
0xd142);
snd_soc_component_update_bits(component,
RT5682_CBJ_CTRL_3, RT5682_CBJ_IN_BUF_EN,
RT5682_CBJ_IN_BUF_EN);
snd_soc_component_update_bits(component,
RT5682_SAR_IL_CMD_1, RT5682_SAR_POW_MASK,
RT5682_SAR_POW_EN);
regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ);
regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
RT5682_POW_IRQ | RT5682_POW_JDH |
RT5682_POW_ANA, RT5682_POW_IRQ |
RT5682_POW_JDH | RT5682_POW_ANA);
regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2,
RT5682_PWR_JDH, RT5682_PWR_JDH);
regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK,
RT5682_JD1_EN | RT5682_JD1_POL_NOR);
regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_4,
0x7f7f, (rt5682->pdata.btndet_delay << 8 |
rt5682->pdata.btndet_delay));
regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_5,
0x7f7f, (rt5682->pdata.btndet_delay << 8 |
rt5682->pdata.btndet_delay));
regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_6,
0x7f7f, (rt5682->pdata.btndet_delay << 8 |
rt5682->pdata.btndet_delay));
regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_7,
0x7f7f, (rt5682->pdata.btndet_delay << 8 |
rt5682->pdata.btndet_delay));
mod_delayed_work(system_power_efficient_wq,
&rt5682->jack_detect_work,
msecs_to_jiffies(250));
break;
case RT5682_JD_NULL:
regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
RT5682_POW_JDH | RT5682_POW_JDL, 0);
break;
default:
dev_warn(component->dev, "Wrong JD source\n");
break;
}
}
return 0;
}
void rt5682_jack_detect_handler(struct work_struct *work)
{
struct rt5682_priv *rt5682 =
container_of(work, struct rt5682_priv, jack_detect_work.work);
struct snd_soc_dapm_context *dapm;
int val, btn_type;
if (!rt5682->component ||
!snd_soc_card_is_instantiated(rt5682->component->card)) {
/* card not yet ready, try later */
mod_delayed_work(system_power_efficient_wq,
&rt5682->jack_detect_work, msecs_to_jiffies(15));
return;
}
if (rt5682->is_sdw) {
if (pm_runtime_status_suspended(rt5682->slave->dev.parent)) {
dev_dbg(&rt5682->slave->dev,
"%s: parent device is pm_runtime_status_suspended, skipping jack detection\n",
__func__);
return;
}
}
dapm = snd_soc_component_get_dapm(rt5682->component);
snd_soc_dapm_mutex_lock(dapm);
mutex_lock(&rt5682->calibrate_mutex);
val = snd_soc_component_read(rt5682->component, RT5682_AJD1_CTRL)
& RT5682_JDH_RS_MASK;
if (!val) {
/* jack in */
if (rt5682->jack_type == 0) {
/* jack was out, report jack type */
rt5682->jack_type =
rt5682_headset_detect(rt5682->component, 1);
rt5682->irq_work_delay_time = 0;
} else if ((rt5682->jack_type & SND_JACK_HEADSET) ==
SND_JACK_HEADSET) {
/* jack is already in, report button event */
rt5682->jack_type = SND_JACK_HEADSET;
btn_type = rt5682_button_detect(rt5682->component);
/**
* rt5682 can report three kinds of button behavior,
* one click, double click and hold. However,
* currently we will report button pressed/released
* event. So all the three button behaviors are
* treated as button pressed.
*/
switch (btn_type) {
case 0x8000:
case 0x4000:
case 0x2000:
rt5682->jack_type |= SND_JACK_BTN_0;
break;
case 0x1000:
case 0x0800:
case 0x0400:
rt5682->jack_type |= SND_JACK_BTN_1;
break;
case 0x0200:
case 0x0100:
case 0x0080:
rt5682->jack_type |= SND_JACK_BTN_2;
break;
case 0x0040:
case 0x0020:
case 0x0010:
rt5682->jack_type |= SND_JACK_BTN_3;
break;
case 0x0000: /* unpressed */
break;
default:
dev_err(rt5682->component->dev,
"Unexpected button code 0x%04x\n",
btn_type);
break;
}
}
} else {
/* jack out */
rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
rt5682->irq_work_delay_time = 50;
}
mutex_unlock(&rt5682->calibrate_mutex);
snd_soc_dapm_mutex_unlock(dapm);
snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3);
if (!rt5682->is_sdw) {
if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3))
schedule_delayed_work(&rt5682->jd_check_work, 0);
else
cancel_delayed_work_sync(&rt5682->jd_check_work);
}
}
EXPORT_SYMBOL_GPL(rt5682_jack_detect_handler);
static const struct snd_kcontrol_new rt5682_snd_controls[] = {
/* DAC Digital Volume */
SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL,
RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
/* IN Boost Volume */
SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL,
RT5682_BST_CBJ_SFT, 8, 0, bst_tlv),
/* ADC Digital Volume Control */
SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL,
RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1),
SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL,
RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
/* ADC Boost Volume Control */
SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST,
RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT,
3, 0, adc_bst_tlv),
};
static int rt5682_div_sel(struct rt5682_priv *rt5682,
int target, const int div[], int size)
{
int i;
if (rt5682->sysclk < target) {
dev_err(rt5682->component->dev,
"sysclk rate %d is too low\n", rt5682->sysclk);
return 0;
}
for (i = 0; i < size - 1; i++) {
dev_dbg(rt5682->component->dev, "div[%d]=%d\n", i, div[i]);
if (target * div[i] == rt5682->sysclk)
return i;
if (target * div[i + 1] > rt5682->sysclk) {
dev_dbg(rt5682->component->dev,
"can't find div for sysclk %d\n",
rt5682->sysclk);
return i;
}
}
if (target * div[i] < rt5682->sysclk)
dev_err(rt5682->component->dev,
"sysclk rate %d is too high\n", rt5682->sysclk);
return size - 1;
}
/**
* set_dmic_clk - Set parameter of dmic.
*
* @w: DAPM widget.
* @kcontrol: The kcontrol of this widget.
* @event: Event id.
*
* Choose dmic clock between 1MHz and 3MHz.
* It is better for clock to approximate 3MHz.
*/
static int set_dmic_clk(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
int idx, dmic_clk_rate = 3072000;
static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
if (rt5682->pdata.dmic_clk_rate)
dmic_clk_rate = rt5682->pdata.dmic_clk_rate;
idx = rt5682_div_sel(rt5682, dmic_clk_rate, div, ARRAY_SIZE(div));
snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1,
RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT);
return 0;
}
static int set_filter_clk(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
int ref, val, reg, idx;
static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48};
if (rt5682->is_sdw)
return 0;
val = snd_soc_component_read(component, RT5682_GPIO_CTRL_1) &
RT5682_GP4_PIN_MASK;
if (w->shift == RT5682_PWR_ADC_S1F_BIT &&
val == RT5682_GP4_PIN_ADCDAT2)
ref = 256 * rt5682->lrck[RT5682_AIF2];
else
ref = 256 * rt5682->lrck[RT5682_AIF1];
idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f));
if (w->shift == RT5682_PWR_ADC_S1F_BIT)
reg = RT5682_PLL_TRACK_3;
else
reg = RT5682_PLL_TRACK_2;
snd_soc_component_update_bits(component, reg,
RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT);
/* select over sample rate */
for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) {
if (rt5682->sysclk <= 12288000 * div_o[idx])
break;
}
snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
RT5682_ADC_OSR_MASK | RT5682_DAC_OSR_MASK,
(idx << RT5682_ADC_OSR_SFT) | (idx << RT5682_DAC_OSR_SFT));
return 0;
}
static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w,
struct snd_soc_dapm_widget *sink)
{
unsigned int val;
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
val = snd_soc_component_read(component, RT5682_GLB_CLK);
val &= RT5682_SCLK_SRC_MASK;
if (val == RT5682_SCLK_SRC_PLL1)
return 1;
else
return 0;
}
static int is_sys_clk_from_pll2(struct snd_soc_dapm_widget *w,
struct snd_soc_dapm_widget *sink)
{
unsigned int val;
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
val = snd_soc_component_read(component, RT5682_GLB_CLK);
val &= RT5682_SCLK_SRC_MASK;
if (val == RT5682_SCLK_SRC_PLL2)
return 1;
else
return 0;
}
static int is_using_asrc(struct snd_soc_dapm_widget *w,
struct snd_soc_dapm_widget *sink)
{
unsigned int reg, shift, val;
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
switch (w->shift) {
case RT5682_ADC_STO1_ASRC_SFT:
reg = RT5682_PLL_TRACK_3;
shift = RT5682_FILTER_CLK_SEL_SFT;
break;
case RT5682_DAC_STO1_ASRC_SFT:
reg = RT5682_PLL_TRACK_2;
shift = RT5682_FILTER_CLK_SEL_SFT;
break;
default:
return 0;
}
val = (snd_soc_component_read(component, reg) >> shift) & 0xf;
switch (val) {
case RT5682_CLK_SEL_I2S1_ASRC:
case RT5682_CLK_SEL_I2S2_ASRC:
return 1;
default:
return 0;
}
}
/* Digital Mixer */
static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
RT5682_M_STO1_ADC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
RT5682_M_STO1_ADC_L2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
RT5682_M_STO1_ADC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
RT5682_M_STO1_ADC_R2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5682_dac_l_mix[] = {
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
RT5682_M_ADCMIX_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
RT5682_M_DAC1_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5682_dac_r_mix[] = {
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
RT5682_M_ADCMIX_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
RT5682_M_DAC1_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
RT5682_M_DAC_L1_STO_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
RT5682_M_DAC_R1_STO_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
RT5682_M_DAC_L1_STO_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
RT5682_M_DAC_R1_STO_R_SFT, 1, 1),
};
/* Analog Input Mixer */
static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = {
SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER,
RT5682_M_CBJ_RM1_L_SFT, 1, 1),
};
/* STO1 ADC1 Source */
/* MX-26 [13] [5] */
static const char * const rt5682_sto1_adc1_src[] = {
"DAC MIX", "ADC"
};
static SOC_ENUM_SINGLE_DECL(
rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER,
RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src);
static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux =
SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum);
static SOC_ENUM_SINGLE_DECL(
rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER,
RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src);
static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux =
SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum);
/* STO1 ADC Source */
/* MX-26 [11:10] [3:2] */
static const char * const rt5682_sto1_adc_src[] = {
"ADC1 L", "ADC1 R"
};
static SOC_ENUM_SINGLE_DECL(
rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER,
RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src);
static const struct snd_kcontrol_new rt5682_sto1_adcl_mux =
SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum);
static SOC_ENUM_SINGLE_DECL(
rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER,
RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src);
static const struct snd_kcontrol_new rt5682_sto1_adcr_mux =
SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum);
/* STO1 ADC2 Source */
/* MX-26 [12] [4] */
static const char * const rt5682_sto1_adc2_src[] = {
"DAC MIX", "DMIC"
};
static SOC_ENUM_SINGLE_DECL(
rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER,
RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src);
static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux =
SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum);
static SOC_ENUM_SINGLE_DECL(
rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER,
RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src);
static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux =
SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum);
/* MX-79 [6:4] I2S1 ADC data location */
static const unsigned int rt5682_if1_adc_slot_values[] = {
0,
2,
4,
6,
};
static const char * const rt5682_if1_adc_slot_src[] = {
"Slot 0", "Slot 2", "Slot 4", "Slot 6"
};
static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum,
RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK,
rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values);
static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux =
SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum);
/* Analog DAC L1 Source, Analog DAC R1 Source*/
/* MX-2B [4], MX-2B [0]*/
static const char * const rt5682_alg_dac1_src[] = {
"Stereo1 DAC Mixer", "DAC1"
};
static SOC_ENUM_SINGLE_DECL(
rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX,
RT5682_A_DACL1_SFT, rt5682_alg_dac1_src);
static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux =
SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum);
static SOC_ENUM_SINGLE_DECL(
rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX,
RT5682_A_DACR1_SFT, rt5682_alg_dac1_src);
static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux =
SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum);
/* Out Switch */
static const struct snd_kcontrol_new hpol_switch =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
RT5682_L_MUTE_SFT, 1, 1);
static const struct snd_kcontrol_new hpor_switch =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
RT5682_R_MUTE_SFT, 1, 1);
static int rt5682_hp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_component_update_bits(component, RT5682_HP_CTRL_2,
RT5682_HP_C2_DAC_AMP_MUTE, 0);
snd_soc_component_update_bits(component, RT5682_HP_LOGIC_CTRL_2,
RT5682_HP_LC2_SIG_SOUR2_MASK, RT5682_HP_LC2_SIG_SOUR2_REG);
snd_soc_component_update_bits(component,
RT5682_DEPOP_1, 0x60, 0x60);
snd_soc_component_update_bits(component,
RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0080);
snd_soc_component_update_bits(component, RT5682_HP_CTRL_2,
RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN,
RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN);
usleep_range(5000, 10000);
snd_soc_component_update_bits(component, RT5682_CHARGE_PUMP_1,
RT5682_CP_SW_SIZE_MASK, RT5682_CP_SW_SIZE_L);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component, RT5682_HP_CTRL_2,
RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN, 0);
snd_soc_component_update_bits(component, RT5682_CHARGE_PUMP_1,
RT5682_CP_SW_SIZE_MASK, RT5682_CP_SW_SIZE_M);
snd_soc_component_update_bits(component,
RT5682_DEPOP_1, 0x60, 0x0);
snd_soc_component_update_bits(component,
RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000);
break;
}
return 0;
}
static int set_dmic_power(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
unsigned int delay = 50, val;
if (rt5682->pdata.dmic_delay)
delay = rt5682->pdata.dmic_delay;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
val = snd_soc_component_read(component, RT5682_GLB_CLK);
val &= RT5682_SCLK_SRC_MASK;
if (val == RT5682_SCLK_SRC_PLL1 || val == RT5682_SCLK_SRC_PLL2)
snd_soc_component_update_bits(component,
RT5682_PWR_ANLG_1,
RT5682_PWR_VREF2 | RT5682_PWR_MB,
RT5682_PWR_VREF2 | RT5682_PWR_MB);
/*Add delay to avoid pop noise*/
msleep(delay);
break;
case SND_SOC_DAPM_POST_PMD:
if (!rt5682->jack_type) {
if (!snd_soc_dapm_get_pin_status(w->dapm, "MICBIAS"))
snd_soc_component_update_bits(component,
RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0);
if (!snd_soc_dapm_get_pin_status(w->dapm, "Vref2"))
snd_soc_component_update_bits(component,
RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0);
}
break;
}
return 0;
}
static int rt5682_set_verf(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
switch (w->shift) {
case RT5682_PWR_VREF1_BIT:
snd_soc_component_update_bits(component,
RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0);
break;
case RT5682_PWR_VREF2_BIT:
snd_soc_component_update_bits(component,
RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
break;
}
break;
case SND_SOC_DAPM_POST_PMU:
usleep_range(15000, 20000);
switch (w->shift) {
case RT5682_PWR_VREF1_BIT:
snd_soc_component_update_bits(component,
RT5682_PWR_ANLG_1, RT5682_PWR_FV1,
RT5682_PWR_FV1);
break;
case RT5682_PWR_VREF2_BIT:
snd_soc_component_update_bits(component,
RT5682_PWR_ANLG_1, RT5682_PWR_FV2,
RT5682_PWR_FV2);
break;
}
break;
}
return 0;
}
static const unsigned int rt5682_adcdat_pin_values[] = {
1,
3,
};
static const char * const rt5682_adcdat_pin_select[] = {
"ADCDAT1",
"ADCDAT2",
};
static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum,
RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK,
rt5682_adcdat_pin_select, rt5682_adcdat_pin_values);
static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl =
SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum);
static const unsigned int rt5682_hpo_sig_out_values[] = {
2,
7,
};
static const char * const rt5682_hpo_sig_out_mode[] = {
"Legacy",
"OneBit",
};
static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_hpo_sig_out_enum,
RT5682_HP_LOGIC_CTRL_2, 0, RT5682_HP_LC2_SIG_SOUR1_MASK,
rt5682_hpo_sig_out_mode, rt5682_hpo_sig_out_values);
static const struct snd_kcontrol_new rt5682_hpo_sig_demux =
SOC_DAPM_ENUM("HPO Signal Demux", rt5682_hpo_sig_out_enum);
static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT,
0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0,
rt5682_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY("Vref2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, NULL, 0),
/* ASRC */
SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1,
RT5682_AD_ASRC_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1,
RT5682_DA_ASRC_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1,
RT5682_DMIC_ASRC_SFT, 0, NULL, 0),
/* Input Side */
SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT,
0, NULL, 0),
/* Input Lines */
SND_SOC_DAPM_INPUT("DMIC L1"),
SND_SOC_DAPM_INPUT("DMIC R1"),
SND_SOC_DAPM_INPUT("IN1P"),
SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1,
RT5682_DMIC_1_EN_SFT, 0, set_dmic_power,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
/* Boost */
SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
0, 0, NULL, 0),
/* REC Mixer */
SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix,
ARRAY_SIZE(rt5682_rec1_l_mix)),
SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2,
RT5682_PWR_RM1_L_BIT, 0, NULL, 0),
/* ADCs */
SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1,
RT5682_PWR_ADC_L1_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1,
RT5682_PWR_ADC_R1_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC,
RT5682_CKGEN_ADC1_SFT, 0, NULL, 0),
/* ADC Mux */
SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
&rt5682_sto1_adc1l_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
&rt5682_sto1_adc1r_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
&rt5682_sto1_adc2l_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
&rt5682_sto1_adc2r_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
&rt5682_sto1_adcl_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
&rt5682_sto1_adcr_mux),
SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
&rt5682_if1_adc_slot_mux),
/* ADC Mixer */
SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2,
RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk,
SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL,
RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix,
ARRAY_SIZE(rt5682_sto1_adc_l_mix)),
SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL,
RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix,
ARRAY_SIZE(rt5682_sto1_adc_r_mix)),
/* ADC PGA */
SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
/* Digital Interface */
SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT,
0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("SOUND DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("SOUND DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
/* Digital Interface Select */
SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5682_if1_01_adc_swap_mux),
SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5682_if1_23_adc_swap_mux),
SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5682_if1_45_adc_swap_mux),
SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5682_if1_67_adc_swap_mux),
SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5682_if2_adc_swap_mux),
SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0,
&rt5682_adcdat_pin_ctrl),
SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0,
&rt5682_dac_l_mux),
SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0,
&rt5682_dac_r_mux),
/* Audio Interface */
SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1),
SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1),
SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("SDWRX", "SDW Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("SDWTX", "SDW Capture", 0, SND_SOC_NOPM, 0, 0),
/* Output Side */
/* DAC mixer before sound effect */
SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)),
SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)),
/* DAC channel Mux */
SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
&rt5682_alg_dac_l1_mux),
SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
&rt5682_alg_dac_r1_mux),
/* DAC Mixer */
SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2,
RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk,
SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)),
SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)),
/* DACs */
SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1,
RT5682_PWR_DAC_L1_BIT, 0),
SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1,
RT5682_PWR_DAC_R1_BIT, 0),
SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC,
RT5682_CKGEN_DAC1_SFT, 0, NULL, 0),
/* HPO */
SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event,
SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1,
RT5682_PWR_HA_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1,
RT5682_PWR_HA_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1,
RT5682_PUMP_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1,
RT5682_CAPLESS_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0,
&hpol_switch),
SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0,
&hpor_switch),
SND_SOC_DAPM_OUT_DRV("HPO Legacy", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("HPO OneBit", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_DEMUX("HPO Signal Demux", SND_SOC_NOPM, 0, 0, &rt5682_hpo_sig_demux),
/* CLK DET */
SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET,
RT5682_SYS_CLK_DET_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET,
RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET,
RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET,
RT5682_POW_CLK_DET_SFT, 0, NULL, 0),
/* Output Lines */
SND_SOC_DAPM_OUTPUT("HPOL"),
SND_SOC_DAPM_OUTPUT("HPOR"),
};
static const struct snd_soc_dapm_route rt5682_dapm_routes[] = {
/*PLL*/
{"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
{"ADC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
{"ADC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
{"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
{"DAC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
{"DAC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
/*ASRC*/
{"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
{"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
{"ADC STO1 ASRC", NULL, "AD ASRC"},
{"ADC STO1 ASRC", NULL, "DA ASRC"},
{"ADC STO1 ASRC", NULL, "CLKDET"},
{"DAC STO1 ASRC", NULL, "AD ASRC"},
{"DAC STO1 ASRC", NULL, "DA ASRC"},
{"DAC STO1 ASRC", NULL, "CLKDET"},
/*Vref*/
{"MICBIAS1", NULL, "Vref1"},
{"MICBIAS2", NULL, "Vref1"},
{"CLKDET SYS", NULL, "CLKDET"},
{"BST1 CBJ", NULL, "IN1P"},
{"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
{"RECMIX1L", NULL, "RECMIX1L Power"},
{"ADC1 L", NULL, "RECMIX1L"},
{"ADC1 L", NULL, "ADC1 L Power"},
{"ADC1 L", NULL, "ADC1 clock"},
{"DMIC L1", NULL, "DMIC CLK"},
{"DMIC L1", NULL, "DMIC1 Power"},
{"DMIC R1", NULL, "DMIC CLK"},
{"DMIC R1", NULL, "DMIC1 Power"},
{"DMIC CLK", NULL, "DMIC ASRC"},
{"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
{"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
{"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
{"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
{"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
{"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
{"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
{"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
{"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
{"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
{"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
{"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
{"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
{"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
{"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
{"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
{"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
{"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
{"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
{"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
{"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
{"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
{"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
{"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
{"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
{"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
{"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
{"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
{"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
{"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
{"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
{"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
{"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
{"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
{"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
{"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
{"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
{"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
{"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
{"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
{"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
{"AIF1TX", NULL, "I2S1"},
{"AIF1TX", NULL, "ADCDAT Mux"},
{"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
{"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
{"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
{"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
{"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
{"AIF2TX", NULL, "ADCDAT Mux"},
{"SDWTX", NULL, "PLL2B"},
{"SDWTX", NULL, "PLL2F"},
{"SDWTX", NULL, "ADCDAT Mux"},
{"IF1 DAC1 L", NULL, "AIF1RX"},
{"IF1 DAC1 L", NULL, "I2S1"},
{"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
{"IF1 DAC1 R", NULL, "AIF1RX"},
{"IF1 DAC1 R", NULL, "I2S1"},
{"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
{"SOUND DAC L", NULL, "SDWRX"},
{"SOUND DAC L", NULL, "DAC Stereo1 Filter"},
{"SOUND DAC L", NULL, "PLL2B"},
{"SOUND DAC L", NULL, "PLL2F"},
{"SOUND DAC R", NULL, "SDWRX"},
{"SOUND DAC R", NULL, "DAC Stereo1 Filter"},
{"SOUND DAC R", NULL, "PLL2B"},
{"SOUND DAC R", NULL, "PLL2F"},
{"DAC L Mux", "IF1", "IF1 DAC1 L"},
{"DAC L Mux", "SOUND", "SOUND DAC L"},
{"DAC R Mux", "IF1", "IF1 DAC1 R"},
{"DAC R Mux", "SOUND", "SOUND DAC R"},
{"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
{"DAC1 MIXL", "DAC1 Switch", "DAC L Mux"},
{"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
{"DAC1 MIXR", "DAC1 Switch", "DAC R Mux"},
{"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
{"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
{"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
{"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
{"DAC L1 Source", "DAC1", "DAC1 MIXL"},
{"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
{"DAC R1 Source", "DAC1", "DAC1 MIXR"},
{"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
{"DAC L1", NULL, "DAC L1 Source"},
{"DAC R1", NULL, "DAC R1 Source"},
{"DAC L1", NULL, "DAC 1 Clock"},
{"DAC R1", NULL, "DAC 1 Clock"},
{"HP Amp", NULL, "DAC L1"},
{"HP Amp", NULL, "DAC R1"},
{"HP Amp", NULL, "HP Amp L"},
{"HP Amp", NULL, "HP Amp R"},
{"HP Amp", NULL, "Capless"},
{"HP Amp", NULL, "Charge Pump"},
{"HP Amp", NULL, "CLKDET SYS"},
{"HP Amp", NULL, "Vref1"},
{"HPO Signal Demux", NULL, "HP Amp"},
{"HPO Legacy", "Legacy", "HPO Signal Demux"},
{"HPO OneBit", "OneBit", "HPO Signal Demux"},
{"HPOL Playback", "Switch", "HPO Legacy"},
{"HPOR Playback", "Switch", "HPO Legacy"},
{"HPOL", NULL, "HPOL Playback"},
{"HPOR", NULL, "HPOR Playback"},
{"HPOL", NULL, "HPO OneBit"},
{"HPOR", NULL, "HPO OneBit"},
};
static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
unsigned int cl, val = 0;
if (tx_mask || rx_mask)
snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
RT5682_TDM_EN, RT5682_TDM_EN);
else
snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
RT5682_TDM_EN, 0);
switch (slots) {
case 4:
val |= RT5682_TDM_TX_CH_4;
val |= RT5682_TDM_RX_CH_4;
break;
case 6:
val |= RT5682_TDM_TX_CH_6;
val |= RT5682_TDM_RX_CH_6;
break;
case 8:
val |= RT5682_TDM_TX_CH_8;
val |= RT5682_TDM_RX_CH_8;
break;
case 2:
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, RT5682_TDM_CTRL,
RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val);
switch (slot_width) {
case 8:
if (tx_mask || rx_mask)
return -EINVAL;
cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8;
break;
case 16:
val = RT5682_TDM_CL_16;
cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16;
break;
case 20:
val = RT5682_TDM_CL_20;
cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20;
break;
case 24:
val = RT5682_TDM_CL_24;
cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24;
break;
case 32:
val = RT5682_TDM_CL_32;
cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
RT5682_TDM_CL_MASK, val);
snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl);
return 0;
}
static int rt5682_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
unsigned int len_1 = 0, len_2 = 0;
int pre_div, frame_size;
rt5682->lrck[dai->id] = params_rate(params);
pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]);
frame_size = snd_soc_params_to_frame_size(params);
if (frame_size < 0) {
dev_err(component->dev, "Unsupported frame size: %d\n",
frame_size);
return -EINVAL;
}
dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
rt5682->lrck[dai->id], pre_div, dai->id);
switch (params_width(params)) {
case 16:
break;
case 20:
len_1 |= RT5682_I2S1_DL_20;
len_2 |= RT5682_I2S2_DL_20;
break;
case 24:
len_1 |= RT5682_I2S1_DL_24;
len_2 |= RT5682_I2S2_DL_24;
break;
case 32:
len_1 |= RT5682_I2S1_DL_32;
len_2 |= RT5682_I2S2_DL_24;
break;
case 8:
len_1 |= RT5682_I2S2_DL_8;
len_2 |= RT5682_I2S2_DL_8;
break;
default:
return -EINVAL;
}
switch (dai->id) {
case RT5682_AIF1:
snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
RT5682_I2S1_DL_MASK, len_1);
if (rt5682->master[RT5682_AIF1]) {
snd_soc_component_update_bits(component,
RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK |
RT5682_I2S_CLK_SRC_MASK,
pre_div << RT5682_I2S_M_DIV_SFT |
(rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
}
if (params_channels(params) == 1) /* mono mode */
snd_soc_component_update_bits(component,
RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
RT5682_I2S1_MONO_EN);
else
snd_soc_component_update_bits(component,
RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
RT5682_I2S1_MONO_DIS);
break;
case RT5682_AIF2:
snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
RT5682_I2S2_DL_MASK, len_2);
if (rt5682->master[RT5682_AIF2]) {
snd_soc_component_update_bits(component,
RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK,
pre_div << RT5682_I2S2_M_PD_SFT);
}
if (params_channels(params) == 1) /* mono mode */
snd_soc_component_update_bits(component,
RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
RT5682_I2S2_MONO_EN);
else
snd_soc_component_update_bits(component,
RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
RT5682_I2S2_MONO_DIS);
break;
default:
dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
return -EINVAL;
}
return 0;
}
static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0, tdm_ctrl = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
rt5682->master[dai->id] = 1;
break;
case SND_SOC_DAIFMT_CBS_CFS:
rt5682->master[dai->id] = 0;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
reg_val |= RT5682_I2S_BP_INV;
tdm_ctrl |= RT5682_TDM_S_BP_INV;
break;
case SND_SOC_DAIFMT_NB_IF:
if (dai->id == RT5682_AIF1)
tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV;
else
return -EINVAL;
break;
case SND_SOC_DAIFMT_IB_IF:
if (dai->id == RT5682_AIF1)
tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV |
RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV;
else
return -EINVAL;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_LEFT_J:
reg_val |= RT5682_I2S_DF_LEFT;
tdm_ctrl |= RT5682_TDM_DF_LEFT;
break;
case SND_SOC_DAIFMT_DSP_A:
reg_val |= RT5682_I2S_DF_PCM_A;
tdm_ctrl |= RT5682_TDM_DF_PCM_A;
break;
case SND_SOC_DAIFMT_DSP_B:
reg_val |= RT5682_I2S_DF_PCM_B;
tdm_ctrl |= RT5682_TDM_DF_PCM_B;
break;
default:
return -EINVAL;
}
switch (dai->id) {
case RT5682_AIF1:
snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
RT5682_I2S_DF_MASK, reg_val);
snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK |
RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK |
RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK,
tdm_ctrl | rt5682->master[dai->id]);
break;
case RT5682_AIF2:
if (rt5682->master[dai->id] == 0)
reg_val |= RT5682_I2S2_MS_S;
snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK |
RT5682_I2S_DF_MASK, reg_val);
break;
default:
dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
return -EINVAL;
}
return 0;
}
static int rt5682_set_component_sysclk(struct snd_soc_component *component,
int clk_id, int source, unsigned int freq, int dir)
{
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0, src = 0;
if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src)
return 0;
switch (clk_id) {
case RT5682_SCLK_S_MCLK:
reg_val |= RT5682_SCLK_SRC_MCLK;
src = RT5682_CLK_SRC_MCLK;
break;
case RT5682_SCLK_S_PLL1:
reg_val |= RT5682_SCLK_SRC_PLL1;
src = RT5682_CLK_SRC_PLL1;
break;
case RT5682_SCLK_S_PLL2:
reg_val |= RT5682_SCLK_SRC_PLL2;
src = RT5682_CLK_SRC_PLL2;
break;
case RT5682_SCLK_S_RCCLK:
reg_val |= RT5682_SCLK_SRC_RCCLK;
src = RT5682_CLK_SRC_RCCLK;
break;
default:
dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
return -EINVAL;
}
snd_soc_component_update_bits(component, RT5682_GLB_CLK,
RT5682_SCLK_SRC_MASK, reg_val);
if (rt5682->master[RT5682_AIF2]) {
snd_soc_component_update_bits(component,
RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK,
src << RT5682_I2S2_SRC_SFT);
}
rt5682->sysclk = freq;
rt5682->sysclk_src = clk_id;
dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
freq, clk_id);
return 0;
}
static int rt5682_set_component_pll(struct snd_soc_component *component,
int pll_id, int source, unsigned int freq_in,
unsigned int freq_out)
{
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
struct rl6231_pll_code pll_code, pll2f_code, pll2b_code;
unsigned int pll2_fout1, pll2_ps_val;
int ret;
if (source == rt5682->pll_src[pll_id] &&
freq_in == rt5682->pll_in[pll_id] &&
freq_out == rt5682->pll_out[pll_id])
return 0;
if (!freq_in || !freq_out) {
dev_dbg(component->dev, "PLL disabled\n");
rt5682->pll_in[pll_id] = 0;
rt5682->pll_out[pll_id] = 0;
snd_soc_component_update_bits(component, RT5682_GLB_CLK,
RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK);
return 0;
}
if (pll_id == RT5682_PLL2) {
switch (source) {
case RT5682_PLL2_S_MCLK:
snd_soc_component_update_bits(component,
RT5682_GLB_CLK, RT5682_PLL2_SRC_MASK,
RT5682_PLL2_SRC_MCLK);
break;
default:
dev_err(component->dev, "Unknown PLL2 Source %d\n",
source);
return -EINVAL;
}
/**
* PLL2 concatenates 2 PLL units.
* We suggest the Fout of the front PLL is 3.84MHz.
*/
pll2_fout1 = 3840000;
ret = rl6231_pll_calc(freq_in, pll2_fout1, &pll2f_code);
if (ret < 0) {
dev_err(component->dev, "Unsupported input clock %d\n",
freq_in);
return ret;
}
dev_dbg(component->dev, "PLL2F: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
freq_in, pll2_fout1,
pll2f_code.m_bp,
(pll2f_code.m_bp ? 0 : pll2f_code.m_code),
pll2f_code.n_code, pll2f_code.k_code);
ret = rl6231_pll_calc(pll2_fout1, freq_out, &pll2b_code);
if (ret < 0) {
dev_err(component->dev, "Unsupported input clock %d\n",
pll2_fout1);
return ret;
}
dev_dbg(component->dev, "PLL2B: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
pll2_fout1, freq_out,
pll2b_code.m_bp,
(pll2b_code.m_bp ? 0 : pll2b_code.m_code),
pll2b_code.n_code, pll2b_code.k_code);
snd_soc_component_write(component, RT5682_PLL2_CTRL_1,
pll2f_code.k_code << RT5682_PLL2F_K_SFT |
pll2b_code.k_code << RT5682_PLL2B_K_SFT |
pll2b_code.m_code);
snd_soc_component_write(component, RT5682_PLL2_CTRL_2,
pll2f_code.m_code << RT5682_PLL2F_M_SFT |
pll2b_code.n_code);
snd_soc_component_write(component, RT5682_PLL2_CTRL_3,
pll2f_code.n_code << RT5682_PLL2F_N_SFT);
if (freq_out == 22579200)
pll2_ps_val = 1 << RT5682_PLL2B_SEL_PS_SFT;
else
pll2_ps_val = 1 << RT5682_PLL2B_PS_BYP_SFT;
snd_soc_component_update_bits(component, RT5682_PLL2_CTRL_4,
RT5682_PLL2B_SEL_PS_MASK | RT5682_PLL2B_PS_BYP_MASK |
RT5682_PLL2B_M_BP_MASK | RT5682_PLL2F_M_BP_MASK | 0xf,
pll2_ps_val |
(pll2b_code.m_bp ? 1 : 0) << RT5682_PLL2B_M_BP_SFT |
(pll2f_code.m_bp ? 1 : 0) << RT5682_PLL2F_M_BP_SFT |
0xf);
} else {
switch (source) {
case RT5682_PLL1_S_MCLK:
snd_soc_component_update_bits(component,
RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
RT5682_PLL1_SRC_MCLK);
break;
case RT5682_PLL1_S_BCLK1:
snd_soc_component_update_bits(component,
RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
RT5682_PLL1_SRC_BCLK1);
break;
default:
dev_err(component->dev, "Unknown PLL1 Source %d\n",
source);
return -EINVAL;
}
ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
if (ret < 0) {
dev_err(component->dev, "Unsupported input clock %d\n",
freq_in);
return ret;
}
dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
pll_code.n_code, pll_code.k_code);
snd_soc_component_write(component, RT5682_PLL_CTRL_1,
(pll_code.n_code << RT5682_PLL_N_SFT) | pll_code.k_code);
snd_soc_component_write(component, RT5682_PLL_CTRL_2,
((pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT) |
((pll_code.m_bp << RT5682_PLL_M_BP_SFT) | RT5682_PLL_RST));
}
rt5682->pll_in[pll_id] = freq_in;
rt5682->pll_out[pll_id] = freq_out;
rt5682->pll_src[pll_id] = source;
return 0;
}
static int rt5682_set_bclk1_ratio(struct snd_soc_dai *dai, unsigned int ratio)
{
struct snd_soc_component *component = dai->component;
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
rt5682->bclk[dai->id] = ratio;
switch (ratio) {
case 256:
snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_256);
break;
case 128:
snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_128);
break;
case 64:
snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_64);
break;
case 32:
snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_32);
break;
default:
dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio);
return -EINVAL;
}
return 0;
}
static int rt5682_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio)
{
struct snd_soc_component *component = dai->component;
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
rt5682->bclk[dai->id] = ratio;
switch (ratio) {
case 64:
snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
RT5682_I2S2_BCLK_MS2_MASK,
RT5682_I2S2_BCLK_MS2_64);
break;
case 32:
snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
RT5682_I2S2_BCLK_MS2_MASK,
RT5682_I2S2_BCLK_MS2_32);
break;
default:
dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio);
return -EINVAL;
}
return 0;
}
static int rt5682_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_PREPARE:
regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
RT5682_PWR_BG, RT5682_PWR_BG);
regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO,
RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO);
break;
case SND_SOC_BIAS_STANDBY:
regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL);
break;
case SND_SOC_BIAS_OFF:
regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0);
regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
RT5682_PWR_BG, 0);
break;
case SND_SOC_BIAS_ON:
break;
}
return 0;
}
#ifdef CONFIG_COMMON_CLK
#define CLK_PLL2_FIN 48000000
#define CLK_48 48000
#define CLK_44 44100
static bool rt5682_clk_check(struct rt5682_priv *rt5682)
{
if (!rt5682->master[RT5682_AIF1]) {
dev_dbg(rt5682->i2c_dev, "sysclk/dai not set correctly\n");
return false;
}
return true;
}
static int rt5682_wclk_prepare(struct clk_hw *hw)
{
struct rt5682_priv *rt5682 =
container_of(hw, struct rt5682_priv,
dai_clks_hw[RT5682_DAI_WCLK_IDX]);
struct snd_soc_component *component;
struct snd_soc_dapm_context *dapm;
if (!rt5682_clk_check(rt5682))
return -EINVAL;
component = rt5682->component;
dapm = snd_soc_component_get_dapm(component);
snd_soc_dapm_mutex_lock(dapm);
snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS");
snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
RT5682_PWR_MB, RT5682_PWR_MB);
snd_soc_dapm_force_enable_pin_unlocked(dapm, "Vref2");
snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
RT5682_PWR_VREF2 | RT5682_PWR_FV2,
RT5682_PWR_VREF2);
usleep_range(55000, 60000);
snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
RT5682_PWR_FV2, RT5682_PWR_FV2);
snd_soc_dapm_force_enable_pin_unlocked(dapm, "I2S1");
snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2F");
snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2B");
snd_soc_dapm_sync_unlocked(dapm);
snd_soc_dapm_mutex_unlock(dapm);
return 0;
}
static void rt5682_wclk_unprepare(struct clk_hw *hw)
{
struct rt5682_priv *rt5682 =
container_of(hw, struct rt5682_priv,
dai_clks_hw[RT5682_DAI_WCLK_IDX]);
struct snd_soc_component *component;
struct snd_soc_dapm_context *dapm;
if (!rt5682_clk_check(rt5682))
return;
component = rt5682->component;
dapm = snd_soc_component_get_dapm(component);
snd_soc_dapm_mutex_lock(dapm);
snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS");
snd_soc_dapm_disable_pin_unlocked(dapm, "Vref2");
if (!rt5682->jack_type)
snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
RT5682_PWR_VREF2 | RT5682_PWR_FV2 |
RT5682_PWR_MB, 0);
snd_soc_dapm_disable_pin_unlocked(dapm, "I2S1");
snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2F");
snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2B");
snd_soc_dapm_sync_unlocked(dapm);
snd_soc_dapm_mutex_unlock(dapm);
}
static unsigned long rt5682_wclk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct rt5682_priv *rt5682 =
container_of(hw, struct rt5682_priv,
dai_clks_hw[RT5682_DAI_WCLK_IDX]);
const char * const clk_name = clk_hw_get_name(hw);
if (!rt5682_clk_check(rt5682))
return 0;
/*
* Only accept to set wclk rate to 44.1k or 48kHz.
*/
if (rt5682->lrck[RT5682_AIF1] != CLK_48 &&
rt5682->lrck[RT5682_AIF1] != CLK_44) {
dev_warn(rt5682->i2c_dev, "%s: clk %s only support %d or %d Hz output\n",
__func__, clk_name, CLK_44, CLK_48);
return 0;
}
return rt5682->lrck[RT5682_AIF1];
}
static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
struct rt5682_priv *rt5682 =
container_of(hw, struct rt5682_priv,
dai_clks_hw[RT5682_DAI_WCLK_IDX]);
const char * const clk_name = clk_hw_get_name(hw);
if (!rt5682_clk_check(rt5682))
return -EINVAL;
/*
* Only accept to set wclk rate to 44.1k or 48kHz.
* It will force to 48kHz if not both.
*/
if (rate != CLK_48 && rate != CLK_44) {
dev_warn(rt5682->i2c_dev, "%s: clk %s only support %d or %d Hz output\n",
__func__, clk_name, CLK_44, CLK_48);
rate = CLK_48;
}
return rate;
}
static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct rt5682_priv *rt5682 =
container_of(hw, struct rt5682_priv,
dai_clks_hw[RT5682_DAI_WCLK_IDX]);
struct snd_soc_component *component;
struct clk_hw *parent_hw;
const char * const clk_name = clk_hw_get_name(hw);
int pre_div;
unsigned int clk_pll2_out;
if (!rt5682_clk_check(rt5682))
return -EINVAL;
component = rt5682->component;
/*
* Whether the wclk's parent clk (mclk) exists or not, please ensure
* it is fixed or set to 48MHz before setting wclk rate. It's a
* temporary limitation. Only accept 48MHz clk as the clk provider.
*
* It will set the codec anyway by assuming mclk is 48MHz.
*/
parent_hw = clk_hw_get_parent(hw);
if (!parent_hw)
dev_warn(rt5682->i2c_dev,
"Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n",
CLK_PLL2_FIN);
if (parent_rate != CLK_PLL2_FIN)
dev_warn(rt5682->i2c_dev, "clk %s only support %d Hz input\n",
clk_name, CLK_PLL2_FIN);
/*
* To achieve the rate conversion from 48MHz to 44.1k or 48kHz,
* PLL2 is needed.
*/
clk_pll2_out = rate * 512;
rt5682_set_component_pll(component, RT5682_PLL2, RT5682_PLL2_S_MCLK,
CLK_PLL2_FIN, clk_pll2_out);
rt5682_set_component_sysclk(component, RT5682_SCLK_S_PLL2, 0,
clk_pll2_out, SND_SOC_CLOCK_IN);
rt5682->lrck[RT5682_AIF1] = rate;
pre_div = rl6231_get_clk_info(rt5682->sysclk, rate);
snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
RT5682_I2S_M_DIV_MASK | RT5682_I2S_CLK_SRC_MASK,
pre_div << RT5682_I2S_M_DIV_SFT |
(rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
return 0;
}
static unsigned long rt5682_bclk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct rt5682_priv *rt5682 =
container_of(hw, struct rt5682_priv,
dai_clks_hw[RT5682_DAI_BCLK_IDX]);
unsigned int bclks_per_wclk;
regmap_read(rt5682->regmap, RT5682_TDM_TCON_CTRL, &bclks_per_wclk);
switch (bclks_per_wclk & RT5682_TDM_BCLK_MS1_MASK) {
case RT5682_TDM_BCLK_MS1_256:
return parent_rate * 256;
case RT5682_TDM_BCLK_MS1_128:
return parent_rate * 128;
case RT5682_TDM_BCLK_MS1_64:
return parent_rate * 64;
case RT5682_TDM_BCLK_MS1_32:
return parent_rate * 32;
default:
return 0;
}
}
static unsigned long rt5682_bclk_get_factor(unsigned long rate,
unsigned long parent_rate)
{
unsigned long factor;
factor = rate / parent_rate;
if (factor < 64)
return 32;
else if (factor < 128)
return 64;
else if (factor < 256)
return 128;
else
return 256;
}
static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
struct rt5682_priv *rt5682 =
container_of(hw, struct rt5682_priv,
dai_clks_hw[RT5682_DAI_BCLK_IDX]);
unsigned long factor;
if (!*parent_rate || !rt5682_clk_check(rt5682))
return -EINVAL;
/*
* BCLK rates are set as a multiplier of WCLK in HW.
* We don't allow changing the parent WCLK. We just do
* some rounding down based on the parent WCLK rate
* and find the appropriate multiplier of BCLK to
* get the rounded down BCLK value.
*/
factor = rt5682_bclk_get_factor(rate, *parent_rate);
return *parent_rate * factor;
}
static int rt5682_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct rt5682_priv *rt5682 =
container_of(hw, struct rt5682_priv,
dai_clks_hw[RT5682_DAI_BCLK_IDX]);
struct snd_soc_component *component;
struct snd_soc_dai *dai;
unsigned long factor;
if (!rt5682_clk_check(rt5682))
return -EINVAL;
component = rt5682->component;
factor = rt5682_bclk_get_factor(rate, parent_rate);
for_each_component_dais(component, dai)
if (dai->id == RT5682_AIF1)
return rt5682_set_bclk1_ratio(dai, factor);
dev_err(rt5682->i2c_dev, "dai %d not found in component\n",
RT5682_AIF1);
return -ENODEV;
}
static const struct clk_ops rt5682_dai_clk_ops[RT5682_DAI_NUM_CLKS] = {
[RT5682_DAI_WCLK_IDX] = {
.prepare = rt5682_wclk_prepare,
.unprepare = rt5682_wclk_unprepare,
.recalc_rate = rt5682_wclk_recalc_rate,
.round_rate = rt5682_wclk_round_rate,
.set_rate = rt5682_wclk_set_rate,
},
[RT5682_DAI_BCLK_IDX] = {
.recalc_rate = rt5682_bclk_recalc_rate,
.round_rate = rt5682_bclk_round_rate,
.set_rate = rt5682_bclk_set_rate,
},
};
int rt5682_register_dai_clks(struct rt5682_priv *rt5682)
{
struct device *dev = rt5682->i2c_dev;
struct rt5682_platform_data *pdata = &rt5682->pdata;
struct clk_hw *dai_clk_hw;
int i, ret;
for (i = 0; i < RT5682_DAI_NUM_CLKS; ++i) {
struct clk_init_data init = { };
const struct clk_hw *parent;
dai_clk_hw = &rt5682->dai_clks_hw[i];
switch (i) {
case RT5682_DAI_WCLK_IDX:
/* Make MCLK the parent of WCLK */
if (rt5682->mclk) {
parent = __clk_get_hw(rt5682->mclk);
init.parent_hws = &parent;
init.num_parents = 1;
}
break;
case RT5682_DAI_BCLK_IDX:
/* Make WCLK the parent of BCLK */
parent = &rt5682->dai_clks_hw[RT5682_DAI_WCLK_IDX];
init.parent_hws = &parent;
init.num_parents = 1;
break;
default:
dev_err(dev, "Invalid clock index\n");
return -EINVAL;
}
init.name = pdata->dai_clk_names[i];
init.ops = &rt5682_dai_clk_ops[i];
init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE;
dai_clk_hw->init = &init;
ret = devm_clk_hw_register(dev, dai_clk_hw);
if (ret) {
dev_warn(dev, "Failed to register %s: %d\n",
init.name, ret);
return ret;
}
if (dev->of_node) {
devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
dai_clk_hw);
} else {
ret = devm_clk_hw_register_clkdev(dev, dai_clk_hw,
init.name,
dev_name(dev));
if (ret)
return ret;
}
}
return 0;
}
EXPORT_SYMBOL_GPL(rt5682_register_dai_clks);
#endif /* CONFIG_COMMON_CLK */
static int rt5682_probe(struct snd_soc_component *component)
{
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
struct sdw_slave *slave;
unsigned long time;
struct snd_soc_dapm_context *dapm = &component->dapm;
rt5682->component = component;
if (rt5682->is_sdw) {
slave = rt5682->slave;
time = wait_for_completion_timeout(
&slave->initialization_complete,
msecs_to_jiffies(RT5682_PROBE_TIMEOUT));
if (!time) {
dev_err(&slave->dev, "Initialization not complete, timed out\n");
return -ETIMEDOUT;
}
}
snd_soc_dapm_disable_pin(dapm, "MICBIAS");
snd_soc_dapm_disable_pin(dapm, "Vref2");
snd_soc_dapm_sync(dapm);
return 0;
}
static void rt5682_remove(struct snd_soc_component *component)
{
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
rt5682_reset(rt5682);
}
#ifdef CONFIG_PM
static int rt5682_suspend(struct snd_soc_component *component)
{
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
unsigned int val;
if (rt5682->is_sdw)
return 0;
if (rt5682->irq)
disable_irq(rt5682->irq);
cancel_delayed_work_sync(&rt5682->jack_detect_work);
cancel_delayed_work_sync(&rt5682->jd_check_work);
if (rt5682->hs_jack && (rt5682->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) {
val = snd_soc_component_read(component,
RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
switch (val) {
case 0x1:
snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
RT5682_SAR_SEL_MB1_MASK | RT5682_SAR_SEL_MB2_MASK,
RT5682_SAR_SEL_MB1_NOSEL | RT5682_SAR_SEL_MB2_SEL);
break;
case 0x2:
snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
RT5682_SAR_SEL_MB1_MASK | RT5682_SAR_SEL_MB2_MASK,
RT5682_SAR_SEL_MB1_SEL | RT5682_SAR_SEL_MB2_NOSEL);
break;
default:
break;
}
/* enter SAR ADC power saving mode */
snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
RT5682_SAR_BUTT_DET_MASK | RT5682_SAR_BUTDET_MODE_MASK |
RT5682_SAR_SEL_MB1_MB2_MASK, 0);
usleep_range(5000, 6000);
snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
RT5682_MB1_PATH_MASK | RT5682_MB2_PATH_MASK,
RT5682_CTRL_MB1_REG | RT5682_CTRL_MB2_REG);
usleep_range(10000, 12000);
snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
RT5682_SAR_BUTT_DET_MASK | RT5682_SAR_BUTDET_MODE_MASK,
RT5682_SAR_BUTT_DET_EN | RT5682_SAR_BUTDET_POW_SAV);
snd_soc_component_update_bits(component, RT5682_HP_CHARGE_PUMP_1,
RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0);
}
regcache_cache_only(rt5682->regmap, true);
regcache_mark_dirty(rt5682->regmap);
return 0;
}
static int rt5682_resume(struct snd_soc_component *component)
{
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
if (rt5682->is_sdw)
return 0;
regcache_cache_only(rt5682->regmap, false);
regcache_sync(rt5682->regmap);
if (rt5682->hs_jack && (rt5682->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) {
snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
RT5682_SAR_BUTDET_MODE_MASK | RT5682_SAR_SEL_MB1_MB2_MASK,
RT5682_SAR_BUTDET_POW_NORM | RT5682_SAR_SEL_MB1_MB2_AUTO);
usleep_range(5000, 6000);
snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
RT5682_MB1_PATH_MASK | RT5682_MB2_PATH_MASK,
RT5682_CTRL_MB1_FSM | RT5682_CTRL_MB2_FSM);
snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
RT5682_PWR_CBJ, RT5682_PWR_CBJ);
}
rt5682->jack_type = 0;
mod_delayed_work(system_power_efficient_wq,
&rt5682->jack_detect_work, msecs_to_jiffies(0));
if (rt5682->irq)
enable_irq(rt5682->irq);
return 0;
}
#else
#define rt5682_suspend NULL
#define rt5682_resume NULL
#endif
const struct snd_soc_dai_ops rt5682_aif1_dai_ops = {
.hw_params = rt5682_hw_params,
.set_fmt = rt5682_set_dai_fmt,
.set_tdm_slot = rt5682_set_tdm_slot,
.set_bclk_ratio = rt5682_set_bclk1_ratio,
};
EXPORT_SYMBOL_GPL(rt5682_aif1_dai_ops);
const struct snd_soc_dai_ops rt5682_aif2_dai_ops = {
.hw_params = rt5682_hw_params,
.set_fmt = rt5682_set_dai_fmt,
.set_bclk_ratio = rt5682_set_bclk2_ratio,
};
EXPORT_SYMBOL_GPL(rt5682_aif2_dai_ops);
const struct snd_soc_component_driver rt5682_soc_component_dev = {
.probe = rt5682_probe,
.remove = rt5682_remove,
.suspend = rt5682_suspend,
.resume = rt5682_resume,
.set_bias_level = rt5682_set_bias_level,
.controls = rt5682_snd_controls,
.num_controls = ARRAY_SIZE(rt5682_snd_controls),
.dapm_widgets = rt5682_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets),
.dapm_routes = rt5682_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes),
.set_sysclk = rt5682_set_component_sysclk,
.set_pll = rt5682_set_component_pll,
.set_jack = rt5682_set_jack_detect,
.use_pmdown_time = 1,
.endianness = 1,
};
EXPORT_SYMBOL_GPL(rt5682_soc_component_dev);
int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev)
{
device_property_read_u32(dev, "realtek,dmic1-data-pin",
&rt5682->pdata.dmic1_data_pin);
device_property_read_u32(dev, "realtek,dmic1-clk-pin",
&rt5682->pdata.dmic1_clk_pin);
device_property_read_u32(dev, "realtek,jd-src",
&rt5682->pdata.jd_src);
device_property_read_u32(dev, "realtek,btndet-delay",
&rt5682->pdata.btndet_delay);
device_property_read_u32(dev, "realtek,dmic-clk-rate-hz",
&rt5682->pdata.dmic_clk_rate);
device_property_read_u32(dev, "realtek,dmic-delay-ms",
&rt5682->pdata.dmic_delay);
if (device_property_read_string_array(dev, "clock-output-names",
rt5682->pdata.dai_clk_names,
RT5682_DAI_NUM_CLKS) < 0)
dev_warn(dev, "Using default DAI clk names: %s, %s\n",
rt5682->pdata.dai_clk_names[RT5682_DAI_WCLK_IDX],
rt5682->pdata.dai_clk_names[RT5682_DAI_BCLK_IDX]);
rt5682->pdata.dmic_clk_driving_high = device_property_read_bool(dev,
"realtek,dmic-clk-driving-high");
return 0;
}
EXPORT_SYMBOL_GPL(rt5682_parse_dt);
int rt5682_get_ldo1(struct rt5682_priv *rt5682, struct device *dev)
{
rt5682->ldo1_en = devm_gpiod_get_optional(dev,
"realtek,ldo1-en",
GPIOD_OUT_HIGH);
if (IS_ERR(rt5682->ldo1_en)) {
dev_err(dev, "Fail gpio request ldo1_en\n");
return PTR_ERR(rt5682->ldo1_en);
}
return 0;
}
EXPORT_SYMBOL_GPL(rt5682_get_ldo1);
void rt5682_calibrate(struct rt5682_priv *rt5682)
{
int value, count;
mutex_lock(&rt5682->calibrate_mutex);
rt5682_reset(rt5682);
regmap_write(rt5682->regmap, RT5682_I2C_CTRL, 0x000f);
regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af);
usleep_range(15000, 20000);
regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af);
regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300);
regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000);
regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100);
regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800);
regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000);
regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005);
regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c);
regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d);
regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321);
regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004);
regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1);
regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311);
regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00);
for (count = 0; count < 60; count++) {
regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value);
if (!(value & 0x8000))
break;
usleep_range(10000, 10005);
}
if (count >= 60)
dev_err(rt5682->component->dev, "HP Calibration Failure\n");
/* restore settings */
regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x002f);
regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080);
regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000);
regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000);
regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000);
regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005);
regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4);
regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0c0c);
mutex_unlock(&rt5682->calibrate_mutex);
}
EXPORT_SYMBOL_GPL(rt5682_calibrate);
MODULE_DESCRIPTION("ASoC RT5682 driver");
MODULE_AUTHOR("Bard Liao <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/rt5682.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ALSA SoC codec for HDMI encoder drivers
* Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com/
* Author: Jyri Sarha <[email protected]>
*/
#include <linux/module.h>
#include <linux/string.h>
#include <sound/core.h>
#include <sound/jack.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <sound/pcm_drm_eld.h>
#include <sound/hdmi-codec.h>
#include <sound/pcm_iec958.h>
#include <drm/drm_crtc.h> /* This is only to get MAX_ELD_BYTES */
#define HDMI_CODEC_CHMAP_IDX_UNKNOWN -1
/*
* CEA speaker placement for HDMI 1.4:
*
* FL FLC FC FRC FR FRW
*
* LFE
*
* RL RLC RC RRC RR
*
* Speaker placement has to be extended to support HDMI 2.0
*/
enum hdmi_codec_cea_spk_placement {
FL = BIT(0), /* Front Left */
FC = BIT(1), /* Front Center */
FR = BIT(2), /* Front Right */
FLC = BIT(3), /* Front Left Center */
FRC = BIT(4), /* Front Right Center */
RL = BIT(5), /* Rear Left */
RC = BIT(6), /* Rear Center */
RR = BIT(7), /* Rear Right */
RLC = BIT(8), /* Rear Left Center */
RRC = BIT(9), /* Rear Right Center */
LFE = BIT(10), /* Low Frequency Effect */
};
/*
* cea Speaker allocation structure
*/
struct hdmi_codec_cea_spk_alloc {
const int ca_id;
unsigned int n_ch;
unsigned long mask;
};
/* Channel maps stereo HDMI */
static const struct snd_pcm_chmap_elem hdmi_codec_stereo_chmaps[] = {
{ .channels = 2,
.map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
{ }
};
/* Channel maps for multi-channel playbacks, up to 8 n_ch */
static const struct snd_pcm_chmap_elem hdmi_codec_8ch_chmaps[] = {
{ .channels = 2, /* CA_ID 0x00 */
.map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
{ .channels = 4, /* CA_ID 0x01 */
.map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, SNDRV_CHMAP_LFE,
SNDRV_CHMAP_NA } },
{ .channels = 4, /* CA_ID 0x02 */
.map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, SNDRV_CHMAP_NA,
SNDRV_CHMAP_FC } },
{ .channels = 4, /* CA_ID 0x03 */
.map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, SNDRV_CHMAP_LFE,
SNDRV_CHMAP_FC } },
{ .channels = 6, /* CA_ID 0x04 */
.map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, SNDRV_CHMAP_NA,
SNDRV_CHMAP_NA, SNDRV_CHMAP_RC, SNDRV_CHMAP_NA } },
{ .channels = 6, /* CA_ID 0x05 */
.map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, SNDRV_CHMAP_LFE,
SNDRV_CHMAP_NA, SNDRV_CHMAP_RC, SNDRV_CHMAP_NA } },
{ .channels = 6, /* CA_ID 0x06 */
.map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, SNDRV_CHMAP_NA,
SNDRV_CHMAP_FC, SNDRV_CHMAP_RC, SNDRV_CHMAP_NA } },
{ .channels = 6, /* CA_ID 0x07 */
.map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, SNDRV_CHMAP_LFE,
SNDRV_CHMAP_FC, SNDRV_CHMAP_RC, SNDRV_CHMAP_NA } },
{ .channels = 6, /* CA_ID 0x08 */
.map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, SNDRV_CHMAP_NA,
SNDRV_CHMAP_NA, SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
{ .channels = 6, /* CA_ID 0x09 */
.map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, SNDRV_CHMAP_LFE,
SNDRV_CHMAP_NA, SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
{ .channels = 6, /* CA_ID 0x0A */
.map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, SNDRV_CHMAP_NA,
SNDRV_CHMAP_FC, SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
{ .channels = 6, /* CA_ID 0x0B */
.map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, SNDRV_CHMAP_LFE,
SNDRV_CHMAP_FC, SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
{ .channels = 8, /* CA_ID 0x0C */
.map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, SNDRV_CHMAP_NA,
SNDRV_CHMAP_NA, SNDRV_CHMAP_RL, SNDRV_CHMAP_RR,
SNDRV_CHMAP_RC, SNDRV_CHMAP_NA } },
{ .channels = 8, /* CA_ID 0x0D */
.map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, SNDRV_CHMAP_LFE,
SNDRV_CHMAP_NA, SNDRV_CHMAP_RL, SNDRV_CHMAP_RR,
SNDRV_CHMAP_RC, SNDRV_CHMAP_NA } },
{ .channels = 8, /* CA_ID 0x0E */
.map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, SNDRV_CHMAP_NA,
SNDRV_CHMAP_FC, SNDRV_CHMAP_RL, SNDRV_CHMAP_RR,
SNDRV_CHMAP_RC, SNDRV_CHMAP_NA } },
{ .channels = 8, /* CA_ID 0x0F */
.map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, SNDRV_CHMAP_LFE,
SNDRV_CHMAP_FC, SNDRV_CHMAP_RL, SNDRV_CHMAP_RR,
SNDRV_CHMAP_RC, SNDRV_CHMAP_NA } },
{ .channels = 8, /* CA_ID 0x10 */
.map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, SNDRV_CHMAP_NA,
SNDRV_CHMAP_NA, SNDRV_CHMAP_RL, SNDRV_CHMAP_RR,
SNDRV_CHMAP_RLC, SNDRV_CHMAP_RRC } },
{ .channels = 8, /* CA_ID 0x11 */
.map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, SNDRV_CHMAP_LFE,
SNDRV_CHMAP_NA, SNDRV_CHMAP_RL, SNDRV_CHMAP_RR,
SNDRV_CHMAP_RLC, SNDRV_CHMAP_RRC } },
{ .channels = 8, /* CA_ID 0x12 */
.map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, SNDRV_CHMAP_NA,
SNDRV_CHMAP_FC, SNDRV_CHMAP_RL, SNDRV_CHMAP_RR,
SNDRV_CHMAP_RLC, SNDRV_CHMAP_RRC } },
{ .channels = 8, /* CA_ID 0x13 */
.map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, SNDRV_CHMAP_LFE,
SNDRV_CHMAP_FC, SNDRV_CHMAP_RL, SNDRV_CHMAP_RR,
SNDRV_CHMAP_RLC, SNDRV_CHMAP_RRC } },
{ .channels = 8, /* CA_ID 0x14 */
.map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, SNDRV_CHMAP_NA,
SNDRV_CHMAP_NA, SNDRV_CHMAP_NA, SNDRV_CHMAP_NA,
SNDRV_CHMAP_FLC, SNDRV_CHMAP_FRC } },
{ .channels = 8, /* CA_ID 0x15 */
.map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, SNDRV_CHMAP_LFE,
SNDRV_CHMAP_NA, SNDRV_CHMAP_NA, SNDRV_CHMAP_NA,
SNDRV_CHMAP_FLC, SNDRV_CHMAP_FRC } },
{ .channels = 8, /* CA_ID 0x16 */
.map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, SNDRV_CHMAP_NA,
SNDRV_CHMAP_FC, SNDRV_CHMAP_NA, SNDRV_CHMAP_NA,
SNDRV_CHMAP_FLC, SNDRV_CHMAP_FRC } },
{ .channels = 8, /* CA_ID 0x17 */
.map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, SNDRV_CHMAP_LFE,
SNDRV_CHMAP_FC, SNDRV_CHMAP_NA, SNDRV_CHMAP_NA,
SNDRV_CHMAP_FLC, SNDRV_CHMAP_FRC } },
{ .channels = 8, /* CA_ID 0x18 */
.map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, SNDRV_CHMAP_NA,
SNDRV_CHMAP_NA, SNDRV_CHMAP_NA, SNDRV_CHMAP_NA,
SNDRV_CHMAP_FLC, SNDRV_CHMAP_FRC } },
{ .channels = 8, /* CA_ID 0x19 */
.map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, SNDRV_CHMAP_LFE,
SNDRV_CHMAP_NA, SNDRV_CHMAP_NA, SNDRV_CHMAP_NA,
SNDRV_CHMAP_FLC, SNDRV_CHMAP_FRC } },
{ .channels = 8, /* CA_ID 0x1A */
.map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, SNDRV_CHMAP_NA,
SNDRV_CHMAP_FC, SNDRV_CHMAP_NA, SNDRV_CHMAP_NA,
SNDRV_CHMAP_FLC, SNDRV_CHMAP_FRC } },
{ .channels = 8, /* CA_ID 0x1B */
.map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, SNDRV_CHMAP_LFE,
SNDRV_CHMAP_FC, SNDRV_CHMAP_NA, SNDRV_CHMAP_NA,
SNDRV_CHMAP_FLC, SNDRV_CHMAP_FRC } },
{ .channels = 8, /* CA_ID 0x1C */
.map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, SNDRV_CHMAP_NA,
SNDRV_CHMAP_NA, SNDRV_CHMAP_NA, SNDRV_CHMAP_NA,
SNDRV_CHMAP_FLC, SNDRV_CHMAP_FRC } },
{ .channels = 8, /* CA_ID 0x1D */
.map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, SNDRV_CHMAP_LFE,
SNDRV_CHMAP_NA, SNDRV_CHMAP_NA, SNDRV_CHMAP_NA,
SNDRV_CHMAP_FLC, SNDRV_CHMAP_FRC } },
{ .channels = 8, /* CA_ID 0x1E */
.map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, SNDRV_CHMAP_NA,
SNDRV_CHMAP_FC, SNDRV_CHMAP_NA, SNDRV_CHMAP_NA,
SNDRV_CHMAP_FLC, SNDRV_CHMAP_FRC } },
{ .channels = 8, /* CA_ID 0x1F */
.map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, SNDRV_CHMAP_LFE,
SNDRV_CHMAP_FC, SNDRV_CHMAP_NA, SNDRV_CHMAP_NA,
SNDRV_CHMAP_FLC, SNDRV_CHMAP_FRC } },
{ }
};
/*
* hdmi_codec_channel_alloc: speaker configuration available for CEA
*
* This is an ordered list that must match with hdmi_codec_8ch_chmaps struct
* The preceding ones have better chances to be selected by
* hdmi_codec_get_ch_alloc_table_idx().
*/
static const struct hdmi_codec_cea_spk_alloc hdmi_codec_channel_alloc[] = {
{ .ca_id = 0x00, .n_ch = 2,
.mask = FL | FR},
/* 2.1 */
{ .ca_id = 0x01, .n_ch = 4,
.mask = FL | FR | LFE},
/* Dolby Surround */
{ .ca_id = 0x02, .n_ch = 4,
.mask = FL | FR | FC },
/* surround51 */
{ .ca_id = 0x0b, .n_ch = 6,
.mask = FL | FR | LFE | FC | RL | RR},
/* surround40 */
{ .ca_id = 0x08, .n_ch = 6,
.mask = FL | FR | RL | RR },
/* surround41 */
{ .ca_id = 0x09, .n_ch = 6,
.mask = FL | FR | LFE | RL | RR },
/* surround50 */
{ .ca_id = 0x0a, .n_ch = 6,
.mask = FL | FR | FC | RL | RR },
/* 6.1 */
{ .ca_id = 0x0f, .n_ch = 8,
.mask = FL | FR | LFE | FC | RL | RR | RC },
/* surround71 */
{ .ca_id = 0x13, .n_ch = 8,
.mask = FL | FR | LFE | FC | RL | RR | RLC | RRC },
/* others */
{ .ca_id = 0x03, .n_ch = 8,
.mask = FL | FR | LFE | FC },
{ .ca_id = 0x04, .n_ch = 8,
.mask = FL | FR | RC},
{ .ca_id = 0x05, .n_ch = 8,
.mask = FL | FR | LFE | RC },
{ .ca_id = 0x06, .n_ch = 8,
.mask = FL | FR | FC | RC },
{ .ca_id = 0x07, .n_ch = 8,
.mask = FL | FR | LFE | FC | RC },
{ .ca_id = 0x0c, .n_ch = 8,
.mask = FL | FR | RC | RL | RR },
{ .ca_id = 0x0d, .n_ch = 8,
.mask = FL | FR | LFE | RL | RR | RC },
{ .ca_id = 0x0e, .n_ch = 8,
.mask = FL | FR | FC | RL | RR | RC },
{ .ca_id = 0x10, .n_ch = 8,
.mask = FL | FR | RL | RR | RLC | RRC },
{ .ca_id = 0x11, .n_ch = 8,
.mask = FL | FR | LFE | RL | RR | RLC | RRC },
{ .ca_id = 0x12, .n_ch = 8,
.mask = FL | FR | FC | RL | RR | RLC | RRC },
{ .ca_id = 0x14, .n_ch = 8,
.mask = FL | FR | FLC | FRC },
{ .ca_id = 0x15, .n_ch = 8,
.mask = FL | FR | LFE | FLC | FRC },
{ .ca_id = 0x16, .n_ch = 8,
.mask = FL | FR | FC | FLC | FRC },
{ .ca_id = 0x17, .n_ch = 8,
.mask = FL | FR | LFE | FC | FLC | FRC },
{ .ca_id = 0x18, .n_ch = 8,
.mask = FL | FR | RC | FLC | FRC },
{ .ca_id = 0x19, .n_ch = 8,
.mask = FL | FR | LFE | RC | FLC | FRC },
{ .ca_id = 0x1a, .n_ch = 8,
.mask = FL | FR | RC | FC | FLC | FRC },
{ .ca_id = 0x1b, .n_ch = 8,
.mask = FL | FR | LFE | RC | FC | FLC | FRC },
{ .ca_id = 0x1c, .n_ch = 8,
.mask = FL | FR | RL | RR | FLC | FRC },
{ .ca_id = 0x1d, .n_ch = 8,
.mask = FL | FR | LFE | RL | RR | FLC | FRC },
{ .ca_id = 0x1e, .n_ch = 8,
.mask = FL | FR | FC | RL | RR | FLC | FRC },
{ .ca_id = 0x1f, .n_ch = 8,
.mask = FL | FR | LFE | FC | RL | RR | FLC | FRC },
};
struct hdmi_codec_priv {
struct hdmi_codec_pdata hcd;
uint8_t eld[MAX_ELD_BYTES];
struct snd_pcm_chmap *chmap_info;
unsigned int chmap_idx;
struct mutex lock;
bool busy;
struct snd_soc_jack *jack;
unsigned int jack_status;
u8 iec_status[AES_IEC958_STATUS_SIZE];
};
static const struct snd_soc_dapm_widget hdmi_widgets[] = {
SND_SOC_DAPM_OUTPUT("TX"),
SND_SOC_DAPM_OUTPUT("RX"),
};
enum {
DAI_ID_I2S = 0,
DAI_ID_SPDIF,
};
static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
uinfo->count = sizeof_field(struct hdmi_codec_priv, eld);
return 0;
}
static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct hdmi_codec_priv *hcp = snd_soc_component_get_drvdata(component);
memcpy(ucontrol->value.bytes.data, hcp->eld, sizeof(hcp->eld));
return 0;
}
static unsigned long hdmi_codec_spk_mask_from_alloc(int spk_alloc)
{
int i;
static const unsigned long hdmi_codec_eld_spk_alloc_bits[] = {
[0] = FL | FR, [1] = LFE, [2] = FC, [3] = RL | RR,
[4] = RC, [5] = FLC | FRC, [6] = RLC | RRC,
};
unsigned long spk_mask = 0;
for (i = 0; i < ARRAY_SIZE(hdmi_codec_eld_spk_alloc_bits); i++) {
if (spk_alloc & (1 << i))
spk_mask |= hdmi_codec_eld_spk_alloc_bits[i];
}
return spk_mask;
}
static void hdmi_codec_eld_chmap(struct hdmi_codec_priv *hcp)
{
u8 spk_alloc;
unsigned long spk_mask;
spk_alloc = drm_eld_get_spk_alloc(hcp->eld);
spk_mask = hdmi_codec_spk_mask_from_alloc(spk_alloc);
/* Detect if only stereo supported, else return 8 channels mappings */
if ((spk_mask & ~(FL | FR)) && hcp->chmap_info->max_channels > 2)
hcp->chmap_info->chmap = hdmi_codec_8ch_chmaps;
else
hcp->chmap_info->chmap = hdmi_codec_stereo_chmaps;
}
static int hdmi_codec_get_ch_alloc_table_idx(struct hdmi_codec_priv *hcp,
unsigned char channels)
{
int i;
u8 spk_alloc;
unsigned long spk_mask;
const struct hdmi_codec_cea_spk_alloc *cap = hdmi_codec_channel_alloc;
spk_alloc = drm_eld_get_spk_alloc(hcp->eld);
spk_mask = hdmi_codec_spk_mask_from_alloc(spk_alloc);
for (i = 0; i < ARRAY_SIZE(hdmi_codec_channel_alloc); i++, cap++) {
/* If spk_alloc == 0, HDMI is unplugged return stereo config*/
if (!spk_alloc && cap->ca_id == 0)
return i;
if (cap->n_ch != channels)
continue;
if (!(cap->mask == (spk_mask & cap->mask)))
continue;
return i;
}
return -EINVAL;
}
static int hdmi_codec_chmap_ctl_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
unsigned const char *map;
unsigned int i;
struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
struct hdmi_codec_priv *hcp = info->private_data;
map = info->chmap[hcp->chmap_idx].map;
for (i = 0; i < info->max_channels; i++) {
if (hcp->chmap_idx == HDMI_CODEC_CHMAP_IDX_UNKNOWN)
ucontrol->value.integer.value[i] = 0;
else
ucontrol->value.integer.value[i] = map[i];
}
return 0;
}
static int hdmi_codec_iec958_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
uinfo->count = 1;
return 0;
}
static int hdmi_codec_iec958_default_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct hdmi_codec_priv *hcp = snd_soc_component_get_drvdata(component);
memcpy(ucontrol->value.iec958.status, hcp->iec_status,
sizeof(hcp->iec_status));
return 0;
}
static int hdmi_codec_iec958_default_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct hdmi_codec_priv *hcp = snd_soc_component_get_drvdata(component);
memcpy(hcp->iec_status, ucontrol->value.iec958.status,
sizeof(hcp->iec_status));
return 0;
}
static int hdmi_codec_iec958_mask_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
memset(ucontrol->value.iec958.status, 0xff,
sizeof_field(struct hdmi_codec_priv, iec_status));
return 0;
}
static int hdmi_codec_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct hdmi_codec_priv *hcp = snd_soc_dai_get_drvdata(dai);
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
bool has_capture = !hcp->hcd.no_i2s_capture;
bool has_playback = !hcp->hcd.no_i2s_playback;
int ret = 0;
if (!((has_playback && tx) || (has_capture && !tx)))
return 0;
mutex_lock(&hcp->lock);
if (hcp->busy) {
dev_err(dai->dev, "Only one simultaneous stream supported!\n");
mutex_unlock(&hcp->lock);
return -EINVAL;
}
if (hcp->hcd.ops->audio_startup) {
ret = hcp->hcd.ops->audio_startup(dai->dev->parent, hcp->hcd.data);
if (ret)
goto err;
}
if (tx && hcp->hcd.ops->get_eld) {
ret = hcp->hcd.ops->get_eld(dai->dev->parent, hcp->hcd.data,
hcp->eld, sizeof(hcp->eld));
if (ret)
goto err;
ret = snd_pcm_hw_constraint_eld(substream->runtime, hcp->eld);
if (ret)
goto err;
/* Select chmap supported */
hdmi_codec_eld_chmap(hcp);
}
hcp->busy = true;
err:
mutex_unlock(&hcp->lock);
return ret;
}
static void hdmi_codec_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct hdmi_codec_priv *hcp = snd_soc_dai_get_drvdata(dai);
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
bool has_capture = !hcp->hcd.no_i2s_capture;
bool has_playback = !hcp->hcd.no_i2s_playback;
if (!((has_playback && tx) || (has_capture && !tx)))
return;
hcp->chmap_idx = HDMI_CODEC_CHMAP_IDX_UNKNOWN;
hcp->hcd.ops->audio_shutdown(dai->dev->parent, hcp->hcd.data);
mutex_lock(&hcp->lock);
hcp->busy = false;
mutex_unlock(&hcp->lock);
}
static int hdmi_codec_fill_codec_params(struct snd_soc_dai *dai,
unsigned int sample_width,
unsigned int sample_rate,
unsigned int channels,
struct hdmi_codec_params *hp)
{
struct hdmi_codec_priv *hcp = snd_soc_dai_get_drvdata(dai);
int idx = HDMI_CODEC_CHMAP_IDX_UNKNOWN;
u8 ca_id = 0;
bool pcm_audio = !(hcp->iec_status[0] & IEC958_AES0_NONAUDIO);
if (pcm_audio) {
/* Select a channel allocation that matches with ELD and pcm channels */
idx = hdmi_codec_get_ch_alloc_table_idx(hcp, channels);
if (idx < 0) {
dev_err(dai->dev, "Not able to map channels to speakers (%d)\n",
idx);
hcp->chmap_idx = HDMI_CODEC_CHMAP_IDX_UNKNOWN;
return idx;
}
ca_id = hdmi_codec_channel_alloc[idx].ca_id;
}
memset(hp, 0, sizeof(*hp));
hdmi_audio_infoframe_init(&hp->cea);
if (pcm_audio)
hp->cea.channels = channels;
else
hp->cea.channels = 0;
hp->cea.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
hp->cea.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
hp->cea.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
hp->cea.channel_allocation = ca_id;
hp->sample_width = sample_width;
hp->sample_rate = sample_rate;
hp->channels = channels;
hcp->chmap_idx = idx;
return 0;
}
static int hdmi_codec_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct hdmi_codec_priv *hcp = snd_soc_dai_get_drvdata(dai);
struct hdmi_codec_daifmt *cf = snd_soc_dai_dma_data_get_playback(dai);
struct hdmi_codec_params hp = {
.iec = {
.status = { 0 },
.subcode = { 0 },
.pad = 0,
.dig_subframe = { 0 },
}
};
int ret;
if (!hcp->hcd.ops->hw_params)
return 0;
dev_dbg(dai->dev, "%s() width %d rate %d channels %d\n", __func__,
params_width(params), params_rate(params),
params_channels(params));
ret = hdmi_codec_fill_codec_params(dai,
params_width(params),
params_rate(params),
params_channels(params),
&hp);
if (ret < 0)
return ret;
memcpy(hp.iec.status, hcp->iec_status, sizeof(hp.iec.status));
ret = snd_pcm_fill_iec958_consumer_hw_params(params, hp.iec.status,
sizeof(hp.iec.status));
if (ret < 0) {
dev_err(dai->dev, "Creating IEC958 channel status failed %d\n",
ret);
return ret;
}
cf->bit_fmt = params_format(params);
return hcp->hcd.ops->hw_params(dai->dev->parent, hcp->hcd.data,
cf, &hp);
}
static int hdmi_codec_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct hdmi_codec_priv *hcp = snd_soc_dai_get_drvdata(dai);
struct hdmi_codec_daifmt *cf = snd_soc_dai_dma_data_get_playback(dai);
struct snd_pcm_runtime *runtime = substream->runtime;
unsigned int channels = runtime->channels;
unsigned int width = snd_pcm_format_width(runtime->format);
unsigned int rate = runtime->rate;
struct hdmi_codec_params hp;
int ret;
if (!hcp->hcd.ops->prepare)
return 0;
dev_dbg(dai->dev, "%s() width %d rate %d channels %d\n", __func__,
width, rate, channels);
ret = hdmi_codec_fill_codec_params(dai, width, rate, channels, &hp);
if (ret < 0)
return ret;
memcpy(hp.iec.status, hcp->iec_status, sizeof(hp.iec.status));
ret = snd_pcm_fill_iec958_consumer(runtime, hp.iec.status,
sizeof(hp.iec.status));
if (ret < 0) {
dev_err(dai->dev, "Creating IEC958 channel status failed %d\n",
ret);
return ret;
}
cf->bit_fmt = runtime->format;
return hcp->hcd.ops->prepare(dai->dev->parent, hcp->hcd.data,
cf, &hp);
}
static int hdmi_codec_i2s_set_fmt(struct snd_soc_dai *dai,
unsigned int fmt)
{
struct hdmi_codec_daifmt *cf = snd_soc_dai_dma_data_get_playback(dai);
/* Reset daifmt */
memset(cf, 0, sizeof(*cf));
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
cf->bit_clk_provider = 1;
cf->frame_clk_provider = 1;
break;
case SND_SOC_DAIFMT_CBC_CFP:
cf->frame_clk_provider = 1;
break;
case SND_SOC_DAIFMT_CBP_CFC:
cf->bit_clk_provider = 1;
break;
case SND_SOC_DAIFMT_CBC_CFC:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_NB_IF:
cf->frame_clk_inv = 1;
break;
case SND_SOC_DAIFMT_IB_NF:
cf->bit_clk_inv = 1;
break;
case SND_SOC_DAIFMT_IB_IF:
cf->frame_clk_inv = 1;
cf->bit_clk_inv = 1;
break;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
cf->fmt = HDMI_I2S;
break;
case SND_SOC_DAIFMT_DSP_A:
cf->fmt = HDMI_DSP_A;
break;
case SND_SOC_DAIFMT_DSP_B:
cf->fmt = HDMI_DSP_B;
break;
case SND_SOC_DAIFMT_RIGHT_J:
cf->fmt = HDMI_RIGHT_J;
break;
case SND_SOC_DAIFMT_LEFT_J:
cf->fmt = HDMI_LEFT_J;
break;
case SND_SOC_DAIFMT_AC97:
cf->fmt = HDMI_AC97;
break;
default:
dev_err(dai->dev, "Invalid DAI interface format\n");
return -EINVAL;
}
return 0;
}
static int hdmi_codec_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct hdmi_codec_priv *hcp = snd_soc_dai_get_drvdata(dai);
/*
* ignore if direction was CAPTURE
* and it had .no_capture_mute flag
* see
* snd_soc_dai_digital_mute()
*/
if (hcp->hcd.ops->mute_stream &&
(direction == SNDRV_PCM_STREAM_PLAYBACK ||
!hcp->hcd.ops->no_capture_mute))
return hcp->hcd.ops->mute_stream(dai->dev->parent,
hcp->hcd.data,
mute, direction);
return -ENOTSUPP;
}
/*
* This driver can select all SND_SOC_DAIFMT_CBx_CFx,
* but need to be selected from Sound Card, not be auto selected.
* Because it might be used from other driver.
* For example,
* ${LINUX}/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
*/
static u64 hdmi_codec_formats =
SND_SOC_POSSIBLE_DAIFMT_NB_NF |
SND_SOC_POSSIBLE_DAIFMT_NB_IF |
SND_SOC_POSSIBLE_DAIFMT_IB_NF |
SND_SOC_POSSIBLE_DAIFMT_IB_IF |
SND_SOC_POSSIBLE_DAIFMT_I2S |
SND_SOC_POSSIBLE_DAIFMT_DSP_A |
SND_SOC_POSSIBLE_DAIFMT_DSP_B |
SND_SOC_POSSIBLE_DAIFMT_RIGHT_J |
SND_SOC_POSSIBLE_DAIFMT_LEFT_J |
SND_SOC_POSSIBLE_DAIFMT_AC97;
#define HDMI_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |\
SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
SNDRV_PCM_RATE_192000)
#define SPDIF_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
/*
* This list is only for formats allowed on the I2S bus. So there is
* some formats listed that are not supported by HDMI interface. For
* instance allowing the 32-bit formats enables 24-precision with CPU
* DAIs that do not support 24-bit formats. If the extra formats cause
* problems, we should add the video side driver an option to disable
* them.
*/
#define I2S_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE)
static struct snd_kcontrol_new hdmi_codec_controls[] = {
{
.access = SNDRV_CTL_ELEM_ACCESS_READ,
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
.info = hdmi_codec_iec958_info,
.get = hdmi_codec_iec958_mask_get,
},
{
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
.info = hdmi_codec_iec958_info,
.get = hdmi_codec_iec958_default_get,
.put = hdmi_codec_iec958_default_put,
},
{
.access = (SNDRV_CTL_ELEM_ACCESS_READ |
SNDRV_CTL_ELEM_ACCESS_VOLATILE),
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = "ELD",
.info = hdmi_eld_ctl_info,
.get = hdmi_eld_ctl_get,
},
};
static int hdmi_codec_pcm_new(struct snd_soc_pcm_runtime *rtd,
struct snd_soc_dai *dai)
{
struct snd_soc_dai_driver *drv = dai->driver;
struct hdmi_codec_priv *hcp = snd_soc_dai_get_drvdata(dai);
unsigned int i;
int ret;
ret = snd_pcm_add_chmap_ctls(rtd->pcm, SNDRV_PCM_STREAM_PLAYBACK,
NULL, drv->playback.channels_max, 0,
&hcp->chmap_info);
if (ret < 0)
return ret;
/* override handlers */
hcp->chmap_info->private_data = hcp;
hcp->chmap_info->kctl->get = hdmi_codec_chmap_ctl_get;
/* default chmap supported is stereo */
hcp->chmap_info->chmap = hdmi_codec_stereo_chmaps;
hcp->chmap_idx = HDMI_CODEC_CHMAP_IDX_UNKNOWN;
for (i = 0; i < ARRAY_SIZE(hdmi_codec_controls); i++) {
struct snd_kcontrol *kctl;
/* add ELD ctl with the device number corresponding to the PCM stream */
kctl = snd_ctl_new1(&hdmi_codec_controls[i], dai->component);
if (!kctl)
return -ENOMEM;
kctl->id.device = rtd->pcm->device;
ret = snd_ctl_add(rtd->card->snd_card, kctl);
if (ret < 0)
return ret;
}
return 0;
}
static int hdmi_dai_probe(struct snd_soc_dai *dai)
{
struct snd_soc_dapm_context *dapm;
struct hdmi_codec_daifmt *daifmt;
struct snd_soc_dapm_route route[] = {
{
.sink = "TX",
.source = dai->driver->playback.stream_name,
},
{
.sink = dai->driver->capture.stream_name,
.source = "RX",
},
};
int ret, i;
dapm = snd_soc_component_get_dapm(dai->component);
/* One of the directions might be omitted for unidirectional DAIs */
for (i = 0; i < ARRAY_SIZE(route); i++) {
if (!route[i].source || !route[i].sink)
continue;
ret = snd_soc_dapm_add_routes(dapm, &route[i], 1);
if (ret)
return ret;
}
daifmt = devm_kzalloc(dai->dev, sizeof(*daifmt), GFP_KERNEL);
if (!daifmt)
return -ENOMEM;
snd_soc_dai_dma_data_set_playback(dai, daifmt);
return 0;
}
static void hdmi_codec_jack_report(struct hdmi_codec_priv *hcp,
unsigned int jack_status)
{
if (hcp->jack && jack_status != hcp->jack_status) {
snd_soc_jack_report(hcp->jack, jack_status, SND_JACK_LINEOUT);
hcp->jack_status = jack_status;
}
}
static void plugged_cb(struct device *dev, bool plugged)
{
struct hdmi_codec_priv *hcp = dev_get_drvdata(dev);
if (plugged) {
if (hcp->hcd.ops->get_eld) {
hcp->hcd.ops->get_eld(dev->parent, hcp->hcd.data,
hcp->eld, sizeof(hcp->eld));
}
hdmi_codec_jack_report(hcp, SND_JACK_LINEOUT);
} else {
hdmi_codec_jack_report(hcp, 0);
memset(hcp->eld, 0, sizeof(hcp->eld));
}
}
static int hdmi_codec_set_jack(struct snd_soc_component *component,
struct snd_soc_jack *jack,
void *data)
{
struct hdmi_codec_priv *hcp = snd_soc_component_get_drvdata(component);
int ret = -ENOTSUPP;
if (hcp->hcd.ops->hook_plugged_cb) {
hcp->jack = jack;
ret = hcp->hcd.ops->hook_plugged_cb(component->dev->parent,
hcp->hcd.data,
plugged_cb,
component->dev);
if (ret)
hcp->jack = NULL;
}
return ret;
}
static int hdmi_dai_spdif_probe(struct snd_soc_dai *dai)
{
struct hdmi_codec_daifmt *cf;
int ret;
ret = hdmi_dai_probe(dai);
if (ret)
return ret;
cf = snd_soc_dai_dma_data_get_playback(dai);
cf->fmt = HDMI_SPDIF;
return 0;
}
static const struct snd_soc_dai_ops hdmi_codec_i2s_dai_ops = {
.probe = hdmi_dai_probe,
.startup = hdmi_codec_startup,
.shutdown = hdmi_codec_shutdown,
.hw_params = hdmi_codec_hw_params,
.prepare = hdmi_codec_prepare,
.set_fmt = hdmi_codec_i2s_set_fmt,
.mute_stream = hdmi_codec_mute,
.pcm_new = hdmi_codec_pcm_new,
.auto_selectable_formats = &hdmi_codec_formats,
.num_auto_selectable_formats = 1,
};
static const struct snd_soc_dai_ops hdmi_codec_spdif_dai_ops = {
.probe = hdmi_dai_spdif_probe,
.startup = hdmi_codec_startup,
.shutdown = hdmi_codec_shutdown,
.hw_params = hdmi_codec_hw_params,
.mute_stream = hdmi_codec_mute,
.pcm_new = hdmi_codec_pcm_new,
};
static const struct snd_soc_dai_driver hdmi_i2s_dai = {
.name = "i2s-hifi",
.id = DAI_ID_I2S,
.playback = {
.stream_name = "I2S Playback",
.channels_min = 2,
.channels_max = 8,
.rates = HDMI_RATES,
.formats = I2S_FORMATS,
.sig_bits = 24,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 8,
.rates = HDMI_RATES,
.formats = I2S_FORMATS,
.sig_bits = 24,
},
.ops = &hdmi_codec_i2s_dai_ops,
};
static const struct snd_soc_dai_driver hdmi_spdif_dai = {
.name = "spdif-hifi",
.id = DAI_ID_SPDIF,
.playback = {
.stream_name = "SPDIF Playback",
.channels_min = 2,
.channels_max = 2,
.rates = HDMI_RATES,
.formats = SPDIF_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = HDMI_RATES,
.formats = SPDIF_FORMATS,
},
.ops = &hdmi_codec_spdif_dai_ops,
};
static int hdmi_of_xlate_dai_id(struct snd_soc_component *component,
struct device_node *endpoint)
{
struct hdmi_codec_priv *hcp = snd_soc_component_get_drvdata(component);
int ret = -ENOTSUPP; /* see snd_soc_get_dai_id() */
if (hcp->hcd.ops->get_dai_id)
ret = hcp->hcd.ops->get_dai_id(component, endpoint);
return ret;
}
static void hdmi_remove(struct snd_soc_component *component)
{
struct hdmi_codec_priv *hcp = snd_soc_component_get_drvdata(component);
if (hcp->hcd.ops->hook_plugged_cb)
hcp->hcd.ops->hook_plugged_cb(component->dev->parent,
hcp->hcd.data, NULL, NULL);
}
static const struct snd_soc_component_driver hdmi_driver = {
.remove = hdmi_remove,
.dapm_widgets = hdmi_widgets,
.num_dapm_widgets = ARRAY_SIZE(hdmi_widgets),
.of_xlate_dai_id = hdmi_of_xlate_dai_id,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
.set_jack = hdmi_codec_set_jack,
};
static int hdmi_codec_probe(struct platform_device *pdev)
{
struct hdmi_codec_pdata *hcd = pdev->dev.platform_data;
struct snd_soc_dai_driver *daidrv;
struct device *dev = &pdev->dev;
struct hdmi_codec_priv *hcp;
int dai_count, i = 0;
int ret;
if (!hcd) {
dev_err(dev, "%s: No platform data\n", __func__);
return -EINVAL;
}
dai_count = hcd->i2s + hcd->spdif;
if (dai_count < 1 || !hcd->ops ||
(!hcd->ops->hw_params && !hcd->ops->prepare) ||
!hcd->ops->audio_shutdown) {
dev_err(dev, "%s: Invalid parameters\n", __func__);
return -EINVAL;
}
hcp = devm_kzalloc(dev, sizeof(*hcp), GFP_KERNEL);
if (!hcp)
return -ENOMEM;
hcp->hcd = *hcd;
mutex_init(&hcp->lock);
ret = snd_pcm_create_iec958_consumer_default(hcp->iec_status,
sizeof(hcp->iec_status));
if (ret < 0)
return ret;
daidrv = devm_kcalloc(dev, dai_count, sizeof(*daidrv), GFP_KERNEL);
if (!daidrv)
return -ENOMEM;
if (hcd->i2s) {
daidrv[i] = hdmi_i2s_dai;
daidrv[i].playback.channels_max = hcd->max_i2s_channels;
if (hcd->no_i2s_playback)
memset(&daidrv[i].playback, 0,
sizeof(daidrv[i].playback));
if (hcd->no_i2s_capture)
memset(&daidrv[i].capture, 0,
sizeof(daidrv[i].capture));
i++;
}
if (hcd->spdif) {
daidrv[i] = hdmi_spdif_dai;
if (hcd->no_spdif_playback)
memset(&daidrv[i].playback, 0,
sizeof(daidrv[i].playback));
if (hcd->no_spdif_capture)
memset(&daidrv[i].capture, 0,
sizeof(daidrv[i].capture));
}
dev_set_drvdata(dev, hcp);
ret = devm_snd_soc_register_component(dev, &hdmi_driver, daidrv,
dai_count);
if (ret) {
dev_err(dev, "%s: snd_soc_register_component() failed (%d)\n",
__func__, ret);
return ret;
}
return 0;
}
static struct platform_driver hdmi_codec_driver = {
.driver = {
.name = HDMI_CODEC_DRV_NAME,
},
.probe = hdmi_codec_probe,
};
module_platform_driver(hdmi_codec_driver);
MODULE_AUTHOR("Jyri Sarha <[email protected]>");
MODULE_DESCRIPTION("HDMI Audio Codec Driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" HDMI_CODEC_DRV_NAME);
| linux-master | sound/soc/codecs/hdmi-codec.c |
// SPDX-License-Identifier: GPL-2.0
// TLV320ADCX140 Sound driver
// Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/gpio/consumer.h>
#include <linux/regulator/consumer.h>
#include <linux/acpi.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "tlv320adcx140.h"
struct adcx140_priv {
struct snd_soc_component *component;
struct regulator *supply_areg;
struct gpio_desc *gpio_reset;
struct regmap *regmap;
struct device *dev;
bool micbias_vg;
bool phase_calib_on;
unsigned int dai_fmt;
unsigned int slot_width;
};
static const char * const gpo_config_names[] = {
"ti,gpo-config-1",
"ti,gpo-config-2",
"ti,gpo-config-3",
"ti,gpo-config-4",
};
static const struct reg_default adcx140_reg_defaults[] = {
{ ADCX140_PAGE_SELECT, 0x00 },
{ ADCX140_SW_RESET, 0x00 },
{ ADCX140_SLEEP_CFG, 0x00 },
{ ADCX140_SHDN_CFG, 0x05 },
{ ADCX140_ASI_CFG0, 0x30 },
{ ADCX140_ASI_CFG1, 0x00 },
{ ADCX140_ASI_CFG2, 0x00 },
{ ADCX140_ASI_CH1, 0x00 },
{ ADCX140_ASI_CH2, 0x01 },
{ ADCX140_ASI_CH3, 0x02 },
{ ADCX140_ASI_CH4, 0x03 },
{ ADCX140_ASI_CH5, 0x04 },
{ ADCX140_ASI_CH6, 0x05 },
{ ADCX140_ASI_CH7, 0x06 },
{ ADCX140_ASI_CH8, 0x07 },
{ ADCX140_MST_CFG0, 0x02 },
{ ADCX140_MST_CFG1, 0x48 },
{ ADCX140_ASI_STS, 0xff },
{ ADCX140_CLK_SRC, 0x10 },
{ ADCX140_PDMCLK_CFG, 0x40 },
{ ADCX140_PDM_CFG, 0x00 },
{ ADCX140_GPIO_CFG0, 0x22 },
{ ADCX140_GPO_CFG0, 0x00 },
{ ADCX140_GPO_CFG1, 0x00 },
{ ADCX140_GPO_CFG2, 0x00 },
{ ADCX140_GPO_CFG3, 0x00 },
{ ADCX140_GPO_VAL, 0x00 },
{ ADCX140_GPIO_MON, 0x00 },
{ ADCX140_GPI_CFG0, 0x00 },
{ ADCX140_GPI_CFG1, 0x00 },
{ ADCX140_GPI_MON, 0x00 },
{ ADCX140_INT_CFG, 0x00 },
{ ADCX140_INT_MASK0, 0xff },
{ ADCX140_INT_LTCH0, 0x00 },
{ ADCX140_BIAS_CFG, 0x00 },
{ ADCX140_CH1_CFG0, 0x00 },
{ ADCX140_CH1_CFG1, 0x00 },
{ ADCX140_CH1_CFG2, 0xc9 },
{ ADCX140_CH1_CFG3, 0x80 },
{ ADCX140_CH1_CFG4, 0x00 },
{ ADCX140_CH2_CFG0, 0x00 },
{ ADCX140_CH2_CFG1, 0x00 },
{ ADCX140_CH2_CFG2, 0xc9 },
{ ADCX140_CH2_CFG3, 0x80 },
{ ADCX140_CH2_CFG4, 0x00 },
{ ADCX140_CH3_CFG0, 0x00 },
{ ADCX140_CH3_CFG1, 0x00 },
{ ADCX140_CH3_CFG2, 0xc9 },
{ ADCX140_CH3_CFG3, 0x80 },
{ ADCX140_CH3_CFG4, 0x00 },
{ ADCX140_CH4_CFG0, 0x00 },
{ ADCX140_CH4_CFG1, 0x00 },
{ ADCX140_CH4_CFG2, 0xc9 },
{ ADCX140_CH4_CFG3, 0x80 },
{ ADCX140_CH4_CFG4, 0x00 },
{ ADCX140_CH5_CFG2, 0xc9 },
{ ADCX140_CH5_CFG3, 0x80 },
{ ADCX140_CH5_CFG4, 0x00 },
{ ADCX140_CH6_CFG2, 0xc9 },
{ ADCX140_CH6_CFG3, 0x80 },
{ ADCX140_CH6_CFG4, 0x00 },
{ ADCX140_CH7_CFG2, 0xc9 },
{ ADCX140_CH7_CFG3, 0x80 },
{ ADCX140_CH7_CFG4, 0x00 },
{ ADCX140_CH8_CFG2, 0xc9 },
{ ADCX140_CH8_CFG3, 0x80 },
{ ADCX140_CH8_CFG4, 0x00 },
{ ADCX140_DSP_CFG0, 0x01 },
{ ADCX140_DSP_CFG1, 0x40 },
{ ADCX140_DRE_CFG0, 0x7b },
{ ADCX140_AGC_CFG0, 0xe7 },
{ ADCX140_IN_CH_EN, 0xf0 },
{ ADCX140_ASI_OUT_CH_EN, 0x00 },
{ ADCX140_PWR_CFG, 0x00 },
{ ADCX140_DEV_STS0, 0x00 },
{ ADCX140_DEV_STS1, 0x80 },
};
static const struct regmap_range_cfg adcx140_ranges[] = {
{
.range_min = 0,
.range_max = 12 * 128,
.selector_reg = ADCX140_PAGE_SELECT,
.selector_mask = 0xff,
.selector_shift = 0,
.window_start = 0,
.window_len = 128,
},
};
static bool adcx140_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case ADCX140_SW_RESET:
case ADCX140_DEV_STS0:
case ADCX140_DEV_STS1:
case ADCX140_ASI_STS:
return true;
default:
return false;
}
}
static const struct regmap_config adcx140_i2c_regmap = {
.reg_bits = 8,
.val_bits = 8,
.reg_defaults = adcx140_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(adcx140_reg_defaults),
.cache_type = REGCACHE_FLAT,
.ranges = adcx140_ranges,
.num_ranges = ARRAY_SIZE(adcx140_ranges),
.max_register = 12 * 128,
.volatile_reg = adcx140_volatile,
};
/* Digital Volume control. From -100 to 27 dB in 0.5 dB steps */
static DECLARE_TLV_DB_SCALE(dig_vol_tlv, -10050, 50, 0);
/* ADC gain. From 0 to 42 dB in 1 dB steps */
static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 100, 0);
/* DRE Level. From -12 dB to -66 dB in 1 dB steps */
static DECLARE_TLV_DB_SCALE(dre_thresh_tlv, -6600, 100, 0);
/* DRE Max Gain. From 2 dB to 26 dB in 2 dB steps */
static DECLARE_TLV_DB_SCALE(dre_gain_tlv, 200, 200, 0);
/* AGC Level. From -6 dB to -36 dB in 2 dB steps */
static DECLARE_TLV_DB_SCALE(agc_thresh_tlv, -3600, 200, 0);
/* AGC Max Gain. From 3 dB to 42 dB in 3 dB steps */
static DECLARE_TLV_DB_SCALE(agc_gain_tlv, 300, 300, 0);
static const char * const decimation_filter_text[] = {
"Linear Phase", "Low Latency", "Ultra-low Latency"
};
static SOC_ENUM_SINGLE_DECL(decimation_filter_enum, ADCX140_DSP_CFG0, 4,
decimation_filter_text);
static const struct snd_kcontrol_new decimation_filter_controls[] = {
SOC_DAPM_ENUM("Decimation Filter", decimation_filter_enum),
};
static const char * const pdmclk_text[] = {
"2.8224 MHz", "1.4112 MHz", "705.6 kHz", "5.6448 MHz"
};
static SOC_ENUM_SINGLE_DECL(pdmclk_select_enum, ADCX140_PDMCLK_CFG, 0,
pdmclk_text);
static const struct snd_kcontrol_new pdmclk_div_controls[] = {
SOC_DAPM_ENUM("PDM Clk Divider Select", pdmclk_select_enum),
};
static const char * const resistor_text[] = {
"2.5 kOhm", "10 kOhm", "20 kOhm"
};
static SOC_ENUM_SINGLE_DECL(in1_resistor_enum, ADCX140_CH1_CFG0, 2,
resistor_text);
static SOC_ENUM_SINGLE_DECL(in2_resistor_enum, ADCX140_CH2_CFG0, 2,
resistor_text);
static SOC_ENUM_SINGLE_DECL(in3_resistor_enum, ADCX140_CH3_CFG0, 2,
resistor_text);
static SOC_ENUM_SINGLE_DECL(in4_resistor_enum, ADCX140_CH4_CFG0, 2,
resistor_text);
static const struct snd_kcontrol_new in1_resistor_controls[] = {
SOC_DAPM_ENUM("CH1 Resistor Select", in1_resistor_enum),
};
static const struct snd_kcontrol_new in2_resistor_controls[] = {
SOC_DAPM_ENUM("CH2 Resistor Select", in2_resistor_enum),
};
static const struct snd_kcontrol_new in3_resistor_controls[] = {
SOC_DAPM_ENUM("CH3 Resistor Select", in3_resistor_enum),
};
static const struct snd_kcontrol_new in4_resistor_controls[] = {
SOC_DAPM_ENUM("CH4 Resistor Select", in4_resistor_enum),
};
/* Analog/Digital Selection */
static const char * const adcx140_mic_sel_text[] = {"Analog", "Line In", "Digital"};
static const char * const adcx140_analog_sel_text[] = {"Analog", "Line In"};
static SOC_ENUM_SINGLE_DECL(adcx140_mic1p_enum,
ADCX140_CH1_CFG0, 5,
adcx140_mic_sel_text);
static const struct snd_kcontrol_new adcx140_dapm_mic1p_control =
SOC_DAPM_ENUM("MIC1P MUX", adcx140_mic1p_enum);
static SOC_ENUM_SINGLE_DECL(adcx140_mic1_analog_enum,
ADCX140_CH1_CFG0, 7,
adcx140_analog_sel_text);
static const struct snd_kcontrol_new adcx140_dapm_mic1_analog_control =
SOC_DAPM_ENUM("MIC1 Analog MUX", adcx140_mic1_analog_enum);
static SOC_ENUM_SINGLE_DECL(adcx140_mic1m_enum,
ADCX140_CH1_CFG0, 5,
adcx140_mic_sel_text);
static const struct snd_kcontrol_new adcx140_dapm_mic1m_control =
SOC_DAPM_ENUM("MIC1M MUX", adcx140_mic1m_enum);
static SOC_ENUM_SINGLE_DECL(adcx140_mic2p_enum,
ADCX140_CH2_CFG0, 5,
adcx140_mic_sel_text);
static const struct snd_kcontrol_new adcx140_dapm_mic2p_control =
SOC_DAPM_ENUM("MIC2P MUX", adcx140_mic2p_enum);
static SOC_ENUM_SINGLE_DECL(adcx140_mic2_analog_enum,
ADCX140_CH2_CFG0, 7,
adcx140_analog_sel_text);
static const struct snd_kcontrol_new adcx140_dapm_mic2_analog_control =
SOC_DAPM_ENUM("MIC2 Analog MUX", adcx140_mic2_analog_enum);
static SOC_ENUM_SINGLE_DECL(adcx140_mic2m_enum,
ADCX140_CH2_CFG0, 5,
adcx140_mic_sel_text);
static const struct snd_kcontrol_new adcx140_dapm_mic2m_control =
SOC_DAPM_ENUM("MIC2M MUX", adcx140_mic2m_enum);
static SOC_ENUM_SINGLE_DECL(adcx140_mic3p_enum,
ADCX140_CH3_CFG0, 5,
adcx140_mic_sel_text);
static const struct snd_kcontrol_new adcx140_dapm_mic3p_control =
SOC_DAPM_ENUM("MIC3P MUX", adcx140_mic3p_enum);
static SOC_ENUM_SINGLE_DECL(adcx140_mic3_analog_enum,
ADCX140_CH3_CFG0, 7,
adcx140_analog_sel_text);
static const struct snd_kcontrol_new adcx140_dapm_mic3_analog_control =
SOC_DAPM_ENUM("MIC3 Analog MUX", adcx140_mic3_analog_enum);
static SOC_ENUM_SINGLE_DECL(adcx140_mic3m_enum,
ADCX140_CH3_CFG0, 5,
adcx140_mic_sel_text);
static const struct snd_kcontrol_new adcx140_dapm_mic3m_control =
SOC_DAPM_ENUM("MIC3M MUX", adcx140_mic3m_enum);
static SOC_ENUM_SINGLE_DECL(adcx140_mic4p_enum,
ADCX140_CH4_CFG0, 5,
adcx140_mic_sel_text);
static const struct snd_kcontrol_new adcx140_dapm_mic4p_control =
SOC_DAPM_ENUM("MIC4P MUX", adcx140_mic4p_enum);
static SOC_ENUM_SINGLE_DECL(adcx140_mic4_analog_enum,
ADCX140_CH4_CFG0, 7,
adcx140_analog_sel_text);
static const struct snd_kcontrol_new adcx140_dapm_mic4_analog_control =
SOC_DAPM_ENUM("MIC4 Analog MUX", adcx140_mic4_analog_enum);
static SOC_ENUM_SINGLE_DECL(adcx140_mic4m_enum,
ADCX140_CH4_CFG0, 5,
adcx140_mic_sel_text);
static const struct snd_kcontrol_new adcx140_dapm_mic4m_control =
SOC_DAPM_ENUM("MIC4M MUX", adcx140_mic4m_enum);
static const struct snd_kcontrol_new adcx140_dapm_ch1_en_switch =
SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 7, 1, 0);
static const struct snd_kcontrol_new adcx140_dapm_ch2_en_switch =
SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 6, 1, 0);
static const struct snd_kcontrol_new adcx140_dapm_ch3_en_switch =
SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 5, 1, 0);
static const struct snd_kcontrol_new adcx140_dapm_ch4_en_switch =
SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 4, 1, 0);
static const struct snd_kcontrol_new adcx140_dapm_ch5_en_switch =
SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 3, 1, 0);
static const struct snd_kcontrol_new adcx140_dapm_ch6_en_switch =
SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 2, 1, 0);
static const struct snd_kcontrol_new adcx140_dapm_ch7_en_switch =
SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 1, 1, 0);
static const struct snd_kcontrol_new adcx140_dapm_ch8_en_switch =
SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 0, 1, 0);
static const struct snd_kcontrol_new adcx140_dapm_ch1_dre_en_switch =
SOC_DAPM_SINGLE("Switch", ADCX140_CH1_CFG0, 0, 1, 0);
static const struct snd_kcontrol_new adcx140_dapm_ch2_dre_en_switch =
SOC_DAPM_SINGLE("Switch", ADCX140_CH2_CFG0, 0, 1, 0);
static const struct snd_kcontrol_new adcx140_dapm_ch3_dre_en_switch =
SOC_DAPM_SINGLE("Switch", ADCX140_CH3_CFG0, 0, 1, 0);
static const struct snd_kcontrol_new adcx140_dapm_ch4_dre_en_switch =
SOC_DAPM_SINGLE("Switch", ADCX140_CH4_CFG0, 0, 1, 0);
static const struct snd_kcontrol_new adcx140_dapm_dre_en_switch =
SOC_DAPM_SINGLE("Switch", ADCX140_DSP_CFG1, 3, 1, 0);
/* Output Mixer */
static const struct snd_kcontrol_new adcx140_output_mixer_controls[] = {
SOC_DAPM_SINGLE("Digital CH1 Switch", 0, 0, 0, 0),
SOC_DAPM_SINGLE("Digital CH2 Switch", 0, 0, 0, 0),
SOC_DAPM_SINGLE("Digital CH3 Switch", 0, 0, 0, 0),
SOC_DAPM_SINGLE("Digital CH4 Switch", 0, 0, 0, 0),
};
static const struct snd_soc_dapm_widget adcx140_dapm_widgets[] = {
/* Analog Differential Inputs */
SND_SOC_DAPM_INPUT("MIC1P"),
SND_SOC_DAPM_INPUT("MIC1M"),
SND_SOC_DAPM_INPUT("MIC2P"),
SND_SOC_DAPM_INPUT("MIC2M"),
SND_SOC_DAPM_INPUT("MIC3P"),
SND_SOC_DAPM_INPUT("MIC3M"),
SND_SOC_DAPM_INPUT("MIC4P"),
SND_SOC_DAPM_INPUT("MIC4M"),
SND_SOC_DAPM_OUTPUT("CH1_OUT"),
SND_SOC_DAPM_OUTPUT("CH2_OUT"),
SND_SOC_DAPM_OUTPUT("CH3_OUT"),
SND_SOC_DAPM_OUTPUT("CH4_OUT"),
SND_SOC_DAPM_OUTPUT("CH5_OUT"),
SND_SOC_DAPM_OUTPUT("CH6_OUT"),
SND_SOC_DAPM_OUTPUT("CH7_OUT"),
SND_SOC_DAPM_OUTPUT("CH8_OUT"),
SND_SOC_DAPM_MIXER("Output Mixer", SND_SOC_NOPM, 0, 0,
&adcx140_output_mixer_controls[0],
ARRAY_SIZE(adcx140_output_mixer_controls)),
/* Input Selection to MIC_PGA */
SND_SOC_DAPM_MUX("MIC1P Input Mux", SND_SOC_NOPM, 0, 0,
&adcx140_dapm_mic1p_control),
SND_SOC_DAPM_MUX("MIC2P Input Mux", SND_SOC_NOPM, 0, 0,
&adcx140_dapm_mic2p_control),
SND_SOC_DAPM_MUX("MIC3P Input Mux", SND_SOC_NOPM, 0, 0,
&adcx140_dapm_mic3p_control),
SND_SOC_DAPM_MUX("MIC4P Input Mux", SND_SOC_NOPM, 0, 0,
&adcx140_dapm_mic4p_control),
/* Input Selection to MIC_PGA */
SND_SOC_DAPM_MUX("MIC1 Analog Mux", SND_SOC_NOPM, 0, 0,
&adcx140_dapm_mic1_analog_control),
SND_SOC_DAPM_MUX("MIC2 Analog Mux", SND_SOC_NOPM, 0, 0,
&adcx140_dapm_mic2_analog_control),
SND_SOC_DAPM_MUX("MIC3 Analog Mux", SND_SOC_NOPM, 0, 0,
&adcx140_dapm_mic3_analog_control),
SND_SOC_DAPM_MUX("MIC4 Analog Mux", SND_SOC_NOPM, 0, 0,
&adcx140_dapm_mic4_analog_control),
SND_SOC_DAPM_MUX("MIC1M Input Mux", SND_SOC_NOPM, 0, 0,
&adcx140_dapm_mic1m_control),
SND_SOC_DAPM_MUX("MIC2M Input Mux", SND_SOC_NOPM, 0, 0,
&adcx140_dapm_mic2m_control),
SND_SOC_DAPM_MUX("MIC3M Input Mux", SND_SOC_NOPM, 0, 0,
&adcx140_dapm_mic3m_control),
SND_SOC_DAPM_MUX("MIC4M Input Mux", SND_SOC_NOPM, 0, 0,
&adcx140_dapm_mic4m_control),
SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH3", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH4", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_ADC("CH1_ADC", "CH1 Capture", ADCX140_IN_CH_EN, 7, 0),
SND_SOC_DAPM_ADC("CH2_ADC", "CH2 Capture", ADCX140_IN_CH_EN, 6, 0),
SND_SOC_DAPM_ADC("CH3_ADC", "CH3 Capture", ADCX140_IN_CH_EN, 5, 0),
SND_SOC_DAPM_ADC("CH4_ADC", "CH4 Capture", ADCX140_IN_CH_EN, 4, 0),
SND_SOC_DAPM_ADC("CH1_DIG", "CH1 Capture", ADCX140_IN_CH_EN, 7, 0),
SND_SOC_DAPM_ADC("CH2_DIG", "CH2 Capture", ADCX140_IN_CH_EN, 6, 0),
SND_SOC_DAPM_ADC("CH3_DIG", "CH3 Capture", ADCX140_IN_CH_EN, 5, 0),
SND_SOC_DAPM_ADC("CH4_DIG", "CH4 Capture", ADCX140_IN_CH_EN, 4, 0),
SND_SOC_DAPM_ADC("CH5_DIG", "CH5 Capture", ADCX140_IN_CH_EN, 3, 0),
SND_SOC_DAPM_ADC("CH6_DIG", "CH6 Capture", ADCX140_IN_CH_EN, 2, 0),
SND_SOC_DAPM_ADC("CH7_DIG", "CH7 Capture", ADCX140_IN_CH_EN, 1, 0),
SND_SOC_DAPM_ADC("CH8_DIG", "CH8 Capture", ADCX140_IN_CH_EN, 0, 0),
SND_SOC_DAPM_SWITCH("CH1_ASI_EN", SND_SOC_NOPM, 0, 0,
&adcx140_dapm_ch1_en_switch),
SND_SOC_DAPM_SWITCH("CH2_ASI_EN", SND_SOC_NOPM, 0, 0,
&adcx140_dapm_ch2_en_switch),
SND_SOC_DAPM_SWITCH("CH3_ASI_EN", SND_SOC_NOPM, 0, 0,
&adcx140_dapm_ch3_en_switch),
SND_SOC_DAPM_SWITCH("CH4_ASI_EN", SND_SOC_NOPM, 0, 0,
&adcx140_dapm_ch4_en_switch),
SND_SOC_DAPM_SWITCH("CH5_ASI_EN", SND_SOC_NOPM, 0, 0,
&adcx140_dapm_ch5_en_switch),
SND_SOC_DAPM_SWITCH("CH6_ASI_EN", SND_SOC_NOPM, 0, 0,
&adcx140_dapm_ch6_en_switch),
SND_SOC_DAPM_SWITCH("CH7_ASI_EN", SND_SOC_NOPM, 0, 0,
&adcx140_dapm_ch7_en_switch),
SND_SOC_DAPM_SWITCH("CH8_ASI_EN", SND_SOC_NOPM, 0, 0,
&adcx140_dapm_ch8_en_switch),
SND_SOC_DAPM_SWITCH("DRE_ENABLE", SND_SOC_NOPM, 0, 0,
&adcx140_dapm_dre_en_switch),
SND_SOC_DAPM_SWITCH("CH1_DRE_EN", SND_SOC_NOPM, 0, 0,
&adcx140_dapm_ch1_dre_en_switch),
SND_SOC_DAPM_SWITCH("CH2_DRE_EN", SND_SOC_NOPM, 0, 0,
&adcx140_dapm_ch2_dre_en_switch),
SND_SOC_DAPM_SWITCH("CH3_DRE_EN", SND_SOC_NOPM, 0, 0,
&adcx140_dapm_ch3_dre_en_switch),
SND_SOC_DAPM_SWITCH("CH4_DRE_EN", SND_SOC_NOPM, 0, 0,
&adcx140_dapm_ch4_dre_en_switch),
SND_SOC_DAPM_MUX("IN1 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
in1_resistor_controls),
SND_SOC_DAPM_MUX("IN2 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
in2_resistor_controls),
SND_SOC_DAPM_MUX("IN3 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
in3_resistor_controls),
SND_SOC_DAPM_MUX("IN4 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
in4_resistor_controls),
SND_SOC_DAPM_MUX("PDM Clk Div Select", SND_SOC_NOPM, 0, 0,
pdmclk_div_controls),
SND_SOC_DAPM_MUX("Decimation Filter", SND_SOC_NOPM, 0, 0,
decimation_filter_controls),
};
static const struct snd_soc_dapm_route adcx140_audio_map[] = {
/* Outputs */
{"CH1_OUT", NULL, "Output Mixer"},
{"CH2_OUT", NULL, "Output Mixer"},
{"CH3_OUT", NULL, "Output Mixer"},
{"CH4_OUT", NULL, "Output Mixer"},
{"CH1_ASI_EN", "Switch", "CH1_ADC"},
{"CH2_ASI_EN", "Switch", "CH2_ADC"},
{"CH3_ASI_EN", "Switch", "CH3_ADC"},
{"CH4_ASI_EN", "Switch", "CH4_ADC"},
{"CH1_ASI_EN", "Switch", "CH1_DIG"},
{"CH2_ASI_EN", "Switch", "CH2_DIG"},
{"CH3_ASI_EN", "Switch", "CH3_DIG"},
{"CH4_ASI_EN", "Switch", "CH4_DIG"},
{"CH5_ASI_EN", "Switch", "CH5_DIG"},
{"CH6_ASI_EN", "Switch", "CH6_DIG"},
{"CH7_ASI_EN", "Switch", "CH7_DIG"},
{"CH8_ASI_EN", "Switch", "CH8_DIG"},
{"CH5_ASI_EN", "Switch", "CH5_OUT"},
{"CH6_ASI_EN", "Switch", "CH6_OUT"},
{"CH7_ASI_EN", "Switch", "CH7_OUT"},
{"CH8_ASI_EN", "Switch", "CH8_OUT"},
{"Decimation Filter", "Linear Phase", "DRE_ENABLE"},
{"Decimation Filter", "Low Latency", "DRE_ENABLE"},
{"Decimation Filter", "Ultra-low Latency", "DRE_ENABLE"},
{"DRE_ENABLE", "Switch", "CH1_DRE_EN"},
{"DRE_ENABLE", "Switch", "CH2_DRE_EN"},
{"DRE_ENABLE", "Switch", "CH3_DRE_EN"},
{"DRE_ENABLE", "Switch", "CH4_DRE_EN"},
{"CH1_DRE_EN", "Switch", "CH1_ADC"},
{"CH2_DRE_EN", "Switch", "CH2_ADC"},
{"CH3_DRE_EN", "Switch", "CH3_ADC"},
{"CH4_DRE_EN", "Switch", "CH4_ADC"},
/* Mic input */
{"CH1_ADC", NULL, "MIC_GAIN_CTL_CH1"},
{"CH2_ADC", NULL, "MIC_GAIN_CTL_CH2"},
{"CH3_ADC", NULL, "MIC_GAIN_CTL_CH3"},
{"CH4_ADC", NULL, "MIC_GAIN_CTL_CH4"},
{"MIC_GAIN_CTL_CH1", NULL, "IN1 Analog Mic Resistor"},
{"MIC_GAIN_CTL_CH1", NULL, "IN1 Analog Mic Resistor"},
{"MIC_GAIN_CTL_CH2", NULL, "IN2 Analog Mic Resistor"},
{"MIC_GAIN_CTL_CH2", NULL, "IN2 Analog Mic Resistor"},
{"MIC_GAIN_CTL_CH3", NULL, "IN3 Analog Mic Resistor"},
{"MIC_GAIN_CTL_CH3", NULL, "IN3 Analog Mic Resistor"},
{"MIC_GAIN_CTL_CH4", NULL, "IN4 Analog Mic Resistor"},
{"MIC_GAIN_CTL_CH4", NULL, "IN4 Analog Mic Resistor"},
{"IN1 Analog Mic Resistor", "2.5 kOhm", "MIC1P Input Mux"},
{"IN1 Analog Mic Resistor", "10 kOhm", "MIC1P Input Mux"},
{"IN1 Analog Mic Resistor", "20 kOhm", "MIC1P Input Mux"},
{"IN1 Analog Mic Resistor", "2.5 kOhm", "MIC1M Input Mux"},
{"IN1 Analog Mic Resistor", "10 kOhm", "MIC1M Input Mux"},
{"IN1 Analog Mic Resistor", "20 kOhm", "MIC1M Input Mux"},
{"IN2 Analog Mic Resistor", "2.5 kOhm", "MIC2P Input Mux"},
{"IN2 Analog Mic Resistor", "10 kOhm", "MIC2P Input Mux"},
{"IN2 Analog Mic Resistor", "20 kOhm", "MIC2P Input Mux"},
{"IN2 Analog Mic Resistor", "2.5 kOhm", "MIC2M Input Mux"},
{"IN2 Analog Mic Resistor", "10 kOhm", "MIC2M Input Mux"},
{"IN2 Analog Mic Resistor", "20 kOhm", "MIC2M Input Mux"},
{"IN3 Analog Mic Resistor", "2.5 kOhm", "MIC3P Input Mux"},
{"IN3 Analog Mic Resistor", "10 kOhm", "MIC3P Input Mux"},
{"IN3 Analog Mic Resistor", "20 kOhm", "MIC3P Input Mux"},
{"IN3 Analog Mic Resistor", "2.5 kOhm", "MIC3M Input Mux"},
{"IN3 Analog Mic Resistor", "10 kOhm", "MIC3M Input Mux"},
{"IN3 Analog Mic Resistor", "20 kOhm", "MIC3M Input Mux"},
{"IN4 Analog Mic Resistor", "2.5 kOhm", "MIC4P Input Mux"},
{"IN4 Analog Mic Resistor", "10 kOhm", "MIC4P Input Mux"},
{"IN4 Analog Mic Resistor", "20 kOhm", "MIC4P Input Mux"},
{"IN4 Analog Mic Resistor", "2.5 kOhm", "MIC4M Input Mux"},
{"IN4 Analog Mic Resistor", "10 kOhm", "MIC4M Input Mux"},
{"IN4 Analog Mic Resistor", "20 kOhm", "MIC4M Input Mux"},
{"PDM Clk Div Select", "2.8224 MHz", "MIC1P Input Mux"},
{"PDM Clk Div Select", "1.4112 MHz", "MIC1P Input Mux"},
{"PDM Clk Div Select", "705.6 kHz", "MIC1P Input Mux"},
{"PDM Clk Div Select", "5.6448 MHz", "MIC1P Input Mux"},
{"MIC1P Input Mux", NULL, "CH1_DIG"},
{"MIC1M Input Mux", NULL, "CH2_DIG"},
{"MIC2P Input Mux", NULL, "CH3_DIG"},
{"MIC2M Input Mux", NULL, "CH4_DIG"},
{"MIC3P Input Mux", NULL, "CH5_DIG"},
{"MIC3M Input Mux", NULL, "CH6_DIG"},
{"MIC4P Input Mux", NULL, "CH7_DIG"},
{"MIC4M Input Mux", NULL, "CH8_DIG"},
{"MIC1 Analog Mux", "Line In", "MIC1P"},
{"MIC2 Analog Mux", "Line In", "MIC2P"},
{"MIC3 Analog Mux", "Line In", "MIC3P"},
{"MIC4 Analog Mux", "Line In", "MIC4P"},
{"MIC1P Input Mux", "Analog", "MIC1P"},
{"MIC1M Input Mux", "Analog", "MIC1M"},
{"MIC2P Input Mux", "Analog", "MIC2P"},
{"MIC2M Input Mux", "Analog", "MIC2M"},
{"MIC3P Input Mux", "Analog", "MIC3P"},
{"MIC3M Input Mux", "Analog", "MIC3M"},
{"MIC4P Input Mux", "Analog", "MIC4P"},
{"MIC4M Input Mux", "Analog", "MIC4M"},
{"MIC1P Input Mux", "Digital", "MIC1P"},
{"MIC1M Input Mux", "Digital", "MIC1M"},
{"MIC2P Input Mux", "Digital", "MIC2P"},
{"MIC2M Input Mux", "Digital", "MIC2M"},
{"MIC3P Input Mux", "Digital", "MIC3P"},
{"MIC3M Input Mux", "Digital", "MIC3M"},
{"MIC4P Input Mux", "Digital", "MIC4P"},
{"MIC4M Input Mux", "Digital", "MIC4M"},
};
#define ADCX140_PHASE_CALIB_SWITCH(xname) {\
.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
.access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
.info = adcx140_phase_calib_info, \
.get = adcx140_phase_calib_get, \
.put = adcx140_phase_calib_put}
static int adcx140_phase_calib_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
uinfo->count = 1;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = 1;
return 0;
}
static int adcx140_phase_calib_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *value)
{
struct snd_soc_component *codec =
snd_soc_kcontrol_component(kcontrol);
struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(codec);
value->value.integer.value[0] = adcx140->phase_calib_on ? 1 : 0;
return 0;
}
static int adcx140_phase_calib_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *value)
{
struct snd_soc_component *codec
= snd_soc_kcontrol_component(kcontrol);
struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(codec);
bool v = value->value.integer.value[0] ? true : false;
if (adcx140->phase_calib_on != v) {
adcx140->phase_calib_on = v;
return 1;
}
return 0;
}
static const struct snd_kcontrol_new adcx140_snd_controls[] = {
SOC_SINGLE_TLV("Analog CH1 Mic Gain Volume", ADCX140_CH1_CFG1, 2, 42, 0,
adc_tlv),
SOC_SINGLE_TLV("Analog CH2 Mic Gain Volume", ADCX140_CH2_CFG1, 2, 42, 0,
adc_tlv),
SOC_SINGLE_TLV("Analog CH3 Mic Gain Volume", ADCX140_CH3_CFG1, 2, 42, 0,
adc_tlv),
SOC_SINGLE_TLV("Analog CH4 Mic Gain Volume", ADCX140_CH4_CFG1, 2, 42, 0,
adc_tlv),
SOC_SINGLE_TLV("DRE Threshold", ADCX140_DRE_CFG0, 4, 9, 0,
dre_thresh_tlv),
SOC_SINGLE_TLV("DRE Max Gain", ADCX140_DRE_CFG0, 0, 12, 0,
dre_gain_tlv),
SOC_SINGLE_TLV("AGC Threshold", ADCX140_AGC_CFG0, 4, 15, 0,
agc_thresh_tlv),
SOC_SINGLE_TLV("AGC Max Gain", ADCX140_AGC_CFG0, 0, 13, 0,
agc_gain_tlv),
SOC_SINGLE_TLV("Digital CH1 Out Volume", ADCX140_CH1_CFG2,
0, 0xff, 0, dig_vol_tlv),
SOC_SINGLE_TLV("Digital CH2 Out Volume", ADCX140_CH2_CFG2,
0, 0xff, 0, dig_vol_tlv),
SOC_SINGLE_TLV("Digital CH3 Out Volume", ADCX140_CH3_CFG2,
0, 0xff, 0, dig_vol_tlv),
SOC_SINGLE_TLV("Digital CH4 Out Volume", ADCX140_CH4_CFG2,
0, 0xff, 0, dig_vol_tlv),
SOC_SINGLE_TLV("Digital CH5 Out Volume", ADCX140_CH5_CFG2,
0, 0xff, 0, dig_vol_tlv),
SOC_SINGLE_TLV("Digital CH6 Out Volume", ADCX140_CH6_CFG2,
0, 0xff, 0, dig_vol_tlv),
SOC_SINGLE_TLV("Digital CH7 Out Volume", ADCX140_CH7_CFG2,
0, 0xff, 0, dig_vol_tlv),
SOC_SINGLE_TLV("Digital CH8 Out Volume", ADCX140_CH8_CFG2,
0, 0xff, 0, dig_vol_tlv),
ADCX140_PHASE_CALIB_SWITCH("Phase Calibration Switch"),
};
static int adcx140_reset(struct adcx140_priv *adcx140)
{
int ret = 0;
if (adcx140->gpio_reset) {
gpiod_direction_output(adcx140->gpio_reset, 0);
/* 8.4.1: wait for hw shutdown (25ms) + >= 1ms */
usleep_range(30000, 100000);
gpiod_direction_output(adcx140->gpio_reset, 1);
} else {
ret = regmap_write(adcx140->regmap, ADCX140_SW_RESET,
ADCX140_RESET);
}
/* 8.4.2: wait >= 10 ms after entering sleep mode. */
usleep_range(10000, 100000);
return ret;
}
static void adcx140_pwr_ctrl(struct adcx140_priv *adcx140, bool power_state)
{
int pwr_ctrl = 0;
int ret = 0;
struct snd_soc_component *component = adcx140->component;
if (power_state)
pwr_ctrl = ADCX140_PWR_CFG_ADC_PDZ | ADCX140_PWR_CFG_PLL_PDZ;
if (adcx140->micbias_vg && power_state)
pwr_ctrl |= ADCX140_PWR_CFG_BIAS_PDZ;
if (pwr_ctrl) {
ret = regmap_write(adcx140->regmap, ADCX140_PHASE_CALIB,
adcx140->phase_calib_on ? 0x00 : 0x40);
if (ret)
dev_err(component->dev, "%s: register write error %d\n",
__func__, ret);
}
regmap_update_bits(adcx140->regmap, ADCX140_PWR_CFG,
ADCX140_PWR_CTRL_MSK, pwr_ctrl);
}
static int adcx140_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
u8 data = 0;
switch (params_width(params)) {
case 16:
data = ADCX140_16_BIT_WORD;
break;
case 20:
data = ADCX140_20_BIT_WORD;
break;
case 24:
data = ADCX140_24_BIT_WORD;
break;
case 32:
data = ADCX140_32_BIT_WORD;
break;
default:
dev_err(component->dev, "%s: Unsupported width %d\n",
__func__, params_width(params));
return -EINVAL;
}
adcx140_pwr_ctrl(adcx140, false);
snd_soc_component_update_bits(component, ADCX140_ASI_CFG0,
ADCX140_WORD_LEN_MSK, data);
adcx140_pwr_ctrl(adcx140, true);
return 0;
}
static int adcx140_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
u8 iface_reg1 = 0;
u8 iface_reg2 = 0;
int offset = 0;
bool inverted_bclk = false;
/* set master/slave audio interface */
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
iface_reg2 |= ADCX140_BCLK_FSYNC_MASTER;
break;
case SND_SOC_DAIFMT_CBC_CFC:
break;
default:
dev_err(component->dev, "Invalid DAI clock provider\n");
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface_reg1 |= ADCX140_I2S_MODE_BIT;
break;
case SND_SOC_DAIFMT_LEFT_J:
iface_reg1 |= ADCX140_LEFT_JUST_BIT;
break;
case SND_SOC_DAIFMT_DSP_A:
offset = 1;
inverted_bclk = true;
break;
case SND_SOC_DAIFMT_DSP_B:
inverted_bclk = true;
break;
default:
dev_err(component->dev, "Invalid DAI interface format\n");
return -EINVAL;
}
/* signal polarity */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_IB_NF:
case SND_SOC_DAIFMT_IB_IF:
inverted_bclk = !inverted_bclk;
break;
case SND_SOC_DAIFMT_NB_IF:
iface_reg1 |= ADCX140_FSYNCINV_BIT;
break;
case SND_SOC_DAIFMT_NB_NF:
break;
default:
dev_err(component->dev, "Invalid DAI clock signal polarity\n");
return -EINVAL;
}
if (inverted_bclk)
iface_reg1 |= ADCX140_BCLKINV_BIT;
adcx140->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
adcx140_pwr_ctrl(adcx140, false);
snd_soc_component_update_bits(component, ADCX140_ASI_CFG0,
ADCX140_FSYNCINV_BIT |
ADCX140_BCLKINV_BIT |
ADCX140_ASI_FORMAT_MSK,
iface_reg1);
snd_soc_component_update_bits(component, ADCX140_MST_CFG0,
ADCX140_BCLK_FSYNC_MASTER, iface_reg2);
/* Configure data offset */
snd_soc_component_update_bits(component, ADCX140_ASI_CFG1,
ADCX140_TX_OFFSET_MASK, offset);
adcx140_pwr_ctrl(adcx140, true);
return 0;
}
static int adcx140_set_dai_tdm_slot(struct snd_soc_dai *codec_dai,
unsigned int tx_mask, unsigned int rx_mask,
int slots, int slot_width)
{
struct snd_soc_component *component = codec_dai->component;
struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
/*
* The chip itself supports arbitrary masks, but the driver currently
* only supports adjacent slots beginning at the first slot.
*/
if (tx_mask != GENMASK(__fls(tx_mask), 0)) {
dev_err(component->dev, "Only lower adjacent slots are supported\n");
return -EINVAL;
}
switch (slot_width) {
case 16:
case 20:
case 24:
case 32:
break;
default:
dev_err(component->dev, "Unsupported slot width %d\n", slot_width);
return -EINVAL;
}
adcx140->slot_width = slot_width;
return 0;
}
static const struct snd_soc_dai_ops adcx140_dai_ops = {
.hw_params = adcx140_hw_params,
.set_fmt = adcx140_set_dai_fmt,
.set_tdm_slot = adcx140_set_dai_tdm_slot,
};
static int adcx140_configure_gpo(struct adcx140_priv *adcx140)
{
u32 gpo_outputs[ADCX140_NUM_GPOS];
u32 gpo_output_val = 0;
int ret;
int i;
for (i = 0; i < ADCX140_NUM_GPOS; i++) {
ret = device_property_read_u32_array(adcx140->dev,
gpo_config_names[i],
gpo_outputs,
ADCX140_NUM_GPO_CFGS);
if (ret)
continue;
if (gpo_outputs[0] > ADCX140_GPO_CFG_MAX) {
dev_err(adcx140->dev, "GPO%d config out of range\n", i + 1);
return -EINVAL;
}
if (gpo_outputs[1] > ADCX140_GPO_DRV_MAX) {
dev_err(adcx140->dev, "GPO%d drive out of range\n", i + 1);
return -EINVAL;
}
gpo_output_val = gpo_outputs[0] << ADCX140_GPO_SHIFT |
gpo_outputs[1];
ret = regmap_write(adcx140->regmap, ADCX140_GPO_CFG0 + i,
gpo_output_val);
if (ret)
return ret;
}
return 0;
}
static int adcx140_configure_gpio(struct adcx140_priv *adcx140)
{
int gpio_count = 0;
u32 gpio_outputs[ADCX140_NUM_GPIO_CFGS];
u32 gpio_output_val = 0;
int ret;
gpio_count = device_property_count_u32(adcx140->dev,
"ti,gpio-config");
if (gpio_count <= 0)
return 0;
if (gpio_count != ADCX140_NUM_GPIO_CFGS)
return -EINVAL;
ret = device_property_read_u32_array(adcx140->dev, "ti,gpio-config",
gpio_outputs, gpio_count);
if (ret)
return ret;
if (gpio_outputs[0] > ADCX140_GPIO_CFG_MAX) {
dev_err(adcx140->dev, "GPIO config out of range\n");
return -EINVAL;
}
if (gpio_outputs[1] > ADCX140_GPIO_DRV_MAX) {
dev_err(adcx140->dev, "GPIO drive out of range\n");
return -EINVAL;
}
gpio_output_val = gpio_outputs[0] << ADCX140_GPIO_SHIFT
| gpio_outputs[1];
return regmap_write(adcx140->regmap, ADCX140_GPIO_CFG0, gpio_output_val);
}
static int adcx140_codec_probe(struct snd_soc_component *component)
{
struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
int sleep_cfg_val = ADCX140_WAKE_DEV;
u32 bias_source;
u32 vref_source;
u8 bias_cfg;
int pdm_count;
u32 pdm_edges[ADCX140_NUM_PDM_EDGES];
u32 pdm_edge_val = 0;
int gpi_count;
u32 gpi_inputs[ADCX140_NUM_GPI_PINS];
u32 gpi_input_val = 0;
int i;
int ret;
bool tx_high_z;
ret = device_property_read_u32(adcx140->dev, "ti,mic-bias-source",
&bias_source);
if (ret || bias_source > ADCX140_MIC_BIAS_VAL_AVDD) {
bias_source = ADCX140_MIC_BIAS_VAL_VREF;
adcx140->micbias_vg = false;
} else {
adcx140->micbias_vg = true;
}
ret = device_property_read_u32(adcx140->dev, "ti,vref-source",
&vref_source);
if (ret)
vref_source = ADCX140_MIC_BIAS_VREF_275V;
if (vref_source > ADCX140_MIC_BIAS_VREF_1375V) {
dev_err(adcx140->dev, "Mic Bias source value is invalid\n");
return -EINVAL;
}
bias_cfg = bias_source << ADCX140_MIC_BIAS_SHIFT | vref_source;
ret = adcx140_reset(adcx140);
if (ret)
goto out;
if (adcx140->supply_areg == NULL)
sleep_cfg_val |= ADCX140_AREG_INTERNAL;
ret = regmap_write(adcx140->regmap, ADCX140_SLEEP_CFG, sleep_cfg_val);
if (ret) {
dev_err(adcx140->dev, "setting sleep config failed %d\n", ret);
goto out;
}
/* 8.4.3: Wait >= 1ms after entering active mode. */
usleep_range(1000, 100000);
pdm_count = device_property_count_u32(adcx140->dev,
"ti,pdm-edge-select");
if (pdm_count <= ADCX140_NUM_PDM_EDGES && pdm_count > 0) {
ret = device_property_read_u32_array(adcx140->dev,
"ti,pdm-edge-select",
pdm_edges, pdm_count);
if (ret)
return ret;
for (i = 0; i < pdm_count; i++)
pdm_edge_val |= pdm_edges[i] << (ADCX140_PDM_EDGE_SHIFT - i);
ret = regmap_write(adcx140->regmap, ADCX140_PDM_CFG,
pdm_edge_val);
if (ret)
return ret;
}
gpi_count = device_property_count_u32(adcx140->dev, "ti,gpi-config");
if (gpi_count <= ADCX140_NUM_GPI_PINS && gpi_count > 0) {
ret = device_property_read_u32_array(adcx140->dev,
"ti,gpi-config",
gpi_inputs, gpi_count);
if (ret)
return ret;
gpi_input_val = gpi_inputs[ADCX140_GPI1_INDEX] << ADCX140_GPI_SHIFT |
gpi_inputs[ADCX140_GPI2_INDEX];
ret = regmap_write(adcx140->regmap, ADCX140_GPI_CFG0,
gpi_input_val);
if (ret)
return ret;
gpi_input_val = gpi_inputs[ADCX140_GPI3_INDEX] << ADCX140_GPI_SHIFT |
gpi_inputs[ADCX140_GPI4_INDEX];
ret = regmap_write(adcx140->regmap, ADCX140_GPI_CFG1,
gpi_input_val);
if (ret)
return ret;
}
ret = adcx140_configure_gpio(adcx140);
if (ret)
return ret;
ret = adcx140_configure_gpo(adcx140);
if (ret)
goto out;
ret = regmap_update_bits(adcx140->regmap, ADCX140_BIAS_CFG,
ADCX140_MIC_BIAS_VAL_MSK |
ADCX140_MIC_BIAS_VREF_MSK, bias_cfg);
if (ret)
dev_err(adcx140->dev, "setting MIC bias failed %d\n", ret);
tx_high_z = device_property_read_bool(adcx140->dev, "ti,asi-tx-drive");
if (tx_high_z) {
ret = regmap_update_bits(adcx140->regmap, ADCX140_ASI_CFG0,
ADCX140_TX_FILL, ADCX140_TX_FILL);
if (ret) {
dev_err(adcx140->dev, "Setting Tx drive failed %d\n", ret);
goto out;
}
}
adcx140_pwr_ctrl(adcx140, true);
out:
return ret;
}
static int adcx140_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_ON:
case SND_SOC_BIAS_PREPARE:
case SND_SOC_BIAS_STANDBY:
adcx140_pwr_ctrl(adcx140, true);
break;
case SND_SOC_BIAS_OFF:
adcx140_pwr_ctrl(adcx140, false);
break;
}
return 0;
}
static const struct snd_soc_component_driver soc_codec_driver_adcx140 = {
.probe = adcx140_codec_probe,
.set_bias_level = adcx140_set_bias_level,
.controls = adcx140_snd_controls,
.num_controls = ARRAY_SIZE(adcx140_snd_controls),
.dapm_widgets = adcx140_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(adcx140_dapm_widgets),
.dapm_routes = adcx140_audio_map,
.num_dapm_routes = ARRAY_SIZE(adcx140_audio_map),
.suspend_bias_off = 1,
.idle_bias_on = 0,
.use_pmdown_time = 1,
.endianness = 1,
};
static struct snd_soc_dai_driver adcx140_dai_driver[] = {
{
.name = "tlv320adcx140-codec",
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = ADCX140_MAX_CHANNELS,
.rates = ADCX140_RATES,
.formats = ADCX140_FORMATS,
},
.ops = &adcx140_dai_ops,
.symmetric_rate = 1,
}
};
#ifdef CONFIG_OF
static const struct of_device_id tlv320adcx140_of_match[] = {
{ .compatible = "ti,tlv320adc3140" },
{ .compatible = "ti,tlv320adc5140" },
{ .compatible = "ti,tlv320adc6140" },
{},
};
MODULE_DEVICE_TABLE(of, tlv320adcx140_of_match);
#endif
static void adcx140_disable_regulator(void *arg)
{
struct adcx140_priv *adcx140 = arg;
regulator_disable(adcx140->supply_areg);
}
static int adcx140_i2c_probe(struct i2c_client *i2c)
{
struct adcx140_priv *adcx140;
int ret;
adcx140 = devm_kzalloc(&i2c->dev, sizeof(*adcx140), GFP_KERNEL);
if (!adcx140)
return -ENOMEM;
adcx140->phase_calib_on = false;
adcx140->dev = &i2c->dev;
adcx140->gpio_reset = devm_gpiod_get_optional(adcx140->dev,
"reset", GPIOD_OUT_LOW);
if (IS_ERR(adcx140->gpio_reset))
dev_info(&i2c->dev, "Reset GPIO not defined\n");
adcx140->supply_areg = devm_regulator_get_optional(adcx140->dev,
"areg");
if (IS_ERR(adcx140->supply_areg)) {
if (PTR_ERR(adcx140->supply_areg) == -EPROBE_DEFER)
return -EPROBE_DEFER;
adcx140->supply_areg = NULL;
} else {
ret = regulator_enable(adcx140->supply_areg);
if (ret) {
dev_err(adcx140->dev, "Failed to enable areg\n");
return ret;
}
ret = devm_add_action_or_reset(&i2c->dev, adcx140_disable_regulator, adcx140);
if (ret)
return ret;
}
adcx140->regmap = devm_regmap_init_i2c(i2c, &adcx140_i2c_regmap);
if (IS_ERR(adcx140->regmap)) {
ret = PTR_ERR(adcx140->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
i2c_set_clientdata(i2c, adcx140);
return devm_snd_soc_register_component(&i2c->dev,
&soc_codec_driver_adcx140,
adcx140_dai_driver, 1);
}
static const struct i2c_device_id adcx140_i2c_id[] = {
{ "tlv320adc3140", 0 },
{ "tlv320adc5140", 1 },
{ "tlv320adc6140", 2 },
{}
};
MODULE_DEVICE_TABLE(i2c, adcx140_i2c_id);
static struct i2c_driver adcx140_i2c_driver = {
.driver = {
.name = "tlv320adcx140-codec",
.of_match_table = of_match_ptr(tlv320adcx140_of_match),
},
.probe = adcx140_i2c_probe,
.id_table = adcx140_i2c_id,
};
module_i2c_driver(adcx140_i2c_driver);
MODULE_AUTHOR("Dan Murphy <[email protected]>");
MODULE_DESCRIPTION("ASoC TLV320ADCX140 CODEC Driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/tlv320adcx140.c |
// SPDX-License-Identifier: GPL-2.0-or-later
//
// File: sound/soc/codecs/ssm2602.c
// Author: Cliff Cai <[email protected]>
//
// Created: Tue June 06 2008
// Description: Driver for ssm2602 sound chip
//
// Modified:
// Copyright 2008 Analog Devices Inc.
//
// Bugs: Enter bugs at http://blackfin.uclinux.org/
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include "ssm2602.h"
/* codec private data */
struct ssm2602_priv {
unsigned int sysclk;
const struct snd_pcm_hw_constraint_list *sysclk_constraints;
struct regmap *regmap;
enum ssm2602_type type;
unsigned int clk_out_pwr;
};
/*
* ssm2602 register cache
* We can't read the ssm2602 register space when we are
* using 2 wire for device control, so we cache them instead.
* There is no point in caching the reset register
*/
static const struct reg_default ssm2602_reg[SSM2602_CACHEREGNUM] = {
{ .reg = 0x00, .def = 0x0097 },
{ .reg = 0x01, .def = 0x0097 },
{ .reg = 0x02, .def = 0x0079 },
{ .reg = 0x03, .def = 0x0079 },
{ .reg = 0x04, .def = 0x000a },
{ .reg = 0x05, .def = 0x0008 },
{ .reg = 0x06, .def = 0x009f },
{ .reg = 0x07, .def = 0x000a },
{ .reg = 0x08, .def = 0x0000 },
{ .reg = 0x09, .def = 0x0000 }
};
/*
* ssm2602 register patch
* Workaround for playback distortions after power up: activates digital
* core, and then powers on output, DAC, and whole chip at the same time
*/
static const struct reg_sequence ssm2602_patch[] = {
{ SSM2602_ACTIVE, 0x01 },
{ SSM2602_PWR, 0x07 },
{ SSM2602_RESET, 0x00 },
};
/*Appending several "None"s just for OSS mixer use*/
static const char *ssm2602_input_select[] = {
"Line", "Mic",
};
static const char *ssm2602_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"};
static const struct soc_enum ssm2602_enum[] = {
SOC_ENUM_SINGLE(SSM2602_APANA, 2, ARRAY_SIZE(ssm2602_input_select),
ssm2602_input_select),
SOC_ENUM_SINGLE(SSM2602_APDIGI, 1, ARRAY_SIZE(ssm2602_deemph),
ssm2602_deemph),
};
static const DECLARE_TLV_DB_RANGE(ssm260x_outmix_tlv,
0, 47, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0),
48, 127, TLV_DB_SCALE_ITEM(-7400, 100, 0)
);
static const DECLARE_TLV_DB_SCALE(ssm260x_inpga_tlv, -3450, 150, 0);
static const DECLARE_TLV_DB_SCALE(ssm260x_sidetone_tlv, -1500, 300, 0);
static const struct snd_kcontrol_new ssm260x_snd_controls[] = {
SOC_DOUBLE_R_TLV("Capture Volume", SSM2602_LINVOL, SSM2602_RINVOL, 0, 45, 0,
ssm260x_inpga_tlv),
SOC_DOUBLE_R("Capture Switch", SSM2602_LINVOL, SSM2602_RINVOL, 7, 1, 1),
SOC_SINGLE("ADC High Pass Filter Switch", SSM2602_APDIGI, 0, 1, 1),
SOC_SINGLE("Store DC Offset Switch", SSM2602_APDIGI, 4, 1, 0),
SOC_ENUM("Playback De-emphasis", ssm2602_enum[1]),
};
static const struct snd_kcontrol_new ssm2602_snd_controls[] = {
SOC_DOUBLE_R_TLV("Master Playback Volume", SSM2602_LOUT1V, SSM2602_ROUT1V,
0, 127, 0, ssm260x_outmix_tlv),
SOC_DOUBLE_R("Master Playback ZC Switch", SSM2602_LOUT1V, SSM2602_ROUT1V,
7, 1, 0),
SOC_SINGLE_TLV("Sidetone Playback Volume", SSM2602_APANA, 6, 3, 1,
ssm260x_sidetone_tlv),
SOC_SINGLE("Mic Boost (+20dB)", SSM2602_APANA, 0, 1, 0),
SOC_SINGLE("Mic Boost2 (+20dB)", SSM2602_APANA, 8, 1, 0),
};
/* Output Mixer */
static const struct snd_kcontrol_new ssm260x_output_mixer_controls[] = {
SOC_DAPM_SINGLE("Line Bypass Switch", SSM2602_APANA, 3, 1, 0),
SOC_DAPM_SINGLE("HiFi Playback Switch", SSM2602_APANA, 4, 1, 0),
SOC_DAPM_SINGLE("Mic Sidetone Switch", SSM2602_APANA, 5, 1, 0),
};
static const struct snd_kcontrol_new mic_ctl =
SOC_DAPM_SINGLE("Switch", SSM2602_APANA, 1, 1, 1);
/* Input mux */
static const struct snd_kcontrol_new ssm2602_input_mux_controls =
SOC_DAPM_ENUM("Input Select", ssm2602_enum[0]);
static int ssm2602_mic_switch_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
/*
* According to the ssm2603 data sheet (control register sequencing),
* the digital core should be activated only after all necessary bits
* in the power register are enabled, and a delay determined by the
* decoupling capacitor on the VMID pin has passed. If the digital core
* is activated too early, or even before the ADC is powered up, audible
* artifacts appear at the beginning and end of the recorded signal.
*
* In practice, audible artifacts disappear well over 500 ms.
*/
msleep(500);
return 0;
}
static const struct snd_soc_dapm_widget ssm260x_dapm_widgets[] = {
SND_SOC_DAPM_DAC("DAC", "HiFi Playback", SSM2602_PWR, 3, 1),
SND_SOC_DAPM_ADC("ADC", "HiFi Capture", SSM2602_PWR, 2, 1),
SND_SOC_DAPM_PGA("Line Input", SSM2602_PWR, 0, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("Digital Core Power", SSM2602_ACTIVE, 0, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("LOUT"),
SND_SOC_DAPM_OUTPUT("ROUT"),
SND_SOC_DAPM_INPUT("RLINEIN"),
SND_SOC_DAPM_INPUT("LLINEIN"),
};
static const struct snd_soc_dapm_widget ssm2602_dapm_widgets[] = {
SND_SOC_DAPM_MIXER("Output Mixer", SSM2602_PWR, 4, 1,
ssm260x_output_mixer_controls,
ARRAY_SIZE(ssm260x_output_mixer_controls)),
SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0, &ssm2602_input_mux_controls),
SND_SOC_DAPM_MICBIAS("Mic Bias", SSM2602_PWR, 1, 1),
SND_SOC_DAPM_SWITCH_E("Mic Switch", SSM2602_APANA, 1, 1, &mic_ctl,
ssm2602_mic_switch_event, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_OUTPUT("LHPOUT"),
SND_SOC_DAPM_OUTPUT("RHPOUT"),
SND_SOC_DAPM_INPUT("MICIN"),
};
static const struct snd_soc_dapm_widget ssm2604_dapm_widgets[] = {
SND_SOC_DAPM_MIXER("Output Mixer", SND_SOC_NOPM, 0, 0,
ssm260x_output_mixer_controls,
ARRAY_SIZE(ssm260x_output_mixer_controls) - 1), /* Last element is the mic */
};
static const struct snd_soc_dapm_route ssm260x_routes[] = {
{"DAC", NULL, "Digital Core Power"},
{"ADC", NULL, "Digital Core Power"},
{"Output Mixer", "Line Bypass Switch", "Line Input"},
{"Output Mixer", "HiFi Playback Switch", "DAC"},
{"ROUT", NULL, "Output Mixer"},
{"LOUT", NULL, "Output Mixer"},
{"Line Input", NULL, "LLINEIN"},
{"Line Input", NULL, "RLINEIN"},
};
static const struct snd_soc_dapm_route ssm2602_routes[] = {
{"Output Mixer", "Mic Sidetone Switch", "Mic Bias"},
{"RHPOUT", NULL, "Output Mixer"},
{"LHPOUT", NULL, "Output Mixer"},
{"Input Mux", "Line", "Line Input"},
{"Input Mux", "Mic", "Mic Switch"},
{"ADC", NULL, "Input Mux"},
{"Mic Switch", NULL, "Mic Bias"},
{"Mic Bias", NULL, "MICIN"},
};
static const struct snd_soc_dapm_route ssm2604_routes[] = {
{"ADC", NULL, "Line Input"},
};
static const unsigned int ssm2602_rates_12288000[] = {
8000, 16000, 32000, 48000, 96000,
};
static const struct snd_pcm_hw_constraint_list ssm2602_constraints_12288000 = {
.list = ssm2602_rates_12288000,
.count = ARRAY_SIZE(ssm2602_rates_12288000),
};
static const unsigned int ssm2602_rates_11289600[] = {
8000, 11025, 22050, 44100, 88200,
};
static const struct snd_pcm_hw_constraint_list ssm2602_constraints_11289600 = {
.list = ssm2602_rates_11289600,
.count = ARRAY_SIZE(ssm2602_rates_11289600),
};
struct ssm2602_coeff {
u32 mclk;
u32 rate;
u8 srate;
};
#define SSM2602_COEFF_SRATE(sr, bosr, usb) (((sr) << 2) | ((bosr) << 1) | (usb))
/* codec mclk clock coefficients */
static const struct ssm2602_coeff ssm2602_coeff_table[] = {
/* 48k */
{12288000, 48000, SSM2602_COEFF_SRATE(0x0, 0x0, 0x0)},
{18432000, 48000, SSM2602_COEFF_SRATE(0x0, 0x1, 0x0)},
{12000000, 48000, SSM2602_COEFF_SRATE(0x0, 0x0, 0x1)},
/* 32k */
{12288000, 32000, SSM2602_COEFF_SRATE(0x6, 0x0, 0x0)},
{18432000, 32000, SSM2602_COEFF_SRATE(0x6, 0x1, 0x0)},
{12000000, 32000, SSM2602_COEFF_SRATE(0x6, 0x0, 0x1)},
/* 16k */
{12288000, 16000, SSM2602_COEFF_SRATE(0x5, 0x0, 0x0)},
{18432000, 16000, SSM2602_COEFF_SRATE(0x5, 0x1, 0x0)},
{12000000, 16000, SSM2602_COEFF_SRATE(0xa, 0x0, 0x1)},
/* 8k */
{12288000, 8000, SSM2602_COEFF_SRATE(0x3, 0x0, 0x0)},
{18432000, 8000, SSM2602_COEFF_SRATE(0x3, 0x1, 0x0)},
{11289600, 8000, SSM2602_COEFF_SRATE(0xb, 0x0, 0x0)},
{16934400, 8000, SSM2602_COEFF_SRATE(0xb, 0x1, 0x0)},
{12000000, 8000, SSM2602_COEFF_SRATE(0x3, 0x0, 0x1)},
/* 96k */
{12288000, 96000, SSM2602_COEFF_SRATE(0x7, 0x0, 0x0)},
{18432000, 96000, SSM2602_COEFF_SRATE(0x7, 0x1, 0x0)},
{12000000, 96000, SSM2602_COEFF_SRATE(0x7, 0x0, 0x1)},
/* 11.025k */
{11289600, 11025, SSM2602_COEFF_SRATE(0xc, 0x0, 0x0)},
{16934400, 11025, SSM2602_COEFF_SRATE(0xc, 0x1, 0x0)},
{12000000, 11025, SSM2602_COEFF_SRATE(0xc, 0x1, 0x1)},
/* 22.05k */
{11289600, 22050, SSM2602_COEFF_SRATE(0xd, 0x0, 0x0)},
{16934400, 22050, SSM2602_COEFF_SRATE(0xd, 0x1, 0x0)},
{12000000, 22050, SSM2602_COEFF_SRATE(0xd, 0x1, 0x1)},
/* 44.1k */
{11289600, 44100, SSM2602_COEFF_SRATE(0x8, 0x0, 0x0)},
{16934400, 44100, SSM2602_COEFF_SRATE(0x8, 0x1, 0x0)},
{12000000, 44100, SSM2602_COEFF_SRATE(0x8, 0x1, 0x1)},
/* 88.2k */
{11289600, 88200, SSM2602_COEFF_SRATE(0xf, 0x0, 0x0)},
{16934400, 88200, SSM2602_COEFF_SRATE(0xf, 0x1, 0x0)},
{12000000, 88200, SSM2602_COEFF_SRATE(0xf, 0x1, 0x1)},
};
static inline int ssm2602_get_coeff(int mclk, int rate)
{
int i;
for (i = 0; i < ARRAY_SIZE(ssm2602_coeff_table); i++) {
if (ssm2602_coeff_table[i].rate == rate) {
if (ssm2602_coeff_table[i].mclk == mclk)
return ssm2602_coeff_table[i].srate;
if (ssm2602_coeff_table[i].mclk == mclk / 2)
return ssm2602_coeff_table[i].srate | SRATE_CORECLK_DIV2;
}
}
return -EINVAL;
}
static int ssm2602_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct ssm2602_priv *ssm2602 = snd_soc_component_get_drvdata(component);
int srate = ssm2602_get_coeff(ssm2602->sysclk, params_rate(params));
unsigned int iface;
if (srate < 0)
return srate;
regmap_write(ssm2602->regmap, SSM2602_SRATE, srate);
/* bit size */
switch (params_width(params)) {
case 16:
iface = 0x0;
break;
case 20:
iface = 0x4;
break;
case 24:
iface = 0x8;
break;
case 32:
iface = 0xc;
break;
default:
return -EINVAL;
}
regmap_update_bits(ssm2602->regmap, SSM2602_IFACE,
IFACE_AUDIO_DATA_LEN, iface);
return 0;
}
static int ssm2602_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct ssm2602_priv *ssm2602 = snd_soc_component_get_drvdata(component);
if (ssm2602->sysclk_constraints) {
snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
ssm2602->sysclk_constraints);
}
return 0;
}
static int ssm2602_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct ssm2602_priv *ssm2602 = snd_soc_component_get_drvdata(dai->component);
if (mute)
regmap_update_bits(ssm2602->regmap, SSM2602_APDIGI,
APDIGI_ENABLE_DAC_MUTE,
APDIGI_ENABLE_DAC_MUTE);
else
regmap_update_bits(ssm2602->regmap, SSM2602_APDIGI,
APDIGI_ENABLE_DAC_MUTE, 0);
return 0;
}
static int ssm2602_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct ssm2602_priv *ssm2602 = snd_soc_component_get_drvdata(component);
if (dir == SND_SOC_CLOCK_IN) {
if (clk_id != SSM2602_SYSCLK)
return -EINVAL;
switch (freq) {
case 12288000:
case 18432000:
case 24576000:
case 36864000:
ssm2602->sysclk_constraints = &ssm2602_constraints_12288000;
break;
case 11289600:
case 16934400:
case 22579200:
case 33868800:
ssm2602->sysclk_constraints = &ssm2602_constraints_11289600;
break;
case 12000000:
case 24000000:
ssm2602->sysclk_constraints = NULL;
break;
default:
return -EINVAL;
}
ssm2602->sysclk = freq;
} else {
unsigned int mask;
switch (clk_id) {
case SSM2602_CLK_CLKOUT:
mask = PWR_CLK_OUT_PDN;
break;
case SSM2602_CLK_XTO:
mask = PWR_OSC_PDN;
break;
default:
return -EINVAL;
}
if (freq == 0)
ssm2602->clk_out_pwr |= mask;
else
ssm2602->clk_out_pwr &= ~mask;
regmap_update_bits(ssm2602->regmap, SSM2602_PWR,
PWR_CLK_OUT_PDN | PWR_OSC_PDN, ssm2602->clk_out_pwr);
}
return 0;
}
static int ssm2602_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct ssm2602_priv *ssm2602 = snd_soc_component_get_drvdata(codec_dai->component);
unsigned int iface = 0;
/* set master/slave audio interface */
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
iface |= 0x0040;
break;
case SND_SOC_DAIFMT_CBC_CFC:
break;
default:
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface |= 0x0002;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
iface |= 0x0001;
break;
case SND_SOC_DAIFMT_DSP_A:
iface |= 0x0013;
break;
case SND_SOC_DAIFMT_DSP_B:
iface |= 0x0003;
break;
default:
return -EINVAL;
}
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
iface |= 0x0090;
break;
case SND_SOC_DAIFMT_IB_NF:
iface |= 0x0080;
break;
case SND_SOC_DAIFMT_NB_IF:
iface |= 0x0010;
break;
default:
return -EINVAL;
}
/* set iface */
regmap_write(ssm2602->regmap, SSM2602_IFACE, iface);
return 0;
}
static int ssm2602_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct ssm2602_priv *ssm2602 = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_ON:
/* vref/mid on, osc and clkout on if enabled */
regmap_update_bits(ssm2602->regmap, SSM2602_PWR,
PWR_POWER_OFF | PWR_CLK_OUT_PDN | PWR_OSC_PDN,
ssm2602->clk_out_pwr);
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
/* everything off except vref/vmid, */
regmap_update_bits(ssm2602->regmap, SSM2602_PWR,
PWR_POWER_OFF | PWR_CLK_OUT_PDN | PWR_OSC_PDN,
PWR_CLK_OUT_PDN | PWR_OSC_PDN);
break;
case SND_SOC_BIAS_OFF:
/* everything off */
regmap_update_bits(ssm2602->regmap, SSM2602_PWR,
PWR_POWER_OFF, PWR_POWER_OFF);
break;
}
return 0;
}
#define SSM2602_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |\
SNDRV_PCM_RATE_96000)
#define SSM2602_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops ssm2602_dai_ops = {
.startup = ssm2602_startup,
.hw_params = ssm2602_hw_params,
.mute_stream = ssm2602_mute,
.set_sysclk = ssm2602_set_dai_sysclk,
.set_fmt = ssm2602_set_dai_fmt,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver ssm2602_dai = {
.name = "ssm2602-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SSM2602_RATES,
.formats = SSM2602_FORMATS,},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SSM2602_RATES,
.formats = SSM2602_FORMATS,},
.ops = &ssm2602_dai_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
};
static int ssm2602_resume(struct snd_soc_component *component)
{
struct ssm2602_priv *ssm2602 = snd_soc_component_get_drvdata(component);
regcache_sync(ssm2602->regmap);
return 0;
}
static int ssm2602_component_probe(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct ssm2602_priv *ssm2602 = snd_soc_component_get_drvdata(component);
int ret;
regmap_update_bits(ssm2602->regmap, SSM2602_LOUT1V,
LOUT1V_LRHP_BOTH, LOUT1V_LRHP_BOTH);
regmap_update_bits(ssm2602->regmap, SSM2602_ROUT1V,
ROUT1V_RLHP_BOTH, ROUT1V_RLHP_BOTH);
ret = snd_soc_add_component_controls(component, ssm2602_snd_controls,
ARRAY_SIZE(ssm2602_snd_controls));
if (ret)
return ret;
ret = snd_soc_dapm_new_controls(dapm, ssm2602_dapm_widgets,
ARRAY_SIZE(ssm2602_dapm_widgets));
if (ret)
return ret;
return snd_soc_dapm_add_routes(dapm, ssm2602_routes,
ARRAY_SIZE(ssm2602_routes));
}
static int ssm2604_component_probe(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
int ret;
ret = snd_soc_dapm_new_controls(dapm, ssm2604_dapm_widgets,
ARRAY_SIZE(ssm2604_dapm_widgets));
if (ret)
return ret;
return snd_soc_dapm_add_routes(dapm, ssm2604_routes,
ARRAY_SIZE(ssm2604_routes));
}
static int ssm260x_component_probe(struct snd_soc_component *component)
{
struct ssm2602_priv *ssm2602 = snd_soc_component_get_drvdata(component);
int ret;
ret = regmap_write(ssm2602->regmap, SSM2602_RESET, 0);
if (ret < 0) {
dev_err(component->dev, "Failed to issue reset: %d\n", ret);
return ret;
}
regmap_register_patch(ssm2602->regmap, ssm2602_patch,
ARRAY_SIZE(ssm2602_patch));
/* set the update bits */
regmap_update_bits(ssm2602->regmap, SSM2602_LINVOL,
LINVOL_LRIN_BOTH, LINVOL_LRIN_BOTH);
regmap_update_bits(ssm2602->regmap, SSM2602_RINVOL,
RINVOL_RLIN_BOTH, RINVOL_RLIN_BOTH);
/*select Line in as default input*/
regmap_write(ssm2602->regmap, SSM2602_APANA, APANA_SELECT_DAC |
APANA_ENABLE_MIC_BOOST);
switch (ssm2602->type) {
case SSM2602:
ret = ssm2602_component_probe(component);
break;
case SSM2604:
ret = ssm2604_component_probe(component);
break;
}
return ret;
}
static const struct snd_soc_component_driver soc_component_dev_ssm2602 = {
.probe = ssm260x_component_probe,
.resume = ssm2602_resume,
.set_bias_level = ssm2602_set_bias_level,
.controls = ssm260x_snd_controls,
.num_controls = ARRAY_SIZE(ssm260x_snd_controls),
.dapm_widgets = ssm260x_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(ssm260x_dapm_widgets),
.dapm_routes = ssm260x_routes,
.num_dapm_routes = ARRAY_SIZE(ssm260x_routes),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static bool ssm2602_register_volatile(struct device *dev, unsigned int reg)
{
return reg == SSM2602_RESET;
}
const struct regmap_config ssm2602_regmap_config = {
.val_bits = 9,
.reg_bits = 7,
.max_register = SSM2602_RESET,
.volatile_reg = ssm2602_register_volatile,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = ssm2602_reg,
.num_reg_defaults = ARRAY_SIZE(ssm2602_reg),
};
EXPORT_SYMBOL_GPL(ssm2602_regmap_config);
int ssm2602_probe(struct device *dev, enum ssm2602_type type,
struct regmap *regmap)
{
struct ssm2602_priv *ssm2602;
if (IS_ERR(regmap))
return PTR_ERR(regmap);
ssm2602 = devm_kzalloc(dev, sizeof(*ssm2602), GFP_KERNEL);
if (ssm2602 == NULL)
return -ENOMEM;
dev_set_drvdata(dev, ssm2602);
ssm2602->type = type;
ssm2602->regmap = regmap;
return devm_snd_soc_register_component(dev, &soc_component_dev_ssm2602,
&ssm2602_dai, 1);
}
EXPORT_SYMBOL_GPL(ssm2602_probe);
MODULE_DESCRIPTION("ASoC SSM2602/SSM2603/SSM2604 driver");
MODULE_AUTHOR("Cliff Cai");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/ssm2602.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ak4641.c -- AK4641 ALSA Soc Audio driver
*
* Copyright (C) 2008 Harald Welte <[email protected]>
* Copyright (C) 2011 Dmitry Artamonow <[email protected]>
*
* Based on ak4535.c by Richard Purdie
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/ak4641.h>
/* AK4641 register space */
#define AK4641_PM1 0x00
#define AK4641_PM2 0x01
#define AK4641_SIG1 0x02
#define AK4641_SIG2 0x03
#define AK4641_MODE1 0x04
#define AK4641_MODE2 0x05
#define AK4641_DAC 0x06
#define AK4641_MIC 0x07
#define AK4641_TIMER 0x08
#define AK4641_ALC1 0x09
#define AK4641_ALC2 0x0a
#define AK4641_PGA 0x0b
#define AK4641_LATT 0x0c
#define AK4641_RATT 0x0d
#define AK4641_VOL 0x0e
#define AK4641_STATUS 0x0f
#define AK4641_EQLO 0x10
#define AK4641_EQMID 0x11
#define AK4641_EQHI 0x12
#define AK4641_BTIF 0x13
/* codec private data */
struct ak4641_priv {
struct regmap *regmap;
unsigned int sysclk;
int deemph;
int playback_fs;
};
/*
* ak4641 register cache
*/
static const struct reg_default ak4641_reg_defaults[] = {
{ 0, 0x00 }, { 1, 0x80 }, { 2, 0x00 }, { 3, 0x80 },
{ 4, 0x02 }, { 5, 0x00 }, { 6, 0x11 }, { 7, 0x05 },
{ 8, 0x00 }, { 9, 0x00 }, { 10, 0x36 }, { 11, 0x10 },
{ 12, 0x00 }, { 13, 0x00 }, { 14, 0x57 }, { 15, 0x00 },
{ 16, 0x88 }, { 17, 0x88 }, { 18, 0x08 }, { 19, 0x08 }
};
static const int deemph_settings[] = {44100, 0, 48000, 32000};
static int ak4641_set_deemph(struct snd_soc_component *component)
{
struct ak4641_priv *ak4641 = snd_soc_component_get_drvdata(component);
int i, best = 0;
for (i = 0 ; i < ARRAY_SIZE(deemph_settings); i++) {
/* if deemphasis is on, select the nearest available rate */
if (ak4641->deemph && deemph_settings[i] != 0 &&
abs(deemph_settings[i] - ak4641->playback_fs) <
abs(deemph_settings[best] - ak4641->playback_fs))
best = i;
if (!ak4641->deemph && deemph_settings[i] == 0)
best = i;
}
dev_dbg(component->dev, "Set deemphasis %d\n", best);
return snd_soc_component_update_bits(component, AK4641_DAC, 0x3, best);
}
static int ak4641_put_deemph(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct ak4641_priv *ak4641 = snd_soc_component_get_drvdata(component);
int deemph = ucontrol->value.integer.value[0];
if (deemph > 1)
return -EINVAL;
ak4641->deemph = deemph;
return ak4641_set_deemph(component);
}
static int ak4641_get_deemph(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct ak4641_priv *ak4641 = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = ak4641->deemph;
return 0;
};
static const char *ak4641_mono_out[] = {"(L + R)/2", "Hi-Z"};
static const char *ak4641_hp_out[] = {"Stereo", "Mono"};
static const char *ak4641_mic_select[] = {"Internal", "External"};
static const char *ak4641_mic_or_dac[] = {"Microphone", "Voice DAC"};
static const DECLARE_TLV_DB_SCALE(mono_gain_tlv, -1700, 2300, 0);
static const DECLARE_TLV_DB_SCALE(mic_boost_tlv, 0, 2000, 0);
static const DECLARE_TLV_DB_SCALE(eq_tlv, -1050, 150, 0);
static const DECLARE_TLV_DB_SCALE(master_tlv, -12750, 50, 0);
static const DECLARE_TLV_DB_SCALE(mic_stereo_sidetone_tlv, -2700, 300, 0);
static const DECLARE_TLV_DB_SCALE(mic_mono_sidetone_tlv, -400, 400, 0);
static const DECLARE_TLV_DB_SCALE(capture_tlv, -800, 50, 0);
static const DECLARE_TLV_DB_SCALE(alc_tlv, -800, 50, 0);
static const DECLARE_TLV_DB_SCALE(aux_in_tlv, -2100, 300, 0);
static SOC_ENUM_SINGLE_DECL(ak4641_mono_out_enum,
AK4641_SIG1, 6, ak4641_mono_out);
static SOC_ENUM_SINGLE_DECL(ak4641_hp_out_enum,
AK4641_MODE2, 2, ak4641_hp_out);
static SOC_ENUM_SINGLE_DECL(ak4641_mic_select_enum,
AK4641_MIC, 1, ak4641_mic_select);
static SOC_ENUM_SINGLE_DECL(ak4641_mic_or_dac_enum,
AK4641_BTIF, 4, ak4641_mic_or_dac);
static const struct snd_kcontrol_new ak4641_snd_controls[] = {
SOC_ENUM("Mono 1 Output", ak4641_mono_out_enum),
SOC_SINGLE_TLV("Mono 1 Gain Volume", AK4641_SIG1, 7, 1, 1,
mono_gain_tlv),
SOC_ENUM("Headphone Output", ak4641_hp_out_enum),
SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
ak4641_get_deemph, ak4641_put_deemph),
SOC_SINGLE_TLV("Mic Boost Volume", AK4641_MIC, 0, 1, 0, mic_boost_tlv),
SOC_SINGLE("ALC Operation Time", AK4641_TIMER, 0, 3, 0),
SOC_SINGLE("ALC Recovery Time", AK4641_TIMER, 2, 3, 0),
SOC_SINGLE("ALC ZC Time", AK4641_TIMER, 4, 3, 0),
SOC_SINGLE("ALC 1 Switch", AK4641_ALC1, 5, 1, 0),
SOC_SINGLE_TLV("ALC Volume", AK4641_ALC2, 0, 71, 0, alc_tlv),
SOC_SINGLE("Left Out Enable Switch", AK4641_SIG2, 1, 1, 0),
SOC_SINGLE("Right Out Enable Switch", AK4641_SIG2, 0, 1, 0),
SOC_SINGLE_TLV("Capture Volume", AK4641_PGA, 0, 71, 0, capture_tlv),
SOC_DOUBLE_R_TLV("Master Playback Volume", AK4641_LATT,
AK4641_RATT, 0, 255, 1, master_tlv),
SOC_SINGLE_TLV("AUX In Volume", AK4641_VOL, 0, 15, 0, aux_in_tlv),
SOC_SINGLE("Equalizer Switch", AK4641_DAC, 2, 1, 0),
SOC_SINGLE_TLV("EQ1 100 Hz Volume", AK4641_EQLO, 0, 15, 1, eq_tlv),
SOC_SINGLE_TLV("EQ2 250 Hz Volume", AK4641_EQLO, 4, 15, 1, eq_tlv),
SOC_SINGLE_TLV("EQ3 1 kHz Volume", AK4641_EQMID, 0, 15, 1, eq_tlv),
SOC_SINGLE_TLV("EQ4 3.5 kHz Volume", AK4641_EQMID, 4, 15, 1, eq_tlv),
SOC_SINGLE_TLV("EQ5 10 kHz Volume", AK4641_EQHI, 0, 15, 1, eq_tlv),
};
/* Mono 1 Mixer */
static const struct snd_kcontrol_new ak4641_mono1_mixer_controls[] = {
SOC_DAPM_SINGLE_TLV("Mic Mono Sidetone Volume", AK4641_VOL, 7, 1, 0,
mic_mono_sidetone_tlv),
SOC_DAPM_SINGLE("Mic Mono Sidetone Switch", AK4641_SIG1, 4, 1, 0),
SOC_DAPM_SINGLE("Mono Playback Switch", AK4641_SIG1, 5, 1, 0),
};
/* Stereo Mixer */
static const struct snd_kcontrol_new ak4641_stereo_mixer_controls[] = {
SOC_DAPM_SINGLE_TLV("Mic Sidetone Volume", AK4641_VOL, 4, 7, 0,
mic_stereo_sidetone_tlv),
SOC_DAPM_SINGLE("Mic Sidetone Switch", AK4641_SIG2, 4, 1, 0),
SOC_DAPM_SINGLE("Playback Switch", AK4641_SIG2, 7, 1, 0),
SOC_DAPM_SINGLE("Aux Bypass Switch", AK4641_SIG2, 5, 1, 0),
};
/* Input Mixer */
static const struct snd_kcontrol_new ak4641_input_mixer_controls[] = {
SOC_DAPM_SINGLE("Mic Capture Switch", AK4641_MIC, 2, 1, 0),
SOC_DAPM_SINGLE("Aux Capture Switch", AK4641_MIC, 5, 1, 0),
};
/* Mic mux */
static const struct snd_kcontrol_new ak4641_mic_mux_control =
SOC_DAPM_ENUM("Mic Select", ak4641_mic_select_enum);
/* Input mux */
static const struct snd_kcontrol_new ak4641_input_mux_control =
SOC_DAPM_ENUM("Input Select", ak4641_mic_or_dac_enum);
/* mono 2 switch */
static const struct snd_kcontrol_new ak4641_mono2_control =
SOC_DAPM_SINGLE("Switch", AK4641_SIG1, 0, 1, 0);
/* ak4641 dapm widgets */
static const struct snd_soc_dapm_widget ak4641_dapm_widgets[] = {
SND_SOC_DAPM_MIXER("Stereo Mixer", SND_SOC_NOPM, 0, 0,
&ak4641_stereo_mixer_controls[0],
ARRAY_SIZE(ak4641_stereo_mixer_controls)),
SND_SOC_DAPM_MIXER("Mono1 Mixer", SND_SOC_NOPM, 0, 0,
&ak4641_mono1_mixer_controls[0],
ARRAY_SIZE(ak4641_mono1_mixer_controls)),
SND_SOC_DAPM_MIXER("Input Mixer", SND_SOC_NOPM, 0, 0,
&ak4641_input_mixer_controls[0],
ARRAY_SIZE(ak4641_input_mixer_controls)),
SND_SOC_DAPM_MUX("Mic Mux", SND_SOC_NOPM, 0, 0,
&ak4641_mic_mux_control),
SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0,
&ak4641_input_mux_control),
SND_SOC_DAPM_SWITCH("Mono 2 Enable", SND_SOC_NOPM, 0, 0,
&ak4641_mono2_control),
SND_SOC_DAPM_OUTPUT("LOUT"),
SND_SOC_DAPM_OUTPUT("ROUT"),
SND_SOC_DAPM_OUTPUT("MOUT1"),
SND_SOC_DAPM_OUTPUT("MOUT2"),
SND_SOC_DAPM_OUTPUT("MICOUT"),
SND_SOC_DAPM_ADC("ADC", "HiFi Capture", AK4641_PM1, 0, 0),
SND_SOC_DAPM_PGA("Mic", AK4641_PM1, 1, 0, NULL, 0),
SND_SOC_DAPM_PGA("AUX In", AK4641_PM1, 2, 0, NULL, 0),
SND_SOC_DAPM_PGA("Mono Out", AK4641_PM1, 3, 0, NULL, 0),
SND_SOC_DAPM_PGA("Line Out", AK4641_PM1, 4, 0, NULL, 0),
SND_SOC_DAPM_DAC("DAC", "HiFi Playback", AK4641_PM2, 0, 0),
SND_SOC_DAPM_PGA("Mono Out 2", AK4641_PM2, 3, 0, NULL, 0),
SND_SOC_DAPM_ADC("Voice ADC", "Voice Capture", AK4641_BTIF, 0, 0),
SND_SOC_DAPM_DAC("Voice DAC", "Voice Playback", AK4641_BTIF, 1, 0),
SND_SOC_DAPM_MICBIAS("Mic Int Bias", AK4641_MIC, 3, 0),
SND_SOC_DAPM_MICBIAS("Mic Ext Bias", AK4641_MIC, 4, 0),
SND_SOC_DAPM_INPUT("MICIN"),
SND_SOC_DAPM_INPUT("MICEXT"),
SND_SOC_DAPM_INPUT("AUX"),
SND_SOC_DAPM_INPUT("AIN"),
};
static const struct snd_soc_dapm_route ak4641_audio_map[] = {
/* Stereo Mixer */
{"Stereo Mixer", "Playback Switch", "DAC"},
{"Stereo Mixer", "Mic Sidetone Switch", "Input Mux"},
{"Stereo Mixer", "Aux Bypass Switch", "AUX In"},
/* Mono 1 Mixer */
{"Mono1 Mixer", "Mic Mono Sidetone Switch", "Input Mux"},
{"Mono1 Mixer", "Mono Playback Switch", "DAC"},
/* Mic */
{"Mic", NULL, "AIN"},
{"Mic Mux", "Internal", "Mic Int Bias"},
{"Mic Mux", "External", "Mic Ext Bias"},
{"Mic Int Bias", NULL, "MICIN"},
{"Mic Ext Bias", NULL, "MICEXT"},
{"MICOUT", NULL, "Mic Mux"},
/* Input Mux */
{"Input Mux", "Microphone", "Mic"},
{"Input Mux", "Voice DAC", "Voice DAC"},
/* Line Out */
{"LOUT", NULL, "Line Out"},
{"ROUT", NULL, "Line Out"},
{"Line Out", NULL, "Stereo Mixer"},
/* Mono 1 Out */
{"MOUT1", NULL, "Mono Out"},
{"Mono Out", NULL, "Mono1 Mixer"},
/* Mono 2 Out */
{"MOUT2", NULL, "Mono 2 Enable"},
{"Mono 2 Enable", "Switch", "Mono Out 2"},
{"Mono Out 2", NULL, "Stereo Mixer"},
{"Voice ADC", NULL, "Mono 2 Enable"},
/* Aux In */
{"AUX In", NULL, "AUX"},
/* ADC */
{"ADC", NULL, "Input Mixer"},
{"Input Mixer", "Mic Capture Switch", "Mic"},
{"Input Mixer", "Aux Capture Switch", "AUX In"},
};
static int ak4641_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct ak4641_priv *ak4641 = snd_soc_component_get_drvdata(component);
ak4641->sysclk = freq;
return 0;
}
static int ak4641_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct ak4641_priv *ak4641 = snd_soc_component_get_drvdata(component);
int rate = params_rate(params), fs = 256;
u8 mode2;
if (rate)
fs = ak4641->sysclk / rate;
else
return -EINVAL;
/* set fs */
switch (fs) {
case 1024:
mode2 = (0x2 << 5);
break;
case 512:
mode2 = (0x1 << 5);
break;
case 256:
mode2 = (0x0 << 5);
break;
default:
dev_err(component->dev, "Error: unsupported fs=%d\n", fs);
return -EINVAL;
}
snd_soc_component_update_bits(component, AK4641_MODE2, (0x3 << 5), mode2);
/* Update de-emphasis filter for the new rate */
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
ak4641->playback_fs = rate;
ak4641_set_deemph(component);
}
return 0;
}
static int ak4641_pcm_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
u8 btif;
int ret;
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
btif = (0x3 << 5);
break;
case SND_SOC_DAIFMT_LEFT_J:
btif = (0x2 << 5);
break;
case SND_SOC_DAIFMT_DSP_A: /* MSB after FRM */
btif = (0x0 << 5);
break;
case SND_SOC_DAIFMT_DSP_B: /* MSB during FRM */
btif = (0x1 << 5);
break;
default:
return -EINVAL;
}
ret = snd_soc_component_update_bits(component, AK4641_BTIF, (0x3 << 5), btif);
if (ret < 0)
return ret;
return 0;
}
static int ak4641_i2s_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
u8 mode1 = 0;
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
mode1 = 0x02;
break;
case SND_SOC_DAIFMT_LEFT_J:
mode1 = 0x01;
break;
default:
return -EINVAL;
}
return snd_soc_component_write(component, AK4641_MODE1, mode1);
}
static int ak4641_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
return snd_soc_component_update_bits(component, AK4641_DAC, 0x20, mute ? 0x20 : 0);
}
static int ak4641_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct ak4641_priv *ak4641 = snd_soc_component_get_drvdata(component);
struct ak4641_platform_data *pdata = component->dev->platform_data;
int ret;
switch (level) {
case SND_SOC_BIAS_ON:
/* unmute */
snd_soc_component_update_bits(component, AK4641_DAC, 0x20, 0);
break;
case SND_SOC_BIAS_PREPARE:
/* mute */
snd_soc_component_update_bits(component, AK4641_DAC, 0x20, 0x20);
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
if (pdata && gpio_is_valid(pdata->gpio_power))
gpio_set_value(pdata->gpio_power, 1);
mdelay(1);
if (pdata && gpio_is_valid(pdata->gpio_npdn))
gpio_set_value(pdata->gpio_npdn, 1);
mdelay(1);
ret = regcache_sync(ak4641->regmap);
if (ret) {
dev_err(component->dev,
"Failed to sync cache: %d\n", ret);
return ret;
}
}
snd_soc_component_update_bits(component, AK4641_PM1, 0x80, 0x80);
snd_soc_component_update_bits(component, AK4641_PM2, 0x80, 0);
break;
case SND_SOC_BIAS_OFF:
snd_soc_component_update_bits(component, AK4641_PM1, 0x80, 0);
if (pdata && gpio_is_valid(pdata->gpio_npdn))
gpio_set_value(pdata->gpio_npdn, 0);
if (pdata && gpio_is_valid(pdata->gpio_power))
gpio_set_value(pdata->gpio_power, 0);
regcache_mark_dirty(ak4641->regmap);
break;
}
return 0;
}
#define AK4641_RATES (SNDRV_PCM_RATE_8000_48000)
#define AK4641_RATES_BT (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
SNDRV_PCM_RATE_16000)
#define AK4641_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
static const struct snd_soc_dai_ops ak4641_i2s_dai_ops = {
.hw_params = ak4641_i2s_hw_params,
.set_fmt = ak4641_i2s_set_dai_fmt,
.mute_stream = ak4641_mute,
.set_sysclk = ak4641_set_dai_sysclk,
.no_capture_mute = 1,
};
static const struct snd_soc_dai_ops ak4641_pcm_dai_ops = {
.hw_params = NULL, /* rates are controlled by BT chip */
.set_fmt = ak4641_pcm_set_dai_fmt,
.mute_stream = ak4641_mute,
.set_sysclk = ak4641_set_dai_sysclk,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver ak4641_dai[] = {
{
.name = "ak4641-hifi",
.id = 1,
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 1,
.channels_max = 2,
.rates = AK4641_RATES,
.formats = AK4641_FORMATS,
},
.capture = {
.stream_name = "HiFi Capture",
.channels_min = 1,
.channels_max = 2,
.rates = AK4641_RATES,
.formats = AK4641_FORMATS,
},
.ops = &ak4641_i2s_dai_ops,
.symmetric_rate = 1,
},
{
.name = "ak4641-voice",
.id = 1,
.playback = {
.stream_name = "Voice Playback",
.channels_min = 1,
.channels_max = 1,
.rates = AK4641_RATES_BT,
.formats = AK4641_FORMATS,
},
.capture = {
.stream_name = "Voice Capture",
.channels_min = 1,
.channels_max = 1,
.rates = AK4641_RATES_BT,
.formats = AK4641_FORMATS,
},
.ops = &ak4641_pcm_dai_ops,
.symmetric_rate = 1,
},
};
static const struct snd_soc_component_driver soc_component_dev_ak4641 = {
.controls = ak4641_snd_controls,
.num_controls = ARRAY_SIZE(ak4641_snd_controls),
.dapm_widgets = ak4641_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(ak4641_dapm_widgets),
.dapm_routes = ak4641_audio_map,
.num_dapm_routes = ARRAY_SIZE(ak4641_audio_map),
.set_bias_level = ak4641_set_bias_level,
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config ak4641_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = AK4641_BTIF,
.reg_defaults = ak4641_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(ak4641_reg_defaults),
.cache_type = REGCACHE_RBTREE,
};
static int ak4641_i2c_probe(struct i2c_client *i2c)
{
struct ak4641_platform_data *pdata = i2c->dev.platform_data;
struct ak4641_priv *ak4641;
int ret;
ak4641 = devm_kzalloc(&i2c->dev, sizeof(struct ak4641_priv),
GFP_KERNEL);
if (!ak4641)
return -ENOMEM;
ak4641->regmap = devm_regmap_init_i2c(i2c, &ak4641_regmap);
if (IS_ERR(ak4641->regmap))
return PTR_ERR(ak4641->regmap);
if (pdata) {
if (gpio_is_valid(pdata->gpio_power)) {
ret = gpio_request_one(pdata->gpio_power,
GPIOF_OUT_INIT_LOW, "ak4641 power");
if (ret)
goto err_out;
}
if (gpio_is_valid(pdata->gpio_npdn)) {
ret = gpio_request_one(pdata->gpio_npdn,
GPIOF_OUT_INIT_LOW, "ak4641 npdn");
if (ret)
goto err_gpio;
udelay(1); /* > 150 ns */
gpio_set_value(pdata->gpio_npdn, 1);
}
}
i2c_set_clientdata(i2c, ak4641);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_ak4641,
ak4641_dai, ARRAY_SIZE(ak4641_dai));
if (ret != 0)
goto err_gpio2;
return 0;
err_gpio2:
if (pdata) {
if (gpio_is_valid(pdata->gpio_power))
gpio_set_value(pdata->gpio_power, 0);
if (gpio_is_valid(pdata->gpio_npdn))
gpio_free(pdata->gpio_npdn);
}
err_gpio:
if (pdata && gpio_is_valid(pdata->gpio_power))
gpio_free(pdata->gpio_power);
err_out:
return ret;
}
static void ak4641_i2c_remove(struct i2c_client *i2c)
{
struct ak4641_platform_data *pdata = i2c->dev.platform_data;
if (pdata) {
if (gpio_is_valid(pdata->gpio_power)) {
gpio_set_value(pdata->gpio_power, 0);
gpio_free(pdata->gpio_power);
}
if (gpio_is_valid(pdata->gpio_npdn))
gpio_free(pdata->gpio_npdn);
}
}
static const struct i2c_device_id ak4641_i2c_id[] = {
{ "ak4641", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, ak4641_i2c_id);
static struct i2c_driver ak4641_i2c_driver = {
.driver = {
.name = "ak4641",
},
.probe = ak4641_i2c_probe,
.remove = ak4641_i2c_remove,
.id_table = ak4641_i2c_id,
};
module_i2c_driver(ak4641_i2c_driver);
MODULE_DESCRIPTION("SoC AK4641 driver");
MODULE_AUTHOR("Harald Welte <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/ak4641.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* SSM2602/SSM2603/SSM2604 I2C audio driver
*
* Copyright 2014 Analog Devices Inc.
*/
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include "ssm2602.h"
static const struct i2c_device_id ssm2602_i2c_id[];
/*
* ssm2602 2 wire address is determined by GPIO5
* state during powerup.
* low = 0x1a
* high = 0x1b
*/
static int ssm2602_i2c_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_match_id(ssm2602_i2c_id, client);
return ssm2602_probe(&client->dev, id->driver_data,
devm_regmap_init_i2c(client, &ssm2602_regmap_config));
}
static const struct i2c_device_id ssm2602_i2c_id[] = {
{ "ssm2602", SSM2602 },
{ "ssm2603", SSM2602 },
{ "ssm2604", SSM2604 },
{ }
};
MODULE_DEVICE_TABLE(i2c, ssm2602_i2c_id);
static const struct of_device_id ssm2602_of_match[] = {
{ .compatible = "adi,ssm2602", },
{ .compatible = "adi,ssm2603", },
{ .compatible = "adi,ssm2604", },
{ }
};
MODULE_DEVICE_TABLE(of, ssm2602_of_match);
static struct i2c_driver ssm2602_i2c_driver = {
.driver = {
.name = "ssm2602",
.of_match_table = ssm2602_of_match,
},
.probe = ssm2602_i2c_probe,
.id_table = ssm2602_i2c_id,
};
module_i2c_driver(ssm2602_i2c_driver);
MODULE_DESCRIPTION("ASoC SSM2602/SSM2603/SSM2604 I2C driver");
MODULE_AUTHOR("Cliff Cai");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/ssm2602-i2c.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* rt5665.c -- RT5665/RT5658 ALSA SoC audio codec driver
*
* Copyright 2016 Realtek Semiconductor Corp.
* Author: Bard Liao <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/acpi.h>
#include <linux/gpio/consumer.h>
#include <linux/regulator/consumer.h>
#include <linux/mutex.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/jack.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/rt5665.h>
#include "rl6231.h"
#include "rt5665.h"
#define RT5665_NUM_SUPPLIES 3
static const char *rt5665_supply_names[RT5665_NUM_SUPPLIES] = {
"AVDD",
"MICVDD",
"VBAT",
};
struct rt5665_priv {
struct snd_soc_component *component;
struct rt5665_platform_data pdata;
struct regmap *regmap;
struct gpio_desc *gpiod_ldo1_en;
struct gpio_desc *gpiod_reset;
struct snd_soc_jack *hs_jack;
struct regulator_bulk_data supplies[RT5665_NUM_SUPPLIES];
struct delayed_work jack_detect_work;
struct delayed_work calibrate_work;
struct delayed_work jd_check_work;
struct mutex calibrate_mutex;
int sysclk;
int sysclk_src;
int lrck[RT5665_AIFS];
int bclk[RT5665_AIFS];
int master[RT5665_AIFS];
int id;
int pll_src;
int pll_in;
int pll_out;
int jack_type;
int irq_work_delay_time;
unsigned int sar_adc_value;
bool calibration_done;
};
static const struct reg_default rt5665_reg[] = {
{0x0000, 0x0000},
{0x0001, 0xc8c8},
{0x0002, 0x8080},
{0x0003, 0x8000},
{0x0004, 0xc80a},
{0x0005, 0x0000},
{0x0006, 0x0000},
{0x0007, 0x0000},
{0x000a, 0x0000},
{0x000b, 0x0000},
{0x000c, 0x0000},
{0x000d, 0x0000},
{0x000f, 0x0808},
{0x0010, 0x4040},
{0x0011, 0x0000},
{0x0012, 0x1404},
{0x0013, 0x1000},
{0x0014, 0xa00a},
{0x0015, 0x0404},
{0x0016, 0x0404},
{0x0017, 0x0011},
{0x0018, 0xafaf},
{0x0019, 0xafaf},
{0x001a, 0xafaf},
{0x001b, 0x0011},
{0x001c, 0x2f2f},
{0x001d, 0x2f2f},
{0x001e, 0x2f2f},
{0x001f, 0x0000},
{0x0020, 0x0000},
{0x0021, 0x0000},
{0x0022, 0x5757},
{0x0023, 0x0039},
{0x0026, 0xc0c0},
{0x0027, 0xc0c0},
{0x0028, 0xc0c0},
{0x0029, 0x8080},
{0x002a, 0xaaaa},
{0x002b, 0xaaaa},
{0x002c, 0xaba8},
{0x002d, 0x0000},
{0x002e, 0x0000},
{0x002f, 0x0000},
{0x0030, 0x0000},
{0x0031, 0x5000},
{0x0032, 0x0000},
{0x0033, 0x0000},
{0x0034, 0x0000},
{0x0035, 0x0000},
{0x003a, 0x0000},
{0x003b, 0x0000},
{0x003c, 0x00ff},
{0x003d, 0x0000},
{0x003e, 0x00ff},
{0x003f, 0x0000},
{0x0040, 0x0000},
{0x0041, 0x00ff},
{0x0042, 0x0000},
{0x0043, 0x00ff},
{0x0044, 0x0c0c},
{0x0049, 0xc00b},
{0x004a, 0x0000},
{0x004b, 0x031f},
{0x004d, 0x0000},
{0x004e, 0x001f},
{0x004f, 0x0000},
{0x0050, 0x001f},
{0x0052, 0xf000},
{0x0061, 0x0000},
{0x0062, 0x0000},
{0x0063, 0x003e},
{0x0064, 0x0000},
{0x0065, 0x0000},
{0x0066, 0x003f},
{0x0067, 0x0000},
{0x006b, 0x0000},
{0x006d, 0xff00},
{0x006e, 0x2808},
{0x006f, 0x000a},
{0x0070, 0x8000},
{0x0071, 0x8000},
{0x0072, 0x8000},
{0x0073, 0x7000},
{0x0074, 0x7770},
{0x0075, 0x0002},
{0x0076, 0x0001},
{0x0078, 0x00f0},
{0x0079, 0x0000},
{0x007a, 0x0000},
{0x007b, 0x0000},
{0x007c, 0x0000},
{0x007d, 0x0123},
{0x007e, 0x4500},
{0x007f, 0x8003},
{0x0080, 0x0000},
{0x0081, 0x0000},
{0x0082, 0x0000},
{0x0083, 0x0000},
{0x0084, 0x0000},
{0x0085, 0x0000},
{0x0086, 0x0008},
{0x0087, 0x0000},
{0x0088, 0x0000},
{0x0089, 0x0000},
{0x008a, 0x0000},
{0x008b, 0x0000},
{0x008c, 0x0003},
{0x008e, 0x0060},
{0x008f, 0x1000},
{0x0091, 0x0c26},
{0x0092, 0x0073},
{0x0093, 0x0000},
{0x0094, 0x0080},
{0x0098, 0x0000},
{0x0099, 0x0000},
{0x009a, 0x0007},
{0x009f, 0x0000},
{0x00a0, 0x0000},
{0x00a1, 0x0002},
{0x00a2, 0x0001},
{0x00a3, 0x0002},
{0x00a4, 0x0001},
{0x00ae, 0x2040},
{0x00af, 0x0000},
{0x00b6, 0x0000},
{0x00b7, 0x0000},
{0x00b8, 0x0000},
{0x00b9, 0x0000},
{0x00ba, 0x0002},
{0x00bb, 0x0000},
{0x00be, 0x0000},
{0x00c0, 0x0000},
{0x00c1, 0x0aaa},
{0x00c2, 0xaa80},
{0x00c3, 0x0003},
{0x00c4, 0x0000},
{0x00d0, 0x0000},
{0x00d1, 0x2244},
{0x00d3, 0x3300},
{0x00d4, 0x2200},
{0x00d9, 0x0809},
{0x00da, 0x0000},
{0x00db, 0x0008},
{0x00dc, 0x00c0},
{0x00dd, 0x6724},
{0x00de, 0x3131},
{0x00df, 0x0008},
{0x00e0, 0x4000},
{0x00e1, 0x3131},
{0x00e2, 0x600c},
{0x00ea, 0xb320},
{0x00eb, 0x0000},
{0x00ec, 0xb300},
{0x00ed, 0x0000},
{0x00ee, 0xb320},
{0x00ef, 0x0000},
{0x00f0, 0x0201},
{0x00f1, 0x0ddd},
{0x00f2, 0x0ddd},
{0x00f6, 0x0000},
{0x00f7, 0x0000},
{0x00f8, 0x0000},
{0x00fa, 0x0000},
{0x00fb, 0x0000},
{0x00fc, 0x0000},
{0x00fd, 0x0000},
{0x00fe, 0x10ec},
{0x00ff, 0x6451},
{0x0100, 0xaaaa},
{0x0101, 0x000a},
{0x010a, 0xaaaa},
{0x010b, 0xa0a0},
{0x010c, 0xaeae},
{0x010d, 0xaaaa},
{0x010e, 0xaaaa},
{0x010f, 0xaaaa},
{0x0110, 0xe002},
{0x0111, 0xa402},
{0x0112, 0xaaaa},
{0x0113, 0x2000},
{0x0117, 0x0f00},
{0x0125, 0x0410},
{0x0132, 0x0000},
{0x0133, 0x0000},
{0x0137, 0x5540},
{0x0138, 0x3700},
{0x0139, 0x79a1},
{0x013a, 0x2020},
{0x013b, 0x2020},
{0x013c, 0x2005},
{0x013f, 0x0000},
{0x0145, 0x0002},
{0x0146, 0x0000},
{0x0147, 0x0000},
{0x0148, 0x0000},
{0x0150, 0x0000},
{0x0160, 0x4eff},
{0x0161, 0x0080},
{0x0162, 0x0200},
{0x0163, 0x0800},
{0x0164, 0x0000},
{0x0165, 0x0000},
{0x0166, 0x0000},
{0x0167, 0x000f},
{0x0170, 0x4e87},
{0x0171, 0x0080},
{0x0172, 0x0200},
{0x0173, 0x0800},
{0x0174, 0x00ff},
{0x0175, 0x0000},
{0x0190, 0x413d},
{0x0191, 0x4139},
{0x0192, 0x4135},
{0x0193, 0x413d},
{0x0194, 0x0000},
{0x0195, 0x0000},
{0x0196, 0x0000},
{0x0197, 0x0000},
{0x0198, 0x0000},
{0x0199, 0x0000},
{0x01a0, 0x1e64},
{0x01a1, 0x06a3},
{0x01a2, 0x0000},
{0x01a3, 0x0000},
{0x01a4, 0x0000},
{0x01a5, 0x0000},
{0x01a6, 0x0000},
{0x01a7, 0x8000},
{0x01a8, 0x0000},
{0x01a9, 0x0000},
{0x01aa, 0x0000},
{0x01ab, 0x0000},
{0x01b5, 0x0000},
{0x01b6, 0x01c3},
{0x01b7, 0x02a0},
{0x01b8, 0x03e9},
{0x01b9, 0x1389},
{0x01ba, 0xc351},
{0x01bb, 0x0009},
{0x01bc, 0x0018},
{0x01bd, 0x002a},
{0x01be, 0x004c},
{0x01bf, 0x0097},
{0x01c0, 0x433d},
{0x01c1, 0x0000},
{0x01c2, 0x0000},
{0x01c3, 0x0000},
{0x01c4, 0x0000},
{0x01c5, 0x0000},
{0x01c6, 0x0000},
{0x01c7, 0x0000},
{0x01c8, 0x40af},
{0x01c9, 0x0702},
{0x01ca, 0x0000},
{0x01cb, 0x0000},
{0x01cc, 0x5757},
{0x01cd, 0x5757},
{0x01ce, 0x5757},
{0x01cf, 0x5757},
{0x01d0, 0x5757},
{0x01d1, 0x5757},
{0x01d2, 0x5757},
{0x01d3, 0x5757},
{0x01d4, 0x5757},
{0x01d5, 0x5757},
{0x01d6, 0x003c},
{0x01da, 0x0000},
{0x01db, 0x0000},
{0x01dc, 0x0000},
{0x01de, 0x7c00},
{0x01df, 0x0320},
{0x01e0, 0x06a1},
{0x01e1, 0x0000},
{0x01e2, 0x0000},
{0x01e3, 0x0000},
{0x01e4, 0x0000},
{0x01e6, 0x0001},
{0x01e7, 0x0000},
{0x01e8, 0x0000},
{0x01ea, 0xbf3f},
{0x01eb, 0x0000},
{0x01ec, 0x0000},
{0x01ed, 0x0000},
{0x01ee, 0x0000},
{0x01ef, 0x0000},
{0x01f0, 0x0000},
{0x01f1, 0x0000},
{0x01f2, 0x0000},
{0x01f3, 0x0000},
{0x01f4, 0x0000},
{0x0200, 0x0000},
{0x0201, 0x0000},
{0x0202, 0x0000},
{0x0203, 0x0000},
{0x0204, 0x0000},
{0x0205, 0x0000},
{0x0206, 0x0000},
{0x0207, 0x0000},
{0x0208, 0x0000},
{0x0210, 0x60b1},
{0x0211, 0xa005},
{0x0212, 0x024c},
{0x0213, 0xf7ff},
{0x0214, 0x024c},
{0x0215, 0x0102},
{0x0216, 0x00a3},
{0x0217, 0x0048},
{0x0218, 0xa2c0},
{0x0219, 0x0400},
{0x021a, 0x00c8},
{0x021b, 0x00c0},
{0x02ff, 0x0110},
{0x0300, 0x001f},
{0x0301, 0x032c},
{0x0302, 0x5f21},
{0x0303, 0x4000},
{0x0304, 0x4000},
{0x0305, 0x06d5},
{0x0306, 0x8000},
{0x0307, 0x0700},
{0x0310, 0x4560},
{0x0311, 0xa4a8},
{0x0312, 0x7418},
{0x0313, 0x0000},
{0x0314, 0x0006},
{0x0315, 0xffff},
{0x0316, 0xc400},
{0x0317, 0x0000},
{0x0330, 0x00a6},
{0x0331, 0x04c3},
{0x0332, 0x27c8},
{0x0333, 0xbf50},
{0x0334, 0x0045},
{0x0335, 0x0007},
{0x0336, 0x7418},
{0x0337, 0x0501},
{0x0338, 0x0000},
{0x0339, 0x0010},
{0x033a, 0x1010},
{0x03c0, 0x7e00},
{0x03c1, 0x8000},
{0x03c2, 0x8000},
{0x03c3, 0x8000},
{0x03c4, 0x8000},
{0x03c5, 0x8000},
{0x03c6, 0x8000},
{0x03c7, 0x8000},
{0x03c8, 0x8000},
{0x03c9, 0x8000},
{0x03ca, 0x8000},
{0x03cb, 0x8000},
{0x03cc, 0x8000},
{0x03d0, 0x0000},
{0x03d1, 0x0000},
{0x03d2, 0x0000},
{0x03d3, 0x0000},
{0x03d4, 0x2000},
{0x03d5, 0x2000},
{0x03d6, 0x0000},
{0x03d7, 0x0000},
{0x03d8, 0x2000},
{0x03d9, 0x2000},
{0x03da, 0x2000},
{0x03db, 0x2000},
{0x03dc, 0x0000},
{0x03dd, 0x0000},
{0x03de, 0x0000},
{0x03df, 0x2000},
{0x03e0, 0x0000},
{0x03e1, 0x0000},
{0x03e2, 0x0000},
{0x03e3, 0x0000},
{0x03e4, 0x0000},
{0x03e5, 0x0000},
{0x03e6, 0x0000},
{0x03e7, 0x0000},
{0x03e8, 0x0000},
{0x03e9, 0x0000},
{0x03ea, 0x0000},
{0x03eb, 0x0000},
{0x03ec, 0x0000},
{0x03ed, 0x0000},
{0x03ee, 0x0000},
{0x03ef, 0x0000},
{0x03f0, 0x0800},
{0x03f1, 0x0800},
{0x03f2, 0x0800},
{0x03f3, 0x0800},
};
static bool rt5665_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case RT5665_RESET:
case RT5665_EJD_CTRL_2:
case RT5665_GPIO_STA:
case RT5665_INT_ST_1:
case RT5665_IL_CMD_1:
case RT5665_4BTN_IL_CMD_1:
case RT5665_PSV_IL_CMD_1:
case RT5665_AJD1_CTRL:
case RT5665_JD_CTRL_3:
case RT5665_STO_NG2_CTRL_1:
case RT5665_SAR_IL_CMD_4:
case RT5665_DEVICE_ID:
case RT5665_STO1_DAC_SIL_DET ... RT5665_STO2_DAC_SIL_DET:
case RT5665_MONO_AMP_CALIB_STA1 ... RT5665_MONO_AMP_CALIB_STA6:
case RT5665_HP_IMP_SENS_CTRL_12 ... RT5665_HP_IMP_SENS_CTRL_15:
case RT5665_HP_CALIB_STA_1 ... RT5665_HP_CALIB_STA_11:
return true;
default:
return false;
}
}
static bool rt5665_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case RT5665_RESET:
case RT5665_VENDOR_ID:
case RT5665_VENDOR_ID_1:
case RT5665_DEVICE_ID:
case RT5665_LOUT:
case RT5665_HP_CTRL_1:
case RT5665_HP_CTRL_2:
case RT5665_MONO_OUT:
case RT5665_HPL_GAIN:
case RT5665_HPR_GAIN:
case RT5665_MONO_GAIN:
case RT5665_CAL_BST_CTRL:
case RT5665_CBJ_BST_CTRL:
case RT5665_IN1_IN2:
case RT5665_IN3_IN4:
case RT5665_INL1_INR1_VOL:
case RT5665_EJD_CTRL_1:
case RT5665_EJD_CTRL_2:
case RT5665_EJD_CTRL_3:
case RT5665_EJD_CTRL_4:
case RT5665_EJD_CTRL_5:
case RT5665_EJD_CTRL_6:
case RT5665_EJD_CTRL_7:
case RT5665_DAC2_CTRL:
case RT5665_DAC2_DIG_VOL:
case RT5665_DAC1_DIG_VOL:
case RT5665_DAC3_DIG_VOL:
case RT5665_DAC3_CTRL:
case RT5665_STO1_ADC_DIG_VOL:
case RT5665_MONO_ADC_DIG_VOL:
case RT5665_STO2_ADC_DIG_VOL:
case RT5665_STO1_ADC_BOOST:
case RT5665_MONO_ADC_BOOST:
case RT5665_STO2_ADC_BOOST:
case RT5665_HP_IMP_GAIN_1:
case RT5665_HP_IMP_GAIN_2:
case RT5665_STO1_ADC_MIXER:
case RT5665_MONO_ADC_MIXER:
case RT5665_STO2_ADC_MIXER:
case RT5665_AD_DA_MIXER:
case RT5665_STO1_DAC_MIXER:
case RT5665_MONO_DAC_MIXER:
case RT5665_STO2_DAC_MIXER:
case RT5665_A_DAC1_MUX:
case RT5665_A_DAC2_MUX:
case RT5665_DIG_INF2_DATA:
case RT5665_DIG_INF3_DATA:
case RT5665_PDM_OUT_CTRL:
case RT5665_PDM_DATA_CTRL_1:
case RT5665_PDM_DATA_CTRL_2:
case RT5665_PDM_DATA_CTRL_3:
case RT5665_PDM_DATA_CTRL_4:
case RT5665_REC1_GAIN:
case RT5665_REC1_L1_MIXER:
case RT5665_REC1_L2_MIXER:
case RT5665_REC1_R1_MIXER:
case RT5665_REC1_R2_MIXER:
case RT5665_REC2_GAIN:
case RT5665_REC2_L1_MIXER:
case RT5665_REC2_L2_MIXER:
case RT5665_REC2_R1_MIXER:
case RT5665_REC2_R2_MIXER:
case RT5665_CAL_REC:
case RT5665_ALC_BACK_GAIN:
case RT5665_MONOMIX_GAIN:
case RT5665_MONOMIX_IN_GAIN:
case RT5665_OUT_L_GAIN:
case RT5665_OUT_L_MIXER:
case RT5665_OUT_R_GAIN:
case RT5665_OUT_R_MIXER:
case RT5665_LOUT_MIXER:
case RT5665_PWR_DIG_1:
case RT5665_PWR_DIG_2:
case RT5665_PWR_ANLG_1:
case RT5665_PWR_ANLG_2:
case RT5665_PWR_ANLG_3:
case RT5665_PWR_MIXER:
case RT5665_PWR_VOL:
case RT5665_CLK_DET:
case RT5665_HPF_CTRL1:
case RT5665_DMIC_CTRL_1:
case RT5665_DMIC_CTRL_2:
case RT5665_I2S1_SDP:
case RT5665_I2S2_SDP:
case RT5665_I2S3_SDP:
case RT5665_ADDA_CLK_1:
case RT5665_ADDA_CLK_2:
case RT5665_I2S1_F_DIV_CTRL_1:
case RT5665_I2S1_F_DIV_CTRL_2:
case RT5665_TDM_CTRL_1:
case RT5665_TDM_CTRL_2:
case RT5665_TDM_CTRL_3:
case RT5665_TDM_CTRL_4:
case RT5665_TDM_CTRL_5:
case RT5665_TDM_CTRL_6:
case RT5665_TDM_CTRL_7:
case RT5665_TDM_CTRL_8:
case RT5665_GLB_CLK:
case RT5665_PLL_CTRL_1:
case RT5665_PLL_CTRL_2:
case RT5665_ASRC_1:
case RT5665_ASRC_2:
case RT5665_ASRC_3:
case RT5665_ASRC_4:
case RT5665_ASRC_5:
case RT5665_ASRC_6:
case RT5665_ASRC_7:
case RT5665_ASRC_8:
case RT5665_ASRC_9:
case RT5665_ASRC_10:
case RT5665_DEPOP_1:
case RT5665_DEPOP_2:
case RT5665_HP_CHARGE_PUMP_1:
case RT5665_HP_CHARGE_PUMP_2:
case RT5665_MICBIAS_1:
case RT5665_MICBIAS_2:
case RT5665_ASRC_12:
case RT5665_ASRC_13:
case RT5665_ASRC_14:
case RT5665_RC_CLK_CTRL:
case RT5665_I2S_M_CLK_CTRL_1:
case RT5665_I2S2_F_DIV_CTRL_1:
case RT5665_I2S2_F_DIV_CTRL_2:
case RT5665_I2S3_F_DIV_CTRL_1:
case RT5665_I2S3_F_DIV_CTRL_2:
case RT5665_EQ_CTRL_1:
case RT5665_EQ_CTRL_2:
case RT5665_IRQ_CTRL_1:
case RT5665_IRQ_CTRL_2:
case RT5665_IRQ_CTRL_3:
case RT5665_IRQ_CTRL_4:
case RT5665_IRQ_CTRL_5:
case RT5665_IRQ_CTRL_6:
case RT5665_INT_ST_1:
case RT5665_GPIO_CTRL_1:
case RT5665_GPIO_CTRL_2:
case RT5665_GPIO_CTRL_3:
case RT5665_GPIO_CTRL_4:
case RT5665_GPIO_STA:
case RT5665_HP_AMP_DET_CTRL_1:
case RT5665_HP_AMP_DET_CTRL_2:
case RT5665_MID_HP_AMP_DET:
case RT5665_LOW_HP_AMP_DET:
case RT5665_SV_ZCD_1:
case RT5665_SV_ZCD_2:
case RT5665_IL_CMD_1:
case RT5665_IL_CMD_2:
case RT5665_IL_CMD_3:
case RT5665_IL_CMD_4:
case RT5665_4BTN_IL_CMD_1:
case RT5665_4BTN_IL_CMD_2:
case RT5665_4BTN_IL_CMD_3:
case RT5665_PSV_IL_CMD_1:
case RT5665_ADC_STO1_HP_CTRL_1:
case RT5665_ADC_STO1_HP_CTRL_2:
case RT5665_ADC_MONO_HP_CTRL_1:
case RT5665_ADC_MONO_HP_CTRL_2:
case RT5665_ADC_STO2_HP_CTRL_1:
case RT5665_ADC_STO2_HP_CTRL_2:
case RT5665_AJD1_CTRL:
case RT5665_JD1_THD:
case RT5665_JD2_THD:
case RT5665_JD_CTRL_1:
case RT5665_JD_CTRL_2:
case RT5665_JD_CTRL_3:
case RT5665_DIG_MISC:
case RT5665_DUMMY_2:
case RT5665_DUMMY_3:
case RT5665_DAC_ADC_DIG_VOL1:
case RT5665_DAC_ADC_DIG_VOL2:
case RT5665_BIAS_CUR_CTRL_1:
case RT5665_BIAS_CUR_CTRL_2:
case RT5665_BIAS_CUR_CTRL_3:
case RT5665_BIAS_CUR_CTRL_4:
case RT5665_BIAS_CUR_CTRL_5:
case RT5665_BIAS_CUR_CTRL_6:
case RT5665_BIAS_CUR_CTRL_7:
case RT5665_BIAS_CUR_CTRL_8:
case RT5665_BIAS_CUR_CTRL_9:
case RT5665_BIAS_CUR_CTRL_10:
case RT5665_VREF_REC_OP_FB_CAP_CTRL:
case RT5665_CHARGE_PUMP_1:
case RT5665_DIG_IN_CTRL_1:
case RT5665_DIG_IN_CTRL_2:
case RT5665_PAD_DRIVING_CTRL:
case RT5665_SOFT_RAMP_DEPOP:
case RT5665_PLL:
case RT5665_CHOP_DAC:
case RT5665_CHOP_ADC:
case RT5665_CALIB_ADC_CTRL:
case RT5665_VOL_TEST:
case RT5665_TEST_MODE_CTRL_1:
case RT5665_TEST_MODE_CTRL_2:
case RT5665_TEST_MODE_CTRL_3:
case RT5665_TEST_MODE_CTRL_4:
case RT5665_BASSBACK_CTRL:
case RT5665_STO_NG2_CTRL_1:
case RT5665_STO_NG2_CTRL_2:
case RT5665_STO_NG2_CTRL_3:
case RT5665_STO_NG2_CTRL_4:
case RT5665_STO_NG2_CTRL_5:
case RT5665_STO_NG2_CTRL_6:
case RT5665_STO_NG2_CTRL_7:
case RT5665_STO_NG2_CTRL_8:
case RT5665_MONO_NG2_CTRL_1:
case RT5665_MONO_NG2_CTRL_2:
case RT5665_MONO_NG2_CTRL_3:
case RT5665_MONO_NG2_CTRL_4:
case RT5665_MONO_NG2_CTRL_5:
case RT5665_MONO_NG2_CTRL_6:
case RT5665_STO1_DAC_SIL_DET:
case RT5665_MONOL_DAC_SIL_DET:
case RT5665_MONOR_DAC_SIL_DET:
case RT5665_STO2_DAC_SIL_DET:
case RT5665_SIL_PSV_CTRL1:
case RT5665_SIL_PSV_CTRL2:
case RT5665_SIL_PSV_CTRL3:
case RT5665_SIL_PSV_CTRL4:
case RT5665_SIL_PSV_CTRL5:
case RT5665_SIL_PSV_CTRL6:
case RT5665_MONO_AMP_CALIB_CTRL_1:
case RT5665_MONO_AMP_CALIB_CTRL_2:
case RT5665_MONO_AMP_CALIB_CTRL_3:
case RT5665_MONO_AMP_CALIB_CTRL_4:
case RT5665_MONO_AMP_CALIB_CTRL_5:
case RT5665_MONO_AMP_CALIB_CTRL_6:
case RT5665_MONO_AMP_CALIB_CTRL_7:
case RT5665_MONO_AMP_CALIB_STA1:
case RT5665_MONO_AMP_CALIB_STA2:
case RT5665_MONO_AMP_CALIB_STA3:
case RT5665_MONO_AMP_CALIB_STA4:
case RT5665_MONO_AMP_CALIB_STA6:
case RT5665_HP_IMP_SENS_CTRL_01:
case RT5665_HP_IMP_SENS_CTRL_02:
case RT5665_HP_IMP_SENS_CTRL_03:
case RT5665_HP_IMP_SENS_CTRL_04:
case RT5665_HP_IMP_SENS_CTRL_05:
case RT5665_HP_IMP_SENS_CTRL_06:
case RT5665_HP_IMP_SENS_CTRL_07:
case RT5665_HP_IMP_SENS_CTRL_08:
case RT5665_HP_IMP_SENS_CTRL_09:
case RT5665_HP_IMP_SENS_CTRL_10:
case RT5665_HP_IMP_SENS_CTRL_11:
case RT5665_HP_IMP_SENS_CTRL_12:
case RT5665_HP_IMP_SENS_CTRL_13:
case RT5665_HP_IMP_SENS_CTRL_14:
case RT5665_HP_IMP_SENS_CTRL_15:
case RT5665_HP_IMP_SENS_CTRL_16:
case RT5665_HP_IMP_SENS_CTRL_17:
case RT5665_HP_IMP_SENS_CTRL_18:
case RT5665_HP_IMP_SENS_CTRL_19:
case RT5665_HP_IMP_SENS_CTRL_20:
case RT5665_HP_IMP_SENS_CTRL_21:
case RT5665_HP_IMP_SENS_CTRL_22:
case RT5665_HP_IMP_SENS_CTRL_23:
case RT5665_HP_IMP_SENS_CTRL_24:
case RT5665_HP_IMP_SENS_CTRL_25:
case RT5665_HP_IMP_SENS_CTRL_26:
case RT5665_HP_IMP_SENS_CTRL_27:
case RT5665_HP_IMP_SENS_CTRL_28:
case RT5665_HP_IMP_SENS_CTRL_29:
case RT5665_HP_IMP_SENS_CTRL_30:
case RT5665_HP_IMP_SENS_CTRL_31:
case RT5665_HP_IMP_SENS_CTRL_32:
case RT5665_HP_IMP_SENS_CTRL_33:
case RT5665_HP_IMP_SENS_CTRL_34:
case RT5665_HP_LOGIC_CTRL_1:
case RT5665_HP_LOGIC_CTRL_2:
case RT5665_HP_LOGIC_CTRL_3:
case RT5665_HP_CALIB_CTRL_1:
case RT5665_HP_CALIB_CTRL_2:
case RT5665_HP_CALIB_CTRL_3:
case RT5665_HP_CALIB_CTRL_4:
case RT5665_HP_CALIB_CTRL_5:
case RT5665_HP_CALIB_CTRL_6:
case RT5665_HP_CALIB_CTRL_7:
case RT5665_HP_CALIB_CTRL_9:
case RT5665_HP_CALIB_CTRL_10:
case RT5665_HP_CALIB_CTRL_11:
case RT5665_HP_CALIB_STA_1:
case RT5665_HP_CALIB_STA_2:
case RT5665_HP_CALIB_STA_3:
case RT5665_HP_CALIB_STA_4:
case RT5665_HP_CALIB_STA_5:
case RT5665_HP_CALIB_STA_6:
case RT5665_HP_CALIB_STA_7:
case RT5665_HP_CALIB_STA_8:
case RT5665_HP_CALIB_STA_9:
case RT5665_HP_CALIB_STA_10:
case RT5665_HP_CALIB_STA_11:
case RT5665_PGM_TAB_CTRL1:
case RT5665_PGM_TAB_CTRL2:
case RT5665_PGM_TAB_CTRL3:
case RT5665_PGM_TAB_CTRL4:
case RT5665_PGM_TAB_CTRL5:
case RT5665_PGM_TAB_CTRL6:
case RT5665_PGM_TAB_CTRL7:
case RT5665_PGM_TAB_CTRL8:
case RT5665_PGM_TAB_CTRL9:
case RT5665_SAR_IL_CMD_1:
case RT5665_SAR_IL_CMD_2:
case RT5665_SAR_IL_CMD_3:
case RT5665_SAR_IL_CMD_4:
case RT5665_SAR_IL_CMD_5:
case RT5665_SAR_IL_CMD_6:
case RT5665_SAR_IL_CMD_7:
case RT5665_SAR_IL_CMD_8:
case RT5665_SAR_IL_CMD_9:
case RT5665_SAR_IL_CMD_10:
case RT5665_SAR_IL_CMD_11:
case RT5665_SAR_IL_CMD_12:
case RT5665_DRC1_CTRL_0:
case RT5665_DRC1_CTRL_1:
case RT5665_DRC1_CTRL_2:
case RT5665_DRC1_CTRL_3:
case RT5665_DRC1_CTRL_4:
case RT5665_DRC1_CTRL_5:
case RT5665_DRC1_CTRL_6:
case RT5665_DRC1_HARD_LMT_CTRL_1:
case RT5665_DRC1_HARD_LMT_CTRL_2:
case RT5665_DRC1_PRIV_1:
case RT5665_DRC1_PRIV_2:
case RT5665_DRC1_PRIV_3:
case RT5665_DRC1_PRIV_4:
case RT5665_DRC1_PRIV_5:
case RT5665_DRC1_PRIV_6:
case RT5665_DRC1_PRIV_7:
case RT5665_DRC1_PRIV_8:
case RT5665_ALC_PGA_CTRL_1:
case RT5665_ALC_PGA_CTRL_2:
case RT5665_ALC_PGA_CTRL_3:
case RT5665_ALC_PGA_CTRL_4:
case RT5665_ALC_PGA_CTRL_5:
case RT5665_ALC_PGA_CTRL_6:
case RT5665_ALC_PGA_CTRL_7:
case RT5665_ALC_PGA_CTRL_8:
case RT5665_ALC_PGA_STA_1:
case RT5665_ALC_PGA_STA_2:
case RT5665_ALC_PGA_STA_3:
case RT5665_EQ_AUTO_RCV_CTRL1:
case RT5665_EQ_AUTO_RCV_CTRL2:
case RT5665_EQ_AUTO_RCV_CTRL3:
case RT5665_EQ_AUTO_RCV_CTRL4:
case RT5665_EQ_AUTO_RCV_CTRL5:
case RT5665_EQ_AUTO_RCV_CTRL6:
case RT5665_EQ_AUTO_RCV_CTRL7:
case RT5665_EQ_AUTO_RCV_CTRL8:
case RT5665_EQ_AUTO_RCV_CTRL9:
case RT5665_EQ_AUTO_RCV_CTRL10:
case RT5665_EQ_AUTO_RCV_CTRL11:
case RT5665_EQ_AUTO_RCV_CTRL12:
case RT5665_EQ_AUTO_RCV_CTRL13:
case RT5665_ADC_L_EQ_LPF1_A1:
case RT5665_R_EQ_LPF1_A1:
case RT5665_L_EQ_LPF1_H0:
case RT5665_R_EQ_LPF1_H0:
case RT5665_L_EQ_BPF1_A1:
case RT5665_R_EQ_BPF1_A1:
case RT5665_L_EQ_BPF1_A2:
case RT5665_R_EQ_BPF1_A2:
case RT5665_L_EQ_BPF1_H0:
case RT5665_R_EQ_BPF1_H0:
case RT5665_L_EQ_BPF2_A1:
case RT5665_R_EQ_BPF2_A1:
case RT5665_L_EQ_BPF2_A2:
case RT5665_R_EQ_BPF2_A2:
case RT5665_L_EQ_BPF2_H0:
case RT5665_R_EQ_BPF2_H0:
case RT5665_L_EQ_BPF3_A1:
case RT5665_R_EQ_BPF3_A1:
case RT5665_L_EQ_BPF3_A2:
case RT5665_R_EQ_BPF3_A2:
case RT5665_L_EQ_BPF3_H0:
case RT5665_R_EQ_BPF3_H0:
case RT5665_L_EQ_BPF4_A1:
case RT5665_R_EQ_BPF4_A1:
case RT5665_L_EQ_BPF4_A2:
case RT5665_R_EQ_BPF4_A2:
case RT5665_L_EQ_BPF4_H0:
case RT5665_R_EQ_BPF4_H0:
case RT5665_L_EQ_HPF1_A1:
case RT5665_R_EQ_HPF1_A1:
case RT5665_L_EQ_HPF1_H0:
case RT5665_R_EQ_HPF1_H0:
case RT5665_L_EQ_PRE_VOL:
case RT5665_R_EQ_PRE_VOL:
case RT5665_L_EQ_POST_VOL:
case RT5665_R_EQ_POST_VOL:
case RT5665_SCAN_MODE_CTRL:
case RT5665_I2C_MODE:
return true;
default:
return false;
}
}
static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0);
static const DECLARE_TLV_DB_SCALE(mono_vol_tlv, -1400, 150, 0);
static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
static const DECLARE_TLV_DB_SCALE(in_bst_tlv, -1200, 75, 0);
/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
static const DECLARE_TLV_DB_RANGE(bst_tlv,
0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
);
/* Interface data select */
static const char * const rt5665_data_select[] = {
"L/R", "R/L", "L/L", "R/R"
};
static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_01_adc_enum,
RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT01_SFT, rt5665_data_select);
static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_23_adc_enum,
RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT23_SFT, rt5665_data_select);
static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_45_adc_enum,
RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT45_SFT, rt5665_data_select);
static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_67_adc_enum,
RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT67_SFT, rt5665_data_select);
static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_01_adc_enum,
RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT01_SFT, rt5665_data_select);
static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_23_adc_enum,
RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT23_SFT, rt5665_data_select);
static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_45_adc_enum,
RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT45_SFT, rt5665_data_select);
static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_67_adc_enum,
RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT67_SFT, rt5665_data_select);
static SOC_ENUM_SINGLE_DECL(rt5665_if2_1_dac_enum,
RT5665_DIG_INF2_DATA, RT5665_IF2_1_DAC_SEL_SFT, rt5665_data_select);
static SOC_ENUM_SINGLE_DECL(rt5665_if2_1_adc_enum,
RT5665_DIG_INF2_DATA, RT5665_IF2_1_ADC_SEL_SFT, rt5665_data_select);
static SOC_ENUM_SINGLE_DECL(rt5665_if2_2_dac_enum,
RT5665_DIG_INF2_DATA, RT5665_IF2_2_DAC_SEL_SFT, rt5665_data_select);
static SOC_ENUM_SINGLE_DECL(rt5665_if2_2_adc_enum,
RT5665_DIG_INF2_DATA, RT5665_IF2_2_ADC_SEL_SFT, rt5665_data_select);
static SOC_ENUM_SINGLE_DECL(rt5665_if3_dac_enum,
RT5665_DIG_INF3_DATA, RT5665_IF3_DAC_SEL_SFT, rt5665_data_select);
static SOC_ENUM_SINGLE_DECL(rt5665_if3_adc_enum,
RT5665_DIG_INF3_DATA, RT5665_IF3_ADC_SEL_SFT, rt5665_data_select);
static const struct snd_kcontrol_new rt5665_if1_1_01_adc_swap_mux =
SOC_DAPM_ENUM("IF1_1 01 ADC Swap Mux", rt5665_if1_1_01_adc_enum);
static const struct snd_kcontrol_new rt5665_if1_1_23_adc_swap_mux =
SOC_DAPM_ENUM("IF1_1 23 ADC Swap Mux", rt5665_if1_1_23_adc_enum);
static const struct snd_kcontrol_new rt5665_if1_1_45_adc_swap_mux =
SOC_DAPM_ENUM("IF1_1 45 ADC Swap Mux", rt5665_if1_1_45_adc_enum);
static const struct snd_kcontrol_new rt5665_if1_1_67_adc_swap_mux =
SOC_DAPM_ENUM("IF1_1 67 ADC Swap Mux", rt5665_if1_1_67_adc_enum);
static const struct snd_kcontrol_new rt5665_if1_2_01_adc_swap_mux =
SOC_DAPM_ENUM("IF1_2 01 ADC Swap Mux", rt5665_if1_2_01_adc_enum);
static const struct snd_kcontrol_new rt5665_if1_2_23_adc_swap_mux =
SOC_DAPM_ENUM("IF1_2 23 ADC1 Swap Mux", rt5665_if1_2_23_adc_enum);
static const struct snd_kcontrol_new rt5665_if1_2_45_adc_swap_mux =
SOC_DAPM_ENUM("IF1_2 45 ADC1 Swap Mux", rt5665_if1_2_45_adc_enum);
static const struct snd_kcontrol_new rt5665_if1_2_67_adc_swap_mux =
SOC_DAPM_ENUM("IF1_2 67 ADC1 Swap Mux", rt5665_if1_2_67_adc_enum);
static const struct snd_kcontrol_new rt5665_if2_1_dac_swap_mux =
SOC_DAPM_ENUM("IF2_1 DAC Swap Source", rt5665_if2_1_dac_enum);
static const struct snd_kcontrol_new rt5665_if2_1_adc_swap_mux =
SOC_DAPM_ENUM("IF2_1 ADC Swap Source", rt5665_if2_1_adc_enum);
static const struct snd_kcontrol_new rt5665_if2_2_dac_swap_mux =
SOC_DAPM_ENUM("IF2_2 DAC Swap Source", rt5665_if2_2_dac_enum);
static const struct snd_kcontrol_new rt5665_if2_2_adc_swap_mux =
SOC_DAPM_ENUM("IF2_2 ADC Swap Source", rt5665_if2_2_adc_enum);
static const struct snd_kcontrol_new rt5665_if3_dac_swap_mux =
SOC_DAPM_ENUM("IF3 DAC Swap Source", rt5665_if3_dac_enum);
static const struct snd_kcontrol_new rt5665_if3_adc_swap_mux =
SOC_DAPM_ENUM("IF3 ADC Swap Source", rt5665_if3_adc_enum);
static int rt5665_hp_vol_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
int ret = snd_soc_put_volsw(kcontrol, ucontrol);
if (snd_soc_component_read(component, RT5665_STO_NG2_CTRL_1) & RT5665_NG2_EN) {
snd_soc_component_update_bits(component, RT5665_STO_NG2_CTRL_1,
RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
snd_soc_component_update_bits(component, RT5665_STO_NG2_CTRL_1,
RT5665_NG2_EN_MASK, RT5665_NG2_EN);
}
return ret;
}
static int rt5665_mono_vol_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
int ret = snd_soc_put_volsw(kcontrol, ucontrol);
if (snd_soc_component_read(component, RT5665_MONO_NG2_CTRL_1) & RT5665_NG2_EN) {
snd_soc_component_update_bits(component, RT5665_MONO_NG2_CTRL_1,
RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
snd_soc_component_update_bits(component, RT5665_MONO_NG2_CTRL_1,
RT5665_NG2_EN_MASK, RT5665_NG2_EN);
}
return ret;
}
/**
* rt5665_sel_asrc_clk_src - select ASRC clock source for a set of filters
* @component: SoC audio component device.
* @filter_mask: mask of filters.
* @clk_src: clock source
*
* The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5665 can
* only support standard 32fs or 64fs i2s format, ASRC should be enabled to
* support special i2s clock format such as Intel's 100fs(100 * sampling rate).
* ASRC function will track i2s clock and generate a corresponding system clock
* for codec. This function provides an API to select the clock source for a
* set of filters specified by the mask. And the codec driver will turn on ASRC
* for these filters if ASRC is selected as their clock source.
*/
int rt5665_sel_asrc_clk_src(struct snd_soc_component *component,
unsigned int filter_mask, unsigned int clk_src)
{
unsigned int asrc2_mask = 0;
unsigned int asrc2_value = 0;
unsigned int asrc3_mask = 0;
unsigned int asrc3_value = 0;
switch (clk_src) {
case RT5665_CLK_SEL_SYS:
case RT5665_CLK_SEL_I2S1_ASRC:
case RT5665_CLK_SEL_I2S2_ASRC:
case RT5665_CLK_SEL_I2S3_ASRC:
case RT5665_CLK_SEL_SYS2:
case RT5665_CLK_SEL_SYS3:
case RT5665_CLK_SEL_SYS4:
break;
default:
return -EINVAL;
}
if (filter_mask & RT5665_DA_STEREO1_FILTER) {
asrc2_mask |= RT5665_DA_STO1_CLK_SEL_MASK;
asrc2_value = (asrc2_value & ~RT5665_DA_STO1_CLK_SEL_MASK)
| (clk_src << RT5665_DA_STO1_CLK_SEL_SFT);
}
if (filter_mask & RT5665_DA_STEREO2_FILTER) {
asrc2_mask |= RT5665_DA_STO2_CLK_SEL_MASK;
asrc2_value = (asrc2_value & ~RT5665_DA_STO2_CLK_SEL_MASK)
| (clk_src << RT5665_DA_STO2_CLK_SEL_SFT);
}
if (filter_mask & RT5665_DA_MONO_L_FILTER) {
asrc2_mask |= RT5665_DA_MONOL_CLK_SEL_MASK;
asrc2_value = (asrc2_value & ~RT5665_DA_MONOL_CLK_SEL_MASK)
| (clk_src << RT5665_DA_MONOL_CLK_SEL_SFT);
}
if (filter_mask & RT5665_DA_MONO_R_FILTER) {
asrc2_mask |= RT5665_DA_MONOR_CLK_SEL_MASK;
asrc2_value = (asrc2_value & ~RT5665_DA_MONOR_CLK_SEL_MASK)
| (clk_src << RT5665_DA_MONOR_CLK_SEL_SFT);
}
if (filter_mask & RT5665_AD_STEREO1_FILTER) {
asrc3_mask |= RT5665_AD_STO1_CLK_SEL_MASK;
asrc3_value = (asrc2_value & ~RT5665_AD_STO1_CLK_SEL_MASK)
| (clk_src << RT5665_AD_STO1_CLK_SEL_SFT);
}
if (filter_mask & RT5665_AD_STEREO2_FILTER) {
asrc3_mask |= RT5665_AD_STO2_CLK_SEL_MASK;
asrc3_value = (asrc2_value & ~RT5665_AD_STO2_CLK_SEL_MASK)
| (clk_src << RT5665_AD_STO2_CLK_SEL_SFT);
}
if (filter_mask & RT5665_AD_MONO_L_FILTER) {
asrc3_mask |= RT5665_AD_MONOL_CLK_SEL_MASK;
asrc3_value = (asrc3_value & ~RT5665_AD_MONOL_CLK_SEL_MASK)
| (clk_src << RT5665_AD_MONOL_CLK_SEL_SFT);
}
if (filter_mask & RT5665_AD_MONO_R_FILTER) {
asrc3_mask |= RT5665_AD_MONOR_CLK_SEL_MASK;
asrc3_value = (asrc3_value & ~RT5665_AD_MONOR_CLK_SEL_MASK)
| (clk_src << RT5665_AD_MONOR_CLK_SEL_SFT);
}
if (asrc2_mask)
snd_soc_component_update_bits(component, RT5665_ASRC_2,
asrc2_mask, asrc2_value);
if (asrc3_mask)
snd_soc_component_update_bits(component, RT5665_ASRC_3,
asrc3_mask, asrc3_value);
return 0;
}
EXPORT_SYMBOL_GPL(rt5665_sel_asrc_clk_src);
static int rt5665_button_detect(struct snd_soc_component *component)
{
int btn_type, val;
val = snd_soc_component_read(component, RT5665_4BTN_IL_CMD_1);
btn_type = val & 0xfff0;
snd_soc_component_write(component, RT5665_4BTN_IL_CMD_1, val);
return btn_type;
}
static void rt5665_enable_push_button_irq(struct snd_soc_component *component,
bool enable)
{
if (enable) {
snd_soc_component_write(component, RT5665_4BTN_IL_CMD_1, 0x0003);
snd_soc_component_update_bits(component, RT5665_SAR_IL_CMD_9, 0x1, 0x1);
snd_soc_component_write(component, RT5665_IL_CMD_1, 0x0048);
snd_soc_component_update_bits(component, RT5665_4BTN_IL_CMD_2,
RT5665_4BTN_IL_MASK | RT5665_4BTN_IL_RST_MASK,
RT5665_4BTN_IL_EN | RT5665_4BTN_IL_NOR);
snd_soc_component_update_bits(component, RT5665_IRQ_CTRL_3,
RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_EN);
} else {
snd_soc_component_update_bits(component, RT5665_IRQ_CTRL_3,
RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_DIS);
snd_soc_component_update_bits(component, RT5665_4BTN_IL_CMD_2,
RT5665_4BTN_IL_MASK, RT5665_4BTN_IL_DIS);
snd_soc_component_update_bits(component, RT5665_4BTN_IL_CMD_2,
RT5665_4BTN_IL_RST_MASK, RT5665_4BTN_IL_RST);
}
}
/**
* rt5665_headset_detect - Detect headset.
* @component: SoC audio component device.
* @jack_insert: Jack insert or not.
*
* Detect whether is headset or not when jack inserted.
*
* Returns detect status.
*/
static int rt5665_headset_detect(struct snd_soc_component *component, int jack_insert)
{
struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
unsigned int sar_hs_type, val;
if (jack_insert) {
snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
snd_soc_dapm_sync(dapm);
regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100,
0x100);
regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val);
if (val & 0x4) {
regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
0x100, 0);
regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val);
while (val & 0x4) {
usleep_range(10000, 15000);
regmap_read(rt5665->regmap, RT5665_GPIO_STA,
&val);
}
}
regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
0x1a0, 0x120);
regmap_write(rt5665->regmap, RT5665_EJD_CTRL_3, 0x3424);
regmap_write(rt5665->regmap, RT5665_IL_CMD_1, 0x0048);
regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0xa291);
usleep_range(10000, 15000);
rt5665->sar_adc_value = snd_soc_component_read(rt5665->component,
RT5665_SAR_IL_CMD_4) & 0x7ff;
sar_hs_type = rt5665->pdata.sar_hs_type ?
rt5665->pdata.sar_hs_type : 729;
if (rt5665->sar_adc_value > sar_hs_type) {
rt5665->jack_type = SND_JACK_HEADSET;
rt5665_enable_push_button_irq(component, true);
} else {
rt5665->jack_type = SND_JACK_HEADPHONE;
regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1,
0x2291);
regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2,
0x100, 0);
snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
snd_soc_dapm_sync(dapm);
}
} else {
regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0x2291);
regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100, 0);
snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
snd_soc_dapm_sync(dapm);
if (rt5665->jack_type == SND_JACK_HEADSET)
rt5665_enable_push_button_irq(component, false);
rt5665->jack_type = 0;
}
dev_dbg(component->dev, "jack_type = %d\n", rt5665->jack_type);
return rt5665->jack_type;
}
static irqreturn_t rt5665_irq(int irq, void *data)
{
struct rt5665_priv *rt5665 = data;
mod_delayed_work(system_power_efficient_wq,
&rt5665->jack_detect_work, msecs_to_jiffies(250));
return IRQ_HANDLED;
}
static void rt5665_jd_check_handler(struct work_struct *work)
{
struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv,
jd_check_work.work);
if (snd_soc_component_read(rt5665->component, RT5665_AJD1_CTRL) & 0x0010) {
/* jack out */
rt5665->jack_type = rt5665_headset_detect(rt5665->component, 0);
snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type,
SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3);
} else {
schedule_delayed_work(&rt5665->jd_check_work, 500);
}
}
static int rt5665_set_jack_detect(struct snd_soc_component *component,
struct snd_soc_jack *hs_jack, void *data)
{
struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
switch (rt5665->pdata.jd_src) {
case RT5665_JD1:
regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
RT5665_GP1_PIN_MASK, RT5665_GP1_PIN_IRQ);
regmap_update_bits(rt5665->regmap, RT5665_RC_CLK_CTRL,
0xc000, 0xc000);
regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_2,
RT5665_PWR_JD1, RT5665_PWR_JD1);
regmap_update_bits(rt5665->regmap, RT5665_IRQ_CTRL_1, 0x8, 0x8);
break;
case RT5665_JD_NULL:
break;
default:
dev_warn(component->dev, "Wrong JD source\n");
break;
}
rt5665->hs_jack = hs_jack;
return 0;
}
static void rt5665_jack_detect_handler(struct work_struct *work)
{
struct rt5665_priv *rt5665 =
container_of(work, struct rt5665_priv, jack_detect_work.work);
int val, btn_type;
while (!rt5665->component) {
pr_debug("%s codec = null\n", __func__);
usleep_range(10000, 15000);
}
while (!snd_soc_card_is_instantiated(rt5665->component->card)) {
pr_debug("%s\n", __func__);
usleep_range(10000, 15000);
}
while (!rt5665->calibration_done) {
pr_debug("%s calibration not ready\n", __func__);
usleep_range(10000, 15000);
}
mutex_lock(&rt5665->calibrate_mutex);
val = snd_soc_component_read(rt5665->component, RT5665_AJD1_CTRL) & 0x0010;
if (!val) {
/* jack in */
if (rt5665->jack_type == 0) {
/* jack was out, report jack type */
rt5665->jack_type =
rt5665_headset_detect(rt5665->component, 1);
} else {
/* jack is already in, report button event */
rt5665->jack_type = SND_JACK_HEADSET;
btn_type = rt5665_button_detect(rt5665->component);
/**
* rt5665 can report three kinds of button behavior,
* one click, double click and hold. However,
* currently we will report button pressed/released
* event. So all the three button behaviors are
* treated as button pressed.
*/
switch (btn_type) {
case 0x8000:
case 0x4000:
case 0x2000:
rt5665->jack_type |= SND_JACK_BTN_0;
break;
case 0x1000:
case 0x0800:
case 0x0400:
rt5665->jack_type |= SND_JACK_BTN_1;
break;
case 0x0200:
case 0x0100:
case 0x0080:
rt5665->jack_type |= SND_JACK_BTN_2;
break;
case 0x0040:
case 0x0020:
case 0x0010:
rt5665->jack_type |= SND_JACK_BTN_3;
break;
case 0x0000: /* unpressed */
break;
default:
btn_type = 0;
dev_err(rt5665->component->dev,
"Unexpected button code 0x%04x\n",
btn_type);
break;
}
}
} else {
/* jack out */
rt5665->jack_type = rt5665_headset_detect(rt5665->component, 0);
}
snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type,
SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3);
if (rt5665->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3))
schedule_delayed_work(&rt5665->jd_check_work, 0);
else
cancel_delayed_work_sync(&rt5665->jd_check_work);
mutex_unlock(&rt5665->calibrate_mutex);
}
static const char * const rt5665_clk_sync[] = {
"I2S1_1", "I2S1_2", "I2S2", "I2S3", "IF2 Slave", "IF3 Slave"
};
static const struct soc_enum rt5665_enum[] = {
SOC_ENUM_SINGLE(RT5665_I2S1_SDP, 11, 5, rt5665_clk_sync),
SOC_ENUM_SINGLE(RT5665_I2S2_SDP, 11, 5, rt5665_clk_sync),
SOC_ENUM_SINGLE(RT5665_I2S3_SDP, 11, 5, rt5665_clk_sync),
};
static const struct snd_kcontrol_new rt5665_snd_controls[] = {
/* Headphone Output Volume */
SOC_DOUBLE_R_EXT_TLV("Headphone Playback Volume", RT5665_HPL_GAIN,
RT5665_HPR_GAIN, RT5665_G_HP_SFT, 15, 1, snd_soc_get_volsw,
rt5665_hp_vol_put, hp_vol_tlv),
/* Mono Output Volume */
SOC_SINGLE_EXT_TLV("Mono Playback Volume", RT5665_MONO_GAIN,
RT5665_L_VOL_SFT, 15, 1, snd_soc_get_volsw,
rt5665_mono_vol_put, mono_vol_tlv),
SOC_SINGLE_TLV("MONOVOL Playback Volume", RT5665_MONO_OUT,
RT5665_L_VOL_SFT, 39, 1, out_vol_tlv),
/* Output Volume */
SOC_DOUBLE_TLV("OUT Playback Volume", RT5665_LOUT, RT5665_L_VOL_SFT,
RT5665_R_VOL_SFT, 39, 1, out_vol_tlv),
/* DAC Digital Volume */
SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5665_DAC1_DIG_VOL,
RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv),
SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5665_DAC2_DIG_VOL,
RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv),
SOC_DOUBLE("DAC2 Playback Switch", RT5665_DAC2_CTRL,
RT5665_M_DAC2_L_VOL_SFT, RT5665_M_DAC2_R_VOL_SFT, 1, 1),
/* IN1/IN2/IN3/IN4 Volume */
SOC_SINGLE_TLV("IN1 Boost Volume", RT5665_IN1_IN2,
RT5665_BST1_SFT, 69, 0, in_bst_tlv),
SOC_SINGLE_TLV("IN2 Boost Volume", RT5665_IN1_IN2,
RT5665_BST2_SFT, 69, 0, in_bst_tlv),
SOC_SINGLE_TLV("IN3 Boost Volume", RT5665_IN3_IN4,
RT5665_BST3_SFT, 69, 0, in_bst_tlv),
SOC_SINGLE_TLV("IN4 Boost Volume", RT5665_IN3_IN4,
RT5665_BST4_SFT, 69, 0, in_bst_tlv),
SOC_SINGLE_TLV("CBJ Boost Volume", RT5665_CBJ_BST_CTRL,
RT5665_BST_CBJ_SFT, 8, 0, bst_tlv),
/* INL/INR Volume Control */
SOC_DOUBLE_TLV("IN Capture Volume", RT5665_INL1_INR1_VOL,
RT5665_INL_VOL_SFT, RT5665_INR_VOL_SFT, 31, 1, in_vol_tlv),
/* ADC Digital Volume Control */
SOC_DOUBLE("STO1 ADC Capture Switch", RT5665_STO1_ADC_DIG_VOL,
RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5665_STO1_ADC_DIG_VOL,
RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
SOC_DOUBLE("Mono ADC Capture Switch", RT5665_MONO_ADC_DIG_VOL,
RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5665_MONO_ADC_DIG_VOL,
RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
SOC_DOUBLE("STO2 ADC Capture Switch", RT5665_STO2_ADC_DIG_VOL,
RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
SOC_DOUBLE_TLV("STO2 ADC Capture Volume", RT5665_STO2_ADC_DIG_VOL,
RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
/* ADC Boost Volume Control */
SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5665_STO1_ADC_BOOST,
RT5665_STO1_ADC_L_BST_SFT, RT5665_STO1_ADC_R_BST_SFT,
3, 0, adc_bst_tlv),
SOC_DOUBLE_TLV("Mono ADC Boost Gain Volume", RT5665_MONO_ADC_BOOST,
RT5665_MONO_ADC_L_BST_SFT, RT5665_MONO_ADC_R_BST_SFT,
3, 0, adc_bst_tlv),
SOC_DOUBLE_TLV("STO2 ADC Boost Gain Volume", RT5665_STO2_ADC_BOOST,
RT5665_STO2_ADC_L_BST_SFT, RT5665_STO2_ADC_R_BST_SFT,
3, 0, adc_bst_tlv),
/* I2S3 CLK Source */
SOC_ENUM("I2S1 Master Clk Sel", rt5665_enum[0]),
SOC_ENUM("I2S2 Master Clk Sel", rt5665_enum[1]),
SOC_ENUM("I2S3 Master Clk Sel", rt5665_enum[2]),
};
/**
* set_dmic_clk - Set parameter of dmic.
*
* @w: DAPM widget.
* @kcontrol: The kcontrol of this widget.
* @event: Event id.
*
* Choose dmic clock between 1MHz and 3MHz.
* It is better for clock to approximate 3MHz.
*/
static int set_dmic_clk(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
int pd, idx;
pd = rl6231_get_pre_div(rt5665->regmap,
RT5665_ADDA_CLK_1, RT5665_I2S_PD1_SFT);
idx = rl6231_calc_dmic_clk(rt5665->sysclk / pd);
if (idx < 0)
dev_err(component->dev, "Failed to set DMIC clock\n");
else {
snd_soc_component_update_bits(component, RT5665_DMIC_CTRL_1,
RT5665_DMIC_CLK_MASK, idx << RT5665_DMIC_CLK_SFT);
}
return idx;
}
static int rt5665_charge_pump_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_component_update_bits(component, RT5665_HP_CHARGE_PUMP_1,
RT5665_PM_HP_MASK | RT5665_OSW_L_MASK,
RT5665_PM_HP_HV | RT5665_OSW_L_EN);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component, RT5665_HP_CHARGE_PUMP_1,
RT5665_PM_HP_MASK | RT5665_OSW_L_MASK,
RT5665_PM_HP_LV | RT5665_OSW_L_DIS);
break;
default:
return 0;
}
return 0;
}
static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
struct snd_soc_dapm_widget *sink)
{
unsigned int val;
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
val = snd_soc_component_read(component, RT5665_GLB_CLK);
val &= RT5665_SCLK_SRC_MASK;
if (val == RT5665_SCLK_SRC_PLL1)
return 1;
else
return 0;
}
static int is_using_asrc(struct snd_soc_dapm_widget *w,
struct snd_soc_dapm_widget *sink)
{
unsigned int reg, shift, val;
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (w->shift) {
case RT5665_ADC_MONO_R_ASRC_SFT:
reg = RT5665_ASRC_3;
shift = RT5665_AD_MONOR_CLK_SEL_SFT;
break;
case RT5665_ADC_MONO_L_ASRC_SFT:
reg = RT5665_ASRC_3;
shift = RT5665_AD_MONOL_CLK_SEL_SFT;
break;
case RT5665_ADC_STO1_ASRC_SFT:
reg = RT5665_ASRC_3;
shift = RT5665_AD_STO1_CLK_SEL_SFT;
break;
case RT5665_ADC_STO2_ASRC_SFT:
reg = RT5665_ASRC_3;
shift = RT5665_AD_STO2_CLK_SEL_SFT;
break;
case RT5665_DAC_MONO_R_ASRC_SFT:
reg = RT5665_ASRC_2;
shift = RT5665_DA_MONOR_CLK_SEL_SFT;
break;
case RT5665_DAC_MONO_L_ASRC_SFT:
reg = RT5665_ASRC_2;
shift = RT5665_DA_MONOL_CLK_SEL_SFT;
break;
case RT5665_DAC_STO1_ASRC_SFT:
reg = RT5665_ASRC_2;
shift = RT5665_DA_STO1_CLK_SEL_SFT;
break;
case RT5665_DAC_STO2_ASRC_SFT:
reg = RT5665_ASRC_2;
shift = RT5665_DA_STO2_CLK_SEL_SFT;
break;
default:
return 0;
}
val = (snd_soc_component_read(component, reg) >> shift) & 0xf;
switch (val) {
case RT5665_CLK_SEL_I2S1_ASRC:
case RT5665_CLK_SEL_I2S2_ASRC:
case RT5665_CLK_SEL_I2S3_ASRC:
/* I2S_Pre_Div1 should be 1 in asrc mode */
snd_soc_component_update_bits(component, RT5665_ADDA_CLK_1,
RT5665_I2S_PD1_MASK, RT5665_I2S_PD1_2);
return 1;
default:
return 0;
}
}
/* Digital Mixer */
static const struct snd_kcontrol_new rt5665_sto1_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO1_ADC_MIXER,
RT5665_M_STO1_ADC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO1_ADC_MIXER,
RT5665_M_STO1_ADC_L2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5665_sto1_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO1_ADC_MIXER,
RT5665_M_STO1_ADC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO1_ADC_MIXER,
RT5665_M_STO1_ADC_R2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5665_sto2_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO2_ADC_MIXER,
RT5665_M_STO2_ADC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO2_ADC_MIXER,
RT5665_M_STO2_ADC_L2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5665_sto2_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO2_ADC_MIXER,
RT5665_M_STO2_ADC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO2_ADC_MIXER,
RT5665_M_STO2_ADC_R2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5665_mono_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5665_MONO_ADC_MIXER,
RT5665_M_MONO_ADC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5665_MONO_ADC_MIXER,
RT5665_M_MONO_ADC_L2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5665_mono_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5665_MONO_ADC_MIXER,
RT5665_M_MONO_ADC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5665_MONO_ADC_MIXER,
RT5665_M_MONO_ADC_R2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5665_dac_l_mix[] = {
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5665_AD_DA_MIXER,
RT5665_M_ADCMIX_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC1 Switch", RT5665_AD_DA_MIXER,
RT5665_M_DAC1_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5665_dac_r_mix[] = {
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5665_AD_DA_MIXER,
RT5665_M_ADCMIX_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC1 Switch", RT5665_AD_DA_MIXER,
RT5665_M_DAC1_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5665_sto1_dac_l_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO1_DAC_MIXER,
RT5665_M_DAC_L1_STO_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO1_DAC_MIXER,
RT5665_M_DAC_R1_STO_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO1_DAC_MIXER,
RT5665_M_DAC_L2_STO_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO1_DAC_MIXER,
RT5665_M_DAC_R2_STO_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5665_sto1_dac_r_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO1_DAC_MIXER,
RT5665_M_DAC_L1_STO_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO1_DAC_MIXER,
RT5665_M_DAC_R1_STO_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO1_DAC_MIXER,
RT5665_M_DAC_L2_STO_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO1_DAC_MIXER,
RT5665_M_DAC_R2_STO_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5665_sto2_dac_l_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO2_DAC_MIXER,
RT5665_M_DAC_L1_STO2_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO2_DAC_MIXER,
RT5665_M_DAC_L2_STO2_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L3 Switch", RT5665_STO2_DAC_MIXER,
RT5665_M_DAC_L3_STO2_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5665_sto2_dac_r_mix[] = {
SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO2_DAC_MIXER,
RT5665_M_DAC_R1_STO2_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO2_DAC_MIXER,
RT5665_M_DAC_R2_STO2_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R3 Switch", RT5665_STO2_DAC_MIXER,
RT5665_M_DAC_R3_STO2_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5665_mono_dac_l_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_MONO_DAC_MIXER,
RT5665_M_DAC_L1_MONO_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_MONO_DAC_MIXER,
RT5665_M_DAC_R1_MONO_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONO_DAC_MIXER,
RT5665_M_DAC_L2_MONO_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_MONO_DAC_MIXER,
RT5665_M_DAC_R2_MONO_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5665_mono_dac_r_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_MONO_DAC_MIXER,
RT5665_M_DAC_L1_MONO_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_MONO_DAC_MIXER,
RT5665_M_DAC_R1_MONO_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONO_DAC_MIXER,
RT5665_M_DAC_L2_MONO_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_MONO_DAC_MIXER,
RT5665_M_DAC_R2_MONO_R_SFT, 1, 1),
};
/* Analog Input Mixer */
static const struct snd_kcontrol_new rt5665_rec1_l_mix[] = {
SOC_DAPM_SINGLE("CBJ Switch", RT5665_REC1_L2_MIXER,
RT5665_M_CBJ_RM1_L_SFT, 1, 1),
SOC_DAPM_SINGLE("INL Switch", RT5665_REC1_L2_MIXER,
RT5665_M_INL_RM1_L_SFT, 1, 1),
SOC_DAPM_SINGLE("INR Switch", RT5665_REC1_L2_MIXER,
RT5665_M_INR_RM1_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC1_L2_MIXER,
RT5665_M_BST4_RM1_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC1_L2_MIXER,
RT5665_M_BST3_RM1_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC1_L2_MIXER,
RT5665_M_BST2_RM1_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC1_L2_MIXER,
RT5665_M_BST1_RM1_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5665_rec1_r_mix[] = {
SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_REC1_R2_MIXER,
RT5665_M_AEC_REF_RM1_R_SFT, 1, 1),
SOC_DAPM_SINGLE("INR Switch", RT5665_REC1_R2_MIXER,
RT5665_M_INR_RM1_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC1_R2_MIXER,
RT5665_M_BST4_RM1_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC1_R2_MIXER,
RT5665_M_BST3_RM1_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC1_R2_MIXER,
RT5665_M_BST2_RM1_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC1_R2_MIXER,
RT5665_M_BST1_RM1_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5665_rec2_l_mix[] = {
SOC_DAPM_SINGLE("INL Switch", RT5665_REC2_L2_MIXER,
RT5665_M_INL_RM2_L_SFT, 1, 1),
SOC_DAPM_SINGLE("INR Switch", RT5665_REC2_L2_MIXER,
RT5665_M_INR_RM2_L_SFT, 1, 1),
SOC_DAPM_SINGLE("CBJ Switch", RT5665_REC2_L2_MIXER,
RT5665_M_CBJ_RM2_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC2_L2_MIXER,
RT5665_M_BST4_RM2_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC2_L2_MIXER,
RT5665_M_BST3_RM2_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC2_L2_MIXER,
RT5665_M_BST2_RM2_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC2_L2_MIXER,
RT5665_M_BST1_RM2_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5665_rec2_r_mix[] = {
SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_REC2_R2_MIXER,
RT5665_M_MONOVOL_RM2_R_SFT, 1, 1),
SOC_DAPM_SINGLE("INL Switch", RT5665_REC2_R2_MIXER,
RT5665_M_INL_RM2_R_SFT, 1, 1),
SOC_DAPM_SINGLE("INR Switch", RT5665_REC2_R2_MIXER,
RT5665_M_INR_RM2_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC2_R2_MIXER,
RT5665_M_BST4_RM2_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC2_R2_MIXER,
RT5665_M_BST3_RM2_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC2_R2_MIXER,
RT5665_M_BST2_RM2_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC2_R2_MIXER,
RT5665_M_BST1_RM2_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5665_monovol_mix[] = {
SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONOMIX_IN_GAIN,
RT5665_M_DAC_L2_MM_SFT, 1, 1),
SOC_DAPM_SINGLE("RECMIX2L Switch", RT5665_MONOMIX_IN_GAIN,
RT5665_M_RECMIC2L_MM_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5665_MONOMIX_IN_GAIN,
RT5665_M_BST1_MM_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5665_MONOMIX_IN_GAIN,
RT5665_M_BST2_MM_SFT, 1, 1),
SOC_DAPM_SINGLE("BST3 Switch", RT5665_MONOMIX_IN_GAIN,
RT5665_M_BST3_MM_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5665_out_l_mix[] = {
SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_OUT_L_MIXER,
RT5665_M_DAC_L2_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("INL Switch", RT5665_OUT_L_MIXER,
RT5665_M_IN_L_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5665_OUT_L_MIXER,
RT5665_M_BST1_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5665_OUT_L_MIXER,
RT5665_M_BST2_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST3 Switch", RT5665_OUT_L_MIXER,
RT5665_M_BST3_OM_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5665_out_r_mix[] = {
SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_OUT_R_MIXER,
RT5665_M_DAC_R2_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("INR Switch", RT5665_OUT_R_MIXER,
RT5665_M_IN_R_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5665_OUT_R_MIXER,
RT5665_M_BST2_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST3 Switch", RT5665_OUT_R_MIXER,
RT5665_M_BST3_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST4 Switch", RT5665_OUT_R_MIXER,
RT5665_M_BST4_OM_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5665_mono_mix[] = {
SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONOMIX_IN_GAIN,
RT5665_M_DAC_L2_MA_SFT, 1, 1),
SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_MONOMIX_IN_GAIN,
RT5665_M_MONOVOL_MA_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5665_lout_l_mix[] = {
SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_LOUT_MIXER,
RT5665_M_DAC_L2_LM_SFT, 1, 1),
SOC_DAPM_SINGLE("OUTVOL L Switch", RT5665_LOUT_MIXER,
RT5665_M_OV_L_LM_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5665_lout_r_mix[] = {
SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_LOUT_MIXER,
RT5665_M_DAC_R2_LM_SFT, 1, 1),
SOC_DAPM_SINGLE("OUTVOL R Switch", RT5665_LOUT_MIXER,
RT5665_M_OV_R_LM_SFT, 1, 1),
};
/*DAC L2, DAC R2*/
/*MX-17 [6:4], MX-17 [2:0]*/
static const char * const rt5665_dac2_src[] = {
"IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC", "Mono ADC MIX"
};
static SOC_ENUM_SINGLE_DECL(
rt5665_dac_l2_enum, RT5665_DAC2_CTRL,
RT5665_DAC_L2_SEL_SFT, rt5665_dac2_src);
static const struct snd_kcontrol_new rt5665_dac_l2_mux =
SOC_DAPM_ENUM("Digital DAC L2 Source", rt5665_dac_l2_enum);
static SOC_ENUM_SINGLE_DECL(
rt5665_dac_r2_enum, RT5665_DAC2_CTRL,
RT5665_DAC_R2_SEL_SFT, rt5665_dac2_src);
static const struct snd_kcontrol_new rt5665_dac_r2_mux =
SOC_DAPM_ENUM("Digital DAC R2 Source", rt5665_dac_r2_enum);
/*DAC L3, DAC R3*/
/*MX-1B [6:4], MX-1B [2:0]*/
static const char * const rt5665_dac3_src[] = {
"IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC", "STO2 ADC MIX"
};
static SOC_ENUM_SINGLE_DECL(
rt5665_dac_l3_enum, RT5665_DAC3_CTRL,
RT5665_DAC_L3_SEL_SFT, rt5665_dac3_src);
static const struct snd_kcontrol_new rt5665_dac_l3_mux =
SOC_DAPM_ENUM("Digital DAC L3 Source", rt5665_dac_l3_enum);
static SOC_ENUM_SINGLE_DECL(
rt5665_dac_r3_enum, RT5665_DAC3_CTRL,
RT5665_DAC_R3_SEL_SFT, rt5665_dac3_src);
static const struct snd_kcontrol_new rt5665_dac_r3_mux =
SOC_DAPM_ENUM("Digital DAC R3 Source", rt5665_dac_r3_enum);
/* STO1 ADC1 Source */
/* MX-26 [13] [5] */
static const char * const rt5665_sto1_adc1_src[] = {
"DD Mux", "ADC"
};
static SOC_ENUM_SINGLE_DECL(
rt5665_sto1_adc1l_enum, RT5665_STO1_ADC_MIXER,
RT5665_STO1_ADC1L_SRC_SFT, rt5665_sto1_adc1_src);
static const struct snd_kcontrol_new rt5665_sto1_adc1l_mux =
SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5665_sto1_adc1l_enum);
static SOC_ENUM_SINGLE_DECL(
rt5665_sto1_adc1r_enum, RT5665_STO1_ADC_MIXER,
RT5665_STO1_ADC1R_SRC_SFT, rt5665_sto1_adc1_src);
static const struct snd_kcontrol_new rt5665_sto1_adc1r_mux =
SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5665_sto1_adc1r_enum);
/* STO1 ADC Source */
/* MX-26 [11:10] [3:2] */
static const char * const rt5665_sto1_adc_src[] = {
"ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
};
static SOC_ENUM_SINGLE_DECL(
rt5665_sto1_adcl_enum, RT5665_STO1_ADC_MIXER,
RT5665_STO1_ADCL_SRC_SFT, rt5665_sto1_adc_src);
static const struct snd_kcontrol_new rt5665_sto1_adcl_mux =
SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5665_sto1_adcl_enum);
static SOC_ENUM_SINGLE_DECL(
rt5665_sto1_adcr_enum, RT5665_STO1_ADC_MIXER,
RT5665_STO1_ADCR_SRC_SFT, rt5665_sto1_adc_src);
static const struct snd_kcontrol_new rt5665_sto1_adcr_mux =
SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5665_sto1_adcr_enum);
/* STO1 ADC2 Source */
/* MX-26 [12] [4] */
static const char * const rt5665_sto1_adc2_src[] = {
"DAC MIX", "DMIC"
};
static SOC_ENUM_SINGLE_DECL(
rt5665_sto1_adc2l_enum, RT5665_STO1_ADC_MIXER,
RT5665_STO1_ADC2L_SRC_SFT, rt5665_sto1_adc2_src);
static const struct snd_kcontrol_new rt5665_sto1_adc2l_mux =
SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5665_sto1_adc2l_enum);
static SOC_ENUM_SINGLE_DECL(
rt5665_sto1_adc2r_enum, RT5665_STO1_ADC_MIXER,
RT5665_STO1_ADC2R_SRC_SFT, rt5665_sto1_adc2_src);
static const struct snd_kcontrol_new rt5665_sto1_adc2r_mux =
SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5665_sto1_adc2r_enum);
/* STO1 DMIC Source */
/* MX-26 [8] */
static const char * const rt5665_sto1_dmic_src[] = {
"DMIC1", "DMIC2"
};
static SOC_ENUM_SINGLE_DECL(
rt5665_sto1_dmic_enum, RT5665_STO1_ADC_MIXER,
RT5665_STO1_DMIC_SRC_SFT, rt5665_sto1_dmic_src);
static const struct snd_kcontrol_new rt5665_sto1_dmic_mux =
SOC_DAPM_ENUM("Stereo1 DMIC Mux", rt5665_sto1_dmic_enum);
/* MX-26 [9] */
static const char * const rt5665_sto1_dd_l_src[] = {
"STO2 DAC", "MONO DAC"
};
static SOC_ENUM_SINGLE_DECL(
rt5665_sto1_dd_l_enum, RT5665_STO1_ADC_MIXER,
RT5665_STO1_DD_L_SRC_SFT, rt5665_sto1_dd_l_src);
static const struct snd_kcontrol_new rt5665_sto1_dd_l_mux =
SOC_DAPM_ENUM("Stereo1 DD L Source", rt5665_sto1_dd_l_enum);
/* MX-26 [1:0] */
static const char * const rt5665_sto1_dd_r_src[] = {
"STO2 DAC", "MONO DAC", "AEC REF"
};
static SOC_ENUM_SINGLE_DECL(
rt5665_sto1_dd_r_enum, RT5665_STO1_ADC_MIXER,
RT5665_STO1_DD_R_SRC_SFT, rt5665_sto1_dd_r_src);
static const struct snd_kcontrol_new rt5665_sto1_dd_r_mux =
SOC_DAPM_ENUM("Stereo1 DD R Source", rt5665_sto1_dd_r_enum);
/* MONO ADC L2 Source */
/* MX-27 [12] */
static const char * const rt5665_mono_adc_l2_src[] = {
"DAC MIXL", "DMIC"
};
static SOC_ENUM_SINGLE_DECL(
rt5665_mono_adc_l2_enum, RT5665_MONO_ADC_MIXER,
RT5665_MONO_ADC_L2_SRC_SFT, rt5665_mono_adc_l2_src);
static const struct snd_kcontrol_new rt5665_mono_adc_l2_mux =
SOC_DAPM_ENUM("Mono ADC L2 Source", rt5665_mono_adc_l2_enum);
/* MONO ADC L1 Source */
/* MX-27 [13] */
static const char * const rt5665_mono_adc_l1_src[] = {
"DD Mux", "ADC"
};
static SOC_ENUM_SINGLE_DECL(
rt5665_mono_adc_l1_enum, RT5665_MONO_ADC_MIXER,
RT5665_MONO_ADC_L1_SRC_SFT, rt5665_mono_adc_l1_src);
static const struct snd_kcontrol_new rt5665_mono_adc_l1_mux =
SOC_DAPM_ENUM("Mono ADC L1 Source", rt5665_mono_adc_l1_enum);
/* MX-27 [9][1]*/
static const char * const rt5665_mono_dd_src[] = {
"STO2 DAC", "MONO DAC"
};
static SOC_ENUM_SINGLE_DECL(
rt5665_mono_dd_l_enum, RT5665_MONO_ADC_MIXER,
RT5665_MONO_DD_L_SRC_SFT, rt5665_mono_dd_src);
static const struct snd_kcontrol_new rt5665_mono_dd_l_mux =
SOC_DAPM_ENUM("Mono DD L Source", rt5665_mono_dd_l_enum);
static SOC_ENUM_SINGLE_DECL(
rt5665_mono_dd_r_enum, RT5665_MONO_ADC_MIXER,
RT5665_MONO_DD_R_SRC_SFT, rt5665_mono_dd_src);
static const struct snd_kcontrol_new rt5665_mono_dd_r_mux =
SOC_DAPM_ENUM("Mono DD R Source", rt5665_mono_dd_r_enum);
/* MONO ADC L Source, MONO ADC R Source*/
/* MX-27 [11:10], MX-27 [3:2] */
static const char * const rt5665_mono_adc_src[] = {
"ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
};
static SOC_ENUM_SINGLE_DECL(
rt5665_mono_adc_l_enum, RT5665_MONO_ADC_MIXER,
RT5665_MONO_ADC_L_SRC_SFT, rt5665_mono_adc_src);
static const struct snd_kcontrol_new rt5665_mono_adc_l_mux =
SOC_DAPM_ENUM("Mono ADC L Source", rt5665_mono_adc_l_enum);
static SOC_ENUM_SINGLE_DECL(
rt5665_mono_adcr_enum, RT5665_MONO_ADC_MIXER,
RT5665_MONO_ADC_R_SRC_SFT, rt5665_mono_adc_src);
static const struct snd_kcontrol_new rt5665_mono_adc_r_mux =
SOC_DAPM_ENUM("Mono ADC R Source", rt5665_mono_adcr_enum);
/* MONO DMIC L Source */
/* MX-27 [8] */
static const char * const rt5665_mono_dmic_l_src[] = {
"DMIC1 L", "DMIC2 L"
};
static SOC_ENUM_SINGLE_DECL(
rt5665_mono_dmic_l_enum, RT5665_MONO_ADC_MIXER,
RT5665_MONO_DMIC_L_SRC_SFT, rt5665_mono_dmic_l_src);
static const struct snd_kcontrol_new rt5665_mono_dmic_l_mux =
SOC_DAPM_ENUM("Mono DMIC L Source", rt5665_mono_dmic_l_enum);
/* MONO ADC R2 Source */
/* MX-27 [4] */
static const char * const rt5665_mono_adc_r2_src[] = {
"DAC MIXR", "DMIC"
};
static SOC_ENUM_SINGLE_DECL(
rt5665_mono_adc_r2_enum, RT5665_MONO_ADC_MIXER,
RT5665_MONO_ADC_R2_SRC_SFT, rt5665_mono_adc_r2_src);
static const struct snd_kcontrol_new rt5665_mono_adc_r2_mux =
SOC_DAPM_ENUM("Mono ADC R2 Source", rt5665_mono_adc_r2_enum);
/* MONO ADC R1 Source */
/* MX-27 [5] */
static const char * const rt5665_mono_adc_r1_src[] = {
"DD Mux", "ADC"
};
static SOC_ENUM_SINGLE_DECL(
rt5665_mono_adc_r1_enum, RT5665_MONO_ADC_MIXER,
RT5665_MONO_ADC_R1_SRC_SFT, rt5665_mono_adc_r1_src);
static const struct snd_kcontrol_new rt5665_mono_adc_r1_mux =
SOC_DAPM_ENUM("Mono ADC R1 Source", rt5665_mono_adc_r1_enum);
/* MONO DMIC R Source */
/* MX-27 [0] */
static const char * const rt5665_mono_dmic_r_src[] = {
"DMIC1 R", "DMIC2 R"
};
static SOC_ENUM_SINGLE_DECL(
rt5665_mono_dmic_r_enum, RT5665_MONO_ADC_MIXER,
RT5665_MONO_DMIC_R_SRC_SFT, rt5665_mono_dmic_r_src);
static const struct snd_kcontrol_new rt5665_mono_dmic_r_mux =
SOC_DAPM_ENUM("Mono DMIC R Source", rt5665_mono_dmic_r_enum);
/* STO2 ADC1 Source */
/* MX-28 [13] [5] */
static const char * const rt5665_sto2_adc1_src[] = {
"DD Mux", "ADC"
};
static SOC_ENUM_SINGLE_DECL(
rt5665_sto2_adc1l_enum, RT5665_STO2_ADC_MIXER,
RT5665_STO2_ADC1L_SRC_SFT, rt5665_sto2_adc1_src);
static const struct snd_kcontrol_new rt5665_sto2_adc1l_mux =
SOC_DAPM_ENUM("Stereo2 ADC1L Source", rt5665_sto2_adc1l_enum);
static SOC_ENUM_SINGLE_DECL(
rt5665_sto2_adc1r_enum, RT5665_STO2_ADC_MIXER,
RT5665_STO2_ADC1R_SRC_SFT, rt5665_sto2_adc1_src);
static const struct snd_kcontrol_new rt5665_sto2_adc1r_mux =
SOC_DAPM_ENUM("Stereo2 ADC1L Source", rt5665_sto2_adc1r_enum);
/* STO2 ADC Source */
/* MX-28 [11:10] [3:2] */
static const char * const rt5665_sto2_adc_src[] = {
"ADC1 L", "ADC1 R", "ADC2 L"
};
static SOC_ENUM_SINGLE_DECL(
rt5665_sto2_adcl_enum, RT5665_STO2_ADC_MIXER,
RT5665_STO2_ADCL_SRC_SFT, rt5665_sto2_adc_src);
static const struct snd_kcontrol_new rt5665_sto2_adcl_mux =
SOC_DAPM_ENUM("Stereo2 ADCL Source", rt5665_sto2_adcl_enum);
static SOC_ENUM_SINGLE_DECL(
rt5665_sto2_adcr_enum, RT5665_STO2_ADC_MIXER,
RT5665_STO2_ADCR_SRC_SFT, rt5665_sto2_adc_src);
static const struct snd_kcontrol_new rt5665_sto2_adcr_mux =
SOC_DAPM_ENUM("Stereo2 ADCR Source", rt5665_sto2_adcr_enum);
/* STO2 ADC2 Source */
/* MX-28 [12] [4] */
static const char * const rt5665_sto2_adc2_src[] = {
"DAC MIX", "DMIC"
};
static SOC_ENUM_SINGLE_DECL(
rt5665_sto2_adc2l_enum, RT5665_STO2_ADC_MIXER,
RT5665_STO2_ADC2L_SRC_SFT, rt5665_sto2_adc2_src);
static const struct snd_kcontrol_new rt5665_sto2_adc2l_mux =
SOC_DAPM_ENUM("Stereo2 ADC2L Source", rt5665_sto2_adc2l_enum);
static SOC_ENUM_SINGLE_DECL(
rt5665_sto2_adc2r_enum, RT5665_STO2_ADC_MIXER,
RT5665_STO2_ADC2R_SRC_SFT, rt5665_sto2_adc2_src);
static const struct snd_kcontrol_new rt5665_sto2_adc2r_mux =
SOC_DAPM_ENUM("Stereo2 ADC2R Source", rt5665_sto2_adc2r_enum);
/* STO2 DMIC Source */
/* MX-28 [8] */
static const char * const rt5665_sto2_dmic_src[] = {
"DMIC1", "DMIC2"
};
static SOC_ENUM_SINGLE_DECL(
rt5665_sto2_dmic_enum, RT5665_STO2_ADC_MIXER,
RT5665_STO2_DMIC_SRC_SFT, rt5665_sto2_dmic_src);
static const struct snd_kcontrol_new rt5665_sto2_dmic_mux =
SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5665_sto2_dmic_enum);
/* MX-28 [9] */
static const char * const rt5665_sto2_dd_l_src[] = {
"STO2 DAC", "MONO DAC"
};
static SOC_ENUM_SINGLE_DECL(
rt5665_sto2_dd_l_enum, RT5665_STO2_ADC_MIXER,
RT5665_STO2_DD_L_SRC_SFT, rt5665_sto2_dd_l_src);
static const struct snd_kcontrol_new rt5665_sto2_dd_l_mux =
SOC_DAPM_ENUM("Stereo2 DD L Source", rt5665_sto2_dd_l_enum);
/* MX-28 [1] */
static const char * const rt5665_sto2_dd_r_src[] = {
"STO2 DAC", "MONO DAC"
};
static SOC_ENUM_SINGLE_DECL(
rt5665_sto2_dd_r_enum, RT5665_STO2_ADC_MIXER,
RT5665_STO2_DD_R_SRC_SFT, rt5665_sto2_dd_r_src);
static const struct snd_kcontrol_new rt5665_sto2_dd_r_mux =
SOC_DAPM_ENUM("Stereo2 DD R Source", rt5665_sto2_dd_r_enum);
/* DAC R1 Source, DAC L1 Source*/
/* MX-29 [11:10], MX-29 [9:8]*/
static const char * const rt5665_dac1_src[] = {
"IF1 DAC1", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC"
};
static SOC_ENUM_SINGLE_DECL(
rt5665_dac_r1_enum, RT5665_AD_DA_MIXER,
RT5665_DAC1_R_SEL_SFT, rt5665_dac1_src);
static const struct snd_kcontrol_new rt5665_dac_r1_mux =
SOC_DAPM_ENUM("DAC R1 Source", rt5665_dac_r1_enum);
static SOC_ENUM_SINGLE_DECL(
rt5665_dac_l1_enum, RT5665_AD_DA_MIXER,
RT5665_DAC1_L_SEL_SFT, rt5665_dac1_src);
static const struct snd_kcontrol_new rt5665_dac_l1_mux =
SOC_DAPM_ENUM("DAC L1 Source", rt5665_dac_l1_enum);
/* DAC Digital Mixer L Source, DAC Digital Mixer R Source*/
/* MX-2D [13:12], MX-2D [9:8]*/
static const char * const rt5665_dig_dac_mix_src[] = {
"Stereo1 DAC Mixer", "Stereo2 DAC Mixer", "Mono DAC Mixer"
};
static SOC_ENUM_SINGLE_DECL(
rt5665_dig_dac_mixl_enum, RT5665_A_DAC1_MUX,
RT5665_DAC_MIX_L_SFT, rt5665_dig_dac_mix_src);
static const struct snd_kcontrol_new rt5665_dig_dac_mixl_mux =
SOC_DAPM_ENUM("DAC Digital Mixer L Source", rt5665_dig_dac_mixl_enum);
static SOC_ENUM_SINGLE_DECL(
rt5665_dig_dac_mixr_enum, RT5665_A_DAC1_MUX,
RT5665_DAC_MIX_R_SFT, rt5665_dig_dac_mix_src);
static const struct snd_kcontrol_new rt5665_dig_dac_mixr_mux =
SOC_DAPM_ENUM("DAC Digital Mixer R Source", rt5665_dig_dac_mixr_enum);
/* Analog DAC L1 Source, Analog DAC R1 Source*/
/* MX-2D [5:4], MX-2D [1:0]*/
static const char * const rt5665_alg_dac1_src[] = {
"Stereo1 DAC Mixer", "DAC1", "DMIC1"
};
static SOC_ENUM_SINGLE_DECL(
rt5665_alg_dac_l1_enum, RT5665_A_DAC1_MUX,
RT5665_A_DACL1_SFT, rt5665_alg_dac1_src);
static const struct snd_kcontrol_new rt5665_alg_dac_l1_mux =
SOC_DAPM_ENUM("Analog DAC L1 Source", rt5665_alg_dac_l1_enum);
static SOC_ENUM_SINGLE_DECL(
rt5665_alg_dac_r1_enum, RT5665_A_DAC1_MUX,
RT5665_A_DACR1_SFT, rt5665_alg_dac1_src);
static const struct snd_kcontrol_new rt5665_alg_dac_r1_mux =
SOC_DAPM_ENUM("Analog DAC R1 Source", rt5665_alg_dac_r1_enum);
/* Analog DAC LR Source, Analog DAC R2 Source*/
/* MX-2E [5:4], MX-2E [0]*/
static const char * const rt5665_alg_dac2_src[] = {
"Mono DAC Mixer", "DAC2"
};
static SOC_ENUM_SINGLE_DECL(
rt5665_alg_dac_l2_enum, RT5665_A_DAC2_MUX,
RT5665_A_DACL2_SFT, rt5665_alg_dac2_src);
static const struct snd_kcontrol_new rt5665_alg_dac_l2_mux =
SOC_DAPM_ENUM("Analog DAC L2 Source", rt5665_alg_dac_l2_enum);
static SOC_ENUM_SINGLE_DECL(
rt5665_alg_dac_r2_enum, RT5665_A_DAC2_MUX,
RT5665_A_DACR2_SFT, rt5665_alg_dac2_src);
static const struct snd_kcontrol_new rt5665_alg_dac_r2_mux =
SOC_DAPM_ENUM("Analog DAC R2 Source", rt5665_alg_dac_r2_enum);
/* Interface2 ADC Data Input*/
/* MX-2F [14:12] */
static const char * const rt5665_if2_1_adc_in_src[] = {
"STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
"IF1 DAC2", "IF2_2 DAC", "IF3 DAC", "DAC1 MIX"
};
static SOC_ENUM_SINGLE_DECL(
rt5665_if2_1_adc_in_enum, RT5665_DIG_INF2_DATA,
RT5665_IF2_1_ADC_IN_SFT, rt5665_if2_1_adc_in_src);
static const struct snd_kcontrol_new rt5665_if2_1_adc_in_mux =
SOC_DAPM_ENUM("IF2_1 ADC IN Source", rt5665_if2_1_adc_in_enum);
/* MX-2F [6:4] */
static const char * const rt5665_if2_2_adc_in_src[] = {
"STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
"IF1 DAC2", "IF2_1 DAC", "IF3 DAC", "DAC1 MIX"
};
static SOC_ENUM_SINGLE_DECL(
rt5665_if2_2_adc_in_enum, RT5665_DIG_INF2_DATA,
RT5665_IF2_2_ADC_IN_SFT, rt5665_if2_2_adc_in_src);
static const struct snd_kcontrol_new rt5665_if2_2_adc_in_mux =
SOC_DAPM_ENUM("IF2_1 ADC IN Source", rt5665_if2_2_adc_in_enum);
/* Interface3 ADC Data Input*/
/* MX-30 [6:4] */
static const char * const rt5665_if3_adc_in_src[] = {
"STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
"IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "DAC1 MIX"
};
static SOC_ENUM_SINGLE_DECL(
rt5665_if3_adc_in_enum, RT5665_DIG_INF3_DATA,
RT5665_IF3_ADC_IN_SFT, rt5665_if3_adc_in_src);
static const struct snd_kcontrol_new rt5665_if3_adc_in_mux =
SOC_DAPM_ENUM("IF3 ADC IN Source", rt5665_if3_adc_in_enum);
/* PDM 1 L/R*/
/* MX-31 [11:10] [9:8] */
static const char * const rt5665_pdm_src[] = {
"Stereo1 DAC", "Stereo2 DAC", "Mono DAC"
};
static SOC_ENUM_SINGLE_DECL(
rt5665_pdm_l_enum, RT5665_PDM_OUT_CTRL,
RT5665_PDM1_L_SFT, rt5665_pdm_src);
static const struct snd_kcontrol_new rt5665_pdm_l_mux =
SOC_DAPM_ENUM("PDM L Source", rt5665_pdm_l_enum);
static SOC_ENUM_SINGLE_DECL(
rt5665_pdm_r_enum, RT5665_PDM_OUT_CTRL,
RT5665_PDM1_R_SFT, rt5665_pdm_src);
static const struct snd_kcontrol_new rt5665_pdm_r_mux =
SOC_DAPM_ENUM("PDM R Source", rt5665_pdm_r_enum);
/* I2S1 TDM ADCDAT Source */
/* MX-7a[10] */
static const char * const rt5665_if1_1_adc1_data_src[] = {
"STO1 ADC", "IF2_1 DAC",
};
static SOC_ENUM_SINGLE_DECL(
rt5665_if1_1_adc1_data_enum, RT5665_TDM_CTRL_3,
RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_1_adc1_data_src);
static const struct snd_kcontrol_new rt5665_if1_1_adc1_mux =
SOC_DAPM_ENUM("IF1_1 ADC1 Source", rt5665_if1_1_adc1_data_enum);
/* MX-7a[9] */
static const char * const rt5665_if1_1_adc2_data_src[] = {
"STO2 ADC", "IF2_2 DAC",
};
static SOC_ENUM_SINGLE_DECL(
rt5665_if1_1_adc2_data_enum, RT5665_TDM_CTRL_3,
RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_1_adc2_data_src);
static const struct snd_kcontrol_new rt5665_if1_1_adc2_mux =
SOC_DAPM_ENUM("IF1_1 ADC2 Source", rt5665_if1_1_adc2_data_enum);
/* MX-7a[8] */
static const char * const rt5665_if1_1_adc3_data_src[] = {
"MONO ADC", "IF3 DAC",
};
static SOC_ENUM_SINGLE_DECL(
rt5665_if1_1_adc3_data_enum, RT5665_TDM_CTRL_3,
RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_1_adc3_data_src);
static const struct snd_kcontrol_new rt5665_if1_1_adc3_mux =
SOC_DAPM_ENUM("IF1_1 ADC3 Source", rt5665_if1_1_adc3_data_enum);
/* MX-7b[10] */
static const char * const rt5665_if1_2_adc1_data_src[] = {
"STO1 ADC", "IF1 DAC",
};
static SOC_ENUM_SINGLE_DECL(
rt5665_if1_2_adc1_data_enum, RT5665_TDM_CTRL_4,
RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_2_adc1_data_src);
static const struct snd_kcontrol_new rt5665_if1_2_adc1_mux =
SOC_DAPM_ENUM("IF1_2 ADC1 Source", rt5665_if1_2_adc1_data_enum);
/* MX-7b[9] */
static const char * const rt5665_if1_2_adc2_data_src[] = {
"STO2 ADC", "IF2_1 DAC",
};
static SOC_ENUM_SINGLE_DECL(
rt5665_if1_2_adc2_data_enum, RT5665_TDM_CTRL_4,
RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_2_adc2_data_src);
static const struct snd_kcontrol_new rt5665_if1_2_adc2_mux =
SOC_DAPM_ENUM("IF1_2 ADC2 Source", rt5665_if1_2_adc2_data_enum);
/* MX-7b[8] */
static const char * const rt5665_if1_2_adc3_data_src[] = {
"MONO ADC", "IF2_2 DAC",
};
static SOC_ENUM_SINGLE_DECL(
rt5665_if1_2_adc3_data_enum, RT5665_TDM_CTRL_4,
RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_2_adc3_data_src);
static const struct snd_kcontrol_new rt5665_if1_2_adc3_mux =
SOC_DAPM_ENUM("IF1_2 ADC3 Source", rt5665_if1_2_adc3_data_enum);
/* MX-7b[7] */
static const char * const rt5665_if1_2_adc4_data_src[] = {
"DAC1", "IF3 DAC",
};
static SOC_ENUM_SINGLE_DECL(
rt5665_if1_2_adc4_data_enum, RT5665_TDM_CTRL_4,
RT5665_IF1_ADC4_SEL_SFT, rt5665_if1_2_adc4_data_src);
static const struct snd_kcontrol_new rt5665_if1_2_adc4_mux =
SOC_DAPM_ENUM("IF1_2 ADC4 Source", rt5665_if1_2_adc4_data_enum);
/* MX-7a[4:0] MX-7b[4:0] */
static const char * const rt5665_tdm_adc_data_src[] = {
"1234", "1243", "1324", "1342", "1432", "1423",
"2134", "2143", "2314", "2341", "2431", "2413",
"3124", "3142", "3214", "3241", "3412", "3421",
"4123", "4132", "4213", "4231", "4312", "4321"
};
static SOC_ENUM_SINGLE_DECL(
rt5665_tdm1_adc_data_enum, RT5665_TDM_CTRL_3,
RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src);
static const struct snd_kcontrol_new rt5665_tdm1_adc_mux =
SOC_DAPM_ENUM("TDM1 ADC Mux", rt5665_tdm1_adc_data_enum);
static SOC_ENUM_SINGLE_DECL(
rt5665_tdm2_adc_data_enum, RT5665_TDM_CTRL_4,
RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src);
static const struct snd_kcontrol_new rt5665_tdm2_adc_mux =
SOC_DAPM_ENUM("TDM2 ADCDAT Source", rt5665_tdm2_adc_data_enum);
/* Out Volume Switch */
static const struct snd_kcontrol_new monovol_switch =
SOC_DAPM_SINGLE("Switch", RT5665_MONO_OUT, RT5665_VOL_L_SFT, 1, 1);
static const struct snd_kcontrol_new outvol_l_switch =
SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_VOL_L_SFT, 1, 1);
static const struct snd_kcontrol_new outvol_r_switch =
SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_VOL_R_SFT, 1, 1);
/* Out Switch */
static const struct snd_kcontrol_new mono_switch =
SOC_DAPM_SINGLE("Switch", RT5665_MONO_OUT, RT5665_L_MUTE_SFT, 1, 1);
static const struct snd_kcontrol_new hpo_switch =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5665_HP_CTRL_2,
RT5665_VOL_L_SFT, 1, 0);
static const struct snd_kcontrol_new lout_l_switch =
SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_L_MUTE_SFT, 1, 1);
static const struct snd_kcontrol_new lout_r_switch =
SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_R_MUTE_SFT, 1, 1);
static const struct snd_kcontrol_new pdm_l_switch =
SOC_DAPM_SINGLE("Switch", RT5665_PDM_OUT_CTRL,
RT5665_M_PDM1_L_SFT, 1, 1);
static const struct snd_kcontrol_new pdm_r_switch =
SOC_DAPM_SINGLE("Switch", RT5665_PDM_OUT_CTRL,
RT5665_M_PDM1_R_SFT, 1, 1);
static int rt5665_mono_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_component_update_bits(component, RT5665_MONO_NG2_CTRL_1,
RT5665_NG2_EN_MASK, RT5665_NG2_EN);
snd_soc_component_update_bits(component, RT5665_MONO_AMP_CALIB_CTRL_1, 0x40,
0x0);
snd_soc_component_update_bits(component, RT5665_MONO_OUT, 0x10, 0x10);
snd_soc_component_update_bits(component, RT5665_MONO_OUT, 0x20, 0x20);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component, RT5665_MONO_OUT, 0x20, 0);
snd_soc_component_update_bits(component, RT5665_MONO_OUT, 0x10, 0);
snd_soc_component_update_bits(component, RT5665_MONO_AMP_CALIB_CTRL_1, 0x40,
0x40);
snd_soc_component_update_bits(component, RT5665_MONO_NG2_CTRL_1,
RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
break;
default:
return 0;
}
return 0;
}
static int rt5665_hp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_component_update_bits(component, RT5665_STO_NG2_CTRL_1,
RT5665_NG2_EN_MASK, RT5665_NG2_EN);
snd_soc_component_write(component, RT5665_HP_LOGIC_CTRL_2, 0x0003);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_write(component, RT5665_HP_LOGIC_CTRL_2, 0x0002);
snd_soc_component_update_bits(component, RT5665_STO_NG2_CTRL_1,
RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
break;
default:
return 0;
}
return 0;
}
static int rt5665_lout_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(component, RT5665_DEPOP_1,
RT5665_PUMP_EN, RT5665_PUMP_EN);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, RT5665_DEPOP_1,
RT5665_PUMP_EN, 0);
break;
default:
return 0;
}
return 0;
}
static int set_dmic_power(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
switch (event) {
case SND_SOC_DAPM_POST_PMU:
/*Add delay to avoid pop noise*/
msleep(150);
break;
default:
return 0;
}
return 0;
}
static int rt5665_set_verf(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
switch (w->shift) {
case RT5665_PWR_VREF1_BIT:
snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1,
RT5665_PWR_FV1, 0);
break;
case RT5665_PWR_VREF2_BIT:
snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1,
RT5665_PWR_FV2, 0);
break;
case RT5665_PWR_VREF3_BIT:
snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1,
RT5665_PWR_FV3, 0);
break;
default:
break;
}
break;
case SND_SOC_DAPM_POST_PMU:
usleep_range(15000, 20000);
switch (w->shift) {
case RT5665_PWR_VREF1_BIT:
snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1,
RT5665_PWR_FV1, RT5665_PWR_FV1);
break;
case RT5665_PWR_VREF2_BIT:
snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1,
RT5665_PWR_FV2, RT5665_PWR_FV2);
break;
case RT5665_PWR_VREF3_BIT:
snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1,
RT5665_PWR_FV3, RT5665_PWR_FV3);
break;
default:
break;
}
break;
default:
return 0;
}
return 0;
}
static int rt5665_i2s_pin_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
unsigned int val1, val2, mask1 = 0, mask2 = 0;
switch (w->shift) {
case RT5665_PWR_I2S2_1_BIT:
mask1 = RT5665_GP2_PIN_MASK | RT5665_GP3_PIN_MASK |
RT5665_GP4_PIN_MASK | RT5665_GP5_PIN_MASK;
val1 = RT5665_GP2_PIN_BCLK2 | RT5665_GP3_PIN_LRCK2 |
RT5665_GP4_PIN_DACDAT2_1 | RT5665_GP5_PIN_ADCDAT2_1;
break;
case RT5665_PWR_I2S2_2_BIT:
mask1 = RT5665_GP2_PIN_MASK | RT5665_GP3_PIN_MASK |
RT5665_GP8_PIN_MASK;
val1 = RT5665_GP2_PIN_BCLK2 | RT5665_GP3_PIN_LRCK2 |
RT5665_GP8_PIN_DACDAT2_2;
mask2 = RT5665_GP9_PIN_MASK;
val2 = RT5665_GP9_PIN_ADCDAT2_2;
break;
case RT5665_PWR_I2S3_BIT:
mask1 = RT5665_GP6_PIN_MASK | RT5665_GP7_PIN_MASK |
RT5665_GP8_PIN_MASK;
val1 = RT5665_GP6_PIN_BCLK3 | RT5665_GP7_PIN_LRCK3 |
RT5665_GP8_PIN_DACDAT3;
mask2 = RT5665_GP9_PIN_MASK;
val2 = RT5665_GP9_PIN_ADCDAT3;
break;
}
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
if (mask1)
snd_soc_component_update_bits(component, RT5665_GPIO_CTRL_1,
mask1, val1);
if (mask2)
snd_soc_component_update_bits(component, RT5665_GPIO_CTRL_2,
mask2, val2);
break;
case SND_SOC_DAPM_POST_PMD:
if (mask1)
snd_soc_component_update_bits(component, RT5665_GPIO_CTRL_1,
mask1, 0);
if (mask2)
snd_soc_component_update_bits(component, RT5665_GPIO_CTRL_2,
mask2, 0);
break;
default:
return 0;
}
return 0;
}
static const struct snd_soc_dapm_widget rt5665_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("LDO2", RT5665_PWR_ANLG_3, RT5665_PWR_LDO2_BIT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("PLL", RT5665_PWR_ANLG_3, RT5665_PWR_PLL_BIT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5665_PWR_VOL,
RT5665_PWR_MIC_DET_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Vref1", RT5665_PWR_ANLG_1, RT5665_PWR_VREF1_BIT, 0,
rt5665_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY("Vref2", RT5665_PWR_ANLG_1, RT5665_PWR_VREF2_BIT, 0,
rt5665_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY("Vref3", RT5665_PWR_ANLG_1, RT5665_PWR_VREF3_BIT, 0,
rt5665_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
/* ASRC */
SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5665_ASRC_1,
RT5665_I2S1_ASRC_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5665_ASRC_1,
RT5665_I2S2_ASRC_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5665_ASRC_1,
RT5665_I2S3_ASRC_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5665_ASRC_1,
RT5665_DAC_STO1_ASRC_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DAC STO2 ASRC", 1, RT5665_ASRC_1,
RT5665_DAC_STO2_ASRC_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DAC Mono L ASRC", 1, RT5665_ASRC_1,
RT5665_DAC_MONO_L_ASRC_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DAC Mono R ASRC", 1, RT5665_ASRC_1,
RT5665_DAC_MONO_R_ASRC_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5665_ASRC_1,
RT5665_ADC_STO1_ASRC_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5665_ASRC_1,
RT5665_ADC_STO2_ASRC_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADC Mono L ASRC", 1, RT5665_ASRC_1,
RT5665_ADC_MONO_L_ASRC_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADC Mono R ASRC", 1, RT5665_ASRC_1,
RT5665_ADC_MONO_R_ASRC_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5665_ASRC_1,
RT5665_DMIC_STO1_ASRC_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5665_ASRC_1,
RT5665_DMIC_STO2_ASRC_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5665_ASRC_1,
RT5665_DMIC_MONO_L_ASRC_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5665_ASRC_1,
RT5665_DMIC_MONO_R_ASRC_SFT, 0, NULL, 0),
/* Input Side */
SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5665_PWR_ANLG_2, RT5665_PWR_MB1_BIT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5665_PWR_ANLG_2, RT5665_PWR_MB2_BIT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS3", RT5665_PWR_ANLG_2, RT5665_PWR_MB3_BIT,
0, NULL, 0),
/* Input Lines */
SND_SOC_DAPM_INPUT("DMIC L1"),
SND_SOC_DAPM_INPUT("DMIC R1"),
SND_SOC_DAPM_INPUT("DMIC L2"),
SND_SOC_DAPM_INPUT("DMIC R2"),
SND_SOC_DAPM_INPUT("IN1P"),
SND_SOC_DAPM_INPUT("IN1N"),
SND_SOC_DAPM_INPUT("IN2P"),
SND_SOC_DAPM_INPUT("IN2N"),
SND_SOC_DAPM_INPUT("IN3P"),
SND_SOC_DAPM_INPUT("IN3N"),
SND_SOC_DAPM_INPUT("IN4P"),
SND_SOC_DAPM_INPUT("IN4N"),
SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5665_DMIC_CTRL_1,
RT5665_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5665_DMIC_CTRL_1,
RT5665_DMIC_2_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
/* Boost */
SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM,
0, 0, NULL, 0),
SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM,
0, 0, NULL, 0),
SND_SOC_DAPM_PGA("BST3", SND_SOC_NOPM,
0, 0, NULL, 0),
SND_SOC_DAPM_PGA("BST4", SND_SOC_NOPM,
0, 0, NULL, 0),
SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("BST1 Power", RT5665_PWR_ANLG_2,
RT5665_PWR_BST1_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("BST2 Power", RT5665_PWR_ANLG_2,
RT5665_PWR_BST2_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("BST3 Power", RT5665_PWR_ANLG_2,
RT5665_PWR_BST3_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("BST4 Power", RT5665_PWR_ANLG_2,
RT5665_PWR_BST4_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("BST1P Power", RT5665_PWR_ANLG_2,
RT5665_PWR_BST1_P_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("BST2P Power", RT5665_PWR_ANLG_2,
RT5665_PWR_BST2_P_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("BST3P Power", RT5665_PWR_ANLG_2,
RT5665_PWR_BST3_P_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("BST4P Power", RT5665_PWR_ANLG_2,
RT5665_PWR_BST4_P_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CBJ Power", RT5665_PWR_ANLG_3,
RT5665_PWR_CBJ_BIT, 0, NULL, 0),
/* Input Volume */
SND_SOC_DAPM_PGA("INL VOL", RT5665_PWR_VOL, RT5665_PWR_IN_L_BIT,
0, NULL, 0),
SND_SOC_DAPM_PGA("INR VOL", RT5665_PWR_VOL, RT5665_PWR_IN_R_BIT,
0, NULL, 0),
/* REC Mixer */
SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5665_rec1_l_mix,
ARRAY_SIZE(rt5665_rec1_l_mix)),
SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5665_rec1_r_mix,
ARRAY_SIZE(rt5665_rec1_r_mix)),
SND_SOC_DAPM_MIXER("RECMIX2L", SND_SOC_NOPM, 0, 0, rt5665_rec2_l_mix,
ARRAY_SIZE(rt5665_rec2_l_mix)),
SND_SOC_DAPM_MIXER("RECMIX2R", SND_SOC_NOPM, 0, 0, rt5665_rec2_r_mix,
ARRAY_SIZE(rt5665_rec2_r_mix)),
SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5665_PWR_ANLG_2,
RT5665_PWR_RM1_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5665_PWR_ANLG_2,
RT5665_PWR_RM1_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("RECMIX2L Power", RT5665_PWR_MIXER,
RT5665_PWR_RM2_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("RECMIX2R Power", RT5665_PWR_MIXER,
RT5665_PWR_RM2_R_BIT, 0, NULL, 0),
/* ADCs */
SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("ADC2 L", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("ADC2 R", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5665_PWR_DIG_1,
RT5665_PWR_ADC_L1_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5665_PWR_DIG_1,
RT5665_PWR_ADC_R1_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC2 L Power", RT5665_PWR_DIG_1,
RT5665_PWR_ADC_L2_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC2 R Power", RT5665_PWR_DIG_1,
RT5665_PWR_ADC_R2_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5665_CHOP_ADC,
RT5665_CKGEN_ADC1_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5665_CHOP_ADC,
RT5665_CKGEN_ADC2_SFT, 0, NULL, 0),
/* ADC Mux */
SND_SOC_DAPM_MUX("Stereo1 DMIC L Mux", SND_SOC_NOPM, 0, 0,
&rt5665_sto1_dmic_mux),
SND_SOC_DAPM_MUX("Stereo1 DMIC R Mux", SND_SOC_NOPM, 0, 0,
&rt5665_sto1_dmic_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
&rt5665_sto1_adc1l_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
&rt5665_sto1_adc1r_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
&rt5665_sto1_adc2l_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
&rt5665_sto1_adc2r_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
&rt5665_sto1_adcl_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
&rt5665_sto1_adcr_mux),
SND_SOC_DAPM_MUX("Stereo1 DD L Mux", SND_SOC_NOPM, 0, 0,
&rt5665_sto1_dd_l_mux),
SND_SOC_DAPM_MUX("Stereo1 DD R Mux", SND_SOC_NOPM, 0, 0,
&rt5665_sto1_dd_r_mux),
SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
&rt5665_mono_adc_l2_mux),
SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
&rt5665_mono_adc_r2_mux),
SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
&rt5665_mono_adc_l1_mux),
SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
&rt5665_mono_adc_r1_mux),
SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
&rt5665_mono_dmic_l_mux),
SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
&rt5665_mono_dmic_r_mux),
SND_SOC_DAPM_MUX("Mono ADC L Mux", SND_SOC_NOPM, 0, 0,
&rt5665_mono_adc_l_mux),
SND_SOC_DAPM_MUX("Mono ADC R Mux", SND_SOC_NOPM, 0, 0,
&rt5665_mono_adc_r_mux),
SND_SOC_DAPM_MUX("Mono DD L Mux", SND_SOC_NOPM, 0, 0,
&rt5665_mono_dd_l_mux),
SND_SOC_DAPM_MUX("Mono DD R Mux", SND_SOC_NOPM, 0, 0,
&rt5665_mono_dd_r_mux),
SND_SOC_DAPM_MUX("Stereo2 DMIC L Mux", SND_SOC_NOPM, 0, 0,
&rt5665_sto2_dmic_mux),
SND_SOC_DAPM_MUX("Stereo2 DMIC R Mux", SND_SOC_NOPM, 0, 0,
&rt5665_sto2_dmic_mux),
SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
&rt5665_sto2_adc1l_mux),
SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
&rt5665_sto2_adc1r_mux),
SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
&rt5665_sto2_adc2l_mux),
SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
&rt5665_sto2_adc2r_mux),
SND_SOC_DAPM_MUX("Stereo2 ADC L Mux", SND_SOC_NOPM, 0, 0,
&rt5665_sto2_adcl_mux),
SND_SOC_DAPM_MUX("Stereo2 ADC R Mux", SND_SOC_NOPM, 0, 0,
&rt5665_sto2_adcr_mux),
SND_SOC_DAPM_MUX("Stereo2 DD L Mux", SND_SOC_NOPM, 0, 0,
&rt5665_sto2_dd_l_mux),
SND_SOC_DAPM_MUX("Stereo2 DD R Mux", SND_SOC_NOPM, 0, 0,
&rt5665_sto2_dd_r_mux),
/* ADC Mixer */
SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5665_PWR_DIG_2,
RT5665_PWR_ADC_S1F_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC Stereo2 Filter", RT5665_PWR_DIG_2,
RT5665_PWR_ADC_S2F_BIT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5665_STO1_ADC_DIG_VOL,
RT5665_L_MUTE_SFT, 1, rt5665_sto1_adc_l_mix,
ARRAY_SIZE(rt5665_sto1_adc_l_mix)),
SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5665_STO1_ADC_DIG_VOL,
RT5665_R_MUTE_SFT, 1, rt5665_sto1_adc_r_mix,
ARRAY_SIZE(rt5665_sto1_adc_r_mix)),
SND_SOC_DAPM_MIXER("Stereo2 ADC MIXL", RT5665_STO2_ADC_DIG_VOL,
RT5665_L_MUTE_SFT, 1, rt5665_sto2_adc_l_mix,
ARRAY_SIZE(rt5665_sto2_adc_l_mix)),
SND_SOC_DAPM_MIXER("Stereo2 ADC MIXR", RT5665_STO2_ADC_DIG_VOL,
RT5665_R_MUTE_SFT, 1, rt5665_sto2_adc_r_mix,
ARRAY_SIZE(rt5665_sto2_adc_r_mix)),
SND_SOC_DAPM_SUPPLY("ADC Mono Left Filter", RT5665_PWR_DIG_2,
RT5665_PWR_ADC_MF_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Mono ADC MIXL", RT5665_MONO_ADC_DIG_VOL,
RT5665_L_MUTE_SFT, 1, rt5665_mono_adc_l_mix,
ARRAY_SIZE(rt5665_mono_adc_l_mix)),
SND_SOC_DAPM_SUPPLY("ADC Mono Right Filter", RT5665_PWR_DIG_2,
RT5665_PWR_ADC_MF_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Mono ADC MIXR", RT5665_MONO_ADC_DIG_VOL,
RT5665_R_MUTE_SFT, 1, rt5665_mono_adc_r_mix,
ARRAY_SIZE(rt5665_mono_adc_r_mix)),
/* ADC PGA */
SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
/* Digital Interface */
SND_SOC_DAPM_SUPPLY("I2S1_1", RT5665_PWR_DIG_1, RT5665_PWR_I2S1_1_BIT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY("I2S1_2", RT5665_PWR_DIG_1, RT5665_PWR_I2S1_2_BIT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY("I2S2_1", RT5665_PWR_DIG_1, RT5665_PWR_I2S2_1_BIT,
0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("I2S2_2", RT5665_PWR_DIG_1, RT5665_PWR_I2S2_2_BIT,
0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("I2S3", RT5665_PWR_DIG_1, RT5665_PWR_I2S3_BIT,
0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC3 L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC3 R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2_1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2_2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2_1 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2_1 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2_2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2_2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2_1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2_2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
/* Digital Interface Select */
SND_SOC_DAPM_MUX("IF1_1_ADC1 Mux", SND_SOC_NOPM, 0, 0,
&rt5665_if1_1_adc1_mux),
SND_SOC_DAPM_MUX("IF1_1_ADC2 Mux", SND_SOC_NOPM, 0, 0,
&rt5665_if1_1_adc2_mux),
SND_SOC_DAPM_MUX("IF1_1_ADC3 Mux", SND_SOC_NOPM, 0, 0,
&rt5665_if1_1_adc3_mux),
SND_SOC_DAPM_PGA("IF1_1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX("IF1_2_ADC1 Mux", SND_SOC_NOPM, 0, 0,
&rt5665_if1_2_adc1_mux),
SND_SOC_DAPM_MUX("IF1_2_ADC2 Mux", SND_SOC_NOPM, 0, 0,
&rt5665_if1_2_adc2_mux),
SND_SOC_DAPM_MUX("IF1_2_ADC3 Mux", SND_SOC_NOPM, 0, 0,
&rt5665_if1_2_adc3_mux),
SND_SOC_DAPM_MUX("IF1_2_ADC4 Mux", SND_SOC_NOPM, 0, 0,
&rt5665_if1_2_adc4_mux),
SND_SOC_DAPM_MUX("TDM1 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
&rt5665_tdm1_adc_mux),
SND_SOC_DAPM_MUX("TDM1 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
&rt5665_tdm1_adc_mux),
SND_SOC_DAPM_MUX("TDM1 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
&rt5665_tdm1_adc_mux),
SND_SOC_DAPM_MUX("TDM1 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
&rt5665_tdm1_adc_mux),
SND_SOC_DAPM_MUX("TDM2 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
&rt5665_tdm2_adc_mux),
SND_SOC_DAPM_MUX("TDM2 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
&rt5665_tdm2_adc_mux),
SND_SOC_DAPM_MUX("TDM2 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
&rt5665_tdm2_adc_mux),
SND_SOC_DAPM_MUX("TDM2 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
&rt5665_tdm2_adc_mux),
SND_SOC_DAPM_MUX("IF2_1 ADC Mux", SND_SOC_NOPM, 0, 0,
&rt5665_if2_1_adc_in_mux),
SND_SOC_DAPM_MUX("IF2_2 ADC Mux", SND_SOC_NOPM, 0, 0,
&rt5665_if2_2_adc_in_mux),
SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
&rt5665_if3_adc_in_mux),
SND_SOC_DAPM_MUX("IF1_1 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5665_if1_1_01_adc_swap_mux),
SND_SOC_DAPM_MUX("IF1_1 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5665_if1_1_01_adc_swap_mux),
SND_SOC_DAPM_MUX("IF1_1 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5665_if1_1_23_adc_swap_mux),
SND_SOC_DAPM_MUX("IF1_1 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5665_if1_1_23_adc_swap_mux),
SND_SOC_DAPM_MUX("IF1_1 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5665_if1_1_45_adc_swap_mux),
SND_SOC_DAPM_MUX("IF1_1 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5665_if1_1_45_adc_swap_mux),
SND_SOC_DAPM_MUX("IF1_1 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5665_if1_1_67_adc_swap_mux),
SND_SOC_DAPM_MUX("IF1_1 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5665_if1_1_67_adc_swap_mux),
SND_SOC_DAPM_MUX("IF1_2 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5665_if1_2_01_adc_swap_mux),
SND_SOC_DAPM_MUX("IF1_2 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5665_if1_2_01_adc_swap_mux),
SND_SOC_DAPM_MUX("IF1_2 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5665_if1_2_23_adc_swap_mux),
SND_SOC_DAPM_MUX("IF1_2 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5665_if1_2_23_adc_swap_mux),
SND_SOC_DAPM_MUX("IF1_2 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5665_if1_2_45_adc_swap_mux),
SND_SOC_DAPM_MUX("IF1_2 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5665_if1_2_45_adc_swap_mux),
SND_SOC_DAPM_MUX("IF1_2 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5665_if1_2_67_adc_swap_mux),
SND_SOC_DAPM_MUX("IF1_2 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5665_if1_2_67_adc_swap_mux),
SND_SOC_DAPM_MUX("IF2_1 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5665_if2_1_dac_swap_mux),
SND_SOC_DAPM_MUX("IF2_1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5665_if2_1_adc_swap_mux),
SND_SOC_DAPM_MUX("IF2_2 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5665_if2_2_dac_swap_mux),
SND_SOC_DAPM_MUX("IF2_2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5665_if2_2_adc_swap_mux),
SND_SOC_DAPM_MUX("IF3 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5665_if3_dac_swap_mux),
SND_SOC_DAPM_MUX("IF3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5665_if3_adc_swap_mux),
/* Audio Interface */
SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 0", "AIF1_1 Capture",
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 1", "AIF1_1 Capture",
1, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 2", "AIF1_1 Capture",
2, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 3", "AIF1_1 Capture",
3, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 4", "AIF1_1 Capture",
4, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 5", "AIF1_1 Capture",
5, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 6", "AIF1_1 Capture",
6, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 7", "AIF1_1 Capture",
7, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 0", "AIF1_2 Capture",
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 1", "AIF1_2 Capture",
1, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 2", "AIF1_2 Capture",
2, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 3", "AIF1_2 Capture",
3, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 4", "AIF1_2 Capture",
4, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 5", "AIF1_2 Capture",
5, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 6", "AIF1_2 Capture",
6, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 7", "AIF1_2 Capture",
7, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF2_1TX", "AIF2_1 Capture",
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF2_2TX", "AIF2_2 Capture",
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture",
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback",
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIF2_1RX", "AIF2_1 Playback",
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIF2_2RX", "AIF2_2 Playback",
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback",
0, SND_SOC_NOPM, 0, 0),
/* Output Side */
/* DAC mixer before sound effect */
SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
rt5665_dac_l_mix, ARRAY_SIZE(rt5665_dac_l_mix)),
SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
rt5665_dac_r_mix, ARRAY_SIZE(rt5665_dac_r_mix)),
/* DAC channel Mux */
SND_SOC_DAPM_MUX("DAC L1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l1_mux),
SND_SOC_DAPM_MUX("DAC R1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r1_mux),
SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l2_mux),
SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r2_mux),
SND_SOC_DAPM_MUX("DAC L3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l3_mux),
SND_SOC_DAPM_MUX("DAC R3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r3_mux),
SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
&rt5665_alg_dac_l1_mux),
SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
&rt5665_alg_dac_r1_mux),
SND_SOC_DAPM_MUX("DAC L2 Source", SND_SOC_NOPM, 0, 0,
&rt5665_alg_dac_l2_mux),
SND_SOC_DAPM_MUX("DAC R2 Source", SND_SOC_NOPM, 0, 0,
&rt5665_alg_dac_r2_mux),
/* DAC Mixer */
SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5665_PWR_DIG_2,
RT5665_PWR_DAC_S1F_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC Stereo2 Filter", RT5665_PWR_DIG_2,
RT5665_PWR_DAC_S2F_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC Mono Left Filter", RT5665_PWR_DIG_2,
RT5665_PWR_DAC_MF_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC Mono Right Filter", RT5665_PWR_DIG_2,
RT5665_PWR_DAC_MF_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
rt5665_sto1_dac_l_mix, ARRAY_SIZE(rt5665_sto1_dac_l_mix)),
SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
rt5665_sto1_dac_r_mix, ARRAY_SIZE(rt5665_sto1_dac_r_mix)),
SND_SOC_DAPM_MIXER("Stereo2 DAC MIXL", SND_SOC_NOPM, 0, 0,
rt5665_sto2_dac_l_mix, ARRAY_SIZE(rt5665_sto2_dac_l_mix)),
SND_SOC_DAPM_MIXER("Stereo2 DAC MIXR", SND_SOC_NOPM, 0, 0,
rt5665_sto2_dac_r_mix, ARRAY_SIZE(rt5665_sto2_dac_r_mix)),
SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
rt5665_mono_dac_l_mix, ARRAY_SIZE(rt5665_mono_dac_l_mix)),
SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
rt5665_mono_dac_r_mix, ARRAY_SIZE(rt5665_mono_dac_r_mix)),
SND_SOC_DAPM_MUX("DAC MIXL", SND_SOC_NOPM, 0, 0,
&rt5665_dig_dac_mixl_mux),
SND_SOC_DAPM_MUX("DAC MIXR", SND_SOC_NOPM, 0, 0,
&rt5665_dig_dac_mixr_mux),
/* DACs */
SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SUPPLY("DAC L2 Power", RT5665_PWR_DIG_1,
RT5665_PWR_DAC_L2_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC R2 Power", RT5665_PWR_DIG_1,
RT5665_PWR_DAC_R2_BIT, 0, NULL, 0),
SND_SOC_DAPM_DAC("DAC L2", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DAC R2", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_PGA("DAC1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 1, RT5665_CHOP_DAC,
RT5665_CKGEN_DAC1_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DAC 2 Clock", 1, RT5665_CHOP_DAC,
RT5665_CKGEN_DAC2_SFT, 0, NULL, 0),
/* OUT Mixer */
SND_SOC_DAPM_MIXER("MONOVOL MIX", RT5665_PWR_MIXER, RT5665_PWR_MM_BIT,
0, rt5665_monovol_mix, ARRAY_SIZE(rt5665_monovol_mix)),
SND_SOC_DAPM_MIXER("OUT MIXL", RT5665_PWR_MIXER, RT5665_PWR_OM_L_BIT,
0, rt5665_out_l_mix, ARRAY_SIZE(rt5665_out_l_mix)),
SND_SOC_DAPM_MIXER("OUT MIXR", RT5665_PWR_MIXER, RT5665_PWR_OM_R_BIT,
0, rt5665_out_r_mix, ARRAY_SIZE(rt5665_out_r_mix)),
/* Output Volume */
SND_SOC_DAPM_SWITCH("MONOVOL", RT5665_PWR_VOL, RT5665_PWR_MV_BIT, 0,
&monovol_switch),
SND_SOC_DAPM_SWITCH("OUTVOL L", RT5665_PWR_VOL, RT5665_PWR_OV_L_BIT, 0,
&outvol_l_switch),
SND_SOC_DAPM_SWITCH("OUTVOL R", RT5665_PWR_VOL, RT5665_PWR_OV_R_BIT, 0,
&outvol_r_switch),
/* MONO/HPO/LOUT */
SND_SOC_DAPM_MIXER("Mono MIX", SND_SOC_NOPM, 0, 0, rt5665_mono_mix,
ARRAY_SIZE(rt5665_mono_mix)),
SND_SOC_DAPM_MIXER("LOUT L MIX", SND_SOC_NOPM, 0, 0, rt5665_lout_l_mix,
ARRAY_SIZE(rt5665_lout_l_mix)),
SND_SOC_DAPM_MIXER("LOUT R MIX", SND_SOC_NOPM, 0, 0, rt5665_lout_r_mix,
ARRAY_SIZE(rt5665_lout_r_mix)),
SND_SOC_DAPM_PGA_S("Mono Amp", 1, RT5665_PWR_ANLG_1, RT5665_PWR_MA_BIT,
0, rt5665_mono_event, SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5665_hp_event,
SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_PGA_S("LOUT Amp", 1, RT5665_PWR_ANLG_1,
RT5665_PWR_LM_BIT, 0, rt5665_lout_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_SUPPLY("Charge Pump", SND_SOC_NOPM, 0, 0,
rt5665_charge_pump_event, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SWITCH("Mono Playback", SND_SOC_NOPM, 0, 0,
&mono_switch),
SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
&hpo_switch),
SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
&lout_l_switch),
SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
&lout_r_switch),
SND_SOC_DAPM_SWITCH("PDM L Playback", SND_SOC_NOPM, 0, 0,
&pdm_l_switch),
SND_SOC_DAPM_SWITCH("PDM R Playback", SND_SOC_NOPM, 0, 0,
&pdm_r_switch),
/* PDM */
SND_SOC_DAPM_SUPPLY("PDM Power", RT5665_PWR_DIG_2,
RT5665_PWR_PDM1_BIT, 0, NULL, 0),
SND_SOC_DAPM_MUX("PDM L Mux", SND_SOC_NOPM,
0, 1, &rt5665_pdm_l_mux),
SND_SOC_DAPM_MUX("PDM R Mux", SND_SOC_NOPM,
0, 1, &rt5665_pdm_r_mux),
/* CLK DET */
SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5665_CLK_DET, RT5665_SYS_CLK_DET,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CLKDET HP", RT5665_CLK_DET, RT5665_HP_CLK_DET,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CLKDET MONO", RT5665_CLK_DET, RT5665_MONO_CLK_DET,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CLKDET LOUT", RT5665_CLK_DET, RT5665_LOUT_CLK_DET,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CLKDET", RT5665_CLK_DET, RT5665_POW_CLK_DET,
0, NULL, 0),
/* Output Lines */
SND_SOC_DAPM_OUTPUT("HPOL"),
SND_SOC_DAPM_OUTPUT("HPOR"),
SND_SOC_DAPM_OUTPUT("LOUTL"),
SND_SOC_DAPM_OUTPUT("LOUTR"),
SND_SOC_DAPM_OUTPUT("MONOOUT"),
SND_SOC_DAPM_OUTPUT("PDML"),
SND_SOC_DAPM_OUTPUT("PDMR"),
};
static const struct snd_soc_dapm_route rt5665_dapm_routes[] = {
/*PLL*/
{"ADC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll},
{"ADC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll},
{"ADC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll},
{"ADC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll},
{"DAC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll},
{"DAC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll},
{"DAC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll},
{"DAC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll},
/*ASRC*/
{"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
{"ADC Stereo2 Filter", NULL, "ADC STO2 ASRC", is_using_asrc},
{"ADC Mono Left Filter", NULL, "ADC Mono L ASRC", is_using_asrc},
{"ADC Mono Right Filter", NULL, "ADC Mono R ASRC", is_using_asrc},
{"DAC Mono Left Filter", NULL, "DAC Mono L ASRC", is_using_asrc},
{"DAC Mono Right Filter", NULL, "DAC Mono R ASRC", is_using_asrc},
{"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
{"DAC Stereo2 Filter", NULL, "DAC STO2 ASRC", is_using_asrc},
{"I2S1 ASRC", NULL, "CLKDET"},
{"I2S2 ASRC", NULL, "CLKDET"},
{"I2S3 ASRC", NULL, "CLKDET"},
/*Vref*/
{"Mic Det Power", NULL, "Vref2"},
{"MICBIAS1", NULL, "Vref1"},
{"MICBIAS1", NULL, "Vref2"},
{"MICBIAS2", NULL, "Vref1"},
{"MICBIAS2", NULL, "Vref2"},
{"MICBIAS3", NULL, "Vref1"},
{"MICBIAS3", NULL, "Vref2"},
{"Stereo1 DMIC L Mux", NULL, "DMIC STO1 ASRC"},
{"Stereo1 DMIC R Mux", NULL, "DMIC STO1 ASRC"},
{"Stereo2 DMIC L Mux", NULL, "DMIC STO2 ASRC"},
{"Stereo2 DMIC R Mux", NULL, "DMIC STO2 ASRC"},
{"Mono DMIC L Mux", NULL, "DMIC MONO L ASRC"},
{"Mono DMIC R Mux", NULL, "DMIC MONO R ASRC"},
{"I2S1_1", NULL, "I2S1 ASRC"},
{"I2S1_2", NULL, "I2S1 ASRC"},
{"I2S2_1", NULL, "I2S2 ASRC"},
{"I2S2_2", NULL, "I2S2 ASRC"},
{"I2S3", NULL, "I2S3 ASRC"},
{"CLKDET SYS", NULL, "CLKDET"},
{"CLKDET HP", NULL, "CLKDET"},
{"CLKDET MONO", NULL, "CLKDET"},
{"CLKDET LOUT", NULL, "CLKDET"},
{"IN1P", NULL, "LDO2"},
{"IN2P", NULL, "LDO2"},
{"IN3P", NULL, "LDO2"},
{"IN4P", NULL, "LDO2"},
{"DMIC1", NULL, "DMIC L1"},
{"DMIC1", NULL, "DMIC R1"},
{"DMIC2", NULL, "DMIC L2"},
{"DMIC2", NULL, "DMIC R2"},
{"BST1", NULL, "IN1P"},
{"BST1", NULL, "IN1N"},
{"BST1", NULL, "BST1 Power"},
{"BST1", NULL, "BST1P Power"},
{"BST2", NULL, "IN2P"},
{"BST2", NULL, "IN2N"},
{"BST2", NULL, "BST2 Power"},
{"BST2", NULL, "BST2P Power"},
{"BST3", NULL, "IN3P"},
{"BST3", NULL, "IN3N"},
{"BST3", NULL, "BST3 Power"},
{"BST3", NULL, "BST3P Power"},
{"BST4", NULL, "IN4P"},
{"BST4", NULL, "IN4N"},
{"BST4", NULL, "BST4 Power"},
{"BST4", NULL, "BST4P Power"},
{"BST1 CBJ", NULL, "IN1P"},
{"BST1 CBJ", NULL, "IN1N"},
{"BST1 CBJ", NULL, "CBJ Power"},
{"CBJ Power", NULL, "Vref2"},
{"INL VOL", NULL, "IN3P"},
{"INR VOL", NULL, "IN3N"},
{"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
{"RECMIX1L", "INL Switch", "INL VOL"},
{"RECMIX1L", "INR Switch", "INR VOL"},
{"RECMIX1L", "BST4 Switch", "BST4"},
{"RECMIX1L", "BST3 Switch", "BST3"},
{"RECMIX1L", "BST2 Switch", "BST2"},
{"RECMIX1L", "BST1 Switch", "BST1"},
{"RECMIX1L", NULL, "RECMIX1L Power"},
{"RECMIX1R", "MONOVOL Switch", "MONOVOL"},
{"RECMIX1R", "INR Switch", "INR VOL"},
{"RECMIX1R", "BST4 Switch", "BST4"},
{"RECMIX1R", "BST3 Switch", "BST3"},
{"RECMIX1R", "BST2 Switch", "BST2"},
{"RECMIX1R", "BST1 Switch", "BST1"},
{"RECMIX1R", NULL, "RECMIX1R Power"},
{"RECMIX2L", "CBJ Switch", "BST1 CBJ"},
{"RECMIX2L", "INL Switch", "INL VOL"},
{"RECMIX2L", "INR Switch", "INR VOL"},
{"RECMIX2L", "BST4 Switch", "BST4"},
{"RECMIX2L", "BST3 Switch", "BST3"},
{"RECMIX2L", "BST2 Switch", "BST2"},
{"RECMIX2L", "BST1 Switch", "BST1"},
{"RECMIX2L", NULL, "RECMIX2L Power"},
{"RECMIX2R", "MONOVOL Switch", "MONOVOL"},
{"RECMIX2R", "INL Switch", "INL VOL"},
{"RECMIX2R", "INR Switch", "INR VOL"},
{"RECMIX2R", "BST4 Switch", "BST4"},
{"RECMIX2R", "BST3 Switch", "BST3"},
{"RECMIX2R", "BST2 Switch", "BST2"},
{"RECMIX2R", "BST1 Switch", "BST1"},
{"RECMIX2R", NULL, "RECMIX2R Power"},
{"ADC1 L", NULL, "RECMIX1L"},
{"ADC1 L", NULL, "ADC1 L Power"},
{"ADC1 L", NULL, "ADC1 clock"},
{"ADC1 R", NULL, "RECMIX1R"},
{"ADC1 R", NULL, "ADC1 R Power"},
{"ADC1 R", NULL, "ADC1 clock"},
{"ADC2 L", NULL, "RECMIX2L"},
{"ADC2 L", NULL, "ADC2 L Power"},
{"ADC2 L", NULL, "ADC2 clock"},
{"ADC2 R", NULL, "RECMIX2R"},
{"ADC2 R", NULL, "ADC2 R Power"},
{"ADC2 R", NULL, "ADC2 clock"},
{"DMIC L1", NULL, "DMIC CLK"},
{"DMIC L1", NULL, "DMIC1 Power"},
{"DMIC R1", NULL, "DMIC CLK"},
{"DMIC R1", NULL, "DMIC1 Power"},
{"DMIC L2", NULL, "DMIC CLK"},
{"DMIC L2", NULL, "DMIC2 Power"},
{"DMIC R2", NULL, "DMIC CLK"},
{"DMIC R2", NULL, "DMIC2 Power"},
{"Stereo1 DMIC L Mux", "DMIC1", "DMIC L1"},
{"Stereo1 DMIC L Mux", "DMIC2", "DMIC L2"},
{"Stereo1 DMIC R Mux", "DMIC1", "DMIC R1"},
{"Stereo1 DMIC R Mux", "DMIC2", "DMIC R2"},
{"Mono DMIC L Mux", "DMIC1 L", "DMIC L1"},
{"Mono DMIC L Mux", "DMIC2 L", "DMIC L2"},
{"Mono DMIC R Mux", "DMIC1 R", "DMIC R1"},
{"Mono DMIC R Mux", "DMIC2 R", "DMIC R2"},
{"Stereo2 DMIC L Mux", "DMIC1", "DMIC L1"},
{"Stereo2 DMIC L Mux", "DMIC2", "DMIC L2"},
{"Stereo2 DMIC R Mux", "DMIC1", "DMIC R1"},
{"Stereo2 DMIC R Mux", "DMIC2", "DMIC R2"},
{"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
{"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
{"Stereo1 ADC L Mux", "ADC2 L", "ADC2 L"},
{"Stereo1 ADC L Mux", "ADC2 R", "ADC2 R"},
{"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
{"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
{"Stereo1 ADC R Mux", "ADC2 L", "ADC2 L"},
{"Stereo1 ADC R Mux", "ADC2 R", "ADC2 R"},
{"Stereo1 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
{"Stereo1 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
{"Stereo1 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
{"Stereo1 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
{"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
{"Stereo1 ADC L1 Mux", "DD Mux", "Stereo1 DD L Mux"},
{"Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC L Mux"},
{"Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
{"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
{"Stereo1 ADC R1 Mux", "DD Mux", "Stereo1 DD R Mux"},
{"Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC R Mux"},
{"Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
{"Mono ADC L Mux", "ADC1 L", "ADC1 L"},
{"Mono ADC L Mux", "ADC1 R", "ADC1 R"},
{"Mono ADC L Mux", "ADC2 L", "ADC2 L"},
{"Mono ADC L Mux", "ADC2 R", "ADC2 R"},
{"Mono ADC R Mux", "ADC1 L", "ADC1 L"},
{"Mono ADC R Mux", "ADC1 R", "ADC1 R"},
{"Mono ADC R Mux", "ADC2 L", "ADC2 L"},
{"Mono ADC R Mux", "ADC2 R", "ADC2 R"},
{"Mono DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
{"Mono DD L Mux", "MONO DAC", "Mono DAC MIXL"},
{"Mono DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
{"Mono DD R Mux", "MONO DAC", "Mono DAC MIXR"},
{"Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux"},
{"Mono ADC L2 Mux", "DAC MIXL", "DAC MIXL"},
{"Mono ADC L1 Mux", "DD Mux", "Mono DD L Mux"},
{"Mono ADC L1 Mux", "ADC", "Mono ADC L Mux"},
{"Mono ADC R1 Mux", "DD Mux", "Mono DD R Mux"},
{"Mono ADC R1 Mux", "ADC", "Mono ADC R Mux"},
{"Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux"},
{"Mono ADC R2 Mux", "DAC MIXR", "DAC MIXR"},
{"Stereo2 ADC L Mux", "ADC1 L", "ADC1 L"},
{"Stereo2 ADC L Mux", "ADC2 L", "ADC2 L"},
{"Stereo2 ADC L Mux", "ADC1 R", "ADC1 R"},
{"Stereo2 ADC R Mux", "ADC1 L", "ADC1 L"},
{"Stereo2 ADC R Mux", "ADC2 L", "ADC2 L"},
{"Stereo2 ADC R Mux", "ADC1 R", "ADC1 R"},
{"Stereo2 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
{"Stereo2 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
{"Stereo2 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
{"Stereo2 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
{"Stereo2 ADC L1 Mux", "ADC", "Stereo2 ADC L Mux"},
{"Stereo2 ADC L1 Mux", "DD Mux", "Stereo2 DD L Mux"},
{"Stereo2 ADC L2 Mux", "DMIC", "Stereo2 DMIC L Mux"},
{"Stereo2 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
{"Stereo2 ADC R1 Mux", "ADC", "Stereo2 ADC R Mux"},
{"Stereo2 ADC R1 Mux", "DD Mux", "Stereo2 DD R Mux"},
{"Stereo2 ADC R2 Mux", "DMIC", "Stereo2 DMIC R Mux"},
{"Stereo2 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
{"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
{"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
{"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
{"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
{"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
{"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
{"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"},
{"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
{"Mono ADC MIXL", NULL, "ADC Mono Left Filter"},
{"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
{"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
{"Mono ADC MIXR", NULL, "ADC Mono Right Filter"},
{"Stereo2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux"},
{"Stereo2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux"},
{"Stereo2 ADC MIXL", NULL, "ADC Stereo2 Filter"},
{"Stereo2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux"},
{"Stereo2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux"},
{"Stereo2 ADC MIXR", NULL, "ADC Stereo2 Filter"},
{"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
{"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
{"Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL"},
{"Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR"},
{"Mono ADC MIX", NULL, "Mono ADC MIXL"},
{"Mono ADC MIX", NULL, "Mono ADC MIXR"},
{"IF1_1_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
{"IF1_1_ADC1 Mux", "IF2_1 DAC", "IF2_1 DAC"},
{"IF1_1_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
{"IF1_1_ADC2 Mux", "IF2_2 DAC", "IF2_2 DAC"},
{"IF1_1_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
{"IF1_1_ADC3 Mux", "IF3 DAC", "IF3 DAC"},
{"IF1_1_ADC4", NULL, "DAC1 MIX"},
{"IF1_2_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
{"IF1_2_ADC1 Mux", "IF1 DAC", "IF1 DAC1"},
{"IF1_2_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
{"IF1_2_ADC2 Mux", "IF2_1 DAC", "IF2_1 DAC"},
{"IF1_2_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
{"IF1_2_ADC3 Mux", "IF2_2 DAC", "IF2_2 DAC"},
{"IF1_2_ADC4 Mux", "DAC1", "DAC1 MIX"},
{"IF1_2_ADC4 Mux", "IF3 DAC", "IF3 DAC"},
{"TDM1 slot 01 Data Mux", "1234", "IF1_1_ADC1 Mux"},
{"TDM1 slot 01 Data Mux", "1243", "IF1_1_ADC1 Mux"},
{"TDM1 slot 01 Data Mux", "1324", "IF1_1_ADC1 Mux"},
{"TDM1 slot 01 Data Mux", "1342", "IF1_1_ADC1 Mux"},
{"TDM1 slot 01 Data Mux", "1432", "IF1_1_ADC1 Mux"},
{"TDM1 slot 01 Data Mux", "1423", "IF1_1_ADC1 Mux"},
{"TDM1 slot 01 Data Mux", "2134", "IF1_1_ADC2 Mux"},
{"TDM1 slot 01 Data Mux", "2143", "IF1_1_ADC2 Mux"},
{"TDM1 slot 01 Data Mux", "2314", "IF1_1_ADC2 Mux"},
{"TDM1 slot 01 Data Mux", "2341", "IF1_1_ADC2 Mux"},
{"TDM1 slot 01 Data Mux", "2431", "IF1_1_ADC2 Mux"},
{"TDM1 slot 01 Data Mux", "2413", "IF1_1_ADC2 Mux"},
{"TDM1 slot 01 Data Mux", "3124", "IF1_1_ADC3 Mux"},
{"TDM1 slot 01 Data Mux", "3142", "IF1_1_ADC3 Mux"},
{"TDM1 slot 01 Data Mux", "3214", "IF1_1_ADC3 Mux"},
{"TDM1 slot 01 Data Mux", "3241", "IF1_1_ADC3 Mux"},
{"TDM1 slot 01 Data Mux", "3412", "IF1_1_ADC3 Mux"},
{"TDM1 slot 01 Data Mux", "3421", "IF1_1_ADC3 Mux"},
{"TDM1 slot 01 Data Mux", "4123", "IF1_1_ADC4"},
{"TDM1 slot 01 Data Mux", "4132", "IF1_1_ADC4"},
{"TDM1 slot 01 Data Mux", "4213", "IF1_1_ADC4"},
{"TDM1 slot 01 Data Mux", "4231", "IF1_1_ADC4"},
{"TDM1 slot 01 Data Mux", "4312", "IF1_1_ADC4"},
{"TDM1 slot 01 Data Mux", "4321", "IF1_1_ADC4"},
{"TDM1 slot 01 Data Mux", NULL, "I2S1_1"},
{"TDM1 slot 23 Data Mux", "1234", "IF1_1_ADC2 Mux"},
{"TDM1 slot 23 Data Mux", "1243", "IF1_1_ADC2 Mux"},
{"TDM1 slot 23 Data Mux", "1324", "IF1_1_ADC3 Mux"},
{"TDM1 slot 23 Data Mux", "1342", "IF1_1_ADC3 Mux"},
{"TDM1 slot 23 Data Mux", "1432", "IF1_1_ADC4"},
{"TDM1 slot 23 Data Mux", "1423", "IF1_1_ADC4"},
{"TDM1 slot 23 Data Mux", "2134", "IF1_1_ADC1 Mux"},
{"TDM1 slot 23 Data Mux", "2143", "IF1_1_ADC1 Mux"},
{"TDM1 slot 23 Data Mux", "2314", "IF1_1_ADC3 Mux"},
{"TDM1 slot 23 Data Mux", "2341", "IF1_1_ADC3 Mux"},
{"TDM1 slot 23 Data Mux", "2431", "IF1_1_ADC4"},
{"TDM1 slot 23 Data Mux", "2413", "IF1_1_ADC4"},
{"TDM1 slot 23 Data Mux", "3124", "IF1_1_ADC1 Mux"},
{"TDM1 slot 23 Data Mux", "3142", "IF1_1_ADC1 Mux"},
{"TDM1 slot 23 Data Mux", "3214", "IF1_1_ADC2 Mux"},
{"TDM1 slot 23 Data Mux", "3241", "IF1_1_ADC2 Mux"},
{"TDM1 slot 23 Data Mux", "3412", "IF1_1_ADC4"},
{"TDM1 slot 23 Data Mux", "3421", "IF1_1_ADC4"},
{"TDM1 slot 23 Data Mux", "4123", "IF1_1_ADC1 Mux"},
{"TDM1 slot 23 Data Mux", "4132", "IF1_1_ADC1 Mux"},
{"TDM1 slot 23 Data Mux", "4213", "IF1_1_ADC2 Mux"},
{"TDM1 slot 23 Data Mux", "4231", "IF1_1_ADC2 Mux"},
{"TDM1 slot 23 Data Mux", "4312", "IF1_1_ADC3 Mux"},
{"TDM1 slot 23 Data Mux", "4321", "IF1_1_ADC3 Mux"},
{"TDM1 slot 23 Data Mux", NULL, "I2S1_1"},
{"TDM1 slot 45 Data Mux", "1234", "IF1_1_ADC3 Mux"},
{"TDM1 slot 45 Data Mux", "1243", "IF1_1_ADC4"},
{"TDM1 slot 45 Data Mux", "1324", "IF1_1_ADC2 Mux"},
{"TDM1 slot 45 Data Mux", "1342", "IF1_1_ADC4"},
{"TDM1 slot 45 Data Mux", "1432", "IF1_1_ADC3 Mux"},
{"TDM1 slot 45 Data Mux", "1423", "IF1_1_ADC2 Mux"},
{"TDM1 slot 45 Data Mux", "2134", "IF1_1_ADC3 Mux"},
{"TDM1 slot 45 Data Mux", "2143", "IF1_1_ADC4"},
{"TDM1 slot 45 Data Mux", "2314", "IF1_1_ADC1 Mux"},
{"TDM1 slot 45 Data Mux", "2341", "IF1_1_ADC4"},
{"TDM1 slot 45 Data Mux", "2431", "IF1_1_ADC3 Mux"},
{"TDM1 slot 45 Data Mux", "2413", "IF1_1_ADC1 Mux"},
{"TDM1 slot 45 Data Mux", "3124", "IF1_1_ADC2 Mux"},
{"TDM1 slot 45 Data Mux", "3142", "IF1_1_ADC4"},
{"TDM1 slot 45 Data Mux", "3214", "IF1_1_ADC1 Mux"},
{"TDM1 slot 45 Data Mux", "3241", "IF1_1_ADC4"},
{"TDM1 slot 45 Data Mux", "3412", "IF1_1_ADC1 Mux"},
{"TDM1 slot 45 Data Mux", "3421", "IF1_1_ADC2 Mux"},
{"TDM1 slot 45 Data Mux", "4123", "IF1_1_ADC2 Mux"},
{"TDM1 slot 45 Data Mux", "4132", "IF1_1_ADC3 Mux"},
{"TDM1 slot 45 Data Mux", "4213", "IF1_1_ADC1 Mux"},
{"TDM1 slot 45 Data Mux", "4231", "IF1_1_ADC3 Mux"},
{"TDM1 slot 45 Data Mux", "4312", "IF1_1_ADC1 Mux"},
{"TDM1 slot 45 Data Mux", "4321", "IF1_1_ADC2 Mux"},
{"TDM1 slot 45 Data Mux", NULL, "I2S1_1"},
{"TDM1 slot 67 Data Mux", "1234", "IF1_1_ADC4"},
{"TDM1 slot 67 Data Mux", "1243", "IF1_1_ADC3 Mux"},
{"TDM1 slot 67 Data Mux", "1324", "IF1_1_ADC4"},
{"TDM1 slot 67 Data Mux", "1342", "IF1_1_ADC2 Mux"},
{"TDM1 slot 67 Data Mux", "1432", "IF1_1_ADC2 Mux"},
{"TDM1 slot 67 Data Mux", "1423", "IF1_1_ADC3 Mux"},
{"TDM1 slot 67 Data Mux", "2134", "IF1_1_ADC4"},
{"TDM1 slot 67 Data Mux", "2143", "IF1_1_ADC3 Mux"},
{"TDM1 slot 67 Data Mux", "2314", "IF1_1_ADC4"},
{"TDM1 slot 67 Data Mux", "2341", "IF1_1_ADC1 Mux"},
{"TDM1 slot 67 Data Mux", "2431", "IF1_1_ADC1 Mux"},
{"TDM1 slot 67 Data Mux", "2413", "IF1_1_ADC3 Mux"},
{"TDM1 slot 67 Data Mux", "3124", "IF1_1_ADC4"},
{"TDM1 slot 67 Data Mux", "3142", "IF1_1_ADC2 Mux"},
{"TDM1 slot 67 Data Mux", "3214", "IF1_1_ADC4"},
{"TDM1 slot 67 Data Mux", "3241", "IF1_1_ADC1 Mux"},
{"TDM1 slot 67 Data Mux", "3412", "IF1_1_ADC2 Mux"},
{"TDM1 slot 67 Data Mux", "3421", "IF1_1_ADC1 Mux"},
{"TDM1 slot 67 Data Mux", "4123", "IF1_1_ADC3 Mux"},
{"TDM1 slot 67 Data Mux", "4132", "IF1_1_ADC2 Mux"},
{"TDM1 slot 67 Data Mux", "4213", "IF1_1_ADC3 Mux"},
{"TDM1 slot 67 Data Mux", "4231", "IF1_1_ADC1 Mux"},
{"TDM1 slot 67 Data Mux", "4312", "IF1_1_ADC2 Mux"},
{"TDM1 slot 67 Data Mux", "4321", "IF1_1_ADC1 Mux"},
{"TDM1 slot 67 Data Mux", NULL, "I2S1_1"},
{"TDM2 slot 01 Data Mux", "1234", "IF1_2_ADC1 Mux"},
{"TDM2 slot 01 Data Mux", "1243", "IF1_2_ADC1 Mux"},
{"TDM2 slot 01 Data Mux", "1324", "IF1_2_ADC1 Mux"},
{"TDM2 slot 01 Data Mux", "1342", "IF1_2_ADC1 Mux"},
{"TDM2 slot 01 Data Mux", "1432", "IF1_2_ADC1 Mux"},
{"TDM2 slot 01 Data Mux", "1423", "IF1_2_ADC1 Mux"},
{"TDM2 slot 01 Data Mux", "2134", "IF1_2_ADC2 Mux"},
{"TDM2 slot 01 Data Mux", "2143", "IF1_2_ADC2 Mux"},
{"TDM2 slot 01 Data Mux", "2314", "IF1_2_ADC2 Mux"},
{"TDM2 slot 01 Data Mux", "2341", "IF1_2_ADC2 Mux"},
{"TDM2 slot 01 Data Mux", "2431", "IF1_2_ADC2 Mux"},
{"TDM2 slot 01 Data Mux", "2413", "IF1_2_ADC2 Mux"},
{"TDM2 slot 01 Data Mux", "3124", "IF1_2_ADC3 Mux"},
{"TDM2 slot 01 Data Mux", "3142", "IF1_2_ADC3 Mux"},
{"TDM2 slot 01 Data Mux", "3214", "IF1_2_ADC3 Mux"},
{"TDM2 slot 01 Data Mux", "3241", "IF1_2_ADC3 Mux"},
{"TDM2 slot 01 Data Mux", "3412", "IF1_2_ADC3 Mux"},
{"TDM2 slot 01 Data Mux", "3421", "IF1_2_ADC3 Mux"},
{"TDM2 slot 01 Data Mux", "4123", "IF1_2_ADC4 Mux"},
{"TDM2 slot 01 Data Mux", "4132", "IF1_2_ADC4 Mux"},
{"TDM2 slot 01 Data Mux", "4213", "IF1_2_ADC4 Mux"},
{"TDM2 slot 01 Data Mux", "4231", "IF1_2_ADC4 Mux"},
{"TDM2 slot 01 Data Mux", "4312", "IF1_2_ADC4 Mux"},
{"TDM2 slot 01 Data Mux", "4321", "IF1_2_ADC4 Mux"},
{"TDM2 slot 01 Data Mux", NULL, "I2S1_2"},
{"TDM2 slot 23 Data Mux", "1234", "IF1_2_ADC2 Mux"},
{"TDM2 slot 23 Data Mux", "1243", "IF1_2_ADC2 Mux"},
{"TDM2 slot 23 Data Mux", "1324", "IF1_2_ADC3 Mux"},
{"TDM2 slot 23 Data Mux", "1342", "IF1_2_ADC3 Mux"},
{"TDM2 slot 23 Data Mux", "1432", "IF1_2_ADC4 Mux"},
{"TDM2 slot 23 Data Mux", "1423", "IF1_2_ADC4 Mux"},
{"TDM2 slot 23 Data Mux", "2134", "IF1_2_ADC1 Mux"},
{"TDM2 slot 23 Data Mux", "2143", "IF1_2_ADC1 Mux"},
{"TDM2 slot 23 Data Mux", "2314", "IF1_2_ADC3 Mux"},
{"TDM2 slot 23 Data Mux", "2341", "IF1_2_ADC3 Mux"},
{"TDM2 slot 23 Data Mux", "2431", "IF1_2_ADC4 Mux"},
{"TDM2 slot 23 Data Mux", "2413", "IF1_2_ADC4 Mux"},
{"TDM2 slot 23 Data Mux", "3124", "IF1_2_ADC1 Mux"},
{"TDM2 slot 23 Data Mux", "3142", "IF1_2_ADC1 Mux"},
{"TDM2 slot 23 Data Mux", "3214", "IF1_2_ADC2 Mux"},
{"TDM2 slot 23 Data Mux", "3241", "IF1_2_ADC2 Mux"},
{"TDM2 slot 23 Data Mux", "3412", "IF1_2_ADC4 Mux"},
{"TDM2 slot 23 Data Mux", "3421", "IF1_2_ADC4 Mux"},
{"TDM2 slot 23 Data Mux", "4123", "IF1_2_ADC1 Mux"},
{"TDM2 slot 23 Data Mux", "4132", "IF1_2_ADC1 Mux"},
{"TDM2 slot 23 Data Mux", "4213", "IF1_2_ADC2 Mux"},
{"TDM2 slot 23 Data Mux", "4231", "IF1_2_ADC2 Mux"},
{"TDM2 slot 23 Data Mux", "4312", "IF1_2_ADC3 Mux"},
{"TDM2 slot 23 Data Mux", "4321", "IF1_2_ADC3 Mux"},
{"TDM2 slot 23 Data Mux", NULL, "I2S1_2"},
{"TDM2 slot 45 Data Mux", "1234", "IF1_2_ADC3 Mux"},
{"TDM2 slot 45 Data Mux", "1243", "IF1_2_ADC4 Mux"},
{"TDM2 slot 45 Data Mux", "1324", "IF1_2_ADC2 Mux"},
{"TDM2 slot 45 Data Mux", "1342", "IF1_2_ADC4 Mux"},
{"TDM2 slot 45 Data Mux", "1432", "IF1_2_ADC3 Mux"},
{"TDM2 slot 45 Data Mux", "1423", "IF1_2_ADC2 Mux"},
{"TDM2 slot 45 Data Mux", "2134", "IF1_2_ADC3 Mux"},
{"TDM2 slot 45 Data Mux", "2143", "IF1_2_ADC4 Mux"},
{"TDM2 slot 45 Data Mux", "2314", "IF1_2_ADC1 Mux"},
{"TDM2 slot 45 Data Mux", "2341", "IF1_2_ADC4 Mux"},
{"TDM2 slot 45 Data Mux", "2431", "IF1_2_ADC3 Mux"},
{"TDM2 slot 45 Data Mux", "2413", "IF1_2_ADC1 Mux"},
{"TDM2 slot 45 Data Mux", "3124", "IF1_2_ADC2 Mux"},
{"TDM2 slot 45 Data Mux", "3142", "IF1_2_ADC4 Mux"},
{"TDM2 slot 45 Data Mux", "3214", "IF1_2_ADC1 Mux"},
{"TDM2 slot 45 Data Mux", "3241", "IF1_2_ADC4 Mux"},
{"TDM2 slot 45 Data Mux", "3412", "IF1_2_ADC1 Mux"},
{"TDM2 slot 45 Data Mux", "3421", "IF1_2_ADC2 Mux"},
{"TDM2 slot 45 Data Mux", "4123", "IF1_2_ADC2 Mux"},
{"TDM2 slot 45 Data Mux", "4132", "IF1_2_ADC3 Mux"},
{"TDM2 slot 45 Data Mux", "4213", "IF1_2_ADC1 Mux"},
{"TDM2 slot 45 Data Mux", "4231", "IF1_2_ADC3 Mux"},
{"TDM2 slot 45 Data Mux", "4312", "IF1_2_ADC1 Mux"},
{"TDM2 slot 45 Data Mux", "4321", "IF1_2_ADC2 Mux"},
{"TDM2 slot 45 Data Mux", NULL, "I2S1_2"},
{"TDM2 slot 67 Data Mux", "1234", "IF1_2_ADC4 Mux"},
{"TDM2 slot 67 Data Mux", "1243", "IF1_2_ADC3 Mux"},
{"TDM2 slot 67 Data Mux", "1324", "IF1_2_ADC4 Mux"},
{"TDM2 slot 67 Data Mux", "1342", "IF1_2_ADC2 Mux"},
{"TDM2 slot 67 Data Mux", "1432", "IF1_2_ADC2 Mux"},
{"TDM2 slot 67 Data Mux", "1423", "IF1_2_ADC3 Mux"},
{"TDM2 slot 67 Data Mux", "2134", "IF1_2_ADC4 Mux"},
{"TDM2 slot 67 Data Mux", "2143", "IF1_2_ADC3 Mux"},
{"TDM2 slot 67 Data Mux", "2314", "IF1_2_ADC4 Mux"},
{"TDM2 slot 67 Data Mux", "2341", "IF1_2_ADC1 Mux"},
{"TDM2 slot 67 Data Mux", "2431", "IF1_2_ADC1 Mux"},
{"TDM2 slot 67 Data Mux", "2413", "IF1_2_ADC3 Mux"},
{"TDM2 slot 67 Data Mux", "3124", "IF1_2_ADC4 Mux"},
{"TDM2 slot 67 Data Mux", "3142", "IF1_2_ADC2 Mux"},
{"TDM2 slot 67 Data Mux", "3214", "IF1_2_ADC4 Mux"},
{"TDM2 slot 67 Data Mux", "3241", "IF1_2_ADC1 Mux"},
{"TDM2 slot 67 Data Mux", "3412", "IF1_2_ADC2 Mux"},
{"TDM2 slot 67 Data Mux", "3421", "IF1_2_ADC1 Mux"},
{"TDM2 slot 67 Data Mux", "4123", "IF1_2_ADC3 Mux"},
{"TDM2 slot 67 Data Mux", "4132", "IF1_2_ADC2 Mux"},
{"TDM2 slot 67 Data Mux", "4213", "IF1_2_ADC3 Mux"},
{"TDM2 slot 67 Data Mux", "4231", "IF1_2_ADC1 Mux"},
{"TDM2 slot 67 Data Mux", "4312", "IF1_2_ADC2 Mux"},
{"TDM2 slot 67 Data Mux", "4321", "IF1_2_ADC1 Mux"},
{"TDM2 slot 67 Data Mux", NULL, "I2S1_2"},
{"IF1_1 0 ADC Swap Mux", "L/R", "TDM1 slot 01 Data Mux"},
{"IF1_1 0 ADC Swap Mux", "L/L", "TDM1 slot 01 Data Mux"},
{"IF1_1 1 ADC Swap Mux", "R/L", "TDM1 slot 01 Data Mux"},
{"IF1_1 1 ADC Swap Mux", "R/R", "TDM1 slot 01 Data Mux"},
{"IF1_1 2 ADC Swap Mux", "L/R", "TDM1 slot 23 Data Mux"},
{"IF1_1 2 ADC Swap Mux", "R/L", "TDM1 slot 23 Data Mux"},
{"IF1_1 3 ADC Swap Mux", "L/L", "TDM1 slot 23 Data Mux"},
{"IF1_1 3 ADC Swap Mux", "R/R", "TDM1 slot 23 Data Mux"},
{"IF1_1 4 ADC Swap Mux", "L/R", "TDM1 slot 45 Data Mux"},
{"IF1_1 4 ADC Swap Mux", "R/L", "TDM1 slot 45 Data Mux"},
{"IF1_1 5 ADC Swap Mux", "L/L", "TDM1 slot 45 Data Mux"},
{"IF1_1 5 ADC Swap Mux", "R/R", "TDM1 slot 45 Data Mux"},
{"IF1_1 6 ADC Swap Mux", "L/R", "TDM1 slot 67 Data Mux"},
{"IF1_1 6 ADC Swap Mux", "R/L", "TDM1 slot 67 Data Mux"},
{"IF1_1 7 ADC Swap Mux", "L/L", "TDM1 slot 67 Data Mux"},
{"IF1_1 7 ADC Swap Mux", "R/R", "TDM1 slot 67 Data Mux"},
{"IF1_2 0 ADC Swap Mux", "L/R", "TDM2 slot 01 Data Mux"},
{"IF1_2 0 ADC Swap Mux", "R/L", "TDM2 slot 01 Data Mux"},
{"IF1_2 1 ADC Swap Mux", "L/L", "TDM2 slot 01 Data Mux"},
{"IF1_2 1 ADC Swap Mux", "R/R", "TDM2 slot 01 Data Mux"},
{"IF1_2 2 ADC Swap Mux", "L/R", "TDM2 slot 23 Data Mux"},
{"IF1_2 2 ADC Swap Mux", "R/L", "TDM2 slot 23 Data Mux"},
{"IF1_2 3 ADC Swap Mux", "L/L", "TDM2 slot 23 Data Mux"},
{"IF1_2 3 ADC Swap Mux", "R/R", "TDM2 slot 23 Data Mux"},
{"IF1_2 4 ADC Swap Mux", "L/R", "TDM2 slot 45 Data Mux"},
{"IF1_2 4 ADC Swap Mux", "R/L", "TDM2 slot 45 Data Mux"},
{"IF1_2 5 ADC Swap Mux", "L/L", "TDM2 slot 45 Data Mux"},
{"IF1_2 5 ADC Swap Mux", "R/R", "TDM2 slot 45 Data Mux"},
{"IF1_2 6 ADC Swap Mux", "L/R", "TDM2 slot 67 Data Mux"},
{"IF1_2 6 ADC Swap Mux", "R/L", "TDM2 slot 67 Data Mux"},
{"IF1_2 7 ADC Swap Mux", "L/L", "TDM2 slot 67 Data Mux"},
{"IF1_2 7 ADC Swap Mux", "R/R", "TDM2 slot 67 Data Mux"},
{"IF2_1 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
{"IF2_1 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
{"IF2_1 ADC Mux", "MONO ADC", "Mono ADC MIX"},
{"IF2_1 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
{"IF2_1 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
{"IF2_1 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
{"IF2_1 ADC Mux", "IF3 DAC", "IF3 DAC"},
{"IF2_1 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
{"IF2_1 ADC", NULL, "IF2_1 ADC Mux"},
{"IF2_1 ADC", NULL, "I2S2_1"},
{"IF2_2 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
{"IF2_2 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
{"IF2_2 ADC Mux", "MONO ADC", "Mono ADC MIX"},
{"IF2_2 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
{"IF2_2 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
{"IF2_2 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
{"IF2_2 ADC Mux", "IF3 DAC", "IF3 DAC"},
{"IF2_2 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
{"IF2_2 ADC", NULL, "IF2_2 ADC Mux"},
{"IF2_2 ADC", NULL, "I2S2_2"},
{"IF3 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
{"IF3 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
{"IF3 ADC Mux", "MONO ADC", "Mono ADC MIX"},
{"IF3 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
{"IF3 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
{"IF3 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
{"IF3 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
{"IF3 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
{"IF3 ADC", NULL, "IF3 ADC Mux"},
{"IF3 ADC", NULL, "I2S3"},
{"AIF1_1TX slot 0", NULL, "IF1_1 0 ADC Swap Mux"},
{"AIF1_1TX slot 1", NULL, "IF1_1 1 ADC Swap Mux"},
{"AIF1_1TX slot 2", NULL, "IF1_1 2 ADC Swap Mux"},
{"AIF1_1TX slot 3", NULL, "IF1_1 3 ADC Swap Mux"},
{"AIF1_1TX slot 4", NULL, "IF1_1 4 ADC Swap Mux"},
{"AIF1_1TX slot 5", NULL, "IF1_1 5 ADC Swap Mux"},
{"AIF1_1TX slot 6", NULL, "IF1_1 6 ADC Swap Mux"},
{"AIF1_1TX slot 7", NULL, "IF1_1 7 ADC Swap Mux"},
{"AIF1_2TX slot 0", NULL, "IF1_2 0 ADC Swap Mux"},
{"AIF1_2TX slot 1", NULL, "IF1_2 1 ADC Swap Mux"},
{"AIF1_2TX slot 2", NULL, "IF1_2 2 ADC Swap Mux"},
{"AIF1_2TX slot 3", NULL, "IF1_2 3 ADC Swap Mux"},
{"AIF1_2TX slot 4", NULL, "IF1_2 4 ADC Swap Mux"},
{"AIF1_2TX slot 5", NULL, "IF1_2 5 ADC Swap Mux"},
{"AIF1_2TX slot 6", NULL, "IF1_2 6 ADC Swap Mux"},
{"AIF1_2TX slot 7", NULL, "IF1_2 7 ADC Swap Mux"},
{"IF2_1 ADC Swap Mux", "L/R", "IF2_1 ADC"},
{"IF2_1 ADC Swap Mux", "R/L", "IF2_1 ADC"},
{"IF2_1 ADC Swap Mux", "L/L", "IF2_1 ADC"},
{"IF2_1 ADC Swap Mux", "R/R", "IF2_1 ADC"},
{"AIF2_1TX", NULL, "IF2_1 ADC Swap Mux"},
{"IF2_2 ADC Swap Mux", "L/R", "IF2_2 ADC"},
{"IF2_2 ADC Swap Mux", "R/L", "IF2_2 ADC"},
{"IF2_2 ADC Swap Mux", "L/L", "IF2_2 ADC"},
{"IF2_2 ADC Swap Mux", "R/R", "IF2_2 ADC"},
{"AIF2_2TX", NULL, "IF2_2 ADC Swap Mux"},
{"IF3 ADC Swap Mux", "L/R", "IF3 ADC"},
{"IF3 ADC Swap Mux", "R/L", "IF3 ADC"},
{"IF3 ADC Swap Mux", "L/L", "IF3 ADC"},
{"IF3 ADC Swap Mux", "R/R", "IF3 ADC"},
{"AIF3TX", NULL, "IF3 ADC Swap Mux"},
{"IF1 DAC1", NULL, "AIF1RX"},
{"IF1 DAC2", NULL, "AIF1RX"},
{"IF1 DAC3", NULL, "AIF1RX"},
{"IF2_1 DAC Swap Mux", "L/R", "AIF2_1RX"},
{"IF2_1 DAC Swap Mux", "R/L", "AIF2_1RX"},
{"IF2_1 DAC Swap Mux", "L/L", "AIF2_1RX"},
{"IF2_1 DAC Swap Mux", "R/R", "AIF2_1RX"},
{"IF2_2 DAC Swap Mux", "L/R", "AIF2_2RX"},
{"IF2_2 DAC Swap Mux", "R/L", "AIF2_2RX"},
{"IF2_2 DAC Swap Mux", "L/L", "AIF2_2RX"},
{"IF2_2 DAC Swap Mux", "R/R", "AIF2_2RX"},
{"IF2_1 DAC", NULL, "IF2_1 DAC Swap Mux"},
{"IF2_2 DAC", NULL, "IF2_2 DAC Swap Mux"},
{"IF3 DAC Swap Mux", "L/R", "AIF3RX"},
{"IF3 DAC Swap Mux", "R/L", "AIF3RX"},
{"IF3 DAC Swap Mux", "L/L", "AIF3RX"},
{"IF3 DAC Swap Mux", "R/R", "AIF3RX"},
{"IF3 DAC", NULL, "IF3 DAC Swap Mux"},
{"IF1 DAC1", NULL, "I2S1_1"},
{"IF1 DAC2", NULL, "I2S1_1"},
{"IF1 DAC3", NULL, "I2S1_1"},
{"IF2_1 DAC", NULL, "I2S2_1"},
{"IF2_2 DAC", NULL, "I2S2_2"},
{"IF3 DAC", NULL, "I2S3"},
{"IF1 DAC1 L", NULL, "IF1 DAC1"},
{"IF1 DAC1 R", NULL, "IF1 DAC1"},
{"IF1 DAC2 L", NULL, "IF1 DAC2"},
{"IF1 DAC2 R", NULL, "IF1 DAC2"},
{"IF1 DAC3 L", NULL, "IF1 DAC3"},
{"IF1 DAC3 R", NULL, "IF1 DAC3"},
{"IF2_1 DAC L", NULL, "IF2_1 DAC"},
{"IF2_1 DAC R", NULL, "IF2_1 DAC"},
{"IF2_2 DAC L", NULL, "IF2_2 DAC"},
{"IF2_2 DAC R", NULL, "IF2_2 DAC"},
{"IF3 DAC L", NULL, "IF3 DAC"},
{"IF3 DAC R", NULL, "IF3 DAC"},
{"DAC L1 Mux", "IF1 DAC1", "IF1 DAC1 L"},
{"DAC L1 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
{"DAC L1 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
{"DAC L1 Mux", "IF3 DAC", "IF3 DAC L"},
{"DAC L1 Mux", NULL, "DAC Stereo1 Filter"},
{"DAC R1 Mux", "IF1 DAC1", "IF1 DAC1 R"},
{"DAC R1 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
{"DAC R1 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
{"DAC R1 Mux", "IF3 DAC", "IF3 DAC R"},
{"DAC R1 Mux", NULL, "DAC Stereo1 Filter"},
{"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
{"DAC1 MIXL", "DAC1 Switch", "DAC L1 Mux"},
{"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
{"DAC1 MIXR", "DAC1 Switch", "DAC R1 Mux"},
{"DAC1 MIX", NULL, "DAC1 MIXL"},
{"DAC1 MIX", NULL, "DAC1 MIXR"},
{"DAC L2 Mux", "IF1 DAC2", "IF1 DAC2 L"},
{"DAC L2 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
{"DAC L2 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
{"DAC L2 Mux", "IF3 DAC", "IF3 DAC L"},
{"DAC L2 Mux", "Mono ADC MIX", "Mono ADC MIXL"},
{"DAC L2 Mux", NULL, "DAC Mono Left Filter"},
{"DAC R2 Mux", "IF1 DAC2", "IF1 DAC2 R"},
{"DAC R2 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
{"DAC R2 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
{"DAC R2 Mux", "IF3 DAC", "IF3 DAC R"},
{"DAC R2 Mux", "Mono ADC MIX", "Mono ADC MIXR"},
{"DAC R2 Mux", NULL, "DAC Mono Right Filter"},
{"DAC L3 Mux", "IF1 DAC2", "IF1 DAC2 L"},
{"DAC L3 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
{"DAC L3 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
{"DAC L3 Mux", "IF3 DAC", "IF3 DAC L"},
{"DAC L3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXL"},
{"DAC L3 Mux", NULL, "DAC Stereo2 Filter"},
{"DAC R3 Mux", "IF1 DAC2", "IF1 DAC2 R"},
{"DAC R3 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
{"DAC R3 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
{"DAC R3 Mux", "IF3 DAC", "IF3 DAC R"},
{"DAC R3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXR"},
{"DAC R3 Mux", NULL, "DAC Stereo2 Filter"},
{"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
{"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
{"Stereo1 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
{"Stereo1 DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
{"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
{"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
{"Stereo1 DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
{"Stereo1 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
{"Stereo2 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
{"Stereo2 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
{"Stereo2 DAC MIXL", "DAC L3 Switch", "DAC L3 Mux"},
{"Stereo2 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
{"Stereo2 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
{"Stereo2 DAC MIXR", "DAC R3 Switch", "DAC R3 Mux"},
{"Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
{"Mono DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
{"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
{"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
{"Mono DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
{"Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
{"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
{"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
{"DAC MIXL", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
{"DAC MIXL", "Stereo2 DAC Mixer", "Stereo2 DAC MIXL"},
{"DAC MIXL", "Mono DAC Mixer", "Mono DAC MIXL"},
{"DAC MIXR", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
{"DAC MIXR", "Stereo2 DAC Mixer", "Stereo2 DAC MIXR"},
{"DAC MIXR", "Mono DAC Mixer", "Mono DAC MIXR"},
{"DAC L1 Source", "DAC1", "DAC1 MIXL"},
{"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
{"DAC L1 Source", "DMIC1", "DMIC L1"},
{"DAC R1 Source", "DAC1", "DAC1 MIXR"},
{"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
{"DAC R1 Source", "DMIC1", "DMIC R1"},
{"DAC L2 Source", "DAC2", "DAC L2 Mux"},
{"DAC L2 Source", "Mono DAC Mixer", "Mono DAC MIXL"},
{"DAC L2 Source", NULL, "DAC L2 Power"},
{"DAC R2 Source", "DAC2", "DAC R2 Mux"},
{"DAC R2 Source", "Mono DAC Mixer", "Mono DAC MIXR"},
{"DAC R2 Source", NULL, "DAC R2 Power"},
{"DAC L1", NULL, "DAC L1 Source"},
{"DAC R1", NULL, "DAC R1 Source"},
{"DAC L2", NULL, "DAC L2 Source"},
{"DAC R2", NULL, "DAC R2 Source"},
{"DAC L1", NULL, "DAC 1 Clock"},
{"DAC R1", NULL, "DAC 1 Clock"},
{"DAC L2", NULL, "DAC 2 Clock"},
{"DAC R2", NULL, "DAC 2 Clock"},
{"MONOVOL MIX", "DAC L2 Switch", "DAC L2"},
{"MONOVOL MIX", "RECMIX2L Switch", "RECMIX2L"},
{"MONOVOL MIX", "BST1 Switch", "BST1"},
{"MONOVOL MIX", "BST2 Switch", "BST2"},
{"MONOVOL MIX", "BST3 Switch", "BST3"},
{"OUT MIXL", "DAC L2 Switch", "DAC L2"},
{"OUT MIXL", "INL Switch", "INL VOL"},
{"OUT MIXL", "BST1 Switch", "BST1"},
{"OUT MIXL", "BST2 Switch", "BST2"},
{"OUT MIXL", "BST3 Switch", "BST3"},
{"OUT MIXR", "DAC R2 Switch", "DAC R2"},
{"OUT MIXR", "INR Switch", "INR VOL"},
{"OUT MIXR", "BST2 Switch", "BST2"},
{"OUT MIXR", "BST3 Switch", "BST3"},
{"OUT MIXR", "BST4 Switch", "BST4"},
{"MONOVOL", "Switch", "MONOVOL MIX"},
{"Mono MIX", "DAC L2 Switch", "DAC L2"},
{"Mono MIX", "MONOVOL Switch", "MONOVOL"},
{"Mono Amp", NULL, "Mono MIX"},
{"Mono Amp", NULL, "Vref2"},
{"Mono Amp", NULL, "Vref3"},
{"Mono Amp", NULL, "CLKDET SYS"},
{"Mono Amp", NULL, "CLKDET MONO"},
{"Mono Playback", "Switch", "Mono Amp"},
{"MONOOUT", NULL, "Mono Playback"},
{"HP Amp", NULL, "DAC L1"},
{"HP Amp", NULL, "DAC R1"},
{"HP Amp", NULL, "Charge Pump"},
{"HP Amp", NULL, "CLKDET SYS"},
{"HP Amp", NULL, "CLKDET HP"},
{"HP Amp", NULL, "CBJ Power"},
{"HP Amp", NULL, "Vref2"},
{"HPO Playback", "Switch", "HP Amp"},
{"HPOL", NULL, "HPO Playback"},
{"HPOR", NULL, "HPO Playback"},
{"OUTVOL L", "Switch", "OUT MIXL"},
{"OUTVOL R", "Switch", "OUT MIXR"},
{"LOUT L MIX", "DAC L2 Switch", "DAC L2"},
{"LOUT L MIX", "OUTVOL L Switch", "OUTVOL L"},
{"LOUT R MIX", "DAC R2 Switch", "DAC R2"},
{"LOUT R MIX", "OUTVOL R Switch", "OUTVOL R"},
{"LOUT Amp", NULL, "LOUT L MIX"},
{"LOUT Amp", NULL, "LOUT R MIX"},
{"LOUT Amp", NULL, "Vref1"},
{"LOUT Amp", NULL, "Vref2"},
{"LOUT Amp", NULL, "CLKDET SYS"},
{"LOUT Amp", NULL, "CLKDET LOUT"},
{"LOUT L Playback", "Switch", "LOUT Amp"},
{"LOUT R Playback", "Switch", "LOUT Amp"},
{"LOUTL", NULL, "LOUT L Playback"},
{"LOUTR", NULL, "LOUT R Playback"},
{"PDM L Mux", "Mono DAC", "Mono DAC MIXL"},
{"PDM L Mux", "Stereo1 DAC", "Stereo1 DAC MIXL"},
{"PDM L Mux", "Stereo2 DAC", "Stereo2 DAC MIXL"},
{"PDM L Mux", NULL, "PDM Power"},
{"PDM R Mux", "Mono DAC", "Mono DAC MIXR"},
{"PDM R Mux", "Stereo1 DAC", "Stereo1 DAC MIXR"},
{"PDM R Mux", "Stereo2 DAC", "Stereo2 DAC MIXR"},
{"PDM R Mux", NULL, "PDM Power"},
{"PDM L Playback", "Switch", "PDM L Mux"},
{"PDM R Playback", "Switch", "PDM R Mux"},
{"PDML", NULL, "PDM L Playback"},
{"PDMR", NULL, "PDM R Playback"},
};
static int rt5665_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
unsigned int val = 0;
if (rx_mask || tx_mask)
val |= RT5665_I2S1_MODE_TDM;
switch (slots) {
case 4:
val |= RT5665_TDM_IN_CH_4;
val |= RT5665_TDM_OUT_CH_4;
break;
case 6:
val |= RT5665_TDM_IN_CH_6;
val |= RT5665_TDM_OUT_CH_6;
break;
case 8:
val |= RT5665_TDM_IN_CH_8;
val |= RT5665_TDM_OUT_CH_8;
break;
case 2:
break;
default:
return -EINVAL;
}
switch (slot_width) {
case 20:
val |= RT5665_TDM_IN_LEN_20;
val |= RT5665_TDM_OUT_LEN_20;
break;
case 24:
val |= RT5665_TDM_IN_LEN_24;
val |= RT5665_TDM_OUT_LEN_24;
break;
case 32:
val |= RT5665_TDM_IN_LEN_32;
val |= RT5665_TDM_OUT_LEN_32;
break;
case 16:
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, RT5665_TDM_CTRL_1,
RT5665_I2S1_MODE_MASK | RT5665_TDM_IN_CH_MASK |
RT5665_TDM_OUT_CH_MASK | RT5665_TDM_IN_LEN_MASK |
RT5665_TDM_OUT_LEN_MASK, val);
return 0;
}
static int rt5665_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
unsigned int val_len = 0, val_clk, reg_clk, mask_clk, val_bits = 0x0100;
int pre_div, frame_size;
rt5665->lrck[dai->id] = params_rate(params);
pre_div = rl6231_get_clk_info(rt5665->sysclk, rt5665->lrck[dai->id]);
if (pre_div < 0) {
dev_warn(component->dev, "Force using PLL");
snd_soc_component_set_pll(component, 0, RT5665_PLL1_S_MCLK,
rt5665->sysclk, rt5665->lrck[dai->id] * 512);
snd_soc_component_set_sysclk(component, RT5665_SCLK_S_PLL1, 0,
rt5665->lrck[dai->id] * 512, 0);
pre_div = 1;
}
frame_size = snd_soc_params_to_frame_size(params);
if (frame_size < 0) {
dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
return -EINVAL;
}
dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
rt5665->lrck[dai->id], pre_div, dai->id);
switch (params_width(params)) {
case 16:
val_bits = 0x0100;
break;
case 20:
val_len |= RT5665_I2S_DL_20;
val_bits = 0x1300;
break;
case 24:
val_len |= RT5665_I2S_DL_24;
val_bits = 0x2500;
break;
case 8:
val_len |= RT5665_I2S_DL_8;
break;
default:
return -EINVAL;
}
switch (dai->id) {
case RT5665_AIF1_1:
case RT5665_AIF1_2:
if (params_channels(params) > 2)
rt5665_set_tdm_slot(dai, 0xf, 0xf,
params_channels(params), params_width(params));
reg_clk = RT5665_ADDA_CLK_1;
mask_clk = RT5665_I2S_PD1_MASK;
val_clk = pre_div << RT5665_I2S_PD1_SFT;
snd_soc_component_update_bits(component, RT5665_I2S1_SDP,
RT5665_I2S_DL_MASK, val_len);
break;
case RT5665_AIF2_1:
case RT5665_AIF2_2:
reg_clk = RT5665_ADDA_CLK_2;
mask_clk = RT5665_I2S_PD2_MASK;
val_clk = pre_div << RT5665_I2S_PD2_SFT;
snd_soc_component_update_bits(component, RT5665_I2S2_SDP,
RT5665_I2S_DL_MASK, val_len);
break;
case RT5665_AIF3:
reg_clk = RT5665_ADDA_CLK_2;
mask_clk = RT5665_I2S_PD3_MASK;
val_clk = pre_div << RT5665_I2S_PD3_SFT;
snd_soc_component_update_bits(component, RT5665_I2S3_SDP,
RT5665_I2S_DL_MASK, val_len);
break;
default:
dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
return -EINVAL;
}
snd_soc_component_update_bits(component, reg_clk, mask_clk, val_clk);
snd_soc_component_update_bits(component, RT5665_STO1_DAC_SIL_DET, 0x3700, val_bits);
switch (rt5665->lrck[dai->id]) {
case 192000:
snd_soc_component_update_bits(component, RT5665_ADDA_CLK_1,
RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
RT5665_DAC_OSR_32 | RT5665_ADC_OSR_32);
break;
case 96000:
snd_soc_component_update_bits(component, RT5665_ADDA_CLK_1,
RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
RT5665_DAC_OSR_64 | RT5665_ADC_OSR_64);
break;
default:
snd_soc_component_update_bits(component, RT5665_ADDA_CLK_1,
RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
RT5665_DAC_OSR_128 | RT5665_ADC_OSR_128);
break;
}
if (rt5665->master[RT5665_AIF2_1] || rt5665->master[RT5665_AIF2_2]) {
snd_soc_component_update_bits(component, RT5665_I2S_M_CLK_CTRL_1,
RT5665_I2S2_M_PD_MASK, pre_div << RT5665_I2S2_M_PD_SFT);
}
if (rt5665->master[RT5665_AIF3]) {
snd_soc_component_update_bits(component, RT5665_I2S_M_CLK_CTRL_1,
RT5665_I2S3_M_PD_MASK, pre_div << RT5665_I2S3_M_PD_SFT);
}
return 0;
}
static int rt5665_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
rt5665->master[dai->id] = 1;
break;
case SND_SOC_DAIFMT_CBS_CFS:
reg_val |= RT5665_I2S_MS_S;
rt5665->master[dai->id] = 0;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
reg_val |= RT5665_I2S_BP_INV;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_LEFT_J:
reg_val |= RT5665_I2S_DF_LEFT;
break;
case SND_SOC_DAIFMT_DSP_A:
reg_val |= RT5665_I2S_DF_PCM_A;
break;
case SND_SOC_DAIFMT_DSP_B:
reg_val |= RT5665_I2S_DF_PCM_B;
break;
default:
return -EINVAL;
}
switch (dai->id) {
case RT5665_AIF1_1:
case RT5665_AIF1_2:
snd_soc_component_update_bits(component, RT5665_I2S1_SDP,
RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
RT5665_I2S_DF_MASK, reg_val);
break;
case RT5665_AIF2_1:
case RT5665_AIF2_2:
snd_soc_component_update_bits(component, RT5665_I2S2_SDP,
RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
RT5665_I2S_DF_MASK, reg_val);
break;
case RT5665_AIF3:
snd_soc_component_update_bits(component, RT5665_I2S3_SDP,
RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
RT5665_I2S_DF_MASK, reg_val);
break;
default:
dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
return -EINVAL;
}
return 0;
}
static int rt5665_set_component_sysclk(struct snd_soc_component *component, int clk_id,
int source, unsigned int freq, int dir)
{
struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0, src = 0;
if (freq == rt5665->sysclk && clk_id == rt5665->sysclk_src)
return 0;
switch (clk_id) {
case RT5665_SCLK_S_MCLK:
reg_val |= RT5665_SCLK_SRC_MCLK;
src = RT5665_CLK_SRC_MCLK;
break;
case RT5665_SCLK_S_PLL1:
reg_val |= RT5665_SCLK_SRC_PLL1;
src = RT5665_CLK_SRC_PLL1;
break;
case RT5665_SCLK_S_RCCLK:
reg_val |= RT5665_SCLK_SRC_RCCLK;
src = RT5665_CLK_SRC_RCCLK;
break;
default:
dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
return -EINVAL;
}
snd_soc_component_update_bits(component, RT5665_GLB_CLK,
RT5665_SCLK_SRC_MASK, reg_val);
if (rt5665->master[RT5665_AIF2_1] || rt5665->master[RT5665_AIF2_2]) {
snd_soc_component_update_bits(component, RT5665_I2S_M_CLK_CTRL_1,
RT5665_I2S2_SRC_MASK, src << RT5665_I2S2_SRC_SFT);
}
if (rt5665->master[RT5665_AIF3]) {
snd_soc_component_update_bits(component, RT5665_I2S_M_CLK_CTRL_1,
RT5665_I2S3_SRC_MASK, src << RT5665_I2S3_SRC_SFT);
}
rt5665->sysclk = freq;
rt5665->sysclk_src = clk_id;
dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
return 0;
}
static int rt5665_set_component_pll(struct snd_soc_component *component, int pll_id,
int source, unsigned int freq_in,
unsigned int freq_out)
{
struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
struct rl6231_pll_code pll_code;
int ret;
if (source == rt5665->pll_src && freq_in == rt5665->pll_in &&
freq_out == rt5665->pll_out)
return 0;
if (!freq_in || !freq_out) {
dev_dbg(component->dev, "PLL disabled\n");
rt5665->pll_in = 0;
rt5665->pll_out = 0;
snd_soc_component_update_bits(component, RT5665_GLB_CLK,
RT5665_SCLK_SRC_MASK, RT5665_SCLK_SRC_MCLK);
return 0;
}
switch (source) {
case RT5665_PLL1_S_MCLK:
snd_soc_component_update_bits(component, RT5665_GLB_CLK,
RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_MCLK);
break;
case RT5665_PLL1_S_BCLK1:
snd_soc_component_update_bits(component, RT5665_GLB_CLK,
RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK1);
break;
case RT5665_PLL1_S_BCLK2:
snd_soc_component_update_bits(component, RT5665_GLB_CLK,
RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK2);
break;
case RT5665_PLL1_S_BCLK3:
snd_soc_component_update_bits(component, RT5665_GLB_CLK,
RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK3);
break;
default:
dev_err(component->dev, "Unknown PLL Source %d\n", source);
return -EINVAL;
}
ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
if (ret < 0) {
dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
return ret;
}
dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
pll_code.n_code, pll_code.k_code);
snd_soc_component_write(component, RT5665_PLL_CTRL_1,
pll_code.n_code << RT5665_PLL_N_SFT | pll_code.k_code);
snd_soc_component_write(component, RT5665_PLL_CTRL_2,
((pll_code.m_bp ? 0 : pll_code.m_code) << RT5665_PLL_M_SFT) |
(pll_code.m_bp << RT5665_PLL_M_BP_SFT));
rt5665->pll_in = freq_in;
rt5665->pll_out = freq_out;
rt5665->pll_src = source;
return 0;
}
static int rt5665_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
{
struct snd_soc_component *component = dai->component;
struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio);
rt5665->bclk[dai->id] = ratio;
if (ratio == 64) {
switch (dai->id) {
case RT5665_AIF2_1:
case RT5665_AIF2_2:
snd_soc_component_update_bits(component, RT5665_ADDA_CLK_2,
RT5665_I2S_BCLK_MS2_MASK,
RT5665_I2S_BCLK_MS2_64);
break;
case RT5665_AIF3:
snd_soc_component_update_bits(component, RT5665_ADDA_CLK_2,
RT5665_I2S_BCLK_MS3_MASK,
RT5665_I2S_BCLK_MS3_64);
break;
}
}
return 0;
}
static int rt5665_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_PREPARE:
regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC,
RT5665_DIG_GATE_CTRL, RT5665_DIG_GATE_CTRL);
break;
case SND_SOC_BIAS_STANDBY:
regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1,
RT5665_PWR_LDO, RT5665_PWR_LDO);
regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
RT5665_PWR_MB, RT5665_PWR_MB);
regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC,
RT5665_DIG_GATE_CTRL, 0);
break;
case SND_SOC_BIAS_OFF:
regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1,
RT5665_PWR_LDO, 0);
regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
RT5665_PWR_MB, 0);
break;
default:
break;
}
return 0;
}
static int rt5665_probe(struct snd_soc_component *component)
{
struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
rt5665->component = component;
schedule_delayed_work(&rt5665->calibrate_work, msecs_to_jiffies(100));
return 0;
}
static void rt5665_remove(struct snd_soc_component *component)
{
struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
regmap_write(rt5665->regmap, RT5665_RESET, 0);
regulator_bulk_disable(ARRAY_SIZE(rt5665->supplies), rt5665->supplies);
}
#ifdef CONFIG_PM
static int rt5665_suspend(struct snd_soc_component *component)
{
struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
regcache_cache_only(rt5665->regmap, true);
regcache_mark_dirty(rt5665->regmap);
return 0;
}
static int rt5665_resume(struct snd_soc_component *component)
{
struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
regcache_cache_only(rt5665->regmap, false);
regcache_sync(rt5665->regmap);
return 0;
}
#else
#define rt5665_suspend NULL
#define rt5665_resume NULL
#endif
#define RT5665_STEREO_RATES SNDRV_PCM_RATE_8000_192000
#define RT5665_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
static const struct snd_soc_dai_ops rt5665_aif_dai_ops = {
.hw_params = rt5665_hw_params,
.set_fmt = rt5665_set_dai_fmt,
.set_tdm_slot = rt5665_set_tdm_slot,
.set_bclk_ratio = rt5665_set_bclk_ratio,
};
static struct snd_soc_dai_driver rt5665_dai[] = {
{
.name = "rt5665-aif1_1",
.id = RT5665_AIF1_1,
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 8,
.rates = RT5665_STEREO_RATES,
.formats = RT5665_FORMATS,
},
.capture = {
.stream_name = "AIF1_1 Capture",
.channels_min = 1,
.channels_max = 8,
.rates = RT5665_STEREO_RATES,
.formats = RT5665_FORMATS,
},
.ops = &rt5665_aif_dai_ops,
},
{
.name = "rt5665-aif1_2",
.id = RT5665_AIF1_2,
.capture = {
.stream_name = "AIF1_2 Capture",
.channels_min = 1,
.channels_max = 8,
.rates = RT5665_STEREO_RATES,
.formats = RT5665_FORMATS,
},
.ops = &rt5665_aif_dai_ops,
},
{
.name = "rt5665-aif2_1",
.id = RT5665_AIF2_1,
.playback = {
.stream_name = "AIF2_1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT5665_STEREO_RATES,
.formats = RT5665_FORMATS,
},
.capture = {
.stream_name = "AIF2_1 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT5665_STEREO_RATES,
.formats = RT5665_FORMATS,
},
.ops = &rt5665_aif_dai_ops,
},
{
.name = "rt5665-aif2_2",
.id = RT5665_AIF2_2,
.playback = {
.stream_name = "AIF2_2 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT5665_STEREO_RATES,
.formats = RT5665_FORMATS,
},
.capture = {
.stream_name = "AIF2_2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT5665_STEREO_RATES,
.formats = RT5665_FORMATS,
},
.ops = &rt5665_aif_dai_ops,
},
{
.name = "rt5665-aif3",
.id = RT5665_AIF3,
.playback = {
.stream_name = "AIF3 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT5665_STEREO_RATES,
.formats = RT5665_FORMATS,
},
.capture = {
.stream_name = "AIF3 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT5665_STEREO_RATES,
.formats = RT5665_FORMATS,
},
.ops = &rt5665_aif_dai_ops,
},
};
static const struct snd_soc_component_driver soc_component_dev_rt5665 = {
.probe = rt5665_probe,
.remove = rt5665_remove,
.suspend = rt5665_suspend,
.resume = rt5665_resume,
.set_bias_level = rt5665_set_bias_level,
.controls = rt5665_snd_controls,
.num_controls = ARRAY_SIZE(rt5665_snd_controls),
.dapm_widgets = rt5665_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt5665_dapm_widgets),
.dapm_routes = rt5665_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(rt5665_dapm_routes),
.set_sysclk = rt5665_set_component_sysclk,
.set_pll = rt5665_set_component_pll,
.set_jack = rt5665_set_jack_detect,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config rt5665_regmap = {
.reg_bits = 16,
.val_bits = 16,
.max_register = 0x0400,
.volatile_reg = rt5665_volatile_register,
.readable_reg = rt5665_readable_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = rt5665_reg,
.num_reg_defaults = ARRAY_SIZE(rt5665_reg),
.use_single_read = true,
.use_single_write = true,
};
static const struct i2c_device_id rt5665_i2c_id[] = {
{"rt5665", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, rt5665_i2c_id);
static int rt5665_parse_dt(struct rt5665_priv *rt5665, struct device *dev)
{
rt5665->pdata.in1_diff = of_property_read_bool(dev->of_node,
"realtek,in1-differential");
rt5665->pdata.in2_diff = of_property_read_bool(dev->of_node,
"realtek,in2-differential");
rt5665->pdata.in3_diff = of_property_read_bool(dev->of_node,
"realtek,in3-differential");
rt5665->pdata.in4_diff = of_property_read_bool(dev->of_node,
"realtek,in4-differential");
of_property_read_u32(dev->of_node, "realtek,dmic1-data-pin",
&rt5665->pdata.dmic1_data_pin);
of_property_read_u32(dev->of_node, "realtek,dmic2-data-pin",
&rt5665->pdata.dmic2_data_pin);
of_property_read_u32(dev->of_node, "realtek,jd-src",
&rt5665->pdata.jd_src);
return 0;
}
static void rt5665_calibrate(struct rt5665_priv *rt5665)
{
int value, count;
mutex_lock(&rt5665->calibrate_mutex);
regcache_cache_bypass(rt5665->regmap, true);
regmap_write(rt5665->regmap, RT5665_RESET, 0);
regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602);
regmap_write(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1, 0x0c26);
regmap_write(rt5665->regmap, RT5665_MONOMIX_IN_GAIN, 0x021f);
regmap_write(rt5665->regmap, RT5665_MONO_OUT, 0x480a);
regmap_write(rt5665->regmap, RT5665_PWR_MIXER, 0x083f);
regmap_write(rt5665->regmap, RT5665_PWR_DIG_1, 0x0180);
regmap_write(rt5665->regmap, RT5665_EJD_CTRL_1, 0x4040);
regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0000);
regmap_write(rt5665->regmap, RT5665_DIG_MISC, 0x0001);
regmap_write(rt5665->regmap, RT5665_MICBIAS_2, 0x0380);
regmap_write(rt5665->regmap, RT5665_GLB_CLK, 0x8000);
regmap_write(rt5665->regmap, RT5665_ADDA_CLK_1, 0x1000);
regmap_write(rt5665->regmap, RT5665_CHOP_DAC, 0x3030);
regmap_write(rt5665->regmap, RT5665_CALIB_ADC_CTRL, 0x3c05);
regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xaa3e);
usleep_range(15000, 20000);
regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xfe7e);
regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_2, 0x0321);
regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_1, 0xfc00);
count = 0;
while (true) {
regmap_read(rt5665->regmap, RT5665_HP_CALIB_STA_1, &value);
if (value & 0x8000)
usleep_range(10000, 10005);
else
break;
if (count > 60) {
pr_err("HP Calibration Failure\n");
regmap_write(rt5665->regmap, RT5665_RESET, 0);
regcache_cache_bypass(rt5665->regmap, false);
goto out_unlock;
}
count++;
}
regmap_write(rt5665->regmap, RT5665_MONO_AMP_CALIB_CTRL_1, 0x9e24);
count = 0;
while (true) {
regmap_read(rt5665->regmap, RT5665_MONO_AMP_CALIB_STA1, &value);
if (value & 0x8000)
usleep_range(10000, 10005);
else
break;
if (count > 60) {
pr_err("MONO Calibration Failure\n");
regmap_write(rt5665->regmap, RT5665_RESET, 0);
regcache_cache_bypass(rt5665->regmap, false);
goto out_unlock;
}
count++;
}
regmap_write(rt5665->regmap, RT5665_RESET, 0);
regcache_cache_bypass(rt5665->regmap, false);
regcache_mark_dirty(rt5665->regmap);
regcache_sync(rt5665->regmap);
regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602);
regmap_write(rt5665->regmap, RT5665_ASRC_8, 0x0120);
out_unlock:
rt5665->calibration_done = true;
mutex_unlock(&rt5665->calibrate_mutex);
}
static void rt5665_calibrate_handler(struct work_struct *work)
{
struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv,
calibrate_work.work);
while (!snd_soc_card_is_instantiated(rt5665->component->card)) {
pr_debug("%s\n", __func__);
usleep_range(10000, 15000);
}
rt5665_calibrate(rt5665);
}
static int rt5665_i2c_probe(struct i2c_client *i2c)
{
struct rt5665_platform_data *pdata = dev_get_platdata(&i2c->dev);
struct rt5665_priv *rt5665;
int i, ret;
unsigned int val;
rt5665 = devm_kzalloc(&i2c->dev, sizeof(struct rt5665_priv),
GFP_KERNEL);
if (rt5665 == NULL)
return -ENOMEM;
i2c_set_clientdata(i2c, rt5665);
if (pdata)
rt5665->pdata = *pdata;
else
rt5665_parse_dt(rt5665, &i2c->dev);
for (i = 0; i < ARRAY_SIZE(rt5665->supplies); i++)
rt5665->supplies[i].supply = rt5665_supply_names[i];
ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5665->supplies),
rt5665->supplies);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
return ret;
}
ret = regulator_bulk_enable(ARRAY_SIZE(rt5665->supplies),
rt5665->supplies);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
return ret;
}
rt5665->gpiod_ldo1_en = devm_gpiod_get_optional(&i2c->dev,
"realtek,ldo1-en",
GPIOD_OUT_HIGH);
if (IS_ERR(rt5665->gpiod_ldo1_en)) {
dev_err(&i2c->dev, "Failed gpio request ldo1_en\n");
return PTR_ERR(rt5665->gpiod_ldo1_en);
}
/* Sleep for 300 ms miniumum */
usleep_range(300000, 350000);
rt5665->regmap = devm_regmap_init_i2c(i2c, &rt5665_regmap);
if (IS_ERR(rt5665->regmap)) {
ret = PTR_ERR(rt5665->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
regmap_read(rt5665->regmap, RT5665_DEVICE_ID, &val);
if (val != DEVICE_ID) {
dev_err(&i2c->dev,
"Device with ID register %x is not rt5665\n", val);
return -ENODEV;
}
regmap_read(rt5665->regmap, RT5665_RESET, &val);
switch (val) {
case 0x0:
rt5665->id = CODEC_5666;
break;
case 0x3:
default:
rt5665->id = CODEC_5665;
break;
}
regmap_write(rt5665->regmap, RT5665_RESET, 0);
/* line in diff mode*/
if (rt5665->pdata.in1_diff)
regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2,
RT5665_IN1_DF_MASK, RT5665_IN1_DF_MASK);
if (rt5665->pdata.in2_diff)
regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2,
RT5665_IN2_DF_MASK, RT5665_IN2_DF_MASK);
if (rt5665->pdata.in3_diff)
regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4,
RT5665_IN3_DF_MASK, RT5665_IN3_DF_MASK);
if (rt5665->pdata.in4_diff)
regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4,
RT5665_IN4_DF_MASK, RT5665_IN4_DF_MASK);
/* DMIC pin*/
if (rt5665->pdata.dmic1_data_pin != RT5665_DMIC1_NULL ||
rt5665->pdata.dmic2_data_pin != RT5665_DMIC2_NULL) {
regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2,
RT5665_GP9_PIN_MASK, RT5665_GP9_PIN_DMIC1_SCL);
regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
RT5665_GP8_PIN_MASK, RT5665_GP8_PIN_DMIC2_SCL);
switch (rt5665->pdata.dmic1_data_pin) {
case RT5665_DMIC1_DATA_IN2N:
regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_IN2N);
break;
case RT5665_DMIC1_DATA_GPIO4:
regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_GPIO4);
regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
RT5665_GP4_PIN_MASK, RT5665_GP4_PIN_DMIC1_SDA);
break;
default:
dev_dbg(&i2c->dev, "no DMIC1\n");
break;
}
switch (rt5665->pdata.dmic2_data_pin) {
case RT5665_DMIC2_DATA_IN2P:
regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
RT5665_DMIC_2_DP_MASK, RT5665_DMIC_2_DP_IN2P);
break;
case RT5665_DMIC2_DATA_GPIO5:
regmap_update_bits(rt5665->regmap,
RT5665_DMIC_CTRL_1,
RT5665_DMIC_2_DP_MASK,
RT5665_DMIC_2_DP_GPIO5);
regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
RT5665_GP5_PIN_MASK, RT5665_GP5_PIN_DMIC2_SDA);
break;
default:
dev_dbg(&i2c->dev, "no DMIC2\n");
break;
}
}
regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0002);
regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
0xf000 | RT5665_VREF_POW_MASK, 0xe000 | RT5665_VREF_POW_REG);
/* Work around for pow_pump */
regmap_update_bits(rt5665->regmap, RT5665_STO1_DAC_SIL_DET,
RT5665_DEB_STO_DAC_MASK, RT5665_DEB_80_MS);
regmap_update_bits(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1,
RT5665_PM_HP_MASK, RT5665_PM_HP_HV);
/* Set GPIO4,8 as input for combo jack */
if (rt5665->id == CODEC_5666) {
regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2,
RT5665_GP4_PF_MASK, RT5665_GP4_PF_IN);
regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_3,
RT5665_GP8_PF_MASK, RT5665_GP8_PF_IN);
}
/* Enhance performance*/
regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
RT5665_HP_DRIVER_MASK | RT5665_LDO1_DVO_MASK,
RT5665_HP_DRIVER_5X | RT5665_LDO1_DVO_12);
INIT_DELAYED_WORK(&rt5665->jack_detect_work,
rt5665_jack_detect_handler);
INIT_DELAYED_WORK(&rt5665->calibrate_work,
rt5665_calibrate_handler);
INIT_DELAYED_WORK(&rt5665->jd_check_work,
rt5665_jd_check_handler);
mutex_init(&rt5665->calibrate_mutex);
if (i2c->irq) {
ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
rt5665_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
| IRQF_ONESHOT, "rt5665", rt5665);
if (ret)
dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
}
return devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_rt5665,
rt5665_dai, ARRAY_SIZE(rt5665_dai));
}
static void rt5665_i2c_shutdown(struct i2c_client *client)
{
struct rt5665_priv *rt5665 = i2c_get_clientdata(client);
regmap_write(rt5665->regmap, RT5665_RESET, 0);
}
#ifdef CONFIG_OF
static const struct of_device_id rt5665_of_match[] = {
{.compatible = "realtek,rt5665"},
{.compatible = "realtek,rt5666"},
{},
};
MODULE_DEVICE_TABLE(of, rt5665_of_match);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id rt5665_acpi_match[] = {
{"10EC5665", 0,},
{"10EC5666", 0,},
{},
};
MODULE_DEVICE_TABLE(acpi, rt5665_acpi_match);
#endif
static struct i2c_driver rt5665_i2c_driver = {
.driver = {
.name = "rt5665",
.of_match_table = of_match_ptr(rt5665_of_match),
.acpi_match_table = ACPI_PTR(rt5665_acpi_match),
},
.probe = rt5665_i2c_probe,
.shutdown = rt5665_i2c_shutdown,
.id_table = rt5665_i2c_id,
};
module_i2c_driver(rt5665_i2c_driver);
MODULE_DESCRIPTION("ASoC RT5665 driver");
MODULE_AUTHOR("Bard Liao <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/rt5665.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* rt274.c -- RT274 ALSA SoC audio codec driver
*
* Copyright 2017 Realtek Semiconductor Corp.
* Author: Bard Liao <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/dmi.h>
#include <linux/acpi.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/jack.h>
#include <linux/workqueue.h>
#include "rl6347a.h"
#include "rt274.h"
#define RT274_VENDOR_ID 0x10ec0274
struct rt274_priv {
struct reg_default *index_cache;
int index_cache_size;
struct regmap *regmap;
struct snd_soc_component *component;
struct i2c_client *i2c;
struct snd_soc_jack *jack;
struct delayed_work jack_detect_work;
int sys_clk;
int clk_id;
int fs;
bool master;
};
static const struct reg_default rt274_index_def[] = {
{ 0x00, 0x1004 },
{ 0x01, 0xaaaa },
{ 0x02, 0x88aa },
{ 0x03, 0x0002 },
{ 0x04, 0xaa09 },
{ 0x05, 0x0700 },
{ 0x06, 0x6110 },
{ 0x07, 0x0200 },
{ 0x08, 0xa807 },
{ 0x09, 0x0021 },
{ 0x0a, 0x7770 },
{ 0x0b, 0x7770 },
{ 0x0c, 0x002b },
{ 0x0d, 0x2420 },
{ 0x0e, 0x65c0 },
{ 0x0f, 0x7770 },
{ 0x10, 0x0420 },
{ 0x11, 0x7418 },
{ 0x12, 0x6bd0 },
{ 0x13, 0x645f },
{ 0x14, 0x0400 },
{ 0x15, 0x8ccc },
{ 0x16, 0x4c50 },
{ 0x17, 0xff00 },
{ 0x18, 0x0003 },
{ 0x19, 0x2c11 },
{ 0x1a, 0x830b },
{ 0x1b, 0x4e4b },
{ 0x1c, 0x0000 },
{ 0x1d, 0x0000 },
{ 0x1e, 0x0000 },
{ 0x1f, 0x0000 },
{ 0x20, 0x51ff },
{ 0x21, 0x8000 },
{ 0x22, 0x8f00 },
{ 0x23, 0x88f4 },
{ 0x24, 0x0000 },
{ 0x25, 0x0000 },
{ 0x26, 0x0000 },
{ 0x27, 0x0000 },
{ 0x28, 0x0000 },
{ 0x29, 0x3000 },
{ 0x2a, 0x0000 },
{ 0x2b, 0x0000 },
{ 0x2c, 0x0f00 },
{ 0x2d, 0x100f },
{ 0x2e, 0x2902 },
{ 0x2f, 0xe280 },
{ 0x30, 0x1000 },
{ 0x31, 0x8400 },
{ 0x32, 0x5aaa },
{ 0x33, 0x8420 },
{ 0x34, 0xa20c },
{ 0x35, 0x096a },
{ 0x36, 0x5757 },
{ 0x37, 0xfe05 },
{ 0x38, 0x4901 },
{ 0x39, 0x110a },
{ 0x3a, 0x0010 },
{ 0x3b, 0x60d9 },
{ 0x3c, 0xf214 },
{ 0x3d, 0xc2ba },
{ 0x3e, 0xa928 },
{ 0x3f, 0x0000 },
{ 0x40, 0x9800 },
{ 0x41, 0x0000 },
{ 0x42, 0x2000 },
{ 0x43, 0x3d90 },
{ 0x44, 0x4900 },
{ 0x45, 0x5289 },
{ 0x46, 0x0004 },
{ 0x47, 0xa47a },
{ 0x48, 0xd049 },
{ 0x49, 0x0049 },
{ 0x4a, 0xa83b },
{ 0x4b, 0x0777 },
{ 0x4c, 0x065c },
{ 0x4d, 0x7fff },
{ 0x4e, 0x7fff },
{ 0x4f, 0x0000 },
{ 0x50, 0x0000 },
{ 0x51, 0x0000 },
{ 0x52, 0xbf5f },
{ 0x53, 0x3320 },
{ 0x54, 0xcc00 },
{ 0x55, 0x0000 },
{ 0x56, 0x3f00 },
{ 0x57, 0x0000 },
{ 0x58, 0x0000 },
{ 0x59, 0x0000 },
{ 0x5a, 0x1300 },
{ 0x5b, 0x005f },
{ 0x5c, 0x0000 },
{ 0x5d, 0x1001 },
{ 0x5e, 0x1000 },
{ 0x5f, 0x0000 },
{ 0x60, 0x5554 },
{ 0x61, 0xffc0 },
{ 0x62, 0xa000 },
{ 0x63, 0xd010 },
{ 0x64, 0x0000 },
{ 0x65, 0x3fb1 },
{ 0x66, 0x1881 },
{ 0x67, 0xc810 },
{ 0x68, 0x2000 },
{ 0x69, 0xfff0 },
{ 0x6a, 0x0300 },
{ 0x6b, 0x5060 },
{ 0x6c, 0x0000 },
{ 0x6d, 0x0000 },
{ 0x6e, 0x0c25 },
{ 0x6f, 0x0c0b },
{ 0x70, 0x8000 },
{ 0x71, 0x4008 },
{ 0x72, 0x0000 },
{ 0x73, 0x0800 },
{ 0x74, 0xa28f },
{ 0x75, 0xa050 },
{ 0x76, 0x7fe8 },
{ 0x77, 0xdb8c },
{ 0x78, 0x0000 },
{ 0x79, 0x0000 },
{ 0x7a, 0x2a96 },
{ 0x7b, 0x800f },
{ 0x7c, 0x0200 },
{ 0x7d, 0x1600 },
{ 0x7e, 0x0000 },
{ 0x7f, 0x0000 },
};
#define INDEX_CACHE_SIZE ARRAY_SIZE(rt274_index_def)
static const struct reg_default rt274_reg[] = {
{ 0x00170500, 0x00000400 },
{ 0x00220000, 0x00000031 },
{ 0x00239000, 0x00000057 },
{ 0x0023a000, 0x00000057 },
{ 0x00270500, 0x00000400 },
{ 0x00370500, 0x00000400 },
{ 0x00870500, 0x00000400 },
{ 0x00920000, 0x00000031 },
{ 0x00935000, 0x00000097 },
{ 0x00936000, 0x00000097 },
{ 0x00970500, 0x00000400 },
{ 0x00b37000, 0x00000400 },
{ 0x00b37200, 0x00000400 },
{ 0x00b37300, 0x00000400 },
{ 0x00c37000, 0x00000400 },
{ 0x00c37100, 0x00000400 },
{ 0x01270500, 0x00000400 },
{ 0x01370500, 0x00000400 },
{ 0x01371f00, 0x411111f0 },
{ 0x01937000, 0x00000000 },
{ 0x01970500, 0x00000400 },
{ 0x02050000, 0x0000001b },
{ 0x02139000, 0x00000080 },
{ 0x0213a000, 0x00000080 },
{ 0x02170100, 0x00000001 },
{ 0x02170500, 0x00000400 },
{ 0x02170700, 0x00000000 },
{ 0x02270100, 0x00000000 },
{ 0x02370100, 0x00000000 },
{ 0x01970700, 0x00000020 },
{ 0x00830000, 0x00000097 },
{ 0x00930000, 0x00000097 },
{ 0x01270700, 0x00000000 },
};
static bool rt274_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0 ... 0xff:
case RT274_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
case RT274_GET_HP_SENSE:
case RT274_GET_MIC_SENSE:
case RT274_PROC_COEF:
case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT274_MIC, 0):
case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT274_HP_OUT, 0):
case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_DAC_OUT0, 0):
case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_DAC_OUT1, 0):
case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_ADC_IN1, 0):
case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_ADC_IN2, 0):
case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DAC_OUT0, 0):
case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DAC_OUT1, 0):
case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_ADC_IN1, 0):
case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_ADC_IN2, 0):
case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DMIC1, 0):
case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DMIC2, 0):
case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_MIC, 0):
case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_LINE1, 0):
case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_LINE2, 0):
case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_HP_OUT, 0):
case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_HP_OUT, 0):
case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_MIXER_IN1, 0):
case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_MIXER_IN2, 0):
case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_DMIC1, 0):
case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_DMIC2, 0):
case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_MIC, 0):
case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_LINE1, 0):
case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_LINE2, 0):
case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_HP_OUT, 0):
case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_HP_OUT, 0):
case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_MIC, 0):
case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_INLINE_CMD, 0):
return true;
default:
return false;
}
}
static bool rt274_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0 ... 0xff:
case RT274_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
case RT274_GET_HP_SENSE:
case RT274_GET_MIC_SENSE:
case RT274_SET_AUDIO_POWER:
case RT274_SET_HPO_POWER:
case RT274_SET_DMIC1_POWER:
case RT274_LOUT_MUX:
case RT274_HPO_MUX:
case RT274_ADC0_MUX:
case RT274_ADC1_MUX:
case RT274_SET_MIC:
case RT274_SET_PIN_HPO:
case RT274_SET_PIN_LOUT3:
case RT274_SET_PIN_DMIC1:
case RT274_SET_AMP_GAIN_HPO:
case RT274_SET_DMIC2_DEFAULT:
case RT274_DAC0L_GAIN:
case RT274_DAC0R_GAIN:
case RT274_DAC1L_GAIN:
case RT274_DAC1R_GAIN:
case RT274_ADCL_GAIN:
case RT274_ADCR_GAIN:
case RT274_MIC_GAIN:
case RT274_HPOL_GAIN:
case RT274_HPOR_GAIN:
case RT274_LOUTL_GAIN:
case RT274_LOUTR_GAIN:
case RT274_DAC_FORMAT:
case RT274_ADC_FORMAT:
case RT274_COEF_INDEX:
case RT274_PROC_COEF:
case RT274_SET_AMP_GAIN_ADC_IN1:
case RT274_SET_AMP_GAIN_ADC_IN2:
case RT274_SET_POWER(RT274_DAC_OUT0):
case RT274_SET_POWER(RT274_DAC_OUT1):
case RT274_SET_POWER(RT274_ADC_IN1):
case RT274_SET_POWER(RT274_ADC_IN2):
case RT274_SET_POWER(RT274_DMIC2):
case RT274_SET_POWER(RT274_MIC):
case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT274_MIC, 0):
case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT274_HP_OUT, 0):
case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_DAC_OUT0, 0):
case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_DAC_OUT1, 0):
case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_ADC_IN1, 0):
case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_ADC_IN2, 0):
case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DAC_OUT0, 0):
case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DAC_OUT1, 0):
case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_ADC_IN1, 0):
case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_ADC_IN2, 0):
case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DMIC1, 0):
case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DMIC2, 0):
case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_MIC, 0):
case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_LINE1, 0):
case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_LINE2, 0):
case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_HP_OUT, 0):
case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_HP_OUT, 0):
case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_MIXER_IN1, 0):
case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_MIXER_IN2, 0):
case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_DMIC1, 0):
case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_DMIC2, 0):
case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_MIC, 0):
case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_LINE1, 0):
case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_LINE2, 0):
case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_HP_OUT, 0):
case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_HP_OUT, 0):
case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_MIC, 0):
case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_INLINE_CMD, 0):
return true;
default:
return false;
}
}
#ifdef CONFIG_PM
static void rt274_index_sync(struct snd_soc_component *component)
{
struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
int i;
for (i = 0; i < INDEX_CACHE_SIZE; i++) {
snd_soc_component_write(component, rt274->index_cache[i].reg,
rt274->index_cache[i].def);
}
}
#endif
static int rt274_jack_detect(struct rt274_priv *rt274, bool *hp, bool *mic)
{
unsigned int buf;
int ret;
*hp = false;
*mic = false;
if (!rt274->component)
return -EINVAL;
ret = regmap_read(rt274->regmap, RT274_GET_HP_SENSE, &buf);
if (ret)
return ret;
*hp = buf & 0x80000000;
ret = regmap_read(rt274->regmap, RT274_GET_MIC_SENSE, &buf);
if (ret)
return ret;
*mic = buf & 0x80000000;
pr_debug("*hp = %d *mic = %d\n", *hp, *mic);
return 0;
}
static void rt274_jack_detect_work(struct work_struct *work)
{
struct rt274_priv *rt274 =
container_of(work, struct rt274_priv, jack_detect_work.work);
int status = 0;
bool hp = false;
bool mic = false;
if (rt274_jack_detect(rt274, &hp, &mic) < 0)
return;
if (hp)
status |= SND_JACK_HEADPHONE;
if (mic)
status |= SND_JACK_MICROPHONE;
snd_soc_jack_report(rt274->jack, status,
SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
}
static irqreturn_t rt274_irq(int irq, void *data);
static int rt274_mic_detect(struct snd_soc_component *component,
struct snd_soc_jack *jack, void *data)
{
struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
rt274->jack = jack;
if (jack == NULL) {
/* Disable jack detection */
regmap_update_bits(rt274->regmap, RT274_EAPD_GPIO_IRQ_CTRL,
RT274_IRQ_EN, RT274_IRQ_DIS);
return 0;
}
regmap_update_bits(rt274->regmap, RT274_EAPD_GPIO_IRQ_CTRL,
RT274_IRQ_EN, RT274_IRQ_EN);
/* Send an initial report */
rt274_irq(0, rt274);
return 0;
}
static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0);
static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
static const struct snd_kcontrol_new rt274_snd_controls[] = {
SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT274_DAC0L_GAIN,
RT274_DAC0R_GAIN, 0, 0x7f, 0, out_vol_tlv),
SOC_DOUBLE_R_TLV("DAC1 Playback Volume", RT274_DAC1L_GAIN,
RT274_DAC1R_GAIN, 0, 0x7f, 0, out_vol_tlv),
SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT274_ADCL_GAIN,
RT274_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv),
SOC_DOUBLE_R("ADC0 Capture Switch", RT274_ADCL_GAIN,
RT274_ADCR_GAIN, RT274_MUTE_SFT, 1, 1),
SOC_SINGLE_TLV("AMIC Volume", RT274_MIC_GAIN,
0, 0x3, 0, mic_vol_tlv),
};
static const struct snd_kcontrol_new hpol_enable_control =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT274_HPOL_GAIN,
RT274_MUTE_SFT, 1, 1);
static const struct snd_kcontrol_new hpor_enable_control =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT274_HPOR_GAIN,
RT274_MUTE_SFT, 1, 1);
static const struct snd_kcontrol_new loutl_enable_control =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT274_LOUTL_GAIN,
RT274_MUTE_SFT, 1, 1);
static const struct snd_kcontrol_new loutr_enable_control =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT274_LOUTR_GAIN,
RT274_MUTE_SFT, 1, 1);
/* ADC0 source */
static const char * const rt274_adc_src[] = {
"Mic", "Line1", "Line2", "Dmic"
};
static SOC_ENUM_SINGLE_DECL(
rt274_adc0_enum, RT274_ADC0_MUX, RT274_ADC_SEL_SFT,
rt274_adc_src);
static const struct snd_kcontrol_new rt274_adc0_mux =
SOC_DAPM_ENUM("ADC 0 source", rt274_adc0_enum);
static SOC_ENUM_SINGLE_DECL(
rt274_adc1_enum, RT274_ADC1_MUX, RT274_ADC_SEL_SFT,
rt274_adc_src);
static const struct snd_kcontrol_new rt274_adc1_mux =
SOC_DAPM_ENUM("ADC 1 source", rt274_adc1_enum);
static const char * const rt274_dac_src[] = {
"DAC OUT0", "DAC OUT1"
};
/* HP-OUT source */
static SOC_ENUM_SINGLE_DECL(rt274_hpo_enum, RT274_HPO_MUX,
0, rt274_dac_src);
static const struct snd_kcontrol_new rt274_hpo_mux =
SOC_DAPM_ENUM("HPO source", rt274_hpo_enum);
/* Line out source */
static SOC_ENUM_SINGLE_DECL(rt274_lout_enum, RT274_LOUT_MUX,
0, rt274_dac_src);
static const struct snd_kcontrol_new rt274_lout_mux =
SOC_DAPM_ENUM("LOUT source", rt274_lout_enum);
static const struct snd_soc_dapm_widget rt274_dapm_widgets[] = {
/* Input Lines */
SND_SOC_DAPM_INPUT("DMIC1 Pin"),
SND_SOC_DAPM_INPUT("DMIC2 Pin"),
SND_SOC_DAPM_INPUT("MIC"),
SND_SOC_DAPM_INPUT("LINE1"),
SND_SOC_DAPM_INPUT("LINE2"),
/* DMIC */
SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
/* ADCs */
SND_SOC_DAPM_ADC("ADC 0", NULL, RT274_SET_STREAMID_ADC1, 4, 0),
SND_SOC_DAPM_ADC("ADC 1", NULL, RT274_SET_STREAMID_ADC2, 4, 0),
/* ADC Mux */
SND_SOC_DAPM_MUX("ADC 0 Mux", SND_SOC_NOPM, 0, 0,
&rt274_adc0_mux),
SND_SOC_DAPM_MUX("ADC 1 Mux", SND_SOC_NOPM, 0, 0,
&rt274_adc1_mux),
/* Audio Interface */
SND_SOC_DAPM_AIF_IN("AIF1RXL", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIF1RXR", "AIF1 Playback", 1, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TXL", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TXR", "AIF1 Capture", 1, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIF2RXL", "AIF1 Playback", 2, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIF2RXR", "AIF1 Playback", 3, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TXL", "AIF1 Capture", 2, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TXR", "AIF1 Capture", 3, SND_SOC_NOPM, 0, 0),
/* Output Side */
/* DACs */
SND_SOC_DAPM_DAC("DAC 0", NULL, RT274_SET_STREAMID_DAC0, 4, 0),
SND_SOC_DAPM_DAC("DAC 1", NULL, RT274_SET_STREAMID_DAC1, 4, 0),
/* Output Mux */
SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt274_hpo_mux),
SND_SOC_DAPM_MUX("LOUT Mux", SND_SOC_NOPM, 0, 0, &rt274_lout_mux),
SND_SOC_DAPM_SUPPLY("HP Power", RT274_SET_PIN_HPO,
RT274_SET_PIN_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("LOUT Power", RT274_SET_PIN_LOUT3,
RT274_SET_PIN_SFT, 0, NULL, 0),
/* Output Mixer */
SND_SOC_DAPM_PGA("DAC OUT0", SND_SOC_NOPM, 0, 0,
NULL, 0),
SND_SOC_DAPM_PGA("DAC OUT1", SND_SOC_NOPM, 0, 0,
NULL, 0),
/* Output Pga */
SND_SOC_DAPM_SWITCH("LOUT L", SND_SOC_NOPM, 0, 0,
&loutl_enable_control),
SND_SOC_DAPM_SWITCH("LOUT R", SND_SOC_NOPM, 0, 0,
&loutr_enable_control),
SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0,
&hpol_enable_control),
SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0,
&hpor_enable_control),
/* Output Lines */
SND_SOC_DAPM_OUTPUT("HPO Pin"),
SND_SOC_DAPM_OUTPUT("SPDIF"),
SND_SOC_DAPM_OUTPUT("LINE3"),
};
static const struct snd_soc_dapm_route rt274_dapm_routes[] = {
{"DMIC1", NULL, "DMIC1 Pin"},
{"DMIC2", NULL, "DMIC2 Pin"},
{"ADC 0 Mux", "Mic", "MIC"},
{"ADC 0 Mux", "Dmic", "DMIC1"},
{"ADC 0 Mux", "Line1", "LINE1"},
{"ADC 0 Mux", "Line2", "LINE2"},
{"ADC 1 Mux", "Mic", "MIC"},
{"ADC 1 Mux", "Dmic", "DMIC2"},
{"ADC 1 Mux", "Line1", "LINE1"},
{"ADC 1 Mux", "Line2", "LINE2"},
{"ADC 0", NULL, "ADC 0 Mux"},
{"ADC 1", NULL, "ADC 1 Mux"},
{"AIF1TXL", NULL, "ADC 0"},
{"AIF1TXR", NULL, "ADC 0"},
{"AIF2TXL", NULL, "ADC 1"},
{"AIF2TXR", NULL, "ADC 1"},
{"DAC 0", NULL, "AIF1RXL"},
{"DAC 0", NULL, "AIF1RXR"},
{"DAC 1", NULL, "AIF2RXL"},
{"DAC 1", NULL, "AIF2RXR"},
{"DAC OUT0", NULL, "DAC 0"},
{"DAC OUT1", NULL, "DAC 1"},
{"LOUT Mux", "DAC OUT0", "DAC OUT0"},
{"LOUT Mux", "DAC OUT1", "DAC OUT1"},
{"LOUT L", "Switch", "LOUT Mux"},
{"LOUT R", "Switch", "LOUT Mux"},
{"LOUT L", NULL, "LOUT Power"},
{"LOUT R", NULL, "LOUT Power"},
{"LINE3", NULL, "LOUT L"},
{"LINE3", NULL, "LOUT R"},
{"HPO Mux", "DAC OUT0", "DAC OUT0"},
{"HPO Mux", "DAC OUT1", "DAC OUT1"},
{"HPO L", "Switch", "HPO Mux"},
{"HPO R", "Switch", "HPO Mux"},
{"HPO L", NULL, "HP Power"},
{"HPO R", NULL, "HP Power"},
{"HPO Pin", NULL, "HPO L"},
{"HPO Pin", NULL, "HPO R"},
};
static int rt274_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
unsigned int val = 0;
int d_len_code = 0, c_len_code = 0;
switch (params_rate(params)) {
/* bit 14 0:48K 1:44.1K */
case 44100:
case 48000:
break;
default:
dev_err(component->dev, "Unsupported sample rate %d\n",
params_rate(params));
return -EINVAL;
}
switch (rt274->sys_clk) {
case 12288000:
case 24576000:
if (params_rate(params) != 48000) {
dev_err(component->dev, "Sys_clk is not matched (%d %d)\n",
params_rate(params), rt274->sys_clk);
return -EINVAL;
}
break;
case 11289600:
case 22579200:
if (params_rate(params) != 44100) {
dev_err(component->dev, "Sys_clk is not matched (%d %d)\n",
params_rate(params), rt274->sys_clk);
return -EINVAL;
}
break;
}
if (params_channels(params) <= 16) {
/* bit 3:0 Number of Channel */
val |= (params_channels(params) - 1);
} else {
dev_err(component->dev, "Unsupported channels %d\n",
params_channels(params));
return -EINVAL;
}
switch (params_width(params)) {
/* bit 6:4 Bits per Sample */
case 16:
d_len_code = 0;
c_len_code = 0;
val |= (0x1 << 4);
break;
case 32:
d_len_code = 2;
c_len_code = 3;
val |= (0x4 << 4);
break;
case 20:
d_len_code = 1;
c_len_code = 1;
val |= (0x2 << 4);
break;
case 24:
d_len_code = 2;
c_len_code = 2;
val |= (0x3 << 4);
break;
case 8:
d_len_code = 3;
c_len_code = 0;
break;
default:
return -EINVAL;
}
if (rt274->master)
c_len_code = 0x3;
snd_soc_component_update_bits(component,
RT274_I2S_CTRL1, 0xc018, d_len_code << 3 | c_len_code << 14);
dev_dbg(component->dev, "format val = 0x%x\n", val);
snd_soc_component_update_bits(component, RT274_DAC_FORMAT, 0x407f, val);
snd_soc_component_update_bits(component, RT274_ADC_FORMAT, 0x407f, val);
return 0;
}
static int rt274_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
snd_soc_component_update_bits(component,
RT274_I2S_CTRL1, RT274_I2S_MODE_MASK, RT274_I2S_MODE_M);
rt274->master = true;
break;
case SND_SOC_DAIFMT_CBS_CFS:
snd_soc_component_update_bits(component,
RT274_I2S_CTRL1, RT274_I2S_MODE_MASK, RT274_I2S_MODE_S);
rt274->master = false;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
snd_soc_component_update_bits(component, RT274_I2S_CTRL1,
RT274_I2S_FMT_MASK, RT274_I2S_FMT_I2S);
break;
case SND_SOC_DAIFMT_LEFT_J:
snd_soc_component_update_bits(component, RT274_I2S_CTRL1,
RT274_I2S_FMT_MASK, RT274_I2S_FMT_LJ);
break;
case SND_SOC_DAIFMT_DSP_A:
snd_soc_component_update_bits(component, RT274_I2S_CTRL1,
RT274_I2S_FMT_MASK, RT274_I2S_FMT_PCMA);
break;
case SND_SOC_DAIFMT_DSP_B:
snd_soc_component_update_bits(component, RT274_I2S_CTRL1,
RT274_I2S_FMT_MASK, RT274_I2S_FMT_PCMB);
break;
default:
return -EINVAL;
}
/* bit 15 Stream Type 0:PCM 1:Non-PCM */
snd_soc_component_update_bits(component, RT274_DAC_FORMAT, 0x8000, 0);
snd_soc_component_update_bits(component, RT274_ADC_FORMAT, 0x8000, 0);
return 0;
}
static int rt274_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
unsigned int freq_in, unsigned int freq_out)
{
struct snd_soc_component *component = dai->component;
struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
switch (source) {
case RT274_PLL2_S_MCLK:
snd_soc_component_update_bits(component, RT274_PLL2_CTRL,
RT274_PLL2_SRC_MASK, RT274_PLL2_SRC_MCLK);
break;
default:
dev_warn(component->dev, "invalid pll source, use BCLK\n");
fallthrough;
case RT274_PLL2_S_BCLK:
snd_soc_component_update_bits(component, RT274_PLL2_CTRL,
RT274_PLL2_SRC_MASK, RT274_PLL2_SRC_BCLK);
break;
}
if (source == RT274_PLL2_S_BCLK) {
snd_soc_component_update_bits(component, RT274_MCLK_CTRL,
(0x3 << 12), (0x3 << 12));
switch (rt274->fs) {
case 50:
snd_soc_component_write(component, 0x7a, 0xaab6);
snd_soc_component_write(component, 0x7b, 0x0301);
snd_soc_component_write(component, 0x7c, 0x04fe);
break;
case 64:
snd_soc_component_write(component, 0x7a, 0xaa96);
snd_soc_component_write(component, 0x7b, 0x8003);
snd_soc_component_write(component, 0x7c, 0x081e);
break;
case 128:
snd_soc_component_write(component, 0x7a, 0xaa96);
snd_soc_component_write(component, 0x7b, 0x8003);
snd_soc_component_write(component, 0x7c, 0x080e);
break;
default:
dev_warn(component->dev, "invalid freq_in, assume 4.8M\n");
fallthrough;
case 100:
snd_soc_component_write(component, 0x7a, 0xaab6);
snd_soc_component_write(component, 0x7b, 0x0301);
snd_soc_component_write(component, 0x7c, 0x047e);
break;
}
}
return 0;
}
static int rt274_set_dai_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
unsigned int clk_src, mclk_en;
dev_dbg(component->dev, "%s freq=%d\n", __func__, freq);
switch (clk_id) {
case RT274_SCLK_S_MCLK:
mclk_en = RT274_MCLK_MODE_EN;
clk_src = RT274_CLK_SRC_MCLK;
break;
case RT274_SCLK_S_PLL1:
mclk_en = RT274_MCLK_MODE_DIS;
clk_src = RT274_CLK_SRC_MCLK;
break;
case RT274_SCLK_S_PLL2:
mclk_en = RT274_MCLK_MODE_EN;
clk_src = RT274_CLK_SRC_PLL2;
break;
default:
mclk_en = RT274_MCLK_MODE_DIS;
clk_src = RT274_CLK_SRC_MCLK;
dev_warn(component->dev, "invalid sysclk source, use PLL1\n");
break;
}
snd_soc_component_update_bits(component, RT274_MCLK_CTRL,
RT274_MCLK_MODE_MASK, mclk_en);
snd_soc_component_update_bits(component, RT274_CLK_CTRL,
RT274_CLK_SRC_MASK, clk_src);
switch (freq) {
case 19200000:
if (clk_id == RT274_SCLK_S_MCLK) {
dev_err(component->dev, "Should not use MCLK\n");
return -EINVAL;
}
snd_soc_component_update_bits(component,
RT274_I2S_CTRL2, 0x40, 0x40);
break;
case 24000000:
if (clk_id == RT274_SCLK_S_MCLK) {
dev_err(component->dev, "Should not use MCLK\n");
return -EINVAL;
}
snd_soc_component_update_bits(component,
RT274_I2S_CTRL2, 0x40, 0x0);
break;
case 12288000:
case 11289600:
snd_soc_component_update_bits(component,
RT274_MCLK_CTRL, 0x1fcf, 0x0008);
break;
case 24576000:
case 22579200:
snd_soc_component_update_bits(component,
RT274_MCLK_CTRL, 0x1fcf, 0x1543);
break;
default:
dev_err(component->dev, "Unsupported system clock\n");
return -EINVAL;
}
rt274->sys_clk = freq;
rt274->clk_id = clk_id;
return 0;
}
static int rt274_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
{
struct snd_soc_component *component = dai->component;
struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio);
rt274->fs = ratio;
if ((ratio / 50) == 0)
snd_soc_component_update_bits(component,
RT274_I2S_CTRL1, 0x1000, 0x1000);
else
snd_soc_component_update_bits(component,
RT274_I2S_CTRL1, 0x1000, 0x0);
return 0;
}
static int rt274_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
if (rx_mask || tx_mask) {
snd_soc_component_update_bits(component,
RT274_I2S_CTRL1, RT274_TDM_EN, RT274_TDM_EN);
} else {
snd_soc_component_update_bits(component,
RT274_I2S_CTRL1, RT274_TDM_EN, RT274_TDM_DIS);
return 0;
}
switch (slots) {
case 4:
snd_soc_component_update_bits(component,
RT274_I2S_CTRL1, RT274_TDM_CH_NUM, RT274_TDM_4CH);
break;
case 2:
snd_soc_component_update_bits(component,
RT274_I2S_CTRL1, RT274_TDM_CH_NUM, RT274_TDM_2CH);
break;
default:
dev_err(component->dev,
"Support 2 or 4 slots TDM only\n");
return -EINVAL;
}
return 0;
}
static int rt274_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
switch (level) {
case SND_SOC_BIAS_PREPARE:
if (SND_SOC_BIAS_STANDBY ==
snd_soc_component_get_bias_level(component)) {
snd_soc_component_write(component,
RT274_SET_AUDIO_POWER, AC_PWRST_D0);
}
break;
case SND_SOC_BIAS_STANDBY:
snd_soc_component_write(component,
RT274_SET_AUDIO_POWER, AC_PWRST_D3);
break;
default:
break;
}
return 0;
}
static irqreturn_t rt274_irq(int irq, void *data)
{
struct rt274_priv *rt274 = data;
bool hp = false;
bool mic = false;
int ret, status = 0;
/* Clear IRQ */
regmap_update_bits(rt274->regmap, RT274_EAPD_GPIO_IRQ_CTRL,
RT274_IRQ_CLR, RT274_IRQ_CLR);
ret = rt274_jack_detect(rt274, &hp, &mic);
if (ret == 0) {
if (hp)
status |= SND_JACK_HEADPHONE;
if (mic)
status |= SND_JACK_MICROPHONE;
snd_soc_jack_report(rt274->jack, status,
SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
pm_wakeup_event(&rt274->i2c->dev, 300);
}
return IRQ_HANDLED;
}
static int rt274_probe(struct snd_soc_component *component)
{
struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
rt274->component = component;
INIT_DELAYED_WORK(&rt274->jack_detect_work, rt274_jack_detect_work);
if (rt274->i2c->irq)
schedule_delayed_work(&rt274->jack_detect_work,
msecs_to_jiffies(1250));
return 0;
}
static void rt274_remove(struct snd_soc_component *component)
{
struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
cancel_delayed_work_sync(&rt274->jack_detect_work);
rt274->component = NULL;
}
#ifdef CONFIG_PM
static int rt274_suspend(struct snd_soc_component *component)
{
struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
regcache_cache_only(rt274->regmap, true);
regcache_mark_dirty(rt274->regmap);
return 0;
}
static int rt274_resume(struct snd_soc_component *component)
{
struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
regcache_cache_only(rt274->regmap, false);
rt274_index_sync(component);
regcache_sync(rt274->regmap);
return 0;
}
#else
#define rt274_suspend NULL
#define rt274_resume NULL
#endif
#define RT274_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
#define RT274_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
static const struct snd_soc_dai_ops rt274_aif_dai_ops = {
.hw_params = rt274_hw_params,
.set_fmt = rt274_set_dai_fmt,
.set_sysclk = rt274_set_dai_sysclk,
.set_pll = rt274_set_dai_pll,
.set_bclk_ratio = rt274_set_bclk_ratio,
.set_tdm_slot = rt274_set_tdm_slot,
};
static struct snd_soc_dai_driver rt274_dai[] = {
{
.name = "rt274-aif1",
.id = RT274_AIF1,
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT274_STEREO_RATES,
.formats = RT274_FORMATS,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT274_STEREO_RATES,
.formats = RT274_FORMATS,
},
.ops = &rt274_aif_dai_ops,
.symmetric_rate = 1,
},
};
static const struct snd_soc_component_driver soc_component_dev_rt274 = {
.probe = rt274_probe,
.remove = rt274_remove,
.suspend = rt274_suspend,
.resume = rt274_resume,
.set_bias_level = rt274_set_bias_level,
.set_jack = rt274_mic_detect,
.controls = rt274_snd_controls,
.num_controls = ARRAY_SIZE(rt274_snd_controls),
.dapm_widgets = rt274_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt274_dapm_widgets),
.dapm_routes = rt274_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(rt274_dapm_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config rt274_regmap = {
.reg_bits = 32,
.val_bits = 32,
.max_register = 0x05bfffff,
.volatile_reg = rt274_volatile_register,
.readable_reg = rt274_readable_register,
.reg_write = rl6347a_hw_write,
.reg_read = rl6347a_hw_read,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = rt274_reg,
.num_reg_defaults = ARRAY_SIZE(rt274_reg),
};
#ifdef CONFIG_OF
static const struct of_device_id rt274_of_match[] = {
{.compatible = "realtek,rt274"},
{},
};
MODULE_DEVICE_TABLE(of, rt274_of_match);
#endif
static const struct i2c_device_id rt274_i2c_id[] = {
{"rt274", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, rt274_i2c_id);
#ifdef CONFIG_ACPI
static const struct acpi_device_id rt274_acpi_match[] = {
{ "10EC0274", 0 },
{ "INT34C2", 0 },
{},
};
MODULE_DEVICE_TABLE(acpi, rt274_acpi_match);
#endif
static int rt274_i2c_probe(struct i2c_client *i2c)
{
struct rt274_priv *rt274;
int ret;
unsigned int val;
rt274 = devm_kzalloc(&i2c->dev, sizeof(*rt274),
GFP_KERNEL);
if (rt274 == NULL)
return -ENOMEM;
rt274->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt274_regmap);
if (IS_ERR(rt274->regmap)) {
ret = PTR_ERR(rt274->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
ret = regmap_read(rt274->regmap,
RT274_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &val);
if (ret)
return ret;
if (val != RT274_VENDOR_ID) {
dev_err(&i2c->dev,
"Device with ID register %#x is not rt274\n", val);
return -ENODEV;
}
rt274->index_cache = devm_kmemdup(&i2c->dev, rt274_index_def,
sizeof(rt274_index_def), GFP_KERNEL);
if (!rt274->index_cache)
return -ENOMEM;
rt274->index_cache_size = INDEX_CACHE_SIZE;
rt274->i2c = i2c;
i2c_set_clientdata(i2c, rt274);
/* reset codec */
regmap_write(rt274->regmap, RT274_RESET, 0);
regmap_update_bits(rt274->regmap, 0x1a, 0x4000, 0x4000);
/* Set Pad PDB is floating */
regmap_update_bits(rt274->regmap, RT274_PAD_CTRL12, 0x3, 0x0);
regmap_write(rt274->regmap, RT274_COEF5b_INDEX, 0x01);
regmap_write(rt274->regmap, RT274_COEF5b_COEF, 0x8540);
regmap_update_bits(rt274->regmap, 0x6f, 0x0100, 0x0100);
/* Combo jack auto detect */
regmap_write(rt274->regmap, 0x4a, 0x201b);
/* Aux mode off */
regmap_update_bits(rt274->regmap, 0x6f, 0x3000, 0x2000);
/* HP DC Calibration */
regmap_update_bits(rt274->regmap, 0x6f, 0xf, 0x0);
/* Set NID=58h.Index 00h [15]= 1b; */
regmap_write(rt274->regmap, RT274_COEF58_INDEX, 0x00);
regmap_write(rt274->regmap, RT274_COEF58_COEF, 0xb888);
msleep(500);
regmap_update_bits(rt274->regmap, 0x6f, 0xf, 0xb);
regmap_write(rt274->regmap, RT274_COEF58_INDEX, 0x00);
regmap_write(rt274->regmap, RT274_COEF58_COEF, 0x3888);
/* Set pin widget */
regmap_write(rt274->regmap, RT274_SET_PIN_HPO, 0x40);
regmap_write(rt274->regmap, RT274_SET_PIN_LOUT3, 0x40);
regmap_write(rt274->regmap, RT274_SET_MIC, 0x20);
regmap_write(rt274->regmap, RT274_SET_PIN_DMIC1, 0x20);
regmap_update_bits(rt274->regmap, RT274_I2S_CTRL2, 0xc004, 0x4004);
regmap_update_bits(rt274->regmap, RT274_EAPD_GPIO_IRQ_CTRL,
RT274_GPI2_SEL_MASK, RT274_GPI2_SEL_DMIC_CLK);
/* jack detection */
regmap_write(rt274->regmap, RT274_UNSOLICITED_HP_OUT, 0x81);
regmap_write(rt274->regmap, RT274_UNSOLICITED_MIC, 0x82);
if (rt274->i2c->irq) {
ret = request_threaded_irq(rt274->i2c->irq, NULL, rt274_irq,
IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt274", rt274);
if (ret != 0) {
dev_err(&i2c->dev,
"Failed to reguest IRQ: %d\n", ret);
return ret;
}
}
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_rt274,
rt274_dai, ARRAY_SIZE(rt274_dai));
return ret;
}
static void rt274_i2c_remove(struct i2c_client *i2c)
{
struct rt274_priv *rt274 = i2c_get_clientdata(i2c);
if (i2c->irq)
free_irq(i2c->irq, rt274);
}
static struct i2c_driver rt274_i2c_driver = {
.driver = {
.name = "rt274",
.acpi_match_table = ACPI_PTR(rt274_acpi_match),
#ifdef CONFIG_OF
.of_match_table = of_match_ptr(rt274_of_match),
#endif
},
.probe = rt274_i2c_probe,
.remove = rt274_i2c_remove,
.id_table = rt274_i2c_id,
};
module_i2c_driver(rt274_i2c_driver);
MODULE_DESCRIPTION("ASoC RT274 driver");
MODULE_AUTHOR("Bard Liao <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/rt274.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Analog Devices ADAU1373 Audio Codec drive
*
* Copyright 2011 Analog Devices Inc.
* Author: Lars-Peter Clausen <[email protected]>
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/tlv.h>
#include <sound/soc.h>
#include <sound/adau1373.h>
#include "adau1373.h"
#include "adau-utils.h"
struct adau1373_dai {
unsigned int clk_src;
unsigned int sysclk;
bool enable_src;
bool clock_provider;
};
struct adau1373 {
struct regmap *regmap;
struct adau1373_dai dais[3];
};
#define ADAU1373_INPUT_MODE 0x00
#define ADAU1373_AINL_CTRL(x) (0x01 + (x) * 2)
#define ADAU1373_AINR_CTRL(x) (0x02 + (x) * 2)
#define ADAU1373_LLINE_OUT(x) (0x9 + (x) * 2)
#define ADAU1373_RLINE_OUT(x) (0xa + (x) * 2)
#define ADAU1373_LSPK_OUT 0x0d
#define ADAU1373_RSPK_OUT 0x0e
#define ADAU1373_LHP_OUT 0x0f
#define ADAU1373_RHP_OUT 0x10
#define ADAU1373_ADC_GAIN 0x11
#define ADAU1373_LADC_MIXER 0x12
#define ADAU1373_RADC_MIXER 0x13
#define ADAU1373_LLINE1_MIX 0x14
#define ADAU1373_RLINE1_MIX 0x15
#define ADAU1373_LLINE2_MIX 0x16
#define ADAU1373_RLINE2_MIX 0x17
#define ADAU1373_LSPK_MIX 0x18
#define ADAU1373_RSPK_MIX 0x19
#define ADAU1373_LHP_MIX 0x1a
#define ADAU1373_RHP_MIX 0x1b
#define ADAU1373_EP_MIX 0x1c
#define ADAU1373_HP_CTRL 0x1d
#define ADAU1373_HP_CTRL2 0x1e
#define ADAU1373_LS_CTRL 0x1f
#define ADAU1373_EP_CTRL 0x21
#define ADAU1373_MICBIAS_CTRL1 0x22
#define ADAU1373_MICBIAS_CTRL2 0x23
#define ADAU1373_OUTPUT_CTRL 0x24
#define ADAU1373_PWDN_CTRL1 0x25
#define ADAU1373_PWDN_CTRL2 0x26
#define ADAU1373_PWDN_CTRL3 0x27
#define ADAU1373_DPLL_CTRL(x) (0x28 + (x) * 7)
#define ADAU1373_PLL_CTRL1(x) (0x29 + (x) * 7)
#define ADAU1373_PLL_CTRL2(x) (0x2a + (x) * 7)
#define ADAU1373_PLL_CTRL3(x) (0x2b + (x) * 7)
#define ADAU1373_PLL_CTRL4(x) (0x2c + (x) * 7)
#define ADAU1373_PLL_CTRL5(x) (0x2d + (x) * 7)
#define ADAU1373_PLL_CTRL6(x) (0x2e + (x) * 7)
#define ADAU1373_HEADDECT 0x36
#define ADAU1373_ADC_DAC_STATUS 0x37
#define ADAU1373_ADC_CTRL 0x3c
#define ADAU1373_DAI(x) (0x44 + (x))
#define ADAU1373_CLK_SRC_DIV(x) (0x40 + (x) * 2)
#define ADAU1373_BCLKDIV(x) (0x47 + (x))
#define ADAU1373_SRC_RATIOA(x) (0x4a + (x) * 2)
#define ADAU1373_SRC_RATIOB(x) (0x4b + (x) * 2)
#define ADAU1373_DEEMP_CTRL 0x50
#define ADAU1373_SRC_DAI_CTRL(x) (0x51 + (x))
#define ADAU1373_DIN_MIX_CTRL(x) (0x56 + (x))
#define ADAU1373_DOUT_MIX_CTRL(x) (0x5b + (x))
#define ADAU1373_DAI_PBL_VOL(x) (0x62 + (x) * 2)
#define ADAU1373_DAI_PBR_VOL(x) (0x63 + (x) * 2)
#define ADAU1373_DAI_RECL_VOL(x) (0x68 + (x) * 2)
#define ADAU1373_DAI_RECR_VOL(x) (0x69 + (x) * 2)
#define ADAU1373_DAC1_PBL_VOL 0x6e
#define ADAU1373_DAC1_PBR_VOL 0x6f
#define ADAU1373_DAC2_PBL_VOL 0x70
#define ADAU1373_DAC2_PBR_VOL 0x71
#define ADAU1373_ADC_RECL_VOL 0x72
#define ADAU1373_ADC_RECR_VOL 0x73
#define ADAU1373_DMIC_RECL_VOL 0x74
#define ADAU1373_DMIC_RECR_VOL 0x75
#define ADAU1373_VOL_GAIN1 0x76
#define ADAU1373_VOL_GAIN2 0x77
#define ADAU1373_VOL_GAIN3 0x78
#define ADAU1373_HPF_CTRL 0x7d
#define ADAU1373_BASS1 0x7e
#define ADAU1373_BASS2 0x7f
#define ADAU1373_DRC(x) (0x80 + (x) * 0x10)
#define ADAU1373_3D_CTRL1 0xc0
#define ADAU1373_3D_CTRL2 0xc1
#define ADAU1373_FDSP_SEL1 0xdc
#define ADAU1373_FDSP_SEL2 0xdd
#define ADAU1373_FDSP_SEL3 0xde
#define ADAU1373_FDSP_SEL4 0xdf
#define ADAU1373_DIGMICCTRL 0xe2
#define ADAU1373_DIGEN 0xeb
#define ADAU1373_SOFT_RESET 0xff
#define ADAU1373_PLL_CTRL6_DPLL_BYPASS BIT(1)
#define ADAU1373_PLL_CTRL6_PLL_EN BIT(0)
#define ADAU1373_DAI_INVERT_BCLK BIT(7)
#define ADAU1373_DAI_MASTER BIT(6)
#define ADAU1373_DAI_INVERT_LRCLK BIT(4)
#define ADAU1373_DAI_WLEN_16 0x0
#define ADAU1373_DAI_WLEN_20 0x4
#define ADAU1373_DAI_WLEN_24 0x8
#define ADAU1373_DAI_WLEN_32 0xc
#define ADAU1373_DAI_WLEN_MASK 0xc
#define ADAU1373_DAI_FORMAT_RIGHT_J 0x0
#define ADAU1373_DAI_FORMAT_LEFT_J 0x1
#define ADAU1373_DAI_FORMAT_I2S 0x2
#define ADAU1373_DAI_FORMAT_DSP 0x3
#define ADAU1373_BCLKDIV_SOURCE BIT(5)
#define ADAU1373_BCLKDIV_SR_MASK (0x07 << 2)
#define ADAU1373_BCLKDIV_BCLK_MASK 0x03
#define ADAU1373_BCLKDIV_32 0x03
#define ADAU1373_BCLKDIV_64 0x02
#define ADAU1373_BCLKDIV_128 0x01
#define ADAU1373_BCLKDIV_256 0x00
#define ADAU1373_ADC_CTRL_PEAK_DETECT BIT(0)
#define ADAU1373_ADC_CTRL_RESET BIT(1)
#define ADAU1373_ADC_CTRL_RESET_FORCE BIT(2)
#define ADAU1373_OUTPUT_CTRL_LDIFF BIT(3)
#define ADAU1373_OUTPUT_CTRL_LNFBEN BIT(2)
#define ADAU1373_PWDN_CTRL3_PWR_EN BIT(0)
#define ADAU1373_EP_CTRL_MICBIAS1_OFFSET 4
#define ADAU1373_EP_CTRL_MICBIAS2_OFFSET 2
static const struct reg_default adau1373_reg_defaults[] = {
{ ADAU1373_INPUT_MODE, 0x00 },
{ ADAU1373_AINL_CTRL(0), 0x00 },
{ ADAU1373_AINR_CTRL(0), 0x00 },
{ ADAU1373_AINL_CTRL(1), 0x00 },
{ ADAU1373_AINR_CTRL(1), 0x00 },
{ ADAU1373_AINL_CTRL(2), 0x00 },
{ ADAU1373_AINR_CTRL(2), 0x00 },
{ ADAU1373_AINL_CTRL(3), 0x00 },
{ ADAU1373_AINR_CTRL(3), 0x00 },
{ ADAU1373_LLINE_OUT(0), 0x00 },
{ ADAU1373_RLINE_OUT(0), 0x00 },
{ ADAU1373_LLINE_OUT(1), 0x00 },
{ ADAU1373_RLINE_OUT(1), 0x00 },
{ ADAU1373_LSPK_OUT, 0x00 },
{ ADAU1373_RSPK_OUT, 0x00 },
{ ADAU1373_LHP_OUT, 0x00 },
{ ADAU1373_RHP_OUT, 0x00 },
{ ADAU1373_ADC_GAIN, 0x00 },
{ ADAU1373_LADC_MIXER, 0x00 },
{ ADAU1373_RADC_MIXER, 0x00 },
{ ADAU1373_LLINE1_MIX, 0x00 },
{ ADAU1373_RLINE1_MIX, 0x00 },
{ ADAU1373_LLINE2_MIX, 0x00 },
{ ADAU1373_RLINE2_MIX, 0x00 },
{ ADAU1373_LSPK_MIX, 0x00 },
{ ADAU1373_RSPK_MIX, 0x00 },
{ ADAU1373_LHP_MIX, 0x00 },
{ ADAU1373_RHP_MIX, 0x00 },
{ ADAU1373_EP_MIX, 0x00 },
{ ADAU1373_HP_CTRL, 0x00 },
{ ADAU1373_HP_CTRL2, 0x00 },
{ ADAU1373_LS_CTRL, 0x00 },
{ ADAU1373_EP_CTRL, 0x00 },
{ ADAU1373_MICBIAS_CTRL1, 0x00 },
{ ADAU1373_MICBIAS_CTRL2, 0x00 },
{ ADAU1373_OUTPUT_CTRL, 0x00 },
{ ADAU1373_PWDN_CTRL1, 0x00 },
{ ADAU1373_PWDN_CTRL2, 0x00 },
{ ADAU1373_PWDN_CTRL3, 0x00 },
{ ADAU1373_DPLL_CTRL(0), 0x00 },
{ ADAU1373_PLL_CTRL1(0), 0x00 },
{ ADAU1373_PLL_CTRL2(0), 0x00 },
{ ADAU1373_PLL_CTRL3(0), 0x00 },
{ ADAU1373_PLL_CTRL4(0), 0x00 },
{ ADAU1373_PLL_CTRL5(0), 0x00 },
{ ADAU1373_PLL_CTRL6(0), 0x02 },
{ ADAU1373_DPLL_CTRL(1), 0x00 },
{ ADAU1373_PLL_CTRL1(1), 0x00 },
{ ADAU1373_PLL_CTRL2(1), 0x00 },
{ ADAU1373_PLL_CTRL3(1), 0x00 },
{ ADAU1373_PLL_CTRL4(1), 0x00 },
{ ADAU1373_PLL_CTRL5(1), 0x00 },
{ ADAU1373_PLL_CTRL6(1), 0x02 },
{ ADAU1373_HEADDECT, 0x00 },
{ ADAU1373_ADC_CTRL, 0x00 },
{ ADAU1373_CLK_SRC_DIV(0), 0x00 },
{ ADAU1373_CLK_SRC_DIV(1), 0x00 },
{ ADAU1373_DAI(0), 0x0a },
{ ADAU1373_DAI(1), 0x0a },
{ ADAU1373_DAI(2), 0x0a },
{ ADAU1373_BCLKDIV(0), 0x00 },
{ ADAU1373_BCLKDIV(1), 0x00 },
{ ADAU1373_BCLKDIV(2), 0x00 },
{ ADAU1373_SRC_RATIOA(0), 0x00 },
{ ADAU1373_SRC_RATIOB(0), 0x00 },
{ ADAU1373_SRC_RATIOA(1), 0x00 },
{ ADAU1373_SRC_RATIOB(1), 0x00 },
{ ADAU1373_SRC_RATIOA(2), 0x00 },
{ ADAU1373_SRC_RATIOB(2), 0x00 },
{ ADAU1373_DEEMP_CTRL, 0x00 },
{ ADAU1373_SRC_DAI_CTRL(0), 0x08 },
{ ADAU1373_SRC_DAI_CTRL(1), 0x08 },
{ ADAU1373_SRC_DAI_CTRL(2), 0x08 },
{ ADAU1373_DIN_MIX_CTRL(0), 0x00 },
{ ADAU1373_DIN_MIX_CTRL(1), 0x00 },
{ ADAU1373_DIN_MIX_CTRL(2), 0x00 },
{ ADAU1373_DIN_MIX_CTRL(3), 0x00 },
{ ADAU1373_DIN_MIX_CTRL(4), 0x00 },
{ ADAU1373_DOUT_MIX_CTRL(0), 0x00 },
{ ADAU1373_DOUT_MIX_CTRL(1), 0x00 },
{ ADAU1373_DOUT_MIX_CTRL(2), 0x00 },
{ ADAU1373_DOUT_MIX_CTRL(3), 0x00 },
{ ADAU1373_DOUT_MIX_CTRL(4), 0x00 },
{ ADAU1373_DAI_PBL_VOL(0), 0x00 },
{ ADAU1373_DAI_PBR_VOL(0), 0x00 },
{ ADAU1373_DAI_PBL_VOL(1), 0x00 },
{ ADAU1373_DAI_PBR_VOL(1), 0x00 },
{ ADAU1373_DAI_PBL_VOL(2), 0x00 },
{ ADAU1373_DAI_PBR_VOL(2), 0x00 },
{ ADAU1373_DAI_RECL_VOL(0), 0x00 },
{ ADAU1373_DAI_RECR_VOL(0), 0x00 },
{ ADAU1373_DAI_RECL_VOL(1), 0x00 },
{ ADAU1373_DAI_RECR_VOL(1), 0x00 },
{ ADAU1373_DAI_RECL_VOL(2), 0x00 },
{ ADAU1373_DAI_RECR_VOL(2), 0x00 },
{ ADAU1373_DAC1_PBL_VOL, 0x00 },
{ ADAU1373_DAC1_PBR_VOL, 0x00 },
{ ADAU1373_DAC2_PBL_VOL, 0x00 },
{ ADAU1373_DAC2_PBR_VOL, 0x00 },
{ ADAU1373_ADC_RECL_VOL, 0x00 },
{ ADAU1373_ADC_RECR_VOL, 0x00 },
{ ADAU1373_DMIC_RECL_VOL, 0x00 },
{ ADAU1373_DMIC_RECR_VOL, 0x00 },
{ ADAU1373_VOL_GAIN1, 0x00 },
{ ADAU1373_VOL_GAIN2, 0x00 },
{ ADAU1373_VOL_GAIN3, 0x00 },
{ ADAU1373_HPF_CTRL, 0x00 },
{ ADAU1373_BASS1, 0x00 },
{ ADAU1373_BASS2, 0x00 },
{ ADAU1373_DRC(0) + 0x0, 0x78 },
{ ADAU1373_DRC(0) + 0x1, 0x18 },
{ ADAU1373_DRC(0) + 0x2, 0x00 },
{ ADAU1373_DRC(0) + 0x3, 0x00 },
{ ADAU1373_DRC(0) + 0x4, 0x00 },
{ ADAU1373_DRC(0) + 0x5, 0xc0 },
{ ADAU1373_DRC(0) + 0x6, 0x00 },
{ ADAU1373_DRC(0) + 0x7, 0x00 },
{ ADAU1373_DRC(0) + 0x8, 0x00 },
{ ADAU1373_DRC(0) + 0x9, 0xc0 },
{ ADAU1373_DRC(0) + 0xa, 0x88 },
{ ADAU1373_DRC(0) + 0xb, 0x7a },
{ ADAU1373_DRC(0) + 0xc, 0xdf },
{ ADAU1373_DRC(0) + 0xd, 0x20 },
{ ADAU1373_DRC(0) + 0xe, 0x00 },
{ ADAU1373_DRC(0) + 0xf, 0x00 },
{ ADAU1373_DRC(1) + 0x0, 0x78 },
{ ADAU1373_DRC(1) + 0x1, 0x18 },
{ ADAU1373_DRC(1) + 0x2, 0x00 },
{ ADAU1373_DRC(1) + 0x3, 0x00 },
{ ADAU1373_DRC(1) + 0x4, 0x00 },
{ ADAU1373_DRC(1) + 0x5, 0xc0 },
{ ADAU1373_DRC(1) + 0x6, 0x00 },
{ ADAU1373_DRC(1) + 0x7, 0x00 },
{ ADAU1373_DRC(1) + 0x8, 0x00 },
{ ADAU1373_DRC(1) + 0x9, 0xc0 },
{ ADAU1373_DRC(1) + 0xa, 0x88 },
{ ADAU1373_DRC(1) + 0xb, 0x7a },
{ ADAU1373_DRC(1) + 0xc, 0xdf },
{ ADAU1373_DRC(1) + 0xd, 0x20 },
{ ADAU1373_DRC(1) + 0xe, 0x00 },
{ ADAU1373_DRC(1) + 0xf, 0x00 },
{ ADAU1373_DRC(2) + 0x0, 0x78 },
{ ADAU1373_DRC(2) + 0x1, 0x18 },
{ ADAU1373_DRC(2) + 0x2, 0x00 },
{ ADAU1373_DRC(2) + 0x3, 0x00 },
{ ADAU1373_DRC(2) + 0x4, 0x00 },
{ ADAU1373_DRC(2) + 0x5, 0xc0 },
{ ADAU1373_DRC(2) + 0x6, 0x00 },
{ ADAU1373_DRC(2) + 0x7, 0x00 },
{ ADAU1373_DRC(2) + 0x8, 0x00 },
{ ADAU1373_DRC(2) + 0x9, 0xc0 },
{ ADAU1373_DRC(2) + 0xa, 0x88 },
{ ADAU1373_DRC(2) + 0xb, 0x7a },
{ ADAU1373_DRC(2) + 0xc, 0xdf },
{ ADAU1373_DRC(2) + 0xd, 0x20 },
{ ADAU1373_DRC(2) + 0xe, 0x00 },
{ ADAU1373_DRC(2) + 0xf, 0x00 },
{ ADAU1373_3D_CTRL1, 0x00 },
{ ADAU1373_3D_CTRL2, 0x00 },
{ ADAU1373_FDSP_SEL1, 0x00 },
{ ADAU1373_FDSP_SEL2, 0x00 },
{ ADAU1373_FDSP_SEL2, 0x00 },
{ ADAU1373_FDSP_SEL4, 0x00 },
{ ADAU1373_DIGMICCTRL, 0x00 },
{ ADAU1373_DIGEN, 0x00 },
};
static const DECLARE_TLV_DB_RANGE(adau1373_out_tlv,
0, 7, TLV_DB_SCALE_ITEM(-7900, 400, 1),
8, 15, TLV_DB_SCALE_ITEM(-4700, 300, 0),
16, 23, TLV_DB_SCALE_ITEM(-2300, 200, 0),
24, 31, TLV_DB_SCALE_ITEM(-700, 100, 0)
);
static const DECLARE_TLV_DB_MINMAX(adau1373_digital_tlv, -9563, 0);
static const DECLARE_TLV_DB_SCALE(adau1373_in_pga_tlv, -1300, 100, 1);
static const DECLARE_TLV_DB_SCALE(adau1373_ep_tlv, -600, 600, 1);
static const DECLARE_TLV_DB_SCALE(adau1373_input_boost_tlv, 0, 2000, 0);
static const DECLARE_TLV_DB_SCALE(adau1373_gain_boost_tlv, 0, 600, 0);
static const DECLARE_TLV_DB_SCALE(adau1373_speaker_boost_tlv, 1200, 600, 0);
static const char *adau1373_fdsp_sel_text[] = {
"None",
"Channel 1",
"Channel 2",
"Channel 3",
"Channel 4",
"Channel 5",
};
static SOC_ENUM_SINGLE_DECL(adau1373_drc1_channel_enum,
ADAU1373_FDSP_SEL1, 4, adau1373_fdsp_sel_text);
static SOC_ENUM_SINGLE_DECL(adau1373_drc2_channel_enum,
ADAU1373_FDSP_SEL1, 0, adau1373_fdsp_sel_text);
static SOC_ENUM_SINGLE_DECL(adau1373_drc3_channel_enum,
ADAU1373_FDSP_SEL2, 0, adau1373_fdsp_sel_text);
static SOC_ENUM_SINGLE_DECL(adau1373_hpf_channel_enum,
ADAU1373_FDSP_SEL3, 0, adau1373_fdsp_sel_text);
static SOC_ENUM_SINGLE_DECL(adau1373_bass_channel_enum,
ADAU1373_FDSP_SEL4, 4, adau1373_fdsp_sel_text);
static const char *adau1373_hpf_cutoff_text[] = {
"3.7Hz", "50Hz", "100Hz", "150Hz", "200Hz", "250Hz", "300Hz", "350Hz",
"400Hz", "450Hz", "500Hz", "550Hz", "600Hz", "650Hz", "700Hz", "750Hz",
"800Hz",
};
static SOC_ENUM_SINGLE_DECL(adau1373_hpf_cutoff_enum,
ADAU1373_HPF_CTRL, 3, adau1373_hpf_cutoff_text);
static const char *adau1373_bass_lpf_cutoff_text[] = {
"801Hz", "1001Hz",
};
static const char *adau1373_bass_clip_level_text[] = {
"0.125", "0.250", "0.370", "0.500", "0.625", "0.750", "0.875",
};
static const unsigned int adau1373_bass_clip_level_values[] = {
1, 2, 3, 4, 5, 6, 7,
};
static const char *adau1373_bass_hpf_cutoff_text[] = {
"158Hz", "232Hz", "347Hz", "520Hz",
};
static const DECLARE_TLV_DB_RANGE(adau1373_bass_tlv,
0, 2, TLV_DB_SCALE_ITEM(-600, 600, 1),
3, 4, TLV_DB_SCALE_ITEM(950, 250, 0),
5, 7, TLV_DB_SCALE_ITEM(1400, 150, 0)
);
static SOC_ENUM_SINGLE_DECL(adau1373_bass_lpf_cutoff_enum,
ADAU1373_BASS1, 5, adau1373_bass_lpf_cutoff_text);
static SOC_VALUE_ENUM_SINGLE_DECL(adau1373_bass_clip_level_enum,
ADAU1373_BASS1, 2, 7, adau1373_bass_clip_level_text,
adau1373_bass_clip_level_values);
static SOC_ENUM_SINGLE_DECL(adau1373_bass_hpf_cutoff_enum,
ADAU1373_BASS1, 0, adau1373_bass_hpf_cutoff_text);
static const char *adau1373_3d_level_text[] = {
"0%", "6.67%", "13.33%", "20%", "26.67%", "33.33%",
"40%", "46.67%", "53.33%", "60%", "66.67%", "73.33%",
"80%", "86.67", "99.33%", "100%"
};
static const char *adau1373_3d_cutoff_text[] = {
"No 3D", "0.03125 fs", "0.04583 fs", "0.075 fs", "0.11458 fs",
"0.16875 fs", "0.27083 fs"
};
static SOC_ENUM_SINGLE_DECL(adau1373_3d_level_enum,
ADAU1373_3D_CTRL1, 4, adau1373_3d_level_text);
static SOC_ENUM_SINGLE_DECL(adau1373_3d_cutoff_enum,
ADAU1373_3D_CTRL1, 0, adau1373_3d_cutoff_text);
static const DECLARE_TLV_DB_RANGE(adau1373_3d_tlv,
0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1, 7, TLV_DB_LINEAR_ITEM(-1800, -120)
);
static const char *adau1373_lr_mux_text[] = {
"Mute",
"Right Channel (L+R)",
"Left Channel (L+R)",
"Stereo",
};
static SOC_ENUM_SINGLE_DECL(adau1373_lineout1_lr_mux_enum,
ADAU1373_OUTPUT_CTRL, 4, adau1373_lr_mux_text);
static SOC_ENUM_SINGLE_DECL(adau1373_lineout2_lr_mux_enum,
ADAU1373_OUTPUT_CTRL, 6, adau1373_lr_mux_text);
static SOC_ENUM_SINGLE_DECL(adau1373_speaker_lr_mux_enum,
ADAU1373_LS_CTRL, 4, adau1373_lr_mux_text);
static const struct snd_kcontrol_new adau1373_controls[] = {
SOC_DOUBLE_R_TLV("AIF1 Capture Volume", ADAU1373_DAI_RECL_VOL(0),
ADAU1373_DAI_RECR_VOL(0), 0, 0xff, 1, adau1373_digital_tlv),
SOC_DOUBLE_R_TLV("AIF2 Capture Volume", ADAU1373_DAI_RECL_VOL(1),
ADAU1373_DAI_RECR_VOL(1), 0, 0xff, 1, adau1373_digital_tlv),
SOC_DOUBLE_R_TLV("AIF3 Capture Volume", ADAU1373_DAI_RECL_VOL(2),
ADAU1373_DAI_RECR_VOL(2), 0, 0xff, 1, adau1373_digital_tlv),
SOC_DOUBLE_R_TLV("ADC Capture Volume", ADAU1373_ADC_RECL_VOL,
ADAU1373_ADC_RECR_VOL, 0, 0xff, 1, adau1373_digital_tlv),
SOC_DOUBLE_R_TLV("DMIC Capture Volume", ADAU1373_DMIC_RECL_VOL,
ADAU1373_DMIC_RECR_VOL, 0, 0xff, 1, adau1373_digital_tlv),
SOC_DOUBLE_R_TLV("AIF1 Playback Volume", ADAU1373_DAI_PBL_VOL(0),
ADAU1373_DAI_PBR_VOL(0), 0, 0xff, 1, adau1373_digital_tlv),
SOC_DOUBLE_R_TLV("AIF2 Playback Volume", ADAU1373_DAI_PBL_VOL(1),
ADAU1373_DAI_PBR_VOL(1), 0, 0xff, 1, adau1373_digital_tlv),
SOC_DOUBLE_R_TLV("AIF3 Playback Volume", ADAU1373_DAI_PBL_VOL(2),
ADAU1373_DAI_PBR_VOL(2), 0, 0xff, 1, adau1373_digital_tlv),
SOC_DOUBLE_R_TLV("DAC1 Playback Volume", ADAU1373_DAC1_PBL_VOL,
ADAU1373_DAC1_PBR_VOL, 0, 0xff, 1, adau1373_digital_tlv),
SOC_DOUBLE_R_TLV("DAC2 Playback Volume", ADAU1373_DAC2_PBL_VOL,
ADAU1373_DAC2_PBR_VOL, 0, 0xff, 1, adau1373_digital_tlv),
SOC_DOUBLE_R_TLV("Lineout1 Playback Volume", ADAU1373_LLINE_OUT(0),
ADAU1373_RLINE_OUT(0), 0, 0x1f, 0, adau1373_out_tlv),
SOC_DOUBLE_R_TLV("Speaker Playback Volume", ADAU1373_LSPK_OUT,
ADAU1373_RSPK_OUT, 0, 0x1f, 0, adau1373_out_tlv),
SOC_DOUBLE_R_TLV("Headphone Playback Volume", ADAU1373_LHP_OUT,
ADAU1373_RHP_OUT, 0, 0x1f, 0, adau1373_out_tlv),
SOC_DOUBLE_R_TLV("Input 1 Capture Volume", ADAU1373_AINL_CTRL(0),
ADAU1373_AINR_CTRL(0), 0, 0x1f, 0, adau1373_in_pga_tlv),
SOC_DOUBLE_R_TLV("Input 2 Capture Volume", ADAU1373_AINL_CTRL(1),
ADAU1373_AINR_CTRL(1), 0, 0x1f, 0, adau1373_in_pga_tlv),
SOC_DOUBLE_R_TLV("Input 3 Capture Volume", ADAU1373_AINL_CTRL(2),
ADAU1373_AINR_CTRL(2), 0, 0x1f, 0, adau1373_in_pga_tlv),
SOC_DOUBLE_R_TLV("Input 4 Capture Volume", ADAU1373_AINL_CTRL(3),
ADAU1373_AINR_CTRL(3), 0, 0x1f, 0, adau1373_in_pga_tlv),
SOC_SINGLE_TLV("Earpiece Playback Volume", ADAU1373_EP_CTRL, 0, 3, 0,
adau1373_ep_tlv),
SOC_DOUBLE_TLV("AIF3 Boost Playback Volume", ADAU1373_VOL_GAIN1, 4, 5,
1, 0, adau1373_gain_boost_tlv),
SOC_DOUBLE_TLV("AIF2 Boost Playback Volume", ADAU1373_VOL_GAIN1, 2, 3,
1, 0, adau1373_gain_boost_tlv),
SOC_DOUBLE_TLV("AIF1 Boost Playback Volume", ADAU1373_VOL_GAIN1, 0, 1,
1, 0, adau1373_gain_boost_tlv),
SOC_DOUBLE_TLV("AIF3 Boost Capture Volume", ADAU1373_VOL_GAIN2, 4, 5,
1, 0, adau1373_gain_boost_tlv),
SOC_DOUBLE_TLV("AIF2 Boost Capture Volume", ADAU1373_VOL_GAIN2, 2, 3,
1, 0, adau1373_gain_boost_tlv),
SOC_DOUBLE_TLV("AIF1 Boost Capture Volume", ADAU1373_VOL_GAIN2, 0, 1,
1, 0, adau1373_gain_boost_tlv),
SOC_DOUBLE_TLV("DMIC Boost Capture Volume", ADAU1373_VOL_GAIN3, 6, 7,
1, 0, adau1373_gain_boost_tlv),
SOC_DOUBLE_TLV("ADC Boost Capture Volume", ADAU1373_VOL_GAIN3, 4, 5,
1, 0, adau1373_gain_boost_tlv),
SOC_DOUBLE_TLV("DAC2 Boost Playback Volume", ADAU1373_VOL_GAIN3, 2, 3,
1, 0, adau1373_gain_boost_tlv),
SOC_DOUBLE_TLV("DAC1 Boost Playback Volume", ADAU1373_VOL_GAIN3, 0, 1,
1, 0, adau1373_gain_boost_tlv),
SOC_DOUBLE_TLV("Input 1 Boost Capture Volume", ADAU1373_ADC_GAIN, 0, 4,
1, 0, adau1373_input_boost_tlv),
SOC_DOUBLE_TLV("Input 2 Boost Capture Volume", ADAU1373_ADC_GAIN, 1, 5,
1, 0, adau1373_input_boost_tlv),
SOC_DOUBLE_TLV("Input 3 Boost Capture Volume", ADAU1373_ADC_GAIN, 2, 6,
1, 0, adau1373_input_boost_tlv),
SOC_DOUBLE_TLV("Input 4 Boost Capture Volume", ADAU1373_ADC_GAIN, 3, 7,
1, 0, adau1373_input_boost_tlv),
SOC_DOUBLE_TLV("Speaker Boost Playback Volume", ADAU1373_LS_CTRL, 2, 3,
1, 0, adau1373_speaker_boost_tlv),
SOC_ENUM("Lineout1 LR Mux", adau1373_lineout1_lr_mux_enum),
SOC_ENUM("Speaker LR Mux", adau1373_speaker_lr_mux_enum),
SOC_ENUM("HPF Cutoff", adau1373_hpf_cutoff_enum),
SOC_DOUBLE("HPF Switch", ADAU1373_HPF_CTRL, 1, 0, 1, 0),
SOC_ENUM("HPF Channel", adau1373_hpf_channel_enum),
SOC_ENUM("Bass HPF Cutoff", adau1373_bass_hpf_cutoff_enum),
SOC_ENUM("Bass Clip Level Threshold", adau1373_bass_clip_level_enum),
SOC_ENUM("Bass LPF Cutoff", adau1373_bass_lpf_cutoff_enum),
SOC_DOUBLE("Bass Playback Switch", ADAU1373_BASS2, 0, 1, 1, 0),
SOC_SINGLE_TLV("Bass Playback Volume", ADAU1373_BASS2, 2, 7, 0,
adau1373_bass_tlv),
SOC_ENUM("Bass Channel", adau1373_bass_channel_enum),
SOC_ENUM("3D Freq", adau1373_3d_cutoff_enum),
SOC_ENUM("3D Level", adau1373_3d_level_enum),
SOC_SINGLE("3D Playback Switch", ADAU1373_3D_CTRL2, 0, 1, 0),
SOC_SINGLE_TLV("3D Playback Volume", ADAU1373_3D_CTRL2, 2, 7, 0,
adau1373_3d_tlv),
SOC_ENUM("3D Channel", adau1373_bass_channel_enum),
SOC_SINGLE("Zero Cross Switch", ADAU1373_PWDN_CTRL3, 7, 1, 0),
};
static const struct snd_kcontrol_new adau1373_lineout2_controls[] = {
SOC_DOUBLE_R_TLV("Lineout2 Playback Volume", ADAU1373_LLINE_OUT(1),
ADAU1373_RLINE_OUT(1), 0, 0x1f, 0, adau1373_out_tlv),
SOC_ENUM("Lineout2 LR Mux", adau1373_lineout2_lr_mux_enum),
};
static const struct snd_kcontrol_new adau1373_drc_controls[] = {
SOC_ENUM("DRC1 Channel", adau1373_drc1_channel_enum),
SOC_ENUM("DRC2 Channel", adau1373_drc2_channel_enum),
SOC_ENUM("DRC3 Channel", adau1373_drc3_channel_enum),
};
static int adau1373_pll_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
unsigned int pll_id = w->name[3] - '1';
unsigned int val;
if (SND_SOC_DAPM_EVENT_ON(event))
val = ADAU1373_PLL_CTRL6_PLL_EN;
else
val = 0;
regmap_update_bits(adau1373->regmap, ADAU1373_PLL_CTRL6(pll_id),
ADAU1373_PLL_CTRL6_PLL_EN, val);
if (SND_SOC_DAPM_EVENT_ON(event))
mdelay(5);
return 0;
}
static const char *adau1373_decimator_text[] = {
"ADC",
"DMIC1",
};
static SOC_ENUM_SINGLE_VIRT_DECL(adau1373_decimator_enum,
adau1373_decimator_text);
static const struct snd_kcontrol_new adau1373_decimator_mux =
SOC_DAPM_ENUM("Decimator Mux", adau1373_decimator_enum);
static const struct snd_kcontrol_new adau1373_left_adc_mixer_controls[] = {
SOC_DAPM_SINGLE("DAC1 Switch", ADAU1373_LADC_MIXER, 4, 1, 0),
SOC_DAPM_SINGLE("Input 4 Switch", ADAU1373_LADC_MIXER, 3, 1, 0),
SOC_DAPM_SINGLE("Input 3 Switch", ADAU1373_LADC_MIXER, 2, 1, 0),
SOC_DAPM_SINGLE("Input 2 Switch", ADAU1373_LADC_MIXER, 1, 1, 0),
SOC_DAPM_SINGLE("Input 1 Switch", ADAU1373_LADC_MIXER, 0, 1, 0),
};
static const struct snd_kcontrol_new adau1373_right_adc_mixer_controls[] = {
SOC_DAPM_SINGLE("DAC1 Switch", ADAU1373_RADC_MIXER, 4, 1, 0),
SOC_DAPM_SINGLE("Input 4 Switch", ADAU1373_RADC_MIXER, 3, 1, 0),
SOC_DAPM_SINGLE("Input 3 Switch", ADAU1373_RADC_MIXER, 2, 1, 0),
SOC_DAPM_SINGLE("Input 2 Switch", ADAU1373_RADC_MIXER, 1, 1, 0),
SOC_DAPM_SINGLE("Input 1 Switch", ADAU1373_RADC_MIXER, 0, 1, 0),
};
#define DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(_name, _reg) \
const struct snd_kcontrol_new _name[] = { \
SOC_DAPM_SINGLE("Left DAC2 Switch", _reg, 7, 1, 0), \
SOC_DAPM_SINGLE("Right DAC2 Switch", _reg, 6, 1, 0), \
SOC_DAPM_SINGLE("Left DAC1 Switch", _reg, 5, 1, 0), \
SOC_DAPM_SINGLE("Right DAC1 Switch", _reg, 4, 1, 0), \
SOC_DAPM_SINGLE("Input 4 Bypass Switch", _reg, 3, 1, 0), \
SOC_DAPM_SINGLE("Input 3 Bypass Switch", _reg, 2, 1, 0), \
SOC_DAPM_SINGLE("Input 2 Bypass Switch", _reg, 1, 1, 0), \
SOC_DAPM_SINGLE("Input 1 Bypass Switch", _reg, 0, 1, 0), \
}
static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_left_line1_mixer_controls,
ADAU1373_LLINE1_MIX);
static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_right_line1_mixer_controls,
ADAU1373_RLINE1_MIX);
static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_left_line2_mixer_controls,
ADAU1373_LLINE2_MIX);
static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_right_line2_mixer_controls,
ADAU1373_RLINE2_MIX);
static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_left_spk_mixer_controls,
ADAU1373_LSPK_MIX);
static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_right_spk_mixer_controls,
ADAU1373_RSPK_MIX);
static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_ep_mixer_controls,
ADAU1373_EP_MIX);
static const struct snd_kcontrol_new adau1373_left_hp_mixer_controls[] = {
SOC_DAPM_SINGLE("Left DAC1 Switch", ADAU1373_LHP_MIX, 5, 1, 0),
SOC_DAPM_SINGLE("Left DAC2 Switch", ADAU1373_LHP_MIX, 4, 1, 0),
SOC_DAPM_SINGLE("Input 4 Bypass Switch", ADAU1373_LHP_MIX, 3, 1, 0),
SOC_DAPM_SINGLE("Input 3 Bypass Switch", ADAU1373_LHP_MIX, 2, 1, 0),
SOC_DAPM_SINGLE("Input 2 Bypass Switch", ADAU1373_LHP_MIX, 1, 1, 0),
SOC_DAPM_SINGLE("Input 1 Bypass Switch", ADAU1373_LHP_MIX, 0, 1, 0),
};
static const struct snd_kcontrol_new adau1373_right_hp_mixer_controls[] = {
SOC_DAPM_SINGLE("Right DAC1 Switch", ADAU1373_RHP_MIX, 5, 1, 0),
SOC_DAPM_SINGLE("Right DAC2 Switch", ADAU1373_RHP_MIX, 4, 1, 0),
SOC_DAPM_SINGLE("Input 4 Bypass Switch", ADAU1373_RHP_MIX, 3, 1, 0),
SOC_DAPM_SINGLE("Input 3 Bypass Switch", ADAU1373_RHP_MIX, 2, 1, 0),
SOC_DAPM_SINGLE("Input 2 Bypass Switch", ADAU1373_RHP_MIX, 1, 1, 0),
SOC_DAPM_SINGLE("Input 1 Bypass Switch", ADAU1373_RHP_MIX, 0, 1, 0),
};
#define DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(_name, _reg) \
const struct snd_kcontrol_new _name[] = { \
SOC_DAPM_SINGLE("DMIC2 Swapped Switch", _reg, 6, 1, 0), \
SOC_DAPM_SINGLE("DMIC2 Switch", _reg, 5, 1, 0), \
SOC_DAPM_SINGLE("ADC/DMIC1 Swapped Switch", _reg, 4, 1, 0), \
SOC_DAPM_SINGLE("ADC/DMIC1 Switch", _reg, 3, 1, 0), \
SOC_DAPM_SINGLE("AIF3 Switch", _reg, 2, 1, 0), \
SOC_DAPM_SINGLE("AIF2 Switch", _reg, 1, 1, 0), \
SOC_DAPM_SINGLE("AIF1 Switch", _reg, 0, 1, 0), \
}
static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel1_mixer_controls,
ADAU1373_DIN_MIX_CTRL(0));
static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel2_mixer_controls,
ADAU1373_DIN_MIX_CTRL(1));
static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel3_mixer_controls,
ADAU1373_DIN_MIX_CTRL(2));
static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel4_mixer_controls,
ADAU1373_DIN_MIX_CTRL(3));
static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel5_mixer_controls,
ADAU1373_DIN_MIX_CTRL(4));
#define DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(_name, _reg) \
const struct snd_kcontrol_new _name[] = { \
SOC_DAPM_SINGLE("DSP Channel5 Switch", _reg, 4, 1, 0), \
SOC_DAPM_SINGLE("DSP Channel4 Switch", _reg, 3, 1, 0), \
SOC_DAPM_SINGLE("DSP Channel3 Switch", _reg, 2, 1, 0), \
SOC_DAPM_SINGLE("DSP Channel2 Switch", _reg, 1, 1, 0), \
SOC_DAPM_SINGLE("DSP Channel1 Switch", _reg, 0, 1, 0), \
}
static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_aif1_mixer_controls,
ADAU1373_DOUT_MIX_CTRL(0));
static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_aif2_mixer_controls,
ADAU1373_DOUT_MIX_CTRL(1));
static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_aif3_mixer_controls,
ADAU1373_DOUT_MIX_CTRL(2));
static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_dac1_mixer_controls,
ADAU1373_DOUT_MIX_CTRL(3));
static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_dac2_mixer_controls,
ADAU1373_DOUT_MIX_CTRL(4));
static const struct snd_soc_dapm_widget adau1373_dapm_widgets[] = {
/* Datasheet claims Left ADC is bit 6 and Right ADC is bit 7, but that
* doesn't seem to be the case. */
SND_SOC_DAPM_ADC("Left ADC", NULL, ADAU1373_PWDN_CTRL1, 7, 0),
SND_SOC_DAPM_ADC("Right ADC", NULL, ADAU1373_PWDN_CTRL1, 6, 0),
SND_SOC_DAPM_ADC("DMIC1", NULL, ADAU1373_DIGMICCTRL, 0, 0),
SND_SOC_DAPM_ADC("DMIC2", NULL, ADAU1373_DIGMICCTRL, 2, 0),
SND_SOC_DAPM_MUX("Decimator Mux", SND_SOC_NOPM, 0, 0,
&adau1373_decimator_mux),
SND_SOC_DAPM_SUPPLY("MICBIAS2", ADAU1373_PWDN_CTRL1, 5, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS1", ADAU1373_PWDN_CTRL1, 4, 0, NULL, 0),
SND_SOC_DAPM_PGA("IN4PGA", ADAU1373_PWDN_CTRL1, 3, 0, NULL, 0),
SND_SOC_DAPM_PGA("IN3PGA", ADAU1373_PWDN_CTRL1, 2, 0, NULL, 0),
SND_SOC_DAPM_PGA("IN2PGA", ADAU1373_PWDN_CTRL1, 1, 0, NULL, 0),
SND_SOC_DAPM_PGA("IN1PGA", ADAU1373_PWDN_CTRL1, 0, 0, NULL, 0),
SND_SOC_DAPM_DAC("Left DAC2", NULL, ADAU1373_PWDN_CTRL2, 7, 0),
SND_SOC_DAPM_DAC("Right DAC2", NULL, ADAU1373_PWDN_CTRL2, 6, 0),
SND_SOC_DAPM_DAC("Left DAC1", NULL, ADAU1373_PWDN_CTRL2, 5, 0),
SND_SOC_DAPM_DAC("Right DAC1", NULL, ADAU1373_PWDN_CTRL2, 4, 0),
SOC_MIXER_ARRAY("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
adau1373_left_adc_mixer_controls),
SOC_MIXER_ARRAY("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
adau1373_right_adc_mixer_controls),
SOC_MIXER_ARRAY("Left Lineout2 Mixer", ADAU1373_PWDN_CTRL2, 3, 0,
adau1373_left_line2_mixer_controls),
SOC_MIXER_ARRAY("Right Lineout2 Mixer", ADAU1373_PWDN_CTRL2, 2, 0,
adau1373_right_line2_mixer_controls),
SOC_MIXER_ARRAY("Left Lineout1 Mixer", ADAU1373_PWDN_CTRL2, 1, 0,
adau1373_left_line1_mixer_controls),
SOC_MIXER_ARRAY("Right Lineout1 Mixer", ADAU1373_PWDN_CTRL2, 0, 0,
adau1373_right_line1_mixer_controls),
SOC_MIXER_ARRAY("Earpiece Mixer", ADAU1373_PWDN_CTRL3, 4, 0,
adau1373_ep_mixer_controls),
SOC_MIXER_ARRAY("Left Speaker Mixer", ADAU1373_PWDN_CTRL3, 3, 0,
adau1373_left_spk_mixer_controls),
SOC_MIXER_ARRAY("Right Speaker Mixer", ADAU1373_PWDN_CTRL3, 2, 0,
adau1373_right_spk_mixer_controls),
SOC_MIXER_ARRAY("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
adau1373_left_hp_mixer_controls),
SOC_MIXER_ARRAY("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
adau1373_right_hp_mixer_controls),
SND_SOC_DAPM_SUPPLY("Headphone Enable", ADAU1373_PWDN_CTRL3, 1, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("AIF1 CLK", ADAU1373_SRC_DAI_CTRL(0), 0, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("AIF2 CLK", ADAU1373_SRC_DAI_CTRL(1), 0, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("AIF3 CLK", ADAU1373_SRC_DAI_CTRL(2), 0, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("AIF1 IN SRC", ADAU1373_SRC_DAI_CTRL(0), 2, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("AIF1 OUT SRC", ADAU1373_SRC_DAI_CTRL(0), 1, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("AIF2 IN SRC", ADAU1373_SRC_DAI_CTRL(1), 2, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("AIF2 OUT SRC", ADAU1373_SRC_DAI_CTRL(1), 1, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("AIF3 IN SRC", ADAU1373_SRC_DAI_CTRL(2), 2, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("AIF3 OUT SRC", ADAU1373_SRC_DAI_CTRL(2), 1, 0,
NULL, 0),
SND_SOC_DAPM_AIF_IN("AIF1 IN", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1 OUT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIF2 IN", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF2 OUT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIF3 IN", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF3 OUT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
SOC_MIXER_ARRAY("DSP Channel1 Mixer", SND_SOC_NOPM, 0, 0,
adau1373_dsp_channel1_mixer_controls),
SOC_MIXER_ARRAY("DSP Channel2 Mixer", SND_SOC_NOPM, 0, 0,
adau1373_dsp_channel2_mixer_controls),
SOC_MIXER_ARRAY("DSP Channel3 Mixer", SND_SOC_NOPM, 0, 0,
adau1373_dsp_channel3_mixer_controls),
SOC_MIXER_ARRAY("DSP Channel4 Mixer", SND_SOC_NOPM, 0, 0,
adau1373_dsp_channel4_mixer_controls),
SOC_MIXER_ARRAY("DSP Channel5 Mixer", SND_SOC_NOPM, 0, 0,
adau1373_dsp_channel5_mixer_controls),
SOC_MIXER_ARRAY("AIF1 Mixer", SND_SOC_NOPM, 0, 0,
adau1373_aif1_mixer_controls),
SOC_MIXER_ARRAY("AIF2 Mixer", SND_SOC_NOPM, 0, 0,
adau1373_aif2_mixer_controls),
SOC_MIXER_ARRAY("AIF3 Mixer", SND_SOC_NOPM, 0, 0,
adau1373_aif3_mixer_controls),
SOC_MIXER_ARRAY("DAC1 Mixer", SND_SOC_NOPM, 0, 0,
adau1373_dac1_mixer_controls),
SOC_MIXER_ARRAY("DAC2 Mixer", SND_SOC_NOPM, 0, 0,
adau1373_dac2_mixer_controls),
SND_SOC_DAPM_SUPPLY("DSP", ADAU1373_DIGEN, 4, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Recording Engine B", ADAU1373_DIGEN, 3, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Recording Engine A", ADAU1373_DIGEN, 2, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Playback Engine B", ADAU1373_DIGEN, 1, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Playback Engine A", ADAU1373_DIGEN, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PLL1", SND_SOC_NOPM, 0, 0, adau1373_pll_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("PLL2", SND_SOC_NOPM, 0, 0, adau1373_pll_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("SYSCLK1", ADAU1373_CLK_SRC_DIV(0), 7, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("SYSCLK2", ADAU1373_CLK_SRC_DIV(1), 7, 0, NULL, 0),
SND_SOC_DAPM_INPUT("AIN1L"),
SND_SOC_DAPM_INPUT("AIN1R"),
SND_SOC_DAPM_INPUT("AIN2L"),
SND_SOC_DAPM_INPUT("AIN2R"),
SND_SOC_DAPM_INPUT("AIN3L"),
SND_SOC_DAPM_INPUT("AIN3R"),
SND_SOC_DAPM_INPUT("AIN4L"),
SND_SOC_DAPM_INPUT("AIN4R"),
SND_SOC_DAPM_INPUT("DMIC1DAT"),
SND_SOC_DAPM_INPUT("DMIC2DAT"),
SND_SOC_DAPM_OUTPUT("LOUT1L"),
SND_SOC_DAPM_OUTPUT("LOUT1R"),
SND_SOC_DAPM_OUTPUT("LOUT2L"),
SND_SOC_DAPM_OUTPUT("LOUT2R"),
SND_SOC_DAPM_OUTPUT("HPL"),
SND_SOC_DAPM_OUTPUT("HPR"),
SND_SOC_DAPM_OUTPUT("SPKL"),
SND_SOC_DAPM_OUTPUT("SPKR"),
SND_SOC_DAPM_OUTPUT("EP"),
};
static int adau1373_check_aif_clk(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
unsigned int dai;
const char *clk;
dai = sink->name[3] - '1';
if (!adau1373->dais[dai].clock_provider)
return 0;
if (adau1373->dais[dai].clk_src == ADAU1373_CLK_SRC_PLL1)
clk = "SYSCLK1";
else
clk = "SYSCLK2";
return strcmp(source->name, clk) == 0;
}
static int adau1373_check_src(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
unsigned int dai;
dai = sink->name[3] - '1';
return adau1373->dais[dai].enable_src;
}
#define DSP_CHANNEL_MIXER_ROUTES(_sink) \
{ _sink, "DMIC2 Swapped Switch", "DMIC2" }, \
{ _sink, "DMIC2 Switch", "DMIC2" }, \
{ _sink, "ADC/DMIC1 Swapped Switch", "Decimator Mux" }, \
{ _sink, "ADC/DMIC1 Switch", "Decimator Mux" }, \
{ _sink, "AIF1 Switch", "AIF1 IN" }, \
{ _sink, "AIF2 Switch", "AIF2 IN" }, \
{ _sink, "AIF3 Switch", "AIF3 IN" }
#define DSP_OUTPUT_MIXER_ROUTES(_sink) \
{ _sink, "DSP Channel1 Switch", "DSP Channel1 Mixer" }, \
{ _sink, "DSP Channel2 Switch", "DSP Channel2 Mixer" }, \
{ _sink, "DSP Channel3 Switch", "DSP Channel3 Mixer" }, \
{ _sink, "DSP Channel4 Switch", "DSP Channel4 Mixer" }, \
{ _sink, "DSP Channel5 Switch", "DSP Channel5 Mixer" }
#define LEFT_OUTPUT_MIXER_ROUTES(_sink) \
{ _sink, "Right DAC2 Switch", "Right DAC2" }, \
{ _sink, "Left DAC2 Switch", "Left DAC2" }, \
{ _sink, "Right DAC1 Switch", "Right DAC1" }, \
{ _sink, "Left DAC1 Switch", "Left DAC1" }, \
{ _sink, "Input 1 Bypass Switch", "IN1PGA" }, \
{ _sink, "Input 2 Bypass Switch", "IN2PGA" }, \
{ _sink, "Input 3 Bypass Switch", "IN3PGA" }, \
{ _sink, "Input 4 Bypass Switch", "IN4PGA" }
#define RIGHT_OUTPUT_MIXER_ROUTES(_sink) \
{ _sink, "Right DAC2 Switch", "Right DAC2" }, \
{ _sink, "Left DAC2 Switch", "Left DAC2" }, \
{ _sink, "Right DAC1 Switch", "Right DAC1" }, \
{ _sink, "Left DAC1 Switch", "Left DAC1" }, \
{ _sink, "Input 1 Bypass Switch", "IN1PGA" }, \
{ _sink, "Input 2 Bypass Switch", "IN2PGA" }, \
{ _sink, "Input 3 Bypass Switch", "IN3PGA" }, \
{ _sink, "Input 4 Bypass Switch", "IN4PGA" }
static const struct snd_soc_dapm_route adau1373_dapm_routes[] = {
{ "Left ADC Mixer", "DAC1 Switch", "Left DAC1" },
{ "Left ADC Mixer", "Input 1 Switch", "IN1PGA" },
{ "Left ADC Mixer", "Input 2 Switch", "IN2PGA" },
{ "Left ADC Mixer", "Input 3 Switch", "IN3PGA" },
{ "Left ADC Mixer", "Input 4 Switch", "IN4PGA" },
{ "Right ADC Mixer", "DAC1 Switch", "Right DAC1" },
{ "Right ADC Mixer", "Input 1 Switch", "IN1PGA" },
{ "Right ADC Mixer", "Input 2 Switch", "IN2PGA" },
{ "Right ADC Mixer", "Input 3 Switch", "IN3PGA" },
{ "Right ADC Mixer", "Input 4 Switch", "IN4PGA" },
{ "Left ADC", NULL, "Left ADC Mixer" },
{ "Right ADC", NULL, "Right ADC Mixer" },
{ "Decimator Mux", "ADC", "Left ADC" },
{ "Decimator Mux", "ADC", "Right ADC" },
{ "Decimator Mux", "DMIC1", "DMIC1" },
DSP_CHANNEL_MIXER_ROUTES("DSP Channel1 Mixer"),
DSP_CHANNEL_MIXER_ROUTES("DSP Channel2 Mixer"),
DSP_CHANNEL_MIXER_ROUTES("DSP Channel3 Mixer"),
DSP_CHANNEL_MIXER_ROUTES("DSP Channel4 Mixer"),
DSP_CHANNEL_MIXER_ROUTES("DSP Channel5 Mixer"),
DSP_OUTPUT_MIXER_ROUTES("AIF1 Mixer"),
DSP_OUTPUT_MIXER_ROUTES("AIF2 Mixer"),
DSP_OUTPUT_MIXER_ROUTES("AIF3 Mixer"),
DSP_OUTPUT_MIXER_ROUTES("DAC1 Mixer"),
DSP_OUTPUT_MIXER_ROUTES("DAC2 Mixer"),
{ "AIF1 OUT", NULL, "AIF1 Mixer" },
{ "AIF2 OUT", NULL, "AIF2 Mixer" },
{ "AIF3 OUT", NULL, "AIF3 Mixer" },
{ "Left DAC1", NULL, "DAC1 Mixer" },
{ "Right DAC1", NULL, "DAC1 Mixer" },
{ "Left DAC2", NULL, "DAC2 Mixer" },
{ "Right DAC2", NULL, "DAC2 Mixer" },
LEFT_OUTPUT_MIXER_ROUTES("Left Lineout1 Mixer"),
RIGHT_OUTPUT_MIXER_ROUTES("Right Lineout1 Mixer"),
LEFT_OUTPUT_MIXER_ROUTES("Left Lineout2 Mixer"),
RIGHT_OUTPUT_MIXER_ROUTES("Right Lineout2 Mixer"),
LEFT_OUTPUT_MIXER_ROUTES("Left Speaker Mixer"),
RIGHT_OUTPUT_MIXER_ROUTES("Right Speaker Mixer"),
{ "Left Headphone Mixer", "Left DAC2 Switch", "Left DAC2" },
{ "Left Headphone Mixer", "Left DAC1 Switch", "Left DAC1" },
{ "Left Headphone Mixer", "Input 1 Bypass Switch", "IN1PGA" },
{ "Left Headphone Mixer", "Input 2 Bypass Switch", "IN2PGA" },
{ "Left Headphone Mixer", "Input 3 Bypass Switch", "IN3PGA" },
{ "Left Headphone Mixer", "Input 4 Bypass Switch", "IN4PGA" },
{ "Right Headphone Mixer", "Right DAC2 Switch", "Right DAC2" },
{ "Right Headphone Mixer", "Right DAC1 Switch", "Right DAC1" },
{ "Right Headphone Mixer", "Input 1 Bypass Switch", "IN1PGA" },
{ "Right Headphone Mixer", "Input 2 Bypass Switch", "IN2PGA" },
{ "Right Headphone Mixer", "Input 3 Bypass Switch", "IN3PGA" },
{ "Right Headphone Mixer", "Input 4 Bypass Switch", "IN4PGA" },
{ "Left Headphone Mixer", NULL, "Headphone Enable" },
{ "Right Headphone Mixer", NULL, "Headphone Enable" },
{ "Earpiece Mixer", "Right DAC2 Switch", "Right DAC2" },
{ "Earpiece Mixer", "Left DAC2 Switch", "Left DAC2" },
{ "Earpiece Mixer", "Right DAC1 Switch", "Right DAC1" },
{ "Earpiece Mixer", "Left DAC1 Switch", "Left DAC1" },
{ "Earpiece Mixer", "Input 1 Bypass Switch", "IN1PGA" },
{ "Earpiece Mixer", "Input 2 Bypass Switch", "IN2PGA" },
{ "Earpiece Mixer", "Input 3 Bypass Switch", "IN3PGA" },
{ "Earpiece Mixer", "Input 4 Bypass Switch", "IN4PGA" },
{ "LOUT1L", NULL, "Left Lineout1 Mixer" },
{ "LOUT1R", NULL, "Right Lineout1 Mixer" },
{ "LOUT2L", NULL, "Left Lineout2 Mixer" },
{ "LOUT2R", NULL, "Right Lineout2 Mixer" },
{ "SPKL", NULL, "Left Speaker Mixer" },
{ "SPKR", NULL, "Right Speaker Mixer" },
{ "HPL", NULL, "Left Headphone Mixer" },
{ "HPR", NULL, "Right Headphone Mixer" },
{ "EP", NULL, "Earpiece Mixer" },
{ "IN1PGA", NULL, "AIN1L" },
{ "IN2PGA", NULL, "AIN2L" },
{ "IN3PGA", NULL, "AIN3L" },
{ "IN4PGA", NULL, "AIN4L" },
{ "IN1PGA", NULL, "AIN1R" },
{ "IN2PGA", NULL, "AIN2R" },
{ "IN3PGA", NULL, "AIN3R" },
{ "IN4PGA", NULL, "AIN4R" },
{ "SYSCLK1", NULL, "PLL1" },
{ "SYSCLK2", NULL, "PLL2" },
{ "Left DAC1", NULL, "SYSCLK1" },
{ "Right DAC1", NULL, "SYSCLK1" },
{ "Left DAC2", NULL, "SYSCLK1" },
{ "Right DAC2", NULL, "SYSCLK1" },
{ "Left ADC", NULL, "SYSCLK1" },
{ "Right ADC", NULL, "SYSCLK1" },
{ "DSP", NULL, "SYSCLK1" },
{ "AIF1 Mixer", NULL, "DSP" },
{ "AIF2 Mixer", NULL, "DSP" },
{ "AIF3 Mixer", NULL, "DSP" },
{ "DAC1 Mixer", NULL, "DSP" },
{ "DAC2 Mixer", NULL, "DSP" },
{ "DAC1 Mixer", NULL, "Playback Engine A" },
{ "DAC2 Mixer", NULL, "Playback Engine B" },
{ "Left ADC Mixer", NULL, "Recording Engine A" },
{ "Right ADC Mixer", NULL, "Recording Engine A" },
{ "AIF1 CLK", NULL, "SYSCLK1", adau1373_check_aif_clk },
{ "AIF2 CLK", NULL, "SYSCLK1", adau1373_check_aif_clk },
{ "AIF3 CLK", NULL, "SYSCLK1", adau1373_check_aif_clk },
{ "AIF1 CLK", NULL, "SYSCLK2", adau1373_check_aif_clk },
{ "AIF2 CLK", NULL, "SYSCLK2", adau1373_check_aif_clk },
{ "AIF3 CLK", NULL, "SYSCLK2", adau1373_check_aif_clk },
{ "AIF1 IN", NULL, "AIF1 CLK" },
{ "AIF1 OUT", NULL, "AIF1 CLK" },
{ "AIF2 IN", NULL, "AIF2 CLK" },
{ "AIF2 OUT", NULL, "AIF2 CLK" },
{ "AIF3 IN", NULL, "AIF3 CLK" },
{ "AIF3 OUT", NULL, "AIF3 CLK" },
{ "AIF1 IN", NULL, "AIF1 IN SRC", adau1373_check_src },
{ "AIF1 OUT", NULL, "AIF1 OUT SRC", adau1373_check_src },
{ "AIF2 IN", NULL, "AIF2 IN SRC", adau1373_check_src },
{ "AIF2 OUT", NULL, "AIF2 OUT SRC", adau1373_check_src },
{ "AIF3 IN", NULL, "AIF3 IN SRC", adau1373_check_src },
{ "AIF3 OUT", NULL, "AIF3 OUT SRC", adau1373_check_src },
{ "DMIC1", NULL, "DMIC1DAT" },
{ "DMIC1", NULL, "SYSCLK1" },
{ "DMIC1", NULL, "Recording Engine A" },
{ "DMIC2", NULL, "DMIC2DAT" },
{ "DMIC2", NULL, "SYSCLK1" },
{ "DMIC2", NULL, "Recording Engine B" },
};
static int adau1373_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
struct adau1373_dai *adau1373_dai = &adau1373->dais[dai->id];
unsigned int div;
unsigned int freq;
unsigned int ctrl;
freq = adau1373_dai->sysclk;
if (freq % params_rate(params) != 0)
return -EINVAL;
switch (freq / params_rate(params)) {
case 1024: /* sysclk / 256 */
div = 0;
break;
case 1536: /* 2/3 sysclk / 256 */
div = 1;
break;
case 2048: /* 1/2 sysclk / 256 */
div = 2;
break;
case 3072: /* 1/3 sysclk / 256 */
div = 3;
break;
case 4096: /* 1/4 sysclk / 256 */
div = 4;
break;
case 6144: /* 1/6 sysclk / 256 */
div = 5;
break;
case 5632: /* 2/11 sysclk / 256 */
div = 6;
break;
default:
return -EINVAL;
}
adau1373_dai->enable_src = (div != 0);
regmap_update_bits(adau1373->regmap, ADAU1373_BCLKDIV(dai->id),
ADAU1373_BCLKDIV_SR_MASK | ADAU1373_BCLKDIV_BCLK_MASK,
(div << 2) | ADAU1373_BCLKDIV_64);
switch (params_width(params)) {
case 16:
ctrl = ADAU1373_DAI_WLEN_16;
break;
case 20:
ctrl = ADAU1373_DAI_WLEN_20;
break;
case 24:
ctrl = ADAU1373_DAI_WLEN_24;
break;
case 32:
ctrl = ADAU1373_DAI_WLEN_32;
break;
default:
return -EINVAL;
}
return regmap_update_bits(adau1373->regmap, ADAU1373_DAI(dai->id),
ADAU1373_DAI_WLEN_MASK, ctrl);
}
static int adau1373_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
struct adau1373_dai *adau1373_dai = &adau1373->dais[dai->id];
unsigned int ctrl;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
ctrl = ADAU1373_DAI_MASTER;
adau1373_dai->clock_provider = true;
break;
case SND_SOC_DAIFMT_CBC_CFC:
ctrl = 0;
adau1373_dai->clock_provider = false;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
ctrl |= ADAU1373_DAI_FORMAT_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
ctrl |= ADAU1373_DAI_FORMAT_LEFT_J;
break;
case SND_SOC_DAIFMT_RIGHT_J:
ctrl |= ADAU1373_DAI_FORMAT_RIGHT_J;
break;
case SND_SOC_DAIFMT_DSP_B:
ctrl |= ADAU1373_DAI_FORMAT_DSP;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
ctrl |= ADAU1373_DAI_INVERT_BCLK;
break;
case SND_SOC_DAIFMT_NB_IF:
ctrl |= ADAU1373_DAI_INVERT_LRCLK;
break;
case SND_SOC_DAIFMT_IB_IF:
ctrl |= ADAU1373_DAI_INVERT_LRCLK | ADAU1373_DAI_INVERT_BCLK;
break;
default:
return -EINVAL;
}
regmap_update_bits(adau1373->regmap, ADAU1373_DAI(dai->id),
~ADAU1373_DAI_WLEN_MASK, ctrl);
return 0;
}
static int adau1373_set_dai_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct adau1373 *adau1373 = snd_soc_component_get_drvdata(dai->component);
struct adau1373_dai *adau1373_dai = &adau1373->dais[dai->id];
switch (clk_id) {
case ADAU1373_CLK_SRC_PLL1:
case ADAU1373_CLK_SRC_PLL2:
break;
default:
return -EINVAL;
}
adau1373_dai->sysclk = freq;
adau1373_dai->clk_src = clk_id;
regmap_update_bits(adau1373->regmap, ADAU1373_BCLKDIV(dai->id),
ADAU1373_BCLKDIV_SOURCE, clk_id << 5);
return 0;
}
static const struct snd_soc_dai_ops adau1373_dai_ops = {
.hw_params = adau1373_hw_params,
.set_sysclk = adau1373_set_dai_sysclk,
.set_fmt = adau1373_set_dai_fmt,
};
#define ADAU1373_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver adau1373_dai_driver[] = {
{
.id = 0,
.name = "adau1373-aif1",
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = ADAU1373_FORMATS,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = ADAU1373_FORMATS,
},
.ops = &adau1373_dai_ops,
.symmetric_rate = 1,
},
{
.id = 1,
.name = "adau1373-aif2",
.playback = {
.stream_name = "AIF2 Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = ADAU1373_FORMATS,
},
.capture = {
.stream_name = "AIF2 Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = ADAU1373_FORMATS,
},
.ops = &adau1373_dai_ops,
.symmetric_rate = 1,
},
{
.id = 2,
.name = "adau1373-aif3",
.playback = {
.stream_name = "AIF3 Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = ADAU1373_FORMATS,
},
.capture = {
.stream_name = "AIF3 Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = ADAU1373_FORMATS,
},
.ops = &adau1373_dai_ops,
.symmetric_rate = 1,
},
};
static int adau1373_set_pll(struct snd_soc_component *component, int pll_id,
int source, unsigned int freq_in, unsigned int freq_out)
{
struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
unsigned int dpll_div = 0;
uint8_t pll_regs[5];
int ret;
switch (pll_id) {
case ADAU1373_PLL1:
case ADAU1373_PLL2:
break;
default:
return -EINVAL;
}
switch (source) {
case ADAU1373_PLL_SRC_BCLK1:
case ADAU1373_PLL_SRC_BCLK2:
case ADAU1373_PLL_SRC_BCLK3:
case ADAU1373_PLL_SRC_LRCLK1:
case ADAU1373_PLL_SRC_LRCLK2:
case ADAU1373_PLL_SRC_LRCLK3:
case ADAU1373_PLL_SRC_MCLK1:
case ADAU1373_PLL_SRC_MCLK2:
case ADAU1373_PLL_SRC_GPIO1:
case ADAU1373_PLL_SRC_GPIO2:
case ADAU1373_PLL_SRC_GPIO3:
case ADAU1373_PLL_SRC_GPIO4:
break;
default:
return -EINVAL;
}
if (freq_in < 7813 || freq_in > 27000000)
return -EINVAL;
if (freq_out < 45158000 || freq_out > 49152000)
return -EINVAL;
/* APLL input needs to be >= 8Mhz, so in case freq_in is less we use the
* DPLL to get it there. DPLL_out = (DPLL_in / div) * 1024 */
while (freq_in < 8000000) {
freq_in *= 2;
dpll_div++;
}
ret = adau_calc_pll_cfg(freq_in, freq_out, pll_regs);
if (ret)
return -EINVAL;
if (dpll_div) {
dpll_div = 11 - dpll_div;
regmap_update_bits(adau1373->regmap, ADAU1373_PLL_CTRL6(pll_id),
ADAU1373_PLL_CTRL6_DPLL_BYPASS, 0);
} else {
regmap_update_bits(adau1373->regmap, ADAU1373_PLL_CTRL6(pll_id),
ADAU1373_PLL_CTRL6_DPLL_BYPASS,
ADAU1373_PLL_CTRL6_DPLL_BYPASS);
}
regmap_write(adau1373->regmap, ADAU1373_DPLL_CTRL(pll_id),
(source << 4) | dpll_div);
regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL1(pll_id), pll_regs[0]);
regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL2(pll_id), pll_regs[1]);
regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL3(pll_id), pll_regs[2]);
regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL4(pll_id), pll_regs[3]);
regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL5(pll_id), pll_regs[4]);
/* Set sysclk to pll_rate / 4 */
regmap_update_bits(adau1373->regmap, ADAU1373_CLK_SRC_DIV(pll_id), 0x3f, 0x09);
return 0;
}
static void adau1373_load_drc_settings(struct adau1373 *adau1373,
unsigned int nr, uint8_t *drc)
{
unsigned int i;
for (i = 0; i < ADAU1373_DRC_SIZE; ++i)
regmap_write(adau1373->regmap, ADAU1373_DRC(nr) + i, drc[i]);
}
static bool adau1373_valid_micbias(enum adau1373_micbias_voltage micbias)
{
switch (micbias) {
case ADAU1373_MICBIAS_2_9V:
case ADAU1373_MICBIAS_2_2V:
case ADAU1373_MICBIAS_2_6V:
case ADAU1373_MICBIAS_1_8V:
return true;
default:
break;
}
return false;
}
static int adau1373_probe(struct snd_soc_component *component)
{
struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
struct adau1373_platform_data *pdata = component->dev->platform_data;
bool lineout_differential = false;
unsigned int val;
int i;
if (pdata) {
if (pdata->num_drc > ARRAY_SIZE(pdata->drc_setting))
return -EINVAL;
if (!adau1373_valid_micbias(pdata->micbias1) ||
!adau1373_valid_micbias(pdata->micbias2))
return -EINVAL;
for (i = 0; i < pdata->num_drc; ++i) {
adau1373_load_drc_settings(adau1373, i,
pdata->drc_setting[i]);
}
snd_soc_add_component_controls(component, adau1373_drc_controls,
pdata->num_drc);
val = 0;
for (i = 0; i < 4; ++i) {
if (pdata->input_differential[i])
val |= BIT(i);
}
regmap_write(adau1373->regmap, ADAU1373_INPUT_MODE, val);
val = 0;
if (pdata->lineout_differential)
val |= ADAU1373_OUTPUT_CTRL_LDIFF;
if (pdata->lineout_ground_sense)
val |= ADAU1373_OUTPUT_CTRL_LNFBEN;
regmap_write(adau1373->regmap, ADAU1373_OUTPUT_CTRL, val);
lineout_differential = pdata->lineout_differential;
regmap_write(adau1373->regmap, ADAU1373_EP_CTRL,
(pdata->micbias1 << ADAU1373_EP_CTRL_MICBIAS1_OFFSET) |
(pdata->micbias2 << ADAU1373_EP_CTRL_MICBIAS2_OFFSET));
}
if (!lineout_differential) {
snd_soc_add_component_controls(component, adau1373_lineout2_controls,
ARRAY_SIZE(adau1373_lineout2_controls));
}
regmap_write(adau1373->regmap, ADAU1373_ADC_CTRL,
ADAU1373_ADC_CTRL_RESET_FORCE | ADAU1373_ADC_CTRL_PEAK_DETECT);
return 0;
}
static int adau1373_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
regmap_update_bits(adau1373->regmap, ADAU1373_PWDN_CTRL3,
ADAU1373_PWDN_CTRL3_PWR_EN, ADAU1373_PWDN_CTRL3_PWR_EN);
break;
case SND_SOC_BIAS_OFF:
regmap_update_bits(adau1373->regmap, ADAU1373_PWDN_CTRL3,
ADAU1373_PWDN_CTRL3_PWR_EN, 0);
break;
}
return 0;
}
static int adau1373_resume(struct snd_soc_component *component)
{
struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
regcache_sync(adau1373->regmap);
return 0;
}
static bool adau1373_register_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case ADAU1373_SOFT_RESET:
case ADAU1373_ADC_DAC_STATUS:
return true;
default:
return false;
}
}
static const struct regmap_config adau1373_regmap_config = {
.val_bits = 8,
.reg_bits = 8,
.volatile_reg = adau1373_register_volatile,
.max_register = ADAU1373_SOFT_RESET,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = adau1373_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(adau1373_reg_defaults),
};
static const struct snd_soc_component_driver adau1373_component_driver = {
.probe = adau1373_probe,
.resume = adau1373_resume,
.set_bias_level = adau1373_set_bias_level,
.set_pll = adau1373_set_pll,
.controls = adau1373_controls,
.num_controls = ARRAY_SIZE(adau1373_controls),
.dapm_widgets = adau1373_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(adau1373_dapm_widgets),
.dapm_routes = adau1373_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(adau1373_dapm_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
static int adau1373_i2c_probe(struct i2c_client *client)
{
struct adau1373 *adau1373;
int ret;
adau1373 = devm_kzalloc(&client->dev, sizeof(*adau1373), GFP_KERNEL);
if (!adau1373)
return -ENOMEM;
adau1373->regmap = devm_regmap_init_i2c(client,
&adau1373_regmap_config);
if (IS_ERR(adau1373->regmap))
return PTR_ERR(adau1373->regmap);
regmap_write(adau1373->regmap, ADAU1373_SOFT_RESET, 0x00);
dev_set_drvdata(&client->dev, adau1373);
ret = devm_snd_soc_register_component(&client->dev,
&adau1373_component_driver,
adau1373_dai_driver, ARRAY_SIZE(adau1373_dai_driver));
return ret;
}
static const struct i2c_device_id adau1373_i2c_id[] = {
{ "adau1373", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, adau1373_i2c_id);
static struct i2c_driver adau1373_i2c_driver = {
.driver = {
.name = "adau1373",
},
.probe = adau1373_i2c_probe,
.id_table = adau1373_i2c_id,
};
module_i2c_driver(adau1373_i2c_driver);
MODULE_DESCRIPTION("ASoC ADAU1373 driver");
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/adau1373.c |
// SPDX-License-Identifier: GPL-2.0+
//
// DA7210 ALSA Soc codec driver
//
// Copyright (c) 2009 Dialog Semiconductor
// Written by David Chen <[email protected]>
//
// Copyright (C) 2009 Renesas Solutions Corp.
// Cleanups by Kuninori Morimoto <[email protected]>
//
// Tested on SuperH Ecovec24 board with S16/S24 LE in 48KHz using I2S
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/spi/spi.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
/* DA7210 register space */
#define DA7210_PAGE_CONTROL 0x00
#define DA7210_CONTROL 0x01
#define DA7210_STATUS 0x02
#define DA7210_STARTUP1 0x03
#define DA7210_STARTUP2 0x04
#define DA7210_STARTUP3 0x05
#define DA7210_MIC_L 0x07
#define DA7210_MIC_R 0x08
#define DA7210_AUX1_L 0x09
#define DA7210_AUX1_R 0x0A
#define DA7210_AUX2 0x0B
#define DA7210_IN_GAIN 0x0C
#define DA7210_INMIX_L 0x0D
#define DA7210_INMIX_R 0x0E
#define DA7210_ADC_HPF 0x0F
#define DA7210_ADC 0x10
#define DA7210_ADC_EQ1_2 0X11
#define DA7210_ADC_EQ3_4 0x12
#define DA7210_ADC_EQ5 0x13
#define DA7210_DAC_HPF 0x14
#define DA7210_DAC_L 0x15
#define DA7210_DAC_R 0x16
#define DA7210_DAC_SEL 0x17
#define DA7210_SOFTMUTE 0x18
#define DA7210_DAC_EQ1_2 0x19
#define DA7210_DAC_EQ3_4 0x1A
#define DA7210_DAC_EQ5 0x1B
#define DA7210_OUTMIX_L 0x1C
#define DA7210_OUTMIX_R 0x1D
#define DA7210_OUT1_L 0x1E
#define DA7210_OUT1_R 0x1F
#define DA7210_OUT2 0x20
#define DA7210_HP_L_VOL 0x21
#define DA7210_HP_R_VOL 0x22
#define DA7210_HP_CFG 0x23
#define DA7210_ZERO_CROSS 0x24
#define DA7210_DAI_SRC_SEL 0x25
#define DA7210_DAI_CFG1 0x26
#define DA7210_DAI_CFG3 0x28
#define DA7210_PLL_DIV1 0x29
#define DA7210_PLL_DIV2 0x2A
#define DA7210_PLL_DIV3 0x2B
#define DA7210_PLL 0x2C
#define DA7210_ALC_MAX 0x83
#define DA7210_ALC_MIN 0x84
#define DA7210_ALC_NOIS 0x85
#define DA7210_ALC_ATT 0x86
#define DA7210_ALC_REL 0x87
#define DA7210_ALC_DEL 0x88
#define DA7210_A_HID_UNLOCK 0x8A
#define DA7210_A_TEST_UNLOCK 0x8B
#define DA7210_A_PLL1 0x90
#define DA7210_A_CP_MODE 0xA7
/* STARTUP1 bit fields */
#define DA7210_SC_MST_EN (1 << 0)
/* MIC_L bit fields */
#define DA7210_MICBIAS_EN (1 << 6)
#define DA7210_MIC_L_EN (1 << 7)
/* MIC_R bit fields */
#define DA7210_MIC_R_EN (1 << 7)
/* INMIX_L bit fields */
#define DA7210_IN_L_EN (1 << 7)
/* INMIX_R bit fields */
#define DA7210_IN_R_EN (1 << 7)
/* ADC bit fields */
#define DA7210_ADC_ALC_EN (1 << 0)
#define DA7210_ADC_L_EN (1 << 3)
#define DA7210_ADC_R_EN (1 << 7)
/* DAC/ADC HPF fields */
#define DA7210_VOICE_F0_MASK (0x7 << 4)
#define DA7210_VOICE_F0_25 (1 << 4)
#define DA7210_VOICE_EN (1 << 7)
/* DAC_SEL bit fields */
#define DA7210_DAC_L_SRC_DAI_L (4 << 0)
#define DA7210_DAC_L_EN (1 << 3)
#define DA7210_DAC_R_SRC_DAI_R (5 << 4)
#define DA7210_DAC_R_EN (1 << 7)
/* OUTMIX_L bit fields */
#define DA7210_OUT_L_EN (1 << 7)
/* OUTMIX_R bit fields */
#define DA7210_OUT_R_EN (1 << 7)
/* HP_CFG bit fields */
#define DA7210_HP_2CAP_MODE (1 << 1)
#define DA7210_HP_SENSE_EN (1 << 2)
#define DA7210_HP_L_EN (1 << 3)
#define DA7210_HP_MODE (1 << 6)
#define DA7210_HP_R_EN (1 << 7)
/* DAI_SRC_SEL bit fields */
#define DA7210_DAI_OUT_L_SRC (6 << 0)
#define DA7210_DAI_OUT_R_SRC (7 << 4)
/* DAI_CFG1 bit fields */
#define DA7210_DAI_WORD_S16_LE (0 << 0)
#define DA7210_DAI_WORD_S20_3LE (1 << 0)
#define DA7210_DAI_WORD_S24_LE (2 << 0)
#define DA7210_DAI_WORD_S32_LE (3 << 0)
#define DA7210_DAI_FLEN_64BIT (1 << 2)
#define DA7210_DAI_MODE_SLAVE (0 << 7)
#define DA7210_DAI_MODE_MASTER (1 << 7)
/* DAI_CFG3 bit fields */
#define DA7210_DAI_FORMAT_I2SMODE (0 << 0)
#define DA7210_DAI_FORMAT_LEFT_J (1 << 0)
#define DA7210_DAI_FORMAT_RIGHT_J (2 << 0)
#define DA7210_DAI_OE (1 << 3)
#define DA7210_DAI_EN (1 << 7)
/*PLL_DIV3 bit fields */
#define DA7210_PLL_DIV_L_MASK (0xF << 0)
#define DA7210_MCLK_RANGE_10_20_MHZ (1 << 4)
#define DA7210_PLL_BYP (1 << 6)
/* PLL bit fields */
#define DA7210_PLL_FS_MASK (0xF << 0)
#define DA7210_PLL_FS_8000 (0x1 << 0)
#define DA7210_PLL_FS_11025 (0x2 << 0)
#define DA7210_PLL_FS_12000 (0x3 << 0)
#define DA7210_PLL_FS_16000 (0x5 << 0)
#define DA7210_PLL_FS_22050 (0x6 << 0)
#define DA7210_PLL_FS_24000 (0x7 << 0)
#define DA7210_PLL_FS_32000 (0x9 << 0)
#define DA7210_PLL_FS_44100 (0xA << 0)
#define DA7210_PLL_FS_48000 (0xB << 0)
#define DA7210_PLL_FS_88200 (0xE << 0)
#define DA7210_PLL_FS_96000 (0xF << 0)
#define DA7210_MCLK_DET_EN (0x1 << 5)
#define DA7210_MCLK_SRM_EN (0x1 << 6)
#define DA7210_PLL_EN (0x1 << 7)
/* SOFTMUTE bit fields */
#define DA7210_RAMP_EN (1 << 6)
/* CONTROL bit fields */
#define DA7210_REG_EN (1 << 0)
#define DA7210_BIAS_EN (1 << 2)
#define DA7210_NOISE_SUP_EN (1 << 3)
/* IN_GAIN bit fields */
#define DA7210_INPGA_L_VOL (0x0F << 0)
#define DA7210_INPGA_R_VOL (0xF0 << 0)
/* ZERO_CROSS bit fields */
#define DA7210_AUX1_L_ZC (1 << 0)
#define DA7210_AUX1_R_ZC (1 << 1)
#define DA7210_HP_L_ZC (1 << 6)
#define DA7210_HP_R_ZC (1 << 7)
/* AUX1_L bit fields */
#define DA7210_AUX1_L_VOL (0x3F << 0)
#define DA7210_AUX1_L_EN (1 << 7)
/* AUX1_R bit fields */
#define DA7210_AUX1_R_VOL (0x3F << 0)
#define DA7210_AUX1_R_EN (1 << 7)
/* AUX2 bit fields */
#define DA7210_AUX2_EN (1 << 3)
/* Minimum INPGA and AUX1 volume to enable noise suppression */
#define DA7210_INPGA_MIN_VOL_NS 0x0A /* 10.5dB */
#define DA7210_AUX1_MIN_VOL_NS 0x35 /* 6dB */
/* OUT1_L bit fields */
#define DA7210_OUT1_L_EN (1 << 7)
/* OUT1_R bit fields */
#define DA7210_OUT1_R_EN (1 << 7)
/* OUT2 bit fields */
#define DA7210_OUT2_OUTMIX_R (1 << 5)
#define DA7210_OUT2_OUTMIX_L (1 << 6)
#define DA7210_OUT2_EN (1 << 7)
struct pll_div {
int fref;
int fout;
u8 div1;
u8 div2;
u8 div3;
u8 mode; /* 0 = slave, 1 = master */
};
/* PLL dividers table */
static const struct pll_div da7210_pll_div[] = {
/* for MASTER mode, fs = 44.1Khz */
{ 12000000, 2822400, 0xE8, 0x6C, 0x2, 1}, /* MCLK=12Mhz */
{ 13000000, 2822400, 0xDF, 0x28, 0xC, 1}, /* MCLK=13Mhz */
{ 13500000, 2822400, 0xDB, 0x0A, 0xD, 1}, /* MCLK=13.5Mhz */
{ 14400000, 2822400, 0xD4, 0x5A, 0x2, 1}, /* MCLK=14.4Mhz */
{ 19200000, 2822400, 0xBB, 0x43, 0x9, 1}, /* MCLK=19.2Mhz */
{ 19680000, 2822400, 0xB9, 0x6D, 0xA, 1}, /* MCLK=19.68Mhz */
{ 19800000, 2822400, 0xB8, 0xFB, 0xB, 1}, /* MCLK=19.8Mhz */
/* for MASTER mode, fs = 48Khz */
{ 12000000, 3072000, 0xF3, 0x12, 0x7, 1}, /* MCLK=12Mhz */
{ 13000000, 3072000, 0xE8, 0xFD, 0x5, 1}, /* MCLK=13Mhz */
{ 13500000, 3072000, 0xE4, 0x82, 0x3, 1}, /* MCLK=13.5Mhz */
{ 14400000, 3072000, 0xDD, 0x3A, 0x0, 1}, /* MCLK=14.4Mhz */
{ 19200000, 3072000, 0xC1, 0xEB, 0x8, 1}, /* MCLK=19.2Mhz */
{ 19680000, 3072000, 0xBF, 0xEC, 0x0, 1}, /* MCLK=19.68Mhz */
{ 19800000, 3072000, 0xBF, 0x70, 0x0, 1}, /* MCLK=19.8Mhz */
/* for SLAVE mode with SRM */
{ 12000000, 2822400, 0xED, 0xBF, 0x5, 0}, /* MCLK=12Mhz */
{ 13000000, 2822400, 0xE4, 0x13, 0x0, 0}, /* MCLK=13Mhz */
{ 13500000, 2822400, 0xDF, 0xC6, 0x8, 0}, /* MCLK=13.5Mhz */
{ 14400000, 2822400, 0xD8, 0xCA, 0x1, 0}, /* MCLK=14.4Mhz */
{ 19200000, 2822400, 0xBE, 0x97, 0x9, 0}, /* MCLK=19.2Mhz */
{ 19680000, 2822400, 0xBC, 0xAC, 0xD, 0}, /* MCLK=19.68Mhz */
{ 19800000, 2822400, 0xBC, 0x35, 0xE, 0}, /* MCLK=19.8Mhz */
};
enum clk_src {
DA7210_CLKSRC_MCLK
};
#define DA7210_VERSION "0.0.1"
/*
* Playback Volume
*
* max : 0x3F (+15.0 dB)
* (1.5 dB step)
* min : 0x11 (-54.0 dB)
* mute : 0x10
* reserved : 0x00 - 0x0F
*
* Reserved area are considered as "mute".
*/
static const DECLARE_TLV_DB_RANGE(hp_out_tlv,
0x0, 0x10, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
/* -54 dB to +15 dB */
0x11, 0x3f, TLV_DB_SCALE_ITEM(-5400, 150, 0)
);
static const DECLARE_TLV_DB_RANGE(lineout_vol_tlv,
0x0, 0x10, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
/* -54dB to 15dB */
0x11, 0x3f, TLV_DB_SCALE_ITEM(-5400, 150, 0)
);
static const DECLARE_TLV_DB_RANGE(mono_vol_tlv,
0x0, 0x2, TLV_DB_SCALE_ITEM(-1800, 0, 1),
/* -18dB to 6dB */
0x3, 0x7, TLV_DB_SCALE_ITEM(-1800, 600, 0)
);
static const DECLARE_TLV_DB_RANGE(aux1_vol_tlv,
0x0, 0x10, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
/* -48dB to 21dB */
0x11, 0x3f, TLV_DB_SCALE_ITEM(-4800, 150, 0)
);
static const DECLARE_TLV_DB_SCALE(eq_gain_tlv, -1050, 150, 0);
static const DECLARE_TLV_DB_SCALE(adc_eq_master_gain_tlv, -1800, 600, 1);
static const DECLARE_TLV_DB_SCALE(dac_gain_tlv, -7725, 75, 0);
static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -600, 600, 0);
static const DECLARE_TLV_DB_SCALE(aux2_vol_tlv, -600, 600, 0);
static const DECLARE_TLV_DB_SCALE(inpga_gain_tlv, -450, 150, 0);
/* ADC and DAC high pass filter f0 value */
static const char * const da7210_hpf_cutoff_txt[] = {
"Fs/8192*pi", "Fs/4096*pi", "Fs/2048*pi", "Fs/1024*pi"
};
static SOC_ENUM_SINGLE_DECL(da7210_dac_hpf_cutoff,
DA7210_DAC_HPF, 0, da7210_hpf_cutoff_txt);
static SOC_ENUM_SINGLE_DECL(da7210_adc_hpf_cutoff,
DA7210_ADC_HPF, 0, da7210_hpf_cutoff_txt);
/* ADC and DAC voice (8kHz) high pass cutoff value */
static const char * const da7210_vf_cutoff_txt[] = {
"2.5Hz", "25Hz", "50Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
};
static SOC_ENUM_SINGLE_DECL(da7210_dac_vf_cutoff,
DA7210_DAC_HPF, 4, da7210_vf_cutoff_txt);
static SOC_ENUM_SINGLE_DECL(da7210_adc_vf_cutoff,
DA7210_ADC_HPF, 4, da7210_vf_cutoff_txt);
static const char *da7210_hp_mode_txt[] = {
"Class H", "Class G"
};
static SOC_ENUM_SINGLE_DECL(da7210_hp_mode_sel,
DA7210_HP_CFG, 0, da7210_hp_mode_txt);
/* ALC can be enabled only if noise suppression is disabled */
static int da7210_put_alc_sw(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
if (ucontrol->value.integer.value[0]) {
/* Check if noise suppression is enabled */
if (snd_soc_component_read(component, DA7210_CONTROL) & DA7210_NOISE_SUP_EN) {
dev_dbg(component->dev,
"Disable noise suppression to enable ALC\n");
return -EINVAL;
}
}
/* If all conditions are met or we are actually disabling ALC */
return snd_soc_put_volsw(kcontrol, ucontrol);
}
/* Noise suppression can be enabled only if following conditions are met
* ALC disabled
* ZC enabled for HP and AUX1 PGA
* INPGA_L_VOL and INPGA_R_VOL >= 10.5 dB
* AUX1_L_VOL and AUX1_R_VOL >= 6 dB
*/
static int da7210_put_noise_sup_sw(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
u8 val;
if (ucontrol->value.integer.value[0]) {
/* Check if ALC is enabled */
if (snd_soc_component_read(component, DA7210_ADC) & DA7210_ADC_ALC_EN)
goto err;
/* Check ZC for HP and AUX1 PGA */
if ((snd_soc_component_read(component, DA7210_ZERO_CROSS) &
(DA7210_AUX1_L_ZC | DA7210_AUX1_R_ZC | DA7210_HP_L_ZC |
DA7210_HP_R_ZC)) != (DA7210_AUX1_L_ZC |
DA7210_AUX1_R_ZC | DA7210_HP_L_ZC | DA7210_HP_R_ZC))
goto err;
/* Check INPGA_L_VOL and INPGA_R_VOL */
val = snd_soc_component_read(component, DA7210_IN_GAIN);
if (((val & DA7210_INPGA_L_VOL) < DA7210_INPGA_MIN_VOL_NS) ||
(((val & DA7210_INPGA_R_VOL) >> 4) <
DA7210_INPGA_MIN_VOL_NS))
goto err;
/* Check AUX1_L_VOL and AUX1_R_VOL */
if (((snd_soc_component_read(component, DA7210_AUX1_L) & DA7210_AUX1_L_VOL) <
DA7210_AUX1_MIN_VOL_NS) ||
((snd_soc_component_read(component, DA7210_AUX1_R) & DA7210_AUX1_R_VOL) <
DA7210_AUX1_MIN_VOL_NS))
goto err;
}
/* If all conditions are met or we are actually disabling Noise sup */
return snd_soc_put_volsw(kcontrol, ucontrol);
err:
return -EINVAL;
}
static const struct snd_kcontrol_new da7210_snd_controls[] = {
SOC_DOUBLE_R_TLV("HeadPhone Playback Volume",
DA7210_HP_L_VOL, DA7210_HP_R_VOL,
0, 0x3F, 0, hp_out_tlv),
SOC_DOUBLE_R_TLV("Digital Playback Volume",
DA7210_DAC_L, DA7210_DAC_R,
0, 0x77, 1, dac_gain_tlv),
SOC_DOUBLE_R_TLV("Lineout Playback Volume",
DA7210_OUT1_L, DA7210_OUT1_R,
0, 0x3f, 0, lineout_vol_tlv),
SOC_SINGLE_TLV("Mono Playback Volume", DA7210_OUT2, 0, 0x7, 0,
mono_vol_tlv),
SOC_DOUBLE_R_TLV("Mic Capture Volume",
DA7210_MIC_L, DA7210_MIC_R,
0, 0x5, 0, mic_vol_tlv),
SOC_DOUBLE_R_TLV("Aux1 Capture Volume",
DA7210_AUX1_L, DA7210_AUX1_R,
0, 0x3f, 0, aux1_vol_tlv),
SOC_SINGLE_TLV("Aux2 Capture Volume", DA7210_AUX2, 0, 0x3, 0,
aux2_vol_tlv),
SOC_DOUBLE_TLV("In PGA Capture Volume", DA7210_IN_GAIN, 0, 4, 0xF, 0,
inpga_gain_tlv),
/* DAC Equalizer controls */
SOC_SINGLE("DAC EQ Switch", DA7210_DAC_EQ5, 7, 1, 0),
SOC_SINGLE_TLV("DAC EQ1 Volume", DA7210_DAC_EQ1_2, 0, 0xf, 1,
eq_gain_tlv),
SOC_SINGLE_TLV("DAC EQ2 Volume", DA7210_DAC_EQ1_2, 4, 0xf, 1,
eq_gain_tlv),
SOC_SINGLE_TLV("DAC EQ3 Volume", DA7210_DAC_EQ3_4, 0, 0xf, 1,
eq_gain_tlv),
SOC_SINGLE_TLV("DAC EQ4 Volume", DA7210_DAC_EQ3_4, 4, 0xf, 1,
eq_gain_tlv),
SOC_SINGLE_TLV("DAC EQ5 Volume", DA7210_DAC_EQ5, 0, 0xf, 1,
eq_gain_tlv),
/* ADC Equalizer controls */
SOC_SINGLE("ADC EQ Switch", DA7210_ADC_EQ5, 7, 1, 0),
SOC_SINGLE_TLV("ADC EQ Master Volume", DA7210_ADC_EQ5, 4, 0x3,
1, adc_eq_master_gain_tlv),
SOC_SINGLE_TLV("ADC EQ1 Volume", DA7210_ADC_EQ1_2, 0, 0xf, 1,
eq_gain_tlv),
SOC_SINGLE_TLV("ADC EQ2 Volume", DA7210_ADC_EQ1_2, 4, 0xf, 1,
eq_gain_tlv),
SOC_SINGLE_TLV("ADC EQ3 Volume", DA7210_ADC_EQ3_4, 0, 0xf, 1,
eq_gain_tlv),
SOC_SINGLE_TLV("ADC EQ4 Volume", DA7210_ADC_EQ3_4, 4, 0xf, 1,
eq_gain_tlv),
SOC_SINGLE_TLV("ADC EQ5 Volume", DA7210_ADC_EQ5, 0, 0xf, 1,
eq_gain_tlv),
SOC_SINGLE("DAC HPF Switch", DA7210_DAC_HPF, 3, 1, 0),
SOC_ENUM("DAC HPF Cutoff", da7210_dac_hpf_cutoff),
SOC_SINGLE("DAC Voice Mode Switch", DA7210_DAC_HPF, 7, 1, 0),
SOC_ENUM("DAC Voice Cutoff", da7210_dac_vf_cutoff),
SOC_SINGLE("ADC HPF Switch", DA7210_ADC_HPF, 3, 1, 0),
SOC_ENUM("ADC HPF Cutoff", da7210_adc_hpf_cutoff),
SOC_SINGLE("ADC Voice Mode Switch", DA7210_ADC_HPF, 7, 1, 0),
SOC_ENUM("ADC Voice Cutoff", da7210_adc_vf_cutoff),
/* Mute controls */
SOC_DOUBLE_R("Mic Capture Switch", DA7210_MIC_L, DA7210_MIC_R, 3, 1, 0),
SOC_SINGLE("Aux2 Capture Switch", DA7210_AUX2, 2, 1, 0),
SOC_DOUBLE("ADC Capture Switch", DA7210_ADC, 2, 6, 1, 0),
SOC_SINGLE("Digital Soft Mute Switch", DA7210_SOFTMUTE, 7, 1, 0),
SOC_SINGLE("Digital Soft Mute Rate", DA7210_SOFTMUTE, 0, 0x7, 0),
/* Zero cross controls */
SOC_DOUBLE("Aux1 ZC Switch", DA7210_ZERO_CROSS, 0, 1, 1, 0),
SOC_DOUBLE("In PGA ZC Switch", DA7210_ZERO_CROSS, 2, 3, 1, 0),
SOC_DOUBLE("Lineout ZC Switch", DA7210_ZERO_CROSS, 4, 5, 1, 0),
SOC_DOUBLE("Headphone ZC Switch", DA7210_ZERO_CROSS, 6, 7, 1, 0),
SOC_ENUM("Headphone Class", da7210_hp_mode_sel),
/* ALC controls */
SOC_SINGLE_EXT("ALC Enable Switch", DA7210_ADC, 0, 1, 0,
snd_soc_get_volsw, da7210_put_alc_sw),
SOC_SINGLE("ALC Capture Max Volume", DA7210_ALC_MAX, 0, 0x3F, 0),
SOC_SINGLE("ALC Capture Min Volume", DA7210_ALC_MIN, 0, 0x3F, 0),
SOC_SINGLE("ALC Capture Noise Volume", DA7210_ALC_NOIS, 0, 0x3F, 0),
SOC_SINGLE("ALC Capture Attack Rate", DA7210_ALC_ATT, 0, 0xFF, 0),
SOC_SINGLE("ALC Capture Release Rate", DA7210_ALC_REL, 0, 0xFF, 0),
SOC_SINGLE("ALC Capture Release Delay", DA7210_ALC_DEL, 0, 0xFF, 0),
SOC_SINGLE_EXT("Noise Suppression Enable Switch", DA7210_CONTROL, 3, 1,
0, snd_soc_get_volsw, da7210_put_noise_sup_sw),
};
/*
* DAPM Controls
*
* Current DAPM implementation covers almost all codec components e.g. IOs,
* mixers, PGAs,ADC and DAC.
*/
/* In Mixer Left */
static const struct snd_kcontrol_new da7210_dapm_inmixl_controls[] = {
SOC_DAPM_SINGLE("Mic Left Switch", DA7210_INMIX_L, 0, 1, 0),
SOC_DAPM_SINGLE("Mic Right Switch", DA7210_INMIX_L, 1, 1, 0),
SOC_DAPM_SINGLE("Aux1 Left Switch", DA7210_INMIX_L, 2, 1, 0),
SOC_DAPM_SINGLE("Aux2 Switch", DA7210_INMIX_L, 3, 1, 0),
SOC_DAPM_SINGLE("Outmix Left Switch", DA7210_INMIX_L, 4, 1, 0),
};
/* In Mixer Right */
static const struct snd_kcontrol_new da7210_dapm_inmixr_controls[] = {
SOC_DAPM_SINGLE("Mic Right Switch", DA7210_INMIX_R, 0, 1, 0),
SOC_DAPM_SINGLE("Mic Left Switch", DA7210_INMIX_R, 1, 1, 0),
SOC_DAPM_SINGLE("Aux1 Right Switch", DA7210_INMIX_R, 2, 1, 0),
SOC_DAPM_SINGLE("Aux2 Switch", DA7210_INMIX_R, 3, 1, 0),
SOC_DAPM_SINGLE("Outmix Right Switch", DA7210_INMIX_R, 4, 1, 0),
};
/* Out Mixer Left */
static const struct snd_kcontrol_new da7210_dapm_outmixl_controls[] = {
SOC_DAPM_SINGLE("Aux1 Left Switch", DA7210_OUTMIX_L, 0, 1, 0),
SOC_DAPM_SINGLE("Aux2 Switch", DA7210_OUTMIX_L, 1, 1, 0),
SOC_DAPM_SINGLE("INPGA Left Switch", DA7210_OUTMIX_L, 2, 1, 0),
SOC_DAPM_SINGLE("INPGA Right Switch", DA7210_OUTMIX_L, 3, 1, 0),
SOC_DAPM_SINGLE("DAC Left Switch", DA7210_OUTMIX_L, 4, 1, 0),
};
/* Out Mixer Right */
static const struct snd_kcontrol_new da7210_dapm_outmixr_controls[] = {
SOC_DAPM_SINGLE("Aux1 Right Switch", DA7210_OUTMIX_R, 0, 1, 0),
SOC_DAPM_SINGLE("Aux2 Switch", DA7210_OUTMIX_R, 1, 1, 0),
SOC_DAPM_SINGLE("INPGA Left Switch", DA7210_OUTMIX_R, 2, 1, 0),
SOC_DAPM_SINGLE("INPGA Right Switch", DA7210_OUTMIX_R, 3, 1, 0),
SOC_DAPM_SINGLE("DAC Right Switch", DA7210_OUTMIX_R, 4, 1, 0),
};
/* Mono Mixer */
static const struct snd_kcontrol_new da7210_dapm_monomix_controls[] = {
SOC_DAPM_SINGLE("INPGA Right Switch", DA7210_OUT2, 3, 1, 0),
SOC_DAPM_SINGLE("INPGA Left Switch", DA7210_OUT2, 4, 1, 0),
SOC_DAPM_SINGLE("Outmix Right Switch", DA7210_OUT2, 5, 1, 0),
SOC_DAPM_SINGLE("Outmix Left Switch", DA7210_OUT2, 6, 1, 0),
};
/* DAPM widgets */
static const struct snd_soc_dapm_widget da7210_dapm_widgets[] = {
/* Input Side */
/* Input Lines */
SND_SOC_DAPM_INPUT("MICL"),
SND_SOC_DAPM_INPUT("MICR"),
SND_SOC_DAPM_INPUT("AUX1L"),
SND_SOC_DAPM_INPUT("AUX1R"),
SND_SOC_DAPM_INPUT("AUX2"),
/* Input PGAs */
SND_SOC_DAPM_PGA("Mic Left", DA7210_STARTUP3, 0, 1, NULL, 0),
SND_SOC_DAPM_PGA("Mic Right", DA7210_STARTUP3, 1, 1, NULL, 0),
SND_SOC_DAPM_PGA("Aux1 Left", DA7210_STARTUP3, 2, 1, NULL, 0),
SND_SOC_DAPM_PGA("Aux1 Right", DA7210_STARTUP3, 3, 1, NULL, 0),
SND_SOC_DAPM_PGA("Aux2 Mono", DA7210_STARTUP3, 4, 1, NULL, 0),
SND_SOC_DAPM_PGA("INPGA Left", DA7210_INMIX_L, 7, 0, NULL, 0),
SND_SOC_DAPM_PGA("INPGA Right", DA7210_INMIX_R, 7, 0, NULL, 0),
/* MICBIAS */
SND_SOC_DAPM_SUPPLY("Mic Bias", DA7210_MIC_L, 6, 0, NULL, 0),
/* Input Mixers */
SND_SOC_DAPM_MIXER("In Mixer Left", SND_SOC_NOPM, 0, 0,
&da7210_dapm_inmixl_controls[0],
ARRAY_SIZE(da7210_dapm_inmixl_controls)),
SND_SOC_DAPM_MIXER("In Mixer Right", SND_SOC_NOPM, 0, 0,
&da7210_dapm_inmixr_controls[0],
ARRAY_SIZE(da7210_dapm_inmixr_controls)),
/* ADCs */
SND_SOC_DAPM_ADC("ADC Left", "Capture", DA7210_STARTUP3, 5, 1),
SND_SOC_DAPM_ADC("ADC Right", "Capture", DA7210_STARTUP3, 6, 1),
/* Output Side */
/* DACs */
SND_SOC_DAPM_DAC("DAC Left", "Playback", DA7210_STARTUP2, 5, 1),
SND_SOC_DAPM_DAC("DAC Right", "Playback", DA7210_STARTUP2, 6, 1),
/* Output Mixers */
SND_SOC_DAPM_MIXER("Out Mixer Left", SND_SOC_NOPM, 0, 0,
&da7210_dapm_outmixl_controls[0],
ARRAY_SIZE(da7210_dapm_outmixl_controls)),
SND_SOC_DAPM_MIXER("Out Mixer Right", SND_SOC_NOPM, 0, 0,
&da7210_dapm_outmixr_controls[0],
ARRAY_SIZE(da7210_dapm_outmixr_controls)),
SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
&da7210_dapm_monomix_controls[0],
ARRAY_SIZE(da7210_dapm_monomix_controls)),
/* Output PGAs */
SND_SOC_DAPM_PGA("OUTPGA Left Enable", DA7210_OUTMIX_L, 7, 0, NULL, 0),
SND_SOC_DAPM_PGA("OUTPGA Right Enable", DA7210_OUTMIX_R, 7, 0, NULL, 0),
SND_SOC_DAPM_PGA("Out1 Left", DA7210_STARTUP2, 0, 1, NULL, 0),
SND_SOC_DAPM_PGA("Out1 Right", DA7210_STARTUP2, 1, 1, NULL, 0),
SND_SOC_DAPM_PGA("Out2 Mono", DA7210_STARTUP2, 2, 1, NULL, 0),
SND_SOC_DAPM_PGA("Headphone Left", DA7210_STARTUP2, 3, 1, NULL, 0),
SND_SOC_DAPM_PGA("Headphone Right", DA7210_STARTUP2, 4, 1, NULL, 0),
/* Output Lines */
SND_SOC_DAPM_OUTPUT("OUT1L"),
SND_SOC_DAPM_OUTPUT("OUT1R"),
SND_SOC_DAPM_OUTPUT("HPL"),
SND_SOC_DAPM_OUTPUT("HPR"),
SND_SOC_DAPM_OUTPUT("OUT2"),
};
/* DAPM audio route definition */
static const struct snd_soc_dapm_route da7210_audio_map[] = {
/* Dest Connecting Widget source */
/* Input path */
{"Mic Left", NULL, "MICL"},
{"Mic Right", NULL, "MICR"},
{"Aux1 Left", NULL, "AUX1L"},
{"Aux1 Right", NULL, "AUX1R"},
{"Aux2 Mono", NULL, "AUX2"},
{"In Mixer Left", "Mic Left Switch", "Mic Left"},
{"In Mixer Left", "Mic Right Switch", "Mic Right"},
{"In Mixer Left", "Aux1 Left Switch", "Aux1 Left"},
{"In Mixer Left", "Aux2 Switch", "Aux2 Mono"},
{"In Mixer Left", "Outmix Left Switch", "Out Mixer Left"},
{"In Mixer Right", "Mic Right Switch", "Mic Right"},
{"In Mixer Right", "Mic Left Switch", "Mic Left"},
{"In Mixer Right", "Aux1 Right Switch", "Aux1 Right"},
{"In Mixer Right", "Aux2 Switch", "Aux2 Mono"},
{"In Mixer Right", "Outmix Right Switch", "Out Mixer Right"},
{"INPGA Left", NULL, "In Mixer Left"},
{"ADC Left", NULL, "INPGA Left"},
{"INPGA Right", NULL, "In Mixer Right"},
{"ADC Right", NULL, "INPGA Right"},
/* Output path */
{"Out Mixer Left", "Aux1 Left Switch", "Aux1 Left"},
{"Out Mixer Left", "Aux2 Switch", "Aux2 Mono"},
{"Out Mixer Left", "INPGA Left Switch", "INPGA Left"},
{"Out Mixer Left", "INPGA Right Switch", "INPGA Right"},
{"Out Mixer Left", "DAC Left Switch", "DAC Left"},
{"Out Mixer Right", "Aux1 Right Switch", "Aux1 Right"},
{"Out Mixer Right", "Aux2 Switch", "Aux2 Mono"},
{"Out Mixer Right", "INPGA Right Switch", "INPGA Right"},
{"Out Mixer Right", "INPGA Left Switch", "INPGA Left"},
{"Out Mixer Right", "DAC Right Switch", "DAC Right"},
{"Mono Mixer", "INPGA Right Switch", "INPGA Right"},
{"Mono Mixer", "INPGA Left Switch", "INPGA Left"},
{"Mono Mixer", "Outmix Right Switch", "Out Mixer Right"},
{"Mono Mixer", "Outmix Left Switch", "Out Mixer Left"},
{"OUTPGA Left Enable", NULL, "Out Mixer Left"},
{"OUTPGA Right Enable", NULL, "Out Mixer Right"},
{"Out1 Left", NULL, "OUTPGA Left Enable"},
{"OUT1L", NULL, "Out1 Left"},
{"Out1 Right", NULL, "OUTPGA Right Enable"},
{"OUT1R", NULL, "Out1 Right"},
{"Headphone Left", NULL, "OUTPGA Left Enable"},
{"HPL", NULL, "Headphone Left"},
{"Headphone Right", NULL, "OUTPGA Right Enable"},
{"HPR", NULL, "Headphone Right"},
{"Out2 Mono", NULL, "Mono Mixer"},
{"OUT2", NULL, "Out2 Mono"},
};
/* Codec private data */
struct da7210_priv {
struct regmap *regmap;
unsigned int mclk_rate;
int master;
};
static const struct reg_default da7210_reg_defaults[] = {
{ 0x00, 0x00 },
{ 0x01, 0x11 },
{ 0x03, 0x00 },
{ 0x04, 0x00 },
{ 0x05, 0x00 },
{ 0x06, 0x00 },
{ 0x07, 0x00 },
{ 0x08, 0x00 },
{ 0x09, 0x00 },
{ 0x0a, 0x00 },
{ 0x0b, 0x00 },
{ 0x0c, 0x00 },
{ 0x0d, 0x00 },
{ 0x0e, 0x00 },
{ 0x0f, 0x08 },
{ 0x10, 0x00 },
{ 0x11, 0x00 },
{ 0x12, 0x00 },
{ 0x13, 0x00 },
{ 0x14, 0x08 },
{ 0x15, 0x10 },
{ 0x16, 0x10 },
{ 0x17, 0x54 },
{ 0x18, 0x40 },
{ 0x19, 0x00 },
{ 0x1a, 0x00 },
{ 0x1b, 0x00 },
{ 0x1c, 0x00 },
{ 0x1d, 0x00 },
{ 0x1e, 0x00 },
{ 0x1f, 0x00 },
{ 0x20, 0x00 },
{ 0x21, 0x00 },
{ 0x22, 0x00 },
{ 0x23, 0x02 },
{ 0x24, 0x00 },
{ 0x25, 0x76 },
{ 0x26, 0x00 },
{ 0x27, 0x00 },
{ 0x28, 0x04 },
{ 0x29, 0x00 },
{ 0x2a, 0x00 },
{ 0x2b, 0x30 },
{ 0x2c, 0x2A },
{ 0x83, 0x00 },
{ 0x84, 0x00 },
{ 0x85, 0x00 },
{ 0x86, 0x00 },
{ 0x87, 0x00 },
{ 0x88, 0x00 },
};
static bool da7210_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case DA7210_A_HID_UNLOCK:
case DA7210_A_TEST_UNLOCK:
case DA7210_A_PLL1:
case DA7210_A_CP_MODE:
return false;
default:
return true;
}
}
static bool da7210_volatile_register(struct device *dev,
unsigned int reg)
{
switch (reg) {
case DA7210_STATUS:
return true;
default:
return false;
}
}
/*
* Set PCM DAI word length.
*/
static int da7210_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct da7210_priv *da7210 = snd_soc_component_get_drvdata(component);
u32 dai_cfg1;
u32 fs, sysclk;
/* set DAI source to Left and Right ADC */
snd_soc_component_write(component, DA7210_DAI_SRC_SEL,
DA7210_DAI_OUT_R_SRC | DA7210_DAI_OUT_L_SRC);
/* Enable DAI */
snd_soc_component_write(component, DA7210_DAI_CFG3, DA7210_DAI_OE | DA7210_DAI_EN);
dai_cfg1 = 0xFC & snd_soc_component_read(component, DA7210_DAI_CFG1);
switch (params_width(params)) {
case 16:
dai_cfg1 |= DA7210_DAI_WORD_S16_LE;
break;
case 20:
dai_cfg1 |= DA7210_DAI_WORD_S20_3LE;
break;
case 24:
dai_cfg1 |= DA7210_DAI_WORD_S24_LE;
break;
case 32:
dai_cfg1 |= DA7210_DAI_WORD_S32_LE;
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, DA7210_DAI_CFG1, dai_cfg1);
switch (params_rate(params)) {
case 8000:
fs = DA7210_PLL_FS_8000;
sysclk = 3072000;
break;
case 11025:
fs = DA7210_PLL_FS_11025;
sysclk = 2822400;
break;
case 12000:
fs = DA7210_PLL_FS_12000;
sysclk = 3072000;
break;
case 16000:
fs = DA7210_PLL_FS_16000;
sysclk = 3072000;
break;
case 22050:
fs = DA7210_PLL_FS_22050;
sysclk = 2822400;
break;
case 32000:
fs = DA7210_PLL_FS_32000;
sysclk = 3072000;
break;
case 44100:
fs = DA7210_PLL_FS_44100;
sysclk = 2822400;
break;
case 48000:
fs = DA7210_PLL_FS_48000;
sysclk = 3072000;
break;
case 88200:
fs = DA7210_PLL_FS_88200;
sysclk = 2822400;
break;
case 96000:
fs = DA7210_PLL_FS_96000;
sysclk = 3072000;
break;
default:
return -EINVAL;
}
/* Disable active mode */
snd_soc_component_update_bits(component, DA7210_STARTUP1, DA7210_SC_MST_EN, 0);
snd_soc_component_update_bits(component, DA7210_PLL, DA7210_PLL_FS_MASK, fs);
if (da7210->mclk_rate && (da7210->mclk_rate != sysclk)) {
/* PLL mode, disable PLL bypass */
snd_soc_component_update_bits(component, DA7210_PLL_DIV3, DA7210_PLL_BYP, 0);
if (!da7210->master) {
/* PLL slave mode, also enable SRM */
snd_soc_component_update_bits(component, DA7210_PLL,
(DA7210_MCLK_SRM_EN |
DA7210_MCLK_DET_EN),
(DA7210_MCLK_SRM_EN |
DA7210_MCLK_DET_EN));
}
} else {
/* PLL bypass mode, enable PLL bypass and Auto Detection */
snd_soc_component_update_bits(component, DA7210_PLL, DA7210_MCLK_DET_EN,
DA7210_MCLK_DET_EN);
snd_soc_component_update_bits(component, DA7210_PLL_DIV3, DA7210_PLL_BYP,
DA7210_PLL_BYP);
}
/* Enable active mode */
snd_soc_component_update_bits(component, DA7210_STARTUP1,
DA7210_SC_MST_EN, DA7210_SC_MST_EN);
return 0;
}
/*
* Set DAI mode and Format
*/
static int da7210_set_dai_fmt(struct snd_soc_dai *codec_dai, u32 fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct da7210_priv *da7210 = snd_soc_component_get_drvdata(component);
u32 dai_cfg1;
u32 dai_cfg3;
dai_cfg1 = 0x7f & snd_soc_component_read(component, DA7210_DAI_CFG1);
dai_cfg3 = 0xfc & snd_soc_component_read(component, DA7210_DAI_CFG3);
if ((snd_soc_component_read(component, DA7210_PLL) & DA7210_PLL_EN) &&
(!(snd_soc_component_read(component, DA7210_PLL_DIV3) & DA7210_PLL_BYP)))
return -EINVAL;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
da7210->master = 1;
dai_cfg1 |= DA7210_DAI_MODE_MASTER;
break;
case SND_SOC_DAIFMT_CBS_CFS:
da7210->master = 0;
dai_cfg1 |= DA7210_DAI_MODE_SLAVE;
break;
default:
return -EINVAL;
}
/* FIXME
*
* It support I2S only now
*/
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
dai_cfg3 |= DA7210_DAI_FORMAT_I2SMODE;
break;
case SND_SOC_DAIFMT_LEFT_J:
dai_cfg3 |= DA7210_DAI_FORMAT_LEFT_J;
break;
case SND_SOC_DAIFMT_RIGHT_J:
dai_cfg3 |= DA7210_DAI_FORMAT_RIGHT_J;
break;
default:
return -EINVAL;
}
/* FIXME
*
* It support 64bit data transmission only now
*/
dai_cfg1 |= DA7210_DAI_FLEN_64BIT;
snd_soc_component_write(component, DA7210_DAI_CFG1, dai_cfg1);
snd_soc_component_write(component, DA7210_DAI_CFG3, dai_cfg3);
return 0;
}
static int da7210_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
u8 mute_reg = snd_soc_component_read(component, DA7210_DAC_HPF) & 0xFB;
if (mute)
snd_soc_component_write(component, DA7210_DAC_HPF, mute_reg | 0x4);
else
snd_soc_component_write(component, DA7210_DAC_HPF, mute_reg);
return 0;
}
#define DA7210_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static int da7210_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct da7210_priv *da7210 = snd_soc_component_get_drvdata(component);
switch (clk_id) {
case DA7210_CLKSRC_MCLK:
switch (freq) {
case 12000000:
case 13000000:
case 13500000:
case 14400000:
case 19200000:
case 19680000:
case 19800000:
da7210->mclk_rate = freq;
return 0;
default:
dev_err(codec_dai->dev, "Unsupported MCLK value %d\n",
freq);
return -EINVAL;
}
break;
default:
dev_err(codec_dai->dev, "Unknown clock source %d\n", clk_id);
return -EINVAL;
}
}
/**
* da7210_set_dai_pll :Configure the codec PLL
* @codec_dai: pointer to codec DAI
* @pll_id: da7210 has only one pll, so pll_id is always zero
* @source: clock source
* @fref: MCLK frequency, should be < 20MHz
* @fout: FsDM value, Refer page 44 & 45 of datasheet
*
* Note: Supported PLL input frequencies are 12MHz, 13MHz, 13.5MHz, 14.4MHz,
* 19.2MHz, 19.6MHz and 19.8MHz
*
* Return: Zero for success, negative error code for error
*/
static int da7210_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
int source, unsigned int fref, unsigned int fout)
{
struct snd_soc_component *component = codec_dai->component;
struct da7210_priv *da7210 = snd_soc_component_get_drvdata(component);
u8 pll_div1, pll_div2, pll_div3, cnt;
/* In slave mode, there is only one set of divisors */
if (!da7210->master)
fout = 2822400;
/* Search pll div array for correct divisors */
for (cnt = 0; cnt < ARRAY_SIZE(da7210_pll_div); cnt++) {
/* check fref, mode and fout */
if ((fref == da7210_pll_div[cnt].fref) &&
(da7210->master == da7210_pll_div[cnt].mode) &&
(fout == da7210_pll_div[cnt].fout)) {
/* all match, pick up divisors */
pll_div1 = da7210_pll_div[cnt].div1;
pll_div2 = da7210_pll_div[cnt].div2;
pll_div3 = da7210_pll_div[cnt].div3;
break;
}
}
if (cnt >= ARRAY_SIZE(da7210_pll_div))
goto err;
/* Disable active mode */
snd_soc_component_update_bits(component, DA7210_STARTUP1, DA7210_SC_MST_EN, 0);
/* Write PLL dividers */
snd_soc_component_write(component, DA7210_PLL_DIV1, pll_div1);
snd_soc_component_write(component, DA7210_PLL_DIV2, pll_div2);
snd_soc_component_update_bits(component, DA7210_PLL_DIV3,
DA7210_PLL_DIV_L_MASK, pll_div3);
/* Enable PLL */
snd_soc_component_update_bits(component, DA7210_PLL, DA7210_PLL_EN, DA7210_PLL_EN);
/* Enable active mode */
snd_soc_component_update_bits(component, DA7210_STARTUP1, DA7210_SC_MST_EN,
DA7210_SC_MST_EN);
return 0;
err:
dev_err(codec_dai->dev, "Unsupported PLL input frequency %d\n", fref);
return -EINVAL;
}
/* DAI operations */
static const struct snd_soc_dai_ops da7210_dai_ops = {
.hw_params = da7210_hw_params,
.set_fmt = da7210_set_dai_fmt,
.set_sysclk = da7210_set_dai_sysclk,
.set_pll = da7210_set_dai_pll,
.mute_stream = da7210_mute,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver da7210_dai = {
.name = "da7210-hifi",
/* playback capabilities */
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = DA7210_FORMATS,
},
/* capture capabilities */
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = DA7210_FORMATS,
},
.ops = &da7210_dai_ops,
.symmetric_rate = 1,
};
static int da7210_probe(struct snd_soc_component *component)
{
struct da7210_priv *da7210 = snd_soc_component_get_drvdata(component);
dev_info(component->dev, "DA7210 Audio Codec %s\n", DA7210_VERSION);
da7210->mclk_rate = 0; /* This will be set from set_sysclk() */
da7210->master = 0; /* This will be set from set_fmt() */
/* Enable internal regulator & bias current */
snd_soc_component_write(component, DA7210_CONTROL, DA7210_REG_EN | DA7210_BIAS_EN);
/*
* ADC settings
*/
/* Enable Left & Right MIC PGA and Mic Bias */
snd_soc_component_write(component, DA7210_MIC_L, DA7210_MIC_L_EN | DA7210_MICBIAS_EN);
snd_soc_component_write(component, DA7210_MIC_R, DA7210_MIC_R_EN);
/* Enable Left and Right input PGA */
snd_soc_component_write(component, DA7210_INMIX_L, DA7210_IN_L_EN);
snd_soc_component_write(component, DA7210_INMIX_R, DA7210_IN_R_EN);
/* Enable Left and Right ADC */
snd_soc_component_write(component, DA7210_ADC, DA7210_ADC_L_EN | DA7210_ADC_R_EN);
/*
* DAC settings
*/
/* Enable Left and Right DAC */
snd_soc_component_write(component, DA7210_DAC_SEL,
DA7210_DAC_L_SRC_DAI_L | DA7210_DAC_L_EN |
DA7210_DAC_R_SRC_DAI_R | DA7210_DAC_R_EN);
/* Enable Left and Right out PGA */
snd_soc_component_write(component, DA7210_OUTMIX_L, DA7210_OUT_L_EN);
snd_soc_component_write(component, DA7210_OUTMIX_R, DA7210_OUT_R_EN);
/* Enable Left and Right HeadPhone PGA */
snd_soc_component_write(component, DA7210_HP_CFG,
DA7210_HP_2CAP_MODE | DA7210_HP_SENSE_EN |
DA7210_HP_L_EN | DA7210_HP_MODE | DA7210_HP_R_EN);
/* Enable ramp mode for DAC gain update */
snd_soc_component_write(component, DA7210_SOFTMUTE, DA7210_RAMP_EN);
/*
* For DA7210 codec, there are two ways to enable/disable analog IOs
* and ADC/DAC,
* (1) Using "Enable Bit" of register associated with that IO
* (or ADC/DAC)
* e.g. Mic Left can be enabled using bit 7 of MIC_L(0x7) reg
*
* (2) Using "Standby Bit" of STARTUP2 or STARTUP3 register
* e.g. Mic left can be put to STANDBY using bit 0 of STARTUP3(0x5)
*
* Out of these two methods, the one using STANDBY bits is preferred
* way to enable/disable individual blocks. This is because STANDBY
* registers are part of system controller which allows system power
* up/down in a controlled, pop-free manner. Also, as per application
* note of DA7210, STANDBY register bits are only effective if a
* particular IO (or ADC/DAC) is already enabled using enable/disable
* register bits. Keeping these things in mind, current DAPM
* implementation manipulates only STANDBY bits.
*
* Overall implementation can be outlined as below,
*
* - "Enable bit" of an IO or ADC/DAC is used to enable it in probe()
* - "STANDBY bit" is controlled by DAPM
*/
/* Enable Line out amplifiers */
snd_soc_component_write(component, DA7210_OUT1_L, DA7210_OUT1_L_EN);
snd_soc_component_write(component, DA7210_OUT1_R, DA7210_OUT1_R_EN);
snd_soc_component_write(component, DA7210_OUT2, DA7210_OUT2_EN |
DA7210_OUT2_OUTMIX_L | DA7210_OUT2_OUTMIX_R);
/* Enable Aux1 */
snd_soc_component_write(component, DA7210_AUX1_L, DA7210_AUX1_L_EN);
snd_soc_component_write(component, DA7210_AUX1_R, DA7210_AUX1_R_EN);
/* Enable Aux2 */
snd_soc_component_write(component, DA7210_AUX2, DA7210_AUX2_EN);
/* Set PLL Master clock range 10-20 MHz, enable PLL bypass */
snd_soc_component_write(component, DA7210_PLL_DIV3, DA7210_MCLK_RANGE_10_20_MHZ |
DA7210_PLL_BYP);
/* Diable PLL and bypass it */
snd_soc_component_write(component, DA7210_PLL, DA7210_PLL_FS_48000);
/* Activate all enabled subsystem */
snd_soc_component_write(component, DA7210_STARTUP1, DA7210_SC_MST_EN);
dev_info(component->dev, "DA7210 Audio Codec %s\n", DA7210_VERSION);
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_da7210 = {
.probe = da7210_probe,
.controls = da7210_snd_controls,
.num_controls = ARRAY_SIZE(da7210_snd_controls),
.dapm_widgets = da7210_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(da7210_dapm_widgets),
.dapm_routes = da7210_audio_map,
.num_dapm_routes = ARRAY_SIZE(da7210_audio_map),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
#if IS_ENABLED(CONFIG_I2C)
static const struct reg_sequence da7210_regmap_i2c_patch[] = {
/* System controller master disable */
{ DA7210_STARTUP1, 0x00 },
/* Set PLL Master clock range 10-20 MHz */
{ DA7210_PLL_DIV3, DA7210_MCLK_RANGE_10_20_MHZ },
/* to unlock */
{ DA7210_A_HID_UNLOCK, 0x8B},
{ DA7210_A_TEST_UNLOCK, 0xB4},
{ DA7210_A_PLL1, 0x01},
{ DA7210_A_CP_MODE, 0x7C},
/* to re-lock */
{ DA7210_A_HID_UNLOCK, 0x00},
{ DA7210_A_TEST_UNLOCK, 0x00},
};
static const struct regmap_config da7210_regmap_config_i2c = {
.reg_bits = 8,
.val_bits = 8,
.reg_defaults = da7210_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(da7210_reg_defaults),
.volatile_reg = da7210_volatile_register,
.readable_reg = da7210_readable_register,
.cache_type = REGCACHE_RBTREE,
};
static int da7210_i2c_probe(struct i2c_client *i2c)
{
struct da7210_priv *da7210;
int ret;
da7210 = devm_kzalloc(&i2c->dev, sizeof(struct da7210_priv),
GFP_KERNEL);
if (!da7210)
return -ENOMEM;
i2c_set_clientdata(i2c, da7210);
da7210->regmap = devm_regmap_init_i2c(i2c, &da7210_regmap_config_i2c);
if (IS_ERR(da7210->regmap)) {
ret = PTR_ERR(da7210->regmap);
dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);
return ret;
}
ret = regmap_register_patch(da7210->regmap, da7210_regmap_i2c_patch,
ARRAY_SIZE(da7210_regmap_i2c_patch));
if (ret != 0)
dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_da7210, &da7210_dai, 1);
if (ret < 0)
dev_err(&i2c->dev, "Failed to register component: %d\n", ret);
return ret;
}
static const struct i2c_device_id da7210_i2c_id[] = {
{ "da7210", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, da7210_i2c_id);
/* I2C codec control layer */
static struct i2c_driver da7210_i2c_driver = {
.driver = {
.name = "da7210",
},
.probe = da7210_i2c_probe,
.id_table = da7210_i2c_id,
};
#endif
#if defined(CONFIG_SPI_MASTER)
static const struct reg_sequence da7210_regmap_spi_patch[] = {
/* Dummy read to give two pulses over nCS for SPI */
{ DA7210_AUX2, 0x00 },
{ DA7210_AUX2, 0x00 },
/* System controller master disable */
{ DA7210_STARTUP1, 0x00 },
/* Set PLL Master clock range 10-20 MHz */
{ DA7210_PLL_DIV3, DA7210_MCLK_RANGE_10_20_MHZ },
/* to set PAGE1 of SPI register space */
{ DA7210_PAGE_CONTROL, 0x80 },
/* to unlock */
{ DA7210_A_HID_UNLOCK, 0x8B},
{ DA7210_A_TEST_UNLOCK, 0xB4},
{ DA7210_A_PLL1, 0x01},
{ DA7210_A_CP_MODE, 0x7C},
/* to re-lock */
{ DA7210_A_HID_UNLOCK, 0x00},
{ DA7210_A_TEST_UNLOCK, 0x00},
/* to set back PAGE0 of SPI register space */
{ DA7210_PAGE_CONTROL, 0x00 },
};
static const struct regmap_config da7210_regmap_config_spi = {
.reg_bits = 8,
.val_bits = 8,
.read_flag_mask = 0x01,
.write_flag_mask = 0x00,
.reg_defaults = da7210_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(da7210_reg_defaults),
.volatile_reg = da7210_volatile_register,
.readable_reg = da7210_readable_register,
.cache_type = REGCACHE_RBTREE,
};
static int da7210_spi_probe(struct spi_device *spi)
{
struct da7210_priv *da7210;
int ret;
da7210 = devm_kzalloc(&spi->dev, sizeof(struct da7210_priv),
GFP_KERNEL);
if (!da7210)
return -ENOMEM;
spi_set_drvdata(spi, da7210);
da7210->regmap = devm_regmap_init_spi(spi, &da7210_regmap_config_spi);
if (IS_ERR(da7210->regmap)) {
ret = PTR_ERR(da7210->regmap);
dev_err(&spi->dev, "Failed to register regmap: %d\n", ret);
return ret;
}
ret = regmap_register_patch(da7210->regmap, da7210_regmap_spi_patch,
ARRAY_SIZE(da7210_regmap_spi_patch));
if (ret != 0)
dev_warn(&spi->dev, "Failed to apply regmap patch: %d\n", ret);
ret = devm_snd_soc_register_component(&spi->dev,
&soc_component_dev_da7210, &da7210_dai, 1);
return ret;
}
static struct spi_driver da7210_spi_driver = {
.driver = {
.name = "da7210",
},
.probe = da7210_spi_probe,
};
#endif
static int __init da7210_modinit(void)
{
int ret = 0;
#if IS_ENABLED(CONFIG_I2C)
ret = i2c_add_driver(&da7210_i2c_driver);
if (ret)
return ret;
#endif
#if defined(CONFIG_SPI_MASTER)
ret = spi_register_driver(&da7210_spi_driver);
if (ret) {
printk(KERN_ERR "Failed to register da7210 SPI driver: %d\n",
ret);
}
#endif
return ret;
}
module_init(da7210_modinit);
static void __exit da7210_exit(void)
{
#if IS_ENABLED(CONFIG_I2C)
i2c_del_driver(&da7210_i2c_driver);
#endif
#if defined(CONFIG_SPI_MASTER)
spi_unregister_driver(&da7210_spi_driver);
#endif
}
module_exit(da7210_exit);
MODULE_DESCRIPTION("ASoC DA7210 driver");
MODULE_AUTHOR("David Chen, Kuninori Morimoto");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/da7210.c |
// SPDX-License-Identifier: GPL-2.0
//
// Ingenic JZ4760 CODEC driver
//
// Copyright (C) 2021, Christophe Branchereau <[email protected]>
// Copyright (C) 2021, Paul Cercueil <[email protected]>
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/time64.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include <sound/soc-dapm.h>
#include <sound/tlv.h>
#define ICDC_RGADW_OFFSET 0x00
#define ICDC_RGDATA_OFFSET 0x04
/* ICDC internal register access control register(RGADW) */
#define ICDC_RGADW_RGWR BIT(16)
#define ICDC_RGADW_RGADDR_MASK GENMASK(14, 8)
#define ICDC_RGADW_RGDIN_MASK GENMASK(7, 0)
/* ICDC internal register data output register (RGDATA)*/
#define ICDC_RGDATA_IRQ BIT(8)
#define ICDC_RGDATA_RGDOUT_MASK GENMASK(7, 0)
/* Internal register space, accessed through regmap */
enum {
JZ4760_CODEC_REG_SR,
JZ4760_CODEC_REG_AICR,
JZ4760_CODEC_REG_CR1,
JZ4760_CODEC_REG_CR2,
JZ4760_CODEC_REG_CR3,
JZ4760_CODEC_REG_CR4,
JZ4760_CODEC_REG_CCR1,
JZ4760_CODEC_REG_CCR2,
JZ4760_CODEC_REG_PMR1,
JZ4760_CODEC_REG_PMR2,
JZ4760_CODEC_REG_ICR,
JZ4760_CODEC_REG_IFR,
JZ4760_CODEC_REG_GCR1,
JZ4760_CODEC_REG_GCR2,
JZ4760_CODEC_REG_GCR3,
JZ4760_CODEC_REG_GCR4,
JZ4760_CODEC_REG_GCR5,
JZ4760_CODEC_REG_GCR6,
JZ4760_CODEC_REG_GCR7,
JZ4760_CODEC_REG_GCR8,
JZ4760_CODEC_REG_GCR9,
JZ4760_CODEC_REG_AGC1,
JZ4760_CODEC_REG_AGC2,
JZ4760_CODEC_REG_AGC3,
JZ4760_CODEC_REG_AGC4,
JZ4760_CODEC_REG_AGC5,
JZ4760_CODEC_REG_MIX1,
JZ4760_CODEC_REG_MIX2,
};
#define REG_AICR_DAC_ADWL_MASK GENMASK(7, 6)
#define REG_AICR_DAC_SERIAL BIT(3)
#define REG_AICR_DAC_I2S BIT(1)
#define REG_AICR_ADC_ADWL_MASK GENMASK(5, 4)
#define REG_AICR_ADC_SERIAL BIT(2)
#define REG_AICR_ADC_I2S BIT(0)
#define REG_CR1_HP_LOAD BIT(7)
#define REG_CR1_HP_MUTE BIT(5)
#define REG_CR1_LO_MUTE_OFFSET 4
#define REG_CR1_BTL_MUTE_OFFSET 3
#define REG_CR1_OUTSEL_OFFSET 0
#define REG_CR1_OUTSEL_MASK GENMASK(1, REG_CR1_OUTSEL_OFFSET)
#define REG_CR2_DAC_MONO BIT(7)
#define REG_CR2_DAC_MUTE BIT(5)
#define REG_CR2_DAC_NOMAD BIT(1)
#define REG_CR2_DAC_RIGHT_ONLY BIT(0)
#define REG_CR3_ADC_INSEL_OFFSET 2
#define REG_CR3_ADC_INSEL_MASK GENMASK(3, REG_CR3_ADC_INSEL_OFFSET)
#define REG_CR3_MICSTEREO_OFFSET 1
#define REG_CR3_MICDIFF_OFFSET 0
#define REG_CR4_ADC_HPF_OFFSET 7
#define REG_CR4_ADC_RIGHT_ONLY BIT(0)
#define REG_CCR1_CRYSTAL_MASK GENMASK(3, 0)
#define REG_CCR2_DAC_FREQ_MASK GENMASK(7, 4)
#define REG_CCR2_ADC_FREQ_MASK GENMASK(3, 0)
#define REG_PMR1_SB BIT(7)
#define REG_PMR1_SB_SLEEP BIT(6)
#define REG_PMR1_SB_AIP_OFFSET 5
#define REG_PMR1_SB_LINE_OFFSET 4
#define REG_PMR1_SB_MIC1_OFFSET 3
#define REG_PMR1_SB_MIC2_OFFSET 2
#define REG_PMR1_SB_BYPASS_OFFSET 1
#define REG_PMR1_SB_MICBIAS_OFFSET 0
#define REG_PMR2_SB_ADC_OFFSET 4
#define REG_PMR2_SB_HP_OFFSET 3
#define REG_PMR2_SB_BTL_OFFSET 2
#define REG_PMR2_SB_LOUT_OFFSET 1
#define REG_PMR2_SB_DAC_OFFSET 0
#define REG_ICR_INT_FORM_MASK GENMASK(7, 6)
#define REG_ICR_ALL_MASK GENMASK(5, 0)
#define REG_ICR_JACK_MASK BIT(5)
#define REG_ICR_SCMC_MASK BIT(4)
#define REG_ICR_RUP_MASK BIT(3)
#define REG_ICR_RDO_MASK BIT(2)
#define REG_ICR_GUP_MASK BIT(1)
#define REG_ICR_GDO_MASK BIT(0)
#define REG_IFR_ALL_MASK GENMASK(5, 0)
#define REG_IFR_JACK BIT(6)
#define REG_IFR_JACK_EVENT BIT(5)
#define REG_IFR_SCMC BIT(4)
#define REG_IFR_RUP BIT(3)
#define REG_IFR_RDO BIT(2)
#define REG_IFR_GUP BIT(1)
#define REG_IFR_GDO BIT(0)
#define REG_GCR_GAIN_OFFSET 0
#define REG_GCR_GAIN_MAX 0x1f
#define REG_GCR_RL BIT(7)
#define REG_GCR_GIM1_MASK GENMASK(5, 3)
#define REG_GCR_GIM2_MASK GENMASK(2, 0)
#define REG_GCR_GIM_GAIN_MAX 7
#define REG_AGC1_EN BIT(7)
#define REG_AGC1_TARGET_MASK GENMASK(5, 2)
#define REG_AGC2_NG_THR_MASK GENMASK(6, 4)
#define REG_AGC2_HOLD_MASK GENMASK(3, 0)
#define REG_AGC3_ATK_MASK GENMASK(7, 4)
#define REG_AGC3_DCY_MASK GENMASK(3, 0)
#define REG_AGC4_AGC_MAX_MASK GENMASK(4, 0)
#define REG_AGC5_AGC_MIN_MASK GENMASK(4, 0)
#define REG_MIX1_MIX_REC_MASK GENMASK(7, 6)
#define REG_MIX1_GIMIX_MASK GENMASK(4, 0)
#define REG_MIX2_DAC_MIX_MASK GENMASK(7, 6)
#define REG_MIX2_GOMIX_MASK GENMASK(4, 0)
/* codec private data */
struct jz_codec {
struct device *dev;
struct regmap *regmap;
void __iomem *base;
struct clk *clk;
};
static int jz4760_codec_set_bias_level(struct snd_soc_component *codec,
enum snd_soc_bias_level level)
{
struct jz_codec *jz_codec = snd_soc_component_get_drvdata(codec);
struct regmap *regmap = jz_codec->regmap;
switch (level) {
case SND_SOC_BIAS_PREPARE:
/* Reset all interrupt flags. */
regmap_write(regmap, JZ4760_CODEC_REG_IFR, REG_IFR_ALL_MASK);
regmap_clear_bits(regmap, JZ4760_CODEC_REG_PMR1, REG_PMR1_SB);
msleep(250);
regmap_clear_bits(regmap, JZ4760_CODEC_REG_PMR1, REG_PMR1_SB_SLEEP);
msleep(400);
break;
case SND_SOC_BIAS_STANDBY:
regmap_set_bits(regmap, JZ4760_CODEC_REG_PMR1, REG_PMR1_SB_SLEEP);
regmap_set_bits(regmap, JZ4760_CODEC_REG_PMR1, REG_PMR1_SB);
break;
default:
break;
}
return 0;
}
static int jz4760_codec_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *codec = dai->component;
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(codec);
int ret = 0;
/*
* SYSCLK output from the codec to the AIC is required to keep the
* DMA transfer going during playback when all audible outputs have
* been disabled.
*/
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
ret = snd_soc_dapm_force_enable_pin(dapm, "SYSCLK");
return ret;
}
static void jz4760_codec_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *codec = dai->component;
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(codec);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
snd_soc_dapm_disable_pin(dapm, "SYSCLK");
}
static int jz4760_codec_pcm_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
struct snd_soc_component *codec = dai->component;
int ret = 0;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
snd_soc_component_force_bias_level(codec, SND_SOC_BIAS_ON);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
/* do nothing */
break;
default:
ret = -EINVAL;
}
return ret;
}
static int jz4760_codec_mute_stream(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *codec = dai->component;
struct jz_codec *jz_codec = snd_soc_component_get_drvdata(codec);
unsigned int gain_bit = mute ? REG_IFR_GDO : REG_IFR_GUP;
unsigned int val, reg;
int change, err;
change = snd_soc_component_update_bits(codec, JZ4760_CODEC_REG_CR2,
REG_CR2_DAC_MUTE,
mute ? REG_CR2_DAC_MUTE : 0);
if (change == 1) {
regmap_read(jz_codec->regmap, JZ4760_CODEC_REG_PMR2, &val);
if (val & BIT(REG_PMR2_SB_DAC_OFFSET))
return 1;
err = regmap_read_poll_timeout(jz_codec->regmap,
JZ4760_CODEC_REG_IFR,
val, val & gain_bit,
1000, 1 * USEC_PER_SEC);
if (err) {
dev_err(jz_codec->dev,
"Timeout while setting digital mute: %d", err);
return err;
}
/* clear GUP/GDO flag */
regmap_write(jz_codec->regmap, JZ4760_CODEC_REG_IFR, gain_bit);
}
regmap_read(jz_codec->regmap, JZ4760_CODEC_REG_CR2, ®);
return 0;
}
/* unit: 0.01dB */
static const DECLARE_TLV_DB_MINMAX_MUTE(dac_tlv, -3100, 100);
static const DECLARE_TLV_DB_SCALE(adc_tlv, 0, 100, 0);
static const DECLARE_TLV_DB_MINMAX(out_tlv, -2500, 100);
static const DECLARE_TLV_DB_SCALE(linein_tlv, -2500, 100, 0);
static const DECLARE_TLV_DB_MINMAX(mixer_tlv, -3100, 0);
/* Unconditional controls. */
static const struct snd_kcontrol_new jz4760_codec_snd_controls[] = {
/* record gain control */
SOC_DOUBLE_R_TLV("PCM Capture Volume",
JZ4760_CODEC_REG_GCR9, JZ4760_CODEC_REG_GCR8,
REG_GCR_GAIN_OFFSET, REG_GCR_GAIN_MAX, 0, adc_tlv),
SOC_DOUBLE_R_TLV("Line In Bypass Playback Volume",
JZ4760_CODEC_REG_GCR4, JZ4760_CODEC_REG_GCR3,
REG_GCR_GAIN_OFFSET, REG_GCR_GAIN_MAX, 1, linein_tlv),
SOC_SINGLE_TLV("Mixer Capture Volume",
JZ4760_CODEC_REG_MIX1,
REG_GCR_GAIN_OFFSET, REG_GCR_GAIN_MAX, 1, mixer_tlv),
SOC_SINGLE_TLV("Mixer Playback Volume",
JZ4760_CODEC_REG_MIX2,
REG_GCR_GAIN_OFFSET, REG_GCR_GAIN_MAX, 1, mixer_tlv),
SOC_SINGLE("High-Pass Filter Capture Switch",
JZ4760_CODEC_REG_CR4,
REG_CR4_ADC_HPF_OFFSET, 1, 0),
};
static const struct snd_kcontrol_new jz4760_codec_pcm_playback_controls[] = {
{
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "Volume",
.info = snd_soc_info_volsw,
.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ
| SNDRV_CTL_ELEM_ACCESS_READWRITE,
.tlv.p = dac_tlv,
.get = snd_soc_dapm_get_volsw,
.put = snd_soc_dapm_put_volsw,
.private_value = SOC_DOUBLE_R_VALUE(JZ4760_CODEC_REG_GCR6,
JZ4760_CODEC_REG_GCR5,
REG_GCR_GAIN_OFFSET,
REG_GCR_GAIN_MAX, 1),
},
};
static const struct snd_kcontrol_new jz4760_codec_hp_playback_controls[] = {
{
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "Volume",
.info = snd_soc_info_volsw,
.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ
| SNDRV_CTL_ELEM_ACCESS_READWRITE,
.tlv.p = out_tlv,
.get = snd_soc_dapm_get_volsw,
.put = snd_soc_dapm_put_volsw,
.private_value = SOC_DOUBLE_R_VALUE(JZ4760_CODEC_REG_GCR2,
JZ4760_CODEC_REG_GCR1,
REG_GCR_GAIN_OFFSET,
REG_GCR_GAIN_MAX, 1),
},
};
static int hpout_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *codec = snd_soc_dapm_to_component(w->dapm);
struct jz_codec *jz_codec = snd_soc_component_get_drvdata(codec);
unsigned int val;
int err;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* unmute HP */
regmap_clear_bits(jz_codec->regmap, JZ4760_CODEC_REG_CR1,
REG_CR1_HP_MUTE);
break;
case SND_SOC_DAPM_POST_PMU:
/* wait for ramp-up complete (RUP) */
err = regmap_read_poll_timeout(jz_codec->regmap,
JZ4760_CODEC_REG_IFR,
val, val & REG_IFR_RUP,
1000, 1 * USEC_PER_SEC);
if (err) {
dev_err(jz_codec->dev, "RUP timeout: %d", err);
return err;
}
/* clear RUP flag */
regmap_set_bits(jz_codec->regmap, JZ4760_CODEC_REG_IFR,
REG_IFR_RUP);
break;
case SND_SOC_DAPM_POST_PMD:
/* mute HP */
regmap_set_bits(jz_codec->regmap, JZ4760_CODEC_REG_CR1,
REG_CR1_HP_MUTE);
err = regmap_read_poll_timeout(jz_codec->regmap,
JZ4760_CODEC_REG_IFR,
val, val & REG_IFR_RDO,
1000, 1 * USEC_PER_SEC);
if (err) {
dev_err(jz_codec->dev, "RDO timeout: %d", err);
return err;
}
/* clear RDO flag */
regmap_set_bits(jz_codec->regmap, JZ4760_CODEC_REG_IFR,
REG_IFR_RDO);
break;
}
return 0;
}
static const char * const jz4760_codec_hp_texts[] = {
"PCM", "Line In", "Mic 1", "Mic 2"
};
static const unsigned int jz4760_codec_hp_values[] = { 3, 2, 0, 1 };
static SOC_VALUE_ENUM_SINGLE_DECL(jz4760_codec_hp_enum,
JZ4760_CODEC_REG_CR1,
REG_CR1_OUTSEL_OFFSET,
REG_CR1_OUTSEL_MASK >> REG_CR1_OUTSEL_OFFSET,
jz4760_codec_hp_texts,
jz4760_codec_hp_values);
static const struct snd_kcontrol_new jz4760_codec_hp_source =
SOC_DAPM_ENUM("Route", jz4760_codec_hp_enum);
static const char * const jz4760_codec_cap_texts[] = {
"Line In", "Mic 1", "Mic 2"
};
static const unsigned int jz4760_codec_cap_values[] = { 2, 0, 1 };
static SOC_VALUE_ENUM_SINGLE_DECL(jz4760_codec_cap_enum,
JZ4760_CODEC_REG_CR3,
REG_CR3_ADC_INSEL_OFFSET,
REG_CR3_ADC_INSEL_MASK >> REG_CR3_ADC_INSEL_OFFSET,
jz4760_codec_cap_texts,
jz4760_codec_cap_values);
static const struct snd_kcontrol_new jz4760_codec_cap_source =
SOC_DAPM_ENUM("Route", jz4760_codec_cap_enum);
static const struct snd_kcontrol_new jz4760_codec_mic_controls[] = {
SOC_DAPM_SINGLE("Stereo Capture Switch", JZ4760_CODEC_REG_CR3,
REG_CR3_MICSTEREO_OFFSET, 1, 0),
};
static const struct snd_kcontrol_new jz4760_codec_line_out_switch =
SOC_DAPM_SINGLE("Switch", JZ4760_CODEC_REG_CR1,
REG_CR1_LO_MUTE_OFFSET, 0, 0);
static const struct snd_kcontrol_new jz4760_codec_btl_out_switch =
SOC_DAPM_SINGLE("Switch", JZ4760_CODEC_REG_CR1,
REG_CR1_BTL_MUTE_OFFSET, 0, 0);
static const struct snd_soc_dapm_widget jz4760_codec_dapm_widgets[] = {
SND_SOC_DAPM_PGA_E("HP Out", JZ4760_CODEC_REG_PMR2,
REG_PMR2_SB_HP_OFFSET, 1, NULL, 0, hpout_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SWITCH("Line Out", JZ4760_CODEC_REG_PMR2,
REG_PMR2_SB_LOUT_OFFSET, 1,
&jz4760_codec_line_out_switch),
SND_SOC_DAPM_SWITCH("BTL Out", JZ4760_CODEC_REG_PMR2,
REG_PMR2_SB_BTL_OFFSET, 1,
&jz4760_codec_btl_out_switch),
SND_SOC_DAPM_PGA("Line In", JZ4760_CODEC_REG_PMR1,
REG_PMR1_SB_LINE_OFFSET, 1, NULL, 0),
SND_SOC_DAPM_MUX("Headphones Source", SND_SOC_NOPM, 0, 0,
&jz4760_codec_hp_source),
SND_SOC_DAPM_MUX("Capture Source", SND_SOC_NOPM, 0, 0,
&jz4760_codec_cap_source),
SND_SOC_DAPM_PGA("Mic 1", JZ4760_CODEC_REG_PMR1,
REG_PMR1_SB_MIC1_OFFSET, 1, NULL, 0),
SND_SOC_DAPM_PGA("Mic 2", JZ4760_CODEC_REG_PMR1,
REG_PMR1_SB_MIC2_OFFSET, 1, NULL, 0),
SND_SOC_DAPM_PGA("Mic Diff", JZ4760_CODEC_REG_CR3,
REG_CR3_MICDIFF_OFFSET, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Mic", SND_SOC_NOPM, 0, 0,
jz4760_codec_mic_controls,
ARRAY_SIZE(jz4760_codec_mic_controls)),
SND_SOC_DAPM_PGA("Line In Bypass", JZ4760_CODEC_REG_PMR1,
REG_PMR1_SB_BYPASS_OFFSET, 1, NULL, 0),
SND_SOC_DAPM_ADC("ADC", "Capture", JZ4760_CODEC_REG_PMR2,
REG_PMR2_SB_ADC_OFFSET, 1),
SND_SOC_DAPM_DAC("DAC", "Playback", JZ4760_CODEC_REG_PMR2,
REG_PMR2_SB_DAC_OFFSET, 1),
SND_SOC_DAPM_MIXER("PCM Playback", SND_SOC_NOPM, 0, 0,
jz4760_codec_pcm_playback_controls,
ARRAY_SIZE(jz4760_codec_pcm_playback_controls)),
SND_SOC_DAPM_MIXER("Headphones Playback", SND_SOC_NOPM, 0, 0,
jz4760_codec_hp_playback_controls,
ARRAY_SIZE(jz4760_codec_hp_playback_controls)),
SND_SOC_DAPM_SUPPLY("MICBIAS", JZ4760_CODEC_REG_PMR1,
REG_PMR1_SB_MICBIAS_OFFSET, 1, NULL, 0),
SND_SOC_DAPM_INPUT("MIC1P"),
SND_SOC_DAPM_INPUT("MIC1N"),
SND_SOC_DAPM_INPUT("MIC2P"),
SND_SOC_DAPM_INPUT("MIC2N"),
SND_SOC_DAPM_INPUT("LLINEIN"),
SND_SOC_DAPM_INPUT("RLINEIN"),
SND_SOC_DAPM_OUTPUT("LHPOUT"),
SND_SOC_DAPM_OUTPUT("RHPOUT"),
SND_SOC_DAPM_OUTPUT("LOUT"),
SND_SOC_DAPM_OUTPUT("ROUT"),
SND_SOC_DAPM_OUTPUT("BTLP"),
SND_SOC_DAPM_OUTPUT("BTLN"),
SND_SOC_DAPM_OUTPUT("SYSCLK"),
};
/* Unconditional routes. */
static const struct snd_soc_dapm_route jz4760_codec_dapm_routes[] = {
{ "Mic 1", NULL, "MIC1P" },
{ "Mic Diff", NULL, "MIC1N" },
{ "Mic 1", NULL, "Mic Diff" },
{ "Mic 2", NULL, "MIC2P" },
{ "Mic Diff", NULL, "MIC2N" },
{ "Mic 2", NULL, "Mic Diff" },
{ "Line In", NULL, "LLINEIN" },
{ "Line In", NULL, "RLINEIN" },
{ "Mic", "Stereo Capture Switch", "Mic 1" },
{ "Mic", "Stereo Capture Switch", "Mic 2" },
{ "Headphones Source", "Mic 1", "Mic" },
{ "Headphones Source", "Mic 2", "Mic" },
{ "Capture Source", "Mic 1", "Mic" },
{ "Capture Source", "Mic 2", "Mic" },
{ "Capture Source", "Line In", "Line In" },
{ "Capture Source", "Mic 1", "Mic 1" },
{ "Capture Source", "Mic 2", "Mic 2" },
{ "ADC", NULL, "Capture Source" },
{ "Line In Bypass", NULL, "Line In" },
{ "Headphones Source", "Mic 1", "Mic 1" },
{ "Headphones Source", "Mic 2", "Mic 2" },
{ "Headphones Source", "Line In", "Line In Bypass" },
{ "Headphones Source", "PCM", "Headphones Playback" },
{ "HP Out", NULL, "Headphones Source" },
{ "LHPOUT", NULL, "HP Out" },
{ "RHPOUT", NULL, "HP Out" },
{ "Line Out", "Switch", "HP Out" },
{ "LOUT", NULL, "Line Out" },
{ "ROUT", NULL, "Line Out" },
{ "BTL Out", "Switch", "Line Out" },
{ "BTLP", NULL, "BTL Out"},
{ "BTLN", NULL, "BTL Out"},
{ "PCM Playback", "Volume", "DAC" },
{ "Headphones Playback", "Volume", "PCM Playback" },
{ "SYSCLK", NULL, "DAC" },
};
static void jz4760_codec_codec_init_regs(struct snd_soc_component *codec)
{
struct jz_codec *jz_codec = snd_soc_component_get_drvdata(codec);
struct regmap *regmap = jz_codec->regmap;
/* Collect updates for later sending. */
regcache_cache_only(regmap, true);
/* default Amp output to PCM */
regmap_set_bits(regmap, JZ4760_CODEC_REG_CR1, REG_CR1_OUTSEL_MASK);
/* Disable stereo mic */
regmap_clear_bits(regmap, JZ4760_CODEC_REG_CR3,
BIT(REG_CR3_MICSTEREO_OFFSET));
/* Set mic 1 as default source for ADC */
regmap_clear_bits(regmap, JZ4760_CODEC_REG_CR3,
REG_CR3_ADC_INSEL_MASK);
/* ADC/DAC: serial + i2s */
regmap_set_bits(regmap, JZ4760_CODEC_REG_AICR,
REG_AICR_ADC_SERIAL | REG_AICR_ADC_I2S |
REG_AICR_DAC_SERIAL | REG_AICR_DAC_I2S);
/* The generated IRQ is a high level */
regmap_clear_bits(regmap, JZ4760_CODEC_REG_ICR, REG_ICR_INT_FORM_MASK);
regmap_update_bits(regmap, JZ4760_CODEC_REG_ICR, REG_ICR_ALL_MASK,
REG_ICR_JACK_MASK | REG_ICR_RUP_MASK |
REG_ICR_RDO_MASK | REG_ICR_GUP_MASK |
REG_ICR_GDO_MASK);
/* 12M oscillator */
regmap_clear_bits(regmap, JZ4760_CODEC_REG_CCR1, REG_CCR1_CRYSTAL_MASK);
/* 0: 16ohm/220uF, 1: 10kohm/1uF */
regmap_clear_bits(regmap, JZ4760_CODEC_REG_CR1, REG_CR1_HP_LOAD);
/* default to NOMAD */
regmap_set_bits(jz_codec->regmap, JZ4760_CODEC_REG_CR2,
REG_CR2_DAC_NOMAD);
/* disable automatic gain */
regmap_clear_bits(regmap, JZ4760_CODEC_REG_AGC1, REG_AGC1_EN);
/* Independent L/R DAC gain control */
regmap_clear_bits(regmap, JZ4760_CODEC_REG_GCR5,
REG_GCR_RL);
/* Send collected updates. */
regcache_cache_only(regmap, false);
regcache_sync(regmap);
}
static int jz4760_codec_codec_probe(struct snd_soc_component *codec)
{
struct jz_codec *jz_codec = snd_soc_component_get_drvdata(codec);
clk_prepare_enable(jz_codec->clk);
jz4760_codec_codec_init_regs(codec);
return 0;
}
static void jz4760_codec_codec_remove(struct snd_soc_component *codec)
{
struct jz_codec *jz_codec = snd_soc_component_get_drvdata(codec);
clk_disable_unprepare(jz_codec->clk);
}
static const struct snd_soc_component_driver jz4760_codec_soc_codec_dev = {
.probe = jz4760_codec_codec_probe,
.remove = jz4760_codec_codec_remove,
.set_bias_level = jz4760_codec_set_bias_level,
.controls = jz4760_codec_snd_controls,
.num_controls = ARRAY_SIZE(jz4760_codec_snd_controls),
.dapm_widgets = jz4760_codec_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(jz4760_codec_dapm_widgets),
.dapm_routes = jz4760_codec_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(jz4760_codec_dapm_routes),
.suspend_bias_off = 1,
.use_pmdown_time = 1,
};
static const unsigned int jz4760_codec_sample_rates[] = {
96000, 48000, 44100, 32000,
24000, 22050, 16000, 12000,
11025, 9600, 8000,
};
static int jz4760_codec_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct jz_codec *codec = snd_soc_component_get_drvdata(dai->component);
unsigned int rate, bit_width;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
bit_width = 0;
break;
case SNDRV_PCM_FORMAT_S18_3LE:
bit_width = 1;
break;
case SNDRV_PCM_FORMAT_S20_3LE:
bit_width = 2;
break;
case SNDRV_PCM_FORMAT_S24_3LE:
bit_width = 3;
break;
default:
return -EINVAL;
}
for (rate = 0; rate < ARRAY_SIZE(jz4760_codec_sample_rates); rate++) {
if (jz4760_codec_sample_rates[rate] == params_rate(params))
break;
}
if (rate == ARRAY_SIZE(jz4760_codec_sample_rates))
return -EINVAL;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
regmap_update_bits(codec->regmap, JZ4760_CODEC_REG_AICR,
REG_AICR_DAC_ADWL_MASK,
FIELD_PREP(REG_AICR_DAC_ADWL_MASK, bit_width));
regmap_update_bits(codec->regmap, JZ4760_CODEC_REG_CCR2,
REG_CCR2_DAC_FREQ_MASK,
FIELD_PREP(REG_CCR2_DAC_FREQ_MASK, rate));
} else {
regmap_update_bits(codec->regmap, JZ4760_CODEC_REG_AICR,
REG_AICR_ADC_ADWL_MASK,
FIELD_PREP(REG_AICR_ADC_ADWL_MASK, bit_width));
regmap_update_bits(codec->regmap, JZ4760_CODEC_REG_CCR2,
REG_CCR2_ADC_FREQ_MASK,
FIELD_PREP(REG_CCR2_ADC_FREQ_MASK, rate));
}
return 0;
}
static const struct snd_soc_dai_ops jz4760_codec_dai_ops = {
.startup = jz4760_codec_startup,
.shutdown = jz4760_codec_shutdown,
.hw_params = jz4760_codec_hw_params,
.trigger = jz4760_codec_pcm_trigger,
.mute_stream = jz4760_codec_mute_stream,
.no_capture_mute = 1,
};
#define JZ_CODEC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S18_3LE | \
SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_3LE)
static struct snd_soc_dai_driver jz4760_codec_dai = {
.name = "jz4760-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = JZ_CODEC_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = JZ_CODEC_FORMATS,
},
.ops = &jz4760_codec_dai_ops,
};
static bool jz4760_codec_volatile(struct device *dev, unsigned int reg)
{
return reg == JZ4760_CODEC_REG_SR || reg == JZ4760_CODEC_REG_IFR;
}
static bool jz4760_codec_writeable(struct device *dev, unsigned int reg)
{
switch (reg) {
case JZ4760_CODEC_REG_SR:
return false;
default:
return true;
}
}
static int jz4760_codec_io_wait(struct jz_codec *codec)
{
u32 reg;
return readl_poll_timeout(codec->base + ICDC_RGADW_OFFSET, reg,
!(reg & ICDC_RGADW_RGWR),
1000, 1 * USEC_PER_SEC);
}
static int jz4760_codec_reg_read(void *context, unsigned int reg,
unsigned int *val)
{
struct jz_codec *codec = context;
unsigned int i;
u32 tmp;
int ret;
ret = jz4760_codec_io_wait(codec);
if (ret)
return ret;
tmp = readl(codec->base + ICDC_RGADW_OFFSET);
tmp &= ~ICDC_RGADW_RGADDR_MASK;
tmp |= FIELD_PREP(ICDC_RGADW_RGADDR_MASK, reg);
writel(tmp, codec->base + ICDC_RGADW_OFFSET);
/* wait 6+ cycles */
for (i = 0; i < 6; i++)
*val = readl(codec->base + ICDC_RGDATA_OFFSET) &
ICDC_RGDATA_RGDOUT_MASK;
return 0;
}
static int jz4760_codec_reg_write(void *context, unsigned int reg,
unsigned int val)
{
struct jz_codec *codec = context;
int ret;
ret = jz4760_codec_io_wait(codec);
if (ret)
return ret;
writel(ICDC_RGADW_RGWR | FIELD_PREP(ICDC_RGADW_RGADDR_MASK, reg) | val,
codec->base + ICDC_RGADW_OFFSET);
ret = jz4760_codec_io_wait(codec);
if (ret)
return ret;
return 0;
}
static const u8 jz4760_codec_reg_defaults[] = {
0x00, 0xFC, 0x1B, 0x20, 0x00, 0x80, 0x00, 0x00,
0xFF, 0x1F, 0x3F, 0x00, 0x06, 0x06, 0x06, 0x06,
0x00, 0x00, 0x00, 0x00, 0x00, 0x34, 0x07, 0x44,
0x1F, 0x00, 0x00, 0x00
};
static struct regmap_config jz4760_codec_regmap_config = {
.reg_bits = 7,
.val_bits = 8,
.max_register = JZ4760_CODEC_REG_MIX2,
.volatile_reg = jz4760_codec_volatile,
.writeable_reg = jz4760_codec_writeable,
.reg_read = jz4760_codec_reg_read,
.reg_write = jz4760_codec_reg_write,
.reg_defaults_raw = jz4760_codec_reg_defaults,
.num_reg_defaults_raw = ARRAY_SIZE(jz4760_codec_reg_defaults),
.cache_type = REGCACHE_FLAT,
};
static int jz4760_codec_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct jz_codec *codec;
int ret;
codec = devm_kzalloc(dev, sizeof(*codec), GFP_KERNEL);
if (!codec)
return -ENOMEM;
codec->dev = dev;
codec->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(codec->base))
return PTR_ERR(codec->base);
codec->regmap = devm_regmap_init(dev, NULL, codec,
&jz4760_codec_regmap_config);
if (IS_ERR(codec->regmap))
return PTR_ERR(codec->regmap);
codec->clk = devm_clk_get(dev, "aic");
if (IS_ERR(codec->clk))
return PTR_ERR(codec->clk);
platform_set_drvdata(pdev, codec);
ret = devm_snd_soc_register_component(dev, &jz4760_codec_soc_codec_dev,
&jz4760_codec_dai, 1);
if (ret) {
dev_err(dev, "Failed to register codec: %d\n", ret);
return ret;
}
return 0;
}
static const struct of_device_id jz4760_codec_of_matches[] = {
{ .compatible = "ingenic,jz4760-codec", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, jz4760_codec_of_matches);
static struct platform_driver jz4760_codec_driver = {
.probe = jz4760_codec_probe,
.driver = {
.name = "jz4760-codec",
.of_match_table = jz4760_codec_of_matches,
},
};
module_platform_driver(jz4760_codec_driver);
MODULE_DESCRIPTION("JZ4760 SoC internal codec driver");
MODULE_AUTHOR("Christophe Branchereau <[email protected]>");
MODULE_AUTHOR("Paul Cercueil <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/jz4760.c |
// SPDX-License-Identifier: GPL-2.0
//
// rt1016.c -- RT1016 ALSA SoC audio amplifier driver
//
// Copyright 2020 Realtek Semiconductor Corp.
// Author: Oder Chiou <[email protected]>
//
#include <linux/fs.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/regmap.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/firmware.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "rl6231.h"
#include "rt1016.h"
static const struct reg_sequence rt1016_patch[] = {
{RT1016_VOL_CTRL_3, 0x8900},
{RT1016_ANA_CTRL_1, 0xa002},
{RT1016_ANA_CTRL_2, 0x0002},
{RT1016_CLOCK_4, 0x6700},
{RT1016_CLASSD_3, 0xdc55},
{RT1016_CLASSD_4, 0x376a},
{RT1016_CLASSD_5, 0x009f},
};
static const struct reg_default rt1016_reg[] = {
{0x00, 0x0000},
{0x01, 0x5400},
{0x02, 0x5506},
{0x03, 0xf800},
{0x04, 0x0000},
{0x05, 0xbfbf},
{0x06, 0x8900},
{0x07, 0xa002},
{0x08, 0x0000},
{0x09, 0x0000},
{0x0a, 0x0000},
{0x0c, 0x0000},
{0x0d, 0x0000},
{0x0e, 0x10ec},
{0x0f, 0x6595},
{0x11, 0x0002},
{0x1c, 0x0000},
{0x1d, 0x0000},
{0x1e, 0x0000},
{0x1f, 0xf000},
{0x20, 0x0000},
{0x21, 0x6000},
{0x22, 0x0000},
{0x23, 0x6700},
{0x24, 0x0000},
{0x25, 0x0000},
{0x26, 0x0000},
{0x40, 0x0018},
{0x60, 0x00a5},
{0x80, 0x0010},
{0x81, 0x0009},
{0x82, 0x0000},
{0x83, 0x0000},
{0xa0, 0x0700},
{0xc0, 0x0080},
{0xc1, 0x02a0},
{0xc2, 0x1400},
{0xc3, 0x0a4a},
{0xc4, 0x552a},
{0xc5, 0x087e},
{0xc6, 0x0020},
{0xc7, 0xa833},
{0xc8, 0x0433},
{0xc9, 0x8040},
{0xca, 0xdc55},
{0xcb, 0x376a},
{0xcc, 0x009f},
{0xcf, 0x0020},
};
static bool rt1016_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case RT1016_ANA_FLAG:
case RT1016_VERSION2_ID:
case RT1016_VERSION1_ID:
case RT1016_VENDER_ID:
case RT1016_DEVICE_ID:
case RT1016_TEST_SIGNAL:
case RT1016_SC_CTRL_1:
return true;
default:
return false;
}
}
static bool rt1016_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case RT1016_RESET:
case RT1016_PADS_CTRL_1:
case RT1016_PADS_CTRL_2:
case RT1016_I2C_CTRL:
case RT1016_VOL_CTRL_1:
case RT1016_VOL_CTRL_2:
case RT1016_VOL_CTRL_3:
case RT1016_ANA_CTRL_1:
case RT1016_MUX_SEL:
case RT1016_RX_I2S_CTRL:
case RT1016_ANA_FLAG:
case RT1016_VERSION2_ID:
case RT1016_VERSION1_ID:
case RT1016_VENDER_ID:
case RT1016_DEVICE_ID:
case RT1016_ANA_CTRL_2:
case RT1016_TEST_SIGNAL:
case RT1016_TEST_CTRL_1:
case RT1016_TEST_CTRL_2:
case RT1016_TEST_CTRL_3:
case RT1016_CLOCK_1:
case RT1016_CLOCK_2:
case RT1016_CLOCK_3:
case RT1016_CLOCK_4:
case RT1016_CLOCK_5:
case RT1016_CLOCK_6:
case RT1016_CLOCK_7:
case RT1016_I2S_CTRL:
case RT1016_DAC_CTRL_1:
case RT1016_SC_CTRL_1:
case RT1016_SC_CTRL_2:
case RT1016_SC_CTRL_3:
case RT1016_SC_CTRL_4:
case RT1016_SIL_DET:
case RT1016_SYS_CLK:
case RT1016_BIAS_CUR:
case RT1016_DAC_CTRL_2:
case RT1016_LDO_CTRL:
case RT1016_CLASSD_1:
case RT1016_PLL1:
case RT1016_PLL2:
case RT1016_PLL3:
case RT1016_CLASSD_2:
case RT1016_CLASSD_OUT:
case RT1016_CLASSD_3:
case RT1016_CLASSD_4:
case RT1016_CLASSD_5:
case RT1016_PWR_CTRL:
return true;
default:
return false;
}
}
static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9550, 50, 0);
static const struct snd_kcontrol_new rt1016_snd_controls[] = {
SOC_DOUBLE_TLV("DAC Playback Volume", RT1016_VOL_CTRL_2,
RT1016_L_VOL_SFT, RT1016_R_VOL_SFT, 191, 0, dac_vol_tlv),
SOC_DOUBLE("DAC Playback Switch", RT1016_VOL_CTRL_1,
RT1016_DA_MUTE_L_SFT, RT1016_DA_MUTE_R_SFT, 1, 1),
};
static int rt1016_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(source->dapm);
struct rt1016_priv *rt1016 = snd_soc_component_get_drvdata(component);
if (rt1016->sysclk_src == RT1016_SCLK_S_PLL)
return 1;
else
return 0;
}
/* Interface data select */
static const char * const rt1016_data_select[] = {
"L/R", "R/L", "L/L", "R/R"
};
static SOC_ENUM_SINGLE_DECL(rt1016_if_data_swap_enum,
RT1016_I2S_CTRL, RT1016_I2S_DATA_SWAP_SFT, rt1016_data_select);
static const struct snd_kcontrol_new rt1016_if_data_swap_mux =
SOC_DAPM_ENUM("Data Swap Mux", rt1016_if_data_swap_enum);
static const struct snd_soc_dapm_widget rt1016_dapm_widgets[] = {
SND_SOC_DAPM_MUX("Data Swap Mux", SND_SOC_NOPM, 0, 0,
&rt1016_if_data_swap_mux),
SND_SOC_DAPM_SUPPLY("DAC Filter", RT1016_CLOCK_3,
RT1016_PWR_DAC_FILTER_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAMOD", RT1016_CLOCK_3, RT1016_PWR_DACMOD_BIT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("FIFO", RT1016_CLOCK_3, RT1016_PWR_CLK_FIFO_BIT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("Pure DC", RT1016_CLOCK_3,
RT1016_PWR_CLK_PUREDC_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CLK Silence Det", RT1016_CLOCK_3,
RT1016_PWR_SIL_DET_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("RC 25M", RT1016_CLOCK_3, RT1016_PWR_RC_25M_BIT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("PLL1", RT1016_CLOCK_3, RT1016_PWR_PLL1_BIT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("ANA CTRL", RT1016_CLOCK_3, RT1016_PWR_ANA_CTRL_BIT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CLK SYS", RT1016_CLOCK_3, RT1016_PWR_CLK_SYS_BIT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY("LRCK Det", RT1016_CLOCK_4, RT1016_PWR_LRCK_DET_BIT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY("BCLK Det", RT1016_CLOCK_4, RT1016_PWR_BCLK_DET_BIT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CKGEN DAC", RT1016_DAC_CTRL_2,
RT1016_CKGEN_DAC_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("VCM SLOW", RT1016_CLASSD_1, RT1016_VCM_SLOW_BIT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("Silence Det", RT1016_SIL_DET,
RT1016_SIL_DET_EN_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PLL2", RT1016_PLL2, RT1016_PLL2_EN_BIT, 0, NULL,
0),
SND_SOC_DAPM_SUPPLY_S("BG1 BG2", 1, RT1016_PWR_CTRL,
RT1016_PWR_BG_1_2_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("MBIAS BG", 1, RT1016_PWR_CTRL,
RT1016_PWR_MBIAS_BG_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("PLL", 1, RT1016_PWR_CTRL, RT1016_PWR_PLL_BIT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY_S("BASIC", 1, RT1016_PWR_CTRL, RT1016_PWR_BASIC_BIT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("CLASS D", 1, RT1016_PWR_CTRL,
RT1016_PWR_CLSD_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("25M", 1, RT1016_PWR_CTRL, RT1016_PWR_25M_BIT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DACL", 1, RT1016_PWR_CTRL, RT1016_PWR_DACL_BIT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DACR", 1, RT1016_PWR_CTRL, RT1016_PWR_DACR_BIT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("LDO2", 1, RT1016_PWR_CTRL, RT1016_PWR_LDO2_BIT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("VREF", 1, RT1016_PWR_CTRL, RT1016_PWR_VREF_BIT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("MBIAS", 1, RT1016_PWR_CTRL, RT1016_PWR_MBIAS_BIT,
0, NULL, 0),
SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_OUTPUT("SPO"),
};
static const struct snd_soc_dapm_route rt1016_dapm_routes[] = {
{ "Data Swap Mux", "L/R", "AIFRX" },
{ "Data Swap Mux", "R/L", "AIFRX" },
{ "Data Swap Mux", "L/L", "AIFRX" },
{ "Data Swap Mux", "R/R", "AIFRX" },
{ "DAC", NULL, "DAC Filter" },
{ "DAC", NULL, "DAMOD" },
{ "DAC", NULL, "FIFO" },
{ "DAC", NULL, "Pure DC" },
{ "DAC", NULL, "Silence Det" },
{ "DAC", NULL, "ANA CTRL" },
{ "DAC", NULL, "CLK SYS" },
{ "DAC", NULL, "LRCK Det" },
{ "DAC", NULL, "BCLK Det" },
{ "DAC", NULL, "CKGEN DAC" },
{ "DAC", NULL, "VCM SLOW" },
{ "PLL", NULL, "PLL1" },
{ "PLL", NULL, "PLL2" },
{ "25M", NULL, "RC 25M" },
{ "Silence Det", NULL, "CLK Silence Det" },
{ "DAC", NULL, "Data Swap Mux" },
{ "DAC", NULL, "BG1 BG2" },
{ "DAC", NULL, "MBIAS BG" },
{ "DAC", NULL, "PLL", rt1016_is_sys_clk_from_pll},
{ "DAC", NULL, "BASIC" },
{ "DAC", NULL, "CLASS D" },
{ "DAC", NULL, "25M" },
{ "DAC", NULL, "DACL" },
{ "DAC", NULL, "DACR" },
{ "DAC", NULL, "LDO2" },
{ "DAC", NULL, "VREF" },
{ "DAC", NULL, "MBIAS" },
{ "SPO", NULL, "DAC" },
};
static int rt1016_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt1016_priv *rt1016 = snd_soc_component_get_drvdata(component);
int pre_div, bclk_ms, frame_size;
unsigned int val_len = 0;
rt1016->lrck = params_rate(params);
pre_div = rl6231_get_clk_info(rt1016->sysclk, rt1016->lrck);
if (pre_div < 0) {
dev_err(component->dev, "Unsupported clock rate\n");
return -EINVAL;
}
frame_size = snd_soc_params_to_frame_size(params);
if (frame_size < 0) {
dev_err(component->dev, "Unsupported frame size: %d\n",
frame_size);
return -EINVAL;
}
bclk_ms = frame_size > 32;
rt1016->bclk = rt1016->lrck * (32 << bclk_ms);
if (bclk_ms && rt1016->master)
snd_soc_component_update_bits(component, RT1016_I2S_CTRL,
RT1016_I2S_BCLK_MS_MASK, RT1016_I2S_BCLK_MS_64);
dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
rt1016->lrck, pre_div, dai->id);
switch (params_width(params)) {
case 16:
val_len = RT1016_I2S_DL_16;
break;
case 20:
val_len = RT1016_I2S_DL_20;
break;
case 24:
val_len = RT1016_I2S_DL_24;
break;
case 32:
val_len = RT1016_I2S_DL_32;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, RT1016_I2S_CTRL,
RT1016_I2S_DL_MASK, val_len);
snd_soc_component_update_bits(component, RT1016_CLOCK_2,
RT1016_FS_PD_MASK | RT1016_OSR_PD_MASK,
((pre_div + 3) << RT1016_FS_PD_SFT) |
(pre_div << RT1016_OSR_PD_SFT));
return 0;
}
static int rt1016_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct rt1016_priv *rt1016 = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
reg_val |= RT1016_I2S_MS_M;
rt1016->master = 1;
break;
case SND_SOC_DAIFMT_CBS_CFS:
reg_val |= RT1016_I2S_MS_S;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
reg_val |= RT1016_I2S_BCLK_POL_INV;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_LEFT_J:
reg_val |= RT1016_I2S_DF_LEFT;
break;
case SND_SOC_DAIFMT_DSP_A:
reg_val |= RT1016_I2S_DF_PCM_A;
break;
case SND_SOC_DAIFMT_DSP_B:
reg_val |= RT1016_I2S_DF_PCM_B;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, RT1016_I2S_CTRL,
RT1016_I2S_MS_MASK | RT1016_I2S_BCLK_POL_MASK |
RT1016_I2S_DF_MASK, reg_val);
return 0;
}
static int rt1016_set_component_sysclk(struct snd_soc_component *component,
int clk_id, int source, unsigned int freq, int dir)
{
struct rt1016_priv *rt1016 = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0;
if (freq == rt1016->sysclk && clk_id == rt1016->sysclk_src)
return 0;
switch (clk_id) {
case RT1016_SCLK_S_MCLK:
reg_val |= RT1016_CLK_SYS_SEL_MCLK;
break;
case RT1016_SCLK_S_PLL:
reg_val |= RT1016_CLK_SYS_SEL_PLL;
break;
default:
dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
return -EINVAL;
}
rt1016->sysclk = freq;
rt1016->sysclk_src = clk_id;
dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
freq, clk_id);
snd_soc_component_update_bits(component, RT1016_CLOCK_1,
RT1016_CLK_SYS_SEL_MASK, reg_val);
return 0;
}
static int rt1016_set_component_pll(struct snd_soc_component *component,
int pll_id, int source, unsigned int freq_in,
unsigned int freq_out)
{
struct rt1016_priv *rt1016 = snd_soc_component_get_drvdata(component);
struct rl6231_pll_code pll_code;
int ret;
if (!freq_in || !freq_out) {
dev_dbg(component->dev, "PLL disabled\n");
rt1016->pll_in = 0;
rt1016->pll_out = 0;
return 0;
}
if (source == rt1016->pll_src && freq_in == rt1016->pll_in &&
freq_out == rt1016->pll_out)
return 0;
switch (source) {
case RT1016_PLL_S_MCLK:
snd_soc_component_update_bits(component, RT1016_CLOCK_1,
RT1016_PLL_SEL_MASK, RT1016_PLL_SEL_MCLK);
break;
case RT1016_PLL_S_BCLK:
snd_soc_component_update_bits(component, RT1016_CLOCK_1,
RT1016_PLL_SEL_MASK, RT1016_PLL_SEL_BCLK);
break;
default:
dev_err(component->dev, "Unknown PLL Source %d\n", source);
return -EINVAL;
}
ret = rl6231_pll_calc(freq_in, freq_out * 4, &pll_code);
if (ret < 0) {
dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
return ret;
}
dev_dbg(component->dev, "mbypass=%d m=%d n=%d kbypass=%d k=%d\n",
pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
pll_code.n_code, pll_code.k_bp,
(pll_code.k_bp ? 0 : pll_code.k_code));
snd_soc_component_write(component, RT1016_PLL1,
((pll_code.m_bp ? 0 : pll_code.m_code) << RT1016_PLL_M_SFT) |
(pll_code.m_bp << RT1016_PLL_M_BP_SFT) |
pll_code.n_code);
snd_soc_component_write(component, RT1016_PLL2,
(pll_code.k_bp << RT1016_PLL_K_BP_SFT) |
(pll_code.k_bp ? 0 : pll_code.k_code));
rt1016->pll_in = freq_in;
rt1016->pll_out = freq_out;
rt1016->pll_src = source;
return 0;
}
static int rt1016_probe(struct snd_soc_component *component)
{
struct rt1016_priv *rt1016 =
snd_soc_component_get_drvdata(component);
rt1016->component = component;
return 0;
}
static void rt1016_remove(struct snd_soc_component *component)
{
struct rt1016_priv *rt1016 = snd_soc_component_get_drvdata(component);
regmap_write(rt1016->regmap, RT1016_RESET, 0);
}
#define RT1016_STEREO_RATES SNDRV_PCM_RATE_8000_48000
#define RT1016_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
static const struct snd_soc_dai_ops rt1016_aif_dai_ops = {
.hw_params = rt1016_hw_params,
.set_fmt = rt1016_set_dai_fmt,
};
static struct snd_soc_dai_driver rt1016_dai[] = {
{
.name = "rt1016-aif",
.id = 0,
.playback = {
.stream_name = "AIF Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT1016_STEREO_RATES,
.formats = RT1016_FORMATS,
},
.ops = &rt1016_aif_dai_ops,
}
};
#ifdef CONFIG_PM
static int rt1016_suspend(struct snd_soc_component *component)
{
struct rt1016_priv *rt1016 = snd_soc_component_get_drvdata(component);
regcache_cache_only(rt1016->regmap, true);
regcache_mark_dirty(rt1016->regmap);
return 0;
}
static int rt1016_resume(struct snd_soc_component *component)
{
struct rt1016_priv *rt1016 = snd_soc_component_get_drvdata(component);
regcache_cache_only(rt1016->regmap, false);
regcache_sync(rt1016->regmap);
return 0;
}
#else
#define rt1016_suspend NULL
#define rt1016_resume NULL
#endif
static const struct snd_soc_component_driver soc_component_dev_rt1016 = {
.probe = rt1016_probe,
.remove = rt1016_remove,
.suspend = rt1016_suspend,
.resume = rt1016_resume,
.controls = rt1016_snd_controls,
.num_controls = ARRAY_SIZE(rt1016_snd_controls),
.dapm_widgets = rt1016_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt1016_dapm_widgets),
.dapm_routes = rt1016_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(rt1016_dapm_routes),
.set_sysclk = rt1016_set_component_sysclk,
.set_pll = rt1016_set_component_pll,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config rt1016_regmap = {
.reg_bits = 8,
.val_bits = 16,
.max_register = RT1016_PWR_CTRL,
.volatile_reg = rt1016_volatile_register,
.readable_reg = rt1016_readable_register,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = rt1016_reg,
.num_reg_defaults = ARRAY_SIZE(rt1016_reg),
};
static const struct i2c_device_id rt1016_i2c_id[] = {
{ "rt1016", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, rt1016_i2c_id);
#if defined(CONFIG_OF)
static const struct of_device_id rt1016_of_match[] = {
{ .compatible = "realtek,rt1016", },
{},
};
MODULE_DEVICE_TABLE(of, rt1016_of_match);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id rt1016_acpi_match[] = {
{"10EC1016", 0,},
{},
};
MODULE_DEVICE_TABLE(acpi, rt1016_acpi_match);
#endif
static int rt1016_i2c_probe(struct i2c_client *i2c)
{
struct rt1016_priv *rt1016;
int ret;
unsigned int val;
rt1016 = devm_kzalloc(&i2c->dev, sizeof(struct rt1016_priv),
GFP_KERNEL);
if (rt1016 == NULL)
return -ENOMEM;
i2c_set_clientdata(i2c, rt1016);
rt1016->regmap = devm_regmap_init_i2c(i2c, &rt1016_regmap);
if (IS_ERR(rt1016->regmap)) {
ret = PTR_ERR(rt1016->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
regmap_read(rt1016->regmap, RT1016_DEVICE_ID, &val);
if (val != RT1016_DEVICE_ID_VAL) {
dev_err(&i2c->dev,
"Device with ID register %x is not rt1016\n", val);
return -ENODEV;
}
regmap_write(rt1016->regmap, RT1016_RESET, 0);
ret = regmap_register_patch(rt1016->regmap, rt1016_patch,
ARRAY_SIZE(rt1016_patch));
if (ret != 0)
dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
return devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_rt1016,
rt1016_dai, ARRAY_SIZE(rt1016_dai));
}
static void rt1016_i2c_shutdown(struct i2c_client *client)
{
struct rt1016_priv *rt1016 = i2c_get_clientdata(client);
regmap_write(rt1016->regmap, RT1016_RESET, 0);
}
static struct i2c_driver rt1016_i2c_driver = {
.driver = {
.name = "rt1016",
.of_match_table = of_match_ptr(rt1016_of_match),
.acpi_match_table = ACPI_PTR(rt1016_acpi_match),
},
.probe = rt1016_i2c_probe,
.shutdown = rt1016_i2c_shutdown,
.id_table = rt1016_i2c_id,
};
module_i2c_driver(rt1016_i2c_driver);
MODULE_DESCRIPTION("ASoC RT1016 driver");
MODULE_AUTHOR("Oder Chiou <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/rt1016.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8741.c -- WM8741 ALSA SoC Audio driver
*
* Copyright 2010-1 Wolfson Microelectronics plc
*
* Author: Ian Lartey <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/spi/spi.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <linux/of_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "wm8741.h"
#define WM8741_NUM_SUPPLIES 2
static const char *wm8741_supply_names[WM8741_NUM_SUPPLIES] = {
"AVDD",
"DVDD",
};
/* codec private data */
struct wm8741_priv {
struct wm8741_platform_data pdata;
struct regmap *regmap;
struct regulator_bulk_data supplies[WM8741_NUM_SUPPLIES];
unsigned int sysclk;
const struct snd_pcm_hw_constraint_list *sysclk_constraints;
};
static const struct reg_default wm8741_reg_defaults[] = {
{ 0, 0x0000 }, /* R0 - DACLLSB Attenuation */
{ 1, 0x0000 }, /* R1 - DACLMSB Attenuation */
{ 2, 0x0000 }, /* R2 - DACRLSB Attenuation */
{ 3, 0x0000 }, /* R3 - DACRMSB Attenuation */
{ 4, 0x0000 }, /* R4 - Volume Control */
{ 5, 0x000A }, /* R5 - Format Control */
{ 6, 0x0000 }, /* R6 - Filter Control */
{ 7, 0x0000 }, /* R7 - Mode Control 1 */
{ 8, 0x0002 }, /* R8 - Mode Control 2 */
{ 32, 0x0002 }, /* R32 - ADDITONAL_CONTROL_1 */
};
static int wm8741_reset(struct snd_soc_component *component)
{
return snd_soc_component_write(component, WM8741_RESET, 0);
}
static const DECLARE_TLV_DB_SCALE(dac_tlv_fine, -12700, 13, 0);
static const DECLARE_TLV_DB_SCALE(dac_tlv, -12700, 400, 0);
static const struct snd_kcontrol_new wm8741_snd_controls_stereo[] = {
SOC_DOUBLE_R_TLV("Fine Playback Volume", WM8741_DACLLSB_ATTENUATION,
WM8741_DACRLSB_ATTENUATION, 1, 255, 1, dac_tlv_fine),
SOC_DOUBLE_R_TLV("Playback Volume", WM8741_DACLMSB_ATTENUATION,
WM8741_DACRMSB_ATTENUATION, 0, 511, 1, dac_tlv),
};
static const struct snd_kcontrol_new wm8741_snd_controls_mono_left[] = {
SOC_SINGLE_TLV("Fine Playback Volume", WM8741_DACLLSB_ATTENUATION,
1, 255, 1, dac_tlv_fine),
SOC_SINGLE_TLV("Playback Volume", WM8741_DACLMSB_ATTENUATION,
0, 511, 1, dac_tlv),
};
static const struct snd_kcontrol_new wm8741_snd_controls_mono_right[] = {
SOC_SINGLE_TLV("Fine Playback Volume", WM8741_DACRLSB_ATTENUATION,
1, 255, 1, dac_tlv_fine),
SOC_SINGLE_TLV("Playback Volume", WM8741_DACRMSB_ATTENUATION,
0, 511, 1, dac_tlv),
};
static const struct snd_soc_dapm_widget wm8741_dapm_widgets[] = {
SND_SOC_DAPM_DAC("DACL", "Playback", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DACR", "Playback", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_OUTPUT("VOUTLP"),
SND_SOC_DAPM_OUTPUT("VOUTLN"),
SND_SOC_DAPM_OUTPUT("VOUTRP"),
SND_SOC_DAPM_OUTPUT("VOUTRN"),
};
static const struct snd_soc_dapm_route wm8741_dapm_routes[] = {
{ "VOUTLP", NULL, "DACL" },
{ "VOUTLN", NULL, "DACL" },
{ "VOUTRP", NULL, "DACR" },
{ "VOUTRN", NULL, "DACR" },
};
static const unsigned int rates_11289[] = {
44100, 88200,
};
static const struct snd_pcm_hw_constraint_list constraints_11289 = {
.count = ARRAY_SIZE(rates_11289),
.list = rates_11289,
};
static const unsigned int rates_12288[] = {
32000, 48000, 96000,
};
static const struct snd_pcm_hw_constraint_list constraints_12288 = {
.count = ARRAY_SIZE(rates_12288),
.list = rates_12288,
};
static const unsigned int rates_16384[] = {
32000,
};
static const struct snd_pcm_hw_constraint_list constraints_16384 = {
.count = ARRAY_SIZE(rates_16384),
.list = rates_16384,
};
static const unsigned int rates_16934[] = {
44100, 88200,
};
static const struct snd_pcm_hw_constraint_list constraints_16934 = {
.count = ARRAY_SIZE(rates_16934),
.list = rates_16934,
};
static const unsigned int rates_18432[] = {
48000, 96000,
};
static const struct snd_pcm_hw_constraint_list constraints_18432 = {
.count = ARRAY_SIZE(rates_18432),
.list = rates_18432,
};
static const unsigned int rates_22579[] = {
44100, 88200, 176400
};
static const struct snd_pcm_hw_constraint_list constraints_22579 = {
.count = ARRAY_SIZE(rates_22579),
.list = rates_22579,
};
static const unsigned int rates_24576[] = {
32000, 48000, 96000, 192000
};
static const struct snd_pcm_hw_constraint_list constraints_24576 = {
.count = ARRAY_SIZE(rates_24576),
.list = rates_24576,
};
static const unsigned int rates_36864[] = {
48000, 96000, 192000
};
static const struct snd_pcm_hw_constraint_list constraints_36864 = {
.count = ARRAY_SIZE(rates_36864),
.list = rates_36864,
};
static int wm8741_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm8741_priv *wm8741 = snd_soc_component_get_drvdata(component);
if (wm8741->sysclk)
snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
wm8741->sysclk_constraints);
return 0;
}
static int wm8741_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm8741_priv *wm8741 = snd_soc_component_get_drvdata(component);
unsigned int iface, mode;
int i;
/* The set of sample rates that can be supported depends on the
* MCLK supplied to the CODEC - enforce this.
*/
if (!wm8741->sysclk) {
dev_err(component->dev,
"No MCLK configured, call set_sysclk() on init or in hw_params\n");
return -EINVAL;
}
/* Find a supported LRCLK rate */
for (i = 0; i < wm8741->sysclk_constraints->count; i++) {
if (wm8741->sysclk_constraints->list[i] == params_rate(params))
break;
}
if (i == wm8741->sysclk_constraints->count) {
dev_err(component->dev, "LRCLK %d unsupported with MCLK %d\n",
params_rate(params), wm8741->sysclk);
return -EINVAL;
}
/* bit size */
switch (params_width(params)) {
case 16:
iface = 0x0;
break;
case 20:
iface = 0x1;
break;
case 24:
iface = 0x2;
break;
case 32:
iface = 0x3;
break;
default:
dev_dbg(component->dev, "wm8741_hw_params: Unsupported bit size param = %d",
params_width(params));
return -EINVAL;
}
/* oversampling rate */
if (params_rate(params) > 96000)
mode = 0x40;
else if (params_rate(params) > 48000)
mode = 0x20;
else
mode = 0x00;
dev_dbg(component->dev, "wm8741_hw_params: bit size param = %d, rate param = %d",
params_width(params), params_rate(params));
snd_soc_component_update_bits(component, WM8741_FORMAT_CONTROL, WM8741_IWL_MASK,
iface);
snd_soc_component_update_bits(component, WM8741_MODE_CONTROL_1, WM8741_OSR_MASK,
mode);
return 0;
}
static int wm8741_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct wm8741_priv *wm8741 = snd_soc_component_get_drvdata(component);
dev_dbg(component->dev, "wm8741_set_dai_sysclk info: freq=%dHz\n", freq);
switch (freq) {
case 0:
wm8741->sysclk_constraints = NULL;
break;
case 11289600:
wm8741->sysclk_constraints = &constraints_11289;
break;
case 12288000:
wm8741->sysclk_constraints = &constraints_12288;
break;
case 16384000:
wm8741->sysclk_constraints = &constraints_16384;
break;
case 16934400:
wm8741->sysclk_constraints = &constraints_16934;
break;
case 18432000:
wm8741->sysclk_constraints = &constraints_18432;
break;
case 22579200:
case 33868800:
wm8741->sysclk_constraints = &constraints_22579;
break;
case 24576000:
wm8741->sysclk_constraints = &constraints_24576;
break;
case 36864000:
wm8741->sysclk_constraints = &constraints_36864;
break;
default:
return -EINVAL;
}
wm8741->sysclk = freq;
return 0;
}
static int wm8741_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
unsigned int iface;
/* check master/slave audio interface */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface = 0x08;
break;
case SND_SOC_DAIFMT_RIGHT_J:
iface = 0x00;
break;
case SND_SOC_DAIFMT_LEFT_J:
iface = 0x04;
break;
case SND_SOC_DAIFMT_DSP_A:
iface = 0x0C;
break;
case SND_SOC_DAIFMT_DSP_B:
iface = 0x1C;
break;
default:
return -EINVAL;
}
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_NB_IF:
iface |= 0x10;
break;
case SND_SOC_DAIFMT_IB_NF:
iface |= 0x20;
break;
case SND_SOC_DAIFMT_IB_IF:
iface |= 0x30;
break;
default:
return -EINVAL;
}
dev_dbg(component->dev, "wm8741_set_dai_fmt: Format=%x, Clock Inv=%x\n",
fmt & SND_SOC_DAIFMT_FORMAT_MASK,
((fmt & SND_SOC_DAIFMT_INV_MASK)));
snd_soc_component_update_bits(component, WM8741_FORMAT_CONTROL,
WM8741_BCP_MASK | WM8741_LRP_MASK | WM8741_FMT_MASK,
iface);
return 0;
}
static int wm8741_mute(struct snd_soc_dai *codec_dai, int mute, int direction)
{
struct snd_soc_component *component = codec_dai->component;
snd_soc_component_update_bits(component, WM8741_VOLUME_CONTROL,
WM8741_SOFT_MASK, !!mute << WM8741_SOFT_SHIFT);
return 0;
}
#define WM8741_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | \
SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | \
SNDRV_PCM_RATE_192000)
#define WM8741_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops wm8741_dai_ops = {
.startup = wm8741_startup,
.hw_params = wm8741_hw_params,
.set_sysclk = wm8741_set_dai_sysclk,
.set_fmt = wm8741_set_dai_fmt,
.mute_stream = wm8741_mute,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver wm8741_dai = {
.name = "wm8741",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = WM8741_RATES,
.formats = WM8741_FORMATS,
},
.ops = &wm8741_dai_ops,
};
#ifdef CONFIG_PM
static int wm8741_resume(struct snd_soc_component *component)
{
snd_soc_component_cache_sync(component);
return 0;
}
#else
#define wm8741_resume NULL
#endif
static int wm8741_configure(struct snd_soc_component *component)
{
struct wm8741_priv *wm8741 = snd_soc_component_get_drvdata(component);
/* Configure differential mode */
switch (wm8741->pdata.diff_mode) {
case WM8741_DIFF_MODE_STEREO:
case WM8741_DIFF_MODE_STEREO_REVERSED:
case WM8741_DIFF_MODE_MONO_LEFT:
case WM8741_DIFF_MODE_MONO_RIGHT:
snd_soc_component_update_bits(component, WM8741_MODE_CONTROL_2,
WM8741_DIFF_MASK,
wm8741->pdata.diff_mode << WM8741_DIFF_SHIFT);
break;
default:
return -EINVAL;
}
/* Change some default settings - latch VU */
snd_soc_component_update_bits(component, WM8741_DACLLSB_ATTENUATION,
WM8741_UPDATELL, WM8741_UPDATELL);
snd_soc_component_update_bits(component, WM8741_DACLMSB_ATTENUATION,
WM8741_UPDATELM, WM8741_UPDATELM);
snd_soc_component_update_bits(component, WM8741_DACRLSB_ATTENUATION,
WM8741_UPDATERL, WM8741_UPDATERL);
snd_soc_component_update_bits(component, WM8741_DACRMSB_ATTENUATION,
WM8741_UPDATERM, WM8741_UPDATERM);
return 0;
}
static int wm8741_add_controls(struct snd_soc_component *component)
{
struct wm8741_priv *wm8741 = snd_soc_component_get_drvdata(component);
switch (wm8741->pdata.diff_mode) {
case WM8741_DIFF_MODE_STEREO:
case WM8741_DIFF_MODE_STEREO_REVERSED:
snd_soc_add_component_controls(component,
wm8741_snd_controls_stereo,
ARRAY_SIZE(wm8741_snd_controls_stereo));
break;
case WM8741_DIFF_MODE_MONO_LEFT:
snd_soc_add_component_controls(component,
wm8741_snd_controls_mono_left,
ARRAY_SIZE(wm8741_snd_controls_mono_left));
break;
case WM8741_DIFF_MODE_MONO_RIGHT:
snd_soc_add_component_controls(component,
wm8741_snd_controls_mono_right,
ARRAY_SIZE(wm8741_snd_controls_mono_right));
break;
default:
return -EINVAL;
}
return 0;
}
static int wm8741_probe(struct snd_soc_component *component)
{
struct wm8741_priv *wm8741 = snd_soc_component_get_drvdata(component);
int ret = 0;
ret = regulator_bulk_enable(ARRAY_SIZE(wm8741->supplies),
wm8741->supplies);
if (ret != 0) {
dev_err(component->dev, "Failed to enable supplies: %d\n", ret);
goto err_get;
}
ret = wm8741_reset(component);
if (ret < 0) {
dev_err(component->dev, "Failed to issue reset\n");
goto err_enable;
}
ret = wm8741_configure(component);
if (ret < 0) {
dev_err(component->dev, "Failed to change default settings\n");
goto err_enable;
}
ret = wm8741_add_controls(component);
if (ret < 0) {
dev_err(component->dev, "Failed to add controls\n");
goto err_enable;
}
dev_dbg(component->dev, "Successful registration\n");
return ret;
err_enable:
regulator_bulk_disable(ARRAY_SIZE(wm8741->supplies), wm8741->supplies);
err_get:
return ret;
}
static void wm8741_remove(struct snd_soc_component *component)
{
struct wm8741_priv *wm8741 = snd_soc_component_get_drvdata(component);
regulator_bulk_disable(ARRAY_SIZE(wm8741->supplies), wm8741->supplies);
}
static const struct snd_soc_component_driver soc_component_dev_wm8741 = {
.probe = wm8741_probe,
.remove = wm8741_remove,
.resume = wm8741_resume,
.dapm_widgets = wm8741_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8741_dapm_widgets),
.dapm_routes = wm8741_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(wm8741_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct of_device_id wm8741_of_match[] = {
{ .compatible = "wlf,wm8741", },
{ }
};
MODULE_DEVICE_TABLE(of, wm8741_of_match);
static const struct regmap_config wm8741_regmap = {
.reg_bits = 7,
.val_bits = 9,
.max_register = WM8741_MAX_REGISTER,
.reg_defaults = wm8741_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8741_reg_defaults),
.cache_type = REGCACHE_MAPLE,
};
static int wm8741_set_pdata(struct device *dev, struct wm8741_priv *wm8741)
{
const struct wm8741_platform_data *pdata = dev_get_platdata(dev);
u32 diff_mode;
if (dev->of_node) {
if (of_property_read_u32(dev->of_node, "diff-mode", &diff_mode)
>= 0)
wm8741->pdata.diff_mode = diff_mode;
} else {
if (pdata != NULL)
memcpy(&wm8741->pdata, pdata, sizeof(wm8741->pdata));
}
return 0;
}
#if IS_ENABLED(CONFIG_I2C)
static int wm8741_i2c_probe(struct i2c_client *i2c)
{
struct wm8741_priv *wm8741;
int ret, i;
wm8741 = devm_kzalloc(&i2c->dev, sizeof(struct wm8741_priv),
GFP_KERNEL);
if (wm8741 == NULL)
return -ENOMEM;
for (i = 0; i < ARRAY_SIZE(wm8741->supplies); i++)
wm8741->supplies[i].supply = wm8741_supply_names[i];
ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8741->supplies),
wm8741->supplies);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
return ret;
}
wm8741->regmap = devm_regmap_init_i2c(i2c, &wm8741_regmap);
if (IS_ERR(wm8741->regmap)) {
ret = PTR_ERR(wm8741->regmap);
dev_err(&i2c->dev, "Failed to init regmap: %d\n", ret);
return ret;
}
ret = wm8741_set_pdata(&i2c->dev, wm8741);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to set pdata: %d\n", ret);
return ret;
}
i2c_set_clientdata(i2c, wm8741);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_wm8741, &wm8741_dai, 1);
return ret;
}
static const struct i2c_device_id wm8741_i2c_id[] = {
{ "wm8741", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8741_i2c_id);
static struct i2c_driver wm8741_i2c_driver = {
.driver = {
.name = "wm8741",
.of_match_table = wm8741_of_match,
},
.probe = wm8741_i2c_probe,
.id_table = wm8741_i2c_id,
};
#endif
#if defined(CONFIG_SPI_MASTER)
static int wm8741_spi_probe(struct spi_device *spi)
{
struct wm8741_priv *wm8741;
int ret, i;
wm8741 = devm_kzalloc(&spi->dev, sizeof(struct wm8741_priv),
GFP_KERNEL);
if (wm8741 == NULL)
return -ENOMEM;
for (i = 0; i < ARRAY_SIZE(wm8741->supplies); i++)
wm8741->supplies[i].supply = wm8741_supply_names[i];
ret = devm_regulator_bulk_get(&spi->dev, ARRAY_SIZE(wm8741->supplies),
wm8741->supplies);
if (ret != 0) {
dev_err(&spi->dev, "Failed to request supplies: %d\n", ret);
return ret;
}
wm8741->regmap = devm_regmap_init_spi(spi, &wm8741_regmap);
if (IS_ERR(wm8741->regmap)) {
ret = PTR_ERR(wm8741->regmap);
dev_err(&spi->dev, "Failed to init regmap: %d\n", ret);
return ret;
}
ret = wm8741_set_pdata(&spi->dev, wm8741);
if (ret != 0) {
dev_err(&spi->dev, "Failed to set pdata: %d\n", ret);
return ret;
}
spi_set_drvdata(spi, wm8741);
ret = devm_snd_soc_register_component(&spi->dev,
&soc_component_dev_wm8741, &wm8741_dai, 1);
return ret;
}
static struct spi_driver wm8741_spi_driver = {
.driver = {
.name = "wm8741",
.of_match_table = wm8741_of_match,
},
.probe = wm8741_spi_probe,
};
#endif /* CONFIG_SPI_MASTER */
static int __init wm8741_modinit(void)
{
int ret = 0;
#if IS_ENABLED(CONFIG_I2C)
ret = i2c_add_driver(&wm8741_i2c_driver);
if (ret != 0)
pr_err("Failed to register WM8741 I2C driver: %d\n", ret);
#endif
#if defined(CONFIG_SPI_MASTER)
ret = spi_register_driver(&wm8741_spi_driver);
if (ret != 0) {
printk(KERN_ERR "Failed to register wm8741 SPI driver: %d\n",
ret);
}
#endif
return ret;
}
module_init(wm8741_modinit);
static void __exit wm8741_exit(void)
{
#if defined(CONFIG_SPI_MASTER)
spi_unregister_driver(&wm8741_spi_driver);
#endif
#if IS_ENABLED(CONFIG_I2C)
i2c_del_driver(&wm8741_i2c_driver);
#endif
}
module_exit(wm8741_exit);
MODULE_DESCRIPTION("ASoC WM8741 driver");
MODULE_AUTHOR("Ian Lartey <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8741.c |
/* SPDX-License-Identifier: GPL-2.0
*
* ALSA SoC TLV320AIC3x codec driver SPI interface
*
* Author: Arun KS, <[email protected]>
* Copyright: (C) 2008 Mistral Solutions Pvt Ltd.,
*
* Based on sound/soc/codecs/wm8731.c by Richard Purdie
*
*/
#include <linux/spi/spi.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include "tlv320aic3x.h"
static int aic3x_spi_probe(struct spi_device *spi)
{
struct regmap *regmap;
struct regmap_config config;
const struct spi_device_id *id = spi_get_device_id(spi);
config = aic3x_regmap;
config.reg_bits = 7;
config.pad_bits = 1;
config.val_bits = 8;
config.read_flag_mask = 0x01;
dev_dbg(&spi->dev, "probing tlv320aic3x spi device\n");
regmap = devm_regmap_init_spi(spi, &config);
return aic3x_probe(&spi->dev, regmap, id->driver_data);
}
static void aic3x_spi_remove(struct spi_device *spi)
{
aic3x_remove(&spi->dev);
}
static const struct spi_device_id aic3x_spi_id[] = {
{ "tlv320aic3x", AIC3X_MODEL_3X },
{ "tlv320aic33", AIC3X_MODEL_33 },
{ "tlv320aic3007", AIC3X_MODEL_3007 },
{ "tlv320aic3104", AIC3X_MODEL_3104 },
{ "tlv320aic3106", AIC3X_MODEL_3106 },
{ }
};
MODULE_DEVICE_TABLE(spi, aic3x_spi_id);
static const struct of_device_id aic3x_of_id[] = {
{ .compatible = "ti,tlv320aic3x", },
{ .compatible = "ti,tlv320aic33" },
{ .compatible = "ti,tlv320aic3007" },
{ .compatible = "ti,tlv320aic3104" },
{ .compatible = "ti,tlv320aic3106" },
{},
};
MODULE_DEVICE_TABLE(of, aic3x_of_id);
static struct spi_driver aic3x_spi_driver = {
.driver = {
.name = "tlv320aic3x",
.owner = THIS_MODULE,
.of_match_table = aic3x_of_id,
},
.probe = aic3x_spi_probe,
.remove = aic3x_spi_remove,
.id_table = aic3x_spi_id,
};
module_spi_driver(aic3x_spi_driver);
MODULE_DESCRIPTION("ASoC TLV320AIC3x codec driver SPI");
MODULE_AUTHOR("Arun KS <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/tlv320aic3x-spi.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ALSA SoC Texas Instruments TPA6130A2 headset stereo amplifier driver
*
* Copyright (C) Nokia Corporation
*
* Author: Peter Ujfalusi <[email protected]>
*/
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/device.h>
#include <linux/i2c.h>
#include <linux/gpio.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <sound/tpa6130a2-plat.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/regmap.h>
#include "tpa6130a2.h"
enum tpa_model {
TPA6130A2,
TPA6140A2,
};
/* This struct is used to save the context */
struct tpa6130a2_data {
struct device *dev;
struct regmap *regmap;
struct regulator *supply;
int power_gpio;
enum tpa_model id;
};
static int tpa6130a2_power(struct tpa6130a2_data *data, bool enable)
{
int ret = 0, ret2;
if (enable) {
ret = regulator_enable(data->supply);
if (ret != 0) {
dev_err(data->dev,
"Failed to enable supply: %d\n", ret);
return ret;
}
/* Power on */
if (data->power_gpio >= 0)
gpio_set_value(data->power_gpio, 1);
/* Sync registers */
regcache_cache_only(data->regmap, false);
ret = regcache_sync(data->regmap);
if (ret != 0) {
dev_err(data->dev,
"Failed to sync registers: %d\n", ret);
regcache_cache_only(data->regmap, true);
if (data->power_gpio >= 0)
gpio_set_value(data->power_gpio, 0);
ret2 = regulator_disable(data->supply);
if (ret2 != 0)
dev_err(data->dev,
"Failed to disable supply: %d\n", ret2);
return ret;
}
} else {
/* Powered off device does not retain registers. While device
* is off, any register updates (i.e. volume changes) should
* happen in cache only.
*/
regcache_mark_dirty(data->regmap);
regcache_cache_only(data->regmap, true);
/* Power off */
if (data->power_gpio >= 0)
gpio_set_value(data->power_gpio, 0);
ret = regulator_disable(data->supply);
if (ret != 0) {
dev_err(data->dev,
"Failed to disable supply: %d\n", ret);
return ret;
}
}
return ret;
}
static int tpa6130a2_power_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kctrl, int event)
{
struct snd_soc_component *c = snd_soc_dapm_to_component(w->dapm);
struct tpa6130a2_data *data = snd_soc_component_get_drvdata(c);
if (SND_SOC_DAPM_EVENT_ON(event)) {
/* Before widget power up: turn chip on, sync registers */
return tpa6130a2_power(data, true);
} else {
/* After widget power down: turn chip off */
return tpa6130a2_power(data, false);
}
}
/*
* TPA6130 volume. From -59.5 to 4 dB with increasing step size when going
* down in gain.
*/
static const DECLARE_TLV_DB_RANGE(tpa6130_tlv,
0, 1, TLV_DB_SCALE_ITEM(-5950, 600, 0),
2, 3, TLV_DB_SCALE_ITEM(-5000, 250, 0),
4, 5, TLV_DB_SCALE_ITEM(-4550, 160, 0),
6, 7, TLV_DB_SCALE_ITEM(-4140, 190, 0),
8, 9, TLV_DB_SCALE_ITEM(-3650, 120, 0),
10, 11, TLV_DB_SCALE_ITEM(-3330, 160, 0),
12, 13, TLV_DB_SCALE_ITEM(-3040, 180, 0),
14, 20, TLV_DB_SCALE_ITEM(-2710, 110, 0),
21, 37, TLV_DB_SCALE_ITEM(-1960, 74, 0),
38, 63, TLV_DB_SCALE_ITEM(-720, 45, 0)
);
static const struct snd_kcontrol_new tpa6130a2_controls[] = {
SOC_SINGLE_TLV("Headphone Playback Volume",
TPA6130A2_REG_VOL_MUTE, 0, 0x3f, 0,
tpa6130_tlv),
};
static const DECLARE_TLV_DB_RANGE(tpa6140_tlv,
0, 8, TLV_DB_SCALE_ITEM(-5900, 400, 0),
9, 16, TLV_DB_SCALE_ITEM(-2500, 200, 0),
17, 31, TLV_DB_SCALE_ITEM(-1000, 100, 0)
);
static const struct snd_kcontrol_new tpa6140a2_controls[] = {
SOC_SINGLE_TLV("Headphone Playback Volume",
TPA6130A2_REG_VOL_MUTE, 1, 0x1f, 0,
tpa6140_tlv),
};
static int tpa6130a2_component_probe(struct snd_soc_component *component)
{
struct tpa6130a2_data *data = snd_soc_component_get_drvdata(component);
if (data->id == TPA6140A2)
return snd_soc_add_component_controls(component,
tpa6140a2_controls, ARRAY_SIZE(tpa6140a2_controls));
else
return snd_soc_add_component_controls(component,
tpa6130a2_controls, ARRAY_SIZE(tpa6130a2_controls));
}
static const struct snd_soc_dapm_widget tpa6130a2_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("LEFTIN"),
SND_SOC_DAPM_INPUT("RIGHTIN"),
SND_SOC_DAPM_OUTPUT("HPLEFT"),
SND_SOC_DAPM_OUTPUT("HPRIGHT"),
SND_SOC_DAPM_PGA("Left Mute", TPA6130A2_REG_VOL_MUTE,
TPA6130A2_HP_EN_L_SHIFT, 1, NULL, 0),
SND_SOC_DAPM_PGA("Right Mute", TPA6130A2_REG_VOL_MUTE,
TPA6130A2_HP_EN_R_SHIFT, 1, NULL, 0),
SND_SOC_DAPM_PGA("Left PGA", TPA6130A2_REG_CONTROL,
TPA6130A2_HP_EN_L_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right PGA", TPA6130A2_REG_CONTROL,
TPA6130A2_HP_EN_R_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Power", TPA6130A2_REG_CONTROL,
TPA6130A2_SWS_SHIFT, 1, tpa6130a2_power_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
};
static const struct snd_soc_dapm_route tpa6130a2_dapm_routes[] = {
{ "Left PGA", NULL, "LEFTIN" },
{ "Right PGA", NULL, "RIGHTIN" },
{ "Left Mute", NULL, "Left PGA" },
{ "Right Mute", NULL, "Right PGA" },
{ "HPLEFT", NULL, "Left Mute" },
{ "HPRIGHT", NULL, "Right Mute" },
{ "Left PGA", NULL, "Power" },
{ "Right PGA", NULL, "Power" },
};
static const struct snd_soc_component_driver tpa6130a2_component_driver = {
.name = "tpa6130a2",
.probe = tpa6130a2_component_probe,
.dapm_widgets = tpa6130a2_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(tpa6130a2_dapm_widgets),
.dapm_routes = tpa6130a2_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(tpa6130a2_dapm_routes),
};
static const struct reg_default tpa6130a2_reg_defaults[] = {
{ TPA6130A2_REG_CONTROL, TPA6130A2_SWS },
{ TPA6130A2_REG_VOL_MUTE, TPA6130A2_MUTE_R | TPA6130A2_MUTE_L },
};
static const struct regmap_config tpa6130a2_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = TPA6130A2_REG_VERSION,
.reg_defaults = tpa6130a2_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tpa6130a2_reg_defaults),
.cache_type = REGCACHE_RBTREE,
};
static const struct i2c_device_id tpa6130a2_id[] = {
{ "tpa6130a2", TPA6130A2 },
{ "tpa6140a2", TPA6140A2 },
{ }
};
MODULE_DEVICE_TABLE(i2c, tpa6130a2_id);
static int tpa6130a2_probe(struct i2c_client *client)
{
struct device *dev;
struct tpa6130a2_data *data;
struct tpa6130a2_platform_data *pdata = client->dev.platform_data;
struct device_node *np = client->dev.of_node;
const struct i2c_device_id *id;
const char *regulator;
unsigned int version;
int ret;
dev = &client->dev;
data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->dev = dev;
data->regmap = devm_regmap_init_i2c(client, &tpa6130a2_regmap_config);
if (IS_ERR(data->regmap))
return PTR_ERR(data->regmap);
if (pdata) {
data->power_gpio = pdata->power_gpio;
} else if (np) {
data->power_gpio = of_get_named_gpio(np, "power-gpio", 0);
} else {
dev_err(dev, "Platform data not set\n");
dump_stack();
return -ENODEV;
}
i2c_set_clientdata(client, data);
id = i2c_match_id(tpa6130a2_id, client);
data->id = id->driver_data;
if (data->power_gpio >= 0) {
ret = devm_gpio_request(dev, data->power_gpio,
"tpa6130a2 enable");
if (ret < 0) {
dev_err(dev, "Failed to request power GPIO (%d)\n",
data->power_gpio);
return ret;
}
gpio_direction_output(data->power_gpio, 0);
}
switch (data->id) {
default:
dev_warn(dev, "Unknown TPA model (%d). Assuming 6130A2\n",
data->id);
fallthrough;
case TPA6130A2:
regulator = "Vdd";
break;
case TPA6140A2:
regulator = "AVdd";
break;
}
data->supply = devm_regulator_get(dev, regulator);
if (IS_ERR(data->supply)) {
ret = PTR_ERR(data->supply);
dev_err(dev, "Failed to request supply: %d\n", ret);
return ret;
}
ret = tpa6130a2_power(data, true);
if (ret != 0)
return ret;
/* Read version */
regmap_read(data->regmap, TPA6130A2_REG_VERSION, &version);
version &= TPA6130A2_VERSION_MASK;
if ((version != 1) && (version != 2))
dev_warn(dev, "UNTESTED version detected (%d)\n", version);
/* Disable the chip */
ret = tpa6130a2_power(data, false);
if (ret != 0)
return ret;
return devm_snd_soc_register_component(&client->dev,
&tpa6130a2_component_driver, NULL, 0);
}
#if IS_ENABLED(CONFIG_OF)
static const struct of_device_id tpa6130a2_of_match[] = {
{ .compatible = "ti,tpa6130a2", },
{ .compatible = "ti,tpa6140a2" },
{},
};
MODULE_DEVICE_TABLE(of, tpa6130a2_of_match);
#endif
static struct i2c_driver tpa6130a2_i2c_driver = {
.driver = {
.name = "tpa6130a2",
.of_match_table = of_match_ptr(tpa6130a2_of_match),
},
.probe = tpa6130a2_probe,
.id_table = tpa6130a2_id,
};
module_i2c_driver(tpa6130a2_i2c_driver);
MODULE_AUTHOR("Peter Ujfalusi <[email protected]>");
MODULE_DESCRIPTION("TPA6130A2 Headphone amplifier driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/tpa6130a2.c |
// SPDX-License-Identifier: GPL-2.0
//
// tasdevice-fmw.c -- TASDEVICE firmware support
//
// Copyright 2023 Texas Instruments, Inc.
//
// Author: Shenghao Ding <[email protected]>
#include <linux/crc8.h>
#include <linux/firmware.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/of_irq.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <sound/tas2781.h>
#define ERROR_PRAM_CRCCHK 0x0000000
#define ERROR_YRAM_CRCCHK 0x0000001
#define PPC_DRIVER_CRCCHK 0x00000200
#define TAS2781_SA_COEFF_SWAP_REG TASDEVICE_REG(0, 0x35, 0x2c)
#define TAS2781_YRAM_BOOK1 140
#define TAS2781_YRAM1_PAGE 42
#define TAS2781_YRAM1_START_REG 88
#define TAS2781_YRAM2_START_PAGE 43
#define TAS2781_YRAM2_END_PAGE 49
#define TAS2781_YRAM2_START_REG 8
#define TAS2781_YRAM2_END_REG 127
#define TAS2781_YRAM3_PAGE 50
#define TAS2781_YRAM3_START_REG 8
#define TAS2781_YRAM3_END_REG 27
/*should not include B0_P53_R44-R47 */
#define TAS2781_YRAM_BOOK2 0
#define TAS2781_YRAM4_START_PAGE 50
#define TAS2781_YRAM4_END_PAGE 60
#define TAS2781_YRAM5_PAGE 61
#define TAS2781_YRAM5_START_REG TAS2781_YRAM3_START_REG
#define TAS2781_YRAM5_END_REG TAS2781_YRAM3_END_REG
#define TASDEVICE_MAXPROGRAM_NUM_KERNEL 5
#define TASDEVICE_MAXCONFIG_NUM_KERNEL_MULTIPLE_AMPS 64
#define TASDEVICE_MAXCONFIG_NUM_KERNEL 10
#define MAIN_ALL_DEVICES_1X 0x01
#define MAIN_DEVICE_A_1X 0x02
#define MAIN_DEVICE_B_1X 0x03
#define MAIN_DEVICE_C_1X 0x04
#define MAIN_DEVICE_D_1X 0x05
#define COEFF_DEVICE_A_1X 0x12
#define COEFF_DEVICE_B_1X 0x13
#define COEFF_DEVICE_C_1X 0x14
#define COEFF_DEVICE_D_1X 0x15
#define PRE_DEVICE_A_1X 0x22
#define PRE_DEVICE_B_1X 0x23
#define PRE_DEVICE_C_1X 0x24
#define PRE_DEVICE_D_1X 0x25
#define PRE_SOFTWARE_RESET_DEVICE_A 0x41
#define PRE_SOFTWARE_RESET_DEVICE_B 0x42
#define PRE_SOFTWARE_RESET_DEVICE_C 0x43
#define PRE_SOFTWARE_RESET_DEVICE_D 0x44
#define POST_SOFTWARE_RESET_DEVICE_A 0x45
#define POST_SOFTWARE_RESET_DEVICE_B 0x46
#define POST_SOFTWARE_RESET_DEVICE_C 0x47
#define POST_SOFTWARE_RESET_DEVICE_D 0x48
struct tas_crc {
unsigned char offset;
unsigned char len;
};
static const char deviceNumber[TASDEVICE_DSP_TAS_MAX_DEVICE] = {
1, 2, 1, 2, 1, 1, 0, 2, 4, 3, 1, 2, 3, 4
};
static struct tasdevice_config_info *tasdevice_add_config(
struct tasdevice_priv *tas_priv, unsigned char *config_data,
unsigned int config_size, int *status)
{
struct tasdevice_config_info *cfg_info;
struct tasdev_blk_data **bk_da;
unsigned int config_offset = 0;
unsigned int i;
/* In most projects are many audio cases, such as music, handfree,
* receiver, games, audio-to-haptics, PMIC record, bypass mode,
* portrait, landscape, etc. Even in multiple audios, one or
* two of the chips will work for the special case, such as
* ultrasonic application. In order to support these variable-numbers
* of audio cases, flexible configs have been introduced in the
* dsp firmware.
*/
cfg_info = kzalloc(sizeof(struct tasdevice_config_info), GFP_KERNEL);
if (!cfg_info) {
*status = -ENOMEM;
goto out;
}
if (tas_priv->rcabin.fw_hdr.binary_version_num >= 0x105) {
if (config_offset + 64 > (int)config_size) {
*status = -EINVAL;
dev_err(tas_priv->dev, "add conf: Out of boundary\n");
goto out;
}
config_offset += 64;
}
if (config_offset + 4 > (int)config_size) {
*status = -EINVAL;
dev_err(tas_priv->dev, "add config: Out of boundary\n");
goto out;
}
/* convert data[offset], data[offset + 1], data[offset + 2] and
* data[offset + 3] into host
*/
cfg_info->nblocks =
be32_to_cpup((__be32 *)&config_data[config_offset]);
config_offset += 4;
/* Several kinds of dsp/algorithm firmwares can run on tas2781,
* the number and size of blk are not fixed and different among
* these firmwares.
*/
bk_da = cfg_info->blk_data = kcalloc(cfg_info->nblocks,
sizeof(struct tasdev_blk_data *), GFP_KERNEL);
if (!bk_da) {
*status = -ENOMEM;
goto out;
}
cfg_info->real_nblocks = 0;
for (i = 0; i < cfg_info->nblocks; i++) {
if (config_offset + 12 > config_size) {
*status = -EINVAL;
dev_err(tas_priv->dev,
"%s: Out of boundary: i = %d nblocks = %u!\n",
__func__, i, cfg_info->nblocks);
break;
}
bk_da[i] = kzalloc(sizeof(struct tasdev_blk_data), GFP_KERNEL);
if (!bk_da[i]) {
*status = -ENOMEM;
break;
}
bk_da[i]->dev_idx = config_data[config_offset];
config_offset++;
bk_da[i]->block_type = config_data[config_offset];
config_offset++;
if (bk_da[i]->block_type == TASDEVICE_BIN_BLK_PRE_POWER_UP) {
if (bk_da[i]->dev_idx == 0)
cfg_info->active_dev =
(1 << tas_priv->ndev) - 1;
else
cfg_info->active_dev |= 1 <<
(bk_da[i]->dev_idx - 1);
}
bk_da[i]->yram_checksum =
be16_to_cpup((__be16 *)&config_data[config_offset]);
config_offset += 2;
bk_da[i]->block_size =
be32_to_cpup((__be32 *)&config_data[config_offset]);
config_offset += 4;
bk_da[i]->n_subblks =
be32_to_cpup((__be32 *)&config_data[config_offset]);
config_offset += 4;
if (config_offset + bk_da[i]->block_size > config_size) {
*status = -EINVAL;
dev_err(tas_priv->dev,
"%s: Out of boundary: i = %d blks = %u!\n",
__func__, i, cfg_info->nblocks);
break;
}
/* instead of kzalloc+memcpy */
bk_da[i]->regdata = kmemdup(&config_data[config_offset],
bk_da[i]->block_size, GFP_KERNEL);
if (!bk_da[i]->regdata) {
*status = -ENOMEM;
goto out;
}
config_offset += bk_da[i]->block_size;
cfg_info->real_nblocks += 1;
}
out:
return cfg_info;
}
int tasdevice_rca_parser(void *context, const struct firmware *fmw)
{
struct tasdevice_priv *tas_priv = context;
struct tasdevice_config_info **cfg_info;
struct tasdevice_rca_hdr *fw_hdr;
struct tasdevice_rca *rca;
unsigned int total_config_sz = 0;
unsigned char *buf;
int offset = 0;
int ret = 0;
int i;
rca = &(tas_priv->rcabin);
fw_hdr = &(rca->fw_hdr);
if (!fmw || !fmw->data) {
dev_err(tas_priv->dev, "Failed to read %s\n",
tas_priv->rca_binaryname);
tas_priv->fw_state = TASDEVICE_DSP_FW_FAIL;
ret = -EINVAL;
goto out;
}
buf = (unsigned char *)fmw->data;
fw_hdr->img_sz = be32_to_cpup((__be32 *)&buf[offset]);
offset += 4;
if (fw_hdr->img_sz != fmw->size) {
dev_err(tas_priv->dev,
"File size not match, %d %u", (int)fmw->size,
fw_hdr->img_sz);
tas_priv->fw_state = TASDEVICE_DSP_FW_FAIL;
ret = -EINVAL;
goto out;
}
fw_hdr->checksum = be32_to_cpup((__be32 *)&buf[offset]);
offset += 4;
fw_hdr->binary_version_num = be32_to_cpup((__be32 *)&buf[offset]);
if (fw_hdr->binary_version_num < 0x103) {
dev_err(tas_priv->dev, "File version 0x%04x is too low",
fw_hdr->binary_version_num);
tas_priv->fw_state = TASDEVICE_DSP_FW_FAIL;
ret = -EINVAL;
goto out;
}
offset += 4;
fw_hdr->drv_fw_version = be32_to_cpup((__be32 *)&buf[offset]);
offset += 8;
fw_hdr->plat_type = buf[offset];
offset += 1;
fw_hdr->dev_family = buf[offset];
offset += 1;
fw_hdr->reserve = buf[offset];
offset += 1;
fw_hdr->ndev = buf[offset];
offset += 1;
if (fw_hdr->ndev != tas_priv->ndev) {
dev_err(tas_priv->dev,
"ndev(%u) in rcabin mismatch ndev(%u) in DTS\n",
fw_hdr->ndev, tas_priv->ndev);
tas_priv->fw_state = TASDEVICE_DSP_FW_FAIL;
ret = -EINVAL;
goto out;
}
if (offset + TASDEVICE_DEVICE_SUM > fw_hdr->img_sz) {
dev_err(tas_priv->dev, "rca_ready: Out of boundary!\n");
ret = -EINVAL;
tas_priv->fw_state = TASDEVICE_DSP_FW_FAIL;
goto out;
}
for (i = 0; i < TASDEVICE_DEVICE_SUM; i++, offset++)
fw_hdr->devs[i] = buf[offset];
fw_hdr->nconfig = be32_to_cpup((__be32 *)&buf[offset]);
offset += 4;
for (i = 0; i < TASDEVICE_CONFIG_SUM; i++) {
fw_hdr->config_size[i] = be32_to_cpup((__be32 *)&buf[offset]);
offset += 4;
total_config_sz += fw_hdr->config_size[i];
}
if (fw_hdr->img_sz - total_config_sz != (unsigned int)offset) {
dev_err(tas_priv->dev, "Bin file error!\n");
ret = -EINVAL;
tas_priv->fw_state = TASDEVICE_DSP_FW_FAIL;
goto out;
}
cfg_info = kcalloc(fw_hdr->nconfig, sizeof(*cfg_info), GFP_KERNEL);
if (!cfg_info) {
ret = -ENOMEM;
tas_priv->fw_state = TASDEVICE_DSP_FW_FAIL;
goto out;
}
rca->cfg_info = cfg_info;
rca->ncfgs = 0;
for (i = 0; i < (int)fw_hdr->nconfig; i++) {
rca->ncfgs += 1;
cfg_info[i] = tasdevice_add_config(tas_priv, &buf[offset],
fw_hdr->config_size[i], &ret);
if (ret) {
tas_priv->fw_state = TASDEVICE_DSP_FW_FAIL;
goto out;
}
offset += (int)fw_hdr->config_size[i];
}
out:
return ret;
}
EXPORT_SYMBOL_NS_GPL(tasdevice_rca_parser, SND_SOC_TAS2781_FMWLIB);
static int fw_parse_block_data_kernel(struct tasdevice_fw *tas_fmw,
struct tasdev_blk *block, const struct firmware *fmw, int offset)
{
const unsigned char *data = fmw->data;
if (offset + 16 > fmw->size) {
dev_err(tas_fmw->dev, "%s: File Size error\n", __func__);
offset = -EINVAL;
goto out;
}
/* convert data[offset], data[offset + 1], data[offset + 2] and
* data[offset + 3] into host
*/
block->type = be32_to_cpup((__be32 *)&data[offset]);
offset += 4;
block->is_pchksum_present = data[offset];
offset++;
block->pchksum = data[offset];
offset++;
block->is_ychksum_present = data[offset];
offset++;
block->ychksum = data[offset];
offset++;
block->blk_size = be32_to_cpup((__be32 *)&data[offset]);
offset += 4;
block->nr_subblocks = be32_to_cpup((__be32 *)&data[offset]);
offset += 4;
if (offset + block->blk_size > fmw->size) {
dev_err(tas_fmw->dev, "%s: nSublocks error\n", __func__);
offset = -EINVAL;
goto out;
}
/* instead of kzalloc+memcpy */
block->data = kmemdup(&data[offset], block->blk_size, GFP_KERNEL);
if (!block->data) {
offset = -ENOMEM;
goto out;
}
offset += block->blk_size;
out:
return offset;
}
static int fw_parse_data_kernel(struct tasdevice_fw *tas_fmw,
struct tasdevice_data *img_data, const struct firmware *fmw,
int offset)
{
const unsigned char *data = fmw->data;
struct tasdev_blk *blk;
unsigned int i;
if (offset + 4 > fmw->size) {
dev_err(tas_fmw->dev, "%s: File Size error\n", __func__);
offset = -EINVAL;
goto out;
}
img_data->nr_blk = be32_to_cpup((__be32 *)&data[offset]);
offset += 4;
img_data->dev_blks = kcalloc(img_data->nr_blk,
sizeof(struct tasdev_blk), GFP_KERNEL);
if (!img_data->dev_blks) {
offset = -ENOMEM;
goto out;
}
for (i = 0; i < img_data->nr_blk; i++) {
blk = &(img_data->dev_blks[i]);
offset = fw_parse_block_data_kernel(tas_fmw, blk, fmw, offset);
if (offset < 0) {
offset = -EINVAL;
break;
}
}
out:
return offset;
}
static int fw_parse_program_data_kernel(
struct tasdevice_priv *tas_priv, struct tasdevice_fw *tas_fmw,
const struct firmware *fmw, int offset)
{
struct tasdevice_prog *program;
unsigned int i;
for (i = 0; i < tas_fmw->nr_programs; i++) {
program = &(tas_fmw->programs[i]);
if (offset + 72 > fmw->size) {
dev_err(tas_priv->dev, "%s: mpName error\n", __func__);
offset = -EINVAL;
goto out;
}
/*skip 72 unused byts*/
offset += 72;
offset = fw_parse_data_kernel(tas_fmw, &(program->dev_data),
fmw, offset);
if (offset < 0)
goto out;
}
out:
return offset;
}
static int fw_parse_configuration_data_kernel(
struct tasdevice_priv *tas_priv,
struct tasdevice_fw *tas_fmw, const struct firmware *fmw, int offset)
{
const unsigned char *data = fmw->data;
struct tasdevice_config *config;
unsigned int i;
for (i = 0; i < tas_fmw->nr_configurations; i++) {
config = &(tas_fmw->configs[i]);
if (offset + 80 > fmw->size) {
dev_err(tas_priv->dev, "%s: mpName error\n", __func__);
offset = -EINVAL;
goto out;
}
memcpy(config->name, &data[offset], 64);
/*skip extra 16 bytes*/
offset += 80;
offset = fw_parse_data_kernel(tas_fmw, &(config->dev_data),
fmw, offset);
if (offset < 0)
goto out;
}
out:
return offset;
}
static int fw_parse_variable_header_kernel(
struct tasdevice_priv *tas_priv, const struct firmware *fmw,
int offset)
{
struct tasdevice_fw *tas_fmw = tas_priv->fmw;
struct tasdevice_dspfw_hdr *fw_hdr = &(tas_fmw->fw_hdr);
struct tasdevice_prog *program;
struct tasdevice_config *config;
const unsigned char *buf = fmw->data;
unsigned short max_confs;
unsigned int i;
if (offset + 12 + 4 * TASDEVICE_MAXPROGRAM_NUM_KERNEL > fmw->size) {
dev_err(tas_priv->dev, "%s: File Size error\n", __func__);
offset = -EINVAL;
goto out;
}
fw_hdr->device_family = be16_to_cpup((__be16 *)&buf[offset]);
if (fw_hdr->device_family != 0) {
dev_err(tas_priv->dev, "%s:not TAS device\n", __func__);
offset = -EINVAL;
goto out;
}
offset += 2;
fw_hdr->device = be16_to_cpup((__be16 *)&buf[offset]);
if (fw_hdr->device >= TASDEVICE_DSP_TAS_MAX_DEVICE ||
fw_hdr->device == 6) {
dev_err(tas_priv->dev, "Unsupported dev %d\n", fw_hdr->device);
offset = -EINVAL;
goto out;
}
offset += 2;
fw_hdr->ndev = deviceNumber[fw_hdr->device];
if (fw_hdr->ndev != tas_priv->ndev) {
dev_err(tas_priv->dev,
"%s: ndev(%u) in dspbin mismatch ndev(%u) in DTS\n",
__func__, fw_hdr->ndev, tas_priv->ndev);
offset = -EINVAL;
goto out;
}
tas_fmw->nr_programs = be32_to_cpup((__be32 *)&buf[offset]);
offset += 4;
if (tas_fmw->nr_programs == 0 || tas_fmw->nr_programs >
TASDEVICE_MAXPROGRAM_NUM_KERNEL) {
dev_err(tas_priv->dev, "mnPrograms is invalid\n");
offset = -EINVAL;
goto out;
}
tas_fmw->programs = kcalloc(tas_fmw->nr_programs,
sizeof(struct tasdevice_prog), GFP_KERNEL);
if (!tas_fmw->programs) {
offset = -ENOMEM;
goto out;
}
for (i = 0; i < tas_fmw->nr_programs; i++) {
program = &(tas_fmw->programs[i]);
program->prog_size = be32_to_cpup((__be32 *)&buf[offset]);
offset += 4;
}
/* Skip the unused prog_size */
offset += 4 * (TASDEVICE_MAXPROGRAM_NUM_KERNEL - tas_fmw->nr_programs);
tas_fmw->nr_configurations = be32_to_cpup((__be32 *)&buf[offset]);
offset += 4;
/* The max number of config in firmware greater than 4 pieces of
* tas2781s is different from the one lower than 4 pieces of
* tas2781s.
*/
max_confs = (fw_hdr->ndev >= 4) ?
TASDEVICE_MAXCONFIG_NUM_KERNEL_MULTIPLE_AMPS :
TASDEVICE_MAXCONFIG_NUM_KERNEL;
if (tas_fmw->nr_configurations == 0 ||
tas_fmw->nr_configurations > max_confs) {
dev_err(tas_priv->dev, "%s: Conf is invalid\n", __func__);
offset = -EINVAL;
goto out;
}
if (offset + 4 * max_confs > fmw->size) {
dev_err(tas_priv->dev, "%s: mpConfigurations err\n", __func__);
offset = -EINVAL;
goto out;
}
tas_fmw->configs = kcalloc(tas_fmw->nr_configurations,
sizeof(struct tasdevice_config), GFP_KERNEL);
if (!tas_fmw->configs) {
offset = -ENOMEM;
goto out;
}
for (i = 0; i < tas_fmw->nr_programs; i++) {
config = &(tas_fmw->configs[i]);
config->cfg_size = be32_to_cpup((__be32 *)&buf[offset]);
offset += 4;
}
/* Skip the unused configs */
offset += 4 * (max_confs - tas_fmw->nr_programs);
out:
return offset;
}
static int tasdevice_process_block(void *context, unsigned char *data,
unsigned char dev_idx, int sublocksize)
{
struct tasdevice_priv *tas_priv = (struct tasdevice_priv *)context;
int subblk_offset, chn, chnend, rc;
unsigned char subblk_typ = data[1];
int blktyp = dev_idx & 0xC0;
int idx = dev_idx & 0x3F;
bool is_err = false;
if (idx) {
chn = idx - 1;
chnend = idx;
} else {
chn = 0;
chnend = tas_priv->ndev;
}
for (; chn < chnend; chn++) {
if (tas_priv->tasdevice[chn].is_loading == false)
continue;
is_err = false;
subblk_offset = 2;
switch (subblk_typ) {
case TASDEVICE_CMD_SING_W: {
int i;
unsigned short len = be16_to_cpup((__be16 *)&data[2]);
subblk_offset += 2;
if (subblk_offset + 4 * len > sublocksize) {
dev_err(tas_priv->dev,
"process_block: Out of boundary\n");
is_err = true;
break;
}
for (i = 0; i < len; i++) {
rc = tasdevice_dev_write(tas_priv, chn,
TASDEVICE_REG(data[subblk_offset],
data[subblk_offset + 1],
data[subblk_offset + 2]),
data[subblk_offset + 3]);
if (rc < 0) {
is_err = true;
dev_err(tas_priv->dev,
"process_block: single write error\n");
}
subblk_offset += 4;
}
}
break;
case TASDEVICE_CMD_BURST: {
unsigned short len = be16_to_cpup((__be16 *)&data[2]);
subblk_offset += 2;
if (subblk_offset + 4 + len > sublocksize) {
dev_err(tas_priv->dev,
"%s: BST Out of boundary\n",
__func__);
is_err = true;
break;
}
if (len % 4) {
dev_err(tas_priv->dev,
"%s:Bst-len(%u)not div by 4\n",
__func__, len);
break;
}
rc = tasdevice_dev_bulk_write(tas_priv, chn,
TASDEVICE_REG(data[subblk_offset],
data[subblk_offset + 1],
data[subblk_offset + 2]),
&(data[subblk_offset + 4]), len);
if (rc < 0) {
is_err = true;
dev_err(tas_priv->dev,
"%s: bulk_write error = %d\n",
__func__, rc);
}
subblk_offset += (len + 4);
}
break;
case TASDEVICE_CMD_DELAY: {
unsigned int sleep_time = 0;
if (subblk_offset + 2 > sublocksize) {
dev_err(tas_priv->dev,
"%s: delay Out of boundary\n",
__func__);
is_err = true;
break;
}
sleep_time = be16_to_cpup((__be16 *)&data[2]) * 1000;
usleep_range(sleep_time, sleep_time + 50);
subblk_offset += 2;
}
break;
case TASDEVICE_CMD_FIELD_W:
if (subblk_offset + 6 > sublocksize) {
dev_err(tas_priv->dev,
"%s: bit write Out of boundary\n",
__func__);
is_err = true;
break;
}
rc = tasdevice_dev_update_bits(tas_priv, chn,
TASDEVICE_REG(data[subblk_offset + 2],
data[subblk_offset + 3],
data[subblk_offset + 4]),
data[subblk_offset + 1],
data[subblk_offset + 5]);
if (rc < 0) {
is_err = true;
dev_err(tas_priv->dev,
"%s: update_bits error = %d\n",
__func__, rc);
}
subblk_offset += 6;
break;
default:
break;
}
if (is_err == true && blktyp != 0) {
if (blktyp == 0x80) {
tas_priv->tasdevice[chn].cur_prog = -1;
tas_priv->tasdevice[chn].cur_conf = -1;
} else
tas_priv->tasdevice[chn].cur_conf = -1;
}
}
return subblk_offset;
}
void tasdevice_select_cfg_blk(void *pContext, int conf_no,
unsigned char block_type)
{
struct tasdevice_priv *tas_priv = (struct tasdevice_priv *) pContext;
struct tasdevice_rca *rca = &(tas_priv->rcabin);
struct tasdevice_config_info **cfg_info = rca->cfg_info;
struct tasdev_blk_data **blk_data;
int j, k, chn, chnend;
if (conf_no >= rca->ncfgs || conf_no < 0 || !cfg_info) {
dev_err(tas_priv->dev, "conf_no should be not more than %u\n",
rca->ncfgs);
return;
}
blk_data = cfg_info[conf_no]->blk_data;
for (j = 0; j < (int)cfg_info[conf_no]->real_nblocks; j++) {
unsigned int length = 0, rc = 0;
if (block_type > 5 || block_type < 2) {
dev_err(tas_priv->dev,
"block_type should be in range from 2 to 5\n");
break;
}
if (block_type != blk_data[j]->block_type)
continue;
for (k = 0; k < (int)blk_data[j]->n_subblks; k++) {
if (blk_data[j]->dev_idx) {
chn = blk_data[j]->dev_idx - 1;
chnend = blk_data[j]->dev_idx;
} else {
chn = 0;
chnend = tas_priv->ndev;
}
for (; chn < chnend; chn++)
tas_priv->tasdevice[chn].is_loading = true;
rc = tasdevice_process_block(tas_priv,
blk_data[j]->regdata + length,
blk_data[j]->dev_idx,
blk_data[j]->block_size - length);
length += rc;
if (blk_data[j]->block_size < length) {
dev_err(tas_priv->dev,
"%s: %u %u out of boundary\n",
__func__, length,
blk_data[j]->block_size);
break;
}
}
if (length != blk_data[j]->block_size)
dev_err(tas_priv->dev, "%s: %u %u size is not same\n",
__func__, length, blk_data[j]->block_size);
}
}
EXPORT_SYMBOL_NS_GPL(tasdevice_select_cfg_blk, SND_SOC_TAS2781_FMWLIB);
static int tasdevice_load_block_kernel(
struct tasdevice_priv *tasdevice, struct tasdev_blk *block)
{
struct tasdevice_dspfw_hdr *fw_hdr = &(tasdevice->fmw->fw_hdr);
struct tasdevice_fw_fixed_hdr *fw_fixed_hdr = &(fw_hdr->fixed_hdr);
const unsigned int blk_size = block->blk_size;
unsigned int i, length;
unsigned char *data = block->data;
unsigned char dev_idx = 0;
if (fw_fixed_hdr->ppcver >= PPC3_VERSION_TAS2781) {
switch (block->type) {
case MAIN_ALL_DEVICES_1X:
dev_idx = 0x80;
break;
case MAIN_DEVICE_A_1X:
dev_idx = 0x81;
break;
case COEFF_DEVICE_A_1X:
case PRE_DEVICE_A_1X:
case PRE_SOFTWARE_RESET_DEVICE_A:
case POST_SOFTWARE_RESET_DEVICE_A:
dev_idx = 0xC1;
break;
case MAIN_DEVICE_B_1X:
dev_idx = 0x82;
break;
case COEFF_DEVICE_B_1X:
case PRE_DEVICE_B_1X:
case PRE_SOFTWARE_RESET_DEVICE_B:
case POST_SOFTWARE_RESET_DEVICE_B:
dev_idx = 0xC2;
break;
case MAIN_DEVICE_C_1X:
dev_idx = 0x83;
break;
case COEFF_DEVICE_C_1X:
case PRE_DEVICE_C_1X:
case PRE_SOFTWARE_RESET_DEVICE_C:
case POST_SOFTWARE_RESET_DEVICE_C:
dev_idx = 0xC3;
break;
case MAIN_DEVICE_D_1X:
dev_idx = 0x84;
break;
case COEFF_DEVICE_D_1X:
case PRE_DEVICE_D_1X:
case PRE_SOFTWARE_RESET_DEVICE_D:
case POST_SOFTWARE_RESET_DEVICE_D:
dev_idx = 0xC4;
break;
default:
dev_info(tasdevice->dev,
"%s: load block: Other Type = 0x%02x\n",
__func__, block->type);
break;
}
} else if (fw_fixed_hdr->ppcver >=
PPC3_VERSION) {
switch (block->type) {
case MAIN_ALL_DEVICES_1X:
dev_idx = 0x80;
break;
case MAIN_DEVICE_A_1X:
dev_idx = 0x81;
break;
case COEFF_DEVICE_A_1X:
case PRE_DEVICE_A_1X:
dev_idx = 0xC1;
break;
case MAIN_DEVICE_B_1X:
dev_idx = 0x82;
break;
case COEFF_DEVICE_B_1X:
case PRE_DEVICE_B_1X:
dev_idx = 0xC2;
break;
case MAIN_DEVICE_C_1X:
dev_idx = 0x83;
break;
case COEFF_DEVICE_C_1X:
case PRE_DEVICE_C_1X:
dev_idx = 0xC3;
break;
case MAIN_DEVICE_D_1X:
dev_idx = 0x84;
break;
case COEFF_DEVICE_D_1X:
case PRE_DEVICE_D_1X:
dev_idx = 0xC4;
break;
default:
dev_info(tasdevice->dev,
"%s: load block: Other Type = 0x%02x\n",
__func__, block->type);
break;
}
} else {
switch (block->type) {
case MAIN_ALL_DEVICES:
dev_idx = 0|0x80;
break;
case MAIN_DEVICE_A:
dev_idx = 0x81;
break;
case COEFF_DEVICE_A:
case PRE_DEVICE_A:
dev_idx = 0xC1;
break;
case MAIN_DEVICE_B:
dev_idx = 0x82;
break;
case COEFF_DEVICE_B:
case PRE_DEVICE_B:
dev_idx = 0xC2;
break;
case MAIN_DEVICE_C:
dev_idx = 0x83;
break;
case COEFF_DEVICE_C:
case PRE_DEVICE_C:
dev_idx = 0xC3;
break;
case MAIN_DEVICE_D:
dev_idx = 0x84;
break;
case COEFF_DEVICE_D:
case PRE_DEVICE_D:
dev_idx = 0xC4;
break;
default:
dev_info(tasdevice->dev,
"%s: load block: Other Type = 0x%02x\n",
__func__, block->type);
break;
}
}
for (i = 0, length = 0; i < block->nr_subblocks; i++) {
int rc = tasdevice_process_block(tasdevice, data + length,
dev_idx, blk_size - length);
if (rc < 0) {
dev_err(tasdevice->dev,
"%s: %u %u sublock write error\n",
__func__, length, blk_size);
break;
}
length += (unsigned int)rc;
if (blk_size < length) {
dev_err(tasdevice->dev, "%s: %u %u out of boundary\n",
__func__, length, blk_size);
break;
}
}
return 0;
}
static int fw_parse_variable_hdr(struct tasdevice_priv
*tas_priv, struct tasdevice_dspfw_hdr *fw_hdr,
const struct firmware *fmw, int offset)
{
const unsigned char *buf = fmw->data;
int len = strlen((char *)&buf[offset]);
len++;
if (offset + len + 8 > fmw->size) {
dev_err(tas_priv->dev, "%s: File Size error\n", __func__);
offset = -EINVAL;
goto out;
}
offset += len;
fw_hdr->device_family = be32_to_cpup((__be32 *)&buf[offset]);
if (fw_hdr->device_family != 0) {
dev_err(tas_priv->dev, "%s: not TAS device\n", __func__);
offset = -EINVAL;
goto out;
}
offset += 4;
fw_hdr->device = be32_to_cpup((__be32 *)&buf[offset]);
if (fw_hdr->device >= TASDEVICE_DSP_TAS_MAX_DEVICE ||
fw_hdr->device == 6) {
dev_err(tas_priv->dev, "Unsupported dev %d\n", fw_hdr->device);
offset = -EINVAL;
goto out;
}
offset += 4;
fw_hdr->ndev = deviceNumber[fw_hdr->device];
out:
return offset;
}
static int fw_parse_variable_header_git(struct tasdevice_priv
*tas_priv, const struct firmware *fmw, int offset)
{
struct tasdevice_fw *tas_fmw = tas_priv->fmw;
struct tasdevice_dspfw_hdr *fw_hdr = &(tas_fmw->fw_hdr);
offset = fw_parse_variable_hdr(tas_priv, fw_hdr, fmw, offset);
if (offset < 0)
goto out;
if (fw_hdr->ndev != tas_priv->ndev) {
dev_err(tas_priv->dev,
"%s: ndev(%u) in dspbin mismatch ndev(%u) in DTS\n",
__func__, fw_hdr->ndev, tas_priv->ndev);
offset = -EINVAL;
}
out:
return offset;
}
static int fw_parse_block_data(struct tasdevice_fw *tas_fmw,
struct tasdev_blk *block, const struct firmware *fmw, int offset)
{
unsigned char *data = (unsigned char *)fmw->data;
int n;
if (offset + 8 > fmw->size) {
dev_err(tas_fmw->dev, "%s: Type error\n", __func__);
offset = -EINVAL;
goto out;
}
block->type = be32_to_cpup((__be32 *)&data[offset]);
offset += 4;
if (tas_fmw->fw_hdr.fixed_hdr.drv_ver >= PPC_DRIVER_CRCCHK) {
if (offset + 8 > fmw->size) {
dev_err(tas_fmw->dev, "PChkSumPresent error\n");
offset = -EINVAL;
goto out;
}
block->is_pchksum_present = data[offset];
offset++;
block->pchksum = data[offset];
offset++;
block->is_ychksum_present = data[offset];
offset++;
block->ychksum = data[offset];
offset++;
} else {
block->is_pchksum_present = 0;
block->is_ychksum_present = 0;
}
block->nr_cmds = be32_to_cpup((__be32 *)&data[offset]);
offset += 4;
n = block->nr_cmds * 4;
if (offset + n > fmw->size) {
dev_err(tas_fmw->dev,
"%s: File Size(%lu) error offset = %d n = %d\n",
__func__, (unsigned long)fmw->size, offset, n);
offset = -EINVAL;
goto out;
}
/* instead of kzalloc+memcpy */
block->data = kmemdup(&data[offset], n, GFP_KERNEL);
if (!block->data) {
offset = -ENOMEM;
goto out;
}
offset += n;
out:
return offset;
}
/* When parsing error occurs, all the memory resource will be released
* in the end of tasdevice_rca_ready.
*/
static int fw_parse_data(struct tasdevice_fw *tas_fmw,
struct tasdevice_data *img_data, const struct firmware *fmw,
int offset)
{
const unsigned char *data = (unsigned char *)fmw->data;
struct tasdev_blk *blk;
unsigned int i;
int n;
if (offset + 64 > fmw->size) {
dev_err(tas_fmw->dev, "%s: Name error\n", __func__);
offset = -EINVAL;
goto out;
}
memcpy(img_data->name, &data[offset], 64);
offset += 64;
n = strlen((char *)&data[offset]);
n++;
if (offset + n + 2 > fmw->size) {
dev_err(tas_fmw->dev, "%s: Description error\n", __func__);
offset = -EINVAL;
goto out;
}
offset += n;
img_data->nr_blk = be16_to_cpup((__be16 *)&data[offset]);
offset += 2;
img_data->dev_blks = kcalloc(img_data->nr_blk,
sizeof(struct tasdev_blk), GFP_KERNEL);
if (!img_data->dev_blks) {
offset = -ENOMEM;
goto out;
}
for (i = 0; i < img_data->nr_blk; i++) {
blk = &(img_data->dev_blks[i]);
offset = fw_parse_block_data(tas_fmw, blk, fmw, offset);
if (offset < 0) {
offset = -EINVAL;
goto out;
}
}
out:
return offset;
}
/* When parsing error occurs, all the memory resource will be released
* in the end of tasdevice_rca_ready.
*/
static int fw_parse_program_data(struct tasdevice_priv *tas_priv,
struct tasdevice_fw *tas_fmw, const struct firmware *fmw, int offset)
{
unsigned char *buf = (unsigned char *)fmw->data;
struct tasdevice_prog *program;
int i;
if (offset + 2 > fmw->size) {
dev_err(tas_priv->dev, "%s: File Size error\n", __func__);
offset = -EINVAL;
goto out;
}
tas_fmw->nr_programs = be16_to_cpup((__be16 *)&buf[offset]);
offset += 2;
if (tas_fmw->nr_programs == 0) {
/*Not error in calibration Data file, return directly*/
dev_info(tas_priv->dev, "%s: No Programs data, maybe calbin\n",
__func__);
goto out;
}
tas_fmw->programs =
kcalloc(tas_fmw->nr_programs, sizeof(struct tasdevice_prog),
GFP_KERNEL);
if (!tas_fmw->programs) {
offset = -ENOMEM;
goto out;
}
for (i = 0; i < tas_fmw->nr_programs; i++) {
int n = 0;
program = &(tas_fmw->programs[i]);
if (offset + 64 > fmw->size) {
dev_err(tas_priv->dev, "%s: mpName error\n", __func__);
offset = -EINVAL;
goto out;
}
offset += 64;
n = strlen((char *)&buf[offset]);
/* skip '\0' and 5 unused bytes */
n += 6;
if (offset + n > fmw->size) {
dev_err(tas_priv->dev, "Description err\n");
offset = -EINVAL;
goto out;
}
offset += n;
offset = fw_parse_data(tas_fmw, &(program->dev_data), fmw,
offset);
if (offset < 0)
goto out;
}
out:
return offset;
}
/* When parsing error occurs, all the memory resource will be released
* in the end of tasdevice_rca_ready.
*/
static int fw_parse_configuration_data(
struct tasdevice_priv *tas_priv,
struct tasdevice_fw *tas_fmw,
const struct firmware *fmw, int offset)
{
unsigned char *data = (unsigned char *)fmw->data;
struct tasdevice_config *config;
unsigned int i;
int n;
if (offset + 2 > fmw->size) {
dev_err(tas_priv->dev, "%s: File Size error\n", __func__);
offset = -EINVAL;
goto out;
}
tas_fmw->nr_configurations = be16_to_cpup((__be16 *)&data[offset]);
offset += 2;
if (tas_fmw->nr_configurations == 0) {
dev_err(tas_priv->dev, "%s: Conf is zero\n", __func__);
/*Not error for calibration Data file, return directly*/
goto out;
}
tas_fmw->configs = kcalloc(tas_fmw->nr_configurations,
sizeof(struct tasdevice_config), GFP_KERNEL);
if (!tas_fmw->configs) {
offset = -ENOMEM;
goto out;
}
for (i = 0; i < tas_fmw->nr_configurations; i++) {
config = &(tas_fmw->configs[i]);
if (offset + 64 > fmw->size) {
dev_err(tas_priv->dev, "File Size err\n");
offset = -EINVAL;
goto out;
}
memcpy(config->name, &data[offset], 64);
offset += 64;
n = strlen((char *)&data[offset]);
n += 15;
if (offset + n > fmw->size) {
dev_err(tas_priv->dev, "Description err\n");
offset = -EINVAL;
goto out;
}
offset += n;
offset = fw_parse_data(tas_fmw, &(config->dev_data),
fmw, offset);
if (offset < 0)
goto out;
}
out:
return offset;
}
static bool check_inpage_yram_rg(struct tas_crc *cd,
unsigned char reg, unsigned char len)
{
bool in = false;
if (reg <= TAS2781_YRAM5_END_REG &&
reg >= TAS2781_YRAM5_START_REG) {
if (reg + len > TAS2781_YRAM5_END_REG)
cd->len = TAS2781_YRAM5_END_REG - reg + 1;
else
cd->len = len;
cd->offset = reg;
in = true;
} else if (reg < TAS2781_YRAM5_START_REG) {
if (reg + len > TAS2781_YRAM5_START_REG) {
cd->offset = TAS2781_YRAM5_START_REG;
cd->len = len - TAS2781_YRAM5_START_REG + reg;
in = true;
}
}
return in;
}
static bool check_inpage_yram_bk1(struct tas_crc *cd,
unsigned char page, unsigned char reg, unsigned char len)
{
bool in = false;
if (page == TAS2781_YRAM1_PAGE) {
if (reg >= TAS2781_YRAM1_START_REG) {
cd->offset = reg;
cd->len = len;
in = true;
} else if (reg + len > TAS2781_YRAM1_START_REG) {
cd->offset = TAS2781_YRAM1_START_REG;
cd->len = len - TAS2781_YRAM1_START_REG + reg;
in = true;
}
} else if (page == TAS2781_YRAM3_PAGE)
in = check_inpage_yram_rg(cd, reg, len);
return in;
}
/* Return Code:
* true -- the registers are in the inpage yram
* false -- the registers are NOT in the inpage yram
*/
static bool check_inpage_yram(struct tas_crc *cd, unsigned char book,
unsigned char page, unsigned char reg, unsigned char len)
{
bool in = false;
if (book == TAS2781_YRAM_BOOK1) {
in = check_inpage_yram_bk1(cd, page, reg, len);
goto end;
}
if (book == TAS2781_YRAM_BOOK2 && page == TAS2781_YRAM5_PAGE)
in = check_inpage_yram_rg(cd, reg, len);
end:
return in;
}
static bool check_inblock_yram_bk(struct tas_crc *cd,
unsigned char page, unsigned char reg, unsigned char len)
{
bool in = false;
if ((page >= TAS2781_YRAM4_START_PAGE &&
page <= TAS2781_YRAM4_END_PAGE) ||
(page >= TAS2781_YRAM2_START_PAGE &&
page <= TAS2781_YRAM2_END_PAGE)) {
if (reg <= TAS2781_YRAM2_END_REG &&
reg >= TAS2781_YRAM2_START_REG) {
cd->offset = reg;
cd->len = len;
in = true;
} else if (reg < TAS2781_YRAM2_START_REG) {
if (reg + len - 1 >= TAS2781_YRAM2_START_REG) {
cd->offset = TAS2781_YRAM2_START_REG;
cd->len = reg + len - TAS2781_YRAM2_START_REG;
in = true;
}
}
}
return in;
}
/* Return Code:
* true -- the registers are in the inblock yram
* false -- the registers are NOT in the inblock yram
*/
static bool check_inblock_yram(struct tas_crc *cd, unsigned char book,
unsigned char page, unsigned char reg, unsigned char len)
{
bool in = false;
if (book == TAS2781_YRAM_BOOK1 || book == TAS2781_YRAM_BOOK2)
in = check_inblock_yram_bk(cd, page, reg, len);
return in;
}
static bool check_yram(struct tas_crc *cd, unsigned char book,
unsigned char page, unsigned char reg, unsigned char len)
{
bool in;
in = check_inpage_yram(cd, book, page, reg, len);
if (in)
goto end;
in = check_inblock_yram(cd, book, page, reg, len);
end:
return in;
}
static int tasdev_multibytes_chksum(struct tasdevice_priv *tasdevice,
unsigned short chn, unsigned char book, unsigned char page,
unsigned char reg, unsigned int len)
{
struct tas_crc crc_data;
unsigned char crc_chksum = 0;
unsigned char nBuf1[128];
int ret = 0;
int i;
bool in;
if ((reg + len - 1) > 127) {
ret = -EINVAL;
dev_err(tasdevice->dev, "firmware error\n");
goto end;
}
if ((book == TASDEVICE_BOOK_ID(TAS2781_SA_COEFF_SWAP_REG))
&& (page == TASDEVICE_PAGE_ID(TAS2781_SA_COEFF_SWAP_REG))
&& (reg == TASDEVICE_PAGE_REG(TAS2781_SA_COEFF_SWAP_REG))
&& (len == 4)) {
/*DSP swap command, pass */
ret = 0;
goto end;
}
in = check_yram(&crc_data, book, page, reg, len);
if (!in)
goto end;
if (len == 1) {
dev_err(tasdevice->dev, "firmware error\n");
ret = -EINVAL;
goto end;
}
ret = tasdevice_dev_bulk_read(tasdevice, chn,
TASDEVICE_REG(book, page, crc_data.offset),
nBuf1, crc_data.len);
if (ret < 0)
goto end;
for (i = 0; i < crc_data.len; i++) {
if ((book == TASDEVICE_BOOK_ID(TAS2781_SA_COEFF_SWAP_REG))
&& (page == TASDEVICE_PAGE_ID(
TAS2781_SA_COEFF_SWAP_REG))
&& ((i + crc_data.offset)
>= TASDEVICE_PAGE_REG(TAS2781_SA_COEFF_SWAP_REG))
&& ((i + crc_data.offset)
<= (TASDEVICE_PAGE_REG(TAS2781_SA_COEFF_SWAP_REG)
+ 4)))
/*DSP swap command, bypass */
continue;
else
crc_chksum += crc8(tasdevice->crc8_lkp_tbl, &nBuf1[i],
1, 0);
}
ret = crc_chksum;
end:
return ret;
}
static int do_singlereg_checksum(struct tasdevice_priv *tasdevice,
unsigned short chl, unsigned char book, unsigned char page,
unsigned char reg, unsigned char val)
{
struct tas_crc crc_data;
unsigned int nData1;
int ret = 0;
bool in;
if ((book == TASDEVICE_BOOK_ID(TAS2781_SA_COEFF_SWAP_REG))
&& (page == TASDEVICE_PAGE_ID(TAS2781_SA_COEFF_SWAP_REG))
&& (reg >= TASDEVICE_PAGE_REG(TAS2781_SA_COEFF_SWAP_REG))
&& (reg <= (TASDEVICE_PAGE_REG(
TAS2781_SA_COEFF_SWAP_REG) + 4))) {
/*DSP swap command, pass */
ret = 0;
goto end;
}
in = check_yram(&crc_data, book, page, reg, 1);
if (!in)
goto end;
ret = tasdevice_dev_read(tasdevice, chl,
TASDEVICE_REG(book, page, reg), &nData1);
if (ret < 0)
goto end;
if (nData1 != val) {
dev_err(tasdevice->dev,
"B[0x%x]P[0x%x]R[0x%x] W[0x%x], R[0x%x]\n",
book, page, reg, val, nData1);
tasdevice->tasdevice[chl].err_code |= ERROR_YRAM_CRCCHK;
ret = -EAGAIN;
goto end;
}
ret = crc8(tasdevice->crc8_lkp_tbl, &val, 1, 0);
end:
return ret;
}
static void set_err_prg_cfg(unsigned int type, struct tasdevice *dev)
{
if ((type == MAIN_ALL_DEVICES) || (type == MAIN_DEVICE_A)
|| (type == MAIN_DEVICE_B) || (type == MAIN_DEVICE_C)
|| (type == MAIN_DEVICE_D))
dev->cur_prog = -1;
else
dev->cur_conf = -1;
}
static int tasdev_bytes_chksum(struct tasdevice_priv *tas_priv,
struct tasdev_blk *block, int chn, unsigned char book,
unsigned char page, unsigned char reg, unsigned int len,
unsigned char val, unsigned char *crc_chksum)
{
int ret;
if (len > 1)
ret = tasdev_multibytes_chksum(tas_priv, chn, book, page, reg,
len);
else
ret = do_singlereg_checksum(tas_priv, chn, book, page, reg,
val);
if (ret > 0) {
*crc_chksum += (unsigned char)ret;
goto end;
}
if (ret != -EAGAIN)
goto end;
block->nr_retry--;
if (block->nr_retry > 0)
goto end;
set_err_prg_cfg(block->type, &tas_priv->tasdevice[chn]);
end:
return ret;
}
static int tasdev_multibytes_wr(struct tasdevice_priv *tas_priv,
struct tasdev_blk *block, int chn, unsigned char book,
unsigned char page, unsigned char reg, unsigned char *data,
unsigned int len, unsigned int *nr_cmds,
unsigned char *crc_chksum)
{
int ret;
if (len > 1) {
ret = tasdevice_dev_bulk_write(tas_priv, chn,
TASDEVICE_REG(book, page, reg), data + 3, len);
if (ret < 0)
goto end;
if (block->is_ychksum_present)
ret = tasdev_bytes_chksum(tas_priv, block, chn,
book, page, reg, len, 0, crc_chksum);
} else {
ret = tasdevice_dev_write(tas_priv, chn,
TASDEVICE_REG(book, page, reg), data[3]);
if (ret < 0)
goto end;
if (block->is_ychksum_present)
ret = tasdev_bytes_chksum(tas_priv, block, chn, book,
page, reg, 1, data[3], crc_chksum);
}
if (!block->is_ychksum_present || ret >= 0) {
*nr_cmds += 1;
if (len >= 2)
*nr_cmds += ((len - 2) / 4) + 1;
}
end:
return ret;
}
static int tasdev_block_chksum(struct tasdevice_priv *tas_priv,
struct tasdev_blk *block, int chn)
{
unsigned int nr_value;
int ret;
ret = tasdevice_dev_read(tas_priv, chn, TASDEVICE_I2CChecksum,
&nr_value);
if (ret < 0) {
dev_err(tas_priv->dev, "%s: Chn %d\n", __func__, chn);
set_err_prg_cfg(block->type, &tas_priv->tasdevice[chn]);
goto end;
}
if ((nr_value & 0xff) != block->pchksum) {
dev_err(tas_priv->dev, "%s: Blk PChkSum Chn %d ", __func__,
chn);
dev_err(tas_priv->dev, "PChkSum = 0x%x, Reg = 0x%x\n",
block->pchksum, (nr_value & 0xff));
tas_priv->tasdevice[chn].err_code |= ERROR_PRAM_CRCCHK;
ret = -EAGAIN;
block->nr_retry--;
if (block->nr_retry <= 0)
set_err_prg_cfg(block->type,
&tas_priv->tasdevice[chn]);
} else
tas_priv->tasdevice[chn].err_code &= ~ERROR_PRAM_CRCCHK;
end:
return ret;
}
static int tasdev_load_blk(struct tasdevice_priv *tas_priv,
struct tasdev_blk *block, int chn)
{
unsigned int sleep_time;
unsigned int len;
unsigned int nr_cmds;
unsigned char *data = block->data;
unsigned char crc_chksum = 0;
unsigned char offset;
unsigned char book;
unsigned char page;
unsigned char val;
int ret = 0;
while (block->nr_retry > 0) {
if (block->is_pchksum_present) {
ret = tasdevice_dev_write(tas_priv, chn,
TASDEVICE_I2CChecksum, 0);
if (ret < 0)
break;
}
if (block->is_ychksum_present)
crc_chksum = 0;
nr_cmds = 0;
while (nr_cmds < block->nr_cmds) {
data = block->data + nr_cmds * 4;
book = data[0];
page = data[1];
offset = data[2];
val = data[3];
nr_cmds++;
/*Single byte write*/
if (offset <= 0x7F) {
ret = tasdevice_dev_write(tas_priv, chn,
TASDEVICE_REG(book, page, offset),
val);
if (ret < 0)
goto end;
if (block->is_ychksum_present) {
ret = tasdev_bytes_chksum(tas_priv,
block, chn, book, page, offset,
1, val, &crc_chksum);
if (ret < 0)
break;
}
continue;
}
/*sleep command*/
if (offset == 0x81) {
/*book -- data[0] page -- data[1]*/
sleep_time = ((book << 8) + page)*1000;
usleep_range(sleep_time, sleep_time + 50);
continue;
}
/*Multiple bytes write*/
if (offset == 0x85) {
data += 4;
len = (book << 8) + page;
book = data[0];
page = data[1];
offset = data[2];
ret = tasdev_multibytes_wr(tas_priv,
block, chn, book, page, offset, data,
len, &nr_cmds, &crc_chksum);
if (ret < 0)
break;
}
}
if (ret == -EAGAIN) {
if (block->nr_retry > 0)
continue;
} else if (ret < 0) /*err in current device, skip it*/
break;
if (block->is_pchksum_present) {
ret = tasdev_block_chksum(tas_priv, block, chn);
if (ret == -EAGAIN) {
if (block->nr_retry > 0)
continue;
} else if (ret < 0) /*err in current device, skip it*/
break;
}
if (block->is_ychksum_present) {
/* TBD, open it when FW ready */
dev_err(tas_priv->dev,
"Blk YChkSum: FW = 0x%x, YCRC = 0x%x\n",
block->ychksum, crc_chksum);
tas_priv->tasdevice[chn].err_code &=
~ERROR_YRAM_CRCCHK;
ret = 0;
}
/*skip current blk*/
break;
}
end:
return ret;
}
static int tasdevice_load_block(struct tasdevice_priv *tas_priv,
struct tasdev_blk *block)
{
int chnend = 0;
int ret = 0;
int chn = 0;
int rc = 0;
switch (block->type) {
case MAIN_ALL_DEVICES:
chn = 0;
chnend = tas_priv->ndev;
break;
case MAIN_DEVICE_A:
case COEFF_DEVICE_A:
case PRE_DEVICE_A:
chn = 0;
chnend = 1;
break;
case MAIN_DEVICE_B:
case COEFF_DEVICE_B:
case PRE_DEVICE_B:
chn = 1;
chnend = 2;
break;
case MAIN_DEVICE_C:
case COEFF_DEVICE_C:
case PRE_DEVICE_C:
chn = 2;
chnend = 3;
break;
case MAIN_DEVICE_D:
case COEFF_DEVICE_D:
case PRE_DEVICE_D:
chn = 3;
chnend = 4;
break;
default:
dev_dbg(tas_priv->dev, "load blk: Other Type = 0x%02x\n",
block->type);
break;
}
for (; chn < chnend; chn++) {
block->nr_retry = 6;
if (tas_priv->tasdevice[chn].is_loading == false)
continue;
ret = tasdev_load_blk(tas_priv, block, chn);
if (ret < 0)
dev_err(tas_priv->dev, "dev %d, Blk (%d) load error\n",
chn, block->type);
rc |= ret;
}
return rc;
}
static int dspfw_default_callback(struct tasdevice_priv *tas_priv,
unsigned int drv_ver, unsigned int ppcver)
{
int rc = 0;
if (drv_ver == 0x100) {
if (ppcver >= PPC3_VERSION) {
tas_priv->fw_parse_variable_header =
fw_parse_variable_header_kernel;
tas_priv->fw_parse_program_data =
fw_parse_program_data_kernel;
tas_priv->fw_parse_configuration_data =
fw_parse_configuration_data_kernel;
tas_priv->tasdevice_load_block =
tasdevice_load_block_kernel;
} else {
switch (ppcver) {
case 0x00:
tas_priv->fw_parse_variable_header =
fw_parse_variable_header_git;
tas_priv->fw_parse_program_data =
fw_parse_program_data;
tas_priv->fw_parse_configuration_data =
fw_parse_configuration_data;
tas_priv->tasdevice_load_block =
tasdevice_load_block;
break;
default:
dev_err(tas_priv->dev,
"%s: PPCVer must be 0x0 or 0x%02x",
__func__, PPC3_VERSION);
dev_err(tas_priv->dev, " Current:0x%02x\n",
ppcver);
rc = -EINVAL;
break;
}
}
} else {
dev_err(tas_priv->dev,
"DrvVer must be 0x0, 0x230 or above 0x230 ");
dev_err(tas_priv->dev, "current is 0x%02x\n", drv_ver);
rc = -EINVAL;
}
return rc;
}
static int load_calib_data(struct tasdevice_priv *tas_priv,
struct tasdevice_data *dev_data)
{
struct tasdev_blk *block;
unsigned int i;
int ret = 0;
for (i = 0; i < dev_data->nr_blk; i++) {
block = &(dev_data->dev_blks[i]);
ret = tasdevice_load_block(tas_priv, block);
if (ret < 0)
break;
}
return ret;
}
static int fw_parse_header(struct tasdevice_priv *tas_priv,
struct tasdevice_fw *tas_fmw, const struct firmware *fmw, int offset)
{
struct tasdevice_dspfw_hdr *fw_hdr = &(tas_fmw->fw_hdr);
struct tasdevice_fw_fixed_hdr *fw_fixed_hdr = &(fw_hdr->fixed_hdr);
const unsigned char magic_number[] = { 0x35, 0x35, 0x35, 0x32 };
const unsigned char *buf = (unsigned char *)fmw->data;
if (offset + 92 > fmw->size) {
dev_err(tas_priv->dev, "%s: File Size error\n", __func__);
offset = -EINVAL;
goto out;
}
if (memcmp(&buf[offset], magic_number, 4)) {
dev_err(tas_priv->dev, "%s: Magic num NOT match\n", __func__);
offset = -EINVAL;
goto out;
}
offset += 4;
/* Convert data[offset], data[offset + 1], data[offset + 2] and
* data[offset + 3] into host
*/
fw_fixed_hdr->fwsize = be32_to_cpup((__be32 *)&buf[offset]);
offset += 4;
if (fw_fixed_hdr->fwsize != fmw->size) {
dev_err(tas_priv->dev, "File size not match, %lu %u",
(unsigned long)fmw->size, fw_fixed_hdr->fwsize);
offset = -EINVAL;
goto out;
}
offset += 4;
fw_fixed_hdr->ppcver = be32_to_cpup((__be32 *)&buf[offset]);
offset += 8;
fw_fixed_hdr->drv_ver = be32_to_cpup((__be32 *)&buf[offset]);
offset += 72;
out:
return offset;
}
static int fw_parse_variable_hdr_cal(struct tasdevice_priv *tas_priv,
struct tasdevice_fw *tas_fmw, const struct firmware *fmw, int offset)
{
struct tasdevice_dspfw_hdr *fw_hdr = &(tas_fmw->fw_hdr);
offset = fw_parse_variable_hdr(tas_priv, fw_hdr, fmw, offset);
if (offset < 0)
goto out;
if (fw_hdr->ndev != 1) {
dev_err(tas_priv->dev,
"%s: calbin must be 1, but currently ndev(%u)\n",
__func__, fw_hdr->ndev);
offset = -EINVAL;
}
out:
return offset;
}
/* When calibrated data parsing error occurs, DSP can still work with default
* calibrated data, memory resource related to calibrated data will be
* released in the tasdevice_codec_remove.
*/
static int fw_parse_calibration_data(struct tasdevice_priv *tas_priv,
struct tasdevice_fw *tas_fmw, const struct firmware *fmw, int offset)
{
struct tasdevice_calibration *calibration;
unsigned char *data = (unsigned char *)fmw->data;
unsigned int i, n;
if (offset + 2 > fmw->size) {
dev_err(tas_priv->dev, "%s: Calibrations error\n", __func__);
offset = -EINVAL;
goto out;
}
tas_fmw->nr_calibrations = be16_to_cpup((__be16 *)&data[offset]);
offset += 2;
if (tas_fmw->nr_calibrations != 1) {
dev_err(tas_priv->dev,
"%s: only supports one calibration (%d)!\n",
__func__, tas_fmw->nr_calibrations);
goto out;
}
tas_fmw->calibrations = kcalloc(tas_fmw->nr_calibrations,
sizeof(struct tasdevice_calibration), GFP_KERNEL);
if (!tas_fmw->calibrations) {
offset = -ENOMEM;
goto out;
}
for (i = 0; i < tas_fmw->nr_calibrations; i++) {
if (offset + 64 > fmw->size) {
dev_err(tas_priv->dev, "Calibrations error\n");
offset = -EINVAL;
goto out;
}
calibration = &(tas_fmw->calibrations[i]);
offset += 64;
n = strlen((char *)&data[offset]);
/* skip '\0' and 2 unused bytes */
n += 3;
if (offset + n > fmw->size) {
dev_err(tas_priv->dev, "Description err\n");
offset = -EINVAL;
goto out;
}
offset += n;
offset = fw_parse_data(tas_fmw, &(calibration->dev_data), fmw,
offset);
if (offset < 0)
goto out;
}
out:
return offset;
}
int tas2781_load_calibration(void *context, char *file_name,
unsigned short i)
{
struct tasdevice_priv *tas_priv = (struct tasdevice_priv *)context;
struct tasdevice *tasdev = &(tas_priv->tasdevice[i]);
const struct firmware *fw_entry;
struct tasdevice_fw *tas_fmw;
struct firmware fmw;
int offset = 0;
int ret;
ret = request_firmware(&fw_entry, file_name, tas_priv->dev);
if (ret) {
dev_err(tas_priv->dev, "%s: Request firmware %s failed\n",
__func__, file_name);
goto out;
}
if (!fw_entry->size) {
dev_err(tas_priv->dev, "%s: file read error: size = %lu\n",
__func__, (unsigned long)fw_entry->size);
ret = -EINVAL;
goto out;
}
fmw.size = fw_entry->size;
fmw.data = fw_entry->data;
tas_fmw = tasdev->cali_data_fmw = kzalloc(sizeof(struct tasdevice_fw),
GFP_KERNEL);
if (!tasdev->cali_data_fmw) {
ret = -ENOMEM;
goto out;
}
tas_fmw->dev = tas_priv->dev;
offset = fw_parse_header(tas_priv, tas_fmw, &fmw, offset);
if (offset == -EINVAL) {
dev_err(tas_priv->dev, "fw_parse_header EXIT!\n");
ret = offset;
goto out;
}
offset = fw_parse_variable_hdr_cal(tas_priv, tas_fmw, &fmw, offset);
if (offset == -EINVAL) {
dev_err(tas_priv->dev,
"%s: fw_parse_variable_header_cal EXIT!\n", __func__);
ret = offset;
goto out;
}
offset = fw_parse_program_data(tas_priv, tas_fmw, &fmw, offset);
if (offset < 0) {
dev_err(tas_priv->dev, "fw_parse_program_data EXIT!\n");
ret = offset;
goto out;
}
offset = fw_parse_configuration_data(tas_priv, tas_fmw, &fmw, offset);
if (offset < 0) {
dev_err(tas_priv->dev, "fw_parse_configuration_data EXIT!\n");
ret = offset;
goto out;
}
offset = fw_parse_calibration_data(tas_priv, tas_fmw, &fmw, offset);
if (offset < 0) {
dev_err(tas_priv->dev, "fw_parse_calibration_data EXIT!\n");
ret = offset;
goto out;
}
out:
if (fw_entry)
release_firmware(fw_entry);
return ret;
}
EXPORT_SYMBOL_NS_GPL(tas2781_load_calibration, SND_SOC_TAS2781_FMWLIB);
static int tasdevice_dspfw_ready(const struct firmware *fmw,
void *context)
{
struct tasdevice_priv *tas_priv = (struct tasdevice_priv *) context;
struct tasdevice_fw_fixed_hdr *fw_fixed_hdr;
struct tasdevice_fw *tas_fmw;
int offset = 0;
int ret = 0;
if (!fmw || !fmw->data) {
dev_err(tas_priv->dev, "%s: Failed to read firmware %s\n",
__func__, tas_priv->coef_binaryname);
ret = -EINVAL;
goto out;
}
tas_priv->fmw = kzalloc(sizeof(struct tasdevice_fw), GFP_KERNEL);
if (!tas_priv->fmw) {
ret = -ENOMEM;
goto out;
}
tas_fmw = tas_priv->fmw;
tas_fmw->dev = tas_priv->dev;
offset = fw_parse_header(tas_priv, tas_fmw, fmw, offset);
if (offset == -EINVAL) {
ret = -EINVAL;
goto out;
}
fw_fixed_hdr = &(tas_fmw->fw_hdr.fixed_hdr);
/* Support different versions of firmware */
switch (fw_fixed_hdr->drv_ver) {
case 0x301:
case 0x302:
case 0x502:
tas_priv->fw_parse_variable_header =
fw_parse_variable_header_kernel;
tas_priv->fw_parse_program_data =
fw_parse_program_data_kernel;
tas_priv->fw_parse_configuration_data =
fw_parse_configuration_data_kernel;
tas_priv->tasdevice_load_block =
tasdevice_load_block_kernel;
break;
case 0x202:
case 0x400:
tas_priv->fw_parse_variable_header =
fw_parse_variable_header_git;
tas_priv->fw_parse_program_data =
fw_parse_program_data;
tas_priv->fw_parse_configuration_data =
fw_parse_configuration_data;
tas_priv->tasdevice_load_block =
tasdevice_load_block;
break;
default:
ret = dspfw_default_callback(tas_priv,
fw_fixed_hdr->drv_ver, fw_fixed_hdr->ppcver);
if (ret)
goto out;
break;
}
offset = tas_priv->fw_parse_variable_header(tas_priv, fmw, offset);
if (offset < 0) {
ret = offset;
goto out;
}
offset = tas_priv->fw_parse_program_data(tas_priv, tas_fmw, fmw,
offset);
if (offset < 0) {
ret = offset;
goto out;
}
offset = tas_priv->fw_parse_configuration_data(tas_priv,
tas_fmw, fmw, offset);
if (offset < 0)
ret = offset;
out:
return ret;
}
int tasdevice_dsp_parser(void *context)
{
struct tasdevice_priv *tas_priv = (struct tasdevice_priv *)context;
const struct firmware *fw_entry;
int ret;
ret = request_firmware(&fw_entry, tas_priv->coef_binaryname,
tas_priv->dev);
if (ret) {
dev_err(tas_priv->dev, "%s: load %s error\n", __func__,
tas_priv->coef_binaryname);
goto out;
}
ret = tasdevice_dspfw_ready(fw_entry, tas_priv);
release_firmware(fw_entry);
fw_entry = NULL;
out:
return ret;
}
EXPORT_SYMBOL_NS_GPL(tasdevice_dsp_parser, SND_SOC_TAS2781_FMWLIB);
static void tas2781_clear_calfirmware(struct tasdevice_fw *tas_fmw)
{
struct tasdevice_calibration *calibration;
struct tasdev_blk *block;
struct tasdevice_data *im;
unsigned int blks;
int i;
if (!tas_fmw->calibrations)
goto out;
for (i = 0; i < tas_fmw->nr_calibrations; i++) {
calibration = &(tas_fmw->calibrations[i]);
if (!calibration)
continue;
im = &(calibration->dev_data);
if (!im->dev_blks)
continue;
for (blks = 0; blks < im->nr_blk; blks++) {
block = &(im->dev_blks[blks]);
if (!block)
continue;
kfree(block->data);
}
kfree(im->dev_blks);
}
kfree(tas_fmw->calibrations);
out:
kfree(tas_fmw);
}
void tasdevice_calbin_remove(void *context)
{
struct tasdevice_priv *tas_priv = (struct tasdevice_priv *) context;
struct tasdevice *tasdev;
int i;
if (!tas_priv)
return;
for (i = 0; i < tas_priv->ndev; i++) {
tasdev = &(tas_priv->tasdevice[i]);
if (!tasdev->cali_data_fmw)
continue;
tas2781_clear_calfirmware(tasdev->cali_data_fmw);
tasdev->cali_data_fmw = NULL;
}
}
EXPORT_SYMBOL_NS_GPL(tasdevice_calbin_remove, SND_SOC_TAS2781_FMWLIB);
void tasdevice_config_info_remove(void *context)
{
struct tasdevice_priv *tas_priv = (struct tasdevice_priv *) context;
struct tasdevice_rca *rca = &(tas_priv->rcabin);
struct tasdevice_config_info **ci = rca->cfg_info;
int i, j;
if (!ci)
return;
for (i = 0; i < rca->ncfgs; i++) {
if (!ci[i])
continue;
if (ci[i]->blk_data) {
for (j = 0; j < (int)ci[i]->real_nblocks; j++) {
if (!ci[i]->blk_data[j])
continue;
kfree(ci[i]->blk_data[j]->regdata);
kfree(ci[i]->blk_data[j]);
}
kfree(ci[i]->blk_data);
}
kfree(ci[i]);
}
kfree(ci);
}
EXPORT_SYMBOL_NS_GPL(tasdevice_config_info_remove, SND_SOC_TAS2781_FMWLIB);
static int tasdevice_load_data(struct tasdevice_priv *tas_priv,
struct tasdevice_data *dev_data)
{
struct tasdev_blk *block;
unsigned int i;
int ret = 0;
for (i = 0; i < dev_data->nr_blk; i++) {
block = &(dev_data->dev_blks[i]);
ret = tas_priv->tasdevice_load_block(tas_priv, block);
if (ret < 0)
break;
}
return ret;
}
int tasdevice_select_tuningprm_cfg(void *context, int prm_no,
int cfg_no, int rca_conf_no)
{
struct tasdevice_priv *tas_priv = (struct tasdevice_priv *) context;
struct tasdevice_rca *rca = &(tas_priv->rcabin);
struct tasdevice_config_info **cfg_info = rca->cfg_info;
struct tasdevice_fw *tas_fmw = tas_priv->fmw;
struct tasdevice_prog *program;
struct tasdevice_config *conf;
int prog_status = 0;
int status, i;
if (!tas_fmw) {
dev_err(tas_priv->dev, "%s: Firmware is NULL\n", __func__);
goto out;
}
if (cfg_no >= tas_fmw->nr_configurations) {
dev_err(tas_priv->dev,
"%s: cfg(%d) is not in range of conf %u\n",
__func__, cfg_no, tas_fmw->nr_configurations);
goto out;
}
if (prm_no >= tas_fmw->nr_programs) {
dev_err(tas_priv->dev,
"%s: prm(%d) is not in range of Programs %u\n",
__func__, prm_no, tas_fmw->nr_programs);
goto out;
}
if (rca_conf_no >= rca->ncfgs || rca_conf_no < 0 ||
!cfg_info) {
dev_err(tas_priv->dev,
"conf_no:%d should be in range from 0 to %u\n",
rca_conf_no, rca->ncfgs-1);
goto out;
}
conf = &(tas_fmw->configs[cfg_no]);
for (i = 0, prog_status = 0; i < tas_priv->ndev; i++) {
if (cfg_info[rca_conf_no]->active_dev & (1 << i)) {
if (tas_priv->tasdevice[i].cur_prog != prm_no
|| tas_priv->force_fwload_status) {
tas_priv->tasdevice[i].cur_conf = -1;
tas_priv->tasdevice[i].is_loading = true;
prog_status++;
}
} else
tas_priv->tasdevice[i].is_loading = false;
tas_priv->tasdevice[i].is_loaderr = false;
}
if (prog_status) {
program = &(tas_fmw->programs[prm_no]);
tasdevice_load_data(tas_priv, &(program->dev_data));
for (i = 0; i < tas_priv->ndev; i++) {
if (tas_priv->tasdevice[i].is_loaderr == true)
continue;
else if (tas_priv->tasdevice[i].is_loaderr == false
&& tas_priv->tasdevice[i].is_loading == true) {
struct tasdevice_fw *cal_fmw =
tas_priv->tasdevice[i].cali_data_fmw;
if (cal_fmw) {
struct tasdevice_calibration
*cal = cal_fmw->calibrations;
if (cal)
load_calib_data(tas_priv,
&(cal->dev_data));
}
tas_priv->tasdevice[i].cur_prog = prm_no;
}
}
}
for (i = 0, status = 0; i < tas_priv->ndev; i++) {
if (tas_priv->tasdevice[i].cur_conf != cfg_no
&& (cfg_info[rca_conf_no]->active_dev & (1 << i))
&& (tas_priv->tasdevice[i].is_loaderr == false)) {
status++;
tas_priv->tasdevice[i].is_loading = true;
} else
tas_priv->tasdevice[i].is_loading = false;
}
if (status) {
status = 0;
tasdevice_load_data(tas_priv, &(conf->dev_data));
for (i = 0; i < tas_priv->ndev; i++) {
if (tas_priv->tasdevice[i].is_loaderr == true) {
status |= 1 << (i + 4);
continue;
} else if (tas_priv->tasdevice[i].is_loaderr == false
&& tas_priv->tasdevice[i].is_loading == true)
tas_priv->tasdevice[i].cur_conf = cfg_no;
}
} else
dev_dbg(tas_priv->dev, "%s: Unneeded loading dsp conf %d\n",
__func__, cfg_no);
status |= cfg_info[rca_conf_no]->active_dev;
out:
return prog_status;
}
EXPORT_SYMBOL_NS_GPL(tasdevice_select_tuningprm_cfg,
SND_SOC_TAS2781_FMWLIB);
int tasdevice_prmg_load(void *context, int prm_no)
{
struct tasdevice_priv *tas_priv = (struct tasdevice_priv *) context;
struct tasdevice_fw *tas_fmw = tas_priv->fmw;
struct tasdevice_prog *program;
int prog_status = 0;
int i;
if (!tas_fmw) {
dev_err(tas_priv->dev, "%s: Firmware is NULL\n", __func__);
goto out;
}
if (prm_no >= tas_fmw->nr_programs) {
dev_err(tas_priv->dev,
"%s: prm(%d) is not in range of Programs %u\n",
__func__, prm_no, tas_fmw->nr_programs);
goto out;
}
for (i = 0, prog_status = 0; i < tas_priv->ndev; i++) {
if (tas_priv->tasdevice[i].cur_prog != prm_no) {
tas_priv->tasdevice[i].cur_conf = -1;
tas_priv->tasdevice[i].is_loading = true;
prog_status++;
}
}
if (prog_status) {
program = &(tas_fmw->programs[prm_no]);
tasdevice_load_data(tas_priv, &(program->dev_data));
for (i = 0; i < tas_priv->ndev; i++) {
if (tas_priv->tasdevice[i].is_loaderr == true)
continue;
else if (tas_priv->tasdevice[i].is_loaderr == false
&& tas_priv->tasdevice[i].is_loading == true)
tas_priv->tasdevice[i].cur_prog = prm_no;
}
}
out:
return prog_status;
}
EXPORT_SYMBOL_NS_GPL(tasdevice_prmg_load, SND_SOC_TAS2781_FMWLIB);
int tasdevice_prmg_calibdata_load(void *context, int prm_no)
{
struct tasdevice_priv *tas_priv = (struct tasdevice_priv *) context;
struct tasdevice_fw *tas_fmw = tas_priv->fmw;
struct tasdevice_prog *program;
int prog_status = 0;
int i;
if (!tas_fmw) {
dev_err(tas_priv->dev, "%s: Firmware is NULL\n", __func__);
goto out;
}
if (prm_no >= tas_fmw->nr_programs) {
dev_err(tas_priv->dev,
"%s: prm(%d) is not in range of Programs %u\n",
__func__, prm_no, tas_fmw->nr_programs);
goto out;
}
for (i = 0, prog_status = 0; i < tas_priv->ndev; i++) {
if (tas_priv->tasdevice[i].cur_prog != prm_no) {
tas_priv->tasdevice[i].cur_conf = -1;
tas_priv->tasdevice[i].is_loading = true;
prog_status++;
}
tas_priv->tasdevice[i].is_loaderr = false;
}
if (prog_status) {
program = &(tas_fmw->programs[prm_no]);
tasdevice_load_data(tas_priv, &(program->dev_data));
for (i = 0; i < tas_priv->ndev; i++) {
if (tas_priv->tasdevice[i].is_loaderr == true)
continue;
else if (tas_priv->tasdevice[i].is_loaderr == false
&& tas_priv->tasdevice[i].is_loading == true) {
struct tasdevice_fw *cal_fmw =
tas_priv->tasdevice[i].cali_data_fmw;
if (cal_fmw) {
struct tasdevice_calibration *cal =
cal_fmw->calibrations;
if (cal)
load_calib_data(tas_priv,
&(cal->dev_data));
}
tas_priv->tasdevice[i].cur_prog = prm_no;
}
}
}
out:
return prog_status;
}
EXPORT_SYMBOL_NS_GPL(tasdevice_prmg_calibdata_load,
SND_SOC_TAS2781_FMWLIB);
void tasdevice_tuning_switch(void *context, int state)
{
struct tasdevice_priv *tas_priv = (struct tasdevice_priv *) context;
struct tasdevice_fw *tas_fmw = tas_priv->fmw;
int profile_cfg_id = tas_priv->rcabin.profile_cfg_id;
if (tas_priv->fw_state == TASDEVICE_DSP_FW_FAIL) {
dev_err(tas_priv->dev, "DSP bin file not loaded\n");
return;
}
if (state == 0) {
if (tas_priv->cur_prog < tas_fmw->nr_programs) {
/*dsp mode or tuning mode*/
profile_cfg_id = tas_priv->rcabin.profile_cfg_id;
tasdevice_select_tuningprm_cfg(tas_priv,
tas_priv->cur_prog, tas_priv->cur_conf,
profile_cfg_id);
}
tasdevice_select_cfg_blk(tas_priv, profile_cfg_id,
TASDEVICE_BIN_BLK_PRE_POWER_UP);
} else
tasdevice_select_cfg_blk(tas_priv, profile_cfg_id,
TASDEVICE_BIN_BLK_PRE_SHUTDOWN);
}
EXPORT_SYMBOL_NS_GPL(tasdevice_tuning_switch,
SND_SOC_TAS2781_FMWLIB);
MODULE_DESCRIPTION("Texas Firmware Support");
MODULE_AUTHOR("Shenghao Ding, TI, <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/tas2781-fmwlib.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8961.c -- WM8961 ALSA SoC Audio driver
*
* Copyright 2009-10 Wolfson Microelectronics, plc
*
* Author: Mark Brown
*
* Currently unimplemented features:
* - ALC
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "wm8961.h"
#define WM8961_MAX_REGISTER 0xFC
static const struct reg_default wm8961_reg_defaults[] = {
{ 0, 0x009F }, /* R0 - Left Input volume */
{ 1, 0x009F }, /* R1 - Right Input volume */
{ 2, 0x0000 }, /* R2 - LOUT1 volume */
{ 3, 0x0000 }, /* R3 - ROUT1 volume */
{ 4, 0x0020 }, /* R4 - Clocking1 */
{ 5, 0x0008 }, /* R5 - ADC & DAC Control 1 */
{ 6, 0x0000 }, /* R6 - ADC & DAC Control 2 */
{ 7, 0x000A }, /* R7 - Audio Interface 0 */
{ 8, 0x01F4 }, /* R8 - Clocking2 */
{ 9, 0x0000 }, /* R9 - Audio Interface 1 */
{ 10, 0x00FF }, /* R10 - Left DAC volume */
{ 11, 0x00FF }, /* R11 - Right DAC volume */
{ 14, 0x0040 }, /* R14 - Audio Interface 2 */
{ 17, 0x007B }, /* R17 - ALC1 */
{ 18, 0x0000 }, /* R18 - ALC2 */
{ 19, 0x0032 }, /* R19 - ALC3 */
{ 20, 0x0000 }, /* R20 - Noise Gate */
{ 21, 0x00C0 }, /* R21 - Left ADC volume */
{ 22, 0x00C0 }, /* R22 - Right ADC volume */
{ 23, 0x0120 }, /* R23 - Additional control(1) */
{ 24, 0x0000 }, /* R24 - Additional control(2) */
{ 25, 0x0000 }, /* R25 - Pwr Mgmt (1) */
{ 26, 0x0000 }, /* R26 - Pwr Mgmt (2) */
{ 27, 0x0000 }, /* R27 - Additional Control (3) */
{ 28, 0x0000 }, /* R28 - Anti-pop */
{ 30, 0x005F }, /* R30 - Clocking 3 */
{ 32, 0x0000 }, /* R32 - ADCL signal path */
{ 33, 0x0000 }, /* R33 - ADCR signal path */
{ 40, 0x0000 }, /* R40 - LOUT2 volume */
{ 41, 0x0000 }, /* R41 - ROUT2 volume */
{ 47, 0x0000 }, /* R47 - Pwr Mgmt (3) */
{ 48, 0x0023 }, /* R48 - Additional Control (4) */
{ 49, 0x0000 }, /* R49 - Class D Control 1 */
{ 51, 0x0003 }, /* R51 - Class D Control 2 */
{ 56, 0x0106 }, /* R56 - Clocking 4 */
{ 57, 0x0000 }, /* R57 - DSP Sidetone 0 */
{ 58, 0x0000 }, /* R58 - DSP Sidetone 1 */
{ 60, 0x0000 }, /* R60 - DC Servo 0 */
{ 61, 0x0000 }, /* R61 - DC Servo 1 */
{ 63, 0x015E }, /* R63 - DC Servo 3 */
{ 65, 0x0010 }, /* R65 - DC Servo 5 */
{ 68, 0x0003 }, /* R68 - Analogue PGA Bias */
{ 69, 0x0000 }, /* R69 - Analogue HP 0 */
{ 71, 0x01FB }, /* R71 - Analogue HP 2 */
{ 72, 0x0000 }, /* R72 - Charge Pump 1 */
{ 82, 0x0000 }, /* R82 - Charge Pump B */
{ 87, 0x0000 }, /* R87 - Write Sequencer 1 */
{ 88, 0x0000 }, /* R88 - Write Sequencer 2 */
{ 89, 0x0000 }, /* R89 - Write Sequencer 3 */
{ 90, 0x0000 }, /* R90 - Write Sequencer 4 */
{ 91, 0x0000 }, /* R91 - Write Sequencer 5 */
{ 92, 0x0000 }, /* R92 - Write Sequencer 6 */
{ 93, 0x0000 }, /* R93 - Write Sequencer 7 */
{ 252, 0x0001 }, /* R252 - General test 1 */
};
struct wm8961_priv {
struct regmap *regmap;
int sysclk;
};
static bool wm8961_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8961_SOFTWARE_RESET:
case WM8961_WRITE_SEQUENCER_7:
case WM8961_DC_SERVO_1:
return true;
default:
return false;
}
}
static bool wm8961_readable(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8961_LEFT_INPUT_VOLUME:
case WM8961_RIGHT_INPUT_VOLUME:
case WM8961_LOUT1_VOLUME:
case WM8961_ROUT1_VOLUME:
case WM8961_CLOCKING1:
case WM8961_ADC_DAC_CONTROL_1:
case WM8961_ADC_DAC_CONTROL_2:
case WM8961_AUDIO_INTERFACE_0:
case WM8961_CLOCKING2:
case WM8961_AUDIO_INTERFACE_1:
case WM8961_LEFT_DAC_VOLUME:
case WM8961_RIGHT_DAC_VOLUME:
case WM8961_AUDIO_INTERFACE_2:
case WM8961_SOFTWARE_RESET:
case WM8961_ALC1:
case WM8961_ALC2:
case WM8961_ALC3:
case WM8961_NOISE_GATE:
case WM8961_LEFT_ADC_VOLUME:
case WM8961_RIGHT_ADC_VOLUME:
case WM8961_ADDITIONAL_CONTROL_1:
case WM8961_ADDITIONAL_CONTROL_2:
case WM8961_PWR_MGMT_1:
case WM8961_PWR_MGMT_2:
case WM8961_ADDITIONAL_CONTROL_3:
case WM8961_ANTI_POP:
case WM8961_CLOCKING_3:
case WM8961_ADCL_SIGNAL_PATH:
case WM8961_ADCR_SIGNAL_PATH:
case WM8961_LOUT2_VOLUME:
case WM8961_ROUT2_VOLUME:
case WM8961_PWR_MGMT_3:
case WM8961_ADDITIONAL_CONTROL_4:
case WM8961_CLASS_D_CONTROL_1:
case WM8961_CLASS_D_CONTROL_2:
case WM8961_CLOCKING_4:
case WM8961_DSP_SIDETONE_0:
case WM8961_DSP_SIDETONE_1:
case WM8961_DC_SERVO_0:
case WM8961_DC_SERVO_1:
case WM8961_DC_SERVO_3:
case WM8961_DC_SERVO_5:
case WM8961_ANALOGUE_PGA_BIAS:
case WM8961_ANALOGUE_HP_0:
case WM8961_ANALOGUE_HP_2:
case WM8961_CHARGE_PUMP_1:
case WM8961_CHARGE_PUMP_B:
case WM8961_WRITE_SEQUENCER_1:
case WM8961_WRITE_SEQUENCER_2:
case WM8961_WRITE_SEQUENCER_3:
case WM8961_WRITE_SEQUENCER_4:
case WM8961_WRITE_SEQUENCER_5:
case WM8961_WRITE_SEQUENCER_6:
case WM8961_WRITE_SEQUENCER_7:
case WM8961_GENERAL_TEST_1:
return true;
default:
return false;
}
}
/*
* The headphone output supports special anti-pop sequences giving
* silent power up and power down.
*/
static int wm8961_hp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
u16 hp_reg = snd_soc_component_read(component, WM8961_ANALOGUE_HP_0);
u16 cp_reg = snd_soc_component_read(component, WM8961_CHARGE_PUMP_1);
u16 pwr_reg = snd_soc_component_read(component, WM8961_PWR_MGMT_2);
u16 dcs_reg = snd_soc_component_read(component, WM8961_DC_SERVO_1);
int timeout = 500;
if (event & SND_SOC_DAPM_POST_PMU) {
/* Make sure the output is shorted */
hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT);
snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg);
/* Enable the charge pump */
cp_reg |= WM8961_CP_ENA;
snd_soc_component_write(component, WM8961_CHARGE_PUMP_1, cp_reg);
mdelay(5);
/* Enable the PGA */
pwr_reg |= WM8961_LOUT1_PGA | WM8961_ROUT1_PGA;
snd_soc_component_write(component, WM8961_PWR_MGMT_2, pwr_reg);
/* Enable the amplifier */
hp_reg |= WM8961_HPR_ENA | WM8961_HPL_ENA;
snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg);
/* Second stage enable */
hp_reg |= WM8961_HPR_ENA_DLY | WM8961_HPL_ENA_DLY;
snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg);
/* Enable the DC servo & trigger startup */
dcs_reg |=
WM8961_DCS_ENA_CHAN_HPR | WM8961_DCS_TRIG_STARTUP_HPR |
WM8961_DCS_ENA_CHAN_HPL | WM8961_DCS_TRIG_STARTUP_HPL;
dev_dbg(component->dev, "Enabling DC servo\n");
snd_soc_component_write(component, WM8961_DC_SERVO_1, dcs_reg);
do {
msleep(1);
dcs_reg = snd_soc_component_read(component, WM8961_DC_SERVO_1);
} while (--timeout &&
dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR |
WM8961_DCS_TRIG_STARTUP_HPL));
if (dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR |
WM8961_DCS_TRIG_STARTUP_HPL))
dev_err(component->dev, "DC servo timed out\n");
else
dev_dbg(component->dev, "DC servo startup complete\n");
/* Enable the output stage */
hp_reg |= WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP;
snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg);
/* Remove the short on the output stage */
hp_reg |= WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT;
snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg);
}
if (event & SND_SOC_DAPM_PRE_PMD) {
/* Short the output */
hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT);
snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg);
/* Disable the output stage */
hp_reg &= ~(WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP);
snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg);
/* Disable DC offset cancellation */
dcs_reg &= ~(WM8961_DCS_ENA_CHAN_HPR |
WM8961_DCS_ENA_CHAN_HPL);
snd_soc_component_write(component, WM8961_DC_SERVO_1, dcs_reg);
/* Finish up */
hp_reg &= ~(WM8961_HPR_ENA_DLY | WM8961_HPR_ENA |
WM8961_HPL_ENA_DLY | WM8961_HPL_ENA);
snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg);
/* Disable the PGA */
pwr_reg &= ~(WM8961_LOUT1_PGA | WM8961_ROUT1_PGA);
snd_soc_component_write(component, WM8961_PWR_MGMT_2, pwr_reg);
/* Disable the charge pump */
dev_dbg(component->dev, "Disabling charge pump\n");
snd_soc_component_write(component, WM8961_CHARGE_PUMP_1,
cp_reg & ~WM8961_CP_ENA);
}
return 0;
}
static int wm8961_spk_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
u16 pwr_reg = snd_soc_component_read(component, WM8961_PWR_MGMT_2);
u16 spk_reg = snd_soc_component_read(component, WM8961_CLASS_D_CONTROL_1);
if (event & SND_SOC_DAPM_POST_PMU) {
/* Enable the PGA */
pwr_reg |= WM8961_SPKL_PGA | WM8961_SPKR_PGA;
snd_soc_component_write(component, WM8961_PWR_MGMT_2, pwr_reg);
/* Enable the amplifier */
spk_reg |= WM8961_SPKL_ENA | WM8961_SPKR_ENA;
snd_soc_component_write(component, WM8961_CLASS_D_CONTROL_1, spk_reg);
}
if (event & SND_SOC_DAPM_PRE_PMD) {
/* Disable the amplifier */
spk_reg &= ~(WM8961_SPKL_ENA | WM8961_SPKR_ENA);
snd_soc_component_write(component, WM8961_CLASS_D_CONTROL_1, spk_reg);
/* Disable the PGA */
pwr_reg &= ~(WM8961_SPKL_PGA | WM8961_SPKR_PGA);
snd_soc_component_write(component, WM8961_PWR_MGMT_2, pwr_reg);
}
return 0;
}
static const char *adc_hpf_text[] = {
"Hi-fi", "Voice 1", "Voice 2", "Voice 3",
};
static SOC_ENUM_SINGLE_DECL(adc_hpf,
WM8961_ADC_DAC_CONTROL_2, 7, adc_hpf_text);
static const char *dac_deemph_text[] = {
"None", "32kHz", "44.1kHz", "48kHz",
};
static SOC_ENUM_SINGLE_DECL(dac_deemph,
WM8961_ADC_DAC_CONTROL_1, 1, dac_deemph_text);
static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
static const DECLARE_TLV_DB_SCALE(hp_sec_tlv, -700, 100, 0);
static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);
static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
static const DECLARE_TLV_DB_RANGE(boost_tlv,
0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1, 1, TLV_DB_SCALE_ITEM(13, 0, 0),
2, 2, TLV_DB_SCALE_ITEM(20, 0, 0),
3, 3, TLV_DB_SCALE_ITEM(29, 0, 0)
);
static const DECLARE_TLV_DB_SCALE(pga_tlv, -2325, 75, 0);
static const struct snd_kcontrol_new wm8961_snd_controls[] = {
SOC_DOUBLE_R_TLV("Headphone Volume", WM8961_LOUT1_VOLUME, WM8961_ROUT1_VOLUME,
0, 127, 0, out_tlv),
SOC_DOUBLE_TLV("Headphone Secondary Volume", WM8961_ANALOGUE_HP_2,
6, 3, 7, 0, hp_sec_tlv),
SOC_DOUBLE_R("Headphone ZC Switch", WM8961_LOUT1_VOLUME, WM8961_ROUT1_VOLUME,
7, 1, 0),
SOC_DOUBLE_R_TLV("Speaker Volume", WM8961_LOUT2_VOLUME, WM8961_ROUT2_VOLUME,
0, 127, 0, out_tlv),
SOC_DOUBLE_R("Speaker ZC Switch", WM8961_LOUT2_VOLUME, WM8961_ROUT2_VOLUME,
7, 1, 0),
SOC_SINGLE("Speaker AC Gain", WM8961_CLASS_D_CONTROL_2, 0, 7, 0),
SOC_SINGLE("DAC x128 OSR Switch", WM8961_ADC_DAC_CONTROL_2, 0, 1, 0),
SOC_ENUM("DAC Deemphasis", dac_deemph),
SOC_SINGLE("DAC Soft Mute Switch", WM8961_ADC_DAC_CONTROL_2, 3, 1, 0),
SOC_DOUBLE_R_TLV("Sidetone Volume", WM8961_DSP_SIDETONE_0,
WM8961_DSP_SIDETONE_1, 4, 12, 0, sidetone_tlv),
SOC_SINGLE("ADC High Pass Filter Switch", WM8961_ADC_DAC_CONTROL_1, 0, 1, 0),
SOC_ENUM("ADC High Pass Filter Mode", adc_hpf),
SOC_DOUBLE_R_TLV("Capture Volume",
WM8961_LEFT_ADC_VOLUME, WM8961_RIGHT_ADC_VOLUME,
1, 119, 0, adc_tlv),
SOC_DOUBLE_R_TLV("Capture Boost Volume",
WM8961_ADCL_SIGNAL_PATH, WM8961_ADCR_SIGNAL_PATH,
4, 3, 0, boost_tlv),
SOC_DOUBLE_R_TLV("Capture PGA Volume",
WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
0, 62, 0, pga_tlv),
SOC_DOUBLE_R("Capture PGA ZC Switch",
WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
6, 1, 1),
SOC_DOUBLE_R("Capture PGA Switch",
WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
7, 1, 1),
};
static const char *sidetone_text[] = {
"None", "Left", "Right"
};
static SOC_ENUM_SINGLE_DECL(dacl_sidetone,
WM8961_DSP_SIDETONE_0, 2, sidetone_text);
static SOC_ENUM_SINGLE_DECL(dacr_sidetone,
WM8961_DSP_SIDETONE_1, 2, sidetone_text);
static const struct snd_kcontrol_new dacl_mux =
SOC_DAPM_ENUM("DACL Sidetone", dacl_sidetone);
static const struct snd_kcontrol_new dacr_mux =
SOC_DAPM_ENUM("DACR Sidetone", dacr_sidetone);
static const struct snd_soc_dapm_widget wm8961_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("LINPUT"),
SND_SOC_DAPM_INPUT("RINPUT"),
SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8961_CLOCKING2, 4, 0, NULL, 0),
SND_SOC_DAPM_PGA("Left Input", WM8961_PWR_MGMT_1, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Input", WM8961_PWR_MGMT_1, 4, 0, NULL, 0),
SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", WM8961_PWR_MGMT_1, 3, 0),
SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", WM8961_PWR_MGMT_1, 2, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS", WM8961_PWR_MGMT_1, 1, 0, NULL, 0),
SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &dacl_mux),
SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &dacr_mux),
SND_SOC_DAPM_DAC("DACL", "HiFi Playback", WM8961_PWR_MGMT_2, 8, 0),
SND_SOC_DAPM_DAC("DACR", "HiFi Playback", WM8961_PWR_MGMT_2, 7, 0),
/* Handle as a mono path for DCS */
SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM,
4, 0, NULL, 0, wm8961_hp_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA_E("Speaker Output", SND_SOC_NOPM,
4, 0, NULL, 0, wm8961_spk_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_OUTPUT("HP_L"),
SND_SOC_DAPM_OUTPUT("HP_R"),
SND_SOC_DAPM_OUTPUT("SPK_LN"),
SND_SOC_DAPM_OUTPUT("SPK_LP"),
SND_SOC_DAPM_OUTPUT("SPK_RN"),
SND_SOC_DAPM_OUTPUT("SPK_RP"),
};
static const struct snd_soc_dapm_route audio_paths[] = {
{ "DACL", NULL, "CLK_DSP" },
{ "DACL", NULL, "DACL Sidetone" },
{ "DACR", NULL, "CLK_DSP" },
{ "DACR", NULL, "DACR Sidetone" },
{ "DACL Sidetone", "Left", "ADCL" },
{ "DACL Sidetone", "Right", "ADCR" },
{ "DACR Sidetone", "Left", "ADCL" },
{ "DACR Sidetone", "Right", "ADCR" },
{ "HP_L", NULL, "Headphone Output" },
{ "HP_R", NULL, "Headphone Output" },
{ "Headphone Output", NULL, "DACL" },
{ "Headphone Output", NULL, "DACR" },
{ "SPK_LN", NULL, "Speaker Output" },
{ "SPK_LP", NULL, "Speaker Output" },
{ "SPK_RN", NULL, "Speaker Output" },
{ "SPK_RP", NULL, "Speaker Output" },
{ "Speaker Output", NULL, "DACL" },
{ "Speaker Output", NULL, "DACR" },
{ "ADCL", NULL, "Left Input" },
{ "ADCL", NULL, "CLK_DSP" },
{ "ADCR", NULL, "Right Input" },
{ "ADCR", NULL, "CLK_DSP" },
{ "Left Input", NULL, "LINPUT" },
{ "Right Input", NULL, "RINPUT" },
};
/* Values for CLK_SYS_RATE */
static struct {
int ratio;
u16 val;
} wm8961_clk_sys_ratio[] = {
{ 64, 0 },
{ 128, 1 },
{ 192, 2 },
{ 256, 3 },
{ 384, 4 },
{ 512, 5 },
{ 768, 6 },
{ 1024, 7 },
{ 1408, 8 },
{ 1536, 9 },
};
/* Values for SAMPLE_RATE */
static struct {
int rate;
u16 val;
} wm8961_srate[] = {
{ 48000, 0 },
{ 44100, 0 },
{ 32000, 1 },
{ 22050, 2 },
{ 24000, 2 },
{ 16000, 3 },
{ 11250, 4 },
{ 12000, 4 },
{ 8000, 5 },
};
static int wm8961_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm8961_priv *wm8961 = snd_soc_component_get_drvdata(component);
int i, best, target, fs;
u16 reg;
fs = params_rate(params);
if (!wm8961->sysclk) {
dev_err(component->dev, "MCLK has not been specified\n");
return -EINVAL;
}
/* Find the closest sample rate for the filters */
best = 0;
for (i = 0; i < ARRAY_SIZE(wm8961_srate); i++) {
if (abs(wm8961_srate[i].rate - fs) <
abs(wm8961_srate[best].rate - fs))
best = i;
}
reg = snd_soc_component_read(component, WM8961_ADDITIONAL_CONTROL_3);
reg &= ~WM8961_SAMPLE_RATE_MASK;
reg |= wm8961_srate[best].val;
snd_soc_component_write(component, WM8961_ADDITIONAL_CONTROL_3, reg);
dev_dbg(component->dev, "Selected SRATE %dHz for %dHz\n",
wm8961_srate[best].rate, fs);
/* Select a CLK_SYS/fs ratio equal to or higher than required */
target = wm8961->sysclk / fs;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && target < 64) {
dev_err(component->dev,
"SYSCLK must be at least 64*fs for DAC\n");
return -EINVAL;
}
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE && target < 256) {
dev_err(component->dev,
"SYSCLK must be at least 256*fs for ADC\n");
return -EINVAL;
}
for (i = 0; i < ARRAY_SIZE(wm8961_clk_sys_ratio); i++) {
if (wm8961_clk_sys_ratio[i].ratio >= target)
break;
}
if (i == ARRAY_SIZE(wm8961_clk_sys_ratio)) {
dev_err(component->dev, "Unable to generate CLK_SYS_RATE\n");
return -EINVAL;
}
dev_dbg(component->dev, "Selected CLK_SYS_RATE of %d for %d/%d=%d\n",
wm8961_clk_sys_ratio[i].ratio, wm8961->sysclk, fs,
wm8961->sysclk / fs);
reg = snd_soc_component_read(component, WM8961_CLOCKING_4);
reg &= ~WM8961_CLK_SYS_RATE_MASK;
reg |= wm8961_clk_sys_ratio[i].val << WM8961_CLK_SYS_RATE_SHIFT;
snd_soc_component_write(component, WM8961_CLOCKING_4, reg);
reg = snd_soc_component_read(component, WM8961_AUDIO_INTERFACE_0);
reg &= ~WM8961_WL_MASK;
switch (params_width(params)) {
case 16:
break;
case 20:
reg |= 1 << WM8961_WL_SHIFT;
break;
case 24:
reg |= 2 << WM8961_WL_SHIFT;
break;
case 32:
reg |= 3 << WM8961_WL_SHIFT;
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, WM8961_AUDIO_INTERFACE_0, reg);
/* Sloping stop-band filter is recommended for <= 24kHz */
reg = snd_soc_component_read(component, WM8961_ADC_DAC_CONTROL_2);
if (fs <= 24000)
reg |= WM8961_DACSLOPE;
else
reg &= ~WM8961_DACSLOPE;
snd_soc_component_write(component, WM8961_ADC_DAC_CONTROL_2, reg);
return 0;
}
static int wm8961_set_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq,
int dir)
{
struct snd_soc_component *component = dai->component;
struct wm8961_priv *wm8961 = snd_soc_component_get_drvdata(component);
u16 reg = snd_soc_component_read(component, WM8961_CLOCKING1);
if (freq > 33000000) {
dev_err(component->dev, "MCLK must be <33MHz\n");
return -EINVAL;
}
if (freq > 16500000) {
dev_dbg(component->dev, "Using MCLK/2 for %dHz MCLK\n", freq);
reg |= WM8961_MCLKDIV;
freq /= 2;
} else {
dev_dbg(component->dev, "Using MCLK/1 for %dHz MCLK\n", freq);
reg &= ~WM8961_MCLKDIV;
}
snd_soc_component_write(component, WM8961_CLOCKING1, reg);
wm8961->sysclk = freq;
return 0;
}
static int wm8961_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
u16 aif = snd_soc_component_read(component, WM8961_AUDIO_INTERFACE_0);
aif &= ~(WM8961_BCLKINV | WM8961_LRP |
WM8961_MS | WM8961_FORMAT_MASK);
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
aif |= WM8961_MS;
break;
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
aif |= 1;
break;
case SND_SOC_DAIFMT_I2S:
aif |= 2;
break;
case SND_SOC_DAIFMT_DSP_B:
aif |= WM8961_LRP;
fallthrough;
case SND_SOC_DAIFMT_DSP_A:
aif |= 3;
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
case SND_SOC_DAIFMT_IB_NF:
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_NB_IF:
aif |= WM8961_LRP;
break;
case SND_SOC_DAIFMT_IB_NF:
aif |= WM8961_BCLKINV;
break;
case SND_SOC_DAIFMT_IB_IF:
aif |= WM8961_BCLKINV | WM8961_LRP;
break;
default:
return -EINVAL;
}
return snd_soc_component_write(component, WM8961_AUDIO_INTERFACE_0, aif);
}
static int wm8961_set_tristate(struct snd_soc_dai *dai, int tristate)
{
struct snd_soc_component *component = dai->component;
u16 reg = snd_soc_component_read(component, WM8961_ADDITIONAL_CONTROL_2);
if (tristate)
reg |= WM8961_TRIS;
else
reg &= ~WM8961_TRIS;
return snd_soc_component_write(component, WM8961_ADDITIONAL_CONTROL_2, reg);
}
static int wm8961_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
u16 reg = snd_soc_component_read(component, WM8961_ADC_DAC_CONTROL_1);
if (mute)
reg |= WM8961_DACMU;
else
reg &= ~WM8961_DACMU;
msleep(17);
return snd_soc_component_write(component, WM8961_ADC_DAC_CONTROL_1, reg);
}
static int wm8961_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
{
struct snd_soc_component *component = dai->component;
u16 reg;
switch (div_id) {
case WM8961_BCLK:
reg = snd_soc_component_read(component, WM8961_CLOCKING2);
reg &= ~WM8961_BCLKDIV_MASK;
reg |= div;
snd_soc_component_write(component, WM8961_CLOCKING2, reg);
break;
case WM8961_LRCLK:
reg = snd_soc_component_read(component, WM8961_AUDIO_INTERFACE_2);
reg &= ~WM8961_LRCLK_RATE_MASK;
reg |= div;
snd_soc_component_write(component, WM8961_AUDIO_INTERFACE_2, reg);
break;
default:
return -EINVAL;
}
return 0;
}
static int wm8961_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
u16 reg;
/* This is all slightly unusual since we have no bypass paths
* and the output amplifier structure means we can just slam
* the biases straight up rather than having to ramp them
* slowly.
*/
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY) {
/* Enable bias generation */
reg = snd_soc_component_read(component, WM8961_ANTI_POP);
reg |= WM8961_BUFIOEN | WM8961_BUFDCOPEN;
snd_soc_component_write(component, WM8961_ANTI_POP, reg);
/* VMID=2*50k, VREF */
reg = snd_soc_component_read(component, WM8961_PWR_MGMT_1);
reg &= ~WM8961_VMIDSEL_MASK;
reg |= (1 << WM8961_VMIDSEL_SHIFT) | WM8961_VREF;
snd_soc_component_write(component, WM8961_PWR_MGMT_1, reg);
}
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE) {
/* VREF off */
reg = snd_soc_component_read(component, WM8961_PWR_MGMT_1);
reg &= ~WM8961_VREF;
snd_soc_component_write(component, WM8961_PWR_MGMT_1, reg);
/* Bias generation off */
reg = snd_soc_component_read(component, WM8961_ANTI_POP);
reg &= ~(WM8961_BUFIOEN | WM8961_BUFDCOPEN);
snd_soc_component_write(component, WM8961_ANTI_POP, reg);
/* VMID off */
reg = snd_soc_component_read(component, WM8961_PWR_MGMT_1);
reg &= ~WM8961_VMIDSEL_MASK;
snd_soc_component_write(component, WM8961_PWR_MGMT_1, reg);
}
break;
case SND_SOC_BIAS_OFF:
break;
}
return 0;
}
#define WM8961_RATES SNDRV_PCM_RATE_8000_48000
#define WM8961_FORMATS \
(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE)
static const struct snd_soc_dai_ops wm8961_dai_ops = {
.hw_params = wm8961_hw_params,
.set_sysclk = wm8961_set_sysclk,
.set_fmt = wm8961_set_fmt,
.mute_stream = wm8961_mute,
.set_tristate = wm8961_set_tristate,
.set_clkdiv = wm8961_set_clkdiv,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver wm8961_dai = {
.name = "wm8961-hifi",
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM8961_RATES,
.formats = WM8961_FORMATS,},
.capture = {
.stream_name = "HiFi Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM8961_RATES,
.formats = WM8961_FORMATS,},
.ops = &wm8961_dai_ops,
};
static int wm8961_probe(struct snd_soc_component *component)
{
u16 reg;
/* Enable class W */
reg = snd_soc_component_read(component, WM8961_CHARGE_PUMP_B);
reg |= WM8961_CP_DYN_PWR_MASK;
snd_soc_component_write(component, WM8961_CHARGE_PUMP_B, reg);
/* Latch volume update bits (right channel only, we always
* write both out) and default ZC on. */
reg = snd_soc_component_read(component, WM8961_ROUT1_VOLUME);
snd_soc_component_write(component, WM8961_ROUT1_VOLUME,
reg | WM8961_LO1ZC | WM8961_OUT1VU);
snd_soc_component_write(component, WM8961_LOUT1_VOLUME, reg | WM8961_LO1ZC);
reg = snd_soc_component_read(component, WM8961_ROUT2_VOLUME);
snd_soc_component_write(component, WM8961_ROUT2_VOLUME,
reg | WM8961_SPKRZC | WM8961_SPKVU);
snd_soc_component_write(component, WM8961_LOUT2_VOLUME, reg | WM8961_SPKLZC);
reg = snd_soc_component_read(component, WM8961_RIGHT_ADC_VOLUME);
snd_soc_component_write(component, WM8961_RIGHT_ADC_VOLUME, reg | WM8961_ADCVU);
reg = snd_soc_component_read(component, WM8961_RIGHT_INPUT_VOLUME);
snd_soc_component_write(component, WM8961_RIGHT_INPUT_VOLUME, reg | WM8961_IPVU);
/* Use soft mute by default */
reg = snd_soc_component_read(component, WM8961_ADC_DAC_CONTROL_2);
reg |= WM8961_DACSMM;
snd_soc_component_write(component, WM8961_ADC_DAC_CONTROL_2, reg);
/* Use automatic clocking mode by default; for now this is all
* we support.
*/
reg = snd_soc_component_read(component, WM8961_CLOCKING_3);
reg &= ~WM8961_MANUAL_MODE;
snd_soc_component_write(component, WM8961_CLOCKING_3, reg);
return 0;
}
#ifdef CONFIG_PM
static int wm8961_resume(struct snd_soc_component *component)
{
snd_soc_component_cache_sync(component);
return 0;
}
#else
#define wm8961_resume NULL
#endif
static const struct snd_soc_component_driver soc_component_dev_wm8961 = {
.probe = wm8961_probe,
.resume = wm8961_resume,
.set_bias_level = wm8961_set_bias_level,
.controls = wm8961_snd_controls,
.num_controls = ARRAY_SIZE(wm8961_snd_controls),
.dapm_widgets = wm8961_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8961_dapm_widgets),
.dapm_routes = audio_paths,
.num_dapm_routes = ARRAY_SIZE(audio_paths),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config wm8961_regmap = {
.reg_bits = 8,
.val_bits = 16,
.max_register = WM8961_MAX_REGISTER,
.reg_defaults = wm8961_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8961_reg_defaults),
.cache_type = REGCACHE_MAPLE,
.volatile_reg = wm8961_volatile,
.readable_reg = wm8961_readable,
};
static int wm8961_i2c_probe(struct i2c_client *i2c)
{
struct wm8961_priv *wm8961;
unsigned int val;
int ret;
wm8961 = devm_kzalloc(&i2c->dev, sizeof(struct wm8961_priv),
GFP_KERNEL);
if (wm8961 == NULL)
return -ENOMEM;
wm8961->regmap = devm_regmap_init_i2c(i2c, &wm8961_regmap);
if (IS_ERR(wm8961->regmap))
return PTR_ERR(wm8961->regmap);
ret = regmap_read(wm8961->regmap, WM8961_SOFTWARE_RESET, &val);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret);
return ret;
}
if (val != 0x1801) {
dev_err(&i2c->dev, "Device is not a WM8961: ID=0x%x\n", val);
return -EINVAL;
}
/* This isn't volatile - readback doesn't correspond to write */
regcache_cache_bypass(wm8961->regmap, true);
ret = regmap_read(wm8961->regmap, WM8961_RIGHT_INPUT_VOLUME, &val);
regcache_cache_bypass(wm8961->regmap, false);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to read chip revision: %d\n", ret);
return ret;
}
dev_info(&i2c->dev, "WM8961 family %d revision %c\n",
(val & WM8961_DEVICE_ID_MASK) >> WM8961_DEVICE_ID_SHIFT,
((val & WM8961_CHIP_REV_MASK) >> WM8961_CHIP_REV_SHIFT)
+ 'A');
ret = regmap_write(wm8961->regmap, WM8961_SOFTWARE_RESET, 0x1801);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
return ret;
}
i2c_set_clientdata(i2c, wm8961);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_wm8961, &wm8961_dai, 1);
return ret;
}
static const struct i2c_device_id wm8961_i2c_id[] = {
{ "wm8961", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8961_i2c_id);
static const struct of_device_id wm8961_of_match[] __maybe_unused = {
{ .compatible = "wlf,wm8961", },
{ }
};
MODULE_DEVICE_TABLE(of, wm8961_of_match);
static struct i2c_driver wm8961_i2c_driver = {
.driver = {
.name = "wm8961",
.of_match_table = of_match_ptr(wm8961_of_match),
},
.probe = wm8961_i2c_probe,
.id_table = wm8961_i2c_id,
};
module_i2c_driver(wm8961_i2c_driver);
MODULE_DESCRIPTION("ASoC WM8961 driver");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8961.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* alc5632.c -- ALC5632 ALSA SoC Audio Codec
*
* Copyright (C) 2011 The AC100 Kernel Team <[email protected]>
*
* Authors: Leon Romanovsky <[email protected]>
* Andrey Danin <[email protected]>
* Ilya Petrov <[email protected]>
* Marc Dietrich <[email protected]>
*
* Based on alc5623.c by Arnaud Patard
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/tlv.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include "alc5632.h"
/*
* ALC5632 register cache
*/
static const struct reg_default alc5632_reg_defaults[] = {
{ 2, 0x8080 }, /* R2 - Speaker Output Volume */
{ 4, 0x8080 }, /* R4 - Headphone Output Volume */
{ 6, 0x8080 }, /* R6 - AUXOUT Volume */
{ 8, 0xC800 }, /* R8 - Phone Input */
{ 10, 0xE808 }, /* R10 - LINE_IN Volume */
{ 12, 0x1010 }, /* R12 - STEREO DAC Input Volume */
{ 14, 0x0808 }, /* R14 - MIC Input Volume */
{ 16, 0xEE0F }, /* R16 - Stereo DAC and MIC Routing Control */
{ 18, 0xCBCB }, /* R18 - ADC Record Gain */
{ 20, 0x7F7F }, /* R20 - ADC Record Mixer Control */
{ 24, 0xE010 }, /* R24 - Voice DAC Volume */
{ 28, 0x8008 }, /* R28 - Output Mixer Control */
{ 34, 0x0000 }, /* R34 - Microphone Control */
{ 36, 0x00C0 }, /* R36 - Codec Digital MIC/Digital Boost
Control */
{ 46, 0x0000 }, /* R46 - Stereo DAC/Voice DAC/Stereo ADC
Function Select */
{ 52, 0x8000 }, /* R52 - Main Serial Data Port Control
(Stereo I2S) */
{ 54, 0x0000 }, /* R54 - Extend Serial Data Port Control
(VoDAC_I2S/PCM) */
{ 58, 0x0000 }, /* R58 - Power Management Addition 1 */
{ 60, 0x0000 }, /* R60 - Power Management Addition 2 */
{ 62, 0x8000 }, /* R62 - Power Management Addition 3 */
{ 64, 0x0C0A }, /* R64 - General Purpose Control Register 1 */
{ 66, 0x0000 }, /* R66 - General Purpose Control Register 2 */
{ 68, 0x0000 }, /* R68 - PLL1 Control */
{ 70, 0x0000 }, /* R70 - PLL2 Control */
{ 76, 0xBE3E }, /* R76 - GPIO Pin Configuration */
{ 78, 0xBE3E }, /* R78 - GPIO Pin Polarity */
{ 80, 0x0000 }, /* R80 - GPIO Pin Sticky */
{ 82, 0x0000 }, /* R82 - GPIO Pin Wake Up */
{ 86, 0x0000 }, /* R86 - Pin Sharing */
{ 90, 0x0009 }, /* R90 - Soft Volume Control Setting */
{ 92, 0x0000 }, /* R92 - GPIO_Output Pin Control */
{ 94, 0x3000 }, /* R94 - MISC Control */
{ 96, 0x3075 }, /* R96 - Stereo DAC Clock Control_1 */
{ 98, 0x1010 }, /* R98 - Stereo DAC Clock Control_2 */
{ 100, 0x3110 }, /* R100 - VoDAC_PCM Clock Control_1 */
{ 104, 0x0553 }, /* R104 - Pseudo Stereo and Spatial Effect
Block Control */
{ 106, 0x0000 }, /* R106 - Private Register Address */
};
/* codec private data */
struct alc5632_priv {
struct regmap *regmap;
u8 id;
unsigned int sysclk;
};
static bool alc5632_volatile_register(struct device *dev,
unsigned int reg)
{
switch (reg) {
case ALC5632_RESET:
case ALC5632_PWR_DOWN_CTRL_STATUS:
case ALC5632_GPIO_PIN_STATUS:
case ALC5632_OVER_CURR_STATUS:
case ALC5632_HID_CTRL_DATA:
case ALC5632_EQ_CTRL:
case ALC5632_VENDOR_ID1:
case ALC5632_VENDOR_ID2:
return true;
default:
break;
}
return false;
}
static inline int alc5632_reset(struct regmap *map)
{
return regmap_write(map, ALC5632_RESET, 0x59B4);
}
static int amp_mixer_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
/* to power-on/off class-d amp generators/speaker */
/* need to write to 'index-46h' register : */
/* so write index num (here 0x46) to reg 0x6a */
/* and then 0xffff/0 to reg 0x6c */
snd_soc_component_write(component, ALC5632_HID_CTRL_INDEX, 0x46);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_component_write(component, ALC5632_HID_CTRL_DATA, 0xFFFF);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_write(component, ALC5632_HID_CTRL_DATA, 0);
break;
}
return 0;
}
/*
* ALC5632 Controls
*/
/* -34.5db min scale, 1.5db steps, no mute */
static const DECLARE_TLV_DB_SCALE(vol_tlv, -3450, 150, 0);
/* -46.5db min scale, 1.5db steps, no mute */
static const DECLARE_TLV_DB_SCALE(hp_tlv, -4650, 150, 0);
/* -16.5db min scale, 1.5db steps, no mute */
static const DECLARE_TLV_DB_SCALE(adc_rec_tlv, -1650, 150, 0);
static const DECLARE_TLV_DB_RANGE(boost_tlv,
0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0)
);
/* 0db min scale, 6 db steps, no mute */
static const DECLARE_TLV_DB_SCALE(dig_tlv, 0, 600, 0);
/* 0db min scalem 0.75db steps, no mute */
static const DECLARE_TLV_DB_SCALE(vdac_tlv, -3525, 75, 0);
static const struct snd_kcontrol_new alc5632_vol_snd_controls[] = {
/* left starts at bit 8, right at bit 0 */
/* 31 steps (5 bit), -46.5db scale */
SOC_DOUBLE_TLV("Speaker Playback Volume",
ALC5632_SPK_OUT_VOL, 8, 0, 31, 1, hp_tlv),
/* bit 15 mutes left, bit 7 right */
SOC_DOUBLE("Speaker Playback Switch",
ALC5632_SPK_OUT_VOL, 15, 7, 1, 1),
SOC_DOUBLE_TLV("Headphone Playback Volume",
ALC5632_HP_OUT_VOL, 8, 0, 31, 1, hp_tlv),
SOC_DOUBLE("Headphone Playback Switch",
ALC5632_HP_OUT_VOL, 15, 7, 1, 1),
};
static const struct snd_kcontrol_new alc5632_snd_controls[] = {
SOC_DOUBLE_TLV("Auxout Playback Volume",
ALC5632_AUX_OUT_VOL, 8, 0, 31, 1, hp_tlv),
SOC_DOUBLE("Auxout Playback Switch",
ALC5632_AUX_OUT_VOL, 15, 7, 1, 1),
SOC_SINGLE_TLV("Voice DAC Playback Volume",
ALC5632_VOICE_DAC_VOL, 0, 63, 0, vdac_tlv),
SOC_SINGLE("Voice DAC Playback Switch",
ALC5632_VOICE_DAC_VOL, 12, 1, 1),
SOC_SINGLE_TLV("Phone Playback Volume",
ALC5632_PHONE_IN_VOL, 8, 31, 1, vol_tlv),
SOC_DOUBLE_TLV("LineIn Playback Volume",
ALC5632_LINE_IN_VOL, 8, 0, 31, 1, vol_tlv),
SOC_DOUBLE_TLV("Master Playback Volume",
ALC5632_STEREO_DAC_IN_VOL, 8, 0, 63, 1, vdac_tlv),
SOC_DOUBLE("Master Playback Switch",
ALC5632_STEREO_DAC_IN_VOL, 15, 7, 1, 1),
SOC_SINGLE_TLV("Mic1 Playback Volume",
ALC5632_MIC_VOL, 8, 31, 1, vol_tlv),
SOC_SINGLE_TLV("Mic2 Playback Volume",
ALC5632_MIC_VOL, 0, 31, 1, vol_tlv),
SOC_DOUBLE_TLV("Rec Capture Volume",
ALC5632_ADC_REC_GAIN, 8, 0, 31, 0, adc_rec_tlv),
SOC_SINGLE_TLV("Mic 1 Boost Volume",
ALC5632_MIC_CTRL, 10, 3, 0, boost_tlv),
SOC_SINGLE_TLV("Mic 2 Boost Volume",
ALC5632_MIC_CTRL, 8, 3, 0, boost_tlv),
SOC_SINGLE_TLV("DMIC Boost Capture Volume",
ALC5632_DIGI_BOOST_CTRL, 0, 7, 0, dig_tlv),
SOC_SINGLE("DMIC En Capture Switch",
ALC5632_DIGI_BOOST_CTRL, 15, 1, 0),
SOC_SINGLE("DMIC PreFilter Capture Switch",
ALC5632_DIGI_BOOST_CTRL, 12, 1, 0),
};
/*
* DAPM Controls
*/
static const struct snd_kcontrol_new alc5632_hp_mixer_controls[] = {
SOC_DAPM_SINGLE("LI2HP Playback Switch", ALC5632_LINE_IN_VOL, 15, 1, 1),
SOC_DAPM_SINGLE("PHONE2HP Playback Switch", ALC5632_PHONE_IN_VOL, 15, 1, 1),
SOC_DAPM_SINGLE("MIC12HP Playback Switch", ALC5632_MIC_ROUTING_CTRL, 15, 1, 1),
SOC_DAPM_SINGLE("MIC22HP Playback Switch", ALC5632_MIC_ROUTING_CTRL, 11, 1, 1),
SOC_DAPM_SINGLE("VOICE2HP Playback Switch", ALC5632_VOICE_DAC_VOL, 15, 1, 1),
};
static const struct snd_kcontrol_new alc5632_hpl_mixer_controls[] = {
SOC_DAPM_SINGLE("ADC2HP_L Playback Switch", ALC5632_ADC_REC_GAIN, 15, 1, 1),
SOC_DAPM_SINGLE("DACL2HP Playback Switch", ALC5632_MIC_ROUTING_CTRL, 3, 1, 1),
};
static const struct snd_kcontrol_new alc5632_hpr_mixer_controls[] = {
SOC_DAPM_SINGLE("ADC2HP_R Playback Switch", ALC5632_ADC_REC_GAIN, 7, 1, 1),
SOC_DAPM_SINGLE("DACR2HP Playback Switch", ALC5632_MIC_ROUTING_CTRL, 2, 1, 1),
};
static const struct snd_kcontrol_new alc5632_mono_mixer_controls[] = {
SOC_DAPM_SINGLE("ADC2MONO_L Playback Switch", ALC5632_ADC_REC_GAIN, 14, 1, 1),
SOC_DAPM_SINGLE("ADC2MONO_R Playback Switch", ALC5632_ADC_REC_GAIN, 6, 1, 1),
SOC_DAPM_SINGLE("LI2MONO Playback Switch", ALC5632_LINE_IN_VOL, 13, 1, 1),
SOC_DAPM_SINGLE("MIC12MONO Playback Switch",
ALC5632_MIC_ROUTING_CTRL, 13, 1, 1),
SOC_DAPM_SINGLE("MIC22MONO Playback Switch",
ALC5632_MIC_ROUTING_CTRL, 9, 1, 1),
SOC_DAPM_SINGLE("DAC2MONO Playback Switch", ALC5632_MIC_ROUTING_CTRL, 0, 1, 1),
SOC_DAPM_SINGLE("VOICE2MONO Playback Switch", ALC5632_VOICE_DAC_VOL, 13, 1, 1),
};
static const struct snd_kcontrol_new alc5632_speaker_mixer_controls[] = {
SOC_DAPM_SINGLE("LI2SPK Playback Switch", ALC5632_LINE_IN_VOL, 14, 1, 1),
SOC_DAPM_SINGLE("PHONE2SPK Playback Switch", ALC5632_PHONE_IN_VOL, 14, 1, 1),
SOC_DAPM_SINGLE("MIC12SPK Playback Switch",
ALC5632_MIC_ROUTING_CTRL, 14, 1, 1),
SOC_DAPM_SINGLE("MIC22SPK Playback Switch",
ALC5632_MIC_ROUTING_CTRL, 10, 1, 1),
SOC_DAPM_SINGLE("DAC2SPK Playback Switch", ALC5632_MIC_ROUTING_CTRL, 1, 1, 1),
SOC_DAPM_SINGLE("VOICE2SPK Playback Switch", ALC5632_VOICE_DAC_VOL, 14, 1, 1),
};
/* Left Record Mixer */
static const struct snd_kcontrol_new alc5632_captureL_mixer_controls[] = {
SOC_DAPM_SINGLE("MIC12REC_L Capture Switch", ALC5632_ADC_REC_MIXER, 14, 1, 1),
SOC_DAPM_SINGLE("MIC22REC_L Capture Switch", ALC5632_ADC_REC_MIXER, 13, 1, 1),
SOC_DAPM_SINGLE("LIL2REC Capture Switch", ALC5632_ADC_REC_MIXER, 12, 1, 1),
SOC_DAPM_SINGLE("PH2REC_L Capture Switch", ALC5632_ADC_REC_MIXER, 11, 1, 1),
SOC_DAPM_SINGLE("HPL2REC Capture Switch", ALC5632_ADC_REC_MIXER, 10, 1, 1),
SOC_DAPM_SINGLE("SPK2REC_L Capture Switch", ALC5632_ADC_REC_MIXER, 9, 1, 1),
SOC_DAPM_SINGLE("MONO2REC_L Capture Switch", ALC5632_ADC_REC_MIXER, 8, 1, 1),
};
/* Right Record Mixer */
static const struct snd_kcontrol_new alc5632_captureR_mixer_controls[] = {
SOC_DAPM_SINGLE("MIC12REC_R Capture Switch", ALC5632_ADC_REC_MIXER, 6, 1, 1),
SOC_DAPM_SINGLE("MIC22REC_R Capture Switch", ALC5632_ADC_REC_MIXER, 5, 1, 1),
SOC_DAPM_SINGLE("LIR2REC Capture Switch", ALC5632_ADC_REC_MIXER, 4, 1, 1),
SOC_DAPM_SINGLE("PH2REC_R Capture Switch", ALC5632_ADC_REC_MIXER, 3, 1, 1),
SOC_DAPM_SINGLE("HPR2REC Capture Switch", ALC5632_ADC_REC_MIXER, 2, 1, 1),
SOC_DAPM_SINGLE("SPK2REC_R Capture Switch", ALC5632_ADC_REC_MIXER, 1, 1, 1),
SOC_DAPM_SINGLE("MONO2REC_R Capture Switch", ALC5632_ADC_REC_MIXER, 0, 1, 1),
};
/* Dmic Mixer */
static const struct snd_kcontrol_new alc5632_dmicl_mixer_controls[] = {
SOC_DAPM_SINGLE("DMICL2ADC Capture Switch", ALC5632_DIGI_BOOST_CTRL, 7, 1, 1),
};
static const struct snd_kcontrol_new alc5632_dmicr_mixer_controls[] = {
SOC_DAPM_SINGLE("DMICR2ADC Capture Switch", ALC5632_DIGI_BOOST_CTRL, 6, 1, 1),
};
static const char * const alc5632_spk_n_sour_sel[] = {
"RN/-R", "RP/+R", "LN/-R", "Mute"};
static const char * const alc5632_hpl_out_input_sel[] = {
"Vmid", "HP Left Mix"};
static const char * const alc5632_hpr_out_input_sel[] = {
"Vmid", "HP Right Mix"};
static const char * const alc5632_spkout_input_sel[] = {
"Vmid", "HPOut Mix", "Speaker Mix", "Mono Mix"};
static const char * const alc5632_aux_out_input_sel[] = {
"Vmid", "HPOut Mix", "Speaker Mix", "Mono Mix"};
static const char * const alc5632_adcr_func_sel[] = {
"Stereo ADC", "Voice ADC"};
static const char * const alc5632_i2s_out_sel[] = {
"ADC LR", "Voice Stereo Digital"};
/* auxout output mux */
static SOC_ENUM_SINGLE_DECL(alc5632_aux_out_input_enum,
ALC5632_OUTPUT_MIXER_CTRL, 6,
alc5632_aux_out_input_sel);
static const struct snd_kcontrol_new alc5632_auxout_mux_controls =
SOC_DAPM_ENUM("AuxOut Mux", alc5632_aux_out_input_enum);
/* speaker output mux */
static SOC_ENUM_SINGLE_DECL(alc5632_spkout_input_enum,
ALC5632_OUTPUT_MIXER_CTRL, 10,
alc5632_spkout_input_sel);
static const struct snd_kcontrol_new alc5632_spkout_mux_controls =
SOC_DAPM_ENUM("SpeakerOut Mux", alc5632_spkout_input_enum);
/* headphone left output mux */
static SOC_ENUM_SINGLE_DECL(alc5632_hpl_out_input_enum,
ALC5632_OUTPUT_MIXER_CTRL, 9,
alc5632_hpl_out_input_sel);
static const struct snd_kcontrol_new alc5632_hpl_out_mux_controls =
SOC_DAPM_ENUM("Left Headphone Mux", alc5632_hpl_out_input_enum);
/* headphone right output mux */
static SOC_ENUM_SINGLE_DECL(alc5632_hpr_out_input_enum,
ALC5632_OUTPUT_MIXER_CTRL, 8,
alc5632_hpr_out_input_sel);
static const struct snd_kcontrol_new alc5632_hpr_out_mux_controls =
SOC_DAPM_ENUM("Right Headphone Mux", alc5632_hpr_out_input_enum);
/* speaker output N select */
static SOC_ENUM_SINGLE_DECL(alc5632_spk_n_sour_enum,
ALC5632_OUTPUT_MIXER_CTRL, 14,
alc5632_spk_n_sour_sel);
static const struct snd_kcontrol_new alc5632_spkoutn_mux_controls =
SOC_DAPM_ENUM("SpeakerOut N Mux", alc5632_spk_n_sour_enum);
/* speaker amplifier */
static const char *alc5632_amp_names[] = {"AB Amp", "D Amp"};
static SOC_ENUM_SINGLE_DECL(alc5632_amp_enum,
ALC5632_OUTPUT_MIXER_CTRL, 13,
alc5632_amp_names);
static const struct snd_kcontrol_new alc5632_amp_mux_controls =
SOC_DAPM_ENUM("AB-D Amp Mux", alc5632_amp_enum);
/* ADC output select */
static SOC_ENUM_SINGLE_DECL(alc5632_adcr_func_enum,
ALC5632_DAC_FUNC_SELECT, 5,
alc5632_adcr_func_sel);
static const struct snd_kcontrol_new alc5632_adcr_func_controls =
SOC_DAPM_ENUM("ADCR Mux", alc5632_adcr_func_enum);
/* I2S out select */
static SOC_ENUM_SINGLE_DECL(alc5632_i2s_out_enum,
ALC5632_I2S_OUT_CTL, 5,
alc5632_i2s_out_sel);
static const struct snd_kcontrol_new alc5632_i2s_out_controls =
SOC_DAPM_ENUM("I2SOut Mux", alc5632_i2s_out_enum);
static const struct snd_soc_dapm_widget alc5632_dapm_widgets[] = {
/* Muxes */
SND_SOC_DAPM_MUX("AuxOut Mux", SND_SOC_NOPM, 0, 0,
&alc5632_auxout_mux_controls),
SND_SOC_DAPM_MUX("SpeakerOut Mux", SND_SOC_NOPM, 0, 0,
&alc5632_spkout_mux_controls),
SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0,
&alc5632_hpl_out_mux_controls),
SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0,
&alc5632_hpr_out_mux_controls),
SND_SOC_DAPM_MUX("SpeakerOut N Mux", SND_SOC_NOPM, 0, 0,
&alc5632_spkoutn_mux_controls),
SND_SOC_DAPM_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0,
&alc5632_adcr_func_controls),
SND_SOC_DAPM_MUX("I2SOut Mux", ALC5632_PWR_MANAG_ADD1, 11, 0,
&alc5632_i2s_out_controls),
/* output mixers */
SND_SOC_DAPM_MIXER("HP Mix", SND_SOC_NOPM, 0, 0,
&alc5632_hp_mixer_controls[0],
ARRAY_SIZE(alc5632_hp_mixer_controls)),
SND_SOC_DAPM_MIXER("HPR Mix", ALC5632_PWR_MANAG_ADD2, 4, 0,
&alc5632_hpr_mixer_controls[0],
ARRAY_SIZE(alc5632_hpr_mixer_controls)),
SND_SOC_DAPM_MIXER("HPL Mix", ALC5632_PWR_MANAG_ADD2, 5, 0,
&alc5632_hpl_mixer_controls[0],
ARRAY_SIZE(alc5632_hpl_mixer_controls)),
SND_SOC_DAPM_MIXER("HPOut Mix", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Mono Mix", ALC5632_PWR_MANAG_ADD2, 2, 0,
&alc5632_mono_mixer_controls[0],
ARRAY_SIZE(alc5632_mono_mixer_controls)),
SND_SOC_DAPM_MIXER("Speaker Mix", ALC5632_PWR_MANAG_ADD2, 3, 0,
&alc5632_speaker_mixer_controls[0],
ARRAY_SIZE(alc5632_speaker_mixer_controls)),
SND_SOC_DAPM_MIXER("DMICL Mix", SND_SOC_NOPM, 0, 0,
&alc5632_dmicl_mixer_controls[0],
ARRAY_SIZE(alc5632_dmicl_mixer_controls)),
SND_SOC_DAPM_MIXER("DMICR Mix", SND_SOC_NOPM, 0, 0,
&alc5632_dmicr_mixer_controls[0],
ARRAY_SIZE(alc5632_dmicr_mixer_controls)),
/* input mixers */
SND_SOC_DAPM_MIXER("Left Capture Mix", ALC5632_PWR_MANAG_ADD2, 1, 0,
&alc5632_captureL_mixer_controls[0],
ARRAY_SIZE(alc5632_captureL_mixer_controls)),
SND_SOC_DAPM_MIXER("Right Capture Mix", ALC5632_PWR_MANAG_ADD2, 0, 0,
&alc5632_captureR_mixer_controls[0],
ARRAY_SIZE(alc5632_captureR_mixer_controls)),
SND_SOC_DAPM_AIF_IN("AIFRXL", "Left HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIFRXR", "Right HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("VAIFRX", "Voice Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("VAIFTX", "Voice Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("Voice DAC", NULL, ALC5632_PWR_MANAG_ADD2, 10, 0),
SND_SOC_DAPM_DAC("Left DAC", NULL, ALC5632_PWR_MANAG_ADD2, 9, 0),
SND_SOC_DAPM_DAC("Right DAC", NULL, ALC5632_PWR_MANAG_ADD2, 8, 0),
SND_SOC_DAPM_ADC("Left ADC", NULL, ALC5632_PWR_MANAG_ADD2, 7, 0),
SND_SOC_DAPM_ADC("Right ADC", NULL, ALC5632_PWR_MANAG_ADD2, 6, 0),
SND_SOC_DAPM_MIXER("DAC Left Channel", ALC5632_PWR_MANAG_ADD1, 15, 0, NULL, 0),
SND_SOC_DAPM_MIXER("DAC Right Channel",
ALC5632_PWR_MANAG_ADD1, 14, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I2S Mix", ALC5632_PWR_MANAG_ADD1, 11, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Phone Mix", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Line Mix", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Voice Mix", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("ADCLR", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Left Headphone", ALC5632_PWR_MANAG_ADD3, 11, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Headphone", ALC5632_PWR_MANAG_ADD3, 10, 0, NULL, 0),
SND_SOC_DAPM_PGA("Left Speaker", ALC5632_PWR_MANAG_ADD3, 13, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Speaker", ALC5632_PWR_MANAG_ADD3, 12, 0, NULL, 0),
SND_SOC_DAPM_PGA("Aux Out", ALC5632_PWR_MANAG_ADD3, 14, 0, NULL, 0),
SND_SOC_DAPM_PGA("Left LineIn", ALC5632_PWR_MANAG_ADD3, 7, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right LineIn", ALC5632_PWR_MANAG_ADD3, 6, 0, NULL, 0),
SND_SOC_DAPM_PGA("Phone", ALC5632_PWR_MANAG_ADD3, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA("Phone ADMix", ALC5632_PWR_MANAG_ADD3, 4, 0, NULL, 0),
SND_SOC_DAPM_PGA("MIC1 PGA", ALC5632_PWR_MANAG_ADD3, 3, 0, NULL, 0),
SND_SOC_DAPM_PGA("MIC2 PGA", ALC5632_PWR_MANAG_ADD3, 2, 0, NULL, 0),
SND_SOC_DAPM_PGA("MIC1 Pre Amp", ALC5632_PWR_MANAG_ADD3, 1, 0, NULL, 0),
SND_SOC_DAPM_PGA("MIC2 Pre Amp", ALC5632_PWR_MANAG_ADD3, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS1", ALC5632_PWR_MANAG_ADD1, 3, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS2", ALC5632_PWR_MANAG_ADD1, 2, 0, NULL, 0),
SND_SOC_DAPM_PGA_E("D Amp", ALC5632_PWR_MANAG_ADD2, 14, 0, NULL, 0,
amp_mixer_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA("AB Amp", ALC5632_PWR_MANAG_ADD2, 15, 0, NULL, 0),
SND_SOC_DAPM_MUX("AB-D Amp Mux", ALC5632_PWR_MANAG_ADD1, 10, 0,
&alc5632_amp_mux_controls),
SND_SOC_DAPM_OUTPUT("AUXOUT"),
SND_SOC_DAPM_OUTPUT("HPL"),
SND_SOC_DAPM_OUTPUT("HPR"),
SND_SOC_DAPM_OUTPUT("SPKOUT"),
SND_SOC_DAPM_OUTPUT("SPKOUTN"),
SND_SOC_DAPM_INPUT("LINEINL"),
SND_SOC_DAPM_INPUT("LINEINR"),
SND_SOC_DAPM_INPUT("PHONEP"),
SND_SOC_DAPM_INPUT("PHONEN"),
SND_SOC_DAPM_INPUT("DMICDAT"),
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_INPUT("MIC2"),
SND_SOC_DAPM_VMID("Vmid"),
};
static const struct snd_soc_dapm_route alc5632_dapm_routes[] = {
/* Playback streams */
{"Left DAC", NULL, "AIFRXL"},
{"Right DAC", NULL, "AIFRXR"},
/* virtual mixer - mixes left & right channels */
{"I2S Mix", NULL, "Left DAC"},
{"I2S Mix", NULL, "Right DAC"},
{"Line Mix", NULL, "Right LineIn"},
{"Line Mix", NULL, "Left LineIn"},
{"Phone Mix", NULL, "Phone"},
{"Phone Mix", NULL, "Phone ADMix"},
{"AUXOUT", NULL, "Aux Out"},
/* DAC */
{"DAC Right Channel", NULL, "I2S Mix"},
{"DAC Left Channel", NULL, "I2S Mix"},
/* HP mixer */
{"HPL Mix", "ADC2HP_L Playback Switch", "Left Capture Mix"},
{"HPL Mix", NULL, "HP Mix"},
{"HPR Mix", "ADC2HP_R Playback Switch", "Right Capture Mix"},
{"HPR Mix", NULL, "HP Mix"},
{"HP Mix", "LI2HP Playback Switch", "Line Mix"},
{"HP Mix", "PHONE2HP Playback Switch", "Phone Mix"},
{"HP Mix", "MIC12HP Playback Switch", "MIC1 PGA"},
{"HP Mix", "MIC22HP Playback Switch", "MIC2 PGA"},
{"HP Mix", "VOICE2HP Playback Switch", "Voice Mix"},
{"HPR Mix", "DACR2HP Playback Switch", "DAC Right Channel"},
{"HPL Mix", "DACL2HP Playback Switch", "DAC Left Channel"},
{"HPOut Mix", NULL, "HP Mix"},
{"HPOut Mix", NULL, "HPR Mix"},
{"HPOut Mix", NULL, "HPL Mix"},
/* speaker mixer */
{"Speaker Mix", "LI2SPK Playback Switch", "Line Mix"},
{"Speaker Mix", "PHONE2SPK Playback Switch", "Phone Mix"},
{"Speaker Mix", "MIC12SPK Playback Switch", "MIC1 PGA"},
{"Speaker Mix", "MIC22SPK Playback Switch", "MIC2 PGA"},
{"Speaker Mix", "DAC2SPK Playback Switch", "DAC Left Channel"},
{"Speaker Mix", "VOICE2SPK Playback Switch", "Voice Mix"},
/* mono mixer */
{"Mono Mix", "ADC2MONO_L Playback Switch", "Left Capture Mix"},
{"Mono Mix", "ADC2MONO_R Playback Switch", "Right Capture Mix"},
{"Mono Mix", "LI2MONO Playback Switch", "Line Mix"},
{"Mono Mix", "MIC12MONO Playback Switch", "MIC1 PGA"},
{"Mono Mix", "MIC22MONO Playback Switch", "MIC2 PGA"},
{"Mono Mix", "DAC2MONO Playback Switch", "DAC Left Channel"},
{"Mono Mix", "VOICE2MONO Playback Switch", "Voice Mix"},
/* Left record mixer */
{"Left Capture Mix", "LIL2REC Capture Switch", "LINEINL"},
{"Left Capture Mix", "PH2REC_L Capture Switch", "PHONEN"},
{"Left Capture Mix", "MIC12REC_L Capture Switch", "MIC1 Pre Amp"},
{"Left Capture Mix", "MIC22REC_L Capture Switch", "MIC2 Pre Amp"},
{"Left Capture Mix", "HPL2REC Capture Switch", "HPL Mix"},
{"Left Capture Mix", "SPK2REC_L Capture Switch", "Speaker Mix"},
{"Left Capture Mix", "MONO2REC_L Capture Switch", "Mono Mix"},
/*Right record mixer */
{"Right Capture Mix", "LIR2REC Capture Switch", "LINEINR"},
{"Right Capture Mix", "PH2REC_R Capture Switch", "PHONEP"},
{"Right Capture Mix", "MIC12REC_R Capture Switch", "MIC1 Pre Amp"},
{"Right Capture Mix", "MIC22REC_R Capture Switch", "MIC2 Pre Amp"},
{"Right Capture Mix", "HPR2REC Capture Switch", "HPR Mix"},
{"Right Capture Mix", "SPK2REC_R Capture Switch", "Speaker Mix"},
{"Right Capture Mix", "MONO2REC_R Capture Switch", "Mono Mix"},
/* headphone left mux */
{"Left Headphone Mux", "HP Left Mix", "HPL Mix"},
{"Left Headphone Mux", "Vmid", "Vmid"},
/* headphone right mux */
{"Right Headphone Mux", "HP Right Mix", "HPR Mix"},
{"Right Headphone Mux", "Vmid", "Vmid"},
/* speaker out mux */
{"SpeakerOut Mux", "Vmid", "Vmid"},
{"SpeakerOut Mux", "HPOut Mix", "HPOut Mix"},
{"SpeakerOut Mux", "Speaker Mix", "Speaker Mix"},
{"SpeakerOut Mux", "Mono Mix", "Mono Mix"},
/* Mono/Aux Out mux */
{"AuxOut Mux", "Vmid", "Vmid"},
{"AuxOut Mux", "HPOut Mix", "HPOut Mix"},
{"AuxOut Mux", "Speaker Mix", "Speaker Mix"},
{"AuxOut Mux", "Mono Mix", "Mono Mix"},
/* output pga */
{"HPL", NULL, "Left Headphone"},
{"Left Headphone", NULL, "Left Headphone Mux"},
{"HPR", NULL, "Right Headphone"},
{"Right Headphone", NULL, "Right Headphone Mux"},
{"Aux Out", NULL, "AuxOut Mux"},
/* input pga */
{"Left LineIn", NULL, "LINEINL"},
{"Right LineIn", NULL, "LINEINR"},
{"Phone", NULL, "PHONEP"},
{"MIC1 Pre Amp", NULL, "MIC1"},
{"MIC2 Pre Amp", NULL, "MIC2"},
{"MIC1 PGA", NULL, "MIC1 Pre Amp"},
{"MIC2 PGA", NULL, "MIC2 Pre Amp"},
/* left ADC */
{"Left ADC", NULL, "Left Capture Mix"},
{"DMICL Mix", "DMICL2ADC Capture Switch", "DMICDAT"},
{"Left ADC", NULL, "DMICL Mix"},
{"ADCLR", NULL, "Left ADC"},
/* right ADC */
{"Right ADC", NULL, "Right Capture Mix"},
{"DMICR Mix", "DMICR2ADC Capture Switch", "DMICDAT"},
{"Right ADC", NULL, "DMICR Mix"},
{"ADCR Mux", "Stereo ADC", "Right ADC"},
{"ADCR Mux", "Voice ADC", "Right ADC"},
{"ADCLR", NULL, "ADCR Mux"},
{"VAIFTX", NULL, "ADCR Mux"},
/* Digital I2S out */
{"I2SOut Mux", "ADC LR", "ADCLR"},
{"I2SOut Mux", "Voice Stereo Digital", "VAIFRX"},
{"AIFTXL", NULL, "I2SOut Mux"},
{"AIFTXR", NULL, "I2SOut Mux"},
/* Voice Mix */
{"Voice DAC", NULL, "VAIFRX"},
{"Voice Mix", NULL, "Voice DAC"},
/* Speaker Output */
{"SpeakerOut N Mux", "RN/-R", "Left Speaker"},
{"SpeakerOut N Mux", "RP/+R", "Left Speaker"},
{"SpeakerOut N Mux", "LN/-R", "Left Speaker"},
{"SpeakerOut N Mux", "Mute", "Vmid"},
{"SpeakerOut N Mux", "RN/-R", "Right Speaker"},
{"SpeakerOut N Mux", "RP/+R", "Right Speaker"},
{"SpeakerOut N Mux", "LN/-R", "Right Speaker"},
{"SpeakerOut N Mux", "Mute", "Vmid"},
{"AB Amp", NULL, "SpeakerOut Mux"},
{"D Amp", NULL, "SpeakerOut Mux"},
{"AB-D Amp Mux", "AB Amp", "AB Amp"},
{"AB-D Amp Mux", "D Amp", "D Amp"},
{"Left Speaker", NULL, "AB-D Amp Mux"},
{"Right Speaker", NULL, "AB-D Amp Mux"},
{"SPKOUT", NULL, "Left Speaker"},
{"SPKOUT", NULL, "Right Speaker"},
{"SPKOUTN", NULL, "SpeakerOut N Mux"},
};
/* PLL divisors */
struct _pll_div {
u32 pll_in;
u32 pll_out;
u16 regvalue;
};
/* Note : pll code from original alc5632 driver. Not sure of how good it is */
/* useful only for master mode */
static const struct _pll_div codec_master_pll_div[] = {
{ 2048000, 8192000, 0x0ea0},
{ 3686400, 8192000, 0x4e27},
{ 12000000, 8192000, 0x456b},
{ 13000000, 8192000, 0x495f},
{ 13100000, 8192000, 0x0320},
{ 2048000, 11289600, 0xf637},
{ 3686400, 11289600, 0x2f22},
{ 12000000, 11289600, 0x3e2f},
{ 13000000, 11289600, 0x4d5b},
{ 13100000, 11289600, 0x363b},
{ 2048000, 16384000, 0x1ea0},
{ 3686400, 16384000, 0x9e27},
{ 12000000, 16384000, 0x452b},
{ 13000000, 16384000, 0x542f},
{ 13100000, 16384000, 0x03a0},
{ 2048000, 16934400, 0xe625},
{ 3686400, 16934400, 0x9126},
{ 12000000, 16934400, 0x4d2c},
{ 13000000, 16934400, 0x742f},
{ 13100000, 16934400, 0x3c27},
{ 2048000, 22579200, 0x2aa0},
{ 3686400, 22579200, 0x2f20},
{ 12000000, 22579200, 0x7e2f},
{ 13000000, 22579200, 0x742f},
{ 13100000, 22579200, 0x3c27},
{ 2048000, 24576000, 0x2ea0},
{ 3686400, 24576000, 0xee27},
{ 12000000, 24576000, 0x2915},
{ 13000000, 24576000, 0x772e},
{ 13100000, 24576000, 0x0d20},
};
/* FOUT = MCLK*(N+2)/((M+2)*(K+2))
N: bit 15:8 (div 2 .. div 257)
K: bit 6:4 typical 2
M: bit 3:0 (div 2 .. div 17)
same as for 5623 - thanks!
*/
static const struct _pll_div codec_slave_pll_div[] = {
{ 1024000, 16384000, 0x3ea0},
{ 1411200, 22579200, 0x3ea0},
{ 1536000, 24576000, 0x3ea0},
{ 2048000, 16384000, 0x1ea0},
{ 2822400, 22579200, 0x1ea0},
{ 3072000, 24576000, 0x1ea0},
};
static int alc5632_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
int source, unsigned int freq_in, unsigned int freq_out)
{
int i;
struct snd_soc_component *component = codec_dai->component;
int gbl_clk = 0, pll_div = 0;
u16 reg;
if (pll_id < ALC5632_PLL_FR_MCLK || pll_id > ALC5632_PLL_FR_VBCLK)
return -EINVAL;
/* Disable PLL power */
snd_soc_component_update_bits(component, ALC5632_PWR_MANAG_ADD2,
ALC5632_PWR_ADD2_PLL1,
0);
snd_soc_component_update_bits(component, ALC5632_PWR_MANAG_ADD2,
ALC5632_PWR_ADD2_PLL2,
0);
/* pll is not used in slave mode */
reg = snd_soc_component_read(component, ALC5632_DAI_CONTROL);
if (reg & ALC5632_DAI_SDP_SLAVE_MODE)
return 0;
if (!freq_in || !freq_out)
return 0;
switch (pll_id) {
case ALC5632_PLL_FR_MCLK:
for (i = 0; i < ARRAY_SIZE(codec_master_pll_div); i++) {
if (codec_master_pll_div[i].pll_in == freq_in
&& codec_master_pll_div[i].pll_out == freq_out) {
/* PLL source from MCLK */
pll_div = codec_master_pll_div[i].regvalue;
break;
}
}
break;
case ALC5632_PLL_FR_BCLK:
for (i = 0; i < ARRAY_SIZE(codec_slave_pll_div); i++) {
if (codec_slave_pll_div[i].pll_in == freq_in
&& codec_slave_pll_div[i].pll_out == freq_out) {
/* PLL source from Bitclk */
gbl_clk = ALC5632_PLL_FR_BCLK;
pll_div = codec_slave_pll_div[i].regvalue;
break;
}
}
break;
case ALC5632_PLL_FR_VBCLK:
for (i = 0; i < ARRAY_SIZE(codec_slave_pll_div); i++) {
if (codec_slave_pll_div[i].pll_in == freq_in
&& codec_slave_pll_div[i].pll_out == freq_out) {
/* PLL source from voice clock */
gbl_clk = ALC5632_PLL_FR_VBCLK;
pll_div = codec_slave_pll_div[i].regvalue;
break;
}
}
break;
default:
return -EINVAL;
}
if (!pll_div)
return -EINVAL;
/* choose MCLK/BCLK/VBCLK */
snd_soc_component_write(component, ALC5632_GPCR2, gbl_clk);
/* choose PLL1 clock rate */
snd_soc_component_write(component, ALC5632_PLL1_CTRL, pll_div);
/* enable PLL1 */
snd_soc_component_update_bits(component, ALC5632_PWR_MANAG_ADD2,
ALC5632_PWR_ADD2_PLL1,
ALC5632_PWR_ADD2_PLL1);
/* enable PLL2 */
snd_soc_component_update_bits(component, ALC5632_PWR_MANAG_ADD2,
ALC5632_PWR_ADD2_PLL2,
ALC5632_PWR_ADD2_PLL2);
/* use PLL1 as main SYSCLK */
snd_soc_component_update_bits(component, ALC5632_GPCR1,
ALC5632_GPCR1_CLK_SYS_SRC_SEL_PLL1,
ALC5632_GPCR1_CLK_SYS_SRC_SEL_PLL1);
return 0;
}
struct _coeff_div {
u16 fs;
u16 regvalue;
};
/* codec hifi mclk (after PLL) clock divider coefficients */
/* values inspired from column BCLK=32Fs of Appendix A table */
static const struct _coeff_div coeff_div[] = {
{512*1, 0x3075},
};
static int get_coeff(struct snd_soc_component *component, int rate)
{
struct alc5632_priv *alc5632 = snd_soc_component_get_drvdata(component);
int i;
for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
if (coeff_div[i].fs * rate == alc5632->sysclk)
return i;
}
return -EINVAL;
}
/*
* Clock after PLL and dividers
*/
static int alc5632_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct alc5632_priv *alc5632 = snd_soc_component_get_drvdata(component);
switch (freq) {
case 4096000:
case 8192000:
case 11289600:
case 12288000:
case 16384000:
case 16934400:
case 18432000:
case 22579200:
case 24576000:
alc5632->sysclk = freq;
return 0;
}
return -EINVAL;
}
static int alc5632_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
u16 iface = 0;
/* set audio interface clocking */
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
iface = ALC5632_DAI_SDP_MASTER_MODE;
break;
case SND_SOC_DAIFMT_CBC_CFC:
iface = ALC5632_DAI_SDP_SLAVE_MODE;
break;
default:
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface |= ALC5632_DAI_I2S_DF_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
iface |= ALC5632_DAI_I2S_DF_LEFT;
break;
case SND_SOC_DAIFMT_DSP_A:
iface |= ALC5632_DAI_I2S_DF_PCM_A;
break;
case SND_SOC_DAIFMT_DSP_B:
iface |= ALC5632_DAI_I2S_DF_PCM_B;
break;
default:
return -EINVAL;
}
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
iface |= ALC5632_DAI_MAIN_I2S_BCLK_POL_CTRL;
break;
case SND_SOC_DAIFMT_IB_NF:
iface |= ALC5632_DAI_MAIN_I2S_BCLK_POL_CTRL;
break;
case SND_SOC_DAIFMT_NB_IF:
break;
default:
return -EINVAL;
}
return snd_soc_component_write(component, ALC5632_DAI_CONTROL, iface);
}
static int alc5632_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
int coeff, rate;
u16 iface;
iface = snd_soc_component_read(component, ALC5632_DAI_CONTROL);
iface &= ~ALC5632_DAI_I2S_DL_MASK;
/* bit size */
switch (params_width(params)) {
case 16:
iface |= ALC5632_DAI_I2S_DL_16;
break;
case 20:
iface |= ALC5632_DAI_I2S_DL_20;
break;
case 24:
iface |= ALC5632_DAI_I2S_DL_24;
break;
default:
return -EINVAL;
}
/* set iface & srate */
snd_soc_component_write(component, ALC5632_DAI_CONTROL, iface);
rate = params_rate(params);
coeff = get_coeff(component, rate);
if (coeff < 0)
return -EINVAL;
coeff = coeff_div[coeff].regvalue;
snd_soc_component_write(component, ALC5632_DAC_CLK_CTRL1, coeff);
return 0;
}
static int alc5632_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
u16 hp_mute = ALC5632_MISC_HP_DEPOP_MUTE_L
|ALC5632_MISC_HP_DEPOP_MUTE_R;
u16 mute_reg = snd_soc_component_read(component, ALC5632_MISC_CTRL) & ~hp_mute;
if (mute)
mute_reg |= hp_mute;
return snd_soc_component_write(component, ALC5632_MISC_CTRL, mute_reg);
}
#define ALC5632_ADD2_POWER_EN (ALC5632_PWR_ADD2_VREF)
#define ALC5632_ADD3_POWER_EN (ALC5632_PWR_ADD3_MIC1_BOOST_AD)
#define ALC5632_ADD1_POWER_EN \
(ALC5632_PWR_ADD1_DAC_REF \
| ALC5632_PWR_ADD1_SOFTGEN_EN \
| ALC5632_PWR_ADD1_HP_OUT_AMP \
| ALC5632_PWR_ADD1_HP_OUT_ENH_AMP \
| ALC5632_PWR_ADD1_MAIN_BIAS)
static void enable_power_depop(struct snd_soc_component *component)
{
snd_soc_component_update_bits(component, ALC5632_PWR_MANAG_ADD1,
ALC5632_PWR_ADD1_SOFTGEN_EN,
ALC5632_PWR_ADD1_SOFTGEN_EN);
snd_soc_component_update_bits(component, ALC5632_PWR_MANAG_ADD3,
ALC5632_ADD3_POWER_EN,
ALC5632_ADD3_POWER_EN);
snd_soc_component_update_bits(component, ALC5632_MISC_CTRL,
ALC5632_MISC_HP_DEPOP_MODE2_EN,
ALC5632_MISC_HP_DEPOP_MODE2_EN);
/* "normal" mode: 0 @ 26 */
/* set all PR0-7 mixers to 0 */
snd_soc_component_update_bits(component, ALC5632_PWR_DOWN_CTRL_STATUS,
ALC5632_PWR_DOWN_CTRL_STATUS_MASK,
0);
msleep(500);
snd_soc_component_update_bits(component, ALC5632_PWR_MANAG_ADD2,
ALC5632_ADD2_POWER_EN,
ALC5632_ADD2_POWER_EN);
snd_soc_component_update_bits(component, ALC5632_PWR_MANAG_ADD1,
ALC5632_ADD1_POWER_EN,
ALC5632_ADD1_POWER_EN);
/* disable HP Depop2 */
snd_soc_component_update_bits(component, ALC5632_MISC_CTRL,
ALC5632_MISC_HP_DEPOP_MODE2_EN,
0);
}
static int alc5632_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
switch (level) {
case SND_SOC_BIAS_ON:
enable_power_depop(component);
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
/* everything off except vref/vmid, */
snd_soc_component_update_bits(component, ALC5632_PWR_MANAG_ADD1,
ALC5632_PWR_MANAG_ADD1_MASK,
ALC5632_PWR_ADD1_MAIN_BIAS);
snd_soc_component_update_bits(component, ALC5632_PWR_MANAG_ADD2,
ALC5632_PWR_MANAG_ADD2_MASK,
ALC5632_PWR_ADD2_VREF);
/* "normal" mode: 0 @ 26 */
snd_soc_component_update_bits(component, ALC5632_PWR_DOWN_CTRL_STATUS,
ALC5632_PWR_DOWN_CTRL_STATUS_MASK,
0xffff ^ (ALC5632_PWR_VREF_PR3
| ALC5632_PWR_VREF_PR2));
break;
case SND_SOC_BIAS_OFF:
/* everything off, dac mute, inactive */
snd_soc_component_update_bits(component, ALC5632_PWR_MANAG_ADD2,
ALC5632_PWR_MANAG_ADD2_MASK, 0);
snd_soc_component_update_bits(component, ALC5632_PWR_MANAG_ADD3,
ALC5632_PWR_MANAG_ADD3_MASK, 0);
snd_soc_component_update_bits(component, ALC5632_PWR_MANAG_ADD1,
ALC5632_PWR_MANAG_ADD1_MASK, 0);
break;
}
return 0;
}
#define ALC5632_FORMATS (SNDRV_PCM_FMTBIT_S16_LE \
| SNDRV_PCM_FMTBIT_S24_LE \
| SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops alc5632_dai_ops = {
.hw_params = alc5632_pcm_hw_params,
.mute_stream = alc5632_mute,
.set_fmt = alc5632_set_dai_fmt,
.set_sysclk = alc5632_set_dai_sysclk,
.set_pll = alc5632_set_dai_pll,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver alc5632_dai = {
.name = "alc5632-hifi",
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 48000,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = ALC5632_FORMATS,},
.capture = {
.stream_name = "HiFi Capture",
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 48000,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = ALC5632_FORMATS,},
.ops = &alc5632_dai_ops,
.symmetric_rate = 1,
};
#ifdef CONFIG_PM
static int alc5632_resume(struct snd_soc_component *component)
{
struct alc5632_priv *alc5632 = snd_soc_component_get_drvdata(component);
regcache_sync(alc5632->regmap);
return 0;
}
#else
#define alc5632_resume NULL
#endif
static int alc5632_probe(struct snd_soc_component *component)
{
struct alc5632_priv *alc5632 = snd_soc_component_get_drvdata(component);
switch (alc5632->id) {
case 0x5c:
snd_soc_add_component_controls(component, alc5632_vol_snd_controls,
ARRAY_SIZE(alc5632_vol_snd_controls));
break;
default:
return -EINVAL;
}
return 0;
}
static const struct snd_soc_component_driver soc_component_device_alc5632 = {
.probe = alc5632_probe,
.resume = alc5632_resume,
.set_bias_level = alc5632_set_bias_level,
.controls = alc5632_snd_controls,
.num_controls = ARRAY_SIZE(alc5632_snd_controls),
.dapm_widgets = alc5632_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(alc5632_dapm_widgets),
.dapm_routes = alc5632_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(alc5632_dapm_routes),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config alc5632_regmap = {
.reg_bits = 8,
.val_bits = 16,
.max_register = ALC5632_MAX_REGISTER,
.reg_defaults = alc5632_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(alc5632_reg_defaults),
.volatile_reg = alc5632_volatile_register,
.cache_type = REGCACHE_RBTREE,
};
static const struct i2c_device_id alc5632_i2c_table[] = {
{"alc5632", 0x5c},
{}
};
MODULE_DEVICE_TABLE(i2c, alc5632_i2c_table);
/*
* alc5632 2 wire address is determined by A1 pin
* state during powerup.
* low = 0x1a
* high = 0x1b
*/
static int alc5632_i2c_probe(struct i2c_client *client)
{
struct alc5632_priv *alc5632;
int ret, ret1, ret2;
unsigned int vid1, vid2;
const struct i2c_device_id *id;
alc5632 = devm_kzalloc(&client->dev,
sizeof(struct alc5632_priv), GFP_KERNEL);
if (alc5632 == NULL)
return -ENOMEM;
i2c_set_clientdata(client, alc5632);
alc5632->regmap = devm_regmap_init_i2c(client, &alc5632_regmap);
if (IS_ERR(alc5632->regmap)) {
ret = PTR_ERR(alc5632->regmap);
dev_err(&client->dev, "regmap_init() failed: %d\n", ret);
return ret;
}
ret1 = regmap_read(alc5632->regmap, ALC5632_VENDOR_ID1, &vid1);
ret2 = regmap_read(alc5632->regmap, ALC5632_VENDOR_ID2, &vid2);
if (ret1 != 0 || ret2 != 0) {
dev_err(&client->dev,
"Failed to read chip ID: ret1=%d, ret2=%d\n", ret1, ret2);
return -EIO;
}
vid2 >>= 8;
id = i2c_match_id(alc5632_i2c_table, client);
if ((vid1 != 0x10EC) || (vid2 != id->driver_data)) {
dev_err(&client->dev,
"Device is not a ALC5632: VID1=0x%x, VID2=0x%x\n", vid1, vid2);
return -EINVAL;
}
ret = alc5632_reset(alc5632->regmap);
if (ret < 0) {
dev_err(&client->dev, "Failed to issue reset\n");
return ret;
}
alc5632->id = vid2;
switch (alc5632->id) {
case 0x5c:
alc5632_dai.name = "alc5632-hifi";
break;
default:
return -EINVAL;
}
ret = devm_snd_soc_register_component(&client->dev,
&soc_component_device_alc5632, &alc5632_dai, 1);
if (ret < 0) {
dev_err(&client->dev, "Failed to register component: %d\n", ret);
return ret;
}
return ret;
}
#ifdef CONFIG_OF
static const struct of_device_id alc5632_of_match[] = {
{ .compatible = "realtek,alc5632", },
{ }
};
MODULE_DEVICE_TABLE(of, alc5632_of_match);
#endif
/* i2c codec control layer */
static struct i2c_driver alc5632_i2c_driver = {
.driver = {
.name = "alc5632",
.of_match_table = of_match_ptr(alc5632_of_match),
},
.probe = alc5632_i2c_probe,
.id_table = alc5632_i2c_table,
};
module_i2c_driver(alc5632_i2c_driver);
MODULE_DESCRIPTION("ASoC ALC5632 driver");
MODULE_AUTHOR("Leon Romanovsky <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/alc5632.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Driver for the PCM512x CODECs
*
* Author: Mark Brown <[email protected]>
* Copyright 2014 Linaro Ltd
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/kernel.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/gcd.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/pcm_params.h>
#include <sound/tlv.h>
#include "pcm512x.h"
#define PCM512x_NUM_SUPPLIES 3
static const char * const pcm512x_supply_names[PCM512x_NUM_SUPPLIES] = {
"AVDD",
"DVDD",
"CPVDD",
};
struct pcm512x_priv {
struct regmap *regmap;
struct clk *sclk;
struct regulator_bulk_data supplies[PCM512x_NUM_SUPPLIES];
struct notifier_block supply_nb[PCM512x_NUM_SUPPLIES];
int fmt;
int pll_in;
int pll_out;
int pll_r;
int pll_j;
int pll_d;
int pll_p;
unsigned long real_pll;
unsigned long overclock_pll;
unsigned long overclock_dac;
unsigned long overclock_dsp;
int mute;
struct mutex mutex;
unsigned int bclk_ratio;
};
/*
* We can't use the same notifier block for more than one supply and
* there's no way I can see to get from a callback to the caller
* except container_of().
*/
#define PCM512x_REGULATOR_EVENT(n) \
static int pcm512x_regulator_event_##n(struct notifier_block *nb, \
unsigned long event, void *data) \
{ \
struct pcm512x_priv *pcm512x = container_of(nb, struct pcm512x_priv, \
supply_nb[n]); \
if (event & REGULATOR_EVENT_DISABLE) { \
regcache_mark_dirty(pcm512x->regmap); \
regcache_cache_only(pcm512x->regmap, true); \
} \
return 0; \
}
PCM512x_REGULATOR_EVENT(0)
PCM512x_REGULATOR_EVENT(1)
PCM512x_REGULATOR_EVENT(2)
static const struct reg_default pcm512x_reg_defaults[] = {
{ PCM512x_RESET, 0x00 },
{ PCM512x_POWER, 0x00 },
{ PCM512x_MUTE, 0x00 },
{ PCM512x_DSP, 0x00 },
{ PCM512x_PLL_REF, 0x00 },
{ PCM512x_DAC_REF, 0x00 },
{ PCM512x_DAC_ROUTING, 0x11 },
{ PCM512x_DSP_PROGRAM, 0x01 },
{ PCM512x_CLKDET, 0x00 },
{ PCM512x_AUTO_MUTE, 0x00 },
{ PCM512x_ERROR_DETECT, 0x00 },
{ PCM512x_DIGITAL_VOLUME_1, 0x00 },
{ PCM512x_DIGITAL_VOLUME_2, 0x30 },
{ PCM512x_DIGITAL_VOLUME_3, 0x30 },
{ PCM512x_DIGITAL_MUTE_1, 0x22 },
{ PCM512x_DIGITAL_MUTE_2, 0x00 },
{ PCM512x_DIGITAL_MUTE_3, 0x07 },
{ PCM512x_OUTPUT_AMPLITUDE, 0x00 },
{ PCM512x_ANALOG_GAIN_CTRL, 0x00 },
{ PCM512x_UNDERVOLTAGE_PROT, 0x00 },
{ PCM512x_ANALOG_MUTE_CTRL, 0x00 },
{ PCM512x_ANALOG_GAIN_BOOST, 0x00 },
{ PCM512x_VCOM_CTRL_1, 0x00 },
{ PCM512x_VCOM_CTRL_2, 0x01 },
{ PCM512x_BCLK_LRCLK_CFG, 0x00 },
{ PCM512x_MASTER_MODE, 0x7c },
{ PCM512x_GPIO_DACIN, 0x00 },
{ PCM512x_GPIO_PLLIN, 0x00 },
{ PCM512x_SYNCHRONIZE, 0x10 },
{ PCM512x_PLL_COEFF_0, 0x00 },
{ PCM512x_PLL_COEFF_1, 0x00 },
{ PCM512x_PLL_COEFF_2, 0x00 },
{ PCM512x_PLL_COEFF_3, 0x00 },
{ PCM512x_PLL_COEFF_4, 0x00 },
{ PCM512x_DSP_CLKDIV, 0x00 },
{ PCM512x_DAC_CLKDIV, 0x00 },
{ PCM512x_NCP_CLKDIV, 0x00 },
{ PCM512x_OSR_CLKDIV, 0x00 },
{ PCM512x_MASTER_CLKDIV_1, 0x00 },
{ PCM512x_MASTER_CLKDIV_2, 0x00 },
{ PCM512x_FS_SPEED_MODE, 0x00 },
{ PCM512x_IDAC_1, 0x01 },
{ PCM512x_IDAC_2, 0x00 },
{ PCM512x_I2S_1, 0x02 },
{ PCM512x_I2S_2, 0x00 },
};
static bool pcm512x_readable(struct device *dev, unsigned int reg)
{
switch (reg) {
case PCM512x_RESET:
case PCM512x_POWER:
case PCM512x_MUTE:
case PCM512x_PLL_EN:
case PCM512x_SPI_MISO_FUNCTION:
case PCM512x_DSP:
case PCM512x_GPIO_EN:
case PCM512x_BCLK_LRCLK_CFG:
case PCM512x_DSP_GPIO_INPUT:
case PCM512x_MASTER_MODE:
case PCM512x_PLL_REF:
case PCM512x_DAC_REF:
case PCM512x_GPIO_DACIN:
case PCM512x_GPIO_PLLIN:
case PCM512x_SYNCHRONIZE:
case PCM512x_PLL_COEFF_0:
case PCM512x_PLL_COEFF_1:
case PCM512x_PLL_COEFF_2:
case PCM512x_PLL_COEFF_3:
case PCM512x_PLL_COEFF_4:
case PCM512x_DSP_CLKDIV:
case PCM512x_DAC_CLKDIV:
case PCM512x_NCP_CLKDIV:
case PCM512x_OSR_CLKDIV:
case PCM512x_MASTER_CLKDIV_1:
case PCM512x_MASTER_CLKDIV_2:
case PCM512x_FS_SPEED_MODE:
case PCM512x_IDAC_1:
case PCM512x_IDAC_2:
case PCM512x_ERROR_DETECT:
case PCM512x_I2S_1:
case PCM512x_I2S_2:
case PCM512x_DAC_ROUTING:
case PCM512x_DSP_PROGRAM:
case PCM512x_CLKDET:
case PCM512x_AUTO_MUTE:
case PCM512x_DIGITAL_VOLUME_1:
case PCM512x_DIGITAL_VOLUME_2:
case PCM512x_DIGITAL_VOLUME_3:
case PCM512x_DIGITAL_MUTE_1:
case PCM512x_DIGITAL_MUTE_2:
case PCM512x_DIGITAL_MUTE_3:
case PCM512x_GPIO_OUTPUT_1:
case PCM512x_GPIO_OUTPUT_2:
case PCM512x_GPIO_OUTPUT_3:
case PCM512x_GPIO_OUTPUT_4:
case PCM512x_GPIO_OUTPUT_5:
case PCM512x_GPIO_OUTPUT_6:
case PCM512x_GPIO_CONTROL_1:
case PCM512x_GPIO_CONTROL_2:
case PCM512x_OVERFLOW:
case PCM512x_RATE_DET_1:
case PCM512x_RATE_DET_2:
case PCM512x_RATE_DET_3:
case PCM512x_RATE_DET_4:
case PCM512x_CLOCK_STATUS:
case PCM512x_ANALOG_MUTE_DET:
case PCM512x_GPIN:
case PCM512x_DIGITAL_MUTE_DET:
case PCM512x_OUTPUT_AMPLITUDE:
case PCM512x_ANALOG_GAIN_CTRL:
case PCM512x_UNDERVOLTAGE_PROT:
case PCM512x_ANALOG_MUTE_CTRL:
case PCM512x_ANALOG_GAIN_BOOST:
case PCM512x_VCOM_CTRL_1:
case PCM512x_VCOM_CTRL_2:
case PCM512x_CRAM_CTRL:
case PCM512x_FLEX_A:
case PCM512x_FLEX_B:
return true;
default:
/* There are 256 raw register addresses */
return reg < 0xff;
}
}
static bool pcm512x_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case PCM512x_PLL_EN:
case PCM512x_OVERFLOW:
case PCM512x_RATE_DET_1:
case PCM512x_RATE_DET_2:
case PCM512x_RATE_DET_3:
case PCM512x_RATE_DET_4:
case PCM512x_CLOCK_STATUS:
case PCM512x_ANALOG_MUTE_DET:
case PCM512x_GPIN:
case PCM512x_DIGITAL_MUTE_DET:
case PCM512x_CRAM_CTRL:
return true;
default:
/* There are 256 raw register addresses */
return reg < 0xff;
}
}
static int pcm512x_overclock_pll_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = pcm512x->overclock_pll;
return 0;
}
static int pcm512x_overclock_pll_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
switch (snd_soc_component_get_bias_level(component)) {
case SND_SOC_BIAS_OFF:
case SND_SOC_BIAS_STANDBY:
break;
default:
return -EBUSY;
}
pcm512x->overclock_pll = ucontrol->value.integer.value[0];
return 0;
}
static int pcm512x_overclock_dsp_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = pcm512x->overclock_dsp;
return 0;
}
static int pcm512x_overclock_dsp_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
switch (snd_soc_component_get_bias_level(component)) {
case SND_SOC_BIAS_OFF:
case SND_SOC_BIAS_STANDBY:
break;
default:
return -EBUSY;
}
pcm512x->overclock_dsp = ucontrol->value.integer.value[0];
return 0;
}
static int pcm512x_overclock_dac_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = pcm512x->overclock_dac;
return 0;
}
static int pcm512x_overclock_dac_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
switch (snd_soc_component_get_bias_level(component)) {
case SND_SOC_BIAS_OFF:
case SND_SOC_BIAS_STANDBY:
break;
default:
return -EBUSY;
}
pcm512x->overclock_dac = ucontrol->value.integer.value[0];
return 0;
}
static const DECLARE_TLV_DB_SCALE(digital_tlv, -10350, 50, 1);
static const DECLARE_TLV_DB_SCALE(analog_tlv, -600, 600, 0);
static const DECLARE_TLV_DB_SCALE(boost_tlv, 0, 80, 0);
static const char * const pcm512x_dsp_program_texts[] = {
"FIR interpolation with de-emphasis",
"Low latency IIR with de-emphasis",
"High attenuation with de-emphasis",
"Fixed process flow",
"Ringing-less low latency FIR",
};
static const unsigned int pcm512x_dsp_program_values[] = {
1,
2,
3,
5,
7,
};
static SOC_VALUE_ENUM_SINGLE_DECL(pcm512x_dsp_program,
PCM512x_DSP_PROGRAM, 0, 0x1f,
pcm512x_dsp_program_texts,
pcm512x_dsp_program_values);
static const char * const pcm512x_clk_missing_text[] = {
"1s", "2s", "3s", "4s", "5s", "6s", "7s", "8s"
};
static const struct soc_enum pcm512x_clk_missing =
SOC_ENUM_SINGLE(PCM512x_CLKDET, 0, 8, pcm512x_clk_missing_text);
static const char * const pcm512x_autom_text[] = {
"21ms", "106ms", "213ms", "533ms", "1.07s", "2.13s", "5.33s", "10.66s"
};
static const struct soc_enum pcm512x_autom_l =
SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATML_SHIFT, 8,
pcm512x_autom_text);
static const struct soc_enum pcm512x_autom_r =
SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATMR_SHIFT, 8,
pcm512x_autom_text);
static const char * const pcm512x_ramp_rate_text[] = {
"1 sample/update", "2 samples/update", "4 samples/update",
"Immediate"
};
static const struct soc_enum pcm512x_vndf =
SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDF_SHIFT, 4,
pcm512x_ramp_rate_text);
static const struct soc_enum pcm512x_vnuf =
SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUF_SHIFT, 4,
pcm512x_ramp_rate_text);
static const struct soc_enum pcm512x_vedf =
SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDF_SHIFT, 4,
pcm512x_ramp_rate_text);
static const char * const pcm512x_ramp_step_text[] = {
"4dB/step", "2dB/step", "1dB/step", "0.5dB/step"
};
static const struct soc_enum pcm512x_vnds =
SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDS_SHIFT, 4,
pcm512x_ramp_step_text);
static const struct soc_enum pcm512x_vnus =
SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUS_SHIFT, 4,
pcm512x_ramp_step_text);
static const struct soc_enum pcm512x_veds =
SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDS_SHIFT, 4,
pcm512x_ramp_step_text);
static int pcm512x_update_mute(struct pcm512x_priv *pcm512x)
{
return regmap_update_bits(
pcm512x->regmap, PCM512x_MUTE, PCM512x_RQML | PCM512x_RQMR,
(!!(pcm512x->mute & 0x5) << PCM512x_RQML_SHIFT)
| (!!(pcm512x->mute & 0x3) << PCM512x_RQMR_SHIFT));
}
static int pcm512x_digital_playback_switch_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
mutex_lock(&pcm512x->mutex);
ucontrol->value.integer.value[0] = !(pcm512x->mute & 0x4);
ucontrol->value.integer.value[1] = !(pcm512x->mute & 0x2);
mutex_unlock(&pcm512x->mutex);
return 0;
}
static int pcm512x_digital_playback_switch_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
int ret, changed = 0;
mutex_lock(&pcm512x->mutex);
if ((pcm512x->mute & 0x4) == (ucontrol->value.integer.value[0] << 2)) {
pcm512x->mute ^= 0x4;
changed = 1;
}
if ((pcm512x->mute & 0x2) == (ucontrol->value.integer.value[1] << 1)) {
pcm512x->mute ^= 0x2;
changed = 1;
}
if (changed) {
ret = pcm512x_update_mute(pcm512x);
if (ret != 0) {
dev_err(component->dev,
"Failed to update digital mute: %d\n", ret);
mutex_unlock(&pcm512x->mutex);
return ret;
}
}
mutex_unlock(&pcm512x->mutex);
return changed;
}
static const struct snd_kcontrol_new pcm512x_controls[] = {
SOC_DOUBLE_R_TLV("Digital Playback Volume", PCM512x_DIGITAL_VOLUME_2,
PCM512x_DIGITAL_VOLUME_3, 0, 255, 1, digital_tlv),
SOC_DOUBLE_TLV("Analogue Playback Volume", PCM512x_ANALOG_GAIN_CTRL,
PCM512x_LAGN_SHIFT, PCM512x_RAGN_SHIFT, 1, 1, analog_tlv),
SOC_DOUBLE_TLV("Analogue Playback Boost Volume", PCM512x_ANALOG_GAIN_BOOST,
PCM512x_AGBL_SHIFT, PCM512x_AGBR_SHIFT, 1, 0, boost_tlv),
{
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "Digital Playback Switch",
.index = 0,
.access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
.info = snd_ctl_boolean_stereo_info,
.get = pcm512x_digital_playback_switch_get,
.put = pcm512x_digital_playback_switch_put
},
SOC_SINGLE("Deemphasis Switch", PCM512x_DSP, PCM512x_DEMP_SHIFT, 1, 1),
SOC_ENUM("DSP Program", pcm512x_dsp_program),
SOC_ENUM("Clock Missing Period", pcm512x_clk_missing),
SOC_ENUM("Auto Mute Time Left", pcm512x_autom_l),
SOC_ENUM("Auto Mute Time Right", pcm512x_autom_r),
SOC_SINGLE("Auto Mute Mono Switch", PCM512x_DIGITAL_MUTE_3,
PCM512x_ACTL_SHIFT, 1, 0),
SOC_DOUBLE("Auto Mute Switch", PCM512x_DIGITAL_MUTE_3, PCM512x_AMLE_SHIFT,
PCM512x_AMRE_SHIFT, 1, 0),
SOC_ENUM("Volume Ramp Down Rate", pcm512x_vndf),
SOC_ENUM("Volume Ramp Down Step", pcm512x_vnds),
SOC_ENUM("Volume Ramp Up Rate", pcm512x_vnuf),
SOC_ENUM("Volume Ramp Up Step", pcm512x_vnus),
SOC_ENUM("Volume Ramp Down Emergency Rate", pcm512x_vedf),
SOC_ENUM("Volume Ramp Down Emergency Step", pcm512x_veds),
SOC_SINGLE_EXT("Max Overclock PLL", SND_SOC_NOPM, 0, 20, 0,
pcm512x_overclock_pll_get, pcm512x_overclock_pll_put),
SOC_SINGLE_EXT("Max Overclock DSP", SND_SOC_NOPM, 0, 40, 0,
pcm512x_overclock_dsp_get, pcm512x_overclock_dsp_put),
SOC_SINGLE_EXT("Max Overclock DAC", SND_SOC_NOPM, 0, 40, 0,
pcm512x_overclock_dac_get, pcm512x_overclock_dac_put),
};
static const struct snd_soc_dapm_widget pcm512x_dapm_widgets[] = {
SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_OUTPUT("OUTL"),
SND_SOC_DAPM_OUTPUT("OUTR"),
};
static const struct snd_soc_dapm_route pcm512x_dapm_routes[] = {
{ "DACL", NULL, "Playback" },
{ "DACR", NULL, "Playback" },
{ "OUTL", NULL, "DACL" },
{ "OUTR", NULL, "DACR" },
};
static unsigned long pcm512x_pll_max(struct pcm512x_priv *pcm512x)
{
return 25000000 + 25000000 * pcm512x->overclock_pll / 100;
}
static unsigned long pcm512x_dsp_max(struct pcm512x_priv *pcm512x)
{
return 50000000 + 50000000 * pcm512x->overclock_dsp / 100;
}
static unsigned long pcm512x_dac_max(struct pcm512x_priv *pcm512x,
unsigned long rate)
{
return rate + rate * pcm512x->overclock_dac / 100;
}
static unsigned long pcm512x_sck_max(struct pcm512x_priv *pcm512x)
{
if (!pcm512x->pll_out)
return 25000000;
return pcm512x_pll_max(pcm512x);
}
static unsigned long pcm512x_ncp_target(struct pcm512x_priv *pcm512x,
unsigned long dac_rate)
{
/*
* If the DAC is not actually overclocked, use the good old
* NCP target rate...
*/
if (dac_rate <= 6144000)
return 1536000;
/*
* ...but if the DAC is in fact overclocked, bump the NCP target
* rate to get the recommended dividers even when overclocking.
*/
return pcm512x_dac_max(pcm512x, 1536000);
}
static const u32 pcm512x_dai_rates[] = {
8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
88200, 96000, 176400, 192000, 384000,
};
static const struct snd_pcm_hw_constraint_list constraints_slave = {
.count = ARRAY_SIZE(pcm512x_dai_rates),
.list = pcm512x_dai_rates,
};
static int pcm512x_hw_rule_rate(struct snd_pcm_hw_params *params,
struct snd_pcm_hw_rule *rule)
{
struct pcm512x_priv *pcm512x = rule->private;
struct snd_interval ranges[2];
int frame_size;
frame_size = snd_soc_params_to_frame_size(params);
if (frame_size < 0)
return frame_size;
switch (frame_size) {
case 32:
/* No hole when the frame size is 32. */
return 0;
case 48:
case 64:
/* There is only one hole in the range of supported
* rates, but it moves with the frame size.
*/
memset(ranges, 0, sizeof(ranges));
ranges[0].min = 8000;
ranges[0].max = pcm512x_sck_max(pcm512x) / frame_size / 2;
ranges[1].min = DIV_ROUND_UP(16000000, frame_size);
ranges[1].max = 384000;
break;
default:
return -EINVAL;
}
return snd_interval_ranges(hw_param_interval(params, rule->var),
ARRAY_SIZE(ranges), ranges, 0);
}
static int pcm512x_dai_startup_master(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
struct device *dev = dai->dev;
struct snd_pcm_hw_constraint_ratnums *constraints_no_pll;
struct snd_ratnum *rats_no_pll;
if (IS_ERR(pcm512x->sclk)) {
dev_err(dev, "Need SCLK for master mode: %ld\n",
PTR_ERR(pcm512x->sclk));
return PTR_ERR(pcm512x->sclk);
}
if (pcm512x->pll_out)
return snd_pcm_hw_rule_add(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
pcm512x_hw_rule_rate,
pcm512x,
SNDRV_PCM_HW_PARAM_FRAME_BITS,
SNDRV_PCM_HW_PARAM_CHANNELS, -1);
constraints_no_pll = devm_kzalloc(dev, sizeof(*constraints_no_pll),
GFP_KERNEL);
if (!constraints_no_pll)
return -ENOMEM;
constraints_no_pll->nrats = 1;
rats_no_pll = devm_kzalloc(dev, sizeof(*rats_no_pll), GFP_KERNEL);
if (!rats_no_pll)
return -ENOMEM;
constraints_no_pll->rats = rats_no_pll;
rats_no_pll->num = clk_get_rate(pcm512x->sclk) / 64;
rats_no_pll->den_min = 1;
rats_no_pll->den_max = 128;
rats_no_pll->den_step = 1;
return snd_pcm_hw_constraint_ratnums(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
constraints_no_pll);
}
static int pcm512x_dai_startup_slave(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
struct device *dev = dai->dev;
struct regmap *regmap = pcm512x->regmap;
if (IS_ERR(pcm512x->sclk)) {
dev_info(dev, "No SCLK, using BCLK: %ld\n",
PTR_ERR(pcm512x->sclk));
/* Disable reporting of missing SCLK as an error */
regmap_update_bits(regmap, PCM512x_ERROR_DETECT,
PCM512x_IDCH, PCM512x_IDCH);
/* Switch PLL input to BCLK */
regmap_update_bits(regmap, PCM512x_PLL_REF,
PCM512x_SREF, PCM512x_SREF_BCK);
}
return snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&constraints_slave);
}
static int pcm512x_dai_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
switch (pcm512x->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
case SND_SOC_DAIFMT_CBP_CFC:
return pcm512x_dai_startup_master(substream, dai);
case SND_SOC_DAIFMT_CBC_CFC:
return pcm512x_dai_startup_slave(substream, dai);
default:
return -EINVAL;
}
}
static int pcm512x_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct pcm512x_priv *pcm512x = dev_get_drvdata(component->dev);
int ret;
switch (level) {
case SND_SOC_BIAS_ON:
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
PCM512x_RQST, 0);
if (ret != 0) {
dev_err(component->dev, "Failed to remove standby: %d\n",
ret);
return ret;
}
break;
case SND_SOC_BIAS_OFF:
ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
PCM512x_RQST, PCM512x_RQST);
if (ret != 0) {
dev_err(component->dev, "Failed to request standby: %d\n",
ret);
return ret;
}
break;
}
return 0;
}
static unsigned long pcm512x_find_sck(struct snd_soc_dai *dai,
unsigned long bclk_rate)
{
struct device *dev = dai->dev;
struct snd_soc_component *component = dai->component;
struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
unsigned long sck_rate;
int pow2;
/* 64 MHz <= pll_rate <= 100 MHz, VREF mode */
/* 16 MHz <= sck_rate <= 25 MHz, VREF mode */
/* select sck_rate as a multiple of bclk_rate but still with
* as many factors of 2 as possible, as that makes it easier
* to find a fast DAC rate
*/
pow2 = 1 << fls((pcm512x_pll_max(pcm512x) - 16000000) / bclk_rate);
for (; pow2; pow2 >>= 1) {
sck_rate = rounddown(pcm512x_pll_max(pcm512x),
bclk_rate * pow2);
if (sck_rate >= 16000000)
break;
}
if (!pow2) {
dev_err(dev, "Impossible to generate a suitable SCK\n");
return 0;
}
dev_dbg(dev, "sck_rate %lu\n", sck_rate);
return sck_rate;
}
/* pll_rate = pllin_rate * R * J.D / P
* 1 <= R <= 16
* 1 <= J <= 63
* 0 <= D <= 9999
* 1 <= P <= 15
* 64 MHz <= pll_rate <= 100 MHz
* if D == 0
* 1 MHz <= pllin_rate / P <= 20 MHz
* else if D > 0
* 6.667 MHz <= pllin_rate / P <= 20 MHz
* 4 <= J <= 11
* R = 1
*/
static int pcm512x_find_pll_coeff(struct snd_soc_dai *dai,
unsigned long pllin_rate,
unsigned long pll_rate)
{
struct device *dev = dai->dev;
struct snd_soc_component *component = dai->component;
struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
unsigned long common;
int R, J, D, P;
unsigned long K; /* 10000 * J.D */
unsigned long num;
unsigned long den;
common = gcd(pll_rate, pllin_rate);
dev_dbg(dev, "pll %lu pllin %lu common %lu\n",
pll_rate, pllin_rate, common);
num = pll_rate / common;
den = pllin_rate / common;
/* pllin_rate / P (or here, den) cannot be greater than 20 MHz */
if (pllin_rate / den > 20000000 && num < 8) {
num *= DIV_ROUND_UP(pllin_rate / den, 20000000);
den *= DIV_ROUND_UP(pllin_rate / den, 20000000);
}
dev_dbg(dev, "num / den = %lu / %lu\n", num, den);
P = den;
if (den <= 15 && num <= 16 * 63
&& 1000000 <= pllin_rate / P && pllin_rate / P <= 20000000) {
/* Try the case with D = 0 */
D = 0;
/* factor 'num' into J and R, such that R <= 16 and J <= 63 */
for (R = 16; R; R--) {
if (num % R)
continue;
J = num / R;
if (J == 0 || J > 63)
continue;
dev_dbg(dev, "R * J / P = %d * %d / %d\n", R, J, P);
pcm512x->real_pll = pll_rate;
goto done;
}
/* no luck */
}
R = 1;
if (num > 0xffffffffUL / 10000)
goto fallback;
/* Try to find an exact pll_rate using the D > 0 case */
common = gcd(10000 * num, den);
num = 10000 * num / common;
den /= common;
dev_dbg(dev, "num %lu den %lu common %lu\n", num, den, common);
for (P = den; P <= 15; P++) {
if (pllin_rate / P < 6667000 || 200000000 < pllin_rate / P)
continue;
if (num * P % den)
continue;
K = num * P / den;
/* J == 12 is ok if D == 0 */
if (K < 40000 || K > 120000)
continue;
J = K / 10000;
D = K % 10000;
dev_dbg(dev, "J.D / P = %d.%04d / %d\n", J, D, P);
pcm512x->real_pll = pll_rate;
goto done;
}
/* Fall back to an approximate pll_rate */
fallback:
/* find smallest possible P */
P = DIV_ROUND_UP(pllin_rate, 20000000);
if (!P)
P = 1;
else if (P > 15) {
dev_err(dev, "Need a slower clock as pll-input\n");
return -EINVAL;
}
if (pllin_rate / P < 6667000) {
dev_err(dev, "Need a faster clock as pll-input\n");
return -EINVAL;
}
K = DIV_ROUND_CLOSEST_ULL(10000ULL * pll_rate * P, pllin_rate);
if (K < 40000)
K = 40000;
/* J == 12 is ok if D == 0 */
if (K > 120000)
K = 120000;
J = K / 10000;
D = K % 10000;
dev_dbg(dev, "J.D / P ~ %d.%04d / %d\n", J, D, P);
pcm512x->real_pll = DIV_ROUND_DOWN_ULL((u64)K * pllin_rate, 10000 * P);
done:
pcm512x->pll_r = R;
pcm512x->pll_j = J;
pcm512x->pll_d = D;
pcm512x->pll_p = P;
return 0;
}
static unsigned long pcm512x_pllin_dac_rate(struct snd_soc_dai *dai,
unsigned long osr_rate,
unsigned long pllin_rate)
{
struct snd_soc_component *component = dai->component;
struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
unsigned long dac_rate;
if (!pcm512x->pll_out)
return 0; /* no PLL to bypass, force SCK as DAC input */
if (pllin_rate % osr_rate)
return 0; /* futile, quit early */
/* run DAC no faster than 6144000 Hz */
for (dac_rate = rounddown(pcm512x_dac_max(pcm512x, 6144000), osr_rate);
dac_rate;
dac_rate -= osr_rate) {
if (pllin_rate / dac_rate > 128)
return 0; /* DAC divider would be too big */
if (!(pllin_rate % dac_rate))
return dac_rate;
dac_rate -= osr_rate;
}
return 0;
}
static int pcm512x_set_dividers(struct snd_soc_dai *dai,
struct snd_pcm_hw_params *params)
{
struct device *dev = dai->dev;
struct snd_soc_component *component = dai->component;
struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
unsigned long pllin_rate = 0;
unsigned long pll_rate;
unsigned long sck_rate;
unsigned long mck_rate;
unsigned long bclk_rate;
unsigned long sample_rate;
unsigned long osr_rate;
unsigned long dacsrc_rate;
int bclk_div;
int lrclk_div;
int dsp_div;
int dac_div;
unsigned long dac_rate;
int ncp_div;
int osr_div;
int ret;
int idac;
int fssp;
int gpio;
if (pcm512x->bclk_ratio > 0) {
lrclk_div = pcm512x->bclk_ratio;
} else {
lrclk_div = snd_soc_params_to_frame_size(params);
if (lrclk_div == 0) {
dev_err(dev, "No LRCLK?\n");
return -EINVAL;
}
}
if (!pcm512x->pll_out) {
sck_rate = clk_get_rate(pcm512x->sclk);
bclk_rate = params_rate(params) * lrclk_div;
bclk_div = DIV_ROUND_CLOSEST(sck_rate, bclk_rate);
mck_rate = sck_rate;
} else {
ret = snd_soc_params_to_bclk(params);
if (ret < 0) {
dev_err(dev, "Failed to find suitable BCLK: %d\n", ret);
return ret;
}
if (ret == 0) {
dev_err(dev, "No BCLK?\n");
return -EINVAL;
}
bclk_rate = ret;
pllin_rate = clk_get_rate(pcm512x->sclk);
sck_rate = pcm512x_find_sck(dai, bclk_rate);
if (!sck_rate)
return -EINVAL;
pll_rate = 4 * sck_rate;
ret = pcm512x_find_pll_coeff(dai, pllin_rate, pll_rate);
if (ret != 0)
return ret;
ret = regmap_write(pcm512x->regmap,
PCM512x_PLL_COEFF_0, pcm512x->pll_p - 1);
if (ret != 0) {
dev_err(dev, "Failed to write PLL P: %d\n", ret);
return ret;
}
ret = regmap_write(pcm512x->regmap,
PCM512x_PLL_COEFF_1, pcm512x->pll_j);
if (ret != 0) {
dev_err(dev, "Failed to write PLL J: %d\n", ret);
return ret;
}
ret = regmap_write(pcm512x->regmap,
PCM512x_PLL_COEFF_2, pcm512x->pll_d >> 8);
if (ret != 0) {
dev_err(dev, "Failed to write PLL D msb: %d\n", ret);
return ret;
}
ret = regmap_write(pcm512x->regmap,
PCM512x_PLL_COEFF_3, pcm512x->pll_d & 0xff);
if (ret != 0) {
dev_err(dev, "Failed to write PLL D lsb: %d\n", ret);
return ret;
}
ret = regmap_write(pcm512x->regmap,
PCM512x_PLL_COEFF_4, pcm512x->pll_r - 1);
if (ret != 0) {
dev_err(dev, "Failed to write PLL R: %d\n", ret);
return ret;
}
mck_rate = pcm512x->real_pll;
bclk_div = DIV_ROUND_CLOSEST(sck_rate, bclk_rate);
}
if (bclk_div > 128) {
dev_err(dev, "Failed to find BCLK divider\n");
return -EINVAL;
}
/* the actual rate */
sample_rate = sck_rate / bclk_div / lrclk_div;
osr_rate = 16 * sample_rate;
/* run DSP no faster than 50 MHz */
dsp_div = mck_rate > pcm512x_dsp_max(pcm512x) ? 2 : 1;
dac_rate = pcm512x_pllin_dac_rate(dai, osr_rate, pllin_rate);
if (dac_rate) {
/* the desired clock rate is "compatible" with the pll input
* clock, so use that clock as dac input instead of the pll
* output clock since the pll will introduce jitter and thus
* noise.
*/
dev_dbg(dev, "using pll input as dac input\n");
ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF,
PCM512x_SDAC, PCM512x_SDAC_GPIO);
if (ret != 0) {
dev_err(component->dev,
"Failed to set gpio as dacref: %d\n", ret);
return ret;
}
gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1;
ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_DACIN,
PCM512x_GREF, gpio);
if (ret != 0) {
dev_err(component->dev,
"Failed to set gpio %d as dacin: %d\n",
pcm512x->pll_in, ret);
return ret;
}
dacsrc_rate = pllin_rate;
} else {
/* run DAC no faster than 6144000 Hz */
unsigned long dac_mul = pcm512x_dac_max(pcm512x, 6144000)
/ osr_rate;
unsigned long sck_mul = sck_rate / osr_rate;
for (; dac_mul; dac_mul--) {
if (!(sck_mul % dac_mul))
break;
}
if (!dac_mul) {
dev_err(dev, "Failed to find DAC rate\n");
return -EINVAL;
}
dac_rate = dac_mul * osr_rate;
dev_dbg(dev, "dac_rate %lu sample_rate %lu\n",
dac_rate, sample_rate);
ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF,
PCM512x_SDAC, PCM512x_SDAC_SCK);
if (ret != 0) {
dev_err(component->dev,
"Failed to set sck as dacref: %d\n", ret);
return ret;
}
dacsrc_rate = sck_rate;
}
osr_div = DIV_ROUND_CLOSEST(dac_rate, osr_rate);
if (osr_div > 128) {
dev_err(dev, "Failed to find OSR divider\n");
return -EINVAL;
}
dac_div = DIV_ROUND_CLOSEST(dacsrc_rate, dac_rate);
if (dac_div > 128) {
dev_err(dev, "Failed to find DAC divider\n");
return -EINVAL;
}
dac_rate = dacsrc_rate / dac_div;
ncp_div = DIV_ROUND_CLOSEST(dac_rate,
pcm512x_ncp_target(pcm512x, dac_rate));
if (ncp_div > 128 || dac_rate / ncp_div > 2048000) {
/* run NCP no faster than 2048000 Hz, but why? */
ncp_div = DIV_ROUND_UP(dac_rate, 2048000);
if (ncp_div > 128) {
dev_err(dev, "Failed to find NCP divider\n");
return -EINVAL;
}
}
idac = mck_rate / (dsp_div * sample_rate);
ret = regmap_write(pcm512x->regmap, PCM512x_DSP_CLKDIV, dsp_div - 1);
if (ret != 0) {
dev_err(dev, "Failed to write DSP divider: %d\n", ret);
return ret;
}
ret = regmap_write(pcm512x->regmap, PCM512x_DAC_CLKDIV, dac_div - 1);
if (ret != 0) {
dev_err(dev, "Failed to write DAC divider: %d\n", ret);
return ret;
}
ret = regmap_write(pcm512x->regmap, PCM512x_NCP_CLKDIV, ncp_div - 1);
if (ret != 0) {
dev_err(dev, "Failed to write NCP divider: %d\n", ret);
return ret;
}
ret = regmap_write(pcm512x->regmap, PCM512x_OSR_CLKDIV, osr_div - 1);
if (ret != 0) {
dev_err(dev, "Failed to write OSR divider: %d\n", ret);
return ret;
}
ret = regmap_write(pcm512x->regmap,
PCM512x_MASTER_CLKDIV_1, bclk_div - 1);
if (ret != 0) {
dev_err(dev, "Failed to write BCLK divider: %d\n", ret);
return ret;
}
ret = regmap_write(pcm512x->regmap,
PCM512x_MASTER_CLKDIV_2, lrclk_div - 1);
if (ret != 0) {
dev_err(dev, "Failed to write LRCLK divider: %d\n", ret);
return ret;
}
ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_1, idac >> 8);
if (ret != 0) {
dev_err(dev, "Failed to write IDAC msb divider: %d\n", ret);
return ret;
}
ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_2, idac & 0xff);
if (ret != 0) {
dev_err(dev, "Failed to write IDAC lsb divider: %d\n", ret);
return ret;
}
if (sample_rate <= pcm512x_dac_max(pcm512x, 48000))
fssp = PCM512x_FSSP_48KHZ;
else if (sample_rate <= pcm512x_dac_max(pcm512x, 96000))
fssp = PCM512x_FSSP_96KHZ;
else if (sample_rate <= pcm512x_dac_max(pcm512x, 192000))
fssp = PCM512x_FSSP_192KHZ;
else
fssp = PCM512x_FSSP_384KHZ;
ret = regmap_update_bits(pcm512x->regmap, PCM512x_FS_SPEED_MODE,
PCM512x_FSSP, fssp);
if (ret != 0) {
dev_err(component->dev, "Failed to set fs speed: %d\n", ret);
return ret;
}
dev_dbg(component->dev, "DSP divider %d\n", dsp_div);
dev_dbg(component->dev, "DAC divider %d\n", dac_div);
dev_dbg(component->dev, "NCP divider %d\n", ncp_div);
dev_dbg(component->dev, "OSR divider %d\n", osr_div);
dev_dbg(component->dev, "BCK divider %d\n", bclk_div);
dev_dbg(component->dev, "LRCK divider %d\n", lrclk_div);
dev_dbg(component->dev, "IDAC %d\n", idac);
dev_dbg(component->dev, "1<<FSSP %d\n", 1 << fssp);
return 0;
}
static int pcm512x_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
int alen;
int gpio;
int ret;
dev_dbg(component->dev, "hw_params %u Hz, %u channels\n",
params_rate(params),
params_channels(params));
switch (params_width(params)) {
case 16:
alen = PCM512x_ALEN_16;
break;
case 20:
alen = PCM512x_ALEN_20;
break;
case 24:
alen = PCM512x_ALEN_24;
break;
case 32:
alen = PCM512x_ALEN_32;
break;
default:
dev_err(component->dev, "Bad frame size: %d\n",
params_width(params));
return -EINVAL;
}
ret = regmap_update_bits(pcm512x->regmap, PCM512x_I2S_1,
PCM512x_ALEN, alen);
if (ret != 0) {
dev_err(component->dev, "Failed to set frame size: %d\n", ret);
return ret;
}
if ((pcm512x->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) ==
SND_SOC_DAIFMT_CBC_CFC) {
ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT,
PCM512x_DCAS, 0);
if (ret != 0) {
dev_err(component->dev,
"Failed to enable clock divider autoset: %d\n",
ret);
return ret;
}
goto skip_pll;
}
if (pcm512x->pll_out) {
ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_A, 0x11);
if (ret != 0) {
dev_err(component->dev, "Failed to set FLEX_A: %d\n", ret);
return ret;
}
ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_B, 0xff);
if (ret != 0) {
dev_err(component->dev, "Failed to set FLEX_B: %d\n", ret);
return ret;
}
ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT,
PCM512x_IDFS | PCM512x_IDBK
| PCM512x_IDSK | PCM512x_IDCH
| PCM512x_IDCM | PCM512x_DCAS
| PCM512x_IPLK,
PCM512x_IDFS | PCM512x_IDBK
| PCM512x_IDSK | PCM512x_IDCH
| PCM512x_DCAS);
if (ret != 0) {
dev_err(component->dev,
"Failed to ignore auto-clock failures: %d\n",
ret);
return ret;
}
} else {
ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT,
PCM512x_IDFS | PCM512x_IDBK
| PCM512x_IDSK | PCM512x_IDCH
| PCM512x_IDCM | PCM512x_DCAS
| PCM512x_IPLK,
PCM512x_IDFS | PCM512x_IDBK
| PCM512x_IDSK | PCM512x_IDCH
| PCM512x_DCAS | PCM512x_IPLK);
if (ret != 0) {
dev_err(component->dev,
"Failed to ignore auto-clock failures: %d\n",
ret);
return ret;
}
ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN,
PCM512x_PLLE, 0);
if (ret != 0) {
dev_err(component->dev, "Failed to disable pll: %d\n", ret);
return ret;
}
}
ret = pcm512x_set_dividers(dai, params);
if (ret != 0)
return ret;
if (pcm512x->pll_out) {
ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_REF,
PCM512x_SREF, PCM512x_SREF_GPIO);
if (ret != 0) {
dev_err(component->dev,
"Failed to set gpio as pllref: %d\n", ret);
return ret;
}
gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1;
ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_PLLIN,
PCM512x_GREF, gpio);
if (ret != 0) {
dev_err(component->dev,
"Failed to set gpio %d as pllin: %d\n",
pcm512x->pll_in, ret);
return ret;
}
ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN,
PCM512x_PLLE, PCM512x_PLLE);
if (ret != 0) {
dev_err(component->dev, "Failed to enable pll: %d\n", ret);
return ret;
}
gpio = PCM512x_G1OE << (pcm512x->pll_out - 1);
ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_EN,
gpio, gpio);
if (ret != 0) {
dev_err(component->dev, "Failed to enable gpio %d: %d\n",
pcm512x->pll_out, ret);
return ret;
}
gpio = PCM512x_GPIO_OUTPUT_1 + pcm512x->pll_out - 1;
ret = regmap_update_bits(pcm512x->regmap, gpio,
PCM512x_GxSL, PCM512x_GxSL_PLLCK);
if (ret != 0) {
dev_err(component->dev, "Failed to output pll on %d: %d\n",
ret, pcm512x->pll_out);
return ret;
}
}
ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE,
PCM512x_RQSY, PCM512x_RQSY_HALT);
if (ret != 0) {
dev_err(component->dev, "Failed to halt clocks: %d\n", ret);
return ret;
}
ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE,
PCM512x_RQSY, PCM512x_RQSY_RESUME);
if (ret != 0) {
dev_err(component->dev, "Failed to resume clocks: %d\n", ret);
return ret;
}
skip_pll:
return 0;
}
static int pcm512x_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
int afmt;
int offset = 0;
int clock_output;
int provider_mode;
int ret;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC:
clock_output = 0;
provider_mode = 0;
break;
case SND_SOC_DAIFMT_CBP_CFP:
clock_output = PCM512x_BCKO | PCM512x_LRKO;
provider_mode = PCM512x_RLRK | PCM512x_RBCK;
break;
case SND_SOC_DAIFMT_CBP_CFC:
clock_output = PCM512x_BCKO;
provider_mode = PCM512x_RBCK;
break;
default:
return -EINVAL;
}
ret = regmap_update_bits(pcm512x->regmap, PCM512x_BCLK_LRCLK_CFG,
PCM512x_BCKP | PCM512x_BCKO | PCM512x_LRKO,
clock_output);
if (ret != 0) {
dev_err(component->dev, "Failed to enable clock output: %d\n", ret);
return ret;
}
ret = regmap_update_bits(pcm512x->regmap, PCM512x_MASTER_MODE,
PCM512x_RLRK | PCM512x_RBCK,
provider_mode);
if (ret != 0) {
dev_err(component->dev, "Failed to enable provider mode: %d\n", ret);
return ret;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
afmt = PCM512x_AFMT_I2S;
break;
case SND_SOC_DAIFMT_RIGHT_J:
afmt = PCM512x_AFMT_RTJ;
break;
case SND_SOC_DAIFMT_LEFT_J:
afmt = PCM512x_AFMT_LTJ;
break;
case SND_SOC_DAIFMT_DSP_A:
offset = 1;
fallthrough;
case SND_SOC_DAIFMT_DSP_B:
afmt = PCM512x_AFMT_DSP;
break;
default:
dev_err(component->dev, "unsupported DAI format: 0x%x\n",
pcm512x->fmt);
return -EINVAL;
}
ret = regmap_update_bits(pcm512x->regmap, PCM512x_I2S_1,
PCM512x_AFMT, afmt);
if (ret != 0) {
dev_err(component->dev, "Failed to set data format: %d\n", ret);
return ret;
}
ret = regmap_update_bits(pcm512x->regmap, PCM512x_I2S_2,
0xFF, offset);
if (ret != 0) {
dev_err(component->dev, "Failed to set data offset: %d\n", ret);
return ret;
}
pcm512x->fmt = fmt;
return 0;
}
static int pcm512x_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
{
struct snd_soc_component *component = dai->component;
struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
if (ratio > 256)
return -EINVAL;
pcm512x->bclk_ratio = ratio;
return 0;
}
static int pcm512x_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
int ret;
unsigned int mute_det;
mutex_lock(&pcm512x->mutex);
if (mute) {
pcm512x->mute |= 0x1;
ret = regmap_update_bits(pcm512x->regmap, PCM512x_MUTE,
PCM512x_RQML | PCM512x_RQMR,
PCM512x_RQML | PCM512x_RQMR);
if (ret != 0) {
dev_err(component->dev,
"Failed to set digital mute: %d\n", ret);
goto unlock;
}
regmap_read_poll_timeout(pcm512x->regmap,
PCM512x_ANALOG_MUTE_DET,
mute_det, (mute_det & 0x3) == 0,
200, 10000);
} else {
pcm512x->mute &= ~0x1;
ret = pcm512x_update_mute(pcm512x);
if (ret != 0) {
dev_err(component->dev,
"Failed to update digital mute: %d\n", ret);
goto unlock;
}
regmap_read_poll_timeout(pcm512x->regmap,
PCM512x_ANALOG_MUTE_DET,
mute_det,
(mute_det & 0x3)
== ((~pcm512x->mute >> 1) & 0x3),
200, 10000);
}
unlock:
mutex_unlock(&pcm512x->mutex);
return ret;
}
static const struct snd_soc_dai_ops pcm512x_dai_ops = {
.startup = pcm512x_dai_startup,
.hw_params = pcm512x_hw_params,
.set_fmt = pcm512x_set_fmt,
.mute_stream = pcm512x_mute,
.set_bclk_ratio = pcm512x_set_bclk_ratio,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver pcm512x_dai = {
.name = "pcm512x-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.rate_min = 8000,
.rate_max = 384000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S32_LE
},
.ops = &pcm512x_dai_ops,
};
static const struct snd_soc_component_driver pcm512x_component_driver = {
.set_bias_level = pcm512x_set_bias_level,
.controls = pcm512x_controls,
.num_controls = ARRAY_SIZE(pcm512x_controls),
.dapm_widgets = pcm512x_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(pcm512x_dapm_widgets),
.dapm_routes = pcm512x_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(pcm512x_dapm_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_range_cfg pcm512x_range = {
.name = "Pages", .range_min = PCM512x_VIRT_BASE,
.range_max = PCM512x_MAX_REGISTER,
.selector_reg = PCM512x_PAGE,
.selector_mask = 0xff,
.window_start = 0, .window_len = 0x100,
};
const struct regmap_config pcm512x_regmap = {
.reg_bits = 8,
.val_bits = 8,
.readable_reg = pcm512x_readable,
.volatile_reg = pcm512x_volatile,
.ranges = &pcm512x_range,
.num_ranges = 1,
.max_register = PCM512x_MAX_REGISTER,
.reg_defaults = pcm512x_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(pcm512x_reg_defaults),
.cache_type = REGCACHE_RBTREE,
};
EXPORT_SYMBOL_GPL(pcm512x_regmap);
int pcm512x_probe(struct device *dev, struct regmap *regmap)
{
struct pcm512x_priv *pcm512x;
int i, ret;
pcm512x = devm_kzalloc(dev, sizeof(struct pcm512x_priv), GFP_KERNEL);
if (!pcm512x)
return -ENOMEM;
mutex_init(&pcm512x->mutex);
dev_set_drvdata(dev, pcm512x);
pcm512x->regmap = regmap;
for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++)
pcm512x->supplies[i].supply = pcm512x_supply_names[i];
ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pcm512x->supplies),
pcm512x->supplies);
if (ret != 0) {
dev_err(dev, "Failed to get supplies: %d\n", ret);
return ret;
}
pcm512x->supply_nb[0].notifier_call = pcm512x_regulator_event_0;
pcm512x->supply_nb[1].notifier_call = pcm512x_regulator_event_1;
pcm512x->supply_nb[2].notifier_call = pcm512x_regulator_event_2;
for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++) {
ret = devm_regulator_register_notifier(
pcm512x->supplies[i].consumer,
&pcm512x->supply_nb[i]);
if (ret != 0) {
dev_err(dev,
"Failed to register regulator notifier: %d\n",
ret);
}
}
ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies),
pcm512x->supplies);
if (ret != 0) {
dev_err(dev, "Failed to enable supplies: %d\n", ret);
return ret;
}
/* Reset the device, verifying I/O in the process for I2C */
ret = regmap_write(regmap, PCM512x_RESET,
PCM512x_RSTM | PCM512x_RSTR);
if (ret != 0) {
dev_err(dev, "Failed to reset device: %d\n", ret);
goto err;
}
ret = regmap_write(regmap, PCM512x_RESET, 0);
if (ret != 0) {
dev_err(dev, "Failed to reset device: %d\n", ret);
goto err;
}
pcm512x->sclk = devm_clk_get(dev, NULL);
if (PTR_ERR(pcm512x->sclk) == -EPROBE_DEFER) {
ret = -EPROBE_DEFER;
goto err;
}
if (!IS_ERR(pcm512x->sclk)) {
ret = clk_prepare_enable(pcm512x->sclk);
if (ret != 0) {
dev_err(dev, "Failed to enable SCLK: %d\n", ret);
goto err;
}
}
/* Default to standby mode */
ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
PCM512x_RQST, PCM512x_RQST);
if (ret != 0) {
dev_err(dev, "Failed to request standby: %d\n",
ret);
goto err_clk;
}
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
pm_runtime_idle(dev);
#ifdef CONFIG_OF
if (dev->of_node) {
const struct device_node *np = dev->of_node;
u32 val;
if (of_property_read_u32(np, "pll-in", &val) >= 0) {
if (val > 6) {
dev_err(dev, "Invalid pll-in\n");
ret = -EINVAL;
goto err_pm;
}
pcm512x->pll_in = val;
}
if (of_property_read_u32(np, "pll-out", &val) >= 0) {
if (val > 6) {
dev_err(dev, "Invalid pll-out\n");
ret = -EINVAL;
goto err_pm;
}
pcm512x->pll_out = val;
}
if (!pcm512x->pll_in != !pcm512x->pll_out) {
dev_err(dev,
"Error: both pll-in and pll-out, or none\n");
ret = -EINVAL;
goto err_pm;
}
if (pcm512x->pll_in && pcm512x->pll_in == pcm512x->pll_out) {
dev_err(dev, "Error: pll-in == pll-out\n");
ret = -EINVAL;
goto err_pm;
}
}
#endif
ret = devm_snd_soc_register_component(dev, &pcm512x_component_driver,
&pcm512x_dai, 1);
if (ret != 0) {
dev_err(dev, "Failed to register CODEC: %d\n", ret);
goto err_pm;
}
return 0;
err_pm:
pm_runtime_disable(dev);
err_clk:
if (!IS_ERR(pcm512x->sclk))
clk_disable_unprepare(pcm512x->sclk);
err:
regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies),
pcm512x->supplies);
return ret;
}
EXPORT_SYMBOL_GPL(pcm512x_probe);
void pcm512x_remove(struct device *dev)
{
struct pcm512x_priv *pcm512x = dev_get_drvdata(dev);
pm_runtime_disable(dev);
if (!IS_ERR(pcm512x->sclk))
clk_disable_unprepare(pcm512x->sclk);
regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies),
pcm512x->supplies);
}
EXPORT_SYMBOL_GPL(pcm512x_remove);
#ifdef CONFIG_PM
static int pcm512x_suspend(struct device *dev)
{
struct pcm512x_priv *pcm512x = dev_get_drvdata(dev);
int ret;
ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
PCM512x_RQPD, PCM512x_RQPD);
if (ret != 0) {
dev_err(dev, "Failed to request power down: %d\n", ret);
return ret;
}
ret = regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies),
pcm512x->supplies);
if (ret != 0) {
dev_err(dev, "Failed to disable supplies: %d\n", ret);
return ret;
}
if (!IS_ERR(pcm512x->sclk))
clk_disable_unprepare(pcm512x->sclk);
return 0;
}
static int pcm512x_resume(struct device *dev)
{
struct pcm512x_priv *pcm512x = dev_get_drvdata(dev);
int ret;
if (!IS_ERR(pcm512x->sclk)) {
ret = clk_prepare_enable(pcm512x->sclk);
if (ret != 0) {
dev_err(dev, "Failed to enable SCLK: %d\n", ret);
return ret;
}
}
ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies),
pcm512x->supplies);
if (ret != 0) {
dev_err(dev, "Failed to enable supplies: %d\n", ret);
return ret;
}
regcache_cache_only(pcm512x->regmap, false);
ret = regcache_sync(pcm512x->regmap);
if (ret != 0) {
dev_err(dev, "Failed to sync cache: %d\n", ret);
return ret;
}
ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
PCM512x_RQPD, 0);
if (ret != 0) {
dev_err(dev, "Failed to remove power down: %d\n", ret);
return ret;
}
return 0;
}
#endif
const struct dev_pm_ops pcm512x_pm_ops = {
SET_RUNTIME_PM_OPS(pcm512x_suspend, pcm512x_resume, NULL)
};
EXPORT_SYMBOL_GPL(pcm512x_pm_ops);
MODULE_DESCRIPTION("ASoC PCM512x codec driver");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/pcm512x.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Driver for ADAU1372 codec
*
* Copyright 2016 Analog Devices Inc.
* Author: Lars-Peter Clausen <[email protected]>
*/
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include <sound/soc.h>
#include "adau1372.h"
static void adau1372_spi_switch_mode(struct device *dev)
{
struct spi_device *spi = to_spi_device(dev);
/*
* To get the device into SPI mode CLATCH has to be pulled low three
* times. Do this by issuing three dummy reads.
*/
spi_w8r8(spi, 0x00);
spi_w8r8(spi, 0x00);
spi_w8r8(spi, 0x00);
}
static int adau1372_spi_probe(struct spi_device *spi)
{
struct regmap_config config;
config = adau1372_regmap_config;
config.read_flag_mask = 0x1;
return adau1372_probe(&spi->dev,
devm_regmap_init_spi(spi, &config), adau1372_spi_switch_mode);
}
static const struct spi_device_id adau1372_spi_id[] = {
{ "adau1372", 0 },
{ }
};
MODULE_DEVICE_TABLE(spi, adau1372_spi_id);
static struct spi_driver adau1372_spi_driver = {
.driver = {
.name = "adau1372",
},
.probe = adau1372_spi_probe,
.id_table = adau1372_spi_id,
};
module_spi_driver(adau1372_spi_driver);
MODULE_DESCRIPTION("ASoC ADAU1372 CODEC SPI driver");
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/adau1372-spi.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* isabelle.c - Low power high fidelity audio codec driver
*
* Copyright (c) 2012 Texas Instruments, Inc
*
* Initially based on sound/soc/codecs/twl6040.c
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/regmap.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/tlv.h>
#include <sound/jack.h>
#include <sound/initval.h>
#include <asm/div64.h>
#include "isabelle.h"
/* Register default values for ISABELLE driver. */
static const struct reg_default isabelle_reg_defs[] = {
{ 0, 0x00 },
{ 1, 0x00 },
{ 2, 0x00 },
{ 3, 0x00 },
{ 4, 0x00 },
{ 5, 0x00 },
{ 6, 0x00 },
{ 7, 0x00 },
{ 8, 0x00 },
{ 9, 0x00 },
{ 10, 0x00 },
{ 11, 0x00 },
{ 12, 0x00 },
{ 13, 0x00 },
{ 14, 0x00 },
{ 15, 0x00 },
{ 16, 0x00 },
{ 17, 0x00 },
{ 18, 0x00 },
{ 19, 0x00 },
{ 20, 0x00 },
{ 21, 0x02 },
{ 22, 0x02 },
{ 23, 0x02 },
{ 24, 0x02 },
{ 25, 0x0F },
{ 26, 0x8F },
{ 27, 0x0F },
{ 28, 0x8F },
{ 29, 0x00 },
{ 30, 0x00 },
{ 31, 0x00 },
{ 32, 0x00 },
{ 33, 0x00 },
{ 34, 0x00 },
{ 35, 0x00 },
{ 36, 0x00 },
{ 37, 0x00 },
{ 38, 0x00 },
{ 39, 0x00 },
{ 40, 0x00 },
{ 41, 0x00 },
{ 42, 0x00 },
{ 43, 0x00 },
{ 44, 0x00 },
{ 45, 0x00 },
{ 46, 0x00 },
{ 47, 0x00 },
{ 48, 0x00 },
{ 49, 0x00 },
{ 50, 0x00 },
{ 51, 0x00 },
{ 52, 0x00 },
{ 53, 0x00 },
{ 54, 0x00 },
{ 55, 0x00 },
{ 56, 0x00 },
{ 57, 0x00 },
{ 58, 0x00 },
{ 59, 0x00 },
{ 60, 0x00 },
{ 61, 0x00 },
{ 62, 0x00 },
{ 63, 0x00 },
{ 64, 0x00 },
{ 65, 0x00 },
{ 66, 0x00 },
{ 67, 0x00 },
{ 68, 0x00 },
{ 69, 0x90 },
{ 70, 0x90 },
{ 71, 0x90 },
{ 72, 0x00 },
{ 73, 0x00 },
{ 74, 0x00 },
{ 75, 0x00 },
{ 76, 0x00 },
{ 77, 0x00 },
{ 78, 0x00 },
{ 79, 0x00 },
{ 80, 0x00 },
{ 81, 0x00 },
{ 82, 0x00 },
{ 83, 0x00 },
{ 84, 0x00 },
{ 85, 0x07 },
{ 86, 0x00 },
{ 87, 0x00 },
{ 88, 0x00 },
{ 89, 0x07 },
{ 90, 0x80 },
{ 91, 0x07 },
{ 92, 0x07 },
{ 93, 0x00 },
{ 94, 0x00 },
{ 95, 0x00 },
{ 96, 0x00 },
{ 97, 0x00 },
{ 98, 0x00 },
{ 99, 0x00 },
};
static const char *isabelle_rx1_texts[] = {"VRX1", "ARX1"};
static const char *isabelle_rx2_texts[] = {"VRX2", "ARX2"};
static const struct soc_enum isabelle_rx1_enum[] = {
SOC_ENUM_SINGLE(ISABELLE_VOICE_HPF_CFG_REG, 3,
ARRAY_SIZE(isabelle_rx1_texts), isabelle_rx1_texts),
SOC_ENUM_SINGLE(ISABELLE_AUDIO_HPF_CFG_REG, 5,
ARRAY_SIZE(isabelle_rx1_texts), isabelle_rx1_texts),
};
static const struct soc_enum isabelle_rx2_enum[] = {
SOC_ENUM_SINGLE(ISABELLE_VOICE_HPF_CFG_REG, 2,
ARRAY_SIZE(isabelle_rx2_texts), isabelle_rx2_texts),
SOC_ENUM_SINGLE(ISABELLE_AUDIO_HPF_CFG_REG, 4,
ARRAY_SIZE(isabelle_rx2_texts), isabelle_rx2_texts),
};
/* Headset DAC playback switches */
static const struct snd_kcontrol_new rx1_mux_controls =
SOC_DAPM_ENUM("Route", isabelle_rx1_enum);
static const struct snd_kcontrol_new rx2_mux_controls =
SOC_DAPM_ENUM("Route", isabelle_rx2_enum);
/* TX input selection */
static const char *isabelle_atx_texts[] = {"AMIC1", "DMIC"};
static const char *isabelle_vtx_texts[] = {"AMIC2", "DMIC"};
static const struct soc_enum isabelle_atx_enum[] = {
SOC_ENUM_SINGLE(ISABELLE_AMIC_CFG_REG, 7,
ARRAY_SIZE(isabelle_atx_texts), isabelle_atx_texts),
SOC_ENUM_SINGLE(ISABELLE_DMIC_CFG_REG, 0,
ARRAY_SIZE(isabelle_atx_texts), isabelle_atx_texts),
};
static const struct soc_enum isabelle_vtx_enum[] = {
SOC_ENUM_SINGLE(ISABELLE_AMIC_CFG_REG, 6,
ARRAY_SIZE(isabelle_vtx_texts), isabelle_vtx_texts),
SOC_ENUM_SINGLE(ISABELLE_DMIC_CFG_REG, 0,
ARRAY_SIZE(isabelle_vtx_texts), isabelle_vtx_texts),
};
static const struct snd_kcontrol_new atx_mux_controls =
SOC_DAPM_ENUM("Route", isabelle_atx_enum);
static const struct snd_kcontrol_new vtx_mux_controls =
SOC_DAPM_ENUM("Route", isabelle_vtx_enum);
/* Left analog microphone selection */
static const char *isabelle_amic1_texts[] = {
"Main Mic", "Headset Mic", "Aux/FM Left"};
/* Left analog microphone selection */
static const char *isabelle_amic2_texts[] = {"Sub Mic", "Aux/FM Right"};
static SOC_ENUM_SINGLE_DECL(isabelle_amic1_enum,
ISABELLE_AMIC_CFG_REG, 5,
isabelle_amic1_texts);
static SOC_ENUM_SINGLE_DECL(isabelle_amic2_enum,
ISABELLE_AMIC_CFG_REG, 4,
isabelle_amic2_texts);
static const struct snd_kcontrol_new amic1_control =
SOC_DAPM_ENUM("Route", isabelle_amic1_enum);
static const struct snd_kcontrol_new amic2_control =
SOC_DAPM_ENUM("Route", isabelle_amic2_enum);
static const char *isabelle_st_audio_texts[] = {"ATX1", "ATX2"};
static const char *isabelle_st_voice_texts[] = {"VTX1", "VTX2"};
static const struct soc_enum isabelle_st_audio_enum[] = {
SOC_ENUM_SINGLE(ISABELLE_ATX_STPGA1_CFG_REG, 7,
ARRAY_SIZE(isabelle_st_audio_texts),
isabelle_st_audio_texts),
SOC_ENUM_SINGLE(ISABELLE_ATX_STPGA2_CFG_REG, 7,
ARRAY_SIZE(isabelle_st_audio_texts),
isabelle_st_audio_texts),
};
static const struct soc_enum isabelle_st_voice_enum[] = {
SOC_ENUM_SINGLE(ISABELLE_VTX_STPGA1_CFG_REG, 7,
ARRAY_SIZE(isabelle_st_voice_texts),
isabelle_st_voice_texts),
SOC_ENUM_SINGLE(ISABELLE_VTX2_STPGA2_CFG_REG, 7,
ARRAY_SIZE(isabelle_st_voice_texts),
isabelle_st_voice_texts),
};
static const struct snd_kcontrol_new st_audio_control =
SOC_DAPM_ENUM("Route", isabelle_st_audio_enum);
static const struct snd_kcontrol_new st_voice_control =
SOC_DAPM_ENUM("Route", isabelle_st_voice_enum);
/* Mixer controls */
static const struct snd_kcontrol_new isabelle_hs_left_mixer_controls[] = {
SOC_DAPM_SINGLE("DAC1L Playback Switch", ISABELLE_HSDRV_CFG1_REG, 7, 1, 0),
SOC_DAPM_SINGLE("APGA1 Playback Switch", ISABELLE_HSDRV_CFG1_REG, 6, 1, 0),
};
static const struct snd_kcontrol_new isabelle_hs_right_mixer_controls[] = {
SOC_DAPM_SINGLE("DAC1R Playback Switch", ISABELLE_HSDRV_CFG1_REG, 5, 1, 0),
SOC_DAPM_SINGLE("APGA2 Playback Switch", ISABELLE_HSDRV_CFG1_REG, 4, 1, 0),
};
static const struct snd_kcontrol_new isabelle_hf_left_mixer_controls[] = {
SOC_DAPM_SINGLE("DAC2L Playback Switch", ISABELLE_HFLPGA_CFG_REG, 7, 1, 0),
SOC_DAPM_SINGLE("APGA1 Playback Switch", ISABELLE_HFLPGA_CFG_REG, 6, 1, 0),
};
static const struct snd_kcontrol_new isabelle_hf_right_mixer_controls[] = {
SOC_DAPM_SINGLE("DAC2R Playback Switch", ISABELLE_HFRPGA_CFG_REG, 7, 1, 0),
SOC_DAPM_SINGLE("APGA2 Playback Switch", ISABELLE_HFRPGA_CFG_REG, 6, 1, 0),
};
static const struct snd_kcontrol_new isabelle_ep_mixer_controls[] = {
SOC_DAPM_SINGLE("DAC2L Playback Switch", ISABELLE_EARDRV_CFG1_REG, 7, 1, 0),
SOC_DAPM_SINGLE("APGA1 Playback Switch", ISABELLE_EARDRV_CFG1_REG, 6, 1, 0),
};
static const struct snd_kcontrol_new isabelle_aux_left_mixer_controls[] = {
SOC_DAPM_SINGLE("DAC3L Playback Switch", ISABELLE_LINEAMP_CFG_REG, 7, 1, 0),
SOC_DAPM_SINGLE("APGA1 Playback Switch", ISABELLE_LINEAMP_CFG_REG, 6, 1, 0),
};
static const struct snd_kcontrol_new isabelle_aux_right_mixer_controls[] = {
SOC_DAPM_SINGLE("DAC3R Playback Switch", ISABELLE_LINEAMP_CFG_REG, 5, 1, 0),
SOC_DAPM_SINGLE("APGA2 Playback Switch", ISABELLE_LINEAMP_CFG_REG, 4, 1, 0),
};
static const struct snd_kcontrol_new isabelle_dpga1_left_mixer_controls[] = {
SOC_DAPM_SINGLE("RX1 Playback Switch", ISABELLE_DPGA1LR_IN_SEL_REG, 7, 1, 0),
SOC_DAPM_SINGLE("RX3 Playback Switch", ISABELLE_DPGA1LR_IN_SEL_REG, 6, 1, 0),
SOC_DAPM_SINGLE("RX5 Playback Switch", ISABELLE_DPGA1LR_IN_SEL_REG, 5, 1, 0),
};
static const struct snd_kcontrol_new isabelle_dpga1_right_mixer_controls[] = {
SOC_DAPM_SINGLE("RX2 Playback Switch", ISABELLE_DPGA1LR_IN_SEL_REG, 3, 1, 0),
SOC_DAPM_SINGLE("RX4 Playback Switch", ISABELLE_DPGA1LR_IN_SEL_REG, 2, 1, 0),
SOC_DAPM_SINGLE("RX6 Playback Switch", ISABELLE_DPGA1LR_IN_SEL_REG, 1, 1, 0),
};
static const struct snd_kcontrol_new isabelle_dpga2_left_mixer_controls[] = {
SOC_DAPM_SINGLE("RX1 Playback Switch", ISABELLE_DPGA2L_IN_SEL_REG, 7, 1, 0),
SOC_DAPM_SINGLE("RX2 Playback Switch", ISABELLE_DPGA2L_IN_SEL_REG, 6, 1, 0),
SOC_DAPM_SINGLE("RX3 Playback Switch", ISABELLE_DPGA2L_IN_SEL_REG, 5, 1, 0),
SOC_DAPM_SINGLE("RX4 Playback Switch", ISABELLE_DPGA2L_IN_SEL_REG, 4, 1, 0),
SOC_DAPM_SINGLE("RX5 Playback Switch", ISABELLE_DPGA2L_IN_SEL_REG, 3, 1, 0),
SOC_DAPM_SINGLE("RX6 Playback Switch", ISABELLE_DPGA2L_IN_SEL_REG, 2, 1, 0),
};
static const struct snd_kcontrol_new isabelle_dpga2_right_mixer_controls[] = {
SOC_DAPM_SINGLE("USNC Playback Switch", ISABELLE_DPGA2R_IN_SEL_REG, 7, 1, 0),
SOC_DAPM_SINGLE("RX2 Playback Switch", ISABELLE_DPGA2R_IN_SEL_REG, 3, 1, 0),
SOC_DAPM_SINGLE("RX4 Playback Switch", ISABELLE_DPGA2R_IN_SEL_REG, 2, 1, 0),
SOC_DAPM_SINGLE("RX6 Playback Switch", ISABELLE_DPGA2R_IN_SEL_REG, 1, 1, 0),
};
static const struct snd_kcontrol_new isabelle_dpga3_left_mixer_controls[] = {
SOC_DAPM_SINGLE("RX1 Playback Switch", ISABELLE_DPGA3LR_IN_SEL_REG, 7, 1, 0),
SOC_DAPM_SINGLE("RX3 Playback Switch", ISABELLE_DPGA3LR_IN_SEL_REG, 6, 1, 0),
SOC_DAPM_SINGLE("RX5 Playback Switch", ISABELLE_DPGA3LR_IN_SEL_REG, 5, 1, 0),
};
static const struct snd_kcontrol_new isabelle_dpga3_right_mixer_controls[] = {
SOC_DAPM_SINGLE("RX2 Playback Switch", ISABELLE_DPGA3LR_IN_SEL_REG, 3, 1, 0),
SOC_DAPM_SINGLE("RX4 Playback Switch", ISABELLE_DPGA3LR_IN_SEL_REG, 2, 1, 0),
SOC_DAPM_SINGLE("RX6 Playback Switch", ISABELLE_DPGA3LR_IN_SEL_REG, 1, 1, 0),
};
static const struct snd_kcontrol_new isabelle_rx1_mixer_controls[] = {
SOC_DAPM_SINGLE("ST1 Playback Switch", ISABELLE_RX_INPUT_CFG_REG, 7, 1, 0),
SOC_DAPM_SINGLE("DL1 Playback Switch", ISABELLE_RX_INPUT_CFG_REG, 6, 1, 0),
};
static const struct snd_kcontrol_new isabelle_rx2_mixer_controls[] = {
SOC_DAPM_SINGLE("ST2 Playback Switch", ISABELLE_RX_INPUT_CFG_REG, 5, 1, 0),
SOC_DAPM_SINGLE("DL2 Playback Switch", ISABELLE_RX_INPUT_CFG_REG, 4, 1, 0),
};
static const struct snd_kcontrol_new isabelle_rx3_mixer_controls[] = {
SOC_DAPM_SINGLE("ST1 Playback Switch", ISABELLE_RX_INPUT_CFG_REG, 3, 1, 0),
SOC_DAPM_SINGLE("DL3 Playback Switch", ISABELLE_RX_INPUT_CFG_REG, 2, 1, 0),
};
static const struct snd_kcontrol_new isabelle_rx4_mixer_controls[] = {
SOC_DAPM_SINGLE("ST2 Playback Switch", ISABELLE_RX_INPUT_CFG_REG, 1, 1, 0),
SOC_DAPM_SINGLE("DL4 Playback Switch", ISABELLE_RX_INPUT_CFG_REG, 0, 1, 0),
};
static const struct snd_kcontrol_new isabelle_rx5_mixer_controls[] = {
SOC_DAPM_SINGLE("ST1 Playback Switch", ISABELLE_RX_INPUT_CFG2_REG, 7, 1, 0),
SOC_DAPM_SINGLE("DL5 Playback Switch", ISABELLE_RX_INPUT_CFG2_REG, 6, 1, 0),
};
static const struct snd_kcontrol_new isabelle_rx6_mixer_controls[] = {
SOC_DAPM_SINGLE("ST2 Playback Switch", ISABELLE_RX_INPUT_CFG2_REG, 5, 1, 0),
SOC_DAPM_SINGLE("DL6 Playback Switch", ISABELLE_RX_INPUT_CFG2_REG, 4, 1, 0),
};
static const struct snd_kcontrol_new ep_path_enable_control =
SOC_DAPM_SINGLE("Switch", ISABELLE_EARDRV_CFG2_REG, 0, 1, 0);
/* TLV Declarations */
static const DECLARE_TLV_DB_SCALE(mic_amp_tlv, 0, 100, 0);
static const DECLARE_TLV_DB_SCALE(afm_amp_tlv, -3300, 300, 0);
static const DECLARE_TLV_DB_SCALE(dac_tlv, -1200, 200, 0);
static const DECLARE_TLV_DB_SCALE(hf_tlv, -5000, 200, 0);
/* from -63 to 0 dB in 1 dB steps */
static const DECLARE_TLV_DB_SCALE(dpga_tlv, -6300, 100, 1);
/* from -63 to 9 dB in 1 dB steps */
static const DECLARE_TLV_DB_SCALE(rx_tlv, -6300, 100, 1);
static const DECLARE_TLV_DB_SCALE(st_tlv, -2700, 300, 1);
static const DECLARE_TLV_DB_SCALE(tx_tlv, -600, 100, 0);
static const struct snd_kcontrol_new isabelle_snd_controls[] = {
SOC_DOUBLE_TLV("Headset Playback Volume", ISABELLE_HSDRV_GAIN_REG,
4, 0, 0xF, 0, dac_tlv),
SOC_DOUBLE_R_TLV("Handsfree Playback Volume",
ISABELLE_HFLPGA_CFG_REG, ISABELLE_HFRPGA_CFG_REG,
0, 0x1F, 0, hf_tlv),
SOC_DOUBLE_TLV("Aux Playback Volume", ISABELLE_LINEAMP_GAIN_REG,
4, 0, 0xF, 0, dac_tlv),
SOC_SINGLE_TLV("Earpiece Playback Volume", ISABELLE_EARDRV_CFG1_REG,
0, 0xF, 0, dac_tlv),
SOC_DOUBLE_TLV("Aux FM Volume", ISABELLE_APGA_GAIN_REG, 4, 0, 0xF, 0,
afm_amp_tlv),
SOC_SINGLE_TLV("Mic1 Capture Volume", ISABELLE_MIC1_GAIN_REG, 3, 0x1F,
0, mic_amp_tlv),
SOC_SINGLE_TLV("Mic2 Capture Volume", ISABELLE_MIC2_GAIN_REG, 3, 0x1F,
0, mic_amp_tlv),
SOC_DOUBLE_R_TLV("DPGA1 Volume", ISABELLE_DPGA1L_GAIN_REG,
ISABELLE_DPGA1R_GAIN_REG, 0, 0x3F, 0, dpga_tlv),
SOC_DOUBLE_R_TLV("DPGA2 Volume", ISABELLE_DPGA2L_GAIN_REG,
ISABELLE_DPGA2R_GAIN_REG, 0, 0x3F, 0, dpga_tlv),
SOC_DOUBLE_R_TLV("DPGA3 Volume", ISABELLE_DPGA3L_GAIN_REG,
ISABELLE_DPGA3R_GAIN_REG, 0, 0x3F, 0, dpga_tlv),
SOC_SINGLE_TLV("Sidetone Audio TX1 Volume",
ISABELLE_ATX_STPGA1_CFG_REG, 0, 0xF, 0, st_tlv),
SOC_SINGLE_TLV("Sidetone Audio TX2 Volume",
ISABELLE_ATX_STPGA2_CFG_REG, 0, 0xF, 0, st_tlv),
SOC_SINGLE_TLV("Sidetone Voice TX1 Volume",
ISABELLE_VTX_STPGA1_CFG_REG, 0, 0xF, 0, st_tlv),
SOC_SINGLE_TLV("Sidetone Voice TX2 Volume",
ISABELLE_VTX2_STPGA2_CFG_REG, 0, 0xF, 0, st_tlv),
SOC_SINGLE_TLV("Audio TX1 Volume", ISABELLE_ATX1_DPGA_REG, 4, 0xF, 0,
tx_tlv),
SOC_SINGLE_TLV("Audio TX2 Volume", ISABELLE_ATX2_DPGA_REG, 4, 0xF, 0,
tx_tlv),
SOC_SINGLE_TLV("Voice TX1 Volume", ISABELLE_VTX1_DPGA_REG, 4, 0xF, 0,
tx_tlv),
SOC_SINGLE_TLV("Voice TX2 Volume", ISABELLE_VTX2_DPGA_REG, 4, 0xF, 0,
tx_tlv),
SOC_SINGLE_TLV("RX1 DPGA Volume", ISABELLE_RX1_DPGA_REG, 0, 0x3F, 0,
rx_tlv),
SOC_SINGLE_TLV("RX2 DPGA Volume", ISABELLE_RX2_DPGA_REG, 0, 0x3F, 0,
rx_tlv),
SOC_SINGLE_TLV("RX3 DPGA Volume", ISABELLE_RX3_DPGA_REG, 0, 0x3F, 0,
rx_tlv),
SOC_SINGLE_TLV("RX4 DPGA Volume", ISABELLE_RX4_DPGA_REG, 0, 0x3F, 0,
rx_tlv),
SOC_SINGLE_TLV("RX5 DPGA Volume", ISABELLE_RX5_DPGA_REG, 0, 0x3F, 0,
rx_tlv),
SOC_SINGLE_TLV("RX6 DPGA Volume", ISABELLE_RX6_DPGA_REG, 0, 0x3F, 0,
rx_tlv),
SOC_SINGLE("Headset Noise Gate", ISABELLE_HS_NG_CFG1_REG, 7, 1, 0),
SOC_SINGLE("Handsfree Noise Gate", ISABELLE_HF_NG_CFG1_REG, 7, 1, 0),
SOC_SINGLE("ATX1 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
7, 1, 0),
SOC_SINGLE("ATX2 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
6, 1, 0),
SOC_SINGLE("ARX1 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
5, 1, 0),
SOC_SINGLE("ARX2 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
4, 1, 0),
SOC_SINGLE("ARX3 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
3, 1, 0),
SOC_SINGLE("ARX4 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
2, 1, 0),
SOC_SINGLE("ARX5 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
1, 1, 0),
SOC_SINGLE("ARX6 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
0, 1, 0),
SOC_SINGLE("VRX1 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
3, 1, 0),
SOC_SINGLE("VRX2 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
2, 1, 0),
SOC_SINGLE("ATX1 Filter Enable Switch", ISABELLE_ALU_TX_EN_REG,
7, 1, 0),
SOC_SINGLE("ATX2 Filter Enable Switch", ISABELLE_ALU_TX_EN_REG,
6, 1, 0),
SOC_SINGLE("VTX1 Filter Enable Switch", ISABELLE_ALU_TX_EN_REG,
5, 1, 0),
SOC_SINGLE("VTX2 Filter Enable Switch", ISABELLE_ALU_TX_EN_REG,
4, 1, 0),
SOC_SINGLE("RX1 Filter Enable Switch", ISABELLE_ALU_RX_EN_REG,
5, 1, 0),
SOC_SINGLE("RX2 Filter Enable Switch", ISABELLE_ALU_RX_EN_REG,
4, 1, 0),
SOC_SINGLE("RX3 Filter Enable Switch", ISABELLE_ALU_RX_EN_REG,
3, 1, 0),
SOC_SINGLE("RX4 Filter Enable Switch", ISABELLE_ALU_RX_EN_REG,
2, 1, 0),
SOC_SINGLE("RX5 Filter Enable Switch", ISABELLE_ALU_RX_EN_REG,
1, 1, 0),
SOC_SINGLE("RX6 Filter Enable Switch", ISABELLE_ALU_RX_EN_REG,
0, 1, 0),
SOC_SINGLE("ULATX12 Capture Switch", ISABELLE_ULATX12_INTF_CFG_REG,
7, 1, 0),
SOC_SINGLE("DL12 Playback Switch", ISABELLE_DL12_INTF_CFG_REG,
7, 1, 0),
SOC_SINGLE("DL34 Playback Switch", ISABELLE_DL34_INTF_CFG_REG,
7, 1, 0),
SOC_SINGLE("DL56 Playback Switch", ISABELLE_DL56_INTF_CFG_REG,
7, 1, 0),
/* DMIC Switch */
SOC_SINGLE("DMIC Switch", ISABELLE_DMIC_CFG_REG, 0, 1, 0),
};
static const struct snd_soc_dapm_widget isabelle_dapm_widgets[] = {
/* Inputs */
SND_SOC_DAPM_INPUT("MAINMIC"),
SND_SOC_DAPM_INPUT("HSMIC"),
SND_SOC_DAPM_INPUT("SUBMIC"),
SND_SOC_DAPM_INPUT("LINEIN1"),
SND_SOC_DAPM_INPUT("LINEIN2"),
SND_SOC_DAPM_INPUT("DMICDAT"),
/* Outputs */
SND_SOC_DAPM_OUTPUT("HSOL"),
SND_SOC_DAPM_OUTPUT("HSOR"),
SND_SOC_DAPM_OUTPUT("HFL"),
SND_SOC_DAPM_OUTPUT("HFR"),
SND_SOC_DAPM_OUTPUT("EP"),
SND_SOC_DAPM_OUTPUT("LINEOUT1"),
SND_SOC_DAPM_OUTPUT("LINEOUT2"),
SND_SOC_DAPM_PGA("DL1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DL2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DL3", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DL4", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DL5", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DL6", SND_SOC_NOPM, 0, 0, NULL, 0),
/* Analog input muxes for the capture amplifiers */
SND_SOC_DAPM_MUX("Analog Left Capture Route",
SND_SOC_NOPM, 0, 0, &amic1_control),
SND_SOC_DAPM_MUX("Analog Right Capture Route",
SND_SOC_NOPM, 0, 0, &amic2_control),
SND_SOC_DAPM_MUX("Sidetone Audio Playback", SND_SOC_NOPM, 0, 0,
&st_audio_control),
SND_SOC_DAPM_MUX("Sidetone Voice Playback", SND_SOC_NOPM, 0, 0,
&st_voice_control),
/* AIF */
SND_SOC_DAPM_AIF_IN("INTF1_SDI", NULL, 0, ISABELLE_INTF_EN_REG, 7, 0),
SND_SOC_DAPM_AIF_IN("INTF2_SDI", NULL, 0, ISABELLE_INTF_EN_REG, 6, 0),
SND_SOC_DAPM_AIF_OUT("INTF1_SDO", NULL, 0, ISABELLE_INTF_EN_REG, 5, 0),
SND_SOC_DAPM_AIF_OUT("INTF2_SDO", NULL, 0, ISABELLE_INTF_EN_REG, 4, 0),
SND_SOC_DAPM_OUT_DRV("ULATX1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("ULATX2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("ULVTX1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("ULVTX2", SND_SOC_NOPM, 0, 0, NULL, 0),
/* Analog Capture PGAs */
SND_SOC_DAPM_PGA("MicAmp1", ISABELLE_AMIC_CFG_REG, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA("MicAmp2", ISABELLE_AMIC_CFG_REG, 4, 0, NULL, 0),
/* Auxiliary FM PGAs */
SND_SOC_DAPM_PGA("APGA1", ISABELLE_APGA_CFG_REG, 7, 0, NULL, 0),
SND_SOC_DAPM_PGA("APGA2", ISABELLE_APGA_CFG_REG, 6, 0, NULL, 0),
/* ADCs */
SND_SOC_DAPM_ADC("ADC1", "Left Front Capture",
ISABELLE_AMIC_CFG_REG, 7, 0),
SND_SOC_DAPM_ADC("ADC2", "Right Front Capture",
ISABELLE_AMIC_CFG_REG, 6, 0),
/* Microphone Bias */
SND_SOC_DAPM_SUPPLY("Headset Mic Bias", ISABELLE_ABIAS_CFG_REG,
3, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Main Mic Bias", ISABELLE_ABIAS_CFG_REG,
2, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Digital Mic1 Bias",
ISABELLE_DBIAS_CFG_REG, 3, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Digital Mic2 Bias",
ISABELLE_DBIAS_CFG_REG, 2, 0, NULL, 0),
/* Mixers */
SND_SOC_DAPM_MIXER("Headset Left Mixer", SND_SOC_NOPM, 0, 0,
isabelle_hs_left_mixer_controls,
ARRAY_SIZE(isabelle_hs_left_mixer_controls)),
SND_SOC_DAPM_MIXER("Headset Right Mixer", SND_SOC_NOPM, 0, 0,
isabelle_hs_right_mixer_controls,
ARRAY_SIZE(isabelle_hs_right_mixer_controls)),
SND_SOC_DAPM_MIXER("Handsfree Left Mixer", SND_SOC_NOPM, 0, 0,
isabelle_hf_left_mixer_controls,
ARRAY_SIZE(isabelle_hf_left_mixer_controls)),
SND_SOC_DAPM_MIXER("Handsfree Right Mixer", SND_SOC_NOPM, 0, 0,
isabelle_hf_right_mixer_controls,
ARRAY_SIZE(isabelle_hf_right_mixer_controls)),
SND_SOC_DAPM_MIXER("LINEOUT1 Mixer", SND_SOC_NOPM, 0, 0,
isabelle_aux_left_mixer_controls,
ARRAY_SIZE(isabelle_aux_left_mixer_controls)),
SND_SOC_DAPM_MIXER("LINEOUT2 Mixer", SND_SOC_NOPM, 0, 0,
isabelle_aux_right_mixer_controls,
ARRAY_SIZE(isabelle_aux_right_mixer_controls)),
SND_SOC_DAPM_MIXER("Earphone Mixer", SND_SOC_NOPM, 0, 0,
isabelle_ep_mixer_controls,
ARRAY_SIZE(isabelle_ep_mixer_controls)),
SND_SOC_DAPM_MIXER("DPGA1L Mixer", SND_SOC_NOPM, 0, 0,
isabelle_dpga1_left_mixer_controls,
ARRAY_SIZE(isabelle_dpga1_left_mixer_controls)),
SND_SOC_DAPM_MIXER("DPGA1R Mixer", SND_SOC_NOPM, 0, 0,
isabelle_dpga1_right_mixer_controls,
ARRAY_SIZE(isabelle_dpga1_right_mixer_controls)),
SND_SOC_DAPM_MIXER("DPGA2L Mixer", SND_SOC_NOPM, 0, 0,
isabelle_dpga2_left_mixer_controls,
ARRAY_SIZE(isabelle_dpga2_left_mixer_controls)),
SND_SOC_DAPM_MIXER("DPGA2R Mixer", SND_SOC_NOPM, 0, 0,
isabelle_dpga2_right_mixer_controls,
ARRAY_SIZE(isabelle_dpga2_right_mixer_controls)),
SND_SOC_DAPM_MIXER("DPGA3L Mixer", SND_SOC_NOPM, 0, 0,
isabelle_dpga3_left_mixer_controls,
ARRAY_SIZE(isabelle_dpga3_left_mixer_controls)),
SND_SOC_DAPM_MIXER("DPGA3R Mixer", SND_SOC_NOPM, 0, 0,
isabelle_dpga3_right_mixer_controls,
ARRAY_SIZE(isabelle_dpga3_right_mixer_controls)),
SND_SOC_DAPM_MIXER("RX1 Mixer", SND_SOC_NOPM, 0, 0,
isabelle_rx1_mixer_controls,
ARRAY_SIZE(isabelle_rx1_mixer_controls)),
SND_SOC_DAPM_MIXER("RX2 Mixer", SND_SOC_NOPM, 0, 0,
isabelle_rx2_mixer_controls,
ARRAY_SIZE(isabelle_rx2_mixer_controls)),
SND_SOC_DAPM_MIXER("RX3 Mixer", SND_SOC_NOPM, 0, 0,
isabelle_rx3_mixer_controls,
ARRAY_SIZE(isabelle_rx3_mixer_controls)),
SND_SOC_DAPM_MIXER("RX4 Mixer", SND_SOC_NOPM, 0, 0,
isabelle_rx4_mixer_controls,
ARRAY_SIZE(isabelle_rx4_mixer_controls)),
SND_SOC_DAPM_MIXER("RX5 Mixer", SND_SOC_NOPM, 0, 0,
isabelle_rx5_mixer_controls,
ARRAY_SIZE(isabelle_rx5_mixer_controls)),
SND_SOC_DAPM_MIXER("RX6 Mixer", SND_SOC_NOPM, 0, 0,
isabelle_rx6_mixer_controls,
ARRAY_SIZE(isabelle_rx6_mixer_controls)),
/* DACs */
SND_SOC_DAPM_DAC("DAC1L", "Headset Playback", ISABELLE_DAC_CFG_REG,
5, 0),
SND_SOC_DAPM_DAC("DAC1R", "Headset Playback", ISABELLE_DAC_CFG_REG,
4, 0),
SND_SOC_DAPM_DAC("DAC2L", "Handsfree Playback", ISABELLE_DAC_CFG_REG,
3, 0),
SND_SOC_DAPM_DAC("DAC2R", "Handsfree Playback", ISABELLE_DAC_CFG_REG,
2, 0),
SND_SOC_DAPM_DAC("DAC3L", "Lineout Playback", ISABELLE_DAC_CFG_REG,
1, 0),
SND_SOC_DAPM_DAC("DAC3R", "Lineout Playback", ISABELLE_DAC_CFG_REG,
0, 0),
/* Analog Playback PGAs */
SND_SOC_DAPM_PGA("Sidetone Audio PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Sidetone Voice PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("HF Left PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("HF Right PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DPGA1L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DPGA1R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DPGA2L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DPGA2R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DPGA3L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DPGA3R", SND_SOC_NOPM, 0, 0, NULL, 0),
/* Analog Playback Mux */
SND_SOC_DAPM_MUX("RX1 Playback", ISABELLE_ALU_RX_EN_REG, 5, 0,
&rx1_mux_controls),
SND_SOC_DAPM_MUX("RX2 Playback", ISABELLE_ALU_RX_EN_REG, 4, 0,
&rx2_mux_controls),
/* TX Select */
SND_SOC_DAPM_MUX("ATX Select", ISABELLE_TX_INPUT_CFG_REG,
7, 0, &atx_mux_controls),
SND_SOC_DAPM_MUX("VTX Select", ISABELLE_TX_INPUT_CFG_REG,
6, 0, &vtx_mux_controls),
SND_SOC_DAPM_SWITCH("Earphone Playback", SND_SOC_NOPM, 0, 0,
&ep_path_enable_control),
/* Output Drivers */
SND_SOC_DAPM_OUT_DRV("HS Left Driver", ISABELLE_HSDRV_CFG2_REG,
1, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("HS Right Driver", ISABELLE_HSDRV_CFG2_REG,
0, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("LINEOUT1 Left Driver", ISABELLE_LINEAMP_CFG_REG,
1, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("LINEOUT2 Right Driver", ISABELLE_LINEAMP_CFG_REG,
0, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("Earphone Driver", ISABELLE_EARDRV_CFG2_REG,
1, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("HF Left Driver", ISABELLE_HFDRV_CFG_REG,
1, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("HF Right Driver", ISABELLE_HFDRV_CFG_REG,
0, 0, NULL, 0),
};
static const struct snd_soc_dapm_route isabelle_intercon[] = {
/* Interface mapping */
{ "DL1", "DL12 Playback Switch", "INTF1_SDI" },
{ "DL2", "DL12 Playback Switch", "INTF1_SDI" },
{ "DL3", "DL34 Playback Switch", "INTF1_SDI" },
{ "DL4", "DL34 Playback Switch", "INTF1_SDI" },
{ "DL5", "DL56 Playback Switch", "INTF1_SDI" },
{ "DL6", "DL56 Playback Switch", "INTF1_SDI" },
{ "DL1", "DL12 Playback Switch", "INTF2_SDI" },
{ "DL2", "DL12 Playback Switch", "INTF2_SDI" },
{ "DL3", "DL34 Playback Switch", "INTF2_SDI" },
{ "DL4", "DL34 Playback Switch", "INTF2_SDI" },
{ "DL5", "DL56 Playback Switch", "INTF2_SDI" },
{ "DL6", "DL56 Playback Switch", "INTF2_SDI" },
/* Input side mapping */
{ "Sidetone Audio PGA", NULL, "Sidetone Audio Playback" },
{ "Sidetone Voice PGA", NULL, "Sidetone Voice Playback" },
{ "RX1 Mixer", "ST1 Playback Switch", "Sidetone Audio PGA" },
{ "RX1 Mixer", "ST1 Playback Switch", "Sidetone Voice PGA" },
{ "RX1 Mixer", "DL1 Playback Switch", "DL1" },
{ "RX2 Mixer", "ST2 Playback Switch", "Sidetone Audio PGA" },
{ "RX2 Mixer", "ST2 Playback Switch", "Sidetone Voice PGA" },
{ "RX2 Mixer", "DL2 Playback Switch", "DL2" },
{ "RX3 Mixer", "ST1 Playback Switch", "Sidetone Voice PGA" },
{ "RX3 Mixer", "DL3 Playback Switch", "DL3" },
{ "RX4 Mixer", "ST2 Playback Switch", "Sidetone Voice PGA" },
{ "RX4 Mixer", "DL4 Playback Switch", "DL4" },
{ "RX5 Mixer", "ST1 Playback Switch", "Sidetone Voice PGA" },
{ "RX5 Mixer", "DL5 Playback Switch", "DL5" },
{ "RX6 Mixer", "ST2 Playback Switch", "Sidetone Voice PGA" },
{ "RX6 Mixer", "DL6 Playback Switch", "DL6" },
/* Capture path */
{ "Analog Left Capture Route", "Headset Mic", "HSMIC" },
{ "Analog Left Capture Route", "Main Mic", "MAINMIC" },
{ "Analog Left Capture Route", "Aux/FM Left", "LINEIN1" },
{ "Analog Right Capture Route", "Sub Mic", "SUBMIC" },
{ "Analog Right Capture Route", "Aux/FM Right", "LINEIN2" },
{ "MicAmp1", NULL, "Analog Left Capture Route" },
{ "MicAmp2", NULL, "Analog Right Capture Route" },
{ "ADC1", NULL, "MicAmp1" },
{ "ADC2", NULL, "MicAmp2" },
{ "ATX Select", "AMIC1", "ADC1" },
{ "ATX Select", "DMIC", "DMICDAT" },
{ "ATX Select", "AMIC2", "ADC2" },
{ "VTX Select", "AMIC1", "ADC1" },
{ "VTX Select", "DMIC", "DMICDAT" },
{ "VTX Select", "AMIC2", "ADC2" },
{ "ULATX1", "ATX1 Filter Enable Switch", "ATX Select" },
{ "ULATX1", "ATX1 Filter Bypass Switch", "ATX Select" },
{ "ULATX2", "ATX2 Filter Enable Switch", "ATX Select" },
{ "ULATX2", "ATX2 Filter Bypass Switch", "ATX Select" },
{ "ULVTX1", "VTX1 Filter Enable Switch", "VTX Select" },
{ "ULVTX1", "VTX1 Filter Bypass Switch", "VTX Select" },
{ "ULVTX2", "VTX2 Filter Enable Switch", "VTX Select" },
{ "ULVTX2", "VTX2 Filter Bypass Switch", "VTX Select" },
{ "INTF1_SDO", "ULATX12 Capture Switch", "ULATX1" },
{ "INTF1_SDO", "ULATX12 Capture Switch", "ULATX2" },
{ "INTF2_SDO", "ULATX12 Capture Switch", "ULATX1" },
{ "INTF2_SDO", "ULATX12 Capture Switch", "ULATX2" },
{ "INTF1_SDO", NULL, "ULVTX1" },
{ "INTF1_SDO", NULL, "ULVTX2" },
{ "INTF2_SDO", NULL, "ULVTX1" },
{ "INTF2_SDO", NULL, "ULVTX2" },
/* AFM Path */
{ "APGA1", NULL, "LINEIN1" },
{ "APGA2", NULL, "LINEIN2" },
{ "RX1 Playback", "VRX1 Filter Bypass Switch", "RX1 Mixer" },
{ "RX1 Playback", "ARX1 Filter Bypass Switch", "RX1 Mixer" },
{ "RX1 Playback", "RX1 Filter Enable Switch", "RX1 Mixer" },
{ "RX2 Playback", "VRX2 Filter Bypass Switch", "RX2 Mixer" },
{ "RX2 Playback", "ARX2 Filter Bypass Switch", "RX2 Mixer" },
{ "RX2 Playback", "RX2 Filter Enable Switch", "RX2 Mixer" },
{ "RX3 Playback", "ARX3 Filter Bypass Switch", "RX3 Mixer" },
{ "RX3 Playback", "RX3 Filter Enable Switch", "RX3 Mixer" },
{ "RX4 Playback", "ARX4 Filter Bypass Switch", "RX4 Mixer" },
{ "RX4 Playback", "RX4 Filter Enable Switch", "RX4 Mixer" },
{ "RX5 Playback", "ARX5 Filter Bypass Switch", "RX5 Mixer" },
{ "RX5 Playback", "RX5 Filter Enable Switch", "RX5 Mixer" },
{ "RX6 Playback", "ARX6 Filter Bypass Switch", "RX6 Mixer" },
{ "RX6 Playback", "RX6 Filter Enable Switch", "RX6 Mixer" },
{ "DPGA1L Mixer", "RX1 Playback Switch", "RX1 Playback" },
{ "DPGA1L Mixer", "RX3 Playback Switch", "RX3 Playback" },
{ "DPGA1L Mixer", "RX5 Playback Switch", "RX5 Playback" },
{ "DPGA1R Mixer", "RX2 Playback Switch", "RX2 Playback" },
{ "DPGA1R Mixer", "RX4 Playback Switch", "RX4 Playback" },
{ "DPGA1R Mixer", "RX6 Playback Switch", "RX6 Playback" },
{ "DPGA1L", NULL, "DPGA1L Mixer" },
{ "DPGA1R", NULL, "DPGA1R Mixer" },
{ "DAC1L", NULL, "DPGA1L" },
{ "DAC1R", NULL, "DPGA1R" },
{ "DPGA2L Mixer", "RX1 Playback Switch", "RX1 Playback" },
{ "DPGA2L Mixer", "RX2 Playback Switch", "RX2 Playback" },
{ "DPGA2L Mixer", "RX3 Playback Switch", "RX3 Playback" },
{ "DPGA2L Mixer", "RX4 Playback Switch", "RX4 Playback" },
{ "DPGA2L Mixer", "RX5 Playback Switch", "RX5 Playback" },
{ "DPGA2L Mixer", "RX6 Playback Switch", "RX6 Playback" },
{ "DPGA2R Mixer", "RX2 Playback Switch", "RX2 Playback" },
{ "DPGA2R Mixer", "RX4 Playback Switch", "RX4 Playback" },
{ "DPGA2R Mixer", "RX6 Playback Switch", "RX6 Playback" },
{ "DPGA2L", NULL, "DPGA2L Mixer" },
{ "DPGA2R", NULL, "DPGA2R Mixer" },
{ "DAC2L", NULL, "DPGA2L" },
{ "DAC2R", NULL, "DPGA2R" },
{ "DPGA3L Mixer", "RX1 Playback Switch", "RX1 Playback" },
{ "DPGA3L Mixer", "RX3 Playback Switch", "RX3 Playback" },
{ "DPGA3L Mixer", "RX5 Playback Switch", "RX5 Playback" },
{ "DPGA3R Mixer", "RX2 Playback Switch", "RX2 Playback" },
{ "DPGA3R Mixer", "RX4 Playback Switch", "RX4 Playback" },
{ "DPGA3R Mixer", "RX6 Playback Switch", "RX6 Playback" },
{ "DPGA3L", NULL, "DPGA3L Mixer" },
{ "DPGA3R", NULL, "DPGA3R Mixer" },
{ "DAC3L", NULL, "DPGA3L" },
{ "DAC3R", NULL, "DPGA3R" },
{ "Headset Left Mixer", "DAC1L Playback Switch", "DAC1L" },
{ "Headset Left Mixer", "APGA1 Playback Switch", "APGA1" },
{ "Headset Right Mixer", "DAC1R Playback Switch", "DAC1R" },
{ "Headset Right Mixer", "APGA2 Playback Switch", "APGA2" },
{ "HS Left Driver", NULL, "Headset Left Mixer" },
{ "HS Right Driver", NULL, "Headset Right Mixer" },
{ "HSOL", NULL, "HS Left Driver" },
{ "HSOR", NULL, "HS Right Driver" },
/* Earphone playback path */
{ "Earphone Mixer", "DAC2L Playback Switch", "DAC2L" },
{ "Earphone Mixer", "APGA1 Playback Switch", "APGA1" },
{ "Earphone Playback", "Switch", "Earphone Mixer" },
{ "Earphone Driver", NULL, "Earphone Playback" },
{ "EP", NULL, "Earphone Driver" },
{ "Handsfree Left Mixer", "DAC2L Playback Switch", "DAC2L" },
{ "Handsfree Left Mixer", "APGA1 Playback Switch", "APGA1" },
{ "Handsfree Right Mixer", "DAC2R Playback Switch", "DAC2R" },
{ "Handsfree Right Mixer", "APGA2 Playback Switch", "APGA2" },
{ "HF Left PGA", NULL, "Handsfree Left Mixer" },
{ "HF Right PGA", NULL, "Handsfree Right Mixer" },
{ "HF Left Driver", NULL, "HF Left PGA" },
{ "HF Right Driver", NULL, "HF Right PGA" },
{ "HFL", NULL, "HF Left Driver" },
{ "HFR", NULL, "HF Right Driver" },
{ "LINEOUT1 Mixer", "DAC3L Playback Switch", "DAC3L" },
{ "LINEOUT1 Mixer", "APGA1 Playback Switch", "APGA1" },
{ "LINEOUT2 Mixer", "DAC3R Playback Switch", "DAC3R" },
{ "LINEOUT2 Mixer", "APGA2 Playback Switch", "APGA2" },
{ "LINEOUT1 Driver", NULL, "LINEOUT1 Mixer" },
{ "LINEOUT2 Driver", NULL, "LINEOUT2 Mixer" },
{ "LINEOUT1", NULL, "LINEOUT1 Driver" },
{ "LINEOUT2", NULL, "LINEOUT2 Driver" },
};
static int isabelle_hs_mute(struct snd_soc_dai *dai, int mute, int direction)
{
snd_soc_component_update_bits(dai->component, ISABELLE_DAC1_SOFTRAMP_REG,
BIT(4), (mute ? BIT(4) : 0));
return 0;
}
static int isabelle_hf_mute(struct snd_soc_dai *dai, int mute, int direction)
{
snd_soc_component_update_bits(dai->component, ISABELLE_DAC2_SOFTRAMP_REG,
BIT(4), (mute ? BIT(4) : 0));
return 0;
}
static int isabelle_line_mute(struct snd_soc_dai *dai, int mute, int direction)
{
snd_soc_component_update_bits(dai->component, ISABELLE_DAC3_SOFTRAMP_REG,
BIT(4), (mute ? BIT(4) : 0));
return 0;
}
static int isabelle_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
snd_soc_component_update_bits(component, ISABELLE_PWR_EN_REG,
ISABELLE_CHIP_EN, BIT(0));
break;
case SND_SOC_BIAS_OFF:
snd_soc_component_update_bits(component, ISABELLE_PWR_EN_REG,
ISABELLE_CHIP_EN, 0);
break;
}
return 0;
}
static int isabelle_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
u16 aif = 0;
unsigned int fs_val = 0;
switch (params_rate(params)) {
case 8000:
fs_val = ISABELLE_FS_RATE_8;
break;
case 11025:
fs_val = ISABELLE_FS_RATE_11;
break;
case 12000:
fs_val = ISABELLE_FS_RATE_12;
break;
case 16000:
fs_val = ISABELLE_FS_RATE_16;
break;
case 22050:
fs_val = ISABELLE_FS_RATE_22;
break;
case 24000:
fs_val = ISABELLE_FS_RATE_24;
break;
case 32000:
fs_val = ISABELLE_FS_RATE_32;
break;
case 44100:
fs_val = ISABELLE_FS_RATE_44;
break;
case 48000:
fs_val = ISABELLE_FS_RATE_48;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, ISABELLE_FS_RATE_CFG_REG,
ISABELLE_FS_RATE_MASK, fs_val);
/* bit size */
switch (params_width(params)) {
case 20:
aif |= ISABELLE_AIF_LENGTH_20;
break;
case 32:
aif |= ISABELLE_AIF_LENGTH_32;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, ISABELLE_INTF_CFG_REG,
ISABELLE_AIF_LENGTH_MASK, aif);
return 0;
}
static int isabelle_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
unsigned int aif_val = 0;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC:
aif_val &= ~ISABELLE_AIF_MS;
break;
case SND_SOC_DAIFMT_CBP_CFP:
aif_val |= ISABELLE_AIF_MS;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
aif_val |= ISABELLE_I2S_MODE;
break;
case SND_SOC_DAIFMT_LEFT_J:
aif_val |= ISABELLE_LEFT_J_MODE;
break;
case SND_SOC_DAIFMT_PDM:
aif_val |= ISABELLE_PDM_MODE;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, ISABELLE_INTF_CFG_REG,
(ISABELLE_AIF_MS | ISABELLE_AIF_FMT_MASK), aif_val);
return 0;
}
/* Rates supported by Isabelle driver */
#define ISABELLE_RATES SNDRV_PCM_RATE_8000_48000
/* Formates supported by Isabelle driver. */
#define ISABELLE_FORMATS (SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops isabelle_hs_dai_ops = {
.hw_params = isabelle_hw_params,
.set_fmt = isabelle_set_dai_fmt,
.mute_stream = isabelle_hs_mute,
.no_capture_mute = 1,
};
static const struct snd_soc_dai_ops isabelle_hf_dai_ops = {
.hw_params = isabelle_hw_params,
.set_fmt = isabelle_set_dai_fmt,
.mute_stream = isabelle_hf_mute,
.no_capture_mute = 1,
};
static const struct snd_soc_dai_ops isabelle_line_dai_ops = {
.hw_params = isabelle_hw_params,
.set_fmt = isabelle_set_dai_fmt,
.mute_stream = isabelle_line_mute,
.no_capture_mute = 1,
};
static const struct snd_soc_dai_ops isabelle_ul_dai_ops = {
.hw_params = isabelle_hw_params,
.set_fmt = isabelle_set_dai_fmt,
};
/* ISABELLE dai structure */
static struct snd_soc_dai_driver isabelle_dai[] = {
{
.name = "isabelle-dl1",
.playback = {
.stream_name = "Headset Playback",
.channels_min = 1,
.channels_max = 2,
.rates = ISABELLE_RATES,
.formats = ISABELLE_FORMATS,
},
.ops = &isabelle_hs_dai_ops,
},
{
.name = "isabelle-dl2",
.playback = {
.stream_name = "Handsfree Playback",
.channels_min = 1,
.channels_max = 2,
.rates = ISABELLE_RATES,
.formats = ISABELLE_FORMATS,
},
.ops = &isabelle_hf_dai_ops,
},
{
.name = "isabelle-lineout",
.playback = {
.stream_name = "Lineout Playback",
.channels_min = 1,
.channels_max = 2,
.rates = ISABELLE_RATES,
.formats = ISABELLE_FORMATS,
},
.ops = &isabelle_line_dai_ops,
},
{
.name = "isabelle-ul",
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = ISABELLE_RATES,
.formats = ISABELLE_FORMATS,
},
.ops = &isabelle_ul_dai_ops,
},
};
static const struct snd_soc_component_driver soc_component_dev_isabelle = {
.set_bias_level = isabelle_set_bias_level,
.controls = isabelle_snd_controls,
.num_controls = ARRAY_SIZE(isabelle_snd_controls),
.dapm_widgets = isabelle_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(isabelle_dapm_widgets),
.dapm_routes = isabelle_intercon,
.num_dapm_routes = ARRAY_SIZE(isabelle_intercon),
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config isabelle_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = ISABELLE_MAX_REGISTER,
.reg_defaults = isabelle_reg_defs,
.num_reg_defaults = ARRAY_SIZE(isabelle_reg_defs),
.cache_type = REGCACHE_RBTREE,
};
static int isabelle_i2c_probe(struct i2c_client *i2c)
{
struct regmap *isabelle_regmap;
int ret = 0;
isabelle_regmap = devm_regmap_init_i2c(i2c, &isabelle_regmap_config);
if (IS_ERR(isabelle_regmap)) {
ret = PTR_ERR(isabelle_regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
i2c_set_clientdata(i2c, isabelle_regmap);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_isabelle, isabelle_dai,
ARRAY_SIZE(isabelle_dai));
if (ret < 0) {
dev_err(&i2c->dev, "Failed to register component: %d\n", ret);
return ret;
}
return ret;
}
static const struct i2c_device_id isabelle_i2c_id[] = {
{ "isabelle", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, isabelle_i2c_id);
static struct i2c_driver isabelle_i2c_driver = {
.driver = {
.name = "isabelle",
},
.probe = isabelle_i2c_probe,
.id_table = isabelle_i2c_id,
};
module_i2c_driver(isabelle_i2c_driver);
MODULE_DESCRIPTION("ASoC ISABELLE driver");
MODULE_AUTHOR("Vishwas A Deshpande <[email protected]>");
MODULE_AUTHOR("M R Swami Reddy <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/isabelle.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017 BayLibre, SAS.
* Author: Jerome Brunet <[email protected]>
*/
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/regulator/consumer.h>
#include <sound/soc.h>
#define DRV_NAME "simple-amplifier"
struct simple_amp {
struct gpio_desc *gpiod_enable;
};
static int drv_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *control, int event)
{
struct snd_soc_component *c = snd_soc_dapm_to_component(w->dapm);
struct simple_amp *priv = snd_soc_component_get_drvdata(c);
int val;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
val = 1;
break;
case SND_SOC_DAPM_PRE_PMD:
val = 0;
break;
default:
WARN(1, "Unexpected event");
return -EINVAL;
}
gpiod_set_value_cansleep(priv->gpiod_enable, val);
return 0;
}
static const struct snd_soc_dapm_widget simple_amp_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("INL"),
SND_SOC_DAPM_INPUT("INR"),
SND_SOC_DAPM_OUT_DRV_E("DRV", SND_SOC_NOPM, 0, 0, NULL, 0, drv_event,
(SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD)),
SND_SOC_DAPM_OUTPUT("OUTL"),
SND_SOC_DAPM_OUTPUT("OUTR"),
SND_SOC_DAPM_REGULATOR_SUPPLY("VCC", 20, 0),
};
static const struct snd_soc_dapm_route simple_amp_dapm_routes[] = {
{ "DRV", NULL, "INL" },
{ "DRV", NULL, "INR" },
{ "OUTL", NULL, "VCC" },
{ "OUTR", NULL, "VCC" },
{ "OUTL", NULL, "DRV" },
{ "OUTR", NULL, "DRV" },
};
static const struct snd_soc_component_driver simple_amp_component_driver = {
.dapm_widgets = simple_amp_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(simple_amp_dapm_widgets),
.dapm_routes = simple_amp_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(simple_amp_dapm_routes),
};
static int simple_amp_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct simple_amp *priv;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (priv == NULL)
return -ENOMEM;
platform_set_drvdata(pdev, priv);
priv->gpiod_enable = devm_gpiod_get_optional(dev, "enable",
GPIOD_OUT_LOW);
if (IS_ERR(priv->gpiod_enable))
return dev_err_probe(dev, PTR_ERR(priv->gpiod_enable),
"Failed to get 'enable' gpio");
return devm_snd_soc_register_component(dev,
&simple_amp_component_driver,
NULL, 0);
}
#ifdef CONFIG_OF
static const struct of_device_id simple_amp_ids[] = {
{ .compatible = "dioo,dio2125", },
{ .compatible = "simple-audio-amplifier", },
{ }
};
MODULE_DEVICE_TABLE(of, simple_amp_ids);
#endif
static struct platform_driver simple_amp_driver = {
.driver = {
.name = DRV_NAME,
.of_match_table = of_match_ptr(simple_amp_ids),
},
.probe = simple_amp_probe,
};
module_platform_driver(simple_amp_driver);
MODULE_DESCRIPTION("ASoC Simple Audio Amplifier driver");
MODULE_AUTHOR("Jerome Brunet <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/simple-amplifier.c |
/*
* Cirrus Logic CS42448/CS42888 Audio CODEC DAI I2C driver
*
* Copyright (C) 2014 Freescale Semiconductor, Inc.
*
* Author: Nicolin Chen <[email protected]>
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/pm_runtime.h>
#include <sound/soc.h>
#include "cs42xx8.h"
static const struct of_device_id cs42xx8_of_match[];
static int cs42xx8_i2c_probe(struct i2c_client *i2c)
{
int ret;
struct cs42xx8_driver_data *drvdata;
const struct of_device_id *of_id;
of_id = of_match_device(cs42xx8_of_match, &i2c->dev);
if (!of_id) {
dev_err(&i2c->dev, "failed to find driver data\n");
return -EINVAL;
}
drvdata = (struct cs42xx8_driver_data *)of_id->data;
ret = cs42xx8_probe(&i2c->dev,
devm_regmap_init_i2c(i2c, &cs42xx8_regmap_config), drvdata);
if (ret)
return ret;
pm_runtime_enable(&i2c->dev);
pm_request_idle(&i2c->dev);
return 0;
}
static void cs42xx8_i2c_remove(struct i2c_client *i2c)
{
pm_runtime_disable(&i2c->dev);
}
static const struct of_device_id cs42xx8_of_match[] = {
{ .compatible = "cirrus,cs42448", .data = &cs42448_data, },
{ .compatible = "cirrus,cs42888", .data = &cs42888_data, },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, cs42xx8_of_match);
static const struct i2c_device_id cs42xx8_i2c_id[] = {
{"cs42448", (kernel_ulong_t)&cs42448_data},
{"cs42888", (kernel_ulong_t)&cs42888_data},
{}
};
MODULE_DEVICE_TABLE(i2c, cs42xx8_i2c_id);
static struct i2c_driver cs42xx8_i2c_driver = {
.driver = {
.name = "cs42xx8",
.pm = &cs42xx8_pm,
.of_match_table = cs42xx8_of_match,
},
.probe = cs42xx8_i2c_probe,
.remove = cs42xx8_i2c_remove,
.id_table = cs42xx8_i2c_id,
};
module_i2c_driver(cs42xx8_i2c_driver);
MODULE_DESCRIPTION("Cirrus Logic CS42448/CS42888 ALSA SoC Codec I2C Driver");
MODULE_AUTHOR("Freescale Semiconductor, Inc.");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cs42xx8-i2c.c |
// SPDX-License-Identifier: GPL-2.0
//
// ROHM BD28623MUV class D speaker amplifier codec driver.
//
// Copyright (c) 2018 Socionext Inc.
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regulator/consumer.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#define BD28623_NUM_SUPPLIES 3
static const char *const bd28623_supply_names[BD28623_NUM_SUPPLIES] = {
"VCCA",
"VCCP1",
"VCCP2",
};
struct bd28623_priv {
struct device *dev;
struct regulator_bulk_data supplies[BD28623_NUM_SUPPLIES];
struct gpio_desc *reset_gpio;
struct gpio_desc *mute_gpio;
int switch_spk;
};
static const struct snd_soc_dapm_widget bd28623_widgets[] = {
SND_SOC_DAPM_DAC("DAC", "Playback", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_OUTPUT("OUT1P"),
SND_SOC_DAPM_OUTPUT("OUT1N"),
SND_SOC_DAPM_OUTPUT("OUT2P"),
SND_SOC_DAPM_OUTPUT("OUT2N"),
};
static const struct snd_soc_dapm_route bd28623_routes[] = {
{ "OUT1P", NULL, "DAC" },
{ "OUT1N", NULL, "DAC" },
{ "OUT2P", NULL, "DAC" },
{ "OUT2N", NULL, "DAC" },
};
static int bd28623_power_on(struct bd28623_priv *bd)
{
int ret;
ret = regulator_bulk_enable(ARRAY_SIZE(bd->supplies), bd->supplies);
if (ret) {
dev_err(bd->dev, "Failed to enable supplies: %d\n", ret);
return ret;
}
gpiod_set_value_cansleep(bd->reset_gpio, 0);
usleep_range(300000, 400000);
return 0;
}
static void bd28623_power_off(struct bd28623_priv *bd)
{
gpiod_set_value_cansleep(bd->reset_gpio, 1);
regulator_bulk_disable(ARRAY_SIZE(bd->supplies), bd->supplies);
}
static int bd28623_get_switch_spk(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct bd28623_priv *bd = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = bd->switch_spk;
return 0;
}
static int bd28623_set_switch_spk(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct bd28623_priv *bd = snd_soc_component_get_drvdata(component);
if (bd->switch_spk == ucontrol->value.integer.value[0])
return 0;
bd->switch_spk = ucontrol->value.integer.value[0];
gpiod_set_value_cansleep(bd->mute_gpio, bd->switch_spk ? 0 : 1);
return 0;
}
static const struct snd_kcontrol_new bd28623_controls[] = {
SOC_SINGLE_BOOL_EXT("Speaker Switch", 0,
bd28623_get_switch_spk, bd28623_set_switch_spk),
};
static int bd28623_codec_probe(struct snd_soc_component *component)
{
struct bd28623_priv *bd = snd_soc_component_get_drvdata(component);
int ret;
bd->switch_spk = 1;
ret = bd28623_power_on(bd);
if (ret)
return ret;
gpiod_set_value_cansleep(bd->mute_gpio, bd->switch_spk ? 0 : 1);
return 0;
}
static void bd28623_codec_remove(struct snd_soc_component *component)
{
struct bd28623_priv *bd = snd_soc_component_get_drvdata(component);
bd28623_power_off(bd);
}
static int bd28623_codec_suspend(struct snd_soc_component *component)
{
struct bd28623_priv *bd = snd_soc_component_get_drvdata(component);
bd28623_power_off(bd);
return 0;
}
static int bd28623_codec_resume(struct snd_soc_component *component)
{
struct bd28623_priv *bd = snd_soc_component_get_drvdata(component);
int ret;
ret = bd28623_power_on(bd);
if (ret)
return ret;
gpiod_set_value_cansleep(bd->mute_gpio, bd->switch_spk ? 0 : 1);
return 0;
}
static const struct snd_soc_component_driver soc_codec_bd = {
.probe = bd28623_codec_probe,
.remove = bd28623_codec_remove,
.suspend = bd28623_codec_suspend,
.resume = bd28623_codec_resume,
.dapm_widgets = bd28623_widgets,
.num_dapm_widgets = ARRAY_SIZE(bd28623_widgets),
.dapm_routes = bd28623_routes,
.num_dapm_routes = ARRAY_SIZE(bd28623_routes),
.controls = bd28623_controls,
.num_controls = ARRAY_SIZE(bd28623_controls),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static struct snd_soc_dai_driver soc_dai_bd = {
.name = "bd28623-speaker",
.playback = {
.stream_name = "Playback",
.formats = SNDRV_PCM_FMTBIT_S32_LE |
SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S16_LE,
.rates = SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_44100 |
SNDRV_PCM_RATE_32000,
.channels_min = 2,
.channels_max = 2,
},
};
static int bd28623_probe(struct platform_device *pdev)
{
struct bd28623_priv *bd;
struct device *dev = &pdev->dev;
int i, ret;
bd = devm_kzalloc(&pdev->dev, sizeof(struct bd28623_priv), GFP_KERNEL);
if (!bd)
return -ENOMEM;
for (i = 0; i < ARRAY_SIZE(bd->supplies); i++)
bd->supplies[i].supply = bd28623_supply_names[i];
ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(bd->supplies),
bd->supplies);
if (ret) {
dev_err(dev, "Failed to get supplies: %d\n", ret);
return ret;
}
bd->reset_gpio = devm_gpiod_get_optional(dev, "reset",
GPIOD_OUT_HIGH);
if (IS_ERR(bd->reset_gpio)) {
dev_err(dev, "Failed to request reset_gpio: %ld\n",
PTR_ERR(bd->reset_gpio));
return PTR_ERR(bd->reset_gpio);
}
bd->mute_gpio = devm_gpiod_get_optional(dev, "mute",
GPIOD_OUT_HIGH);
if (IS_ERR(bd->mute_gpio)) {
dev_err(dev, "Failed to request mute_gpio: %ld\n",
PTR_ERR(bd->mute_gpio));
return PTR_ERR(bd->mute_gpio);
}
platform_set_drvdata(pdev, bd);
bd->dev = dev;
return devm_snd_soc_register_component(dev, &soc_codec_bd,
&soc_dai_bd, 1);
}
static const struct of_device_id bd28623_of_match[] __maybe_unused = {
{ .compatible = "rohm,bd28623", },
{}
};
MODULE_DEVICE_TABLE(of, bd28623_of_match);
static struct platform_driver bd28623_codec_driver = {
.driver = {
.name = "bd28623",
.of_match_table = of_match_ptr(bd28623_of_match),
},
.probe = bd28623_probe,
};
module_platform_driver(bd28623_codec_driver);
MODULE_AUTHOR("Katsuhiro Suzuki <[email protected]>");
MODULE_DESCRIPTION("ROHM BD28623 speaker amplifier driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/bd28623.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// ALSA SoC Audio driver for CS47L35 codec
//
// Copyright (C) 2015-2019 Cirrus Logic, Inc. and
// Cirrus Logic International Semiconductor Ltd.
//
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <linux/irqchip/irq-madera.h>
#include <linux/mfd/madera/core.h>
#include <linux/mfd/madera/registers.h>
#include "madera.h"
#include "wm_adsp.h"
#define CS47L35_NUM_ADSP 3
#define CS47L35_MONO_OUTPUTS 1
#define DRV_NAME "cs47l35-codec"
struct cs47l35 {
struct madera_priv core;
struct madera_fll fll;
};
static const struct cs_dsp_region cs47l35_dsp1_regions[] = {
{ .type = WMFW_ADSP2_PM, .base = 0x080000 },
{ .type = WMFW_ADSP2_ZM, .base = 0x0e0000 },
{ .type = WMFW_ADSP2_XM, .base = 0x0a0000 },
{ .type = WMFW_ADSP2_YM, .base = 0x0c0000 },
};
static const struct cs_dsp_region cs47l35_dsp2_regions[] = {
{ .type = WMFW_ADSP2_PM, .base = 0x100000 },
{ .type = WMFW_ADSP2_ZM, .base = 0x160000 },
{ .type = WMFW_ADSP2_XM, .base = 0x120000 },
{ .type = WMFW_ADSP2_YM, .base = 0x140000 },
};
static const struct cs_dsp_region cs47l35_dsp3_regions[] = {
{ .type = WMFW_ADSP2_PM, .base = 0x180000 },
{ .type = WMFW_ADSP2_ZM, .base = 0x1e0000 },
{ .type = WMFW_ADSP2_XM, .base = 0x1a0000 },
{ .type = WMFW_ADSP2_YM, .base = 0x1c0000 },
};
static const struct cs_dsp_region *cs47l35_dsp_regions[] = {
cs47l35_dsp1_regions,
cs47l35_dsp2_regions,
cs47l35_dsp3_regions,
};
static const int wm_adsp2_control_bases[] = {
MADERA_DSP1_CONFIG_1,
MADERA_DSP2_CONFIG_1,
MADERA_DSP3_CONFIG_1,
};
static const char * const cs47l35_outdemux_texts[] = {
"HPOUT",
"EPOUT",
};
static SOC_ENUM_SINGLE_DECL(cs47l35_outdemux_enum, SND_SOC_NOPM, 0,
cs47l35_outdemux_texts);
static const struct snd_kcontrol_new cs47l35_outdemux =
SOC_DAPM_ENUM_EXT("HPOUT1 Demux", cs47l35_outdemux_enum,
madera_out1_demux_get, madera_out1_demux_put);
static int cs47l35_adsp_power_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct cs47l35 *cs47l35 = snd_soc_component_get_drvdata(component);
struct madera_priv *priv = &cs47l35->core;
struct madera *madera = priv->madera;
unsigned int freq;
int ret;
ret = regmap_read(madera->regmap, MADERA_DSP_CLOCK_1, &freq);
if (ret != 0) {
dev_err(madera->dev,
"Failed to read MADERA_DSP_CLOCK_1: %d\n", ret);
return ret;
}
freq &= MADERA_DSP_CLK_FREQ_LEGACY_MASK;
freq >>= MADERA_DSP_CLK_FREQ_LEGACY_SHIFT;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
ret = madera_set_adsp_clk(&cs47l35->core, w->shift, freq);
if (ret)
return ret;
break;
default:
break;
}
return wm_adsp_early_event(w, kcontrol, event);
}
#define CS47L35_NG_SRC(name, base) \
SOC_SINGLE(name " NG HPOUT1L Switch", base, 0, 1, 0), \
SOC_SINGLE(name " NG HPOUT1R Switch", base, 1, 1, 0), \
SOC_SINGLE(name " NG SPKOUT Switch", base, 6, 1, 0), \
SOC_SINGLE(name " NG SPKDAT1L Switch", base, 8, 1, 0), \
SOC_SINGLE(name " NG SPKDAT1R Switch", base, 9, 1, 0)
static void cs47l35_hp_post_enable(struct snd_soc_dapm_widget *w)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
unsigned int val;
switch (w->shift) {
case MADERA_OUT1L_ENA_SHIFT:
case MADERA_OUT1R_ENA_SHIFT:
val = snd_soc_component_read(component, MADERA_OUTPUT_ENABLES_1);
val &= (MADERA_OUT1L_ENA | MADERA_OUT1R_ENA);
if (val != (MADERA_OUT1L_ENA | MADERA_OUT1R_ENA))
break;
snd_soc_component_update_bits(component,
MADERA_EDRE_HP_STEREO_CONTROL,
0x0001, 1);
break;
default:
break;
}
}
static void cs47l35_hp_post_disable(struct snd_soc_dapm_widget *w)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
switch (w->shift) {
case MADERA_OUT1L_ENA_SHIFT:
snd_soc_component_write(component, MADERA_DCS_HP1L_CONTROL,
0x2006);
break;
case MADERA_OUT1R_ENA_SHIFT:
snd_soc_component_write(component, MADERA_DCS_HP1R_CONTROL,
0x2006);
break;
default:
return;
}
/* Only get to here for OUT1L and OUT1R */
snd_soc_component_update_bits(component,
MADERA_EDRE_HP_STEREO_CONTROL,
0x0001, 0);
}
static int cs47l35_hp_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
int ret;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
case SND_SOC_DAPM_PRE_PMD:
return madera_hp_ev(w, kcontrol, event);
case SND_SOC_DAPM_POST_PMU:
ret = madera_hp_ev(w, kcontrol, event);
if (ret < 0)
return ret;
cs47l35_hp_post_enable(w);
return 0;
case SND_SOC_DAPM_POST_PMD:
ret = madera_hp_ev(w, kcontrol, event);
cs47l35_hp_post_disable(w);
return ret;
default:
return -EINVAL;
}
}
static const struct snd_kcontrol_new cs47l35_snd_controls[] = {
SOC_ENUM("IN1 OSR", madera_in_dmic_osr[0]),
SOC_ENUM("IN2 OSR", madera_in_dmic_osr[1]),
SOC_SINGLE_RANGE_TLV("IN1L Volume", MADERA_IN1L_CONTROL,
MADERA_IN1L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
SOC_SINGLE_RANGE_TLV("IN1R Volume", MADERA_IN1R_CONTROL,
MADERA_IN1R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
SOC_SINGLE_RANGE_TLV("IN2L Volume", MADERA_IN2L_CONTROL,
MADERA_IN2L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
SOC_SINGLE_RANGE_TLV("IN2R Volume", MADERA_IN2R_CONTROL,
MADERA_IN2R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
SOC_ENUM("IN HPF Cutoff Frequency", madera_in_hpf_cut_enum),
SOC_SINGLE("IN1L HPF Switch", MADERA_IN1L_CONTROL,
MADERA_IN1L_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN1R HPF Switch", MADERA_IN1R_CONTROL,
MADERA_IN1R_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN2L HPF Switch", MADERA_IN2L_CONTROL,
MADERA_IN2L_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN2R HPF Switch", MADERA_IN2R_CONTROL,
MADERA_IN2R_HPF_SHIFT, 1, 0),
SOC_SINGLE_TLV("IN1L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_1L,
MADERA_IN1L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_SINGLE_TLV("IN1R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_1R,
MADERA_IN1R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_SINGLE_TLV("IN2L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_2L,
MADERA_IN2L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_SINGLE_TLV("IN2R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_2R,
MADERA_IN2R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_ENUM("Input Ramp Up", madera_in_vi_ramp),
SOC_ENUM("Input Ramp Down", madera_in_vd_ramp),
MADERA_MIXER_CONTROLS("EQ1", MADERA_EQ1MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("EQ2", MADERA_EQ2MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("EQ3", MADERA_EQ3MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("EQ4", MADERA_EQ4MIX_INPUT_1_SOURCE),
MADERA_EQ_CONTROL("EQ1 Coefficients", MADERA_EQ1_2),
SOC_SINGLE_TLV("EQ1 B1 Volume", MADERA_EQ1_1, MADERA_EQ1_B1_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ1 B2 Volume", MADERA_EQ1_1, MADERA_EQ1_B2_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ1 B3 Volume", MADERA_EQ1_1, MADERA_EQ1_B3_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ1 B4 Volume", MADERA_EQ1_2, MADERA_EQ1_B4_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ1 B5 Volume", MADERA_EQ1_2, MADERA_EQ1_B5_GAIN_SHIFT,
24, 0, madera_eq_tlv),
MADERA_EQ_CONTROL("EQ2 Coefficients", MADERA_EQ2_2),
SOC_SINGLE_TLV("EQ2 B1 Volume", MADERA_EQ2_1, MADERA_EQ2_B1_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ2 B2 Volume", MADERA_EQ2_1, MADERA_EQ2_B2_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ2 B3 Volume", MADERA_EQ2_1, MADERA_EQ2_B3_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ2 B4 Volume", MADERA_EQ2_2, MADERA_EQ2_B4_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ2 B5 Volume", MADERA_EQ2_2, MADERA_EQ2_B5_GAIN_SHIFT,
24, 0, madera_eq_tlv),
MADERA_EQ_CONTROL("EQ3 Coefficients", MADERA_EQ3_2),
SOC_SINGLE_TLV("EQ3 B1 Volume", MADERA_EQ3_1, MADERA_EQ3_B1_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ3 B2 Volume", MADERA_EQ3_1, MADERA_EQ3_B2_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ3 B3 Volume", MADERA_EQ3_1, MADERA_EQ3_B3_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ3 B4 Volume", MADERA_EQ3_2, MADERA_EQ3_B4_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ3 B5 Volume", MADERA_EQ3_2, MADERA_EQ3_B5_GAIN_SHIFT,
24, 0, madera_eq_tlv),
MADERA_EQ_CONTROL("EQ4 Coefficients", MADERA_EQ4_2),
SOC_SINGLE_TLV("EQ4 B1 Volume", MADERA_EQ4_1, MADERA_EQ4_B1_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ4 B2 Volume", MADERA_EQ4_1, MADERA_EQ4_B2_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ4 B3 Volume", MADERA_EQ4_1, MADERA_EQ4_B3_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ4 B4 Volume", MADERA_EQ4_2, MADERA_EQ4_B4_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ4 B5 Volume", MADERA_EQ4_2, MADERA_EQ4_B5_GAIN_SHIFT,
24, 0, madera_eq_tlv),
MADERA_MIXER_CONTROLS("DRC1L", MADERA_DRC1LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DRC1R", MADERA_DRC1RMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DRC2L", MADERA_DRC2LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DRC2R", MADERA_DRC2RMIX_INPUT_1_SOURCE),
SND_SOC_BYTES_MASK("DRC1", MADERA_DRC1_CTRL1, 5,
MADERA_DRC1R_ENA | MADERA_DRC1L_ENA),
SND_SOC_BYTES_MASK("DRC2", MADERA_DRC2_CTRL1, 5,
MADERA_DRC2R_ENA | MADERA_DRC2L_ENA),
MADERA_MIXER_CONTROLS("LHPF1", MADERA_HPLP1MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("LHPF2", MADERA_HPLP2MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("LHPF3", MADERA_HPLP3MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("LHPF4", MADERA_HPLP4MIX_INPUT_1_SOURCE),
MADERA_LHPF_CONTROL("LHPF1 Coefficients", MADERA_HPLPF1_2),
MADERA_LHPF_CONTROL("LHPF2 Coefficients", MADERA_HPLPF2_2),
MADERA_LHPF_CONTROL("LHPF3 Coefficients", MADERA_HPLPF3_2),
MADERA_LHPF_CONTROL("LHPF4 Coefficients", MADERA_HPLPF4_2),
SOC_ENUM("LHPF1 Mode", madera_lhpf1_mode),
SOC_ENUM("LHPF2 Mode", madera_lhpf2_mode),
SOC_ENUM("LHPF3 Mode", madera_lhpf3_mode),
SOC_ENUM("LHPF4 Mode", madera_lhpf4_mode),
MADERA_RATE_ENUM("ISRC1 FSL", madera_isrc_fsl[0]),
MADERA_RATE_ENUM("ISRC2 FSL", madera_isrc_fsl[1]),
MADERA_RATE_ENUM("ISRC1 FSH", madera_isrc_fsh[0]),
MADERA_RATE_ENUM("ISRC2 FSH", madera_isrc_fsh[1]),
WM_ADSP2_PRELOAD_SWITCH("DSP1", 1),
WM_ADSP2_PRELOAD_SWITCH("DSP2", 2),
WM_ADSP2_PRELOAD_SWITCH("DSP3", 3),
MADERA_MIXER_CONTROLS("DSP1L", MADERA_DSP1LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DSP1R", MADERA_DSP1RMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DSP2L", MADERA_DSP2LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DSP2R", MADERA_DSP2RMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DSP3L", MADERA_DSP3LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DSP3R", MADERA_DSP3RMIX_INPUT_1_SOURCE),
SOC_SINGLE_TLV("Noise Generator Volume", MADERA_COMFORT_NOISE_GENERATOR,
MADERA_NOISE_GEN_GAIN_SHIFT, 0x16, 0, madera_noise_tlv),
MADERA_MIXER_CONTROLS("HPOUT1L", MADERA_OUT1LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("HPOUT1R", MADERA_OUT1RMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SPKOUT", MADERA_OUT4LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SPKDAT1L", MADERA_OUT5LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SPKDAT1R", MADERA_OUT5RMIX_INPUT_1_SOURCE),
SOC_SINGLE("HPOUT1 SC Protect Switch", MADERA_HP1_SHORT_CIRCUIT_CTRL,
MADERA_HP1_SC_ENA_SHIFT, 1, 0),
SOC_SINGLE("SPKDAT1 High Performance Switch", MADERA_OUTPUT_PATH_CONFIG_5L,
MADERA_OUT5_OSR_SHIFT, 1, 0),
SOC_DOUBLE_R("HPOUT1 Digital Switch", MADERA_DAC_DIGITAL_VOLUME_1L,
MADERA_DAC_DIGITAL_VOLUME_1R, MADERA_OUT1L_MUTE_SHIFT, 1, 1),
SOC_SINGLE("Speaker Digital Switch", MADERA_DAC_DIGITAL_VOLUME_4L,
MADERA_OUT4L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R("SPKDAT1 Digital Switch", MADERA_DAC_DIGITAL_VOLUME_5L,
MADERA_DAC_DIGITAL_VOLUME_5R, MADERA_OUT5L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", MADERA_DAC_DIGITAL_VOLUME_1L,
MADERA_DAC_DIGITAL_VOLUME_1R, MADERA_OUT1L_VOL_SHIFT,
0xbf, 0, madera_digital_tlv),
SOC_SINGLE_TLV("Speaker Digital Volume", MADERA_DAC_DIGITAL_VOLUME_4L,
MADERA_OUT4L_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", MADERA_DAC_DIGITAL_VOLUME_5L,
MADERA_DAC_DIGITAL_VOLUME_5R, MADERA_OUT5L_VOL_SHIFT,
0xbf, 0, madera_digital_tlv),
SOC_DOUBLE("SPKDAT1 Switch", MADERA_PDM_SPK1_CTRL_1, MADERA_SPK1L_MUTE_SHIFT,
MADERA_SPK1R_MUTE_SHIFT, 1, 1),
SOC_ENUM("Output Ramp Up", madera_out_vi_ramp),
SOC_ENUM("Output Ramp Down", madera_out_vd_ramp),
SOC_SINGLE("Noise Gate Switch", MADERA_NOISE_GATE_CONTROL,
MADERA_NGATE_ENA_SHIFT, 1, 0),
SOC_SINGLE_TLV("Noise Gate Threshold Volume", MADERA_NOISE_GATE_CONTROL,
MADERA_NGATE_THR_SHIFT, 7, 1, madera_ng_tlv),
SOC_ENUM("Noise Gate Hold", madera_ng_hold),
CS47L35_NG_SRC("HPOUT1L", MADERA_NOISE_GATE_SELECT_1L),
CS47L35_NG_SRC("HPOUT1R", MADERA_NOISE_GATE_SELECT_1R),
CS47L35_NG_SRC("SPKOUT", MADERA_NOISE_GATE_SELECT_4L),
CS47L35_NG_SRC("SPKDAT1L", MADERA_NOISE_GATE_SELECT_5L),
CS47L35_NG_SRC("SPKDAT1R", MADERA_NOISE_GATE_SELECT_5R),
MADERA_MIXER_CONTROLS("AIF1TX1", MADERA_AIF1TX1MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF1TX2", MADERA_AIF1TX2MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF1TX3", MADERA_AIF1TX3MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF1TX4", MADERA_AIF1TX4MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF1TX5", MADERA_AIF1TX5MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF1TX6", MADERA_AIF1TX6MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF2TX1", MADERA_AIF2TX1MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF2TX2", MADERA_AIF2TX2MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF3TX1", MADERA_AIF3TX1MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF3TX2", MADERA_AIF3TX2MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SLIMTX1", MADERA_SLIMTX1MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SLIMTX2", MADERA_SLIMTX2MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SLIMTX3", MADERA_SLIMTX3MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SLIMTX4", MADERA_SLIMTX4MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SLIMTX5", MADERA_SLIMTX5MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SLIMTX6", MADERA_SLIMTX6MIX_INPUT_1_SOURCE),
MADERA_GAINMUX_CONTROLS("SPDIF1TX1", MADERA_SPDIF1TX1MIX_INPUT_1_SOURCE),
MADERA_GAINMUX_CONTROLS("SPDIF1TX2", MADERA_SPDIF1TX2MIX_INPUT_1_SOURCE),
WM_ADSP_FW_CONTROL("DSP1", 0),
WM_ADSP_FW_CONTROL("DSP2", 1),
WM_ADSP_FW_CONTROL("DSP3", 2),
};
MADERA_MIXER_ENUMS(EQ1, MADERA_EQ1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(EQ2, MADERA_EQ2MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(EQ3, MADERA_EQ3MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(EQ4, MADERA_EQ4MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DRC1L, MADERA_DRC1LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DRC1R, MADERA_DRC1RMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DRC2L, MADERA_DRC2LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DRC2R, MADERA_DRC2RMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(LHPF1, MADERA_HPLP1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(LHPF2, MADERA_HPLP2MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(LHPF3, MADERA_HPLP3MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(LHPF4, MADERA_HPLP4MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP1L, MADERA_DSP1LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP1R, MADERA_DSP1RMIX_INPUT_1_SOURCE);
MADERA_DSP_AUX_ENUMS(DSP1, MADERA_DSP1AUX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP2L, MADERA_DSP2LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP2R, MADERA_DSP2RMIX_INPUT_1_SOURCE);
MADERA_DSP_AUX_ENUMS(DSP2, MADERA_DSP2AUX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP3L, MADERA_DSP3LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP3R, MADERA_DSP3RMIX_INPUT_1_SOURCE);
MADERA_DSP_AUX_ENUMS(DSP3, MADERA_DSP3AUX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(PWM1, MADERA_PWM1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(PWM2, MADERA_PWM2MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(OUT1L, MADERA_OUT1LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(OUT1R, MADERA_OUT1RMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SPKOUT, MADERA_OUT4LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SPKDAT1L, MADERA_OUT5LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SPKDAT1R, MADERA_OUT5RMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX1, MADERA_AIF1TX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX2, MADERA_AIF1TX2MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX3, MADERA_AIF1TX3MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX4, MADERA_AIF1TX4MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX5, MADERA_AIF1TX5MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX6, MADERA_AIF1TX6MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF2TX1, MADERA_AIF2TX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF2TX2, MADERA_AIF2TX2MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF3TX1, MADERA_AIF3TX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF3TX2, MADERA_AIF3TX2MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SLIMTX1, MADERA_SLIMTX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SLIMTX2, MADERA_SLIMTX2MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SLIMTX3, MADERA_SLIMTX3MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SLIMTX4, MADERA_SLIMTX4MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SLIMTX5, MADERA_SLIMTX5MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SLIMTX6, MADERA_SLIMTX6MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(SPD1TX1, MADERA_SPDIF1TX1MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(SPD1TX2, MADERA_SPDIF1TX2MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1INT1, MADERA_ISRC1INT1MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1INT2, MADERA_ISRC1INT2MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1INT3, MADERA_ISRC1INT3MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1INT4, MADERA_ISRC1INT4MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1DEC1, MADERA_ISRC1DEC1MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1DEC2, MADERA_ISRC1DEC2MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1DEC3, MADERA_ISRC1DEC3MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1DEC4, MADERA_ISRC1DEC4MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2INT1, MADERA_ISRC2INT1MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2INT2, MADERA_ISRC2INT2MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2INT3, MADERA_ISRC2INT3MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2INT4, MADERA_ISRC2INT4MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2DEC1, MADERA_ISRC2DEC1MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2DEC2, MADERA_ISRC2DEC2MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2DEC3, MADERA_ISRC2DEC3MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2DEC4, MADERA_ISRC2DEC4MIX_INPUT_1_SOURCE);
static const char * const cs47l35_aec_loopback_texts[] = {
"HPOUT1L", "HPOUT1R", "SPKOUT", "SPKDAT1L", "SPKDAT1R",
};
static const unsigned int cs47l35_aec_loopback_values[] = {
0, 1, 6, 8, 9,
};
static const struct soc_enum cs47l35_aec1_loopback =
SOC_VALUE_ENUM_SINGLE(MADERA_DAC_AEC_CONTROL_1,
MADERA_AEC1_LOOPBACK_SRC_SHIFT, 0xf,
ARRAY_SIZE(cs47l35_aec_loopback_texts),
cs47l35_aec_loopback_texts,
cs47l35_aec_loopback_values);
static const struct soc_enum cs47l35_aec2_loopback =
SOC_VALUE_ENUM_SINGLE(MADERA_DAC_AEC_CONTROL_2,
MADERA_AEC2_LOOPBACK_SRC_SHIFT, 0xf,
ARRAY_SIZE(cs47l35_aec_loopback_texts),
cs47l35_aec_loopback_texts,
cs47l35_aec_loopback_values);
static const struct snd_kcontrol_new cs47l35_aec_loopback_mux[] = {
SOC_DAPM_ENUM("AEC1 Loopback", cs47l35_aec1_loopback),
SOC_DAPM_ENUM("AEC2 Loopback", cs47l35_aec2_loopback),
};
static const struct snd_soc_dapm_widget cs47l35_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("SYSCLK", MADERA_SYSTEM_CLOCK_1, MADERA_SYSCLK_ENA_SHIFT,
0, madera_sysclk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("OPCLK", MADERA_OUTPUT_SYSTEM_CLOCK,
MADERA_OPCLK_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DSPCLK", MADERA_DSP_CLOCK_1, MADERA_DSP_CLK_ENA_SHIFT,
0, madera_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD2", 0, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD1", 20, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD2", 20, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("MICVDD", 0, SND_SOC_DAPM_REGULATOR_BYPASS),
SND_SOC_DAPM_REGULATOR_SUPPLY("SPKVDD", 0, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS1", MADERA_MIC_BIAS_CTRL_1,
MADERA_MICB1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS2", MADERA_MIC_BIAS_CTRL_2,
MADERA_MICB1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS1A", MADERA_MIC_BIAS_CTRL_5,
MADERA_MICB1A_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS1B", MADERA_MIC_BIAS_CTRL_5,
MADERA_MICB1B_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS2A", MADERA_MIC_BIAS_CTRL_6,
MADERA_MICB2A_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS2B", MADERA_MIC_BIAS_CTRL_6,
MADERA_MICB2B_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("FXCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_FX, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("ISRC1CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_ISRC1, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("ISRC2CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_ISRC2, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("OUTCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_OUT, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("SPDCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_SPD, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_DSP1, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_DSP2, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("DSP3CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_DSP3, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("AIF1TXCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_AIF1, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("AIF2TXCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_AIF2, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("AIF3TXCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_AIF3, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("SLIMBUSCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_SLIMBUS, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("PWMCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_PWM, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SIGGEN("TONE"),
SND_SOC_DAPM_SIGGEN("NOISE"),
SND_SOC_DAPM_INPUT("IN1ALN"),
SND_SOC_DAPM_INPUT("IN1ALP"),
SND_SOC_DAPM_INPUT("IN1BLN"),
SND_SOC_DAPM_INPUT("IN1BLP"),
SND_SOC_DAPM_INPUT("IN1ARN"),
SND_SOC_DAPM_INPUT("IN1ARP"),
SND_SOC_DAPM_INPUT("IN1BRN"),
SND_SOC_DAPM_INPUT("IN1BRP"),
SND_SOC_DAPM_INPUT("IN2LN"),
SND_SOC_DAPM_INPUT("IN2LP"),
SND_SOC_DAPM_INPUT("IN2RN"),
SND_SOC_DAPM_INPUT("IN2RP"),
SND_SOC_DAPM_MUX("IN1L Analog Mux", SND_SOC_NOPM, 0, 0, &madera_inmux[0]),
SND_SOC_DAPM_MUX("IN1R Analog Mux", SND_SOC_NOPM, 0, 0, &madera_inmux[1]),
SND_SOC_DAPM_MUX("IN1L Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[0]),
SND_SOC_DAPM_MUX("IN1R Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[0]),
SND_SOC_DAPM_MUX("IN2L Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[1]),
SND_SOC_DAPM_MUX("IN2R Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[1]),
SND_SOC_DAPM_OUTPUT("DRC1 Signal Activity"),
SND_SOC_DAPM_OUTPUT("DRC2 Signal Activity"),
SND_SOC_DAPM_OUTPUT("DSP Trigger Out"),
SND_SOC_DAPM_DEMUX("HPOUT1 Demux", SND_SOC_NOPM, 0, 0, &cs47l35_outdemux),
SND_SOC_DAPM_MUX("HPOUT1 Mono Mux", SND_SOC_NOPM, 0, 0, &cs47l35_outdemux),
SND_SOC_DAPM_PGA("PWM1 Driver", MADERA_PWM_DRIVE_1, MADERA_PWM1_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA("PWM2 Driver", MADERA_PWM_DRIVE_1, MADERA_PWM2_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 0,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 1,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 2,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 3,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 4,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX6", NULL, 5,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0,
MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX2", NULL, 1,
MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF3TX1", NULL, 0,
MADERA_AIF3_TX_ENABLES, MADERA_AIF3TX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF3TX2", NULL, 1,
MADERA_AIF3_TX_ENABLES, MADERA_AIF3TX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX1", NULL, 0,
MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
MADERA_SLIMTX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX2", NULL, 1,
MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
MADERA_SLIMTX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX3", NULL, 2,
MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
MADERA_SLIMTX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX4", NULL, 3,
MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
MADERA_SLIMTX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX5", NULL, 4,
MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
MADERA_SLIMTX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX6", NULL, 5,
MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
MADERA_SLIMTX6_ENA_SHIFT, 0),
SND_SOC_DAPM_PGA_E("OUT1L", SND_SOC_NOPM,
MADERA_OUT1L_ENA_SHIFT, 0, NULL, 0, cs47l35_hp_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT1R", SND_SOC_NOPM,
MADERA_OUT1R_ENA_SHIFT, 0, NULL, 0, cs47l35_hp_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT4L", SND_SOC_NOPM,
MADERA_OUT4L_ENA_SHIFT, 0, NULL, 0, madera_spk_ev,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA_E("OUT5L", MADERA_OUTPUT_ENABLES_1,
MADERA_OUT5L_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT5R", MADERA_OUTPUT_ENABLES_1,
MADERA_OUT5R_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA("SPD1TX1", MADERA_SPD1_TX_CONTROL,
MADERA_SPD1_VAL1_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("SPD1TX2", MADERA_SPD1_TX_CONTROL,
MADERA_SPD1_VAL2_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("SPD1", MADERA_SPD1_TX_CONTROL,
MADERA_SPD1_ENA_SHIFT, 0, NULL, 0),
/*
* Input mux widgets arranged in order of sources in MADERA_MIXER_INPUT_ROUTES
* to take advantage of cache lookup in DAPM
*/
SND_SOC_DAPM_PGA("Noise Generator", MADERA_COMFORT_NOISE_GENERATOR,
MADERA_NOISE_GEN_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("Tone Generator 1", MADERA_TONE_GENERATOR_1,
MADERA_TONE1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("Tone Generator 2", MADERA_TONE_GENERATOR_1,
MADERA_TONE2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SIGGEN("HAPTICS"),
SND_SOC_DAPM_MUX("AEC1 Loopback", MADERA_DAC_AEC_CONTROL_1,
MADERA_AEC1_LOOPBACK_ENA_SHIFT, 0,
&cs47l35_aec_loopback_mux[0]),
SND_SOC_DAPM_MUX("AEC2 Loopback", MADERA_DAC_AEC_CONTROL_2,
MADERA_AEC2_LOOPBACK_ENA_SHIFT, 0,
&cs47l35_aec_loopback_mux[1]),
SND_SOC_DAPM_PGA_E("IN1L", MADERA_INPUT_ENABLES, MADERA_IN1L_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN1R", MADERA_INPUT_ENABLES, MADERA_IN1R_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN2L", MADERA_INPUT_ENABLES, MADERA_IN2L_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN2R", MADERA_INPUT_ENABLES, MADERA_IN2R_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 0,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 1,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 2,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 3,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 4,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX6", NULL, 5,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0,
MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX2", NULL, 1,
MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF3RX1", NULL, 0,
MADERA_AIF3_RX_ENABLES, MADERA_AIF3RX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF3RX2", NULL, 1,
MADERA_AIF3_RX_ENABLES, MADERA_AIF3RX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX1", NULL, 0,
MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
MADERA_SLIMRX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX2", NULL, 1,
MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
MADERA_SLIMRX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX3", NULL, 2,
MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
MADERA_SLIMRX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX4", NULL, 3,
MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
MADERA_SLIMRX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX5", NULL, 4,
MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
MADERA_SLIMRX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX6", NULL, 5,
MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
MADERA_SLIMRX6_ENA_SHIFT, 0),
SND_SOC_DAPM_PGA("EQ1", MADERA_EQ1_1, MADERA_EQ1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ2", MADERA_EQ2_1, MADERA_EQ2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ3", MADERA_EQ3_1, MADERA_EQ3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ4", MADERA_EQ4_1, MADERA_EQ4_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("DRC1L", MADERA_DRC1_CTRL1, MADERA_DRC1L_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("DRC1R", MADERA_DRC1_CTRL1, MADERA_DRC1R_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("DRC2L", MADERA_DRC2_CTRL1, MADERA_DRC2L_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("DRC2R", MADERA_DRC2_CTRL1, MADERA_DRC2R_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF1", MADERA_HPLPF1_1, MADERA_LHPF1_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF2", MADERA_HPLPF2_1, MADERA_LHPF2_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF3", MADERA_HPLPF3_1, MADERA_LHPF3_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF4", MADERA_HPLPF4_1, MADERA_LHPF4_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC1", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_DEC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC2", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_DEC2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC3", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_DEC3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC4", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_DEC4_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1INT1", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_INT1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1INT2", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_INT2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1INT3", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_INT3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1INT4", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_INT4_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2DEC1", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_DEC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2DEC2", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_DEC2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2DEC3", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_DEC3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2DEC4", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_DEC4_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2INT1", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_INT1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2INT2", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_INT2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2INT3", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_INT3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2INT4", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_INT4_ENA_SHIFT, 0, NULL, 0),
WM_ADSP2("DSP1", 0, cs47l35_adsp_power_ev),
WM_ADSP2("DSP2", 1, cs47l35_adsp_power_ev),
WM_ADSP2("DSP3", 2, cs47l35_adsp_power_ev),
/* End of ordered input mux widgets */
MADERA_MIXER_WIDGETS(EQ1, "EQ1"),
MADERA_MIXER_WIDGETS(EQ2, "EQ2"),
MADERA_MIXER_WIDGETS(EQ3, "EQ3"),
MADERA_MIXER_WIDGETS(EQ4, "EQ4"),
MADERA_MIXER_WIDGETS(DRC1L, "DRC1L"),
MADERA_MIXER_WIDGETS(DRC1R, "DRC1R"),
MADERA_MIXER_WIDGETS(DRC2L, "DRC2L"),
MADERA_MIXER_WIDGETS(DRC2R, "DRC2R"),
SND_SOC_DAPM_SWITCH("DRC1 Activity Output", SND_SOC_NOPM, 0, 0,
&madera_drc_activity_output_mux[0]),
SND_SOC_DAPM_SWITCH("DRC2 Activity Output", SND_SOC_NOPM, 0, 0,
&madera_drc_activity_output_mux[1]),
MADERA_MIXER_WIDGETS(LHPF1, "LHPF1"),
MADERA_MIXER_WIDGETS(LHPF2, "LHPF2"),
MADERA_MIXER_WIDGETS(LHPF3, "LHPF3"),
MADERA_MIXER_WIDGETS(LHPF4, "LHPF4"),
MADERA_MIXER_WIDGETS(PWM1, "PWM1"),
MADERA_MIXER_WIDGETS(PWM2, "PWM2"),
MADERA_MIXER_WIDGETS(OUT1L, "HPOUT1L"),
MADERA_MIXER_WIDGETS(OUT1R, "HPOUT1R"),
MADERA_MIXER_WIDGETS(SPKOUT, "SPKOUT"),
MADERA_MIXER_WIDGETS(SPKDAT1L, "SPKDAT1L"),
MADERA_MIXER_WIDGETS(SPKDAT1R, "SPKDAT1R"),
MADERA_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"),
MADERA_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"),
MADERA_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"),
MADERA_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"),
MADERA_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"),
MADERA_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"),
MADERA_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"),
MADERA_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"),
MADERA_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"),
MADERA_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"),
MADERA_MIXER_WIDGETS(SLIMTX1, "SLIMTX1"),
MADERA_MIXER_WIDGETS(SLIMTX2, "SLIMTX2"),
MADERA_MIXER_WIDGETS(SLIMTX3, "SLIMTX3"),
MADERA_MIXER_WIDGETS(SLIMTX4, "SLIMTX4"),
MADERA_MIXER_WIDGETS(SLIMTX5, "SLIMTX5"),
MADERA_MIXER_WIDGETS(SLIMTX6, "SLIMTX6"),
MADERA_MUX_WIDGETS(SPD1TX1, "SPDIF1TX1"),
MADERA_MUX_WIDGETS(SPD1TX2, "SPDIF1TX2"),
MADERA_DSP_WIDGETS(DSP1, "DSP1"),
MADERA_DSP_WIDGETS(DSP2, "DSP2"),
MADERA_DSP_WIDGETS(DSP3, "DSP3"),
SND_SOC_DAPM_SWITCH("DSP1 Trigger Output", SND_SOC_NOPM, 0, 0,
&madera_dsp_trigger_output_mux[0]),
SND_SOC_DAPM_SWITCH("DSP2 Trigger Output", SND_SOC_NOPM, 0, 0,
&madera_dsp_trigger_output_mux[1]),
SND_SOC_DAPM_SWITCH("DSP3 Trigger Output", SND_SOC_NOPM, 0, 0,
&madera_dsp_trigger_output_mux[2]),
MADERA_MUX_WIDGETS(ISRC1DEC1, "ISRC1DEC1"),
MADERA_MUX_WIDGETS(ISRC1DEC2, "ISRC1DEC2"),
MADERA_MUX_WIDGETS(ISRC1DEC3, "ISRC1DEC3"),
MADERA_MUX_WIDGETS(ISRC1DEC4, "ISRC1DEC4"),
MADERA_MUX_WIDGETS(ISRC1INT1, "ISRC1INT1"),
MADERA_MUX_WIDGETS(ISRC1INT2, "ISRC1INT2"),
MADERA_MUX_WIDGETS(ISRC1INT3, "ISRC1INT3"),
MADERA_MUX_WIDGETS(ISRC1INT4, "ISRC1INT4"),
MADERA_MUX_WIDGETS(ISRC2DEC1, "ISRC2DEC1"),
MADERA_MUX_WIDGETS(ISRC2DEC2, "ISRC2DEC2"),
MADERA_MUX_WIDGETS(ISRC2DEC3, "ISRC2DEC3"),
MADERA_MUX_WIDGETS(ISRC2DEC4, "ISRC2DEC4"),
MADERA_MUX_WIDGETS(ISRC2INT1, "ISRC2INT1"),
MADERA_MUX_WIDGETS(ISRC2INT2, "ISRC2INT2"),
MADERA_MUX_WIDGETS(ISRC2INT3, "ISRC2INT3"),
MADERA_MUX_WIDGETS(ISRC2INT4, "ISRC2INT4"),
SND_SOC_DAPM_OUTPUT("HPOUTL"),
SND_SOC_DAPM_OUTPUT("HPOUTR"),
SND_SOC_DAPM_OUTPUT("EPOUTP"),
SND_SOC_DAPM_OUTPUT("EPOUTN"),
SND_SOC_DAPM_OUTPUT("SPKOUTN"),
SND_SOC_DAPM_OUTPUT("SPKOUTP"),
SND_SOC_DAPM_OUTPUT("SPKDAT1L"),
SND_SOC_DAPM_OUTPUT("SPKDAT1R"),
SND_SOC_DAPM_OUTPUT("SPDIF1"),
SND_SOC_DAPM_OUTPUT("MICSUPP"),
};
#define MADERA_MIXER_INPUT_ROUTES(name) \
{ name, "Noise Generator", "Noise Generator" }, \
{ name, "Tone Generator 1", "Tone Generator 1" }, \
{ name, "Tone Generator 2", "Tone Generator 2" }, \
{ name, "Haptics", "HAPTICS" }, \
{ name, "AEC1", "AEC1 Loopback" }, \
{ name, "AEC2", "AEC2 Loopback" }, \
{ name, "IN1L", "IN1L" }, \
{ name, "IN1R", "IN1R" }, \
{ name, "IN2L", "IN2L" }, \
{ name, "IN2R", "IN2R" }, \
{ name, "AIF1RX1", "AIF1RX1" }, \
{ name, "AIF1RX2", "AIF1RX2" }, \
{ name, "AIF1RX3", "AIF1RX3" }, \
{ name, "AIF1RX4", "AIF1RX4" }, \
{ name, "AIF1RX5", "AIF1RX5" }, \
{ name, "AIF1RX6", "AIF1RX6" }, \
{ name, "AIF2RX1", "AIF2RX1" }, \
{ name, "AIF2RX2", "AIF2RX2" }, \
{ name, "AIF3RX1", "AIF3RX1" }, \
{ name, "AIF3RX2", "AIF3RX2" }, \
{ name, "SLIMRX1", "SLIMRX1" }, \
{ name, "SLIMRX2", "SLIMRX2" }, \
{ name, "SLIMRX3", "SLIMRX3" }, \
{ name, "SLIMRX4", "SLIMRX4" }, \
{ name, "SLIMRX5", "SLIMRX5" }, \
{ name, "SLIMRX6", "SLIMRX6" }, \
{ name, "EQ1", "EQ1" }, \
{ name, "EQ2", "EQ2" }, \
{ name, "EQ3", "EQ3" }, \
{ name, "EQ4", "EQ4" }, \
{ name, "DRC1L", "DRC1L" }, \
{ name, "DRC1R", "DRC1R" }, \
{ name, "DRC2L", "DRC2L" }, \
{ name, "DRC2R", "DRC2R" }, \
{ name, "LHPF1", "LHPF1" }, \
{ name, "LHPF2", "LHPF2" }, \
{ name, "LHPF3", "LHPF3" }, \
{ name, "LHPF4", "LHPF4" }, \
{ name, "ISRC1DEC1", "ISRC1DEC1" }, \
{ name, "ISRC1DEC2", "ISRC1DEC2" }, \
{ name, "ISRC1DEC3", "ISRC1DEC3" }, \
{ name, "ISRC1DEC4", "ISRC1DEC4" }, \
{ name, "ISRC1INT1", "ISRC1INT1" }, \
{ name, "ISRC1INT2", "ISRC1INT2" }, \
{ name, "ISRC1INT3", "ISRC1INT3" }, \
{ name, "ISRC1INT4", "ISRC1INT4" }, \
{ name, "ISRC2DEC1", "ISRC2DEC1" }, \
{ name, "ISRC2DEC2", "ISRC2DEC2" }, \
{ name, "ISRC2DEC3", "ISRC2DEC3" }, \
{ name, "ISRC2DEC4", "ISRC2DEC4" }, \
{ name, "ISRC2INT1", "ISRC2INT1" }, \
{ name, "ISRC2INT2", "ISRC2INT2" }, \
{ name, "ISRC2INT3", "ISRC2INT3" }, \
{ name, "ISRC2INT4", "ISRC2INT4" }, \
{ name, "DSP1.1", "DSP1" }, \
{ name, "DSP1.2", "DSP1" }, \
{ name, "DSP1.3", "DSP1" }, \
{ name, "DSP1.4", "DSP1" }, \
{ name, "DSP1.5", "DSP1" }, \
{ name, "DSP1.6", "DSP1" }, \
{ name, "DSP2.1", "DSP2" }, \
{ name, "DSP2.2", "DSP2" }, \
{ name, "DSP2.3", "DSP2" }, \
{ name, "DSP2.4", "DSP2" }, \
{ name, "DSP2.5", "DSP2" }, \
{ name, "DSP2.6", "DSP2" }, \
{ name, "DSP3.1", "DSP3" }, \
{ name, "DSP3.2", "DSP3" }, \
{ name, "DSP3.3", "DSP3" }, \
{ name, "DSP3.4", "DSP3" }, \
{ name, "DSP3.5", "DSP3" }, \
{ name, "DSP3.6", "DSP3" }
static const struct snd_soc_dapm_route cs47l35_dapm_routes[] = {
/* Internal clock domains */
{ "EQ1", NULL, "FXCLK" },
{ "EQ2", NULL, "FXCLK" },
{ "EQ3", NULL, "FXCLK" },
{ "EQ4", NULL, "FXCLK" },
{ "DRC1L", NULL, "FXCLK" },
{ "DRC1R", NULL, "FXCLK" },
{ "DRC2L", NULL, "FXCLK" },
{ "DRC2R", NULL, "FXCLK" },
{ "LHPF1", NULL, "FXCLK" },
{ "LHPF2", NULL, "FXCLK" },
{ "LHPF3", NULL, "FXCLK" },
{ "LHPF4", NULL, "FXCLK" },
{ "PWM1 Mixer", NULL, "PWMCLK" },
{ "PWM2 Mixer", NULL, "PWMCLK" },
{ "OUT1L", NULL, "OUTCLK" },
{ "OUT1R", NULL, "OUTCLK" },
{ "OUT4L", NULL, "OUTCLK" },
{ "OUT5L", NULL, "OUTCLK" },
{ "OUT5R", NULL, "OUTCLK" },
{ "AIF1TX1", NULL, "AIF1TXCLK" },
{ "AIF1TX2", NULL, "AIF1TXCLK" },
{ "AIF1TX3", NULL, "AIF1TXCLK" },
{ "AIF1TX4", NULL, "AIF1TXCLK" },
{ "AIF1TX5", NULL, "AIF1TXCLK" },
{ "AIF1TX6", NULL, "AIF1TXCLK" },
{ "AIF2TX1", NULL, "AIF2TXCLK" },
{ "AIF2TX2", NULL, "AIF2TXCLK" },
{ "AIF3TX1", NULL, "AIF3TXCLK" },
{ "AIF3TX2", NULL, "AIF3TXCLK" },
{ "SLIMTX1", NULL, "SLIMBUSCLK" },
{ "SLIMTX2", NULL, "SLIMBUSCLK" },
{ "SLIMTX3", NULL, "SLIMBUSCLK" },
{ "SLIMTX4", NULL, "SLIMBUSCLK" },
{ "SLIMTX5", NULL, "SLIMBUSCLK" },
{ "SLIMTX6", NULL, "SLIMBUSCLK" },
{ "SPD1TX1", NULL, "SPDCLK" },
{ "SPD1TX2", NULL, "SPDCLK" },
{ "DSP1", NULL, "DSP1CLK" },
{ "DSP2", NULL, "DSP2CLK" },
{ "DSP3", NULL, "DSP3CLK" },
{ "ISRC1DEC1", NULL, "ISRC1CLK" },
{ "ISRC1DEC2", NULL, "ISRC1CLK" },
{ "ISRC1DEC3", NULL, "ISRC1CLK" },
{ "ISRC1DEC4", NULL, "ISRC1CLK" },
{ "ISRC1INT1", NULL, "ISRC1CLK" },
{ "ISRC1INT2", NULL, "ISRC1CLK" },
{ "ISRC1INT3", NULL, "ISRC1CLK" },
{ "ISRC1INT4", NULL, "ISRC1CLK" },
{ "ISRC2DEC1", NULL, "ISRC2CLK" },
{ "ISRC2DEC2", NULL, "ISRC2CLK" },
{ "ISRC2DEC3", NULL, "ISRC2CLK" },
{ "ISRC2DEC4", NULL, "ISRC2CLK" },
{ "ISRC2INT1", NULL, "ISRC2CLK" },
{ "ISRC2INT2", NULL, "ISRC2CLK" },
{ "ISRC2INT3", NULL, "ISRC2CLK" },
{ "ISRC2INT4", NULL, "ISRC2CLK" },
{ "AIF2 Capture", NULL, "DBVDD2" },
{ "AIF2 Playback", NULL, "DBVDD2" },
{ "AIF3 Capture", NULL, "DBVDD2" },
{ "AIF3 Playback", NULL, "DBVDD2" },
{ "OUT1L", NULL, "CPVDD1" },
{ "OUT1R", NULL, "CPVDD1" },
{ "OUT1L", NULL, "CPVDD2" },
{ "OUT1R", NULL, "CPVDD2" },
{ "OUT4L", NULL, "SPKVDD" },
{ "OUT1L", NULL, "SYSCLK" },
{ "OUT1R", NULL, "SYSCLK" },
{ "OUT4L", NULL, "SYSCLK" },
{ "OUT5L", NULL, "SYSCLK" },
{ "OUT5R", NULL, "SYSCLK" },
{ "SPD1", NULL, "SYSCLK" },
{ "SPD1", NULL, "SPD1TX1" },
{ "SPD1", NULL, "SPD1TX2" },
{ "IN1L", NULL, "SYSCLK" },
{ "IN1R", NULL, "SYSCLK" },
{ "IN2L", NULL, "SYSCLK" },
{ "IN2R", NULL, "SYSCLK" },
{ "MICBIAS1", NULL, "MICVDD" },
{ "MICBIAS2", NULL, "MICVDD" },
{ "MICBIAS1A", NULL, "MICBIAS1" },
{ "MICBIAS1B", NULL, "MICBIAS1" },
{ "MICBIAS2A", NULL, "MICBIAS2" },
{ "MICBIAS2B", NULL, "MICBIAS2" },
{ "Noise Generator", NULL, "SYSCLK" },
{ "Tone Generator 1", NULL, "SYSCLK" },
{ "Tone Generator 2", NULL, "SYSCLK" },
{ "Noise Generator", NULL, "NOISE" },
{ "Tone Generator 1", NULL, "TONE" },
{ "Tone Generator 2", NULL, "TONE" },
{ "AIF1 Capture", NULL, "AIF1TX1" },
{ "AIF1 Capture", NULL, "AIF1TX2" },
{ "AIF1 Capture", NULL, "AIF1TX3" },
{ "AIF1 Capture", NULL, "AIF1TX4" },
{ "AIF1 Capture", NULL, "AIF1TX5" },
{ "AIF1 Capture", NULL, "AIF1TX6" },
{ "AIF1RX1", NULL, "AIF1 Playback" },
{ "AIF1RX2", NULL, "AIF1 Playback" },
{ "AIF1RX3", NULL, "AIF1 Playback" },
{ "AIF1RX4", NULL, "AIF1 Playback" },
{ "AIF1RX5", NULL, "AIF1 Playback" },
{ "AIF1RX6", NULL, "AIF1 Playback" },
{ "AIF2 Capture", NULL, "AIF2TX1" },
{ "AIF2 Capture", NULL, "AIF2TX2" },
{ "AIF2RX1", NULL, "AIF2 Playback" },
{ "AIF2RX2", NULL, "AIF2 Playback" },
{ "AIF3 Capture", NULL, "AIF3TX1" },
{ "AIF3 Capture", NULL, "AIF3TX2" },
{ "AIF3RX1", NULL, "AIF3 Playback" },
{ "AIF3RX2", NULL, "AIF3 Playback" },
{ "Slim1 Capture", NULL, "SLIMTX1" },
{ "Slim1 Capture", NULL, "SLIMTX2" },
{ "Slim1 Capture", NULL, "SLIMTX3" },
{ "Slim1 Capture", NULL, "SLIMTX4" },
{ "SLIMRX1", NULL, "Slim1 Playback" },
{ "SLIMRX2", NULL, "Slim1 Playback" },
{ "SLIMRX3", NULL, "Slim1 Playback" },
{ "SLIMRX4", NULL, "Slim1 Playback" },
{ "Slim2 Capture", NULL, "SLIMTX5" },
{ "Slim2 Capture", NULL, "SLIMTX6" },
{ "SLIMRX5", NULL, "Slim2 Playback" },
{ "SLIMRX6", NULL, "Slim2 Playback" },
{ "AIF1 Playback", NULL, "SYSCLK" },
{ "AIF2 Playback", NULL, "SYSCLK" },
{ "AIF3 Playback", NULL, "SYSCLK" },
{ "Slim1 Playback", NULL, "SYSCLK" },
{ "Slim2 Playback", NULL, "SYSCLK" },
{ "AIF1 Capture", NULL, "SYSCLK" },
{ "AIF2 Capture", NULL, "SYSCLK" },
{ "AIF3 Capture", NULL, "SYSCLK" },
{ "Slim1 Capture", NULL, "SYSCLK" },
{ "Slim2 Capture", NULL, "SYSCLK" },
{ "Voice Control DSP", NULL, "DSP3" },
{ "Audio Trace DSP", NULL, "DSP1" },
{ "IN1L Analog Mux", "A", "IN1ALN" },
{ "IN1L Analog Mux", "A", "IN1ALP" },
{ "IN1L Analog Mux", "B", "IN1BLN" },
{ "IN1L Analog Mux", "B", "IN1BLP" },
{ "IN1R Analog Mux", "A", "IN1ARN" },
{ "IN1R Analog Mux", "A", "IN1ARP" },
{ "IN1R Analog Mux", "B", "IN1BRN" },
{ "IN1R Analog Mux", "B", "IN1BRP" },
{ "IN1L Mode", "Analog", "IN1L Analog Mux" },
{ "IN1R Mode", "Analog", "IN1R Analog Mux" },
{ "IN1L Mode", "Digital", "IN1ALN" },
{ "IN1L Mode", "Digital", "IN1ARN" },
{ "IN1R Mode", "Digital", "IN1ALN" },
{ "IN1R Mode", "Digital", "IN1ARN" },
{ "IN1L", NULL, "IN1L Mode" },
{ "IN1R", NULL, "IN1R Mode" },
{ "IN2L Mode", "Analog", "IN2LN" },
{ "IN2L Mode", "Analog", "IN2LP" },
{ "IN2R Mode", "Analog", "IN2RN" },
{ "IN2R Mode", "Analog", "IN2RP" },
{ "IN2L Mode", "Digital", "IN2LN" },
{ "IN2L Mode", "Digital", "IN2RN" },
{ "IN2R Mode", "Digital", "IN2LN" },
{ "IN2R Mode", "Digital", "IN2RN" },
{ "IN2L", NULL, "IN2L Mode" },
{ "IN2R", NULL, "IN2R Mode" },
MADERA_MIXER_ROUTES("OUT1L", "HPOUT1L"),
MADERA_MIXER_ROUTES("OUT1R", "HPOUT1R"),
MADERA_MIXER_ROUTES("OUT4L", "SPKOUT"),
MADERA_MIXER_ROUTES("OUT5L", "SPKDAT1L"),
MADERA_MIXER_ROUTES("OUT5R", "SPKDAT1R"),
MADERA_MIXER_ROUTES("PWM1 Driver", "PWM1"),
MADERA_MIXER_ROUTES("PWM2 Driver", "PWM2"),
MADERA_MIXER_ROUTES("AIF1TX1", "AIF1TX1"),
MADERA_MIXER_ROUTES("AIF1TX2", "AIF1TX2"),
MADERA_MIXER_ROUTES("AIF1TX3", "AIF1TX3"),
MADERA_MIXER_ROUTES("AIF1TX4", "AIF1TX4"),
MADERA_MIXER_ROUTES("AIF1TX5", "AIF1TX5"),
MADERA_MIXER_ROUTES("AIF1TX6", "AIF1TX6"),
MADERA_MIXER_ROUTES("AIF2TX1", "AIF2TX1"),
MADERA_MIXER_ROUTES("AIF2TX2", "AIF2TX2"),
MADERA_MIXER_ROUTES("AIF3TX1", "AIF3TX1"),
MADERA_MIXER_ROUTES("AIF3TX2", "AIF3TX2"),
MADERA_MIXER_ROUTES("SLIMTX1", "SLIMTX1"),
MADERA_MIXER_ROUTES("SLIMTX2", "SLIMTX2"),
MADERA_MIXER_ROUTES("SLIMTX3", "SLIMTX3"),
MADERA_MIXER_ROUTES("SLIMTX4", "SLIMTX4"),
MADERA_MIXER_ROUTES("SLIMTX5", "SLIMTX5"),
MADERA_MIXER_ROUTES("SLIMTX6", "SLIMTX6"),
MADERA_MUX_ROUTES("SPD1TX1", "SPDIF1TX1"),
MADERA_MUX_ROUTES("SPD1TX2", "SPDIF1TX2"),
MADERA_MIXER_ROUTES("EQ1", "EQ1"),
MADERA_MIXER_ROUTES("EQ2", "EQ2"),
MADERA_MIXER_ROUTES("EQ3", "EQ3"),
MADERA_MIXER_ROUTES("EQ4", "EQ4"),
MADERA_MIXER_ROUTES("DRC1L", "DRC1L"),
MADERA_MIXER_ROUTES("DRC1R", "DRC1R"),
MADERA_MIXER_ROUTES("DRC2L", "DRC2L"),
MADERA_MIXER_ROUTES("DRC2R", "DRC2R"),
MADERA_MIXER_ROUTES("LHPF1", "LHPF1"),
MADERA_MIXER_ROUTES("LHPF2", "LHPF2"),
MADERA_MIXER_ROUTES("LHPF3", "LHPF3"),
MADERA_MIXER_ROUTES("LHPF4", "LHPF4"),
MADERA_DSP_ROUTES("DSP1"),
MADERA_DSP_ROUTES("DSP2"),
MADERA_DSP_ROUTES("DSP3"),
{ "DSP Trigger Out", NULL, "DSP1 Trigger Output" },
{ "DSP Trigger Out", NULL, "DSP2 Trigger Output" },
{ "DSP Trigger Out", NULL, "DSP3 Trigger Output" },
{ "DSP1 Trigger Output", "Switch", "DSP1" },
{ "DSP2 Trigger Output", "Switch", "DSP2" },
{ "DSP3 Trigger Output", "Switch", "DSP3" },
MADERA_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"),
MADERA_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"),
MADERA_MUX_ROUTES("ISRC1INT3", "ISRC1INT3"),
MADERA_MUX_ROUTES("ISRC1INT4", "ISRC1INT4"),
MADERA_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"),
MADERA_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"),
MADERA_MUX_ROUTES("ISRC1DEC3", "ISRC1DEC3"),
MADERA_MUX_ROUTES("ISRC1DEC4", "ISRC1DEC4"),
MADERA_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"),
MADERA_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"),
MADERA_MUX_ROUTES("ISRC2INT3", "ISRC2INT3"),
MADERA_MUX_ROUTES("ISRC2INT4", "ISRC2INT4"),
MADERA_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"),
MADERA_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"),
MADERA_MUX_ROUTES("ISRC2DEC3", "ISRC2DEC3"),
MADERA_MUX_ROUTES("ISRC2DEC4", "ISRC2DEC4"),
{ "AEC1 Loopback", "HPOUT1L", "OUT1L" },
{ "AEC1 Loopback", "HPOUT1R", "OUT1R" },
{ "AEC2 Loopback", "HPOUT1L", "OUT1L" },
{ "AEC2 Loopback", "HPOUT1R", "OUT1R" },
{ "HPOUT1 Demux", NULL, "OUT1L" },
{ "HPOUT1 Demux", NULL, "OUT1R" },
{ "AEC1 Loopback", "SPKOUT", "OUT4L" },
{ "AEC2 Loopback", "SPKOUT", "OUT4L" },
{ "SPKOUTN", NULL, "OUT4L" },
{ "SPKOUTP", NULL, "OUT4L" },
{ "OUT1R", NULL, "HPOUT1 Mono Mux" },
{ "HPOUT1 Mono Mux", "EPOUT", "OUT1L" },
{ "HPOUTL", "HPOUT", "HPOUT1 Demux" },
{ "HPOUTR", "HPOUT", "HPOUT1 Demux" },
{ "EPOUTP", "EPOUT", "HPOUT1 Demux" },
{ "EPOUTN", "EPOUT", "HPOUT1 Demux" },
{ "AEC1 Loopback", "SPKDAT1L", "OUT5L" },
{ "AEC1 Loopback", "SPKDAT1R", "OUT5R" },
{ "AEC2 Loopback", "SPKDAT1L", "OUT5L" },
{ "AEC2 Loopback", "SPKDAT1R", "OUT5R" },
{ "SPKDAT1L", NULL, "OUT5L" },
{ "SPKDAT1R", NULL, "OUT5R" },
{ "SPDIF1", NULL, "SPD1" },
{ "MICSUPP", NULL, "SYSCLK" },
{ "DRC1 Signal Activity", NULL, "DRC1 Activity Output" },
{ "DRC2 Signal Activity", NULL, "DRC2 Activity Output" },
{ "DRC1 Activity Output", "Switch", "DRC1L" },
{ "DRC1 Activity Output", "Switch", "DRC1R" },
{ "DRC2 Activity Output", "Switch", "DRC2L" },
{ "DRC2 Activity Output", "Switch", "DRC2R" },
};
static int cs47l35_set_fll(struct snd_soc_component *component, int fll_id,
int source, unsigned int fref, unsigned int fout)
{
struct cs47l35 *cs47l35 = snd_soc_component_get_drvdata(component);
switch (fll_id) {
case MADERA_FLL1_REFCLK:
return madera_set_fll_refclk(&cs47l35->fll, source, fref,
fout);
case MADERA_FLL1_SYNCCLK:
return madera_set_fll_syncclk(&cs47l35->fll, source, fref,
fout);
default:
return -EINVAL;
}
}
static const struct snd_soc_dai_ops cs47l35_dai_ops = {
.compress_new = snd_soc_new_compress,
};
static struct snd_soc_dai_driver cs47l35_dai[] = {
{
.name = "cs47l35-aif1",
.id = 1,
.base = MADERA_AIF1_BCLK_CTRL,
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 6,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 1,
.channels_max = 6,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &madera_dai_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
{
.name = "cs47l35-aif2",
.id = 2,
.base = MADERA_AIF2_BCLK_CTRL,
.playback = {
.stream_name = "AIF2 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.capture = {
.stream_name = "AIF2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &madera_dai_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
{
.name = "cs47l35-aif3",
.id = 3,
.base = MADERA_AIF3_BCLK_CTRL,
.playback = {
.stream_name = "AIF3 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.capture = {
.stream_name = "AIF3 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &madera_dai_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
{
.name = "cs47l35-slim1",
.id = 4,
.playback = {
.stream_name = "Slim1 Playback",
.channels_min = 1,
.channels_max = 4,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.capture = {
.stream_name = "Slim1 Capture",
.channels_min = 1,
.channels_max = 4,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &madera_simple_dai_ops,
},
{
.name = "cs47l35-slim2",
.id = 5,
.playback = {
.stream_name = "Slim2 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.capture = {
.stream_name = "Slim2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &madera_simple_dai_ops,
},
{
.name = "cs47l35-cpu-voicectrl",
.capture = {
.stream_name = "Voice Control CPU",
.channels_min = 1,
.channels_max = 1,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &cs47l35_dai_ops,
},
{
.name = "cs47l35-dsp-voicectrl",
.capture = {
.stream_name = "Voice Control DSP",
.channels_min = 1,
.channels_max = 1,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
},
{
.name = "cs47l35-cpu-trace",
.capture = {
.stream_name = "Audio Trace CPU",
.channels_min = 1,
.channels_max = 6,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &cs47l35_dai_ops,
},
{
.name = "cs47l35-dsp-trace",
.capture = {
.stream_name = "Audio Trace DSP",
.channels_min = 1,
.channels_max = 6,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
},
};
static int cs47l35_open(struct snd_soc_component *component,
struct snd_compr_stream *stream)
{
struct snd_soc_pcm_runtime *rtd = stream->private_data;
struct cs47l35 *cs47l35 = snd_soc_component_get_drvdata(component);
struct madera_priv *priv = &cs47l35->core;
struct madera *madera = priv->madera;
int n_adsp;
if (strcmp(asoc_rtd_to_codec(rtd, 0)->name, "cs47l35-dsp-voicectrl") == 0) {
n_adsp = 2;
} else if (strcmp(asoc_rtd_to_codec(rtd, 0)->name, "cs47l35-dsp-trace") == 0) {
n_adsp = 0;
} else {
dev_err(madera->dev,
"No suitable compressed stream for DAI '%s'\n",
asoc_rtd_to_codec(rtd, 0)->name);
return -EINVAL;
}
return wm_adsp_compr_open(&priv->adsp[n_adsp], stream);
}
static irqreturn_t cs47l35_adsp2_irq(int irq, void *data)
{
struct cs47l35 *cs47l35 = data;
struct madera_priv *priv = &cs47l35->core;
struct madera *madera = priv->madera;
struct madera_voice_trigger_info trig_info;
int serviced = 0;
int i, ret;
for (i = 0; i < CS47L35_NUM_ADSP; ++i) {
ret = wm_adsp_compr_handle_irq(&priv->adsp[i]);
if (ret != -ENODEV)
serviced++;
if (ret == WM_ADSP_COMPR_VOICE_TRIGGER) {
trig_info.core_num = i + 1;
blocking_notifier_call_chain(&madera->notifier,
MADERA_NOTIFY_VOICE_TRIGGER,
&trig_info);
}
}
if (!serviced) {
dev_err(madera->dev, "Spurious compressed data IRQ\n");
return IRQ_NONE;
}
return IRQ_HANDLED;
}
static const struct snd_soc_dapm_route cs47l35_mono_routes[] = {
{ "HPOUT1 Mono Mux", "HPOUT", "OUT1L" },
};
static int cs47l35_component_probe(struct snd_soc_component *component)
{
struct cs47l35 *cs47l35 = snd_soc_component_get_drvdata(component);
struct madera *madera = cs47l35->core.madera;
int i, ret;
snd_soc_component_init_regmap(component, madera->regmap);
mutex_lock(&madera->dapm_ptr_lock);
madera->dapm = snd_soc_component_get_dapm(component);
mutex_unlock(&madera->dapm_ptr_lock);
ret = madera_init_inputs(component);
if (ret)
return ret;
ret = madera_init_outputs(component, cs47l35_mono_routes,
ARRAY_SIZE(cs47l35_mono_routes),
CS47L35_MONO_OUTPUTS);
if (ret)
return ret;
snd_soc_component_disable_pin(component, "HAPTICS");
ret = snd_soc_add_component_controls(component,
madera_adsp_rate_controls,
CS47L35_NUM_ADSP);
if (ret)
return ret;
for (i = 0; i < CS47L35_NUM_ADSP; i++)
wm_adsp2_component_probe(&cs47l35->core.adsp[i], component);
return 0;
}
static void cs47l35_component_remove(struct snd_soc_component *component)
{
struct cs47l35 *cs47l35 = snd_soc_component_get_drvdata(component);
struct madera *madera = cs47l35->core.madera;
int i;
mutex_lock(&madera->dapm_ptr_lock);
madera->dapm = NULL;
mutex_unlock(&madera->dapm_ptr_lock);
for (i = 0; i < CS47L35_NUM_ADSP; i++)
wm_adsp2_component_remove(&cs47l35->core.adsp[i], component);
}
#define CS47L35_DIG_VU 0x0200
static unsigned int cs47l35_digital_vu[] = {
MADERA_DAC_DIGITAL_VOLUME_1L,
MADERA_DAC_DIGITAL_VOLUME_1R,
MADERA_DAC_DIGITAL_VOLUME_4L,
MADERA_DAC_DIGITAL_VOLUME_5L,
MADERA_DAC_DIGITAL_VOLUME_5R,
};
static const struct snd_compress_ops cs47l35_compress_ops = {
.open = &cs47l35_open,
.free = &wm_adsp_compr_free,
.set_params = &wm_adsp_compr_set_params,
.get_caps = &wm_adsp_compr_get_caps,
.trigger = &wm_adsp_compr_trigger,
.pointer = &wm_adsp_compr_pointer,
.copy = &wm_adsp_compr_copy,
};
static const struct snd_soc_component_driver soc_component_dev_cs47l35 = {
.probe = &cs47l35_component_probe,
.remove = &cs47l35_component_remove,
.set_sysclk = &madera_set_sysclk,
.set_pll = &cs47l35_set_fll,
.name = DRV_NAME,
.compress_ops = &cs47l35_compress_ops,
.controls = cs47l35_snd_controls,
.num_controls = ARRAY_SIZE(cs47l35_snd_controls),
.dapm_widgets = cs47l35_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(cs47l35_dapm_widgets),
.dapm_routes = cs47l35_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(cs47l35_dapm_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
static int cs47l35_probe(struct platform_device *pdev)
{
struct madera *madera = dev_get_drvdata(pdev->dev.parent);
struct cs47l35 *cs47l35;
int i, ret;
BUILD_BUG_ON(ARRAY_SIZE(cs47l35_dai) > MADERA_MAX_DAI);
/* quick exit if Madera irqchip driver hasn't completed probe */
if (!madera->irq_dev) {
dev_dbg(&pdev->dev, "irqchip driver not ready\n");
return -EPROBE_DEFER;
}
cs47l35 = devm_kzalloc(&pdev->dev, sizeof(struct cs47l35), GFP_KERNEL);
if (!cs47l35)
return -ENOMEM;
platform_set_drvdata(pdev, cs47l35);
cs47l35->core.madera = madera;
cs47l35->core.dev = &pdev->dev;
cs47l35->core.num_inputs = 4;
ret = madera_core_init(&cs47l35->core);
if (ret)
return ret;
ret = madera_init_overheat(&cs47l35->core);
if (ret)
goto error_core;
ret = madera_request_irq(madera, MADERA_IRQ_DSP_IRQ1,
"ADSP2 Compressed IRQ", cs47l35_adsp2_irq,
cs47l35);
if (ret) {
dev_err(&pdev->dev, "Failed to request DSP IRQ: %d\n", ret);
goto error_overheat;
}
ret = madera_set_irq_wake(madera, MADERA_IRQ_DSP_IRQ1, 1);
if (ret)
dev_warn(&pdev->dev, "Failed to set DSP IRQ wake: %d\n", ret);
for (i = 0; i < CS47L35_NUM_ADSP; i++) {
cs47l35->core.adsp[i].part = "cs47l35";
cs47l35->core.adsp[i].cs_dsp.num = i + 1;
cs47l35->core.adsp[i].cs_dsp.type = WMFW_ADSP2;
cs47l35->core.adsp[i].cs_dsp.rev = 1;
cs47l35->core.adsp[i].cs_dsp.dev = madera->dev;
cs47l35->core.adsp[i].cs_dsp.regmap = madera->regmap_32bit;
cs47l35->core.adsp[i].cs_dsp.base = wm_adsp2_control_bases[i];
cs47l35->core.adsp[i].cs_dsp.mem = cs47l35_dsp_regions[i];
cs47l35->core.adsp[i].cs_dsp.num_mems =
ARRAY_SIZE(cs47l35_dsp1_regions);
ret = wm_adsp2_init(&cs47l35->core.adsp[i]);
if (ret) {
for (--i; i >= 0; --i)
wm_adsp2_remove(&cs47l35->core.adsp[i]);
goto error_dsp_irq;
}
}
madera_init_fll(madera, 1, MADERA_FLL1_CONTROL_1 - 1, &cs47l35->fll);
for (i = 0; i < ARRAY_SIZE(cs47l35_dai); i++)
madera_init_dai(&cs47l35->core, i);
/* Latch volume update bits */
for (i = 0; i < ARRAY_SIZE(cs47l35_digital_vu); i++)
regmap_update_bits(madera->regmap, cs47l35_digital_vu[i],
CS47L35_DIG_VU, CS47L35_DIG_VU);
pm_runtime_enable(&pdev->dev);
pm_runtime_idle(&pdev->dev);
ret = devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_cs47l35,
cs47l35_dai,
ARRAY_SIZE(cs47l35_dai));
if (ret < 0) {
dev_err(&pdev->dev, "Failed to register component: %d\n", ret);
goto error_pm_runtime;
}
return ret;
error_pm_runtime:
pm_runtime_disable(&pdev->dev);
for (i = 0; i < CS47L35_NUM_ADSP; i++)
wm_adsp2_remove(&cs47l35->core.adsp[i]);
error_dsp_irq:
madera_set_irq_wake(madera, MADERA_IRQ_DSP_IRQ1, 0);
madera_free_irq(madera, MADERA_IRQ_DSP_IRQ1, cs47l35);
error_overheat:
madera_free_overheat(&cs47l35->core);
error_core:
madera_core_free(&cs47l35->core);
return ret;
}
static void cs47l35_remove(struct platform_device *pdev)
{
struct cs47l35 *cs47l35 = platform_get_drvdata(pdev);
int i;
pm_runtime_disable(&pdev->dev);
for (i = 0; i < CS47L35_NUM_ADSP; i++)
wm_adsp2_remove(&cs47l35->core.adsp[i]);
madera_set_irq_wake(cs47l35->core.madera, MADERA_IRQ_DSP_IRQ1, 0);
madera_free_irq(cs47l35->core.madera, MADERA_IRQ_DSP_IRQ1, cs47l35);
madera_free_overheat(&cs47l35->core);
madera_core_free(&cs47l35->core);
}
static struct platform_driver cs47l35_codec_driver = {
.driver = {
.name = "cs47l35-codec",
},
.probe = &cs47l35_probe,
.remove_new = cs47l35_remove,
};
module_platform_driver(cs47l35_codec_driver);
MODULE_SOFTDEP("pre: madera irq-madera arizona-micsupp");
MODULE_DESCRIPTION("ASoC CS47L35 driver");
MODULE_AUTHOR("Piotr Stankiewicz <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:cs47l35-codec");
| linux-master | sound/soc/codecs/cs47l35.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* rt5631.c -- RT5631 ALSA Soc Audio driver
*
* Copyright 2011 Realtek Microelectronics
*
* Author: flove <[email protected]>
*
* Based on WM8753.c
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "rt5631.h"
struct rt5631_priv {
struct regmap *regmap;
int codec_version;
int master;
int sysclk;
int rx_rate;
int bclk_rate;
int dmic_used_flag;
};
static const struct reg_default rt5631_reg[] = {
{ RT5631_SPK_OUT_VOL, 0x8888 },
{ RT5631_HP_OUT_VOL, 0x8080 },
{ RT5631_MONO_AXO_1_2_VOL, 0xa080 },
{ RT5631_AUX_IN_VOL, 0x0808 },
{ RT5631_ADC_REC_MIXER, 0xf0f0 },
{ RT5631_VDAC_DIG_VOL, 0x0010 },
{ RT5631_OUTMIXER_L_CTRL, 0xffc0 },
{ RT5631_OUTMIXER_R_CTRL, 0xffc0 },
{ RT5631_AXO1MIXER_CTRL, 0x88c0 },
{ RT5631_AXO2MIXER_CTRL, 0x88c0 },
{ RT5631_DIG_MIC_CTRL, 0x3000 },
{ RT5631_MONO_INPUT_VOL, 0x8808 },
{ RT5631_SPK_MIXER_CTRL, 0xf8f8 },
{ RT5631_SPK_MONO_OUT_CTRL, 0xfc00 },
{ RT5631_SPK_MONO_HP_OUT_CTRL, 0x4440 },
{ RT5631_SDP_CTRL, 0x8000 },
{ RT5631_MONO_SDP_CTRL, 0x8000 },
{ RT5631_STEREO_AD_DA_CLK_CTRL, 0x2010 },
{ RT5631_GEN_PUR_CTRL_REG, 0x0e00 },
{ RT5631_INT_ST_IRQ_CTRL_2, 0x071a },
{ RT5631_MISC_CTRL, 0x2040 },
{ RT5631_DEPOP_FUN_CTRL_2, 0x8000 },
{ RT5631_SOFT_VOL_CTRL, 0x07e0 },
{ RT5631_ALC_CTRL_1, 0x0206 },
{ RT5631_ALC_CTRL_3, 0x2000 },
{ RT5631_PSEUDO_SPATL_CTRL, 0x0553 },
};
/*
* rt5631_write_index - write index register of 2nd layer
*/
static void rt5631_write_index(struct snd_soc_component *component,
unsigned int reg, unsigned int value)
{
snd_soc_component_write(component, RT5631_INDEX_ADD, reg);
snd_soc_component_write(component, RT5631_INDEX_DATA, value);
}
/*
* rt5631_read_index - read index register of 2nd layer
*/
static unsigned int rt5631_read_index(struct snd_soc_component *component,
unsigned int reg)
{
unsigned int value;
snd_soc_component_write(component, RT5631_INDEX_ADD, reg);
value = snd_soc_component_read(component, RT5631_INDEX_DATA);
return value;
}
static int rt5631_reset(struct snd_soc_component *component)
{
return snd_soc_component_write(component, RT5631_RESET, 0);
}
static bool rt5631_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case RT5631_RESET:
case RT5631_INT_ST_IRQ_CTRL_2:
case RT5631_INDEX_ADD:
case RT5631_INDEX_DATA:
case RT5631_EQ_CTRL:
return true;
default:
return false;
}
}
static bool rt5631_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case RT5631_RESET:
case RT5631_SPK_OUT_VOL:
case RT5631_HP_OUT_VOL:
case RT5631_MONO_AXO_1_2_VOL:
case RT5631_AUX_IN_VOL:
case RT5631_STEREO_DAC_VOL_1:
case RT5631_MIC_CTRL_1:
case RT5631_STEREO_DAC_VOL_2:
case RT5631_ADC_CTRL_1:
case RT5631_ADC_REC_MIXER:
case RT5631_ADC_CTRL_2:
case RT5631_VDAC_DIG_VOL:
case RT5631_OUTMIXER_L_CTRL:
case RT5631_OUTMIXER_R_CTRL:
case RT5631_AXO1MIXER_CTRL:
case RT5631_AXO2MIXER_CTRL:
case RT5631_MIC_CTRL_2:
case RT5631_DIG_MIC_CTRL:
case RT5631_MONO_INPUT_VOL:
case RT5631_SPK_MIXER_CTRL:
case RT5631_SPK_MONO_OUT_CTRL:
case RT5631_SPK_MONO_HP_OUT_CTRL:
case RT5631_SDP_CTRL:
case RT5631_MONO_SDP_CTRL:
case RT5631_STEREO_AD_DA_CLK_CTRL:
case RT5631_PWR_MANAG_ADD1:
case RT5631_PWR_MANAG_ADD2:
case RT5631_PWR_MANAG_ADD3:
case RT5631_PWR_MANAG_ADD4:
case RT5631_GEN_PUR_CTRL_REG:
case RT5631_GLOBAL_CLK_CTRL:
case RT5631_PLL_CTRL:
case RT5631_INT_ST_IRQ_CTRL_1:
case RT5631_INT_ST_IRQ_CTRL_2:
case RT5631_GPIO_CTRL:
case RT5631_MISC_CTRL:
case RT5631_DEPOP_FUN_CTRL_1:
case RT5631_DEPOP_FUN_CTRL_2:
case RT5631_JACK_DET_CTRL:
case RT5631_SOFT_VOL_CTRL:
case RT5631_ALC_CTRL_1:
case RT5631_ALC_CTRL_2:
case RT5631_ALC_CTRL_3:
case RT5631_PSEUDO_SPATL_CTRL:
case RT5631_INDEX_ADD:
case RT5631_INDEX_DATA:
case RT5631_EQ_CTRL:
case RT5631_VENDOR_ID:
case RT5631_VENDOR_ID1:
case RT5631_VENDOR_ID2:
return true;
default:
return false;
}
}
static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -95625, 375, 0);
static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
/* {0, +20, +24, +30, +35, +40, +44, +50, +52}dB */
static const DECLARE_TLV_DB_RANGE(mic_bst_tlv,
0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
);
static int rt5631_dmic_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct rt5631_priv *rt5631 = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = rt5631->dmic_used_flag;
return 0;
}
static int rt5631_dmic_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct rt5631_priv *rt5631 = snd_soc_component_get_drvdata(component);
rt5631->dmic_used_flag = ucontrol->value.integer.value[0];
return 0;
}
/* MIC Input Type */
static const char *rt5631_input_mode[] = {
"Single ended", "Differential"};
static SOC_ENUM_SINGLE_DECL(rt5631_mic1_mode_enum, RT5631_MIC_CTRL_1,
RT5631_MIC1_DIFF_INPUT_SHIFT, rt5631_input_mode);
static SOC_ENUM_SINGLE_DECL(rt5631_mic2_mode_enum, RT5631_MIC_CTRL_1,
RT5631_MIC2_DIFF_INPUT_SHIFT, rt5631_input_mode);
/* MONO Input Type */
static SOC_ENUM_SINGLE_DECL(rt5631_monoin_mode_enum, RT5631_MONO_INPUT_VOL,
RT5631_MONO_DIFF_INPUT_SHIFT, rt5631_input_mode);
/* SPK Ratio Gain Control */
static const char *rt5631_spk_ratio[] = {"1.00x", "1.09x", "1.27x", "1.44x",
"1.56x", "1.68x", "1.99x", "2.34x"};
static SOC_ENUM_SINGLE_DECL(rt5631_spk_ratio_enum, RT5631_GEN_PUR_CTRL_REG,
RT5631_SPK_AMP_RATIO_CTRL_SHIFT, rt5631_spk_ratio);
static const struct snd_kcontrol_new rt5631_snd_controls[] = {
/* MIC */
SOC_ENUM("MIC1 Mode Control", rt5631_mic1_mode_enum),
SOC_SINGLE_TLV("MIC1 Boost Volume", RT5631_MIC_CTRL_2,
RT5631_MIC1_BOOST_SHIFT, 8, 0, mic_bst_tlv),
SOC_ENUM("MIC2 Mode Control", rt5631_mic2_mode_enum),
SOC_SINGLE_TLV("MIC2 Boost Volume", RT5631_MIC_CTRL_2,
RT5631_MIC2_BOOST_SHIFT, 8, 0, mic_bst_tlv),
/* MONO IN */
SOC_ENUM("MONOIN Mode Control", rt5631_monoin_mode_enum),
SOC_DOUBLE_TLV("MONOIN_RX Capture Volume", RT5631_MONO_INPUT_VOL,
RT5631_L_VOL_SHIFT, RT5631_R_VOL_SHIFT,
RT5631_VOL_MASK, 1, in_vol_tlv),
/* AXI */
SOC_DOUBLE_TLV("AXI Capture Volume", RT5631_AUX_IN_VOL,
RT5631_L_VOL_SHIFT, RT5631_R_VOL_SHIFT,
RT5631_VOL_MASK, 1, in_vol_tlv),
/* DAC */
SOC_DOUBLE_TLV("PCM Playback Volume", RT5631_STEREO_DAC_VOL_2,
RT5631_L_VOL_SHIFT, RT5631_R_VOL_SHIFT,
RT5631_DAC_VOL_MASK, 1, dac_vol_tlv),
SOC_DOUBLE("PCM Playback Switch", RT5631_STEREO_DAC_VOL_1,
RT5631_L_MUTE_SHIFT, RT5631_R_MUTE_SHIFT, 1, 1),
/* AXO */
SOC_SINGLE("AXO1 Playback Switch", RT5631_MONO_AXO_1_2_VOL,
RT5631_L_MUTE_SHIFT, 1, 1),
SOC_SINGLE("AXO2 Playback Switch", RT5631_MONO_AXO_1_2_VOL,
RT5631_R_VOL_SHIFT, 1, 1),
/* OUTVOL */
SOC_DOUBLE("OUTVOL Channel Switch", RT5631_SPK_OUT_VOL,
RT5631_L_EN_SHIFT, RT5631_R_EN_SHIFT, 1, 0),
/* SPK */
SOC_DOUBLE("Speaker Playback Switch", RT5631_SPK_OUT_VOL,
RT5631_L_MUTE_SHIFT, RT5631_R_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_TLV("Speaker Playback Volume", RT5631_SPK_OUT_VOL,
RT5631_L_VOL_SHIFT, RT5631_R_VOL_SHIFT, 39, 1, out_vol_tlv),
/* MONO OUT */
SOC_SINGLE("MONO Playback Switch", RT5631_MONO_AXO_1_2_VOL,
RT5631_MUTE_MONO_SHIFT, 1, 1),
/* HP */
SOC_DOUBLE("HP Playback Switch", RT5631_HP_OUT_VOL,
RT5631_L_MUTE_SHIFT, RT5631_R_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_TLV("HP Playback Volume", RT5631_HP_OUT_VOL,
RT5631_L_VOL_SHIFT, RT5631_R_VOL_SHIFT,
RT5631_VOL_MASK, 1, out_vol_tlv),
/* DMIC */
SOC_SINGLE_EXT("DMIC Switch", 0, 0, 1, 0,
rt5631_dmic_get, rt5631_dmic_put),
SOC_DOUBLE("DMIC Capture Switch", RT5631_DIG_MIC_CTRL,
RT5631_DMIC_L_CH_MUTE_SHIFT,
RT5631_DMIC_R_CH_MUTE_SHIFT, 1, 1),
/* SPK Ratio Gain Control */
SOC_ENUM("SPK Ratio Control", rt5631_spk_ratio_enum),
};
static int check_sysclk1_source(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
unsigned int reg;
reg = snd_soc_component_read(component, RT5631_GLOBAL_CLK_CTRL);
return reg & RT5631_SYSCLK_SOUR_SEL_PLL;
}
static int check_dmic_used(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
struct rt5631_priv *rt5631 = snd_soc_component_get_drvdata(component);
return rt5631->dmic_used_flag;
}
static int check_dacl_to_outmixl(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
unsigned int reg;
reg = snd_soc_component_read(component, RT5631_OUTMIXER_L_CTRL);
return !(reg & RT5631_M_DAC_L_TO_OUTMIXER_L);
}
static int check_dacr_to_outmixr(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
unsigned int reg;
reg = snd_soc_component_read(component, RT5631_OUTMIXER_R_CTRL);
return !(reg & RT5631_M_DAC_R_TO_OUTMIXER_R);
}
static int check_dacl_to_spkmixl(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
unsigned int reg;
reg = snd_soc_component_read(component, RT5631_SPK_MIXER_CTRL);
return !(reg & RT5631_M_DAC_L_TO_SPKMIXER_L);
}
static int check_dacr_to_spkmixr(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
unsigned int reg;
reg = snd_soc_component_read(component, RT5631_SPK_MIXER_CTRL);
return !(reg & RT5631_M_DAC_R_TO_SPKMIXER_R);
}
static int check_adcl_select(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
unsigned int reg;
reg = snd_soc_component_read(component, RT5631_ADC_REC_MIXER);
return !(reg & RT5631_M_MIC1_TO_RECMIXER_L);
}
static int check_adcr_select(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
unsigned int reg;
reg = snd_soc_component_read(component, RT5631_ADC_REC_MIXER);
return !(reg & RT5631_M_MIC2_TO_RECMIXER_R);
}
/**
* onebit_depop_power_stage - auto depop in power stage.
* @component: ASoC component
* @enable: power on/off
*
* When power on/off headphone, the depop sequence is done by hardware.
*/
static void onebit_depop_power_stage(struct snd_soc_component *component, int enable)
{
unsigned int soft_vol, hp_zc;
/* enable one-bit depop function */
snd_soc_component_update_bits(component, RT5631_DEPOP_FUN_CTRL_2,
RT5631_EN_ONE_BIT_DEPOP, 0);
/* keep soft volume and zero crossing setting */
soft_vol = snd_soc_component_read(component, RT5631_SOFT_VOL_CTRL);
snd_soc_component_write(component, RT5631_SOFT_VOL_CTRL, 0);
hp_zc = snd_soc_component_read(component, RT5631_INT_ST_IRQ_CTRL_2);
snd_soc_component_write(component, RT5631_INT_ST_IRQ_CTRL_2, hp_zc & 0xf7ff);
if (enable) {
/* config one-bit depop parameter */
rt5631_write_index(component, RT5631_TEST_MODE_CTRL, 0x84c0);
rt5631_write_index(component, RT5631_SPK_INTL_CTRL, 0x309f);
rt5631_write_index(component, RT5631_CP_INTL_REG2, 0x6530);
/* power on capless block */
snd_soc_component_write(component, RT5631_DEPOP_FUN_CTRL_2,
RT5631_EN_CAP_FREE_DEPOP);
} else {
/* power off capless block */
snd_soc_component_write(component, RT5631_DEPOP_FUN_CTRL_2, 0);
msleep(100);
}
/* recover soft volume and zero crossing setting */
snd_soc_component_write(component, RT5631_SOFT_VOL_CTRL, soft_vol);
snd_soc_component_write(component, RT5631_INT_ST_IRQ_CTRL_2, hp_zc);
}
/**
* onebit_depop_mute_stage - auto depop in mute stage.
* @component: ASoC component
* @enable: mute/unmute
*
* When mute/unmute headphone, the depop sequence is done by hardware.
*/
static void onebit_depop_mute_stage(struct snd_soc_component *component, int enable)
{
unsigned int soft_vol, hp_zc;
/* enable one-bit depop function */
snd_soc_component_update_bits(component, RT5631_DEPOP_FUN_CTRL_2,
RT5631_EN_ONE_BIT_DEPOP, 0);
/* keep soft volume and zero crossing setting */
soft_vol = snd_soc_component_read(component, RT5631_SOFT_VOL_CTRL);
snd_soc_component_write(component, RT5631_SOFT_VOL_CTRL, 0);
hp_zc = snd_soc_component_read(component, RT5631_INT_ST_IRQ_CTRL_2);
snd_soc_component_write(component, RT5631_INT_ST_IRQ_CTRL_2, hp_zc & 0xf7ff);
if (enable) {
schedule_timeout_uninterruptible(msecs_to_jiffies(10));
/* config one-bit depop parameter */
rt5631_write_index(component, RT5631_SPK_INTL_CTRL, 0x307f);
snd_soc_component_update_bits(component, RT5631_HP_OUT_VOL,
RT5631_L_MUTE | RT5631_R_MUTE, 0);
msleep(300);
} else {
snd_soc_component_update_bits(component, RT5631_HP_OUT_VOL,
RT5631_L_MUTE | RT5631_R_MUTE,
RT5631_L_MUTE | RT5631_R_MUTE);
msleep(100);
}
/* recover soft volume and zero crossing setting */
snd_soc_component_write(component, RT5631_SOFT_VOL_CTRL, soft_vol);
snd_soc_component_write(component, RT5631_INT_ST_IRQ_CTRL_2, hp_zc);
}
/**
* depop_seq_power_stage - step by step depop sequence in power stage.
* @component: ASoC component
* @enable: power on/off
*
* When power on/off headphone, the depop sequence is done in step by step.
*/
static void depop_seq_power_stage(struct snd_soc_component *component, int enable)
{
unsigned int soft_vol, hp_zc;
/* depop control by register */
snd_soc_component_update_bits(component, RT5631_DEPOP_FUN_CTRL_2,
RT5631_EN_ONE_BIT_DEPOP, RT5631_EN_ONE_BIT_DEPOP);
/* keep soft volume and zero crossing setting */
soft_vol = snd_soc_component_read(component, RT5631_SOFT_VOL_CTRL);
snd_soc_component_write(component, RT5631_SOFT_VOL_CTRL, 0);
hp_zc = snd_soc_component_read(component, RT5631_INT_ST_IRQ_CTRL_2);
snd_soc_component_write(component, RT5631_INT_ST_IRQ_CTRL_2, hp_zc & 0xf7ff);
if (enable) {
/* config depop sequence parameter */
rt5631_write_index(component, RT5631_SPK_INTL_CTRL, 0x303e);
/* power on headphone and charge pump */
snd_soc_component_update_bits(component, RT5631_PWR_MANAG_ADD3,
RT5631_PWR_CHARGE_PUMP | RT5631_PWR_HP_L_AMP |
RT5631_PWR_HP_R_AMP,
RT5631_PWR_CHARGE_PUMP | RT5631_PWR_HP_L_AMP |
RT5631_PWR_HP_R_AMP);
/* power on soft generator and depop mode2 */
snd_soc_component_write(component, RT5631_DEPOP_FUN_CTRL_1,
RT5631_POW_ON_SOFT_GEN | RT5631_EN_DEPOP2_FOR_HP);
msleep(100);
/* stop depop mode */
snd_soc_component_update_bits(component, RT5631_PWR_MANAG_ADD3,
RT5631_PWR_HP_DEPOP_DIS, RT5631_PWR_HP_DEPOP_DIS);
} else {
/* config depop sequence parameter */
rt5631_write_index(component, RT5631_SPK_INTL_CTRL, 0x303F);
snd_soc_component_write(component, RT5631_DEPOP_FUN_CTRL_1,
RT5631_POW_ON_SOFT_GEN | RT5631_EN_MUTE_UNMUTE_DEPOP |
RT5631_PD_HPAMP_L_ST_UP | RT5631_PD_HPAMP_R_ST_UP);
msleep(75);
snd_soc_component_write(component, RT5631_DEPOP_FUN_CTRL_1,
RT5631_POW_ON_SOFT_GEN | RT5631_PD_HPAMP_L_ST_UP |
RT5631_PD_HPAMP_R_ST_UP);
/* start depop mode */
snd_soc_component_update_bits(component, RT5631_PWR_MANAG_ADD3,
RT5631_PWR_HP_DEPOP_DIS, 0);
/* config depop sequence parameter */
snd_soc_component_write(component, RT5631_DEPOP_FUN_CTRL_1,
RT5631_POW_ON_SOFT_GEN | RT5631_EN_DEPOP2_FOR_HP |
RT5631_PD_HPAMP_L_ST_UP | RT5631_PD_HPAMP_R_ST_UP);
msleep(80);
snd_soc_component_write(component, RT5631_DEPOP_FUN_CTRL_1,
RT5631_POW_ON_SOFT_GEN);
/* power down headphone and charge pump */
snd_soc_component_update_bits(component, RT5631_PWR_MANAG_ADD3,
RT5631_PWR_CHARGE_PUMP | RT5631_PWR_HP_L_AMP |
RT5631_PWR_HP_R_AMP, 0);
}
/* recover soft volume and zero crossing setting */
snd_soc_component_write(component, RT5631_SOFT_VOL_CTRL, soft_vol);
snd_soc_component_write(component, RT5631_INT_ST_IRQ_CTRL_2, hp_zc);
}
/**
* depop_seq_mute_stage - step by step depop sequence in mute stage.
* @component: ASoC component
* @enable: mute/unmute
*
* When mute/unmute headphone, the depop sequence is done in step by step.
*/
static void depop_seq_mute_stage(struct snd_soc_component *component, int enable)
{
unsigned int soft_vol, hp_zc;
/* depop control by register */
snd_soc_component_update_bits(component, RT5631_DEPOP_FUN_CTRL_2,
RT5631_EN_ONE_BIT_DEPOP, RT5631_EN_ONE_BIT_DEPOP);
/* keep soft volume and zero crossing setting */
soft_vol = snd_soc_component_read(component, RT5631_SOFT_VOL_CTRL);
snd_soc_component_write(component, RT5631_SOFT_VOL_CTRL, 0);
hp_zc = snd_soc_component_read(component, RT5631_INT_ST_IRQ_CTRL_2);
snd_soc_component_write(component, RT5631_INT_ST_IRQ_CTRL_2, hp_zc & 0xf7ff);
if (enable) {
schedule_timeout_uninterruptible(msecs_to_jiffies(10));
/* config depop sequence parameter */
rt5631_write_index(component, RT5631_SPK_INTL_CTRL, 0x302f);
snd_soc_component_write(component, RT5631_DEPOP_FUN_CTRL_1,
RT5631_POW_ON_SOFT_GEN | RT5631_EN_MUTE_UNMUTE_DEPOP |
RT5631_EN_HP_R_M_UN_MUTE_DEPOP |
RT5631_EN_HP_L_M_UN_MUTE_DEPOP);
snd_soc_component_update_bits(component, RT5631_HP_OUT_VOL,
RT5631_L_MUTE | RT5631_R_MUTE, 0);
msleep(160);
} else {
/* config depop sequence parameter */
rt5631_write_index(component, RT5631_SPK_INTL_CTRL, 0x302f);
snd_soc_component_write(component, RT5631_DEPOP_FUN_CTRL_1,
RT5631_POW_ON_SOFT_GEN | RT5631_EN_MUTE_UNMUTE_DEPOP |
RT5631_EN_HP_R_M_UN_MUTE_DEPOP |
RT5631_EN_HP_L_M_UN_MUTE_DEPOP);
snd_soc_component_update_bits(component, RT5631_HP_OUT_VOL,
RT5631_L_MUTE | RT5631_R_MUTE,
RT5631_L_MUTE | RT5631_R_MUTE);
msleep(150);
}
/* recover soft volume and zero crossing setting */
snd_soc_component_write(component, RT5631_SOFT_VOL_CTRL, soft_vol);
snd_soc_component_write(component, RT5631_INT_ST_IRQ_CTRL_2, hp_zc);
}
static int hp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5631_priv *rt5631 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMD:
if (rt5631->codec_version) {
onebit_depop_mute_stage(component, 0);
onebit_depop_power_stage(component, 0);
} else {
depop_seq_mute_stage(component, 0);
depop_seq_power_stage(component, 0);
}
break;
case SND_SOC_DAPM_POST_PMU:
if (rt5631->codec_version) {
onebit_depop_power_stage(component, 1);
onebit_depop_mute_stage(component, 1);
} else {
depop_seq_power_stage(component, 1);
depop_seq_mute_stage(component, 1);
}
break;
default:
break;
}
return 0;
}
static int set_dmic_params(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5631_priv *rt5631 = snd_soc_component_get_drvdata(component);
switch (rt5631->rx_rate) {
case 44100:
case 48000:
snd_soc_component_update_bits(component, RT5631_DIG_MIC_CTRL,
RT5631_DMIC_CLK_CTRL_MASK,
RT5631_DMIC_CLK_CTRL_TO_32FS);
break;
case 32000:
case 22050:
snd_soc_component_update_bits(component, RT5631_DIG_MIC_CTRL,
RT5631_DMIC_CLK_CTRL_MASK,
RT5631_DMIC_CLK_CTRL_TO_64FS);
break;
case 16000:
case 11025:
case 8000:
snd_soc_component_update_bits(component, RT5631_DIG_MIC_CTRL,
RT5631_DMIC_CLK_CTRL_MASK,
RT5631_DMIC_CLK_CTRL_TO_128FS);
break;
default:
return -EINVAL;
}
return 0;
}
static const struct snd_kcontrol_new rt5631_recmixl_mixer_controls[] = {
SOC_DAPM_SINGLE("OUTMIXL Capture Switch", RT5631_ADC_REC_MIXER,
RT5631_M_OUTMIXL_RECMIXL_BIT, 1, 1),
SOC_DAPM_SINGLE("MIC1_BST1 Capture Switch", RT5631_ADC_REC_MIXER,
RT5631_M_MIC1_RECMIXL_BIT, 1, 1),
SOC_DAPM_SINGLE("AXILVOL Capture Switch", RT5631_ADC_REC_MIXER,
RT5631_M_AXIL_RECMIXL_BIT, 1, 1),
SOC_DAPM_SINGLE("MONOIN_RX Capture Switch", RT5631_ADC_REC_MIXER,
RT5631_M_MONO_IN_RECMIXL_BIT, 1, 1),
};
static const struct snd_kcontrol_new rt5631_recmixr_mixer_controls[] = {
SOC_DAPM_SINGLE("MONOIN_RX Capture Switch", RT5631_ADC_REC_MIXER,
RT5631_M_MONO_IN_RECMIXR_BIT, 1, 1),
SOC_DAPM_SINGLE("AXIRVOL Capture Switch", RT5631_ADC_REC_MIXER,
RT5631_M_AXIR_RECMIXR_BIT, 1, 1),
SOC_DAPM_SINGLE("MIC2_BST2 Capture Switch", RT5631_ADC_REC_MIXER,
RT5631_M_MIC2_RECMIXR_BIT, 1, 1),
SOC_DAPM_SINGLE("OUTMIXR Capture Switch", RT5631_ADC_REC_MIXER,
RT5631_M_OUTMIXR_RECMIXR_BIT, 1, 1),
};
static const struct snd_kcontrol_new rt5631_spkmixl_mixer_controls[] = {
SOC_DAPM_SINGLE("RECMIXL Playback Switch", RT5631_SPK_MIXER_CTRL,
RT5631_M_RECMIXL_SPKMIXL_BIT, 1, 1),
SOC_DAPM_SINGLE("MIC1_P Playback Switch", RT5631_SPK_MIXER_CTRL,
RT5631_M_MIC1P_SPKMIXL_BIT, 1, 1),
SOC_DAPM_SINGLE("DACL Playback Switch", RT5631_SPK_MIXER_CTRL,
RT5631_M_DACL_SPKMIXL_BIT, 1, 1),
SOC_DAPM_SINGLE("OUTMIXL Playback Switch", RT5631_SPK_MIXER_CTRL,
RT5631_M_OUTMIXL_SPKMIXL_BIT, 1, 1),
};
static const struct snd_kcontrol_new rt5631_spkmixr_mixer_controls[] = {
SOC_DAPM_SINGLE("OUTMIXR Playback Switch", RT5631_SPK_MIXER_CTRL,
RT5631_M_OUTMIXR_SPKMIXR_BIT, 1, 1),
SOC_DAPM_SINGLE("DACR Playback Switch", RT5631_SPK_MIXER_CTRL,
RT5631_M_DACR_SPKMIXR_BIT, 1, 1),
SOC_DAPM_SINGLE("MIC2_P Playback Switch", RT5631_SPK_MIXER_CTRL,
RT5631_M_MIC2P_SPKMIXR_BIT, 1, 1),
SOC_DAPM_SINGLE("RECMIXR Playback Switch", RT5631_SPK_MIXER_CTRL,
RT5631_M_RECMIXR_SPKMIXR_BIT, 1, 1),
};
static const struct snd_kcontrol_new rt5631_outmixl_mixer_controls[] = {
SOC_DAPM_SINGLE("RECMIXL Playback Switch", RT5631_OUTMIXER_L_CTRL,
RT5631_M_RECMIXL_OUTMIXL_BIT, 1, 1),
SOC_DAPM_SINGLE("RECMIXR Playback Switch", RT5631_OUTMIXER_L_CTRL,
RT5631_M_RECMIXR_OUTMIXL_BIT, 1, 1),
SOC_DAPM_SINGLE("DACL Playback Switch", RT5631_OUTMIXER_L_CTRL,
RT5631_M_DACL_OUTMIXL_BIT, 1, 1),
SOC_DAPM_SINGLE("MIC1_BST1 Playback Switch", RT5631_OUTMIXER_L_CTRL,
RT5631_M_MIC1_OUTMIXL_BIT, 1, 1),
SOC_DAPM_SINGLE("MIC2_BST2 Playback Switch", RT5631_OUTMIXER_L_CTRL,
RT5631_M_MIC2_OUTMIXL_BIT, 1, 1),
SOC_DAPM_SINGLE("MONOIN_RXP Playback Switch", RT5631_OUTMIXER_L_CTRL,
RT5631_M_MONO_INP_OUTMIXL_BIT, 1, 1),
SOC_DAPM_SINGLE("AXILVOL Playback Switch", RT5631_OUTMIXER_L_CTRL,
RT5631_M_AXIL_OUTMIXL_BIT, 1, 1),
SOC_DAPM_SINGLE("AXIRVOL Playback Switch", RT5631_OUTMIXER_L_CTRL,
RT5631_M_AXIR_OUTMIXL_BIT, 1, 1),
SOC_DAPM_SINGLE("VDAC Playback Switch", RT5631_OUTMIXER_L_CTRL,
RT5631_M_VDAC_OUTMIXL_BIT, 1, 1),
};
static const struct snd_kcontrol_new rt5631_outmixr_mixer_controls[] = {
SOC_DAPM_SINGLE("VDAC Playback Switch", RT5631_OUTMIXER_R_CTRL,
RT5631_M_VDAC_OUTMIXR_BIT, 1, 1),
SOC_DAPM_SINGLE("AXIRVOL Playback Switch", RT5631_OUTMIXER_R_CTRL,
RT5631_M_AXIR_OUTMIXR_BIT, 1, 1),
SOC_DAPM_SINGLE("AXILVOL Playback Switch", RT5631_OUTMIXER_R_CTRL,
RT5631_M_AXIL_OUTMIXR_BIT, 1, 1),
SOC_DAPM_SINGLE("MONOIN_RXN Playback Switch", RT5631_OUTMIXER_R_CTRL,
RT5631_M_MONO_INN_OUTMIXR_BIT, 1, 1),
SOC_DAPM_SINGLE("MIC2_BST2 Playback Switch", RT5631_OUTMIXER_R_CTRL,
RT5631_M_MIC2_OUTMIXR_BIT, 1, 1),
SOC_DAPM_SINGLE("MIC1_BST1 Playback Switch", RT5631_OUTMIXER_R_CTRL,
RT5631_M_MIC1_OUTMIXR_BIT, 1, 1),
SOC_DAPM_SINGLE("DACR Playback Switch", RT5631_OUTMIXER_R_CTRL,
RT5631_M_DACR_OUTMIXR_BIT, 1, 1),
SOC_DAPM_SINGLE("RECMIXR Playback Switch", RT5631_OUTMIXER_R_CTRL,
RT5631_M_RECMIXR_OUTMIXR_BIT, 1, 1),
SOC_DAPM_SINGLE("RECMIXL Playback Switch", RT5631_OUTMIXER_R_CTRL,
RT5631_M_RECMIXL_OUTMIXR_BIT, 1, 1),
};
static const struct snd_kcontrol_new rt5631_AXO1MIX_mixer_controls[] = {
SOC_DAPM_SINGLE("MIC1_BST1 Playback Switch", RT5631_AXO1MIXER_CTRL,
RT5631_M_MIC1_AXO1MIX_BIT , 1, 1),
SOC_DAPM_SINGLE("MIC2_BST2 Playback Switch", RT5631_AXO1MIXER_CTRL,
RT5631_M_MIC2_AXO1MIX_BIT, 1, 1),
SOC_DAPM_SINGLE("OUTVOLL Playback Switch", RT5631_AXO1MIXER_CTRL,
RT5631_M_OUTMIXL_AXO1MIX_BIT , 1 , 1),
SOC_DAPM_SINGLE("OUTVOLR Playback Switch", RT5631_AXO1MIXER_CTRL,
RT5631_M_OUTMIXR_AXO1MIX_BIT, 1, 1),
};
static const struct snd_kcontrol_new rt5631_AXO2MIX_mixer_controls[] = {
SOC_DAPM_SINGLE("MIC1_BST1 Playback Switch", RT5631_AXO2MIXER_CTRL,
RT5631_M_MIC1_AXO2MIX_BIT, 1, 1),
SOC_DAPM_SINGLE("MIC2_BST2 Playback Switch", RT5631_AXO2MIXER_CTRL,
RT5631_M_MIC2_AXO2MIX_BIT, 1, 1),
SOC_DAPM_SINGLE("OUTVOLL Playback Switch", RT5631_AXO2MIXER_CTRL,
RT5631_M_OUTMIXL_AXO2MIX_BIT, 1, 1),
SOC_DAPM_SINGLE("OUTVOLR Playback Switch", RT5631_AXO2MIXER_CTRL,
RT5631_M_OUTMIXR_AXO2MIX_BIT, 1 , 1),
};
static const struct snd_kcontrol_new rt5631_spolmix_mixer_controls[] = {
SOC_DAPM_SINGLE("SPKVOLL Playback Switch", RT5631_SPK_MONO_OUT_CTRL,
RT5631_M_SPKVOLL_SPOLMIX_BIT, 1, 1),
SOC_DAPM_SINGLE("SPKVOLR Playback Switch", RT5631_SPK_MONO_OUT_CTRL,
RT5631_M_SPKVOLR_SPOLMIX_BIT, 1, 1),
};
static const struct snd_kcontrol_new rt5631_spormix_mixer_controls[] = {
SOC_DAPM_SINGLE("SPKVOLL Playback Switch", RT5631_SPK_MONO_OUT_CTRL,
RT5631_M_SPKVOLL_SPORMIX_BIT, 1, 1),
SOC_DAPM_SINGLE("SPKVOLR Playback Switch", RT5631_SPK_MONO_OUT_CTRL,
RT5631_M_SPKVOLR_SPORMIX_BIT, 1, 1),
};
static const struct snd_kcontrol_new rt5631_monomix_mixer_controls[] = {
SOC_DAPM_SINGLE("OUTVOLL Playback Switch", RT5631_SPK_MONO_OUT_CTRL,
RT5631_M_OUTVOLL_MONOMIX_BIT, 1, 1),
SOC_DAPM_SINGLE("OUTVOLR Playback Switch", RT5631_SPK_MONO_OUT_CTRL,
RT5631_M_OUTVOLR_MONOMIX_BIT, 1, 1),
};
/* Left SPK Volume Input */
static const char *rt5631_spkvoll_sel[] = {"Vmid", "SPKMIXL"};
static SOC_ENUM_SINGLE_DECL(rt5631_spkvoll_enum, RT5631_SPK_OUT_VOL,
RT5631_L_EN_SHIFT, rt5631_spkvoll_sel);
static const struct snd_kcontrol_new rt5631_spkvoll_mux_control =
SOC_DAPM_ENUM("Left SPKVOL SRC", rt5631_spkvoll_enum);
/* Left HP Volume Input */
static const char *rt5631_hpvoll_sel[] = {"Vmid", "OUTMIXL"};
static SOC_ENUM_SINGLE_DECL(rt5631_hpvoll_enum, RT5631_HP_OUT_VOL,
RT5631_L_EN_SHIFT, rt5631_hpvoll_sel);
static const struct snd_kcontrol_new rt5631_hpvoll_mux_control =
SOC_DAPM_ENUM("Left HPVOL SRC", rt5631_hpvoll_enum);
/* Left Out Volume Input */
static const char *rt5631_outvoll_sel[] = {"Vmid", "OUTMIXL"};
static SOC_ENUM_SINGLE_DECL(rt5631_outvoll_enum, RT5631_MONO_AXO_1_2_VOL,
RT5631_L_EN_SHIFT, rt5631_outvoll_sel);
static const struct snd_kcontrol_new rt5631_outvoll_mux_control =
SOC_DAPM_ENUM("Left OUTVOL SRC", rt5631_outvoll_enum);
/* Right Out Volume Input */
static const char *rt5631_outvolr_sel[] = {"Vmid", "OUTMIXR"};
static SOC_ENUM_SINGLE_DECL(rt5631_outvolr_enum, RT5631_MONO_AXO_1_2_VOL,
RT5631_R_EN_SHIFT, rt5631_outvolr_sel);
static const struct snd_kcontrol_new rt5631_outvolr_mux_control =
SOC_DAPM_ENUM("Right OUTVOL SRC", rt5631_outvolr_enum);
/* Right HP Volume Input */
static const char *rt5631_hpvolr_sel[] = {"Vmid", "OUTMIXR"};
static SOC_ENUM_SINGLE_DECL(rt5631_hpvolr_enum, RT5631_HP_OUT_VOL,
RT5631_R_EN_SHIFT, rt5631_hpvolr_sel);
static const struct snd_kcontrol_new rt5631_hpvolr_mux_control =
SOC_DAPM_ENUM("Right HPVOL SRC", rt5631_hpvolr_enum);
/* Right SPK Volume Input */
static const char *rt5631_spkvolr_sel[] = {"Vmid", "SPKMIXR"};
static SOC_ENUM_SINGLE_DECL(rt5631_spkvolr_enum, RT5631_SPK_OUT_VOL,
RT5631_R_EN_SHIFT, rt5631_spkvolr_sel);
static const struct snd_kcontrol_new rt5631_spkvolr_mux_control =
SOC_DAPM_ENUM("Right SPKVOL SRC", rt5631_spkvolr_enum);
/* SPO Left Channel Input */
static const char *rt5631_spol_src_sel[] = {
"SPOLMIX", "MONOIN_RX", "VDAC", "DACL"};
static SOC_ENUM_SINGLE_DECL(rt5631_spol_src_enum, RT5631_SPK_MONO_HP_OUT_CTRL,
RT5631_SPK_L_MUX_SEL_SHIFT, rt5631_spol_src_sel);
static const struct snd_kcontrol_new rt5631_spol_mux_control =
SOC_DAPM_ENUM("SPOL SRC", rt5631_spol_src_enum);
/* SPO Right Channel Input */
static const char *rt5631_spor_src_sel[] = {
"SPORMIX", "MONOIN_RX", "VDAC", "DACR"};
static SOC_ENUM_SINGLE_DECL(rt5631_spor_src_enum, RT5631_SPK_MONO_HP_OUT_CTRL,
RT5631_SPK_R_MUX_SEL_SHIFT, rt5631_spor_src_sel);
static const struct snd_kcontrol_new rt5631_spor_mux_control =
SOC_DAPM_ENUM("SPOR SRC", rt5631_spor_src_enum);
/* MONO Input */
static const char *rt5631_mono_src_sel[] = {"MONOMIX", "MONOIN_RX", "VDAC"};
static SOC_ENUM_SINGLE_DECL(rt5631_mono_src_enum, RT5631_SPK_MONO_HP_OUT_CTRL,
RT5631_MONO_MUX_SEL_SHIFT, rt5631_mono_src_sel);
static const struct snd_kcontrol_new rt5631_mono_mux_control =
SOC_DAPM_ENUM("MONO SRC", rt5631_mono_src_enum);
/* Left HPO Input */
static const char *rt5631_hpl_src_sel[] = {"Left HPVOL", "Left DAC"};
static SOC_ENUM_SINGLE_DECL(rt5631_hpl_src_enum, RT5631_SPK_MONO_HP_OUT_CTRL,
RT5631_HP_L_MUX_SEL_SHIFT, rt5631_hpl_src_sel);
static const struct snd_kcontrol_new rt5631_hpl_mux_control =
SOC_DAPM_ENUM("HPL SRC", rt5631_hpl_src_enum);
/* Right HPO Input */
static const char *rt5631_hpr_src_sel[] = {"Right HPVOL", "Right DAC"};
static SOC_ENUM_SINGLE_DECL(rt5631_hpr_src_enum, RT5631_SPK_MONO_HP_OUT_CTRL,
RT5631_HP_R_MUX_SEL_SHIFT, rt5631_hpr_src_sel);
static const struct snd_kcontrol_new rt5631_hpr_mux_control =
SOC_DAPM_ENUM("HPR SRC", rt5631_hpr_src_enum);
static const struct snd_soc_dapm_widget rt5631_dapm_widgets[] = {
/* Vmid */
SND_SOC_DAPM_VMID("Vmid"),
/* PLL1 */
SND_SOC_DAPM_SUPPLY("PLL1", RT5631_PWR_MANAG_ADD2,
RT5631_PWR_PLL1_BIT, 0, NULL, 0),
/* Input Side */
/* Input Lines */
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_INPUT("MIC2"),
SND_SOC_DAPM_INPUT("AXIL"),
SND_SOC_DAPM_INPUT("AXIR"),
SND_SOC_DAPM_INPUT("MONOIN_RXN"),
SND_SOC_DAPM_INPUT("MONOIN_RXP"),
SND_SOC_DAPM_INPUT("DMIC"),
/* MICBIAS */
SND_SOC_DAPM_MICBIAS("MIC Bias1", RT5631_PWR_MANAG_ADD2,
RT5631_PWR_MICBIAS1_VOL_BIT, 0),
SND_SOC_DAPM_MICBIAS("MIC Bias2", RT5631_PWR_MANAG_ADD2,
RT5631_PWR_MICBIAS2_VOL_BIT, 0),
/* Boost */
SND_SOC_DAPM_PGA("MIC1 Boost", RT5631_PWR_MANAG_ADD2,
RT5631_PWR_MIC1_BOOT_GAIN_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("MIC2 Boost", RT5631_PWR_MANAG_ADD2,
RT5631_PWR_MIC2_BOOT_GAIN_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("MONOIN_RXP Boost", RT5631_PWR_MANAG_ADD4,
RT5631_PWR_MONO_IN_P_VOL_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("MONOIN_RXN Boost", RT5631_PWR_MANAG_ADD4,
RT5631_PWR_MONO_IN_N_VOL_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("AXIL Boost", RT5631_PWR_MANAG_ADD4,
RT5631_PWR_AXIL_IN_VOL_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("AXIR Boost", RT5631_PWR_MANAG_ADD4,
RT5631_PWR_AXIR_IN_VOL_BIT, 0, NULL, 0),
/* MONO In */
SND_SOC_DAPM_MIXER("MONO_IN", SND_SOC_NOPM, 0, 0, NULL, 0),
/* REC Mixer */
SND_SOC_DAPM_MIXER("RECMIXL Mixer", RT5631_PWR_MANAG_ADD2,
RT5631_PWR_RECMIXER_L_BIT, 0,
&rt5631_recmixl_mixer_controls[0],
ARRAY_SIZE(rt5631_recmixl_mixer_controls)),
SND_SOC_DAPM_MIXER("RECMIXR Mixer", RT5631_PWR_MANAG_ADD2,
RT5631_PWR_RECMIXER_R_BIT, 0,
&rt5631_recmixr_mixer_controls[0],
ARRAY_SIZE(rt5631_recmixr_mixer_controls)),
/* Because of record duplication for L/R channel,
* L/R ADCs need power up at the same time */
SND_SOC_DAPM_MIXER("ADC Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
/* DMIC */
SND_SOC_DAPM_SUPPLY("DMIC Supply", RT5631_DIG_MIC_CTRL,
RT5631_DMIC_ENA_SHIFT, 0,
set_dmic_params, SND_SOC_DAPM_PRE_PMU),
/* ADC Data Srouce */
SND_SOC_DAPM_SUPPLY("Left ADC Select", RT5631_INT_ST_IRQ_CTRL_2,
RT5631_ADC_DATA_SEL_MIC1_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Right ADC Select", RT5631_INT_ST_IRQ_CTRL_2,
RT5631_ADC_DATA_SEL_MIC2_SHIFT, 0, NULL, 0),
/* ADCs */
SND_SOC_DAPM_ADC("Left ADC", "HIFI Capture",
RT5631_PWR_MANAG_ADD1, RT5631_PWR_ADC_L_CLK_BIT, 0),
SND_SOC_DAPM_ADC("Right ADC", "HIFI Capture",
RT5631_PWR_MANAG_ADD1, RT5631_PWR_ADC_R_CLK_BIT, 0),
/* DAC and ADC supply power */
SND_SOC_DAPM_SUPPLY("I2S", RT5631_PWR_MANAG_ADD1,
RT5631_PWR_MAIN_I2S_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC REF", RT5631_PWR_MANAG_ADD1,
RT5631_PWR_DAC_REF_BIT, 0, NULL, 0),
/* Output Side */
/* DACs */
SND_SOC_DAPM_DAC("Left DAC", "HIFI Playback",
RT5631_PWR_MANAG_ADD1, RT5631_PWR_DAC_L_CLK_BIT, 0),
SND_SOC_DAPM_DAC("Right DAC", "HIFI Playback",
RT5631_PWR_MANAG_ADD1, RT5631_PWR_DAC_R_CLK_BIT, 0),
SND_SOC_DAPM_DAC("Voice DAC", "Voice DAC Mono Playback",
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_PGA("Voice DAC Boost", SND_SOC_NOPM, 0, 0, NULL, 0),
/* DAC supply power */
SND_SOC_DAPM_SUPPLY("Left DAC To Mixer", RT5631_PWR_MANAG_ADD1,
RT5631_PWR_DAC_L_TO_MIXER_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Right DAC To Mixer", RT5631_PWR_MANAG_ADD1,
RT5631_PWR_DAC_R_TO_MIXER_BIT, 0, NULL, 0),
/* Left SPK Mixer */
SND_SOC_DAPM_MIXER("SPKMIXL Mixer", RT5631_PWR_MANAG_ADD2,
RT5631_PWR_SPKMIXER_L_BIT, 0,
&rt5631_spkmixl_mixer_controls[0],
ARRAY_SIZE(rt5631_spkmixl_mixer_controls)),
/* Left Out Mixer */
SND_SOC_DAPM_MIXER("OUTMIXL Mixer", RT5631_PWR_MANAG_ADD2,
RT5631_PWR_OUTMIXER_L_BIT, 0,
&rt5631_outmixl_mixer_controls[0],
ARRAY_SIZE(rt5631_outmixl_mixer_controls)),
/* Right Out Mixer */
SND_SOC_DAPM_MIXER("OUTMIXR Mixer", RT5631_PWR_MANAG_ADD2,
RT5631_PWR_OUTMIXER_R_BIT, 0,
&rt5631_outmixr_mixer_controls[0],
ARRAY_SIZE(rt5631_outmixr_mixer_controls)),
/* Right SPK Mixer */
SND_SOC_DAPM_MIXER("SPKMIXR Mixer", RT5631_PWR_MANAG_ADD2,
RT5631_PWR_SPKMIXER_R_BIT, 0,
&rt5631_spkmixr_mixer_controls[0],
ARRAY_SIZE(rt5631_spkmixr_mixer_controls)),
/* Volume Mux */
SND_SOC_DAPM_MUX("Left SPKVOL Mux", RT5631_PWR_MANAG_ADD4,
RT5631_PWR_SPK_L_VOL_BIT, 0,
&rt5631_spkvoll_mux_control),
SND_SOC_DAPM_MUX("Left HPVOL Mux", RT5631_PWR_MANAG_ADD4,
RT5631_PWR_HP_L_OUT_VOL_BIT, 0,
&rt5631_hpvoll_mux_control),
SND_SOC_DAPM_MUX("Left OUTVOL Mux", RT5631_PWR_MANAG_ADD4,
RT5631_PWR_LOUT_VOL_BIT, 0,
&rt5631_outvoll_mux_control),
SND_SOC_DAPM_MUX("Right OUTVOL Mux", RT5631_PWR_MANAG_ADD4,
RT5631_PWR_ROUT_VOL_BIT, 0,
&rt5631_outvolr_mux_control),
SND_SOC_DAPM_MUX("Right HPVOL Mux", RT5631_PWR_MANAG_ADD4,
RT5631_PWR_HP_R_OUT_VOL_BIT, 0,
&rt5631_hpvolr_mux_control),
SND_SOC_DAPM_MUX("Right SPKVOL Mux", RT5631_PWR_MANAG_ADD4,
RT5631_PWR_SPK_R_VOL_BIT, 0,
&rt5631_spkvolr_mux_control),
/* DAC To HP */
SND_SOC_DAPM_PGA_S("Left DAC_HP", 0, SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("Right DAC_HP", 0, SND_SOC_NOPM, 0, 0, NULL, 0),
/* HP Depop */
SND_SOC_DAPM_PGA_S("HP Depop", 1, SND_SOC_NOPM, 0, 0,
hp_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
/* AXO1 Mixer */
SND_SOC_DAPM_MIXER("AXO1MIX Mixer", RT5631_PWR_MANAG_ADD3,
RT5631_PWR_AXO1MIXER_BIT, 0,
&rt5631_AXO1MIX_mixer_controls[0],
ARRAY_SIZE(rt5631_AXO1MIX_mixer_controls)),
/* SPOL Mixer */
SND_SOC_DAPM_MIXER("SPOLMIX Mixer", SND_SOC_NOPM, 0, 0,
&rt5631_spolmix_mixer_controls[0],
ARRAY_SIZE(rt5631_spolmix_mixer_controls)),
/* MONO Mixer */
SND_SOC_DAPM_MIXER("MONOMIX Mixer", RT5631_PWR_MANAG_ADD3,
RT5631_PWR_MONOMIXER_BIT, 0,
&rt5631_monomix_mixer_controls[0],
ARRAY_SIZE(rt5631_monomix_mixer_controls)),
/* SPOR Mixer */
SND_SOC_DAPM_MIXER("SPORMIX Mixer", SND_SOC_NOPM, 0, 0,
&rt5631_spormix_mixer_controls[0],
ARRAY_SIZE(rt5631_spormix_mixer_controls)),
/* AXO2 Mixer */
SND_SOC_DAPM_MIXER("AXO2MIX Mixer", RT5631_PWR_MANAG_ADD3,
RT5631_PWR_AXO2MIXER_BIT, 0,
&rt5631_AXO2MIX_mixer_controls[0],
ARRAY_SIZE(rt5631_AXO2MIX_mixer_controls)),
/* Mux */
SND_SOC_DAPM_MUX("SPOL Mux", SND_SOC_NOPM, 0, 0,
&rt5631_spol_mux_control),
SND_SOC_DAPM_MUX("SPOR Mux", SND_SOC_NOPM, 0, 0,
&rt5631_spor_mux_control),
SND_SOC_DAPM_MUX("MONO Mux", SND_SOC_NOPM, 0, 0,
&rt5631_mono_mux_control),
SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0,
&rt5631_hpl_mux_control),
SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0,
&rt5631_hpr_mux_control),
/* AMP supply */
SND_SOC_DAPM_SUPPLY("MONO Depop", RT5631_PWR_MANAG_ADD3,
RT5631_PWR_MONO_DEPOP_DIS_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Class D", RT5631_PWR_MANAG_ADD1,
RT5631_PWR_CLASS_D_BIT, 0, NULL, 0),
/* Output Lines */
SND_SOC_DAPM_OUTPUT("AUXO1"),
SND_SOC_DAPM_OUTPUT("AUXO2"),
SND_SOC_DAPM_OUTPUT("SPOL"),
SND_SOC_DAPM_OUTPUT("SPOR"),
SND_SOC_DAPM_OUTPUT("HPOL"),
SND_SOC_DAPM_OUTPUT("HPOR"),
SND_SOC_DAPM_OUTPUT("MONO"),
};
static const struct snd_soc_dapm_route rt5631_dapm_routes[] = {
{"MIC1 Boost", NULL, "MIC1"},
{"MIC2 Boost", NULL, "MIC2"},
{"MONOIN_RXP Boost", NULL, "MONOIN_RXP"},
{"MONOIN_RXN Boost", NULL, "MONOIN_RXN"},
{"AXIL Boost", NULL, "AXIL"},
{"AXIR Boost", NULL, "AXIR"},
{"MONO_IN", NULL, "MONOIN_RXP Boost"},
{"MONO_IN", NULL, "MONOIN_RXN Boost"},
{"RECMIXL Mixer", "OUTMIXL Capture Switch", "OUTMIXL Mixer"},
{"RECMIXL Mixer", "MIC1_BST1 Capture Switch", "MIC1 Boost"},
{"RECMIXL Mixer", "AXILVOL Capture Switch", "AXIL Boost"},
{"RECMIXL Mixer", "MONOIN_RX Capture Switch", "MONO_IN"},
{"RECMIXR Mixer", "OUTMIXR Capture Switch", "OUTMIXR Mixer"},
{"RECMIXR Mixer", "MIC2_BST2 Capture Switch", "MIC2 Boost"},
{"RECMIXR Mixer", "AXIRVOL Capture Switch", "AXIR Boost"},
{"RECMIXR Mixer", "MONOIN_RX Capture Switch", "MONO_IN"},
{"ADC Mixer", NULL, "RECMIXL Mixer"},
{"ADC Mixer", NULL, "RECMIXR Mixer"},
{"Left ADC", NULL, "ADC Mixer"},
{"Left ADC", NULL, "Left ADC Select", check_adcl_select},
{"Left ADC", NULL, "PLL1", check_sysclk1_source},
{"Left ADC", NULL, "I2S"},
{"Left ADC", NULL, "DAC REF"},
{"Right ADC", NULL, "ADC Mixer"},
{"Right ADC", NULL, "Right ADC Select", check_adcr_select},
{"Right ADC", NULL, "PLL1", check_sysclk1_source},
{"Right ADC", NULL, "I2S"},
{"Right ADC", NULL, "DAC REF"},
{"DMIC", NULL, "DMIC Supply", check_dmic_used},
{"Left ADC", NULL, "DMIC"},
{"Right ADC", NULL, "DMIC"},
{"Left DAC", NULL, "PLL1", check_sysclk1_source},
{"Left DAC", NULL, "I2S"},
{"Left DAC", NULL, "DAC REF"},
{"Right DAC", NULL, "PLL1", check_sysclk1_source},
{"Right DAC", NULL, "I2S"},
{"Right DAC", NULL, "DAC REF"},
{"Voice DAC Boost", NULL, "Voice DAC"},
{"SPKMIXL Mixer", NULL, "Left DAC To Mixer", check_dacl_to_spkmixl},
{"SPKMIXL Mixer", "RECMIXL Playback Switch", "RECMIXL Mixer"},
{"SPKMIXL Mixer", "MIC1_P Playback Switch", "MIC1"},
{"SPKMIXL Mixer", "DACL Playback Switch", "Left DAC"},
{"SPKMIXL Mixer", "OUTMIXL Playback Switch", "OUTMIXL Mixer"},
{"SPKMIXR Mixer", NULL, "Right DAC To Mixer", check_dacr_to_spkmixr},
{"SPKMIXR Mixer", "OUTMIXR Playback Switch", "OUTMIXR Mixer"},
{"SPKMIXR Mixer", "DACR Playback Switch", "Right DAC"},
{"SPKMIXR Mixer", "MIC2_P Playback Switch", "MIC2"},
{"SPKMIXR Mixer", "RECMIXR Playback Switch", "RECMIXR Mixer"},
{"OUTMIXL Mixer", NULL, "Left DAC To Mixer", check_dacl_to_outmixl},
{"OUTMIXL Mixer", "RECMIXL Playback Switch", "RECMIXL Mixer"},
{"OUTMIXL Mixer", "RECMIXR Playback Switch", "RECMIXR Mixer"},
{"OUTMIXL Mixer", "DACL Playback Switch", "Left DAC"},
{"OUTMIXL Mixer", "MIC1_BST1 Playback Switch", "MIC1 Boost"},
{"OUTMIXL Mixer", "MIC2_BST2 Playback Switch", "MIC2 Boost"},
{"OUTMIXL Mixer", "MONOIN_RXP Playback Switch", "MONOIN_RXP Boost"},
{"OUTMIXL Mixer", "AXILVOL Playback Switch", "AXIL Boost"},
{"OUTMIXL Mixer", "AXIRVOL Playback Switch", "AXIR Boost"},
{"OUTMIXL Mixer", "VDAC Playback Switch", "Voice DAC Boost"},
{"OUTMIXR Mixer", NULL, "Right DAC To Mixer", check_dacr_to_outmixr},
{"OUTMIXR Mixer", "RECMIXL Playback Switch", "RECMIXL Mixer"},
{"OUTMIXR Mixer", "RECMIXR Playback Switch", "RECMIXR Mixer"},
{"OUTMIXR Mixer", "DACR Playback Switch", "Right DAC"},
{"OUTMIXR Mixer", "MIC1_BST1 Playback Switch", "MIC1 Boost"},
{"OUTMIXR Mixer", "MIC2_BST2 Playback Switch", "MIC2 Boost"},
{"OUTMIXR Mixer", "MONOIN_RXN Playback Switch", "MONOIN_RXN Boost"},
{"OUTMIXR Mixer", "AXILVOL Playback Switch", "AXIL Boost"},
{"OUTMIXR Mixer", "AXIRVOL Playback Switch", "AXIR Boost"},
{"OUTMIXR Mixer", "VDAC Playback Switch", "Voice DAC Boost"},
{"Left SPKVOL Mux", "SPKMIXL", "SPKMIXL Mixer"},
{"Left SPKVOL Mux", "Vmid", "Vmid"},
{"Left HPVOL Mux", "OUTMIXL", "OUTMIXL Mixer"},
{"Left HPVOL Mux", "Vmid", "Vmid"},
{"Left OUTVOL Mux", "OUTMIXL", "OUTMIXL Mixer"},
{"Left OUTVOL Mux", "Vmid", "Vmid"},
{"Right OUTVOL Mux", "OUTMIXR", "OUTMIXR Mixer"},
{"Right OUTVOL Mux", "Vmid", "Vmid"},
{"Right HPVOL Mux", "OUTMIXR", "OUTMIXR Mixer"},
{"Right HPVOL Mux", "Vmid", "Vmid"},
{"Right SPKVOL Mux", "SPKMIXR", "SPKMIXR Mixer"},
{"Right SPKVOL Mux", "Vmid", "Vmid"},
{"AXO1MIX Mixer", "MIC1_BST1 Playback Switch", "MIC1 Boost"},
{"AXO1MIX Mixer", "OUTVOLL Playback Switch", "Left OUTVOL Mux"},
{"AXO1MIX Mixer", "OUTVOLR Playback Switch", "Right OUTVOL Mux"},
{"AXO1MIX Mixer", "MIC2_BST2 Playback Switch", "MIC2 Boost"},
{"AXO2MIX Mixer", "MIC1_BST1 Playback Switch", "MIC1 Boost"},
{"AXO2MIX Mixer", "OUTVOLL Playback Switch", "Left OUTVOL Mux"},
{"AXO2MIX Mixer", "OUTVOLR Playback Switch", "Right OUTVOL Mux"},
{"AXO2MIX Mixer", "MIC2_BST2 Playback Switch", "MIC2 Boost"},
{"SPOLMIX Mixer", "SPKVOLL Playback Switch", "Left SPKVOL Mux"},
{"SPOLMIX Mixer", "SPKVOLR Playback Switch", "Right SPKVOL Mux"},
{"SPORMIX Mixer", "SPKVOLL Playback Switch", "Left SPKVOL Mux"},
{"SPORMIX Mixer", "SPKVOLR Playback Switch", "Right SPKVOL Mux"},
{"MONOMIX Mixer", "OUTVOLL Playback Switch", "Left OUTVOL Mux"},
{"MONOMIX Mixer", "OUTVOLR Playback Switch", "Right OUTVOL Mux"},
{"SPOL Mux", "SPOLMIX", "SPOLMIX Mixer"},
{"SPOL Mux", "MONOIN_RX", "MONO_IN"},
{"SPOL Mux", "VDAC", "Voice DAC Boost"},
{"SPOL Mux", "DACL", "Left DAC"},
{"SPOR Mux", "SPORMIX", "SPORMIX Mixer"},
{"SPOR Mux", "MONOIN_RX", "MONO_IN"},
{"SPOR Mux", "VDAC", "Voice DAC Boost"},
{"SPOR Mux", "DACR", "Right DAC"},
{"MONO Mux", "MONOMIX", "MONOMIX Mixer"},
{"MONO Mux", "MONOIN_RX", "MONO_IN"},
{"MONO Mux", "VDAC", "Voice DAC Boost"},
{"Right DAC_HP", NULL, "Right DAC"},
{"Left DAC_HP", NULL, "Left DAC"},
{"HPL Mux", "Left HPVOL", "Left HPVOL Mux"},
{"HPL Mux", "Left DAC", "Left DAC_HP"},
{"HPR Mux", "Right HPVOL", "Right HPVOL Mux"},
{"HPR Mux", "Right DAC", "Right DAC_HP"},
{"HP Depop", NULL, "HPL Mux"},
{"HP Depop", NULL, "HPR Mux"},
{"AUXO1", NULL, "AXO1MIX Mixer"},
{"AUXO2", NULL, "AXO2MIX Mixer"},
{"SPOL", NULL, "Class D"},
{"SPOL", NULL, "SPOL Mux"},
{"SPOR", NULL, "Class D"},
{"SPOR", NULL, "SPOR Mux"},
{"HPOL", NULL, "HP Depop"},
{"HPOR", NULL, "HP Depop"},
{"MONO", NULL, "MONO Depop"},
{"MONO", NULL, "MONO Mux"},
};
struct coeff_clk_div {
u32 mclk;
u32 bclk;
u32 rate;
u16 reg_val;
};
/* PLL divisors */
struct pll_div {
u32 pll_in;
u32 pll_out;
u16 reg_val;
};
static const struct pll_div codec_master_pll_div[] = {
{2048000, 8192000, 0x0ea0},
{3686400, 8192000, 0x4e27},
{12000000, 8192000, 0x456b},
{13000000, 8192000, 0x495f},
{13100000, 8192000, 0x0320},
{2048000, 11289600, 0xf637},
{3686400, 11289600, 0x2f22},
{12000000, 11289600, 0x3e2f},
{13000000, 11289600, 0x4d5b},
{13100000, 11289600, 0x363b},
{2048000, 16384000, 0x1ea0},
{3686400, 16384000, 0x9e27},
{12000000, 16384000, 0x452b},
{13000000, 16384000, 0x542f},
{13100000, 16384000, 0x03a0},
{2048000, 16934400, 0xe625},
{3686400, 16934400, 0x9126},
{12000000, 16934400, 0x4d2c},
{13000000, 16934400, 0x742f},
{13100000, 16934400, 0x3c27},
{2048000, 22579200, 0x2aa0},
{3686400, 22579200, 0x2f20},
{12000000, 22579200, 0x7e2f},
{13000000, 22579200, 0x742f},
{13100000, 22579200, 0x3c27},
{2048000, 24576000, 0x2ea0},
{3686400, 24576000, 0xee27},
{12000000, 24576000, 0x2915},
{13000000, 24576000, 0x772e},
{13100000, 24576000, 0x0d20},
{26000000, 24576000, 0x2027},
{26000000, 22579200, 0x392f},
{24576000, 22579200, 0x0921},
{24576000, 24576000, 0x02a0},
};
static const struct pll_div codec_slave_pll_div[] = {
{256000, 2048000, 0x46f0},
{256000, 4096000, 0x3ea0},
{352800, 5644800, 0x3ea0},
{512000, 8192000, 0x3ea0},
{1024000, 8192000, 0x46f0},
{705600, 11289600, 0x3ea0},
{1024000, 16384000, 0x3ea0},
{1411200, 22579200, 0x3ea0},
{1536000, 24576000, 0x3ea0},
{2048000, 16384000, 0x1ea0},
{2822400, 22579200, 0x1ea0},
{2822400, 45158400, 0x5ec0},
{5644800, 45158400, 0x46f0},
{3072000, 24576000, 0x1ea0},
{3072000, 49152000, 0x5ec0},
{6144000, 49152000, 0x46f0},
{705600, 11289600, 0x3ea0},
{705600, 8467200, 0x3ab0},
{24576000, 24576000, 0x02a0},
{1411200, 11289600, 0x1690},
{2822400, 11289600, 0x0a90},
{1536000, 12288000, 0x1690},
{3072000, 12288000, 0x0a90},
};
static const struct coeff_clk_div coeff_div[] = {
/* sysclk is 256fs */
{2048000, 8000 * 32, 8000, 0x1000},
{2048000, 8000 * 64, 8000, 0x0000},
{2822400, 11025 * 32, 11025, 0x1000},
{2822400, 11025 * 64, 11025, 0x0000},
{4096000, 16000 * 32, 16000, 0x1000},
{4096000, 16000 * 64, 16000, 0x0000},
{5644800, 22050 * 32, 22050, 0x1000},
{5644800, 22050 * 64, 22050, 0x0000},
{8192000, 32000 * 32, 32000, 0x1000},
{8192000, 32000 * 64, 32000, 0x0000},
{11289600, 44100 * 32, 44100, 0x1000},
{11289600, 44100 * 64, 44100, 0x0000},
{12288000, 48000 * 32, 48000, 0x1000},
{12288000, 48000 * 64, 48000, 0x0000},
{22579200, 88200 * 32, 88200, 0x1000},
{22579200, 88200 * 64, 88200, 0x0000},
{24576000, 96000 * 32, 96000, 0x1000},
{24576000, 96000 * 64, 96000, 0x0000},
/* sysclk is 512fs */
{4096000, 8000 * 32, 8000, 0x3000},
{4096000, 8000 * 64, 8000, 0x2000},
{5644800, 11025 * 32, 11025, 0x3000},
{5644800, 11025 * 64, 11025, 0x2000},
{8192000, 16000 * 32, 16000, 0x3000},
{8192000, 16000 * 64, 16000, 0x2000},
{11289600, 22050 * 32, 22050, 0x3000},
{11289600, 22050 * 64, 22050, 0x2000},
{16384000, 32000 * 32, 32000, 0x3000},
{16384000, 32000 * 64, 32000, 0x2000},
{22579200, 44100 * 32, 44100, 0x3000},
{22579200, 44100 * 64, 44100, 0x2000},
{24576000, 48000 * 32, 48000, 0x3000},
{24576000, 48000 * 64, 48000, 0x2000},
{45158400, 88200 * 32, 88200, 0x3000},
{45158400, 88200 * 64, 88200, 0x2000},
{49152000, 96000 * 32, 96000, 0x3000},
{49152000, 96000 * 64, 96000, 0x2000},
/* sysclk is 24.576Mhz or 22.5792Mhz */
{24576000, 8000 * 32, 8000, 0x7080},
{24576000, 8000 * 64, 8000, 0x6080},
{24576000, 16000 * 32, 16000, 0x5080},
{24576000, 16000 * 64, 16000, 0x4080},
{24576000, 24000 * 32, 24000, 0x5000},
{24576000, 24000 * 64, 24000, 0x4000},
{24576000, 32000 * 32, 32000, 0x3080},
{24576000, 32000 * 64, 32000, 0x2080},
{22579200, 11025 * 32, 11025, 0x7000},
{22579200, 11025 * 64, 11025, 0x6000},
{22579200, 22050 * 32, 22050, 0x5000},
{22579200, 22050 * 64, 22050, 0x4000},
};
static int get_coeff(int mclk, int rate, int timesofbclk)
{
int i;
for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
if (coeff_div[i].mclk == mclk && coeff_div[i].rate == rate &&
(coeff_div[i].bclk / coeff_div[i].rate) == timesofbclk)
return i;
}
return -EINVAL;
}
static int rt5631_hifi_pcm_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt5631_priv *rt5631 = snd_soc_component_get_drvdata(component);
int timesofbclk = 32, coeff;
unsigned int iface = 0;
dev_dbg(component->dev, "enter %s\n", __func__);
rt5631->bclk_rate = snd_soc_params_to_bclk(params);
if (rt5631->bclk_rate < 0) {
dev_err(component->dev, "Fail to get BCLK rate\n");
return rt5631->bclk_rate;
}
rt5631->rx_rate = params_rate(params);
if (rt5631->master)
coeff = get_coeff(rt5631->sysclk, rt5631->rx_rate,
rt5631->bclk_rate / rt5631->rx_rate);
else
coeff = get_coeff(rt5631->sysclk, rt5631->rx_rate,
timesofbclk);
if (coeff < 0) {
dev_err(component->dev, "Fail to get coeff\n");
return coeff;
}
switch (params_width(params)) {
case 16:
break;
case 20:
iface |= RT5631_SDP_I2S_DL_20;
break;
case 24:
iface |= RT5631_SDP_I2S_DL_24;
break;
case 8:
iface |= RT5631_SDP_I2S_DL_8;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, RT5631_SDP_CTRL,
RT5631_SDP_I2S_DL_MASK, iface);
snd_soc_component_write(component, RT5631_STEREO_AD_DA_CLK_CTRL,
coeff_div[coeff].reg_val);
return 0;
}
static int rt5631_hifi_codec_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct rt5631_priv *rt5631 = snd_soc_component_get_drvdata(component);
unsigned int iface = 0;
dev_dbg(component->dev, "enter %s\n", __func__);
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
rt5631->master = 1;
break;
case SND_SOC_DAIFMT_CBS_CFS:
iface |= RT5631_SDP_MODE_SEL_SLAVE;
rt5631->master = 0;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_LEFT_J:
iface |= RT5631_SDP_I2S_DF_LEFT;
break;
case SND_SOC_DAIFMT_DSP_A:
iface |= RT5631_SDP_I2S_DF_PCM_A;
break;
case SND_SOC_DAIFMT_DSP_B:
iface |= RT5631_SDP_I2S_DF_PCM_B;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
iface |= RT5631_SDP_I2S_BCLK_POL_CTRL;
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, RT5631_SDP_CTRL, iface);
return 0;
}
static int rt5631_hifi_codec_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct rt5631_priv *rt5631 = snd_soc_component_get_drvdata(component);
dev_dbg(component->dev, "enter %s, syclk=%d\n", __func__, freq);
if ((freq >= (256 * 8000)) && (freq <= (512 * 96000))) {
rt5631->sysclk = freq;
return 0;
}
return -EINVAL;
}
static int rt5631_codec_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
int source, unsigned int freq_in, unsigned int freq_out)
{
struct snd_soc_component *component = codec_dai->component;
struct rt5631_priv *rt5631 = snd_soc_component_get_drvdata(component);
int i, ret = -EINVAL;
dev_dbg(component->dev, "enter %s\n", __func__);
if (!freq_in || !freq_out) {
dev_dbg(component->dev, "PLL disabled\n");
snd_soc_component_update_bits(component, RT5631_GLOBAL_CLK_CTRL,
RT5631_SYSCLK_SOUR_SEL_MASK,
RT5631_SYSCLK_SOUR_SEL_MCLK);
return 0;
}
if (rt5631->master) {
for (i = 0; i < ARRAY_SIZE(codec_master_pll_div); i++)
if (freq_in == codec_master_pll_div[i].pll_in &&
freq_out == codec_master_pll_div[i].pll_out) {
dev_info(component->dev,
"change PLL in master mode\n");
snd_soc_component_write(component, RT5631_PLL_CTRL,
codec_master_pll_div[i].reg_val);
schedule_timeout_uninterruptible(
msecs_to_jiffies(20));
snd_soc_component_update_bits(component,
RT5631_GLOBAL_CLK_CTRL,
RT5631_SYSCLK_SOUR_SEL_MASK |
RT5631_PLLCLK_SOUR_SEL_MASK,
RT5631_SYSCLK_SOUR_SEL_PLL |
RT5631_PLLCLK_SOUR_SEL_MCLK);
ret = 0;
break;
}
} else {
for (i = 0; i < ARRAY_SIZE(codec_slave_pll_div); i++)
if (freq_in == codec_slave_pll_div[i].pll_in &&
freq_out == codec_slave_pll_div[i].pll_out) {
dev_info(component->dev,
"change PLL in slave mode\n");
snd_soc_component_write(component, RT5631_PLL_CTRL,
codec_slave_pll_div[i].reg_val);
schedule_timeout_uninterruptible(
msecs_to_jiffies(20));
snd_soc_component_update_bits(component,
RT5631_GLOBAL_CLK_CTRL,
RT5631_SYSCLK_SOUR_SEL_MASK |
RT5631_PLLCLK_SOUR_SEL_MASK,
RT5631_SYSCLK_SOUR_SEL_PLL |
RT5631_PLLCLK_SOUR_SEL_BCLK);
ret = 0;
break;
}
}
return ret;
}
static int rt5631_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct rt5631_priv *rt5631 = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_ON:
case SND_SOC_BIAS_PREPARE:
snd_soc_component_update_bits(component, RT5631_PWR_MANAG_ADD2,
RT5631_PWR_MICBIAS1_VOL | RT5631_PWR_MICBIAS2_VOL,
RT5631_PWR_MICBIAS1_VOL | RT5631_PWR_MICBIAS2_VOL);
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
snd_soc_component_update_bits(component, RT5631_PWR_MANAG_ADD3,
RT5631_PWR_VREF | RT5631_PWR_MAIN_BIAS,
RT5631_PWR_VREF | RT5631_PWR_MAIN_BIAS);
msleep(80);
snd_soc_component_update_bits(component, RT5631_PWR_MANAG_ADD3,
RT5631_PWR_FAST_VREF_CTRL,
RT5631_PWR_FAST_VREF_CTRL);
regcache_cache_only(rt5631->regmap, false);
regcache_sync(rt5631->regmap);
}
break;
case SND_SOC_BIAS_OFF:
snd_soc_component_write(component, RT5631_PWR_MANAG_ADD1, 0x0000);
snd_soc_component_write(component, RT5631_PWR_MANAG_ADD2, 0x0000);
snd_soc_component_write(component, RT5631_PWR_MANAG_ADD3, 0x0000);
snd_soc_component_write(component, RT5631_PWR_MANAG_ADD4, 0x0000);
break;
default:
break;
}
return 0;
}
static int rt5631_probe(struct snd_soc_component *component)
{
struct rt5631_priv *rt5631 = snd_soc_component_get_drvdata(component);
unsigned int val;
val = rt5631_read_index(component, RT5631_ADDA_MIXER_INTL_REG3);
if (val & 0x0002)
rt5631->codec_version = 1;
else
rt5631->codec_version = 0;
rt5631_reset(component);
snd_soc_component_update_bits(component, RT5631_PWR_MANAG_ADD3,
RT5631_PWR_VREF | RT5631_PWR_MAIN_BIAS,
RT5631_PWR_VREF | RT5631_PWR_MAIN_BIAS);
msleep(80);
snd_soc_component_update_bits(component, RT5631_PWR_MANAG_ADD3,
RT5631_PWR_FAST_VREF_CTRL, RT5631_PWR_FAST_VREF_CTRL);
/* enable HP zero cross */
snd_soc_component_write(component, RT5631_INT_ST_IRQ_CTRL_2, 0x0f18);
/* power off ClassD auto Recovery */
if (rt5631->codec_version)
snd_soc_component_update_bits(component, RT5631_INT_ST_IRQ_CTRL_2,
0x2000, 0x2000);
else
snd_soc_component_update_bits(component, RT5631_INT_ST_IRQ_CTRL_2,
0x2000, 0);
/* DMIC */
if (rt5631->dmic_used_flag) {
snd_soc_component_update_bits(component, RT5631_GPIO_CTRL,
RT5631_GPIO_PIN_FUN_SEL_MASK |
RT5631_GPIO_DMIC_FUN_SEL_MASK,
RT5631_GPIO_PIN_FUN_SEL_GPIO_DIMC |
RT5631_GPIO_DMIC_FUN_SEL_DIMC);
snd_soc_component_update_bits(component, RT5631_DIG_MIC_CTRL,
RT5631_DMIC_L_CH_LATCH_MASK |
RT5631_DMIC_R_CH_LATCH_MASK,
RT5631_DMIC_L_CH_LATCH_FALLING |
RT5631_DMIC_R_CH_LATCH_RISING);
}
snd_soc_component_init_bias_level(component, SND_SOC_BIAS_STANDBY);
return 0;
}
#define RT5631_STEREO_RATES SNDRV_PCM_RATE_8000_96000
#define RT5631_FORMAT (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S8)
static const struct snd_soc_dai_ops rt5631_ops = {
.hw_params = rt5631_hifi_pcm_params,
.set_fmt = rt5631_hifi_codec_set_dai_fmt,
.set_sysclk = rt5631_hifi_codec_set_dai_sysclk,
.set_pll = rt5631_codec_set_dai_pll,
};
static struct snd_soc_dai_driver rt5631_dai[] = {
{
.name = "rt5631-hifi",
.id = 1,
.playback = {
.stream_name = "HIFI Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT5631_STEREO_RATES,
.formats = RT5631_FORMAT,
},
.capture = {
.stream_name = "HIFI Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT5631_STEREO_RATES,
.formats = RT5631_FORMAT,
},
.ops = &rt5631_ops,
},
};
static const struct snd_soc_component_driver soc_component_dev_rt5631 = {
.probe = rt5631_probe,
.set_bias_level = rt5631_set_bias_level,
.controls = rt5631_snd_controls,
.num_controls = ARRAY_SIZE(rt5631_snd_controls),
.dapm_widgets = rt5631_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt5631_dapm_widgets),
.dapm_routes = rt5631_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(rt5631_dapm_routes),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct i2c_device_id rt5631_i2c_id[] = {
{ "rt5631", 0 },
{ "alc5631", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, rt5631_i2c_id);
#ifdef CONFIG_OF
static const struct of_device_id rt5631_i2c_dt_ids[] = {
{ .compatible = "realtek,rt5631"},
{ .compatible = "realtek,alc5631"},
{ }
};
MODULE_DEVICE_TABLE(of, rt5631_i2c_dt_ids);
#endif
static const struct regmap_config rt5631_regmap_config = {
.reg_bits = 8,
.val_bits = 16,
.readable_reg = rt5631_readable_register,
.volatile_reg = rt5631_volatile_register,
.max_register = RT5631_VENDOR_ID2,
.reg_defaults = rt5631_reg,
.num_reg_defaults = ARRAY_SIZE(rt5631_reg),
.cache_type = REGCACHE_MAPLE,
.use_single_read = true,
.use_single_write = true,
};
static int rt5631_i2c_probe(struct i2c_client *i2c)
{
struct rt5631_priv *rt5631;
int ret;
rt5631 = devm_kzalloc(&i2c->dev, sizeof(struct rt5631_priv),
GFP_KERNEL);
if (NULL == rt5631)
return -ENOMEM;
i2c_set_clientdata(i2c, rt5631);
rt5631->regmap = devm_regmap_init_i2c(i2c, &rt5631_regmap_config);
if (IS_ERR(rt5631->regmap))
return PTR_ERR(rt5631->regmap);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_rt5631,
rt5631_dai, ARRAY_SIZE(rt5631_dai));
return ret;
}
static void rt5631_i2c_remove(struct i2c_client *client)
{}
static struct i2c_driver rt5631_i2c_driver = {
.driver = {
.name = "rt5631",
.of_match_table = of_match_ptr(rt5631_i2c_dt_ids),
},
.probe = rt5631_i2c_probe,
.remove = rt5631_i2c_remove,
.id_table = rt5631_i2c_id,
};
module_i2c_driver(rt5631_i2c_driver);
MODULE_DESCRIPTION("ASoC RT5631 driver");
MODULE_AUTHOR("flove <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/rt5631.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8900.c -- WM8900 ALSA Soc Audio driver
*
* Copyright 2007, 2008 Wolfson Microelectronics PLC.
*
* Author: Mark Brown <[email protected]>
*
* TODO:
* - Tristating.
* - TDM.
* - Jack detect.
* - FLL source configuration, currently only MCLK is supported.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "wm8900.h"
/* WM8900 register space */
#define WM8900_REG_RESET 0x0
#define WM8900_REG_ID 0x0
#define WM8900_REG_POWER1 0x1
#define WM8900_REG_POWER2 0x2
#define WM8900_REG_POWER3 0x3
#define WM8900_REG_AUDIO1 0x4
#define WM8900_REG_AUDIO2 0x5
#define WM8900_REG_CLOCKING1 0x6
#define WM8900_REG_CLOCKING2 0x7
#define WM8900_REG_AUDIO3 0x8
#define WM8900_REG_AUDIO4 0x9
#define WM8900_REG_DACCTRL 0xa
#define WM8900_REG_LDAC_DV 0xb
#define WM8900_REG_RDAC_DV 0xc
#define WM8900_REG_SIDETONE 0xd
#define WM8900_REG_ADCCTRL 0xe
#define WM8900_REG_LADC_DV 0xf
#define WM8900_REG_RADC_DV 0x10
#define WM8900_REG_GPIO 0x12
#define WM8900_REG_INCTL 0x15
#define WM8900_REG_LINVOL 0x16
#define WM8900_REG_RINVOL 0x17
#define WM8900_REG_INBOOSTMIX1 0x18
#define WM8900_REG_INBOOSTMIX2 0x19
#define WM8900_REG_ADCPATH 0x1a
#define WM8900_REG_AUXBOOST 0x1b
#define WM8900_REG_ADDCTL 0x1e
#define WM8900_REG_FLLCTL1 0x24
#define WM8900_REG_FLLCTL2 0x25
#define WM8900_REG_FLLCTL3 0x26
#define WM8900_REG_FLLCTL4 0x27
#define WM8900_REG_FLLCTL5 0x28
#define WM8900_REG_FLLCTL6 0x29
#define WM8900_REG_LOUTMIXCTL1 0x2c
#define WM8900_REG_ROUTMIXCTL1 0x2d
#define WM8900_REG_BYPASS1 0x2e
#define WM8900_REG_BYPASS2 0x2f
#define WM8900_REG_AUXOUT_CTL 0x30
#define WM8900_REG_LOUT1CTL 0x33
#define WM8900_REG_ROUT1CTL 0x34
#define WM8900_REG_LOUT2CTL 0x35
#define WM8900_REG_ROUT2CTL 0x36
#define WM8900_REG_HPCTL1 0x3a
#define WM8900_REG_OUTBIASCTL 0x73
#define WM8900_MAXREG 0x80
#define WM8900_REG_ADDCTL_OUT1_DIS 0x80
#define WM8900_REG_ADDCTL_OUT2_DIS 0x40
#define WM8900_REG_ADDCTL_VMID_DIS 0x20
#define WM8900_REG_ADDCTL_BIAS_SRC 0x10
#define WM8900_REG_ADDCTL_VMID_SOFTST 0x04
#define WM8900_REG_ADDCTL_TEMP_SD 0x02
#define WM8900_REG_GPIO_TEMP_ENA 0x2
#define WM8900_REG_POWER1_STARTUP_BIAS_ENA 0x0100
#define WM8900_REG_POWER1_BIAS_ENA 0x0008
#define WM8900_REG_POWER1_VMID_BUF_ENA 0x0004
#define WM8900_REG_POWER1_FLL_ENA 0x0040
#define WM8900_REG_POWER2_SYSCLK_ENA 0x8000
#define WM8900_REG_POWER2_ADCL_ENA 0x0002
#define WM8900_REG_POWER2_ADCR_ENA 0x0001
#define WM8900_REG_POWER3_DACL_ENA 0x0002
#define WM8900_REG_POWER3_DACR_ENA 0x0001
#define WM8900_REG_AUDIO1_AIF_FMT_MASK 0x0018
#define WM8900_REG_AUDIO1_LRCLK_INV 0x0080
#define WM8900_REG_AUDIO1_BCLK_INV 0x0100
#define WM8900_REG_CLOCKING1_BCLK_DIR 0x1
#define WM8900_REG_CLOCKING1_MCLK_SRC 0x100
#define WM8900_REG_CLOCKING1_BCLK_MASK 0x01e
#define WM8900_REG_CLOCKING1_OPCLK_MASK 0x7000
#define WM8900_REG_CLOCKING2_ADC_CLKDIV 0xe0
#define WM8900_REG_CLOCKING2_DAC_CLKDIV 0x1c
#define WM8900_REG_DACCTRL_MUTE 0x004
#define WM8900_REG_DACCTRL_DAC_SB_FILT 0x100
#define WM8900_REG_DACCTRL_AIF_LRCLKRATE 0x400
#define WM8900_REG_AUDIO3_ADCLRC_DIR 0x0800
#define WM8900_REG_AUDIO4_DACLRC_DIR 0x0800
#define WM8900_REG_FLLCTL1_OSC_ENA 0x100
#define WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF 0x100
#define WM8900_REG_HPCTL1_HP_IPSTAGE_ENA 0x80
#define WM8900_REG_HPCTL1_HP_OPSTAGE_ENA 0x40
#define WM8900_REG_HPCTL1_HP_CLAMP_IP 0x20
#define WM8900_REG_HPCTL1_HP_CLAMP_OP 0x10
#define WM8900_REG_HPCTL1_HP_SHORT 0x08
#define WM8900_REG_HPCTL1_HP_SHORT2 0x04
#define WM8900_LRC_MASK 0x03ff
struct wm8900_priv {
struct regmap *regmap;
u32 fll_in; /* FLL input frequency */
u32 fll_out; /* FLL output frequency */
};
/*
* wm8900 register cache. We can't read the entire register space and we
* have slow control buses so we cache the registers.
*/
static const struct reg_default wm8900_reg_defaults[] = {
{ 1, 0x0000 },
{ 2, 0xc000 },
{ 3, 0x0000 },
{ 4, 0x4050 },
{ 5, 0x4000 },
{ 6, 0x0008 },
{ 7, 0x0000 },
{ 8, 0x0040 },
{ 9, 0x0040 },
{ 10, 0x1004 },
{ 11, 0x00c0 },
{ 12, 0x00c0 },
{ 13, 0x0000 },
{ 14, 0x0100 },
{ 15, 0x00c0 },
{ 16, 0x00c0 },
{ 17, 0x0000 },
{ 18, 0xb001 },
{ 19, 0x0000 },
{ 20, 0x0000 },
{ 21, 0x0044 },
{ 22, 0x004c },
{ 23, 0x004c },
{ 24, 0x0044 },
{ 25, 0x0044 },
{ 26, 0x0000 },
{ 27, 0x0044 },
{ 28, 0x0000 },
{ 29, 0x0000 },
{ 30, 0x0002 },
{ 31, 0x0000 },
{ 32, 0x0000 },
{ 33, 0x0000 },
{ 34, 0x0000 },
{ 35, 0x0000 },
{ 36, 0x0008 },
{ 37, 0x0000 },
{ 38, 0x0000 },
{ 39, 0x0008 },
{ 40, 0x0097 },
{ 41, 0x0100 },
{ 42, 0x0000 },
{ 43, 0x0000 },
{ 44, 0x0050 },
{ 45, 0x0050 },
{ 46, 0x0055 },
{ 47, 0x0055 },
{ 48, 0x0055 },
{ 49, 0x0000 },
{ 50, 0x0000 },
{ 51, 0x0079 },
{ 52, 0x0079 },
{ 53, 0x0079 },
{ 54, 0x0079 },
{ 55, 0x0000 },
};
static bool wm8900_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8900_REG_ID:
return true;
default:
return false;
}
}
static void wm8900_reset(struct snd_soc_component *component)
{
snd_soc_component_write(component, WM8900_REG_RESET, 0);
}
static int wm8900_hp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
u16 hpctl1 = snd_soc_component_read(component, WM8900_REG_HPCTL1);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* Clamp headphone outputs */
hpctl1 = WM8900_REG_HPCTL1_HP_CLAMP_IP |
WM8900_REG_HPCTL1_HP_CLAMP_OP;
snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
break;
case SND_SOC_DAPM_POST_PMU:
/* Enable the input stage */
hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_IP;
hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT |
WM8900_REG_HPCTL1_HP_SHORT2 |
WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
msleep(400);
/* Enable the output stage */
hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_OP;
hpctl1 |= WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
/* Remove the shorts */
hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT2;
snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT;
snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
break;
case SND_SOC_DAPM_PRE_PMD:
/* Short the output */
hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT;
snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
/* Disable the output stage */
hpctl1 &= ~WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
/* Clamp the outputs and power down input */
hpctl1 |= WM8900_REG_HPCTL1_HP_CLAMP_IP |
WM8900_REG_HPCTL1_HP_CLAMP_OP;
hpctl1 &= ~WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
break;
case SND_SOC_DAPM_POST_PMD:
/* Disable everything */
snd_soc_component_write(component, WM8900_REG_HPCTL1, 0);
break;
default:
WARN(1, "Invalid event %d\n", event);
break;
}
return 0;
}
static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 100, 0);
static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 0);
static const DECLARE_TLV_DB_SCALE(in_boost_tlv, -1200, 600, 0);
static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1200, 100, 0);
static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
static const DECLARE_TLV_DB_SCALE(adc_svol_tlv, -3600, 300, 0);
static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);
static const char *mic_bias_level_txt[] = { "0.9*AVDD", "0.65*AVDD" };
static SOC_ENUM_SINGLE_DECL(mic_bias_level,
WM8900_REG_INCTL, 8, mic_bias_level_txt);
static const char *dac_mute_rate_txt[] = { "Fast", "Slow" };
static SOC_ENUM_SINGLE_DECL(dac_mute_rate,
WM8900_REG_DACCTRL, 7, dac_mute_rate_txt);
static const char *dac_deemphasis_txt[] = {
"Disabled", "32kHz", "44.1kHz", "48kHz"
};
static SOC_ENUM_SINGLE_DECL(dac_deemphasis,
WM8900_REG_DACCTRL, 4, dac_deemphasis_txt);
static const char *adc_hpf_cut_txt[] = {
"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"
};
static SOC_ENUM_SINGLE_DECL(adc_hpf_cut,
WM8900_REG_ADCCTRL, 5, adc_hpf_cut_txt);
static const char *lr_txt[] = {
"Left", "Right"
};
static SOC_ENUM_SINGLE_DECL(aifl_src,
WM8900_REG_AUDIO1, 15, lr_txt);
static SOC_ENUM_SINGLE_DECL(aifr_src,
WM8900_REG_AUDIO1, 14, lr_txt);
static SOC_ENUM_SINGLE_DECL(dacl_src,
WM8900_REG_AUDIO2, 15, lr_txt);
static SOC_ENUM_SINGLE_DECL(dacr_src,
WM8900_REG_AUDIO2, 14, lr_txt);
static const char *sidetone_txt[] = {
"Disabled", "Left ADC", "Right ADC"
};
static SOC_ENUM_SINGLE_DECL(dacl_sidetone,
WM8900_REG_SIDETONE, 2, sidetone_txt);
static SOC_ENUM_SINGLE_DECL(dacr_sidetone,
WM8900_REG_SIDETONE, 0, sidetone_txt);
static const struct snd_kcontrol_new wm8900_snd_controls[] = {
SOC_ENUM("Mic Bias Level", mic_bias_level),
SOC_SINGLE_TLV("Left Input PGA Volume", WM8900_REG_LINVOL, 0, 31, 0,
in_pga_tlv),
SOC_SINGLE("Left Input PGA Switch", WM8900_REG_LINVOL, 6, 1, 1),
SOC_SINGLE("Left Input PGA ZC Switch", WM8900_REG_LINVOL, 7, 1, 0),
SOC_SINGLE_TLV("Right Input PGA Volume", WM8900_REG_RINVOL, 0, 31, 0,
in_pga_tlv),
SOC_SINGLE("Right Input PGA Switch", WM8900_REG_RINVOL, 6, 1, 1),
SOC_SINGLE("Right Input PGA ZC Switch", WM8900_REG_RINVOL, 7, 1, 0),
SOC_SINGLE("DAC Soft Mute Switch", WM8900_REG_DACCTRL, 6, 1, 1),
SOC_ENUM("DAC Mute Rate", dac_mute_rate),
SOC_SINGLE("DAC Mono Switch", WM8900_REG_DACCTRL, 9, 1, 0),
SOC_ENUM("DAC Deemphasis", dac_deemphasis),
SOC_SINGLE("DAC Sigma-Delta Modulator Clock Switch", WM8900_REG_DACCTRL,
12, 1, 0),
SOC_SINGLE("ADC HPF Switch", WM8900_REG_ADCCTRL, 8, 1, 0),
SOC_ENUM("ADC HPF Cut-Off", adc_hpf_cut),
SOC_DOUBLE("ADC Invert Switch", WM8900_REG_ADCCTRL, 1, 0, 1, 0),
SOC_SINGLE_TLV("Left ADC Sidetone Volume", WM8900_REG_SIDETONE, 9, 12, 0,
adc_svol_tlv),
SOC_SINGLE_TLV("Right ADC Sidetone Volume", WM8900_REG_SIDETONE, 5, 12, 0,
adc_svol_tlv),
SOC_ENUM("Left Digital Audio Source", aifl_src),
SOC_ENUM("Right Digital Audio Source", aifr_src),
SOC_SINGLE_TLV("DAC Input Boost Volume", WM8900_REG_AUDIO2, 10, 4, 0,
dac_boost_tlv),
SOC_ENUM("Left DAC Source", dacl_src),
SOC_ENUM("Right DAC Source", dacr_src),
SOC_ENUM("Left DAC Sidetone", dacl_sidetone),
SOC_ENUM("Right DAC Sidetone", dacr_sidetone),
SOC_DOUBLE("DAC Invert Switch", WM8900_REG_DACCTRL, 1, 0, 1, 0),
SOC_DOUBLE_R_TLV("Digital Playback Volume",
WM8900_REG_LDAC_DV, WM8900_REG_RDAC_DV,
1, 96, 0, dac_tlv),
SOC_DOUBLE_R_TLV("Digital Capture Volume",
WM8900_REG_LADC_DV, WM8900_REG_RADC_DV, 1, 119, 0, adc_tlv),
SOC_SINGLE_TLV("LINPUT3 Bypass Volume", WM8900_REG_LOUTMIXCTL1, 4, 7, 0,
out_mix_tlv),
SOC_SINGLE_TLV("RINPUT3 Bypass Volume", WM8900_REG_ROUTMIXCTL1, 4, 7, 0,
out_mix_tlv),
SOC_SINGLE_TLV("Left AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 4, 7, 0,
out_mix_tlv),
SOC_SINGLE_TLV("Right AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 0, 7, 0,
out_mix_tlv),
SOC_SINGLE_TLV("LeftIn to RightOut Mixer Volume", WM8900_REG_BYPASS1, 0, 7, 0,
out_mix_tlv),
SOC_SINGLE_TLV("LeftIn to LeftOut Mixer Volume", WM8900_REG_BYPASS1, 4, 7, 0,
out_mix_tlv),
SOC_SINGLE_TLV("RightIn to LeftOut Mixer Volume", WM8900_REG_BYPASS2, 0, 7, 0,
out_mix_tlv),
SOC_SINGLE_TLV("RightIn to RightOut Mixer Volume", WM8900_REG_BYPASS2, 4, 7, 0,
out_mix_tlv),
SOC_SINGLE_TLV("IN2L Boost Volume", WM8900_REG_INBOOSTMIX1, 0, 3, 0,
in_boost_tlv),
SOC_SINGLE_TLV("IN3L Boost Volume", WM8900_REG_INBOOSTMIX1, 4, 3, 0,
in_boost_tlv),
SOC_SINGLE_TLV("IN2R Boost Volume", WM8900_REG_INBOOSTMIX2, 0, 3, 0,
in_boost_tlv),
SOC_SINGLE_TLV("IN3R Boost Volume", WM8900_REG_INBOOSTMIX2, 4, 3, 0,
in_boost_tlv),
SOC_SINGLE_TLV("Left AUX Boost Volume", WM8900_REG_AUXBOOST, 4, 3, 0,
in_boost_tlv),
SOC_SINGLE_TLV("Right AUX Boost Volume", WM8900_REG_AUXBOOST, 0, 3, 0,
in_boost_tlv),
SOC_DOUBLE_R_TLV("LINEOUT1 Volume", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
0, 63, 0, out_pga_tlv),
SOC_DOUBLE_R("LINEOUT1 Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
6, 1, 1),
SOC_DOUBLE_R("LINEOUT1 ZC Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
7, 1, 0),
SOC_DOUBLE_R_TLV("LINEOUT2 Volume",
WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL,
0, 63, 0, out_pga_tlv),
SOC_DOUBLE_R("LINEOUT2 Switch",
WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 6, 1, 1),
SOC_DOUBLE_R("LINEOUT2 ZC Switch",
WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 7, 1, 0),
SOC_SINGLE("LINEOUT2 LP -12dB", WM8900_REG_LOUTMIXCTL1,
0, 1, 1),
};
static const struct snd_kcontrol_new wm8900_loutmix_controls[] = {
SOC_DAPM_SINGLE("LINPUT3 Bypass Switch", WM8900_REG_LOUTMIXCTL1, 7, 1, 0),
SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 7, 1, 0),
SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 7, 1, 0),
SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 3, 1, 0),
SOC_DAPM_SINGLE("DACL Switch", WM8900_REG_LOUTMIXCTL1, 8, 1, 0),
};
static const struct snd_kcontrol_new wm8900_routmix_controls[] = {
SOC_DAPM_SINGLE("RINPUT3 Bypass Switch", WM8900_REG_ROUTMIXCTL1, 7, 1, 0),
SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 3, 1, 0),
SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 3, 1, 0),
SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 7, 1, 0),
SOC_DAPM_SINGLE("DACR Switch", WM8900_REG_ROUTMIXCTL1, 8, 1, 0),
};
static const struct snd_kcontrol_new wm8900_linmix_controls[] = {
SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INBOOSTMIX1, 2, 1, 1),
SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INBOOSTMIX1, 6, 1, 1),
SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 6, 1, 1),
SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 6, 1, 0),
};
static const struct snd_kcontrol_new wm8900_rinmix_controls[] = {
SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INBOOSTMIX2, 2, 1, 1),
SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INBOOSTMIX2, 6, 1, 1),
SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 2, 1, 1),
SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 2, 1, 0),
};
static const struct snd_kcontrol_new wm8900_linpga_controls[] = {
SOC_DAPM_SINGLE("LINPUT1 Switch", WM8900_REG_INCTL, 6, 1, 0),
SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INCTL, 5, 1, 0),
SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INCTL, 4, 1, 0),
};
static const struct snd_kcontrol_new wm8900_rinpga_controls[] = {
SOC_DAPM_SINGLE("RINPUT1 Switch", WM8900_REG_INCTL, 2, 1, 0),
SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INCTL, 1, 1, 0),
SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INCTL, 0, 1, 0),
};
static const char *wm8900_lp_mux[] = { "Disabled", "Enabled" };
static SOC_ENUM_SINGLE_DECL(wm8900_lineout2_lp_mux,
WM8900_REG_LOUTMIXCTL1, 1, wm8900_lp_mux);
static const struct snd_kcontrol_new wm8900_lineout2_lp =
SOC_DAPM_ENUM("Route", wm8900_lineout2_lp_mux);
static const struct snd_soc_dapm_widget wm8900_dapm_widgets[] = {
/* Externally visible pins */
SND_SOC_DAPM_OUTPUT("LINEOUT1L"),
SND_SOC_DAPM_OUTPUT("LINEOUT1R"),
SND_SOC_DAPM_OUTPUT("LINEOUT2L"),
SND_SOC_DAPM_OUTPUT("LINEOUT2R"),
SND_SOC_DAPM_OUTPUT("HP_L"),
SND_SOC_DAPM_OUTPUT("HP_R"),
SND_SOC_DAPM_INPUT("RINPUT1"),
SND_SOC_DAPM_INPUT("LINPUT1"),
SND_SOC_DAPM_INPUT("RINPUT2"),
SND_SOC_DAPM_INPUT("LINPUT2"),
SND_SOC_DAPM_INPUT("RINPUT3"),
SND_SOC_DAPM_INPUT("LINPUT3"),
SND_SOC_DAPM_INPUT("AUX"),
SND_SOC_DAPM_VMID("VMID"),
/* Input */
SND_SOC_DAPM_MIXER("Left Input PGA", WM8900_REG_POWER2, 3, 0,
wm8900_linpga_controls,
ARRAY_SIZE(wm8900_linpga_controls)),
SND_SOC_DAPM_MIXER("Right Input PGA", WM8900_REG_POWER2, 2, 0,
wm8900_rinpga_controls,
ARRAY_SIZE(wm8900_rinpga_controls)),
SND_SOC_DAPM_MIXER("Left Input Mixer", WM8900_REG_POWER2, 5, 0,
wm8900_linmix_controls,
ARRAY_SIZE(wm8900_linmix_controls)),
SND_SOC_DAPM_MIXER("Right Input Mixer", WM8900_REG_POWER2, 4, 0,
wm8900_rinmix_controls,
ARRAY_SIZE(wm8900_rinmix_controls)),
SND_SOC_DAPM_SUPPLY("Mic Bias", WM8900_REG_POWER1, 4, 0, NULL, 0),
SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8900_REG_POWER2, 1, 0),
SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8900_REG_POWER2, 0, 0),
/* Output */
SND_SOC_DAPM_DAC("DACL", "Left HiFi Playback", WM8900_REG_POWER3, 1, 0),
SND_SOC_DAPM_DAC("DACR", "Right HiFi Playback", WM8900_REG_POWER3, 0, 0),
SND_SOC_DAPM_PGA_E("Headphone Amplifier", WM8900_REG_POWER3, 7, 0, NULL, 0,
wm8900_hp_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA("LINEOUT1L PGA", WM8900_REG_POWER2, 8, 0, NULL, 0),
SND_SOC_DAPM_PGA("LINEOUT1R PGA", WM8900_REG_POWER2, 7, 0, NULL, 0),
SND_SOC_DAPM_MUX("LINEOUT2 LP", SND_SOC_NOPM, 0, 0, &wm8900_lineout2_lp),
SND_SOC_DAPM_PGA("LINEOUT2L PGA", WM8900_REG_POWER3, 6, 0, NULL, 0),
SND_SOC_DAPM_PGA("LINEOUT2R PGA", WM8900_REG_POWER3, 5, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Left Output Mixer", WM8900_REG_POWER3, 3, 0,
wm8900_loutmix_controls,
ARRAY_SIZE(wm8900_loutmix_controls)),
SND_SOC_DAPM_MIXER("Right Output Mixer", WM8900_REG_POWER3, 2, 0,
wm8900_routmix_controls,
ARRAY_SIZE(wm8900_routmix_controls)),
};
/* Target, Path, Source */
static const struct snd_soc_dapm_route wm8900_dapm_routes[] = {
/* Inputs */
{"Left Input PGA", "LINPUT1 Switch", "LINPUT1"},
{"Left Input PGA", "LINPUT2 Switch", "LINPUT2"},
{"Left Input PGA", "LINPUT3 Switch", "LINPUT3"},
{"Right Input PGA", "RINPUT1 Switch", "RINPUT1"},
{"Right Input PGA", "RINPUT2 Switch", "RINPUT2"},
{"Right Input PGA", "RINPUT3 Switch", "RINPUT3"},
{"Left Input Mixer", "LINPUT2 Switch", "LINPUT2"},
{"Left Input Mixer", "LINPUT3 Switch", "LINPUT3"},
{"Left Input Mixer", "AUX Switch", "AUX"},
{"Left Input Mixer", "Input PGA Switch", "Left Input PGA"},
{"Right Input Mixer", "RINPUT2 Switch", "RINPUT2"},
{"Right Input Mixer", "RINPUT3 Switch", "RINPUT3"},
{"Right Input Mixer", "AUX Switch", "AUX"},
{"Right Input Mixer", "Input PGA Switch", "Right Input PGA"},
{"ADCL", NULL, "Left Input Mixer"},
{"ADCR", NULL, "Right Input Mixer"},
/* Outputs */
{"LINEOUT1L", NULL, "LINEOUT1L PGA"},
{"LINEOUT1L PGA", NULL, "Left Output Mixer"},
{"LINEOUT1R", NULL, "LINEOUT1R PGA"},
{"LINEOUT1R PGA", NULL, "Right Output Mixer"},
{"LINEOUT2L PGA", NULL, "Left Output Mixer"},
{"LINEOUT2 LP", "Disabled", "LINEOUT2L PGA"},
{"LINEOUT2 LP", "Enabled", "Left Output Mixer"},
{"LINEOUT2L", NULL, "LINEOUT2 LP"},
{"LINEOUT2R PGA", NULL, "Right Output Mixer"},
{"LINEOUT2 LP", "Disabled", "LINEOUT2R PGA"},
{"LINEOUT2 LP", "Enabled", "Right Output Mixer"},
{"LINEOUT2R", NULL, "LINEOUT2 LP"},
{"Left Output Mixer", "LINPUT3 Bypass Switch", "LINPUT3"},
{"Left Output Mixer", "AUX Bypass Switch", "AUX"},
{"Left Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
{"Left Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
{"Left Output Mixer", "DACL Switch", "DACL"},
{"Right Output Mixer", "RINPUT3 Bypass Switch", "RINPUT3"},
{"Right Output Mixer", "AUX Bypass Switch", "AUX"},
{"Right Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
{"Right Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
{"Right Output Mixer", "DACR Switch", "DACR"},
/* Note that the headphone output stage needs to be connected
* externally to LINEOUT2 via DC blocking capacitors. Other
* configurations are not supported.
*
* Note also that left and right headphone paths are treated as a
* mono path.
*/
{"Headphone Amplifier", NULL, "LINEOUT2 LP"},
{"Headphone Amplifier", NULL, "LINEOUT2 LP"},
{"HP_L", NULL, "Headphone Amplifier"},
{"HP_R", NULL, "Headphone Amplifier"},
};
static int wm8900_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
u16 reg;
reg = snd_soc_component_read(component, WM8900_REG_AUDIO1) & ~0x60;
switch (params_width(params)) {
case 16:
break;
case 20:
reg |= 0x20;
break;
case 24:
reg |= 0x40;
break;
case 32:
reg |= 0x60;
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, WM8900_REG_AUDIO1, reg);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
reg = snd_soc_component_read(component, WM8900_REG_DACCTRL);
if (params_rate(params) <= 24000)
reg |= WM8900_REG_DACCTRL_DAC_SB_FILT;
else
reg &= ~WM8900_REG_DACCTRL_DAC_SB_FILT;
snd_soc_component_write(component, WM8900_REG_DACCTRL, reg);
}
return 0;
}
/* FLL divisors */
struct _fll_div {
u16 fll_ratio;
u16 fllclk_div;
u16 fll_slow_lock_ref;
u16 n;
u16 k;
};
/* The size in bits of the FLL divide multiplied by 10
* to allow rounding later */
#define FIXED_FLL_SIZE ((1 << 16) * 10)
static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
unsigned int Fout)
{
u64 Kpart;
unsigned int K, Ndiv, Nmod, target;
unsigned int div;
if (WARN_ON(!Fout))
return -EINVAL;
/* The FLL must run at 90-100MHz which is then scaled down to
* the output value by FLLCLK_DIV. */
target = Fout;
div = 1;
while (target < 90000000) {
div *= 2;
target *= 2;
}
if (target > 100000000)
printk(KERN_WARNING "wm8900: FLL rate %u out of range, Fref=%u"
" Fout=%u\n", target, Fref, Fout);
if (div > 32) {
printk(KERN_ERR "wm8900: Invalid FLL division rate %u, "
"Fref=%u, Fout=%u, target=%u\n",
div, Fref, Fout, target);
return -EINVAL;
}
fll_div->fllclk_div = div >> 2;
if (Fref < 48000)
fll_div->fll_slow_lock_ref = 1;
else
fll_div->fll_slow_lock_ref = 0;
Ndiv = target / Fref;
if (Fref < 1000000)
fll_div->fll_ratio = 8;
else
fll_div->fll_ratio = 1;
fll_div->n = Ndiv / fll_div->fll_ratio;
Nmod = (target / fll_div->fll_ratio) % Fref;
/* Calculate fractional part - scale up so we can round. */
Kpart = FIXED_FLL_SIZE * (long long)Nmod;
do_div(Kpart, Fref);
K = Kpart & 0xFFFFFFFF;
if ((K % 10) >= 5)
K += 5;
/* Move down to proper range now rounding is done */
fll_div->k = K / 10;
if (WARN_ON(target != Fout * (fll_div->fllclk_div << 2)) ||
WARN_ON(!K && target != Fref * fll_div->fll_ratio * fll_div->n))
return -EINVAL;
return 0;
}
static int wm8900_set_fll(struct snd_soc_component *component,
int fll_id, unsigned int freq_in, unsigned int freq_out)
{
struct wm8900_priv *wm8900 = snd_soc_component_get_drvdata(component);
struct _fll_div fll_div;
if (wm8900->fll_in == freq_in && wm8900->fll_out == freq_out)
return 0;
/* The digital side should be disabled during any change. */
snd_soc_component_update_bits(component, WM8900_REG_POWER1,
WM8900_REG_POWER1_FLL_ENA, 0);
/* Disable the FLL? */
if (!freq_in || !freq_out) {
snd_soc_component_update_bits(component, WM8900_REG_CLOCKING1,
WM8900_REG_CLOCKING1_MCLK_SRC, 0);
snd_soc_component_update_bits(component, WM8900_REG_FLLCTL1,
WM8900_REG_FLLCTL1_OSC_ENA, 0);
wm8900->fll_in = freq_in;
wm8900->fll_out = freq_out;
return 0;
}
if (fll_factors(&fll_div, freq_in, freq_out) != 0)
goto reenable;
wm8900->fll_in = freq_in;
wm8900->fll_out = freq_out;
/* The osclilator *MUST* be enabled before we enable the
* digital circuit. */
snd_soc_component_write(component, WM8900_REG_FLLCTL1,
fll_div.fll_ratio | WM8900_REG_FLLCTL1_OSC_ENA);
snd_soc_component_write(component, WM8900_REG_FLLCTL4, fll_div.n >> 5);
snd_soc_component_write(component, WM8900_REG_FLLCTL5,
(fll_div.fllclk_div << 6) | (fll_div.n & 0x1f));
if (fll_div.k) {
snd_soc_component_write(component, WM8900_REG_FLLCTL2,
(fll_div.k >> 8) | 0x100);
snd_soc_component_write(component, WM8900_REG_FLLCTL3, fll_div.k & 0xff);
} else
snd_soc_component_write(component, WM8900_REG_FLLCTL2, 0);
if (fll_div.fll_slow_lock_ref)
snd_soc_component_write(component, WM8900_REG_FLLCTL6,
WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF);
else
snd_soc_component_write(component, WM8900_REG_FLLCTL6, 0);
snd_soc_component_update_bits(component, WM8900_REG_POWER1,
WM8900_REG_POWER1_FLL_ENA,
WM8900_REG_POWER1_FLL_ENA);
reenable:
snd_soc_component_update_bits(component, WM8900_REG_CLOCKING1,
WM8900_REG_CLOCKING1_MCLK_SRC,
WM8900_REG_CLOCKING1_MCLK_SRC);
return 0;
}
static int wm8900_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
int source, unsigned int freq_in, unsigned int freq_out)
{
return wm8900_set_fll(codec_dai->component, pll_id, freq_in, freq_out);
}
static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
int div_id, int div)
{
struct snd_soc_component *component = codec_dai->component;
switch (div_id) {
case WM8900_BCLK_DIV:
snd_soc_component_update_bits(component, WM8900_REG_CLOCKING1,
WM8900_REG_CLOCKING1_BCLK_MASK, div);
break;
case WM8900_OPCLK_DIV:
snd_soc_component_update_bits(component, WM8900_REG_CLOCKING1,
WM8900_REG_CLOCKING1_OPCLK_MASK, div);
break;
case WM8900_DAC_LRCLK:
snd_soc_component_update_bits(component, WM8900_REG_AUDIO4,
WM8900_LRC_MASK, div);
break;
case WM8900_ADC_LRCLK:
snd_soc_component_update_bits(component, WM8900_REG_AUDIO3,
WM8900_LRC_MASK, div);
break;
case WM8900_DAC_CLKDIV:
snd_soc_component_update_bits(component, WM8900_REG_CLOCKING2,
WM8900_REG_CLOCKING2_DAC_CLKDIV, div);
break;
case WM8900_ADC_CLKDIV:
snd_soc_component_update_bits(component, WM8900_REG_CLOCKING2,
WM8900_REG_CLOCKING2_ADC_CLKDIV, div);
break;
case WM8900_LRCLK_MODE:
snd_soc_component_update_bits(component, WM8900_REG_DACCTRL,
WM8900_REG_DACCTRL_AIF_LRCLKRATE, div);
break;
default:
return -EINVAL;
}
return 0;
}
static int wm8900_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
unsigned int clocking1, aif1, aif3, aif4;
clocking1 = snd_soc_component_read(component, WM8900_REG_CLOCKING1);
aif1 = snd_soc_component_read(component, WM8900_REG_AUDIO1);
aif3 = snd_soc_component_read(component, WM8900_REG_AUDIO3);
aif4 = snd_soc_component_read(component, WM8900_REG_AUDIO4);
/* set master/slave audio interface */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
break;
case SND_SOC_DAIFMT_CBS_CFM:
clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
break;
case SND_SOC_DAIFMT_CBM_CFM:
clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
break;
case SND_SOC_DAIFMT_CBM_CFS:
clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
break;
case SND_SOC_DAIFMT_DSP_B:
aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
break;
case SND_SOC_DAIFMT_I2S:
aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
aif1 |= 0x10;
break;
case SND_SOC_DAIFMT_RIGHT_J:
aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
break;
case SND_SOC_DAIFMT_LEFT_J:
aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
aif1 |= 0x8;
break;
default:
return -EINVAL;
}
/* Clock inversion */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B:
/* frame inversion not valid for DSP modes */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
break;
case SND_SOC_DAIFMT_IB_NF:
aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
break;
default:
return -EINVAL;
}
break;
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_RIGHT_J:
case SND_SOC_DAIFMT_LEFT_J:
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
break;
case SND_SOC_DAIFMT_IB_IF:
aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
break;
case SND_SOC_DAIFMT_IB_NF:
aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
break;
case SND_SOC_DAIFMT_NB_IF:
aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, WM8900_REG_CLOCKING1, clocking1);
snd_soc_component_write(component, WM8900_REG_AUDIO1, aif1);
snd_soc_component_write(component, WM8900_REG_AUDIO3, aif3);
snd_soc_component_write(component, WM8900_REG_AUDIO4, aif4);
return 0;
}
static int wm8900_mute(struct snd_soc_dai *codec_dai, int mute, int direction)
{
struct snd_soc_component *component = codec_dai->component;
u16 reg;
reg = snd_soc_component_read(component, WM8900_REG_DACCTRL);
if (mute)
reg |= WM8900_REG_DACCTRL_MUTE;
else
reg &= ~WM8900_REG_DACCTRL_MUTE;
snd_soc_component_write(component, WM8900_REG_DACCTRL, reg);
return 0;
}
#define WM8900_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
#define WM8900_PCM_FORMATS \
(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE)
static const struct snd_soc_dai_ops wm8900_dai_ops = {
.hw_params = wm8900_hw_params,
.set_clkdiv = wm8900_set_dai_clkdiv,
.set_pll = wm8900_set_dai_pll,
.set_fmt = wm8900_set_dai_fmt,
.mute_stream = wm8900_mute,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver wm8900_dai = {
.name = "wm8900-hifi",
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM8900_RATES,
.formats = WM8900_PCM_FORMATS,
},
.capture = {
.stream_name = "HiFi Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM8900_RATES,
.formats = WM8900_PCM_FORMATS,
},
.ops = &wm8900_dai_ops,
};
static int wm8900_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
u16 reg;
switch (level) {
case SND_SOC_BIAS_ON:
/* Enable thermal shutdown */
snd_soc_component_update_bits(component, WM8900_REG_GPIO,
WM8900_REG_GPIO_TEMP_ENA,
WM8900_REG_GPIO_TEMP_ENA);
snd_soc_component_update_bits(component, WM8900_REG_ADDCTL,
WM8900_REG_ADDCTL_TEMP_SD,
WM8900_REG_ADDCTL_TEMP_SD);
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
/* Charge capacitors if initial power up */
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
/* STARTUP_BIAS_ENA on */
snd_soc_component_write(component, WM8900_REG_POWER1,
WM8900_REG_POWER1_STARTUP_BIAS_ENA);
/* Startup bias mode */
snd_soc_component_write(component, WM8900_REG_ADDCTL,
WM8900_REG_ADDCTL_BIAS_SRC |
WM8900_REG_ADDCTL_VMID_SOFTST);
/* VMID 2x50k */
snd_soc_component_write(component, WM8900_REG_POWER1,
WM8900_REG_POWER1_STARTUP_BIAS_ENA | 0x1);
/* Allow capacitors to charge */
schedule_timeout_interruptible(msecs_to_jiffies(400));
/* Enable bias */
snd_soc_component_write(component, WM8900_REG_POWER1,
WM8900_REG_POWER1_STARTUP_BIAS_ENA |
WM8900_REG_POWER1_BIAS_ENA | 0x1);
snd_soc_component_write(component, WM8900_REG_ADDCTL, 0);
snd_soc_component_write(component, WM8900_REG_POWER1,
WM8900_REG_POWER1_BIAS_ENA | 0x1);
}
reg = snd_soc_component_read(component, WM8900_REG_POWER1);
snd_soc_component_write(component, WM8900_REG_POWER1,
(reg & WM8900_REG_POWER1_FLL_ENA) |
WM8900_REG_POWER1_BIAS_ENA | 0x1);
snd_soc_component_write(component, WM8900_REG_POWER2,
WM8900_REG_POWER2_SYSCLK_ENA);
snd_soc_component_write(component, WM8900_REG_POWER3, 0);
break;
case SND_SOC_BIAS_OFF:
/* Startup bias enable */
reg = snd_soc_component_read(component, WM8900_REG_POWER1);
snd_soc_component_write(component, WM8900_REG_POWER1,
reg & WM8900_REG_POWER1_STARTUP_BIAS_ENA);
snd_soc_component_write(component, WM8900_REG_ADDCTL,
WM8900_REG_ADDCTL_BIAS_SRC |
WM8900_REG_ADDCTL_VMID_SOFTST);
/* Discharge caps */
snd_soc_component_write(component, WM8900_REG_POWER1,
WM8900_REG_POWER1_STARTUP_BIAS_ENA);
schedule_timeout_interruptible(msecs_to_jiffies(500));
/* Remove clamp */
snd_soc_component_write(component, WM8900_REG_HPCTL1, 0);
/* Power down */
snd_soc_component_write(component, WM8900_REG_ADDCTL, 0);
snd_soc_component_write(component, WM8900_REG_POWER1, 0);
snd_soc_component_write(component, WM8900_REG_POWER2, 0);
snd_soc_component_write(component, WM8900_REG_POWER3, 0);
/* Need to let things settle before stopping the clock
* to ensure that restart works, see "Stopping the
* master clock" in the datasheet. */
schedule_timeout_interruptible(msecs_to_jiffies(1));
snd_soc_component_write(component, WM8900_REG_POWER2,
WM8900_REG_POWER2_SYSCLK_ENA);
break;
}
return 0;
}
static int wm8900_suspend(struct snd_soc_component *component)
{
struct wm8900_priv *wm8900 = snd_soc_component_get_drvdata(component);
int fll_out = wm8900->fll_out;
int fll_in = wm8900->fll_in;
int ret;
/* Stop the FLL in an orderly fashion */
ret = wm8900_set_fll(component, 0, 0, 0);
if (ret != 0) {
dev_err(component->dev, "Failed to stop FLL\n");
return ret;
}
wm8900->fll_out = fll_out;
wm8900->fll_in = fll_in;
snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
return 0;
}
static int wm8900_resume(struct snd_soc_component *component)
{
struct wm8900_priv *wm8900 = snd_soc_component_get_drvdata(component);
int ret;
wm8900_reset(component);
ret = regcache_sync(wm8900->regmap);
if (ret != 0) {
dev_err(component->dev, "Failed to restore cache: %d\n", ret);
return ret;
}
snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
/* Restart the FLL? */
if (wm8900->fll_out) {
int fll_out = wm8900->fll_out;
int fll_in = wm8900->fll_in;
wm8900->fll_in = 0;
wm8900->fll_out = 0;
ret = wm8900_set_fll(component, 0, fll_in, fll_out);
if (ret != 0) {
dev_err(component->dev, "Failed to restart FLL\n");
return ret;
}
}
return 0;
}
static int wm8900_probe(struct snd_soc_component *component)
{
int reg;
reg = snd_soc_component_read(component, WM8900_REG_ID);
if (reg != 0x8900) {
dev_err(component->dev, "Device is not a WM8900 - ID %x\n", reg);
return -ENODEV;
}
wm8900_reset(component);
/* Turn the chip on */
snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
/* Latch the volume update bits */
snd_soc_component_update_bits(component, WM8900_REG_LINVOL, 0x100, 0x100);
snd_soc_component_update_bits(component, WM8900_REG_RINVOL, 0x100, 0x100);
snd_soc_component_update_bits(component, WM8900_REG_LOUT1CTL, 0x100, 0x100);
snd_soc_component_update_bits(component, WM8900_REG_ROUT1CTL, 0x100, 0x100);
snd_soc_component_update_bits(component, WM8900_REG_LOUT2CTL, 0x100, 0x100);
snd_soc_component_update_bits(component, WM8900_REG_ROUT2CTL, 0x100, 0x100);
snd_soc_component_update_bits(component, WM8900_REG_LDAC_DV, 0x100, 0x100);
snd_soc_component_update_bits(component, WM8900_REG_RDAC_DV, 0x100, 0x100);
snd_soc_component_update_bits(component, WM8900_REG_LADC_DV, 0x100, 0x100);
snd_soc_component_update_bits(component, WM8900_REG_RADC_DV, 0x100, 0x100);
/* Set the DAC and mixer output bias */
snd_soc_component_write(component, WM8900_REG_OUTBIASCTL, 0x81);
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_wm8900 = {
.probe = wm8900_probe,
.suspend = wm8900_suspend,
.resume = wm8900_resume,
.set_bias_level = wm8900_set_bias_level,
.controls = wm8900_snd_controls,
.num_controls = ARRAY_SIZE(wm8900_snd_controls),
.dapm_widgets = wm8900_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8900_dapm_widgets),
.dapm_routes = wm8900_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(wm8900_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config wm8900_regmap = {
.reg_bits = 8,
.val_bits = 16,
.max_register = WM8900_MAXREG,
.reg_defaults = wm8900_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8900_reg_defaults),
.cache_type = REGCACHE_MAPLE,
.volatile_reg = wm8900_volatile_register,
};
#if defined(CONFIG_SPI_MASTER)
static int wm8900_spi_probe(struct spi_device *spi)
{
struct wm8900_priv *wm8900;
int ret;
wm8900 = devm_kzalloc(&spi->dev, sizeof(struct wm8900_priv),
GFP_KERNEL);
if (wm8900 == NULL)
return -ENOMEM;
wm8900->regmap = devm_regmap_init_spi(spi, &wm8900_regmap);
if (IS_ERR(wm8900->regmap))
return PTR_ERR(wm8900->regmap);
spi_set_drvdata(spi, wm8900);
ret = devm_snd_soc_register_component(&spi->dev,
&soc_component_dev_wm8900, &wm8900_dai, 1);
return ret;
}
static struct spi_driver wm8900_spi_driver = {
.driver = {
.name = "wm8900",
},
.probe = wm8900_spi_probe,
};
#endif /* CONFIG_SPI_MASTER */
#if IS_ENABLED(CONFIG_I2C)
static int wm8900_i2c_probe(struct i2c_client *i2c)
{
struct wm8900_priv *wm8900;
int ret;
wm8900 = devm_kzalloc(&i2c->dev, sizeof(struct wm8900_priv),
GFP_KERNEL);
if (wm8900 == NULL)
return -ENOMEM;
wm8900->regmap = devm_regmap_init_i2c(i2c, &wm8900_regmap);
if (IS_ERR(wm8900->regmap))
return PTR_ERR(wm8900->regmap);
i2c_set_clientdata(i2c, wm8900);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_wm8900, &wm8900_dai, 1);
return ret;
}
static void wm8900_i2c_remove(struct i2c_client *client)
{}
static const struct i2c_device_id wm8900_i2c_id[] = {
{ "wm8900", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8900_i2c_id);
static struct i2c_driver wm8900_i2c_driver = {
.driver = {
.name = "wm8900",
},
.probe = wm8900_i2c_probe,
.remove = wm8900_i2c_remove,
.id_table = wm8900_i2c_id,
};
#endif
static int __init wm8900_modinit(void)
{
int ret = 0;
#if IS_ENABLED(CONFIG_I2C)
ret = i2c_add_driver(&wm8900_i2c_driver);
if (ret != 0) {
printk(KERN_ERR "Failed to register wm8900 I2C driver: %d\n",
ret);
}
#endif
#if defined(CONFIG_SPI_MASTER)
ret = spi_register_driver(&wm8900_spi_driver);
if (ret != 0) {
printk(KERN_ERR "Failed to register wm8900 SPI driver: %d\n",
ret);
}
#endif
return ret;
}
module_init(wm8900_modinit);
static void __exit wm8900_exit(void)
{
#if IS_ENABLED(CONFIG_I2C)
i2c_del_driver(&wm8900_i2c_driver);
#endif
#if defined(CONFIG_SPI_MASTER)
spi_unregister_driver(&wm8900_spi_driver);
#endif
}
module_exit(wm8900_exit);
MODULE_DESCRIPTION("ASoC WM8900 driver");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8900.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* cs42l42.c -- CS42L42 ALSA SoC audio driver
*
* Copyright 2016 Cirrus Logic, Inc.
*
* Author: James Schulman <[email protected]>
* Author: Brian Austin <[email protected]>
* Author: Michael White <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/version.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/acpi.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/property.h>
#include <linux/regulator/consumer.h>
#include <linux/gpio/consumer.h>
#include <linux/of_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <dt-bindings/sound/cs42l42.h>
#include "cs42l42.h"
#include "cirrus_legacy.h"
static const char * const cs42l42_supply_names[] = {
"VA",
"VP",
"VCP",
"VD_FILT",
"VL",
};
static const struct reg_default cs42l42_reg_defaults[] = {
{ CS42L42_FRZ_CTL, 0x00 },
{ CS42L42_SRC_CTL, 0x10 },
{ CS42L42_MCLK_CTL, 0x02 },
{ CS42L42_SFTRAMP_RATE, 0xA4 },
{ CS42L42_SLOW_START_ENABLE, 0x70 },
{ CS42L42_I2C_DEBOUNCE, 0x88 },
{ CS42L42_I2C_STRETCH, 0x03 },
{ CS42L42_I2C_TIMEOUT, 0xB7 },
{ CS42L42_PWR_CTL1, 0xFF },
{ CS42L42_PWR_CTL2, 0x84 },
{ CS42L42_PWR_CTL3, 0x20 },
{ CS42L42_RSENSE_CTL1, 0x40 },
{ CS42L42_RSENSE_CTL2, 0x00 },
{ CS42L42_OSC_SWITCH, 0x00 },
{ CS42L42_RSENSE_CTL3, 0x1B },
{ CS42L42_TSENSE_CTL, 0x1B },
{ CS42L42_TSRS_INT_DISABLE, 0x00 },
{ CS42L42_HSDET_CTL1, 0x77 },
{ CS42L42_HSDET_CTL2, 0x00 },
{ CS42L42_HS_SWITCH_CTL, 0xF3 },
{ CS42L42_HS_CLAMP_DISABLE, 0x00 },
{ CS42L42_MCLK_SRC_SEL, 0x00 },
{ CS42L42_SPDIF_CLK_CFG, 0x00 },
{ CS42L42_FSYNC_PW_LOWER, 0x00 },
{ CS42L42_FSYNC_PW_UPPER, 0x00 },
{ CS42L42_FSYNC_P_LOWER, 0xF9 },
{ CS42L42_FSYNC_P_UPPER, 0x00 },
{ CS42L42_ASP_CLK_CFG, 0x00 },
{ CS42L42_ASP_FRM_CFG, 0x10 },
{ CS42L42_FS_RATE_EN, 0x00 },
{ CS42L42_IN_ASRC_CLK, 0x00 },
{ CS42L42_OUT_ASRC_CLK, 0x00 },
{ CS42L42_PLL_DIV_CFG1, 0x00 },
{ CS42L42_ADC_OVFL_INT_MASK, 0x01 },
{ CS42L42_MIXER_INT_MASK, 0x0F },
{ CS42L42_SRC_INT_MASK, 0x0F },
{ CS42L42_ASP_RX_INT_MASK, 0x1F },
{ CS42L42_ASP_TX_INT_MASK, 0x0F },
{ CS42L42_CODEC_INT_MASK, 0x03 },
{ CS42L42_SRCPL_INT_MASK, 0x7F },
{ CS42L42_VPMON_INT_MASK, 0x01 },
{ CS42L42_PLL_LOCK_INT_MASK, 0x01 },
{ CS42L42_TSRS_PLUG_INT_MASK, 0x0F },
{ CS42L42_PLL_CTL1, 0x00 },
{ CS42L42_PLL_DIV_FRAC0, 0x00 },
{ CS42L42_PLL_DIV_FRAC1, 0x00 },
{ CS42L42_PLL_DIV_FRAC2, 0x00 },
{ CS42L42_PLL_DIV_INT, 0x40 },
{ CS42L42_PLL_CTL3, 0x10 },
{ CS42L42_PLL_CAL_RATIO, 0x80 },
{ CS42L42_PLL_CTL4, 0x03 },
{ CS42L42_LOAD_DET_EN, 0x00 },
{ CS42L42_HSBIAS_SC_AUTOCTL, 0x03 },
{ CS42L42_WAKE_CTL, 0xC0 },
{ CS42L42_ADC_DISABLE_MUTE, 0x00 },
{ CS42L42_TIPSENSE_CTL, 0x02 },
{ CS42L42_MISC_DET_CTL, 0x03 },
{ CS42L42_MIC_DET_CTL1, 0x1F },
{ CS42L42_MIC_DET_CTL2, 0x2F },
{ CS42L42_DET_INT1_MASK, 0xE0 },
{ CS42L42_DET_INT2_MASK, 0xFF },
{ CS42L42_HS_BIAS_CTL, 0xC2 },
{ CS42L42_ADC_CTL, 0x00 },
{ CS42L42_ADC_VOLUME, 0x00 },
{ CS42L42_ADC_WNF_HPF_CTL, 0x71 },
{ CS42L42_DAC_CTL1, 0x00 },
{ CS42L42_DAC_CTL2, 0x02 },
{ CS42L42_HP_CTL, 0x0D },
{ CS42L42_CLASSH_CTL, 0x07 },
{ CS42L42_MIXER_CHA_VOL, 0x3F },
{ CS42L42_MIXER_ADC_VOL, 0x3F },
{ CS42L42_MIXER_CHB_VOL, 0x3F },
{ CS42L42_EQ_COEF_IN0, 0x00 },
{ CS42L42_EQ_COEF_IN1, 0x00 },
{ CS42L42_EQ_COEF_IN2, 0x00 },
{ CS42L42_EQ_COEF_IN3, 0x00 },
{ CS42L42_EQ_COEF_RW, 0x00 },
{ CS42L42_EQ_COEF_OUT0, 0x00 },
{ CS42L42_EQ_COEF_OUT1, 0x00 },
{ CS42L42_EQ_COEF_OUT2, 0x00 },
{ CS42L42_EQ_COEF_OUT3, 0x00 },
{ CS42L42_EQ_INIT_STAT, 0x00 },
{ CS42L42_EQ_START_FILT, 0x00 },
{ CS42L42_EQ_MUTE_CTL, 0x00 },
{ CS42L42_SP_RX_CH_SEL, 0x04 },
{ CS42L42_SP_RX_ISOC_CTL, 0x04 },
{ CS42L42_SP_RX_FS, 0x8C },
{ CS42l42_SPDIF_CH_SEL, 0x0E },
{ CS42L42_SP_TX_ISOC_CTL, 0x04 },
{ CS42L42_SP_TX_FS, 0xCC },
{ CS42L42_SPDIF_SW_CTL1, 0x3F },
{ CS42L42_SRC_SDIN_FS, 0x40 },
{ CS42L42_SRC_SDOUT_FS, 0x40 },
{ CS42L42_SPDIF_CTL1, 0x01 },
{ CS42L42_SPDIF_CTL2, 0x00 },
{ CS42L42_SPDIF_CTL3, 0x00 },
{ CS42L42_SPDIF_CTL4, 0x42 },
{ CS42L42_ASP_TX_SZ_EN, 0x00 },
{ CS42L42_ASP_TX_CH_EN, 0x00 },
{ CS42L42_ASP_TX_CH_AP_RES, 0x0F },
{ CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 },
{ CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 },
{ CS42L42_ASP_TX_HIZ_DLY_CFG, 0x00 },
{ CS42L42_ASP_TX_CH2_BIT_MSB, 0x00 },
{ CS42L42_ASP_TX_CH2_BIT_LSB, 0x00 },
{ CS42L42_ASP_RX_DAI0_EN, 0x00 },
{ CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x03 },
{ CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 },
{ CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x00 },
{ CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x03 },
{ CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 },
{ CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0x00 },
{ CS42L42_ASP_RX_DAI0_CH3_AP_RES, 0x03 },
{ CS42L42_ASP_RX_DAI0_CH3_BIT_MSB, 0x00 },
{ CS42L42_ASP_RX_DAI0_CH3_BIT_LSB, 0x00 },
{ CS42L42_ASP_RX_DAI0_CH4_AP_RES, 0x03 },
{ CS42L42_ASP_RX_DAI0_CH4_BIT_MSB, 0x00 },
{ CS42L42_ASP_RX_DAI0_CH4_BIT_LSB, 0x00 },
{ CS42L42_ASP_RX_DAI1_CH1_AP_RES, 0x03 },
{ CS42L42_ASP_RX_DAI1_CH1_BIT_MSB, 0x00 },
{ CS42L42_ASP_RX_DAI1_CH1_BIT_LSB, 0x00 },
{ CS42L42_ASP_RX_DAI1_CH2_AP_RES, 0x03 },
{ CS42L42_ASP_RX_DAI1_CH2_BIT_MSB, 0x00 },
{ CS42L42_ASP_RX_DAI1_CH2_BIT_LSB, 0x00 },
};
bool cs42l42_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS42L42_PAGE_REGISTER:
case CS42L42_DEVID_AB:
case CS42L42_DEVID_CD:
case CS42L42_DEVID_E:
case CS42L42_FABID:
case CS42L42_REVID:
case CS42L42_FRZ_CTL:
case CS42L42_SRC_CTL:
case CS42L42_MCLK_STATUS:
case CS42L42_MCLK_CTL:
case CS42L42_SFTRAMP_RATE:
case CS42L42_SLOW_START_ENABLE:
case CS42L42_I2C_DEBOUNCE:
case CS42L42_I2C_STRETCH:
case CS42L42_I2C_TIMEOUT:
case CS42L42_PWR_CTL1:
case CS42L42_PWR_CTL2:
case CS42L42_PWR_CTL3:
case CS42L42_RSENSE_CTL1:
case CS42L42_RSENSE_CTL2:
case CS42L42_OSC_SWITCH:
case CS42L42_OSC_SWITCH_STATUS:
case CS42L42_RSENSE_CTL3:
case CS42L42_TSENSE_CTL:
case CS42L42_TSRS_INT_DISABLE:
case CS42L42_TRSENSE_STATUS:
case CS42L42_HSDET_CTL1:
case CS42L42_HSDET_CTL2:
case CS42L42_HS_SWITCH_CTL:
case CS42L42_HS_DET_STATUS:
case CS42L42_HS_CLAMP_DISABLE:
case CS42L42_MCLK_SRC_SEL:
case CS42L42_SPDIF_CLK_CFG:
case CS42L42_FSYNC_PW_LOWER:
case CS42L42_FSYNC_PW_UPPER:
case CS42L42_FSYNC_P_LOWER:
case CS42L42_FSYNC_P_UPPER:
case CS42L42_ASP_CLK_CFG:
case CS42L42_ASP_FRM_CFG:
case CS42L42_FS_RATE_EN:
case CS42L42_IN_ASRC_CLK:
case CS42L42_OUT_ASRC_CLK:
case CS42L42_PLL_DIV_CFG1:
case CS42L42_ADC_OVFL_STATUS:
case CS42L42_MIXER_STATUS:
case CS42L42_SRC_STATUS:
case CS42L42_ASP_RX_STATUS:
case CS42L42_ASP_TX_STATUS:
case CS42L42_CODEC_STATUS:
case CS42L42_DET_INT_STATUS1:
case CS42L42_DET_INT_STATUS2:
case CS42L42_SRCPL_INT_STATUS:
case CS42L42_VPMON_STATUS:
case CS42L42_PLL_LOCK_STATUS:
case CS42L42_TSRS_PLUG_STATUS:
case CS42L42_ADC_OVFL_INT_MASK:
case CS42L42_MIXER_INT_MASK:
case CS42L42_SRC_INT_MASK:
case CS42L42_ASP_RX_INT_MASK:
case CS42L42_ASP_TX_INT_MASK:
case CS42L42_CODEC_INT_MASK:
case CS42L42_SRCPL_INT_MASK:
case CS42L42_VPMON_INT_MASK:
case CS42L42_PLL_LOCK_INT_MASK:
case CS42L42_TSRS_PLUG_INT_MASK:
case CS42L42_PLL_CTL1:
case CS42L42_PLL_DIV_FRAC0:
case CS42L42_PLL_DIV_FRAC1:
case CS42L42_PLL_DIV_FRAC2:
case CS42L42_PLL_DIV_INT:
case CS42L42_PLL_CTL3:
case CS42L42_PLL_CAL_RATIO:
case CS42L42_PLL_CTL4:
case CS42L42_LOAD_DET_RCSTAT:
case CS42L42_LOAD_DET_DONE:
case CS42L42_LOAD_DET_EN:
case CS42L42_HSBIAS_SC_AUTOCTL:
case CS42L42_WAKE_CTL:
case CS42L42_ADC_DISABLE_MUTE:
case CS42L42_TIPSENSE_CTL:
case CS42L42_MISC_DET_CTL:
case CS42L42_MIC_DET_CTL1:
case CS42L42_MIC_DET_CTL2:
case CS42L42_DET_STATUS1:
case CS42L42_DET_STATUS2:
case CS42L42_DET_INT1_MASK:
case CS42L42_DET_INT2_MASK:
case CS42L42_HS_BIAS_CTL:
case CS42L42_ADC_CTL:
case CS42L42_ADC_VOLUME:
case CS42L42_ADC_WNF_HPF_CTL:
case CS42L42_DAC_CTL1:
case CS42L42_DAC_CTL2:
case CS42L42_HP_CTL:
case CS42L42_CLASSH_CTL:
case CS42L42_MIXER_CHA_VOL:
case CS42L42_MIXER_ADC_VOL:
case CS42L42_MIXER_CHB_VOL:
case CS42L42_EQ_COEF_IN0:
case CS42L42_EQ_COEF_IN1:
case CS42L42_EQ_COEF_IN2:
case CS42L42_EQ_COEF_IN3:
case CS42L42_EQ_COEF_RW:
case CS42L42_EQ_COEF_OUT0:
case CS42L42_EQ_COEF_OUT1:
case CS42L42_EQ_COEF_OUT2:
case CS42L42_EQ_COEF_OUT3:
case CS42L42_EQ_INIT_STAT:
case CS42L42_EQ_START_FILT:
case CS42L42_EQ_MUTE_CTL:
case CS42L42_SP_RX_CH_SEL:
case CS42L42_SP_RX_ISOC_CTL:
case CS42L42_SP_RX_FS:
case CS42l42_SPDIF_CH_SEL:
case CS42L42_SP_TX_ISOC_CTL:
case CS42L42_SP_TX_FS:
case CS42L42_SPDIF_SW_CTL1:
case CS42L42_SRC_SDIN_FS:
case CS42L42_SRC_SDOUT_FS:
case CS42L42_SOFT_RESET_REBOOT:
case CS42L42_SPDIF_CTL1:
case CS42L42_SPDIF_CTL2:
case CS42L42_SPDIF_CTL3:
case CS42L42_SPDIF_CTL4:
case CS42L42_ASP_TX_SZ_EN:
case CS42L42_ASP_TX_CH_EN:
case CS42L42_ASP_TX_CH_AP_RES:
case CS42L42_ASP_TX_CH1_BIT_MSB:
case CS42L42_ASP_TX_CH1_BIT_LSB:
case CS42L42_ASP_TX_HIZ_DLY_CFG:
case CS42L42_ASP_TX_CH2_BIT_MSB:
case CS42L42_ASP_TX_CH2_BIT_LSB:
case CS42L42_ASP_RX_DAI0_EN:
case CS42L42_ASP_RX_DAI0_CH1_AP_RES:
case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB:
case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB:
case CS42L42_ASP_RX_DAI0_CH2_AP_RES:
case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB:
case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB:
case CS42L42_ASP_RX_DAI0_CH3_AP_RES:
case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB:
case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB:
case CS42L42_ASP_RX_DAI0_CH4_AP_RES:
case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB:
case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB:
case CS42L42_ASP_RX_DAI1_CH1_AP_RES:
case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB:
case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB:
case CS42L42_ASP_RX_DAI1_CH2_AP_RES:
case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB:
case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB:
case CS42L42_SUB_REVID:
return true;
default:
return false;
}
}
EXPORT_SYMBOL_NS_GPL(cs42l42_readable_register, SND_SOC_CS42L42_CORE);
bool cs42l42_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS42L42_DEVID_AB:
case CS42L42_DEVID_CD:
case CS42L42_DEVID_E:
case CS42L42_MCLK_STATUS:
case CS42L42_OSC_SWITCH_STATUS:
case CS42L42_TRSENSE_STATUS:
case CS42L42_HS_DET_STATUS:
case CS42L42_ADC_OVFL_STATUS:
case CS42L42_MIXER_STATUS:
case CS42L42_SRC_STATUS:
case CS42L42_ASP_RX_STATUS:
case CS42L42_ASP_TX_STATUS:
case CS42L42_CODEC_STATUS:
case CS42L42_DET_INT_STATUS1:
case CS42L42_DET_INT_STATUS2:
case CS42L42_SRCPL_INT_STATUS:
case CS42L42_VPMON_STATUS:
case CS42L42_PLL_LOCK_STATUS:
case CS42L42_TSRS_PLUG_STATUS:
case CS42L42_LOAD_DET_RCSTAT:
case CS42L42_LOAD_DET_DONE:
case CS42L42_DET_STATUS1:
case CS42L42_DET_STATUS2:
case CS42L42_SOFT_RESET_REBOOT:
return true;
default:
return false;
}
}
EXPORT_SYMBOL_NS_GPL(cs42l42_volatile_register, SND_SOC_CS42L42_CORE);
const struct regmap_range_cfg cs42l42_page_range = {
.name = "Pages",
.range_min = 0,
.range_max = CS42L42_MAX_REGISTER,
.selector_reg = CS42L42_PAGE_REGISTER,
.selector_mask = 0xff,
.selector_shift = 0,
.window_start = 0,
.window_len = 256,
};
EXPORT_SYMBOL_NS_GPL(cs42l42_page_range, SND_SOC_CS42L42_CORE);
const struct regmap_config cs42l42_regmap = {
.reg_bits = 8,
.val_bits = 8,
.readable_reg = cs42l42_readable_register,
.volatile_reg = cs42l42_volatile_register,
.ranges = &cs42l42_page_range,
.num_ranges = 1,
.max_register = CS42L42_MAX_REGISTER,
.reg_defaults = cs42l42_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults),
.cache_type = REGCACHE_MAPLE,
.use_single_read = true,
.use_single_write = true,
};
EXPORT_SYMBOL_NS_GPL(cs42l42_regmap, SND_SOC_CS42L42_CORE);
static DECLARE_TLV_DB_SCALE(adc_tlv, -9700, 100, true);
static DECLARE_TLV_DB_SCALE(mixer_tlv, -6300, 100, true);
static int cs42l42_slow_start_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
u8 val;
/* all bits of SLOW_START_EN must change together */
switch (ucontrol->value.integer.value[0]) {
case 0:
val = 0;
break;
case 1:
val = CS42L42_SLOW_START_EN_MASK;
break;
default:
return -EINVAL;
}
return snd_soc_component_update_bits(component, CS42L42_SLOW_START_ENABLE,
CS42L42_SLOW_START_EN_MASK, val);
}
static const char * const cs42l42_hpf_freq_text[] = {
"1.86Hz", "120Hz", "235Hz", "466Hz"
};
static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
CS42L42_ADC_HPF_CF_SHIFT,
cs42l42_hpf_freq_text);
static const char * const cs42l42_wnf3_freq_text[] = {
"160Hz", "180Hz", "200Hz", "220Hz",
"240Hz", "260Hz", "280Hz", "300Hz"
};
static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
CS42L42_ADC_WNF_CF_SHIFT,
cs42l42_wnf3_freq_text);
static const struct snd_kcontrol_new cs42l42_snd_controls[] = {
/* ADC Volume and Filter Controls */
SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL,
CS42L42_ADC_NOTCH_DIS_SHIFT, true, true),
SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL,
CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false),
SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL,
CS42L42_ADC_INV_SHIFT, true, false),
SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL,
CS42L42_ADC_DIG_BOOST_SHIFT, true, false),
SOC_SINGLE_S8_TLV("ADC Volume", CS42L42_ADC_VOLUME, -97, 12, adc_tlv),
SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL,
CS42L42_ADC_WNF_EN_SHIFT, true, false),
SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL,
CS42L42_ADC_HPF_EN_SHIFT, true, false),
SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum),
SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum),
/* DAC Volume and Filter Controls */
SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1,
CS42L42_DACA_INV_SHIFT, true, false),
SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1,
CS42L42_DACB_INV_SHIFT, true, false),
SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2,
CS42L42_DAC_HPF_EN_SHIFT, true, false),
SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL,
CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT,
0x3f, 1, mixer_tlv),
SOC_SINGLE_EXT("Slow Start Switch", CS42L42_SLOW_START_ENABLE,
CS42L42_SLOW_START_EN_SHIFT, true, false,
snd_soc_get_volsw, cs42l42_slow_start_put),
};
static int cs42l42_hp_adc_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
cs42l42->hp_adc_up_pending = true;
break;
case SND_SOC_DAPM_POST_PMU:
/* Only need one delay if HP and ADC are both powering-up */
if (cs42l42->hp_adc_up_pending) {
usleep_range(CS42L42_HP_ADC_EN_TIME_US,
CS42L42_HP_ADC_EN_TIME_US + 1000);
cs42l42->hp_adc_up_pending = false;
}
break;
default:
break;
}
return 0;
}
static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = {
/* Playback Path */
SND_SOC_DAPM_OUTPUT("HP"),
SND_SOC_DAPM_DAC_E("DAC", NULL, CS42L42_PWR_CTL1, CS42L42_HP_PDN_SHIFT, 1,
cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_MIXER("MIXER", CS42L42_PWR_CTL1, CS42L42_MIXER_PDN_SHIFT, 1, NULL, 0),
SND_SOC_DAPM_AIF_IN("SDIN1", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("SDIN2", NULL, 1, SND_SOC_NOPM, 0, 0),
/* Playback Requirements */
SND_SOC_DAPM_SUPPLY("ASP DAI0", CS42L42_PWR_CTL1, CS42L42_ASP_DAI_PDN_SHIFT, 1, NULL, 0),
/* Capture Path */
SND_SOC_DAPM_INPUT("HS"),
SND_SOC_DAPM_ADC_E("ADC", NULL, CS42L42_PWR_CTL1, CS42L42_ADC_PDN_SHIFT, 1,
cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_AIF_OUT("SDOUT1", NULL, 0, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH1_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SDOUT2", NULL, 1, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH2_SHIFT, 0),
/* Capture Requirements */
SND_SOC_DAPM_SUPPLY("ASP DAO0", CS42L42_PWR_CTL1, CS42L42_ASP_DAO_PDN_SHIFT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("ASP TX EN", CS42L42_ASP_TX_SZ_EN, CS42L42_ASP_TX_EN_SHIFT, 0, NULL, 0),
/* Playback/Capture Requirements */
SND_SOC_DAPM_SUPPLY("SCLK", CS42L42_ASP_CLK_CFG, CS42L42_ASP_SCLK_EN_SHIFT, 0, NULL, 0),
/* Soundwire SRC power control */
SND_SOC_DAPM_PGA("DACSRC", CS42L42_PWR_CTL2, CS42L42_DAC_SRC_PDNB_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ADCSRC", CS42L42_PWR_CTL2, CS42L42_ADC_SRC_PDNB_SHIFT, 0, NULL, 0),
};
static const struct snd_soc_dapm_route cs42l42_audio_map[] = {
/* Playback Path */
{"HP", NULL, "DAC"},
{"DAC", NULL, "MIXER"},
{"MIXER", NULL, "SDIN1"},
{"MIXER", NULL, "SDIN2"},
{"SDIN1", NULL, "Playback"},
{"SDIN2", NULL, "Playback"},
/* Playback Requirements */
{"SDIN1", NULL, "ASP DAI0"},
{"SDIN2", NULL, "ASP DAI0"},
{"SDIN1", NULL, "SCLK"},
{"SDIN2", NULL, "SCLK"},
/* Capture Path */
{"ADC", NULL, "HS"},
{ "SDOUT1", NULL, "ADC" },
{ "SDOUT2", NULL, "ADC" },
{ "Capture", NULL, "SDOUT1" },
{ "Capture", NULL, "SDOUT2" },
/* Capture Requirements */
{ "SDOUT1", NULL, "ASP DAO0" },
{ "SDOUT2", NULL, "ASP DAO0" },
{ "SDOUT1", NULL, "SCLK" },
{ "SDOUT2", NULL, "SCLK" },
{ "SDOUT1", NULL, "ASP TX EN" },
{ "SDOUT2", NULL, "ASP TX EN" },
};
static int cs42l42_set_jack(struct snd_soc_component *component, struct snd_soc_jack *jk, void *d)
{
struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
/* Prevent race with interrupt handler */
mutex_lock(&cs42l42->irq_lock);
cs42l42->jack = jk;
if (jk) {
switch (cs42l42->hs_type) {
case CS42L42_PLUG_CTIA:
case CS42L42_PLUG_OMTP:
snd_soc_jack_report(jk, SND_JACK_HEADSET, SND_JACK_HEADSET);
break;
case CS42L42_PLUG_HEADPHONE:
snd_soc_jack_report(jk, SND_JACK_HEADPHONE, SND_JACK_HEADPHONE);
break;
default:
break;
}
}
mutex_unlock(&cs42l42->irq_lock);
return 0;
}
const struct snd_soc_component_driver cs42l42_soc_component = {
.set_jack = cs42l42_set_jack,
.dapm_widgets = cs42l42_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(cs42l42_dapm_widgets),
.dapm_routes = cs42l42_audio_map,
.num_dapm_routes = ARRAY_SIZE(cs42l42_audio_map),
.controls = cs42l42_snd_controls,
.num_controls = ARRAY_SIZE(cs42l42_snd_controls),
.endianness = 1,
};
EXPORT_SYMBOL_NS_GPL(cs42l42_soc_component, SND_SOC_CS42L42_CORE);
/* Switch to SCLK. Atomic delay after the write to allow the switch to complete. */
static const struct reg_sequence cs42l42_to_sclk_seq[] = {
{
.reg = CS42L42_OSC_SWITCH,
.def = CS42L42_SCLK_PRESENT_MASK,
.delay_us = CS42L42_CLOCK_SWITCH_DELAY_US,
},
};
/* Switch to OSC. Atomic delay after the write to allow the switch to complete. */
static const struct reg_sequence cs42l42_to_osc_seq[] = {
{
.reg = CS42L42_OSC_SWITCH,
.def = 0,
.delay_us = CS42L42_CLOCK_SWITCH_DELAY_US,
},
};
struct cs42l42_pll_params {
u32 sclk;
u8 mclk_src_sel;
u8 sclk_prediv;
u8 pll_div_int;
u32 pll_div_frac;
u8 pll_mode;
u8 pll_divout;
u32 mclk_int;
u8 pll_cal_ratio;
u8 n;
};
/*
* Common PLL Settings for given SCLK
* Table 4-5 from the Datasheet
*/
static const struct cs42l42_pll_params pll_ratio_table[] = {
{ 1411200, 1, 0x00, 0x80, 0x000000, 0x03, 0x10, 11289600, 128, 2},
{ 1536000, 1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125, 2},
{ 2304000, 1, 0x00, 0x55, 0xC00000, 0x02, 0x10, 12288000, 85, 2},
{ 2400000, 1, 0x00, 0x50, 0x000000, 0x03, 0x10, 12000000, 80, 2},
{ 2822400, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
{ 3000000, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
{ 3072000, 1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1},
{ 4000000, 1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000, 96, 1},
{ 4096000, 1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000, 94, 1},
{ 4800000, 1, 0x01, 0x50, 0x000000, 0x03, 0x10, 12000000, 80, 2},
{ 4800000, 1, 0x01, 0x50, 0x000000, 0x01, 0x10, 12288000, 82, 2},
{ 5644800, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
{ 6000000, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
{ 6144000, 1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1},
{ 6144000, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12288000, 128, 1},
{ 9600000, 1, 0x02, 0x50, 0x000000, 0x03, 0x10, 12000000, 80, 2},
{ 9600000, 1, 0x02, 0x50, 0x000000, 0x01, 0x10, 12288000, 82, 2},
{ 11289600, 0, 0, 0, 0, 0, 0, 11289600, 0, 1},
{ 12000000, 0, 0, 0, 0, 0, 0, 12000000, 0, 1},
{ 12288000, 0, 0, 0, 0, 0, 0, 12288000, 0, 1},
{ 19200000, 1, 0x03, 0x50, 0x000000, 0x03, 0x10, 12000000, 80, 2},
{ 19200000, 1, 0x03, 0x50, 0x000000, 0x01, 0x10, 12288000, 82, 2},
{ 22579200, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
{ 24000000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
{ 24576000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12288000, 128, 1}
};
int cs42l42_pll_config(struct snd_soc_component *component, unsigned int clk,
unsigned int sample_rate)
{
struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
int i;
/* Don't reconfigure if there is an audio stream running */
if (cs42l42->stream_use) {
if (pll_ratio_table[cs42l42->pll_config].sclk == clk)
return 0;
else
return -EBUSY;
}
for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
/* MCLKint must be a multiple of the sample rate */
if (pll_ratio_table[i].mclk_int % sample_rate)
continue;
if (pll_ratio_table[i].sclk == clk) {
cs42l42->pll_config = i;
/* Configure the internal sample rate */
snd_soc_component_update_bits(component, CS42L42_MCLK_CTL,
CS42L42_INTERNAL_FS_MASK,
((pll_ratio_table[i].mclk_int !=
12000000) &&
(pll_ratio_table[i].mclk_int !=
24000000)) <<
CS42L42_INTERNAL_FS_SHIFT);
if (pll_ratio_table[i].mclk_src_sel == 0) {
/* Pass the clock straight through */
snd_soc_component_update_bits(component,
CS42L42_PLL_CTL1,
CS42L42_PLL_START_MASK, 0);
} else {
/* Configure PLL per table 4-5 */
snd_soc_component_update_bits(component,
CS42L42_PLL_DIV_CFG1,
CS42L42_SCLK_PREDIV_MASK,
pll_ratio_table[i].sclk_prediv
<< CS42L42_SCLK_PREDIV_SHIFT);
snd_soc_component_update_bits(component,
CS42L42_PLL_DIV_INT,
CS42L42_PLL_DIV_INT_MASK,
pll_ratio_table[i].pll_div_int
<< CS42L42_PLL_DIV_INT_SHIFT);
snd_soc_component_update_bits(component,
CS42L42_PLL_DIV_FRAC0,
CS42L42_PLL_DIV_FRAC_MASK,
CS42L42_FRAC0_VAL(
pll_ratio_table[i].pll_div_frac)
<< CS42L42_PLL_DIV_FRAC_SHIFT);
snd_soc_component_update_bits(component,
CS42L42_PLL_DIV_FRAC1,
CS42L42_PLL_DIV_FRAC_MASK,
CS42L42_FRAC1_VAL(
pll_ratio_table[i].pll_div_frac)
<< CS42L42_PLL_DIV_FRAC_SHIFT);
snd_soc_component_update_bits(component,
CS42L42_PLL_DIV_FRAC2,
CS42L42_PLL_DIV_FRAC_MASK,
CS42L42_FRAC2_VAL(
pll_ratio_table[i].pll_div_frac)
<< CS42L42_PLL_DIV_FRAC_SHIFT);
snd_soc_component_update_bits(component,
CS42L42_PLL_CTL4,
CS42L42_PLL_MODE_MASK,
pll_ratio_table[i].pll_mode
<< CS42L42_PLL_MODE_SHIFT);
snd_soc_component_update_bits(component,
CS42L42_PLL_CTL3,
CS42L42_PLL_DIVOUT_MASK,
(pll_ratio_table[i].pll_divout * pll_ratio_table[i].n)
<< CS42L42_PLL_DIVOUT_SHIFT);
snd_soc_component_update_bits(component,
CS42L42_PLL_CAL_RATIO,
CS42L42_PLL_CAL_RATIO_MASK,
pll_ratio_table[i].pll_cal_ratio
<< CS42L42_PLL_CAL_RATIO_SHIFT);
}
return 0;
}
}
return -EINVAL;
}
EXPORT_SYMBOL_NS_GPL(cs42l42_pll_config, SND_SOC_CS42L42_CORE);
void cs42l42_src_config(struct snd_soc_component *component, unsigned int sample_rate)
{
struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
unsigned int fs;
/* Don't reconfigure if there is an audio stream running */
if (cs42l42->stream_use)
return;
/* SRC MCLK must be as close as possible to 125 * sample rate */
if (sample_rate <= 48000)
fs = CS42L42_CLK_IASRC_SEL_6;
else
fs = CS42L42_CLK_IASRC_SEL_12;
/* Set the sample rates (96k or lower) */
snd_soc_component_update_bits(component,
CS42L42_FS_RATE_EN,
CS42L42_FS_EN_MASK,
(CS42L42_FS_EN_IASRC_96K |
CS42L42_FS_EN_OASRC_96K) <<
CS42L42_FS_EN_SHIFT);
snd_soc_component_update_bits(component,
CS42L42_IN_ASRC_CLK,
CS42L42_CLK_IASRC_SEL_MASK,
fs << CS42L42_CLK_IASRC_SEL_SHIFT);
snd_soc_component_update_bits(component,
CS42L42_OUT_ASRC_CLK,
CS42L42_CLK_OASRC_SEL_MASK,
fs << CS42L42_CLK_OASRC_SEL_SHIFT);
}
EXPORT_SYMBOL_NS_GPL(cs42l42_src_config, SND_SOC_CS42L42_CORE);
static int cs42l42_asp_config(struct snd_soc_component *component,
unsigned int sclk, unsigned int sample_rate)
{
u32 fsync = sclk / sample_rate;
/* Set up the LRCLK */
if (((fsync * sample_rate) != sclk) || ((fsync % 2) != 0)) {
dev_err(component->dev,
"Unsupported sclk %d/sample rate %d\n",
sclk,
sample_rate);
return -EINVAL;
}
/* Set the LRCLK period */
snd_soc_component_update_bits(component,
CS42L42_FSYNC_P_LOWER,
CS42L42_FSYNC_PERIOD_MASK,
CS42L42_FRAC0_VAL(fsync - 1) <<
CS42L42_FSYNC_PERIOD_SHIFT);
snd_soc_component_update_bits(component,
CS42L42_FSYNC_P_UPPER,
CS42L42_FSYNC_PERIOD_MASK,
CS42L42_FRAC1_VAL(fsync - 1) <<
CS42L42_FSYNC_PERIOD_SHIFT);
/* Set the LRCLK to 50% duty cycle */
fsync = fsync / 2;
snd_soc_component_update_bits(component,
CS42L42_FSYNC_PW_LOWER,
CS42L42_FSYNC_PULSE_WIDTH_MASK,
CS42L42_FRAC0_VAL(fsync - 1) <<
CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
snd_soc_component_update_bits(component,
CS42L42_FSYNC_PW_UPPER,
CS42L42_FSYNC_PULSE_WIDTH_MASK,
CS42L42_FRAC1_VAL(fsync - 1) <<
CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
return 0;
}
static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
u32 asp_cfg_val = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFM:
asp_cfg_val |= CS42L42_ASP_MASTER_MODE <<
CS42L42_ASP_MODE_SHIFT;
break;
case SND_SOC_DAIFMT_CBS_CFS:
asp_cfg_val |= CS42L42_ASP_SLAVE_MODE <<
CS42L42_ASP_MODE_SHIFT;
break;
default:
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
/*
* 5050 mode, frame starts on falling edge of LRCLK,
* frame delayed by 1.0 SCLKs
*/
snd_soc_component_update_bits(component,
CS42L42_ASP_FRM_CFG,
CS42L42_ASP_STP_MASK |
CS42L42_ASP_5050_MASK |
CS42L42_ASP_FSD_MASK,
CS42L42_ASP_5050_MASK |
(CS42L42_ASP_FSD_1_0 <<
CS42L42_ASP_FSD_SHIFT));
break;
default:
return -EINVAL;
}
/* Bitclock/frame inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
break;
case SND_SOC_DAIFMT_NB_IF:
asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
break;
case SND_SOC_DAIFMT_IB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
break;
}
snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG, CS42L42_ASP_MODE_MASK |
CS42L42_ASP_SCPOL_MASK |
CS42L42_ASP_LCPOL_MASK,
asp_cfg_val);
return 0;
}
static int cs42l42_dai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
/*
* Sample rates < 44.1 kHz would produce an out-of-range SCLK with
* a standard I2S frame. If the machine driver sets SCLK it must be
* legal.
*/
if (cs42l42->sclk)
return 0;
/* Machine driver has not set a SCLK, limit bottom end to 44.1 kHz */
return snd_pcm_hw_constraint_minmax(substream->runtime,
SNDRV_PCM_HW_PARAM_RATE,
44100, 96000);
}
static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
unsigned int channels = params_channels(params);
unsigned int width = (params_width(params) / 8) - 1;
unsigned int sample_rate = params_rate(params);
unsigned int slot_width = 0;
unsigned int val = 0;
unsigned int bclk;
int ret;
if (cs42l42->bclk_ratio) {
/* machine driver has set the BCLK/samp-rate ratio */
bclk = cs42l42->bclk_ratio * params_rate(params);
} else if (cs42l42->sclk) {
/* machine driver has set the SCLK */
bclk = cs42l42->sclk;
} else {
/*
* Assume 24-bit samples are in 32-bit slots, to prevent SCLK being
* more than assumed (which would result in overclocking).
*/
if (params_width(params) == 24)
slot_width = 32;
/* I2S frame always has multiple of 2 channels */
bclk = snd_soc_tdm_params_to_bclk(params, slot_width, 0, 2);
}
switch (substream->stream) {
case SNDRV_PCM_STREAM_CAPTURE:
/* channel 2 on high LRCLK */
val = CS42L42_ASP_TX_CH2_AP_MASK |
(width << CS42L42_ASP_TX_CH2_RES_SHIFT) |
(width << CS42L42_ASP_TX_CH1_RES_SHIFT);
snd_soc_component_update_bits(component, CS42L42_ASP_TX_CH_AP_RES,
CS42L42_ASP_TX_CH1_AP_MASK | CS42L42_ASP_TX_CH2_AP_MASK |
CS42L42_ASP_TX_CH2_RES_MASK | CS42L42_ASP_TX_CH1_RES_MASK, val);
break;
case SNDRV_PCM_STREAM_PLAYBACK:
val |= width << CS42L42_ASP_RX_CH_RES_SHIFT;
/* channel 1 on low LRCLK */
snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH1_AP_RES,
CS42L42_ASP_RX_CH_AP_MASK |
CS42L42_ASP_RX_CH_RES_MASK, val);
/* Channel 2 on high LRCLK */
val |= CS42L42_ASP_RX_CH_AP_HI << CS42L42_ASP_RX_CH_AP_SHIFT;
snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH2_AP_RES,
CS42L42_ASP_RX_CH_AP_MASK |
CS42L42_ASP_RX_CH_RES_MASK, val);
/* Channel B comes from the last active channel */
snd_soc_component_update_bits(component, CS42L42_SP_RX_CH_SEL,
CS42L42_SP_RX_CHB_SEL_MASK,
(channels - 1) << CS42L42_SP_RX_CHB_SEL_SHIFT);
/* Both LRCLK slots must be enabled */
snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN,
CS42L42_ASP_RX0_CH_EN_MASK,
BIT(CS42L42_ASP_RX0_CH1_SHIFT) |
BIT(CS42L42_ASP_RX0_CH2_SHIFT));
break;
default:
break;
}
ret = cs42l42_pll_config(component, bclk, sample_rate);
if (ret)
return ret;
ret = cs42l42_asp_config(component, bclk, sample_rate);
if (ret)
return ret;
cs42l42_src_config(component, sample_rate);
return 0;
}
static int cs42l42_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
int i;
if (freq == 0) {
cs42l42->sclk = 0;
return 0;
}
for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
if (pll_ratio_table[i].sclk == freq) {
cs42l42->sclk = freq;
return 0;
}
}
dev_err(component->dev, "SCLK %u not supported\n", freq);
return -EINVAL;
}
static int cs42l42_set_bclk_ratio(struct snd_soc_dai *dai,
unsigned int bclk_ratio)
{
struct snd_soc_component *component = dai->component;
struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
cs42l42->bclk_ratio = bclk_ratio;
return 0;
}
int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
{
struct snd_soc_component *component = dai->component;
struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
unsigned int regval;
int ret;
if (mute) {
/* Mute the headphone */
if (stream == SNDRV_PCM_STREAM_PLAYBACK)
snd_soc_component_update_bits(component, CS42L42_HP_CTL,
CS42L42_HP_ANA_AMUTE_MASK |
CS42L42_HP_ANA_BMUTE_MASK,
CS42L42_HP_ANA_AMUTE_MASK |
CS42L42_HP_ANA_BMUTE_MASK);
cs42l42->stream_use &= ~(1 << stream);
if (!cs42l42->stream_use) {
/*
* Switch to the internal oscillator.
* SCLK must remain running until after this clock switch.
* Without a source of clock the I2C bus doesn't work.
*/
regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_osc_seq,
ARRAY_SIZE(cs42l42_to_osc_seq));
/* Must disconnect PLL before stopping it */
snd_soc_component_update_bits(component,
CS42L42_MCLK_SRC_SEL,
CS42L42_MCLK_SRC_SEL_MASK,
0);
usleep_range(100, 200);
snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
CS42L42_PLL_START_MASK, 0);
}
} else {
if (!cs42l42->stream_use) {
/* SCLK must be running before codec unmute.
*
* PLL must not be started with ADC and HP both off
* otherwise the FILT+ supply will not charge properly.
* DAPM widgets power-up before stream unmute so at least
* one of the "DAC" or "ADC" widgets will already have
* powered-up.
*/
if (pll_ratio_table[cs42l42->pll_config].mclk_src_sel) {
snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
CS42L42_PLL_START_MASK, 1);
if (pll_ratio_table[cs42l42->pll_config].n > 1) {
usleep_range(CS42L42_PLL_DIVOUT_TIME_US,
CS42L42_PLL_DIVOUT_TIME_US * 2);
regval = pll_ratio_table[cs42l42->pll_config].pll_divout;
snd_soc_component_update_bits(component, CS42L42_PLL_CTL3,
CS42L42_PLL_DIVOUT_MASK,
regval <<
CS42L42_PLL_DIVOUT_SHIFT);
}
ret = regmap_read_poll_timeout(cs42l42->regmap,
CS42L42_PLL_LOCK_STATUS,
regval,
(regval & 1),
CS42L42_PLL_LOCK_POLL_US,
CS42L42_PLL_LOCK_TIMEOUT_US);
if (ret < 0)
dev_warn(component->dev, "PLL failed to lock: %d\n", ret);
/* PLL must be running to drive glitchless switch logic */
snd_soc_component_update_bits(component,
CS42L42_MCLK_SRC_SEL,
CS42L42_MCLK_SRC_SEL_MASK,
CS42L42_MCLK_SRC_SEL_MASK);
}
/* Mark SCLK as present, turn off internal oscillator */
regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_sclk_seq,
ARRAY_SIZE(cs42l42_to_sclk_seq));
}
cs42l42->stream_use |= 1 << stream;
if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
/* Un-mute the headphone */
snd_soc_component_update_bits(component, CS42L42_HP_CTL,
CS42L42_HP_ANA_AMUTE_MASK |
CS42L42_HP_ANA_BMUTE_MASK,
0);
}
}
return 0;
}
EXPORT_SYMBOL_NS_GPL(cs42l42_mute_stream, SND_SOC_CS42L42_CORE);
#define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops cs42l42_ops = {
.startup = cs42l42_dai_startup,
.hw_params = cs42l42_pcm_hw_params,
.set_fmt = cs42l42_set_dai_fmt,
.set_sysclk = cs42l42_set_sysclk,
.set_bclk_ratio = cs42l42_set_bclk_ratio,
.mute_stream = cs42l42_mute_stream,
};
struct snd_soc_dai_driver cs42l42_dai = {
.name = "cs42l42",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = CS42L42_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = CS42L42_FORMATS,
},
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
.ops = &cs42l42_ops,
};
EXPORT_SYMBOL_NS_GPL(cs42l42_dai, SND_SOC_CS42L42_CORE);
static void cs42l42_manual_hs_type_detect(struct cs42l42_private *cs42l42)
{
unsigned int hs_det_status;
unsigned int hs_det_comp1;
unsigned int hs_det_comp2;
unsigned int hs_det_sw;
/* Set hs detect to manual, active mode */
regmap_update_bits(cs42l42->regmap,
CS42L42_HSDET_CTL2,
CS42L42_HSDET_CTRL_MASK |
CS42L42_HSDET_SET_MASK |
CS42L42_HSBIAS_REF_MASK |
CS42L42_HSDET_AUTO_TIME_MASK,
(1 << CS42L42_HSDET_CTRL_SHIFT) |
(0 << CS42L42_HSDET_SET_SHIFT) |
(0 << CS42L42_HSBIAS_REF_SHIFT) |
(0 << CS42L42_HSDET_AUTO_TIME_SHIFT));
/* Configure HS DET comparator reference levels. */
regmap_update_bits(cs42l42->regmap,
CS42L42_HSDET_CTL1,
CS42L42_HSDET_COMP1_LVL_MASK |
CS42L42_HSDET_COMP2_LVL_MASK,
(CS42L42_HSDET_COMP1_LVL_VAL << CS42L42_HSDET_COMP1_LVL_SHIFT) |
(CS42L42_HSDET_COMP2_LVL_VAL << CS42L42_HSDET_COMP2_LVL_SHIFT));
/* Open the SW_HSB_HS3 switch and close SW_HSB_HS4 for a Type 1 headset. */
regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP1);
msleep(100);
regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
hs_det_comp1 = (hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >>
CS42L42_HSDET_COMP1_OUT_SHIFT;
hs_det_comp2 = (hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >>
CS42L42_HSDET_COMP2_OUT_SHIFT;
/* Close the SW_HSB_HS3 switch for a Type 2 headset. */
regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP2);
msleep(100);
regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
hs_det_comp1 |= ((hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >>
CS42L42_HSDET_COMP1_OUT_SHIFT) << 1;
hs_det_comp2 |= ((hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >>
CS42L42_HSDET_COMP2_OUT_SHIFT) << 1;
/* Use Comparator 1 with 1.25V Threshold. */
switch (hs_det_comp1) {
case CS42L42_HSDET_COMP_TYPE1:
cs42l42->hs_type = CS42L42_PLUG_CTIA;
hs_det_sw = CS42L42_HSDET_SW_TYPE1;
break;
case CS42L42_HSDET_COMP_TYPE2:
cs42l42->hs_type = CS42L42_PLUG_OMTP;
hs_det_sw = CS42L42_HSDET_SW_TYPE2;
break;
default:
/* Fallback to Comparator 2 with 1.75V Threshold. */
switch (hs_det_comp2) {
case CS42L42_HSDET_COMP_TYPE1:
cs42l42->hs_type = CS42L42_PLUG_CTIA;
hs_det_sw = CS42L42_HSDET_SW_TYPE1;
break;
case CS42L42_HSDET_COMP_TYPE2:
cs42l42->hs_type = CS42L42_PLUG_OMTP;
hs_det_sw = CS42L42_HSDET_SW_TYPE2;
break;
/* Detect Type 3 and Type 4 Headsets as Headphones */
default:
cs42l42->hs_type = CS42L42_PLUG_HEADPHONE;
hs_det_sw = CS42L42_HSDET_SW_TYPE3;
break;
}
}
/* Set Switches */
regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, hs_det_sw);
/* Set HSDET mode to Manual—Disabled */
regmap_update_bits(cs42l42->regmap,
CS42L42_HSDET_CTL2,
CS42L42_HSDET_CTRL_MASK |
CS42L42_HSDET_SET_MASK |
CS42L42_HSBIAS_REF_MASK |
CS42L42_HSDET_AUTO_TIME_MASK,
(0 << CS42L42_HSDET_CTRL_SHIFT) |
(0 << CS42L42_HSDET_SET_SHIFT) |
(0 << CS42L42_HSBIAS_REF_SHIFT) |
(0 << CS42L42_HSDET_AUTO_TIME_SHIFT));
/* Configure HS DET comparator reference levels. */
regmap_update_bits(cs42l42->regmap,
CS42L42_HSDET_CTL1,
CS42L42_HSDET_COMP1_LVL_MASK |
CS42L42_HSDET_COMP2_LVL_MASK,
(CS42L42_HSDET_COMP1_LVL_DEFAULT << CS42L42_HSDET_COMP1_LVL_SHIFT) |
(CS42L42_HSDET_COMP2_LVL_DEFAULT << CS42L42_HSDET_COMP2_LVL_SHIFT));
}
static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42)
{
unsigned int hs_det_status;
unsigned int int_status;
/* Read and save the hs detection result */
regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
/* Mask the auto detect interrupt */
regmap_update_bits(cs42l42->regmap,
CS42L42_CODEC_INT_MASK,
CS42L42_PDN_DONE_MASK |
CS42L42_HSDET_AUTO_DONE_MASK,
(1 << CS42L42_PDN_DONE_SHIFT) |
(1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >>
CS42L42_HSDET_TYPE_SHIFT;
/* Set hs detect to automatic, disabled mode */
regmap_update_bits(cs42l42->regmap,
CS42L42_HSDET_CTL2,
CS42L42_HSDET_CTRL_MASK |
CS42L42_HSDET_SET_MASK |
CS42L42_HSBIAS_REF_MASK |
CS42L42_HSDET_AUTO_TIME_MASK,
(2 << CS42L42_HSDET_CTRL_SHIFT) |
(2 << CS42L42_HSDET_SET_SHIFT) |
(0 << CS42L42_HSBIAS_REF_SHIFT) |
(3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
/* Run Manual detection if auto detect has not found a headset.
* We Re-Run with Manual Detection if the original detection was invalid or headphones,
* to ensure that a headset mic is detected in all cases.
*/
if (cs42l42->hs_type == CS42L42_PLUG_INVALID ||
cs42l42->hs_type == CS42L42_PLUG_HEADPHONE) {
dev_dbg(cs42l42->dev, "Running Manual Detection Fallback\n");
cs42l42_manual_hs_type_detect(cs42l42);
}
/* Set up button detection */
if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) ||
(cs42l42->hs_type == CS42L42_PLUG_OMTP)) {
/* Set auto HS bias settings to default */
regmap_update_bits(cs42l42->regmap,
CS42L42_HSBIAS_SC_AUTOCTL,
CS42L42_HSBIAS_SENSE_EN_MASK |
CS42L42_AUTO_HSBIAS_HIZ_MASK |
CS42L42_TIP_SENSE_EN_MASK |
CS42L42_HSBIAS_SENSE_TRIP_MASK,
(0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
(0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
(0 << CS42L42_TIP_SENSE_EN_SHIFT) |
(3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
/* Set up hs detect level sensitivity */
regmap_update_bits(cs42l42->regmap,
CS42L42_MIC_DET_CTL1,
CS42L42_LATCH_TO_VP_MASK |
CS42L42_EVENT_STAT_SEL_MASK |
CS42L42_HS_DET_LEVEL_MASK,
(1 << CS42L42_LATCH_TO_VP_SHIFT) |
(0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
(cs42l42->bias_thresholds[0] <<
CS42L42_HS_DET_LEVEL_SHIFT));
/* Set auto HS bias settings to default */
regmap_update_bits(cs42l42->regmap,
CS42L42_HSBIAS_SC_AUTOCTL,
CS42L42_HSBIAS_SENSE_EN_MASK |
CS42L42_AUTO_HSBIAS_HIZ_MASK |
CS42L42_TIP_SENSE_EN_MASK |
CS42L42_HSBIAS_SENSE_TRIP_MASK,
(cs42l42->hs_bias_sense_en << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
(1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
(0 << CS42L42_TIP_SENSE_EN_SHIFT) |
(3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
/* Turn on level detect circuitry */
regmap_update_bits(cs42l42->regmap,
CS42L42_MISC_DET_CTL,
CS42L42_HSBIAS_CTL_MASK |
CS42L42_PDN_MIC_LVL_DET_MASK,
(3 << CS42L42_HSBIAS_CTL_SHIFT) |
(0 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
msleep(cs42l42->btn_det_init_dbnce);
/* Clear any button interrupts before unmasking them */
regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
&int_status);
/* Unmask button detect interrupts */
regmap_update_bits(cs42l42->regmap,
CS42L42_DET_INT2_MASK,
CS42L42_M_DETECT_TF_MASK |
CS42L42_M_DETECT_FT_MASK |
CS42L42_M_HSBIAS_HIZ_MASK |
CS42L42_M_SHORT_RLS_MASK |
CS42L42_M_SHORT_DET_MASK,
(0 << CS42L42_M_DETECT_TF_SHIFT) |
(0 << CS42L42_M_DETECT_FT_SHIFT) |
(0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
(1 << CS42L42_M_SHORT_RLS_SHIFT) |
(1 << CS42L42_M_SHORT_DET_SHIFT));
} else {
/* Make sure button detect and HS bias circuits are off */
regmap_update_bits(cs42l42->regmap,
CS42L42_MISC_DET_CTL,
CS42L42_HSBIAS_CTL_MASK |
CS42L42_PDN_MIC_LVL_DET_MASK,
(1 << CS42L42_HSBIAS_CTL_SHIFT) |
(1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
}
regmap_update_bits(cs42l42->regmap,
CS42L42_DAC_CTL2,
CS42L42_HPOUT_PULLDOWN_MASK |
CS42L42_HPOUT_LOAD_MASK |
CS42L42_HPOUT_CLAMP_MASK |
CS42L42_DAC_HPF_EN_MASK |
CS42L42_DAC_MON_EN_MASK,
(0 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
(0 << CS42L42_HPOUT_LOAD_SHIFT) |
(0 << CS42L42_HPOUT_CLAMP_SHIFT) |
(1 << CS42L42_DAC_HPF_EN_SHIFT) |
(0 << CS42L42_DAC_MON_EN_SHIFT));
/* Unmask tip sense interrupts */
regmap_update_bits(cs42l42->regmap,
CS42L42_TSRS_PLUG_INT_MASK,
CS42L42_TS_PLUG_MASK |
CS42L42_TS_UNPLUG_MASK,
(0 << CS42L42_TS_PLUG_SHIFT) |
(0 << CS42L42_TS_UNPLUG_SHIFT));
}
static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42)
{
/* Mask tip sense interrupts */
regmap_update_bits(cs42l42->regmap,
CS42L42_TSRS_PLUG_INT_MASK,
CS42L42_TS_PLUG_MASK |
CS42L42_TS_UNPLUG_MASK,
(1 << CS42L42_TS_PLUG_SHIFT) |
(1 << CS42L42_TS_UNPLUG_SHIFT));
/* Make sure button detect and HS bias circuits are off */
regmap_update_bits(cs42l42->regmap,
CS42L42_MISC_DET_CTL,
CS42L42_HSBIAS_CTL_MASK |
CS42L42_PDN_MIC_LVL_DET_MASK,
(1 << CS42L42_HSBIAS_CTL_SHIFT) |
(1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
/* Set auto HS bias settings to default */
regmap_update_bits(cs42l42->regmap,
CS42L42_HSBIAS_SC_AUTOCTL,
CS42L42_HSBIAS_SENSE_EN_MASK |
CS42L42_AUTO_HSBIAS_HIZ_MASK |
CS42L42_TIP_SENSE_EN_MASK |
CS42L42_HSBIAS_SENSE_TRIP_MASK,
(0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
(0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
(0 << CS42L42_TIP_SENSE_EN_SHIFT) |
(3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
/* Set hs detect to manual, disabled mode */
regmap_update_bits(cs42l42->regmap,
CS42L42_HSDET_CTL2,
CS42L42_HSDET_CTRL_MASK |
CS42L42_HSDET_SET_MASK |
CS42L42_HSBIAS_REF_MASK |
CS42L42_HSDET_AUTO_TIME_MASK,
(0 << CS42L42_HSDET_CTRL_SHIFT) |
(2 << CS42L42_HSDET_SET_SHIFT) |
(0 << CS42L42_HSBIAS_REF_SHIFT) |
(3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
regmap_update_bits(cs42l42->regmap,
CS42L42_DAC_CTL2,
CS42L42_HPOUT_PULLDOWN_MASK |
CS42L42_HPOUT_LOAD_MASK |
CS42L42_HPOUT_CLAMP_MASK |
CS42L42_DAC_HPF_EN_MASK |
CS42L42_DAC_MON_EN_MASK,
(8 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
(0 << CS42L42_HPOUT_LOAD_SHIFT) |
(1 << CS42L42_HPOUT_CLAMP_SHIFT) |
(1 << CS42L42_DAC_HPF_EN_SHIFT) |
(1 << CS42L42_DAC_MON_EN_SHIFT));
/* Power up HS bias to 2.7V */
regmap_update_bits(cs42l42->regmap,
CS42L42_MISC_DET_CTL,
CS42L42_HSBIAS_CTL_MASK |
CS42L42_PDN_MIC_LVL_DET_MASK,
(3 << CS42L42_HSBIAS_CTL_SHIFT) |
(1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
/* Wait for HS bias to ramp up */
msleep(cs42l42->hs_bias_ramp_time);
/* Unmask auto detect interrupt */
regmap_update_bits(cs42l42->regmap,
CS42L42_CODEC_INT_MASK,
CS42L42_PDN_DONE_MASK |
CS42L42_HSDET_AUTO_DONE_MASK,
(1 << CS42L42_PDN_DONE_SHIFT) |
(0 << CS42L42_HSDET_AUTO_DONE_SHIFT));
/* Set hs detect to automatic, enabled mode */
regmap_update_bits(cs42l42->regmap,
CS42L42_HSDET_CTL2,
CS42L42_HSDET_CTRL_MASK |
CS42L42_HSDET_SET_MASK |
CS42L42_HSBIAS_REF_MASK |
CS42L42_HSDET_AUTO_TIME_MASK,
(3 << CS42L42_HSDET_CTRL_SHIFT) |
(2 << CS42L42_HSDET_SET_SHIFT) |
(0 << CS42L42_HSBIAS_REF_SHIFT) |
(3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
}
static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42)
{
/* Mask button detect interrupts */
regmap_update_bits(cs42l42->regmap,
CS42L42_DET_INT2_MASK,
CS42L42_M_DETECT_TF_MASK |
CS42L42_M_DETECT_FT_MASK |
CS42L42_M_HSBIAS_HIZ_MASK |
CS42L42_M_SHORT_RLS_MASK |
CS42L42_M_SHORT_DET_MASK,
(1 << CS42L42_M_DETECT_TF_SHIFT) |
(1 << CS42L42_M_DETECT_FT_SHIFT) |
(1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
(1 << CS42L42_M_SHORT_RLS_SHIFT) |
(1 << CS42L42_M_SHORT_DET_SHIFT));
/* Ground HS bias */
regmap_update_bits(cs42l42->regmap,
CS42L42_MISC_DET_CTL,
CS42L42_HSBIAS_CTL_MASK |
CS42L42_PDN_MIC_LVL_DET_MASK,
(1 << CS42L42_HSBIAS_CTL_SHIFT) |
(1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
/* Set auto HS bias settings to default */
regmap_update_bits(cs42l42->regmap,
CS42L42_HSBIAS_SC_AUTOCTL,
CS42L42_HSBIAS_SENSE_EN_MASK |
CS42L42_AUTO_HSBIAS_HIZ_MASK |
CS42L42_TIP_SENSE_EN_MASK |
CS42L42_HSBIAS_SENSE_TRIP_MASK,
(0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
(0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
(0 << CS42L42_TIP_SENSE_EN_SHIFT) |
(3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
/* Set hs detect to manual, disabled mode */
regmap_update_bits(cs42l42->regmap,
CS42L42_HSDET_CTL2,
CS42L42_HSDET_CTRL_MASK |
CS42L42_HSDET_SET_MASK |
CS42L42_HSBIAS_REF_MASK |
CS42L42_HSDET_AUTO_TIME_MASK,
(0 << CS42L42_HSDET_CTRL_SHIFT) |
(2 << CS42L42_HSDET_SET_SHIFT) |
(0 << CS42L42_HSBIAS_REF_SHIFT) |
(3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
}
static int cs42l42_handle_button_press(struct cs42l42_private *cs42l42)
{
int bias_level;
unsigned int detect_status;
/* Mask button detect interrupts */
regmap_update_bits(cs42l42->regmap,
CS42L42_DET_INT2_MASK,
CS42L42_M_DETECT_TF_MASK |
CS42L42_M_DETECT_FT_MASK |
CS42L42_M_HSBIAS_HIZ_MASK |
CS42L42_M_SHORT_RLS_MASK |
CS42L42_M_SHORT_DET_MASK,
(1 << CS42L42_M_DETECT_TF_SHIFT) |
(1 << CS42L42_M_DETECT_FT_SHIFT) |
(1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
(1 << CS42L42_M_SHORT_RLS_SHIFT) |
(1 << CS42L42_M_SHORT_DET_SHIFT));
usleep_range(cs42l42->btn_det_event_dbnce * 1000,
cs42l42->btn_det_event_dbnce * 2000);
/* Test all 4 level detect biases */
bias_level = 1;
do {
/* Adjust button detect level sensitivity */
regmap_update_bits(cs42l42->regmap,
CS42L42_MIC_DET_CTL1,
CS42L42_LATCH_TO_VP_MASK |
CS42L42_EVENT_STAT_SEL_MASK |
CS42L42_HS_DET_LEVEL_MASK,
(1 << CS42L42_LATCH_TO_VP_SHIFT) |
(0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
(cs42l42->bias_thresholds[bias_level] <<
CS42L42_HS_DET_LEVEL_SHIFT));
regmap_read(cs42l42->regmap, CS42L42_DET_STATUS2,
&detect_status);
} while ((detect_status & CS42L42_HS_TRUE_MASK) &&
(++bias_level < CS42L42_NUM_BIASES));
switch (bias_level) {
case 1: /* Function C button press */
bias_level = SND_JACK_BTN_2;
dev_dbg(cs42l42->dev, "Function C button press\n");
break;
case 2: /* Function B button press */
bias_level = SND_JACK_BTN_1;
dev_dbg(cs42l42->dev, "Function B button press\n");
break;
case 3: /* Function D button press */
bias_level = SND_JACK_BTN_3;
dev_dbg(cs42l42->dev, "Function D button press\n");
break;
case 4: /* Function A button press */
bias_level = SND_JACK_BTN_0;
dev_dbg(cs42l42->dev, "Function A button press\n");
break;
default:
bias_level = 0;
break;
}
/* Set button detect level sensitivity back to default */
regmap_update_bits(cs42l42->regmap,
CS42L42_MIC_DET_CTL1,
CS42L42_LATCH_TO_VP_MASK |
CS42L42_EVENT_STAT_SEL_MASK |
CS42L42_HS_DET_LEVEL_MASK,
(1 << CS42L42_LATCH_TO_VP_SHIFT) |
(0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
(cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT));
/* Clear any button interrupts before unmasking them */
regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
&detect_status);
/* Unmask button detect interrupts */
regmap_update_bits(cs42l42->regmap,
CS42L42_DET_INT2_MASK,
CS42L42_M_DETECT_TF_MASK |
CS42L42_M_DETECT_FT_MASK |
CS42L42_M_HSBIAS_HIZ_MASK |
CS42L42_M_SHORT_RLS_MASK |
CS42L42_M_SHORT_DET_MASK,
(0 << CS42L42_M_DETECT_TF_SHIFT) |
(0 << CS42L42_M_DETECT_FT_SHIFT) |
(0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
(1 << CS42L42_M_SHORT_RLS_SHIFT) |
(1 << CS42L42_M_SHORT_DET_SHIFT));
return bias_level;
}
struct cs42l42_irq_params {
u16 status_addr;
u16 mask_addr;
u8 mask;
};
static const struct cs42l42_irq_params irq_params_table[] = {
{CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK,
CS42L42_ADC_OVFL_VAL_MASK},
{CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK,
CS42L42_MIXER_VAL_MASK},
{CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK,
CS42L42_SRC_VAL_MASK},
{CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK,
CS42L42_ASP_RX_VAL_MASK},
{CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK,
CS42L42_ASP_TX_VAL_MASK},
{CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK,
CS42L42_CODEC_VAL_MASK},
{CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK,
CS42L42_DET_INT_VAL1_MASK},
{CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK,
CS42L42_DET_INT_VAL2_MASK},
{CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK,
CS42L42_SRCPL_VAL_MASK},
{CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK,
CS42L42_VPMON_VAL_MASK},
{CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK,
CS42L42_PLL_LOCK_VAL_MASK},
{CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK,
CS42L42_TSRS_PLUG_VAL_MASK}
};
irqreturn_t cs42l42_irq_thread(int irq, void *data)
{
struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data;
unsigned int stickies[12];
unsigned int masks[12];
unsigned int current_plug_status;
unsigned int current_button_status;
unsigned int i;
pm_runtime_get_sync(cs42l42->dev);
mutex_lock(&cs42l42->irq_lock);
if (cs42l42->suspended || !cs42l42->init_done) {
mutex_unlock(&cs42l42->irq_lock);
pm_runtime_put_autosuspend(cs42l42->dev);
return IRQ_NONE;
}
/* Read sticky registers to clear interurpt */
for (i = 0; i < ARRAY_SIZE(stickies); i++) {
regmap_read(cs42l42->regmap, irq_params_table[i].status_addr,
&(stickies[i]));
regmap_read(cs42l42->regmap, irq_params_table[i].mask_addr,
&(masks[i]));
stickies[i] = stickies[i] & (~masks[i]) &
irq_params_table[i].mask;
}
/* Read tip sense status before handling type detect */
current_plug_status = (stickies[11] &
(CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
CS42L42_TS_PLUG_SHIFT;
/* Read button sense status */
current_button_status = stickies[7] &
(CS42L42_M_DETECT_TF_MASK |
CS42L42_M_DETECT_FT_MASK |
CS42L42_M_HSBIAS_HIZ_MASK);
/*
* Check auto-detect status. Don't assume a previous unplug event has
* cleared the flags. If the jack is unplugged and plugged during
* system suspend there won't have been an unplug event.
*/
if ((~masks[5]) & irq_params_table[5].mask) {
if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) {
cs42l42_process_hs_type_detect(cs42l42);
switch (cs42l42->hs_type) {
case CS42L42_PLUG_CTIA:
case CS42L42_PLUG_OMTP:
snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADSET,
SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3);
break;
case CS42L42_PLUG_HEADPHONE:
snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADPHONE,
SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3);
break;
default:
break;
}
dev_dbg(cs42l42->dev, "Auto detect done (%d)\n", cs42l42->hs_type);
}
}
/* Check tip sense status */
if ((~masks[11]) & irq_params_table[11].mask) {
switch (current_plug_status) {
case CS42L42_TS_PLUG:
if (cs42l42->plug_state != CS42L42_TS_PLUG) {
cs42l42->plug_state = CS42L42_TS_PLUG;
cs42l42_init_hs_type_detect(cs42l42);
}
break;
case CS42L42_TS_UNPLUG:
if (cs42l42->plug_state != CS42L42_TS_UNPLUG) {
cs42l42->plug_state = CS42L42_TS_UNPLUG;
cs42l42_cancel_hs_type_detect(cs42l42);
snd_soc_jack_report(cs42l42->jack, 0,
SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3);
dev_dbg(cs42l42->dev, "Unplug event\n");
}
break;
default:
cs42l42->plug_state = CS42L42_TS_TRANS;
}
}
/* Check button detect status */
if (cs42l42->plug_state == CS42L42_TS_PLUG && ((~masks[7]) & irq_params_table[7].mask)) {
if (!(current_button_status &
CS42L42_M_HSBIAS_HIZ_MASK)) {
if (current_button_status & CS42L42_M_DETECT_TF_MASK) {
dev_dbg(cs42l42->dev, "Button released\n");
snd_soc_jack_report(cs42l42->jack, 0,
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3);
} else if (current_button_status & CS42L42_M_DETECT_FT_MASK) {
snd_soc_jack_report(cs42l42->jack,
cs42l42_handle_button_press(cs42l42),
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3);
}
}
}
mutex_unlock(&cs42l42->irq_lock);
pm_runtime_mark_last_busy(cs42l42->dev);
pm_runtime_put_autosuspend(cs42l42->dev);
return IRQ_HANDLED;
}
EXPORT_SYMBOL_NS_GPL(cs42l42_irq_thread, SND_SOC_CS42L42_CORE);
static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42)
{
regmap_update_bits(cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK,
CS42L42_ADC_OVFL_MASK,
(1 << CS42L42_ADC_OVFL_SHIFT));
regmap_update_bits(cs42l42->regmap, CS42L42_MIXER_INT_MASK,
CS42L42_MIX_CHB_OVFL_MASK |
CS42L42_MIX_CHA_OVFL_MASK |
CS42L42_EQ_OVFL_MASK |
CS42L42_EQ_BIQUAD_OVFL_MASK,
(1 << CS42L42_MIX_CHB_OVFL_SHIFT) |
(1 << CS42L42_MIX_CHA_OVFL_SHIFT) |
(1 << CS42L42_EQ_OVFL_SHIFT) |
(1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT));
regmap_update_bits(cs42l42->regmap, CS42L42_SRC_INT_MASK,
CS42L42_SRC_ILK_MASK |
CS42L42_SRC_OLK_MASK |
CS42L42_SRC_IUNLK_MASK |
CS42L42_SRC_OUNLK_MASK,
(1 << CS42L42_SRC_ILK_SHIFT) |
(1 << CS42L42_SRC_OLK_SHIFT) |
(1 << CS42L42_SRC_IUNLK_SHIFT) |
(1 << CS42L42_SRC_OUNLK_SHIFT));
regmap_update_bits(cs42l42->regmap, CS42L42_ASP_RX_INT_MASK,
CS42L42_ASPRX_NOLRCK_MASK |
CS42L42_ASPRX_EARLY_MASK |
CS42L42_ASPRX_LATE_MASK |
CS42L42_ASPRX_ERROR_MASK |
CS42L42_ASPRX_OVLD_MASK,
(1 << CS42L42_ASPRX_NOLRCK_SHIFT) |
(1 << CS42L42_ASPRX_EARLY_SHIFT) |
(1 << CS42L42_ASPRX_LATE_SHIFT) |
(1 << CS42L42_ASPRX_ERROR_SHIFT) |
(1 << CS42L42_ASPRX_OVLD_SHIFT));
regmap_update_bits(cs42l42->regmap, CS42L42_ASP_TX_INT_MASK,
CS42L42_ASPTX_NOLRCK_MASK |
CS42L42_ASPTX_EARLY_MASK |
CS42L42_ASPTX_LATE_MASK |
CS42L42_ASPTX_SMERROR_MASK,
(1 << CS42L42_ASPTX_NOLRCK_SHIFT) |
(1 << CS42L42_ASPTX_EARLY_SHIFT) |
(1 << CS42L42_ASPTX_LATE_SHIFT) |
(1 << CS42L42_ASPTX_SMERROR_SHIFT));
regmap_update_bits(cs42l42->regmap, CS42L42_CODEC_INT_MASK,
CS42L42_PDN_DONE_MASK |
CS42L42_HSDET_AUTO_DONE_MASK,
(1 << CS42L42_PDN_DONE_SHIFT) |
(1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
regmap_update_bits(cs42l42->regmap, CS42L42_SRCPL_INT_MASK,
CS42L42_SRCPL_ADC_LK_MASK |
CS42L42_SRCPL_DAC_LK_MASK |
CS42L42_SRCPL_ADC_UNLK_MASK |
CS42L42_SRCPL_DAC_UNLK_MASK,
(1 << CS42L42_SRCPL_ADC_LK_SHIFT) |
(1 << CS42L42_SRCPL_DAC_LK_SHIFT) |
(1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) |
(1 << CS42L42_SRCPL_DAC_UNLK_SHIFT));
regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT1_MASK,
CS42L42_TIP_SENSE_UNPLUG_MASK |
CS42L42_TIP_SENSE_PLUG_MASK |
CS42L42_HSBIAS_SENSE_MASK,
(1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) |
(1 << CS42L42_TIP_SENSE_PLUG_SHIFT) |
(1 << CS42L42_HSBIAS_SENSE_SHIFT));
regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT2_MASK,
CS42L42_M_DETECT_TF_MASK |
CS42L42_M_DETECT_FT_MASK |
CS42L42_M_HSBIAS_HIZ_MASK |
CS42L42_M_SHORT_RLS_MASK |
CS42L42_M_SHORT_DET_MASK,
(1 << CS42L42_M_DETECT_TF_SHIFT) |
(1 << CS42L42_M_DETECT_FT_SHIFT) |
(1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
(1 << CS42L42_M_SHORT_RLS_SHIFT) |
(1 << CS42L42_M_SHORT_DET_SHIFT));
regmap_update_bits(cs42l42->regmap, CS42L42_VPMON_INT_MASK,
CS42L42_VPMON_MASK,
(1 << CS42L42_VPMON_SHIFT));
regmap_update_bits(cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK,
CS42L42_PLL_LOCK_MASK,
(1 << CS42L42_PLL_LOCK_SHIFT));
regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK,
CS42L42_RS_PLUG_MASK |
CS42L42_RS_UNPLUG_MASK |
CS42L42_TS_PLUG_MASK |
CS42L42_TS_UNPLUG_MASK,
(1 << CS42L42_RS_PLUG_SHIFT) |
(1 << CS42L42_RS_UNPLUG_SHIFT) |
(0 << CS42L42_TS_PLUG_SHIFT) |
(0 << CS42L42_TS_UNPLUG_SHIFT));
}
static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42)
{
unsigned int reg;
cs42l42->hs_type = CS42L42_PLUG_INVALID;
/*
* DETECT_MODE must always be 0 with ADC and HP both off otherwise the
* FILT+ supply will not charge properly.
*/
regmap_update_bits(cs42l42->regmap, CS42L42_MISC_DET_CTL,
CS42L42_DETECT_MODE_MASK, 0);
/* Latch analog controls to VP power domain */
regmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1,
CS42L42_LATCH_TO_VP_MASK |
CS42L42_EVENT_STAT_SEL_MASK |
CS42L42_HS_DET_LEVEL_MASK,
(1 << CS42L42_LATCH_TO_VP_SHIFT) |
(0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
(cs42l42->bias_thresholds[0] <<
CS42L42_HS_DET_LEVEL_SHIFT));
/* Remove ground noise-suppression clamps */
regmap_update_bits(cs42l42->regmap,
CS42L42_HS_CLAMP_DISABLE,
CS42L42_HS_CLAMP_DISABLE_MASK,
(1 << CS42L42_HS_CLAMP_DISABLE_SHIFT));
/* Enable the tip sense circuit */
regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
CS42L42_TS_INV_MASK, CS42L42_TS_INV_MASK);
regmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL,
CS42L42_TIP_SENSE_CTRL_MASK |
CS42L42_TIP_SENSE_INV_MASK |
CS42L42_TIP_SENSE_DEBOUNCE_MASK,
(3 << CS42L42_TIP_SENSE_CTRL_SHIFT) |
(!cs42l42->ts_inv << CS42L42_TIP_SENSE_INV_SHIFT) |
(2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT));
/* Save the initial status of the tip sense */
regmap_read(cs42l42->regmap,
CS42L42_TSRS_PLUG_STATUS,
®);
cs42l42->plug_state = (((char) reg) &
(CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
CS42L42_TS_PLUG_SHIFT;
}
static const unsigned int threshold_defaults[] = {
CS42L42_HS_DET_LEVEL_15,
CS42L42_HS_DET_LEVEL_8,
CS42L42_HS_DET_LEVEL_4,
CS42L42_HS_DET_LEVEL_1
};
static int cs42l42_handle_device_data(struct device *dev,
struct cs42l42_private *cs42l42)
{
unsigned int val;
u32 thresholds[CS42L42_NUM_BIASES];
int ret;
int i;
ret = device_property_read_u32(dev, "cirrus,ts-inv", &val);
if (!ret) {
switch (val) {
case CS42L42_TS_INV_EN:
case CS42L42_TS_INV_DIS:
cs42l42->ts_inv = val;
break;
default:
dev_err(dev,
"Wrong cirrus,ts-inv DT value %d\n",
val);
cs42l42->ts_inv = CS42L42_TS_INV_DIS;
}
} else {
cs42l42->ts_inv = CS42L42_TS_INV_DIS;
}
ret = device_property_read_u32(dev, "cirrus,ts-dbnc-rise", &val);
if (!ret) {
switch (val) {
case CS42L42_TS_DBNCE_0:
case CS42L42_TS_DBNCE_125:
case CS42L42_TS_DBNCE_250:
case CS42L42_TS_DBNCE_500:
case CS42L42_TS_DBNCE_750:
case CS42L42_TS_DBNCE_1000:
case CS42L42_TS_DBNCE_1250:
case CS42L42_TS_DBNCE_1500:
cs42l42->ts_dbnc_rise = val;
break;
default:
dev_err(dev,
"Wrong cirrus,ts-dbnc-rise DT value %d\n",
val);
cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
}
} else {
cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
}
regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
CS42L42_TS_RISE_DBNCE_TIME_MASK,
(cs42l42->ts_dbnc_rise <<
CS42L42_TS_RISE_DBNCE_TIME_SHIFT));
ret = device_property_read_u32(dev, "cirrus,ts-dbnc-fall", &val);
if (!ret) {
switch (val) {
case CS42L42_TS_DBNCE_0:
case CS42L42_TS_DBNCE_125:
case CS42L42_TS_DBNCE_250:
case CS42L42_TS_DBNCE_500:
case CS42L42_TS_DBNCE_750:
case CS42L42_TS_DBNCE_1000:
case CS42L42_TS_DBNCE_1250:
case CS42L42_TS_DBNCE_1500:
cs42l42->ts_dbnc_fall = val;
break;
default:
dev_err(dev,
"Wrong cirrus,ts-dbnc-fall DT value %d\n",
val);
cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
}
} else {
cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
}
regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
CS42L42_TS_FALL_DBNCE_TIME_MASK,
(cs42l42->ts_dbnc_fall <<
CS42L42_TS_FALL_DBNCE_TIME_SHIFT));
ret = device_property_read_u32(dev, "cirrus,btn-det-init-dbnce", &val);
if (!ret) {
if (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX)
cs42l42->btn_det_init_dbnce = val;
else {
dev_err(dev,
"Wrong cirrus,btn-det-init-dbnce DT value %d\n",
val);
cs42l42->btn_det_init_dbnce =
CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
}
} else {
cs42l42->btn_det_init_dbnce =
CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
}
ret = device_property_read_u32(dev, "cirrus,btn-det-event-dbnce", &val);
if (!ret) {
if (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX)
cs42l42->btn_det_event_dbnce = val;
else {
dev_err(dev,
"Wrong cirrus,btn-det-event-dbnce DT value %d\n", val);
cs42l42->btn_det_event_dbnce =
CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
}
} else {
cs42l42->btn_det_event_dbnce =
CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
}
ret = device_property_read_u32_array(dev, "cirrus,bias-lvls",
thresholds, ARRAY_SIZE(thresholds));
if (!ret) {
for (i = 0; i < CS42L42_NUM_BIASES; i++) {
if (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX)
cs42l42->bias_thresholds[i] = thresholds[i];
else {
dev_err(dev,
"Wrong cirrus,bias-lvls[%d] DT value %d\n", i,
thresholds[i]);
cs42l42->bias_thresholds[i] = threshold_defaults[i];
}
}
} else {
for (i = 0; i < CS42L42_NUM_BIASES; i++)
cs42l42->bias_thresholds[i] = threshold_defaults[i];
}
ret = device_property_read_u32(dev, "cirrus,hs-bias-ramp-rate", &val);
if (!ret) {
switch (val) {
case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL:
cs42l42->hs_bias_ramp_rate = val;
cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0;
break;
case CS42L42_HSBIAS_RAMP_FAST:
cs42l42->hs_bias_ramp_rate = val;
cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1;
break;
case CS42L42_HSBIAS_RAMP_SLOW:
cs42l42->hs_bias_ramp_rate = val;
cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
break;
case CS42L42_HSBIAS_RAMP_SLOWEST:
cs42l42->hs_bias_ramp_rate = val;
cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3;
break;
default:
dev_err(dev,
"Wrong cirrus,hs-bias-ramp-rate DT value %d\n",
val);
cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
}
} else {
cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
}
regmap_update_bits(cs42l42->regmap, CS42L42_HS_BIAS_CTL,
CS42L42_HSBIAS_RAMP_MASK,
(cs42l42->hs_bias_ramp_rate <<
CS42L42_HSBIAS_RAMP_SHIFT));
if (device_property_read_bool(dev, "cirrus,hs-bias-sense-disable"))
cs42l42->hs_bias_sense_en = 0;
else
cs42l42->hs_bias_sense_en = 1;
return 0;
}
/* Datasheet suspend sequence */
static const struct reg_sequence __maybe_unused cs42l42_shutdown_seq[] = {
REG_SEQ0(CS42L42_MIC_DET_CTL1, 0x9F),
REG_SEQ0(CS42L42_ADC_OVFL_INT_MASK, 0x01),
REG_SEQ0(CS42L42_MIXER_INT_MASK, 0x0F),
REG_SEQ0(CS42L42_SRC_INT_MASK, 0x0F),
REG_SEQ0(CS42L42_ASP_RX_INT_MASK, 0x1F),
REG_SEQ0(CS42L42_ASP_TX_INT_MASK, 0x0F),
REG_SEQ0(CS42L42_CODEC_INT_MASK, 0x03),
REG_SEQ0(CS42L42_SRCPL_INT_MASK, 0x7F),
REG_SEQ0(CS42L42_VPMON_INT_MASK, 0x01),
REG_SEQ0(CS42L42_PLL_LOCK_INT_MASK, 0x01),
REG_SEQ0(CS42L42_TSRS_PLUG_INT_MASK, 0x0F),
REG_SEQ0(CS42L42_WAKE_CTL, 0xE1),
REG_SEQ0(CS42L42_DET_INT1_MASK, 0xE0),
REG_SEQ0(CS42L42_DET_INT2_MASK, 0xFF),
REG_SEQ0(CS42L42_MIXER_CHA_VOL, 0x3F),
REG_SEQ0(CS42L42_MIXER_ADC_VOL, 0x3F),
REG_SEQ0(CS42L42_MIXER_CHB_VOL, 0x3F),
REG_SEQ0(CS42L42_HP_CTL, 0x0F),
REG_SEQ0(CS42L42_ASP_RX_DAI0_EN, 0x00),
REG_SEQ0(CS42L42_ASP_CLK_CFG, 0x00),
REG_SEQ0(CS42L42_HSDET_CTL2, 0x00),
REG_SEQ0(CS42L42_PWR_CTL1, 0xFE),
REG_SEQ0(CS42L42_PWR_CTL2, 0x8C),
REG_SEQ0(CS42L42_DAC_CTL2, 0x02),
REG_SEQ0(CS42L42_HS_CLAMP_DISABLE, 0x00),
REG_SEQ0(CS42L42_MISC_DET_CTL, 0x03),
REG_SEQ0(CS42L42_TIPSENSE_CTL, 0x02),
REG_SEQ0(CS42L42_HSBIAS_SC_AUTOCTL, 0x03),
REG_SEQ0(CS42L42_PWR_CTL1, 0xFF)
};
int cs42l42_suspend(struct device *dev)
{
struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
unsigned int reg;
u8 save_regs[ARRAY_SIZE(cs42l42_shutdown_seq)];
int i, ret;
if (!cs42l42->init_done)
return 0;
/*
* Wait for threaded irq handler to be idle and stop it processing
* future interrupts. This ensures a safe disable if the interrupt
* is shared.
*/
mutex_lock(&cs42l42->irq_lock);
cs42l42->suspended = true;
/* Save register values that will be overwritten by shutdown sequence */
for (i = 0; i < ARRAY_SIZE(cs42l42_shutdown_seq); ++i) {
regmap_read(cs42l42->regmap, cs42l42_shutdown_seq[i].reg, ®);
save_regs[i] = (u8)reg;
}
/* Shutdown codec */
regmap_multi_reg_write(cs42l42->regmap,
cs42l42_shutdown_seq,
ARRAY_SIZE(cs42l42_shutdown_seq));
/* All interrupt sources are now disabled */
mutex_unlock(&cs42l42->irq_lock);
/* Wait for power-down complete */
msleep(CS42L42_PDN_DONE_TIME_MS);
ret = regmap_read_poll_timeout(cs42l42->regmap,
CS42L42_CODEC_STATUS, reg,
(reg & CS42L42_PDN_DONE_MASK),
CS42L42_PDN_DONE_POLL_US,
CS42L42_PDN_DONE_TIMEOUT_US);
if (ret)
dev_warn(dev, "Failed to get PDN_DONE: %d\n", ret);
/* Discharge FILT+ */
regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL2,
CS42L42_DISCHARGE_FILT_MASK, CS42L42_DISCHARGE_FILT_MASK);
msleep(CS42L42_FILT_DISCHARGE_TIME_MS);
regcache_cache_only(cs42l42->regmap, true);
gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies);
/* Restore register values to the regmap cache */
for (i = 0; i < ARRAY_SIZE(cs42l42_shutdown_seq); ++i)
regmap_write(cs42l42->regmap, cs42l42_shutdown_seq[i].reg, save_regs[i]);
/* The cached address page register value is now stale */
regcache_drop_region(cs42l42->regmap, CS42L42_PAGE_REGISTER, CS42L42_PAGE_REGISTER);
dev_dbg(dev, "System suspended\n");
return 0;
}
EXPORT_SYMBOL_NS_GPL(cs42l42_suspend, SND_SOC_CS42L42_CORE);
int cs42l42_resume(struct device *dev)
{
struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
int ret;
if (!cs42l42->init_done)
return 0;
/*
* If jack was unplugged and re-plugged during suspend it could
* have changed type but the tip-sense state hasn't changed.
* Force a plugged state to be re-evaluated.
*/
if (cs42l42->plug_state != CS42L42_TS_UNPLUG)
cs42l42->plug_state = CS42L42_TS_TRANS;
ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies);
if (ret != 0) {
dev_err(dev, "Failed to enable supplies: %d\n", ret);
return ret;
}
gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
dev_dbg(dev, "System resume powered up\n");
return 0;
}
EXPORT_SYMBOL_NS_GPL(cs42l42_resume, SND_SOC_CS42L42_CORE);
void cs42l42_resume_restore(struct device *dev)
{
struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
regcache_cache_only(cs42l42->regmap, false);
regcache_mark_dirty(cs42l42->regmap);
mutex_lock(&cs42l42->irq_lock);
/* Sync LATCH_TO_VP first so the VP domain registers sync correctly */
regcache_sync_region(cs42l42->regmap, CS42L42_MIC_DET_CTL1, CS42L42_MIC_DET_CTL1);
regcache_sync(cs42l42->regmap);
cs42l42->suspended = false;
mutex_unlock(&cs42l42->irq_lock);
dev_dbg(dev, "System resumed\n");
}
EXPORT_SYMBOL_NS_GPL(cs42l42_resume_restore, SND_SOC_CS42L42_CORE);
static int __maybe_unused cs42l42_i2c_resume(struct device *dev)
{
int ret;
ret = cs42l42_resume(dev);
if (ret)
return ret;
cs42l42_resume_restore(dev);
return 0;
}
int cs42l42_common_probe(struct cs42l42_private *cs42l42,
const struct snd_soc_component_driver *component_drv,
struct snd_soc_dai_driver *dai)
{
int ret, i;
dev_set_drvdata(cs42l42->dev, cs42l42);
mutex_init(&cs42l42->irq_lock);
BUILD_BUG_ON(ARRAY_SIZE(cs42l42_supply_names) != ARRAY_SIZE(cs42l42->supplies));
for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++)
cs42l42->supplies[i].supply = cs42l42_supply_names[i];
ret = devm_regulator_bulk_get(cs42l42->dev,
ARRAY_SIZE(cs42l42->supplies),
cs42l42->supplies);
if (ret != 0) {
dev_err(cs42l42->dev,
"Failed to request supplies: %d\n", ret);
return ret;
}
ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies),
cs42l42->supplies);
if (ret != 0) {
dev_err(cs42l42->dev,
"Failed to enable supplies: %d\n", ret);
return ret;
}
/* Reset the Device */
cs42l42->reset_gpio = devm_gpiod_get_optional(cs42l42->dev,
"reset", GPIOD_OUT_LOW);
if (IS_ERR(cs42l42->reset_gpio)) {
ret = PTR_ERR(cs42l42->reset_gpio);
goto err_disable_noreset;
}
if (cs42l42->reset_gpio) {
dev_dbg(cs42l42->dev, "Found reset GPIO\n");
/*
* ACPI can override the default GPIO state we requested
* so ensure that we start with RESET low.
*/
gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
/* Ensure minimum reset pulse width */
usleep_range(10, 500);
/*
* On SoundWire keep the chip in reset until we get an UNATTACH
* notification from the SoundWire core. This acts as a
* synchronization point to reject stale ATTACH notifications
* if the chip was already enumerated before we reset it.
*/
if (cs42l42->sdw_peripheral)
cs42l42->sdw_waiting_first_unattach = true;
else
gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
}
usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
/* Request IRQ if one was specified */
if (cs42l42->irq) {
ret = request_threaded_irq(cs42l42->irq,
NULL, cs42l42_irq_thread,
IRQF_ONESHOT | IRQF_TRIGGER_LOW,
"cs42l42", cs42l42);
if (ret) {
dev_err_probe(cs42l42->dev, ret,
"Failed to request IRQ\n");
goto err_disable_noirq;
}
}
/* Register codec now so it can EPROBE_DEFER */
ret = devm_snd_soc_register_component(cs42l42->dev, component_drv, dai, 1);
if (ret < 0)
goto err;
return 0;
err:
if (cs42l42->irq)
free_irq(cs42l42->irq, cs42l42);
err_disable_noirq:
gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
err_disable_noreset:
regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies);
return ret;
}
EXPORT_SYMBOL_NS_GPL(cs42l42_common_probe, SND_SOC_CS42L42_CORE);
int cs42l42_init(struct cs42l42_private *cs42l42)
{
unsigned int reg;
int devid, ret;
/* initialize codec */
devid = cirrus_read_device_id(cs42l42->regmap, CS42L42_DEVID_AB);
if (devid < 0) {
ret = devid;
dev_err(cs42l42->dev, "Failed to read device ID: %d\n", ret);
goto err_disable;
}
if (devid != cs42l42->devid) {
ret = -ENODEV;
dev_err(cs42l42->dev,
"CS42L%x Device ID (%X). Expected %X\n",
cs42l42->devid & 0xff, devid, cs42l42->devid);
goto err_disable;
}
ret = regmap_read(cs42l42->regmap, CS42L42_REVID, ®);
if (ret < 0) {
dev_err(cs42l42->dev, "Get Revision ID failed\n");
goto err_shutdown;
}
dev_info(cs42l42->dev,
"Cirrus Logic CS42L%x, Revision: %02X\n",
cs42l42->devid & 0xff, reg & 0xFF);
/* Power up the codec */
regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1,
CS42L42_ASP_DAO_PDN_MASK |
CS42L42_ASP_DAI_PDN_MASK |
CS42L42_MIXER_PDN_MASK |
CS42L42_EQ_PDN_MASK |
CS42L42_HP_PDN_MASK |
CS42L42_ADC_PDN_MASK |
CS42L42_PDN_ALL_MASK,
(1 << CS42L42_ASP_DAO_PDN_SHIFT) |
(1 << CS42L42_ASP_DAI_PDN_SHIFT) |
(1 << CS42L42_MIXER_PDN_SHIFT) |
(1 << CS42L42_EQ_PDN_SHIFT) |
(1 << CS42L42_HP_PDN_SHIFT) |
(1 << CS42L42_ADC_PDN_SHIFT) |
(0 << CS42L42_PDN_ALL_SHIFT));
ret = cs42l42_handle_device_data(cs42l42->dev, cs42l42);
if (ret != 0)
goto err_shutdown;
/*
* SRC power is linked to ASP power so doesn't work in Soundwire mode.
* Override it and use DAPM to control SRC power for Soundwire.
*/
if (cs42l42->sdw_peripheral) {
regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL2,
CS42L42_SRC_PDN_OVERRIDE_MASK |
CS42L42_DAC_SRC_PDNB_MASK |
CS42L42_ADC_SRC_PDNB_MASK,
CS42L42_SRC_PDN_OVERRIDE_MASK);
}
/* Setup headset detection */
cs42l42_setup_hs_type_detect(cs42l42);
/*
* Set init_done before unmasking interrupts so any triggered
* immediately will be handled.
*/
cs42l42->init_done = true;
/* Mask/Unmask Interrupts */
cs42l42_set_interrupt_masks(cs42l42);
return 0;
err_shutdown:
regmap_write(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 0xff);
regmap_write(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 0xff);
regmap_write(cs42l42->regmap, CS42L42_PWR_CTL1, 0xff);
err_disable:
if (cs42l42->irq)
free_irq(cs42l42->irq, cs42l42);
gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
cs42l42->supplies);
return ret;
}
EXPORT_SYMBOL_NS_GPL(cs42l42_init, SND_SOC_CS42L42_CORE);
void cs42l42_common_remove(struct cs42l42_private *cs42l42)
{
if (cs42l42->irq)
free_irq(cs42l42->irq, cs42l42);
/*
* The driver might not have control of reset and power supplies,
* so ensure that the chip internals are powered down.
*/
if (cs42l42->init_done) {
regmap_write(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 0xff);
regmap_write(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 0xff);
regmap_write(cs42l42->regmap, CS42L42_PWR_CTL1, 0xff);
}
gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies);
}
EXPORT_SYMBOL_NS_GPL(cs42l42_common_remove, SND_SOC_CS42L42_CORE);
MODULE_DESCRIPTION("ASoC CS42L42 driver");
MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <[email protected]>");
MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <[email protected]>");
MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <[email protected]>");
MODULE_AUTHOR("Lucas Tanure <[email protected]>");
MODULE_AUTHOR("Richard Fitzgerald <[email protected]>");
MODULE_AUTHOR("Vitaly Rodionov <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cs42l42.c |
// SPDX-License-Identifier: GPL-2.0
// tscs454.c -- TSCS454 ALSA SoC Audio driver
// Copyright 2018 Tempo Semiconductor, Inc.
// Author: Steven Eckhoff <[email protected]>
#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/regmap.h>
#include <linux/i2c.h>
#include <linux/err.h>
#include <linux/string.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/mutex.h>
#include <sound/tlv.h>
#include <sound/pcm_params.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include "tscs454.h"
static const unsigned int PLL_44_1K_RATE = (44100 * 256);
#define COEFF_SIZE 3
#define BIQUAD_COEFF_COUNT 5
#define BIQUAD_SIZE (COEFF_SIZE * BIQUAD_COEFF_COUNT)
#define COEFF_RAM_MAX_ADDR 0xcd
#define COEFF_RAM_COEFF_COUNT (COEFF_RAM_MAX_ADDR + 1)
#define COEFF_RAM_SIZE (COEFF_SIZE * COEFF_RAM_COEFF_COUNT)
enum {
TSCS454_DAI1_ID,
TSCS454_DAI2_ID,
TSCS454_DAI3_ID,
TSCS454_DAI_COUNT,
};
struct pll {
int id;
unsigned int users;
struct mutex lock;
};
static inline void pll_init(struct pll *pll, int id)
{
pll->id = id;
mutex_init(&pll->lock);
}
struct internal_rate {
struct pll *pll;
};
struct aif {
unsigned int id;
bool provider;
struct pll *pll;
};
static inline void aif_init(struct aif *aif, unsigned int id)
{
aif->id = id;
}
struct coeff_ram {
u8 cache[COEFF_RAM_SIZE];
bool synced;
struct mutex lock;
};
static inline void init_coeff_ram_cache(u8 *cache)
{
static const u8 norm_addrs[] = { 0x00, 0x05, 0x0a, 0x0f, 0x14, 0x19,
0x1f, 0x20, 0x25, 0x2a, 0x2f, 0x34, 0x39, 0x3f, 0x40, 0x45,
0x4a, 0x4f, 0x54, 0x59, 0x5f, 0x60, 0x65, 0x6a, 0x6f, 0x74,
0x79, 0x7f, 0x80, 0x85, 0x8c, 0x91, 0x96, 0x97, 0x9c, 0xa3,
0xa8, 0xad, 0xaf, 0xb0, 0xb5, 0xba, 0xbf, 0xc4, 0xc9};
int i;
for (i = 0; i < ARRAY_SIZE(norm_addrs); i++)
cache[((norm_addrs[i] + 1) * COEFF_SIZE) - 1] = 0x40;
}
static inline void coeff_ram_init(struct coeff_ram *ram)
{
init_coeff_ram_cache(ram->cache);
mutex_init(&ram->lock);
}
struct aifs_status {
u8 streams;
};
static inline void set_aif_status_active(struct aifs_status *status,
int aif_id, bool playback)
{
u8 mask = 0x01 << (aif_id * 2 + !playback);
status->streams |= mask;
}
static inline void set_aif_status_inactive(struct aifs_status *status,
int aif_id, bool playback)
{
u8 mask = ~(0x01 << (aif_id * 2 + !playback));
status->streams &= mask;
}
static bool aifs_active(struct aifs_status *status)
{
return status->streams;
}
static bool aif_active(struct aifs_status *status, int aif_id)
{
return (0x03 << aif_id * 2) & status->streams;
}
struct tscs454 {
struct regmap *regmap;
struct aif aifs[TSCS454_DAI_COUNT];
struct aifs_status aifs_status;
struct mutex aifs_status_lock;
struct pll pll1;
struct pll pll2;
struct internal_rate internal_rate;
struct coeff_ram dac_ram;
struct coeff_ram spk_ram;
struct coeff_ram sub_ram;
struct clk *sysclk;
int sysclk_src_id;
unsigned int bclk_freq;
};
struct coeff_ram_ctl {
unsigned int addr;
struct soc_bytes_ext bytes_ext;
};
static const struct reg_sequence tscs454_patch[] = {
/* Assign ASRC out of the box so DAI 1 just works */
{ R_AUDIOMUX1, FV_ASRCIMUX_I2S1 | FV_I2S2MUX_I2S2 },
{ R_AUDIOMUX2, FV_ASRCOMUX_I2S1 | FV_DACMUX_I2S1 | FV_I2S3MUX_I2S3 },
{ R_AUDIOMUX3, FV_CLSSDMUX_I2S1 | FV_SUBMUX_I2S1_LR },
{ R_TDMCTL0, FV_TDMMD_256 },
{ VIRT_ADDR(0x0A, 0x13), 1 << 3 },
};
static bool tscs454_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case R_PLLSTAT:
case R_SPKCRRDL:
case R_SPKCRRDM:
case R_SPKCRRDH:
case R_SPKCRS:
case R_DACCRRDL:
case R_DACCRRDM:
case R_DACCRRDH:
case R_DACCRS:
case R_SUBCRRDL:
case R_SUBCRRDM:
case R_SUBCRRDH:
case R_SUBCRS:
return true;
default:
return false;
}
}
static bool tscs454_writable(struct device *dev, unsigned int reg)
{
switch (reg) {
case R_SPKCRRDL:
case R_SPKCRRDM:
case R_SPKCRRDH:
case R_DACCRRDL:
case R_DACCRRDM:
case R_DACCRRDH:
case R_SUBCRRDL:
case R_SUBCRRDM:
case R_SUBCRRDH:
return false;
default:
return true;
}
}
static bool tscs454_readable(struct device *dev, unsigned int reg)
{
switch (reg) {
case R_SPKCRWDL:
case R_SPKCRWDM:
case R_SPKCRWDH:
case R_DACCRWDL:
case R_DACCRWDM:
case R_DACCRWDH:
case R_SUBCRWDL:
case R_SUBCRWDM:
case R_SUBCRWDH:
return false;
default:
return true;
}
}
static bool tscs454_precious(struct device *dev, unsigned int reg)
{
switch (reg) {
case R_SPKCRWDL:
case R_SPKCRWDM:
case R_SPKCRWDH:
case R_SPKCRRDL:
case R_SPKCRRDM:
case R_SPKCRRDH:
case R_DACCRWDL:
case R_DACCRWDM:
case R_DACCRWDH:
case R_DACCRRDL:
case R_DACCRRDM:
case R_DACCRRDH:
case R_SUBCRWDL:
case R_SUBCRWDM:
case R_SUBCRWDH:
case R_SUBCRRDL:
case R_SUBCRRDM:
case R_SUBCRRDH:
return true;
default:
return false;
}
}
static const struct regmap_range_cfg tscs454_regmap_range_cfg = {
.name = "Pages",
.range_min = VIRT_BASE,
.range_max = VIRT_ADDR(0xFE, 0x02),
.selector_reg = R_PAGESEL,
.selector_mask = 0xff,
.selector_shift = 0,
.window_start = 0,
.window_len = 0x100,
};
static struct regmap_config const tscs454_regmap_cfg = {
.reg_bits = 8,
.val_bits = 8,
.writeable_reg = tscs454_writable,
.readable_reg = tscs454_readable,
.volatile_reg = tscs454_volatile,
.precious_reg = tscs454_precious,
.ranges = &tscs454_regmap_range_cfg,
.num_ranges = 1,
.max_register = VIRT_ADDR(0xFE, 0x02),
.cache_type = REGCACHE_RBTREE,
};
static inline int tscs454_data_init(struct tscs454 *tscs454,
struct i2c_client *i2c)
{
int i;
int ret;
tscs454->regmap = devm_regmap_init_i2c(i2c, &tscs454_regmap_cfg);
if (IS_ERR(tscs454->regmap)) {
ret = PTR_ERR(tscs454->regmap);
return ret;
}
for (i = 0; i < TSCS454_DAI_COUNT; i++)
aif_init(&tscs454->aifs[i], i);
mutex_init(&tscs454->aifs_status_lock);
pll_init(&tscs454->pll1, 1);
pll_init(&tscs454->pll2, 2);
coeff_ram_init(&tscs454->dac_ram);
coeff_ram_init(&tscs454->spk_ram);
coeff_ram_init(&tscs454->sub_ram);
return 0;
}
struct reg_setting {
unsigned int addr;
unsigned int val;
};
static int coeff_ram_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
struct coeff_ram_ctl *ctl =
(struct coeff_ram_ctl *)kcontrol->private_value;
struct soc_bytes_ext *params = &ctl->bytes_ext;
u8 *coeff_ram;
struct mutex *coeff_ram_lock;
if (strstr(kcontrol->id.name, "DAC")) {
coeff_ram = tscs454->dac_ram.cache;
coeff_ram_lock = &tscs454->dac_ram.lock;
} else if (strstr(kcontrol->id.name, "Speaker")) {
coeff_ram = tscs454->spk_ram.cache;
coeff_ram_lock = &tscs454->spk_ram.lock;
} else if (strstr(kcontrol->id.name, "Sub")) {
coeff_ram = tscs454->sub_ram.cache;
coeff_ram_lock = &tscs454->sub_ram.lock;
} else {
return -EINVAL;
}
mutex_lock(coeff_ram_lock);
memcpy(ucontrol->value.bytes.data,
&coeff_ram[ctl->addr * COEFF_SIZE], params->max);
mutex_unlock(coeff_ram_lock);
return 0;
}
#define DACCRSTAT_MAX_TRYS 10
static int write_coeff_ram(struct snd_soc_component *component, u8 *coeff_ram,
unsigned int r_stat, unsigned int r_addr, unsigned int r_wr,
unsigned int coeff_addr, unsigned int coeff_cnt)
{
struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
unsigned int val;
int cnt;
int trys;
int ret;
for (cnt = 0; cnt < coeff_cnt; cnt++, coeff_addr++) {
for (trys = 0; trys < DACCRSTAT_MAX_TRYS; trys++) {
val = snd_soc_component_read(component, r_stat);
if (!val)
break;
}
if (trys == DACCRSTAT_MAX_TRYS) {
ret = -EIO;
dev_err(component->dev,
"Coefficient write error (%d)\n", ret);
return ret;
}
ret = regmap_write(tscs454->regmap, r_addr, coeff_addr);
if (ret < 0) {
dev_err(component->dev,
"Failed to write dac ram address (%d)\n", ret);
return ret;
}
ret = regmap_bulk_write(tscs454->regmap, r_wr,
&coeff_ram[coeff_addr * COEFF_SIZE],
COEFF_SIZE);
if (ret < 0) {
dev_err(component->dev,
"Failed to write dac ram (%d)\n", ret);
return ret;
}
}
return 0;
}
static int coeff_ram_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
struct coeff_ram_ctl *ctl =
(struct coeff_ram_ctl *)kcontrol->private_value;
struct soc_bytes_ext *params = &ctl->bytes_ext;
unsigned int coeff_cnt = params->max / COEFF_SIZE;
u8 *coeff_ram;
struct mutex *coeff_ram_lock;
bool *coeff_ram_synced;
unsigned int r_stat;
unsigned int r_addr;
unsigned int r_wr;
unsigned int val;
int ret;
if (strstr(kcontrol->id.name, "DAC")) {
coeff_ram = tscs454->dac_ram.cache;
coeff_ram_lock = &tscs454->dac_ram.lock;
coeff_ram_synced = &tscs454->dac_ram.synced;
r_stat = R_DACCRS;
r_addr = R_DACCRADD;
r_wr = R_DACCRWDL;
} else if (strstr(kcontrol->id.name, "Speaker")) {
coeff_ram = tscs454->spk_ram.cache;
coeff_ram_lock = &tscs454->spk_ram.lock;
coeff_ram_synced = &tscs454->spk_ram.synced;
r_stat = R_SPKCRS;
r_addr = R_SPKCRADD;
r_wr = R_SPKCRWDL;
} else if (strstr(kcontrol->id.name, "Sub")) {
coeff_ram = tscs454->sub_ram.cache;
coeff_ram_lock = &tscs454->sub_ram.lock;
coeff_ram_synced = &tscs454->sub_ram.synced;
r_stat = R_SUBCRS;
r_addr = R_SUBCRADD;
r_wr = R_SUBCRWDL;
} else {
return -EINVAL;
}
mutex_lock(coeff_ram_lock);
*coeff_ram_synced = false;
memcpy(&coeff_ram[ctl->addr * COEFF_SIZE],
ucontrol->value.bytes.data, params->max);
mutex_lock(&tscs454->pll1.lock);
mutex_lock(&tscs454->pll2.lock);
val = snd_soc_component_read(component, R_PLLSTAT);
if (val) { /* PLLs locked */
ret = write_coeff_ram(component, coeff_ram,
r_stat, r_addr, r_wr,
ctl->addr, coeff_cnt);
if (ret < 0) {
dev_err(component->dev,
"Failed to flush coeff ram cache (%d)\n", ret);
goto exit;
}
*coeff_ram_synced = true;
}
ret = 0;
exit:
mutex_unlock(&tscs454->pll2.lock);
mutex_unlock(&tscs454->pll1.lock);
mutex_unlock(coeff_ram_lock);
return ret;
}
static inline int coeff_ram_sync(struct snd_soc_component *component,
struct tscs454 *tscs454)
{
int ret;
mutex_lock(&tscs454->dac_ram.lock);
if (!tscs454->dac_ram.synced) {
ret = write_coeff_ram(component, tscs454->dac_ram.cache,
R_DACCRS, R_DACCRADD, R_DACCRWDL,
0x00, COEFF_RAM_COEFF_COUNT);
if (ret < 0) {
mutex_unlock(&tscs454->dac_ram.lock);
return ret;
}
}
mutex_unlock(&tscs454->dac_ram.lock);
mutex_lock(&tscs454->spk_ram.lock);
if (!tscs454->spk_ram.synced) {
ret = write_coeff_ram(component, tscs454->spk_ram.cache,
R_SPKCRS, R_SPKCRADD, R_SPKCRWDL,
0x00, COEFF_RAM_COEFF_COUNT);
if (ret < 0) {
mutex_unlock(&tscs454->spk_ram.lock);
return ret;
}
}
mutex_unlock(&tscs454->spk_ram.lock);
mutex_lock(&tscs454->sub_ram.lock);
if (!tscs454->sub_ram.synced) {
ret = write_coeff_ram(component, tscs454->sub_ram.cache,
R_SUBCRS, R_SUBCRADD, R_SUBCRWDL,
0x00, COEFF_RAM_COEFF_COUNT);
if (ret < 0) {
mutex_unlock(&tscs454->sub_ram.lock);
return ret;
}
}
mutex_unlock(&tscs454->sub_ram.lock);
return 0;
}
#define PLL_REG_SETTINGS_COUNT 11
struct pll_ctl {
int freq_in;
struct reg_setting settings[PLL_REG_SETTINGS_COUNT];
};
#define PLL_CTL(f, t, c1, r1, o1, f1l, f1h, c2, r2, o2, f2l, f2h) \
{ \
.freq_in = f, \
.settings = { \
{R_PLL1CTL, c1}, \
{R_PLL1RDIV, r1}, \
{R_PLL1ODIV, o1}, \
{R_PLL1FDIVL, f1l}, \
{R_PLL1FDIVH, f1h}, \
{R_PLL2CTL, c2}, \
{R_PLL2RDIV, r2}, \
{R_PLL2ODIV, o2}, \
{R_PLL2FDIVL, f2l}, \
{R_PLL2FDIVH, f2h}, \
{R_TIMEBASE, t}, \
}, \
}
static const struct pll_ctl pll_ctls[] = {
PLL_CTL(1411200, 0x05,
0xB9, 0x07, 0x02, 0xC3, 0x04,
0x5A, 0x02, 0x03, 0xE0, 0x01),
PLL_CTL(1536000, 0x05,
0x5A, 0x02, 0x03, 0xE0, 0x01,
0x5A, 0x02, 0x03, 0xB9, 0x01),
PLL_CTL(2822400, 0x0A,
0x63, 0x07, 0x04, 0xC3, 0x04,
0x62, 0x07, 0x03, 0x48, 0x03),
PLL_CTL(3072000, 0x0B,
0x62, 0x07, 0x03, 0x48, 0x03,
0x5A, 0x04, 0x03, 0xB9, 0x01),
PLL_CTL(5644800, 0x15,
0x63, 0x0E, 0x04, 0xC3, 0x04,
0x5A, 0x08, 0x03, 0xE0, 0x01),
PLL_CTL(6144000, 0x17,
0x5A, 0x08, 0x03, 0xE0, 0x01,
0x5A, 0x08, 0x03, 0xB9, 0x01),
PLL_CTL(12000000, 0x2E,
0x5B, 0x19, 0x03, 0x00, 0x03,
0x6A, 0x19, 0x05, 0x98, 0x04),
PLL_CTL(19200000, 0x4A,
0x53, 0x14, 0x03, 0x80, 0x01,
0x5A, 0x19, 0x03, 0xB9, 0x01),
PLL_CTL(22000000, 0x55,
0x6A, 0x37, 0x05, 0x00, 0x06,
0x62, 0x26, 0x03, 0x49, 0x02),
PLL_CTL(22579200, 0x57,
0x62, 0x31, 0x03, 0x20, 0x03,
0x53, 0x1D, 0x03, 0xB3, 0x01),
PLL_CTL(24000000, 0x5D,
0x53, 0x19, 0x03, 0x80, 0x01,
0x5B, 0x19, 0x05, 0x4C, 0x02),
PLL_CTL(24576000, 0x5F,
0x53, 0x1D, 0x03, 0xB3, 0x01,
0x62, 0x40, 0x03, 0x72, 0x03),
PLL_CTL(27000000, 0x68,
0x62, 0x4B, 0x03, 0x00, 0x04,
0x6A, 0x7D, 0x03, 0x20, 0x06),
PLL_CTL(36000000, 0x8C,
0x5B, 0x4B, 0x03, 0x00, 0x03,
0x6A, 0x7D, 0x03, 0x98, 0x04),
PLL_CTL(11289600, 0x2B,
0x6A, 0x31, 0x03, 0x40, 0x06,
0x5A, 0x12, 0x03, 0x1C, 0x02),
PLL_CTL(26000000, 0x65,
0x63, 0x41, 0x05, 0x00, 0x06,
0x5A, 0x26, 0x03, 0xEF, 0x01),
PLL_CTL(12288000, 0x2F,
0x5A, 0x12, 0x03, 0x1C, 0x02,
0x62, 0x20, 0x03, 0x72, 0x03),
PLL_CTL(40000000, 0x9B,
0xA2, 0x7D, 0x03, 0x80, 0x04,
0x63, 0x7D, 0x05, 0xE4, 0x06),
PLL_CTL(512000, 0x01,
0x62, 0x01, 0x03, 0xD0, 0x02,
0x5B, 0x01, 0x04, 0x72, 0x03),
PLL_CTL(705600, 0x02,
0x62, 0x02, 0x03, 0x15, 0x04,
0x62, 0x01, 0x04, 0x80, 0x02),
PLL_CTL(1024000, 0x03,
0x62, 0x02, 0x03, 0xD0, 0x02,
0x5B, 0x02, 0x04, 0x72, 0x03),
PLL_CTL(2048000, 0x07,
0x62, 0x04, 0x03, 0xD0, 0x02,
0x5B, 0x04, 0x04, 0x72, 0x03),
PLL_CTL(2400000, 0x08,
0x62, 0x05, 0x03, 0x00, 0x03,
0x63, 0x05, 0x05, 0x98, 0x04),
};
static inline const struct pll_ctl *get_pll_ctl(unsigned long freq_in)
{
int i;
struct pll_ctl const *pll_ctl = NULL;
for (i = 0; i < ARRAY_SIZE(pll_ctls); ++i)
if (pll_ctls[i].freq_in == freq_in) {
pll_ctl = &pll_ctls[i];
break;
}
return pll_ctl;
}
enum {
PLL_INPUT_XTAL = 0,
PLL_INPUT_MCLK1,
PLL_INPUT_MCLK2,
PLL_INPUT_BCLK,
};
static int set_sysclk(struct snd_soc_component *component)
{
struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
struct pll_ctl const *pll_ctl;
unsigned long freq;
int i;
int ret;
if (tscs454->sysclk_src_id < PLL_INPUT_BCLK)
freq = clk_get_rate(tscs454->sysclk);
else
freq = tscs454->bclk_freq;
pll_ctl = get_pll_ctl(freq);
if (!pll_ctl) {
ret = -EINVAL;
dev_err(component->dev,
"Invalid PLL input %lu (%d)\n", freq, ret);
return ret;
}
for (i = 0; i < PLL_REG_SETTINGS_COUNT; ++i) {
ret = snd_soc_component_write(component,
pll_ctl->settings[i].addr,
pll_ctl->settings[i].val);
if (ret < 0) {
dev_err(component->dev,
"Failed to set pll setting (%d)\n",
ret);
return ret;
}
}
return 0;
}
static inline void reserve_pll(struct pll *pll)
{
mutex_lock(&pll->lock);
pll->users++;
mutex_unlock(&pll->lock);
}
static inline void free_pll(struct pll *pll)
{
mutex_lock(&pll->lock);
pll->users--;
mutex_unlock(&pll->lock);
}
static int pll_connected(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(source->dapm);
struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
int users;
if (strstr(source->name, "PLL 1")) {
mutex_lock(&tscs454->pll1.lock);
users = tscs454->pll1.users;
mutex_unlock(&tscs454->pll1.lock);
dev_dbg(component->dev, "%s(): PLL 1 users = %d\n", __func__,
users);
} else {
mutex_lock(&tscs454->pll2.lock);
users = tscs454->pll2.users;
mutex_unlock(&tscs454->pll2.lock);
dev_dbg(component->dev, "%s(): PLL 2 users = %d\n", __func__,
users);
}
return users;
}
/*
* PLL must be enabled after power up and must be disabled before power down
* for proper clock switching.
*/
static int pll_power_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
bool enable;
bool pll1;
unsigned int msk;
unsigned int val;
int ret;
if (strstr(w->name, "PLL 1"))
pll1 = true;
else
pll1 = false;
msk = pll1 ? FM_PLLCTL_PLL1CLKEN : FM_PLLCTL_PLL2CLKEN;
if (event == SND_SOC_DAPM_POST_PMU)
enable = true;
else
enable = false;
if (enable)
val = pll1 ? FV_PLL1CLKEN_ENABLE : FV_PLL2CLKEN_ENABLE;
else
/*
* FV_PLL1CLKEN_DISABLE and FV_PLL2CLKEN_DISABLE are
* identical zero vzalues, there is no need to test
* the PLL index
*/
val = FV_PLL1CLKEN_DISABLE;
ret = snd_soc_component_update_bits(component, R_PLLCTL, msk, val);
if (ret < 0) {
dev_err(component->dev, "Failed to %s PLL %d (%d)\n",
enable ? "enable" : "disable",
pll1 ? 1 : 2,
ret);
return ret;
}
if (enable) {
msleep(20); // Wait for lock
ret = coeff_ram_sync(component, tscs454);
if (ret < 0) {
dev_err(component->dev,
"Failed to sync coeff ram (%d)\n", ret);
return ret;
}
}
return 0;
}
static inline int aif_set_provider(struct snd_soc_component *component,
unsigned int aif_id, bool provider)
{
unsigned int reg;
unsigned int mask;
unsigned int val;
int ret;
switch (aif_id) {
case TSCS454_DAI1_ID:
reg = R_I2SP1CTL;
break;
case TSCS454_DAI2_ID:
reg = R_I2SP2CTL;
break;
case TSCS454_DAI3_ID:
reg = R_I2SP3CTL;
break;
default:
ret = -ENODEV;
dev_err(component->dev, "Unknown DAI %d (%d)\n", aif_id, ret);
return ret;
}
mask = FM_I2SPCTL_PORTMS;
val = provider ? FV_PORTMS_MASTER : FV_PORTMS_SLAVE;
ret = snd_soc_component_update_bits(component, reg, mask, val);
if (ret < 0) {
dev_err(component->dev, "Failed to set DAI %d to %s (%d)\n",
aif_id, provider ? "provider" : "consumer", ret);
return ret;
}
return 0;
}
static inline
int aif_prepare(struct snd_soc_component *component, struct aif *aif)
{
int ret;
ret = aif_set_provider(component, aif->id, aif->provider);
if (ret < 0)
return ret;
return 0;
}
static inline int aif_free(struct snd_soc_component *component,
struct aif *aif, bool playback)
{
struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
mutex_lock(&tscs454->aifs_status_lock);
dev_dbg(component->dev, "%s(): aif %d\n", __func__, aif->id);
set_aif_status_inactive(&tscs454->aifs_status, aif->id, playback);
dev_dbg(component->dev, "Set aif %d inactive. Streams status is 0x%x\n",
aif->id, tscs454->aifs_status.streams);
if (!aif_active(&tscs454->aifs_status, aif->id)) {
/* Do config in slave mode */
aif_set_provider(component, aif->id, false);
dev_dbg(component->dev, "Freeing pll %d from aif %d\n",
aif->pll->id, aif->id);
free_pll(aif->pll);
}
if (!aifs_active(&tscs454->aifs_status)) {
dev_dbg(component->dev, "Freeing pll %d from ir\n",
tscs454->internal_rate.pll->id);
free_pll(tscs454->internal_rate.pll);
}
mutex_unlock(&tscs454->aifs_status_lock);
return 0;
}
/* R_PLLCTL PG 0 ADDR 0x15 */
static char const * const bclk_sel_txt[] = {
"BCLK 1", "BCLK 2", "BCLK 3"};
static struct soc_enum const bclk_sel_enum =
SOC_ENUM_SINGLE(R_PLLCTL, FB_PLLCTL_BCLKSEL,
ARRAY_SIZE(bclk_sel_txt), bclk_sel_txt);
/* R_ISRC PG 0 ADDR 0x16 */
static char const * const isrc_br_txt[] = {
"44.1kHz", "48kHz"};
static struct soc_enum const isrc_br_enum =
SOC_ENUM_SINGLE(R_ISRC, FB_ISRC_IBR,
ARRAY_SIZE(isrc_br_txt), isrc_br_txt);
static char const * const isrc_bm_txt[] = {
"0.25x", "0.5x", "1.0x", "2.0x"};
static struct soc_enum const isrc_bm_enum =
SOC_ENUM_SINGLE(R_ISRC, FB_ISRC_IBM,
ARRAY_SIZE(isrc_bm_txt), isrc_bm_txt);
/* R_SCLKCTL PG 0 ADDR 0x18 */
static char const * const modular_rate_txt[] = {
"Reserved", "Half", "Full", "Auto",};
static struct soc_enum const adc_modular_rate_enum =
SOC_ENUM_SINGLE(R_SCLKCTL, FB_SCLKCTL_ASDM,
ARRAY_SIZE(modular_rate_txt), modular_rate_txt);
static struct soc_enum const dac_modular_rate_enum =
SOC_ENUM_SINGLE(R_SCLKCTL, FB_SCLKCTL_DSDM,
ARRAY_SIZE(modular_rate_txt), modular_rate_txt);
/* R_I2SIDCTL PG 0 ADDR 0x38 */
static char const * const data_ctrl_txt[] = {
"L/R", "L/L", "R/R", "R/L"};
static struct soc_enum const data_in_ctrl_enums[] = {
SOC_ENUM_SINGLE(R_I2SIDCTL, FB_I2SIDCTL_I2SI1DCTL,
ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
SOC_ENUM_SINGLE(R_I2SIDCTL, FB_I2SIDCTL_I2SI2DCTL,
ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
SOC_ENUM_SINGLE(R_I2SIDCTL, FB_I2SIDCTL_I2SI3DCTL,
ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
};
/* R_I2SODCTL PG 0 ADDR 0x39 */
static struct soc_enum const data_out_ctrl_enums[] = {
SOC_ENUM_SINGLE(R_I2SODCTL, FB_I2SODCTL_I2SO1DCTL,
ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
SOC_ENUM_SINGLE(R_I2SODCTL, FB_I2SODCTL_I2SO2DCTL,
ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
SOC_ENUM_SINGLE(R_I2SODCTL, FB_I2SODCTL_I2SO3DCTL,
ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
};
/* R_AUDIOMUX1 PG 0 ADDR 0x3A */
static char const * const asrc_mux_txt[] = {
"None", "DAI 1", "DAI 2", "DAI 3"};
static struct soc_enum const asrc_in_mux_enum =
SOC_ENUM_SINGLE(R_AUDIOMUX1, FB_AUDIOMUX1_ASRCIMUX,
ARRAY_SIZE(asrc_mux_txt), asrc_mux_txt);
static char const * const dai_mux_txt[] = {
"CH 0_1", "CH 2_3", "CH 4_5", "ADC/DMic 1",
"DMic 2", "ClassD", "DAC", "Sub"};
static struct soc_enum const dai2_mux_enum =
SOC_ENUM_SINGLE(R_AUDIOMUX1, FB_AUDIOMUX1_I2S2MUX,
ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
static struct snd_kcontrol_new const dai2_mux_dapm_enum =
SOC_DAPM_ENUM("DAI 2 Mux", dai2_mux_enum);
static struct soc_enum const dai1_mux_enum =
SOC_ENUM_SINGLE(R_AUDIOMUX1, FB_AUDIOMUX1_I2S1MUX,
ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
static struct snd_kcontrol_new const dai1_mux_dapm_enum =
SOC_DAPM_ENUM("DAI 1 Mux", dai1_mux_enum);
/* R_AUDIOMUX2 PG 0 ADDR 0x3B */
static struct soc_enum const asrc_out_mux_enum =
SOC_ENUM_SINGLE(R_AUDIOMUX2, FB_AUDIOMUX2_ASRCOMUX,
ARRAY_SIZE(asrc_mux_txt), asrc_mux_txt);
static struct soc_enum const dac_mux_enum =
SOC_ENUM_SINGLE(R_AUDIOMUX2, FB_AUDIOMUX2_DACMUX,
ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
static struct snd_kcontrol_new const dac_mux_dapm_enum =
SOC_DAPM_ENUM("DAC Mux", dac_mux_enum);
static struct soc_enum const dai3_mux_enum =
SOC_ENUM_SINGLE(R_AUDIOMUX2, FB_AUDIOMUX2_I2S3MUX,
ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
static struct snd_kcontrol_new const dai3_mux_dapm_enum =
SOC_DAPM_ENUM("DAI 3 Mux", dai3_mux_enum);
/* R_AUDIOMUX3 PG 0 ADDR 0x3C */
static char const * const sub_mux_txt[] = {
"CH 0", "CH 1", "CH 0 + 1",
"CH 2", "CH 3", "CH 2 + 3",
"CH 4", "CH 5", "CH 4 + 5",
"ADC/DMic 1 Left", "ADC/DMic 1 Right",
"ADC/DMic 1 Left Plus Right",
"DMic 2 Left", "DMic 2 Right", "DMic 2 Left Plus Right",
"ClassD Left", "ClassD Right", "ClassD Left Plus Right"};
static struct soc_enum const sub_mux_enum =
SOC_ENUM_SINGLE(R_AUDIOMUX3, FB_AUDIOMUX3_SUBMUX,
ARRAY_SIZE(sub_mux_txt), sub_mux_txt);
static struct snd_kcontrol_new const sub_mux_dapm_enum =
SOC_DAPM_ENUM("Sub Mux", sub_mux_enum);
static struct soc_enum const classd_mux_enum =
SOC_ENUM_SINGLE(R_AUDIOMUX3, FB_AUDIOMUX3_CLSSDMUX,
ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
static struct snd_kcontrol_new const classd_mux_dapm_enum =
SOC_DAPM_ENUM("ClassD Mux", classd_mux_enum);
/* R_HSDCTL1 PG 1 ADDR 0x01 */
static char const * const jack_type_txt[] = {
"3 Terminal", "4 Terminal"};
static struct soc_enum const hp_jack_type_enum =
SOC_ENUM_SINGLE(R_HSDCTL1, FB_HSDCTL1_HPJKTYPE,
ARRAY_SIZE(jack_type_txt), jack_type_txt);
static char const * const hs_det_pol_txt[] = {
"Rising", "Falling"};
static struct soc_enum const hs_det_pol_enum =
SOC_ENUM_SINGLE(R_HSDCTL1, FB_HSDCTL1_HSDETPOL,
ARRAY_SIZE(hs_det_pol_txt), hs_det_pol_txt);
/* R_HSDCTL1 PG 1 ADDR 0x02 */
static char const * const hs_mic_bias_force_txt[] = {
"Off", "Ring", "Sleeve"};
static struct soc_enum const hs_mic_bias_force_enum =
SOC_ENUM_SINGLE(R_HSDCTL2, FB_HSDCTL2_FMICBIAS1,
ARRAY_SIZE(hs_mic_bias_force_txt),
hs_mic_bias_force_txt);
static char const * const plug_type_txt[] = {
"OMTP", "CTIA", "Reserved", "Headphone"};
static struct soc_enum const plug_type_force_enum =
SOC_ENUM_SINGLE(R_HSDCTL2, FB_HSDCTL2_FPLUGTYPE,
ARRAY_SIZE(plug_type_txt), plug_type_txt);
/* R_CH0AIC PG 1 ADDR 0x06 */
static char const * const in_bst_mux_txt[] = {
"Input 1", "Input 2", "Input 3", "D2S"};
static struct soc_enum const in_bst_mux_ch0_enum =
SOC_ENUM_SINGLE(R_CH0AIC, FB_CH0AIC_INSELL,
ARRAY_SIZE(in_bst_mux_txt),
in_bst_mux_txt);
static struct snd_kcontrol_new const in_bst_mux_ch0_dapm_enum =
SOC_DAPM_ENUM("Input Boost Channel 0 Enum",
in_bst_mux_ch0_enum);
static DECLARE_TLV_DB_SCALE(in_bst_vol_tlv_arr, 0, 1000, 0);
static char const * const adc_mux_txt[] = {
"Input 1 Boost Bypass", "Input 2 Boost Bypass",
"Input 3 Boost Bypass", "Input Boost"};
static struct soc_enum const adc_mux_ch0_enum =
SOC_ENUM_SINGLE(R_CH0AIC, FB_CH0AIC_LADCIN,
ARRAY_SIZE(adc_mux_txt), adc_mux_txt);
static struct snd_kcontrol_new const adc_mux_ch0_dapm_enum =
SOC_DAPM_ENUM("ADC Channel 0 Enum", adc_mux_ch0_enum);
static char const * const in_proc_mux_txt[] = {
"ADC", "DMic"};
static struct soc_enum const in_proc_ch0_enum =
SOC_ENUM_SINGLE(R_CH0AIC, FB_CH0AIC_IPCH0S,
ARRAY_SIZE(in_proc_mux_txt), in_proc_mux_txt);
static struct snd_kcontrol_new const in_proc_mux_ch0_dapm_enum =
SOC_DAPM_ENUM("Input Processor Channel 0 Enum",
in_proc_ch0_enum);
/* R_CH1AIC PG 1 ADDR 0x07 */
static struct soc_enum const in_bst_mux_ch1_enum =
SOC_ENUM_SINGLE(R_CH1AIC, FB_CH1AIC_INSELR,
ARRAY_SIZE(in_bst_mux_txt),
in_bst_mux_txt);
static struct snd_kcontrol_new const in_bst_mux_ch1_dapm_enum =
SOC_DAPM_ENUM("Input Boost Channel 1 Enum",
in_bst_mux_ch1_enum);
static struct soc_enum const adc_mux_ch1_enum =
SOC_ENUM_SINGLE(R_CH1AIC, FB_CH1AIC_RADCIN,
ARRAY_SIZE(adc_mux_txt), adc_mux_txt);
static struct snd_kcontrol_new const adc_mux_ch1_dapm_enum =
SOC_DAPM_ENUM("ADC Channel 1 Enum", adc_mux_ch1_enum);
static struct soc_enum const in_proc_ch1_enum =
SOC_ENUM_SINGLE(R_CH1AIC, FB_CH1AIC_IPCH1S,
ARRAY_SIZE(in_proc_mux_txt), in_proc_mux_txt);
static struct snd_kcontrol_new const in_proc_mux_ch1_dapm_enum =
SOC_DAPM_ENUM("Input Processor Channel 1 Enum",
in_proc_ch1_enum);
/* R_ICTL0 PG 1 ADDR 0x0A */
static char const * const pol_txt[] = {
"Normal", "Invert"};
static struct soc_enum const in_pol_ch1_enum =
SOC_ENUM_SINGLE(R_ICTL0, FB_ICTL0_IN0POL,
ARRAY_SIZE(pol_txt), pol_txt);
static struct soc_enum const in_pol_ch0_enum =
SOC_ENUM_SINGLE(R_ICTL0, FB_ICTL0_IN1POL,
ARRAY_SIZE(pol_txt), pol_txt);
static char const * const in_proc_ch_sel_txt[] = {
"Normal", "Mono Mix to Channel 0",
"Mono Mix to Channel 1", "Add"};
static struct soc_enum const in_proc_ch01_sel_enum =
SOC_ENUM_SINGLE(R_ICTL0, FB_ICTL0_INPCH10SEL,
ARRAY_SIZE(in_proc_ch_sel_txt),
in_proc_ch_sel_txt);
/* R_ICTL1 PG 1 ADDR 0x0B */
static struct soc_enum const in_pol_ch3_enum =
SOC_ENUM_SINGLE(R_ICTL1, FB_ICTL1_IN2POL,
ARRAY_SIZE(pol_txt), pol_txt);
static struct soc_enum const in_pol_ch2_enum =
SOC_ENUM_SINGLE(R_ICTL1, FB_ICTL1_IN3POL,
ARRAY_SIZE(pol_txt), pol_txt);
static struct soc_enum const in_proc_ch23_sel_enum =
SOC_ENUM_SINGLE(R_ICTL1, FB_ICTL1_INPCH32SEL,
ARRAY_SIZE(in_proc_ch_sel_txt),
in_proc_ch_sel_txt);
/* R_MICBIAS PG 1 ADDR 0x0C */
static char const * const mic_bias_txt[] = {
"2.5V", "2.1V", "1.8V", "Vdd"};
static struct soc_enum const mic_bias_2_enum =
SOC_ENUM_SINGLE(R_MICBIAS, FB_MICBIAS_MICBOV2,
ARRAY_SIZE(mic_bias_txt), mic_bias_txt);
static struct soc_enum const mic_bias_1_enum =
SOC_ENUM_SINGLE(R_MICBIAS, FB_MICBIAS_MICBOV1,
ARRAY_SIZE(mic_bias_txt), mic_bias_txt);
/* R_PGACTL0 PG 1 ADDR 0x0D */
/* R_PGACTL1 PG 1 ADDR 0x0E */
/* R_PGACTL2 PG 1 ADDR 0x0F */
/* R_PGACTL3 PG 1 ADDR 0x10 */
static DECLARE_TLV_DB_SCALE(in_pga_vol_tlv_arr, -1725, 75, 0);
/* R_ICH0VOL PG1 ADDR 0x12 */
/* R_ICH1VOL PG1 ADDR 0x13 */
/* R_ICH2VOL PG1 ADDR 0x14 */
/* R_ICH3VOL PG1 ADDR 0x15 */
static DECLARE_TLV_DB_MINMAX(in_vol_tlv_arr, -7125, 2400);
/* R_ASRCILVOL PG1 ADDR 0x16 */
/* R_ASRCIRVOL PG1 ADDR 0x17 */
/* R_ASRCOLVOL PG1 ADDR 0x18 */
/* R_ASRCORVOL PG1 ADDR 0x19 */
static DECLARE_TLV_DB_MINMAX(asrc_vol_tlv_arr, -9562, 600);
/* R_ALCCTL0 PG1 ADDR 0x1D */
static char const * const alc_mode_txt[] = {
"ALC", "Limiter"};
static struct soc_enum const alc_mode_enum =
SOC_ENUM_SINGLE(R_ALCCTL0, FB_ALCCTL0_ALCMODE,
ARRAY_SIZE(alc_mode_txt), alc_mode_txt);
static char const * const alc_ref_text[] = {
"Channel 0", "Channel 1", "Channel 2", "Channel 3", "Peak"};
static struct soc_enum const alc_ref_enum =
SOC_ENUM_SINGLE(R_ALCCTL0, FB_ALCCTL0_ALCREF,
ARRAY_SIZE(alc_ref_text), alc_ref_text);
/* R_ALCCTL1 PG 1 ADDR 0x1E */
static DECLARE_TLV_DB_SCALE(alc_max_gain_tlv_arr, -1200, 600, 0);
static DECLARE_TLV_DB_SCALE(alc_target_tlv_arr, -2850, 150, 0);
/* R_ALCCTL2 PG 1 ADDR 0x1F */
static DECLARE_TLV_DB_SCALE(alc_min_gain_tlv_arr, -1725, 600, 0);
/* R_NGATE PG 1 ADDR 0x21 */
static DECLARE_TLV_DB_SCALE(ngth_tlv_arr, -7650, 150, 0);
static char const * const ngate_type_txt[] = {
"PGA Constant", "ADC Mute"};
static struct soc_enum const ngate_type_enum =
SOC_ENUM_SINGLE(R_NGATE, FB_NGATE_NGG,
ARRAY_SIZE(ngate_type_txt), ngate_type_txt);
/* R_DMICCTL PG 1 ADDR 0x22 */
static char const * const dmic_mono_sel_txt[] = {
"Stereo", "Mono"};
static struct soc_enum const dmic_mono_sel_enum =
SOC_ENUM_SINGLE(R_DMICCTL, FB_DMICCTL_DMONO,
ARRAY_SIZE(dmic_mono_sel_txt), dmic_mono_sel_txt);
/* R_DACCTL PG 2 ADDR 0x01 */
static struct soc_enum const dac_pol_r_enum =
SOC_ENUM_SINGLE(R_DACCTL, FB_DACCTL_DACPOLR,
ARRAY_SIZE(pol_txt), pol_txt);
static struct soc_enum const dac_pol_l_enum =
SOC_ENUM_SINGLE(R_DACCTL, FB_DACCTL_DACPOLL,
ARRAY_SIZE(pol_txt), pol_txt);
static char const * const dac_dith_txt[] = {
"Half", "Full", "Disabled", "Static"};
static struct soc_enum const dac_dith_enum =
SOC_ENUM_SINGLE(R_DACCTL, FB_DACCTL_DACDITH,
ARRAY_SIZE(dac_dith_txt), dac_dith_txt);
/* R_SPKCTL PG 2 ADDR 0x02 */
static struct soc_enum const spk_pol_r_enum =
SOC_ENUM_SINGLE(R_SPKCTL, FB_SPKCTL_SPKPOLR,
ARRAY_SIZE(pol_txt), pol_txt);
static struct soc_enum const spk_pol_l_enum =
SOC_ENUM_SINGLE(R_SPKCTL, FB_SPKCTL_SPKPOLL,
ARRAY_SIZE(pol_txt), pol_txt);
/* R_SUBCTL PG 2 ADDR 0x03 */
static struct soc_enum const sub_pol_enum =
SOC_ENUM_SINGLE(R_SUBCTL, FB_SUBCTL_SUBPOL,
ARRAY_SIZE(pol_txt), pol_txt);
/* R_MVOLL PG 2 ADDR 0x08 */
/* R_MVOLR PG 2 ADDR 0x09 */
static DECLARE_TLV_DB_MINMAX(mvol_tlv_arr, -9562, 0);
/* R_HPVOLL PG 2 ADDR 0x0A */
/* R_HPVOLR PG 2 ADDR 0x0B */
static DECLARE_TLV_DB_SCALE(hp_vol_tlv_arr, -8850, 75, 0);
/* R_SPKVOLL PG 2 ADDR 0x0C */
/* R_SPKVOLR PG 2 ADDR 0x0D */
static DECLARE_TLV_DB_SCALE(spk_vol_tlv_arr, -7725, 75, 0);
/* R_SPKEQFILT PG 3 ADDR 0x01 */
static char const * const eq_txt[] = {
"Pre Scale",
"Pre Scale + EQ Band 0",
"Pre Scale + EQ Band 0 - 1",
"Pre Scale + EQ Band 0 - 2",
"Pre Scale + EQ Band 0 - 3",
"Pre Scale + EQ Band 0 - 4",
"Pre Scale + EQ Band 0 - 5",
};
static struct soc_enum const spk_eq_enums[] = {
SOC_ENUM_SINGLE(R_SPKEQFILT, FB_SPKEQFILT_EQ2BE,
ARRAY_SIZE(eq_txt), eq_txt),
SOC_ENUM_SINGLE(R_SPKEQFILT, FB_SPKEQFILT_EQ1BE,
ARRAY_SIZE(eq_txt), eq_txt),
};
/* R_SPKMBCCTL PG 3 ADDR 0x0B */
static char const * const lvl_mode_txt[] = {
"Average", "Peak"};
static struct soc_enum const spk_mbc3_lvl_det_mode_enum =
SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_LVLMODE3,
ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
static char const * const win_sel_txt[] = {
"512", "64"};
static struct soc_enum const spk_mbc3_win_sel_enum =
SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_WINSEL3,
ARRAY_SIZE(win_sel_txt), win_sel_txt);
static struct soc_enum const spk_mbc2_lvl_det_mode_enum =
SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_LVLMODE2,
ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
static struct soc_enum const spk_mbc2_win_sel_enum =
SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_WINSEL2,
ARRAY_SIZE(win_sel_txt), win_sel_txt);
static struct soc_enum const spk_mbc1_lvl_det_mode_enum =
SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_LVLMODE1,
ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
static struct soc_enum const spk_mbc1_win_sel_enum =
SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_WINSEL1,
ARRAY_SIZE(win_sel_txt), win_sel_txt);
/* R_SPKMBCMUG1 PG 3 ADDR 0x0C */
static struct soc_enum const spk_mbc1_phase_pol_enum =
SOC_ENUM_SINGLE(R_SPKMBCMUG1, FB_SPKMBCMUG_PHASE,
ARRAY_SIZE(pol_txt), pol_txt);
static DECLARE_TLV_DB_MINMAX(mbc_mug_tlv_arr, -4650, 0);
/* R_SPKMBCTHR1 PG 3 ADDR 0x0D */
static DECLARE_TLV_DB_MINMAX(thr_tlv_arr, -9562, 0);
/* R_SPKMBCRAT1 PG 3 ADDR 0x0E */
static char const * const comp_rat_txt[] = {
"Reserved", "1.5:1", "2:1", "3:1", "4:1", "5:1", "6:1",
"7:1", "8:1", "9:1", "10:1", "11:1", "12:1", "13:1", "14:1",
"15:1", "16:1", "17:1", "18:1", "19:1", "20:1"};
static struct soc_enum const spk_mbc1_comp_rat_enum =
SOC_ENUM_SINGLE(R_SPKMBCRAT1, FB_SPKMBCRAT_RATIO,
ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
/* R_SPKMBCMUG2 PG 3 ADDR 0x13 */
static struct soc_enum const spk_mbc2_phase_pol_enum =
SOC_ENUM_SINGLE(R_SPKMBCMUG2, FB_SPKMBCMUG_PHASE,
ARRAY_SIZE(pol_txt), pol_txt);
/* R_SPKMBCRAT2 PG 3 ADDR 0x15 */
static struct soc_enum const spk_mbc2_comp_rat_enum =
SOC_ENUM_SINGLE(R_SPKMBCRAT2, FB_SPKMBCRAT_RATIO,
ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
/* R_SPKMBCMUG3 PG 3 ADDR 0x1A */
static struct soc_enum const spk_mbc3_phase_pol_enum =
SOC_ENUM_SINGLE(R_SPKMBCMUG3, FB_SPKMBCMUG_PHASE,
ARRAY_SIZE(pol_txt), pol_txt);
/* R_SPKMBCRAT3 PG 3 ADDR 0x1C */
static struct soc_enum const spk_mbc3_comp_rat_enum =
SOC_ENUM_SINGLE(R_SPKMBCRAT3, FB_SPKMBCRAT_RATIO,
ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
/* R_SPKCLECTL PG 3 ADDR 0x21 */
static struct soc_enum const spk_cle_lvl_mode_enum =
SOC_ENUM_SINGLE(R_SPKCLECTL, FB_SPKCLECTL_LVLMODE,
ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
static struct soc_enum const spk_cle_win_sel_enum =
SOC_ENUM_SINGLE(R_SPKCLECTL, FB_SPKCLECTL_WINSEL,
ARRAY_SIZE(win_sel_txt), win_sel_txt);
/* R_SPKCLEMUG PG 3 ADDR 0x22 */
static DECLARE_TLV_DB_MINMAX(cle_mug_tlv_arr, 0, 4650);
/* R_SPKCOMPRAT PG 3 ADDR 0x24 */
static struct soc_enum const spk_comp_rat_enum =
SOC_ENUM_SINGLE(R_SPKCOMPRAT, FB_SPKCOMPRAT_RATIO,
ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
/* R_SPKEXPTHR PG 3 ADDR 0x2F */
static char const * const exp_rat_txt[] = {
"Reserved", "Reserved", "1:2", "1:3",
"1:4", "1:5", "1:6", "1:7"};
static struct soc_enum const spk_exp_rat_enum =
SOC_ENUM_SINGLE(R_SPKEXPRAT, FB_SPKEXPRAT_RATIO,
ARRAY_SIZE(exp_rat_txt), exp_rat_txt);
/* R_DACEQFILT PG 4 ADDR 0x01 */
static struct soc_enum const dac_eq_enums[] = {
SOC_ENUM_SINGLE(R_DACEQFILT, FB_DACEQFILT_EQ2BE,
ARRAY_SIZE(eq_txt), eq_txt),
SOC_ENUM_SINGLE(R_DACEQFILT, FB_DACEQFILT_EQ1BE,
ARRAY_SIZE(eq_txt), eq_txt),
};
/* R_DACMBCCTL PG 4 ADDR 0x0B */
static struct soc_enum const dac_mbc3_lvl_det_mode_enum =
SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE3,
ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
static struct soc_enum const dac_mbc3_win_sel_enum =
SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL3,
ARRAY_SIZE(win_sel_txt), win_sel_txt);
static struct soc_enum const dac_mbc2_lvl_det_mode_enum =
SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE2,
ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
static struct soc_enum const dac_mbc2_win_sel_enum =
SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL2,
ARRAY_SIZE(win_sel_txt), win_sel_txt);
static struct soc_enum const dac_mbc1_lvl_det_mode_enum =
SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE1,
ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
static struct soc_enum const dac_mbc1_win_sel_enum =
SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL1,
ARRAY_SIZE(win_sel_txt), win_sel_txt);
/* R_DACMBCMUG1 PG 4 ADDR 0x0C */
static struct soc_enum const dac_mbc1_phase_pol_enum =
SOC_ENUM_SINGLE(R_DACMBCMUG1, FB_DACMBCMUG_PHASE,
ARRAY_SIZE(pol_txt), pol_txt);
/* R_DACMBCRAT1 PG 4 ADDR 0x0E */
static struct soc_enum const dac_mbc1_comp_rat_enum =
SOC_ENUM_SINGLE(R_DACMBCRAT1, FB_DACMBCRAT_RATIO,
ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
/* R_DACMBCMUG2 PG 4 ADDR 0x13 */
static struct soc_enum const dac_mbc2_phase_pol_enum =
SOC_ENUM_SINGLE(R_DACMBCMUG2, FB_DACMBCMUG_PHASE,
ARRAY_SIZE(pol_txt), pol_txt);
/* R_DACMBCRAT2 PG 4 ADDR 0x15 */
static struct soc_enum const dac_mbc2_comp_rat_enum =
SOC_ENUM_SINGLE(R_DACMBCRAT2, FB_DACMBCRAT_RATIO,
ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
/* R_DACMBCMUG3 PG 4 ADDR 0x1A */
static struct soc_enum const dac_mbc3_phase_pol_enum =
SOC_ENUM_SINGLE(R_DACMBCMUG3, FB_DACMBCMUG_PHASE,
ARRAY_SIZE(pol_txt), pol_txt);
/* R_DACMBCRAT3 PG 4 ADDR 0x1C */
static struct soc_enum const dac_mbc3_comp_rat_enum =
SOC_ENUM_SINGLE(R_DACMBCRAT3, FB_DACMBCRAT_RATIO,
ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
/* R_DACCLECTL PG 4 ADDR 0x21 */
static struct soc_enum const dac_cle_lvl_mode_enum =
SOC_ENUM_SINGLE(R_DACCLECTL, FB_DACCLECTL_LVLMODE,
ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
static struct soc_enum const dac_cle_win_sel_enum =
SOC_ENUM_SINGLE(R_DACCLECTL, FB_DACCLECTL_WINSEL,
ARRAY_SIZE(win_sel_txt), win_sel_txt);
/* R_DACCOMPRAT PG 4 ADDR 0x24 */
static struct soc_enum const dac_comp_rat_enum =
SOC_ENUM_SINGLE(R_DACCOMPRAT, FB_DACCOMPRAT_RATIO,
ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
/* R_DACEXPRAT PG 4 ADDR 0x30 */
static struct soc_enum const dac_exp_rat_enum =
SOC_ENUM_SINGLE(R_DACEXPRAT, FB_DACEXPRAT_RATIO,
ARRAY_SIZE(exp_rat_txt), exp_rat_txt);
/* R_SUBEQFILT PG 5 ADDR 0x01 */
static struct soc_enum const sub_eq_enums[] = {
SOC_ENUM_SINGLE(R_SUBEQFILT, FB_SUBEQFILT_EQ2BE,
ARRAY_SIZE(eq_txt), eq_txt),
SOC_ENUM_SINGLE(R_SUBEQFILT, FB_SUBEQFILT_EQ1BE,
ARRAY_SIZE(eq_txt), eq_txt),
};
/* R_SUBMBCCTL PG 5 ADDR 0x0B */
static struct soc_enum const sub_mbc3_lvl_det_mode_enum =
SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_LVLMODE3,
ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
static struct soc_enum const sub_mbc3_win_sel_enum =
SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_WINSEL3,
ARRAY_SIZE(win_sel_txt), win_sel_txt);
static struct soc_enum const sub_mbc2_lvl_det_mode_enum =
SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_LVLMODE2,
ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
static struct soc_enum const sub_mbc2_win_sel_enum =
SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_WINSEL2,
ARRAY_SIZE(win_sel_txt), win_sel_txt);
static struct soc_enum const sub_mbc1_lvl_det_mode_enum =
SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_LVLMODE1,
ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
static struct soc_enum const sub_mbc1_win_sel_enum =
SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_WINSEL1,
ARRAY_SIZE(win_sel_txt), win_sel_txt);
/* R_SUBMBCMUG1 PG 5 ADDR 0x0C */
static struct soc_enum const sub_mbc1_phase_pol_enum =
SOC_ENUM_SINGLE(R_SUBMBCMUG1, FB_SUBMBCMUG_PHASE,
ARRAY_SIZE(pol_txt), pol_txt);
/* R_SUBMBCRAT1 PG 5 ADDR 0x0E */
static struct soc_enum const sub_mbc1_comp_rat_enum =
SOC_ENUM_SINGLE(R_SUBMBCRAT1, FB_SUBMBCRAT_RATIO,
ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
/* R_SUBMBCMUG2 PG 5 ADDR 0x13 */
static struct soc_enum const sub_mbc2_phase_pol_enum =
SOC_ENUM_SINGLE(R_SUBMBCMUG2, FB_SUBMBCMUG_PHASE,
ARRAY_SIZE(pol_txt), pol_txt);
/* R_SUBMBCRAT2 PG 5 ADDR 0x15 */
static struct soc_enum const sub_mbc2_comp_rat_enum =
SOC_ENUM_SINGLE(R_SUBMBCRAT2, FB_SUBMBCRAT_RATIO,
ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
/* R_SUBMBCMUG3 PG 5 ADDR 0x1A */
static struct soc_enum const sub_mbc3_phase_pol_enum =
SOC_ENUM_SINGLE(R_SUBMBCMUG3, FB_SUBMBCMUG_PHASE,
ARRAY_SIZE(pol_txt), pol_txt);
/* R_SUBMBCRAT3 PG 5 ADDR 0x1C */
static struct soc_enum const sub_mbc3_comp_rat_enum =
SOC_ENUM_SINGLE(R_SUBMBCRAT3, FB_SUBMBCRAT_RATIO,
ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
/* R_SUBCLECTL PG 5 ADDR 0x21 */
static struct soc_enum const sub_cle_lvl_mode_enum =
SOC_ENUM_SINGLE(R_SUBCLECTL, FB_SUBCLECTL_LVLMODE,
ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
static struct soc_enum const sub_cle_win_sel_enum =
SOC_ENUM_SINGLE(R_SUBCLECTL, FB_SUBCLECTL_WINSEL,
ARRAY_SIZE(win_sel_txt), win_sel_txt);
/* R_SUBCOMPRAT PG 5 ADDR 0x24 */
static struct soc_enum const sub_comp_rat_enum =
SOC_ENUM_SINGLE(R_SUBCOMPRAT, FB_SUBCOMPRAT_RATIO,
ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
/* R_SUBEXPRAT PG 5 ADDR 0x30 */
static struct soc_enum const sub_exp_rat_enum =
SOC_ENUM_SINGLE(R_SUBEXPRAT, FB_SUBEXPRAT_RATIO,
ARRAY_SIZE(exp_rat_txt), exp_rat_txt);
static int bytes_info_ext(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *ucontrol)
{
struct coeff_ram_ctl *ctl =
(struct coeff_ram_ctl *)kcontrol->private_value;
struct soc_bytes_ext *params = &ctl->bytes_ext;
ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
ucontrol->count = params->max;
return 0;
}
/* CH 0_1 Input Mux */
static char const * const ch_0_1_mux_txt[] = {"DAI 1", "TDM 0_1"};
static struct soc_enum const ch_0_1_mux_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
ARRAY_SIZE(ch_0_1_mux_txt), ch_0_1_mux_txt);
static struct snd_kcontrol_new const ch_0_1_mux_dapm_enum =
SOC_DAPM_ENUM("CH 0_1 Input Mux", ch_0_1_mux_enum);
/* CH 2_3 Input Mux */
static char const * const ch_2_3_mux_txt[] = {"DAI 2", "TDM 2_3"};
static struct soc_enum const ch_2_3_mux_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
ARRAY_SIZE(ch_2_3_mux_txt), ch_2_3_mux_txt);
static struct snd_kcontrol_new const ch_2_3_mux_dapm_enum =
SOC_DAPM_ENUM("CH 2_3 Input Mux", ch_2_3_mux_enum);
/* CH 4_5 Input Mux */
static char const * const ch_4_5_mux_txt[] = {"DAI 3", "TDM 4_5"};
static struct soc_enum const ch_4_5_mux_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
ARRAY_SIZE(ch_4_5_mux_txt), ch_4_5_mux_txt);
static struct snd_kcontrol_new const ch_4_5_mux_dapm_enum =
SOC_DAPM_ENUM("CH 4_5 Input Mux", ch_4_5_mux_enum);
#define COEFF_RAM_CTL(xname, xcount, xaddr) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
.info = bytes_info_ext, \
.get = coeff_ram_get, .put = coeff_ram_put, \
.private_value = (unsigned long)&(struct coeff_ram_ctl) { \
.addr = xaddr, \
.bytes_ext = {.max = xcount, }, \
} \
}
static struct snd_kcontrol_new const tscs454_snd_controls[] = {
/* R_PLLCTL PG 0 ADDR 0x15 */
SOC_ENUM("PLL BCLK Input", bclk_sel_enum),
/* R_ISRC PG 0 ADDR 0x16 */
SOC_ENUM("Internal Rate", isrc_br_enum),
SOC_ENUM("Internal Rate Multiple", isrc_bm_enum),
/* R_SCLKCTL PG 0 ADDR 0x18 */
SOC_ENUM("ADC Modular Rate", adc_modular_rate_enum),
SOC_ENUM("DAC Modular Rate", dac_modular_rate_enum),
/* R_ASRC PG 0 ADDR 0x28 */
SOC_SINGLE("ASRC Out High Bandwidth Switch",
R_ASRC, FB_ASRC_ASRCOBW, 1, 0),
SOC_SINGLE("ASRC In High Bandwidth Switch",
R_ASRC, FB_ASRC_ASRCIBW, 1, 0),
/* R_I2SIDCTL PG 0 ADDR 0x38 */
SOC_ENUM("I2S 1 Data In Control", data_in_ctrl_enums[0]),
SOC_ENUM("I2S 2 Data In Control", data_in_ctrl_enums[1]),
SOC_ENUM("I2S 3 Data In Control", data_in_ctrl_enums[2]),
/* R_I2SODCTL PG 0 ADDR 0x39 */
SOC_ENUM("I2S 1 Data Out Control", data_out_ctrl_enums[0]),
SOC_ENUM("I2S 2 Data Out Control", data_out_ctrl_enums[1]),
SOC_ENUM("I2S 3 Data Out Control", data_out_ctrl_enums[2]),
/* R_AUDIOMUX1 PG 0 ADDR 0x3A */
SOC_ENUM("ASRC In", asrc_in_mux_enum),
/* R_AUDIOMUX2 PG 0 ADDR 0x3B */
SOC_ENUM("ASRC Out", asrc_out_mux_enum),
/* R_HSDCTL1 PG 1 ADDR 0x01 */
SOC_ENUM("Headphone Jack Type", hp_jack_type_enum),
SOC_ENUM("Headset Detection Polarity", hs_det_pol_enum),
SOC_SINGLE("Headphone Detection Switch",
R_HSDCTL1, FB_HSDCTL1_HPID_EN, 1, 0),
SOC_SINGLE("Headset OMTP/CTIA Switch",
R_HSDCTL1, FB_HSDCTL1_GBLHS_EN, 1, 0),
/* R_HSDCTL1 PG 1 ADDR 0x02 */
SOC_ENUM("Headset Mic Bias Force", hs_mic_bias_force_enum),
SOC_SINGLE("Manual Mic Bias Switch",
R_HSDCTL2, FB_HSDCTL2_MB1MODE, 1, 0),
SOC_SINGLE("Ring/Sleeve Auto Switch",
R_HSDCTL2, FB_HSDCTL2_SWMODE, 1, 0),
SOC_ENUM("Manual Mode Plug Type", plug_type_force_enum),
/* R_CH0AIC PG 1 ADDR 0x06 */
SOC_SINGLE_TLV("Input Boost Channel 0 Volume", R_CH0AIC,
FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr),
/* R_CH1AIC PG 1 ADDR 0x07 */
SOC_SINGLE_TLV("Input Boost Channel 1 Volume", R_CH1AIC,
FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr),
/* R_CH2AIC PG 1 ADDR 0x08 */
SOC_SINGLE_TLV("Input Boost Channel 2 Volume", R_CH2AIC,
FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr),
/* R_CH3AIC PG 1 ADDR 0x09 */
SOC_SINGLE_TLV("Input Boost Channel 3 Volume", R_CH3AIC,
FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr),
/* R_ICTL0 PG 1 ADDR 0x0A */
SOC_ENUM("Input Channel 1 Polarity", in_pol_ch1_enum),
SOC_ENUM("Input Channel 0 Polarity", in_pol_ch0_enum),
SOC_ENUM("Input Processor Channel 0/1 Operation",
in_proc_ch01_sel_enum),
SOC_SINGLE("Input Channel 1 Mute Switch",
R_ICTL0, FB_ICTL0_IN1MUTE, 1, 0),
SOC_SINGLE("Input Channel 0 Mute Switch",
R_ICTL0, FB_ICTL0_IN0MUTE, 1, 0),
SOC_SINGLE("Input Channel 1 HPF Disable Switch",
R_ICTL0, FB_ICTL0_IN1HP, 1, 0),
SOC_SINGLE("Input Channel 0 HPF Disable Switch",
R_ICTL0, FB_ICTL0_IN0HP, 1, 0),
/* R_ICTL1 PG 1 ADDR 0x0B */
SOC_ENUM("Input Channel 3 Polarity", in_pol_ch3_enum),
SOC_ENUM("Input Channel 2 Polarity", in_pol_ch2_enum),
SOC_ENUM("Input Processor Channel 2/3 Operation",
in_proc_ch23_sel_enum),
SOC_SINGLE("Input Channel 3 Mute Switch",
R_ICTL1, FB_ICTL1_IN3MUTE, 1, 0),
SOC_SINGLE("Input Channel 2 Mute Switch",
R_ICTL1, FB_ICTL1_IN2MUTE, 1, 0),
SOC_SINGLE("Input Channel 3 HPF Disable Switch",
R_ICTL1, FB_ICTL1_IN3HP, 1, 0),
SOC_SINGLE("Input Channel 2 HPF Disable Switch",
R_ICTL1, FB_ICTL1_IN2HP, 1, 0),
/* R_MICBIAS PG 1 ADDR 0x0C */
SOC_ENUM("Mic Bias 2 Voltage", mic_bias_2_enum),
SOC_ENUM("Mic Bias 1 Voltage", mic_bias_1_enum),
/* R_PGACTL0 PG 1 ADDR 0x0D */
SOC_SINGLE("Input Channel 0 PGA Mute Switch",
R_PGACTL0, FB_PGACTL_PGAMUTE, 1, 0),
SOC_SINGLE_TLV("Input Channel 0 PGA Volume", R_PGACTL0,
FB_PGACTL_PGAVOL,
FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr),
/* R_PGACTL1 PG 1 ADDR 0x0E */
SOC_SINGLE("Input Channel 1 PGA Mute Switch",
R_PGACTL1, FB_PGACTL_PGAMUTE, 1, 0),
SOC_SINGLE_TLV("Input Channel 1 PGA Volume", R_PGACTL1,
FB_PGACTL_PGAVOL,
FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr),
/* R_PGACTL2 PG 1 ADDR 0x0F */
SOC_SINGLE("Input Channel 2 PGA Mute Switch",
R_PGACTL2, FB_PGACTL_PGAMUTE, 1, 0),
SOC_SINGLE_TLV("Input Channel 2 PGA Volume", R_PGACTL2,
FB_PGACTL_PGAVOL,
FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr),
/* R_PGACTL3 PG 1 ADDR 0x10 */
SOC_SINGLE("Input Channel 3 PGA Mute Switch",
R_PGACTL3, FB_PGACTL_PGAMUTE, 1, 0),
SOC_SINGLE_TLV("Input Channel 3 PGA Volume", R_PGACTL3,
FB_PGACTL_PGAVOL,
FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr),
/* R_ICH0VOL PG 1 ADDR 0x12 */
SOC_SINGLE_TLV("Input Channel 0 Volume", R_ICH0VOL,
FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr),
/* R_ICH1VOL PG 1 ADDR 0x13 */
SOC_SINGLE_TLV("Input Channel 1 Volume", R_ICH1VOL,
FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr),
/* R_ICH2VOL PG 1 ADDR 0x14 */
SOC_SINGLE_TLV("Input Channel 2 Volume", R_ICH2VOL,
FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr),
/* R_ICH3VOL PG 1 ADDR 0x15 */
SOC_SINGLE_TLV("Input Channel 3 Volume", R_ICH3VOL,
FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr),
/* R_ASRCILVOL PG 1 ADDR 0x16 */
SOC_SINGLE_TLV("ASRC Input Left Volume", R_ASRCILVOL,
FB_ASRCILVOL_ASRCILVOL, FM_ASRCILVOL_ASRCILVOL,
0, asrc_vol_tlv_arr),
/* R_ASRCIRVOL PG 1 ADDR 0x17 */
SOC_SINGLE_TLV("ASRC Input Right Volume", R_ASRCIRVOL,
FB_ASRCIRVOL_ASRCIRVOL, FM_ASRCIRVOL_ASRCIRVOL,
0, asrc_vol_tlv_arr),
/* R_ASRCOLVOL PG 1 ADDR 0x18 */
SOC_SINGLE_TLV("ASRC Output Left Volume", R_ASRCOLVOL,
FB_ASRCOLVOL_ASRCOLVOL, FM_ASRCOLVOL_ASRCOLVOL,
0, asrc_vol_tlv_arr),
/* R_ASRCORVOL PG 1 ADDR 0x19 */
SOC_SINGLE_TLV("ASRC Output Right Volume", R_ASRCORVOL,
FB_ASRCORVOL_ASRCOLVOL, FM_ASRCORVOL_ASRCOLVOL,
0, asrc_vol_tlv_arr),
/* R_IVOLCTLU PG 1 ADDR 0x1C */
/* R_ALCCTL0 PG 1 ADDR 0x1D */
SOC_ENUM("ALC Mode", alc_mode_enum),
SOC_ENUM("ALC Reference", alc_ref_enum),
SOC_SINGLE("Input Channel 3 ALC Switch",
R_ALCCTL0, FB_ALCCTL0_ALCEN3, 1, 0),
SOC_SINGLE("Input Channel 2 ALC Switch",
R_ALCCTL0, FB_ALCCTL0_ALCEN2, 1, 0),
SOC_SINGLE("Input Channel 1 ALC Switch",
R_ALCCTL0, FB_ALCCTL0_ALCEN1, 1, 0),
SOC_SINGLE("Input Channel 0 ALC Switch",
R_ALCCTL0, FB_ALCCTL0_ALCEN0, 1, 0),
/* R_ALCCTL1 PG 1 ADDR 0x1E */
SOC_SINGLE_TLV("ALC Max Gain Volume", R_ALCCTL1,
FB_ALCCTL1_MAXGAIN, FM_ALCCTL1_MAXGAIN,
0, alc_max_gain_tlv_arr),
SOC_SINGLE_TLV("ALC Target Volume", R_ALCCTL1,
FB_ALCCTL1_ALCL, FM_ALCCTL1_ALCL,
0, alc_target_tlv_arr),
/* R_ALCCTL2 PG 1 ADDR 0x1F */
SOC_SINGLE("ALC Zero Cross Switch",
R_ALCCTL2, FB_ALCCTL2_ALCZC, 1, 0),
SOC_SINGLE_TLV("ALC Min Gain Volume", R_ALCCTL2,
FB_ALCCTL2_MINGAIN, FM_ALCCTL2_MINGAIN,
0, alc_min_gain_tlv_arr),
SOC_SINGLE_RANGE("ALC Hold", R_ALCCTL2,
FB_ALCCTL2_HLD, 0, FM_ALCCTL2_HLD, 0),
/* R_ALCCTL3 PG 1 ADDR 0x20 */
SOC_SINGLE_RANGE("ALC Decay", R_ALCCTL3,
FB_ALCCTL3_DCY, 0, FM_ALCCTL3_DCY, 0),
SOC_SINGLE_RANGE("ALC Attack", R_ALCCTL3,
FB_ALCCTL3_ATK, 0, FM_ALCCTL3_ATK, 0),
/* R_NGATE PG 1 ADDR 0x21 */
SOC_SINGLE_TLV("Noise Gate Threshold Volume", R_NGATE,
FB_NGATE_NGTH, FM_NGATE_NGTH, 0, ngth_tlv_arr),
SOC_ENUM("Noise Gate Type", ngate_type_enum),
SOC_SINGLE("Noise Gate Switch", R_NGATE, FB_NGATE_NGAT, 1, 0),
/* R_DMICCTL PG 1 ADDR 0x22 */
SOC_SINGLE("Digital Mic 2 Switch", R_DMICCTL, FB_DMICCTL_DMIC2EN, 1, 0),
SOC_SINGLE("Digital Mic 1 Switch", R_DMICCTL, FB_DMICCTL_DMIC1EN, 1, 0),
SOC_ENUM("Digital Mic Mono Select", dmic_mono_sel_enum),
/* R_DACCTL PG 2 ADDR 0x01 */
SOC_ENUM("DAC Polarity Left", dac_pol_r_enum),
SOC_ENUM("DAC Polarity Right", dac_pol_l_enum),
SOC_ENUM("DAC Dither", dac_dith_enum),
SOC_SINGLE("DAC Mute Switch", R_DACCTL, FB_DACCTL_DACMUTE, 1, 0),
SOC_SINGLE("DAC De-Emphasis Switch", R_DACCTL, FB_DACCTL_DACDEM, 1, 0),
/* R_SPKCTL PG 2 ADDR 0x02 */
SOC_ENUM("Speaker Polarity Right", spk_pol_r_enum),
SOC_ENUM("Speaker Polarity Left", spk_pol_l_enum),
SOC_SINGLE("Speaker Mute Switch", R_SPKCTL, FB_SPKCTL_SPKMUTE, 1, 0),
SOC_SINGLE("Speaker De-Emphasis Switch",
R_SPKCTL, FB_SPKCTL_SPKDEM, 1, 0),
/* R_SUBCTL PG 2 ADDR 0x03 */
SOC_ENUM("Sub Polarity", sub_pol_enum),
SOC_SINGLE("SUB Mute Switch", R_SUBCTL, FB_SUBCTL_SUBMUTE, 1, 0),
SOC_SINGLE("Sub De-Emphasis Switch", R_SUBCTL, FB_SUBCTL_SUBDEM, 1, 0),
/* R_DCCTL PG 2 ADDR 0x04 */
SOC_SINGLE("Sub DC Removal Switch", R_DCCTL, FB_DCCTL_SUBDCBYP, 1, 1),
SOC_SINGLE("DAC DC Removal Switch", R_DCCTL, FB_DCCTL_DACDCBYP, 1, 1),
SOC_SINGLE("Speaker DC Removal Switch",
R_DCCTL, FB_DCCTL_SPKDCBYP, 1, 1),
SOC_SINGLE("DC Removal Coefficient Switch", R_DCCTL, FB_DCCTL_DCCOEFSEL,
FM_DCCTL_DCCOEFSEL, 0),
/* R_OVOLCTLU PG 2 ADDR 0x06 */
SOC_SINGLE("Output Fade Switch", R_OVOLCTLU, FB_OVOLCTLU_OFADE, 1, 0),
/* R_MVOLL PG 2 ADDR 0x08 */
/* R_MVOLR PG 2 ADDR 0x09 */
SOC_DOUBLE_R_TLV("Master Volume", R_MVOLL, R_MVOLR,
FB_MVOLL_MVOL_L, FM_MVOLL_MVOL_L, 0, mvol_tlv_arr),
/* R_HPVOLL PG 2 ADDR 0x0A */
/* R_HPVOLR PG 2 ADDR 0x0B */
SOC_DOUBLE_R_TLV("Headphone Volume", R_HPVOLL, R_HPVOLR,
FB_HPVOLL_HPVOL_L, FM_HPVOLL_HPVOL_L, 0,
hp_vol_tlv_arr),
/* R_SPKVOLL PG 2 ADDR 0x0C */
/* R_SPKVOLR PG 2 ADDR 0x0D */
SOC_DOUBLE_R_TLV("Speaker Volume", R_SPKVOLL, R_SPKVOLR,
FB_SPKVOLL_SPKVOL_L, FM_SPKVOLL_SPKVOL_L, 0,
spk_vol_tlv_arr),
/* R_SUBVOL PG 2 ADDR 0x10 */
SOC_SINGLE_TLV("Sub Volume", R_SUBVOL,
FB_SUBVOL_SUBVOL, FM_SUBVOL_SUBVOL, 0, spk_vol_tlv_arr),
/* R_SPKEQFILT PG 3 ADDR 0x01 */
SOC_SINGLE("Speaker EQ 2 Switch",
R_SPKEQFILT, FB_SPKEQFILT_EQ2EN, 1, 0),
SOC_ENUM("Speaker EQ 2 Band", spk_eq_enums[0]),
SOC_SINGLE("Speaker EQ 1 Switch",
R_SPKEQFILT, FB_SPKEQFILT_EQ1EN, 1, 0),
SOC_ENUM("Speaker EQ 1 Band", spk_eq_enums[1]),
/* R_SPKMBCEN PG 3 ADDR 0x0A */
SOC_SINGLE("Speaker MBC 3 Switch",
R_SPKMBCEN, FB_SPKMBCEN_MBCEN3, 1, 0),
SOC_SINGLE("Speaker MBC 2 Switch",
R_SPKMBCEN, FB_SPKMBCEN_MBCEN2, 1, 0),
SOC_SINGLE("Speaker MBC 1 Switch",
R_SPKMBCEN, FB_SPKMBCEN_MBCEN1, 1, 0),
/* R_SPKMBCCTL PG 3 ADDR 0x0B */
SOC_ENUM("Speaker MBC 3 Mode", spk_mbc3_lvl_det_mode_enum),
SOC_ENUM("Speaker MBC 3 Window", spk_mbc3_win_sel_enum),
SOC_ENUM("Speaker MBC 2 Mode", spk_mbc2_lvl_det_mode_enum),
SOC_ENUM("Speaker MBC 2 Window", spk_mbc2_win_sel_enum),
SOC_ENUM("Speaker MBC 1 Mode", spk_mbc1_lvl_det_mode_enum),
SOC_ENUM("Speaker MBC 1 Window", spk_mbc1_win_sel_enum),
/* R_SPKMBCMUG1 PG 3 ADDR 0x0C */
SOC_ENUM("Speaker MBC 1 Phase Polarity", spk_mbc1_phase_pol_enum),
SOC_SINGLE_TLV("Speaker MBC1 Make-Up Gain Volume", R_SPKMBCMUG1,
FB_SPKMBCMUG_MUGAIN, FM_SPKMBCMUG_MUGAIN,
0, mbc_mug_tlv_arr),
/* R_SPKMBCTHR1 PG 3 ADDR 0x0D */
SOC_SINGLE_TLV("Speaker MBC 1 Compressor Threshold Volume",
R_SPKMBCTHR1, FB_SPKMBCTHR_THRESH, FM_SPKMBCTHR_THRESH,
0, thr_tlv_arr),
/* R_SPKMBCRAT1 PG 3 ADDR 0x0E */
SOC_ENUM("Speaker MBC 1 Compressor Ratio", spk_mbc1_comp_rat_enum),
/* R_SPKMBCATK1L PG 3 ADDR 0x0F */
/* R_SPKMBCATK1H PG 3 ADDR 0x10 */
SND_SOC_BYTES("Speaker MBC 1 Attack", R_SPKMBCATK1L, 2),
/* R_SPKMBCREL1L PG 3 ADDR 0x11 */
/* R_SPKMBCREL1H PG 3 ADDR 0x12 */
SND_SOC_BYTES("Speaker MBC 1 Release", R_SPKMBCREL1L, 2),
/* R_SPKMBCMUG2 PG 3 ADDR 0x13 */
SOC_ENUM("Speaker MBC 2 Phase Polarity", spk_mbc2_phase_pol_enum),
SOC_SINGLE_TLV("Speaker MBC2 Make-Up Gain Volume", R_SPKMBCMUG2,
FB_SPKMBCMUG_MUGAIN, FM_SPKMBCMUG_MUGAIN,
0, mbc_mug_tlv_arr),
/* R_SPKMBCTHR2 PG 3 ADDR 0x14 */
SOC_SINGLE_TLV("Speaker MBC 2 Compressor Threshold Volume",
R_SPKMBCTHR2, FB_SPKMBCTHR_THRESH, FM_SPKMBCTHR_THRESH,
0, thr_tlv_arr),
/* R_SPKMBCRAT2 PG 3 ADDR 0x15 */
SOC_ENUM("Speaker MBC 2 Compressor Ratio", spk_mbc2_comp_rat_enum),
/* R_SPKMBCATK2L PG 3 ADDR 0x16 */
/* R_SPKMBCATK2H PG 3 ADDR 0x17 */
SND_SOC_BYTES("Speaker MBC 2 Attack", R_SPKMBCATK2L, 2),
/* R_SPKMBCREL2L PG 3 ADDR 0x18 */
/* R_SPKMBCREL2H PG 3 ADDR 0x19 */
SND_SOC_BYTES("Speaker MBC 2 Release", R_SPKMBCREL2L, 2),
/* R_SPKMBCMUG3 PG 3 ADDR 0x1A */
SOC_ENUM("Speaker MBC 3 Phase Polarity", spk_mbc3_phase_pol_enum),
SOC_SINGLE_TLV("Speaker MBC 3 Make-Up Gain Volume", R_SPKMBCMUG3,
FB_SPKMBCMUG_MUGAIN, FM_SPKMBCMUG_MUGAIN,
0, mbc_mug_tlv_arr),
/* R_SPKMBCTHR3 PG 3 ADDR 0x1B */
SOC_SINGLE_TLV("Speaker MBC 3 Threshold Volume", R_SPKMBCTHR3,
FB_SPKMBCTHR_THRESH, FM_SPKMBCTHR_THRESH,
0, thr_tlv_arr),
/* R_SPKMBCRAT3 PG 3 ADDR 0x1C */
SOC_ENUM("Speaker MBC 3 Compressor Ratio", spk_mbc3_comp_rat_enum),
/* R_SPKMBCATK3L PG 3 ADDR 0x1D */
/* R_SPKMBCATK3H PG 3 ADDR 0x1E */
SND_SOC_BYTES("Speaker MBC 3 Attack", R_SPKMBCATK3L, 3),
/* R_SPKMBCREL3L PG 3 ADDR 0x1F */
/* R_SPKMBCREL3H PG 3 ADDR 0x20 */
SND_SOC_BYTES("Speaker MBC 3 Release", R_SPKMBCREL3L, 3),
/* R_SPKCLECTL PG 3 ADDR 0x21 */
SOC_ENUM("Speaker CLE Level Mode", spk_cle_lvl_mode_enum),
SOC_ENUM("Speaker CLE Window", spk_cle_win_sel_enum),
SOC_SINGLE("Speaker CLE Expander Switch",
R_SPKCLECTL, FB_SPKCLECTL_EXPEN, 1, 0),
SOC_SINGLE("Speaker CLE Limiter Switch",
R_SPKCLECTL, FB_SPKCLECTL_LIMEN, 1, 0),
SOC_SINGLE("Speaker CLE Compressor Switch",
R_SPKCLECTL, FB_SPKCLECTL_COMPEN, 1, 0),
/* R_SPKCLEMUG PG 3 ADDR 0x22 */
SOC_SINGLE_TLV("Speaker CLE Make-Up Gain Volume", R_SPKCLEMUG,
FB_SPKCLEMUG_MUGAIN, FM_SPKCLEMUG_MUGAIN,
0, cle_mug_tlv_arr),
/* R_SPKCOMPTHR PG 3 ADDR 0x23 */
SOC_SINGLE_TLV("Speaker Compressor Threshold Volume", R_SPKCOMPTHR,
FB_SPKCOMPTHR_THRESH, FM_SPKCOMPTHR_THRESH,
0, thr_tlv_arr),
/* R_SPKCOMPRAT PG 3 ADDR 0x24 */
SOC_ENUM("Speaker Compressor Ratio", spk_comp_rat_enum),
/* R_SPKCOMPATKL PG 3 ADDR 0x25 */
/* R_SPKCOMPATKH PG 3 ADDR 0x26 */
SND_SOC_BYTES("Speaker Compressor Attack", R_SPKCOMPATKL, 2),
/* R_SPKCOMPRELL PG 3 ADDR 0x27 */
/* R_SPKCOMPRELH PG 3 ADDR 0x28 */
SND_SOC_BYTES("Speaker Compressor Release", R_SPKCOMPRELL, 2),
/* R_SPKLIMTHR PG 3 ADDR 0x29 */
SOC_SINGLE_TLV("Speaker Limiter Threshold Volume", R_SPKLIMTHR,
FB_SPKLIMTHR_THRESH, FM_SPKLIMTHR_THRESH,
0, thr_tlv_arr),
/* R_SPKLIMTGT PG 3 ADDR 0x2A */
SOC_SINGLE_TLV("Speaker Limiter Target Volume", R_SPKLIMTGT,
FB_SPKLIMTGT_TARGET, FM_SPKLIMTGT_TARGET,
0, thr_tlv_arr),
/* R_SPKLIMATKL PG 3 ADDR 0x2B */
/* R_SPKLIMATKH PG 3 ADDR 0x2C */
SND_SOC_BYTES("Speaker Limiter Attack", R_SPKLIMATKL, 2),
/* R_SPKLIMRELL PG 3 ADDR 0x2D */
/* R_SPKLIMRELR PG 3 ADDR 0x2E */
SND_SOC_BYTES("Speaker Limiter Release", R_SPKLIMRELL, 2),
/* R_SPKEXPTHR PG 3 ADDR 0x2F */
SOC_SINGLE_TLV("Speaker Expander Threshold Volume", R_SPKEXPTHR,
FB_SPKEXPTHR_THRESH, FM_SPKEXPTHR_THRESH,
0, thr_tlv_arr),
/* R_SPKEXPRAT PG 3 ADDR 0x30 */
SOC_ENUM("Speaker Expander Ratio", spk_exp_rat_enum),
/* R_SPKEXPATKL PG 3 ADDR 0x31 */
/* R_SPKEXPATKR PG 3 ADDR 0x32 */
SND_SOC_BYTES("Speaker Expander Attack", R_SPKEXPATKL, 2),
/* R_SPKEXPRELL PG 3 ADDR 0x33 */
/* R_SPKEXPRELR PG 3 ADDR 0x34 */
SND_SOC_BYTES("Speaker Expander Release", R_SPKEXPRELL, 2),
/* R_SPKFXCTL PG 3 ADDR 0x35 */
SOC_SINGLE("Speaker 3D Switch", R_SPKFXCTL, FB_SPKFXCTL_3DEN, 1, 0),
SOC_SINGLE("Speaker Treble Enhancement Switch",
R_SPKFXCTL, FB_SPKFXCTL_TEEN, 1, 0),
SOC_SINGLE("Speaker Treble NLF Switch",
R_SPKFXCTL, FB_SPKFXCTL_TNLFBYP, 1, 1),
SOC_SINGLE("Speaker Bass Enhancement Switch",
R_SPKFXCTL, FB_SPKFXCTL_BEEN, 1, 0),
SOC_SINGLE("Speaker Bass NLF Switch",
R_SPKFXCTL, FB_SPKFXCTL_BNLFBYP, 1, 1),
/* R_DACEQFILT PG 4 ADDR 0x01 */
SOC_SINGLE("DAC EQ 2 Switch",
R_DACEQFILT, FB_DACEQFILT_EQ2EN, 1, 0),
SOC_ENUM("DAC EQ 2 Band", dac_eq_enums[0]),
SOC_SINGLE("DAC EQ 1 Switch", R_DACEQFILT, FB_DACEQFILT_EQ1EN, 1, 0),
SOC_ENUM("DAC EQ 1 Band", dac_eq_enums[1]),
/* R_DACMBCEN PG 4 ADDR 0x0A */
SOC_SINGLE("DAC MBC 3 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN3, 1, 0),
SOC_SINGLE("DAC MBC 2 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN2, 1, 0),
SOC_SINGLE("DAC MBC 1 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN1, 1, 0),
/* R_DACMBCCTL PG 4 ADDR 0x0B */
SOC_ENUM("DAC MBC 3 Mode", dac_mbc3_lvl_det_mode_enum),
SOC_ENUM("DAC MBC 3 Window", dac_mbc3_win_sel_enum),
SOC_ENUM("DAC MBC 2 Mode", dac_mbc2_lvl_det_mode_enum),
SOC_ENUM("DAC MBC 2 Window", dac_mbc2_win_sel_enum),
SOC_ENUM("DAC MBC 1 Mode", dac_mbc1_lvl_det_mode_enum),
SOC_ENUM("DAC MBC 1 Window", dac_mbc1_win_sel_enum),
/* R_DACMBCMUG1 PG 4 ADDR 0x0C */
SOC_ENUM("DAC MBC 1 Phase Polarity", dac_mbc1_phase_pol_enum),
SOC_SINGLE_TLV("DAC MBC 1 Make-Up Gain Volume", R_DACMBCMUG1,
FB_DACMBCMUG_MUGAIN, FM_DACMBCMUG_MUGAIN,
0, mbc_mug_tlv_arr),
/* R_DACMBCTHR1 PG 4 ADDR 0x0D */
SOC_SINGLE_TLV("DAC MBC 1 Compressor Threshold Volume", R_DACMBCTHR1,
FB_DACMBCTHR_THRESH, FM_DACMBCTHR_THRESH,
0, thr_tlv_arr),
/* R_DACMBCRAT1 PG 4 ADDR 0x0E */
SOC_ENUM("DAC MBC 1 Compressor Ratio", dac_mbc1_comp_rat_enum),
/* R_DACMBCATK1L PG 4 ADDR 0x0F */
/* R_DACMBCATK1H PG 4 ADDR 0x10 */
SND_SOC_BYTES("DAC MBC 1 Attack", R_DACMBCATK1L, 2),
/* R_DACMBCREL1L PG 4 ADDR 0x11 */
/* R_DACMBCREL1H PG 4 ADDR 0x12 */
SND_SOC_BYTES("DAC MBC 1 Release", R_DACMBCREL1L, 2),
/* R_DACMBCMUG2 PG 4 ADDR 0x13 */
SOC_ENUM("DAC MBC 2 Phase Polarity", dac_mbc2_phase_pol_enum),
SOC_SINGLE_TLV("DAC MBC 2 Make-Up Gain Volume", R_DACMBCMUG2,
FB_DACMBCMUG_MUGAIN, FM_DACMBCMUG_MUGAIN,
0, mbc_mug_tlv_arr),
/* R_DACMBCTHR2 PG 4 ADDR 0x14 */
SOC_SINGLE_TLV("DAC MBC 2 Compressor Threshold Volume", R_DACMBCTHR2,
FB_DACMBCTHR_THRESH, FM_DACMBCTHR_THRESH,
0, thr_tlv_arr),
/* R_DACMBCRAT2 PG 4 ADDR 0x15 */
SOC_ENUM("DAC MBC 2 Compressor Ratio", dac_mbc2_comp_rat_enum),
/* R_DACMBCATK2L PG 4 ADDR 0x16 */
/* R_DACMBCATK2H PG 4 ADDR 0x17 */
SND_SOC_BYTES("DAC MBC 2 Attack", R_DACMBCATK2L, 2),
/* R_DACMBCREL2L PG 4 ADDR 0x18 */
/* R_DACMBCREL2H PG 4 ADDR 0x19 */
SND_SOC_BYTES("DAC MBC 2 Release", R_DACMBCREL2L, 2),
/* R_DACMBCMUG3 PG 4 ADDR 0x1A */
SOC_ENUM("DAC MBC 3 Phase Polarity", dac_mbc3_phase_pol_enum),
SOC_SINGLE_TLV("DAC MBC 3 Make-Up Gain Volume", R_DACMBCMUG3,
FB_DACMBCMUG_MUGAIN, FM_DACMBCMUG_MUGAIN,
0, mbc_mug_tlv_arr),
/* R_DACMBCTHR3 PG 4 ADDR 0x1B */
SOC_SINGLE_TLV("DAC MBC 3 Threshold Volume", R_DACMBCTHR3,
FB_DACMBCTHR_THRESH, FM_DACMBCTHR_THRESH,
0, thr_tlv_arr),
/* R_DACMBCRAT3 PG 4 ADDR 0x1C */
SOC_ENUM("DAC MBC 3 Compressor Ratio", dac_mbc3_comp_rat_enum),
/* R_DACMBCATK3L PG 4 ADDR 0x1D */
/* R_DACMBCATK3H PG 4 ADDR 0x1E */
SND_SOC_BYTES("DAC MBC 3 Attack", R_DACMBCATK3L, 3),
/* R_DACMBCREL3L PG 4 ADDR 0x1F */
/* R_DACMBCREL3H PG 4 ADDR 0x20 */
SND_SOC_BYTES("DAC MBC 3 Release", R_DACMBCREL3L, 3),
/* R_DACCLECTL PG 4 ADDR 0x21 */
SOC_ENUM("DAC CLE Level Mode", dac_cle_lvl_mode_enum),
SOC_ENUM("DAC CLE Window", dac_cle_win_sel_enum),
SOC_SINGLE("DAC CLE Expander Switch",
R_DACCLECTL, FB_DACCLECTL_EXPEN, 1, 0),
SOC_SINGLE("DAC CLE Limiter Switch",
R_DACCLECTL, FB_DACCLECTL_LIMEN, 1, 0),
SOC_SINGLE("DAC CLE Compressor Switch",
R_DACCLECTL, FB_DACCLECTL_COMPEN, 1, 0),
/* R_DACCLEMUG PG 4 ADDR 0x22 */
SOC_SINGLE_TLV("DAC CLE Make-Up Gain Volume", R_DACCLEMUG,
FB_DACCLEMUG_MUGAIN, FM_DACCLEMUG_MUGAIN,
0, cle_mug_tlv_arr),
/* R_DACCOMPTHR PG 4 ADDR 0x23 */
SOC_SINGLE_TLV("DAC Compressor Threshold Volume", R_DACCOMPTHR,
FB_DACCOMPTHR_THRESH, FM_DACCOMPTHR_THRESH,
0, thr_tlv_arr),
/* R_DACCOMPRAT PG 4 ADDR 0x24 */
SOC_ENUM("DAC Compressor Ratio", dac_comp_rat_enum),
/* R_DACCOMPATKL PG 4 ADDR 0x25 */
/* R_DACCOMPATKH PG 4 ADDR 0x26 */
SND_SOC_BYTES("DAC Compressor Attack", R_DACCOMPATKL, 2),
/* R_DACCOMPRELL PG 4 ADDR 0x27 */
/* R_DACCOMPRELH PG 4 ADDR 0x28 */
SND_SOC_BYTES("DAC Compressor Release", R_DACCOMPRELL, 2),
/* R_DACLIMTHR PG 4 ADDR 0x29 */
SOC_SINGLE_TLV("DAC Limiter Threshold Volume", R_DACLIMTHR,
FB_DACLIMTHR_THRESH, FM_DACLIMTHR_THRESH,
0, thr_tlv_arr),
/* R_DACLIMTGT PG 4 ADDR 0x2A */
SOC_SINGLE_TLV("DAC Limiter Target Volume", R_DACLIMTGT,
FB_DACLIMTGT_TARGET, FM_DACLIMTGT_TARGET,
0, thr_tlv_arr),
/* R_DACLIMATKL PG 4 ADDR 0x2B */
/* R_DACLIMATKH PG 4 ADDR 0x2C */
SND_SOC_BYTES("DAC Limiter Attack", R_DACLIMATKL, 2),
/* R_DACLIMRELL PG 4 ADDR 0x2D */
/* R_DACLIMRELR PG 4 ADDR 0x2E */
SND_SOC_BYTES("DAC Limiter Release", R_DACLIMRELL, 2),
/* R_DACEXPTHR PG 4 ADDR 0x2F */
SOC_SINGLE_TLV("DAC Expander Threshold Volume", R_DACEXPTHR,
FB_DACEXPTHR_THRESH, FM_DACEXPTHR_THRESH,
0, thr_tlv_arr),
/* R_DACEXPRAT PG 4 ADDR 0x30 */
SOC_ENUM("DAC Expander Ratio", dac_exp_rat_enum),
/* R_DACEXPATKL PG 4 ADDR 0x31 */
/* R_DACEXPATKR PG 4 ADDR 0x32 */
SND_SOC_BYTES("DAC Expander Attack", R_DACEXPATKL, 2),
/* R_DACEXPRELL PG 4 ADDR 0x33 */
/* R_DACEXPRELR PG 4 ADDR 0x34 */
SND_SOC_BYTES("DAC Expander Release", R_DACEXPRELL, 2),
/* R_DACFXCTL PG 4 ADDR 0x35 */
SOC_SINGLE("DAC 3D Switch", R_DACFXCTL, FB_DACFXCTL_3DEN, 1, 0),
SOC_SINGLE("DAC Treble Enhancement Switch",
R_DACFXCTL, FB_DACFXCTL_TEEN, 1, 0),
SOC_SINGLE("DAC Treble NLF Switch",
R_DACFXCTL, FB_DACFXCTL_TNLFBYP, 1, 1),
SOC_SINGLE("DAC Bass Enhancement Switch",
R_DACFXCTL, FB_DACFXCTL_BEEN, 1, 0),
SOC_SINGLE("DAC Bass NLF Switch",
R_DACFXCTL, FB_DACFXCTL_BNLFBYP, 1, 1),
/* R_SUBEQFILT PG 5 ADDR 0x01 */
SOC_SINGLE("Sub EQ 2 Switch",
R_SUBEQFILT, FB_SUBEQFILT_EQ2EN, 1, 0),
SOC_ENUM("Sub EQ 2 Band", sub_eq_enums[0]),
SOC_SINGLE("Sub EQ 1 Switch", R_SUBEQFILT, FB_SUBEQFILT_EQ1EN, 1, 0),
SOC_ENUM("Sub EQ 1 Band", sub_eq_enums[1]),
/* R_SUBMBCEN PG 5 ADDR 0x0A */
SOC_SINGLE("Sub MBC 3 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN3, 1, 0),
SOC_SINGLE("Sub MBC 2 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN2, 1, 0),
SOC_SINGLE("Sub MBC 1 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN1, 1, 0),
/* R_SUBMBCCTL PG 5 ADDR 0x0B */
SOC_ENUM("Sub MBC 3 Mode", sub_mbc3_lvl_det_mode_enum),
SOC_ENUM("Sub MBC 3 Window", sub_mbc3_win_sel_enum),
SOC_ENUM("Sub MBC 2 Mode", sub_mbc2_lvl_det_mode_enum),
SOC_ENUM("Sub MBC 2 Window", sub_mbc2_win_sel_enum),
SOC_ENUM("Sub MBC 1 Mode", sub_mbc1_lvl_det_mode_enum),
SOC_ENUM("Sub MBC 1 Window", sub_mbc1_win_sel_enum),
/* R_SUBMBCMUG1 PG 5 ADDR 0x0C */
SOC_ENUM("Sub MBC 1 Phase Polarity", sub_mbc1_phase_pol_enum),
SOC_SINGLE_TLV("Sub MBC 1 Make-Up Gain Volume", R_SUBMBCMUG1,
FB_SUBMBCMUG_MUGAIN, FM_SUBMBCMUG_MUGAIN,
0, mbc_mug_tlv_arr),
/* R_SUBMBCTHR1 PG 5 ADDR 0x0D */
SOC_SINGLE_TLV("Sub MBC 1 Compressor Threshold Volume", R_SUBMBCTHR1,
FB_SUBMBCTHR_THRESH, FM_SUBMBCTHR_THRESH,
0, thr_tlv_arr),
/* R_SUBMBCRAT1 PG 5 ADDR 0x0E */
SOC_ENUM("Sub MBC 1 Compressor Ratio", sub_mbc1_comp_rat_enum),
/* R_SUBMBCATK1L PG 5 ADDR 0x0F */
/* R_SUBMBCATK1H PG 5 ADDR 0x10 */
SND_SOC_BYTES("Sub MBC 1 Attack", R_SUBMBCATK1L, 2),
/* R_SUBMBCREL1L PG 5 ADDR 0x11 */
/* R_SUBMBCREL1H PG 5 ADDR 0x12 */
SND_SOC_BYTES("Sub MBC 1 Release", R_SUBMBCREL1L, 2),
/* R_SUBMBCMUG2 PG 5 ADDR 0x13 */
SOC_ENUM("Sub MBC 2 Phase Polarity", sub_mbc2_phase_pol_enum),
SOC_SINGLE_TLV("Sub MBC 2 Make-Up Gain Volume", R_SUBMBCMUG2,
FB_SUBMBCMUG_MUGAIN, FM_SUBMBCMUG_MUGAIN,
0, mbc_mug_tlv_arr),
/* R_SUBMBCTHR2 PG 5 ADDR 0x14 */
SOC_SINGLE_TLV("Sub MBC 2 Compressor Threshold Volume", R_SUBMBCTHR2,
FB_SUBMBCTHR_THRESH, FM_SUBMBCTHR_THRESH,
0, thr_tlv_arr),
/* R_SUBMBCRAT2 PG 5 ADDR 0x15 */
SOC_ENUM("Sub MBC 2 Compressor Ratio", sub_mbc2_comp_rat_enum),
/* R_SUBMBCATK2L PG 5 ADDR 0x16 */
/* R_SUBMBCATK2H PG 5 ADDR 0x17 */
SND_SOC_BYTES("Sub MBC 2 Attack", R_SUBMBCATK2L, 2),
/* R_SUBMBCREL2L PG 5 ADDR 0x18 */
/* R_SUBMBCREL2H PG 5 ADDR 0x19 */
SND_SOC_BYTES("Sub MBC 2 Release", R_SUBMBCREL2L, 2),
/* R_SUBMBCMUG3 PG 5 ADDR 0x1A */
SOC_ENUM("Sub MBC 3 Phase Polarity", sub_mbc3_phase_pol_enum),
SOC_SINGLE_TLV("Sub MBC 3 Make-Up Gain Volume", R_SUBMBCMUG3,
FB_SUBMBCMUG_MUGAIN, FM_SUBMBCMUG_MUGAIN,
0, mbc_mug_tlv_arr),
/* R_SUBMBCTHR3 PG 5 ADDR 0x1B */
SOC_SINGLE_TLV("Sub MBC 3 Threshold Volume", R_SUBMBCTHR3,
FB_SUBMBCTHR_THRESH, FM_SUBMBCTHR_THRESH,
0, thr_tlv_arr),
/* R_SUBMBCRAT3 PG 5 ADDR 0x1C */
SOC_ENUM("Sub MBC 3 Compressor Ratio", sub_mbc3_comp_rat_enum),
/* R_SUBMBCATK3L PG 5 ADDR 0x1D */
/* R_SUBMBCATK3H PG 5 ADDR 0x1E */
SND_SOC_BYTES("Sub MBC 3 Attack", R_SUBMBCATK3L, 3),
/* R_SUBMBCREL3L PG 5 ADDR 0x1F */
/* R_SUBMBCREL3H PG 5 ADDR 0x20 */
SND_SOC_BYTES("Sub MBC 3 Release", R_SUBMBCREL3L, 3),
/* R_SUBCLECTL PG 5 ADDR 0x21 */
SOC_ENUM("Sub CLE Level Mode", sub_cle_lvl_mode_enum),
SOC_ENUM("Sub CLE Window", sub_cle_win_sel_enum),
SOC_SINGLE("Sub CLE Expander Switch",
R_SUBCLECTL, FB_SUBCLECTL_EXPEN, 1, 0),
SOC_SINGLE("Sub CLE Limiter Switch",
R_SUBCLECTL, FB_SUBCLECTL_LIMEN, 1, 0),
SOC_SINGLE("Sub CLE Compressor Switch",
R_SUBCLECTL, FB_SUBCLECTL_COMPEN, 1, 0),
/* R_SUBCLEMUG PG 5 ADDR 0x22 */
SOC_SINGLE_TLV("Sub CLE Make-Up Gain Volume", R_SUBCLEMUG,
FB_SUBCLEMUG_MUGAIN, FM_SUBCLEMUG_MUGAIN,
0, cle_mug_tlv_arr),
/* R_SUBCOMPTHR PG 5 ADDR 0x23 */
SOC_SINGLE_TLV("Sub Compressor Threshold Volume", R_SUBCOMPTHR,
FB_SUBCOMPTHR_THRESH, FM_SUBCOMPTHR_THRESH,
0, thr_tlv_arr),
/* R_SUBCOMPRAT PG 5 ADDR 0x24 */
SOC_ENUM("Sub Compressor Ratio", sub_comp_rat_enum),
/* R_SUBCOMPATKL PG 5 ADDR 0x25 */
/* R_SUBCOMPATKH PG 5 ADDR 0x26 */
SND_SOC_BYTES("Sub Compressor Attack", R_SUBCOMPATKL, 2),
/* R_SUBCOMPRELL PG 5 ADDR 0x27 */
/* R_SUBCOMPRELH PG 5 ADDR 0x28 */
SND_SOC_BYTES("Sub Compressor Release", R_SUBCOMPRELL, 2),
/* R_SUBLIMTHR PG 5 ADDR 0x29 */
SOC_SINGLE_TLV("Sub Limiter Threshold Volume", R_SUBLIMTHR,
FB_SUBLIMTHR_THRESH, FM_SUBLIMTHR_THRESH,
0, thr_tlv_arr),
/* R_SUBLIMTGT PG 5 ADDR 0x2A */
SOC_SINGLE_TLV("Sub Limiter Target Volume", R_SUBLIMTGT,
FB_SUBLIMTGT_TARGET, FM_SUBLIMTGT_TARGET,
0, thr_tlv_arr),
/* R_SUBLIMATKL PG 5 ADDR 0x2B */
/* R_SUBLIMATKH PG 5 ADDR 0x2C */
SND_SOC_BYTES("Sub Limiter Attack", R_SUBLIMATKL, 2),
/* R_SUBLIMRELL PG 5 ADDR 0x2D */
/* R_SUBLIMRELR PG 5 ADDR 0x2E */
SND_SOC_BYTES("Sub Limiter Release", R_SUBLIMRELL, 2),
/* R_SUBEXPTHR PG 5 ADDR 0x2F */
SOC_SINGLE_TLV("Sub Expander Threshold Volume", R_SUBEXPTHR,
FB_SUBEXPTHR_THRESH, FM_SUBEXPTHR_THRESH,
0, thr_tlv_arr),
/* R_SUBEXPRAT PG 5 ADDR 0x30 */
SOC_ENUM("Sub Expander Ratio", sub_exp_rat_enum),
/* R_SUBEXPATKL PG 5 ADDR 0x31 */
/* R_SUBEXPATKR PG 5 ADDR 0x32 */
SND_SOC_BYTES("Sub Expander Attack", R_SUBEXPATKL, 2),
/* R_SUBEXPRELL PG 5 ADDR 0x33 */
/* R_SUBEXPRELR PG 5 ADDR 0x34 */
SND_SOC_BYTES("Sub Expander Release", R_SUBEXPRELL, 2),
/* R_SUBFXCTL PG 5 ADDR 0x35 */
SOC_SINGLE("Sub Treble Enhancement Switch",
R_SUBFXCTL, FB_SUBFXCTL_TEEN, 1, 0),
SOC_SINGLE("Sub Treble NLF Switch",
R_SUBFXCTL, FB_SUBFXCTL_TNLFBYP, 1, 1),
SOC_SINGLE("Sub Bass Enhancement Switch",
R_SUBFXCTL, FB_SUBFXCTL_BEEN, 1, 0),
SOC_SINGLE("Sub Bass NLF Switch",
R_SUBFXCTL, FB_SUBFXCTL_BNLFBYP, 1, 1),
COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00),
COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05),
COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a),
COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f),
COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14),
COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19),
COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20),
COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25),
COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a),
COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f),
COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34),
COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39),
COEFF_RAM_CTL("DAC Cascade 1 Left Prescale", COEFF_SIZE, 0x1f),
COEFF_RAM_CTL("DAC Cascade 1 Right Prescale", COEFF_SIZE, 0x3f),
COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40),
COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45),
COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a),
COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f),
COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54),
COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59),
COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60),
COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65),
COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a),
COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f),
COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74),
COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79),
COEFF_RAM_CTL("DAC Cascade 2 Left Prescale", COEFF_SIZE, 0x5f),
COEFF_RAM_CTL("DAC Cascade 2 Right Prescale", COEFF_SIZE, 0x7f),
COEFF_RAM_CTL("DAC Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80),
COEFF_RAM_CTL("DAC Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85),
COEFF_RAM_CTL("DAC Bass Non Linear Function 1", COEFF_SIZE, 0x8a),
COEFF_RAM_CTL("DAC Bass Non Linear Function 2", COEFF_SIZE, 0x8b),
COEFF_RAM_CTL("DAC Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c),
COEFF_RAM_CTL("DAC Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91),
COEFF_RAM_CTL("DAC Bass Mix", COEFF_SIZE, 0x96),
COEFF_RAM_CTL("DAC Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97),
COEFF_RAM_CTL("DAC Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c),
COEFF_RAM_CTL("DAC Treb Non Linear Function 1", COEFF_SIZE, 0xa1),
COEFF_RAM_CTL("DAC Treb Non Linear Function 2", COEFF_SIZE, 0xa2),
COEFF_RAM_CTL("DAC Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3),
COEFF_RAM_CTL("DAC Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8),
COEFF_RAM_CTL("DAC Treb Mix", COEFF_SIZE, 0xad),
COEFF_RAM_CTL("DAC 3D", COEFF_SIZE, 0xae),
COEFF_RAM_CTL("DAC 3D Mix", COEFF_SIZE, 0xaf),
COEFF_RAM_CTL("DAC MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0),
COEFF_RAM_CTL("DAC MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5),
COEFF_RAM_CTL("DAC MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba),
COEFF_RAM_CTL("DAC MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf),
COEFF_RAM_CTL("DAC MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4),
COEFF_RAM_CTL("DAC MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9),
COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00),
COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05),
COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a),
COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f),
COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14),
COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19),
COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20),
COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25),
COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a),
COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f),
COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34),
COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39),
COEFF_RAM_CTL("Speaker Cascade 1 Left Prescale", COEFF_SIZE, 0x1f),
COEFF_RAM_CTL("Speaker Cascade 1 Right Prescale", COEFF_SIZE, 0x3f),
COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40),
COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45),
COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a),
COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f),
COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54),
COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59),
COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60),
COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65),
COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a),
COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f),
COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74),
COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79),
COEFF_RAM_CTL("Speaker Cascade 2 Left Prescale", COEFF_SIZE, 0x5f),
COEFF_RAM_CTL("Speaker Cascade 2 Right Prescale", COEFF_SIZE, 0x7f),
COEFF_RAM_CTL("Speaker Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80),
COEFF_RAM_CTL("Speaker Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85),
COEFF_RAM_CTL("Speaker Bass Non Linear Function 1", COEFF_SIZE, 0x8a),
COEFF_RAM_CTL("Speaker Bass Non Linear Function 2", COEFF_SIZE, 0x8b),
COEFF_RAM_CTL("Speaker Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c),
COEFF_RAM_CTL("Speaker Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91),
COEFF_RAM_CTL("Speaker Bass Mix", COEFF_SIZE, 0x96),
COEFF_RAM_CTL("Speaker Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97),
COEFF_RAM_CTL("Speaker Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c),
COEFF_RAM_CTL("Speaker Treb Non Linear Function 1", COEFF_SIZE, 0xa1),
COEFF_RAM_CTL("Speaker Treb Non Linear Function 2", COEFF_SIZE, 0xa2),
COEFF_RAM_CTL("Speaker Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3),
COEFF_RAM_CTL("Speaker Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8),
COEFF_RAM_CTL("Speaker Treb Mix", COEFF_SIZE, 0xad),
COEFF_RAM_CTL("Speaker 3D", COEFF_SIZE, 0xae),
COEFF_RAM_CTL("Speaker 3D Mix", COEFF_SIZE, 0xaf),
COEFF_RAM_CTL("Speaker MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0),
COEFF_RAM_CTL("Speaker MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5),
COEFF_RAM_CTL("Speaker MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba),
COEFF_RAM_CTL("Speaker MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf),
COEFF_RAM_CTL("Speaker MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4),
COEFF_RAM_CTL("Speaker MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9),
COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00),
COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05),
COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a),
COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f),
COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14),
COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19),
COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20),
COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25),
COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a),
COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f),
COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34),
COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39),
COEFF_RAM_CTL("Sub Cascade 1 Left Prescale", COEFF_SIZE, 0x1f),
COEFF_RAM_CTL("Sub Cascade 1 Right Prescale", COEFF_SIZE, 0x3f),
COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40),
COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45),
COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a),
COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f),
COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54),
COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59),
COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60),
COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65),
COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a),
COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f),
COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74),
COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79),
COEFF_RAM_CTL("Sub Cascade 2 Left Prescale", COEFF_SIZE, 0x5f),
COEFF_RAM_CTL("Sub Cascade 2 Right Prescale", COEFF_SIZE, 0x7f),
COEFF_RAM_CTL("Sub Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80),
COEFF_RAM_CTL("Sub Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85),
COEFF_RAM_CTL("Sub Bass Non Linear Function 1", COEFF_SIZE, 0x8a),
COEFF_RAM_CTL("Sub Bass Non Linear Function 2", COEFF_SIZE, 0x8b),
COEFF_RAM_CTL("Sub Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c),
COEFF_RAM_CTL("Sub Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91),
COEFF_RAM_CTL("Sub Bass Mix", COEFF_SIZE, 0x96),
COEFF_RAM_CTL("Sub Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97),
COEFF_RAM_CTL("Sub Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c),
COEFF_RAM_CTL("Sub Treb Non Linear Function 1", COEFF_SIZE, 0xa1),
COEFF_RAM_CTL("Sub Treb Non Linear Function 2", COEFF_SIZE, 0xa2),
COEFF_RAM_CTL("Sub Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3),
COEFF_RAM_CTL("Sub Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8),
COEFF_RAM_CTL("Sub Treb Mix", COEFF_SIZE, 0xad),
COEFF_RAM_CTL("Sub 3D", COEFF_SIZE, 0xae),
COEFF_RAM_CTL("Sub 3D Mix", COEFF_SIZE, 0xaf),
COEFF_RAM_CTL("Sub MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0),
COEFF_RAM_CTL("Sub MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5),
COEFF_RAM_CTL("Sub MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba),
COEFF_RAM_CTL("Sub MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf),
COEFF_RAM_CTL("Sub MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4),
COEFF_RAM_CTL("Sub MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9),
};
static struct snd_soc_dapm_widget const tscs454_dapm_widgets[] = {
/* R_PLLCTL PG 0 ADDR 0x15 */
SND_SOC_DAPM_SUPPLY("PLL 1 Power", R_PLLCTL, FB_PLLCTL_PU_PLL1, 0,
pll_power_event,
SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SUPPLY("PLL 2 Power", R_PLLCTL, FB_PLLCTL_PU_PLL2, 0,
pll_power_event,
SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD),
/* R_I2SPINC0 PG 0 ADDR 0x22 */
SND_SOC_DAPM_AIF_OUT("DAI 3 Out", "DAI 3 Capture", 0,
R_I2SPINC0, FB_I2SPINC0_SDO3TRI, 1),
SND_SOC_DAPM_AIF_OUT("DAI 2 Out", "DAI 2 Capture", 0,
R_I2SPINC0, FB_I2SPINC0_SDO2TRI, 1),
SND_SOC_DAPM_AIF_OUT("DAI 1 Out", "DAI 1 Capture", 0,
R_I2SPINC0, FB_I2SPINC0_SDO1TRI, 1),
/* R_PWRM0 PG 0 ADDR 0x33 */
SND_SOC_DAPM_ADC("Input Processor Channel 3", NULL,
R_PWRM0, FB_PWRM0_INPROC3PU, 0),
SND_SOC_DAPM_ADC("Input Processor Channel 2", NULL,
R_PWRM0, FB_PWRM0_INPROC2PU, 0),
SND_SOC_DAPM_ADC("Input Processor Channel 1", NULL,
R_PWRM0, FB_PWRM0_INPROC1PU, 0),
SND_SOC_DAPM_ADC("Input Processor Channel 0", NULL,
R_PWRM0, FB_PWRM0_INPROC0PU, 0),
SND_SOC_DAPM_SUPPLY("Mic Bias 2",
R_PWRM0, FB_PWRM0_MICB2PU, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Mic Bias 1", R_PWRM0,
FB_PWRM0_MICB1PU, 0, NULL, 0),
/* R_PWRM1 PG 0 ADDR 0x34 */
SND_SOC_DAPM_SUPPLY("Sub Power", R_PWRM1, FB_PWRM1_SUBPU, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Headphone Left Power",
R_PWRM1, FB_PWRM1_HPLPU, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Headphone Right Power",
R_PWRM1, FB_PWRM1_HPRPU, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Speaker Left Power",
R_PWRM1, FB_PWRM1_SPKLPU, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Speaker Right Power",
R_PWRM1, FB_PWRM1_SPKRPU, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Differential Input 2 Power",
R_PWRM1, FB_PWRM1_D2S2PU, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Differential Input 1 Power",
R_PWRM1, FB_PWRM1_D2S1PU, 0, NULL, 0),
/* R_PWRM2 PG 0 ADDR 0x35 */
SND_SOC_DAPM_SUPPLY("DAI 3 Out Power",
R_PWRM2, FB_PWRM2_I2S3OPU, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAI 2 Out Power",
R_PWRM2, FB_PWRM2_I2S2OPU, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAI 1 Out Power",
R_PWRM2, FB_PWRM2_I2S1OPU, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAI 3 In Power",
R_PWRM2, FB_PWRM2_I2S3IPU, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAI 2 In Power",
R_PWRM2, FB_PWRM2_I2S2IPU, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAI 1 In Power",
R_PWRM2, FB_PWRM2_I2S1IPU, 0, NULL, 0),
/* R_PWRM3 PG 0 ADDR 0x36 */
SND_SOC_DAPM_SUPPLY("Line Out Left Power",
R_PWRM3, FB_PWRM3_LLINEPU, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Line Out Right Power",
R_PWRM3, FB_PWRM3_RLINEPU, 0, NULL, 0),
/* R_PWRM4 PG 0 ADDR 0x37 */
SND_SOC_DAPM_DAC("Sub", NULL, R_PWRM4, FB_PWRM4_OPSUBPU, 0),
SND_SOC_DAPM_DAC("DAC Left", NULL, R_PWRM4, FB_PWRM4_OPDACLPU, 0),
SND_SOC_DAPM_DAC("DAC Right", NULL, R_PWRM4, FB_PWRM4_OPDACRPU, 0),
SND_SOC_DAPM_DAC("ClassD Left", NULL, R_PWRM4, FB_PWRM4_OPSPKLPU, 0),
SND_SOC_DAPM_DAC("ClassD Right", NULL, R_PWRM4, FB_PWRM4_OPSPKRPU, 0),
/* R_AUDIOMUX1 PG 0 ADDR 0x3A */
SND_SOC_DAPM_MUX("DAI 2 Out Mux", SND_SOC_NOPM, 0, 0,
&dai2_mux_dapm_enum),
SND_SOC_DAPM_MUX("DAI 1 Out Mux", SND_SOC_NOPM, 0, 0,
&dai1_mux_dapm_enum),
/* R_AUDIOMUX2 PG 0 ADDR 0x3B */
SND_SOC_DAPM_MUX("DAC Mux", SND_SOC_NOPM, 0, 0,
&dac_mux_dapm_enum),
SND_SOC_DAPM_MUX("DAI 3 Out Mux", SND_SOC_NOPM, 0, 0,
&dai3_mux_dapm_enum),
/* R_AUDIOMUX3 PG 0 ADDR 0x3C */
SND_SOC_DAPM_MUX("Sub Mux", SND_SOC_NOPM, 0, 0,
&sub_mux_dapm_enum),
SND_SOC_DAPM_MUX("Speaker Mux", SND_SOC_NOPM, 0, 0,
&classd_mux_dapm_enum),
/* R_HSDCTL1 PG 1 ADDR 0x01 */
SND_SOC_DAPM_SUPPLY("GHS Detect Power", R_HSDCTL1,
FB_HSDCTL1_CON_DET_PWD, 1, NULL, 0),
/* R_CH0AIC PG 1 ADDR 0x06 */
SND_SOC_DAPM_MUX("Input Boost Channel 0 Mux", SND_SOC_NOPM, 0, 0,
&in_bst_mux_ch0_dapm_enum),
SND_SOC_DAPM_MUX("ADC Channel 0 Mux", SND_SOC_NOPM, 0, 0,
&adc_mux_ch0_dapm_enum),
SND_SOC_DAPM_MUX("Input Processor Channel 0 Mux", SND_SOC_NOPM, 0, 0,
&in_proc_mux_ch0_dapm_enum),
/* R_CH1AIC PG 1 ADDR 0x07 */
SND_SOC_DAPM_MUX("Input Boost Channel 1 Mux", SND_SOC_NOPM, 0, 0,
&in_bst_mux_ch1_dapm_enum),
SND_SOC_DAPM_MUX("ADC Channel 1 Mux", SND_SOC_NOPM, 0, 0,
&adc_mux_ch1_dapm_enum),
SND_SOC_DAPM_MUX("Input Processor Channel 1 Mux", SND_SOC_NOPM, 0, 0,
&in_proc_mux_ch1_dapm_enum),
/* Virtual */
SND_SOC_DAPM_AIF_IN("DAI 3 In", "DAI 3 Playback", 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("DAI 2 In", "DAI 2 Playback", 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("DAI 1 In", "DAI 1 Playback", 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SUPPLY("PLLs", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("Sub Out"),
SND_SOC_DAPM_OUTPUT("Headphone Left"),
SND_SOC_DAPM_OUTPUT("Headphone Right"),
SND_SOC_DAPM_OUTPUT("Speaker Left"),
SND_SOC_DAPM_OUTPUT("Speaker Right"),
SND_SOC_DAPM_OUTPUT("Line Out Left"),
SND_SOC_DAPM_OUTPUT("Line Out Right"),
SND_SOC_DAPM_INPUT("D2S 2"),
SND_SOC_DAPM_INPUT("D2S 1"),
SND_SOC_DAPM_INPUT("Line In 1 Left"),
SND_SOC_DAPM_INPUT("Line In 1 Right"),
SND_SOC_DAPM_INPUT("Line In 2 Left"),
SND_SOC_DAPM_INPUT("Line In 2 Right"),
SND_SOC_DAPM_INPUT("Line In 3 Left"),
SND_SOC_DAPM_INPUT("Line In 3 Right"),
SND_SOC_DAPM_INPUT("DMic 1"),
SND_SOC_DAPM_INPUT("DMic 2"),
SND_SOC_DAPM_MUX("CH 0_1 Mux", SND_SOC_NOPM, 0, 0,
&ch_0_1_mux_dapm_enum),
SND_SOC_DAPM_MUX("CH 2_3 Mux", SND_SOC_NOPM, 0, 0,
&ch_2_3_mux_dapm_enum),
SND_SOC_DAPM_MUX("CH 4_5 Mux", SND_SOC_NOPM, 0, 0,
&ch_4_5_mux_dapm_enum),
};
static struct snd_soc_dapm_route const tscs454_intercon[] = {
/* PLLs */
{"PLLs", NULL, "PLL 1 Power", pll_connected},
{"PLLs", NULL, "PLL 2 Power", pll_connected},
/* Inputs */
{"DAI 3 In", NULL, "DAI 3 In Power"},
{"DAI 2 In", NULL, "DAI 2 In Power"},
{"DAI 1 In", NULL, "DAI 1 In Power"},
/* Outputs */
{"DAI 3 Out", NULL, "DAI 3 Out Power"},
{"DAI 2 Out", NULL, "DAI 2 Out Power"},
{"DAI 1 Out", NULL, "DAI 1 Out Power"},
/* Ch Muxing */
{"CH 0_1 Mux", "DAI 1", "DAI 1 In"},
{"CH 0_1 Mux", "TDM 0_1", "DAI 1 In"},
{"CH 2_3 Mux", "DAI 2", "DAI 2 In"},
{"CH 2_3 Mux", "TDM 2_3", "DAI 1 In"},
{"CH 4_5 Mux", "DAI 3", "DAI 2 In"},
{"CH 4_5 Mux", "TDM 4_5", "DAI 1 In"},
/* In/Out Muxing */
{"DAI 1 Out Mux", "CH 0_1", "CH 0_1 Mux"},
{"DAI 1 Out Mux", "CH 2_3", "CH 2_3 Mux"},
{"DAI 1 Out Mux", "CH 4_5", "CH 4_5 Mux"},
{"DAI 2 Out Mux", "CH 0_1", "CH 0_1 Mux"},
{"DAI 2 Out Mux", "CH 2_3", "CH 2_3 Mux"},
{"DAI 2 Out Mux", "CH 4_5", "CH 4_5 Mux"},
{"DAI 3 Out Mux", "CH 0_1", "CH 0_1 Mux"},
{"DAI 3 Out Mux", "CH 2_3", "CH 2_3 Mux"},
{"DAI 3 Out Mux", "CH 4_5", "CH 4_5 Mux"},
/******************
* Playback Paths *
******************/
/* DAC Path */
{"DAC Mux", "CH 4_5", "CH 4_5 Mux"},
{"DAC Mux", "CH 2_3", "CH 2_3 Mux"},
{"DAC Mux", "CH 0_1", "CH 0_1 Mux"},
{"DAC Left", NULL, "DAC Mux"},
{"DAC Right", NULL, "DAC Mux"},
{"DAC Left", NULL, "PLLs"},
{"DAC Right", NULL, "PLLs"},
{"Headphone Left", NULL, "Headphone Left Power"},
{"Headphone Right", NULL, "Headphone Right Power"},
{"Headphone Left", NULL, "DAC Left"},
{"Headphone Right", NULL, "DAC Right"},
/* Line Out */
{"Line Out Left", NULL, "Line Out Left Power"},
{"Line Out Right", NULL, "Line Out Right Power"},
{"Line Out Left", NULL, "DAC Left"},
{"Line Out Right", NULL, "DAC Right"},
/* ClassD Path */
{"Speaker Mux", "CH 4_5", "CH 4_5 Mux"},
{"Speaker Mux", "CH 2_3", "CH 2_3 Mux"},
{"Speaker Mux", "CH 0_1", "CH 0_1 Mux"},
{"ClassD Left", NULL, "Speaker Mux"},
{"ClassD Right", NULL, "Speaker Mux"},
{"ClassD Left", NULL, "PLLs"},
{"ClassD Right", NULL, "PLLs"},
{"Speaker Left", NULL, "Speaker Left Power"},
{"Speaker Right", NULL, "Speaker Right Power"},
{"Speaker Left", NULL, "ClassD Left"},
{"Speaker Right", NULL, "ClassD Right"},
/* Sub Path */
{"Sub Mux", "CH 4", "CH 4_5 Mux"},
{"Sub Mux", "CH 5", "CH 4_5 Mux"},
{"Sub Mux", "CH 4 + 5", "CH 4_5 Mux"},
{"Sub Mux", "CH 2", "CH 2_3 Mux"},
{"Sub Mux", "CH 3", "CH 2_3 Mux"},
{"Sub Mux", "CH 2 + 3", "CH 2_3 Mux"},
{"Sub Mux", "CH 0", "CH 0_1 Mux"},
{"Sub Mux", "CH 1", "CH 0_1 Mux"},
{"Sub Mux", "CH 0 + 1", "CH 0_1 Mux"},
{"Sub Mux", "ADC/DMic 1 Left", "Input Processor Channel 0"},
{"Sub Mux", "ADC/DMic 1 Right", "Input Processor Channel 1"},
{"Sub Mux", "ADC/DMic 1 Left Plus Right", "Input Processor Channel 0"},
{"Sub Mux", "ADC/DMic 1 Left Plus Right", "Input Processor Channel 1"},
{"Sub Mux", "DMic 2 Left", "DMic 2"},
{"Sub Mux", "DMic 2 Right", "DMic 2"},
{"Sub Mux", "DMic 2 Left Plus Right", "DMic 2"},
{"Sub Mux", "ClassD Left", "ClassD Left"},
{"Sub Mux", "ClassD Right", "ClassD Right"},
{"Sub Mux", "ClassD Left Plus Right", "ClassD Left"},
{"Sub Mux", "ClassD Left Plus Right", "ClassD Right"},
{"Sub", NULL, "Sub Mux"},
{"Sub", NULL, "PLLs"},
{"Sub Out", NULL, "Sub Power"},
{"Sub Out", NULL, "Sub"},
/*****************
* Capture Paths *
*****************/
{"Input Boost Channel 0 Mux", "Input 3", "Line In 3 Left"},
{"Input Boost Channel 0 Mux", "Input 2", "Line In 2 Left"},
{"Input Boost Channel 0 Mux", "Input 1", "Line In 1 Left"},
{"Input Boost Channel 0 Mux", "D2S", "D2S 1"},
{"Input Boost Channel 1 Mux", "Input 3", "Line In 3 Right"},
{"Input Boost Channel 1 Mux", "Input 2", "Line In 2 Right"},
{"Input Boost Channel 1 Mux", "Input 1", "Line In 1 Right"},
{"Input Boost Channel 1 Mux", "D2S", "D2S 2"},
{"ADC Channel 0 Mux", "Input 3 Boost Bypass", "Line In 3 Left"},
{"ADC Channel 0 Mux", "Input 2 Boost Bypass", "Line In 2 Left"},
{"ADC Channel 0 Mux", "Input 1 Boost Bypass", "Line In 1 Left"},
{"ADC Channel 0 Mux", "Input Boost", "Input Boost Channel 0 Mux"},
{"ADC Channel 1 Mux", "Input 3 Boost Bypass", "Line In 3 Right"},
{"ADC Channel 1 Mux", "Input 2 Boost Bypass", "Line In 2 Right"},
{"ADC Channel 1 Mux", "Input 1 Boost Bypass", "Line In 1 Right"},
{"ADC Channel 1 Mux", "Input Boost", "Input Boost Channel 1 Mux"},
{"Input Processor Channel 0 Mux", "ADC", "ADC Channel 0 Mux"},
{"Input Processor Channel 0 Mux", "DMic", "DMic 1"},
{"Input Processor Channel 0", NULL, "PLLs"},
{"Input Processor Channel 0", NULL, "Input Processor Channel 0 Mux"},
{"Input Processor Channel 1 Mux", "ADC", "ADC Channel 1 Mux"},
{"Input Processor Channel 1 Mux", "DMic", "DMic 1"},
{"Input Processor Channel 1", NULL, "PLLs"},
{"Input Processor Channel 1", NULL, "Input Processor Channel 1 Mux"},
{"Input Processor Channel 2", NULL, "PLLs"},
{"Input Processor Channel 2", NULL, "DMic 2"},
{"Input Processor Channel 3", NULL, "PLLs"},
{"Input Processor Channel 3", NULL, "DMic 2"},
{"DAI 1 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"},
{"DAI 1 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"},
{"DAI 1 Out Mux", "DMic 2", "Input Processor Channel 2"},
{"DAI 1 Out Mux", "DMic 2", "Input Processor Channel 3"},
{"DAI 2 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"},
{"DAI 2 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"},
{"DAI 2 Out Mux", "DMic 2", "Input Processor Channel 2"},
{"DAI 2 Out Mux", "DMic 2", "Input Processor Channel 3"},
{"DAI 3 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"},
{"DAI 3 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"},
{"DAI 3 Out Mux", "DMic 2", "Input Processor Channel 2"},
{"DAI 3 Out Mux", "DMic 2", "Input Processor Channel 3"},
{"DAI 1 Out", NULL, "DAI 1 Out Mux"},
{"DAI 2 Out", NULL, "DAI 2 Out Mux"},
{"DAI 3 Out", NULL, "DAI 3 Out Mux"},
};
/* This is used when BCLK is sourcing the PLLs */
static int tscs454_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
unsigned int val;
int bclk_dai;
dev_dbg(component->dev, "%s(): freq = %u\n", __func__, freq);
val = snd_soc_component_read(component, R_PLLCTL);
bclk_dai = (val & FM_PLLCTL_BCLKSEL) >> FB_PLLCTL_BCLKSEL;
if (bclk_dai != dai->id)
return 0;
tscs454->bclk_freq = freq;
return set_sysclk(component);
}
static int tscs454_set_bclk_ratio(struct snd_soc_dai *dai,
unsigned int ratio)
{
unsigned int mask;
int ret;
struct snd_soc_component *component = dai->component;
unsigned int val;
int shift;
dev_dbg(component->dev, "set_bclk_ratio() id = %d ratio = %u\n",
dai->id, ratio);
switch (dai->id) {
case TSCS454_DAI1_ID:
mask = FM_I2SCMC_BCMP1;
shift = FB_I2SCMC_BCMP1;
break;
case TSCS454_DAI2_ID:
mask = FM_I2SCMC_BCMP2;
shift = FB_I2SCMC_BCMP2;
break;
case TSCS454_DAI3_ID:
mask = FM_I2SCMC_BCMP3;
shift = FB_I2SCMC_BCMP3;
break;
default:
ret = -EINVAL;
dev_err(component->dev, "Unknown audio interface (%d)\n", ret);
return ret;
}
switch (ratio) {
case 32:
val = I2SCMC_BCMP_32X;
break;
case 40:
val = I2SCMC_BCMP_40X;
break;
case 64:
val = I2SCMC_BCMP_64X;
break;
default:
ret = -EINVAL;
dev_err(component->dev, "Unsupported bclk ratio (%d)\n", ret);
return ret;
}
ret = snd_soc_component_update_bits(component,
R_I2SCMC, mask, val << shift);
if (ret < 0) {
dev_err(component->dev,
"Failed to set DAI BCLK ratio (%d)\n", ret);
return ret;
}
return 0;
}
static inline int set_aif_provider_from_fmt(struct snd_soc_component *component,
struct aif *aif, unsigned int fmt)
{
int ret;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
aif->provider = true;
break;
case SND_SOC_DAIFMT_CBC_CFC:
aif->provider = false;
break;
default:
ret = -EINVAL;
dev_err(component->dev, "Unsupported format (%d)\n", ret);
return ret;
}
return 0;
}
static inline int set_aif_tdm_delay(struct snd_soc_component *component,
unsigned int dai_id, bool delay)
{
unsigned int reg;
int ret;
switch (dai_id) {
case TSCS454_DAI1_ID:
reg = R_TDMCTL0;
break;
case TSCS454_DAI2_ID:
reg = R_PCMP2CTL0;
break;
case TSCS454_DAI3_ID:
reg = R_PCMP3CTL0;
break;
default:
ret = -EINVAL;
dev_err(component->dev,
"DAI %d unknown (%d)\n", dai_id + 1, ret);
return ret;
}
ret = snd_soc_component_update_bits(component,
reg, FM_TDMCTL0_BDELAY, delay);
if (ret < 0) {
dev_err(component->dev, "Failed to setup tdm format (%d)\n",
ret);
return ret;
}
return 0;
}
static inline int set_aif_format_from_fmt(struct snd_soc_component *component,
unsigned int dai_id, unsigned int fmt)
{
unsigned int reg;
unsigned int val;
int ret;
switch (dai_id) {
case TSCS454_DAI1_ID:
reg = R_I2SP1CTL;
break;
case TSCS454_DAI2_ID:
reg = R_I2SP2CTL;
break;
case TSCS454_DAI3_ID:
reg = R_I2SP3CTL;
break;
default:
ret = -EINVAL;
dev_err(component->dev,
"DAI %d unknown (%d)\n", dai_id + 1, ret);
return ret;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_RIGHT_J:
val = FV_FORMAT_RIGHT;
break;
case SND_SOC_DAIFMT_LEFT_J:
val = FV_FORMAT_LEFT;
break;
case SND_SOC_DAIFMT_I2S:
val = FV_FORMAT_I2S;
break;
case SND_SOC_DAIFMT_DSP_A:
ret = set_aif_tdm_delay(component, dai_id, true);
if (ret < 0)
return ret;
val = FV_FORMAT_TDM;
break;
case SND_SOC_DAIFMT_DSP_B:
ret = set_aif_tdm_delay(component, dai_id, false);
if (ret < 0)
return ret;
val = FV_FORMAT_TDM;
break;
default:
ret = -EINVAL;
dev_err(component->dev, "Format unsupported (%d)\n", ret);
return ret;
}
ret = snd_soc_component_update_bits(component,
reg, FM_I2SPCTL_FORMAT, val);
if (ret < 0) {
dev_err(component->dev, "Failed to set DAI %d format (%d)\n",
dai_id + 1, ret);
return ret;
}
return 0;
}
static inline int
set_aif_clock_format_from_fmt(struct snd_soc_component *component,
unsigned int dai_id, unsigned int fmt)
{
unsigned int reg;
unsigned int val;
int ret;
switch (dai_id) {
case TSCS454_DAI1_ID:
reg = R_I2SP1CTL;
break;
case TSCS454_DAI2_ID:
reg = R_I2SP2CTL;
break;
case TSCS454_DAI3_ID:
reg = R_I2SP3CTL;
break;
default:
ret = -EINVAL;
dev_err(component->dev,
"DAI %d unknown (%d)\n", dai_id + 1, ret);
return ret;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
val = FV_BCLKP_NOT_INVERTED | FV_LRCLKP_NOT_INVERTED;
break;
case SND_SOC_DAIFMT_NB_IF:
val = FV_BCLKP_NOT_INVERTED | FV_LRCLKP_INVERTED;
break;
case SND_SOC_DAIFMT_IB_NF:
val = FV_BCLKP_INVERTED | FV_LRCLKP_NOT_INVERTED;
break;
case SND_SOC_DAIFMT_IB_IF:
val = FV_BCLKP_INVERTED | FV_LRCLKP_INVERTED;
break;
default:
ret = -EINVAL;
dev_err(component->dev, "Format unknown (%d)\n", ret);
return ret;
}
ret = snd_soc_component_update_bits(component, reg,
FM_I2SPCTL_BCLKP | FM_I2SPCTL_LRCLKP, val);
if (ret < 0) {
dev_err(component->dev,
"Failed to set clock polarity for DAI%d (%d)\n",
dai_id + 1, ret);
return ret;
}
return 0;
}
static int tscs454_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
struct aif *aif = &tscs454->aifs[dai->id];
int ret;
ret = set_aif_provider_from_fmt(component, aif, fmt);
if (ret < 0)
return ret;
ret = set_aif_format_from_fmt(component, dai->id, fmt);
if (ret < 0)
return ret;
ret = set_aif_clock_format_from_fmt(component, dai->id, fmt);
if (ret < 0)
return ret;
return 0;
}
static int tscs454_dai1_set_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask, int slots,
int slot_width)
{
struct snd_soc_component *component = dai->component;
unsigned int val;
int ret;
if (!slots)
return 0;
if (tx_mask >= (1 << slots) || rx_mask >= (1 << slots)) {
ret = -EINVAL;
dev_err(component->dev, "Invalid TDM slot mask (%d)\n", ret);
return ret;
}
switch (slots) {
case 2:
val = FV_TDMSO_2 | FV_TDMSI_2;
break;
case 4:
val = FV_TDMSO_4 | FV_TDMSI_4;
break;
case 6:
val = FV_TDMSO_6 | FV_TDMSI_6;
break;
default:
ret = -EINVAL;
dev_err(component->dev, "Invalid number of slots (%d)\n", ret);
return ret;
}
switch (slot_width) {
case 16:
val = val | FV_TDMDSS_16;
break;
case 24:
val = val | FV_TDMDSS_24;
break;
case 32:
val = val | FV_TDMDSS_32;
break;
default:
ret = -EINVAL;
dev_err(component->dev, "Invalid TDM slot width (%d)\n", ret);
return ret;
}
ret = snd_soc_component_write(component, R_TDMCTL1, val);
if (ret < 0) {
dev_err(component->dev, "Failed to set slots (%d)\n", ret);
return ret;
}
return 0;
}
static int tscs454_dai23_set_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask, int slots,
int slot_width)
{
struct snd_soc_component *component = dai->component;
unsigned int reg;
unsigned int val;
int ret;
if (!slots)
return 0;
if (tx_mask >= (1 << slots) || rx_mask >= (1 << slots)) {
ret = -EINVAL;
dev_err(component->dev, "Invalid TDM slot mask (%d)\n", ret);
return ret;
}
switch (dai->id) {
case TSCS454_DAI2_ID:
reg = R_PCMP2CTL1;
break;
case TSCS454_DAI3_ID:
reg = R_PCMP3CTL1;
break;
default:
ret = -EINVAL;
dev_err(component->dev, "Unrecognized interface %d (%d)\n",
dai->id, ret);
return ret;
}
switch (slots) {
case 1:
val = FV_PCMSOP_1 | FV_PCMSIP_1;
break;
case 2:
val = FV_PCMSOP_2 | FV_PCMSIP_2;
break;
default:
ret = -EINVAL;
dev_err(component->dev, "Invalid number of slots (%d)\n", ret);
return ret;
}
switch (slot_width) {
case 16:
val = val | FV_PCMDSSP_16;
break;
case 24:
val = val | FV_PCMDSSP_24;
break;
case 32:
val = val | FV_PCMDSSP_32;
break;
default:
ret = -EINVAL;
dev_err(component->dev, "Invalid TDM slot width (%d)\n", ret);
return ret;
}
ret = snd_soc_component_write(component, reg, val);
if (ret < 0) {
dev_err(component->dev, "Failed to set slots (%d)\n", ret);
return ret;
}
return 0;
}
static int set_aif_fs(struct snd_soc_component *component,
unsigned int id,
unsigned int rate)
{
unsigned int reg;
unsigned int br;
unsigned int bm;
int ret;
switch (rate) {
case 8000:
br = FV_I2SMBR_32;
bm = FV_I2SMBM_0PT25;
break;
case 16000:
br = FV_I2SMBR_32;
bm = FV_I2SMBM_0PT5;
break;
case 24000:
br = FV_I2SMBR_48;
bm = FV_I2SMBM_0PT5;
break;
case 32000:
br = FV_I2SMBR_32;
bm = FV_I2SMBM_1;
break;
case 48000:
br = FV_I2SMBR_48;
bm = FV_I2SMBM_1;
break;
case 96000:
br = FV_I2SMBR_48;
bm = FV_I2SMBM_2;
break;
case 11025:
br = FV_I2SMBR_44PT1;
bm = FV_I2SMBM_0PT25;
break;
case 22050:
br = FV_I2SMBR_44PT1;
bm = FV_I2SMBM_0PT5;
break;
case 44100:
br = FV_I2SMBR_44PT1;
bm = FV_I2SMBM_1;
break;
case 88200:
br = FV_I2SMBR_44PT1;
bm = FV_I2SMBM_2;
break;
default:
ret = -EINVAL;
dev_err(component->dev, "Unsupported sample rate (%d)\n", ret);
return ret;
}
switch (id) {
case TSCS454_DAI1_ID:
reg = R_I2S1MRATE;
break;
case TSCS454_DAI2_ID:
reg = R_I2S2MRATE;
break;
case TSCS454_DAI3_ID:
reg = R_I2S3MRATE;
break;
default:
ret = -EINVAL;
dev_err(component->dev, "DAI ID not recognized (%d)\n", ret);
return ret;
}
ret = snd_soc_component_update_bits(component, reg,
FM_I2SMRATE_I2SMBR | FM_I2SMRATE_I2SMBM, br|bm);
if (ret < 0) {
dev_err(component->dev,
"Failed to update register (%d)\n", ret);
return ret;
}
return 0;
}
static int set_aif_sample_format(struct snd_soc_component *component,
snd_pcm_format_t format,
int aif_id)
{
unsigned int reg;
unsigned int width;
int ret;
switch (snd_pcm_format_width(format)) {
case 16:
width = FV_WL_16;
break;
case 20:
width = FV_WL_20;
break;
case 24:
width = FV_WL_24;
break;
case 32:
width = FV_WL_32;
break;
default:
ret = -EINVAL;
dev_err(component->dev, "Unsupported format width (%d)\n", ret);
return ret;
}
switch (aif_id) {
case TSCS454_DAI1_ID:
reg = R_I2SP1CTL;
break;
case TSCS454_DAI2_ID:
reg = R_I2SP2CTL;
break;
case TSCS454_DAI3_ID:
reg = R_I2SP3CTL;
break;
default:
ret = -EINVAL;
dev_err(component->dev, "AIF ID not recognized (%d)\n", ret);
return ret;
}
ret = snd_soc_component_update_bits(component,
reg, FM_I2SPCTL_WL, width);
if (ret < 0) {
dev_err(component->dev,
"Failed to set sample width (%d)\n", ret);
return ret;
}
return 0;
}
static int tscs454_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
unsigned int fs = params_rate(params);
struct aif *aif = &tscs454->aifs[dai->id];
unsigned int val;
int ret;
mutex_lock(&tscs454->aifs_status_lock);
dev_dbg(component->dev, "%s(): aif %d fs = %u\n", __func__,
aif->id, fs);
if (!aif_active(&tscs454->aifs_status, aif->id)) {
if (PLL_44_1K_RATE % fs)
aif->pll = &tscs454->pll1;
else
aif->pll = &tscs454->pll2;
dev_dbg(component->dev, "Reserving pll %d for aif %d\n",
aif->pll->id, aif->id);
reserve_pll(aif->pll);
}
if (!aifs_active(&tscs454->aifs_status)) { /* First active aif */
val = snd_soc_component_read(component, R_ISRC);
if ((val & FM_ISRC_IBR) == FV_IBR_48)
tscs454->internal_rate.pll = &tscs454->pll1;
else
tscs454->internal_rate.pll = &tscs454->pll2;
dev_dbg(component->dev, "Reserving pll %d for ir\n",
tscs454->internal_rate.pll->id);
reserve_pll(tscs454->internal_rate.pll);
}
ret = set_aif_fs(component, aif->id, fs);
if (ret < 0) {
dev_err(component->dev, "Failed to set aif fs (%d)\n", ret);
goto exit;
}
ret = set_aif_sample_format(component, params_format(params), aif->id);
if (ret < 0) {
dev_err(component->dev,
"Failed to set aif sample format (%d)\n", ret);
goto exit;
}
set_aif_status_active(&tscs454->aifs_status, aif->id,
substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
dev_dbg(component->dev, "Set aif %d active. Streams status is 0x%x\n",
aif->id, tscs454->aifs_status.streams);
ret = 0;
exit:
mutex_unlock(&tscs454->aifs_status_lock);
return ret;
}
static int tscs454_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
struct aif *aif = &tscs454->aifs[dai->id];
return aif_free(component, aif,
substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
}
static int tscs454_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
int ret;
struct snd_soc_component *component = dai->component;
struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
struct aif *aif = &tscs454->aifs[dai->id];
ret = aif_prepare(component, aif);
if (ret < 0)
return ret;
return 0;
}
static struct snd_soc_dai_ops const tscs454_dai1_ops = {
.set_sysclk = tscs454_set_sysclk,
.set_bclk_ratio = tscs454_set_bclk_ratio,
.set_fmt = tscs454_set_dai_fmt,
.set_tdm_slot = tscs454_dai1_set_tdm_slot,
.hw_params = tscs454_hw_params,
.hw_free = tscs454_hw_free,
.prepare = tscs454_prepare,
};
static struct snd_soc_dai_ops const tscs454_dai23_ops = {
.set_sysclk = tscs454_set_sysclk,
.set_bclk_ratio = tscs454_set_bclk_ratio,
.set_fmt = tscs454_set_dai_fmt,
.set_tdm_slot = tscs454_dai23_set_tdm_slot,
.hw_params = tscs454_hw_params,
.hw_free = tscs454_hw_free,
.prepare = tscs454_prepare,
};
static int tscs454_probe(struct snd_soc_component *component)
{
struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
unsigned int val;
int ret = 0;
switch (tscs454->sysclk_src_id) {
case PLL_INPUT_XTAL:
val = FV_PLLISEL_XTAL;
break;
case PLL_INPUT_MCLK1:
val = FV_PLLISEL_MCLK1;
break;
case PLL_INPUT_MCLK2:
val = FV_PLLISEL_MCLK2;
break;
case PLL_INPUT_BCLK:
val = FV_PLLISEL_BCLK;
break;
default:
ret = -EINVAL;
dev_err(component->dev, "Invalid sysclk src id (%d)\n", ret);
return ret;
}
ret = snd_soc_component_update_bits(component, R_PLLCTL,
FM_PLLCTL_PLLISEL, val);
if (ret < 0) {
dev_err(component->dev, "Failed to set PLL input (%d)\n", ret);
return ret;
}
if (tscs454->sysclk_src_id < PLL_INPUT_BCLK)
ret = set_sysclk(component);
return ret;
}
static const struct snd_soc_component_driver soc_component_dev_tscs454 = {
.probe = tscs454_probe,
.dapm_widgets = tscs454_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(tscs454_dapm_widgets),
.dapm_routes = tscs454_intercon,
.num_dapm_routes = ARRAY_SIZE(tscs454_intercon),
.controls = tscs454_snd_controls,
.num_controls = ARRAY_SIZE(tscs454_snd_controls),
.endianness = 1,
};
#define TSCS454_RATES SNDRV_PCM_RATE_8000_96000
#define TSCS454_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
| SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE \
| SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver tscs454_dais[] = {
{
.name = "tscs454-dai1",
.id = TSCS454_DAI1_ID,
.playback = {
.stream_name = "DAI 1 Playback",
.channels_min = 1,
.channels_max = 6,
.rates = TSCS454_RATES,
.formats = TSCS454_FORMATS,},
.capture = {
.stream_name = "DAI 1 Capture",
.channels_min = 1,
.channels_max = 6,
.rates = TSCS454_RATES,
.formats = TSCS454_FORMATS,},
.ops = &tscs454_dai1_ops,
.symmetric_rate = 1,
.symmetric_channels = 1,
.symmetric_sample_bits = 1,
},
{
.name = "tscs454-dai2",
.id = TSCS454_DAI2_ID,
.playback = {
.stream_name = "DAI 2 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = TSCS454_RATES,
.formats = TSCS454_FORMATS,},
.capture = {
.stream_name = "DAI 2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = TSCS454_RATES,
.formats = TSCS454_FORMATS,},
.ops = &tscs454_dai23_ops,
.symmetric_rate = 1,
.symmetric_channels = 1,
.symmetric_sample_bits = 1,
},
{
.name = "tscs454-dai3",
.id = TSCS454_DAI3_ID,
.playback = {
.stream_name = "DAI 3 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = TSCS454_RATES,
.formats = TSCS454_FORMATS,},
.capture = {
.stream_name = "DAI 3 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = TSCS454_RATES,
.formats = TSCS454_FORMATS,},
.ops = &tscs454_dai23_ops,
.symmetric_rate = 1,
.symmetric_channels = 1,
.symmetric_sample_bits = 1,
},
};
static char const * const src_names[] = {
"xtal", "mclk1", "mclk2", "bclk"};
static int tscs454_i2c_probe(struct i2c_client *i2c)
{
struct tscs454 *tscs454;
int src;
int ret;
tscs454 = devm_kzalloc(&i2c->dev, sizeof(*tscs454), GFP_KERNEL);
if (!tscs454)
return -ENOMEM;
ret = tscs454_data_init(tscs454, i2c);
if (ret < 0)
return ret;
i2c_set_clientdata(i2c, tscs454);
for (src = PLL_INPUT_XTAL; src < PLL_INPUT_BCLK; src++) {
tscs454->sysclk = devm_clk_get(&i2c->dev, src_names[src]);
if (!IS_ERR(tscs454->sysclk)) {
break;
} else if (PTR_ERR(tscs454->sysclk) != -ENOENT) {
ret = PTR_ERR(tscs454->sysclk);
dev_err(&i2c->dev, "Failed to get sysclk (%d)\n", ret);
return ret;
}
}
dev_dbg(&i2c->dev, "PLL input is %s\n", src_names[src]);
tscs454->sysclk_src_id = src;
ret = regmap_write(tscs454->regmap,
R_RESET, FV_RESET_PWR_ON_DEFAULTS);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to reset the component (%d)\n", ret);
return ret;
}
regcache_mark_dirty(tscs454->regmap);
ret = regmap_register_patch(tscs454->regmap, tscs454_patch,
ARRAY_SIZE(tscs454_patch));
if (ret < 0) {
dev_err(&i2c->dev, "Failed to apply patch (%d)\n", ret);
return ret;
}
/* Sync pg sel reg with cache */
regmap_write(tscs454->regmap, R_PAGESEL, 0x00);
ret = devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_tscs454,
tscs454_dais, ARRAY_SIZE(tscs454_dais));
if (ret) {
dev_err(&i2c->dev, "Failed to register component (%d)\n", ret);
return ret;
}
return 0;
}
static const struct i2c_device_id tscs454_i2c_id[] = {
{ "tscs454", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, tscs454_i2c_id);
static const struct of_device_id tscs454_of_match[] = {
{ .compatible = "tempo,tscs454", },
{ }
};
MODULE_DEVICE_TABLE(of, tscs454_of_match);
static struct i2c_driver tscs454_i2c_driver = {
.driver = {
.name = "tscs454",
.of_match_table = tscs454_of_match,
},
.probe = tscs454_i2c_probe,
.id_table = tscs454_i2c_id,
};
module_i2c_driver(tscs454_i2c_driver);
MODULE_AUTHOR("Tempo Semiconductor <[email protected]");
MODULE_DESCRIPTION("ASoC TSCS454 driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/tscs454.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2008 Juergen Beisert, [email protected]
* Copyright 2009 Sascha Hauer, [email protected]
* Copyright 2012 Philippe Retornaz, [email protected]
*
* Initial development of this code was funded by
* Phytec Messtechnik GmbH, https://www.phytec.de
*/
#include <linux/module.h>
#include <linux/device.h>
#include <linux/of.h>
#include <linux/mfd/mc13xxx.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/control.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/soc-dapm.h>
#include <linux/regmap.h>
#include "mc13783.h"
#define AUDIO_RX0_ALSPEN (1 << 5)
#define AUDIO_RX0_ALSPSEL (1 << 7)
#define AUDIO_RX0_ADDCDC (1 << 21)
#define AUDIO_RX0_ADDSTDC (1 << 22)
#define AUDIO_RX0_ADDRXIN (1 << 23)
#define AUDIO_RX1_PGARXEN (1 << 0);
#define AUDIO_RX1_PGASTEN (1 << 5)
#define AUDIO_RX1_ARXINEN (1 << 10)
#define AUDIO_TX_AMC1REN (1 << 5)
#define AUDIO_TX_AMC1LEN (1 << 7)
#define AUDIO_TX_AMC2EN (1 << 9)
#define AUDIO_TX_ATXINEN (1 << 11)
#define AUDIO_TX_RXINREC (1 << 13)
#define SSI_NETWORK_CDCTXRXSLOT(x) (((x) & 0x3) << 2)
#define SSI_NETWORK_CDCTXSECSLOT(x) (((x) & 0x3) << 4)
#define SSI_NETWORK_CDCRXSECSLOT(x) (((x) & 0x3) << 6)
#define SSI_NETWORK_CDCRXSECGAIN(x) (((x) & 0x3) << 8)
#define SSI_NETWORK_CDCSUMGAIN(x) (1 << 10)
#define SSI_NETWORK_CDCFSDLY(x) (1 << 11)
#define SSI_NETWORK_DAC_SLOTS_8 (1 << 12)
#define SSI_NETWORK_DAC_SLOTS_4 (2 << 12)
#define SSI_NETWORK_DAC_SLOTS_2 (3 << 12)
#define SSI_NETWORK_DAC_SLOT_MASK (3 << 12)
#define SSI_NETWORK_DAC_RXSLOT_0_1 (0 << 14)
#define SSI_NETWORK_DAC_RXSLOT_2_3 (1 << 14)
#define SSI_NETWORK_DAC_RXSLOT_4_5 (2 << 14)
#define SSI_NETWORK_DAC_RXSLOT_6_7 (3 << 14)
#define SSI_NETWORK_DAC_RXSLOT_MASK (3 << 14)
#define SSI_NETWORK_STDCRXSECSLOT(x) (((x) & 0x3) << 16)
#define SSI_NETWORK_STDCRXSECGAIN(x) (((x) & 0x3) << 18)
#define SSI_NETWORK_STDCSUMGAIN (1 << 20)
/*
* MC13783_AUDIO_CODEC and MC13783_AUDIO_DAC mostly share the same
* register layout
*/
#define AUDIO_SSI_SEL (1 << 0)
#define AUDIO_CLK_SEL (1 << 1)
#define AUDIO_CSM (1 << 2)
#define AUDIO_BCL_INV (1 << 3)
#define AUDIO_CFS_INV (1 << 4)
#define AUDIO_CFS(x) (((x) & 0x3) << 5)
#define AUDIO_CLK(x) (((x) & 0x7) << 7)
#define AUDIO_C_EN (1 << 11)
#define AUDIO_C_CLK_EN (1 << 12)
#define AUDIO_C_RESET (1 << 15)
#define AUDIO_CODEC_CDCFS8K16K (1 << 10)
#define AUDIO_DAC_CFS_DLY_B (1 << 10)
struct mc13783_priv {
struct mc13xxx *mc13xxx;
struct regmap *regmap;
enum mc13783_ssi_port adc_ssi_port;
enum mc13783_ssi_port dac_ssi_port;
};
/* Mapping between sample rates and register value */
static unsigned int mc13783_rates[] = {
8000, 11025, 12000, 16000,
22050, 24000, 32000, 44100,
48000, 64000, 96000
};
static int mc13783_pcm_hw_params_dac(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
unsigned int rate = params_rate(params);
int i;
for (i = 0; i < ARRAY_SIZE(mc13783_rates); i++) {
if (rate == mc13783_rates[i]) {
snd_soc_component_update_bits(component, MC13783_AUDIO_DAC,
0xf << 17, i << 17);
return 0;
}
}
return -EINVAL;
}
static int mc13783_pcm_hw_params_codec(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
unsigned int rate = params_rate(params);
unsigned int val;
switch (rate) {
case 8000:
val = 0;
break;
case 16000:
val = AUDIO_CODEC_CDCFS8K16K;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, MC13783_AUDIO_CODEC, AUDIO_CODEC_CDCFS8K16K,
val);
return 0;
}
static int mc13783_pcm_hw_params_sync(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
return mc13783_pcm_hw_params_dac(substream, params, dai);
else
return mc13783_pcm_hw_params_codec(substream, params, dai);
}
static int mc13783_set_fmt(struct snd_soc_dai *dai, unsigned int fmt,
unsigned int reg)
{
struct snd_soc_component *component = dai->component;
unsigned int val = 0;
unsigned int mask = AUDIO_CFS(3) | AUDIO_BCL_INV | AUDIO_CFS_INV |
AUDIO_CSM | AUDIO_C_CLK_EN | AUDIO_C_RESET;
/* DAI mode */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
val |= AUDIO_CFS(2);
break;
case SND_SOC_DAIFMT_DSP_A:
val |= AUDIO_CFS(1);
break;
default:
return -EINVAL;
}
/* DAI clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
val |= AUDIO_BCL_INV;
break;
case SND_SOC_DAIFMT_NB_IF:
val |= AUDIO_BCL_INV | AUDIO_CFS_INV;
break;
case SND_SOC_DAIFMT_IB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
val |= AUDIO_CFS_INV;
break;
}
/* DAI clock master masks */
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
val |= AUDIO_C_CLK_EN;
break;
case SND_SOC_DAIFMT_CBC_CFC:
val |= AUDIO_CSM;
break;
default:
return -EINVAL;
}
val |= AUDIO_C_RESET;
snd_soc_component_update_bits(component, reg, mask, val);
return 0;
}
static int mc13783_set_fmt_async(struct snd_soc_dai *dai, unsigned int fmt)
{
if (dai->id == MC13783_ID_STEREO_DAC)
return mc13783_set_fmt(dai, fmt, MC13783_AUDIO_DAC);
else
return mc13783_set_fmt(dai, fmt, MC13783_AUDIO_CODEC);
}
static int mc13783_set_fmt_sync(struct snd_soc_dai *dai, unsigned int fmt)
{
int ret;
ret = mc13783_set_fmt(dai, fmt, MC13783_AUDIO_DAC);
if (ret)
return ret;
/*
* In synchronous mode force the voice codec into consumer mode
* so that the clock / framesync from the stereo DAC is used
*/
fmt &= ~SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK;
fmt |= SND_SOC_DAIFMT_CBC_CFC;
ret = mc13783_set_fmt(dai, fmt, MC13783_AUDIO_CODEC);
return ret;
}
static int mc13783_sysclk[] = {
13000000,
15360000,
16800000,
-1,
26000000,
-1, /* 12000000, invalid for voice codec */
-1, /* 3686400, invalid for voice codec */
33600000,
};
static int mc13783_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir,
unsigned int reg)
{
struct snd_soc_component *component = dai->component;
int clk;
unsigned int val = 0;
unsigned int mask = AUDIO_CLK(0x7) | AUDIO_CLK_SEL;
for (clk = 0; clk < ARRAY_SIZE(mc13783_sysclk); clk++) {
if (mc13783_sysclk[clk] < 0)
continue;
if (mc13783_sysclk[clk] == freq)
break;
}
if (clk == ARRAY_SIZE(mc13783_sysclk))
return -EINVAL;
if (clk_id == MC13783_CLK_CLIB)
val |= AUDIO_CLK_SEL;
val |= AUDIO_CLK(clk);
snd_soc_component_update_bits(component, reg, mask, val);
return 0;
}
static int mc13783_set_sysclk_dac(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
return mc13783_set_sysclk(dai, clk_id, freq, dir, MC13783_AUDIO_DAC);
}
static int mc13783_set_sysclk_codec(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
return mc13783_set_sysclk(dai, clk_id, freq, dir, MC13783_AUDIO_CODEC);
}
static int mc13783_set_sysclk_sync(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
int ret;
ret = mc13783_set_sysclk(dai, clk_id, freq, dir, MC13783_AUDIO_DAC);
if (ret)
return ret;
return mc13783_set_sysclk(dai, clk_id, freq, dir, MC13783_AUDIO_CODEC);
}
static int mc13783_set_tdm_slot_dac(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask, int slots,
int slot_width)
{
struct snd_soc_component *component = dai->component;
unsigned int val = 0;
unsigned int mask = SSI_NETWORK_DAC_SLOT_MASK |
SSI_NETWORK_DAC_RXSLOT_MASK;
switch (slots) {
case 2:
val |= SSI_NETWORK_DAC_SLOTS_2;
break;
case 4:
val |= SSI_NETWORK_DAC_SLOTS_4;
break;
case 8:
val |= SSI_NETWORK_DAC_SLOTS_8;
break;
default:
return -EINVAL;
}
switch (rx_mask) {
case 0x03:
val |= SSI_NETWORK_DAC_RXSLOT_0_1;
break;
case 0x0c:
val |= SSI_NETWORK_DAC_RXSLOT_2_3;
break;
case 0x30:
val |= SSI_NETWORK_DAC_RXSLOT_4_5;
break;
case 0xc0:
val |= SSI_NETWORK_DAC_RXSLOT_6_7;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, MC13783_SSI_NETWORK, mask, val);
return 0;
}
static int mc13783_set_tdm_slot_codec(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask, int slots,
int slot_width)
{
struct snd_soc_component *component = dai->component;
unsigned int val = 0;
unsigned int mask = 0x3f;
if (slots != 4)
return -EINVAL;
if (tx_mask != 0x3)
return -EINVAL;
val |= (0x00 << 2); /* primary timeslot RX/TX(?) is 0 */
val |= (0x01 << 4); /* secondary timeslot TX is 1 */
snd_soc_component_update_bits(component, MC13783_SSI_NETWORK, mask, val);
return 0;
}
static int mc13783_set_tdm_slot_sync(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask, int slots,
int slot_width)
{
int ret;
ret = mc13783_set_tdm_slot_dac(dai, tx_mask, rx_mask, slots,
slot_width);
if (ret)
return ret;
ret = mc13783_set_tdm_slot_codec(dai, tx_mask, rx_mask, slots,
slot_width);
return ret;
}
static const struct snd_kcontrol_new mc1l_amp_ctl =
SOC_DAPM_SINGLE("Switch", MC13783_AUDIO_TX, 7, 1, 0);
static const struct snd_kcontrol_new mc1r_amp_ctl =
SOC_DAPM_SINGLE("Switch", MC13783_AUDIO_TX, 5, 1, 0);
static const struct snd_kcontrol_new mc2_amp_ctl =
SOC_DAPM_SINGLE("Switch", MC13783_AUDIO_TX, 9, 1, 0);
static const struct snd_kcontrol_new atx_amp_ctl =
SOC_DAPM_SINGLE("Switch", MC13783_AUDIO_TX, 11, 1, 0);
/* Virtual mux. The chip does the input selection automatically
* as soon as we enable one input. */
static const char * const adcl_enum_text[] = {
"MC1L", "RXINL",
};
static SOC_ENUM_SINGLE_VIRT_DECL(adcl_enum, adcl_enum_text);
static const struct snd_kcontrol_new left_input_mux =
SOC_DAPM_ENUM("Route", adcl_enum);
static const char * const adcr_enum_text[] = {
"MC1R", "MC2", "RXINR", "TXIN",
};
static SOC_ENUM_SINGLE_VIRT_DECL(adcr_enum, adcr_enum_text);
static const struct snd_kcontrol_new right_input_mux =
SOC_DAPM_ENUM("Route", adcr_enum);
static const struct snd_kcontrol_new samp_ctl =
SOC_DAPM_SINGLE("Switch", MC13783_AUDIO_RX0, 3, 1, 0);
static const char * const speaker_amp_source_text[] = {
"CODEC", "Right"
};
static SOC_ENUM_SINGLE_DECL(speaker_amp_source, MC13783_AUDIO_RX0, 4,
speaker_amp_source_text);
static const struct snd_kcontrol_new speaker_amp_source_mux =
SOC_DAPM_ENUM("Speaker Amp Source MUX", speaker_amp_source);
static const char * const headset_amp_source_text[] = {
"CODEC", "Mixer"
};
static SOC_ENUM_SINGLE_DECL(headset_amp_source, MC13783_AUDIO_RX0, 11,
headset_amp_source_text);
static const struct snd_kcontrol_new headset_amp_source_mux =
SOC_DAPM_ENUM("Headset Amp Source MUX", headset_amp_source);
static const struct snd_kcontrol_new cdcout_ctl =
SOC_DAPM_SINGLE("Switch", MC13783_AUDIO_RX0, 18, 1, 0);
static const struct snd_kcontrol_new adc_bypass_ctl =
SOC_DAPM_SINGLE("Switch", MC13783_AUDIO_CODEC, 16, 1, 0);
static const struct snd_kcontrol_new lamp_ctl =
SOC_DAPM_SINGLE("Switch", MC13783_AUDIO_RX0, 5, 1, 0);
static const struct snd_kcontrol_new hlamp_ctl =
SOC_DAPM_SINGLE("Switch", MC13783_AUDIO_RX0, 10, 1, 0);
static const struct snd_kcontrol_new hramp_ctl =
SOC_DAPM_SINGLE("Switch", MC13783_AUDIO_RX0, 9, 1, 0);
static const struct snd_kcontrol_new llamp_ctl =
SOC_DAPM_SINGLE("Switch", MC13783_AUDIO_RX0, 16, 1, 0);
static const struct snd_kcontrol_new lramp_ctl =
SOC_DAPM_SINGLE("Switch", MC13783_AUDIO_RX0, 15, 1, 0);
static const struct snd_soc_dapm_widget mc13783_dapm_widgets[] = {
/* Input */
SND_SOC_DAPM_INPUT("MC1LIN"),
SND_SOC_DAPM_INPUT("MC1RIN"),
SND_SOC_DAPM_INPUT("MC2IN"),
SND_SOC_DAPM_INPUT("RXINR"),
SND_SOC_DAPM_INPUT("RXINL"),
SND_SOC_DAPM_INPUT("TXIN"),
SND_SOC_DAPM_SUPPLY("MC1 Bias", MC13783_AUDIO_TX, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MC2 Bias", MC13783_AUDIO_TX, 1, 0, NULL, 0),
SND_SOC_DAPM_SWITCH("MC1L Amp", MC13783_AUDIO_TX, 7, 0, &mc1l_amp_ctl),
SND_SOC_DAPM_SWITCH("MC1R Amp", MC13783_AUDIO_TX, 5, 0, &mc1r_amp_ctl),
SND_SOC_DAPM_SWITCH("MC2 Amp", MC13783_AUDIO_TX, 9, 0, &mc2_amp_ctl),
SND_SOC_DAPM_SWITCH("TXIN Amp", MC13783_AUDIO_TX, 11, 0, &atx_amp_ctl),
SND_SOC_DAPM_MUX("PGA Left Input Mux", SND_SOC_NOPM, 0, 0,
&left_input_mux),
SND_SOC_DAPM_MUX("PGA Right Input Mux", SND_SOC_NOPM, 0, 0,
&right_input_mux),
SND_SOC_DAPM_MUX("Speaker Amp Source MUX", SND_SOC_NOPM, 0, 0,
&speaker_amp_source_mux),
SND_SOC_DAPM_MUX("Headset Amp Source MUX", SND_SOC_NOPM, 0, 0,
&headset_amp_source_mux),
SND_SOC_DAPM_PGA("PGA Left Input", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("PGA Right Input", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_ADC("ADC", "Capture", MC13783_AUDIO_CODEC, 11, 0),
SND_SOC_DAPM_SUPPLY("ADC_Reset", MC13783_AUDIO_CODEC, 15, 0, NULL, 0),
SND_SOC_DAPM_PGA("Voice CODEC PGA", MC13783_AUDIO_RX1, 0, 0, NULL, 0),
SND_SOC_DAPM_SWITCH("Voice CODEC Bypass", MC13783_AUDIO_CODEC, 16, 0,
&adc_bypass_ctl),
/* Output */
SND_SOC_DAPM_SUPPLY("DAC_E", MC13783_AUDIO_DAC, 11, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC_Reset", MC13783_AUDIO_DAC, 15, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("RXOUTL"),
SND_SOC_DAPM_OUTPUT("RXOUTR"),
SND_SOC_DAPM_OUTPUT("HSL"),
SND_SOC_DAPM_OUTPUT("HSR"),
SND_SOC_DAPM_OUTPUT("LSPL"),
SND_SOC_DAPM_OUTPUT("LSP"),
SND_SOC_DAPM_OUTPUT("SP"),
SND_SOC_DAPM_OUTPUT("CDCOUT"),
SND_SOC_DAPM_SWITCH("CDCOUT Switch", MC13783_AUDIO_RX0, 18, 0,
&cdcout_ctl),
SND_SOC_DAPM_SWITCH("Speaker Amp Switch", MC13783_AUDIO_RX0, 3, 0,
&samp_ctl),
SND_SOC_DAPM_SWITCH("Loudspeaker Amp", SND_SOC_NOPM, 0, 0, &lamp_ctl),
SND_SOC_DAPM_SWITCH("Headset Amp Left", MC13783_AUDIO_RX0, 10, 0,
&hlamp_ctl),
SND_SOC_DAPM_SWITCH("Headset Amp Right", MC13783_AUDIO_RX0, 9, 0,
&hramp_ctl),
SND_SOC_DAPM_SWITCH("Line out Amp Left", MC13783_AUDIO_RX0, 16, 0,
&llamp_ctl),
SND_SOC_DAPM_SWITCH("Line out Amp Right", MC13783_AUDIO_RX0, 15, 0,
&lramp_ctl),
SND_SOC_DAPM_DAC("DAC", "Playback", MC13783_AUDIO_RX0, 22, 0),
SND_SOC_DAPM_PGA("DAC PGA", MC13783_AUDIO_RX1, 5, 0, NULL, 0),
};
static struct snd_soc_dapm_route mc13783_routes[] = {
/* Input */
{ "MC1L Amp", NULL, "MC1LIN"},
{ "MC1R Amp", NULL, "MC1RIN" },
{ "MC2 Amp", NULL, "MC2IN" },
{ "TXIN Amp", NULL, "TXIN"},
{ "PGA Left Input Mux", "MC1L", "MC1L Amp" },
{ "PGA Left Input Mux", "RXINL", "RXINL"},
{ "PGA Right Input Mux", "MC1R", "MC1R Amp" },
{ "PGA Right Input Mux", "MC2", "MC2 Amp"},
{ "PGA Right Input Mux", "TXIN", "TXIN Amp"},
{ "PGA Right Input Mux", "RXINR", "RXINR"},
{ "PGA Left Input", NULL, "PGA Left Input Mux"},
{ "PGA Right Input", NULL, "PGA Right Input Mux"},
{ "ADC", NULL, "PGA Left Input"},
{ "ADC", NULL, "PGA Right Input"},
{ "ADC", NULL, "ADC_Reset"},
{ "Voice CODEC PGA", "Voice CODEC Bypass", "ADC" },
{ "Speaker Amp Source MUX", "CODEC", "Voice CODEC PGA"},
{ "Speaker Amp Source MUX", "Right", "DAC PGA"},
{ "Headset Amp Source MUX", "CODEC", "Voice CODEC PGA"},
{ "Headset Amp Source MUX", "Mixer", "DAC PGA"},
/* Output */
{ "HSL", NULL, "Headset Amp Left" },
{ "HSR", NULL, "Headset Amp Right"},
{ "RXOUTL", NULL, "Line out Amp Left"},
{ "RXOUTR", NULL, "Line out Amp Right"},
{ "SP", "Speaker Amp Switch", "Speaker Amp Source MUX"},
{ "LSP", "Loudspeaker Amp", "Speaker Amp Source MUX"},
{ "HSL", "Headset Amp Left", "Headset Amp Source MUX"},
{ "HSR", "Headset Amp Right", "Headset Amp Source MUX"},
{ "Line out Amp Left", NULL, "DAC PGA"},
{ "Line out Amp Right", NULL, "DAC PGA"},
{ "DAC PGA", NULL, "DAC"},
{ "DAC", NULL, "DAC_E"},
{ "CDCOUT", "CDCOUT Switch", "Voice CODEC PGA"},
};
static const char * const mc13783_3d_mixer[] = {"Stereo", "Phase Mix",
"Mono", "Mono Mix"};
static SOC_ENUM_SINGLE_DECL(mc13783_enum_3d_mixer,
MC13783_AUDIO_RX1, 16,
mc13783_3d_mixer);
static struct snd_kcontrol_new mc13783_control_list[] = {
SOC_SINGLE("Loudspeaker enable", MC13783_AUDIO_RX0, 5, 1, 0),
SOC_SINGLE("PCM Playback Volume", MC13783_AUDIO_RX1, 6, 15, 0),
SOC_SINGLE("PCM Playback Switch", MC13783_AUDIO_RX1, 5, 1, 0),
SOC_DOUBLE("PCM Capture Volume", MC13783_AUDIO_TX, 19, 14, 31, 0),
SOC_ENUM("3D Control", mc13783_enum_3d_mixer),
SOC_SINGLE("CDCOUT Switch", MC13783_AUDIO_RX0, 18, 1, 0),
SOC_SINGLE("Earpiece Amp Switch", MC13783_AUDIO_RX0, 3, 1, 0),
SOC_DOUBLE("Headset Amp Switch", MC13783_AUDIO_RX0, 10, 9, 1, 0),
SOC_DOUBLE("Line out Amp Switch", MC13783_AUDIO_RX0, 16, 15, 1, 0),
SOC_SINGLE("PCM Capture Mixin Switch", MC13783_AUDIO_RX0, 22, 1, 0),
SOC_SINGLE("Line in Capture Mixin Switch", MC13783_AUDIO_RX0, 23, 1, 0),
SOC_SINGLE("CODEC Capture Volume", MC13783_AUDIO_RX1, 1, 15, 0),
SOC_SINGLE("CODEC Capture Mixin Switch", MC13783_AUDIO_RX0, 21, 1, 0),
SOC_SINGLE("Line in Capture Volume", MC13783_AUDIO_RX1, 12, 15, 0),
SOC_SINGLE("Line in Capture Switch", MC13783_AUDIO_RX1, 10, 1, 0),
SOC_SINGLE("MC1 Capture Bias Switch", MC13783_AUDIO_TX, 0, 1, 0),
SOC_SINGLE("MC2 Capture Bias Switch", MC13783_AUDIO_TX, 1, 1, 0),
};
static int mc13783_probe(struct snd_soc_component *component)
{
struct mc13783_priv *priv = snd_soc_component_get_drvdata(component);
snd_soc_component_init_regmap(component,
dev_get_regmap(component->dev->parent, NULL));
/* these are the reset values */
mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_RX0, 0x25893);
mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_RX1, 0x00d35A);
mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_TX, 0x420000);
mc13xxx_reg_write(priv->mc13xxx, MC13783_SSI_NETWORK, 0x013060);
mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_CODEC, 0x180027);
mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_DAC, 0x0e0004);
if (priv->adc_ssi_port == MC13783_SSI1_PORT)
mc13xxx_reg_rmw(priv->mc13xxx, MC13783_AUDIO_CODEC,
AUDIO_SSI_SEL, 0);
else
mc13xxx_reg_rmw(priv->mc13xxx, MC13783_AUDIO_CODEC,
AUDIO_SSI_SEL, AUDIO_SSI_SEL);
if (priv->dac_ssi_port == MC13783_SSI1_PORT)
mc13xxx_reg_rmw(priv->mc13xxx, MC13783_AUDIO_DAC,
AUDIO_SSI_SEL, 0);
else
mc13xxx_reg_rmw(priv->mc13xxx, MC13783_AUDIO_DAC,
AUDIO_SSI_SEL, AUDIO_SSI_SEL);
return 0;
}
static void mc13783_remove(struct snd_soc_component *component)
{
struct mc13783_priv *priv = snd_soc_component_get_drvdata(component);
/* Make sure VAUDIOON is off */
mc13xxx_reg_rmw(priv->mc13xxx, MC13783_AUDIO_RX0, 0x3, 0);
}
#define MC13783_RATES_RECORD (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000)
#define MC13783_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE)
static const struct snd_soc_dai_ops mc13783_ops_dac = {
.hw_params = mc13783_pcm_hw_params_dac,
.set_fmt = mc13783_set_fmt_async,
.set_sysclk = mc13783_set_sysclk_dac,
.set_tdm_slot = mc13783_set_tdm_slot_dac,
};
static const struct snd_soc_dai_ops mc13783_ops_codec = {
.hw_params = mc13783_pcm_hw_params_codec,
.set_fmt = mc13783_set_fmt_async,
.set_sysclk = mc13783_set_sysclk_codec,
.set_tdm_slot = mc13783_set_tdm_slot_codec,
};
/*
* The mc13783 has two SSI ports, both of them can be routed either
* to the voice codec or the stereo DAC. When two different SSI ports
* are used for the voice codec and the stereo DAC we can do different
* formats and sysclock settings for playback and capture
* (mc13783-hifi-playback and mc13783-hifi-capture). Using the same port
* forces us to use symmetric rates (mc13783-hifi).
*/
static struct snd_soc_dai_driver mc13783_dai_async[] = {
{
.name = "mc13783-hifi-playback",
.id = MC13783_ID_STEREO_DAC,
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = MC13783_FORMATS,
},
.ops = &mc13783_ops_dac,
}, {
.name = "mc13783-hifi-capture",
.id = MC13783_ID_STEREO_CODEC,
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = MC13783_RATES_RECORD,
.formats = MC13783_FORMATS,
},
.ops = &mc13783_ops_codec,
},
};
static const struct snd_soc_dai_ops mc13783_ops_sync = {
.hw_params = mc13783_pcm_hw_params_sync,
.set_fmt = mc13783_set_fmt_sync,
.set_sysclk = mc13783_set_sysclk_sync,
.set_tdm_slot = mc13783_set_tdm_slot_sync,
};
static struct snd_soc_dai_driver mc13783_dai_sync[] = {
{
.name = "mc13783-hifi",
.id = MC13783_ID_SYNC,
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = MC13783_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = MC13783_RATES_RECORD,
.formats = MC13783_FORMATS,
},
.ops = &mc13783_ops_sync,
.symmetric_rate = 1,
}
};
static const struct snd_soc_component_driver soc_component_dev_mc13783 = {
.probe = mc13783_probe,
.remove = mc13783_remove,
.controls = mc13783_control_list,
.num_controls = ARRAY_SIZE(mc13783_control_list),
.dapm_widgets = mc13783_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(mc13783_dapm_widgets),
.dapm_routes = mc13783_routes,
.num_dapm_routes = ARRAY_SIZE(mc13783_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int __init mc13783_codec_probe(struct platform_device *pdev)
{
struct mc13783_priv *priv;
struct mc13xxx_codec_platform_data *pdata = pdev->dev.platform_data;
struct device_node *np;
int ret;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
if (pdata) {
priv->adc_ssi_port = pdata->adc_ssi_port;
priv->dac_ssi_port = pdata->dac_ssi_port;
} else {
np = of_get_child_by_name(pdev->dev.parent->of_node, "codec");
if (!np)
return -ENOSYS;
ret = of_property_read_u32(np, "adc-port", &priv->adc_ssi_port);
if (ret) {
of_node_put(np);
return ret;
}
ret = of_property_read_u32(np, "dac-port", &priv->dac_ssi_port);
if (ret) {
of_node_put(np);
return ret;
}
of_node_put(np);
}
dev_set_drvdata(&pdev->dev, priv);
priv->mc13xxx = dev_get_drvdata(pdev->dev.parent);
if (priv->adc_ssi_port == priv->dac_ssi_port)
ret = devm_snd_soc_register_component(&pdev->dev, &soc_component_dev_mc13783,
mc13783_dai_sync, ARRAY_SIZE(mc13783_dai_sync));
else
ret = devm_snd_soc_register_component(&pdev->dev, &soc_component_dev_mc13783,
mc13783_dai_async, ARRAY_SIZE(mc13783_dai_async));
return ret;
}
static struct platform_driver mc13783_codec_driver = {
.driver = {
.name = "mc13783-codec",
},
};
module_platform_driver_probe(mc13783_codec_driver, mc13783_codec_probe);
MODULE_DESCRIPTION("ASoC MC13783 driver");
MODULE_AUTHOR("Sascha Hauer, Pengutronix <[email protected]>");
MODULE_AUTHOR("Philippe Retornaz <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/mc13783.c |
// SPDX-License-Identifier: GPL-2.0
//
// tas2781-lib.c -- TAS2781 Common functions for HDA and ASoC Audio drivers
//
// Copyright 2023 Texas Instruments, Inc.
//
// Author: Shenghao Ding <[email protected]>
#include <linux/crc8.h>
#include <linux/firmware.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/of_irq.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tas2781.h>
#define TASDEVICE_CRC8_POLYNOMIAL 0x4d
static const struct regmap_range_cfg tasdevice_ranges[] = {
{
.range_min = 0,
.range_max = 256 * 128,
.selector_reg = TASDEVICE_PAGE_SELECT,
.selector_mask = 0xff,
.selector_shift = 0,
.window_start = 0,
.window_len = 128,
},
};
static const struct regmap_config tasdevice_regmap = {
.reg_bits = 8,
.val_bits = 8,
.cache_type = REGCACHE_RBTREE,
.ranges = tasdevice_ranges,
.num_ranges = ARRAY_SIZE(tasdevice_ranges),
.max_register = 256 * 128,
};
static int tasdevice_change_chn_book(struct tasdevice_priv *tas_priv,
unsigned short chn, int book)
{
struct i2c_client *client = (struct i2c_client *)tas_priv->client;
int ret = 0;
if (chn < tas_priv->ndev) {
struct tasdevice *tasdev = &tas_priv->tasdevice[chn];
struct regmap *map = tas_priv->regmap;
if (client->addr != tasdev->dev_addr) {
client->addr = tasdev->dev_addr;
/* All tas2781s share the same regmap, clear the page
* inside regmap once switching to another tas2781.
* Register 0 at any pages and any books inside tas2781
* is the same one for page-switching.
*/
ret = regmap_write(map, TASDEVICE_PAGE_SELECT, 0);
if (ret < 0) {
dev_err(tas_priv->dev, "%s, E=%d\n",
__func__, ret);
goto out;
}
}
if (tasdev->cur_book != book) {
ret = regmap_write(map, TASDEVICE_BOOKCTL_REG, book);
if (ret < 0) {
dev_err(tas_priv->dev, "%s, E=%d\n",
__func__, ret);
goto out;
}
tasdev->cur_book = book;
}
} else {
ret = -EINVAL;
dev_err(tas_priv->dev, "%s, no such channel(%d)\n", __func__,
chn);
}
out:
return ret;
}
int tasdevice_dev_read(struct tasdevice_priv *tas_priv,
unsigned short chn, unsigned int reg, unsigned int *val)
{
int ret = 0;
if (chn < tas_priv->ndev) {
struct regmap *map = tas_priv->regmap;
ret = tasdevice_change_chn_book(tas_priv, chn,
TASDEVICE_BOOK_ID(reg));
if (ret < 0)
goto out;
ret = regmap_read(map, TASDEVICE_PGRG(reg), val);
if (ret < 0)
dev_err(tas_priv->dev, "%s, E=%d\n", __func__, ret);
} else {
ret = -EINVAL;
dev_err(tas_priv->dev, "%s, no such channel(%d)\n", __func__,
chn);
}
out:
return ret;
}
EXPORT_SYMBOL_GPL(tasdevice_dev_read);
int tasdevice_dev_write(struct tasdevice_priv *tas_priv,
unsigned short chn, unsigned int reg, unsigned int value)
{
int ret = 0;
if (chn < tas_priv->ndev) {
struct regmap *map = tas_priv->regmap;
ret = tasdevice_change_chn_book(tas_priv, chn,
TASDEVICE_BOOK_ID(reg));
if (ret < 0)
goto out;
ret = regmap_write(map, TASDEVICE_PGRG(reg),
value);
if (ret < 0)
dev_err(tas_priv->dev, "%s, E=%d\n", __func__, ret);
} else {
ret = -EINVAL;
dev_err(tas_priv->dev, "%s, no such channel(%d)\n", __func__,
chn);
}
out:
return ret;
}
EXPORT_SYMBOL_GPL(tasdevice_dev_write);
int tasdevice_dev_bulk_write(
struct tasdevice_priv *tas_priv, unsigned short chn,
unsigned int reg, unsigned char *data,
unsigned int len)
{
int ret = 0;
if (chn < tas_priv->ndev) {
struct regmap *map = tas_priv->regmap;
ret = tasdevice_change_chn_book(tas_priv, chn,
TASDEVICE_BOOK_ID(reg));
if (ret < 0)
goto out;
ret = regmap_bulk_write(map, TASDEVICE_PGRG(reg),
data, len);
if (ret < 0)
dev_err(tas_priv->dev, "%s, E=%d\n", __func__, ret);
} else {
ret = -EINVAL;
dev_err(tas_priv->dev, "%s, no such channel(%d)\n", __func__,
chn);
}
out:
return ret;
}
EXPORT_SYMBOL_GPL(tasdevice_dev_bulk_write);
int tasdevice_dev_bulk_read(struct tasdevice_priv *tas_priv,
unsigned short chn, unsigned int reg, unsigned char *data,
unsigned int len)
{
int ret = 0;
if (chn < tas_priv->ndev) {
struct regmap *map = tas_priv->regmap;
ret = tasdevice_change_chn_book(tas_priv, chn,
TASDEVICE_BOOK_ID(reg));
if (ret < 0)
goto out;
ret = regmap_bulk_read(map, TASDEVICE_PGRG(reg), data, len);
if (ret < 0)
dev_err(tas_priv->dev, "%s, E=%d\n", __func__, ret);
} else
dev_err(tas_priv->dev, "%s, no such channel(%d)\n", __func__,
chn);
out:
return ret;
}
EXPORT_SYMBOL_GPL(tasdevice_dev_bulk_read);
int tasdevice_dev_update_bits(
struct tasdevice_priv *tas_priv, unsigned short chn,
unsigned int reg, unsigned int mask, unsigned int value)
{
int ret = 0;
if (chn < tas_priv->ndev) {
struct regmap *map = tas_priv->regmap;
ret = tasdevice_change_chn_book(tas_priv, chn,
TASDEVICE_BOOK_ID(reg));
if (ret < 0)
goto out;
ret = regmap_update_bits(map, TASDEVICE_PGRG(reg),
mask, value);
if (ret < 0)
dev_err(tas_priv->dev, "%s, E=%d\n", __func__, ret);
} else {
dev_err(tas_priv->dev, "%s, no such channel(%d)\n", __func__,
chn);
ret = -EINVAL;
}
out:
return ret;
}
EXPORT_SYMBOL_GPL(tasdevice_dev_update_bits);
struct tasdevice_priv *tasdevice_kzalloc(struct i2c_client *i2c)
{
struct tasdevice_priv *tas_priv;
tas_priv = devm_kzalloc(&i2c->dev, sizeof(*tas_priv), GFP_KERNEL);
if (!tas_priv)
return NULL;
tas_priv->dev = &i2c->dev;
tas_priv->client = (void *)i2c;
return tas_priv;
}
EXPORT_SYMBOL_GPL(tasdevice_kzalloc);
void tas2781_reset(struct tasdevice_priv *tas_dev)
{
int ret, i;
if (tas_dev->reset) {
gpiod_set_value_cansleep(tas_dev->reset, 0);
usleep_range(500, 1000);
gpiod_set_value_cansleep(tas_dev->reset, 1);
} else {
for (i = 0; i < tas_dev->ndev; i++) {
ret = tasdevice_dev_write(tas_dev, i,
TAS2781_REG_SWRESET,
TAS2781_REG_SWRESET_RESET);
if (ret < 0)
dev_err(tas_dev->dev,
"dev %d swreset fail, %d\n",
i, ret);
}
}
usleep_range(1000, 1050);
}
EXPORT_SYMBOL_GPL(tas2781_reset);
int tascodec_init(struct tasdevice_priv *tas_priv, void *codec,
void (*cont)(const struct firmware *fw, void *context))
{
int ret = 0;
/* Codec Lock Hold to ensure that codec_probe and firmware parsing and
* loading do not simultaneously execute.
*/
mutex_lock(&tas_priv->codec_lock);
scnprintf(tas_priv->rca_binaryname, 64, "%sRCA%d.bin",
tas_priv->dev_name, tas_priv->ndev);
crc8_populate_msb(tas_priv->crc8_lkp_tbl, TASDEVICE_CRC8_POLYNOMIAL);
tas_priv->codec = codec;
ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_UEVENT,
tas_priv->rca_binaryname, tas_priv->dev, GFP_KERNEL, tas_priv,
cont);
if (ret)
dev_err(tas_priv->dev, "request_firmware_nowait err:0x%08x\n",
ret);
/* Codec Lock Release*/
mutex_unlock(&tas_priv->codec_lock);
return ret;
}
EXPORT_SYMBOL_GPL(tascodec_init);
int tasdevice_init(struct tasdevice_priv *tas_priv)
{
int ret = 0;
int i;
tas_priv->regmap = devm_regmap_init_i2c(tas_priv->client,
&tasdevice_regmap);
if (IS_ERR(tas_priv->regmap)) {
ret = PTR_ERR(tas_priv->regmap);
dev_err(tas_priv->dev, "Failed to allocate register map: %d\n",
ret);
goto out;
}
tas_priv->cur_prog = -1;
tas_priv->cur_conf = -1;
for (i = 0; i < tas_priv->ndev; i++) {
tas_priv->tasdevice[i].cur_book = -1;
tas_priv->tasdevice[i].cur_prog = -1;
tas_priv->tasdevice[i].cur_conf = -1;
}
dev_set_drvdata(tas_priv->dev, tas_priv);
mutex_init(&tas_priv->codec_lock);
out:
return ret;
}
EXPORT_SYMBOL_GPL(tasdevice_init);
static void tasdev_dsp_prog_blk_remove(struct tasdevice_prog *prog)
{
struct tasdevice_data *tas_dt;
struct tasdev_blk *blk;
unsigned int i;
if (!prog)
return;
tas_dt = &(prog->dev_data);
if (!tas_dt->dev_blks)
return;
for (i = 0; i < tas_dt->nr_blk; i++) {
blk = &(tas_dt->dev_blks[i]);
kfree(blk->data);
}
kfree(tas_dt->dev_blks);
}
static void tasdev_dsp_prog_remove(struct tasdevice_prog *prog,
unsigned short nr)
{
int i;
for (i = 0; i < nr; i++)
tasdev_dsp_prog_blk_remove(&prog[i]);
kfree(prog);
}
static void tasdev_dsp_cfg_blk_remove(struct tasdevice_config *cfg)
{
struct tasdevice_data *tas_dt;
struct tasdev_blk *blk;
unsigned int i;
if (cfg) {
tas_dt = &(cfg->dev_data);
if (!tas_dt->dev_blks)
return;
for (i = 0; i < tas_dt->nr_blk; i++) {
blk = &(tas_dt->dev_blks[i]);
kfree(blk->data);
}
kfree(tas_dt->dev_blks);
}
}
static void tasdev_dsp_cfg_remove(struct tasdevice_config *config,
unsigned short nr)
{
int i;
for (i = 0; i < nr; i++)
tasdev_dsp_cfg_blk_remove(&config[i]);
kfree(config);
}
void tasdevice_dsp_remove(void *context)
{
struct tasdevice_priv *tas_dev = (struct tasdevice_priv *) context;
struct tasdevice_fw *tas_fmw = tas_dev->fmw;
if (!tas_dev->fmw)
return;
if (tas_fmw->programs)
tasdev_dsp_prog_remove(tas_fmw->programs,
tas_fmw->nr_programs);
if (tas_fmw->configs)
tasdev_dsp_cfg_remove(tas_fmw->configs,
tas_fmw->nr_configurations);
kfree(tas_fmw);
tas_dev->fmw = NULL;
}
EXPORT_SYMBOL_GPL(tasdevice_dsp_remove);
void tasdevice_remove(struct tasdevice_priv *tas_priv)
{
if (gpio_is_valid(tas_priv->irq_info.irq_gpio))
gpio_free(tas_priv->irq_info.irq_gpio);
kfree(tas_priv->acpi_subsystem_id);
mutex_destroy(&tas_priv->codec_lock);
}
EXPORT_SYMBOL_GPL(tasdevice_remove);
static int tasdevice_clamp(int val, int max, unsigned int invert)
{
if (val > max)
val = max;
if (invert)
val = max - val;
if (val < 0)
val = 0;
return val;
}
int tasdevice_amp_putvol(struct tasdevice_priv *tas_priv,
struct snd_ctl_elem_value *ucontrol, struct soc_mixer_control *mc)
{
unsigned int invert = mc->invert;
unsigned char mask;
int max = mc->max;
int err_cnt = 0;
int val, i, ret;
mask = (1 << fls(max)) - 1;
mask <<= mc->shift;
val = tasdevice_clamp(ucontrol->value.integer.value[0], max, invert);
for (i = 0; i < tas_priv->ndev; i++) {
ret = tasdevice_dev_update_bits(tas_priv, i,
mc->reg, mask, (unsigned int)(val << mc->shift));
if (!ret)
continue;
err_cnt++;
dev_err(tas_priv->dev, "set AMP vol error in dev %d\n", i);
}
/* All the devices set error, return 0 */
return (err_cnt == tas_priv->ndev) ? 0 : 1;
}
EXPORT_SYMBOL_GPL(tasdevice_amp_putvol);
int tasdevice_amp_getvol(struct tasdevice_priv *tas_priv,
struct snd_ctl_elem_value *ucontrol, struct soc_mixer_control *mc)
{
unsigned int invert = mc->invert;
unsigned char mask = 0;
int max = mc->max;
int ret = 0;
int val;
/* Read the primary device */
ret = tasdevice_dev_read(tas_priv, 0, mc->reg, &val);
if (ret) {
dev_err(tas_priv->dev, "%s, get AMP vol error\n", __func__);
goto out;
}
mask = (1 << fls(max)) - 1;
mask <<= mc->shift;
val = (val & mask) >> mc->shift;
val = tasdevice_clamp(val, max, invert);
ucontrol->value.integer.value[0] = val;
out:
return ret;
}
EXPORT_SYMBOL_GPL(tasdevice_amp_getvol);
int tasdevice_digital_putvol(struct tasdevice_priv *tas_priv,
struct snd_ctl_elem_value *ucontrol, struct soc_mixer_control *mc)
{
unsigned int invert = mc->invert;
int max = mc->max;
int err_cnt = 0;
int ret;
int val, i;
val = tasdevice_clamp(ucontrol->value.integer.value[0], max, invert);
for (i = 0; i < tas_priv->ndev; i++) {
ret = tasdevice_dev_write(tas_priv, i, mc->reg,
(unsigned int)val);
if (!ret)
continue;
err_cnt++;
dev_err(tas_priv->dev,
"set digital vol err in dev %d\n", i);
}
/* All the devices set error, return 0 */
return (err_cnt == tas_priv->ndev) ? 0 : 1;
}
EXPORT_SYMBOL_GPL(tasdevice_digital_putvol);
int tasdevice_digital_getvol(struct tasdevice_priv *tas_priv,
struct snd_ctl_elem_value *ucontrol, struct soc_mixer_control *mc)
{
unsigned int invert = mc->invert;
int max = mc->max;
int ret, val;
/* Read the primary device as the whole */
ret = tasdevice_dev_read(tas_priv, 0, mc->reg, &val);
if (ret) {
dev_err(tas_priv->dev, "%s, get digital vol error\n",
__func__);
goto out;
}
val = tasdevice_clamp(val, max, invert);
ucontrol->value.integer.value[0] = val;
out:
return ret;
}
EXPORT_SYMBOL_GPL(tasdevice_digital_getvol);
MODULE_DESCRIPTION("TAS2781 common library");
MODULE_AUTHOR("Shenghao Ding, TI, <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/tas2781-comlib.c |
// SPDX-License-Identifier: GPL-2.0
//
// rt1308.c -- RT1308 ALSA SoC amplifier component driver
//
// Copyright 2019 Realtek Semiconductor Corp.
// Author: Derek Fang <[email protected]>
//
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/acpi.h>
#include <linux/platform_device.h>
#include <linux/firmware.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "rl6231.h"
#include "rt1308.h"
static const struct reg_sequence init_list[] = {
{ RT1308_I2C_I2S_SDW_SET, 0x01014005 },
{ RT1308_CLASS_D_SET_2, 0x227f5501 },
{ RT1308_PADS_1, 0x50150505 },
{ RT1308_VREF, 0x18100000 },
{ RT1308_IV_SENSE, 0x87010000 },
{ RT1308_DUMMY_REG, 0x00000200 },
{ RT1308_SIL_DET, 0xe1c30000 },
{ RT1308_DC_CAL_2, 0x00ffff00 },
{ RT1308_CLK_DET, 0x01000000 },
{ RT1308_POWER_STATUS, 0x08800000 },
{ RT1308_DAC_SET, 0xafaf0700 },
};
#define RT1308_INIT_REG_LEN ARRAY_SIZE(init_list)
struct rt1308_priv {
struct snd_soc_component *component;
struct regmap *regmap;
int sysclk;
int sysclk_src;
int lrck;
int bclk;
int master;
int pll_src;
int pll_in;
int pll_out;
};
static const struct reg_default rt1308_reg[] = {
{ 0x01, 0x1f3f5f00 },
{ 0x02, 0x07000000 },
{ 0x03, 0x80003e00 },
{ 0x04, 0x80800600 },
{ 0x05, 0x0aaa1a0a },
{ 0x06, 0x52000000 },
{ 0x07, 0x00000000 },
{ 0x08, 0x00600000 },
{ 0x09, 0xe1030000 },
{ 0x0a, 0x00000000 },
{ 0x0b, 0x30000000 },
{ 0x0c, 0x7fff7000 },
{ 0x10, 0xffff0700 },
{ 0x11, 0x0a000000 },
{ 0x12, 0x60040000 },
{ 0x13, 0x00000000 },
{ 0x14, 0x0f300000 },
{ 0x15, 0x00000022 },
{ 0x16, 0x02000000 },
{ 0x17, 0x01004045 },
{ 0x18, 0x00000000 },
{ 0x19, 0x00000000 },
{ 0x1a, 0x80000000 },
{ 0x1b, 0x10325476 },
{ 0x1c, 0x1d1d0000 },
{ 0x20, 0xd2101300 },
{ 0x21, 0xf3ffff00 },
{ 0x22, 0x00000000 },
{ 0x23, 0x00000000 },
{ 0x24, 0x00000000 },
{ 0x25, 0x00000000 },
{ 0x26, 0x00000000 },
{ 0x27, 0x00000000 },
{ 0x28, 0x00000000 },
{ 0x29, 0x00000000 },
{ 0x2a, 0x00000000 },
{ 0x2b, 0x00000000 },
{ 0x2c, 0x00000000 },
{ 0x2d, 0x00000000 },
{ 0x2e, 0x00000000 },
{ 0x2f, 0x00000000 },
{ 0x30, 0x01000000 },
{ 0x31, 0x20025501 },
{ 0x32, 0x00000000 },
{ 0x33, 0x105a0000 },
{ 0x34, 0x10100000 },
{ 0x35, 0x2aaa52aa },
{ 0x36, 0x00c00000 },
{ 0x37, 0x20046100 },
{ 0x50, 0x10022f00 },
{ 0x51, 0x003c0000 },
{ 0x54, 0x04000000 },
{ 0x55, 0x01000000 },
{ 0x56, 0x02000000 },
{ 0x57, 0x02000000 },
{ 0x58, 0x02000000 },
{ 0x59, 0x02000000 },
{ 0x5b, 0x02000000 },
{ 0x5c, 0x00000000 },
{ 0x5d, 0x00000000 },
{ 0x5e, 0x00000000 },
{ 0x5f, 0x00000000 },
{ 0x60, 0x02000000 },
{ 0x61, 0x00000000 },
{ 0x62, 0x00000000 },
{ 0x63, 0x00000000 },
{ 0x64, 0x00000000 },
{ 0x65, 0x02000000 },
{ 0x66, 0x00000000 },
{ 0x67, 0x00000000 },
{ 0x68, 0x00000000 },
{ 0x69, 0x00000000 },
{ 0x6a, 0x02000000 },
{ 0x6c, 0x00000000 },
{ 0x6d, 0x00000000 },
{ 0x6e, 0x00000000 },
{ 0x70, 0x10EC1308 },
{ 0x71, 0x00000000 },
{ 0x72, 0x00000000 },
{ 0x73, 0x00000000 },
{ 0x74, 0x00000000 },
{ 0x75, 0x00000000 },
{ 0x76, 0x00000000 },
{ 0x77, 0x00000000 },
{ 0x78, 0x00000000 },
{ 0x79, 0x00000000 },
{ 0x7a, 0x00000000 },
{ 0x7b, 0x00000000 },
{ 0x7c, 0x00000000 },
{ 0x7d, 0x00000000 },
{ 0x7e, 0x00000000 },
{ 0x7f, 0x00020f00 },
{ 0x80, 0x00000000 },
{ 0x81, 0x00000000 },
{ 0x82, 0x00000000 },
{ 0x83, 0x00000000 },
{ 0x84, 0x00000000 },
{ 0x85, 0x00000000 },
{ 0x86, 0x00000000 },
{ 0x87, 0x00000000 },
{ 0x88, 0x00000000 },
{ 0x89, 0x00000000 },
{ 0x8a, 0x00000000 },
{ 0x8b, 0x00000000 },
{ 0x8c, 0x00000000 },
{ 0x8d, 0x00000000 },
{ 0x8e, 0x00000000 },
{ 0x90, 0x50250905 },
{ 0x91, 0x15050000 },
{ 0xa0, 0x00000000 },
{ 0xa1, 0x00000000 },
{ 0xa2, 0x00000000 },
{ 0xa3, 0x00000000 },
{ 0xa4, 0x00000000 },
{ 0xb0, 0x00000000 },
{ 0xb1, 0x00000000 },
{ 0xb2, 0x00000000 },
{ 0xb3, 0x00000000 },
{ 0xb4, 0x00000000 },
{ 0xb5, 0x00000000 },
{ 0xb6, 0x00000000 },
{ 0xb7, 0x00000000 },
{ 0xb8, 0x00000000 },
{ 0xb9, 0x00000000 },
{ 0xba, 0x00000000 },
{ 0xbb, 0x00000000 },
{ 0xc0, 0x01000000 },
{ 0xc1, 0x00000000 },
{ 0xf0, 0x00000000 },
};
static int rt1308_reg_init(struct snd_soc_component *component)
{
struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
return regmap_multi_reg_write(rt1308->regmap, init_list,
RT1308_INIT_REG_LEN);
}
static bool rt1308_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case RT1308_RESET:
case RT1308_RESET_N:
case RT1308_CLK_2:
case RT1308_SIL_DET:
case RT1308_CLK_DET:
case RT1308_DC_DET:
case RT1308_DAC_SET:
case RT1308_DAC_BUF:
case RT1308_SDW_REG_RDATA:
case RT1308_DC_CAL_1:
case RT1308_PVDD_OFFSET_CTL:
case RT1308_CAL_OFFSET_DAC_PBTL:
case RT1308_CAL_OFFSET_DAC_L:
case RT1308_CAL_OFFSET_DAC_R:
case RT1308_CAL_OFFSET_PWM_L:
case RT1308_CAL_OFFSET_PWM_R:
case RT1308_CAL_PWM_VOS_ADC_L:
case RT1308_CAL_PWM_VOS_ADC_R:
case RT1308_MBIAS:
case RT1308_POWER_STATUS:
case RT1308_POWER_INT:
case RT1308_SINE_TONE_GEN_2:
case RT1308_BQ_SET:
case RT1308_BQ_PARA_UPDATE:
case RT1308_VEN_DEV_ID:
case RT1308_VERSION_ID:
case RT1308_EFUSE_1:
case RT1308_EFUSE_READ_PVDD_L:
case RT1308_EFUSE_READ_PVDD_R:
case RT1308_EFUSE_READ_PVDD_PTBL:
case RT1308_EFUSE_READ_DEV:
case RT1308_EFUSE_READ_R0:
case RT1308_EFUSE_READ_ADC_L:
case RT1308_EFUSE_READ_ADC_R:
case RT1308_EFUSE_READ_ADC_PBTL:
case RT1308_EFUSE_RESERVE:
case RT1308_EFUSE_DATA_0_MSB:
case RT1308_EFUSE_DATA_0_LSB:
case RT1308_EFUSE_DATA_1_MSB:
case RT1308_EFUSE_DATA_1_LSB:
case RT1308_EFUSE_DATA_2_MSB:
case RT1308_EFUSE_DATA_2_LSB:
case RT1308_EFUSE_DATA_3_MSB:
case RT1308_EFUSE_DATA_3_LSB:
case RT1308_EFUSE_STATUS_1:
case RT1308_EFUSE_STATUS_2:
case RT1308_DUMMY_REG:
return true;
default:
return false;
}
}
static bool rt1308_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case RT1308_RESET:
case RT1308_RESET_N:
case RT1308_CLK_GATING ... RT1308_DC_DET_THRES:
case RT1308_DAC_SET ... RT1308_AD_FILTER_SET:
case RT1308_DC_CAL_1 ... RT1308_POWER_INT:
case RT1308_SINE_TONE_GEN_1:
case RT1308_SINE_TONE_GEN_2:
case RT1308_BQ_SET:
case RT1308_BQ_PARA_UPDATE:
case RT1308_BQ_PRE_VOL_L ... RT1308_BQ_POST_VOL_R:
case RT1308_BQ1_L_H0 ... RT1308_BQ2_R_A2:
case RT1308_VEN_DEV_ID:
case RT1308_VERSION_ID:
case RT1308_SPK_BOUND:
case RT1308_BQ1_EQ_L_1 ... RT1308_BQ2_EQ_R_3:
case RT1308_EFUSE_1 ... RT1308_EFUSE_RESERVE:
case RT1308_PADS_1:
case RT1308_PADS_2:
case RT1308_TEST_MODE:
case RT1308_TEST_1:
case RT1308_TEST_2:
case RT1308_TEST_3:
case RT1308_TEST_4:
case RT1308_EFUSE_DATA_0_MSB ... RT1308_EFUSE_STATUS_2:
case RT1308_TCON_1:
case RT1308_TCON_2:
case RT1308_DUMMY_REG:
case RT1308_MAX_REG:
return true;
default:
return false;
}
}
static int rt1308_classd_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
msleep(30);
snd_soc_component_update_bits(component, RT1308_POWER_STATUS,
RT1308_POW_PDB_REG_BIT | RT1308_POW_PDB_MN_BIT,
RT1308_POW_PDB_REG_BIT | RT1308_POW_PDB_MN_BIT);
msleep(40);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, RT1308_POWER_STATUS,
RT1308_POW_PDB_REG_BIT | RT1308_POW_PDB_MN_BIT, 0);
usleep_range(150000, 200000);
break;
default:
break;
}
return 0;
}
static const char * const rt1308_rx_data_ch_select[] = {
"LR",
"LL",
"RL",
"RR",
};
static SOC_ENUM_SINGLE_DECL(rt1308_rx_data_ch_enum, RT1308_DATA_PATH, 24,
rt1308_rx_data_ch_select);
static const struct snd_kcontrol_new rt1308_snd_controls[] = {
/* I2S Data Channel Selection */
SOC_ENUM("RX Channel Select", rt1308_rx_data_ch_enum),
};
static const struct snd_kcontrol_new rt1308_sto_dac_l =
SOC_DAPM_SINGLE("Switch", RT1308_DAC_SET,
RT1308_DVOL_MUTE_L_EN_SFT, 1, 1);
static const struct snd_kcontrol_new rt1308_sto_dac_r =
SOC_DAPM_SINGLE("Switch", RT1308_DAC_SET,
RT1308_DVOL_MUTE_R_EN_SFT, 1, 1);
static const struct snd_soc_dapm_widget rt1308_dapm_widgets[] = {
/* Audio Interface */
SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
/* Supply Widgets */
SND_SOC_DAPM_SUPPLY("MBIAS20U", RT1308_POWER,
RT1308_POW_MBIAS20U_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ALDO", RT1308_POWER,
RT1308_POW_ALDO_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DBG", RT1308_POWER,
RT1308_POW_DBG_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DACL", RT1308_POWER,
RT1308_POW_DACL_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CLK25M", RT1308_POWER,
RT1308_POW_CLK25M_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC_R", RT1308_POWER,
RT1308_POW_ADC_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC_L", RT1308_POWER,
RT1308_POW_ADC_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DLDO", RT1308_POWER,
RT1308_POW_DLDO_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("VREF", RT1308_POWER,
RT1308_POW_VREF_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MIXER_R", RT1308_POWER,
RT1308_POW_MIXER_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MIXER_L", RT1308_POWER,
RT1308_POW_MIXER_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MBIAS4U", RT1308_POWER,
RT1308_POW_MBIAS4U_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PLL2_LDO", RT1308_POWER,
RT1308_POW_PLL2_LDO_EN_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PLL2B", RT1308_POWER,
RT1308_POW_PLL2B_EN_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PLL2F", RT1308_POWER,
RT1308_POW_PLL2F_EN_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PLL2F2", RT1308_POWER,
RT1308_POW_PLL2F2_EN_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PLL2B2", RT1308_POWER,
RT1308_POW_PLL2B2_EN_BIT, 0, NULL, 0),
/* Digital Interface */
SND_SOC_DAPM_SUPPLY("DAC Power", RT1308_POWER,
RT1308_POW_DAC1_BIT, 0, NULL, 0),
SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SWITCH("DAC L", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_l),
SND_SOC_DAPM_SWITCH("DAC R", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_r),
/* Output Lines */
SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
rt1308_classd_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_OUTPUT("SPOL"),
SND_SOC_DAPM_OUTPUT("SPOR"),
};
static const struct snd_soc_dapm_route rt1308_dapm_routes[] = {
{ "DAC", NULL, "AIF1RX" },
{ "DAC", NULL, "MBIAS20U" },
{ "DAC", NULL, "ALDO" },
{ "DAC", NULL, "DBG" },
{ "DAC", NULL, "DACL" },
{ "DAC", NULL, "CLK25M" },
{ "DAC", NULL, "ADC_R" },
{ "DAC", NULL, "ADC_L" },
{ "DAC", NULL, "DLDO" },
{ "DAC", NULL, "VREF" },
{ "DAC", NULL, "MIXER_R" },
{ "DAC", NULL, "MIXER_L" },
{ "DAC", NULL, "MBIAS4U" },
{ "DAC", NULL, "PLL2_LDO" },
{ "DAC", NULL, "PLL2B" },
{ "DAC", NULL, "PLL2F" },
{ "DAC", NULL, "PLL2F2" },
{ "DAC", NULL, "PLL2B2" },
{ "DAC L", "Switch", "DAC" },
{ "DAC R", "Switch", "DAC" },
{ "DAC L", NULL, "DAC Power" },
{ "DAC R", NULL, "DAC Power" },
{ "CLASS D", NULL, "DAC L" },
{ "CLASS D", NULL, "DAC R" },
{ "SPOL", NULL, "CLASS D" },
{ "SPOR", NULL, "CLASS D" },
};
static int rt1308_get_clk_info(int sclk, int rate)
{
int i;
static const int pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
if (sclk <= 0 || rate <= 0)
return -EINVAL;
rate = rate << 8;
for (i = 0; i < ARRAY_SIZE(pd); i++)
if (sclk == rate * pd[i])
return i;
return -EINVAL;
}
static int rt1308_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
unsigned int val_len = 0, val_clk, mask_clk;
int pre_div, bclk_ms, frame_size;
rt1308->lrck = params_rate(params);
pre_div = rt1308_get_clk_info(rt1308->sysclk, rt1308->lrck);
if (pre_div < 0) {
dev_err(component->dev,
"Unsupported clock setting %d\n", rt1308->lrck);
return -EINVAL;
}
frame_size = snd_soc_params_to_frame_size(params);
if (frame_size < 0) {
dev_err(component->dev, "Unsupported frame size: %d\n",
frame_size);
return -EINVAL;
}
bclk_ms = frame_size > 32;
rt1308->bclk = rt1308->lrck * (32 << bclk_ms);
dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
bclk_ms, pre_div, dai->id);
dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
rt1308->lrck, pre_div, dai->id);
switch (params_width(params)) {
case 16:
val_len |= RT1308_I2S_DL_SEL_16B;
break;
case 20:
val_len |= RT1308_I2S_DL_SEL_20B;
break;
case 24:
val_len |= RT1308_I2S_DL_SEL_24B;
break;
case 8:
val_len |= RT1308_I2S_DL_SEL_8B;
break;
default:
return -EINVAL;
}
switch (dai->id) {
case RT1308_AIF1:
mask_clk = RT1308_DIV_FS_SYS_MASK;
val_clk = pre_div << RT1308_DIV_FS_SYS_SFT;
snd_soc_component_update_bits(component,
RT1308_I2S_SET_2, RT1308_I2S_DL_SEL_MASK,
val_len);
break;
default:
dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
return -EINVAL;
}
snd_soc_component_update_bits(component, RT1308_CLK_1,
mask_clk, val_clk);
return 0;
}
static int rt1308_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0, reg1_val = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
rt1308->master = 0;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_LEFT_J:
reg_val |= RT1308_I2S_DF_SEL_LEFT;
break;
case SND_SOC_DAIFMT_DSP_A:
reg_val |= RT1308_I2S_DF_SEL_PCM_A;
break;
case SND_SOC_DAIFMT_DSP_B:
reg_val |= RT1308_I2S_DF_SEL_PCM_B;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
reg1_val |= RT1308_I2S_BCLK_INV;
break;
default:
return -EINVAL;
}
switch (dai->id) {
case RT1308_AIF1:
snd_soc_component_update_bits(component,
RT1308_I2S_SET_1, RT1308_I2S_DF_SEL_MASK,
reg_val);
snd_soc_component_update_bits(component,
RT1308_I2S_SET_2, RT1308_I2S_BCLK_MASK,
reg1_val);
break;
default:
dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
return -EINVAL;
}
return 0;
}
static int rt1308_set_component_sysclk(struct snd_soc_component *component,
int clk_id, int source, unsigned int freq, int dir)
{
struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0;
if (freq == rt1308->sysclk && clk_id == rt1308->sysclk_src)
return 0;
switch (clk_id) {
case RT1308_FS_SYS_S_MCLK:
reg_val |= RT1308_SEL_FS_SYS_SRC_MCLK;
snd_soc_component_update_bits(component,
RT1308_CLK_DET, RT1308_MCLK_DET_EN_MASK,
RT1308_MCLK_DET_EN);
break;
case RT1308_FS_SYS_S_BCLK:
reg_val |= RT1308_SEL_FS_SYS_SRC_BCLK;
break;
case RT1308_FS_SYS_S_PLL:
reg_val |= RT1308_SEL_FS_SYS_SRC_PLL;
break;
case RT1308_FS_SYS_S_RCCLK:
reg_val |= RT1308_SEL_FS_SYS_SRC_RCCLK;
break;
default:
dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
return -EINVAL;
}
snd_soc_component_update_bits(component, RT1308_CLK_1,
RT1308_SEL_FS_SYS_MASK, reg_val);
rt1308->sysclk = freq;
rt1308->sysclk_src = clk_id;
dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
freq, clk_id);
return 0;
}
static int rt1308_set_component_pll(struct snd_soc_component *component,
int pll_id, int source, unsigned int freq_in,
unsigned int freq_out)
{
struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
struct rl6231_pll_code pll_code;
int ret;
if (source == rt1308->pll_src && freq_in == rt1308->pll_in &&
freq_out == rt1308->pll_out)
return 0;
if (!freq_in || !freq_out) {
dev_dbg(component->dev, "PLL disabled\n");
rt1308->pll_in = 0;
rt1308->pll_out = 0;
snd_soc_component_update_bits(component,
RT1308_CLK_1, RT1308_SEL_FS_SYS_MASK,
RT1308_SEL_FS_SYS_SRC_MCLK);
return 0;
}
switch (source) {
case RT1308_PLL_S_MCLK:
snd_soc_component_update_bits(component,
RT1308_CLK_2, RT1308_SEL_PLL_SRC_MASK,
RT1308_SEL_PLL_SRC_MCLK);
snd_soc_component_update_bits(component,
RT1308_CLK_DET, RT1308_MCLK_DET_EN_MASK,
RT1308_MCLK_DET_EN);
break;
case RT1308_PLL_S_BCLK:
snd_soc_component_update_bits(component,
RT1308_CLK_2, RT1308_SEL_PLL_SRC_MASK,
RT1308_SEL_PLL_SRC_BCLK);
break;
case RT1308_PLL_S_RCCLK:
snd_soc_component_update_bits(component,
RT1308_CLK_2, RT1308_SEL_PLL_SRC_MASK,
RT1308_SEL_PLL_SRC_RCCLK);
freq_in = 25000000;
break;
default:
dev_err(component->dev, "Unknown PLL Source %d\n", source);
return -EINVAL;
}
ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
if (ret < 0) {
dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
return ret;
}
dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
pll_code.n_code, pll_code.k_code);
snd_soc_component_write(component, RT1308_PLL_1,
(pll_code.k_code << RT1308_PLL1_K_SFT) |
(pll_code.m_bp << RT1308_PLL1_M_BYPASS_SFT) |
((pll_code.m_bp ? 0 : pll_code.m_code) << RT1308_PLL1_M_SFT) |
(pll_code.n_code << RT1308_PLL1_N_SFT));
rt1308->pll_in = freq_in;
rt1308->pll_out = freq_out;
rt1308->pll_src = source;
return 0;
}
static int rt1308_probe(struct snd_soc_component *component)
{
struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
rt1308->component = component;
return rt1308_reg_init(component);
}
static void rt1308_remove(struct snd_soc_component *component)
{
struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
regmap_write(rt1308->regmap, RT1308_RESET, 0);
}
#ifdef CONFIG_PM
static int rt1308_suspend(struct snd_soc_component *component)
{
struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
regcache_cache_only(rt1308->regmap, true);
regcache_mark_dirty(rt1308->regmap);
return 0;
}
static int rt1308_resume(struct snd_soc_component *component)
{
struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
regcache_cache_only(rt1308->regmap, false);
regcache_sync(rt1308->regmap);
return 0;
}
#else
#define rt1308_suspend NULL
#define rt1308_resume NULL
#endif
#define RT1308_STEREO_RATES SNDRV_PCM_RATE_48000
#define RT1308_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE)
static const struct snd_soc_dai_ops rt1308_aif_dai_ops = {
.hw_params = rt1308_hw_params,
.set_fmt = rt1308_set_dai_fmt,
};
static struct snd_soc_dai_driver rt1308_dai[] = {
{
.name = "rt1308-aif",
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT1308_STEREO_RATES,
.formats = RT1308_FORMATS,
},
.ops = &rt1308_aif_dai_ops,
},
};
static const struct snd_soc_component_driver soc_component_dev_rt1308 = {
.probe = rt1308_probe,
.remove = rt1308_remove,
.suspend = rt1308_suspend,
.resume = rt1308_resume,
.controls = rt1308_snd_controls,
.num_controls = ARRAY_SIZE(rt1308_snd_controls),
.dapm_widgets = rt1308_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt1308_dapm_widgets),
.dapm_routes = rt1308_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(rt1308_dapm_routes),
.set_sysclk = rt1308_set_component_sysclk,
.set_pll = rt1308_set_component_pll,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config rt1308_regmap = {
.reg_bits = 8,
.val_bits = 32,
.max_register = RT1308_MAX_REG,
.volatile_reg = rt1308_volatile_register,
.readable_reg = rt1308_readable_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = rt1308_reg,
.num_reg_defaults = ARRAY_SIZE(rt1308_reg),
.use_single_read = true,
.use_single_write = true,
};
#ifdef CONFIG_OF
static const struct of_device_id rt1308_of_match[] = {
{ .compatible = "realtek,rt1308", },
{ },
};
MODULE_DEVICE_TABLE(of, rt1308_of_match);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id rt1308_acpi_match[] = {
{ "10EC1308", 0, },
{ },
};
MODULE_DEVICE_TABLE(acpi, rt1308_acpi_match);
#endif
static const struct i2c_device_id rt1308_i2c_id[] = {
{ "rt1308", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, rt1308_i2c_id);
static void rt1308_efuse(struct rt1308_priv *rt1308)
{
regmap_write(rt1308->regmap, RT1308_RESET, 0);
regmap_write(rt1308->regmap, RT1308_POWER_STATUS, 0x01800000);
msleep(100);
regmap_write(rt1308->regmap, RT1308_EFUSE_1, 0x44fe0f00);
msleep(20);
regmap_write(rt1308->regmap, RT1308_PVDD_OFFSET_CTL, 0x10000000);
}
static int rt1308_i2c_probe(struct i2c_client *i2c)
{
struct rt1308_priv *rt1308;
int ret;
unsigned int val;
rt1308 = devm_kzalloc(&i2c->dev, sizeof(struct rt1308_priv),
GFP_KERNEL);
if (rt1308 == NULL)
return -ENOMEM;
i2c_set_clientdata(i2c, rt1308);
rt1308->regmap = devm_regmap_init_i2c(i2c, &rt1308_regmap);
if (IS_ERR(rt1308->regmap)) {
ret = PTR_ERR(rt1308->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
regmap_read(rt1308->regmap, RT1308_VEN_DEV_ID, &val);
/* ignore last byte difference */
if ((val & 0xFFFFFF00) != RT1308_DEVICE_ID_NUM) {
dev_err(&i2c->dev,
"Device with ID register %x is not rt1308\n", val);
return -ENODEV;
}
rt1308_efuse(rt1308);
return devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_rt1308,
rt1308_dai, ARRAY_SIZE(rt1308_dai));
}
static void rt1308_i2c_shutdown(struct i2c_client *client)
{
struct rt1308_priv *rt1308 = i2c_get_clientdata(client);
regmap_write(rt1308->regmap, RT1308_RESET, 0);
}
static struct i2c_driver rt1308_i2c_driver = {
.driver = {
.name = "rt1308",
.of_match_table = of_match_ptr(rt1308_of_match),
.acpi_match_table = ACPI_PTR(rt1308_acpi_match),
},
.probe = rt1308_i2c_probe,
.shutdown = rt1308_i2c_shutdown,
.id_table = rt1308_i2c_id,
};
module_i2c_driver(rt1308_i2c_driver);
MODULE_DESCRIPTION("ASoC RT1308 amplifier driver");
MODULE_AUTHOR("Derek Fang <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/rt1308.c |
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/module.h>
#include <sound/soc.h>
static struct snd_soc_dai_driver chv3_codec_dai = {
.name = "chv3-codec-hifi",
.capture = {
.stream_name = "Capture",
.channels_min = 8,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.formats = SNDRV_PCM_FMTBIT_S32_LE,
},
};
static const struct snd_soc_component_driver soc_component_dev_chv3_codec = {
};
static int chv3_codec_probe(struct platform_device *pdev)
{
return devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_chv3_codec, &chv3_codec_dai, 1);
}
static const struct of_device_id chv3_codec_of_match[] = {
{ .compatible = "google,chv3-codec", },
{ }
};
static struct platform_driver chv3_codec_platform_driver = {
.driver = {
.name = "chv3-codec",
.of_match_table = chv3_codec_of_match,
},
.probe = chv3_codec_probe,
};
module_platform_driver(chv3_codec_platform_driver);
MODULE_DESCRIPTION("ASoC Chameleon v3 codec driver");
MODULE_AUTHOR("Pawel Anikiel <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/chv3-codec.c |
// SPDX-License-Identifier: GPL-2.0
/*
* rt715.c -- rt715 ALSA SoC audio driver
*
* Copyright(c) 2019 Realtek Semiconductor Corp.
*
* ALC715 ASoC Codec Driver based Intel Dummy SdW codec driver
*
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/pm_runtime.h>
#include <linux/pm.h>
#include <linux/soundwire/sdw.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/sdw.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/hda_verbs.h>
#include "rt715.h"
static int rt715_index_write(struct regmap *regmap, unsigned int reg,
unsigned int value)
{
int ret;
unsigned int addr = ((RT715_PRIV_INDEX_W_H) << 8) | reg;
ret = regmap_write(regmap, addr, value);
if (ret < 0) {
pr_err("Failed to set private value: %08x <= %04x %d\n", ret,
addr, value);
}
return ret;
}
static int rt715_index_write_nid(struct regmap *regmap,
unsigned int nid, unsigned int reg, unsigned int value)
{
int ret;
unsigned int addr = ((RT715_PRIV_INDEX_W_H_2 | nid) << 8) | reg;
ret = regmap_write(regmap, addr, value);
if (ret < 0)
pr_err("Failed to set private value: %06x <= %04x ret=%d\n",
addr, value, ret);
return ret;
}
static int rt715_index_read_nid(struct regmap *regmap,
unsigned int nid, unsigned int reg, unsigned int *value)
{
int ret;
unsigned int addr = ((RT715_PRIV_INDEX_W_H_2 | nid) << 8) | reg;
*value = 0;
ret = regmap_read(regmap, addr, value);
if (ret < 0)
pr_err("Failed to get private value: %06x => %04x ret=%d\n",
addr, *value, ret);
return ret;
}
static int rt715_index_update_bits(struct regmap *regmap, unsigned int nid,
unsigned int reg, unsigned int mask, unsigned int val)
{
unsigned int tmp, orig;
int ret;
ret = rt715_index_read_nid(regmap, nid, reg, &orig);
if (ret < 0)
return ret;
tmp = orig & ~mask;
tmp |= val & mask;
return rt715_index_write_nid(regmap, nid, reg, tmp);
}
static void rt715_reset(struct regmap *regmap)
{
regmap_write(regmap, RT715_FUNC_RESET, 0);
rt715_index_update_bits(regmap, RT715_VENDOR_REGISTERS,
RT715_VD_CLEAR_CTRL, RT715_CLEAR_HIDDEN_REG,
RT715_CLEAR_HIDDEN_REG);
}
static void rt715_get_gain(struct rt715_priv *rt715, unsigned int addr_h,
unsigned int addr_l, unsigned int val_h,
unsigned int *r_val, unsigned int *l_val)
{
int ret;
/* R Channel */
*r_val = val_h << 8;
ret = regmap_read(rt715->regmap, addr_l, r_val);
if (ret < 0)
pr_err("Failed to get R channel gain.\n");
/* L Channel */
val_h |= 0x20;
*l_val = val_h << 8;
ret = regmap_read(rt715->regmap, addr_h, l_val);
if (ret < 0)
pr_err("Failed to get L channel gain.\n");
}
/* For Verb-Set Amplifier Gain (Verb ID = 3h) */
static int rt715_set_amp_gain_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct snd_soc_dapm_context *dapm =
snd_soc_component_get_dapm(component);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
unsigned int addr_h, addr_l, val_h, val_ll, val_lr;
unsigned int read_ll, read_rl, i;
unsigned int k_vol_changed = 0;
for (i = 0; i < 2; i++) {
if (ucontrol->value.integer.value[i] != rt715->kctl_2ch_vol_ori[i]) {
k_vol_changed = 1;
break;
}
}
/* Can't use update bit function, so read the original value first */
addr_h = mc->reg;
addr_l = mc->rreg;
if (mc->shift == RT715_DIR_OUT_SFT) /* output */
val_h = 0x80;
else /* input */
val_h = 0x0;
rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll);
if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
regmap_write(rt715->regmap,
RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D0);
/* L Channel */
rt715->kctl_2ch_vol_ori[0] = ucontrol->value.integer.value[0];
/* for gain */
val_ll = ((ucontrol->value.integer.value[0]) & 0x7f);
if (val_ll > mc->max)
val_ll = mc->max;
/* keep mute status */
val_ll |= read_ll & 0x80;
/* R Channel */
rt715->kctl_2ch_vol_ori[1] = ucontrol->value.integer.value[1];
/* for gain */
val_lr = ((ucontrol->value.integer.value[1]) & 0x7f);
if (val_lr > mc->max)
val_lr = mc->max;
/* keep mute status */
val_lr |= read_rl & 0x80;
for (i = 0; i < 3; i++) { /* retry 3 times at most */
if (val_ll == val_lr) {
/* Set both L/R channels at the same time */
val_h = (1 << mc->shift) | (3 << 4);
regmap_write(rt715->regmap, addr_h,
(val_h << 8) | val_ll);
regmap_write(rt715->regmap, addr_l,
(val_h << 8) | val_ll);
} else {
/* Lch*/
val_h = (1 << mc->shift) | (1 << 5);
regmap_write(rt715->regmap, addr_h,
(val_h << 8) | val_ll);
/* Rch */
val_h = (1 << mc->shift) | (1 << 4);
regmap_write(rt715->regmap, addr_l,
(val_h << 8) | val_lr);
}
/* check result */
if (mc->shift == RT715_DIR_OUT_SFT) /* output */
val_h = 0x80;
else /* input */
val_h = 0x0;
rt715_get_gain(rt715, addr_h, addr_l, val_h,
&read_rl, &read_ll);
if (read_rl == val_lr && read_ll == val_ll)
break;
}
/* D0:power on state, D3: power saving mode */
if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
regmap_write(rt715->regmap,
RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D3);
return k_vol_changed;
}
static int rt715_set_amp_gain_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
unsigned int addr_h, addr_l, val_h;
unsigned int read_ll, read_rl;
addr_h = mc->reg;
addr_l = mc->rreg;
if (mc->shift == RT715_DIR_OUT_SFT) /* output */
val_h = 0x80;
else /* input */
val_h = 0x0;
rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll);
if (mc->invert) {
/* for mute status */
read_ll = !(read_ll & 0x80);
read_rl = !(read_rl & 0x80);
} else {
/* for gain */
read_ll = read_ll & 0x7f;
read_rl = read_rl & 0x7f;
}
ucontrol->value.integer.value[0] = read_ll;
ucontrol->value.integer.value[1] = read_rl;
return 0;
}
static int rt715_set_main_switch_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct snd_soc_dapm_context *dapm =
snd_soc_component_get_dapm(component);
struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
static const unsigned int capture_reg_H[] = {
RT715_SET_GAIN_MIC_ADC_H, RT715_SET_GAIN_LINE_ADC_H,
RT715_SET_GAIN_MIX_ADC_H, RT715_SET_GAIN_MIX_ADC2_H };
static const unsigned int capture_reg_L[] = {
RT715_SET_GAIN_MIC_ADC_L, RT715_SET_GAIN_LINE_ADC_L,
RT715_SET_GAIN_MIX_ADC_L, RT715_SET_GAIN_MIX_ADC2_L };
unsigned int addr_h, addr_l, val_h = 0x0, val_ll, val_lr;
unsigned int k_shift = RT715_DIR_IN_SFT, k_changed = 0;
unsigned int read_ll, read_rl, i, j, loop_cnt = 4;
for (i = 0; i < 8; i++) {
if (ucontrol->value.integer.value[i] != rt715->kctl_8ch_switch_ori[i])
k_changed = 1;
}
for (j = 0; j < loop_cnt; j++) {
/* Can't use update bit function, so read the original value first */
addr_h = capture_reg_H[j];
addr_l = capture_reg_L[j];
rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll);
if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
regmap_write(rt715->regmap,
RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D0);
/* L Channel */
/* for mute */
rt715->kctl_8ch_switch_ori[j * 2] =
ucontrol->value.integer.value[j * 2];
val_ll = (!ucontrol->value.integer.value[j * 2]) << 7;
/* keep gain */
val_ll |= read_ll & 0x7f;
/* R Channel */
/* for mute */
rt715->kctl_8ch_switch_ori[j * 2 + 1] =
ucontrol->value.integer.value[j * 2 + 1];
val_lr = (!ucontrol->value.integer.value[j * 2 + 1]) << 7;
/* keep gain */
val_lr |= read_rl & 0x7f;
for (i = 0; i < 3; i++) { /* retry 3 times at most */
if (val_ll == val_lr) {
/* Set both L/R channels at the same time */
val_h = (1 << k_shift) | (3 << 4);
regmap_write(rt715->regmap, addr_h,
(val_h << 8) | val_ll);
regmap_write(rt715->regmap, addr_l,
(val_h << 8) | val_ll);
} else {
/* Lch*/
val_h = (1 << k_shift) | (1 << 5);
regmap_write(rt715->regmap, addr_h,
(val_h << 8) | val_ll);
/* Rch */
val_h = (1 << k_shift) | (1 << 4);
regmap_write(rt715->regmap, addr_l,
(val_h << 8) | val_lr);
}
val_h = 0x0;
rt715_get_gain(rt715, addr_h, addr_l, val_h,
&read_rl, &read_ll);
if (read_rl == val_lr && read_ll == val_ll)
break;
}
}
/* D0:power on state, D3: power saving mode */
if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
regmap_write(rt715->regmap,
RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D3);
return k_changed;
}
static int rt715_set_main_switch_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
static const unsigned int capture_reg_H[] = {
RT715_SET_GAIN_MIC_ADC_H, RT715_SET_GAIN_LINE_ADC_H,
RT715_SET_GAIN_MIX_ADC_H, RT715_SET_GAIN_MIX_ADC2_H };
static const unsigned int capture_reg_L[] = {
RT715_SET_GAIN_MIC_ADC_L, RT715_SET_GAIN_LINE_ADC_L,
RT715_SET_GAIN_MIX_ADC_L, RT715_SET_GAIN_MIX_ADC2_L };
unsigned int addr_h, addr_l, val_h = 0x0, i, loop_cnt = 4;
unsigned int read_ll, read_rl;
for (i = 0; i < loop_cnt; i++) {
addr_h = capture_reg_H[i];
addr_l = capture_reg_L[i];
rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll);
ucontrol->value.integer.value[i * 2] = !(read_ll & 0x80);
ucontrol->value.integer.value[i * 2 + 1] = !(read_rl & 0x80);
}
return 0;
}
static int rt715_set_main_vol_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct snd_soc_dapm_context *dapm =
snd_soc_component_get_dapm(component);
struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
static const unsigned int capture_reg_H[] = {
RT715_SET_GAIN_MIC_ADC_H, RT715_SET_GAIN_LINE_ADC_H,
RT715_SET_GAIN_MIX_ADC_H, RT715_SET_GAIN_MIX_ADC2_H };
static const unsigned int capture_reg_L[] = {
RT715_SET_GAIN_MIC_ADC_L, RT715_SET_GAIN_LINE_ADC_L,
RT715_SET_GAIN_MIX_ADC_L, RT715_SET_GAIN_MIX_ADC2_L};
unsigned int addr_h, addr_l, val_h = 0x0, val_ll, val_lr;
unsigned int read_ll, read_rl, i, j, loop_cnt = 4, k_changed = 0;
unsigned int k_shift = RT715_DIR_IN_SFT, k_max = 0x3f;
for (i = 0; i < 8; i++) {
if (ucontrol->value.integer.value[i] != rt715->kctl_8ch_vol_ori[i])
k_changed = 1;
}
for (j = 0; j < loop_cnt; j++) {
addr_h = capture_reg_H[j];
addr_l = capture_reg_L[j];
rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll);
if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
regmap_write(rt715->regmap,
RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D0);
/* L Channel */
/* for gain */
rt715->kctl_8ch_vol_ori[j * 2] = ucontrol->value.integer.value[j * 2];
val_ll = ((ucontrol->value.integer.value[j * 2]) & 0x7f);
if (val_ll > k_max)
val_ll = k_max;
/* keep mute status */
val_ll |= read_ll & 0x80;
/* R Channel */
/* for gain */
rt715->kctl_8ch_vol_ori[j * 2 + 1] =
ucontrol->value.integer.value[j * 2 + 1];
val_lr = ((ucontrol->value.integer.value[j * 2 + 1]) & 0x7f);
if (val_lr > k_max)
val_lr = k_max;
/* keep mute status */
val_lr |= read_rl & 0x80;
for (i = 0; i < 3; i++) { /* retry 3 times at most */
if (val_ll == val_lr) {
/* Set both L/R channels at the same time */
val_h = (1 << k_shift) | (3 << 4);
regmap_write(rt715->regmap, addr_h,
(val_h << 8) | val_ll);
regmap_write(rt715->regmap, addr_l,
(val_h << 8) | val_ll);
} else {
/* Lch*/
val_h = (1 << k_shift) | (1 << 5);
regmap_write(rt715->regmap, addr_h,
(val_h << 8) | val_ll);
/* Rch */
val_h = (1 << k_shift) | (1 << 4);
regmap_write(rt715->regmap, addr_l,
(val_h << 8) | val_lr);
}
val_h = 0x0;
rt715_get_gain(rt715, addr_h, addr_l, val_h,
&read_rl, &read_ll);
if (read_rl == val_lr && read_ll == val_ll)
break;
}
}
/* D0:power on state, D3: power saving mode */
if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
regmap_write(rt715->regmap,
RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D3);
return k_changed;
}
static int rt715_set_main_vol_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
static const unsigned int capture_reg_H[] = {
RT715_SET_GAIN_MIC_ADC_H, RT715_SET_GAIN_LINE_ADC_H,
RT715_SET_GAIN_MIX_ADC_H, RT715_SET_GAIN_MIX_ADC2_H };
static const unsigned int capture_reg_L[] = {
RT715_SET_GAIN_MIC_ADC_L, RT715_SET_GAIN_LINE_ADC_L,
RT715_SET_GAIN_MIX_ADC_L, RT715_SET_GAIN_MIX_ADC2_L };
unsigned int addr_h, addr_l, val_h = 0x0, i, loop_cnt = 4;
unsigned int read_ll, read_rl;
for (i = 0; i < loop_cnt; i++) {
addr_h = capture_reg_H[i];
addr_l = capture_reg_L[i];
rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll);
ucontrol->value.integer.value[i * 2] = read_ll & 0x7f;
ucontrol->value.integer.value[i * 2 + 1] = read_rl & 0x7f;
}
return 0;
}
static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -1725, 75, 0);
static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
static int rt715_switch_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
uinfo->count = 8;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = 1;
return 0;
}
static int rt715_vol_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = 8;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = 0x3f;
return 0;
}
#define SOC_DOUBLE_R_EXT(xname, reg_left, reg_right, xshift, xmax, xinvert,\
xhandler_get, xhandler_put) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
.info = snd_soc_info_volsw, \
.get = xhandler_get, .put = xhandler_put, \
.private_value = SOC_DOUBLE_R_VALUE(reg_left, reg_right, xshift, \
xmax, xinvert) }
#define RT715_MAIN_SWITCH_EXT(xname, xhandler_get, xhandler_put) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
.info = rt715_switch_info, \
.get = xhandler_get, .put = xhandler_put, \
}
#define RT715_MAIN_VOL_EXT_TLV(xname, xhandler_get, xhandler_put, tlv_array) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
SNDRV_CTL_ELEM_ACCESS_READWRITE, \
.tlv.p = (tlv_array), \
.info = rt715_vol_info, \
.get = xhandler_get, .put = xhandler_put, \
}
static const struct snd_kcontrol_new rt715_snd_controls[] = {
/* Capture switch */
RT715_MAIN_SWITCH_EXT("Capture Switch",
rt715_set_main_switch_get, rt715_set_main_switch_put),
/* Volume Control */
RT715_MAIN_VOL_EXT_TLV("Capture Volume",
rt715_set_main_vol_get, rt715_set_main_vol_put, in_vol_tlv),
/* MIC Boost Control */
SOC_DOUBLE_R_EXT_TLV("DMIC1 Boost", RT715_SET_GAIN_DMIC1_H,
RT715_SET_GAIN_DMIC1_L, RT715_DIR_IN_SFT, 3, 0,
rt715_set_amp_gain_get, rt715_set_amp_gain_put,
mic_vol_tlv),
SOC_DOUBLE_R_EXT_TLV("DMIC2 Boost", RT715_SET_GAIN_DMIC2_H,
RT715_SET_GAIN_DMIC2_L, RT715_DIR_IN_SFT, 3, 0,
rt715_set_amp_gain_get, rt715_set_amp_gain_put,
mic_vol_tlv),
SOC_DOUBLE_R_EXT_TLV("DMIC3 Boost", RT715_SET_GAIN_DMIC3_H,
RT715_SET_GAIN_DMIC3_L, RT715_DIR_IN_SFT, 3, 0,
rt715_set_amp_gain_get, rt715_set_amp_gain_put,
mic_vol_tlv),
SOC_DOUBLE_R_EXT_TLV("DMIC4 Boost", RT715_SET_GAIN_DMIC4_H,
RT715_SET_GAIN_DMIC4_L, RT715_DIR_IN_SFT, 3, 0,
rt715_set_amp_gain_get, rt715_set_amp_gain_put,
mic_vol_tlv),
SOC_DOUBLE_R_EXT_TLV("MIC1 Boost", RT715_SET_GAIN_MIC1_H,
RT715_SET_GAIN_MIC1_L, RT715_DIR_IN_SFT, 3, 0,
rt715_set_amp_gain_get, rt715_set_amp_gain_put,
mic_vol_tlv),
SOC_DOUBLE_R_EXT_TLV("MIC2 Boost", RT715_SET_GAIN_MIC2_H,
RT715_SET_GAIN_MIC2_L, RT715_DIR_IN_SFT, 3, 0,
rt715_set_amp_gain_get, rt715_set_amp_gain_put,
mic_vol_tlv),
SOC_DOUBLE_R_EXT_TLV("LINE1 Boost", RT715_SET_GAIN_LINE1_H,
RT715_SET_GAIN_LINE1_L, RT715_DIR_IN_SFT, 3, 0,
rt715_set_amp_gain_get, rt715_set_amp_gain_put,
mic_vol_tlv),
SOC_DOUBLE_R_EXT_TLV("LINE2 Boost", RT715_SET_GAIN_LINE2_H,
RT715_SET_GAIN_LINE2_L, RT715_DIR_IN_SFT, 3, 0,
rt715_set_amp_gain_get, rt715_set_amp_gain_put,
mic_vol_tlv),
};
static int rt715_mux_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_dapm_kcontrol_component(kcontrol);
struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int reg, val;
int ret;
/* nid = e->reg, vid = 0xf01 */
reg = RT715_VERB_SET_CONNECT_SEL | e->reg;
ret = regmap_read(rt715->regmap, reg, &val);
if (ret < 0) {
dev_err(component->dev, "%s: sdw read failed: %d\n",
__func__, ret);
return ret;
}
/*
* The first two indices of ADC Mux 24/25 are routed to the same
* hardware source. ie, ADC Mux 24 0/1 will both connect to MIC2.
* To have a unique set of inputs, we skip the index1 of the muxes.
*/
if ((e->reg == RT715_MUX_IN3 || e->reg == RT715_MUX_IN4) && (val > 0))
val -= 1;
ucontrol->value.enumerated.item[0] = val;
return 0;
}
static int rt715_mux_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_dapm_kcontrol_component(kcontrol);
struct snd_soc_dapm_context *dapm =
snd_soc_dapm_kcontrol_dapm(kcontrol);
struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int *item = ucontrol->value.enumerated.item;
unsigned int val, val2 = 0, change, reg;
int ret;
if (item[0] >= e->items)
return -EINVAL;
/* Verb ID = 0x701h, nid = e->reg */
val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
reg = RT715_VERB_SET_CONNECT_SEL | e->reg;
ret = regmap_read(rt715->regmap, reg, &val2);
if (ret < 0) {
dev_err(component->dev, "%s: sdw read failed: %d\n",
__func__, ret);
return ret;
}
if (val == val2)
change = 0;
else
change = 1;
if (change) {
reg = RT715_VERB_SET_CONNECT_SEL | e->reg;
regmap_write(rt715->regmap, reg, val);
}
snd_soc_dapm_mux_update_power(dapm, kcontrol,
item[0], e, NULL);
return change;
}
static const char * const adc_22_23_mux_text[] = {
"MIC1",
"MIC2",
"LINE1",
"LINE2",
"DMIC1",
"DMIC2",
"DMIC3",
"DMIC4",
};
/*
* Due to mux design for nid 24 (MUX_IN3)/25 (MUX_IN4), connection index 0 and
* 1 will be connected to the same dmic source, therefore we skip index 1 to
* avoid misunderstanding on usage of dapm routing.
*/
static const unsigned int rt715_adc_24_25_values[] = {
0,
2,
3,
4,
5,
};
static const char * const adc_24_mux_text[] = {
"MIC2",
"DMIC1",
"DMIC2",
"DMIC3",
"DMIC4",
};
static const char * const adc_25_mux_text[] = {
"MIC1",
"DMIC1",
"DMIC2",
"DMIC3",
"DMIC4",
};
static SOC_ENUM_SINGLE_DECL(
rt715_adc22_enum, RT715_MUX_IN1, 0, adc_22_23_mux_text);
static SOC_ENUM_SINGLE_DECL(
rt715_adc23_enum, RT715_MUX_IN2, 0, adc_22_23_mux_text);
static SOC_VALUE_ENUM_SINGLE_DECL(rt715_adc24_enum,
RT715_MUX_IN3, 0, 0xf,
adc_24_mux_text, rt715_adc_24_25_values);
static SOC_VALUE_ENUM_SINGLE_DECL(rt715_adc25_enum,
RT715_MUX_IN4, 0, 0xf,
adc_25_mux_text, rt715_adc_24_25_values);
static const struct snd_kcontrol_new rt715_adc22_mux =
SOC_DAPM_ENUM_EXT("ADC 22 Mux", rt715_adc22_enum,
rt715_mux_get, rt715_mux_put);
static const struct snd_kcontrol_new rt715_adc23_mux =
SOC_DAPM_ENUM_EXT("ADC 23 Mux", rt715_adc23_enum,
rt715_mux_get, rt715_mux_put);
static const struct snd_kcontrol_new rt715_adc24_mux =
SOC_DAPM_ENUM_EXT("ADC 24 Mux", rt715_adc24_enum,
rt715_mux_get, rt715_mux_put);
static const struct snd_kcontrol_new rt715_adc25_mux =
SOC_DAPM_ENUM_EXT("ADC 25 Mux", rt715_adc25_enum,
rt715_mux_get, rt715_mux_put);
static const struct snd_soc_dapm_widget rt715_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("DMIC1"),
SND_SOC_DAPM_INPUT("DMIC2"),
SND_SOC_DAPM_INPUT("DMIC3"),
SND_SOC_DAPM_INPUT("DMIC4"),
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_INPUT("MIC2"),
SND_SOC_DAPM_INPUT("LINE1"),
SND_SOC_DAPM_INPUT("LINE2"),
SND_SOC_DAPM_ADC("ADC 07", NULL, RT715_SET_STREAMID_MIC_ADC, 4, 0),
SND_SOC_DAPM_ADC("ADC 08", NULL, RT715_SET_STREAMID_LINE_ADC, 4, 0),
SND_SOC_DAPM_ADC("ADC 09", NULL, RT715_SET_STREAMID_MIX_ADC, 4, 0),
SND_SOC_DAPM_ADC("ADC 27", NULL, RT715_SET_STREAMID_MIX_ADC2, 4, 0),
SND_SOC_DAPM_MUX("ADC 22 Mux", SND_SOC_NOPM, 0, 0,
&rt715_adc22_mux),
SND_SOC_DAPM_MUX("ADC 23 Mux", SND_SOC_NOPM, 0, 0,
&rt715_adc23_mux),
SND_SOC_DAPM_MUX("ADC 24 Mux", SND_SOC_NOPM, 0, 0,
&rt715_adc24_mux),
SND_SOC_DAPM_MUX("ADC 25 Mux", SND_SOC_NOPM, 0, 0,
&rt715_adc25_mux),
SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("DP6TX", "DP6 Capture", 0, SND_SOC_NOPM, 0, 0),
};
static const struct snd_soc_dapm_route rt715_audio_map[] = {
{"DP6TX", NULL, "ADC 09"},
{"DP6TX", NULL, "ADC 08"},
{"DP4TX", NULL, "ADC 07"},
{"DP4TX", NULL, "ADC 27"},
{"ADC 09", NULL, "ADC 22 Mux"},
{"ADC 08", NULL, "ADC 23 Mux"},
{"ADC 07", NULL, "ADC 24 Mux"},
{"ADC 27", NULL, "ADC 25 Mux"},
{"ADC 22 Mux", "MIC1", "MIC1"},
{"ADC 22 Mux", "MIC2", "MIC2"},
{"ADC 22 Mux", "LINE1", "LINE1"},
{"ADC 22 Mux", "LINE2", "LINE2"},
{"ADC 22 Mux", "DMIC1", "DMIC1"},
{"ADC 22 Mux", "DMIC2", "DMIC2"},
{"ADC 22 Mux", "DMIC3", "DMIC3"},
{"ADC 22 Mux", "DMIC4", "DMIC4"},
{"ADC 23 Mux", "MIC1", "MIC1"},
{"ADC 23 Mux", "MIC2", "MIC2"},
{"ADC 23 Mux", "LINE1", "LINE1"},
{"ADC 23 Mux", "LINE2", "LINE2"},
{"ADC 23 Mux", "DMIC1", "DMIC1"},
{"ADC 23 Mux", "DMIC2", "DMIC2"},
{"ADC 23 Mux", "DMIC3", "DMIC3"},
{"ADC 23 Mux", "DMIC4", "DMIC4"},
{"ADC 24 Mux", "MIC2", "MIC2"},
{"ADC 24 Mux", "DMIC1", "DMIC1"},
{"ADC 24 Mux", "DMIC2", "DMIC2"},
{"ADC 24 Mux", "DMIC3", "DMIC3"},
{"ADC 24 Mux", "DMIC4", "DMIC4"},
{"ADC 25 Mux", "MIC1", "MIC1"},
{"ADC 25 Mux", "DMIC1", "DMIC1"},
{"ADC 25 Mux", "DMIC2", "DMIC2"},
{"ADC 25 Mux", "DMIC3", "DMIC3"},
{"ADC 25 Mux", "DMIC4", "DMIC4"},
};
static int rt715_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct snd_soc_dapm_context *dapm =
snd_soc_component_get_dapm(component);
struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_PREPARE:
if (dapm->bias_level == SND_SOC_BIAS_STANDBY) {
regmap_write(rt715->regmap,
RT715_SET_AUDIO_POWER_STATE,
AC_PWRST_D0);
msleep(RT715_POWER_UP_DELAY_MS);
}
break;
case SND_SOC_BIAS_STANDBY:
regmap_write(rt715->regmap,
RT715_SET_AUDIO_POWER_STATE,
AC_PWRST_D3);
break;
default:
break;
}
dapm->bias_level = level;
return 0;
}
static int rt715_probe(struct snd_soc_component *component)
{
struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
int ret;
if (!rt715->first_hw_init)
return 0;
ret = pm_runtime_resume(component->dev);
if (ret < 0 && ret != -EACCES)
return ret;
return 0;
}
static const struct snd_soc_component_driver soc_codec_dev_rt715 = {
.probe = rt715_probe,
.set_bias_level = rt715_set_bias_level,
.controls = rt715_snd_controls,
.num_controls = ARRAY_SIZE(rt715_snd_controls),
.dapm_widgets = rt715_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt715_dapm_widgets),
.dapm_routes = rt715_audio_map,
.num_dapm_routes = ARRAY_SIZE(rt715_audio_map),
.endianness = 1,
};
static int rt715_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
int direction)
{
snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
return 0;
}
static void rt715_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
snd_soc_dai_set_dma_data(dai, substream, NULL);
}
static int rt715_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
struct sdw_stream_config stream_config = {0};
struct sdw_port_config port_config = {0};
struct sdw_stream_runtime *sdw_stream;
int retval;
unsigned int val = 0;
sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
if (!sdw_stream)
return -EINVAL;
if (!rt715->slave)
return -EINVAL;
snd_sdw_params_to_config(substream, params, &stream_config, &port_config);
switch (dai->id) {
case RT715_AIF1:
port_config.num = 6;
rt715_index_write(rt715->regmap, RT715_SDW_INPUT_SEL, 0xa500);
break;
case RT715_AIF2:
port_config.num = 4;
rt715_index_write(rt715->regmap, RT715_SDW_INPUT_SEL, 0xa000);
break;
default:
dev_err(component->dev, "Invalid DAI id %d\n", dai->id);
return -EINVAL;
}
retval = sdw_stream_add_slave(rt715->slave, &stream_config,
&port_config, 1, sdw_stream);
if (retval) {
dev_err(dai->dev, "Unable to configure port\n");
return retval;
}
switch (params_rate(params)) {
/* bit 14 0:48K 1:44.1K */
/* bit 15 Stream Type 0:PCM 1:Non-PCM, should always be PCM */
case 44100:
val |= 0x40 << 8;
break;
case 48000:
val |= 0x0 << 8;
break;
default:
dev_err(component->dev, "Unsupported sample rate %d\n",
params_rate(params));
return -EINVAL;
}
if (params_channels(params) <= 16) {
/* bit 3:0 Number of Channel */
val |= (params_channels(params) - 1);
} else {
dev_err(component->dev, "Unsupported channels %d\n",
params_channels(params));
return -EINVAL;
}
switch (params_width(params)) {
/* bit 6:4 Bits per Sample */
case 8:
break;
case 16:
val |= (0x1 << 4);
break;
case 20:
val |= (0x2 << 4);
break;
case 24:
val |= (0x3 << 4);
break;
case 32:
val |= (0x4 << 4);
break;
default:
return -EINVAL;
}
regmap_write(rt715->regmap, RT715_MIC_ADC_FORMAT_H, val);
regmap_write(rt715->regmap, RT715_MIC_LINE_FORMAT_H, val);
regmap_write(rt715->regmap, RT715_MIX_ADC_FORMAT_H, val);
regmap_write(rt715->regmap, RT715_MIX_ADC2_FORMAT_H, val);
return retval;
}
static int rt715_pcm_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
struct sdw_stream_runtime *sdw_stream =
snd_soc_dai_get_dma_data(dai, substream);
if (!rt715->slave)
return -EINVAL;
sdw_stream_remove_slave(rt715->slave, sdw_stream);
return 0;
}
#define RT715_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
#define RT715_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
static const struct snd_soc_dai_ops rt715_ops = {
.hw_params = rt715_pcm_hw_params,
.hw_free = rt715_pcm_hw_free,
.set_stream = rt715_set_sdw_stream,
.shutdown = rt715_shutdown,
};
static struct snd_soc_dai_driver rt715_dai[] = {
{
.name = "rt715-aif1",
.id = RT715_AIF1,
.capture = {
.stream_name = "DP6 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT715_STEREO_RATES,
.formats = RT715_FORMATS,
},
.ops = &rt715_ops,
},
{
.name = "rt715-aif2",
.id = RT715_AIF2,
.capture = {
.stream_name = "DP4 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT715_STEREO_RATES,
.formats = RT715_FORMATS,
},
.ops = &rt715_ops,
},
};
/* Bus clock frequency */
#define RT715_CLK_FREQ_9600000HZ 9600000
#define RT715_CLK_FREQ_12000000HZ 12000000
#define RT715_CLK_FREQ_6000000HZ 6000000
#define RT715_CLK_FREQ_4800000HZ 4800000
#define RT715_CLK_FREQ_2400000HZ 2400000
#define RT715_CLK_FREQ_12288000HZ 12288000
int rt715_clock_config(struct device *dev)
{
struct rt715_priv *rt715 = dev_get_drvdata(dev);
unsigned int clk_freq, value;
clk_freq = (rt715->params.curr_dr_freq >> 1);
switch (clk_freq) {
case RT715_CLK_FREQ_12000000HZ:
value = 0x0;
break;
case RT715_CLK_FREQ_6000000HZ:
value = 0x1;
break;
case RT715_CLK_FREQ_9600000HZ:
value = 0x2;
break;
case RT715_CLK_FREQ_4800000HZ:
value = 0x3;
break;
case RT715_CLK_FREQ_2400000HZ:
value = 0x4;
break;
case RT715_CLK_FREQ_12288000HZ:
value = 0x5;
break;
default:
return -EINVAL;
}
regmap_write(rt715->regmap, 0xe0, value);
regmap_write(rt715->regmap, 0xf0, value);
return 0;
}
int rt715_init(struct device *dev, struct regmap *sdw_regmap,
struct regmap *regmap, struct sdw_slave *slave)
{
struct rt715_priv *rt715;
int ret;
rt715 = devm_kzalloc(dev, sizeof(*rt715), GFP_KERNEL);
if (!rt715)
return -ENOMEM;
dev_set_drvdata(dev, rt715);
rt715->slave = slave;
rt715->regmap = regmap;
rt715->sdw_regmap = sdw_regmap;
regcache_cache_only(rt715->regmap, true);
/*
* Mark hw_init to false
* HW init will be performed when device reports present
*/
rt715->hw_init = false;
rt715->first_hw_init = false;
ret = devm_snd_soc_register_component(dev,
&soc_codec_dev_rt715,
rt715_dai,
ARRAY_SIZE(rt715_dai));
if (ret < 0)
return ret;
/* set autosuspend parameters */
pm_runtime_set_autosuspend_delay(dev, 3000);
pm_runtime_use_autosuspend(dev);
/* make sure the device does not suspend immediately */
pm_runtime_mark_last_busy(dev);
pm_runtime_enable(dev);
/* important note: the device is NOT tagged as 'active' and will remain
* 'suspended' until the hardware is enumerated/initialized. This is required
* to make sure the ASoC framework use of pm_runtime_get_sync() does not silently
* fail with -EACCESS because of race conditions between card creation and enumeration
*/
return 0;
}
int rt715_io_init(struct device *dev, struct sdw_slave *slave)
{
struct rt715_priv *rt715 = dev_get_drvdata(dev);
if (rt715->hw_init)
return 0;
regcache_cache_only(rt715->regmap, false);
/*
* PM runtime status is marked as 'active' only when a Slave reports as Attached
*/
if (!rt715->first_hw_init)
/* update count of parent 'active' children */
pm_runtime_set_active(&slave->dev);
pm_runtime_get_noresume(&slave->dev);
rt715_reset(rt715->regmap);
/* Mute nid=08h/09h */
regmap_write(rt715->regmap, RT715_SET_GAIN_LINE_ADC_H, 0xb080);
regmap_write(rt715->regmap, RT715_SET_GAIN_MIX_ADC_H, 0xb080);
/* Mute nid=07h/27h */
regmap_write(rt715->regmap, RT715_SET_GAIN_MIC_ADC_H, 0xb080);
regmap_write(rt715->regmap, RT715_SET_GAIN_MIX_ADC2_H, 0xb080);
/* Set Pin Widget */
regmap_write(rt715->regmap, RT715_SET_PIN_DMIC1, 0x20);
regmap_write(rt715->regmap, RT715_SET_PIN_DMIC2, 0x20);
regmap_write(rt715->regmap, RT715_SET_PIN_DMIC3, 0x20);
regmap_write(rt715->regmap, RT715_SET_PIN_DMIC4, 0x20);
/* Set Converter Stream */
regmap_write(rt715->regmap, RT715_SET_STREAMID_LINE_ADC, 0x10);
regmap_write(rt715->regmap, RT715_SET_STREAMID_MIX_ADC, 0x10);
regmap_write(rt715->regmap, RT715_SET_STREAMID_MIC_ADC, 0x10);
regmap_write(rt715->regmap, RT715_SET_STREAMID_MIX_ADC2, 0x10);
/* Set Configuration Default */
regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT1, 0xd0);
regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT2, 0x11);
regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT3, 0xa1);
regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT4, 0x81);
regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT1, 0xd1);
regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT2, 0x11);
regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT3, 0xa1);
regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT4, 0x81);
regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT1, 0xd0);
regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT2, 0x11);
regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT3, 0xa1);
regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT4, 0x81);
regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT1, 0xd1);
regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT2, 0x11);
regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT3, 0xa1);
regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT4, 0x81);
/* Finish Initial Settings, set power to D3 */
regmap_write(rt715->regmap, RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D3);
if (rt715->first_hw_init)
regcache_mark_dirty(rt715->regmap);
else
rt715->first_hw_init = true;
/* Mark Slave initialization complete */
rt715->hw_init = true;
pm_runtime_mark_last_busy(&slave->dev);
pm_runtime_put_autosuspend(&slave->dev);
return 0;
}
MODULE_DESCRIPTION("ASoC rt715 driver");
MODULE_DESCRIPTION("ASoC rt715 driver SDW");
MODULE_AUTHOR("Jack Yu <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/rt715.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Components shared between ASoC and HDA CS35L56 drivers
//
// Copyright (C) 2023 Cirrus Logic, Inc. and
// Cirrus Logic International Semiconductor Ltd.
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/types.h>
#include "cs35l56.h"
static const struct reg_sequence cs35l56_patch[] = {
/* These are not reset by a soft-reset, so patch to defaults. */
{ CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 },
{ CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 },
{ CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 },
};
int cs35l56_set_patch(struct cs35l56_base *cs35l56_base)
{
return regmap_register_patch(cs35l56_base->regmap, cs35l56_patch,
ARRAY_SIZE(cs35l56_patch));
}
EXPORT_SYMBOL_NS_GPL(cs35l56_set_patch, SND_SOC_CS35L56_SHARED);
static const struct reg_default cs35l56_reg_defaults[] = {
{ CS35L56_ASP1_ENABLES1, 0x00000000 },
{ CS35L56_ASP1_CONTROL1, 0x00000028 },
{ CS35L56_ASP1_CONTROL2, 0x18180200 },
{ CS35L56_ASP1_CONTROL3, 0x00000002 },
{ CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 },
{ CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 },
{ CS35L56_ASP1_DATA_CONTROL1, 0x00000018 },
{ CS35L56_ASP1_DATA_CONTROL5, 0x00000018 },
{ CS35L56_ASP1TX1_INPUT, 0x00000018 },
{ CS35L56_ASP1TX2_INPUT, 0x00000019 },
{ CS35L56_ASP1TX3_INPUT, 0x00000020 },
{ CS35L56_ASP1TX4_INPUT, 0x00000028 },
{ CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 },
{ CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 },
{ CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 },
{ CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 },
{ CS35L56_IRQ1_CFG, 0x00000000 },
{ CS35L56_IRQ1_MASK_1, 0x83ffffff },
{ CS35L56_IRQ1_MASK_2, 0xffff7fff },
{ CS35L56_IRQ1_MASK_4, 0xe0ffffff },
{ CS35L56_IRQ1_MASK_8, 0xfc000fff },
{ CS35L56_IRQ1_MASK_18, 0x1f7df0ff },
{ CS35L56_IRQ1_MASK_20, 0x15c00000 },
{ CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 },
{ CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 },
{ CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 },
};
static bool cs35l56_is_dsp_memory(unsigned int reg)
{
switch (reg) {
case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143:
case CS35L56_DSP1_XMEM_UNPACKED32_0 ... CS35L56_DSP1_XMEM_UNPACKED32_4095:
case CS35L56_DSP1_XMEM_UNPACKED24_0 ... CS35L56_DSP1_XMEM_UNPACKED24_8191:
case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604:
case CS35L56_DSP1_YMEM_UNPACKED32_0 ... CS35L56_DSP1_YMEM_UNPACKED32_3070:
case CS35L56_DSP1_YMEM_UNPACKED24_0 ... CS35L56_DSP1_YMEM_UNPACKED24_6141:
case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114:
return true;
default:
return false;
}
}
static bool cs35l56_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS35L56_DEVID:
case CS35L56_REVID:
case CS35L56_RELID:
case CS35L56_OTPID:
case CS35L56_SFT_RESET:
case CS35L56_GLOBAL_ENABLES:
case CS35L56_BLOCK_ENABLES:
case CS35L56_BLOCK_ENABLES2:
case CS35L56_REFCLK_INPUT:
case CS35L56_GLOBAL_SAMPLE_RATE:
case CS35L56_ASP1_ENABLES1:
case CS35L56_ASP1_CONTROL1:
case CS35L56_ASP1_CONTROL2:
case CS35L56_ASP1_CONTROL3:
case CS35L56_ASP1_FRAME_CONTROL1:
case CS35L56_ASP1_FRAME_CONTROL5:
case CS35L56_ASP1_DATA_CONTROL1:
case CS35L56_ASP1_DATA_CONTROL5:
case CS35L56_DACPCM1_INPUT:
case CS35L56_DACPCM2_INPUT:
case CS35L56_ASP1TX1_INPUT:
case CS35L56_ASP1TX2_INPUT:
case CS35L56_ASP1TX3_INPUT:
case CS35L56_ASP1TX4_INPUT:
case CS35L56_DSP1RX1_INPUT:
case CS35L56_DSP1RX2_INPUT:
case CS35L56_SWIRE_DP3_CH1_INPUT:
case CS35L56_SWIRE_DP3_CH2_INPUT:
case CS35L56_SWIRE_DP3_CH3_INPUT:
case CS35L56_SWIRE_DP3_CH4_INPUT:
case CS35L56_IRQ1_CFG:
case CS35L56_IRQ1_STATUS:
case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8:
case CS35L56_IRQ1_EINT_18:
case CS35L56_IRQ1_EINT_20:
case CS35L56_IRQ1_MASK_1:
case CS35L56_IRQ1_MASK_2:
case CS35L56_IRQ1_MASK_4:
case CS35L56_IRQ1_MASK_8:
case CS35L56_IRQ1_MASK_18:
case CS35L56_IRQ1_MASK_20:
case CS35L56_DSP_VIRTUAL1_MBOX_1:
case CS35L56_DSP_VIRTUAL1_MBOX_2:
case CS35L56_DSP_VIRTUAL1_MBOX_3:
case CS35L56_DSP_VIRTUAL1_MBOX_4:
case CS35L56_DSP_VIRTUAL1_MBOX_5:
case CS35L56_DSP_VIRTUAL1_MBOX_6:
case CS35L56_DSP_VIRTUAL1_MBOX_7:
case CS35L56_DSP_VIRTUAL1_MBOX_8:
case CS35L56_DSP_RESTRICT_STS1:
case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END:
case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0:
case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1:
case CS35L56_DSP1_SCRATCH1:
case CS35L56_DSP1_SCRATCH2:
case CS35L56_DSP1_SCRATCH3:
case CS35L56_DSP1_SCRATCH4:
return true;
default:
return cs35l56_is_dsp_memory(reg);
}
}
static bool cs35l56_precious_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143:
case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604:
case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114:
return true;
default:
return false;
}
}
static bool cs35l56_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS35L56_DEVID:
case CS35L56_REVID:
case CS35L56_RELID:
case CS35L56_OTPID:
case CS35L56_SFT_RESET:
case CS35L56_GLOBAL_ENABLES: /* owned by firmware */
case CS35L56_BLOCK_ENABLES: /* owned by firmware */
case CS35L56_BLOCK_ENABLES2: /* owned by firmware */
case CS35L56_REFCLK_INPUT: /* owned by firmware */
case CS35L56_GLOBAL_SAMPLE_RATE: /* owned by firmware */
case CS35L56_DACPCM1_INPUT: /* owned by firmware */
case CS35L56_DACPCM2_INPUT: /* owned by firmware */
case CS35L56_DSP1RX1_INPUT: /* owned by firmware */
case CS35L56_DSP1RX2_INPUT: /* owned by firmware */
case CS35L56_IRQ1_STATUS:
case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8:
case CS35L56_IRQ1_EINT_18:
case CS35L56_IRQ1_EINT_20:
case CS35L56_DSP_VIRTUAL1_MBOX_1:
case CS35L56_DSP_VIRTUAL1_MBOX_2:
case CS35L56_DSP_VIRTUAL1_MBOX_3:
case CS35L56_DSP_VIRTUAL1_MBOX_4:
case CS35L56_DSP_VIRTUAL1_MBOX_5:
case CS35L56_DSP_VIRTUAL1_MBOX_6:
case CS35L56_DSP_VIRTUAL1_MBOX_7:
case CS35L56_DSP_VIRTUAL1_MBOX_8:
case CS35L56_DSP_RESTRICT_STS1:
case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END:
case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0:
case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1:
case CS35L56_DSP1_SCRATCH1:
case CS35L56_DSP1_SCRATCH2:
case CS35L56_DSP1_SCRATCH3:
case CS35L56_DSP1_SCRATCH4:
return true;
case CS35L56_MAIN_RENDER_USER_MUTE:
case CS35L56_MAIN_RENDER_USER_VOLUME:
case CS35L56_MAIN_POSTURE_NUMBER:
return false;
default:
return cs35l56_is_dsp_memory(reg);
}
}
int cs35l56_mbox_send(struct cs35l56_base *cs35l56_base, unsigned int command)
{
unsigned int val;
int ret;
regmap_write(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, command);
ret = regmap_read_poll_timeout(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1,
val, (val == 0),
CS35L56_MBOX_POLL_US, CS35L56_MBOX_TIMEOUT_US);
if (ret) {
dev_warn(cs35l56_base->dev, "MBOX command %#x failed: %d\n", command, ret);
return ret;
}
return 0;
}
EXPORT_SYMBOL_NS_GPL(cs35l56_mbox_send, SND_SOC_CS35L56_SHARED);
int cs35l56_firmware_shutdown(struct cs35l56_base *cs35l56_base)
{
int ret;
unsigned int reg;
unsigned int val;
ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_SHUTDOWN);
if (ret)
return ret;
if (cs35l56_base->rev < CS35L56_REVID_B0)
reg = CS35L56_DSP1_PM_CUR_STATE_A1;
else
reg = CS35L56_DSP1_PM_CUR_STATE;
ret = regmap_read_poll_timeout(cs35l56_base->regmap, reg,
val, (val == CS35L56_HALO_STATE_SHUTDOWN),
CS35L56_HALO_STATE_POLL_US,
CS35L56_HALO_STATE_TIMEOUT_US);
if (ret < 0)
dev_err(cs35l56_base->dev, "Failed to poll PM_CUR_STATE to 1 is %d (ret %d)\n",
val, ret);
return ret;
}
EXPORT_SYMBOL_NS_GPL(cs35l56_firmware_shutdown, SND_SOC_CS35L56_SHARED);
int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base)
{
unsigned int reg;
unsigned int val;
int read_ret, poll_ret;
if (cs35l56_base->rev < CS35L56_REVID_B0)
reg = CS35L56_DSP1_HALO_STATE_A1;
else
reg = CS35L56_DSP1_HALO_STATE;
/*
* This can't be a regmap_read_poll_timeout() because cs35l56 will NAK
* I2C until it has booted which would terminate the poll
*/
poll_ret = read_poll_timeout(regmap_read, read_ret,
(val < 0xFFFF) && (val >= CS35L56_HALO_STATE_BOOT_DONE),
CS35L56_HALO_STATE_POLL_US,
CS35L56_HALO_STATE_TIMEOUT_US,
false,
cs35l56_base->regmap, reg, &val);
if (poll_ret) {
dev_err(cs35l56_base->dev, "Firmware boot timed out(%d): HALO_STATE=%#x\n",
read_ret, val);
return -EIO;
}
return 0;
}
EXPORT_SYMBOL_NS_GPL(cs35l56_wait_for_firmware_boot, SND_SOC_CS35L56_SHARED);
void cs35l56_wait_control_port_ready(void)
{
/* Wait for control port to be ready (datasheet tIRS). */
usleep_range(CS35L56_CONTROL_PORT_READY_US, 2 * CS35L56_CONTROL_PORT_READY_US);
}
EXPORT_SYMBOL_NS_GPL(cs35l56_wait_control_port_ready, SND_SOC_CS35L56_SHARED);
void cs35l56_wait_min_reset_pulse(void)
{
/* Satisfy minimum reset pulse width spec */
usleep_range(CS35L56_RESET_PULSE_MIN_US, 2 * CS35L56_RESET_PULSE_MIN_US);
}
EXPORT_SYMBOL_NS_GPL(cs35l56_wait_min_reset_pulse, SND_SOC_CS35L56_SHARED);
static const struct reg_sequence cs35l56_system_reset_seq[] = {
REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET),
};
void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire)
{
/*
* Must enter cache-only first so there can't be any more register
* accesses other than the controlled system reset sequence below.
*/
regcache_cache_only(cs35l56_base->regmap, true);
regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
cs35l56_system_reset_seq,
ARRAY_SIZE(cs35l56_system_reset_seq));
/* On SoundWire the registers won't be accessible until it re-enumerates. */
if (is_soundwire)
return;
cs35l56_wait_control_port_ready();
regcache_cache_only(cs35l56_base->regmap, false);
}
EXPORT_SYMBOL_NS_GPL(cs35l56_system_reset, SND_SOC_CS35L56_SHARED);
int cs35l56_irq_request(struct cs35l56_base *cs35l56_base, int irq)
{
int ret;
if (!irq)
return 0;
ret = devm_request_threaded_irq(cs35l56_base->dev, irq, NULL, cs35l56_irq,
IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_LOW,
"cs35l56", cs35l56_base);
if (!ret)
cs35l56_base->irq = irq;
else
dev_err(cs35l56_base->dev, "Failed to get IRQ: %d\n", ret);
return ret;
}
EXPORT_SYMBOL_NS_GPL(cs35l56_irq_request, SND_SOC_CS35L56_SHARED);
irqreturn_t cs35l56_irq(int irq, void *data)
{
struct cs35l56_base *cs35l56_base = data;
unsigned int status1 = 0, status8 = 0, status20 = 0;
unsigned int mask1, mask8, mask20;
unsigned int val;
int rv;
irqreturn_t ret = IRQ_NONE;
if (!cs35l56_base->init_done)
return IRQ_NONE;
mutex_lock(&cs35l56_base->irq_lock);
rv = pm_runtime_resume_and_get(cs35l56_base->dev);
if (rv < 0) {
dev_err(cs35l56_base->dev, "irq: failed to get pm_runtime: %d\n", rv);
goto err_unlock;
}
regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val);
if ((val & CS35L56_IRQ1_STS_MASK) == 0) {
dev_dbg(cs35l56_base->dev, "Spurious IRQ: no pending interrupt\n");
goto err;
}
/* Ack interrupts */
regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, &status1);
regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, &mask1);
status1 &= ~mask1;
regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, status1);
regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, &status8);
regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, &mask8);
status8 &= ~mask8;
regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, status8);
regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_20, &status20);
regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, &mask20);
status20 &= ~mask20;
/* We don't want EINT20 but they default to unmasked: force mask */
regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff);
dev_dbg(cs35l56_base->dev, "%s: %#x %#x\n", __func__, status1, status8);
/* Check to see if unmasked bits are active */
if (!status1 && !status8 && !status20)
goto err;
if (status1 & CS35L56_AMP_SHORT_ERR_EINT1_MASK)
dev_crit(cs35l56_base->dev, "Amp short error\n");
if (status8 & CS35L56_TEMP_ERR_EINT1_MASK)
dev_crit(cs35l56_base->dev, "Overtemp error\n");
ret = IRQ_HANDLED;
err:
pm_runtime_put(cs35l56_base->dev);
err_unlock:
mutex_unlock(&cs35l56_base->irq_lock);
return ret;
}
EXPORT_SYMBOL_NS_GPL(cs35l56_irq, SND_SOC_CS35L56_SHARED);
int cs35l56_is_fw_reload_needed(struct cs35l56_base *cs35l56_base)
{
unsigned int val;
int ret;
/* Nothing to re-patch if we haven't done any patching yet. */
if (!cs35l56_base->fw_patched)
return false;
/*
* If we have control of RESET we will have asserted it so the firmware
* will need re-patching.
*/
if (cs35l56_base->reset_gpio)
return true;
/*
* In secure mode FIRMWARE_MISSING is cleared by the BIOS loader so
* can't be used here to test for memory retention.
* Assume that tuning must be re-loaded.
*/
if (cs35l56_base->secured)
return true;
ret = pm_runtime_resume_and_get(cs35l56_base->dev);
if (ret) {
dev_err(cs35l56_base->dev, "Failed to runtime_get: %d\n", ret);
return ret;
}
ret = regmap_read(cs35l56_base->regmap, CS35L56_PROTECTION_STATUS, &val);
if (ret)
dev_err(cs35l56_base->dev, "Failed to read PROTECTION_STATUS: %d\n", ret);
else
ret = !!(val & CS35L56_FIRMWARE_MISSING);
pm_runtime_put_autosuspend(cs35l56_base->dev);
return ret;
}
EXPORT_SYMBOL_NS_GPL(cs35l56_is_fw_reload_needed, SND_SOC_CS35L56_SHARED);
static const struct reg_sequence cs35l56_hibernate_seq[] = {
/* This must be the last register access */
REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_HIBERNATE_NOW),
};
static const struct reg_sequence cs35l56_hibernate_wake_seq[] = {
REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_WAKEUP),
};
int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base)
{
unsigned int val;
int ret;
if (!cs35l56_base->init_done)
return 0;
/* Firmware must have entered a power-save state */
ret = regmap_read_poll_timeout(cs35l56_base->regmap,
CS35L56_TRANSDUCER_ACTUAL_PS,
val, (val >= CS35L56_PS3),
CS35L56_PS3_POLL_US,
CS35L56_PS3_TIMEOUT_US);
if (ret)
dev_warn(cs35l56_base->dev, "PS3 wait failed: %d\n", ret);
/* Clear BOOT_DONE so it can be used to detect a reboot */
regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, CS35L56_OTP_BOOT_DONE_MASK);
if (!cs35l56_base->can_hibernate) {
regcache_cache_only(cs35l56_base->regmap, true);
dev_dbg(cs35l56_base->dev, "Suspended: no hibernate");
return 0;
}
/*
* Enable auto-hibernate. If it is woken by some other wake source
* it will automatically return to hibernate.
*/
cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE);
/*
* Must enter cache-only first so there can't be any more register
* accesses other than the controlled hibernate sequence below.
*/
regcache_cache_only(cs35l56_base->regmap, true);
regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
cs35l56_hibernate_seq,
ARRAY_SIZE(cs35l56_hibernate_seq));
dev_dbg(cs35l56_base->dev, "Suspended: hibernate");
return 0;
}
EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_suspend_common, SND_SOC_CS35L56_SHARED);
int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_soundwire)
{
unsigned int val;
int ret;
if (!cs35l56_base->init_done)
return 0;
if (!cs35l56_base->can_hibernate)
goto out_sync;
if (!is_soundwire) {
/*
* Dummy transaction to trigger I2C/SPI auto-wake. This will NAK on I2C.
* Must be done before releasing cache-only.
*/
regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
cs35l56_hibernate_wake_seq,
ARRAY_SIZE(cs35l56_hibernate_wake_seq));
cs35l56_wait_control_port_ready();
}
out_sync:
regcache_cache_only(cs35l56_base->regmap, false);
ret = cs35l56_wait_for_firmware_boot(cs35l56_base);
if (ret) {
dev_err(cs35l56_base->dev, "Hibernate wake failed: %d\n", ret);
goto err;
}
ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE);
if (ret)
goto err;
/* BOOT_DONE will be 1 if the amp reset */
regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, &val);
if (val & CS35L56_OTP_BOOT_DONE_MASK) {
dev_dbg(cs35l56_base->dev, "Registers reset in suspend\n");
regcache_mark_dirty(cs35l56_base->regmap);
}
regcache_sync(cs35l56_base->regmap);
dev_dbg(cs35l56_base->dev, "Resumed");
return 0;
err:
regmap_write(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1,
CS35L56_MBOX_CMD_HIBERNATE_NOW);
regcache_cache_only(cs35l56_base->regmap, true);
return ret;
}
EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_resume_common, SND_SOC_CS35L56_SHARED);
static const struct cs_dsp_region cs35l56_dsp1_regions[] = {
{ .type = WMFW_HALO_PM_PACKED, .base = CS35L56_DSP1_PMEM_0 },
{ .type = WMFW_HALO_XM_PACKED, .base = CS35L56_DSP1_XMEM_PACKED_0 },
{ .type = WMFW_HALO_YM_PACKED, .base = CS35L56_DSP1_YMEM_PACKED_0 },
{ .type = WMFW_ADSP2_XM, .base = CS35L56_DSP1_XMEM_UNPACKED24_0 },
{ .type = WMFW_ADSP2_YM, .base = CS35L56_DSP1_YMEM_UNPACKED24_0 },
};
void cs35l56_init_cs_dsp(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp)
{
cs_dsp->num = 1;
cs_dsp->type = WMFW_HALO;
cs_dsp->rev = 0;
cs_dsp->dev = cs35l56_base->dev;
cs_dsp->regmap = cs35l56_base->regmap;
cs_dsp->base = CS35L56_DSP1_CORE_BASE;
cs_dsp->base_sysinfo = CS35L56_DSP1_SYS_INFO_ID;
cs_dsp->mem = cs35l56_dsp1_regions;
cs_dsp->num_mems = ARRAY_SIZE(cs35l56_dsp1_regions);
cs_dsp->no_core_startstop = true;
}
EXPORT_SYMBOL_NS_GPL(cs35l56_init_cs_dsp, SND_SOC_CS35L56_SHARED);
int cs35l56_hw_init(struct cs35l56_base *cs35l56_base)
{
int ret;
unsigned int devid, revid, otpid, secured;
/*
* If the system is not using a reset_gpio then issue a
* dummy read to force a wakeup.
*/
if (!cs35l56_base->reset_gpio)
regmap_read(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, &devid);
cs35l56_wait_control_port_ready();
/*
* The HALO_STATE register is in different locations on Ax and B0
* devices so the REVID needs to be determined before waiting for the
* firmware to boot.
*/
ret = regmap_read(cs35l56_base->regmap, CS35L56_REVID, &revid);
if (ret < 0) {
dev_err(cs35l56_base->dev, "Get Revision ID failed\n");
return ret;
}
cs35l56_base->rev = revid & (CS35L56_AREVID_MASK | CS35L56_MTLREVID_MASK);
ret = cs35l56_wait_for_firmware_boot(cs35l56_base);
if (ret)
return ret;
ret = regmap_read(cs35l56_base->regmap, CS35L56_DEVID, &devid);
if (ret < 0) {
dev_err(cs35l56_base->dev, "Get Device ID failed\n");
return ret;
}
devid &= CS35L56_DEVID_MASK;
switch (devid) {
case 0x35A56:
break;
default:
dev_err(cs35l56_base->dev, "Unknown device %x\n", devid);
return ret;
}
ret = regmap_read(cs35l56_base->regmap, CS35L56_DSP_RESTRICT_STS1, &secured);
if (ret) {
dev_err(cs35l56_base->dev, "Get Secure status failed\n");
return ret;
}
/* When any bus is restricted treat the device as secured */
if (secured & CS35L56_RESTRICTED_MASK)
cs35l56_base->secured = true;
ret = regmap_read(cs35l56_base->regmap, CS35L56_OTPID, &otpid);
if (ret < 0) {
dev_err(cs35l56_base->dev, "Get OTP ID failed\n");
return ret;
}
dev_info(cs35l56_base->dev, "Cirrus Logic CS35L56%s Rev %02X OTP%d\n",
cs35l56_base->secured ? "s" : "", cs35l56_base->rev, otpid);
/* Wake source and *_BLOCKED interrupts default to unmasked, so mask them */
regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff);
regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1,
CS35L56_AMP_SHORT_ERR_EINT1_MASK,
0);
regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8,
CS35L56_TEMP_ERR_EINT1_MASK,
0);
return 0;
}
EXPORT_SYMBOL_NS_GPL(cs35l56_hw_init, SND_SOC_CS35L56_SHARED);
static const u32 cs35l56_bclk_valid_for_pll_freq_table[] = {
[0x0C] = 128000,
[0x0F] = 256000,
[0x11] = 384000,
[0x12] = 512000,
[0x15] = 768000,
[0x17] = 1024000,
[0x1A] = 1500000,
[0x1B] = 1536000,
[0x1C] = 2000000,
[0x1D] = 2048000,
[0x1E] = 2400000,
[0x20] = 3000000,
[0x21] = 3072000,
[0x23] = 4000000,
[0x24] = 4096000,
[0x25] = 4800000,
[0x27] = 6000000,
[0x28] = 6144000,
[0x29] = 6250000,
[0x2A] = 6400000,
[0x2E] = 8000000,
[0x2F] = 8192000,
[0x30] = 9600000,
[0x32] = 12000000,
[0x33] = 12288000,
[0x37] = 13500000,
[0x38] = 19200000,
[0x39] = 22579200,
[0x3B] = 24576000,
};
int cs35l56_get_bclk_freq_id(unsigned int freq)
{
int i;
if (freq == 0)
return -EINVAL;
/* The BCLK frequency must be a valid PLL REFCLK */
for (i = 0; i < ARRAY_SIZE(cs35l56_bclk_valid_for_pll_freq_table); ++i) {
if (cs35l56_bclk_valid_for_pll_freq_table[i] == freq)
return i;
}
return -EINVAL;
}
EXPORT_SYMBOL_NS_GPL(cs35l56_get_bclk_freq_id, SND_SOC_CS35L56_SHARED);
static const char * const cs35l56_supplies[/* auto-sized */] = {
"VDD_P",
"VDD_IO",
"VDD_A",
};
void cs35l56_fill_supply_names(struct regulator_bulk_data *data)
{
int i;
BUILD_BUG_ON(ARRAY_SIZE(cs35l56_supplies) != CS35L56_NUM_BULK_SUPPLIES);
for (i = 0; i < ARRAY_SIZE(cs35l56_supplies); i++)
data[i].supply = cs35l56_supplies[i];
}
EXPORT_SYMBOL_NS_GPL(cs35l56_fill_supply_names, SND_SOC_CS35L56_SHARED);
const char * const cs35l56_tx_input_texts[] = {
"None", "ASP1RX1", "ASP1RX2", "VMON", "IMON", "ERRVOL", "CLASSH",
"VDDBMON", "VBSTMON", "DSP1TX1", "DSP1TX2", "DSP1TX3", "DSP1TX4",
"DSP1TX5", "DSP1TX6", "DSP1TX7", "DSP1TX8", "TEMPMON",
"INTERPOLATOR", "SDW1RX1", "SDW1RX2",
};
EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_texts, SND_SOC_CS35L56_SHARED);
const unsigned int cs35l56_tx_input_values[] = {
CS35L56_INPUT_SRC_NONE,
CS35L56_INPUT_SRC_ASP1RX1,
CS35L56_INPUT_SRC_ASP1RX2,
CS35L56_INPUT_SRC_VMON,
CS35L56_INPUT_SRC_IMON,
CS35L56_INPUT_SRC_ERR_VOL,
CS35L56_INPUT_SRC_CLASSH,
CS35L56_INPUT_SRC_VDDBMON,
CS35L56_INPUT_SRC_VBSTMON,
CS35L56_INPUT_SRC_DSP1TX1,
CS35L56_INPUT_SRC_DSP1TX2,
CS35L56_INPUT_SRC_DSP1TX3,
CS35L56_INPUT_SRC_DSP1TX4,
CS35L56_INPUT_SRC_DSP1TX5,
CS35L56_INPUT_SRC_DSP1TX6,
CS35L56_INPUT_SRC_DSP1TX7,
CS35L56_INPUT_SRC_DSP1TX8,
CS35L56_INPUT_SRC_TEMPMON,
CS35L56_INPUT_SRC_INTERPOLATOR,
CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL1,
CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL2,
};
EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_values, SND_SOC_CS35L56_SHARED);
struct regmap_config cs35l56_regmap_i2c = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = CS35L56_DSP1_PMEM_5114,
.reg_defaults = cs35l56_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
.volatile_reg = cs35l56_volatile_reg,
.readable_reg = cs35l56_readable_reg,
.precious_reg = cs35l56_precious_reg,
.cache_type = REGCACHE_MAPLE,
};
EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_i2c, SND_SOC_CS35L56_SHARED);
struct regmap_config cs35l56_regmap_spi = {
.reg_bits = 32,
.val_bits = 32,
.pad_bits = 16,
.reg_stride = 4,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = CS35L56_DSP1_PMEM_5114,
.reg_defaults = cs35l56_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
.volatile_reg = cs35l56_volatile_reg,
.readable_reg = cs35l56_readable_reg,
.precious_reg = cs35l56_precious_reg,
.cache_type = REGCACHE_MAPLE,
};
EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_spi, SND_SOC_CS35L56_SHARED);
struct regmap_config cs35l56_regmap_sdw = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.reg_format_endian = REGMAP_ENDIAN_LITTLE,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = CS35L56_DSP1_PMEM_5114,
.reg_defaults = cs35l56_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
.volatile_reg = cs35l56_volatile_reg,
.readable_reg = cs35l56_readable_reg,
.precious_reg = cs35l56_precious_reg,
.cache_type = REGCACHE_MAPLE,
};
EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_sdw, SND_SOC_CS35L56_SHARED);
MODULE_DESCRIPTION("ASoC CS35L56 Shared");
MODULE_AUTHOR("Richard Fitzgerald <[email protected]>");
MODULE_AUTHOR("Simon Trimmer <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cs35l56-shared.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* CS4271 I2C audio driver
*
* Copyright (c) 2010 Alexander Sverdlin <[email protected]>
*/
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include "cs4271.h"
static int cs4271_i2c_probe(struct i2c_client *client)
{
struct regmap_config config;
config = cs4271_regmap_config;
config.reg_bits = 8;
return cs4271_probe(&client->dev,
devm_regmap_init_i2c(client, &config));
}
static const struct i2c_device_id cs4271_i2c_id[] = {
{ "cs4271", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, cs4271_i2c_id);
static struct i2c_driver cs4271_i2c_driver = {
.driver = {
.name = "cs4271",
.of_match_table = of_match_ptr(cs4271_dt_ids),
},
.probe = cs4271_i2c_probe,
.id_table = cs4271_i2c_id,
};
module_i2c_driver(cs4271_i2c_driver);
MODULE_DESCRIPTION("ASoC CS4271 I2C Driver");
MODULE_AUTHOR("Alexander Sverdlin <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cs4271-i2c.c |
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
*
* max98357a.c -- MAX98357A ALSA SoC Codec driver
*/
#include <linux/acpi.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include <sound/soc-dapm.h>
struct max98357a_priv {
struct gpio_desc *sdmode;
unsigned int sdmode_delay;
int sdmode_switch;
};
static int max98357a_daiops_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct max98357a_priv *max98357a =
snd_soc_component_get_drvdata(component);
if (!max98357a->sdmode)
return 0;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
mdelay(max98357a->sdmode_delay);
if (max98357a->sdmode_switch) {
gpiod_set_value(max98357a->sdmode, 1);
dev_dbg(component->dev, "set sdmode to 1");
}
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
gpiod_set_value(max98357a->sdmode, 0);
dev_dbg(component->dev, "set sdmode to 0");
break;
}
return 0;
}
static int max98357a_sdmode_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct max98357a_priv *max98357a =
snd_soc_component_get_drvdata(component);
if (event & SND_SOC_DAPM_POST_PMU)
max98357a->sdmode_switch = 1;
else if (event & SND_SOC_DAPM_POST_PMD)
max98357a->sdmode_switch = 0;
return 0;
}
static const struct snd_soc_dapm_widget max98357a_dapm_widgets[] = {
SND_SOC_DAPM_OUTPUT("Speaker"),
SND_SOC_DAPM_OUT_DRV_E("SD_MODE", SND_SOC_NOPM, 0, 0, NULL, 0,
max98357a_sdmode_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
};
static const struct snd_soc_dapm_route max98357a_dapm_routes[] = {
{"SD_MODE", NULL, "HiFi Playback"},
{"Speaker", NULL, "SD_MODE"},
};
static const struct snd_soc_component_driver max98357a_component_driver = {
.dapm_widgets = max98357a_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(max98357a_dapm_widgets),
.dapm_routes = max98357a_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(max98357a_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct snd_soc_dai_ops max98357a_dai_ops = {
.trigger = max98357a_daiops_trigger,
};
static struct snd_soc_dai_driver max98357a_dai_driver = {
.name = "HiFi",
.playback = {
.stream_name = "HiFi Playback",
.formats = SNDRV_PCM_FMTBIT_S16 |
SNDRV_PCM_FMTBIT_S24 |
SNDRV_PCM_FMTBIT_S32,
.rates = SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_32000 |
SNDRV_PCM_RATE_44100 |
SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_88200 |
SNDRV_PCM_RATE_96000,
.rate_min = 8000,
.rate_max = 96000,
.channels_min = 1,
.channels_max = 2,
},
.ops = &max98357a_dai_ops,
};
static int max98357a_platform_probe(struct platform_device *pdev)
{
struct max98357a_priv *max98357a;
int ret;
max98357a = devm_kzalloc(&pdev->dev, sizeof(*max98357a), GFP_KERNEL);
if (!max98357a)
return -ENOMEM;
max98357a->sdmode = devm_gpiod_get_optional(&pdev->dev,
"sdmode", GPIOD_OUT_LOW);
if (IS_ERR(max98357a->sdmode))
return PTR_ERR(max98357a->sdmode);
ret = device_property_read_u32(&pdev->dev, "sdmode-delay",
&max98357a->sdmode_delay);
if (ret) {
max98357a->sdmode_delay = 0;
dev_dbg(&pdev->dev,
"no optional property 'sdmode-delay' found, "
"default: no delay\n");
}
dev_set_drvdata(&pdev->dev, max98357a);
return devm_snd_soc_register_component(&pdev->dev,
&max98357a_component_driver,
&max98357a_dai_driver, 1);
}
#ifdef CONFIG_OF
static const struct of_device_id max98357a_device_id[] = {
{ .compatible = "maxim,max98357a" },
{ .compatible = "maxim,max98360a" },
{}
};
MODULE_DEVICE_TABLE(of, max98357a_device_id);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id max98357a_acpi_match[] = {
{ "MX98357A", 0 },
{ "MX98360A", 0 },
{},
};
MODULE_DEVICE_TABLE(acpi, max98357a_acpi_match);
#endif
static struct platform_driver max98357a_platform_driver = {
.driver = {
.name = "max98357a",
.of_match_table = of_match_ptr(max98357a_device_id),
.acpi_match_table = ACPI_PTR(max98357a_acpi_match),
},
.probe = max98357a_platform_probe,
};
module_platform_driver(max98357a_platform_driver);
MODULE_DESCRIPTION("Maxim MAX98357A Codec Driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/max98357a.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* I2S MEMS microphone driver for InvenSense ICS-43432 and similar
* MEMS-based microphones.
*
* - Non configurable.
* - I2S interface, 64 BCLs per frame, 32 bits per channel, 24 bit data
*
* Copyright (c) 2015 Axis Communications AB
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#define ICS43432_RATE_MIN 7190 /* Hz, from data sheet */
#define ICS43432_RATE_MAX 52800 /* Hz, from data sheet */
#define ICS43432_FORMATS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32)
static struct snd_soc_dai_driver ics43432_dai = {
.name = "ics43432-hifi",
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rate_min = ICS43432_RATE_MIN,
.rate_max = ICS43432_RATE_MAX,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.formats = ICS43432_FORMATS,
},
};
static const struct snd_soc_component_driver ics43432_component_driver = {
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int ics43432_probe(struct platform_device *pdev)
{
return devm_snd_soc_register_component(&pdev->dev,
&ics43432_component_driver,
&ics43432_dai, 1);
}
#ifdef CONFIG_OF
static const struct of_device_id ics43432_ids[] = {
{ .compatible = "invensense,ics43432", },
{ .compatible = "cui,cmm-4030d-261", },
{ }
};
MODULE_DEVICE_TABLE(of, ics43432_ids);
#endif
static struct platform_driver ics43432_driver = {
.driver = {
.name = "ics43432",
.of_match_table = of_match_ptr(ics43432_ids),
},
.probe = ics43432_probe,
};
module_platform_driver(ics43432_driver);
MODULE_DESCRIPTION("ASoC ICS43432 driver");
MODULE_AUTHOR("Ricard Wanderlof <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/ics43432.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm_adsp.c -- Wolfson ADSP support
*
* Copyright 2012 Wolfson Microelectronics plc
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/ctype.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/firmware.h>
#include <linux/list.h>
#include <linux/pm.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <linux/vmalloc.h>
#include <linux/workqueue.h>
#include <linux/debugfs.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/jack.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "wm_adsp.h"
#define adsp_crit(_dsp, fmt, ...) \
dev_crit(_dsp->cs_dsp.dev, "%s: " fmt, _dsp->cs_dsp.name, ##__VA_ARGS__)
#define adsp_err(_dsp, fmt, ...) \
dev_err(_dsp->cs_dsp.dev, "%s: " fmt, _dsp->cs_dsp.name, ##__VA_ARGS__)
#define adsp_warn(_dsp, fmt, ...) \
dev_warn(_dsp->cs_dsp.dev, "%s: " fmt, _dsp->cs_dsp.name, ##__VA_ARGS__)
#define adsp_info(_dsp, fmt, ...) \
dev_info(_dsp->cs_dsp.dev, "%s: " fmt, _dsp->cs_dsp.name, ##__VA_ARGS__)
#define adsp_dbg(_dsp, fmt, ...) \
dev_dbg(_dsp->cs_dsp.dev, "%s: " fmt, _dsp->cs_dsp.name, ##__VA_ARGS__)
#define compr_err(_obj, fmt, ...) \
adsp_err(_obj->dsp, "%s: " fmt, _obj->name ? _obj->name : "legacy", \
##__VA_ARGS__)
#define compr_dbg(_obj, fmt, ...) \
adsp_dbg(_obj->dsp, "%s: " fmt, _obj->name ? _obj->name : "legacy", \
##__VA_ARGS__)
#define ADSP_MAX_STD_CTRL_SIZE 512
static const struct cs_dsp_client_ops wm_adsp1_client_ops;
static const struct cs_dsp_client_ops wm_adsp2_client_ops;
#define WM_ADSP_FW_MBC_VSS 0
#define WM_ADSP_FW_HIFI 1
#define WM_ADSP_FW_TX 2
#define WM_ADSP_FW_TX_SPK 3
#define WM_ADSP_FW_RX 4
#define WM_ADSP_FW_RX_ANC 5
#define WM_ADSP_FW_CTRL 6
#define WM_ADSP_FW_ASR 7
#define WM_ADSP_FW_TRACE 8
#define WM_ADSP_FW_SPK_PROT 9
#define WM_ADSP_FW_SPK_CALI 10
#define WM_ADSP_FW_SPK_DIAG 11
#define WM_ADSP_FW_MISC 12
#define WM_ADSP_NUM_FW 13
static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = {
[WM_ADSP_FW_MBC_VSS] = "MBC/VSS",
[WM_ADSP_FW_HIFI] = "MasterHiFi",
[WM_ADSP_FW_TX] = "Tx",
[WM_ADSP_FW_TX_SPK] = "Tx Speaker",
[WM_ADSP_FW_RX] = "Rx",
[WM_ADSP_FW_RX_ANC] = "Rx ANC",
[WM_ADSP_FW_CTRL] = "Voice Ctrl",
[WM_ADSP_FW_ASR] = "ASR Assist",
[WM_ADSP_FW_TRACE] = "Dbg Trace",
[WM_ADSP_FW_SPK_PROT] = "Protection",
[WM_ADSP_FW_SPK_CALI] = "Calibration",
[WM_ADSP_FW_SPK_DIAG] = "Diagnostic",
[WM_ADSP_FW_MISC] = "Misc",
};
struct wm_adsp_system_config_xm_hdr {
__be32 sys_enable;
__be32 fw_id;
__be32 fw_rev;
__be32 boot_status;
__be32 watchdog;
__be32 dma_buffer_size;
__be32 rdma[6];
__be32 wdma[8];
__be32 build_job_name[3];
__be32 build_job_number;
} __packed;
struct wm_halo_system_config_xm_hdr {
__be32 halo_heartbeat;
__be32 build_job_name[3];
__be32 build_job_number;
} __packed;
struct wm_adsp_alg_xm_struct {
__be32 magic;
__be32 smoothing;
__be32 threshold;
__be32 host_buf_ptr;
__be32 start_seq;
__be32 high_water_mark;
__be32 low_water_mark;
__be64 smoothed_power;
} __packed;
struct wm_adsp_host_buf_coeff_v1 {
__be32 host_buf_ptr; /* Host buffer pointer */
__be32 versions; /* Version numbers */
__be32 name[4]; /* The buffer name */
} __packed;
struct wm_adsp_buffer {
__be32 buf1_base; /* Base addr of first buffer area */
__be32 buf1_size; /* Size of buf1 area in DSP words */
__be32 buf2_base; /* Base addr of 2nd buffer area */
__be32 buf1_buf2_size; /* Size of buf1+buf2 in DSP words */
__be32 buf3_base; /* Base addr of buf3 area */
__be32 buf_total_size; /* Size of buf1+buf2+buf3 in DSP words */
__be32 high_water_mark; /* Point at which IRQ is asserted */
__be32 irq_count; /* bits 1-31 count IRQ assertions */
__be32 irq_ack; /* acked IRQ count, bit 0 enables IRQ */
__be32 next_write_index; /* word index of next write */
__be32 next_read_index; /* word index of next read */
__be32 error; /* error if any */
__be32 oldest_block_index; /* word index of oldest surviving */
__be32 requested_rewind; /* how many blocks rewind was done */
__be32 reserved_space; /* internal */
__be32 min_free; /* min free space since stream start */
__be32 blocks_written[2]; /* total blocks written (64 bit) */
__be32 words_written[2]; /* total words written (64 bit) */
} __packed;
struct wm_adsp_compr;
struct wm_adsp_compr_buf {
struct list_head list;
struct wm_adsp *dsp;
struct wm_adsp_compr *compr;
struct wm_adsp_buffer_region *regions;
u32 host_buf_ptr;
u32 error;
u32 irq_count;
int read_index;
int avail;
int host_buf_mem_type;
char *name;
};
struct wm_adsp_compr {
struct list_head list;
struct wm_adsp *dsp;
struct wm_adsp_compr_buf *buf;
struct snd_compr_stream *stream;
struct snd_compressed_buffer size;
u32 *raw_buf;
unsigned int copied_total;
unsigned int sample_rate;
const char *name;
};
#define WM_ADSP_MIN_FRAGMENTS 1
#define WM_ADSP_MAX_FRAGMENTS 256
#define WM_ADSP_MIN_FRAGMENT_SIZE (16 * CS_DSP_DATA_WORD_SIZE)
#define WM_ADSP_MAX_FRAGMENT_SIZE (4096 * CS_DSP_DATA_WORD_SIZE)
#define WM_ADSP_ALG_XM_STRUCT_MAGIC 0x49aec7
#define HOST_BUFFER_FIELD(field) \
(offsetof(struct wm_adsp_buffer, field) / sizeof(__be32))
#define ALG_XM_FIELD(field) \
(offsetof(struct wm_adsp_alg_xm_struct, field) / sizeof(__be32))
#define HOST_BUF_COEFF_SUPPORTED_COMPAT_VER 1
#define HOST_BUF_COEFF_COMPAT_VER_MASK 0xFF00
#define HOST_BUF_COEFF_COMPAT_VER_SHIFT 8
static int wm_adsp_buffer_init(struct wm_adsp *dsp);
static int wm_adsp_buffer_free(struct wm_adsp *dsp);
struct wm_adsp_buffer_region {
unsigned int offset;
unsigned int cumulative_size;
unsigned int mem_type;
unsigned int base_addr;
};
struct wm_adsp_buffer_region_def {
unsigned int mem_type;
unsigned int base_offset;
unsigned int size_offset;
};
static const struct wm_adsp_buffer_region_def default_regions[] = {
{
.mem_type = WMFW_ADSP2_XM,
.base_offset = HOST_BUFFER_FIELD(buf1_base),
.size_offset = HOST_BUFFER_FIELD(buf1_size),
},
{
.mem_type = WMFW_ADSP2_XM,
.base_offset = HOST_BUFFER_FIELD(buf2_base),
.size_offset = HOST_BUFFER_FIELD(buf1_buf2_size),
},
{
.mem_type = WMFW_ADSP2_YM,
.base_offset = HOST_BUFFER_FIELD(buf3_base),
.size_offset = HOST_BUFFER_FIELD(buf_total_size),
},
};
struct wm_adsp_fw_caps {
u32 id;
struct snd_codec_desc desc;
int num_regions;
const struct wm_adsp_buffer_region_def *region_defs;
};
static const struct wm_adsp_fw_caps ctrl_caps[] = {
{
.id = SND_AUDIOCODEC_BESPOKE,
.desc = {
.max_ch = 8,
.sample_rates = { 16000 },
.num_sample_rates = 1,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.num_regions = ARRAY_SIZE(default_regions),
.region_defs = default_regions,
},
};
static const struct wm_adsp_fw_caps trace_caps[] = {
{
.id = SND_AUDIOCODEC_BESPOKE,
.desc = {
.max_ch = 8,
.sample_rates = {
4000, 8000, 11025, 12000, 16000, 22050,
24000, 32000, 44100, 48000, 64000, 88200,
96000, 176400, 192000
},
.num_sample_rates = 15,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.num_regions = ARRAY_SIZE(default_regions),
.region_defs = default_regions,
},
};
static const struct {
const char *file;
int compr_direction;
int num_caps;
const struct wm_adsp_fw_caps *caps;
bool voice_trigger;
} wm_adsp_fw[WM_ADSP_NUM_FW] = {
[WM_ADSP_FW_MBC_VSS] = { .file = "mbc-vss" },
[WM_ADSP_FW_HIFI] = { .file = "hifi" },
[WM_ADSP_FW_TX] = { .file = "tx" },
[WM_ADSP_FW_TX_SPK] = { .file = "tx-spk" },
[WM_ADSP_FW_RX] = { .file = "rx" },
[WM_ADSP_FW_RX_ANC] = { .file = "rx-anc" },
[WM_ADSP_FW_CTRL] = {
.file = "ctrl",
.compr_direction = SND_COMPRESS_CAPTURE,
.num_caps = ARRAY_SIZE(ctrl_caps),
.caps = ctrl_caps,
.voice_trigger = true,
},
[WM_ADSP_FW_ASR] = { .file = "asr" },
[WM_ADSP_FW_TRACE] = {
.file = "trace",
.compr_direction = SND_COMPRESS_CAPTURE,
.num_caps = ARRAY_SIZE(trace_caps),
.caps = trace_caps,
},
[WM_ADSP_FW_SPK_PROT] = {
.file = "spk-prot",
.compr_direction = SND_COMPRESS_CAPTURE,
.num_caps = ARRAY_SIZE(trace_caps),
.caps = trace_caps,
},
[WM_ADSP_FW_SPK_CALI] = { .file = "spk-cali" },
[WM_ADSP_FW_SPK_DIAG] = { .file = "spk-diag" },
[WM_ADSP_FW_MISC] = { .file = "misc" },
};
struct wm_coeff_ctl {
const char *name;
struct cs_dsp_coeff_ctl *cs_ctl;
struct soc_bytes_ext bytes_ext;
struct work_struct work;
};
int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
struct wm_adsp *dsp = snd_soc_component_get_drvdata(component);
ucontrol->value.enumerated.item[0] = dsp[e->shift_l].fw;
return 0;
}
EXPORT_SYMBOL_GPL(wm_adsp_fw_get);
int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
struct wm_adsp *dsp = snd_soc_component_get_drvdata(component);
int ret = 1;
if (ucontrol->value.enumerated.item[0] == dsp[e->shift_l].fw)
return 0;
if (ucontrol->value.enumerated.item[0] >= WM_ADSP_NUM_FW)
return -EINVAL;
mutex_lock(&dsp[e->shift_l].cs_dsp.pwr_lock);
if (dsp[e->shift_l].cs_dsp.booted || !list_empty(&dsp[e->shift_l].compr_list))
ret = -EBUSY;
else
dsp[e->shift_l].fw = ucontrol->value.enumerated.item[0];
mutex_unlock(&dsp[e->shift_l].cs_dsp.pwr_lock);
return ret;
}
EXPORT_SYMBOL_GPL(wm_adsp_fw_put);
const struct soc_enum wm_adsp_fw_enum[] = {
SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
SOC_ENUM_SINGLE(0, 4, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
SOC_ENUM_SINGLE(0, 5, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
SOC_ENUM_SINGLE(0, 6, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
};
EXPORT_SYMBOL_GPL(wm_adsp_fw_enum);
static inline struct wm_coeff_ctl *bytes_ext_to_ctl(struct soc_bytes_ext *ext)
{
return container_of(ext, struct wm_coeff_ctl, bytes_ext);
}
static int wm_coeff_info(struct snd_kcontrol *kctl,
struct snd_ctl_elem_info *uinfo)
{
struct soc_bytes_ext *bytes_ext =
(struct soc_bytes_ext *)kctl->private_value;
struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
struct cs_dsp_coeff_ctl *cs_ctl = ctl->cs_ctl;
switch (cs_ctl->type) {
case WMFW_CTL_TYPE_ACKED:
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->value.integer.min = CS_DSP_ACKED_CTL_MIN_VALUE;
uinfo->value.integer.max = CS_DSP_ACKED_CTL_MAX_VALUE;
uinfo->value.integer.step = 1;
uinfo->count = 1;
break;
default:
uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
uinfo->count = cs_ctl->len;
break;
}
return 0;
}
static int wm_coeff_put(struct snd_kcontrol *kctl,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_bytes_ext *bytes_ext =
(struct soc_bytes_ext *)kctl->private_value;
struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
struct cs_dsp_coeff_ctl *cs_ctl = ctl->cs_ctl;
char *p = ucontrol->value.bytes.data;
int ret = 0;
mutex_lock(&cs_ctl->dsp->pwr_lock);
ret = cs_dsp_coeff_write_ctrl(cs_ctl, 0, p, cs_ctl->len);
mutex_unlock(&cs_ctl->dsp->pwr_lock);
return ret;
}
static int wm_coeff_tlv_put(struct snd_kcontrol *kctl,
const unsigned int __user *bytes, unsigned int size)
{
struct soc_bytes_ext *bytes_ext =
(struct soc_bytes_ext *)kctl->private_value;
struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
struct cs_dsp_coeff_ctl *cs_ctl = ctl->cs_ctl;
void *scratch;
int ret = 0;
scratch = vmalloc(size);
if (!scratch)
return -ENOMEM;
if (copy_from_user(scratch, bytes, size)) {
ret = -EFAULT;
} else {
mutex_lock(&cs_ctl->dsp->pwr_lock);
ret = cs_dsp_coeff_write_ctrl(cs_ctl, 0, scratch, size);
mutex_unlock(&cs_ctl->dsp->pwr_lock);
}
vfree(scratch);
return ret;
}
static int wm_coeff_put_acked(struct snd_kcontrol *kctl,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_bytes_ext *bytes_ext =
(struct soc_bytes_ext *)kctl->private_value;
struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
struct cs_dsp_coeff_ctl *cs_ctl = ctl->cs_ctl;
unsigned int val = ucontrol->value.integer.value[0];
int ret;
if (val == 0)
return 0; /* 0 means no event */
mutex_lock(&cs_ctl->dsp->pwr_lock);
if (cs_ctl->enabled)
ret = cs_dsp_coeff_write_acked_control(cs_ctl, val);
else
ret = -EPERM;
mutex_unlock(&cs_ctl->dsp->pwr_lock);
if (ret < 0)
return ret;
return 1;
}
static int wm_coeff_get(struct snd_kcontrol *kctl,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_bytes_ext *bytes_ext =
(struct soc_bytes_ext *)kctl->private_value;
struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
struct cs_dsp_coeff_ctl *cs_ctl = ctl->cs_ctl;
char *p = ucontrol->value.bytes.data;
int ret;
mutex_lock(&cs_ctl->dsp->pwr_lock);
ret = cs_dsp_coeff_read_ctrl(cs_ctl, 0, p, cs_ctl->len);
mutex_unlock(&cs_ctl->dsp->pwr_lock);
return ret;
}
static int wm_coeff_tlv_get(struct snd_kcontrol *kctl,
unsigned int __user *bytes, unsigned int size)
{
struct soc_bytes_ext *bytes_ext =
(struct soc_bytes_ext *)kctl->private_value;
struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
struct cs_dsp_coeff_ctl *cs_ctl = ctl->cs_ctl;
int ret = 0;
mutex_lock(&cs_ctl->dsp->pwr_lock);
ret = cs_dsp_coeff_read_ctrl(cs_ctl, 0, cs_ctl->cache, size);
if (!ret && copy_to_user(bytes, cs_ctl->cache, size))
ret = -EFAULT;
mutex_unlock(&cs_ctl->dsp->pwr_lock);
return ret;
}
static int wm_coeff_get_acked(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
/*
* Although it's not useful to read an acked control, we must satisfy
* user-side assumptions that all controls are readable and that a
* write of the same value should be filtered out (it's valid to send
* the same event number again to the firmware). We therefore return 0,
* meaning "no event" so valid event numbers will always be a change
*/
ucontrol->value.integer.value[0] = 0;
return 0;
}
static unsigned int wmfw_convert_flags(unsigned int in, unsigned int len)
{
unsigned int out, rd, wr, vol;
if (len > ADSP_MAX_STD_CTRL_SIZE) {
rd = SNDRV_CTL_ELEM_ACCESS_TLV_READ;
wr = SNDRV_CTL_ELEM_ACCESS_TLV_WRITE;
vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE;
out = SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK;
} else {
rd = SNDRV_CTL_ELEM_ACCESS_READ;
wr = SNDRV_CTL_ELEM_ACCESS_WRITE;
vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE;
out = 0;
}
if (in) {
out |= rd;
if (in & WMFW_CTL_FLAG_WRITEABLE)
out |= wr;
if (in & WMFW_CTL_FLAG_VOLATILE)
out |= vol;
} else {
out |= rd | wr | vol;
}
return out;
}
static void wm_adsp_ctl_work(struct work_struct *work)
{
struct wm_coeff_ctl *ctl = container_of(work,
struct wm_coeff_ctl,
work);
struct cs_dsp_coeff_ctl *cs_ctl = ctl->cs_ctl;
struct wm_adsp *dsp = container_of(cs_ctl->dsp,
struct wm_adsp,
cs_dsp);
struct snd_kcontrol_new *kcontrol;
kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL);
if (!kcontrol)
return;
kcontrol->name = ctl->name;
kcontrol->info = wm_coeff_info;
kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER;
kcontrol->tlv.c = snd_soc_bytes_tlv_callback;
kcontrol->private_value = (unsigned long)&ctl->bytes_ext;
kcontrol->access = wmfw_convert_flags(cs_ctl->flags, cs_ctl->len);
switch (cs_ctl->type) {
case WMFW_CTL_TYPE_ACKED:
kcontrol->get = wm_coeff_get_acked;
kcontrol->put = wm_coeff_put_acked;
break;
default:
if (kcontrol->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
ctl->bytes_ext.max = cs_ctl->len;
ctl->bytes_ext.get = wm_coeff_tlv_get;
ctl->bytes_ext.put = wm_coeff_tlv_put;
} else {
kcontrol->get = wm_coeff_get;
kcontrol->put = wm_coeff_put;
}
break;
}
snd_soc_add_component_controls(dsp->component, kcontrol, 1);
kfree(kcontrol);
}
static int wm_adsp_control_add(struct cs_dsp_coeff_ctl *cs_ctl)
{
struct wm_adsp *dsp = container_of(cs_ctl->dsp, struct wm_adsp, cs_dsp);
struct cs_dsp *cs_dsp = &dsp->cs_dsp;
struct wm_coeff_ctl *ctl;
char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
const char *region_name;
int ret;
if (cs_ctl->flags & WMFW_CTL_FLAG_SYS)
return 0;
region_name = cs_dsp_mem_region_name(cs_ctl->alg_region.type);
if (!region_name) {
adsp_err(dsp, "Unknown region type: %d\n", cs_ctl->alg_region.type);
return -EINVAL;
}
switch (cs_dsp->fw_ver) {
case 0:
case 1:
ret = scnprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN,
"%s %s %x", cs_dsp->name, region_name,
cs_ctl->alg_region.alg);
break;
case 2:
ret = scnprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN,
"%s%c %.12s %x", cs_dsp->name, *region_name,
wm_adsp_fw_text[dsp->fw], cs_ctl->alg_region.alg);
break;
default:
ret = scnprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN,
"%s %.12s %x", cs_dsp->name,
wm_adsp_fw_text[dsp->fw], cs_ctl->alg_region.alg);
break;
}
if (cs_ctl->subname) {
int avail = SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret - 2;
int skip = 0;
if (dsp->component->name_prefix)
avail -= strlen(dsp->component->name_prefix) + 1;
/* Truncate the subname from the start if it is too long */
if (cs_ctl->subname_len > avail)
skip = cs_ctl->subname_len - avail;
snprintf(name + ret, SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret,
" %.*s", cs_ctl->subname_len - skip, cs_ctl->subname + skip);
}
ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
if (!ctl)
return -ENOMEM;
ctl->cs_ctl = cs_ctl;
ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL);
if (!ctl->name) {
ret = -ENOMEM;
goto err_ctl;
}
cs_ctl->priv = ctl;
INIT_WORK(&ctl->work, wm_adsp_ctl_work);
schedule_work(&ctl->work);
return 0;
err_ctl:
kfree(ctl);
return ret;
}
static void wm_adsp_control_remove(struct cs_dsp_coeff_ctl *cs_ctl)
{
struct wm_coeff_ctl *ctl = cs_ctl->priv;
cancel_work_sync(&ctl->work);
kfree(ctl->name);
kfree(ctl);
}
int wm_adsp_write_ctl(struct wm_adsp *dsp, const char *name, int type,
unsigned int alg, void *buf, size_t len)
{
struct cs_dsp_coeff_ctl *cs_ctl = cs_dsp_get_ctl(&dsp->cs_dsp, name, type, alg);
struct wm_coeff_ctl *ctl;
int ret;
mutex_lock(&dsp->cs_dsp.pwr_lock);
ret = cs_dsp_coeff_write_ctrl(cs_ctl, 0, buf, len);
mutex_unlock(&dsp->cs_dsp.pwr_lock);
if (ret < 0)
return ret;
if (ret == 0 || (cs_ctl->flags & WMFW_CTL_FLAG_SYS))
return 0;
ctl = cs_ctl->priv;
return snd_soc_component_notify_control(dsp->component, ctl->name);
}
EXPORT_SYMBOL_GPL(wm_adsp_write_ctl);
int wm_adsp_read_ctl(struct wm_adsp *dsp, const char *name, int type,
unsigned int alg, void *buf, size_t len)
{
int ret;
mutex_lock(&dsp->cs_dsp.pwr_lock);
ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(&dsp->cs_dsp, name, type, alg),
0, buf, len);
mutex_unlock(&dsp->cs_dsp.pwr_lock);
return ret;
}
EXPORT_SYMBOL_GPL(wm_adsp_read_ctl);
static void wm_adsp_release_firmware_files(struct wm_adsp *dsp,
const struct firmware *wmfw_firmware,
char *wmfw_filename,
const struct firmware *coeff_firmware,
char *coeff_filename)
{
if (wmfw_firmware)
release_firmware(wmfw_firmware);
kfree(wmfw_filename);
if (coeff_firmware)
release_firmware(coeff_firmware);
kfree(coeff_filename);
}
static int wm_adsp_request_firmware_file(struct wm_adsp *dsp,
const struct firmware **firmware, char **filename,
const char *dir, const char *system_name,
const char *asoc_component_prefix,
const char *filetype)
{
struct cs_dsp *cs_dsp = &dsp->cs_dsp;
char *s, c;
int ret = 0;
if (system_name && asoc_component_prefix)
*filename = kasprintf(GFP_KERNEL, "%s%s-%s-%s-%s-%s.%s", dir, dsp->part,
dsp->fwf_name, wm_adsp_fw[dsp->fw].file, system_name,
asoc_component_prefix, filetype);
else if (system_name)
*filename = kasprintf(GFP_KERNEL, "%s%s-%s-%s-%s.%s", dir, dsp->part,
dsp->fwf_name, wm_adsp_fw[dsp->fw].file, system_name,
filetype);
else
*filename = kasprintf(GFP_KERNEL, "%s%s-%s-%s.%s", dir, dsp->part, dsp->fwf_name,
wm_adsp_fw[dsp->fw].file, filetype);
if (*filename == NULL)
return -ENOMEM;
/*
* Make sure that filename is lower-case and any non alpha-numeric
* characters except full stop and forward slash are replaced with
* hyphens.
*/
s = *filename;
while (*s) {
c = *s;
if (isalnum(c))
*s = tolower(c);
else if ((c != '.') && (c != '/'))
*s = '-';
s++;
}
ret = firmware_request_nowarn(firmware, *filename, cs_dsp->dev);
if (ret != 0) {
adsp_dbg(dsp, "Failed to request '%s'\n", *filename);
kfree(*filename);
*filename = NULL;
} else {
adsp_dbg(dsp, "Found '%s'\n", *filename);
}
return ret;
}
static const char *cirrus_dir = "cirrus/";
static int wm_adsp_request_firmware_files(struct wm_adsp *dsp,
const struct firmware **wmfw_firmware,
char **wmfw_filename,
const struct firmware **coeff_firmware,
char **coeff_filename)
{
const char *system_name = dsp->system_name;
const char *asoc_component_prefix = dsp->component->name_prefix;
int ret = 0;
if (system_name && asoc_component_prefix) {
if (!wm_adsp_request_firmware_file(dsp, wmfw_firmware, wmfw_filename,
cirrus_dir, system_name,
asoc_component_prefix, "wmfw")) {
wm_adsp_request_firmware_file(dsp, coeff_firmware, coeff_filename,
cirrus_dir, system_name,
asoc_component_prefix, "bin");
return 0;
}
}
if (system_name) {
if (!wm_adsp_request_firmware_file(dsp, wmfw_firmware, wmfw_filename,
cirrus_dir, system_name,
NULL, "wmfw")) {
if (asoc_component_prefix)
wm_adsp_request_firmware_file(dsp, coeff_firmware, coeff_filename,
cirrus_dir, system_name,
asoc_component_prefix, "bin");
if (!*coeff_firmware)
wm_adsp_request_firmware_file(dsp, coeff_firmware, coeff_filename,
cirrus_dir, system_name,
NULL, "bin");
return 0;
}
}
if (!wm_adsp_request_firmware_file(dsp, wmfw_firmware, wmfw_filename,
"", NULL, NULL, "wmfw")) {
wm_adsp_request_firmware_file(dsp, coeff_firmware, coeff_filename,
"", NULL, NULL, "bin");
return 0;
}
ret = wm_adsp_request_firmware_file(dsp, wmfw_firmware, wmfw_filename,
cirrus_dir, NULL, NULL, "wmfw");
if (!ret) {
wm_adsp_request_firmware_file(dsp, coeff_firmware, coeff_filename,
cirrus_dir, NULL, NULL, "bin");
return 0;
}
if (dsp->wmfw_optional) {
if (system_name) {
if (asoc_component_prefix)
wm_adsp_request_firmware_file(dsp, coeff_firmware, coeff_filename,
cirrus_dir, system_name,
asoc_component_prefix, "bin");
if (!*coeff_firmware)
wm_adsp_request_firmware_file(dsp, coeff_firmware, coeff_filename,
cirrus_dir, system_name,
NULL, "bin");
}
if (!*coeff_firmware)
wm_adsp_request_firmware_file(dsp, coeff_firmware, coeff_filename,
"", NULL, NULL, "bin");
if (!*coeff_firmware)
wm_adsp_request_firmware_file(dsp, coeff_firmware, coeff_filename,
cirrus_dir, NULL, NULL, "bin");
return 0;
}
adsp_err(dsp, "Failed to request firmware <%s>%s-%s-%s<-%s<%s>>.wmfw\n",
cirrus_dir, dsp->part, dsp->fwf_name, wm_adsp_fw[dsp->fw].file,
system_name, asoc_component_prefix);
return -ENOENT;
}
static int wm_adsp_common_init(struct wm_adsp *dsp)
{
char *p;
INIT_LIST_HEAD(&dsp->compr_list);
INIT_LIST_HEAD(&dsp->buffer_list);
if (!dsp->fwf_name) {
p = devm_kstrdup(dsp->cs_dsp.dev, dsp->cs_dsp.name, GFP_KERNEL);
if (!p)
return -ENOMEM;
dsp->fwf_name = p;
for (; *p != 0; ++p)
*p = tolower(*p);
}
return 0;
}
int wm_adsp1_init(struct wm_adsp *dsp)
{
int ret;
dsp->cs_dsp.client_ops = &wm_adsp1_client_ops;
ret = cs_dsp_adsp1_init(&dsp->cs_dsp);
if (ret)
return ret;
return wm_adsp_common_init(dsp);
}
EXPORT_SYMBOL_GPL(wm_adsp1_init);
int wm_adsp1_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
struct wm_adsp *dsp = &dsps[w->shift];
int ret = 0;
char *wmfw_filename = NULL;
const struct firmware *wmfw_firmware = NULL;
char *coeff_filename = NULL;
const struct firmware *coeff_firmware = NULL;
dsp->component = component;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
ret = wm_adsp_request_firmware_files(dsp,
&wmfw_firmware, &wmfw_filename,
&coeff_firmware, &coeff_filename);
if (ret)
break;
ret = cs_dsp_adsp1_power_up(&dsp->cs_dsp,
wmfw_firmware, wmfw_filename,
coeff_firmware, coeff_filename,
wm_adsp_fw_text[dsp->fw]);
wm_adsp_release_firmware_files(dsp,
wmfw_firmware, wmfw_filename,
coeff_firmware, coeff_filename);
break;
case SND_SOC_DAPM_PRE_PMD:
cs_dsp_adsp1_power_down(&dsp->cs_dsp);
break;
default:
break;
}
return ret;
}
EXPORT_SYMBOL_GPL(wm_adsp1_event);
int wm_adsp2_set_dspclk(struct snd_soc_dapm_widget *w, unsigned int freq)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
struct wm_adsp *dsp = &dsps[w->shift];
return cs_dsp_set_dspclk(&dsp->cs_dsp, freq);
}
EXPORT_SYMBOL_GPL(wm_adsp2_set_dspclk);
int wm_adsp2_preloader_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct wm_adsp *dsp = &dsps[mc->shift - 1];
ucontrol->value.integer.value[0] = dsp->preloaded;
return 0;
}
EXPORT_SYMBOL_GPL(wm_adsp2_preloader_get);
int wm_adsp2_preloader_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct wm_adsp *dsp = &dsps[mc->shift - 1];
char preload[32];
if (dsp->preloaded == ucontrol->value.integer.value[0])
return 0;
snprintf(preload, ARRAY_SIZE(preload), "%s Preload", dsp->cs_dsp.name);
if (ucontrol->value.integer.value[0] || dsp->toggle_preload)
snd_soc_component_force_enable_pin(component, preload);
else
snd_soc_component_disable_pin(component, preload);
snd_soc_dapm_sync(dapm);
flush_work(&dsp->boot_work);
dsp->preloaded = ucontrol->value.integer.value[0];
if (dsp->toggle_preload) {
snd_soc_component_disable_pin(component, preload);
snd_soc_dapm_sync(dapm);
}
return 1;
}
EXPORT_SYMBOL_GPL(wm_adsp2_preloader_put);
int wm_adsp_power_up(struct wm_adsp *dsp, bool load_firmware)
{
int ret = 0;
char *wmfw_filename = NULL;
const struct firmware *wmfw_firmware = NULL;
char *coeff_filename = NULL;
const struct firmware *coeff_firmware = NULL;
if (load_firmware) {
ret = wm_adsp_request_firmware_files(dsp,
&wmfw_firmware, &wmfw_filename,
&coeff_firmware, &coeff_filename);
if (ret)
return ret;
}
ret = cs_dsp_power_up(&dsp->cs_dsp,
wmfw_firmware, wmfw_filename,
coeff_firmware, coeff_filename,
wm_adsp_fw_text[dsp->fw]);
wm_adsp_release_firmware_files(dsp,
wmfw_firmware, wmfw_filename,
coeff_firmware, coeff_filename);
return ret;
}
EXPORT_SYMBOL_GPL(wm_adsp_power_up);
void wm_adsp_power_down(struct wm_adsp *dsp)
{
cs_dsp_power_down(&dsp->cs_dsp);
}
EXPORT_SYMBOL_GPL(wm_adsp_power_down);
static void wm_adsp_boot_work(struct work_struct *work)
{
struct wm_adsp *dsp = container_of(work,
struct wm_adsp,
boot_work);
wm_adsp_power_up(dsp, true);
}
int wm_adsp_early_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
struct wm_adsp *dsp = &dsps[w->shift];
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
queue_work(system_unbound_wq, &dsp->boot_work);
break;
case SND_SOC_DAPM_PRE_PMD:
wm_adsp_power_down(dsp);
break;
default:
break;
}
return 0;
}
EXPORT_SYMBOL_GPL(wm_adsp_early_event);
static int wm_adsp_pre_run(struct cs_dsp *cs_dsp)
{
struct wm_adsp *dsp = container_of(cs_dsp, struct wm_adsp, cs_dsp);
if (!dsp->pre_run)
return 0;
return (*dsp->pre_run)(dsp);
}
static int wm_adsp_event_post_run(struct cs_dsp *cs_dsp)
{
struct wm_adsp *dsp = container_of(cs_dsp, struct wm_adsp, cs_dsp);
if (wm_adsp_fw[dsp->fw].num_caps != 0)
return wm_adsp_buffer_init(dsp);
return 0;
}
static void wm_adsp_event_post_stop(struct cs_dsp *cs_dsp)
{
struct wm_adsp *dsp = container_of(cs_dsp, struct wm_adsp, cs_dsp);
if (wm_adsp_fw[dsp->fw].num_caps != 0)
wm_adsp_buffer_free(dsp);
dsp->fatal_error = false;
}
int wm_adsp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
struct wm_adsp *dsp = &dsps[w->shift];
int ret = 0;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
flush_work(&dsp->boot_work);
ret = cs_dsp_run(&dsp->cs_dsp);
break;
case SND_SOC_DAPM_PRE_PMD:
cs_dsp_stop(&dsp->cs_dsp);
break;
default:
break;
}
return ret;
}
EXPORT_SYMBOL_GPL(wm_adsp_event);
int wm_adsp2_component_probe(struct wm_adsp *dsp, struct snd_soc_component *component)
{
char preload[32];
if (!dsp->cs_dsp.no_core_startstop) {
snprintf(preload, ARRAY_SIZE(preload), "%s Preload", dsp->cs_dsp.name);
snd_soc_component_disable_pin(component, preload);
}
cs_dsp_init_debugfs(&dsp->cs_dsp, component->debugfs_root);
dsp->component = component;
return 0;
}
EXPORT_SYMBOL_GPL(wm_adsp2_component_probe);
int wm_adsp2_component_remove(struct wm_adsp *dsp, struct snd_soc_component *component)
{
cs_dsp_cleanup_debugfs(&dsp->cs_dsp);
return 0;
}
EXPORT_SYMBOL_GPL(wm_adsp2_component_remove);
int wm_adsp2_init(struct wm_adsp *dsp)
{
int ret;
INIT_WORK(&dsp->boot_work, wm_adsp_boot_work);
dsp->sys_config_size = sizeof(struct wm_adsp_system_config_xm_hdr);
dsp->cs_dsp.client_ops = &wm_adsp2_client_ops;
ret = cs_dsp_adsp2_init(&dsp->cs_dsp);
if (ret)
return ret;
return wm_adsp_common_init(dsp);
}
EXPORT_SYMBOL_GPL(wm_adsp2_init);
int wm_halo_init(struct wm_adsp *dsp)
{
int ret;
INIT_WORK(&dsp->boot_work, wm_adsp_boot_work);
dsp->sys_config_size = sizeof(struct wm_halo_system_config_xm_hdr);
dsp->cs_dsp.client_ops = &wm_adsp2_client_ops;
ret = cs_dsp_halo_init(&dsp->cs_dsp);
if (ret)
return ret;
return wm_adsp_common_init(dsp);
}
EXPORT_SYMBOL_GPL(wm_halo_init);
void wm_adsp2_remove(struct wm_adsp *dsp)
{
cs_dsp_remove(&dsp->cs_dsp);
}
EXPORT_SYMBOL_GPL(wm_adsp2_remove);
static inline int wm_adsp_compr_attached(struct wm_adsp_compr *compr)
{
return compr->buf != NULL;
}
static int wm_adsp_compr_attach(struct wm_adsp_compr *compr)
{
struct wm_adsp_compr_buf *buf = NULL, *tmp;
if (compr->dsp->fatal_error)
return -EINVAL;
list_for_each_entry(tmp, &compr->dsp->buffer_list, list) {
if (!tmp->name || !strcmp(compr->name, tmp->name)) {
buf = tmp;
break;
}
}
if (!buf)
return -EINVAL;
compr->buf = buf;
buf->compr = compr;
return 0;
}
static void wm_adsp_compr_detach(struct wm_adsp_compr *compr)
{
if (!compr)
return;
/* Wake the poll so it can see buffer is no longer attached */
if (compr->stream)
snd_compr_fragment_elapsed(compr->stream);
if (wm_adsp_compr_attached(compr)) {
compr->buf->compr = NULL;
compr->buf = NULL;
}
}
int wm_adsp_compr_open(struct wm_adsp *dsp, struct snd_compr_stream *stream)
{
struct wm_adsp_compr *compr, *tmp;
struct snd_soc_pcm_runtime *rtd = stream->private_data;
int ret = 0;
mutex_lock(&dsp->cs_dsp.pwr_lock);
if (wm_adsp_fw[dsp->fw].num_caps == 0) {
adsp_err(dsp, "%s: Firmware does not support compressed API\n",
asoc_rtd_to_codec(rtd, 0)->name);
ret = -ENXIO;
goto out;
}
if (wm_adsp_fw[dsp->fw].compr_direction != stream->direction) {
adsp_err(dsp, "%s: Firmware does not support stream direction\n",
asoc_rtd_to_codec(rtd, 0)->name);
ret = -EINVAL;
goto out;
}
list_for_each_entry(tmp, &dsp->compr_list, list) {
if (!strcmp(tmp->name, asoc_rtd_to_codec(rtd, 0)->name)) {
adsp_err(dsp, "%s: Only a single stream supported per dai\n",
asoc_rtd_to_codec(rtd, 0)->name);
ret = -EBUSY;
goto out;
}
}
compr = kzalloc(sizeof(*compr), GFP_KERNEL);
if (!compr) {
ret = -ENOMEM;
goto out;
}
compr->dsp = dsp;
compr->stream = stream;
compr->name = asoc_rtd_to_codec(rtd, 0)->name;
list_add_tail(&compr->list, &dsp->compr_list);
stream->runtime->private_data = compr;
out:
mutex_unlock(&dsp->cs_dsp.pwr_lock);
return ret;
}
EXPORT_SYMBOL_GPL(wm_adsp_compr_open);
int wm_adsp_compr_free(struct snd_soc_component *component,
struct snd_compr_stream *stream)
{
struct wm_adsp_compr *compr = stream->runtime->private_data;
struct wm_adsp *dsp = compr->dsp;
mutex_lock(&dsp->cs_dsp.pwr_lock);
wm_adsp_compr_detach(compr);
list_del(&compr->list);
kfree(compr->raw_buf);
kfree(compr);
mutex_unlock(&dsp->cs_dsp.pwr_lock);
return 0;
}
EXPORT_SYMBOL_GPL(wm_adsp_compr_free);
static int wm_adsp_compr_check_params(struct snd_compr_stream *stream,
struct snd_compr_params *params)
{
struct wm_adsp_compr *compr = stream->runtime->private_data;
struct wm_adsp *dsp = compr->dsp;
const struct wm_adsp_fw_caps *caps;
const struct snd_codec_desc *desc;
int i, j;
if (params->buffer.fragment_size < WM_ADSP_MIN_FRAGMENT_SIZE ||
params->buffer.fragment_size > WM_ADSP_MAX_FRAGMENT_SIZE ||
params->buffer.fragments < WM_ADSP_MIN_FRAGMENTS ||
params->buffer.fragments > WM_ADSP_MAX_FRAGMENTS ||
params->buffer.fragment_size % CS_DSP_DATA_WORD_SIZE) {
compr_err(compr, "Invalid buffer fragsize=%d fragments=%d\n",
params->buffer.fragment_size,
params->buffer.fragments);
return -EINVAL;
}
for (i = 0; i < wm_adsp_fw[dsp->fw].num_caps; i++) {
caps = &wm_adsp_fw[dsp->fw].caps[i];
desc = &caps->desc;
if (caps->id != params->codec.id)
continue;
if (stream->direction == SND_COMPRESS_PLAYBACK) {
if (desc->max_ch < params->codec.ch_out)
continue;
} else {
if (desc->max_ch < params->codec.ch_in)
continue;
}
if (!(desc->formats & (1 << params->codec.format)))
continue;
for (j = 0; j < desc->num_sample_rates; ++j)
if (desc->sample_rates[j] == params->codec.sample_rate)
return 0;
}
compr_err(compr, "Invalid params id=%u ch=%u,%u rate=%u fmt=%u\n",
params->codec.id, params->codec.ch_in, params->codec.ch_out,
params->codec.sample_rate, params->codec.format);
return -EINVAL;
}
static inline unsigned int wm_adsp_compr_frag_words(struct wm_adsp_compr *compr)
{
return compr->size.fragment_size / CS_DSP_DATA_WORD_SIZE;
}
int wm_adsp_compr_set_params(struct snd_soc_component *component,
struct snd_compr_stream *stream,
struct snd_compr_params *params)
{
struct wm_adsp_compr *compr = stream->runtime->private_data;
unsigned int size;
int ret;
ret = wm_adsp_compr_check_params(stream, params);
if (ret)
return ret;
compr->size = params->buffer;
compr_dbg(compr, "fragment_size=%d fragments=%d\n",
compr->size.fragment_size, compr->size.fragments);
size = wm_adsp_compr_frag_words(compr) * sizeof(*compr->raw_buf);
compr->raw_buf = kmalloc(size, GFP_DMA | GFP_KERNEL);
if (!compr->raw_buf)
return -ENOMEM;
compr->sample_rate = params->codec.sample_rate;
return 0;
}
EXPORT_SYMBOL_GPL(wm_adsp_compr_set_params);
int wm_adsp_compr_get_caps(struct snd_soc_component *component,
struct snd_compr_stream *stream,
struct snd_compr_caps *caps)
{
struct wm_adsp_compr *compr = stream->runtime->private_data;
int fw = compr->dsp->fw;
int i;
if (wm_adsp_fw[fw].caps) {
for (i = 0; i < wm_adsp_fw[fw].num_caps; i++)
caps->codecs[i] = wm_adsp_fw[fw].caps[i].id;
caps->num_codecs = i;
caps->direction = wm_adsp_fw[fw].compr_direction;
caps->min_fragment_size = WM_ADSP_MIN_FRAGMENT_SIZE;
caps->max_fragment_size = WM_ADSP_MAX_FRAGMENT_SIZE;
caps->min_fragments = WM_ADSP_MIN_FRAGMENTS;
caps->max_fragments = WM_ADSP_MAX_FRAGMENTS;
}
return 0;
}
EXPORT_SYMBOL_GPL(wm_adsp_compr_get_caps);
static inline int wm_adsp_buffer_read(struct wm_adsp_compr_buf *buf,
unsigned int field_offset, u32 *data)
{
return cs_dsp_read_data_word(&buf->dsp->cs_dsp, buf->host_buf_mem_type,
buf->host_buf_ptr + field_offset, data);
}
static inline int wm_adsp_buffer_write(struct wm_adsp_compr_buf *buf,
unsigned int field_offset, u32 data)
{
return cs_dsp_write_data_word(&buf->dsp->cs_dsp, buf->host_buf_mem_type,
buf->host_buf_ptr + field_offset,
data);
}
static int wm_adsp_buffer_populate(struct wm_adsp_compr_buf *buf)
{
const struct wm_adsp_fw_caps *caps = wm_adsp_fw[buf->dsp->fw].caps;
struct wm_adsp_buffer_region *region;
u32 offset = 0;
int i, ret;
buf->regions = kcalloc(caps->num_regions, sizeof(*buf->regions),
GFP_KERNEL);
if (!buf->regions)
return -ENOMEM;
for (i = 0; i < caps->num_regions; ++i) {
region = &buf->regions[i];
region->offset = offset;
region->mem_type = caps->region_defs[i].mem_type;
ret = wm_adsp_buffer_read(buf, caps->region_defs[i].base_offset,
®ion->base_addr);
if (ret < 0)
return ret;
ret = wm_adsp_buffer_read(buf, caps->region_defs[i].size_offset,
&offset);
if (ret < 0)
return ret;
region->cumulative_size = offset;
compr_dbg(buf,
"region=%d type=%d base=%08x off=%08x size=%08x\n",
i, region->mem_type, region->base_addr,
region->offset, region->cumulative_size);
}
return 0;
}
static void wm_adsp_buffer_clear(struct wm_adsp_compr_buf *buf)
{
buf->irq_count = 0xFFFFFFFF;
buf->read_index = -1;
buf->avail = 0;
}
static struct wm_adsp_compr_buf *wm_adsp_buffer_alloc(struct wm_adsp *dsp)
{
struct wm_adsp_compr_buf *buf;
buf = kzalloc(sizeof(*buf), GFP_KERNEL);
if (!buf)
return NULL;
buf->dsp = dsp;
wm_adsp_buffer_clear(buf);
return buf;
}
static int wm_adsp_buffer_parse_legacy(struct wm_adsp *dsp)
{
struct cs_dsp_alg_region *alg_region;
struct wm_adsp_compr_buf *buf;
u32 xmalg, addr, magic;
int i, ret;
alg_region = cs_dsp_find_alg_region(&dsp->cs_dsp, WMFW_ADSP2_XM, dsp->cs_dsp.fw_id);
if (!alg_region) {
adsp_err(dsp, "No algorithm region found\n");
return -EINVAL;
}
xmalg = dsp->sys_config_size / sizeof(__be32);
addr = alg_region->base + xmalg + ALG_XM_FIELD(magic);
ret = cs_dsp_read_data_word(&dsp->cs_dsp, WMFW_ADSP2_XM, addr, &magic);
if (ret < 0)
return ret;
if (magic != WM_ADSP_ALG_XM_STRUCT_MAGIC)
return -ENODEV;
buf = wm_adsp_buffer_alloc(dsp);
if (!buf)
return -ENOMEM;
addr = alg_region->base + xmalg + ALG_XM_FIELD(host_buf_ptr);
for (i = 0; i < 5; ++i) {
ret = cs_dsp_read_data_word(&dsp->cs_dsp, WMFW_ADSP2_XM, addr,
&buf->host_buf_ptr);
if (ret < 0)
goto err;
if (buf->host_buf_ptr)
break;
usleep_range(1000, 2000);
}
if (!buf->host_buf_ptr) {
ret = -EIO;
goto err;
}
buf->host_buf_mem_type = WMFW_ADSP2_XM;
ret = wm_adsp_buffer_populate(buf);
if (ret < 0)
goto err;
list_add_tail(&buf->list, &dsp->buffer_list);
compr_dbg(buf, "legacy host_buf_ptr=%x\n", buf->host_buf_ptr);
return 0;
err:
kfree(buf);
return ret;
}
static int wm_adsp_buffer_parse_coeff(struct cs_dsp_coeff_ctl *cs_ctl)
{
struct wm_adsp_host_buf_coeff_v1 coeff_v1;
struct wm_adsp_compr_buf *buf;
struct wm_adsp *dsp = container_of(cs_ctl->dsp, struct wm_adsp, cs_dsp);
unsigned int version = 0;
int ret, i;
for (i = 0; i < 5; ++i) {
ret = cs_dsp_coeff_read_ctrl(cs_ctl, 0, &coeff_v1,
min(cs_ctl->len, sizeof(coeff_v1)));
if (ret < 0)
return ret;
if (coeff_v1.host_buf_ptr)
break;
usleep_range(1000, 2000);
}
if (!coeff_v1.host_buf_ptr) {
adsp_err(dsp, "Failed to acquire host buffer\n");
return -EIO;
}
buf = wm_adsp_buffer_alloc(dsp);
if (!buf)
return -ENOMEM;
buf->host_buf_mem_type = cs_ctl->alg_region.type;
buf->host_buf_ptr = be32_to_cpu(coeff_v1.host_buf_ptr);
ret = wm_adsp_buffer_populate(buf);
if (ret < 0)
goto err;
/*
* v0 host_buffer coefficients didn't have versioning, so if the
* control is one word, assume version 0.
*/
if (cs_ctl->len == 4)
goto done;
version = be32_to_cpu(coeff_v1.versions) & HOST_BUF_COEFF_COMPAT_VER_MASK;
version >>= HOST_BUF_COEFF_COMPAT_VER_SHIFT;
if (version > HOST_BUF_COEFF_SUPPORTED_COMPAT_VER) {
adsp_err(dsp,
"Host buffer coeff ver %u > supported version %u\n",
version, HOST_BUF_COEFF_SUPPORTED_COMPAT_VER);
ret = -EINVAL;
goto err;
}
cs_dsp_remove_padding((u32 *)&coeff_v1.name, ARRAY_SIZE(coeff_v1.name));
buf->name = kasprintf(GFP_KERNEL, "%s-dsp-%s", dsp->part,
(char *)&coeff_v1.name);
done:
list_add_tail(&buf->list, &dsp->buffer_list);
compr_dbg(buf, "host_buf_ptr=%x coeff version %u\n",
buf->host_buf_ptr, version);
return version;
err:
kfree(buf);
return ret;
}
static int wm_adsp_buffer_init(struct wm_adsp *dsp)
{
struct cs_dsp_coeff_ctl *cs_ctl;
int ret;
list_for_each_entry(cs_ctl, &dsp->cs_dsp.ctl_list, list) {
if (cs_ctl->type != WMFW_CTL_TYPE_HOST_BUFFER)
continue;
if (!cs_ctl->enabled)
continue;
ret = wm_adsp_buffer_parse_coeff(cs_ctl);
if (ret < 0) {
adsp_err(dsp, "Failed to parse coeff: %d\n", ret);
goto error;
} else if (ret == 0) {
/* Only one buffer supported for version 0 */
return 0;
}
}
if (list_empty(&dsp->buffer_list)) {
/* Fall back to legacy support */
ret = wm_adsp_buffer_parse_legacy(dsp);
if (ret == -ENODEV)
adsp_info(dsp, "Legacy support not available\n");
else if (ret)
adsp_warn(dsp, "Failed to parse legacy: %d\n", ret);
}
return 0;
error:
wm_adsp_buffer_free(dsp);
return ret;
}
static int wm_adsp_buffer_free(struct wm_adsp *dsp)
{
struct wm_adsp_compr_buf *buf, *tmp;
list_for_each_entry_safe(buf, tmp, &dsp->buffer_list, list) {
wm_adsp_compr_detach(buf->compr);
kfree(buf->name);
kfree(buf->regions);
list_del(&buf->list);
kfree(buf);
}
return 0;
}
static int wm_adsp_buffer_get_error(struct wm_adsp_compr_buf *buf)
{
int ret;
ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(error), &buf->error);
if (ret < 0) {
compr_err(buf, "Failed to check buffer error: %d\n", ret);
return ret;
}
if (buf->error != 0) {
compr_err(buf, "Buffer error occurred: %d\n", buf->error);
return -EIO;
}
return 0;
}
int wm_adsp_compr_trigger(struct snd_soc_component *component,
struct snd_compr_stream *stream, int cmd)
{
struct wm_adsp_compr *compr = stream->runtime->private_data;
struct wm_adsp *dsp = compr->dsp;
int ret = 0;
compr_dbg(compr, "Trigger: %d\n", cmd);
mutex_lock(&dsp->cs_dsp.pwr_lock);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
if (!wm_adsp_compr_attached(compr)) {
ret = wm_adsp_compr_attach(compr);
if (ret < 0) {
compr_err(compr, "Failed to link buffer and stream: %d\n",
ret);
break;
}
}
ret = wm_adsp_buffer_get_error(compr->buf);
if (ret < 0)
break;
/* Trigger the IRQ at one fragment of data */
ret = wm_adsp_buffer_write(compr->buf,
HOST_BUFFER_FIELD(high_water_mark),
wm_adsp_compr_frag_words(compr));
if (ret < 0) {
compr_err(compr, "Failed to set high water mark: %d\n",
ret);
break;
}
break;
case SNDRV_PCM_TRIGGER_STOP:
if (wm_adsp_compr_attached(compr))
wm_adsp_buffer_clear(compr->buf);
break;
default:
ret = -EINVAL;
break;
}
mutex_unlock(&dsp->cs_dsp.pwr_lock);
return ret;
}
EXPORT_SYMBOL_GPL(wm_adsp_compr_trigger);
static inline int wm_adsp_buffer_size(struct wm_adsp_compr_buf *buf)
{
int last_region = wm_adsp_fw[buf->dsp->fw].caps->num_regions - 1;
return buf->regions[last_region].cumulative_size;
}
static int wm_adsp_buffer_update_avail(struct wm_adsp_compr_buf *buf)
{
u32 next_read_index, next_write_index;
int write_index, read_index, avail;
int ret;
/* Only sync read index if we haven't already read a valid index */
if (buf->read_index < 0) {
ret = wm_adsp_buffer_read(buf,
HOST_BUFFER_FIELD(next_read_index),
&next_read_index);
if (ret < 0)
return ret;
read_index = sign_extend32(next_read_index, 23);
if (read_index < 0) {
compr_dbg(buf, "Avail check on unstarted stream\n");
return 0;
}
buf->read_index = read_index;
}
ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(next_write_index),
&next_write_index);
if (ret < 0)
return ret;
write_index = sign_extend32(next_write_index, 23);
avail = write_index - buf->read_index;
if (avail < 0)
avail += wm_adsp_buffer_size(buf);
compr_dbg(buf, "readindex=0x%x, writeindex=0x%x, avail=%d\n",
buf->read_index, write_index, avail * CS_DSP_DATA_WORD_SIZE);
buf->avail = avail;
return 0;
}
int wm_adsp_compr_handle_irq(struct wm_adsp *dsp)
{
struct wm_adsp_compr_buf *buf;
struct wm_adsp_compr *compr;
int ret = 0;
mutex_lock(&dsp->cs_dsp.pwr_lock);
if (list_empty(&dsp->buffer_list)) {
ret = -ENODEV;
goto out;
}
adsp_dbg(dsp, "Handling buffer IRQ\n");
list_for_each_entry(buf, &dsp->buffer_list, list) {
compr = buf->compr;
ret = wm_adsp_buffer_get_error(buf);
if (ret < 0)
goto out_notify; /* Wake poll to report error */
ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(irq_count),
&buf->irq_count);
if (ret < 0) {
compr_err(buf, "Failed to get irq_count: %d\n", ret);
goto out;
}
ret = wm_adsp_buffer_update_avail(buf);
if (ret < 0) {
compr_err(buf, "Error reading avail: %d\n", ret);
goto out;
}
if (wm_adsp_fw[dsp->fw].voice_trigger && buf->irq_count == 2)
ret = WM_ADSP_COMPR_VOICE_TRIGGER;
out_notify:
if (compr && compr->stream)
snd_compr_fragment_elapsed(compr->stream);
}
out:
mutex_unlock(&dsp->cs_dsp.pwr_lock);
return ret;
}
EXPORT_SYMBOL_GPL(wm_adsp_compr_handle_irq);
static int wm_adsp_buffer_reenable_irq(struct wm_adsp_compr_buf *buf)
{
if (buf->irq_count & 0x01)
return 0;
compr_dbg(buf, "Enable IRQ(0x%x) for next fragment\n", buf->irq_count);
buf->irq_count |= 0x01;
return wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(irq_ack),
buf->irq_count);
}
int wm_adsp_compr_pointer(struct snd_soc_component *component,
struct snd_compr_stream *stream,
struct snd_compr_tstamp *tstamp)
{
struct wm_adsp_compr *compr = stream->runtime->private_data;
struct wm_adsp *dsp = compr->dsp;
struct wm_adsp_compr_buf *buf;
int ret = 0;
compr_dbg(compr, "Pointer request\n");
mutex_lock(&dsp->cs_dsp.pwr_lock);
buf = compr->buf;
if (dsp->fatal_error || !buf || buf->error) {
snd_compr_stop_error(stream, SNDRV_PCM_STATE_XRUN);
ret = -EIO;
goto out;
}
if (buf->avail < wm_adsp_compr_frag_words(compr)) {
ret = wm_adsp_buffer_update_avail(buf);
if (ret < 0) {
compr_err(compr, "Error reading avail: %d\n", ret);
goto out;
}
/*
* If we really have less than 1 fragment available tell the
* DSP to inform us once a whole fragment is available.
*/
if (buf->avail < wm_adsp_compr_frag_words(compr)) {
ret = wm_adsp_buffer_get_error(buf);
if (ret < 0) {
if (buf->error)
snd_compr_stop_error(stream,
SNDRV_PCM_STATE_XRUN);
goto out;
}
ret = wm_adsp_buffer_reenable_irq(buf);
if (ret < 0) {
compr_err(compr, "Failed to re-enable buffer IRQ: %d\n",
ret);
goto out;
}
}
}
tstamp->copied_total = compr->copied_total;
tstamp->copied_total += buf->avail * CS_DSP_DATA_WORD_SIZE;
tstamp->sampling_rate = compr->sample_rate;
out:
mutex_unlock(&dsp->cs_dsp.pwr_lock);
return ret;
}
EXPORT_SYMBOL_GPL(wm_adsp_compr_pointer);
static int wm_adsp_buffer_capture_block(struct wm_adsp_compr *compr, int target)
{
struct wm_adsp_compr_buf *buf = compr->buf;
unsigned int adsp_addr;
int mem_type, nwords, max_read;
int i, ret;
/* Calculate read parameters */
for (i = 0; i < wm_adsp_fw[buf->dsp->fw].caps->num_regions; ++i)
if (buf->read_index < buf->regions[i].cumulative_size)
break;
if (i == wm_adsp_fw[buf->dsp->fw].caps->num_regions)
return -EINVAL;
mem_type = buf->regions[i].mem_type;
adsp_addr = buf->regions[i].base_addr +
(buf->read_index - buf->regions[i].offset);
max_read = wm_adsp_compr_frag_words(compr);
nwords = buf->regions[i].cumulative_size - buf->read_index;
if (nwords > target)
nwords = target;
if (nwords > buf->avail)
nwords = buf->avail;
if (nwords > max_read)
nwords = max_read;
if (!nwords)
return 0;
/* Read data from DSP */
ret = cs_dsp_read_raw_data_block(&buf->dsp->cs_dsp, mem_type, adsp_addr,
nwords, (__be32 *)compr->raw_buf);
if (ret < 0)
return ret;
cs_dsp_remove_padding(compr->raw_buf, nwords);
/* update read index to account for words read */
buf->read_index += nwords;
if (buf->read_index == wm_adsp_buffer_size(buf))
buf->read_index = 0;
ret = wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(next_read_index),
buf->read_index);
if (ret < 0)
return ret;
/* update avail to account for words read */
buf->avail -= nwords;
return nwords;
}
static int wm_adsp_compr_read(struct wm_adsp_compr *compr,
char __user *buf, size_t count)
{
struct wm_adsp *dsp = compr->dsp;
int ntotal = 0;
int nwords, nbytes;
compr_dbg(compr, "Requested read of %zu bytes\n", count);
if (dsp->fatal_error || !compr->buf || compr->buf->error) {
snd_compr_stop_error(compr->stream, SNDRV_PCM_STATE_XRUN);
return -EIO;
}
count /= CS_DSP_DATA_WORD_SIZE;
do {
nwords = wm_adsp_buffer_capture_block(compr, count);
if (nwords < 0) {
compr_err(compr, "Failed to capture block: %d\n",
nwords);
return nwords;
}
nbytes = nwords * CS_DSP_DATA_WORD_SIZE;
compr_dbg(compr, "Read %d bytes\n", nbytes);
if (copy_to_user(buf + ntotal, compr->raw_buf, nbytes)) {
compr_err(compr, "Failed to copy data to user: %d, %d\n",
ntotal, nbytes);
return -EFAULT;
}
count -= nwords;
ntotal += nbytes;
} while (nwords > 0 && count > 0);
compr->copied_total += ntotal;
return ntotal;
}
int wm_adsp_compr_copy(struct snd_soc_component *component,
struct snd_compr_stream *stream, char __user *buf,
size_t count)
{
struct wm_adsp_compr *compr = stream->runtime->private_data;
struct wm_adsp *dsp = compr->dsp;
int ret;
mutex_lock(&dsp->cs_dsp.pwr_lock);
if (stream->direction == SND_COMPRESS_CAPTURE)
ret = wm_adsp_compr_read(compr, buf, count);
else
ret = -ENOTSUPP;
mutex_unlock(&dsp->cs_dsp.pwr_lock);
return ret;
}
EXPORT_SYMBOL_GPL(wm_adsp_compr_copy);
static void wm_adsp_fatal_error(struct cs_dsp *cs_dsp)
{
struct wm_adsp *dsp = container_of(cs_dsp, struct wm_adsp, cs_dsp);
struct wm_adsp_compr *compr;
dsp->fatal_error = true;
list_for_each_entry(compr, &dsp->compr_list, list) {
if (compr->stream)
snd_compr_fragment_elapsed(compr->stream);
}
}
irqreturn_t wm_adsp2_bus_error(int irq, void *data)
{
struct wm_adsp *dsp = (struct wm_adsp *)data;
cs_dsp_adsp2_bus_error(&dsp->cs_dsp);
return IRQ_HANDLED;
}
EXPORT_SYMBOL_GPL(wm_adsp2_bus_error);
irqreturn_t wm_halo_bus_error(int irq, void *data)
{
struct wm_adsp *dsp = (struct wm_adsp *)data;
cs_dsp_halo_bus_error(&dsp->cs_dsp);
return IRQ_HANDLED;
}
EXPORT_SYMBOL_GPL(wm_halo_bus_error);
irqreturn_t wm_halo_wdt_expire(int irq, void *data)
{
struct wm_adsp *dsp = data;
cs_dsp_halo_wdt_expire(&dsp->cs_dsp);
return IRQ_HANDLED;
}
EXPORT_SYMBOL_GPL(wm_halo_wdt_expire);
static const struct cs_dsp_client_ops wm_adsp1_client_ops = {
.control_add = wm_adsp_control_add,
.control_remove = wm_adsp_control_remove,
};
static const struct cs_dsp_client_ops wm_adsp2_client_ops = {
.control_add = wm_adsp_control_add,
.control_remove = wm_adsp_control_remove,
.pre_run = wm_adsp_pre_run,
.post_run = wm_adsp_event_post_run,
.post_stop = wm_adsp_event_post_stop,
.watchdog_expired = wm_adsp_fatal_error,
};
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(FW_CS_DSP);
| linux-master | sound/soc/codecs/wm_adsp.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2015-2017, The Linux Foundation.
// Copyright (c) 2019, Linaro Limited
#include <linux/bitops.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/soundwire/sdw.h>
#include <linux/soundwire/sdw_registers.h>
#include <linux/soundwire/sdw_type.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#define WSA881X_DIGITAL_BASE 0x3000
#define WSA881X_ANALOG_BASE 0x3100
/* Digital register address space */
#define WSA881X_CHIP_ID0 (WSA881X_DIGITAL_BASE + 0x0000)
#define WSA881X_CHIP_ID1 (WSA881X_DIGITAL_BASE + 0x0001)
#define WSA881X_CHIP_ID2 (WSA881X_DIGITAL_BASE + 0x0002)
#define WSA881X_CHIP_ID3 (WSA881X_DIGITAL_BASE + 0x0003)
#define WSA881X_BUS_ID (WSA881X_DIGITAL_BASE + 0x0004)
#define WSA881X_CDC_RST_CTL (WSA881X_DIGITAL_BASE + 0x0005)
#define WSA881X_CDC_TOP_CLK_CTL (WSA881X_DIGITAL_BASE + 0x0006)
#define WSA881X_CDC_ANA_CLK_CTL (WSA881X_DIGITAL_BASE + 0x0007)
#define WSA881X_CDC_DIG_CLK_CTL (WSA881X_DIGITAL_BASE + 0x0008)
#define WSA881X_CLOCK_CONFIG (WSA881X_DIGITAL_BASE + 0x0009)
#define WSA881X_ANA_CTL (WSA881X_DIGITAL_BASE + 0x000A)
#define WSA881X_SWR_RESET_EN (WSA881X_DIGITAL_BASE + 0x000B)
#define WSA881X_RESET_CTL (WSA881X_DIGITAL_BASE + 0x000C)
#define WSA881X_TADC_VALUE_CTL (WSA881X_DIGITAL_BASE + 0x000F)
#define WSA881X_TEMP_DETECT_CTL (WSA881X_DIGITAL_BASE + 0x0010)
#define WSA881X_TEMP_MSB (WSA881X_DIGITAL_BASE + 0x0011)
#define WSA881X_TEMP_LSB (WSA881X_DIGITAL_BASE + 0x0012)
#define WSA881X_TEMP_CONFIG0 (WSA881X_DIGITAL_BASE + 0x0013)
#define WSA881X_TEMP_CONFIG1 (WSA881X_DIGITAL_BASE + 0x0014)
#define WSA881X_CDC_CLIP_CTL (WSA881X_DIGITAL_BASE + 0x0015)
#define WSA881X_SDM_PDM9_LSB (WSA881X_DIGITAL_BASE + 0x0016)
#define WSA881X_SDM_PDM9_MSB (WSA881X_DIGITAL_BASE + 0x0017)
#define WSA881X_CDC_RX_CTL (WSA881X_DIGITAL_BASE + 0x0018)
#define WSA881X_DEM_BYPASS_DATA0 (WSA881X_DIGITAL_BASE + 0x0019)
#define WSA881X_DEM_BYPASS_DATA1 (WSA881X_DIGITAL_BASE + 0x001A)
#define WSA881X_DEM_BYPASS_DATA2 (WSA881X_DIGITAL_BASE + 0x001B)
#define WSA881X_DEM_BYPASS_DATA3 (WSA881X_DIGITAL_BASE + 0x001C)
#define WSA881X_OTP_CTRL0 (WSA881X_DIGITAL_BASE + 0x001D)
#define WSA881X_OTP_CTRL1 (WSA881X_DIGITAL_BASE + 0x001E)
#define WSA881X_HDRIVE_CTL_GROUP1 (WSA881X_DIGITAL_BASE + 0x001F)
#define WSA881X_INTR_MODE (WSA881X_DIGITAL_BASE + 0x0020)
#define WSA881X_INTR_MASK (WSA881X_DIGITAL_BASE + 0x0021)
#define WSA881X_INTR_STATUS (WSA881X_DIGITAL_BASE + 0x0022)
#define WSA881X_INTR_CLEAR (WSA881X_DIGITAL_BASE + 0x0023)
#define WSA881X_INTR_LEVEL (WSA881X_DIGITAL_BASE + 0x0024)
#define WSA881X_INTR_SET (WSA881X_DIGITAL_BASE + 0x0025)
#define WSA881X_INTR_TEST (WSA881X_DIGITAL_BASE + 0x0026)
#define WSA881X_PDM_TEST_MODE (WSA881X_DIGITAL_BASE + 0x0030)
#define WSA881X_ATE_TEST_MODE (WSA881X_DIGITAL_BASE + 0x0031)
#define WSA881X_PIN_CTL_MODE (WSA881X_DIGITAL_BASE + 0x0032)
#define WSA881X_PIN_CTL_OE (WSA881X_DIGITAL_BASE + 0x0033)
#define WSA881X_PIN_WDATA_IOPAD (WSA881X_DIGITAL_BASE + 0x0034)
#define WSA881X_PIN_STATUS (WSA881X_DIGITAL_BASE + 0x0035)
#define WSA881X_DIG_DEBUG_MODE (WSA881X_DIGITAL_BASE + 0x0037)
#define WSA881X_DIG_DEBUG_SEL (WSA881X_DIGITAL_BASE + 0x0038)
#define WSA881X_DIG_DEBUG_EN (WSA881X_DIGITAL_BASE + 0x0039)
#define WSA881X_SWR_HM_TEST1 (WSA881X_DIGITAL_BASE + 0x003B)
#define WSA881X_SWR_HM_TEST2 (WSA881X_DIGITAL_BASE + 0x003C)
#define WSA881X_TEMP_DETECT_DBG_CTL (WSA881X_DIGITAL_BASE + 0x003D)
#define WSA881X_TEMP_DEBUG_MSB (WSA881X_DIGITAL_BASE + 0x003E)
#define WSA881X_TEMP_DEBUG_LSB (WSA881X_DIGITAL_BASE + 0x003F)
#define WSA881X_SAMPLE_EDGE_SEL (WSA881X_DIGITAL_BASE + 0x0044)
#define WSA881X_IOPAD_CTL (WSA881X_DIGITAL_BASE + 0x0045)
#define WSA881X_SPARE_0 (WSA881X_DIGITAL_BASE + 0x0050)
#define WSA881X_SPARE_1 (WSA881X_DIGITAL_BASE + 0x0051)
#define WSA881X_SPARE_2 (WSA881X_DIGITAL_BASE + 0x0052)
#define WSA881X_OTP_REG_0 (WSA881X_DIGITAL_BASE + 0x0080)
#define WSA881X_OTP_REG_1 (WSA881X_DIGITAL_BASE + 0x0081)
#define WSA881X_OTP_REG_2 (WSA881X_DIGITAL_BASE + 0x0082)
#define WSA881X_OTP_REG_3 (WSA881X_DIGITAL_BASE + 0x0083)
#define WSA881X_OTP_REG_4 (WSA881X_DIGITAL_BASE + 0x0084)
#define WSA881X_OTP_REG_5 (WSA881X_DIGITAL_BASE + 0x0085)
#define WSA881X_OTP_REG_6 (WSA881X_DIGITAL_BASE + 0x0086)
#define WSA881X_OTP_REG_7 (WSA881X_DIGITAL_BASE + 0x0087)
#define WSA881X_OTP_REG_8 (WSA881X_DIGITAL_BASE + 0x0088)
#define WSA881X_OTP_REG_9 (WSA881X_DIGITAL_BASE + 0x0089)
#define WSA881X_OTP_REG_10 (WSA881X_DIGITAL_BASE + 0x008A)
#define WSA881X_OTP_REG_11 (WSA881X_DIGITAL_BASE + 0x008B)
#define WSA881X_OTP_REG_12 (WSA881X_DIGITAL_BASE + 0x008C)
#define WSA881X_OTP_REG_13 (WSA881X_DIGITAL_BASE + 0x008D)
#define WSA881X_OTP_REG_14 (WSA881X_DIGITAL_BASE + 0x008E)
#define WSA881X_OTP_REG_15 (WSA881X_DIGITAL_BASE + 0x008F)
#define WSA881X_OTP_REG_16 (WSA881X_DIGITAL_BASE + 0x0090)
#define WSA881X_OTP_REG_17 (WSA881X_DIGITAL_BASE + 0x0091)
#define WSA881X_OTP_REG_18 (WSA881X_DIGITAL_BASE + 0x0092)
#define WSA881X_OTP_REG_19 (WSA881X_DIGITAL_BASE + 0x0093)
#define WSA881X_OTP_REG_20 (WSA881X_DIGITAL_BASE + 0x0094)
#define WSA881X_OTP_REG_21 (WSA881X_DIGITAL_BASE + 0x0095)
#define WSA881X_OTP_REG_22 (WSA881X_DIGITAL_BASE + 0x0096)
#define WSA881X_OTP_REG_23 (WSA881X_DIGITAL_BASE + 0x0097)
#define WSA881X_OTP_REG_24 (WSA881X_DIGITAL_BASE + 0x0098)
#define WSA881X_OTP_REG_25 (WSA881X_DIGITAL_BASE + 0x0099)
#define WSA881X_OTP_REG_26 (WSA881X_DIGITAL_BASE + 0x009A)
#define WSA881X_OTP_REG_27 (WSA881X_DIGITAL_BASE + 0x009B)
#define WSA881X_OTP_REG_28 (WSA881X_DIGITAL_BASE + 0x009C)
#define WSA881X_OTP_REG_29 (WSA881X_DIGITAL_BASE + 0x009D)
#define WSA881X_OTP_REG_30 (WSA881X_DIGITAL_BASE + 0x009E)
#define WSA881X_OTP_REG_31 (WSA881X_DIGITAL_BASE + 0x009F)
#define WSA881X_OTP_REG_63 (WSA881X_DIGITAL_BASE + 0x00BF)
/* Analog Register address space */
#define WSA881X_BIAS_REF_CTRL (WSA881X_ANALOG_BASE + 0x0000)
#define WSA881X_BIAS_TEST (WSA881X_ANALOG_BASE + 0x0001)
#define WSA881X_BIAS_BIAS (WSA881X_ANALOG_BASE + 0x0002)
#define WSA881X_TEMP_OP (WSA881X_ANALOG_BASE + 0x0003)
#define WSA881X_TEMP_IREF_CTRL (WSA881X_ANALOG_BASE + 0x0004)
#define WSA881X_TEMP_ISENS_CTRL (WSA881X_ANALOG_BASE + 0x0005)
#define WSA881X_TEMP_CLK_CTRL (WSA881X_ANALOG_BASE + 0x0006)
#define WSA881X_TEMP_TEST (WSA881X_ANALOG_BASE + 0x0007)
#define WSA881X_TEMP_BIAS (WSA881X_ANALOG_BASE + 0x0008)
#define WSA881X_TEMP_ADC_CTRL (WSA881X_ANALOG_BASE + 0x0009)
#define WSA881X_TEMP_DOUT_MSB (WSA881X_ANALOG_BASE + 0x000A)
#define WSA881X_TEMP_DOUT_LSB (WSA881X_ANALOG_BASE + 0x000B)
#define WSA881X_ADC_EN_MODU_V (WSA881X_ANALOG_BASE + 0x0010)
#define WSA881X_ADC_EN_MODU_I (WSA881X_ANALOG_BASE + 0x0011)
#define WSA881X_ADC_EN_DET_TEST_V (WSA881X_ANALOG_BASE + 0x0012)
#define WSA881X_ADC_EN_DET_TEST_I (WSA881X_ANALOG_BASE + 0x0013)
#define WSA881X_ADC_SEL_IBIAS (WSA881X_ANALOG_BASE + 0x0014)
#define WSA881X_ADC_EN_SEL_IBAIS (WSA881X_ANALOG_BASE + 0x0015)
#define WSA881X_SPKR_DRV_EN (WSA881X_ANALOG_BASE + 0x001A)
#define WSA881X_SPKR_DRV_GAIN (WSA881X_ANALOG_BASE + 0x001B)
#define WSA881X_PA_GAIN_SEL_MASK BIT(3)
#define WSA881X_PA_GAIN_SEL_REG BIT(3)
#define WSA881X_PA_GAIN_SEL_DRE 0
#define WSA881X_SPKR_PAG_GAIN_MASK GENMASK(7, 4)
#define WSA881X_SPKR_DAC_CTL (WSA881X_ANALOG_BASE + 0x001C)
#define WSA881X_SPKR_DRV_DBG (WSA881X_ANALOG_BASE + 0x001D)
#define WSA881X_SPKR_PWRSTG_DBG (WSA881X_ANALOG_BASE + 0x001E)
#define WSA881X_SPKR_OCP_CTL (WSA881X_ANALOG_BASE + 0x001F)
#define WSA881X_SPKR_OCP_MASK GENMASK(7, 6)
#define WSA881X_SPKR_OCP_EN BIT(7)
#define WSA881X_SPKR_OCP_HOLD BIT(6)
#define WSA881X_SPKR_CLIP_CTL (WSA881X_ANALOG_BASE + 0x0020)
#define WSA881X_SPKR_BBM_CTL (WSA881X_ANALOG_BASE + 0x0021)
#define WSA881X_SPKR_MISC_CTL1 (WSA881X_ANALOG_BASE + 0x0022)
#define WSA881X_SPKR_MISC_CTL2 (WSA881X_ANALOG_BASE + 0x0023)
#define WSA881X_SPKR_BIAS_INT (WSA881X_ANALOG_BASE + 0x0024)
#define WSA881X_SPKR_PA_INT (WSA881X_ANALOG_BASE + 0x0025)
#define WSA881X_SPKR_BIAS_CAL (WSA881X_ANALOG_BASE + 0x0026)
#define WSA881X_SPKR_BIAS_PSRR (WSA881X_ANALOG_BASE + 0x0027)
#define WSA881X_SPKR_STATUS1 (WSA881X_ANALOG_BASE + 0x0028)
#define WSA881X_SPKR_STATUS2 (WSA881X_ANALOG_BASE + 0x0029)
#define WSA881X_BOOST_EN_CTL (WSA881X_ANALOG_BASE + 0x002A)
#define WSA881X_BOOST_EN_MASK BIT(7)
#define WSA881X_BOOST_EN BIT(7)
#define WSA881X_BOOST_CURRENT_LIMIT (WSA881X_ANALOG_BASE + 0x002B)
#define WSA881X_BOOST_PS_CTL (WSA881X_ANALOG_BASE + 0x002C)
#define WSA881X_BOOST_PRESET_OUT1 (WSA881X_ANALOG_BASE + 0x002D)
#define WSA881X_BOOST_PRESET_OUT2 (WSA881X_ANALOG_BASE + 0x002E)
#define WSA881X_BOOST_FORCE_OUT (WSA881X_ANALOG_BASE + 0x002F)
#define WSA881X_BOOST_LDO_PROG (WSA881X_ANALOG_BASE + 0x0030)
#define WSA881X_BOOST_SLOPE_COMP_ISENSE_FB (WSA881X_ANALOG_BASE + 0x0031)
#define WSA881X_BOOST_RON_CTL (WSA881X_ANALOG_BASE + 0x0032)
#define WSA881X_BOOST_LOOP_STABILITY (WSA881X_ANALOG_BASE + 0x0033)
#define WSA881X_BOOST_ZX_CTL (WSA881X_ANALOG_BASE + 0x0034)
#define WSA881X_BOOST_START_CTL (WSA881X_ANALOG_BASE + 0x0035)
#define WSA881X_BOOST_MISC1_CTL (WSA881X_ANALOG_BASE + 0x0036)
#define WSA881X_BOOST_MISC2_CTL (WSA881X_ANALOG_BASE + 0x0037)
#define WSA881X_BOOST_MISC3_CTL (WSA881X_ANALOG_BASE + 0x0038)
#define WSA881X_BOOST_ATEST_CTL (WSA881X_ANALOG_BASE + 0x0039)
#define WSA881X_SPKR_PROT_FE_GAIN (WSA881X_ANALOG_BASE + 0x003A)
#define WSA881X_SPKR_PROT_FE_CM_LDO_SET (WSA881X_ANALOG_BASE + 0x003B)
#define WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1 (WSA881X_ANALOG_BASE + 0x003C)
#define WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2 (WSA881X_ANALOG_BASE + 0x003D)
#define WSA881X_SPKR_PROT_ATEST1 (WSA881X_ANALOG_BASE + 0x003E)
#define WSA881X_SPKR_PROT_ATEST2 (WSA881X_ANALOG_BASE + 0x003F)
#define WSA881X_SPKR_PROT_FE_VSENSE_VCM (WSA881X_ANALOG_BASE + 0x0040)
#define WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1 (WSA881X_ANALOG_BASE + 0x0041)
#define WSA881X_BONGO_RESRV_REG1 (WSA881X_ANALOG_BASE + 0x0042)
#define WSA881X_BONGO_RESRV_REG2 (WSA881X_ANALOG_BASE + 0x0043)
#define WSA881X_SPKR_PROT_SAR (WSA881X_ANALOG_BASE + 0x0044)
#define WSA881X_SPKR_STATUS3 (WSA881X_ANALOG_BASE + 0x0045)
#define SWRS_SCP_FRAME_CTRL_BANK(m) (0x60 + 0x10 * (m))
#define SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(m) (0xE0 + 0x10 * (m))
#define SWR_SLV_MAX_REG_ADDR 0x390
#define SWR_SLV_START_REG_ADDR 0x40
#define SWR_SLV_MAX_BUF_LEN 20
#define BYTES_PER_LINE 12
#define SWR_SLV_RD_BUF_LEN 8
#define SWR_SLV_WR_BUF_LEN 32
#define SWR_SLV_MAX_DEVICES 2
#define WSA881X_MAX_SWR_PORTS 4
#define WSA881X_VERSION_ENTRY_SIZE 27
#define WSA881X_OCP_CTL_TIMER_SEC 2
#define WSA881X_OCP_CTL_TEMP_CELSIUS 25
#define WSA881X_OCP_CTL_POLL_TIMER_SEC 60
#define WSA881X_PROBE_TIMEOUT 1000
#define WSA881X_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
SNDRV_CTL_ELEM_ACCESS_READWRITE,\
.tlv.p = (tlv_array), \
.info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
.put = wsa881x_put_pa_gain, \
.private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) }
static struct reg_default wsa881x_defaults[] = {
{ WSA881X_CHIP_ID0, 0x00 },
{ WSA881X_CHIP_ID1, 0x00 },
{ WSA881X_CHIP_ID2, 0x00 },
{ WSA881X_CHIP_ID3, 0x02 },
{ WSA881X_BUS_ID, 0x00 },
{ WSA881X_CDC_RST_CTL, 0x00 },
{ WSA881X_CDC_TOP_CLK_CTL, 0x03 },
{ WSA881X_CDC_ANA_CLK_CTL, 0x00 },
{ WSA881X_CDC_DIG_CLK_CTL, 0x00 },
{ WSA881X_CLOCK_CONFIG, 0x00 },
{ WSA881X_ANA_CTL, 0x08 },
{ WSA881X_SWR_RESET_EN, 0x00 },
{ WSA881X_TEMP_DETECT_CTL, 0x01 },
{ WSA881X_TEMP_MSB, 0x00 },
{ WSA881X_TEMP_LSB, 0x00 },
{ WSA881X_TEMP_CONFIG0, 0x00 },
{ WSA881X_TEMP_CONFIG1, 0x00 },
{ WSA881X_CDC_CLIP_CTL, 0x03 },
{ WSA881X_SDM_PDM9_LSB, 0x00 },
{ WSA881X_SDM_PDM9_MSB, 0x00 },
{ WSA881X_CDC_RX_CTL, 0x7E },
{ WSA881X_DEM_BYPASS_DATA0, 0x00 },
{ WSA881X_DEM_BYPASS_DATA1, 0x00 },
{ WSA881X_DEM_BYPASS_DATA2, 0x00 },
{ WSA881X_DEM_BYPASS_DATA3, 0x00 },
{ WSA881X_OTP_CTRL0, 0x00 },
{ WSA881X_OTP_CTRL1, 0x00 },
{ WSA881X_HDRIVE_CTL_GROUP1, 0x00 },
{ WSA881X_INTR_MODE, 0x00 },
{ WSA881X_INTR_STATUS, 0x00 },
{ WSA881X_INTR_CLEAR, 0x00 },
{ WSA881X_INTR_LEVEL, 0x00 },
{ WSA881X_INTR_SET, 0x00 },
{ WSA881X_INTR_TEST, 0x00 },
{ WSA881X_PDM_TEST_MODE, 0x00 },
{ WSA881X_ATE_TEST_MODE, 0x00 },
{ WSA881X_PIN_CTL_MODE, 0x00 },
{ WSA881X_PIN_CTL_OE, 0x00 },
{ WSA881X_PIN_WDATA_IOPAD, 0x00 },
{ WSA881X_PIN_STATUS, 0x00 },
{ WSA881X_DIG_DEBUG_MODE, 0x00 },
{ WSA881X_DIG_DEBUG_SEL, 0x00 },
{ WSA881X_DIG_DEBUG_EN, 0x00 },
{ WSA881X_SWR_HM_TEST1, 0x08 },
{ WSA881X_SWR_HM_TEST2, 0x00 },
{ WSA881X_TEMP_DETECT_DBG_CTL, 0x00 },
{ WSA881X_TEMP_DEBUG_MSB, 0x00 },
{ WSA881X_TEMP_DEBUG_LSB, 0x00 },
{ WSA881X_SAMPLE_EDGE_SEL, 0x0C },
{ WSA881X_SPARE_0, 0x00 },
{ WSA881X_SPARE_1, 0x00 },
{ WSA881X_SPARE_2, 0x00 },
{ WSA881X_OTP_REG_0, 0x01 },
{ WSA881X_OTP_REG_1, 0xFF },
{ WSA881X_OTP_REG_2, 0xC0 },
{ WSA881X_OTP_REG_3, 0xFF },
{ WSA881X_OTP_REG_4, 0xC0 },
{ WSA881X_OTP_REG_5, 0xFF },
{ WSA881X_OTP_REG_6, 0xFF },
{ WSA881X_OTP_REG_7, 0xFF },
{ WSA881X_OTP_REG_8, 0xFF },
{ WSA881X_OTP_REG_9, 0xFF },
{ WSA881X_OTP_REG_10, 0xFF },
{ WSA881X_OTP_REG_11, 0xFF },
{ WSA881X_OTP_REG_12, 0xFF },
{ WSA881X_OTP_REG_13, 0xFF },
{ WSA881X_OTP_REG_14, 0xFF },
{ WSA881X_OTP_REG_15, 0xFF },
{ WSA881X_OTP_REG_16, 0xFF },
{ WSA881X_OTP_REG_17, 0xFF },
{ WSA881X_OTP_REG_18, 0xFF },
{ WSA881X_OTP_REG_19, 0xFF },
{ WSA881X_OTP_REG_20, 0xFF },
{ WSA881X_OTP_REG_21, 0xFF },
{ WSA881X_OTP_REG_22, 0xFF },
{ WSA881X_OTP_REG_23, 0xFF },
{ WSA881X_OTP_REG_24, 0x03 },
{ WSA881X_OTP_REG_25, 0x01 },
{ WSA881X_OTP_REG_26, 0x03 },
{ WSA881X_OTP_REG_27, 0x11 },
{ WSA881X_OTP_REG_63, 0x40 },
/* WSA881x Analog registers */
{ WSA881X_BIAS_REF_CTRL, 0x6C },
{ WSA881X_BIAS_TEST, 0x16 },
{ WSA881X_BIAS_BIAS, 0xF0 },
{ WSA881X_TEMP_OP, 0x00 },
{ WSA881X_TEMP_IREF_CTRL, 0x56 },
{ WSA881X_TEMP_ISENS_CTRL, 0x47 },
{ WSA881X_TEMP_CLK_CTRL, 0x87 },
{ WSA881X_TEMP_TEST, 0x00 },
{ WSA881X_TEMP_BIAS, 0x51 },
{ WSA881X_TEMP_DOUT_MSB, 0x00 },
{ WSA881X_TEMP_DOUT_LSB, 0x00 },
{ WSA881X_ADC_EN_MODU_V, 0x00 },
{ WSA881X_ADC_EN_MODU_I, 0x00 },
{ WSA881X_ADC_EN_DET_TEST_V, 0x00 },
{ WSA881X_ADC_EN_DET_TEST_I, 0x00 },
{ WSA881X_ADC_EN_SEL_IBAIS, 0x10 },
{ WSA881X_SPKR_DRV_EN, 0x74 },
{ WSA881X_SPKR_DRV_DBG, 0x15 },
{ WSA881X_SPKR_PWRSTG_DBG, 0x00 },
{ WSA881X_SPKR_OCP_CTL, 0xD4 },
{ WSA881X_SPKR_CLIP_CTL, 0x90 },
{ WSA881X_SPKR_PA_INT, 0x54 },
{ WSA881X_SPKR_BIAS_CAL, 0xAC },
{ WSA881X_SPKR_STATUS1, 0x00 },
{ WSA881X_SPKR_STATUS2, 0x00 },
{ WSA881X_BOOST_EN_CTL, 0x18 },
{ WSA881X_BOOST_CURRENT_LIMIT, 0x7A },
{ WSA881X_BOOST_PRESET_OUT2, 0x70 },
{ WSA881X_BOOST_FORCE_OUT, 0x0E },
{ WSA881X_BOOST_LDO_PROG, 0x16 },
{ WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, 0x71 },
{ WSA881X_BOOST_RON_CTL, 0x0F },
{ WSA881X_BOOST_ZX_CTL, 0x34 },
{ WSA881X_BOOST_START_CTL, 0x23 },
{ WSA881X_BOOST_MISC1_CTL, 0x80 },
{ WSA881X_BOOST_MISC2_CTL, 0x00 },
{ WSA881X_BOOST_MISC3_CTL, 0x00 },
{ WSA881X_BOOST_ATEST_CTL, 0x00 },
{ WSA881X_SPKR_PROT_FE_GAIN, 0x46 },
{ WSA881X_SPKR_PROT_FE_CM_LDO_SET, 0x3B },
{ WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1, 0x8D },
{ WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2, 0x8D },
{ WSA881X_SPKR_PROT_ATEST1, 0x01 },
{ WSA881X_SPKR_PROT_FE_VSENSE_VCM, 0x8D },
{ WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1, 0x4D },
{ WSA881X_SPKR_PROT_SAR, 0x00 },
{ WSA881X_SPKR_STATUS3, 0x00 },
};
static const struct reg_sequence wsa881x_pre_pmu_pa_2_0[] = {
{ WSA881X_SPKR_DRV_GAIN, 0x41, 0 },
{ WSA881X_SPKR_MISC_CTL1, 0x87, 0 },
};
static const struct reg_sequence wsa881x_vi_txfe_en_2_0[] = {
{ WSA881X_SPKR_PROT_FE_VSENSE_VCM, 0x85, 0 },
{ WSA881X_SPKR_PROT_ATEST2, 0x0A, 0 },
{ WSA881X_SPKR_PROT_FE_GAIN, 0x47, 0 },
};
/* Default register reset values for WSA881x rev 2.0 */
static struct reg_sequence wsa881x_rev_2_0[] = {
{ WSA881X_RESET_CTL, 0x00, 0x00 },
{ WSA881X_TADC_VALUE_CTL, 0x01, 0x00 },
{ WSA881X_INTR_MASK, 0x1B, 0x00 },
{ WSA881X_IOPAD_CTL, 0x00, 0x00 },
{ WSA881X_OTP_REG_28, 0x3F, 0x00 },
{ WSA881X_OTP_REG_29, 0x3F, 0x00 },
{ WSA881X_OTP_REG_30, 0x01, 0x00 },
{ WSA881X_OTP_REG_31, 0x01, 0x00 },
{ WSA881X_TEMP_ADC_CTRL, 0x03, 0x00 },
{ WSA881X_ADC_SEL_IBIAS, 0x45, 0x00 },
{ WSA881X_SPKR_DRV_GAIN, 0xC1, 0x00 },
{ WSA881X_SPKR_DAC_CTL, 0x42, 0x00 },
{ WSA881X_SPKR_BBM_CTL, 0x02, 0x00 },
{ WSA881X_SPKR_MISC_CTL1, 0x40, 0x00 },
{ WSA881X_SPKR_MISC_CTL2, 0x07, 0x00 },
{ WSA881X_SPKR_BIAS_INT, 0x5F, 0x00 },
{ WSA881X_SPKR_BIAS_PSRR, 0x44, 0x00 },
{ WSA881X_BOOST_PS_CTL, 0xA0, 0x00 },
{ WSA881X_BOOST_PRESET_OUT1, 0xB7, 0x00 },
{ WSA881X_BOOST_LOOP_STABILITY, 0x8D, 0x00 },
{ WSA881X_SPKR_PROT_ATEST2, 0x02, 0x00 },
{ WSA881X_BONGO_RESRV_REG1, 0x5E, 0x00 },
{ WSA881X_BONGO_RESRV_REG2, 0x07, 0x00 },
};
enum wsa_port_ids {
WSA881X_PORT_DAC,
WSA881X_PORT_COMP,
WSA881X_PORT_BOOST,
WSA881X_PORT_VISENSE,
};
/* 4 ports */
static struct sdw_dpn_prop wsa_sink_dpn_prop[WSA881X_MAX_SWR_PORTS] = {
{
/* DAC */
.num = 1,
.type = SDW_DPN_SIMPLE,
.min_ch = 1,
.max_ch = 1,
.simple_ch_prep_sm = true,
.read_only_wordlength = true,
}, {
/* COMP */
.num = 2,
.type = SDW_DPN_SIMPLE,
.min_ch = 1,
.max_ch = 1,
.simple_ch_prep_sm = true,
.read_only_wordlength = true,
}, {
/* BOOST */
.num = 3,
.type = SDW_DPN_SIMPLE,
.min_ch = 1,
.max_ch = 1,
.simple_ch_prep_sm = true,
.read_only_wordlength = true,
}, {
/* VISENSE */
.num = 4,
.type = SDW_DPN_SIMPLE,
.min_ch = 1,
.max_ch = 1,
.simple_ch_prep_sm = true,
.read_only_wordlength = true,
}
};
static const struct sdw_port_config wsa881x_pconfig[WSA881X_MAX_SWR_PORTS] = {
{
.num = 1,
.ch_mask = 0x1,
}, {
.num = 2,
.ch_mask = 0xf,
}, {
.num = 3,
.ch_mask = 0x3,
}, { /* IV feedback */
.num = 4,
.ch_mask = 0x3,
},
};
static bool wsa881x_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case WSA881X_CHIP_ID0:
case WSA881X_CHIP_ID1:
case WSA881X_CHIP_ID2:
case WSA881X_CHIP_ID3:
case WSA881X_BUS_ID:
case WSA881X_CDC_RST_CTL:
case WSA881X_CDC_TOP_CLK_CTL:
case WSA881X_CDC_ANA_CLK_CTL:
case WSA881X_CDC_DIG_CLK_CTL:
case WSA881X_CLOCK_CONFIG:
case WSA881X_ANA_CTL:
case WSA881X_SWR_RESET_EN:
case WSA881X_RESET_CTL:
case WSA881X_TADC_VALUE_CTL:
case WSA881X_TEMP_DETECT_CTL:
case WSA881X_TEMP_MSB:
case WSA881X_TEMP_LSB:
case WSA881X_TEMP_CONFIG0:
case WSA881X_TEMP_CONFIG1:
case WSA881X_CDC_CLIP_CTL:
case WSA881X_SDM_PDM9_LSB:
case WSA881X_SDM_PDM9_MSB:
case WSA881X_CDC_RX_CTL:
case WSA881X_DEM_BYPASS_DATA0:
case WSA881X_DEM_BYPASS_DATA1:
case WSA881X_DEM_BYPASS_DATA2:
case WSA881X_DEM_BYPASS_DATA3:
case WSA881X_OTP_CTRL0:
case WSA881X_OTP_CTRL1:
case WSA881X_HDRIVE_CTL_GROUP1:
case WSA881X_INTR_MODE:
case WSA881X_INTR_MASK:
case WSA881X_INTR_STATUS:
case WSA881X_INTR_CLEAR:
case WSA881X_INTR_LEVEL:
case WSA881X_INTR_SET:
case WSA881X_INTR_TEST:
case WSA881X_PDM_TEST_MODE:
case WSA881X_ATE_TEST_MODE:
case WSA881X_PIN_CTL_MODE:
case WSA881X_PIN_CTL_OE:
case WSA881X_PIN_WDATA_IOPAD:
case WSA881X_PIN_STATUS:
case WSA881X_DIG_DEBUG_MODE:
case WSA881X_DIG_DEBUG_SEL:
case WSA881X_DIG_DEBUG_EN:
case WSA881X_SWR_HM_TEST1:
case WSA881X_SWR_HM_TEST2:
case WSA881X_TEMP_DETECT_DBG_CTL:
case WSA881X_TEMP_DEBUG_MSB:
case WSA881X_TEMP_DEBUG_LSB:
case WSA881X_SAMPLE_EDGE_SEL:
case WSA881X_IOPAD_CTL:
case WSA881X_SPARE_0:
case WSA881X_SPARE_1:
case WSA881X_SPARE_2:
case WSA881X_OTP_REG_0:
case WSA881X_OTP_REG_1:
case WSA881X_OTP_REG_2:
case WSA881X_OTP_REG_3:
case WSA881X_OTP_REG_4:
case WSA881X_OTP_REG_5:
case WSA881X_OTP_REG_6:
case WSA881X_OTP_REG_7:
case WSA881X_OTP_REG_8:
case WSA881X_OTP_REG_9:
case WSA881X_OTP_REG_10:
case WSA881X_OTP_REG_11:
case WSA881X_OTP_REG_12:
case WSA881X_OTP_REG_13:
case WSA881X_OTP_REG_14:
case WSA881X_OTP_REG_15:
case WSA881X_OTP_REG_16:
case WSA881X_OTP_REG_17:
case WSA881X_OTP_REG_18:
case WSA881X_OTP_REG_19:
case WSA881X_OTP_REG_20:
case WSA881X_OTP_REG_21:
case WSA881X_OTP_REG_22:
case WSA881X_OTP_REG_23:
case WSA881X_OTP_REG_24:
case WSA881X_OTP_REG_25:
case WSA881X_OTP_REG_26:
case WSA881X_OTP_REG_27:
case WSA881X_OTP_REG_28:
case WSA881X_OTP_REG_29:
case WSA881X_OTP_REG_30:
case WSA881X_OTP_REG_31:
case WSA881X_OTP_REG_63:
case WSA881X_BIAS_REF_CTRL:
case WSA881X_BIAS_TEST:
case WSA881X_BIAS_BIAS:
case WSA881X_TEMP_OP:
case WSA881X_TEMP_IREF_CTRL:
case WSA881X_TEMP_ISENS_CTRL:
case WSA881X_TEMP_CLK_CTRL:
case WSA881X_TEMP_TEST:
case WSA881X_TEMP_BIAS:
case WSA881X_TEMP_ADC_CTRL:
case WSA881X_TEMP_DOUT_MSB:
case WSA881X_TEMP_DOUT_LSB:
case WSA881X_ADC_EN_MODU_V:
case WSA881X_ADC_EN_MODU_I:
case WSA881X_ADC_EN_DET_TEST_V:
case WSA881X_ADC_EN_DET_TEST_I:
case WSA881X_ADC_SEL_IBIAS:
case WSA881X_ADC_EN_SEL_IBAIS:
case WSA881X_SPKR_DRV_EN:
case WSA881X_SPKR_DRV_GAIN:
case WSA881X_SPKR_DAC_CTL:
case WSA881X_SPKR_DRV_DBG:
case WSA881X_SPKR_PWRSTG_DBG:
case WSA881X_SPKR_OCP_CTL:
case WSA881X_SPKR_CLIP_CTL:
case WSA881X_SPKR_BBM_CTL:
case WSA881X_SPKR_MISC_CTL1:
case WSA881X_SPKR_MISC_CTL2:
case WSA881X_SPKR_BIAS_INT:
case WSA881X_SPKR_PA_INT:
case WSA881X_SPKR_BIAS_CAL:
case WSA881X_SPKR_BIAS_PSRR:
case WSA881X_SPKR_STATUS1:
case WSA881X_SPKR_STATUS2:
case WSA881X_BOOST_EN_CTL:
case WSA881X_BOOST_CURRENT_LIMIT:
case WSA881X_BOOST_PS_CTL:
case WSA881X_BOOST_PRESET_OUT1:
case WSA881X_BOOST_PRESET_OUT2:
case WSA881X_BOOST_FORCE_OUT:
case WSA881X_BOOST_LDO_PROG:
case WSA881X_BOOST_SLOPE_COMP_ISENSE_FB:
case WSA881X_BOOST_RON_CTL:
case WSA881X_BOOST_LOOP_STABILITY:
case WSA881X_BOOST_ZX_CTL:
case WSA881X_BOOST_START_CTL:
case WSA881X_BOOST_MISC1_CTL:
case WSA881X_BOOST_MISC2_CTL:
case WSA881X_BOOST_MISC3_CTL:
case WSA881X_BOOST_ATEST_CTL:
case WSA881X_SPKR_PROT_FE_GAIN:
case WSA881X_SPKR_PROT_FE_CM_LDO_SET:
case WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1:
case WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2:
case WSA881X_SPKR_PROT_ATEST1:
case WSA881X_SPKR_PROT_ATEST2:
case WSA881X_SPKR_PROT_FE_VSENSE_VCM:
case WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1:
case WSA881X_BONGO_RESRV_REG1:
case WSA881X_BONGO_RESRV_REG2:
case WSA881X_SPKR_PROT_SAR:
case WSA881X_SPKR_STATUS3:
return true;
default:
return false;
}
}
static bool wsa881x_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case WSA881X_CHIP_ID0:
case WSA881X_CHIP_ID1:
case WSA881X_CHIP_ID2:
case WSA881X_CHIP_ID3:
case WSA881X_BUS_ID:
case WSA881X_TEMP_MSB:
case WSA881X_TEMP_LSB:
case WSA881X_SDM_PDM9_LSB:
case WSA881X_SDM_PDM9_MSB:
case WSA881X_OTP_CTRL1:
case WSA881X_INTR_STATUS:
case WSA881X_ATE_TEST_MODE:
case WSA881X_PIN_STATUS:
case WSA881X_SWR_HM_TEST2:
case WSA881X_SPKR_STATUS1:
case WSA881X_SPKR_STATUS2:
case WSA881X_SPKR_STATUS3:
case WSA881X_OTP_REG_0:
case WSA881X_OTP_REG_1:
case WSA881X_OTP_REG_2:
case WSA881X_OTP_REG_3:
case WSA881X_OTP_REG_4:
case WSA881X_OTP_REG_5:
case WSA881X_OTP_REG_31:
case WSA881X_TEMP_DOUT_MSB:
case WSA881X_TEMP_DOUT_LSB:
case WSA881X_TEMP_OP:
case WSA881X_SPKR_PROT_SAR:
return true;
default:
return false;
}
}
static struct regmap_config wsa881x_regmap_config = {
.reg_bits = 32,
.val_bits = 8,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = wsa881x_defaults,
.max_register = WSA881X_SPKR_STATUS3,
.num_reg_defaults = ARRAY_SIZE(wsa881x_defaults),
.volatile_reg = wsa881x_volatile_register,
.readable_reg = wsa881x_readable_register,
.reg_format_endian = REGMAP_ENDIAN_NATIVE,
.val_format_endian = REGMAP_ENDIAN_NATIVE,
};
enum {
G_18DB = 0,
G_16P5DB,
G_15DB,
G_13P5DB,
G_12DB,
G_10P5DB,
G_9DB,
G_7P5DB,
G_6DB,
G_4P5DB,
G_3DB,
G_1P5DB,
G_0DB,
};
/*
* Private data Structure for wsa881x. All parameters related to
* WSA881X codec needs to be defined here.
*/
struct wsa881x_priv {
struct regmap *regmap;
struct device *dev;
struct sdw_slave *slave;
struct sdw_stream_config sconfig;
struct sdw_stream_runtime *sruntime;
struct sdw_port_config port_config[WSA881X_MAX_SWR_PORTS];
struct gpio_desc *sd_n;
/*
* Logical state for SD_N GPIO: high for shutdown, low for enable.
* For backwards compatibility.
*/
unsigned int sd_n_val;
int version;
int active_ports;
bool port_prepared[WSA881X_MAX_SWR_PORTS];
bool port_enable[WSA881X_MAX_SWR_PORTS];
};
static void wsa881x_init(struct wsa881x_priv *wsa881x)
{
struct regmap *rm = wsa881x->regmap;
unsigned int val = 0;
regmap_read(rm, WSA881X_CHIP_ID1, &wsa881x->version);
regmap_register_patch(wsa881x->regmap, wsa881x_rev_2_0,
ARRAY_SIZE(wsa881x_rev_2_0));
/* Enable software reset output from soundwire slave */
regmap_update_bits(rm, WSA881X_SWR_RESET_EN, 0x07, 0x07);
/* Bring out of analog reset */
regmap_update_bits(rm, WSA881X_CDC_RST_CTL, 0x02, 0x02);
/* Bring out of digital reset */
regmap_update_bits(rm, WSA881X_CDC_RST_CTL, 0x01, 0x01);
regmap_update_bits(rm, WSA881X_CLOCK_CONFIG, 0x10, 0x10);
regmap_update_bits(rm, WSA881X_SPKR_OCP_CTL, 0x02, 0x02);
regmap_update_bits(rm, WSA881X_SPKR_MISC_CTL1, 0xC0, 0x80);
regmap_update_bits(rm, WSA881X_SPKR_MISC_CTL1, 0x06, 0x06);
regmap_update_bits(rm, WSA881X_SPKR_BIAS_INT, 0xFF, 0x00);
regmap_update_bits(rm, WSA881X_SPKR_PA_INT, 0xF0, 0x40);
regmap_update_bits(rm, WSA881X_SPKR_PA_INT, 0x0E, 0x0E);
regmap_update_bits(rm, WSA881X_BOOST_LOOP_STABILITY, 0x03, 0x03);
regmap_update_bits(rm, WSA881X_BOOST_MISC2_CTL, 0xFF, 0x14);
regmap_update_bits(rm, WSA881X_BOOST_START_CTL, 0x80, 0x80);
regmap_update_bits(rm, WSA881X_BOOST_START_CTL, 0x03, 0x00);
regmap_update_bits(rm, WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, 0x0C, 0x04);
regmap_update_bits(rm, WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, 0x03, 0x00);
regmap_read(rm, WSA881X_OTP_REG_0, &val);
if (val)
regmap_update_bits(rm, WSA881X_BOOST_PRESET_OUT1, 0xF0, 0x70);
regmap_update_bits(rm, WSA881X_BOOST_PRESET_OUT2, 0xF0, 0x30);
regmap_update_bits(rm, WSA881X_SPKR_DRV_EN, 0x08, 0x08);
regmap_update_bits(rm, WSA881X_BOOST_CURRENT_LIMIT, 0x0F, 0x08);
regmap_update_bits(rm, WSA881X_SPKR_OCP_CTL, 0x30, 0x30);
regmap_update_bits(rm, WSA881X_SPKR_OCP_CTL, 0x0C, 0x00);
regmap_update_bits(rm, WSA881X_OTP_REG_28, 0x3F, 0x3A);
regmap_update_bits(rm, WSA881X_BONGO_RESRV_REG1, 0xFF, 0xB2);
regmap_update_bits(rm, WSA881X_BONGO_RESRV_REG2, 0xFF, 0x05);
}
static int wsa881x_component_probe(struct snd_soc_component *comp)
{
struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(comp);
snd_soc_component_init_regmap(comp, wsa881x->regmap);
return 0;
}
static int wsa881x_put_pa_gain(struct snd_kcontrol *kc,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *comp = snd_soc_kcontrol_component(kc);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kc->private_value;
int max = mc->max;
unsigned int mask = (1 << fls(max)) - 1;
int val, ret, min_gain, max_gain;
ret = pm_runtime_resume_and_get(comp->dev);
if (ret < 0 && ret != -EACCES)
return ret;
max_gain = (max - ucontrol->value.integer.value[0]) & mask;
/*
* Gain has to set incrementally in 4 steps
* as per HW sequence
*/
if (max_gain > G_4P5DB)
min_gain = G_0DB;
else
min_gain = max_gain + 3;
/*
* 1ms delay is needed before change in gain
* as per HW requirement.
*/
usleep_range(1000, 1010);
for (val = min_gain; max_gain <= val; val--) {
ret = snd_soc_component_update_bits(comp,
WSA881X_SPKR_DRV_GAIN,
WSA881X_SPKR_PAG_GAIN_MASK,
val << 4);
if (ret < 0)
dev_err(comp->dev, "Failed to change PA gain");
usleep_range(1000, 1010);
}
pm_runtime_mark_last_busy(comp->dev);
pm_runtime_put_autosuspend(comp->dev);
return 1;
}
static int wsa881x_get_port(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
struct wsa881x_priv *data = snd_soc_component_get_drvdata(comp);
struct soc_mixer_control *mixer =
(struct soc_mixer_control *)kcontrol->private_value;
int portidx = mixer->reg;
ucontrol->value.integer.value[0] = data->port_enable[portidx];
return 0;
}
static int wsa881x_boost_ctrl(struct snd_soc_component *comp, bool enable)
{
if (enable)
snd_soc_component_update_bits(comp, WSA881X_BOOST_EN_CTL,
WSA881X_BOOST_EN_MASK,
WSA881X_BOOST_EN);
else
snd_soc_component_update_bits(comp, WSA881X_BOOST_EN_CTL,
WSA881X_BOOST_EN_MASK, 0);
/*
* 1.5ms sleep is needed after boost enable/disable as per
* HW requirement
*/
usleep_range(1500, 1510);
return 0;
}
static int wsa881x_set_port(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
struct wsa881x_priv *data = snd_soc_component_get_drvdata(comp);
struct soc_mixer_control *mixer =
(struct soc_mixer_control *)kcontrol->private_value;
int portidx = mixer->reg;
if (ucontrol->value.integer.value[0]) {
if (data->port_enable[portidx])
return 0;
data->port_enable[portidx] = true;
} else {
if (!data->port_enable[portidx])
return 0;
data->port_enable[portidx] = false;
}
if (portidx == WSA881X_PORT_BOOST) /* Boost Switch */
wsa881x_boost_ctrl(comp, data->port_enable[portidx]);
return 1;
}
static const char * const smart_boost_lvl_text[] = {
"6.625 V", "6.750 V", "6.875 V", "7.000 V",
"7.125 V", "7.250 V", "7.375 V", "7.500 V",
"7.625 V", "7.750 V", "7.875 V", "8.000 V",
"8.125 V", "8.250 V", "8.375 V", "8.500 V"
};
static const struct soc_enum smart_boost_lvl_enum =
SOC_ENUM_SINGLE(WSA881X_BOOST_PRESET_OUT1, 0,
ARRAY_SIZE(smart_boost_lvl_text),
smart_boost_lvl_text);
static const DECLARE_TLV_DB_SCALE(pa_gain, 0, 150, 0);
static const struct snd_kcontrol_new wsa881x_snd_controls[] = {
SOC_ENUM("Smart Boost Level", smart_boost_lvl_enum),
WSA881X_PA_GAIN_TLV("PA Volume", WSA881X_SPKR_DRV_GAIN,
4, 0xC, 1, pa_gain),
SOC_SINGLE_EXT("DAC Switch", WSA881X_PORT_DAC, 0, 1, 0,
wsa881x_get_port, wsa881x_set_port),
SOC_SINGLE_EXT("COMP Switch", WSA881X_PORT_COMP, 0, 1, 0,
wsa881x_get_port, wsa881x_set_port),
SOC_SINGLE_EXT("BOOST Switch", WSA881X_PORT_BOOST, 0, 1, 0,
wsa881x_get_port, wsa881x_set_port),
SOC_SINGLE_EXT("VISENSE Switch", WSA881X_PORT_VISENSE, 0, 1, 0,
wsa881x_get_port, wsa881x_set_port),
};
static const struct snd_soc_dapm_route wsa881x_audio_map[] = {
{ "RDAC", NULL, "IN" },
{ "RDAC", NULL, "DCLK" },
{ "RDAC", NULL, "ACLK" },
{ "RDAC", NULL, "Bandgap" },
{ "SPKR PGA", NULL, "RDAC" },
{ "SPKR", NULL, "SPKR PGA" },
};
static int wsa881x_visense_txfe_ctrl(struct snd_soc_component *comp,
bool enable)
{
struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(comp);
if (enable) {
regmap_multi_reg_write(wsa881x->regmap, wsa881x_vi_txfe_en_2_0,
ARRAY_SIZE(wsa881x_vi_txfe_en_2_0));
} else {
snd_soc_component_update_bits(comp,
WSA881X_SPKR_PROT_FE_VSENSE_VCM,
0x08, 0x08);
/*
* 200us sleep is needed after visense txfe disable as per
* HW requirement.
*/
usleep_range(200, 210);
snd_soc_component_update_bits(comp, WSA881X_SPKR_PROT_FE_GAIN,
0x01, 0x00);
}
return 0;
}
static int wsa881x_visense_adc_ctrl(struct snd_soc_component *comp,
bool enable)
{
snd_soc_component_update_bits(comp, WSA881X_ADC_EN_MODU_V, BIT(7),
(enable << 7));
snd_soc_component_update_bits(comp, WSA881X_ADC_EN_MODU_I, BIT(7),
(enable << 7));
return 0;
}
static int wsa881x_spkr_pa_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(comp);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_component_update_bits(comp, WSA881X_SPKR_OCP_CTL,
WSA881X_SPKR_OCP_MASK,
WSA881X_SPKR_OCP_EN);
regmap_multi_reg_write(wsa881x->regmap, wsa881x_pre_pmu_pa_2_0,
ARRAY_SIZE(wsa881x_pre_pmu_pa_2_0));
snd_soc_component_update_bits(comp, WSA881X_SPKR_DRV_GAIN,
WSA881X_PA_GAIN_SEL_MASK,
WSA881X_PA_GAIN_SEL_REG);
break;
case SND_SOC_DAPM_POST_PMU:
if (wsa881x->port_prepared[WSA881X_PORT_VISENSE]) {
wsa881x_visense_txfe_ctrl(comp, true);
snd_soc_component_update_bits(comp,
WSA881X_ADC_EN_SEL_IBAIS,
0x07, 0x01);
wsa881x_visense_adc_ctrl(comp, true);
}
break;
case SND_SOC_DAPM_POST_PMD:
if (wsa881x->port_prepared[WSA881X_PORT_VISENSE]) {
wsa881x_visense_adc_ctrl(comp, false);
wsa881x_visense_txfe_ctrl(comp, false);
}
snd_soc_component_update_bits(comp, WSA881X_SPKR_OCP_CTL,
WSA881X_SPKR_OCP_MASK,
WSA881X_SPKR_OCP_EN |
WSA881X_SPKR_OCP_HOLD);
break;
}
return 0;
}
static const struct snd_soc_dapm_widget wsa881x_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("IN"),
SND_SOC_DAPM_DAC_E("RDAC", NULL, WSA881X_SPKR_DAC_CTL, 7, 0,
NULL,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("SPKR PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
wsa881x_spkr_pa_event, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("DCLK", WSA881X_CDC_DIG_CLK_CTL, 0, 0, NULL,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("ACLK", WSA881X_CDC_ANA_CLK_CTL, 0, 0, NULL,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("Bandgap", WSA881X_TEMP_OP, 3, 0,
NULL,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_OUTPUT("SPKR"),
};
static int wsa881x_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev);
int i;
wsa881x->active_ports = 0;
for (i = 0; i < WSA881X_MAX_SWR_PORTS; i++) {
if (!wsa881x->port_enable[i])
continue;
wsa881x->port_config[wsa881x->active_ports] =
wsa881x_pconfig[i];
wsa881x->active_ports++;
}
return sdw_stream_add_slave(wsa881x->slave, &wsa881x->sconfig,
wsa881x->port_config, wsa881x->active_ports,
wsa881x->sruntime);
}
static int wsa881x_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev);
sdw_stream_remove_slave(wsa881x->slave, wsa881x->sruntime);
return 0;
}
static int wsa881x_set_sdw_stream(struct snd_soc_dai *dai,
void *stream, int direction)
{
struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev);
wsa881x->sruntime = stream;
return 0;
}
static int wsa881x_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
{
struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev);
if (mute)
regmap_update_bits(wsa881x->regmap, WSA881X_SPKR_DRV_EN, 0x80,
0x00);
else
regmap_update_bits(wsa881x->regmap, WSA881X_SPKR_DRV_EN, 0x80,
0x80);
return 0;
}
static const struct snd_soc_dai_ops wsa881x_dai_ops = {
.hw_params = wsa881x_hw_params,
.hw_free = wsa881x_hw_free,
.mute_stream = wsa881x_digital_mute,
.set_stream = wsa881x_set_sdw_stream,
};
static struct snd_soc_dai_driver wsa881x_dais[] = {
{
.name = "SPKR",
.id = 0,
.playback = {
.stream_name = "SPKR Playback",
.rates = SNDRV_PCM_RATE_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.rate_max = 48000,
.rate_min = 48000,
.channels_min = 1,
.channels_max = 1,
},
.ops = &wsa881x_dai_ops,
},
};
static const struct snd_soc_component_driver wsa881x_component_drv = {
.name = "WSA881x",
.probe = wsa881x_component_probe,
.controls = wsa881x_snd_controls,
.num_controls = ARRAY_SIZE(wsa881x_snd_controls),
.dapm_widgets = wsa881x_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wsa881x_dapm_widgets),
.dapm_routes = wsa881x_audio_map,
.num_dapm_routes = ARRAY_SIZE(wsa881x_audio_map),
.endianness = 1,
};
static int wsa881x_update_status(struct sdw_slave *slave,
enum sdw_slave_status status)
{
struct wsa881x_priv *wsa881x = dev_get_drvdata(&slave->dev);
if (status == SDW_SLAVE_ATTACHED && slave->dev_num > 0)
wsa881x_init(wsa881x);
return 0;
}
static int wsa881x_port_prep(struct sdw_slave *slave,
struct sdw_prepare_ch *prepare_ch,
enum sdw_port_prep_ops state)
{
struct wsa881x_priv *wsa881x = dev_get_drvdata(&slave->dev);
if (state == SDW_OPS_PORT_POST_PREP)
wsa881x->port_prepared[prepare_ch->num - 1] = true;
else
wsa881x->port_prepared[prepare_ch->num - 1] = false;
return 0;
}
static int wsa881x_bus_config(struct sdw_slave *slave,
struct sdw_bus_params *params)
{
sdw_write(slave, SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(params->next_bank),
0x01);
return 0;
}
static const struct sdw_slave_ops wsa881x_slave_ops = {
.update_status = wsa881x_update_status,
.bus_config = wsa881x_bus_config,
.port_prep = wsa881x_port_prep,
};
static int wsa881x_probe(struct sdw_slave *pdev,
const struct sdw_device_id *id)
{
struct wsa881x_priv *wsa881x;
struct device *dev = &pdev->dev;
wsa881x = devm_kzalloc(dev, sizeof(*wsa881x), GFP_KERNEL);
if (!wsa881x)
return -ENOMEM;
wsa881x->sd_n = devm_gpiod_get_optional(dev, "powerdown",
GPIOD_FLAGS_BIT_NONEXCLUSIVE);
if (IS_ERR(wsa881x->sd_n))
return dev_err_probe(dev, PTR_ERR(wsa881x->sd_n),
"Shutdown Control GPIO not found\n");
/*
* Backwards compatibility work-around.
*
* The SD_N GPIO is active low, however upstream DTS used always active
* high. Changing the flag in driver and DTS will break backwards
* compatibility, so add a simple value inversion to work with both old
* and new DTS.
*
* This won't work properly with DTS using the flags properly in cases:
* 1. Old DTS with proper ACTIVE_LOW, however such case was broken
* before as the driver required the active high.
* 2. New DTS with proper ACTIVE_HIGH (intended), which is rare case
* (not existing upstream) but possible. This is the price of
* backwards compatibility, therefore this hack should be removed at
* some point.
*/
wsa881x->sd_n_val = gpiod_is_active_low(wsa881x->sd_n);
if (!wsa881x->sd_n_val)
dev_warn(dev, "Using ACTIVE_HIGH for shutdown GPIO. Your DTB might be outdated or you use unsupported configuration for the GPIO.");
dev_set_drvdata(dev, wsa881x);
wsa881x->slave = pdev;
wsa881x->dev = dev;
wsa881x->sconfig.ch_count = 1;
wsa881x->sconfig.bps = 1;
wsa881x->sconfig.frame_rate = 48000;
wsa881x->sconfig.direction = SDW_DATA_DIR_RX;
wsa881x->sconfig.type = SDW_STREAM_PDM;
pdev->prop.sink_ports = GENMASK(WSA881X_MAX_SWR_PORTS, 0);
pdev->prop.sink_dpn_prop = wsa_sink_dpn_prop;
pdev->prop.scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
gpiod_direction_output(wsa881x->sd_n, !wsa881x->sd_n_val);
wsa881x->regmap = devm_regmap_init_sdw(pdev, &wsa881x_regmap_config);
if (IS_ERR(wsa881x->regmap))
return dev_err_probe(dev, PTR_ERR(wsa881x->regmap), "regmap_init failed\n");
pm_runtime_set_autosuspend_delay(dev, 3000);
pm_runtime_use_autosuspend(dev);
pm_runtime_mark_last_busy(dev);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
return devm_snd_soc_register_component(dev,
&wsa881x_component_drv,
wsa881x_dais,
ARRAY_SIZE(wsa881x_dais));
}
static int __maybe_unused wsa881x_runtime_suspend(struct device *dev)
{
struct regmap *regmap = dev_get_regmap(dev, NULL);
struct wsa881x_priv *wsa881x = dev_get_drvdata(dev);
gpiod_direction_output(wsa881x->sd_n, wsa881x->sd_n_val);
regcache_cache_only(regmap, true);
regcache_mark_dirty(regmap);
return 0;
}
static int __maybe_unused wsa881x_runtime_resume(struct device *dev)
{
struct sdw_slave *slave = dev_to_sdw_dev(dev);
struct regmap *regmap = dev_get_regmap(dev, NULL);
struct wsa881x_priv *wsa881x = dev_get_drvdata(dev);
unsigned long time;
gpiod_direction_output(wsa881x->sd_n, !wsa881x->sd_n_val);
time = wait_for_completion_timeout(&slave->initialization_complete,
msecs_to_jiffies(WSA881X_PROBE_TIMEOUT));
if (!time) {
dev_err(dev, "Initialization not complete, timed out\n");
gpiod_direction_output(wsa881x->sd_n, wsa881x->sd_n_val);
return -ETIMEDOUT;
}
regcache_cache_only(regmap, false);
regcache_sync(regmap);
return 0;
}
static const struct dev_pm_ops wsa881x_pm_ops = {
SET_RUNTIME_PM_OPS(wsa881x_runtime_suspend, wsa881x_runtime_resume, NULL)
};
static const struct sdw_device_id wsa881x_slave_id[] = {
SDW_SLAVE_ENTRY(0x0217, 0x2010, 0),
SDW_SLAVE_ENTRY(0x0217, 0x2110, 0),
{},
};
MODULE_DEVICE_TABLE(sdw, wsa881x_slave_id);
static struct sdw_driver wsa881x_codec_driver = {
.probe = wsa881x_probe,
.ops = &wsa881x_slave_ops,
.id_table = wsa881x_slave_id,
.driver = {
.name = "wsa881x-codec",
.pm = &wsa881x_pm_ops,
}
};
module_sdw_driver(wsa881x_codec_driver);
MODULE_DESCRIPTION("WSA881x codec driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/wsa881x.c |
// SPDX-License-Identifier: GPL-2.0
//
// Lochnagar sound card driver
//
// Copyright (c) 2017-2019 Cirrus Logic, Inc. and
// Cirrus Logic International Semiconductor Ltd.
//
// Author: Charles Keepax <[email protected]>
// Piotr Stankiewicz <[email protected]>
#include <linux/clk.h>
#include <linux/module.h>
#include <sound/soc.h>
#include <linux/mfd/lochnagar.h>
#include <linux/mfd/lochnagar1_regs.h>
#include <linux/mfd/lochnagar2_regs.h>
struct lochnagar_sc_priv {
struct clk *mclk;
};
static const struct snd_soc_dapm_widget lochnagar_sc_widgets[] = {
SND_SOC_DAPM_LINE("Line Jack", NULL),
SND_SOC_DAPM_LINE("USB Audio", NULL),
};
static const struct snd_soc_dapm_route lochnagar_sc_routes[] = {
{ "Line Jack", NULL, "AIF1 Playback" },
{ "AIF1 Capture", NULL, "Line Jack" },
{ "USB Audio", NULL, "USB1 Playback" },
{ "USB Audio", NULL, "USB2 Playback" },
{ "USB1 Capture", NULL, "USB Audio" },
{ "USB2 Capture", NULL, "USB Audio" },
};
static const unsigned int lochnagar_sc_chan_vals[] = {
4, 8,
};
static const struct snd_pcm_hw_constraint_list lochnagar_sc_chan_constraint = {
.count = ARRAY_SIZE(lochnagar_sc_chan_vals),
.list = lochnagar_sc_chan_vals,
};
static const unsigned int lochnagar_sc_rate_vals[] = {
8000, 16000, 24000, 32000, 48000, 96000, 192000,
22050, 44100, 88200, 176400,
};
static const struct snd_pcm_hw_constraint_list lochnagar_sc_rate_constraint = {
.count = ARRAY_SIZE(lochnagar_sc_rate_vals),
.list = lochnagar_sc_rate_vals,
};
static int lochnagar_sc_hw_rule_rate(struct snd_pcm_hw_params *params,
struct snd_pcm_hw_rule *rule)
{
struct snd_interval range = {
.min = 8000,
.max = 24576000 / hw_param_interval(params, rule->deps[0])->max,
};
return snd_interval_refine(hw_param_interval(params, rule->var),
&range);
}
static int lochnagar_sc_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *comp = dai->component;
struct lochnagar_sc_priv *priv = snd_soc_component_get_drvdata(comp);
int ret;
ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&lochnagar_sc_rate_constraint);
if (ret)
return ret;
return snd_pcm_hw_rule_add(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
lochnagar_sc_hw_rule_rate, priv,
SNDRV_PCM_HW_PARAM_FRAME_BITS, -1);
}
static int lochnagar_sc_line_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *comp = dai->component;
struct lochnagar_sc_priv *priv = snd_soc_component_get_drvdata(comp);
int ret;
ret = clk_prepare_enable(priv->mclk);
if (ret < 0) {
dev_err(dai->dev, "Failed to enable MCLK: %d\n", ret);
return ret;
}
ret = lochnagar_sc_startup(substream, dai);
if (ret)
return ret;
return snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_CHANNELS,
&lochnagar_sc_chan_constraint);
}
static void lochnagar_sc_line_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *comp = dai->component;
struct lochnagar_sc_priv *priv = snd_soc_component_get_drvdata(comp);
clk_disable_unprepare(priv->mclk);
}
static int lochnagar_sc_check_fmt(struct snd_soc_dai *dai, unsigned int fmt,
unsigned int tar)
{
tar |= SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF;
if ((fmt & ~SND_SOC_DAIFMT_CLOCK_MASK) != tar)
return -EINVAL;
return 0;
}
static int lochnagar_sc_set_line_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
return lochnagar_sc_check_fmt(dai, fmt, SND_SOC_DAIFMT_CBS_CFS);
}
static int lochnagar_sc_set_usb_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
return lochnagar_sc_check_fmt(dai, fmt, SND_SOC_DAIFMT_CBM_CFM);
}
static const struct snd_soc_dai_ops lochnagar_sc_line_ops = {
.startup = lochnagar_sc_line_startup,
.shutdown = lochnagar_sc_line_shutdown,
.set_fmt = lochnagar_sc_set_line_fmt,
};
static const struct snd_soc_dai_ops lochnagar_sc_usb_ops = {
.startup = lochnagar_sc_startup,
.set_fmt = lochnagar_sc_set_usb_fmt,
};
static struct snd_soc_dai_driver lochnagar_sc_dai[] = {
{
.name = "lochnagar-line",
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 4,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = SNDRV_PCM_FMTBIT_S32_LE,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 4,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = SNDRV_PCM_FMTBIT_S32_LE,
},
.ops = &lochnagar_sc_line_ops,
.symmetric_rate = true,
.symmetric_sample_bits = true,
},
{
.name = "lochnagar-usb1",
.playback = {
.stream_name = "USB1 Playback",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = SNDRV_PCM_FMTBIT_S32_LE,
},
.capture = {
.stream_name = "USB1 Capture",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = SNDRV_PCM_FMTBIT_S32_LE,
},
.ops = &lochnagar_sc_usb_ops,
.symmetric_rate = true,
.symmetric_sample_bits = true,
},
{
.name = "lochnagar-usb2",
.playback = {
.stream_name = "USB2 Playback",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = SNDRV_PCM_FMTBIT_S32_LE,
},
.capture = {
.stream_name = "USB2 Capture",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = SNDRV_PCM_FMTBIT_S32_LE,
},
.ops = &lochnagar_sc_usb_ops,
.symmetric_rate = true,
.symmetric_sample_bits = true,
},
};
static const struct snd_soc_component_driver lochnagar_sc_driver = {
.dapm_widgets = lochnagar_sc_widgets,
.num_dapm_widgets = ARRAY_SIZE(lochnagar_sc_widgets),
.dapm_routes = lochnagar_sc_routes,
.num_dapm_routes = ARRAY_SIZE(lochnagar_sc_routes),
.endianness = 1,
};
static int lochnagar_sc_probe(struct platform_device *pdev)
{
struct lochnagar_sc_priv *priv;
int ret;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->mclk = devm_clk_get(&pdev->dev, "mclk");
if (IS_ERR(priv->mclk)) {
ret = PTR_ERR(priv->mclk);
dev_err(&pdev->dev, "Failed to get MCLK: %d\n", ret);
return ret;
}
platform_set_drvdata(pdev, priv);
return devm_snd_soc_register_component(&pdev->dev,
&lochnagar_sc_driver,
lochnagar_sc_dai,
ARRAY_SIZE(lochnagar_sc_dai));
}
static const struct of_device_id lochnagar_of_match[] = {
{ .compatible = "cirrus,lochnagar2-soundcard" },
{}
};
MODULE_DEVICE_TABLE(of, lochnagar_of_match);
static struct platform_driver lochnagar_sc_codec_driver = {
.driver = {
.name = "lochnagar-soundcard",
.of_match_table = lochnagar_of_match,
},
.probe = lochnagar_sc_probe,
};
module_platform_driver(lochnagar_sc_codec_driver);
MODULE_DESCRIPTION("ASoC Lochnagar Sound Card Driver");
MODULE_AUTHOR("Piotr Stankiewicz <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:lochnagar-soundcard");
| linux-master | sound/soc/codecs/lochnagar-sc.c |
// SPDX-License-Identifier: GPL-2.0
//
// Ingenic JZ4770 CODEC driver
//
// Copyright (C) 2012, Maarten ter Huurne <[email protected]>
// Copyright (C) 2019, Paul Cercueil <[email protected]>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/time64.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include <sound/soc-dapm.h>
#include <sound/tlv.h>
#define ICDC_RGADW_OFFSET 0x00
#define ICDC_RGDATA_OFFSET 0x04
/* ICDC internal register access control register(RGADW) */
#define ICDC_RGADW_RGWR BIT(16)
#define ICDC_RGADW_RGADDR_OFFSET 8
#define ICDC_RGADW_RGADDR_MASK GENMASK(14, ICDC_RGADW_RGADDR_OFFSET)
#define ICDC_RGADW_RGDIN_OFFSET 0
#define ICDC_RGADW_RGDIN_MASK GENMASK(7, ICDC_RGADW_RGDIN_OFFSET)
/* ICDC internal register data output register (RGDATA)*/
#define ICDC_RGDATA_IRQ BIT(8)
#define ICDC_RGDATA_RGDOUT_OFFSET 0
#define ICDC_RGDATA_RGDOUT_MASK GENMASK(7, ICDC_RGDATA_RGDOUT_OFFSET)
/* Internal register space, accessed through regmap */
enum {
JZ4770_CODEC_REG_SR,
JZ4770_CODEC_REG_AICR_DAC,
JZ4770_CODEC_REG_AICR_ADC,
JZ4770_CODEC_REG_CR_LO,
JZ4770_CODEC_REG_CR_HP,
JZ4770_CODEC_REG_MISSING_REG1,
JZ4770_CODEC_REG_CR_DAC,
JZ4770_CODEC_REG_CR_MIC,
JZ4770_CODEC_REG_CR_LI,
JZ4770_CODEC_REG_CR_ADC,
JZ4770_CODEC_REG_CR_MIX,
JZ4770_CODEC_REG_CR_VIC,
JZ4770_CODEC_REG_CCR,
JZ4770_CODEC_REG_FCR_DAC,
JZ4770_CODEC_REG_FCR_ADC,
JZ4770_CODEC_REG_ICR,
JZ4770_CODEC_REG_IMR,
JZ4770_CODEC_REG_IFR,
JZ4770_CODEC_REG_GCR_HPL,
JZ4770_CODEC_REG_GCR_HPR,
JZ4770_CODEC_REG_GCR_LIBYL,
JZ4770_CODEC_REG_GCR_LIBYR,
JZ4770_CODEC_REG_GCR_DACL,
JZ4770_CODEC_REG_GCR_DACR,
JZ4770_CODEC_REG_GCR_MIC1,
JZ4770_CODEC_REG_GCR_MIC2,
JZ4770_CODEC_REG_GCR_ADCL,
JZ4770_CODEC_REG_GCR_ADCR,
JZ4770_CODEC_REG_MISSING_REG2,
JZ4770_CODEC_REG_GCR_MIXADC,
JZ4770_CODEC_REG_GCR_MIXDAC,
JZ4770_CODEC_REG_AGC1,
JZ4770_CODEC_REG_AGC2,
JZ4770_CODEC_REG_AGC3,
JZ4770_CODEC_REG_AGC4,
JZ4770_CODEC_REG_AGC5,
};
#define REG_AICR_DAC_ADWL_OFFSET 6
#define REG_AICR_DAC_ADWL_MASK (0x3 << REG_AICR_DAC_ADWL_OFFSET)
#define REG_AICR_DAC_SERIAL BIT(1)
#define REG_AICR_DAC_I2S BIT(0)
#define REG_AICR_ADC_ADWL_OFFSET 6
#define REG_AICR_ADC_ADWL_MASK (0x3 << REG_AICR_ADC_ADWL_OFFSET)
#define REG_AICR_ADC_SERIAL BIT(1)
#define REG_AICR_ADC_I2S BIT(0)
#define REG_CR_LO_MUTE_OFFSET 7
#define REG_CR_LO_SB_OFFSET 4
#define REG_CR_LO_SEL_OFFSET 0
#define REG_CR_LO_SEL_MASK (0x3 << REG_CR_LO_SEL_OFFSET)
#define REG_CR_HP_MUTE BIT(7)
#define REG_CR_HP_LOAD BIT(6)
#define REG_CR_HP_SB_OFFSET 4
#define REG_CR_HP_SB_HPCM_OFFSET 3
#define REG_CR_HP_SEL_OFFSET 0
#define REG_CR_HP_SEL_MASK (0x3 << REG_CR_HP_SEL_OFFSET)
#define REG_CR_DAC_MUTE BIT(7)
#define REG_CR_DAC_MONO BIT(6)
#define REG_CR_DAC_LEFT_ONLY BIT(5)
#define REG_CR_DAC_SB_OFFSET 4
#define REG_CR_DAC_LRSWAP BIT(3)
#define REG_CR_MIC_STEREO_OFFSET 7
#define REG_CR_MIC_IDIFF_OFFSET 6
#define REG_CR_MIC_SB_MIC2_OFFSET 5
#define REG_CR_MIC_SB_MIC1_OFFSET 4
#define REG_CR_MIC_BIAS_V0_OFFSET 1
#define REG_CR_MIC_BIAS_SB_OFFSET 0
#define REG_CR_LI_LIBY_OFFSET 4
#define REG_CR_LI_SB_OFFSET 0
#define REG_CR_ADC_DMIC_SEL BIT(7)
#define REG_CR_ADC_MONO BIT(6)
#define REG_CR_ADC_LEFT_ONLY BIT(5)
#define REG_CR_ADC_SB_OFFSET 4
#define REG_CR_ADC_LRSWAP BIT(3)
#define REG_CR_ADC_IN_SEL_OFFSET 0
#define REG_CR_ADC_IN_SEL_MASK (0x3 << REG_CR_ADC_IN_SEL_OFFSET)
#define REG_CR_VIC_SB_SLEEP BIT(1)
#define REG_CR_VIC_SB BIT(0)
#define REG_CCR_CRYSTAL_OFFSET 0
#define REG_CCR_CRYSTAL_MASK (0xf << REG_CCR_CRYSTAL_OFFSET)
#define REG_FCR_DAC_FREQ_OFFSET 0
#define REG_FCR_DAC_FREQ_MASK (0xf << REG_FCR_DAC_FREQ_OFFSET)
#define REG_FCR_ADC_FREQ_OFFSET 0
#define REG_FCR_ADC_FREQ_MASK (0xf << REG_FCR_ADC_FREQ_OFFSET)
#define REG_ICR_INT_FORM_OFFSET 6
#define REG_ICR_INT_FORM_MASK (0x3 << REG_ICR_INT_FORM_OFFSET)
#define REG_IMR_ALL_MASK (0x7f)
#define REG_IMR_SCLR_MASK BIT(6)
#define REG_IMR_JACK_MASK BIT(5)
#define REG_IMR_SCMC_MASK BIT(4)
#define REG_IMR_RUP_MASK BIT(3)
#define REG_IMR_RDO_MASK BIT(2)
#define REG_IMR_GUP_MASK BIT(1)
#define REG_IMR_GDO_MASK BIT(0)
#define REG_IFR_ALL_MASK (0x7f)
#define REG_IFR_SCLR BIT(6)
#define REG_IFR_JACK BIT(5)
#define REG_IFR_SCMC BIT(4)
#define REG_IFR_RUP BIT(3)
#define REG_IFR_RDO BIT(2)
#define REG_IFR_GUP BIT(1)
#define REG_IFR_GDO BIT(0)
#define REG_GCR_HPL_LRGO BIT(7)
#define REG_GCR_DACL_RLGOD BIT(7)
#define REG_GCR_GAIN_OFFSET 0
#define REG_GCR_GAIN_MAX 0x1f
#define REG_GCR_MIC_GAIN_OFFSET 0
#define REG_GCR_MIC_GAIN_MAX 5
#define REG_GCR_ADC_GAIN_OFFSET 0
#define REG_GCR_ADC_GAIN_MAX 23
#define REG_AGC1_EN BIT(7)
/* codec private data */
struct jz_codec {
struct device *dev;
struct regmap *regmap;
void __iomem *base;
struct clk *clk;
};
static int jz4770_codec_set_bias_level(struct snd_soc_component *codec,
enum snd_soc_bias_level level)
{
struct jz_codec *jz_codec = snd_soc_component_get_drvdata(codec);
struct regmap *regmap = jz_codec->regmap;
switch (level) {
case SND_SOC_BIAS_PREPARE:
/* Reset all interrupt flags. */
regmap_write(regmap, JZ4770_CODEC_REG_IFR, REG_IFR_ALL_MASK);
regmap_clear_bits(regmap, JZ4770_CODEC_REG_CR_VIC,
REG_CR_VIC_SB);
msleep(250);
regmap_clear_bits(regmap, JZ4770_CODEC_REG_CR_VIC,
REG_CR_VIC_SB_SLEEP);
msleep(400);
break;
case SND_SOC_BIAS_STANDBY:
regmap_set_bits(regmap, JZ4770_CODEC_REG_CR_VIC,
REG_CR_VIC_SB_SLEEP);
regmap_set_bits(regmap, JZ4770_CODEC_REG_CR_VIC,
REG_CR_VIC_SB);
fallthrough;
default:
break;
}
return 0;
}
static int jz4770_codec_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *codec = dai->component;
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(codec);
/*
* SYSCLK output from the codec to the AIC is required to keep the
* DMA transfer going during playback when all audible outputs have
* been disabled.
*/
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
snd_soc_dapm_force_enable_pin(dapm, "SYSCLK");
return 0;
}
static void jz4770_codec_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *codec = dai->component;
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(codec);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
snd_soc_dapm_disable_pin(dapm, "SYSCLK");
}
static int jz4770_codec_pcm_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
struct snd_soc_component *codec = dai->component;
int ret = 0;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
snd_soc_component_force_bias_level(codec,
SND_SOC_BIAS_ON);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
/* do nothing */
break;
default:
ret = -EINVAL;
}
return ret;
}
static int jz4770_codec_mute_stream(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *codec = dai->component;
struct jz_codec *jz_codec = snd_soc_component_get_drvdata(codec);
unsigned int gain_bit = mute ? REG_IFR_GDO : REG_IFR_GUP;
unsigned int val;
int change, err;
change = snd_soc_component_update_bits(codec, JZ4770_CODEC_REG_CR_DAC,
REG_CR_DAC_MUTE,
mute ? REG_CR_DAC_MUTE : 0);
if (change == 1) {
regmap_read(jz_codec->regmap, JZ4770_CODEC_REG_CR_DAC, &val);
if (val & BIT(REG_CR_DAC_SB_OFFSET))
return 1;
err = regmap_read_poll_timeout(jz_codec->regmap,
JZ4770_CODEC_REG_IFR,
val, val & gain_bit,
1000, 1 * USEC_PER_SEC);
if (err) {
dev_err(jz_codec->dev,
"Timeout while setting digital mute: %d", err);
return err;
}
/* clear GUP/GDO flag */
regmap_set_bits(jz_codec->regmap, JZ4770_CODEC_REG_IFR,
gain_bit);
}
return 0;
}
/* unit: 0.01dB */
static const DECLARE_TLV_DB_MINMAX_MUTE(dac_tlv, -3100, 0);
static const DECLARE_TLV_DB_SCALE(adc_tlv, 0, 100, 0);
static const DECLARE_TLV_DB_MINMAX(out_tlv, -2500, 600);
static const DECLARE_TLV_DB_SCALE(linein_tlv, -2500, 100, 0);
static const DECLARE_TLV_DB_MINMAX(mixer_tlv, -3100, 0);
/* Unconditional controls. */
static const struct snd_kcontrol_new jz4770_codec_snd_controls[] = {
/* record gain control */
SOC_DOUBLE_R_TLV("PCM Capture Volume",
JZ4770_CODEC_REG_GCR_ADCL, JZ4770_CODEC_REG_GCR_ADCR,
REG_GCR_ADC_GAIN_OFFSET, REG_GCR_ADC_GAIN_MAX,
0, adc_tlv),
SOC_DOUBLE_R_TLV("Line In Bypass Playback Volume",
JZ4770_CODEC_REG_GCR_LIBYL, JZ4770_CODEC_REG_GCR_LIBYR,
REG_GCR_GAIN_OFFSET, REG_GCR_GAIN_MAX, 1, linein_tlv),
SOC_SINGLE_TLV("Mixer Capture Volume",
JZ4770_CODEC_REG_GCR_MIXADC,
REG_GCR_GAIN_OFFSET, REG_GCR_GAIN_MAX, 1, mixer_tlv),
SOC_SINGLE_TLV("Mixer Playback Volume",
JZ4770_CODEC_REG_GCR_MIXDAC,
REG_GCR_GAIN_OFFSET, REG_GCR_GAIN_MAX, 1, mixer_tlv),
};
static const struct snd_kcontrol_new jz4770_codec_pcm_playback_controls[] = {
{
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "Volume",
.info = snd_soc_info_volsw,
.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ
| SNDRV_CTL_ELEM_ACCESS_READWRITE,
.tlv.p = dac_tlv,
.get = snd_soc_dapm_get_volsw,
.put = snd_soc_dapm_put_volsw,
/*
* NOTE: DACR/DACL are inversed; the gain value written to DACR
* seems to affect the left channel, and the gain value written
* to DACL seems to affect the right channel.
*/
.private_value = SOC_DOUBLE_R_VALUE(JZ4770_CODEC_REG_GCR_DACR,
JZ4770_CODEC_REG_GCR_DACL,
REG_GCR_GAIN_OFFSET,
REG_GCR_GAIN_MAX, 1),
},
};
static const struct snd_kcontrol_new jz4770_codec_hp_playback_controls[] = {
{
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "Volume",
.info = snd_soc_info_volsw,
.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ
| SNDRV_CTL_ELEM_ACCESS_READWRITE,
.tlv.p = out_tlv,
.get = snd_soc_dapm_get_volsw,
.put = snd_soc_dapm_put_volsw,
/* HPR/HPL inversed for the same reason as above */
.private_value = SOC_DOUBLE_R_VALUE(JZ4770_CODEC_REG_GCR_HPR,
JZ4770_CODEC_REG_GCR_HPL,
REG_GCR_GAIN_OFFSET,
REG_GCR_GAIN_MAX, 1),
},
};
static int hpout_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *codec = snd_soc_dapm_to_component(w->dapm);
struct jz_codec *jz_codec = snd_soc_component_get_drvdata(codec);
unsigned int val;
int err;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* unmute HP */
regmap_clear_bits(jz_codec->regmap, JZ4770_CODEC_REG_CR_HP,
REG_CR_HP_MUTE);
break;
case SND_SOC_DAPM_POST_PMU:
/* wait for ramp-up complete (RUP) */
err = regmap_read_poll_timeout(jz_codec->regmap,
JZ4770_CODEC_REG_IFR,
val, val & REG_IFR_RUP,
1000, 1 * USEC_PER_SEC);
if (err) {
dev_err(jz_codec->dev, "RUP timeout: %d", err);
return err;
}
/* clear RUP flag */
regmap_set_bits(jz_codec->regmap, JZ4770_CODEC_REG_IFR,
REG_IFR_RUP);
break;
case SND_SOC_DAPM_POST_PMD:
/* mute HP */
regmap_set_bits(jz_codec->regmap, JZ4770_CODEC_REG_CR_HP,
REG_CR_HP_MUTE);
err = regmap_read_poll_timeout(jz_codec->regmap,
JZ4770_CODEC_REG_IFR,
val, val & REG_IFR_RDO,
1000, 1 * USEC_PER_SEC);
if (err) {
dev_err(jz_codec->dev, "RDO timeout: %d", err);
return err;
}
/* clear RDO flag */
regmap_set_bits(jz_codec->regmap, JZ4770_CODEC_REG_IFR,
REG_IFR_RDO);
break;
}
return 0;
}
static int adc_poweron_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
if (event == SND_SOC_DAPM_POST_PMU)
msleep(1000);
return 0;
}
static const char * const jz4770_codec_hp_texts[] = {
"PCM", "Line In", "Mic 1", "Mic 2"
};
static const unsigned int jz4770_codec_hp_values[] = { 3, 2, 0, 1 };
static SOC_VALUE_ENUM_SINGLE_DECL(jz4770_codec_hp_enum,
JZ4770_CODEC_REG_CR_HP,
REG_CR_HP_SEL_OFFSET,
REG_CR_HP_SEL_MASK,
jz4770_codec_hp_texts,
jz4770_codec_hp_values);
static const struct snd_kcontrol_new jz4770_codec_hp_source =
SOC_DAPM_ENUM("Route", jz4770_codec_hp_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(jz4770_codec_lo_enum,
JZ4770_CODEC_REG_CR_LO,
REG_CR_LO_SEL_OFFSET,
REG_CR_LO_SEL_MASK,
jz4770_codec_hp_texts,
jz4770_codec_hp_values);
static const struct snd_kcontrol_new jz4770_codec_lo_source =
SOC_DAPM_ENUM("Route", jz4770_codec_lo_enum);
static const char * const jz4770_codec_cap_texts[] = {
"Line In", "Mic 1", "Mic 2"
};
static const unsigned int jz4770_codec_cap_values[] = { 2, 0, 1 };
static SOC_VALUE_ENUM_SINGLE_DECL(jz4770_codec_cap_enum,
JZ4770_CODEC_REG_CR_ADC,
REG_CR_ADC_IN_SEL_OFFSET,
REG_CR_ADC_IN_SEL_MASK,
jz4770_codec_cap_texts,
jz4770_codec_cap_values);
static const struct snd_kcontrol_new jz4770_codec_cap_source =
SOC_DAPM_ENUM("Route", jz4770_codec_cap_enum);
static const struct snd_kcontrol_new jz4770_codec_mic_controls[] = {
SOC_DAPM_SINGLE("Stereo Capture Switch", JZ4770_CODEC_REG_CR_MIC,
REG_CR_MIC_STEREO_OFFSET, 1, 0),
};
static const struct snd_soc_dapm_widget jz4770_codec_dapm_widgets[] = {
SND_SOC_DAPM_PGA_E("HP Out", JZ4770_CODEC_REG_CR_HP,
REG_CR_HP_SB_OFFSET, 1, NULL, 0, hpout_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA("Line Out", JZ4770_CODEC_REG_CR_LO,
REG_CR_LO_SB_OFFSET, 1, NULL, 0),
SND_SOC_DAPM_PGA("Line Out Switch 2", JZ4770_CODEC_REG_CR_LO,
REG_CR_LO_MUTE_OFFSET, 1, NULL, 0),
SND_SOC_DAPM_PGA("Line In", JZ4770_CODEC_REG_CR_LI,
REG_CR_LI_SB_OFFSET, 1, NULL, 0),
SND_SOC_DAPM_MUX("Headphones Source", SND_SOC_NOPM, 0, 0,
&jz4770_codec_hp_source),
SND_SOC_DAPM_MUX("Capture Source", SND_SOC_NOPM, 0, 0,
&jz4770_codec_cap_source),
SND_SOC_DAPM_MUX("Line Out Source", SND_SOC_NOPM, 0, 0,
&jz4770_codec_lo_source),
SND_SOC_DAPM_PGA("Mic 1", JZ4770_CODEC_REG_CR_MIC,
REG_CR_MIC_SB_MIC1_OFFSET, 1, NULL, 0),
SND_SOC_DAPM_PGA("Mic 2", JZ4770_CODEC_REG_CR_MIC,
REG_CR_MIC_SB_MIC2_OFFSET, 1, NULL, 0),
SND_SOC_DAPM_PGA("Mic Diff", JZ4770_CODEC_REG_CR_MIC,
REG_CR_MIC_IDIFF_OFFSET, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Mic", SND_SOC_NOPM, 0, 0,
jz4770_codec_mic_controls,
ARRAY_SIZE(jz4770_codec_mic_controls)),
SND_SOC_DAPM_PGA("Line In Bypass", JZ4770_CODEC_REG_CR_LI,
REG_CR_LI_LIBY_OFFSET, 1, NULL, 0),
SND_SOC_DAPM_ADC_E("ADC", "HiFi Capture", JZ4770_CODEC_REG_CR_ADC,
REG_CR_ADC_SB_OFFSET, 1, adc_poweron_event,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_DAC("DAC", "HiFi Playback", JZ4770_CODEC_REG_CR_DAC,
REG_CR_DAC_SB_OFFSET, 1),
SND_SOC_DAPM_MIXER("PCM Playback", SND_SOC_NOPM, 0, 0,
jz4770_codec_pcm_playback_controls,
ARRAY_SIZE(jz4770_codec_pcm_playback_controls)),
SND_SOC_DAPM_MIXER("Headphones Playback", SND_SOC_NOPM, 0, 0,
jz4770_codec_hp_playback_controls,
ARRAY_SIZE(jz4770_codec_hp_playback_controls)),
SND_SOC_DAPM_SUPPLY("MICBIAS", JZ4770_CODEC_REG_CR_MIC,
REG_CR_MIC_BIAS_SB_OFFSET, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("Cap-less", JZ4770_CODEC_REG_CR_HP,
REG_CR_HP_SB_HPCM_OFFSET, 1, NULL, 0),
SND_SOC_DAPM_INPUT("MIC1P"),
SND_SOC_DAPM_INPUT("MIC1N"),
SND_SOC_DAPM_INPUT("MIC2P"),
SND_SOC_DAPM_INPUT("MIC2N"),
SND_SOC_DAPM_OUTPUT("LOUT"),
SND_SOC_DAPM_OUTPUT("ROUT"),
SND_SOC_DAPM_OUTPUT("LHPOUT"),
SND_SOC_DAPM_OUTPUT("RHPOUT"),
SND_SOC_DAPM_INPUT("LLINEIN"),
SND_SOC_DAPM_INPUT("RLINEIN"),
SND_SOC_DAPM_OUTPUT("SYSCLK"),
};
/* Unconditional routes. */
static const struct snd_soc_dapm_route jz4770_codec_dapm_routes[] = {
{ "Mic 1", NULL, "MIC1P" },
{ "Mic Diff", NULL, "MIC1N" },
{ "Mic 1", NULL, "Mic Diff" },
{ "Mic 2", NULL, "MIC2P" },
{ "Mic Diff", NULL, "MIC2N" },
{ "Mic 2", NULL, "Mic Diff" },
{ "Line In", NULL, "LLINEIN" },
{ "Line In", NULL, "RLINEIN" },
{ "Mic", "Stereo Capture Switch", "Mic 1" },
{ "Mic", "Stereo Capture Switch", "Mic 2" },
{ "Headphones Source", "Mic 1", "Mic" },
{ "Headphones Source", "Mic 2", "Mic" },
{ "Capture Source", "Mic 1", "Mic" },
{ "Capture Source", "Mic 2", "Mic" },
{ "Headphones Source", "Mic 1", "Mic 1" },
{ "Headphones Source", "Mic 2", "Mic 2" },
{ "Headphones Source", "Line In", "Line In Bypass" },
{ "Headphones Source", "PCM", "Headphones Playback" },
{ "HP Out", NULL, "Headphones Source" },
{ "Capture Source", "Line In", "Line In" },
{ "Capture Source", "Mic 1", "Mic 1" },
{ "Capture Source", "Mic 2", "Mic 2" },
{ "ADC", NULL, "Capture Source" },
{ "Line In Bypass", NULL, "Line In" },
{ "Line Out Source", "Line In", "Line In Bypass" },
{ "Line Out Source", "PCM", "PCM Playback" },
{ "LHPOUT", NULL, "HP Out"},
{ "RHPOUT", NULL, "HP Out"},
{ "Line Out", NULL, "Line Out Source" },
{ "Line Out Switch 2", NULL, "Line Out" },
{ "LOUT", NULL, "Line Out Switch 2"},
{ "ROUT", NULL, "Line Out Switch 2"},
{ "PCM Playback", "Volume", "DAC" },
{ "Headphones Playback", "Volume", "PCM Playback" },
{ "SYSCLK", NULL, "DAC" },
};
static void jz4770_codec_codec_init_regs(struct snd_soc_component *codec)
{
struct jz_codec *jz_codec = snd_soc_component_get_drvdata(codec);
struct regmap *regmap = jz_codec->regmap;
/* Collect updates for later sending. */
regcache_cache_only(regmap, true);
/* default HP output to PCM */
regmap_set_bits(regmap, JZ4770_CODEC_REG_CR_HP, REG_CR_HP_SEL_MASK);
/* default line output to PCM */
regmap_set_bits(regmap, JZ4770_CODEC_REG_CR_LO, REG_CR_LO_SEL_MASK);
/* Disable stereo mic */
regmap_clear_bits(regmap, JZ4770_CODEC_REG_CR_MIC,
BIT(REG_CR_MIC_STEREO_OFFSET));
/* Set mic 1 as default source for ADC */
regmap_clear_bits(regmap, JZ4770_CODEC_REG_CR_ADC,
REG_CR_ADC_IN_SEL_MASK);
/* ADC/DAC: serial + i2s */
regmap_set_bits(regmap, JZ4770_CODEC_REG_AICR_ADC,
REG_AICR_ADC_SERIAL | REG_AICR_ADC_I2S);
regmap_set_bits(regmap, JZ4770_CODEC_REG_AICR_DAC,
REG_AICR_DAC_SERIAL | REG_AICR_DAC_I2S);
/* The generated IRQ is a high level */
regmap_clear_bits(regmap, JZ4770_CODEC_REG_ICR, REG_ICR_INT_FORM_MASK);
regmap_update_bits(regmap, JZ4770_CODEC_REG_IMR, REG_IMR_ALL_MASK,
REG_IMR_JACK_MASK | REG_IMR_RUP_MASK |
REG_IMR_RDO_MASK | REG_IMR_GUP_MASK |
REG_IMR_GDO_MASK);
/* 12M oscillator */
regmap_clear_bits(regmap, JZ4770_CODEC_REG_CCR, REG_CCR_CRYSTAL_MASK);
/* 0: 16ohm/220uF, 1: 10kohm/1uF */
regmap_clear_bits(regmap, JZ4770_CODEC_REG_CR_HP, REG_CR_HP_LOAD);
/* disable automatic gain */
regmap_clear_bits(regmap, JZ4770_CODEC_REG_AGC1, REG_AGC1_EN);
/* Disable DAC lrswap */
regmap_set_bits(regmap, JZ4770_CODEC_REG_CR_DAC, REG_CR_DAC_LRSWAP);
/* Independent L/R DAC gain control */
regmap_clear_bits(regmap, JZ4770_CODEC_REG_GCR_DACL,
REG_GCR_DACL_RLGOD);
/* Disable ADC lrswap */
regmap_set_bits(regmap, JZ4770_CODEC_REG_CR_ADC, REG_CR_ADC_LRSWAP);
/* default to cap-less mode(0) */
regmap_clear_bits(regmap, JZ4770_CODEC_REG_CR_HP,
BIT(REG_CR_HP_SB_HPCM_OFFSET));
/* Send collected updates. */
regcache_cache_only(regmap, false);
regcache_sync(regmap);
}
static int jz4770_codec_codec_probe(struct snd_soc_component *codec)
{
struct jz_codec *jz_codec = snd_soc_component_get_drvdata(codec);
clk_prepare_enable(jz_codec->clk);
jz4770_codec_codec_init_regs(codec);
return 0;
}
static void jz4770_codec_codec_remove(struct snd_soc_component *codec)
{
struct jz_codec *jz_codec = snd_soc_component_get_drvdata(codec);
clk_disable_unprepare(jz_codec->clk);
}
static const struct snd_soc_component_driver jz4770_codec_soc_codec_dev = {
.probe = jz4770_codec_codec_probe,
.remove = jz4770_codec_codec_remove,
.set_bias_level = jz4770_codec_set_bias_level,
.controls = jz4770_codec_snd_controls,
.num_controls = ARRAY_SIZE(jz4770_codec_snd_controls),
.dapm_widgets = jz4770_codec_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(jz4770_codec_dapm_widgets),
.dapm_routes = jz4770_codec_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(jz4770_codec_dapm_routes),
.suspend_bias_off = 1,
.use_pmdown_time = 1,
};
static const unsigned int jz4770_codec_sample_rates[] = {
96000, 48000, 44100, 32000,
24000, 22050, 16000, 12000,
11025, 9600, 8000,
};
static int jz4770_codec_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct jz_codec *codec = snd_soc_component_get_drvdata(dai->component);
unsigned int rate, bit_width;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
bit_width = 0;
break;
case SNDRV_PCM_FORMAT_S18_3LE:
bit_width = 1;
break;
case SNDRV_PCM_FORMAT_S20_3LE:
bit_width = 2;
break;
case SNDRV_PCM_FORMAT_S24_3LE:
bit_width = 3;
break;
default:
return -EINVAL;
}
for (rate = 0; rate < ARRAY_SIZE(jz4770_codec_sample_rates); rate++) {
if (jz4770_codec_sample_rates[rate] == params_rate(params))
break;
}
if (rate == ARRAY_SIZE(jz4770_codec_sample_rates))
return -EINVAL;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
regmap_update_bits(codec->regmap, JZ4770_CODEC_REG_AICR_DAC,
REG_AICR_DAC_ADWL_MASK,
bit_width << REG_AICR_DAC_ADWL_OFFSET);
regmap_update_bits(codec->regmap, JZ4770_CODEC_REG_FCR_DAC,
REG_FCR_DAC_FREQ_MASK,
rate << REG_FCR_DAC_FREQ_OFFSET);
} else {
regmap_update_bits(codec->regmap, JZ4770_CODEC_REG_AICR_ADC,
REG_AICR_ADC_ADWL_MASK,
bit_width << REG_AICR_ADC_ADWL_OFFSET);
regmap_update_bits(codec->regmap, JZ4770_CODEC_REG_FCR_ADC,
REG_FCR_ADC_FREQ_MASK,
rate << REG_FCR_ADC_FREQ_OFFSET);
}
return 0;
}
static const struct snd_soc_dai_ops jz4770_codec_dai_ops = {
.startup = jz4770_codec_startup,
.shutdown = jz4770_codec_shutdown,
.hw_params = jz4770_codec_hw_params,
.trigger = jz4770_codec_pcm_trigger,
.mute_stream = jz4770_codec_mute_stream,
.no_capture_mute = 1,
};
#define JZ_CODEC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S18_3LE | \
SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_3LE)
static struct snd_soc_dai_driver jz4770_codec_dai = {
.name = "jz4770-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = JZ_CODEC_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = JZ_CODEC_FORMATS,
},
.ops = &jz4770_codec_dai_ops,
};
static bool jz4770_codec_volatile(struct device *dev, unsigned int reg)
{
return reg == JZ4770_CODEC_REG_SR || reg == JZ4770_CODEC_REG_IFR;
}
static bool jz4770_codec_readable(struct device *dev, unsigned int reg)
{
switch (reg) {
case JZ4770_CODEC_REG_MISSING_REG1:
case JZ4770_CODEC_REG_MISSING_REG2:
return false;
default:
return true;
}
}
static bool jz4770_codec_writeable(struct device *dev, unsigned int reg)
{
switch (reg) {
case JZ4770_CODEC_REG_SR:
case JZ4770_CODEC_REG_MISSING_REG1:
case JZ4770_CODEC_REG_MISSING_REG2:
return false;
default:
return true;
}
}
static int jz4770_codec_io_wait(struct jz_codec *codec)
{
u32 reg;
return readl_poll_timeout(codec->base + ICDC_RGADW_OFFSET, reg,
!(reg & ICDC_RGADW_RGWR),
1000, 1 * USEC_PER_SEC);
}
static int jz4770_codec_reg_read(void *context, unsigned int reg,
unsigned int *val)
{
struct jz_codec *codec = context;
unsigned int i;
u32 tmp;
int ret;
ret = jz4770_codec_io_wait(codec);
if (ret)
return ret;
tmp = readl(codec->base + ICDC_RGADW_OFFSET);
tmp = (tmp & ~ICDC_RGADW_RGADDR_MASK)
| (reg << ICDC_RGADW_RGADDR_OFFSET);
writel(tmp, codec->base + ICDC_RGADW_OFFSET);
/* wait 6+ cycles */
for (i = 0; i < 6; i++)
*val = readl(codec->base + ICDC_RGDATA_OFFSET) &
ICDC_RGDATA_RGDOUT_MASK;
return 0;
}
static int jz4770_codec_reg_write(void *context, unsigned int reg,
unsigned int val)
{
struct jz_codec *codec = context;
int ret;
ret = jz4770_codec_io_wait(codec);
if (ret)
return ret;
writel(ICDC_RGADW_RGWR | (reg << ICDC_RGADW_RGADDR_OFFSET) | val,
codec->base + ICDC_RGADW_OFFSET);
ret = jz4770_codec_io_wait(codec);
if (ret)
return ret;
return 0;
}
static const u8 jz4770_codec_reg_defaults[] = {
0x00, 0xC3, 0xC3, 0x90, 0x98, 0xFF, 0x90, 0xB1,
0x11, 0x10, 0x00, 0x03, 0x00, 0x00, 0x40, 0x00,
0xFF, 0x00, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x34,
0x07, 0x44, 0x1F, 0x00
};
static struct regmap_config jz4770_codec_regmap_config = {
.reg_bits = 7,
.val_bits = 8,
.max_register = JZ4770_CODEC_REG_AGC5,
.volatile_reg = jz4770_codec_volatile,
.readable_reg = jz4770_codec_readable,
.writeable_reg = jz4770_codec_writeable,
.reg_read = jz4770_codec_reg_read,
.reg_write = jz4770_codec_reg_write,
.reg_defaults_raw = jz4770_codec_reg_defaults,
.num_reg_defaults_raw = ARRAY_SIZE(jz4770_codec_reg_defaults),
.cache_type = REGCACHE_FLAT,
};
static int jz4770_codec_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct jz_codec *codec;
int ret;
codec = devm_kzalloc(dev, sizeof(*codec), GFP_KERNEL);
if (!codec)
return -ENOMEM;
codec->dev = dev;
codec->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(codec->base))
return PTR_ERR(codec->base);
codec->regmap = devm_regmap_init(dev, NULL, codec,
&jz4770_codec_regmap_config);
if (IS_ERR(codec->regmap))
return PTR_ERR(codec->regmap);
codec->clk = devm_clk_get(dev, "aic");
if (IS_ERR(codec->clk))
return PTR_ERR(codec->clk);
platform_set_drvdata(pdev, codec);
ret = devm_snd_soc_register_component(dev, &jz4770_codec_soc_codec_dev,
&jz4770_codec_dai, 1);
if (ret) {
dev_err(dev, "Failed to register codec: %d\n", ret);
return ret;
}
return 0;
}
static const struct of_device_id jz4770_codec_of_matches[] = {
{ .compatible = "ingenic,jz4770-codec", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, jz4770_codec_of_matches);
static struct platform_driver jz4770_codec_driver = {
.probe = jz4770_codec_probe,
.driver = {
.name = "jz4770-codec",
.of_match_table = jz4770_codec_of_matches,
},
};
module_platform_driver(jz4770_codec_driver);
MODULE_DESCRIPTION("JZ4770 SoC internal codec driver");
MODULE_AUTHOR("Maarten ter Huurne <[email protected]>");
MODULE_AUTHOR("Paul Cercueil <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/jz4770.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm9705.c -- ALSA Soc WM9705 codec support
*
* Copyright 2008 Ian Molton <[email protected]>
*/
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/mfd/wm97xx.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/ac97_codec.h>
#include <sound/ac97/codec.h>
#include <sound/ac97/compat.h>
#include <sound/initval.h>
#include <sound/soc.h>
#define WM9705_VENDOR_ID 0x574d4c05
#define WM9705_VENDOR_ID_MASK 0xffffffff
struct wm9705_priv {
struct snd_ac97 *ac97;
struct wm97xx_platform_data *mfd_pdata;
};
static const struct reg_default wm9705_reg_defaults[] = {
{ 0x02, 0x8000 },
{ 0x04, 0x8000 },
{ 0x06, 0x8000 },
{ 0x0a, 0x8000 },
{ 0x0c, 0x8008 },
{ 0x0e, 0x8008 },
{ 0x10, 0x8808 },
{ 0x12, 0x8808 },
{ 0x14, 0x8808 },
{ 0x16, 0x8808 },
{ 0x18, 0x8808 },
{ 0x1a, 0x0000 },
{ 0x1c, 0x8000 },
{ 0x20, 0x0000 },
{ 0x22, 0x0000 },
{ 0x26, 0x000f },
{ 0x28, 0x0605 },
{ 0x2a, 0x0000 },
{ 0x2c, 0xbb80 },
{ 0x32, 0xbb80 },
{ 0x34, 0x2000 },
{ 0x5a, 0x0000 },
{ 0x5c, 0x0000 },
{ 0x72, 0x0808 },
{ 0x74, 0x0000 },
{ 0x76, 0x0006 },
{ 0x78, 0x0000 },
{ 0x7a, 0x0000 },
};
static const struct regmap_config wm9705_regmap_config = {
.reg_bits = 16,
.reg_stride = 2,
.val_bits = 16,
.max_register = 0x7e,
.cache_type = REGCACHE_MAPLE,
.volatile_reg = regmap_ac97_default_volatile,
.reg_defaults = wm9705_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm9705_reg_defaults),
};
static const struct snd_kcontrol_new wm9705_snd_ac97_controls[] = {
SOC_DOUBLE("Master Playback Volume", AC97_MASTER, 8, 0, 31, 1),
SOC_SINGLE("Master Playback Switch", AC97_MASTER, 15, 1, 1),
SOC_DOUBLE("Headphone Playback Volume", AC97_HEADPHONE, 8, 0, 31, 1),
SOC_SINGLE("Headphone Playback Switch", AC97_HEADPHONE, 15, 1, 1),
SOC_DOUBLE("PCM Playback Volume", AC97_PCM, 8, 0, 31, 1),
SOC_SINGLE("PCM Playback Switch", AC97_PCM, 15, 1, 1),
SOC_SINGLE("Mono Playback Volume", AC97_MASTER_MONO, 0, 31, 1),
SOC_SINGLE("Mono Playback Switch", AC97_MASTER_MONO, 15, 1, 1),
SOC_SINGLE("PCBeep Playback Volume", AC97_PC_BEEP, 1, 15, 1),
SOC_SINGLE("Phone Playback Volume", AC97_PHONE, 0, 31, 1),
SOC_DOUBLE("Line Playback Volume", AC97_LINE, 8, 0, 31, 1),
SOC_DOUBLE("CD Playback Volume", AC97_CD, 8, 0, 31, 1),
SOC_SINGLE("Mic Playback Volume", AC97_MIC, 0, 31, 1),
SOC_SINGLE("Mic 20dB Boost Switch", AC97_MIC, 6, 1, 0),
SOC_DOUBLE("Capture Volume", AC97_REC_GAIN, 8, 0, 15, 0),
SOC_SINGLE("Capture Switch", AC97_REC_GAIN, 15, 1, 1),
};
static const char *wm9705_mic[] = {"Mic 1", "Mic 2"};
static const char *wm9705_rec_sel[] = {"Mic", "CD", "NC", "NC",
"Line", "Stereo Mix", "Mono Mix", "Phone"};
static SOC_ENUM_SINGLE_DECL(wm9705_enum_mic,
AC97_GENERAL_PURPOSE, 8, wm9705_mic);
static SOC_ENUM_SINGLE_DECL(wm9705_enum_rec_l,
AC97_REC_SEL, 8, wm9705_rec_sel);
static SOC_ENUM_SINGLE_DECL(wm9705_enum_rec_r,
AC97_REC_SEL, 0, wm9705_rec_sel);
/* Headphone Mixer */
static const struct snd_kcontrol_new wm9705_hp_mixer_controls[] = {
SOC_DAPM_SINGLE("PCBeep Playback Switch", AC97_PC_BEEP, 15, 1, 1),
SOC_DAPM_SINGLE("CD Playback Switch", AC97_CD, 15, 1, 1),
SOC_DAPM_SINGLE("Mic Playback Switch", AC97_MIC, 15, 1, 1),
SOC_DAPM_SINGLE("Phone Playback Switch", AC97_PHONE, 15, 1, 1),
SOC_DAPM_SINGLE("Line Playback Switch", AC97_LINE, 15, 1, 1),
};
/* Mic source */
static const struct snd_kcontrol_new wm9705_mic_src_controls =
SOC_DAPM_ENUM("Route", wm9705_enum_mic);
/* Capture source */
static const struct snd_kcontrol_new wm9705_capture_selectl_controls =
SOC_DAPM_ENUM("Route", wm9705_enum_rec_l);
static const struct snd_kcontrol_new wm9705_capture_selectr_controls =
SOC_DAPM_ENUM("Route", wm9705_enum_rec_r);
/* DAPM widgets */
static const struct snd_soc_dapm_widget wm9705_dapm_widgets[] = {
SND_SOC_DAPM_MUX("Mic Source", SND_SOC_NOPM, 0, 0,
&wm9705_mic_src_controls),
SND_SOC_DAPM_MUX("Left Capture Source", SND_SOC_NOPM, 0, 0,
&wm9705_capture_selectl_controls),
SND_SOC_DAPM_MUX("Right Capture Source", SND_SOC_NOPM, 0, 0,
&wm9705_capture_selectr_controls),
SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback",
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback",
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_MIXER_NAMED_CTL("HP Mixer", SND_SOC_NOPM, 0, 0,
&wm9705_hp_mixer_controls[0],
ARRAY_SIZE(wm9705_hp_mixer_controls)),
SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_ADC("Left ADC", "Left HiFi Capture", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("Right ADC", "Right HiFi Capture", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_PGA("Headphone PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Speaker PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Line PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Line out PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Mono PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Phone PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Mic PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("PCBEEP PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("CD PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("ADC PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("HPOUTL"),
SND_SOC_DAPM_OUTPUT("HPOUTR"),
SND_SOC_DAPM_OUTPUT("LOUT"),
SND_SOC_DAPM_OUTPUT("ROUT"),
SND_SOC_DAPM_OUTPUT("MONOOUT"),
SND_SOC_DAPM_INPUT("PHONE"),
SND_SOC_DAPM_INPUT("LINEINL"),
SND_SOC_DAPM_INPUT("LINEINR"),
SND_SOC_DAPM_INPUT("CDINL"),
SND_SOC_DAPM_INPUT("CDINR"),
SND_SOC_DAPM_INPUT("PCBEEP"),
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_INPUT("MIC2"),
};
/* Audio map
* WM9705 has no switches to disable the route from the inputs to the HP mixer
* so in order to prevent active inputs from forcing the audio outputs to be
* constantly enabled, we use the mutes on those inputs to simulate such
* controls.
*/
static const struct snd_soc_dapm_route wm9705_audio_map[] = {
/* HP mixer */
{"HP Mixer", "PCBeep Playback Switch", "PCBEEP PGA"},
{"HP Mixer", "CD Playback Switch", "CD PGA"},
{"HP Mixer", "Mic Playback Switch", "Mic PGA"},
{"HP Mixer", "Phone Playback Switch", "Phone PGA"},
{"HP Mixer", "Line Playback Switch", "Line PGA"},
{"HP Mixer", NULL, "Left DAC"},
{"HP Mixer", NULL, "Right DAC"},
/* mono mixer */
{"Mono Mixer", NULL, "HP Mixer"},
/* outputs */
{"Headphone PGA", NULL, "HP Mixer"},
{"HPOUTL", NULL, "Headphone PGA"},
{"HPOUTR", NULL, "Headphone PGA"},
{"Line out PGA", NULL, "HP Mixer"},
{"LOUT", NULL, "Line out PGA"},
{"ROUT", NULL, "Line out PGA"},
{"Mono PGA", NULL, "Mono Mixer"},
{"MONOOUT", NULL, "Mono PGA"},
/* inputs */
{"CD PGA", NULL, "CDINL"},
{"CD PGA", NULL, "CDINR"},
{"Line PGA", NULL, "LINEINL"},
{"Line PGA", NULL, "LINEINR"},
{"Phone PGA", NULL, "PHONE"},
{"Mic Source", "Mic 1", "MIC1"},
{"Mic Source", "Mic 2", "MIC2"},
{"Mic PGA", NULL, "Mic Source"},
{"PCBEEP PGA", NULL, "PCBEEP"},
/* Left capture selector */
{"Left Capture Source", "Mic", "Mic Source"},
{"Left Capture Source", "CD", "CDINL"},
{"Left Capture Source", "Line", "LINEINL"},
{"Left Capture Source", "Stereo Mix", "HP Mixer"},
{"Left Capture Source", "Mono Mix", "HP Mixer"},
{"Left Capture Source", "Phone", "PHONE"},
/* Right capture source */
{"Right Capture Source", "Mic", "Mic Source"},
{"Right Capture Source", "CD", "CDINR"},
{"Right Capture Source", "Line", "LINEINR"},
{"Right Capture Source", "Stereo Mix", "HP Mixer"},
{"Right Capture Source", "Mono Mix", "HP Mixer"},
{"Right Capture Source", "Phone", "PHONE"},
{"ADC PGA", NULL, "Left Capture Source"},
{"ADC PGA", NULL, "Right Capture Source"},
/* ADC's */
{"Left ADC", NULL, "ADC PGA"},
{"Right ADC", NULL, "ADC PGA"},
};
static int ac97_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
int reg;
snd_soc_component_update_bits(component, AC97_EXTENDED_STATUS, 0x1, 0x1);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
reg = AC97_PCM_FRONT_DAC_RATE;
else
reg = AC97_PCM_LR_ADC_RATE;
return snd_soc_component_write(component, reg, substream->runtime->rate);
}
#define WM9705_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | \
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000)
static const struct snd_soc_dai_ops wm9705_dai_ops = {
.prepare = ac97_prepare,
};
static struct snd_soc_dai_driver wm9705_dai[] = {
{
.name = "wm9705-hifi",
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM9705_AC97_RATES,
.formats = SND_SOC_STD_AC97_FMTS,
},
.capture = {
.stream_name = "HiFi Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM9705_AC97_RATES,
.formats = SND_SOC_STD_AC97_FMTS,
},
.ops = &wm9705_dai_ops,
},
{
.name = "wm9705-aux",
.playback = {
.stream_name = "Aux Playback",
.channels_min = 1,
.channels_max = 1,
.rates = WM9705_AC97_RATES,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
}
};
#ifdef CONFIG_PM
static int wm9705_soc_suspend(struct snd_soc_component *component)
{
regcache_cache_bypass(component->regmap, true);
snd_soc_component_write(component, AC97_POWERDOWN, 0xffff);
regcache_cache_bypass(component->regmap, false);
return 0;
}
static int wm9705_soc_resume(struct snd_soc_component *component)
{
struct wm9705_priv *wm9705 = snd_soc_component_get_drvdata(component);
int ret;
ret = snd_ac97_reset(wm9705->ac97, true, WM9705_VENDOR_ID,
WM9705_VENDOR_ID_MASK);
if (ret < 0)
return ret;
snd_soc_component_cache_sync(component);
return 0;
}
#else
#define wm9705_soc_suspend NULL
#define wm9705_soc_resume NULL
#endif
static int wm9705_soc_probe(struct snd_soc_component *component)
{
struct wm9705_priv *wm9705 = snd_soc_component_get_drvdata(component);
struct regmap *regmap;
if (wm9705->mfd_pdata) {
wm9705->ac97 = wm9705->mfd_pdata->ac97;
regmap = wm9705->mfd_pdata->regmap;
} else if (IS_ENABLED(CONFIG_SND_SOC_AC97_BUS)) {
wm9705->ac97 = snd_soc_new_ac97_component(component, WM9705_VENDOR_ID,
WM9705_VENDOR_ID_MASK);
if (IS_ERR(wm9705->ac97)) {
dev_err(component->dev, "Failed to register AC97 codec\n");
return PTR_ERR(wm9705->ac97);
}
regmap = regmap_init_ac97(wm9705->ac97, &wm9705_regmap_config);
if (IS_ERR(regmap)) {
snd_soc_free_ac97_component(wm9705->ac97);
return PTR_ERR(regmap);
}
} else {
return -ENXIO;
}
snd_soc_component_set_drvdata(component, wm9705->ac97);
snd_soc_component_init_regmap(component, regmap);
return 0;
}
static void wm9705_soc_remove(struct snd_soc_component *component)
{
struct wm9705_priv *wm9705 = snd_soc_component_get_drvdata(component);
if (IS_ENABLED(CONFIG_SND_SOC_AC97_BUS) && !wm9705->mfd_pdata) {
snd_soc_component_exit_regmap(component);
snd_soc_free_ac97_component(wm9705->ac97);
}
}
static const struct snd_soc_component_driver soc_component_dev_wm9705 = {
.probe = wm9705_soc_probe,
.remove = wm9705_soc_remove,
.suspend = wm9705_soc_suspend,
.resume = wm9705_soc_resume,
.controls = wm9705_snd_ac97_controls,
.num_controls = ARRAY_SIZE(wm9705_snd_ac97_controls),
.dapm_widgets = wm9705_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm9705_dapm_widgets),
.dapm_routes = wm9705_audio_map,
.num_dapm_routes = ARRAY_SIZE(wm9705_audio_map),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int wm9705_probe(struct platform_device *pdev)
{
struct wm9705_priv *wm9705;
wm9705 = devm_kzalloc(&pdev->dev, sizeof(*wm9705), GFP_KERNEL);
if (wm9705 == NULL)
return -ENOMEM;
wm9705->mfd_pdata = dev_get_platdata(&pdev->dev);
platform_set_drvdata(pdev, wm9705);
return devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_wm9705, wm9705_dai, ARRAY_SIZE(wm9705_dai));
}
static struct platform_driver wm9705_codec_driver = {
.driver = {
.name = "wm9705-codec",
},
.probe = wm9705_probe,
};
module_platform_driver(wm9705_codec_driver);
MODULE_DESCRIPTION("ASoC WM9705 driver");
MODULE_AUTHOR("Ian Molton");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/wm9705.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// rt712-sdca-sdw.c -- rt712 SDCA ALSA SoC audio driver
//
// Copyright(c) 2023 Realtek Semiconductor Corp.
//
//
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/soundwire/sdw_registers.h>
#include "rt712-sdca.h"
#include "rt712-sdca-sdw.h"
static bool rt712_sdca_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x201a ... 0x201f:
case 0x2029 ... 0x202a:
case 0x202d ... 0x2034:
case 0x2230 ... 0x2232:
case 0x2f01 ... 0x2f0a:
case 0x2f35 ... 0x2f36:
case 0x2f50:
case 0x2f54:
case 0x2f58 ... 0x2f5d:
case 0x3201:
case 0x320c:
case 0x3301 ... 0x3303:
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_GE49, RT712_SDCA_CTL_SELECTED_MODE, 0):
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_GE49, RT712_SDCA_CTL_DETECTED_MODE, 0):
case SDW_SDCA_CTL(FUNC_NUM_HID, RT712_SDCA_ENT_HID01, RT712_SDCA_CTL_HIDTX_CURRENT_OWNER, 0) ...
SDW_SDCA_CTL(FUNC_NUM_HID, RT712_SDCA_ENT_HID01, RT712_SDCA_CTL_HIDTX_MESSAGE_LENGTH, 0):
case RT712_BUF_ADDR_HID1 ... RT712_BUF_ADDR_HID2:
return true;
default:
return false;
}
}
static bool rt712_sdca_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x201b:
case 0x201c:
case 0x201d:
case 0x201f:
case 0x202d ... 0x202f:
case 0x2230:
case 0x2f01:
case 0x2f35:
case 0x320c:
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_GE49, RT712_SDCA_CTL_DETECTED_MODE, 0):
case SDW_SDCA_CTL(FUNC_NUM_HID, RT712_SDCA_ENT_HID01, RT712_SDCA_CTL_HIDTX_CURRENT_OWNER, 0) ...
SDW_SDCA_CTL(FUNC_NUM_HID, RT712_SDCA_ENT_HID01, RT712_SDCA_CTL_HIDTX_MESSAGE_LENGTH, 0):
case RT712_BUF_ADDR_HID1 ... RT712_BUF_ADDR_HID2:
return true;
default:
return false;
}
}
static bool rt712_sdca_mbq_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x2000000 ... 0x200008e:
case 0x5300000 ... 0x530000e:
case 0x5400000 ... 0x540000e:
case 0x5600000 ... 0x5600008:
case 0x5700000 ... 0x570000d:
case 0x5800000 ... 0x5800021:
case 0x5900000 ... 0x5900028:
case 0x5a00000 ... 0x5a00009:
case 0x5b00000 ... 0x5b00051:
case 0x5c00000 ... 0x5c0009a:
case 0x5d00000 ... 0x5d00009:
case 0x5f00000 ... 0x5f00030:
case 0x6100000 ... 0x6100068:
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_USER_FU05, RT712_SDCA_CTL_FU_VOLUME, CH_L):
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_USER_FU05, RT712_SDCA_CTL_FU_VOLUME, CH_R):
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_USER_FU0F, RT712_SDCA_CTL_FU_VOLUME, CH_L):
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_USER_FU0F, RT712_SDCA_CTL_FU_VOLUME, CH_R):
case SDW_SDCA_CTL(FUNC_NUM_AMP, RT712_SDCA_ENT_USER_FU06, RT712_SDCA_CTL_FU_VOLUME, CH_L):
case SDW_SDCA_CTL(FUNC_NUM_AMP, RT712_SDCA_ENT_USER_FU06, RT712_SDCA_CTL_FU_VOLUME, CH_R):
return true;
default:
return false;
}
}
static bool rt712_sdca_mbq_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x2000000:
case 0x200001a:
case 0x2000024:
case 0x2000046:
case 0x200008a:
case 0x5800000:
case 0x5800001:
case 0x6100008:
return true;
default:
return false;
}
}
static const struct regmap_config rt712_sdca_regmap = {
.reg_bits = 32,
.val_bits = 8,
.readable_reg = rt712_sdca_readable_register,
.volatile_reg = rt712_sdca_volatile_register,
.max_register = 0x44ffffff,
.reg_defaults = rt712_sdca_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(rt712_sdca_reg_defaults),
.cache_type = REGCACHE_MAPLE,
.use_single_read = true,
.use_single_write = true,
};
static const struct regmap_config rt712_sdca_mbq_regmap = {
.name = "sdw-mbq",
.reg_bits = 32,
.val_bits = 16,
.readable_reg = rt712_sdca_mbq_readable_register,
.volatile_reg = rt712_sdca_mbq_volatile_register,
.max_register = 0x41000312,
.reg_defaults = rt712_sdca_mbq_defaults,
.num_reg_defaults = ARRAY_SIZE(rt712_sdca_mbq_defaults),
.cache_type = REGCACHE_MAPLE,
.use_single_read = true,
.use_single_write = true,
};
static int rt712_sdca_update_status(struct sdw_slave *slave,
enum sdw_slave_status status)
{
struct rt712_sdca_priv *rt712 = dev_get_drvdata(&slave->dev);
if (status == SDW_SLAVE_UNATTACHED)
rt712->hw_init = false;
if (status == SDW_SLAVE_ATTACHED) {
if (rt712->hs_jack) {
/*
* Due to the SCP_SDCA_INTMASK will be cleared by any reset, and then
* if the device attached again, we will need to set the setting back.
* It could avoid losing the jack detection interrupt.
* This also could sync with the cache value as the rt712_sdca_jack_init set.
*/
sdw_write_no_pm(rt712->slave, SDW_SCP_SDCA_INTMASK1,
SDW_SCP_SDCA_INTMASK_SDCA_0);
sdw_write_no_pm(rt712->slave, SDW_SCP_SDCA_INTMASK2,
SDW_SCP_SDCA_INTMASK_SDCA_8);
}
}
/*
* Perform initialization only if slave status is present and
* hw_init flag is false
*/
if (rt712->hw_init || status != SDW_SLAVE_ATTACHED)
return 0;
/* perform I/O transfers required for Slave initialization */
return rt712_sdca_io_init(&slave->dev, slave);
}
static int rt712_sdca_read_prop(struct sdw_slave *slave)
{
struct sdw_slave_prop *prop = &slave->prop;
int nval;
int i, j;
u32 bit;
unsigned long addr;
struct sdw_dpn_prop *dpn;
prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
prop->paging_support = true;
/* first we need to allocate memory for set bits in port lists */
prop->source_ports = BIT(4); /* BITMAP: 00010000 */
prop->sink_ports = BIT(3) | BIT(1); /* BITMAP: 00001010 */
nval = hweight32(prop->source_ports);
prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
sizeof(*prop->src_dpn_prop), GFP_KERNEL);
if (!prop->src_dpn_prop)
return -ENOMEM;
i = 0;
dpn = prop->src_dpn_prop;
addr = prop->source_ports;
for_each_set_bit(bit, &addr, 32) {
dpn[i].num = bit;
dpn[i].type = SDW_DPN_FULL;
dpn[i].simple_ch_prep_sm = true;
dpn[i].ch_prep_timeout = 10;
i++;
}
/* do this again for sink now */
nval = hweight32(prop->sink_ports);
prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
sizeof(*prop->sink_dpn_prop), GFP_KERNEL);
if (!prop->sink_dpn_prop)
return -ENOMEM;
j = 0;
dpn = prop->sink_dpn_prop;
addr = prop->sink_ports;
for_each_set_bit(bit, &addr, 32) {
dpn[j].num = bit;
dpn[j].type = SDW_DPN_FULL;
dpn[j].simple_ch_prep_sm = true;
dpn[j].ch_prep_timeout = 10;
j++;
}
/* set the timeout values */
prop->clk_stop_timeout = 1380;
/* wake-up event */
prop->wake_capable = 1;
return 0;
}
static int rt712_sdca_interrupt_callback(struct sdw_slave *slave,
struct sdw_slave_intr_status *status)
{
struct rt712_sdca_priv *rt712 = dev_get_drvdata(&slave->dev);
int ret, stat;
int count = 0, retry = 3;
unsigned int sdca_cascade, scp_sdca_stat1, scp_sdca_stat2 = 0;
dev_dbg(&slave->dev,
"%s control_port_stat=%x, sdca_cascade=%x", __func__,
status->control_port, status->sdca_cascade);
if (cancel_delayed_work_sync(&rt712->jack_detect_work)) {
dev_warn(&slave->dev, "%s the pending delayed_work was cancelled", __func__);
/* avoid the HID owner doesn't change to device */
if (rt712->scp_sdca_stat2)
scp_sdca_stat2 = rt712->scp_sdca_stat2;
}
/*
* The critical section below intentionally protects a rather large piece of code.
* We don't want to allow the system suspend to disable an interrupt while we are
* processing it, which could be problematic given the quirky SoundWire interrupt
* scheme. We do want however to prevent new workqueues from being scheduled if
* the disable_irq flag was set during system suspend.
*/
mutex_lock(&rt712->disable_irq_lock);
ret = sdw_read_no_pm(rt712->slave, SDW_SCP_SDCA_INT1);
if (ret < 0)
goto io_error;
rt712->scp_sdca_stat1 = ret;
ret = sdw_read_no_pm(rt712->slave, SDW_SCP_SDCA_INT2);
if (ret < 0)
goto io_error;
rt712->scp_sdca_stat2 = ret;
if (scp_sdca_stat2)
rt712->scp_sdca_stat2 |= scp_sdca_stat2;
do {
/* clear flag */
ret = sdw_read_no_pm(rt712->slave, SDW_SCP_SDCA_INT1);
if (ret < 0)
goto io_error;
if (ret & SDW_SCP_SDCA_INTMASK_SDCA_0) {
ret = sdw_write_no_pm(rt712->slave, SDW_SCP_SDCA_INT1,
SDW_SCP_SDCA_INTMASK_SDCA_0);
if (ret < 0)
goto io_error;
}
ret = sdw_read_no_pm(rt712->slave, SDW_SCP_SDCA_INT2);
if (ret < 0)
goto io_error;
if (ret & SDW_SCP_SDCA_INTMASK_SDCA_8) {
ret = sdw_write_no_pm(rt712->slave, SDW_SCP_SDCA_INT2,
SDW_SCP_SDCA_INTMASK_SDCA_8);
if (ret < 0)
goto io_error;
}
/* check if flag clear or not */
ret = sdw_read_no_pm(rt712->slave, SDW_DP0_INT);
if (ret < 0)
goto io_error;
sdca_cascade = ret & SDW_DP0_SDCA_CASCADE;
ret = sdw_read_no_pm(rt712->slave, SDW_SCP_SDCA_INT1);
if (ret < 0)
goto io_error;
scp_sdca_stat1 = ret & SDW_SCP_SDCA_INTMASK_SDCA_0;
ret = sdw_read_no_pm(rt712->slave, SDW_SCP_SDCA_INT2);
if (ret < 0)
goto io_error;
scp_sdca_stat2 = ret & SDW_SCP_SDCA_INTMASK_SDCA_8;
stat = scp_sdca_stat1 || scp_sdca_stat2 || sdca_cascade;
count++;
} while (stat != 0 && count < retry);
if (stat)
dev_warn(&slave->dev,
"%s scp_sdca_stat1=0x%x, scp_sdca_stat2=0x%x\n", __func__,
rt712->scp_sdca_stat1, rt712->scp_sdca_stat2);
if (status->sdca_cascade && !rt712->disable_irq)
mod_delayed_work(system_power_efficient_wq,
&rt712->jack_detect_work, msecs_to_jiffies(30));
mutex_unlock(&rt712->disable_irq_lock);
return 0;
io_error:
mutex_unlock(&rt712->disable_irq_lock);
pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret);
return ret;
}
static struct sdw_slave_ops rt712_sdca_slave_ops = {
.read_prop = rt712_sdca_read_prop,
.interrupt_callback = rt712_sdca_interrupt_callback,
.update_status = rt712_sdca_update_status,
};
static int rt712_sdca_sdw_probe(struct sdw_slave *slave,
const struct sdw_device_id *id)
{
struct regmap *regmap, *mbq_regmap;
/* Regmap Initialization */
mbq_regmap = devm_regmap_init_sdw_mbq(slave, &rt712_sdca_mbq_regmap);
if (IS_ERR(mbq_regmap))
return PTR_ERR(mbq_regmap);
regmap = devm_regmap_init_sdw(slave, &rt712_sdca_regmap);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return rt712_sdca_init(&slave->dev, regmap, mbq_regmap, slave);
}
static int rt712_sdca_sdw_remove(struct sdw_slave *slave)
{
struct rt712_sdca_priv *rt712 = dev_get_drvdata(&slave->dev);
if (rt712->hw_init) {
cancel_delayed_work_sync(&rt712->jack_detect_work);
cancel_delayed_work_sync(&rt712->jack_btn_check_work);
}
pm_runtime_disable(&slave->dev);
mutex_destroy(&rt712->calibrate_mutex);
mutex_destroy(&rt712->disable_irq_lock);
return 0;
}
static const struct sdw_device_id rt712_sdca_id[] = {
SDW_SLAVE_ENTRY_EXT(0x025d, 0x712, 0x3, 0x1, 0),
SDW_SLAVE_ENTRY_EXT(0x025d, 0x713, 0x3, 0x1, 0),
SDW_SLAVE_ENTRY_EXT(0x025d, 0x716, 0x3, 0x1, 0),
SDW_SLAVE_ENTRY_EXT(0x025d, 0x717, 0x3, 0x1, 0),
{},
};
MODULE_DEVICE_TABLE(sdw, rt712_sdca_id);
static int __maybe_unused rt712_sdca_dev_suspend(struct device *dev)
{
struct rt712_sdca_priv *rt712 = dev_get_drvdata(dev);
if (!rt712->hw_init)
return 0;
cancel_delayed_work_sync(&rt712->jack_detect_work);
cancel_delayed_work_sync(&rt712->jack_btn_check_work);
regcache_cache_only(rt712->regmap, true);
regcache_cache_only(rt712->mbq_regmap, true);
return 0;
}
static int __maybe_unused rt712_sdca_dev_system_suspend(struct device *dev)
{
struct rt712_sdca_priv *rt712_sdca = dev_get_drvdata(dev);
struct sdw_slave *slave = dev_to_sdw_dev(dev);
int ret1, ret2;
if (!rt712_sdca->hw_init)
return 0;
/*
* prevent new interrupts from being handled after the
* deferred work completes and before the parent disables
* interrupts on the link
*/
mutex_lock(&rt712_sdca->disable_irq_lock);
rt712_sdca->disable_irq = true;
ret1 = sdw_update_no_pm(slave, SDW_SCP_SDCA_INTMASK1,
SDW_SCP_SDCA_INTMASK_SDCA_0, 0);
ret2 = sdw_update_no_pm(slave, SDW_SCP_SDCA_INTMASK2,
SDW_SCP_SDCA_INTMASK_SDCA_8, 0);
mutex_unlock(&rt712_sdca->disable_irq_lock);
if (ret1 < 0 || ret2 < 0) {
/* log but don't prevent suspend from happening */
dev_dbg(&slave->dev, "%s: could not disable SDCA interrupts\n:", __func__);
}
return rt712_sdca_dev_suspend(dev);
}
#define RT712_PROBE_TIMEOUT 5000
static int __maybe_unused rt712_sdca_dev_resume(struct device *dev)
{
struct sdw_slave *slave = dev_to_sdw_dev(dev);
struct rt712_sdca_priv *rt712 = dev_get_drvdata(dev);
unsigned long time;
if (!rt712->first_hw_init)
return 0;
if (!slave->unattach_request) {
if (rt712->disable_irq == true) {
mutex_lock(&rt712->disable_irq_lock);
sdw_write_no_pm(slave, SDW_SCP_SDCA_INTMASK1, SDW_SCP_SDCA_INTMASK_SDCA_0);
sdw_write_no_pm(slave, SDW_SCP_SDCA_INTMASK2, SDW_SCP_SDCA_INTMASK_SDCA_8);
rt712->disable_irq = false;
mutex_unlock(&rt712->disable_irq_lock);
}
goto regmap_sync;
}
time = wait_for_completion_timeout(&slave->initialization_complete,
msecs_to_jiffies(RT712_PROBE_TIMEOUT));
if (!time) {
dev_err(&slave->dev, "Initialization not complete, timed out\n");
sdw_show_ping_status(slave->bus, true);
return -ETIMEDOUT;
}
regmap_sync:
slave->unattach_request = 0;
regcache_cache_only(rt712->regmap, false);
regcache_sync(rt712->regmap);
regcache_cache_only(rt712->mbq_regmap, false);
regcache_sync(rt712->mbq_regmap);
return 0;
}
static const struct dev_pm_ops rt712_sdca_pm = {
SET_SYSTEM_SLEEP_PM_OPS(rt712_sdca_dev_system_suspend, rt712_sdca_dev_resume)
SET_RUNTIME_PM_OPS(rt712_sdca_dev_suspend, rt712_sdca_dev_resume, NULL)
};
static struct sdw_driver rt712_sdca_sdw_driver = {
.driver = {
.name = "rt712-sdca",
.owner = THIS_MODULE,
.pm = &rt712_sdca_pm,
},
.probe = rt712_sdca_sdw_probe,
.remove = rt712_sdca_sdw_remove,
.ops = &rt712_sdca_slave_ops,
.id_table = rt712_sdca_id,
};
module_sdw_driver(rt712_sdca_sdw_driver);
MODULE_DESCRIPTION("ASoC RT712 SDCA SDW driver");
MODULE_AUTHOR("Shuming Fan <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/rt712-sdca-sdw.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// CS35L56 ALSA SoC audio driver I2C binding
//
// Copyright (C) 2023 Cirrus Logic, Inc. and
// Cirrus Logic International Semiconductor Ltd.
#include <linux/acpi.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/types.h>
#include "cs35l56.h"
static int cs35l56_i2c_probe(struct i2c_client *client)
{
struct cs35l56_private *cs35l56;
struct device *dev = &client->dev;
const struct regmap_config *regmap_config = &cs35l56_regmap_i2c;
int ret;
cs35l56 = devm_kzalloc(dev, sizeof(struct cs35l56_private), GFP_KERNEL);
if (!cs35l56)
return -ENOMEM;
cs35l56->base.dev = dev;
i2c_set_clientdata(client, cs35l56);
cs35l56->base.regmap = devm_regmap_init_i2c(client, regmap_config);
if (IS_ERR(cs35l56->base.regmap)) {
ret = PTR_ERR(cs35l56->base.regmap);
return dev_err_probe(cs35l56->base.dev, ret, "Failed to allocate register map\n");
}
ret = cs35l56_common_probe(cs35l56);
if (ret != 0)
return ret;
ret = cs35l56_init(cs35l56);
if (ret == 0)
ret = cs35l56_irq_request(&cs35l56->base, client->irq);
if (ret < 0)
cs35l56_remove(cs35l56);
return ret;
}
static void cs35l56_i2c_remove(struct i2c_client *client)
{
struct cs35l56_private *cs35l56 = i2c_get_clientdata(client);
cs35l56_remove(cs35l56);
}
static const struct i2c_device_id cs35l56_id_i2c[] = {
{ "cs35l56", 0 },
{}
};
MODULE_DEVICE_TABLE(i2c, cs35l56_id_i2c);
#ifdef CONFIG_ACPI
static const struct acpi_device_id cs35l56_asoc_acpi_match[] = {
{ "CSC355C", 0 },
{},
};
MODULE_DEVICE_TABLE(acpi, cs35l56_asoc_acpi_match);
#endif
static struct i2c_driver cs35l56_i2c_driver = {
.driver = {
.name = "cs35l56",
.pm = &cs35l56_pm_ops_i2c_spi,
.acpi_match_table = ACPI_PTR(cs35l56_asoc_acpi_match),
},
.id_table = cs35l56_id_i2c,
.probe = cs35l56_i2c_probe,
.remove = cs35l56_i2c_remove,
};
module_i2c_driver(cs35l56_i2c_driver);
MODULE_DESCRIPTION("ASoC CS35L56 I2C driver");
MODULE_IMPORT_NS(SND_SOC_CS35L56_CORE);
MODULE_IMPORT_NS(SND_SOC_CS35L56_SHARED);
MODULE_AUTHOR("Richard Fitzgerald <[email protected]>");
MODULE_AUTHOR("Simon Trimmer <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cs35l56-i2c.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* cs53l30.c -- CS53l30 ALSA Soc Audio driver
*
* Copyright 2015 Cirrus Logic, Inc.
*
* Authors: Paul Handrigan <[email protected]>,
* Tim Howe <[email protected]>
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/of_gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/regulator/consumer.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include "cs53l30.h"
#include "cirrus_legacy.h"
#define CS53L30_NUM_SUPPLIES 2
static const char *const cs53l30_supply_names[CS53L30_NUM_SUPPLIES] = {
"VA",
"VP",
};
struct cs53l30_private {
struct regulator_bulk_data supplies[CS53L30_NUM_SUPPLIES];
struct regmap *regmap;
struct gpio_desc *reset_gpio;
struct gpio_desc *mute_gpio;
struct clk *mclk;
bool use_sdout2;
u32 mclk_rate;
};
static const struct reg_default cs53l30_reg_defaults[] = {
{ CS53L30_PWRCTL, CS53L30_PWRCTL_DEFAULT },
{ CS53L30_MCLKCTL, CS53L30_MCLKCTL_DEFAULT },
{ CS53L30_INT_SR_CTL, CS53L30_INT_SR_CTL_DEFAULT },
{ CS53L30_MICBIAS_CTL, CS53L30_MICBIAS_CTL_DEFAULT },
{ CS53L30_ASPCFG_CTL, CS53L30_ASPCFG_CTL_DEFAULT },
{ CS53L30_ASP_CTL1, CS53L30_ASP_CTL1_DEFAULT },
{ CS53L30_ASP_TDMTX_CTL1, CS53L30_ASP_TDMTX_CTLx_DEFAULT },
{ CS53L30_ASP_TDMTX_CTL2, CS53L30_ASP_TDMTX_CTLx_DEFAULT },
{ CS53L30_ASP_TDMTX_CTL3, CS53L30_ASP_TDMTX_CTLx_DEFAULT },
{ CS53L30_ASP_TDMTX_CTL4, CS53L30_ASP_TDMTX_CTLx_DEFAULT },
{ CS53L30_ASP_TDMTX_EN1, CS53L30_ASP_TDMTX_ENx_DEFAULT },
{ CS53L30_ASP_TDMTX_EN2, CS53L30_ASP_TDMTX_ENx_DEFAULT },
{ CS53L30_ASP_TDMTX_EN3, CS53L30_ASP_TDMTX_ENx_DEFAULT },
{ CS53L30_ASP_TDMTX_EN4, CS53L30_ASP_TDMTX_ENx_DEFAULT },
{ CS53L30_ASP_TDMTX_EN5, CS53L30_ASP_TDMTX_ENx_DEFAULT },
{ CS53L30_ASP_TDMTX_EN6, CS53L30_ASP_TDMTX_ENx_DEFAULT },
{ CS53L30_ASP_CTL2, CS53L30_ASP_CTL2_DEFAULT },
{ CS53L30_SFT_RAMP, CS53L30_SFT_RMP_DEFAULT },
{ CS53L30_LRCK_CTL1, CS53L30_LRCK_CTLx_DEFAULT },
{ CS53L30_LRCK_CTL2, CS53L30_LRCK_CTLx_DEFAULT },
{ CS53L30_MUTEP_CTL1, CS53L30_MUTEP_CTL1_DEFAULT },
{ CS53L30_MUTEP_CTL2, CS53L30_MUTEP_CTL2_DEFAULT },
{ CS53L30_INBIAS_CTL1, CS53L30_INBIAS_CTL1_DEFAULT },
{ CS53L30_INBIAS_CTL2, CS53L30_INBIAS_CTL2_DEFAULT },
{ CS53L30_DMIC1_STR_CTL, CS53L30_DMIC1_STR_CTL_DEFAULT },
{ CS53L30_DMIC2_STR_CTL, CS53L30_DMIC2_STR_CTL_DEFAULT },
{ CS53L30_ADCDMIC1_CTL1, CS53L30_ADCDMICx_CTL1_DEFAULT },
{ CS53L30_ADCDMIC1_CTL2, CS53L30_ADCDMIC1_CTL2_DEFAULT },
{ CS53L30_ADC1_CTL3, CS53L30_ADCx_CTL3_DEFAULT },
{ CS53L30_ADC1_NG_CTL, CS53L30_ADCx_NG_CTL_DEFAULT },
{ CS53L30_ADC1A_AFE_CTL, CS53L30_ADCxy_AFE_CTL_DEFAULT },
{ CS53L30_ADC1B_AFE_CTL, CS53L30_ADCxy_AFE_CTL_DEFAULT },
{ CS53L30_ADC1A_DIG_VOL, CS53L30_ADCxy_DIG_VOL_DEFAULT },
{ CS53L30_ADC1B_DIG_VOL, CS53L30_ADCxy_DIG_VOL_DEFAULT },
{ CS53L30_ADCDMIC2_CTL1, CS53L30_ADCDMICx_CTL1_DEFAULT },
{ CS53L30_ADCDMIC2_CTL2, CS53L30_ADCDMIC1_CTL2_DEFAULT },
{ CS53L30_ADC2_CTL3, CS53L30_ADCx_CTL3_DEFAULT },
{ CS53L30_ADC2_NG_CTL, CS53L30_ADCx_NG_CTL_DEFAULT },
{ CS53L30_ADC2A_AFE_CTL, CS53L30_ADCxy_AFE_CTL_DEFAULT },
{ CS53L30_ADC2B_AFE_CTL, CS53L30_ADCxy_AFE_CTL_DEFAULT },
{ CS53L30_ADC2A_DIG_VOL, CS53L30_ADCxy_DIG_VOL_DEFAULT },
{ CS53L30_ADC2B_DIG_VOL, CS53L30_ADCxy_DIG_VOL_DEFAULT },
{ CS53L30_INT_MASK, CS53L30_DEVICE_INT_MASK },
};
static bool cs53l30_volatile_register(struct device *dev, unsigned int reg)
{
if (reg == CS53L30_IS)
return true;
else
return false;
}
static bool cs53l30_writeable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS53L30_DEVID_AB:
case CS53L30_DEVID_CD:
case CS53L30_DEVID_E:
case CS53L30_REVID:
case CS53L30_IS:
return false;
default:
return true;
}
}
static bool cs53l30_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS53L30_DEVID_AB:
case CS53L30_DEVID_CD:
case CS53L30_DEVID_E:
case CS53L30_REVID:
case CS53L30_PWRCTL:
case CS53L30_MCLKCTL:
case CS53L30_INT_SR_CTL:
case CS53L30_MICBIAS_CTL:
case CS53L30_ASPCFG_CTL:
case CS53L30_ASP_CTL1:
case CS53L30_ASP_TDMTX_CTL1:
case CS53L30_ASP_TDMTX_CTL2:
case CS53L30_ASP_TDMTX_CTL3:
case CS53L30_ASP_TDMTX_CTL4:
case CS53L30_ASP_TDMTX_EN1:
case CS53L30_ASP_TDMTX_EN2:
case CS53L30_ASP_TDMTX_EN3:
case CS53L30_ASP_TDMTX_EN4:
case CS53L30_ASP_TDMTX_EN5:
case CS53L30_ASP_TDMTX_EN6:
case CS53L30_ASP_CTL2:
case CS53L30_SFT_RAMP:
case CS53L30_LRCK_CTL1:
case CS53L30_LRCK_CTL2:
case CS53L30_MUTEP_CTL1:
case CS53L30_MUTEP_CTL2:
case CS53L30_INBIAS_CTL1:
case CS53L30_INBIAS_CTL2:
case CS53L30_DMIC1_STR_CTL:
case CS53L30_DMIC2_STR_CTL:
case CS53L30_ADCDMIC1_CTL1:
case CS53L30_ADCDMIC1_CTL2:
case CS53L30_ADC1_CTL3:
case CS53L30_ADC1_NG_CTL:
case CS53L30_ADC1A_AFE_CTL:
case CS53L30_ADC1B_AFE_CTL:
case CS53L30_ADC1A_DIG_VOL:
case CS53L30_ADC1B_DIG_VOL:
case CS53L30_ADCDMIC2_CTL1:
case CS53L30_ADCDMIC2_CTL2:
case CS53L30_ADC2_CTL3:
case CS53L30_ADC2_NG_CTL:
case CS53L30_ADC2A_AFE_CTL:
case CS53L30_ADC2B_AFE_CTL:
case CS53L30_ADC2A_DIG_VOL:
case CS53L30_ADC2B_DIG_VOL:
case CS53L30_INT_MASK:
return true;
default:
return false;
}
}
static DECLARE_TLV_DB_SCALE(adc_boost_tlv, 0, 2000, 0);
static DECLARE_TLV_DB_SCALE(adc_ng_boost_tlv, 0, 3000, 0);
static DECLARE_TLV_DB_SCALE(pga_tlv, -600, 50, 0);
static DECLARE_TLV_DB_SCALE(dig_tlv, -9600, 100, 1);
static DECLARE_TLV_DB_SCALE(pga_preamp_tlv, 0, 10000, 0);
static const char * const input1_sel_text[] = {
"DMIC1 On AB In",
"DMIC1 On A In",
"DMIC1 On B In",
"ADC1 On AB In",
"ADC1 On A In",
"ADC1 On B In",
"DMIC1 Off ADC1 Off",
};
static unsigned int const input1_sel_values[] = {
CS53L30_CH_TYPE,
CS53L30_ADCxB_PDN | CS53L30_CH_TYPE,
CS53L30_ADCxA_PDN | CS53L30_CH_TYPE,
CS53L30_DMICx_PDN,
CS53L30_ADCxB_PDN | CS53L30_DMICx_PDN,
CS53L30_ADCxA_PDN | CS53L30_DMICx_PDN,
CS53L30_ADCxA_PDN | CS53L30_ADCxB_PDN | CS53L30_DMICx_PDN,
};
static const char * const input2_sel_text[] = {
"DMIC2 On AB In",
"DMIC2 On A In",
"DMIC2 On B In",
"ADC2 On AB In",
"ADC2 On A In",
"ADC2 On B In",
"DMIC2 Off ADC2 Off",
};
static unsigned int const input2_sel_values[] = {
0x0,
CS53L30_ADCxB_PDN,
CS53L30_ADCxA_PDN,
CS53L30_DMICx_PDN,
CS53L30_ADCxB_PDN | CS53L30_DMICx_PDN,
CS53L30_ADCxA_PDN | CS53L30_DMICx_PDN,
CS53L30_ADCxA_PDN | CS53L30_ADCxB_PDN | CS53L30_DMICx_PDN,
};
static const char * const input1_route_sel_text[] = {
"ADC1_SEL", "DMIC1_SEL",
};
static const struct soc_enum input1_route_sel_enum =
SOC_ENUM_SINGLE(CS53L30_ADCDMIC1_CTL1, CS53L30_CH_TYPE_SHIFT,
ARRAY_SIZE(input1_route_sel_text),
input1_route_sel_text);
static SOC_VALUE_ENUM_SINGLE_DECL(input1_sel_enum, CS53L30_ADCDMIC1_CTL1, 0,
CS53L30_ADCDMICx_PDN_MASK, input1_sel_text,
input1_sel_values);
static const struct snd_kcontrol_new input1_route_sel_mux =
SOC_DAPM_ENUM("Input 1 Route", input1_route_sel_enum);
static const char * const input2_route_sel_text[] = {
"ADC2_SEL", "DMIC2_SEL",
};
/* Note: CS53L30_ADCDMIC1_CTL1 CH_TYPE controls inputs 1 and 2 */
static const struct soc_enum input2_route_sel_enum =
SOC_ENUM_SINGLE(CS53L30_ADCDMIC1_CTL1, 0,
ARRAY_SIZE(input2_route_sel_text),
input2_route_sel_text);
static SOC_VALUE_ENUM_SINGLE_DECL(input2_sel_enum, CS53L30_ADCDMIC2_CTL1, 0,
CS53L30_ADCDMICx_PDN_MASK, input2_sel_text,
input2_sel_values);
static const struct snd_kcontrol_new input2_route_sel_mux =
SOC_DAPM_ENUM("Input 2 Route", input2_route_sel_enum);
/*
* TB = 6144*(MCLK(int) scaling factor)/MCLK(internal)
* TB - Time base
* NOTE: If MCLK_INT_SCALE = 0, then TB=1
*/
static const char * const cs53l30_ng_delay_text[] = {
"TB*50ms", "TB*100ms", "TB*150ms", "TB*200ms",
};
static const struct soc_enum adc1_ng_delay_enum =
SOC_ENUM_SINGLE(CS53L30_ADC1_NG_CTL, CS53L30_ADCx_NG_DELAY_SHIFT,
ARRAY_SIZE(cs53l30_ng_delay_text),
cs53l30_ng_delay_text);
static const struct soc_enum adc2_ng_delay_enum =
SOC_ENUM_SINGLE(CS53L30_ADC2_NG_CTL, CS53L30_ADCx_NG_DELAY_SHIFT,
ARRAY_SIZE(cs53l30_ng_delay_text),
cs53l30_ng_delay_text);
/* The noise gate threshold selected will depend on NG Boost */
static const char * const cs53l30_ng_thres_text[] = {
"-64dB/-34dB", "-66dB/-36dB", "-70dB/-40dB", "-73dB/-43dB",
"-76dB/-46dB", "-82dB/-52dB", "-58dB", "-64dB",
};
static const struct soc_enum adc1_ng_thres_enum =
SOC_ENUM_SINGLE(CS53L30_ADC1_NG_CTL, CS53L30_ADCx_NG_THRESH_SHIFT,
ARRAY_SIZE(cs53l30_ng_thres_text),
cs53l30_ng_thres_text);
static const struct soc_enum adc2_ng_thres_enum =
SOC_ENUM_SINGLE(CS53L30_ADC2_NG_CTL, CS53L30_ADCx_NG_THRESH_SHIFT,
ARRAY_SIZE(cs53l30_ng_thres_text),
cs53l30_ng_thres_text);
/* Corner frequencies are with an Fs of 48kHz. */
static const char * const hpf_corner_freq_text[] = {
"1.86Hz", "120Hz", "235Hz", "466Hz",
};
static const struct soc_enum adc1_hpf_enum =
SOC_ENUM_SINGLE(CS53L30_ADC1_CTL3, CS53L30_ADCx_HPF_CF_SHIFT,
ARRAY_SIZE(hpf_corner_freq_text), hpf_corner_freq_text);
static const struct soc_enum adc2_hpf_enum =
SOC_ENUM_SINGLE(CS53L30_ADC2_CTL3, CS53L30_ADCx_HPF_CF_SHIFT,
ARRAY_SIZE(hpf_corner_freq_text), hpf_corner_freq_text);
static const struct snd_kcontrol_new cs53l30_snd_controls[] = {
SOC_SINGLE("Digital Soft-Ramp Switch", CS53L30_SFT_RAMP,
CS53L30_DIGSFT_SHIFT, 1, 0),
SOC_SINGLE("ADC1 Noise Gate Ganging Switch", CS53L30_ADC1_CTL3,
CS53L30_ADCx_NG_ALL_SHIFT, 1, 0),
SOC_SINGLE("ADC2 Noise Gate Ganging Switch", CS53L30_ADC2_CTL3,
CS53L30_ADCx_NG_ALL_SHIFT, 1, 0),
SOC_SINGLE("ADC1A Noise Gate Enable Switch", CS53L30_ADC1_NG_CTL,
CS53L30_ADCxA_NG_SHIFT, 1, 0),
SOC_SINGLE("ADC1B Noise Gate Enable Switch", CS53L30_ADC1_NG_CTL,
CS53L30_ADCxB_NG_SHIFT, 1, 0),
SOC_SINGLE("ADC2A Noise Gate Enable Switch", CS53L30_ADC2_NG_CTL,
CS53L30_ADCxA_NG_SHIFT, 1, 0),
SOC_SINGLE("ADC2B Noise Gate Enable Switch", CS53L30_ADC2_NG_CTL,
CS53L30_ADCxB_NG_SHIFT, 1, 0),
SOC_SINGLE("ADC1 Notch Filter Switch", CS53L30_ADCDMIC1_CTL2,
CS53L30_ADCx_NOTCH_DIS_SHIFT, 1, 1),
SOC_SINGLE("ADC2 Notch Filter Switch", CS53L30_ADCDMIC2_CTL2,
CS53L30_ADCx_NOTCH_DIS_SHIFT, 1, 1),
SOC_SINGLE("ADC1A Invert Switch", CS53L30_ADCDMIC1_CTL2,
CS53L30_ADCxA_INV_SHIFT, 1, 0),
SOC_SINGLE("ADC1B Invert Switch", CS53L30_ADCDMIC1_CTL2,
CS53L30_ADCxB_INV_SHIFT, 1, 0),
SOC_SINGLE("ADC2A Invert Switch", CS53L30_ADCDMIC2_CTL2,
CS53L30_ADCxA_INV_SHIFT, 1, 0),
SOC_SINGLE("ADC2B Invert Switch", CS53L30_ADCDMIC2_CTL2,
CS53L30_ADCxB_INV_SHIFT, 1, 0),
SOC_SINGLE_TLV("ADC1A Digital Boost Volume", CS53L30_ADCDMIC1_CTL2,
CS53L30_ADCxA_DIG_BOOST_SHIFT, 1, 0, adc_boost_tlv),
SOC_SINGLE_TLV("ADC1B Digital Boost Volume", CS53L30_ADCDMIC1_CTL2,
CS53L30_ADCxB_DIG_BOOST_SHIFT, 1, 0, adc_boost_tlv),
SOC_SINGLE_TLV("ADC2A Digital Boost Volume", CS53L30_ADCDMIC2_CTL2,
CS53L30_ADCxA_DIG_BOOST_SHIFT, 1, 0, adc_boost_tlv),
SOC_SINGLE_TLV("ADC2B Digital Boost Volume", CS53L30_ADCDMIC2_CTL2,
CS53L30_ADCxB_DIG_BOOST_SHIFT, 1, 0, adc_boost_tlv),
SOC_SINGLE_TLV("ADC1 NG Boost Volume", CS53L30_ADC1_NG_CTL,
CS53L30_ADCx_NG_BOOST_SHIFT, 1, 0, adc_ng_boost_tlv),
SOC_SINGLE_TLV("ADC2 NG Boost Volume", CS53L30_ADC2_NG_CTL,
CS53L30_ADCx_NG_BOOST_SHIFT, 1, 0, adc_ng_boost_tlv),
SOC_DOUBLE_R_TLV("ADC1 Preamplifier Volume", CS53L30_ADC1A_AFE_CTL,
CS53L30_ADC1B_AFE_CTL, CS53L30_ADCxy_PREAMP_SHIFT,
2, 0, pga_preamp_tlv),
SOC_DOUBLE_R_TLV("ADC2 Preamplifier Volume", CS53L30_ADC2A_AFE_CTL,
CS53L30_ADC2B_AFE_CTL, CS53L30_ADCxy_PREAMP_SHIFT,
2, 0, pga_preamp_tlv),
SOC_ENUM("Input 1 Channel Select", input1_sel_enum),
SOC_ENUM("Input 2 Channel Select", input2_sel_enum),
SOC_ENUM("ADC1 HPF Select", adc1_hpf_enum),
SOC_ENUM("ADC2 HPF Select", adc2_hpf_enum),
SOC_ENUM("ADC1 NG Threshold", adc1_ng_thres_enum),
SOC_ENUM("ADC2 NG Threshold", adc2_ng_thres_enum),
SOC_ENUM("ADC1 NG Delay", adc1_ng_delay_enum),
SOC_ENUM("ADC2 NG Delay", adc2_ng_delay_enum),
SOC_SINGLE_SX_TLV("ADC1A PGA Volume",
CS53L30_ADC1A_AFE_CTL, 0, 0x34, 0x24, pga_tlv),
SOC_SINGLE_SX_TLV("ADC1B PGA Volume",
CS53L30_ADC1B_AFE_CTL, 0, 0x34, 0x24, pga_tlv),
SOC_SINGLE_SX_TLV("ADC2A PGA Volume",
CS53L30_ADC2A_AFE_CTL, 0, 0x34, 0x24, pga_tlv),
SOC_SINGLE_SX_TLV("ADC2B PGA Volume",
CS53L30_ADC2B_AFE_CTL, 0, 0x34, 0x24, pga_tlv),
SOC_SINGLE_SX_TLV("ADC1A Digital Volume",
CS53L30_ADC1A_DIG_VOL, 0, 0xA0, 0x6C, dig_tlv),
SOC_SINGLE_SX_TLV("ADC1B Digital Volume",
CS53L30_ADC1B_DIG_VOL, 0, 0xA0, 0x6C, dig_tlv),
SOC_SINGLE_SX_TLV("ADC2A Digital Volume",
CS53L30_ADC2A_DIG_VOL, 0, 0xA0, 0x6C, dig_tlv),
SOC_SINGLE_SX_TLV("ADC2B Digital Volume",
CS53L30_ADC2B_DIG_VOL, 0, 0xA0, 0x6C, dig_tlv),
};
static const struct snd_soc_dapm_widget cs53l30_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("IN1_DMIC1"),
SND_SOC_DAPM_INPUT("IN2"),
SND_SOC_DAPM_INPUT("IN3_DMIC2"),
SND_SOC_DAPM_INPUT("IN4"),
SND_SOC_DAPM_SUPPLY("MIC1 Bias", CS53L30_MICBIAS_CTL,
CS53L30_MIC1_BIAS_PDN_SHIFT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("MIC2 Bias", CS53L30_MICBIAS_CTL,
CS53L30_MIC2_BIAS_PDN_SHIFT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("MIC3 Bias", CS53L30_MICBIAS_CTL,
CS53L30_MIC3_BIAS_PDN_SHIFT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("MIC4 Bias", CS53L30_MICBIAS_CTL,
CS53L30_MIC4_BIAS_PDN_SHIFT, 1, NULL, 0),
SND_SOC_DAPM_AIF_OUT("ASP_SDOUT1", NULL, 0, CS53L30_ASP_CTL1,
CS53L30_ASP_SDOUTx_PDN_SHIFT, 1),
SND_SOC_DAPM_AIF_OUT("ASP_SDOUT2", NULL, 0, CS53L30_ASP_CTL2,
CS53L30_ASP_SDOUTx_PDN_SHIFT, 1),
SND_SOC_DAPM_MUX("Input Mux 1", SND_SOC_NOPM, 0, 0,
&input1_route_sel_mux),
SND_SOC_DAPM_MUX("Input Mux 2", SND_SOC_NOPM, 0, 0,
&input2_route_sel_mux),
SND_SOC_DAPM_ADC("ADC1A", NULL, CS53L30_ADCDMIC1_CTL1,
CS53L30_ADCxA_PDN_SHIFT, 1),
SND_SOC_DAPM_ADC("ADC1B", NULL, CS53L30_ADCDMIC1_CTL1,
CS53L30_ADCxB_PDN_SHIFT, 1),
SND_SOC_DAPM_ADC("ADC2A", NULL, CS53L30_ADCDMIC2_CTL1,
CS53L30_ADCxA_PDN_SHIFT, 1),
SND_SOC_DAPM_ADC("ADC2B", NULL, CS53L30_ADCDMIC2_CTL1,
CS53L30_ADCxB_PDN_SHIFT, 1),
SND_SOC_DAPM_ADC("DMIC1", NULL, CS53L30_ADCDMIC1_CTL1,
CS53L30_DMICx_PDN_SHIFT, 1),
SND_SOC_DAPM_ADC("DMIC2", NULL, CS53L30_ADCDMIC2_CTL1,
CS53L30_DMICx_PDN_SHIFT, 1),
};
static const struct snd_soc_dapm_route cs53l30_dapm_routes[] = {
/* ADC Input Paths */
{"ADC1A", NULL, "IN1_DMIC1"},
{"Input Mux 1", "ADC1_SEL", "ADC1A"},
{"ADC1B", NULL, "IN2"},
{"ADC2A", NULL, "IN3_DMIC2"},
{"Input Mux 2", "ADC2_SEL", "ADC2A"},
{"ADC2B", NULL, "IN4"},
/* MIC Bias Paths */
{"ADC1A", NULL, "MIC1 Bias"},
{"ADC1B", NULL, "MIC2 Bias"},
{"ADC2A", NULL, "MIC3 Bias"},
{"ADC2B", NULL, "MIC4 Bias"},
/* DMIC Paths */
{"DMIC1", NULL, "IN1_DMIC1"},
{"Input Mux 1", "DMIC1_SEL", "DMIC1"},
{"DMIC2", NULL, "IN3_DMIC2"},
{"Input Mux 2", "DMIC2_SEL", "DMIC2"},
};
static const struct snd_soc_dapm_route cs53l30_dapm_routes_sdout1[] = {
/* Output Paths when using SDOUT1 only */
{"ASP_SDOUT1", NULL, "ADC1A" },
{"ASP_SDOUT1", NULL, "Input Mux 1"},
{"ASP_SDOUT1", NULL, "ADC1B"},
{"ASP_SDOUT1", NULL, "ADC2A"},
{"ASP_SDOUT1", NULL, "Input Mux 2"},
{"ASP_SDOUT1", NULL, "ADC2B"},
{"Capture", NULL, "ASP_SDOUT1"},
};
static const struct snd_soc_dapm_route cs53l30_dapm_routes_sdout2[] = {
/* Output Paths when using both SDOUT1 and SDOUT2 */
{"ASP_SDOUT1", NULL, "ADC1A" },
{"ASP_SDOUT1", NULL, "Input Mux 1"},
{"ASP_SDOUT1", NULL, "ADC1B"},
{"ASP_SDOUT2", NULL, "ADC2A"},
{"ASP_SDOUT2", NULL, "Input Mux 2"},
{"ASP_SDOUT2", NULL, "ADC2B"},
{"Capture", NULL, "ASP_SDOUT1"},
{"Capture", NULL, "ASP_SDOUT2"},
};
struct cs53l30_mclk_div {
u32 mclk_rate;
u32 srate;
u8 asp_rate;
u8 internal_fs_ratio;
u8 mclk_int_scale;
};
static const struct cs53l30_mclk_div cs53l30_mclk_coeffs[] = {
/* NOTE: Enable MCLK_INT_SCALE to save power. */
/* MCLK, Sample Rate, asp_rate, internal_fs_ratio, mclk_int_scale */
{5644800, 11025, 0x4, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{5644800, 22050, 0x8, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{5644800, 44100, 0xC, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6000000, 8000, 0x1, 0, CS53L30_MCLK_INT_SCALE},
{6000000, 11025, 0x2, 0, CS53L30_MCLK_INT_SCALE},
{6000000, 12000, 0x4, 0, CS53L30_MCLK_INT_SCALE},
{6000000, 16000, 0x5, 0, CS53L30_MCLK_INT_SCALE},
{6000000, 22050, 0x6, 0, CS53L30_MCLK_INT_SCALE},
{6000000, 24000, 0x8, 0, CS53L30_MCLK_INT_SCALE},
{6000000, 32000, 0x9, 0, CS53L30_MCLK_INT_SCALE},
{6000000, 44100, 0xA, 0, CS53L30_MCLK_INT_SCALE},
{6000000, 48000, 0xC, 0, CS53L30_MCLK_INT_SCALE},
{6144000, 8000, 0x1, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6144000, 11025, 0x2, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6144000, 12000, 0x4, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6144000, 16000, 0x5, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6144000, 22050, 0x6, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6144000, 24000, 0x8, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6144000, 32000, 0x9, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6144000, 44100, 0xA, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6144000, 48000, 0xC, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6400000, 8000, 0x1, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6400000, 11025, 0x2, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6400000, 12000, 0x4, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6400000, 16000, 0x5, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6400000, 22050, 0x6, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6400000, 24000, 0x8, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6400000, 32000, 0x9, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6400000, 44100, 0xA, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6400000, 48000, 0xC, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
};
struct cs53l30_mclkx_div {
u32 mclkx;
u8 ratio;
u8 mclkdiv;
};
static const struct cs53l30_mclkx_div cs53l30_mclkx_coeffs[] = {
{5644800, 1, CS53L30_MCLK_DIV_BY_1},
{6000000, 1, CS53L30_MCLK_DIV_BY_1},
{6144000, 1, CS53L30_MCLK_DIV_BY_1},
{11289600, 2, CS53L30_MCLK_DIV_BY_2},
{12288000, 2, CS53L30_MCLK_DIV_BY_2},
{12000000, 2, CS53L30_MCLK_DIV_BY_2},
{19200000, 3, CS53L30_MCLK_DIV_BY_3},
};
static int cs53l30_get_mclkx_coeff(int mclkx)
{
int i;
for (i = 0; i < ARRAY_SIZE(cs53l30_mclkx_coeffs); i++) {
if (cs53l30_mclkx_coeffs[i].mclkx == mclkx)
return i;
}
return -EINVAL;
}
static int cs53l30_get_mclk_coeff(int mclk_rate, int srate)
{
int i;
for (i = 0; i < ARRAY_SIZE(cs53l30_mclk_coeffs); i++) {
if (cs53l30_mclk_coeffs[i].mclk_rate == mclk_rate &&
cs53l30_mclk_coeffs[i].srate == srate)
return i;
}
return -EINVAL;
}
static int cs53l30_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct cs53l30_private *priv = snd_soc_component_get_drvdata(dai->component);
int mclkx_coeff;
u32 mclk_rate;
/* MCLKX -> MCLK */
mclkx_coeff = cs53l30_get_mclkx_coeff(freq);
if (mclkx_coeff < 0)
return mclkx_coeff;
mclk_rate = cs53l30_mclkx_coeffs[mclkx_coeff].mclkx /
cs53l30_mclkx_coeffs[mclkx_coeff].ratio;
regmap_update_bits(priv->regmap, CS53L30_MCLKCTL,
CS53L30_MCLK_DIV_MASK,
cs53l30_mclkx_coeffs[mclkx_coeff].mclkdiv);
priv->mclk_rate = mclk_rate;
return 0;
}
static int cs53l30_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct cs53l30_private *priv = snd_soc_component_get_drvdata(dai->component);
u8 aspcfg = 0, aspctl1 = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
aspcfg |= CS53L30_ASP_MS;
break;
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
/* DAI mode */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
/* Set TDM_PDN to turn off TDM mode -- Reset default */
aspctl1 |= CS53L30_ASP_TDM_PDN;
break;
case SND_SOC_DAIFMT_DSP_A:
/*
* Clear TDM_PDN to turn on TDM mode; Use ASP_SCLK_INV = 0
* with SHIFT_LEFT = 1 combination as Figure 4-13 shows in
* the CS53L30 datasheet
*/
aspctl1 |= CS53L30_SHIFT_LEFT;
break;
default:
return -EINVAL;
}
/* Check to see if the SCLK is inverted */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_IB_NF:
case SND_SOC_DAIFMT_IB_IF:
aspcfg ^= CS53L30_ASP_SCLK_INV;
break;
default:
break;
}
regmap_update_bits(priv->regmap, CS53L30_ASPCFG_CTL,
CS53L30_ASP_MS | CS53L30_ASP_SCLK_INV, aspcfg);
regmap_update_bits(priv->regmap, CS53L30_ASP_CTL1,
CS53L30_ASP_TDM_PDN | CS53L30_SHIFT_LEFT, aspctl1);
return 0;
}
static int cs53l30_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct cs53l30_private *priv = snd_soc_component_get_drvdata(dai->component);
int srate = params_rate(params);
int mclk_coeff;
/* MCLK -> srate */
mclk_coeff = cs53l30_get_mclk_coeff(priv->mclk_rate, srate);
if (mclk_coeff < 0)
return -EINVAL;
regmap_update_bits(priv->regmap, CS53L30_INT_SR_CTL,
CS53L30_INTRNL_FS_RATIO_MASK,
cs53l30_mclk_coeffs[mclk_coeff].internal_fs_ratio);
regmap_update_bits(priv->regmap, CS53L30_MCLKCTL,
CS53L30_MCLK_INT_SCALE_MASK,
cs53l30_mclk_coeffs[mclk_coeff].mclk_int_scale);
regmap_update_bits(priv->regmap, CS53L30_ASPCFG_CTL,
CS53L30_ASP_RATE_MASK,
cs53l30_mclk_coeffs[mclk_coeff].asp_rate);
return 0;
}
static int cs53l30_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct cs53l30_private *priv = snd_soc_component_get_drvdata(component);
unsigned int reg;
int i, inter_max_check, ret;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
if (dapm->bias_level == SND_SOC_BIAS_STANDBY)
regmap_update_bits(priv->regmap, CS53L30_PWRCTL,
CS53L30_PDN_LP_MASK, 0);
break;
case SND_SOC_BIAS_STANDBY:
if (dapm->bias_level == SND_SOC_BIAS_OFF) {
ret = clk_prepare_enable(priv->mclk);
if (ret) {
dev_err(component->dev,
"failed to enable MCLK: %d\n", ret);
return ret;
}
regmap_update_bits(priv->regmap, CS53L30_MCLKCTL,
CS53L30_MCLK_DIS_MASK, 0);
regmap_update_bits(priv->regmap, CS53L30_PWRCTL,
CS53L30_PDN_ULP_MASK, 0);
msleep(50);
} else {
regmap_update_bits(priv->regmap, CS53L30_PWRCTL,
CS53L30_PDN_ULP_MASK,
CS53L30_PDN_ULP);
}
break;
case SND_SOC_BIAS_OFF:
regmap_update_bits(priv->regmap, CS53L30_INT_MASK,
CS53L30_PDN_DONE, 0);
/*
* If digital softramp is set, the amount of time required
* for power down increases and depends on the digital
* volume setting.
*/
/* Set the max possible time if digsft is set */
regmap_read(priv->regmap, CS53L30_SFT_RAMP, ®);
if (reg & CS53L30_DIGSFT_MASK)
inter_max_check = CS53L30_PDN_POLL_MAX;
else
inter_max_check = 10;
regmap_update_bits(priv->regmap, CS53L30_PWRCTL,
CS53L30_PDN_ULP_MASK,
CS53L30_PDN_ULP);
/* PDN_DONE will take a min of 20ms to be set.*/
msleep(20);
/* Clr status */
regmap_read(priv->regmap, CS53L30_IS, ®);
for (i = 0; i < inter_max_check; i++) {
if (inter_max_check < 10) {
usleep_range(1000, 1100);
regmap_read(priv->regmap, CS53L30_IS, ®);
if (reg & CS53L30_PDN_DONE)
break;
} else {
usleep_range(10000, 10100);
regmap_read(priv->regmap, CS53L30_IS, ®);
if (reg & CS53L30_PDN_DONE)
break;
}
}
/* PDN_DONE is set. We now can disable the MCLK */
regmap_update_bits(priv->regmap, CS53L30_INT_MASK,
CS53L30_PDN_DONE, CS53L30_PDN_DONE);
regmap_update_bits(priv->regmap, CS53L30_MCLKCTL,
CS53L30_MCLK_DIS_MASK,
CS53L30_MCLK_DIS);
clk_disable_unprepare(priv->mclk);
break;
}
return 0;
}
static int cs53l30_set_tristate(struct snd_soc_dai *dai, int tristate)
{
struct cs53l30_private *priv = snd_soc_component_get_drvdata(dai->component);
u8 val = tristate ? CS53L30_ASP_3ST : 0;
return regmap_update_bits(priv->regmap, CS53L30_ASP_CTL1,
CS53L30_ASP_3ST_MASK, val);
}
static unsigned int const cs53l30_src_rates[] = {
8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000
};
static const struct snd_pcm_hw_constraint_list src_constraints = {
.count = ARRAY_SIZE(cs53l30_src_rates),
.list = cs53l30_src_rates,
};
static int cs53l30_pcm_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE, &src_constraints);
return 0;
}
/*
* Note: CS53L30 counts the slot number per byte while ASoC counts the slot
* number per slot_width. So there is a difference between the slots of ASoC
* and the slots of CS53L30.
*/
static int cs53l30_set_dai_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask,
int slots, int slot_width)
{
struct cs53l30_private *priv = snd_soc_component_get_drvdata(dai->component);
unsigned int loc[CS53L30_TDM_SLOT_MAX] = {48, 48, 48, 48};
unsigned int slot_next, slot_step;
u64 tx_enable = 0;
int i;
if (!rx_mask) {
dev_err(dai->dev, "rx masks must not be 0\n");
return -EINVAL;
}
/* Assuming slot_width is not supposed to be greater than 64 */
if (slots <= 0 || slot_width <= 0 || slot_width > 64) {
dev_err(dai->dev, "invalid slot number or slot width\n");
return -EINVAL;
}
if (slot_width & 0x7) {
dev_err(dai->dev, "slot width must count in byte\n");
return -EINVAL;
}
/* How many bytes in each ASoC slot */
slot_step = slot_width >> 3;
for (i = 0; rx_mask && i < CS53L30_TDM_SLOT_MAX; i++) {
/* Find the first slot from LSB */
slot_next = __ffs(rx_mask);
/* Save the slot location by converting to CS53L30 slot */
loc[i] = slot_next * slot_step;
/* Create the mask of CS53L30 slot */
tx_enable |= (u64)((u64)(1 << slot_step) - 1) << (u64)loc[i];
/* Clear this slot from rx_mask */
rx_mask &= ~(1 << slot_next);
}
/* Error out to avoid slot shift */
if (rx_mask && i == CS53L30_TDM_SLOT_MAX) {
dev_err(dai->dev, "rx_mask exceeds max slot number: %d\n",
CS53L30_TDM_SLOT_MAX);
return -EINVAL;
}
/* Validate the last active CS53L30 slot */
slot_next = loc[i - 1] + slot_step - 1;
if (slot_next > 47) {
dev_err(dai->dev, "slot selection out of bounds: %u\n",
slot_next);
return -EINVAL;
}
for (i = 0; i < CS53L30_TDM_SLOT_MAX && loc[i] != 48; i++) {
regmap_update_bits(priv->regmap, CS53L30_ASP_TDMTX_CTL(i),
CS53L30_ASP_CHx_TX_LOC_MASK, loc[i]);
dev_dbg(dai->dev, "loc[%d]=%x\n", i, loc[i]);
}
for (i = 0; i < CS53L30_ASP_TDMTX_ENx_MAX && tx_enable; i++) {
regmap_write(priv->regmap, CS53L30_ASP_TDMTX_ENx(i),
tx_enable & 0xff);
tx_enable >>= 8;
dev_dbg(dai->dev, "en_reg=%x, tx_enable=%llx\n",
CS53L30_ASP_TDMTX_ENx(i), tx_enable & 0xff);
}
return 0;
}
static int cs53l30_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
{
struct cs53l30_private *priv = snd_soc_component_get_drvdata(dai->component);
gpiod_set_value_cansleep(priv->mute_gpio, mute);
return 0;
}
/* SNDRV_PCM_RATE_KNOT -> 12000, 24000 Hz, limit with constraint list */
#define CS53L30_RATES (SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_KNOT)
#define CS53L30_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE)
static const struct snd_soc_dai_ops cs53l30_ops = {
.startup = cs53l30_pcm_startup,
.hw_params = cs53l30_pcm_hw_params,
.set_fmt = cs53l30_set_dai_fmt,
.set_sysclk = cs53l30_set_sysclk,
.set_tristate = cs53l30_set_tristate,
.set_tdm_slot = cs53l30_set_dai_tdm_slot,
.mute_stream = cs53l30_mute_stream,
};
static struct snd_soc_dai_driver cs53l30_dai = {
.name = "cs53l30",
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 4,
.rates = CS53L30_RATES,
.formats = CS53L30_FORMATS,
},
.ops = &cs53l30_ops,
.symmetric_rate = 1,
};
static int cs53l30_component_probe(struct snd_soc_component *component)
{
struct cs53l30_private *priv = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
if (priv->use_sdout2)
snd_soc_dapm_add_routes(dapm, cs53l30_dapm_routes_sdout2,
ARRAY_SIZE(cs53l30_dapm_routes_sdout2));
else
snd_soc_dapm_add_routes(dapm, cs53l30_dapm_routes_sdout1,
ARRAY_SIZE(cs53l30_dapm_routes_sdout1));
return 0;
}
static const struct snd_soc_component_driver cs53l30_driver = {
.probe = cs53l30_component_probe,
.set_bias_level = cs53l30_set_bias_level,
.controls = cs53l30_snd_controls,
.num_controls = ARRAY_SIZE(cs53l30_snd_controls),
.dapm_widgets = cs53l30_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(cs53l30_dapm_widgets),
.dapm_routes = cs53l30_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(cs53l30_dapm_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
static struct regmap_config cs53l30_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = CS53L30_MAX_REGISTER,
.reg_defaults = cs53l30_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(cs53l30_reg_defaults),
.volatile_reg = cs53l30_volatile_register,
.writeable_reg = cs53l30_writeable_register,
.readable_reg = cs53l30_readable_register,
.cache_type = REGCACHE_MAPLE,
.use_single_read = true,
.use_single_write = true,
};
static int cs53l30_i2c_probe(struct i2c_client *client)
{
const struct device_node *np = client->dev.of_node;
struct device *dev = &client->dev;
struct cs53l30_private *cs53l30;
unsigned int reg;
int ret = 0, i, devid;
u8 val;
cs53l30 = devm_kzalloc(dev, sizeof(*cs53l30), GFP_KERNEL);
if (!cs53l30)
return -ENOMEM;
for (i = 0; i < ARRAY_SIZE(cs53l30->supplies); i++)
cs53l30->supplies[i].supply = cs53l30_supply_names[i];
ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(cs53l30->supplies),
cs53l30->supplies);
if (ret) {
dev_err(dev, "failed to get supplies: %d\n", ret);
return ret;
}
ret = regulator_bulk_enable(ARRAY_SIZE(cs53l30->supplies),
cs53l30->supplies);
if (ret) {
dev_err(dev, "failed to enable supplies: %d\n", ret);
return ret;
}
/* Reset the Device */
cs53l30->reset_gpio = devm_gpiod_get_optional(dev, "reset",
GPIOD_OUT_LOW);
if (IS_ERR(cs53l30->reset_gpio)) {
ret = PTR_ERR(cs53l30->reset_gpio);
goto error_supplies;
}
gpiod_set_value_cansleep(cs53l30->reset_gpio, 1);
i2c_set_clientdata(client, cs53l30);
cs53l30->mclk_rate = 0;
cs53l30->regmap = devm_regmap_init_i2c(client, &cs53l30_regmap);
if (IS_ERR(cs53l30->regmap)) {
ret = PTR_ERR(cs53l30->regmap);
dev_err(dev, "regmap_init() failed: %d\n", ret);
goto error;
}
/* Initialize codec */
devid = cirrus_read_device_id(cs53l30->regmap, CS53L30_DEVID_AB);
if (devid < 0) {
ret = devid;
dev_err(dev, "Failed to read device ID: %d\n", ret);
goto error;
}
if (devid != CS53L30_DEVID) {
ret = -ENODEV;
dev_err(dev, "Device ID (%X). Expected %X\n",
devid, CS53L30_DEVID);
goto error;
}
ret = regmap_read(cs53l30->regmap, CS53L30_REVID, ®);
if (ret < 0) {
dev_err(dev, "failed to get Revision ID: %d\n", ret);
goto error;
}
/* Check if MCLK provided */
cs53l30->mclk = devm_clk_get_optional(dev, "mclk");
if (IS_ERR(cs53l30->mclk)) {
ret = PTR_ERR(cs53l30->mclk);
goto error;
}
/* Fetch the MUTE control */
cs53l30->mute_gpio = devm_gpiod_get_optional(dev, "mute",
GPIOD_OUT_HIGH);
if (IS_ERR(cs53l30->mute_gpio)) {
ret = PTR_ERR(cs53l30->mute_gpio);
goto error;
}
if (cs53l30->mute_gpio) {
/* Enable MUTE controls via MUTE pin */
regmap_write(cs53l30->regmap, CS53L30_MUTEP_CTL1,
CS53L30_MUTEP_CTL1_MUTEALL);
/* Flip the polarity of MUTE pin */
if (gpiod_is_active_low(cs53l30->mute_gpio))
regmap_update_bits(cs53l30->regmap, CS53L30_MUTEP_CTL2,
CS53L30_MUTE_PIN_POLARITY, 0);
}
if (!of_property_read_u8(np, "cirrus,micbias-lvl", &val))
regmap_update_bits(cs53l30->regmap, CS53L30_MICBIAS_CTL,
CS53L30_MIC_BIAS_CTRL_MASK, val);
if (of_property_read_bool(np, "cirrus,use-sdout2"))
cs53l30->use_sdout2 = true;
dev_info(dev, "Cirrus Logic CS53L30, Revision: %02X\n", reg & 0xFF);
ret = devm_snd_soc_register_component(dev, &cs53l30_driver, &cs53l30_dai, 1);
if (ret) {
dev_err(dev, "failed to register component: %d\n", ret);
goto error;
}
return 0;
error:
gpiod_set_value_cansleep(cs53l30->reset_gpio, 0);
error_supplies:
regulator_bulk_disable(ARRAY_SIZE(cs53l30->supplies),
cs53l30->supplies);
return ret;
}
static void cs53l30_i2c_remove(struct i2c_client *client)
{
struct cs53l30_private *cs53l30 = i2c_get_clientdata(client);
/* Hold down reset */
gpiod_set_value_cansleep(cs53l30->reset_gpio, 0);
regulator_bulk_disable(ARRAY_SIZE(cs53l30->supplies),
cs53l30->supplies);
}
#ifdef CONFIG_PM
static int cs53l30_runtime_suspend(struct device *dev)
{
struct cs53l30_private *cs53l30 = dev_get_drvdata(dev);
regcache_cache_only(cs53l30->regmap, true);
/* Hold down reset */
gpiod_set_value_cansleep(cs53l30->reset_gpio, 0);
regulator_bulk_disable(ARRAY_SIZE(cs53l30->supplies),
cs53l30->supplies);
return 0;
}
static int cs53l30_runtime_resume(struct device *dev)
{
struct cs53l30_private *cs53l30 = dev_get_drvdata(dev);
int ret;
ret = regulator_bulk_enable(ARRAY_SIZE(cs53l30->supplies),
cs53l30->supplies);
if (ret) {
dev_err(dev, "failed to enable supplies: %d\n", ret);
return ret;
}
gpiod_set_value_cansleep(cs53l30->reset_gpio, 1);
regcache_cache_only(cs53l30->regmap, false);
ret = regcache_sync(cs53l30->regmap);
if (ret) {
dev_err(dev, "failed to synchronize regcache: %d\n", ret);
return ret;
}
return 0;
}
#endif
static const struct dev_pm_ops cs53l30_runtime_pm = {
SET_RUNTIME_PM_OPS(cs53l30_runtime_suspend, cs53l30_runtime_resume,
NULL)
};
static const struct of_device_id cs53l30_of_match[] = {
{ .compatible = "cirrus,cs53l30", },
{},
};
MODULE_DEVICE_TABLE(of, cs53l30_of_match);
static const struct i2c_device_id cs53l30_id[] = {
{ "cs53l30", 0 },
{}
};
MODULE_DEVICE_TABLE(i2c, cs53l30_id);
static struct i2c_driver cs53l30_i2c_driver = {
.driver = {
.name = "cs53l30",
.of_match_table = cs53l30_of_match,
.pm = &cs53l30_runtime_pm,
},
.id_table = cs53l30_id,
.probe = cs53l30_i2c_probe,
.remove = cs53l30_i2c_remove,
};
module_i2c_driver(cs53l30_i2c_driver);
MODULE_DESCRIPTION("ASoC CS53L30 driver");
MODULE_AUTHOR("Paul Handrigan, Cirrus Logic Inc, <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cs53l30.c |
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